: +0x0002 ? 2400 eor r0,r0[0K +0x0003 ? c001 rjmp 0x000005 [0K +0x0004 ? 9403 inc r0[0K + +0x0005 : +0x0005 ? cfff rjmp 0x000005 [0K +Loading from [ELIDED] +6 words read from [ELIDED] diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/avr.src/test/symdis/Makefile sdcc-4.2.0+dfsg/sim/ucsim/avr.src/test/symdis/Makefile --- sdcc-4.0.0+dfsg/sim/ucsim/avr.src/test/symdis/Makefile 1970-01-01 00:00:00.000000000 +0000 +++ sdcc-4.2.0+dfsg/sim/ucsim/avr.src/test/symdis/Makefile 2021-05-07 16:21:16.000000000 +0000 @@ -0,0 +1,23 @@ +OUTPUTS = stdout + + +# Ignore changes in white space. The field widths for labels +# depends on the length of the longest label. This will be +# different for different simulators and should not be assumed +# to be constant for any given simulator. +DIFF_OPTS += -b + + +stdout: test.ihx test.cmd + $(call run-sim) + + +%.p: %.asm + asl -L -h -U -olist '$*.lst' -o '$@' '$<' + +%.ihx: %.p + p2hex -F Intel '$<' '$@' + + +include test-lib.mk + diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/avr.src/test/symdis/test.asm sdcc-4.2.0+dfsg/sim/ucsim/avr.src/test/symdis/test.asm --- sdcc-4.0.0+dfsg/sim/ucsim/avr.src/test/symdis/test.asm 1970-01-01 00:00:00.000000000 +0000 +++ sdcc-4.2.0+dfsg/sim/ucsim/avr.src/test/symdis/test.asm 2021-05-07 16:21:16.000000000 +0000 @@ -0,0 +1,9 @@ + cpu ATMEGA8 + +init: call main + +main: clr r0 + rjmp forever + inc r0 +forever: + rjmp forever diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/avr.src/test/symdis/test.cmd sdcc-4.2.0+dfsg/sim/ucsim/avr.src/test/symdis/test.cmd --- sdcc-4.0.0+dfsg/sim/ucsim/avr.src/test/symdis/test.cmd 1970-01-01 00:00:00.000000000 +0000 +++ sdcc-4.2.0+dfsg/sim/ucsim/avr.src/test/symdis/test.cmd 2021-05-07 16:21:16.000000000 +0000 @@ -0,0 +1,4 @@ +var init rom[0x0000] +var main rom[0x0002] +var forever rom[0x0005] +dc 0x0000 0x0005 diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/avr.src/test/symdis/test.ihx sdcc-4.2.0+dfsg/sim/ucsim/avr.src/test/symdis/test.ihx --- sdcc-4.0.0+dfsg/sim/ucsim/avr.src/test/symdis/test.ihx 1970-01-01 00:00:00.000000000 +0000 +++ sdcc-4.2.0+dfsg/sim/ucsim/avr.src/test/symdis/test.ihx 2021-05-07 16:21:16.000000000 +0000 @@ -0,0 +1,2 @@ +:0C0000000E940200002401C00394FFCF06 +:00000001FF diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/chars.cc sdcc-4.2.0+dfsg/sim/ucsim/chars.cc --- sdcc-4.0.0+dfsg/sim/ucsim/chars.cc 2019-02-26 14:40:39.000000000 +0000 +++ sdcc-4.2.0+dfsg/sim/ucsim/chars.cc 2022-01-24 11:09:43.000000000 +0000 @@ -25,10 +25,12 @@ 02111-1307, USA. */ /*@1@*/ +#include #include #include #include #include +#include #include "charscl.h" @@ -50,26 +52,18 @@ chars::chars(const char *s) { - if ((chars_string= (char*)s) != NULL) + if ((chars_string= const_cast(s)) != NULL) chars_length= strlen(s); else chars_length= 0; dynamic= false; pars_pos= 0; } -/* -chars::chars(const char *s) -{ - chars_string= 0; - chars_length= 0; - allocate_string((char*)s); -} -*/ chars::chars(const chars &cs) { chars_string= 0; chars_length= 0; - allocate_string((char*)cs); + allocate_string(cs); } chars::chars(const char *, const char *fmt, ...) @@ -94,7 +88,7 @@ void -chars::allocate_string(char *s) +chars::allocate_string(const char *s) { char *n= NULL; int l= 0; @@ -127,11 +121,11 @@ chars -chars::token(chars delims) +chars::token(const char *delims) const { chars c= (char*)NULL; - if (delims.len() < 1) + if (!delims || !*delims) return c; if (pars_pos >= chars_length) return c; @@ -140,12 +134,12 @@ int l; // skip initial delims first; - l= strspn(&chars_string[pars_pos], (char*)delims); + l= strspn(&chars_string[pars_pos], delims); pars_pos+= l; if (pars_pos >= chars_length) return c; // skip chars not in delims: search token end - l= strcspn(&chars_string[pars_pos], (char*)delims); + l= strcspn(&chars_string[pars_pos], delims); if (l > 0) { // found @@ -154,7 +148,7 @@ c+= chars_string[i]; pars_pos= i; // skip delims at end - l= strspn(&chars_string[pars_pos], (char*)delims); + l= strspn(&chars_string[pars_pos], delims); pars_pos+= l; return c; } @@ -163,8 +157,35 @@ } +void +chars::ltrim(void) +{ + char *p= chars_string; + if (!p) + return; + while (*p && isspace(*p)) + p++; + allocate_string(p); +} + +void +chars::rtrim(void) +{ + char *p= chars_string; + if (!p) + return; + if (*p == 0) + return; + p= p+len()-1; + while ((p!=chars_string) && isspace(*p)) + p--; + if (isspace(*p)) + *p= 0; +} + + bool -chars::starts_with(char *x) +chars::starts_with(const char *x) const { if (empty() || !x || @@ -175,21 +196,9 @@ return false; } -bool -chars::starts_with(const char *x) -{ - return starts_with((char*)x); -} - -bool -chars::starts_with(chars x) -{ - return starts_with((char*)x); -} - chars & -chars::append(char *s) +chars::append(const char *s) { if (!s) return(*this); @@ -238,7 +247,7 @@ } chars & -chars::append(const char *format, ...) +chars::appendf(const char *format, ...) { va_list ap; char n[1000]; @@ -293,21 +302,34 @@ return *this; } -bool -chars::empty() +chars & +chars::uppercase(void) { - return chars_length == 0; + if (!dynamic) + allocate_string(chars_string); + + for (int i= 0; i < chars_length; i++) + chars_string[i]= toupper(chars_string[i]); + + return *this; } -bool -chars::is_null() +chars & +chars::subst(const char *what, char with) { - return chars_string == NULL; + if (!dynamic) + allocate_string(chars_string); + + for (int i= 0; i < chars_length; i++) + if (strchr(what, chars_string[i])) + chars_string[i] = with; + + return *this; } // Assignment operators chars & -chars::operator=(char *s) +chars::operator=(const char *s) { allocate_string(s); return(*this); @@ -316,7 +338,8 @@ chars & chars::operator=(const chars &cs) { - allocate_string((char*)cs); + if (this != &cs) + allocate_string(cs.chars_string); return(*this); } @@ -324,7 +347,7 @@ // Arithmetic operators chars -chars::operator+(char c) +chars::operator+(char c) const { char b[2]; b[0]= c; @@ -334,40 +357,26 @@ } chars -chars::operator+(char *s) +chars::operator+(const char *s) const { chars temp(chars_string); return(temp.append(s)); } chars -chars::operator+(const chars &cs) -{ - chars temp(chars_string); - return(temp.append(cs)); -} - -chars operator+(char c, const chars &cs) { char b[2]; b[0]= c; b[1]= 0; chars temp(b); - return(temp.append((char*)cs)); -}; - -chars -operator+(char *s, const chars &cs) -{ - chars temp(s); - return(temp.append((char*)cs)); -}; + return(temp.append(cs)); +} // Boolean operators bool -chars::equal(char *s) +chars::equal(const char *s) const { if ((chars_string && !s) || @@ -381,95 +390,16 @@ } bool -chars::operator==(char *s) +chars::operator==(const char *s) const { return(equal(s)); } bool -chars::operator==(const char *s) -{ - return(equal((char*)s)); -} - -bool -chars::operator==(chars &cs) -{ - return(*this == (char*)cs); -} - -bool -operator==(char *s, const chars &cs) -{ - return((chars(cs)).equal(s)); -} - -bool -operator==(const char *s, const chars &cs) -{ - return((chars(cs)).equal((char*)s)); -} - -bool -chars::operator!=(char *s) +chars::operator!=(const char *s) const { return(!equal(s)); } -bool -chars::operator!=(const char *s) -{ - return(!equal((char*)s)); -} - -bool -chars::operator!=(chars &cs) -{ - return(*this != (char*)cs); -} - -bool -operator!=(char *s, const chars &cs) -{ - return(!(chars(cs)).equal(s)); -} - -bool -operator!=(const char *s, const chars &cs) -{ - return(!(chars(cs)).equal((char*)s)); -} - -/* -cchars::cchars(const char *s): -chars(s) -{ -} -*/ -/* -cchars::cchars(char const *s): -chars(s) -{ -} - -cchars::~cchars(void) -{ - deallocate_string(); -} - -void -cchars::allocate_string(const char *s) -{ - deallocate_string(); - allocate_string((char*)s); -} - -void -cchars::deallocate_string(void) -{ - chars_string= 0; - chars_length= 0; -} -*/ /* End of chars.cc */ diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/charscl.h sdcc-4.2.0+dfsg/sim/ucsim/charscl.h --- sdcc-4.0.0+dfsg/sim/ucsim/charscl.h 2019-03-22 11:23:06.000000000 +0000 +++ sdcc-4.2.0+dfsg/sim/ucsim/charscl.h 2022-01-24 11:09:43.000000000 +0000 @@ -35,7 +35,7 @@ char *chars_string; // stores the value int chars_length; // track of string length bool dynamic; - int pars_pos; + mutable int pars_pos; public: chars(void); chars(char *s); @@ -44,72 +44,51 @@ chars(const char *, const char *fmt, ...); virtual ~chars(void); private: - virtual void allocate_string(char *s); - virtual void deallocate_string(void); + void allocate_string(const char *s); + void deallocate_string(void); public: - virtual chars &append(char *s); - virtual chars &append(char c); - virtual chars &append(const char *format, ...); - virtual chars &format(const char *format, ...); - virtual bool empty(); - virtual bool nempty() { return !empty(); } - virtual bool is_null(); - virtual int len() { return chars_length; } - virtual void start_parse(void) { start_parse(0); } - virtual void start_parse(int at) { pars_pos= at; } - virtual chars token(chars delims); + const char *c_str(void) const { return chars_string; } + chars &append(const char *s); + chars &append(char c); + chars &appendf(const char *format, ...); + chars &format(const char *format, ...); + bool empty() const { return chars_length == 0; } + bool nempty() const { return !empty(); } + bool is_null()const { return !chars_string; } + chars &uppercase(void); + chars &subst(const char *what, char with); + int len() const { return chars_length; } + int length() const { return chars_length; } + void start_parse(void) const { start_parse(0); } + void start_parse(int at) const { pars_pos= at; } + chars token(const char *delims) const; + void ltrim(void); + void rtrim(void); + void trim() { ltrim(); rtrim(); } // search - bool starts_with(char *x); - bool starts_with(const char *x); - bool starts_with(chars x); + bool starts_with(const char *x) const; public: // Operators // Cast - operator char*(void) { return(chars_string); }; - operator char*(void) const { return(chars_string); }; + operator const char*(void) const { return(chars_string); }; // Assignment - chars &operator=(char *s); + chars &operator=(const char *s); chars &operator=(const chars &cs); // Arithmetic - chars operator+(char c); - chars operator+(char *s); - chars operator+(const chars &cs); + chars operator+(char c) const; + chars operator+(const char *s) const; chars &operator+=(char c) { return(append(c)); } - chars &operator+=(char *s) { return(append(s)); } - chars &operator+=(const chars &cs) { return(append((char*)cs)); } + chars &operator+=(const char *s) { return(append(s)); } // Boolean - bool equal(char *); - bool operator==(char *s); - bool operator==(const char *s); - bool operator==(chars &cs); - bool operator!=(char *s); - bool operator!=(const char *s); - bool operator!=(chars &cs); + bool equal(const char *) const; + bool operator==(const char *s) const; + bool operator!=(const char *s) const; }; extern chars operator+(char s, const chars &cs); -extern chars operator+(char *s, const chars &cs); -extern bool operator==(char *s, const chars &cs); -extern bool operator==(const char *s, const chars &cs); -extern bool operator!=(char *s, const chars &cs); -extern bool operator!=(const char *s, const chars &cs); - -/* -class cchars: public chars -{ - public: - //cchars(const char *s); - cchars(char const *s); - virtual ~cchars(void); - private: - virtual void allocate_string(const char *s); - virtual void deallocate_string(void); -}; -*/ -#define cchars chars #endif diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/clean.mk sdcc-4.2.0+dfsg/sim/ucsim/clean.mk --- sdcc-4.0.0+dfsg/sim/ucsim/clean.mk 2019-03-18 14:08:33.000000000 +0000 +++ sdcc-4.2.0+dfsg/sim/ucsim/clean.mk 2020-03-27 20:18:53.000000000 +0000 @@ -1,7 +1,8 @@ # Deleting all files created by building the program # -------------------------------------------------- clean: - rm -f *core *[%~] *.[oa] *.so ucsim$(EXEEXT) ucsim.map relay$(EXEEXT) + rm -f *core *[%~] *.[oa] *.so ucsim.map + rm -f ucsim$(EXEEXT) relay$(EXEEXT) ucsim.exe relay.exe rm -f .[a-z]*~ ptt diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/cmd.src/cmd_bp.cc sdcc-4.2.0+dfsg/sim/ucsim/cmd.src/cmd_bp.cc --- sdcc-4.0.0+dfsg/sim/ucsim/cmd.src/cmd_bp.cc 2019-04-02 10:46:33.000000000 +0000 +++ sdcc-4.2.0+dfsg/sim/ucsim/cmd.src/cmd_bp.cc 2021-05-02 15:29:48.000000000 +0000 @@ -26,14 +26,14 @@ /*@1@*/ #include +#include +#include -#include "ddconfig.h" - -#include "stdlib.h" +//#include "ddconfig.h" // sim -#include "brkcl.h" -#include "argcl.h" +//#include "brkcl.h" +//#include "argcl.h" #include "simcl.h" // cmd @@ -217,9 +217,9 @@ b->init(); b->cond= cond; uc->fbrk->add_bp(b); - const char *s= uc->disass(addr, NULL); - con->dd_printf("Breakpoint %d at 0x%06x: %s (cond=\"%s\")\n", b->nr, AI(addr), s, (char*)cond); - free((char *)s); + con->dd_printf("Breakpoint %d at 0x%06x: ", b->nr, AI(addr)); + uc->print_disass(addr, con, false); + con->dd_printf(" (cond=\"%s\")\n", cond.c_str()); } } @@ -342,9 +342,9 @@ } if (!s.empty()) { - if (isdigit(((char*)s)[0])) + if (isdigit((s.c_str())[0])) { - char *p0= (char*)s; + const char *p0= s; if (p0 && *p0) { long l=-2; diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/cmd.src/cmd_conf.cc sdcc-4.2.0+dfsg/sim/ucsim/cmd.src/cmd_conf.cc --- sdcc-4.0.0+dfsg/sim/ucsim/cmd.src/cmd_conf.cc 2019-03-22 11:23:06.000000000 +0000 +++ sdcc-4.2.0+dfsg/sim/ucsim/cmd.src/cmd_conf.cc 2022-02-03 14:06:06.000000000 +0000 @@ -27,10 +27,10 @@ // prj #include "globals.h" -#include "utils.h" +//#include "utils.h" // sim -#include "simcl.h" +//#include "simcl.h" // local #include "cmd_confcl.h" @@ -55,7 +55,8 @@ { int i; - con->dd_printf("ucsim version %s\n", VERSIONSTR); + if (!application->quiet) + con->dd_printf("ucsim version %s\n", VERSIONSTR); con->dd_printf("Type of microcontroller: %s", uc->id_string()); if (cpus && uc->type) @@ -127,6 +128,29 @@ "Show object tree", "long help of conf objects") + +/* + * Command: ver + *---------------------------------------------------------------------------- + */ + +COMMAND_DO_WORK_APP(cl_ver_cmd) +{ + con->dd_printf("%s\n", VERSIONSTR); + return false; +} + +CMDHELP(cl_ver_cmd, + "version", + "Version of the program", + "long help of ver command") + + +/* + * Command: jaj + *---------------------------------------------------------------------------- + */ + COMMAND_DO_WORK_APP(cl_jaj_cmd) { //class cl_address_space *mem= 0; @@ -134,13 +158,19 @@ cmdline->param(1), cmdline->param(2), cmdline->param(3) }; - + int i; + if (params[0] != NULL) { - int i= params[0]->i_value; + i= params[0]->i_value; jaj= i?true:false; } - con->dd_printf("%d\n", jaj); + if (params[1] != NULL) + { + i= params[1]->i_value; + juj= i; + } + con->dd_printf("%d %d\n", jaj, juj); return(false); } diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/cmd.src/cmd_confcl.h sdcc-4.2.0+dfsg/sim/ucsim/cmd.src/cmd_confcl.h --- sdcc-4.0.0+dfsg/sim/ucsim/cmd.src/cmd_confcl.h 2019-03-22 11:23:06.000000000 +0000 +++ sdcc-4.2.0+dfsg/sim/ucsim/cmd.src/cmd_confcl.h 2020-12-08 20:50:59.000000000 +0000 @@ -34,8 +34,8 @@ extern void set_conf_help(class cl_cmd *cmd); // CONF -//COMMAND_ON(uc,cl_conf_cmd); -class cl_conf_cmd: public cl_cmd +COMMAND_ON(uc,cl_conf_cmd); +/*class cl_conf_cmd: public cl_cmd { public: cl_conf_cmd(const char *aname, @@ -44,11 +44,14 @@ virtual int do_work(class cl_uc *uc , class cl_cmdline *cmdline, class cl_console_base *con); virtual void set_help(void); -}; + };*/ // CONF OBJECTS COMMAND_ON(app,cl_conf_objects_cmd); +// VER +COMMAND_ON(app,cl_ver_cmd); + // JAJ COMMAND_ON(app,cl_jaj_cmd); diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/cmd.src/cmd_exec.cc sdcc-4.2.0+dfsg/sim/ucsim/cmd.src/cmd_exec.cc --- sdcc-4.0.0+dfsg/sim/ucsim/cmd.src/cmd_exec.cc 2019-04-02 10:46:33.000000000 +0000 +++ sdcc-4.2.0+dfsg/sim/ucsim/cmd.src/cmd_exec.cc 2022-01-26 16:35:40.000000000 +0000 @@ -24,21 +24,25 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ /*@1@*/ -#include -#include "ddconfig.h" + +//#include +#include +#include + +//#include "ddconfig.h" // prj -#include "i_string.h" +//#include "i_string.h" #include "utils.h" #include "globals.h" // sim.src -#include "simcl.h" -#include "uccl.h" +//#include "simcl.h" +//#include "uccl.h" // local, cmd.src #include "cmd_execcl.h" -#include "cmdutil.h" +//#include "cmdutil.h" /* @@ -61,26 +65,26 @@ if (params[0]) if (!(params[0]->get_address(sim->uc, &start))) { - con->dd_printf(cchars("Error: wrong start address\n")); + con->dd_printf("Error: wrong start address\n"); return(false); } if (params[1]) if (!(params[1]->get_address(sim->uc, &end))) { - con->dd_printf(cchars("Error: wromg end address\n")); + con->dd_printf("Error: wrong end address\n"); return(false); } if (params[0]) { if (!sim->uc->inst_at(start)) - con->dd_printf(cchars("Warning: maybe not instruction at 0x%06x\n"), + con->dd_printf("Warning: maybe not instruction at 0x%06x\n", AI(start)); sim->uc->PC= start; if (params[1]) { if (start == end) { - con->dd_printf(cchars("Addresses must be different.\n")); + con->dd_printf("Addresses must be different.\n"); return(false); } if ((b= sim->uc->fbrk_at(end))) @@ -95,7 +99,7 @@ } } } - con->dd_printf(cchars("Simulation started, PC=0x%06x\n"), AI(sim->uc->PC)); + con->dd_printf("Simulation started, PC=0x%06x\n", AI(sim->uc->PC)); /* if (sim->uc->fbrk_at(sim->uc->PC)) sim->uc->do_inst(1); @@ -231,9 +235,10 @@ } CMDHELP(cl_step_cmd, - "step [number [unit]]", + "step [number[unit]]", "Step", "long help of step") + /* * Command: next *---------------------------------------------------------------------------- @@ -326,9 +331,9 @@ { class cl_cmd *c= (class cl_cmd *)(cmdset->at(i)); /*if (c->short_help.nempty()) - con->dd_printf("%s\n", (char*)c->short_help); + con->dd_printf("%s\n", c->short_help.c_str()); else - con->dd_printf("%s\n", (char*)(c->names->at(0)));*/ + con->dd_printf("%s\n", c->names->at(0).c_str());*/ c->print_short(con); } } @@ -342,24 +347,24 @@ int names; con->dd_printf("Names of command:"); for (names= 0; names < cmd_found->names->count; names++) - con->dd_printf(" %s", (char*)(cmd_found->names->at(names))); + con->dd_printf(" %s", cmd_found->names->at(names)); con->dd_printf("\n"); class cl_cmdset *subset= cmd_found->get_subcommands(); if (subset) { con->dd_printf("\"%s\" must be followed by the name of a " "subcommand\nList of subcommands:\n", - (char*)(cmd_found->names->at(0))); + cmd_found->names->at(0)); for (i= 0; i < subset->count; i++) { class cl_cmd *c= dynamic_cast(subset->object_at(i)); - //con->dd_printf("%s\n", (char*)c->short_help); + //con->dd_printf("%s\n", c->short_help.c_str()); c->print_short(con); } } if (cmd_found->long_help.nempty()) - con->dd_printf("%s\n", (char*)cmd_found->long_help); + con->dd_printf("%s\n", cmd_found->long_help.c_str()); } if (!matches || !cmd_found) @@ -397,9 +402,9 @@ matches++; cmd_found= cmd; /*if (cmd->short_help.nempty()) - con->dd_printf("%s\n", (char*)cmd->short_help); + con->dd_printf("%s\n", cmd->short_help.c_str()); else - con->dd_printf("%s\n", (char*)(cmd->names->at(0)));*/ + con->dd_printf("%s\n", cmd->names->at(0).c_str());*/ cmd->print_short(con); //continue; } @@ -486,57 +491,156 @@ COMMAND_DO_WORK_APP(cl_expression_cmd) { - char *s= cmdline->cmd; - char *fmt= NULL; - int fmt_len= 0; + const char *s; + chars cs, w, fmt; + + cmdline->shift(); + s= cmdline->cmd; if (!s || !*s) return(false); - int i= strspn(s, " \t\v\n\r"); - s+= i; - i= strspn(s, "abcdefghijklmnopqrstuvwxyz"); - s+= i; - i= strspn(s, " \t\v\n"); - s+= i; - t_mem v= 0; - if (s && *s) + + cs= s; + cs.start_parse(); + w= cs.token(" \r\n\v\r"); + fmt= ""; + con->dd_color("result"); + while (w.nempty()) { - if (*s == '/') - { - i= strcspn(s, " \t\v\n\r"); - fmt= s+1; - fmt_len= i; - s+= i; - i= strspn(s, " \t\v\n\r"); - s+= i; - } - if (s && *s) - v= application->eval(s); - if (fmt) + if (w.starts_with("/")) + fmt= w; + else { - for (i= 0; i < fmt_len; i++) + t_mem v= 0; + if (w.nempty()) { - switch (fmt[i]) - { - case 'x': con->dd_printf("%x\n", MU(v)); break; - case 'X': con->dd_printf("0x%x\n", MU(v)); break; - case '0': con->dd_printf("0x%08x\n", MU32(v)); break; - case 'd': con->dd_printf("%d\n", MI(v)); break; - case 'o': con->dd_printf("%o\n", MU(v)); break; - case 'u': con->dd_printf("%u\n", MU(v)); break; - case 'b': con->dd_printf("%s\n", (char*)cbin(v,8*sizeof(v))); break; - } + v= application->eval(w); + con->print_expr_result(v, fmt.nempty()?((const char *)fmt):NULL); } + fmt= ""; } - else - con->dd_printf("%d\n", MI(v)); + w= cs.token(" \n\r\v\t"); } return(false); } CMDHELP(cl_expression_cmd, "expression [/format] expr", - "Evaluate the expression", - "long help of expression ") + "Evaluate the expression and print result", + "Parameter of the command is interpreted as an expression,\n" + "the value evaluated and the result is printed.\n" + "Optional format specifier can be used to specify output format,\n" + "for example printing 0xa5f can be formatted as:\n" + " /x hexadecimal, without prefix: 5fa\n" + " /X hexadecimal with 0x prefix: 0x5fa\n" + " /$ hexadecimal with $ prefix: $5fa\n" + " /0 hexadecimal with 0x prefix, leading zeros to length 8: 0x00000a5f\n" + " /d signed 32 bit decimal (default): 2655\n" + " /o octal: 5137\n" + " /u unsigned 32 bit decimal: 2655\n" + " /b 32 bit binary without prefix: 00000000000000000000101001011111\n" + " /B C style boolean value with 1|0: 1\n" + " /L logical boolean value with T|F: T\n" + " /c ascii character in C style escape: \'\\5137\'\n" + "If more format characters are specified then result is printed in all\n" + "requested format.\n" + ) + + +/* + * HISTORY command + *---------------------------------------------------------------------------- + */ + +COMMAND_DO_WORK_UC(cl_hist_cmd) +{ + class cl_exec_hist *hi= uc->hist; + + if (hi->get_used() == 0) + return 0; + uc->hist->list(con, true, 10); + return 0; +} + +CMDHELP(cl_hist_cmd, + "history", + "Execution history", + "long help of history") + + +/* + * HISTORY INFO command + *---------------------------------------------------------------------------- + */ + +COMMAND_DO_WORK_UC(cl_hist_info_cmd) +{ + //int i; + //class cl_cmd_arg *params[1]= { cmdline->param(0) }; + //char *s= NULL; + class cl_exec_hist *hi= uc->hist; + + con->dd_printf("len: %d\n", hi->get_len()); + con->dd_printf("used: %u\n", hi->get_used()); + con->dd_printf("insts: %u\n", hi->get_insts()); + return 0; +} + +CMDHELP(cl_hist_info_cmd, + "history info", + "Information about execution history", + "long help of history info") + + +/* + * HISTORY CLEAR command + *---------------------------------------------------------------------------- + */ + +COMMAND_DO_WORK_UC(cl_hist_clear_cmd) +{ + //int i; + //class cl_cmd_arg *params[1]= { cmdline->param(0) }; + //char *s= NULL; + class cl_exec_hist *hi= uc->hist; + + hi->clear(); + + return 0; +} + +CMDHELP(cl_hist_clear_cmd, + "history clear", + "Clear execution history", + "long help of history clear") + + +/* + * HISTORY LIST command + *---------------------------------------------------------------------------- + */ + +COMMAND_DO_WORK_UC(cl_hist_list_cmd) +{ + int nr= 10; + class cl_cmd_arg *params[1]= { cmdline->param(0) }; + //char *s= NULL; + class cl_exec_hist *hi= uc->hist; + + if (hi->get_used() == 0) + return 0; + + if (params[0] != NULL) + nr= params[0]->i_value; + uc->hist->list(con, true, nr); + + return 0; +} + +CMDHELP(cl_hist_list_cmd, + "history list [nr]", + "List last `nr' elements of execution history", + "long help of history list") + /* End of cmd.src/cmd_exec.cc */ diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/cmd.src/cmd_execcl.h sdcc-4.2.0+dfsg/sim/ucsim/cmd.src/cmd_execcl.h --- sdcc-4.0.0+dfsg/sim/ucsim/cmd.src/cmd_execcl.h 2016-07-26 21:10:26.000000000 +0000 +++ sdcc-4.2.0+dfsg/sim/ucsim/cmd.src/cmd_execcl.h 2020-12-08 20:50:59.000000000 +0000 @@ -55,6 +55,13 @@ COMMAND_ON(app,cl_expression_cmd); +// History +COMMAND_ON(uc,cl_hist_cmd); +COMMAND_ON(uc,cl_hist_info_cmd); +COMMAND_ON(uc,cl_hist_clear_cmd); +COMMAND_ON(uc,cl_hist_list_cmd); + + #endif /* End of cmd.src/cmd_execcl.h */ diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/cmd.src/cmd_get.cc sdcc-4.2.0+dfsg/sim/ucsim/cmd.src/cmd_get.cc --- sdcc-4.0.0+dfsg/sim/ucsim/cmd.src/cmd_get.cc 2019-07-02 08:44:01.000000000 +0000 +++ sdcc-4.2.0+dfsg/sim/ucsim/cmd.src/cmd_get.cc 2020-11-20 07:26:04.000000000 +0000 @@ -25,30 +25,32 @@ 02111-1307, USA. */ /*@1@*/ -#include "ddconfig.h" +//#include "ddconfig.h" -#include -#include "i_string.h" +//#include +#include -#include +//#include "i_string.h" + +//#include // prj #include "utils.h" #include "appcl.h" // sim -#include "simcl.h" -#include "optioncl.h" +//#include "simcl.h" +//#include "optioncl.h" // local #include "cmd_getcl.h" -#include "cmdutil.h" +//#include "cmdutil.h" void set_get_help(class cl_cmd *cmd) { cmd->set_help("get subcommand", - "Get value of differend objects", + "Get value of different objects", "Long of get"); } @@ -78,7 +80,7 @@ if (!parm->as_address(uc) || !mem->valid_address(parm->value.address)) con->dd_printf("Warning: Invalid address %s\n", - (char*)cmdline->tokens->at(i)); + cmdline->tokens->at(i)); else mem->dump(parm->value.address, parm->value.address, 1, con/*->get_fout()*/); } diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/cmd.src/cmd_gui.cc sdcc-4.2.0+dfsg/sim/ucsim/cmd.src/cmd_gui.cc --- sdcc-4.0.0+dfsg/sim/ucsim/cmd.src/cmd_gui.cc 2019-03-24 10:01:12.000000000 +0000 +++ sdcc-4.2.0+dfsg/sim/ucsim/cmd.src/cmd_gui.cc 2020-03-27 20:18:53.000000000 +0000 @@ -25,13 +25,13 @@ 02111-1307, USA. */ /*@1@*/ -#include "ddconfig.h" +//#include "ddconfig.h" // prj -#include "globals.h" +//#include "globals.h" // sim -#include "simcl.h" +//#include "simcl.h" // local #include "cmd_guicl.h" diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/cmd.src/cmd_info.cc sdcc-4.2.0+dfsg/sim/ucsim/cmd.src/cmd_info.cc --- sdcc-4.0.0+dfsg/sim/ucsim/cmd.src/cmd_info.cc 2019-04-02 10:46:33.000000000 +0000 +++ sdcc-4.2.0+dfsg/sim/ucsim/cmd.src/cmd_info.cc 2022-01-26 16:35:40.000000000 +0000 @@ -26,7 +26,9 @@ /*@1@*/ #include -#include "i_string.h" +#include + +//#include "i_string.h" // sim.src #include "simcl.h" @@ -55,18 +57,16 @@ for (i= 0; i < uc->fbrk->count; i++) { class cl_brk *fb= (class cl_brk *)(uc->fbrk->at(i)); - const char *s= uc->disass(fb->addr, NULL); - con->dd_printf("%-3d %-10s %s %-5d %-5d 0x%06x %-5s %s\n", fb->nr, + con->dd_printf("%-3d %-10s %s %-5d %-5d 0x%06x %-5s ", fb->nr, "fetch", (fb->perm==brkFIX)?"keep":"del ", fb->hit, fb->cnt, AU(fb->addr), - fb->condition()?"true":"false", - s); + fb->condition()?"true":"false"); + uc->print_disass(fb->addr, con); extra= false; if (!(fb->cond.empty())) - con->dd_printf(" cond=\"%s\"", (char*)(fb->cond)), extra= true; + con->dd_printf(" cond=\"%s\"", fb->cond.c_str()), extra= true; if (!(fb->commands.empty())) - con->dd_printf(" cmd=\"%s\"", (char*)(fb->commands)), extra= true; - free((char *)s); + con->dd_printf(" cmd=\"%s\"", fb->commands.c_str()), extra= true; if (extra) con->dd_printf("\n"); } for (i= 0; i < uc->ebrk->count; i++) @@ -78,9 +78,9 @@ AU(eb->addr), eb->id); extra= false; if (!(eb->cond.empty())) - con->dd_printf(" cond=\"%s\"", (char*)(eb->cond)), extra= true; + con->dd_printf(" cond=\"%s\"", eb->cond.c_str()), extra= true; if (!(eb->commands.empty())) - con->dd_printf(" cmd=\"%s\"", (char*)(eb->commands)), extra= true; + con->dd_printf(" cmd=\"%s\"", eb->commands.c_str()), extra= true; if (extra) con->dd_printf("\n"); } return(0); @@ -123,9 +123,11 @@ if (cmdline->syntax_match(uc, HW)) { hw= params[0]->value.hw; + con->dd_color("answer"); hw->print_info(con); + hw->print_cfg_info(con); } - else if (cmdline->syntax_match(uc, STRING)) + /*else if (cmdline->syntax_match(uc, STRING)) { char *s= params[0]->get_svalue(); if (s && *s && (strcmp("cpu", s)==0)) @@ -133,7 +135,7 @@ if (uc->cpu) uc->cpu->print_info(con); } - } + }*/ else syntax_error(con); @@ -141,7 +143,7 @@ } CMDHELP(cl_info_hw_cmd, - "info hardware cathegory", + "info hardware category", "Status of hardware elements of the CPU", "long help of info hardware") @@ -232,7 +234,7 @@ COMMAND_DO_WORK_UC(cl_info_var_cmd) { - class cl_var *v; + class cl_cvar *v; int i; class cl_cmd_arg *params[1]= { cmdline->param(0) }; char *s= NULL; @@ -244,15 +246,11 @@ !*s) s= NULL; } - for (i= 0; i < uc->vars->count; i++) + for (i= 0; i < uc->vars->by_name.count; i++) { - v= (class cl_var *)(uc->vars->at(i)); - if ((s == NULL) || - ( - (strstr(v->as->get_name(), s) != NULL) || - (strstr(v->get_name(), s) != NULL) - ) - ) + v= uc->vars->by_name.at(i); + if ((s == NULL && *(v->get_name()) != '.') || + (s != NULL && strstr(v->get_name(), s) != NULL)) v->print_info(con); } return 0; @@ -263,4 +261,5 @@ "Information about variables", "long help of info variables") + /* End of cmd.src/cmd_info.cc */ diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/cmd.src/cmdlex.l sdcc-4.2.0+dfsg/sim/ucsim/cmd.src/cmdlex.l --- sdcc-4.0.0+dfsg/sim/ucsim/cmd.src/cmdlex.l 2019-05-30 07:36:35.000000000 +0000 +++ sdcc-4.2.0+dfsg/sim/ucsim/cmd.src/cmdlex.l 2022-01-27 21:35:29.000000000 +0000 @@ -1,8 +1,11 @@ %{ #include //#include +#include +#include #include "cmdlexcl.h" #include "cmdpars.hh" +#include "cmdutil.h" static int uc_yy_check_id(char *token); static int uc_yy_input(char *buf, int max_size); @@ -54,7 +57,7 @@ "?" return(PTOK_QUESTION); ":" return(PTOK_COLON); "<" return(PTOK_LESS); -">" return(PTOK_GREATHER); +">" return(PTOK_GREATER); "!" return(PTOK_EXCLAMATION); "," return(PTOK_COMMA); @@ -71,7 +74,28 @@ return PTOK_NUMBER; } -[a-zA-Z_][0-9a-zA-Z_]* return(uc_yy_check_id(yytext)); +$[0-9a-fA-F]+ { + yylval.number= strtol(&yytext[1], 0, 16); + return PTOK_NUMBER; +} + +\.?[a-zA-Z_][0-9a-zA-Z_]*($[0-9]+)? return(uc_yy_check_id(yytext)); + +'.*' { + char *s, *p; + int l= strlen(&yytext[1]); + yylval.number=0; + if (l>0) + { + s= strdup(&yytext[1]); + s[strlen(s)-1]= 0; + p= proc_escape(s, &l); + yylval.number= p[0]; + free(s); + free(p); + } + return PTOK_NUMBER; +} . return(yytext[0]); @@ -148,34 +172,34 @@ } t_addr addr; - class cl_address_space *as; bool found; - if ((found= uc->symbol2address(yytext, &as, &addr))) + if ((found= uc->symbol2address(yytext, &mem, &addr))) { - yylval.memory.memory= as; + yylval.memory.memory= mem; yylval.memory.address= addr; return PTOK_MEMORY; } - /* - else if ((found= uc->symbol2address(yytext, uc->sfr_tbl(), &addr))) - { - //yylval.number= addr; return PTOK_NUMBER; - yylval.memory.memory = uc->address_space(MEM_SFR_ID); - yylval.memory.address = addr; - return PTOK_MEMORY; - } - */ - //found= uc->symbol2address(yytext, uc->bit_tbl(), &addr); if (found) { t_addr memaddr; - t_mem mask; - yylval.bit.memory= uc->bit2mem(addr, &memaddr, &mask); + int bitnr_low, bitnr_high; + yylval.bit.memory= uc->bit2mem(addr, &memaddr, &bitnr_high, &bitnr_low); yylval.bit.mem_address = memaddr; yylval.bit.bit_address = addr; - yylval.bit.mask = mask; - return PTOK_BIT; + yylval.bit.bitnr_high = bitnr_high; + yylval.bit.bitnr_low = bitnr_low; + return PTOK_BITS; } + { + t_index i; + found= uc->vars->by_name.search(token, i); + if (found) + { + class cl_cvar *v= (class cl_cvar *)uc->vars->by_name.at(i); + yylval.cell= v->get_cell(); + return PTOK_CELL; + } + } } return 0; diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/cmd.src/cmd_mem.cc sdcc-4.2.0+dfsg/sim/ucsim/cmd.src/cmd_mem.cc --- sdcc-4.0.0+dfsg/sim/ucsim/cmd.src/cmd_mem.cc 2019-05-06 09:55:43.000000000 +0000 +++ sdcc-4.2.0+dfsg/sim/ucsim/cmd.src/cmd_mem.cc 2021-12-29 23:20:23.000000000 +0000 @@ -27,10 +27,10 @@ // prj #include "globals.h" -#include "utils.h" +//#include "utils.h" // sim -#include "simcl.h" +//#include "simcl.h" // local #include "cmd_memcl.h" @@ -93,8 +93,7 @@ con->dd_printf("Wrong width\n"); else { - class cl_memory *mem= new cl_memory_chip(memid, size, width); - mem->init(); + class cl_memory *mem= new_chip(memid, size, width); uc->memchips->add(mem); mem->set_uc(uc); } @@ -481,10 +480,10 @@ con->dd_printf("%s", as->get_name()); con->dd_printf("["); con->dd_printf(as->addr_format, a); - con->dd_printf("] %s\n", (char*)uc->cell_name(c)); + con->dd_printf("] %s\n", uc->cell_name(c).c_str()); - con->dd_printf("cell data=%p/%d mask=%x flags=%x\n", - c->get_data(), + con->dd_printf("cell width=%d mask=%x flags=%x\n", + //c->get_data(), MU(c->get_width()), MU(c->get_mask()), MU(c->get_flags())); @@ -513,4 +512,52 @@ "Information about a memory cell", "long help of memory cell") + + +void +set_memory_remove_help(class cl_cmd *cmd) +{ + cmd->set_help("memory remove subcommand", + "Set of commands to remove memory objects", + "Long of memory remove"); +} + + +COMMAND_DO_WORK_UC(cl_memory_remove_chip_cmd) +{ + class cl_cmd_arg *params[4]= { cmdline->param(0), + cmdline->param(1), + cmdline->param(2), + cmdline->param(3) }; + class cl_memory *chip= 0; + + if (cmdline->syntax_match(uc, MEMORY)) { + chip= params[0]->value.memory.memory; + } + else + syntax_error(con); + + if (!chip) + con->dd_printf("Wrong id\n"); + else if (!chip->is_chip()) + con->dd_printf("Not chip\n"); + else + { + /* + class cl_memory *mem= new_chip(memid, size, width); + uc->memchips->add(mem); + mem->set_uc(uc); + */ + uc->remove_chip(chip); + } + return(false); +} + +CMDHELP(cl_memory_remove_chip_cmd, + "memory remove chip id", + "Delete a memory chip", + "long help of memory remove chip") + + + /* End of cmd.src/cmd_mem.cc */ diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/cmd.src/cmd_memcl.h sdcc-4.2.0+dfsg/sim/ucsim/cmd.src/cmd_memcl.h --- sdcc-4.0.0+dfsg/sim/ucsim/cmd.src/cmd_memcl.h 2019-03-22 11:23:06.000000000 +0000 +++ sdcc-4.2.0+dfsg/sim/ucsim/cmd.src/cmd_memcl.h 2021-12-04 17:57:16.000000000 +0000 @@ -56,6 +56,11 @@ COMMAND_ON(uc,cl_memory_cell_cmd); +extern void set_memory_remove_help(class cl_cmd *cmd); + +// MEMORY REMOVE CHIP +COMMAND_ON(uc,cl_memory_remove_chip_cmd); + #endif /* End of cmd.src/cmd_memcl.h */ diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/cmd.src/cmdpars.y sdcc-4.2.0+dfsg/sim/ucsim/cmd.src/cmdpars.y --- sdcc-4.0.0+dfsg/sim/ucsim/cmd.src/cmdpars.y 2019-07-02 08:44:01.000000000 +0000 +++ sdcc-4.2.0+dfsg/sim/ucsim/cmd.src/cmdpars.y 2022-01-27 21:35:29.000000000 +0000 @@ -1,9 +1,11 @@ %{ - +#include +#include + #include "cmdlexcl.h" -#include "memcl.h" + //#include "memcl.h" #include "globals.h" -#include "stypes.h" + //#include "stypes.h" static void yyerror (const char *msg); %} @@ -14,7 +16,7 @@ %token PTOK_LEFT_BRACKET PTOK_RIGHT_BRACKET %token PTOK_DOT PTOK_AMPERSAND PTOK_PIPE PTOK_CIRCUM %token PTOK_PERCENT PTOK_TILDE PTOK_QUESTION PTOK_COLON PTOK_EXCLAMATION -%token PTOK_LESS PTOK_GREATHER PTOK_COMMA +%token PTOK_LESS PTOK_GREATER PTOK_COMMA %token PTOK_AND_OP PTOK_OR_OP %token PTOK_INC_OP PTOK_DEC_OP @@ -38,7 +40,8 @@ %token PTOK_MEMORY_OBJECT %token PTOK_MEMORY %token PTOK_NUMBER -%token PTOK_BIT +%token PTOK_BITS +%token PTOK_CELL %type ucsim_grammar expr %type primary_expr postfix_expr @@ -57,6 +60,7 @@ %union { long number; class cl_memory *memory_object; + class cl_memory_cell *cell; struct { class cl_memory *memory; long address; @@ -64,7 +68,7 @@ struct { class cl_memory *memory; long mem_address, bit_address; - long mask; + int bitnr_high, bitnr_low; } bit; } @@ -138,8 +142,14 @@ primary_expr /* : identifier */ : memory { $$= $1.memory->read($1.address); } -| bit { $$= ($1.memory->read($1.mem_address) & $1.mask)?1:0; } +| bit + { + t_mem mask = 0; + for (int i = $1.bitnr_low; i <= $1.bitnr_high; mask |= 1U << i++); + $$= ($1.memory->read($1.mem_address) & mask) >> $1.bitnr_low; + } | PTOK_NUMBER { $$= $1; } +| PTOK_CELL { $$= $1->read(); } /* | string_literal_val*/ | PTOK_LEFT_PAREN expr PTOK_RIGHT_PAREN { $$= $2; } /* | generic_selection*/ @@ -158,12 +168,22 @@ $$= $1.memory->read($1.address); $1.memory->write($1.address, $$+1); } +| PTOK_CELL PTOK_INC_OP + { + $$= $1->read(); + $1->write($$+1); + } /*| postfix_expr PTOK_DEC_OP*/ | memory PTOK_DEC_OP { $$= $1.memory->read($1.address); $1.memory->write($1.address, $$-1); } +| PTOK_CELL PTOK_DEC_OP + { + $$= $1->read(); + $1->write($$-1); + } ; /* argument_expr_list @@ -181,6 +201,12 @@ $2.memory->write($2.address, $$+1); $$= $2.memory->read($2.address); } +| PTOK_INC_OP PTOK_CELL + { + $$= $2->read(); + $2->write($$+1); + $$= $2->read(); + } /*| PTOK_DEC_OP unary_expr */ | PTOK_DEC_OP memory { @@ -188,6 +214,12 @@ $2.memory->write($2.address, $$-1); $$= $2.memory->read($2.address); } +| PTOK_DEC_OP PTOK_CELL + { + $$= $2->read(); + $2->write($$-1); + $$= $2->read(); + } /*| unary_operator cast_expr */ /*| PTOK_AMPERSAND unary_expr*/ |PTOK_AMPERSAND memory { $$= $2.address; } @@ -264,7 +296,7 @@ relational_expr : shift_expr { $$= $1; } | relational_expr PTOK_LESS shift_expr { $$= ($1 < $3)?1:0; } -| relational_expr PTOK_GREATHER shift_expr { $$= ($1 > $3)?1:0; } +| relational_expr PTOK_GREATER shift_expr { $$= ($1 > $3)?1:0; } | relational_expr PTOK_LE_OP shift_expr { $$= ($1 <= $3)?1:0; } | relational_expr PTOK_GE_OP shift_expr { $$= ($1 >= $3)?1:0; } ; @@ -353,18 +385,53 @@ } | bit PTOK_EQUAL assignment_expr { - if ($3) - { - $1.memory->write($1.mem_address, - $1.memory->read($1.mem_address) | $1.mask); - $$= 1; - } - else + t_mem mask = 0; + for (int i = $1.bitnr_low; i <= $1.bitnr_high; mask |= 1U << i++); + mask= ($1.memory->read($1.mem_address) & (~mask)) | (($3 & mask) << $1.bitnr_low); + $1.memory->write($1.mem_address, mask); + $$= mask; + } +| PTOK_CELL assignment_operator assignment_expr + { + t_mem org= $1->read(); + $$= $3; + switch ($2) { - $1.memory->write($1.mem_address, - $1.memory->read($1.mem_address) & ~($1.mask)); - $$= 0; + case PTOK_EQUAL: + $1->write($3); + break; + case PTOK_MUL_ASSIGN: + $1->write(org *= $3); + break; + case PTOK_DIV_ASSIGN: + $1->write(org /= $3); + break; + case PTOK_MOD_ASSIGN: + $1->write(org %= $3); + break; + case PTOK_ADD_ASSIGN: + $1->write(org += $3); + break; + case PTOK_SUB_ASSIGN: + $1->write(org -= $3); + break; + case PTOK_LEFT_ASSIGN: + $1->write(org <<= $3); + break; + case PTOK_RIGHT_ASSIGN: + $1->write(org >>= $3); + break; + case PTOK_AND_ASSIGN: + $1->write(org &= $3); + break; + case PTOK_XOR_ASSIGN: + $1->write(org ^= $3); + break; + case PTOK_OR_ASSIGN: + $1->write(org |= $3); + break; } + $$= $1->read(); } ; @@ -394,19 +461,36 @@ $$.memory= $1; $$.address= $3; } + ; bit: - PTOK_BIT + PTOK_BITS | memory PTOK_DOT expr { $$.memory= $1.memory; $$.mem_address= $1.address; - $$.mask= 1 << $3; + $$.bitnr_low= $$.bitnr_high= $3; $$.bit_address= -1; class cl_uc *uc= application->get_uc(); if (uc) $$.bit_address= uc->bit_address($1.memory, $1.address, $3); } + | memory PTOK_LEFT_BRACKET expr PTOK_COLON expr PTOK_RIGHT_BRACKET + { + $$.memory= $1.memory; + $$.mem_address= $1.address; + if ($3 < $5) + { + $$.bitnr_low= $3; + $$.bitnr_high= $5; + } + else + { + $$.bitnr_low= $5; + $$.bitnr_high= $3; + } + $$.bit_address= -1; + } ; %% diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/cmd.src/cmd_set.cc sdcc-4.2.0+dfsg/sim/ucsim/cmd.src/cmd_set.cc --- sdcc-4.0.0+dfsg/sim/ucsim/cmd.src/cmd_set.cc 2019-07-02 08:44:01.000000000 +0000 +++ sdcc-4.2.0+dfsg/sim/ucsim/cmd.src/cmd_set.cc 2022-01-26 16:35:40.000000000 +0000 @@ -27,22 +27,24 @@ */ /*@1@*/ -#include "ddconfig.h" +//#include "ddconfig.h" -#include -#include "i_string.h" +//#include +#include + +//#include "i_string.h" // prj -#include "errorcl.h" +//#include "errorcl.h" #include "appcl.h" // sim -#include "simcl.h" -#include "optioncl.h" +//#include "simcl.h" +//#include "optioncl.h" // local #include "cmd_setcl.h" -#include "cmdutil.h" +//#include "cmdutil.h" void @@ -64,82 +66,74 @@ COMMAND_DO_WORK_UC(cl_set_mem_cmd) { class cl_memory *mem= 0; + t_addr start= 0; + t_mem *array= NULL; + int len= 0; + int bitnr_low= -1, bitnr_high= -1; class cl_cmd_arg *params[4]= { cmdline->param(0), cmdline->param(1), - cmdline->param(2), - cmdline->param(3) }; + cmdline->param(2) }; - if (cmdline->syntax_match(uc, MEMORY ADDRESS DATALIST)) { - mem= params[0]->value.memory.memory; - t_addr start= params[1]->value.address; - t_mem *array= params[2]->value.data_list.array; - int len= params[2]->value.data_list.len; - - if (len == 0) - con->dd_printf("Error: no data\n"); - else if (start < mem->get_start_address()) - con->dd_printf("Start address less then 0x%x\n", - AU(mem->get_start_address())); - else - { - int i; - t_addr addr; - for (i= 0, addr= start; - i < len && mem->valid_address(addr); - i++, addr++) - mem->write(addr, array[i]); - uc->check_errors(); - mem->dump(start, start+len-1, 8, con/*->get_fout()*/); - } - } - else - syntax_error(con); - - return(false);; -} - -CMDHELP(cl_set_mem_cmd, - "set memory memory_type address data...", - "Place list of data into memory", - "long help of set memory") - -/* - * Command: set bit - *---------------------------------------------------------------------------- - */ + if (cmdline->syntax_match(uc, BIT DATALIST)) + { + mem= params[0]->value.bit.mem; + start= params[0]->value.bit.mem_address; + bitnr_low= params[0]->value.bit.bitnr_low; + bitnr_high= params[0]->value.bit.bitnr_high; + array= params[1]->value.data_list.array; + len= params[1]->value.data_list.len; + } + else if (cmdline->syntax_match(uc, MEMORY ADDRESS DATALIST)) + { + mem= params[0]->value.memory.memory; + start= params[1]->value.address; + array= params[2]->value.data_list.array; + len= params[2]->value.data_list.len; + } -//int -//cl_set_bit_cmd::do_work(class cl_sim *sim, -// class cl_cmdline *cmdline, class cl_console *con) -COMMAND_DO_WORK_UC(cl_set_bit_cmd) -{ - class cl_memory *mem; - t_addr mem_addr= 0; - t_mem bit_mask= 0; - class cl_cmd_arg *params[4]= { cmdline->param(0), - cmdline->param(1), - cmdline->param(2), - cmdline->param(3) }; - - if (cmdline->syntax_match(uc, BIT NUMBER)) { - mem= params[0]->value.bit.mem; - mem_addr= params[0]->value.bit.mem_address; - bit_mask= params[0]->value.bit.mask; - if (params[1]->value.number) - mem->set_bit1(mem_addr, bit_mask); - else - mem->set_bit0(mem_addr, bit_mask); - mem->dump(mem_addr, mem_addr, 1, con/*->get_fout()*/); - } + if (mem) + { + if (len == 0) + con->dd_printf("Error: no data\n"); + else if (start < mem->get_start_address()) + { + con->dd_printf("Start address less than "); + con->dd_printf(mem->addr_format, mem->get_start_address()); + con->dd_printf("\n"); + } + else if (bitnr_low >= 0) + { + if (len > 1) + con->dd_printf("Error: excess data for bit(s)\n"); + else + { + t_mem mask= ((1U << (bitnr_high - bitnr_low + 1)) - 1) << bitnr_low; + mem->write(start, (mem->get(start) & (~mask)) | ((array[0] << bitnr_low) & mask)); + uc->check_errors(); + mem->dump(start, bitnr_high, bitnr_low, con); + } + } + else + { + int i; + t_addr addr; + for (i= 0, addr= start; + i < len && mem->valid_address(addr); + i++, addr++) + mem->write(addr, array[i]); + uc->check_errors(); + mem->dump(start, start+len-1, 8, con); + } + } else syntax_error(con); - return(false);; + return(false); } -CMDHELP(cl_set_bit_cmd, - "set bit addr 0|1", - "Set specified bit to 0 or 1", +CMDHELP(cl_set_mem_cmd, + "set memory memory_type address data... | bit data", + "Place list of data into memory OR set specified bit(s) to data", "long help of set bit") /* @@ -150,41 +144,27 @@ COMMAND_DO_WORK_UC(cl_set_hw_cmd) { class cl_hw *hw= 0; - class cl_cmd_arg *params[1]= { cmdline->param(0)/*, - cmdline->param(1), - cmdline->param(2), - cmdline->param(3)*/ }; + class cl_cmd_arg *params[1]= { cmdline->param(0) }; - if (params[0] && /*cmdline->syntax_match(uc, HW)*/params[0]->as_hw(uc)) { + if (params[0] && params[0]->as_hw(uc)) { hw= params[0]->value.hw; - //pn= hw->id; - //l= params[1]->value.number; } - /*else if (cmdline->syntax_match(uc, NUMBER NUMBER)) { - pn= params[0]->value.number; - l= params[1]->value.number; - hw= uc->get_hw(HW_PORT, pn, 0); - }*/ else syntax_error(con); - /*if (pn < 0 || - pn > 3) - con->dd_printf("Error: wrong port\n"); - else*/ + + if (hw) { - if (hw) - { - cmdline->shift(); - hw->set_cmd(cmdline, con); - } - else - con->dd_printf("Error: no hw\n"); + cmdline->shift(); + hw->set_cmd(cmdline, con); } + else + con->dd_printf("Error: no hw\n"); + return(false);; } CMDHELP(cl_set_hw_cmd, - "set hardware cathegory params...", + "set hardware category params...", "Set parameters of specified hardware element", "long help of set hardware") @@ -235,7 +215,7 @@ int n= app->options->nuof_options(id); if (n > 1) { - char *cr= (char*)con->get_name(); + const char *cr= con->get_name(); n= app->options->nuof_options(id, cr); if (n > 1) con->dd_printf("Ambiguous option name, use number instead\n"); @@ -384,7 +364,7 @@ else if ((strstr(s1, "c") == s1) || (strstr(s1, "e") == s1)) { - // coocked, edited + // cooked, edited con->set_cooked(true); } else diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/cmd.src/cmd_setcl.h sdcc-4.2.0+dfsg/sim/ucsim/cmd.src/cmd_setcl.h --- sdcc-4.0.0+dfsg/sim/ucsim/cmd.src/cmd_setcl.h 2019-03-22 11:23:06.000000000 +0000 +++ sdcc-4.2.0+dfsg/sim/ucsim/cmd.src/cmd_setcl.h 2021-04-01 17:52:48.000000000 +0000 @@ -36,9 +36,6 @@ // SET MEMORY COMMAND_ON(uc,cl_set_mem_cmd); -// SET BIT -COMMAND_ON(uc,cl_set_bit_cmd); - // SET HW COMMAND_ON(uc,cl_set_hw_cmd); diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/cmd.src/cmd_show.cc sdcc-4.2.0+dfsg/sim/ucsim/cmd.src/cmd_show.cc --- sdcc-4.0.0+dfsg/sim/ucsim/cmd.src/cmd_show.cc 2019-03-24 10:01:12.000000000 +0000 +++ sdcc-4.2.0+dfsg/sim/ucsim/cmd.src/cmd_show.cc 2020-08-22 10:25:08.000000000 +0000 @@ -25,18 +25,19 @@ 02111-1307, USA. */ /*@1@*/ -#include "ddconfig.h" +//#include "ddconfig.h" #include -#include "i_string.h" +#include +//#include "i_string.h" // prj #include "globals.h" #include "utils.h" -#include "errorcl.h" +//#include "errorcl.h" // sim -#include "simcl.h" +//#include "simcl.h" // local #include "cmd_showcl.h" @@ -211,7 +212,7 @@ "Show class of errors", "long help of show error") -#include "newcmdposixcl.h" +//#include "newcmdposixcl.h" /* * Command: show console @@ -223,9 +224,9 @@ { if (ff) { - char *n= ff->get_file_name(); - chars t= fio_type_name(ff->type); - con->dd_printf("\"%s\",%s,", n, (char*)t); + const char *n= ff->get_file_name(); + const char *t= fio_type_name(ff->type); + con->dd_printf("\"%s\",%s,", n, t); con->dd_printf("%d,%d,", ff->file_id, ff->server_port); con->dd_printf("%s,%s", ff->tty?"tty":"non-tty", diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/cmd.src/cmd_stat.cc sdcc-4.2.0+dfsg/sim/ucsim/cmd.src/cmd_stat.cc --- sdcc-4.0.0+dfsg/sim/ucsim/cmd.src/cmd_stat.cc 2019-04-02 10:46:33.000000000 +0000 +++ sdcc-4.2.0+dfsg/sim/ucsim/cmd.src/cmd_stat.cc 2020-03-27 20:18:53.000000000 +0000 @@ -25,13 +25,13 @@ 02111-1307, USA. */ /*@1@*/ -#include "ddconfig.h" +//#include "ddconfig.h" // prj #include "globals.h" // sim -#include "simcl.h" +//#include "simcl.h" // local #include "cmd_statcl.h" diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/cmd.src/cmd_timer.cc sdcc-4.2.0+dfsg/sim/ucsim/cmd.src/cmd_timer.cc --- sdcc-4.0.0+dfsg/sim/ucsim/cmd.src/cmd_timer.cc 2019-04-02 10:46:33.000000000 +0000 +++ sdcc-4.2.0+dfsg/sim/ucsim/cmd.src/cmd_timer.cc 2022-01-18 21:40:45.000000000 +0000 @@ -25,12 +25,14 @@ 02111-1307, USA. */ /*@1@*/ -#include "ddconfig.h" +//#include -#include "stdio.h" -#include "i_string.h" +//#include "ddconfig.h" + +//#include "i_string.h" // sim +#include "utils.h" #include "simcl.h" // local @@ -62,7 +64,7 @@ if (!params[0]) { - con->dd_printf("Timer id is missing."); + con->dd_printf("Timer id is missing.\n"); return(false); } if (params[0]->as_number()) @@ -102,18 +104,15 @@ COMMAND_DO_WORK_UC(cl_timer_add_cmd) //add(class cl_uc *uc, class cl_cmdline *cmdline, class cl_console *con) { - class cl_cmd_arg *params[4]= { cmdline->param(0), - cmdline->param(1), - cmdline->param(2), - cmdline->param(3) }; - long dir= +1, in_isr= 0; + enum ticker_type type = TICK_ANY; + long dir= +1; if (cl_timer_cmd::do_work(uc, cmdline, con)) return(false); if (ticker) { if (!as_nr) - con->dd_printf("Error: Timer \"%s\" already exists\n", (char*)id_str); + con->dd_printf("Error: Timer \"%s\" already exists\n", id_str.c_str()); else con->dd_printf("Error: Timer %d already exists\n", id_nr); return(false); @@ -122,22 +121,38 @@ if (cmdline->nuof_params() > 0) { if (cmdline->syntax_match(uc, NUMBER)) - dir= params[0]->value.number; + dir= cmdline->param(0)->value.number; else if (cmdline->syntax_match(uc, NUMBER NUMBER)) - { - dir= params[0]->value.number; - in_isr= params[1]->value.number; - } + { + dir= cmdline->param(0)->value.number; + if (cmdline->param(1)->value.number) + type = TICK_INISR; + } + else if (cmdline->syntax_match(uc, NUMBER STRING)) + { + dir= cmdline->param(0)->value.number; + if (!strcmp(cmdline->param(1)->value.string.string, "isr")) + type = TICK_INISR; + else if (!strcmp(cmdline->param(1)->value.string.string, "idle")) + type = TICK_IDLE; + else if (!strcmp(cmdline->param(1)->value.string.string, "halt")) + type = TICK_HALT; + } + else + { + con->dd_printf("Error: Wrong parameters\n"); + return(false); + } } if (!as_nr) { - ticker= new cl_ticker(dir, in_isr, (char*)id_str); + ticker= new cl_ticker(dir, type, id_str); uc->add_counter(ticker, id_str); } else { - ticker= new cl_ticker(dir, in_isr, 0); + ticker= new cl_ticker(dir, type, 0); uc->add_counter(ticker, id_nr); } @@ -145,7 +160,7 @@ } CMDHELP(cl_timer_add_cmd, - "timer add id [direction [in_isr]]", + "timer add id [direction [isr|idle|halt]]", "Create a clock counter (timer)", "log help of timer add") @@ -163,11 +178,16 @@ if (!ticker) { if (!as_nr) - con->dd_printf("Timer \"%s\" does not exist\n", (char*)id_str); + con->dd_printf("Timer \"%s\" does not exist\n", id_str.c_str()); else con->dd_printf("Timer %d does not exist\n", id_nr); return(false); } + if (!ticker->user) + { + con->dd_printf("Timer is not user and cannot be deleted\n"); + return(false); + } if (!as_nr) uc->del_counter(id_str); else @@ -198,17 +218,14 @@ else ticker= 0; if (ticker) - ticker->dump(id_nr, uc->xtal, con); + ticker->dump(id_nr, con); else { - uc->ticks->dump(0, uc->xtal, con); - uc->isr_ticks->dump(0, uc->xtal, con); - uc->idle_ticks->dump(0, uc->xtal, con); for (id_nr= 0; id_nr < uc->counters->count; id_nr++) { ticker= uc->get_counter(id_nr); if (ticker) - ticker->dump(id_nr, uc->xtal, con); + ticker->dump(id_nr, con); } } @@ -234,12 +251,12 @@ if (!ticker) { if (!as_nr) - con->dd_printf("Timer %s does not exist\n", (char*)id_str); + con->dd_printf("Timer %s does not exist\n", id_str.c_str()); else con->dd_printf("Timer %d does not exist\n", id_nr); return(0); } - ticker->options|= TICK_RUN; + ticker->run = true; return(false); } @@ -264,12 +281,12 @@ if (!ticker) { if (!as_nr) - con->dd_printf("Timer %s does not exist\n", (char*)id_str); + con->dd_printf("Timer %s does not exist\n", id_str.c_str()); else con->dd_printf("Timer %d does not exist\n", id_nr); return(false); } - ticker->options&= ~TICK_RUN; + ticker->run = false; return(false); } @@ -297,30 +314,48 @@ if (!ticker) { if (!as_nr) - con->dd_printf("Error: Timer %s does not exist\n", (char*)id_str); + con->dd_printf("Error: Timer %s does not exist\n", id_str.c_str()); else con->dd_printf("Error: Timer %d does not exist\n", id_nr); return(false); } - if (cmdline->param(0) == NULL) - { - con->dd_printf("Error: Value is missing\n"); - return(false); - } - long val; - if (!cmdline->param(0)->get_ivalue(&val)) + if (cmdline->nuof_params() > 0) { - con->dd_printf("Error: Wrong parameter\n"); - return(false); + if (cmdline->syntax_match(uc, NUMBER)) + { + long ticks= cmdline->param(0)->value.number; + ticker->set(ticks, ticks * uc->get_xtal_tick()); + } + else if (cmdline->syntax_match(uc, NUMBER STRING)) + { + const char *units; + double time = (double)cmdline->param(0)->value.number * strtoscale(cmdline->param(1)->value.string.string, &units); + if (units[0] != '\0' && units[0] != 's') + con->dd_printf("Expected units to be in seconds not \"%s\"\n", cmdline->param(1)->value.string.string); + else + ticker->set(time / uc->get_xtal_tick(), time); + } + else if (cmdline->syntax_match(uc, NUMBER NUMBER STRING)) + { + const char *units; + double time = (double)cmdline->param(1)->value.number * strtoscale(cmdline->param(2)->value.string.string, &units); + if (units[0] != '\0' && units[0] != 's') + con->dd_printf("Expected units to be in seconds not \"%s\"\n", cmdline->param(1)->value.string.string); + else + ticker->set(cmdline->param(0)->value.number, time); + } + else + con->dd_printf("Error: Wrong parameters\n"); } - ticker->ticks= val; + else + ticker->dump(id_nr, con); return(false); } CMDHELP(cl_timer_value_cmd, - "timer set id value", - "Set a timer value", + "timer set id [ticks] [time [muµnp]sec]", + "Set a timer", "long help of timer set") /* End of cmd.src/cmd_timer.cc */ diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/cmd.src/cmd_uc.cc sdcc-4.2.0+dfsg/sim/ucsim/cmd.src/cmd_uc.cc --- sdcc-4.0.0+dfsg/sim/ucsim/cmd.src/cmd_uc.cc 2019-07-02 08:44:01.000000000 +0000 +++ sdcc-4.2.0+dfsg/sim/ucsim/cmd.src/cmd_uc.cc 2022-01-24 11:09:43.000000000 +0000 @@ -26,18 +26,26 @@ /*@1@*/ #include +#include // prj #include "globals.h" #include "utils.h" // sim.src -#include "uccl.h" +//#include "uccl.h" // local, cmd.src #include "cmd_uccl.h" +static struct id_element cpu_states[]= { + { stGO, "OK" }, + { stIDLE, "Idle" }, + { stPD, "PowerDown" }, + { 0, 0 } +}; + /* * Command: state *---------------------------------------------------------------------------- @@ -48,10 +56,10 @@ // class cl_cmdline *cmdline, class cl_console *con) COMMAND_DO_WORK_UC(cl_state_cmd) { - con->dd_printf("CPU state= %s PC= 0x%06x XTAL= %g\n", + con->dd_printf("CPU state= %s PC= 0x%06x frequency= %.0f HZ\n", get_id_string(cpu_states, uc->state), AU(uc->PC), - uc->xtal); + uc->get_xtal()); con->dd_printf("Operation since last reset= (%lu vclks)\n", (unsigned long)(uc->vc.fetch) + (unsigned long)(uc->vc.rd) + @@ -60,20 +68,22 @@ con->dd_printf("Fetch= %lu ", (unsigned long)(uc->vc.fetch)); con->dd_printf("Read= %lu ", (unsigned long)(uc->vc.rd)); con->dd_printf("Write= %lu\n", (unsigned long)(uc->vc.wr)); - con->dd_printf("Total time since last reset= %g sec (%lu clks)\n", - uc->get_rtime(), (unsigned long)(uc->ticks->ticks)); - con->dd_printf("Time in isr = %g sec (%lu clks) %3.2g%%\n", - uc->isr_ticks->get_rtime(uc->xtal), - uc->isr_ticks->ticks, - (uc->ticks->ticks == 0)?0.0: - (100.0*((double)(uc->isr_ticks->ticks)/ - (double)(uc->ticks->ticks)))); - con->dd_printf("Time in idle= %g sec (%lu clks) %3.2g%%\n", - uc->idle_ticks->get_rtime(uc->xtal), - uc->idle_ticks->ticks, - (uc->ticks->ticks == 0)?0.0: - (100.0*((double)(uc->idle_ticks->ticks)/ - (double)(uc->ticks->ticks)))); + + con->dd_printf("Total time since last reset= %.15f sec (%lu clks)\n", + uc->ticks->get_rtime(), (unsigned long)(uc->ticks->get_ticks())); + + con->dd_printf("Time in isr = %.15f sec (%lu clks) %3.2f%%\n", + uc->isr_ticks->get_rtime(), + uc->isr_ticks->get_ticks(), + (uc->ticks->get_ticks() == 0 ? 0.0 : + (100.0 * uc->isr_ticks->get_rtime() / uc->ticks->get_rtime()))); + + con->dd_printf("Time in idle= %.15f sec (%lu clks) %3.2f%%\n", + uc->idle_ticks->get_rtime(), + uc->idle_ticks->get_ticks(), + (uc->ticks->get_ticks() == 0 ? 0.0 : + (100.0 * uc->idle_ticks->get_rtime() / uc->ticks->get_rtime()))); + con->dd_printf("Max value of stack pointer= 0x%06x, avg= 0x%06x\n", AU(uc->sp_max), AU(uc->sp_avg)); con->dd_printf("Simulation: %s\n", @@ -98,17 +108,19 @@ { const char *fname= 0; long l; - + if ((cmdline->param(0) == 0) || ((fname= cmdline->param(0)->get_svalue()) == NULL)) { con->dd_printf("File name is missing.\n"); return(0); } - + if ((l= uc->read_file(fname, con)) >= 0) - ;//con->dd_printf("%ld words read from %s\n", l, fname); - + { + //con->dd_printf("%ld words read from %s\n", l, fname); + } + return(0); } @@ -168,7 +180,7 @@ } if (!uc->inst_at(addr)) con->dd_printf("Warning: maybe not instruction at 0x%06x\n", AU(addr)); - uc->PC= addr; + uc->set_PC(addr); } uc->print_disass(uc->PC, con); return(false); @@ -199,6 +211,32 @@ "long help of reset") /* + * Command: tick + *---------------------------------------------------------------------------- + */ + +COMMAND_DO_WORK_UC(cl_tick_cmd) +{ + class cl_cmd_arg *params[1]; + params[0]= cmdline->param(0); + int cycles= 1; + + if (params[0] != NULL) + cycles= params[0]->i_value; + + uc->tick(cycles); + + return 0; +} + +CMDHELP(cl_tick_cmd, + "tick [number]", + "Tick a given number of clock cycles without execution", + "Ticks a given number of clock cycles. Timers and HW update but no" + " execution takes place.") + + +/* * Command: dump *---------------------------------------------------------------------------- */ @@ -208,35 +246,69 @@ // class cl_cmdline *cmdline, class cl_console *con) COMMAND_DO_WORK_UC(cl_dump_cmd) { - class cl_memory *mem= 0; - long bpl= 8; - t_addr start= 0, end; + class cl_memory *mem= uc->rom; + t_addr start = -1, end = -1; + long bpl= -1; + class cl_cmd_arg *params[4]= { cmdline->param(0), cmdline->param(1), cmdline->param(2), cmdline->param(3) }; - /*enum dump_format*/int fmt= df_hex; - + char fmt = 0; + + if (params[0] && + params[0]->as_string()) + { + char *s= params[0]->get_svalue(); + if (s && *s && s[0] == '/') + { + for (size_t i = 1; i < strlen(s); i++) + { + char c = tolower(s[i]); + switch (c) + { + case 'b': + if (con->get_fout() && con->get_fout()->tty) + { + con->dd_printf("Error: binary format not supported on tty\n"); + return false; + } + break; + case 'x': + case 'h': // hex + case 'i': // ihex + case 's': // string + break; + default: + con->dd_printf("Error: unknown format option '%c'\n", c); + return false; + } + fmt = c; + } + cmdline->params->free_at(0); + params[0]= cmdline->param(0); + params[1]= cmdline->param(1); + params[2]= cmdline->param(2); + params[3]= cmdline->param(3); + } + } + if (params[0] && - params[0]->as_bit(uc)) + params[0]->as_bit(uc) && + params[0]->value.bit.bitnr_low >= 0) { int i= 0; while (params[0] && params[0]->as_bit(uc)) { - t_mem m; - mem= params[0]->value.bit.mem; - m= mem->read(params[0]->value.bit.mem_address); - char *sn= - uc->symbolic_bit_name((t_addr)-1, - mem, - params[0]->value.bit.mem_address, - params[0]->value.bit.mask); - con->dd_printf("%10s ", sn?sn:""); - con->dd_printf(mem->addr_format, params[0]->value.bit.mem_address); - con->dd_printf(" "); - con->dd_printf(mem->data_format, m); - con->dd_printf(" %c\n", (m&(params[0]->value.bit.mask))?'1':'0'); + if (!fmt) + params[0]->value.bit.mem->dump(params[0]->value.bit.mem_address, + params[0]->value.bit.bitnr_high, + params[0]->value.bit.bitnr_low, + con); + else + con->dd_printf("Format options may not be specified for bits\n"); + i++; params[0]= cmdline->param(i); } @@ -244,84 +316,73 @@ syntax_error(con); return false; } - if (params[0] && - params[0]->as_string()) - { - char *s= params[0]->get_svalue(); - if (s && *s && - (strlen(s) > 1) && - (s[0]=='/')) - { - size_t i; - for (i= 0; i < strlen(s); i++) - s[i]= tolower(s[i]); - switch (tolower(s[1])) - { - case 's': fmt= df_string; break; - case 'h': fmt= df_hex; break; - case 'i': fmt= df_ihex; bpl= 32; break; - case 'b': - if (con->get_fout() && - con->get_fout()->tty) - return con->dd_printf("Error: binary format not supported on tty\n"), - false; - fmt= df_binary; - break; - } - if (strlen(s) > 2) - for (i= 2; i < strlen(s); i++) - { - switch (s[i]) - { - case 'l': fmt|= df_little; break; - case 'b': fmt|= df_big; break; - case '1': fmt|= df_1; break; - case '2': fmt|= df_2; break; - case '4': fmt|= df_4; break; - case '8': fmt|= df_8; break; - } - } - cmdline->shift(); - params[0]= cmdline->param(0); - params[1]= cmdline->param(1); - params[2]= cmdline->param(2); - params[3]= cmdline->param(3); - } - } - - enum dump_format df= (enum dump_format)fmt; - if ((cmdline->param(0)==NULL) || - (!(cmdline->param(0)->as_memory(uc)))) - { - con->dd_printf("No memory specified. Use \"info memory\" for available memories\n"); - return(false); + + if (params[0] == 0) + ; + else if (cmdline->syntax_match(uc, BIT)) { + mem= params[0]->value.bit.mem; + start= params[0]->value.bit.mem_address; + } + else if (cmdline->syntax_match(uc, BIT BIT)) { + mem= params[0]->value.bit.mem; + if (mem != params[1]->value.bit.mem) { + con->dd_printf("Start and end must be in the same address space\n"); + return false; } - if (cmdline->syntax_match(uc, MEMORY)) - { - mem= cmdline->param(0)->value.memory.memory; - mem->dump(df, -1, -1, bpl, con/*->get_fout()*/); + start= params[0]->value.bit.mem_address; + end= params[1]->value.bit.mem_address; + } + else if (cmdline->syntax_match(uc, BIT BIT NUMBER)) { + mem= params[0]->value.bit.mem; + if (mem != params[1]->value.bit.mem) { + con->dd_printf("Start and end must be in the same address space\n"); + return false; } + start= params[0]->value.bit.mem_address; + end= params[1]->value.bit.mem_address; + bpl = params[2]->value.number; + } + else if (cmdline->syntax_match(uc, MEMORY)) { + mem= params[0]->value.memory.memory; + } else if (cmdline->syntax_match(uc, MEMORY ADDRESS)) { - mem = cmdline->param(0)->value.memory.memory; - start= cmdline->param(1)->value.address; - end = start+10*8-1; - mem->dump(df, start, end, bpl, con/*->get_fout()*/); + mem = params[0]->value.memory.memory; + start= params[1]->value.address; } else if (cmdline->syntax_match(uc, MEMORY ADDRESS ADDRESS)) { - mem = cmdline->param(0)->value.memory.memory; - start= cmdline->param(1)->value.address; - end = cmdline->param(2)->value.address; - mem->dump(df, start, end, bpl, con/*->get_fout()*/); + mem = params[0]->value.memory.memory; + start= params[1]->value.address; + end = params[2]->value.address; } else if (cmdline->syntax_match(uc, MEMORY ADDRESS ADDRESS NUMBER)) { - mem = cmdline->param(0)->value.memory.memory; - start= cmdline->param(1)->value.address; - end = cmdline->param(2)->value.address; - bpl = cmdline->param(3)->value.number; - mem->dump(df, start, end, bpl, con/*->get_fout()*/); + mem = params[0]->value.memory.memory; + start= params[1]->value.address; + end = params[2]->value.address; + bpl = params[3]->value.number; } - else + else { syntax_error(con); + return false; + } + + switch (fmt) + { + case 0: // default + mem->dump(1, start, end, bpl, con); + break; + case 'b': // binary + mem->dump_b(start, end, bpl, con); + break; + case 'h': case 'x':// hex + mem->dump(0, start, end, bpl, con); + break; + case 'i': // ihex + mem->dump_i(start, end, 32, con); + break; + case 's': // string + mem->dump_s(start, end, bpl, con); + break; + } return(false);; } @@ -341,7 +402,8 @@ // class cl_cmdline *cmdline, class cl_console *con) COMMAND_DO_WORK_UC(cl_di_cmd) { - cmdline->insert_param(0, new cl_cmd_sym_arg("iram")); + cmdline->insert_param(0, new cl_cmd_sym_arg("/h")); + cmdline->insert_param(1, new cl_cmd_sym_arg("iram")); cl_dump_cmd::do_work(uc, cmdline, con); return(0); } @@ -361,7 +423,8 @@ // class cl_cmdline *cmdline, class cl_console *con) COMMAND_DO_WORK_UC(cl_dx_cmd) { - cmdline->insert_param(0, new cl_cmd_sym_arg("xram")); + cmdline->insert_param(0, new cl_cmd_sym_arg("/h")); + cmdline->insert_param(1, new cl_cmd_sym_arg("xram")); cl_dump_cmd::do_work(uc, cmdline, con); return(0); } @@ -381,7 +444,8 @@ // class cl_cmdline *cmdline, class cl_console *con) COMMAND_DO_WORK_UC(cl_dch_cmd) { - cmdline->insert_param(0, new cl_cmd_sym_arg(/*"rom"*/uc->rom->get_name("rom"))); + cmdline->insert_param(0, new cl_cmd_sym_arg("/h")); + cmdline->insert_param(1, new cl_cmd_sym_arg(/*"rom"*/uc->rom->get_name("rom"))); cl_dump_cmd::do_work(uc, cmdline, con); return(0); } @@ -401,7 +465,8 @@ // class cl_cmdline *cmdline, class cl_console *con) COMMAND_DO_WORK_UC(cl_ds_cmd) { - cmdline->insert_param(0, new cl_cmd_sym_arg("sfr")); + cmdline->insert_param(0, new cl_cmd_sym_arg("/h")); + cmdline->insert_param(1, new cl_cmd_sym_arg("sfr")); cl_dump_cmd::do_work(uc, cmdline, con); return(0); } @@ -476,6 +541,7 @@ { t_addr start, realstart; int offset= -1, dir, lines= 20; + bool run_analyze= false; class cl_cmd_arg *params[4]= { cmdline->param(0), cmdline->param(1), cmdline->param(2), @@ -483,22 +549,30 @@ start= disass_last_stop; if (params[0] == 0) ; - else if (cmdline->syntax_match(uc, ADDRESS)) { - start= params[0]->value.address; - } - else if (cmdline->syntax_match(uc, ADDRESS NUMBER)) { - start= params[0]->value.address; - offset= params[1]->value.number; - } - else if (cmdline->syntax_match(uc, ADDRESS NUMBER NUMBER)) { - start= params[0]->value.address; - offset= params[1]->value.number; - lines= params[2]->value.number; - } else { - syntax_error(con); - return(false); + char *s= (char*)(cmdline->tokens->at(0)); + if (s && *s && (s[0]=='+')) + { + run_analyze= true; + } + if (cmdline->syntax_match(uc, ADDRESS)) { + start= params[0]->value.address; + } + else if (cmdline->syntax_match(uc, ADDRESS NUMBER)) { + start= params[0]->value.address; + offset= params[1]->value.number; + } + else if (cmdline->syntax_match(uc, ADDRESS NUMBER NUMBER)) { + start= params[0]->value.address; + offset= params[1]->value.number; + lines= params[2]->value.number; + } + else + { + syntax_error(con); + return(false); + } } if (lines < 1) @@ -506,6 +580,8 @@ con->dd_printf("Error: wrong `lines' parameter\n"); return(false); } + if (run_analyze) + uc->analyze(start); if (!uc->there_is_inst()) return(false); realstart= start; @@ -620,7 +696,7 @@ while (found) { if (con->get_fout()) - mem->dump(addr, addr+len-1, 8, con/*->get_fout()*/); + mem->dump(0, addr, addr+len-1, -1, con); addr++; found= mem->search_next(case_sensitive, array, len, &addr); } @@ -763,26 +839,41 @@ COMMAND_DO_WORK_UC(cl_var_cmd) { - class cl_cmd_arg *params[4]= { cmdline->param(0), + class cl_cmd_arg *params[5]= { cmdline->param(0), cmdline->param(1), cmdline->param(2), - cmdline->param(3) }; + cmdline->param(3), + cmdline->param(4) }; class cl_memory *m= NULL; t_addr addr= -1; - int bit= -1; - class cl_var *v; - - if (cmdline->syntax_match(uc, STRING MEMORY ADDRESS NUMBER)) + int bitnr_low= -1; + int bitnr_high= -1; + + if (cmdline->syntax_match(uc, STRING MEMORY ADDRESS NUMBER NUMBER)) { m= params[1]->value.memory.memory; addr= params[2]->value.address; - bit= params[3]->value.number; + bitnr_low= bitnr_high= params[3]->value.number; + bitnr_high= params[4]->value.number; + } + else if (cmdline->syntax_match(uc, STRING MEMORY ADDRESS NUMBER)) + { + m= params[1]->value.memory.memory; + addr= params[2]->value.address; + bitnr_low= bitnr_high= params[3]->value.number; } else if (cmdline->syntax_match(uc, STRING MEMORY ADDRESS)) { m= params[1]->value.memory.memory; addr= params[2]->value.address; } + else if (cmdline->syntax_match(uc, STRING BIT)) + { + m= params[1]->value.bit.mem; + addr= params[1]->value.bit.mem_address; + bitnr_low= params[1]->value.bit.bitnr_low; + bitnr_high= params[1]->value.bit.bitnr_high; + } else if (cmdline->syntax_match(uc, STRING CELL)) { m= uc->address_space(params[1]->value.cell, &addr); @@ -796,10 +887,6 @@ if (!valid_sym_name(params[0]->value.string.string)) return con->dd_printf("name is invalid\n"), false; - if ((bit >= 0) && - (bit >= (int)sizeof(t_mem)*8)) - return con->dd_printf("max bit number is %d\n", (int)sizeof(t_mem)*8), - false; if (m) if (!m->is_address_space()) @@ -809,41 +896,32 @@ if (!m->valid_address(addr)) return con->dd_printf("invalid address\n"), false; - if (bit >= 0) - if (bit >= 32) - return con->dd_printf("invalid bit number\n"), - false; - - if (uc->symbol2address(params[0]->value.string.string, - (class cl_address_space **)NULL, - (t_addr*)NULL)) - return con->dd_printf("already exists\n"), + if (bitnr_low >= (int)sizeof(t_mem)*8 || + bitnr_high >= (int)sizeof(t_mem)*8) + return con->dd_printf("max bit number is %d\n", (int)sizeof(t_mem)*8), false; - + if (m) - { - v= new cl_var(params[0]->value.string.string, - (cl_address_space*)m, addr, chars(""), bit); - v->init(); - uc->vars->add(v); - } + uc->vars->add(params[0]->value.string.string, m, addr, bitnr_high, bitnr_low, ""); else { - if (bit < 0) + if (bitnr_low < 0) { if (addr < 0) { - if (!uc->variables->search_cell(CELL_VAR, false, &addr)) + t_index i; + for (addr= 0; addr < uc->variables->get_size(); addr++) + if (!uc->vars->by_addr.search(uc->variables, addr, i)) + break; + if (addr == uc->variables->get_size()) return con->dd_printf("no space\n"), false; } if (!uc->variables->valid_address(addr)) return con->dd_printf("out of range\n"), false; - v= new cl_var(params[0]->value.string.string, - uc->variables, addr, chars(""), bit); - v->init(); - uc->vars->add(v); + uc->vars->add(params[0]->value.string.string, + uc->variables, addr, bitnr_high, bitnr_low, ""); } else { @@ -858,4 +936,63 @@ "Create new variable", "long help of var") +/* + * Command: rmvar + *---------------------------------------------------------------------------- + */ + +COMMAND_DO_WORK_UC(cl_rmvar_cmd) +{ + if (cmdline->syntax_match(uc, STRING)) + uc->vars->del(cmdline->param(0)->value.string.string); + else + return syntax_error(con), false; + + return false; +} + +CMDHELP(cl_rmvar_cmd, + "rmvar name", + "Remove variable", + "Deletes the name variable") + +/* + * Command: analyze + *---------------------------------------------------------------------------- + */ + +COMMAND_DO_WORK_UC(cl_analyze_cmd) +{ + if (cmdline->nuof_params() == 0) + uc->analyze_init(); + else + for (int i = 0; i < cmdline->nuof_params(); i++) + { + class cl_cmd_arg *param = cmdline->param(i); + if (param) + { + if (param->as_bit(uc)) + { + if (param->value.bit.mem == uc->rom) + uc->analyze(param->value.bit.mem_address); + else + { + con->dd_printf("%s[", param->value.bit.mem->get_name()); + con->dd_printf(param->value.bit.mem->addr_format, param->value.bit.mem_address); + con->dd_printf("]: addresses to analyze must be in %s\n", uc->rom->get_name()); + } + } + else + con->dd_printf("%s cannot be interpreted as a rom address\n", cmdline->tokens->at(i)); + } + } + + return false; +} + +CMDHELP(cl_analyze_cmd, + "analyze [addr...]", + "Analyze reachable code globally or from the address(es) given", + "long help of analyze") + /* End of cmd.src/cmd_uc.cc */ diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/cmd.src/cmd_uccl.h sdcc-4.2.0+dfsg/sim/ucsim/cmd.src/cmd_uccl.h --- sdcc-4.0.0+dfsg/sim/ucsim/cmd.src/cmd_uccl.h 2019-05-18 12:12:53.000000000 +0000 +++ sdcc-4.2.0+dfsg/sim/ucsim/cmd.src/cmd_uccl.h 2022-01-24 11:09:43.000000000 +0000 @@ -35,6 +35,7 @@ COMMAND_ON(uc,cl_dl_cmd); COMMAND_ON(uc,cl_pc_cmd); COMMAND_ON(uc,cl_reset_cmd); +COMMAND_ON(uc,cl_tick_cmd); COMMAND_ON(uc,cl_dump_cmd); COMMAND_ANCESTOR_ON(uc,cl_di_cmd,cl_dump_cmd); COMMAND_ANCESTOR_ON(uc,cl_dx_cmd,cl_dump_cmd); @@ -54,6 +55,8 @@ COMMAND_ON(uc,cl_hole_cmd); COMMAND_ON(uc,cl_var_cmd); +COMMAND_ON(uc,cl_rmvar_cmd); +COMMAND_ON(uc,cl_analyze_cmd); #endif diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/cmd.src/cmdutil.cc sdcc-4.2.0+dfsg/sim/ucsim/cmd.src/cmdutil.cc --- sdcc-4.0.0+dfsg/sim/ucsim/cmd.src/cmdutil.cc 2017-10-27 11:53:14.000000000 +0000 +++ sdcc-4.2.0+dfsg/sim/ucsim/cmd.src/cmdutil.cc 2022-01-26 16:35:40.000000000 +0000 @@ -25,23 +25,19 @@ 02111-1307, USA. */ /*@1@*/ -#include "ddconfig.h" +//#include "ddconfig.h" #include #include #include -#include -#include -#include "i_string.h" - -#include "stypes.h" -#include "globals.h" -#include "uccl.h" +#include +#include + #include "cmdutil.h" /* - * Processing escape sequencies in a string + * Processing escape sequences in a string */ char * @@ -103,44 +99,6 @@ } - -extern "C" int vasprintf(char **strp, const char *format, va_list ap); -extern "C" int vsnprintf(char *str, size_t size,const char *format,va_list ap); - -int -cmd_vfprintf(FILE *f, char *format, va_list ap) -{ - int ret, i; - if (!f) - return(0); -#ifdef HAVE_VASPRINTF - char *msg= NULL; - i= vasprintf(&msg, format, ap); - if (i < 0) - ; - ret= fprintf(f, "%s", msg); - free(msg); -#else - char msg[80*25]; - i= vsnprintf(msg, 80*25, format, ap); - if (i < 0) - ; - ret= fprintf(f, "%s", msg); -#endif - fflush(f); - return(ret); -} - -int -cmd_fprintf(FILE *f, char *format, ...) -{ - va_list ap; - va_start(ap, format); - int ret= cmd_vfprintf(f, format, ap); - va_end(ap); - return(ret); -} - int bool_name(char *s, int *val) { diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/cmd.src/cmdutil.h sdcc-4.2.0+dfsg/sim/ucsim/cmd.src/cmdutil.h --- sdcc-4.0.0+dfsg/sim/ucsim/cmd.src/cmdutil.h 2016-11-05 14:33:30.000000000 +0000 +++ sdcc-4.2.0+dfsg/sim/ucsim/cmd.src/cmdutil.h 2021-01-02 20:38:26.000000000 +0000 @@ -28,17 +28,14 @@ #ifndef CMD_CMDUTIL_HEADER #define CMD_CMDUTIL_HEADER +#include "ddconfig.h" + #ifdef SOCKET_AVAIL # include HEADER_SOCKET #endif -#include "ddconfig.h" - extern char *proc_escape(char *string, int *len); -extern int cmd_vfprintf(FILE *f, char *format, va_list ap); -extern int cmd_fprintf(FILE *f, char *format, ...); - extern int bool_name(char *s, int *val); diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/cmd.src/command.cc sdcc-4.2.0+dfsg/sim/ucsim/cmd.src/command.cc --- sdcc-4.0.0+dfsg/sim/ucsim/cmd.src/command.cc 2019-05-30 07:36:35.000000000 +0000 +++ sdcc-4.2.0+dfsg/sim/ucsim/cmd.src/command.cc 2022-01-24 11:09:43.000000000 +0000 @@ -25,20 +25,24 @@ 02111-1307, USA. */ /*@1@*/ -#include "ddconfig.h" +//#include "ddconfig.h" +#include #include -#include -#include "i_string.h" +//#include +#include +#include + +//#include "i_string.h" // prj -#include "fiocl.h" -#include "utils.h" +//#include "fiocl.h" +//#include "utils.h" #include "appcl.h" // local, cmd #include "commandcl.h" -#include "argcl.h" +//#include "argcl.h" /* @@ -47,7 +51,7 @@ */ cl_cmdline::cl_cmdline(class cl_app *the_app, - char *acmd, class cl_console_base *acon): + const char *acmd, class cl_console_base *acon): cl_base() { app= the_app; @@ -157,10 +161,17 @@ strncpy(param_str, start, i); param_str[i]= '\0'; tokens->add(strdup(param_str)); - if ((dot= strchr(param_str, '.')) != NULL) + if ((dot= strchr(param_str, '[')) != NULL) + { + char *p; + for (p= dot+1; *p && *p != ']' && *p != ':'; p++); + if (*p == ':') + split_out_bit(dot, param_str); + else + split_out_array(dot, param_str); + } + else if ((dot= strchr(param_str, '.')) != NULL && dot != param_str) split_out_bit(dot, param_str); - else if ((dot= strchr(param_str, '[')) != NULL) - split_out_array(dot, param_str); else if (param_str[0] == '0' && param_str[1] == 'b') { long n= 0; @@ -231,71 +242,101 @@ void cl_cmdline::split_out_output_redirection(char **_start, char **_end) { - char *start= *_start, *end/*= *_end*/; - int i; + char *start= *_start; + char *end; + int j; char mode[2]; mode[0]= 'w'; mode[1]= '\0'; start++; - i= strcspn(start, " \t\v\r,"); - end= start+i; - char *param_str= (char *)malloc(i+1); - char *n= param_str; - strncpy(param_str, start, i); - param_str[i]= '\0'; - if (param_str && - param_str[0] == '>') + if (*start=='>') { - n++; mode[0]= 'a'; + start++; } - tokens->add(strdup(n)); - con->redirect(n, mode); - free(param_str); + j= token_length(start); + end= start+j; + con->redirect(get_token(start).c_str(), mode); *_start= start; *_end= end; } void -cl_cmdline::split_out_bit(char *dot, char *param_str) +cl_cmdline::add_bit(char *dot, char *colon, class cl_cmd_arg *sfr) { - class cl_cmd_arg *sfr, *bit; + class cl_cmd_arg *bit_low = NULL, *bit_high = NULL; - *dot= '\0'; - dot++; - if (strchr("0123456789", *param_str) != NULL) - { - sfr= new cl_cmd_int_arg((long)strtol(param_str, 0, 0)); - sfr->init(); - } - else + if (colon) { - sfr= new cl_cmd_sym_arg(param_str); - sfr->init(); + *(colon++) = '\0'; + + char *end = strchr(colon, ']'); + + if (end) + *end = '\0'; + else + { + con->dd_printf("Incomplete bit address\n"); + delete sfr; + return; + } } + if (*dot == '\0') { - bit= 0; - con->dd_printf("Uncomplete bit address\n"); + con->dd_printf("Incomplete bit address\n"); delete sfr; + return; } - else + + while (dot) { + bit_high= bit_low; + if (strchr("0123456789", *dot) != NULL) { - bit= new cl_cmd_int_arg((long)strtol(dot, 0, 0)); - bit->init(); + bit_low= new cl_cmd_int_arg((long)strtol(dot, 0, 0)); + bit_low->init(); } else { - bit= new cl_cmd_sym_arg(dot); - bit->init(); + bit_low= new cl_cmd_sym_arg(dot); + bit_low->init(); } - class cl_cmd_arg *arg; - params->add(arg= new cl_cmd_bit_arg(sfr, bit)); - arg->init(); + + dot= colon; + colon= NULL; + } + + class cl_cmd_arg *arg; + params->add(arg= new cl_cmd_bit_arg(sfr, bit_low, bit_high)); + arg->init(); +} + +void +cl_cmdline::split_out_bit(char *dot, char *param_str) +{ + char *colon = NULL; + class cl_cmd_arg *sfr; + + if (*dot == '[') + colon = strchr(dot+1, ':'); + + *(dot++) = '\0'; + + if (strchr("0123456789", *param_str) != NULL) + { + sfr= new cl_cmd_int_arg((long)strtol(param_str, 0, 0)); + sfr->init(); + } + else + { + sfr= new cl_cmd_sym_arg(param_str); + sfr->init(); } + + add_bit(dot, colon, sfr); } void @@ -318,45 +359,122 @@ if (*dot == '\0') { aname= 0; - con->dd_printf("Uncomplete array\n"); + con->dd_printf("Incomplete array\n"); } else { - char *p; - p= dot + strlen(dot) - 1; - while (p > dot && - *p != ']') - { - *p= '\0'; - p--; - } - if (*p == ']') - *p= '\0'; - if (strlen(dot) == 0) - { - con->dd_printf("Uncomplete array index\n"); - delete aname; - } - else - { - if (strchr("0123456789", *dot) != NULL) - { - aindex= new cl_cmd_int_arg((long)strtol(dot, 0, 0)); - aindex->init(); - } - else - { - aindex= new cl_cmd_sym_arg(dot); - aindex->init(); - } - class cl_cmd_arg *arg; - params->add(arg= new cl_cmd_array_arg(aname, aindex)); - arg->init(); - } + char *p = strchr(dot, ']'); + if (!p) + { + con->dd_printf("Missing ']' in array index\n"); + delete aname; + } + else + { + *(p++)= '\0'; + if (strlen(dot) == 0) + { + con->dd_printf("Incomplete array index\n"); + delete aname; + } + else + { + if (strchr("0123456789", *dot) != NULL) + { + aindex= new cl_cmd_int_arg((long)strtol(dot, 0, 0)); + aindex->init(); + } + else + { + aindex= new cl_cmd_sym_arg(dot); + aindex->init(); + } + class cl_cmd_arg *arg= new cl_cmd_array_arg(aname, aindex); + arg->init(); + if (*p == '.' || *p == '[') + add_bit(p+1, strchr(p+1, ':'), arg); + else + params->add(arg); + } + } } } int +cl_cmdline::token_length(char *start) +{ + if (start==NULL || + *start=='\0') + return 0; + if (*start == '\"') + { + int i; + char c; + for (i=1; start[i]!=0 && start[i]!='\"'; i++) + { + c= start[i]; + if (c == '\\') + i+= 2; + } + return i+1; + } + else + return strcspn(start, " \t\v\r,;"); +} + +chars +cl_cmdline::get_token(char *start) +{ + int i; + char c; + chars cs= chars(); + if (start==NULL || + *start=='\0') + return cs; + if (*start == '\"') + { + for (i=1; start[i]!=0 && start[i]!='\"'; i++) + { + c= start[i]; + if (c == '\\') + { + i++; + if (start[i]) + { + switch (start[i]) + { + case 'a': cs+= '\a'; break; + case 'b': cs+= '\b'; break; + case 'e': cs+= '\x1b'; break; + case 'f': cs+= '\f'; break; + case 'n': cs+= '\n'; break; + case 'r': cs+= '\r'; break; + case 't': cs+= '\t'; break; + case 'v': cs+= '\v'; break; + case '\'': cs+= '\''; break; + case '\"': cs+= '\"'; break; + default: + cs+= start[i]; + break; + } + } + //i++; + } + else + cs+= c; + } + return cs; + } + else + { + int l= strcspn(start, " \t\v\r,;"); + for (i=0; ivalue.data; len++; } @@ -630,7 +758,7 @@ { for (i= 0; i < names->count; i++) { - char *n= (char*)(names->at(i)); + const char *n= names->at(i); if (strcmp(aname, n) == 0) return(1); } @@ -639,7 +767,7 @@ { for (i= 0; i < names->count; i++) { - char *n= (char*)(names->at(i)); + const char *n= names->at(i); if (strstr(n, aname) == n) return(1); } @@ -701,7 +829,7 @@ cl_cmd::do_work(class cl_cmdline *cmdline, class cl_console_base *con) { con->dd_printf("Command \"%s\" does nothing.\n", - (char*)(names->at(0))); + names->at(0)); return(0); } @@ -710,7 +838,7 @@ class cl_cmdline *cmdline, class cl_console_base *con) { con->dd_printf("Command \"%s\" does nothing on application.\n", - (char*)(names->at(0))); + names->at(0)); return(0); } @@ -719,7 +847,7 @@ class cl_cmdline *cmdline, class cl_console_base *con) { con->dd_printf("Command \"%s\" does nothing on simulator.\n", - (char*)(names->at(0))); + names->at(0)); return(0); } @@ -728,7 +856,7 @@ class cl_cmdline *cmdline, class cl_console_base *con) { con->dd_printf("Command \"%s\" does nothing on microcontroller.\n", - (char*)(names->at(0))); + names->at(0)); return(0); } @@ -741,7 +869,7 @@ return; if (usage_help.nempty()) - con->dd_printf("%s", (char*)usage_help); + con->dd_printf("%s", usage_help.c_str()); if (l > 19) { con->dd_printf("\n"); @@ -754,10 +882,10 @@ } if (short_help.nempty()) { - con->dd_printf("%s", (char*)short_help); + con->dd_printf("%s", short_help.c_str()); } else - con->dd_printf("%s", (char*)(names->at(0))); + con->dd_printf("%s", names->at(0)); con->dd_printf("\n"); } @@ -903,11 +1031,11 @@ return(cmd->work(app, cmdline, con)); int i; con->dd_printf("\"%s\" must be followed by the name of a subcommand\n" - "List of subcommands:\n", (char*)(names->at(0))); + "List of subcommands:\n", names->at(0)); for (i= 0; i < commands->count; i++) { cmd= (class cl_cmd *)(commands->at(i)); - //con->dd_printf("%s\n", (char*)cmd->short_help); + //con->dd_printf("%s\n", cmd->short_help.c_str()); cmd->print_short(con); } return(0); @@ -915,7 +1043,7 @@ if ((cmd= commands->get_cmd(cmdline, con->is_interactive())) == NULL) { con->dd_printf("Undefined subcommand: \"%s\". Try \"help %s\".\n", - cmdline->get_name(), (char*)(names->at(0))); + cmdline->get_name(), names->at(0)); return(0); } return(cmd->work(app, cmdline, con)); diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/cmd.src/commandcl.h sdcc-4.2.0+dfsg/sim/ucsim/cmd.src/commandcl.h --- sdcc-4.0.0+dfsg/sim/ucsim/cmd.src/commandcl.h 2019-03-24 10:01:12.000000000 +0000 +++ sdcc-4.2.0+dfsg/sim/ucsim/cmd.src/commandcl.h 2021-04-01 17:52:48.000000000 +0000 @@ -62,15 +62,18 @@ class cl_console_base *con; public: - cl_cmdline(class cl_app *the_app, char *acmd, class cl_console_base *acon); + cl_cmdline(class cl_app *the_app, const char *acmd, class cl_console_base *acon); virtual ~cl_cmdline(void); virtual int init(void); private: virtual void split_out_string(char **_start, char **_end); virtual void split_out_output_redirection(char **_start, char **_end); + virtual void add_bit(char *dot, char *colon, class cl_cmd_arg *sfr); virtual void split_out_bit(char *dot, char *param_str); virtual void split_out_array(char *dot, char *param_str); + virtual int token_length(char *start); + virtual chars get_token(char *start); public: virtual int split(void); virtual int shift(void); @@ -231,9 +234,9 @@ void \ CLASS_NAME::set_help(void) \ { \ - usage_help=(char*)USAGE_HLP; \ - short_help=(char*)SHORT_HLP; \ - long_help=(char*)LONG_HLP; \ + usage_help=USAGE_HLP; \ + short_help=SHORT_HLP; \ + long_help=LONG_HLP; \ } // Command set is list of cl_cmd objects diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/cmd.src/Makefile.in sdcc-4.2.0+dfsg/sim/ucsim/cmd.src/Makefile.in --- sdcc-4.0.0+dfsg/sim/ucsim/cmd.src/Makefile.in 2018-12-18 08:22:48.000000000 +0000 +++ sdcc-4.2.0+dfsg/sim/ucsim/cmd.src/Makefile.in 2022-01-13 08:20:03.000000000 +0000 @@ -22,10 +22,11 @@ top_srcdir = @top_srcdir@ DEFS = $(subs -DHAVE_CONFIG_H,,@DEFS@) +PICOPT = @PICOPT@ CPPFLAGS = @CPPFLAGS@ -I$(srcdir) -I$(top_srcdir) -I$(top_builddir) \ -I$(top_srcdir)/sim.src -I$(top_srcdir)/gui.src -CFLAGS = @CFLAGS@ @WALL_FLAG@ -CXXFLAGS = @CXXFLAGS@ @WALL_FLAG@ +CFLAGS = @WALL_FLAG@ @CFLAGS@ +CXXFLAGS = @WALL_FLAG@ @CXXFLAGS@ $(PICOPT) WINSOCK_AVAIL = @WINSOCK_AVAIL@ prefix = @prefix@ @@ -81,6 +82,8 @@ test: +baseline: + # Performing installation test # ---------------------------- diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/cmd.src/newcmd.cc sdcc-4.2.0+dfsg/sim/ucsim/cmd.src/newcmd.cc --- sdcc-4.0.0+dfsg/sim/ucsim/cmd.src/newcmd.cc 2019-07-02 08:44:01.000000000 +0000 +++ sdcc-4.2.0+dfsg/sim/ucsim/cmd.src/newcmd.cc 2022-02-08 21:21:05.000000000 +0000 @@ -26,30 +26,33 @@ 02111-1307, USA. */ /*@1@*/ -#include "ddconfig.h" +//#include "ddconfig.h" #include -#include +//#include #include #include #include -#include "i_string.h" +#include +#include + +//#include "i_string.h" //#include "cmdlexcl.h" // prj #include "globals.h" #include "utils.h" -#include "fiocl.h" +//#include "fiocl.h" // sim -#include "simcl.h" -#include "argcl.h" -#include "appcl.h" +//#include "simcl.h" +//#include "argcl.h" +//#include "appcl.h" // local #include "newcmdcl.h" -#include "cmdutil.h" +//#include "cmdutil.h" /* @@ -171,12 +174,14 @@ { if (!(flags & CONS_NOWELCOME)) { - dd_printf("uCsim %s, Copyright (C) 1997 Daniel Drotos.\n" + dd_printf("uCsim%s, Copyright (C) %s Daniel Drotos.\n" "uCsim comes with ABSOLUTELY NO WARRANTY; for details type " "`show w'.\n" "This is free software, and you are welcome to redistribute it\n" "under certain conditions; type `show c' for details.\n", - VERSIONSTR); + (application->quiet)?"":(" " VERSIONSTR), + (application->quiet)?"":"1997" + ); } } @@ -206,6 +211,67 @@ } } +void +cl_console_base::print_expr_result(t_mem val, const char *fmt) +{ + class cl_console_base *con= this; + t_mem v= val; + if (fmt == NULL) + { + class cl_option *o= application->options->get_option("expression_format"); + char *cc= NULL; + if (o) + { + o->get_value(&cc); + fmt= cc; + } + } + if (fmt) + { + int i, fmt_len= strlen(fmt); + for (i= 0; i < fmt_len; i++) + { + switch (fmt[i]) + { + case 'x': con->dd_printf("%x\n", MU(v)); break; + case 'X': con->dd_printf("0x%x\n", MU(v)); break; + case '$': con->dd_printf("$%x\n", MU(v)); break; + case '0': con->dd_printf("0x%08x\n", MU32(v)); break; + case 'd': con->dd_printf("%d\n", MI(v)); break; + case 'o': con->dd_printf("%o\n", MU(v)); break; + case 'u': con->dd_printf("%u\n", MU(v)); break; + case 'b': con->dd_printf("%s\n", cbin(v,8*sizeof(v)).c_str()); break; + case 'B': con->dd_printf("%d\n", (v)?1:0); break; + case 'L': con->dd_printf("%c\n", (v)?'T':'F'); break; + case 'c': + if ((MU(v) < 0x100) && isprint(MI(v))) + con->dd_printf("'%c'",MI(v)); + else + { + switch (MI(v)) + { + case '\a': con->dd_printf("'\\a'"); break; + case '\b': con->dd_printf("'\\b'"); break; + case '\e': con->dd_printf("'\\e'"); break; + case '\f': con->dd_printf("'\\f'"); break; + case '\n': con->dd_printf("'\\n'"); break; + case '\r': con->dd_printf("'\\r'"); break; + case '\t': con->dd_printf("'\\t'"); break; + case '\v': con->dd_printf("'\\v'"); break; + default: + con->dd_printf("'\\%03o'",MI(v)); + break; + } + } + con->dd_printf("\n"); + break; + } + } + } + else + con->dd_printf("%d\n", MI(v)); +} + int cl_console_base::dd_printf(const char *format, ...) { @@ -237,11 +303,11 @@ ) bw= true; - o= application->options->get_option((char*)chars("", "color_%s", color_name)); + o= application->options->get_option(chars("", "color_%s", color_name)); cc= NULL; if (o) o->get_value(&cc); cce= colopt2ansiseq(cc); - if (!bw) dd_printf("\033[0m%s", (char*)cce); + if (!bw) dd_printf("\033[0m%s", cce.c_str()); va_start(ap, format); ret= cmd_do_print(format, ap); @@ -260,7 +326,7 @@ chars cce= ""; class cl_f *fo= get_fout(); class cl_option *o= application->options->get_option("black_and_white"); - if (o) o->get_value(&cc); + if (o) o->get_value(&bw); if (!fo || (fo && @@ -269,7 +335,7 @@ ) return cce; - o= application->options->get_option((char*)chars("", "color_%s", color_name)); + o= application->options->get_option(chars("", "color_%s", color_name)); cc= NULL; if (o) o->get_value(&cc); if (add_reset) @@ -283,7 +349,7 @@ void cl_console_base::dd_color(const char *color_name) { - dd_printf("%s", (char*)(get_color_ansiseq(color_name, true))); + dd_printf("%s", get_color_ansiseq(color_name, true).c_str()); } int @@ -354,7 +420,7 @@ { return 0; } - ret= fo->vprintf((char*)format, ap); + ret= fo->vprintf(format, ap); //fo->flush(); return ret; } @@ -379,7 +445,7 @@ ) bw= true; - o= application->options->get_option((char*)chars("", "color_%s", color_name)); + o= application->options->get_option(chars("", "color_%s", color_name)); cc= NULL; if (o) o->get_value(&cc); cce= colopt2ansiseq(cc); @@ -392,8 +458,8 @@ { return 0; } - if (!bw) fo->prntf("\033[0m%s", (char*)cce); - ret= fo->vprintf((char*)format, ap); + if (!bw) fo->prntf("\033[0m%s", cce.c_str()); + ret= fo->vprintf(format, ap); if (!bw) fo->prntf("\033[0m"); //fo->flush(); return ret; @@ -565,8 +631,8 @@ { int retval= 0, i, do_print_prompt= 1; - un_redirect(); - char *cmdstr; + //un_redirect(); + const char *cmdstr; i= read_line(); if (i < 0) { @@ -576,7 +642,7 @@ return 0; cmdstr= lbuf; if (cmdstr==NULL) - cmdstr= (char*)""; + cmdstr= ""; if (is_frozen()) { application->get_sim()->stop(resUSER); @@ -596,6 +662,7 @@ dd_printf("%s\n", cmdstr); do { + un_redirect(); cmdline= new cl_cmdline(app, cmdstr, this); cmdline->init(); if (cmdline->repeat() && @@ -624,8 +691,9 @@ char *e= cmdline->cmd; if (strlen(e) > 0) { - long l= application->eval(e); - dd_cprintf("result", "%ld\n", l); + t_mem l= application->eval(e); + dd_color("result"); + print_expr_result(l, NULL); } } if (get_fin() != NULL) @@ -860,19 +928,11 @@ cl_commander_base::debug(const char *format, ...) { va_list ap; - int i, ret= 0; - for (i= 0; i < cons->count; i++) - { - class cl_console_base *c= (class cl_console_base*)(cons->at(i)); - if (c->get_flag(CONS_DEBUG)) - { - va_start(ap, format); - ret= c->cmd_do_cprint("debug", format, ap); - va_end(ap); - } - } - return(ret); + va_start(ap, format); + int ret = debug(format, ap); + va_end(ap); + return ret; } int @@ -883,9 +943,17 @@ for (i= 0; i < cons->count; i++) { class cl_console_base *c= (class cl_console_base*)(cons->at(i)); - if (c->get_flag(CONS_DEBUG)) + if (c->get_flag(CONS_DEBUG) && !c->get_flag(CONS_INACTIVE)) { - ret= c->cmd_do_cprint("debug", format, ap); + va_list aq; +#ifdef va_copy + va_copy(aq, ap); + ret= c->cmd_do_cprint("debug", format, aq); + va_end(aq); +#else + memcpy(&aq, &ap, sizeof(va_list)); + ret= c->cmd_do_cprint("debug", format, aq); +#endif } } return(ret); @@ -921,7 +989,14 @@ class cl_console_base * cl_commander_base::exec_on(class cl_console_base *cons, char *file_name) { - if (!cons || !file_name || !fopen(file_name, "r")) + FILE *dummy; + bool oped= false; + if ((file_name == NULL) || (*file_name == 0)) + return 0; + dummy= fopen(file_name, "r"); + if (dummy) + oped= true, fclose(dummy); + if (!cons || !oped) return 0; class cl_console_base *subcon = cons->clone_for_exec(file_name); diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/cmd.src/newcmdcl.h sdcc-4.2.0+dfsg/sim/ucsim/cmd.src/newcmdcl.h --- sdcc-4.0.0+dfsg/sim/ucsim/cmd.src/newcmdcl.h 2019-07-02 08:44:01.000000000 +0000 +++ sdcc-4.2.0+dfsg/sim/ucsim/cmd.src/newcmdcl.h 2021-10-29 17:39:15.000000000 +0000 @@ -126,7 +126,7 @@ virtual class cl_console_base *clone_for_exec(char *fin) = 0; - virtual void redirect(char *fname, char *mode) = 0; + virtual void redirect(const char *fname, const char *mode) = 0; virtual void un_redirect(void) = 0; virtual bool is_tty(void) const = 0; virtual bool is_eof(void) const = 0; @@ -148,6 +148,7 @@ virtual bool need_check(void) { return false; } virtual void print_prompt(void); + virtual void print_expr_result(t_mem val, const char *fmt); virtual int dd_printf(const char *format, ...); virtual int dd_cprintf(const char *color_name, const char *format, ...); virtual chars get_color_ansiseq(const char *color_name, bool add_reset= false); @@ -178,7 +179,7 @@ virtual void set_prompt(char *p); virtual bool input_active(void) const; - //virtual bool accept_last(void) { return /*is_tty() ? DD_TRUE : DD_FALSE;*/flags&CONS_INTERACTIVE; } + //virtual bool accept_last(void) { return /*is_tty() ? true : false;*/flags&CONS_INTERACTIVE; } virtual bool prevent_quit(void) { return (prev_quit>=0)?prev_quit:true; } private: @@ -205,7 +206,7 @@ virtual class cl_console_base *clone_for_exec(char *fin) { return NULL; } - virtual void redirect(char *fname, char *mode) {} + virtual void redirect(const char *fname, const char *mode) {} virtual void un_redirect(void) {} virtual bool is_tty(void) const { return false; } virtual bool is_eof(void) const { return false; } diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/cmd.src/newcmdposix.cc sdcc-4.2.0+dfsg/sim/ucsim/cmd.src/newcmdposix.cc --- sdcc-4.0.0+dfsg/sim/ucsim/cmd.src/newcmdposix.cc 2019-05-17 08:53:56.000000000 +0000 +++ sdcc-4.2.0+dfsg/sim/ucsim/cmd.src/newcmdposix.cc 2020-08-25 09:31:26.000000000 +0000 @@ -26,27 +26,28 @@ 02111-1307, USA. */ /*@1@*/ -#include "ddconfig.h" +//#include "ddconfig.h" #include #include -#include +//#include #include -#include -#include -#include "i_string.h" +//#include +//#include +#include +#include + +//#include "i_string.h" // prj #include "globals.h" -#include "utils.h" +//#include "utils.h" // sim -#include "simcl.h" -#include "argcl.h" -#include "appcl.h" +//#include "simcl.h" +//#include "argcl.h" // local -#include "newcmdposixcl.h" /* @@ -60,12 +61,12 @@ fin= 0; if (_fin) { - fin= mk_io(_fin, cchars("r")); + fin= mk_io(_fin, "r"); } fout= 0; if (_fout) { - fout= mk_io(_fout, cchars("w")); + fout= mk_io(_fout, "w"); } prompt= 0; set_flag(~CONS_NONE, false); @@ -76,7 +77,7 @@ fin->cooked(); } else - ; + {} frout= 0; id= 0; lines_printed= new cl_ustrings(100, 100, "console_cache"); @@ -96,7 +97,7 @@ fin->cooked(); } else - ; + {} frout= 0; id= 0; lines_printed= new cl_ustrings(100, 100, "console_cache"); @@ -214,7 +215,7 @@ */ void -cl_console::redirect(char *fname, char *mode) +cl_console::redirect(const char *fname, const char *mode) { frout= mk_io(fname, mode); set_flag(CONS_REDIRECTED, true); @@ -244,7 +245,7 @@ { ret= fin->input_avail(); if (ret) - ; + {} } return ret; } @@ -289,7 +290,7 @@ do { if (startup_command.nempty()) { - char *s= startup_command; + const char *s= startup_command; b[0]= s[0]; startup_command= &s[1]; i= 1; @@ -504,8 +505,8 @@ if (strcmp(cn, "-") == 0) { class cl_f *in, *out; - in= cp_io(fileno(stdin), cchars("r")); - out= cp_io(fileno(stdout), cchars("w")); + in= cp_io(fileno(stdin), "r"); + out= cp_io(fileno(stdout), "w"); in->interactive(out); add_console(con= new cl_console(in, out, app)); config_console= exec_on(con, Config); @@ -527,8 +528,8 @@ if (cons->get_count() == ccnt) { class cl_f *in, *out; - in= cp_io(fileno(stdin), cchars("r")); - out= cp_io(fileno(stdout), cchars("w")); + in= cp_io(fileno(stdin), "r"); + out= cp_io(fileno(stdout), "w"); in->interactive(out); add_console(con= new cl_console(in, out, app)); config_console= exec_on(con, Config); diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/cmd.src/newcmdposixcl.h sdcc-4.2.0+dfsg/sim/ucsim/cmd.src/newcmdposixcl.h --- sdcc-4.0.0+dfsg/sim/ucsim/cmd.src/newcmdposixcl.h 2019-04-02 10:46:33.000000000 +0000 +++ sdcc-4.2.0+dfsg/sim/ucsim/cmd.src/newcmdposixcl.h 2020-08-22 10:25:08.000000000 +0000 @@ -57,7 +57,7 @@ virtual void close_files(bool close_in, bool close_out); virtual void replace_files(bool close_old, cl_f *new_in, cl_f *new_out); - virtual void redirect(char *fname, char *mode); + virtual void redirect(const char *fname, const char *mode); virtual void un_redirect(void); virtual UCSOCKET_T get_in_fd(void) { return(fin ? (fin->file_id) : -1); } virtual bool is_tty(void) const { return fin && (fin->tty); } diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/conf sdcc-4.2.0+dfsg/sim/ucsim/conf --- sdcc-4.0.0+dfsg/sim/ucsim/conf 2019-02-26 14:40:39.000000000 +0000 +++ sdcc-4.2.0+dfsg/sim/ucsim/conf 2021-11-21 14:19:39.000000000 +0000 @@ -1,10 +1,10 @@ #!/bin/bash -[ -f Makefile ] && make distclean +[ -f Makefile ] && ./distclean.sh TARGET=linux -PREFIX="${HOME}/local" +PREFIX="${HOME}/dani" DD_HOSTS="p4 anb anb1 render mms box mazsola v3" PERF_FLAG="" OPT_FLAG="-O2" @@ -16,7 +16,7 @@ PERF_FLAG="-pg" ;; -d) - OPT_FLAG="-O0" + OPT_FLAG="-O0 -DDEVEL" ;; -c) COMP="yes" @@ -45,17 +45,12 @@ case $TARGET in linux|l) if echo $DD_HOSTS|grep $(hostname) >/dev/null 2>&1 ; then - export PREFIX='/usr/local' + : fi ./configure --prefix=${PREFIX} \ - --disable-dlso \ - --enable-serio \ - --enable-avr-port \ - --enable-z80-port \ - --enable-xa-port \ - --enable-stm8-port \ - --enable-st7-port \ - "$@" + --disable-dlso \ + --enable-m68hc12-port \ + "$@" #--enable-ucsim ;; mingw|win|w) @@ -68,18 +63,12 @@ export CXX=i686-w64-mingw32-g++ export HOST_OPT='--host=i686-w64-mingw32' export LDFLAGS='-static-libgcc -static-libstdc++' - export PREFIX='/usr/local' fi echo CC=$CC CXX=$CXX HOST=$HOST_OPT ./configure --prefix=${PREFIX} \ - --disable-dlso \ - --disable-serio \ - --enable-avr-port \ - --enable-z80-port \ - --enable-xa-port \ - --enable-stm8-port \ - --enable-st7-port \ - $HOST_OPT "$@" + --disable-dlso \ + --enable-m68hc12-port \ + $HOST_OPT "$@" #--enable-ucsim ;; w64) @@ -87,17 +76,11 @@ export CXX=x86_64-w64-mingw32-g++ export HOST_OPT='--host=x86_64-w64-mingw32' export LDFLAGS='-static-libgcc -static-libstdc++' - export PREFIX='/usr/local' echo CC=$CC CXX=$CXX HOST=$HOST_OPT ./configure --prefix=${PREFIX} \ - --disable-dlso \ - --disable-serio \ - --enable-avr-port \ - --enable-z80-port \ - --enable-xa-port \ - --enable-stm8-port \ - --enable-st7-port \ - $HOST_OPT "$@" + --disable-dlso \ + --enable-m68hc12-port \ + $HOST_OPT "$@" #--enable-ucsim ;; *) @@ -105,6 +88,10 @@ ;; esac +for d in s51 m6809 stm8 tlcs z80; do + [ -L ${d}.src/dtest ] || ln -s ../../test/$d ${d}.src/dtest +done + if [ "$COMP" = "yes" ]; then make clean make diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/config.guess sdcc-4.2.0+dfsg/sim/ucsim/config.guess --- sdcc-4.0.0+dfsg/sim/ucsim/config.guess 2018-06-06 07:01:50.000000000 +0000 +++ sdcc-4.2.0+dfsg/sim/ucsim/config.guess 2022-01-24 11:09:43.000000000 +0000 @@ -2,7 +2,7 @@ # Attempt to guess a canonical system name. # Copyright 1992-2018 Free Software Foundation, Inc. -timestamp='2018-05-19' +timestamp='2018-12-05' # This file is free software; you can redistribute it and/or modify it # under the terms of the GNU General Public License as published by diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/configure sdcc-4.2.0+dfsg/sim/ucsim/configure --- sdcc-4.0.0+dfsg/sim/ucsim/configure 2019-10-01 14:16:20.000000000 +0000 +++ sdcc-4.2.0+dfsg/sim/ucsim/configure 2022-01-23 12:31:18.000000000 +0000 @@ -1,9 +1,10 @@ #! /bin/sh # Guess values for system-dependent variables and create Makefiles. -# Generated by GNU Autoconf 2.69. +# Generated by GNU Autoconf 2.71. # # -# Copyright (C) 1992-1996, 1998-2012 Free Software Foundation, Inc. +# Copyright (C) 1992-1996, 1998-2017, 2020-2021 Free Software Foundation, +# Inc. # # # This configure script is free software; the Free Software Foundation @@ -14,14 +15,16 @@ # Be more Bourne compatible DUALCASE=1; export DUALCASE # for MKS sh -if test -n "${ZSH_VERSION+set}" && (emulate sh) >/dev/null 2>&1; then : +as_nop=: +if test ${ZSH_VERSION+y} && (emulate sh) >/dev/null 2>&1 +then : emulate sh NULLCMD=: # Pre-4.2 versions of Zsh do word splitting on ${1+"$@"}, which # is contrary to our usage. Disable this feature. alias -g '${1+"$@"}'='"$@"' setopt NO_GLOB_SUBST -else +else $as_nop case `(set -o) 2>/dev/null` in #( *posix*) : set -o posix ;; #( @@ -31,46 +34,46 @@ fi + +# Reset variables that may have inherited troublesome values from +# the environment. + +# IFS needs to be set, to space, tab, and newline, in precisely that order. +# (If _AS_PATH_WALK were called with IFS unset, it would have the +# side effect of setting IFS to empty, thus disabling word splitting.) +# Quoting is to prevent editors from complaining about space-tab. as_nl=' ' export as_nl -# Printing a long string crashes Solaris 7 /usr/bin/printf. -as_echo='\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\' -as_echo=$as_echo$as_echo$as_echo$as_echo$as_echo -as_echo=$as_echo$as_echo$as_echo$as_echo$as_echo$as_echo -# Prefer a ksh shell builtin over an external printf program on Solaris, -# but without wasting forks for bash or zsh. -if test -z "$BASH_VERSION$ZSH_VERSION" \ - && (test "X`print -r -- $as_echo`" = "X$as_echo") 2>/dev/null; then - as_echo='print -r --' - as_echo_n='print -rn --' -elif (test "X`printf %s $as_echo`" = "X$as_echo") 2>/dev/null; then - as_echo='printf %s\n' - as_echo_n='printf %s' -else - if test "X`(/usr/ucb/echo -n -n $as_echo) 2>/dev/null`" = "X-n $as_echo"; then - as_echo_body='eval /usr/ucb/echo -n "$1$as_nl"' - as_echo_n='/usr/ucb/echo -n' - else - as_echo_body='eval expr "X$1" : "X\$.*\$"' - as_echo_n_body='eval - arg=$1; - case $arg in #( - *"$as_nl"*) - expr "X$arg" : "X\$.*\$$as_nl"; - arg=`expr "X$arg" : ".*$as_nl\$.*\$"`;; - esac; - expr "X$arg" : "X\$.*\$" | tr -d "$as_nl" - ' - export as_echo_n_body - as_echo_n='sh -c $as_echo_n_body as_echo' - fi - export as_echo_body - as_echo='sh -c $as_echo_body as_echo' -fi +IFS=" "" $as_nl" + +PS1='$ ' +PS2='> ' +PS4='+ ' + +# Ensure predictable behavior from utilities with locale-dependent output. +LC_ALL=C +export LC_ALL +LANGUAGE=C +export LANGUAGE + +# We cannot yet rely on "unset" to work, but we need these variables +# to be unset--not just set to an empty or harmless value--now, to +# avoid bugs in old shells (e.g. pre-3.0 UWIN ksh). This construct +# also avoids known problems related to "unset" and subshell syntax +# in other old shells (e.g. bash 2.01 and pdksh 5.2.14). +for as_var in BASH_ENV ENV MAIL MAILPATH CDPATH +do eval test \${$as_var+y} \ + && ( (unset $as_var) || exit 1) >/dev/null 2>&1 && unset $as_var || : +done + +# Ensure that fds 0, 1, and 2 are open. +if (exec 3>&0) 2>/dev/null; then :; else exec 0&1) 2>/dev/null; then :; else exec 1>/dev/null; fi +if (exec 3>&2) ; then :; else exec 2>/dev/null; fi # The user is always right. -if test "${PATH_SEPARATOR+set}" != set; then +if ${PATH_SEPARATOR+false} :; then PATH_SEPARATOR=: (PATH='/bin;/bin'; FPATH=$PATH; sh -c :) >/dev/null 2>&1 && { (PATH='/bin:/bin'; FPATH=$PATH; sh -c :) >/dev/null 2>&1 || @@ -79,13 +82,6 @@ fi -# IFS -# We need space, tab and new line, in precisely that order. Quoting is -# there to prevent editors from complaining about space-tab. -# (If _AS_PATH_WALK were called with IFS unset, it would disable word -# splitting by setting IFS to empty value.) -IFS=" "" $as_nl" - # Find who we are. Look in the path if we contain no directory separator. as_myself= case $0 in #(( @@ -94,8 +90,12 @@ for as_dir in $PATH do IFS=$as_save_IFS - test -z "$as_dir" && as_dir=. - test -r "$as_dir/$0" && as_myself=$as_dir/$0 && break + case $as_dir in #((( + '') as_dir=./ ;; + */) ;; + *) as_dir=$as_dir/ ;; + esac + test -r "$as_dir$0" && as_myself=$as_dir$0 && break done IFS=$as_save_IFS @@ -107,30 +107,10 @@ as_myself=$0 fi if test ! -f "$as_myself"; then - $as_echo "$as_myself: error: cannot find myself; rerun with an absolute file name" >&2 + printf "%s\n" "$as_myself: error: cannot find myself; rerun with an absolute file name" >&2 exit 1 fi -# Unset variables that we do not need and which cause bugs (e.g. in -# pre-3.0 UWIN ksh). But do not cause bugs in bash 2.01; the "|| exit 1" -# suppresses any "Segmentation fault" message there. '((' could -# trigger a bug in pdksh 5.2.14. -for as_var in BASH_ENV ENV MAIL MAILPATH -do eval test x\${$as_var+set} = xset \ - && ( (unset $as_var) || exit 1) >/dev/null 2>&1 && unset $as_var || : -done -PS1='$ ' -PS2='> ' -PS4='+ ' - -# NLS nuisances. -LC_ALL=C -export LC_ALL -LANGUAGE=C -export LANGUAGE - -# CDPATH. -(unset CDPATH) >/dev/null 2>&1 && unset CDPATH # Use a proper internal environment variable to ensure we don't fall # into an infinite loop, continuously re-executing ourselves. @@ -152,20 +132,22 @@ exec $CONFIG_SHELL $as_opts "$as_myself" ${1+"$@"} # Admittedly, this is quite paranoid, since all the known shells bail # out after a failed `exec'. -$as_echo "$0: could not re-execute with $CONFIG_SHELL" >&2 -as_fn_exit 255 +printf "%s\n" "$0: could not re-execute with $CONFIG_SHELL" >&2 +exit 255 fi # We don't want this to propagate to other subprocesses. { _as_can_reexec=; unset _as_can_reexec;} if test "x$CONFIG_SHELL" = x; then - as_bourne_compatible="if test -n \"\${ZSH_VERSION+set}\" && (emulate sh) >/dev/null 2>&1; then : + as_bourne_compatible="as_nop=: +if test \${ZSH_VERSION+y} && (emulate sh) >/dev/null 2>&1 +then : emulate sh NULLCMD=: # Pre-4.2 versions of Zsh do word splitting on \${1+\"\$@\"}, which # is contrary to our usage. Disable this feature. alias -g '\${1+\"\$@\"}'='\"\$@\"' setopt NO_GLOB_SUBST -else +else \$as_nop case \`(set -o) 2>/dev/null\` in #( *posix*) : set -o posix ;; #( @@ -185,50 +167,53 @@ as_fn_failure && { exitcode=1; echo as_fn_failure succeeded.; } as_fn_ret_success || { exitcode=1; echo as_fn_ret_success failed.; } as_fn_ret_failure && { exitcode=1; echo as_fn_ret_failure succeeded.; } -if ( set x; as_fn_ret_success y && test x = \"\$1\" ); then : +if ( set x; as_fn_ret_success y && test x = \"\$1\" ) +then : -else +else \$as_nop exitcode=1; echo positional parameters were not saved. fi test x\$exitcode = x0 || exit 1 +blah=\$(echo \$(echo blah)) +test x\"\$blah\" = xblah || exit 1 test -x / || exit 1" as_suggested=" as_lineno_1=";as_suggested=$as_suggested$LINENO;as_suggested=$as_suggested" as_lineno_1a=\$LINENO as_lineno_2=";as_suggested=$as_suggested$LINENO;as_suggested=$as_suggested" as_lineno_2a=\$LINENO eval 'test \"x\$as_lineno_1'\$as_run'\" != \"x\$as_lineno_2'\$as_run'\" && test \"x\`expr \$as_lineno_1'\$as_run' + 1\`\" = \"x\$as_lineno_2'\$as_run'\"' || exit 1 - - test -n \"\${ZSH_VERSION+set}\${BASH_VERSION+set}\" || ( - ECHO='\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\' - ECHO=\$ECHO\$ECHO\$ECHO\$ECHO\$ECHO - ECHO=\$ECHO\$ECHO\$ECHO\$ECHO\$ECHO\$ECHO - PATH=/empty FPATH=/empty; export PATH FPATH - test \"X\`printf %s \$ECHO\`\" = \"X\$ECHO\" \\ - || test \"X\`print -r -- \$ECHO\`\" = \"X\$ECHO\" ) || exit 1 test \$(( 1 + 1 )) = 2 || exit 1" - if (eval "$as_required") 2>/dev/null; then : + if (eval "$as_required") 2>/dev/null +then : as_have_required=yes -else +else $as_nop as_have_required=no fi - if test x$as_have_required = xyes && (eval "$as_suggested") 2>/dev/null; then : + if test x$as_have_required = xyes && (eval "$as_suggested") 2>/dev/null +then : -else +else $as_nop as_save_IFS=$IFS; IFS=$PATH_SEPARATOR as_found=false for as_dir in /bin$PATH_SEPARATOR/usr/bin$PATH_SEPARATOR$PATH do IFS=$as_save_IFS - test -z "$as_dir" && as_dir=. + case $as_dir in #((( + '') as_dir=./ ;; + */) ;; + *) as_dir=$as_dir/ ;; + esac as_found=: case $as_dir in #( /*) for as_base in sh bash ksh sh5; do # Try only shells that exist, to save several forks. - as_shell=$as_dir/$as_base + as_shell=$as_dir$as_base if { test -f "$as_shell" || test -f "$as_shell.exe"; } && - { $as_echo "$as_bourne_compatible""$as_required" | as_run=a "$as_shell"; } 2>/dev/null; then : + as_run=a "$as_shell" -c "$as_bourne_compatible""$as_required" 2>/dev/null +then : CONFIG_SHELL=$as_shell as_have_required=yes - if { $as_echo "$as_bourne_compatible""$as_suggested" | as_run=a "$as_shell"; } 2>/dev/null; then : + if as_run=a "$as_shell" -c "$as_bourne_compatible""$as_suggested" 2>/dev/null +then : break 2 fi fi @@ -236,14 +221,21 @@ esac as_found=false done -$as_found || { if { test -f "$SHELL" || test -f "$SHELL.exe"; } && - { $as_echo "$as_bourne_compatible""$as_required" | as_run=a "$SHELL"; } 2>/dev/null; then : - CONFIG_SHELL=$SHELL as_have_required=yes -fi; } IFS=$as_save_IFS +if $as_found +then : + +else $as_nop + if { test -f "$SHELL" || test -f "$SHELL.exe"; } && + as_run=a "$SHELL" -c "$as_bourne_compatible""$as_required" 2>/dev/null +then : + CONFIG_SHELL=$SHELL as_have_required=yes +fi +fi - if test "x$CONFIG_SHELL" != x; then : + if test "x$CONFIG_SHELL" != x +then : export CONFIG_SHELL # We cannot yet assume a decent shell, so we have to provide a # neutralization value for shells without unset; and this also @@ -261,18 +253,19 @@ exec $CONFIG_SHELL $as_opts "$as_myself" ${1+"$@"} # Admittedly, this is quite paranoid, since all the known shells bail # out after a failed `exec'. -$as_echo "$0: could not re-execute with $CONFIG_SHELL" >&2 +printf "%s\n" "$0: could not re-execute with $CONFIG_SHELL" >&2 exit 255 fi - if test x$as_have_required = xno; then : - $as_echo "$0: This script requires a shell more modern than all" - $as_echo "$0: the shells that I found on your system." - if test x${ZSH_VERSION+set} = xset ; then - $as_echo "$0: In particular, zsh $ZSH_VERSION has bugs and should" - $as_echo "$0: be upgraded to zsh 4.3.4 or later." + if test x$as_have_required = xno +then : + printf "%s\n" "$0: This script requires a shell more modern than all" + printf "%s\n" "$0: the shells that I found on your system." + if test ${ZSH_VERSION+y} ; then + printf "%s\n" "$0: In particular, zsh $ZSH_VERSION has bugs and should" + printf "%s\n" "$0: be upgraded to zsh 4.3.4 or later." else - $as_echo "$0: Please tell bug-autoconf@gnu.org about your system, + printf "%s\n" "$0: Please tell bug-autoconf@gnu.org about your system, $0: including any error possibly output before this $0: message. Then install a modern shell, or manually run $0: the script under such a shell if you do have one." @@ -299,6 +292,7 @@ } as_unset=as_fn_unset + # as_fn_set_status STATUS # ----------------------- # Set $? to STATUS, without forking. @@ -316,6 +310,14 @@ as_fn_set_status $1 exit $1 } # as_fn_exit +# as_fn_nop +# --------- +# Do nothing but, unlike ":", preserve the value of $?. +as_fn_nop () +{ + return $? +} +as_nop=as_fn_nop # as_fn_mkdir_p # ------------- @@ -330,7 +332,7 @@ as_dirs= while :; do case $as_dir in #( - *\'*) as_qdir=`$as_echo "$as_dir" | sed "s/'/'\\\\\\\\''/g"`;; #'( + *\'*) as_qdir=`printf "%s\n" "$as_dir" | sed "s/'/'\\\\\\\\''/g"`;; #'( *) as_qdir=$as_dir;; esac as_dirs="'$as_qdir' $as_dirs" @@ -339,7 +341,7 @@ X"$as_dir" : 'X$//$[^/]' \| \ X"$as_dir" : 'X$//$$' \| \ X"$as_dir" : 'X$/$' \| . 2>/dev/null || -$as_echo X"$as_dir" | +printf "%s\n" X"$as_dir" | sed '/^X$.*[^/]$\/\/*[^/][^/]*\/*$/{ s//\1/ q @@ -378,12 +380,13 @@ # advantage of any shell optimizations that allow amortized linear growth over # repeated appends, instead of the typical quadratic growth present in naive # implementations. -if (eval "as_var=1; as_var+=2; test x\$as_var = x12") 2>/dev/null; then : +if (eval "as_var=1; as_var+=2; test x\$as_var = x12") 2>/dev/null +then : eval 'as_fn_append () { eval $1+=\$2 }' -else +else $as_nop as_fn_append () { eval $1=\$$1\$2 @@ -395,18 +398,27 @@ # Perform arithmetic evaluation on the ARGs, and store the result in the # global $as_val. Take advantage of shells that can avoid forks. The arguments # must be portable across $(()) and expr. -if (eval "test \$(( 1 + 1 )) = 2") 2>/dev/null; then : +if (eval "test \$(( 1 + 1 )) = 2") 2>/dev/null +then : eval 'as_fn_arith () { as_val=$(( $* )) }' -else +else $as_nop as_fn_arith () { as_val=`expr "$@" || test $? -eq 1` } fi # as_fn_arith +# as_fn_nop +# --------- +# Do nothing but, unlike ":", preserve the value of $?. +as_fn_nop () +{ + return $? +} +as_nop=as_fn_nop # as_fn_error STATUS ERROR [LINENO LOG_FD] # ---------------------------------------- @@ -418,9 +430,9 @@ as_status=$1; test $as_status -eq 0 && as_status=1 if test "$4"; then as_lineno=${as_lineno-"$3"} as_lineno_stack=as_lineno_stack=$as_lineno_stack - $as_echo "$as_me:${as_lineno-$LINENO}: error: $2" >&$4 + printf "%s\n" "$as_me:${as_lineno-$LINENO}: error: $2" >&$4 fi - $as_echo "$as_me: error: $2" >&2 + printf "%s\n" "$as_me: error: $2" >&2 as_fn_exit $as_status } # as_fn_error @@ -447,7 +459,7 @@ $as_expr X/"$0" : '.*/$[^/][^/]*$/*$' \| \ X"$0" : 'X$//$$' \| \ X"$0" : 'X$/$' \| . 2>/dev/null || -$as_echo X/"$0" | +printf "%s\n" X/"$0" | sed '/^.*\/$[^/][^/]*$\/*$/{ s//\1/ q @@ -491,7 +503,7 @@ s/-\n.*// ' >$as_me.lineno && chmod +x "$as_me.lineno" || - { $as_echo "$as_me: error: cannot create $as_me.lineno; rerun with a POSIX shell" >&2; as_fn_exit 1; } + { printf "%s\n" "$as_me: error: cannot create $as_me.lineno; rerun with a POSIX shell" >&2; as_fn_exit 1; } # If we had to re-execute with $CONFIG_SHELL, we're ensured to have # already done that, so ensure we don't try to do so again and fall @@ -505,6 +517,10 @@ exit } + +# Determine whether it's possible to make 'echo' print without a newline. +# These variables are no longer used directly by Autoconf, but are AC_SUBSTed +# for compatibility with existing Makefiles. ECHO_C= ECHO_N= ECHO_T= case `echo -n x` in #((((( -n*) @@ -518,6 +534,13 @@ ECHO_N='-n';; esac +# For backward compatibility with old third-party macros, we provide +# the shell variables $as_echo and $as_echo_n. New code should use +# AS_ECHO(["message"]) and AS_ECHO_N(["message"]), respectively. +as_echo='printf %s\n' +as_echo_n='printf %s' + + rm -f conf$$ conf$$.exe conf$$.file if test -d conf$$.dir; then rm -f conf$$.dir/conf$$.file @@ -561,8 +584,6 @@ # Sed expression to map a string onto a valid variable name. as_tr_sh="eval sed 'y%*+%pp%;s%[^_$as_cr_alnum]%_%g'" -SHELL=${CONFIG_SHELL-/bin/sh} - test -n "$DJDIR" || exec 7<&0 &1 @@ -585,50 +606,47 @@ MAKEFLAGS= # Identity of this package. -PACKAGE_NAME= -PACKAGE_TARNAME= -PACKAGE_VERSION= -PACKAGE_STRING= -PACKAGE_BUGREPORT= -PACKAGE_URL= +PACKAGE_NAME='' +PACKAGE_TARNAME='' +PACKAGE_VERSION='' +PACKAGE_STRING='' +PACKAGE_BUGREPORT='' +PACKAGE_URL='' ac_unique_file=".version" # Factoring default headers for most tests. ac_includes_default="\ -#include -#ifdef HAVE_SYS_TYPES_H -# include -#endif -#ifdef HAVE_SYS_STAT_H -# include +#include +#ifdef HAVE_STDIO_H +# include #endif -#ifdef STDC_HEADERS +#ifdef HAVE_STDLIB_H # include -# include -#else -# ifdef HAVE_STDLIB_H -# include -# endif #endif #ifdef HAVE_STRING_H -# if !defined STDC_HEADERS && defined HAVE_MEMORY_H -# include -# endif # include #endif -#ifdef HAVE_STRINGS_H -# include -#endif #ifdef HAVE_INTTYPES_H # include #endif #ifdef HAVE_STDINT_H # include #endif +#ifdef HAVE_STRINGS_H +# include +#endif +#ifdef HAVE_SYS_TYPES_H +# include +#endif +#ifdef HAVE_SYS_STAT_H +# include +#endif #ifdef HAVE_UNISTD_H # include #endif" +ac_header_cxx_list= +ac_func_cxx_list= ac_subst_vars='LTLIBOBJS LIBOBJS dlso_ok @@ -641,46 +659,18 @@ panel_ok DL dl_ok +EGREP +GREP WINSOCK_AVAIL YFLAGS YACC LEXLIB -LEX_OUTPUT_ROOT -LEX -LIBTOOL_DEPS -CPP -LT_SYS_LIBRARY_PATH -OTOOL64 -OTOOL -LIPO -NMEDIT -DSYMUTIL -MANIFEST_TOOL -ac_ct_AR -DLLTOOL -OBJDUMP -LN_S -NM -ac_ct_DUMPBIN -DUMPBIN -LD -FGREP -EGREP -GREP -SED ac_ct_CC CFLAGS CC -host_os -host_vendor -host_cpu -host -build_os -build_vendor -build_cpu -build -LIBTOOL -SREC_CAT +LEX_OUTPUT_ROOT +LEX +LIBTOOL_DEPS AR STRIP RANLIB @@ -696,12 +686,20 @@ CXXFLAGS CXX enable_serio +enable_pblaze_port +enable_rxk_port +enable_mos6502_port +enable_m68hc12_port +enable_m68hc11_port +enable_m6800_port +enable_m6809_port +enable_p1516_port enable_pdk_port enable_st7_port enable_stm8_port enable_xa_port enable_s08_port -enable_hc08_port +enable_m68hc08_port enable_tlcs_port enable_r3ka_port enable_r2k_port @@ -771,22 +769,22 @@ enable_r2k_port enable_r3ka_port enable_tlcs_port -enable_hc08_port +enable_m68hc08_port enable_s08_port enable_xa_port enable_stm8_port enable_pdk_port enable_st7_port +enable_p1516_port +enable_m6809_port +enable_m6800_port +enable_m68hc11_port +enable_m68hc12_port +enable_mos6502_port +enable_rxk_port +enable_pblaze_port enable_serio enable_statistic -enable_shared -enable_static -with_pic -enable_fast_install -with_aix_soname -with_gnu_ld -with_sysroot -enable_libtool_lock ' ac_precious_vars='build_alias host_alias @@ -801,8 +799,6 @@ CXXCPP CC CFLAGS -LT_SYS_LIBRARY_PATH -CPP YACC YFLAGS' @@ -873,8 +869,6 @@ *) ac_optarg=yes ;; esac - # Accept the important Cygnus configure options, so we can diagnose typos. - case $ac_dashdash$ac_option in --) ac_dashdash=yes ;; @@ -915,9 +909,9 @@ ac_useropt=`expr "x$ac_option" : 'x-*disable-$.*$'` # Reject names that are not valid shell variable names. expr "x$ac_useropt" : ".*[^-+._$as_cr_alnum]" >/dev/null && - as_fn_error $? "invalid feature name: $ac_useropt" + as_fn_error $? "invalid feature name: \`$ac_useropt'" ac_useropt_orig=$ac_useropt - ac_useropt=`$as_echo "$ac_useropt" | sed 's/[-+.]/_/g'` + ac_useropt=`printf "%s\n" "$ac_useropt" | sed 's/[-+.]/_/g'` case $ac_user_opts in *" "enable_$ac_useropt" @@ -941,9 +935,9 @@ ac_useropt=`expr "x$ac_option" : 'x-*enable-$[^=]*$'` # Reject names that are not valid shell variable names. expr "x$ac_useropt" : ".*[^-+._$as_cr_alnum]" >/dev/null && - as_fn_error $? "invalid feature name: $ac_useropt" + as_fn_error $? "invalid feature name: \`$ac_useropt'" ac_useropt_orig=$ac_useropt - ac_useropt=`$as_echo "$ac_useropt" | sed 's/[-+.]/_/g'` + ac_useropt=`printf "%s\n" "$ac_useropt" | sed 's/[-+.]/_/g'` case $ac_user_opts in *" "enable_$ac_useropt" @@ -1154,9 +1148,9 @@ ac_useropt=`expr "x$ac_option" : 'x-*with-$[^=]*$'` # Reject names that are not valid shell variable names. expr "x$ac_useropt" : ".*[^-+._$as_cr_alnum]" >/dev/null && - as_fn_error $? "invalid package name: $ac_useropt" + as_fn_error $? "invalid package name: \`$ac_useropt'" ac_useropt_orig=$ac_useropt - ac_useropt=`$as_echo "$ac_useropt" | sed 's/[-+.]/_/g'` + ac_useropt=`printf "%s\n" "$ac_useropt" | sed 's/[-+.]/_/g'` case $ac_user_opts in *" "with_$ac_useropt" @@ -1170,9 +1164,9 @@ ac_useropt=`expr "x$ac_option" : 'x-*without-$.*$'` # Reject names that are not valid shell variable names. expr "x$ac_useropt" : ".*[^-+._$as_cr_alnum]" >/dev/null && - as_fn_error $? "invalid package name: $ac_useropt" + as_fn_error $? "invalid package name: \`$ac_useropt'" ac_useropt_orig=$ac_useropt - ac_useropt=`$as_echo "$ac_useropt" | sed 's/[-+.]/_/g'` + ac_useropt=`printf "%s\n" "$ac_useropt" | sed 's/[-+.]/_/g'` case $ac_user_opts in *" "with_$ac_useropt" @@ -1216,9 +1210,9 @@ *) # FIXME: should be removed in autoconf 3.0. - $as_echo "$as_me: WARNING: you should use --build, --host, --target" >&2 + printf "%s\n" "$as_me: WARNING: you should use --build, --host, --target" >&2 expr "x$ac_option" : ".*[^-._$as_cr_alnum]" >/dev/null && - $as_echo "$as_me: WARNING: invalid host type: $ac_option" >&2 + printf "%s\n" "$as_me: WARNING: invalid host type: $ac_option" >&2 : "${build_alias=$ac_option} ${host_alias=$ac_option} ${target_alias=$ac_option}" ;; @@ -1234,7 +1228,7 @@ case $enable_option_checking in no) ;; fatal) as_fn_error $? "unrecognized options: $ac_unrecognized_opts" ;; - *) $as_echo "$as_me: WARNING: unrecognized options: $ac_unrecognized_opts" >&2 ;; + *) printf "%s\n" "$as_me: WARNING: unrecognized options: $ac_unrecognized_opts" >&2 ;; esac fi @@ -1298,7 +1292,7 @@ X"$as_myself" : 'X$//$[^/]' \| \ X"$as_myself" : 'X$//$$' \| \ X"$as_myself" : 'X$/$' \| . 2>/dev/null || -$as_echo X"$as_myself" | +printf "%s\n" X"$as_myself" | sed '/^X$.*[^/]$\/\/*[^/][^/]*\/*$/{ s//\1/ q @@ -1417,10 +1411,6 @@ --program-prefix=PREFIX prepend PREFIX to installed program names --program-suffix=SUFFIX append SUFFIX to installed program names --program-transform-name=PROGRAM run sed PROGRAM on installed program names - -System types: - --build=BUILD configure for building on BUILD [guessed] - --host=HOST cross-compile to build programs to run on HOST [BUILD] _ACEOF fi @@ -1436,38 +1426,29 @@ --enable-dlso compile dynamically loadable shared libraries --disable-mcs51-port do not compile simulator for mcs51 --disable-ds390-port do not compile simulator for ds390 - --enable-avr-port compile simulator for AVR + --disable-avr-port do not compile simulator for AVR --disable-z80-port do not compile simulator for z80 --disable-z180-port do not compile simulator for z180 --disable-gbz80-port do not compile simulator for gbz80 --disable-r2k-port do not compile simulator for r2k --disable-r3ka-port do not compile simulator for r3ka - --disable-tlcs-port do not compile simulator for TLCS - --disable-hc08-port do not compile simulator for hc08 + --disable-tlcs-port do not compile simulator for TLCS + --disable-m68hc08-port do not compile simulator for m68hc08 --disable-s08-port do not compile simulator for s08 - --enable-xa-port compile simulator for xa + --disable-xa-port do not compile simulator for xa --disable-stm8-port do not compile simulator for stm8 --disable-pdk-port do not compile simulator for pdk - --enable-st7-port compile simulator for st7 - --enable-serio compile serio GUI tool (needs curses) + --disable-st7-port do not compile simulator for st7 + --disable-p1516-port do not compile simulator for p1516 + --disable-m6809-port do not compile simulator for m6809 + --disable-m6800-port do not compile simulator for m6800 + --disable-m68hc11-port do not compile simulator for m68hc11 + --enable-m68hc12-port compile simulator for m68hc12 + --disable-mos6502-port do not compile simulator for mos6502 + --disable-rxk-port do not compile simulator for Rabbit rXk + --disable-pblaze-port do not compile simulator for Xilinx PicoBlaze + --disable-serio do not compile serio GUI tool (needs curses) --enable-statistic compile statistical features (slower simulation) - --enable-shared[=PKGS] build shared libraries [default=yes] - --enable-static[=PKGS] build static libraries [default=yes] - --enable-fast-install[=PKGS] - optimize for fast installation [default=yes] - --disable-libtool-lock avoid locking (might break parallel builds) - -Optional Packages: - --with-PACKAGE[=ARG] use PACKAGE [ARG=yes] - --without-PACKAGE do not use PACKAGE (same as --with-PACKAGE=no) - --with-pic[=PKGS] try to use only PIC/non-PIC objects [default=use - both] - --with-aix-soname=aix|svr4|both - shared library versioning (aka "SONAME") variant to - provide on AIX, [default=aix]. - --with-gnu-ld assume the C compiler uses GNU ld [default=no] - --with-sysroot[=DIR] Search for dependent libraries within DIR (or the - compiler's sysroot if not specified). Some influential environment variables: docdir documentation installation directory @@ -1481,9 +1462,6 @@ CXXCPP C++ preprocessor CC C compiler command CFLAGS C compiler flags - LT_SYS_LIBRARY_PATH - User-defined run-time library search path. - CPP C preprocessor YACC The `Yet Another Compiler Compiler' implementation to use. Defaults to the first program found out of: `bison -y', `byacc', `yacc'. @@ -1510,9 +1488,9 @@ case "$ac_dir" in .) ac_dir_suffix= ac_top_builddir_sub=. ac_top_build_prefix= ;; *) - ac_dir_suffix=/`$as_echo "$ac_dir" | sed 's|^\.[\\/]||'` + ac_dir_suffix=/`printf "%s\n" "$ac_dir" | sed 's|^\.[\\/]||'` # A ".." for each directory in $ac_dir_suffix. - ac_top_builddir_sub=`$as_echo "$ac_dir_suffix" | sed 's|/[^\\/]*|/..|g;s|/||'` + ac_top_builddir_sub=`printf "%s\n" "$ac_dir_suffix" | sed 's|/[^\\/]*|/..|g;s|/||'` case $ac_top_builddir_sub in "") ac_top_builddir_sub=. ac_top_build_prefix= ;; *) ac_top_build_prefix=$ac_top_builddir_sub/ ;; @@ -1540,7 +1518,8 @@ ac_abs_srcdir=$ac_abs_top_srcdir$ac_dir_suffix cd "$ac_dir" || { ac_status=$?; continue; } - # Check for guested configure. + # Check for configure.gnu first; this name is used for a wrapper for + # Metaconfig's "Configure" on case-insensitive file systems. if test -f "$ac_srcdir/configure.gnu"; then echo && $SHELL "$ac_srcdir/configure.gnu" --help=recursive @@ -1548,7 +1527,7 @@ echo && $SHELL "$ac_srcdir/configure" --help=recursive else - $as_echo "$as_me: WARNING: no configuration information is in $ac_dir" >&2 + printf "%s\n" "$as_me: WARNING: no configuration information is in $ac_dir" >&2 fi || ac_status=$? cd "$ac_pwd" || { ac_status=$?; break; } done @@ -1558,9 +1537,9 @@ if $ac_init_version; then cat <<\_ACEOF configure -generated by GNU Autoconf 2.69 +generated by GNU Autoconf 2.71 -Copyright (C) 2012 Free Software Foundation, Inc. +Copyright (C) 2021 Free Software Foundation, Inc. This configure script is free software; the Free Software Foundation gives unlimited permission to copy, distribute and modify it. _ACEOF @@ -1577,14 +1556,14 @@ ac_fn_cxx_try_compile () { as_lineno=${as_lineno-"$1"} as_lineno_stack=as_lineno_stack=$as_lineno_stack - rm -f conftest.$ac_objext + rm -f conftest.$ac_objext conftest.beam if { { ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" -$as_echo "$ac_try_echo"; } >&5 +printf "%s\n" "$ac_try_echo"; } >&5 (eval "$ac_compile") 2>conftest.err ac_status=$? if test -s conftest.err; then @@ -1592,14 +1571,15 @@ cat conftest.er1 >&5 mv -f conftest.er1 conftest.err fi - $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + printf "%s\n" "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 test $ac_status = 0; } && { test -z "$ac_cxx_werror_flag" || test ! -s conftest.err - } && test -s conftest.$ac_objext; then : + } && test -s conftest.$ac_objext +then : ac_retval=0 -else - $as_echo "$as_me: failed program was:" >&5 +else $as_nop + printf "%s\n" "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_retval=1 @@ -1621,7 +1601,7 @@ *) ac_try_echo=$ac_try;; esac eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" -$as_echo "$ac_try_echo"; } >&5 +printf "%s\n" "$ac_try_echo"; } >&5 (eval "$ac_cpp conftest.$ac_ext") 2>conftest.err ac_status=$? if test -s conftest.err; then @@ -1629,14 +1609,15 @@ cat conftest.er1 >&5 mv -f conftest.er1 conftest.err fi - $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + printf "%s\n" "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 test $ac_status = 0; } > conftest.i && { test -z "$ac_cxx_preproc_warn_flag$ac_cxx_werror_flag" || test ! -s conftest.err - }; then : + } +then : ac_retval=0 -else - $as_echo "$as_me: failed program was:" >&5 +else $as_nop + printf "%s\n" "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_retval=1 @@ -1652,14 +1633,14 @@ ac_fn_c_try_compile () { as_lineno=${as_lineno-"$1"} as_lineno_stack=as_lineno_stack=$as_lineno_stack - rm -f conftest.$ac_objext + rm -f conftest.$ac_objext conftest.beam if { { ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" -$as_echo "$ac_try_echo"; } >&5 +printf "%s\n" "$ac_try_echo"; } >&5 (eval "$ac_compile") 2>conftest.err ac_status=$? if test -s conftest.err; then @@ -1667,14 +1648,15 @@ cat conftest.er1 >&5 mv -f conftest.er1 conftest.err fi - $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + printf "%s\n" "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 test $ac_status = 0; } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err - } && test -s conftest.$ac_objext; then : + } && test -s conftest.$ac_objext +then : ac_retval=0 -else - $as_echo "$as_me: failed program was:" >&5 +else $as_nop + printf "%s\n" "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_retval=1 @@ -1690,14 +1672,14 @@ ac_fn_c_try_link () { as_lineno=${as_lineno-"$1"} as_lineno_stack=as_lineno_stack=$as_lineno_stack - rm -f conftest.$ac_objext conftest$ac_exeext + rm -f conftest.$ac_objext conftest.beam conftest$ac_exeext if { { ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" -$as_echo "$ac_try_echo"; } >&5 +printf "%s\n" "$ac_try_echo"; } >&5 (eval "$ac_link") 2>conftest.err ac_status=$? if test -s conftest.err; then @@ -1705,17 +1687,18 @@ cat conftest.er1 >&5 mv -f conftest.er1 conftest.err fi - $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + printf "%s\n" "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 test $ac_status = 0; } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest$ac_exeext && { test "$cross_compiling" = yes || test -x conftest$ac_exeext - }; then : + } +then : ac_retval=0 -else - $as_echo "$as_me: failed program was:" >&5 +else $as_nop + printf "%s\n" "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_retval=1 @@ -1730,127 +1713,155 @@ } # ac_fn_c_try_link -# ac_fn_c_check_header_compile LINENO HEADER VAR INCLUDES -# ------------------------------------------------------- +# ac_fn_cxx_check_header_compile LINENO HEADER VAR INCLUDES +# --------------------------------------------------------- # Tests whether HEADER exists and can be compiled using the include files in # INCLUDES, setting the cache variable VAR accordingly. -ac_fn_c_check_header_compile () +ac_fn_cxx_check_header_compile () { as_lineno=${as_lineno-"$1"} as_lineno_stack=as_lineno_stack=$as_lineno_stack - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $2" >&5 -$as_echo_n "checking for $2... " >&6; } -if eval \${$3+:} false; then : - $as_echo_n "(cached) " >&6 -else + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking for $2" >&5 +printf %s "checking for $2... " >&6; } +if eval test \${$3+y} +then : + printf %s "(cached) " >&6 +else $as_nop cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ $4 #include <$2> _ACEOF -if ac_fn_c_try_compile "$LINENO"; then : +if ac_fn_cxx_try_compile "$LINENO" +then : eval "$3=yes" -else +else $as_nop eval "$3=no" fi -rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +rm -f core conftest.err conftest.$ac_objext conftest.beam conftest.$ac_ext fi eval ac_res=\$$3 - { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5 -$as_echo "$ac_res" >&6; } + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5 +printf "%s\n" "$ac_res" >&6; } eval $as_lineno_stack; ${as_lineno_stack:+:} unset as_lineno -} # ac_fn_c_check_header_compile +} # ac_fn_cxx_check_header_compile -# ac_fn_c_try_cpp LINENO -# ---------------------- -# Try to preprocess conftest.$ac_ext, and return whether this succeeded. -ac_fn_c_try_cpp () +# ac_fn_cxx_try_link LINENO +# ------------------------- +# Try to link conftest.$ac_ext, and return whether this succeeded. +ac_fn_cxx_try_link () { as_lineno=${as_lineno-"$1"} as_lineno_stack=as_lineno_stack=$as_lineno_stack - if { { ac_try="$ac_cpp conftest.$ac_ext" + rm -f conftest.$ac_objext conftest.beam conftest$ac_exeext + if { { ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" -$as_echo "$ac_try_echo"; } >&5 - (eval "$ac_cpp conftest.$ac_ext") 2>conftest.err +printf "%s\n" "$ac_try_echo"; } >&5 + (eval "$ac_link") 2>conftest.err ac_status=$? if test -s conftest.err; then grep -v '^ *+' conftest.err >conftest.er1 cat conftest.er1 >&5 mv -f conftest.er1 conftest.err fi - $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 - test $ac_status = 0; } > conftest.i && { - test -z "$ac_c_preproc_warn_flag$ac_c_werror_flag" || + printf "%s\n" "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } && { + test -z "$ac_cxx_werror_flag" || test ! -s conftest.err - }; then : + } && test -s conftest$ac_exeext && { + test "$cross_compiling" = yes || + test -x conftest$ac_exeext + } +then : ac_retval=0 -else - $as_echo "$as_me: failed program was:" >&5 +else $as_nop + printf "%s\n" "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 - ac_retval=1 + ac_retval=1 fi + # Delete the IPA/IPO (Inter Procedural Analysis/Optimization) information + # created by the PGI compiler (conftest_ipa8_conftest.oo), as it would + # interfere with the next link command; also delete a directory that is + # left behind by Apple's compiler. We do this before executing the actions. + rm -rf conftest.dSYM conftest_ipa8_conftest.oo eval $as_lineno_stack; ${as_lineno_stack:+:} unset as_lineno as_fn_set_status $ac_retval -} # ac_fn_c_try_cpp +} # ac_fn_cxx_try_link -# ac_fn_c_try_run LINENO -# ---------------------- -# Try to link conftest.$ac_ext, and return whether this succeeded. Assumes -# that executables *can* be run. -ac_fn_c_try_run () +# ac_fn_cxx_check_type LINENO TYPE VAR INCLUDES +# --------------------------------------------- +# Tests whether TYPE exists after having included INCLUDES, setting cache +# variable VAR accordingly. +ac_fn_cxx_check_type () { as_lineno=${as_lineno-"$1"} as_lineno_stack=as_lineno_stack=$as_lineno_stack - if { { ac_try="$ac_link" -case "(($ac_try" in - *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; - *) ac_try_echo=$ac_try;; -esac -eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" -$as_echo "$ac_try_echo"; } >&5 - (eval "$ac_link") 2>&5 - ac_status=$? - $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 - test $ac_status = 0; } && { ac_try='./conftest$ac_exeext' - { { case "(($ac_try" in - *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; - *) ac_try_echo=$ac_try;; -esac -eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" -$as_echo "$ac_try_echo"; } >&5 - (eval "$ac_try") 2>&5 - ac_status=$? - $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 - test $ac_status = 0; }; }; then : - ac_retval=0 -else - $as_echo "$as_me: program exited with status $ac_status" >&5 - $as_echo "$as_me: failed program was:" >&5 -sed 's/^/| /' conftest.$ac_ext >&5 + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking for $2" >&5 +printf %s "checking for $2... " >&6; } +if eval test \${$3+y} +then : + printf %s "(cached) " >&6 +else $as_nop + eval "$3=no" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +$4 +int +main (void) +{ +if (sizeof ($2)) + return 0; + ; + return 0; +} +_ACEOF +if ac_fn_cxx_try_compile "$LINENO" +then : + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +$4 +int +main (void) +{ +if (sizeof (($2))) + return 0; + ; + return 0; +} +_ACEOF +if ac_fn_cxx_try_compile "$LINENO" +then : - ac_retval=$ac_status +else $as_nop + eval "$3=yes" fi - rm -rf conftest.dSYM conftest_ipa8_conftest.oo +rm -f core conftest.err conftest.$ac_objext conftest.beam conftest.$ac_ext +fi +rm -f core conftest.err conftest.$ac_objext conftest.beam conftest.$ac_ext +fi +eval ac_res=\$$3 + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5 +printf "%s\n" "$ac_res" >&6; } eval $as_lineno_stack; ${as_lineno_stack:+:} unset as_lineno - as_fn_set_status $ac_retval -} # ac_fn_c_try_run +} # ac_fn_cxx_check_type -# ac_fn_c_check_func LINENO FUNC VAR -# ---------------------------------- +# ac_fn_cxx_check_func LINENO FUNC VAR +# ------------------------------------ # Tests whether FUNC exists, setting the cache variable VAR accordingly -ac_fn_c_check_func () +ac_fn_cxx_check_func () { as_lineno=${as_lineno-"$1"} as_lineno_stack=as_lineno_stack=$as_lineno_stack - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $2" >&5 -$as_echo_n "checking for $2... " >&6; } -if eval \${$3+:} false; then : - $as_echo_n "(cached) " >&6 -else + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking for $2" >&5 +printf %s "checking for $2... " >&6; } +if eval test \${$3+y} +then : + printf %s "(cached) " >&6 +else $as_nop cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ /* Define $2 to an innocuous variant, in case declares $2. @@ -1858,16 +1869,9 @@ #define $2 innocuous_$2 /* System header to define __stub macros and hopefully few prototypes, - which can conflict with char $2 (); below. - Prefer to if __STDC__ is defined, since - exists even on freestanding compilers. */ - -#ifdef __STDC__ -# include -#else -# include -#endif + which can conflict with char $2 (); below. */ +#include #undef $2 /* Override any GCC internal prototype to avoid an error. @@ -1885,78 +1889,33 @@ #endif int -main () +main (void) { return $2 (); ; return 0; } _ACEOF -if ac_fn_c_try_link "$LINENO"; then : +if ac_fn_cxx_try_link "$LINENO" +then : eval "$3=yes" -else +else $as_nop eval "$3=no" fi -rm -f core conftest.err conftest.$ac_objext \ +rm -f core conftest.err conftest.$ac_objext conftest.beam \ conftest$ac_exeext conftest.$ac_ext fi eval ac_res=\$$3 - { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5 -$as_echo "$ac_res" >&6; } - eval $as_lineno_stack; ${as_lineno_stack:+:} unset as_lineno - -} # ac_fn_c_check_func - -# ac_fn_cxx_try_link LINENO -# ------------------------- -# Try to link conftest.$ac_ext, and return whether this succeeded. -ac_fn_cxx_try_link () -{ - as_lineno=${as_lineno-"$1"} as_lineno_stack=as_lineno_stack=$as_lineno_stack - rm -f conftest.$ac_objext conftest$ac_exeext - if { { ac_try="$ac_link" -case "(($ac_try" in - *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; - *) ac_try_echo=$ac_try;; -esac -eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" -$as_echo "$ac_try_echo"; } >&5 - (eval "$ac_link") 2>conftest.err - ac_status=$? - if test -s conftest.err; then - grep -v '^ *+' conftest.err >conftest.er1 - cat conftest.er1 >&5 - mv -f conftest.er1 conftest.err - fi - $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 - test $ac_status = 0; } && { - test -z "$ac_cxx_werror_flag" || - test ! -s conftest.err - } && test -s conftest$ac_exeext && { - test "$cross_compiling" = yes || - test -x conftest$ac_exeext - }; then : - ac_retval=0 -else - $as_echo "$as_me: failed program was:" >&5 -sed 's/^/| /' conftest.$ac_ext >&5 - - ac_retval=1 -fi - # Delete the IPA/IPO (Inter Procedural Analysis/Optimization) information - # created by the PGI compiler (conftest_ipa8_conftest.oo), as it would - # interfere with the next link command; also delete a directory that is - # left behind by Apple's compiler. We do this before executing the actions. - rm -rf conftest.dSYM conftest_ipa8_conftest.oo + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5 +printf "%s\n" "$ac_res" >&6; } eval $as_lineno_stack; ${as_lineno_stack:+:} unset as_lineno - as_fn_set_status $ac_retval -} # ac_fn_cxx_try_link +} # ac_fn_cxx_check_func # ac_fn_cxx_try_run LINENO # ------------------------ -# Try to link conftest.$ac_ext, and return whether this succeeded. Assumes -# that executables *can* be run. +# Try to run conftest.$ac_ext, and return whether this succeeded. Assumes that +# executables *can* be run. ac_fn_cxx_try_run () { as_lineno=${as_lineno-"$1"} as_lineno_stack=as_lineno_stack=$as_lineno_stack @@ -1966,25 +1925,26 @@ *) ac_try_echo=$ac_try;; esac eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" -$as_echo "$ac_try_echo"; } >&5 +printf "%s\n" "$ac_try_echo"; } >&5 (eval "$ac_link") 2>&5 ac_status=$? - $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + printf "%s\n" "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 test $ac_status = 0; } && { ac_try='./conftest$ac_exeext' { { case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" -$as_echo "$ac_try_echo"; } >&5 +printf "%s\n" "$ac_try_echo"; } >&5 (eval "$ac_try") 2>&5 ac_status=$? - $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 - test $ac_status = 0; }; }; then : + printf "%s\n" "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; }; } +then : ac_retval=0 -else - $as_echo "$as_me: program exited with status $ac_status" >&5 - $as_echo "$as_me: failed program was:" >&5 +else $as_nop + printf "%s\n" "$as_me: program exited with status $ac_status" >&5 + printf "%s\n" "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_retval=$ac_status @@ -1995,192 +1955,39 @@ } # ac_fn_cxx_try_run -# ac_fn_cxx_check_header_mongrel LINENO HEADER VAR INCLUDES -# --------------------------------------------------------- -# Tests whether HEADER exists, giving a warning if it cannot be compiled using -# the include files in INCLUDES and setting the cache variable VAR -# accordingly. -ac_fn_cxx_check_header_mongrel () +# ac_fn_cxx_compute_int LINENO EXPR VAR INCLUDES +# ---------------------------------------------- +# Tries to find the compile-time value of EXPR in a program that includes +# INCLUDES, setting VAR accordingly. Returns whether the value could be +# computed +ac_fn_cxx_compute_int () { as_lineno=${as_lineno-"$1"} as_lineno_stack=as_lineno_stack=$as_lineno_stack - if eval \${$3+:} false; then : - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $2" >&5 -$as_echo_n "checking for $2... " >&6; } -if eval \${$3+:} false; then : - $as_echo_n "(cached) " >&6 -fi -eval ac_res=\$$3 - { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5 -$as_echo "$ac_res" >&6; } -else - # Is the header compilable? -{ $as_echo "$as_me:${as_lineno-$LINENO}: checking $2 usability" >&5 -$as_echo_n "checking $2 usability... " >&6; } + if test "$cross_compiling" = yes; then + # Depending upon the size, compute the lo and hi bounds. cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ $4 -#include <$2> +int +main (void) +{ +static int test_array [1 - 2 * !(($2) >= 0)]; +test_array [0] = 0; +return test_array [0]; + + ; + return 0; +} _ACEOF -if ac_fn_cxx_try_compile "$LINENO"; then : - ac_header_compiler=yes -else - ac_header_compiler=no -fi -rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext -{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_header_compiler" >&5 -$as_echo "$ac_header_compiler" >&6; } - -# Is the header present? -{ $as_echo "$as_me:${as_lineno-$LINENO}: checking $2 presence" >&5 -$as_echo_n "checking $2 presence... " >&6; } -cat confdefs.h - <<_ACEOF >conftest.$ac_ext -/* end confdefs.h. */ -#include <$2> -_ACEOF -if ac_fn_cxx_try_cpp "$LINENO"; then : - ac_header_preproc=yes -else - ac_header_preproc=no -fi -rm -f conftest.err conftest.i conftest.$ac_ext -{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_header_preproc" >&5 -$as_echo "$ac_header_preproc" >&6; } - -# So? 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Some functions are actually named - something starting with __ and the normal name is an alias. */ -#if defined __stub_$2 || defined __stub___$2 -choke me -#endif - -int -main () -{ -return $2 (); - ; - return 0; -} -_ACEOF -if ac_fn_cxx_try_link "$LINENO"; then : - eval "$3=yes" -else - eval "$3=no" -fi -rm -f core conftest.err conftest.$ac_objext \ - conftest$ac_exeext conftest.$ac_ext -fi -eval ac_res=\$$3 - { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5 -$as_echo "$ac_res" >&6; } - eval $as_lineno_stack; ${as_lineno_stack:+:} unset as_lineno - -} # ac_fn_cxx_check_func - -# ac_fn_cxx_compute_int LINENO EXPR VAR INCLUDES -# ---------------------------------------------- -# Tries to find the compile-time value of EXPR in a program that includes -# INCLUDES, setting VAR accordingly. Returns whether the value could be -# computed -ac_fn_cxx_compute_int () -{ - as_lineno=${as_lineno-"$1"} as_lineno_stack=as_lineno_stack=$as_lineno_stack - if test "$cross_compiling" = yes; then - # Depending upon the size, compute the lo and hi bounds. -cat confdefs.h - <<_ACEOF >conftest.$ac_ext -/* end confdefs.h. */ -$4 -int -main () -{ -static int test_array [1 - 2 * !(($2) >= 0)]; -test_array [0] = 0; -return test_array [0]; - - ; - return 0; -} -_ACEOF -if ac_fn_cxx_try_compile "$LINENO"; then : - ac_lo=0 ac_mid=0 - while :; do - cat confdefs.h - <<_ACEOF >conftest.$ac_ext +if ac_fn_cxx_try_compile "$LINENO" +then : + ac_lo=0 ac_mid=0 + while :; do + cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ $4 int -main () +main (void) { static int test_array [1 - 2 * !(($2) <= $ac_mid)]; test_array [0] = 0; @@ -2190,9 +1997,10 @@ return 0; } _ACEOF -if ac_fn_cxx_try_compile "$LINENO"; then : +if ac_fn_cxx_try_compile "$LINENO" +then : ac_hi=$ac_mid; break -else +else $as_nop as_fn_arith $ac_mid + 1 && ac_lo=$as_val if test $ac_lo -le $ac_mid; then ac_lo= ac_hi= @@ -2200,14 +2008,14 @@ fi as_fn_arith 2 '*' $ac_mid + 1 && ac_mid=$as_val fi -rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +rm -f core conftest.err conftest.$ac_objext conftest.beam conftest.$ac_ext done -else +else $as_nop cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ $4 int -main () +main (void) { static int test_array [1 - 2 * !(($2) < 0)]; test_array [0] = 0; @@ -2217,14 +2025,15 @@ return 0; } _ACEOF -if ac_fn_cxx_try_compile "$LINENO"; then : +if ac_fn_cxx_try_compile "$LINENO" +then : ac_hi=-1 ac_mid=-1 while :; do cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ $4 int -main () +main (void) { static int test_array [1 - 2 * !(($2) >= $ac_mid)]; test_array [0] = 0; @@ -2234,9 +2043,10 @@ return 0; } _ACEOF -if ac_fn_cxx_try_compile "$LINENO"; then : +if ac_fn_cxx_try_compile "$LINENO" +then : ac_lo=$ac_mid; break -else +else $as_nop as_fn_arith '(' $ac_mid ')' - 1 && ac_hi=$as_val if test $ac_mid -le $ac_hi; then ac_lo= ac_hi= @@ -2244,14 +2054,14 @@ fi as_fn_arith 2 '*' $ac_mid && ac_mid=$as_val fi -rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +rm -f core conftest.err conftest.$ac_objext conftest.beam conftest.$ac_ext done -else +else $as_nop ac_lo= ac_hi= fi -rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +rm -f core conftest.err conftest.$ac_objext conftest.beam conftest.$ac_ext fi -rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +rm -f core conftest.err conftest.$ac_objext conftest.beam conftest.$ac_ext # Binary search between lo and hi bounds. while test "x$ac_lo" != "x$ac_hi"; do as_fn_arith '(' $ac_hi - $ac_lo ')' / 2 + $ac_lo && ac_mid=$as_val @@ -2259,7 +2069,7 @@ /* end confdefs.h. */ $4 int -main () +main (void) { static int test_array [1 - 2 * !(($2) <= $ac_mid)]; test_array [0] = 0; @@ -2269,12 +2079,13 @@ return 0; } _ACEOF -if ac_fn_cxx_try_compile "$LINENO"; then : +if ac_fn_cxx_try_compile "$LINENO" +then : ac_hi=$ac_mid -else +else $as_nop as_fn_arith '(' $ac_mid ')' + 1 && ac_lo=$as_val fi -rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +rm -f core conftest.err conftest.$ac_objext conftest.beam conftest.$ac_ext done case $ac_lo in #(( ?*) eval "$3=\$ac_lo"; ac_retval=0 ;; @@ -2284,12 +2095,12 @@ cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ $4 -static long int longval () { return $2; } -static unsigned long int ulongval () { return $2; } +static long int longval (void) { return $2; } +static unsigned long int ulongval (void) { return $2; } #include #include int -main () +main (void) { FILE *f = fopen ("conftest.val", "w"); @@ -2317,9 +2128,10 @@ return 0; } _ACEOF -if ac_fn_cxx_try_run "$LINENO"; then : +if ac_fn_cxx_try_run "$LINENO" +then : echo >>conftest.val; read $3 config.log <<_ACEOF This file contains any messages produced by compilers while running configure, to aid debugging if configure makes a mistake. It was created by $as_me, which was -generated by GNU Autoconf 2.69. Invocation command line was +generated by GNU Autoconf 2.71. Invocation command line was - $ $0 $@ + $ $0$ac_configure_args_raw _ACEOF exec 5>>config.log @@ -2371,8 +2203,12 @@ for as_dir in $PATH do IFS=$as_save_IFS - test -z "$as_dir" && as_dir=. - $as_echo "PATH: $as_dir" + case $as_dir in #((( + '') as_dir=./ ;; + */) ;; + *) as_dir=$as_dir/ ;; + esac + printf "%s\n" "PATH: $as_dir" done IFS=$as_save_IFS @@ -2407,7 +2243,7 @@ | -silent | --silent | --silen | --sile | --sil) continue ;; *\'*) - ac_arg=`$as_echo "$ac_arg" | sed "s/'/'\\\\\\\\''/g"` ;; + ac_arg=`printf "%s\n" "$ac_arg" | sed "s/'/'\\\\\\\\''/g"` ;; esac case $ac_pass in 1) as_fn_append ac_configure_args0 " '$ac_arg'" ;; @@ -2442,11 +2278,13 @@ # WARNING: Use '\'' to represent an apostrophe within the trap. # WARNING: Do not start the trap code with a newline, due to a FreeBSD 4.0 bug. trap 'exit_status=$? + # Sanitize IFS. + IFS=" "" $as_nl" # Save into config.log some information that might help in debugging. { echo - $as_echo "## ---------------- ## + printf "%s\n" "## ---------------- ## ## Cache variables. ## ## ---------------- ##" echo @@ -2457,8 +2295,8 @@ case $ac_val in #( *${as_nl}*) case $ac_var in #( - *_cv_*) { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: cache variable $ac_var contains a newline" >&5 -$as_echo "$as_me: WARNING: cache variable $ac_var contains a newline" >&2;} ;; + *_cv_*) { printf "%s\n" "$as_me:${as_lineno-$LINENO}: WARNING: cache variable $ac_var contains a newline" >&5 +printf "%s\n" "$as_me: WARNING: cache variable $ac_var contains a newline" >&2;} ;; esac case $ac_var in #( _ | IFS | as_nl) ;; #( @@ -2482,7 +2320,7 @@ ) echo - $as_echo "## ----------------- ## + printf "%s\n" "## ----------------- ## ## Output variables. ## ## ----------------- ##" echo @@ -2490,14 +2328,14 @@ do eval ac_val=\$$ac_var case $ac_val in - *\'\''*) ac_val=`$as_echo "$ac_val" | sed "s/'\''/'\''\\\\\\\\'\'''\''/g"`;; + *\'\''*) ac_val=`printf "%s\n" "$ac_val" | sed "s/'\''/'\''\\\\\\\\'\'''\''/g"`;; esac - $as_echo "$ac_var='\''$ac_val'\''" + printf "%s\n" "$ac_var='\''$ac_val'\''" done | sort echo if test -n "$ac_subst_files"; then - $as_echo "## ------------------- ## + printf "%s\n" "## ------------------- ## ## File substitutions. ## ## ------------------- ##" echo @@ -2505,15 +2343,15 @@ do eval ac_val=\$$ac_var case $ac_val in - *\'\''*) ac_val=`$as_echo "$ac_val" | sed "s/'\''/'\''\\\\\\\\'\'''\''/g"`;; + *\'\''*) ac_val=`printf "%s\n" "$ac_val" | sed "s/'\''/'\''\\\\\\\\'\'''\''/g"`;; esac - $as_echo "$ac_var='\''$ac_val'\''" + printf "%s\n" "$ac_var='\''$ac_val'\''" done | sort echo fi if test -s confdefs.h; then - $as_echo "## ----------- ## + printf "%s\n" "## ----------- ## ## confdefs.h. ## ## ----------- ##" echo @@ -2521,8 +2359,8 @@ echo fi test "$ac_signal" != 0 && - $as_echo "$as_me: caught signal $ac_signal" - $as_echo "$as_me: exit $exit_status" + printf "%s\n" "$as_me: caught signal $ac_signal" + printf "%s\n" "$as_me: exit $exit_status" } >&5 rm -f core *.core core.conftest.* && rm -f -r conftest* confdefs* conf$$* $ac_clean_files && @@ -2536,63 +2374,48 @@ # confdefs.h avoids OS command line length limits that DEFS can exceed. rm -f -r conftest* confdefs.h -$as_echo "/* confdefs.h */" > confdefs.h +printf "%s\n" "/* confdefs.h */" > confdefs.h # Predefined preprocessor variables. -cat >>confdefs.h <<_ACEOF -#define PACKAGE_NAME "$PACKAGE_NAME" -_ACEOF +printf "%s\n" "#define PACKAGE_NAME \"$PACKAGE_NAME\"" >>confdefs.h -cat >>confdefs.h <<_ACEOF -#define PACKAGE_TARNAME "$PACKAGE_TARNAME" -_ACEOF +printf "%s\n" "#define PACKAGE_TARNAME \"$PACKAGE_TARNAME\"" >>confdefs.h -cat >>confdefs.h <<_ACEOF -#define PACKAGE_VERSION "$PACKAGE_VERSION" -_ACEOF +printf "%s\n" "#define PACKAGE_VERSION \"$PACKAGE_VERSION\"" >>confdefs.h -cat >>confdefs.h <<_ACEOF -#define PACKAGE_STRING "$PACKAGE_STRING" -_ACEOF +printf "%s\n" "#define PACKAGE_STRING \"$PACKAGE_STRING\"" >>confdefs.h -cat >>confdefs.h <<_ACEOF -#define PACKAGE_BUGREPORT "$PACKAGE_BUGREPORT" -_ACEOF +printf "%s\n" "#define PACKAGE_BUGREPORT \"$PACKAGE_BUGREPORT\"" >>confdefs.h -cat >>confdefs.h <<_ACEOF -#define PACKAGE_URL "$PACKAGE_URL" -_ACEOF +printf "%s\n" "#define PACKAGE_URL \"$PACKAGE_URL\"" >>confdefs.h # Let the site file select an alternate cache file if it wants to. # Prefer an explicitly selected file to automatically selected ones. -ac_site_file1=NONE -ac_site_file2=NONE if test -n "$CONFIG_SITE"; then - # We do not want a PATH search for config.site. - case $CONFIG_SITE in #(( - -*) ac_site_file1=./$CONFIG_SITE;; - */*) ac_site_file1=$CONFIG_SITE;; - *) ac_site_file1=./$CONFIG_SITE;; - esac + ac_site_files="$CONFIG_SITE" elif test "x$prefix" != xNONE; then - ac_site_file1=$prefix/share/config.site - ac_site_file2=$prefix/etc/config.site + ac_site_files="$prefix/share/config.site $prefix/etc/config.site" else - ac_site_file1=$ac_default_prefix/share/config.site - ac_site_file2=$ac_default_prefix/etc/config.site + ac_site_files="$ac_default_prefix/share/config.site $ac_default_prefix/etc/config.site" fi -for ac_site_file in "$ac_site_file1" "$ac_site_file2" + +for ac_site_file in $ac_site_files do - test "x$ac_site_file" = xNONE && continue - if test /dev/null != "$ac_site_file" && test -r "$ac_site_file"; then - { $as_echo "$as_me:${as_lineno-$LINENO}: loading site script $ac_site_file" >&5 -$as_echo "$as_me: loading site script $ac_site_file" >&6;} + case $ac_site_file in #( + */*) : + ;; #( + *) : + ac_site_file=./$ac_site_file ;; +esac + if test -f "$ac_site_file" && test -r "$ac_site_file"; then + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: loading site script $ac_site_file" >&5 +printf "%s\n" "$as_me: loading site script $ac_site_file" >&6;} sed 's/^/| /' "$ac_site_file" >&5 . "$ac_site_file" \ - || { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 -$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} + || { { printf "%s\n" "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 +printf "%s\n" "$as_me: error: in \`$ac_pwd':" >&2;} as_fn_error $? "failed to load site script $ac_site_file See \`config.log' for more details" "$LINENO" 5; } fi @@ -2602,171 +2425,803 @@ # Some versions of bash will fail to source /dev/null (special files # actually), so we avoid doing that. DJGPP emulates it as a regular file. if test /dev/null != "$cache_file" && test -f "$cache_file"; then - { $as_echo "$as_me:${as_lineno-$LINENO}: loading cache $cache_file" >&5 -$as_echo "$as_me: loading cache $cache_file" >&6;} + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: loading cache $cache_file" >&5 +printf "%s\n" "$as_me: loading cache $cache_file" >&6;} case $cache_file in [\\/]* | ?:[\\/]* ) . "$cache_file";; *) . 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Use of quotes ensures accuracy. - *) as_fn_append ac_configure_args " '$ac_arg'" ;; - esac - fi -done -if $ac_cache_corrupted; then - { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 -$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} - { $as_echo "$as_me:${as_lineno-$LINENO}: error: changes in the environment can compromise the build" >&5 -$as_echo "$as_me: error: changes in the environment can compromise the build" >&2;} - as_fn_error $? "run \`make distclean' and/or \`rm $cache_file' and start over" "$LINENO" 5 -fi -## -------------------- ## -## Main body of script. ## -## -------------------- ## - -ac_ext=c -ac_cpp='$CPP $CPPFLAGS' -ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' -ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' -ac_compiler_gnu=$ac_cv_c_compiler_gnu +# Test code for whether the C++ compiler supports C++98 (global declarations) +ac_cxx_conftest_cxx98_globals=' +// Does the compiler advertise C++98 conformance? +#if !defined __cplusplus || __cplusplus < 199711L +# error "Compiler does not advertise C++98 conformance" +#endif + +// These inclusions are to reject old compilers that +// lack the unsuffixed header files. +#include +#include + +// and are *not* freestanding headers in C++98. +extern void assert (int); +namespace std { + extern int strcmp (const char *, const char *); +} + +// Namespaces, exceptions, and templates were all added after "C++ 2.0". +using std::exception; +using std::strcmp; + +namespace { + +void test_exception_syntax() +{ + try { + throw "test"; + } catch (const char *s) { + // Extra parentheses suppress a warning when building autoconf itself, + // due to lint rules shared with more typical C programs. + assert (!(strcmp) (s, "test")); + } +} +template struct test_template +{ + T const val; + explicit test_template(T t) : val(t) {} + template T add(U u) { return static_cast(u) + val; } +}; +} // anonymous namespace +' -ac_config_headers="$ac_config_headers ddconfig.h:ddconfig_in.h" +# Test code for whether the C++ compiler supports C++98 (body of main) +ac_cxx_conftest_cxx98_main=' + assert (argc); + assert (! argv[0]); +{ + test_exception_syntax (); + test_template tt (2.0); + assert (tt.add (4) == 6.0); + assert (true && !false); +} +' +# Test code for whether the C++ compiler supports C++11 (global declarations) +ac_cxx_conftest_cxx11_globals=' +// Does the compiler advertise C++ 2011 conformance? +#if !defined __cplusplus || __cplusplus < 201103L +# error "Compiler does not advertise C++11 conformance" +#endif -for ac_prog in gawk mawk nawk awk -do - # Extract the first word of "$ac_prog", so it can be a program name with args. -set dummy $ac_prog; ac_word=$2 -{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 -$as_echo_n "checking for $ac_word... " >&6; } -if ${ac_cv_prog_AWK+:} false; then : - $as_echo_n "(cached) " >&6 -else - if test -n "$AWK"; then - ac_cv_prog_AWK="$AWK" # Let the user override the test. -else -as_save_IFS=$IFS; IFS=$PATH_SEPARATOR -for as_dir in $PATH -do - IFS=$as_save_IFS - test -z "$as_dir" && as_dir=. - for ac_exec_ext in '' $ac_executable_extensions; do - if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then - ac_cv_prog_AWK="$ac_prog" - $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 - break 2 - fi -done - done -IFS=$as_save_IFS +namespace cxx11test +{ + constexpr int get_val() { return 20; } -fi -fi -AWK=$ac_cv_prog_AWK -if test -n "$AWK"; then - { $as_echo "$as_me:${as_lineno-$LINENO}: result: $AWK" >&5 -$as_echo "$AWK" >&6; } -else - { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 -$as_echo "no" >&6; } -fi + struct testinit + { + int i; + double d; + }; + class delegate + { + public: + delegate(int n) : n(n) {} + delegate(): delegate(2354) {} + + virtual int getval() { return this->n; }; + protected: + int n; + }; - test -n "$AWK" && break -done + class overridden : public delegate + { + public: + overridden(int n): delegate(n) {} + virtual int getval() override final { return this->n * 2; } + }; + class nocopy + { + public: + nocopy(int i): i(i) {} + nocopy() = default; + nocopy(const nocopy&) = delete; + nocopy & operator=(const nocopy&) = delete; + private: + int i; + }; -{ $as_echo "$as_me:${as_lineno-$LINENO}: checking version of the package" >&5 -$as_echo_n "checking version of the package... " >&6; } -if test -f ${srcdir}/.version; then - { read VERSION; } < ${srcdir}/.version - { $as_echo "$as_me:${as_lineno-$LINENO}: result: $VERSION" >&5 -$as_echo "$VERSION" >&6; } -else - VERSION="0.0.0" - { $as_echo "$as_me:${as_lineno-$LINENO}: result: unknown using 0.0.0" >&5 -$as_echo "unknown using 0.0.0" >&6; } -fi -VERSIONHI=`echo $VERSION|$AWK 'BEGIN {FS="."} {print $1}'` -VERSIONLO=`echo $VERSION|$AWK 'BEGIN {FS="."} {print $2}'` -VERSIONP=`echo $VERSION|$AWK 'BEGIN {FS="."} {print $3}'` + // for testing lambda expressions + template Ret eval(Fn f, Ret v) + { + return f(v); + } + // for testing variadic templates and trailing return types + template auto sum(V first) -> V + { + return first; + } + template auto sum(V first, Args... rest) -> V + { + return first + sum(rest...); + } +} +' +# Test code for whether the C++ compiler supports C++11 (body of main) +ac_cxx_conftest_cxx11_main=' +{ + // Test auto and decltype + auto a1 = 6538; + auto a2 = 48573953.4; + auto a3 = "String literal"; + int total = 0; + for (auto i = a3; *i; ++i) { total += *i; } + decltype(a2) a4 = 34895.034; +} +{ + // Test constexpr + short sa[cxx11test::get_val()] = { 0 }; +} +{ + // Test initializer lists + cxx11test::testinit il = { 4323, 435234.23544 }; +} +{ + // Test range-based for + int array[] = {9, 7, 13, 15, 4, 18, 12, 10, 5, 3, + 14, 19, 17, 8, 6, 20, 16, 2, 11, 1}; + for (auto &x : array) { x += 23; } +} +{ + // Test lambda expressions + using cxx11test::eval; + assert (eval ([](int x) { return x*2; }, 21) == 42); + double d = 2.0; + assert (eval ([&](double x) { return d += x; }, 3.0) == 5.0); + assert (d == 5.0); + assert (eval ([=](double x) mutable { return d += x; }, 4.0) == 9.0); + assert (d == 5.0); +} +{ + // Test use of variadic templates + using cxx11test::sum; + auto a = sum(1); + auto b = sum(1, 2); + auto c = sum(1.0, 2.0, 3.0); +} +{ + // Test constructor delegation + cxx11test::delegate d1; + cxx11test::delegate d2(); + cxx11test::delegate d3(45); +} +{ + // Test override and final + cxx11test::overridden o1(55464); +} +{ + // Test nullptr + char *c = nullptr; +} +{ + // Test template brackets + test_template<::test_template> v(test_template(12)); +} +{ + // Unicode literals + char const *utf8 = u8"UTF-8 string \u2500"; + char16_t const *utf16 = u"UTF-8 string \u2500"; + char32_t const *utf32 = U"UTF-32 string \u2500"; +} +' -cat >>confdefs.h <<_ACEOF -#define VERSIONSTR "${VERSION}" -_ACEOF +# Test code for whether the C compiler supports C++11 (complete). +ac_cxx_conftest_cxx11_program="${ac_cxx_conftest_cxx98_globals} +${ac_cxx_conftest_cxx11_globals} +int +main (int argc, char **argv) +{ + int ok = 0; + ${ac_cxx_conftest_cxx98_main} + ${ac_cxx_conftest_cxx11_main} + return ok; +} +" -cat >>confdefs.h <<_ACEOF -#define VERSIONHI $VERSIONHI -_ACEOF +# Test code for whether the C compiler supports C++98 (complete). +ac_cxx_conftest_cxx98_program="${ac_cxx_conftest_cxx98_globals} +int +main (int argc, char **argv) +{ + int ok = 0; + ${ac_cxx_conftest_cxx98_main} + return ok; +} +" +# Test code for whether the C compiler supports C89 (global declarations) +ac_c_conftest_c89_globals=' +/* Does the compiler advertise C89 conformance? + Do not test the value of __STDC__, because some compilers set it to 0 + while being otherwise adequately conformant. */ +#if !defined __STDC__ +# error "Compiler does not advertise C89 conformance" +#endif -cat >>confdefs.h <<_ACEOF -#define VERSIONLO $VERSIONLO -_ACEOF +#include +#include +struct stat; +/* Most of the following tests are stolen from RCS 5.7 src/conf.sh. */ +struct buf { int x; }; +struct buf * (*rcsopen) (struct buf *, struct stat *, int); +static char *e (p, i) + char **p; + int i; +{ + return p[i]; +} +static char *f (char * (*g) (char **, int), char **p, ...) +{ + char *s; + va_list v; + va_start (v,p); + s = g (p, va_arg (v,int)); + va_end (v); + return s; +} +/* OSF 4.0 Compaq cc is some sort of almost-ANSI by default. It has + function prototypes and stuff, but not \xHH hex character constants. + These do not provoke an error unfortunately, instead are silently treated + as an "x". The following induces an error, until -std is added to get + proper ANSI mode. Curiously \x00 != x always comes out true, for an + array size at least. It is necessary to write \x00 == 0 to get something + that is true only with -std. */ +int osf4_cc_array ['\''\x00'\'' == 0 ? 1 : -1]; -cat >>confdefs.h <<_ACEOF -#define VERSIONP $VERSIONP -_ACEOF +/* IBM C 6 for AIX is almost-ANSI by default, but it replaces macro parameters + inside strings and character constants. */ +#define FOO(x) '\''x'\'' +int xlc6_cc_array[FOO(a) == '\''x'\'' ? 1 : -1]; + +int test (int i, double x); +struct s1 {int (*f) (int a);}; +struct s2 {int (*f) (double a);}; +int pairnames (int, char **, int *(*)(struct buf *, struct stat *, int), + int, int);' + +# Test code for whether the C compiler supports C89 (body of main). +ac_c_conftest_c89_main=' +ok |= (argc == 0 || f (e, argv, 0) != argv[0] || f (e, argv, 1) != argv[1]); +' + +# Test code for whether the C compiler supports C99 (global declarations) +ac_c_conftest_c99_globals=' +// Does the compiler advertise C99 conformance? +#if !defined __STDC_VERSION__ || __STDC_VERSION__ < 199901L +# error "Compiler does not advertise C99 conformance" +#endif + +#include +extern int puts (const char *); +extern int printf (const char *, ...); +extern int dprintf (int, const char *, ...); +extern void *malloc (size_t); + +// Check varargs macros. These examples are taken from C99 6.10.3.5. +// dprintf is used instead of fprintf to avoid needing to declare +// FILE and stderr. +#define debug(...) dprintf (2, __VA_ARGS__) +#define showlist(...) puts (#__VA_ARGS__) +#define report(test,...) ((test) ? puts (#test) : printf (__VA_ARGS__)) +static void +test_varargs_macros (void) +{ + int x = 1234; + int y = 5678; + debug ("Flag"); + debug ("X = %d\n", x); + showlist (The first, second, and third items.); + report (x>y, "x is %d but y is %d", x, y); +} + +// Check long long types. +#define BIG64 18446744073709551615ull +#define BIG32 4294967295ul +#define BIG_OK (BIG64 / BIG32 == 4294967297ull && BIG64 % BIG32 == 0) +#if !BIG_OK + #error "your preprocessor is broken" +#endif +#if BIG_OK +#else + #error "your preprocessor is broken" +#endif +static long long int bignum = -9223372036854775807LL; +static unsigned long long int ubignum = BIG64; + +struct incomplete_array +{ + int datasize; + double data[]; +}; + +struct named_init { + int number; + const wchar_t *name; + double average; +}; + +typedef const char *ccp; + +static inline int +test_restrict (ccp restrict text) +{ + // See if C++-style comments work. + // Iterate through items via the restricted pointer. + // Also check for declarations in for loops. + for (unsigned int i = 0; *(text+i) != '\''\0'\''; ++i) + continue; + return 0; +} + +// Check varargs and va_copy. +static bool +test_varargs (const char *format, ...) +{ + va_list args; + va_start (args, format); + va_list args_copy; + va_copy (args_copy, args); + + const char *str = ""; + int number = 0; + float fnumber = 0; + + while (*format) + { + switch (*format++) + { + case '\''s'\'': // string + str = va_arg (args_copy, const char *); + break; + case '\''d'\'': // int + number = va_arg (args_copy, int); + break; + case '\''f'\'': // float + fnumber = va_arg (args_copy, double); + break; + default: + break; + } + } + va_end (args_copy); + va_end (args); + + return *str && number && fnumber; +} +' + +# Test code for whether the C compiler supports C99 (body of main). +ac_c_conftest_c99_main=' + // Check bool. + _Bool success = false; + success |= (argc != 0); + + // Check restrict. + if (test_restrict ("String literal") == 0) + success = true; + char *restrict newvar = "Another string"; + + // Check varargs. + success &= test_varargs ("s, d'\'' f .", "string", 65, 34.234); + test_varargs_macros (); + + // Check flexible array members. + struct incomplete_array *ia = + malloc (sizeof (struct incomplete_array) + (sizeof (double) * 10)); + ia->datasize = 10; + for (int i = 0; i < ia->datasize; ++i) + ia->data[i] = i * 1.234; + + // Check named initializers. + struct named_init ni = { + .number = 34, + .name = L"Test wide string", + .average = 543.34343, + }; + + ni.number = 58; + + int dynamic_array[ni.number]; + dynamic_array[0] = argv[0][0]; + dynamic_array[ni.number - 1] = 543; + + // work around unused variable warnings + ok |= (!success || bignum == 0LL || ubignum == 0uLL || newvar[0] == '\''x'\'' + || dynamic_array[ni.number - 1] != 543); +' + +# Test code for whether the C compiler supports C11 (global declarations) +ac_c_conftest_c11_globals=' +// Does the compiler advertise C11 conformance? +#if !defined __STDC_VERSION__ || __STDC_VERSION__ < 201112L +# error "Compiler does not advertise C11 conformance" +#endif + +// Check _Alignas. +char _Alignas (double) aligned_as_double; +char _Alignas (0) no_special_alignment; +extern char aligned_as_int; +char _Alignas (0) _Alignas (int) aligned_as_int; + +// Check _Alignof. +enum +{ + int_alignment = _Alignof (int), + int_array_alignment = _Alignof (int[100]), + char_alignment = _Alignof (char) +}; +_Static_assert (0 < -_Alignof (int), "_Alignof is signed"); + +// Check _Noreturn. +int _Noreturn does_not_return (void) { for (;;) continue; } + +// Check _Static_assert. +struct test_static_assert +{ + int x; + _Static_assert (sizeof (int) <= sizeof (long int), + "_Static_assert does not work in struct"); + long int y; +}; + +// Check UTF-8 literals. +#define u8 syntax error! +char const utf8_literal[] = u8"happens to be ASCII" "another string"; + +// Check duplicate typedefs. +typedef long *long_ptr; +typedef long int *long_ptr; +typedef long_ptr long_ptr; + +// Anonymous structures and unions -- taken from C11 6.7.2.1 Example 1. +struct anonymous +{ + union { + struct { int i; int j; }; + struct { int k; long int l; } w; + }; + int m; +} v1; +' + +# Test code for whether the C compiler supports C11 (body of main). +ac_c_conftest_c11_main=' + _Static_assert ((offsetof (struct anonymous, i) + == offsetof (struct anonymous, w.k)), + "Anonymous union alignment botch"); + v1.i = 2; + v1.w.k = 5; + ok |= v1.i != 5; +' + +# Test code for whether the C compiler supports C11 (complete). +ac_c_conftest_c11_program="${ac_c_conftest_c89_globals} +${ac_c_conftest_c99_globals} +${ac_c_conftest_c11_globals} + +int +main (int argc, char **argv) +{ + int ok = 0; + ${ac_c_conftest_c89_main} + ${ac_c_conftest_c99_main} + ${ac_c_conftest_c11_main} + return ok; +} +" + +# Test code for whether the C compiler supports C99 (complete). +ac_c_conftest_c99_program="${ac_c_conftest_c89_globals} +${ac_c_conftest_c99_globals} + +int +main (int argc, char **argv) +{ + int ok = 0; + ${ac_c_conftest_c89_main} + ${ac_c_conftest_c99_main} + return ok; +} +" + +# Test code for whether the C compiler supports C89 (complete). +ac_c_conftest_c89_program="${ac_c_conftest_c89_globals} + +int +main (int argc, char **argv) +{ + int ok = 0; + ${ac_c_conftest_c89_main} + return ok; +} +" + +as_fn_append ac_header_cxx_list " stdio.h stdio_h HAVE_STDIO_H" +as_fn_append ac_header_cxx_list " stdlib.h stdlib_h HAVE_STDLIB_H" +as_fn_append ac_header_cxx_list " string.h string_h HAVE_STRING_H" +as_fn_append ac_header_cxx_list " inttypes.h inttypes_h HAVE_INTTYPES_H" +as_fn_append ac_header_cxx_list " stdint.h stdint_h HAVE_STDINT_H" +as_fn_append ac_header_cxx_list " strings.h strings_h HAVE_STRINGS_H" +as_fn_append ac_header_cxx_list " sys/stat.h sys_stat_h HAVE_SYS_STAT_H" +as_fn_append ac_header_cxx_list " sys/types.h sys_types_h HAVE_SYS_TYPES_H" +as_fn_append ac_header_cxx_list " unistd.h unistd_h HAVE_UNISTD_H" +as_fn_append ac_header_cxx_list " vfork.h vfork_h HAVE_VFORK_H" +as_fn_append ac_func_cxx_list " fork HAVE_FORK" +as_fn_append ac_func_cxx_list " vfork HAVE_VFORK" + +# Auxiliary files required by this configure script. +ac_aux_files="install-sh" + +# Locations in which to look for auxiliary files. +ac_aux_dir_candidates="${srcdir}${PATH_SEPARATOR}${srcdir}/..${PATH_SEPARATOR}${srcdir}/../.." + +# Search for a directory containing all of the required auxiliary files, +# $ac_aux_files, from the $PATH-style list $ac_aux_dir_candidates. +# If we don't find one directory that contains all the files we need, +# we report the set of missing files from the *first* directory in +# $ac_aux_dir_candidates and give up. +ac_missing_aux_files="" +ac_first_candidate=: +printf "%s\n" "$as_me:${as_lineno-$LINENO}: looking for aux files: $ac_aux_files" >&5 +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +as_found=false +for as_dir in $ac_aux_dir_candidates +do + IFS=$as_save_IFS + case $as_dir in #((( + '') as_dir=./ ;; + */) ;; + *) as_dir=$as_dir/ ;; + esac + as_found=: + + printf "%s\n" "$as_me:${as_lineno-$LINENO}: trying $as_dir" >&5 + ac_aux_dir_found=yes + ac_install_sh= + for ac_aux in $ac_aux_files + do + # As a special case, if "install-sh" is required, that requirement + # can be satisfied by any of "install-sh", "install.sh", or "shtool", + # and $ac_install_sh is set appropriately for whichever one is found. + if test x"$ac_aux" = x"install-sh" + then + if test -f "${as_dir}install-sh"; then + printf "%s\n" "$as_me:${as_lineno-$LINENO}: ${as_dir}install-sh found" >&5 + ac_install_sh="${as_dir}install-sh -c" + elif test -f "${as_dir}install.sh"; then + printf "%s\n" "$as_me:${as_lineno-$LINENO}: ${as_dir}install.sh found" >&5 + ac_install_sh="${as_dir}install.sh -c" + elif test -f "${as_dir}shtool"; then + printf "%s\n" "$as_me:${as_lineno-$LINENO}: ${as_dir}shtool found" >&5 + ac_install_sh="${as_dir}shtool install -c" + else + ac_aux_dir_found=no + if $ac_first_candidate; then + ac_missing_aux_files="${ac_missing_aux_files} install-sh" + else + break + fi + fi + else + if test -f "${as_dir}${ac_aux}"; then + printf "%s\n" "$as_me:${as_lineno-$LINENO}: ${as_dir}${ac_aux} found" >&5 + else + ac_aux_dir_found=no + if $ac_first_candidate; then + ac_missing_aux_files="${ac_missing_aux_files} ${ac_aux}" + else + break + fi + fi + fi + done + if test "$ac_aux_dir_found" = yes; then + ac_aux_dir="$as_dir" + break + fi + ac_first_candidate=false + + as_found=false +done +IFS=$as_save_IFS +if $as_found +then : + +else $as_nop + as_fn_error $? "cannot find required auxiliary files:$ac_missing_aux_files" "$LINENO" 5 +fi + + +# These three variables are undocumented and unsupported, +# and are intended to be withdrawn in a future Autoconf release. +# They can cause serious problems if a builder's source tree is in a directory +# whose full name contains unusual characters. +if test -f "${ac_aux_dir}config.guess"; then + ac_config_guess="$SHELL ${ac_aux_dir}config.guess" +fi +if test -f "${ac_aux_dir}config.sub"; then + ac_config_sub="$SHELL ${ac_aux_dir}config.sub" +fi +if test -f "$ac_aux_dir/configure"; then + ac_configure="$SHELL ${ac_aux_dir}configure" +fi + +# Check that the precious variables saved in the cache have kept the same +# value. +ac_cache_corrupted=false +for ac_var in $ac_precious_vars; do + eval ac_old_set=\$ac_cv_env_${ac_var}_set + eval ac_new_set=\$ac_env_${ac_var}_set + eval ac_old_val=\$ac_cv_env_${ac_var}_value + eval ac_new_val=\$ac_env_${ac_var}_value + case $ac_old_set,$ac_new_set in + set,) + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: error: \`$ac_var' was set to \`$ac_old_val' in the previous run" >&5 +printf "%s\n" "$as_me: error: \`$ac_var' was set to \`$ac_old_val' in the previous run" >&2;} + ac_cache_corrupted=: ;; + ,set) + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: error: \`$ac_var' was not set in the previous run" >&5 +printf "%s\n" "$as_me: error: \`$ac_var' was not set in the previous run" >&2;} + ac_cache_corrupted=: ;; + ,);; + *) + if test "x$ac_old_val" != "x$ac_new_val"; then + # differences in whitespace do not lead to failure. + ac_old_val_w=`echo x $ac_old_val` + ac_new_val_w=`echo x $ac_new_val` + if test "$ac_old_val_w" != "$ac_new_val_w"; then + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: error: \`$ac_var' has changed since the previous run:" >&5 +printf "%s\n" "$as_me: error: \`$ac_var' has changed since the previous run:" >&2;} + ac_cache_corrupted=: + else + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: warning: ignoring whitespace changes in \`$ac_var' since the previous run:" >&5 +printf "%s\n" "$as_me: warning: ignoring whitespace changes in \`$ac_var' since the previous run:" >&2;} + eval $ac_var=\$ac_old_val + fi + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: former value: \`$ac_old_val'" >&5 +printf "%s\n" "$as_me: former value: \`$ac_old_val'" >&2;} + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: current value: \`$ac_new_val'" >&5 +printf "%s\n" "$as_me: current value: \`$ac_new_val'" >&2;} + fi;; + esac + # Pass precious variables to config.status. + if test "$ac_new_set" = set; then + case $ac_new_val in + *\'*) ac_arg=$ac_var=`printf "%s\n" "$ac_new_val" | sed "s/'/'\\\\\\\\''/g"` ;; + *) ac_arg=$ac_var=$ac_new_val ;; + esac + case " $ac_configure_args " in + *" '$ac_arg' "*) ;; # Avoid dups. Use of quotes ensures accuracy. + *) as_fn_append ac_configure_args " '$ac_arg'" ;; + esac + fi +done +if $ac_cache_corrupted; then + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 +printf "%s\n" "$as_me: error: in \`$ac_pwd':" >&2;} + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: error: changes in the environment can compromise the build" >&5 +printf "%s\n" "$as_me: error: changes in the environment can compromise the build" >&2;} + as_fn_error $? "run \`${MAKE-make} distclean' and/or \`rm $cache_file' + and start over" "$LINENO" 5 +fi +## -------------------- ## +## Main body of script. ## +## -------------------- ## + +ac_ext=c +ac_cpp='$CPP $CPPFLAGS' +ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_c_compiler_gnu + + + +ac_config_headers="$ac_config_headers ddconfig.h:ddconfig_in.h" + + +for ac_prog in gawk mawk nawk awk +do + # Extract the first word of "$ac_prog", so it can be a program name with args. +set dummy $ac_prog; ac_word=$2 +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +printf %s "checking for $ac_word... " >&6; } +if test ${ac_cv_prog_AWK+y} +then : + printf %s "(cached) " >&6 +else $as_nop + if test -n "$AWK"; then + ac_cv_prog_AWK="$AWK" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + case $as_dir in #((( + '') as_dir=./ ;; + */) ;; + *) as_dir=$as_dir/ ;; + esac + for ac_exec_ext in '' $ac_executable_extensions; do + if as_fn_executable_p "$as_dir$ac_word$ac_exec_ext"; then + ac_cv_prog_AWK="$ac_prog" + printf "%s\n" "$as_me:${as_lineno-$LINENO}: found $as_dir$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +AWK=$ac_cv_prog_AWK +if test -n "$AWK"; then + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: $AWK" >&5 +printf "%s\n" "$AWK" >&6; } +else + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: no" >&5 +printf "%s\n" "no" >&6; } +fi + + + test -n "$AWK" && break +done + + +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking version of the package" >&5 +printf %s "checking version of the package... " >&6; } +if test -f ${srcdir}/.version; then + { read VERSION; } < ${srcdir}/.version + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: $VERSION" >&5 +printf "%s\n" "$VERSION" >&6; } +else + VERSION="0.0.0" + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: unknown using 0.0.0" >&5 +printf "%s\n" "unknown using 0.0.0" >&6; } +fi +VERSIONHI=`echo $VERSION|$AWK 'BEGIN {FS="."} {print $1}'` +VERSIONLO=`echo $VERSION|$AWK 'BEGIN {FS="."} {print $2}'` +VERSIONP=`echo $VERSION|$AWK 'BEGIN {FS="."} {print $3}'` + + + + + +printf "%s\n" "#define VERSIONSTR \"${VERSION}\"" >>confdefs.h + + +printf "%s\n" "#define VERSIONHI $VERSIONHI" >>confdefs.h + + +printf "%s\n" "#define VERSIONLO $VERSIONLO" >>confdefs.h + + +printf "%s\n" "#define VERSIONP $VERSIONP" >>confdefs.h test "$program_prefix" != NONE && program_transform_name="s&^&$program_prefix&;$program_transform_name" @@ -2776,7 +3231,7 @@ # Double any \ or $. # By default was `s,x,x', remove it if useless. ac_script='s/[\\$]/&&/g;s/;s,x,x,$//' -program_transform_name=`$as_echo "$program_transform_name" | sed "$ac_script"` +program_transform_name=`printf "%s\n" "$program_transform_name" | sed "$ac_script"` # Some options #============== @@ -2788,11 +3243,12 @@ # Check whether --enable-ucsim was given. -if test "${enable_ucsim+set}" = set; then : +if test ${enable_ucsim+y} +then : enableval=$enable_ucsim; if test $enable_ucsim != "no"; then enable_ucsim="yes" fi -else +else $as_nop #default enable_ucsim="no" fi @@ -2801,158 +3257,268 @@ enable_ucsim="no" # Check whether --enable-dlso was given. -if test "${enable_dlso+set}" = set; then : +if test ${enable_dlso+y} +then : enableval=$enable_dlso; if test $enable_dlso != "no"; then enable_dlso="yes" fi -else +else $as_nop enable_dlso="no" fi # Check whether --enable-mcs51-port was given. -if test "${enable_mcs51_port+set}" = set; then : +if test ${enable_mcs51_port+y} +then : enableval=$enable_mcs51_port; if test $enable_mcs51_port != "no"; then enable_mcs51_port="yes" fi -else +else $as_nop enable_mcs51_port="yes" fi # Check whether --enable-ds390-port was given. -if test "${enable_ds390_port+set}" = set; then : +if test ${enable_ds390_port+y} +then : enableval=$enable_ds390_port; if test $enable_ds390_port != "no"; then enable_ds390_port="yes" fi -else +else $as_nop enable_ds390_port="yes" fi # Check whether --enable-avr-port was given. -if test "${enable_avr_port+set}" = set; then : +if test ${enable_avr_port+y} +then : enableval=$enable_avr_port; if test $enable_avr_port != "no"; then enable_avr_port="yes" fi -else - enable_avr_port="no" +else $as_nop + enable_avr_port="yes" fi # Check whether --enable-z80-port was given. -if test "${enable_z80_port+set}" = set; then : +if test ${enable_z80_port+y} +then : enableval=$enable_z80_port; if test $enable_z80_port != "no"; then enable_z80_port="yes" fi -else +else $as_nop enable_z80_port="yes" fi # Check whether --enable-z180-port was given. -if test "${enable_z180_port+set}" = set; then : +if test ${enable_z180_port+y} +then : enableval=$enable_z180_port; if test $enable_z180_port != "no"; then enable_z180_port="yes" fi -else +else $as_nop enable_z180_port="yes" fi # Check whether --enable-gbz80-port was given. -if test "${enable_gbz80_port+set}" = set; then : +if test ${enable_gbz80_port+y} +then : enableval=$enable_gbz80_port; if test $enable_gbz80_port != "no"; then enable_gbz80_port="yes" fi -else +else $as_nop enable_gbz80_port="yes" fi # Check whether --enable-r2k-port was given. -if test "${enable_r2k_port+set}" = set; then : +if test ${enable_r2k_port+y} +then : enableval=$enable_r2k_port; if test $enable_r2k_port != "no"; then enable_r2k_port="yes" fi -else +else $as_nop enable_r2k_port="yes" fi # Check whether --enable-r3ka-port was given. -if test "${enable_r3ka_port+set}" = set; then : +if test ${enable_r3ka_port+y} +then : enableval=$enable_r3ka_port; if test $enable_r3ka_port != "no"; then enable_r3ka_port="yes" fi -else +else $as_nop enable_r3ka_port="yes" fi # Check whether --enable-tlcs-port was given. -if test "${enable_tlcs_port+set}" = set; then : +if test ${enable_tlcs_port+y} +then : enableval=$enable_tlcs_port; if test $enable_tlcs_port != "no"; then enable_tlcs_port="yes" fi -else +else $as_nop enable_tlcs_port="yes" fi -# Check whether --enable-hc08-port was given. -if test "${enable_hc08_port+set}" = set; then : - enableval=$enable_hc08_port; if test $enable_hc08_port != "no"; then - enable_hc08_port="yes" +# Check whether --enable-m68hc08-port was given. +if test ${enable_m68hc08_port+y} +then : + enableval=$enable_m68hc08_port; if test $enable_m68hc08_port != "no"; then + enable_m68hc08_port="yes" fi -else - enable_hc08_port="yes" +else $as_nop + enable_m68hc08_port="yes" fi # Check whether --enable-s08-port was given. -if test "${enable_s08_port+set}" = set; then : +if test ${enable_s08_port+y} +then : enableval=$enable_s08_port; if test $enable_s08_port != "no"; then enable_s08_port="yes" fi -else +else $as_nop enable_s08_port="yes" fi # Check whether --enable-xa-port was given. -if test "${enable_xa_port+set}" = set; then : +if test ${enable_xa_port+y} +then : enableval=$enable_xa_port; if test $enable_xa_port != "no"; then enable_xa_port="yes" fi -else - enable_xa_port="no" +else $as_nop + enable_xa_port="yes" fi # Check whether --enable-stm8-port was given. -if test "${enable_stm8_port+set}" = set; then : +if test ${enable_stm8_port+y} +then : enableval=$enable_stm8_port; if test $enable_stm8_port != "no"; then enable_stm8_port="yes" fi -else +else $as_nop enable_stm8_port="yes" fi # Check whether --enable-pdk-port was given. -if test "${enable_pdk_port+set}" = set; then : +if test ${enable_pdk_port+y} +then : enableval=$enable_pdk_port; if test $enable_pdk_port != "no"; then enable_pdk_port="yes" fi -else +else $as_nop enable_pdk_port="yes" fi # Check whether --enable-st7-port was given. -if test "${enable_st7_port+set}" = set; then : +if test ${enable_st7_port+y} +then : enableval=$enable_st7_port; if test $enable_st7_port != "no"; then enable_st7_port="yes" fi -else - enable_st7_port="no" +else $as_nop + enable_st7_port="yes" fi -# Check whether --enable-serio was given. -if test "${enable_serio+set}" = set; then : - enableval=$enable_serio; if test $enable_serio != "no"; then - enable_serio="yes" +# Check whether --enable-p1516-port was given. +if test ${enable_p1516_port+y} +then : + enableval=$enable_p1516_port; if test $enable_p1516_port != "no"; then + enable_p1516_port="yes" fi -else - enable_serio="no" +else $as_nop + enable_p1516_port="yes" fi +# Check whether --enable-m6809-port was given. +if test ${enable_m6809_port+y} +then : + enableval=$enable_m6809_port; if test $enable_m6809_port != "no"; then + enable_m6809_port="yes" +fi +else $as_nop + enable_m6809_port="yes" +fi + + +# Check whether --enable-m6800-port was given. +if test ${enable_m6800_port+y} +then : + enableval=$enable_m6800_port; if test $enable_m6800_port != "no"; then + enable_m6800_port="yes" +fi +else $as_nop + enable_m6800_port="yes" +fi + + +# Check whether --enable-m68hc11-port was given. +if test ${enable_m68hc11_port+y} +then : + enableval=$enable_m68hc11_port; if test $enable_m68hc11_port != "no"; then + enable_m68hc11_port="yes" +fi +else $as_nop + enable_m68hc11_port="yes" +fi + + +# Check whether --enable-m68hc12-port was given. +if test ${enable_m68hc12_port+y} +then : + enableval=$enable_m68hc12_port; if test $enable_m68hc12_port != "no"; then + enable_m68hc12_port="yes" +fi +else $as_nop + enable_m68hc12_port="no" +fi + + +# Check whether --enable-mos6502-port was given. +if test ${enable_mos6502_port+y} +then : + enableval=$enable_mos6502_port; if test $enable_mos6502_port != "no"; then + enable_mos6502_port="yes" +fi +else $as_nop + enable_mos6502_port="yes" +fi + +# Check whether --enable-rxk-port was given. +if test ${enable_rxk_port+y} +then : + enableval=$enable_rxk_port; if test $enable_rxk_port != "no"; then + enable_rxk_port="yes" +fi +else $as_nop + enable_rxk_port="yes" +fi + +# Check whether --enable-pblaze-port was given. +if test ${enable_pblaze_port+y} +then : + enableval=$enable_pblaze_port; if test $enable_pblaze_port != "no"; then + enable_pblaze_port="yes" +fi +else $as_nop + enable_pblaze_port="yes" +fi + +# Check whether --enable-serio was given. +if test ${enable_serio+y} +then : + enableval=$enable_serio; if test $enable_serio != "no"; then + enable_serio="yes" +fi +else $as_nop + enable_serio="yes" +fi + + + + + + + + + + @@ -2971,25 +3537,29 @@ - # Check whether --enable-statistic was given. -if test "${enable_statistic+set}" = set; then : +if test ${enable_statistic+y} +then : enableval=$enable_statistic; if test $enable_statistic != "no"; then enable_statistic="yes" fi -else +else $as_nop enable_statistic="no" fi -cat >>confdefs.h <<_ACEOF -#define STATISTIC $enable_statistic -_ACEOF +printf "%s\n" "#define STATISTIC $enable_statistic" >>confdefs.h # Required programs #------------------- + + + + + + ac_ext=cpp ac_cpp='$CXXCPP $CPPFLAGS' ac_compile='$CXX -c $CXXFLAGS $CPPFLAGS conftest.$ac_ext >&5' @@ -3000,15 +3570,16 @@ CXX=$CCC else if test -n "$ac_tool_prefix"; then - for ac_prog in g++ c++ gpp aCC CC cxx cc++ cl.exe FCC KCC RCC xlC_r xlC + for ac_prog in g++ c++ gpp aCC CC cxx cc++ cl.exe FCC KCC RCC xlC_r xlC clang++ do # Extract the first word of "$ac_tool_prefix$ac_prog", so it can be a program name with args. set dummy $ac_tool_prefix$ac_prog; ac_word=$2 -{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 -$as_echo_n "checking for $ac_word... " >&6; } -if ${ac_cv_prog_CXX+:} false; then : - $as_echo_n "(cached) " >&6 -else +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +printf %s "checking for $ac_word... " >&6; } +if test ${ac_cv_prog_CXX+y} +then : + printf %s "(cached) " >&6 +else $as_nop if test -n "$CXX"; then ac_cv_prog_CXX="$CXX" # Let the user override the test. else @@ -3016,11 +3587,15 @@ for as_dir in $PATH do IFS=$as_save_IFS - test -z "$as_dir" && as_dir=. + case $as_dir in #((( + '') as_dir=./ ;; + */) ;; + *) as_dir=$as_dir/ ;; + esac for ac_exec_ext in '' $ac_executable_extensions; do - if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then + if as_fn_executable_p "$as_dir$ac_word$ac_exec_ext"; then ac_cv_prog_CXX="$ac_tool_prefix$ac_prog" - $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + printf "%s\n" "$as_me:${as_lineno-$LINENO}: found $as_dir$ac_word$ac_exec_ext" >&5 break 2 fi done @@ -3031,11 +3606,11 @@ fi CXX=$ac_cv_prog_CXX if test -n "$CXX"; then - { $as_echo "$as_me:${as_lineno-$LINENO}: result: $CXX" >&5 -$as_echo "$CXX" >&6; } + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: $CXX" >&5 +printf "%s\n" "$CXX" >&6; } else - { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 -$as_echo "no" >&6; } + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: no" >&5 +printf "%s\n" "no" >&6; } fi @@ -3044,15 +3619,16 @@ fi if test -z "$CXX"; then ac_ct_CXX=$CXX - for ac_prog in g++ c++ gpp aCC CC cxx cc++ cl.exe FCC KCC RCC xlC_r xlC + for ac_prog in g++ c++ gpp aCC CC cxx cc++ cl.exe FCC KCC RCC xlC_r xlC clang++ do # Extract the first word of "$ac_prog", so it can be a program name with args. set dummy $ac_prog; ac_word=$2 -{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 -$as_echo_n "checking for $ac_word... " >&6; } -if ${ac_cv_prog_ac_ct_CXX+:} false; then : - $as_echo_n "(cached) " >&6 -else +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +printf %s "checking for $ac_word... " >&6; } +if test ${ac_cv_prog_ac_ct_CXX+y} +then : + printf %s "(cached) " >&6 +else $as_nop if test -n "$ac_ct_CXX"; then ac_cv_prog_ac_ct_CXX="$ac_ct_CXX" # Let the user override the test. else @@ -3060,11 +3636,15 @@ for as_dir in $PATH do IFS=$as_save_IFS - test -z "$as_dir" && as_dir=. + case $as_dir in #((( + '') as_dir=./ ;; + */) ;; + *) as_dir=$as_dir/ ;; + esac for ac_exec_ext in '' $ac_executable_extensions; do - if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then + if as_fn_executable_p "$as_dir$ac_word$ac_exec_ext"; then ac_cv_prog_ac_ct_CXX="$ac_prog" - $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + printf "%s\n" "$as_me:${as_lineno-$LINENO}: found $as_dir$ac_word$ac_exec_ext" >&5 break 2 fi done @@ -3075,11 +3655,11 @@ fi ac_ct_CXX=$ac_cv_prog_ac_ct_CXX if test -n "$ac_ct_CXX"; then - { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_CXX" >&5 -$as_echo "$ac_ct_CXX" >&6; } + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: $ac_ct_CXX" >&5 +printf "%s\n" "$ac_ct_CXX" >&6; } else - { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 -$as_echo "no" >&6; } + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: no" >&5 +printf "%s\n" "no" >&6; } fi @@ -3091,8 +3671,8 @@ else case $cross_compiling:$ac_tool_warned in yes:) -{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 -$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 +printf "%s\n" "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} ac_tool_warned=yes ;; esac CXX=$ac_ct_CXX @@ -3102,7 +3682,7 @@ fi fi # Provide some information about the compiler. -$as_echo "$as_me:${as_lineno-$LINENO}: checking for C++ compiler version" >&5 +printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking for C++ compiler version" >&5 set X $ac_compile ac_compiler=$2 for ac_option in --version -v -V -qversion; do @@ -3112,7 +3692,7 @@ *) ac_try_echo=$ac_try;; esac eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" -$as_echo "$ac_try_echo"; } >&5 +printf "%s\n" "$ac_try_echo"; } >&5 (eval "$ac_compiler $ac_option >&5") 2>conftest.err ac_status=$? if test -s conftest.err; then @@ -3122,7 +3702,7 @@ cat conftest.er1 >&5 fi rm -f conftest.er1 conftest.err - $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + printf "%s\n" "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 test $ac_status = 0; } done @@ -3130,7 +3710,7 @@ /* end confdefs.h. */ int -main () +main (void) { ; @@ -3142,9 +3722,9 @@ # Try to create an executable without -o first, disregard a.out. # It will help us diagnose broken compilers, and finding out an intuition # of exeext. -{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether the C++ compiler works" >&5 -$as_echo_n "checking whether the C++ compiler works... " >&6; } -ac_link_default=`$as_echo "$ac_link" | sed 's/ -o *conftest[^ ]*//'` +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking whether the C++ compiler works" >&5 +printf %s "checking whether the C++ compiler works... " >&6; } +ac_link_default=`printf "%s\n" "$ac_link" | sed 's/ -o *conftest[^ ]*//'` # The possible output files: ac_files="a.out conftest.exe conftest a.exe a_out.exe b.out conftest.*" @@ -3165,11 +3745,12 @@ *) ac_try_echo=$ac_try;; esac eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" -$as_echo "$ac_try_echo"; } >&5 +printf "%s\n" "$ac_try_echo"; } >&5 (eval "$ac_link_default") 2>&5 ac_status=$? - $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 - test $ac_status = 0; }; then : + printf "%s\n" "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } +then : # Autoconf-2.13 could set the ac_cv_exeext variable to `no'. # So ignore a value of `no', otherwise this would lead to `EXEEXT = no' # in a Makefile. We should not override ac_cv_exeext if it was cached, @@ -3186,7 +3767,7 @@ # certainly right. break;; *.* ) - if test "${ac_cv_exeext+set}" = set && test "$ac_cv_exeext" != no; + if test ${ac_cv_exeext+y} && test "$ac_cv_exeext" != no; then :; else ac_cv_exeext=`expr "$ac_file" : '[^.]*$\..*$'` fi @@ -3202,44 +3783,46 @@ done test "$ac_cv_exeext" = no && ac_cv_exeext= -else +else $as_nop ac_file='' fi -if test -z "$ac_file"; then : - { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 -$as_echo "no" >&6; } -$as_echo "$as_me: failed program was:" >&5 +if test -z "$ac_file" +then : + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: no" >&5 +printf "%s\n" "no" >&6; } +printf "%s\n" "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 -{ { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 -$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} +{ { printf "%s\n" "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 +printf "%s\n" "$as_me: error: in \`$ac_pwd':" >&2;} as_fn_error 77 "C++ compiler cannot create executables See \`config.log' for more details" "$LINENO" 5; } -else - { $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5 -$as_echo "yes" >&6; } -fi -{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for C++ compiler default output file name" >&5 -$as_echo_n "checking for C++ compiler default output file name... " >&6; } -{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_file" >&5 -$as_echo "$ac_file" >&6; } +else $as_nop + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: yes" >&5 +printf "%s\n" "yes" >&6; } +fi +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking for C++ compiler default output file name" >&5 +printf %s "checking for C++ compiler default output file name... " >&6; } +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: $ac_file" >&5 +printf "%s\n" "$ac_file" >&6; } ac_exeext=$ac_cv_exeext rm -f -r a.out a.out.dSYM a.exe conftest$ac_cv_exeext b.out ac_clean_files=$ac_clean_files_save -{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for suffix of executables" >&5 -$as_echo_n "checking for suffix of executables... " >&6; } +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking for suffix of executables" >&5 +printf %s "checking for suffix of executables... " >&6; } if { { ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" -$as_echo "$ac_try_echo"; } >&5 +printf "%s\n" "$ac_try_echo"; } >&5 (eval "$ac_link") 2>&5 ac_status=$? - $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 - test $ac_status = 0; }; then : + printf "%s\n" "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } +then : # If both `conftest.exe' and `conftest' are `present' (well, observable) # catch `conftest.exe'. For instance with Cygwin, `ls conftest' will # work properly (i.e., refer to `conftest.exe'), while it won't with @@ -3253,15 +3836,15 @@ * ) break;; esac done -else - { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 -$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} +else $as_nop + { { printf "%s\n" "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 +printf "%s\n" "$as_me: error: in \`$ac_pwd':" >&2;} as_fn_error $? "cannot compute suffix of executables: cannot compile and link See \`config.log' for more details" "$LINENO" 5; } fi rm -f conftest conftest$ac_cv_exeext -{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_exeext" >&5 -$as_echo "$ac_cv_exeext" >&6; } +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: $ac_cv_exeext" >&5 +printf "%s\n" "$ac_cv_exeext" >&6; } rm -f conftest.$ac_ext EXEEXT=$ac_cv_exeext @@ -3270,7 +3853,7 @@ /* end confdefs.h. */ #include int -main () +main (void) { FILE *f = fopen ("conftest.out", "w"); return ferror (f) || fclose (f) != 0; @@ -3282,8 +3865,8 @@ ac_clean_files="$ac_clean_files conftest.out" # Check that the compiler produces executables we can run. If not, either # the compiler is broken, or we cross compile. -{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether we are cross compiling" >&5 -$as_echo_n "checking whether we are cross compiling... " >&6; } +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking whether we are cross compiling" >&5 +printf %s "checking whether we are cross compiling... " >&6; } if test "$cross_compiling" != yes; then { { ac_try="$ac_link" case "(($ac_try" in @@ -3291,10 +3874,10 @@ *) ac_try_echo=$ac_try;; esac eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" -$as_echo "$ac_try_echo"; } >&5 +printf "%s\n" "$ac_try_echo"; } >&5 (eval "$ac_link") 2>&5 ac_status=$? - $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + printf "%s\n" "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 test $ac_status = 0; } if { ac_try='./conftest$ac_cv_exeext' { { case "(($ac_try" in @@ -3302,39 +3885,40 @@ *) ac_try_echo=$ac_try;; esac eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" -$as_echo "$ac_try_echo"; } >&5 +printf "%s\n" "$ac_try_echo"; } >&5 (eval "$ac_try") 2>&5 ac_status=$? - $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + printf "%s\n" "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 test $ac_status = 0; }; }; then cross_compiling=no else if test "$cross_compiling" = maybe; then cross_compiling=yes else - { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 -$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} -as_fn_error $? "cannot run C++ compiled programs. + { { printf "%s\n" "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 +printf "%s\n" "$as_me: error: in \`$ac_pwd':" >&2;} +as_fn_error 77 "cannot run C++ compiled programs. If you meant to cross compile, use \`--host'. See \`config.log' for more details" "$LINENO" 5; } fi fi fi -{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $cross_compiling" >&5 -$as_echo "$cross_compiling" >&6; } +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: $cross_compiling" >&5 +printf "%s\n" "$cross_compiling" >&6; } rm -f conftest.$ac_ext conftest$ac_cv_exeext conftest.out ac_clean_files=$ac_clean_files_save -{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for suffix of object files" >&5 -$as_echo_n "checking for suffix of object files... " >&6; } -if ${ac_cv_objext+:} false; then : - $as_echo_n "(cached) " >&6 -else +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking for suffix of object files" >&5 +printf %s "checking for suffix of object files... " >&6; } +if test ${ac_cv_objext+y} +then : + printf %s "(cached) " >&6 +else $as_nop cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ int -main () +main (void) { ; @@ -3348,11 +3932,12 @@ *) ac_try_echo=$ac_try;; esac eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" -$as_echo "$ac_try_echo"; } >&5 +printf "%s\n" "$ac_try_echo"; } >&5 (eval "$ac_compile") 2>&5 ac_status=$? - $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 - test $ac_status = 0; }; then : + printf "%s\n" "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } +then : for ac_file in conftest.o conftest.obj conftest.*; do test -f "$ac_file" || continue; case $ac_file in @@ -3361,31 +3946,32 @@ break;; esac done -else - $as_echo "$as_me: failed program was:" >&5 +else $as_nop + printf "%s\n" "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 -{ { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 -$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} +{ { printf "%s\n" "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 +printf "%s\n" "$as_me: error: in \`$ac_pwd':" >&2;} as_fn_error $? "cannot compute suffix of object files: cannot compile See \`config.log' for more details" "$LINENO" 5; } fi rm -f conftest.$ac_cv_objext conftest.$ac_ext fi -{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_objext" >&5 -$as_echo "$ac_cv_objext" >&6; } +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: $ac_cv_objext" >&5 +printf "%s\n" "$ac_cv_objext" >&6; } OBJEXT=$ac_cv_objext ac_objext=$OBJEXT -{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether we are using the GNU C++ compiler" >&5 -$as_echo_n "checking whether we are using the GNU C++ compiler... " >&6; } -if ${ac_cv_cxx_compiler_gnu+:} false; then : - $as_echo_n "(cached) " >&6 -else +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking whether the compiler supports GNU C++" >&5 +printf %s "checking whether the compiler supports GNU C++... " >&6; } +if test ${ac_cv_cxx_compiler_gnu+y} +then : + printf %s "(cached) " >&6 +else $as_nop cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ int -main () +main (void) { #ifndef __GNUC__ choke me @@ -3395,29 +3981,33 @@ return 0; } _ACEOF -if ac_fn_cxx_try_compile "$LINENO"; then : +if ac_fn_cxx_try_compile "$LINENO" +then : ac_compiler_gnu=yes -else +else $as_nop ac_compiler_gnu=no fi -rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +rm -f core conftest.err conftest.$ac_objext conftest.beam conftest.$ac_ext ac_cv_cxx_compiler_gnu=$ac_compiler_gnu fi -{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_cxx_compiler_gnu" >&5 -$as_echo "$ac_cv_cxx_compiler_gnu" >&6; } +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: $ac_cv_cxx_compiler_gnu" >&5 +printf "%s\n" "$ac_cv_cxx_compiler_gnu" >&6; } +ac_compiler_gnu=$ac_cv_cxx_compiler_gnu + if test $ac_compiler_gnu = yes; then GXX=yes else GXX= fi -ac_test_CXXFLAGS=${CXXFLAGS+set} +ac_test_CXXFLAGS=${CXXFLAGS+y} ac_save_CXXFLAGS=$CXXFLAGS -{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether $CXX accepts -g" >&5 -$as_echo_n "checking whether $CXX accepts -g... " >&6; } -if ${ac_cv_prog_cxx_g+:} false; then : - $as_echo_n "(cached) " >&6 -else +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking whether $CXX accepts -g" >&5 +printf %s "checking whether $CXX accepts -g... " >&6; } +if test ${ac_cv_prog_cxx_g+y} +then : + printf %s "(cached) " >&6 +else $as_nop ac_save_cxx_werror_flag=$ac_cxx_werror_flag ac_cxx_werror_flag=yes ac_cv_prog_cxx_g=no @@ -3426,57 +4016,60 @@ /* end confdefs.h. */ int -main () +main (void) { ; return 0; } _ACEOF -if ac_fn_cxx_try_compile "$LINENO"; then : +if ac_fn_cxx_try_compile "$LINENO" +then : ac_cv_prog_cxx_g=yes -else +else $as_nop CXXFLAGS="" cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ int -main () +main (void) { ; return 0; } _ACEOF -if ac_fn_cxx_try_compile "$LINENO"; then : +if ac_fn_cxx_try_compile "$LINENO" +then : -else +else $as_nop ac_cxx_werror_flag=$ac_save_cxx_werror_flag CXXFLAGS="-g" cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ int -main () +main (void) { ; return 0; } _ACEOF -if ac_fn_cxx_try_compile "$LINENO"; then : +if ac_fn_cxx_try_compile "$LINENO" +then : ac_cv_prog_cxx_g=yes fi -rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +rm -f core conftest.err conftest.$ac_objext conftest.beam conftest.$ac_ext fi -rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +rm -f core conftest.err conftest.$ac_objext conftest.beam conftest.$ac_ext fi -rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +rm -f core conftest.err conftest.$ac_objext conftest.beam conftest.$ac_ext ac_cxx_werror_flag=$ac_save_cxx_werror_flag fi -{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_prog_cxx_g" >&5 -$as_echo "$ac_cv_prog_cxx_g" >&6; } -if test "$ac_test_CXXFLAGS" = set; then +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: $ac_cv_prog_cxx_g" >&5 +printf "%s\n" "$ac_cv_prog_cxx_g" >&6; } +if test $ac_test_CXXFLAGS; then CXXFLAGS=$ac_save_CXXFLAGS elif test $ac_cv_prog_cxx_g = yes; then if test "$GXX" = yes; then @@ -3491,6 +4084,100 @@ CXXFLAGS= fi fi +ac_prog_cxx_stdcxx=no +if test x$ac_prog_cxx_stdcxx = xno +then : + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking for $CXX option to enable C++11 features" >&5 +printf %s "checking for $CXX option to enable C++11 features... " >&6; } +if test ${ac_cv_prog_cxx_11+y} +then : + printf %s "(cached) " >&6 +else $as_nop + ac_cv_prog_cxx_11=no +ac_save_CXX=$CXX +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +$ac_cxx_conftest_cxx11_program +_ACEOF +for ac_arg in '' -std=gnu++11 -std=gnu++0x -std=c++11 -std=c++0x -qlanglvl=extended0x -AA +do + CXX="$ac_save_CXX $ac_arg" + if ac_fn_cxx_try_compile "$LINENO" +then : + ac_cv_prog_cxx_cxx11=$ac_arg +fi +rm -f core conftest.err conftest.$ac_objext conftest.beam + test "x$ac_cv_prog_cxx_cxx11" != "xno" && break +done +rm -f conftest.$ac_ext +CXX=$ac_save_CXX +fi + +if test "x$ac_cv_prog_cxx_cxx11" = xno +then : + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: unsupported" >&5 +printf "%s\n" "unsupported" >&6; } +else $as_nop + if test "x$ac_cv_prog_cxx_cxx11" = x +then : + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: none needed" >&5 +printf "%s\n" "none needed" >&6; } +else $as_nop + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: $ac_cv_prog_cxx_cxx11" >&5 +printf "%s\n" "$ac_cv_prog_cxx_cxx11" >&6; } + CXX="$CXX $ac_cv_prog_cxx_cxx11" +fi + ac_cv_prog_cxx_stdcxx=$ac_cv_prog_cxx_cxx11 + ac_prog_cxx_stdcxx=cxx11 +fi +fi +if test x$ac_prog_cxx_stdcxx = xno +then : + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking for $CXX option to enable C++98 features" >&5 +printf %s "checking for $CXX option to enable C++98 features... " >&6; } +if test ${ac_cv_prog_cxx_98+y} +then : + printf %s "(cached) " >&6 +else $as_nop + ac_cv_prog_cxx_98=no +ac_save_CXX=$CXX +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +$ac_cxx_conftest_cxx98_program +_ACEOF +for ac_arg in '' -std=gnu++98 -std=c++98 -qlanglvl=extended -AA +do + CXX="$ac_save_CXX $ac_arg" + if ac_fn_cxx_try_compile "$LINENO" +then : + ac_cv_prog_cxx_cxx98=$ac_arg +fi +rm -f core conftest.err conftest.$ac_objext conftest.beam + test "x$ac_cv_prog_cxx_cxx98" != "xno" && break +done +rm -f conftest.$ac_ext +CXX=$ac_save_CXX +fi + +if test "x$ac_cv_prog_cxx_cxx98" = xno +then : + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: unsupported" >&5 +printf "%s\n" "unsupported" >&6; } +else $as_nop + if test "x$ac_cv_prog_cxx_cxx98" = x +then : + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: none needed" >&5 +printf "%s\n" "none needed" >&6; } +else $as_nop + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: $ac_cv_prog_cxx_cxx98" >&5 +printf "%s\n" "$ac_cv_prog_cxx_cxx98" >&6; } + CXX="$CXX $ac_cv_prog_cxx_cxx98" +fi + ac_cv_prog_cxx_stdcxx=$ac_cv_prog_cxx_cxx98 + ac_prog_cxx_stdcxx=cxx98 +fi +fi + ac_ext=c ac_cpp='$CPP $CPPFLAGS' ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' @@ -3502,36 +4189,32 @@ ac_compile='$CXX -c $CXXFLAGS $CPPFLAGS conftest.$ac_ext >&5' ac_link='$CXX -o conftest$ac_exeext $CXXFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' ac_compiler_gnu=$ac_cv_cxx_compiler_gnu -{ $as_echo "$as_me:${as_lineno-$LINENO}: checking how to run the C++ preprocessor" >&5 -$as_echo_n "checking how to run the C++ preprocessor... " >&6; } +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking how to run the C++ preprocessor" >&5 +printf %s "checking how to run the C++ preprocessor... " >&6; } if test -z "$CXXCPP"; then - if ${ac_cv_prog_CXXCPP+:} false; then : - $as_echo_n "(cached) " >&6 -else - # Double quotes because CXXCPP needs to be expanded - for CXXCPP in "$CXX -E" "/lib/cpp" + if test ${ac_cv_prog_CXXCPP+y} +then : + printf %s "(cached) " >&6 +else $as_nop + # Double quotes because $CXX needs to be expanded + for CXXCPP in "$CXX -E" cpp /lib/cpp do ac_preproc_ok=false for ac_cxx_preproc_warn_flag in '' yes do # Use a header file that comes with gcc, so configuring glibc # with a fresh cross-compiler works. - # Prefer to if __STDC__ is defined, since - # exists even on freestanding compilers. # On the NeXT, cc -E runs the code through the compiler's parser, # not just through cpp. "Syntax error" is here to catch this case. cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ -#ifdef __STDC__ -# include -#else -# include -#endif +#include Syntax error _ACEOF -if ac_fn_cxx_try_cpp "$LINENO"; then : +if ac_fn_cxx_try_cpp "$LINENO" +then : -else +else $as_nop # Broken: fails on valid input. continue fi @@ -3543,10 +4226,11 @@ /* end confdefs.h. */ #include _ACEOF -if ac_fn_cxx_try_cpp "$LINENO"; then : +if ac_fn_cxx_try_cpp "$LINENO" +then : # Broken: success on invalid input. continue -else +else $as_nop # Passes both tests. ac_preproc_ok=: break @@ -3556,7 +4240,8 @@ done # Because of `break', _AC_PREPROC_IFELSE's cleaning code was skipped. rm -f conftest.i conftest.err conftest.$ac_ext -if $ac_preproc_ok; then : +if $ac_preproc_ok +then : break fi @@ -3568,29 +4253,24 @@ else ac_cv_prog_CXXCPP=$CXXCPP fi -{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $CXXCPP" >&5 -$as_echo "$CXXCPP" >&6; } +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: $CXXCPP" >&5 +printf "%s\n" "$CXXCPP" >&6; } ac_preproc_ok=false for ac_cxx_preproc_warn_flag in '' yes do # Use a header file that comes with gcc, so configuring glibc # with a fresh cross-compiler works. - # Prefer to if __STDC__ is defined, since - # exists even on freestanding compilers. # On the NeXT, cc -E runs the code through the compiler's parser, # not just through cpp. "Syntax error" is here to catch this case. cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ -#ifdef __STDC__ -# include -#else -# include -#endif +#include Syntax error _ACEOF -if ac_fn_cxx_try_cpp "$LINENO"; then : +if ac_fn_cxx_try_cpp "$LINENO" +then : -else +else $as_nop # Broken: fails on valid input. continue fi @@ -3602,10 +4282,11 @@ /* end confdefs.h. */ #include _ACEOF -if ac_fn_cxx_try_cpp "$LINENO"; then : +if ac_fn_cxx_try_cpp "$LINENO" +then : # Broken: success on invalid input. continue -else +else $as_nop # Passes both tests. ac_preproc_ok=: break @@ -3615,11 +4296,12 @@ done # Because of `break', _AC_PREPROC_IFELSE's cleaning code was skipped. rm -f conftest.i conftest.err conftest.$ac_ext -if $ac_preproc_ok; then : +if $ac_preproc_ok +then : -else - { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 -$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} +else $as_nop + { { printf "%s\n" "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 +printf "%s\n" "$as_me: error: in \`$ac_pwd':" >&2;} as_fn_error $? "C++ preprocessor \"$CXXCPP\" fails sanity check See \`config.log' for more details" "$LINENO" 5; } fi @@ -3630,36 +4312,9 @@ ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' ac_compiler_gnu=$ac_cv_c_compiler_gnu -ac_aux_dir= -for ac_dir in "$srcdir" "$srcdir/.." "$srcdir/../.."; do - if test -f "$ac_dir/install-sh"; then - ac_aux_dir=$ac_dir - ac_install_sh="$ac_aux_dir/install-sh -c" - break - elif test -f "$ac_dir/install.sh"; then - ac_aux_dir=$ac_dir - ac_install_sh="$ac_aux_dir/install.sh -c" - break - elif test -f "$ac_dir/shtool"; then - ac_aux_dir=$ac_dir - ac_install_sh="$ac_aux_dir/shtool install -c" - break - fi -done -if test -z "$ac_aux_dir"; then - as_fn_error $? "cannot find install-sh, install.sh, or shtool in \"$srcdir\" \"$srcdir/..\" \"$srcdir/../..\"" "$LINENO" 5 -fi - -# These three variables are undocumented and unsupported, -# and are intended to be withdrawn in a future Autoconf release. -# They can cause serious problems if a builder's source tree is in a directory -# whose full name contains unusual characters. -ac_config_guess="$SHELL $ac_aux_dir/config.guess" # Please don't use this var. -ac_config_sub="$SHELL $ac_aux_dir/config.sub" # Please don't use this var. -ac_configure="$SHELL $ac_aux_dir/configure" # Please don't use this var. -# Find a good install program. We prefer a C program (faster), + # Find a good install program. We prefer a C program (faster), # so one script is as good as another. But avoid the broken or # incompatible versions: # SysV /etc/install, /usr/sbin/install @@ -3673,20 +4328,25 @@ # OS/2's system install, which has a completely different semantic # ./install, which can be erroneously created by make from ./install.sh. # Reject install programs that cannot install multiple files. -{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for a BSD-compatible install" >&5 -$as_echo_n "checking for a BSD-compatible install... " >&6; } +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking for a BSD-compatible install" >&5 +printf %s "checking for a BSD-compatible install... " >&6; } if test -z "$INSTALL"; then -if ${ac_cv_path_install+:} false; then : - $as_echo_n "(cached) " >&6 -else +if test ${ac_cv_path_install+y} +then : + printf %s "(cached) " >&6 +else $as_nop as_save_IFS=$IFS; IFS=$PATH_SEPARATOR for as_dir in $PATH do IFS=$as_save_IFS - test -z "$as_dir" && as_dir=. - # Account for people who put trailing slashes in PATH elements. -case $as_dir/ in #(( - ./ | .// | /[cC]/* | \ + case $as_dir in #((( + '') as_dir=./ ;; + */) ;; + *) as_dir=$as_dir/ ;; + esac + # Account for fact that we put trailing slashes in our PATH walk. +case $as_dir in #(( + ./ | /[cC]/* | \ /etc/* | /usr/sbin/* | /usr/etc/* | /sbin/* | /usr/afsws/bin/* | \ ?:[\\/]os2[\\/]install[\\/]* | ?:[\\/]OS2[\\/]INSTALL[\\/]* | \ /usr/ucb/* ) ;; @@ -3696,13 +4356,13 @@ # by default. for ac_prog in ginstall scoinst install; do for ac_exec_ext in '' $ac_executable_extensions; do - if as_fn_executable_p "$as_dir/$ac_prog$ac_exec_ext"; then + if as_fn_executable_p "$as_dir$ac_prog$ac_exec_ext"; then if test $ac_prog = install && - grep dspmsg "$as_dir/$ac_prog$ac_exec_ext" >/dev/null 2>&1; then + grep dspmsg "$as_dir$ac_prog$ac_exec_ext" >/dev/null 2>&1; then # AIX install. It has an incompatible calling convention. : elif test $ac_prog = install && - grep pwplus "$as_dir/$ac_prog$ac_exec_ext" >/dev/null 2>&1; then + grep pwplus "$as_dir$ac_prog$ac_exec_ext" >/dev/null 2>&1; then # program-specific install script used by HP pwplus--don't use. : else @@ -3710,12 +4370,12 @@ echo one > conftest.one echo two > conftest.two mkdir conftest.dir - if "$as_dir/$ac_prog$ac_exec_ext" -c conftest.one conftest.two "`pwd`/conftest.dir" && + if "$as_dir$ac_prog$ac_exec_ext" -c conftest.one conftest.two "`pwd`/conftest.dir/" && test -s conftest.one && test -s conftest.two && test -s conftest.dir/conftest.one && test -s conftest.dir/conftest.two then - ac_cv_path_install="$as_dir/$ac_prog$ac_exec_ext -c" + ac_cv_path_install="$as_dir$ac_prog$ac_exec_ext -c" break 3 fi fi @@ -3731,7 +4391,7 @@ rm -rf conftest.one conftest.two conftest.dir fi - if test "${ac_cv_path_install+set}" = set; then + if test ${ac_cv_path_install+y}; then INSTALL=$ac_cv_path_install else # As a last resort, use the slow shell script. Don't cache a @@ -3741,8 +4401,8 @@ INSTALL=$ac_install_sh fi fi -{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $INSTALL" >&5 -$as_echo "$INSTALL" >&6; } +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: $INSTALL" >&5 +printf "%s\n" "$INSTALL" >&6; } # Use test -z because SunOS4 sh mishandles braces in ${var-val}. # It thinks the first close brace ends the variable substitution. @@ -3755,11 +4415,12 @@ if test -n "$ac_tool_prefix"; then # Extract the first word of "${ac_tool_prefix}ranlib", so it can be a program name with args. set dummy ${ac_tool_prefix}ranlib; ac_word=$2 -{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 -$as_echo_n "checking for $ac_word... " >&6; } -if ${ac_cv_prog_RANLIB+:} false; then : - $as_echo_n "(cached) " >&6 -else +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +printf %s "checking for $ac_word... " >&6; } +if test ${ac_cv_prog_RANLIB+y} +then : + printf %s "(cached) " >&6 +else $as_nop if test -n "$RANLIB"; then ac_cv_prog_RANLIB="$RANLIB" # Let the user override the test. else @@ -3767,11 +4428,15 @@ for as_dir in $PATH do IFS=$as_save_IFS - test -z "$as_dir" && as_dir=. + case $as_dir in #((( + '') as_dir=./ ;; + */) ;; + *) as_dir=$as_dir/ ;; + esac for ac_exec_ext in '' $ac_executable_extensions; do - if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then + if as_fn_executable_p "$as_dir$ac_word$ac_exec_ext"; then ac_cv_prog_RANLIB="${ac_tool_prefix}ranlib" - $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + printf "%s\n" "$as_me:${as_lineno-$LINENO}: found $as_dir$ac_word$ac_exec_ext" >&5 break 2 fi done @@ -3782,11 +4447,11 @@ fi RANLIB=$ac_cv_prog_RANLIB if test -n "$RANLIB"; then - { $as_echo "$as_me:${as_lineno-$LINENO}: result: $RANLIB" >&5 -$as_echo "$RANLIB" >&6; } + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: $RANLIB" >&5 +printf "%s\n" "$RANLIB" >&6; } else - { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 -$as_echo "no" >&6; } + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: no" >&5 +printf "%s\n" "no" >&6; } fi @@ -3795,11 +4460,12 @@ ac_ct_RANLIB=$RANLIB # Extract the first word of "ranlib", so it can be a program name with args. set dummy ranlib; ac_word=$2 -{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 -$as_echo_n "checking for $ac_word... " >&6; } -if ${ac_cv_prog_ac_ct_RANLIB+:} false; then : - $as_echo_n "(cached) " >&6 -else +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +printf %s "checking for $ac_word... " >&6; } +if test ${ac_cv_prog_ac_ct_RANLIB+y} +then : + printf %s "(cached) " >&6 +else $as_nop if test -n "$ac_ct_RANLIB"; then ac_cv_prog_ac_ct_RANLIB="$ac_ct_RANLIB" # Let the user override the test. else @@ -3807,11 +4473,15 @@ for as_dir in $PATH do IFS=$as_save_IFS - test -z "$as_dir" && as_dir=. + case $as_dir in #((( + '') as_dir=./ ;; + */) ;; + *) as_dir=$as_dir/ ;; + esac for ac_exec_ext in '' $ac_executable_extensions; do - if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then + if as_fn_executable_p "$as_dir$ac_word$ac_exec_ext"; then ac_cv_prog_ac_ct_RANLIB="ranlib" - $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + printf "%s\n" "$as_me:${as_lineno-$LINENO}: found $as_dir$ac_word$ac_exec_ext" >&5 break 2 fi done @@ -3822,11 +4492,11 @@ fi ac_ct_RANLIB=$ac_cv_prog_ac_ct_RANLIB if test -n "$ac_ct_RANLIB"; then - { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_RANLIB" >&5 -$as_echo "$ac_ct_RANLIB" >&6; } + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: $ac_ct_RANLIB" >&5 +printf "%s\n" "$ac_ct_RANLIB" >&6; } else - { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 -$as_echo "no" >&6; } + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: no" >&5 +printf "%s\n" "no" >&6; } fi if test "x$ac_ct_RANLIB" = x; then @@ -3834,8 +4504,8 @@ else case $cross_compiling:$ac_tool_warned in yes:) -{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 -$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 +printf "%s\n" "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} ac_tool_warned=yes ;; esac RANLIB=$ac_ct_RANLIB @@ -3848,11 +4518,12 @@ if test -n "$ac_tool_prefix"; then # Extract the first word of "${ac_tool_prefix}strip", so it can be a program name with args. set dummy ${ac_tool_prefix}strip; ac_word=$2 -{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 -$as_echo_n "checking for $ac_word... " >&6; } -if ${ac_cv_prog_STRIP+:} false; then : - $as_echo_n "(cached) " >&6 -else +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +printf %s "checking for $ac_word... " >&6; } +if test ${ac_cv_prog_STRIP+y} +then : + printf %s "(cached) " >&6 +else $as_nop if test -n "$STRIP"; then ac_cv_prog_STRIP="$STRIP" # Let the user override the test. else @@ -3860,11 +4531,15 @@ for as_dir in $PATH do IFS=$as_save_IFS - test -z "$as_dir" && as_dir=. + case $as_dir in #((( + '') as_dir=./ ;; + */) ;; + *) as_dir=$as_dir/ ;; + esac for ac_exec_ext in '' $ac_executable_extensions; do - if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then + if as_fn_executable_p "$as_dir$ac_word$ac_exec_ext"; then ac_cv_prog_STRIP="${ac_tool_prefix}strip" - $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + printf "%s\n" "$as_me:${as_lineno-$LINENO}: found $as_dir$ac_word$ac_exec_ext" >&5 break 2 fi done @@ -3875,11 +4550,11 @@ fi STRIP=$ac_cv_prog_STRIP if test -n "$STRIP"; then - { $as_echo "$as_me:${as_lineno-$LINENO}: result: $STRIP" >&5 -$as_echo "$STRIP" >&6; } + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: $STRIP" >&5 +printf "%s\n" "$STRIP" >&6; } else - { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 -$as_echo "no" >&6; } + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: no" >&5 +printf "%s\n" "no" >&6; } fi @@ -3888,11 +4563,12 @@ ac_ct_STRIP=$STRIP # Extract the first word of "strip", so it can be a program name with args. set dummy strip; ac_word=$2 -{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 -$as_echo_n "checking for $ac_word... " >&6; } -if ${ac_cv_prog_ac_ct_STRIP+:} false; then : - $as_echo_n "(cached) " >&6 -else +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +printf %s "checking for $ac_word... " >&6; } +if test ${ac_cv_prog_ac_ct_STRIP+y} +then : + printf %s "(cached) " >&6 +else $as_nop if test -n "$ac_ct_STRIP"; then ac_cv_prog_ac_ct_STRIP="$ac_ct_STRIP" # Let the user override the test. else @@ -3900,11 +4576,15 @@ for as_dir in $PATH do IFS=$as_save_IFS - test -z "$as_dir" && as_dir=. + case $as_dir in #((( + '') as_dir=./ ;; + */) ;; + *) as_dir=$as_dir/ ;; + esac for ac_exec_ext in '' $ac_executable_extensions; do - if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then + if as_fn_executable_p "$as_dir$ac_word$ac_exec_ext"; then ac_cv_prog_ac_ct_STRIP="strip" - $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + printf "%s\n" "$as_me:${as_lineno-$LINENO}: found $as_dir$ac_word$ac_exec_ext" >&5 break 2 fi done @@ -3915,11 +4595,11 @@ fi ac_ct_STRIP=$ac_cv_prog_ac_ct_STRIP if test -n "$ac_ct_STRIP"; then - { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_STRIP" >&5 -$as_echo "$ac_ct_STRIP" >&6; } + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: $ac_ct_STRIP" >&5 +printf "%s\n" "$ac_ct_STRIP" >&6; } else - { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 -$as_echo "no" >&6; } + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: no" >&5 +printf "%s\n" "no" >&6; } fi if test "x$ac_ct_STRIP" = x; then @@ -3927,8 +4607,8 @@ else case $cross_compiling:$ac_tool_warned in yes:) -{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 -$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 +printf "%s\n" "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} ac_tool_warned=yes ;; esac STRIP=$ac_ct_STRIP @@ -3940,11 +4620,12 @@ if test -n "$ac_tool_prefix"; then # Extract the first word of "${ac_tool_prefix}ar", so it can be a program name with args. set dummy ${ac_tool_prefix}ar; ac_word=$2 -{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 -$as_echo_n "checking for $ac_word... " >&6; } -if ${ac_cv_prog_AR+:} false; then : - $as_echo_n "(cached) " >&6 -else +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +printf %s "checking for $ac_word... " >&6; } +if test ${ac_cv_prog_AR+y} +then : + printf %s "(cached) " >&6 +else $as_nop if test -n "$AR"; then ac_cv_prog_AR="$AR" # Let the user override the test. else @@ -3952,11 +4633,15 @@ for as_dir in $PATH do IFS=$as_save_IFS - test -z "$as_dir" && as_dir=. + case $as_dir in #((( + '') as_dir=./ ;; + */) ;; + *) as_dir=$as_dir/ ;; + esac for ac_exec_ext in '' $ac_executable_extensions; do - if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then + if as_fn_executable_p "$as_dir$ac_word$ac_exec_ext"; then ac_cv_prog_AR="${ac_tool_prefix}ar" - $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + printf "%s\n" "$as_me:${as_lineno-$LINENO}: found $as_dir$ac_word$ac_exec_ext" >&5 break 2 fi done @@ -3967,11 +4652,11 @@ fi AR=$ac_cv_prog_AR if test -n "$AR"; then - { $as_echo "$as_me:${as_lineno-$LINENO}: result: $AR" >&5 -$as_echo "$AR" >&6; } + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: $AR" >&5 +printf "%s\n" "$AR" >&6; } else - { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 -$as_echo "no" >&6; } + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: no" >&5 +printf "%s\n" "no" >&6; } fi @@ -3980,11 +4665,12 @@ ac_ct_AR=$AR # Extract the first word of "ar", so it can be a program name with args. set dummy ar; ac_word=$2 -{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 -$as_echo_n "checking for $ac_word... " >&6; } -if ${ac_cv_prog_ac_ct_AR+:} false; then : - $as_echo_n "(cached) " >&6 -else +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +printf %s "checking for $ac_word... " >&6; } +if test ${ac_cv_prog_ac_ct_AR+y} +then : + printf %s "(cached) " >&6 +else $as_nop if test -n "$ac_ct_AR"; then ac_cv_prog_ac_ct_AR="$ac_ct_AR" # Let the user override the test. else @@ -3992,11 +4678,15 @@ for as_dir in $PATH do IFS=$as_save_IFS - test -z "$as_dir" && as_dir=. + case $as_dir in #((( + '') as_dir=./ ;; + */) ;; + *) as_dir=$as_dir/ ;; + esac for ac_exec_ext in '' $ac_executable_extensions; do - if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then + if as_fn_executable_p "$as_dir$ac_word$ac_exec_ext"; then ac_cv_prog_ac_ct_AR="ar" - $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + printf "%s\n" "$as_me:${as_lineno-$LINENO}: found $as_dir$ac_word$ac_exec_ext" >&5 break 2 fi done @@ -4007,11 +4697,11 @@ fi ac_ct_AR=$ac_cv_prog_ac_ct_AR if test -n "$ac_ct_AR"; then - { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_AR" >&5 -$as_echo "$ac_ct_AR" >&6; } + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: $ac_ct_AR" >&5 +printf "%s\n" "$ac_ct_AR" >&6; } else - { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 -$as_echo "no" >&6; } + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: no" >&5 +printf "%s\n" "no" >&6; } fi if test "x$ac_ct_AR" = x; then @@ -4019,8 +4709,8 @@ else case $cross_compiling:$ac_tool_warned in yes:) -{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 -$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 +printf "%s\n" "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} ac_tool_warned=yes ;; esac AR=$ac_ct_AR @@ -4029,256 +4719,6 @@ AR="$ac_cv_prog_AR" fi -if test -n "$ac_tool_prefix"; then - # Extract the first word of "${ac_tool_prefix}srec_cat", so it can be a program name with args. -set dummy ${ac_tool_prefix}srec_cat; ac_word=$2 -{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 -$as_echo_n "checking for $ac_word... " >&6; } -if ${ac_cv_prog_SREC_CAT+:} false; then : - $as_echo_n "(cached) " >&6 -else - if test -n "$SREC_CAT"; then - ac_cv_prog_SREC_CAT="$SREC_CAT" # Let the user override the test. -else -as_save_IFS=$IFS; IFS=$PATH_SEPARATOR -for as_dir in $PATH -do - IFS=$as_save_IFS - test -z "$as_dir" && as_dir=. - for ac_exec_ext in '' $ac_executable_extensions; do - if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then - ac_cv_prog_SREC_CAT="${ac_tool_prefix}srec_cat" - $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 - break 2 - fi -done - done -IFS=$as_save_IFS - -fi -fi -SREC_CAT=$ac_cv_prog_SREC_CAT -if test -n "$SREC_CAT"; then - { $as_echo "$as_me:${as_lineno-$LINENO}: result: $SREC_CAT" >&5 -$as_echo "$SREC_CAT" >&6; } -else - { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 -$as_echo "no" >&6; } -fi - - -fi -if test -z "$ac_cv_prog_SREC_CAT"; then - ac_ct_SREC_CAT=$SREC_CAT - # Extract the first word of "srec_cat", so it can be a program name with args. -set dummy srec_cat; ac_word=$2 -{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 -$as_echo_n "checking for $ac_word... " >&6; } -if ${ac_cv_prog_ac_ct_SREC_CAT+:} false; then : - $as_echo_n "(cached) " >&6 -else - if test -n "$ac_ct_SREC_CAT"; then - ac_cv_prog_ac_ct_SREC_CAT="$ac_ct_SREC_CAT" # Let the user override the test. -else -as_save_IFS=$IFS; IFS=$PATH_SEPARATOR -for as_dir in $PATH -do - IFS=$as_save_IFS - test -z "$as_dir" && as_dir=. - for ac_exec_ext in '' $ac_executable_extensions; do - if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then - ac_cv_prog_ac_ct_SREC_CAT="srec_cat" - $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 - break 2 - fi -done - done -IFS=$as_save_IFS - -fi -fi -ac_ct_SREC_CAT=$ac_cv_prog_ac_ct_SREC_CAT -if test -n "$ac_ct_SREC_CAT"; then - { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_SREC_CAT" >&5 -$as_echo "$ac_ct_SREC_CAT" >&6; } -else - { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 -$as_echo "no" >&6; } -fi - - if test "x$ac_ct_SREC_CAT" = x; then - SREC_CAT="" - else - case $cross_compiling:$ac_tool_warned in -yes:) -{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 -$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} -ac_tool_warned=yes ;; -esac - SREC_CAT=$ac_ct_SREC_CAT - fi -else - SREC_CAT="$ac_cv_prog_SREC_CAT" -fi - - -enable_dlopen=yes - - - -case `pwd` in - *\ * | *\ *) - { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: Libtool does not cope well with whitespace in \`pwd\`" >&5 -$as_echo "$as_me: WARNING: Libtool does not cope well with whitespace in \`pwd\`" >&2;} ;; -esac - - - -macro_version='2.4.6' -macro_revision='2.4.6' - - - - - - - - - - - - - -ltmain=$ac_aux_dir/ltmain.sh - -# Make sure we can run config.sub. -$SHELL "$ac_aux_dir/config.sub" sun4 >/dev/null 2>&1 || - as_fn_error $? "cannot run $SHELL $ac_aux_dir/config.sub" "$LINENO" 5 - -{ $as_echo "$as_me:${as_lineno-$LINENO}: checking build system type" >&5 -$as_echo_n "checking build system type... " >&6; } -if ${ac_cv_build+:} false; then : - $as_echo_n "(cached) " >&6 -else - ac_build_alias=$build_alias -test "x$ac_build_alias" = x && - ac_build_alias=`$SHELL "$ac_aux_dir/config.guess"` -test "x$ac_build_alias" = x && - as_fn_error $? "cannot guess build type; you must specify one" "$LINENO" 5 -ac_cv_build=`$SHELL "$ac_aux_dir/config.sub" $ac_build_alias` || - as_fn_error $? "$SHELL $ac_aux_dir/config.sub $ac_build_alias failed" "$LINENO" 5 - -fi -{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_build" >&5 -$as_echo "$ac_cv_build" >&6; } -case $ac_cv_build in -*-*-*) ;; -*) as_fn_error $? "invalid value of canonical build" "$LINENO" 5;; -esac -build=$ac_cv_build -ac_save_IFS=$IFS; IFS='-' -set x $ac_cv_build -shift -build_cpu=$1 -build_vendor=$2 -shift; shift -# Remember, the first character of IFS is used to create $*, -# except with old shells: -build_os=$* -IFS=$ac_save_IFS -case $build_os in *\ *) build_os=`echo "$build_os" | sed 's/ /-/g'`;; esac - - -{ $as_echo "$as_me:${as_lineno-$LINENO}: checking host system type" >&5 -$as_echo_n "checking host system type... " >&6; } -if ${ac_cv_host+:} false; then : - $as_echo_n "(cached) " >&6 -else - if test "x$host_alias" = x; then - ac_cv_host=$ac_cv_build -else - ac_cv_host=`$SHELL "$ac_aux_dir/config.sub" $host_alias` || - as_fn_error $? "$SHELL $ac_aux_dir/config.sub $host_alias failed" "$LINENO" 5 -fi - -fi -{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_host" >&5 -$as_echo "$ac_cv_host" >&6; } -case $ac_cv_host in -*-*-*) ;; -*) as_fn_error $? "invalid value of canonical host" "$LINENO" 5;; -esac -host=$ac_cv_host -ac_save_IFS=$IFS; IFS='-' -set x $ac_cv_host -shift -host_cpu=$1 -host_vendor=$2 -shift; shift -# Remember, the first character of IFS is used to create $*, -# except with old shells: -host_os=$* -IFS=$ac_save_IFS -case $host_os in *\ *) host_os=`echo "$host_os" | sed 's/ /-/g'`;; esac - - -# Backslashify metacharacters that are still active within -# double-quoted strings. -sed_quote_subst='s/$["`$\\]$/\\\1/g' - -# Same as above, but do not quote variable references. -double_quote_subst='s/$["`\\]$/\\\1/g' - -# Sed substitution to delay expansion of an escaped shell variable in a -# double_quote_subst'ed string. -delay_variable_subst='s/\\\\\\\\\\\$/\\\\\\$/g' - -# Sed substitution to delay expansion of an escaped single quote. -delay_single_quote_subst='s/'\''/'\'\\\\\\\'\''/g' - -# Sed substitution to avoid accidental globbing in evaled expressions -no_glob_subst='s/\*/\\\*/g' - -ECHO='\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\' -ECHO=$ECHO$ECHO$ECHO$ECHO$ECHO -ECHO=$ECHO$ECHO$ECHO$ECHO$ECHO$ECHO - -{ $as_echo "$as_me:${as_lineno-$LINENO}: checking how to print strings" >&5 -$as_echo_n "checking how to print strings... " >&6; } -# Test print first, because it will be a builtin if present. -if test "X`( print -r -- -n ) 2>/dev/null`" = X-n && \ - test "X`print -r -- $ECHO 2>/dev/null`" = "X$ECHO"; then - ECHO='print -r --' -elif test "X`printf %s $ECHO 2>/dev/null`" = "X$ECHO"; then - ECHO='printf %s\n' -else - # Use this function as a fallback that always works. - func_fallback_echo () - { - eval 'cat <<_LTECHO_EOF -$1 -_LTECHO_EOF' - } - ECHO='func_fallback_echo' -fi - -# func_echo_all arg... -# Invoke $ECHO with all args, space-separated. -func_echo_all () -{ - $ECHO "" -} - -case $ECHO in - printf*) { $as_echo "$as_me:${as_lineno-$LINENO}: result: printf" >&5 -$as_echo "printf" >&6; } ;; - print*) { $as_echo "$as_me:${as_lineno-$LINENO}: result: print -r" >&5 -$as_echo "print -r" >&6; } ;; - *) { $as_echo "$as_me:${as_lineno-$LINENO}: result: cat" >&5 -$as_echo "cat" >&6; } ;; -esac - - @@ -4299,11 +4739,12 @@ if test -n "$ac_tool_prefix"; then # Extract the first word of "${ac_tool_prefix}gcc", so it can be a program name with args. set dummy ${ac_tool_prefix}gcc; ac_word=$2 -{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 -$as_echo_n "checking for $ac_word... " >&6; } -if ${ac_cv_prog_CC+:} false; then : - $as_echo_n "(cached) " >&6 -else +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +printf %s "checking for $ac_word... " >&6; } +if test ${ac_cv_prog_CC+y} +then : + printf %s "(cached) " >&6 +else $as_nop if test -n "$CC"; then ac_cv_prog_CC="$CC" # Let the user override the test. else @@ -4311,11 +4752,15 @@ for as_dir in $PATH do IFS=$as_save_IFS - test -z "$as_dir" && as_dir=. + case $as_dir in #((( + '') as_dir=./ ;; + */) ;; + *) as_dir=$as_dir/ ;; + esac for ac_exec_ext in '' $ac_executable_extensions; do - if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then + if as_fn_executable_p "$as_dir$ac_word$ac_exec_ext"; then ac_cv_prog_CC="${ac_tool_prefix}gcc" - $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + printf "%s\n" "$as_me:${as_lineno-$LINENO}: found $as_dir$ac_word$ac_exec_ext" >&5 break 2 fi done @@ -4326,11 +4771,11 @@ fi CC=$ac_cv_prog_CC if test -n "$CC"; then - { $as_echo "$as_me:${as_lineno-$LINENO}: result: $CC" >&5 -$as_echo "$CC" >&6; } + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: $CC" >&5 +printf "%s\n" "$CC" >&6; } else - { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 -$as_echo "no" >&6; } + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: no" >&5 +printf "%s\n" "no" >&6; } fi @@ -4339,11 +4784,12 @@ ac_ct_CC=$CC # Extract the first word of "gcc", so it can be a program name with args. set dummy gcc; ac_word=$2 -{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 -$as_echo_n "checking for $ac_word... " >&6; } -if ${ac_cv_prog_ac_ct_CC+:} false; then : - $as_echo_n "(cached) " >&6 -else +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +printf %s "checking for $ac_word... " >&6; } +if test ${ac_cv_prog_ac_ct_CC+y} +then : + printf %s "(cached) " >&6 +else $as_nop if test -n "$ac_ct_CC"; then ac_cv_prog_ac_ct_CC="$ac_ct_CC" # Let the user override the test. else @@ -4351,11 +4797,15 @@ for as_dir in $PATH do IFS=$as_save_IFS - test -z "$as_dir" && as_dir=. + case $as_dir in #((( + '') as_dir=./ ;; + */) ;; + *) as_dir=$as_dir/ ;; + esac for ac_exec_ext in '' $ac_executable_extensions; do - if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then + if as_fn_executable_p "$as_dir$ac_word$ac_exec_ext"; then ac_cv_prog_ac_ct_CC="gcc" - $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + printf "%s\n" "$as_me:${as_lineno-$LINENO}: found $as_dir$ac_word$ac_exec_ext" >&5 break 2 fi done @@ -4366,11 +4816,11 @@ fi ac_ct_CC=$ac_cv_prog_ac_ct_CC if test -n "$ac_ct_CC"; then - { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_CC" >&5 -$as_echo "$ac_ct_CC" >&6; } + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: $ac_ct_CC" >&5 +printf "%s\n" "$ac_ct_CC" >&6; } else - { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 -$as_echo "no" >&6; } + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: no" >&5 +printf "%s\n" "no" >&6; } fi if test "x$ac_ct_CC" = x; then @@ -4378,8 +4828,8 @@ else case $cross_compiling:$ac_tool_warned in yes:) -{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 -$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 +printf "%s\n" "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} ac_tool_warned=yes ;; esac CC=$ac_ct_CC @@ -4392,11 +4842,12 @@ if test -n "$ac_tool_prefix"; then # Extract the first word of "${ac_tool_prefix}cc", so it can be a program name with args. set dummy ${ac_tool_prefix}cc; ac_word=$2 -{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 -$as_echo_n "checking for $ac_word... " >&6; } -if ${ac_cv_prog_CC+:} false; then : - $as_echo_n "(cached) " >&6 -else +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +printf %s "checking for $ac_word... " >&6; } +if test ${ac_cv_prog_CC+y} +then : + printf %s "(cached) " >&6 +else $as_nop if test -n "$CC"; then ac_cv_prog_CC="$CC" # Let the user override the test. else @@ -4404,11 +4855,15 @@ for as_dir in $PATH do IFS=$as_save_IFS - test -z "$as_dir" && as_dir=. + case $as_dir in #((( + '') as_dir=./ ;; + */) ;; + *) as_dir=$as_dir/ ;; + esac for ac_exec_ext in '' $ac_executable_extensions; do - if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then + if as_fn_executable_p "$as_dir$ac_word$ac_exec_ext"; then ac_cv_prog_CC="${ac_tool_prefix}cc" - $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + printf "%s\n" "$as_me:${as_lineno-$LINENO}: found $as_dir$ac_word$ac_exec_ext" >&5 break 2 fi done @@ -4419,11 +4874,11 @@ fi CC=$ac_cv_prog_CC if test -n "$CC"; then - { $as_echo "$as_me:${as_lineno-$LINENO}: result: $CC" >&5 -$as_echo "$CC" >&6; } + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: $CC" >&5 +printf "%s\n" "$CC" >&6; } else - { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 -$as_echo "no" >&6; } + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: no" >&5 +printf "%s\n" "no" >&6; } fi @@ -4432,11 +4887,12 @@ if test -z "$CC"; then # Extract the first word of "cc", so it can be a program name with args. set dummy cc; ac_word=$2 -{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 -$as_echo_n "checking for $ac_word... " >&6; } -if ${ac_cv_prog_CC+:} false; then : - $as_echo_n "(cached) " >&6 -else +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +printf %s "checking for $ac_word... " >&6; } +if test ${ac_cv_prog_CC+y} +then : + printf %s "(cached) " >&6 +else $as_nop if test -n "$CC"; then ac_cv_prog_CC="$CC" # Let the user override the test. else @@ -4445,15 +4901,19 @@ for as_dir in $PATH do IFS=$as_save_IFS - test -z "$as_dir" && as_dir=. + case $as_dir in #((( + '') as_dir=./ ;; + */) ;; + *) as_dir=$as_dir/ ;; + esac for ac_exec_ext in '' $ac_executable_extensions; do - if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then - if test "$as_dir/$ac_word$ac_exec_ext" = "/usr/ucb/cc"; then + if as_fn_executable_p "$as_dir$ac_word$ac_exec_ext"; then + if test "$as_dir$ac_word$ac_exec_ext" = "/usr/ucb/cc"; then ac_prog_rejected=yes continue fi ac_cv_prog_CC="cc" - $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + printf "%s\n" "$as_me:${as_lineno-$LINENO}: found $as_dir$ac_word$ac_exec_ext" >&5 break 2 fi done @@ -4469,18 +4929,18 @@ # However, it has the same basename, so the bogon will be chosen # first if we set CC to just the basename; use the full file name. shift - ac_cv_prog_CC="$as_dir/$ac_word${1+' '}$@" + ac_cv_prog_CC="$as_dir$ac_word${1+' '}$@" fi fi fi fi CC=$ac_cv_prog_CC if test -n "$CC"; then - { $as_echo "$as_me:${as_lineno-$LINENO}: result: $CC" >&5 -$as_echo "$CC" >&6; } + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: $CC" >&5 +printf "%s\n" "$CC" >&6; } else - { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 -$as_echo "no" >&6; } + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: no" >&5 +printf "%s\n" "no" >&6; } fi @@ -4491,11 +4951,12 @@ do # Extract the first word of "$ac_tool_prefix$ac_prog", so it can be a program name with args. set dummy $ac_tool_prefix$ac_prog; ac_word=$2 -{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 -$as_echo_n "checking for $ac_word... " >&6; } -if ${ac_cv_prog_CC+:} false; then : - $as_echo_n "(cached) " >&6 -else +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +printf %s "checking for $ac_word... " >&6; } +if test ${ac_cv_prog_CC+y} +then : + printf %s "(cached) " >&6 +else $as_nop if test -n "$CC"; then ac_cv_prog_CC="$CC" # Let the user override the test. else @@ -4503,11 +4964,15 @@ for as_dir in $PATH do IFS=$as_save_IFS - test -z "$as_dir" && as_dir=. + case $as_dir in #((( + '') as_dir=./ ;; + */) ;; + *) as_dir=$as_dir/ ;; + esac for ac_exec_ext in '' $ac_executable_extensions; do - if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then + if as_fn_executable_p "$as_dir$ac_word$ac_exec_ext"; then ac_cv_prog_CC="$ac_tool_prefix$ac_prog" - $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + printf "%s\n" "$as_me:${as_lineno-$LINENO}: found $as_dir$ac_word$ac_exec_ext" >&5 break 2 fi done @@ -4518,11 +4983,11 @@ fi CC=$ac_cv_prog_CC if test -n "$CC"; then - { $as_echo "$as_me:${as_lineno-$LINENO}: result: $CC" >&5 -$as_echo "$CC" >&6; } + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: $CC" >&5 +printf "%s\n" "$CC" >&6; } else - { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 -$as_echo "no" >&6; } + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: no" >&5 +printf "%s\n" "no" >&6; } fi @@ -4535,11 +5000,12 @@ do # Extract the first word of "$ac_prog", so it can be a program name with args. set dummy $ac_prog; ac_word=$2 -{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 -$as_echo_n "checking for $ac_word... " >&6; } -if ${ac_cv_prog_ac_ct_CC+:} false; then : - $as_echo_n "(cached) " >&6 -else +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +printf %s "checking for $ac_word... " >&6; } +if test ${ac_cv_prog_ac_ct_CC+y} +then : + printf %s "(cached) " >&6 +else $as_nop if test -n "$ac_ct_CC"; then ac_cv_prog_ac_ct_CC="$ac_ct_CC" # Let the user override the test. else @@ -4547,11 +5013,15 @@ for as_dir in $PATH do IFS=$as_save_IFS - test -z "$as_dir" && as_dir=. + case $as_dir in #((( + '') as_dir=./ ;; + */) ;; + *) as_dir=$as_dir/ ;; + esac for ac_exec_ext in '' $ac_executable_extensions; do - if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then + if as_fn_executable_p "$as_dir$ac_word$ac_exec_ext"; then ac_cv_prog_ac_ct_CC="$ac_prog" - $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + printf "%s\n" "$as_me:${as_lineno-$LINENO}: found $as_dir$ac_word$ac_exec_ext" >&5 break 2 fi done @@ -4562,11 +5032,11 @@ fi ac_ct_CC=$ac_cv_prog_ac_ct_CC if test -n "$ac_ct_CC"; then - { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_CC" >&5 -$as_echo "$ac_ct_CC" >&6; } + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: $ac_ct_CC" >&5 +printf "%s\n" "$ac_ct_CC" >&6; } else - { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 -$as_echo "no" >&6; } + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: no" >&5 +printf "%s\n" "no" >&6; } fi @@ -4578,8 +5048,8 @@ else case $cross_compiling:$ac_tool_warned in yes:) -{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 -$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 +printf "%s\n" "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} ac_tool_warned=yes ;; esac CC=$ac_ct_CC @@ -4587,25 +5057,129 @@ fi fi +if test -z "$CC"; then + if test -n "$ac_tool_prefix"; then + # Extract the first word of "${ac_tool_prefix}clang", so it can be a program name with args. +set dummy ${ac_tool_prefix}clang; ac_word=$2 +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +printf %s "checking for $ac_word... " >&6; } +if test ${ac_cv_prog_CC+y} +then : + printf %s "(cached) " >&6 +else $as_nop + if test -n "$CC"; then + ac_cv_prog_CC="$CC" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + case $as_dir in #((( + '') as_dir=./ ;; + */) ;; + *) as_dir=$as_dir/ ;; + esac + for ac_exec_ext in '' $ac_executable_extensions; do + if as_fn_executable_p "$as_dir$ac_word$ac_exec_ext"; then + ac_cv_prog_CC="${ac_tool_prefix}clang" + printf "%s\n" "$as_me:${as_lineno-$LINENO}: found $as_dir$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS - -test -z "$CC" && { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 -$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} -as_fn_error $? "no acceptable C compiler found in \$PATH +fi +fi +CC=$ac_cv_prog_CC +if test -n "$CC"; then + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: $CC" >&5 +printf "%s\n" "$CC" >&6; } +else + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: no" >&5 +printf "%s\n" "no" >&6; } +fi + + +fi +if test -z "$ac_cv_prog_CC"; then + ac_ct_CC=$CC + # Extract the first word of "clang", so it can be a program name with args. +set dummy clang; ac_word=$2 +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +printf %s "checking for $ac_word... " >&6; } +if test ${ac_cv_prog_ac_ct_CC+y} +then : + printf %s "(cached) " >&6 +else $as_nop + if test -n "$ac_ct_CC"; then + ac_cv_prog_ac_ct_CC="$ac_ct_CC" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + case $as_dir in #((( + '') as_dir=./ ;; + */) ;; + *) as_dir=$as_dir/ ;; + esac + for ac_exec_ext in '' $ac_executable_extensions; do + if as_fn_executable_p "$as_dir$ac_word$ac_exec_ext"; then + ac_cv_prog_ac_ct_CC="clang" + printf "%s\n" "$as_me:${as_lineno-$LINENO}: found $as_dir$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +ac_ct_CC=$ac_cv_prog_ac_ct_CC +if test -n "$ac_ct_CC"; then + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: $ac_ct_CC" >&5 +printf "%s\n" "$ac_ct_CC" >&6; } +else + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: no" >&5 +printf "%s\n" "no" >&6; } +fi + + if test "x$ac_ct_CC" = x; then + CC="" + else + case $cross_compiling:$ac_tool_warned in +yes:) +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 +printf "%s\n" "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} +ac_tool_warned=yes ;; +esac + CC=$ac_ct_CC + fi +else + CC="$ac_cv_prog_CC" +fi + +fi + + +test -z "$CC" && { { printf "%s\n" "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 +printf "%s\n" "$as_me: error: in \`$ac_pwd':" >&2;} +as_fn_error $? "no acceptable C compiler found in \$PATH See \`config.log' for more details" "$LINENO" 5; } # Provide some information about the compiler. -$as_echo "$as_me:${as_lineno-$LINENO}: checking for C compiler version" >&5 +printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking for C compiler version" >&5 set X $ac_compile ac_compiler=$2 -for ac_option in --version -v -V -qversion; do +for ac_option in --version -v -V -qversion -version; do { { ac_try="$ac_compiler $ac_option >&5" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" -$as_echo "$ac_try_echo"; } >&5 +printf "%s\n" "$ac_try_echo"; } >&5 (eval "$ac_compiler $ac_option >&5") 2>conftest.err ac_status=$? if test -s conftest.err; then @@ -4615,20 +5189,21 @@ cat conftest.er1 >&5 fi rm -f conftest.er1 conftest.err - $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + printf "%s\n" "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 test $ac_status = 0; } done -{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether we are using the GNU C compiler" >&5 -$as_echo_n "checking whether we are using the GNU C compiler... " >&6; } -if ${ac_cv_c_compiler_gnu+:} false; then : - $as_echo_n "(cached) " >&6 -else +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking whether the compiler supports GNU C" >&5 +printf %s "checking whether the compiler supports GNU C... " >&6; } +if test ${ac_cv_c_compiler_gnu+y} +then : + printf %s "(cached) " >&6 +else $as_nop cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ int -main () +main (void) { #ifndef __GNUC__ choke me @@ -4638,29 +5213,33 @@ return 0; } _ACEOF -if ac_fn_c_try_compile "$LINENO"; then : +if ac_fn_c_try_compile "$LINENO" +then : ac_compiler_gnu=yes -else +else $as_nop ac_compiler_gnu=no fi -rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +rm -f core conftest.err conftest.$ac_objext conftest.beam conftest.$ac_ext ac_cv_c_compiler_gnu=$ac_compiler_gnu fi -{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_c_compiler_gnu" >&5 -$as_echo "$ac_cv_c_compiler_gnu" >&6; } +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: $ac_cv_c_compiler_gnu" >&5 +printf "%s\n" "$ac_cv_c_compiler_gnu" >&6; } +ac_compiler_gnu=$ac_cv_c_compiler_gnu + if test $ac_compiler_gnu = yes; then GCC=yes else GCC= fi -ac_test_CFLAGS=${CFLAGS+set} +ac_test_CFLAGS=${CFLAGS+y} ac_save_CFLAGS=$CFLAGS -{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether $CC accepts -g" >&5 -$as_echo_n "checking whether $CC accepts -g... " >&6; } -if ${ac_cv_prog_cc_g+:} false; then : - $as_echo_n "(cached) " >&6 -else +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking whether $CC accepts -g" >&5 +printf %s "checking whether $CC accepts -g... " >&6; } +if test ${ac_cv_prog_cc_g+y} +then : + printf %s "(cached) " >&6 +else $as_nop ac_save_c_werror_flag=$ac_c_werror_flag ac_c_werror_flag=yes ac_cv_prog_cc_g=no @@ -4669,11379 +5248,213 @@ /* end confdefs.h. */ int -main () +main (void) { ; return 0; } _ACEOF -if ac_fn_c_try_compile "$LINENO"; then : +if ac_fn_c_try_compile "$LINENO" +then : ac_cv_prog_cc_g=yes -else +else $as_nop CFLAGS="" cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ - -int -main () -{ - - ; - return 0; -} -_ACEOF -if ac_fn_c_try_compile "$LINENO"; then : - -else - ac_c_werror_flag=$ac_save_c_werror_flag - CFLAGS="-g" - cat confdefs.h - <<_ACEOF >conftest.$ac_ext -/* end confdefs.h. */ - -int -main () -{ - - ; - return 0; -} -_ACEOF -if ac_fn_c_try_compile "$LINENO"; then : - ac_cv_prog_cc_g=yes -fi -rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext -fi -rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext -fi -rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext - ac_c_werror_flag=$ac_save_c_werror_flag -fi -{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_prog_cc_g" >&5 -$as_echo "$ac_cv_prog_cc_g" >&6; } -if test "$ac_test_CFLAGS" = set; then - CFLAGS=$ac_save_CFLAGS -elif test $ac_cv_prog_cc_g = yes; then - if test "$GCC" = yes; then - CFLAGS="-g -O2" - else - CFLAGS="-g" - fi -else - if test "$GCC" = yes; then - CFLAGS="-O2" - else - CFLAGS= - fi -fi -{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $CC option to accept ISO C89" >&5 -$as_echo_n "checking for $CC option to accept ISO C89... " >&6; } -if ${ac_cv_prog_cc_c89+:} false; then : - $as_echo_n "(cached) " >&6 -else - ac_cv_prog_cc_c89=no -ac_save_CC=$CC -cat confdefs.h - <<_ACEOF >conftest.$ac_ext -/* end confdefs.h. */ -#include -#include -struct stat; -/* Most of the following tests are stolen from RCS 5.7's src/conf.sh. */ -struct buf { int x; }; -FILE * (*rcsopen) (struct buf *, struct stat *, int); -static char *e (p, i) - char **p; - int i; -{ - return p[i]; -} -static char *f (char * (*g) (char **, int), char **p, ...) -{ - char *s; - va_list v; - va_start (v,p); - s = g (p, va_arg (v,int)); - va_end (v); - return s; -} - -/* OSF 4.0 Compaq cc is some sort of almost-ANSI by default. It has - function prototypes and stuff, but not '\xHH' hex character constants. - These don't provoke an error unfortunately, instead are silently treated - as 'x'. The following induces an error, until -std is added to get - proper ANSI mode. Curiously '\x00'!='x' always comes out true, for an - array size at least. It's necessary to write '\x00'==0 to get something - that's true only with -std. */ -int osf4_cc_array ['\x00' == 0 ? 1 : -1]; - -/* IBM C 6 for AIX is almost-ANSI by default, but it replaces macro parameters - inside strings and character constants. */ -#define FOO(x) 'x' -int xlc6_cc_array[FOO(a) == 'x' ? 1 : -1]; - -int test (int i, double x); -struct s1 {int (*f) (int a);}; -struct s2 {int (*f) (double a);}; -int pairnames (int, char **, FILE *(*)(struct buf *, struct stat *, int), int, int); -int argc; -char **argv; -int -main () -{ -return f (e, argv, 0) != argv[0] || f (e, argv, 1) != argv[1]; - ; - return 0; -} -_ACEOF -for ac_arg in '' -qlanglvl=extc89 -qlanglvl=ansi -std \ - -Ae "-Aa -D_HPUX_SOURCE" "-Xc -D__EXTENSIONS__" -do - CC="$ac_save_CC $ac_arg" - if ac_fn_c_try_compile "$LINENO"; then : - ac_cv_prog_cc_c89=$ac_arg -fi -rm -f core conftest.err conftest.$ac_objext - test "x$ac_cv_prog_cc_c89" != "xno" && break -done -rm -f conftest.$ac_ext -CC=$ac_save_CC - -fi -# AC_CACHE_VAL -case "x$ac_cv_prog_cc_c89" in - x) - { $as_echo "$as_me:${as_lineno-$LINENO}: result: none needed" >&5 -$as_echo "none needed" >&6; } ;; - xno) - { $as_echo "$as_me:${as_lineno-$LINENO}: result: unsupported" >&5 -$as_echo "unsupported" >&6; } ;; - *) - CC="$CC $ac_cv_prog_cc_c89" - { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_prog_cc_c89" >&5 -$as_echo "$ac_cv_prog_cc_c89" >&6; } ;; -esac -if test "x$ac_cv_prog_cc_c89" != xno; then : - -fi - -ac_ext=c -ac_cpp='$CPP $CPPFLAGS' -ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' -ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' -ac_compiler_gnu=$ac_cv_c_compiler_gnu - -{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for a sed that does not truncate output" >&5 -$as_echo_n "checking for a sed that does not truncate output... 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- -sysv5* | sco3.2v5* | sco5v6* | unixware* | OpenUNIX* | sysv4*uw2*) - version_type=sco - need_lib_prefix=no - need_version=no - library_names_spec='$libname$release$shared_ext$versuffix $libname$release$shared_ext $libname$shared_ext' - soname_spec='$libname$release$shared_ext$major' - shlibpath_var=LD_LIBRARY_PATH - shlibpath_overrides_runpath=yes - hardcode_into_libs=yes - if test yes = "$with_gnu_ld"; then - sys_lib_search_path_spec='/usr/local/lib /usr/gnu/lib /usr/ccs/lib /usr/lib /lib' +else + if test "$GCC" = yes; then + CFLAGS="-O2" else - sys_lib_search_path_spec='/usr/ccs/lib /usr/lib' - case $host_os in - sco3.2v5*) - sys_lib_search_path_spec="$sys_lib_search_path_spec /lib" - ;; - esac + CFLAGS= fi - sys_lib_dlsearch_path_spec='/usr/lib' - ;; - -tpf*) - # TPF is a cross-target only. Preferred cross-host = GNU/Linux. - version_type=linux # correct to gnu/linux during the next big refactor - need_lib_prefix=no - need_version=no - library_names_spec='$libname$release$shared_ext$versuffix $libname$release$shared_ext$major $libname$shared_ext' - shlibpath_var=LD_LIBRARY_PATH - shlibpath_overrides_runpath=no - hardcode_into_libs=yes - ;; - -uts4*) - version_type=linux # correct to gnu/linux during the next big refactor - library_names_spec='$libname$release$shared_ext$versuffix $libname$release$shared_ext$major $libname$shared_ext' - soname_spec='$libname$release$shared_ext$major' - shlibpath_var=LD_LIBRARY_PATH - ;; - -*) - dynamic_linker=no - ;; -esac -{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $dynamic_linker" >&5 -$as_echo "$dynamic_linker" >&6; } -test no = "$dynamic_linker" && can_build_shared=no - -variables_saved_for_relink="PATH $shlibpath_var $runpath_var" -if test yes = "$GCC"; then - variables_saved_for_relink="$variables_saved_for_relink GCC_EXEC_PREFIX COMPILER_PATH LIBRARY_PATH" fi - -if test set = "${lt_cv_sys_lib_search_path_spec+set}"; then - sys_lib_search_path_spec=$lt_cv_sys_lib_search_path_spec +ac_prog_cc_stdc=no +if test x$ac_prog_cc_stdc = xno +then : + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking for $CC option to enable C11 features" >&5 +printf %s "checking for $CC option to enable C11 features... " >&6; } +if test ${ac_cv_prog_cc_c11+y} +then : + printf %s "(cached) " >&6 +else $as_nop + ac_cv_prog_cc_c11=no +ac_save_CC=$CC +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +$ac_c_conftest_c11_program +_ACEOF +for ac_arg in '' -std=gnu11 +do + CC="$ac_save_CC $ac_arg" + if ac_fn_c_try_compile "$LINENO" +then : + ac_cv_prog_cc_c11=$ac_arg fi - -if test set = "${lt_cv_sys_lib_dlsearch_path_spec+set}"; then - sys_lib_dlsearch_path_spec=$lt_cv_sys_lib_dlsearch_path_spec +rm -f core conftest.err conftest.$ac_objext conftest.beam + test "x$ac_cv_prog_cc_c11" != "xno" && break +done +rm -f conftest.$ac_ext +CC=$ac_save_CC fi -# remember unaugmented sys_lib_dlsearch_path content for libtool script decls... -configure_time_dlsearch_path=$sys_lib_dlsearch_path_spec - -# ... but it needs LT_SYS_LIBRARY_PATH munging for other configure-time code -func_munge_path_list sys_lib_dlsearch_path_spec "$LT_SYS_LIBRARY_PATH" - -# to be used as default LT_SYS_LIBRARY_PATH value in generated libtool -configure_time_lt_sys_library_path=$LT_SYS_LIBRARY_PATH - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - { $as_echo "$as_me:${as_lineno-$LINENO}: checking how to hardcode library paths into programs" >&5 -$as_echo_n "checking how to hardcode library paths into programs... " >&6; } -hardcode_action_CXX= -if test -n "$hardcode_libdir_flag_spec_CXX" || - test -n "$runpath_var_CXX" || - test yes = "$hardcode_automatic_CXX"; then - - # We can hardcode non-existent directories. - if test no != "$hardcode_direct_CXX" && - # If the only mechanism to avoid hardcoding is shlibpath_var, we - # have to relink, otherwise we might link with an installed library - # when we should be linking with a yet-to-be-installed one - ## test no != "$_LT_TAGVAR(hardcode_shlibpath_var, CXX)" && - test no != "$hardcode_minus_L_CXX"; then - # Linking always hardcodes the temporary library directory. - hardcode_action_CXX=relink - else - # We can link without hardcoding, and we can hardcode nonexisting dirs. - hardcode_action_CXX=immediate - fi -else - # We cannot hardcode anything, or else we can only hardcode existing - # directories. - hardcode_action_CXX=unsupported +if test "x$ac_cv_prog_cc_c11" = xno +then : + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: unsupported" >&5 +printf "%s\n" "unsupported" >&6; } +else $as_nop + if test "x$ac_cv_prog_cc_c11" = x +then : + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: none needed" >&5 +printf "%s\n" "none needed" >&6; } +else $as_nop + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: $ac_cv_prog_cc_c11" >&5 +printf "%s\n" "$ac_cv_prog_cc_c11" >&6; } + CC="$CC $ac_cv_prog_cc_c11" +fi + ac_cv_prog_cc_stdc=$ac_cv_prog_cc_c11 + ac_prog_cc_stdc=c11 +fi +fi +if test x$ac_prog_cc_stdc = xno +then : + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking for $CC option to enable C99 features" >&5 +printf %s "checking for $CC option to enable C99 features... " >&6; } +if test ${ac_cv_prog_cc_c99+y} +then : + printf %s "(cached) " >&6 +else $as_nop + ac_cv_prog_cc_c99=no +ac_save_CC=$CC +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +$ac_c_conftest_c99_program +_ACEOF +for ac_arg in '' -std=gnu99 -std=c99 -c99 -qlanglvl=extc1x -qlanglvl=extc99 -AC99 -D_STDC_C99= +do + CC="$ac_save_CC $ac_arg" + if ac_fn_c_try_compile "$LINENO" +then : + ac_cv_prog_cc_c99=$ac_arg fi -{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $hardcode_action_CXX" >&5 -$as_echo "$hardcode_action_CXX" >&6; } - -if test relink = "$hardcode_action_CXX" || - test yes = "$inherit_rpath_CXX"; then - # Fast installation is not supported - enable_fast_install=no -elif test yes = "$shlibpath_overrides_runpath" || - test no = "$enable_shared"; then - # Fast installation is not necessary - enable_fast_install=needless +rm -f core conftest.err conftest.$ac_objext conftest.beam + test "x$ac_cv_prog_cc_c99" != "xno" && break +done +rm -f conftest.$ac_ext +CC=$ac_save_CC fi +if test "x$ac_cv_prog_cc_c99" = xno +then : + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: unsupported" >&5 +printf "%s\n" "unsupported" >&6; } +else $as_nop + if test "x$ac_cv_prog_cc_c99" = x +then : + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: none needed" >&5 +printf "%s\n" "none needed" >&6; } +else $as_nop + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: $ac_cv_prog_cc_c99" >&5 +printf "%s\n" "$ac_cv_prog_cc_c99" >&6; } + CC="$CC $ac_cv_prog_cc_c99" +fi + ac_cv_prog_cc_stdc=$ac_cv_prog_cc_c99 + ac_prog_cc_stdc=c99 +fi +fi +if test x$ac_prog_cc_stdc = xno +then : + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking for $CC option to enable C89 features" >&5 +printf %s "checking for $CC option to enable C89 features... " >&6; } +if test ${ac_cv_prog_cc_c89+y} +then : + printf %s "(cached) " >&6 +else $as_nop + ac_cv_prog_cc_c89=no +ac_save_CC=$CC +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +$ac_c_conftest_c89_program +_ACEOF +for ac_arg in '' -qlanglvl=extc89 -qlanglvl=ansi -std -Ae "-Aa -D_HPUX_SOURCE" "-Xc -D__EXTENSIONS__" +do + CC="$ac_save_CC $ac_arg" + if ac_fn_c_try_compile "$LINENO" +then : + ac_cv_prog_cc_c89=$ac_arg +fi +rm -f core conftest.err conftest.$ac_objext conftest.beam + test "x$ac_cv_prog_cc_c89" != "xno" && break +done +rm -f conftest.$ac_ext +CC=$ac_save_CC +fi - - - - - - fi # test -n "$compiler" - - CC=$lt_save_CC - CFLAGS=$lt_save_CFLAGS - LDCXX=$LD - LD=$lt_save_LD - GCC=$lt_save_GCC - with_gnu_ld=$lt_save_with_gnu_ld - lt_cv_path_LDCXX=$lt_cv_path_LD - lt_cv_path_LD=$lt_save_path_LD - lt_cv_prog_gnu_ldcxx=$lt_cv_prog_gnu_ld - lt_cv_prog_gnu_ld=$lt_save_with_gnu_ld -fi # test yes != "$_lt_caught_CXX_error" +if test "x$ac_cv_prog_cc_c89" = xno +then : + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: unsupported" >&5 +printf "%s\n" "unsupported" >&6; } +else $as_nop + if test "x$ac_cv_prog_cc_c89" = x +then : + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: none needed" >&5 +printf "%s\n" "none needed" >&6; } +else $as_nop + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: $ac_cv_prog_cc_c89" >&5 +printf "%s\n" "$ac_cv_prog_cc_c89" >&6; } + CC="$CC $ac_cv_prog_cc_c89" +fi + ac_cv_prog_cc_stdc=$ac_cv_prog_cc_c89 + ac_prog_cc_stdc=c89 +fi +fi ac_ext=c ac_cpp='$CPP $CPPFLAGS' @@ -16050,38 +5463,16 @@ ac_compiler_gnu=$ac_cv_c_compiler_gnu - - - - - - - - - - - - - - ac_config_commands="$ac_config_commands libtool" - - - - -# Only expand once: - - - - for ac_prog in flex lex do # Extract the first word of "$ac_prog", so it can be a program name with args. set dummy $ac_prog; ac_word=$2 -{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 -$as_echo_n "checking for $ac_word... " >&6; } -if ${ac_cv_prog_LEX+:} false; then : - $as_echo_n "(cached) " >&6 -else +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +printf %s "checking for $ac_word... " >&6; } +if test ${ac_cv_prog_LEX+y} +then : + printf %s "(cached) " >&6 +else $as_nop if test -n "$LEX"; then ac_cv_prog_LEX="$LEX" # Let the user override the test. else @@ -16089,11 +5480,15 @@ for as_dir in $PATH do IFS=$as_save_IFS - test -z "$as_dir" && as_dir=. + case $as_dir in #((( + '') as_dir=./ ;; + */) ;; + *) as_dir=$as_dir/ ;; + esac for ac_exec_ext in '' $ac_executable_extensions; do - if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then + if as_fn_executable_p "$as_dir$ac_word$ac_exec_ext"; then ac_cv_prog_LEX="$ac_prog" - $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + printf "%s\n" "$as_me:${as_lineno-$LINENO}: found $as_dir$ac_word$ac_exec_ext" >&5 break 2 fi done @@ -16104,11 +5499,11 @@ fi LEX=$ac_cv_prog_LEX if test -n "$LEX"; then - { $as_echo "$as_me:${as_lineno-$LINENO}: result: $LEX" >&5 -$as_echo "$LEX" >&6; } + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: $LEX" >&5 +printf "%s\n" "$LEX" >&6; } else - { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 -$as_echo "no" >&6; } + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: no" >&5 +printf "%s\n" "no" >&6; } fi @@ -16116,15 +5511,26 @@ done test -n "$LEX" || LEX=":" -if test "x$LEX" != "x:"; then - cat >conftest.l <<_ACEOF + if test "x$LEX" != "x:"; then + cat >conftest.l <<_ACEOF +%{ +#ifdef __cplusplus +extern "C" +#endif +int yywrap(void); +%} %% a { ECHO; } b { REJECT; } c { yymore (); } d { yyless (1); } e { /* IRIX 6.5 flex 2.5.4 underquotes its yyless argument. */ - yyless ((input () != 0)); } +#ifdef __cplusplus + yyless ((yyinput () != 0)); +#else + yyless ((input () != 0)); +#endif + } f { unput (yytext[0]); } . { BEGIN INITIAL; } %% @@ -16132,101 +5538,144 @@ extern char *yytext; #endif int +yywrap (void) +{ + return 1; +} +int main (void) { - return ! yylex () + ! yywrap (); + return ! yylex (); } _ACEOF +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking for lex output file root" >&5 +printf %s "checking for lex output file root... " >&6; } +if test ${ac_cv_prog_lex_root+y} +then : + printf %s "(cached) " >&6 +else $as_nop + +ac_cv_prog_lex_root=unknown { { ac_try="$LEX conftest.l" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" -$as_echo "$ac_try_echo"; } >&5 +printf "%s\n" "$ac_try_echo"; } >&5 (eval "$LEX conftest.l") 2>&5 ac_status=$? - $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 - test $ac_status = 0; } -{ $as_echo "$as_me:${as_lineno-$LINENO}: checking lex output file root" >&5 -$as_echo_n "checking lex output file root... " >&6; } -if ${ac_cv_prog_lex_root+:} false; then : - $as_echo_n "(cached) " >&6 -else - + printf "%s\n" "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } && if test -f lex.yy.c; then ac_cv_prog_lex_root=lex.yy elif test -f lexyy.c; then ac_cv_prog_lex_root=lexyy -else - as_fn_error $? "cannot find output from $LEX; giving up" "$LINENO" 5 fi fi -{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_prog_lex_root" >&5 -$as_echo "$ac_cv_prog_lex_root" >&6; } +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: $ac_cv_prog_lex_root" >&5 +printf "%s\n" "$ac_cv_prog_lex_root" >&6; } +if test "$ac_cv_prog_lex_root" = unknown +then : + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: WARNING: cannot find output from $LEX; giving up on $LEX" >&5 +printf "%s\n" "$as_me: WARNING: cannot find output from $LEX; giving up on $LEX" >&2;} + LEX=: LEXLIB= +fi LEX_OUTPUT_ROOT=$ac_cv_prog_lex_root -if test -z "${LEXLIB+set}"; then - { $as_echo "$as_me:${as_lineno-$LINENO}: checking lex library" >&5 -$as_echo_n "checking lex library... " >&6; } -if ${ac_cv_lib_lex+:} false; then : - $as_echo_n "(cached) " >&6 -else +if test ${LEXLIB+y} +then : + +else $as_nop + + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking for lex library" >&5 +printf %s "checking for lex library... " >&6; } +if test ${ac_cv_lib_lex+y} +then : + printf %s "(cached) " >&6 +else $as_nop + + ac_save_LIBS="$LIBS" + ac_found=false + for ac_cv_lib_lex in 'none needed' -lfl -ll 'not found'; do + case $ac_cv_lib_lex in #( + 'none needed') : + ;; #( + 'not found') : + break ;; #( + *) : + LIBS="$ac_cv_lib_lex $ac_save_LIBS" ;; #( + *) : + ;; +esac - ac_save_LIBS=$LIBS - ac_cv_lib_lex='none needed' - for ac_lib in '' -lfl -ll; do - LIBS="$ac_lib $ac_save_LIBS" cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ `cat $LEX_OUTPUT_ROOT.c` _ACEOF -if ac_fn_c_try_link "$LINENO"; then : - ac_cv_lib_lex=$ac_lib +if ac_fn_c_try_link "$LINENO" +then : + ac_found=: fi -rm -f core conftest.err conftest.$ac_objext \ +rm -f core conftest.err conftest.$ac_objext conftest.beam \ conftest$ac_exeext conftest.$ac_ext - test "$ac_cv_lib_lex" != 'none needed' && break + if $ac_found; then + break + fi done - LIBS=$ac_save_LIBS + LIBS="$ac_save_LIBS" fi -{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_lex" >&5 -$as_echo "$ac_cv_lib_lex" >&6; } - test "$ac_cv_lib_lex" != 'none needed' && LEXLIB=$ac_cv_lib_lex +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_lex" >&5 +printf "%s\n" "$ac_cv_lib_lex" >&6; } + if test "$ac_cv_lib_lex" = 'not found' +then : + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: WARNING: required lex library not found; giving up on $LEX" >&5 +printf "%s\n" "$as_me: WARNING: required lex library not found; giving up on $LEX" >&2;} + LEX=: LEXLIB= +elif test "$ac_cv_lib_lex" = 'none needed' +then : + LEXLIB='' +else $as_nop + LEXLIB=$ac_cv_lib_lex fi +fi -{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether yytext is a pointer" >&5 -$as_echo_n "checking whether yytext is a pointer... " >&6; } -if ${ac_cv_prog_lex_yytext_pointer+:} false; then : - $as_echo_n "(cached) " >&6 -else + +if test "$LEX" != : +then : + +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking whether yytext is a pointer" >&5 +printf %s "checking whether yytext is a pointer... " >&6; } +if test ${ac_cv_prog_lex_yytext_pointer+y} +then : + printf %s "(cached) " >&6 +else $as_nop # POSIX says lex can declare yytext either as a pointer or an array; the # default is implementation-dependent. Figure out which it is, since # not all implementations provide the %pointer and %array declarations. ac_cv_prog_lex_yytext_pointer=no -ac_save_LIBS=$LIBS -LIBS="$LEXLIB $ac_save_LIBS" cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ #define YYTEXT_POINTER 1 `cat $LEX_OUTPUT_ROOT.c` _ACEOF -if ac_fn_c_try_link "$LINENO"; then : +if ac_fn_c_try_compile "$LINENO" +then : ac_cv_prog_lex_yytext_pointer=yes fi -rm -f core conftest.err conftest.$ac_objext \ - conftest$ac_exeext conftest.$ac_ext -LIBS=$ac_save_LIBS +rm -f core conftest.err conftest.$ac_objext conftest.beam conftest.$ac_ext fi -{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_prog_lex_yytext_pointer" >&5 -$as_echo "$ac_cv_prog_lex_yytext_pointer" >&6; } +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: $ac_cv_prog_lex_yytext_pointer" >&5 +printf "%s\n" "$ac_cv_prog_lex_yytext_pointer" >&6; } if test $ac_cv_prog_lex_yytext_pointer = yes; then -$as_echo "#define YYTEXT_POINTER 1" >>confdefs.h +printf "%s\n" "#define YYTEXT_POINTER 1" >>confdefs.h + +fi fi rm -f conftest.l $LEX_OUTPUT_ROOT.c @@ -16234,18 +5683,19 @@ fi if test ${LEX} = "flex"; then -$as_echo "#define HAVE_FLEX 1" >>confdefs.h +printf "%s\n" "#define HAVE_FLEX 1" >>confdefs.h fi for ac_prog in 'bison -y' byacc do # Extract the first word of "$ac_prog", so it can be a program name with args. set dummy $ac_prog; ac_word=$2 -{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 -$as_echo_n "checking for $ac_word... " >&6; } -if ${ac_cv_prog_YACC+:} false; then : - $as_echo_n "(cached) " >&6 -else +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +printf %s "checking for $ac_word... " >&6; } +if test ${ac_cv_prog_YACC+y} +then : + printf %s "(cached) " >&6 +else $as_nop if test -n "$YACC"; then ac_cv_prog_YACC="$YACC" # Let the user override the test. else @@ -16253,11 +5703,15 @@ for as_dir in $PATH do IFS=$as_save_IFS - test -z "$as_dir" && as_dir=. + case $as_dir in #((( + '') as_dir=./ ;; + */) ;; + *) as_dir=$as_dir/ ;; + esac for ac_exec_ext in '' $ac_executable_extensions; do - if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then + if as_fn_executable_p "$as_dir$ac_word$ac_exec_ext"; then ac_cv_prog_YACC="$ac_prog" - $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + printf "%s\n" "$as_me:${as_lineno-$LINENO}: found $as_dir$ac_word$ac_exec_ext" >&5 break 2 fi done @@ -16268,11 +5722,11 @@ fi YACC=$ac_cv_prog_YACC if test -n "$YACC"; then - { $as_echo "$as_me:${as_lineno-$LINENO}: result: $YACC" >&5 -$as_echo "$YACC" >&6; } + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: $YACC" >&5 +printf "%s\n" "$YACC" >&6; } else - { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 -$as_echo "no" >&6; } + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: no" >&5 +printf "%s\n" "no" >&6; } fi @@ -16292,280 +5746,357 @@ # Checking for header files. # =========================================================================== -if test -d /stuff/include; then - CPPFLAGS="$CPPFLAGS -I/stuff/include" -fi +#if test -d /stuff/include; then +# CPPFLAGS="$CPPFLAGS -I/stuff/include" +#fi -{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for ANSI C header files" >&5 -$as_echo_n "checking for ANSI C header files... " >&6; } -if ${ac_cv_header_stdc+:} false; then : - $as_echo_n "(cached) " >&6 -else - cat confdefs.h - <<_ACEOF >conftest.$ac_ext -/* end confdefs.h. */ -#include -#include -#include -#include +ac_header= ac_cache= +for ac_item in $ac_header_cxx_list +do + if test $ac_cache; then + ac_fn_cxx_check_header_compile "$LINENO" $ac_header ac_cv_header_$ac_cache "$ac_includes_default" + if eval test \"x\$ac_cv_header_$ac_cache\" = xyes; then + printf "%s\n" "#define $ac_item 1" >> confdefs.h + fi + ac_header= ac_cache= + elif test $ac_header; then + ac_cache=$ac_item + else + ac_header=$ac_item + fi +done -int -main () -{ - ; - return 0; -} -_ACEOF -if ac_fn_cxx_try_compile "$LINENO"; then : - ac_cv_header_stdc=yes -else - ac_cv_header_stdc=no -fi -rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext -if test $ac_cv_header_stdc = yes; then - # SunOS 4.x string.h does not declare mem*, contrary to ANSI. - cat confdefs.h - <<_ACEOF >conftest.$ac_ext -/* end confdefs.h. */ -#include -_ACEOF -if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | - $EGREP "memchr" >/dev/null 2>&1; then : -else - ac_cv_header_stdc=no -fi -rm -f conftest* -fi -if test $ac_cv_header_stdc = yes; then - # ISC 2.0.2 stdlib.h does not declare free, contrary to ANSI. - cat confdefs.h - <<_ACEOF >conftest.$ac_ext -/* end confdefs.h. */ -#include -_ACEOF -if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | - $EGREP "free" >/dev/null 2>&1; then : +if test $ac_cv_header_stdlib_h = yes && test $ac_cv_header_string_h = yes +then : -else - ac_cv_header_stdc=no -fi -rm -f conftest* +printf "%s\n" "#define STDC_HEADERS 1" >>confdefs.h fi +ac_fn_cxx_check_header_compile "$LINENO" "endian.h" "ac_cv_header_endian_h" "$ac_includes_default" +if test "x$ac_cv_header_endian_h" = xyes +then : + printf "%s\n" "#define HAVE_ENDIAN_H 1" >>confdefs.h -if test $ac_cv_header_stdc = yes; then - # /bin/cc in Irix-4.0.5 gets non-ANSI ctype macros unless using -ansi. - if test "$cross_compiling" = yes; then : - : -else - cat confdefs.h - <<_ACEOF >conftest.$ac_ext -/* end confdefs.h. */ -#include -#include -#if ((' ' & 0x0FF) == 0x020) -# define ISLOWER(c) ('a' <= (c) && (c) <= 'z') -# define TOUPPER(c) (ISLOWER(c) ? 'A' + ((c) - 'a') : (c)) -#else -# define ISLOWER(c) \ - (('a' <= (c) && (c) <= 'i') \ - || ('j' <= (c) && (c) <= 'r') \ - || ('s' <= (c) && (c) <= 'z')) -# define TOUPPER(c) (ISLOWER(c) ? ((c) | 0x40) : (c)) -#endif - -#define XOR(e, f) (((e) && !(f)) || (!(e) && (f))) -int -main () -{ - int i; - for (i = 0; i < 256; i++) - if (XOR (islower (i), ISLOWER (i)) - || toupper (i) != TOUPPER (i)) - return 2; - return 0; -} -_ACEOF -if ac_fn_cxx_try_run "$LINENO"; then : - -else - ac_cv_header_stdc=no fi -rm -f core *.core core.conftest.* gmon.out bb.out conftest$ac_exeext \ - conftest.$ac_objext conftest.beam conftest.$ac_ext +ac_fn_cxx_check_header_compile "$LINENO" "sys/endian.h" "ac_cv_header_sys_endian_h" "$ac_includes_default" +if test "x$ac_cv_header_sys_endian_h" = xyes +then : + printf "%s\n" "#define HAVE_SYS_ENDIAN_H 1" >>confdefs.h + fi +ac_fn_cxx_check_header_compile "$LINENO" "machine/endian.h" "ac_cv_header_machine_endian_h" "$ac_includes_default" +if test "x$ac_cv_header_machine_endian_h" = xyes +then : + printf "%s\n" "#define HAVE_MACHINE_ENDIAN_H 1" >>confdefs.h fi +ac_fn_cxx_check_header_compile "$LINENO" "sys/isa_defs.h" "ac_cv_header_sys_isa_defs_h" "$ac_includes_default" +if test "x$ac_cv_header_sys_isa_defs_h" = xyes +then : + printf "%s\n" "#define HAVE_SYS_ISA_DEFS_H 1" >>confdefs.h + fi -{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_header_stdc" >&5 -$as_echo "$ac_cv_header_stdc" >&6; } -if test $ac_cv_header_stdc = yes; then -$as_echo "#define STDC_HEADERS 1" >>confdefs.h +ac_fn_cxx_check_header_compile "$LINENO" "getopt.h" "ac_cv_header_getopt_h" "$ac_includes_default" +if test "x$ac_cv_header_getopt_h" = xyes +then : + printf "%s\n" "#define HAVE_GETOPT_H 1" >>confdefs.h fi -for ac_header in endian.h sys/endian.h machine/endian.h sys/isa_defs.h -do : - as_ac_Header=`$as_echo "ac_cv_header_$ac_header" | $as_tr_sh` -ac_fn_cxx_check_header_mongrel "$LINENO" "$ac_header" "$as_ac_Header" "$ac_includes_default" -if eval test \"x\$"$as_ac_Header"\" = x"yes"; then : - cat >>confdefs.h <<_ACEOF -#define `$as_echo "HAVE_$ac_header" | $as_tr_cpp` 1 -_ACEOF +ac_fn_cxx_check_header_compile "$LINENO" "unistd.h" "ac_cv_header_unistd_h" "$ac_includes_default" +if test "x$ac_cv_header_unistd_h" = xyes +then : + printf "%s\n" "#define HAVE_UNISTD_H 1" >>confdefs.h fi -done - -for ac_header in getopt.h -do : - ac_fn_cxx_check_header_mongrel "$LINENO" "getopt.h" "ac_cv_header_getopt_h" "$ac_includes_default" -if test "x$ac_cv_header_getopt_h" = xyes; then : - cat >>confdefs.h <<_ACEOF -#define HAVE_GETOPT_H 1 -_ACEOF +ac_fn_cxx_check_header_compile "$LINENO" "termios.h" "ac_cv_header_termios_h" "$ac_includes_default" +if test "x$ac_cv_header_termios_h" = xyes +then : + printf "%s\n" "#define HAVE_TERMIOS_H 1" >>confdefs.h fi -done - -for ac_header in unistd.h -do : - ac_fn_cxx_check_header_mongrel "$LINENO" "unistd.h" "ac_cv_header_unistd_h" "$ac_includes_default" -if test "x$ac_cv_header_unistd_h" = xyes; then : - cat >>confdefs.h <<_ACEOF -#define HAVE_UNISTD_H 1 -_ACEOF +ac_fn_cxx_check_header_compile "$LINENO" "inttypes.h" "ac_cv_header_inttypes_h" "$ac_includes_default" +if test "x$ac_cv_header_inttypes_h" = xyes +then : + printf "%s\n" "#define HAVE_INTTYPES_H 1" >>confdefs.h fi -done +ac_fn_cxx_check_header_compile "$LINENO" "cstdint.h" "ac_cv_header_cstdint_h" "$ac_includes_default" +if test "x$ac_cv_header_cstdint_h" = xyes +then : + printf "%s\n" "#define HAVE_CSTDINT_H 1" >>confdefs.h -for ac_header in termios.h -do : - ac_fn_cxx_check_header_mongrel "$LINENO" "termios.h" "ac_cv_header_termios_h" "$ac_includes_default" -if test "x$ac_cv_header_termios_h" = xyes; then : - cat >>confdefs.h <<_ACEOF -#define HAVE_TERMIOS_H 1 -_ACEOF +fi + +ac_fn_cxx_check_header_compile "$LINENO" "stdint.h" "ac_cv_header_stdint_h" "$ac_includes_default" +if test "x$ac_cv_header_stdint_h" = xyes +then : + printf "%s\n" "#define HAVE_STDINT_H 1" >>confdefs.h fi -done +ac_fn_cxx_check_header_compile "$LINENO" "sys/wait.h" "ac_cv_header_sys_wait_h" "$ac_includes_default" +if test "x$ac_cv_header_sys_wait_h" = xyes +then : + printf "%s\n" "#define HAVE_SYS_WAIT_H 1" >>confdefs.h + +fi -ac_fn_cxx_check_header_mongrel "$LINENO" "curses.h" "ac_cv_header_curses_h" "$ac_includes_default" -if test "x$ac_cv_header_curses_h" = xyes; then : +ac_fn_cxx_check_header_compile "$LINENO" "curses.h" "ac_cv_header_curses_h" "$ac_includes_default" +if test "x$ac_cv_header_curses_h" = xyes +then : -$as_echo "#define HAVE_CURSES_H 1" >>confdefs.h +printf "%s\n" "#define HAVE_CURSES_H 1" >>confdefs.h curses_h_ok=yes -else +else $as_nop curses_h_ok=no fi - ucsim_cv_socket="unknown" -ac_fn_cxx_check_header_mongrel "$LINENO" "sys/socket.h" "ac_cv_header_sys_socket_h" "$ac_includes_default" -if test "x$ac_cv_header_sys_socket_h" = xyes; then : +ac_fn_cxx_check_header_compile "$LINENO" "sys/socket.h" "ac_cv_header_sys_socket_h" "$ac_includes_default" +if test "x$ac_cv_header_sys_socket_h" = xyes +then : -$as_echo "#define HAVE_SYS_SOCKET_H 1" >>confdefs.h +printf "%s\n" "#define HAVE_SYS_SOCKET_H 1" >>confdefs.h -$as_echo "#define SOCKET_AVAIL 1" >>confdefs.h +printf "%s\n" "#define SOCKET_AVAIL 1" >>confdefs.h -cat >>confdefs.h <<_ACEOF -#define UCSOCKET_T int -_ACEOF +printf "%s\n" "#define UCSOCKET_T int" >>confdefs.h ucsim_cv_socket="" fi - WINSOCK_AVAIL=0 if test $ucsim_cv_socket = unknown; then - ac_fn_cxx_check_header_mongrel "$LINENO" "winsock2.h" "ac_cv_header_winsock2_h" "$ac_includes_default" -if test "x$ac_cv_header_winsock2_h" = xyes; then : + ac_fn_cxx_check_header_compile "$LINENO" "winsock2.h" "ac_cv_header_winsock2_h" "$ac_includes_default" +if test "x$ac_cv_header_winsock2_h" = xyes +then : -$as_echo "#define HAVE_WINSOCK2_H 1" >>confdefs.h +printf "%s\n" "#define HAVE_WINSOCK2_H 1" >>confdefs.h -$as_echo "#define SOCKET_AVAIL 1" >>confdefs.h +printf "%s\n" "#define SOCKET_AVAIL 1" >>confdefs.h -cat >>confdefs.h <<_ACEOF -#define UCSOCKET_T SOCKET -_ACEOF +printf "%s\n" "#define UCSOCKET_T SOCKET" >>confdefs.h ucsim_cv_socket="" WINSOCK_AVAIL=1 fi - fi if test $ucsim_cv_socket != unknown; then - cat confdefs.h - <<_ACEOF >conftest.$ac_ext + +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking for grep that handles long lines and -e" >&5 +printf %s "checking for grep that handles long lines and -e... " >&6; } +if test ${ac_cv_path_GREP+y} +then : + printf %s "(cached) " >&6 +else $as_nop + if test -z "$GREP"; then + ac_path_GREP_found=false + # Loop through the user's path and test for each of PROGNAME-LIST + as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH$PATH_SEPARATOR/usr/xpg4/bin +do + IFS=$as_save_IFS + case $as_dir in #((( + '') as_dir=./ ;; + */) ;; + *) as_dir=$as_dir/ ;; + esac + for ac_prog in grep ggrep + do + for ac_exec_ext in '' $ac_executable_extensions; do + ac_path_GREP="$as_dir$ac_prog$ac_exec_ext" + as_fn_executable_p "$ac_path_GREP" || continue +# Check for GNU ac_path_GREP and select it if it is found. + # Check for GNU $ac_path_GREP +case `"$ac_path_GREP" --version 2>&1` in +*GNU*) + ac_cv_path_GREP="$ac_path_GREP" ac_path_GREP_found=:;; +*) + ac_count=0 + printf %s 0123456789 >"conftest.in" + while : + do + cat "conftest.in" "conftest.in" >"conftest.tmp" + mv "conftest.tmp" "conftest.in" + cp "conftest.in" "conftest.nl" + printf "%s\n" 'GREP' >> "conftest.nl" + "$ac_path_GREP" -e 'GREP$' -e '-(cannot match)-' < "conftest.nl" >"conftest.out" 2>/dev/null || break + diff "conftest.out" "conftest.nl" >/dev/null 2>&1 || break + as_fn_arith $ac_count + 1 && ac_count=$as_val + if test $ac_count -gt ${ac_path_GREP_max-0}; then + # Best one so far, save it but keep looking for a better one + ac_cv_path_GREP="$ac_path_GREP" + ac_path_GREP_max=$ac_count + fi + # 10*(2^10) chars as input seems more than enough + test $ac_count -gt 10 && break + done + rm -f conftest.in conftest.tmp conftest.nl conftest.out;; +esac + + $ac_path_GREP_found && break 3 + done + done + done +IFS=$as_save_IFS + if test -z "$ac_cv_path_GREP"; then + as_fn_error $? "no acceptable grep could be found in $PATH$PATH_SEPARATOR/usr/xpg4/bin" "$LINENO" 5 + fi +else + ac_cv_path_GREP=$GREP +fi + +fi +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: $ac_cv_path_GREP" >&5 +printf "%s\n" "$ac_cv_path_GREP" >&6; } + GREP="$ac_cv_path_GREP" + + +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking for egrep" >&5 +printf %s "checking for egrep... " >&6; } +if test ${ac_cv_path_EGREP+y} +then : + printf %s "(cached) " >&6 +else $as_nop + if echo a | $GREP -E '(a|b)' >/dev/null 2>&1 + then ac_cv_path_EGREP="$GREP -E" + else + if test -z "$EGREP"; then + ac_path_EGREP_found=false + # Loop through the user's path and test for each of PROGNAME-LIST + as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH$PATH_SEPARATOR/usr/xpg4/bin +do + IFS=$as_save_IFS + case $as_dir in #((( + '') as_dir=./ ;; + */) ;; + *) as_dir=$as_dir/ ;; + esac + for ac_prog in egrep + do + for ac_exec_ext in '' $ac_executable_extensions; do + ac_path_EGREP="$as_dir$ac_prog$ac_exec_ext" + as_fn_executable_p "$ac_path_EGREP" || continue +# Check for GNU ac_path_EGREP and select it if it is found. + # Check for GNU $ac_path_EGREP +case `"$ac_path_EGREP" --version 2>&1` in +*GNU*) + ac_cv_path_EGREP="$ac_path_EGREP" ac_path_EGREP_found=:;; +*) + ac_count=0 + printf %s 0123456789 >"conftest.in" + while : + do + cat "conftest.in" "conftest.in" >"conftest.tmp" + mv "conftest.tmp" "conftest.in" + cp "conftest.in" "conftest.nl" + printf "%s\n" 'EGREP' >> "conftest.nl" + "$ac_path_EGREP" 'EGREP$' < "conftest.nl" >"conftest.out" 2>/dev/null || break + diff "conftest.out" "conftest.nl" >/dev/null 2>&1 || break + as_fn_arith $ac_count + 1 && ac_count=$as_val + if test $ac_count -gt ${ac_path_EGREP_max-0}; then + # Best one so far, save it but keep looking for a better one + ac_cv_path_EGREP="$ac_path_EGREP" + ac_path_EGREP_max=$ac_count + fi + # 10*(2^10) chars as input seems more than enough + test $ac_count -gt 10 && break + done + rm -f conftest.in conftest.tmp conftest.nl conftest.out;; +esac + + $ac_path_EGREP_found && break 3 + done + done + done +IFS=$as_save_IFS + if test -z "$ac_cv_path_EGREP"; then + as_fn_error $? "no acceptable egrep could be found in $PATH$PATH_SEPARATOR/usr/xpg4/bin" "$LINENO" 5 + fi +else + ac_cv_path_EGREP=$EGREP +fi + + fi +fi +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: $ac_cv_path_EGREP" >&5 +printf "%s\n" "$ac_cv_path_EGREP" >&6; } + EGREP="$ac_cv_path_EGREP" + + +cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ #include <$ucsim_cv_socket> _ACEOF if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | - $EGREP "socklen_t" >/dev/null 2>&1; then : + $EGREP "socklen_t" >/dev/null 2>&1 +then : -cat >>confdefs.h <<_ACEOF -#define SOCKLEN_T socklen_t -_ACEOF +printf "%s\n" "#define SOCKLEN_T socklen_t" >>confdefs.h -else +else $as_nop -cat >>confdefs.h <<_ACEOF -#define SOCKLEN_T uint -_ACEOF +printf "%s\n" "#define SOCKLEN_T uint" >>confdefs.h fi -rm -f conftest* +rm -rf conftest* fi -cat >>confdefs.h <<_ACEOF -#define HEADER_SOCKET ${ucsim_cv_socket} -_ACEOF +printf "%s\n" "#define HEADER_SOCKET ${ucsim_cv_socket}" >>confdefs.h -ac_fn_cxx_check_header_mongrel "$LINENO" "dlfcn.h" "ac_cv_header_dlfcn_h" "$ac_includes_default" -if test "x$ac_cv_header_dlfcn_h" = xyes; then : +ac_fn_cxx_check_header_compile "$LINENO" "dlfcn.h" "ac_cv_header_dlfcn_h" "$ac_includes_default" +if test "x$ac_cv_header_dlfcn_h" = xyes +then : fi - ac_header_dirent=no for ac_hdr in dirent.h sys/ndir.h sys/dir.h ndir.h; do - as_ac_Header=`$as_echo "ac_cv_header_dirent_$ac_hdr" | $as_tr_sh` -{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_hdr that defines DIR" >&5 -$as_echo_n "checking for $ac_hdr that defines DIR... " >&6; } -if eval \${$as_ac_Header+:} false; then : - $as_echo_n "(cached) " >&6 -else + as_ac_Header=`printf "%s\n" "ac_cv_header_dirent_$ac_hdr" | $as_tr_sh` +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking for $ac_hdr that defines DIR" >&5 +printf %s "checking for $ac_hdr that defines DIR... " >&6; } +if eval test \${$as_ac_Header+y} +then : + printf %s "(cached) " >&6 +else $as_nop cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ #include #include <$ac_hdr> int -main () +main (void) { if ((DIR *) 0) return 0; @@ -16573,19 +6104,21 @@ return 0; } _ACEOF -if ac_fn_cxx_try_compile "$LINENO"; then : +if ac_fn_cxx_try_compile "$LINENO" +then : eval "$as_ac_Header=yes" -else +else $as_nop eval "$as_ac_Header=no" fi -rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +rm -f core conftest.err conftest.$ac_objext conftest.beam conftest.$ac_ext fi eval ac_res=\$$as_ac_Header - { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5 -$as_echo "$ac_res" >&6; } -if eval test \"x\$"$as_ac_Header"\" = x"yes"; then : + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5 +printf "%s\n" "$ac_res" >&6; } +if eval test \"x\$"$as_ac_Header"\" = x"yes" +then : cat >>confdefs.h <<_ACEOF -#define `$as_echo "HAVE_$ac_hdr" | $as_tr_cpp` 1 +#define `printf "%s\n" "HAVE_$ac_hdr" | $as_tr_cpp` 1 _ACEOF ac_header_dirent=$ac_hdr; break @@ -16594,115 +6127,119 @@ done # Two versions of opendir et al. are in -ldir and -lx on SCO Xenix. if test $ac_header_dirent = dirent.h; then - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for library containing opendir" >&5 -$as_echo_n "checking for library containing opendir... " >&6; } -if ${ac_cv_search_opendir+:} false; then : - $as_echo_n "(cached) " >&6 -else + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking for library containing opendir" >&5 +printf %s "checking for library containing opendir... " >&6; } +if test ${ac_cv_search_opendir+y} +then : + printf %s "(cached) " >&6 +else $as_nop ac_func_search_save_LIBS=$LIBS cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ -/* Override any GCC internal prototype to avoid an error. - Use char because int might match the return type of a GCC - builtin and then its argument prototype would still apply. */ -#ifdef __cplusplus -extern "C" -#endif -char opendir (); +namespace conftest { + extern "C" int opendir (); +} int -main () +main (void) { -return opendir (); +return conftest::opendir (); ; return 0; } _ACEOF -for ac_lib in '' dir; do +for ac_lib in '' dir +do if test -z "$ac_lib"; then ac_res="none required" else ac_res=-l$ac_lib LIBS="-l$ac_lib $ac_func_search_save_LIBS" fi - if ac_fn_cxx_try_link "$LINENO"; then : + if ac_fn_cxx_try_link "$LINENO" +then : ac_cv_search_opendir=$ac_res fi -rm -f core conftest.err conftest.$ac_objext \ +rm -f core conftest.err conftest.$ac_objext conftest.beam \ conftest$ac_exeext - if ${ac_cv_search_opendir+:} false; then : + if test ${ac_cv_search_opendir+y} +then : break fi done -if ${ac_cv_search_opendir+:} false; then : +if test ${ac_cv_search_opendir+y} +then : -else +else $as_nop ac_cv_search_opendir=no fi rm conftest.$ac_ext LIBS=$ac_func_search_save_LIBS fi -{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_search_opendir" >&5 -$as_echo "$ac_cv_search_opendir" >&6; } +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: $ac_cv_search_opendir" >&5 +printf "%s\n" "$ac_cv_search_opendir" >&6; } ac_res=$ac_cv_search_opendir -if test "$ac_res" != no; then : +if test "$ac_res" != no +then : test "$ac_res" = "none required" || LIBS="$ac_res $LIBS" fi else - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for library containing opendir" >&5 -$as_echo_n "checking for library containing opendir... " >&6; } -if ${ac_cv_search_opendir+:} false; then : - $as_echo_n "(cached) " >&6 -else + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking for library containing opendir" >&5 +printf %s "checking for library containing opendir... " >&6; } +if test ${ac_cv_search_opendir+y} +then : + printf %s "(cached) " >&6 +else $as_nop ac_func_search_save_LIBS=$LIBS cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ -/* Override any GCC internal prototype to avoid an error. - Use char because int might match the return type of a GCC - builtin and then its argument prototype would still apply. */ -#ifdef __cplusplus -extern "C" -#endif -char opendir (); +namespace conftest { + extern "C" int opendir (); +} int -main () +main (void) { -return opendir (); +return conftest::opendir (); ; return 0; } _ACEOF -for ac_lib in '' x; do +for ac_lib in '' x +do if test -z "$ac_lib"; then ac_res="none required" else ac_res=-l$ac_lib LIBS="-l$ac_lib $ac_func_search_save_LIBS" fi - if ac_fn_cxx_try_link "$LINENO"; then : + if ac_fn_cxx_try_link "$LINENO" +then : ac_cv_search_opendir=$ac_res fi -rm -f core conftest.err conftest.$ac_objext \ +rm -f core conftest.err conftest.$ac_objext conftest.beam \ conftest$ac_exeext - if ${ac_cv_search_opendir+:} false; then : + if test ${ac_cv_search_opendir+y} +then : break fi done -if ${ac_cv_search_opendir+:} false; then : +if test ${ac_cv_search_opendir+y} +then : -else +else $as_nop ac_cv_search_opendir=no fi rm conftest.$ac_ext LIBS=$ac_func_search_save_LIBS fi -{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_search_opendir" >&5 -$as_echo "$ac_cv_search_opendir" >&6; } +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: $ac_cv_search_opendir" >&5 +printf "%s\n" "$ac_cv_search_opendir" >&6; } ac_res=$ac_cv_search_opendir -if test "$ac_res" != no; then : +if test "$ac_res" != no +then : test "$ac_res" = "none required" || LIBS="$ac_res $LIBS" fi @@ -16712,11 +6249,12 @@ # This must be after CXXCPP -{ $as_echo "$as_me:${as_lineno-$LINENO}: checking which header file defines FD_ macros" >&5 -$as_echo_n "checking which header file defines FD_ macros... " >&6; } -if ${ucsim_cv_fd+:} false; then : - $as_echo_n "(cached) " >&6 -else +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking which header file defines FD_ macros" >&5 +printf %s "checking which header file defines FD_ macros... " >&6; } +if test ${ucsim_cv_fd+y} +then : + printf %s "(cached) " >&6 +else $as_nop ucsim_cv_fd="unknown" cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ @@ -16727,10 +6265,11 @@ #endif _ACEOF if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | - $EGREP "yes" >/dev/null 2>&1; then : + $EGREP "yes" >/dev/null 2>&1 +then : ucsim_cv_fd="" fi -rm -f conftest* +rm -rf conftest* cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ @@ -16741,10 +6280,11 @@ #endif _ACEOF if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | - $EGREP "yes" >/dev/null 2>&1; then : + $EGREP "yes" >/dev/null 2>&1 +then : ucsim_cv_fd="" fi -rm -f conftest* +rm -rf conftest* cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ @@ -16755,10 +6295,11 @@ #endif _ACEOF if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | - $EGREP "yes" >/dev/null 2>&1; then : + $EGREP "yes" >/dev/null 2>&1 +then : ucsim_cv_fd="" fi -rm -f conftest* +rm -rf conftest* cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ @@ -16769,66 +6310,60 @@ #endif _ACEOF if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | - $EGREP "yes" >/dev/null 2>&1; then : + $EGREP "yes" >/dev/null 2>&1 +then : ucsim_cv_fd="" fi -rm -f conftest* +rm -rf conftest* fi -{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ucsim_cv_fd" >&5 -$as_echo "$ucsim_cv_fd" >&6; } +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: $ucsim_cv_fd" >&5 +printf "%s\n" "$ucsim_cv_fd" >&6; } ucsim_cv_header_ok=0 if echo $ucsim_cv_fd|grep time >/dev/null 2>&1; then -$as_echo "#define FD_NEED_TIME_H 1" >>confdefs.h +printf "%s\n" "#define FD_NEED_TIME_H 1" >>confdefs.h ucsim_cv_header_ok=1 else -$as_echo "#define FD_NEED_TIME_H 0" >>confdefs.h +printf "%s\n" "#define FD_NEED_TIME_H 0" >>confdefs.h fi if echo $ucsim_cv_fd|grep types >/dev/null 2>&1; then -$as_echo "#define FD_NEED_TYPES_H 1" >>confdefs.h +printf "%s\n" "#define FD_NEED_TYPES_H 1" >>confdefs.h ucsim_cv_header_ok=1 else -$as_echo "#define FD_NEED_TYPES_H 0" >>confdefs.h +printf "%s\n" "#define FD_NEED_TYPES_H 0" >>confdefs.h fi if echo $ucsim_cv_fd|grep select >/dev/null 2>&1; then -$as_echo "#define FD_NEED_SELECT_H 1" >>confdefs.h +printf "%s\n" "#define FD_NEED_SELECT_H 1" >>confdefs.h ucsim_cv_header_ok=1 else -$as_echo "#define FD_NEED_SELECT_H 0" >>confdefs.h +printf "%s\n" "#define FD_NEED_SELECT_H 0" >>confdefs.h fi if echo $ucsim_cv_fd|grep winsock2 >/dev/null 2>&1; then -$as_echo "#define FD_NEED_WINSOCK2_H 1" >>confdefs.h +printf "%s\n" "#define FD_NEED_WINSOCK2_H 1" >>confdefs.h ucsim_cv_header_ok=1 else -$as_echo "#define FD_NEED_WINSOCK2_H 0" >>confdefs.h +printf "%s\n" "#define FD_NEED_WINSOCK2_H 0" >>confdefs.h fi -cat >>confdefs.h <<_ACEOF -#define FD_HEADER_OK ${ucsim_cv_header_ok} -_ACEOF - - -cat >>confdefs.h <<_ACEOF -#define HEADER_FD ${ucsim_cv_fd} -_ACEOF +printf "%s\n" "#define HEADER_FD ${ucsim_cv_fd}" >>confdefs.h @@ -16837,136 +6372,127 @@ if echo $ucsim_cv_socket|grep winsock2 >/dev/null 2>&1; then LIBS="-lws2_32 $LIBS" else - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for socket in -lsocket" >&5 -$as_echo_n "checking for socket in -lsocket... " >&6; } -if ${ac_cv_lib_socket_socket+:} false; then : - $as_echo_n "(cached) " >&6 -else + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking for socket in -lsocket" >&5 +printf %s "checking for socket in -lsocket... " >&6; } +if test ${ac_cv_lib_socket_socket+y} +then : + printf %s "(cached) " >&6 +else $as_nop ac_check_lib_save_LIBS=$LIBS LIBS="-lsocket $LIBS" cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ -/* Override any GCC internal prototype to avoid an error. - Use char because int might match the return type of a GCC - builtin and then its argument prototype would still apply. */ -#ifdef __cplusplus -extern "C" -#endif -char socket (); +namespace conftest { + extern "C" int socket (); +} int -main () +main (void) { -return socket (); +return conftest::socket (); ; return 0; } _ACEOF -if ac_fn_cxx_try_link "$LINENO"; then : +if ac_fn_cxx_try_link "$LINENO" +then : ac_cv_lib_socket_socket=yes -else +else $as_nop ac_cv_lib_socket_socket=no fi -rm -f core conftest.err conftest.$ac_objext \ +rm -f core conftest.err conftest.$ac_objext conftest.beam \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi -{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_socket_socket" >&5 -$as_echo "$ac_cv_lib_socket_socket" >&6; } -if test "x$ac_cv_lib_socket_socket" = xyes; then : - cat >>confdefs.h <<_ACEOF -#define HAVE_LIBSOCKET 1 -_ACEOF +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_socket_socket" >&5 +printf "%s\n" "$ac_cv_lib_socket_socket" >&6; } +if test "x$ac_cv_lib_socket_socket" = xyes +then : + printf "%s\n" "#define HAVE_LIBSOCKET 1" >>confdefs.h LIBS="-lsocket $LIBS" fi - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for xdr_short in -lnsl" >&5 -$as_echo_n "checking for xdr_short in -lnsl... " >&6; } -if ${ac_cv_lib_nsl_xdr_short+:} false; then : - $as_echo_n "(cached) " >&6 -else + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking for xdr_short in -lnsl" >&5 +printf %s "checking for xdr_short in -lnsl... " >&6; } +if test ${ac_cv_lib_nsl_xdr_short+y} +then : + printf %s "(cached) " >&6 +else $as_nop ac_check_lib_save_LIBS=$LIBS LIBS="-lnsl $LIBS" cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ -/* Override any GCC internal prototype to avoid an error. - Use char because int might match the return type of a GCC - builtin and then its argument prototype would still apply. */ -#ifdef __cplusplus -extern "C" -#endif -char xdr_short (); +namespace conftest { + extern "C" int xdr_short (); +} int -main () +main (void) { -return xdr_short (); +return conftest::xdr_short (); ; return 0; } _ACEOF -if ac_fn_cxx_try_link "$LINENO"; then : +if ac_fn_cxx_try_link "$LINENO" +then : ac_cv_lib_nsl_xdr_short=yes -else +else $as_nop ac_cv_lib_nsl_xdr_short=no fi -rm -f core conftest.err conftest.$ac_objext \ +rm -f core conftest.err conftest.$ac_objext conftest.beam \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi -{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_nsl_xdr_short" >&5 -$as_echo "$ac_cv_lib_nsl_xdr_short" >&6; } -if test "x$ac_cv_lib_nsl_xdr_short" = xyes; then : - cat >>confdefs.h <<_ACEOF -#define HAVE_LIBNSL 1 -_ACEOF +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_nsl_xdr_short" >&5 +printf "%s\n" "$ac_cv_lib_nsl_xdr_short" >&6; } +if test "x$ac_cv_lib_nsl_xdr_short" = xyes +then : + printf "%s\n" "#define HAVE_LIBNSL 1" >>confdefs.h LIBS="-lnsl $LIBS" fi - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for nanosleep in -lrt" >&5 -$as_echo_n "checking for nanosleep in -lrt... " >&6; } -if ${ac_cv_lib_rt_nanosleep+:} false; then : - $as_echo_n "(cached) " >&6 -else + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking for nanosleep in -lrt" >&5 +printf %s "checking for nanosleep in -lrt... " >&6; } +if test ${ac_cv_lib_rt_nanosleep+y} +then : + printf %s "(cached) " >&6 +else $as_nop ac_check_lib_save_LIBS=$LIBS LIBS="-lrt $LIBS" cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ -/* Override any GCC internal prototype to avoid an error. - Use char because int might match the return type of a GCC - builtin and then its argument prototype would still apply. */ -#ifdef __cplusplus -extern "C" -#endif -char nanosleep (); +namespace conftest { + extern "C" int nanosleep (); +} int -main () +main (void) { -return nanosleep (); +return conftest::nanosleep (); ; return 0; } _ACEOF -if ac_fn_cxx_try_link "$LINENO"; then : +if ac_fn_cxx_try_link "$LINENO" +then : ac_cv_lib_rt_nanosleep=yes -else +else $as_nop ac_cv_lib_rt_nanosleep=no fi -rm -f core conftest.err conftest.$ac_objext \ +rm -f core conftest.err conftest.$ac_objext conftest.beam \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi -{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_rt_nanosleep" >&5 -$as_echo "$ac_cv_lib_rt_nanosleep" >&6; } -if test "x$ac_cv_lib_rt_nanosleep" = xyes; then : - cat >>confdefs.h <<_ACEOF -#define HAVE_LIBRT 1 -_ACEOF +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_rt_nanosleep" >&5 +printf "%s\n" "$ac_cv_lib_rt_nanosleep" >&6; } +if test "x$ac_cv_lib_rt_nanosleep" = xyes +then : + printf "%s\n" "#define HAVE_LIBRT 1" >>confdefs.h LIBS="-lrt $LIBS" @@ -16974,46 +6500,45 @@ fi -{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for dlopen in -ldl" >&5 -$as_echo_n "checking for dlopen in -ldl... " >&6; } -if ${ac_cv_lib_dl_dlopen+:} false; then : - $as_echo_n "(cached) " >&6 -else +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking for dlopen in -ldl" >&5 +printf %s "checking for dlopen in -ldl... " >&6; } +if test ${ac_cv_lib_dl_dlopen+y} +then : + printf %s "(cached) " >&6 +else $as_nop ac_check_lib_save_LIBS=$LIBS LIBS="-ldl $LIBS" cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ -/* Override any GCC internal prototype to avoid an error. - Use char because int might match the return type of a GCC - builtin and then its argument prototype would still apply. */ -#ifdef __cplusplus -extern "C" -#endif -char dlopen (); +namespace conftest { + extern "C" int dlopen (); +} int -main () +main (void) { -return dlopen (); +return conftest::dlopen (); ; return 0; } _ACEOF -if ac_fn_cxx_try_link "$LINENO"; then : +if ac_fn_cxx_try_link "$LINENO" +then : ac_cv_lib_dl_dlopen=yes -else +else $as_nop ac_cv_lib_dl_dlopen=no fi -rm -f core conftest.err conftest.$ac_objext \ +rm -f core conftest.err conftest.$ac_objext conftest.beam \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi -{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_dl_dlopen" >&5 -$as_echo "$ac_cv_lib_dl_dlopen" >&6; } -if test "x$ac_cv_lib_dl_dlopen" = xyes; then : +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_dl_dlopen" >&5 +printf "%s\n" "$ac_cv_lib_dl_dlopen" >&6; } +if test "x$ac_cv_lib_dl_dlopen" = xyes +then : dl_ok="yes" DL="-ldl" -else +else $as_nop dl_ok="no" DL="" fi @@ -17021,65 +6546,51 @@ -#AC_CHECK_LIB(panel,panel_above, -#panel_ok="yes" -#curses_ok="yes" -#CURSES_LIBS="-lpanel -lcurses" -#, -#panel_ok="no" -#AC_CHECK_LIB(curses,nl, -#curses_ok="yes" -#CURSES_LIBS="-lcurses" -#, -#curses_ok="no") -#, -#-lcurses) CURSES_LIBS="" if test $curses_h_ok != yes; then panel_ok="no" curses_ok="no" else - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for panel_above in -lpanel" >&5 -$as_echo_n "checking for panel_above in -lpanel... " >&6; } -if ${ac_cv_lib_panel_panel_above+:} false; then : - $as_echo_n "(cached) " >&6 -else + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking for panel_above in -lpanel" >&5 +printf %s "checking for panel_above in -lpanel... " >&6; } +if test ${ac_cv_lib_panel_panel_above+y} +then : + printf %s "(cached) " >&6 +else $as_nop ac_check_lib_save_LIBS=$LIBS LIBS="-lpanel $LIBS" cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ -/* Override any GCC internal prototype to avoid an error. - Use char because int might match the return type of a GCC - builtin and then its argument prototype would still apply. */ -#ifdef __cplusplus -extern "C" -#endif -char panel_above (); +namespace conftest { + extern "C" int panel_above (); +} int -main () +main (void) { -return panel_above (); +return conftest::panel_above (); ; return 0; } _ACEOF -if ac_fn_cxx_try_link "$LINENO"; then : +if ac_fn_cxx_try_link "$LINENO" +then : ac_cv_lib_panel_panel_above=yes -else +else $as_nop ac_cv_lib_panel_panel_above=no fi -rm -f core conftest.err conftest.$ac_objext \ +rm -f core conftest.err conftest.$ac_objext conftest.beam \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi -{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_panel_panel_above" >&5 -$as_echo "$ac_cv_lib_panel_panel_above" >&6; } -if test "x$ac_cv_lib_panel_panel_above" = xyes; then : +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_panel_panel_above" >&5 +printf "%s\n" "$ac_cv_lib_panel_panel_above" >&6; } +if test "x$ac_cv_lib_panel_panel_above" = xyes +then : panel_ok="yes" curses_ok="no" CURSES_LIBS="-lpanel" -else +else $as_nop panel_ok="no" curses_ok="no" @@ -17087,92 +6598,90 @@ if test $curses_ok != yes; then - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for nl in -lcurses" >&5 -$as_echo_n "checking for nl in -lcurses... " >&6; } -if ${ac_cv_lib_curses_nl+:} false; then : - $as_echo_n "(cached) " >&6 -else + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking for nl in -lcurses" >&5 +printf %s "checking for nl in -lcurses... " >&6; } +if test ${ac_cv_lib_curses_nl+y} +then : + printf %s "(cached) " >&6 +else $as_nop ac_check_lib_save_LIBS=$LIBS LIBS="-lcurses $LIBS" cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ -/* Override any GCC internal prototype to avoid an error. - Use char because int might match the return type of a GCC - builtin and then its argument prototype would still apply. */ -#ifdef __cplusplus -extern "C" -#endif -char nl (); +namespace conftest { + extern "C" int nl (); +} int -main () +main (void) { -return nl (); +return conftest::nl (); ; return 0; } _ACEOF -if ac_fn_cxx_try_link "$LINENO"; then : +if ac_fn_cxx_try_link "$LINENO" +then : ac_cv_lib_curses_nl=yes -else +else $as_nop ac_cv_lib_curses_nl=no fi -rm -f core conftest.err conftest.$ac_objext \ +rm -f core conftest.err conftest.$ac_objext conftest.beam \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi -{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_curses_nl" >&5 -$as_echo "$ac_cv_lib_curses_nl" >&6; } -if test "x$ac_cv_lib_curses_nl" = xyes; then : +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_curses_nl" >&5 +printf "%s\n" "$ac_cv_lib_curses_nl" >&6; } +if test "x$ac_cv_lib_curses_nl" = xyes +then : curses_ok="yes" CURSES_LIBS="${CURSES_LIBS} -lcurses" -else +else $as_nop curses_ok="no" fi fi if test $curses_ok != yes; then - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for nl in -lncurses" >&5 -$as_echo_n "checking for nl in -lncurses... " >&6; } -if ${ac_cv_lib_ncurses_nl+:} false; then : - $as_echo_n "(cached) " >&6 -else + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking for nl in -lncurses" >&5 +printf %s "checking for nl in -lncurses... " >&6; } +if test ${ac_cv_lib_ncurses_nl+y} +then : + printf %s "(cached) " >&6 +else $as_nop ac_check_lib_save_LIBS=$LIBS LIBS="-lncurses $LIBS" cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ -/* Override any GCC internal prototype to avoid an error. - Use char because int might match the return type of a GCC - builtin and then its argument prototype would still apply. */ -#ifdef __cplusplus -extern "C" -#endif -char nl (); +namespace conftest { + extern "C" int nl (); +} int -main () +main (void) { -return nl (); +return conftest::nl (); ; return 0; } _ACEOF -if ac_fn_cxx_try_link "$LINENO"; then : +if ac_fn_cxx_try_link "$LINENO" +then : ac_cv_lib_ncurses_nl=yes -else +else $as_nop ac_cv_lib_ncurses_nl=no fi -rm -f core conftest.err conftest.$ac_objext \ +rm -f core conftest.err conftest.$ac_objext conftest.beam \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi -{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_ncurses_nl" >&5 -$as_echo "$ac_cv_lib_ncurses_nl" >&6; } -if test "x$ac_cv_lib_ncurses_nl" = xyes; then : +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_ncurses_nl" >&5 +printf "%s\n" "$ac_cv_lib_ncurses_nl" >&6; } +if test "x$ac_cv_lib_ncurses_nl" = xyes +then : curses_ok="yes" CURSES_LIBS="${CURSES_LIBS} -lncurses" -else +else $as_nop curses_ok="no" fi @@ -17183,168 +6692,388 @@ -for ac_func in vasprintf -do : - ac_fn_cxx_check_func "$LINENO" "vasprintf" "ac_cv_func_vasprintf" -if test "x$ac_cv_func_vasprintf" = xyes; then : - cat >>confdefs.h <<_ACEOF -#define HAVE_VASPRINTF 1 -_ACEOF - -fi -done - -for ac_func in strdup -do : - ac_fn_cxx_check_func "$LINENO" "strdup" "ac_cv_func_strdup" -if test "x$ac_cv_func_strdup" = xyes; then : - cat >>confdefs.h <<_ACEOF -#define HAVE_STRDUP 1 -_ACEOF - -fi -done - -for ac_func in yylex -do : - ac_fn_cxx_check_func "$LINENO" "yylex" "ac_cv_func_yylex" -if test "x$ac_cv_func_yylex" = xyes; then : - cat >>confdefs.h <<_ACEOF -#define HAVE_YYLEX 1 -_ACEOF - -fi -done - -{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether scanf knows %a" >&5 -$as_echo_n "checking whether scanf knows %a... " >&6; } -if ${ucsim_cv_scanf_a+:} false; then : - $as_echo_n "(cached) " >&6 -else - echo "a b" >conftest.data -if test "$cross_compiling" = yes; then : - ucsim_cv_scanf_a="unknown" -else - cat confdefs.h - <<_ACEOF >conftest.$ac_ext + ac_fn_cxx_check_type "$LINENO" "pid_t" "ac_cv_type_pid_t" "$ac_includes_default +" +if test "x$ac_cv_type_pid_t" = xyes +then : + +else $as_nop + cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ -#include -void main(void) + #if defined _WIN64 && !defined __CYGWIN__ + LLP64 + #endif + +int +main (void) { - FILE *f; - char *a; - int i; - if ((f= fopen("conftest.data", "r")) == NULL) - exit(1); - i= fscanf(f, " %a[a-z] ", &a); - fclose(f); - if (i == 0) - exit(2); - if (i == 1) - exit(0); - exit(3); + + ; + return 0; } + _ACEOF -if ac_fn_cxx_try_run "$LINENO"; then : - ucsim_cv_scanf_a="yes" -else - ucsim_cv_scanf_a="no" -fi -rm -f core *.core core.conftest.* gmon.out bb.out conftest$ac_exeext \ - conftest.$ac_objext conftest.beam conftest.$ac_ext +if ac_fn_cxx_try_compile "$LINENO" +then : + ac_pid_type='int' +else $as_nop + ac_pid_type='__int64' fi +rm -f core conftest.err conftest.$ac_objext conftest.beam conftest.$ac_ext + +printf "%s\n" "#define pid_t $ac_pid_type" >>confdefs.h fi -{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ucsim_cv_scanf_a" >&5 -$as_echo "$ucsim_cv_scanf_a" >&6; } -if test "$ucsim_cv_scanf_a" = "yes"; then -$as_echo "#define SCANF_A 1" >>confdefs.h -fi -{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether getcwd is GNUish" >&5 -$as_echo_n "checking whether getcwd is GNUish... " >&6; } -if ${ucsim_cv_getcwd+:} false; then : - $as_echo_n "(cached) " >&6 -else - if test "$cross_compiling" = yes; then : - ucsim_cv_getcwd="unknown" -else +ac_func= +for ac_item in $ac_func_cxx_list +do + if test $ac_func; then + ac_fn_cxx_check_func "$LINENO" $ac_func ac_cv_func_$ac_func + if eval test \"x\$ac_cv_func_$ac_func\" = xyes; then + echo "#define $ac_item 1" >> confdefs.h + fi + ac_func= + else + ac_func=$ac_item + fi +done + + + +if test "x$ac_cv_func_fork" = xyes; then + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking for working fork" >&5 +printf %s "checking for working fork... " >&6; } +if test ${ac_cv_func_fork_works+y} +then : + printf %s "(cached) " >&6 +else $as_nop + if test "$cross_compiling" = yes +then : + ac_cv_func_fork_works=cross +else $as_nop cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ - -#include -void main(void) +$ac_includes_default +int +main (void) { - if ((getcwd(NULL, 0)) == NULL) - exit(1); - exit(0); + + /* By Ruediger Kuhlmann. */ + return fork () < 0; + + ; + return 0; } _ACEOF -if ac_fn_cxx_try_run "$LINENO"; then : - ucsim_cv_getcwd="yes" -else - ucsim_cv_getcwd="no" +if ac_fn_cxx_try_run "$LINENO" +then : + ac_cv_func_fork_works=yes +else $as_nop + ac_cv_func_fork_works=no fi rm -f core *.core core.conftest.* gmon.out bb.out conftest$ac_exeext \ conftest.$ac_objext conftest.beam conftest.$ac_ext fi - -fi -{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ucsim_cv_getcwd" >&5 -$as_echo "$ucsim_cv_getcwd" >&6; } -if test "$ucsim_cv_getcwd" = "yes"; then - -$as_echo "#define GNU_GETCWD 1" >>confdefs.h - fi +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: $ac_cv_func_fork_works" >&5 +printf "%s\n" "$ac_cv_func_fork_works" >&6; } - -#' - -{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for type of length pointer parameter of accept" >&5 -$as_echo_n "checking for type of length pointer parameter of accept... " >&6; } -if ${ucsim_cv_accept_length_type+:} false; then : - $as_echo_n "(cached) " >&6 else - ac_save_CPPFLAGS="$CPPFLAGS" - ucsim_cv_accept_length_type=no - for ac_val in int size_t socklen_t; do - CPPFLAGS="$ac_save_CPPFLAGS -DACCEPT_SOCKLEN_T=$ac_val" - cat confdefs.h - <<_ACEOF >conftest.$ac_ext + ac_cv_func_fork_works=$ac_cv_func_fork +fi +if test "x$ac_cv_func_fork_works" = xcross; then + case $host in + *-*-amigaos* | *-*-msdosdjgpp*) + # Override, as these systems have only a dummy fork() stub + ac_cv_func_fork_works=no + ;; + *) + ac_cv_func_fork_works=yes + ;; + esac + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: WARNING: result $ac_cv_func_fork_works guessed because of cross compilation" >&5 +printf "%s\n" "$as_me: WARNING: result $ac_cv_func_fork_works guessed because of cross compilation" >&2;} +fi +ac_cv_func_vfork_works=$ac_cv_func_vfork +if test "x$ac_cv_func_vfork" = xyes; then + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking for working vfork" >&5 +printf %s "checking for working vfork... " >&6; } +if test ${ac_cv_func_vfork_works+y} +then : + printf %s "(cached) " >&6 +else $as_nop + if test "$cross_compiling" = yes +then : + ac_cv_func_vfork_works=cross +else $as_nop + cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ -#include -#include ${ucsim_cv_socket} +/* Thanks to Paul Eggert for this test. */ +$ac_includes_default +#include +#include +#ifdef HAVE_VFORK_H +# include +#endif + +static void +do_nothing (int sig) +{ + (void) sig; +} + +/* On some sparc systems, changes by the child to local and incoming + argument registers are propagated back to the parent. The compiler + is told about this with #include , but some compilers + (e.g. gcc -O) don't grok . Test for this by using a + static variable whose address is put into a register that is + clobbered by the vfork. */ +static void +sparc_address_test (int arg) +{ + static pid_t child; + if (!child) { + child = vfork (); + if (child < 0) { + perror ("vfork"); + _exit(2); + } + if (!child) { + arg = getpid(); + write(-1, "", 0); + _exit (arg); + } + } +} + int -main () +main (void) { -struct sockaddr a; $ac_val len; accept (0, &a, &len); - ; - return 0; + pid_t parent = getpid (); + pid_t child; + + sparc_address_test (0); + + /* On Solaris 2.4, changes by the child to the signal handler + also munge signal handlers in the parent. To detect this, + start by putting the parent's handler in a known state. */ + signal (SIGTERM, SIG_DFL); + + child = vfork (); + + if (child == 0) { + /* Here is another test for sparc vfork register problems. This + test uses lots of local variables, at least as many local + variables as main has allocated so far including compiler + temporaries. 4 locals are enough for gcc 1.40.3 on a Solaris + 4.1.3 sparc, but we use 8 to be safe. A buggy compiler should + reuse the register of parent for one of the local variables, + since it will think that parent can't possibly be used any more + in this routine. Assigning to the local variable will thus + munge parent in the parent process. */ + pid_t + p = getpid(), p1 = getpid(), p2 = getpid(), p3 = getpid(), + p4 = getpid(), p5 = getpid(), p6 = getpid(), p7 = getpid(); + /* Convince the compiler that p..p7 are live; otherwise, it might + use the same hardware register for all 8 local variables. */ + if (p != p1 || p != p2 || p != p3 || p != p4 + || p != p5 || p != p6 || p != p7) + _exit(1); + + /* Alter the child's signal handler. */ + if (signal (SIGTERM, do_nothing) != SIG_DFL) + _exit(1); + + /* On some systems (e.g. IRIX 3.3), vfork doesn't separate parent + from child file descriptors. If the child closes a descriptor + before it execs or exits, this munges the parent's descriptor + as well. Test for this by closing stdout in the child. */ + _exit(close(fileno(stdout)) != 0); + } else { + int status; + struct stat st; + + while (wait(&status) != child) + ; + return ( + /* Was there some problem with vforking? */ + child < 0 + + /* Did the child munge the parent's signal handler? */ + || signal (SIGTERM, SIG_DFL) != SIG_DFL + + /* Did the child fail? (This shouldn't happen.) */ + || status + + /* Did the vfork/compiler bug occur? */ + || parent != getpid() + + /* Did the file descriptor bug occur? */ + || fstat(fileno(stdout), &st) != 0 + ); + } } _ACEOF -if ac_fn_cxx_try_compile "$LINENO"; then : - ucsim_cv_accept_length_type=$ac_val; break +if ac_fn_cxx_try_run "$LINENO" +then : + ac_cv_func_vfork_works=yes +else $as_nop + ac_cv_func_vfork_works=no fi -rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext - done - CPPFLAGS="$ac_save_CPPFLAGS" +rm -f core *.core core.conftest.* gmon.out bb.out conftest$ac_exeext \ + conftest.$ac_objext conftest.beam conftest.$ac_ext fi -{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ucsim_cv_accept_length_type" >&5 -$as_echo "$ucsim_cv_accept_length_type" >&6; } - if test "$ucsim_cv_accept_length_type" != no; then - -cat >>confdefs.h <<_ACEOF -#define ACCEPT_SOCKLEN_T $ucsim_cv_accept_length_type -_ACEOF - - fi +fi +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: $ac_cv_func_vfork_works" >&5 +printf "%s\n" "$ac_cv_func_vfork_works" >&6; } +fi; +if test "x$ac_cv_func_fork_works" = xcross; then + ac_cv_func_vfork_works=$ac_cv_func_vfork + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: WARNING: result $ac_cv_func_vfork_works guessed because of cross compilation" >&5 +printf "%s\n" "$as_me: WARNING: result $ac_cv_func_vfork_works guessed because of cross compilation" >&2;} +fi + +if test "x$ac_cv_func_vfork_works" = xyes; then + +printf "%s\n" "#define HAVE_WORKING_VFORK 1" >>confdefs.h + +else + +printf "%s\n" "#define vfork fork" >>confdefs.h + +fi +if test "x$ac_cv_func_fork_works" = xyes; then + +printf "%s\n" "#define HAVE_WORKING_FORK 1" >>confdefs.h + +fi + +ac_fn_cxx_check_func "$LINENO" "_exit" "ac_cv_func__exit" +if test "x$ac_cv_func__exit" = xyes +then : + printf "%s\n" "#define HAVE__EXIT 1" >>confdefs.h + +fi +ac_fn_cxx_check_func "$LINENO" "dup2" "ac_cv_func_dup2" +if test "x$ac_cv_func_dup2" = xyes +then : + printf "%s\n" "#define HAVE_DUP2 1" >>confdefs.h + +fi +ac_fn_cxx_check_func "$LINENO" "dup3" "ac_cv_func_dup3" +if test "x$ac_cv_func_dup3" = xyes +then : + printf "%s\n" "#define HAVE_DUP3 1" >>confdefs.h + +fi +ac_fn_cxx_check_func "$LINENO" "pipe" "ac_cv_func_pipe" +if test "x$ac_cv_func_pipe" = xyes +then : + printf "%s\n" "#define HAVE_PIPE 1" >>confdefs.h + +fi +ac_fn_cxx_check_func "$LINENO" "pipe2" "ac_cv_func_pipe2" +if test "x$ac_cv_func_pipe2" = xyes +then : + printf "%s\n" "#define HAVE_PIPE2 1" >>confdefs.h + +fi +ac_fn_cxx_check_func "$LINENO" "waitpid" "ac_cv_func_waitpid" +if test "x$ac_cv_func_waitpid" = xyes +then : + printf "%s\n" "#define HAVE_WAITPID 1" >>confdefs.h + +fi + +ac_fn_cxx_check_func "$LINENO" "vasprintf" "ac_cv_func_vasprintf" +if test "x$ac_cv_func_vasprintf" = xyes +then : + printf "%s\n" "#define HAVE_VASPRINTF 1" >>confdefs.h + +fi + +ac_fn_cxx_check_func "$LINENO" "yylex" "ac_cv_func_yylex" +if test "x$ac_cv_func_yylex" = xyes +then : + printf "%s\n" "#define HAVE_YYLEX 1" >>confdefs.h + +fi + + +# AC_CACHE_CHECK(whether scanf knows %a, ucsim_cv_scanf_a, +# [echo "a b" >conftest.data +# AC_TRY_RUN([ +# #include +# void main(void) +# { +# FILE *f; +# char *a; +# int i; +# if ((f= fopen("conftest.data", "r")) == NULL) +# exit(1); +# i= fscanf(f, " %a[a-z] ", &a); +# fclose(f); +# if (i == 0) +# exit(2); +# if (i == 1) +# exit(0); +# exit(3); +# }], +# ucsim_cv_scanf_a="yes", +# ucsim_cv_scanf_a="no", +# ucsim_cv_scanf_a="unknown") +# ]) +# if test "$ucsim_cv_scanf_a" = "yes"; then +# AC_DEFINE(SCANF_A, 1, [XXX]) +# fi + +# AC_CACHE_CHECK(whether getcwd is GNUish, ucsim_cv_getcwd, +# [AC_TRY_RUN([ +# #include +# void main(void) +# { +# if ((getcwd(NULL, 0)) == NULL) +# exit(1); +# exit(0); +# }], +# ucsim_cv_getcwd="yes", +# ucsim_cv_getcwd="no", +# ucsim_cv_getcwd="unknown") +# ]) +# if test "$ucsim_cv_getcwd" = "yes"; then +# AC_DEFINE(GNU_GETCWD, 1, [XXX]) +# fi + +#AC_DEFUN([ucsim_ACCEPT_LENGTH_T], +# [AC_CACHE_CHECK([for type of length pointer parameter of accept], +# ucsim_cv_accept_length_type, +# [ac_save_CPPFLAGS="$CPPFLAGS" +# ucsim_cv_accept_length_type=no +# for ac_val in int size_t socklen_t; do +# CPPFLAGS="$ac_save_CPPFLAGS -DACCEPT_SOCKLEN_T=$ac_val" +# AC_TRY_COMPILE([#include +# [struct sockaddr a; $ac_val len; accept (0, &a, &len);], +# [ucsim_cv_accept_length_type=$ac_val; break]) +# done +# CPPFLAGS="$ac_save_CPPFLAGS"]) +# if test "$ucsim_cv_accept_length_type" != no; then +# AC_DEFINE_UNQUOTED(ACCEPT_SOCKLEN_T, $ucsim_cv_accept_length_type, +# [Define to be the type of length parameter of accept (without the \*').]) +# fi +# ] +#) +##' +# +#ucsim_ACCEPT_LENGTH_T # Macro definitions ################### @@ -17374,13 +7103,15 @@ ac_cv_sizeof_long_long=4 fi + # Checking whether byte ordering is bigendian # -------------------------------------------------------- - { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether byte ordering is bigendian" >&5 -$as_echo_n "checking whether byte ordering is bigendian... " >&6; } -if ${ac_cv_c_bigendian+:} false; then : - $as_echo_n "(cached) " >&6 -else + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking whether byte ordering is bigendian" >&5 +printf %s "checking whether byte ordering is bigendian... " >&6; } +if test ${ac_cv_c_bigendian+y} +then : + printf %s "(cached) " >&6 +else $as_nop ac_cv_c_bigendian=unknown # See if we're dealing with a universal compiler. cat confdefs.h - <<_ACEOF >conftest.$ac_ext @@ -17391,7 +7122,8 @@ typedef int dummy; _ACEOF -if ac_fn_cxx_try_compile "$LINENO"; then : +if ac_fn_cxx_try_compile "$LINENO" +then : # Check for potential -arch flags. It is not universal unless # there are at least two -arch flags with different values. @@ -17415,7 +7147,7 @@ fi done fi -rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +rm -f core conftest.err conftest.$ac_objext conftest.beam conftest.$ac_ext if test $ac_cv_c_bigendian = unknown; then # See if sys/param.h defines the BYTE_ORDER macro. cat confdefs.h - <<_ACEOF >conftest.$ac_ext @@ -17424,7 +7156,7 @@ #include int -main () +main (void) { #if ! (defined BYTE_ORDER && defined BIG_ENDIAN \ && defined LITTLE_ENDIAN && BYTE_ORDER && BIG_ENDIAN \ @@ -17436,7 +7168,8 @@ return 0; } _ACEOF -if ac_fn_cxx_try_compile "$LINENO"; then : +if ac_fn_cxx_try_compile "$LINENO" +then : # It does; now see whether it defined to BIG_ENDIAN or not. cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ @@ -17444,7 +7177,7 @@ #include int -main () +main (void) { #if BYTE_ORDER != BIG_ENDIAN not big endian @@ -17454,14 +7187,15 @@ return 0; } _ACEOF -if ac_fn_cxx_try_compile "$LINENO"; then : +if ac_fn_cxx_try_compile "$LINENO" +then : ac_cv_c_bigendian=yes -else +else $as_nop ac_cv_c_bigendian=no fi -rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +rm -f core conftest.err conftest.$ac_objext conftest.beam conftest.$ac_ext fi -rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +rm -f core conftest.err conftest.$ac_objext conftest.beam conftest.$ac_ext fi if test $ac_cv_c_bigendian = unknown; then # See if defines _LITTLE_ENDIAN or _BIG_ENDIAN (e.g., Solaris). @@ -17470,7 +7204,7 @@ #include int -main () +main (void) { #if ! (defined _LITTLE_ENDIAN || defined _BIG_ENDIAN) bogus endian macros @@ -17480,14 +7214,15 @@ return 0; } _ACEOF -if ac_fn_cxx_try_compile "$LINENO"; then : +if ac_fn_cxx_try_compile "$LINENO" +then : # It does; now see whether it defined to _BIG_ENDIAN or not. cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ #include int -main () +main (void) { #ifndef _BIG_ENDIAN not big endian @@ -17497,31 +7232,33 @@ return 0; } _ACEOF -if ac_fn_cxx_try_compile "$LINENO"; then : +if ac_fn_cxx_try_compile "$LINENO" +then : ac_cv_c_bigendian=yes -else +else $as_nop ac_cv_c_bigendian=no fi -rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +rm -f core conftest.err conftest.$ac_objext conftest.beam conftest.$ac_ext fi -rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +rm -f core conftest.err conftest.$ac_objext conftest.beam conftest.$ac_ext fi if test $ac_cv_c_bigendian = unknown; then # Compile a test program. - if test "$cross_compiling" = yes; then : + if test "$cross_compiling" = yes +then : # Try to guess by grepping values from an object file. cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ -short int ascii_mm[] = +unsigned short int ascii_mm[] = { 0x4249, 0x4765, 0x6E44, 0x6961, 0x6E53, 0x7953, 0 }; - short int ascii_ii[] = + unsigned short int ascii_ii[] = { 0x694C, 0x5454, 0x656C, 0x6E45, 0x6944, 0x6E61, 0 }; int use_ascii (int i) { return ascii_mm[i] + ascii_ii[i]; } - short int ebcdic_ii[] = + unsigned short int ebcdic_ii[] = { 0x89D3, 0xE3E3, 0x8593, 0x95C5, 0x89C4, 0x9581, 0 }; - short int ebcdic_mm[] = + unsigned short int ebcdic_mm[] = { 0xC2C9, 0xC785, 0x95C4, 0x8981, 0x95E2, 0xA8E2, 0 }; int use_ebcdic (int i) { return ebcdic_mm[i] + ebcdic_ii[i]; @@ -17529,14 +7266,15 @@ extern int foo; int -main () +main (void) { return use_ascii (foo) == use_ebcdic (foo); ; return 0; } _ACEOF -if ac_fn_cxx_try_compile "$LINENO"; then : +if ac_fn_cxx_try_compile "$LINENO" +then : if grep BIGenDianSyS conftest.$ac_objext >/dev/null; then ac_cv_c_bigendian=yes fi @@ -17549,13 +7287,13 @@ fi fi fi -rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext -else +rm -f core conftest.err conftest.$ac_objext conftest.beam conftest.$ac_ext +else $as_nop cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ $ac_includes_default int -main () +main (void) { /* Are we little or big endian? From Harbison&Steele. */ @@ -17571,9 +7309,10 @@ return 0; } _ACEOF -if ac_fn_cxx_try_run "$LINENO"; then : +if ac_fn_cxx_try_run "$LINENO" +then : ac_cv_c_bigendian=no -else +else $as_nop ac_cv_c_bigendian=yes fi rm -f core *.core core.conftest.* gmon.out bb.out conftest$ac_exeext \ @@ -17582,17 +7321,17 @@ fi fi -{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_c_bigendian" >&5 -$as_echo "$ac_cv_c_bigendian" >&6; } +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: $ac_cv_c_bigendian" >&5 +printf "%s\n" "$ac_cv_c_bigendian" >&6; } case $ac_cv_c_bigendian in #( yes) - $as_echo "#define WORDS_BIGENDIAN 1" >>confdefs.h + printf "%s\n" "#define WORDS_BIGENDIAN 1" >>confdefs.h ;; #( no) ;; #( universal) -$as_echo "#define AC_APPLE_UNIVERSAL_BUILD 1" >>confdefs.h +printf "%s\n" "#define AC_APPLE_UNIVERSAL_BUILD 1" >>confdefs.h ;; #( *) @@ -17605,11 +7344,12 @@ SHAREDLIB="no" if test "$ac_cv_cxx_compiler_gnu" = "yes"; then - { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether preprocessor accepts -MM or -M" >&5 -$as_echo_n "checking whether preprocessor accepts -MM or -M... " >&6; } -if ${ucsim_cv_MM+:} false; then : - $as_echo_n "(cached) " >&6 -else + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking whether preprocessor accepts -MM or -M" >&5 +printf %s "checking whether preprocessor accepts -MM or -M... " >&6; } +if test ${ucsim_cv_MM+y} +then : + printf %s "(cached) " >&6 +else $as_nop echo "#include " >_test_.c echo "" >>_test_.c $CXXCPP -v -MM _test_.c 1>&5 2>&5 @@ -17620,19 +7360,20 @@ fi rm -f _test_.* fi -{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ucsim_cv_MM" >&5 -$as_echo "$ucsim_cv_MM" >&6; } +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: $ucsim_cv_MM" >&5 +printf "%s\n" "$ucsim_cv_MM" >&6; } # This is the first time when CFLAGS are set/modified!! - arg1=`echo -ggdb | sed -e"s/^-*//" -e"s/-/_/"` + arg1=`echo -ggdb | sed -e"s/^-*//" -e"s/-/_/g"` ac_test_CXXFLAGS=${CXXFLAGS+set} sdcc_save_CXXFLAGS=$CXXFLAGS -{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether C++ accepts -ggdb" >&5 -$as_echo_n "checking whether C++ accepts -ggdb... " >&6; } -if eval \${sdcc_cv_cxx_$arg1+:} false; then : - $as_echo_n "(cached) " >&6 -else +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking whether C++ accepts -ggdb" >&5 +printf %s "checking whether C++ accepts -ggdb... " >&6; } +if eval test \${sdcc_cv_cxx_$arg1+y} +then : + printf %s "(cached) " >&6 +else $as_nop sdcc_save_cxx_werror_flag=$ac_cxx_werror_flag ac_cxx_werror_flag=yes @@ -17641,128 +7382,128 @@ /* end confdefs.h. */ int -main () +main (void) { ; return 0; } _ACEOF -if ac_fn_cxx_try_compile "$LINENO"; then : +if ac_fn_cxx_try_compile "$LINENO" +then : eval sdcc_cv_cxx_$arg1=yes -else +else $as_nop eval sdcc_cv_cxx_$arg1=no fi -rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +rm -f core conftest.err conftest.$ac_objext conftest.beam conftest.$ac_ext ac_cxx_werror_flag=$sdcc_save_cxx_werror_flag fi eval ac_res=\$sdcc_cv_cxx_$arg1 - { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5 -$as_echo "$ac_res" >&6; } + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5 +printf "%s\n" "$ac_res" >&6; } CXXFLAGS=$sdcc_save_CXXFLAGS - arg1=`echo -gstabs | sed -e"s/^-*//" -e"s/-/_/"` + if test "$sdcc_cv_cxx_ggdb" = "yes"; then + CXXFLAGS="$CXXFLAGS -ggdb" + fi + arg1=`echo -pipe | sed -e"s/^-*//" -e"s/-/_/g"` ac_test_CXXFLAGS=${CXXFLAGS+set} sdcc_save_CXXFLAGS=$CXXFLAGS -{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether C++ accepts -gstabs" >&5 -$as_echo_n "checking whether C++ accepts -gstabs... " >&6; } -if eval \${sdcc_cv_cxx_$arg1+:} false; then : - $as_echo_n "(cached) " >&6 -else +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking whether C++ accepts -pipe" >&5 +printf %s "checking whether C++ accepts -pipe... " >&6; } +if eval test \${sdcc_cv_cxx_$arg1+y} +then : + printf %s "(cached) " >&6 +else $as_nop sdcc_save_cxx_werror_flag=$ac_cxx_werror_flag ac_cxx_werror_flag=yes - CXXFLAGS="-gstabs" + CXXFLAGS="-pipe" cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ int -main () +main (void) { ; return 0; } _ACEOF -if ac_fn_cxx_try_compile "$LINENO"; then : +if ac_fn_cxx_try_compile "$LINENO" +then : eval sdcc_cv_cxx_$arg1=yes -else +else $as_nop eval sdcc_cv_cxx_$arg1=no fi -rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +rm -f core conftest.err conftest.$ac_objext conftest.beam conftest.$ac_ext ac_cxx_werror_flag=$sdcc_save_cxx_werror_flag fi eval ac_res=\$sdcc_cv_cxx_$arg1 - { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5 -$as_echo "$ac_res" >&6; } + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5 +printf "%s\n" "$ac_res" >&6; } CXXFLAGS=$sdcc_save_CXXFLAGS - if test "$ucsim_cv_cxx_gstabs" = "yes"; then - gopt="-gstabs+ -g3" - elif test "$ucsim_cv_cxx_ggdb" = "yes"; then - gopt="-ggdb -g3" - else - gopt="-g" - fi - if test "$CXXFLAGS"x = x ;then - CXXFLAGS="$gopt" - else - CXXFLAGS="$CXXFLAGS $gopt" + if test "$sdcc_cv_cxx_pipe" = "yes"; then + CXXFLAGS="$CXXFLAGS -pipe" fi - arg1=`echo -pipe | sed -e"s/^-*//" -e"s/-/_/"` + MAKEDEP="$CXX $ucsim_cv_MM" + WALL_FLAG="-Wall" + + arg1=`echo -Wno-overloaded-virtual | sed -e"s/^-*//" -e"s/-/_/g"` ac_test_CXXFLAGS=${CXXFLAGS+set} sdcc_save_CXXFLAGS=$CXXFLAGS -{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether C++ accepts -pipe" >&5 -$as_echo_n "checking whether C++ accepts -pipe... " >&6; } -if eval \${sdcc_cv_cxx_$arg1+:} false; then : - $as_echo_n "(cached) " >&6 -else +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking whether C++ accepts -Wno-overloaded-virtual" >&5 +printf %s "checking whether C++ accepts -Wno-overloaded-virtual... " >&6; } +if eval test \${sdcc_cv_cxx_$arg1+y} +then : + printf %s "(cached) " >&6 +else $as_nop sdcc_save_cxx_werror_flag=$ac_cxx_werror_flag ac_cxx_werror_flag=yes - CXXFLAGS="-pipe" + CXXFLAGS="-Wno-overloaded-virtual" cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ int -main () +main (void) { ; return 0; } _ACEOF -if ac_fn_cxx_try_compile "$LINENO"; then : +if ac_fn_cxx_try_compile "$LINENO" +then : eval sdcc_cv_cxx_$arg1=yes -else +else $as_nop eval sdcc_cv_cxx_$arg1=no fi -rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +rm -f core conftest.err conftest.$ac_objext conftest.beam conftest.$ac_ext ac_cxx_werror_flag=$sdcc_save_cxx_werror_flag fi eval ac_res=\$sdcc_cv_cxx_$arg1 - { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5 -$as_echo "$ac_res" >&6; } + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5 +printf "%s\n" "$ac_res" >&6; } CXXFLAGS=$sdcc_save_CXXFLAGS - if test "$ucsim_cv_cxx_pipe" = "yes"; then - CXXFLAGS="$CXXFLAGS -pipe" + if test "$sdcc_cv_cxx_Wno_overloaded_virtual" = "yes"; then + WALL_FLAG="$WALL_FLAG -Wno-overloaded-virtual" fi - - MAKEDEP="$CXX $ucsim_cv_MM" - WALL_FLAG="-Wall" -else - { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether we are using the SunPRO C++ compiler" >&5 -$as_echo_n "checking whether we are using the SunPRO C++ compiler... " >&6; } -if ${sdcc_cv_cxx_compiler_sunpro+:} false; then : - $as_echo_n "(cached) " >&6 else + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking whether we are using the SunPRO C++ compiler" >&5 +printf %s "checking whether we are using the SunPRO C++ compiler... " >&6; } +if test ${sdcc_cv_cxx_compiler_sunpro+y} +then : + printf %s "(cached) " >&6 +else $as_nop cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ int -main () +main (void) { #if !defined __SUNPRO_C && !defined __SUNPRO_CC choke me @@ -17772,16 +7513,17 @@ return 0; } _ACEOF -if ac_fn_cxx_try_compile "$LINENO"; then : +if ac_fn_cxx_try_compile "$LINENO" +then : sdcc_cv_cxx_compiler_sunpro=yes -else +else $as_nop sdcc_cv_cxx_compiler_sunpro=no fi -rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +rm -f core conftest.err conftest.$ac_objext conftest.beam conftest.$ac_ext fi -{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $sdcc_cv_cxx_compiler_sunpro" >&5 -$as_echo "$sdcc_cv_cxx_compiler_sunpro" >&6; } +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: $sdcc_cv_cxx_compiler_sunpro" >&5 +printf "%s\n" "$sdcc_cv_cxx_compiler_sunpro" >&6; } if test "$sdcc_cv_cxx_compiler_sunpro" = "yes"; then CXXFLAGS="-xO2 $CXXFLAGS" MAKEDEP="$CXX -xM1" @@ -17809,55 +7551,24 @@ # Checks for typedefs, structures, and compiler characteristics. # =========================================================================== -{ $as_echo "$as_me:${as_lineno-$LINENO}: checking return type of signal handlers" >&5 -$as_echo_n "checking return type of signal handlers... " >&6; } -if ${ac_cv_type_signal+:} false; then : - $as_echo_n "(cached) " >&6 -else - cat confdefs.h - <<_ACEOF >conftest.$ac_ext -/* end confdefs.h. */ -#include -#include - -int -main () -{ -return *(signal (0, 0)) (0) == 1; - ; - return 0; -} -_ACEOF -if ac_fn_cxx_try_compile "$LINENO"; then : - ac_cv_type_signal=int -else - ac_cv_type_signal=void -fi -rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext -fi -{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_type_signal" >&5 -$as_echo "$ac_cv_type_signal" >&6; } - -cat >>confdefs.h <<_ACEOF -#define RETSIGTYPE $ac_cv_type_signal -_ACEOF - - if test "$cross_compiling" = "no"; then # The cast to long int works around a bug in the HP C Compiler # version HP92453-01 B.11.11.23709.GP, which incorrectly rejects # declarations like `int a3[[(sizeof (unsigned char)) >= 0]];'. # This bug is HP SR number 8606223364. -{ $as_echo "$as_me:${as_lineno-$LINENO}: checking size of char" >&5 -$as_echo_n "checking size of char... " >&6; } -if ${ac_cv_sizeof_char+:} false; then : - $as_echo_n "(cached) " >&6 -else - if ac_fn_cxx_compute_int "$LINENO" "(long int) (sizeof (char))" "ac_cv_sizeof_char" "$ac_includes_default"; then : +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking size of char" >&5 +printf %s "checking size of char... " >&6; } +if test ${ac_cv_sizeof_char+y} +then : + printf %s "(cached) " >&6 +else $as_nop + if ac_fn_cxx_compute_int "$LINENO" "(long int) (sizeof (char))" "ac_cv_sizeof_char" "$ac_includes_default" +then : -else +else $as_nop if test "$ac_cv_type_char" = yes; then - { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 -$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} + { { printf "%s\n" "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 +printf "%s\n" "$as_me: error: in \`$ac_pwd':" >&2;} as_fn_error 77 "cannot compute sizeof (char) See \`config.log' for more details" "$LINENO" 5; } else @@ -17866,31 +7577,31 @@ fi fi -{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_sizeof_char" >&5 -$as_echo "$ac_cv_sizeof_char" >&6; } +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: $ac_cv_sizeof_char" >&5 +printf "%s\n" "$ac_cv_sizeof_char" >&6; } -cat >>confdefs.h <<_ACEOF -#define SIZEOF_CHAR $ac_cv_sizeof_char -_ACEOF +printf "%s\n" "#define SIZEOF_CHAR $ac_cv_sizeof_char" >>confdefs.h # The cast to long int works around a bug in the HP C Compiler # version HP92453-01 B.11.11.23709.GP, which incorrectly rejects # declarations like `int a3[[(sizeof (unsigned char)) >= 0]];'. # This bug is HP SR number 8606223364. -{ $as_echo "$as_me:${as_lineno-$LINENO}: checking size of short" >&5 -$as_echo_n "checking size of short... " >&6; } -if ${ac_cv_sizeof_short+:} false; then : - $as_echo_n "(cached) " >&6 -else - if ac_fn_cxx_compute_int "$LINENO" "(long int) (sizeof (short))" "ac_cv_sizeof_short" "$ac_includes_default"; then : +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking size of short" >&5 +printf %s "checking size of short... " >&6; } +if test ${ac_cv_sizeof_short+y} +then : + printf %s "(cached) " >&6 +else $as_nop + if ac_fn_cxx_compute_int "$LINENO" "(long int) (sizeof (short))" "ac_cv_sizeof_short" "$ac_includes_default" +then : -else +else $as_nop if test "$ac_cv_type_short" = yes; then - { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 -$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} + { { printf "%s\n" "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 +printf "%s\n" "$as_me: error: in \`$ac_pwd':" >&2;} as_fn_error 77 "cannot compute sizeof (short) See \`config.log' for more details" "$LINENO" 5; } else @@ -17899,31 +7610,31 @@ fi fi -{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_sizeof_short" >&5 -$as_echo "$ac_cv_sizeof_short" >&6; } +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: $ac_cv_sizeof_short" >&5 +printf "%s\n" "$ac_cv_sizeof_short" >&6; } -cat >>confdefs.h <<_ACEOF -#define SIZEOF_SHORT $ac_cv_sizeof_short -_ACEOF +printf "%s\n" "#define SIZEOF_SHORT $ac_cv_sizeof_short" >>confdefs.h # The cast to long int works around a bug in the HP C Compiler # version HP92453-01 B.11.11.23709.GP, which incorrectly rejects # declarations like `int a3[[(sizeof (unsigned char)) >= 0]];'. # This bug is HP SR number 8606223364. -{ $as_echo "$as_me:${as_lineno-$LINENO}: checking size of int" >&5 -$as_echo_n "checking size of int... " >&6; } -if ${ac_cv_sizeof_int+:} false; then : - $as_echo_n "(cached) " >&6 -else - if ac_fn_cxx_compute_int "$LINENO" "(long int) (sizeof (int))" "ac_cv_sizeof_int" "$ac_includes_default"; then : +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking size of int" >&5 +printf %s "checking size of int... " >&6; } +if test ${ac_cv_sizeof_int+y} +then : + printf %s "(cached) " >&6 +else $as_nop + if ac_fn_cxx_compute_int "$LINENO" "(long int) (sizeof (int))" "ac_cv_sizeof_int" "$ac_includes_default" +then : -else +else $as_nop if test "$ac_cv_type_int" = yes; then - { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 -$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} + { { printf "%s\n" "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 +printf "%s\n" "$as_me: error: in \`$ac_pwd':" >&2;} as_fn_error 77 "cannot compute sizeof (int) See \`config.log' for more details" "$LINENO" 5; } else @@ -17932,31 +7643,31 @@ fi fi -{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_sizeof_int" >&5 -$as_echo "$ac_cv_sizeof_int" >&6; } +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: $ac_cv_sizeof_int" >&5 +printf "%s\n" "$ac_cv_sizeof_int" >&6; } -cat >>confdefs.h <<_ACEOF -#define SIZEOF_INT $ac_cv_sizeof_int -_ACEOF +printf "%s\n" "#define SIZEOF_INT $ac_cv_sizeof_int" >>confdefs.h # The cast to long int works around a bug in the HP C Compiler # version HP92453-01 B.11.11.23709.GP, which incorrectly rejects # declarations like `int a3[[(sizeof (unsigned char)) >= 0]];'. # This bug is HP SR number 8606223364. -{ $as_echo "$as_me:${as_lineno-$LINENO}: checking size of long" >&5 -$as_echo_n "checking size of long... " >&6; } -if ${ac_cv_sizeof_long+:} false; then : - $as_echo_n "(cached) " >&6 -else - if ac_fn_cxx_compute_int "$LINENO" "(long int) (sizeof (long))" "ac_cv_sizeof_long" "$ac_includes_default"; then : +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking size of long" >&5 +printf %s "checking size of long... " >&6; } +if test ${ac_cv_sizeof_long+y} +then : + printf %s "(cached) " >&6 +else $as_nop + if ac_fn_cxx_compute_int "$LINENO" "(long int) (sizeof (long))" "ac_cv_sizeof_long" "$ac_includes_default" +then : -else +else $as_nop if test "$ac_cv_type_long" = yes; then - { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 -$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} + { { printf "%s\n" "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 +printf "%s\n" "$as_me: error: in \`$ac_pwd':" >&2;} as_fn_error 77 "cannot compute sizeof (long) See \`config.log' for more details" "$LINENO" 5; } else @@ -17965,31 +7676,31 @@ fi fi -{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_sizeof_long" >&5 -$as_echo "$ac_cv_sizeof_long" >&6; } +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: $ac_cv_sizeof_long" >&5 +printf "%s\n" "$ac_cv_sizeof_long" >&6; } -cat >>confdefs.h <<_ACEOF -#define SIZEOF_LONG $ac_cv_sizeof_long -_ACEOF +printf "%s\n" "#define SIZEOF_LONG $ac_cv_sizeof_long" >>confdefs.h # The cast to long int works around a bug in the HP C Compiler # version HP92453-01 B.11.11.23709.GP, which incorrectly rejects # declarations like `int a3[[(sizeof (unsigned char)) >= 0]];'. # This bug is HP SR number 8606223364. -{ $as_echo "$as_me:${as_lineno-$LINENO}: checking size of long long" >&5 -$as_echo_n "checking size of long long... " >&6; } -if ${ac_cv_sizeof_long_long+:} false; then : - $as_echo_n "(cached) " >&6 -else - if ac_fn_cxx_compute_int "$LINENO" "(long int) (sizeof (long long))" "ac_cv_sizeof_long_long" "$ac_includes_default"; then : +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking size of long long" >&5 +printf %s "checking size of long long... " >&6; } +if test ${ac_cv_sizeof_long_long+y} +then : + printf %s "(cached) " >&6 +else $as_nop + if ac_fn_cxx_compute_int "$LINENO" "(long int) (sizeof (long long))" "ac_cv_sizeof_long_long" "$ac_includes_default" +then : -else +else $as_nop if test "$ac_cv_type_long_long" = yes; then - { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 -$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} + { { printf "%s\n" "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 +printf "%s\n" "$as_me: error: in \`$ac_pwd':" >&2;} as_fn_error 77 "cannot compute sizeof (long long) See \`config.log' for more details" "$LINENO" 5; } else @@ -17998,14 +7709,12 @@ fi fi -{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_sizeof_long_long" >&5 -$as_echo "$ac_cv_sizeof_long_long" >&6; } +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: $ac_cv_sizeof_long_long" >&5 +printf "%s\n" "$ac_cv_sizeof_long_long" >&6; } -cat >>confdefs.h <<_ACEOF -#define SIZEOF_LONG_LONG $ac_cv_sizeof_long_long -_ACEOF +printf "%s\n" "#define SIZEOF_LONG_LONG $ac_cv_sizeof_long_long" >>confdefs.h else @@ -18018,7 +7727,6 @@ else : # FIXME fi -#echo fi type_name() @@ -18071,86 +7779,70 @@ echo "\"L\"" } -{ $as_echo "$as_me:${as_lineno-$LINENO}: checking type name for byte" >&5 -$as_echo_n "checking type name for byte... " >&6; } +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking type name for byte" >&5 +printf %s "checking type name for byte... " >&6; } TYPE_BYTE=`type_name 1` -{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $TYPE_BYTE" >&5 -$as_echo "$TYPE_BYTE" >&6; } -{ $as_echo "$as_me:${as_lineno-$LINENO}: checking specifier for byte" >&5 -$as_echo_n "checking specifier for byte... " >&6; } +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: $TYPE_BYTE" >&5 +printf "%s\n" "$TYPE_BYTE" >&6; } +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking specifier for byte" >&5 +printf %s "checking specifier for byte... " >&6; } SPEC_BYTE=`specifier_name 1` -{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $SPEC_BYTE" >&5 -$as_echo "$SPEC_BYTE" >&6; } -{ $as_echo "$as_me:${as_lineno-$LINENO}: checking type name for word" >&5 -$as_echo_n "checking type name for word... " >&6; } +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: $SPEC_BYTE" >&5 +printf "%s\n" "$SPEC_BYTE" >&6; } +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking type name for word" >&5 +printf %s "checking type name for word... " >&6; } TYPE_WORD=`type_name 2` -{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $TYPE_WORD" >&5 -$as_echo "$TYPE_WORD" >&6; } -{ $as_echo "$as_me:${as_lineno-$LINENO}: checking specifier for word" >&5 -$as_echo_n "checking specifier for word... " >&6; } +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: $TYPE_WORD" >&5 +printf "%s\n" "$TYPE_WORD" >&6; } +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking specifier for word" >&5 +printf %s "checking specifier for word... " >&6; } SPEC_WORD=`specifier_name 2` -{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $SPEC_WORD" >&5 -$as_echo "$SPEC_WORD" >&6; } -{ $as_echo "$as_me:${as_lineno-$LINENO}: checking type name for dword" >&5 -$as_echo_n "checking type name for dword... " >&6; } +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: $SPEC_WORD" >&5 +printf "%s\n" "$SPEC_WORD" >&6; } +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking type name for dword" >&5 +printf %s "checking type name for dword... " >&6; } TYPE_DWORD=`type_name 4` -{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $TYPE_DWORD" >&5 -$as_echo "$TYPE_DWORD" >&6; } -{ $as_echo "$as_me:${as_lineno-$LINENO}: checking specifier for dword" >&5 -$as_echo_n "checking specifier for dword... " >&6; } +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: $TYPE_DWORD" >&5 +printf "%s\n" "$TYPE_DWORD" >&6; } +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking specifier for dword" >&5 +printf %s "checking specifier for dword... " >&6; } SPEC_DWORD=`specifier_name 4` -{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $SPEC_DWORD" >&5 -$as_echo "$SPEC_DWORD" >&6; } -{ $as_echo "$as_me:${as_lineno-$LINENO}: checking type name for qword" >&5 -$as_echo_n "checking type name for qword... " >&6; } +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: $SPEC_DWORD" >&5 +printf "%s\n" "$SPEC_DWORD" >&6; } +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking type name for qword" >&5 +printf %s "checking type name for qword... " >&6; } TYPE_QWORD=`type_name 8` -{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $TYPE_QWORD" >&5 -$as_echo "$TYPE_QWORD" >&6; } -{ $as_echo "$as_me:${as_lineno-$LINENO}: checking specifier for qword" >&5 -$as_echo_n "checking specifier for qword... " >&6; } +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: $TYPE_QWORD" >&5 +printf "%s\n" "$TYPE_QWORD" >&6; } +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking specifier for qword" >&5 +printf %s "checking specifier for qword... " >&6; } SPEC_QWORD=`specifier_name 8` -{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $SPEC_QWORD" >&5 -$as_echo "$SPEC_QWORD" >&6; } +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: $SPEC_QWORD" >&5 +printf "%s\n" "$SPEC_QWORD" >&6; } -cat >>confdefs.h <<_ACEOF -#define TYPE_BYTE $TYPE_BYTE -_ACEOF +printf "%s\n" "#define TYPE_BYTE $TYPE_BYTE" >>confdefs.h -cat >>confdefs.h <<_ACEOF -#define SPEC_BYTE $SPEC_BYTE -_ACEOF +printf "%s\n" "#define SPEC_BYTE $SPEC_BYTE" >>confdefs.h -cat >>confdefs.h <<_ACEOF -#define TYPE_WORD $TYPE_WORD -_ACEOF +printf "%s\n" "#define TYPE_WORD $TYPE_WORD" >>confdefs.h -cat >>confdefs.h <<_ACEOF -#define SPEC_WORD $SPEC_WORD -_ACEOF +printf "%s\n" "#define SPEC_WORD $SPEC_WORD" >>confdefs.h -cat >>confdefs.h <<_ACEOF -#define TYPE_DWORD $TYPE_DWORD -_ACEOF +printf "%s\n" "#define TYPE_DWORD $TYPE_DWORD" >>confdefs.h -cat >>confdefs.h <<_ACEOF -#define SPEC_DWORD $SPEC_DWORD -_ACEOF +printf "%s\n" "#define SPEC_DWORD $SPEC_DWORD" >>confdefs.h -cat >>confdefs.h <<_ACEOF -#define TYPE_QWORD $TYPE_QWORD -_ACEOF +printf "%s\n" "#define TYPE_QWORD $TYPE_QWORD" >>confdefs.h -cat >>confdefs.h <<_ACEOF -#define SPEC_QWORD $SPEC_QWORD -_ACEOF +printf "%s\n" "#define SPEC_QWORD $SPEC_QWORD" >>confdefs.h #AC_DEFINE_UNQUOTED(TYPE_UBYTE, [unsigned $TYPE_BYTE], [XXX]) #AC_DEFINE_UNQUOTED(TYPE_UWORD, [unsigned $TYPE_WORD], [XXX]) @@ -18173,20 +7865,16 @@ fi -cat >>confdefs.h <<_ACEOF -#define _A_ "${A}" -_ACEOF +printf "%s\n" "#define _A_ \"${A}\"" >>confdefs.h -cat >>confdefs.h <<_ACEOF -#define _M_ "${M}" -_ACEOF +printf "%s\n" "#define _M_ \"${M}\"" >>confdefs.h # Generating output files # =========================================================================== -ac_config_files="$ac_config_files Makefile main.mk:main_in.mk packages.mk:packages_in.mk sim.src/Makefile cmd.src/Makefile s51.src/Makefile avr.src/Makefile z80.src/Makefile tlcs.src/Makefile hc08.src/Makefile xa.src/Makefile stm8.src/Makefile pdk.src/Makefile st7.src/Makefile gui.src/Makefile gui.src/serio.src/Makefile doc/Makefile" +ac_config_files="$ac_config_files Makefile main.mk:main_in.mk packages.mk:packages_in.mk cmd.src/Makefile motorola.src/Makefile sim.src/Makefile sim.src/test/Makefile avr.src/Makefile avr.src/test/Makefile m68hc08.src/Makefile m68hc08.src/test/Makefile m6809.src/Makefile m6809.src/test/Makefile m6800.src/Makefile m6800.src/test/Makefile m68hc11.src/Makefile m68hc11.src/test/Makefile m68hc12.src/Makefile m68hc12.src/test/Makefile mos6502.src/Makefile mos6502.src/test/Makefile rxk.src/Makefile rxk.src/test/Makefile pblaze.src/Makefile pblaze.src/test/Makefile p1516.src/Makefile p1516.src/test/Makefile pdk.src/Makefile pdk.src/test/Makefile s51.src/Makefile s51.src/test/Makefile st7.src/Makefile st7.src/test/Makefile stm8.src/Makefile stm8.src/test/Makefile tlcs.src/Makefile tlcs.src/test/Makefile xa.src/Makefile xa.src/test/Makefile z80.src/Makefile z80.src/test/Makefile gui.src/Makefile gui.src/serio.src/Makefile doc/Makefile" cat >confcache <<\_ACEOF # This file is a shell script that caches the results of configure @@ -18215,8 +7903,8 @@ case $ac_val in #( *${as_nl}*) case $ac_var in #( - *_cv_*) { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: cache variable $ac_var contains a newline" >&5 -$as_echo "$as_me: WARNING: cache variable $ac_var contains a newline" >&2;} ;; + *_cv_*) { printf "%s\n" "$as_me:${as_lineno-$LINENO}: WARNING: cache variable $ac_var contains a newline" >&5 +printf "%s\n" "$as_me: WARNING: cache variable $ac_var contains a newline" >&2;} ;; esac case $ac_var in #( _ | IFS | as_nl) ;; #( @@ -18246,15 +7934,15 @@ /^ac_cv_env_/b end t clear :clear - s/^$[^=]*$=$.*[{}].*$$/test "${\1+set}" = set || &/ + s/^$[^=]*$=$.*[{}].*$$/test ${\1+y} || &/ t end s/^$[^=]*$=$.*$$/\1=${\1=\2}/ :end' >>confcache if diff "$cache_file" confcache >/dev/null 2>&1; then :; else if test -w "$cache_file"; then if test "x$cache_file" != "x/dev/null"; then - { $as_echo "$as_me:${as_lineno-$LINENO}: updating cache $cache_file" >&5 -$as_echo "$as_me: updating cache $cache_file" >&6;} + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: updating cache $cache_file" >&5 +printf "%s\n" "$as_me: updating cache $cache_file" >&6;} if test ! -f "$cache_file" || test -h "$cache_file"; then cat confcache >"$cache_file" else @@ -18268,8 +7956,8 @@ fi fi else - { $as_echo "$as_me:${as_lineno-$LINENO}: not updating unwritable cache $cache_file" >&5 -$as_echo "$as_me: not updating unwritable cache $cache_file" >&6;} + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: not updating unwritable cache $cache_file" >&5 +printf "%s\n" "$as_me: not updating unwritable cache $cache_file" >&6;} fi fi rm -f confcache @@ -18286,7 +7974,7 @@ for ac_i in : $LIBOBJS; do test "x$ac_i" = x: && continue # 1. Remove the extension, and $U if already installed. ac_script='s/\$U\././;s/\.o$//;s/\.obj$//' - ac_i=`$as_echo "$ac_i" | sed "$ac_script"` + ac_i=`printf "%s\n" "$ac_i" | sed "$ac_script"` # 2. Prepend LIBOBJDIR. When used with automake>=1.10 LIBOBJDIR # will be set to the directory where LIBOBJS objects are built. as_fn_append ac_libobjs " \${LIBOBJDIR}$ac_i\$U.$ac_objext" @@ -18303,8 +7991,8 @@ ac_write_fail=0 ac_clean_files_save=$ac_clean_files ac_clean_files="$ac_clean_files $CONFIG_STATUS" -{ $as_echo "$as_me:${as_lineno-$LINENO}: creating $CONFIG_STATUS" >&5 -$as_echo "$as_me: creating $CONFIG_STATUS" >&6;} +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: creating $CONFIG_STATUS" >&5 +printf "%s\n" "$as_me: creating $CONFIG_STATUS" >&6;} as_write_fail=0 cat >$CONFIG_STATUS <<_ASEOF || as_write_fail=1 #! $SHELL @@ -18327,14 +8015,16 @@ # Be more Bourne compatible DUALCASE=1; export DUALCASE # for MKS sh -if test -n "${ZSH_VERSION+set}" && (emulate sh) >/dev/null 2>&1; then : +as_nop=: +if test ${ZSH_VERSION+y} && (emulate sh) >/dev/null 2>&1 +then : emulate sh NULLCMD=: # Pre-4.2 versions of Zsh do word splitting on ${1+"$@"}, which # is contrary to our usage. Disable this feature. alias -g '${1+"$@"}'='"$@"' setopt NO_GLOB_SUBST -else +else $as_nop case `(set -o) 2>/dev/null` in #( *posix*) : set -o posix ;; #( @@ -18344,46 +8034,46 @@ fi + +# Reset variables that may have inherited troublesome values from +# the environment. + +# IFS needs to be set, to space, tab, and newline, in precisely that order. +# (If _AS_PATH_WALK were called with IFS unset, it would have the +# side effect of setting IFS to empty, thus disabling word splitting.) +# Quoting is to prevent editors from complaining about space-tab. as_nl=' ' export as_nl -# Printing a long string crashes Solaris 7 /usr/bin/printf. -as_echo='\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\' -as_echo=$as_echo$as_echo$as_echo$as_echo$as_echo -as_echo=$as_echo$as_echo$as_echo$as_echo$as_echo$as_echo -# Prefer a ksh shell builtin over an external printf program on Solaris, -# but without wasting forks for bash or zsh. -if test -z "$BASH_VERSION$ZSH_VERSION" \ - && (test "X`print -r -- $as_echo`" = "X$as_echo") 2>/dev/null; then - as_echo='print -r --' - as_echo_n='print -rn --' -elif (test "X`printf %s $as_echo`" = "X$as_echo") 2>/dev/null; then - as_echo='printf %s\n' - as_echo_n='printf %s' -else - if test "X`(/usr/ucb/echo -n -n $as_echo) 2>/dev/null`" = "X-n $as_echo"; then - as_echo_body='eval /usr/ucb/echo -n "$1$as_nl"' - as_echo_n='/usr/ucb/echo -n' - else - as_echo_body='eval expr "X$1" : "X\$.*\$"' - as_echo_n_body='eval - arg=$1; - case $arg in #( - *"$as_nl"*) - expr "X$arg" : "X\$.*\$$as_nl"; - arg=`expr "X$arg" : ".*$as_nl\$.*\$"`;; - esac; - expr "X$arg" : "X\$.*\$" | tr -d "$as_nl" - ' - export as_echo_n_body - as_echo_n='sh -c $as_echo_n_body as_echo' - fi - export as_echo_body - as_echo='sh -c $as_echo_body as_echo' -fi +IFS=" "" $as_nl" + +PS1='$ ' +PS2='> ' +PS4='+ ' + +# Ensure predictable behavior from utilities with locale-dependent output. +LC_ALL=C +export LC_ALL +LANGUAGE=C +export LANGUAGE + +# We cannot yet rely on "unset" to work, but we need these variables +# to be unset--not just set to an empty or harmless value--now, to +# avoid bugs in old shells (e.g. pre-3.0 UWIN ksh). This construct +# also avoids known problems related to "unset" and subshell syntax +# in other old shells (e.g. bash 2.01 and pdksh 5.2.14). +for as_var in BASH_ENV ENV MAIL MAILPATH CDPATH +do eval test \${$as_var+y} \ + && ( (unset $as_var) || exit 1) >/dev/null 2>&1 && unset $as_var || : +done + +# Ensure that fds 0, 1, and 2 are open. +if (exec 3>&0) 2>/dev/null; then :; else exec 0&1) 2>/dev/null; then :; else exec 1>/dev/null; fi +if (exec 3>&2) ; then :; else exec 2>/dev/null; fi # The user is always right. -if test "${PATH_SEPARATOR+set}" != set; then +if ${PATH_SEPARATOR+false} :; then PATH_SEPARATOR=: (PATH='/bin;/bin'; FPATH=$PATH; sh -c :) >/dev/null 2>&1 && { (PATH='/bin:/bin'; FPATH=$PATH; sh -c :) >/dev/null 2>&1 || @@ -18392,13 +8082,6 @@ fi -# IFS -# We need space, tab and new line, in precisely that order. Quoting is -# there to prevent editors from complaining about space-tab. -# (If _AS_PATH_WALK were called with IFS unset, it would disable word -# splitting by setting IFS to empty value.) -IFS=" "" $as_nl" - # Find who we are. Look in the path if we contain no directory separator. as_myself= case $0 in #(( @@ -18407,8 +8090,12 @@ for as_dir in $PATH do IFS=$as_save_IFS - test -z "$as_dir" && as_dir=. - test -r "$as_dir/$0" && as_myself=$as_dir/$0 && break + case $as_dir in #((( + '') as_dir=./ ;; + */) ;; + *) as_dir=$as_dir/ ;; + esac + test -r "$as_dir$0" && as_myself=$as_dir$0 && break done IFS=$as_save_IFS @@ -18420,30 +8107,10 @@ as_myself=$0 fi if test ! -f "$as_myself"; then - $as_echo "$as_myself: error: cannot find myself; rerun with an absolute file name" >&2 + printf "%s\n" "$as_myself: error: cannot find myself; rerun with an absolute file name" >&2 exit 1 fi -# Unset variables that we do not need and which cause bugs (e.g. in -# pre-3.0 UWIN ksh). But do not cause bugs in bash 2.01; the "|| exit 1" -# suppresses any "Segmentation fault" message there. '((' could -# trigger a bug in pdksh 5.2.14. -for as_var in BASH_ENV ENV MAIL MAILPATH -do eval test x\${$as_var+set} = xset \ - && ( (unset $as_var) || exit 1) >/dev/null 2>&1 && unset $as_var || : -done -PS1='$ ' -PS2='> ' -PS4='+ ' - -# NLS nuisances. -LC_ALL=C -export LC_ALL -LANGUAGE=C -export LANGUAGE - -# CDPATH. -(unset CDPATH) >/dev/null 2>&1 && unset CDPATH # as_fn_error STATUS ERROR [LINENO LOG_FD] @@ -18456,13 +8123,14 @@ as_status=$1; test $as_status -eq 0 && as_status=1 if test "$4"; then as_lineno=${as_lineno-"$3"} as_lineno_stack=as_lineno_stack=$as_lineno_stack - $as_echo "$as_me:${as_lineno-$LINENO}: error: $2" >&$4 + printf "%s\n" "$as_me:${as_lineno-$LINENO}: error: $2" >&$4 fi - $as_echo "$as_me: error: $2" >&2 + printf "%s\n" "$as_me: error: $2" >&2 as_fn_exit $as_status } # as_fn_error + # as_fn_set_status STATUS # ----------------------- # Set $? to STATUS, without forking. @@ -18489,18 +8157,20 @@ { eval $1=; unset $1;} } as_unset=as_fn_unset + # as_fn_append VAR VALUE # ---------------------- # Append the text in VALUE to the end of the definition contained in VAR. Take # advantage of any shell optimizations that allow amortized linear growth over # repeated appends, instead of the typical quadratic growth present in naive # implementations. -if (eval "as_var=1; as_var+=2; test x\$as_var = x12") 2>/dev/null; then : +if (eval "as_var=1; as_var+=2; test x\$as_var = x12") 2>/dev/null +then : eval 'as_fn_append () { eval $1+=\$2 }' -else +else $as_nop as_fn_append () { eval $1=\$$1\$2 @@ -18512,12 +8182,13 @@ # Perform arithmetic evaluation on the ARGs, and store the result in the # global $as_val. Take advantage of shells that can avoid forks. The arguments # must be portable across $(()) and expr. -if (eval "test \$(( 1 + 1 )) = 2") 2>/dev/null; then : +if (eval "test \$(( 1 + 1 )) = 2") 2>/dev/null +then : eval 'as_fn_arith () { as_val=$(( $* )) }' -else +else $as_nop as_fn_arith () { as_val=`expr "$@" || test $? -eq 1` @@ -18548,7 +8219,7 @@ $as_expr X/"$0" : '.*/$[^/][^/]*$/*$' \| \ X"$0" : 'X$//$$' \| \ X"$0" : 'X$/$' \| . 2>/dev/null || -$as_echo X/"$0" | +printf "%s\n" X/"$0" | sed '/^.*\/$[^/][^/]*$\/*$/{ s//\1/ q @@ -18570,6 +8241,10 @@ as_cr_digits='0123456789' as_cr_alnum=$as_cr_Letters$as_cr_digits + +# Determine whether it's possible to make 'echo' print without a newline. +# These variables are no longer used directly by Autoconf, but are AC_SUBSTed +# for compatibility with existing Makefiles. ECHO_C= ECHO_N= ECHO_T= case `echo -n x` in #((((( -n*) @@ -18583,6 +8258,12 @@ ECHO_N='-n';; esac +# For backward compatibility with old third-party macros, we provide +# the shell variables $as_echo and $as_echo_n. New code should use +# AS_ECHO(["message"]) and AS_ECHO_N(["message"]), respectively. +as_echo='printf %s\n' +as_echo_n='printf %s' + rm -f conf$$ conf$$.exe conf$$.file if test -d conf$$.dir; then rm -f conf$$.dir/conf$$.file @@ -18624,7 +8305,7 @@ as_dirs= while :; do case $as_dir in #( - *\'*) as_qdir=`$as_echo "$as_dir" | sed "s/'/'\\\\\\\\''/g"`;; #'( + *\'*) as_qdir=`printf "%s\n" "$as_dir" | sed "s/'/'\\\\\\\\''/g"`;; #'( *) as_qdir=$as_dir;; esac as_dirs="'$as_qdir' $as_dirs" @@ -18633,7 +8314,7 @@ X"$as_dir" : 'X$//$[^/]' \| \ X"$as_dir" : 'X$//$$' \| \ X"$as_dir" : 'X$/$' \| . 2>/dev/null || -$as_echo X"$as_dir" | +printf "%s\n" X"$as_dir" | sed '/^X$.*[^/]$\/\/*[^/][^/]*\/*$/{ s//\1/ q @@ -18696,7 +8377,7 @@ # values after options handling. ac_log=" This file was extended by $as_me, which was -generated by GNU Autoconf 2.69. Invocation command line was +generated by GNU Autoconf 2.71. Invocation command line was CONFIG_FILES = $CONFIG_FILES CONFIG_HEADERS = $CONFIG_HEADERS @@ -18722,7 +8403,6 @@ # Files that config.status was made for. config_files="$ac_config_files" config_headers="$ac_config_headers" -config_commands="$ac_config_commands" _ACEOF @@ -18752,20 +8432,19 @@ Configuration headers: $config_headers -Configuration commands: -$config_commands - Report bugs to the package provider." _ACEOF +ac_cs_config=`printf "%s\n" "$ac_configure_args" | sed "$ac_safe_unquote"` +ac_cs_config_escaped=`printf "%s\n" "$ac_cs_config" | sed "s/^ //; s/'/'\\\\\\\\''/g"` cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 -ac_cs_config="`$as_echo "$ac_configure_args" | sed 's/^ //; s/[\\""\`\$]/\\\\&/g'`" +ac_cs_config='$ac_cs_config_escaped' ac_cs_version="\\ config.status -configured by $0, generated by GNU Autoconf 2.69, +configured by $0, generated by GNU Autoconf 2.71, with options \\"\$ac_cs_config\\" -Copyright (C) 2012 Free Software Foundation, Inc. +Copyright (C) 2021 Free Software Foundation, Inc. This config.status script is free software; the Free Software Foundation gives unlimited permission to copy, distribute and modify it." @@ -18804,15 +8483,15 @@ -recheck | --recheck | --rechec | --reche | --rech | --rec | --re | --r) ac_cs_recheck=: ;; --version | --versio | --versi | --vers | --ver | --ve | --v | -V ) - $as_echo "$ac_cs_version"; exit ;; + printf "%s\n" "$ac_cs_version"; exit ;; --config | --confi | --conf | --con | --co | --c ) - $as_echo "$ac_cs_config"; exit ;; + printf "%s\n" "$ac_cs_config"; exit ;; --debug | --debu | --deb | --de | --d | -d ) debug=: ;; --file | --fil | --fi | --f ) $ac_shift case $ac_optarg in - *\'*) ac_optarg=`$as_echo "$ac_optarg" | sed "s/'/'\\\\\\\\''/g"` ;; + *\'*) ac_optarg=`printf "%s\n" "$ac_optarg" | sed "s/'/'\\\\\\\\''/g"` ;; '') as_fn_error $? "missing file argument" ;; esac as_fn_append CONFIG_FILES " '$ac_optarg'" @@ -18820,7 +8499,7 @@ --header | --heade | --head | --hea ) $ac_shift case $ac_optarg in - *\'*) ac_optarg=`$as_echo "$ac_optarg" | sed "s/'/'\\\\\\\\''/g"` ;; + *\'*) ac_optarg=`printf "%s\n" "$ac_optarg" | sed "s/'/'\\\\\\\\''/g"` ;; esac as_fn_append CONFIG_HEADERS " '$ac_optarg'" ac_need_defaults=false;; @@ -18829,7 +8508,7 @@ as_fn_error $? "ambiguous option: \`$1' Try \`$0 --help' for more information.";; --help | --hel | -h ) - $as_echo "$ac_cs_usage"; exit ;; + printf "%s\n" "$ac_cs_usage"; exit ;; -q | -quiet | --quiet | --quie | --qui | --qu | --q \ | -silent | --silent | --silen | --sile | --sil | --si | --s) ac_cs_silent=: ;; @@ -18848,420 +8527,35 @@ ac_configure_extra_args= if $ac_cs_silent; then - exec 6>/dev/null - ac_configure_extra_args="$ac_configure_extra_args --silent" -fi - -_ACEOF -cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 -if \$ac_cs_recheck; then - set X $SHELL '$0' $ac_configure_args \$ac_configure_extra_args --no-create --no-recursion - shift - \$as_echo "running CONFIG_SHELL=$SHELL \$*" >&6 - CONFIG_SHELL='$SHELL' - export CONFIG_SHELL - exec "\$@" -fi - -_ACEOF -cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 -exec 5>>config.log -{ - echo - sed 'h;s/./-/g;s/^.../## /;s/...$/ ##/;p;x;p;x' <<_ASBOX -## Running $as_me. ## -_ASBOX - $as_echo "$ac_log" -} >&5 - -_ACEOF -cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 -# -# INIT-COMMANDS -# - - -# The HP-UX ksh and POSIX shell print the target directory to stdout -# if CDPATH is set. -(unset CDPATH) >/dev/null 2>&1 && unset CDPATH - -sed_quote_subst='$sed_quote_subst' -double_quote_subst='$double_quote_subst' -delay_variable_subst='$delay_variable_subst' -macro_version='`$ECHO "$macro_version" | $SED "$delay_single_quote_subst"`' -macro_revision='`$ECHO "$macro_revision" | $SED "$delay_single_quote_subst"`' -enable_shared='`$ECHO "$enable_shared" | $SED "$delay_single_quote_subst"`' -enable_static='`$ECHO "$enable_static" | $SED "$delay_single_quote_subst"`' -pic_mode='`$ECHO "$pic_mode" | $SED "$delay_single_quote_subst"`' -enable_fast_install='`$ECHO "$enable_fast_install" | $SED "$delay_single_quote_subst"`' -shared_archive_member_spec='`$ECHO "$shared_archive_member_spec" | $SED "$delay_single_quote_subst"`' -SHELL='`$ECHO "$SHELL" | $SED "$delay_single_quote_subst"`' -ECHO='`$ECHO "$ECHO" | $SED "$delay_single_quote_subst"`' -PATH_SEPARATOR='`$ECHO "$PATH_SEPARATOR" | $SED "$delay_single_quote_subst"`' -host_alias='`$ECHO "$host_alias" | $SED "$delay_single_quote_subst"`' -host='`$ECHO "$host" | $SED "$delay_single_quote_subst"`' -host_os='`$ECHO "$host_os" | $SED "$delay_single_quote_subst"`' -build_alias='`$ECHO "$build_alias" | $SED "$delay_single_quote_subst"`' -build='`$ECHO "$build" | $SED "$delay_single_quote_subst"`' -build_os='`$ECHO "$build_os" | $SED "$delay_single_quote_subst"`' -SED='`$ECHO "$SED" | $SED "$delay_single_quote_subst"`' -Xsed='`$ECHO "$Xsed" | $SED "$delay_single_quote_subst"`' -GREP='`$ECHO "$GREP" | $SED "$delay_single_quote_subst"`' -EGREP='`$ECHO "$EGREP" | $SED "$delay_single_quote_subst"`' -FGREP='`$ECHO "$FGREP" | $SED "$delay_single_quote_subst"`' -LD='`$ECHO "$LD" | $SED "$delay_single_quote_subst"`' -NM='`$ECHO "$NM" | $SED "$delay_single_quote_subst"`' -LN_S='`$ECHO "$LN_S" | $SED "$delay_single_quote_subst"`' -max_cmd_len='`$ECHO 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sc_prohibit_nested_quotes - ;; - *) - eval "lt_\$var=\\\\\\"\\\$\$var\\\\\\"" - ;; - esac -done - -# Double-quote double-evaled strings. -for var in reload_cmds \ -old_postinstall_cmds \ -old_postuninstall_cmds \ -old_archive_cmds \ -extract_expsyms_cmds \ -old_archive_from_new_cmds \ -old_archive_from_expsyms_cmds \ -archive_cmds \ -archive_expsym_cmds \ -module_cmds \ -module_expsym_cmds \ -export_symbols_cmds \ -prelink_cmds \ -postlink_cmds \ -postinstall_cmds \ -postuninstall_cmds \ -finish_cmds \ -sys_lib_search_path_spec \ -configure_time_dlsearch_path \ -configure_time_lt_sys_library_path \ -reload_cmds_CXX \ -old_archive_cmds_CXX \ -old_archive_from_new_cmds_CXX \ -old_archive_from_expsyms_cmds_CXX \ -archive_cmds_CXX \ -archive_expsym_cmds_CXX \ -module_cmds_CXX \ -module_expsym_cmds_CXX \ -export_symbols_cmds_CXX \ -prelink_cmds_CXX \ -postlink_cmds_CXX; do - case \`eval \\\\\$ECHO \\\\""\\\\\$\$var"\\\\"\` in - *[\\\\\\\`\\"\\\$]*) - eval "lt_\$var=\\\\\\"\\\`\\\$ECHO \\"\\\$\$var\\" | \\\$SED -e \\"\\\$double_quote_subst\\" -e \\"\\\$sed_quote_subst\\" -e \\"\\\$delay_variable_subst\\"\\\`\\\\\\"" ## exclude from sc_prohibit_nested_quotes - ;; - *) - eval "lt_\$var=\\\\\\"\\\$\$var\\\\\\"" - ;; - esac -done - -ac_aux_dir='$ac_aux_dir' - -# See if we are running on zsh, and set the options that allow our -# commands through without removal of \ escapes INIT. -if test -n "\${ZSH_VERSION+set}"; then - setopt NO_GLOB_SUBST -fi - - - PACKAGE='$PACKAGE' - VERSION='$VERSION' - RM='$RM' - ofile='$ofile' - - - + exec 6>/dev/null + ac_configure_extra_args="$ac_configure_extra_args --silent" +fi +_ACEOF +cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 +if \$ac_cs_recheck; then + set X $SHELL '$0' $ac_configure_args \$ac_configure_extra_args --no-create --no-recursion + shift + \printf "%s\n" "running CONFIG_SHELL=$SHELL \$*" >&6 + CONFIG_SHELL='$SHELL' + export CONFIG_SHELL + exec "\$@" +fi +_ACEOF +cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 +exec 5>>config.log +{ + echo + sed 'h;s/./-/g;s/^.../## /;s/...$/ ##/;p;x;p;x' <<_ASBOX +## Running $as_me. ## +_ASBOX + printf "%s\n" "$ac_log" +} >&5 _ACEOF +cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 +_ACEOF cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 @@ -19270,21 +8564,47 @@ do case $ac_config_target in "ddconfig.h") CONFIG_HEADERS="$CONFIG_HEADERS ddconfig.h:ddconfig_in.h" ;; - "libtool") CONFIG_COMMANDS="$CONFIG_COMMANDS libtool" ;; "Makefile") CONFIG_FILES="$CONFIG_FILES Makefile" ;; "main.mk") CONFIG_FILES="$CONFIG_FILES main.mk:main_in.mk" ;; "packages.mk") CONFIG_FILES="$CONFIG_FILES packages.mk:packages_in.mk" ;; - "sim.src/Makefile") CONFIG_FILES="$CONFIG_FILES sim.src/Makefile" ;; "cmd.src/Makefile") CONFIG_FILES="$CONFIG_FILES cmd.src/Makefile" ;; - "s51.src/Makefile") CONFIG_FILES="$CONFIG_FILES s51.src/Makefile" ;; + "motorola.src/Makefile") CONFIG_FILES="$CONFIG_FILES motorola.src/Makefile" ;; + "sim.src/Makefile") CONFIG_FILES="$CONFIG_FILES sim.src/Makefile" ;; + "sim.src/test/Makefile") CONFIG_FILES="$CONFIG_FILES sim.src/test/Makefile" ;; "avr.src/Makefile") CONFIG_FILES="$CONFIG_FILES avr.src/Makefile" ;; - "z80.src/Makefile") CONFIG_FILES="$CONFIG_FILES z80.src/Makefile" ;; - "tlcs.src/Makefile") CONFIG_FILES="$CONFIG_FILES tlcs.src/Makefile" ;; - "hc08.src/Makefile") CONFIG_FILES="$CONFIG_FILES hc08.src/Makefile" ;; - "xa.src/Makefile") CONFIG_FILES="$CONFIG_FILES xa.src/Makefile" ;; - "stm8.src/Makefile") CONFIG_FILES="$CONFIG_FILES stm8.src/Makefile" ;; + "avr.src/test/Makefile") CONFIG_FILES="$CONFIG_FILES avr.src/test/Makefile" ;; + "m68hc08.src/Makefile") CONFIG_FILES="$CONFIG_FILES m68hc08.src/Makefile" ;; + "m68hc08.src/test/Makefile") CONFIG_FILES="$CONFIG_FILES m68hc08.src/test/Makefile" ;; + "m6809.src/Makefile") CONFIG_FILES="$CONFIG_FILES m6809.src/Makefile" ;; + "m6809.src/test/Makefile") CONFIG_FILES="$CONFIG_FILES m6809.src/test/Makefile" ;; + "m6800.src/Makefile") CONFIG_FILES="$CONFIG_FILES m6800.src/Makefile" ;; + "m6800.src/test/Makefile") CONFIG_FILES="$CONFIG_FILES m6800.src/test/Makefile" ;; + "m68hc11.src/Makefile") CONFIG_FILES="$CONFIG_FILES m68hc11.src/Makefile" ;; + "m68hc11.src/test/Makefile") CONFIG_FILES="$CONFIG_FILES m68hc11.src/test/Makefile" ;; + "m68hc12.src/Makefile") CONFIG_FILES="$CONFIG_FILES m68hc12.src/Makefile" ;; + "m68hc12.src/test/Makefile") CONFIG_FILES="$CONFIG_FILES m68hc12.src/test/Makefile" ;; + "mos6502.src/Makefile") CONFIG_FILES="$CONFIG_FILES mos6502.src/Makefile" ;; + "mos6502.src/test/Makefile") CONFIG_FILES="$CONFIG_FILES mos6502.src/test/Makefile" ;; + "rxk.src/Makefile") CONFIG_FILES="$CONFIG_FILES rxk.src/Makefile" ;; + "rxk.src/test/Makefile") CONFIG_FILES="$CONFIG_FILES rxk.src/test/Makefile" ;; + "pblaze.src/Makefile") CONFIG_FILES="$CONFIG_FILES pblaze.src/Makefile" ;; + "pblaze.src/test/Makefile") CONFIG_FILES="$CONFIG_FILES pblaze.src/test/Makefile" ;; + "p1516.src/Makefile") CONFIG_FILES="$CONFIG_FILES p1516.src/Makefile" ;; + "p1516.src/test/Makefile") CONFIG_FILES="$CONFIG_FILES p1516.src/test/Makefile" ;; "pdk.src/Makefile") CONFIG_FILES="$CONFIG_FILES pdk.src/Makefile" ;; + "pdk.src/test/Makefile") CONFIG_FILES="$CONFIG_FILES pdk.src/test/Makefile" ;; + "s51.src/Makefile") CONFIG_FILES="$CONFIG_FILES s51.src/Makefile" ;; + "s51.src/test/Makefile") CONFIG_FILES="$CONFIG_FILES s51.src/test/Makefile" ;; "st7.src/Makefile") CONFIG_FILES="$CONFIG_FILES st7.src/Makefile" ;; + "st7.src/test/Makefile") CONFIG_FILES="$CONFIG_FILES st7.src/test/Makefile" ;; + "stm8.src/Makefile") CONFIG_FILES="$CONFIG_FILES stm8.src/Makefile" ;; + "stm8.src/test/Makefile") CONFIG_FILES="$CONFIG_FILES stm8.src/test/Makefile" ;; + "tlcs.src/Makefile") CONFIG_FILES="$CONFIG_FILES tlcs.src/Makefile" ;; + "tlcs.src/test/Makefile") CONFIG_FILES="$CONFIG_FILES tlcs.src/test/Makefile" ;; + "xa.src/Makefile") CONFIG_FILES="$CONFIG_FILES xa.src/Makefile" ;; + "xa.src/test/Makefile") CONFIG_FILES="$CONFIG_FILES xa.src/test/Makefile" ;; + "z80.src/Makefile") CONFIG_FILES="$CONFIG_FILES z80.src/Makefile" ;; + "z80.src/test/Makefile") CONFIG_FILES="$CONFIG_FILES z80.src/test/Makefile" ;; "gui.src/Makefile") CONFIG_FILES="$CONFIG_FILES gui.src/Makefile" ;; "gui.src/serio.src/Makefile") CONFIG_FILES="$CONFIG_FILES gui.src/serio.src/Makefile" ;; "doc/Makefile") CONFIG_FILES="$CONFIG_FILES doc/Makefile" ;; @@ -19299,9 +8619,8 @@ # We use the long form for the default assignment because of an extremely # bizarre bug on SunOS 4.1.3. if $ac_need_defaults; then - test "${CONFIG_FILES+set}" = set || CONFIG_FILES=$config_files - test "${CONFIG_HEADERS+set}" = set || CONFIG_HEADERS=$config_headers - test "${CONFIG_COMMANDS+set}" = set || CONFIG_COMMANDS=$config_commands + test ${CONFIG_FILES+y} || CONFIG_FILES=$config_files + test ${CONFIG_HEADERS+y} || CONFIG_HEADERS=$config_headers fi # Have a temporary directory for convenience. Make it in the build tree @@ -19598,7 +8917,7 @@ fi # test -n "$CONFIG_HEADERS" -eval set X " :F $CONFIG_FILES :H $CONFIG_HEADERS :C $CONFIG_COMMANDS" +eval set X " :F $CONFIG_FILES :H $CONFIG_HEADERS " shift for ac_tag do @@ -19637,7 +8956,7 @@ esac || as_fn_error 1 "cannot find input file: \`$ac_f'" "$LINENO" 5;; esac - case $ac_f in *\'*) ac_f=`$as_echo "$ac_f" | sed "s/'/'\\\\\\\\''/g"`;; esac + case $ac_f in *\'*) ac_f=`printf "%s\n" "$ac_f" | sed "s/'/'\\\\\\\\''/g"`;; esac as_fn_append ac_file_inputs " '$ac_f'" done @@ -19645,17 +8964,17 @@ # use $as_me), people would be surprised to read: # /* config.h. Generated by config.status. */ configure_input='Generated from '` - $as_echo "$*" | sed 's|^[^:]*/||;s|:[^:]*/|, |g' + printf "%s\n" "$*" | sed 's|^[^:]*/||;s|:[^:]*/|, |g' `' by configure.' if test x"$ac_file" != x-; then configure_input="$ac_file. $configure_input" - { $as_echo "$as_me:${as_lineno-$LINENO}: creating $ac_file" >&5 -$as_echo "$as_me: creating $ac_file" >&6;} + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: creating $ac_file" >&5 +printf "%s\n" "$as_me: creating $ac_file" >&6;} fi # Neutralize special characters interpreted by sed in replacement strings. case $configure_input in #( *\&* | *\|* | *\\* ) - ac_sed_conf_input=`$as_echo "$configure_input" | + ac_sed_conf_input=`printf "%s\n" "$configure_input" | sed 's/[\\\\&|]/\\\\&/g'`;; #( *) ac_sed_conf_input=$configure_input;; esac @@ -19672,7 +8991,7 @@ X"$ac_file" : 'X$//$[^/]' \| \ X"$ac_file" : 'X$//$$' \| \ X"$ac_file" : 'X$/$' \| . 2>/dev/null || -$as_echo X"$ac_file" | +printf "%s\n" X"$ac_file" | sed '/^X$.*[^/]$\/\/*[^/][^/]*\/*$/{ s//\1/ q @@ -19696,9 +9015,9 @@ case "$ac_dir" in .) ac_dir_suffix= ac_top_builddir_sub=. ac_top_build_prefix= ;; *) - ac_dir_suffix=/`$as_echo "$ac_dir" | sed 's|^\.[\\/]||'` + ac_dir_suffix=/`printf "%s\n" "$ac_dir" | sed 's|^\.[\\/]||'` # A ".." for each directory in $ac_dir_suffix. - ac_top_builddir_sub=`$as_echo "$ac_dir_suffix" | sed 's|/[^\\/]*|/..|g;s|/||'` + ac_top_builddir_sub=`printf "%s\n" "$ac_dir_suffix" | sed 's|/[^\\/]*|/..|g;s|/||'` case $ac_top_builddir_sub in "") ac_top_builddir_sub=. ac_top_build_prefix= ;; *) ac_top_build_prefix=$ac_top_builddir_sub/ ;; @@ -19755,8 +9074,8 @@ case `eval "sed -n \"\$ac_sed_dataroot\" $ac_file_inputs"` in *datarootdir*) ac_datarootdir_seen=yes;; *@datadir@*|*@docdir@*|*@infodir@*|*@localedir@*|*@mandir@*) - { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: $ac_file_inputs seems to ignore the --datarootdir setting" >&5 -$as_echo "$as_me: WARNING: $ac_file_inputs seems to ignore the --datarootdir setting" >&2;} + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: WARNING: $ac_file_inputs seems to ignore the --datarootdir setting" >&5 +printf "%s\n" "$as_me: WARNING: $ac_file_inputs seems to ignore the --datarootdir setting" >&2;} _ACEOF cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 ac_datarootdir_hack=' @@ -19799,9 +9118,9 @@ { ac_out=`sed -n '/\${datarootdir}/p' "$ac_tmp/out"`; test -n "$ac_out"; } && { ac_out=`sed -n '/^[ ]*datarootdir[ ]*:*=/p' \ "$ac_tmp/out"`; test -z "$ac_out"; } && - { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: $ac_file contains a reference to the variable \`datarootdir' + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: WARNING: $ac_file contains a reference to the variable \`datarootdir' which seems to be undefined. Please make sure it is defined" >&5 -$as_echo "$as_me: WARNING: $ac_file contains a reference to the variable \`datarootdir' +printf "%s\n" "$as_me: WARNING: $ac_file contains a reference to the variable \`datarootdir' which seems to be undefined. Please make sure it is defined" >&2;} rm -f "$ac_tmp/stdin" @@ -19817,743 +9136,28 @@ # if test x"$ac_file" != x-; then { - $as_echo "/* $configure_input */" \ + printf "%s\n" "/* $configure_input */" >&1 \ && eval '$AWK -f "$ac_tmp/defines.awk"' "$ac_file_inputs" } >"$ac_tmp/config.h" \ || as_fn_error $? "could not create $ac_file" "$LINENO" 5 if diff "$ac_file" "$ac_tmp/config.h" >/dev/null 2>&1; then - { $as_echo "$as_me:${as_lineno-$LINENO}: $ac_file is unchanged" >&5 -$as_echo "$as_me: $ac_file is unchanged" >&6;} + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: $ac_file is unchanged" >&5 +printf "%s\n" "$as_me: $ac_file is unchanged" >&6;} else rm -f "$ac_file" mv "$ac_tmp/config.h" "$ac_file" \ || as_fn_error $? "could not create $ac_file" "$LINENO" 5 fi else - $as_echo "/* $configure_input */" \ + printf "%s\n" "/* $configure_input */" >&1 \ && eval '$AWK -f "$ac_tmp/defines.awk"' "$ac_file_inputs" \ || as_fn_error $? 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library path into an executable. -hardcode_action=$hardcode_action_CXX - -# The directories searched by this compiler when creating a shared library. -compiler_lib_search_dirs=$lt_compiler_lib_search_dirs_CXX - -# Dependencies to place before and after the objects being linked to -# create a shared library. -predep_objects=$lt_predep_objects_CXX -postdep_objects=$lt_postdep_objects_CXX -predeps=$lt_predeps_CXX -postdeps=$lt_postdeps_CXX - -# The library search path used internally by the compiler when linking -# a shared library. -compiler_lib_search_path=$lt_compiler_lib_search_path_CXX - -# ### END LIBTOOL TAG CONFIG: CXX -_LT_EOF - - ;; - - esac done # for ac_tag @@ -20586,8 +9190,8 @@ $ac_cs_success || as_fn_exit 1 fi if test -n "$ac_unrecognized_opts" && test "$enable_option_checking" != no; then - { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: unrecognized options: $ac_unrecognized_opts" >&5 -$as_echo "$as_me: WARNING: unrecognized options: $ac_unrecognized_opts" >&2;} + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: WARNING: unrecognized options: $ac_unrecognized_opts" >&5 +printf "%s\n" "$as_me: WARNING: unrecognized options: $ac_unrecognized_opts" >&2;} fi @@ -20595,3 +9199,4 @@ # End of configure.ac + diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/configure.ac sdcc-4.2.0+dfsg/sim/ucsim/configure.ac --- sdcc-4.0.0+dfsg/sim/ucsim/configure.ac 2019-10-01 14:16:20.000000000 +0000 +++ sdcc-4.2.0+dfsg/sim/ucsim/configure.ac 2022-01-23 12:31:18.000000000 +0000 @@ -3,7 +3,7 @@ AC_PREREQ(2.60) AC_INIT AC_CONFIG_SRCDIR(.version) -AC_CONFIG_HEADER(ddconfig.h:ddconfig_in.h) +AC_CONFIG_HEADERS([ddconfig.h:ddconfig_in.h]) AC_PROG_AWK @@ -65,11 +65,11 @@ fi, enable_ds390_port="yes") AC_ARG_ENABLE(avr-port, -[ --enable-avr-port compile simulator for AVR], +[ --disable-avr-port do not compile simulator for AVR], if test $enable_avr_port != "no"; then enable_avr_port="yes" fi, -enable_avr_port="no") +enable_avr_port="yes") AC_ARG_ENABLE(z80-port, [ --disable-z80-port do not compile simulator for z80], if test $enable_z80_port != "no"; then @@ -101,17 +101,17 @@ fi, enable_r3ka_port="yes") AC_ARG_ENABLE(tlcs-port, -[ --disable-tlcs-port do not compile simulator for TLCS], +[ --disable-tlcs-port do not compile simulator for TLCS], if test $enable_tlcs_port != "no"; then enable_tlcs_port="yes" fi, enable_tlcs_port="yes") -AC_ARG_ENABLE(hc08-port, -[ --disable-hc08-port do not compile simulator for hc08], -if test $enable_hc08_port != "no"; then - enable_hc08_port="yes" +AC_ARG_ENABLE(m68hc08-port, +[ --disable-m68hc08-port do not compile simulator for m68hc08], +if test $enable_m68hc08_port != "no"; then + enable_m68hc08_port="yes" fi, -enable_hc08_port="yes") +enable_m68hc08_port="yes") AC_ARG_ENABLE(s08-port, [ --disable-s08-port do not compile simulator for s08], if test $enable_s08_port != "no"; then @@ -119,11 +119,11 @@ fi, enable_s08_port="yes") AC_ARG_ENABLE(xa-port, -[ --enable-xa-port compile simulator for xa], +[ --disable-xa-port do not compile simulator for xa], if test $enable_xa_port != "no"; then enable_xa_port="yes" fi, -enable_xa_port="no") +enable_xa_port="yes") AC_ARG_ENABLE(stm8-port, [ --disable-stm8-port do not compile simulator for stm8], if test $enable_stm8_port != "no"; then @@ -137,17 +137,69 @@ fi, enable_pdk_port="yes") AC_ARG_ENABLE(st7-port, -[ --enable-st7-port compile simulator for st7], +[ --disable-st7-port do not compile simulator for st7], if test $enable_st7_port != "no"; then enable_st7_port="yes" fi, -enable_st7_port="no") +enable_st7_port="yes") +AC_ARG_ENABLE(p1516-port, +[ --disable-p1516-port do not compile simulator for p1516], +if test $enable_p1516_port != "no"; then + enable_p1516_port="yes" +fi, +enable_p1516_port="yes") +AC_ARG_ENABLE(m6809-port, +[ --disable-m6809-port do not compile simulator for m6809], +if test $enable_m6809_port != "no"; then + enable_m6809_port="yes" +fi, +enable_m6809_port="yes") + +AC_ARG_ENABLE(m6800-port, +[ --disable-m6800-port do not compile simulator for m6800], +if test $enable_m6800_port != "no"; then + enable_m6800_port="yes" +fi, +enable_m6800_port="yes") + +AC_ARG_ENABLE(m68hc11-port, +[ --disable-m68hc11-port do not compile simulator for m68hc11], +if test $enable_m68hc11_port != "no"; then + enable_m68hc11_port="yes" +fi, +enable_m68hc11_port="yes") + +AC_ARG_ENABLE(m68hc12-port, +[ --enable-m68hc12-port compile simulator for m68hc12], +if test $enable_m68hc12_port != "no"; then + enable_m68hc12_port="yes" +fi, +enable_m68hc12_port="no") + +AC_ARG_ENABLE(mos6502-port, +[ --disable-mos6502-port do not compile simulator for mos6502], +if test $enable_mos6502_port != "no"; then + enable_mos6502_port="yes" +fi, +enable_mos6502_port="yes") +AC_ARG_ENABLE(rxk-port, +[ --disable-rxk-port do not compile simulator for Rabbit rXk], +if test $enable_rxk_port != "no"; then + enable_rxk_port="yes" +fi, +enable_rxk_port="yes") +AC_ARG_ENABLE(pblaze-port, +[ --disable-pblaze-port do not compile simulator for Xilinx PicoBlaze], +if test $enable_pblaze_port != "no"; then + enable_pblaze_port="yes" +fi, +enable_pblaze_port="yes") AC_ARG_ENABLE(serio, -[ --enable-serio compile serio GUI tool (needs curses)], +[ --disable-serio do not compile serio GUI tool (needs curses)], if test $enable_serio != "no"; then enable_serio="yes" fi, -enable_serio="no") +enable_serio="yes") AC_SUBST(enable_ucsim) AC_SUBST(enable_dlso) AC_SUBST(enable_mcs51_port) @@ -159,12 +211,20 @@ AC_SUBST(enable_r2k_port) AC_SUBST(enable_r3ka_port) AC_SUBST(enable_tlcs_port) -AC_SUBST(enable_hc08_port) +AC_SUBST(enable_m68hc08_port) AC_SUBST(enable_s08_port) AC_SUBST(enable_xa_port) AC_SUBST(enable_stm8_port) AC_SUBST(enable_st7_port) AC_SUBST(enable_pdk_port) +AC_SUBST(enable_p1516_port) +AC_SUBST(enable_m6809_port) +AC_SUBST(enable_m6800_port) +AC_SUBST(enable_m68hc11_port) +AC_SUBST(enable_m68hc12_port) +AC_SUBST(enable_mos6502_port) +AC_SUBST(enable_rxk_port) +AC_SUBST(enable_pblaze_port) AC_SUBST(enable_serio) AC_ARG_ENABLE(statistic, @@ -186,35 +246,39 @@ AC_CHECK_TOOL(STRIP, strip) AC_CHECK_TOOL(AR, ar) -AC_CHECK_TOOL(SREC_CAT, srec_cat) +dnl AC_CHECK_TOOL(SREC_CAT, srec_cat) -AC_LIBTOOL_DLOPEN -dnl AC_LIBTOOL_WIN32_DLL -AC_PROG_LIBTOOL +dnl AC_LIBTOOL_DLOPEN +dnl dnl AC_LIBTOOL_WIN32_DLL +dnl AC_PROG_LIBTOOL AC_SUBST(LIBTOOL_DEPS) -AC_PROG_LEX +AC_PROG_LEX(noyywrap) if test ${LEX} = "flex"; then AC_DEFINE(HAVE_FLEX, 1, [XXX]) fi AC_PROG_YACC -AC_LANG_CPLUSPLUS +AC_LANG([C++]) # Checking for header files. # =========================================================================== -if test -d /stuff/include; then - CPPFLAGS="$CPPFLAGS -I/stuff/include" -fi +#if test -d /stuff/include; then +# CPPFLAGS="$CPPFLAGS -I/stuff/include" +#fi -AC_HEADER_STDC +dnl AC_HEADER_STDC AC_CHECK_HEADERS(endian.h sys/endian.h machine/endian.h sys/isa_defs.h) AC_CHECK_HEADERS(getopt.h) AC_CHECK_HEADERS(unistd.h) AC_CHECK_HEADERS(termios.h) - +AC_CHECK_HEADERS(inttypes.h) +AC_CHECK_HEADERS(cstdint.h) +AC_CHECK_HEADERS(stdint.h) +AC_CHECK_HEADERS(sys/wait.h) + AC_CHECK_HEADER(curses.h, AC_DEFINE(HAVE_CURSES_H, 1, [XXX]) curses_h_ok=yes, @@ -303,7 +367,7 @@ AC_DEFINE(FD_NEED_WINSOCK2_H, 0, [XXX]) fi -AC_DEFINE_UNQUOTED(FD_HEADER_OK, ${ucsim_cv_header_ok}, [XXX]) +dnl AC_DEFINE_UNQUOTED(FD_HEADER_OK, ${ucsim_cv_header_ok}, [XXX]) AC_DEFINE_UNQUOTED(HEADER_FD, ${ucsim_cv_fd}, [XXX]) @@ -325,19 +389,6 @@ AC_SUBST(dl_ok) AC_SUBST(DL) -#AC_CHECK_LIB(panel,panel_above, -#panel_ok="yes" -#curses_ok="yes" -#CURSES_LIBS="-lpanel -lcurses" -#, -#panel_ok="no" -#AC_CHECK_LIB(curses,nl, -#curses_ok="yes" -#CURSES_LIBS="-lcurses" -#, -#curses_ok="no") -#, -#-lcurses) CURSES_LIBS="" if test $curses_h_ok != yes; then panel_ok="no" @@ -370,78 +421,79 @@ AC_SUBST(curses_ok) AC_SUBST(CURSES_LIBS) +AC_FUNC_FORK +AC_CHECK_FUNCS(_exit dup2 dup3 pipe pipe2 waitpid) AC_CHECK_FUNCS(vasprintf) -AC_CHECK_FUNCS(strdup) +dnl AC_CHECK_FUNCS(strdup) dnl AC_CHECK_FUNCS(getline) dnl AC_CHECK_FUNCS(getdelim) AC_CHECK_FUNCS(yylex) -AC_CACHE_CHECK(whether scanf knows %a, ucsim_cv_scanf_a, -[echo "a b" >conftest.data -AC_TRY_RUN([ -#include -void main(void) -{ - FILE *f; - char *a; - int i; - if ((f= fopen("conftest.data", "r")) == NULL) - exit(1); - i= fscanf(f, " %a[a-z] ", &a); - fclose(f); - if (i == 0) - exit(2); - if (i == 1) - exit(0); - exit(3); -}], -ucsim_cv_scanf_a="yes", -ucsim_cv_scanf_a="no", -ucsim_cv_scanf_a="unknown") -]) -if test "$ucsim_cv_scanf_a" = "yes"; then - AC_DEFINE(SCANF_A, 1, [XXX]) -fi - -AC_CACHE_CHECK(whether getcwd is GNUish, ucsim_cv_getcwd, -[AC_TRY_RUN([ -#include -void main(void) -{ - if ((getcwd(NULL, 0)) == NULL) - exit(1); - exit(0); -}], -ucsim_cv_getcwd="yes", -ucsim_cv_getcwd="no", -ucsim_cv_getcwd="unknown") -]) -if test "$ucsim_cv_getcwd" = "yes"; then - AC_DEFINE(GNU_GETCWD, 1, [XXX]) -fi - -AC_DEFUN([ucsim_ACCEPT_LENGTH_T], - [AC_CACHE_CHECK([for type of length pointer parameter of accept], - ucsim_cv_accept_length_type, - [ac_save_CPPFLAGS="$CPPFLAGS" - ucsim_cv_accept_length_type=no - for ac_val in int size_t socklen_t; do - CPPFLAGS="$ac_save_CPPFLAGS -DACCEPT_SOCKLEN_T=$ac_val" - AC_TRY_COMPILE([#include -#include ${ucsim_cv_socket}], - [struct sockaddr a; $ac_val len; accept (0, &a, &len);], - [ucsim_cv_accept_length_type=$ac_val; break]) - done - CPPFLAGS="$ac_save_CPPFLAGS"]) - if test "$ucsim_cv_accept_length_type" != no; then - AC_DEFINE_UNQUOTED(ACCEPT_SOCKLEN_T, $ucsim_cv_accept_length_type, - [Define to be the type of length parameter of accept (without the \*').]) - fi - ] -) -#' - -ucsim_ACCEPT_LENGTH_T +# AC_CACHE_CHECK(whether scanf knows %a, ucsim_cv_scanf_a, +# [echo "a b" >conftest.data +# AC_TRY_RUN([ +# #include +# void main(void) +# { +# FILE *f; +# char *a; +# int i; +# if ((f= fopen("conftest.data", "r")) == NULL) +# exit(1); +# i= fscanf(f, " %a[a-z] ", &a); +# fclose(f); +# if (i == 0) +# exit(2); +# if (i == 1) +# exit(0); +# exit(3); +# }], +# ucsim_cv_scanf_a="yes", +# ucsim_cv_scanf_a="no", +# ucsim_cv_scanf_a="unknown") +# ]) +# if test "$ucsim_cv_scanf_a" = "yes"; then +# AC_DEFINE(SCANF_A, 1, [XXX]) +# fi + +# AC_CACHE_CHECK(whether getcwd is GNUish, ucsim_cv_getcwd, +# [AC_TRY_RUN([ +# #include +# void main(void) +# { +# if ((getcwd(NULL, 0)) == NULL) +# exit(1); +# exit(0); +# }], +# ucsim_cv_getcwd="yes", +# ucsim_cv_getcwd="no", +# ucsim_cv_getcwd="unknown") +# ]) +# if test "$ucsim_cv_getcwd" = "yes"; then +# AC_DEFINE(GNU_GETCWD, 1, [XXX]) +# fi + +#AC_DEFUN([ucsim_ACCEPT_LENGTH_T], +# [AC_CACHE_CHECK([for type of length pointer parameter of accept], +# ucsim_cv_accept_length_type, +# [ac_save_CPPFLAGS="$CPPFLAGS" +# ucsim_cv_accept_length_type=no +# for ac_val in int size_t socklen_t; do +# CPPFLAGS="$ac_save_CPPFLAGS -DACCEPT_SOCKLEN_T=$ac_val" +# AC_TRY_COMPILE([#include +# [struct sockaddr a; $ac_val len; accept (0, &a, &len);], +# [ucsim_cv_accept_length_type=$ac_val; break]) +# done +# CPPFLAGS="$ac_save_CPPFLAGS"]) +# if test "$ucsim_cv_accept_length_type" != no; then +# AC_DEFINE_UNQUOTED(ACCEPT_SOCKLEN_T, $ucsim_cv_accept_length_type, +# [Define to be the type of length parameter of accept (without the \*').]) +# fi +# ] +#) +##' +# +#ucsim_ACCEPT_LENGTH_T # Macro definitions ################### @@ -465,7 +517,7 @@ # For example: sdcc_VALID_OPT(-fPIC) AC_DEFUN([sdcc_IS_VALID_OPTION], -[arg1=`echo $1 | sed -e"s/^-*//" -e"s/-/_/"` +[arg1=`echo $1 | sed -e"s/^-*//" -e"s/-/_/g"` ac_test_[]_AC_LANG_PREFIX[]FLAGS=${[]_AC_LANG_PREFIX[]FLAGS+set} sdcc_save_[]_AC_LANG_PREFIX[]FLAGS=$[]_AC_LANG_PREFIX[]FLAGS AC_CACHE_CHECK(whether _AC_LANG accepts $1, sdcc_cv_[]_AC_LANG_ABBREV[]_$arg1, @@ -494,6 +546,7 @@ ac_cv_sizeof_long_long=4 fi + # Checking whether byte ordering is bigendian # -------------------------------------------------------- AC_C_BIGENDIAN @@ -516,27 +569,22 @@ # This is the first time when CFLAGS are set/modified!! sdcc_IS_VALID_OPTION(-ggdb) - sdcc_IS_VALID_OPTION(-gstabs) - if test "$ucsim_cv_cxx_gstabs" = "yes"; then - gopt="-gstabs+ -g3" - elif test "$ucsim_cv_cxx_ggdb" = "yes"; then - gopt="-ggdb -g3" - else - gopt="-g" - fi - if test "$CXXFLAGS"x = x ;then - CXXFLAGS="$gopt" - else - CXXFLAGS="$CXXFLAGS $gopt" + if test "$sdcc_cv_cxx_ggdb" = "yes"; then + CXXFLAGS="$CXXFLAGS -ggdb" fi - +dnl sdcc_IS_VALID_OPTION(-gstabs) sdcc_IS_VALID_OPTION(-pipe) - if test "$ucsim_cv_cxx_pipe" = "yes"; then + if test "$sdcc_cv_cxx_pipe" = "yes"; then CXXFLAGS="$CXXFLAGS -pipe" fi - + MAKEDEP="$CXX $ucsim_cv_MM" WALL_FLAG="-Wall" + + sdcc_IS_VALID_OPTION(-Wno-overloaded-virtual) + if test "$sdcc_cv_cxx_Wno_overloaded_virtual" = "yes"; then + WALL_FLAG="$WALL_FLAG -Wno-overloaded-virtual" + fi else sdcc_IS_SUNPRO if test "$sdcc_cv_cxx_compiler_sunpro" = "yes"; then @@ -566,7 +614,7 @@ # Checks for typedefs, structures, and compiler characteristics. # =========================================================================== -AC_TYPE_SIGNAL +dnl AC_TYPE_SIGNAL if test "$cross_compiling" = "no"; then AC_CHECK_SIZEOF(char) AC_CHECK_SIZEOF(short) @@ -583,7 +631,6 @@ else : # FIXME fi -#echo fi type_name() @@ -675,12 +722,8 @@ AH_TOP([#ifndef DDCONFIG_HEADER #define DDCONFIG_HEADER]) -AH_BOTTOM([/* ucsim custom defines */ -#define DD_TRUE 1 -#define DD_FALSE 0 -#define NIL 0 -#endif /* DDCONFIG_HEADER */]) - +AH_BOTTOM([#endif]) + if echo $TYPE_DWORD|grep short >/dev/null; then A="h" elif echo $TYPE_DWORD|grep long >/dev/null; then @@ -700,24 +743,38 @@ # Generating output files # =========================================================================== -AC_OUTPUT(Makefile +AC_CONFIG_FILES(Makefile main.mk:main_in.mk packages.mk:packages_in.mk -sim.src/Makefile cmd.src/Makefile -s51.src/Makefile -avr.src/Makefile -z80.src/Makefile -tlcs.src/Makefile -hc08.src/Makefile -xa.src/Makefile -stm8.src/Makefile -pdk.src/Makefile -st7.src/Makefile +motorola.src/Makefile + +sim.src/Makefile sim.src/test/Makefile + +avr.src/Makefile avr.src/test/Makefile +m68hc08.src/Makefile m68hc08.src/test/Makefile +m6809.src/Makefile m6809.src/test/Makefile +m6800.src/Makefile m6800.src/test/Makefile +m68hc11.src/Makefile m68hc11.src/test/Makefile +m68hc12.src/Makefile m68hc12.src/test/Makefile +mos6502.src/Makefile mos6502.src/test/Makefile +rxk.src/Makefile rxk.src/test/Makefile +pblaze.src/Makefile pblaze.src/test/Makefile +p1516.src/Makefile p1516.src/test/Makefile +pdk.src/Makefile pdk.src/test/Makefile +s51.src/Makefile s51.src/test/Makefile +st7.src/Makefile st7.src/test/Makefile +stm8.src/Makefile stm8.src/test/Makefile +tlcs.src/Makefile tlcs.src/test/Makefile +xa.src/Makefile xa.src/test/Makefile +z80.src/Makefile z80.src/test/Makefile + gui.src/Makefile gui.src/serio.src/Makefile + doc/Makefile ) +AC_OUTPUT #gui.src/portmon.src/Makefile diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/ddconfig_in.h sdcc-4.2.0+dfsg/sim/ucsim/ddconfig_in.h --- sdcc-4.0.0+dfsg/sim/ucsim/ddconfig_in.h 2019-10-01 14:41:40.000000000 +0000 +++ sdcc-4.2.0+dfsg/sim/ucsim/ddconfig_in.h 2022-01-11 07:28:55.000000000 +0000 @@ -4,13 +4,13 @@ #define DDCONFIG_HEADER /* Define to be the type of length parameter of accept (without the \*'). */ -#undef ACCEPT_SOCKLEN_T +//#undef ACCEPT_SOCKLEN_T /* Define if building universal (internal helper macro) */ #undef AC_APPLE_UNIVERSAL_BUILD /* XXX */ -#undef FD_HEADER_OK +//#undef FD_HEADER_OK /* XXX */ #undef FD_NEED_SELECT_H @@ -25,7 +25,7 @@ #undef FD_NEED_WINSOCK2_H /* XXX */ -#undef GNU_GETCWD +//#undef GNU_GETCWD /* XXX */ #undef HAVE_CURSES_H @@ -49,6 +49,9 @@ /* Define to 1 if you have the header file. */ #undef HAVE_INTTYPES_H +/* Define to 1 if you have the header file. */ +#undef HAVE_SYS_WAIT_H + /* Define to 1 if you have the `nsl' library (-lnsl). */ #undef HAVE_LIBNSL @@ -70,11 +73,14 @@ /* Define to 1 if you have the header file. */ #undef HAVE_STDINT_H +/* Define to 1 if you have the header file. */ +#undef HAVE_CSTDINT_H + /* Define to 1 if you have the header file. */ #undef HAVE_STDLIB_H /* Define to 1 if you have the `strdup' function. */ -#undef HAVE_STRDUP +//#undef HAVE_STRDUP /* Define to 1 if you have the header file. */ #undef HAVE_STRINGS_H @@ -111,6 +117,27 @@ /* Define to 1 if you have the header file. */ #undef HAVE_UNISTD_H +/* Define to 1 if you have a working `fork' function. */ +#undef HAVE_WORKING_FORK + +/* Define to 1 if you have the `_exit' function. */ +#undef HAVE__EXIT + +/* Define to 1 if you have the `dup2' function. */ +#undef HAVE_DUP2 + +/* Define to 1 if you have the `dup3' function. */ +#undef HAVE_DUP3 + +/* Define to 1 if you have the `pipe' function. */ +#undef HAVE_PIPE + +/* Define to 1 if you have the `pipe2' function. */ +#undef HAVE_PIPE2 + +/* Define to 1 if you have the `waitpid' function. */ +#undef HAVE_WAITPID + /* Define to 1 if you have the `vasprintf' function. */ #undef HAVE_VASPRINTF @@ -151,7 +178,7 @@ #undef RETSIGTYPE /* XXX */ -#undef SCANF_A +//#undef SCANF_A /* The size of `char', as computed by sizeof. */ #undef SIZEOF_CHAR @@ -241,8 +268,4 @@ /* XXX */ #undef _M_ -/* ucsim custom defines */ -#define DD_TRUE 1 -#define DD_FALSE 0 -#define NIL 0 #endif /* DDCONFIG_HEADER */ diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/distclean.sh sdcc-4.2.0+dfsg/sim/ucsim/distclean.sh --- sdcc-4.0.0+dfsg/sim/ucsim/distclean.sh 1970-01-01 00:00:00.000000000 +0000 +++ sdcc-4.2.0+dfsg/sim/ucsim/distclean.sh 2022-01-23 12:31:18.000000000 +0000 @@ -0,0 +1,26 @@ +#!/bin/sh + +echo "Make distclean of main directory..." +make -f clean.mk distclean + +for pkg in cmd.src sim.src gui.src motorola.src \ + s51.src avr.src z80.src tlcs.src xa.src \ + stm8.src st7.src pdk.src p1516.src \ + m68hc08.src m6809.src m6800.src m68hc11.src m68hc12.src \ + mos6502.src rxk.src \ + pblaze.src \ + doc +do + echo "Make distclean of package ${pkg} directory..." + make -C $pkg -f clean.mk distclean + test -L ${pkg}/dtest && rm -f ${pkg}/dtest +done +echo "Make clean of example directory..." +make -C example clean +echo "Make clean of test directory..." +make -C test clean + +echo "Make clean of outside tests..." +for d in $(ls ../test); do + make -C ../test/$d clean +done diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/doc/analyzer.html sdcc-4.2.0+dfsg/sim/ucsim/doc/analyzer.html --- sdcc-4.0.0+dfsg/sim/ucsim/doc/analyzer.html 2019-03-22 11:23:06.000000000 +0000 +++ sdcc-4.2.0+dfsg/sim/ucsim/doc/analyzer.html 2022-01-24 11:09:43.000000000 +0000 @@ -4,29 +4,56 @@ μCsim: Code Analyzer +

Code analyser

- Code - analyser analyses the code of the simulated program and tries to - figure out which address contains valid instruction.
-
- Analyser starts - analysing of the code with address 0 which always must contain an - instruction because reset of the device sets zero into program - counter. So, analyser marks address 0 that it contains an - instruction. Then it marks the address of the next instruction and so - on. If the analyser finds a jump instruction it continues with - destination address of the jump instruction. If it finds a - call instruction, it recursively analyses destination address - as well as next instruction follows the call one.
-
- Analysator - stops if it finds an address which is already marked or if it finds a - return instruction or an indirect jump which is - impossible to follow. All these mean that it is impossible to discover - all instructions of the program. -

This problem is solved in very simple way. If the - execution reaches an unmarked address, the analyser is called to - analyse the code starting at actual address pointed by the PC.

+ +

The code analyser analyses the memory of the simulated microprocessor and + tries to figure out which address contains valid instruction.

+ +

The analyser starts from the known hardware vectors (reset, IRQs etc.) + and follows the possible execution paths through jumps, branches and + calls marking data as code and adding variables as necessary. Execution + paths that are indirect, indexed or otherwise computed are not followed + initially but will be analyzed when, or if, execution reaches them.

+ +

If code is known to exist elsewhere in memory and is not reachable + without being run explicitly (such as by the "run addr" + command) you can use "analyze addr" to ask the analyzer + to look there. This is not persistent however. Whenever data is loaded + or "analyze" run with no addr argument all the analyzer + state is reset and recreated from the known vectors so any explicit + "analyze addr" needs to be rerun if required.

+ +

Variables created by the analyzer always start with a dot. Such variables + cannot be created by the "var" command and are not listed by + "info var" (although can be using "info var .") but + otherwise work like any other variable with one exception. If you create + a new variable for the exact same memory location the analyzer's variable + will be silently removed.

+ +

0> dump .loop$21
+
+0x081f8    <.loop$21>:
+0x081f8    d6 81 da       ld     A,(0x81da <.bit0_isset$19>,X)
+0x081fb    d7 00 3d       ld     (0x003d,X),A
+0x081fe    5a             decw   X
+0x081ff    26 f7          jrne   0x81f8 <.loop$21>
+
+0> var copy_data .loop$21
+
+0> dump .loop$21
+dump [/format] memory_type [start [stop [bytes_per_line]]] | dump bit...
+                    Dump memory of specified type or bit(s)
+
+0> dump copy_data
+
+0x081f8    <copy_data>:
+0x081f8    d6 81 da       ld     A,(0x81da <.bit0_isset$19>,X)
+0x081fb    d7 00 3d       ld     (0x003d,X),A
+0x081fe    5a             decw   X
+0x081ff    26 f7          jrne   0x81f8 <copy_data>
+

diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/doc/cmd_bp.html sdcc-4.2.0+dfsg/sim/ucsim/doc/cmd_bp.html --- sdcc-4.0.0+dfsg/sim/ucsim/doc/cmd_bp.html 2019-04-02 10:46:33.000000000 +0000 +++ sdcc-4.2.0+dfsg/sim/ucsim/doc/cmd_bp.html 2021-09-19 19:38:05.000000000 +0000 @@ -1,11 +1,11 @@ - Breakpoints commands of μCsim + Breakpoints commands of μCsim - + -

Commands of μCsim to manage breakpoints

Two kind of breakpoint can be used: fetch and event breakpoint. Fetch breakpoints are classical breakpoints. They can be placed at any instruction in the code memory. Breakpoint will be hit if CPU fetches instruction code @@ -51,7 +51,7 @@ Remaining parameters are address of watched memory location and an optional hit number (1 by default). -

$ s51 remoansi.hex
+    $ ucsim_51 remoansi.hex
 ucsim 0.2.24, Copyright (C) 1997 Daniel Drotos, Talker Bt.
 ucsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
 This is free software, and you are welcome to redistribute it
@@ -78,6 +78,9 @@
 Stop at 000160: (4) Breakpoint
 F 000160
 > 
+    Breakpoint hits can be made more noticeable by printing a beep character on
+    the console. This function can be turned on by setting
+      the option beep_break (FALSE by default).

     
 
       clear [addr...]
      Delete fetch breakpoint. Parameter specifies address of breakpoint. If
@@ -104,8 +107,17 @@
      Delete breakpoint(s) by its number.
     If parameter is not used then all breakpoints are deleted. 
     
 
-      commands script
+      commands [breakpoint-nr] script
     
+    Attach a script to a breakpoint. Breakpoint number can
+        be omitted if only one breakpoint exists. Breakpoint numbers can be
+        checked by info
+        breakpoint command. Script is command or a list of commands
+      separated by ; character. It will be executed when the specified
+      breakpoint is hit. If the text of the script is printed before execution
+      is controlled by the option echo_script, which is FALSE by
+      default. See set option command
+      how to set it.
      
     
   
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/doc/cmd_dump.html sdcc-4.2.0+dfsg/sim/ucsim/doc/cmd_dump.html
--- sdcc-4.0.0+dfsg/sim/ucsim/doc/cmd_dump.html	2019-04-02 10:46:33.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/doc/cmd_dump.html	2022-01-24 11:09:43.000000000 +0000
@@ -3,28 +3,108 @@
     
     Dump commands of μCsim
   
-  
+  
     Dump commands of μCsim
     
-      dump [/format] memory_type [start [end [bytes_per_line]]] 

-        dump bit_name...
-     First form can be used get content of memory while second form can be
-    used to check value of bit or bits.
-     
-        dump [/format] memory_type [start [end [bytes_per_line]]]
-       Hexadecimal dump of a memory region. First parameter specifies
-      memory. It can be name of an address space or a chip, and can be checked
-      using info memory command
-      which lists size and name of all available memories.
+      dump [/format] memory_type [start [end [bytes_per_line]]]
+        

+        dump bit...
+    
+    The first form can be used get the contents of memory while the second form can be
+    used to check the value of one or more bits.
+    
+      
+        dump [/format] memory_name [start [end
+            [bytes_per_line]]]
+      
+      Dump a memory region.
+      The optional /format specifies how memory is to be dumped.
+      

+        /b - binary
+          Dumps raw binary data. The output MUST be redirected to a file.
+        /h - hexadecimal
+          Dumps data in a tabular hexadecimal format with an accompanying
+              table of equivalent characters to the right.
+        /i - ihex
+          Dumps data in ihex format.
+        /s - string
+          Dumps a single, null terminated string starting at start.
+      
+      If no format is given dump uses a "smart" mode. This will disassemble
+      where the  code analyzer has identified executable
+      code otherwise it is similar to
+      the hexadecimal format except that where labels (vars that name an address)
+      are found they are shown between the address and data and where HW
+      registers (vars that name an address AND specify the full bit range)
+      are found that address is shown on a line of its own and the data is
+      given as binary, character, hex, unsigned decimal and, if the high bit
+      is set, signed decimal. Note that smart mode only applies if
+      memory_name is an address space since vars can only be set for
+      cells within an address space. If memory_name is a chip the
+      output is the same as hexadecimal (/h) output.
+      
+      memory_name specifies
+      memory. It can be the name of an address space or a chip, and can be
+      checked using info memory
+      command which lists size and name of all available memories.
+      
       start and end parameters can be used to specify the
         first and last address of the dumped region. If end is omitted
-        then 64 memory location is dumped. If both start and end
-        are omitted then next 64 memory location will be dumped out. Every time
-        when dump command is used the address of last dumped memory location is
-        stored and next dump command automatically continues at next address. 
-      Last parameter can be used to specify how many memory locations should
-        be dumped out in one line. It is 8 by default. 
-      $ s51 remo.hex
+        then 64 memory locations are dumped. If both start and end
+        are omitted then the next 64 memory locations will be dumped out. Every
+        time when dump command is used the address of the last dumped memory
+        location is stored and next dump command automatically continues at
+        the next address.
+      
+      bytes_per_line can be used to specify how many memory locations
+        should be dumped out in one line. It is 8 by default.
+      
+      $ ucsim_51
+uCsim 0.6-pre34, Copyright (C) 1997 Daniel Drotos.
+uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+This is free software, and you are welcome to redistribute it
+under certain conditions; type `show c' for details.
+> dump regs
+regs[0x0]      R0         0b00001000 0x08 '.'   8
+regs[0x1]      R1         0b01110000 0x70 'p' 112
+regs[0x2]      R2         0b11010100 0xd4 '.' 212 (212)
+regs[0x3]      R3         0b10110010 0xb2 '.' 178 (178)
+regs[0x4]      R4         0b10001010 0x8a '.' 138 (138)
+regs[0x5]      R5         0b00101001 0x29 ')'  41
+regs[0x6]      R6         0b01010100 0x54 'T'  84
+regs[0x7]      R7         0b01001000 0x48 'H'  72
+> dump rom 0
+0x0000            00 00 00 00 00 00 00 00 ........
+0x0008            00 00 00 00 00 00 00 00 ........
+0x0010            00 00 00 00 00 00 00 00 ........
+0x0018            00 00 00 00 00 00 00 00 ........
+0x0020            00 00 00 00 00 00 00 00 ........
+0x0028            00 00 00 00 00 00 00 00 ........
+0x0030            00 00 00 00 00 00 00 00 ........
+0x0038            00 00 00 00 00 00 00 00 ........
+0x0040            00 00 00 00 00 00 00 00 ........
+0x0048            00 00 00 00 00 00 00 00 ........
+> var label1 rom 0x0016
+> var reg1 rom[0x0020][7:0]
+> var reg2 rom[0x0021][7:0]
+> dump rom 0
+0x0000            00 00 00 00 00 00 00 00 ........
+0x0008            00 00 00 00 00 00 00 00 ........
+0x0010            00 00 00 00 00 00       ......
+0x0016 label1     00 00 00 00 00 00 00 00 ........
+0x001e            00 00                   ..
+0x0020 reg1       0b00000000 0x00 '.'   0
+0x0021 reg2       0b00000000 0x00 '.'   0
+0x0022            00 00 00 00 00 00 00 00 ........
+0x002a            00 00 00 00 00 00 00 00 ........
+0x0032            00 00 00 00 00 00 00 00 ........
+0x003a            00 00 00 00 00 00 00 00 ........
+0x0042            00 00 00 00 00 00 00 00 ........
+0x004a            00 00 00 00 00 00       ......
+>
+
+
+      $ ucsim_51
 ucsim 0.2.38-pre2, Copyright (C) 1997 Daniel Drotos, Talker Bt.
 ucsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
 This is free software, and you are welcome to redistribute it
@@ -62,26 +142,49 @@
 0x0055 00 00 00 94 a7 01 0c a6 ........
 0x005d 00 6f ff 00 00 00 00 00 .o......
 >
-
+First parameter can be a dump format specifier if it starts with /
+      character. Following characters select format and can set some parameters
+      for it. Know fomats are:

+      
+        /h
+        Hexadecimal dump, this is the default format. See examples above.
+        /s
+        String format. Ascii characters of bytes will be printed from
+          specified address until first 0 byte. None-printable characters will
+          be escaped in C style.
+        /i
+        Intel hex format. It can be useful to save code memory content for
+          reload it later.
+        /b
+        Binary dump. It is not supported on command console. To produce
+          binary dump the output of the command must be redirected to a file.
+      
+      Some other characters can be appended to format specifier to
+      define ho many bytes are used as one data entity and the byte order:

+      
+        /l
+        Use little endian byte order.
+        /b
+        Use big endian byte order.
+        /1
+        Use 1 byte as one data.
+        /2
+        Two bytes is dumped as one data.
+        /4
+        Four bytes treated as one data.
+        /8
+        Eight bytes mean one data.
+      
+      Default data size is determined by the memory width and the byte order is
+      determined by the simulated processor.

       
 
         dump bit_name...
-       If the simulated controller supports addressable bits (such as MCS51
-      does) this command can be used to print out values of bit(s). Any
+      This command can be used to print out values of bit(s). Any
         form of bit address can be used as parameter:
-      0> dump ac p1.2 0x21
-     PSW.6 0xd0 00 0
-      P1.2 0x90 ff 1
-    0x24.1 0x24 24 0
-0> 
- Please note, that this command can not be used, if there is no address
-      space called sfr.
-      $ sz80
-uCsim 0.5.0-pre3, Copyright (C) 1997 Daniel Drotos, Talker Bt.
-uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
-This is free software, and you are welcome to redistribute it
-under certain conditions; type `show c' for details.
-0> dump 0.0
-No memory specified. Use "info memory" for available memories
+      0> dump AC P1.2 0x21
+0xd6      AC:                       0b0 0x00 '.'   0
+0x90.2                              0b-----1-- 0x01 '.'   1
+0x24.1                              0b------0- 0x00 '.'   0
 0> 
 
 
     
 
@@ -90,7 +193,7 @@
     address stop. Default value of start address is address of following
     memory cell which was dumped by previous dch command. If stop
     parameter is not given dch command lists 10 lines 8 bytes per line.
-    $ s51 remo.hex
+    $ ucsim_51 remo.hex
 ucsim 0.2.24, Copyright (C) 1997 Daniel Drotos, Talker Bt.
 ucsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
 This is free software, and you are welcome to redistribute it
@@ -120,7 +223,7 @@
     disassembled list of memory area specified by the parameters. Default value
     of start parameter is last address listed by previous dc
     command. If stop parameter is not given 20 lines are listed.
-    $ s51 remoansi.hex 
+    $ ucsim_51 remoansi.hex 
 ucsim 0.2.12, Copyright (C) 1997 Daniel Drotos, Talker Bt.
 ucsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
 This is free software, and you are welcome to redistribute it
@@ -155,7 +258,7 @@
     instructions which discovered by the code analyser.
     First two parameters specify the address where the list starts. First
     parameter is address where the command starts to search an instruction. This
-    search goes forward. When the first instruction marked by code analyser
+    search goes forward. When the first instruction marked by code analyzer
     found the simulator skips as many instructions as you specify in second
     parameter. If offset is negative the simulator goes backward and
     skips specified number of instructions. Default value of start
@@ -164,7 +267,7 @@
     list repeating parameterless dis command.
     In third parameter you can specify how many instructions you want to
       list. Default value is 20. 
-    $ s51 remoansi.hex
+    $ ucsim_51 remoansi.hex
 ucsim 0.2.12, Copyright (C) 1997 Daniel Drotos, Talker Bt.
 ucsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
 This is free software, and you are welcome to redistribute it
@@ -206,9 +309,9 @@
 > 
     If there is an F or D character at the beginning of the
     line, it means that there is a fix or dynamic fetch breakpoint at listed
-    address. Next element on the list can be an asterix (*) which means
-    that the listed address is not marked by the code analyser. dis
-    lists marked instructions only so asterix never appears in the list. Next
+    address. Next element on the list can be an asterisk (*) which means
+    that the listed address is not marked by the code analyzer. dis
+    lists marked instructions only so asterisk never appears in the list. Next
     element of the list is address displayed as six digit hexadecimal number.
     Address is followed by hexadecimal dump of instruction's code. Last element
     of the list is disassembled instruction. Every number appeared on the list
@@ -220,7 +323,7 @@
     address of following memory cell which was dumped by previous di
     command. If stop parameter is not given di command lists 10
     lines 8 bytes per line.
-    $ s51 remoansi.hex
+    $ ucsim_51 remoansi.hex
 ucsim 0.5.0-pre3, Copyright (C) 1997 Daniel Drotos, Talker Bt.
 ucsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
 This is free software, and you are welcome to redistribute it
@@ -251,7 +354,7 @@
     address of following memory cell which was dumped by previous dx
     command. If stop parameter is not given dx command lists 10
     lines 8 bytes per line.
-    $ s51 remoansi.hex
+    $ ucsim_51 remoansi.hex
 ucsim 0.5.0-pre3, Copyright (C) 1997 Daniel Drotos, Talker Bt.
 ucsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
 This is free software, and you are welcome to redistribute it
@@ -281,7 +384,7 @@
     to address stop. Default value of start address is address of
     following memory cell which was dumped by previous ds command. If stop
     parameter is not given ds command lists 10 lines 8 bytes per line.
-    $ s51 remo.hex
+    $ ucsim_51 remo.hex
 ucsim 0.5.0-pre3, Copyright (C) 1997 Daniel Drotos, Talker Bt.
 ucsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
 This is free software, and you are welcome to redistribute it
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/doc/cmd_exec.html sdcc-4.2.0+dfsg/sim/ucsim/doc/cmd_exec.html
--- sdcc-4.0.0+dfsg/sim/ucsim/doc/cmd_exec.html	2019-03-22 11:23:06.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/doc/cmd_exec.html	2021-09-19 19:38:05.000000000 +0000
@@ -1,38 +1,32 @@
 
   
-    
-    Execution commands of μCsim
+    
+    Execution commands of μCsim
   
   
-    Execution commands of μCsim
+    Execution commands of μCsim
     
       r,run,go [start [stop]]
-    
-    This command starts the execution of the simulated program.
-    Parameters are optional. First parameter specifies start address of
-      the execution. By default execution starts at address specified by
-      actual value of the PC. This can be overridden by first parameter.
-    
+     This command starts the execution of the simulated program.
+    Parameters are optional. First parameter specifies start address of the
+      execution. By default execution starts at address specified by actual
+      value of the PC. This can be overridden by first parameter. 
     If second parameter is specified it places a dynamic breakpoint at
-      specified address which stops the execution. If stop address is not
-      given the simulator stops if it reaches a breakpoint, or the CPU
-      accepts an interrupt and stopit option is TRUE, or fatal error
-      occurs or stop command is used on an other
-      console, or ENTER key is pressed on the console where the run command
-      was issued.
-    
-    If program execution is started the console is frozen it is
-      not possible to give commands on this console to the simulator while
-      execution is running. If it is needed to control the simulator during
-      program execution then more consoles can be used. See using multiple
-        consoles for more information.
-    
-    Note that first instruction is executed without effect of
-      breakpoints and simulation will be started afterwards. It means that
-      if there is a breakpoint at start address then it will not be hit. See
-      following example:
-    
-    $ ./s51
+      specified address which stops the execution. If stop address is not given
+      the simulator stops if it reaches a breakpoint, or the CPU accepts an
+      interrupt and stopit option is TRUE, or fatal error occurs or stop command is used on an other console, or ENTER key
+      is pressed on the console where the run command was issued. 
+    If program execution is started the console is frozen it is not
+      possible to give commands on this console to the simulator while execution
+      is running. If it is needed to control the simulator during program
+      execution then more consoles can be used. See using multiple
+        consoles for more information. 
+    Note that first instruction is executed without effect of breakpoints and
+      simulation will be started afterwards. It means that if there is a
+      breakpoint at start address then it will not be hit. See following
+      example: 
+    $ ./ucsim_51
 ucsim 0.2.38-pre1, Copyright (C) 1997 Daniel Drotos, Talker Bt.
 ucsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
 This is free software, and you are welcome to redistribute it
@@ -48,13 +42,11 @@
 F 0x000020
 > 
 
-    
-    
+    
 
       stop
-    
-    This command stops the simulation, it freezes the CPU and all the
+     This command stops the simulation, it freezes the CPU and all the
     peripherals.
-    $ s51 remoansi.hex
+    $ ucsim_51 remoansi.hex
 ucsim 0.2.24, Copyright (C) 1997 Daniel Drotos, Talker Bt.
 ucsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
 This is free software, and you are welcome to redistribute it
@@ -70,22 +62,18 @@
 > stop
    006ac5 24 a5    ADD   A,#a5
 > 
-
-    Simulated program is executed in background and the simulator accepts
-    commands. If it stopped by the stop command the instruction pointed by
-    PC is disassembled, see the dis command for
-    description of disassembled form.
-    
-    
+
 Simulated program is executed in background and the simulator accepts
+    commands. If it stopped by the stop command the instruction pointed by PC is
+    disassembled, see the dis command for description
+    of disassembled form.
+    
 
       s,step [steps]
-    
-    Step command. It executes one instruction without effect of
+     Step command. It executes one instruction without effect of
     breakpoints.
-    The optional parameter can be used to specify number of instructions
-      to execute. Note that breakpoints will stop the execution after the
-      first instruction.
-    
-    $ s51 remoansi.hex
+    The optional parameter can be used to specify number of instructions to
+      execute. Note that breakpoints will stop the execution after the first
+      instruction. 
+    $ ucsim_51 remoansi.hex
 ucsim 0.2.12, Copyright (C) 1997 Daniel Drotos, Talker Bt.
 ucsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
 This is free software, and you are welcome to redistribute it
@@ -97,22 +85,42 @@
 000000 00 .  PSW= 0x00 CY=0 AC=0 OV=0 P=0
    000160 c2 90    CLR   P1.0
 > 
-    After execution of actual instruction pointed by PC (or all
-    instructions specified by the optional parameter) the step
-    command dumps out the register set.
-    
-    
+     After execution of actual instruction pointed by PC (or all instructions
+      specified by the optional parameter) the step command dumps out
+      the register set.
+    Number of steps can be specified in different units. If no unit is
+      appended to step number then it will be interpreted as number of
+      instruction. Other know units are:
+    
+       s, sec
+      Simulated execution time in seconds.
+      ms, msec
+      Simulated execution time in milliseconds.
+      us, usec
+      Simulated execution time in microseconds.
+      ns, nsec
+      Simulated execution time in nanoseconds.
+      vclk
+      Number of virtual clock counts.
+      fclk, fetch
+      Number of fetches.
+      rclk, read
+      Number of memory read operations.
+      wclk, write
+      Number of memory write operations.
+    
+    

+    
 
       n,next
-    
-    Execute until next instruction is reached. This command is similar to
-    step command described above but if actual
-    instruction to execute is a subroutine call the next command
-    places a dynamic breakpoint after the call instruction and starts to
-    execute the subroutine. If the subroutine is infinite the breakpoint
-    set by next will never reached. It can be a dangerous situation
-    because the execution started by the next command can not be
-    stopped interactively. But it can be stopped by other breakpoints.
-    $ s51 remoansi.hex
+     Execute until next instruction is reached. This command is similar to step command described above but if actual
+    instruction to execute is a subroutine call the next command places
+    a dynamic breakpoint after the call instruction and starts to execute the
+    subroutine. If the subroutine is infinite the breakpoint set by next
+    will never reached. It can be a dangerous situation because the execution
+    started by the next command can not be stopped interactively. But it
+    can be stopped by other breakpoints.
+    $ ucsim_51 remoansi.hex
 ucsim 0.2.12, Copyright (C) 1997 Daniel Drotos, Talker Bt.
 ucsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
 This is free software, and you are welcome to redistribute it
@@ -138,14 +146,11 @@
 000004 00 .  PSW= 0x00 CY=0 AC=0 OV=0 P=0
    000177 0f       INC   R7
 > 
-    
-    
+    
 
       pc [address]
-    
-    Using this command without any parameter it simply dumps out
-    instruction pointed by the PC. Specify address if you want to set the
-    PC.
-    $ s51
+     Using this command without any parameter it simply dumps out
+    instruction pointed by the PC. Specify address if you want to set the PC.
+    $ ucsim_51
 S51 0.1.5, Copyright (C) 1997 Daniel Drotos, Talker Bt.
 S51 comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
 This is free software, and you are welcome to redistribute it
@@ -160,6 +165,100 @@
  * 000020 ff       MOV   R7,A
 > 
     
+    history
+    History command can be used to inspect and manipulate history of executed
+    instructions. It accepts following subcommands:
+    history 

+      history information 

+      history list 

+      history clear 
+    
+      history
+      This command (without a subcommand) prints out last 10 elements of the
+      command history in disassembled form.
+      0> hist
+ ? 0x0211 78          LD      A,B
+ ? 0x0212 de 22       SBC     A,#0x22
+ ? 0x0214 38 f7       JR      C,#-9
+ ? 0x0216 c9          RET
+ ? 0x0109 c3 04 02    JP      #0x0204
+ ? 0x0204 3e 00       LD      A,#0x00
+ ? 0x0206 cf          RST     8
+ ? 0x0008 fb          EI
+ ? 0x0009 ed 4d       RETI
+ ? 0x0207 76          HALT
+0>
+	
+      
+      history information
+      Print out information about execution history.
+      0> hist info
+len: 100
+used: 100
+insts: 100
+0>
+	
+      Len is size of the history, used shows how many slots are
+      filled, insts is number of the instructions recorded by the
+      history.
+      
+      history list [nr] 

+        history print [nr]
+      This command is the same as the history command
+      but it accepts a parameter which specifies how many records to print
+      (defaults to 10):
+      0> hist list 3
+ ? 0x0008 fb          EI
+ ? 0x0009 ed 4d       RETI
+ ? 0x0207 76          HALT
+0> hist list 30
+ ? 0x020e 79          LD      A,C
+ ? 0x020f d6 33       sub     #0x33
+ ? 0x0211 78          LD      A,B
+ ? 0x0212 de 22       SBC     A,#0x22
+ ? 0x0214 38 f7       JR      C,#-9
+ ? 0x020d 03          INC     BC
+ ? 0x020e 79          LD      A,C
+ ? 0x020f d6 33       sub     #0x33
+ ? 0x0211 78          LD      A,B
+ ? 0x0212 de 22       SBC     A,#0x22
+ ? 0x0214 38 f7       JR      C,#-9
+ ? 0x020d 03          INC     BC
+ ? 0x020e 79          LD      A,C
+ ? 0x020f d6 33       sub     #0x33
+ ? 0x0211 78          LD      A,B
+ ? 0x0212 de 22       SBC     A,#0x22
+ ? 0x0214 38 f7       JR      C,#-9
+ ? 0x020d 03          INC     BC
+ ? 0x020e 79          LD      A,C
+ ? 0x020f d6 33       sub     #0x33
+ ? 0x0211 78          LD      A,B
+ ? 0x0212 de 22       SBC     A,#0x22
+ ? 0x0214 38 f7       JR      C,#-9
+ ? 0x0216 c9          RET
+ ? 0x0109 c3 04 02    JP      #0x0204
+ ? 0x0204 3e 00       LD      A,#0x00
+ ? 0x0206 cf          RST     8
+ ? 0x0008 fb          EI
+ ? 0x0009 ed 4d       RETI
+ ? 0x0207 76          HALT
+0>
+	
+      
+      history clear
+      This command clears the history, it deletes all recorded elements.
+      0> hist list 3
+ ? 0x0008 fb          EI
+ ? 0x0009 ed 4d       RETI
+ ? 0x0207 76          HALT
+0> hist clear
+0> hist info
+len: 100
+used: 0
+insts: 0
+0>
+	
+    
     
   
 
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/doc/cmd_general.html sdcc-4.2.0+dfsg/sim/ucsim/doc/cmd_general.html
--- sdcc-4.0.0+dfsg/sim/ucsim/doc/cmd_general.html	2019-04-02 10:46:33.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/doc/cmd_general.html	2022-01-24 11:09:43.000000000 +0000
@@ -1,12 +1,19 @@
 
   
-    
-    General commands of μCsim
+    
+    General commands of ?Csim
   
-  
-    General commands of μCsim
+  
+    General commands of μCsim
+    analyze [addr]
+    Runs the analyzer to identify code.
+    If an address is given it is taken as the starting point and the results
+    added to any existing analysis. If no address is given or a file is loaded
+    into memory using the file,load command
+    any existing analysis is cleared and a new one created using all the known
+    hardware vectors as starting points.
     conf
-    Conf command can be used to display different kind of information about μCsim.
+    Conf command can be used to display different kind of information about μCsim.
     It can be followed by a subcommand:
     conf 

       conf objects 
@@ -34,9 +41,16 @@
       conf objects
       This command is for development only. 
     
+    version
+    Print out the version of the program.
+    0> ver
+0.6-pre58
+0> 
+    
+    
     ?,help [command]
     Help command. It prints out short description of the commands.
-    If a command name is given as parameter then μCsim prints out all
+    
If a command name is given as parameter then ?Csim prints out all
       command that has similar names: 
     0> ? s
 show subcommand    Generic command for showing things about the uCsim
@@ -74,14 +88,13 @@
     quit
     Quit. This command terminates actual console, it does not ask you to confirm
     your intention. Simulator always reads commands from a file so end of file
-    condition finishes too. If command console is on standard input/output,
-    pressing the CTRL-D will quit just like the quit command.
+    condition finishes too.
     Note that if -Z option was used at
       invocation then the quit command does not terminate the simulator program.
       In this case kill command can be used to terminate
       the simulator. See for more information about using
         multiple consoles. 
-    $ s51
+    $ ucsim_51
 ucsim 0.2.24, Copyright (C) 1997 Daniel Drotos, Talker Bt.
 ucsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
 This is free software, and you are welcome to redistribute it
@@ -94,7 +107,7 @@
     doesn't matter how many consoles are used and what commands are running on
     them.
     
-    exec file
+    exec "file"
     Reads commands from "file" and executes them. This command opens a new
     console (which will use same in/out file as the actual one) to execute the
     file. This means the "quit" command in the file will not exit the simulator:
@@ -102,7 +115,7 @@
 get opt
 quit
 conf
-drdani@emma:~$ s51
+drdani@emma:~$ ucsim_51
 uCsim 0.5.0-pre3, Copyright (C) 1997 Daniel Drotos, Talker Bt.
 uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
 This is free software, and you are welcome to redistribute it
@@ -135,7 +148,27 @@
 0> expr xram[256*dph+dpl]= &sp
 129
 0> 
-
+    
+    Following formats are supported:
+    
+      x hexadecimal
+      X hexadecimal prefixed with 0x
+      0 8 characted long hexadecimal prefixed with 0x
+      d signed decimal
+      o octal
+      u unsigned decimal
+      b binary
+      B logical value as one bit
+      L logical value in T/F form
+      c chacter constant in 'c' form (non-printable values are
+        escaped in c syntax)
+    
+    If more then one format character is used then all requested form will be
+    printed:
+    0> expr /bx 123
+00000000000000000000000001111011
+7b
+0>    
     
     show
     Show command can be used to display different kind of information. It must
@@ -161,7 +194,7 @@
       Errors or warnings are events which can happen in the simulated system
       during simulation. Report of that events can be turned on or off using set error command. Errors are organized in
-      parent-child relationship. Childs are listed under the parent:
+      parent-child relationship. Children are listed under the parent:
       0> sh er
 Error: non-classified [on/ON]
   Error: memory [on/ON]
@@ -201,7 +234,7 @@
         memory or ds can be used as well.
       Parameters are interpreted as SFR names or addresses and values of
         addressed locations are dumped out. 
-      $ s51 
+      $ ucsim_51 
 ucsim 0.5.0-pre3, Copyright (C) 1997 Daniel Drotos, Talker Bt.
 ucsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
 This is free software, and you are welcome to redistribute it
@@ -222,7 +255,7 @@
         option you can get actual value of these options. If you use this
       command without parameter you get list of all options known by the
       program. In this way you can figure out which options can be used.
-      $ s51 -V
+      $ ucsim_51 -V
 ucsim 0.5.0, Copyright (C) 1997 Daniel Drotos, Talker Bt.
 ucsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
 This is free software, and you are welcome to redistribute it
@@ -250,7 +283,7 @@
         default value when a new instance of a console is created: 
       $ cat /tmp/x
 get opt debug
-$ s51
+$ ucsim_51
 uCsim 0.5.0-pre3, Copyright (C) 1997 Daniel Drotos, Talker Bt.
 uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
 This is free software, and you are welcome to redistribute it
@@ -291,7 +324,7 @@
         boolean type of option interpreted as follows: if first character of the
         value is one of 1, t, T, y, Y
         then value will be TRUE otherwise it will be FALSE. 
-      $ s51 -V
+      $ ucsim_51 -V
 uCsim 0.5.0-pre3, Copyright (C) 1997 Daniel Drotos, Talker Bt.
 uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
 This is free software, and you are welcome to redistribute it
@@ -329,7 +362,7 @@
       set memory memory_type address data...
       This command can be used to modify content of any simulated memory. First
       parameter must be a class name to specify type of memory. Class names can
-      de checked by info memory
+      be checked by info memory
       command. Chips and address spaces can be used as well.
       Second parameter specifies start address of the modification. 
       Remaining parameters will be written into the memory starting at
@@ -355,7 +388,7 @@
       addressable.
       
Second parameter interpreted as 1 if it is not zero. 
       Modified memory location is dumped out. 
-      $ s51 
+      $ ucsim_51 
 ucsim 0.2.38-pre2, Copyright (C) 1997 Daniel Drotos, Talker Bt.
 ucsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
 This is free software, and you are welcome to redistribute it
@@ -410,11 +443,14 @@
     state
     State of the simulator and the simulated microcontroller:
     > state
-CPU state= OK PC= 0x004349 XTAL= 1.10592e+07
-Total time since last reset= 0.614873 sec (6800004 clks)
-Time in isr = 0.0144227 sec (159504 clks) 2.3%
+CPU state= OK PC= 0x009c6c XTAL= 1.10592e+07
+Operation since last reset= (51682412 vclks)
+Inst= 51682412 Fetch= 51682412 Read= 0 Write= 0
+Total time since last reset= 56.079 sec (620188944 clks)
+Time in isr = 0 sec (0 clks)   0%
 Time in idle= 0 sec (0 clks)   0%
-Max value of stack pointer= 0x000049, avg= 0x000026
+Max value of stack pointer= 0x000007, avg= 0x000003
+Simulation: stopped
 > 
  The "CPU state" in the first line is an internal information. PC is value
     of the program counter. First line shows XTAL frequency too.
@@ -423,13 +459,14 @@
       number of clock periods then same data is printed out about time spent in
       interrupt service routines as well as in idle mode. Last data in lines of
       ISR and IDLE time shows ratio of ISRs, Idle times and main program. 
-    Last line informs about maximum value of the stack pointer and a "not
-      very well" calculated average value of it. 
+    Last lines inform about maximum value of the stack pointer and a "not
+      very well" calculated average value of it, and if the simulation is
+      running or stopped. 
     
     reset
     Reset command. It resets the microcontroller. It has same effect as active
     signal on the RST pin.
-    $ s51 -V remoansi.hex
+    $ ucsim_51 -V remoansi.hex
 ucsim 0.2.24, Copyright (C) 1997 Daniel Drotos, Talker Bt.
 ucsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
 This is free software, and you are welcome to redistribute it
@@ -464,9 +501,9 @@
     info breakpoints 

       info registers 

       info hardware 

-      
       info memory 

-      info variables 
+      info variables 

+      info history 
     
       info breakpoints
       This subcommand prints out information about breakpoints:
@@ -510,7 +547,7 @@
       This subcommand prints out full register set of the CPU. Output of this
       command depends of type of CPU.
       Registers of MCS51 family
-      $ s51 remoansi.hex 
+      $ ucsim_51 remoansi.hex 
 ucsim 0.2.12, Copyright (C) 1997 Daniel Drotos, Talker Bt.
 ucsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
 This is free software, and you are welcome to redistribute it
@@ -543,7 +580,7 @@
         flag bits of PSW register. Last line is disassembled instruction at PC.
       
       Registers of AVR family
-      $ savr test_arith.hex
+      $ ucsim_avr test_arith.hex
 ucsim 0.2.37, Copyright (C) 1997 Daniel Drotos, Talker Bt.
 ucsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
 This is free software, and you are welcome to redistribute it
@@ -571,7 +608,7 @@
         as pointed memory values. 
       Last line is disassembled instruction at PC. 
       Registers of Z80 family
-      $ sz80
+      $ ucsim_z80
 uCsim 0.5.0-pre3, Copyright (C) 1997 Daniel Drotos, Talker Bt.
 uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
 This is free software, and you are welcome to redistribute it
@@ -585,7 +622,7 @@
 0> 
 
       Registers of XA family
-      $ sxa
+      $ ucsim_xa
 uCsim 0.5.0-pre3, Copyright (C) 1997 Daniel Drotos, Talker Bt.
 uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
 This is free software, and you are welcome to redistribute it
@@ -598,7 +635,7 @@
 0> 
 
       Registers of HC08 family
-      $ shc08
+      $ ucsim_m68hc08
 uCsim 0.5.0-pre3, Copyright (C) 1997 Daniel Drotos, Talker Bt.
 uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
 This is free software, and you are welcome to redistribute it
@@ -621,7 +658,7 @@
       Output format of this command depends on CPU family and type of the CPU
         too because requested unit can be different in different type of
         controller even in the same CPU family. 
-      $ s51 -t 51
+      $ ucsim_51 -t 51
 ucsim 0.5.0-pre3, Copyright (C) 1997 Daniel Drotos, Talker Bt.
 ucsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
 This is free software, and you are welcome to redistribute it
@@ -652,7 +689,7 @@
 Transmitter TB8=0 irq=0
 0> 
  Timer #2 differs a little bit from other timers of MCS51:
-      $ s51 -t 52
+      $ ucsim_51 -t 52
 ucsim 0.5.0-pre3, Copyright (C) 1997 Daniel Drotos, Talker Bt.
 ucsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
 This is free software, and you are welcome to redistribute it
@@ -663,42 +700,14 @@
 timer2[2] 0x0000 reload 0x0000 timer OFF irq=0 dis prio=0
 0> 
 
-
-
+      
+      
       info memory
       This command shows information about memory system:
       chips, address spaces and address decoders.
-      $ s51
+      $ ucsim_51
 uCsim 0.5.0-pre3, Copyright (C) 1997 Daniel Drotos, Talker Bt.
 uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
 This is free software, and you are welcome to redistribute it
@@ -750,8 +759,44 @@
 0> 
 
       
-      info variables
-    
+      info variables [name]
+      Print out information about variables. Variable is memory location which
+      has a name. It can be created by var
+      command and several variables are created by the simulator. Optionally the
+      name can be specified in the command to search for it in variable names.
+      0> info var a
+pa rom[0xf000] = 00000000
+  Data register of pa
+sim_real_time simif_0_cfg[0xa] = 00000000
+  Real time since reset in msec (int, RO)
+sim_reason simif_0_cfg[0x5] = 00000000
+  Reason of last stop (int, RO)
+sim_start simif_0_cfg[0x2] = 00000000
+  WR: start simulation, RD: true if running
+sim_xtal simif_0_cfg[0x6] = 00a8c000
+  Xtal frequency in Hz (int, RW)
+0> var abc
+0> i v a
+abc variables[0x00] = 00000000
+pa rom[0xf000] = 00000000
+  Data register of pa
+sim_real_time simif_0_cfg[0xa] = 00000000
+  Real time since reset in msec (int, RO)
+sim_reason simif_0_cfg[0x5] = 00000000
+  Reason of last stop (int, RO)
+sim_start simif_0_cfg[0x2] = 00000000
+  WR: start simulation, RD: true if running
+sim_xtal simif_0_cfg[0x6] = 00a8c000
+  Xtal frequency in Hz (int, RW)
+0>
+      
+      First word is the name of the variable, followed by memory and the
+      address, last word is the actual value in hexadecimal. Predefined
+      variables have a short description which is printed in next line.
+      
+      info history
+      This command is the same as history
+        information. 
     
     timer
     Handling of timers. Don't be confused! This command doesn't handle timer
@@ -766,7 +811,7 @@
       timer set 
     Each subcommand can (some must) be followed by a timer id which can be a
       number or a string. Timers are numbered from 1. You can use any number
-      greater than 0 to identify a timer. Or you can use a simbolic name, in
+      greater than 0 to identify a timer. Or you can use a symbolic name, in
       this case simulator uses the first unused number to allocate a new timer.
     
     
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/doc/cmd.html sdcc-4.2.0+dfsg/sim/ucsim/doc/cmd.html
--- sdcc-4.0.0+dfsg/sim/ucsim/doc/cmd.html	2019-05-18 12:12:53.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/doc/cmd.html	2022-01-24 11:09:43.000000000 +0000
@@ -1,17 +1,20 @@
 
   
     
-    Commands of s51
+    Commands of μCsim
   
   
-    Command reference of μCsim
+    Command reference of μCsim
      General commands and information
     
+      analyze Analyze code
       conf Configuration
         
           conf objects
         
       
+      version Print version of the
+          program
       help,? Help about commands
       quit Quit
       kill Shut down the simulator
@@ -58,18 +61,19 @@
           
           info memory
-          info variables
+          info variables
+	  info history
         
       
       timer Managing timers to
           measure execution time and profiling
         
-          timer add 
-          timer delete 
-          timer get 
-          timer start 
-          timer stop 
-          timer set 
+          timer add 
+          timer delete 
+          timer get 
+          timer start 
+          timer stop 
+          timer set 
         
       
     
@@ -82,29 +86,29 @@
       fill Fill memory region with
           data
       where,Where Search for data in
-        memory
-      hole search area in
-      memory, filled with value
+          memory
+      hole search area in memory,
+          filled with value 
       memory Manage address spaces,
           memory chips and address decoders
         
-          memory create
+          memory create
           
-            memory create chip
+            memory create chip
           
           
-            memory
-                create addressspace
-            memory
-                create addressdecoder
-            memory create banker
-            memory create bank
-            memory create bander
+            memory
+              create addressspace
+            memory
+              create addressdecoder
+            memory create banker
+            memory create bank
+            memory create bander
           
         
         
-          memory info
-          memory cell
+          memory info
+          memory cell
         
         
         
@@ -113,7 +117,7 @@
           
         
       
-      var
+      var
     
      Execution
     
@@ -122,6 +126,13 @@
       s,step Step
       n,next Next 
       pc Set/get PC
+      history Print and manage execution history
+	history
+	  history information
+	  history list
+	  history clear
+	
+      
     
      Breakpoints
     
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/doc/cmd_memory.html sdcc-4.2.0+dfsg/sim/ucsim/doc/cmd_memory.html
--- sdcc-4.0.0+dfsg/sim/ucsim/doc/cmd_memory.html	2019-05-18 12:12:53.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/doc/cmd_memory.html	2022-01-26 16:35:40.000000000 +0000
@@ -1,36 +1,30 @@
 
   
-    
-    Memory manipulation commands of μCsim
+    
+    Memory manipulation commands of μCsim
   
-  
-    Memory manipulation commands of μCsim
+  
+    Memory manipulation commands of μCsim
     Every command which changes content of ROM area such as dl
-    or set
-        memory deletes result of code
-      analyser and causes to re-analyse the code.
-    
-    
-      file,load "FILE"
-    
-    Loads file named FILE into the simulated code memory. File must
-    contain data in Intel HEX format.
+    or set memory deletes result of
+    code analyser and causes to re-analyse the code.
+    
 
+      file,load "file"
+     Loads file named file into the simulated code memory. File must contain
+    data in Intel HEX format.
     > file "../../remo.hex"
 55470 words read from ../../remo.hex
 > 
-
-    Don't forget to enclose file name in quotes to make the parameter to
-    be a string.
-    
-    
+
 Don't forget to enclose file name in quotes to make the parameter to be a
+    string.
+    
 
       download,dl
-    
-    Download command. It is same as load above but it
-    reads information from command console which is standard input by
-    default. This command stops read records when it detects an "END"
-    record which is normally the last record. This command has two
-    equivalent forms download and dl.
-    $ s51 -V
+     Download command. It is same as load above but it
+    reads information from command console which is standard input by default.
+    This command stops read records when it detects an "END" record which is
+    normally the last record. This command has two equivalent forms download
+    and dl.
+    $ ucsim_51 -V
 ucsim 0.2.24, Copyright (C) 1997 Daniel Drotos, Talker Bt.
 ucsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
 This is free software, and you are welcome to redistribute it
@@ -53,21 +47,16 @@
 :00000001FF
 197 bytes loaded
 > 
-    
-    
+    
 
       fill memory_type start end data
-    
-    Fill memory region with specified data. First parameter specifies
+     Fill memory region with specified data. First parameter specifies
     memory. Name of the memory must be used, it can be checked using info
-      memory command which
-    lists size and name of all available memories.
-    start and end parameters specify first and last
-      address of the memory region to be filled.
-    
-    data parameter specifies the data which is used to fill the
-      memory region.
-    
-    $ s51 
+      memory command which lists size and name of all available memories.
+    start and end parameters specify first and last address of
+      the memory region to be filled. 
+    data parameter specifies the data which is used to fill the memory
+      region. 
+    $ ucsim_51 
 ucsim 0.2.38-pre2, Copyright (C) 1997 Daniel Drotos, Talker Bt.
 ucsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
 This is free software, and you are welcome to redistribute it
@@ -80,25 +69,19 @@
 0x0018 00 00 00 00 00 00 00 00 ........
 0x0020 00                      .
 > 
-    
-    
+    
 
       where,Where memory_type data...
-    
-    Searching for some data in memory. First parameter specifies
-    memory. Name of the memory must be used, it can be checked using info
-      memory command which
-    lists size and name of all available memories.
-    Other parameters can be mixed list of strings (characters between "
-      and ") and numbers. Strings can contain escape sequencies. μCsim
-      merges all parameters together and will search for merged list of
-      values in specified memory.
-    
+     Searching for some data in memory. First parameter specifies memory.
+    Name of the memory must be used, it can be checked using info
+      memory command which lists size and name of all available memories.
+    Other parameters can be mixed list of strings (characters between " and
+      ") and numbers. Strings can contain escape sequences. μCsim merges all
+      parameters together and will search for merged list of values in specified
+      memory. 
     where command do case unsensitive search while Where
-      command is for case sensitive search.
-    
-    Search is done in whole memory and all matches are dumped out.
-    
-    $ s51
+      command is for case sensitive search. 
+    Search is done in whole memory and all matches are dumped out. 
+    $ ucsim_51
 ucsim 0.2.38-pre2, Copyright (C) 1997 Daniel Drotos, Talker Bt.
 ucsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
 This is free software, and you are welcome to redistribute it
@@ -115,17 +98,15 @@
 > Where xram "d ani"
 0x0019 64 20 61 6e 69          d ani
 > 
-    
-    
+    
 
       hole [memory [length [value]]]
     
-    Searching for a memory area where all locations are filled with
-    value. By default this command searches rom but any memory can be
-    specified. Areas shorter than specified length (default is 100)
-    will not be listed. Searched value is 0 (zero) by default but
-    other can be sepcified as the last patrameter.
-    
-    $ s51
+    Searching for a memory area where all locations are filled with value. By
+      default this command searches rom but any memory can be specified. Areas
+      shorter than specified length (default is 100) will not be listed.
+      Searched value is 0 (zero) by default but other can be specified as the
+      last parameter. 
+    $ ucsim_51
 uCsim 0.6-pre55, Copyright (C) 1997 Daniel Drotos.
 uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
 This is free software, and you are welcome to redistribute it
@@ -137,7 +118,7 @@
 0> hole xram 50 11
 0x0100 255
 0> fill xram 0x500 0x600 11
-0&ht; hole xram 50 11    
+0&ht; hole xram 50 11    
 0x0100 255
 0x0500 256
 0> rom[0x200]=1
@@ -146,62 +127,55 @@
 0x0000 511
 0x0201 65022
 0> 
-    
-      Data of found areas are listed in two columns. First column is
-      the start address of the area in hexadecimal and the second
-      column is area lenght (in decimal).
-    
-    
-    
+     Data of found areas are listed in two columns. First column is the start
+      address of the area in hexadecimal and the second column is area length
+      (in decimal). 
+    
 
       memory
-    
-    This set of commands can be used to manipulate memory
+     This set of commands can be used to manipulate memory
       system including chips, address
       spaces and address decoders.
-    Subcommands are:
-    
-    memory createchip
-      

-      memory createaddressspace
-      

-      memory createaddressdecoder
-      

-      memory info
-    
-    
-      
-        memory createchip|cchip id size
-            cellsize
-      
-      This command creates a chip (array of storage elements). id
+    Subcommands are: 
+    memory create

+      memory remove

+      memory info

+      memory cell
+    
+      memory create
+    
+    This set of commands can be used to create new memory objects. It
+      requires a subcommand, which can be:
+    memory create chip

+      memory create addressspace

+      memory create addressdecoder

+      memory create banker

+      memory create bank

+      memory create bander
+    
+     
+        memory create chip id size cellsize
+       This command creates a chip (array of storage elements). id
       must be a unique name which will be used to identify the chip in other
-      commands. size is number of storage elements, cellsize
-      is number of bits stored in one element.
-      
-      
-        memory
-createaddressspace|caddressspace|caddrspace|caspace|createaddrspace|createaspace
-          id startaddr size
-      
-      This command should never be used. It defines an address space, names
-      it as id sets its starting address and size. Simulator programs
-      (s51, savr, etc.) define necessary address spaces for
-      themself, so this command is not needed.
-      
-      
-        memory
-createaddressdecoder|caddrdecoder|caddressdecoder|cadecoder|createaddrdecoder|createadecoder
-          addressspace begin end chip begin
-      
-      Address decoder maps a part of the address space to a chip
-      area. addressspace parameter is name of the address space,
-      begin and end specify address range of the address space
-      to be mapped. chip parameter is name of the memory chip and
-      the second begin parameter is the (start of the) chip address
-      where the area is mapped to.
-      Address space will be split if a "middle" are is mapped:
-      
-      $ s51
+      commands. size is number of storage elements, cellsize is
+      number of bits stored in one element.
+      
 
+        memory create as|addressspace|addr|addrs|addrspace|aspace id
+            startaddr size
+       This command should never be used. It defines an address space, names
+      it as id, sets its starting address and size. Simulator programs (ucsim_51,
+      ucsim_avr, etc.) define necessary address spaces for themself, so
+      this command is not needed.
+      
 
+        memory create
+          ad|addrdec|addrdecoder|addressdec|addressdecoder|adec|adecoder addressspace
+            begin end chip begin
+       Address decoder maps a part of the address space to a chip area. addressspace
+      parameter is name of the address space, begin and end
+      specify address range of the address space to be mapped. chip
+      parameter is name of the memory chip and the second begin
+      parameter is the (start of the) chip address where the area is mapped to.
+      Address space will be split if a "middle" area is mapped: 
+      $ ucsim_51
 uCsim 0.5.0-pre3, Copyright (C) 1997 Daniel Drotos, Talker Bt.
 uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
 This is free software, and you are welcome to redistribute it
@@ -244,9 +218,8 @@
  1 xram 0x04d2 0x07d0 -> myram 0x00f activated
  2 xram 0x07d1 0xffff -> xram_chip 0x07d1 activated
 0> 
-
-      It is easy to share chip area between address spaces:
-      $ s51
+ It is easy to share chip area between address spaces:
+      $ ucsim_51
 uCsim 0.5.0-pre3, Copyright (C) 1997 Daniel Drotos, Talker Bt.
 uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
 This is free software, and you are welcome to redistribute it
@@ -275,13 +248,81 @@
 171
 0> 
 
-      
-    
-    
-      memory info
-    
-    This command is same as info
+      
 
+        memory create banker switcher_addressspace switcher_address
+            switcher_mask banked_addressspace start end
+      This command creates a "banker", which is a controllable dynamic
+      address decoder. This means that some part of an address space can be
+      mapped to different chips and the actual map is controlled by a memory
+      location.

+      This command specifies the range of the address space and the control.

+      Following parameters specify the controller:

+      
+        switcher_addressspace address space where the controller
+          memory location is.
+        switcher_address address of the controller.
+        switcher_mask mask of the bits which select a chip. This
+          parameter specifies, how many banks will be used, so how many chips
+          will be needed. 
+      
+      Following parameters specify the address space and range which is covered
+      by this address decoder:

+      
+        banked_asddressspace name of the address space which will be
+          banked.
+        start start address of the area, and
+        end and address of the area which will be banked.
+      
+      
 
+        memory create bank addressspace begin bank_nr chip begin
+       Bank.
+      
 
+        memory create bander addressspace begin end chip begin
+            bits_per_chip [distance]
+       Bander. 
+    
 
+      memory remove|rm|del
+     This set of commands can be used to remove some memory object. It
+    requires a subcommand, which can be:
+    memory remove chip 
+     
+        memory remove chip id
+       
+    
 
+      memory info
+     This command is same as info
       memory.
-    
+    
 
+      var name [memory addr]
+     This command assigns a name to a memory location. This name can be used
+    in expressions as variable. If
+    memory is not specified, next yet unnamed location will be used from a
+    special address space, called variables. This address space have 256
+    locations by default (32 bit each), but the size can be specified using -a option of the simulator program.
+    0> var abc
+0> i v abc
+abc variables[0x00] = 00000000
+0> abc=12
+12
+0> expr /b abc
+00000000000000000000000000001100
+0> 
+    
+    Memory location can be specified in two forms:
+    0> var vname rom 45
+0> i var vname
+vname rom[0x002d] = 73d4d3c4
+0> var other rom[45]
+0> i v other
+other rom[0x002d] = 73d4d3c4
+0>
+    
+    
 
+      rmvar name
+     This command removes a variable.
+    0> rmvar abc
+No such variable
+    
   
 
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/doc/cmd_removed.html sdcc-4.2.0+dfsg/sim/ucsim/doc/cmd_removed.html
--- sdcc-4.0.0+dfsg/sim/ucsim/doc/cmd_removed.html	2019-03-22 11:23:06.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/doc/cmd_removed.html	2022-01-26 16:35:40.000000000 +0000
@@ -22,7 +22,7 @@
       Forth parameter is optional and it specifies the hit number. It is
         1 by default.
       
-      $ s51 remoansi.hex
+      $ ucsim_51 remoansi.hex
 ucsim 0.2.12, Copyright (C) 1997 Daniel Drotos, Talker Bt.
 ucsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
 This is free software, and you are welcome to redistribute it
@@ -95,7 +95,7 @@
           hardware instead!!
       Dump out ports. This command shows actual value of ports.
       
-      $ s51 remoansi.hex 
+      $ ucsim_51 remoansi.hex 
 ucsim 0.2.12, Copyright (C) 1997 Daniel Drotos, Talker Bt.
 ucsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
 This is free software, and you are welcome to redistribute it
@@ -114,11 +114,11 @@
 Pin2  11111111 0xff 255 .    Pin3  11111111 0xff 255 .
 Port2 11111111 0xff 255 .    Port3 11111111 0xff 255 .
 > 
-      First lines on the list (labelled with Px) are value of SFRs which are
-      internal latch registers. Second lines (labelled with Pinx) are outputs
+      First lines on the list (labeled with Px) are value of SFRs which are
+      internal latch registers. Second lines (labeled with Pinx) are outputs
       of external devices connected to port pins of the
       microcontroller. These values can be set by you using sp
-      command. Third lines (labelled with Portx)
+      command. Third lines (labeled with Portx)
       show actual values can be measured on pins of the device. These values
       are calculated with following pseudo formula:
       Portx= Px AND Pinx
@@ -132,7 +132,7 @@
       Print out SFR. This command can be used to get value of all or some
       SFRs. If you do not specify any parameter the ds command simply
       dumps out full SFR area 16 bytes per line.
-      
$ s51 remoansi.hex 
+      $ ucsim_51 remoansi.hex 
 ucsim 0.2.12, Copyright (C) 1997 Daniel Drotos, Talker Bt.
 ucsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
 This is free software, and you are welcome to redistribute it
@@ -169,14 +169,14 @@
       Note that different type of controllers can implement different
         registers:
       
-      $ s51
+      $ ucsim_51
 ucsim 0.2.12, Copyright (C) 1997 Daniel Drotos, Talker Bt.
 ucsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
 This is free software, and you are welcome to redistribute it
 under certain conditions; type `show c' for details.
 > ds rcap2l
 > q
-$ s51 -t 52
+$ ucsim_51 -t 52
 ucsim 0.2.12, Copyright (C) 1997 Daniel Drotos, Talker Bt.
 ucsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
 This is free software, and you are welcome to redistribute it
@@ -196,7 +196,7 @@
       or SFR which contains the bit and bit number within the byte separated
       by a dot. If the requested bit is in an SFR the address of the
       register can be specified by its name.
-      $ s51
+      $ ucsim_51
 ucsim 0.2.12, Copyright (C) 1997 Daniel Drotos, Talker Bt.
 ucsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
 This is free software, and you are welcome to redistribute it
@@ -247,7 +247,7 @@
         breakpoints. It means that if there is a breakpoint at start address
         then it will not be hit.
       
-      $ s51 remoansi.hex
+      $ ucsim_51 remoansi.hex
 ucsim 0.2.24, Copyright (C) 1997 Daniel Drotos, Talker Bt.
 ucsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
 This is free software, and you are welcome to redistribute it
@@ -275,14 +275,14 @@
 Invalid address used in an instruction. For example indirectaddress is bigger then 127 in 51 type of controller. Execution can be
 continued but result will be undefined.
 
3
-
Stack overflow. Execution can be continued but result will beundefined.
+
Stack overflow. Execution can be continued but result will be undefined.
 
4
 
Breakpoint has been reached.
 
5
 
Interrupt accepted. It only stops the execution if stopit
 option is set to TRUE. See sopt command.
 
-After this diagnostic message the simulator prints out intruction atthe PC in disassembled form. See dis
+After this diagnostic message the simulator prints out instruction at the PC in disassembled form. See dis
 commands for description of disassembled form.-->
       
         wi,Wi string
@@ -299,7 +299,7 @@
         \0, and \0xxx where xxx is an octadecimal
         number of the code of the character.
       
-      $ s51 remoansi.hex
+      $ ucsim_51 remoansi.hex
 ucsim 0.2.24, Copyright (C) 1997 Daniel Drotos, Talker Bt.
 ucsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
 This is free software, and you are welcome to redistribute it
@@ -348,7 +348,7 @@
         options known by the program. In this way you can figure out which
         options can be used.
       
-      $ s51 -V
+      $ ucsim_51 -V
 ucsim 0.2.24, Copyright (C) 1997 Daniel Drotos, Talker Bt.
 ucsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
 This is free software, and you are welcome to redistribute it
@@ -396,7 +396,7 @@
         T, y, Y then value will be TRUE otherwise
         it will be FALSE.
       
-      $ s51 -V
+      $ ucsim_51 -V
 ucsim 0.2.24, Copyright (C) 1997 Daniel Drotos, Talker Bt.
 ucsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
 This is free software, and you are welcome to redistribute it
@@ -419,7 +419,7 @@
       Write data into internal RAM area. First parameter specifies start
         address of memory area to set and other parameters are data to set.
       
-      $ s51
+      $ ucsim_51
 ucsim 0.2.12, Copyright (C) 1997 Daniel Drotos, Talker Bt.
 ucsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
 This is free software, and you are welcome to redistribute it
@@ -456,7 +456,7 @@
         first parameter (start address) can be specified by name of SFR
         not by address only.
       
-      $ s51
+      $ ucsim_51
 ucsim 0.2.12, Copyright (C) 1997 Daniel Drotos, Talker Bt.
 ucsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
 This is free software, and you are welcome to redistribute it
@@ -474,7 +474,7 @@
         be specified. If first character of data parameter is 0 it
         means zero otherwise it means one.
       
-      $ s51
+      $ ucsim_51
 ucsim 0.2.12, Copyright (C) 1997 Daniel Drotos, Talker Bt.
 ucsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
 This is free software, and you are welcome to redistribute it
@@ -509,7 +509,7 @@
         read back value of the port can be false. First parameter must be
         number of the port between 0 and 3.
       
-      $ s51
+      $ ucsim_51
 ucsim 0.2.12, Copyright (C) 1997 Daniel Drotos, Talker Bt.
 ucsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
 This is free software, and you are welcome to redistribute it
@@ -542,7 +542,7 @@
       Fill command. It can be used to fill up an area of internal RAM with a
         specified data.
       
-      $ s51
+      $ ucsim_51
 ucsim 0.2.12, Copyright (C) 1997 Daniel Drotos, Talker Bt.
 ucsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
 This is free software, and you are welcome to redistribute it
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/doc/index.html sdcc-4.2.0+dfsg/sim/ucsim/doc/index.html
--- sdcc-4.0.0+dfsg/sim/ucsim/doc/index.html	2019-07-02 08:44:01.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/doc/index.html	2022-01-18 09:48:32.000000000 +0000
@@ -1,6 +1,6 @@
 
   
-    
+    
     Mikrocontroller Simulator
   
    [ News ]
@@ -19,18 +19,18 @@
 |_|                           
   
     Software simulator for microcontrollers
-    μCsim can be used to simulate microcontrollers. It supports
-    MCS51 family, AVR core, Z80, HC08, ST7, STM8, TLCS90, XA51 and Paduk. It can
+    μCsim can be used to simulate microcontrollers. It supports
+    MCS51 family, AVR core, Z80, HC08, ST7, STM8, TLCS90, XA51 and Padauk. It can
     run on Linux, Windows, OSX, BSD, and other systems.

     

     See what's new in current version.

     Download
-    There are two places where you can download μCsim from:

+    There are two places where you can download μCsim from:

     
-      SDCC homepage. μCsim is part of the SDCC (Small Device C
+      
SDCC homepage. μCsim is part of the SDCC (Small Device C
         Compiler) project. You can download source of SDCC and precompiled
         binaries from http://sdcc.sf.net.
-      μCsim site. Standalone source package is available on the μCsim
+      
μCsim site. Standalone source package is available on the μCsim
         web site:

         http://mazsola.iit.uni-miskolc.hu/ucsim/download
       
@@ -50,8 +50,8 @@
         option to the configure. Default directory is /usr/local.
         Executable file will be placed in bin subdirectory. 
       Compile the package with make command. 
-      Install executables s51, savr, shc08, sxa,
-        sz80, etc. to any directory you want. It can be done with make
+      
Install executables ucsim_51, ucsim_avr, ucsim_hc08, ucsim_xa,
+        ucsim_z80, etc. to any directory you want. It can be done with make
             install command which will place files in installation
         directory specified with --prefix=dir option of configure. Note that you may have to have
@@ -66,7 +66,7 @@
     
     Features of the simulator 
     
-      Code analyser. 

+      
Code analyzer. 

         The simulator tries to figure out places of valid instructions in code
         area.
       Processor types. 

@@ -85,22 +85,31 @@
         This is a special interface which provides services for the simulated
         program. This services can be used to control the simulator (for example
         run/stop) and access some host features (print, file I/O).
-      VCD file dumper.

+      
VCD file I/O.

         This is a special virtual hardware peripheral which can monitor changes
         of a memory location (or a bit in MCS51 where bit address space is
-        available) and write out changes to a VCD file.
+        available) and write out changes to a VCD file. It can also be used to
+        replay events from a VCD file in order to simulate external events.
       Command syntax and command
           reference. 

         The simulator can be controlled via a command line interface. It accepts
         simple commands. 
     
+    Microcontroller specific features 
+    
+	    STM8
+    
+    Developers
+    
+      Regression Testing
+    
     
     
-          
+          
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/doc/invoke.html sdcc-4.2.0+dfsg/sim/ucsim/doc/invoke.html
--- sdcc-4.0.0+dfsg/sim/ucsim/doc/invoke.html	2019-07-02 08:44:01.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/doc/invoke.html	2022-01-15 21:15:29.000000000 +0000
@@ -6,18 +6,26 @@
   Starting the simulator
     There are separate programs to simulate different microcontroller families:
-    MCS51 family is simulated by s51 

-      AVR family is simulated by savr 

-      Z80 processor is simulated by sz80 

-      XA family is simulated by sxa 

-      HC08 processor is simulated by shc08 

-      ST7 family is simulated by sst7 

-      STM8 family is simulated by sstm8 

-      TLCS90 family is simulated by stlcs

-      Padauk family is simulated by spdk
+    Intel MCS51 family is simulated by ucsim_51 

+      Philips XA processor is simulated by ucsim_xa 

+      Atmel AVR processor is simulated by ucsim_avr 

+      Zilog Z80 family is simulated by ucsim_z80 

+      Toshiba TLCS90 processor is simulated by ucsim_tlcs 

+      Rabbit family is simulated by ucsim_rxk 

+      Motorola M68HC08 processor is simulated by ucsim_m68hc08 

+      Motorola MC6800 processor is simulated by ucsim_m6800 

+      Motorola MC6809 processor family is simulated by ucsim_m6809

+      
+      MOS MOS6502 processor is simulated by ucsim_mos6502 

+      ST ST7 processor is simulated by ucsim_st7 

+      ST STM8 family is simulated by ucsim_stm8 

+      Padauk family is simulated by ucsim_pdk

+      p1516 processor is simulated by ucsim_p1516
+    
+
     The simulator can be started in the following way: 
-    $ s51 [-hHVvPgGwb] [-p prompt] [-t CPU] [-X
-        freq[k|M]] [-C cfg_file] [-e command] [-c file] [-s file] [-S
+    
$ ucsim_51 [-hHVvPgGwlbB] [-p prompt] [-t CPU] [-X
+        freq[k|M]] [-R seed] [-C cfg_file] [-e command] [-c file] [-s file] [-S
         optionlist] [-I if_optionlist] [-a nr] [-Z portnum] [-k portnum] [-o colorlist] [files...] 
Specified files must be names of Intel hex files. Simulator loads them in
       the specified order into the ROM of the simulated system. If the file is
@@ -47,6 +55,8 @@
         used to specify frequency in kHZ or MHz. Space is not allowed between
         the number and the k or M. Default value is 11059200 Hz.
         
+      
-R seed

+      Set seed value for the random number generator.
       -C cfg_file
       Read and execute initial commands from specified file.
       -e command
@@ -90,7 +100,7 @@
       -p prompt 
       Using this option you can specify any string to be the prompt of
         command interpreter, for example:
-        $ s51 -p "s51> "
+        $ ucsim_51 -p "s51> "
 ucsim 0.2.12, Copyright (C) 1997 Daniel Drotos, Talker Bt.
 ucsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
 This is free software, and you are welcome to redistribute it
@@ -119,10 +129,12 @@
             expression result,
           dump_address address
             color in memory dump (1^st column)
+          dump_label label
+            color in memory dump (2^nd column)
           dump_number color of
-            numerical part of the dump (2^nd column)
+            numerical part of the dump (3^rd column)
           dump_char color of
-            textual part of the dump (3^rd column)
+            textual part of the dump (4^th column)
           error color of error
             messages
           debug color of debug
@@ -187,8 +199,13 @@
         underlined bright green on black):

         -o
           prompt=lb:white:green,command=u:bgreen:black

+      -l
+      Use colors of light theme (default is dark)
       -b
       Black & white (non-color) console.
+      -B
+      Beep on breakpoints. Print out a beep character to the
+      console when a breakpoint hits.
       -g
       Go, start simulation when the program is loaded.
       -G
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/doc/Makefile.in sdcc-4.2.0+dfsg/sim/ucsim/doc/Makefile.in
--- sdcc-4.0.0+dfsg/sim/ucsim/doc/Makefile.in	2019-03-26 06:58:18.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/doc/Makefile.in	2021-10-29 17:39:15.000000000 +0000
@@ -41,20 +41,24 @@
 	cp $(srcdir)/*.html $(DESTDIR)$(docdir)
 	cp $(srcdir)/*.svg $(DESTDIR)$(docdir)
 	cp $(srcdir)/*.jpg $(DESTDIR)$(docdir)
-	cp $(srcdir)/*.fig $(DESTDIR)$(docdir)
+	cp $(srcdir)/ucsim.1 $(DESTDIR)$(man1dir)
+	cp $(srcdir)/serialview.1 $(DESTDIR)$(man1dir)
 
 
 # Deleting all the installed files
 # --------------------------------
 uninstall:
 	rm -rf $(DESTDIR)$(docdir)
+	rm -rf $(DESTDIR)$(man1dir)/ucsim.1
+	rm -rf $(DESTDIR)$(man1dir)/serialview.1
 
 
 # Performing self-test
 # --------------------
 check:
 
-test:
+test baseline:
+	@true
 
 
 # Performing installation test
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/doc/mulcons.html sdcc-4.2.0+dfsg/sim/ucsim/doc/mulcons.html
--- sdcc-4.0.0+dfsg/sim/ucsim/doc/mulcons.html	2019-03-22 11:23:06.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/doc/mulcons.html	2021-09-19 19:38:05.000000000 +0000
@@ -1,50 +1,42 @@
 
   
-    
-    μCsim: Multiple Consoles
+    
+    μCsim: Multiple Consoles
   
   
     Using multiple consoles
     Why?
-    Using more than one console can be useful if you want to issue a
-    command during the simulated program is executed.
+    Using more than one console can be useful if you want to issue a command
+    during the simulated program is executed.
     How?
-    To get multiple consoles you have to execute the simulator in the
-      background like daemons run in UNIX systems. The simulator
-      then will listen and wait for network connection requests and provide
-      console functions for network connections.
-    
-    To run μCsim in the background you have to use -Z
-      option for the simulator:
-    
-    pigmy$ s51 -Z 5555 foo.hex
-
-    In this case s51 runs in foreground in your command interpreters point
-    of view. Of course you can run the program really in the background:
-    pigmy$ s51 -Z 5555 foo.hex &
-
-    The parameter of the -Z option is a
-    port number. This can be number of any unused port of your machine. If
-    the specified port is already occupied then following message appears:
-    pigmy$ s51 -Z 5555
+    To get multiple consoles you have to execute the simulator in the background
+      like daemons run in UNIX systems. The simulator then will listen and wait
+      for network connection requests and provide console functions for network
+      connections. 
+    To run μCsim in the background you have to use -Z
+      option for the simulator: 
+    pigmy$ ucsim_51 -Z 5555 foo.hex
+ In this case ucsim_51 runs in foreground in your command interpreters point of
+    view. Of course you can run the program really in the background:
+    pigmy$ ucsim_51 -Z 5555 foo.hex &
+
 The parameter of the -Z option is a
+    port number. This can be number of any unused port of your machine. If the
+    specified port is already occupied then following message appears:
+    pigmy$ ucsim_51 -Z 5555
 bind: Address already in use
-
-    In this case you have to use an other number.
-    Let's suppose you have found a free port number and the simulator
-      listens on it. Now go to somewhere else, at least to an other window
-      and connect to the simulator:
-    
+ In this case you have to use an other number.
+    Let's suppose you have found a free port number and the simulator listens
+      on it. Now go to somewhere else, at least to an other window and connect
+      to the simulator: 
     other_machine$ telnet pigmy 5555
-
-    First parameter to the telnet command is the name of the machine where
-    the simulator is running on. It can be localhost if you are
-    on the same machine or the fully qualified host name if you are at the
-    other end of the world. Second parameter is the number of the port
-    where the simulator is listening. It must be the same number which was
-    specified as parameter of the -Z
-    option when the simulator was started (see above).
-    Connecting to the simulator you get a command console:
-    
+ First parameter to the telnet command is the name of the machine where
+    the simulator is running on. It can be localhost if you are on the
+    same machine or the fully qualified host name if you are at the other end of
+    the world. Second parameter is the number of the port where the simulator is
+    listening. It must be the same number which was specified as parameter of
+    the -Z option when the simulator was
+    started (see above).
+    Connecting to the simulator you get a command console: 
     pigmy$ telnet pigmy 5555
 Trying 127.0.0.1...
 Connected to pigmy.talker.bt.
@@ -57,26 +49,23 @@
  
 
     What to do with it?
-    Obviously you can telnet into the simulator as many times as many
-    command consoles you want. You can start the execution using one
-    console and while the program is executed you can, for example, modify
-    ports on the other console.
+    Obviously you can telnet into the simulator as many times as many command
+    consoles you want. You can start the execution using one console and while
+    the program is executed you can, for example, modify ports on the other
+    console.
     Stop
     Using quit (q) command you can not stop the
-    simulator. It just stops the actual console and the simulator
-    continues to listen for incoming network connections.
+    simulator. It just stops the actual console and the simulator continues to
+    listen for incoming network connections.
     To stop the simulator completely you have to use kill
-      command. Note that if you stop the
-      simulator then all the active network connections (all other consoles)
-      will stop.
-    
+      command. Note that if you stop the simulator (by kill) then all the active
+      network connections (all other consoles) will stop. 
     Tricks
-    You can get a console on the terminal where you started the
-    simulator. To do this you must explicitly ask the simulator to open a
-    console on the standard input/output. You can do this using -c
-    option and specify the actual
-    terminal as parameter for it:
-    pigmy$ s51 -Z 5555 foo.hex -c /dev/tty
+    You can get a console on the terminal where you started the simulator. To do
+    this you must explicitly ask the simulator to open a console on the standard
+    input/output. You can do this using -c
+    option and specify the actual terminal as parameter for it:
+    pigmy$ ucsim_51 -Z 5555 foo.hex -c /dev/tty
 
     
   
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/doc/news.html sdcc-4.2.0+dfsg/sim/ucsim/doc/news.html
--- sdcc-4.0.0+dfsg/sim/ucsim/doc/news.html	2019-07-02 08:44:01.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/doc/news.html	2021-11-17 12:40:43.000000000 +0000
@@ -5,25 +5,31 @@
   
   
     News
+    
     version 0.6
     
       Command line editing
       Command line history
       New operators for expr and variables
-      TLCS90 simulator
+      New simulators: TLCS90, pdk, M6809
+      New simulators: PicoBlaze, MCS6502, MC6800, Rabbit
       Simulator interface
       Memory banking
       Bit banding
       Serial line simulation for STM8
-      pdk14 simulator
       Conditional breakpoints
       Breakpoint script
       Built-in terminal for UART with simulator control
       Built-in display and control for MCS51 ports
       Dump changes of values to VCD file
-      Read information from SDCC outputs: cdb and omf file
+      Read information from SDCC outputs: cdb and omf files
       Variables
       Colors
+      Execution history
     
     
   
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/doc/serial.html sdcc-4.2.0+dfsg/sim/ucsim/doc/serial.html
--- sdcc-4.0.0+dfsg/sim/ucsim/doc/serial.html	2019-03-22 11:23:06.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/doc/serial.html	2022-01-26 16:35:40.000000000 +0000
@@ -1,7 +1,7 @@
 
   
     
-    μCsim: Serial Interafces
+    μCsim: Serial Interfaces
   
   
     Using serial interfaces
@@ -10,7 +10,7 @@
     simulated microcontroller. This terminal is just a file so it can be
     anything which is represented as a file. It can be a real serial line
     of the computer:
-    $ s51 -s/dev/ttyS1
+    $ ucsim_51 -s/dev/ttyS1
 
     Of course you must use the actual device name of your operating
     system. Device name ttyS1 above is used in Linux
@@ -39,14 +39,14 @@
         
       
       Run the simulator in the other window:
-        $ s51 -s/dev/ttyp1 program.hex
+        $ ucsim_51 -s/dev/ttyp1 program.hex
 
         Use the output of the tty command above as the parameter of the
         -s option.
       
     
     Every character sent out by the simulated program
-    appears in the "terminal" window and every charater you type in there
+    appears in the "terminal" window and every character you type in there
     will be received by the simulated controller's serial line.
     Connecting two instances of simulator
     Executing two instances of the simulator, serial lines of two
@@ -65,9 +65,9 @@
       Start two simulators and specify the FIFOs as input and output of
         serial interface:
         term1 $ # start sim "1"
-term1 $ s51 -Sin=2-1,out=1-2 program_1_.hex
+term1 $ ucsim_51 -Sin=2-1,out=1-2 program_1_.hex
 term2 $ # start sim "2"
-term2 $ s51 -Sout=2-1,in=1-2 program_2_.hex
+term2 $ ucsim_51 -Sout=2-1,in=1-2 program_2_.hex
 
         Because opening a pipe blocks the program until other direction is
         opened, the order of arguments above is important!
@@ -77,7 +77,7 @@
       
Debug programs as usual.
       
     
-    Using the most usefull unix commands cat and tee and
+    Using the most useful unix commands cat and tee and
     just some more FIFOs you can monitor serial communication, here is a
     sample:
     
@@ -93,8 +93,8 @@
 
       
       Now you can start simulators (on two other terminals:)
-        xterm3 $ s51 -Sin=tee_1,out=1_tee program_1_.hex
-xterm4 $ s51 -Sin=tee_2,out=2_tee program_2_.hex
+        xterm3 $ ucsim_51 -Sin=tee_1,out=1_tee program_1_.hex
+xterm4 $ ucsim_51 -Sin=tee_2,out=2_tee program_2_.hex
 
       
       Start your apps and listen what they are talking about.
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/doc/serialview.1 sdcc-4.2.0+dfsg/sim/ucsim/doc/serialview.1
--- sdcc-4.0.0+dfsg/sim/ucsim/doc/serialview.1	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/doc/serialview.1	2021-10-29 17:39:15.000000000 +0000
@@ -0,0 +1,79 @@
+.TH SERIALVIEW 1
+
+.SH NAME
+serialview \- Terminal emulator for uCsim
+
+
+.SH SYNOPSIS
+.B serialview
+\-i  \-o  \-L n \-a  \-A  \-IOh
+
+
+.SH DESCRIPTION
+serialview is a simple terminal emulator which can be used with uCsim.
+
+
+.SH OPTIONS
+
+.TP
+.B \-i filename
+.I filename
+is the pipe to the controllers's serial input. Characters typed into
+the input panel will be written to this file.
+
+.TP
+.B \-o filename
+.I filename
+is the pipe to the controllers's serial output. Content of this file
+is prosented on the output panel.
+
+.TP
+.B \-I
+Use hexadecimal filter on input. Only hexadecimal characters are
+accepted in input panel. Two characters are combined into a
+hexadecimal code and value is written to the input pipe.
+
+.TP
+.B \-O
+Use hexadecimal filter on output. Content of output pipe is presented
+as a hexadecimal dump. \-L option can be used to set how many bytes
+are printed in one line.
+
+.TP
+.B \-a pattern
+.I pattern
+is a string which is recognized in output stream and automaticaly
+answered by sending an answer string (see \-A option). String can be
+formatted as a C string, non-asci characters can be escaped in C
+style.
+
+.TP
+.B \-A answer
+.I answer
+is a string which is sent when a pattern (see \-a option) is detected
+in simulator's output. This answer string is written to the input pipe
+but not shown in the input panel.
+
+.TP
+.B \-L n
+Set line length of hexadecimal dump in output panel (default=8).
+
+.TP
+.B \-h
+Show summary of options.
+
+.PP
+When no options are provided the input and output pipes are created in
+.B /tmp
+and named respectively
+.B in
+and
+.B out
+
+
+.SH "SEE ALSO"
+sdcc(1), ucsim(1).
+
+
+.SH AUTHOR
+Timothy Hurman
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/doc/simif.html sdcc-4.2.0+dfsg/sim/ucsim/doc/simif.html
--- sdcc-4.0.0+dfsg/sim/ucsim/doc/simif.html	2019-07-02 08:44:01.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/doc/simif.html	2022-01-07 16:27:29.000000000 +0000
@@ -3,23 +3,6 @@
   
     
     μCsim: Simulator interface
-    
-    
   
   
     Simulator interface
@@ -43,7 +26,7 @@
       if
       this setting is used to turn on the interface. Its value must be a
         memory name and the address, like:

-        s51 -I if=xram[0xffff]

+        ucsim_51 -I if=xram[0xffff]

         memory name must be followed by the address in square brackets.
         Address can be specified in decimal, octal or hexadecimal.

       in
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/doc/stm8/index.html sdcc-4.2.0+dfsg/sim/ucsim/doc/stm8/index.html
--- sdcc-4.0.0+dfsg/sim/ucsim/doc/stm8/index.html	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/doc/stm8/index.html	2022-01-27 21:35:29.000000000 +0000
@@ -0,0 +1,267 @@
+
+
+
+  
+
+  Features of the STM8 Simulator
+
+
+
+  Features of the STM8 Simulator
+
+
+  Cycle Counts
+
+  Instruction timings are correct and take into account pipeline overlaps
+  and stall cycles. The only known exceptions are HALT, WFI and WFE which
+  are either not yet implemented or, in the case of HALT, only partially
+  and minimally implemented.
+
+  Notes on Documention
+
+  PM0044 Section 5.3 Pipelined execution examples
+      There are some errors in these tables. See the trace outputs in the
+      Example Analyses section below for details.
+
+  PM0044 Section 7.4 Instruction Set
+      The cycle counts shown for instructions in PM0044 section 7 are one less
+          than the actual counts because the first decode cycle of an instruction
+          normally overlaps with the last execution cycle of the preceding
+          instruction.
+
+
+  Stall Cycle Detection
+
+  Error/warning event reporting of stall cycles is available should timings
+  be important in your application.
+      
0> show error
+  Error: non-classified [on/ON]
+    [...]
+    Error: stm8 [off/OFF]
+      Warning: pipeline [unset/OFF]
+        Warning: decode_stall [unset/OFF]
+        Warning: fetch_stall [unset/OFF]
+    [...]
+
+  These are off by default but may be enabled as required either as a group:
+      
0> set error pipeline
+  or individually:
+      0> set error decode_stall on
+0> set error fetch_stall on
+  
+
+
+  Cycle and Pipeline Analysis
+
+  The simulator is able to generate detailed analyses of execution showing timings
+  for each instruction executed including pipeline overlaps and stalls. This is controlled
+  via the pipetrace feature of the STM8 CPU module. The output is in the form
+  of a self-contained HTML document that can be opened with a browser or imported into
+  other application documentation.
+
+  To generate a pipeline analysis:
+
+  
+      Set the title for the next pipetrace to be opened.
+          0> set hw cpu pipetrace title "..."
+      
+
+      Replace the embedded default styling with a stylesheet link to the given URL.
+          0> set hw cpu pipetrace style "url"
+      
+
+      Open the given file, write the header (including title and stylesheet) and
+          continue writing the pipeline analysis as instructions are executed.
+          0> set hw cpu pipetrace start "path"
+      
+
+      Set folding of the analysis on (the default) or off. Folding causes the cycle
+          count to be reset to zero (moving the output back to the left) after every
+          pipeline flush (i.e. after every branch, jump or call). It is recommended you
+          leave this on unless you have very wide paper or are single stepping
+          and annotating the analysis between steps.
+          0> set hw cpu pipetrace fold [on|off]
+      
+
+      Pause writing the pipeline analysis. The output file remains open but nothing
+          will be written to as instructions are executed.
+          0> set hw cpu pipetrace pause
+      
+
+      Insert the given text into the current pipeline analysis. The text is
+          inserted verbatim and may contain HTML markup. If the output is not
+          paused the cycle count for the analysis is set back to zero so that the
+          next instruction output will be moved back to the left (the first cycle
+          after the inserted text does however overlap the last cycle before the
+          inserted text as normal).
+          0> set hw cpu pipetrace data "text"
+      
+
+      Resume a paused pipeline analysis. Instruction execution will update the
+          analysis output again. Resuming a paused analysis resets the cycle count
+          to zero so that the next instruction output is moved back to the left.
+          (The next cycle may or may not overlap the last cycle before the pause
+          depending on whether or not any instructions were executed while the
+          output was paused.)
+          0> set hw cpu pipetrace resume
+      
+
+      Stop the pipeline analysis and close the output file. No further analysis will
+          occur until a new analysis file is started.
+          0> set hw cpu pipetrace stop
+      
+  
+
+  
+  Example Analyses
+
+  Documented Examples
+
+  These are taken from the examples in ST's “PM0044 Programming Manual”
+  section “5.3 Pipelined execution examples” and are generated by
+  the test ucsim/stm8.src/test/stm8-cycles
+  using the “pipetrace”functionality described above.
+
+  Note that there are some errors in the examples in section 5.3. These are noted in
+  the output below and the differences confirmed on HW.
+
+  
+    
+        PM0044 5.4 Table 3. Example with exact number of cycles
+        
+    

+        PM0044 5.4.1 Table 8. Optimized pipeline example - execution from Flash
+        
+    

+        PM0044 5.4.2 Table 6. Optimized pipeline example - execution from RAM
+        
+    

+        PM0044 5.4.3 Table 10. Pipeline with Call/Jump
+        
+    

+        PM0044 5.4.4 Table 12. Example of stalled pipeline
+        
+  
+
+  Additional Examples
+
+  The DIV instruction is special in that it takes a variable number of cycles and
+  is interruptible.
+
+  
+    
+        Examples of DIV execution
+        
+    

+        Examples of interrupted DIV execution
+         (not currently implemented)
+  
+
+  Other instructions, each run individually starting from an empty pipeline and
+  showing the overlap with the following instruction.
+
+  
+    
+        Examples of individual instruction execution
+        
+  
+
+  Hardware Cycle Counting
+
+  Actual cycle counts may be obtained from hardware for comparison using a combination
+  of stm8-gdb, openocd and an STLink
+  or other openocd/SWIM compatible debugger. Set the master and CPU clocks to be equivalent
+  and use one of the target's timers to count cycles.
+  For instance:
+  +$ openocd -f interface/stlink.cfg -f target/stm8s003.cfg &
+$ stm8-gdb
+[...]
+(gdb) target extended-remote :3333
+
+
+(gdb) set $DM_CSR2 = 0x7f99
+(gdb) set $DM_ENFCTR = 0x7f9a
+
+(gdb) set $CLK_CKDIVR  = 0x50c6
+(gdb) set $CLK_PCKENR1 = 0x50c7
+
+(gdb) set $TIM2_CR1  = 0x5300
+(gdb) set $TIM2_EGR  = 0x5306
+(gdb) set $TIM2_CNTRH = 0x530c
+(gdb) set $TIM2_CNTRL = 0x530d
+(gdb) set $TIM2_PSCR = 0x530e
+
+
+(gdb) define cycles
+    dont-repeat
+
+    # Freeze TIM2 when CPU is stalled by DM
+    set {unsigned char}$DM_ENFCTR = 0xfd
+
+    # Set HSIDIV = 0, CPUDIV = 0
+    set {unsigned char}$CLK_CKDIVR = 0x00
+    # Set TIM2 prescalar to 0 so f_CK_CNT matches f_MASTER (and hence f_CPU)
+    set {unsigned char}$TIM2_PSCR = 0x00
+
+    # Clear count and update config
+    set {unsigned char}$TIM2_EGR = 1
+    set {unsigned char}$TIM2_CNTRH = 0xff
+    set {unsigned char}$TIM2_CNTRL = 0xff
+
+    # Enable counter
+    set {unsigned char}$TIM2_CR1  = 0x01
+    # Enable clock gate
+    set {unsigned char}$CLK_PCKENR1 = 0x20
+
+    # Set PC
+    # N.B. Do not attempt to flush the decoder by writing to DM_CSR2. It upsets
+    # openocd which is then unable to set breakpoints.
+    set $pc = $arg0
+    #set {unsigned char}$DM_CSR2 = 0x81
+
+    # Set a HW breakpoint, run, then clear
+    monitor bp $arg1 1 hw
+    cont
+    monitor rbp $arg1
+
+    set $_tmp = {unsigned short}$TIM2_CNTR
+    disass/r $arg0,$arg1
+    printf "%u cycles\n", $_tmp
+end
+
+(gdb) document cycles
+Set PC to the first address, set a HW break at the second address,
+run and report how many cycles (as reported by $TIM2_CNTR) it took.
+The target is assumed to be halted initially.
+end
+
+(gdb) monitor reset halt
+target halted due to debug-request, pc: 0x00008000
+(gdb) x/3i 0x811c
+   0x811c:      ldw X,#0xfc00 ;0xfc00
+   0x811f:      ld A,#0x80 ;0x80
+   0x8121:      div X,A
+(gdb) cycles 0x811c 0x8122
+target halted due to debug-request, pc: 0x00008000
+breakpoint set at 0x00008122
+
+
+Program received signal SIGTRAP, Trace/breakpoint trap.
+0x00008122 in ?? ()
+Dump of assembler code from 0x811c to 0x8122:
+   0x0000811c:  ae fc 00        ldw X,#0xfc00 ;0xfc00
+   0x0000811f:  a6 80   ld A,#0x80 ;0x80
+   0x00008121:  62      div X,A
+End of assembler dump.
+14 cycles
+  
+
+  Don't forget that there will be an initial pipeline fetch cycle
+  before the first instruction can be decoded, there may be stall
+  cycles, multiple instructions (mostly) overlap by one cycle (which is
+  assumed in the timings given by PM0044), and you may have interrupts
+  that should be disabled.
+
+
+
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/doc/stm8/test.div.html sdcc-4.2.0+dfsg/sim/ucsim/doc/stm8/test.div.html
--- sdcc-4.0.0+dfsg/sim/ucsim/doc/stm8/test.div.html	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/doc/stm8/test.div.html	2022-01-18 09:48:32.000000000 +0000
@@ -0,0 +1,473 @@
+
+
+DIV tests - available ST docs simply say '2-17 cycles'
+
+
+
+
+
+
+
+DIV tests - available ST docs simply say '2-17 cycles'
+
+
       
         
           © 1997,99 D�niel Dr�tos, Talker Bt. 

+                border="0" align="top"> © 1997,99 Dániel Drótos, Talker Bt. 

             drdani@mazsola.iit.uni-miskolc.hu
         
       
     
     

+    
+    
+    
+    
+    
+    
+    
+    
+    
+Legend
Decode
Execute
Fetch
Flush
Fetch Stall - space in prefetch buffer but bus busy
Decode Stall - bus busy
Decode Stall - insufficient data in prefetch buffer
Decode Stall - read after write

+
+The stated cycle count would seem to imply binary long division and
+   this is how the STM8 emulator in ucsim currently treats div for.
+   cycle counting. However the cycles measured on actual hardware
+   suggest this is not correct.
+
+
+
+    
+        
+        
+        
+        
+    
+    
+        
+    
+ 
0x08100 ldw    X,#0x8000 
0x08103 ld     A,#0x80 
0x08105 div    X,A 
Address Instruction 1 2 3 4 5 6 7 8
+
+
+
+
+    
+        
+        
+        
+        
+    
+    
+        
+    
+ 
0x08108 ldw    X,#0x8000 
0x0810b ld     A,#0x40 
0x0810d div    X,A 
Address Instruction 1 2 3 4 5 6 7 8
+
+
+
+
+    
+        
+        
+        
+        
+    
+    
+        
+    
+ 
0x08110 ldw    X,#0x8000 
0x08113 ld     A,#0x20 
0x08115 div    X,A 
Address Instruction 1 2 3 4 5 6 7 8
+
+
+
+
+    
+        
+        
+        
+        
+    
+    
+        
+    
+ 
0x08118 ldw    X,#0x8000 
0x0811b ld     A,#0x10 
0x0811d div    X,A 
Address Instruction 1 2 3 4 5 6 7 8
+
+
+
+
+    
+        
+        
+        
+        
+    
+    
+        
+    
+ 
0x08120 ldw    X,#0x8000 
0x08123 ld     A,#0x08 
0x08125 div    X,A 
Address Instruction 1 2 3 4 5 6 7 8
+
+
+
+
+    
+        
+        
+        
+        
+    
+    
+        
+    
+ 
0x08128 ldw    X,#0x8000 
0x0812b ld     A,#0x04 
0x0812d div    X,A 
Address Instruction 1 2 3 4 5 6 7 8
+
+
+
+
+    
+        
+        
+        
+        
+    
+    
+        
+    
+ 
0x08130 ldw    X,#0x8000 
0x08133 ld     A,#0x02 
0x08135 div    X,A 
Address Instruction 1 2 3 4 5 6 7 8
+
+
+
+
+    
+        
+        
+        
+        
+    
+    
+        
+    
+ 
0x08138 ldw    X,#0x8000 
0x0813b ld     A,#0x01 
0x0813d div    X,A 
Address Instruction 1 2 3 4 5 6
+
+
+
+
+    
+        
+        
+        
+        
+    
+    
+        
+    
+ 
0x08140 ldw    X,#0x8000 
0x08143 ld     A,#0x80 
0x08145 div    X,A 
Address Instruction 1 2 3 4 5 6 7 8
+
+
+
+
+    
+        
+        
+        
+        
+    
+    
+        
+    
+ 
0x08148 ldw    X,#0x4000 
0x0814b ld     A,#0x80 
0x0814d div    X,A 
Address Instruction 1 2 3 4 5 6 7 8
+
+
+
+
+    
+        
+        
+        
+        
+    
+    
+        
+    
+ 
0x08150 ldw    X,#0x2000 
0x08153 ld     A,#0x80 
0x08155 div    X,A 
Address Instruction 1 2 3 4 5 6 7 8
+
+
+
+
+    
+        
+        
+        
+        
+    
+    
+        
+    
+ 
0x08158 ldw    X,#0x1000 
0x0815b ld     A,#0x80 
0x0815d div    X,A 
Address Instruction 1 2 3 4 5 6 7 8
+
+
+
+
+    
+        
+        
+        
+        
+    
+    
+        
+    
+ 
0x08160 ldw    X,#0x0800 
0x08163 ld     A,#0x80 
0x08165 div    X,A 
Address Instruction 1 2 3 4 5 6 7 8
+
+
+
+
+    
+        
+        
+        
+        
+    
+    
+        
+    
+ 
0x08168 ldw    X,#0x0400 
0x0816b ld     A,#0x80 
0x0816d div    X,A 
Address Instruction 1 2 3 4 5 6 7 8
+
+
+
+
+    
+        
+        
+        
+        
+    
+    
+        
+    
+ 
0x08170 ldw    X,#0x0200 
0x08173 ld     A,#0x80 
0x08175 div    X,A 
Address Instruction 1 2 3 4 5 6 7 8
+
+
+
+
+    
+        
+        
+        
+        
+    
+    
+        
+    
+ 
0x08178 ldw    X,#0x0100 
0x0817b ld     A,#0x80 
0x0817d div    X,A 
Address Instruction 1 2 3 4 5 6 7 8
+
+
+
+
+    
+        
+        
+        
+        
+    
+    
+        
+    
+ 
0x08180 ldw    X,#0x0080 
0x08183 ld     A,#0x80 
0x08185 div    X,A 
Address Instruction 1 2 3 4 5 6 7
+
+
+
+
+    
+        
+        
+        
+        
+    
+    
+        
+    
+ 
0x08188 ldw    X,#0x0040 
0x0818b ld     A,#0x80 
0x0818d div    X,A 
Address Instruction 1 2 3 4 5 6 7
+
+
+
+
+    
+        
+        
+        
+        
+    
+    
+        
+    
+ 
0x08190 ldw    X,#0x0020 
0x08193 ld     A,#0x80 
0x08195 div    X,A 
Address Instruction 1 2 3 4 5 6 7
+
+
+
+
+    
+        
+        
+        
+        
+    
+    
+        
+    
+ 
0x08198 ldw    X,#0x0010 
0x0819b ld     A,#0x80 
0x0819d div    X,A 
Address Instruction 1 2 3 4 5 6 7
+
+
+
+
+    
+        
+        
+        
+        
+    
+    
+        
+    
+ 
0x081a0 ldw    X,#0x0008 
0x081a3 ld     A,#0x80 
0x081a5 div    X,A 
Address Instruction 1 2 3 4 5 6 7
+
+
+
+
+    
+        
+        
+        
+        
+    
+    
+        
+    
+ 
0x081a8 ldw    X,#0x0004 
0x081ab ld     A,#0x80 
0x081ad div    X,A 
Address Instruction 1 2 3 4 5 6 7
+
+
+
+
+    
+        
+        
+        
+        
+    
+    
+        
+    
+ 
0x081b0 ldw    X,#0x0002 
0x081b3 ld     A,#0x80 
0x081b5 div    X,A 
Address Instruction 1 2 3 4 5 6 7
+
+
+
+
+    
+        
+        
+        
+        
+    
+    
+        
+    
+ 
0x081b8 ldw    X,#0x0001 
0x081bb ld     A,#0x80 
0x081bd div    X,A 
Address Instruction 1 2 3 4 5 6 7
+
+
+
+
+    
+        
+        
+        
+        
+    
+    
+        
+    
+ 
0x081c0 ldw    X,#0x0000 
0x081c3 ld     A,#0x80 
0x081c5 div    X,A 
Address Instruction 1 2 3 4 5 6 7
+
+
+
+
+    
+        
+        
+        
+        
+    
+    
+        
+    
+ 
0x081c8 ldw    X,#0x003f 
0x081cb ld     A,#0x08 
0x081cd div    X,A 
Address Instruction 1 2 3 4 5 6 7 8 9
+
+
+
+
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+    
+ 
0x081d0 ldw    X,#0x0040 
0x081d3 ld     A,#0x08 
0x081d5 div    X,A 
Address Instruction 1 2 3 4 5 6 7 8
+
+
+
+
+    
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+    
+ 
0x081d8 ldw    X,#0x0041 
0x081db ld     A,#0x08 
0x081dd div    X,A 
Address Instruction 1 2 3 4 5 6 7 8
+
+
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+    
+ 
0x081e0 ldw    X,#0x8000 
0x081e3 ldw    Y,#0x0001 
0x081e7 divw   X,Y 
Address Instruction 1 2 3 4 5 6 7
+
+
+
+
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/doc/stm8/test.instrs.html sdcc-4.2.0+dfsg/sim/ucsim/doc/stm8/test.instrs.html
--- sdcc-4.0.0+dfsg/sim/ucsim/doc/stm8/test.instrs.html	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/doc/stm8/test.instrs.html	2022-01-18 09:48:32.000000000 +0000
@@ -0,0 +1,1627 @@
+
+
+All instructions and addressing modes
+
+
+
+
+
+
+
+All instructions and addressing modes
+
+
+    
+    
+    
+    
+    
+    
+    
+    
+    
+Legend
Decode
Execute
Fetch
Flush
Fetch Stall - space in prefetch buffer but bus busy
Decode Stall - bus busy
Decode Stall - insufficient data in prefetch buffer
Decode Stall - read after write
+
+Note that timings given in PM0044 assume a 1 cycle overlap
+with the previous instruction and are specified as being
+one cycle less than they are in the no prefetch/stall case.
+Instructions that flush the prefetch buffer such as jumps
+prevent the overlap with the following instruction. The cycle
+count for these instructions includes the extra cycles for
+the unavoidable fetches and stalls that follow them.
+
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+ 
0x08204 adc    A,#0x55 
0x08206 jra    0x8208 
0x08208 adc    A,0x10 
0x0820a jra    0x820c 
0x0820c adc    A,0x1000 
0x0820f jra    0x8214 
0x08214 adc    A,(X) 
0x08215 jra    0x8218 
0x08218 adc    A,(0x10,X) 
0x0821a jra    0x821c 
0x0821c adc    A,(0x1000,X) 
0x0821f jra    0x8224 
0x08224 adc    A,(Y) 
0x08226 jra    0x8228 
0x08228 adc    A,(0x10,Y) 
0x0822b jra    0x8230 
0x08230 adc    A,(0x1000,Y) 
0x08234 jra    0x8238 
0x08238 adc    A,(0x10,SP) 
0x0823a jra    0x823c 
0x0823c adc    A,[0x10.w] 
0x0823f jra    0x8244 
0x08244 adc    A,[0x1000.w] 
0x08248 jra    0x824c 
0x0824c adc    A,([0x10.w],X) 
0x0824f jra    0x8254 
0x08254 adc    A,([0x1000.w],X) 
0x08258 jra    0x825c 
0x0825c adc    A,([0x10.w],Y) 
0x0825f jra    0x8264 
0x08264 add    A,#0x55 
0x08266 jra    0x8268 
0x08268 add    A,0x10 
0x0826a jra    0x826c 
0x0826c add    A,0x1000 
0x0826f jra    0x8274 
0x08274 add    A,(X) 
0x08275 jra    0x8278 
0x08278 add    A,(0x10,X) 
0x0827a jra    0x827c 
0x0827c add    A,(0x1000,X) 
0x0827f jra    0x8284 
0x08284 add    A,(Y) 
0x08286 jra    0x8288 
0x08288 add    A,(0x10,Y) 
0x0828b jra    0x8290 
0x08290 add    A,(0x1000,Y) 
0x08294 jra    0x8298 
0x08298 add    A,(0x10,SP) 
0x0829a jra    0x829c 
0x0829c add    A,[0x10.w] 
0x0829f jra    0x82a4 
0x082a4 add    A,[0x1000.w] 
0x082a8 jra    0x82ac 
0x082ac add    A,([0x10.w],X) 
0x082af jra    0x82b4 
0x082b4 add    A,([0x1000.w],X) 
0x082b8 jra    0x82bc 
0x082bc add    A,([0x10.w],Y) 
0x082bf jra    0x82c4 
0x082c4 addw   X,#0x1000 
0x082c7 jra    0x82cc 
0x082cc addw   X,0x1000 
0x082d0 jra    0x82d4 
0x082d4 addw   X,(0x10,SP) 
0x082d7 jra    0x82dc 
0x082dc addw   Y,#0x1000 
0x082e0 jra    0x82e4 
0x082e4 addw   Y,0x1000 
0x082e8 jra    0x82ec 
0x082ec addw   Y,0x10 
0x082ef jra    0x82f4 
0x082f4 add    SP,#0x55 
0x082f6 jra    0x82f8 
0x082f8 and    A,#0x55 
0x082fa jra    0x82fc 
0x082fc and    A,0x10 
0x082fe jra    0x8300 
0x08300 and    A,0x1000 
0x08303 jra    0x8308 
0x08308 and    A,(X) 
0x08309 jra    0x830c 
0x0830c and    A,(0x10,X) 
0x0830e jra    0x8310 
0x08310 and    A,(0x1000,X) 
0x08313 jra    0x8318 
0x08318 and    A,(Y) 
0x0831a jra    0x831c 
0x0831c and    A,(0x10,Y) 
0x0831f jra    0x8324 
0x08324 and    A,(0x1000,Y) 
0x08328 jra    0x832c 
0x0832c and    A,(0x10,SP) 
0x0832e jra    0x8330 
0x08330 and    A,[0x10.w] 
0x08333 jra    0x8338 
0x08338 and    A,[0x1000.w] 
0x0833c jra    0x8340 
0x08340 and    A,([0x10.w],X) 
0x08343 jra    0x8348 
0x08348 and    A,([0x1000.w],X) 
0x0834c jra    0x8350 
0x08350 and    A,([0x10.w],Y) 
0x08353 jra    0x8358 
0x08358 bccm   0x10,#2 
0x0835c jra    0x8360 
0x08360 bcp    A,#0x55 
0x08362 jra    0x8364 
0x08364 bcp    A,0x10 
0x08366 jra    0x8368 
0x08368 bcp    A,0x1000 
0x0836b jra    0x8370 
0x08370 bcp    A,(X) 
0x08371 jra    0x8374 
0x08374 bcp    A,(0x10,X) 
0x08376 jra    0x8378 
0x08378 bcp    A,(0x1000,X) 
0x0837b jra    0x8380 
0x08380 bcp    A,(Y) 
0x08382 jra    0x8384 
0x08384 bcp    A,(0x10,Y) 
0x08387 jra    0x838c 
0x0838c bcp    A,(0x1000,Y) 
0x08390 jra    0x8394 
0x08394 bcp    A,(0x10,SP) 
0x08396 jra    0x8398 
0x08398 bcp    A,[0x10.w] 
0x0839b jra    0x83a0 
0x083a0 bcp    A,[0x1000.w] 
0x083a4 jra    0x83a8 
0x083a8 bcp    A,([0x10.w],X) 
0x083ab jra    0x83b0 
0x083b0 bcp    A,([0x1000.w],X) 
0x083b4 jra    0x83b8 
0x083b8 bcp    A,([0x10.w],Y) 
0x083bb jra    0x83c0 
0x083c0 bcpl   0x10,#2 
0x083c4 jra    0x83c8 
0x083c8 bres   0x1000,#2 
0x083cc jra    0x83d0 
0x083d0 bset   0x1000,#2 
0x083d4 jra    0x83d8 
0x083d8 ccf 
0x083d9 jra    0x83dc 
0x083dc clr    A 
0x083dd jra    0x83e0 
0x083e0 clr    0xf5 
0x083e2 jra    0x83e4 
0x083e4 clr    0xf5c2 
0x083e8 jra    0x83ec 
0x083ec clr    (X) 
0x083ed jra    0x83f0 
0x083f0 clr    (0xf5,X) 
0x083f2 jra    0x83f4 
0x083f4 clr    (0xf5c2,X) 
0x083f8 jra    0x83fc 
0x083fc clr    (Y) 
0x083fe jra    0x8400 
0x08400 clr    (0xf5,Y) 
0x08403 jra    0x8408 
0x08408 clr    (0xf5c2,Y) 
0x0840c jra    0x8410 
0x08410 clr    (0xf5,SP) 
0x08412 jra    0x8414 
0x08414 clr    [0xf5.w] 
0x08417 jra    0x841c 
0x0841c clr    [0xf5c2.w] 
0x08420 jra    0x8424 
0x08424 clr    ([0xf5.w],X) 
0x08427 jra    0x842c 
0x0842c clr    ([0xf5c2.w],X) 
0x08430 jra    0x8434 
0x08434 clr    ([0xf5.w],Y) 
0x08437 jra    0x843c 
0x0843c clrw   X 
0x0843d jra    0x8440 
0x08440 clrw   Y 
0x08442 jra    0x8444 
0x08444 cp     A,#0x55 
0x08446 jra    0x8448 
0x08448 cp     A,0x10 
0x0844a jra    0x844c 
0x0844c cp     A,0x1000 
0x0844f jra    0x8454 
0x08454 cp     A,(X) 
0x08455 jra    0x8458 
0x08458 cp     A,(0x10,X) 
0x0845a jra    0x845c 
0x0845c cp     A,(0x1000,X) 
0x0845f jra    0x8464 
0x08464 cp     A,(Y) 
0x08466 jra    0x8468 
0x08468 cp     A,(0x10,Y) 
0x0846b jra    0x8470 
0x08470 cp     A,(0x1000,Y) 
0x08474 jra    0x8478 
0x08478 cp     A,(0x10,SP) 
0x0847a jra    0x847c 
0x0847c cp     A,[0x10.w] 
0x0847f jra    0x8484 
0x08484 cp     A,[0x1000.w] 
0x08488 jra    0x848c 
0x0848c cp     A,([0x10.w],X) 
0x0848f jra    0x8494 
0x08494 cp     A,([0x1000.w],X) 
0x08498 jra    0x849c 
0x0849c cp     A,([0x10.w],Y) 
0x0849f jra    0x84a4 
0x084a4 cpw    X,#0x0055 
0x084a7 jra    0x84ac 
0x084ac cpw    X,0x10 
0x084ae jra    0x84b0 
0x084b0 cpw    X,0x1000 
0x084b3 jra    0x84b8 
0x084b8 cpw    X,(Y) 
0x084ba jra    0x84bc 
0x084bc cpw    X,(0x10,Y) 
0x084bf jra    0x84c4 
0x084c4 cpw    X,(0x1000,Y) 
0x084c8 jra    0x84cc 
0x084cc cpw    X,(0x10,SP) 
0x084ce jra    0x84d0 
0x084d0 cpw    X,[0x10.w] 
0x084d3 jra    0x84d8 
0x084d8 cpw    Y,[0x1000.w] 
0x084dc jra    0x84e0 
0x084e0 cpw    X,([0x10.w],Y) 
0x084e3 jra    0x84e8 
0x084e8 cpw    Y,([0x1000.w],X) 
0x084ec jra    0x84f0 
0x084f0 cpl    A 
0x084f1 jra    0x84f4 
0x084f4 cpl    0xf5 
0x084f6 jra    0x84f8 
0x084f8 cpl    0xf5c2 
0x084fc jra    0x8500 
0x08500 cpl    (X) 
0x08501 jra    0x8504 
0x08504 cpl    (0xf5,X) 
0x08506 jra    0x8508 
0x08508 cpl    (0xf5c2,X) 
0x0850c jra    0x8510 
0x08510 cpl    (Y) 
0x08512 jra    0x8514 
0x08514 cpl    (0xf5,Y) 
0x08517 jra    0x851c 
0x0851c cpl    (0xf5c2,Y) 
0x08520 jra    0x8524 
0x08524 cpl    (0xf5,SP) 
0x08526 jra    0x8528 
0x08528 cpl    [0xf5.w] 
0x0852b jra    0x8530 
0x08530 cpl    [0xf5c2.w] 
0x08534 jra    0x8538 
0x08538 cpl    ([0xf5.w],X) 
0x0853b jra    0x8540 
0x08540 cpl    ([0xf5c2.w],X) 
0x08544 jra    0x8548 
0x08548 cpl    ([0xf5.w],Y) 
0x0854b jra    0x8550 
0x08550 cplw   X 
0x08551 jra    0x8554 
0x08554 cplw   Y 
0x08556 jra    0x8558 
0x08558 dec    A 
0x08559 jra    0x855c 
0x0855c dec    0xf5 
0x0855e jra    0x8560 
0x08560 dec    0xf5c2 
0x08564 jra    0x8568 
0x08568 dec    (X) 
0x08569 jra    0x856c 
0x0856c dec    (0xf5,X) 
0x0856e jra    0x8570 
0x08570 dec    (0xf5c2,X) 
0x08574 jra    0x8578 
0x08578 dec    (Y) 
0x0857a jra    0x857c 
0x0857c dec    (0xf5,Y) 
0x0857f jra    0x8584 
0x08584 dec    (0xf5c2,Y) 
0x08588 jra    0x858c 
0x0858c dec    (0xf5,SP) 
0x0858e jra    0x8590 
0x08590 dec    [0xf5.w] 
0x08593 jra    0x8598 
0x08598 dec    [0xf5c2.w] 
0x0859c jra    0x85a0 
0x085a0 dec    ([0xf5.w],X) 
0x085a3 jra    0x85a8 
0x085a8 dec    ([0xf5c2.w],X) 
0x085ac jra    0x85b0 
0x085b0 dec    ([0xf5.w],Y) 
0x085b3 jra    0x85b8 
0x085b8 decw   X 
0x085b9 jra    0x85bc 
0x085bc decw   Y 
0x085be jra    0x85c0 
0x085c0 exg    A,XL 
0x085c1 jra    0x85c4 
0x085c4 exg    A,YL 
0x085c5 jra    0x85c8 
0x085c8 exg    A,0x1000 
0x085cb jra    0x85d0 
0x085d0 exgw   X,Y 
0x085d1 jra    0x85d4 
0x085d4 inc    A 
0x085d5 jra    0x85d8 
0x085d8 inc    0xf5 
0x085da jra    0x85dc 
0x085dc inc    0xf5c2 
0x085e0 jra    0x85e4 
0x085e4 inc    (X) 
0x085e5 jra    0x85e8 
0x085e8 inc    (0xf5,X) 
0x085ea jra    0x85ec 
0x085ec inc    (0xf5c2,X) 
0x085f0 jra    0x85f4 
0x085f4 inc    (Y) 
0x085f6 jra    0x85f8 
0x085f8 inc    (0xf5,Y) 
0x085fb jra    0x8600 
0x08600 inc    (0xf5c2,Y) 
0x08604 jra    0x8608 
0x08608 inc    (0xf5,SP) 
0x0860a jra    0x860c 
0x0860c inc    [0xf5.w] 
0x0860f jra    0x8614 
0x08614 inc    [0xf5c2.w] 
0x08618 jra    0x861c 
0x0861c inc    ([0xf5.w],X) 
0x0861f jra    0x8624 
0x08624 inc    ([0xf5c2.w],X) 
0x08628 jra    0x862c 
0x0862c inc    ([0xf5.w],Y) 
0x0862f jra    0x8634 
0x08634 incw   X 
0x08635 jra    0x8638 
0x08638 incw   Y 
0x0863a jra    0x863c 
0x0863c ld     A,#0x55 
0x0863e jra    0x8640 
0x08640 ld     A,0x10 
0x08642 jra    0x8644 
0x08644 ld     A,0x1000 
0x08647 jra    0x864c 
0x0864c ld     A,(X) 
0x0864d jra    0x8650 
0x08650 ld     A,(0x10,X) 
0x08652 jra    0x8654 
0x08654 ld     A,(0x1000,X) 
0x08657 jra    0x865c 
0x0865c ld     A,(Y) 
0x0865e jra    0x8660 
0x08660 ld     A,(0x10,Y) 
0x08663 jra    0x8668 
0x08668 ld     A,(0x1000,Y) 
0x0866c jra    0x8670 
0x08670 ld     A,(0x10,SP) 
0x08672 jra    0x8674 
0x08674 ld     A,[0x10.w] 
0x08677 jra    0x867c 
0x0867c ld     A,[0x1000.w] 
0x08680 jra    0x8684 
0x08684 ld     A,([0x10.w],X) 
0x08687 jra    0x868c 
0x0868c ld     A,([0x1000.w],X) 
0x08690 jra    0x8694 
0x08694 ld     A,([0x10.w],Y) 
0x08697 jra    0x869c 
0x0869c ld     0x10,A 
0x0869e jra    0x86a0 
0x086a0 ld     0x1000,A 
0x086a3 jra    0x86a8 
0x086a8 ld     (X),A 
0x086a9 jra    0x86ac 
0x086ac ld     (0x10,X),A 
0x086ae jra    0x86b0 
0x086b0 ld     (0x1000,X),A 
0x086b3 jra    0x86b8 
0x086b8 ld     (Y),A 
0x086ba jra    0x86bc 
0x086bc ld     (0x10,Y),A 
0x086bf jra    0x86c4 
0x086c4 ld     (0x1000,Y),A 
0x086c8 jra    0x86cc 
0x086cc ld     (0x10,SP),A 
0x086ce jra    0x86d0 
0x086d0 ld     [0x10.w],A 
0x086d3 jra    0x86d8 
0x086d8 ld     [0x1000.w],A 
0x086dc jra    0x86e0 
0x086e0 ld     ([0x10.w],X),A 
0x086e3 jra    0x86e8 
0x086e8 ld     ([0x1000.w],X),A 
0x086ec jra    0x86f0 
0x086f0 ld     ([0x10.w],Y),A 
0x086f3 jra    0x86f8 
0x086f8 ldf    A,0x500000 
0x086fc jra    0x8700 
0x08700 ldf    A,(0x500000,X) 
0x08704 jra    0x8708 
0x08708 ldf    A,(0x500000,Y) 
0x0870d jra    0x8710 
0x08710 ldf    A,([0x5000 <pa_odr>.e],X) 
0x08714 jra    0x8718 
0x08718 ldf    A,([0x5000 <pa_odr>.e],Y) 
0x0871c jra    0x8720 
0x08720 ldf    A,[0x50.e] 
0x08724 jra    0x8728 
0x08728 ldw    X,#0x0055 
0x0872b jra    0x8730 
0x08730 ldw    X,0x10 
0x08732 jra    0x8734 
0x08734 ldw    X,0x1000 
0x08737 jra    0x873c 
0x0873c ldw    X,(X) 
0x0873d jra    0x8740 
0x08740 ldw    X,(0x10,X) 
0x08742 jra    0x8744 
0x08744 ldw    X,(0x1000,X) 
0x08747 jra    0x874c 
0x0874c ldw    X,(0x10,SP) 
0x0874e jra    0x8750 
0x08750 ldw    X,[0x10.w] 
0x08753 jra    0x8758 
0x08758 ldw    X,[0x1000.w] 
0x0875c jra    0x8760 
0x08760 ldw    X,([0x10.w],X) 
0x08763 jra    0x8768 
0x08768 ldw    X,([0x1000.w],X) 
0x0876c jra    0x8770 
0x08770 mov    0x8000,#0xaa 
0x08774 jra    0x8778 
0x08778 mov    0x80,0x10 
0x0877b jra    0x8780 
0x08780 mov    0x8000,0x1000 
0x08785 jra    0x8788 
0x08788 mul    X,A 
0x08789 jra    0x878c 
0x0878c neg    A 
0x0878d jra    0x8790 
0x08790 neg    0xf5 
0x08792 jra    0x8794 
0x08794 neg    0xf5c2 
0x08798 jra    0x879c 
0x0879c neg    (X) 
0x0879d jra    0x87a0 
0x087a0 neg    (0xf5,X) 
0x087a2 jra    0x87a4 
0x087a4 neg    (0xf5c2,X) 
0x087a8 jra    0x87ac 
0x087ac neg    (Y) 
0x087ae jra    0x87b0 
0x087b0 neg    (0xf5,Y) 
0x087b3 jra    0x87b8 
0x087b8 neg    (0xf5c2,Y) 
0x087bc jra    0x87c0 
0x087c0 neg    (0xf5,SP) 
0x087c2 jra    0x87c4 
0x087c4 neg    [0xf5.w] 
0x087c7 jra    0x87cc 
0x087cc neg    [0xf5c2.w] 
0x087d0 jra    0x87d4 
0x087d4 neg    ([0xf5.w],X) 
0x087d7 jra    0x87dc 
0x087dc neg    ([0xf5c2.w],X) 
0x087e0 jra    0x87e4 
0x087e4 neg    ([0xf5.w],Y) 
0x087e7 jra    0x87ec 
0x087ec negw   X 
0x087ed jra    0x87f0 
0x087f0 negw   Y 
0x087f2 jra    0x87f4 
0x087f4 nop 
0x087f5 jra    0x87f8 
0x087f8 or     A,#0x55 
0x087fa jra    0x87fc 
0x087fc or     A,0x10 
0x087fe jra    0x8800 
0x08800 or     A,0x1000 
0x08803 jra    0x8808 
0x08808 or     A,(X) 
0x08809 jra    0x880c 
0x0880c or     A,(0x10,X) 
0x0880e jra    0x8810 
0x08810 or     A,(0x1000,X) 
0x08813 jra    0x8818 
0x08818 or     A,(Y) 
0x0881a jra    0x881c 
0x0881c or     A,(0x10,Y) 
0x0881f jra    0x8824 
0x08824 or     A,(0x1000,Y) 
0x08828 jra    0x882c 
0x0882c or     A,(0x10,SP) 
0x0882e jra    0x8830 
0x08830 or     A,[0x10.w] 
0x08833 jra    0x8838 
0x08838 or     A,[0x1000.w] 
0x0883c jra    0x8840 
0x08840 or     A,([0x10.w],X) 
0x08843 jra    0x8848 
0x08848 or     A,([0x1000.w],X) 
0x0884c jra    0x8850 
0x08850 or     A,([0x10.w],Y) 
0x08853 jra    0x8858 
0x08858 rcf 
0x08859 jra    0x885c 
0x0885c rlc    A 
0x0885d jra    0x8860 
0x08860 rlc    0xf5 
0x08862 jra    0x8864 
0x08864 rlc    0xf5c2 
0x08868 jra    0x886c 
0x0886c rlc    (X) 
0x0886d jra    0x8870 
0x08870 rlc    (0xf5,X) 
0x08872 jra    0x8874 
0x08874 rlc    (0xf5c2,X) 
0x08878 jra    0x887c 
0x0887c rlc    (Y) 
0x0887e jra    0x8880 
0x08880 rlc    (0xf5,Y) 
0x08883 jra    0x8888 
0x08888 rlc    (0xf5c2,Y) 
0x0888c jra    0x8890 
0x08890 rlc    (0xf5,SP) 
0x08892 jra    0x8894 
0x08894 rlc    [0xf5.w] 
0x08897 jra    0x889c 
0x0889c rlc    [0xf5c2.w] 
0x088a0 jra    0x88a4 
0x088a4 rlc    ([0xf5.w],X) 
0x088a7 jra    0x88ac 
0x088ac rlc    ([0xf5c2.w],X) 
0x088b0 jra    0x88b4 
0x088b4 rlc    ([0xf5.w],Y) 
0x088b7 jra    0x88bc 
0x088bc rlcw   X 
0x088bd jra    0x88c0 
0x088c0 rlcw   Y 
0x088c2 jra    0x88c4 
0x088c4 rlwa   X 
0x088c5 jra    0x88c8 
0x088c8 rlwa   Y 
0x088ca jra    0x88cc 
0x088cc rrc    A 
0x088cd jra    0x88d0 
0x088d0 rrc    0xf5 
0x088d2 jra    0x88d4 
0x088d4 rrc    0xf5c2 
0x088d8 jra    0x88dc 
0x088dc rrc    (X) 
0x088dd jra    0x88e0 
0x088e0 rrc    (0xf5,X) 
0x088e2 jra    0x88e4 
0x088e4 rrc    (0xf5c2,X) 
0x088e8 jra    0x88ec 
0x088ec rrc    (Y) 
0x088ee jra    0x88f0 
0x088f0 rrc    (0xf5,Y) 
0x088f3 jra    0x88f8 
0x088f8 rrc    (0xf5c2,Y) 
0x088fc jra    0x8900 
0x08900 rrc    (0xf5,SP) 
0x08902 jra    0x8904 
0x08904 rrc    [0xf5.w] 
0x08907 jra    0x890c 
0x0890c rrc    [0xf5c2.w] 
0x08910 jra    0x8914 
0x08914 rrc    ([0xf5.w],X) 
0x08917 jra    0x891c 
0x0891c rrc    ([0xf5c2.w],X) 
0x08920 jra    0x8924 
0x08924 rrc    ([0xf5.w],Y) 
0x08927 jra    0x892c 
0x0892c rrcw   X 
0x0892d jra    0x8930 
0x08930 rrcw   Y 
0x08932 jra    0x8934 
0x08934 rrwa   X 
0x08935 jra    0x8938 
0x08938 rrwa   Y 
0x0893a jra    0x893c 
0x0893c rvf 
0x0893d jra    0x8940 
0x08940 sbc    A,#0x55 
0x08942 jra    0x8944 
0x08944 sbc    A,0x10 
0x08946 jra    0x8948 
0x08948 sbc    A,0x1000 
0x0894b jra    0x8950 
0x08950 sbc    A,(X) 
0x08951 jra    0x8954 
0x08954 sbc    A,(0x10,X) 
0x08956 jra    0x8958 
0x08958 sbc    A,(0x1000,X) 
0x0895b jra    0x8960 
0x08960 sbc    A,(Y) 
0x08962 jra    0x8964 
0x08964 sbc    A,(0x10,Y) 
0x08967 jra    0x896c 
0x0896c sbc    A,(0x1000,Y) 
0x08970 jra    0x8974 
0x08974 sbc    A,(0x10,SP) 
0x08976 jra    0x8978 
0x08978 sbc    A,[0x10.w] 
0x0897b jra    0x8980 
0x08980 sbc    A,[0x1000.w] 
0x08984 jra    0x8988 
0x08988 sbc    A,([0x10.w],X) 
0x0898b jra    0x8990 
0x08990 sbc    A,([0x1000.w],X) 
0x08994 jra    0x8998 
0x08998 sbc    A,([0x10.w],Y) 
0x0899b jra    0x89a0 
0x089a0 scf 
0x089a1 jra    0x89a4 
0x089a4 subw   X,#0x5500 
0x089a7 jra    0x89ac 
0x089ac subw   X,0x10 
0x089b0 jra    0x89b4 
0x089b4 subw   X,(0x10,SP) 
0x089b7 jra    0x89bc 
0x089bc ldw    Y,X 
0x089be jra    0x89c0 
0x089c0 ldw    0x10,X 
0x089c2 jra    0x89c4 
0x089c4 ldw    0x1000,X 
0x089c7 jra    0x89cc 
0x089cc ldw    (X),Y 
0x089cd jra    0x89d0 
0x089d0 ldw    (0x10,X),Y 
0x089d2 jra    0x89d4 
0x089d4 ldw    (0x1000,X),Y 
0x089d7 jra    0x89dc 
0x089dc ldw    (0x10,SP),X 
0x089de jra    0x89e0 
0x089e0 ldw    [0x10.w],X 
0x089e3 jra    0x89e8 
0x089e8 ldw    [0x1000.w],X 
0x089ec jra    0x89f0 
0x089f0 ldw    ([0x10.w],X),Y 
0x089f3 jra    0x89f8 
0x089f8 ldw    ([0x1000.w],X),Y 
0x089fc jra    0x8a00 
0x08a00 sla    A 
0x08a01 jra    0x8a04 
0x08a04 sla    0xf5 
0x08a06 jra    0x8a08 
0x08a08 sla    0xf5c2 
0x08a0c jra    0x8a10 
0x08a10 sla    (X) 
0x08a11 jra    0x8a14 
0x08a14 sla    (0xf5,X) 
0x08a16 jra    0x8a18 
0x08a18 sla    (0xf5c2,X) 
0x08a1c jra    0x8a20 
0x08a20 sla    (Y) 
0x08a22 jra    0x8a24 
0x08a24 sla    (0xf5,Y) 
0x08a27 jra    0x8a2c 
0x08a2c sla    (0xf5c2,Y) 
0x08a30 jra    0x8a34 
0x08a34 sla    (0xf5,SP) 
0x08a36 jra    0x8a38 
0x08a38 sla    [0xf5.w] 
0x08a3b jra    0x8a40 
0x08a40 sla    [0xf5c2.w] 
0x08a44 jra    0x8a48 
0x08a48 sla    ([0xf5.w],X) 
0x08a4b jra    0x8a50 
0x08a50 sla    ([0xf5c2.w],X) 
0x08a54 jra    0x8a58 
0x08a58 sla    ([0xf5.w],Y) 
0x08a5b jra    0x8a60 
0x08a60 slaw   X 
0x08a61 jra    0x8a64 
0x08a64 slaw   Y 
0x08a66 jra    0x8a68 
0x08a68 sla    A 
0x08a69 jra    0x8a6c 
0x08a6c sla    0xf5 
0x08a6e jra    0x8a70 
0x08a70 sla    0xf5c2 
0x08a74 jra    0x8a78 
0x08a78 sla    (X) 
0x08a79 jra    0x8a7c 
0x08a7c sla    (0xf5,X) 
0x08a7e jra    0x8a80 
0x08a80 sla    (0xf5c2,X) 
0x08a84 jra    0x8a88 
0x08a88 sla    (Y) 
0x08a8a jra    0x8a8c 
0x08a8c sla    (0xf5,Y) 
0x08a8f jra    0x8a94 
0x08a94 sla    (0xf5c2,Y) 
0x08a98 jra    0x8a9c 
0x08a9c sla    (0xf5,SP) 
0x08a9e jra    0x8aa0 
0x08aa0 sla    [0xf5.w] 
0x08aa3 jra    0x8aa8 
0x08aa8 sla    [0xf5c2.w] 
0x08aac jra    0x8ab0 
0x08ab0 sla    ([0xf5.w],X) 
0x08ab3 jra    0x8ab8 
0x08ab8 sla    ([0xf5c2.w],X) 
0x08abc jra    0x8ac0 
0x08ac0 sla    ([0xf5.w],Y) 
0x08ac3 jra    0x8ac8 
0x08ac8 slaw   X 
0x08ac9 jra    0x8acc 
0x08acc slaw   Y 
0x08ace jra    0x8ad0 
0x08ad0 sra    A 
0x08ad1 jra    0x8ad4 
0x08ad4 sra    0xf5 
0x08ad6 jra    0x8ad8 
0x08ad8 sra    0xf5c2 
0x08adc jra    0x8ae0 
0x08ae0 sra    (X) 
0x08ae1 jra    0x8ae4 
0x08ae4 sra    (0xf5,X) 
0x08ae6 jra    0x8ae8 
0x08ae8 sra    (0xf5c2,X) 
0x08aec jra    0x8af0 
0x08af0 sra    (Y) 
0x08af2 jra    0x8af4 
0x08af4 sra    (0xf5,Y) 
0x08af7 jra    0x8afc 
0x08afc sra    (0xf5c2,Y) 
0x08b00 jra    0x8b04 
0x08b04 sra    (0xf5,SP) 
0x08b06 jra    0x8b08 
0x08b08 sra    [0xf5.w] 
0x08b0b jra    0x8b10 
0x08b10 sra    [0xf5c2.w] 
0x08b14 jra    0x8b18 
0x08b18 sra    ([0xf5.w],X) 
0x08b1b jra    0x8b20 
0x08b20 sra    ([0xf5c2.w],X) 
0x08b24 jra    0x8b28 
0x08b28 sra    ([0xf5.w],Y) 
0x08b2b jra    0x8b30 
0x08b30 sraw   X 
0x08b31 jra    0x8b34 
0x08b34 sraw   Y 
0x08b36 jra    0x8b38 
0x08b38 srl    A 
0x08b39 jra    0x8b3c 
0x08b3c srl    0xf5 
0x08b3e jra    0x8b40 
0x08b40 srl    0xf5c2 
0x08b44 jra    0x8b48 
0x08b48 srl    (X) 
0x08b49 jra    0x8b4c 
0x08b4c srl    (0xf5,X) 
0x08b4e jra    0x8b50 
0x08b50 srl    (0xf5c2,X) 
0x08b54 jra    0x8b58 
0x08b58 srl    (Y) 
0x08b5a jra    0x8b5c 
0x08b5c srl    (0xf5,Y) 
0x08b5f jra    0x8b64 
0x08b64 srl    (0xf5c2,Y) 
0x08b68 jra    0x8b6c 
0x08b6c srl    (0xf5,SP) 
0x08b6e jra    0x8b70 
0x08b70 srl    [0xf5.w] 
0x08b73 jra    0x8b78 
0x08b78 srl    [0xf5c2.w] 
0x08b7c jra    0x8b80 
0x08b80 srl    ([0xf5.w],X) 
0x08b83 jra    0x8b88 
0x08b88 srl    ([0xf5c2.w],X) 
0x08b8c jra    0x8b90 
0x08b90 srl    ([0xf5.w],Y) 
0x08b93 jra    0x8b98 
0x08b98 srlw   X 
0x08b99 jra    0x8b9c 
0x08b9c srlw   Y 
0x08b9e jra    0x8ba0 
0x08ba0 sub    A,#0x55 
0x08ba2 jra    0x8ba4 
0x08ba4 sub    A,0x10 
0x08ba6 jra    0x8ba8 
0x08ba8 sub    A,0x1000 
0x08bab jra    0x8bb0 
0x08bb0 sub    A,(X) 
0x08bb1 jra    0x8bb4 
0x08bb4 sub    A,(0x10,X) 
0x08bb6 jra    0x8bb8 
0x08bb8 sub    A,(0x1000,X) 
0x08bbb jra    0x8bc0 
0x08bc0 sub    A,(Y) 
0x08bc2 jra    0x8bc4 
0x08bc4 sub    A,(0x10,Y) 
0x08bc7 jra    0x8bcc 
0x08bcc sub    A,(0x1000,Y) 
0x08bd0 jra    0x8bd4 
0x08bd4 sub    A,(0x10,SP) 
0x08bd6 jra    0x8bd8 
0x08bd8 sub    A,[0x10.w] 
0x08bdb jra    0x8be0 
0x08be0 sub    A,[0x1000.w] 
0x08be4 jra    0x8be8 
0x08be8 sub    A,([0x10.w],X) 
0x08beb jra    0x8bf0 
0x08bf0 sub    A,([0x1000.w],X) 
0x08bf4 jra    0x8bf8 
0x08bf8 sub    A,([0x10.w],Y) 
0x08bfb jra    0x8c00 
0x08c00 sub    SP,#0x55 
0x08c02 jra    0x8c04 
0x08c04 swap   A 
0x08c05 jra    0x8c08 
0x08c08 swap   0xf5 
0x08c0a jra    0x8c0c 
0x08c0c swap   0xf5c2 
0x08c10 jra    0x8c14 
0x08c14 swap   (X) 
0x08c15 jra    0x8c18 
0x08c18 swap   (0xf5,X) 
0x08c1a jra    0x8c1c 
0x08c1c swap   (0xf5c2,X) 
0x08c20 jra    0x8c24 
0x08c24 swap   (Y) 
0x08c26 jra    0x8c28 
0x08c28 swap   (0xf5,Y) 
0x08c2b jra    0x8c30 
0x08c30 swap   (0xf5c2,Y) 
0x08c34 jra    0x8c38 
0x08c38 swap   (0xf5,SP) 
0x08c3a jra    0x8c3c 
0x08c3c swap   [0xf5.w] 
0x08c3f jra    0x8c44 
0x08c44 swap   [0xf5c2.w] 
0x08c48 jra    0x8c4c 
0x08c4c swap   ([0xf5.w],X) 
0x08c4f jra    0x8c54 
0x08c54 swap   ([0xf5c2.w],X) 
0x08c58 jra    0x8c5c 
0x08c5c swap   ([0xf5.w],Y) 
0x08c5f jra    0x8c64 
0x08c64 swapw  X 
0x08c65 jra    0x8c68 
0x08c68 swapw  Y 
0x08c6a jra    0x8c6c 
0x08c6c tnz    A 
0x08c6d jra    0x8c70 
0x08c70 tnz    0xf5 
0x08c72 jra    0x8c74 
0x08c74 tnz    0xf5c2 
0x08c78 jra    0x8c7c 
0x08c7c tnz    (X) 
0x08c7d jra    0x8c80 
0x08c80 tnz    (0xf5,X) 
0x08c82 jra    0x8c84 
0x08c84 tnz    (0xf5c2,X) 
0x08c88 jra    0x8c8c 
0x08c8c tnz    (Y) 
0x08c8e jra    0x8c90 
0x08c90 tnz    (0xf5,Y) 
0x08c93 jra    0x8c98 
0x08c98 tnz    (0xf5c2,Y) 
0x08c9c jra    0x8ca0 
0x08ca0 tnz    (0xf5,SP) 
0x08ca2 jra    0x8ca4 
0x08ca4 tnz    [0xf5.w] 
0x08ca7 jra    0x8cac 
0x08cac tnz    [0xf5c2.w] 
0x08cb0 jra    0x8cb4 
0x08cb4 tnz    ([0xf5.w],X) 
0x08cb7 jra    0x8cbc 
0x08cbc tnz    ([0xf5c2.w],X) 
0x08cc0 jra    0x8cc4 
0x08cc4 tnz    ([0xf5.w],Y) 
0x08cc7 jra    0x8ccc 
0x08ccc tnzw   X 
0x08ccd jra    0x8cd0 
0x08cd0 tnzw   Y 
0x08cd2 jra    0x8cd4 
0x08cd4 xor    A,#0x55 
0x08cd6 jra    0x8cd8 
0x08cd8 xor    A,0x10 
0x08cda jra    0x8cdc 
0x08cdc xor    A,0x1000 
0x08cdf jra    0x8ce4 
0x08ce4 xor    A,(X) 
0x08ce5 jra    0x8ce8 
0x08ce8 xor    A,(0x10,X) 
0x08cea jra    0x8cec 
0x08cec xor    A,(0x1000,X) 
0x08cef jra    0x8cf4 
0x08cf4 xor    A,(Y) 
0x08cf6 jra    0x8cf8 
0x08cf8 xor    A,(0x10,Y) 
0x08cfb jra    0x8d00 
0x08d00 xor    A,(0x1000,Y) 
0x08d04 jra    0x8d08 
0x08d08 xor    A,(0x10,SP) 
0x08d0a jra    0x8d0c 
0x08d0c xor    A,[0x10.w] 
0x08d0f jra    0x8d14 
0x08d14 xor    A,[0x1000.w] 
0x08d18 jra    0x8d1c 
0x08d1c xor    A,([0x10.w],X) 
0x08d1f jra    0x8d24 
0x08d24 xor    A,([0x1000.w],X) 
0x08d28 jra    0x8d2c 
0x08d2c xor    A,([0x10.w],Y) 
0x08d2f jra    0x8d34 
0x08d34 ldw    X,#0x8000 
0x08d37 ld     A,#0x02 
0x08d39 div    X,A 
0x08d3a jra    0x8d3c 
0x08d3c ldw    X,#0x4000 
0x08d3f ld     A,#0x02 
0x08d41 div    X,A 
0x08d42 jra    0x8d44 
0x08d44 ldw    X,#0x2000 
0x08d47 ld     A,#0x02 
0x08d49 div    X,A 
0x08d4a jra    0x8d4c 
0x08d4c ldw    X,#0x1000 
0x08d4f ld     A,#0x02 
0x08d51 div    X,A 
0x08d52 jra    0x8d54 
0x08d54 ldw    X,#0x0800 
0x08d57 ld     A,#0x02 
0x08d59 div    X,A 
0x08d5a jra    0x8d5c 
0x08d5c ldw    X,#0x0400 
0x08d5f ld     A,#0x02 
0x08d61 div    X,A 
0x08d62 jra    0x8d64 
0x08d64 ldw    X,#0x0200 
0x08d67 ld     A,#0x02 
0x08d69 div    X,A 
0x08d6a jra    0x8d6c 
0x08d6c ldw    X,#0x0100 
0x08d6f ld     A,#0x02 
0x08d71 div    X,A 
0x08d72 jra    0x8d74 
0x08d74 ldw    X,#0x0080 
0x08d77 ld     A,#0x02 
0x08d79 div    X,A 
0x08d7a jra    0x8d7c 
0x08d7c ldw    X,#0x0040 
0x08d7f ld     A,#0x02 
0x08d81 div    X,A 
0x08d82 jra    0x8d84 
0x08d84 ldw    X,#0x0020 
0x08d87 ld     A,#0x02 
0x08d89 div    X,A 
0x08d8a jra    0x8d8c 
0x08d8c ldw    X,#0x0010 
0x08d8f ld     A,#0x02 
0x08d91 div    X,A 
0x08d92 jra    0x8d94 
0x08d94 ldw    X,#0x0008 
0x08d97 ld     A,#0x02 
0x08d99 div    X,A 
0x08d9a jra    0x8d9c 
0x08d9c ldw    X,#0x0004 
0x08d9f ld     A,#0x02 
0x08da1 div    X,A 
0x08da2 jra    0x8da4 
0x08da4 ldw    X,#0x0002 
0x08da7 ld     A,#0x02 
0x08da9 div    X,A 
0x08daa jra    0x8dac 
0x08dac ldw    X,#0xffff 
0x08daf ld     A,#0x02 
0x08db1 div    X,A 
0x08db2 jra    0x8db4 
0x08db4 ldw    X,#0x7fff 
0x08db7 ld     A,#0x02 
0x08db9 div    X,A 
0x08dba jra    0x8dbc 
0x08dbc ldw    X,#0x3fff 
0x08dbf ld     A,#0x02 
0x08dc1 div    X,A 
0x08dc2 jra    0x8dc4 
0x08dc4 ldw    X,#0x1fff 
0x08dc7 ld     A,#0x02 
0x08dc9 div    X,A 
0x08dca jra    0x8dcc 
0x08dcc ldw    X,#0x0fff 
0x08dcf ld     A,#0x02 
0x08dd1 div    X,A 
0x08dd2 jra    0x8dd4 
0x08dd4 ldw    X,#0x07ff 
0x08dd7 ld     A,#0x02 
0x08dd9 div    X,A 
0x08dda jra    0x8ddc 
0x08ddc ldw    X,#0x03ff 
0x08ddf ld     A,#0x02 
0x08de1 div    X,A 
0x08de2 jra    0x8de4 
0x08de4 ldw    X,#0x01ff 
0x08de7 ld     A,#0x02 
0x08de9 div    X,A 
0x08dea jra    0x8dec 
0x08dec ldw    X,#0x00ff 
0x08def ld     A,#0x02 
0x08df1 div    X,A 
0x08df2 jra    0x8df4 
0x08df4 ldw    X,#0x007f 
0x08df7 ld     A,#0x02 
0x08df9 div    X,A 
0x08dfa jra    0x8dfc 
0x08dfc ldw    X,#0x003f 
0x08dff ld     A,#0x02 
0x08e01 div    X,A 
0x08e02 jra    0x8e04 
0x08e04 ldw    X,#0x001f 
0x08e07 ld     A,#0x02 
0x08e09 div    X,A 
0x08e0a jra    0x8e0c 
0x08e0c ldw    X,#0x000f 
0x08e0f ld     A,#0x02 
0x08e11 div    X,A 
0x08e12 jra    0x8e14 
0x08e14 ldw    X,#0x0007 
0x08e17 ld     A,#0x02 
0x08e19 div    X,A 
0x08e1a jra    0x8e1c 
0x08e1c ldw    X,#0x0003 
0x08e1f ld     A,#0x02 
0x08e21 div    X,A 
0x08e22 jra    0x8e24 
0x08e24 ldw    X,#0x2000 
0x08e27 ld     A,#0x02 
0x08e29 div    X,A 
0x08e2a jra    0x8e2c 
0x08e2c ldw    X,#0x2040 
0x08e2f ld     A,#0x02 
0x08e31 div    X,A 
0x08e32 jra    0x8e34 
0x08e34 ldw    X,#0x2048 
0x08e37 ld     A,#0x02 
0x08e39 div    X,A 
0x08e3a jra    0x8e3c 
0x08e3c ldw    X,#0x2148 
0x08e3f ld     A,#0x02 
0x08e41 div    X,A 
0x08e42 jra    0x8e44 
0x08e44 ldw    X,#0x21c8 
0x08e47 ld     A,#0x02 
0x08e49 div    X,A 
0x08e4a jra    0x8e4c 
0x08e4c ldw    X,#0xb307 
0x08e4f ld     A,#0x5e 
0x08e51 div    X,A 
0x08e52 halt 
Address Instruction 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
+
+
+
+
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/doc/stm8/test.int_div.html sdcc-4.2.0+dfsg/sim/ucsim/doc/stm8/test.int_div.html
--- sdcc-4.0.0+dfsg/sim/ucsim/doc/stm8/test.int_div.html	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/doc/stm8/test.int_div.html	2022-01-18 09:48:32.000000000 +0000
@@ -0,0 +1,74 @@
+
+
+Interrupted div
+
+
+
+
+
+
+
+Interrupted div
+
+
+    
+    
+    
+    
+    
+    
+    
+    
+    
+Legend
Decode
Execute
Fetch
Flush
Fetch Stall - space in prefetch buffer but bus busy
Decode Stall - bus busy
Decode Stall - insufficient data in prefetch buffer
Decode Stall - read after write
+
+(Not currently implemented.)
+
+
+    
+        
+    
+    
+        
+    
+0x08201 div    X,A 
Address Instruction 1 2 3 4 5
+
+
+
+
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/doc/stm8/test.table10.html sdcc-4.2.0+dfsg/sim/ucsim/doc/stm8/test.table10.html
--- sdcc-4.0.0+dfsg/sim/ucsim/doc/stm8/test.table10.html	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/doc/stm8/test.table10.html	2022-01-18 09:48:32.000000000 +0000
@@ -0,0 +1,92 @@
+
+
+PM0044 5.4.3 Pipeline with Call/Jump, table 10
+
+
+
+
+
+
+
+PM0044 5.4.3 Pipeline with Call/Jump, table 10
+
+
+    
+    
+    
+    
+    
+    
+    
+    
+    
+Legend
Decode
Execute
Fetch
Flush
Fetch Stall - space in prefetch buffer but bus busy
Decode Stall - bus busy
Decode Stall - insufficient data in prefetch buffer
Decode Stall - read after write
+
+PM0044 table 10 shows a fetch stall in the first execution cycle
+of the call (cycle 7) however it should be possible for a fetch
+to take place since pushing the return address only busies the
+data bus (and STM8 is a Harvard architecture with unified address
+space so the data and program are separate buses).
+Also note that since the flush happens on the last execute cycle
+of the call (unlike the jp) there is no overlap and we mark
+the following cycle as a decode stall. Technically this is correct
+but table 10 does not and says the call takes 3 cycles which
+ignores the unavoidable stall cycle. The later instruction documentation
+for call says it takes 4 cycles which is presumed to include the
+stall cycle that follows it.
+
+
+    
+        
+        
+        
+        
+        
+        
+        
+        
+    
+    
+        
+    
+ 
0x080c4 inc    A 
0x080c5 jp     0x80cc 
0x080cc neg    A 
0x080cd call   0x80d8 
0x080d8 incw   X 
Address Instruction 1 2 3 4 5 6 7 8 9 10 11
+
+
+
+
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/doc/stm8/test.table12.html sdcc-4.2.0+dfsg/sim/ucsim/doc/stm8/test.table12.html
--- sdcc-4.0.0+dfsg/sim/ucsim/doc/stm8/test.table12.html	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/doc/stm8/test.table12.html	2022-01-18 09:48:32.000000000 +0000
@@ -0,0 +1,94 @@
+
+
+PM0044 5.4.4 Pipeline stalled, table 12
+
+
+
+
+
+
+
+PM0044 5.4.4 Pipeline stalled, table 12
+
+
+    
+    
+    
+    
+    
+    
+    
+    
+    
+Legend
Decode
Execute
Fetch
Flush
Fetch Stall - space in prefetch buffer but bus busy
Decode Stall - bus busy
Decode Stall - insufficient data in prefetch buffer
Decode Stall - read after write
+
+Errata
+
+Table 12 shows the BTJT as taking 1 decode, 2 execute cycles but the
+    later documention for the instruction implies the second execution
+    cycle is only used if the branch is taken - and this isn't.
+    
+Table 12 has a jump in time (cycles) from 4 straight to 7.
+    
+The last instruction is shown one cycle early in table 12. The decode stall
+    should line up with the execution cycle of the previous instruction
+    as the description above the table says.
+    
+
+
+
+    
+        
+        
+        
+        
+        
+        
+        
+        
+        
+    
+    
+        
+    
+ 
0x080e0 sub    SP,#0x14 
0x080e2 ld     A,#0x14 
0x080e4 btjt   0x0010,#5,0x80f8 
0x080e9 inc    A 
0x080ea btjf   0x0020,#3,0x80f8 
0x080f8 incw   Y 
0x080fa ld     A,(X) 
Address Instruction 1 2 3 4 5 6 7 8 9 10 11 12
+
+
+
+
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/doc/stm8/test.table3.html sdcc-4.2.0+dfsg/sim/ucsim/doc/stm8/test.table3.html
--- sdcc-4.0.0+dfsg/sim/ucsim/doc/stm8/test.table3.html	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/doc/stm8/test.table3.html	2022-01-18 09:48:32.000000000 +0000
@@ -0,0 +1,88 @@
+
+
+PM0044 5.4 Conventions, table 3
+
+
+
+
+
+
+
+PM0044 5.4 Conventions, table 3
+
+
+    
+    
+    
+    
+    
+    
+    
+    
+    
+Legend
Decode
Execute
Fetch
Flush
Fetch Stall - space in prefetch buffer but bus busy
Decode Stall - bus busy
Decode Stall - insufficient data in prefetch buffer
Decode Stall - read after write
+
+Errata
+
+The LDW shown in PM0044 table 3 is missing a decode cycle.
+    

+    (Confirmed on HW)
+    
+The ADDW shown in PM0044 table 3 has one too many decode cycles.
+    

+    (Confirmed on HW)
+    
+The LD shown in PM0044 table 3 is missing a decode cycle.
+
+
+
+    
+        
+        
+        
+        
+    
+    
+        
+    
+ 
0x0808c ldw    X,[0x50.w] 
0x0808f addw   X,#0x0014 
0x08092 ld     A,[0x30.w] 
Address Instruction 1 2 3 4 5 6 7 8 9 10 11 12 13
+
+
+
+
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/doc/stm8/test.table6.html sdcc-4.2.0+dfsg/sim/ucsim/doc/stm8/test.table6.html
--- sdcc-4.0.0+dfsg/sim/ucsim/doc/stm8/test.table6.html	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/doc/stm8/test.table6.html	2022-01-18 09:48:32.000000000 +0000
@@ -0,0 +1,85 @@
+
+
+PM0044 5.4.1 Optimized pipeline example - execution from flash, table 6
+
+
+
+
+
+
+
+PM0044 5.4.1 Optimized pipeline example - execution from flash, table 6
+
+
+    
+    
+    
+    
+    
+    
+    
+    
+    
+Legend
Decode
Execute
Fetch
Flush
Fetch Stall - space in prefetch buffer but bus busy
Decode Stall - bus busy
Decode Stall - insufficient data in prefetch buffer
Decode Stall - read after write
+
+
+
+    
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+    
+    
+        
+    
+ 
0x08098 neg    A 
0x08099 xor    A,0x10 
0x0809b ld     A,#0x14 
0x0809d sub    A,0x1000 
0x080a0 inc    A 
0x080a1 ld     XL,A 
0x080a2 srl    A 
0x080a3 swap   A 
0x080a4 sla    0x15 
0x080a6 cp     A,#0xfe 
0x080a8 mov    0x0100,#0x0b 
0x080ac mov    0x0101,#0x16 
Address Instruction 1 2 3 4 5 6 7 8 9 10 11 12 13 14
+
+
+
+
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/doc/stm8/test.table8.html sdcc-4.2.0+dfsg/sim/ucsim/doc/stm8/test.table8.html
--- sdcc-4.0.0+dfsg/sim/ucsim/doc/stm8/test.table8.html	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/doc/stm8/test.table8.html	2022-01-18 09:48:32.000000000 +0000
@@ -0,0 +1,83 @@
+
+
+PM0044 5.4.2 Optimize pipeline example - execution from RAM, table 8
+
+
+
+
+
+
+
+PM0044 5.4.2 Optimize pipeline example - execution from RAM, table 8
+
+
+    
+    
+    
+    
+    
+    
+    
+    
+    
+Legend
Decode
Execute
Fetch
Flush
Fetch Stall - space in prefetch buffer but bus busy
Decode Stall - bus busy
Decode Stall - insufficient data in prefetch buffer
Decode Stall - read after write
+
+
+
+    
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+    
+    
+        
+    
+ 
0x00104 neg    A 
0x00105 xor    A,0x10 
0x00107 ld     A,#0x14 
0x00109 sub    A,0x1000 
0x0010c inc    A 
0x0010d ld     XL,A 
0x0010e srl    A 
0x0010f swap   A 
0x00110 sla    0x15 
0x00112 cp     A,#0xfe 
Address Instruction 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
+
+
+
+
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/doc/syntax.html sdcc-4.2.0+dfsg/sim/ucsim/doc/syntax.html
--- sdcc-4.0.0+dfsg/sim/ucsim/doc/syntax.html	2019-07-02 08:44:01.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/doc/syntax.html	2022-01-26 16:35:40.000000000 +0000
@@ -44,10 +44,10 @@
                    Set value of an option
 set error on|off|unset
                    Set value of an error
-set memory memory_type address data...
+set memory memory_type address data... or bitspec data
                    Place list of data into memory
-set bit addr 0|1   Set specified bit to 0 or 1
-set hardware cathegory params...
+set bit bitspec data   Set specified bit(s)
+set hardware category params...
                    Set parameters of specified hardware element
 

     Type of parameters
@@ -61,9 +61,10 @@
 0.s51> 
 

     Bit type
-    If parameter contains a dot (.) it is treated as bit specification. Part
-    before the dot gives memory address and part after the dot means bit number
-    in the specified data.
+    If a parameter contains a dot (.) or a colon contained in square brackets ([...:...])
+    it is treated as a bit specification. If there is a dot the part before the dot gives
+    the memory address and part after the dot gives the bit number. The bracketed form is
+    used to specify a range of bits.
     0> dump p1.1
       P1.1 0x90 ff 1
 0> dump 0x80.1
@@ -90,7 +91,7 @@
         style="font-family: monospace;">1 characters. In this case it
     is interpreted as binary number. If it begins with 0
     followed by digits it is interpreted as octal number. In other cases
-    it is interpreted as decimal number.
+    it is interpreted as decimal number.

     Symbol type
     If a command parameter can not be classified in other ways (doesn't start
     with a digit or a quote, doesn't contain dot or [) then it will be treated
@@ -126,14 +127,31 @@
     Bits can be specified by several ways. One way is using bit type of command
     parameter:
     0> dump 0.2
-    0x00.2 0x00 00 0
+    0x00000.2               0
 0> dump 0xc3.2
-    0xc3.2 0xc3 00 0
-0> dump p2.3
-      P2.3 0xa0 ff 1
+    0x000c3.2               1
+0> var a_reg rom[0x1000]
+0> dump a_reg[7:0]
+      0x01000      a_reg           0b11110111 0xf7 '.' 247 ( -9)
+0> dump a_reg[5:2]
+      0x01000[5:2] a_reg[5:2]      0b--1101-- 0x0d '.'  13 ( -3)
+0> var some_bits rom[0x1000][5:2]
+0> dump some_bits
+      0x01000[5:2] some_bits       0b--1101-- 0x0d '.'  13 ( -3)
+0> dump some_bits[4:3]
+      0x01000[4:3] a_reg[4:3]      0b---10--- 0x02 '.'   2 ( -2)
 0>
- In this way, any IRAM or SFR location can be addressed as the above
-    example shows.
+
+    Note that in the above the [4:3] overrides the
+    [5:2] defined for the var and some_bits[4:3]means
+    bits 4 through 3 of the value stored at 0x1000. It does not mean
+    take the bits defined by the var and then take a subset of those bits.
+    Note also that the output does not tell us we are looking at some_bit
+    (because we're not) but since we have a var set for the address as a whole
+    it does tell us that we are looking at a subset of a_reg.
+
+    In this way, any IRAM or SFR location can be addressed as the above
+    example shows.
     Other way is using bit address either by value or by symbolic name: 
     0> dump ea
      IE0.7 0xa8 00 0
@@ -173,7 +191,9 @@
 0> 
 
  Numbers must be integers (floating point is not supported) and not bigger
-    than the value which can be stored as long int.
+    than the value which can be stored as long int. Numbers can be
+    specified in ascii form too: 'a', result will be ascii code of the
+    character. This form accepts C style escapes, for example: '\n' or '\033'.
     Memory operands
     Memory can be an address space location or a memory chip cell. It can be
     specified in following form:
@@ -244,7 +264,7 @@
         
           Logical
           < > <= >= == !=
-          Comparision of two values
+          Comparison of two values
         
         
           && || ^^
@@ -336,7 +356,7 @@
     Output of any command can be redirected to a file. Same syntax can be used
     for this as for UNIX shell. The only difference is that μCsim
     doesn't allow to put redirection at the beginning of the command!
-    $ s51 remo.hex
+    $ ucsim_51 remo.hex
 uCsim 0.5.0-pre3, Copyright (C) 1997 Daniel Drotos, Talker Bt.
 uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
 This is free software, and you are welcome to redistribute it
@@ -355,7 +375,7 @@
 0x0038 d2 02 08 41 c0 82 c0 83 ...A....
 0x0040 c0 d0 c0 e0 c0 00 a2 90 ........
 0x0048 c0 d0 c2 90 78 18 06 30 ....x..0
-$ s51 remo.hex
+$ ucsim_51 remo.hex
 uCsim 0.5.0-pre3, Copyright (C) 1997 Daniel Drotos, Talker Bt.
 uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
 This is free software, and you are welcome to redistribute it
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/doc/testing.html sdcc-4.2.0+dfsg/sim/ucsim/doc/testing.html
--- sdcc-4.0.0+dfsg/sim/ucsim/doc/testing.html	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/doc/testing.html	2021-03-28 10:28:14.000000000 +0000
@@ -0,0 +1,152 @@
+
+  
+    
+    μCsim: Regression Testing
+  
+  
+    Regression Testing
+
+    Running Tests
+
+    If you are making changes to μCsim you should both run tests
+    to ensure nothing breaks and write new tests to ensure your changes
+    work and do not get broken in the future!
+    In all cases the tests are run using the locally built simulators.
+    i.e. you need to have completed a successful build before you can
+    test it! Tests produce output when run which is captured to a file
+    and compared with baseline output held in the source tree. If there
+    are any differences they are output and the test is considered
+    failed. In that case either the code needs to be changed to correct
+    the output or the baseline needs to be updated to reflect the new
+    expected output. Only when there are no differences to the baseline
+    can tests be said to have passed.
+
+    All Tests
+
+    To run all tests run make test in the top-level
+    ucsim directory.

+    E.g.:
+
+      
.../ucsim$ make test
+    
+
+    For a Single MCU
+
+    To run tests for a single MCU type run make test
+    in the directory for that simulator.

+    E.g.:
+
+      
.../ucsim/s51.src$ make test
+
+    or run make in the test subdirectory.

+    E.g.:
+
+      .../ucsim/s51.src/test$ make
+    
+
+    Note that tests for functionality generic to all simulators and that
+    does not depend on a particular MCU type lives in
+    sim.src/test and should be run there. These tests require
+    at least one simulator to have been built but unless there is only one
+    it is indeterminate which simulator will be used.
+
+    Running a Single Test
+    To run a single test run make test_name
+    in the test subdirectory of the relevant simulator. E.g.:
+
+      
.../ucsim/s51.src/test$ make config
+
+    In this case the test is run verbosely and the commands executed by make
+    are displayed. In all other cases only the final differences to baseline
+    (if any) are displayed.
+
+    Updating the Baselines
+    If changes to the simulator code base lead to changes in test outputs
+    and these changes are as expected then the baselines should be
+    updated to match the new output by copying the contents of the out
+    directories to the corresponding baseline directories.
+
+    To update all baselines run make baseline in the top-level
+    ucsim directory.

+
+    
To update baselines for a single MCU type run make baseline
+    in the directory for that simulator.

+
+    
If you need to update the baseline for a single test you should copy the
+    relevant files manually.
+
+    Remember that the updated baselines form part of your changes and
+    need to be committed or submitted as part of your patch!
+
+    Writing Tests
+
+    
+        Create a directory named after your test under the relevant simulator's
+            test directory:
+        
+
+        Place the data needed for your test, .cmd files, .asm
+            or C files etc, in your test directory:
+        
+
+        Create a baseline directory in your test directory:
+        
+
+        Create an empty file in the baseline directory for each
+            output that your test generates:
+        
+
+        Create a Makefile that lists the output(s) to be generated,
+            the recipes to create them and which includes test-lib.mk:
+        
+
+        Run your test, verify the contents of the out directory
+            and then copy it to the baseline directory:
+        
+    
+
+    +.../ucsim/s51.src/test$ mkdir name
+.../ucsim/s51.src/test$ cd name
+.../ucsim/s51.src/test/name$ vim test.{cmd,asm}
+.../ucsim/s51.src/test/name$ mkdir baseline
+.../ucsim/s51.src/test/name$ touch baseline/stdout
+.../ucsim/s51.src/test/name$ cat > Makefile <<EOF
+OUTPUTS = stdout
+
+stdout: mytest.ihx mytest.cmd
+        $(call run-sim)
+
+include test-lib.mk
+EOF
+.../ucsim/s51.src/test/name$ cd ..
+.../ucsim/s51.src/test$ make name
+.../ucsim/s51.src/test$ cp -r name/out name/baseline/.
+
+    test-lib.mk takes care of building any .ihx files
+    needed from corresponding .asm or .c files.
+    The call to run-sim will invoke the simulator with the
+    .ihx and .cmd prerequisites, capturing the
+    output.
+
+    If there are no .cmd prerequisites and there is no
+    -e in the arguments to run-sim it
+    will add a -g argument to start the simulator running.
+    It is assumed there is at least one .ihx file in the
+    prerequisites in this case and that it places code at the reset
+    address.
+
+    If you wish to pass arguments of your own to the simulator these
+    can be given as arguments to run-sim. This can be used to pass commands
+    with the -e option rather than using a .cmd file
+    for instance, as is done with the config tests.
+
+    If you create any other output from within the simulator you should
+    specify a pathname starting with out/. Anything written
+    to the out directory will be compared to the baseline
+    when the test is complete.
+    
+
+    
+  
+
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/doc/ucsim.1 sdcc-4.2.0+dfsg/sim/ucsim/doc/ucsim.1
--- sdcc-4.0.0+dfsg/sim/ucsim/doc/ucsim.1	2019-07-02 08:44:01.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/doc/ucsim.1	2022-01-15 21:15:29.000000000 +0000
@@ -1,37 +1,87 @@
 .TH UCSIM 1
+
 .SH NAME
 uCsim \- Micro\-controller simulator
+
 .SH SYNOPSIS
-.B s51|sz80|savr|sxa|shc08|spdk|sst7|sstm8|stlc
-.BR \-t type
-.BR \-X freq[k|M]
-.BR \-C file
-.BR \-e command
-.BR \-c file
-.BR \-Z portnum
-.BR \-s file
-.BR \-S options
-.BR \-I options
-.BR \-p prompt
-.BR \-P
-.BR \-g
-.BR \-G
-.BR \-a nr
-.BR \-w
-.BR \-V
-.BR \-H
-.BR \-h
+.B ucsim_51
+.br
+.B ucsim_xa
+.br
+.B ucsim_z80
+.br
+.B ucsim_tlc
+.br
+.B ucsim_rxk
+.br
+.B ucsim_avr
+.br
+.B ucsim_pdk
+.br
+.B ucsim_st7
+.br
+.B ucsim_stm8
+.br
+.B ucsim_p1516
+.br
+.B ucsim_m6800
+.br
+.B ucsim_m6809
+.br
+.B ucsim_m68hc08
+.br
+.B ucsim_m68hc11
+.br
+.B ucsim_mos6502
+.br
+.B ucsim_plaze
+.br
+.RS
+.B \-t cpu_type
+.B \-X freq[k|M]
+.B \-R seed
+.B \-C cfg_file
+.B \-e command
+.B \-c file
+.B \-Z portnum
+.B \-k portnum
+.B \-s file
+.B \-S options
+.B \-I options
+.B \-p prompt
+.B \-P
+.B \-o colors
+.B \-l
+.B \-b
+.B \-B
+.B \-g
+.B \-G
+.B \-a nr
+.B \-w
+.B \-V
+.B \-v
+.B \-H
+.B \-h
+.RE
+
 .SH DESCRIPTION
-.I s51
-command is used to simulate MCS51 controller family.
-.I sz80
-command is Z80 simulator.
-.PP
+uCsim is a microcontroller, microprocessor simulator for several
+processor familes. It can be started as
+.B ucsim_XXXX
+command, where XXXX specifies the simulated processor type. Eg.
+.I ucsim_51
+starts Intel MCS51 microcontroller simulator,
+.I ucsim_z80
+starts Zilog Z80 microprocessor simulator, etc.
+
+.SH OPTIONS
+
 .B Options of the command
+
 .TP
-.B \-t type
+.B \-t cpu_type
 Specifies type of the controller. Use \-H to list possible values.
-.PP
+
 .TP
 .B \-X freq[k|M]
 XTAL frequency in Hz, Use
@@ -39,42 +89,47 @@
 or
 .I M
 suffix to specify frequency in kHz or MHz.
-.PP
+
+.TP
+.B \-R seed
+Set the random number generator seed.
+
 .TP
 .B \-C file
 Read initial commands from
 .I file
 and execute them.
-.PP
+
 .TP
 .B \-e command
 Execute
 .I command
 at program startup (before config file).
-.PP
+
 .TP
 .B \-c file
 Open command console on
 .I file
 (use \- for std in/out).
-.PP
+
 .TP
 .B \-Z portnum
 Use
 .I localhost:portnum
-for command console
-.PP
+for command console.
+
 .TP
 .B \-k portnum
 Use
 .I localhost:portnum
-for serial I/O
-.PP
+for serial I/O. This option is obsolete, use \-S instead.
+
 .TP
 .B \-s file
 Connect serial interface uart0 to
 .I file
-.PP
+This option is obsolete, use \-S instead.
+
 .TP
 .B \-S options
 .I options
@@ -84,90 +139,106 @@
 number of uart (default=0)
 .br
 .I in=file
-serial input will be read from file named `file'
+serial input will be read from file named `file'.
 .br
 .I out=file
-serial output will be written to `file'
+serial output will be written to `file'.
 .br
 .I port=nr
-Use localhost:nr as server for serial line
+Use localhost:nr as server for serial line.
 .br
 .I iport=nr
-Use localhost:nr as server for serial input
+Use localhost:nr as server for serial input.
 .br
 .I oport=nr
-Use localhost:nr as server for serial onput
-.PP
+Use localhost:nr as server for serial onput.
+
 .TP
 .B \-I options
 .I options
-is a comma separated list of options according to simulator interface. Known options are:
+is a comma separated list of options according to simulator
+interface. Known options are:
 .br
 .I if=memory[address]
-turn on interface on given memory location
+turn on interface on given memory location.
 .br
 .I in=file
-specify input file for IO
+specify input file for IO.
 .br
 .I out=file
-specify output file for IO
+specify output file for IO.
 .PP
+
 .TP
 .B \-p prompt
-Specify string for prompt
-.PP
+Specify string for prompt.
+
 .TP
 .B \-P
-Prompt is a null ('\\0') character
+Prompt is a null ('\\0') character.
 .PP
+
 .TP
 .B \-o colors
 List of color specification: what=colspec,... where colspec is :
 separated list of color options e.g.: prompt=b:white:black (bold white
-on black)
+on black).
+
+.TP
+.B \-l
+Use colors of the light theme (default is dark).
 .PP
+
 .TP
 .B \-b
-Black & white (non-color) console
-.PP
+Black & white (non-color) console.
+
+.TP
+.B \-B
+Beep on breakpoints.
+
 .TP
 .B \-g
-Go, start simulation
-.PP
+Go, start simulation.
+
 .TP
 .B \-G
-Go, start simulation, quit on stop
-.PP
+Go, start simulation, quit on stop.
+
 .TP
 .B \-a nr
-Specify size of variable space (default=256)
-.PP
+Specify size of variable space (default=256).
+
 .TP
 .B \-w
-Writable flash
-.PP
+Writable flash.
+
 .TP
 .B \-V
-Verbose mode
-.PP
+Verbose mode.
+
 .TP
 .B \-v
-Print out version number and quit
-.PP
+Print out version number and quit.
+
 .TP
 .B \-H
-Print out types of known CPUs and quit
-.PP
+Print out types of known CPUs and quit.
+
 .TP
 .B \-h
-Print out this help and quit
+Print out this help and quit.
+
 .SH EXAMPLES
 None yet.
+
 .SH "SEE ALSO"
-sdcc(1), sdcdb(1).
+sdcc(1), sdcdb(1), serialview(1).
+
 .SH BUGS
 Probably many.
-.SH AUTHORS
+
+.SH AUTHORS, CONTRIBUTORS
 Daniel Drotos,
 Gunar Holm,
 Sandeep Dutta,
@@ -184,4 +255,12 @@
 Alexis Pavlov,
 Davine Zanni,
 Anton Persson,
-Nicolas Lesser
+Nicolas Lesser,
+Mike Jagdis,
+Jiri Simek,
+Zbynek Krivka,
+Vaclav Peroutka,
+Valentin Dudouyt,
+Erik Petrich,
+Leland Morrison,
+Johan Knol.
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/doc/vcd.html sdcc-4.2.0+dfsg/sim/ucsim/doc/vcd.html
--- sdcc-4.0.0+dfsg/sim/ucsim/doc/vcd.html	2019-07-02 08:44:01.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/doc/vcd.html	2022-02-02 07:12:49.000000000 +0000
@@ -3,45 +3,192 @@
     
     μCsim: VCD file dumper
   
-  
-    VCD file dumper
-    1. specify output file:

-      

-      0> set hw vcd[0] file "name.vcd"

-      

-      2. add locations to dump (sorry, I didn't remember correctly, bits can not
-      be dumped yet):

-      

-      0> set hw vcd[0] add pc_odr

-      0> set hw vcd[0] add rom[0x500a]

-      

-      You can set the name of the module if you want (set hw vcd[0] module
-      name), it will be

-      ucsim_vcd_0 by default.

-      

-      3. start recording:

-      

-      0> set hw vcd[0] start

-      

-      4. run the program
-    5. you can suspend/resume recording:

-      

-      0> set hw vcd[0] pause

-      0> set hw vcd[0] restart

-      

-      You can create an additional recorder with "set hw vcd[0] new id" and
-      setup it with "set

-      hw vcd[id] ..." commands ("id" must be a number).

-      

-      6. stop recording and close the vcd file:

-      

-      0> set hw vcd[0] stop

-      

-      After "stop", you have to specify a new file, because "start" overwrites
-      the old one!

-      

-      For examine, I use gtkwave on linux.

-    
-    
+  
+    VCD file I/O
+
+      Initially there is one vcd defined called "vcd[0]" (or just "vcd").
+      You can create an additional vcds with "set hw vcd[0] new id" and
+      configure it with "set hw vcd[id] ..." commands ("id" must
+      be an integer).
+
+    Output (event logging)
+
+      The vcd module creates VCD files compatible with industry standards and
+      readable with open source tools such as gtkwave and sigrok/pulseview.
+      (N.B. sigrok/pulseview only supports VCD files containing events that
+      are 1 bit wide only.)
+
+      
+        Specify output file

+          +          0> set hw vcd[0] output "name.vcd"
+          
+          Alternatively specify no, or an empty, output file or use the
+          "view" command and the simulator will attempt to invoke
+          gtkwave
+          directly.
+          +          0> set hw vcd[0] output ""
+          0> set hw vcd[0] view
+          
+        
+
+        Add locations to dump

+          +          0> set hw vcd[0] add pc_odr
+          0> set hw vcd[0] add rom[0x500a].3
+          
+          You can set the name of the module if you want (set hw vcd[0] module
+          name), it will be ucsim_vcd_0 by default.

+          

+        
+
+        Check the configuration

+          +          0> info hw vcd[0]
+          vcd[0] value change dump
+            Modul:      ucsim_vcd_0
+            Started:    no
+            Paused:     no
+            File:       name.vcd
+            Mode:       output
+            Time scale: auto set on start
+            Start time: 0.000000000000000 s
+            Last event: 0.000000000000000 s
+            Simul time: 0.000000000000000 s
+            Variables:
+              Address           Symbol
+              rom[0x0500a][7:0] pc_odr
+              rom[0x0500a].3
+          
+        
+
+        Start recording

+          +          0> set hw vcd[0] start
+          
+        
+
+        Run the program

+          

+        
+
+        You can pause/resume recording

+          +          0> set hw vcd[0] pause
+          0> set hw vcd[0] restart
+          
+          While the vcd is paused no changes are recorded in the
+          output and values will show as unknown when the VCD is viewed
+          by something such as
+	  gtkwave.
+	  If you set pausetime then the time recorded as unknown
+	  will be limited to the specified time and time beyond that
+	  will simply not exist as far as the VCD is concerned.
+	  This may be used to compress pause gaps in the VCD for the
+	  sake of viewers which are not able to do this themselves.
+          +          0> set hw vcd[0] pausetime 300 ns
+          
+        
+
+        Stop recording and close the VCD file

+          +          0> set hw vcd[0] stop
+          
+        
+      
+
+    Input (event replay)
+
+      
+        Define any variables used by the input file

+          +          0> var loc1 rom[0x5001]
+          
+        
+
+        Specify input file

+          +          0> set hw vcd[0] input "name.vcd"
+          
+        
+
+        Adjust the base time

+          By default time 0 in the VCD file corresponds to the simulator time
+          when the vcd is started. You can adjust this by setting the start time
+          of the vcd. For instance, to move the VCD events 750 ns into the future
+          you would use
+          +          0> set hw vcd[0] starttime 750 ns
+          
+          This can be done at any time, regardless of whether the vcd is started,
+          paused or even part way through.
+          Note that the argument to starttime is the amount to add or subtract
+          from the current start time not an absolute time.
+          

+        
+
+        Start the replay

+          +          0> set hw vcd[0] start
+          +        
+
+        Check the configuration

+          N.B. The VCD file's header is only parsed when the vcd is started.
+          Until then the configuration details are unknown.

+          +          0> info hw vcd[0]
+          vcd[0] value change dump
+            Modul:      ucsim_vcd_0
+            Started:    YES
+            Paused:     no
+            File:       name.vcd
+            Mode:       input
+            Break:      disabled
+            Time scale: 1 ns
+            Start time: 0.000000000000000 s
+            Next event: 0.000000000000000 s
+            Simul time: 0.000000000000000 s
+            Variables:
+              Address           Symbol
+              rom[0x0500a]      pc_odr
+              rom[0x0500a].3
+          
+        
+
+        Run the program

+          

+        
+
+        Pause/resume replay

+          +          0> set hw vcd[0] pause
+          0> set hw vcd[0] restart
+          
+          While the replay is paused any cycles used by the simulator
+          are ignored by vcd and do NOT advance you towards the next
+          event.
+          

+        
+
+        Toggle the break flag as required

+          +          0> set hw vcd[0] break
+          
+          The break flag causes vcd to generate a break each an event
+          is replayed giving you the opportunity to check that your program
+          responds to it correctly.
+          

+        
+
+        Stop the replay and close the VCD file

+          +          0> set hw vcd[0] stop
+          
+        
+      
+
   
 
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/error.cc sdcc-4.2.0+dfsg/sim/ucsim/error.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/error.cc	2016-07-26 21:10:26.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/error.cc	2020-08-22 10:25:08.000000000 +0000
@@ -107,10 +107,10 @@
   return(name);
 }*/
 
-char *
-cl_error_class::get_type_name()
+const char *
+cl_error_class::get_type_name(void)
 {
-  return(get_id_string(error_type_names, type, /*cchars*/((char*)"untyped")));
+  return(get_id_string(error_type_names, type, "untyped"));
   /*switch (type)
     {
     case err_unknown: return("unclassified"); break;
@@ -127,7 +127,7 @@
 cl_error::cl_error(void):
   cl_base()
 {
-  classification= error_registry.find(/*cchars*/("non-classified"));
+  classification= error_registry.find("non-classified");
 
 }
 
@@ -168,20 +168,20 @@
 void
 cl_error::print(class cl_commander_base *c)
 {
-  c->dd_printf(cchars("%s\n"), get_type_name());
+  c->dd_cprintf("error", "%s\n", get_type_name());
 }
 
-char *
-cl_error::get_type_name()
+const char *
+cl_error::get_type_name(void)
 {
   enum error_type type= get_type();
-  return(get_id_string(error_type_names, type, /*cchars*/((char*)"untyped")));
+  return(get_id_string(error_type_names, type, "untyped"));
 }
 
 cl_error_registry::cl_error_registry(void)
 {
-  if (NULL == error_registry.find(/*cchars*/("non-classified")))
-    register_error(new cl_error_class(err_error, /*cchars*/("non-classified"), ERROR_ON));
+  if (NULL == error_registry.find("non-classified"))
+    register_error(new cl_error_class(err_error, "non-classified", ERROR_ON));
 }
 
 /* End of sim.src/error.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/errorcl.h sdcc-4.2.0+dfsg/sim/ucsim/errorcl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/errorcl.h	2016-07-26 21:10:26.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/errorcl.h	2022-01-27 21:35:29.000000000 +0000
@@ -61,7 +61,7 @@
   void set_on(enum error_on_off val);
   bool is_on(void);
   enum error_type get_type(void);
-  char *get_type_name(void);
+  const char *get_type_name(void);
   //char *get_name(void);
 };
 
@@ -73,7 +73,7 @@
   {
     if (0 == registered_errors)
       return 0;
-    return static_cast(registered_errors->first_that(compare, static_cast((void*)type_name)));
+    return static_cast(registered_errors->first_that(compare, static_cast(type_name)));
   }
   static class cl_list *get_list(void)
   {
@@ -84,16 +84,16 @@
   class cl_error_class *register_error(class cl_error_class *error_class)
   {
     if (!registered_errors)
-      registered_errors= new cl_list(2, 2, /*cchars*/("registered errors"));
+      registered_errors= new cl_list(2, 2, "registered errors");
     registered_errors->add(error_class);
     return error_class;
   }
   
 private:
   static class cl_list *registered_errors;
-  static int compare(void *obj1, void *obj2)
+  static int compare(const void *obj1, const void *obj2)
   {
-    return (static_cast(obj1))->is_named(static_cast(obj2));
+    return (static_cast(obj1))->is_named(static_cast(obj2));
   }
 };
 
@@ -104,7 +104,7 @@
 protected:
   class cl_error_class *classification;
 public:
-  bool inst;	// Occured during instruction execution
+  bool inst;	// Occurred during instruction execution
   t_addr PC;	// Address of the instruction
 public:
   cl_error(void);
@@ -118,7 +118,7 @@
   virtual class cl_error_class *get_class(void) { return(classification); }
 
   virtual void print(class cl_commander_base *c);
-  virtual char *get_type_name();
+  virtual const char *get_type_name(void);
 };
 
 
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/fio.cc sdcc-4.2.0+dfsg/sim/ucsim/fio.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/fio.cc	2019-07-02 08:44:01.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/fio.cc	2021-11-02 13:14:45.000000000 +0000
@@ -28,16 +28,17 @@
 #include "ddconfig.h"
 
 #include 
-#include 
+//#include 
 #include 
 #include 
 #include HEADER_FD
-#include 
+//#include 
 #include 
 #if defined HAVE_SYS_SOCKET_H
 # include 
 # include 
 # include 
+# include 
 #endif
 #include 
 #include 
@@ -77,27 +78,27 @@
 {
 }
 
-char *
+const char *
 cl_history::up(chars line)
 {
   replace(line);
   if (nr > 0)
     nr--;
-  return (char*)(Items[nr]);
+  return (char*)Items[nr];
 }
 
-char *
+const char *
 cl_history::down(chars line)
 {
   replace(line);
   if (nr < count)
     nr++;
   if (nr < count)
-    return (char*)(Items[nr]);
+    return (char*)Items[nr];
   return NULL;
 }
 
-char *
+void
 cl_history::enter(chars line)
 {
   if (count > 1000)
@@ -111,7 +112,6 @@
       add(strdup(line));
       nr= count;
     }
-  return NULL;
 }
 
 void
@@ -140,7 +140,7 @@
   server_port= -1;
   echo_of= NULL;
   echo_to= NULL;
-  echo_color= (char*)"";
+  echo_color= "";
   at_end= 0;
   last_used= first_free= 0;
   cooking= 0;
@@ -164,7 +164,7 @@
   server_port= -1;
   echo_of= NULL;
   echo_to= NULL;
-  echo_color= (char*)"";
+  echo_color= "";
   at_end= 0;
   last_used= first_free= 0;
   cooking= 0;
@@ -186,7 +186,7 @@
   server_port= the_server_port;
   echo_of= NULL;
   echo_to= NULL;
-  echo_color= (char*)"";
+  echo_color= "";
   at_end= 0;
   last_used= first_free= 0;
   cooking= 0;
@@ -201,13 +201,13 @@
 class cl_f *
 cl_f::copy(chars mode)
 {
-  class cl_f *io= mk_io(chars(""), chars(""));
+  class cl_f *io= mk_io("", "");
   io->use_opened(file_id, mode);
   return io;
 }
 
 static int
-open_flags(char *m)
+open_flags(const char *m)
 {
   if (strcmp(m, "r") == 0)
     return O_RDONLY;
@@ -230,6 +230,12 @@
   if (server_port > 0)
     {
       file_id= mk_srv_socket(server_port);
+      if (file_id <= 0)
+	{
+	  file_id= -1;
+	  own= false;
+	  return -1;
+	}
       listen(file_id, 50);
       own= true;
       tty= false;
@@ -238,7 +244,7 @@
   else if (!file_name.empty())
     {
       if (file_mode.empty())
-	file_mode= cchars("r+");
+	file_mode= "r+";
       if ((file_id= ::open(file_name, open_flags(file_mode), (S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH))) >= 0)
 	{
 	  tty= isatty(file_id);
@@ -256,13 +262,13 @@
 }
 
 int
-cl_f::use_opened(int opened_file_id, char *mode)
+cl_f::use_opened(int opened_file_id, const char *mode)
 {
   close();
   if (mode)
     file_mode= mode;
   else
-    file_mode= cchars("r+");
+    file_mode= "r+";
   own= false;
   if (opened_file_id >= 0)
     {
@@ -274,7 +280,7 @@
 }
 
 int
-cl_f::own_opened(int opened_file_id, char *mode)
+cl_f::own_opened(int opened_file_id, const char *mode)
 {
   use_opened(opened_file_id, mode);
   own= true;
@@ -282,7 +288,7 @@
 }
 
 int
-cl_f::use_opened(FILE *f, chars mode)
+cl_f::use_opened(FILE *f, const char *mode)
 {
   close();
   if (f)
@@ -301,7 +307,7 @@
 }
 
 int
-cl_f::own_opened(FILE *f, chars mode)
+cl_f::own_opened(FILE *f, const char *mode)
 {
   use_opened(f, mode);
   own= true;
@@ -309,7 +315,7 @@
 }
 
 int
-cl_f::open(char *fn)
+cl_f::open(const char *fn)
 {
   close();
   if (fn)
@@ -318,7 +324,7 @@
 }
 
 int
-cl_f::open(char *fn, char *mode)
+cl_f::open(const char *fn, const char *mode)
 {
   close();
   if (mode)
@@ -698,7 +704,7 @@
   // HISTORY
   else if (k == TU_UP)
     {
-      char *s= hist->up(line);
+      const char *s= hist->up(line);
       if (cursor > 0)
 	echo_cursor_go_left(cursor);
       echo_cursor_save();
@@ -715,7 +721,7 @@
     }
   else if (k == TU_DOWN)
     {
-      char *s= hist->down(line);
+      const char *s= hist->down(line);
       if (cursor > 0)
 	echo_cursor_go_left(cursor);
       echo_cursor_save();
@@ -771,8 +777,7 @@
 	  echo_cursor_restore();
 	}
     }
-  else if (//(k == 127) || /*DEL*/
-	   (k == TU_DEL))
+  else if (k == TU_DEL)
     {
       if (line[cursor] != 0)
 	{
@@ -847,7 +852,7 @@
       at_end= 1;
     }
   if (i < 0)
-    ;
+    {}
   return i;
 }
 
@@ -964,7 +969,7 @@
 
 
 int
-cl_f::write(char *buf, int count)
+cl_f::write(const char *buf, int count)
 {
   int i;
   if (file_id >= 0)
@@ -982,13 +987,13 @@
 	    {
 	      j= ::write(file_id, "\r\n", 2);
 	      if (j != 2)
-		;
+	        {}
 	    }
 	  else
 	    {
 	      j= ::write(file_id, &buf[i], 1);
 	      if (j != 1)
-		;
+	        {}
 	    }
 	}
       return i;
@@ -998,7 +1003,7 @@
 
 
 int
-cl_f::write_str(char *s)
+cl_f::write_str(const char *s)
 {
   if (!s ||
       !*s)
@@ -1008,15 +1013,6 @@
 
 
 int
-cl_f::write_str(const char *s)
-{
-  if (!s ||
-      !*s)
-    return 0;
-  return write((char*)s, strlen((char*)s));
-}
-
-int
 cl_f::vprintf(const char *format, va_list ap)
 {
   char *s= vformat_string(format, ap);
@@ -1060,7 +1056,7 @@
 {
   if (echo_to)
     {
-      echo_to->write(cchars("\033[s"), 3);
+      echo_to->write("\033[s", 3);
       //echo_to->flush();
     }
 }
@@ -1070,7 +1066,7 @@
 {
   if (echo_to)
     {
-      echo_to->write(cchars("\033[u"), 3);
+      echo_to->write("\033[u", 3);
       //echo_to->flush();
     }
 }
@@ -1100,36 +1096,24 @@
 }
 
 void
-cl_f::echo_write(char *b, int l)
+cl_f::echo_write(const char *b, int l)
 {
   if (echo_to)
     {
       if (echo_color.nempty())
-	echo_to->prntf("%s", (char*)echo_color);
+	echo_to->prntf("%s", echo_color.c_str());
       echo_to->write(b, l);
       //echo_to->flush();
     }
 }
 
 void
-cl_f::echo_write_str(char *s)
-{
-  if (echo_to)
-    {
-      if (echo_color.nempty())
-	echo_to->prntf("%s", (char*)echo_color);
-      echo_to->write_str(s);
-      //echo_to->flush();
-    }
-}
-
-void
 cl_f::echo_write_str(const char *s)
 {
   if (echo_to)
     {
       if (echo_color.nempty())
-	echo_to->prntf("%s", (char*)echo_color);
+	echo_to->prntf("%s", echo_color.c_str());
       echo_to->write_str(s);
       //echo_to->flush();
     }
@@ -1233,7 +1217,7 @@
 }
 
 
-chars
+const char *
 fio_type_name(enum file_type t)
 {
   switch (t)
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/fiocl.h sdcc-4.2.0+dfsg/sim/ucsim/fiocl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/fiocl.h	2019-07-02 08:44:01.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/fiocl.h	2020-08-22 10:25:08.000000000 +0000
@@ -100,9 +100,9 @@
   virtual ~cl_history(void);
 
  public:
-  char *up(chars line);
-  char *down(chars line);
-  char *enter(chars line);
+  const char *up(chars line);
+  const char *down(chars line);
+  void enter(chars line);
   void replace(chars line);
 };
 
@@ -140,20 +140,20 @@
   virtual class cl_f *copy(chars mode);
   virtual int init(void);
   //virtual int open(void) { return init(); }
-  virtual int open(char *fn);
-  virtual int open(char *fn, char *mode);
-  virtual int use_opened(int opened_file_id, char *mode);
-  virtual int own_opened(int opened_file_id, char *mode);
-  virtual int use_opened(FILE *f, chars mode);
-  virtual int own_opened(FILE *f, chars mode);
+  virtual int open(const char *fn);
+  virtual int open(const char *fn, const char *mode);
+  virtual int use_opened(int opened_file_id, const char *mode);
+  virtual int own_opened(int opened_file_id, const char *mode);
+  virtual int use_opened(FILE *f, const char *mode);
+  virtual int own_opened(FILE *f, const char *mode);
   virtual enum file_type determine_type(void)= 0;
   virtual void changed(void);
   virtual int close(void);
   virtual int stop_use(void);
   virtual bool opened(void) { return file_id >= 0; }
   
-  virtual char *get_file_name() { return file_name; };
-  virtual char *get_fname() { return file_name; };
+  virtual const char *get_file_name() { return file_name; };
+  virtual const char *get_fname() { return file_name; };
   virtual class cl_f *get_echo_to() { return echo_to; }
  protected:
   virtual int put(int c);
@@ -179,8 +179,7 @@
 
   virtual int check_dev(void)= 0;
   virtual int read_dev(int *buf, int max);
-  virtual int write(char *buf, int count);
-  virtual int write_str(char *s);
+  virtual int write(const char *buf, int count);
   virtual int write_str(const char *s);
   virtual int vprintf(const char *format, va_list ap);
   virtual int prntf(const char *format, ...);
@@ -191,8 +190,7 @@
   virtual void echo_cursor_restore();
   virtual void echo_cursor_go_left(int n);
   virtual void echo_cursor_go_right(int n);
-  virtual void echo_write(char *b, int l);
-  virtual void echo_write_str(char *s);
+  virtual void echo_write(const char *b, int l);
   virtual void echo_write_str(const char *s);
   virtual void set_echo_color(chars col);
   virtual chars get_echo_color() { return echo_color; }
@@ -223,8 +221,8 @@
 
 extern int mk_srv_socket(int port);
 
-extern class cl_f *mk_io(chars fn, chars mode);
-extern class cl_f *cp_io(/*FILE *f*/int file_id, chars mode);
+extern class cl_f *mk_io(const char *fn, const char *mode);
+extern class cl_f *cp_io(/*FILE *f*/int file_id, const char *mode);
 extern class cl_f *mk_srv(int server_port);
 extern int srv_accept(class cl_f *listen_io,
 		      class cl_f **fin, class cl_f **fout);
@@ -234,7 +232,7 @@
 extern void msleep(int msec);
 extern void loop_delay();
 
-extern chars fio_type_name(enum file_type t);
+extern const char *fio_type_name(enum file_type t);
 extern void  sigpipe_off();
 
 
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/ftest.cc sdcc-4.2.0+dfsg/sim/ucsim/ftest.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/ftest.cc	2016-07-26 21:10:26.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/ftest.cc	2020-08-22 10:25:08.000000000 +0000
@@ -7,19 +7,19 @@
 
 
 void
-regular_ftest(char *fn)
+regular_ftest(const char *fn)
 {
   int i;
   class cl_f *f;
 
   printf("Testing regular file access: %s\n", fn);
   printf("Write test\n");
-  f= mk_io(fn, cchars("w"));
+  f= mk_io(fn, "w");
   f->init();
   f->write_str("proba\n");
 
   printf("Read test\n");
-  f->open(fn, cchars("r"));
+  f->open(fn, "r");
   while (f->input_avail())
     {
       char buf[100];
@@ -44,7 +44,7 @@
   int i, p= 0, done= 0;
 
   printf("STDIN test\n");
-  f->use_opened(0, (char*)"r");
+  f->use_opened(0, "r");
   printf("istty= %d\n", f->tty);
   i= f->read(buf, 99);
   buf[i]= '\0';
@@ -76,12 +76,12 @@
 int
 main(int argc, char *argv[])
 {
-  char *fn;
+  const char *fn;
 
   if (argc > 1)
     fn= argv[1];
   else
-    fn= (char*)"ftest.txt";
+    fn= "ftest.txt";
   regular_ftest(fn);
   stdin_ftest();
   
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/fuio.cc sdcc-4.2.0+dfsg/sim/ucsim/fuio.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/fuio.cc	2019-03-18 19:13:38.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/fuio.cc	2021-10-29 17:39:15.000000000 +0000
@@ -13,10 +13,12 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
 #include 
+#include 
 
 #include "utils.h"
 
@@ -28,22 +30,21 @@
 void deb(const char *format, ...)
 {
   return;
+  /*
   if (dd==NULL)
     {
-      dd= mk_io(/*cchars("/dev/pts/2"),cchars("w")*/"","");
+      dd= mk_io("", "");
       dd->file_id= open("/dev/pts/4", O_WRONLY);
-      //dd->init();
     }
   va_list ap;
   va_start(ap, format);
-  //dd->vprintf(format, ap);
-  //vdprintf(dd->file_id, format, ap);
   {
     char *buf= vformat_string(format, ap);
-    /*dd->*/write(dd->file_id, buf, strlen(buf));
+    write(dd->file_id, buf, strlen(buf));
     free(buf);
   }
   va_end(ap);
+  */
 }
 
 
@@ -71,19 +72,12 @@
       restore_attributes();
       shutdown(file_id, 2/*SHUT_RDWR*/);
     }
-  /*
-  if (file_f)
-    {
-      restore_attributes();
-      i= fclose(file_f);
-    }
-    else*/ if (file_id >= 0)
+  if (file_id >= 0)
     {
       restore_attributes();
       i= ::close(file_id);
     }
 
-  //file_f= NULL;
   file_id= -1;
   own= false;
   file_name= 0;
@@ -99,7 +93,7 @@
   restore_attributes();
   if (echo_of != NULL)
     echo_of->echo(NULL);
-  if (/*file_f*/file_id>=0)
+  if (file_id>=0)
     {
       if (own)
 	close();
@@ -258,7 +252,7 @@
 
   /* Give the socket a name. */
   i= 1;
-  if (setsockopt(sock, SOL_SOCKET, SO_REUSEADDR, (char*)&i, sizeof(i)) < 0)
+  if (setsockopt(sock, SOL_SOCKET, SO_REUSEADDR, (void*)&i, sizeof(i)) < 0)
     {
       perror("setsockopt");
     }
@@ -268,6 +262,7 @@
   if (bind(sock, (struct sockaddr *)&name, sizeof(name)) < 0)
     {
       perror("bind");
+      close(sock);
       return(0);
     }
 
@@ -276,11 +271,11 @@
 
 
 class cl_f *
-mk_io(chars fn, chars mode)
+mk_io(const char *fn, const char *mode)
 {
   class cl_io *io;
 
-  if (fn.empty())
+  if (!fn || !*fn)
     {
       io= new cl_io();
       io->init();
@@ -299,13 +294,13 @@
 }
 
 class cl_f *
-cp_io(/*FILE *f*/int file_id, chars mode)
+cp_io(int file_id, const char *mode)
 {
   class cl_io *io;
 
   io= new cl_io();
-  if (/*f*/file_id>=0)
-    io->use_opened(/*fileno(f)*/file_id, mode);
+  if (file_id>=0)
+    io->use_opened(file_id, mode);
   return io;
 }
 
@@ -326,19 +321,16 @@
 	   class cl_f **fin, class cl_f **fout)
 {
   class cl_io *io;
-  //ACCEPT_SOCKLEN_T size;
-  //struct sockaddr_in sock_addr;
   int new_sock;
 
-  //size= sizeof(struct sockaddr);
-  new_sock= accept(listen_io->file_id, /*(struct sockaddr *)sock_addr*/NULL, /*&size*/NULL);
+  new_sock= accept(listen_io->file_id, NULL, NULL);
   
   if (fin)
     {
       io= new cl_io(listen_io->server_port);
       if (new_sock > 0)
 	{
-	  io->own_opened(new_sock, cchars("r"));
+	  io->own_opened(new_sock, "r");
 	}
       *fin= io;
     }
@@ -348,7 +340,7 @@
       io= new cl_io(listen_io->server_port);
       if (new_sock > 0)
 	{
-	  io->use_opened(new_sock, cchars("w"));
+	  io->use_opened(new_sock, "w");
 	}
       *fout= io;
     }
@@ -381,7 +373,9 @@
 	  ret= true;
 	}
       else
-	;//deb("no dev input on fid=%d\n", fio->file_id);
+        {
+          //deb("no dev input on fid=%d\n", fio->file_id);
+        }
     }
   return ret;
 }
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/fwio.cc sdcc-4.2.0+dfsg/sim/ucsim/fwio.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/fwio.cc	2019-03-18 19:13:38.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/fwio.cc	2020-11-20 07:26:04.000000000 +0000
@@ -26,7 +26,7 @@
   return;
   /*if (dd==NULL)
     {
-      dd= cp_io(stdout,cchars("w"));
+      dd= cp_io(stdout,"w");
       dd->init();
       }*/
   va_list ap;
@@ -370,7 +370,7 @@
   if (server_port > 0)
     {
       //printf("win opened socket id=%d\n", file_id);
-      handle= (void*)file_id;
+      handle= (void *)file_id;
       type= F_SOCKET;
       deb("assuming TTY on socket %d\n", file_id);
       tty= true;
@@ -455,11 +455,11 @@
 
 
 class cl_f *
-mk_io(chars fn, chars mode)
+mk_io(const char *fn, const char *mode)
 {
   class cl_io *io;
 
-  if (fn.empty())
+  if (!fn || !*fn)
     {
       io= new cl_io();
       io->init();
@@ -482,7 +482,7 @@
 }
 
 class cl_f *
-cp_io(/*FILE *f*/int file_id, chars mode)
+cp_io(/*FILE *f*/int file_id, const char *mode)
 {
   class cl_io *io;
 
@@ -528,7 +528,7 @@
 	    {
 	      FILE *f= fdopen(fh, "r");
 	      //printf("fdopened f=%p for fh=%d as input\n", f, fh);
-	      io->own_opened(f, cchars("r"));
+	      io->own_opened(f, "r");
 	      io->type= F_SOCKET;
 	      io->server_port= listen_io->server_port;
 	    }
@@ -546,7 +546,7 @@
 	    {
 	      FILE *f= fdopen(fh, "w");
 	      //printf("fdopened f=%p for fh=%d as output\n", f, fh);
-	      io->use_opened(f, cchars("w"));
+	      io->use_opened(f, "w");
 	      io->type= F_SOCKET;
 	      io->server_port= listen_io->server_port;
 	    }
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/globals.cc sdcc-4.2.0+dfsg/sim/ucsim/globals.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/globals.cc	2019-04-17 15:16:48.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/globals.cc	2022-01-27 21:35:29.000000000 +0000
@@ -25,13 +25,12 @@
 02111-1307, USA. */
 /*@1@*/
 
-#include "ddconfig.h"
+//#include "ddconfig.h"
 
 #include 
 
 #include "stypes.h"
 
-
 // No other global variable should exists!
 class cl_app *application;
 
@@ -39,32 +38,6 @@
 /* Delimiters to split up command line */
 char delimiters[]= " ,;\t\r\n";
 
-struct id_element mem_ids[]= {
-  { MEM_ROM  , "ROM  " },
-  { MEM_XRAM , "XRAM " },
-  { MEM_IRAM , "IRAM " },
-  { MEM_SFR  , "SFR  " },
-  { MEM_IXRAM, "IXRAM" },
-  { MEM_DUMMY, "DUMMY" },
-  { 0, 0 }
-};
-
-struct id_element mem_classes[]= {
-  { MEM_ROM  , "rom" },
-  { MEM_XRAM , "xram" },
-  { MEM_IRAM , "iram" },
-  { MEM_SFR  , "sfr" },
-  { MEM_IXRAM, "ixram" },
-  { MEM_DUMMY, "dummy" },
-  { 0, 0 }
-};
-
-struct id_element cpu_states[]= {
-  { stGO,	"OK" },
-  { stIDLE,	"Idle" },
-  { stPD,	"PowerDown" },
-  { 0, 0 }
-};
 
 struct id_element error_type_names[]= {
   { err_unknown,	"unclassified" },
@@ -282,7 +255,7 @@
 "signed it.  However, nothing else grants you permission to modify or\n"
 "distribute the Program or its derivative works.  These actions are\n"
 "prohibited by law if you do not accept this License.  Therefore, by\n"
-"odifying or distributing the Program (or any work based on the\n"
+"modifying or distributing the Program (or any work based on the\n"
 "Program), you indicate your acceptance of this License to do so, and\n"
 "all its terms and conditions for copying, distributing or modifying\n"
 "the Program or works based on it.\n"
@@ -433,9 +406,13 @@
     {"Z180"   , CPU_Z180,    0			, ""		, ""},
     {"R2K"    , CPU_R2K,     0			, ""		, ""},
     {"R3KA"   , CPU_R3KA,    0			, ""		, ""},
+
+    {"GB80"   , CPU_GB80,    0			, ""		, ""},
     {"LR35902", CPU_LR35902, 0			, ""		, ""},
 
     {"EZ80"   , CPU_EZ80,    0			, ""		, ""},
+
+    {"Z80N"   , CPU_Z80N,    0                  , ""            , ""},
     
     {NULL, CPU_NONE, 0, "", ""}
   };
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/globals.h sdcc-4.2.0+dfsg/sim/ucsim/globals.h
--- sdcc-4.0.0+dfsg/sim/ucsim/globals.h	2019-03-14 16:34:34.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/globals.h	2021-11-20 19:14:19.000000000 +0000
@@ -34,14 +34,10 @@
 #include "stypes.h"
 #include "appcl.h"
 
-
 extern class cl_app *application;
 
 extern char delimiters[];
 
-extern struct id_element mem_ids[];
-extern struct id_element mem_classes[];
-extern struct id_element cpu_states[];
 extern struct id_element error_type_names[];
 //extern char *case_string(enum letter_case lcase, const char *str);
 
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/gstring_append.cc sdcc-4.2.0+dfsg/sim/ucsim/gstring_append.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/gstring_append.cc	2016-07-26 21:10:26.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/gstring_append.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,23 +0,0 @@
-#include 
-#include 
-#include 
-
-/**
- * Append and prepend data to a string.
- */
-int main(void)
-{
-	gstring a;
-	gstring foo = "Hello";
-	gstring bar = "World!";
-
-	cout << "Variable is initialized to nothing: " << a << endl;
-
-	a.append(bar);
-	cout << "String is appended to variable: " << a << endl;
-
-	a.prepend(foo + " ");
-	cout << "String is prepended to variable: " << a << endl;
-
-	return 0;
-}
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/gstring_basic.cc sdcc-4.2.0+dfsg/sim/ucsim/gstring_basic.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/gstring_basic.cc	2016-07-26 21:10:26.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/gstring_basic.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,19 +0,0 @@
-#include 
-#include 
-#include 
-
-/**
- * Basic uses of the gstring.
- */
-int main(void)
-{
-	gstring a = "Hello";
-
-	cout << "Variable is set to: " << a << endl;
-
-	a = a + " ";
-	a += "World!";
-	cout << "String is added to variable: " << a << endl;
-
-	return 0;
-}
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/gstring.cc sdcc-4.2.0+dfsg/sim/ucsim/gstring.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/gstring.cc	2016-07-26 21:10:26.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/gstring.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,519 +0,0 @@
-/**
- * Copyright 1999, 2000 by PC Drew
- *
- * All rights reserved.
- *
- * This file is a part of the gstring class - a string class for
- * C++ programs.
- *
- * The gstring class, including all files distributed with it,
- * is free software; you can redistribute it and/or use it and/or modify it
- * under the terms of the Python License (http://www.python.org/doc/Copyright.html)
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
- *
- */
-
-#include "gstring.h"
-
-/**
- * Precondition: none.
- * Postcondition: a new gstring is created, with an empty  string.
- */
-gstring::gstring(void)
-{
-    create("");
-}
-
-/**
- * Precondition: _s is a char.
- * Postcondition: a new gstring is returned, with the value of _s.
- */
-/*gstring::gstring(char _s)
-{
-    create((char*)_s);
-}*/
-
-/**
- * Precondition: _str is a char*.
- * Postcondition: a new gstring is returned, with the value of _str.
- */
-gstring::gstring(char* _str)
-{
-    create(_str);
-}
-
-/**
- * Precondition: _x is an integer.
- * Postcondition: a new gstring is returned, with the string value of _x.
- */
-gstring::gstring(int _x)
-{
-    char* str = new char;
-
-    sprintf(str, "%i", _x);
-    create(str);
-
-    delete [] str;
-}
-
-/**
- * Precondition: _y is an double.
- * Postcondition: a new gstring is returned, with the string value of _y.
- */
-gstring::gstring(double _y)
-{
-    char* str = new char;
-
-    sprintf(str, "%f", _y);
-    create(str);
-
-    delete [] str;
-}
-
-/**
- * Precondition: _gstr is a gstring.
- * Postcondition: a copy of the existing gstring is returned.
- */
-gstring::gstring(const gstring& _gstr)
-{
-    create((char*)_gstr);
-}
-
-/**
- * Precondition: none.
- * Postcondition: the current gstring is destroyed.
- */
-gstring::~gstring(void)
-{
-    destroy();
-}
-
-/**
- * Precondition: _str is a char*.
- * Postcondition: _str is copied into the new gstring.
- */
-int gstring::create(char* _str)
-{
-    assert(_str != NULL);
-
-    // We want to create our own char*, instead of using
-    // strdup() because new will never return NULL, and
-    // malloc() (used by strdup()) might.
-    str = new char[strlen(_str)];
-    strcpy(str, _str);
-
-    return 0;
-}
-
-/**
- * Precondition: none.
- * Postcondition: the current gstring is deleted.
- */
-int gstring::destroy(void)
-{
-    delete [] str;
-
-    return 0;
-}
-
-/**
- * Precondition: _index is the first char in the substring, starting at 0,
- *   _num is the number of chars in the substring.
- * Postcondition: the substring starting at _index and going _num chars
- *   in length is returned, as a gstring.
- */
-gstring gstring::at(int _index, int _num)
-{
-    int len = length();
-
-    assert(_index >= 0 && _num >= 1 && _index <= len - _num);
-
-    char* temp_str = new char[len - _index];
-    char* begin = str;
-    char* end = temp_str;
-
-    // Go to the character that is at _index and copy the
-    // rest of the char* to temp_str.
-    begin += _index;
-    strcpy(temp_str, begin);
-
-    // Go to the character that is at _index + _num and set
-    // it equal to the null terminator.
-    end += _num;
-    *end = '\0';
-
-    // Create a new gstring from the substring that we extracted.
-    gstring gstr(temp_str);
-
-    // Clean up.
-    delete [] temp_str;
-
-    return gstr;
-}
-
-/**
- * Precondition: _num is either an integer >= 1 or it is not specified.
- *   If the function is called without any args (i.e. first()), then
- *   _num = 1 by default.
- * Postcondition: the substring from the beginning of the string, going
- *   _num chars in length is returned.
- */
-gstring gstring::first(int _num)
-{
-    return (at(0, _num));
-}
-
-/**
- * Precondition: _num is either an integer >= 1 or it is not specified.
- *   If the function is called without any args (i.e. first()), then
- *   _num = 1 by default.
- * Postcondition: the substring _num chars from the end of the string, going
- *   to the end of the string is to returned.
- */
-gstring gstring::last(int _num)
-{
-    return (at(length() - _num, _num));
-}
-
-/**
- * Precondition: _num is the number of times you want the string repeated.
- * Postcondition: the current string is changed to be the current string,
- *   repeated _num times.
- */
-gstring& gstring::repeatme(int _num)
-{
-    assert(str != NULL && _num >= 1);
-
-    char* temp_str = new char[length() * _num];
-
-    // Tack str onto the end of temp_str, _num times.
-    for (int i = 0; i < _num; i++) {
-        strcat(temp_str, str);
-    }
-
-    destroy();
-    create(temp_str);
-
-    delete [] temp_str;
-
-    return *this;
-}
-
-/**
- * Precondition: _token is a char*.
- * Postcondition: returns the number of occurences of _token in the string.
- */
-int gstring::ntokens(char* _token)
-{
-  char* temp_str = str;
-  int len = strlen(_token);
-  int i = 0;
-
-  assert(_token != NULL && len >= 1);
-
-  // Iterate through the string...
-  for ( ; *temp_str != '\0'; temp_str++) {
-    if (*temp_str == *_token && strncmp(_token, temp_str, len) == 0) {
-      i++;
-    }
-  }
-
-  return i;
-}
-
-/**
- * Precondition: _token is a char*.
- * Postcondition: an array of gstrings is returned.  The contents of each
- *   gstring in the array is the value either from the beginning of the
- *   original string to the first occurance of _token or from one occurance
- *   of _token to the next.  _token will not be returned in any of the strings.
- *
- * **NOTE**
- * Don't initialize you're array (i.e. call "new") before calling
- * this function...this function will do that for you.  You do, however,
- * need to call "delete [] array" in your own code.
- */
-gstring* gstring::explode(char* _token)
-{
-    assert(_token != NULL && strlen(_token) >= 1);
-
-    int i;
-    int n = nfields(_token);
-    char* ptr;
-    char* temp_str = new char[length()];
-    gstring* arr = new gstring[n];
-
-    strcpy(temp_str, str);
-    for (i = 0, ptr = strtok(temp_str, _token); ptr != NULL;
-            i++, ptr = strtok(NULL, _token)) {
-        arr[i] = ptr;
-    }
-
-    delete [] temp_str;
-
-    return arr;
-}
-
-/**
- * Precondition: _arr is an array of char*'s and _token is a char*, one or more characters
- *     in length.
- * Postcondition: value returned is each char* in the array joined
- *     together by _token.
- */
-gstring implode(char** _arr, char* _token, int _num)
-{
-    assert(_arr != NULL && _token != NULL && strlen(_token) >= 1);
-
-    gstring s = _arr[0];
-
-    for (int i = 1; i < _num; i++) {
-        s.append(_token);
-        s.append(_arr[i]);
-    }
-
-    return s;
-}
-
-/**
- * Precondition: _arr is an array of gstrings and _token is a char*, one or more characters
- *     in length.
- * Postcondition: value returned is each gstring in the array joined
- *     together by _token.
- */
-gstring implode(gstring* _arr, char* _token, int _num)
-{
-    assert(_arr != NULL && _token != NULL);
-
-    gstring s = _arr[0];
-
-    for (int i = 1; i < _num; i++) {
-        s.append(_token + _arr[i]);
-    }
-
-    return s;
-}
-
-/**
- * Precondition: _x is the number of characters to chop off the end of the string.
- *     The default value (chop called without any parameters) is 1 -- the last
- *     character will be removed.
- * Postcondition: the current gstring has the last _x characters removed from the string.
- *     together by _token.
- */
-gstring& gstring::chop(int _x)
-{
-    int len = length() - _x;
-    char* temp_str = new char[len];
-
-    assert(_x >= 0);
-
-    // This allows implode to join the strings together with a "" string (nothing).
-    if (_x > 0) {
-        strcpy(temp_str, str);
-        temp_str[len] = '\0';
-
-        destroy();
-        create(temp_str);
-    }
-
-    delete [] temp_str;
-
-    return *this;
-}
-
-/**
- * Precondition: _str is not NULL.
- * Postcondition: _str is appended to current gstring.
- */
-gstring& gstring::append(char* _str)
-{
-    assert(_str != NULL);
-
-    char* temp_str = new char[length() + strlen(_str)];
-
-    strcpy(temp_str, str);
-    strcat(temp_str, _str);
-
-    destroy();
-    create(temp_str);
-
-    delete [] temp_str;
-
-    return *this;
-}
-
-/**
- * Precondition: _str is not NULL.
- * Postcondition: _str is prepended to current gstring.
- */
-gstring& gstring::prepend(char* _str)
-{
-    assert(_str != NULL);
-
-    char* temp_str = new char[strlen(_str) + length()];
-
-    strcpy(temp_str, _str);
-    strcat(temp_str, str);
-
-    destroy();
-    create(temp_str);
-
-    delete [] temp_str;
-
-    return *this;
-}
-
-/**
- * Precondition: current gstring is not NULL.
- * Postcondition: current gstring is converted to uppercase.
- */
-gstring& gstring::upcaseme(void)
-{
-    char* ptr = str;
-    int len = length();
-
-    assert(str != NULL);
-
-    for (int i = 0; i < len; i++, ptr++) {
-        *ptr = (char)toupper((int) * ptr);
-    }
-
-    return *this;
-}
-
-/**
- * Precondition: current gstring is not equal to NULL.
- * Postcondition: current gstring is converted to lowercase.
- */
-gstring& gstring::downcaseme(void)
-{
-    char* ptr = str;
-    int len = length();
-
-    assert(str != NULL);
-
-    for (int i = 0; i < len; i++, ptr++) {
-        *ptr = (char)tolower((int) * ptr);
-    }
-
-    return *this;
-}
-
-/**
- * Precondition: _gstrarr is an array of gstrings and _num is the number of
- *   gstrings in the array.
- * Postcondition: the value returned is an exact copy of _gstrarr, only it
- *   it is an array of char*'s instead.
- */
-char** tochararray(gstring* _gstrarr, int _num)
-{
-    char** strarr = new char * [_num];
-
-    for (int i = 0; i < _num; i++) {
-        strarr[i] = (char*)_gstrarr[i];
-    }
-
-    return strarr;
-}
-
-/**
- * Precondition: _strarr is an array of char*s and _num is the number of
- *   char*'s in the array.
- * Postcondition: the value returned is an exact copy of _strarr, only it
- *   it is an array of gstrings instead.
- */
-gstring* togstringarray(char** _strarr, int _num)
-{
-    gstring* gstrarr = new gstring[_num];
-
-    for (int i = 0; i < _num; i++) {
-        gstrarr[i] = _strarr[i];
-    }
-
-    return gstrarr;
-}
-
-/*gstring& gstring::operator =(char _s)
-{
-    assert(_s != NULL);
-
-    if (str != NULL) {
-        destroy();
-    }
-    create((char*)_s);
-    return *this;
-}*/
-
-gstring& gstring::operator =(char* _str)
-{
-    assert(_str != NULL);
-
-    if (str != NULL) {
-        destroy();
-    }
-    create(_str);
-    return *this;
-}
-
-gstring& gstring::operator =(int _x)
-{
-  assert(_x != 0/*NULL*/);
-
-  char* temp_str = new char;
-
-  if (str != NULL) {
-    destroy();
-  }
-
-  sprintf(temp_str, "%i", _x);
-  create(temp_str);
-
-  delete [] temp_str;
-  return *this;
-}
-
-gstring& gstring::operator =(double _y)
-{
-  assert(_y != 0/*NULL*/);
-
-  char* temp_str = new char;
-
-  if (str != NULL) {
-    destroy();
-  }
-
-  sprintf(temp_str, "%f", _y);
-  create(temp_str);
-
-  delete [] temp_str;
-  return *this;
-}
-
-gstring& gstring::operator =(const gstring& _gstr)
-{
-    assert((char*)_gstr != NULL);
-
-    if (str != NULL) {
-        destroy();
-    }
-
-    create((char*)_gstr);
-
-    return *this;
-}
-
-/*istream& operator >>(istream& in, gstring& _gstr)
-{
-    char** temp_str = new char * [1];
-
-    in.gets(temp_str);
-    _gstr = temp_str[0];
-
-    delete [] temp_str[0];
-    delete [] temp_str;
-
-    return in;
-}*/
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/gstring_copyright.html sdcc-4.2.0+dfsg/sim/ucsim/gstring_copyright.html
--- sdcc-4.0.0+dfsg/sim/ucsim/gstring_copyright.html	2016-07-26 21:10:26.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/gstring_copyright.html	1970-01-01 00:00:00.000000000 +0000
@@ -1,231 +0,0 @@
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-otherwise the notice is similar.
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-commercial use (including resale).  There is no GNU-like
-"copyleft" restriction.
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A clarification: some very picky lawyers are worried that the
-notice doesn't explicitly grant permission to distribute modified
-copies (even though it grants permission to copy, modify, and
-distribute).  This can be considered an oversight in the notice; we
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-otherwise play by the rules).  Similarly, the words "without fee" are
-to be read connected to "permission": permission is granted without
-fee.  We are in the process of revising the notice to clarify it, but
-this is a slow process.
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Another clarification: the limitation of the copyright to 1991-1995
-in the notice is not a mistake, but rather a deliberate decision.
-Copyright applies regardless of whether it is explicitly stated or
-not.
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-The Netherlands.
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All Rights Reserved
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-documentation for any purpose and without fee is hereby granted,
-provided that the above copyright notice appear in all copies and that
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-Centrum or CWI or Corporation for National Research Initiatives or
-CNRI not be used in advertising or publicity pertaining to
-distribution of the software without specific, written prior
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-is made available by the Corporation for National Research Initiatives
-(CNRI) at the Internet address ftp://ftp.python.org.
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-REGARD TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF
-MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL STICHTING MATHEMATISCH
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-DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
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-
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/gstring_explode.cc sdcc-4.2.0+dfsg/sim/ucsim/gstring_explode.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/gstring_explode.cc	2016-07-26 21:10:26.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/gstring_explode.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,34 +0,0 @@
-#include 
-#include 
-#include 
-
-/**
- * Uses of explode and implode.  Note: there are no memory leaks here.
- */
-int main(void)
-{
-	gstring a = "drewpc:x:38241:29:Drew Philip C:/home/cia/drewpc:/usr/local/bin/tcsh";
-	gstring token = ":";
-	gstring bar;
-	gstring* foo;  // Array of gstrings.
-	int nfields = a.nfields(token);
-
-	cout << "Variable is initialized to a string: " << a << endl;
-	cout << "Variable is seperated by token: '" << token << "'" << endl;
-
-	// explode() allocates memory for each array index automatically.
-	foo = a.explode(token);
-
-	for(int i = 0; i < nfields; i++) {
-		cout << "Array[" << i << "]: " << foo[i] << endl;
-	}
-
-	// implode puts foo back together, separated by token.
-	bar = implode(foo, token, nfields);
-	cout << "Variable is set to implosion of array: " << bar << endl;
-
-	// you do have to delete foo, or you'll have memory leaks.
-	delete [] foo;
-
-	return 0;
-}
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/gstring.h sdcc-4.2.0+dfsg/sim/ucsim/gstring.h
--- sdcc-4.0.0+dfsg/sim/ucsim/gstring.h	2016-07-26 21:10:26.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/gstring.h	1970-01-01 00:00:00.000000000 +0000
@@ -1,312 +0,0 @@
-/**
- * Copyright 1999, 2000 by PC Drew
- *
- * All rights reserved.
- *
- * This file is a part of the gstring class - a string class for
- * C++ programs.
- *
- * The gstring class, including all files distributed with it,
- * is free software; you can redistribute it and/or use it and/or modify it
- * under the terms of the Python License (http://www.python.org/doc/Copyright.html)
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
- *
- */
-
-#ifndef _GSTRING_H
-#define _GSTRING_H
-
-//#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-
-class gstring
-{
-public:
-  // Constructors.
-  gstring(void);
-  //gstring(char);
-  gstring(char*);
-  gstring(int);
-  gstring(double);
-
-  // Copy Constructor.
-  gstring(const gstring&);
-
-  // Destructor.
-  virtual ~gstring(void);
-
-  // ASCII to Integer.
-  inline int a2i(void)
-  {
-    assert(str != NULL);
-    return (atoi(str));
-  };
-
-  // ASCII to Double.
-  inline double a2d(void)
-  {
-    assert(str != NULL);
-    return (atof(str));
-  };
-
-  // String length.
-  inline int length(void)
-  {
-    assert(str != NULL);
-    return (strlen(str));
-  };
-
-  // Repeat the string _x times.
-  gstring& repeatme(int);
-  inline gstring repeat(int _x)
-  {
-    return (gstring(str).repeatme(_x));
-  };
-
-  // Return the number of times _token appears in the string.
-  int ntokens(char*);
-  /*inline int ntokens(char _token)
-  {
-    return (ntokens((char*)_token));
-    };*/
-  inline int ntokens(gstring _token)
-  { 
-    return (ntokens((char*)_token));
-  };
-
-  // Return the number of times _token appears in the string, +1.
-  // This is, theoretically, the number of fields seperated by _token.
-  /*inline int nfields(char _token)
-  {
-    return (ntokens((char*)_token) + 1);
-    };*/
-  inline int nfields(char* _token)
-  {
-    return (ntokens(_token) + 1);
-  };
-  inline int nfields(gstring _token)
-  {
-    return (ntokens((char*)_token) + 1);
-  };
-
-  // Chop of the _xth character off the string.
-  gstring& chop(int = 1);
-
-  // Return a substring.
-  gstring at(int, int);
-  gstring first(int = 1);
-  gstring last(int = 1);
-
-  // Convert to upper case.
-  gstring& upcaseme(void);
-  inline gstring upcase(void)
-  {
-    return (gstring(str).upcaseme());
-  };
-
-  // Convert to lower case.
-  gstring& downcaseme(void);
-  inline gstring downcase(void)
-  {
-    return (gstring(str).downcaseme());
-  };
-
-  // Explode the string, delimted by a token, into an array of gstrings.
-  gstring* explode(char*);
-  /*inline gstring* explode(char _token)
-  {
-    return (explode((char*)_token));
-    };*/
-  inline gstring* explode(gstring _token)
-  {
-    return (explode((char*)_token));
-  };
-
-  // Append.
-  gstring& append(char*);
-  /*inline gstring& append(char _s)
-  {
-    return (append((char*)_s));
-    };*/
-  inline gstring& append(const gstring& _gstr)
-  {
-    return (append((char*)_gstr));
-  };
-
-  // Prepend.
-  gstring& prepend(char*);
-  /*inline gstring& prepend(char _s)
-  {
-    return (prepend((char*)_s));
-    };*/
-  inline gstring& prepend(gstring _gstr)
-  {
-    return (prepend((char*)_gstr));
-  };
-
-  // Addition assignment operators.
-  /*inline gstring& operator +=(char _s)
-  {
-    return (append((char*)_s));
-    };*/
-  inline gstring& operator +=(char* _str)
-  {
-    return (append(_str));
-  };
-  inline gstring& operator +=(const gstring& _gstr)
-  {
-    return (append((char*)_gstr));
-  };
-
-  // Assignment operators.
-  //gstring& operator =(char);
-  gstring& operator =(char *);
-  gstring& operator =(double);
-  gstring& operator =(const gstring&);
-  gstring& operator =(int);
-
-  // Use for casting.  You can do both (char*)gstring and
-  // (const char*)gstring.
-  * operator char(void) { return str; };
-  * operator char(void) const { return str; };
-
-private:
-  // Use for creating and destroying current gstrings.
-  int create(char* _str);
-  int destroy(void);
-
-  // The string itself.
-  char* str;
-};
-
-// Useful for converting one array type to another.
-char** tochararray(gstring*, int);
-gstring* togstringarray(char**, int);
-
-// Implode an array of gstrings or char*s into a gstring.
-gstring implode(char**, char*, int);
-/*inline gstring implode(char** _strarr, char _token, int _num)
-{
-  return (implode(_strarr, (char*)_token, _num));
-};*/
-inline gstring implode(char** _strarr, gstring _token, int _num)
-{
-  return (implode(_strarr, (char*)_token, _num));
-};
-gstring implode(gstring*, char*, int);
-/*inline gstring implode(gstring* _gstrarr, char _token, int _num)
-{
-  return (implode(_gstrarr, (char*)_token, _num));
-};*/
-inline gstring implode(gstring* _gstrarr, gstring _token, int _num)
-{
-  return (implode(_gstrarr, (char*)_token, _num));
-};
-
-// Addition operators.
-inline gstring operator +(const gstring& _gstr, char* _str)
-{
-  gstring gstr(_gstr); return (gstr.append(_str));
-};
-inline gstring operator +(char* _str, const gstring& _gstr)
-{
-  gstring gstr(_str); return (gstr.append(_gstr));
-};
-inline gstring operator +(const gstring& _gstr1, const gstring& _gstr2)
-{
-  gstring gstr(_gstr1); return (gstr.append(_gstr2));
-};
-
-// Boolean equality operators.
-/*inline bool operator ==(const gstring& _gstr, char _s)
-{
-  return (strcmp((char*)_gstr, (char*)_s) == 0);
-};*/
-inline bool operator ==(const gstring& _gstr, char* _str)
-{
-  return (strcmp((char*)_gstr, _str) == 0);
-};
-inline bool operator ==(const gstring& _gstr1, gstring _gstr2)
-{
-  return (strcmp((char*)_gstr1, (char*)_gstr2) == 0);
-};
-
-// Boolean inequality operators.
-/*inline bool operator !=(const gstring& _gstr, char _s)
-{
-  return (strcmp((char*)_gstr, (char*)_s) != 0);
-};*/
-inline bool operator !=(const gstring& _gstr, char* _str)
-{
-  return (strcmp((char*)_gstr, _str) != 0);
-};
-inline bool operator !=(const gstring& _gstr1, const gstring& _gstr2)
-{
-  return (strcmp((char*)_gstr1, (char*)_gstr2) != 0);
-};
-
-// Boolean comparison operators.
-/*inline bool operator <=(const gstring& _gstr, char _s)
-{
-  return (strcmp((char*)_gstr, (char*)_s) <= 0);
-};*/
-inline bool operator <=(const gstring& _gstr, char* _str)
-{
-  return (strcmp((char*)_gstr, _str) <= 0);
-};
-inline bool operator <=(const gstring& _gstr1, const gstring& _gstr2)
-{
-  return (strcmp((char*)_gstr1, (char*)_gstr2) <= 0);
-};
-/*inline bool operator >=(const gstring& _gstr, char _s)
-{
-  return (strcmp((char*)_gstr, (char*)_s) >= 0);
-};*/
-inline bool operator >=(const gstring& _gstr, char* _str)
-{
-  return (strcmp((char*)_gstr, _str) >= 0);
-};
-inline bool operator >=(const gstring& _gstr1, const gstring& _gstr2)
-{
-  return (strcmp((char*)_gstr1, (char*)_gstr2) >= 0);
-};
-/*inline bool operator <(const gstring& _gstr, char _s)
-{
-  return (strcmp((char*)_gstr, (char*)_s) < 0);
-};*/
-inline bool operator <(const gstring& _gstr, char* _str)
-{
-  return (strcmp((char*)_gstr, _str) < 0);
-};
-inline bool operator <(const gstring& _gstr1, const gstring& _gstr2)
-{
-  return (strcmp((char*)_gstr1, (char*)_gstr2) < 0);
-};
-/*inline bool operator >(const gstring& _gstr, char _s)
-{
-  return (strcmp((char*)_gstr, (char*)_s) > 0);
-};*/
-inline bool operator >(const gstring& _gstr, char* _str)
-{
-  return (strcmp((char*)_gstr, _str) > 0);
-};
-inline bool operator >(const gstring& _gstr1, const gstring& _gstr2)
-{
-  return (strcmp((char*)_gstr1, (char*)_gstr2) > 0);
-};
-
-// Stream operators (i.e. cin >> gstring or cout << gstring).
-/*inline ostream& operator <<(ostream& _out, const gstring _gstr)
-{
-  return (_out << (char*)_gstr);
-};
-istream& operator >>(istream&, gstring&);*/
-
-#endif 
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/gstring_LICENSE sdcc-4.2.0+dfsg/sim/ucsim/gstring_LICENSE
--- sdcc-4.0.0+dfsg/sim/ucsim/gstring_LICENSE	2016-07-26 21:10:26.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/gstring_LICENSE	1970-01-01 00:00:00.000000000 +0000
@@ -1,7 +0,0 @@
-Copyright 1999, 2000 by PC Drew 
-
-All Rights Reserved.
-
-The license that is included with this distrobution was copied from
-the Python website on 2/21/2000.  See http://www.python.org/doc/Copyright.html
-for a more recent copy of the Python License.
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/gstring_REAME sdcc-4.2.0+dfsg/sim/ucsim/gstring_REAME
--- sdcc-4.0.0+dfsg/sim/ucsim/gstring_REAME	2016-07-26 21:10:26.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/gstring_REAME	1970-01-01 00:00:00.000000000 +0000
@@ -1,17 +0,0 @@
-USAGE:
-  * You can copy the gstring.{cpp, h} files into your application's
-	src directory, and use it directly in your application.
-
-  * Make and install the library.  Then, in your application's Makefile
-	add the works '-lgstring' in order to link the gstring library
-	to your application.
-
-INSTALL:
-  * Verify the variables in the Makefile are correct and to
-	your liking.
-
-  * Type 'make' then 'make install' 
-
-AUTHOR:
-  PC Drew 
-  http://gstring.sourceforge.net
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/gui.src/clean.mk sdcc-4.2.0+dfsg/sim/ucsim/gui.src/clean.mk
--- sdcc-4.0.0+dfsg/sim/ucsim/gui.src/clean.mk	2006-04-24 20:29:10.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/gui.src/clean.mk	2020-09-27 14:17:23.000000000 +0000
@@ -10,7 +10,7 @@
 
 clean: clean_local
 	@for pkg in $(PKGS); do\
-	  $(MAKE) -C $$pkg clean;\
+	  $(MAKE) -C $$pkg -f clean.mk clean;\
 	done
 
 
@@ -22,7 +22,7 @@
 
 distclean: distclean_local
 	@for pkg in $(PKGS); do\
-	  $(MAKE) -C $$pkg distclean;\
+	  $(MAKE) -C $$pkg -f clean.mk distclean;\
 	done
 
 
@@ -30,7 +30,7 @@
 # -----------------------------------------
 mostlyclean: clean_local
 	@for pkg in $(PKGS); do\
-	  $(MAKE) -C $$pkg mostlyclean;\
+	  $(MAKE) -C $$pkg -f clean.mk mostlyclean;\
 	done
 
 
@@ -39,7 +39,7 @@
 # -----------------------------------------------------------------------
 realclean: distclean_local
 	@for pkg in $(PKGS); do\
-	  $(MAKE) $$pkg realclean;\
+	  $(MAKE) $$pkg -f clean.mk realclean;\
 	done
 
 # End of gui.src/clean.mk
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/gui.src/Makefile.in sdcc-4.2.0+dfsg/sim/ucsim/gui.src/Makefile.in
--- sdcc-4.0.0+dfsg/sim/ucsim/gui.src/Makefile.in	2017-05-06 08:34:01.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/gui.src/Makefile.in	2022-01-13 08:20:03.000000000 +0000
@@ -17,10 +17,11 @@
 top_srcdir	= @top_srcdir@
 
 DEFS            = $(subs -DHAVE_CONFIG_H,,@DEFS@)
+PICOPT		= @PICOPT@
 CPPFLAGS        = @CPPFLAGS@ -I$(srcdir) -I$(top_builddir) -I$(top_srcdir) \
 		  -I$(top_srcdir)/sim.src -I$(top_srcdir)/cmd.src
-CFLAGS          = @CFLAGS@ @WALL_FLAG@
-CXXFLAGS        = @CXXFLAGS@ @WALL_FLAG@
+CFLAGS          = @WALL_FLAG@ @CFLAGS@
+CXXFLAGS        = @WALL_FLAG@ @CXXFLAGS@ $(PICOPT)
 
 LIBS		= @LIBS@ @CURSES_LIBS@ -L$(top_builddir)
 
@@ -131,6 +132,8 @@
 
 test_local:
 
+baseline:
+
 
 # Performing installation test
 # ----------------------------
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/gui.src/obsolete/a.cc sdcc-4.2.0+dfsg/sim/ucsim/gui.src/obsolete/a.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/gui.src/obsolete/a.cc	2001-04-02 13:08:48.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/gui.src/obsolete/a.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,87 +0,0 @@
-#include 
-#include 
-
-int sfr[4];
-int port[4];
-
-void
-init_panel(PANEL *p)
-{
-  int mask, x, y;
-  int na, ha;
-  int cursor= 2;
-  WINDOW *w= panel_window(p);
-  
-  if (has_colors())
-    {
-      na= COLOR_PAIR(1);
-      ha= COLOR_PAIR(2);
-    }
-  else
-    {
-      na= A_NORMAL;
-      ha= A_STANDOUT;
-    }
-  //wattron(w, COLOR_PAIR);
-  x= 0;
-  for (mask= 1, y= 0; mask < 0x100; mask<<= 1,y++)
-    {
-      wattrset(w, (y==cursor)?ha:na);
-      mvwprintw(w, y,x, "%s", (sfr[0]&mask)?"High":" Low");
-    }
-}
-
-wchar_t
-wait_input(PANEL *p)
-{
-  WINDOW *w= panel_window(p);
-  wchar_t c;
-
-  c= wgetch(w);
-  printw("%d 0x%x\n",c,c);
-  return(c);
-}
-
-int
-main(int argc, char *argv[])
-{
-  wchar_t c;
-
-  initscr();      /* initialize the curses library */
-  keypad(stdscr, TRUE);  /* enable keyboard mapping */
-  nonl();         /* tell curses not to do NL->CR/NL on output */
-  cbreak();       /* take input chars one at a time, no wait for \n */
-  noecho();       /* don't echo input */
-  if (has_colors())
-    {
-      start_color();
-      printw("has %d colors and %d pairs\n", COLORS, COLOR_PAIRS);
-      init_pair(1, COLOR_WHITE, COLOR_BLUE);
-      init_pair(2, COLOR_WHITE, COLOR_RED);
-    }
-  if (has_key(KEY_UP))
-    printw("has UP KEY_UP=0x%x\n",KEY_UP);
-  else
-    printf("has no UP\n");
-  c= getch();
-  printw("got %d %x\n",c,c);
-
-  WINDOW *w= newwin(10,10, 3,3);
-  keypad(w, TRUE);
-  PANEL *p= new_panel(w);
-
-  sfr[0]= 0x5a;
-  init_panel(p);
-  update_panels();
-  doupdate();
-  c= wait_input(p);
-  //c= getch();
-
-  endwin();
-  if (c==KEY_UP)
-    printf("got UP\n");
-  else if (c==KEY_DOWN)
-    printf("got DOWN\n");
-  else
-    printf("got \"%d\"\n", c);
-}
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/gui.src/obsolete/app.cc sdcc-4.2.0+dfsg/sim/ucsim/gui.src/obsolete/app.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/gui.src/obsolete/app.cc	2001-04-02 13:08:48.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/gui.src/obsolete/app.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,171 +0,0 @@
-/*
- * Simulator of microcontrollers (app.cc)
- *
- * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
- * 
- * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
- *
- */
-
-/* This file is part of microcontroller simulator: ucsim.
-
-UCSIM is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2 of the License, or
-(at your option) any later version.
-
-UCSIM is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with UCSIM; see the file COPYING.  If not, write to the Free
-Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-02111-1307, USA. */
-/*@1@*/
-
-#include 
-
-#include "appcl.h"
-#include "deskcl.h"
-
-
-cl_app::cl_app(char *iname):
-  cl_group(iname, this)
-{
-  drawn= 0;
-}
-
-cl_app::~cl_app(void)
-{
-  endwin();
-}
-
-int
-cl_app::init(void)
-{
-  initscr();
-  keypad(stdscr, TRUE);
-  nonl();
-  cbreak();
-  noecho();
-  
-  pos= new cl_box(0,0, COLS, LINES);
-  cl_view::init();
-  state|= SF_SELECTED;//select();
-  class cl_box b(*pos);
-  //b.move_rel(0,1);
-  //b.grow(0,-2);
-  if ((desk= mk_desk(&b)))
-    insert(desk);
-  desk->select();
-  mk_views(desk);
-
-  //update();
-  update_panels();
-  doupdate();
-  return(0);
-}
-
-class cl_gin *
-cl_app::mk_input(void)
-{
-  class cl_gin *i= new cl_gin();
-  i->init();
-  i->add_input(stdin, 0);
-  return(i);
-}
-
-int *
-cl_app::mk_palette(void)
-{
-  int *p, i;
-  int colors;
-
-  colors= 64;
-  p= (int*)malloc(colors * sizeof(int));
-  if (has_colors())
-    {
-      start_color();
-
-      init_pair(i= C_WIN+C_WIN_NORMAL, COLOR_YELLOW, COLOR_BLUE);
-      p[i]= COLOR_PAIR(i)|A_BOLD;
-      for (i= 1; i < colors; i++)
-	p[i]= p[C_WIN+C_WIN_NORMAL];
-      // desktop
-      init_pair(i= C_DSK_BG, COLOR_BLACK, COLOR_WHITE);
-      p[i]= COLOR_PAIR(i);
-      // menus and status bar
-      init_pair(i= C_DSK_NORMAL, COLOR_WHITE, COLOR_BLUE);
-      p[i]= COLOR_PAIR(i)|A_BOLD;
-      init_pair(i= C_DSK_DISABLED, COLOR_WHITE, COLOR_BLUE);
-      p[i]= COLOR_PAIR(i);
-      // window
-      init_pair(i= C_WIN+C_WIN_FPASSIVE, COLOR_WHITE, COLOR_BLUE);
-      p[i]= COLOR_PAIR(i);
-      init_pair(i= C_WIN+C_WIN_FACTIVE, COLOR_WHITE, COLOR_BLUE);
-      p[i]= COLOR_PAIR(i)|A_BOLD;
-      init_pair(i= C_WIN+C_WIN_SELECTED, COLOR_YELLOW, COLOR_RED);
-      p[i]= COLOR_PAIR(i)|A_BOLD; 
-    }
-  else
-    {
-      for (i= 0; i < colors; i++)
-	p[i]= A_NORMAL;
-      p[C_WIN+C_WIN_FACTIVE]|= A_BOLD;
-      p[C_WIN+C_WIN_SELECTED]|= A_REVERSE;
-    }
-  return(p);
-}
-
-class cl_group *
-cl_app::mk_desk(class cl_box *ipos)
-{
-  class cl_group *d= new cl_desk(ipos, "desktop", this);
-  d->init();
-  return(d);
-}
-
-
-int
-cl_app::handle_event(struct t_event *event)
-{
-  if (!cl_group::handle_event(event))
-    {
-      if (event->what == EV_KEY)
-	switch (event->event.key)
-	  {
-	  case KEY_BREAK: case KEY_EXIT:
-	    event->what= EV_COMMAND;
-	    event->event.msg.cmd= CMD_QUIT;
-	    break;
-	  }
-    }
-  return(0);
-}
-
-int
-cl_app::run(void)
-{
-  struct t_event event;
-  
-  drawn= 0;
-  while (get_event(&event))
-    {
-      if (!handle_event(&event))
-	{
-	  if (event.what == EV_COMMAND &&
-	      event.event.msg.cmd == CMD_QUIT)
-	    return(0);
-	  unhandled(&event);
-	}
-      if (drawn)
-	update();
-      drawn= 0;
-    }
-  return(0);
-}
-
-
-/* End of gui.src/app.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/gui.src/obsolete/appcl.h sdcc-4.2.0+dfsg/sim/ucsim/gui.src/obsolete/appcl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/gui.src/obsolete/appcl.h	2001-04-02 13:08:48.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/gui.src/obsolete/appcl.h	1970-01-01 00:00:00.000000000 +0000
@@ -1,54 +0,0 @@
-/*
- * Simulator of microcontrollers (appcl.h)
- *
- * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
- * 
- * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
- *
- */
-
-/* This file is part of microcontroller simulator: ucsim.
-
-UCSIM is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2 of the License, or
-(at your option) any later version.
-
-UCSIM is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with UCSIM; see the file COPYING.  If not, write to the Free
-Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-02111-1307, USA. */
-/*@1@*/
-
-#ifndef APPCL_HEADER
-#define APPCL_HEADER
-
-#include "groupcl.h"
-
-
-class cl_app: public cl_group
-{
-public:
-  class cl_group *desk;
-  int drawn;
-public:
-  cl_app(char *iname);
-  ~cl_app(void);
-  virtual int init(void);
-  virtual class cl_gin *mk_input(void);
-  virtual int *mk_palette(void);
-  virtual class cl_group *mk_desk(class cl_box *ipos);
-  
-  virtual int handle_event(struct t_event *event);
-  virtual int run(void);
-};
-
-
-#endif
-
-/* End of gui.src/appcl.h */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/gui.src/obsolete/bg.cc sdcc-4.2.0+dfsg/sim/ucsim/gui.src/obsolete/bg.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/gui.src/obsolete/bg.cc	2001-04-02 13:08:48.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/gui.src/obsolete/bg.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,63 +0,0 @@
-/*
- * Simulator of microcontrollers (bg.cc)
- *
- * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
- * 
- * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
- *
- */
-
-/* This file is part of microcontroller simulator: ucsim.
-
-UCSIM is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2 of the License, or
-(at your option) any later version.
-
-UCSIM is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with UCSIM; see the file COPYING.  If not, write to the Free
-Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-02111-1307, USA. */
-/*@1@*/
-
-#include 
-
-#include "bgcl.h"
-
-
-cl_bg::cl_bg(class cl_box *ipos, char *iname, class cl_app *iapp):
-  cl_view(ipos, iname, iapp)
-{
-  options&= ~OF_SELECTABLE;
-}
-
-int *
-cl_bg::mk_palette(void)
-{
-  int *p;
-
-  p= (int*)malloc(1*sizeof(int));
-  p[0]= C_DSK_BG;
-  return(p);
-}
-
-int
-cl_bg::draw(void)
-{
-  int x, y, color= get_color(0);
-  
-  wmove(window, 0, 0);
-  wattrset(window, color);
-  for (y= 0; y < pos->h; y++)
-    for (x= 0; x < pos->w; x++)
-      waddch(window, ACS_CKBOARD);
-  return(0);
-}
-
-
-/* End of gui.src/bg.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/gui.src/obsolete/bgcl.h sdcc-4.2.0+dfsg/sim/ucsim/gui.src/obsolete/bgcl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/gui.src/obsolete/bgcl.h	2001-04-02 13:08:48.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/gui.src/obsolete/bgcl.h	1970-01-01 00:00:00.000000000 +0000
@@ -1,47 +0,0 @@
-/*
- * Simulator of microcontrollers (bgcl.h)
- *
- * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
- * 
- * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
- *
- */
-
-/* This file is part of microcontroller simulator: ucsim.
-
-UCSIM is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2 of the License, or
-(at your option) any later version.
-
-UCSIM is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with UCSIM; see the file COPYING.  If not, write to the Free
-Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-02111-1307, USA. */
-/*@1@*/
-
-#ifndef BGCL_HEADER
-#define BGCL_HEADER
-
-
-#include "viewcl.h"
-#include "appcl.h"
-
-
-class cl_bg: public cl_view
-{
-public:
-  cl_bg(class cl_box *ipos, char *iname, class cl_app *iapp);
-  virtual int *mk_palette(void);
-  virtual int draw(void);
-};
-
-
-#endif
-
-/* End of gui.src/bgcl.h */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/gui.src/obsolete/desk.cc sdcc-4.2.0+dfsg/sim/ucsim/gui.src/obsolete/desk.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/gui.src/obsolete/desk.cc	2001-04-02 13:08:48.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/gui.src/obsolete/desk.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,58 +0,0 @@
-/*
- * Simulator of microcontrollers (desk.cc)
- *
- * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
- * 
- * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
- *
- */
-
-/* This file is part of microcontroller simulator: ucsim.
-
-UCSIM is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2 of the License, or
-(at your option) any later version.
-
-UCSIM is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with UCSIM; see the file COPYING.  If not, write to the Free
-Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-02111-1307, USA. */
-/*@1@*/
-
-#include "deskcl.h"
-#include "bgcl.h"
-
-
-int
-cl_desk::handle_event(struct t_event *event)
-{
-  if (cl_group::handle_event(event))
-    return(1);
-  if (event->what == EV_KEY &&
-      event->event.key == KEY_F(6))
-    {
-      select_next();
-      return(1);
-    }
-  return(0);
-}
-
-int
-cl_desk::mk_views(class cl_group *ins_to)
-{
-  class cl_box b(*pos);
-
-  b.move_rel(0,1);
-  b.grow(0,-2);
-  insert(new cl_bg(&b, "background", app));
-  return(0);
-}
-
-
-/* End of gui.src/desk.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/gui.src/obsolete/deskcl.h sdcc-4.2.0+dfsg/sim/ucsim/gui.src/obsolete/deskcl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/gui.src/obsolete/deskcl.h	2001-04-02 13:08:48.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/gui.src/obsolete/deskcl.h	1970-01-01 00:00:00.000000000 +0000
@@ -1,42 +0,0 @@
-/*
- * Simulator of microcontrollers (deskcl.h)
- *
- * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
- * 
- * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
- *
- */
-
-/* This file is part of microcontroller simulator: ucsim.
-
-UCSIM is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2 of the License, or
-(at your option) any later version.
-
-UCSIM is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with UCSIM; see the file COPYING.  If not, write to the Free
-Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-02111-1307, USA. */
-/*@1@*/
-
-#include "groupcl.h"
-
-
-class cl_desk: public cl_group
-{
-public:
-  cl_desk(class cl_box *ipos, char *iname, class cl_app *iapp):
-    cl_group(ipos, iname, iapp) {}
-  virtual int mk_views(class cl_group *ins_to);
-
-  virtual int handle_event(struct t_event *event);
-};
-
-
-/* End of gui.src/deskcl.h */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/gui.src/obsolete/event.cc sdcc-4.2.0+dfsg/sim/ucsim/gui.src/obsolete/event.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/gui.src/obsolete/event.cc	2001-04-02 13:08:48.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/gui.src/obsolete/event.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,126 +0,0 @@
-/*
- * Simulator of microcontrollers (event.cc)
- *
- * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
- * 
- * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
- *
- */
-
-/* This file is part of microcontroller simulator: ucsim.
-
-UCSIM is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2 of the License, or
-(at your option) any later version.
-
-UCSIM is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with UCSIM; see the file COPYING.  If not, write to the Free
-Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-02111-1307, USA. */
-/*@1@*/
-
-#include "ddconfig.h"
-
-#include 
-
-//#include 
-
-#include "eventcl.h"
-
-
-cl_input_src::cl_input_src(FILE *ifile, class cl_view *iview)
-{
-  file= ifile;
-  view= iview;
-}
-
-
-cl_gin::cl_gin(void)
-{
-  FD_ZERO(&in_set);
-  max_fdes= 0;
-  inputs= new cl_list(1, 1);
-}
-
-cl_gin::~cl_gin(void)
-{
-  delete inputs;
-}
-
-
-int
-cl_gin::add_input(FILE *ifile, class cl_view *iview)
-{
-  int d= fileno(ifile);
-
-  inputs->add(new cl_input_src(ifile, iview));
-  if (d > max_fdes)
-    max_fdes= d;
-  FD_SET(d, &in_set);
-  return(0);
-}
-
-class cl_input_src *
-cl_gin::get_input_src(int fdes)
-{
-  int i;
-  
-  for (i= 0; i < inputs->count; i++)
-    {
-      class cl_input_src *s= (class cl_input_src *)(inputs->at(i));
-      if (fileno(s->file) == fdes)
-	return(s);
-    }
-  return(0);
-}
-
-int
-cl_gin::get_event(struct t_event *event)
-{
-  fd_set set;
-  //static struct timeval timeout= {0,0};
-  wchar_t c;
-
-  //FD_ZERO(&set);
-  set= in_set;
-  //FD_SET(fileno(stdin), &set);
-  if(::select(/*fileno(stdin)*/max_fdes+1,
-	      &set, NULL, NULL,
-	      NULL/*&timeout*/) > 0)
-    {
-      int i;
-      for (i= 0; i < inputs->count; i++)
-	{
-	  class cl_input_src *s= (class cl_input_src *)(inputs->at(i));
-	  if (!s->file ||
-	      !(FD_ISSET(fileno(s->file), &set)))
-	    continue;
-	  if (s->view)
-	    {
-	      if (s->file)
-		{
-		  c= fgetc(s->file);
-		  return(s->view->mk_event(event, s->file, c));
-		}
-	    }
-	  else
-	    if ((c= getch()) > 0)
-	      {
-		event->what= EV_KEY;
-		event->event.key= c;
-		return(1);
-	      }
-	}
-    }
-  
-  return(0);
-}
-
-
-/* End of gui.src/event.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/gui.src/obsolete/eventcl.h sdcc-4.2.0+dfsg/sim/ucsim/gui.src/obsolete/eventcl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/gui.src/obsolete/eventcl.h	2001-04-02 13:08:48.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/gui.src/obsolete/eventcl.h	1970-01-01 00:00:00.000000000 +0000
@@ -1,96 +0,0 @@
-/*
- * Simulator of microcontrollers (eventcl.h)
- *
- * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
- * 
- * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
- *
- */
-
-/* This file is part of microcontroller simulator: ucsim.
-
-UCSIM is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2 of the License, or
-(at your option) any later version.
-
-UCSIM is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with UCSIM; see the file COPYING.  If not, write to the Free
-Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-02111-1307, USA. */
-/*@1@*/
-
-#ifndef EVENTCL_HEADER
-#define EVENTCL_HEADER
-
-#include "ddconfig.h"
-
-#if FD_HEADER_OK
-# include HEADER_FD
-#endif
-
-#include "pobjcl.h"
-
-#include "viewcl.h"
-
-
-#define EV_NOTHING	0x0000
-#define EV_MOUSE_DOWN	0x0001
-#define EV_MOUSE_UP	0x0002
-#define EV_MOUSE_MOVE	0x0004
-#define EV_MOUSE_AUTO	0x0008
-#define EV_KEY		0x0010
-#define EV_COMMAND	0x0100
-#define EV_BROADCAST	0x0200
-
-// cathegories
-#define EV_MOUSE	(EV_MOUSE_DOWN|EV_MOUSE_UP|EV_MOUSE_MOVE|EV_MOUSE_AUTO)
-#define EV_KEYBOARD	EV_KEY
-#define EV_MESSAGE	0xff00
-
-#define CMD_QUIT	0
-
-struct t_event {
-  int what;
-  union {
-    wchar_t key;
-    struct {
-      int cmd;
-      long param;
-    } msg;
-  } event;
-};
-
-
-class cl_input_src: public cl_base
-{
-public:
-  FILE *file;
-  class cl_view *view;
-  cl_input_src(FILE *ifile, class cl_view *iview);
-};
-
-class cl_gin: public cl_base
-{
-public:
-  fd_set in_set;
-  int max_fdes;
-  cl_list *inputs;
-public:
-  cl_gin(void);
-  ~cl_gin(void);
-
-  virtual int add_input(FILE *ifile, class cl_view *iview);
-  virtual class cl_input_src *get_input_src(int fdes);
-  virtual int get_event(struct t_event *event);
-};
-
-
-#endif
-
-/* End of gui.src/eventcl.h */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/gui.src/obsolete/frame.cc sdcc-4.2.0+dfsg/sim/ucsim/gui.src/obsolete/frame.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/gui.src/obsolete/frame.cc	2001-04-02 13:08:48.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/gui.src/obsolete/frame.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,76 +0,0 @@
-/*
- * Simulator of microcontrollers (frame.cc)
- *
- * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
- * 
- * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
- *
- */
-
-/* This file is part of microcontroller simulator: ucsim.
-
-UCSIM is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2 of the License, or
-(at your option) any later version.
-
-UCSIM is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with UCSIM; see the file COPYING.  If not, write to the Free
-Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-02111-1307, USA. */
-/*@1@*/
-
-#include "ddconfig.h"
-
-#include 
-#include "i_string.h"
-
-#include "framecl.h"
-#include "wincl.h"
-
-
-cl_frame::cl_frame(class cl_box *ipos, class cl_view *iwindow, char *iname,
-		   class cl_app *iapp):
-  cl_view(ipos, iname, iapp)
-{
-  win= iwindow;
-  options&= ~OF_SELECTABLE;
-}
-
-int *
-cl_frame::mk_palette(void)
-{
-  int *p;
-
-  p= (int*)malloc(2*sizeof(int));
-  p[0]= C_WIN_FPASSIVE;
-  p[1]= C_WIN_FACTIVE;
-  return(p);
-}
-
-int
-cl_frame::draw(void)
-{
-  char *t;
-  int color;
-
-  color= get_color((win && (win->state&SF_SELECTED))?1:0);
-  wattrset(window, color);
-  box(window, ACS_VLINE, ACS_HLINE);
-  if (!(t= strdup(((class cl_win *)win)->get_title())))
-    return(0);
-  if ((signed)strlen(t) > (pos->w)-4)
-    t[(pos->w)-4]= '\0';
-  mvwprintw(window, 0,((pos->w)-strlen(t))/2, "[%s]", t);
-  free(t);
-  app->drawn++;
-  return(0);
-}
-
-
-/* End of gui.src/frame.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/gui.src/obsolete/framecl.h sdcc-4.2.0+dfsg/sim/ucsim/gui.src/obsolete/framecl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/gui.src/obsolete/framecl.h	2001-04-02 13:08:48.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/gui.src/obsolete/framecl.h	1970-01-01 00:00:00.000000000 +0000
@@ -1,48 +0,0 @@
-/*
- * Simulator of microcontrollers (framecl.h)
- *
- * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
- * 
- * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
- *
- */
-
-/* This file is part of microcontroller simulator: ucsim.
-
-UCSIM is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2 of the License, or
-(at your option) any later version.
-
-UCSIM is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with UCSIM; see the file COPYING.  If not, write to the Free
-Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-02111-1307, USA. */
-/*@1@*/
-
-#ifndef FRAMELCL_HEADER
-#define FRAMELCL_HEADER
-
-#include "viewcl.h"
-#include "appcl.h"
-
-
-class cl_frame: public cl_view
-{
-  class cl_view *win;
-public:
-  cl_frame(class cl_box *ipos, class cl_view *iwindow, char *iname,
-	   class cl_app *iapp);
-  virtual int *mk_palette(void);
-  virtual int draw(void);
-};
-
-
-#endif
-
-/* End of gui.src/framecl.h */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/gui.src/obsolete/group.cc sdcc-4.2.0+dfsg/sim/ucsim/gui.src/obsolete/group.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/gui.src/obsolete/group.cc	2001-04-02 13:08:48.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/gui.src/obsolete/group.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,393 +0,0 @@
-/*
- * Simulator of microcontrollers (group.cc)
- *
- * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
- * 
- * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
- *
- */
-
-/* This file is part of microcontroller simulator: ucsim.
-
-UCSIM is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2 of the License, or
-(at your option) any later version.
-
-UCSIM is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with UCSIM; see the file COPYING.  If not, write to the Free
-Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-02111-1307, USA. */
-/*@1@*/
-
-#include "groupcl.h"
-#include "appcl.h"
-
-
-cl_group::cl_group(class cl_box *ipos, char *iname, class cl_app *iapp):
-  cl_view(ipos, iname, iapp)
-{
-  current= 0;
-}
-
-cl_group::cl_group(char *iname, class cl_app *iapp):
-  cl_view(iname, iapp)
-{
-  current= 0;
-}
-
-cl_group::~cl_group(void)
-{}
-
-int
-cl_group::init(void)
-{
-  cl_view::init();
-  mk_views(this);
-  return(0);
-}
-
-int
-cl_group::mk_views(class cl_group *ins_to)
-{
-  return(0);
-}
-
-
-/*
- * Make output by drawing all subviews
- */
-
-static void do_draw_view(class cl_view *view)
-{
-  view->draw();
-}
-
-int
-cl_group::draw(void)
-{
-  /*int i;
-
-  for (i= 0; i < views->count; i++)
-    {
-      class cl_view *v= (class cl_view *)(views->at(i));
-      v->draw();
-      app->drawn++;
-      }*/
-  for_each(do_draw_view);
-  return(0);
-}
-
-/*int
-cl_group::update(void)
-{
-  draw();
-  update_panels();
-  doupdate();
-}*/
-
-
-int
-cl_group::handle_event(struct t_event *event)
-{
-  int handled= 0;
-
-  if (event->what & (EV_KEY|EV_COMMAND))
-    {
-      if (current)
-	handled= current->handle_event(event);
-    }
-  else if (event->what & EV_MESSAGE)
-    {
-      class cl_view *v= last;
-      do 
-	{
-	  handled= v->handle_event(event);
-	  v= v->next;
-	}
-      while (! handled &&
-	     v != last);
-    }
-  return(handled);
-}
-
-
-/*
- * Managing views
- */
-
-//class cl_view *
-void
-cl_group::insert(class cl_view *view)
-{
-  /*if (view &&
-      view->ok())
-    {
-      views->add_at(0, view);
-      view->parent= this;
-      view->select();
-      //view->draw();
-      return(view);
-      }
-      return(0);*/
-  insert_before(view, first());
-  if (view->options & OF_SELECTABLE)
-    view->select();
-  draw();
-}
-
-void
-cl_group::insert_before(class cl_view *view, class cl_view *target)
-{
-  unsigned int ss;
-
-  if (view &&
-      !(view->parent) &&
-      (!target ||
-       target->parent == this))
-    {
-      ss= view->state;
-      //view->hide();
-      insert_view(view, target);
-      /*if (ss & SF_VISIBLE)
-	view->show();*/
-      if (state & SF_ACTIVE)
-	view->change_state(SF_ACTIVE, 1);
-    }
-}
-
-void
-cl_group::insert_view(class cl_view *view, class cl_view *target)
-{
-  view->parent= this;
-  if (target)
-    {
-      target= target->prev();
-      view->next= target->next;
-      target->next= view;
-    }
-  else
-    {
-      if (!last)
-	view->next= view;
-      else
-	{
-	  view->next= last->next;
-	  last->next= view;
-	}
-      last= view;
-    }
-}
-
-class cl_view *
-cl_group::first(void)
-{
-  if (!last)
-    return(0);
-  return(last->next);
-}
-
-
-/*class cl_view *
-cl_group::get_by_state(unsigned int what, int enabled)
-{
-  int i;
-
-  for (i= 0; i < views->count; i++)
-    {
-      class cl_view *v= (class cl_view *)(views->at(i));
-      if ((enabled &&
-	   (state&what))
-	  ||
-	  (!enabled &&
-	   ((~state)&what))
-	  )
-	return(v);
-    }
-  return(0);
-}*/
-
-/*int
-cl_group::select(void)
-{
-}*/
-
-/*int
-cl_group::unselect(void)
-{
-}*/
-
-int
-cl_group::select_next()
-{
-  /*  int start, i;
-  class cl_view *v;
-
-  if (views->count <= 1)
-    return(1);
-  if (current)
-    start= views->index_of(current);
-  else
-    if ((v= get_by_state(SF_SELECTED, 1)))
-      start= views->index_of(v);
-    else
-      if ((v= get_by_state(SF_FOCUSED, 1)))
-	start= views->index_of(v);
-      else
-	start= 0;
-  i= (start+1)%(views->count);
-  while (i != start)
-    {
-      v= (class cl_view *)(views->at(i));
-      if ((v->options & OF_SELECTABLE) &&
-	  v->select())
-	{
-	  //update();
-	  return(1);
-	}
-      i= (i+1)%(views->count);
-      }*/
-  return(0);
-}
-
-int
-cl_group::select_prev()
-{
-  /*  int start, i;
-  class cl_view *v;
-
-  if (views->count <= 1)
-    return(1);
-  if (current)
-    start= views->index_of(current);
-  else
-    if ((v= get_by_state(SF_SELECTED, 1)))
-      start= views->index_of(v);
-    else
-      if ((v= get_by_state(SF_FOCUSED, 1)))
-	start= views->index_of(v);
-      else
-	start= 0;
-  i= start-1; if (i < 0) i= views->count-1;
-  while (i != start)
-    {
-      v= (class cl_view *)(views->at(i));
-      if ((v->options & OF_SELECTABLE) &&
-	  v->select())
-	{
-	  //update();
-	  return(1);
-	}
-      i= start-1; if (i < 0) i= views->count-1;
-      }*/
-  return(0);
-}
-
-class cl_view *
-cl_group::current_sub_view(void)
-{
-  return(current);
-}
-
-void
-cl_group::for_each(void (*func)(class cl_view *view))
-{
-  class cl_view *v;
-
-  if (!last)
-    return;
-  v= last->next;
-  do
-    {
-      func(v);
-      v= v->next;
-    }
-  while (v != last);
-}
-
-void
-cl_group::set_current(class cl_view *view)
-{
-  //current= view;
-  if (current == view)
-    return;
-  //lock();
-  /*focus_view(view, 0);*/
-  if ((state & SF_FOCUSED) &&
-      (current != 0))
-    current->change_state(SF_FOCUSED, 0);
-  //if (mode!=ENTER_SELECT) select_view(current, 0);
-  if (current)
-    current->change_state(SF_SELECTED, 0);
-  //if (mode!=LEAVE_SELECT) select_view(view, 1);
-  if (view)
-    view->change_state(SF_SELECTED, 1);
-  //focuse_view(view, 1);
-  if ((state & SF_FOCUSED) &&
-      (view != 0))
-    view->change_state(SF_SELECTED, 1);
-  current= view;
-  //unlock();
-}
-
-/*int
-cl_group::terminal_view(void)
-{
-  return(views->count == 0);
-}*/
-
-static unsigned int grp_what, grp_en;
-
-static void
-do_set_state(class cl_view *v)
-{
-  v->change_state(grp_what, grp_en);
-}
-
-void
-cl_group::change_state(unsigned int what, int enable)
-{
-  cl_view::change_state(what, enable);
-  /*if (enable &&
-      (what & SF_SELECTED))
-    {
-      class cl_view *v= get_by_state(SF_SELECTED, 1);
-      if (v)
-	{
-	  current= v;
-	  current->change_state(SF_FOCUSED, 1);
-	  current->change_state(SF_SELECTED, 1);
-	}
-      else
-	{
-	  if ((v= get_by_state(SF_FOCUSED, 1)))
-	    {
-	      current= v;
-	      current->change_state(SF_SELECTED, 1);
-	    }
-	}
-	}*/
-  switch (what)
-    {
-      case SF_ACTIVE:
-	//lock();
-	grp_what= what;
-	grp_en= enable;
-	for_each(do_set_state);
-	//unlock();
-	break;
-    case SF_FOCUSED:
-      if (current)
-	current->change_state(SF_FOCUSED, enable);
-      break;
-    }
-  draw();
-}
-
-
-/* End of gui.src/group.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/gui.src/obsolete/groupcl.h sdcc-4.2.0+dfsg/sim/ucsim/gui.src/obsolete/groupcl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/gui.src/obsolete/groupcl.h	2001-04-02 13:08:48.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/gui.src/obsolete/groupcl.h	1970-01-01 00:00:00.000000000 +0000
@@ -1,70 +0,0 @@
-/*
- * Simulator of microcontrollers (groupcl.h)
- *
- * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
- * 
- * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
- *
- */
-
-/* This file is part of microcontroller simulator: ucsim.
-
-UCSIM is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2 of the License, or
-(at your option) any later version.
-
-UCSIM is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with UCSIM; see the file COPYING.  If not, write to the Free
-Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-02111-1307, USA. */
-/*@1@*/
-
-#ifndef GROUPCL_HEADER
-#define GROUPCL_HEADER
-
-#include "viewcl.h"
-
-class cl_group: public cl_view
-{
-public:
-  class cl_view *current;
-
-public:
-  cl_group(class cl_box *ipos, char *iname, class cl_app *iapp);
-  cl_group(char *iname, class cl_app *iapp);
-  ~cl_group(void);
-  virtual int init(void);
-  virtual int mk_views(class cl_group *ins_to);
-  virtual int is_group(void) {return(1);}
-
-  virtual int draw(void);
-  //virtual int update(void);
-
-  virtual int handle_event(struct t_event *event);
-
-  virtual /*class cl_view **/void insert(class cl_view *view);
-  virtual void insert_before(class cl_view *view, class cl_view *target);
-  virtual void insert_view(class cl_view *view, class cl_view *target);
-  virtual class cl_view *first(void);
-  virtual void for_each(void (*func)(class cl_view *view));
-  //virtual class cl_view *get_by_state(unsigned int what, int enabled);
-  //virtual int select(void);
-  //virtual int unselect(void);
-  virtual int select_next();
-  virtual int select_prev();
-  virtual class cl_view *current_sub_view(void);
-  virtual void set_current(class cl_view *view);
-  //virtual int terminal_view(void);
-  virtual void change_state(unsigned int what, int enable);
-};
-
-
-#endif
-
-/* End of gui.src/groupcl.h */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/gui.src/obsolete/label.cc sdcc-4.2.0+dfsg/sim/ucsim/gui.src/obsolete/label.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/gui.src/obsolete/label.cc	2001-04-02 13:08:48.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/gui.src/obsolete/label.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,74 +0,0 @@
-/*
- * Simulator of microcontrollers (label.cc)
- *
- * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
- * 
- * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
- *
- */
-
-/* This file is part of microcontroller simulator: ucsim.
-
-UCSIM is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2 of the License, or
-(at your option) any later version.
-
-UCSIM is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with UCSIM; see the file COPYING.  If not, write to the Free
-Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-02111-1307, USA. */
-/*@1@*/
-
-#include "ddconfig.h"
-
-#include 
-#include "i_string.h"
-
-#include "labelcl.h"
-
-
-cl_label::cl_label(class cl_box *ipos, class cl_app *iapp, char *ilabel):
-  cl_view(ipos, "label", iapp)
-{
-  options&= ~OF_SELECTABLE;
-  if (!ilabel ||
-      !(*ilabel))
-    label= strdup("");
-  else
-    label= strdup(ilabel);
-}
-
-cl_label::~cl_label(void)
-{
-  free(label);
-}
-
-int *
-cl_label::mk_palette(void)
-{
-  int *p;
-
-  p= (int*)malloc(1*sizeof(int));
-  p[0]= C_WIN_NORMAL;
-  return(p);
-}
-
-int
-cl_label::draw(void)
-{
-  int color= get_color(0);
-
-  cl_view::draw();
-  wattrset(window, color);
-  mvwprintw(window, 0,0, "%s", label);
-  return(0);
-}
-
-
-/* End of gui.src/label.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/gui.src/obsolete/labelcl.h sdcc-4.2.0+dfsg/sim/ucsim/gui.src/obsolete/labelcl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/gui.src/obsolete/labelcl.h	2001-04-02 13:08:48.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/gui.src/obsolete/labelcl.h	1970-01-01 00:00:00.000000000 +0000
@@ -1,50 +0,0 @@
-/*
- * Simulator of microcontrollers (labelcl.h)
- *
- * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
- * 
- * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
- *
- */
-
-/* This file is part of microcontroller simulator: ucsim.
-
-UCSIM is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2 of the License, or
-(at your option) any later version.
-
-UCSIM is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with UCSIM; see the file COPYING.  If not, write to the Free
-Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-02111-1307, USA. */
-/*@1@*/
-
-#ifndef LABELCL_HEADER
-#define LABELCL_HEADER
-
-
-#include "viewcl.h"
-#include "appcl.h"
-
-
-class cl_label: public cl_view
-{
-public:
-  char *label;
-public:
-  cl_label(class cl_box *ipos, class cl_app *iapp, char *ilabel);
-  ~cl_label(void);
-  virtual int *mk_palette(void);
-  virtual int draw(void);
-};
-
-
-#endif
-
-/* End of gui.src/labelcl.h */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/gui.src/obsolete/palette.h sdcc-4.2.0+dfsg/sim/ucsim/gui.src/obsolete/palette.h
--- sdcc-4.0.0+dfsg/sim/ucsim/gui.src/obsolete/palette.h	2001-04-02 13:08:48.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/gui.src/obsolete/palette.h	1970-01-01 00:00:00.000000000 +0000
@@ -1,44 +0,0 @@
-/*
- * Simulator of microcontrollers (palette.h)
- *
- * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
- * 
- * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
- *
- */
-
-/* This file is part of microcontroller simulator: ucsim.
-
-UCSIM is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2 of the License, or
-(at your option) any later version.
-
-UCSIM is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with UCSIM; see the file COPYING.  If not, write to the Free
-Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-02111-1307, USA. */
-/*@1@*/
-
-#ifndef PALETTE_HEADER
-#define PALETTE_HEADER
-
-
-#define C_DSK_BG		1
-#define C_DSK_NORMAL		2
-#define C_DSK_DISABLED		3
-
-#define C_WIN			8
-#define C_WIN_FPASSIVE		0
-#define C_WIN_FACTIVE		1
-#define C_WIN_NORMAL		5
-#define C_WIN_SELECTED		6
-
-#endif
-
-/* End of gui.src/palette.h */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/gui.src/obsolete/portmon.src/(c).1 sdcc-4.2.0+dfsg/sim/ucsim/gui.src/obsolete/portmon.src/(c).1
--- sdcc-4.0.0+dfsg/sim/ucsim/gui.src/obsolete/portmon.src/(c).1	2001-04-02 13:08:48.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/gui.src/obsolete/portmon.src/(c).1	1970-01-01 00:00:00.000000000 +0000
@@ -1,25 +0,0 @@
-/*
- * Simulator of microcontrollers (@@F@@)
- *
- * Copyright (C) @@S@@,@@Y@@ Drotos Daniel, Talker Bt.
- * 
- * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
- *
- */
-
-/* This file is part of microcontroller simulator: ucsim.
-
-UCSIM is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2 of the License, or
-(at your option) any later version.
-
-UCSIM is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with UCSIM; see the file COPYING.  If not, write to the Free
-Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-02111-1307, USA. */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/gui.src/obsolete/portmon.src/clean.mk sdcc-4.2.0+dfsg/sim/ucsim/gui.src/obsolete/portmon.src/clean.mk
--- sdcc-4.0.0+dfsg/sim/ucsim/gui.src/obsolete/portmon.src/clean.mk	2001-04-02 13:08:48.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/gui.src/obsolete/portmon.src/clean.mk	1970-01-01 00:00:00.000000000 +0000
@@ -1,28 +0,0 @@
-# uCsim gui.src/portmon.src/clean.mk
-
-# Deleting all files created by building the program
-# --------------------------------------------------
-clean:
-	rm -f *core *[%~] *.[oa]
-	rm -f .[a-z]*~
-	rm -f portmon
-
-
-# Deleting all files created by configuring or building the program
-# -----------------------------------------------------------------
-distclean: clean
-	rm -f config.cache config.log config.status
-	rm -f Makefile *.dep
-
-
-# Like clean but some files may still exist
-# -----------------------------------------
-mostlyclean: clean
-
-
-# Deleting everything that can reconstructed by this Makefile. It deletes
-# everything deleted by distclean plus files created by bison, etc.
-# -----------------------------------------------------------------------
-realclean: distclean
-
-# End of gui.src/portmon.src/clean.mk
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/gui.src/obsolete/portmon.src/conf.mk sdcc-4.2.0+dfsg/sim/ucsim/gui.src/obsolete/portmon.src/conf.mk
--- sdcc-4.0.0+dfsg/sim/ucsim/gui.src/obsolete/portmon.src/conf.mk	2016-07-29 14:28:30.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/gui.src/obsolete/portmon.src/conf.mk	1970-01-01 00:00:00.000000000 +0000
@@ -1,12 +0,0 @@
-# uCsim gui.src/portmon.src/conf.mk
-
-#
-# Makefile targets to remake configuration
-#
-
-freshconf: Makefile
-
-Makefile: $(srcdir)/Makefile.in $(top_srcdir)/configure.ac
-	cd $(top_builddir) && $(SHELL) ./config.status
-
-# End of gui.src/portmon.src/conf.mk
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/gui.src/obsolete/portmon.src/Makefile.in sdcc-4.2.0+dfsg/sim/ucsim/gui.src/obsolete/portmon.src/Makefile.in
--- sdcc-4.0.0+dfsg/sim/ucsim/gui.src/obsolete/portmon.src/Makefile.in	2010-03-23 20:59:47.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/gui.src/obsolete/portmon.src/Makefile.in	1970-01-01 00:00:00.000000000 +0000
@@ -1,131 +0,0 @@
-#
-# uCsim gui.src/portmon.src/Makefile
-#
-# (c) Drotos Daniel, Talker Bt. 1999
-#
-
-SHELL		= /bin/sh
-CXX		= @CXX@
-CPP		= @CPP@
-CXXCPP		= @CXXCPP@
-RANLIB		= @RANLIB@
-INSTALL		= @INSTALL@
-MAKEDEP         = @MAKEDEP
-
-top_builddir	= @top_builddir@
-top_srcdir	= @top_srcdir@
-PKGDIR		= ../
-
-DEFS            = $(subs -DHAVE_CONFIG_H,,@DEFS@)
-CPPFLAGS        = @CPPFLAGS@ -I. -I$(top_builddir) -I$(PKGDIR)
-CFLAGS          = @CFLAGS@ @WALL_FLAG@
-CXXFLAGS        = @CXXFLAGS@ @WALL_FLAG@
-
-LIBS		= -L$(top_builddir) -L$(PKGDIR) -lgui @CURSES_LIBS@ -lutil @LIBS@
-
-curses_ok	= @curses_ok@
-
-prefix          = @prefix@
-exec_prefix     = @exec_prefix@
-bindir          = @bindir@
-libdir          = @libdir@
-datadir         = @datadir@
-includedir      = @includedir@
-mandir          = @mandir@
-man1dir         = $(mandir)/man1
-man2dir         = $(mandir)/man2
-infodir         = @infodir@
-srcdir          = @srcdir@
-
-OBJECTS         = portmon.o \
-		  pmapp.o port.o
-
-
-# Compiling entire program or any subproject
-# ------------------------------------------
-all: checkconf otherlibs portmon.src
-
-
-# Compiling and installing everything and runing test
-# ---------------------------------------------------
-install: all installdirs
-	$(INSTALL) -s portmon $(bindir)
-
-
-# Deleting all the installed files
-# --------------------------------
-uninstall:
-	rm -f $(bindir)/portmon
-
-
-# Performing self-test
-# --------------------
-check:
-
-
-# Performing installation test
-# ----------------------------
-installcheck:
-
-
-# Creating installation directories
-# ---------------------------------
-installdirs:
-	test -d $(bindir) || $(INSTALL) -d $(bindir)
-
-
-# Creating dependencies
-# ---------------------
-dep: Makefile.dep
-
-Makefile.dep: $(srcdir)/*.cc $(top_builddir)/*.h $(PKGDIR)/*.h
-	$(MAKEDEP) $(CPPFLAGS) $(filter %.cc,$^) >Makefile.dep
-
--include Makefile.dep
-include clean.mk
-
-#parser.cc: parser.y
-
-#plex.cc: plex.l
-
-# My rules
-# --------
-ifeq ($(curses_ok),yes)
-portmon.src: portmon
-else
-portmon.src:
-endif
-
-portmon: $(OBJECTS) $(top_builddir)/*.a $(PKGDIR)/*.a
-	$(CXX) $(CXXFLAGS) -o portmon $(OBJECTS) $(LIBS)
-
-ifeq ($(curses_ok),yes)
-otherlibs:
-	$(MAKE) -C $(top_builddir) libs
-	$(MAKE) -C $(PKGDIR) libs
-else
-otherlibs:
-endif
-
-.cc.o:
-	$(CXX) $(CXXFLAGS) $(CPPFLAGS) -c $< -o $@
-
-.y.cc:
-	rm -f $*.cc $*.h
-	$(YACC) -d $<
-	mv y.tab.c $*.cc
-	mv y.tab.h $*.h
-
-.l.cc:
-	rm -f $*.cc
-	$(LEX) -t $< >$*.cc
-
-
-# Remaking configuration
-# ----------------------
-checkconf:
-	@if [ -f $(top_builddir)/devel ]; then\
-	  $(MAKE) -f conf.mk srcdir="$(srcdir)" top_builddir="$(top_builddir)" freshconf;\
-	fi
-
-# End of gui.src/portmon.src/Makefile.in
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/gui.src/obsolete/portmon.src/pmapp.cc sdcc-4.2.0+dfsg/sim/ucsim/gui.src/obsolete/portmon.src/pmapp.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/gui.src/obsolete/portmon.src/pmapp.cc	2001-04-02 13:08:48.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/gui.src/obsolete/portmon.src/pmapp.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,113 +0,0 @@
-/*
- * Simulator of microcontrollers (pmapp.cc)
- *
- * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
- * 
- * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
- *
- */
-
-/* This file is part of microcontroller simulator: ucsim.
-
-UCSIM is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2 of the License, or
-(at your option) any later version.
-
-UCSIM is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with UCSIM; see the file COPYING.  If not, write to the Free
-Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-02111-1307, USA. */
-/*@1@*/
-
-#include "wincl.h"
-#include "labelcl.h"
-
-#include "pmappcl.h"
-#include "portcl.h"
-
-
-int
-cl_pmapp::mk_views(class cl_group *ins_to)
-{
-  class cl_view *v;
-  //class cl_win *w;
-  class cl_box *b;
-  
-  b= new cl_box(0,0,0,0);
-
-  if (!ins_to)
-    return(0);
-  
-  b->set(43,2,14,13);
-  v= new cl_portw(b, 3, "Port #3", this);
-  v->init();
-  ins_to->insert(v);
-    
-  b->set(29,2,14,13);
-  v= new cl_portw(b, 2, "Port #2", this);
-  v->init();
-  ins_to->insert(v);
-  /*
-  b->set(15,2,14,13);
-  ins_to->insert(v= new cl_portw(b, 1, "Port #1", this));
-  v->init();
-
-  b->set(1,2,14,13);
-  ins_to->insert(v= new cl_portw(b, 0, "Port #0", this));
-  v->init();
-
-  b->set(59,3,19,11);
-  v= new cl_label(b, this,
-"Next win: n,TAB\nPrev win: p\nCursor  : u,d,l,r,\n          arrows\nToggle  : space,CR\nQuit    : q");
-  v->init();
-  b->move_rel(-1,-1);
-  b->grow(2,2);
-  
-  b->set(58,2,21,13);
-  w= new cl_win(b, "Help", this);
-  w->options&= ~OF_SELECTABLE;
-  w->init();
-  w->insert(v);
-  ins_to->insert(w);
-  w->draw();
-  */
-  delete b;
-
-  return(0);
-}
-
-int *
-cl_pmapp::mk_palette(void)
-{
-  return(cl_app::mk_palette());
-}
-
-int
-cl_pmapp::handle_event(struct t_event *event)
-{
-  if (event->what == EV_KEY)
-    switch (event->event.key)
-      {
-      case 'q':
-	event->what= EV_COMMAND;
-	event->event.msg.cmd= CMD_QUIT;
-	return(0);
-      case 'p':
-	desk->select_prev();
-	return(1);
-      case 'n': case '\t':
-	desk->select_next();
-	return(1);
-	
-      }
-  return(cl_app::handle_event(event));
-}
-
-
-/* End of gui.src/portmon.src/pmapp.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/gui.src/obsolete/portmon.src/pmappcl.h sdcc-4.2.0+dfsg/sim/ucsim/gui.src/obsolete/portmon.src/pmappcl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/gui.src/obsolete/portmon.src/pmappcl.h	2001-04-02 13:08:48.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/gui.src/obsolete/portmon.src/pmappcl.h	1970-01-01 00:00:00.000000000 +0000
@@ -1,48 +0,0 @@
-/*
- * Simulator of microcontrollers (pmappcl.h)
- *
- * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
- * 
- * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
- *
- */
-
-/* This file is part of microcontroller simulator: ucsim.
-
-UCSIM is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2 of the License, or
-(at your option) any later version.
-
-UCSIM is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with UCSIM; see the file COPYING.  If not, write to the Free
-Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-02111-1307, USA. */
-/*@1@*/
-
-#ifndef PMAPPCL_HEADER
-#define PMAPPCL_HEADER
-
-#include "appcl.h"
-
-
-class cl_pmapp: public cl_app
-{
-public:
-  cl_pmapp(char *iname): cl_app(iname) {}
-
-  virtual int mk_views(class cl_group *ins_to);
-  virtual int *mk_palette(void);
-
-  virtual int handle_event(struct t_event *event);
-};
-
-
-#endif
-
-/* End of gui.src/portmon.src/pmappcl.h */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/gui.src/obsolete/portmon.src/port.cc sdcc-4.2.0+dfsg/sim/ucsim/gui.src/obsolete/portmon.src/port.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/gui.src/obsolete/portmon.src/port.cc	2001-04-02 13:08:48.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/gui.src/obsolete/portmon.src/port.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,143 +0,0 @@
-/*@1@*/
-
-#include "portcl.h"
-
-
-/*
- * Viewer of the port
- */
-
-cl_port::cl_port(class cl_box *ipos, int iid, char *iname, class cl_app *iapp):
-  cl_view(ipos, iname, iapp)
-{
-  id= iid;
-  sfr= 0;
-  pin= 0;
-  curs_x= curs_y= 0;
-}
-
-int
-cl_port::draw(void)
-{
-  int x, y, mask, hc, nc;
-
-  cl_view::draw();
-
-  nc= hc= get_color(C_WIN_NORMAL);
-  if (state & SF_SELECTED)
-    hc= get_color(C_WIN_SELECTED);
-  mvwprintw(window, 0,0, "SFR PORT PIN");
-  for (x= 0, mask= 0x80, y= 1; mask; mask>>= 1,y++)
-    {
-      wattrset(window, (curs_x)?nc:(curs_y==y-1?hc:nc));
-      mvwprintw(window, y,x, "  %c", (sfr&mask)?'1':'0');
-    }
-  wattrset(window, nc);
-  for (x= 5, mask= 0x80, y= 1; mask; mask>>= 1,y++)
-    mvwprintw(window, y,x, "%c", (sfr&pin&mask)?'1':'0');
-  for (x=9, mask= 0x80, y= 1; mask; mask>>= 1,y++)
-    {
-      wattrset(window, curs_x?(curs_y==y-1?hc:nc):nc);
-      mvwprintw(window, y,x, "%c  ", (pin&mask)?'1':'0');
-    }
-  wattrset(window, nc);
-  mvwprintw(window, 9,0, "0x%02x    0x%02x", sfr, pin);
-  mvwprintw(window, 10,4, "0x%02x", sfr&pin);
-  app->drawn++;
-  return(0);
-}
-
-int
-cl_port::handle_event(struct t_event *event)
-{
-  if (event->what == EV_KEY)
-    switch (event->event.key)
-      {
-      case KEY_HOME:
-	curs_y= 0; draw(); return(1);
-      case KEY_A1:
-	curs_x= curs_y= 0; draw(); return(1);
-      case KEY_A3:
-	curs_y= 0; curs_x= 1; draw(); return(1);
-      case KEY_C1:
-	curs_x= 0; curs_y= 7; draw(); return(1);
-      case KEY_C3:
-	curs_x= 1; curs_y= 7; draw(); return(1);
-      case KEY_LEFT: case KEY_RIGHT: case 'j': case 'k': case 'l': case 'r':
-	if (curs_x)
-	  curs_x= 0;
-	else
-	  curs_x= 1;
-	draw();
-	return(1);
-      case KEY_UP: case 'u':
-	curs_y--;
-	if (curs_y < 0)
-	  curs_y= 7;
-	draw();
-	return(1);
-      case KEY_DOWN: case 'd':
-	curs_y++;
-	if (curs_y > 7)
-	  curs_y= 0;
-	draw();
-	return(1);
-      case ' ': case '\n': case '\r':
-	if (curs_x)
-	  toggle_pin(7-curs_y);
-	else
-	  toggle_sfr(7-curs_y);
-	return(1);
-      }
-  return(cl_view::handle_event(event));
-}
-
-int
-cl_port::toggle_sfr(int bitnr)
-{
-  int mask= 1<init();
-  return(v);
-}
-
-int
-cl_portw::handle_event(struct t_event *event)
-{
-  return(cl_win::handle_event(event));
-}
-
-
-/* End of gui.src/portmap.src/port.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/gui.src/obsolete/portmon.src/portcl.h sdcc-4.2.0+dfsg/sim/ucsim/gui.src/obsolete/portmon.src/portcl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/gui.src/obsolete/portmon.src/portcl.h	2001-04-02 13:08:48.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/gui.src/obsolete/portmon.src/portcl.h	1970-01-01 00:00:00.000000000 +0000
@@ -1,64 +0,0 @@
-/*
- * Simulator of microcontrollers (portcl.h)
- *
- * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
- * 
- * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
- *
- */
-
-/* This file is part of microcontroller simulator: ucsim.
-
-UCSIM is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2 of the License, or
-(at your option) any later version.
-
-UCSIM is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with UCSIM; see the file COPYING.  If not, write to the Free
-Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-02111-1307, USA. */
-/*@1@*/
-
-#ifndef PORTCL_HEADER
-#define PORTCL_HEADER
-
-#include "viewcl.h"
-#include "wincl.h"
-
-
-class cl_port: public cl_view
-{
-public:
-  int id;
-  int sfr, pin;
-  int curs_x, curs_y;
-public:
-  cl_port(class cl_box *ipos, int iid, char *iname, class cl_app *iapp);
-
-  virtual int draw(void);
-  virtual int handle_event(struct t_event *event);
-  int toggle_sfr(int bitnr);
-  int toggle_pin(int bitnr);
-};
-
-class cl_portw: public cl_win
-{
-public:
-  int id;
-public:
-  cl_portw(class cl_box *ipos, int iid, char *ititle, class cl_app *iapp);
-  virtual class cl_view *mk_intern(class cl_box *ipos);
-
-  virtual int handle_event(struct t_event *event);
-};
-
-
-#endif
-
-/* End of gui.src/portmon.src/portcl.h */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/gui.src/obsolete/portmon.src/portmon.cc sdcc-4.2.0+dfsg/sim/ucsim/gui.src/obsolete/portmon.src/portmon.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/gui.src/obsolete/portmon.src/portmon.cc	2001-04-02 13:08:48.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/gui.src/obsolete/portmon.src/portmon.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,68 +0,0 @@
-/*
- * Simulator of microcontrollers (portmon.cc)
- *
- * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
- * 
- * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
- *
- */
-
-/* This file is part of microcontroller simulator: ucsim.
-
-UCSIM is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2 of the License, or
-(at your option) any later version.
-
-UCSIM is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with UCSIM; see the file COPYING.  If not, write to the Free
-Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-02111-1307, USA. */
-/*@1@*/
-
-#include 
-
-#include "pmappcl.h"
-
-
-class cl_pmapp *app;
-
-void xx(class cl_view *v)
-{
-  fprintf(stderr,"%s 0x%x ", v->name, v->state);
-}
-
-int
-main(int argc, char *argv)
-{
-  app= new cl_pmapp("portmon");
-  app->init();
-  {
-    class cl_view *v= app;
-    while (v)
-      {
-	if (v->is_group())
-	  {
-	    class cl_group *g= (class cl_group *)v;
-	    fprintf(stderr, "%s->%s\n", g->name,(g->current)?(g->current->name):"none");
-	    g->for_each(xx);
-	    fprintf(stderr, "\n");
-	    v= g->current;
-	  }
-	else
-	  v= 0;
-      }
-  }
-  app->run();
-  //getch();
-  delete app;
-  return(0);
-}
-
-
-/* End of gui.src/portmon.src/portmon.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/gui.src/obsolete/view.cc sdcc-4.2.0+dfsg/sim/ucsim/gui.src/obsolete/view.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/gui.src/obsolete/view.cc	2001-04-02 13:08:48.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/gui.src/obsolete/view.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,356 +0,0 @@
-/*
- * Simulator of microcontrollers (view.cc)
- *
- * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
- * 
- * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
- *
- */
-
-/* This file is part of microcontroller simulator: ucsim.
-
-UCSIM is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2 of the License, or
-(at your option) any later version.
-
-UCSIM is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with UCSIM; see the file COPYING.  If not, write to the Free
-Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-02111-1307, USA. */
-/*@1@*/
-
-#include "ddconfig.h"
-
-#include 
-#include "i_string.h"
-
-#include "appcl.h"
-
-
-/*
- * Box
- */
-
-cl_box::cl_box(int ix, int iy, int iw, int ih):
-  cl_base()
-{
-  x= ix;
-  y= iy;
-  w= iw;
-  h= ih;
-}
-
-void
-cl_box::set(int ix, int iy, int iw, int ih)
-{
-  x= ix;
-  y= iy;
-  w= iw;
-  h= ih;
-}
-
-void
-cl_box::move_rel(int dx, int dy)
-{
-  x+= dx;
-  y+= dy;
-}
-
-void
-cl_box::grow(int dw, int dh)
-{
-  w+= dw;
-  h+= dh;
-}
-
-
-/*
- * Astbract of a viewer
- ******************************************************************************
- */
-
-cl_view::cl_view(class cl_box *ipos, char *iname, class cl_app *iapp):
-  cl_base()
-{
-  pos= new cl_box(ipos->x,ipos->y, ipos->w,ipos->h);
-  if ((window= newwin(pos->h,pos->w, pos->y,pos->x)))
-    {
-      leaveok(window, TRUE);
-      panel= new_panel(window);
-    }
-  else
-    {
-      panel= 0;
-      delwin(window);
-      window= 0;
-    }
-  parent= 0;
-  next= last= 0;
-  app= iapp;
-  state= SF_NOTHING;
-  options= OF_SELECTABLE;
-  if (!iname ||
-      !(*iname))
-    {
-      name= (char*)malloc(100);
-      sprintf(name, "view%p", this);
-    }
-  else
-    name= strdup(iname);
-}
-
-cl_view::cl_view(char *iname, class cl_app *iapp):
-  cl_base()
-{
-  window= 0;
-  panel= 0;
-  parent= 0;
-  next= last= 0;
-  app= iapp;
-  state= SF_NOTHING;
-  options= OF_SELECTABLE;
-  if (!iname ||
-      !(*iname))
-    {
-      name= (char*)malloc(100);
-      sprintf(name, "view%p", this);
-    }
-  else
-    name= strdup(iname);
-}
-
-cl_view::~cl_view(void)
-{
-  if (panel)
-    del_panel(panel);
-  if (window)
-    delwin(window);
-  if (palette)
-    free(palette);
-  if (name)
-    free(name);
-}
-
-int
-cl_view::init(void)
-{
-  input= mk_input();
-  palette= mk_palette();
-  //draw();
-  return(0);
-}
-
-class cl_gin *
-cl_view::mk_input(void)
-{
-  return(0);
-}
-
-int *
-cl_view::mk_palette(void)
-{
-  return(0);
-}
-
-int
-cl_view::ok(void)
-{
-  return(window && panel);
-}
-
-
-/*
- * Make output into the view
- */
-
-int
-cl_view::draw(void)
-{
-  int color, x, y;
-
-  color= get_color(palette?0:C_WIN_NORMAL);
-  
-  wattrset(window, color);
-  for (y= 0; y < pos->h; y++)
-    for (x= 0; x < pos->w; x++)
-      mvwaddch(window, y,x, ' ');
-  app->drawn++;
-
-  return(0);
-}
-
-int
-cl_view::update(void)
-{
-  draw();
-  update_panels();
-  doupdate();
-  return(0);
-}
-
-int
-cl_view::get_color(int color)
-{
-  int *p;
-  class cl_view *v;
-
-  v= this;
-  while (v)
-    {
-      p= v->get_palette();
-      if (p)
-	color= p[color];
-      v= v->parent;
-    }
-  return(color);
-}
-
-int *
-cl_view::get_palette(void)
-{
-  return(palette);
-}
-
-
-/*
- * Event handling
- */
-
-int
-cl_view::get_event(struct t_event *event)
-{
-  if (parent)
-    return(parent->get_event(event));
-  if (input)
-    return(input->get_event(event));
-  return(0);
-}
-
-int
-cl_view::handle_event(struct t_event *event)
-{
-  return(0);
-}
-
-int
-cl_view::unhandled(struct t_event *event)
-{
-  return(0);
-}
-
-int
-cl_view::mk_event(struct t_event *event, FILE *f, int key)
-{
-  event->what= EV_KEY;
-  event->event.key= key;
-  return(1);
-}
-
-
-class cl_view *
-cl_view::prev(void)
-{
-  class cl_view *v;
-
-  v= next;
-  while (v != this)
-    v= v->next;
-  return(v);
-}
-
-class cl_view *
-cl_view::prev_view(void)
-{
-  if (parent &&
-      parent->first() == this)
-    return(0);
-  else
-    return(prev());    
-}
-
-
-int
-cl_view::select(void)
-{
-  /*  class cl_view *v;
-
-  if (!(options & OF_SELECTABLE))
-    return(0);
-  if (state & SF_SELECTED)
-    return(1);
-  if (parent &&
-      !(parent->select()))
-    return(0);
-  if (parent)
-    {
-      v= parent->current_sub_view();
-      if (v &&
-	  v != this)
-	v->unselect();
-      parent->set_current(this);
-    }
-  change_state(SF_FOCUSED, 1);
-  change_state(SF_SELECTED, 1);
-  draw();
-  return(1);*/
-  if (options & OF_SELECTABLE)
-    if (parent)
-      parent->set_current(this);
-  return(1);
-}
-
-int
-cl_view::unselect(void)
-{
-  class cl_view *csv= current_sub_view();
-  if (csv &&
-      !(csv->unselect()))
-    return(0);
-  if (!terminal_view())
-    change_state(SF_FOCUSED, 0);
-  change_state(SF_SELECTED, 0);
-  draw();
-  return(1);
-}
-
-class cl_view *
-cl_view::current_sub_view(void)
-{
-  return(0);
-}
-
-int
-cl_view::terminal_view(void)
-{
-  return(1);
-}
-
-void
-cl_view::change_state(unsigned int what, int enable)
-{
-  if (enable)
-    state|= what;
-  else
-    state&= ~what;
-  if (parent)
-    {
-      switch (what)
-	{
-	case SF_FOCUSED:
-	  //reset_cursor();
-	  /*message(parent, EV_BROADCAST,
-	    (enable)?CM_RECEIVED_FOCUS:CM_RELEASED_FOCUS, this);*/
-	  break;
-	}
-    }
-  draw();
-}
-
-
-/* End of gui.src/view.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/gui.src/obsolete/viewcl.h sdcc-4.2.0+dfsg/sim/ucsim/gui.src/obsolete/viewcl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/gui.src/obsolete/viewcl.h	2001-04-02 13:08:48.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/gui.src/obsolete/viewcl.h	1970-01-01 00:00:00.000000000 +0000
@@ -1,118 +0,0 @@
-/*
- * Simulator of microcontrollers (viewcl.h)
- *
- * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
- * 
- * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
- *
- */
-
-/* This file is part of microcontroller simulator: ucsim.
-
-UCSIM is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2 of the License, or
-(at your option) any later version.
-
-UCSIM is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with UCSIM; see the file COPYING.  If not, write to the Free
-Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-02111-1307, USA. */
-/*@1@*/
-
-#ifndef VIEWCL_HEADER
-#define VIEWCL_HEADER
-
-#include 
-#include 
-
-#include "pobjcl.h"
-
-#include "palette.h"
-#include "eventcl.h"
-
-
-// Status flags
-#define SF_NOTHING	0x0000
-#define SF_SELECTED	0x0001
-#define SF_FOCUSED	0x0002
-#define SF_ACTIVE	0x0004
-
-// Option flags
-#define OF_NOTHING	0x0000
-#define OF_SELECTABLE	0x0001
-
-
-class cl_box: public cl_base
-{
-public:
-  int x, y;
-  int w, h;
-public:
-  cl_box(int ix, int iy, int iw, int ih);
-  void set(int ix, int iy, int iw, int ih);
-  void move_rel(int dx, int dy);
-  void grow(int dw, int dh);
-};
-
-
-class cl_app;
-class cl_group;
-
-class cl_view: public cl_base
-{
-public:
-  char *name;
-  WINDOW *window;
-  PANEL *panel;
-  class cl_group *parent;
-  class cl_view *next, *last;
-  class cl_app *app;
-  class cl_gin *input;
-  class cl_box *pos;
-  int *palette;
-  unsigned int state; // See SF_XXXX
-  unsigned int options; // See OF_XXXX
-public:
-  cl_view(class cl_box *ipos, char *iname, class cl_app *iapp);
-  cl_view(char *name, class cl_app *iapp);
-  ~cl_view(void);
-  virtual int init(void);
-  virtual class cl_gin *mk_input(void);
-  virtual int *mk_palette(void);
-  virtual int is_group(void) {return(0);}
-
-  virtual int ok(void);
-  virtual int draw(void);
-  virtual int update(void);
-  virtual int get_color(int color);
-  virtual int *get_palette(void);
-
-  virtual int get_event(struct t_event *event);
-  virtual int handle_event(struct t_event *event);
-  virtual int unhandled(struct t_event *event);
-  virtual int mk_event(struct t_event *event, FILE *f, int key);
-
-  virtual class cl_view *prev(void);
-  virtual class cl_view *prev_view(void);
-
-  virtual int select(void);
-  virtual int unselect(void);
-  virtual class cl_view *get_by_state(unsigned int what, int enabled)
-    {return(0);}
-  virtual int select_next() {return(0);}
-  virtual class cl_view *current_sub_view(void);
-  virtual void set_current(class cl_view *view) {}
-  virtual int terminal_view(void);
-  virtual void change_state(unsigned int what, int enable);
-};
-
-
-#endif
-
-/* End of gui.src/viewcl.h */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/gui.src/obsolete/win.cc sdcc-4.2.0+dfsg/sim/ucsim/gui.src/obsolete/win.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/gui.src/obsolete/win.cc	2001-04-02 13:08:48.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/gui.src/obsolete/win.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,111 +0,0 @@
-/*
- * Simulator of microcontrollers (win.cc)
- *
- * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
- * 
- * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
- *
- */
-
-/* This file is part of microcontroller simulator: ucsim.
-
-UCSIM is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2 of the License, or
-(at your option) any later version.
-
-UCSIM is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with UCSIM; see the file COPYING.  If not, write to the Free
-Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-02111-1307, USA. */
-/*@1@*/
-
-#include "ddconfig.h"
-
-#include 
-#include "i_string.h"
-
-#include "wincl.h"
-
-
-cl_win::cl_win(class cl_box *ipos, char *ititle, class cl_app *iapp):
-  cl_group(ipos, 0, iapp)
-{
-  title= strdup(ititle);
-  free(name);
-  if (!ititle ||
-      !(*ititle))
-    {
-      name= (char*)malloc(100);
-      sprintf(name, "win%p", this);
-    }
-  else
-    name= strdup(ititle);
-}
-
-cl_win::~cl_win(void)
-{
-  if (frame)
-    delete frame;
-  if (title)
-    free(title);
-}
-
-int
-cl_win::init(void)
-{
-  cl_group::init();
-  if ((frame= mk_frame(pos)))
-    insert(frame);
-  class cl_box *b= new cl_box(pos->x,pos->y, pos->w,pos->h);
-  b->move_rel(1,1);
-  b->grow(-2,-2);
-  if ((intern= mk_intern(b)))
-    insert(intern);
-  //draw();
-  delete b;
-  return(0);
-}
-
-int *
-cl_win::mk_palette(void)
-{
-  int *p= (int*)malloc(8*sizeof(int)), i;
-  for (i= 0; i < 8; i++)
-    p[i]= i+C_WIN;
-  return(p);
-}
-
-class cl_frame *
-cl_win::mk_frame(class cl_box *ipos)
-{
-  char n[100]= "";
-  
-  sprintf(n, "frameof_\"%s\"", name);
-  class cl_frame *f= new cl_frame(ipos, this, n, app);
-  f->init();
-  return(f);
-}
-
-class cl_view *
-cl_win::mk_intern(class cl_box *ipos)
-{
-  class cl_view *v= new cl_view(ipos, 0, app);
-  v->init();
-  v->options&= ~OF_SELECTABLE;
-  return(v);
-}
-
-char *
-cl_win::get_title(void)
-{
-  return(title);
-}
-
-
-/* End of gui.src/win.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/gui.src/obsolete/wincl.h sdcc-4.2.0+dfsg/sim/ucsim/gui.src/obsolete/wincl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/gui.src/obsolete/wincl.h	2001-04-02 13:08:48.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/gui.src/obsolete/wincl.h	1970-01-01 00:00:00.000000000 +0000
@@ -1,55 +0,0 @@
-/*
- * Simulator of microcontrollers (wincl.h)
- *
- * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
- * 
- * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
- *
- */
-
-/* This file is part of microcontroller simulator: ucsim.
-
-UCSIM is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2 of the License, or
-(at your option) any later version.
-
-UCSIM is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with UCSIM; see the file COPYING.  If not, write to the Free
-Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-02111-1307, USA. */
-/*@1@*/
-
-#ifndef WINCL_HEADER
-#define WINCL_HEADER
-
-#include "groupcl.h"
-#include "framecl.h"
-
-
-class cl_win: public cl_group
-{
-public:
-  class cl_view *frame;
-  class cl_view *intern;
-  char *title;
-public:
-  cl_win(class cl_box *ipos, char *ititle, class cl_app *iapp);
-  ~cl_win(void);
-  virtual int init(void);
-  virtual int *mk_palette(void);
-  virtual class cl_frame *mk_frame(class cl_box *ipos);
-  virtual class cl_view *mk_intern(class cl_box *ipos);
-
-  virtual char *get_title(void);
-};
-
-
-#endif
-
-/* End of gui.src/wincl.h */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/gui.src/serio.src/clean.mk sdcc-4.2.0+dfsg/sim/ucsim/gui.src/serio.src/clean.mk
--- sdcc-4.0.0+dfsg/sim/ucsim/gui.src/serio.src/clean.mk	2003-04-24 21:06:59.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/gui.src/serio.src/clean.mk	2020-03-27 20:18:53.000000000 +0000
@@ -5,7 +5,7 @@
 clean:
 	rm -f *core *[%~] *.[oa]
 	rm -f .[a-z]*~
-	rm -f serialview$(EXEEXT)
+	rm -f serialview$(EXEEXT) serialview.exe
 
 
 # Deleting all files created by configuring or building the program
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/gui.src/serio.src/config.h sdcc-4.2.0+dfsg/sim/ucsim/gui.src/serio.src/config.h
--- sdcc-4.0.0+dfsg/sim/ucsim/gui.src/serio.src/config.h	2019-03-11 07:48:17.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/gui.src/serio.src/config.h	2022-01-26 16:35:40.000000000 +0000
@@ -1,6 +1,6 @@
 /******************************************************************************
  * to emulate the serial input and output of an 8051 controller               *
- * config.h - general defintions                                              *
+ * config.h - general definitions                                              *
  ******************************************************************************/
 #ifndef CONFIG_HEADER
 #define CONFIG_HEADER
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/gui.src/serio.src/frontend.cc sdcc-4.2.0+dfsg/sim/ucsim/gui.src/serio.src/frontend.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/gui.src/serio.src/frontend.cc	2019-03-11 07:48:17.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/gui.src/serio.src/frontend.cc	2020-08-22 10:25:08.000000000 +0000
@@ -2,26 +2,30 @@
  * to emulate the serial input and output of an 8051 controller               *
  * frontend.cc - the ncurses frontend                                         *
  ******************************************************************************/
-#include 
-#include 
+
+#include 
+#include 
+//#include 
+//#include 
 #include 
-#include 
-#include 
-#include 
-#include 
+//#include 
+//#include 
+//#include 
+//#include 
 #include 
-#include 
+//#include 
+
 #include "frontend.hh"
 
-char *
+static const char *
 flt_name(enum filter_t f)
 {
   switch (f)
     {
-    case flt_none	: return (char*)"none";
-    case flt_hex	: return (char*)"hex";
+    case flt_none	: return "none";
+    case flt_hex	: return "hex";
     }
-  return (char*)"unknown";
+  return "unknown";
 }
 
 Viewer::Viewer()
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/gui.src/serio.src/frontend.hh sdcc-4.2.0+dfsg/sim/ucsim/gui.src/serio.src/frontend.hh
--- sdcc-4.0.0+dfsg/sim/ucsim/gui.src/serio.src/frontend.hh	2019-03-11 07:48:17.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/gui.src/serio.src/frontend.hh	2021-11-02 13:14:45.000000000 +0000
@@ -7,7 +7,6 @@
 
 #include 
 #include 
-#include 
 
 #include "config.h"
 
@@ -51,13 +50,13 @@
 private:
   WINDOW *inp, *outp;
   COORDS win_c, inp_c, outp_c;
-  COORDINATES topleft, bottomright, current;
+  COORDINATES topleft, bottomright;//, current;
   int middle_y, middle_x;
   enum filter_t flt_in, flt_out;
   unsigned int ocnt, icnt;
   int line_length;
   
-  uint8_t ohex_buf[16], ihex_buf[16];
+  unsigned char ohex_buf[16];//, ihex_buf[16];
   int ohex_ptr, ihex_ptr, ihex_high, ihex_val;
 };
 
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/gui.src/serio.src/main.cc sdcc-4.2.0+dfsg/sim/ucsim/gui.src/serio.src/main.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/gui.src/serio.src/main.cc	2019-07-02 08:44:01.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/gui.src/serio.src/main.cc	2021-11-02 13:14:45.000000000 +0000
@@ -2,14 +2,16 @@
  * to emulate the serial input and output of an 8051 controller               *
  * main.cc - the main stuff                                                   *
  ******************************************************************************/
-#include "ddconfig.h"
+//#include "ddconfig.h"
 
-#include 
+#include 
+//#include 
+#include 
 #include 
 #include 
-#include 
-#include 
-#include 
+//#include 
+//#include 
+//#include 
 #include 
 #include 
 #include 
@@ -434,6 +436,6 @@
   delete fobj;
   delete view;
   delete sig;
-  delete string;
+  delete[] string;
   return(0);
 }
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/gui.src/serio.src/Makefile.in sdcc-4.2.0+dfsg/sim/ucsim/gui.src/serio.src/Makefile.in
--- sdcc-4.0.0+dfsg/sim/ucsim/gui.src/serio.src/Makefile.in	2017-03-02 10:01:56.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/gui.src/serio.src/Makefile.in	2022-01-13 08:20:03.000000000 +0000
@@ -12,10 +12,11 @@
 top_srcdir	= @top_srcdir@
 
 DEFS            = $(subs -DHAVE_CONFIG_H,,@DEFS@)
+PICOPT		= @PICOPT@
 CPPFLAGS        = @CPPFLAGS@ -I. -I$(top_builddir)
 #		  -I$(top_builddir)/cmd.src -I$(top_builddir)/sim.src
-CFLAGS          = @CFLAGS@ @WALL_FLAG@
-CXXFLAGS        = @CXXFLAGS@ @WALL_FLAG@
+CFLAGS          = @WALL_FLAG@ @CFLAGS@
+CXXFLAGS        = @WALL_FLAG@ @CXXFLAGS@ $(PICOPT)
 
 LIBS		= @CURSES_LIBS@ @LIBS@
 
@@ -99,7 +100,7 @@
 # My rules
 # --------
 serialview$(EXEEXT): $(OBJECTS)
-	$(CXX) -o $@ $(LDFLAGS) $(OBJECTS) $(LIBS)
+	$(CXX) -o $@ $(CXXFLAGS) $(LDFLAGS) $(OBJECTS) $(LIBS)
 
 .cc.o:
 	$(CXX) $(CXXFLAGS)  $(CPPFLAGS) -c $< -o $@
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/gui.src/serio.src/posix_signal.cc sdcc-4.2.0+dfsg/sim/ucsim/gui.src/serio.src/posix_signal.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/gui.src/serio.src/posix_signal.cc	2019-03-11 07:48:17.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/gui.src/serio.src/posix_signal.cc	2022-01-26 16:35:40.000000000 +0000
@@ -5,7 +5,7 @@
  * Last edited on 01th Oct 19999                                              *
  ******************************************************************************/
 /*
- * A quick note, fscking linux, none of this would be neccessary if
+ * A quick note, fscking linux, none of this would be necessary if
  * linux contained support for sighold, sigrelse, sigignore and sigpause.
  *
  */
@@ -15,9 +15,9 @@
 #include    /* header for waitpid() and various macros */
 #include      /* header for signal functions */
 #include 
-#include 
+//#include 
 #include 
-#include 
+//#include 
 #include 
 
 #include "posix_signal.hh"
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/gui.src/serio.src/USAGE sdcc-4.2.0+dfsg/sim/ucsim/gui.src/serio.src/USAGE
--- sdcc-4.0.0+dfsg/sim/ucsim/gui.src/serio.src/USAGE	2000-02-07 08:24:57.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/gui.src/serio.src/USAGE	2022-01-27 21:35:29.000000000 +0000
@@ -1,7 +1,7 @@
 *note: tested on:
 Solaris 7 using gcc version 2.95.1 19990816 (release)
 with ncurses
-should work with curses although not guranteed
+should work with curses although not guaranteed
 
 Start serialview
 Start the s51 simulator with the following command line options:
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/hc08.src/(c).1 sdcc-4.2.0+dfsg/sim/ucsim/hc08.src/(c).1
--- sdcc-4.0.0+dfsg/sim/ucsim/hc08.src/(c).1	2003-10-15 05:14:36.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/hc08.src/(c).1	1970-01-01 00:00:00.000000000 +0000
@@ -1,25 +0,0 @@
-/*
- * Simulator of microcontrollers (@@F@@)
- *
- * Copyright (C) @@S@@,@@Y@@ Drotos Daniel, Talker Bt.
- * 
- * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
- *
- */
-
-/* This file is part of microcontroller simulator: ucsim.
-
-UCSIM is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2 of the License, or
-(at your option) any later version.
-
-UCSIM is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with UCSIM; see the file COPYING.  If not, write to the Free
-Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-02111-1307, USA. */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/hc08.src/clean.mk sdcc-4.2.0+dfsg/sim/ucsim/hc08.src/clean.mk
--- sdcc-4.0.0+dfsg/sim/ucsim/hc08.src/clean.mk	2003-10-15 05:14:36.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/hc08.src/clean.mk	1970-01-01 00:00:00.000000000 +0000
@@ -1,26 +0,0 @@
-# Deleting all files created by building the program
-# --------------------------------------------------
-clean:
-	rm -f *core *[%~] *.[oa]
-	rm -f .[a-z]*~
-	rm -f shc08$(EXEEXT)
-
-
-# Deleting all files created by configuring or building the program
-# -----------------------------------------------------------------
-distclean: clean
-	rm -f config.cache config.log config.status
-	rm -f Makefile *.dep
-
-
-# Like clean but some files may still exist
-# -----------------------------------------
-mostlyclean: clean
-
-
-# Deleting everything that can reconstructed by this Makefile. It deletes
-# everything deleted by distclean plus files created by bison, etc.
-# -----------------------------------------------------------------------
-realclean: distclean
-
-# End of hc08.src/clean.mk
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/hc08.src/conf.mk sdcc-4.2.0+dfsg/sim/ucsim/hc08.src/conf.mk
--- sdcc-4.0.0+dfsg/sim/ucsim/hc08.src/conf.mk	2016-07-29 14:28:30.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/hc08.src/conf.mk	1970-01-01 00:00:00.000000000 +0000
@@ -1,10 +0,0 @@
-#
-# Makefile targets to remake configuration
-#
-
-freshconf: Makefile
-
-Makefile: $(srcdir)/Makefile.in $(top_srcdir)/configure.ac
-	cd $(top_builddir) && $(SHELL) ./config.status
-
-# End of hc08.src/conf.mk
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/hc08.src/glob.cc sdcc-4.2.0+dfsg/sim/ucsim/hc08.src/glob.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/hc08.src/glob.cc	2016-05-23 08:34:18.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/hc08.src/glob.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,395 +0,0 @@
-
-/*
- * Simulator of microcontrollers (glob.cc)
- *
- * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
- * 
- * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
- *
- */
-
-/* This file is part of microcontroller simulator: ucsim.
-
-UCSIM is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2 of the License, or
-(at your option) any later version.
-
-UCSIM is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with UCSIM; see the file COPYING.  If not, write to the Free
-Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-02111-1307, USA. */
-/*@1@*/
-
-#include 
-
-#include "stypes.h"
-
-
-/*
-%d - direct addressing
-%x - extended addressing
-%p - pc relative addressing
-%b - unsigned byte immediate addressing
-%w - unsigned word immediate addressing
-%s - signed byte immediate
-%1 - unsigned byte index offset
-%2 - unsigned word index offset
-*/
-
-/*  uint  code, mask;  char  branch;  uchar length;  char  *mnemonic; */
-struct dis_entry disass_hc08[]= {
-  { 0x0000, 0x00ff, 'R', 3, "brset #0,%d,%p" },
-  { 0x0001, 0x00ff, 'R', 3, "brclr #0,%d,%p" },
-  { 0x0002, 0x00ff, 'R', 3, "brset #1,%d,%p" },
-  { 0x0003, 0x00ff, 'R', 3, "brclr #1,%d,%p" },
-  { 0x0004, 0x00ff, 'R', 3, "brset #2,%d,%p" },
-  { 0x0005, 0x00ff, 'R', 3, "brclr #2,%d,%p" },
-  { 0x0006, 0x00ff, 'R', 3, "brset #3,%d,%p" },
-  { 0x0007, 0x00ff, 'R', 3, "brclr #3,%d,%p" },
-  { 0x0008, 0x00ff, 'R', 3, "brset #4,%d,%p" },
-  { 0x0009, 0x00ff, 'R', 3, "brclr #4,%d,%p" },
-  { 0x000a, 0x00ff, 'R', 3, "brset #5,%d,%p" },
-  { 0x000b, 0x00ff, 'R', 3, "brclr #5,%d,%p" },
-  { 0x000c, 0x00ff, 'R', 3, "brset #6,%d,%p" },
-  { 0x000d, 0x00ff, 'R', 3, "brclr #6,%d,%p" },
-  { 0x000e, 0x00ff, 'R', 3, "brset #7,%d,%p" },
-  { 0x000f, 0x00ff, 'R', 3, "brclr #7,%d,%p" },
-
-  { 0x0010, 0x00ff, ' ', 2, "bset #0,%d" },
-  { 0x0011, 0x00ff, ' ', 2, "bclr #0,%d" },
-  { 0x0012, 0x00ff, ' ', 2, "bset #1,%d" },
-  { 0x0013, 0x00ff, ' ', 2, "bclr #1,%d" },
-  { 0x0014, 0x00ff, ' ', 2, "bset #2,%d" },
-  { 0x0015, 0x00ff, ' ', 2, "bclr #2,%d" },
-  { 0x0016, 0x00ff, ' ', 2, "bset #3,%d" },
-  { 0x0017, 0x00ff, ' ', 2, "bclr #3,%d" },
-  { 0x0018, 0x00ff, ' ', 2, "bset #4,%d" },
-  { 0x0019, 0x00ff, ' ', 2, "bclr #4,%d" },
-  { 0x001a, 0x00ff, ' ', 2, "bset #5,%d" },
-  { 0x001b, 0x00ff, ' ', 2, "bclr #5,%d" },
-  { 0x001c, 0x00ff, ' ', 2, "bset #6,%d" },
-  { 0x001d, 0x00ff, ' ', 2, "bclr #6,%d" },
-  { 0x001e, 0x00ff, ' ', 2, "bset #7,%d" },
-  { 0x001f, 0x00ff, ' ', 2, "bclr #7,%d" },
-
-  { 0x0020, 0x00ff, 'R', 2, "bra %p" },
-  { 0x0021, 0x00ff, 'R', 2, "brn %p" },
-  { 0x0022, 0x00ff, 'R', 2, "bhi %p" },
-  { 0x0023, 0x00ff, 'R', 2, "bls %p" },
-  { 0x0024, 0x00ff, 'R', 2, "bcc %p" },
-  { 0x0025, 0x00ff, 'R', 2, "bcs %p" },
-  { 0x0026, 0x00ff, 'R', 2, "bne %p" },
-  { 0x0027, 0x00ff, 'R', 2, "beq %p" },
-  { 0x0028, 0x00ff, 'R', 2, "bhcc %p" },
-  { 0x0029, 0x00ff, 'R', 2, "bhcs %p" },
-  { 0x002a, 0x00ff, 'R', 2, "bpl %p" },
-  { 0x002b, 0x00ff, 'R', 2, "bmi %p" },
-  { 0x002c, 0x00ff, 'R', 2, "bmc %p" },
-  { 0x002d, 0x00ff, 'R', 2, "bms %p" },
-  { 0x002e, 0x00ff, 'R', 2, "bil %p" },
-  { 0x002f, 0x00ff, 'R', 2, "bih %p" },
-
-  { 0x0030, 0x00ff, ' ', 2, "neg %d" },
-  { 0x0031, 0x00ff, 'R', 3, "cbeq %d,%p" },
-  { 0x0032, 0x00ff, ' ', 3, "ldhx %x" },  //HCS08 only
-  { 0x0033, 0x00ff, ' ', 2, "com %d" },
-  { 0x0034, 0x00ff, ' ', 2, "lsr %d" },
-  { 0x0035, 0x00ff, ' ', 2, "sthx %d" },
-  { 0x0036, 0x00ff, ' ', 2, "ror %d" },
-  { 0x0037, 0x00ff, ' ', 2, "asr %d" },
-  { 0x0038, 0x00ff, ' ', 2, "lsl %d" },
-  { 0x0039, 0x00ff, ' ', 2, "rol %d" },
-  { 0x003a, 0x00ff, ' ', 2, "dec %d" },
-  { 0x003b, 0x00ff, 'R', 3, "dbnz %d,%d" },
-  { 0x003c, 0x00ff, ' ', 2, "inc %d" },
-  { 0x003d, 0x00ff, ' ', 2, "tst %d" },
-  { 0x003e, 0x00ff, ' ', 3, "cphx %x" },  //HCS08 only
-  { 0x003f, 0x00ff, ' ', 2, "clr %d" },
-
-  { 0x0040, 0x00ff, ' ', 1, "nega" },
-  { 0x0041, 0x00ff, 'R', 3, "cbeqa %b,%p" },
-  { 0x0042, 0x00ff, ' ', 1, "mul" },
-  { 0x0043, 0x00ff, ' ', 1, "coma" },
-  { 0x0044, 0x00ff, ' ', 1, "lsra" },
-  { 0x0045, 0x00ff, ' ', 3, "ldhx %w" },
-  { 0x0046, 0x00ff, ' ', 1, "rora" },
-  { 0x0047, 0x00ff, ' ', 1, "asra" },
-  { 0x0048, 0x00ff, ' ', 1, "lsla" },
-  { 0x0049, 0x00ff, ' ', 1, "rola" },
-  { 0x004a, 0x00ff, ' ', 1, "deca" },
-  { 0x004b, 0x00ff, 'R', 2, "dbnza %p" },
-  { 0x004c, 0x00ff, ' ', 1, "inca" },
-  { 0x004d, 0x00ff, ' ', 1, "tsta" },
-  { 0x004e, 0x00ff, ' ', 3, "mov %d,%d" },
-  { 0x004f, 0x00ff, ' ', 1, "clra" },
-
-  { 0x0050, 0x00ff, ' ', 1, "negx" },
-  { 0x0051, 0x00ff, 'R', 3, "cbeqx %b,%p" },
-  { 0x0052, 0x00ff, ' ', 1, "div" },
-  { 0x0053, 0x00ff, ' ', 1, "comx" },
-  { 0x0054, 0x00ff, ' ', 1, "lsrx" },
-  { 0x0055, 0x00ff, ' ', 2, "ldhx %d" },
-  { 0x0056, 0x00ff, ' ', 1, "rorx" },
-  { 0x0057, 0x00ff, ' ', 1, "asrx" },
-  { 0x0058, 0x00ff, ' ', 1, "lslx" },
-  { 0x0059, 0x00ff, ' ', 1, "rolx" },
-  { 0x005a, 0x00ff, ' ', 1, "decx" },
-  { 0x005b, 0x00ff, 'R', 2, "dbnzx %p" },
-  { 0x005c, 0x00ff, ' ', 1, "incx" },
-  { 0x005d, 0x00ff, ' ', 1, "tstx" },
-  { 0x005e, 0x00ff, ' ', 3, "mov %d,x+" },
-  { 0x005f, 0x00ff, ' ', 1, "clrx" },
-
-  { 0x0060, 0x00ff, ' ', 2, "neg %1,x" },
-  { 0x0061, 0x00ff, 'R', 3, "cbeq %1,x+,%p" },
-  { 0x0062, 0x00ff, ' ', 1, "nsa" },
-  { 0x0063, 0x00ff, ' ', 2, "com %1,x" },
-  { 0x0064, 0x00ff, ' ', 2, "lsr %1,x" },
-  { 0x0065, 0x00ff, ' ', 3, "cphx %w" },
-  { 0x0066, 0x00ff, ' ', 2, "ror %1,x" },
-  { 0x0067, 0x00ff, ' ', 2, "asr %1,x" },
-  { 0x0068, 0x00ff, ' ', 2, "lsl %1,x" },
-  { 0x0069, 0x00ff, ' ', 2, "rol %1,x" },
-  { 0x006a, 0x00ff, ' ', 2, "dec %1,x" },
-  { 0x006b, 0x00ff, 'R', 2, "dbnz %1,x,%p" },
-  { 0x006c, 0x00ff, ' ', 2, "inc %1,x" },
-  { 0x006d, 0x00ff, ' ', 2, "tst %1,x" },
-  { 0x006e, 0x00ff, ' ', 3, "mov %b,%d" },
-  { 0x006f, 0x00ff, ' ', 2, "clr %1,x" },
-
-/*
-  { 0x0070, 0x00ff, ' ', 2, "neg %b,sp" },
-  { 0x0071, 0x00ff, 'R', 3, "cbeq %b,sp,%d" },
-  { 0x0073, 0x00ff, ' ', 2, "com %b,sp" },
-  { 0x0074, 0x00ff, ' ', 2, "lsr %b,sp" },
-  { 0x0076, 0x00ff, ' ', 2, "ror %b,sp" },
-  { 0x0077, 0x00ff, ' ', 2, "asr %b,sp" },
-  { 0x0078, 0x00ff, ' ', 2, "lsl %b,sp" },
-  { 0x0079, 0x00ff, ' ', 2, "rol %b,sp" },
-  { 0x007a, 0x00ff, ' ', 2, "dec %b,sp" },
-  { 0x007b, 0x00ff, 'R', 2, "dbnz %b,sp,%d" },
-  { 0x007c, 0x00ff, ' ', 2, "inc %b,sp" },
-  { 0x007d, 0x00ff, ' ', 2, "tst %b,sp" },
-  { 0x007f, 0x00ff, ' ', 2, "clr %b,sp" },
-*/
-
-  { 0x0070, 0x00ff, ' ', 1, "neg ,x" },
-  { 0x0071, 0x00ff, 'R', 2, "cbeq ,x+,%p" },
-  { 0x0072, 0x00ff, ' ', 1, "daa" },
-  { 0x0073, 0x00ff, ' ', 1, "com ,x" },
-  { 0x0074, 0x00ff, ' ', 1, "lsr ,x" },
-  { 0x0075, 0x00ff, ' ', 2, "cphx %d" },
-  { 0x0076, 0x00ff, ' ', 1, "ror ,x" },
-  { 0x0077, 0x00ff, ' ', 1, "asr ,x" },
-  { 0x0078, 0x00ff, ' ', 1, "lsl ,x" },
-  { 0x0079, 0x00ff, ' ', 1, "rol ,x" },
-  { 0x007a, 0x00ff, ' ', 1, "dec ,x" },
-  { 0x007b, 0x00ff, 'R', 2, "dbnz ,x,%p" },
-  { 0x007c, 0x00ff, ' ', 1, "inc ,x" },
-  { 0x007d, 0x00ff, ' ', 1, "tst ,x" },
-  { 0x007e, 0x00ff, ' ', 2, "mov ,x+,%d" },
-  { 0x007f, 0x00ff, ' ', 1, "clr ,x" },
-
-  { 0x0080, 0x00ff, ' ', 1, "rti" },
-  { 0x0081, 0x00ff, ' ', 1, "rts" },
-  { 0x0082, 0x00ff, ' ', 1, "bgnd" },  //HCS08 only
-  { 0x0083, 0x00ff, ' ', 1, "swi", true },
-  { 0x0084, 0x00ff, ' ', 1, "tap" },
-  { 0x0085, 0x00ff, ' ', 1, "tpa" },
-  { 0x0086, 0x00ff, ' ', 1, "pula" },
-  { 0x0087, 0x00ff, ' ', 1, "psha" },
-  { 0x0088, 0x00ff, ' ', 1, "pulx" },
-  { 0x0089, 0x00ff, ' ', 1, "pshx" },
-  { 0x008a, 0x00ff, ' ', 1, "pulh" },
-  { 0x008b, 0x00ff, ' ', 1, "pshh" },
-  { 0x008c, 0x00ff, ' ', 1, "clrh" },
-  { 0x008e, 0x00ff, ' ', 1, "stop" },
-  { 0x008f, 0x00ff, ' ', 1, "wait" },
-
-  { 0x0090, 0x00ff, 'R', 2, "bge %p" },
-  { 0x0091, 0x00ff, 'R', 2, "blt %p" },
-  { 0x0092, 0x00ff, 'R', 2, "bgt %p" },
-  { 0x0093, 0x00ff, 'R', 2, "ble %p" },
-  { 0x0094, 0x00ff, ' ', 1, "txs" },
-  { 0x0095, 0x00ff, ' ', 1, "tsx" },
-  { 0x0096, 0x00ff, ' ', 3, "sthx %x" },  //HCS08 only
-  { 0x0097, 0x00ff, ' ', 1, "tax" },
-  { 0x0098, 0x00ff, ' ', 1, "clc" },
-  { 0x0099, 0x00ff, ' ', 1, "sec" },
-  { 0x009a, 0x00ff, ' ', 1, "cli" },
-  { 0x009b, 0x00ff, ' ', 1, "sei" },
-  { 0x009c, 0x00ff, ' ', 1, "rsp" },
-  { 0x009d, 0x00ff, ' ', 1, "nop" },
-  { 0x009f, 0x00ff, ' ', 1, "txa" },
-
-  { 0x00a0, 0x00ff, ' ', 2, "sub %b" },
-  { 0x00a1, 0x00ff, ' ', 2, "cmp %b" },
-  { 0x00a2, 0x00ff, ' ', 2, "sbc %b" },
-  { 0x00a3, 0x00ff, ' ', 2, "cpx %b" },
-  { 0x00a4, 0x00ff, ' ', 2, "and %b" },
-  { 0x00a5, 0x00ff, ' ', 2, "bit %b" },
-  { 0x00a6, 0x00ff, ' ', 2, "lda %b" },
-  { 0x00a7, 0x00ff, ' ', 2, "ais %s" },
-  { 0x00a8, 0x00ff, ' ', 2, "eor %b" },
-  { 0x00a9, 0x00ff, ' ', 2, "adc %b" },
-  { 0x00aa, 0x00ff, ' ', 2, "ora %b" },
-  { 0x00ab, 0x00ff, ' ', 2, "add %b" },
-  { 0x00ad, 0x00ff, 'R', 2, "bsr %d", true },
-  { 0x00ae, 0x00ff, ' ', 2, "ldx %b" },
-  { 0x00af, 0x00ff, ' ', 2, "aix %s" },
-
-  { 0x00b0, 0x00ff, ' ', 2, "sub %d" },
-  { 0x00b1, 0x00ff, ' ', 2, "cmp %d" },
-  { 0x00b2, 0x00ff, ' ', 2, "sbc %d" },
-  { 0x00b3, 0x00ff, ' ', 2, "cpx %d" },
-  { 0x00b4, 0x00ff, ' ', 2, "and %d" },
-  { 0x00b5, 0x00ff, ' ', 2, "bit %d" },
-  { 0x00b6, 0x00ff, ' ', 2, "lda %d" },
-  { 0x00b7, 0x00ff, ' ', 2, "sta %d" },
-  { 0x00b8, 0x00ff, ' ', 2, "eor %d" },
-  { 0x00b9, 0x00ff, ' ', 2, "adc %d" },
-  { 0x00ba, 0x00ff, ' ', 2, "ora %d" },
-  { 0x00bb, 0x00ff, ' ', 2, "add %d" },
-  { 0x00bc, 0x00ff, 'A', 2, "jmp %d" },
-  { 0x00bd, 0x00ff, 'A', 2, "jsr %d", true },
-  { 0x00be, 0x00ff, ' ', 2, "ldx %d" },
-  { 0x00bf, 0x00ff, ' ', 2, "stx %d" },
-
-  { 0x00c0, 0x00ff, ' ', 3, "sub %x" },
-  { 0x00c1, 0x00ff, ' ', 3, "cmp %x" },
-  { 0x00c2, 0x00ff, ' ', 3, "sbc %x" },
-  { 0x00c3, 0x00ff, ' ', 3, "cpx %x" },
-  { 0x00c4, 0x00ff, ' ', 3, "and %x" },
-  { 0x00c5, 0x00ff, ' ', 3, "bit %x" },
-  { 0x00c6, 0x00ff, ' ', 3, "lda %x" },
-  { 0x00c7, 0x00ff, ' ', 3, "sta %x" },
-  { 0x00c8, 0x00ff, ' ', 3, "eor %x" },
-  { 0x00c9, 0x00ff, ' ', 3, "adc %x" },
-  { 0x00ca, 0x00ff, ' ', 3, "ora %x" },
-  { 0x00cb, 0x00ff, ' ', 3, "add %x" },
-  { 0x00cc, 0x00ff, 'A', 3, "jmp %x" },
-  { 0x00cd, 0x00ff, 'A', 3, "jsr %x", true },
-  { 0x00ce, 0x00ff, ' ', 3, "ldx %x" },
-  { 0x00cf, 0x00ff, ' ', 3, "stx %x" },
-
-  { 0x00d0, 0x00ff, ' ', 3, "sub %2,x" },
-  { 0x00d1, 0x00ff, ' ', 3, "cmp %2,x" },
-  { 0x00d2, 0x00ff, ' ', 3, "sbc %2,x" },
-  { 0x00d3, 0x00ff, ' ', 3, "cpx %2,x" },
-  { 0x00d4, 0x00ff, ' ', 3, "and %2,x" },
-  { 0x00d5, 0x00ff, ' ', 3, "bit %2,x" },
-  { 0x00d6, 0x00ff, ' ', 3, "lda %2,x" },
-  { 0x00d7, 0x00ff, ' ', 3, "sta %2,x" },
-  { 0x00d8, 0x00ff, ' ', 3, "eor %2,x" },
-  { 0x00d9, 0x00ff, ' ', 3, "adc %2,x" },
-  { 0x00da, 0x00ff, ' ', 3, "ora %2,x" },
-  { 0x00db, 0x00ff, ' ', 3, "add %2,x" },
-  { 0x00dc, 0x00ff, ' ', 3, "jmp %2,x" },
-  { 0x00dd, 0x00ff, ' ', 3, "jsr %2,x", true },
-  { 0x00de, 0x00ff, ' ', 3, "ldx %2,x" },
-  { 0x00df, 0x00ff, ' ', 3, "stx %2,x" },
-
-  { 0x00e0, 0x00ff, ' ', 2, "sub %1,x" },
-  { 0x00e1, 0x00ff, ' ', 2, "cmp %1,x" },
-  { 0x00e2, 0x00ff, ' ', 2, "sbc %1,x" },
-  { 0x00e3, 0x00ff, ' ', 2, "cpx %1,x" },
-  { 0x00e4, 0x00ff, ' ', 2, "and %1,x" },
-  { 0x00e5, 0x00ff, ' ', 2, "bit %1,x" },
-  { 0x00e6, 0x00ff, ' ', 2, "lda %1,x" },
-  { 0x00e7, 0x00ff, ' ', 2, "sta %1,x" },
-  { 0x00e8, 0x00ff, ' ', 2, "eor %1,x" },
-  { 0x00e9, 0x00ff, ' ', 2, "adc %1,x" },
-  { 0x00ea, 0x00ff, ' ', 2, "ora %1,x" },
-  { 0x00eb, 0x00ff, ' ', 2, "add %1,x" },
-  { 0x00ec, 0x00ff, ' ', 2, "jmp %1,x" },
-  { 0x00ed, 0x00ff, ' ', 2, "jsr %1,x", true },
-  { 0x00ee, 0x00ff, ' ', 2, "ldx %1,x" },
-  { 0x00ef, 0x00ff, ' ', 2, "stx %1,x" },
-
-  { 0x00f0, 0x00ff, ' ', 1, "sub ,x" },
-  { 0x00f1, 0x00ff, ' ', 1, "cmp ,x" },
-  { 0x00f2, 0x00ff, ' ', 1, "sbc ,x" },
-  { 0x00f3, 0x00ff, ' ', 1, "cpx ,x" },
-  { 0x00f4, 0x00ff, ' ', 1, "and ,x" },
-  { 0x00f5, 0x00ff, ' ', 1, "bit ,x" },
-  { 0x00f6, 0x00ff, ' ', 1, "lda ,x" },
-  { 0x00f7, 0x00ff, ' ', 1, "sta ,x" },
-  { 0x00f8, 0x00ff, ' ', 1, "eor ,x" },
-  { 0x00f9, 0x00ff, ' ', 1, "adc ,x" },
-  { 0x00fa, 0x00ff, ' ', 1, "ora ,x" },
-  { 0x00fb, 0x00ff, ' ', 1, "add ,x" },
-  { 0x00fc, 0x00ff, ' ', 1, "jmp ,x" },
-  { 0x00fd, 0x00ff, ' ', 1, "jsr ,x", true },
-  { 0x00fe, 0x00ff, ' ', 1, "ldx ,x" },
-  { 0x00ff, 0x00ff, ' ', 1, "stx ,x" },
-
-  { 0, 0, 0, 0, NULL }
-};
-
-
-struct dis_entry disass_hc08_9e[]= {
-  { 0x0060, 0x00ff, ' ', 2, "neg %1,sp" },
-  { 0x0061, 0x00ff, 'R', 3, "cbeq %1,sp,%p" },
-  { 0x0063, 0x00ff, ' ', 2, "com %1,sp" },
-  { 0x0064, 0x00ff, ' ', 2, "lsr %1,sp" },
-  { 0x0066, 0x00ff, ' ', 2, "ror %1,sp" },
-  { 0x0067, 0x00ff, ' ', 2, "asr %1,sp" },
-  { 0x0068, 0x00ff, ' ', 2, "lsl %1,sp" },
-  { 0x0069, 0x00ff, ' ', 2, "rol %1,sp" },
-  { 0x006a, 0x00ff, ' ', 2, "dec %1,sp" },
-  { 0x006b, 0x00ff, 'R', 2, "dbnz %1,sp,%p" },
-  { 0x006c, 0x00ff, ' ', 2, "inc %1,sp" },
-  { 0x006d, 0x00ff, ' ', 2, "tst %1,sp" },
-  { 0x006f, 0x00ff, ' ', 2, "clr %1,sp" },
-
-  { 0x00ae, 0x00ff, ' ', 1, "ldhx ,x" },  //HCS08 only
-
-  { 0x00be, 0x00ff, ' ', 3, "ldhx %2,x" },  //HCS08 only
-
-  { 0x00ce, 0x00ff, ' ', 2, "ldhx %1,x" },  //HCS08 only
-
-  { 0x00d0, 0x00ff, ' ', 3, "sub %2,sp" },
-  { 0x00d1, 0x00ff, ' ', 3, "cmp %2,sp" },
-  { 0x00d2, 0x00ff, ' ', 3, "sbc %2,sp" },
-  { 0x00d3, 0x00ff, ' ', 3, "cpx %2,sp" },
-  { 0x00d4, 0x00ff, ' ', 3, "and %2,sp" },
-  { 0x00d5, 0x00ff, ' ', 3, "bit %2,sp" },
-  { 0x00d6, 0x00ff, ' ', 3, "lda %2,sp" },
-  { 0x00d7, 0x00ff, ' ', 3, "sta %2,sp" },
-  { 0x00d8, 0x00ff, ' ', 3, "eor %2,sp" },
-  { 0x00d9, 0x00ff, ' ', 3, "adc %2,sp" },
-  { 0x00da, 0x00ff, ' ', 3, "ora %2,sp" },
-  { 0x00db, 0x00ff, ' ', 3, "add %2,sp" },
-  { 0x00de, 0x00ff, ' ', 3, "ldx %2,sp" },
-  { 0x00df, 0x00ff, ' ', 3, "stx %2,sp" },
-
-  { 0x00e0, 0x00ff, ' ', 2, "sub %1,sp" },
-  { 0x00e1, 0x00ff, ' ', 2, "cmp %1,sp" },
-  { 0x00e2, 0x00ff, ' ', 2, "sbc %1,sp" },
-  { 0x00e3, 0x00ff, ' ', 2, "cpx %1,sp" },
-  { 0x00e4, 0x00ff, ' ', 2, "and %1,sp" },
-  { 0x00e5, 0x00ff, ' ', 2, "bit %1,sp" },
-  { 0x00e6, 0x00ff, ' ', 2, "lda %1,sp" },
-  { 0x00e7, 0x00ff, ' ', 2, "sta %1,sp" },
-  { 0x00e8, 0x00ff, ' ', 2, "eor %1,sp" },
-  { 0x00e9, 0x00ff, ' ', 2, "adc %1,sp" },
-  { 0x00ea, 0x00ff, ' ', 2, "ora %1,sp" },
-  { 0x00eb, 0x00ff, ' ', 2, "add %1,sp" },
-  { 0x00ee, 0x00ff, ' ', 2, "ldx %1,sp" },
-  { 0x00ef, 0x00ff, ' ', 2, "stx %1,sp" },
-
-  { 0x00f3, 0x00ff, ' ', 2, "cphx %1,sp" },  //HCS08 only
-  { 0x00fe, 0x00ff, ' ', 2, "ldhx %1,sp" },  //HCS08 only
-  { 0x00ff, 0x00ff, ' ', 2, "sthx %1,sp" },  //HCS08 only
-
-  { 0, 0, 0, 0, NULL }
-};
-
-
-/* glob.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/hc08.src/glob.h sdcc-4.2.0+dfsg/sim/ucsim/hc08.src/glob.h
--- sdcc-4.0.0+dfsg/sim/ucsim/hc08.src/glob.h	2003-10-15 05:14:36.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/hc08.src/glob.h	1970-01-01 00:00:00.000000000 +0000
@@ -1,41 +0,0 @@
-/*
- * Simulator of microcontrollers (glob.h)
- *
- * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
- * 
- * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
- *
- */
-
-/* This file is part of microcontroller simulator: ucsim.
-
-UCSIM is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2 of the License, or
-(at your option) any later version.
-
-UCSIM is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with UCSIM; see the file COPYING.  If not, write to the Free
-Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-02111-1307, USA. */
-/*@1@*/
-
-#ifndef GLOB_HEADER
-#define GLOB_HEADER
-
-#include "stypes.h"
-
-
-extern struct dis_entry disass_hc08[];
-
-extern struct dis_entry disass_hc08_9e[];
-
-
-#endif
-
-/* End of hc08.src/glob.h */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/hc08.src/hc08.cc sdcc-4.2.0+dfsg/sim/ucsim/hc08.src/hc08.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/hc08.src/hc08.cc	2019-05-06 09:55:43.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/hc08.src/hc08.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,695 +0,0 @@
-/*
- * Simulator of microcontrollers (hc08.cc)
- *
- * some hc08 code base from Karl Bongers karl@turbobit.com
- *
- * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
- *
- * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
- *
- */
-
-/* This file is part of microcontroller simulator: ucsim.
-
-UCSIM is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2 of the License, or
-(at your option) any later version.
-
-UCSIM is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with UCSIM; see the file COPYING.  If not, write to the Free
-Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-02111-1307, USA. */
-/*@1@*/
-
-#include "ddconfig.h"
-
-#include  /* for va_list */
-#include 
-#include 
-#include 
-#include "i_string.h"
-
-// prj
-#include "pobjcl.h"
-
-// sim
-#include "simcl.h"
-
-// local
-#include "hc08cl.h"
-#include "glob.h"
-#include "regshc08.h"
-#include "hc08mac.h"
-
-#define uint32 t_addr
-#define uint8 unsigned char
-#define int8 char
-
-//const bool TRUE = 1;
-//const bool FALSE = 0;
-
-/*******************************************************************/
-
-
-/*
- * Base type of HC08 controllers
- */
-
-cl_hc08::cl_hc08(struct cpu_entry *Itype, class cl_sim *asim):
-  cl_uc(asim)
-{
-  type= Itype;
-}
-
-int
-cl_hc08::init(void)
-{
-  cl_uc::init(); /* Memories now exist */
-
-  xtal = 8000000;
-
-  //rom= address_space(MEM_ROM_ID);
-//  ram= mem(MEM_XRAM);
-  //ram= rom;
-
-  // zero out ram(this is assumed in regression tests)
-  for (int i=0x80; i<0x8000; i++) {
-    ram->set((t_addr) i, 0);
-  }
-
-  return(0);
-}
-
-
-void
-cl_hc08::reset(void)
-{
-  cl_uc::reset();
-
-  regs.SP = 0xff;
-  regs.A = 0;
-  regs.X = 0;
-  regs.H = 0;
-  regs.P = 0x60;
-  regs.VECTOR = 1;
-
-}
-
-
-char *
-cl_hc08::id_string(void)
-{
-  return((char*)"unspecified HC08");
-}
-
-
-/*
- * Making elements of the controller
- */
-/*
-t_addr
-cl_hc08::get_mem_size(enum mem_class type)
-{
-  switch(type)
-    {
-    case MEM_ROM: return(0x10000);
-    case MEM_XRAM: return(0x10000);
-    default: return(0);
-    }
- return(cl_uc::get_mem_size(type));
-}
-*/
-void
-cl_hc08::mk_hw_elements(void)
-{
-  //class cl_base *o;
-  cl_uc::mk_hw_elements();
-}
-
-void
-cl_hc08::make_memories(void)
-{
-  class cl_address_space *as;
-
-  rom= ram= as= new cl_address_space("rom", 0, 0x10000, 8);
-  as->init();
-  address_spaces->add(as);
-
-  class cl_address_decoder *ad;
-  class cl_memory_chip *chip;
-
-  chip= new cl_memory_chip("rom_chip", 0x10000, 8);
-  chip->init();
-  memchips->add(chip);
-  ad= new cl_address_decoder(as= address_space("rom"), chip, 0, 0xffff, 0);
-  ad->init();
-  as->decoders->add(ad);
-  ad->activate(0);
-
-
-  regs8= new cl_address_space("regs8", 0, 4, 8);
-  regs8->init();
-  regs8->get_cell(0)->decode((t_mem*)®s.A);
-  regs8->get_cell(1)->decode((t_mem*)®s.P);
-  regs8->get_cell(2)->decode((t_mem*)®s.H);
-  regs8->get_cell(3)->decode((t_mem*)®s.X);
-
-  regs16= new cl_address_space("regs16", 0, 1, 16);
-  regs16->init();
-
-  regs16->get_cell(0)->decode((t_mem*)®s.SP);
-
-  address_spaces->add(regs8);
-  address_spaces->add(regs16);
-
-  class cl_var *v;
-  vars->add(v= new cl_var(cchars("A"), regs8, 0, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("P"), regs8, 1, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("H"), regs8, 2, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("X"), regs8, 3, ""));
-  v->init();
-
-  vars->add(v= new cl_var(cchars("SP"), regs16, 0, ""));
-  v->init();
-}
-
-
-/*
- * Help command interpreter
- */
-
-struct dis_entry *
-cl_hc08::dis_tbl(void)
-{
-  return(disass_hc08);
-}
-
-/*struct name_entry *
-cl_hc08::sfr_tbl(void)
-{
-  return(0);
-}*/
-
-/*struct name_entry *
-cl_hc08::bit_tbl(void)
-{
-  //FIXME
-  return(0);
-}*/
-
-int
-cl_hc08::inst_length(t_addr addr)
-{
-  int len = 0;
-  /*char *s;
-
-    s =*/ get_disasm_info(addr, &len, NULL, NULL, NULL);
-
-  return len;
-}
-
-int
-cl_hc08::inst_branch(t_addr addr)
-{
-  int b;
-  /*char *s;
-
-    s =*/ get_disasm_info(addr, NULL, &b, NULL, NULL);
-
-  return b;
-}
-
-
-bool
-cl_hc08::is_call(t_addr addr)
-{
-  struct dis_entry *e;
-
-  get_disasm_info(addr, NULL, NULL, NULL, &e);
-  
-  return e?(e->is_call):false;
-}
-
-int
-cl_hc08::longest_inst(void)
-{
-  return 4;
-}
-
-
-const char *
-cl_hc08::get_disasm_info(t_addr addr,
-			 int *ret_len,
-			 int *ret_branch,
-			 int *immed_offset,
-			 struct dis_entry **dentry)
-{
-  const char *b = NULL;
-  uint code;
-  int len = 0;
-  int immed_n = 0;
-  int i;
-  int start_addr = addr;
-  struct dis_entry *dis_e;
-
-  code= rom->get(addr++);
-  dis_e = NULL;
-
-  switch(code) {
-    case 0x9e:  /* ESC code to sp relative op-codes */
-      code= rom->get(addr++);
-      i= 0;
-      while ((code & disass_hc08_9e[i].mask) != disass_hc08_9e[i].code &&
-        disass_hc08_9e[i].mnemonic)
-        i++;
-      dis_e = &disass_hc08_9e[i];
-      b= disass_hc08_9e[i].mnemonic;
-      if (b != NULL)
-        len += (disass_hc08_9e[i].length + 1);
-    break;
-
-    default:
-      i= 0;
-      while ((code & disass_hc08[i].mask) != disass_hc08[i].code &&
-             disass_hc08[i].mnemonic)
-        i++;
-      dis_e = &disass_hc08[i];
-      b= disass_hc08[i].mnemonic;
-      if (b != NULL)
-        len += (disass_hc08[i].length);
-    break;
-  }
-
-  if (ret_branch) {
-    *ret_branch = dis_e->branch;
-  }
-
-  if (immed_offset) {
-    if (immed_n > 0)
-         *immed_offset = immed_n;
-    else *immed_offset = (addr - start_addr);
-  }
-
-  if (len == 0)
-    len = 1;
-
-  if (ret_len)
-    *ret_len = len;
-
-  if (dentry)
-    *dentry= dis_e;
-  
-  return b;
-}
-
-char *
-cl_hc08::disass(t_addr addr, const char *sep)
-{
-  char work[256], temp[20];
-  char *buf, *p, *t, *s;
-  const char *b;
-  int len = 0;
-  int immed_offset = 0;
-
-  p= work;
-
-  b = get_disasm_info(addr, &len, NULL, &immed_offset, NULL);
-
-  if (b == NULL) {
-    buf= (char*)malloc(30);
-    strcpy(buf, "UNKNOWN/INVALID");
-    return(buf);
-  }
-
-  while (*b)
-    {
-      if (*b == '%')
-	{
-	  b++;
-	  switch (*(b++))
-	    {
-	    case 's': // s    signed byte immediate
-	      sprintf(temp, "#%d", (char)rom->get(addr+immed_offset));
-	      ++immed_offset;
-	      break;
-	    case 'w': // w    word immediate operand
-	      sprintf(temp, "#0x%04x",
-	         (uint)((rom->get(addr+immed_offset)<<8) |
-	                (rom->get(addr+immed_offset+1))) );
-	      ++immed_offset;
-	      ++immed_offset;
-	      break;
-	    case 'b': // b    byte immediate operand
-	      sprintf(temp, "#0x%02x", (uint)rom->get(addr+immed_offset));
-	      ++immed_offset;
-	      break;
-	    case 'x': // x    extended addressing
-	      sprintf(temp, "0x%04x",
-	         (uint)((rom->get(addr+immed_offset)<<8) |
-	                (rom->get(addr+immed_offset+1))) );
-	      ++immed_offset;
-	      ++immed_offset;
-	      break;
-	    case 'd': // d    direct addressing
-	      sprintf(temp, "*0x%02x", (uint)rom->get(addr+immed_offset));
-	      ++immed_offset;
-	      break;
-	    case '2': // 2    word index offset
-	      {
-		int i= (uint)((rom->get(addr+immed_offset)<<8) |
-			      (rom->get(addr+immed_offset+1)));
-		sprintf(temp, "0x%04x", i & 0xffff);
-		++immed_offset;
-		++immed_offset;
-		break;
-	      }		
-	    case '1': // b    byte index offset
-              sprintf(temp, "0x%02x", (uint)rom->get(addr+immed_offset));
-	      ++immed_offset;
-	      break;
-	    case 'p': // b    byte index offset
-	      {
-		int i= addr+immed_offset+1
-		  +(char)rom->get(addr+immed_offset);
-		sprintf(temp, "0x%04x", i & 0xffff);
-		++immed_offset;
-		break;
-	      }
-	    default:
-	      strcpy(temp, "?");
-	      break;
-	    }
-	  t= temp;
-	  while (*t)
-	    *(p++)= *(t++);
-	}
-      else
-	*(p++)= *(b++);
-    }
-  *p= '\0';
-
-  p= strchr(work, ' ');
-  if (!p)
-    {
-      buf= strdup(work);
-      return(buf);
-    }
-  if (sep == NULL)
-    buf= (char *)malloc(6+strlen(p)+1);
-  else
-    buf= (char *)malloc((p-work)+strlen(sep)+strlen(p)+1);
-  for (p= work, s= buf; *p != ' '; p++, s++)
-    *s= *p;
-  p++;
-  *s= '\0';
-  if (sep == NULL)
-    {
-      while (strlen(buf) < 6)
-	strcat(buf, " ");
-    }
-  else
-    strcat(buf, sep);
-  strcat(buf, p);
-
-  return(buf);
-}
-
-
-void
-cl_hc08::print_regs(class cl_console_base *con)
-{
-  con->dd_printf("V--HINZC  Flags= 0x%02x %3d %c  ",
-		 regs.P, regs.P, isprint(regs.P)?regs.P:'.');
-  con->dd_printf("A= 0x%02x %3d %c\n",
-		 regs.A, regs.A, isprint(regs.A)?regs.A:'.');
-  con->dd_printf("%c--%c%c%c%c%c  ",
-		 (regs.P&BIT_V)?'1':'0',
-		 (regs.P&BIT_H)?'1':'0',
-		 (regs.P&BIT_I)?'1':'0',
-		 (regs.P&BIT_N)?'1':'0',
-		 (regs.P&BIT_Z)?'1':'0',
-		 (regs.P&BIT_C)?'1':'0');
-  con->dd_printf("    H= 0x%02x %3d %c  ",
-		 regs.H, regs.H, isprint(regs.H)?regs.H:'.');
-  con->dd_printf("X= 0x%02x %3d %c\n",
-		 regs.X, regs.X, isprint(regs.X)?regs.X:'.');
-  con->dd_printf("SP= 0x%04x [SP+1]= %02x %3d %c\n",
-                 regs.SP, ram->get(regs.SP+1), ram->get(regs.SP+1),
-                 isprint(ram->get(regs.SP+1))?ram->get(regs.SP+1):'.');
-
-  print_disass(PC, con);
-}
-
-/*
- * Execution
- */
-
-int
-cl_hc08::exec_inst(void)
-{
-  t_mem code;
-
-  if (regs.VECTOR) {
-    PC = get2(0xfffe);
-    regs.VECTOR = 0;
-    return(resGO);
-  }
-
-  instPC= PC;
-
-  if (fetch(&code))
-    return(resBREAKPOINT);
-  tick(1);
-  switch ((code >> 4) & 0xf) {
-  case 0x0: return(inst_bittestsetclear(code, /*FALSE*/0));
-  case 0x1: return(inst_bitsetclear(code, /*FALSE*/0));
-    case 0x2: return(inst_condbranch(code, /*FALSE*/0));
-    case 0x3:
-    case 0x4:
-    case 0x5:
-    case 0x6:
-    case 0x7:
-      switch (code & 0xf) {
-        case 0x0: return(inst_neg(code, /*FALSE*/0));
-        case 0x1: return(inst_cbeq(code, false));
-        case 0x2:
-          switch (code) {
-            case 0x32: return(inst_ldhx(code, false));
-            case 0x42: return(inst_mul(code, false));
-            case 0x52: return(inst_div(code, false));
-            case 0x62: return(inst_nsa(code, false));
-            case 0x72: return(inst_daa(code, /*FALSE*/0));
-            default: return(resHALT);
-          }
-        case 0x3: return(inst_com(code, /*FALSE*/0));
-        case 0x4: return(inst_lsr(code, /*FALSE*/0));
-        case 0x5:
-          switch (code) {
-            case 0x35: return(inst_sthx(code, /*FALSE*/0));
-            case 0x45:
-            case 0x55: return(inst_ldhx(code, /*FALSE*/0));
-            case 0x65:
-            case 0x75: return(inst_cphx(code, /*FALSE*/0));
-            default: return(resHALT);
-          }
-        case 0x6: return(inst_ror(code, /*FALSE*/0));
-        case 0x7: return(inst_asr(code, /*FALSE*/0));
-        case 0x8: return(inst_lsl(code, /*FALSE*/0));
-        case 0x9: return(inst_rol(code, /*FALSE*/0));
-        case 0xa: return(inst_dec(code, /*FALSE*/0));
-        case 0xb: return(inst_dbnz(code, /*FALSE*/0));
-        case 0xc: return(inst_inc(code, /*FALSE*/0));
-        case 0xd: return(inst_tst(code, false));
-        case 0xe:
-          switch (code) {
-            case 0x3e: return(inst_cphx(code, false));
-            case 0x4e:
-            case 0x5e:
-            case 0x6e:
-            case 0x7e: return(inst_mov(code, /*FALSE*/0));
-            default: return(resHALT);
-          }
-        case 0xf: return(inst_clr(code, /*FALSE*/0));
-        default: return(resHALT);
-      }
-    case 0x8:
-      switch (code & 0xf) {
-        case 0x0: return(inst_rti(code, /*FALSE*/0));
-        case 0x1: return(inst_rts(code, /*FALSE*/0));
-        case 0x3: return(inst_swi(code, /*FALSE*/0));
-        case 0x4:
-        case 0x5: return(inst_transfer(code, /*FALSE*/0));
-        case 0x6:
-        case 0x7:
-        case 0x8:
-        case 0x9:
-        case 0xa:
-        case 0xb: return(inst_pushpull(code, /*FALSE*/0));
-        case 0xc: return(inst_clrh(code, false));
-        case 0xe: return(inst_stop(code, false));
-        case 0xf: return(inst_wait(code, false));
-        default: return(resINV_INST); // 0x82 and 0x8d not valid
-      }
-    case 0x9:
-      switch (code & 0xf) {
-        case 0x0:
-        case 0x1:
-        case 0x2:
-        case 0x3: return(inst_condbranch(code, false));
-        case 0x4:
-        case 0x5: return(inst_transfer(code, false));
-        case 0x6: return(inst_sthx(code, false));
-        case 0x7:
-        case 0xf: return(inst_transfer(code, false));
-        case 0x8:
-        case 0x9:
-        case 0xa:
-        case 0xb: return(inst_setclearflags(code, false));
-        case 0xc: return(inst_rsp(code, false));
-        case 0xd: return(inst_nop(code, false));
-        case 0xe: // start 0x9e prefix handling
-          code = fetch();
-          tick(1);
-          switch ((code >> 4) & 0xf) {
-            case 0x6:
-              switch (code & 0xf) {
-                case 0x0: return(inst_neg(code, /*TRUE*/1));
-                case 0x1: return(inst_cbeq(code, /*TRUE*/1));
-                case 0x3: return(inst_com(code, /*TRUE*/1));
-                case 0x4: return(inst_lsr(code, /*TRUE*/1));
-                case 0x6: return(inst_ror(code, /*TRUE*/1));
-                case 0x7: return(inst_asr(code, /*TRUE*/1));
-                case 0x8: return(inst_lsl(code, /*TRUE*/1));
-                case 0x9: return(inst_rol(code, /*TRUE*/1));
-                case 0xa: return(inst_dec(code, /*TRUE*/1));
-                case 0xb: return(inst_dbnz(code, /*TRUE*/1));
-                case 0xc: return(inst_inc(code, true));
-                case 0xd: return(inst_tst(code, true));
-                case 0xf: return(inst_clr(code, true));
-                default: return(resINV_INST); // 0x9e62, 0x9e65, 0x9e6e not valid
-              }
-            case 0xa:
-              switch (code) {
-                case 0xae: return(inst_ldhx(code,true));
-                default: return(resINV_INST);
-              }
-            case 0xb:
-              switch (code) {
-                case 0xbe: return(inst_ldhx(code,true));
-                default: return(resINV_INST);
-              }
-            case 0xc:
-              switch (code) {
-                case 0xce: return(inst_ldhx(code,true));
-                default: return(resINV_INST);
-              }
-            case 0xd:
-            case 0xe:
-              switch (code & 0xf) {
-                case 0x0: return(inst_sub(code, /*TRUE*/1));
-                case 0x1: return(inst_cmp(code, /*TRUE*/1));
-                case 0x2: return(inst_sbc(code, /*TRUE*/1));
-                case 0x3: return(inst_cpx(code, /*TRUE*/1));
-                case 0x4: return(inst_and(code, /*TRUE*/1));
-                case 0x5: return(inst_bit(code, /*TRUE*/1));
-                case 0x6: return(inst_lda(code, /*TRUE*/1));
-                case 0x7: return(inst_sta(code, /*TRUE*/1));
-                case 0x8: return(inst_eor(code, /*TRUE*/1));
-                case 0x9: return(inst_adc(code, true));
-                case 0xa: return(inst_ora(code, true));
-                case 0xb: return(inst_add(code, true));
-		case 0xc: return(resHALT); // not real instruction: regression test hack to exit simulation
-		case 0xd: putchar(regs.A); fflush(stdout); return(resGO); // not real instruction: regression test hack to output results
-                case 0xe: return(inst_ldx(code, true));
-                case 0xf: return(inst_stx(code, true));
-                default: return(resHALT);
-              }
-            case 0xf:
-              switch (code & 0xf) {
-                case 0x3: return(inst_cphx(code, true));
-                case 0xe: return(inst_ldhx(code, true));
-                case 0xf: return(inst_sthx(code, true));
-              }
-            default: return(resINV_INST);
-	    // end 0x9e prefix handling
-          }
-
-      }
-    case 0xa:
-    case 0xb:
-    case 0xc:
-    case 0xd:
-    case 0xe:
-    case 0xf:
-      switch (code & 0xf) {
-        case 0x0: return(inst_sub(code, /*FALSE*/0));
-        case 0x1: return(inst_cmp(code, /*FALSE*/0));
-        case 0x2: return(inst_sbc(code, /*FALSE*/0));
-        case 0x3: return(inst_cpx(code, /*FALSE*/0));
-        case 0x4: return(inst_and(code, /*FALSE*/0));
-        case 0x5: return(inst_bit(code, /*FALSE*/0));
-        case 0x6: return(inst_lda(code, /*FALSE*/0));
-        case 0x7:
-          if (code==0xa7)
-            return(inst_ais(code, /*FALSE*/0));
-          else
-            return(inst_sta(code, /*FALSE*/0));
-        case 0x8: return(inst_eor(code, /*FALSE*/0));
-        case 0x9: return(inst_adc(code, /*FALSE*/0));
-        case 0xa: return(inst_ora(code, /*FALSE*/0));
-        case 0xb: return(inst_add(code, false));
-        case 0xc:
-          if (code==0xac)
-            return(resINV_INST);
-          else
-            return(inst_jmp(code, false));
-        case 0xd:
-          if (code==0xad)
-            return(inst_bsr(code, /*FALSE*/0));
-          else
-            return(inst_jsr(code, /*FALSE*/0));
-        case 0xe: return(inst_ldx(code, /*FALSE*/0));
-        case 0xf:
-          if (code==0xaf)
-            return(inst_aix(code, /*FALSE*/0));
-          else
-            return(inst_stx(code, /*FALSE*/0));
-        default: return(resHALT);
-      }
-    default: return(resHALT);
-  }
-
-  /*if (PC)
-    PC--;
-  else
-  PC= get_mem_size(MEM_ROM_ID)-1;*/
-  PC= rom->inc_address(PC, -1);
-
-  sim->stop(resINV_INST);
-  return(resINV_INST);
-}
-
-t_mem
-cl_hc08::get_1(t_addr addr)
-{
-  vc.rd++;
-  return ram->read(addr & 0xffff);
-}
-
-t_mem
-cl_hc08::get_2(t_addr addr)
-{
-  vc.rd+= 2;
-  return (ram->read(addr & 0xffff) << 8) | ram->read((addr+1) & 0xffff);
-}
-
-/* End of hc08.src/hc08.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/hc08.src/hc08cl.h sdcc-4.2.0+dfsg/sim/ucsim/hc08.src/hc08cl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/hc08.src/hc08cl.h	2017-01-24 13:53:15.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/hc08.src/hc08cl.h	1970-01-01 00:00:00.000000000 +0000
@@ -1,81 +0,0 @@
-/*
- * Simulator of microcontrollers (hc08cl.h)
- *
- * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
- *
- * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
- *
- */
-
-/* This file is part of microcontroller simulator: ucsim.
-
-UCSIM is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2 of the License, or
-(at your option) any later version.
-
-UCSIM is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with UCSIM; see the file COPYING.  If not, write to the Free
-Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-02111-1307, USA. */
-/*@1@*/
-
-#ifndef HC08CL_HEADER
-#define HC08CL_HEADER
-
-#include "uccl.h"
-
-#include "regshc08.h"
-
-
-/*
- * Base type of Z80 microcontrollers
- */
-
-class cl_hc08: public cl_uc
-{
-public:
-  class cl_memory *ram;
-  class cl_memory *rom;
-  class cl_address_space *regs8, *regs16;
-  struct t_regs regs;
-public:
-  cl_hc08(struct cpu_entry *Itype, class cl_sim *asim);
-  virtual int init(void);
-  virtual char *id_string(void);
-
-  //virtual t_addr get_mem_size(enum mem_class type);
-  virtual void mk_hw_elements(void);
-  virtual void make_memories(void);
-
-  virtual struct dis_entry *dis_tbl(void);
-  virtual int inst_length(t_addr addr);
-  virtual int inst_branch(t_addr addr);
-  virtual int longest_inst(void);
-  virtual char *disass(t_addr addr, const char *sep);
-  virtual void print_regs(class cl_console_base *con);
-
-  virtual int exec_inst(void);
-
-  virtual const char * get_disasm_info(t_addr addr,
-				       int *ret_len,
-				       int *ret_branch,
-				       int *immed_offset,
-				       struct dis_entry **dentry);
-  virtual bool is_call(t_addr addr);
-  virtual t_mem get_1(t_addr addr);
-  virtual t_mem get_2(t_addr addr);
-  
-  virtual void reset(void);
-#include "instcl.h"
-};
-
-
-#endif
-
-/* End of hc08.src/hc08cl.h */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/hc08.src/hc08mac.h sdcc-4.2.0+dfsg/sim/ucsim/hc08.src/hc08mac.h
--- sdcc-4.0.0+dfsg/sim/ucsim/hc08.src/hc08mac.h	2016-12-13 10:53:09.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/hc08.src/hc08mac.h	1970-01-01 00:00:00.000000000 +0000
@@ -1,49 +0,0 @@
-/*
- * Simulator of microcontrollers (z80mac.h)
- *
- * some z80 code base from Karl Bongers karl@turbobit.com
- *
- * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
- * 
- * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
- *
- */
-
-// shift positions
-#define BITPOS_C 0  // 1
-#define BITPOS_Z 1  // 2H
-#define BITPOS_N 2  // 4H
-#define BITPOS_I 3  // 8H
-#define BITPOS_H 4  // 10H
-#define BITPUS_V 7  // 80H
-
-#define store2(addr, val) { ram->write((t_addr) (addr) & 0xffff, (val >> 8) & 0xff); \
-                            ram->write((t_addr) (addr+1) & 0xffff, val & 0xff); \
-  			    vc.wr+=2; }
-#define store1(addr, val) { ram->write((t_addr) (addr), val); vc.wr++; }
-//#define get1(addr) ram->get((t_addr) (addr) & 0xffff)
-#define get1(addr) get_1(addr)
-//#define get2(addr) ((ram->get((t_addr) (addr) & 0xffff) << 8) | ram->get((t_addr) (addr+1) & 0xffff) )
-#define get2(addr) get_2(addr)
-//#define fetch2() ((fetch() << 8) | fetch() )
-#define fetch1() fetch()
-#define push2(val) {store2(regs.SP-1,(val)); regs.SP-=2; }
-#define push1(val) {store1(regs.SP,(val)); regs.SP-=1; }
-#define pop2(var) {var=get2(regs.SP+1); regs.SP+=2;}
-#define pop1(var) {var=get1(regs.SP+1); regs.SP+=1;}
-#define add_u16_disp(_w, _d) (( (unsigned short)(_w) + (char)(_d) ) & 0xffff)
-
-
-#define FLAG_SET(f) {regs.P |= f;}
-#define FLAG_CLEAR(f) {regs.P &= ~(f);}
-#define FLAG_ASSIGN(f,c) {regs.P = (c) ? regs.P | (f) : regs.P & ~(f);}
-#define FLAG_NZ(f) { \
-      regs.P = (regs.P & ~(BIT_N|BIT_Z)) \
-      | (((f) & 0xff) ? 0 : BIT_Z) \
-      | (((f) & 0x80) ? BIT_N : 0) \
-      ; }
-#define EA_IMM(c) ((((c) >> 4) & 0xf)==0xa)
-#define OPERAND(code,prefix) (EA_IMM(code) ? fetch() : get1(fetchea(code,prefix)))
-
-
-
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/hc08.src/inst.cc sdcc-4.2.0+dfsg/sim/ucsim/hc08.src/inst.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/hc08.src/inst.cc	2017-01-24 13:53:15.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/hc08.src/inst.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,1353 +0,0 @@
-/*
- * Simulator of microcontrollers (inst.cc)
- *
- * hc08 code base from Erik Petrich  epetrich@users.sourceforge.net
- *
- * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
- * 
- * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
- *
- */
-
-/* This file is part of microcontroller simulator: ucsim.
-
-UCSIM is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2 of the License, or
-(at your option) any later version.
-
-UCSIM is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with UCSIM; see the file COPYING.  If not, write to the Free
-Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-02111-1307, USA. */
-/*@1@*/
-
-#include "ddconfig.h"
-#include "stdio.h"
-#include 
-
-// local
-#include "hc08cl.h"
-#include "regshc08.h"
-#include "hc08mac.h"
-
-
-void
-cl_hc08::incx(void)
-{
-  int hx = (regs.H << 8) | (regs.X);
-  hx++;
-  regs.H = (hx >> 8) & 0xff;
-  regs.X = hx & 0xff;
-}
-
-int
-cl_hc08::fetch2(void)
-{
-  int result;
-  result = fetch() << 8;
-  result |= fetch();
-  tick(2);
-  return result;
-}
-
-int
-cl_hc08::fetchea(t_mem code, bool prefix)
-{
-  switch ((code >> 4) & 0x0f) {
-    case 0x0: 
-    case 0x1:
-    case 0x3:
-    case 0xb:
-      tick(1);
-      return fetch(); // Direct
-    case 0x7:
-    case 0xf:
-      tick(1); // extra cycle needed, even without fetch
-      return (regs.H << 8) | regs.X;  // IX
-    case 0x6:
-    case 0xe:
-      tick(1);
-      if (!prefix)
-        return ((unsigned char)fetch())+((regs.H << 8) | regs.X); // IX1
-      else
-        return ((unsigned char)fetch())+regs.SP; // SP1
-    case 0xd:
-      if (!prefix)
-        return fetch2()+((regs.H << 8) | regs.X); // IX2
-      else
-        return fetch2()+regs.SP; // SP2
-    case 0xc:
-      return fetch2();
-    default:
-      return(resHALT);
-  }
-}
-
-
-int
-cl_hc08::inst_nop(t_mem code, bool prefix)
-{
-  return(resGO);
-}
-
-
-int
-cl_hc08::inst_transfer(t_mem code, bool prefix)
-{
-  int hx;
-  
-  switch (code) {
-    case 0x84: // TAP
-      regs.P = regs.A | 0x60;
-      break;
-    case 0x85: // TPA
-      regs.A = regs.P | 0x60;
-      break;
-    case 0x97: // TAX
-      regs.X = regs.A;
-      break;
-    case 0x9f: // TXA
-      regs.A = regs.X;
-      break;
-    case 0x94: // TXS
-      hx = (regs.H << 8) | regs.X;
-      regs.SP = (hx - 1) & 0xffff;
-      break;
-    case 0x95: // TSX
-      hx = regs.SP +1;
-      regs.H = (hx >> 8) & 0xff;
-      regs.X = hx & 0xff;
-      break;
-    default:
-      return(resHALT);
-  }
-  return(resGO);
-}
-
-
-int
-cl_hc08::inst_setclearflags(t_mem code, bool prefix)
-{
-  switch (code) {
-    case 0x98:
-      regs.P &= ~BIT_C;
-      break;
-    case 0x99:
-      regs.P |= BIT_C;
-      break;
-    case 0x9a:
-      regs.P &= ~BIT_I;
-      break;
-    case 0x9b:
-      regs.P |= BIT_I;
-      break;
-    default:
-      return(resHALT);
-  }
-  return(resGO);
-}
-
-
-int
-cl_hc08::inst_rsp(t_mem code, bool prefix)
-{
-  regs.SP = 0x00ff;
-  return(resGO);
-}
-
-
-int
-cl_hc08::inst_nsa(t_mem code, bool prefix)
-{
-  regs.A = ((regs.A & 0xf0)>>4) | ((regs.A & 0x0f)<<4);
-  return(resGO);
-}
-
-
-
-int
-cl_hc08::inst_lda(t_mem code, bool prefix)
-{
-  regs.A = OPERAND(code, prefix);
-  tick(1);
-  FLAG_CLEAR(BIT_V);
-  FLAG_NZ(regs.A);
-  return(resGO);
-}
-
-int
-cl_hc08::inst_ldx(t_mem code, bool prefix)
-{
-  regs.X = OPERAND(code, prefix);
-  tick(1);
-  FLAG_CLEAR(BIT_V);
-  FLAG_NZ(regs.X);
-  return(resGO);
-}
-
-int
-cl_hc08::inst_sta(t_mem code, bool prefix)
-{
-  int ea = fetchea(code, prefix);
-
-  FLAG_CLEAR(BIT_V);
-  FLAG_NZ(regs.A);
-  store1(ea, regs.A);
-  tick(1);
-  return(resGO);
-}
-
-int
-cl_hc08::inst_stx(t_mem code, bool prefix)
-{
-  int ea = fetchea(code, prefix);
-
-  FLAG_CLEAR(BIT_V);
-  FLAG_NZ(regs.X);
-  store1(ea, regs.X);
-  tick(1);
-  return(resGO);
-}
-
-int
-cl_hc08::inst_add(t_mem code, bool prefix)
-{
-  int result, operand1, operand2;
-
-  operand1 = regs.A;
-  operand2 = OPERAND(code, prefix);
-  tick(1);
-  result = operand1 + operand2;
-  FLAG_NZ (result);
-  FLAG_ASSIGN (BIT_V, 0x80 & (operand1 ^ operand2 ^ result ^ (result >>1)));
-  FLAG_ASSIGN (BIT_C, 0x100 & result);
-  FLAG_ASSIGN (BIT_H, 0x10 & (operand1 ^ operand2 ^ result));
-
-  regs.A = result & 0xff;
-  return(resGO);
-}
-
-int
-cl_hc08::inst_adc(t_mem code, bool prefix)
-{
-  int result, operand1, operand2;
-  int carryin = (regs.P & BIT_C)!=0;
-
-  operand1 = regs.A;
-  operand2 = OPERAND(code, prefix);
-  tick(1);
-  result = operand1 + operand2 + carryin;
-  FLAG_NZ (result);
-  FLAG_ASSIGN (BIT_V, 0x80 & (operand1 ^ operand2 ^ result ^ (result >>1)));
-  FLAG_ASSIGN (BIT_C, 0x100 & result);
-  FLAG_ASSIGN (BIT_H, 0x10 & (operand1 ^ operand2 ^ result));
-
-  regs.A = result & 0xff;
-  return(resGO);
-}
-
-int
-cl_hc08::inst_sub(t_mem code, bool prefix)
-{
-  int result, operand1, operand2;
-
-  operand1 = regs.A;
-  operand2 = OPERAND(code, prefix);
-  tick(1);
-  result = operand1 - operand2;
-  FLAG_NZ (result);
-  FLAG_ASSIGN (BIT_V, 0x80 & (operand1 ^ operand2 ^ result ^ (result >>1)));
-  FLAG_ASSIGN (BIT_C, 0x100 & result);
-
-  regs.A = result & 0xff;
-  return(resGO);
-}
-
-int
-cl_hc08::inst_sbc(t_mem code, bool prefix)
-{
-  int result, operand1, operand2;
-  int carryin = (regs.P & BIT_C)!=0;
-
-  operand1 = regs.A;
-  operand2 = OPERAND(code, prefix);
-  tick(1);
-  result = operand1 - operand2 - carryin;
-  FLAG_NZ (result);
-  FLAG_ASSIGN (BIT_V, 0x80 & (operand1 ^ operand2 ^ result ^ (result >>1)));
-  FLAG_ASSIGN (BIT_C, 0x100 & result);
-
-  regs.A = result & 0xff;
-  return(resGO);
-}
-
-int
-cl_hc08::inst_cmp(t_mem code, bool prefix)
-{
-  int result, operand1, operand2;
-
-  operand1 = regs.A;
-  operand2 = OPERAND(code, prefix);
-  tick(1);
-  result = operand1 - operand2;
-  FLAG_NZ (result);
-  FLAG_ASSIGN (BIT_V, 0x80 & (operand1 ^ operand2 ^ result ^ (result >>1)));
-  FLAG_ASSIGN (BIT_C, 0x100 & result);
-
-  return(resGO);
-}
-
-int
-cl_hc08::inst_cpx(t_mem code, bool prefix)
-{
-  int result, operand1, operand2;
-
-  operand1 = regs.X;
-  operand2 = OPERAND(code, prefix);
-  tick(1);
-  result = operand1 - operand2;
-  FLAG_NZ (result);
-  FLAG_ASSIGN (BIT_V, 0x80 & (operand1 ^ operand2 ^ result ^ (result >>1)));
-  FLAG_ASSIGN (BIT_C, 0x100 & result);
-
-  return(resGO);
-}
-
-int
-cl_hc08::inst_jmp(t_mem code, bool prefix)
-{
-  PC = fetchea(code, prefix);
-  tick(1); // extra cycle to reload pipeline
-  return(resGO);
-}
-
-int
-cl_hc08::inst_jsr(t_mem code, bool prefix)
-{
-  int newPC = fetchea(code, prefix);
-
-  push2(PC);
-  tick(2);
-  PC = newPC;
-  tick(1); // extra cycle to reload pipeline
-
-  return(resGO);
-}
-
-int
-cl_hc08::inst_bsr(t_mem code, bool prefix)
-{
-  signed char ofs = fetch();
-
-  push2(PC);
-  tick(2);
-  PC += ofs;
-  tick(1); // extra cycle to reload pipeline
-
-  return(resGO);
-}
-
-int
-cl_hc08::inst_ais(t_mem code, bool prefix)
-{
-  regs.SP = regs.SP + (signed char)fetch();
-  return(resGO);
-}
-
-int
-cl_hc08::inst_aix(t_mem code, bool prefix)
-{
-  int hx = (regs.H << 8) | (regs.X);
-  hx += (signed char)fetch();
-  tick(1);
-  regs.H = (hx >> 8) & 0xff;
-  regs.X = hx & 0xff;
-  return(resGO);
-}
-
-int
-cl_hc08::inst_and(t_mem code, bool prefix)
-{
-  regs.A = regs.A & OPERAND(code, prefix);
-  tick(1);
-  FLAG_CLEAR(BIT_V);
-  FLAG_NZ(regs.A);
-  return(resGO);
-}
-
-int
-cl_hc08::inst_bit(t_mem code, bool prefix)
-{
-  uchar operand = regs.A & OPERAND(code, prefix);
-  tick(1);
-  FLAG_CLEAR(BIT_V);
-  FLAG_NZ(operand);
-  return(resGO);
-}
-
-int
-cl_hc08::inst_ora(t_mem code, bool prefix)
-{
-  regs.A = regs.A | OPERAND(code, prefix);
-  tick(1);
-  FLAG_CLEAR(BIT_V);
-  FLAG_NZ(regs.A);
-  return(resGO);
-}
-
-int
-cl_hc08::inst_eor(t_mem code, bool prefix)
-{
-  regs.A = regs.A ^ OPERAND(code, prefix);
-  tick(1);
-  FLAG_CLEAR(BIT_V);
-  FLAG_NZ(regs.A);
-  return(resGO);
-}
-
-int
-cl_hc08::inst_asr(t_mem code, bool prefix)
-{
-  int ea = 0xffff;
-  uchar operand;
-  
-  if ((code & 0xf0) == 0x40)
-    operand = regs.A;
-  else if ((code & 0xf0) == 0x50)
-    operand = regs.X;
-  else {
-    ea = fetchea(code,prefix);
-    operand = get1(ea);
-    tick(1);
-  }
-
-  FLAG_ASSIGN (BIT_C, operand & 1);
-  operand = (operand >> 1) | (operand & 0x80);
-  FLAG_NZ (operand);
-  FLAG_ASSIGN (BIT_V, ((regs.P & BIT_C)!=0) ^ ((regs.P & BIT_N)!=0));
-
-  if ((code & 0xf0) == 0x40)
-    regs.A = operand;
-  else if ((code & 0xf0) == 0x50)
-    regs.X = operand;
-  else {
-    store1(ea, operand);
-    tick(1);
-    if ((code & 0x70) != 0x70)
-      tick(1);
-  }
-
-  return(resGO);
-}
-
-
-int
-cl_hc08::inst_lsr(t_mem code, bool prefix)
-{
-  int ea = 0xffff;
-  uchar operand;
-  
-  if ((code & 0xf0) == 0x40)
-    operand = regs.A;
-  else if ((code & 0xf0) == 0x50)
-    operand = regs.X;
-  else {
-    ea = fetchea(code,prefix);
-    operand = get1(ea);
-    tick(1);
-  }
-
-  FLAG_ASSIGN (BIT_C, operand & 1);
-  operand = (operand >> 1) & 0x7f;
-  FLAG_NZ (operand);
-  FLAG_ASSIGN (BIT_V, ((regs.P & BIT_C)!=0) ^ ((regs.P & BIT_N)!=0));
-
-  if ((code & 0xf0) == 0x40)
-    regs.A = operand;
-  else if ((code & 0xf0) == 0x50)
-    regs.X = operand;
-  else {
-    store1(ea, operand);
-    tick(1);
-    if ((code & 0x70) != 0x70)
-      tick(1);
-  }
-  return(resGO);
-}
-
-
-int
-cl_hc08::inst_lsl(t_mem code, bool prefix)
-{
-  int ea = 0xffff;
-  uchar operand;
-  
-  if ((code & 0xf0) == 0x40)
-    operand = regs.A;
-  else if ((code & 0xf0) == 0x50)
-    operand = regs.X;
-  else {
-    ea = fetchea(code,prefix);
-    operand = get1(ea);
-    tick(1);
-  }
-
-  FLAG_ASSIGN (BIT_C, operand & 0x80);
-  operand = (operand << 1);
-  FLAG_NZ (operand);
-  FLAG_ASSIGN (BIT_V, ((regs.P & BIT_C)!=0) ^ ((regs.P & BIT_N)!=0));
-
-  if ((code & 0xf0) == 0x40)
-    regs.A = operand;
-  else if ((code & 0xf0) == 0x50)
-    regs.X = operand;
-  else {
-    store1(ea, operand);
-    tick(1);
-    if ((code & 0x70) != 0x70)
-      tick(1);
-  }
-  return(resGO);
-}
-
-
-int
-cl_hc08::inst_rol(t_mem code, bool prefix)
-{
-  uchar c = (regs.P & BIT_C)!=0;
-  int ea = 0xffff;
-  uchar operand;
-  
-  if ((code & 0xf0) == 0x40)
-    operand = regs.A;
-  else if ((code & 0xf0) == 0x50)
-    operand = regs.X;
-  else {
-    ea = fetchea(code,prefix);
-    operand = get1(ea);
-    tick(1);
-  }
-
-  FLAG_ASSIGN (BIT_C, operand & 0x80);
-  operand = (operand << 1) | c;
-  FLAG_NZ (operand);
-  FLAG_ASSIGN (BIT_V, ((regs.P & BIT_C)!=0) ^ ((regs.P & BIT_N)!=0));
-
-  if ((code & 0xf0) == 0x40)
-    regs.A = operand;
-  else if ((code & 0xf0) == 0x50)
-    regs.X = operand;
-  else {
-    store1(ea, operand);
-    tick(1);
-    if ((code & 0x70) != 0x70)
-      tick(1);
-  }
-  return(resGO);
-}
-
-
-int
-cl_hc08::inst_ror(t_mem code, bool prefix)
-{
-  uchar c = (regs.P & BIT_C)!=0;
-  int ea = 0xffff;
-  uchar operand;
-  
-  if ((code & 0xf0) == 0x40)
-    operand = regs.A;
-  else if ((code & 0xf0) == 0x50)
-    operand = regs.X;
-  else {
-    ea = fetchea(code,prefix);
-    operand = get1(ea);
-    tick(1);
-  }
-
-  FLAG_ASSIGN (BIT_C, operand & 1);
-  operand = (operand >> 1) | (c << 7);
-  FLAG_NZ (operand);
-  FLAG_ASSIGN (BIT_V, ((regs.P & BIT_C)!=0) ^ ((regs.P & BIT_N)!=0));
-
-  if ((code & 0xf0) == 0x40)
-    regs.A = operand;
-  else if ((code & 0xf0) == 0x50)
-    regs.X = operand;
-  else {
-    store1(ea, operand);
-    tick(1);
-    if ((code & 0x70) != 0x70)
-      tick(1);
-  }
-  return(resGO);
-}
-
-
-int
-cl_hc08::inst_inc(t_mem code, bool prefix)
-{
-  int ea = 0xffff;
-  uchar operand;
-  
-  if ((code & 0xf0) == 0x40)
-    operand = regs.A;
-  else if ((code & 0xf0) == 0x50)
-    operand = regs.X;
-  else {
-    ea = fetchea(code,prefix);
-    operand = get1(ea);
-    tick(1);
-  }
-
-  operand++;
-  FLAG_NZ (operand);
-  FLAG_ASSIGN (BIT_V, operand == 0x80);
-
-  if ((code & 0xf0) == 0x40)
-    regs.A = operand;
-  else if ((code & 0xf0) == 0x50)
-    regs.X = operand;
-  else {
-    store1(ea, operand);
-    tick(1);
-    if ((code & 0x70) != 0x70)
-      tick(1);
-  }
-  return(resGO);
-}
-
-
-int
-cl_hc08::inst_dec(t_mem code, bool prefix)
-{
-  int ea = 0xffff;
-  uchar operand;
-  
-  if ((code & 0xf0) == 0x40)
-    operand = regs.A;
-  else if ((code & 0xf0) == 0x50)
-    operand = regs.X;
-  else {
-    ea = fetchea(code,prefix);
-    operand = get1(ea);
-    tick(1);
-  }
-
-  operand--;
-  FLAG_NZ (operand);
-  FLAG_ASSIGN (BIT_V, operand == 0x7f);
-
-  if ((code & 0xf0) == 0x40)
-    regs.A = operand;
-  else if ((code & 0xf0) == 0x50)
-    regs.X = operand;
-  else {
-    store1(ea, operand);
-    tick(1);
-    if ((code & 0x70) != 0x70)
-      tick(1);
-  }
-  return(resGO);
-}
-
-int
-cl_hc08::inst_dbnz(t_mem code, bool prefix)
-{
-  int ea = 0xffff;
-  uchar operand;
-  signed char ofs;
-  
-  if ((code & 0xf0) == 0x40)
-    operand = regs.A;
-  else if ((code & 0xf0) == 0x50)
-    operand = regs.X;
-  else {
-    ea = fetchea(code,prefix);
-    operand = get1(ea);
-    tick(1);
-  }
-
-  operand--;
-  FLAG_NZ (operand);
-  FLAG_ASSIGN (BIT_V, operand == 0x7f);
-
-  if ((code & 0xf0) == 0x40)
-    regs.A = operand;
-  else if ((code & 0xf0) == 0x50)
-    regs.X = operand;
-  else {
-    store1(ea, operand);
-    tick(1);
-    if ((code & 0x70) != 0x70)
-      tick(1);
-  }
-
-  ofs = fetch();
-  tick(1);
-  if (operand)
-    PC += ofs;
-  tick(1); // extra cycle to reload pipeline
-
-  return(resGO);
-}
-
-
-int
-cl_hc08::inst_tst(t_mem code, bool prefix)
-{
-  int ea = 0xffff;
-  uchar operand;
-
-  if ((code & 0xf0) == 0x40)
-    operand = regs.A;
-  else if ((code & 0xf0) == 0x50)
-    operand = regs.X;
-  else {
-    ea = fetchea(code,prefix);
-    operand = get1(ea);
-    tick(1);
-  }
-
-  FLAG_NZ (operand);
-  FLAG_CLEAR (BIT_V);
-  if ((code & 0xf0) == 0x30 || (code & 0xf0) == 0x60)
-    tick(1);
-
-  return(resGO);
-}
-
-
-int
-cl_hc08::inst_clr(t_mem code, bool prefix)
-{
-  int ea = 0xffff;
-  uchar operand;
-
-  // clr uses read-modify-write cycles, so simulate the read even if the data isn't used
-  if ((code & 0xf0) == 0x40)
-    operand = regs.A;
-  else if ((code & 0xf0) == 0x50)
-    operand = regs.X;
-  else {
-    ea = fetchea(code,prefix);
-    operand = get1(ea);
-    tick(1);
-  }
-
-  operand = 0;
-  FLAG_CLEAR (BIT_V);
-  FLAG_CLEAR (BIT_N);
-  FLAG_SET (BIT_Z);
-
-  if ((code & 0xf0) == 0x40)
-    regs.A = operand;
-  else if ((code & 0xf0) == 0x50)
-    regs.X = operand;
-  else {
-    store1(ea, operand);
-    if ((code & 0x70) != 0x70)
-      tick(1);
-  }
-  return(resGO);
-}
-
-
-int
-cl_hc08::inst_clrh(t_mem code, bool prefix)
-{
-  FLAG_CLEAR (BIT_V);
-  FLAG_CLEAR (BIT_N);
-  FLAG_SET (BIT_Z);
-  regs.H = 0;
-  return(resGO);
-}
-
-
-int
-cl_hc08::inst_com(t_mem code, bool prefix)
-{
-  int ea = 0xffff;
-  uchar operand;
-  
-  if ((code & 0xf0) == 0x40)
-    operand = regs.A;
-  else if ((code & 0xf0) == 0x50)
-    operand = regs.X;
-  else {
-    ea = fetchea(code,prefix);
-    operand = get1(ea);
-    tick(1);
-  }
-
-  operand = ~operand;
-  FLAG_SET (BIT_C);
-  FLAG_NZ (operand);
-  FLAG_CLEAR (BIT_V);
-
-  if ((code & 0xf0) == 0x40)
-    regs.A = operand;
-  else if ((code & 0xf0) == 0x50)
-    regs.X = operand;
-  else {
-    store1(ea, operand);
-    if ((code & 0x70) != 0x70)
-      tick(1);
-  }
-  return(resGO);
-}
-
-
-int
-cl_hc08::inst_neg(t_mem code, bool prefix)
-{
-  int ea = 0xffff;
-  uchar operand;
-  
-  if ((code & 0xf0) == 0x40)
-    operand = regs.A;
-  else if ((code & 0xf0) == 0x50)
-    operand = regs.X;
-  else {
-    ea = fetchea(code,prefix);
-    operand = get1(ea);
-    tick(1);
-  }
-
-  FLAG_ASSIGN (BIT_V, operand==0x80);
-  FLAG_ASSIGN (BIT_C, operand!=0x00);
-  operand = -operand;
-  FLAG_NZ (operand);
-
-  if ((code & 0xf0) == 0x40)
-    regs.A = operand;
-  else if ((code & 0xf0) == 0x50)
-    regs.X = operand;
-  else {
-    store1(ea, operand);
-    if ((code & 0x70) != 0x70)
-      tick(1);
-  }
-  return(resGO);
-}
-
-
-
-int
-cl_hc08::inst_pushpull(t_mem code, bool prefix)
-{
-  switch (code) {
-    case 0x86:
-      pop1(regs.A);
-      tick(2);
-      break;
-    case 0x87:
-      push1(regs.A);
-      tick(1);
-      break;
-    case 0x88:
-      pop1(regs.X);
-      tick(2);
-      break;
-    case 0x89:
-      push1(regs.X);
-      tick(1);
-      break;
-    case 0x8a:
-      pop1(regs.H);
-      tick(2);
-      break;
-    case 0x8b:
-      push1(regs.H);
-      tick(1);
-      break;
-    default:
-      return(resHALT);
-  }
-  return(resGO);
-}
-
-
-
-
-int
-cl_hc08::inst_stop(t_mem code, bool prefix)
-{
-  FLAG_CLEAR (BIT_I);
-  return(resGO);
-}
-
-
-int
-cl_hc08::inst_wait(t_mem code, bool prefix)
-{
-  FLAG_CLEAR (BIT_I);
-  return(resGO);
-}
-
-
-int
-cl_hc08::inst_daa(t_mem code, bool prefix)
-{
-  uchar lsn, msn;
-
-  lsn = regs.A & 0xf;
-  msn = (regs.A >> 4) & 0xf;
-  if (regs.P & BIT_H) {
-    lsn += 16;
-    msn = (msn-1) & 0xf;
-  }
-  if (regs.P & BIT_C)
-    msn += 16;
-
-  FLAG_CLEAR (BIT_C);
-  while (lsn>9) {
-    lsn -= 10;
-    msn++;
-  }
-  if (msn>9) {
-    msn = msn % 10;
-    FLAG_SET (BIT_C);
-  }
-
-  return(resGO);
-}
-
-int
-cl_hc08::inst_mul(t_mem code, bool prefix)
-{
-  int result = regs.A * regs.X;
-  regs.A = result & 0xff;
-  regs.X = (result >> 8) & 0xff;
-  FLAG_CLEAR (BIT_C);
-  FLAG_CLEAR (BIT_H);
-  tick(4);
-  return(resGO);
-}
-
-int
-cl_hc08::inst_div(t_mem code, bool prefix)
-{
-  unsigned int dividend = (regs.H << 8) | regs.A;
-  unsigned int quotient;
-
-  if (regs.X) {
-    quotient = dividend / (unsigned int)regs.X;
-    if (quotient<=0xff) {
-      regs.A = quotient;
-      regs.H = dividend % regs.X;
-      FLAG_CLEAR (BIT_C);
-      FLAG_ASSIGN (BIT_Z, quotient==0);
-    }
-    else
-      FLAG_SET (BIT_C);  // overflow
-  } else
-    FLAG_SET (BIT_C);    // division by zero
-  tick(5);
-
-  return(resGO);
-}
-
-
-int
-cl_hc08::inst_condbranch(t_mem code, bool prefix)
-{
-  bool taken;
-  signed char ofs;
-  unsigned char maskedP;
-  
-  if ((code & 0xf0)==0x20) {
-    switch ((code>>1) & 7) {
-      case 0: // BRA
-        taken = 1;
-        break;
-      case 1: // BHI
-        taken = !(regs.P & (BIT_C | BIT_Z));
-        break;
-      case 2: // BCC
-        taken = !(regs.P & BIT_C);
-        break;
-      case 3: // BNE
-        taken = !(regs.P & BIT_Z);
-        break;
-      case 4: // BHCC
-        taken = !(regs.P & BIT_H);
-        break;
-      case 5: // BPL
-        taken = !(regs.P & BIT_N);
-        break;
-      case 6: // BMC
-        taken = !(regs.P & BIT_I);
-        break;
-      case 7: // BIL
-        taken = 0; // TODO: should read simulated IRQ# pin
-      default:
-        return(resHALT);
-    } 
-  }
-  else if ((code & 0xf0)==0x90) {
-    switch ((code>>1) & 7) {
-      case 0: // BGE
-        maskedP = regs.P & (BIT_N | BIT_V);
-        taken = !maskedP || (maskedP == (BIT_N | BIT_V));
-        break;
-      case 1: // BGT
-        maskedP = regs.P & (BIT_N | BIT_V | BIT_Z);
-        taken = !maskedP || (maskedP == (BIT_N | BIT_V));
-        break;
-      default:
-        return(resHALT);
-    }
-  }
-  else
-    return(resHALT);
-  
-  if (code & 1)
-    taken = ! taken;
-  
-  ofs = fetch();
-  tick(1);
-  if (taken)
-    PC += ofs;
-  tick(1); // extra cycle to reload pipeline
-
-  return(resGO);
-}
-
-int
-cl_hc08::inst_bitsetclear(t_mem code, bool prefix)
-{
-  uchar bit = (code >> 1) & 7;
-  int ea = fetchea(code, prefix);
-  uchar operand = get1(ea);
-  tick(1);
-
-  if (code & 1)
-    operand &= ~(1 << bit);
-  else
-    operand |= (1 << bit);
-  tick(1);
-  store1(ea, operand);
-  tick(1);
-  return(resGO);
-}
-
-int
-cl_hc08::inst_bittestsetclear(t_mem code, bool prefix)
-{
-  uchar bit = (code >> 1) & 7;
-  int ea = fetchea(code, prefix);
-  uchar operand = get1(ea);
-  signed char ofs;
-  bool taken;
-
-  tick(1);
-  if (code & 1)
-    taken = !(operand & (1 << bit));  // brclr
-  else
-    taken = (operand & (1 << bit));   // brset
-
-  ofs = fetch();
-  tick(1);
-  if (taken)
-    PC += ofs;
-  tick(1); // extra cycle to reload pipeline
-
-  FLAG_ASSIGN (BIT_C, operand & (1 << bit));
-  return(resGO);
-}
-
-int
-cl_hc08::inst_cbeq(t_mem code, bool prefix)
-{
-  int ea;
-  uchar operand1, operand2;
-  signed char ofs;
-    
-  if ((code & 0xf0) == 0x40) {
-    operand1 = regs.A;
-    operand2 = fetch();
-    tick(1);
-  }
-  else if ((code & 0xf0) == 0x50) {
-    operand1 = regs.X;
-    operand2 = fetch();
-    tick(1);
-  }
-  else {
-    ea = fetchea(code,prefix);
-    operand1 = get1(ea);
-    tick(1);
-    operand2 = regs.A;
-  }
-
-  ofs = fetch();
-  tick(1);
-  if (operand1==operand2)
-    PC += ofs;  
-
-  if (code == 0x71 || (!prefix && code == 0x61))
-    incx();
-  tick(1); // extra cycle to reload pipeline
-
-  return(resGO);
-}
-
-int
-cl_hc08::inst_rti(t_mem code, bool prefix)
-{
-  pop1(regs.P);
-  tick(1);
-  regs.P |= 0x60;
-  pop1(regs.A);
-  tick(1);
-  pop1(regs.X);
-  tick(1);
-  pop2(PC);
-  tick(2);
-  tick(3); // pipeline reload and some extra overhead?
-
-  return(resGO);
-}
-
-int
-cl_hc08::inst_rts(t_mem code, bool prefix)
-{
-  pop2(PC);
-  tick(2);
-  tick(3); // pipeline reload and some extra overhead?
-
-  return(resGO);
-}
-
-
-int
-cl_hc08::inst_mov(t_mem code, bool prefix)
-{
-  int ea;
-  uchar operand;
-  bool aix;
-  int hx = (regs.H << 8) | (regs.X);
-  
-  switch (code) {
-    case 0x4e:	//mov opr8a,opr8a
-      operand = get1(fetch());
-      tick(2);
-      ea = fetch();
-      tick(1);
-      aix = 0;
-      break;
-    case 0x5e:	//mov opr8a,x+
-      operand = get1(fetch());
-      tick(2);
-      tick(1);
-      ea = hx;
-      aix = 1;
-      break;
-    case 0x6e:	//mov #opr8i,opr8a
-      operand = fetch();
-      tick(1);
-      ea = fetch();
-      tick(1);
-      aix = 0;
-      break;
-    case 0x7e:	//mov x+,opr8a
-      operand = get1(hx);
-      tick(1);
-      ea = fetch();
-      tick(1);
-      tick(1);
-      aix = 1;
-      break;
-    default:
-      return(resHALT);
-  }
-
-  store1(ea, operand);
-  tick(1);
-  if (aix)
-    incx();
-
-  FLAG_NZ(operand);
-  FLAG_CLEAR(BIT_V);
-
-  return(resGO);
-}
-
-
-int
-cl_hc08::inst_sthx(t_mem code, bool prefix)
-{
-  int ea;
-  
-  if (code == 0x35) {
-    ea = fetch();
-    tick(1);
-  }
-  else if ((code == 0x96) && (type->type == CPU_HCS08))
-  {
-    ea = fetch2();
-    tick(2);
-  }
-  else if (prefix && (code == 0xff) && (type->type == CPU_HCS08))
-  {
-    ea = regs.SP + fetch();
-    tick(1);
-  }
-  else
-    return(resINV_INST);
-  
-  store1(ea, regs.H);
-  tick(1);
-  store1((ea+1) & 0xffff, regs.X);
-  tick(1);
-
-  FLAG_CLEAR(BIT_V);
-  FLAG_ASSIGN(BIT_N, regs.H & 0x80);
-  FLAG_ASSIGN(BIT_Z, !regs.X && !regs.H);
-  return(resGO);
-}
-
-int
-cl_hc08::inst_ldhx(t_mem code, bool prefix)
-{
-  int ea;
-  
-  if (code == 0x45) {
-    regs.H = fetch();
-    tick(1);
-    regs.X = fetch();
-    tick(1);
-  }
-  else if (code == 0x55) {
-    ea = fetch();
-    tick(1);
-    regs.H = get1(ea);
-    tick(1);
-    regs.X = get1(ea+1);
-    tick(1);
-  }
-  else if ((code == 0x32) && (type->type == CPU_HCS08)) {
-    ea = fetch2();
-    tick(2);
-    regs.H = get1(ea);
-    tick(1);
-    regs.X = get1(ea+1);
-    tick(1);
-  }
-  else if (prefix && (code == 0xae) && (type->type == CPU_HCS08)) {
-    ea = (regs.H << 8) | regs.X;
-    tick(1);
-    regs.H = get1(ea);
-    tick(1);
-    regs.X = get1(ea+1);
-    tick(1);
-  }
-  else if (prefix && (code == 0xbe) && (type->type == CPU_HCS08)) {
-    ea = ((regs.H << 8) | regs.X) + fetch2();
-    tick(2);
-    regs.H = get1(ea);
-    tick(1);
-    regs.X = get1(ea+1);
-    tick(1);
-  }
-  else if (prefix && (code == 0xce) && (type->type == CPU_HCS08)) {
-    ea = ((regs.H << 8) | regs.X) + fetch();
-    tick(1);
-    regs.H = get1(ea);
-    tick(1);
-    regs.X = get1(ea+1);
-    tick(1);
-  }
-  else if (prefix && (code == 0xfe) && (type->type == CPU_HCS08)) {
-    ea = regs.SP + fetch();
-    tick(1);
-    regs.H = get1(ea);
-    tick(1);
-    regs.X = get1(ea+1);
-    tick(1);
-  }
-  else
-    return(resINV_INST);
-  
-  FLAG_CLEAR(BIT_V);
-  FLAG_ASSIGN(BIT_N, regs.H & 0x80);
-  FLAG_ASSIGN(BIT_Z, !regs.X && !regs.H);
-  return(resGO);
-}
-
-
-int
-cl_hc08::inst_cphx(t_mem code, bool prefix)
-{
-  int ea;
-  int hx;
-  int operand;
-  int result;
-  
-  if (code == 0x65) {
-    operand = fetch2();
-    tick(2);
-  }
-  else if (code == 0x75) {
-    ea = fetch();
-    tick(1);
-    operand = (get1(ea) << 8) | get1(ea+1);
-    tick(2);
-    tick(1);
-  }
-  else if ((code == 0x3e) && (type->type == CPU_HCS08)) {
-    ea = fetch2();
-    tick(2);
-    operand = (get1(ea) << 8) | get1(ea+1);
-    tick(2);
-    tick(1);
-  }
-  else if (prefix && (code == 0xf3) && (type->type == CPU_HCS08)) {
-    ea = ((unsigned char)fetch())+regs.SP;
-    tick(1);
-    operand = (get1(ea) << 8) | get1(ea+1);
-    tick(2);
-    tick(1);
-  }
-  else
-    return(resINV_INST);
-
-  hx = (regs.H << 8) | regs.X;
-  result = hx-operand;
-
-  FLAG_ASSIGN (BIT_V, 0x8000 & (hx ^ operand ^ result ^ (result>>1)));
-  FLAG_ASSIGN (BIT_C, 0x10000 & result);
-  FLAG_ASSIGN(BIT_N, result & 0x8000);
-  FLAG_ASSIGN(BIT_Z, !(result & 0xffff));
-
-  return(resGO);
-}
-
-int
-cl_hc08::inst_swi(t_mem code, bool prefix)
-{
-  push2(PC);
-  tick(2);
-  push1(regs.X);
-  tick(1);
-  push1(regs.A);
-  tick(1);
-  push1(regs.P);
-  tick(1);
-  FLAG_CLEAR(BIT_I);
-
-  PC = get2(0xfffc);
-  tick(2);
-  tick(3);
-
-  return(resGO);
-}
-
-
-/* End of hc08.src/inst.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/hc08.src/instcl.h sdcc-4.2.0+dfsg/sim/ucsim/hc08.src/instcl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/hc08.src/instcl.h	2011-10-01 07:46:51.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/hc08.src/instcl.h	1970-01-01 00:00:00.000000000 +0000
@@ -1,62 +0,0 @@
-/* hc08.src/instcl.h */
-
-  virtual void incx(void);
-  virtual int fetchea(t_mem code, bool prefix);
-  virtual int fetch2(void);
-  virtual int inst_nop(t_mem code, bool prefix);
-  virtual int inst_transfer(t_mem code, bool prefix);
-  virtual int inst_setclearflags(t_mem code, bool prefix);
-  virtual int inst_rsp(t_mem code, bool prefix);
-  virtual int inst_nsa(t_mem code, bool prefix);
-  virtual int inst_lda(t_mem code, bool prefix);
-  virtual int inst_ldx(t_mem code, bool prefix);
-  virtual int inst_sta(t_mem code, bool prefix);
-  virtual int inst_stx(t_mem code, bool prefix);
-  virtual int inst_add(t_mem code, bool prefix);
-  virtual int inst_adc(t_mem code, bool prefix);
-  virtual int inst_sub(t_mem code, bool prefix);
-  virtual int inst_sbc(t_mem code, bool prefix);
-  virtual int inst_cmp(t_mem code, bool prefix);
-  virtual int inst_cpx(t_mem code, bool prefix);
-  virtual int inst_jmp(t_mem code, bool prefix);
-  virtual int inst_jsr(t_mem code, bool prefix);
-  virtual int inst_ais(t_mem code, bool prefix);
-  virtual int inst_aix(t_mem code, bool prefix);
-  virtual int inst_and(t_mem code, bool prefix);
-  virtual int inst_bit(t_mem code, bool prefix);
-  virtual int inst_ora(t_mem code, bool prefix);
-  virtual int inst_eor(t_mem code, bool prefix);
-  virtual int inst_asr(t_mem code, bool prefix);
-  virtual int inst_lsr(t_mem code, bool prefix);
-  virtual int inst_lsl(t_mem code, bool prefix);
-  virtual int inst_rol(t_mem code, bool prefix);
-  virtual int inst_ror(t_mem code, bool prefix);
-  virtual int inst_inc(t_mem code, bool prefix);
-  virtual int inst_dec(t_mem code, bool prefix);
-  virtual int inst_dbnz(t_mem code, bool prefix);
-  virtual int inst_tst(t_mem code, bool prefix);
-  virtual int inst_clr(t_mem code, bool prefix);
-  virtual int inst_clrh(t_mem code, bool prefix);
-  virtual int inst_com(t_mem code, bool prefix);
-  virtual int inst_neg(t_mem code, bool prefix);
-  virtual int inst_pushpull(t_mem code, bool prefix);
-  virtual int inst_stop(t_mem code, bool prefix);
-  virtual int inst_wait(t_mem code, bool prefix);
-  virtual int inst_daa(t_mem code, bool prefix);
-  virtual int inst_mul(t_mem code, bool prefix);
-  virtual int inst_div(t_mem code, bool prefix);
-  virtual int inst_condbranch(t_mem code, bool prefix);
-  virtual int inst_bitsetclear(t_mem code, bool prefix);
-  virtual int inst_bittestsetclear(t_mem code, bool prefix);
-  virtual int inst_cbeq(t_mem code, bool prefix);
-  virtual int inst_rti(t_mem code, bool prefix);
-  virtual int inst_rts(t_mem code, bool prefix);
-  virtual int inst_mov(t_mem code, bool prefix);
-  virtual int inst_sthx(t_mem code, bool prefix);
-  virtual int inst_ldhx(t_mem code, bool prefix);
-  virtual int inst_cphx(t_mem code, bool prefix);
-  virtual int inst_swi(t_mem code, bool prefix);
-  virtual int inst_bsr(t_mem code, bool prefix);
-
-
-/* End of hc08.src/instcl.h */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/hc08.src/Makefile.in sdcc-4.2.0+dfsg/sim/ucsim/hc08.src/Makefile.in
--- sdcc-4.0.0+dfsg/sim/ucsim/hc08.src/Makefile.in	2017-03-12 13:28:55.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/hc08.src/Makefile.in	1970-01-01 00:00:00.000000000 +0000
@@ -1,163 +0,0 @@
-#
-# uCsim hc08.src/Makefile
-#
-# (c) Drotos Daniel, Talker Bt. 1997
-#
-
-STARTYEAR	= 1997
-
-SHELL		= /bin/sh
-CXX		= @CXX@
-CPP		= @CPP@
-CXXCPP		= @CXXCPP@
-RANLIB		= @RANLIB@
-INSTALL		= @INSTALL@
-STRIP		= @STRIP@
-MAKEDEP         = @MAKEDEP@
-
-top_builddir	= @top_builddir@
-top_srcdir	= @top_srcdir@
-
-transform	= @program_transform_name@
-
-DEFS            = $(subs -DHAVE_CONFIG_H,,@DEFS@)
-CPPFLAGS        = @CPPFLAGS@ -I$(srcdir) -I$(top_srcdir) -I$(top_builddir) \
-		  -I$(top_srcdir)/cmd.src -I$(top_srcdir)/sim.src \
-		  -I$(top_srcdir)/gui.src
-CFLAGS          = @CFLAGS@ @WALL_FLAG@
-CXXFLAGS        = @CXXFLAGS@ @WALL_FLAG@
-LDFLAGS         = @LDFLAGS@
-PICOPT		= @PICOPT@
-SHAREDLIB	= @SHAREDLIB@
-
-EXEEXT          = @EXEEXT@
-
-LIBS		= -L$(top_builddir) -lsim -lucsimutil -lguiucsim -lcmd -lsim @LIBS@
-DL		= @DL@
-dl_ok		= @dl_ok@
-
-prefix          = @prefix@
-exec_prefix     = @exec_prefix@
-bindir          = @bindir@
-libdir          = @libdir@
-datadir         = @datadir@
-datarootdir     = @datarootdir@
-includedir      = @includedir@
-mandir          = @mandir@
-man1dir         = $(mandir)/man1
-man2dir         = $(mandir)/man2
-infodir         = @infodir@
-srcdir          = @srcdir@
-VPATH           = @srcdir@
-
-OBJECTS_SHARED	= glob.o \
-		  inst.o \
-		  simhc08.o hc08.o
-OBJECTS_EXE	= shc08.o
-OBJECTS		= $(OBJECTS_SHARED) $(OBJECTS_EXE)
-
-HC08ASM		= 
-
-enable_dlso	= @enable_dlso@
-dlso_ok		= @dlso_ok@
-
-#TEST_OBJ	= test_bit.hex test_dis.hex test_mov.hex test_jmp.hex \
-#		  test_arith.hex
-
-# Compiling entire program or any subproject
-# ------------------------------------------
-all: checkconf otherlibs hc08.src tests
-
-tests: $(TEST_OBJ)
-
-
-# Compiling and installing everything and runing test
-# ---------------------------------------------------
-install: all installdirs
-	$(INSTALL) shc08$(EXEEXT) $(DESTDIR)$(bindir)/`echo shc08|sed '$(transform)'`$(EXEEXT)
-	$(STRIP) $(DESTDIR)$(bindir)/`echo shc08|sed '$(transform)'`$(EXEEXT)
-
-
-# Deleting all the installed files
-# --------------------------------
-uninstall:
-	rm -f $(DESTDIR)$(bindir)/`echo shc08|sed '$(transform)'`$(EXEEXT)
-
-
-# Performing self-test
-# --------------------
-check: test
-
-test:
-
-
-# Performing installation test
-# ----------------------------
-installcheck:
-
-
-# Creating installation directories
-# ---------------------------------
-installdirs:
-	test -d $(DESTDIR)$(bindir) || $(INSTALL) -d $(DESTDIR)$(bindir)
-
-
-# Creating dependencies
-# ---------------------
-dep: Makefile.dep
-
-Makefile.dep: $(srcdir)/*.cc $(srcdir)/*.h
-	$(MAKEDEP) $(CPPFLAGS) $(filter %.cc,$^) >Makefile.dep
-
--include Makefile.dep
-include $(srcdir)/clean.mk
-
-# My rules
-# --------
-.SUFFIXES: .asm .hex
-
-hc08.src: shc08$(EXEEXT)  shared_lib
-
-shc08$(EXEEXT): $(OBJECTS) $(top_builddir)/libcmd.a $(top_builddir)/libguiucsim.a $(top_builddir)/libsim.a $(top_builddir)/libucsimutil.a
-	$(CXX) $(CXXFLAGS) $(LDFLAGS) $(OBJECTS) $(LIBS) -o $@
-
-ifeq ($(dlso_ok),yes)
-shared_lib: $(top_builddir)/shc08.so
-else
-shared_lib:
-	@$(top_srcdir)/mkecho $(top_builddir) "No hc08 shared lib made."
-	@$(top_srcdir)/mkecho $(top_builddir) "(SHAREDLIB="$(SHAREDLIB)",dl_ok="$(dl_ok)",enable_dlso="$(enable_dlso)")"
-endif
-
-$(top_builddir)/shc08.so: $(OBJECTS_SHARED)
-	$(CXX) -shared $(LDFLAGS) $(OBJECTS_SHARED) -o $(top_builddir)/shc08.so
-
-otherlibs: $(top_builddir)/libcmd.a $(top_builddir)/libguiucsim.a $(top_builddir)/libsim.a $(top_builddir)/libucsimutil.a
-
-$(top_builddir)/libcmd.a:
-	$(MAKE) -C $(top_builddir)/cmd.src all
-
-$(top_builddir)/libguiucsim.a:
-	$(MAKE) -C $(top_builddir)/gui.src checkconf ucsim_lib
-
-$(top_builddir)/libsim.a:
-	$(MAKE) -C $(top_builddir)/sim.src all
-
-$(top_builddir)/libucsimutil.a:
-	$(MAKE) -C $(top_builddir) -f main.mk
-
-.cc.o:
-	$(CXX) $(CXXFLAGS) $(PICOPT) $(CPPFLAGS) $(TARGET_ARCH) -c $< -o $@
-
-.asm.hex:
-	$(HC08ASM) -l $< -o $@ -e $<.lst
-
-
-# Remaking configuration
-# ----------------------
-checkconf:
-	@if [ -f $(top_builddir)/devel ]; then\
-	  $(MAKE) -f conf.mk srcdir="$(srcdir)" top_builddir="$(top_builddir)" freshconf;\
-	fi
-
-# End of hc08.src/Makefile.in
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/hc08.src/regshc08.h sdcc-4.2.0+dfsg/sim/ucsim/hc08.src/regshc08.h
--- sdcc-4.0.0+dfsg/sim/ucsim/hc08.src/regshc08.h	2016-11-13 16:22:34.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/hc08.src/regshc08.h	1970-01-01 00:00:00.000000000 +0000
@@ -1,63 +0,0 @@
-/*
- * Simulator of microcontrollers (regsz80.h)
- *
- * some z80 code base from Karl Bongers karl@turbobit.com
- *
- * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
- * 
- * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
- *
- */
-
-/* This file is part of microcontroller simulator: ucsim.
-
-UCSIM is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2 of the License, or
-(at your option) any later version.
-
-UCSIM is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with UCSIM; see the file COPYING.  If not, write to the Free
-Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-02111-1307, USA. */
-/*@1@*/
-
-#ifndef REGHC08_HEADER
-#define REGHC08_HEADER
-
-#include "ddconfig.h"
-
-
-struct t_regs
-{
-  u8_t A;
-  u8_t P;
-  u8_t H;
-  u8_t X;
-  u16_t SP;
-  u8_t VECTOR;
-};
-
-#define BIT_C	0x01  // carry status(out of bit 7)
-#define BIT_Z	0x02  // zero status, 1=zero, 0=nonzero
-#define BIT_N	0x04  // sign, 1=negative, 0=positive (or zero)
-#define BIT_I	0x08  // interrupt mask, 1=disabled, 0=enabled
-#define BIT_H	0x10  // half carry status(out of bit 3)
-#define BIT_V	0x80  // signed overflow, 1=overflow
-#define BIT_ALL	(BIT_C |BIT_Z |BIT_N |BIT_I |BIT_H |BIT_V)  // all bits
-
-#define BITPOS_C 0    // 1
-#define BITPOS_Z 1    // 2H
-#define BITPOS_N 2    // 4H
-#define BITPOS_I 3    // 8H
-#define BITPOS_H 4    // 10H
-#define BITPOS_V 7    // 80H
-
-#endif
-
-/* End of hc08.src/regshc08.h */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/hc08.src/shc08.cc sdcc-4.2.0+dfsg/sim/ucsim/hc08.src/shc08.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/hc08.src/shc08.cc	2019-03-14 11:32:41.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/hc08.src/shc08.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,57 +0,0 @@
-/*
- * Simulator of microcontrollers (shc08.cc)
- *
- * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
- * 
- * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
- *
- */
-
-/* This file is part of microcontroller simulator: ucsim.
-
-UCSIM is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2 of the License, or
-(at your option) any later version.
-
-UCSIM is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with UCSIM; see the file COPYING.  If not, write to the Free
-Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-02111-1307, USA. */
-/*@1@*/
-
-// prj
-#include "globals.h"
-
-// sim.src
-#include "appcl.h"
-
-// local
-#include "simhc08cl.h"
-
-
-int
-main(int argc, char *argv[])
-{
-  class cl_sim *sim;
-
-  cpus= cpus_hc08;
-  application= new cl_app();
-  application->init(argc, argv);
-  sim= new cl_simhc08(application);
-  if (sim->init())
-    sim->state|= SIM_QUIT;
-  application->set_simulator(sim);
-  application->run();
-  application->done();
-  delete application;
-  return(0);
-}
-
-
-/* End of hc08.src/shc08.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/hc08.src/simhc08.cc sdcc-4.2.0+dfsg/sim/ucsim/hc08.src/simhc08.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/hc08.src/simhc08.cc	2017-01-24 13:53:15.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/hc08.src/simhc08.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,75 +0,0 @@
-/*
- * Simulator of microcontrollers (simhc08.cc)
- *
- * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
- * 
- * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
- *
- */
-
-/* This file is part of microcontroller simulator: ucsim.
-
-UCSIM is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2 of the License, or
-(at your option) any later version.
-
-UCSIM is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with UCSIM; see the file COPYING.  If not, write to the Free
-Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-02111-1307, USA. */
-/*@1@*/
-
-#include "globals.h"
-
-// local
-#include "simhc08cl.h"
-#include "hc08cl.h"
-
-
-cl_simhc08::cl_simhc08(class cl_app *the_app):
-  cl_sim(the_app)
-{}
-
-class cl_uc *
-cl_simhc08::mk_controller(void)
-{
-  int i;
-  const char *typ= 0;
-  class cl_optref type_option(this);
-
-  type_option.init();
-  type_option.use("cpu_type");
-  i= 0;
-  if ((typ= type_option.get_value(typ)) == 0)
-    typ= "HC08";
-
-  while ((cpus_hc08[i].type_str != NULL) &&
-	 (strcmp(typ, cpus_hc08[i].type_str) != 0))
-    i++;
-  if (cpus_hc08[i].type_str == NULL)
-    {
-      fprintf(stderr, "Unknown processor type. "
-	      "Use -H option to see known types.\n");
-      return(NULL);
-    }
-
-  switch (cpus_hc08[i].type)
-    {
-    case CPU_HC08:
-    case CPU_HCS08:
-      return(new cl_hc08(&cpus_hc08[i], this));
-    default:
-      return NULL;
-    }
-
-  return(NULL);
-}
-
-
-/* End of hc08.src/simhc08.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/hc08.src/simhc08cl.h sdcc-4.2.0+dfsg/sim/ucsim/hc08.src/simhc08cl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/hc08.src/simhc08cl.h	2003-10-15 05:14:36.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/hc08.src/simhc08cl.h	1970-01-01 00:00:00.000000000 +0000
@@ -1,45 +0,0 @@
-/*
- * Simulator of microcontrollers (simhc08cl.h)
- *
- * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
- * 
- * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
- *
- */
-
-/* This file is part of microcontroller simulator: ucsim.
-
-UCSIM is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2 of the License, or
-(at your option) any later version.
-
-UCSIM is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with UCSIM; see the file COPYING.  If not, write to the Free
-Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-02111-1307, USA. */
-/*@1@*/
-
-#ifndef SIMHC08CL_HEADER
-#define SIMHC08CL_HEADER
-
-#include "simcl.h"
-
-
-class cl_simhc08: public cl_sim
-{
-public:
-  cl_simhc08(class cl_app *the_app);
-
-  virtual class cl_uc *mk_controller(void);
-};
-
-
-#endif
-
-/* End of hc08.src/simhc08cl.h */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/ltmain.sh sdcc-4.2.0+dfsg/sim/ucsim/ltmain.sh
--- sdcc-4.0.0+dfsg/sim/ucsim/ltmain.sh	2014-04-01 22:49:18.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/ltmain.sh	2022-01-27 21:35:29.000000000 +0000
@@ -4394,7 +4394,7 @@
         {
           /* however, if there is an option in the LTWRAPPER_OPTION_PREFIX
              namespace, but it is not one of the ones we know about and
-             have already dealt with, above (inluding dump-script), then
+             have already dealt with, above (including dump-script), then
              report an error. Otherwise, targets might begin to believe
              they are allowed to use options in the LTWRAPPER_OPTION_PREFIX
              namespace. The first time any user complains about this, we'll
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m6800.src/(c).1 sdcc-4.2.0+dfsg/sim/ucsim/m6800.src/(c).1
--- sdcc-4.0.0+dfsg/sim/ucsim/m6800.src/(c).1	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m6800.src/(c).1	2021-04-16 22:21:27.000000000 +0000
@@ -0,0 +1,25 @@
+/*
+ * Simulator of microcontrollers (@@F@@)
+ *
+ * Copyright (C) @@S@@,@@Y@@ Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m6800.src/clean.mk sdcc-4.2.0+dfsg/sim/ucsim/m6800.src/clean.mk
--- sdcc-4.0.0+dfsg/sim/ucsim/m6800.src/clean.mk	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m6800.src/clean.mk	2021-10-03 12:24:27.000000000 +0000
@@ -0,0 +1,34 @@
+# m6800.src/clean.mk
+
+# Deleting all files created by building the program
+# --------------------------------------------------
+clean:
+	rm -f *core *[%~] *.[oa] *.map
+	rm -f .[a-z]*~
+	rm -f sm6800$(EXEEXT) sm6800.exe
+	rm -f sm68hc11$(EXEEXT) sm68hc11.exe
+	rm -f ucsim_m6800$(EXEEXT) ucsim_m6800.exe
+	rm -f ucsim_m68hc11$(EXEEXT) ucsim_m68hc11.exe
+	$(MAKE) -C test -f clean.mk clean
+
+
+# Deleting all files created by configuring or building the program
+# -----------------------------------------------------------------
+distclean: clean
+	rm -f config.cache config.log config.status
+	rm -f Makefile *.dep
+	rm -f *.obj *.list *.lst *.hex
+	$(MAKE) -C test -f clean.mk distclean
+
+
+# Like clean but some files may still exist
+# -----------------------------------------
+mostlyclean: clean
+
+
+# Deleting everything that can reconstructed by this Makefile. It deletes
+# everything deleted by distclean plus files created by bison, etc.
+# -----------------------------------------------------------------------
+realclean: distclean
+
+# End of m6800.src/clean.mk
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m6800.src/conf.mk sdcc-4.2.0+dfsg/sim/ucsim/m6800.src/conf.mk
--- sdcc-4.0.0+dfsg/sim/ucsim/m6800.src/conf.mk	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m6800.src/conf.mk	2021-04-16 22:21:27.000000000 +0000
@@ -0,0 +1,11 @@
+# m6800.src/conf.mk
+#
+# Makefile targets to remake configuration
+#
+
+freshconf: Makefile
+
+Makefile: $(srcdir)/Makefile.in $(top_srcdir)/configure.ac
+	cd $(top_builddir) && $(SHELL) ./config.status
+
+# End of m6800.src/conf.mk
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m6800.src/decode.h sdcc-4.2.0+dfsg/sim/ucsim/m6800.src/decode.h
--- sdcc-4.0.0+dfsg/sim/ucsim/m6800.src/decode.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m6800.src/decode.h	2021-06-03 10:04:45.000000000 +0000
@@ -0,0 +1,247 @@
+/*
+ * Simulator of microcontrollers (decode.h)
+ *
+ * Copyright (C) 2020,20 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef DECODE_HEADER
+#define DECODE_HEADER
+
+#define NOP   instruction_01
+#define TAP   instruction_06
+#define TPA   instruction_07
+#define INX   instruction_08
+#define DEX   instruction_09
+#define CLV   instruction_0a
+#define SEV   instruction_0b
+#define CLC   instruction_0c
+#define SEc   instruction_0d
+#define CLI   instruction_0e
+#define SEI   instruction_0f
+
+#define SBA   instruction_10
+#define CBA   instruction_11
+#define TAB   instruction_16
+#define TBA   instruction_17
+#define DAA   instruction_19
+#define ABA   instruction_1b
+
+#define BRA   instruction_20
+#define BHI   instruction_22
+#define BLS   instruction_23
+#define BCC   instruction_24
+#define BCS   instruction_25
+#define BNE   instruction_26
+#define BEQ   instruction_27
+#define BVC   instruction_28
+#define BVS   instruction_29
+#define BPL   instruction_2a
+#define BMI   instruction_2b
+#define BGE   instruction_2c
+#define BLT   instruction_2d
+#define BGT   instruction_2e
+#define BLE   instruction_2f
+
+#define TSX   instruction_30
+#define INS   instruction_31
+#define PULA  instruction_32
+#define PULB  instruction_33
+#define DES   instruction_34
+#define TXS   instruction_35
+#define PSHA  instruction_36
+#define PSHB  instruction_37
+#define RTS   instruction_39
+
+#define RTI   instruction_3b
+#define WAI   instruction_3e
+#define SWI   instruction_3f
+
+#define NEGA  instruction_40
+#define COMA  instruction_43
+#define LSRA  instruction_44
+#define RORA  instruction_46
+#define ASRA  instruction_47
+#define ASLA  instruction_48
+#define ROLA  instruction_49
+#define DECA  instruction_4a
+#define INCA  instruction_4c
+#define TSTA  instruction_4d
+#define CLRA  instruction_4f
+
+#define NEGB  instruction_50
+#define COMB  instruction_53
+#define LSRB  instruction_54
+#define RORB  instruction_56
+#define ASRB  instruction_57
+#define ASLB  instruction_58
+#define ROLB  instruction_59
+#define DECB  instruction_5a
+#define INCB  instruction_5c
+#define TSTB  instruction_5d
+#define CLRB  instruction_5f
+
+#define NEGi  instruction_60
+#define COMi  instruction_63
+#define LSRi  instruction_64
+#define RORi  instruction_66
+#define ASRi  instruction_67
+#define ASLi  instruction_68
+#define ROLi  instruction_69
+#define DECi  instruction_6a
+#define INCi  instruction_6c
+#define TSTi  instruction_6d
+#define JMPi  instruction_6e
+#define CLRi  instruction_6f
+
+#define NEGe  instruction_70
+#define COMe  instruction_73
+#define LSRe  instruction_74
+#define RORe  instruction_76
+#define ASRe  instruction_77
+#define ASLe  instruction_78
+#define ROLe  instruction_79
+#define DECe  instruction_7a
+#define INCe  instruction_7c
+#define TSTe  instruction_7d
+#define JMPe  instruction_7e
+#define CLRe  instruction_7f
+
+#define SUBA8 instruction_80
+#define CMPA8 instruction_81
+#define SBCA8 instruction_82
+#define ANDA8 instruction_84
+#define BITA8 instruction_85
+#define LDAA8 instruction_86
+#define EORA8 instruction_88
+#define ADCA8 instruction_89
+#define ORAA8 instruction_8a
+#define ADDA8 instruction_8b
+#define CPX16 instruction_8c
+#define BSR   instruction_8d
+#define LDS16 instruction_8e
+
+#define SUBAd instruction_90
+#define CMPAd instruction_91
+#define SBCAd instruction_92
+#define ANDAd instruction_94
+#define BITAd instruction_95
+#define LDAAd instruction_96
+#define STAAd instruction_97
+#define EORAd instruction_98
+#define ADCAd instruction_99
+#define ORAAd instruction_9a
+#define ADDAd instruction_9b
+#define CPXd  instruction_9c
+#define LDSd  instruction_9e
+#define STSd  instruction_9f
+
+#define SUBAi instruction_a0
+#define CMPAi instruction_a1
+#define SBCAi instruction_a2
+#define ANDAi instruction_a4
+#define BITAi instruction_a5
+#define LDAAi instruction_a6
+#define STAAi instruction_a7
+#define EORAi instruction_a8
+#define ADCAi instruction_a9
+#define ORAAi instruction_aa
+#define ADDAi instruction_ab
+#define CPXi  instruction_ac
+#define JSRi  instruction_ad
+#define LDSi  instruction_ae
+#define STSi  instruction_af
+
+#define SUBAe instruction_b0
+#define CMPAe instruction_b1
+#define SBCAe instruction_b2
+#define ANDAe instruction_b4
+#define BITAe instruction_b5
+#define LDAAe instruction_b6
+#define STAAe instruction_b7
+#define EORAe instruction_b8
+#define ADCAe instruction_b9
+#define ORAAe instruction_ba
+#define ADDAe instruction_bb
+#define CPXe  instruction_bc
+#define JSRe  instruction_bd
+#define LDSe  instruction_be
+#define STSe  instruction_bf
+
+#define SUBB8 instruction_c0
+#define CMPB8 instruction_c1
+#define SBCB8 instruction_c2
+#define ANDB8 instruction_c4
+#define BITB8 instruction_c5
+#define LDAB8 instruction_c6
+#define EORB8 instruction_c8
+#define ADCB8 instruction_c9
+#define ORAB8 instruction_ca
+#define ADDB8 instruction_cb
+#define LDX16 instruction_ce
+
+#define SUBBd instruction_d0
+#define CMPBd instruction_d1
+#define SBCBd instruction_d2
+#define ANDBd instruction_d4
+#define BITBd instruction_d5
+#define LDABd instruction_d6
+#define STABd instruction_d7
+#define EORBd instruction_d8
+#define ADCBd instruction_d9
+#define ORABd instruction_da
+#define ADDBd instruction_db
+#define LDXd  instruction_de
+#define STXd  instruction_df
+
+#define SUBBi instruction_e0
+#define CMPBi instruction_e1
+#define SBCBi instruction_e2
+#define ANDBi instruction_e4
+#define BITBi instruction_e5
+#define LDABi instruction_e6
+#define STABi instruction_e7
+#define EORBi instruction_e8
+#define ADCBi instruction_e9
+#define ORABi instruction_ea
+#define ADDBi instruction_eb
+#define LDXi  instruction_ee
+#define STXi  instruction_ef
+
+#define SUBBe instruction_f0
+#define CMPBe instruction_f1
+#define SBCBe instruction_f2
+#define ANDBe instruction_f4
+#define BITBe instruction_f5
+#define LDABe instruction_f6
+#define STABe instruction_f7
+#define EORBe instruction_f8
+#define ADCBe instruction_f9
+#define ORABe instruction_fa
+#define ADDBe instruction_fb
+#define LDXe  instruction_fe
+#define STXe  instruction_ff
+
+#endif
+
+/* End of m6800.src/decode.h */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m6800.src/glob.cc sdcc-4.2.0+dfsg/sim/ucsim/m6800.src/glob.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/m6800.src/glob.cc	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m6800.src/glob.cc	2021-10-29 17:39:15.000000000 +0000
@@ -0,0 +1,251 @@
+/*
+ * Simulator of microcontrollers (glob.cc)
+ *
+ * Copyright (C) 2020,20 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#include "glob.h"
+
+
+// code mask branch len mn call tick
+struct dis_entry disass_m6800[]=
+  {
+    { 0x01, 0xff, ' ', 1, "NOP" },
+    { 0x06, 0xff, ' ', 1, "TAP" },
+    { 0x07, 0xff, ' ', 1, "TAP" },
+    { 0x08, 0xff, ' ', 1, "INX" },
+    { 0x09, 0xff, ' ', 1, "DEX" },
+    { 0x0a, 0xff, ' ', 1, "CLV" },
+    { 0x0b, 0xff, ' ', 1, "SEV" },
+    { 0x0c, 0xff, ' ', 1, "CLC" },
+    { 0x0d, 0xff, ' ', 1, "SEC" },
+    { 0x0e, 0xff, ' ', 1, "CLI" },
+    { 0x0f, 0xff, ' ', 1, "SEI" },
+
+    { 0x10, 0xff, ' ', 1, "SBA" },
+    { 0x11, 0xff, ' ', 1, "CBA" },
+    { 0x16, 0xff, ' ', 1, "TAB" },
+    { 0x17, 0xff, ' ', 1, "TBA" },
+    { 0x19, 0xff, ' ', 1, "DAA" },
+    { 0x1b, 0xff, ' ', 1, "ABA" },
+
+    { 0x20, 0xff, 'r', 2, "BRA %r" },
+    { 0x22, 0xff, 'R', 2, "BHI %r" },
+    { 0x23, 0xff, 'R', 2, "BLS %r" },
+    { 0x24, 0xff, 'R', 2, "BCC %r" },
+    { 0x25, 0xff, 'R', 2, "BCS %r" },
+    { 0x26, 0xff, 'R', 2, "BNE %r" },
+    { 0x27, 0xff, 'R', 2, "BEQ %r" },
+    { 0x28, 0xff, 'R', 2, "BVC %r" },
+    { 0x29, 0xff, 'R', 2, "BVS %r" },
+    { 0x2a, 0xff, 'R', 2, "BPL %r" },
+    { 0x2b, 0xff, 'R', 2, "BMI %r" },
+    { 0x2c, 0xff, 'R', 2, "BGE %r" },
+    { 0x2d, 0xff, 'R', 2, "BLT %r" },
+    { 0x2e, 0xff, 'R', 2, "BGT %r" },
+    { 0x2f, 0xff, 'R', 2, "BLE %r" },
+
+    { 0x30, 0xff, ' ', 1, "TSX" },
+    { 0x31, 0xff, ' ', 1, "INS" },
+    { 0x32, 0xff, ' ', 1, "PUL A" },
+    { 0x33, 0xff, ' ', 1, "PUL B" },
+    { 0x34, 0xff, ' ', 1, "DES" },
+    { 0x35, 0xff, ' ', 1, "TXS" },
+    { 0x36, 0xff, ' ', 1, "PSH A" },
+    { 0x37, 0xff, ' ', 1, "PSH B" },
+    { 0x39, 0xff, '_', 1, "RTS" },
+
+    { 0x3b, 0xff, '_', 1, "RTI" },
+    { 0x3e, 0xff, ' ', 1, "WAI" },
+    { 0x3f, 0xff, 's', 1, "SWI" },
+
+    { 0x40, 0xff, ' ', 1, "NEG A" },
+    { 0x43, 0xff, ' ', 1, "COM A" },
+    { 0x44, 0xff, ' ', 1, "LSR A" },
+    { 0x46, 0xff, ' ', 1, "ROR A" },
+    { 0x47, 0xff, ' ', 1, "ASR A" },
+    { 0x48, 0xff, ' ', 1, "ASL A" },
+    { 0x49, 0xff, ' ', 1, "ROL A" },
+    { 0x4a, 0xff, ' ', 1, "DEC A" },
+    { 0x4c, 0xff, ' ', 1, "INC A" },
+    { 0x4d, 0xff, ' ', 1, "TST A" },
+    { 0x4f, 0xff, ' ', 1, "CLR A" },
+    
+    { 0x50, 0xff, ' ', 1, "NEG B" },
+    { 0x53, 0xff, ' ', 1, "COM B" },
+    { 0x54, 0xff, ' ', 1, "LSR B" },
+    { 0x56, 0xff, ' ', 1, "ROR B" },
+    { 0x57, 0xff, ' ', 1, "ASR B" },
+    { 0x58, 0xff, ' ', 1, "ASL B" },
+    { 0x59, 0xff, ' ', 1, "ROL B" },
+    { 0x5a, 0xff, ' ', 1, "DEC B" },
+    { 0x5c, 0xff, ' ', 1, "INC B" },
+    { 0x5d, 0xff, ' ', 1, "TST B" },
+    { 0x5f, 0xff, ' ', 1, "CLR B" },
+    
+    { 0x60, 0xff, ' ', 2, "NEG %x" },
+    { 0x63, 0xff, ' ', 2, "COM %x" },
+    { 0x64, 0xff, ' ', 2, "LSR %x" },
+    { 0x66, 0xff, ' ', 2, "ROR %x" },
+    { 0x67, 0xff, ' ', 2, "ASR %x" },
+    { 0x68, 0xff, ' ', 2, "ASL %x" },
+    { 0x69, 0xff, ' ', 2, "ROL %x" },
+    { 0x6a, 0xff, ' ', 2, "DEC %x" },
+    { 0x6c, 0xff, ' ', 2, "INC %x" },
+    { 0x6d, 0xff, ' ', 2, "TST %x" },
+    { 0x6e, 0xff, '_', 2, "JMP %x" },
+    { 0x6f, 0xff, ' ', 2, "CLR %x" },
+    
+    { 0x70, 0xff, ' ', 3, "NEG %e" },
+    { 0x73, 0xff, ' ', 3, "COM %e" },
+    { 0x74, 0xff, ' ', 3, "LSR %e" },
+    { 0x76, 0xff, ' ', 3, "ROR %e" },
+    { 0x77, 0xff, ' ', 3, "ASR %e" },
+    { 0x78, 0xff, ' ', 3, "ASL %e" },
+    { 0x79, 0xff, ' ', 3, "ROL %e" },
+    { 0x7a, 0xff, ' ', 3, "DEC %e" },
+    { 0x7c, 0xff, ' ', 3, "INC %e" },
+    { 0x7d, 0xff, ' ', 3, "TST %e" },
+    { 0x7e, 0xff, 'e', 3, "JMP %e" },
+    { 0x7f, 0xff, ' ', 3, "CLR %e" },
+    
+    { 0x80, 0xff, ' ', 2, "SUB A,%b" },
+    { 0x81, 0xff, ' ', 2, "CMP A,%b" },
+    { 0x82, 0xff, ' ', 2, "SBC A,%b" },
+    { 0x84, 0xff, ' ', 2, "AND A,%b" },
+    { 0x85, 0xff, ' ', 2, "BIT A,%b" },
+    { 0x86, 0xff, ' ', 2, "LDA A,%b" },
+    { 0x88, 0xff, ' ', 2, "EOR A,%b" },
+    { 0x89, 0xff, ' ', 2, "ADC A,%b" },
+    { 0x8a, 0xff, ' ', 2, "ORA A,%b" },
+    { 0x8b, 0xff, ' ', 2, "ADD A,%b" },
+    { 0x8c, 0xff, ' ', 3, "CPX %B" },
+    { 0x8d, 0xff, ' ', 2, "BSR %r" },
+    { 0x8e, 0xff, ' ', 3, "LDS %B" },
+
+    { 0x90, 0xff, ' ', 2, "SUB A,%d" },
+    { 0x91, 0xff, ' ', 2, "CMP A,%d" },
+    { 0x92, 0xff, ' ', 2, "SBC A,%d" },
+    { 0x94, 0xff, ' ', 2, "AND A,%d" },
+    { 0x95, 0xff, ' ', 2, "BIT A,%d" },
+    { 0x96, 0xff, ' ', 2, "LDA A,%d" },
+    { 0x97, 0xff, ' ', 2, "STA A,%d" },
+    { 0x98, 0xff, ' ', 2, "EOR A,%d" },
+    { 0x99, 0xff, ' ', 2, "ADC A,%d" },
+    { 0x9a, 0xff, ' ', 2, "ORA A,%d" },
+    { 0x9b, 0xff, ' ', 2, "ADD A,%d" },
+    { 0x9c, 0xff, ' ', 2, "CPX %D" },
+    { 0x9e, 0xff, ' ', 2, "LDS %d" },
+    { 0x9f, 0xff, ' ', 2, "STS %d" },
+
+    { 0xa0, 0xff, ' ', 2, "SUB A,%x" },
+    { 0xa1, 0xff, ' ', 2, "CMP A,%x" },
+    { 0xa2, 0xff, ' ', 2, "SBC A,%x" },
+    { 0xa4, 0xff, ' ', 2, "AND A,%x" },
+    { 0xa5, 0xff, ' ', 2, "BIT A,%x" },
+    { 0xa6, 0xff, ' ', 2, "LDA A,%x" },
+    { 0xa7, 0xff, ' ', 2, "STA A,%x" },
+    { 0xa8, 0xff, ' ', 2, "EOR A,%x" },
+    { 0xa9, 0xff, ' ', 2, "ADC A,%x" },
+    { 0xaa, 0xff, ' ', 2, "ORA A,%x" },
+    { 0xab, 0xff, ' ', 2, "ADD A,%x" },
+    { 0xac, 0xff, ' ', 2, "CPX %X" },
+    { 0xad, 0xff, '_', 2, "JSR %X" },
+    { 0xae, 0xff, ' ', 2, "LDS %X" },
+    { 0xaf, 0xff, ' ', 2, "STS %X" },
+
+    { 0xb0, 0xff, ' ', 3, "SUB A,%e" },
+    { 0xb1, 0xff, ' ', 3, "CMP A,%e" },
+    { 0xb2, 0xff, ' ', 3, "SBC A,%e" },
+    { 0xb4, 0xff, ' ', 3, "AND A,%e" },
+    { 0xb5, 0xff, ' ', 3, "BIT A,%e" },
+    { 0xb6, 0xff, ' ', 3, "LDA A,%e" },
+    { 0xb7, 0xff, ' ', 3, "STA A,%e" },
+    { 0xb8, 0xff, ' ', 3, "EOR A,%e" },
+    { 0xb9, 0xff, ' ', 3, "ADC A,%e" },
+    { 0xba, 0xff, ' ', 3, "ORA A,%e" },
+    { 0xbb, 0xff, ' ', 3, "ADD A,%e" },
+    { 0xbc, 0xff, ' ', 3, "CPX %E" },
+    { 0xbd, 0xff, 'E', 3, "JSR %e" },
+    { 0xbe, 0xff, ' ', 3, "LDS %E" },
+    { 0xbf, 0xff, ' ', 3, "STS %E" },
+
+    { 0xc0, 0xff, ' ', 2, "SUB B,%b" },
+    { 0xc1, 0xff, ' ', 2, "CMP B,%b" },
+    { 0xc2, 0xff, ' ', 2, "SBC B,%b" },
+    { 0xc4, 0xff, ' ', 2, "AND B,%b" },
+    { 0xc5, 0xff, ' ', 2, "BIT B,%b" },
+    { 0xc6, 0xff, ' ', 2, "LDA B,%b" },
+    { 0xc8, 0xff, ' ', 2, "EOR B,%b" },
+    { 0xc9, 0xff, ' ', 2, "ADC B,%b" },
+    { 0xca, 0xff, ' ', 2, "ORA B,%b" },
+    { 0xcb, 0xff, ' ', 2, "ADD B,%b" },
+    { 0xce, 0xff, ' ', 3, "LDX %B" },
+
+    { 0xd0, 0xff, ' ', 2, "SUB B,%d" },
+    { 0xd1, 0xff, ' ', 2, "CMP B,%d" },
+    { 0xd2, 0xff, ' ', 2, "SBC B,%d" },
+    { 0xd4, 0xff, ' ', 2, "AND B,%d" },
+    { 0xd5, 0xff, ' ', 2, "BIT B,%d" },
+    { 0xd6, 0xff, ' ', 2, "LDA B,%d" },
+    { 0xd7, 0xff, ' ', 2, "STA B,%d" },
+    { 0xd8, 0xff, ' ', 2, "EOR B,%d" },
+    { 0xd9, 0xff, ' ', 2, "ADC B,%d" },
+    { 0xda, 0xff, ' ', 2, "ORA B,%d" },
+    { 0xdb, 0xff, ' ', 2, "ADD B,%d" },
+    { 0xde, 0xff, ' ', 2, "LDX %d" },
+    { 0xdf, 0xff, ' ', 2, "STX %d" },
+
+    { 0xe0, 0xff, ' ', 2, "SUB B,%x" },
+    { 0xe1, 0xff, ' ', 2, "CMP B,%x" },
+    { 0xe2, 0xff, ' ', 2, "SBC B,%x" },
+    { 0xe4, 0xff, ' ', 2, "AND B,%x" },
+    { 0xe5, 0xff, ' ', 2, "BIT B,%x" },
+    { 0xe6, 0xff, ' ', 2, "LDA B,%x" },
+    { 0xe7, 0xff, ' ', 2, "STA B,%x" },
+    { 0xe8, 0xff, ' ', 2, "EOR B,%x" },
+    { 0xe9, 0xff, ' ', 2, "ADC B,%x" },
+    { 0xea, 0xff, ' ', 2, "ORA B,%x" },
+    { 0xeb, 0xff, ' ', 2, "ADD B,%x" },
+    { 0xee, 0xff, ' ', 2, "LDX %x" },
+    { 0xef, 0xff, ' ', 2, "STX %x" },
+
+    { 0xf0, 0xff, ' ', 3, "SUB B,%e" },
+    { 0xf1, 0xff, ' ', 3, "CMP B,%e" },
+    { 0xf2, 0xff, ' ', 3, "SBC B,%e" },
+    { 0xf4, 0xff, ' ', 3, "AND B,%e" },
+    { 0xf5, 0xff, ' ', 3, "BIT B,%e" },
+    { 0xf6, 0xff, ' ', 3, "LDA B,%e" },
+    { 0xf7, 0xff, ' ', 3, "STA B,%e" },
+    { 0xf8, 0xff, ' ', 3, "EOR B,%e" },
+    { 0xf9, 0xff, ' ', 3, "ADC B,%e" },
+    { 0xfa, 0xff, ' ', 3, "ORA B,%e" },
+    { 0xfb, 0xff, ' ', 3, "ADD B,%e" },
+    { 0xfe, 0xff, ' ', 3, "LDX %e" },
+    { 0xff, 0xff, ' ', 3, "STX %e" },
+
+    { 0, 0, 0, 0, 0, 0 }
+  };
+
+/* End of m6800.src/glob.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m6800.src/glob.h sdcc-4.2.0+dfsg/sim/ucsim/m6800.src/glob.h
--- sdcc-4.0.0+dfsg/sim/ucsim/m6800.src/glob.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m6800.src/glob.h	2021-10-03 17:23:37.000000000 +0000
@@ -0,0 +1,39 @@
+/*
+ * Simulator of microcontrollers (glob.h)
+ *
+ * Copyright (C) 2020,20 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef GLOB_HEADER
+#define GLOB_HEADER
+
+#include "stypes.h"
+
+
+extern struct dis_entry disass_m6800[];
+
+
+#endif
+
+/* End of m6800.src/glob.h */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m6800.src/ialu.cc sdcc-4.2.0+dfsg/sim/ucsim/m6800.src/ialu.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/m6800.src/ialu.cc	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m6800.src/ialu.cc	2022-01-24 11:09:43.000000000 +0000
@@ -0,0 +1,437 @@
+/*
+ * Simulator of microcontrollers (ialu.cc)
+ *
+ * Copyright (C) @@S@@,@@Y@@ Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+
+#include "m6800cl.h"
+
+
+int
+cl_m6800::sub(class cl_memory_cell &dest, u8_t op, bool c)
+{
+  u8_t orgc= rF&flagC;
+  u8_t f= rF & ~(flagN|flagZ|flagV|flagC);
+  u8_t a= dest.read(), b= op, r;
+  u8_t a7, b7, r7, na7, nb7, nr7;
+  r= a-b;
+  if (c && orgc) r--;
+  a7= a&0x80; na7= a7^0x80;
+  b7= b&0x80; nb7= b7^0x80;
+  r7= r&0x80; nr7= r7^0x80;
+  if (r7) f|= flagN;
+  if (!r) f|= flagZ;
+  if ((a7&nb7&nr7) | (na7&b7&r7)) f|= flagV;
+  if ((na7&b7) | (b7&r7) | (r7&na7)) f|= flagC;
+  dest.W(r);
+  cCC.W(f);
+  return resGO;
+}
+
+int
+cl_m6800::sub(class cl_memory_cell &dest, u8_t op)
+{
+  return sub(dest, op, false);
+}
+
+int
+cl_m6800::sbc(class cl_memory_cell &dest, u8_t op)
+{
+  return sub(dest, op, true);
+}
+
+int
+cl_m6800::cmp(u8_t op1, u8_t op2)
+{
+  u8_t f= rF & ~(flagN|flagZ|flagV|flagC);
+  u8_t a= op1, b= op2, r;
+  u8_t a7, b7, r7, na7, nb7, nr7;
+  r= a-b;
+  a7= a&0x80; na7= a7^0x80;
+  b7= b&0x80; nb7= b7^0x80;
+  r7= r&0x80; nr7= r7^0x80;
+  if (r7) f|= flagN;
+  if (!r) f|= flagZ;
+  if ((a7&nb7&nr7) | (na7&b7&r7)) f|= flagV;
+  if ((na7&b7) | (b7&r7) | (r7&na7)) f|= flagC;
+  cCC.W(f);
+  return resGO;
+}
+
+int
+cl_m6800::add(class cl_memory_cell &dest, u8_t op, bool c)
+{
+  u8_t orgc= rF&flagC;
+  u8_t f= rF & ~(flagN|flagZ|flagV|flagC|flagH);
+  u8_t a= dest.read(), b= op, r;
+  u8_t a7, b7, r7, na7, nb7, nr7;
+  r= a+b;
+  if (c && orgc) r++;
+  a7= a&0x80; na7= a7^0x80;
+  b7= b&0x80; nb7= b7^0x80;
+  r7= r&0x80; nr7= r7^0x80;
+  if ((a&0xf) + (b&0xf) > 0xf) f|= flagH;
+  if (r7) f|= flagN;
+  if (!r) f|= flagZ;
+  if ((a7&b7&nr7) | (na7&nb7&r7)) f|= flagV;
+  if ((a7&b7) | (b7&nr7) | (nr7&a7)) f|= flagC;
+  dest.W(r);
+  cCC.W(f);
+  return resGO;
+}
+
+int
+cl_m6800::add(class cl_memory_cell &dest, u8_t op)
+{
+  return add(dest, op, false);
+}
+
+int
+cl_m6800::adc(class cl_memory_cell &dest, u8_t op)
+{
+  return add(dest, op, true);
+}
+
+int
+cl_m6800::neg(class cl_memory_cell &dest)
+{
+  i8_t op= dest.R();
+  u8_t f= rF & ~(flagN|flagZ|flagV|flagC);
+  op= -op;
+  dest.W(op);
+  if (op&0x80) f|= flagN;
+  if (!op) f|= flagZ; else f|= flagC;
+  if ((u8_t)op == 0x80) f|= flagV;
+  cCC.W(f);
+  return resGO;
+}
+
+int
+cl_m6800::com(class cl_memory_cell &dest)
+{
+  u8_t op= dest.R(), f= rF & ~(flagN|flagZ|flagV);
+  op= ~op;
+  dest.W(op);
+  f|= flagC;
+  if (!op) f|= flagZ;
+  if (op&0x80) f|= flagN;
+  cCC.W(f);
+  return resGO;
+}
+
+// cc_out[VBIT] = left[0];
+int
+cl_m6800::lsr(class cl_memory_cell &dest)
+{
+  u8_t op= dest.R(), f= rF & ~(flagN|flagZ|flagV|flagC);
+  if (op&1) f|= flagC|flagV;
+  op>>= 1;
+  dest.W(op);
+  if (!op) f|= flagZ;
+  cCC.W(f);
+  return resGO;
+}
+
+// cc_out[VBIT] = left[0] ^ cc[CBIT];
+int
+cl_m6800::ror(class cl_memory_cell &dest)
+{
+  u8_t op= dest.R(), f, c= rF&flagC;
+  f= rF & ~(flagN|flagZ|flagV|flagC);
+  if (op&1) f|= flagC;
+  op>>= 1;
+  if (c) op|= 0x80;
+  dest.W(op);
+  if (!op) f|= flagZ;
+  if (op&0x80) f|= flagN;
+  //if (((f&flagN)?1:0) ^ ((f&flagC)?1:0)) f|= flagV;
+  if ((f&flagC) ^ c) f|= flagV;
+  cCC.W(f);
+  return resGO;
+}
+
+// cc_out[VBIT] = left[0] ^ left[7];
+int
+cl_m6800::asr(class cl_memory_cell &dest)
+{
+  i8_t op= dest.R();
+  u8_t f;
+  f= rF & ~(flagN|flagZ|flagV|flagC);
+  if (op&1) f|= flagC;
+  op>>= 1;
+  dest.W(op);
+  if (!op) f|= flagZ;
+  if (op&0x80) f|= flagN;
+  if (((f&flagN)?1:0) ^ ((f&flagC)?1:0)) f|= flagV;
+  cCC.W(f);
+  return resGO;
+}
+
+// cc_out[VBIT] = left[7] ^ left[6];
+int
+cl_m6800::asl(class cl_memory_cell &dest)
+{
+  i8_t op= dest.R();
+  u8_t f;
+  f= rF & ~(flagN|flagZ|flagV|flagC);
+  if (op&0x80) f|= flagC;
+  op<<= 1;
+  dest.W(op);
+  if (!op) f|= flagZ;
+  if (op&0x80) f|= flagN;
+  if (((f&flagN)?1:0) ^ ((f&flagC)?1:0)) f|= flagV;
+  cCC.W(f);
+  return resGO;
+}
+
+// cc_out[VBIT] = left[7] ^ left[6];
+int
+cl_m6800::rol(class cl_memory_cell &dest)
+{
+  u8_t op= dest.R(), f, c= rF&flagC;
+  f= rF & ~(flagN|flagZ|flagV|flagC);
+  if (op&0x80) f|= flagC;
+  op<<= 1;
+  if (c) op|= 1;
+  dest.W(op);
+  if (!op) f|= flagZ;
+  if (op&0x80) f|= flagN;
+  if (((f&flagN)?1:0) ^ ((f&flagC)?1:0)) f|= flagV;
+  cCC.W(f);
+  return resGO;
+}
+
+int
+cl_m6800::dec(class cl_memory_cell &dest)
+{
+  u8_t op= dest.R(), f= rF & ~(flagN|flagZ|flagV);
+  op--;
+  dest.W(op);
+  if (op==0x7f) f|= flagV;
+  if (!op) f|= flagZ;
+  if (op&0x80) f|= flagN;
+  cCC.W(f);
+  return resGO;
+}
+
+int
+cl_m6800::inc(class cl_memory_cell &dest)
+{
+  u8_t op= dest.R(), f= rF & ~(flagN|flagZ|flagV);
+  op++;
+  dest.W(op);
+  if (op==0x80) f|= flagV;
+  if (!op) f|= flagZ;
+  if (op&0x80) f|= flagN;
+  cCC.W(f);
+  return resGO;
+}
+
+int
+cl_m6800::tst(u8_t op)
+{
+  u8_t f= rF & ~(flagN|flagZ|flagV|flagC);
+  if (!op) f|= flagZ;
+  if (op&0x80) f|= flagN;
+  cCC.W(f);
+  return resGO;
+}
+
+int
+cl_m6800::And(class cl_memory_cell &dest, u8_t op)
+{
+  u8_t a= dest.R(), f= rF & ~(flagV|flagN|flagZ);
+  a&= op;
+  if (!a) f|= flagZ;
+  if (a&0x80) f|= flagN;
+  dest.W(a);
+  cCC.W(f);
+  return resGO;
+}
+
+int
+cl_m6800::bit(u8_t op1, u8_t op2)
+{
+  u8_t a= op1, f= rF & ~(flagV|flagN|flagZ);
+  a&= op2;
+  if (!a) f|= flagZ;
+  if (a&0x80) f|= flagN;
+  cCC.W(f);
+  return resGO;
+}
+
+int
+cl_m6800::eor(class cl_memory_cell &dest, u8_t op)
+{
+  u8_t a= dest.R(), f= rF & ~(flagV|flagN|flagZ);
+  a^= op;
+  if (!a) f|= flagZ;
+  if (a&0x80) f|= flagN;
+  dest.W(a);
+  cCC.W(f);
+  return resGO;
+}
+
+int
+cl_m6800::Or(class cl_memory_cell &dest, u8_t op)
+{
+  u8_t a= dest.R(), f= rF & ~(flagV|flagN|flagZ);
+  a|= op;
+  if (!a) f|= flagZ;
+  if (a&0x80) f|= flagN;
+  dest.W(a);
+  cCC.W(f);
+  return resGO;
+}
+
+int
+cl_m6800::cpx(u16_t op)
+{
+  u32_t r;
+  u16_t x= rX, r2;
+  u8_t f= rF & ~(flagN|flagZ|flagV);
+  op= ~op+1;
+  r= x+op;
+  r2= (x&0x7fff) + (op&0x7fff);
+  if (r&0x8000) f|= flagN;
+  if (!(r&0xffff)) f|= flagZ;
+  r &= ~0xffff;
+  r2&= ~0x7fff;
+  if ((r && !r2) ||
+      (!r && r2)) f|= flagV;
+  cCC.W(f);
+  return resGO;
+}
+
+int
+cl_m6800::INX(t_mem code)
+{
+  if (++rIX)
+    rF&= ~mZ;
+  else
+    rF|= mZ;
+  cX.W(rX);
+  cF.W(rF);
+  return resGO;
+}
+
+int
+cl_m6800::DEX(t_mem code)
+{
+  if (--rIX)
+    rF&= ~mZ;
+  else
+    rF|= mZ;
+  cX.W(rX);
+  cF.W(rF);
+  return resGO;
+}
+
+int
+cl_m6800::CLV(t_mem code)
+{
+  rF&= ~mV;
+  return resGO;
+}
+
+int
+cl_m6800::SEV(t_mem code)
+{
+  rF|= mV;
+  return resGO;
+}
+
+int
+cl_m6800::CLC(t_mem code)
+{
+  rF&= ~mC;
+  return resGO;
+}
+
+int
+cl_m6800::SEc(t_mem code)
+{
+  rF|= mC;
+  return resGO;
+}
+
+int
+cl_m6800::CLI(t_mem code)
+{
+  rF&= ~mI;
+  return resGO;
+}
+
+int
+cl_m6800::SEI(t_mem code)
+{
+  rF|= mI;
+  return resGO;
+}
+
+int
+cl_m6800::DAA(t_mem code)
+{
+  int i;
+  if ((rA & 0xf) > 9 ||
+      (rF & flagH))
+    {
+      i= rA+6;
+      if (i > 255)
+	rF|= flagC;
+      rA= i;
+    }
+  if ((rA & 0xf0) > 0x90 ||
+      (rF & flagC))
+    {
+      i= rA + 0x90;
+      if (i > 255)
+	rF|= flagC;
+      rA= i;
+    }
+  rF&= ~(flagZ|flagN);
+  if (rA&0x80)
+    rF|= flagN;
+  if (!rA)
+    rF|= flagZ;
+  cF.W(rF);
+  cA.W(rA);
+  return resGO;
+}
+
+int
+cl_m6800::INS(t_mem code)
+{
+  cSP.W(rSP+1);
+  return resGO;
+}
+
+int
+cl_m6800::DES(t_mem code)
+{
+  cSP.W(rSP-1);
+  return resGO;
+}
+
+
+/* End of m6800.src/ialu.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m6800.src/ibranch.cc sdcc-4.2.0+dfsg/sim/ucsim/m6800.src/ibranch.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/m6800.src/ibranch.cc	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m6800.src/ibranch.cc	2021-10-03 12:24:27.000000000 +0000
@@ -0,0 +1,84 @@
+/*
+ * Simulator of microcontrollers (ibranch.cc)
+ *
+ * Copyright (C) @@S@@,@@Y@@ Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+
+#include "m6800cl.h"
+
+
+int
+cl_m6800::call(t_addr a)
+{
+  u8_t h= PC>>8, l= PC;
+  rom->write(rSP, l);
+  rSP--;
+  rom->write(rSP, h);
+  cSP.W(rSP-1);
+  PC= a;
+  vc.wr+= 2;
+  return resGO;
+}
+
+int
+cl_m6800::RTS(t_mem code)
+{
+  u8_t h, l;
+  rSP++;
+  h= rom->read(rSP);
+  cSP.W(rSP+1);
+  l= rom->read(rSP);
+  PC= h*256 + l;
+  vc.rd+= 2;
+  return resGO;
+}
+
+int
+cl_m6800::branch(t_addr a, bool cond)
+{
+  if (cond)
+    PC= a&0xffff;
+  return resGO;
+}
+
+int
+cl_m6800::JMPi(t_mem code)
+{
+  t_addr a= fetch();
+  a+= rX;
+  PC= a;
+  return resGO;
+}
+
+int
+cl_m6800::JMPe(t_mem code)
+{
+  u8_t h, l;
+  h= fetch();
+  l= fetch();
+  PC= h*256 + l;
+  return resGO;
+}
+
+
+/* End of m6800.src/ibranch.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m6800.src/imove.cc sdcc-4.2.0+dfsg/sim/ucsim/m6800.src/imove.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/m6800.src/imove.cc	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m6800.src/imove.cc	2021-10-29 17:39:15.000000000 +0000
@@ -0,0 +1,174 @@
+/*
+ * Simulator of microcontrollers (imove.cc)
+ *
+ * Copyright (C) @@S@@,@@Y@@ Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+
+#include "m6800cl.h"
+
+
+int
+cl_m6800::clr(class cl_memory_cell &dest)
+{
+  u8_t f= rF & ~(flagN|flagV|flagC);
+  dest.W(0);
+  f|= flagZ;
+  cCC.W(f);
+  return resGO;
+}
+
+int
+cl_m6800::lda(class cl_memory_cell &dest, u8_t op)
+{
+  u8_t f= rF & ~(flagN|flagV|flagC);
+  dest.W(op);
+  if (!op) f|= flagZ;
+  if (op&0x80) f|= flagN;
+  cCC.W(f);
+  return resGO;
+}
+
+int
+cl_m6800::sta(class cl_memory_cell &dest, u8_t op)
+{
+  u8_t f= rF & ~(flagN|flagV|flagC);
+  dest.W(op);
+  if (!op) f|= flagZ;
+  if (op&0x80) f|= flagN;
+  cCC.W(f);
+  return resGO;
+}
+
+int
+cl_m6800::ldsx(class cl_cell16 &dest, u16_t op)
+{
+  u8_t f= rF & ~(flagN|flagV|flagC);
+  dest.W(op);
+  if (!op) f|= flagZ;
+  if (op&0x8000) f|= flagN;
+  cCC.W(f);
+  return resGO;
+}
+
+int
+cl_m6800::stsx(t_addr a, u16_t op)
+{
+  u8_t f= rF & ~(flagN|flagV|flagC);
+  rom->write(a, op>>8);
+  rom->write(a+1, op&0xff);
+  vc.wr+= 2;
+  if (!op) f|= flagZ;
+  if (op&0x8000) f|= flagN;
+  cCC.W(f);
+  return resGO;
+}
+
+
+int
+cl_m6800::TAP(t_mem code)
+{
+  cF.W(rA);
+  return resGO;
+}
+
+int
+cl_m6800::TPA(t_mem code)
+{
+  cA.W(rF);
+  return resGO;
+}
+
+int
+cl_m6800::TAB(t_mem code)
+{
+  u8_t f= rCC & ~(flagN|flagZ|flagV);
+  cB.W(rA);
+  if (!rA) f|= flagZ;
+  if (rA&0x80) f|= flagN;
+  cCC.W(f);
+  return resGO;
+}
+
+int
+cl_m6800::TBA(t_mem code)
+{
+  u8_t f= rF & ~(flagN|flagZ|flagV);
+  cA.W(rB);
+  if (!rB) f|= flagZ;
+  if (rB&0x80) f|= flagN;
+  cF.W(f);
+  return resGO;
+}
+
+int
+cl_m6800::TSX(t_mem code)
+{
+  cIX.W(rSP+1);
+  return resGO;
+}
+
+int
+cl_m6800::PULA(t_mem code)
+{
+  cSP.W(rSP+1);
+  cA.W(rom->read(rSP));
+  vc.rd++;
+  return resGO;
+}
+
+int
+cl_m6800::PULB(t_mem code)
+{
+  cSP.W(rSP+1);
+  cB.W(rom->read(rSP));
+  vc.rd++;
+  return resGO;
+}
+
+int
+cl_m6800::TXS(t_mem code)
+{
+  cSP.W(rIX-1);
+  return resGO;
+}
+
+int
+cl_m6800::PSHA(t_mem code)
+{
+  rom->write(rSP, rA);
+  cSP.W(rSP-1);
+  vc.wr++;
+  return resGO;
+}
+
+int
+cl_m6800::PSHB(t_mem code)
+{
+  rom->write(rSP, rB);
+  cSP.W(rSP-1);
+  vc.wr++;
+  return resGO;
+}
+
+
+/* End of m6800.src/imove.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m6800.src/inst.cc sdcc-4.2.0+dfsg/sim/ucsim/m6800.src/inst.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/m6800.src/inst.cc	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m6800.src/inst.cc	2021-10-03 12:24:27.000000000 +0000
@@ -0,0 +1,59 @@
+/*
+ * Simulator of microcontrollers (inst.cc)
+ *
+ * Copyright (C) @@S@@,@@Y@@ Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+
+#include "m6800cl.h"
+
+int
+cl_m6800::NOP(t_mem code)
+{
+  return resGO;
+}
+
+int
+cl_m6800::RTI(t_mem code)
+{
+  pull_regs(true);
+  return resGO;
+}
+
+int
+cl_m6800::WAI(t_mem code)
+{
+  push_regs(true);
+  wai= true;
+  state= stIDLE;
+  return resGO;
+}
+
+int
+cl_m6800::SWI(t_mem code)
+{
+  src_swi->request();
+  return resGO;
+}
+
+
+/* End of m6800.src/inst.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m6800.src/irq.cc sdcc-4.2.0+dfsg/sim/ucsim/m6800.src/irq.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/m6800.src/irq.cc	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m6800.src/irq.cc	2021-05-20 07:49:29.000000000 +0000
@@ -0,0 +1,106 @@
+/*
+ * Simulator of microcontrollers (irq.cc)
+ *
+ * Copyright (C) @@S@@,@@Y@@ Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+
+#include "globals.h"
+#include "utils.h"
+
+#include "itsrccl.h"
+
+#include "irqcl.h"
+
+
+/* IRQ handling peripheral */
+
+cl_irq_hw::cl_irq_hw(class cl_uc *auc):
+  cl_hw(auc, HW_INTERRUPT, 0, "irq")
+{
+  muc= (class cl_m6800 *)auc;
+}
+
+int
+cl_irq_hw::init()
+{
+  //class cl_var *v;
+
+  cl_hw::init();
+
+  return 0;
+}
+
+const char *
+cl_irq_hw::cfg_help(t_addr addr)
+{
+  switch (addr)
+    {
+    case m68_nmi_en	: return "NMI enable (RO)";
+    case m68_nmi	: return "NMI request/clear (RW)";
+    case m68_irq_en	: return "IRQ enable (RO)";
+    case m68_irq	: return "IRQ request/clear (RW)";
+    case m68_swi_en	: return "SWI enable (RW)";
+    case m68_swi	: return "SWI request/clear (RW)";
+    }
+  return cl_hw::cfg_help(addr);
+}
+
+void
+cl_irq_hw::print_info(class cl_console_base *con)
+{
+  int i;
+  con->dd_printf("  Handler  ISR    En  Pr Req Act Name\n");
+  for (i= 0; i < uc->it_sources->count; i++)
+    {
+      class cl_it_src *is=
+	(class cl_it_src *)(uc->it_sources->at(i));
+      class cl_it_src *pa= is->get_parent();
+      class cl_it_src *isp= (pa)?pa:is;
+      t_addr a= uc->read_addr(uc->rom, isp->addr);
+      con->dd_printf("  [0x%04x] 0x%04x", AU(isp->addr), a);
+      con->dd_printf(" %-3s", (is->enabled())?"en":"dis");
+      con->dd_printf(" %2d", uc->priority_of(is->nuof));
+      con->dd_printf(" %-3s", (is->pending())?"YES":"no");
+      con->dd_printf(" %-3s", (is->active)?"act":"no");
+      con->dd_printf(" %s", object_name(is));
+      con->dd_printf("\n");
+    }
+  con->dd_printf("Active interrupt service(s):\n");
+  con->dd_printf("  Pr Handler  PC       Source\n");
+  for (i= 0; i < uc->it_levels->count; i++)
+    {
+      class it_level *il= (class it_level *)(uc->it_levels->at(i));
+      if (il->level >= 0)
+	{
+	  con->dd_printf("  %2d", il->level);
+	  con->dd_printf(" 0x%06x", AU(il->addr));
+	  con->dd_printf(" 0x%06x", AU(il->PC));
+	  con->dd_printf(" %s", (il->source)?(object_name(il->source)):
+			 "nothing");
+	  con->dd_printf("\n");
+	}
+    }
+}
+
+
+/* End of m6800.src/irq.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m6800.src/irqcl.h sdcc-4.2.0+dfsg/sim/ucsim/m6800.src/irqcl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/m6800.src/irqcl.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m6800.src/irqcl.h	2021-10-29 17:39:15.000000000 +0000
@@ -0,0 +1,55 @@
+/*
+ * Simulator of microcontrollers (irqcl.h)
+ *
+ * Copyright (C) @@S@@,@@Y@@ Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+
+#include "itsrccl.h"
+
+#include "m6800cl.h"
+
+enum irq_cfg
+  {
+    m68_nmi_en	= 0,
+    m68_nmi	= 1,
+    m68_irq_en	= 2,
+    m68_irq	= 3,
+    m68_swi_en	= 4,
+    m68_swi	= 5,
+    m68_nr	= 6
+  };
+
+class cl_irq_hw: public cl_hw
+{
+ public:
+  class cl_m6800 *muc;
+ public:
+  cl_irq_hw(class cl_uc *auc);
+  virtual int init(void);
+  virtual unsigned int cfg_size(void) { return m68_nr; }
+  virtual const char *cfg_help(t_addr addr);
+  virtual void print_info(class cl_console_base *con);  
+};
+
+
+/* End of m6800.src/irqcl.h */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m6800.src/m6800.cc sdcc-4.2.0+dfsg/sim/ucsim/m6800.src/m6800.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/m6800.src/m6800.cc	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m6800.src/m6800.cc	2022-01-30 11:45:58.000000000 +0000
@@ -0,0 +1,727 @@
+/*
+ * Simulator of microcontrollers (m6800.cc)
+ *
+ * Copyright (C) 2020,20 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#include 
+#include 
+
+#include "globals.h"
+#include "utils.h"
+
+#include "dregcl.h"
+#include "ciacl.h"
+#include "piacl.h"
+
+#include "glob.h"
+#include "irqcl.h"
+
+#include "m6800cl.h"
+
+
+instruction_wrapper_fn itab[256];
+
+int8_t p0ticks[256]= {
+  /*      0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f  */
+  /* 0 */ 0, 2, 0, 0, 0, 0, 2, 2, 4, 4, 2, 2, 2, 2, 2, 2,
+  /* 1 */ 2, 2, 0, 0, 0, 0, 2, 2, 0, 2, 0, 2, 0, 0, 0, 0,
+  /* 2 */ 4, 0, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
+  /* 3 */ 4, 4, 4, 4, 4, 4, 4, 4, 0, 5, 0,10, 0, 0, 9,12,
+  /* 4 */ 2, 0, 0, 2, 2, 0, 2, 2, 2, 2, 2, 0, 2, 2, 0, 2,
+  /* 5 */ 2, 0, 0, 2, 2, 0, 2, 2, 2, 2, 2, 0, 2, 2, 0, 2,
+  /* 6 */ 7, 0, 0, 7, 7, 0, 7, 7, 7, 7, 7, 0, 7, 7, 4, 7,
+  /* 7 */ 6, 0, 0, 6, 6, 0, 6, 6, 6, 6, 6, 0, 6, 6, 3, 6,
+  /* 8 */ 2, 2, 2, 0, 2, 2, 2, 0, 2, 2, 2, 2, 3, 8, 3, 0,
+  /* 9 */ 3, 3, 3, 0, 3, 3, 3, 4, 3, 3, 3, 3, 4, 0, 4, 5,
+  /* a */ 5, 5, 5, 0, 5, 5, 5, 6, 5, 5, 5, 5, 6, 8, 6, 7,
+  /* b */ 4, 4, 4, 0, 4, 4, 4, 5, 4, 4, 4, 4, 5, 9, 5, 6,
+  /* c */ 2, 2, 2, 0, 2, 2, 2, 0, 2, 2, 2, 2, 0, 0, 3, 0,
+  /* d */ 3, 3, 3, 0, 3, 3, 3, 4, 3, 3, 3, 3, 0, 0, 4, 5,
+  /* e */ 5, 5, 5, 0, 5, 5, 5, 6, 5, 5, 5, 5, 0, 0, 6, 7,
+  /* f */ 4, 4, 4, 0, 4, 4, 4, 5, 4, 4, 4, 4, 0, 0, 5, 6
+};
+
+void
+cl_mop16::a(u16_t iaddr)
+{
+  addr= iaddr++;
+  h= as->get_cell(addr);
+  l= as->get_cell(iaddr);
+}
+
+void
+cl_mop16::r(u16_t iaddr)
+{
+  addr= iaddr++;
+  l= as->get_cell(addr);
+  h= as->get_cell(iaddr);
+}
+
+void
+cl_mop16::set_uc(class cl_uc *iuc)
+{
+  uc= iuc;;
+  as= uc->rom;
+}
+
+
+cl_m6800::cl_m6800(class cl_sim *asim):
+  cl_uc(asim)
+{
+  IRQ_AT	= 0xfff8;
+  SWI_AT	= 0xfffa;
+  NMI_AT	= 0xfffc;
+  RESET_AT	= 0xfffe;
+}
+
+int
+cl_m6800::init(void)
+{
+  cl_uc::init();
+  mop16.init();
+  mop16.set_uc(this);
+  fill_def_wrappers(itab);
+  
+  set_xtal(1000000);
+    
+#define RCV(R) reg_cell_var(&c ## R , &r ## R , "" #R "" , "CPU register " #R "")
+  RCV(A);
+  RCV(B);
+  RCV(CC);
+  RCV(IX);
+  RCV(SP);
+#undef RCV
+    
+  setup_ccr();
+
+  wai= false;
+  cI= &cIX;
+  cIX.name= "X";
+  
+  return 0;
+}
+
+const char *
+cl_m6800::id_string(void)
+{
+  return "M6800";
+}
+
+void
+cl_m6800::reset(void)
+{
+  cl_uc::reset();
+
+  cCC.W(0xc0);
+  PC= read_addr(rom, RESET_AT);
+  tick(6);
+}
+  
+void
+cl_m6800::set_PC(t_addr addr)
+{
+  PC= addr;
+}
+
+void
+cl_m6800::mk_hw_elements(void)
+{
+  class cl_hw *h;
+  
+  cl_uc::mk_hw_elements();
+
+  add_hw(h= new cl_dreg(this, 0, "dreg"));
+  h->init();
+
+  add_hw(h= new cl_irq_hw(this));
+  h->init();
+
+  src_irq= new cl_it_src(this,
+			 irq_irq,
+			 &cCC, flagI,
+			 h->cfg_cell(m68_irq), 1,
+			 IRQ_AT,
+			 true,
+			 true,
+			 "Interrupt request",
+			 0);
+  src_irq->set_cid('i');
+  src_irq->init();
+  src_irq->set_ie_value(0);
+  it_sources->add(src_irq);
+  
+  src_nmi= new cl_it_src(this,
+			 irq_nmi,
+			 h->cfg_cell(m68_nmi_en), 1,
+			 h->cfg_cell(m68_nmi), 1,
+			 NMI_AT,
+			 true,
+			 true,
+			 "Non-maskable interrupt request",
+			 0);
+  src_nmi->set_cid('n');
+  src_nmi->init();
+  it_sources->add(src_nmi);
+  
+  src_swi= new cl_it_src(this,
+			 irq_swi,
+			 h->cfg_cell(m68_swi_en), 1,
+			 h->cfg_cell(m68_swi), 1,
+			 SWI_AT,
+			 true,
+			 true,
+			 "SWI",
+			 0);
+  src_swi->set_cid('s');
+  src_swi->init();
+  it_sources->add(src_swi);
+  
+  add_hw(h= new cl_cia(this, 0, 0x8000));
+  h->init();
+
+  add_hw(h= new cl_cia(this, 1, 0x8008));
+  h->init();
+
+  class cl_pia *p0, *p1;
+  
+  add_hw(p0= new cl_pia(this, 0, 0x8010));
+  p0->init();
+  add_hw(p1= new cl_pia(this, 1, 0x8020));
+  p1->init();
+
+  class cl_port_ui *d;
+  add_hw(d= new cl_port_ui(this, 0, "dport"));
+  d->init();
+
+  class cl_port_data pd;
+  pd.init();
+  pd.set_name("P0A");
+  pd.cell_dir= p0->ddra;
+  pd.cell_p  = p0->ora;
+  pd.cell_in = p0->ina;
+  pd.keyset  = keysets[0];
+  pd.basx    = 1;
+  pd.basy    = 5;
+  d->add_port(&pd, 0);
+
+  pd.set_name("P0B");
+  pd.cell_dir= p0->ddrb;
+  pd.cell_p  = p0->orb;
+  pd.cell_in = p0->inb;
+  pd.keyset  = keysets[1];
+  pd.basx    = 20;
+  pd.basy    = 5;
+  d->add_port(&pd, 1);
+
+  pd.set_name("P0CA");
+  pd.cell_dir= p0->ddca;
+  pd.cell_p  = p0->oca;
+  pd.cell_in = p0->inca;
+  pd.cell_dir= p0->ddca;
+  pd.keyset  = keysets[2];
+  pd.basx    = 40;
+  pd.basy    = 5;
+  pd.width   = 2;
+  d->add_port(&pd, 2);
+
+  pd.set_name("P0CB");
+  pd.cell_dir= p0->ddcb;
+  pd.cell_p  = p0->ocb;
+  pd.cell_in = p0->incb;
+  pd.cell_dir= p0->ddcb;
+  pd.keyset  = keysets[3];
+  pd.basx    = 54;
+  pd.basy    = 5;
+  pd.width   = 2;
+  d->add_port(&pd, 3);
+
+  // Port #1
+  pd.init();
+  pd.set_name("P1A");
+  pd.cell_dir= p1->ddra;
+  pd.cell_p  = p1->ora;
+  pd.cell_in = p1->ina;
+  pd.keyset  = keysets[4];
+  pd.basx    = 1;
+  pd.basy    = 11;
+  d->add_port(&pd, 4);
+
+  pd.set_name("P1B");
+  pd.cell_dir= p1->ddrb;
+  pd.cell_p  = p1->orb;
+  pd.cell_in = p1->inb;
+  pd.keyset  = keysets[5];
+  pd.basx    = 20;
+  pd.basy    = 11;
+  d->add_port(&pd, 5);
+
+  pd.set_name("P1CA");
+  pd.cell_dir= p1->ddca;
+  pd.cell_p  = p1->oca;
+  pd.cell_in = p1->inca;
+  pd.cell_dir= p1->ddca;
+  pd.keyset  = keysets[6];
+  pd.basx    = 40;
+  pd.basy    = 11;
+  pd.width   = 2;
+  d->add_port(&pd, 6);
+
+  pd.set_name("P1CB");
+  pd.cell_dir= p1->ddcb;
+  pd.cell_p  = p1->ocb;
+  pd.cell_in = p1->incb;
+  pd.cell_dir= p1->ddcb;
+  pd.keyset  = keysets[7];
+  pd.basx    = 54;
+  pd.basy    = 11;
+  pd.width   = 2;
+  d->add_port(&pd, 7);
+}
+
+void
+cl_m6800::make_cpu_hw(void)
+{
+}
+
+void
+cl_m6800::make_memories(void)
+{
+  class cl_address_space *as;
+  class cl_address_decoder *ad;
+  class cl_memory_chip *chip;
+  
+  rom= as= new cl_address_space("rom", 0, 0x10000, 8);
+  as->init();
+  address_spaces->add(as);
+
+  chip= new cl_chip8("rom_chip", 0x10000, 8);
+  chip->init();
+  memchips->add(chip);
+  ad= new cl_address_decoder(as= rom,
+			     chip, 0, 0xffff, 0);
+  ad->init();
+  as->decoders->add(ad);
+  ad->activate(0);
+}
+
+void
+cl_m6800::setup_ccr(void)
+{
+  class cl_memory_operator *op= new cl_cc_operator(&cCC);
+  cCC.append_operator(op);
+}
+
+struct dis_entry *
+cl_m6800::dis_tbl(void)
+{
+  return(disass_m6800);
+}
+
+struct dis_entry *
+cl_m6800::get_dis_entry(t_addr addr)
+{
+  struct dis_entry *dt= dis_tbl();//, *dis_e;
+  int i= 0;
+  t_mem code= rom->get(addr);
+
+  if (dt == NULL)
+    return NULL;
+  while (((code & dt[i].mask) != dt[i].code) &&
+	 dt[i].mnemonic)
+    i++;
+  return &dt[i];
+}
+
+char *
+cl_m6800::disassc(t_addr addr, chars *comment)
+{
+  chars work= chars(), temp= chars();
+  const char *b;
+  //t_mem code= rom->get(addr);
+  struct dis_entry *dis_e;
+  int i;
+  bool first;
+
+  cI= &cX;
+  if ((dis_e= get_dis_entry(addr)) == NULL)
+    return NULL;
+  if (dis_e->mnemonic == NULL)
+    return strdup("-- UNKNOWN/INVALID");
+  b= dis_e->mnemonic;
+  u8_t code= rom->read(addr);
+  if (code == 0x18) { addr++; }
+  if (code == 0x1a) { addr++; }
+  if (code == 0xcd) { addr++; }
+  
+  first= true;
+  work= "";
+  for (i=0; b[i]; i++)
+    {
+      if ((b[i] == ' ') && first)
+	{
+	  first= false;
+	  while (work.len() < 6) work.append(' ');
+	}
+      if (b[i] == '%')
+	{
+	  t_addr a;
+	  u8_t h, l;
+	  i++;
+	  temp= "";
+	  switch (b[i])
+	    {
+	    case 'x': case 'X': // indexed
+	      h= rom->read(++addr);
+	      a= cI->get()+h;
+	      work.appendf("$%02x,%s", h, cI->name.c_str());
+	      //add_spaces(&work, 20);
+	      if (b[i]=='x')
+		temp.appendf("; [$%04x]=$%02x", a, rom->read(a));
+	      else
+		temp.appendf("; [$%04x]=$%04x", a, read_addr(rom, a));
+	      break;
+	    case 'e': case 'E': // extended
+	      h= rom->read(++addr);
+	      l= rom->read(++addr);
+	      a= h*256 + l;
+	      work.appendf("$%04x", a);
+	      //add_spaces(&work, 20);
+	      if (b[i]=='e')
+		temp.appendf("; [$%04x]=$%02x", a, rom->read(a));
+	      else
+		temp.appendf("; [$%04x]=$%04x", a,
+			     read_addr(rom, a));
+	      break;
+	    case 'd': case 'D': // direct
+	      h= a= rom->read(++addr);
+	      work.appendf("$00%02x", h);
+	      //add_spaces(&work, 20);
+	      if (b[i]=='d')
+		temp.appendf("; [$%04x]=$%02x", a, rom->read(a));
+	      else
+	        temp.appendf("; [$%04x]=$%04x", a,
+			     read_addr(rom, a));
+	      break;
+	    case 'b': // immediate 8 bit
+	      work.appendf("#$%02x",
+			   rom->read(++addr));
+	      break;
+	    case 'B': // immediate 16 bit
+	      work.appendf("#$%04x",
+			   read_addr(rom, ++addr));
+	      break;
+	    case 'r': // relative
+	      work.appendf("$%04x",
+			   (addr+2+(i8_t)(rom->read(addr+1))) & 0xffff );
+	      addr++;
+	      break;
+	    }
+	  //work+= temp;
+	  if (comment && temp.nempty())
+	    comment->append(temp);
+	}
+      else
+	work+= b[i];
+    }
+
+  return(strdup(work.c_str()));
+}
+
+void
+cl_m6800::analyze_start(void)
+{
+  struct {
+    const char *name;
+    t_addr vector, addr;
+  } vectors[] = {
+    { ".reset", 0xfffe },
+    { ".nmi",   0xfffc },
+    { ".swi",   0xfffa },
+    { ".irq1",  0xfff8 },
+    { ".icf",   0xfff6 },
+    { ".ocf",   0xfff4 },
+    { ".tof",   0xfff2 },
+    { ".sci",   0xfff0 },
+  };
+
+  for (size_t i = 0; i < sizeof(vectors) / sizeof(vectors[0]); i++)
+    {
+      vectors[i].addr = rom->read(vectors[i].vector) * 256 + rom->read(vectors[i].vector + 1);
+      class cl_var *v = new cl_var(vectors[i].name, rom, vectors[i].addr, chars("Auto-generated by analyze"), -1, -1);
+      v->init();
+      vars->add(v);
+    }
+
+  for (size_t i = 0; i < sizeof(vectors) / sizeof(vectors[0]); i++)
+    analyze(vectors[i].addr);
+}
+
+void
+cl_m6800::analyze(t_addr addr)
+{
+  struct dis_entry *di;
+
+  while (!inst_at(addr) && (di = get_dis_entry(addr)) && (di->mnemonic != NULL))
+    {
+      set_inst_at(addr);
+
+      t_addr ta;
+      switch (di->branch)
+	{
+	case 'r': // uncond jump rel
+	  {
+	    i8_t r= rom->read(addr+di->length-1); // last byte of inst
+	    ta= addr+di->length+r;
+	    analyze_jump(addr, ta, 'j');
+	  }
+	  return;
+	case 'R': // conditional jump rel
+	  {
+	    i8_t r= rom->read(addr+di->length-1); // last byte of inst
+	    ta= addr+di->length+r;
+	    analyze_jump(addr, ta, 'b');
+	  }
+	  break;
+	case 's': // SWI
+	  ta= read_addr(rom, SWI_AT);
+	  analyze_jump(addr, ta, 's');
+	  break;
+	case 'E': // call extended
+	  ta= read_addr(rom, addr+1);
+	  analyze_jump(addr, ta, 's');
+	  break;
+	case 'd': // call direct
+	  ta= rom->read(addr+1);
+	  analyze_jump(addr, ta, 's');
+	  break;
+	case 'e': // jump extended
+	  addr= read_addr(rom, addr+1);
+	  analyze_jump(addr, addr, 'j');
+	  return;
+	case '_':
+	  return;
+	default:
+	  break;
+	}
+      addr= rom->validate_address(addr+di->length);
+    }
+}
+
+int
+cl_m6800::inst_length(t_addr addr)
+{
+  struct dis_entry *di= get_dis_entry(addr);
+  if (di && di->mnemonic)
+    return di->length;
+  return 1;
+}
+
+t_addr
+cl_m6800::read_addr(class cl_memory *m, t_addr start_addr)
+{
+  u8_t h, l;
+  h= m->read(start_addr);
+  l= m->read(start_addr+1);
+  return h*256 + l;
+}
+
+void
+cl_m6800::print_regs(class cl_console_base *con)
+{
+  con->dd_color("answer");
+  con->dd_printf("A= $%02x %3d %+4d %c  ", A, A, (i8_t)A, isprint(A)?A:'.');
+  con->dd_printf("B= $%02x %3d %+4d %c  ", B, B, (i8_t)B, isprint(B)?B:'.');
+  con->dd_printf("\n");
+  con->dd_printf("CC= "); con->print_bin(rF, 8); con->dd_printf("\n");
+  con->dd_printf("      HINZVC\n");
+
+  con->dd_printf("IX= ");
+  rom->dump(0, IX, IX+7, 8, con);
+  con->dd_color("answer");
+  
+  con->dd_printf("SP= ");
+  rom->dump(0, SP, SP+7, 8, con);
+  con->dd_color("answer");
+  
+  print_disass(PC, con);
+}
+
+int
+cl_m6800::exec_inst(void)
+{
+  int res= resGO;
+  
+  cI= &cIX;
+  res= exec_inst_tab(itab);
+  post_inst();
+  if (res != resNOT_DONE)
+    return res;
+
+  inst_unknown(rom->read(instPC));
+  return(res);
+}
+
+int
+cl_m6800::accept_it(class it_level *il)
+{
+  class cl_it_src *is= il->source;
+
+  if (!wai)
+      push_regs(false);
+  wai= false;
+  
+  if ((is == src_irq) ||
+      (is == src_swi))
+    rCC|= flagI;
+  
+  t_addr a= read_addr(rom, is->addr);
+  PC= a;
+  
+  is->clear();
+  it_levels->push(il);
+  
+  return resGO;
+}
+
+void
+cl_m6800::push_regs(bool inst_part)
+{
+  rom->write(rSP--, PC&0xff);
+  rom->write(rSP--, PC>>8);
+  rom->write(rSP--, rIX&0xff);
+  rom->write(rSP--, rIX>>8);
+  rom->write(rSP--, rA);
+  rom->write(rSP--, rB);
+  rom->write(rSP--, rCC);
+  if (!inst_part)
+    tick(7);
+}
+
+void
+cl_m6800::pull_regs(bool inst_part)
+{
+  u8_t l, h;
+  rCC= rom->read(++rSP);
+  rB= rom->read(++rSP);
+  rA= rom->read(++rSP);
+  h= rom->read(++rSP);
+  l= rom->read(++rSP);
+  rIX= h*256+l;
+  h= rom->read(++rSP);
+  l= rom->read(++rSP);
+  PC= h*256+l;
+  if (!inst_part)
+    tick(7);
+}
+
+class cl_memory_cell &
+cl_m6800::idx(void)
+{
+  u16_t a= cI->get();
+  u8_t r= fetch();
+  a+= r;
+  class cl_cell8 *c= (class cl_cell8 *)rom->get_cell(a);
+  return *c;//= rom->get_cell(a);
+}
+
+class cl_memory_cell &
+cl_m6800::ext(void)
+{
+  t_addr a;
+  u8_t h, l;
+  h= fetch();
+  l= fetch();
+  a= h*256 + l;
+  class cl_cell8 *c= (class cl_cell8 *)rom->get_cell(a);
+  return *c;
+}
+
+class cl_memory_cell &
+cl_m6800::dir(void)
+{
+  t_addr a= fetch();
+  class cl_cell8 *c= (class cl_cell8 *)rom->get_cell(a);
+  return *c;
+}
+
+u16_t
+cl_m6800::iop16(void)
+{
+  t_addr a= iaddr();
+  vc.rd+= 2;
+  return read_addr(rom, a);
+}
+
+u16_t
+cl_m6800::eop16(void)
+{
+  t_addr a= eaddr();
+  vc.rd+= 2;
+  return read_addr(rom, a);
+}
+
+u16_t
+cl_m6800::dop16(void)
+{
+  t_addr a= daddr();
+  vc.rd+= 2;
+  return read_addr(rom, a);
+}
+
+t_addr
+cl_m6800::iaddr(void)
+{
+  u16_t a= cI->get();
+  u8_t r= fetch();
+  a+= r;
+  return a;
+}
+
+t_addr
+cl_m6800::eaddr(void)
+{
+  t_addr a;
+  u8_t h, l;
+  h= fetch();
+  l= fetch();
+  a= h*256 + l;
+  return a;
+}
+
+t_addr
+cl_m6800::daddr(void)
+{
+  t_addr a= fetch();
+  return a;
+}
+
+t_addr
+cl_m6800::raddr(void)
+{
+  i8_t a= fetch();
+  return (PC+a)&0xffff;
+}
+
+/* End of m6800.src/m6800.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m6800.src/m6800cl.h sdcc-4.2.0+dfsg/sim/ucsim/m6800.src/m6800cl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/m6800.src/m6800cl.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m6800.src/m6800cl.h	2022-02-02 07:13:37.000000000 +0000
@@ -0,0 +1,483 @@
+/*
+ * Simulator of microcontrollers (m6800cl.h)
+ *
+ * Copyright (C) 2020,20 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef M6800CL_HEADER
+#define M6800CL_HEADER
+
+#include "ddconfig.h"
+
+#include "uccl.h"
+#include "memcl.h"
+#include "itsrccl.h"
+#include "decode.h"
+#include "iwrap.h"
+
+
+extern instruction_wrapper_fn itab[256];
+
+struct acc_t {
+  union {
+    u16_t Dr;
+    struct {
+#ifdef WORDS_BIGENDIAN
+      u8_t Ar;
+      u8_t Br;
+#else
+      u8_t Br;
+      u8_t Ar;
+#endif
+    } a8;
+  } DAB;
+};
+
+struct cc_t {
+  union {
+    u16_t cc16;
+    struct {
+#ifdef WORDS_BIGENDIAN
+      u8_t cch;
+      u8_t ccl;
+#else
+      u8_t ccl;
+      u8_t cch;
+#endif
+    } cc8;
+  } cc16;
+};
+
+#define rA  (acc.DAB.a8.Ar)
+#define A   (acc.DAB.a8.Ar)
+#define rB  (acc.DAB.a8.Br)
+#define B   (acc.DAB.a8.Br)
+#define rD  (acc.DAB.Dr)
+#define D   (acc.DAB.Dr)
+#define rCC (CC.cc16.cc8.ccl)
+#define rF  (CC.cc16.cc8.ccl)
+#define rIX (IX)
+#define rX  (IX)
+#define rSP (SP)
+
+#define cF  (cCC)
+#define cX  (cIX)
+
+
+//  Flag bit masks
+enum {
+  mC	= 0x01,
+  flagC	= 0x01,
+  mO	= 0x02,
+  flagO	= 0x02,
+  mV	= 0x02,
+  flagV	= 0x02,
+  mZ	= 0x04,
+  flagZ	= 0x04,
+  mN	= 0x08,
+  flagN	= 0x08,
+  mI	= 0x10,
+  flagI	= 0x10,
+  mH	= 0x20,
+  flagH	= 0x20,
+  mA	= 0x40,
+  flagA	= 0x40
+};
+
+#define ifCS	(rF&mC)
+#define ifCC	(!(rF&mC))
+#define ifMI	(rF&mN)
+#define ifPL	(!(rF&mN))
+#define ifVS	(rF&mV)
+#define ifVC	(!(rF&mV))
+#define ifEQ	(rF&mZ)
+#define ifNE	(!(rF&mZ))
+#define ifLT	( ((rF&mV)?1:0) ^ ((rF&mV)?1:0) )
+#define ifLE	( (rF&mZ) | (((rF&mN)?mZ:0) ^ ((rF&mV)?mZ:0)) )
+#define ifGE	(!ifLT)
+#define ifGT	(!ifLE)
+#define ifLS	( ((rF&mC)?mZ:0) | (rF&mZ) )
+#define ifHI	(!ifLS)
+#define ifA	(true)
+#define ifN	(false)
+
+extern int8_t p0ticks[256];
+
+class cl_idx16: public cl_cell16
+{
+public:
+  chars name;
+public:
+  cl_idx16(): cl_cell16() { name= ""; }
+};
+
+
+class cl_mop16: public cl_cell16
+{
+protected:
+  cl_memory_cell *l, *h;
+  u16_t addr;
+  class cl_address_space *as;
+  class cl_uc *uc;
+public:
+  cl_mop16(): cl_cell16() {}
+  virtual void set_uc(class cl_uc *iuc);
+  virtual void a(u16_t iaddr);
+  virtual void r(u16_t iaddr);
+  virtual t_mem read(void) { return h->R()*256 + l->R(); }
+  virtual t_mem get(void)  { return h->get()*256 + l->get(); }
+  virtual t_mem write(t_mem val) { return (h->W(val>>8))*256 + l->W(val); }
+  virtual t_mem set(t_mem val) { h->set(val>>8); l->set(val); return val; }
+};
+
+  
+/*
+ * Base of M6800 processor
+ */
+
+class cl_m6800: public cl_uc
+{
+public:
+  struct acc_t acc;
+  struct cc_t CC;
+  u16_t IX, SP;
+  class cl_cell8 cA, cB, cCC;
+  class cl_cell16 cSP;
+  class cl_idx16 cIX;
+  class cl_it_src *src_irq, *src_nmi, *src_swi;
+  class cl_idx16 *cI;
+  class cl_mop16 mop16;
+  bool wai;
+  u16_t IRQ_AT, SWI_AT, NMI_AT, RESET_AT;
+public:
+  cl_m6800(class cl_sim *asim);
+  virtual int init(void);
+  virtual const char *id_string(void);
+  virtual void reset(void);
+  virtual void set_PC(t_addr addr);
+
+  virtual void mk_hw_elements(void);
+  virtual void make_cpu_hw(void);
+  virtual void make_memories(void);
+  virtual void setup_ccr(void);
+  
+  virtual int8_t *tick_tab(t_mem code) { return p0ticks; }
+  virtual int clock_per_cycle(void) { return 1; }
+  virtual struct dis_entry *dis_tbl(void);
+  virtual struct dis_entry *get_dis_entry(t_addr addr);
+  virtual char *disassc(t_addr addr, chars *comment=NULL);
+  virtual t_addr read_addr(class cl_memory *m, t_addr start_addr);
+  virtual void analyze_start(void);
+  virtual void analyze(t_addr addr);
+  virtual int inst_length(t_addr addr);
+  virtual int longest_inst(void) { return 4; }
+  
+  virtual void print_regs(class cl_console_base *con);
+
+  virtual int exec_inst(void);
+  virtual int priority_of(uchar nuof_it) { return nuof_it; }
+  virtual int accept_it(class it_level *il);
+  virtual bool it_enabled(void) { return true; }
+  virtual void push_regs(bool inst_part);
+  virtual void pull_regs(bool inst_part);
+  
+  virtual class cl_memory_cell &idx(void);
+  virtual class cl_memory_cell &ext(void);
+  virtual class cl_memory_cell &dir(void);
+  u8_t i8(void) { return fetch(); }
+  u16_t i16(void) { u8_t h, l; h= fetch(); l= fetch(); return h*256+l; }
+  u8_t iop(void) { vc.rd++; return idx().R(); }
+  u8_t eop(void) { vc.rd++; return ext().R(); }
+  u8_t dop(void) { vc.rd++; return dir().R(); }
+  u16_t iop16(void);
+  u16_t eop16(void);
+  u16_t dop16(void);
+  t_addr iaddr(void);
+  t_addr eaddr(void);
+  t_addr daddr(void);
+  t_addr raddr(void);
+  virtual class cl_memory_cell &idst(void) { vc.rd++; vc.wr++; return idx(); }
+  virtual class cl_memory_cell &edst(void) { vc.rd++; vc.wr++; return ext(); }
+  virtual class cl_memory_cell &ddst(void) { vc.rd++; vc.wr++; return dir(); }
+  
+  virtual int sub(class cl_memory_cell &dest, u8_t op, bool c);
+  virtual int sub(class cl_memory_cell &dest, u8_t op);
+  virtual int sbc(class cl_memory_cell &dest, u8_t op);
+  virtual int cmp(u8_t op1, u8_t op2);
+  virtual int add(class cl_memory_cell &dest, u8_t op, bool c);
+  virtual int add(class cl_memory_cell &dest, u8_t op);
+  virtual int adc(class cl_memory_cell &dest, u8_t op);
+  virtual int neg(class cl_memory_cell &dest);
+  virtual int com(class cl_memory_cell &dest);
+  virtual int lsr(class cl_memory_cell &dest);
+  virtual int ror(class cl_memory_cell &dest);
+  virtual int asr(class cl_memory_cell &dest);
+  virtual int asl(class cl_memory_cell &dest);
+  virtual int rol(class cl_memory_cell &dest);
+  virtual int dec(class cl_memory_cell &dest);
+  virtual int inc(class cl_memory_cell &dest);
+  virtual int tst(u8_t op);
+  virtual int clr(class cl_memory_cell &dest);
+  virtual int And(class cl_memory_cell &dest, u8_t op);
+  virtual int bit(u8_t op1, u8_t op2);
+  virtual int eor(class cl_memory_cell &dest, u8_t op);
+  virtual int Or (class cl_memory_cell &dest, u8_t op);
+  virtual int lda(class cl_memory_cell &dest, u8_t op);
+  virtual int sta(class cl_memory_cell &dest, u8_t op);
+  virtual int cpx(u16_t op);
+  virtual int ldsx(class cl_cell16 &dest, u16_t op);
+  virtual int stsx(t_addr a, u16_t op);
+  virtual int call(t_addr a);
+  virtual int branch(t_addr a, bool cond);
+  
+  virtual int NOP(t_mem code);
+  virtual int TAP(t_mem code);
+  virtual int TPA(t_mem code);
+  virtual int INX(t_mem code);
+  virtual int DEX(t_mem code);
+  virtual int CLV(t_mem code);
+  virtual int SEV(t_mem code);
+  virtual int CLC(t_mem code);
+  virtual int SEc(t_mem code);
+  virtual int CLI(t_mem code);
+  virtual int SEI(t_mem code);
+
+  virtual int SBA(t_mem code) { return sub(cA, rB, false); }
+  virtual int CBA(t_mem code) { return cmp(rA, rB); }
+  virtual int TAB(t_mem code);
+  virtual int TBA(t_mem code);
+  virtual int DAA(t_mem code);
+  virtual int ABA(t_mem code) { return add(cA, rB, false); }
+
+  virtual int BRA(t_mem code) { return branch(raddr(), ifA); }
+  virtual int BRN(t_mem code) { return branch(raddr(), ifN); }
+  virtual int BHI(t_mem code) { return branch(raddr(), ifHI); }
+  virtual int BLS(t_mem code) { return branch(raddr(), ifLS); }
+  virtual int BCC(t_mem code) { return branch(raddr(), ifCC); }
+  virtual int BCS(t_mem code) { return branch(raddr(), ifCS); }
+  virtual int BNE(t_mem code) { return branch(raddr(), ifNE); }
+  virtual int BEQ(t_mem code) { return branch(raddr(), ifEQ); }
+  virtual int BVC(t_mem code) { return branch(raddr(), ifVC); }
+  virtual int BVS(t_mem code) { return branch(raddr(), ifVS); }
+  virtual int BPL(t_mem code) { return branch(raddr(), ifPL); }
+  virtual int BMI(t_mem code) { return branch(raddr(), ifMI); }
+  virtual int BGE(t_mem code) { return branch(raddr(), ifGE); }
+  virtual int BLT(t_mem code) { return branch(raddr(), ifLT); }
+  virtual int BGT(t_mem code) { return branch(raddr(), ifGT); }
+  virtual int BLE(t_mem code) { return branch(raddr(), ifLE); }
+  
+  virtual int TSX(t_mem code);
+  virtual int INS(t_mem code);
+  virtual int PULA(t_mem code);
+  virtual int PULB(t_mem code);
+  virtual int DES(t_mem code);
+  virtual int TXS(t_mem code);
+  virtual int PSHA(t_mem code);
+  virtual int PSHB(t_mem code);
+  virtual int RTS(t_mem code);
+
+  virtual int RTI(t_mem code);
+  virtual int WAI(t_mem code);
+  virtual int SWI(t_mem code);
+  
+  virtual int NEGA(t_mem code) { return neg(cA); }
+  virtual int COMA(t_mem code) { return com(cA); }
+  virtual int LSRA(t_mem code) { return lsr(cA); }
+  virtual int RORA(t_mem code) { return ror(cA); }
+  virtual int ASRA(t_mem code) { return asr(cA); }
+  virtual int ASLA(t_mem code) { return asl(cA); }
+  virtual int ROLA(t_mem code) { return rol(cA); }
+  virtual int DECA(t_mem code) { return dec(cA); }
+  virtual int INCA(t_mem code) { return inc(cA); }
+  virtual int TSTA(t_mem code) { return tst(rA); }
+  virtual int CLRA(t_mem code) { return clr(cA); }
+
+  virtual int NEGB(t_mem code) { return neg(cB); }
+  virtual int COMB(t_mem code) { return com(cB); }
+  virtual int LSRB(t_mem code) { return lsr(cB); }
+  virtual int RORB(t_mem code) { return ror(cB); }
+  virtual int ASRB(t_mem code) { return asr(cB); }
+  virtual int ASLB(t_mem code) { return asl(cB); }
+  virtual int ROLB(t_mem code) { return rol(cB); }
+  virtual int DECB(t_mem code) { return dec(cB); }
+  virtual int INCB(t_mem code) { return inc(cB); }
+  virtual int TSTB(t_mem code) { return tst(rB); }
+  virtual int CLRB(t_mem code) { return clr(cB); }
+
+  virtual int NEGi(t_mem code) { return neg(idst()); }
+  virtual int COMi(t_mem code) { return com(idst()); }
+  virtual int LSRi(t_mem code) { return lsr(idst()); }
+  virtual int RORi(t_mem code) { return ror(idst()); }
+  virtual int ASRi(t_mem code) { return asr(idst()); }
+  virtual int ASLi(t_mem code) { return asl(idst()); }
+  virtual int ROLi(t_mem code) { return rol(idst()); }
+  virtual int DECi(t_mem code) { return dec(idst()); }
+  virtual int INCi(t_mem code) { return inc(idst()); }
+  virtual int TSTi(t_mem code) { vc.rd++; return tst(idx().R()); }
+  virtual int JMPi(t_mem code);
+  virtual int CLRi(t_mem code) { vc.wr++; return clr(idx()); }
+
+  virtual int NEGe(t_mem code) { return neg(edst()); }
+  virtual int COMe(t_mem code) { return com(edst()); }
+  virtual int LSRe(t_mem code) { return lsr(edst()); }
+  virtual int RORe(t_mem code) { return ror(edst()); }
+  virtual int ASRe(t_mem code) { return asr(edst()); }
+  virtual int ASLe(t_mem code) { return asl(edst()); }
+  virtual int ROLe(t_mem code) { return rol(edst()); }
+  virtual int DECe(t_mem code) { return dec(edst()); }
+  virtual int INCe(t_mem code) { return inc(edst()); }
+  virtual int TSTe(t_mem code) { vc.rd++; return tst(ext().R()); }
+  virtual int JMPe(t_mem code);
+  virtual int CLRe(t_mem code) { vc.wr++; return clr(ext()); }
+
+  virtual int SUBA8(t_mem code) { return sub(cA, i8(), false); }
+  virtual int CMPA8(t_mem code) { return cmp(rA, i8()); }
+  virtual int SBCA8(t_mem code) { return sub(cA, i8(), true); }
+  virtual int ANDA8(t_mem code) { return And(cA, i8()); }
+  virtual int BITA8(t_mem code) { return bit(rA, i8()); }
+  virtual int LDAA8(t_mem code) { return lda(cA, i8()); }
+  virtual int EORA8(t_mem code) { return eor(cA, i8()); }
+  virtual int ADCA8(t_mem code) { return add(cA, i8(), true); }
+  virtual int ORAA8(t_mem code) { return Or (cA, i8()); }
+  virtual int ADDA8(t_mem code) { return add(cA, i8(), false); }
+  virtual int CPX16(t_mem code) { return cpx(i16()); }
+  virtual int BSR  (t_mem code) { return call(raddr()); }
+  virtual int LDS16(t_mem code) { return ldsx(cSP, i16()); }
+
+  virtual int SUBAd(t_mem code) { return sub(cA, dop(), false); }
+  virtual int CMPAd(t_mem code) { return cmp(rA, dop()); }
+  virtual int SBCAd(t_mem code) { return sub(cA, dop(), true); }
+  virtual int ANDAd(t_mem code) { return And(cA, dop()); }
+  virtual int BITAd(t_mem code) { return bit(rA, dop()); }
+  virtual int LDAAd(t_mem code) { return lda(cA, dop()); }
+  virtual int STAAd(t_mem code) { return lda(ddst(), rA); }
+  virtual int EORAd(t_mem code) { return eor(cA, dop()); }
+  virtual int ADCAd(t_mem code) { return add(cA, dop(), true); }
+  virtual int ORAAd(t_mem code) { return Or (cA, dop()); }
+  virtual int ADDAd(t_mem code) { return add(cA, dop(), false); }
+  virtual int CPXd (t_mem code) { return cpx(dop16()); }
+  virtual int LDSd (t_mem code) { return ldsx(cSP, dop16()); }
+  virtual int STSd (t_mem code) { return stsx(daddr(), rSP); }
+
+  virtual int SUBAi(t_mem code) { return sub(cA, iop(), false); }
+  virtual int CMPAi(t_mem code) { return cmp(rA, iop()); }
+  virtual int SBCAi(t_mem code) { return sub(cA, iop(), true); }
+  virtual int ANDAi(t_mem code) { return And(cA, iop()); }
+  virtual int BITAi(t_mem code) { return bit(rA, iop()); }
+  virtual int LDAAi(t_mem code) { return lda(cA, iop()); }
+  virtual int STAAi(t_mem code) { return lda(idst(), rA); }
+  virtual int EORAi(t_mem code) { return eor(cA, iop()); }
+  virtual int ADCAi(t_mem code) { return add(cA, iop(), true); }
+  virtual int ORAAi(t_mem code) { return Or (cA, iop()); }
+  virtual int ADDAi(t_mem code) { return add(cA, iop(), false); }
+  virtual int CPXi (t_mem code) { return cpx(iop16()); }
+  virtual int JSRi (t_mem code) { return call(iaddr()); }
+  virtual int LDSi (t_mem code) { return ldsx(cSP, iop16()); }
+  virtual int STSi (t_mem code) { return stsx(iaddr(), rSP); }
+
+  virtual int SUBAe(t_mem code) { return sub(cA, eop(), false); }
+  virtual int CMPAe(t_mem code) { return cmp(rA, eop()); }
+  virtual int SBCAe(t_mem code) { return sub(cA, eop(), true); }
+  virtual int ANDAe(t_mem code) { return And(cA, eop()); }
+  virtual int BITAe(t_mem code) { return bit(rA, eop()); }
+  virtual int LDAAe(t_mem code) { return lda(cA, eop()); }
+  virtual int STAAe(t_mem code) { return lda(edst(), rA); }
+  virtual int EORAe(t_mem code) { return eor(cA, eop()); }
+  virtual int ADCAe(t_mem code) { return add(cA, eop(), true); }
+  virtual int ORAAe(t_mem code) { return Or (cA, eop()); }
+  virtual int ADDAe(t_mem code) { return add(cA, eop(), false); }
+  virtual int CPXe (t_mem code) { return cpx(eop16()); }
+  virtual int JSRe (t_mem code) { return call(eaddr()); }
+  virtual int LDSe (t_mem code) { return ldsx(cSP, eop16()); }
+  virtual int STSe (t_mem code) { return stsx(eaddr(), rSP); }
+
+  virtual int SUBB8(t_mem code) { return sub(cB, i8(), false); }
+  virtual int CMPB8(t_mem code) { return cmp(rB, i8()); }
+  virtual int SBCB8(t_mem code) { return sub(cB, i8(), true); }
+  virtual int ANDB8(t_mem code) { return And(cB, i8()); }
+  virtual int BITB8(t_mem code) { return bit(rB, i8()); }
+  virtual int LDAB8(t_mem code) { return lda(cB, i8()); }
+  virtual int EORB8(t_mem code) { return eor(cB, i8()); }
+  virtual int ADCB8(t_mem code) { return add(cB, i8(), true); }
+  virtual int ORAB8(t_mem code) { return Or (cB, i8()); }
+  virtual int ADDB8(t_mem code) { return add(cB, i8(), false); }
+  virtual int LDX16(t_mem code) { return ldsx(cX, i16()); }
+
+  virtual int SUBBd(t_mem code) { return sub(cB, dop(), false); }
+  virtual int CMPBd(t_mem code) { return cmp(rB, dop()); }
+  virtual int SBCBd(t_mem code) { return sub(cB, dop(), true); }
+  virtual int ANDBd(t_mem code) { return And(cB, dop()); }
+  virtual int BITBd(t_mem code) { return bit(rB, dop()); }
+  virtual int LDABd(t_mem code) { return lda(cB, dop()); }
+  virtual int STABd(t_mem code) { return lda(ddst(), rB); }
+  virtual int EORBd(t_mem code) { return eor(cB, dop()); }
+  virtual int ADCBd(t_mem code) { return add(cB, dop(), true); }
+  virtual int ORABd(t_mem code) { return Or (cB, dop()); }
+  virtual int ADDBd(t_mem code) { return add(cB, dop(), false); }
+  virtual int LDXd (t_mem code) { return ldsx(cX, dop16()); }
+  virtual int STXd (t_mem code) { return stsx(daddr(), rX); }
+
+  virtual int SUBBi(t_mem code) { return sub(cB, iop(), false); }
+  virtual int CMPBi(t_mem code) { return cmp(rB, iop()); }
+  virtual int SBCBi(t_mem code) { return sub(cB, iop(), true); }
+  virtual int ANDBi(t_mem code) { return And(cB, iop()); }
+  virtual int BITBi(t_mem code) { return bit(rB, iop()); }
+  virtual int LDABi(t_mem code) { return lda(cB, iop()); }
+  virtual int STABi(t_mem code) { return lda(idst(), rB); }
+  virtual int EORBi(t_mem code) { return eor(cB, iop()); }
+  virtual int ADCBi(t_mem code) { return add(cB, iop(), true); }
+  virtual int ORABi(t_mem code) { return Or (cB, iop()); }
+  virtual int ADDBi(t_mem code) { return add(cB, iop(), false); }
+  virtual int LDXi (t_mem code) { return ldsx(cX, iop16()); }
+  virtual int STXi (t_mem code) { return stsx(iaddr(), rX); }
+
+  virtual int SUBBe(t_mem code) { return sub(cB, eop(), false); }
+  virtual int CMPBe(t_mem code) { return cmp(rB, eop()); }
+  virtual int SBCBe(t_mem code) { return sub(cB, eop(), true); }
+  virtual int ANDBe(t_mem code) { return And(cB, eop()); }
+  virtual int BITBe(t_mem code) { return bit(rB, eop()); }
+  virtual int LDABe(t_mem code) { return lda(cB, eop()); }
+  virtual int STABe(t_mem code) { return lda(edst(), rB); }
+  virtual int EORBe(t_mem code) { return eor(cB, eop()); }
+  virtual int ADCBe(t_mem code) { return add(cB, eop(), true); }
+  virtual int ORABe(t_mem code) { return Or (cB, eop()); }
+  virtual int ADDBe(t_mem code) { return add(cB, eop(), false); }
+  virtual int LDXe (t_mem code) { return ldsx(cX, eop16()); }
+  virtual int STXe (t_mem code) { return stsx(eaddr(), rX); }
+};
+
+
+/* Unused bits of CC forced to be 1 */
+
+class cl_cc_operator: public cl_memory_operator
+{
+public:
+  cl_cc_operator(class cl_memory_cell *acell): cl_memory_operator(acell) {}
+  virtual t_mem write(t_mem val) { return val|= 0xc0; }
+};
+
+
+#endif
+
+/* End of m6800.src/m6800cl.h */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m6800.src/Makefile.in sdcc-4.2.0+dfsg/sim/ucsim/m6800.src/Makefile.in
--- sdcc-4.0.0+dfsg/sim/ucsim/m6800.src/Makefile.in	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m6800.src/Makefile.in	2022-01-23 12:11:49.000000000 +0000
@@ -0,0 +1,210 @@
+#
+# uCsim m6800.src/Makefile
+#
+# (c) Drotos Daniel, Talker Bt. 1997
+#
+
+# tool name
+TN		= m6800
+
+STARTYEAR	= 1997
+
+SHELL		= /bin/sh
+CXX		= @CXX@
+CPP		= @CPP@
+CXXCPP		= @CXXCPP@
+RANLIB		= @RANLIB@
+INSTALL		= @INSTALL@
+STRIP		= @STRIP@
+MAKEDEP         = @MAKEDEP@
+
+top_builddir	= @top_builddir@
+top_srcdir	= @top_srcdir@
+
+transform	= @program_transform_name@
+
+DEFS            = $(subs -DHAVE_CONFIG_H,,@DEFS@)
+CPPFLAGS        = @CPPFLAGS@ -I$(srcdir) -I$(top_srcdir) -I$(top_builddir) \
+		  -I$(top_srcdir)/cmd.src -I$(top_srcdir)/sim.src \
+		  -I$(top_srcdir)/gui.src -I$(top_srcdir)/motorola.src
+CFLAGS          = @WALL_FLAG@ @CFLAGS@
+CXXFLAGS        = @WALL_FLAG@ @CXXFLAGS@
+LDFLAGS         = @LDFLAGS@
+PICOPT		= @PICOPT@
+SHAREDLIB	= @SHAREDLIB@
+EXEEXT		= @EXEEXT@
+
+LIBS		= -L$(top_builddir) -lmotorola -lsim -lucsimutil -lguiucsim -lcmd -lsim @LIBS@
+DL		= @DL@
+dl_ok		= @dl_ok@
+
+prefix          = @prefix@
+exec_prefix     = @exec_prefix@
+bindir          = @bindir@
+libdir          = @libdir@
+datadir         = @datadir@
+datarootdir     = @datarootdir@
+includedir      = @includedir@
+mandir          = @mandir@
+man1dir         = $(mandir)/man1
+man2dir         = $(mandir)/man2
+infodir         = @infodir@
+srcdir          = @srcdir@
+VPATH           = @srcdir@
+
+OBJECTS_SHARED	= sim$(TN).o $(TN).o glob.o irq.o \
+		  inst.o ialu.o ibranch.o imove.o
+
+#OBJECTS_SHARED11= $(OBJECTS_SHARED) simm68hc11.o m68hc11.o \
+#		  wraps.o glob11.o g11p0.o g11p18.o g11pcd.o g11p1a.o
+
+OBJECTS_EXE	= s$(TN).o
+OBJECTS		= $(OBJECTS_SHARED) $(OBJECTS_EXE)
+
+#OBJECTS_EXE11	= sm68hc11.o
+#BJECTS11	= $(OBJECTS_SHARED11) $(OBJECTS_EXE11)
+
+# short/long exe and lib name
+SEN		= s$(TN)$(EXEEXT)
+LEN		= ucsim_$(TN)$(EXEEXT)
+SONAME		= libucsim_$(TN).so
+
+SEN11		= sm68hc11$(EXEEXT)
+LEN11		= ucsim_m68hc11$(EXEEXT)
+SONAME11	= libucsim_m68hc11.so
+
+enable_dlso	= @enable_dlso@
+dlso_ok		= @dlso_ok@
+
+M6800ASM	=
+TEST_OBJ	= 
+
+
+# Compiling entire program or any subproject
+# ------------------------------------------
+all: checkconf otherlibs $(TN).src
+
+
+# Compiling and installing everything and runing test
+# ---------------------------------------------------
+install: all installdirs install_shared_lib
+	$(INSTALL) $(SEN) $(DESTDIR)$(bindir)/$(SEN)
+	$(STRIP) $(DESTDIR)$(bindir)/$(SEN)
+	$(INSTALL) $(LEN) $(DESTDIR)$(bindir)/$(LEN)
+	$(STRIP) $(DESTDIR)$(bindir)/$(LEN)
+
+#	$(INSTALL) $(SEN11) $(DESTDIR)$(bindir)/$(SEN11)
+#	$(STRIP) $(DESTDIR)$(bindir)/$(SEN11)
+#	$(INSTALL) $(LEN11) $(DESTDIR)$(bindir)/$(LEN11)
+#	$(STRIP) $(DESTDIR)$(bindir)/$(LEN11)
+
+
+# Deleting all the installed files
+# --------------------------------
+uninstall:
+	rm -f $(DESTDIR)$(bindir)/$(SEN)
+	rm -f $(DESTDIR)$(bindir)/$(LEN)
+	rm -f $(DESTDIR)$(libdir)/$(SONAME)
+	rm -f $(DESTDIR)$(bindir)/$(SEN11)
+	rm -f $(DESTDIR)$(bindir)/$(LEN11)
+	rm -f $(DESTDIR)$(libdir)/$(SONAME11)
+
+
+# Performing self-test
+# --------------------
+check: $(TEST_OBJ)
+
+.PHONY:	test baseline
+test:
+	@$(MAKE) --no-print-directory -C test
+
+baseline:
+	@$(MAKE) --no-print-directory -C test baseline
+
+
+# Performing installation test
+# ----------------------------
+installcheck:
+
+
+# Creating installation directories
+# ---------------------------------
+installdirs:
+	test -d $(DESTDIR)$(bindir) || $(INSTALL) -d $(DESTDIR)$(bindir)
+
+
+# Creating dependencies
+# ---------------------
+dep: Makefile.dep
+
+Makefile.dep: $(srcdir)/*.cc $(srcdir)/*.h
+	$(MAKEDEP) $(CPPFLAGS) $(filter %.cc,$^) >Makefile.dep
+
+-include Makefile.dep
+include $(srcdir)/clean.mk
+
+# My rules
+# --------
+.SUFFIXES: .asm .hex
+
+$(TN).src: $(SEN) $(LEN) shared_lib $(TN)lib
+
+$(SEN): $(OBJECTS) $(top_builddir)/libcmd.a $(top_builddir)/libguiucsim.a $(top_builddir)/libsim.a $(top_builddir)/libucsimutil.a $(top_builddir)/libmotorola.a
+	$(CXX) $(CXXFLAGS) $(LDFLAGS) $(OBJECTS) $(LIBS) -o $@
+
+$(LEN): $(SEN)
+	cp $< $@
+
+$(TN)lib: $(top_builddir)/lib$(TN).a
+
+$(top_builddir)/lib$(TN).a: $(OBJECTS_SHARED)
+	$(AR) -rc $@ $(OBJECTS_SHARED)
+	$(RANLIB) $@
+
+ifeq ($(dlso_ok),yes)
+shared_lib: $(top_builddir)/$(SONAME)
+install_shared_lib: shared_lib
+	test -d $(DESTDIR)$(libdir) || $(INSTALL) -d $(DESTDIR)$(libdir)
+	$(INSTALL) $(top_builddir)/$(SONAME) $(DESTDIR)$(libdir)/$(SONAME)
+else
+shared_lib:
+	@$(top_srcdir)/mkecho $(top_builddir) "No $(TN) shared lib made."
+	@$(top_srcdir)/mkecho $(top_builddir) "(SHAREDLIB="$(SHAREDLIB)",dl_ok="$(dl_ok)",enable_dlso="$(enable_dlso)")"
+install_shared_lib:
+endif
+
+$(top_builddir)/$(SONAME): $(OBJECTS_SHARED)
+	$(CXX) -shared $(LDFLAGS) $(OBJECTS_SHARED) -o $@
+
+otherlibs: $(top_builddir)/libcmd.a $(top_builddir)/libguiucsim.a $(top_builddir)/libsim.a $(top_builddir)/libucsimutil.a $(top_builddir)/libmotorola.a
+
+$(top_builddir)/libcmd.a:
+	$(MAKE) -C $(top_builddir)/cmd.src all
+
+$(top_builddir)/libguiucsim.a:
+	$(MAKE) -C $(top_builddir)/gui.src checkconf ucsim_lib
+
+$(top_builddir)/libsim.a:
+	$(MAKE) -C $(top_builddir)/sim.src all
+
+$(top_builddir)/libucsimutil.a:
+	$(MAKE) -C $(top_builddir) -f main.mk
+
+$(top_builddir)/libmotorola.a:
+	$(MAKE) -C $(top_builddir)/motorola.src all
+
+.cc.o:
+	$(CXX) $(CXXFLAGS) $(PICOPT) $(CPPFLAGS) $(TARGET_ARCH) -c $< -o $@
+
+.asm.hex:
+	$(M6800ASM) -l $< -o $@ -e $<.lst
+
+
+# Remaking configuration
+# ----------------------
+checkconf:
+	@if [ -f $(top_builddir)/devel ]; then\
+	  $(MAKE) -C $(top_builddir) -f conf.mk srcdir="$(srcdir)" top_builddir="$(top_builddir)" freshconf;\
+	fi
+
+# End of m6800.src/Makefile.in
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m6800.src/simm6800.cc sdcc-4.2.0+dfsg/sim/ucsim/m6800.src/simm6800.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/m6800.src/simm6800.cc	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m6800.src/simm6800.cc	2021-04-16 22:21:27.000000000 +0000
@@ -0,0 +1,44 @@
+/*
+ * Simulator of microcontrollers (simm6800.cc)
+ *
+ * Copyright (C) 2020,20 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+// local
+#include "simm6800cl.h"
+#include "m6800cl.h"
+
+
+cl_simm6800::cl_simm6800(class cl_app *the_app):
+  cl_sim(the_app)
+{}
+
+class cl_uc *
+cl_simm6800::mk_controller(void)
+{
+  return(new cl_m6800(this));
+}
+
+
+/* End of m6800.src/simm6800.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m6800.src/simm6800cl.h sdcc-4.2.0+dfsg/sim/ucsim/m6800.src/simm6800cl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/m6800.src/simm6800cl.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m6800.src/simm6800cl.h	2021-04-16 22:21:27.000000000 +0000
@@ -0,0 +1,45 @@
+/*
+ * Simulator of microcontrollers (simm6800cl.h)
+ *
+ * Copyright (C) 2020,20 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef SIMM6800CL_HEADER
+#define SIMM6800CL_HEADER
+
+#include "simcl.h"
+
+
+class cl_simm6800: public cl_sim
+{
+public:
+  cl_simm6800(class cl_app *the_app);
+
+  virtual class cl_uc *mk_controller(void);
+};
+
+
+#endif
+
+/* End of m6800.src/simm6800cl.h */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m6800.src/sm6800.cc sdcc-4.2.0+dfsg/sim/ucsim/m6800.src/sm6800.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/m6800.src/sm6800.cc	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m6800.src/sm6800.cc	2021-04-16 22:21:27.000000000 +0000
@@ -0,0 +1,54 @@
+/*
+ * Simulator of microcontrollers (sm6800.cc)
+ *
+ * Copyright (C) 2020,20 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+// prj
+#include "globals.h"
+
+// local
+#include "simm6800cl.h"
+
+
+int
+main(int argc, char *argv[])
+{
+  class cl_sim *sim;
+  
+  application= new cl_app();
+  application->set_name("sm6800");
+  application->init(argc, argv);
+  sim= new cl_simm6800(application);
+  if (sim->init())
+    sim->state|= SIM_QUIT;
+  application->set_simulator(sim);
+  //sim->main();
+  application->run();
+  application->done();
+  delete application;
+  return(0);
+}
+
+/* End of m6800.src/sm6800.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m6800.src/test/clean.mk sdcc-4.2.0+dfsg/sim/ucsim/m6800.src/test/clean.mk
--- sdcc-4.0.0+dfsg/sim/ucsim/m6800.src/test/clean.mk	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m6800.src/test/clean.mk	2021-04-16 22:21:27.000000000 +0000
@@ -0,0 +1,5 @@
+clean:
+
+distclean:
+	rm -f Makefile
+	find . -type d -name out -exec rm -rf {} \;
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m6800.src/test/config/baseline/M6800 sdcc-4.2.0+dfsg/sim/ucsim/m6800.src/test/config/baseline/M6800
--- sdcc-4.0.0+dfsg/sim/ucsim/m6800.src/test/config/baseline/M6800	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m6800.src/test/config/baseline/M6800	2022-02-08 21:21:05.000000000 +0000
@@ -0,0 +1,30 @@
+uCsim, Copyright (C)  Daniel Drotos.
+uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+This is free software, and you are welcome to redistribute it
+under certain conditions; type `show c' for details.
+Type of microcontroller: M6800
+Controller has 9 hardware element(s).
+   on simif[0]
+  off vcd[0]
+   on dreg[0]
+   on irq[0]
+   on uart[0]
+   on uart[1]
+   on pia[0]
+   on pia[1]
+   on dport[0]
+A= $00   0   +0 .  B= $00   0   +0 .  
+CC= 00000000
+      HINZVC
+IX= 0x0000 08 70 d4 b2 8a 29 54 48 .p...)TH
+SP= 0x0000 08 70 d4 b2 8a 29 54 48 .p...)TH
+0x6c75  ? 96 4d       LDA    A,$004d            ; [$004d]=$d3[0K
+Memory chips:
+  0x000000-0x0000ff      256 variable_storage (32,%08x,0x%02lx)
+  0x000000-0x00ffff    65536 rom_chip (8,%02x,0x%04lx)
+Address spaces:
+  0x000000-0x0000ff      256 variables (32,%08x,0x%02lx)
+  0x000000-0x00ffff    65536 rom (8,%02x,0x%04lx)
+Address decoders:
+  variables 0x00 0xff -> variable_storage 0x00 activated
+  rom 0x0000 0xffff -> rom_chip 0x0000 activated
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m6800.src/test/config/Makefile sdcc-4.2.0+dfsg/sim/ucsim/m6800.src/test/config/Makefile
--- sdcc-4.0.0+dfsg/sim/ucsim/m6800.src/test/config/Makefile	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m6800.src/test/config/Makefile	2021-04-16 22:21:27.000000000 +0000
@@ -0,0 +1,8 @@
+OUTPUTS = M6800
+
+
+$(OUTPUTS):
+	$(call run-sim, -e 'conf; info reg; info mem')
+
+
+include test-lib.mk
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m6800.src/test/Makefile.in sdcc-4.2.0+dfsg/sim/ucsim/m6800.src/test/Makefile.in
--- sdcc-4.0.0+dfsg/sim/ucsim/m6800.src/test/Makefile.in	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m6800.src/test/Makefile.in	2021-04-16 22:21:27.000000000 +0000
@@ -0,0 +1,9 @@
+# @configure_input@
+
+srcdir           = @abs_srcdir@
+
+abs_top_builddir = @abs_top_builddir@
+abs_top_srcdir   = @abs_top_srcdir@
+
+
+include $(abs_top_srcdir)/test-target.mk
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m6809.src/(c).1 sdcc-4.2.0+dfsg/sim/ucsim/m6809.src/(c).1
--- sdcc-4.0.0+dfsg/sim/ucsim/m6809.src/(c).1	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m6809.src/(c).1	2020-09-17 06:45:33.000000000 +0000
@@ -0,0 +1,25 @@
+/*
+ * Simulator of microcontrollers (@@F@@)
+ *
+ * Copyright (C) @@S@@,@@Y@@ Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m6809.src/clean.mk sdcc-4.2.0+dfsg/sim/ucsim/m6809.src/clean.mk
--- sdcc-4.0.0+dfsg/sim/ucsim/m6809.src/clean.mk	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m6809.src/clean.mk	2021-03-28 10:28:14.000000000 +0000
@@ -0,0 +1,32 @@
+# m6809.src/clean.mk
+
+# Deleting all files created by building the program
+# --------------------------------------------------
+clean:
+	rm -f *core *[%~] *.[oa] *.map
+	rm -f .[a-z]*~
+	rm -f sm6809$(EXEEXT) sm6809.exe
+	rm -f ucsim_m6809$(EXEEXT) ucsim_m6809.exe
+	$(MAKE) -C test -f clean.mk clean
+
+
+# Deleting all files created by configuring or building the program
+# -----------------------------------------------------------------
+distclean: clean
+	rm -f config.cache config.log config.status
+	rm -f Makefile *.dep
+	rm -f *.obj *.list *.lst *.hex
+	$(MAKE) -C test -f clean.mk distclean
+
+
+# Like clean but some files may still exist
+# -----------------------------------------
+mostlyclean: clean
+
+
+# Deleting everything that can reconstructed by this Makefile. It deletes
+# everything deleted by distclean plus files created by bison, etc.
+# -----------------------------------------------------------------------
+realclean: distclean
+
+# End of m6809.src/clean.mk
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m6809.src/conf.mk sdcc-4.2.0+dfsg/sim/ucsim/m6809.src/conf.mk
--- sdcc-4.0.0+dfsg/sim/ucsim/m6809.src/conf.mk	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m6809.src/conf.mk	2020-09-17 06:45:33.000000000 +0000
@@ -0,0 +1,11 @@
+# m6809.src/conf.mk
+#
+# Makefile targets to remake configuration
+#
+
+freshconf: Makefile
+
+Makefile: $(srcdir)/Makefile.in $(top_srcdir)/configure.ac
+	cd $(top_builddir) && $(SHELL) ./config.status
+
+# End of m6809.src/conf.mk
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m6809.src/glob.cc sdcc-4.2.0+dfsg/sim/ucsim/m6809.src/glob.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/m6809.src/glob.cc	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m6809.src/glob.cc	2022-01-24 11:09:43.000000000 +0000
@@ -0,0 +1,214 @@
+/*
+ * Simulator of microcontrollers (glob.cc)
+ *
+ * Copyright (C) 2020,20 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#include "glob.h"
+
+// code mask branch len mn call tick
+struct dis_entry disass_m6809[]=
+  {
+   { 0x48, 0xff, ' ', 1, "ASLA"		, 0, 0 },
+   { 0x58, 0xff, ' ', 1, "ASLB"		, 0, 0 },
+   { 0x47, 0xff, ' ', 1, "ASRA"		, 0, 0 },
+   { 0x57, 0xff, ' ', 1, "ASRB"		, 0, 0 },
+   { 0x4f, 0xff, ' ', 1, "CLRA"		, 0, 0 },
+   { 0x5f, 0xff, ' ', 1, "CLRB"		, 0, 0 },
+   { 0x43, 0xff, ' ', 1, "COMA"		, 0, 0 },
+   { 0x53, 0xff, ' ', 1, "COMB"		, 0, 0 },
+   { 0x19, 0xff, ' ', 1, "DAA"		, 0, 0 },
+   { 0x4a, 0xff, ' ', 1, "DECA"		, 0, 0 },
+   { 0x5a, 0xff, ' ', 1, "DECB"		, 0, 0 },
+   { 0x4c, 0xff, ' ', 1, "INCA"		, 0, 0 },
+   { 0x5c, 0xff, ' ', 1, "INCB"		, 0, 0 },
+   { 0x44, 0xff, ' ', 1, "LSRA"		, 0, 0 },
+   { 0x54, 0xff, ' ', 1, "LSRB"		, 0, 0 },
+   { 0x3d, 0xff, ' ', 1, "MUL"		, 0, 0 },
+   { 0x40, 0xff, ' ', 1, "NEGA"		, 0, 0 },
+   { 0x50, 0xff, ' ', 1, "NEGB"		, 0, 0 },
+   { 0x12, 0xff, ' ', 1, "NOP"		, 0, 0 },
+   { 0x49, 0xff, ' ', 1, "ROLA"		, 0, 0 },
+   { 0x59, 0xff, ' ', 1, "ROLB"		, 0, 0 },
+   { 0x46, 0xff, ' ', 1, "RORA"		, 0, 0 },
+   { 0x56, 0xff, ' ', 1, "RORB"		, 0, 0 },
+   { 0x3b, 0xff, ' ', 1, "RTI"		, 0, 0 },
+   { 0x39, 0xff, ' ', 1, "RTS"		, 0, 0 },
+   { 0x1d, 0xff, ' ', 1, "SEX"		, 0, 0 },
+   { 0x3f, 0xff, ' ', 1, "SWI"		, 0, 0 },
+   { 0x13, 0xff, ' ', 1, "SYNC"		, 0, 0 },
+   { 0x4d, 0xff, ' ', 1, "TSTA"		, 0, 0 },
+   { 0x5d, 0xff, ' ', 1, "TSTB"		, 0, 0 },
+
+   { 0x20, 0xff, 'b', 1, "BRA %b"	, 0, 0 },
+   { 0x21, 0xff, ' ', 1, "BRN %b"	, 0, 0 },
+   { 0x22, 0xff, 'b', 1, "BHI %b"	, 0, 0 },
+   { 0x23, 0xff, 'b', 1, "BLS %b"	, 0, 0 },
+   { 0x24, 0xff, 'b', 1, "BHS %b"	, 0, 0 },
+   { 0x25, 0xff, 'b', 1, "BLO %b"	, 0, 0 },
+   { 0x26, 0xff, 'b', 1, "BNE %b"	, 0, 0 },
+   { 0x27, 0xff, 'b', 1, "BEQ %b"	, 0, 0 },
+   { 0x28, 0xff, 'b', 1, "BVC %b"	, 0, 0 },
+   { 0x29, 0xff, 'b', 1, "BVS %b"	, 0, 0 },
+   { 0x2a, 0xff, 'b', 1, "BPL %b"	, 0, 0 },
+   { 0x2b, 0xff, 'b', 1, "BMI %b"	, 0, 0 },
+   { 0x2c, 0xff, 'b', 1, "BGE %b"	, 0, 0 },
+   { 0x2d, 0xff, 'b', 1, "BLT %b"	, 0, 0 },
+   { 0x2e, 0xff, 'b', 1, "BGT %b"	, 0, 0 },
+   { 0x2f, 0xff, 'b', 1, "BLE %b"	, 0, 0 },
+
+   { 0x8d, 0xff, 's', 1, "BSR %b"	, 0, 0 },
+   { 0xbd, 0xff, 's', 1, "JSR %j"	, 0, 0 },
+   { 0x8d, 0xcf, 's', 1, "JSR %b"	, 0, 0 },
+   
+   { 0x16, 0xff, ' ', 1, "LBRA %B"	, 0, 0 },
+   { 0x17, 0xff, ' ', 1, "LBSR %B"	, 0, 0 },
+
+   { 0x30, 0xff, ' ', 1, "LEAX %X"	, 0, 0 },
+   { 0x31, 0xff, ' ', 1, "LEAY %X"	, 0, 0 },
+   { 0x32, 0xff, ' ', 1, "LEAS %X"	, 0, 0 },
+   { 0x33, 0xff, ' ', 1, "LEAU %X"	, 0, 0 },
+
+   { 0x34, 0xff, ' ', 1, "PSHS %p"	, 0, 0 },
+   { 0x35, 0xff, ' ', 1, "PULS %p"	, 0, 0 },
+   { 0x36, 0xff, ' ', 1, "PSHU %P"	, 0, 0 },
+   { 0x37, 0xff, ' ', 1, "PULU %P"	, 0, 0 },
+   { 0x39, 0xff, 'x', 1, "RTS"		, 0, 0 },
+   { 0x3a, 0xff, ' ', 1, "ABX"		, 0, 0 },
+   { 0x3b, 0xff, 'x', 1, "RTI"		, 0, 0 },
+   { 0x3d, 0xff, ' ', 1, "MUL"		, 0, 0 },
+   { 0x3e, 0xff, 'x', 1, "RESET"	, 0, 0 },
+   
+   { 0x1c, 0xff, ' ', 1, "ANDCC %i"	, 0, 0 },
+   { 0x3c, 0xff, ' ', 1, "CWAI %i"	, 0, 0 },
+   { 0x1a, 0xff, ' ', 1, "ORCC %i"	, 0, 0 },
+
+   { 0x0e, 0xff, 'j', 1, "JMP %j"	, 0, 0 },
+   { 0x6e, 0xff, ' ', 1, "JMP %j"	, 0, 0 },
+   { 0x7e, 0xff, 'j', 1, "JMP %J"	, 0, 0 },
+   
+   { 0x1e, 0xff, ' ', 1, "EXG %r"	, 0, 0 },
+   { 0x1f, 0xff, ' ', 1, "TFR %r"	, 0, 0 },
+   
+   { 0x89, 0xcf, ' ', 1, "ADCA %u"	, 0, 0 },
+   { 0xc9, 0xcf, ' ', 1, "ADCB %u"	, 0, 0 },
+   { 0x8b, 0xcf, ' ', 1, "ADDA %u"	, 0, 0 },
+   { 0xcb, 0xcf, ' ', 1, "ADDB %u"	, 0, 0 },
+   { 0x84, 0xcf, ' ', 1, "ANDA %u"	, 0, 0 },
+   { 0xc4, 0xcf, ' ', 1, "ANDB %u"	, 0, 0 },
+   { 0x85, 0xcf, ' ', 1, "BITA %u"	, 0, 0 },
+   { 0xc5, 0xcf, ' ', 1, "BITB %u"	, 0, 0 },
+   { 0x81, 0xcf, ' ', 1, "CMPA %u"	, 0, 0 },
+   { 0xc1, 0xcf, ' ', 1, "CMPB %u"	, 0, 0 },
+   { 0x88, 0xcf, ' ', 1, "EORA %u"	, 0, 0 },
+   { 0xc8, 0xcf, ' ', 1, "EORB %u"	, 0, 0 },
+   { 0x86, 0xcf, ' ', 1, "LDA %u"	, 0, 0 },
+   { 0xc6, 0xcf, ' ', 1, "LDB %u"	, 0, 0 },
+   { 0x8a, 0xcf, ' ', 1, "ORA %u"	, 0, 0 },
+   { 0xca, 0xcf, ' ', 1, "ORB %u"	, 0, 0 },
+   { 0x82, 0xcf, ' ', 1, "SBCA %u"	, 0, 0 },
+   { 0xc2, 0xcf, ' ', 1, "SBCB %u"	, 0, 0 },
+   { 0x80, 0xcf, ' ', 1, "SUBA %u"	, 0, 0 },
+   { 0xc0, 0xcf, ' ', 1, "SUBB %u"	, 0, 0 },
+
+   { 0x87, 0xcf, ' ', 1, "STA %n"	, 0, 0 },
+   { 0xc7, 0xcf, ' ', 1, "STB %n"	, 0, 0 },
+
+   { 0xc3, 0xcf, ' ', 1, "ADDD %U"	, 0, 0 },
+   { 0xcc, 0xcf, ' ', 1, "LDD %U"	, 0, 0 },
+   { 0xce, 0xcf, ' ', 1, "LDU %U"	, 0, 0 },
+   { 0x8e, 0xcf, ' ', 1, "LDX %U"	, 0, 0 },
+   { 0x83, 0xcf, ' ', 1, "SUBD %U"	, 0, 0 },
+   { 0x8c, 0xcf, ' ', 1, "CMPX %U"	, 0, 0 },
+   
+   { 0xcd, 0xcf, ' ', 1, "STD %N"	, 0, 0 },
+   { 0x8f, 0xcf, ' ', 1, "STX %N"	, 0, 0 },
+   { 0xcf, 0xcf, ' ', 1, "STU %N"	, 0, 0 },
+   
+   { 0x00, 0xcf, ' ', 1, "NEG %n"	, 0, 0 },
+   { 0x60, 0x6f, ' ', 1, "NEG %n"	, 0, 0 },
+   { 0x03, 0xcf, ' ', 1, "COM %n"	, 0, 0 },
+   { 0x63, 0x6f, ' ', 1, "COM %n"	, 0, 0 },
+   { 0x04, 0xcf, ' ', 1, "LSR %n"	, 0, 0 },
+   { 0x64, 0x6f, ' ', 1, "LSR %n"	, 0, 0 },
+   { 0x06, 0xcf, ' ', 1, "ROR %n"	, 0, 0 },
+   { 0x66, 0x6f, ' ', 1, "ROR %n"	, 0, 0 },
+   { 0x07, 0xcf, ' ', 1, "ASR %n"	, 0, 0 },
+   { 0x67, 0x6f, ' ', 1, "ASR %n"	, 0, 0 },
+   { 0x08, 0xcf, ' ', 1, "ASL %n"	, 0, 0 },
+   { 0x68, 0x6f, ' ', 1, "ASL %n"	, 0, 0 },
+   { 0x09, 0xcf, ' ', 1, "ROL %n"	, 0, 0 }, 
+   { 0x69, 0x6f, ' ', 1, "ROL %n"	, 0, 0 }, 
+   { 0x0a, 0xcf, ' ', 1, "DEC %n"	, 0, 0 }, 
+   { 0x6a, 0x6f, ' ', 1, "DEC %n"	, 0, 0 }, 
+   { 0x0c, 0xcf, ' ', 1, "INC %n"	, 0, 0 }, 
+   { 0x6c, 0x6f, ' ', 1, "INC %n"	, 0, 0 }, 
+   { 0x0d, 0xcf, ' ', 1, "TST %n"	, 0, 0 },
+   { 0x6d, 0x6f, ' ', 1, "TST %n"	, 0, 0 },
+   { 0x0f, 0xcf, ' ', 1, "CLR %n"	, 0, 0 },
+   { 0x6f, 0x6f, ' ', 1, "CLR %n"	, 0, 0 },
+
+   { 0, 0, 0, 0, 0, 0 }
+  };
+
+struct dis_entry disass_m6809_10[]=
+  {
+   { 0x21, 0xff, ' ', 1, "LBRN %E"	, 0, 0 },
+   { 0x22, 0xff, 'b', 1, "LBHI %E"	, 0, 0 },
+   { 0x23, 0xff, 'b', 1, "LBLS %E"	, 0, 0 },
+   { 0x24, 0xff, 'b', 1, "LBCC %E"	, 0, 0 },
+   { 0x25, 0xff, 'b', 1, "LBCS %E"	, 0, 0 },
+   { 0x26, 0xff, 'b', 1, "LBNE %E"	, 0, 0 },
+   { 0x27, 0xff, 'b', 1, "LBEQ %E"	, 0, 0 },
+   { 0x28, 0xff, 'b', 1, "LBVC %E"	, 0, 0 },
+   { 0x29, 0xff, 'b', 1, "LBVS %E"	, 0, 0 },
+   { 0x2a, 0xff, 'b', 1, "LBPL %E"	, 0, 0 },
+   { 0x2b, 0xff, 'b', 1, "LBMI %E"	, 0, 0 },
+   { 0x2c, 0xff, 'b', 1, "LBGE %E"	, 0, 0 },
+   { 0x2d, 0xff, 'b', 1, "LBLT %E"	, 0, 0 },
+   { 0x2e, 0xff, 'b', 1, "LBGT %E"	, 0, 0 },
+   { 0x2f, 0xff, 'b', 1, "LBLE %E"	, 0, 0 },
+   { 0x83, 0xcf, ' ', 1, "CMPD %U"	, 0, 0 },
+   { 0x8c, 0xcf, ' ', 1, "CMPY %U"	, 0, 0 },
+   { 0xce, 0xcf, ' ', 1, "LDS %U"	, 0, 0 },
+   { 0x8e, 0xcf, ' ', 1, "LDY %U"	, 0, 0 },
+   { 0xcf, 0xcf, ' ', 1, "STS %U"	, 0, 0 },
+   { 0x8f, 0xcf, ' ', 1, "STY %U"	, 0, 0 },
+   
+   { 0x3f, 0xff, ' ', 1, "SWI2"		, 0, 0 },
+   
+   { 0, 0, 0, 0, 0, 0 }
+  };
+
+struct dis_entry disass_m6809_11[]=
+  {
+   { 0x83, 0xcf, ' ', 1, "CMPU %U"	, 0, 0 },
+   { 0x8c, 0xcf, ' ', 1, "CMPS %U"	, 0, 0 },
+   
+   { 0x3f, 0xff, ' ', 1, "SWI3"		, 0, 0 },
+
+   { 0, 0, 0, 0, 0, 0 }
+  };
+
+/* End of m6809.src/glob.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m6809.src/glob.h sdcc-4.2.0+dfsg/sim/ucsim/m6809.src/glob.h
--- sdcc-4.0.0+dfsg/sim/ucsim/m6809.src/glob.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m6809.src/glob.h	2020-09-17 19:59:38.000000000 +0000
@@ -0,0 +1,41 @@
+/*
+ * Simulator of microcontrollers (glob.h)
+ *
+ * Copyright (C) 2020,20 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef GLOB_HEADER
+#define GLOB_HEADER
+
+#include "stypes.h"
+
+
+extern struct dis_entry disass_m6809[];
+extern struct dis_entry disass_m6809_10[];
+extern struct dis_entry disass_m6809_11[];
+
+
+#endif
+
+/* End of m6809.src/glob.h */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m6809.src/irq.cc sdcc-4.2.0+dfsg/sim/ucsim/m6809.src/irq.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/m6809.src/irq.cc	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m6809.src/irq.cc	2021-05-20 07:49:29.000000000 +0000
@@ -0,0 +1,170 @@
+/*
+ * Simulator of microcontrollers (irq.cc)
+ *
+ * Copyright (C) 2020,20 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#include "globals.h"
+#include "utils.h"
+
+#include "m6809cl.h"
+
+#include "irqcl.h"
+
+
+/* CPU interrupt handling */
+
+/*
+ * peripheral to handle CPU interrupts
+ */
+
+cl_m6809_irq::cl_m6809_irq(class cl_uc *auc):
+  cl_hw(auc, HW_INTERRUPT, 0, "irq")
+{
+  muc= (class cl_m6809 *)auc;
+}
+
+int
+cl_m6809_irq::init()
+{
+  class cl_var *v;
+
+  cl_hw::init();
+  uc->vars->add(v= new cl_var("NMI", cfg, cpu_nmi, "NMI request/clear"));
+  v->init();
+  uc->vars->add(v= new cl_var("IRQ", cfg, cpu_irq, "IRQ request/clear"));
+  v->init();
+  uc->vars->add(v= new cl_var("FIRQ", cfg, cpu_firq, "FIRQ request/clear"));
+  v->init();
+
+  return 0;
+}
+
+void
+cl_m6809_irq::reset(void)
+{
+  cfg_set(cpu_nmi, 0);
+  cfg_set(cpu_irq, 0);
+  cfg_set(cpu_firq, 0);
+  cfg_read(cpu_nmi_en);
+  cfg_read(cpu_irq_en);
+  cfg_read(cpu_firq_en);
+}
+
+const char *
+cl_m6809_irq::cfg_help(t_addr addr)
+{
+  switch (addr)
+    {
+    case cpu_nmi_en	: return "NMI enable (RO)";
+    case cpu_nmi	: return "NMI request/clear (RW)";
+    case cpu_irq_en	: return "IRQ enable (RO)";
+    case cpu_irq	: return "IRQ request/clear (RW)";
+    case cpu_firq_en	: return "FIRQ enable (RO)";
+    case cpu_firq	: return "FIRQ request/clear (RW)";
+    }
+  return cl_hw::cfg_help(addr);
+}
+
+t_mem
+cl_m6809_irq::conf_op(cl_memory_cell *cell, t_addr addr, t_mem *val)
+{
+  class cl_m6809 *muc= (class cl_m6809 *)uc;
+  switch ((enum cpu_cfg)addr)
+    {
+    case cpu_nmi_en:
+      cell->set(muc->en_nmi?1:0);
+      break;
+    case cpu_nmi:
+      if (val)
+	{
+	  if (*val)
+	    *val= 1;
+	}
+      break;
+    case cpu_irq_en:
+      cell->set((muc->reg.CC & flagI)?0:1);
+      break;
+    case cpu_irq:
+      if (val)
+	{
+	  if (*val)
+	    *val= 1;
+	}
+      break;
+    case cpu_firq_en:
+      cell->set((muc->reg.CC & flagF)?0:1);
+      break;
+    case cpu_firq:
+      if (val)
+	{
+	  if (*val)
+	    *val= 1;
+	}
+      break;
+    case cpu_nr: break;
+    }
+  return cell->get();
+}
+
+void
+cl_m6809_irq::print_info(class cl_console_base *con)
+{
+  int i;
+  con->dd_printf("  Handler  ISR    En  Pr Req Act Name\n");
+  for (i= 0; i < uc->it_sources->count; i++)
+    {
+      class cl_it_src *is=
+	(class cl_it_src *)(uc->it_sources->at(i));
+      class cl_it_src *pa= is->get_parent();
+      class cl_it_src *isp= (pa)?pa:is;
+      t_addr a= uc->rom->get(isp->addr) * 256 + uc->rom->get(isp->addr+1);
+      con->dd_printf("  [0x%04x] 0x%04x", AU(isp->addr), a);
+      con->dd_printf(" %-3s", (is->enabled())?"en":"dis");
+      con->dd_printf(" %2d", uc->priority_of(is->nuof));
+      con->dd_printf(" %-3s", (is->pending())?"YES":"no");
+      con->dd_printf(" %-3s", (is->active)?"act":"no");
+      con->dd_printf(" %s", object_name(is));
+      con->dd_printf("\n");
+    }
+  con->dd_printf("Active interrupt service(s):\n");
+  con->dd_printf("  Pr Handler  PC       Source\n");
+  for (i= 0; i < uc->it_levels->count; i++)
+    {
+      class it_level *il= (class it_level *)(uc->it_levels->at(i));
+      if (il->level >= 0)
+	{
+	  con->dd_printf("  %2d", il->level);
+	  con->dd_printf(" 0x%06x", AU(il->addr));
+	  con->dd_printf(" 0x%06x", AU(il->PC));
+	  con->dd_printf(" %s", (il->source)?(object_name(il->source)):
+			 "nothing");
+	  con->dd_printf("\n");
+	}
+    }
+  //print_cfg_info(con);
+}
+
+
+/* End of m6809.src/irq.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m6809.src/irqcl.h sdcc-4.2.0+dfsg/sim/ucsim/m6809.src/irqcl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/m6809.src/irqcl.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m6809.src/irqcl.h	2021-10-29 17:39:15.000000000 +0000
@@ -0,0 +1,71 @@
+/*
+ * Simulator of microcontrollers (irqcl.h)
+ *
+ * Copyright (C) 2020,20 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef IRQ_HEADER
+#define IRQ_HEADER
+
+#include "hwcl.h"
+#include "itsrccl.h"
+
+
+enum cpu_cfg
+  {
+   cpu_nmi_en	= 0,
+   cpu_nmi	= 1,
+   cpu_irq_en	= 2,
+   cpu_irq	= 3,
+   cpu_firq_en	= 4,
+   cpu_firq	= 5,
+   cpu_nr	= 6
+  };
+
+enum {
+  FIRQ_AT	= 0xfff6,
+  IRQ_AT	= 0xfff8,
+  NMI_AT	= 0xfffc
+};
+
+
+// Interrupt peripheral
+class cl_m6809_irq: public cl_hw
+{
+public:
+  class cl_m6809 *muc;
+public:
+  cl_m6809_irq(class cl_uc *auc);
+  virtual int init(void);
+  virtual unsigned int cfg_size(void) { return cpu_nr; }
+  virtual const char *cfg_help(t_addr addr);
+  virtual void reset(void);
+  virtual t_mem conf_op(cl_memory_cell *cell, t_addr addr, t_mem *val);
+  virtual void print_info(class cl_console_base *con);  
+};
+
+
+#endif
+
+/* End of m6809.src/irqcl.h */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m6809.src/m6809.cc sdcc-4.2.0+dfsg/sim/ucsim/m6809.src/m6809.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/m6809.src/m6809.cc	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m6809.src/m6809.cc	2022-01-24 11:09:43.000000000 +0000
@@ -0,0 +1,2545 @@
+/*
+ * Simulator of microcontrollers (m6809.cc)
+ *
+ * Copyright (C) 2020,20 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#include 
+#include 
+
+#include "globals.h"
+#include "utils.h"
+
+#include "dregcl.h"
+#include "ciacl.h"
+#include "piacl.h"
+
+#include "glob.h"
+#include "irqcl.h"
+
+#include "m6809cl.h"
+
+
+cl_m6809::cl_m6809(class cl_sim *asim):
+  cl_uc(asim)
+{
+}
+
+int
+cl_m6809::init(void)
+{
+  cl_uc::init();
+
+  set_xtal(1000000);
+  
+  reg8_ptr[0]= &A;
+  reg8_ptr[1]= &B;
+  reg8_ptr[2]= &(reg.CC);
+  reg8_ptr[3]= &(reg.DP);
+  reg8_ptr[4]= &A;
+  reg8_ptr[5]= &A;
+  reg8_ptr[6]= &A;
+  reg8_ptr[7]= &A;
+
+  reg16_ptr[0]= &D;
+  reg16_ptr[1]= &(reg.X);
+  reg16_ptr[2]= &(reg.Y);
+  reg16_ptr[3]= &(reg.U);
+  reg16_ptr[4]= &(reg.S);
+  reg16_ptr[5]= NULL;
+  reg16_ptr[6]= &D;
+  reg16_ptr[7]= &D;
+  
+  return 0;
+}
+
+const char *
+cl_m6809::id_string(void)
+{
+  return "M6809";
+}
+
+void
+cl_m6809::reset(void)
+{
+  cl_uc::reset();
+
+  reg.DP= 0;
+  en_nmi= false;
+  cwai= false;
+  reg.CC= flagI | flagF;
+  PC= rom->read(0xfffe)*256 + rom->read(0xffff);
+  tick(6);
+}
+  
+void
+cl_m6809::set_PC(t_addr addr)
+{
+  PC= addr;
+}
+
+void
+cl_m6809::mk_hw_elements(void)
+{
+  class cl_hw *h;
+  class cl_option *o;
+  cl_uc::mk_hw_elements();
+
+  if ((o= application->options->get_option("serial0_in_file")) == NULL)
+    {
+      o= new cl_string_option(this, "serial0_in_file",
+			      "Input file for serial line uart0 (-S)");
+      application->options->new_option(o);
+      o->init();
+      o->hide();
+    }
+  if ((o= application->options->get_option("serial0_out_file")) == NULL)
+    {
+      o= new cl_string_option(this, "serial0_out_file",
+			      "Output file for serial line uart0 (-S)");
+      application->options->new_option(o);
+      o->init();
+      o->hide();
+    }
+
+
+  if ((o= application->options->get_option("serial1_in_file")) == NULL)
+    {
+      o= new cl_string_option(this, "serial1_in_file",
+			      "Input file for serial line uart1 (-S)");
+      application->options->new_option(o);
+      o->init();
+      o->hide();
+    }
+  if ((o= application->options->get_option("serial1_out_file")) == NULL)
+    {
+      o= new cl_string_option(this, "serial1_out_file",
+			      "Output file for serial line uart1 (-S)");
+      application->options->new_option(o);
+      o->init();
+      o->hide();
+    }
+
+  add_hw(h= new cl_dreg(this, 0, "dreg"));
+  h->init();
+  
+  add_hw(h= new cl_m6809_irq(this));
+  h->init();
+
+  src_irq= new cl_it_src(this,
+			 irq_irq,
+			 regs8->get_cell(3), flagI,
+			 h->cfg_cell(cpu_irq), 1,
+			 IRQ_AT,
+			 false,
+			 true,
+			 "Interrupt request",
+			 0);
+  src_irq->set_cid('i');
+  src_irq->set_ie_value(0);
+  src_irq->init();
+  it_sources->add(src_irq);
+  
+  src_firq= new cl_it_src(this,
+			  irq_firq,
+			  regs8->get_cell(3), flagF,
+			  h->cfg_cell(cpu_firq), 1,
+			  FIRQ_AT,
+			  false,
+			  true,
+			  "Fast interrupt request",
+			  0);
+  src_firq->set_cid('f');
+  src_firq->init();
+  it_sources->add(src_firq);
+  
+  src_nmi= new cl_it_src(this,
+			 irq_nmi,
+			 h->cfg_cell(cpu_nmi_en), 1,
+			 h->cfg_cell(cpu_nmi), 1,
+			 NMI_AT,
+			 false,
+			 true,
+			 "Non-maskable interrupt request",
+			 0);
+  src_nmi->set_cid('n');
+  src_nmi->set_nmi(true);
+  src_nmi->init();
+  it_sources->add(src_nmi);
+  
+  add_hw(h= new cl_cia(this, 0, 0xc000));
+  h->init();
+
+  add_hw(h= new cl_cia(this, 1, 0xc008));
+  h->init();
+
+  class cl_pia *p0, *p1;
+  
+  add_hw(p0= new cl_pia(this, 0, 0xc010));
+  p0->init();
+  add_hw(p1= new cl_pia(this, 1, 0xc020));
+  p1->init();
+
+  class cl_port_ui *d;
+  add_hw(d= new cl_port_ui(this, 0, "dport"));
+  d->init();
+
+  class cl_port_data pd;
+  pd.init();
+  pd.set_name("P0A");
+  pd.cell_dir= p0->ddra;
+  pd.cell_p  = p0->ora;
+  pd.cell_in = p0->ina;
+  pd.keyset  = keysets[0];
+  pd.basx    = 1;
+  pd.basy    = 5;
+  d->add_port(&pd, 0);
+
+  pd.set_name("P0B");
+  pd.cell_dir= p0->ddrb;
+  pd.cell_p  = p0->orb;
+  pd.cell_in = p0->inb;
+  pd.keyset  = keysets[1];
+  pd.basx    = 20;
+  pd.basy    = 5;
+  d->add_port(&pd, 1);
+
+  pd.set_name("P0CA");
+  pd.cell_dir= p0->ddca;
+  pd.cell_p  = p0->oca;
+  pd.cell_in = p0->inca;
+  pd.cell_dir= p0->ddca;
+  pd.keyset  = keysets[2];
+  pd.basx    = 40;
+  pd.basy    = 5;
+  pd.width   = 2;
+  d->add_port(&pd, 2);
+
+  pd.set_name("P0CB");
+  pd.cell_dir= p0->ddcb;
+  pd.cell_p  = p0->ocb;
+  pd.cell_in = p0->incb;
+  pd.cell_dir= p0->ddcb;
+  pd.keyset  = keysets[3];
+  pd.basx    = 54;
+  pd.basy    = 5;
+  pd.width   = 2;
+  d->add_port(&pd, 3);
+
+  // Port #1
+  pd.init();
+  pd.set_name("P1A");
+  pd.cell_dir= p1->ddra;
+  pd.cell_p  = p1->ora;
+  pd.cell_in = p1->ina;
+  pd.keyset  = keysets[4];
+  pd.basx    = 1;
+  pd.basy    = 11;
+  d->add_port(&pd, 4);
+
+  pd.set_name("P1B");
+  pd.cell_dir= p1->ddrb;
+  pd.cell_p  = p1->orb;
+  pd.cell_in = p1->inb;
+  pd.keyset  = keysets[5];
+  pd.basx    = 20;
+  pd.basy    = 11;
+  d->add_port(&pd, 5);
+
+  pd.set_name("P1CA");
+  pd.cell_dir= p1->ddca;
+  pd.cell_p  = p1->oca;
+  pd.cell_in = p1->inca;
+  pd.cell_dir= p1->ddca;
+  pd.keyset  = keysets[6];
+  pd.basx    = 40;
+  pd.basy    = 11;
+  pd.width   = 2;
+  d->add_port(&pd, 6);
+
+  pd.set_name("P1CB");
+  pd.cell_dir= p1->ddcb;
+  pd.cell_p  = p1->ocb;
+  pd.cell_in = p1->incb;
+  pd.cell_dir= p1->ddcb;
+  pd.keyset  = keysets[7];
+  pd.basx    = 54;
+  pd.basy    = 11;
+  pd.width   = 2;
+  d->add_port(&pd, 7);
+}
+
+void
+cl_m6809::make_cpu_hw(void)
+{
+}
+
+void
+cl_m6809::make_memories(void)
+{
+  class cl_address_space *as;
+  
+  rom= as= new cl_address_space("rom"/*MEM_ROM_ID*/, 0, 0x10000, 8);
+  as->init();
+  address_spaces->add(as);
+
+  class cl_address_decoder *ad;
+  class cl_memory_chip *chip;
+
+  chip= new cl_chip8("rom_chip", 0x10000, 8);
+  chip->init();
+  memchips->add(chip);
+  ad= new cl_address_decoder(as= rom/*address_space(MEM_ROM_ID)*/,
+			     chip, 0, 0xffff, 0);
+  ad->init();
+  as->decoders->add(ad);
+  ad->activate(0);
+
+  regs8= new cl_address_space("regs8", 0, 4, 8);
+  regs8->init();
+  address_spaces->add(regs8);
+  regs8->get_cell(0)->decode((t_mem*)&(reg.acc.a8.rA));
+  regs8->get_cell(1)->decode((t_mem*)&(reg.acc.a8.rB));
+  regs8->get_cell(2)->decode((t_mem*)&(reg.DP));
+  regs8->get_cell(3)->decode((t_mem*)&(reg.CC));
+
+  regs16= new cl_address_space("regs16", 0, 5, 16);
+  regs16->init();
+  address_spaces->add(regs16);
+  regs16->get_cell(0)->decode((t_mem*)&(reg.U));
+  regs16->get_cell(1)->decode((t_mem*)&(reg.S));
+  regs16->get_cell(2)->decode((t_mem*)&(reg.X));
+  regs16->get_cell(3)->decode((t_mem*)&(reg.Y));
+  regs16->get_cell(4)->decode((t_mem*)&(reg.acc.rD));
+
+  vars->add("A", regs8, 0, 7, 0, "CPU register A");
+  vars->add("B", regs8, 1, 7, 0, "CPU register B");
+  vars->add("DP", regs8, 2, 7, 0, "CPU register DP");
+  vars->add("CC", regs8, 3, 7, 0, "CPU register CC");
+
+  vars->add("U", regs16, 0, 15, 0, "CPU register U");
+  vars->add("S", regs16, 1, 15, 0, "CPU register S");
+  vars->add("X", regs16, 2, 15, 0, "CPU register X");
+  vars->add("Y", regs16, 3, 15, 0, "CPU register Y");
+  vars->add("D", regs16, 4, 15, 0, "CPU register D");
+}
+
+
+void
+cl_m6809::analyze_start(void)
+{
+  struct {
+    const char *name;
+    t_addr vector, addr;
+  } vectors[] = {
+    { ".reset", 0xfffe },
+    { ".nmi",   0xfffc },
+    { ".swi",   0xfffa },
+    { ".irq",   0xfff8 },
+    { ".firq",  0xfff6 },
+    { ".swi2",  0xfff4 },
+    { ".swi3",  0xfff2 },
+  };
+
+  for (size_t i = 0; i < sizeof(vectors) / sizeof(vectors[0]); i++)
+    {
+      vectors[i].addr = rom->read(vectors[i].vector) * 256 + rom->read(vectors[i].vector + 1);
+      class cl_var *v = new cl_var(vectors[i].name, rom, vectors[i].addr, chars("Auto-generated by analyze"), -1, -1);
+      v->init();
+      vars->add(v);
+    }
+
+  for (size_t i = 0; i < sizeof(vectors) / sizeof(vectors[0]); i++)
+    analyze(vectors[i].addr);
+}
+
+
+void
+cl_m6809::analyze(t_addr addr)
+{
+  struct dis_entry *tt, *di;
+  t_addr code;
+
+  code= rom->get(addr);
+  if (code == 0x10)
+    {
+      tt= disass_m6809_10;
+      code= rom->get(++addr);
+    }
+  else if (code == 0x11)
+    {
+      tt= disass_m6809_11;
+      code= rom->get(++addr);
+    }
+  else
+    tt= disass_m6809;
+  addr++;
+
+  for (di= tt; (code & di->mask) != di->code && di->mnemonic; di++);
+
+  while (!inst_at(addr) && di && (di->mnemonic!=NULL))
+    {
+      set_inst_at(addr);
+
+      if (di->branch != ' ')
+        {
+          t_addr target= addr;
+          char branch = di->branch;
+
+          switch (di->branch)
+            {
+              case 'x': // Returns or indirect jumps that end this execution path immediately
+                return;
+
+              case 'j': // Unconditional jumps
+              case 's': // Subroutine calls
+                    switch (code & 0x30)
+                      {
+                      case 0x00: // relative (BSR)
+                        target= rom->validate_address(addr + (i8_t)rom->get(addr));
+                        break;
+                      case 0x10: // direct
+                        target= rom->get(addr);
+                        break;
+                      case 0x20: // indexed
+                        return;
+                      case 0x30: // extended
+                        target= rom->get(addr)*256 + rom->get(addr+1);
+			addr+= 2;
+                        break;
+                      }
+                    break;
+
+              case 'b': // Conditional branches
+              case 'V':
+              case 'v':
+              case 'B': // Unconditional branches
+                if (tt == disass_m6809)
+                  {
+		    target= rom->validate_address(addr + (i8_t)rom->get(addr));
+		    addr++;
+		  }
+                else
+                  {
+		    target= rom->validate_address(addr + (i16_t)(rom->get(addr)*256 + rom->get(addr+1)));
+		    branch = 'b';
+		    addr+= 2;
+		  }
+                break;
+
+              default:
+                return;
+            }
+
+          analyze_jump(addr, target, branch);
+
+          // Unconditional jumps end this execution path
+          if (di->branch == 'j' || di->branch == 'B')
+            break;
+        }
+
+      addr= rom->validate_address(addr + di->length);
+    }
+}
+
+
+struct dis_entry *
+cl_m6809::dis_tbl(void)
+{
+  return(disass_m6809);
+}
+
+const char *idx_reg_name[4]=
+  {
+   "X",
+   "Y",
+   "U",
+   "S"
+  };
+
+void
+cl_m6809::disass_indexed(t_addr *addr, chars *work, int siz)
+{
+  t_addr a= *addr;
+  u8_t idx= rom->get(a++);
+  int r= (idx&0x60) >> 5;
+  chars w= "";
+  i8_t i8;
+  i16_t off;
+  u16_t u16;
+  
+  if ((idx & 0x80) == 0)
+    {
+      off= idx & 0x1f;
+      if (idx & 0x10) off|= 0xfff0;
+      work->appendf("%+d,%s", off, idx_reg_name[r]);		    
+    }
+  else
+    {
+      switch (idx & 0x0f)
+	{
+	case 0x00:
+	  work->appendf(",%s+", idx_reg_name[r]);
+	  break;
+	case 0x01:
+	  w.format(",%s++", idx_reg_name[r]);
+	  break;
+	case 0x02:
+	  work->appendf(",-%s", idx_reg_name[r]);
+	  break;
+	case 0x03:
+	  w.format(",--%s", idx_reg_name[r]);
+	  break;
+	case 0x04:
+	  w.format(",%s", idx_reg_name[r]);
+	  break;
+	case 0x05:
+	  w.format("B,%s", idx_reg_name[r]);
+	  break;
+	case 0x06:
+	  w.format("A,%s", idx_reg_name[r]);
+	  break;
+	case 0x08:
+	  i8= rom->get(a++);
+	  off= i8;
+	  w.format("%+d,%s", off, idx_reg_name[r]);
+	  break;
+	case 0x09:
+	  i8= rom->get(a++);
+	  off= i8*256 + rom->get(a++);
+	  w.format("%+d,%s", off, idx_reg_name[r]);
+	  break;
+	case 0x0b:
+	  w.format("D,%s", idx_reg_name[r]);
+	  break;
+	case 0x0c:
+	  i8= rom->get(a++);
+	  off= i8;
+	  w.format("%+d,PC", off);
+	  break;
+	case 0x0d:
+	  i8= rom->get(a++);
+	  off= i8*256 + rom->get(a++);
+	  w.format("%+d,PC", off);
+	  break;
+	case 0x0f:
+	  u16= rom->get(a++)*256;
+	  u16+= rom->get(a++);
+	  if ((idx & 0x10) == 0)
+	    work->append("??");
+	  else
+	    w.format("$%04x", u16);
+	  break;
+	default:
+	  work->append("??");
+	  break;
+	}
+      if (w.nempty())
+	{
+	  if (idx & 0x10)
+	    work->appendf("[%s]", w.c_str());
+	  else
+	    work->append(w);
+	}
+    }
+  *addr= a;
+}
+
+void
+cl_m6809::disass_immediate(t_addr *addr, chars *work, int siz)
+{
+  t_addr a= *addr;
+  //work+= 'm';
+  u8_t op8= rom->get(a++);
+  if (siz==1)
+    work->appendf("#$%02x", op8);
+  else
+    {
+      u16_t op16= op8*256 + rom->get(a++);
+      work->appendf("#$%04x", op16);
+    }
+  *addr= a;
+}
+
+const char *reg_names[16]=
+  {
+   /* 0*/ "D",
+   /* 1*/ "X",
+   /* 2*/ "Y",
+   /* 3*/ "U",
+   /* 4*/ "S",
+   /* 5*/ "PC",
+   /* 6*/ "?",
+   /* 7*/ "?",
+   /* 8*/ "A",
+   /* 9*/ "B",
+   /*10*/ "CC",
+   /*11*/ "DP",
+   /*12*/ "?",
+   /*13*/ "?",
+   /*14*/ "?",
+   /*15*/ "?"
+  };
+   
+char *
+cl_m6809::disass(t_addr addr)
+{
+  chars work= chars(), temp= chars();
+  const char *b;
+  t_mem code;
+  int i, j;
+  struct dis_entry *tt;
+  u8_t op8;
+  i8_t i8;
+  i16_t i16;
+  u16_t op16;
+  //t_addr ea;
+  bool first;
+  int siz;
+
+  //work= "";
+  //p= (char*)work;
+
+  code= rom->get(addr);
+  if (code == 0x10)
+    {
+      tt= disass_m6809_10;
+      code= rom->get(++addr);
+    }
+  else if (code == 0x11)
+    {
+      tt= disass_m6809_11;
+      code= rom->get(++addr);
+    }
+  else
+    tt= disass_m6809;
+  addr++;
+  
+  i= 0;
+  while ((code & tt[i].mask) != tt[i].code &&
+	 tt[i].mnemonic)
+    {
+      //printf("code=%02x mask=%02x MSKED=%02x ? tt[code]=%02x\n",code,tt[i].mask,code&tt[i].mask,tt[i].code);
+      i++;
+    }
+  if (tt[i].mnemonic == NULL)
+    {
+      return strdup("-- UNKNOWN/INVALID");
+    }
+  b= tt[i].mnemonic;
+
+  work= "";
+  first= true;
+  for (j= 0; b[j]; j++)
+    {
+      if (b[j] == ' ')
+	{
+	  if (first)
+	    {
+	      first= false;
+	      while (work.len() < 7) work.append(' ');
+	    }
+	  else
+	    work+= ' ';
+	}
+      else if (b[j] == '%')
+	{
+	  j++;
+	  switch (b[j])
+	    {
+	    case 'u': case 'U': case 'n': case 'N':
+	      {
+		u8_t mode= code & 0x30;
+		siz= (islower(b[j]))?1:2;
+		switch (mode)
+		  {
+		  case 0x00: // immed
+		    if (toupper(b[j])=='N')
+		      work.append("??");
+		    else
+		      disass_immediate(&addr, &work, siz);
+		    break;
+		  case 0x10: // direct
+		    //work+= 'd';
+		    op8= rom->get(addr++);
+		    work.appendf("DP:$%02x", op8);
+		    break;
+		  case 0x20: // index
+		    //work+= 'i';
+		    disass_indexed(&addr, &work, siz);
+		    break;
+		  case 0x30: // extend
+		    //work+= 'e';
+		    op16= rom->get(addr++)*256;
+		    op16+= rom->get(addr++);
+		    work.appendf("$%04x", op16);
+		    addr_name(op16, rom, &work);
+		    break;
+		  }
+		break;
+	      }
+	    case 'j': case 'J':
+	      {
+		u8_t mode= code & 0x30;
+		switch (mode)
+		  {
+		  case 0x00: // direct (JMP)
+		  case 0x10: // direct (JSR)
+		    op8= rom->get(addr++);
+		    work.appendf("DP:$%02x", op8);
+		    break;
+		  case 0x20: // indexed
+		    disass_indexed(&addr, &work, 1/*siz*/);
+		    break;
+		  case 0x30: // extended
+		    op16= rom->get(addr++)*256;
+		    op16+= rom->get(addr++);
+		    work.appendf("$%04x", op16);
+		    addr_name(op16, rom, &work);
+		    break;
+		  }
+		break;
+	      }
+	    case 'x': case 'X':
+	      {
+		siz= (islower(b[j]))?1:2;
+		disass_indexed(&addr, &work, siz);
+		break;
+	      }
+	    case 'i':
+	      {
+		siz= (islower(b[j]))?1:2;
+		disass_immediate(&addr, &work, siz);
+		break;
+	      }
+	    case 'b': case 'B':
+	      {
+		siz= (islower(b[j]))?1:2;
+		if (siz==1)
+		  {
+		    i8= rom->get(addr++);
+		    i16= i8;
+		  }
+		else
+		  {
+		    i16= rom->get(addr++)*256;
+		    i16+= rom->get(addr++);
+		  }
+		i16= (i16 + addr) & 0xffff;
+		work.appendf("$%04x", i16);
+		addr_name(i16, rom, &work);
+		break;
+	      }
+	    case 'p': case 'P':
+	      { 
+		chars r= "";
+		op8= rom->get(addr++);
+		if (op8 & 0x80) (r.nempty()?(r+=','):r),r+="PC";
+		if (op8 & 0x40) (r.nempty()?(r+=','):r),r+=((b[j]=='p')?"U":"S");
+		if (op8 & 0x20) (r.nempty()?(r+=','):r),r+="Y";
+		if (op8 & 0x10) (r.nempty()?(r+=','):r),r+="X";
+		if (op8 & 0x08) (r.nempty()?(r+=','):r),r+="DP";
+		if (op8 & 0x04) (r.nempty()?(r+=','):r),r+="B";
+		if (op8 & 0x02) (r.nempty()?(r+=','):r),r+="A";
+		if (op8 & 0x01) (r.nempty()?(r+=','):r),r+="CC";
+		work.append(r);
+		break;
+	      }
+	    case 'r':
+	      {
+		op8= rom->get(addr++);
+		u8_t s= op8>>4;
+		u8_t d= op8&0xf;
+		work.appendf("%s,%s", reg_names[s], reg_names[d]);
+		if ((s^d)&0x8)
+		  work+= "-??";
+		break;
+	      }
+	    case 'e': case 'E':
+	      op16= rom->get(addr++);
+	      if (op16 & 0x80)
+		op16|= 0xff00;
+	      if (b[j]=='E')
+		op16= op16*256 + rom->get(addr++);
+	      op16= (addr + op16)&0xffff;
+	      work.appendf("$%04x", op16);
+	      addr_name(op16, rom, &work);
+	      break;
+	    }
+	}
+      else
+	{
+	  work+= b[j];
+	}
+    }
+  
+  return strdup(work.c_str());
+}
+
+void
+cl_m6809::print_regs(class cl_console_base *con)
+{
+  con->dd_color("answer");
+  con->dd_printf("A= $%02x %3d %+4d %c  ", A, A, (i8_t)A, isprint(A)?A:'.');
+  con->dd_printf("B= $%02x %3d %+4d %c  ", B, B, (i8_t)B, isprint(B)?B:'.');
+  con->dd_printf("D= $%04x %5d %+6d\n", D, D, (i16_t)D);
+  con->dd_printf("CC= "); con->print_bin(reg.CC, 8); con->dd_printf("\n");
+  con->dd_printf("    EFHINZVC\n");
+
+  con->dd_printf("DP= $%02x\n", reg.DP);
+
+  con->dd_printf("X= ");
+  rom->dump(0, reg.X, reg.X+7, 8, con);
+  con->dd_color("answer");
+  
+  con->dd_printf("Y= ");
+  rom->dump(0, reg.Y, reg.Y+7, 8, con);
+  con->dd_color("answer");
+  
+  con->dd_printf("S= ");
+  rom->dump(0, reg.S, reg.S+7, 8, con);
+  con->dd_color("answer");
+  
+  con->dd_printf("U= ");
+  rom->dump(0, reg.U, reg.U+7, 8, con);
+  con->dd_color("answer");
+  
+  print_disass(PC, con);
+}
+
+int
+cl_m6809::indexed_length(t_addr addr)
+{
+  u8_t idx= rom->get(addr+1);
+  if ((idx&0x80)!=0)
+    {
+      u8_t il= idx&0xf;
+      if (il==8||il==12)
+	return 3;
+      if (il==9||il==13||il==15)
+	return 4;
+    }
+  return 2;
+}
+
+int
+cl_m6809::inst_length(t_addr addr)
+{
+  u8_t code= rom->get(addr);
+  u8_t ch, cl;
+  int ret= 1;
+  ch= code>>4;
+  cl= code&0xf;
+  if (code == 0x10)
+    {
+      ret= 2;
+      code= rom->get(addr+1);
+      ch= code>>4;
+      cl= code&0xf;
+      int aml= 1;
+      switch (code & 0x30)
+	{
+	case 0x00: aml= 1+1; break; // immed
+	case 0x10: aml= 1; break; // direct
+	case 0x20: aml= indexed_length(addr+1); break;// index
+	case 0x30: aml= 2; // extend
+	}
+      ret+= aml;
+    }
+  else if (code == 0x11)
+    {
+      ret= 2;
+      code= rom->get(addr+1);
+      if (code==0x3f) return ret;
+      int aml= 1;
+      switch (code & 0x30)
+	{
+	case 0x00: aml= 1+1; break; // immed
+	case 0x10: aml= 1; break; // direct
+	case 0x20: aml= indexed_length(addr+1); break;// index
+	case 0x30: aml= 2; // extend
+	}
+      ret+= aml;
+    }
+  else if (code & 0x80)
+    {
+      // HIGH HALF
+      switch (code & 0x30)
+	{
+	case 0x00: // immed
+	  if (cl==3||cl==12||cl==14)
+	    return 3;
+	  return 2;
+	  break;
+	case 0x10: // direct
+	  return 2;
+	  break;
+	case 0x20: // index
+	  return indexed_length(addr);
+	  break;
+	case 0x30: // extend
+	  return 3;
+	  break;
+	}
+    }
+  else
+    {
+      // LOW HALF
+      if (ch==0) return 2; // direct
+      if (ch==1)
+	{
+	  if (cl==6||cl==7) return 3;
+	  if (cl==10||cl==12||cl==13||cl==15) return 2;
+	}
+      if (ch==2) return 2;
+      if (ch==3)
+	{
+	  if (cl < 4) return indexed_length(addr);
+	  if (cl < 8) return 2;
+	}
+      if (ch==6) return indexed_length(addr);
+      if (ch==7) return 3; // extend
+    }
+  return ret;
+}
+
+int
+cl_m6809::index2ea(u8_t idx, t_addr *res_ea)
+{
+  u16_t iv;
+  i16_t off;
+  u16_t *ir= ®.X;
+  t_addr ea= 0;
+
+  switch (idx & 0x60)
+    {
+    case 0x00: ir= ®.X; break;
+    case 0x20: ir= ®.Y; break;
+    case 0x40: ir= ®.U; break;
+    case 0x60: ir= ®.S; break;
+    }
+  iv= *ir;
+  if (!(idx & 0x80))
+    {
+      idx&= 0x1f;
+      off= (idx & 0x10)? (0xffe0 | idx) : (idx);
+      ea= iv + off;
+    }
+  else
+    {
+      i8_t i8;
+      bool ind= true;
+      switch (idx & 0xf)
+	{
+	case 0x00:
+	  if (idx & 0x10) return resINV_INST;
+	  off= 0;
+	  ea= iv;
+	  (*ir)++;
+	  ind= false;
+	  break;
+	case 0x01:
+	  off= 0;
+	  ea= iv;
+	  (*ir)+= 2;
+	  break;
+	case 0x02:
+	  if (idx & 0x10) return resINV_INST;
+	  off= 0;
+	  (*ir)--;
+	  iv= *ir;
+	  ea= iv;
+	  ind= false;
+	  break;
+	case 0x03:
+	  off= 0;
+	  (*ir)-= 2;
+	  iv= *ir;
+	  ea= iv;
+	  break;
+	case 0x04:
+	  off= 0;
+	  ea= iv;
+	  break;
+	case 0x05:
+	  off= (i8_t)B;
+	  ea= iv + off;
+	  break;
+	case 0x06:
+	  off= (i8_t)A;
+	  ea= iv + off;
+	  break;
+	case 0x07:
+	  return resINV_INST;
+	  break;
+	case 0x08:
+	  i8= fetch();
+	  tick(1);
+	  off= i8;
+	  ea= iv + off;
+	  break;
+	case 0x09:
+	  off= fetch()*256 + fetch();
+	  tick(2);
+	  ea= iv + off;
+	  break;
+	case 0x0a:
+	  return resINV_INST;
+	  break;
+	case 0x0b:
+	  off= D;
+	  ea= iv + off;
+	  break;
+	case 0x0c:
+	  i8= fetch();
+	  tick(1);
+	  off= i8;
+	  iv= PC;
+	  ea= iv + off;
+	  break;
+	case 0x0d:
+	  off= fetch()*256 + fetch();
+	  tick(2);
+	  iv= PC;
+	  ea= iv + off;
+	  break;
+	case 0x0e:
+	  return resINV_INST;
+	  break;
+	case 0x0f:
+	  if ((idx & 0x10) == 0) return resINV_INST;
+	  if ((idx & 0x60) != 0) return resINV_INST;
+	  off= 0;
+	  iv= fetch()*256 + fetch();
+	  tick(2);
+	  ea= iv;
+	  break;
+	}
+      if (ind && (idx & 0x10))
+	{
+	  u16_t a;
+	  a= rom->read(ea)*256 + rom->read(ea+1);
+	  ea= a;
+	  tick(2);
+	}
+    }
+
+  if (res_ea)
+    *res_ea= ea;
+  return resGO;
+}
+
+
+void
+cl_m6809::push_regs(bool do_cc)
+{
+  rom->write(--reg.S, PC&0xff);
+  rom->write(--reg.S, PC>>8);
+  tick(2);
+  if (reg.CC & flagE)
+    {
+      rom->write(--reg.S, reg.U&0xff);
+      rom->write(--reg.S, reg.U>>8);
+      rom->write(--reg.S, reg.Y&0xff);
+      rom->write(--reg.S, reg.Y>>8);
+      rom->write(--reg.S, reg.X&0xff);
+      rom->write(--reg.S, reg.X>>8);
+      rom->write(--reg.S, reg.DP);
+      rom->write(--reg.S, B);
+      rom->write(--reg.S, A);
+      tick(9);
+      if (do_cc)
+	rom->write(--reg.S, reg.CC), tick(1);
+    }
+}
+
+void
+cl_m6809::pull_regs(bool do_cc)
+{
+  u8_t l,h;
+  if(do_cc)
+    {
+      reg.CC= rom->read(reg.S++), vc.rd++;
+      tick(1);
+    }
+  if (reg.CC & flagE)
+    {
+      A= rom->read(reg.S++);
+      B= rom->read(reg.S++);
+      reg.DP= rom->read(reg.S++);
+      h= rom->read(reg.S++);
+      l= rom->read(reg.S++);
+      reg.X= h*256 + l;
+      h= rom->read(reg.S++);
+      l= rom->read(reg.S++);
+      reg.Y= h*256 + l;
+      h= rom->read(reg.S++);
+      l= rom->read(reg.S++);
+      reg.U= h*256 + l;
+      vc.rd+= 9;
+      tick(9);
+    }
+  h= rom->read(reg.S++);
+  l= rom->read(reg.S++);
+  tick(2);
+  vc.rd+= 2;
+  PC= h*256 + l;
+}
+
+int
+cl_m6809::inst_add8(t_mem code, u8_t *acc, u8_t op, bool c, bool store, bool invert_c)
+{
+  u8_t r;
+  unsigned int d= *acc;
+  unsigned int o= op;
+  signed int res= (signed char)d + (signed char)o;
+
+  if (c) { ++res, ++o; }
+  
+  reg.CC= ~(flagH|flagV|flagS|flagZ|flagC);
+  if ((d & 0xf) + (o & 0xf) > 0xf)  reg.CC|= flagH;
+  if ((res < -128) || (res > +127)) reg.CC|= flagV;
+  if (d + o > 0xff)                 reg.CC|= flagC;
+  if (invert_c)
+    reg.CC^= flagC;
+
+  r= res & 0xff;
+  if (r == 0)   reg.CC|= flagZ;
+  if (r & 0x80) reg.CC|= flagS;
+
+  if (store)
+    *acc= r;
+  
+  return resGO;
+}
+
+
+int
+cl_m6809::inst_add16(t_mem code, u16_t *acc, u16_t op, bool c,
+		     bool store, bool invert_c, bool is_sub)
+{
+  u16_t r;
+  unsigned int d= *acc;
+  unsigned int o= op;
+  u32_t res= d + o;
+  if (c)
+    res++;
+  r= res;
+  
+  reg.CC= ~(flagV|flagS|flagZ|flagC);
+  //if ((res < (int)(0x8000)) || (res > (int)(0x7fff)))
+  if (is_sub)
+    {
+      o= ~o;
+      if (0x8000 & ((d&~o&~r) | (~d&o&r)))
+	reg.CC|= flagV;
+    }
+  else
+    {
+      if (0x8000 & ((d&o&~r) | (~d&~o&r)))
+	reg.CC|= flagV;
+    }
+  if (res > 0xffff)
+    reg.CC|= flagC;
+  if (invert_c)
+    reg.CC^= flagC;
+
+  //r= res & 0xffff;
+  if (r == 0)     reg.CC|= flagZ;
+  if (r & 0x8000) reg.CC|= flagS;
+
+  if (store)
+    {
+      *acc= r;
+      if (acc == ®.S)
+	en_nmi= true;
+    }
+  
+  return resGO;
+}
+
+int
+cl_m6809::inst_bool(t_mem code, char bop, u8_t *acc, u8_t op, bool store)
+{
+  u8_t r;
+
+  switch (bop)
+    {
+    case '&': r= *acc & op; break;
+    case '|': r= *acc | op; break;
+    case '^': r= *acc ^ op; break;
+    default: r= *acc; break;
+    }
+
+  if (store)
+    *acc= r;
+
+  SET_O(0);
+  SET_Z(r);
+  SET_S(r&0x80);
+  
+  return resGO;
+}
+
+int
+cl_m6809::inst_ld8(t_mem code, u8_t *acc, u8_t op)
+{
+  *acc= op;
+
+  SET_O(0);
+  SET_Z(op);
+  SET_S(op&0x80);
+  
+  return resGO;
+}
+
+int
+cl_m6809::inst_ld16(t_mem code, u16_t *acc, u16_t op)
+{
+  *acc= op;
+
+  SET_O(0);
+  SET_Z(op);
+  SET_S(op&0x8000);
+
+  if (acc == ®.S)
+    en_nmi= true;
+  
+  return resGO;
+}
+
+int
+cl_m6809::inst_st8(t_mem code, u8_t src, t_addr ea)
+{
+  rom->write(ea, src);
+  tick(1);
+  vc.wr++;
+  
+  SET_O(0);
+  SET_Z(src);
+  SET_S(src & 0x80);
+
+  return resGO;
+}
+
+int
+cl_m6809::inst_st16(t_mem code, u16_t src, t_addr ea)
+{
+  rom->write(ea  , (src)>>8);
+  rom->write(ea+1, (src)&0xff);
+  tick(2);
+  vc.wr+= 2;
+  
+  SET_O(0);
+  SET_Z(src);
+  SET_S(src & 0x8000);
+
+  return resGO;
+}
+
+int
+cl_m6809::inst_alu(t_mem code)
+{
+  u8_t *acc, op8, idx;
+  u16_t op16;
+  t_addr ea;
+  
+  if (code == 0x87 ||
+      code == 0xc7 ||
+      code == 0xcd ||
+      code == 0x8f ||
+      code == 0xcf)
+    return resINV_INST;
+  
+  acc= (code & 0x40)? (&B) : (&A);
+
+  switch (code & 0x30)
+    {
+    case 0x00: // immed
+      ea= PC;
+      op8= fetch();
+      tick(1);
+      break;
+    case 0x10: // direct
+      ea= reg.DP*256 + fetch();
+      tick(2);
+      op8= rom->read(ea);
+      tick(1);
+      vc.rd++;
+      break;
+    case 0x20: // index
+      {
+	int r;
+	idx= fetch();
+	tick(1);
+	if ((r= index2ea(idx, &ea)) != resGO)
+	  return r;
+	op8= rom->read(ea);
+	tick(1);
+	vc.rd++;
+	break;
+      }
+    case 0x30: // extend
+      ea= fetch()*256 + fetch();
+      tick(3);
+      op8= rom->read(ea);
+      tick(1);
+      vc.rd++;
+      break;
+    default: op8= 0; break;
+    }
+
+  switch (code & 0x0f)
+    {
+      //          8    9    A    B    C    D    E    F
+    case 0x00: // SUB  SUB  SUB  SUB  SUB  SUB  SUB  SUB
+      return inst_add8(code, acc, ~op8, 1, true, true);
+      break;
+    case 0x01: // CMP  CMP  CMP  CMP  CMP  CMP  CMP  CMP
+      return inst_add8(code, acc, ~op8, 1, false, true);
+      break;
+    case 0x02: // SBC  SBC  SBC  SBC  SBC  SBC  SBC  SBC
+      return inst_add8(code, acc, ~op8, (reg.CC&flagC)?0:1, true, true);
+      break;
+    case 0x03: // SUBD SUBD SUBD SUBD ADDD ADDD ADDD ADDD
+      {
+	int c= 0;
+	int inv= false;
+	bool is_sub= false;
+	if ((code & 0x30) == 0)
+	  {
+	    op16= op8*256 + fetch();
+	    tick(1);
+	  }
+	else
+	  {
+	    op16= op8*256 + rom->read(ea+1);
+	    tick(1);
+	    vc.rd++;
+	  }
+	if ((code & 0x40) == 0)
+	  op16= ~op16, c= 1, inv= true, is_sub= true;
+	return inst_add16(code, &D, op16, c, true, inv, is_sub);
+	break;
+      }
+    case 0x04: // AND  AND  AND  AND  AND  AND  AND  AND
+      return inst_bool(code, '&', acc, op8, true);
+      break;
+    case 0x05: // BIT  BIT  BIT  BIT  BIT  BIT  BIT  BIT
+      return inst_bool(code, '&', acc, op8, false);
+      break;
+    case 0x06: // LD   LD   LD   LD   LD   LD   LD   LD
+      return inst_ld8(code, acc, op8);
+      break;
+    case 0x07: // --   STA  STA  STA  --   STB  STB  STB
+      return inst_st8(code, *acc, ea);
+      break;
+    case 0x08: // EOR  EOR  EOR  EOR  EOR  EOR  EOR  EOR
+      return inst_bool(code, '^', acc, op8, true);
+      break;
+    case 0x09: // ADC  ADC  ADC  ADC  ADC  ADC  ADC  ADC
+      return inst_add8(code, acc, op8, (reg.CC&flagC)?1:0, true, false);
+      break;
+    case 0x0a: // OR   OR   OR   OR   OR   OR   OR   OR
+      return inst_bool(code, '|', acc, op8, true);
+      break;
+    case 0x0b: // ADD  ADD  ADD  ADD  ADD  ADD  ADD  ADD
+      return inst_add8(code, acc, op8, 0, true, false);
+      break;
+    case 0x0c: // CMPX CMPX CMPX CMPX LDD  LDD  LDD  LDD
+      if ((code & 0x30) == 0)
+	{
+	  op16= op8*256 + fetch();
+	  tick(1);
+	}
+      else
+	{
+	  op16= op8*256 + rom->read(ea+1);
+	  tick(1);
+	  vc.rd++;
+	}
+      if ((code & 0x40) == 0)
+	return inst_add16(code, &(reg.X), ~op16, 1, false, true, true);
+      else
+	return inst_ld16(code, &D, op16);
+      break;
+    case 0x0d: // BSR  JSR  JSR  JSR  --   STD  STD  STD
+      if ((code & 0x40) == 0)
+	{
+	  if ((code & 0x30) == 0)
+	    { //BSR
+	      i8_t i8= op8;
+	      ea= (u16_t)((i16_t)PC + (i16_t)i8);
+	      rom->write(--reg.S, PC&0xff);
+	      rom->write(--reg.S, (PC>>8)&0xff);
+	      tick(2);
+	      vc.wr+= 2;
+	    }
+	  else
+	    {
+	      //JSR
+	      rom->write(--reg.S, PC & 0xff);
+	      rom->write(--reg.S, (PC>>8)&0xff);
+	      tick(2);
+	      vc.wr+= 2;
+	    }
+	  PC= ea;
+	}
+      else
+	return inst_st16(code, D, ea);
+      break;
+    case 0x0e: // LDX  LDX  LDX  LDX  LDU  LDU  LDU  LDU
+      if ((code & 0x30) == 0)
+	{
+	  op16= op8*256 + fetch();
+	  tick(1);
+	}
+      else
+	{
+	  op16= op8*256 + rom->read(ea+1);
+	  tick(1);
+	  vc.rd++;
+	}
+      if ((code & 0x40) == 0)
+	return inst_ld16(code, ®.X, op16);
+      else
+	return inst_ld16(code, ®.U, op16);
+      break;
+    case 0x0f: // --   STX  STX  STX  --   STU  STU  STU
+      if ((code & 0x40) == 0)
+	return inst_st16(code, reg.X, ea);
+      else
+	return inst_st16(code, reg.U, ea);
+      break;
+    }
+  
+  return resGO;
+}
+
+
+int
+cl_m6809::inst_10(t_mem code)
+{
+  u8_t op8;
+    
+  switch (code & 0x0f)
+    {
+    case 0x00: // pg1
+      break;
+    case 0x01: // pg2
+      break;
+    case 0x02: // NOP
+      break;
+    case 0x03: // SYNC
+      state= stIDLE;
+      break;
+    case 0x04: // --
+      break;
+    case 0x05: // --
+      break;
+    case 0x06: // LBRA
+      {
+	u16_t u= fetch()*256 + fetch();
+	i16_t i= u;
+	PC= PC + i;
+	tick(2);
+	break;
+      }
+    case 0x07: // LBSR
+      {
+	u16_t u= fetch()*256 + fetch();
+	i16_t i= u;
+	tick(2);
+	rom->write(--reg.S, PC & 0xff);
+	rom->write(--reg.S, (PC>>8)&0xff);
+	tick(2);
+	vc.wr+= 2;
+	PC= PC + i;
+	break;
+      }
+    case 0x08: // --
+      break;
+    case 0x09: // DAA
+      {
+	u8_t cf= 0;
+	int r;
+	if ((reg.CC & flagH) || ((A&0x0f) > 9))
+	  cf|= 0x06;
+	if ((reg.CC & flagC) ||
+	    ((A&0xf0) > 0x90) ||
+	    (
+	     ((A&0xf0) > 0x80) &&
+	     ((A&0x0f) > 0x09)
+	     )
+	    )
+	  cf|= 0x60;
+	r= A + cf;
+	A= r;
+	SET_Z(A);
+	SET_S(A & 0x80);
+	if (r>0xff)
+	  reg.CC|= flagC;
+	tick(1);
+	break;
+      }
+    case 0x0a: // ORCC
+      op8= fetch();
+      reg.CC|= op8;
+      tick(1);
+      break;
+    case 0x0b: // --
+      break;
+    case 0x0c: // ANDCC
+      op8= fetch();
+      reg.CC&= op8;
+      tick(1);
+      break;
+    case 0x0d: // SEX
+      A= (B & 0x80)?0xff:0;
+      SET_Z(D);
+      SET_S(A & 0x80);
+      tick(1);
+      break;
+    case 0x0e: // EXG
+      {
+	u8_t r1, r2;
+	op8= fetch();
+	tick(1);
+	r1= op8>>4;
+	r2= op8&0xf;
+	if (((r1^r2)&0x08)!=0)
+	  return resINV_INST;
+	if (r1<8)
+	  {
+	    u16_t *R1= reg16_ptr[r1&7];
+	    u16_t *R2= reg16_ptr[r2&7];
+	    u16_t t;
+	    t= (R1)?*R1:PC;
+	    *R1= (R2)?*R2:PC;
+	    *R2= t;
+	  }
+	else
+	  {
+	    u8_t *R1= reg8_ptr[r1&7];
+	    u8_t *R2= reg8_ptr[r2&7];
+	    u8_t t;
+	    t= *R1;
+	    *R1= *R2;
+	    *R2= t;
+	  }
+	tick(6);
+	break;
+      }
+    case 0x0f: // TFR
+      {
+	op8= fetch();
+	tick(1);
+	u8_t rs= op8>>4;
+	u8_t rd= op8&0xf;
+	if (((rd^rs)&8)!=0)
+	  return resINV_INST;
+	if (rs<8)
+	  {
+	    u16_t *RS= reg16_ptr[rs&7];
+	    u16_t *RD= reg16_ptr[rd&7];
+	    if (RD)
+	      *RD= (RS)?*RS:PC;
+	    else
+	      PC= (RS)?*RS:PC;
+	  }
+	else
+	  {
+	    u8_t *RS= reg8_ptr[rs&7];
+	    u8_t *RD= reg8_ptr[rd&7];
+	    *RD= *RS;
+	  }
+	tick(4);
+	break;
+      }
+    }
+
+  return resGO;
+}
+
+int
+cl_m6809::inst_branch(t_mem code, bool l)
+{
+  bool c= reg.CC & flagC;
+  bool z= reg.CC & flagZ;
+  bool n= reg.CC & flagN;
+  bool v= reg.CC & flagV;
+  bool t= 0;
+  
+  switch (code & 0x0f)
+    {
+    case 0x00: // BRA 1
+      if (l)
+	return resINV_INST;
+      t= true;
+      break;
+    case 0x01: // BRN 0
+      t= false;
+      break;
+    case 0x02: // BHI ~C * ~Z
+      t= !c && !z;
+      break;
+    case 0x03: // BLS C + Z
+      t= c || z;
+      break;
+    case 0x04: // BHS ~C
+      t= !c;
+      break;
+    case 0x05: // BLO C
+      t= c;
+      break;
+    case 0x06: // BNE ~Z
+      t= !z;
+      break;
+    case 0x07: // BEQ Z
+      t= z;
+      break;
+    case 0x08: // BVC ~V
+      t= !v;
+      break;
+    case 0x09: // BVS V
+      t= v;
+      break;
+    case 0x0a: // BPL ~N
+      t= !n;
+      break;
+    case 0x0b: // BMI N
+      t= n;
+      break;
+    case 0x0c: // BGE N*V + ~N*~V
+      t= (n&&v) || (!n&&!v);
+      break;
+    case 0x0d: // BLT N*~V + ~N*V
+      t= (n&&!v) || (!n&&v);
+      break;
+    case 0x0e: // BGT N*V*~Z + ~N*~V*~Z
+      t= (n&&v&&!z) || (!n&&!v&&!z);
+      break;
+    case 0x0f: // BLE Z + N*~V + ~N*V
+      t= z || (n&&!v) || (!n&&v);
+      break;
+    }
+
+  i16_t i= fetch();
+  tick(1);
+  if (i&0x80) i|= 0xff00;
+  if (l)
+    {
+      i= i*256 + fetch();
+      tick(1);
+    }
+  if (t)
+    {
+      PC= PC + i;
+      tick(1);
+    }
+      
+  return resGO;
+}
+
+int
+cl_m6809::inst_30(t_mem code)
+{
+  t_addr ea;
+  int r;
+  u8_t op8, l, h;    
+  
+  switch (code & 0x0f)
+    {
+    case 0x00: // LEAX
+      r= index2ea(fetch(), &ea);
+      tick(1);
+      if (r!=resGO)
+	return r;
+      reg.X= ea;
+      SET_Z(reg.X);
+      tick(1);
+      break;
+    case 0x01: // LEAY
+      r= index2ea(fetch(), &ea);
+      tick(1);
+      if (r!=resGO)
+	return r;
+      reg.Y= ea;
+      SET_Z(reg.Y);
+      tick(1);
+      break;
+    case 0x02: // LEAS
+      r= index2ea(fetch(), &ea);
+      tick(1);
+      if (r!=resGO)
+	return r;
+      reg.S= ea;
+      tick(1);
+      break;
+    case 0x03: // LEAU
+      r= index2ea(fetch(), &ea);
+      tick(1);
+      if (r!=resGO)
+	return r;
+      reg.U= ea;
+      tick(1);
+      break;
+    case 0x04: // PSHS
+      op8= fetch();
+      tick(1);
+      if (op8 & 0x80)
+	rom->write(--reg.S, PC&0xff),
+	  rom->write(--reg.S, PC>>8),
+	  vc.wr+= 2,
+	  tick(2);
+      if (op8 & 0x40)
+	rom->write(--reg.S, reg.U&0xff),
+	  rom->write(--reg.S, reg.U>>8),
+	  vc.wr+= 2,
+	  tick(2);
+      if (op8 & 0x20)
+	rom->write(--reg.S, reg.Y&0xff),
+	  rom->write(--reg.S, reg.Y>>8),
+	  vc.wr+= 2,
+	  tick(2);
+      if (op8 & 0x10)
+	rom->write(--reg.S, reg.X&0xff),
+	  rom->write(--reg.S, reg.X>>8),
+	  vc.wr+= 2,
+	  tick(2);
+      if (op8 & 0x08)
+	rom->write(--reg.S, reg.DP), vc.wr++, tick(1);
+      if (op8 & 0x04)
+	rom->write(--reg.S, B), vc.wr++, tick(1);
+      if (op8 & 0x02)
+	rom->write(--reg.S, A), vc.wr++, tick(1);
+      if (op8 & 0x01)
+	rom->write(--reg.S, reg.CC), vc.wr++, tick(1);
+      break;
+    case 0x05: // PULS
+      op8= fetch();
+      if(op8 & 0x01)
+	reg.CC= rom->read(reg.S++), vc.rd++, tick(1);
+      if (op8 & 0x02)
+	A= rom->read(reg.S++), vc.rd++, tick(1);
+      if (op8 & 0x04)
+	B= rom->read(reg.S++), vc.rd++, tick(1);
+      if (op8 & 0x08)
+	reg.DP= rom->read(reg.S++), vc.rd++, tick(1);
+      if (op8 & 0x10)
+	h= rom->read(reg.S++),
+	  l= rom->read(reg.S++),
+	  reg.X= h*256 + l,
+	  vc.rd+= 2,
+	  tick(2);
+      if (op8 & 0x20)
+	h= rom->read(reg.S++),
+	  l= rom->read(reg.S++),
+	  reg.Y= h*256 + l,
+	  vc.rd+= 2,
+	  tick(2);
+      if (op8 & 0x40)
+	h= rom->read(reg.S++),
+	  l= rom->read(reg.S++),
+	  reg.U= h*256 + l,
+	  vc.rd+= 2,
+	  tick(2);
+      if (op8 & 0x80)
+	h= rom->read(reg.S++),
+	  l= rom->read(reg.S++),
+	  PC= h*256 + l,
+	  vc.rd+= 2,
+	  tick(2);
+      break;
+    case 0x06: // PSHU
+      op8= fetch();
+      if (op8 & 0x80)
+	rom->write(--reg.U, PC&0xff),
+	  rom->write(--reg.U, PC>>8),
+	  vc.wr+= 2,
+	  tick(2);
+      if (op8 & 0x40)
+	rom->write(--reg.U, reg.S&0xff),
+	  rom->write(--reg.U, reg.S>>8),
+	  vc.wr+= 2,
+	  tick(2);
+      if (op8 & 0x20)
+	rom->write(--reg.U, reg.Y&0xff),
+	  rom->write(--reg.U, reg.Y>>8),
+	  vc.wr+= 2,
+	  tick(2);
+      if (op8 & 0x10)
+	rom->write(--reg.U, reg.X&0xff),
+	  rom->write(--reg.U, reg.X>>8),
+	  vc.wr+= 2,
+	  tick(2);
+      if (op8 & 0x08)
+	rom->write(--reg.U, reg.DP), vc.wr++, tick(1);
+      if (op8 & 0x04)
+	rom->write(--reg.U, B), vc.wr++, tick(1);
+      if (op8 & 0x02)
+	rom->write(--reg.U, A), vc.wr++, tick(1);
+      if (op8 & 0x01)
+	rom->write(--reg.U, reg.CC), vc.wr++, tick(1);
+      break;
+    case 0x07: // PULU
+      op8= fetch();
+      if(op8 & 0x01)
+	reg.CC= rom->read(reg.U++), vc.rd++, tick(1);
+      if (op8 & 0x02)
+	A= rom->read(reg.U++), vc.rd++, tick(1);
+      if (op8 & 0x04)
+	B= rom->read(reg.U++), vc.rd++, tick(1);
+      if (op8 & 0x08)
+	reg.DP= rom->read(reg.U++), vc.rd++, tick(1);
+      if (op8 & 0x10)
+	h= rom->read(reg.U++),
+	  l= rom->read(reg.U++),
+	  reg.X= h*256 + l,
+	  vc.rd+= 2,
+	  tick(2);
+      if (op8 & 0x20)
+	h= rom->read(reg.U++),
+	  l= rom->read(reg.U++),
+	  reg.Y= h*256 + l,
+	  vc.rd+= 2,
+	  tick(2);
+      if (op8 & 0x40)
+	h= rom->read(reg.U++),
+	  l= rom->read(reg.U++),
+	  reg.S= h*256 + l,
+	  vc.rd+= 2,
+	  tick(2);
+      if (op8 & 0x80)
+	h= rom->read(reg.U++),
+	  l= rom->read(reg.U++),
+	  PC= h*256 + l,
+	  vc.rd+= 2,
+	  tick(2);
+      break;
+    case 0x08: // --
+      break;
+    case 0x09: // RTS
+      ea= rom->read(reg.S++) * 256;
+      ea+= rom->read(reg.S++);
+      tick(2);
+      vc.rd+= 2;
+      PC= ea;
+      tick(1);
+      break;
+    case 0x0a: // ABX
+      reg.X+= B;
+      tick(2);
+      break;
+    case 0x0b: // RTI
+      pull_regs(true);
+      tick(1);
+      break;
+    case 0x0c: // CWAI
+      op8= fetch();
+      tick(1);
+      reg.CC&= op8;
+      reg.CC|= flagE;
+      push_regs(true);
+      cwai= true;
+      state= stIDLE;
+      break;
+    case 0x0d: // MUL
+      D= A * B;
+      SET_Z(D);
+      SET_C(B & 0x80);
+      tick(9);
+      break;
+    case 0x0e: // RESET
+      reset();
+      break;
+    case 0x0f: // SWI
+      reg.CC|= flagE;
+      tick(2);
+      push_regs(true);
+      reg.CC|= flagF|flagI;
+      PC= rom->read(0xfffa)*256 + rom->read(0xfffb);
+      tick(2);
+      tick(1);
+      break;
+    }
+
+  return resGO;
+}
+
+
+int
+cl_m6809::inst_neg(t_mem code, u8_t *acc, t_addr ea, u8_t op8)
+{
+  if (acc)
+    {
+      *acc= ~(*acc);
+      return inst_add8(code, acc, 0, 1, true, true);
+    }
+  op8= rom->read(ea);
+  tick(1);
+  vc.rd++;
+  u8_t t= A;
+  A= ~op8;
+  inst_add8(code, &A, 0, 1, true, true);
+  rom->write(ea, A);
+  tick(1);
+  vc.wr++;
+  A= t;
+  return resGO;
+}
+
+int
+cl_m6809::inst_com(t_mem code, u8_t *acc, t_addr ea, u8_t op8)
+{
+  if (acc)
+    {
+      op8= *acc= ~(*acc);
+    }
+  else
+    {
+      op8= ~(rom->read(ea));
+      tick(1);
+      vc.rd++;
+      rom->write(ea, op8);
+      tick(1);
+      vc.wr++;
+    }
+  
+  SET_C(1);
+  SET_O(0);
+  SET_Z(op8);
+  SET_S(op8 & 0x80);
+  
+  return resGO;
+}
+
+int
+cl_m6809::inst_lsr(t_mem code, u8_t *acc, t_addr ea, u8_t op8)
+{
+  if (acc)
+    {
+      SET_C(*acc & 1);
+      op8= *acc= (*acc) >> 1;
+    }
+  else
+    {
+      op8= rom->read(ea);
+      tick(1);
+      vc.rd++;
+      SET_C(op8 & 1);
+      op8>>= 1;
+      rom->write(ea, op8);
+      tick(1);
+      vc.wr++;
+    }
+  
+  SET_Z(op8);
+  SET_S(op8 & 0x80);
+  
+  return resGO;
+}
+
+int
+cl_m6809::inst_ror(t_mem code, u8_t *acc, t_addr ea, u8_t op8)
+{
+  u8_t oldc, newc;
+
+  if (acc)
+    op8= *acc;
+  else
+    {
+      op8= rom->read(ea);
+      tick(1);
+      vc.rd++;
+    }
+  oldc= reg.CC & flagC;
+  newc= op8 & 1;
+  
+  op8>>= 1;
+  if (oldc)
+    op8|= 0x80;
+
+  if (acc)
+    *acc= op8;
+  else
+    rom->write(ea, op8), vc.wr++, tick(1);
+  
+  SET_C(newc);
+  SET_Z(op8);
+  SET_S(op8 & 0x80);
+  
+  return resGO;
+}
+
+int
+cl_m6809::inst_asr(t_mem code, u8_t *acc, t_addr ea, u8_t op8)
+{
+  u8_t old8, newc;
+
+  if (acc)
+    op8= *acc;
+  else
+    {
+      op8= rom->read(ea);
+      tick(1);
+      vc.rd++;
+    }
+  old8= op8 & 0x80;
+  newc= op8 & 1;
+  
+  op8>>= 1;
+  if (old8)
+    op8|= 0x80;
+
+  if (acc)
+    *acc= op8;
+  else
+    rom->write(ea, op8), vc.wr++, tick(1);
+  
+  SET_C(newc);
+  SET_Z(op8);
+  SET_S(op8 & 0x80);
+  
+  return resGO;
+}
+
+int
+cl_m6809::inst_asl(t_mem code, u8_t *acc, t_addr ea, u8_t op8)
+{
+  u8_t newc;
+  
+  op8= (acc)?(*acc):(vc.rd++, tick(1), rom->read(ea));
+  newc= op8 & 0x80;
+  
+  op8<<= 1;
+
+  if (acc)
+    *acc= op8;
+  else
+    rom->write(ea, op8), vc.wr++, tick(1);
+  
+  SET_C(newc);
+  SET_Z(op8);
+  SET_S(op8 & 0x80);
+  
+  return resGO;
+}
+
+int
+cl_m6809::inst_rol(t_mem code, u8_t *acc, t_addr ea, u8_t op8)
+{
+  u8_t oldc, newc;
+  
+  op8= (acc)?(*acc):(vc.rd++, tick(1), rom->read(ea));
+  oldc= reg.CC & flagC;
+  newc= op8 & 0x80;
+
+  SET_O( (op8&0x80) ^ ((op8<<1)&0x80) );
+  
+  op8<<= 1;
+  if (oldc)
+    op8|= 1;
+
+  if (acc)
+    *acc= op8;
+  else
+    rom->write(ea, op8), vc.wr++, tick(1);
+  
+  SET_C(newc);
+  SET_Z(op8);
+  SET_S(op8 & 0x80);
+  
+  return resGO;
+}
+
+int
+cl_m6809::inst_dec(t_mem code, u8_t *acc, t_addr ea, u8_t op8)
+{
+  op8= (acc)?(*acc):(vc.rd++, tick(1), rom->read(ea));
+  SET_O(op8==0x80);
+
+  op8--;
+  
+  if (acc)
+    *acc= op8;
+  else
+    rom->write(ea, op8), vc.wr++, tick(1);
+  
+  SET_Z(op8);
+  SET_S(op8 & 0x80);
+
+  return resGO;
+}
+
+int
+cl_m6809::inst_inc(t_mem code, u8_t *acc, t_addr ea, u8_t op8)
+{
+  op8= (acc)?(*acc):(vc.rd++, tick(1), rom->read(ea));
+  SET_O(op8==0x7f);
+
+  op8++;
+  
+  if (acc)
+    *acc= op8;
+  else
+    rom->write(ea, op8), vc.wr++, tick(1);
+  
+  SET_Z(op8);
+  SET_S(op8 & 0x80);
+
+  return resGO;
+}
+
+int
+cl_m6809::inst_tst(t_mem code, u8_t *acc, t_addr ea, u8_t op8)
+{
+  op8= (acc)?(*acc):(vc.rd++, tick(1), rom->read(ea));
+  SET_O(0);
+  
+  SET_Z(op8);
+  SET_S(op8 & 0x80);
+
+  return resGO;
+}
+
+int
+cl_m6809::inst_clr(t_mem code, u8_t *acc, t_addr ea, u8_t op8)
+{
+  if (!acc)
+    {
+      volatile u8_t u= rom->read(ea);
+      op8= u;
+      vc.rd++;
+      tick(1);
+    }
+  
+  if (acc)
+    *acc= 0;
+  else
+    rom->write(ea, 0), vc.wr++, tick(1);
+  
+  SET_O(0);
+  SET_Z(1);
+  SET_S(0);
+  SET_C(0);
+
+  return resGO;
+}
+
+const u8_t low_illegals[]=
+  {
+   0x01, 0x41, 0x51, 0x61, 0x71,
+   0x02, 0x42, 0x52, 0x62, 0x72,
+   0x14,
+   0x05, 0x15, 0x45, 0x55, 0x65, 0x75,
+   0x18, 0x38,
+   0x0b, 0x1b, 0x4b, 0x5b, 0x6b, 0x7b,
+   0x4e, 0x5e,
+   0
+  };
+
+int
+cl_m6809::inst_low(t_mem code)
+{
+  t_addr ea= 0;
+  u8_t op8= 0, *acc, idx;
+  
+  for (idx= 0; low_illegals[idx]; idx++)
+    if (low_illegals[idx] == code)
+      return resINV_INST;
+
+  if ((code & 0xf0) == 0x10)
+    return inst_10(code);
+
+  if ((code & 0xf0) == 0x20)
+    return inst_branch(code, false);
+
+  if ((code & 0xf0) == 0x30)
+    return inst_30(code);
+  
+  switch (code & 0xf0)
+    {
+    case 0x00: // direct
+      ea= reg.DP*256 + fetch();
+      op8= rom->read(ea);
+      tick(2);
+      vc.rd++;
+      break;
+    case 0x60: // index
+      {
+	int r;
+	idx= fetch();
+	tick(1);
+	if ((r= index2ea(idx, &ea)) != resGO)
+	  return r;
+	op8= rom->read(ea);
+	tick(1);
+	vc.rd++;
+	break;
+      }
+    case 0x70: // extend
+      ea= fetch()*256 + fetch();
+      op8= rom->read(ea);
+      tick(3);
+      vc.rd++;
+      break;
+    }
+
+  if ((code & 0xf0) == 0x40)
+    acc= &A;
+  else if ((code & 0xf0) == 0x50)
+    acc= &B;
+  else
+    acc= NULL;
+  
+  switch (code & 0x0f)
+    {
+      //          0     1     2     3     4     5     6     7
+    case 0x00: // NEG   pg1   BRA   LEAX  NEGA  NEGB  NEG   NEG
+      return inst_neg(code, acc, ea, op8);
+      break;
+    case 0x01: // --    pg2   BRN   LEAY  --    --    --    --
+      break;
+    case 0x02: // --    NOP   BHI   LEAS  --    --    --    --
+      break;
+    case 0x03: // COM   SYNC  BLS   LEAU  COMA  COMB  COM   COM
+      return inst_com(code, acc, ea, op8);
+      break;
+    case 0x04: // LSR   --    BHS   PSHS  LSRA  LSRB  LSR   LSR
+      return inst_lsr(code, acc, ea, op8);
+      break;
+    case 0x05: // --    --    BLO   PULS  --    --    --    --
+      break;
+    case 0x06: // ROR   LBRA  BNE   PSHU  RORA  RORB  ROR   ROR
+      return inst_ror(code, acc, ea, op8);
+      break;
+    case 0x07: // ASR   LBSR  BEQ   PULU  ASRA  ASRB  ASR   ASR
+      return inst_asr(code, acc, ea, op8);
+      break;
+    case 0x08: // ASL   --    BVC   --    ASLA  ASLB  ASL   ASL
+      return inst_asl(code, acc, ea, op8);
+      break;
+    case 0x09: // ROL   DAA   BVS   RTS   ROLA  ROLB  ROL   ROL
+      return inst_rol(code, acc, ea, op8);
+      break;
+    case 0x0a: // DEC   ORCC  BPL   ABX   DECA  DECB  DEC   DEC
+      return inst_dec(code, acc, ea, op8);
+      break;
+    case 0x0b: // --    --    BMI   RTI   --    --    --    --
+      break;
+    case 0x0c: // INC   ANDCC BGE   CWAI  INCA  INCB  INC   INC
+      return inst_inc(code, acc, ea, op8);
+      break;
+    case 0x0d: // TST   SEX   BLT   MUL   TSTA  TSTB  TST   TST
+      return inst_tst(code, acc, ea, op8);
+      break;
+    case 0x0e: // JMP   EXG   BGT   RESET --    --    JMP   JMP
+      PC= ea;
+      break;
+    case 0x0f: // CLR   TFR   BLE   SWI   CLRA  CLRB  CLR   CLR
+      return inst_clr(code, acc, ea, op8);
+      break;
+    }
+  
+  return resGO;
+}
+
+
+int
+cl_m6809::inst_page1(t_mem code)
+{
+  t_addr ea;
+  u8_t op8, idx;
+  u16_t op16;
+
+  if ((code & 0xf0) == 0x20)
+    return inst_branch(code, true);
+  if (code == 0x3f)
+    {
+      // SWI2
+      tick(2);
+      reg.CC|= flagE;
+      push_regs(true);
+      tick(1);
+      PC= rom->read(0xfff4)*256 + rom->read(0xfff5);
+      tick(2);
+      tick(1);
+      vc.rd+= 2;
+    }
+  if ((code & 0x80) == 0)
+    return resINV_INST;
+  
+  /*
+    1000 immed   3 c e
+    1100             e
+
+    1001 direct  3 c e f
+    1101             e f
+
+    1010 index   3 c e f
+    1110             e f
+
+    1011 extend  3 c e f
+    1111             e f
+  */
+  u8_t cl= code & 0xf;
+  u8_t ch= code >> 4;
+  switch (code & 0x30)
+    {
+    case 0x00: // immed
+      if ((ch==8)&&(cl!=3)&&(cl!=12)&&(cl!=14)) return resINV_INST;
+      if ((ch==12)&&(cl!=14)) return resINV_INST;
+      ea= PC;
+      op8= fetch();
+      tick(1);
+      break;
+    case 0x10: // direct
+      if ((ch==9)&&(cl!=3)&&(cl!=12)&&(cl!=14)&&(cl!=15)) return resINV_INST;
+      if ((ch==13)&&(cl!=14)&&(cl!=15)) return resINV_INST;
+      ea= reg.DP*256 + fetch();
+      tick(1);
+      op8= rom->read(ea);
+      tick(1);
+      vc.rd++;
+      break;
+    case 0x20: // index
+      {
+	if ((ch==10)&&(cl!=3)&&(cl!=12)&&(cl!=14)&&(cl!=15)) return resINV_INST;
+	if ((ch==14)&&(cl!=14)&&(cl!=15)) return resINV_INST;
+	int r;
+	idx= fetch();
+	tick(1);
+	if ((r= index2ea(idx, &ea)) != resGO)
+	  return r;
+	op8= rom->read(ea);
+	tick(1);
+	vc.rd++;
+	break;
+      }
+    case 0x30: // extend
+      if ((ch==11)&&(cl!=3)&&(cl!=12)&&(cl!=14)&&(cl!=15)) return resINV_INST;
+      if ((ch==15)&&(cl!=14)&&(cl!=15)) return resINV_INST;
+      ea= fetch()*256 + fetch();
+      tick(2);
+      op8= rom->read(ea);
+      tick(1);
+      vc.rd++;
+      break;
+    default: op8= 0; break;
+    }
+
+  if ((code & 0x30) == 0)
+    {
+      op16= op8*256 + fetch();
+      tick(1);
+    }
+  else
+    {
+      op16= op8*256 + rom->read(ea+1);
+      tick(1);
+      vc.rd++;
+    }
+  
+  switch (cl)
+    {
+    case 3: // CMPD
+      inst_add16(code, &(D), ~op16, 1, false, true, true);
+      break;
+    case 0xc: // CMPY
+      inst_add16(code, &(reg.Y), ~op16, 1, false, true, true);
+      break;
+    case 0xe: // LDY, LDS
+      if ((code & 0x40) == 0)
+	  inst_ld16(code, &(reg.Y), op16);
+      else
+	  inst_ld16(code, &(reg.S), op16);
+      break;
+    case 0xf: // STY, STS
+      if (code & 0x40)
+	inst_st16(code, reg.Y, ea);
+      else
+	inst_st16(code, reg.S, ea);
+      break;
+    }
+  
+  return resGO;
+}
+
+
+int
+cl_m6809::inst_page2(t_mem code)
+{
+  t_addr ea;
+  u8_t op8= 0, idx;
+  u16_t op16;
+  
+  if (code == 0x3f)
+    {
+      // SWI3
+      tick(1);
+      reg.CC|= flagE;
+      push_regs(true);
+      tick(1);
+      PC= rom->read(0xfff2)*256 + rom->read(0xfff3);
+      tick(2);
+      tick(1);
+      vc.rd+= 2;
+    }
+  if ((code!=0x83)&&(code!=0x8c)&&
+      (code!=0x93)&&(code!=0x9c)&&
+      (code!=0xa3)&&(code!=0xac)&&
+      (code!=0xb3)&&(code!=0xbc))
+    return resINV_INST;
+
+  switch (code & 0x30)
+    {
+    case 0x00: //immediate
+      ea= PC;
+      op8= fetch();
+      tick(1);
+      break;
+    case 0x10: // direct
+      ea= reg.DP*256 + fetch();
+      tick(1);
+      op8= rom->read(ea);
+      tick(1);
+      vc.rd++;
+      break;
+    case 0x20: // index
+      {
+	int r;
+	idx= fetch();
+	tick(1);
+	if ((r= index2ea(idx, &ea)) != resGO)
+	  return r;
+	op8= rom->read(ea);
+	tick(1);
+	vc.rd++;
+	break;
+      }
+    case 0x30: // extend
+      ea= fetch()*256 + fetch();
+      tick(2);
+      op8= rom->read(ea);
+      tick(1);
+      vc.rd++;
+      break;
+    }
+
+  if ((code & 0x30) == 0)
+    {
+      op16= op8*256 + fetch();
+      tick(1);
+    }
+  else
+    {
+      op16= op8*256 + rom->read(ea+1);
+      tick(1);
+      vc.rd++;
+    }
+  
+  if ((code & 0x0f) == 0x03)
+    {
+      // CMPU
+      inst_add16(code, &(reg.U), ~op16, 1, false, true, true);
+      tick(1);
+    }
+  if ((code & 0x0f) == 0x0c)
+    {
+      // CMPS
+      inst_add16(code, &(reg.S), ~op16, 1, false, true, true);
+      tick(1);
+    }
+
+  return resGO;
+}
+
+
+int
+cl_m6809::exec_inst(void)
+{
+  t_mem code;
+  bool fe;
+
+  fe= fetch(&code);
+  tick(1);
+  if (fe)
+    return(resBREAKPOINT);
+
+  if (code & 0x80)
+    return inst_alu(code);
+  else
+    {
+      if (code == 0x10)
+	return tick(1), inst_page1(fetch());
+      if (code == 0x11)
+	return tick(1), inst_page2(fetch());
+      return inst_low(code);
+    }
+  
+  return resGO;
+}
+
+int
+cl_m6809::accept_it(class it_level *il)
+{
+  class cl_it_src *is= il->source;
+  //class cl_m6809_src_base *parent= NULL;
+  /*
+  if (is)
+    {
+      if ((parent= is->get_parent()) != NULL)
+	{
+	  is= parent;
+	  il->source= is;
+	}
+    }
+  */
+  tick(3);
+  reg.CC&= ~flagE;
+  if (is == src_irq || is == src_nmi)
+    reg.CC|= flagE;//is->Evalue;
+    
+  if (!cwai)
+    push_regs(true);
+  cwai= false;
+  reg.CC|= flagI;//is->IFvalue;
+  if (is == src_firq || is == src_nmi)
+    reg.CC|= flagF;
+  
+  t_addr a= rom->read(is->addr) * 256 + rom->read(is->addr+1);
+  tick(2);
+  vc.rd+= 2;
+  PC= a;
+
+  is->clear();
+  
+  it_levels->push(il);
+  tick(2);
+  return resGO;
+}
+
+
+/* End of m6809.src/m6809.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m6809.src/m6809cl.h sdcc-4.2.0+dfsg/sim/ucsim/m6809.src/m6809cl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/m6809.src/m6809cl.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m6809.src/m6809cl.h	2022-01-24 11:09:43.000000000 +0000
@@ -0,0 +1,169 @@
+/*
+ * Simulator of microcontrollers (m6809cl.h)
+ *
+ * Copyright (C) 2020,20 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef M6809CL_HEADER
+#define M6809CL_HEADER
+
+#include "uccl.h"
+#include "memcl.h"
+
+
+/*
+ * Base of M6809 processor
+ */
+
+struct reg_t {
+  u16_t U;
+  u16_t S;
+  u16_t X;
+  u16_t Y;
+  union {
+    u16_t rD;
+    struct {
+#ifdef WORDS_BIGENDIAN
+      u8_t rA;
+      u8_t rB;
+#else
+      u8_t rB;
+      u8_t rA;
+#endif      
+    } a8;
+  } acc;
+  u8_t DP;
+  u8_t CC;
+};
+
+#define A  (reg.acc.a8.rA)
+#define B  (reg.acc.a8.rB)
+#define D  (reg.acc.rD)
+
+enum flags
+  {
+   flagC= 1,
+   flagV= 2,
+   flagO= 2,
+   flagZ= 4,
+   flagN= 8,
+   flagS= 8,
+   flagI= 16,
+   flagH= 32,
+   flagF= 64,
+   flagE= 128
+  };
+
+class cl_m6809_src_base;
+
+class cl_m6809: public cl_uc
+{
+public:
+  class cl_address_space *regs8;
+  class cl_address_space *regs16;
+  struct reg_t reg;
+  bool en_nmi;
+  bool cwai;
+public:
+  class cl_address_space *rom;
+  class cl_it_src *src_irq, *src_firq, *src_nmi;
+protected:
+  u8_t *reg8_ptr[8];
+  u16_t *reg16_ptr[8];
+public:
+  cl_m6809(class cl_sim *asim);
+  virtual int init(void);
+  virtual const char *id_string(void);
+  virtual void reset(void);
+  virtual void set_PC(t_addr addr);
+
+  virtual void mk_hw_elements(void);
+  virtual void make_cpu_hw(void);
+  virtual void make_memories(void);
+
+  virtual int clock_per_cycle(void) { return 1; }
+  
+  virtual struct dis_entry *dis_tbl(void);
+  virtual void analyze_start(void);
+  virtual void analyze(t_addr addr);
+  virtual void disass_indexed(t_addr *addr, chars *work, int siz);
+  virtual void disass_immediate(t_addr *addr, chars *work, int siz);
+  virtual char *disass(t_addr addr);
+  virtual void print_regs(class cl_console_base *con);
+  virtual int indexed_length(t_addr addr);
+  virtual int inst_length(t_addr addr);
+  virtual int longest_inst(void) { return 5; }
+
+  virtual int index2ea(u8_t idx, t_addr *res_ea);
+  virtual void push_regs(bool do_cc);
+  virtual void pull_regs(bool do_cc);
+  
+  virtual int inst_add8 (t_mem code,  u8_t *acc,  u8_t op, bool c, bool store, bool invert_c);
+  virtual int inst_add16(t_mem code, u16_t *acc, u16_t op, bool c, bool store, bool invert_c, bool is_sub);
+  virtual int inst_bool (t_mem code, char bop, u8_t *acc, u8_t op, bool store);
+  virtual int inst_ld8  (t_mem code,  u8_t *acc,  u8_t op);
+  virtual int inst_ld16 (t_mem code, u16_t *acc, u16_t op);
+  virtual int inst_st8  (t_mem code,  u8_t  src, t_addr ea);
+  virtual int inst_st16 (t_mem code, u16_t  src, t_addr ea);
+  
+  virtual int inst_alu(t_mem code);
+
+  virtual int inst_10(t_mem code);
+  virtual int inst_branch(t_mem code, bool l);
+  virtual int inst_30(t_mem code);
+
+  virtual int inst_neg(t_mem code, u8_t *acc, t_addr ea, u8_t op8);
+  virtual int inst_com(t_mem code, u8_t *acc, t_addr ea, u8_t op8);
+  virtual int inst_lsr(t_mem code, u8_t *acc, t_addr ea, u8_t op8);
+  virtual int inst_ror(t_mem code, u8_t *acc, t_addr ea, u8_t op8);
+  virtual int inst_asr(t_mem code, u8_t *acc, t_addr ea, u8_t op8);
+  virtual int inst_asl(t_mem code, u8_t *acc, t_addr ea, u8_t op8);
+  virtual int inst_rol(t_mem code, u8_t *acc, t_addr ea, u8_t op8);
+  virtual int inst_dec(t_mem code, u8_t *acc, t_addr ea, u8_t op8);
+  virtual int inst_inc(t_mem code, u8_t *acc, t_addr ea, u8_t op8);
+  virtual int inst_tst(t_mem code, u8_t *acc, t_addr ea, u8_t op8);
+  virtual int inst_clr(t_mem code, u8_t *acc, t_addr ea, u8_t op8);
+
+  virtual int inst_low(t_mem code);
+  
+  virtual int inst_page1(t_mem code);
+
+  virtual int inst_page2(t_mem code);
+    
+  virtual int exec_inst(void);
+  virtual int priority_of(uchar nuof_it) { return nuof_it; }
+  virtual int accept_it(class it_level *il);
+  virtual bool it_enabled(void) { return true; }
+};
+
+#define SET_C(v) ( (reg.CC)= ((reg.CC)&~flagC) | ((v)?flagC:0) )
+#define SET_Z(v) ( (reg.CC)= ((reg.CC)&~flagZ) | ((v==0)?flagZ:0) )
+#define SET_S(v) ( (reg.CC)= ((reg.CC)&~flagS) | ((v)?flagS:0) )
+#define SET_O(v) ( (reg.CC)= ((reg.CC)&~flagV) | ((v)?flagV:0) )
+#define SET_H(v) ( (reg.CC)= ((reg.CC)&~flagH) | ((v)?flagH:0) )
+
+  
+#endif
+
+/* End of m6809.src/m6809.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m6809.src/Makefile.in sdcc-4.2.0+dfsg/sim/ucsim/m6809.src/Makefile.in
--- sdcc-4.0.0+dfsg/sim/ucsim/m6809.src/Makefile.in	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m6809.src/Makefile.in	2022-01-09 14:02:03.000000000 +0000
@@ -0,0 +1,185 @@
+#
+# uCsim m6809.src/Makefile
+#
+# (c) Drotos Daniel, Talker Bt. 1997
+#
+
+# tool name
+TN		= m6809
+
+STARTYEAR	= 1997
+
+SHELL		= /bin/sh
+CXX		= @CXX@
+CPP		= @CPP@
+CXXCPP		= @CXXCPP@
+RANLIB		= @RANLIB@
+INSTALL		= @INSTALL@
+STRIP		= @STRIP@
+MAKEDEP         = @MAKEDEP@
+
+top_builddir	= @top_builddir@
+top_srcdir	= @top_srcdir@
+
+transform	= @program_transform_name@
+
+DEFS            = $(subs -DHAVE_CONFIG_H,,@DEFS@)
+CPPFLAGS        = @CPPFLAGS@ -I$(srcdir) -I$(top_srcdir) -I$(top_builddir) \
+		  -I$(top_srcdir)/cmd.src -I$(top_srcdir)/sim.src \
+		  -I$(top_srcdir)/gui.src -I$(top_srcdir)/motorola.src
+CFLAGS          = @WALL_FLAG@ @CFLAGS@
+CXXFLAGS        = @WALL_FLAG@ @CXXFLAGS@
+LDFLAGS         = @LDFLAGS@
+PICOPT		= @PICOPT@
+SHAREDLIB	= @SHAREDLIB@
+EXEEXT		= @EXEEXT@
+
+LIBS		= -L$(top_builddir) -lmotorola -lsim -lucsimutil -lguiucsim -lcmd -lsim @LIBS@
+DL		= @DL@
+dl_ok		= @dl_ok@
+
+prefix          = @prefix@
+exec_prefix     = @exec_prefix@
+bindir          = @bindir@
+libdir          = @libdir@
+datadir         = @datadir@
+datarootdir     = @datarootdir@
+includedir      = @includedir@
+mandir          = @mandir@
+man1dir         = $(mandir)/man1
+man2dir         = $(mandir)/man2
+infodir         = @infodir@
+srcdir          = @srcdir@
+VPATH           = @srcdir@
+
+OBJECTS_SHARED	= sim$(TN).o $(TN).o glob.o irq.o
+
+OBJECTS_EXE	= s$(TN).o
+OBJECTS		= $(OBJECTS_SHARED) $(OBJECTS_EXE)
+
+# short/long exe and lib name
+SEN		= s$(TN)$(EXEEXT)
+LEN		= ucsim_$(TN)$(EXEEXT)
+SONAME		= libucsim_$(TN).so
+
+enable_dlso	= @enable_dlso@
+dlso_ok		= @dlso_ok@
+
+M6809ASM	=
+TEST_OBJ	= 
+
+
+# Compiling entire program or any subproject
+# ------------------------------------------
+all: checkconf otherlibs $(TN).src
+
+
+# Compiling and installing everything and runing test
+# ---------------------------------------------------
+install: all installdirs install_shared_lib
+	$(INSTALL) $(SEN) $(DESTDIR)$(bindir)/$(SEN)
+	$(STRIP) $(DESTDIR)$(bindir)/$(SEN)
+	$(INSTALL) $(LEN) $(DESTDIR)$(bindir)/$(LEN)
+	$(STRIP) $(DESTDIR)$(bindir)/$(LEN)
+
+
+# Deleting all the installed files
+# --------------------------------
+uninstall:
+	rm -f $(DESTDIR)$(bindir)/$(SEN)
+	rm -f $(DESTDIR)$(bindir)/$(LEN)
+	rm -f $(DESTDIR)$(libdir)/$(SONAME)
+
+
+# Performing self-test
+# --------------------
+check: $(TEST_OBJ)
+
+.PHONY:	test baseline
+test:
+	@$(MAKE) --no-print-directory -C test
+
+baseline:
+	@$(MAKE) --no-print-directory -C test baseline
+
+
+# Performing installation test
+# ----------------------------
+installcheck:
+
+
+# Creating installation directories
+# ---------------------------------
+installdirs:
+	test -d $(DESTDIR)$(bindir) || $(INSTALL) -d $(DESTDIR)$(bindir)
+
+
+# Creating dependencies
+# ---------------------
+dep: Makefile.dep
+
+Makefile.dep: $(srcdir)/*.cc $(srcdir)/*.h
+	$(MAKEDEP) $(CPPFLAGS) $(filter %.cc,$^) >Makefile.dep
+
+-include Makefile.dep
+include $(srcdir)/clean.mk
+
+# My rules
+# --------
+.SUFFIXES: .asm .hex
+
+$(TN).src: $(SEN) $(LEN) shared_lib
+
+$(SEN): $(OBJECTS) $(top_builddir)/libcmd.a $(top_builddir)/libguiucsim.a $(top_builddir)/libsim.a $(top_builddir)/libucsimutil.a $(top_builddir)/libmotorola.a
+	$(CXX) $(CXXFLAGS) $(LDFLAGS) $(OBJECTS) $(LIBS) -o $@
+
+$(LEN): $(SEN)
+	cp $< $@
+
+ifeq ($(dlso_ok),yes)
+shared_lib: $(top_builddir)/$(SONAME)
+install_shared_lib: shared_lib
+	test -d $(DESTDIR)$(libdir) || $(INSTALL) -d $(DESTDIR)$(libdir)
+	$(INSTALL) $(top_builddir)/$(SONAME) $(DESTDIR)$(libdir)/$(SONAME)
+else
+shared_lib:
+	@$(top_srcdir)/mkecho $(top_builddir) "No $(TN) shared lib made."
+	@$(top_srcdir)/mkecho $(top_builddir) "(SHAREDLIB="$(SHAREDLIB)",dl_ok="$(dl_ok)",enable_dlso="$(enable_dlso)")"
+install_shared_lib:
+endif
+
+$(top_builddir)/$(SONAME): $(OBJECTS_SHARED)
+	$(CXX) -shared $(LDFLAGS) $(OBJECTS_SHARED) -o $@
+
+otherlibs: $(top_builddir)/libcmd.a $(top_builddir)/libguiucsim.a $(top_builddir)/libsim.a $(top_builddir)/libucsimutil.a $(top_builddir)/libmotorola.a
+
+$(top_builddir)/libcmd.a:
+	$(MAKE) -C $(top_builddir)/cmd.src all
+
+$(top_builddir)/libguiucsim.a:
+	$(MAKE) -C $(top_builddir)/gui.src checkconf ucsim_lib
+
+$(top_builddir)/libsim.a:
+	$(MAKE) -C $(top_builddir)/sim.src all
+
+$(top_builddir)/libucsimutil.a:
+	$(MAKE) -C $(top_builddir) -f main.mk
+
+$(top_builddir)/libmotorola.a:
+	$(MAKE) -C $(top_builddir)/motorola.src all
+
+.cc.o:
+	$(CXX) $(CXXFLAGS) $(PICOPT) $(CPPFLAGS) $(TARGET_ARCH) -c $< -o $@
+
+.asm.hex:
+	$(M6809ASM) -l $< -o $@ -e $<.lst
+
+
+# Remaking configuration
+# ----------------------
+checkconf:
+	@if [ -f $(top_builddir)/devel ]; then\
+	  $(MAKE) -C $(top_builddir) -f conf.mk srcdir="$(srcdir)" top_builddir="$(top_builddir)" freshconf;\
+	fi
+
+# End of m6809.src/Makefile.in
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m6809.src/simm6809.cc sdcc-4.2.0+dfsg/sim/ucsim/m6809.src/simm6809.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/m6809.src/simm6809.cc	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m6809.src/simm6809.cc	2020-09-17 06:45:33.000000000 +0000
@@ -0,0 +1,44 @@
+/*
+ * Simulator of microcontrollers (simm6809.cc)
+ *
+ * Copyright (C) 2020,20 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+// local
+#include "simm6809cl.h"
+#include "m6809cl.h"
+
+
+cl_simm6809::cl_simm6809(class cl_app *the_app):
+  cl_sim(the_app)
+{}
+
+class cl_uc *
+cl_simm6809::mk_controller(void)
+{
+  return(new cl_m6809(this));
+}
+
+
+/* End of m6809.src/simm6809.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m6809.src/simm6809cl.h sdcc-4.2.0+dfsg/sim/ucsim/m6809.src/simm6809cl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/m6809.src/simm6809cl.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m6809.src/simm6809cl.h	2020-09-17 06:45:33.000000000 +0000
@@ -0,0 +1,45 @@
+/*
+ * Simulator of microcontrollers (simm6809cl.h)
+ *
+ * Copyright (C) 2020,20 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef SIMM6809CL_HEADER
+#define SIMM6809CL_HEADER
+
+#include "simcl.h"
+
+
+class cl_simm6809: public cl_sim
+{
+public:
+  cl_simm6809(class cl_app *the_app);
+
+  virtual class cl_uc *mk_controller(void);
+};
+
+
+#endif
+
+/* End of m6809.src/simm6809cl.h */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m6809.src/sm6809.cc sdcc-4.2.0+dfsg/sim/ucsim/m6809.src/sm6809.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/m6809.src/sm6809.cc	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m6809.src/sm6809.cc	2020-09-17 06:45:33.000000000 +0000
@@ -0,0 +1,54 @@
+/*
+ * Simulator of microcontrollers (sm6809.cc)
+ *
+ * Copyright (C) 2020,20 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+// prj
+#include "globals.h"
+
+// local
+#include "simm6809cl.h"
+
+
+int
+main(int argc, char *argv[])
+{
+  class cl_sim *sim;
+  
+  application= new cl_app();
+  application->set_name("sm6809");
+  application->init(argc, argv);
+  sim= new cl_simm6809(application);
+  if (sim->init())
+    sim->state|= SIM_QUIT;
+  application->set_simulator(sim);
+  //sim->main();
+  application->run();
+  application->done();
+  delete application;
+  return(0);
+}
+
+/* End of m6809.src/sm6809.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m6809.src/test/clean.mk sdcc-4.2.0+dfsg/sim/ucsim/m6809.src/test/clean.mk
--- sdcc-4.0.0+dfsg/sim/ucsim/m6809.src/test/clean.mk	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m6809.src/test/clean.mk	2021-04-01 17:52:48.000000000 +0000
@@ -0,0 +1,5 @@
+clean:
+
+distclean:
+	rm -f Makefile
+	find . -type d -name out -exec rm -rf {} \;
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m6809.src/test/config/baseline/M6809 sdcc-4.2.0+dfsg/sim/ucsim/m6809.src/test/config/baseline/M6809
--- sdcc-4.0.0+dfsg/sim/ucsim/m6809.src/test/config/baseline/M6809	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m6809.src/test/config/baseline/M6809	2022-02-08 21:21:05.000000000 +0000
@@ -0,0 +1,35 @@
+uCsim, Copyright (C)  Daniel Drotos.
+uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+This is free software, and you are welcome to redistribute it
+under certain conditions; type `show c' for details.
+Type of microcontroller: M6809
+Controller has 9 hardware element(s).
+   on simif[0]
+  off vcd[0]
+   on dreg[0]
+   on irq[0]
+   on uart[0]
+   on uart[1]
+   on pia[0]
+   on pia[1]
+   on dport[0]
+A= $00   0   +0 .  B= $00   0   +0 .  D= $0000     0     +0
+CC= 01010000
+    EFHINZVC
+DP= $00
+X= 0x0000 08 70 d4 b2 8a 29 54 48 .p...)TH
+Y= 0x0000 08 70 d4 b2 8a 29 54 48 .p...)TH
+S= 0x0000 08 70 d4 b2 8a 29 54 48 .p...)TH
+U= 0x0000 08 70 d4 b2 8a 29 54 48 .p...)TH
+0x6c75  ? 96 4d          LDA    DP:$4d[0K
+Memory chips:
+  0x000000-0x0000ff      256 variable_storage (32,%08x,0x%02lx)
+  0x000000-0x00ffff    65536 rom_chip (8,%02x,0x%04lx)
+Address spaces:
+  0x000000-0x0000ff      256 variables (32,%08x,0x%02lx)
+  0x000000-0x00ffff    65536 rom (8,%02x,0x%04lx)
+  0x000000-0x000003        4 regs8 (8,%02x,0x%01lx)
+  0x000000-0x000004        5 regs16 (16,%04x,0x%01lx)
+Address decoders:
+  variables 0x00 0xff -> variable_storage 0x00 activated
+  rom 0x0000 0xffff -> rom_chip 0x0000 activated
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m6809.src/test/config/Makefile sdcc-4.2.0+dfsg/sim/ucsim/m6809.src/test/config/Makefile
--- sdcc-4.0.0+dfsg/sim/ucsim/m6809.src/test/config/Makefile	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m6809.src/test/config/Makefile	2021-03-21 12:01:19.000000000 +0000
@@ -0,0 +1,8 @@
+OUTPUTS = M6809
+
+
+$(OUTPUTS):
+	$(call run-sim, -e 'conf; info reg; info mem')
+
+
+include test-lib.mk
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m6809.src/test/Makefile.in sdcc-4.2.0+dfsg/sim/ucsim/m6809.src/test/Makefile.in
--- sdcc-4.0.0+dfsg/sim/ucsim/m6809.src/test/Makefile.in	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m6809.src/test/Makefile.in	2021-03-28 10:28:14.000000000 +0000
@@ -0,0 +1,9 @@
+# @configure_input@
+
+srcdir           = @abs_srcdir@
+
+abs_top_builddir = @abs_top_builddir@
+abs_top_srcdir   = @abs_top_srcdir@
+
+
+include $(abs_top_srcdir)/test-target.mk
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m6809.src/test/symdis/baseline/stdout sdcc-4.2.0+dfsg/sim/ucsim/m6809.src/test/symdis/baseline/stdout
--- sdcc-4.0.0+dfsg/sim/ucsim/m6809.src/test/symdis/baseline/stdout	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m6809.src/test/symdis/baseline/stdout	2022-02-08 21:21:05.000000000 +0000
@@ -0,0 +1,19 @@
+uCsim, Copyright (C)  Daniel Drotos.
+uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+This is free software, and you are welcome to redistribute it
+under certain conditions; type `show c' for details.
+var init rom[0x0000]
+var main rom[0x0002]
+var forever rom[0x0008]
+dc 0x0000 0x0008 
+
+0x0000    :
+0x0000  ? 0e 02          JMP    DP:$02[0K
+
+0x0002    :
+0x0002    86 00          LDA    #$00[0K
+0x0004    27 02          BEQ    $0008 [0K
+0x0006    86 01          LDA    #$01[0K
+
+0x0008    :
+0x0008    20 fe          BRA    $0008 [0K
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m6809.src/test/symdis/Makefile sdcc-4.2.0+dfsg/sim/ucsim/m6809.src/test/symdis/Makefile
--- sdcc-4.0.0+dfsg/sim/ucsim/m6809.src/test/symdis/Makefile	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m6809.src/test/symdis/Makefile	2021-05-07 16:21:16.000000000 +0000
@@ -0,0 +1,16 @@
+OUTPUTS = stdout
+
+
+# Ignore changes in white space. The field widths for labels
+# depends on the length of the longest label. This will be
+# different for different simulators and should not be assumed
+# to be constant for any given simulator.
+DIFF_OPTS += -b
+
+
+stdout:	test.ihx test.cmd
+	$(call run-sim)
+
+
+include test-lib.mk
+
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m6809.src/test/symdis/test.asm sdcc-4.2.0+dfsg/sim/ucsim/m6809.src/test/symdis/test.asm
--- sdcc-4.0.0+dfsg/sim/ucsim/m6809.src/test/symdis/test.asm	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m6809.src/test/symdis/test.asm	2021-05-07 16:21:16.000000000 +0000
@@ -0,0 +1,9 @@
+	cpu 6809
+
+init:	jmp main
+
+main:	lda #0
+	beq forever
+	lda #1
+forever:
+	bra forever
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m6809.src/test/symdis/test.cmd sdcc-4.2.0+dfsg/sim/ucsim/m6809.src/test/symdis/test.cmd
--- sdcc-4.0.0+dfsg/sim/ucsim/m6809.src/test/symdis/test.cmd	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m6809.src/test/symdis/test.cmd	2021-05-07 16:21:16.000000000 +0000
@@ -0,0 +1,4 @@
+var init rom[0x0000]
+var main rom[0x0002]
+var forever rom[0x0008]
+dc 0x0000 0x0008 
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m6809.src/test/symdis/test.ihx sdcc-4.2.0+dfsg/sim/ucsim/m6809.src/test/symdis/test.ihx
--- sdcc-4.0.0+dfsg/sim/ucsim/m6809.src/test/symdis/test.ihx	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m6809.src/test/symdis/test.ihx	2021-05-07 16:21:16.000000000 +0000
@@ -0,0 +1,2 @@
+:0A0000000E0286002702860120FE92
+:00000001FF
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m6809.src/test/test-conf.mk sdcc-4.2.0+dfsg/sim/ucsim/m6809.src/test/test-conf.mk
--- sdcc-4.0.0+dfsg/sim/ucsim/m6809.src/test/test-conf.mk	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m6809.src/test/test-conf.mk	2021-05-07 16:21:16.000000000 +0000
@@ -0,0 +1,10 @@
+# For asl see: http://john.ccac.rwth-aachen.de:8000/as/
+
+AS = asl
+ASFLAGS = -L -h -U
+
+%p:	%.asm
+	$(AS) $(ASFLAGS) -olist '$*.lst' -o '$@' '$<'
+
+%.ihx:	%.p
+	p2hex -F Intel '$<' '$@'
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m68hc08.src/(c).1 sdcc-4.2.0+dfsg/sim/ucsim/m68hc08.src/(c).1
--- sdcc-4.0.0+dfsg/sim/ucsim/m68hc08.src/(c).1	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m68hc08.src/(c).1	2003-10-15 05:14:36.000000000 +0000
@@ -0,0 +1,25 @@
+/*
+ * Simulator of microcontrollers (@@F@@)
+ *
+ * Copyright (C) @@S@@,@@Y@@ Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m68hc08.src/clean.mk sdcc-4.2.0+dfsg/sim/ucsim/m68hc08.src/clean.mk
--- sdcc-4.0.0+dfsg/sim/ucsim/m68hc08.src/clean.mk	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m68hc08.src/clean.mk	2021-10-04 11:31:43.000000000 +0000
@@ -0,0 +1,29 @@
+# Deleting all files created by building the program
+# --------------------------------------------------
+clean:
+	rm -f *core *[%~] *.[oa]
+	rm -f .[a-z]*~
+	rm -f shc08 shc08.exe ucsim_hc08 ucsim_hc08.exe
+	rm -f sm68hc08 sm68hc08.exe ucsim_m68hc08 ucsim_m68hc08.exe
+	$(MAKE) -C test -f clean.mk clean
+
+
+# Deleting all files created by configuring or building the program
+# -----------------------------------------------------------------
+distclean: clean
+	rm -f config.cache config.log config.status
+	rm -f Makefile *.dep
+	$(MAKE) -C test -f clean.mk distclean
+
+
+# Like clean but some files may still exist
+# -----------------------------------------
+mostlyclean: clean
+
+
+# Deleting everything that can reconstructed by this Makefile. It deletes
+# everything deleted by distclean plus files created by bison, etc.
+# -----------------------------------------------------------------------
+realclean: distclean
+
+# End of hc08.src/clean.mk
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m68hc08.src/conf.mk sdcc-4.2.0+dfsg/sim/ucsim/m68hc08.src/conf.mk
--- sdcc-4.0.0+dfsg/sim/ucsim/m68hc08.src/conf.mk	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m68hc08.src/conf.mk	2016-07-29 14:28:30.000000000 +0000
@@ -0,0 +1,10 @@
+#
+# Makefile targets to remake configuration
+#
+
+freshconf: Makefile
+
+Makefile: $(srcdir)/Makefile.in $(top_srcdir)/configure.ac
+	cd $(top_builddir) && $(SHELL) ./config.status
+
+# End of hc08.src/conf.mk
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m68hc08.src/glob.cc sdcc-4.2.0+dfsg/sim/ucsim/m68hc08.src/glob.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/m68hc08.src/glob.cc	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m68hc08.src/glob.cc	2016-05-23 08:34:18.000000000 +0000
@@ -0,0 +1,395 @@
+
+/*
+ * Simulator of microcontrollers (glob.cc)
+ *
+ * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#include 
+
+#include "stypes.h"
+
+
+/*
+%d - direct addressing
+%x - extended addressing
+%p - pc relative addressing
+%b - unsigned byte immediate addressing
+%w - unsigned word immediate addressing
+%s - signed byte immediate
+%1 - unsigned byte index offset
+%2 - unsigned word index offset
+*/
+
+/*  uint  code, mask;  char  branch;  uchar length;  char  *mnemonic; */
+struct dis_entry disass_hc08[]= {
+  { 0x0000, 0x00ff, 'R', 3, "brset #0,%d,%p" },
+  { 0x0001, 0x00ff, 'R', 3, "brclr #0,%d,%p" },
+  { 0x0002, 0x00ff, 'R', 3, "brset #1,%d,%p" },
+  { 0x0003, 0x00ff, 'R', 3, "brclr #1,%d,%p" },
+  { 0x0004, 0x00ff, 'R', 3, "brset #2,%d,%p" },
+  { 0x0005, 0x00ff, 'R', 3, "brclr #2,%d,%p" },
+  { 0x0006, 0x00ff, 'R', 3, "brset #3,%d,%p" },
+  { 0x0007, 0x00ff, 'R', 3, "brclr #3,%d,%p" },
+  { 0x0008, 0x00ff, 'R', 3, "brset #4,%d,%p" },
+  { 0x0009, 0x00ff, 'R', 3, "brclr #4,%d,%p" },
+  { 0x000a, 0x00ff, 'R', 3, "brset #5,%d,%p" },
+  { 0x000b, 0x00ff, 'R', 3, "brclr #5,%d,%p" },
+  { 0x000c, 0x00ff, 'R', 3, "brset #6,%d,%p" },
+  { 0x000d, 0x00ff, 'R', 3, "brclr #6,%d,%p" },
+  { 0x000e, 0x00ff, 'R', 3, "brset #7,%d,%p" },
+  { 0x000f, 0x00ff, 'R', 3, "brclr #7,%d,%p" },
+
+  { 0x0010, 0x00ff, ' ', 2, "bset #0,%d" },
+  { 0x0011, 0x00ff, ' ', 2, "bclr #0,%d" },
+  { 0x0012, 0x00ff, ' ', 2, "bset #1,%d" },
+  { 0x0013, 0x00ff, ' ', 2, "bclr #1,%d" },
+  { 0x0014, 0x00ff, ' ', 2, "bset #2,%d" },
+  { 0x0015, 0x00ff, ' ', 2, "bclr #2,%d" },
+  { 0x0016, 0x00ff, ' ', 2, "bset #3,%d" },
+  { 0x0017, 0x00ff, ' ', 2, "bclr #3,%d" },
+  { 0x0018, 0x00ff, ' ', 2, "bset #4,%d" },
+  { 0x0019, 0x00ff, ' ', 2, "bclr #4,%d" },
+  { 0x001a, 0x00ff, ' ', 2, "bset #5,%d" },
+  { 0x001b, 0x00ff, ' ', 2, "bclr #5,%d" },
+  { 0x001c, 0x00ff, ' ', 2, "bset #6,%d" },
+  { 0x001d, 0x00ff, ' ', 2, "bclr #6,%d" },
+  { 0x001e, 0x00ff, ' ', 2, "bset #7,%d" },
+  { 0x001f, 0x00ff, ' ', 2, "bclr #7,%d" },
+
+  { 0x0020, 0x00ff, 'R', 2, "bra %p" },
+  { 0x0021, 0x00ff, 'R', 2, "brn %p" },
+  { 0x0022, 0x00ff, 'R', 2, "bhi %p" },
+  { 0x0023, 0x00ff, 'R', 2, "bls %p" },
+  { 0x0024, 0x00ff, 'R', 2, "bcc %p" },
+  { 0x0025, 0x00ff, 'R', 2, "bcs %p" },
+  { 0x0026, 0x00ff, 'R', 2, "bne %p" },
+  { 0x0027, 0x00ff, 'R', 2, "beq %p" },
+  { 0x0028, 0x00ff, 'R', 2, "bhcc %p" },
+  { 0x0029, 0x00ff, 'R', 2, "bhcs %p" },
+  { 0x002a, 0x00ff, 'R', 2, "bpl %p" },
+  { 0x002b, 0x00ff, 'R', 2, "bmi %p" },
+  { 0x002c, 0x00ff, 'R', 2, "bmc %p" },
+  { 0x002d, 0x00ff, 'R', 2, "bms %p" },
+  { 0x002e, 0x00ff, 'R', 2, "bil %p" },
+  { 0x002f, 0x00ff, 'R', 2, "bih %p" },
+
+  { 0x0030, 0x00ff, ' ', 2, "neg %d" },
+  { 0x0031, 0x00ff, 'R', 3, "cbeq %d,%p" },
+  { 0x0032, 0x00ff, ' ', 3, "ldhx %x" },  //HCS08 only
+  { 0x0033, 0x00ff, ' ', 2, "com %d" },
+  { 0x0034, 0x00ff, ' ', 2, "lsr %d" },
+  { 0x0035, 0x00ff, ' ', 2, "sthx %d" },
+  { 0x0036, 0x00ff, ' ', 2, "ror %d" },
+  { 0x0037, 0x00ff, ' ', 2, "asr %d" },
+  { 0x0038, 0x00ff, ' ', 2, "lsl %d" },
+  { 0x0039, 0x00ff, ' ', 2, "rol %d" },
+  { 0x003a, 0x00ff, ' ', 2, "dec %d" },
+  { 0x003b, 0x00ff, 'R', 3, "dbnz %d,%d" },
+  { 0x003c, 0x00ff, ' ', 2, "inc %d" },
+  { 0x003d, 0x00ff, ' ', 2, "tst %d" },
+  { 0x003e, 0x00ff, ' ', 3, "cphx %x" },  //HCS08 only
+  { 0x003f, 0x00ff, ' ', 2, "clr %d" },
+
+  { 0x0040, 0x00ff, ' ', 1, "nega" },
+  { 0x0041, 0x00ff, 'R', 3, "cbeqa %b,%p" },
+  { 0x0042, 0x00ff, ' ', 1, "mul" },
+  { 0x0043, 0x00ff, ' ', 1, "coma" },
+  { 0x0044, 0x00ff, ' ', 1, "lsra" },
+  { 0x0045, 0x00ff, ' ', 3, "ldhx %w" },
+  { 0x0046, 0x00ff, ' ', 1, "rora" },
+  { 0x0047, 0x00ff, ' ', 1, "asra" },
+  { 0x0048, 0x00ff, ' ', 1, "lsla" },
+  { 0x0049, 0x00ff, ' ', 1, "rola" },
+  { 0x004a, 0x00ff, ' ', 1, "deca" },
+  { 0x004b, 0x00ff, 'R', 2, "dbnza %p" },
+  { 0x004c, 0x00ff, ' ', 1, "inca" },
+  { 0x004d, 0x00ff, ' ', 1, "tsta" },
+  { 0x004e, 0x00ff, ' ', 3, "mov %d,%d" },
+  { 0x004f, 0x00ff, ' ', 1, "clra" },
+
+  { 0x0050, 0x00ff, ' ', 1, "negx" },
+  { 0x0051, 0x00ff, 'R', 3, "cbeqx %b,%p" },
+  { 0x0052, 0x00ff, ' ', 1, "div" },
+  { 0x0053, 0x00ff, ' ', 1, "comx" },
+  { 0x0054, 0x00ff, ' ', 1, "lsrx" },
+  { 0x0055, 0x00ff, ' ', 2, "ldhx %d" },
+  { 0x0056, 0x00ff, ' ', 1, "rorx" },
+  { 0x0057, 0x00ff, ' ', 1, "asrx" },
+  { 0x0058, 0x00ff, ' ', 1, "lslx" },
+  { 0x0059, 0x00ff, ' ', 1, "rolx" },
+  { 0x005a, 0x00ff, ' ', 1, "decx" },
+  { 0x005b, 0x00ff, 'R', 2, "dbnzx %p" },
+  { 0x005c, 0x00ff, ' ', 1, "incx" },
+  { 0x005d, 0x00ff, ' ', 1, "tstx" },
+  { 0x005e, 0x00ff, ' ', 3, "mov %d,x+" },
+  { 0x005f, 0x00ff, ' ', 1, "clrx" },
+
+  { 0x0060, 0x00ff, ' ', 2, "neg %1,x" },
+  { 0x0061, 0x00ff, 'R', 3, "cbeq %1,x+,%p" },
+  { 0x0062, 0x00ff, ' ', 1, "nsa" },
+  { 0x0063, 0x00ff, ' ', 2, "com %1,x" },
+  { 0x0064, 0x00ff, ' ', 2, "lsr %1,x" },
+  { 0x0065, 0x00ff, ' ', 3, "cphx %w" },
+  { 0x0066, 0x00ff, ' ', 2, "ror %1,x" },
+  { 0x0067, 0x00ff, ' ', 2, "asr %1,x" },
+  { 0x0068, 0x00ff, ' ', 2, "lsl %1,x" },
+  { 0x0069, 0x00ff, ' ', 2, "rol %1,x" },
+  { 0x006a, 0x00ff, ' ', 2, "dec %1,x" },
+  { 0x006b, 0x00ff, 'R', 2, "dbnz %1,x,%p" },
+  { 0x006c, 0x00ff, ' ', 2, "inc %1,x" },
+  { 0x006d, 0x00ff, ' ', 2, "tst %1,x" },
+  { 0x006e, 0x00ff, ' ', 3, "mov %b,%d" },
+  { 0x006f, 0x00ff, ' ', 2, "clr %1,x" },
+
+/*
+  { 0x0070, 0x00ff, ' ', 2, "neg %b,sp" },
+  { 0x0071, 0x00ff, 'R', 3, "cbeq %b,sp,%d" },
+  { 0x0073, 0x00ff, ' ', 2, "com %b,sp" },
+  { 0x0074, 0x00ff, ' ', 2, "lsr %b,sp" },
+  { 0x0076, 0x00ff, ' ', 2, "ror %b,sp" },
+  { 0x0077, 0x00ff, ' ', 2, "asr %b,sp" },
+  { 0x0078, 0x00ff, ' ', 2, "lsl %b,sp" },
+  { 0x0079, 0x00ff, ' ', 2, "rol %b,sp" },
+  { 0x007a, 0x00ff, ' ', 2, "dec %b,sp" },
+  { 0x007b, 0x00ff, 'R', 2, "dbnz %b,sp,%d" },
+  { 0x007c, 0x00ff, ' ', 2, "inc %b,sp" },
+  { 0x007d, 0x00ff, ' ', 2, "tst %b,sp" },
+  { 0x007f, 0x00ff, ' ', 2, "clr %b,sp" },
+*/
+
+  { 0x0070, 0x00ff, ' ', 1, "neg ,x" },
+  { 0x0071, 0x00ff, 'R', 2, "cbeq ,x+,%p" },
+  { 0x0072, 0x00ff, ' ', 1, "daa" },
+  { 0x0073, 0x00ff, ' ', 1, "com ,x" },
+  { 0x0074, 0x00ff, ' ', 1, "lsr ,x" },
+  { 0x0075, 0x00ff, ' ', 2, "cphx %d" },
+  { 0x0076, 0x00ff, ' ', 1, "ror ,x" },
+  { 0x0077, 0x00ff, ' ', 1, "asr ,x" },
+  { 0x0078, 0x00ff, ' ', 1, "lsl ,x" },
+  { 0x0079, 0x00ff, ' ', 1, "rol ,x" },
+  { 0x007a, 0x00ff, ' ', 1, "dec ,x" },
+  { 0x007b, 0x00ff, 'R', 2, "dbnz ,x,%p" },
+  { 0x007c, 0x00ff, ' ', 1, "inc ,x" },
+  { 0x007d, 0x00ff, ' ', 1, "tst ,x" },
+  { 0x007e, 0x00ff, ' ', 2, "mov ,x+,%d" },
+  { 0x007f, 0x00ff, ' ', 1, "clr ,x" },
+
+  { 0x0080, 0x00ff, ' ', 1, "rti" },
+  { 0x0081, 0x00ff, ' ', 1, "rts" },
+  { 0x0082, 0x00ff, ' ', 1, "bgnd" },  //HCS08 only
+  { 0x0083, 0x00ff, ' ', 1, "swi", true },
+  { 0x0084, 0x00ff, ' ', 1, "tap" },
+  { 0x0085, 0x00ff, ' ', 1, "tpa" },
+  { 0x0086, 0x00ff, ' ', 1, "pula" },
+  { 0x0087, 0x00ff, ' ', 1, "psha" },
+  { 0x0088, 0x00ff, ' ', 1, "pulx" },
+  { 0x0089, 0x00ff, ' ', 1, "pshx" },
+  { 0x008a, 0x00ff, ' ', 1, "pulh" },
+  { 0x008b, 0x00ff, ' ', 1, "pshh" },
+  { 0x008c, 0x00ff, ' ', 1, "clrh" },
+  { 0x008e, 0x00ff, ' ', 1, "stop" },
+  { 0x008f, 0x00ff, ' ', 1, "wait" },
+
+  { 0x0090, 0x00ff, 'R', 2, "bge %p" },
+  { 0x0091, 0x00ff, 'R', 2, "blt %p" },
+  { 0x0092, 0x00ff, 'R', 2, "bgt %p" },
+  { 0x0093, 0x00ff, 'R', 2, "ble %p" },
+  { 0x0094, 0x00ff, ' ', 1, "txs" },
+  { 0x0095, 0x00ff, ' ', 1, "tsx" },
+  { 0x0096, 0x00ff, ' ', 3, "sthx %x" },  //HCS08 only
+  { 0x0097, 0x00ff, ' ', 1, "tax" },
+  { 0x0098, 0x00ff, ' ', 1, "clc" },
+  { 0x0099, 0x00ff, ' ', 1, "sec" },
+  { 0x009a, 0x00ff, ' ', 1, "cli" },
+  { 0x009b, 0x00ff, ' ', 1, "sei" },
+  { 0x009c, 0x00ff, ' ', 1, "rsp" },
+  { 0x009d, 0x00ff, ' ', 1, "nop" },
+  { 0x009f, 0x00ff, ' ', 1, "txa" },
+
+  { 0x00a0, 0x00ff, ' ', 2, "sub %b" },
+  { 0x00a1, 0x00ff, ' ', 2, "cmp %b" },
+  { 0x00a2, 0x00ff, ' ', 2, "sbc %b" },
+  { 0x00a3, 0x00ff, ' ', 2, "cpx %b" },
+  { 0x00a4, 0x00ff, ' ', 2, "and %b" },
+  { 0x00a5, 0x00ff, ' ', 2, "bit %b" },
+  { 0x00a6, 0x00ff, ' ', 2, "lda %b" },
+  { 0x00a7, 0x00ff, ' ', 2, "ais %s" },
+  { 0x00a8, 0x00ff, ' ', 2, "eor %b" },
+  { 0x00a9, 0x00ff, ' ', 2, "adc %b" },
+  { 0x00aa, 0x00ff, ' ', 2, "ora %b" },
+  { 0x00ab, 0x00ff, ' ', 2, "add %b" },
+  { 0x00ad, 0x00ff, 'R', 2, "bsr %d", true },
+  { 0x00ae, 0x00ff, ' ', 2, "ldx %b" },
+  { 0x00af, 0x00ff, ' ', 2, "aix %s" },
+
+  { 0x00b0, 0x00ff, ' ', 2, "sub %d" },
+  { 0x00b1, 0x00ff, ' ', 2, "cmp %d" },
+  { 0x00b2, 0x00ff, ' ', 2, "sbc %d" },
+  { 0x00b3, 0x00ff, ' ', 2, "cpx %d" },
+  { 0x00b4, 0x00ff, ' ', 2, "and %d" },
+  { 0x00b5, 0x00ff, ' ', 2, "bit %d" },
+  { 0x00b6, 0x00ff, ' ', 2, "lda %d" },
+  { 0x00b7, 0x00ff, ' ', 2, "sta %d" },
+  { 0x00b8, 0x00ff, ' ', 2, "eor %d" },
+  { 0x00b9, 0x00ff, ' ', 2, "adc %d" },
+  { 0x00ba, 0x00ff, ' ', 2, "ora %d" },
+  { 0x00bb, 0x00ff, ' ', 2, "add %d" },
+  { 0x00bc, 0x00ff, 'A', 2, "jmp %d" },
+  { 0x00bd, 0x00ff, 'A', 2, "jsr %d", true },
+  { 0x00be, 0x00ff, ' ', 2, "ldx %d" },
+  { 0x00bf, 0x00ff, ' ', 2, "stx %d" },
+
+  { 0x00c0, 0x00ff, ' ', 3, "sub %x" },
+  { 0x00c1, 0x00ff, ' ', 3, "cmp %x" },
+  { 0x00c2, 0x00ff, ' ', 3, "sbc %x" },
+  { 0x00c3, 0x00ff, ' ', 3, "cpx %x" },
+  { 0x00c4, 0x00ff, ' ', 3, "and %x" },
+  { 0x00c5, 0x00ff, ' ', 3, "bit %x" },
+  { 0x00c6, 0x00ff, ' ', 3, "lda %x" },
+  { 0x00c7, 0x00ff, ' ', 3, "sta %x" },
+  { 0x00c8, 0x00ff, ' ', 3, "eor %x" },
+  { 0x00c9, 0x00ff, ' ', 3, "adc %x" },
+  { 0x00ca, 0x00ff, ' ', 3, "ora %x" },
+  { 0x00cb, 0x00ff, ' ', 3, "add %x" },
+  { 0x00cc, 0x00ff, 'A', 3, "jmp %x" },
+  { 0x00cd, 0x00ff, 'A', 3, "jsr %x", true },
+  { 0x00ce, 0x00ff, ' ', 3, "ldx %x" },
+  { 0x00cf, 0x00ff, ' ', 3, "stx %x" },
+
+  { 0x00d0, 0x00ff, ' ', 3, "sub %2,x" },
+  { 0x00d1, 0x00ff, ' ', 3, "cmp %2,x" },
+  { 0x00d2, 0x00ff, ' ', 3, "sbc %2,x" },
+  { 0x00d3, 0x00ff, ' ', 3, "cpx %2,x" },
+  { 0x00d4, 0x00ff, ' ', 3, "and %2,x" },
+  { 0x00d5, 0x00ff, ' ', 3, "bit %2,x" },
+  { 0x00d6, 0x00ff, ' ', 3, "lda %2,x" },
+  { 0x00d7, 0x00ff, ' ', 3, "sta %2,x" },
+  { 0x00d8, 0x00ff, ' ', 3, "eor %2,x" },
+  { 0x00d9, 0x00ff, ' ', 3, "adc %2,x" },
+  { 0x00da, 0x00ff, ' ', 3, "ora %2,x" },
+  { 0x00db, 0x00ff, ' ', 3, "add %2,x" },
+  { 0x00dc, 0x00ff, ' ', 3, "jmp %2,x" },
+  { 0x00dd, 0x00ff, ' ', 3, "jsr %2,x", true },
+  { 0x00de, 0x00ff, ' ', 3, "ldx %2,x" },
+  { 0x00df, 0x00ff, ' ', 3, "stx %2,x" },
+
+  { 0x00e0, 0x00ff, ' ', 2, "sub %1,x" },
+  { 0x00e1, 0x00ff, ' ', 2, "cmp %1,x" },
+  { 0x00e2, 0x00ff, ' ', 2, "sbc %1,x" },
+  { 0x00e3, 0x00ff, ' ', 2, "cpx %1,x" },
+  { 0x00e4, 0x00ff, ' ', 2, "and %1,x" },
+  { 0x00e5, 0x00ff, ' ', 2, "bit %1,x" },
+  { 0x00e6, 0x00ff, ' ', 2, "lda %1,x" },
+  { 0x00e7, 0x00ff, ' ', 2, "sta %1,x" },
+  { 0x00e8, 0x00ff, ' ', 2, "eor %1,x" },
+  { 0x00e9, 0x00ff, ' ', 2, "adc %1,x" },
+  { 0x00ea, 0x00ff, ' ', 2, "ora %1,x" },
+  { 0x00eb, 0x00ff, ' ', 2, "add %1,x" },
+  { 0x00ec, 0x00ff, ' ', 2, "jmp %1,x" },
+  { 0x00ed, 0x00ff, ' ', 2, "jsr %1,x", true },
+  { 0x00ee, 0x00ff, ' ', 2, "ldx %1,x" },
+  { 0x00ef, 0x00ff, ' ', 2, "stx %1,x" },
+
+  { 0x00f0, 0x00ff, ' ', 1, "sub ,x" },
+  { 0x00f1, 0x00ff, ' ', 1, "cmp ,x" },
+  { 0x00f2, 0x00ff, ' ', 1, "sbc ,x" },
+  { 0x00f3, 0x00ff, ' ', 1, "cpx ,x" },
+  { 0x00f4, 0x00ff, ' ', 1, "and ,x" },
+  { 0x00f5, 0x00ff, ' ', 1, "bit ,x" },
+  { 0x00f6, 0x00ff, ' ', 1, "lda ,x" },
+  { 0x00f7, 0x00ff, ' ', 1, "sta ,x" },
+  { 0x00f8, 0x00ff, ' ', 1, "eor ,x" },
+  { 0x00f9, 0x00ff, ' ', 1, "adc ,x" },
+  { 0x00fa, 0x00ff, ' ', 1, "ora ,x" },
+  { 0x00fb, 0x00ff, ' ', 1, "add ,x" },
+  { 0x00fc, 0x00ff, ' ', 1, "jmp ,x" },
+  { 0x00fd, 0x00ff, ' ', 1, "jsr ,x", true },
+  { 0x00fe, 0x00ff, ' ', 1, "ldx ,x" },
+  { 0x00ff, 0x00ff, ' ', 1, "stx ,x" },
+
+  { 0, 0, 0, 0, NULL }
+};
+
+
+struct dis_entry disass_hc08_9e[]= {
+  { 0x0060, 0x00ff, ' ', 2, "neg %1,sp" },
+  { 0x0061, 0x00ff, 'R', 3, "cbeq %1,sp,%p" },
+  { 0x0063, 0x00ff, ' ', 2, "com %1,sp" },
+  { 0x0064, 0x00ff, ' ', 2, "lsr %1,sp" },
+  { 0x0066, 0x00ff, ' ', 2, "ror %1,sp" },
+  { 0x0067, 0x00ff, ' ', 2, "asr %1,sp" },
+  { 0x0068, 0x00ff, ' ', 2, "lsl %1,sp" },
+  { 0x0069, 0x00ff, ' ', 2, "rol %1,sp" },
+  { 0x006a, 0x00ff, ' ', 2, "dec %1,sp" },
+  { 0x006b, 0x00ff, 'R', 2, "dbnz %1,sp,%p" },
+  { 0x006c, 0x00ff, ' ', 2, "inc %1,sp" },
+  { 0x006d, 0x00ff, ' ', 2, "tst %1,sp" },
+  { 0x006f, 0x00ff, ' ', 2, "clr %1,sp" },
+
+  { 0x00ae, 0x00ff, ' ', 1, "ldhx ,x" },  //HCS08 only
+
+  { 0x00be, 0x00ff, ' ', 3, "ldhx %2,x" },  //HCS08 only
+
+  { 0x00ce, 0x00ff, ' ', 2, "ldhx %1,x" },  //HCS08 only
+
+  { 0x00d0, 0x00ff, ' ', 3, "sub %2,sp" },
+  { 0x00d1, 0x00ff, ' ', 3, "cmp %2,sp" },
+  { 0x00d2, 0x00ff, ' ', 3, "sbc %2,sp" },
+  { 0x00d3, 0x00ff, ' ', 3, "cpx %2,sp" },
+  { 0x00d4, 0x00ff, ' ', 3, "and %2,sp" },
+  { 0x00d5, 0x00ff, ' ', 3, "bit %2,sp" },
+  { 0x00d6, 0x00ff, ' ', 3, "lda %2,sp" },
+  { 0x00d7, 0x00ff, ' ', 3, "sta %2,sp" },
+  { 0x00d8, 0x00ff, ' ', 3, "eor %2,sp" },
+  { 0x00d9, 0x00ff, ' ', 3, "adc %2,sp" },
+  { 0x00da, 0x00ff, ' ', 3, "ora %2,sp" },
+  { 0x00db, 0x00ff, ' ', 3, "add %2,sp" },
+  { 0x00de, 0x00ff, ' ', 3, "ldx %2,sp" },
+  { 0x00df, 0x00ff, ' ', 3, "stx %2,sp" },
+
+  { 0x00e0, 0x00ff, ' ', 2, "sub %1,sp" },
+  { 0x00e1, 0x00ff, ' ', 2, "cmp %1,sp" },
+  { 0x00e2, 0x00ff, ' ', 2, "sbc %1,sp" },
+  { 0x00e3, 0x00ff, ' ', 2, "cpx %1,sp" },
+  { 0x00e4, 0x00ff, ' ', 2, "and %1,sp" },
+  { 0x00e5, 0x00ff, ' ', 2, "bit %1,sp" },
+  { 0x00e6, 0x00ff, ' ', 2, "lda %1,sp" },
+  { 0x00e7, 0x00ff, ' ', 2, "sta %1,sp" },
+  { 0x00e8, 0x00ff, ' ', 2, "eor %1,sp" },
+  { 0x00e9, 0x00ff, ' ', 2, "adc %1,sp" },
+  { 0x00ea, 0x00ff, ' ', 2, "ora %1,sp" },
+  { 0x00eb, 0x00ff, ' ', 2, "add %1,sp" },
+  { 0x00ee, 0x00ff, ' ', 2, "ldx %1,sp" },
+  { 0x00ef, 0x00ff, ' ', 2, "stx %1,sp" },
+
+  { 0x00f3, 0x00ff, ' ', 2, "cphx %1,sp" },  //HCS08 only
+  { 0x00fe, 0x00ff, ' ', 2, "ldhx %1,sp" },  //HCS08 only
+  { 0x00ff, 0x00ff, ' ', 2, "sthx %1,sp" },  //HCS08 only
+
+  { 0, 0, 0, 0, NULL }
+};
+
+
+/* glob.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m68hc08.src/glob.h sdcc-4.2.0+dfsg/sim/ucsim/m68hc08.src/glob.h
--- sdcc-4.0.0+dfsg/sim/ucsim/m68hc08.src/glob.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m68hc08.src/glob.h	2003-10-15 05:14:36.000000000 +0000
@@ -0,0 +1,41 @@
+/*
+ * Simulator of microcontrollers (glob.h)
+ *
+ * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef GLOB_HEADER
+#define GLOB_HEADER
+
+#include "stypes.h"
+
+
+extern struct dis_entry disass_hc08[];
+
+extern struct dis_entry disass_hc08_9e[];
+
+
+#endif
+
+/* End of hc08.src/glob.h */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m68hc08.src/hc08mac.h sdcc-4.2.0+dfsg/sim/ucsim/m68hc08.src/hc08mac.h
--- sdcc-4.0.0+dfsg/sim/ucsim/m68hc08.src/hc08mac.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m68hc08.src/hc08mac.h	2020-03-27 20:18:53.000000000 +0000
@@ -0,0 +1,65 @@
+/*
+ * Simulator of microcontrollers (z80mac.h)
+ *
+ * some z80 code base from Karl Bongers karl@turbobit.com
+ *
+ * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+// shift positions
+#define BITPOS_C 0  // 1
+#define BITPOS_Z 1  // 2H
+#define BITPOS_N 2  // 4H
+#define BITPOS_I 3  // 8H
+#define BITPOS_H 4  // 10H
+#define BITPUS_V 7  // 80H
+
+#define store2(addr, val) { ram->write((t_addr) (addr) & 0xffff, (val >> 8) & 0xff); \
+                            ram->write((t_addr) (addr+1) & 0xffff, val & 0xff); \
+  			    vc.wr+=2; }
+#define store1(addr, val) { ram->write((t_addr) (addr), val); vc.wr++; }
+//#define get1(addr) ram->get((t_addr) (addr) & 0xffff)
+#define get1(addr) get_1(addr)
+//#define get2(addr) ((ram->get((t_addr) (addr) & 0xffff) << 8) | ram->get((t_addr) (addr+1) & 0xffff) )
+#define get2(addr) get_2(addr)
+//#define fetch2() ((fetch() << 8) | fetch() )
+#define fetch1() fetch()
+#define push2(val) {							\
+    t_addr sp_before= regs.SP;						\
+    store2(regs.SP-1,(val));						\
+    regs.SP-=2;								\
+    class cl_stack_op *so=						\
+      new cl_stack_push(instPC,val,sp_before,regs.SP);			\
+    so->init();								\
+    stack_write(so);							\
+  }
+#define push1(val) {							\
+    t_addr sp_before= regs.SP;						\
+    store1(regs.SP,(val));						\
+    regs.SP-=1;								\
+    class cl_stack_op *so=						\
+      new cl_stack_push(instPC,val,sp_before,regs.SP);			\
+    so->init();								\
+    stack_write(so);							\
+  }
+#define pop2(var) {var=get2(regs.SP+1); regs.SP+=2;}
+#define pop1(var) {var=get1(regs.SP+1); regs.SP+=1;}
+#define add_u16_disp(_w, _d) (( (unsigned short)(_w) + (char)(_d) ) & 0xffff)
+
+
+#define FLAG_SET(f) {regs.P |= f;}
+#define FLAG_CLEAR(f) {regs.P &= ~(f);}
+#define FLAG_ASSIGN(f,c) {regs.P = (c) ? regs.P | (f) : regs.P & ~(f);}
+#define FLAG_NZ(f) { \
+      regs.P = (regs.P & ~(BIT_N|BIT_Z)) \
+      | (((f) & 0xff) ? 0 : BIT_Z) \
+      | (((f) & 0x80) ? BIT_N : 0) \
+      ; }
+#define EA_IMM(c) ((((c) >> 4) & 0xf)==0xa)
+#define OPERAND(code,prefix) (EA_IMM(code) ? fetch() : get1(fetchea(code,prefix)))
+
+
+
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m68hc08.src/inst.cc sdcc-4.2.0+dfsg/sim/ucsim/m68hc08.src/inst.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/m68hc08.src/inst.cc	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m68hc08.src/inst.cc	2021-10-04 11:31:43.000000000 +0000
@@ -0,0 +1,1355 @@
+/*
+ * Simulator of microcontrollers (inst.cc)
+ *
+ * hc08 code base from Erik Petrich  epetrich@users.sourceforge.net
+ *
+ * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+//#include "ddconfig.h"
+
+//#include 
+//#include 
+
+// local
+#include "m68hc08cl.h"
+//#include "regshc08.h"
+#include "hc08mac.h"
+
+
+void
+cl_hc08::incx(void)
+{
+  int hx = (regs.H << 8) | (regs.X);
+  hx++;
+  regs.H = (hx >> 8) & 0xff;
+  regs.X = hx & 0xff;
+}
+
+int
+cl_hc08::fetch2(void)
+{
+  int result;
+  result = fetch() << 8;
+  result |= fetch();
+  tick(2);
+  return result;
+}
+
+int
+cl_hc08::fetchea(t_mem code, bool prefix)
+{
+  switch ((code >> 4) & 0x0f) {
+    case 0x0: 
+    case 0x1:
+    case 0x3:
+    case 0xb:
+      tick(1);
+      return fetch(); // Direct
+    case 0x7:
+    case 0xf:
+      tick(1); // extra cycle needed, even without fetch
+      return (regs.H << 8) | regs.X;  // IX
+    case 0x6:
+    case 0xe:
+      tick(1);
+      if (!prefix)
+        return ((unsigned char)fetch())+((regs.H << 8) | regs.X); // IX1
+      else
+        return ((unsigned char)fetch())+regs.SP; // SP1
+    case 0xd:
+      if (!prefix)
+        return fetch2()+((regs.H << 8) | regs.X); // IX2
+      else
+        return fetch2()+regs.SP; // SP2
+    case 0xc:
+      return fetch2();
+    default:
+      return(resHALT);
+  }
+}
+
+
+int
+cl_hc08::inst_nop(t_mem code, bool prefix)
+{
+  return(resGO);
+}
+
+
+int
+cl_hc08::inst_transfer(t_mem code, bool prefix)
+{
+  int hx;
+  
+  switch (code) {
+    case 0x84: // TAP
+      regs.P = regs.A | 0x60;
+      break;
+    case 0x85: // TPA
+      regs.A = regs.P | 0x60;
+      break;
+    case 0x97: // TAX
+      regs.X = regs.A;
+      break;
+    case 0x9f: // TXA
+      regs.A = regs.X;
+      break;
+    case 0x94: // TXS
+      hx = (regs.H << 8) | regs.X;
+      regs.SP = (hx - 1) & 0xffff;
+      break;
+    case 0x95: // TSX
+      hx = regs.SP +1;
+      regs.H = (hx >> 8) & 0xff;
+      regs.X = hx & 0xff;
+      break;
+    default:
+      return(resHALT);
+  }
+  return(resGO);
+}
+
+
+int
+cl_hc08::inst_setclearflags(t_mem code, bool prefix)
+{
+  switch (code) {
+    case 0x98:
+      regs.P &= ~BIT_C;
+      break;
+    case 0x99:
+      regs.P |= BIT_C;
+      break;
+    case 0x9a:
+      regs.P &= ~BIT_I;
+      break;
+    case 0x9b:
+      regs.P |= BIT_I;
+      break;
+    default:
+      return(resHALT);
+  }
+  return(resGO);
+}
+
+
+int
+cl_hc08::inst_rsp(t_mem code, bool prefix)
+{
+  regs.SP = 0x00ff;
+  return(resGO);
+}
+
+
+int
+cl_hc08::inst_nsa(t_mem code, bool prefix)
+{
+  regs.A = ((regs.A & 0xf0)>>4) | ((regs.A & 0x0f)<<4);
+  return(resGO);
+}
+
+
+
+int
+cl_hc08::inst_lda(t_mem code, bool prefix)
+{
+  regs.A = OPERAND(code, prefix);
+  tick(1);
+  FLAG_CLEAR(BIT_V);
+  FLAG_NZ(regs.A);
+  return(resGO);
+}
+
+int
+cl_hc08::inst_ldx(t_mem code, bool prefix)
+{
+  regs.X = OPERAND(code, prefix);
+  tick(1);
+  FLAG_CLEAR(BIT_V);
+  FLAG_NZ(regs.X);
+  return(resGO);
+}
+
+int
+cl_hc08::inst_sta(t_mem code, bool prefix)
+{
+  int ea = fetchea(code, prefix);
+
+  FLAG_CLEAR(BIT_V);
+  FLAG_NZ(regs.A);
+  store1(ea, regs.A);
+  tick(1);
+  return(resGO);
+}
+
+int
+cl_hc08::inst_stx(t_mem code, bool prefix)
+{
+  int ea = fetchea(code, prefix);
+
+  FLAG_CLEAR(BIT_V);
+  FLAG_NZ(regs.X);
+  store1(ea, regs.X);
+  tick(1);
+  return(resGO);
+}
+
+int
+cl_hc08::inst_add(t_mem code, bool prefix)
+{
+  int result, operand1, operand2;
+
+  operand1 = regs.A;
+  operand2 = OPERAND(code, prefix);
+  tick(1);
+  result = operand1 + operand2;
+  FLAG_NZ (result);
+  FLAG_ASSIGN (BIT_V, 0x80 & (operand1 ^ operand2 ^ result ^ (result >>1)));
+  FLAG_ASSIGN (BIT_C, 0x100 & result);
+  FLAG_ASSIGN (BIT_H, 0x10 & (operand1 ^ operand2 ^ result));
+
+  regs.A = result & 0xff;
+  return(resGO);
+}
+
+int
+cl_hc08::inst_adc(t_mem code, bool prefix)
+{
+  int result, operand1, operand2;
+  int carryin = (regs.P & BIT_C)!=0;
+
+  operand1 = regs.A;
+  operand2 = OPERAND(code, prefix);
+  tick(1);
+  result = operand1 + operand2 + carryin;
+  FLAG_NZ (result);
+  FLAG_ASSIGN (BIT_V, 0x80 & (operand1 ^ operand2 ^ result ^ (result >>1)));
+  FLAG_ASSIGN (BIT_C, 0x100 & result);
+  FLAG_ASSIGN (BIT_H, 0x10 & (operand1 ^ operand2 ^ result));
+
+  regs.A = result & 0xff;
+  return(resGO);
+}
+
+int
+cl_hc08::inst_sub(t_mem code, bool prefix)
+{
+  int result, operand1, operand2;
+
+  operand1 = regs.A;
+  operand2 = OPERAND(code, prefix);
+  tick(1);
+  result = operand1 - operand2;
+  FLAG_NZ (result);
+  FLAG_ASSIGN (BIT_V, 0x80 & (operand1 ^ operand2 ^ result ^ (result >>1)));
+  FLAG_ASSIGN (BIT_C, 0x100 & result);
+
+  regs.A = result & 0xff;
+  return(resGO);
+}
+
+int
+cl_hc08::inst_sbc(t_mem code, bool prefix)
+{
+  int result, operand1, operand2;
+  int carryin = (regs.P & BIT_C)!=0;
+
+  operand1 = regs.A;
+  operand2 = OPERAND(code, prefix);
+  tick(1);
+  result = operand1 - operand2 - carryin;
+  FLAG_NZ (result);
+  FLAG_ASSIGN (BIT_V, 0x80 & (operand1 ^ operand2 ^ result ^ (result >>1)));
+  FLAG_ASSIGN (BIT_C, 0x100 & result);
+
+  regs.A = result & 0xff;
+  return(resGO);
+}
+
+int
+cl_hc08::inst_cmp(t_mem code, bool prefix)
+{
+  int result, operand1, operand2;
+
+  operand1 = regs.A;
+  operand2 = OPERAND(code, prefix);
+  tick(1);
+  result = operand1 - operand2;
+  FLAG_NZ (result);
+  FLAG_ASSIGN (BIT_V, 0x80 & (operand1 ^ operand2 ^ result ^ (result >>1)));
+  FLAG_ASSIGN (BIT_C, 0x100 & result);
+
+  return(resGO);
+}
+
+int
+cl_hc08::inst_cpx(t_mem code, bool prefix)
+{
+  int result, operand1, operand2;
+
+  operand1 = regs.X;
+  operand2 = OPERAND(code, prefix);
+  tick(1);
+  result = operand1 - operand2;
+  FLAG_NZ (result);
+  FLAG_ASSIGN (BIT_V, 0x80 & (operand1 ^ operand2 ^ result ^ (result >>1)));
+  FLAG_ASSIGN (BIT_C, 0x100 & result);
+
+  return(resGO);
+}
+
+int
+cl_hc08::inst_jmp(t_mem code, bool prefix)
+{
+  PC = fetchea(code, prefix);
+  tick(1); // extra cycle to reload pipeline
+  return(resGO);
+}
+
+int
+cl_hc08::inst_jsr(t_mem code, bool prefix)
+{
+  int newPC = fetchea(code, prefix);
+
+  push2(PC);
+  tick(2);
+  PC = newPC;
+  tick(1); // extra cycle to reload pipeline
+
+  return(resGO);
+}
+
+int
+cl_hc08::inst_bsr(t_mem code, bool prefix)
+{
+  signed char ofs = fetch();
+
+  push2(PC);
+  tick(2);
+  PC += ofs;
+  tick(1); // extra cycle to reload pipeline
+
+  return(resGO);
+}
+
+int
+cl_hc08::inst_ais(t_mem code, bool prefix)
+{
+  regs.SP = regs.SP + (signed char)fetch();
+  return(resGO);
+}
+
+int
+cl_hc08::inst_aix(t_mem code, bool prefix)
+{
+  int hx = (regs.H << 8) | (regs.X);
+  hx += (signed char)fetch();
+  tick(1);
+  regs.H = (hx >> 8) & 0xff;
+  regs.X = hx & 0xff;
+  return(resGO);
+}
+
+int
+cl_hc08::inst_and(t_mem code, bool prefix)
+{
+  regs.A = regs.A & OPERAND(code, prefix);
+  tick(1);
+  FLAG_CLEAR(BIT_V);
+  FLAG_NZ(regs.A);
+  return(resGO);
+}
+
+int
+cl_hc08::inst_bit(t_mem code, bool prefix)
+{
+  uchar operand = regs.A & OPERAND(code, prefix);
+  tick(1);
+  FLAG_CLEAR(BIT_V);
+  FLAG_NZ(operand);
+  return(resGO);
+}
+
+int
+cl_hc08::inst_ora(t_mem code, bool prefix)
+{
+  regs.A = regs.A | OPERAND(code, prefix);
+  tick(1);
+  FLAG_CLEAR(BIT_V);
+  FLAG_NZ(regs.A);
+  return(resGO);
+}
+
+int
+cl_hc08::inst_eor(t_mem code, bool prefix)
+{
+  regs.A = regs.A ^ OPERAND(code, prefix);
+  tick(1);
+  FLAG_CLEAR(BIT_V);
+  FLAG_NZ(regs.A);
+  return(resGO);
+}
+
+int
+cl_hc08::inst_asr(t_mem code, bool prefix)
+{
+  int ea = 0xffff;
+  uchar operand;
+  
+  if ((code & 0xf0) == 0x40)
+    operand = regs.A;
+  else if ((code & 0xf0) == 0x50)
+    operand = regs.X;
+  else {
+    ea = fetchea(code,prefix);
+    operand = get1(ea);
+    tick(1);
+  }
+
+  FLAG_ASSIGN (BIT_C, operand & 1);
+  operand = (operand >> 1) | (operand & 0x80);
+  FLAG_NZ (operand);
+  FLAG_ASSIGN (BIT_V, ((regs.P & BIT_C)!=0) ^ ((regs.P & BIT_N)!=0));
+
+  if ((code & 0xf0) == 0x40)
+    regs.A = operand;
+  else if ((code & 0xf0) == 0x50)
+    regs.X = operand;
+  else {
+    store1(ea, operand);
+    tick(1);
+    if ((code & 0x70) != 0x70)
+      tick(1);
+  }
+
+  return(resGO);
+}
+
+
+int
+cl_hc08::inst_lsr(t_mem code, bool prefix)
+{
+  int ea = 0xffff;
+  uchar operand;
+  
+  if ((code & 0xf0) == 0x40)
+    operand = regs.A;
+  else if ((code & 0xf0) == 0x50)
+    operand = regs.X;
+  else {
+    ea = fetchea(code,prefix);
+    operand = get1(ea);
+    tick(1);
+  }
+
+  FLAG_ASSIGN (BIT_C, operand & 1);
+  operand = (operand >> 1) & 0x7f;
+  FLAG_NZ (operand);
+  FLAG_ASSIGN (BIT_V, ((regs.P & BIT_C)!=0) ^ ((regs.P & BIT_N)!=0));
+
+  if ((code & 0xf0) == 0x40)
+    regs.A = operand;
+  else if ((code & 0xf0) == 0x50)
+    regs.X = operand;
+  else {
+    store1(ea, operand);
+    tick(1);
+    if ((code & 0x70) != 0x70)
+      tick(1);
+  }
+  return(resGO);
+}
+
+
+int
+cl_hc08::inst_lsl(t_mem code, bool prefix)
+{
+  int ea = 0xffff;
+  uchar operand;
+  
+  if ((code & 0xf0) == 0x40)
+    operand = regs.A;
+  else if ((code & 0xf0) == 0x50)
+    operand = regs.X;
+  else {
+    ea = fetchea(code,prefix);
+    operand = get1(ea);
+    tick(1);
+  }
+
+  FLAG_ASSIGN (BIT_C, operand & 0x80);
+  operand = (operand << 1);
+  FLAG_NZ (operand);
+  FLAG_ASSIGN (BIT_V, ((regs.P & BIT_C)!=0) ^ ((regs.P & BIT_N)!=0));
+
+  if ((code & 0xf0) == 0x40)
+    regs.A = operand;
+  else if ((code & 0xf0) == 0x50)
+    regs.X = operand;
+  else {
+    store1(ea, operand);
+    tick(1);
+    if ((code & 0x70) != 0x70)
+      tick(1);
+  }
+  return(resGO);
+}
+
+
+int
+cl_hc08::inst_rol(t_mem code, bool prefix)
+{
+  uchar c = (regs.P & BIT_C)!=0;
+  int ea = 0xffff;
+  uchar operand;
+  
+  if ((code & 0xf0) == 0x40)
+    operand = regs.A;
+  else if ((code & 0xf0) == 0x50)
+    operand = regs.X;
+  else {
+    ea = fetchea(code,prefix);
+    operand = get1(ea);
+    tick(1);
+  }
+
+  FLAG_ASSIGN (BIT_C, operand & 0x80);
+  operand = (operand << 1) | c;
+  FLAG_NZ (operand);
+  FLAG_ASSIGN (BIT_V, ((regs.P & BIT_C)!=0) ^ ((regs.P & BIT_N)!=0));
+
+  if ((code & 0xf0) == 0x40)
+    regs.A = operand;
+  else if ((code & 0xf0) == 0x50)
+    regs.X = operand;
+  else {
+    store1(ea, operand);
+    tick(1);
+    if ((code & 0x70) != 0x70)
+      tick(1);
+  }
+  return(resGO);
+}
+
+
+int
+cl_hc08::inst_ror(t_mem code, bool prefix)
+{
+  uchar c = (regs.P & BIT_C)!=0;
+  int ea = 0xffff;
+  uchar operand;
+  
+  if ((code & 0xf0) == 0x40)
+    operand = regs.A;
+  else if ((code & 0xf0) == 0x50)
+    operand = regs.X;
+  else {
+    ea = fetchea(code,prefix);
+    operand = get1(ea);
+    tick(1);
+  }
+
+  FLAG_ASSIGN (BIT_C, operand & 1);
+  operand = (operand >> 1) | (c << 7);
+  FLAG_NZ (operand);
+  FLAG_ASSIGN (BIT_V, ((regs.P & BIT_C)!=0) ^ ((regs.P & BIT_N)!=0));
+
+  if ((code & 0xf0) == 0x40)
+    regs.A = operand;
+  else if ((code & 0xf0) == 0x50)
+    regs.X = operand;
+  else {
+    store1(ea, operand);
+    tick(1);
+    if ((code & 0x70) != 0x70)
+      tick(1);
+  }
+  return(resGO);
+}
+
+
+int
+cl_hc08::inst_inc(t_mem code, bool prefix)
+{
+  int ea = 0xffff;
+  uchar operand;
+  
+  if ((code & 0xf0) == 0x40)
+    operand = regs.A;
+  else if ((code & 0xf0) == 0x50)
+    operand = regs.X;
+  else {
+    ea = fetchea(code,prefix);
+    operand = get1(ea);
+    tick(1);
+  }
+
+  operand++;
+  FLAG_NZ (operand);
+  FLAG_ASSIGN (BIT_V, operand == 0x80);
+
+  if ((code & 0xf0) == 0x40)
+    regs.A = operand;
+  else if ((code & 0xf0) == 0x50)
+    regs.X = operand;
+  else {
+    store1(ea, operand);
+    tick(1);
+    if ((code & 0x70) != 0x70)
+      tick(1);
+  }
+  return(resGO);
+}
+
+
+int
+cl_hc08::inst_dec(t_mem code, bool prefix)
+{
+  int ea = 0xffff;
+  uchar operand;
+  
+  if ((code & 0xf0) == 0x40)
+    operand = regs.A;
+  else if ((code & 0xf0) == 0x50)
+    operand = regs.X;
+  else {
+    ea = fetchea(code,prefix);
+    operand = get1(ea);
+    tick(1);
+  }
+
+  operand--;
+  FLAG_NZ (operand);
+  FLAG_ASSIGN (BIT_V, operand == 0x7f);
+
+  if ((code & 0xf0) == 0x40)
+    regs.A = operand;
+  else if ((code & 0xf0) == 0x50)
+    regs.X = operand;
+  else {
+    store1(ea, operand);
+    tick(1);
+    if ((code & 0x70) != 0x70)
+      tick(1);
+  }
+  return(resGO);
+}
+
+int
+cl_hc08::inst_dbnz(t_mem code, bool prefix)
+{
+  int ea = 0xffff;
+  uchar operand;
+  signed char ofs;
+  
+  if ((code & 0xf0) == 0x40)
+    operand = regs.A;
+  else if ((code & 0xf0) == 0x50)
+    operand = regs.X;
+  else {
+    ea = fetchea(code,prefix);
+    operand = get1(ea);
+    tick(1);
+  }
+
+  operand--;
+  FLAG_NZ (operand);
+  FLAG_ASSIGN (BIT_V, operand == 0x7f);
+
+  if ((code & 0xf0) == 0x40)
+    regs.A = operand;
+  else if ((code & 0xf0) == 0x50)
+    regs.X = operand;
+  else {
+    store1(ea, operand);
+    tick(1);
+    if ((code & 0x70) != 0x70)
+      tick(1);
+  }
+
+  ofs = fetch();
+  tick(1);
+  if (operand)
+    PC += ofs;
+  tick(1); // extra cycle to reload pipeline
+
+  return(resGO);
+}
+
+
+int
+cl_hc08::inst_tst(t_mem code, bool prefix)
+{
+  int ea = 0xffff;
+  uchar operand;
+
+  if ((code & 0xf0) == 0x40)
+    operand = regs.A;
+  else if ((code & 0xf0) == 0x50)
+    operand = regs.X;
+  else {
+    ea = fetchea(code,prefix);
+    operand = get1(ea);
+    tick(1);
+  }
+
+  FLAG_NZ (operand);
+  FLAG_CLEAR (BIT_V);
+  if ((code & 0xf0) == 0x30 || (code & 0xf0) == 0x60)
+    tick(1);
+
+  return(resGO);
+}
+
+
+int
+cl_hc08::inst_clr(t_mem code, bool prefix)
+{
+  int ea = 0xffff;
+  uchar operand;
+
+  // clr uses read-modify-write cycles, so simulate the read even if the data isn't used
+  if ((code & 0xf0) == 0x40)
+    operand = regs.A;
+  else if ((code & 0xf0) == 0x50)
+    operand = regs.X;
+  else {
+    ea = fetchea(code,prefix);
+    operand = get1(ea);
+    tick(1);
+  }
+
+  operand = 0;
+  FLAG_CLEAR (BIT_V);
+  FLAG_CLEAR (BIT_N);
+  FLAG_SET (BIT_Z);
+
+  if ((code & 0xf0) == 0x40)
+    regs.A = operand;
+  else if ((code & 0xf0) == 0x50)
+    regs.X = operand;
+  else {
+    store1(ea, operand);
+    if ((code & 0x70) != 0x70)
+      tick(1);
+  }
+  return(resGO);
+}
+
+
+int
+cl_hc08::inst_clrh(t_mem code, bool prefix)
+{
+  FLAG_CLEAR (BIT_V);
+  FLAG_CLEAR (BIT_N);
+  FLAG_SET (BIT_Z);
+  regs.H = 0;
+  return(resGO);
+}
+
+
+int
+cl_hc08::inst_com(t_mem code, bool prefix)
+{
+  int ea = 0xffff;
+  uchar operand;
+  
+  if ((code & 0xf0) == 0x40)
+    operand = regs.A;
+  else if ((code & 0xf0) == 0x50)
+    operand = regs.X;
+  else {
+    ea = fetchea(code,prefix);
+    operand = get1(ea);
+    tick(1);
+  }
+
+  operand = ~operand;
+  FLAG_SET (BIT_C);
+  FLAG_NZ (operand);
+  FLAG_CLEAR (BIT_V);
+
+  if ((code & 0xf0) == 0x40)
+    regs.A = operand;
+  else if ((code & 0xf0) == 0x50)
+    regs.X = operand;
+  else {
+    store1(ea, operand);
+    if ((code & 0x70) != 0x70)
+      tick(1);
+  }
+  return(resGO);
+}
+
+
+int
+cl_hc08::inst_neg(t_mem code, bool prefix)
+{
+  int ea = 0xffff;
+  uchar operand;
+  
+  if ((code & 0xf0) == 0x40)
+    operand = regs.A;
+  else if ((code & 0xf0) == 0x50)
+    operand = regs.X;
+  else {
+    ea = fetchea(code,prefix);
+    operand = get1(ea);
+    tick(1);
+  }
+
+  FLAG_ASSIGN (BIT_V, operand==0x80);
+  FLAG_ASSIGN (BIT_C, operand!=0x00);
+  operand = -operand;
+  FLAG_NZ (operand);
+
+  if ((code & 0xf0) == 0x40)
+    regs.A = operand;
+  else if ((code & 0xf0) == 0x50)
+    regs.X = operand;
+  else {
+    store1(ea, operand);
+    if ((code & 0x70) != 0x70)
+      tick(1);
+  }
+  return(resGO);
+}
+
+
+
+int
+cl_hc08::inst_pushpull(t_mem code, bool prefix)
+{
+  switch (code) {
+    case 0x86:
+      pop1(regs.A);
+      tick(2);
+      break;
+    case 0x87:
+      push1(regs.A);
+      tick(1);
+      break;
+    case 0x88:
+      pop1(regs.X);
+      tick(2);
+      break;
+    case 0x89:
+      push1(regs.X);
+      tick(1);
+      break;
+    case 0x8a:
+      pop1(regs.H);
+      tick(2);
+      break;
+    case 0x8b:
+      push1(regs.H);
+      tick(1);
+      break;
+    default:
+      return(resHALT);
+  }
+  return(resGO);
+}
+
+
+
+
+int
+cl_hc08::inst_stop(t_mem code, bool prefix)
+{
+  FLAG_CLEAR (BIT_I);
+  return(resGO);
+}
+
+
+int
+cl_hc08::inst_wait(t_mem code, bool prefix)
+{
+  FLAG_CLEAR (BIT_I);
+  return(resGO);
+}
+
+
+int
+cl_hc08::inst_daa(t_mem code, bool prefix)
+{
+  uchar lsn, msn;
+
+  lsn = regs.A & 0xf;
+  msn = (regs.A >> 4) & 0xf;
+  if (regs.P & BIT_H) {
+    lsn += 16;
+    msn = (msn-1) & 0xf;
+  }
+  if (regs.P & BIT_C)
+    msn += 16;
+
+  FLAG_CLEAR (BIT_C);
+  while (lsn>9) {
+    lsn -= 10;
+    msn++;
+  }
+  if (msn>9) {
+    msn = msn % 10;
+    FLAG_SET (BIT_C);
+  }
+
+  return(resGO);
+}
+
+int
+cl_hc08::inst_mul(t_mem code, bool prefix)
+{
+  int result = regs.A * regs.X;
+  regs.A = result & 0xff;
+  regs.X = (result >> 8) & 0xff;
+  FLAG_CLEAR (BIT_C);
+  FLAG_CLEAR (BIT_H);
+  tick(4);
+  return(resGO);
+}
+
+int
+cl_hc08::inst_div(t_mem code, bool prefix)
+{
+  unsigned int dividend = (regs.H << 8) | regs.A;
+  unsigned int quotient;
+
+  if (regs.X) {
+    quotient = dividend / (unsigned int)regs.X;
+    if (quotient<=0xff) {
+      regs.A = quotient;
+      regs.H = dividend % regs.X;
+      FLAG_CLEAR (BIT_C);
+      FLAG_ASSIGN (BIT_Z, quotient==0);
+    }
+    else
+      FLAG_SET (BIT_C);  // overflow
+  } else
+    FLAG_SET (BIT_C);    // division by zero
+  tick(5);
+
+  return(resGO);
+}
+
+
+int
+cl_hc08::inst_condbranch(t_mem code, bool prefix)
+{
+  bool taken;
+  signed char ofs;
+  unsigned char maskedP;
+  
+  if ((code & 0xf0)==0x20) {
+    switch ((code>>1) & 7) {
+      case 0: // BRA
+        taken = 1;
+        break;
+      case 1: // BHI
+        taken = !(regs.P & (BIT_C | BIT_Z));
+        break;
+      case 2: // BCC
+        taken = !(regs.P & BIT_C);
+        break;
+      case 3: // BNE
+        taken = !(regs.P & BIT_Z);
+        break;
+      case 4: // BHCC
+        taken = !(regs.P & BIT_H);
+        break;
+      case 5: // BPL
+        taken = !(regs.P & BIT_N);
+        break;
+      case 6: // BMC
+        taken = !(regs.P & BIT_I);
+        break;
+      case 7: // BIL
+        taken = 0; // TODO: should read simulated IRQ# pin
+	break;
+      default:
+        return(resHALT);
+    } 
+  }
+  else if ((code & 0xf0)==0x90) {
+    switch ((code>>1) & 7) {
+      case 0: // BGE
+        maskedP = regs.P & (BIT_N | BIT_V);
+        taken = !maskedP || (maskedP == (BIT_N | BIT_V));
+        break;
+      case 1: // BGT
+        maskedP = regs.P & (BIT_N | BIT_V | BIT_Z);
+        taken = !maskedP || (maskedP == (BIT_N | BIT_V));
+        break;
+      default:
+        return(resHALT);
+    }
+  }
+  else
+    return(resHALT);
+  
+  if (code & 1)
+    taken = ! taken;
+  
+  ofs = fetch();
+  tick(1);
+  if (taken)
+    PC += ofs;
+  tick(1); // extra cycle to reload pipeline
+
+  return(resGO);
+}
+
+int
+cl_hc08::inst_bitsetclear(t_mem code, bool prefix)
+{
+  uchar bit = (code >> 1) & 7;
+  int ea = fetchea(code, prefix);
+  uchar operand = get1(ea);
+  tick(1);
+
+  if (code & 1)
+    operand &= ~(1 << bit);
+  else
+    operand |= (1 << bit);
+  tick(1);
+  store1(ea, operand);
+  tick(1);
+  return(resGO);
+}
+
+int
+cl_hc08::inst_bittestsetclear(t_mem code, bool prefix)
+{
+  uchar bit = (code >> 1) & 7;
+  int ea = fetchea(code, prefix);
+  uchar operand = get1(ea);
+  signed char ofs;
+  bool taken;
+
+  tick(1);
+  if (code & 1)
+    taken = !(operand & (1 << bit));  // brclr
+  else
+    taken = (operand & (1 << bit));   // brset
+
+  ofs = fetch();
+  tick(1);
+  if (taken)
+    PC += ofs;
+  tick(1); // extra cycle to reload pipeline
+
+  FLAG_ASSIGN (BIT_C, operand & (1 << bit));
+  return(resGO);
+}
+
+int
+cl_hc08::inst_cbeq(t_mem code, bool prefix)
+{
+  int ea;
+  uchar operand1, operand2;
+  signed char ofs;
+    
+  if ((code & 0xf0) == 0x40) {
+    operand1 = regs.A;
+    operand2 = fetch();
+    tick(1);
+  }
+  else if ((code & 0xf0) == 0x50) {
+    operand1 = regs.X;
+    operand2 = fetch();
+    tick(1);
+  }
+  else {
+    ea = fetchea(code,prefix);
+    operand1 = get1(ea);
+    tick(1);
+    operand2 = regs.A;
+  }
+
+  ofs = fetch();
+  tick(1);
+  if (operand1==operand2)
+    PC += ofs;  
+
+  if (code == 0x71 || (!prefix && code == 0x61))
+    incx();
+  tick(1); // extra cycle to reload pipeline
+
+  return(resGO);
+}
+
+int
+cl_hc08::inst_rti(t_mem code, bool prefix)
+{
+  pop1(regs.P);
+  tick(1);
+  regs.P |= 0x60;
+  pop1(regs.A);
+  tick(1);
+  pop1(regs.X);
+  tick(1);
+  pop2(PC);
+  tick(2);
+  tick(3); // pipeline reload and some extra overhead?
+
+  return(resGO);
+}
+
+int
+cl_hc08::inst_rts(t_mem code, bool prefix)
+{
+  pop2(PC);
+  tick(2);
+  tick(3); // pipeline reload and some extra overhead?
+
+  return(resGO);
+}
+
+
+int
+cl_hc08::inst_mov(t_mem code, bool prefix)
+{
+  int ea;
+  uchar operand;
+  bool aix;
+  int hx = (regs.H << 8) | (regs.X);
+  
+  switch (code) {
+    case 0x4e:	//mov opr8a,opr8a
+      operand = get1(fetch());
+      tick(2);
+      ea = fetch();
+      tick(1);
+      aix = 0;
+      break;
+    case 0x5e:	//mov opr8a,x+
+      operand = get1(fetch());
+      tick(2);
+      tick(1);
+      ea = hx;
+      aix = 1;
+      break;
+    case 0x6e:	//mov #opr8i,opr8a
+      operand = fetch();
+      tick(1);
+      ea = fetch();
+      tick(1);
+      aix = 0;
+      break;
+    case 0x7e:	//mov x+,opr8a
+      operand = get1(hx);
+      tick(1);
+      ea = fetch();
+      tick(1);
+      tick(1);
+      aix = 1;
+      break;
+    default:
+      return(resHALT);
+  }
+
+  store1(ea, operand);
+  tick(1);
+  if (aix)
+    incx();
+
+  FLAG_NZ(operand);
+  FLAG_CLEAR(BIT_V);
+
+  return(resGO);
+}
+
+
+int
+cl_hc08::inst_sthx(t_mem code, bool prefix)
+{
+  int ea;
+  
+  if (code == 0x35) {
+    ea = fetch();
+    tick(1);
+  }
+  else if ((code == 0x96) && (type->type == CPU_HCS08))
+  {
+    ea = fetch2();
+    tick(2);
+  }
+  else if (prefix && (code == 0xff) && (type->type == CPU_HCS08))
+  {
+    ea = regs.SP + fetch();
+    tick(1);
+  }
+  else
+    return(resINV_INST);
+  
+  store1(ea, regs.H);
+  tick(1);
+  store1((ea+1) & 0xffff, regs.X);
+  tick(1);
+
+  FLAG_CLEAR(BIT_V);
+  FLAG_ASSIGN(BIT_N, regs.H & 0x80);
+  FLAG_ASSIGN(BIT_Z, !regs.X && !regs.H);
+  return(resGO);
+}
+
+int
+cl_hc08::inst_ldhx(t_mem code, bool prefix)
+{
+  int ea;
+  
+  if (code == 0x45) {
+    regs.H = fetch();
+    tick(1);
+    regs.X = fetch();
+    tick(1);
+  }
+  else if (code == 0x55) {
+    ea = fetch();
+    tick(1);
+    regs.H = get1(ea);
+    tick(1);
+    regs.X = get1(ea+1);
+    tick(1);
+  }
+  else if ((code == 0x32) && (type->type == CPU_HCS08)) {
+    ea = fetch2();
+    tick(2);
+    regs.H = get1(ea);
+    tick(1);
+    regs.X = get1(ea+1);
+    tick(1);
+  }
+  else if (prefix && (code == 0xae) && (type->type == CPU_HCS08)) {
+    ea = (regs.H << 8) | regs.X;
+    tick(1);
+    regs.H = get1(ea);
+    tick(1);
+    regs.X = get1(ea+1);
+    tick(1);
+  }
+  else if (prefix && (code == 0xbe) && (type->type == CPU_HCS08)) {
+    ea = ((regs.H << 8) | regs.X) + fetch2();
+    tick(2);
+    regs.H = get1(ea);
+    tick(1);
+    regs.X = get1(ea+1);
+    tick(1);
+  }
+  else if (prefix && (code == 0xce) && (type->type == CPU_HCS08)) {
+    ea = ((regs.H << 8) | regs.X) + fetch();
+    tick(1);
+    regs.H = get1(ea);
+    tick(1);
+    regs.X = get1(ea+1);
+    tick(1);
+  }
+  else if (prefix && (code == 0xfe) && (type->type == CPU_HCS08)) {
+    ea = regs.SP + fetch();
+    tick(1);
+    regs.H = get1(ea);
+    tick(1);
+    regs.X = get1(ea+1);
+    tick(1);
+  }
+  else
+    return(resINV_INST);
+  
+  FLAG_CLEAR(BIT_V);
+  FLAG_ASSIGN(BIT_N, regs.H & 0x80);
+  FLAG_ASSIGN(BIT_Z, !regs.X && !regs.H);
+  return(resGO);
+}
+
+
+int
+cl_hc08::inst_cphx(t_mem code, bool prefix)
+{
+  int ea;
+  int hx;
+  int operand;
+  int result;
+  
+  if (code == 0x65) {
+    operand = fetch2();
+    tick(2);
+  }
+  else if (code == 0x75) {
+    ea = fetch();
+    tick(1);
+    operand = (get1(ea) << 8) | get1(ea+1);
+    tick(2);
+    tick(1);
+  }
+  else if ((code == 0x3e) && (type->type == CPU_HCS08)) {
+    ea = fetch2();
+    tick(2);
+    operand = (get1(ea) << 8) | get1(ea+1);
+    tick(2);
+    tick(1);
+  }
+  else if (prefix && (code == 0xf3) && (type->type == CPU_HCS08)) {
+    ea = ((unsigned char)fetch())+regs.SP;
+    tick(1);
+    operand = (get1(ea) << 8) | get1(ea+1);
+    tick(2);
+    tick(1);
+  }
+  else
+    return(resINV_INST);
+
+  hx = (regs.H << 8) | regs.X;
+  result = hx-operand;
+
+  FLAG_ASSIGN (BIT_V, 0x8000 & (hx ^ operand ^ result ^ (result>>1)));
+  FLAG_ASSIGN (BIT_C, 0x10000 & result);
+  FLAG_ASSIGN(BIT_N, result & 0x8000);
+  FLAG_ASSIGN(BIT_Z, !(result & 0xffff));
+
+  return(resGO);
+}
+
+int
+cl_hc08::inst_swi(t_mem code, bool prefix)
+{
+  push2(PC);
+  tick(2);
+  push1(regs.X);
+  tick(1);
+  push1(regs.A);
+  tick(1);
+  push1(regs.P);
+  tick(1);
+  FLAG_CLEAR(BIT_I);
+
+  PC = get2(0xfffc);
+  tick(2);
+  tick(3);
+
+  return(resGO);
+}
+
+
+/* End of hc08.src/inst.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m68hc08.src/instcl.h sdcc-4.2.0+dfsg/sim/ucsim/m68hc08.src/instcl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/m68hc08.src/instcl.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m68hc08.src/instcl.h	2011-10-01 07:46:51.000000000 +0000
@@ -0,0 +1,62 @@
+/* hc08.src/instcl.h */
+
+  virtual void incx(void);
+  virtual int fetchea(t_mem code, bool prefix);
+  virtual int fetch2(void);
+  virtual int inst_nop(t_mem code, bool prefix);
+  virtual int inst_transfer(t_mem code, bool prefix);
+  virtual int inst_setclearflags(t_mem code, bool prefix);
+  virtual int inst_rsp(t_mem code, bool prefix);
+  virtual int inst_nsa(t_mem code, bool prefix);
+  virtual int inst_lda(t_mem code, bool prefix);
+  virtual int inst_ldx(t_mem code, bool prefix);
+  virtual int inst_sta(t_mem code, bool prefix);
+  virtual int inst_stx(t_mem code, bool prefix);
+  virtual int inst_add(t_mem code, bool prefix);
+  virtual int inst_adc(t_mem code, bool prefix);
+  virtual int inst_sub(t_mem code, bool prefix);
+  virtual int inst_sbc(t_mem code, bool prefix);
+  virtual int inst_cmp(t_mem code, bool prefix);
+  virtual int inst_cpx(t_mem code, bool prefix);
+  virtual int inst_jmp(t_mem code, bool prefix);
+  virtual int inst_jsr(t_mem code, bool prefix);
+  virtual int inst_ais(t_mem code, bool prefix);
+  virtual int inst_aix(t_mem code, bool prefix);
+  virtual int inst_and(t_mem code, bool prefix);
+  virtual int inst_bit(t_mem code, bool prefix);
+  virtual int inst_ora(t_mem code, bool prefix);
+  virtual int inst_eor(t_mem code, bool prefix);
+  virtual int inst_asr(t_mem code, bool prefix);
+  virtual int inst_lsr(t_mem code, bool prefix);
+  virtual int inst_lsl(t_mem code, bool prefix);
+  virtual int inst_rol(t_mem code, bool prefix);
+  virtual int inst_ror(t_mem code, bool prefix);
+  virtual int inst_inc(t_mem code, bool prefix);
+  virtual int inst_dec(t_mem code, bool prefix);
+  virtual int inst_dbnz(t_mem code, bool prefix);
+  virtual int inst_tst(t_mem code, bool prefix);
+  virtual int inst_clr(t_mem code, bool prefix);
+  virtual int inst_clrh(t_mem code, bool prefix);
+  virtual int inst_com(t_mem code, bool prefix);
+  virtual int inst_neg(t_mem code, bool prefix);
+  virtual int inst_pushpull(t_mem code, bool prefix);
+  virtual int inst_stop(t_mem code, bool prefix);
+  virtual int inst_wait(t_mem code, bool prefix);
+  virtual int inst_daa(t_mem code, bool prefix);
+  virtual int inst_mul(t_mem code, bool prefix);
+  virtual int inst_div(t_mem code, bool prefix);
+  virtual int inst_condbranch(t_mem code, bool prefix);
+  virtual int inst_bitsetclear(t_mem code, bool prefix);
+  virtual int inst_bittestsetclear(t_mem code, bool prefix);
+  virtual int inst_cbeq(t_mem code, bool prefix);
+  virtual int inst_rti(t_mem code, bool prefix);
+  virtual int inst_rts(t_mem code, bool prefix);
+  virtual int inst_mov(t_mem code, bool prefix);
+  virtual int inst_sthx(t_mem code, bool prefix);
+  virtual int inst_ldhx(t_mem code, bool prefix);
+  virtual int inst_cphx(t_mem code, bool prefix);
+  virtual int inst_swi(t_mem code, bool prefix);
+  virtual int inst_bsr(t_mem code, bool prefix);
+
+
+/* End of hc08.src/instcl.h */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m68hc08.src/m68hc08.cc sdcc-4.2.0+dfsg/sim/ucsim/m68hc08.src/m68hc08.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/m68hc08.src/m68hc08.cc	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m68hc08.src/m68hc08.cc	2022-01-18 21:40:45.000000000 +0000
@@ -0,0 +1,772 @@
+/*
+ * Simulator of microcontrollers (m68hc08.cc)
+ *
+ * some hc08 code base from Karl Bongers karl@turbobit.com
+ *
+ * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
+ *
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+//#include "ddconfig.h"
+
+//#include  /* for va_list */
+#include 
+#include 
+#include 
+#include 
+//#include "i_string.h"
+
+// prj
+//#include "pobjcl.h"
+
+// sim
+#include "simcl.h"
+#include "dregcl.h"
+
+// local
+#include "m68hc08cl.h"
+#include "glob.h"
+//#include "regshc08.h"
+#include "hc08mac.h"
+
+#define uint32 t_addr
+#define uint8 unsigned char
+#define int8 char
+
+//const bool TRUE = 1;
+//const bool FALSE = 0;
+
+/*******************************************************************/
+
+
+/*
+ * Base type of HC08 controllers
+ */
+
+cl_hc08::cl_hc08(struct cpu_entry *Itype, class cl_sim *asim):
+  cl_uc(asim)
+{
+  type= Itype;
+}
+
+int
+cl_hc08::init(void)
+{
+  cl_uc::init(); /* Memories now exist */
+
+  set_xtal(8000000);
+
+  //rom= address_space(MEM_ROM_ID);
+//  ram= mem(MEM_XRAM);
+  //ram= rom;
+
+  // zero out ram(this is assumed in regression tests)
+  for (int i=0x80; i<0x8000; i++) {
+    ram->set((t_addr) i, 0);
+  }
+
+  sp_limit= 0x7000;
+  return(0);
+}
+
+
+void
+cl_hc08::reset(void)
+{
+  cl_uc::reset();
+
+  regs.SP = 0xff;
+  regs.A = 0;
+  regs.X = 0;
+  regs.H = 0;
+  regs.P = 0x60;
+  regs.VECTOR = 1;
+
+  PC= rom->get(0xfffe)*256 + rom->get(0xffff);
+}
+
+
+const char *
+cl_hc08::id_string(void)
+{
+  return("unspecified HC08");
+}
+
+
+/*
+ * Making elements of the controller
+ */
+/*
+t_addr
+cl_hc08::get_mem_size(enum mem_class type)
+{
+  switch(type)
+    {
+    case MEM_ROM: return(0x10000);
+    case MEM_XRAM: return(0x10000);
+    default: return(0);
+    }
+ return(cl_uc::get_mem_size(type));
+}
+*/
+void
+cl_hc08::mk_hw_elements(void)
+{
+  //class cl_base *o;
+  class cl_hw *h;
+  cl_uc::mk_hw_elements();
+
+  add_hw(h= new cl_dreg(this, 0, "dreg"));
+  h->init();
+  
+  add_hw(h= new cl_hc08_cpu(this));
+  h->init();
+}
+
+void
+cl_hc08::make_memories(void)
+{
+  class cl_address_space *as;
+
+  rom= ram= as= new cl_address_space("rom", 0, 0x10000, 8);
+  as->init();
+  address_spaces->add(as);
+
+  class cl_address_decoder *ad;
+  class cl_memory_chip *chip;
+
+  chip= new cl_chip8("rom_chip", 0x10000, 8);
+  chip->init();
+  memchips->add(chip);
+  ad= new cl_address_decoder(as= address_space("rom"), chip, 0, 0xffff, 0);
+  ad->init();
+  as->decoders->add(ad);
+  ad->activate(0);
+
+
+  regs8= new cl_address_space("regs8", 0, 4, 8);
+  regs8->init();
+  regs8->get_cell(0)->decode((t_mem*)®s.A);
+  regs8->get_cell(1)->decode((t_mem*)®s.P);
+  regs8->get_cell(2)->decode((t_mem*)®s.H);
+  regs8->get_cell(3)->decode((t_mem*)®s.X);
+
+  regs16= new cl_address_space("regs16", 0, 1, 16);
+  regs16->init();
+
+  regs16->get_cell(0)->decode((t_mem*)®s.SP);
+
+  address_spaces->add(regs8);
+  address_spaces->add(regs16);
+
+  vars->add("A", regs8, 0, 7, 0, "Accumulator");
+  vars->add("P", regs8, 1, -1, -1, "Condition Code Register");
+  vars->add("CC", regs8, 1, -1, -1, "Condition Code Register");
+  vars->add("CC_C", regs8, 1, BITPOS_C, BITPOS_C, "Carry");
+  vars->add("CC_Z", regs8, 1, BITPOS_Z, BITPOS_Z, "Zero");
+  vars->add("CC_N", regs8, 1, BITPOS_N, BITPOS_N, "Negative");
+  vars->add("CC_I", regs8, 1, BITPOS_I, BITPOS_I, "Interrupt Mask");
+  vars->add("CC_H", regs8, 1, BITPOS_H, BITPOS_H, "Half Carry");
+  vars->add("CC_V", regs8, 1, BITPOS_V, BITPOS_V, "Two's Complement Overflow");
+  vars->add("H", regs8, 2, 7, 0, "H Index Register");
+  vars->add("X", regs8, 3, 7, 0, "X Index Register");
+
+  vars->add("SP", regs16, 0, 15, 0, "Stack Pointer");
+}
+
+
+/*
+ * Help command interpreter
+ */
+
+struct dis_entry *
+cl_hc08::dis_tbl(void)
+{
+  return(disass_hc08);
+}
+
+/*struct name_entry *
+cl_hc08::sfr_tbl(void)
+{
+  return(0);
+}*/
+
+/*struct name_entry *
+cl_hc08::bit_tbl(void)
+{
+  //FIXME
+  return(0);
+}*/
+
+int
+cl_hc08::inst_length(t_addr addr)
+{
+  int len = 0;
+  /*char *s;
+
+    s =*/ get_disasm_info(addr, &len, NULL, NULL, NULL);
+
+  return len;
+}
+
+int
+cl_hc08::inst_branch(t_addr addr)
+{
+  int b;
+  /*char *s;
+
+    s =*/ get_disasm_info(addr, NULL, &b, NULL, NULL);
+
+  return b;
+}
+
+
+bool
+cl_hc08::is_call(t_addr addr)
+{
+  struct dis_entry *e;
+
+  get_disasm_info(addr, NULL, NULL, NULL, &e);
+  
+  return e?(e->is_call):false;
+}
+
+int
+cl_hc08::longest_inst(void)
+{
+  return 4;
+}
+
+
+const char *
+cl_hc08::get_disasm_info(t_addr addr,
+			 int *ret_len,
+			 int *ret_branch,
+			 int *immed_offset,
+			 struct dis_entry **dentry)
+{
+  const char *b = NULL;
+  uint code;
+  int len = 0;
+  int immed_n = 0;
+  int i;
+  int start_addr = addr;
+  struct dis_entry *dis_e;
+
+  code= rom->get(addr++);
+  dis_e = NULL;
+
+  switch(code) {
+    case 0x9e:  /* ESC code to sp relative op-codes */
+      code= rom->get(addr++);
+      i= 0;
+      while ((code & disass_hc08_9e[i].mask) != disass_hc08_9e[i].code &&
+        disass_hc08_9e[i].mnemonic)
+        i++;
+      dis_e = &disass_hc08_9e[i];
+      b= disass_hc08_9e[i].mnemonic;
+      if (b != NULL)
+        len += (disass_hc08_9e[i].length + 1);
+    break;
+
+    default:
+      i= 0;
+      while ((code & disass_hc08[i].mask) != disass_hc08[i].code &&
+             disass_hc08[i].mnemonic)
+        i++;
+      dis_e = &disass_hc08[i];
+      b= disass_hc08[i].mnemonic;
+      if (b != NULL)
+        len += (disass_hc08[i].length);
+    break;
+  }
+
+  if (ret_branch) {
+    *ret_branch = dis_e->branch;
+  }
+
+  if (immed_offset) {
+    if (immed_n > 0)
+         *immed_offset = immed_n;
+    else *immed_offset = (addr - start_addr);
+  }
+
+  if (len == 0)
+    len = 1;
+
+  if (ret_len)
+    *ret_len = len;
+
+  if (dentry)
+    *dentry= dis_e;
+  
+  return b;
+}
+
+char *
+cl_hc08::disass(t_addr addr)
+{
+  chars work, temp;
+  t_addr operand;
+  const char *b;
+  int len = 0;
+  int immed_offset = 0;
+  bool first= true;
+  
+  work= "";
+
+  b = get_disasm_info(addr, &len, NULL, &immed_offset, NULL);
+
+  if (b == NULL) {
+    return(strdup("UNKNOWN/INVALID"));
+  }
+
+  while (*b)
+    {
+      if ((*b == ' ') && first)
+	{
+	  first= false;
+	  while (work.len() < 6) work.append(' ');
+	}
+      if (*b == '%')
+	{
+	  b++;
+	  temp= "";
+	  switch (*(b++))
+	    {
+	    case 's': // s    signed byte immediate
+	      temp.format("#%d", (char)rom->get(addr+immed_offset));
+	      ++immed_offset;
+	      break;
+	    case 'w': // w    word immediate operand
+	      operand= ((rom->get(addr+immed_offset)<<8) |
+		       (rom->get(addr+immed_offset+1)));
+	      temp.format("#$%04x", operand);
+	      addr_name(operand, rom, &temp);
+	      ++immed_offset;
+	      ++immed_offset;
+	      break;
+	    case 'b': // b    byte immediate operand
+	      temp.format("#$%02x", (uint)rom->get(addr+immed_offset));
+	      ++immed_offset;
+	      break;
+	    case 'x': // x    extended addressing
+	      operand= ((rom->get(addr+immed_offset)<<8) |
+		       (rom->get(addr+immed_offset+1)));
+	      temp.format("$%04x", operand);
+	      addr_name(operand, rom, &temp);
+	      ++immed_offset;
+	      ++immed_offset;
+	      break;
+	    case 'd': // d    direct addressing
+	      operand= rom->get(addr+immed_offset);
+	      temp.format("*$%02x", operand);
+	      addr_name(operand, rom, &temp);
+	      ++immed_offset;
+	      break;
+	    case '2': // 2    word index offset
+	      {
+		operand= ((rom->get(addr+immed_offset)<<8) |
+			      (rom->get(addr+immed_offset+1)));
+		// Assumption: the word offset address is the address of a
+		// fixed table and index register selects an entry.
+		temp.format("$%04x", operand);
+		addr_name(operand, rom, &temp);
+		++immed_offset;
+		++immed_offset;
+		break;
+	      }		
+	    case '1': // b    byte index offset
+	      // Assumption: the index register points to a struct/record
+	      // and the byte offset selects an entry.
+              temp.format("$%02x", (uint)rom->get(addr+immed_offset));
+	      ++immed_offset;
+	      break;
+	    case 'p': // p    pc relative
+	      {
+		operand= (addr+immed_offset+1 + (i8_t)rom->get(addr+immed_offset)) & 0xffff;
+		temp.format("$%04x", operand);
+		addr_name(operand, rom, &temp);
+		++immed_offset;
+		break;
+	      }
+	    default:
+	      temp= "?";
+	      break;
+	    }
+	  work+= temp;
+	}
+      else
+	work+= *(b++);
+    }
+
+  return strdup(work.c_str());
+}
+
+
+void
+cl_hc08::print_regs(class cl_console_base *con)
+{
+  con->dd_color("answer");
+  con->dd_printf("V--HINZC  Flags= $%02x %3d %c  ",
+		 regs.P, regs.P, isprint(regs.P)?regs.P:'.');
+  con->dd_printf("A= $%02x %3d %c\n",
+		 regs.A, regs.A, isprint(regs.A)?regs.A:'.');
+  con->dd_printf("%c--%c%c%c%c%c  ",
+		 (regs.P&BIT_V)?'1':'0',
+		 (regs.P&BIT_H)?'1':'0',
+		 (regs.P&BIT_I)?'1':'0',
+		 (regs.P&BIT_N)?'1':'0',
+		 (regs.P&BIT_Z)?'1':'0',
+		 (regs.P&BIT_C)?'1':'0');
+  con->dd_printf("    H= $%02x %3d %c  ",
+		 regs.H, regs.H, isprint(regs.H)?regs.H:'.');
+  con->dd_printf("X= $%02x %3d %c\n",
+		 regs.X, regs.X, isprint(regs.X)?regs.X:'.');
+  con->dd_printf("SP= $%04x [SP+1]= %02x %3d %c",
+                 regs.SP, ram->get(regs.SP+1), ram->get(regs.SP+1),
+                 isprint(ram->get(regs.SP+1))?ram->get(regs.SP+1):'.');
+  con->dd_printf("  Limit= $%04x\n", AU(sp_limit));
+  
+  print_disass(PC, con);
+}
+
+/*
+ * Execution
+ */
+
+int
+cl_hc08::exec_inst(void)
+{
+  t_mem code;
+
+  if (regs.VECTOR) {
+    PC = get2(0xfffe);
+    regs.VECTOR = 0;
+    return(resGO);
+  }
+
+  instPC= PC;
+
+  if (fetch(&code))
+    return(resBREAKPOINT);
+  tick(1);
+  switch ((code >> 4) & 0xf) {
+  case 0x0: return(inst_bittestsetclear(code, /*FALSE*/0));
+  case 0x1: return(inst_bitsetclear(code, /*FALSE*/0));
+    case 0x2: return(inst_condbranch(code, /*FALSE*/0));
+    case 0x3:
+    case 0x4:
+    case 0x5:
+    case 0x6:
+    case 0x7:
+      switch (code & 0xf) {
+        case 0x0: return(inst_neg(code, /*FALSE*/0));
+        case 0x1: return(inst_cbeq(code, false));
+        case 0x2:
+          switch (code) {
+            case 0x32: return(inst_ldhx(code, false));
+            case 0x42: return(inst_mul(code, false));
+            case 0x52: return(inst_div(code, false));
+            case 0x62: return(inst_nsa(code, false));
+            case 0x72: return(inst_daa(code, /*FALSE*/0));
+            default: return(resHALT);
+          }
+        case 0x3: return(inst_com(code, /*FALSE*/0));
+        case 0x4: return(inst_lsr(code, /*FALSE*/0));
+        case 0x5:
+          switch (code) {
+            case 0x35: return(inst_sthx(code, /*FALSE*/0));
+            case 0x45:
+            case 0x55: return(inst_ldhx(code, /*FALSE*/0));
+            case 0x65:
+            case 0x75: return(inst_cphx(code, /*FALSE*/0));
+            default: return(resHALT);
+          }
+        case 0x6: return(inst_ror(code, /*FALSE*/0));
+        case 0x7: return(inst_asr(code, /*FALSE*/0));
+        case 0x8: return(inst_lsl(code, /*FALSE*/0));
+        case 0x9: return(inst_rol(code, /*FALSE*/0));
+        case 0xa: return(inst_dec(code, /*FALSE*/0));
+        case 0xb: return(inst_dbnz(code, /*FALSE*/0));
+        case 0xc: return(inst_inc(code, /*FALSE*/0));
+        case 0xd: return(inst_tst(code, false));
+        case 0xe:
+          switch (code) {
+            case 0x3e: return(inst_cphx(code, false));
+            case 0x4e:
+            case 0x5e:
+            case 0x6e:
+            case 0x7e: return(inst_mov(code, /*FALSE*/0));
+            default: return(resHALT);
+          }
+        case 0xf: return(inst_clr(code, /*FALSE*/0));
+        default: return(resHALT);
+      }
+    case 0x8:
+      switch (code & 0xf) {
+        case 0x0: return(inst_rti(code, /*FALSE*/0));
+        case 0x1: return(inst_rts(code, /*FALSE*/0));
+        case 0x3: return(inst_swi(code, /*FALSE*/0));
+        case 0x4:
+        case 0x5: return(inst_transfer(code, /*FALSE*/0));
+        case 0x6:
+        case 0x7:
+        case 0x8:
+        case 0x9:
+        case 0xa:
+        case 0xb: return(inst_pushpull(code, /*FALSE*/0));
+        case 0xc: return(inst_clrh(code, false));
+        case 0xe: return(inst_stop(code, false));
+        case 0xf: return(inst_wait(code, false));
+        default: return(resINV_INST); // 0x82 and 0x8d not valid
+      }
+    case 0x9:
+      switch (code & 0xf) {
+        case 0x0:
+        case 0x1:
+        case 0x2:
+        case 0x3: return(inst_condbranch(code, false));
+        case 0x4:
+        case 0x5: return(inst_transfer(code, false));
+        case 0x6: return(inst_sthx(code, false));
+        case 0x7:
+        case 0xf: return(inst_transfer(code, false));
+        case 0x8:
+        case 0x9:
+        case 0xa:
+        case 0xb: return(inst_setclearflags(code, false));
+        case 0xc: return(inst_rsp(code, false));
+        case 0xd: return(inst_nop(code, false));
+        case 0xe: // start 0x9e prefix handling
+          code = fetch();
+          tick(1);
+          switch ((code >> 4) & 0xf) {
+            case 0x6:
+              switch (code & 0xf) {
+                case 0x0: return(inst_neg(code, /*TRUE*/1));
+                case 0x1: return(inst_cbeq(code, /*TRUE*/1));
+                case 0x3: return(inst_com(code, /*TRUE*/1));
+                case 0x4: return(inst_lsr(code, /*TRUE*/1));
+                case 0x6: return(inst_ror(code, /*TRUE*/1));
+                case 0x7: return(inst_asr(code, /*TRUE*/1));
+                case 0x8: return(inst_lsl(code, /*TRUE*/1));
+                case 0x9: return(inst_rol(code, /*TRUE*/1));
+                case 0xa: return(inst_dec(code, /*TRUE*/1));
+                case 0xb: return(inst_dbnz(code, /*TRUE*/1));
+                case 0xc: return(inst_inc(code, true));
+                case 0xd: return(inst_tst(code, true));
+                case 0xf: return(inst_clr(code, true));
+                default: return(resINV_INST); // 0x9e62, 0x9e65, 0x9e6e not valid
+              }
+            case 0xa:
+              switch (code) {
+                case 0xae: return(inst_ldhx(code,true));
+                default: return(resINV_INST);
+              }
+            case 0xb:
+              switch (code) {
+                case 0xbe: return(inst_ldhx(code,true));
+                default: return(resINV_INST);
+              }
+            case 0xc:
+              switch (code) {
+                case 0xce: return(inst_ldhx(code,true));
+                default: return(resINV_INST);
+              }
+            case 0xd:
+            case 0xe:
+              switch (code & 0xf) {
+                case 0x0: return(inst_sub(code, /*TRUE*/1));
+                case 0x1: return(inst_cmp(code, /*TRUE*/1));
+                case 0x2: return(inst_sbc(code, /*TRUE*/1));
+                case 0x3: return(inst_cpx(code, /*TRUE*/1));
+                case 0x4: return(inst_and(code, /*TRUE*/1));
+                case 0x5: return(inst_bit(code, /*TRUE*/1));
+                case 0x6: return(inst_lda(code, /*TRUE*/1));
+                case 0x7: return(inst_sta(code, /*TRUE*/1));
+                case 0x8: return(inst_eor(code, /*TRUE*/1));
+                case 0x9: return(inst_adc(code, true));
+                case 0xa: return(inst_ora(code, true));
+                case 0xb: return(inst_add(code, true));
+	      case 0xc: return(resINV_INST);
+		return(resHALT); // not real instruction: regression test hack to exit simulation
+	      case 0xd:
+		return(resINV_INST);
+		putchar(regs.A);
+		fflush(stdout);
+		return(resGO); // not real instruction: regression test hack to output results
+                case 0xe: return(inst_ldx(code, true));
+                case 0xf: return(inst_stx(code, true));
+                default: return(resHALT);
+              }
+            case 0xf:
+              switch (code & 0xf) {
+                case 0x3: return(inst_cphx(code, true));
+                case 0xe: return(inst_ldhx(code, true));
+                case 0xf: return(inst_sthx(code, true));
+              }
+            default: return(resINV_INST);
+	    // end 0x9e prefix handling
+          }
+
+      }
+    case 0xa:
+    case 0xb:
+    case 0xc:
+    case 0xd:
+    case 0xe:
+    case 0xf:
+      switch (code & 0xf) {
+        case 0x0: return(inst_sub(code, /*FALSE*/0));
+        case 0x1: return(inst_cmp(code, /*FALSE*/0));
+        case 0x2: return(inst_sbc(code, /*FALSE*/0));
+        case 0x3: return(inst_cpx(code, /*FALSE*/0));
+        case 0x4: return(inst_and(code, /*FALSE*/0));
+        case 0x5: return(inst_bit(code, /*FALSE*/0));
+        case 0x6: return(inst_lda(code, /*FALSE*/0));
+        case 0x7:
+          if (code==0xa7)
+            return(inst_ais(code, /*FALSE*/0));
+          else
+            return(inst_sta(code, /*FALSE*/0));
+        case 0x8: return(inst_eor(code, /*FALSE*/0));
+        case 0x9: return(inst_adc(code, /*FALSE*/0));
+        case 0xa: return(inst_ora(code, /*FALSE*/0));
+        case 0xb: return(inst_add(code, false));
+        case 0xc:
+          if (code==0xac)
+            return(resINV_INST);
+          else
+            return(inst_jmp(code, false));
+        case 0xd:
+          if (code==0xad)
+            return(inst_bsr(code, /*FALSE*/0));
+          else
+            return(inst_jsr(code, /*FALSE*/0));
+        case 0xe: return(inst_ldx(code, /*FALSE*/0));
+        case 0xf:
+          if (code==0xaf)
+            return(inst_aix(code, /*FALSE*/0));
+          else
+            return(inst_stx(code, /*FALSE*/0));
+        default: return(resHALT);
+      }
+    default: return(resHALT);
+  }
+
+  /*if (PC)
+    PC--;
+  else
+  PC= get_mem_size(MEM_ROM_ID)-1;*/
+  PC= rom->inc_address(PC, -1);
+
+  sim->stop(resINV_INST);
+  return(resINV_INST);
+}
+
+
+void
+cl_hc08::stack_check_overflow(class cl_stack_op *op)
+{
+  if (op)
+    {
+      if (op->get_op() & stack_write_operation)
+	{
+	  t_addr a= op->get_after();
+	  if (a < sp_limit)
+	    {
+	      class cl_error_stack_overflow *e=
+		new cl_error_stack_overflow(op);
+	      e->init();
+	      error(e);
+	    }
+	}
+    }
+}
+
+t_mem
+cl_hc08::get_1(t_addr addr)
+{
+  vc.rd++;
+  return ram->read(addr & 0xffff);
+}
+
+t_mem
+cl_hc08::get_2(t_addr addr)
+{
+  vc.rd+= 2;
+  return (ram->read(addr & 0xffff) << 8) | ram->read((addr+1) & 0xffff);
+}
+
+
+cl_hc08_cpu::cl_hc08_cpu(class cl_uc *auc):
+  cl_hw(auc, HW_CPU, 0, "cpu")
+{
+}
+
+int
+cl_hc08_cpu::init(void)
+{
+  cl_hw::init();
+
+  cl_var *v;
+  uc->vars->add(v= new cl_var("sp_limit", cfg, hc08cpu_sp_limit,
+			      cfg_help(hc08cpu_sp_limit)));
+  v->init();
+
+  return 0;
+}
+
+const char *
+cl_hc08_cpu::cfg_help(t_addr addr)
+{
+  switch (addr)
+    {
+    case hc08cpu_sp_limit:
+      return "Stack overflows when SP is below this limit";
+    }
+  return "Not used";
+}
+
+t_mem
+cl_hc08_cpu::conf_op(cl_memory_cell *cell, t_addr addr, t_mem *val)
+{
+  class cl_hc08 *u= (class cl_hc08 *)uc;
+  if (val)
+    cell->set(*val);
+  switch ((enum hc08cpu_confs)addr)
+    {
+    case hc08cpu_sp_limit:
+      if (val)
+	u->sp_limit= *val & 0xffff;
+      else
+	cell->set(u->sp_limit);
+      break;
+    case hc08cpu_nuof: break;
+    }
+  return cell->get();
+}
+
+
+/* End of hc08.src/m68hc08.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m68hc08.src/m68hc08cl.h sdcc-4.2.0+dfsg/sim/ucsim/m68hc08.src/m68hc08cl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/m68hc08.src/m68hc08cl.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m68hc08.src/m68hc08cl.h	2021-10-29 17:39:15.000000000 +0000
@@ -0,0 +1,99 @@
+/*
+ * Simulator of microcontrollers (m68hc08cl.h)
+ *
+ * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
+ *
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef HC08CL_HEADER
+#define HC08CL_HEADER
+
+#include "uccl.h"
+
+#include "regshc08.h"
+
+
+/*
+ * Base type of Z80 microcontrollers
+ */
+
+class cl_hc08: public cl_uc
+{
+public:
+  class cl_address_space *ram, *regs8, *regs16;
+  struct t_regs regs;
+  t_addr sp_limit;
+public:
+  cl_hc08(struct cpu_entry *Itype, class cl_sim *asim);
+  virtual int init(void);
+  virtual const char *id_string(void);
+
+  //virtual t_addr get_mem_size(enum mem_class type);
+  virtual void mk_hw_elements(void);
+  virtual void make_memories(void);
+
+  virtual struct dis_entry *dis_tbl(void);
+  virtual int inst_length(t_addr addr);
+  virtual int inst_branch(t_addr addr);
+  virtual int longest_inst(void);
+  virtual char *disass(t_addr addr);
+  virtual void print_regs(class cl_console_base *con);
+
+  virtual int exec_inst(void);
+
+  virtual void stack_check_overflow(class cl_stack_op *op);
+
+  virtual const char * get_disasm_info(t_addr addr,
+				       int *ret_len,
+				       int *ret_branch,
+				       int *immed_offset,
+				       struct dis_entry **dentry);
+  virtual bool is_call(t_addr addr);
+  virtual t_mem get_1(t_addr addr);
+  virtual t_mem get_2(t_addr addr);
+  
+  virtual void reset(void);
+#include "instcl.h"
+};
+
+
+enum hc08cpu_confs
+  {
+   hc08cpu_sp_limit	= 0,
+   hc08cpu_nuof		= 1
+  };
+
+class cl_hc08_cpu: public cl_hw
+{
+public:
+  cl_hc08_cpu(class cl_uc *auc);
+  virtual int init(void);
+  virtual unsigned int cfg_size(void) { return hc08cpu_nuof; }
+  virtual const char *cfg_help(t_addr addr);
+
+  virtual t_mem conf_op(cl_memory_cell *cell, t_addr addr, t_mem *val);
+};
+
+#endif
+
+/* End of hc08.src/m68hc08cl.h */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m68hc08.src/Makefile.in sdcc-4.2.0+dfsg/sim/ucsim/m68hc08.src/Makefile.in
--- sdcc-4.0.0+dfsg/sim/ucsim/m68hc08.src/Makefile.in	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m68hc08.src/Makefile.in	2022-01-09 14:02:03.000000000 +0000
@@ -0,0 +1,200 @@
+#
+# uCsim hc08.src/Makefile
+#
+# (c) Drotos Daniel, Talker Bt. 1997
+#
+
+# tool name
+TN		= m68hc08
+OLD		= hc08
+
+STARTYEAR	= 1997
+
+SHELL		= /bin/sh
+CXX		= @CXX@
+CPP		= @CPP@
+CXXCPP		= @CXXCPP@
+RANLIB		= @RANLIB@
+INSTALL		= @INSTALL@
+STRIP		= @STRIP@
+MAKEDEP         = @MAKEDEP@
+
+top_builddir	= @top_builddir@
+top_srcdir	= @top_srcdir@
+
+transform	= @program_transform_name@
+
+DEFS            = $(subs -DHAVE_CONFIG_H,,@DEFS@)
+CPPFLAGS        = @CPPFLAGS@ -I$(srcdir) -I$(top_srcdir) -I$(top_builddir) \
+		  -I$(top_srcdir)/cmd.src -I$(top_srcdir)/sim.src \
+		  -I$(top_srcdir)/gui.src
+CFLAGS          = @WALL_FLAG@ @CFLAGS@
+CXXFLAGS        = @WALL_FLAG@ @CXXFLAGS@
+LDFLAGS         = @LDFLAGS@
+PICOPT		= @PICOPT@
+SHAREDLIB	= @SHAREDLIB@
+
+EXEEXT          = @EXEEXT@
+
+LIBS		= -L$(top_builddir) -lsim -lucsimutil -lguiucsim -lcmd -lsim @LIBS@
+DL		= @DL@
+dl_ok		= @dl_ok@
+
+prefix          = @prefix@
+exec_prefix     = @exec_prefix@
+bindir          = @bindir@
+libdir          = @libdir@
+datadir         = @datadir@
+datarootdir     = @datarootdir@
+includedir      = @includedir@
+mandir          = @mandir@
+man1dir         = $(mandir)/man1
+man2dir         = $(mandir)/man2
+infodir         = @infodir@
+srcdir          = @srcdir@
+VPATH           = @srcdir@
+
+OBJECTS_SHARED	= glob.o inst.o sim$(TN).o $(TN).o
+OBJECTS_EXE	= s$(TN).o
+OBJECTS		= $(OBJECTS_SHARED) $(OBJECTS_EXE)
+
+# short/long exe and lib name
+SEN		= s$(TN)$(EXEEXT)
+LEN		= ucsim_$(TN)$(EXEEXT)
+SONAME		= libucsim_$(TN).so
+SOLD		= s$(OLD)$(EXEEXT)
+LOLD		= ucsim_$(OLD)$(EXEEXT)
+
+HC08ASM		= 
+
+enable_dlso	= @enable_dlso@
+dlso_ok		= @dlso_ok@
+
+#TEST_OBJ	= test_bit.hex test_dis.hex test_mov.hex test_jmp.hex \
+#		  test_arith.hex
+
+# Compiling entire program or any subproject
+# ------------------------------------------
+all: checkconf otherlibs $(TN).src tests
+
+tests: $(TEST_OBJ)
+
+
+# Compiling and installing everything and runing test
+# ---------------------------------------------------
+install: all installdirs install_shared_lib
+	$(INSTALL) $(SEN) $(DESTDIR)$(bindir)/$(SEN)
+	$(STRIP) $(DESTDIR)$(bindir)/$(SEN)
+	$(INSTALL) $(LEN) $(DESTDIR)$(bindir)/$(LEN)
+	$(STRIP) $(DESTDIR)$(bindir)/$(LEN)
+	$(INSTALL) $(SOLD) $(DESTDIR)$(bindir)/$(SOLD)
+	$(STRIP) $(DESTDIR)$(bindir)/$(SOLD)
+	$(INSTALL) $(LOLD) $(DESTDIR)$(bindir)/$(LOLD)
+	$(STRIP) $(DESTDIR)$(bindir)/$(LOLD)
+
+
+# Deleting all the installed files
+# --------------------------------
+uninstall:
+	rm -f $(DESTDIR)$(bindir)/$(SEN)
+	rm -f $(DESTDIR)$(bindir)/$(LEN)
+	rm -f $(DESTDIR)$(libdir)/$(SONAME)
+
+
+# Performing self-test
+# --------------------
+check: test
+
+.PHONY:	test baseline
+test:
+	@$(MAKE) --no-print-directory -C test
+
+baseline:
+	@$(MAKE) --no-print-directory -C test baseline
+
+
+# Performing installation test
+# ----------------------------
+installcheck:
+
+
+# Creating installation directories
+# ---------------------------------
+installdirs:
+	test -d $(DESTDIR)$(bindir) || $(INSTALL) -d $(DESTDIR)$(bindir)
+
+
+# Creating dependencies
+# ---------------------
+dep: Makefile.dep
+
+Makefile.dep: $(srcdir)/*.cc $(srcdir)/*.h
+	$(MAKEDEP) $(CPPFLAGS) $(filter %.cc,$^) >Makefile.dep
+
+-include Makefile.dep
+include $(srcdir)/clean.mk
+
+# My rules
+# --------
+.SUFFIXES: .asm .hex
+
+$(TN).src: $(SEN) $(LEN) shared_lib olds
+
+$(SEN): $(OBJECTS) $(top_builddir)/libcmd.a $(top_builddir)/libguiucsim.a $(top_builddir)/libsim.a $(top_builddir)/libucsimutil.a
+	$(CXX) $(CXXFLAGS) $(LDFLAGS) $(OBJECTS) $(LIBS) -o $@
+
+$(LEN): $(SEN)
+	cp $< $@
+
+olds: $(SOLD) $(LOLD)
+
+$(SOLD): $(SEN)
+	cp $< $@
+
+$(LOLD): $(LEN)
+	cp $< $@
+
+ifeq ($(dlso_ok),yes)
+shared_lib: $(top_builddir)/$(SONAME)
+install_shared_lib: shared_lib
+	test -d $(DESTDIR)$(libdir) || $(INSTALL) -d $(DESTDIR)$(libdir)
+	$(INSTALL) $(top_builddir)/$(SONAME) $(DESTDIR)$(libdir)/$(SONAME)
+else
+shared_lib:
+	@$(top_srcdir)/mkecho $(top_builddir) "No $(TN) shared lib made."
+	@$(top_srcdir)/mkecho $(top_builddir) "(SHAREDLIB="$(SHAREDLIB)",dl_ok="$(dl_ok)",enable_dlso="$(enable_dlso)")"
+install_shared_lib:
+endif
+
+$(top_builddir)/$(SONAME): $(OBJECTS_SHARED)
+	$(CXX) -shared $(LDFLAGS) $(OBJECTS_SHARED) -o $@
+
+otherlibs: $(top_builddir)/libcmd.a $(top_builddir)/libguiucsim.a $(top_builddir)/libsim.a $(top_builddir)/libucsimutil.a
+
+$(top_builddir)/libcmd.a:
+	$(MAKE) -C $(top_builddir)/cmd.src all
+
+$(top_builddir)/libguiucsim.a:
+	$(MAKE) -C $(top_builddir)/gui.src checkconf ucsim_lib
+
+$(top_builddir)/libsim.a:
+	$(MAKE) -C $(top_builddir)/sim.src all
+
+$(top_builddir)/libucsimutil.a:
+	$(MAKE) -C $(top_builddir) -f main.mk
+
+.cc.o:
+	$(CXX) $(CXXFLAGS) $(PICOPT) $(CPPFLAGS) $(TARGET_ARCH) -c $< -o $@
+
+.asm.hex:
+	$(HC08ASM) -l $< -o $@ -e $<.lst
+
+
+# Remaking configuration
+# ----------------------
+checkconf:
+	@if [ -f $(top_builddir)/devel ]; then\
+	  $(MAKE) -f conf.mk srcdir="$(srcdir)" top_builddir="$(top_builddir)" freshconf;\
+	fi
+
+# End of hc08.src/Makefile.in
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m68hc08.src/regshc08.h sdcc-4.2.0+dfsg/sim/ucsim/m68hc08.src/regshc08.h
--- sdcc-4.0.0+dfsg/sim/ucsim/m68hc08.src/regshc08.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m68hc08.src/regshc08.h	2016-11-13 16:22:34.000000000 +0000
@@ -0,0 +1,63 @@
+/*
+ * Simulator of microcontrollers (regsz80.h)
+ *
+ * some z80 code base from Karl Bongers karl@turbobit.com
+ *
+ * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef REGHC08_HEADER
+#define REGHC08_HEADER
+
+#include "ddconfig.h"
+
+
+struct t_regs
+{
+  u8_t A;
+  u8_t P;
+  u8_t H;
+  u8_t X;
+  u16_t SP;
+  u8_t VECTOR;
+};
+
+#define BIT_C	0x01  // carry status(out of bit 7)
+#define BIT_Z	0x02  // zero status, 1=zero, 0=nonzero
+#define BIT_N	0x04  // sign, 1=negative, 0=positive (or zero)
+#define BIT_I	0x08  // interrupt mask, 1=disabled, 0=enabled
+#define BIT_H	0x10  // half carry status(out of bit 3)
+#define BIT_V	0x80  // signed overflow, 1=overflow
+#define BIT_ALL	(BIT_C |BIT_Z |BIT_N |BIT_I |BIT_H |BIT_V)  // all bits
+
+#define BITPOS_C 0    // 1
+#define BITPOS_Z 1    // 2H
+#define BITPOS_N 2    // 4H
+#define BITPOS_I 3    // 8H
+#define BITPOS_H 4    // 10H
+#define BITPOS_V 7    // 80H
+
+#endif
+
+/* End of hc08.src/regshc08.h */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m68hc08.src/simm68hc08.cc sdcc-4.2.0+dfsg/sim/ucsim/m68hc08.src/simm68hc08.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/m68hc08.src/simm68hc08.cc	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m68hc08.src/simm68hc08.cc	2021-10-04 11:31:43.000000000 +0000
@@ -0,0 +1,78 @@
+/*
+ * Simulator of microcontrollers (simm68hc08.cc)
+ *
+ * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#include 
+#include 
+
+#include "globals.h"
+
+// local
+#include "simm68hc08cl.h"
+#include "m68hc08cl.h"
+
+
+cl_simm68hc08::cl_simm68hc08(class cl_app *the_app):
+  cl_sim(the_app)
+{}
+
+class cl_uc *
+cl_simm68hc08::mk_controller(void)
+{
+  int i;
+  const char *typ= 0;
+  class cl_optref type_option(this);
+
+  type_option.init();
+  type_option.use("cpu_type");
+  i= 0;
+  if ((typ= type_option.get_value(typ)) == 0)
+    typ= "HC08";
+
+  while ((cpus_hc08[i].type_str != NULL) &&
+	 (strcmp(typ, cpus_hc08[i].type_str) != 0))
+    i++;
+  if (cpus_hc08[i].type_str == NULL)
+    {
+      fprintf(stderr, "Unknown processor type. "
+	      "Use -H option to see known types.\n");
+      return(NULL);
+    }
+
+  switch (cpus_hc08[i].type)
+    {
+    case CPU_HC08:
+    case CPU_HCS08:
+      return(new cl_hc08(&cpus_hc08[i], this));
+    default:
+      return NULL;
+    }
+
+  return(NULL);
+}
+
+
+/* End of hc08.src/simm68hc08.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m68hc08.src/simm68hc08cl.h sdcc-4.2.0+dfsg/sim/ucsim/m68hc08.src/simm68hc08cl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/m68hc08.src/simm68hc08cl.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m68hc08.src/simm68hc08cl.h	2021-10-04 11:31:43.000000000 +0000
@@ -0,0 +1,45 @@
+/*
+ * Simulator of microcontrollers (simm68hc08cl.h)
+ *
+ * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef SIMM68HC08CL_HEADER
+#define SIMM68HC08CL_HEADER
+
+#include "simcl.h"
+
+
+class cl_simm68hc08: public cl_sim
+{
+public:
+  cl_simm68hc08(class cl_app *the_app);
+
+  virtual class cl_uc *mk_controller(void);
+};
+
+
+#endif
+
+/* End of hc08.src/simm68hc08cl.h */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m68hc08.src/sm68hc08.cc sdcc-4.2.0+dfsg/sim/ucsim/m68hc08.src/sm68hc08.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/m68hc08.src/sm68hc08.cc	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m68hc08.src/sm68hc08.cc	2021-10-04 11:31:43.000000000 +0000
@@ -0,0 +1,58 @@
+/*
+ * Simulator of microcontrollers (sm68hc08.cc)
+ *
+ * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+// prj
+#include "globals.h"
+
+// sim.src
+//#include "appcl.h"
+
+// local
+#include "simm68hc08cl.h"
+
+
+int
+main(int argc, char *argv[])
+{
+  class cl_sim *sim;
+
+  cpus= cpus_hc08;
+  application= new cl_app();
+  application->set_name("shc08");
+  application->init(argc, argv);
+  sim= new cl_simm68hc08(application);
+  if (sim->init())
+    sim->state|= SIM_QUIT;
+  application->set_simulator(sim);
+  application->run();
+  application->done();
+  delete application;
+  return(0);
+}
+
+
+/* End of hc08.src/sm68hc08.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m68hc08.src/test/clean.mk sdcc-4.2.0+dfsg/sim/ucsim/m68hc08.src/test/clean.mk
--- sdcc-4.0.0+dfsg/sim/ucsim/m68hc08.src/test/clean.mk	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m68hc08.src/test/clean.mk	2021-04-01 17:52:48.000000000 +0000
@@ -0,0 +1,5 @@
+clean:
+
+distclean:
+	rm -f Makefile
+	find . -type d -name out -exec rm -rf {} \;
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m68hc08.src/test/config/baseline/HC08 sdcc-4.2.0+dfsg/sim/ucsim/m68hc08.src/test/config/baseline/HC08
--- sdcc-4.0.0+dfsg/sim/ucsim/m68hc08.src/test/config/baseline/HC08	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m68hc08.src/test/config/baseline/HC08	2022-02-08 21:21:05.000000000 +0000
@@ -0,0 +1,25 @@
+uCsim, Copyright (C)  Daniel Drotos.
+uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+This is free software, and you are welcome to redistribute it
+under certain conditions; type `show c' for details.
+Type of microcontroller: unspecified HC08
+Controller has 4 hardware element(s).
+   on simif[0]
+  off vcd[0]
+   on dreg[0]
+   on cpu[0]
+V--HINZC  Flags= $60  96 `  A= $00   0 .
+0--00000      H= $00   0 .  X= $00   0 .
+SP= $00ff [SP+1]= 00   0 .  Limit= $7000
+0x6c75  ? 00 00 00    brset  #0,*$00,$6c78[0K
+Memory chips:
+  0x000000-0x0000ff      256 variable_storage (32,%08x,0x%02lx)
+  0x000000-0x00ffff    65536 rom_chip (8,%02x,0x%04lx)
+Address spaces:
+  0x000000-0x0000ff      256 variables (32,%08x,0x%02lx)
+  0x000000-0x00ffff    65536 rom (8,%02x,0x%04lx)
+  0x000000-0x000003        4 regs8 (8,%02x,0x%01lx)
+  0x000000-0x000000        1 regs16 (16,%04x,0x%01lx)
+Address decoders:
+  variables 0x00 0xff -> variable_storage 0x00 activated
+  rom 0x0000 0xffff -> rom_chip 0x0000 activated
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m68hc08.src/test/config/Makefile sdcc-4.2.0+dfsg/sim/ucsim/m68hc08.src/test/config/Makefile
--- sdcc-4.0.0+dfsg/sim/ucsim/m68hc08.src/test/config/Makefile	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m68hc08.src/test/config/Makefile	2021-03-21 12:01:19.000000000 +0000
@@ -0,0 +1,8 @@
+OUTPUTS = $(filter-out Parameter, $(shell $(SIM) -H | sort -u -k2b | cut -d' ' -f1))
+
+
+$(OUTPUTS):
+	$(call run-sim, -t $(@F) -e 'conf; info reg; info mem')
+
+
+include test-lib.mk
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m68hc08.src/test/Makefile.in sdcc-4.2.0+dfsg/sim/ucsim/m68hc08.src/test/Makefile.in
--- sdcc-4.0.0+dfsg/sim/ucsim/m68hc08.src/test/Makefile.in	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m68hc08.src/test/Makefile.in	2021-03-28 10:28:14.000000000 +0000
@@ -0,0 +1,9 @@
+# @configure_input@
+
+srcdir           = @abs_srcdir@
+
+abs_top_builddir = @abs_top_builddir@
+abs_top_srcdir   = @abs_top_srcdir@
+
+
+include $(abs_top_srcdir)/test-target.mk
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m68hc08.src/test/symdis/baseline/stdout sdcc-4.2.0+dfsg/sim/ucsim/m68hc08.src/test/symdis/baseline/stdout
--- sdcc-4.0.0+dfsg/sim/ucsim/m68hc08.src/test/symdis/baseline/stdout	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m68hc08.src/test/symdis/baseline/stdout	2022-02-08 21:21:05.000000000 +0000
@@ -0,0 +1,34 @@
+uCsim, Copyright (C)  Daniel Drotos.
+uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+This is free software, and you are welcome to redistribute it
+under certain conditions; type `show c' for details.
+var __sdcc_gs_init_startup rom[0x8000]
+var __sdcc_init_data rom[0x800c]
+var __sdcc_program_startup rom[0x8021]
+var _main rom[0x8026]
+dc 0x8000 0x8028
+
+0x8000    <__sdcc_gs_init_startup>:
+0x8000  ? 45 80 00    ldhx   #$8000 <__sdcc_gs_init_startup>[0K
+0x8003  ? 94          txs[0K
+0x8004  ? cd 80 29    jsr    $8029[0K
+0x8007  ? 27 03       beq    $800c <__sdcc_init_data>[0K
+0x8009  ? cc 80 21    jmp    $8021 <__sdcc_program_startup>[0K
+
+0x800c    <__sdcc_init_data>:
+0x800c  ? 45 00 00    ldhx   #$0000 <.reset>[0K
+0x800f  ? 65 00 00    cphx   #$0000 <.reset>[0K
+0x8012  ? 27 0a       beq    $801e[0K
+0x8014  ? d6 80 2b    lda    $802b,x[0K
+0x8017  ? d7 00 82    sta    $0082,x[0K
+0x801a  ? af 01       aix    #1[0K
+0x801c  ? 20 f1       bra    $800f[0K
+0x801e  ? cc 80 21    jmp    $8021 <__sdcc_program_startup>[0K
+
+0x8021    <__sdcc_program_startup>:
+0x8021  ? cd 80 26    jsr    $8026 <_main>[0K
+0x8024  ? 20 fe       bra    $8024[0K
+
+0x8026    <_main>:
+0x8026  ? 20 fe       bra    $8026 <_main>[0K
+0x8028  ? 81          rts[0K
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m68hc08.src/test/symdis/Makefile sdcc-4.2.0+dfsg/sim/ucsim/m68hc08.src/test/symdis/Makefile
--- sdcc-4.0.0+dfsg/sim/ucsim/m68hc08.src/test/symdis/Makefile	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m68hc08.src/test/symdis/Makefile	2021-05-07 16:21:16.000000000 +0000
@@ -0,0 +1,15 @@
+OUTPUTS = stdout
+
+
+# Ignore changes in white space. The field widths for labels
+# depends on the length of the longest label. This will be
+# different for different simulators and should not be assumed
+# to be constant for any given simulator.
+DIFF_OPTS += -b
+
+
+stdout:	test.ihx test.cmd
+	$(call run-sim, -t HC08)
+
+
+include test-lib.mk
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m68hc08.src/test/symdis/test.c sdcc-4.2.0+dfsg/sim/ucsim/m68hc08.src/test/symdis/test.c
--- sdcc-4.0.0+dfsg/sim/ucsim/m68hc08.src/test/symdis/test.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m68hc08.src/test/symdis/test.c	2021-05-07 16:21:16.000000000 +0000
@@ -0,0 +1,4 @@
+int main(int argc, char *argv[])
+{
+	for (;;);
+}
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m68hc08.src/test/symdis/test.cmd sdcc-4.2.0+dfsg/sim/ucsim/m68hc08.src/test/symdis/test.cmd
--- sdcc-4.0.0+dfsg/sim/ucsim/m68hc08.src/test/symdis/test.cmd	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m68hc08.src/test/symdis/test.cmd	2021-05-07 16:21:16.000000000 +0000
@@ -0,0 +1,5 @@
+var __sdcc_gs_init_startup rom[0x8000]
+var __sdcc_init_data rom[0x800c]
+var __sdcc_program_startup rom[0x8021]
+var _main rom[0x8026]
+dc 0x8000 0x8028
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m68hc08.src/test/symdis/test.ihx sdcc-4.2.0+dfsg/sim/ucsim/m68hc08.src/test/symdis/test.ihx
--- sdcc-4.0.0+dfsg/sim/ucsim/m68hc08.src/test/symdis/test.ihx	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m68hc08.src/test/symdis/test.ihx	2021-05-07 16:21:16.000000000 +0000
@@ -0,0 +1,5 @@
+:02FFFE00800081
+:2080000045800094CD80292703CC8021450000650000270AD6802BD70082AF0120F1CC8038
+:0680200021CD802620FEA8
+:0580260020FE814F81E6
+:00000001FF
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m68hc08.src/test/test-conf.mk sdcc-4.2.0+dfsg/sim/ucsim/m68hc08.src/test/test-conf.mk
--- sdcc-4.0.0+dfsg/sim/ucsim/m68hc08.src/test/test-conf.mk	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m68hc08.src/test/test-conf.mk	2021-05-07 16:21:16.000000000 +0000
@@ -0,0 +1,3 @@
+CC = sdcc -mhc08
+AS = sdas6808
+LD = sdld6808
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m68hc11.src/(c).1 sdcc-4.2.0+dfsg/sim/ucsim/m68hc11.src/(c).1
--- sdcc-4.0.0+dfsg/sim/ucsim/m68hc11.src/(c).1	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m68hc11.src/(c).1	2022-01-23 12:11:49.000000000 +0000
@@ -0,0 +1,25 @@
+/*
+ * Simulator of microcontrollers (@@F@@)
+ *
+ * Copyright (C) @@S@@,@@Y@@ Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m68hc11.src/clean.mk sdcc-4.2.0+dfsg/sim/ucsim/m68hc11.src/clean.mk
--- sdcc-4.0.0+dfsg/sim/ucsim/m68hc11.src/clean.mk	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m68hc11.src/clean.mk	2022-01-23 12:11:49.000000000 +0000
@@ -0,0 +1,32 @@
+# m68hc11.src/clean.mk
+
+# Deleting all files created by building the program
+# --------------------------------------------------
+clean:
+	rm -f *core *[%~] *.[oa] *.map
+	rm -f .[a-z]*~
+	rm -f sm68hc11$(EXEEXT) sm68hc11.exe
+	rm -f ucsim_m68hc11$(EXEEXT) ucsim_m68hc11.exe
+	$(MAKE) -C test -f clean.mk clean
+
+
+# Deleting all files created by configuring or building the program
+# -----------------------------------------------------------------
+distclean: clean
+	rm -f config.cache config.log config.status
+	rm -f Makefile *.dep
+	rm -f *.obj *.list *.lst *.hex
+	$(MAKE) -C test -f clean.mk distclean
+
+
+# Like clean but some files may still exist
+# -----------------------------------------
+mostlyclean: clean
+
+
+# Deleting everything that can reconstructed by this Makefile. It deletes
+# everything deleted by distclean plus files created by bison, etc.
+# -----------------------------------------------------------------------
+realclean: distclean
+
+# End of m68hc11.src/clean.mk
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m68hc11.src/conf.mk sdcc-4.2.0+dfsg/sim/ucsim/m68hc11.src/conf.mk
--- sdcc-4.0.0+dfsg/sim/ucsim/m68hc11.src/conf.mk	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m68hc11.src/conf.mk	2022-01-23 12:11:49.000000000 +0000
@@ -0,0 +1,11 @@
+# m68hc11.src/conf.mk
+#
+# Makefile targets to remake configuration
+#
+
+freshconf: Makefile
+
+Makefile: $(srcdir)/Makefile.in $(top_srcdir)/configure.ac
+	cd $(top_builddir) && $(SHELL) ./config.status
+
+# End of m68hc11.src/conf.mk
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m68hc11.src/d11p0.h sdcc-4.2.0+dfsg/sim/ucsim/m68hc11.src/d11p0.h
--- sdcc-4.0.0+dfsg/sim/ucsim/m68hc11.src/d11p0.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m68hc11.src/d11p0.h	2022-01-23 12:11:49.000000000 +0000
@@ -0,0 +1,77 @@
+/*
+ * Simulator of microcontrollers (d11p0.h)
+ *
+ * Copyright (C) @@S@@,@@Y@@ Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+
+#ifndef D11P0_HEADER
+#define D11P0_HEADER
+
+
+#define TEST	instruction_00
+#define IDIV	instruction_02
+#define FDIV	instruction_03
+#define LSRD	instruction_04
+#define ASLD	instruction_05
+#define BRN	instruction_21
+#define PULxy	instruction_38
+#define ABxy	instruction_3a
+#define PSHxy	instruction_3c
+#define MUL	instruction_3d
+#define SUBD16	instruction_83
+#define SUBDd	instruction_93
+#define SUBDxy	instruction_a3
+#define SUBDe	instruction_b3
+#define XGDxy	instruction_8f
+#define JSRd	instruction_9d
+#define ADDD16	instruction_c3
+#define ADDDd	instruction_d3
+#define ADDDi	instruction_e3
+#define ADDDe	instruction_f3
+#define LDD16	instruction_cc
+#define LDDd	instruction_dc
+#define LDDi	instruction_ec
+#define LDDe	instruction_fc
+#define STOP	instruction_cf
+#define STDd	instruction_dd
+#define STDi	instruction_ed
+#define STDe	instruction_fd
+#define BRSETd	instruction_12
+#define BRSETi	instruction_1e
+#define BRCLRd	instruction_13
+#define BRCLRi	instruction_1f
+#define BSETd	instruction_14
+#define BSETi	instruction_1c
+#define BCLRd	instruction_15
+#define BCLRi	instruction_1d
+
+#define PAGE18	instruction_18
+#define PAGE1A	instruction_1a
+#define PAGECD	instruction_cd
+
+
+#endif
+
+/* End of m6800.src/d11p0.h */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m68hc11.src/d11p18.h sdcc-4.2.0+dfsg/sim/ucsim/m68hc11.src/d11p18.h
--- sdcc-4.0.0+dfsg/sim/ucsim/m68hc11.src/d11p18.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m68hc11.src/d11p18.h	2022-01-23 12:11:49.000000000 +0000
@@ -0,0 +1,55 @@
+/*
+ * Simulator of microcontrollers (d11p18.h)
+ *
+ * Copyright (C) @@S@@,@@Y@@ Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+
+#ifndef D11P18_HEADER
+#define D11P18_HEADER
+
+
+#define INY	i_18_08
+#define DEY	i_18_09
+#define TSY	i_18_30
+#define TYS	i_18_35
+
+#define CPY16	i_18_8c
+#define CPYd	i_18_9c
+#define CPYi	i_18_ac
+#define CPYe	i_18_bc
+
+#define LDY16	i_18_ce
+#define LDYd	i_18_de
+#define LDYi	i_18_ee
+#define LDYe	i_18_fe
+
+#define STYd	i_18_df
+#define STYi	i_18_ef
+#define STYe	i_18_ff
+
+
+#endif
+
+/* End of m6800.src/d11p18.h */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m68hc11.src/g11p0.cc sdcc-4.2.0+dfsg/sim/ucsim/m68hc11.src/g11p0.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/m68hc11.src/g11p0.cc	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m68hc11.src/g11p0.cc	2022-01-23 12:11:49.000000000 +0000
@@ -0,0 +1,75 @@
+/*
+ * Simulator of microcontrollers (g11p0.cc)
+ *
+ * Copyright (C) @@S@@,@@Y@@ Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#include 
+
+#include "g11p0.h"
+
+// code, mask, branch, len, mnem, iscall, ticks
+struct dis_entry disass11p0[]= {
+
+  { 0x00, 0xff, ' ', 1, "TEST" },
+  { 0x02, 0xff, ' ', 1, "IDIV" },
+  { 0x03, 0xff, ' ', 1, "FDIV" },
+  { 0x04, 0xff, ' ', 1, "LSRD" },
+  { 0x05, 0xff, ' ', 1, "ASL D" },
+  { 0x21, 0xff, 'R', 2, "BRN %r" },
+  { 0x38, 0xff, ' ', 1, "PULX" },
+  { 0x3a, 0xff, ' ', 1, "ABX" },
+  { 0x3c, 0xff, ' ', 1, "PSHX" },
+  { 0x3d, 0xff, ' ', 1, "MUL" },
+  { 0x83, 0xff, ' ', 3, "SUB D,%B" },
+  { 0x93, 0xff, ' ', 2, "SUB D,%D" },
+  { 0xa3, 0xff, ' ', 2, "SUB D,%X" },
+  { 0xb3, 0xff, ' ', 3, "SUB D,%E" },
+  { 0x8f, 0xff, ' ', 1, "XGDX" },
+  { 0x9d, 0xff, 'd', 2, "JSR %d" },
+  { 0xc3, 0xff, ' ', 3, "ADD D,%B" },
+  { 0xd3, 0xff, ' ', 2, "ADD D,%D" },
+  { 0xe3, 0xff, ' ', 2, "ADD D,%X" },
+  { 0xf3, 0xff, ' ', 3, "ADD D,%E" },
+  { 0xcc, 0xff, ' ', 3, "LDD %B" },
+  { 0xdc, 0xff, ' ', 2, "LDD %D" },
+  { 0xec, 0xff, ' ', 2, "LDD %X" },
+  { 0xfc, 0xff, ' ', 3, "LDD %E" },
+  { 0xcf, 0xff, ' ', 1, "STOP" },
+  { 0xdd, 0xff, ' ', 2, "STD %D" },
+  { 0xed, 0xff, ' ', 2, "STD %X" },
+  { 0xfd, 0xff, ' ', 3, "STD %E" },
+  { 0x12, 0xff, 'R', 4, "BRSET %d,%b,%r" },
+  { 0x1e, 0xff, 'R', 4, "BRSET %x,%b,%r" },
+  { 0x13, 0xff, 'R', 4, "BRCLR %d,%b,%r" },
+  { 0x1f, 0xff, 'R', 4, "BRCLR %x,%b,%r" },
+  { 0x14, 0xff, ' ', 3, "BSET %d,%b" },
+  { 0x1c, 0xff, ' ', 3, "BSET %x,%b" },
+  { 0x15, 0xff, ' ', 3, "BCLR %d,%b" },
+  { 0x1d, 0xff, ' ', 3, "BCLR %x,%b" },
+  
+  { 0, 0, 0, 0, 0, 0 }
+};
+
+/* End of m6800.src/g11p0.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m68hc11.src/g11p0.h sdcc-4.2.0+dfsg/sim/ucsim/m68hc11.src/g11p0.h
--- sdcc-4.0.0+dfsg/sim/ucsim/m68hc11.src/g11p0.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m68hc11.src/g11p0.h	2022-01-23 12:11:49.000000000 +0000
@@ -0,0 +1,43 @@
+/*
+ * Simulator of microcontrollers (g11p0.h)
+ *
+ * Copyright (C) @@S@@,@@Y@@ Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef G11P0_HEADER
+#define G11P0_HEADER
+
+// prj
+#include "stypes.h"
+
+// sim
+//#include "iwrap.h"
+
+
+extern struct dis_entry disass11p0[];
+
+
+#endif
+
+/* End of m6800.src/g11p0.h */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m68hc11.src/g11p18.cc sdcc-4.2.0+dfsg/sim/ucsim/m68hc11.src/g11p18.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/m68hc11.src/g11p18.cc	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m68hc11.src/g11p18.cc	2022-01-23 12:11:49.000000000 +0000
@@ -0,0 +1,104 @@
+/*
+ * Simulator of microcontrollers (g11p18.cc)
+ *
+ * Copyright (C) @@S@@,@@Y@@ Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#include 
+
+#include "g11p18.h"
+
+// code, mask, branch, len, mnem, iscall, ticks
+struct dis_entry disass11p18[]= {
+
+  { 0x08, 0xff, ' ', 2, "INY" },
+  { 0x09, 0xff, ' ', 2, "DEY" },
+  { 0x30, 0xff, ' ', 2, "TSY" },
+  { 0x35, 0xff, ' ', 2, "TYS" },
+  { 0x38, 0xff, ' ', 2, "PULY" },
+  { 0x3a, 0xff, ' ', 2, "ABY" },
+  { 0x3c, 0xff, ' ', 2, "PSHY" },
+  { 0x60, 0xff, ' ', 3, "NEG %x" },
+  { 0x63, 0xff, ' ', 3, "COM %x" },
+  { 0x64, 0xff, ' ', 3, "LSR %x" },
+  { 0x66, 0xff, ' ', 3, "ROR %x" },
+  { 0x67, 0xff, ' ', 3, "ASR %x" },
+  { 0x68, 0xff, ' ', 3, "ASL %x" },
+  { 0x69, 0xff, ' ', 3, "ROL %x" },
+  { 0x6a, 0xff, ' ', 3, "DEC %x" },
+  { 0x6c, 0xff, ' ', 3, "INC %x" },
+  { 0x6d, 0xff, ' ', 3, "TST %x" },
+  { 0x6e, 0xff, '_', 3, "JMP %x" },
+  { 0x6f, 0xff, ' ', 3, "CLR %x" },
+  { 0x8c, 0xff, ' ', 4, "CPY %B" },
+  { 0x8f, 0xff, ' ', 2, "XGDY" },
+  { 0x9c, 0xff, ' ', 3, "CPY %D" },
+  { 0xa0, 0xff, ' ', 3, "SUB A,%x" },
+  { 0xa1, 0xff, ' ', 3, "CMP A,%x" },
+  { 0xa2, 0xff, ' ', 3, "SBC A,%x" },
+  { 0xa3, 0xff, ' ', 3, "SUB D,%X" },  
+  { 0xa4, 0xff, ' ', 3, "AND A,%x" },
+  { 0xa5, 0xff, ' ', 3, "BIT A,%x" },
+  { 0xa6, 0xff, ' ', 3, "LDA A,%x" },
+  { 0xa7, 0xff, ' ', 3, "STA A,%x" },
+  { 0xa8, 0xff, ' ', 3, "EOR A,%x" },
+  { 0xa9, 0xff, ' ', 3, "ADC A,%x" },
+  { 0xaa, 0xff, ' ', 3, "ORA A,%x" },
+  { 0xab, 0xff, ' ', 3, "ADD A,%x" },
+  { 0xac, 0xff, ' ', 3, "CPY %X" },
+  { 0xad, 0xff, '_', 3, "JSR %X" },
+  { 0xae, 0xff, ' ', 3, "LDS %X" },
+  { 0xaf, 0xff, ' ', 3, "STS %X" },
+  { 0xbc, 0xff, ' ', 4, "CPY %E" },
+  { 0xce, 0xff, ' ', 3, "LDY %B" },
+  { 0xde, 0xff, ' ', 3, "LDY %D" },
+  { 0xde, 0xff, ' ', 3, "LDY %X" },
+  { 0xfe, 0xff, ' ', 3, "LDY %E" },
+  { 0xdf, 0xff, ' ', 3, "STY %D" },
+  { 0xdf, 0xff, ' ', 3, "STY %X" },
+  { 0xff, 0xff, ' ', 3, "STY %E" },
+  { 0xe0, 0xff, ' ', 3, "SUB B,%x" },
+  { 0xe1, 0xff, ' ', 3, "CMP B,%x" },
+  { 0xe2, 0xff, ' ', 3, "SBC B,%x" },
+  { 0xe3, 0xff, ' ', 3, "ADD D,%X" },
+  { 0xe4, 0xff, ' ', 3, "AND B,%x" },
+  { 0xe5, 0xff, ' ', 3, "BIT B,%x" },
+  { 0xe6, 0xff, ' ', 3, "LDA B,%x" },
+  { 0xe7, 0xff, ' ', 3, "STA B,%x" },
+  { 0xe8, 0xff, ' ', 3, "EOR B,%x" },
+  { 0xe9, 0xff, ' ', 3, "ADC B,%x" },
+  { 0xea, 0xff, ' ', 3, "ORA B,%x" },
+  { 0xeb, 0xff, ' ', 3, "ADD B,%x" },
+  { 0xec, 0xff, ' ', 3, "LDD %X" },
+  { 0xed, 0xff, ' ', 3, "STD %X" },
+
+  { 0x1c, 0xff, ' ', 3, "BSET %x,%b" },
+  { 0x1e, 0xff, 'R', 4, "BRSET %x,%b,%r" },
+  { 0x1d, 0xff, ' ', 3, "BCLR %x,%b" },
+  { 0x1f, 0xff, 'R', 4, "BRCLR %x,%b,%r" },
+
+  { 0, 0, 0, 0, 0, 0 }
+};
+
+/* End of m6800.src/g11p18.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m68hc11.src/g11p18.h sdcc-4.2.0+dfsg/sim/ucsim/m68hc11.src/g11p18.h
--- sdcc-4.0.0+dfsg/sim/ucsim/m68hc11.src/g11p18.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m68hc11.src/g11p18.h	2022-01-23 12:11:49.000000000 +0000
@@ -0,0 +1,43 @@
+/*
+ * Simulator of microcontrollers (g11p18.h)
+ *
+ * Copyright (C) @@S@@,@@Y@@ Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef G11P18_HEADER
+#define G11P18_HEADER
+
+// prj
+#include "stypes.h"
+
+// sim
+//#include "iwrap.h"
+
+
+extern struct dis_entry disass11p18[];
+
+
+#endif
+
+/* End of m6800.src/g11p18.h */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m68hc11.src/g11p1a.cc sdcc-4.2.0+dfsg/sim/ucsim/m68hc11.src/g11p1a.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/m68hc11.src/g11p1a.cc	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m68hc11.src/g11p1a.cc	2022-01-23 12:11:49.000000000 +0000
@@ -0,0 +1,47 @@
+/*
+ * Simulator of microcontrollers (g11p1a.cc)
+ *
+ * Copyright (C) @@S@@,@@Y@@ Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#include 
+
+#include "g11p1a.h"
+
+// code, mask, branch, len, mnem, iscall, ticks
+struct dis_entry disass11p1a[]= {
+
+  { 0x83, 0xff, ' ', 3, "CPD %B" },  
+  { 0x93, 0xff, ' ', 3, "CPD %D" },  
+  { 0xa3, 0xff, ' ', 3, "CPD %X" },  
+  { 0xb3, 0xff, ' ', 3, "CPD %E" },  
+
+  { 0xad, 0xff, ' ', 3, "CPY %X" },
+  { 0xee, 0xff, ' ', 2, "LDY %x" },
+  { 0xef, 0xff, ' ', 2, "STY %x" },
+
+  { 0, 0, 0, 0, 0, 0 }
+};
+
+/* End of m6800.src/g11p1a.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m68hc11.src/g11p1a.h sdcc-4.2.0+dfsg/sim/ucsim/m68hc11.src/g11p1a.h
--- sdcc-4.0.0+dfsg/sim/ucsim/m68hc11.src/g11p1a.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m68hc11.src/g11p1a.h	2022-01-23 12:11:49.000000000 +0000
@@ -0,0 +1,43 @@
+/*
+ * Simulator of microcontrollers (g11p1a.h)
+ *
+ * Copyright (C) @@S@@,@@Y@@ Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef G11P1A_HEADER
+#define G11P1A_HEADER
+
+// prj
+#include "stypes.h"
+
+// sim
+//#include "iwrap.h"
+
+
+extern struct dis_entry disass11p1a[];
+
+
+#endif
+
+/* End of m6800.src/g11p1a.h */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m68hc11.src/g11pcd.cc sdcc-4.2.0+dfsg/sim/ucsim/m68hc11.src/g11pcd.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/m68hc11.src/g11pcd.cc	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m68hc11.src/g11pcd.cc	2022-01-23 12:11:49.000000000 +0000
@@ -0,0 +1,43 @@
+/*
+ * Simulator of microcontrollers (g11pcd.cc)
+ *
+ * Copyright (C) @@S@@,@@Y@@ Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#include 
+
+#include "g11pcd.h"
+
+// code, mask, branch, len, mnem, iscall, ticks
+struct dis_entry disass11pcd[]= {
+
+  { 0xa3, 0xff, ' ', 3, "CPD %X" },  
+  { 0xad, 0xff, ' ', 3, "CPD %X" },
+  { 0xee, 0xff, ' ', 2, "LDX %x" },
+  { 0xef, 0xff, ' ', 2, "STX %x" },
+
+  { 0, 0, 0, 0, 0, 0 }
+};
+
+/* End of m6800.src/g11pcd.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m68hc11.src/g11pcd.h sdcc-4.2.0+dfsg/sim/ucsim/m68hc11.src/g11pcd.h
--- sdcc-4.0.0+dfsg/sim/ucsim/m68hc11.src/g11pcd.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m68hc11.src/g11pcd.h	2022-01-23 12:11:49.000000000 +0000
@@ -0,0 +1,43 @@
+/*
+ * Simulator of microcontrollers (g11pcd.h)
+ *
+ * Copyright (C) @@S@@,@@Y@@ Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef G11PCD_HEADER
+#define G11PCD_HEADER
+
+// prj
+#include "stypes.h"
+
+// sim
+//#include "iwrap.h"
+
+
+extern struct dis_entry disass11pcd[];
+
+
+#endif
+
+/* End of m6800.src/g11pcd.h */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m68hc11.src/glob11.cc sdcc-4.2.0+dfsg/sim/ucsim/m68hc11.src/glob11.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/m68hc11.src/glob11.cc	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m68hc11.src/glob11.cc	2022-01-23 12:11:49.000000000 +0000
@@ -0,0 +1,41 @@
+/*
+ * Simulator of microcontrollers (glob11.cc)
+ *
+ * Copyright (C) @@S@@,@@Y@@ Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#include 
+
+#include "glob11.h"
+
+
+struct cpu_entry cpus_hc11[]=
+  {
+    {"HC11"  , CPU_HC11, CPU_CMOS	, "hc11"	, "cmos"},
+
+    {NULL, CPU_NONE, 0, "", ""}
+  };
+
+
+/* End of m6800.src/glob11.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m68hc11.src/glob11.h sdcc-4.2.0+dfsg/sim/ucsim/m68hc11.src/glob11.h
--- sdcc-4.0.0+dfsg/sim/ucsim/m68hc11.src/glob11.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m68hc11.src/glob11.h	2022-01-23 12:11:49.000000000 +0000
@@ -0,0 +1,43 @@
+/*
+ * Simulator of microcontrollers (glob11.h)
+ *
+ * Copyright (C) @@S@@,@@Y@@ Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef HC12GLOB11_HEADER
+#define HC12GLOB11_HEADER
+
+// prj
+#include "stypes.h"
+
+// sim
+//#include "iwrap.h"
+
+
+extern struct cpu_entry cpus_hc11[];
+
+
+#endif
+
+/* End of m6800.src/glob11.h */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m68hc11.src/hc18.h sdcc-4.2.0+dfsg/sim/ucsim/m68hc11.src/hc18.h
--- sdcc-4.0.0+dfsg/sim/ucsim/m68hc11.src/hc18.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m68hc11.src/hc18.h	2022-01-23 12:11:49.000000000 +0000
@@ -0,0 +1,256 @@
+virtual int i_18_00(t_mem code){return resINV;}
+virtual int i_18_01(t_mem code){return resINV;}
+virtual int i_18_02(t_mem code){return resINV;}
+virtual int i_18_03(t_mem code){return resINV;}
+virtual int i_18_04(t_mem code){return resINV;}
+virtual int i_18_05(t_mem code){return resINV;}
+virtual int i_18_06(t_mem code){return resINV;}
+virtual int i_18_07(t_mem code){return resINV;}
+virtual int i_18_08(t_mem code){return resINV;}
+virtual int i_18_09(t_mem code){return resINV;}
+virtual int i_18_0a(t_mem code){return resINV;}
+virtual int i_18_0b(t_mem code){return resINV;}
+virtual int i_18_0c(t_mem code){return resINV;}
+virtual int i_18_0d(t_mem code){return resINV;}
+virtual int i_18_0e(t_mem code){return resINV;}
+virtual int i_18_0f(t_mem code){return resINV;}
+virtual int i_18_10(t_mem code){return resINV;}
+virtual int i_18_11(t_mem code){return resINV;}
+virtual int i_18_12(t_mem code){return resINV;}
+virtual int i_18_13(t_mem code){return resINV;}
+virtual int i_18_14(t_mem code){return resINV;}
+virtual int i_18_15(t_mem code){return resINV;}
+virtual int i_18_16(t_mem code){return resINV;}
+virtual int i_18_17(t_mem code){return resINV;}
+virtual int i_18_18(t_mem code){return resINV;}
+virtual int i_18_19(t_mem code){return resINV;}
+virtual int i_18_1a(t_mem code){return resINV;}
+virtual int i_18_1b(t_mem code){return resINV;}
+virtual int i_18_1c(t_mem code){return resINV;}
+virtual int i_18_1d(t_mem code){return resINV;}
+virtual int i_18_1e(t_mem code){return resINV;}
+virtual int i_18_1f(t_mem code){return resINV;}
+virtual int i_18_20(t_mem code){return resINV;}
+virtual int i_18_21(t_mem code){return resINV;}
+virtual int i_18_22(t_mem code){return resINV;}
+virtual int i_18_23(t_mem code){return resINV;}
+virtual int i_18_24(t_mem code){return resINV;}
+virtual int i_18_25(t_mem code){return resINV;}
+virtual int i_18_26(t_mem code){return resINV;}
+virtual int i_18_27(t_mem code){return resINV;}
+virtual int i_18_28(t_mem code){return resINV;}
+virtual int i_18_29(t_mem code){return resINV;}
+virtual int i_18_2a(t_mem code){return resINV;}
+virtual int i_18_2b(t_mem code){return resINV;}
+virtual int i_18_2c(t_mem code){return resINV;}
+virtual int i_18_2d(t_mem code){return resINV;}
+virtual int i_18_2e(t_mem code){return resINV;}
+virtual int i_18_2f(t_mem code){return resINV;}
+virtual int i_18_30(t_mem code){return resINV;}
+virtual int i_18_31(t_mem code){return resINV;}
+virtual int i_18_32(t_mem code){return resINV;}
+virtual int i_18_33(t_mem code){return resINV;}
+virtual int i_18_34(t_mem code){return resINV;}
+virtual int i_18_35(t_mem code){return resINV;}
+virtual int i_18_36(t_mem code){return resINV;}
+virtual int i_18_37(t_mem code){return resINV;}
+virtual int i_18_38(t_mem code){return resINV;}
+virtual int i_18_39(t_mem code){return resINV;}
+virtual int i_18_3a(t_mem code){return resINV;}
+virtual int i_18_3b(t_mem code){return resINV;}
+virtual int i_18_3c(t_mem code){return resINV;}
+virtual int i_18_3d(t_mem code){return resINV;}
+virtual int i_18_3e(t_mem code){return resINV;}
+virtual int i_18_3f(t_mem code){return resINV;}
+virtual int i_18_40(t_mem code){return resINV;}
+virtual int i_18_41(t_mem code){return resINV;}
+virtual int i_18_42(t_mem code){return resINV;}
+virtual int i_18_43(t_mem code){return resINV;}
+virtual int i_18_44(t_mem code){return resINV;}
+virtual int i_18_45(t_mem code){return resINV;}
+virtual int i_18_46(t_mem code){return resINV;}
+virtual int i_18_47(t_mem code){return resINV;}
+virtual int i_18_48(t_mem code){return resINV;}
+virtual int i_18_49(t_mem code){return resINV;}
+virtual int i_18_4a(t_mem code){return resINV;}
+virtual int i_18_4b(t_mem code){return resINV;}
+virtual int i_18_4c(t_mem code){return resINV;}
+virtual int i_18_4d(t_mem code){return resINV;}
+virtual int i_18_4e(t_mem code){return resINV;}
+virtual int i_18_4f(t_mem code){return resINV;}
+virtual int i_18_50(t_mem code){return resINV;}
+virtual int i_18_51(t_mem code){return resINV;}
+virtual int i_18_52(t_mem code){return resINV;}
+virtual int i_18_53(t_mem code){return resINV;}
+virtual int i_18_54(t_mem code){return resINV;}
+virtual int i_18_55(t_mem code){return resINV;}
+virtual int i_18_56(t_mem code){return resINV;}
+virtual int i_18_57(t_mem code){return resINV;}
+virtual int i_18_58(t_mem code){return resINV;}
+virtual int i_18_59(t_mem code){return resINV;}
+virtual int i_18_5a(t_mem code){return resINV;}
+virtual int i_18_5b(t_mem code){return resINV;}
+virtual int i_18_5c(t_mem code){return resINV;}
+virtual int i_18_5d(t_mem code){return resINV;}
+virtual int i_18_5e(t_mem code){return resINV;}
+virtual int i_18_5f(t_mem code){return resINV;}
+virtual int i_18_60(t_mem code){return resINV;}
+virtual int i_18_61(t_mem code){return resINV;}
+virtual int i_18_62(t_mem code){return resINV;}
+virtual int i_18_63(t_mem code){return resINV;}
+virtual int i_18_64(t_mem code){return resINV;}
+virtual int i_18_65(t_mem code){return resINV;}
+virtual int i_18_66(t_mem code){return resINV;}
+virtual int i_18_67(t_mem code){return resINV;}
+virtual int i_18_68(t_mem code){return resINV;}
+virtual int i_18_69(t_mem code){return resINV;}
+virtual int i_18_6a(t_mem code){return resINV;}
+virtual int i_18_6b(t_mem code){return resINV;}
+virtual int i_18_6c(t_mem code){return resINV;}
+virtual int i_18_6d(t_mem code){return resINV;}
+virtual int i_18_6e(t_mem code){return resINV;}
+virtual int i_18_6f(t_mem code){return resINV;}
+virtual int i_18_70(t_mem code){return resINV;}
+virtual int i_18_71(t_mem code){return resINV;}
+virtual int i_18_72(t_mem code){return resINV;}
+virtual int i_18_73(t_mem code){return resINV;}
+virtual int i_18_74(t_mem code){return resINV;}
+virtual int i_18_75(t_mem code){return resINV;}
+virtual int i_18_76(t_mem code){return resINV;}
+virtual int i_18_77(t_mem code){return resINV;}
+virtual int i_18_78(t_mem code){return resINV;}
+virtual int i_18_79(t_mem code){return resINV;}
+virtual int i_18_7a(t_mem code){return resINV;}
+virtual int i_18_7b(t_mem code){return resINV;}
+virtual int i_18_7c(t_mem code){return resINV;}
+virtual int i_18_7d(t_mem code){return resINV;}
+virtual int i_18_7e(t_mem code){return resINV;}
+virtual int i_18_7f(t_mem code){return resINV;}
+virtual int i_18_80(t_mem code){return resINV;}
+virtual int i_18_81(t_mem code){return resINV;}
+virtual int i_18_82(t_mem code){return resINV;}
+virtual int i_18_83(t_mem code){return resINV;}
+virtual int i_18_84(t_mem code){return resINV;}
+virtual int i_18_85(t_mem code){return resINV;}
+virtual int i_18_86(t_mem code){return resINV;}
+virtual int i_18_87(t_mem code){return resINV;}
+virtual int i_18_88(t_mem code){return resINV;}
+virtual int i_18_89(t_mem code){return resINV;}
+virtual int i_18_8a(t_mem code){return resINV;}
+virtual int i_18_8b(t_mem code){return resINV;}
+virtual int i_18_8c(t_mem code){return resINV;}
+virtual int i_18_8d(t_mem code){return resINV;}
+virtual int i_18_8e(t_mem code){return resINV;}
+virtual int i_18_8f(t_mem code){return resINV;}
+virtual int i_18_90(t_mem code){return resINV;}
+virtual int i_18_91(t_mem code){return resINV;}
+virtual int i_18_92(t_mem code){return resINV;}
+virtual int i_18_93(t_mem code){return resINV;}
+virtual int i_18_94(t_mem code){return resINV;}
+virtual int i_18_95(t_mem code){return resINV;}
+virtual int i_18_96(t_mem code){return resINV;}
+virtual int i_18_97(t_mem code){return resINV;}
+virtual int i_18_98(t_mem code){return resINV;}
+virtual int i_18_99(t_mem code){return resINV;}
+virtual int i_18_9a(t_mem code){return resINV;}
+virtual int i_18_9b(t_mem code){return resINV;}
+virtual int i_18_9c(t_mem code){return resINV;}
+virtual int i_18_9d(t_mem code){return resINV;}
+virtual int i_18_9e(t_mem code){return resINV;}
+virtual int i_18_9f(t_mem code){return resINV;}
+virtual int i_18_a0(t_mem code){return resINV;}
+virtual int i_18_a1(t_mem code){return resINV;}
+virtual int i_18_a2(t_mem code){return resINV;}
+virtual int i_18_a3(t_mem code){return resINV;}
+virtual int i_18_a4(t_mem code){return resINV;}
+virtual int i_18_a5(t_mem code){return resINV;}
+virtual int i_18_a6(t_mem code){return resINV;}
+virtual int i_18_a7(t_mem code){return resINV;}
+virtual int i_18_a8(t_mem code){return resINV;}
+virtual int i_18_a9(t_mem code){return resINV;}
+virtual int i_18_aa(t_mem code){return resINV;}
+virtual int i_18_ab(t_mem code){return resINV;}
+virtual int i_18_ac(t_mem code){return resINV;}
+virtual int i_18_ad(t_mem code){return resINV;}
+virtual int i_18_ae(t_mem code){return resINV;}
+virtual int i_18_af(t_mem code){return resINV;}
+virtual int i_18_b0(t_mem code){return resINV;}
+virtual int i_18_b1(t_mem code){return resINV;}
+virtual int i_18_b2(t_mem code){return resINV;}
+virtual int i_18_b3(t_mem code){return resINV;}
+virtual int i_18_b4(t_mem code){return resINV;}
+virtual int i_18_b5(t_mem code){return resINV;}
+virtual int i_18_b6(t_mem code){return resINV;}
+virtual int i_18_b7(t_mem code){return resINV;}
+virtual int i_18_b8(t_mem code){return resINV;}
+virtual int i_18_b9(t_mem code){return resINV;}
+virtual int i_18_ba(t_mem code){return resINV;}
+virtual int i_18_bb(t_mem code){return resINV;}
+virtual int i_18_bc(t_mem code){return resINV;}
+virtual int i_18_bd(t_mem code){return resINV;}
+virtual int i_18_be(t_mem code){return resINV;}
+virtual int i_18_bf(t_mem code){return resINV;}
+virtual int i_18_c0(t_mem code){return resINV;}
+virtual int i_18_c1(t_mem code){return resINV;}
+virtual int i_18_c2(t_mem code){return resINV;}
+virtual int i_18_c3(t_mem code){return resINV;}
+virtual int i_18_c4(t_mem code){return resINV;}
+virtual int i_18_c5(t_mem code){return resINV;}
+virtual int i_18_c6(t_mem code){return resINV;}
+virtual int i_18_c7(t_mem code){return resINV;}
+virtual int i_18_c8(t_mem code){return resINV;}
+virtual int i_18_c9(t_mem code){return resINV;}
+virtual int i_18_ca(t_mem code){return resINV;}
+virtual int i_18_cb(t_mem code){return resINV;}
+virtual int i_18_cc(t_mem code){return resINV;}
+virtual int i_18_cd(t_mem code){return resINV;}
+virtual int i_18_ce(t_mem code){return resINV;}
+virtual int i_18_cf(t_mem code){return resINV;}
+virtual int i_18_d0(t_mem code){return resINV;}
+virtual int i_18_d1(t_mem code){return resINV;}
+virtual int i_18_d2(t_mem code){return resINV;}
+virtual int i_18_d3(t_mem code){return resINV;}
+virtual int i_18_d4(t_mem code){return resINV;}
+virtual int i_18_d5(t_mem code){return resINV;}
+virtual int i_18_d6(t_mem code){return resINV;}
+virtual int i_18_d7(t_mem code){return resINV;}
+virtual int i_18_d8(t_mem code){return resINV;}
+virtual int i_18_d9(t_mem code){return resINV;}
+virtual int i_18_da(t_mem code){return resINV;}
+virtual int i_18_db(t_mem code){return resINV;}
+virtual int i_18_dc(t_mem code){return resINV;}
+virtual int i_18_dd(t_mem code){return resINV;}
+virtual int i_18_de(t_mem code){return resINV;}
+virtual int i_18_df(t_mem code){return resINV;}
+virtual int i_18_e0(t_mem code){return resINV;}
+virtual int i_18_e1(t_mem code){return resINV;}
+virtual int i_18_e2(t_mem code){return resINV;}
+virtual int i_18_e3(t_mem code){return resINV;}
+virtual int i_18_e4(t_mem code){return resINV;}
+virtual int i_18_e5(t_mem code){return resINV;}
+virtual int i_18_e6(t_mem code){return resINV;}
+virtual int i_18_e7(t_mem code){return resINV;}
+virtual int i_18_e8(t_mem code){return resINV;}
+virtual int i_18_e9(t_mem code){return resINV;}
+virtual int i_18_ea(t_mem code){return resINV;}
+virtual int i_18_eb(t_mem code){return resINV;}
+virtual int i_18_ec(t_mem code){return resINV;}
+virtual int i_18_ed(t_mem code){return resINV;}
+virtual int i_18_ee(t_mem code){return resINV;}
+virtual int i_18_ef(t_mem code){return resINV;}
+virtual int i_18_f0(t_mem code){return resINV;}
+virtual int i_18_f1(t_mem code){return resINV;}
+virtual int i_18_f2(t_mem code){return resINV;}
+virtual int i_18_f3(t_mem code){return resINV;}
+virtual int i_18_f4(t_mem code){return resINV;}
+virtual int i_18_f5(t_mem code){return resINV;}
+virtual int i_18_f6(t_mem code){return resINV;}
+virtual int i_18_f7(t_mem code){return resINV;}
+virtual int i_18_f8(t_mem code){return resINV;}
+virtual int i_18_f9(t_mem code){return resINV;}
+virtual int i_18_fa(t_mem code){return resINV;}
+virtual int i_18_fb(t_mem code){return resINV;}
+virtual int i_18_fc(t_mem code){return resINV;}
+virtual int i_18_fd(t_mem code){return resINV;}
+virtual int i_18_fe(t_mem code){return resINV;}
+virtual int i_18_ff(t_mem code){return resINV;}
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m68hc11.src/m68hc11.cc sdcc-4.2.0+dfsg/sim/ucsim/m68hc11.src/m68hc11.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/m68hc11.src/m68hc11.cc	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m68hc11.src/m68hc11.cc	2022-01-24 11:09:43.000000000 +0000
@@ -0,0 +1,791 @@
+/*
+ * Simulator of microcontrollers (m68hc11.cc)
+ *
+ * Copyright (C) 2020,20 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#include 
+#include 
+
+#include "globals.h"
+#include "utils.h"
+
+#include "dregcl.h"
+#include "g11p0.h"
+#include "g11p18.h"
+#include "g11p1a.h"
+#include "g11pcd.h"
+#include "wraps.h"
+
+#include "m68hc11cl.h"
+
+
+instruction_wrapper_fn itab18[256];
+
+int8_t p0ticks11[256]= {
+  /*      0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f  */
+  /* 0 */ 0, 2,40,40, 3, 3, 2, 2, 3, 3, 2, 2, 2, 2, 2, 2,
+  /* 1 */ 2, 2, 6, 6, 6, 6, 2, 2, 0, 2, 0, 2, 7, 7, 7, 7,
+  /* 2 */ 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
+  /* 3 */ 3, 3, 4, 4, 3, 3, 3, 3, 5, 5, 3,12, 4, 3,14,14,
+  /* 4 */ 2, 0, 0, 2, 2, 0, 2, 2, 2, 2, 2, 0, 2, 2, 0, 2,
+  /* 5 */ 2, 0, 0, 2, 2, 0, 2, 2, 2, 2, 2, 0, 2, 2, 0, 2,
+  /* 6 */ 6, 0, 0, 6, 6, 0, 6, 6, 6, 6, 6, 0, 6, 6, 3, 6,
+  /* 7 */ 6, 0, 0, 6, 6, 0, 6, 6, 6, 6, 6, 0, 6, 6, 3, 6,
+  /* 8 */ 2, 2, 2, 4, 2, 2, 2, 0, 2, 2, 2, 2, 4, 6, 3, 3,
+  /* 9 */ 3, 3, 3, 5, 3, 3, 3, 3, 3, 3, 3, 3, 5, 5, 4, 4,
+  /* a */ 4, 4, 4, 6, 4, 4, 4, 4, 4, 4, 4, 4, 6, 6, 5, 5,
+  /* b */ 4, 4, 4, 6, 4, 4, 4, 4, 4, 4, 4, 4, 6, 6, 5, 5,
+  /* c */ 2, 2, 2, 4, 2, 2, 2, 0, 2, 2, 2, 2, 3, 0, 3, 2,
+  /* d */ 3, 3, 3, 5, 3, 3, 3, 3, 3, 3, 3, 3, 4, 4, 4, 4,
+  /* e */ 4, 4, 4, 6, 4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 5, 5,
+  /* f */ 4, 4, 4, 6, 4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 5, 5
+};
+
+int8_t p18ticks11[256]= {
+  /*      0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f  */
+  /* 0 */ 0, 0, 0, 0, 0, 0, 0, 0, 4, 4, 0, 0, 0, 0, 0, 0,
+  /* 1 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 8, 8, 8, 8,
+  /* 2 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+  /* 3 */ 4, 0, 0, 0, 0, 4, 0, 0, 6, 0, 4, 0, 5, 0, 0, 0,
+  /* 4 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+  /* 5 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+  /* 6 */ 7, 0, 0, 7, 7, 0, 7, 7, 7, 7, 7, 0, 7, 7, 4, 7,
+  /* 7 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+  /* 8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5, 0, 0, 4,
+  /* 9 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, 0, 0, 0,
+  /* a */ 5, 5, 5, 7, 5, 5, 5, 5, 5, 5, 5, 5, 7, 7, 6, 6,
+  /* b */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 7, 0, 0,
+  /* c */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 0,
+  /* d */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5, 5,
+  /* e */ 5, 5, 5, 7, 5, 5, 5, 5, 5, 5, 5, 5, 6, 6, 5, 6,
+  /* f */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5, 6
+};
+
+int8_t pcdticks11[256]= {
+  /*      0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f  */
+  /* 0 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+  /* 1 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+  /* 2 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+  /* 3 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+  /* 4 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+  /* 5 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+  /* 6 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+  /* 7 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+  /* 8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+  /* 9 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+  /* a */ 0, 0, 0, 7, 0, 0, 0, 0, 0, 0, 0, 0, 7, 0, 0, 0,
+  /* b */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+  /* c */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+  /* d */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+  /* e */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, 6,
+  /* f */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+int8_t p1aticks11[256]= {
+  /*      0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f  */
+  /* 0 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+  /* 1 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+  /* 2 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+  /* 3 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+  /* 4 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+  /* 5 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+  /* 6 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+  /* 7 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+  /* 8 */ 0, 0, 0, 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+  /* 9 */ 0, 0, 0, 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+  /* a */ 0, 0, 0, 7, 0, 0, 0, 0, 0, 0, 0, 0, 7, 0, 0, 0,
+  /* b */ 0, 0, 0, 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+  /* c */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+  /* d */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+  /* e */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, 0,
+  /* f */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, 0
+};
+
+
+int
+cl_m68hcbase::init(void)
+{
+  cl_m6800::init();
+  
+#define RCV(R) reg_cell_var(&c ## R , &r ## R , "" #R "" , "CPU register " #R "")
+  RCV(IY);
+  RCV(D);
+#undef RCV
+
+  cIY.name= "Y";
+  
+  fill_def_18_wrappers(itab18);
+  // un-wrap some codes, where m6800 version is capable to handle
+  // indexing with IY
+#define UW(code) itab18[0x ## code ]= instruction_wrapper_ ## code
+  UW(38); UW(3a); UW(3c);
+  UW(60); UW(63); UW(64); UW(66); UW(67); UW(68);
+  UW(69); UW(6a); UW(6c); UW(6d); UW(6e); UW(6f);
+  UW(8f);
+  UW(a0); UW(a1); UW(a2); UW(a3); UW(a4); UW(a5); UW(a6); UW(a7); 
+  UW(a8); UW(a9); UW(aa); UW(ab);         UW(ad); UW(ae); UW(af); 
+  UW(e0); UW(e1); UW(e2); UW(e3); UW(e4); UW(e5); UW(e6); UW(e7); 
+  UW(e8); UW(e9); UW(ea); UW(eb); UW(ec); UW(ed);
+  UW(1c); UW(1d); UW(1e); UW(1f);
+#undef UW
+  return 0;
+}
+
+void
+cl_m68hcbase::print_regs(class cl_console_base *con)
+{
+  con->dd_color("answer");
+  con->dd_printf("A= $%02x %3d %+4d %c  ", rA, rA, (i8_t)rA, isprint(rA)?rA:'.');
+  con->dd_printf("B= $%02x %3d %+4d %c  ", rB, rB, (i8_t)rB, isprint(rB)?rB:'.');
+  con->dd_printf("D= $%04x %5d %+5d ", rD, rD, (i16_t)rD);
+  con->dd_printf("\n");
+  con->dd_printf("CC= "); con->print_bin(rF, 8); con->dd_printf("\n");
+  con->dd_printf("      HINZVC\n");
+
+  con->dd_printf("IX= ");
+  rom->dump(0, IX, IX+7, 8, con);
+  con->dd_color("answer");
+  
+  con->dd_printf("IY= ");
+  rom->dump(0, IY, IY+7, 8, con);
+  con->dd_color("answer");
+  
+  con->dd_printf("SP= ");
+  rom->dump(0, SP, SP+7, 8, con);
+  con->dd_color("answer");
+  
+  print_disass(PC, con);
+}
+
+
+cl_m68hc11::cl_m68hc11(class cl_sim *asim):
+  cl_m68hcbase(asim)
+{
+}
+
+
+int
+cl_m68hc11::init(void)
+{
+  cl_m68hcbase::init();
+  
+  set_xtal(8000000);
+  
+  return 0;
+}
+
+
+const char *
+cl_m68hc11::id_string(void)
+{
+  return "M68HC11";
+}
+
+void
+cl_m68hc11::reset(void)
+{
+  cl_m68hcbase::reset();
+}
+
+int8_t *
+CL11::tick_tab(t_mem code)
+{
+  if (code == 0x18)
+    return p18ticks11;
+  else if (code == 0x1a)
+    return p1aticks11;
+  else if (code == 0xcd)
+    return pcdticks11;
+  return p0ticks11;
+}
+
+int
+CL11::tickt(t_mem code)
+{
+  int8_t *tt= tick_tab(code);
+  if ((code == 0x18) ||
+      (code == 0x1a) ||
+      (code == 0xcd))
+    code= rom->read(PC);
+  if (tt == NULL)
+    return tick(1);
+  int t= tt[code];
+  if (t)
+    return tick(t);
+  return 0;
+}
+
+
+/*
+struct dis_entry *
+cl_m68hc11::dis_tbl(void)
+{
+  return disass_m68hc11;
+}
+*/
+
+struct dis_entry *
+cl_m68hc11::get_dis_entry(t_addr addr)
+{
+  struct dis_entry *dt= dis_tbl();//, *dis_e;
+  int i= 0;
+  t_mem code= rom->get(addr);
+
+  if (code == 0x18)
+    {
+      cI= &cY;
+      i= 0;
+      code= rom->get(addr+1);
+      dt= disass11p18;
+      while (((code & dt[i].mask) != dt[i].code) &&
+	     dt[i].mnemonic)
+	i++;
+      if (dt[i].mnemonic)
+	return &dt[i];
+      return &dt[i];
+    }
+  
+  if (code == 0xcd)
+    {
+      cI= &cY;
+      i= 0;
+      code= rom->get(addr+1);
+      dt= disass11pcd;
+      while (((code & dt[i].mask) != dt[i].code) &&
+	     dt[i].mnemonic)
+	i++;
+      if (dt[i].mnemonic)
+	return &dt[i];
+      return &dt[i];
+    }
+  
+  if (code == 0x1a)
+    {
+      cI= &cX;
+      i= 0;
+      code= rom->get(addr+1);
+      dt= disass11p1a;
+      while (((code & dt[i].mask) != dt[i].code) &&
+	     dt[i].mnemonic)
+	i++;
+      if (dt[i].mnemonic)
+	return &dt[i];
+      return &dt[i];
+    }
+  
+  if (dt == NULL)
+    return NULL;
+  while (((code & dt[i].mask) != dt[i].code) &&
+	 dt[i].mnemonic)
+    i++;
+  if (dt[i].mnemonic)
+    return &dt[i];
+
+  i= 0;
+  dt= disass11p0;
+  while (((code & dt[i].mask) != dt[i].code) &&
+	 dt[i].mnemonic)
+    i++;
+  if (dt[i].mnemonic)
+    return &dt[i];
+
+  return &dt[i];
+}
+/*
+char *
+cl_m68hc11::disassc(t_addr addr, chars *comment)
+{
+  chars work= chars(), temp= chars();
+  const char *b;
+  //t_mem code= rom->get(addr);
+  struct dis_entry *dis_e;
+  int i;
+  bool first;
+  
+  if ((dis_e= get_dis_entry(addr)) == NULL)
+    return NULL;
+  if (dis_e->mnemonic == NULL)
+    return strdup("-- UNKNOWN/INVALID");
+  b= dis_e->mnemonic;
+
+  first= true;
+  work= "";
+  for (i=0; b[i]; i++)
+    {
+      if ((b[i] == ' ') && first)
+	{
+	  first= false;
+	  while (work.len() < 6) work.append(' ');
+	}
+      if (b[i] == '%')
+	{
+	  t_addr a;
+	  u8_t h, l;
+	  i++;
+	  temp= "";
+	  switch (b[i])
+	    {
+	    case 'x': case 'X': // indexed
+	      h= rom->read(addr+1);
+	      a= rX+h;
+	      work.appendf("$%02x,X", h);
+	      //add_spaces(&work, 20);
+	      if (b[i]=='x')
+		temp.appendf("; [$%04x]=$%02x", a, rom->read(a));
+	      else
+		temp.appendf("; [$%04x]=$%04x", a, read_addr(rom, a));
+	      break;
+	    case 'e': case 'E': // extended
+	      h= rom->read(addr+1);
+	      l= rom->read(addr+2);
+	      a= h*256 + l;
+	      work.appendf("$%04x", a);
+	      //add_spaces(&work, 20);
+	      if (b[i]=='e')
+		temp.appendf("; [$%04x]=$%02x", a, rom->read(a));
+	      else
+		temp.appendf("; [$%04x]=$%04x", a,
+			     read_addr(rom, a));
+	      break;
+	    case 'd': case 'D': // direct
+	      h= a= rom->read(addr+1);
+	      work.appendf("$00%02x", h);
+	      //add_spaces(&work, 20);
+	      if (b[i]=='d')
+		temp.appendf("; [$%04x]=$%02x", a, rom->read(a));
+	      else
+	        temp.appendf("; [$%04x]=$%04x", a,
+			     read_addr(rom, a));
+	      break;
+	    case 'b': // immediate 8 bit
+	      work.appendf("#$%02x",
+			   rom->read(addr+1));
+	      break;
+	    case 'B': // immediate 16 bit
+	      work.appendf("#$%04x",
+			   read_addr(rom, addr+1));
+	      break;
+	    case 'r': // relative
+	      work.appendf("$%04x",
+			   (addr+2+(i8_t)(rom->read(addr+1))) & 0xffff );
+	      break;
+	    }
+	  //work+= temp;
+	  if (comment && temp.nempty())
+	    comment->append(temp);
+	}
+      else
+	work+= b[i];
+    }
+
+  return(strdup(work.c_str()));
+}
+*/
+
+int
+CL11::PAGE18(t_mem code)
+{
+  cI= &cIY;
+  code= fetch();
+  return itab18[code](this, code);
+}
+
+int
+CL11::PAGE1A(t_mem code)
+{
+  cI= &cX;
+  code= fetch();
+  switch (code)
+    {
+    case 0x83: return cp16(cD, i16()); break;
+    case 0x93: return cp16(cD, dop16()); break;
+    case 0xa3: return cp16(cD, iop16()); break;
+    case 0xb3: return cp16(cD, eop16()); break;
+
+    case 0xad: return cp16(cY, iop16()); break;
+    case 0xee: return ldsx(cY, iop16()); break;
+    case 0xef: return stsx(iaddr(), rY); break;
+    }
+  return resINV;
+}
+
+int
+CL11::PAGECD(t_mem code)
+{
+  cI= &cY;
+  code= fetch();
+  switch (code)
+    {
+    case 0xa3: return cp16(cD, iop16()); break;
+
+    case 0xad: return cp16(cX, iop16()); break;
+    case 0xee: return ldsx(cX, iop16()); break;
+    case 0xef: return stsx(iaddr(), rX); break;
+    }
+  return resINV;
+}
+
+
+/* 
+ * OTHER instructions
+ */
+
+int
+CL11::TEST(t_mem code)
+{
+  return resGO;
+}
+
+
+int
+CL11::STOP(t_mem code)
+{
+  if (!(rF & flagN))
+    state= stIDLE;
+  return resGO;
+}
+
+
+/*
+ * MOVE instructions
+ */
+
+int
+CL11::ldd16(u16_t op)
+{
+  u8_t f= rF & ~(flagN|flagZ);
+  cD.W(op);
+  if (!op) f|= flagZ;
+  if (op & 0x8000) f|= flagN;
+  cF.W(f);
+  return resGO;
+}
+
+
+int
+CL11::std16(t_addr addr)
+{
+  u8_t f= rF & ~(flagN|flagZ);
+  rom->write(addr, rA);
+  rom->write(u16_t(addr+1), rB);
+  vc.wr+= 2;
+  if (!rD) f|= flagZ;
+  if (rD & 0x8000) f|= flagN;
+  cF.W(f);
+  return resGO;
+}
+
+
+int
+CL11::PULxy(t_mem code)
+{
+  u8_t h, l;
+  h= rom->read(++rSP);
+  l= rom->read(++rSP);
+  cSP.W(rSP);
+  cI->W(h*256+l);
+  vc.rd+= 2;
+  return resGO;
+}
+
+
+int
+CL11::PSHxy(t_mem code)
+{
+  u16_t r= cI->get();
+  rom->write(rSP--, r);
+  rom->write(rSP--, r>>8);
+  cSP.W(rSP);
+  vc.wr+= 2;
+  return resGO;
+}
+
+
+int
+CL11::XGDxy(t_mem code)
+{
+  u16_t t= rD;
+  cD.W(cI->get());
+  cI->W(t);
+  return resGO;
+}
+
+
+int
+CL11::TSY(t_mem code)
+{
+  cIY.W(rSP+1);
+  return resGO;
+}
+
+
+int
+CL11::TYS(t_mem code)
+{
+  cSP.W(rIY-1);
+  return resGO;
+}
+
+
+/*
+ * ALU instructions
+ */
+
+int
+CL11::sub16(class cl_cell16 &dest, u16_t op, bool c)
+{
+  u8_t orgc= rF&flagC;
+  u8_t f= rF & ~(flagN|flagZ|flagV|flagC);
+  u16_t a= dest.R(), b= op, r;
+  r= a-b;
+  if (c && orgc) r--;
+  if (r&0x8000) f|= flagN;
+  if (!r) f|= flagZ;
+  if (( (~a&b)|(b&r)|(r&~a) ) & 0x8000) f|= flagC;
+  if (( (a&~b&~r)|(~a&b&r) ) & 0x8000) f|= flagV;
+  dest.W(r);
+  cF.W(f);
+  return resGO;
+}
+
+
+int
+CL11::add16(class cl_cell16 &dest, u16_t op, bool c)
+{
+  u8_t orgc= rF&flagC;
+  u8_t f= rF & ~(flagN|flagZ|flagV|flagC);
+  u16_t a= dest.R(), b= op, r;
+  r= a+b;
+  if (c && orgc) r++;
+  if (r&0x8000) f|= flagN;
+  if (!r) f|= flagZ;
+  if (( (a&b)|(b&~r)|(~r&a) ) & 0x8000) f|= flagC;
+  if (( (a&b&~r)|(~a&~b&r) ) & 0x8000) f|= flagV;
+  dest.W(r);
+  cF.W(f);
+  return resGO;
+}
+
+
+int
+CL11::bset(class cl_memory_cell &dest)
+{
+  u8_t m= fetch();
+  u8_t r= dest.R();
+  u8_t f= rF & ~(flagN|flagZ);
+  r|= m;
+  dest.W(r);
+  if (!r) f|= flagZ;
+  if (r & 0x80) f|= flagN;
+  cF.W(f);
+  return resGO;
+}
+
+
+int
+CL11::bclr(class cl_memory_cell &dest)
+{
+  u8_t m= fetch();
+  u8_t r= dest.R();
+  u8_t f= rF & ~(flagN|flagZ|flagV);
+  r&= ~m;
+  dest.W(r);
+  if (!r) f|= flagZ;
+  if (r & 0x80) f|= flagN;
+  cF.W(f);
+  return resGO;
+}
+
+
+int
+CL11::cp16(class cl_cell16 &dest, u16_t op)
+{
+  u16_t a= dest.get(), b= op, r;
+  u8_t f= rF & ~(flagC|flagN|flagZ|flagV);
+  r= a-b;
+  if (r&0x8000) f|= flagN;
+  if (!r) f|= flagZ;
+  if (( (a&~b&~r)|(~a&b&r) ) & 0x8000) f|= flagV;
+  if (( (~a&b)|(b&r)|(~a&r) ) & 0x8000) f|= flagC;
+  cCC.W(f);
+  return resGO;
+}
+
+
+int
+CL11::IDIV(t_mem code)
+{
+  u16_t q, r;
+  u8_t f= rF & ~(flagZ|flagV|flagC);
+  if (rX == 0)
+    {
+      q= 0xffff;
+      r= rX;
+      f|= flagC;
+    }
+  else
+    {
+      cX.W(q= rD/rX);
+      cD.W(r= rD%rX);
+    }
+  if (!q) f|= flagZ;
+  cF.W(f);
+  return resGO;
+}
+
+
+int
+CL11::FDIV(t_mem code)
+{
+  u32_t n= rD << 16;
+  u16_t q, r;
+  u8_t f= rF & ~(flagZ|flagV|flagC);
+  if( rX <= rD) f|= flagV;
+  if (rX == 0)
+    {
+      q= 0xffff;
+      r= rX;
+      f|= flagC;
+    }
+  else
+    {
+      cX.W(q= n/rX);
+      cD.W(r= n%rX);
+    }
+  if (!q) f|= flagZ;
+  cF.W(f);
+  return resGO;
+}
+
+
+int
+CL11::LSRD(t_mem code)
+{
+  u8_t newc= rB&1;
+  u8_t f= rF & ~(flagN|flagZ|flagV|flagC);
+  cD.W(rD>>1);
+  if (!rD) f|= flagZ;
+  if (newc) f|= (flagC|flagV);
+  cF.W(f);
+  return resGO;
+}
+
+
+int
+CL11::ASLD(t_mem code)
+{
+  u8_t newc= rA&0x80;
+  u8_t f= rF & ~(flagN|flagZ|flagV|flagC);
+  cD.W(rD<<1);
+  if (!rD) f|= flagZ;
+  if (newc) f|= flagC;
+  if (rA&0x80) f|= flagN;
+  if ((f ^ (f<<3)) & flagN) f|= flagV;
+  cF.W(f);
+  return resGO;
+}
+
+
+int
+CL11::ABxy(t_mem code)
+{
+  cI->W(rX+rB);
+  return resGO;
+}
+
+
+int
+CL11::MUL(t_mem code)
+{
+  u8_t f= rF & ~flagC;
+  u16_t r= rA * rB;
+  cD.W(r);
+  if (rB & 0x80) f|= flagC;
+  cF.W(f);
+  return resGO;
+}
+
+
+int
+CL11::INY(t_mem code)
+{
+  if (++rY)
+    rF&= ~mZ;
+  else
+    rF|= mZ;
+  cY.W(rY);
+  cF.W(rF);
+  return resGO;
+}
+
+
+int
+CL11::DEY(t_mem code)
+{
+  if (--rY)
+    rF&= ~mZ;
+  else
+    rF|= mZ;
+  cY.W(rY);
+  cF.W(rF);
+  return resGO;
+}
+
+
+/*
+ * BRANCH instructions
+ */
+
+int
+CL11::brset(u8_t op)
+{
+  u8_t m= fetch();
+  i8_t r= fetch();
+  if ((~op & m) == 0)
+    branch(PC+r, true);
+  return resGO;
+}
+
+
+int
+CL11::brclr(u8_t op)
+{
+  u8_t m= fetch();
+  i8_t r= fetch();
+  if ((op & m) == 0)
+    branch(PC+r, true);
+  return resGO;
+}
+
+
+int
+CL11::BRN(t_mem code)
+{
+  fetch();
+  return resGO;
+}
+  
+
+/* End of m6800.src/m68hc11.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m68hc11.src/m68hc11cl.h sdcc-4.2.0+dfsg/sim/ucsim/m68hc11.src/m68hc11cl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/m68hc11.src/m68hc11cl.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m68hc11.src/m68hc11cl.h	2022-01-23 12:11:49.000000000 +0000
@@ -0,0 +1,163 @@
+/*
+ * Simulator of microcontrollers (m68hc11cl.h)
+ *
+ * Copyright (C) 2020,20 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef M68HC11CL_HEADER
+#define M68HC11CL_HEADER
+
+#include "uccl.h"
+#include "memcl.h"
+
+#include "m6800cl.h"
+#include "d11p0.h"
+#include "d11p18.h"
+
+
+#define rY   (IY)
+#define rIY  (IY)
+
+#define cY   (cIY)
+
+
+extern instruction_wrapper_fn itab18[256];
+extern int8_t p0ticks11[256];
+extern int8_t p18ticks11[256];
+
+class cl_m68hcbase: public cl_m6800
+{
+public:
+  u16_t IY;
+  class cl_cell16 cD;
+  class cl_idx16 cIY;
+public:
+  cl_m68hcbase(class cl_sim *asim): cl_m6800(asim) {}
+  virtual int init(void);
+public:
+  virtual int clock_per_cycle(void) { return 1; }
+  virtual void print_regs(class cl_console_base *con);
+public:
+#include "hc18.h"
+};  
+
+
+/*
+ * Base of M68HC11 processor
+ */
+#define CL11 cl_m68hc11
+
+class cl_m68hc11: public cl_m68hcbase
+{
+public:
+  cl_m68hc11(class cl_sim *asim);
+  virtual int init(void);
+  virtual const char *id_string(void);
+  virtual void reset(void);
+
+  virtual int8_t *tick_tab(t_mem code);
+  virtual int tickt(t_mem code);
+  virtual struct dis_entry *get_dis_entry(t_addr addr);
+  //virtual char *disassc(t_addr addr, chars *comment=NULL);
+  virtual int longest_inst(void) { return 6; }
+
+  // MOVE
+  virtual int ldd16(u16_t op);
+  virtual int std16(t_addr addr);
+  
+  // ALU
+  virtual int sub16(class cl_cell16 &dest, u16_t op, bool c);
+  virtual int add16(class cl_cell16 &dest, u16_t op, bool c);
+  virtual int bset(class cl_memory_cell &dest);
+  virtual int bclr(class cl_memory_cell &dest);
+  virtual int cp16(class cl_cell16 &dest, u16_t op);
+  
+  // BRANCH
+  virtual int brset(u8_t op);
+  virtual int brclr(u8_t op);
+  
+  // hc11 specific insts on Page0 
+  virtual int TEST(t_mem code);
+  virtual int IDIV(t_mem code);
+  virtual int FDIV(t_mem code);
+  virtual int LSRD(t_mem code);
+  virtual int ASLD(t_mem code);
+  virtual int BRN(t_mem code);
+  virtual int PULxy(t_mem code);
+  virtual int ABxy(t_mem code);
+  virtual int PSHxy(t_mem code);
+  virtual int MUL(t_mem code);
+  virtual int SUBD16(t_mem code) { return sub16(cD, i16(), false); }
+  virtual int SUBDd(t_mem code) { return sub16(cD, dop16(), false); }
+  virtual int SUBDxy(t_mem code) { return sub16(cD, iop16(), false); }
+  virtual int SUBDe(t_mem code) { return sub16(cD, eop16(), false); }
+  virtual int XGDxy(t_mem code);
+  virtual int JSRd(t_mem code) { return call(daddr()); }
+  virtual int ADDD16(t_mem code) { return add16(cD, i16(), false); }
+  virtual int ADDDd(t_mem code) { return add16(cD, dop16(), false); }
+  virtual int ADDDi(t_mem code) { return add16(cD, iop16(), false); }
+  virtual int ADDDe(t_mem code) { return add16(cD, eop16(), false); }
+  virtual int LDD16(t_mem code) { return ldd16(i16()); }
+  virtual int LDDd(t_mem code) { return ldd16(dop16()); }
+  virtual int LDDi(t_mem code) { return ldd16(iop16()); }
+  virtual int LDDe(t_mem code) { return ldd16(eop16()); }
+  virtual int STOP(t_mem code);
+  virtual int STDd(t_mem code) { return std16(daddr()); }
+  virtual int STDi(t_mem code) { return std16(iaddr()); }
+  virtual int STDe(t_mem code) { return std16(eaddr()); }
+  virtual int BRSETd(t_mem code) { return brset(dop()); }
+  virtual int BRSETi(t_mem code) { return brset(iop()); }
+  virtual int BRCLRd(t_mem code) { return brclr(dop()); }
+  virtual int BRCLRi(t_mem code) { return brclr(iop()); }
+  virtual int BSETd(t_mem code) { return bset(ddst()); }
+  virtual int BSETi(t_mem code) { return bset(idst()); }
+  virtual int BCLRd(t_mem code) { return bclr(ddst()); }
+  virtual int BCLRi(t_mem code) { return bclr(idst()); }
+
+  virtual int PAGE18(t_mem code);
+  virtual int PAGE1A(t_mem code);
+  virtual int PAGECD(t_mem code);
+  
+  // Page 0x18
+  virtual int INY(t_mem code);
+  virtual int DEY(t_mem code);
+  virtual int TSY(t_mem code);
+  virtual int TYS(t_mem code);
+  virtual int CPY16(t_mem code) { return cp16(cY, i16()); }
+  virtual int CPYd(t_mem code) { return cp16(cY, dop16()); }
+  virtual int CPYi(t_mem code) { return cp16(cY, iop16()); }
+  virtual int CPYe(t_mem code) { return cp16(cY, eop16()); }
+  virtual int LDY16(t_mem code) { return ldsx(cY, i16()); }
+  virtual int LDYd(t_mem code) { return ldsx(cY, dop16()); }
+  virtual int LDYi(t_mem code) { return ldsx(cY, iop16()); }
+  virtual int LDYe(t_mem code) { return ldsx(cY, eop16()); }
+  virtual int STYd(t_mem code) { return stsx(daddr(), rY); }
+  virtual int STYi(t_mem code) { return stsx(iaddr(), rY); }
+  virtual int STYe(t_mem code) { return stsx(eaddr(), rY); }
+};
+
+
+#endif
+
+/* End of m6800.src/m68hc11cl.h */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m68hc11.src/Makefile.in sdcc-4.2.0+dfsg/sim/ucsim/m68hc11.src/Makefile.in
--- sdcc-4.0.0+dfsg/sim/ucsim/m68hc11.src/Makefile.in	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m68hc11.src/Makefile.in	2022-01-23 12:11:49.000000000 +0000
@@ -0,0 +1,197 @@
+#
+# uCsim m68hc11.src/Makefile
+#
+# (c) Drotos Daniel, Talker Bt. 1997
+#
+
+# tool name
+TN		= m68hc11
+
+STARTYEAR	= 1997
+
+SHELL		= /bin/sh
+CXX		= @CXX@
+CPP		= @CPP@
+CXXCPP		= @CXXCPP@
+RANLIB		= @RANLIB@
+INSTALL		= @INSTALL@
+STRIP		= @STRIP@
+MAKEDEP         = @MAKEDEP@
+
+top_builddir	= @top_builddir@
+top_srcdir	= @top_srcdir@
+
+transform	= @program_transform_name@
+
+DEFS            = $(subs -DHAVE_CONFIG_H,,@DEFS@)
+CPPFLAGS        = @CPPFLAGS@ -I$(srcdir) -I$(top_srcdir) -I$(top_builddir) \
+		  -I$(top_srcdir)/cmd.src -I$(top_srcdir)/sim.src \
+		  -I$(top_srcdir)/gui.src -I$(top_srcdir)/motorola.src \
+		  -I$(top_srcdir)/m6800.src
+CFLAGS          = @WALL_FLAG@ @CFLAGS@
+CXXFLAGS        = @WALL_FLAG@ @CXXFLAGS@
+LDFLAGS         = @LDFLAGS@
+PICOPT		= @PICOPT@
+SHAREDLIB	= @SHAREDLIB@
+EXEEXT		= @EXEEXT@
+
+LIBS		= -L$(top_builddir) -lm6800 -lmotorola -lsim -lucsimutil -lguiucsim -lcmd -lsim @LIBS@
+DL		= @DL@
+dl_ok		= @dl_ok@
+
+prefix          = @prefix@
+exec_prefix     = @exec_prefix@
+bindir          = @bindir@
+libdir          = @libdir@
+datadir         = @datadir@
+datarootdir     = @datarootdir@
+includedir      = @includedir@
+mandir          = @mandir@
+man1dir         = $(mandir)/man1
+man2dir         = $(mandir)/man2
+infodir         = @infodir@
+srcdir          = @srcdir@
+VPATH           = @srcdir@
+
+OBJECTS_SHARED	= sim$(TN).o $(TN).o \
+		  glob11.o g11p0.o g11p18.o g11pcd.o g11p1a.o \
+		  wraps.o
+
+OBJECTS_EXE	= s$(TN).o
+OBJECTS		= $(OBJECTS_SHARED) $(OBJECTS_EXE)
+
+# short/long exe and lib name
+SEN		= s$(TN)$(EXEEXT)
+LEN		= ucsim_$(TN)$(EXEEXT)
+SONAME		= libucsim_$(TN).so
+
+enable_dlso	= @enable_dlso@
+dlso_ok		= @dlso_ok@
+
+M68HC11ASM	=
+TEST_OBJ	= 
+
+
+# Compiling entire program or any subproject
+# ------------------------------------------
+all: checkconf otherlibs $(TN).src
+
+
+# Compiling and installing everything and runing test
+# ---------------------------------------------------
+install: all installdirs install_shared_lib
+	$(INSTALL) $(SEN) $(DESTDIR)$(bindir)/$(SEN)
+	$(STRIP) $(DESTDIR)$(bindir)/$(SEN)
+	$(INSTALL) $(LEN) $(DESTDIR)$(bindir)/$(LEN)
+	$(STRIP) $(DESTDIR)$(bindir)/$(LEN)
+
+
+# Deleting all the installed files
+# --------------------------------
+uninstall:
+	rm -f $(DESTDIR)$(bindir)/$(SEN)
+	rm -f $(DESTDIR)$(bindir)/$(LEN)
+	rm -f $(DESTDIR)$(libdir)/$(SONAME)
+
+
+# Performing self-test
+# --------------------
+check: $(TEST_OBJ)
+
+.PHONY:	test baseline
+test:
+	@$(MAKE) --no-print-directory -C test
+
+baseline:
+	@$(MAKE) --no-print-directory -C test baseline
+
+
+# Performing installation test
+# ----------------------------
+installcheck:
+
+
+# Creating installation directories
+# ---------------------------------
+installdirs:
+	test -d $(DESTDIR)$(bindir) || $(INSTALL) -d $(DESTDIR)$(bindir)
+
+
+# Creating dependencies
+# ---------------------
+dep: Makefile.dep
+
+Makefile.dep: $(srcdir)/*.cc $(srcdir)/*.h
+	$(MAKEDEP) $(CPPFLAGS) $(filter %.cc,$^) >Makefile.dep
+
+-include Makefile.dep
+include $(srcdir)/clean.mk
+
+# My rules
+# --------
+.SUFFIXES: .asm .hex
+
+$(TN).src: $(SEN) $(LEN) shared_lib $(TN)lib
+
+$(SEN): $(OBJECTS) $(top_builddir)/libcmd.a $(top_builddir)/libguiucsim.a $(top_builddir)/libsim.a $(top_builddir)/libucsimutil.a $(top_builddir)/libmotorola.a $(top_builddir)/libm6800.a
+	$(CXX) $(CXXFLAGS) $(LDFLAGS) $(OBJECTS) $(LIBS) -o $@
+
+$(LEN): $(SEN)
+	cp $< $@
+
+$(TN)lib: $(top_builddir)/lib$(TN).a
+
+$(top_builddir)/lib$(TN).a: $(OBJECTS_SHARED)
+	$(AR) -rc $@ $(OBJECTS_SHARED)
+	$(RANLIB) $@
+
+ifeq ($(dlso_ok),yes)
+shared_lib: $(top_builddir)/$(SONAME)
+install_shared_lib: shared_lib
+	test -d $(DESTDIR)$(libdir) || $(INSTALL) -d $(DESTDIR)$(libdir)
+	$(INSTALL) $(top_builddir)/$(SONAME) $(DESTDIR)$(libdir)/$(SONAME)
+else
+shared_lib:
+	@$(top_srcdir)/mkecho $(top_builddir) "No $(TN) shared lib made."
+	@$(top_srcdir)/mkecho $(top_builddir) "(SHAREDLIB="$(SHAREDLIB)",dl_ok="$(dl_ok)",enable_dlso="$(enable_dlso)")"
+install_shared_lib:
+endif
+
+$(top_builddir)/$(SONAME): $(OBJECTS_SHARED)
+	$(CXX) -shared $(LDFLAGS) $(OBJECTS_SHARED) -o $@
+
+otherlibs: $(top_builddir)/libcmd.a $(top_builddir)/libguiucsim.a $(top_builddir)/libsim.a $(top_builddir)/libucsimutil.a $(top_builddir)/libmotorola.a $(top_builddir)/libm6800.a
+
+$(top_builddir)/libcmd.a:
+	$(MAKE) -C $(top_builddir)/cmd.src all
+
+$(top_builddir)/libguiucsim.a:
+	$(MAKE) -C $(top_builddir)/gui.src checkconf ucsim_lib
+
+$(top_builddir)/libsim.a:
+	$(MAKE) -C $(top_builddir)/sim.src all
+
+$(top_builddir)/libucsimutil.a:
+	$(MAKE) -C $(top_builddir) -f main.mk
+
+$(top_builddir)/libmotorola.a:
+	$(MAKE) -C $(top_builddir)/motorola.src all
+
+$(top_builddir)/libm6800.a:
+	$(MAKE) -C $(top_builddir)/m6800.src m6800lib
+
+.cc.o:
+	$(CXX) $(CXXFLAGS) $(PICOPT) $(CPPFLAGS) $(TARGET_ARCH) -c $< -o $@
+
+.asm.hex:
+	$(M68HC11ASM) -l $< -o $@ -e $<.lst
+
+
+# Remaking configuration
+# ----------------------
+checkconf:
+	@if [ -f $(top_builddir)/devel ]; then\
+	  $(MAKE) -C $(top_builddir) -f conf.mk srcdir="$(srcdir)" top_builddir="$(top_builddir)" freshconf;\
+	fi
+
+# End of m68hc11.src/Makefile.in
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m68hc11.src/simm68hc11.cc sdcc-4.2.0+dfsg/sim/ucsim/m68hc11.src/simm68hc11.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/m68hc11.src/simm68hc11.cc	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m68hc11.src/simm68hc11.cc	2022-01-23 12:11:49.000000000 +0000
@@ -0,0 +1,71 @@
+/*
+ * Simulator of microcontrollers (simm68hc11.cc)
+ *
+ * Copyright (C) 2020,20 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+// local
+#include "glob11.h"
+#include "simm68hc11cl.h"
+#include "m68hc11cl.h"
+
+
+cl_simm68hc11::cl_simm68hc11(class cl_app *the_app):
+  cl_sim(the_app)
+{}
+
+class cl_uc *
+cl_simm68hc11::mk_controller(void)
+{
+  int i;
+  const char *typ= 0;
+  class cl_optref type_option(this);
+
+  type_option.init();
+  type_option.use("cpu_type");
+  i= 0;
+  if ((typ= type_option.get_value(typ)) == 0)
+    typ= "HC11";
+  while ((cpus_hc11[i].type_str != NULL) &&
+	 (strcasecmp(typ, cpus_hc11[i].type_str) != 0))
+    i++;
+  if (cpus_hc11[i].type_str == NULL)
+    {
+      fprintf(stderr, "Unknown processor type. "
+	      "Use -H option to see known types.\n");
+      return(NULL);
+    }
+  switch (cpus_hc11[i].type)
+    {
+    case CPU_HC11:
+      return(new cl_m68hc11(this));
+    default:
+      fprintf(stderr, "Unknown processor type\n");
+      return NULL;
+    }
+  return(NULL);
+}
+
+
+/* End of m6800.src/simm68hc11.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m68hc11.src/simm68hc11cl.h sdcc-4.2.0+dfsg/sim/ucsim/m68hc11.src/simm68hc11cl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/m68hc11.src/simm68hc11cl.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m68hc11.src/simm68hc11cl.h	2022-01-23 12:11:49.000000000 +0000
@@ -0,0 +1,45 @@
+/*
+ * Simulator of microcontrollers (simm68hc11cl.h)
+ *
+ * Copyright (C) 2020,20 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef SIMM68HC11CL_HEADER
+#define SIMM68HC11CL_HEADER
+
+#include "simcl.h"
+
+
+class cl_simm68hc11: public cl_sim
+{
+public:
+  cl_simm68hc11(class cl_app *the_app);
+
+  virtual class cl_uc *mk_controller(void);
+};
+
+
+#endif
+
+/* End of m6800.src/simm68hc11cl.h */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m68hc11.src/sm68hc11.cc sdcc-4.2.0+dfsg/sim/ucsim/m68hc11.src/sm68hc11.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/m68hc11.src/sm68hc11.cc	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m68hc11.src/sm68hc11.cc	2022-01-23 12:11:49.000000000 +0000
@@ -0,0 +1,56 @@
+/*
+ * Simulator of microcontrollers (sm68hc11.cc)
+ *
+ * Copyright (C) 2020,20 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+// prj
+#include "globals.h"
+
+// local
+#include "glob11.h"
+#include "simm68hc11cl.h"
+
+
+int
+main(int argc, char *argv[])
+{
+  class cl_sim *sim;
+
+  cpus= cpus_hc11;
+  application= new cl_app();
+  application->set_name("sm68hc11");
+  application->init(argc, argv);
+  sim= new cl_simm68hc11(application);
+  if (sim->init())
+    sim->state|= SIM_QUIT;
+  application->set_simulator(sim);
+  //sim->main();
+  application->run();
+  application->done();
+  delete application;
+  return(0);
+}
+
+/* End of m6800.src/sm68hc11.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m68hc11.src/test/clean.mk sdcc-4.2.0+dfsg/sim/ucsim/m68hc11.src/test/clean.mk
--- sdcc-4.0.0+dfsg/sim/ucsim/m68hc11.src/test/clean.mk	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m68hc11.src/test/clean.mk	2022-01-23 12:11:49.000000000 +0000
@@ -0,0 +1,5 @@
+clean:
+
+distclean:
+	rm -f Makefile
+	find . -type d -name out -exec rm -rf {} \;
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m68hc11.src/test/config/baseline/M68HC11 sdcc-4.2.0+dfsg/sim/ucsim/m68hc11.src/test/config/baseline/M68HC11
--- sdcc-4.0.0+dfsg/sim/ucsim/m68hc11.src/test/config/baseline/M68HC11	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m68hc11.src/test/config/baseline/M68HC11	2022-02-08 21:21:05.000000000 +0000
@@ -0,0 +1,31 @@
+uCsim, Copyright (C)  Daniel Drotos.
+uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+This is free software, and you are welcome to redistribute it
+under certain conditions; type `show c' for details.
+Type of microcontroller: M68HC11
+Controller has 9 hardware element(s).
+   on simif[0]
+  off vcd[0]
+   on dreg[0]
+   on irq[0]
+   on uart[0]
+   on uart[1]
+   on pia[0]
+   on pia[1]
+   on dport[0]
+A= $00   0   +0 .  B= $00   0   +0 .  D= $0000     0    +0 
+CC= 00000000
+      HINZVC
+IX= 0x0000 08 70 d4 b2 8a 29 54 48 .p...)TH
+IY= 0x0000 08 70 d4 b2 8a 29 54 48 .p...)TH
+SP= 0x0000 08 70 d4 b2 8a 29 54 48 .p...)TH
+0x6c75  ? 96 4d             LDA    A,$004d            ; [$004d]=$d3[0K
+Memory chips:
+  0x000000-0x0000ff      256 variable_storage (32,%08x,0x%02lx)
+  0x000000-0x00ffff    65536 rom_chip (8,%02x,0x%04lx)
+Address spaces:
+  0x000000-0x0000ff      256 variables (32,%08x,0x%02lx)
+  0x000000-0x00ffff    65536 rom (8,%02x,0x%04lx)
+Address decoders:
+  variables 0x00 0xff -> variable_storage 0x00 activated
+  rom 0x0000 0xffff -> rom_chip 0x0000 activated
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m68hc11.src/test/config/Makefile sdcc-4.2.0+dfsg/sim/ucsim/m68hc11.src/test/config/Makefile
--- sdcc-4.0.0+dfsg/sim/ucsim/m68hc11.src/test/config/Makefile	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m68hc11.src/test/config/Makefile	2022-01-23 12:11:49.000000000 +0000
@@ -0,0 +1,8 @@
+OUTPUTS = M68HC11
+
+
+$(OUTPUTS):
+	$(call run-sim, -e 'conf; info reg; info mem')
+
+
+include test-lib.mk
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m68hc11.src/test/Makefile.in sdcc-4.2.0+dfsg/sim/ucsim/m68hc11.src/test/Makefile.in
--- sdcc-4.0.0+dfsg/sim/ucsim/m68hc11.src/test/Makefile.in	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m68hc11.src/test/Makefile.in	2022-01-23 12:11:49.000000000 +0000
@@ -0,0 +1,9 @@
+# @configure_input@
+
+srcdir           = @abs_srcdir@
+
+abs_top_builddir = @abs_top_builddir@
+abs_top_srcdir   = @abs_top_srcdir@
+
+
+include $(abs_top_srcdir)/test-target.mk
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m68hc11.src/wraps.cc sdcc-4.2.0+dfsg/sim/ucsim/m68hc11.src/wraps.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/m68hc11.src/wraps.cc	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m68hc11.src/wraps.cc	2022-01-23 12:11:49.000000000 +0000
@@ -0,0 +1,523 @@
+#include "iwrap.h"
+#include "m68hc11cl.h"
+
+int w_18_00(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_00(code); }
+int w_18_01(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_01(code); }
+int w_18_02(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_02(code); }
+int w_18_03(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_03(code); }
+int w_18_04(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_04(code); }
+int w_18_05(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_05(code); }
+int w_18_06(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_06(code); }
+int w_18_07(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_07(code); }
+int w_18_08(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_08(code); }
+int w_18_09(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_09(code); }
+int w_18_0a(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_0a(code); }
+int w_18_0b(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_0b(code); }
+int w_18_0c(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_0c(code); }
+int w_18_0d(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_0d(code); }
+int w_18_0e(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_0e(code); }
+int w_18_0f(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_0f(code); }
+int w_18_10(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_10(code); }
+int w_18_11(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_11(code); }
+int w_18_12(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_12(code); }
+int w_18_13(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_13(code); }
+int w_18_14(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_14(code); }
+int w_18_15(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_15(code); }
+int w_18_16(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_16(code); }
+int w_18_17(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_17(code); }
+int w_18_18(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_18(code); }
+int w_18_19(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_19(code); }
+int w_18_1a(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_1a(code); }
+int w_18_1b(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_1b(code); }
+int w_18_1c(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_1c(code); }
+int w_18_1d(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_1d(code); }
+int w_18_1e(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_1e(code); }
+int w_18_1f(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_1f(code); }
+int w_18_20(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_20(code); }
+int w_18_21(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_21(code); }
+int w_18_22(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_22(code); }
+int w_18_23(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_23(code); }
+int w_18_24(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_24(code); }
+int w_18_25(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_25(code); }
+int w_18_26(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_26(code); }
+int w_18_27(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_27(code); }
+int w_18_28(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_28(code); }
+int w_18_29(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_29(code); }
+int w_18_2a(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_2a(code); }
+int w_18_2b(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_2b(code); }
+int w_18_2c(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_2c(code); }
+int w_18_2d(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_2d(code); }
+int w_18_2e(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_2e(code); }
+int w_18_2f(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_2f(code); }
+int w_18_30(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_30(code); }
+int w_18_31(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_31(code); }
+int w_18_32(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_32(code); }
+int w_18_33(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_33(code); }
+int w_18_34(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_34(code); }
+int w_18_35(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_35(code); }
+int w_18_36(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_36(code); }
+int w_18_37(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_37(code); }
+int w_18_38(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_38(code); }
+int w_18_39(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_39(code); }
+int w_18_3a(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_3a(code); }
+int w_18_3b(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_3b(code); }
+int w_18_3c(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_3c(code); }
+int w_18_3d(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_3d(code); }
+int w_18_3e(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_3e(code); }
+int w_18_3f(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_3f(code); }
+int w_18_40(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_40(code); }
+int w_18_41(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_41(code); }
+int w_18_42(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_42(code); }
+int w_18_43(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_43(code); }
+int w_18_44(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_44(code); }
+int w_18_45(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_45(code); }
+int w_18_46(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_46(code); }
+int w_18_47(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_47(code); }
+int w_18_48(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_48(code); }
+int w_18_49(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_49(code); }
+int w_18_4a(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_4a(code); }
+int w_18_4b(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_4b(code); }
+int w_18_4c(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_4c(code); }
+int w_18_4d(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_4d(code); }
+int w_18_4e(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_4e(code); }
+int w_18_4f(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_4f(code); }
+int w_18_50(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_50(code); }
+int w_18_51(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_51(code); }
+int w_18_52(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_52(code); }
+int w_18_53(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_53(code); }
+int w_18_54(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_54(code); }
+int w_18_55(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_55(code); }
+int w_18_56(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_56(code); }
+int w_18_57(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_57(code); }
+int w_18_58(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_58(code); }
+int w_18_59(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_59(code); }
+int w_18_5a(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_5a(code); }
+int w_18_5b(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_5b(code); }
+int w_18_5c(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_5c(code); }
+int w_18_5d(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_5d(code); }
+int w_18_5e(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_5e(code); }
+int w_18_5f(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_5f(code); }
+int w_18_60(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_60(code); }
+int w_18_61(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_61(code); }
+int w_18_62(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_62(code); }
+int w_18_63(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_63(code); }
+int w_18_64(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_64(code); }
+int w_18_65(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_65(code); }
+int w_18_66(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_66(code); }
+int w_18_67(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_67(code); }
+int w_18_68(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_68(code); }
+int w_18_69(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_69(code); }
+int w_18_6a(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_6a(code); }
+int w_18_6b(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_6b(code); }
+int w_18_6c(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_6c(code); }
+int w_18_6d(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_6d(code); }
+int w_18_6e(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_6e(code); }
+int w_18_6f(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_6f(code); }
+int w_18_70(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_70(code); }
+int w_18_71(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_71(code); }
+int w_18_72(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_72(code); }
+int w_18_73(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_73(code); }
+int w_18_74(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_74(code); }
+int w_18_75(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_75(code); }
+int w_18_76(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_76(code); }
+int w_18_77(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_77(code); }
+int w_18_78(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_78(code); }
+int w_18_79(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_79(code); }
+int w_18_7a(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_7a(code); }
+int w_18_7b(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_7b(code); }
+int w_18_7c(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_7c(code); }
+int w_18_7d(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_7d(code); }
+int w_18_7e(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_7e(code); }
+int w_18_7f(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_7f(code); }
+int w_18_80(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_80(code); }
+int w_18_81(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_81(code); }
+int w_18_82(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_82(code); }
+int w_18_83(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_83(code); }
+int w_18_84(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_84(code); }
+int w_18_85(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_85(code); }
+int w_18_86(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_86(code); }
+int w_18_87(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_87(code); }
+int w_18_88(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_88(code); }
+int w_18_89(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_89(code); }
+int w_18_8a(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_8a(code); }
+int w_18_8b(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_8b(code); }
+int w_18_8c(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_8c(code); }
+int w_18_8d(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_8d(code); }
+int w_18_8e(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_8e(code); }
+int w_18_8f(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_8f(code); }
+int w_18_90(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_90(code); }
+int w_18_91(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_91(code); }
+int w_18_92(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_92(code); }
+int w_18_93(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_93(code); }
+int w_18_94(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_94(code); }
+int w_18_95(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_95(code); }
+int w_18_96(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_96(code); }
+int w_18_97(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_97(code); }
+int w_18_98(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_98(code); }
+int w_18_99(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_99(code); }
+int w_18_9a(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_9a(code); }
+int w_18_9b(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_9b(code); }
+int w_18_9c(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_9c(code); }
+int w_18_9d(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_9d(code); }
+int w_18_9e(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_9e(code); }
+int w_18_9f(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_9f(code); }
+int w_18_a0(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_a0(code); }
+int w_18_a1(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_a1(code); }
+int w_18_a2(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_a2(code); }
+int w_18_a3(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_a3(code); }
+int w_18_a4(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_a4(code); }
+int w_18_a5(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_a5(code); }
+int w_18_a6(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_a6(code); }
+int w_18_a7(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_a7(code); }
+int w_18_a8(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_a8(code); }
+int w_18_a9(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_a9(code); }
+int w_18_aa(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_aa(code); }
+int w_18_ab(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_ab(code); }
+int w_18_ac(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_ac(code); }
+int w_18_ad(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_ad(code); }
+int w_18_ae(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_ae(code); }
+int w_18_af(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_af(code); }
+int w_18_b0(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_b0(code); }
+int w_18_b1(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_b1(code); }
+int w_18_b2(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_b2(code); }
+int w_18_b3(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_b3(code); }
+int w_18_b4(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_b4(code); }
+int w_18_b5(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_b5(code); }
+int w_18_b6(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_b6(code); }
+int w_18_b7(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_b7(code); }
+int w_18_b8(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_b8(code); }
+int w_18_b9(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_b9(code); }
+int w_18_ba(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_ba(code); }
+int w_18_bb(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_bb(code); }
+int w_18_bc(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_bc(code); }
+int w_18_bd(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_bd(code); }
+int w_18_be(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_be(code); }
+int w_18_bf(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_bf(code); }
+int w_18_c0(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_c0(code); }
+int w_18_c1(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_c1(code); }
+int w_18_c2(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_c2(code); }
+int w_18_c3(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_c3(code); }
+int w_18_c4(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_c4(code); }
+int w_18_c5(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_c5(code); }
+int w_18_c6(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_c6(code); }
+int w_18_c7(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_c7(code); }
+int w_18_c8(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_c8(code); }
+int w_18_c9(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_c9(code); }
+int w_18_ca(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_ca(code); }
+int w_18_cb(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_cb(code); }
+int w_18_cc(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_cc(code); }
+int w_18_cd(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_cd(code); }
+int w_18_ce(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_ce(code); }
+int w_18_cf(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_cf(code); }
+int w_18_d0(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_d0(code); }
+int w_18_d1(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_d1(code); }
+int w_18_d2(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_d2(code); }
+int w_18_d3(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_d3(code); }
+int w_18_d4(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_d4(code); }
+int w_18_d5(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_d5(code); }
+int w_18_d6(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_d6(code); }
+int w_18_d7(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_d7(code); }
+int w_18_d8(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_d8(code); }
+int w_18_d9(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_d9(code); }
+int w_18_da(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_da(code); }
+int w_18_db(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_db(code); }
+int w_18_dc(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_dc(code); }
+int w_18_dd(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_dd(code); }
+int w_18_de(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_de(code); }
+int w_18_df(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_df(code); }
+int w_18_e0(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_e0(code); }
+int w_18_e1(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_e1(code); }
+int w_18_e2(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_e2(code); }
+int w_18_e3(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_e3(code); }
+int w_18_e4(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_e4(code); }
+int w_18_e5(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_e5(code); }
+int w_18_e6(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_e6(code); }
+int w_18_e7(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_e7(code); }
+int w_18_e8(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_e8(code); }
+int w_18_e9(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_e9(code); }
+int w_18_ea(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_ea(code); }
+int w_18_eb(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_eb(code); }
+int w_18_ec(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_ec(code); }
+int w_18_ed(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_ed(code); }
+int w_18_ee(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_ee(code); }
+int w_18_ef(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_ef(code); }
+int w_18_f0(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_f0(code); }
+int w_18_f1(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_f1(code); }
+int w_18_f2(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_f2(code); }
+int w_18_f3(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_f3(code); }
+int w_18_f4(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_f4(code); }
+int w_18_f5(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_f5(code); }
+int w_18_f6(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_f6(code); }
+int w_18_f7(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_f7(code); }
+int w_18_f8(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_f8(code); }
+int w_18_f9(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_f9(code); }
+int w_18_fa(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_fa(code); }
+int w_18_fb(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_fb(code); }
+int w_18_fc(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_fc(code); }
+int w_18_fd(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_fd(code); }
+int w_18_fe(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_fe(code); }
+int w_18_ff(class cl_uc *uc, t_mem code) { return ((class cl_m68hcbase *)uc)->i_18_ff(code); }
+
+void
+fill_def_18_wrappers(instruction_wrapper_fn itab[])
+{
+  itab[0x00]= w_18_00;
+  itab[0x01]= w_18_01;
+  itab[0x02]= w_18_02;
+  itab[0x03]= w_18_03;
+  itab[0x04]= w_18_04;
+  itab[0x05]= w_18_05;
+  itab[0x06]= w_18_06;
+  itab[0x07]= w_18_07;
+  itab[0x08]= w_18_08;
+  itab[0x09]= w_18_09;
+  itab[0x0a]= w_18_0a;
+  itab[0x0b]= w_18_0b;
+  itab[0x0c]= w_18_0c;
+  itab[0x0d]= w_18_0d;
+  itab[0x0e]= w_18_0e;
+  itab[0x0f]= w_18_0f;
+  itab[0x10]= w_18_10;
+  itab[0x11]= w_18_11;
+  itab[0x12]= w_18_12;
+  itab[0x13]= w_18_13;
+  itab[0x14]= w_18_14;
+  itab[0x15]= w_18_15;
+  itab[0x16]= w_18_16;
+  itab[0x17]= w_18_17;
+  itab[0x18]= w_18_18;
+  itab[0x19]= w_18_19;
+  itab[0x1a]= w_18_1a;
+  itab[0x1b]= w_18_1b;
+  itab[0x1c]= w_18_1c;
+  itab[0x1d]= w_18_1d;
+  itab[0x1e]= w_18_1e;
+  itab[0x1f]= w_18_1f;
+  itab[0x20]= w_18_20;
+  itab[0x21]= w_18_21;
+  itab[0x22]= w_18_22;
+  itab[0x23]= w_18_23;
+  itab[0x24]= w_18_24;
+  itab[0x25]= w_18_25;
+  itab[0x26]= w_18_26;
+  itab[0x27]= w_18_27;
+  itab[0x28]= w_18_28;
+  itab[0x29]= w_18_29;
+  itab[0x2a]= w_18_2a;
+  itab[0x2b]= w_18_2b;
+  itab[0x2c]= w_18_2c;
+  itab[0x2d]= w_18_2d;
+  itab[0x2e]= w_18_2e;
+  itab[0x2f]= w_18_2f;
+  itab[0x30]= w_18_30;
+  itab[0x31]= w_18_31;
+  itab[0x32]= w_18_32;
+  itab[0x33]= w_18_33;
+  itab[0x34]= w_18_34;
+  itab[0x35]= w_18_35;
+  itab[0x36]= w_18_36;
+  itab[0x37]= w_18_37;
+  itab[0x38]= w_18_38;
+  itab[0x39]= w_18_39;
+  itab[0x3a]= w_18_3a;
+  itab[0x3b]= w_18_3b;
+  itab[0x3c]= w_18_3c;
+  itab[0x3d]= w_18_3d;
+  itab[0x3e]= w_18_3e;
+  itab[0x3f]= w_18_3f;
+  itab[0x40]= w_18_40;
+  itab[0x41]= w_18_41;
+  itab[0x42]= w_18_42;
+  itab[0x43]= w_18_43;
+  itab[0x44]= w_18_44;
+  itab[0x45]= w_18_45;
+  itab[0x46]= w_18_46;
+  itab[0x47]= w_18_47;
+  itab[0x48]= w_18_48;
+  itab[0x49]= w_18_49;
+  itab[0x4a]= w_18_4a;
+  itab[0x4b]= w_18_4b;
+  itab[0x4c]= w_18_4c;
+  itab[0x4d]= w_18_4d;
+  itab[0x4e]= w_18_4e;
+  itab[0x4f]= w_18_4f;
+  itab[0x50]= w_18_50;
+  itab[0x51]= w_18_51;
+  itab[0x52]= w_18_52;
+  itab[0x53]= w_18_53;
+  itab[0x54]= w_18_54;
+  itab[0x55]= w_18_55;
+  itab[0x56]= w_18_56;
+  itab[0x57]= w_18_57;
+  itab[0x58]= w_18_58;
+  itab[0x59]= w_18_59;
+  itab[0x5a]= w_18_5a;
+  itab[0x5b]= w_18_5b;
+  itab[0x5c]= w_18_5c;
+  itab[0x5d]= w_18_5d;
+  itab[0x5e]= w_18_5e;
+  itab[0x5f]= w_18_5f;
+  itab[0x60]= w_18_60;
+  itab[0x61]= w_18_61;
+  itab[0x62]= w_18_62;
+  itab[0x63]= w_18_63;
+  itab[0x64]= w_18_64;
+  itab[0x65]= w_18_65;
+  itab[0x66]= w_18_66;
+  itab[0x67]= w_18_67;
+  itab[0x68]= w_18_68;
+  itab[0x69]= w_18_69;
+  itab[0x6a]= w_18_6a;
+  itab[0x6b]= w_18_6b;
+  itab[0x6c]= w_18_6c;
+  itab[0x6d]= w_18_6d;
+  itab[0x6e]= w_18_6e;
+  itab[0x6f]= w_18_6f;
+  itab[0x70]= w_18_70;
+  itab[0x71]= w_18_71;
+  itab[0x72]= w_18_72;
+  itab[0x73]= w_18_73;
+  itab[0x74]= w_18_74;
+  itab[0x75]= w_18_75;
+  itab[0x76]= w_18_76;
+  itab[0x77]= w_18_77;
+  itab[0x78]= w_18_78;
+  itab[0x79]= w_18_79;
+  itab[0x7a]= w_18_7a;
+  itab[0x7b]= w_18_7b;
+  itab[0x7c]= w_18_7c;
+  itab[0x7d]= w_18_7d;
+  itab[0x7e]= w_18_7e;
+  itab[0x7f]= w_18_7f;
+  itab[0x80]= w_18_80;
+  itab[0x81]= w_18_81;
+  itab[0x82]= w_18_82;
+  itab[0x83]= w_18_83;
+  itab[0x84]= w_18_84;
+  itab[0x85]= w_18_85;
+  itab[0x86]= w_18_86;
+  itab[0x87]= w_18_87;
+  itab[0x88]= w_18_88;
+  itab[0x89]= w_18_89;
+  itab[0x8a]= w_18_8a;
+  itab[0x8b]= w_18_8b;
+  itab[0x8c]= w_18_8c;
+  itab[0x8d]= w_18_8d;
+  itab[0x8e]= w_18_8e;
+  itab[0x8f]= w_18_8f;
+  itab[0x90]= w_18_90;
+  itab[0x91]= w_18_91;
+  itab[0x92]= w_18_92;
+  itab[0x93]= w_18_93;
+  itab[0x94]= w_18_94;
+  itab[0x95]= w_18_95;
+  itab[0x96]= w_18_96;
+  itab[0x97]= w_18_97;
+  itab[0x98]= w_18_98;
+  itab[0x99]= w_18_99;
+  itab[0x9a]= w_18_9a;
+  itab[0x9b]= w_18_9b;
+  itab[0x9c]= w_18_9c;
+  itab[0x9d]= w_18_9d;
+  itab[0x9e]= w_18_9e;
+  itab[0x9f]= w_18_9f;
+  itab[0xa0]= w_18_a0;
+  itab[0xa1]= w_18_a1;
+  itab[0xa2]= w_18_a2;
+  itab[0xa3]= w_18_a3;
+  itab[0xa4]= w_18_a4;
+  itab[0xa5]= w_18_a5;
+  itab[0xa6]= w_18_a6;
+  itab[0xa7]= w_18_a7;
+  itab[0xa8]= w_18_a8;
+  itab[0xa9]= w_18_a9;
+  itab[0xaa]= w_18_aa;
+  itab[0xab]= w_18_ab;
+  itab[0xac]= w_18_ac;
+  itab[0xad]= w_18_ad;
+  itab[0xae]= w_18_ae;
+  itab[0xaf]= w_18_af;
+  itab[0xb0]= w_18_b0;
+  itab[0xb1]= w_18_b1;
+  itab[0xb2]= w_18_b2;
+  itab[0xb3]= w_18_b3;
+  itab[0xb4]= w_18_b4;
+  itab[0xb5]= w_18_b5;
+  itab[0xb6]= w_18_b6;
+  itab[0xb7]= w_18_b7;
+  itab[0xb8]= w_18_b8;
+  itab[0xb9]= w_18_b9;
+  itab[0xba]= w_18_ba;
+  itab[0xbb]= w_18_bb;
+  itab[0xbc]= w_18_bc;
+  itab[0xbd]= w_18_bd;
+  itab[0xbe]= w_18_be;
+  itab[0xbf]= w_18_bf;
+  itab[0xc0]= w_18_c0;
+  itab[0xc1]= w_18_c1;
+  itab[0xc2]= w_18_c2;
+  itab[0xc3]= w_18_c3;
+  itab[0xc4]= w_18_c4;
+  itab[0xc5]= w_18_c5;
+  itab[0xc6]= w_18_c6;
+  itab[0xc7]= w_18_c7;
+  itab[0xc8]= w_18_c8;
+  itab[0xc9]= w_18_c9;
+  itab[0xca]= w_18_ca;
+  itab[0xcb]= w_18_cb;
+  itab[0xcc]= w_18_cc;
+  itab[0xcd]= w_18_cd;
+  itab[0xce]= w_18_ce;
+  itab[0xcf]= w_18_cf;
+  itab[0xd0]= w_18_d0;
+  itab[0xd1]= w_18_d1;
+  itab[0xd2]= w_18_d2;
+  itab[0xd3]= w_18_d3;
+  itab[0xd4]= w_18_d4;
+  itab[0xd5]= w_18_d5;
+  itab[0xd6]= w_18_d6;
+  itab[0xd7]= w_18_d7;
+  itab[0xd8]= w_18_d8;
+  itab[0xd9]= w_18_d9;
+  itab[0xda]= w_18_da;
+  itab[0xdb]= w_18_db;
+  itab[0xdc]= w_18_dc;
+  itab[0xdd]= w_18_dd;
+  itab[0xde]= w_18_de;
+  itab[0xdf]= w_18_df;
+  itab[0xe0]= w_18_e0;
+  itab[0xe1]= w_18_e1;
+  itab[0xe2]= w_18_e2;
+  itab[0xe3]= w_18_e3;
+  itab[0xe4]= w_18_e4;
+  itab[0xe5]= w_18_e5;
+  itab[0xe6]= w_18_e6;
+  itab[0xe7]= w_18_e7;
+  itab[0xe8]= w_18_e8;
+  itab[0xe9]= w_18_e9;
+  itab[0xea]= w_18_ea;
+  itab[0xeb]= w_18_eb;
+  itab[0xec]= w_18_ec;
+  itab[0xed]= w_18_ed;
+  itab[0xee]= w_18_ee;
+  itab[0xef]= w_18_ef;
+  itab[0xf0]= w_18_f0;
+  itab[0xf1]= w_18_f1;
+  itab[0xf2]= w_18_f2;
+  itab[0xf3]= w_18_f3;
+  itab[0xf4]= w_18_f4;
+  itab[0xf5]= w_18_f5;
+  itab[0xf6]= w_18_f6;
+  itab[0xf7]= w_18_f7;
+  itab[0xf8]= w_18_f8;
+  itab[0xf9]= w_18_f9;
+  itab[0xfa]= w_18_fa;
+  itab[0xfb]= w_18_fb;
+  itab[0xfc]= w_18_fc;
+  itab[0xfd]= w_18_fd;
+  itab[0xfe]= w_18_fe;
+  itab[0xff]= w_18_ff;
+
+}
+
+/* End of m68hc12.src/wraps.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m68hc11.src/wraps.h sdcc-4.2.0+dfsg/sim/ucsim/m68hc11.src/wraps.h
--- sdcc-4.0.0+dfsg/sim/ucsim/m68hc11.src/wraps.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m68hc11.src/wraps.h	2022-01-23 12:11:49.000000000 +0000
@@ -0,0 +1,11 @@
+#ifndef WRAPS_HEADER
+#define WRAPS_HEADER
+
+#include "uccl.h"
+
+extern void fill_def_18_wrappers(instruction_wrapper_fn itab[]);
+
+
+#endif
+
+/* End of m68hc12.src/wraps.h */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m68hc12.src/(c).1 sdcc-4.2.0+dfsg/sim/ucsim/m68hc12.src/(c).1
--- sdcc-4.0.0+dfsg/sim/ucsim/m68hc12.src/(c).1	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m68hc12.src/(c).1	2021-06-10 09:43:56.000000000 +0000
@@ -0,0 +1,25 @@
+/*
+ * Simulator of microcontrollers (@@F@@)
+ *
+ * Copyright (C) @@S@@,@@Y@@ Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m68hc12.src/clean.mk sdcc-4.2.0+dfsg/sim/ucsim/m68hc12.src/clean.mk
--- sdcc-4.0.0+dfsg/sim/ucsim/m68hc12.src/clean.mk	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m68hc12.src/clean.mk	2021-06-10 09:43:56.000000000 +0000
@@ -0,0 +1,32 @@
+# m68hc12.src/clean.mk
+
+# Deleting all files created by building the program
+# --------------------------------------------------
+clean:
+	rm -f *core *[%~] *.[oa] *.map
+	rm -f .[a-z]*~
+	rm -f sm68hc12$(EXEEXT) sm68hc12.exe
+	rm -f ucsim_m68hc12$(EXEEXT) ucsim_m68hc12.exe
+	$(MAKE) -C test -f clean.mk clean
+
+
+# Deleting all files created by configuring or building the program
+# -----------------------------------------------------------------
+distclean: clean
+	rm -f config.cache config.log config.status
+	rm -f Makefile *.dep
+	rm -f *.obj *.list *.lst *.hex
+	$(MAKE) -C test -f clean.mk distclean
+
+
+# Like clean but some files may still exist
+# -----------------------------------------
+mostlyclean: clean
+
+
+# Deleting everything that can reconstructed by this Makefile. It deletes
+# everything deleted by distclean plus files created by bison, etc.
+# -----------------------------------------------------------------------
+realclean: distclean
+
+# End of m68hc12.src/clean.mk
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m68hc12.src/conf.mk sdcc-4.2.0+dfsg/sim/ucsim/m68hc12.src/conf.mk
--- sdcc-4.0.0+dfsg/sim/ucsim/m68hc12.src/conf.mk	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m68hc12.src/conf.mk	2021-06-10 09:43:56.000000000 +0000
@@ -0,0 +1,11 @@
+# m68hc12.src/conf.mk
+#
+# Makefile targets to remake configuration
+#
+
+freshconf: Makefile
+
+Makefile: $(srcdir)/Makefile.in $(top_srcdir)/configure.ac
+	cd $(top_builddir) && $(SHELL) ./config.status
+
+# End of m68hc12.src/conf.mk
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m68hc12.src/decode.h sdcc-4.2.0+dfsg/sim/ucsim/m68hc12.src/decode.h
--- sdcc-4.0.0+dfsg/sim/ucsim/m68hc12.src/decode.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m68hc12.src/decode.h	2022-02-08 09:07:34.000000000 +0000
@@ -0,0 +1,288 @@
+#include "gen.h"
+
+DEC(0, 89,	adc	, _A_i8  	, "ADCA %b"	, ' ', 2	, 1)
+DEC(0, 99,	adc	, _A_dop	, "ADCA %d"	, ' ', 2	, 3)
+DEC(0, a9,	adc	, _A_xbop8	, "ADCA %p"	, ' ', -2	, 0x66433)
+DEC(0, b9,	adc	, _A_eop 	, "ADCA %e"	, ' ', 3	, 3)
+
+DEC(0, c9,	adc	, _B_i8  	, "ADCB %b"	, ' ', 2	, 1)
+DEC(0, d9,	adc	, _B_dop	, "ADCB %d"	, ' ', 2	, 3)
+DEC(0, e9,	adc	, _B_xbop8	, "ADCB %p"	, ' ', -2	, 0x66433)
+DEC(0, f9,	adc	, _B_eop 	, "ADCB %e"	, ' ', 3	, 3)
+
+DEC(0, 8b,	add	, _A_i8  	, "ADDA %b"	, ' ', 2	, 1)
+DEC(0, 9b,	add	, _A_dop	, "ADDA %d"	, ' ', 2	, 3)
+DEC(0, ab,	add	, _A_xbop8	, "ADDA %p"	, ' ', -2	, 0x66433)
+DEC(0, bb,	add	, _A_eop 	, "ADDA %e"	, ' ', 3	, 3)
+
+DEC(0, cb,	add	, _B_i8  	, "ADDB %b"	, ' ', 2	, 1)
+DEC(0, db,	add	, _B_dop	, "ADDB %d"	, ' ', 2	, 3)
+DEC(0, eb,	add	, _B_xbop8	, "ADDB %p"	, ' ', -2	, 0x66433)
+DEC(0, fb,	add	, _B_eop 	, "ADDB %e"	, ' ', 3	, 3)
+
+DEC(0, 84,	And	, _A_i8  	, "ANDA %b"	, ' ', 2	, 1)
+DEC(0, 94,	And	, _A_dop	, "ANDA %d"	, ' ', 2	, 3)
+DEC(0, a4,	And	, _A_xbop8	, "ANDA %p"	, ' ', -2	, 0x66433)
+DEC(0, b4,	And	, _A_eop 	, "ANDA %e"	, ' ', 3	, 3)
+
+DEC(0, c4,	And	, _B_i8  	, "ANDB %b"	, ' ', 2	, 1)
+DEC(0, d4,	And	, _B_dop	, "ANDB %d"	, ' ', 2	, 3)
+DEC(0, e4,	And	, _B_xbop8	, "ANDB %p"	, ' ', -2	, 0x66433)
+DEC(0, f4,	And	, _B_eop 	, "ANDB %e"	, ' ', 3	, 3)
+
+DEC(0, 88,	eor	, _A_i8  	, "EORA %b"	, ' ', 2	, 1)
+DEC(0, 98,	eor	, _A_dop	, "EORA %d"	, ' ', 2	, 3)
+DEC(0, a8,	eor	, _A_xbop8	, "EORA %p"	, ' ', -2	, 0x66433)
+DEC(0, b8,	eor	, _A_eop 	, "EORA %e"	, ' ', 3	, 3)
+
+DEC(0, c8,	eor	, _B_i8  	, "EORB %b"	, ' ', 2	, 1)
+DEC(0, d8,	eor	, _B_dop	, "EORB %d"	, ' ', 2	, 3)
+DEC(0, e8,	eor	, _B_xbop8	, "EORB %p"	, ' ', -2	, 0x66433)
+DEC(0, f8,	eor 	, _B_eop 	, "EORB %e"	, ' ', 3	, 3)
+
+DEC(0, 8a,	Or	, _A_i8  	, "ORAA %b"	, ' ', 2	, 1)
+DEC(0, 9a,	Or	, _A_dop	, "ORAA %d"	, ' ', 2	, 3)
+DEC(0, aa,	Or	, _A_xbop8	, "ORAA %p"	, ' ', -2	, 0x66433)
+DEC(0, ba,	Or	, _A_eop 	, "ORAA %e"	, ' ', 3	, 3)
+
+DEC(0, ca,	Or	, _B_i8  	, "ORAB %b"	, ' ', 2	, 1)
+DEC(0, da,	Or	, _B_dop	, "ORAB %d"	, ' ', 2	, 3)
+DEC(0, ea,	Or	, _B_xbop8	, "ORAB %p"	, ' ', -2	, 0x66433)
+DEC(0, fa,	Or 	, _B_eop 	, "ORAB %e"	, ' ', 3	, 3)
+
+DEC(0, 85,	bit	, _Aop_i8  	, "BITA %b"	, ' ', 2	, 1)
+DEC(0, 95,	bit	, _Aop_dop	, "BITA %d"	, ' ', 2	, 3)
+DEC(0, a5,	bit	, _Aop_xbop8	, "BITA %p"	, ' ', -2	, 0x66433)
+DEC(0, b5,	bit	, _Aop_eop 	, "BITA %e"	, ' ', 3	, 3)
+
+DEC(0, c5,	bit	, _Bop_i8  	, "BITB %b"	, ' ', 2	, 1)
+DEC(0, d5,	bit	, _Bop_dop	, "BITB %d"	, ' ', 2	, 3)
+DEC(0, e5,	bit	, _Bop_xbop8	, "BITB %p"	, ' ', -2	, 0x66433)
+DEC(0, f5,	bit 	, _Bop_eop 	, "BITB %e"	, ' ', 3	, 3)
+
+DEC(0, 81,	cmp	, _Aop_i8  	, "CMPA %b"	, ' ', 2	, 1)
+DEC(0, 91,	cmp	, _Aop_dop	, "CMPA %d"	, ' ', 2	, 3)
+DEC(0, a1,	cmp	, _Aop_xbop8	, "CMPA %p"	, ' ', -2	, 0x66433)
+DEC(0, b1,	cmp	, _Aop_eop 	, "CMPA %e"	, ' ', 3	, 3)
+
+DEC(0, c1,	cmp	, _Bop_i8  	, "CMPB %b"	, ' ', 2	, 1)
+DEC(0, d1,	cmp	, _Bop_dop	, "CMPB %d"	, ' ', 2	, 3)
+DEC(0, e1,	cmp	, _Bop_xbop8	, "CMPB %p"	, ' ', -2	, 0x66433)
+DEC(0, f1,	cmp 	, _Bop_eop 	, "CMPB %e"	, ' ', 3	, 3)
+
+DEC(0, 80,	sub	, _A_i8  	, "SUBA %b"	, ' ', 2	, 1)
+DEC(0, 90,	sub	, _A_dop	, "SUBA %d"	, ' ', 2	, 3)
+DEC(0, a0,	sub	, _A_xbop8	, "SUBA %p"	, ' ', -2	, 0x66433)
+DEC(0, b0,	sub	, _A_eop 	, "SUBA %e"	, ' ', 3	, 3)
+
+DEC(0, c0,	sub	, _B_i8  	, "SUBB %b"	, ' ', 2	, 1)
+DEC(0, d0,	sub	, _B_dop	, "SUBB %d"	, ' ', 2	, 3)
+DEC(0, e0,	sub	, _B_xbop8	, "SUBB %p"	, ' ', -2	, 0x66433)
+DEC(0, f0,	sub	, _B_eop 	, "SUBB %e"	, ' ', 3	, 3)
+
+DEC(0, 82,	sbc	, _A_i8  	, "SBCA %b"	, ' ', 2	, 1)
+DEC(0, 92,	sbc	, _A_dop	, "SBCA %d"	, ' ', 2	, 3)
+DEC(0, a2,	sbc	, _A_xbop8	, "SBCA %p"	, ' ', -2	, 0x66433)
+DEC(0, b2,	sbc	, _A_eop 	, "SBCA %e"	, ' ', 3	, 3)
+
+DEC(0, c2,	sbc	, _B_i8  	, "SBCB %b"	, ' ', 2	, 1)
+DEC(0, d2,	sbc	, _B_dop	, "SBCB %d"	, ' ', 2	, 3)
+DEC(0, e2,	sbc	, _B_xbop8	, "SBCB %p"	, ' ', -2	, 0x66433)
+DEC(0, f2,	sbc	, _B_eop 	, "SBCB %e"	, ' ', 3	, 3)
+
+DEC(0, 86,	lda	, _A_i8  	, "LDAA %b"	, ' ', 2	, 1)
+DEC(0, 96,	lda	, _A_dop	, "LDAA %d"	, ' ', 2	, 3)
+DEC(0, a6,	lda	, _A_xbop8	, "LDAA %p"	, ' ', -2	, 0x66433)
+DEC(0, b6,	lda	, _A_eop 	, "LDAA %e"	, ' ', 3	, 3)
+
+DEC(0, c6,	lda	, _B_i8  	, "LDAB %b"	, ' ', 2	, 1)
+DEC(0, d6,	lda	, _B_dop	, "LDAB %d"	, ' ', 2	, 3)
+DEC(0, e6,	lda	, _B_xbop8	, "LDAB %p"	, ' ', -2	, 0x66433)
+DEC(0, f6,	lda	, _B_eop 	, "LDAB %e"	, ' ', 3	, 3)
+
+DEC(0, 83,	sub16	, _D_i16  	, "SUBD %B"	, ' ', 3	, 2)
+DEC(0, 93,	sub16	, _D_dop16	, "SUBD %D"	, ' ', 2	, 3)
+DEC(0, a3,	sub16	, _D_xbop16	, "SUBD %p"	, ' ', -2	, 0x66433)
+DEC(0, b3,	sub16	, _D_eop16 	, "SUBD %E"	, ' ', 3	, 3)
+
+DEC(0, 8c,	cp16	, _Dop_i16  	, "CPD %B"	, ' ', 3	, 2)
+DEC(0, 9c,	cp16	, _Dop_dop16	, "CPD %D"	, ' ', 2	, 3)
+DEC(0, ac,	cp16	, _Dop_xbop16	, "CPD %p"	, ' ', -2	, 0x66433)
+DEC(0, bc,	cp16	, _Dop_eop16 	, "CPD %E"	, ' ', 3	, 3)
+
+DEC(0, 8d,	cp16	, _Yop_i16  	, "CPY %B"	, ' ', 3	, 2)
+DEC(0, 9d,	cp16	, _Yop_dop16	, "CPY %D"	, ' ', 2	, 3)
+DEC(0, ad,	cp16	, _Yop_xbop16	, "CPY %p"	, ' ', -2	, 0x66433)
+DEC(0, bd,	cp16	, _Yop_eop16 	, "CPY %E"	, ' ', 3	, 3)
+
+DEC(0, 8e,	cp16	, _Xop_i16  	, "CPX %B"	, ' ', 3	, 2)
+DEC(0, 9e,	cp16	, _Xop_dop16	, "CPX %D"	, ' ', 2	, 3)
+DEC(0, ae,	cp16	, _Xop_xbop16	, "CPX %p"	, ' ', -2	, 0x66433)
+DEC(0, be,	cp16	, _Xop_eop16 	, "CPX %E"	, ' ', 3	, 3)
+
+DEC(0, 8f,	cp16	, _Sop_i16  	, "CPS %B"	, ' ', 3	, 2)
+DEC(0, 9f,	cp16	, _Sop_dop16	, "CPS %D"	, ' ', 2	, 3)
+DEC(0, af,	cp16	, _Sop_xbop16	, "CPS %p"	, ' ', -2	, 0x66433)
+DEC(0, bf,	cp16	, _Sop_eop16 	, "CPS %E"	, ' ', 3	, 3)
+
+DEC(0, c3,	add16	, _D_i16  	, "ADDD %B"	, ' ', 3	, 2)
+DEC(0, d3,	add16	, _D_dop16	, "ADDD %D"	, ' ', 2	, 3)
+DEC(0, e3,	add16	, _D_xbop16	, "ADDD %p"	, ' ', -2	, 0x66433)
+DEC(0, f3,	add16	, _D_eop16 	, "ADDD %E"	, ' ', 3	, 3)
+
+DEC(0, cc,	ld16	, _D_i16  	, "LDD %B"	, ' ', 3	, 2)
+DEC(0, dc,	ld16	, _D_dop16	, "LDD %D"	, ' ', 2	, 3)
+DEC(0, ec,	ld16	, _D_xbop16	, "LDD %p"	, ' ', -2	, 0x66433)
+DEC(0, fc,	ld16	, _D_eop16 	, "LDD %E"	, ' ', 3	, 3)
+
+DEC(0, ce,	ld16	, _X_i16  	, "LDX %B"	, ' ', 3	, 2)
+DEC(0, de,	ld16	, _X_dop16	, "LDX %D"	, ' ', 2	, 3)
+DEC(0, ee,	ld16	, _X_xbop16	, "LDX %p"	, ' ', -2	, 0x66433)
+DEC(0, fe,	ld16	, _X_eop16 	, "LDX %E"	, ' ', 3	, 3)
+
+DEC(0, cd,	ld16	, _Y_i16  	, "LDY %B"	, ' ', 3	, 2)
+DEC(0, dd,	ld16	, _Y_dop16	, "LDY %D"	, ' ', 2	, 3)
+DEC(0, ed,	ld16	, _Y_xbop16	, "LDY %p"	, ' ', -2	, 0x66433)
+DEC(0, fd,	ld16	, _Y_eop16 	, "LDY %E"	, ' ', 3	, 3)
+
+DEC(0, cf,	ld16	, _S_i16  	, "LDS %B"	, ' ', 3	, 2)
+DEC(0, df,	ld16	, _S_dop16	, "LDS %D"	, ' ', 2	, 3)
+DEC(0, ef,	ld16	, _S_xbop16	, "LDS %p"	, ' ', -2	, 0x66433)
+DEC(0, ff,	ld16	, _S_eop16 	, "LDS %E"	, ' ', 3	, 3)
+
+DEC(0, 87,	clr	, _cA	 	, "CLRA"	, ' ', 1	, 1)
+DEC(0, c7,	clr	, _cB	 	, "CLRB"	, ' ', 1	, 1)
+DEC(0, 69,	clr	, _xb	 	, "CLR %p"	, ' ', -2	, 0x55322)
+DEC(0, 79,	clr	, _e	 	, "CLR %e"	, ' ', 3	, 3)
+
+DEC(0, 97,	tst	, _Aop	 	, "TSTA"	, ' ', 1	, 1)
+DEC(0, d7,	tst	, _Bop	 	, "TSTB"	, ' ', 1	, 1)
+DEC(0, e7,	tst	, _xbop8 	, "TST %p"	, ' ', -2	, 0x55322)
+DEC(0, f7,	tst	, _eop	 	, "TST %e"	, ' ', 3	, 3)
+
+DEC(0, 40,	neg	, _cA	 	, "NEGA"	, ' ', 1	, 1)
+DEC(0, 50,	neg	, _cB	 	, "NEGB"	, ' ', 1	, 1)
+DEC(0, 60,	neg	, _xb	 	, "NEG %p"	, ' ', -2	, 0x66433)
+DEC(0, 70,	neg	, _e	 	, "NEG %e"	, ' ', 3	, 3)
+
+DEC(0, 41,	com	, _cA	 	, "COMA"	, ' ', 1	, 1)
+DEC(0, 51,	com	, _cB	 	, "COMB"	, ' ', 1	, 1)
+DEC(0, 61,	com	, _xb	 	, "COM %p"	, ' ', -2	, 0x66433)
+DEC(0, 71,	com	, _e	 	, "COM %e"	, ' ', 3	, 3)
+
+DEC(0, 42,	inc	, _cA	 	, "INCA"	, ' ', 1	, 1)
+DEC(0, 52,	inc	, _cB	 	, "INCB"	, ' ', 1	, 1)
+DEC(0, 62,	inc	, _xb	 	, "INC %p"	, ' ', -2	, 0x66433)
+DEC(0, 72,	inc	, _e	 	, "INC %e"	, ' ', 3	, 3)
+
+DEC(0, 43,	dec	, _cA	 	, "DECA"	, ' ', 1	, 1)
+DEC(0, 53,	dec	, _cB	 	, "DECB"	, ' ', 1	, 1)
+DEC(0, 63,	dec	, _xb	 	, "DEC %p"	, ' ', -2	, 0x66433)
+DEC(0, 73,	dec	, _e	 	, "DEC %e"	, ' ', 3	, 3)
+
+DEC(0, 44,	lsr	, _cA	 	, "LSRA"	, ' ', 1	, 1)
+DEC(0, 54,	lsr	, _cB	 	, "LSRB"	, ' ', 1	, 1)
+DEC(0, 64,	lsr	, _xb	 	, "LSR %p"	, ' ', -2	, 0x66433)
+DEC(0, 74,	lsr	, _e	 	, "LSR %e"	, ' ', 3	, 3)
+
+DEC(0, 45,	rol	, _cA	 	, "ROLA"	, ' ', 1	, 1)
+DEC(0, 55,	rol	, _cB	 	, "ROLB"	, ' ', 1	, 1)
+DEC(0, 65,	rol	, _xb	 	, "ROL %p"	, ' ', -2	, 0x66433)
+DEC(0, 75,	rol	, _e	 	, "ROL %e"	, ' ', 3	, 3)
+
+DEC(0, 46,	ror	, _cA	 	, "RORA"	, ' ', 1	, 1)
+DEC(0, 56,	ror	, _cB	 	, "RORB"	, ' ', 1	, 1)
+DEC(0, 66,	ror	, _xb	 	, "ROR %p"	, ' ', -2	, 0x66433)
+DEC(0, 76,	ror	, _e	 	, "ROR %e"	, ' ', 3	, 3)
+
+DEC(0, 47,	asr	, _cA	 	, "ASRA"	, ' ', 1	, 1)
+DEC(0, 57,	asr	, _cB	 	, "ASRB"	, ' ', 1	, 1)
+DEC(0, 67,	asr	, _xb	 	, "ASR %p"	, ' ', -2	, 0x66433)
+DEC(0, 77,	asr	, _e	 	, "ASR %e"	, ' ', 3	, 3)
+
+DEC(0, 48,	asl	, _cA	 	, "ASLA"	, ' ', 1	, 1)
+DEC(0, 58,	asl	, _cB	 	, "ASLB"	, ' ', 1	, 1)
+DEC(0, 68,	asl	, _xb	 	, "ASL %p"	, ' ', -2	, 0x66433)
+DEC(0, 78,	asl	, _e	 	, "ASL %e"	, ' ', 3	, 3)
+
+DEC(0, 49,	lsr16	, _cD		, "LSRD"	, ' ', 1	, 1)
+DEC(0, 59,	asl16	, _cD		, "LSLD"	, ' ', 1	, 1)
+
+DEC(0, 4a,	call_e	, _NONE		, "CALL $ep$"	, ' ', 4	, 7)
+DEC(0, 4b,	call_id	, _NONE		, "CALL $ip$"	, ' ', -2	, 0xaa988)
+
+DEC(0, 5a,	sta	, _d_Aop 	, "STAA %d"	, ' ', 2	, 2)
+DEC(0, 6a,	sta	, _xb_Aop	, "STAA %p"	, ' ', -2	, 0x55332)
+DEC(0, 7a,	sta	, _e_Aop 	, "STAA %e"	, ' ', 3	, 3)
+
+DEC(0, 5b,	sta	, _d_Bop 	, "STAB %d"	, ' ', 2	, 2)
+DEC(0, 6b,	sta	, _xb_Bop	, "STAB %p"	, ' ', -2	, 0x55332)
+DEC(0, 7b,	sta	, _e_Bop 	, "STAB %e"	, ' ', 3	, 3)
+
+DEC(0, 5c,	stsx	, _da_Dop 	, "STD %d"	, ' ', 2	, 2)
+DEC(0, 6c,	stsx	, _xba_Dop	, "STD %p"	, ' ', -2	, 0x55332)
+DEC(0, 7c,	stsx	, _ea_Dop 	, "STD %e"	, ' ', 3	, 3)
+
+DEC(0, 5e,	stsx	, _da_Xop 	, "STX %d"	, ' ', 2	, 2)
+DEC(0, 6e,	stsx	, _xba_Xop	, "STX %p"	, ' ', -2	, 0x55332)
+DEC(0, 7e,	stsx	, _ea_Xop 	, "STX %e"	, ' ', 3	, 3)
+
+DEC(0, 5d,	stsx	, _da_Yop 	, "STY %d"	, ' ', 2	, 2)
+DEC(0, 6d,	stsx	, _xba_Yop	, "STY %p"	, ' ', -2	, 0x55332)
+DEC(0, 7d,	stsx	, _ea_Yop 	, "STY %e"	, ' ', 3	, 3)
+
+DEC(0, 5f,	stsx	, _da_Sop 	, "STS %d"	, ' ', 2	, 2)
+DEC(0, 6f,	stsx	, _xba_Sop	, "STS %p"	, ' ', -2	, 0x55332)
+DEC(0, 7f,	stsx	, _ea_Sop 	, "STS %e"	, ' ', 3	, 3)
+
+DEC(0, 4c,	Or	, _d_i8		, "BSET %d,%b"	, ' ', 3	, 4)
+DEC(0, 0c,	Or	, _xb_i8	, "BSET %p,%b"	, ' ', -4	, 4)
+DEC(0, 1c,	Or	, _e_i8		, "BSET %e,%b"	, ' ', 4	, 4)
+
+DEC(0, 4d,	And	, _d_i8n	, "BCLR %d,%b"	, ' ', 3	, 4)
+DEC(0, 0d,	And	, _xb_i8n	, "BCLR %p,%b"	, ' ', -4	, 4)
+DEC(0, 1d,	And	, _e_i8n	, "BCLR %e,%b"	, ' ', 4	, 4)
+
+DEC(0, 4e,	brset_d	, _NONE		, "BRSET %d,%b,%r", ' ', 4	, 5)
+DEC(0, 0e,	brset_id, _NONE		, "BRSET %p,%b,%r", ' ', -4	, 5)
+DEC(0, 1e,	brset_e	, _NONE		, "BRSET %e,%b,%r", ' ', 5	, 5)
+
+DEC(0, 4f,	brclr_d	, _NONE		, "BRCLR %d,%b,%r", ' ', 4	, 5)
+DEC(0, 0f,	brclr_id, _NONE		, "BRCLR %p,%b,%r", ' ', -4	, 5)
+DEC(0, 1f,	brclr_e	, _NONE		, "BRCLR %e,%b,%r", ' ', 5	, 5)
+
+DEC(0, 20,	BRA	, 0x20		, "BRA %r"	, ' ', 2	, 1)
+DEC(0, 21,	BRN	, 0x21		, "BRN %r"	, ' ', 2	, 1)
+DEC(0, 22,	BHI	, 0x22		, "BHI %r"	, ' ', 2	, 1)
+DEC(0, 23,	BLS	, 0x23		, "BLS %r"	, ' ', 2	, 1)
+DEC(0, 24,	BCC	, 0x24		, "BCC %r"	, ' ', 2	, 1)
+DEC(0, 25,	BCS	, 0x25		, "BCS %r"	, ' ', 2	, 1)
+DEC(0, 26,	BNE	, 0x26		, "BNE %r"	, ' ', 2	, 1)
+DEC(0, 27,	BEQ	, 0x27		, "BEQ %r"	, ' ', 2	, 1)
+DEC(0, 28,	BVC	, 0x28		, "BVC %r"	, ' ', 2	, 1)
+DEC(0, 29,	BVS	, 0x29		, "BVS %r"	, ' ', 2	, 1)
+DEC(0, 2a,	BPL	, 0x2a		, "BPL %r"	, ' ', 2	, 1)
+DEC(0, 2b,	BMI	, 0x2b		, "BMI %r"	, ' ', 2	, 1)
+DEC(0, 2c,	BGE	, 0x2c		, "BGE %r"	, ' ', 2	, 1)
+DEC(0, 2d,	BLT	, 0x2d		, "BLT %r"	, ' ', 2	, 1)
+DEC(0, 2e,	BGT	, 0x2e		, "BGT %r"	, ' ', 2	, 1)
+DEC(0, 2f,	BLE	, 0x2f		, "BLE %r"	, ' ', 2	, 1)
+
+DEC(0, 30,	i_pul16	, _cX		, "PULX"	, ' ', 1	, 3)
+DEC(0, 31,	i_pul16	, _cY		, "PULY"	, ' ', 1	, 3)
+DEC(0, 32,	i_pul8	, _cA		, "PULA"	, ' ', 1	, 3)
+DEC(0, 33,	i_pul8	, _cB		, "PULB"	, ' ', 1	, 3)
+DEC(0, 34,	i_psh16	, _Xop		, "PSHX"	, ' ', 1	, 2)
+DEC(0, 35,	i_psh16	, _Yop		, "PSHY"	, ' ', 1	, 2)
+DEC(0, 36,	i_psh8	, _Aop		, "PSHA"	, ' ', 1	, 2)
+DEC(0, 37,	i_psh8	, _Bop		, "PSHB"	, ' ', 1	, 2)
+DEC(0, 38,	i_pul8	, _cC		, "PULC"	, ' ', 1	, 3)
+DEC(0, 39,	i_psh8	, _Cop		, "PSHC"	, ' ', 1	, 2)
+DEC(0, 3a,	i_pul16	, _cD		, "PULD"	, ' ', 1	, 3)
+DEC(0, 3b,	i_psh16	, _Dop		, "PSHD"	, ' ', 1	, 2)
+
+DEC(0, a7,	NOP	, 0xa7		, "NOP"		, ' ', 1	, 1)
+
+DEC(0, b7,	exec_b7	, _NONE		, "%T"		, ' ', 2	, 0)
+
+DEC(0x18, 06,	add	, _A_B		, "ABA"		, ' ', 2	, 2)
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m68hc12.src/dis.cc sdcc-4.2.0+dfsg/sim/ucsim/m68hc12.src/dis.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/m68hc12.src/dis.cc	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m68hc12.src/dis.cc	2022-02-02 07:13:37.000000000 +0000
@@ -0,0 +1,336 @@
+/*
+ * Simulator of microcontrollers (dis.cc)
+ *
+ * Copyright (C) 2020,20 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#include "glob12.h"
+
+#include "m68hc12cl.h"
+
+
+struct dis_entry *
+cl_m68hc12::dis_tbl(void)
+{
+  return disass12p0;
+}
+
+struct dis_entry *
+cl_m68hc12::get_dis_entry(t_addr addr)
+{
+  struct dis_entry *dt;
+  int i= 0;
+  t_mem code= rom->get(addr);
+
+  if (code == 0x18)
+    {
+      code= rom->get(addr+1);
+      dt= disass12p18;
+      while (((code & dt[i].mask) != dt[i].code) &&
+	     dt[i].mnemonic)
+	i++;
+      return &dt[i];
+    }
+  
+  dt= disass12p0;
+  while (((code & dt[i].mask) != dt[i].code) &&
+	 dt[i].mnemonic)
+    i++;
+  return &dt[i];
+
+}
+
+
+
+char *
+cl_m68hc12::disassc(t_addr addr, chars *comment)
+{
+  chars work= chars(), temp= chars();
+  const char *b;
+  //t_mem code= rom->get(addr);
+  struct dis_entry *dis_e;
+  int i;
+  bool first;
+  
+  if ((dis_e= get_dis_entry(addr)) == NULL)
+    return NULL;
+  if (dis_e->mnemonic == NULL)
+    return strdup("-- UNKNOWN/INVALID");
+  b= dis_e->mnemonic;
+
+  first= true;
+  work= "";
+  for (i=0; b[i]; i++)
+    {
+      if ((b[i] == ' ') && first)
+	{
+	  first= false;
+	  while (work.len() < 6) work.append(' ');
+	}
+      if (b[i] == '%')
+	{
+	  t_addr a;
+	  u8_t h, l;
+	  i++;
+	  temp= "";
+	  switch (b[i])
+	    {
+	    case 'x': case 'X': // indexed
+	      h= rom->read(addr+1);
+	      a= rX+h;
+	      work.appendf("$%02x,X", h);
+	      //add_spaces(&work, 20);
+	      if (b[i]=='x')
+		temp.appendf("; [$%04x]=$%02x", a, rom->read(a));
+	      else
+		temp.appendf("; [$%04x]=$%04x", a, read_addr(rom, a));
+	      break;
+	    case 'e': case 'E': // extended
+	      h= rom->read(addr+1);
+	      l= rom->read(addr+2);
+	      a= h*256 + l;
+	      work.appendf("$%04x", a);
+	      //add_spaces(&work, 20);
+	      if (b[i]=='e')
+		temp.appendf("; [$%04x]=$%02x", a, rom->read(a));
+	      else
+		temp.appendf("; [$%04x]=$%04x", a,
+			     read_addr(rom, a));
+	      break;
+	    case 'd': case 'D': // direct
+	      h= a= rom->read(addr+1);
+	      work.appendf("$00%02x", h);
+	      //add_spaces(&work, 20);
+	      if (b[i]=='d')
+		temp.appendf("; [$%04x]=$%02x", a, rom->read(a));
+	      else
+	        temp.appendf("; [$%04x]=$%04x", a,
+			     read_addr(rom, a));
+	      break;
+	    case 'b': // immediate 8 bit
+	      work.appendf("#$%02x",
+			   rom->read(addr+1));
+	      break;
+	    case 'B': // immediate 16 bit
+	      work.appendf("#$%04x",
+			   read_addr(rom, addr+1));
+	      break;
+	    case 'r': // relative
+	      work.appendf("$%04x",
+			   (addr+2+(i8_t)(rom->read(addr+1))) & 0xffff );
+	      break;
+	    case 'p': // xb postbyte
+	      {
+		t_addr a= addr+1;
+		disass_xb(&a, &work, comment);
+		addr= a;
+		break;
+	      }
+	    case 'T': // TFR/EXG
+	      disass_b7(&a, &work, comment);
+	    }
+	  //work+= temp;
+	  if (comment && temp.nempty())
+	    comment->append(temp);
+	}
+      else
+	work+= b[i];
+    }
+
+  return(strdup(work.c_str()));
+}
+
+const char *rr_names[4]= { "X", "Y", "SP", "PC" };
+
+void
+CL12::disass_xb(t_addr *addr, chars *work, chars *comment)
+{
+  u8_t p, h, l, n;
+  int rr= -1;
+  i16_t offset= 0;
+  t_addr aof_xb= *addr;
+  u16_t a;
+  
+  p= rom->read(aof_xb);
+  (*addr)++;
+  
+  switch (xb_type(p))
+    {
+    case 1: // 1. rr0n nnnn n5,r rr={X,Y,SP,PC}
+      rr= (p>>6)&3;
+      offset= p&0x1f;
+      if (p&0x10) offset|= 0xffe0;
+      if (offset)
+	work->appendf("%+d,", offset);
+      work->appendf("%s", rr_names[rr]);
+      break;
+  
+    case 6: // 6. 111r r111 [D,r] rr={X,Y,SP,PC}
+      work->appendf("[D,%s]", rr_names[(p&0x18)>>3]);
+      break;
+  
+    case 5: // 5. 111r r011 [n16,r] rr={X,Y,SP,PC}
+      h= rom->read(aof_xb+1);
+      l= rom->read(aof_xb+2);
+      work->appendf("[$%04x,%s]", h*256+l,rr_names[(p&0x18)>>3]);
+      break;
+
+    case 3: // 3. rr1p nnnn n4,+-r+- rr={X,Y,SP}
+      n= p&0xf;
+      if (n&0x08) n|= 0xf0;
+      if (p&0x10)
+	{
+	  // post +-
+	  work->appendf("%+d,%s%c",
+			(int)n,
+			rr_names[(p&0xc0)>>6],
+			(n<0)?'-':'+');
+	}
+      else
+	{
+	  // pre +-
+	  work->appendf("%+d,%c%s",
+			(int)n,
+			(n<0)?'-':'+',
+			rr_names[(p&0xc0)>>6]);
+	}
+      break;
+  
+    case 2: // 2. 111r r0zs n9/16,r rr={X,Y,SP,PC}
+      if ((p&0x02) == 0x00)
+	{
+	  // 9 bit
+	  offset= rom->read(aof_xb+1);
+	  if (p&0x01) offset|= 0xff00;
+	}
+      else
+	{
+	  // 16 bit
+	  h= rom->read(aof_xb+1);
+	  l= rom->read(aof_xb+2);
+	  offset= h*256+l;
+	}
+      work->appendf("$%+d,%s", offset, rr_names[(p&0x18)>>3]);
+      break;
+  
+    default: // 4. 111r r1aa {A,B,D},r rr={X,Y,SP,PC}
+      switch (p&0x03)
+	{
+	case 0x00: work->append("A,"); break;
+	case 0x01: work->append("B,"); break;
+	case 0x02: work->append("D,"); break;
+	}
+      work->appendf("%s", rr_names[(p&0x18)>>3]);
+      break;
+    }
+
+  a= naddr(&aof_xb, NULL);
+  if (comment)
+    {
+      bool b= false;
+      comment->append("; [");
+      if (rr >= 0)
+	comment->appendf("%s", rr_names[rr]), b= true;
+      if (offset)
+	comment->appendf("%+d", offset), b= true;
+      if (b)
+	comment->append("=");
+      comment->appendf("%04x]=$%02x%02x%02x",
+		       a,
+		       rom->read(a), rom->read(a+1), rom->read(a+2));
+    }
+  *addr= aof_xb;
+}
+
+void
+CL12::disass_b7(t_addr *addr, chars *work, chars *comment)
+{
+  (*addr)++;
+  u8_t pb= rom->read(*addr);
+  if (pb & 0x08)
+    work->append("TFR/EXG INVALID");
+  else
+    {
+      if (!(pb & 0x80))
+	work->append("TFR");
+      else
+	work->append("EXG");
+      while (work->len() < 6) work->append(' ');
+      u8_t ls= pb&7, ms= (pb>>4)&7;
+      const char *nd= (ms==3)?("TEMP2"):(tex_names[ms]);
+      work->appendf("%s", nd);
+      work->append(",");
+      work->appendf("%s", tex_names[ls]);
+    }
+}
+
+int
+CL12::inst_length(t_addr addr)
+{
+  struct dis_entry *di= get_dis_entry(addr);
+  if (di && di->mnemonic)
+    {
+      if (di->length >= 0)
+	return di->length;
+      int l= -(di->length);
+      u16_t a= (u16_t)addr+l-1;
+      u8_t p= rom->read(a);
+      if ((p & 0x20) == 0)
+	{
+	  // 1. rr0n nnnn n5,r rr={X,Y,SP,PC}
+	  return l;
+	}
+      else if ((p&0xe7) == 0xe7)
+	{
+	  // 6. 111r r111 [D,r] rr={X,Y,SP,PC}
+	  return l;
+	}
+      else if ((p&0xe7) == 0xe3)
+	{
+	  // 5. 111r r011 [n16,r] rr={X,Y,SP,PC}
+	  return l+2;
+	}
+      else if ((p&0xc0) != 0xc0)
+	{
+	  // 3. rr1p nnnn n4,+-r+- rr={X,Y,SP}
+	  return l;
+	}
+      else if ((p&0xe4) == 0xe0)
+	{
+	  // 2. 111r r0zs n9/16,r rr={X,Y,SP,PC}
+	  if ((p & 0x02) == 0)
+	    return l+1;
+	  return l+2;
+	}
+      else // if ((p&0xe4) == 0xe4)
+	{
+	  // 4. 111r r1aa {A,B,D},r rr={X,Y,SP,PC}
+	  return l;
+	}
+    }
+  return 1;
+}
+
+
+/* End of m68hc12.src/dis.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m68hc12.src/gen.h sdcc-4.2.0+dfsg/sim/ucsim/m68hc12.src/gen.h
--- sdcc-4.0.0+dfsg/sim/ucsim/m68hc12.src/gen.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m68hc12.src/gen.h	2022-02-03 14:04:59.000000000 +0000
@@ -0,0 +1,33 @@
+
+#define GEN_WRAPPER(PAGE,CODE,INST,ADDR_MODE)			\
+  int wrap_ ##PAGE ##_ ##CODE(class CL12 *uc, t_mem code)	\
+  {								\
+    return uc-> INST ( ADDR_MODE );				\
+  }
+
+#define GEN_DECL(PAGE,CODE)						\
+  extern int wrap_ ## PAGE ## _ ## CODE (class CL12 *uc, t_mem code);
+
+#define GEN_FILLER_METHOD(PAGE,CODE,MNEMO,BRANCH,LEN,TICKS)	\
+  virtual void fill_##PAGE ##_##CODE()				\
+  {								\
+    page##PAGE[0x## CODE ]= wrap_ ##PAGE ##_ ##CODE;		\
+    set_disass(PAGE, 0x## CODE, MNEMO, BRANCH, LEN);		\
+    set_ticks(PAGE, 0x## CODE, TICKS);				\
+  }
+
+
+#ifdef GEN_W
+#define DEC(PAGE,CODE,INST,ADDR_MODE,MNEMO,BRANCH,LEN,TICKS)		\
+  GEN_WRAPPER(PAGE,CODE,INST,ADDR_MODE)
+#endif
+
+#ifdef GEN_D
+#define DEC(PAGE,CODE,INST,ADDR_MODE,MNEMO,BRANCH,LEN,TICKS)		\
+  GEN_DECL(PAGE,CODE)
+#endif
+
+#ifdef GEN_F
+#define DEC(PAGE,CODE,INST,ADDR_MODE,MNEMO,BRANCH,LEN,TICKS)		\
+  GEN_FILLER_METHOD(PAGE,CODE,MNEMO,BRANCH,LEN,TICKS)
+#endif
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m68hc12.src/glob12.cc sdcc-4.2.0+dfsg/sim/ucsim/m68hc12.src/glob12.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/m68hc12.src/glob12.cc	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m68hc12.src/glob12.cc	2022-01-27 21:35:29.000000000 +0000
@@ -0,0 +1,40 @@
+/*
+ * Simulator of microcontrollers (glob12.cc)
+ *
+ * Copyright (C) @@S@@,@@Y@@ Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#include 
+
+#include "glob12.h"
+
+
+struct dis_entry disass12p0[257];
+struct dis_entry disass12p18[257];
+
+int ticks12p0[256];
+int ticks12p18[256];
+
+
+/* End of m68hc12.src/glob12.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m68hc12.src/glob12.h sdcc-4.2.0+dfsg/sim/ucsim/m68hc12.src/glob12.h
--- sdcc-4.0.0+dfsg/sim/ucsim/m68hc12.src/glob12.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m68hc12.src/glob12.h	2022-01-27 21:35:29.000000000 +0000
@@ -0,0 +1,47 @@
+/*
+ * Simulator of microcontrollers (glob12.h)
+ *
+ * Copyright (C) @@S@@,@@Y@@ Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef HC12GLOB12_HEADER
+#define HC12GLOB12_HEADER
+
+// prj
+#include "stypes.h"
+
+// sim
+//#include "iwrap.h"
+
+
+extern struct dis_entry disass12p0[257];
+extern struct dis_entry disass12p18[257];
+
+extern int ticks12p0[256];
+extern int ticks12p18[256];
+
+
+#endif
+
+/* End of m68hc12.src/glob11.h */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m68hc12.src/glob.cc sdcc-4.2.0+dfsg/sim/ucsim/m68hc12.src/glob.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/m68hc12.src/glob.cc	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m68hc12.src/glob.cc	2021-10-03 12:24:27.000000000 +0000
@@ -0,0 +1,40 @@
+/*
+ * Simulator of microcontrollers (glob.cc)
+ *
+ * Copyright (C) @@S@@,@@Y@@ Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#include 
+
+#include "glob.h"
+
+struct cpu_entry cpus_hc12[]=
+  {
+    {"HC12"  , CPU_HC12, CPU_CMOS	, "hc12"	, "cmos"},
+
+    {NULL, CPU_NONE, 0, "", ""}
+  };
+
+
+/* End of m68hc12.src/glob.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m68hc12.src/glob.h sdcc-4.2.0+dfsg/sim/ucsim/m68hc12.src/glob.h
--- sdcc-4.0.0+dfsg/sim/ucsim/m68hc12.src/glob.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m68hc12.src/glob.h	2021-10-03 12:24:27.000000000 +0000
@@ -0,0 +1,45 @@
+/*
+ * Simulator of microcontrollers (glob.h)
+ *
+ * Copyright (C) @@S@@,@@Y@@ Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef HC12GLOB_HEADER
+#define HC12GLOB_HEADER
+
+// prj
+#include "stypes.h"
+
+// sim
+#include "iwrap.h"
+
+
+extern struct cpu_entry cpus_hc12[];
+
+extern struct dis_entry disass_m68hc11[];
+
+
+#endif
+
+/* End of m68hc12.src/glob.h */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m68hc12.src/hcwrap.cc sdcc-4.2.0+dfsg/sim/ucsim/m68hc12.src/hcwrap.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/m68hc12.src/hcwrap.cc	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m68hc12.src/hcwrap.cc	2022-01-27 21:35:29.000000000 +0000
@@ -0,0 +1,94 @@
+/*
+ * Simulator of microcontrollers (hcwrap.cc)
+ *
+ * Copyright (C) @@S@@,@@Y@@ Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#include "glob12.h"
+
+#include "hcwrapcl.h"
+
+
+int wrap_INV(class CL12 *uc, t_mem code) { return resINV; }
+int wrap_TRAP(class CL12 *uc, t_mem code) { return uc->trap(code); }
+
+cl_wrap::cl_wrap():
+  cl_base()
+{
+  int i;
+  for (i= 0; i < 257; i++)
+    {
+      disass12p0[i].code= (i<=255)?i:0;
+      disass12p0[i].mask= 0xff;
+      disass12p0[i].branch= ' ';
+      disass12p0[i].length= 1;
+      disass12p0[i].mnemonic= "";
+      disass12p0[i].is_call= false;
+      disass12p0[i].ticks= 1;
+
+      disass12p18[i].code= (i<=255)?i:0;
+      disass12p18[i].mask= 0xff;
+      disass12p18[i].branch= ' ';
+      disass12p18[i].length= 1;
+      disass12p18[i].mnemonic= "";
+      disass12p18[i].is_call= false;
+      disass12p18[i].ticks= 1;
+    }
+}
+
+void
+cl_wrap::set_disass(int page, int code, const char *mnemo, char branch, int len)
+{
+  struct dis_entry *tab= NULL;
+  switch (page)
+    {
+    case 0: tab= disass12p0; break;
+    case 0x18: tab= disass12p18; break;
+    }
+  if (tab == NULL)
+    return;
+  tab[code].code= code;
+  tab[code].branch= branch;
+  tab[code].length= len;
+  tab[code].mnemonic= mnemo;
+}
+
+void
+cl_wrap::set_ticks(int page, int code, int ticks)
+{
+  int *tab= NULL;
+  switch (page)
+    {
+    case 0: tab= ticks12p0; break;
+    case 0x18: tab= ticks12p18; break;
+    }
+  if (tab == NULL)
+    return ;
+  tab[code]= ticks;
+}
+
+
+#include "wdefs.h"
+
+/* End of m68hc12.src/hcwrap.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m68hc12.src/hcwrapcl.h sdcc-4.2.0+dfsg/sim/ucsim/m68hc12.src/hcwrapcl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/m68hc12.src/hcwrapcl.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m68hc12.src/hcwrapcl.h	2022-02-03 14:04:59.000000000 +0000
@@ -0,0 +1,1220 @@
+/*
+ * Simulator of microcontrollers (hcwrapcl.h)
+ *
+ * Copyright (C) @@S@@,@@Y@@ Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef HCWRAPCL_HEADER
+#define HCWRAPCL_HEADER
+
+#include "glob12.h"
+#include "m68hc12cl.h"
+
+#define _NONE
+#define _cA		uc->cA
+#define _cB		uc->cB
+#define _cD		uc->cD
+#define _cC		uc->cCC
+#define _cX		uc->cIX
+#define _cY		uc->cIY
+
+#define _d		uc->ddst()
+#define _d_Aop		uc->ddst(),uc->acc.DAB.a8.Ar
+#define _d_Bop		uc->ddst(),uc->acc.DAB.a8.Br
+#define _d_i8		uc->ddst(),uc->i8()
+#define _d_i8n		uc->ddst(),~(uc->i8())
+
+#define _da		uc->daddr()
+#define _da_Dop		uc->daddr(),uc->acc.DAB.Dr
+#define _da_Xop		uc->daddr(),uc->IX
+#define _da_Yop		uc->daddr(),uc->IY
+#define _da_Sop		uc->daddr(),uc->SP
+
+#define _e		uc->edst()
+#define _e_Aop		uc->edst(),uc->acc.DAB.a8.Ar
+#define _e_Bop		uc->edst(),uc->acc.DAB.a8.Br
+#define _e_i8		uc->edst(),uc->i8()
+#define _e_i8n		uc->edst(),~(uc->i8())
+
+#define _ea		uc->eaddr()
+#define _ea_Dop		uc->eaddr(),uc->acc.DAB.Dr
+#define _ea_Xop		uc->eaddr(),uc->IX
+#define _ea_Yop		uc->eaddr(),uc->IY
+#define _ea_Sop		uc->eaddr(),uc->SP
+
+#define _xb		uc->xbdst()
+#define _xb_Aop		uc->xbdst(),uc->acc.DAB.a8.Ar
+#define _xb_Bop		uc->xbdst(),uc->acc.DAB.a8.Br
+#define _xb_i8		uc->xbdst(),uc->i8()
+#define _xb_i8n		uc->xbdst(),~(uc->i8())
+
+#define _xba		uc->xbaddr()
+#define _xba_Dop	uc->xbaddr(),uc->acc.DAB.Dr
+#define _xba_Xop	uc->xbaddr(),uc->IX
+#define _xba_Yop	uc->xbaddr(),uc->IY
+#define _xba_Sop	uc->xbaddr(),uc->SP
+
+#define _Aop		uc->acc.DAB.a8.Ar
+#define _Bop		uc->acc.DAB.a8.Br
+#define _Dop		uc->acc.DAB.Dr
+#define _Cop		uc->CC.cc16.cc8.ccl
+#define _Xop		uc->IX
+#define _Yop		uc->IY
+#define _dop		uc->dop()
+#define _eop		uc->eop()
+#define _xbop8		uc->xbop8()
+
+#define _A_B		uc->cA,uc->acc.DAB.a8.Br
+
+#define _A_i8		uc->cA,uc->i8()
+#define _A_dop		uc->cA,uc->dop()
+#define _A_eop		uc->cA,uc->eop()
+#define _A_xbop8	uc->cA,uc->xbop8()
+
+#define _Aop_i8		uc->acc.DAB.a8.Ar,uc->i8()
+#define _Aop_dop	uc->acc.DAB.a8.Ar,uc->dop()
+#define _Aop_eop	uc->acc.DAB.a8.Ar,uc->eop()
+#define _Aop_xbop8	uc->acc.DAB.a8.Ar,uc->xbop8()
+
+#define _B_i8		uc->cB,uc->i8()
+#define _B_dop		uc->cB,uc->dop()
+#define _B_eop		uc->cB,uc->eop()
+#define _B_xbop8	uc->cB,uc->xbop8()
+
+#define _Bop_i8		uc->acc.DAB.a8.Br,uc->i8()
+#define _Bop_dop	uc->acc.DAB.a8.Br,uc->dop()
+#define _Bop_eop	uc->acc.DAB.a8.Br,uc->eop()
+#define _Bop_xbop8	uc->acc.DAB.a8.Br,uc->xbop8()
+
+#define _D_i16		uc->cD,uc->i16()
+#define _D_dop16	uc->cD,uc->dop16()
+#define _D_eop16	uc->cD,uc->eop16()
+#define _D_xbop16	uc->cD,uc->xbop16()
+
+#define _Dop_i16	uc->acc.DAB.Dr,uc->i16()
+#define _Dop_dop16	uc->acc.DAB.Dr,uc->dop16()
+#define _Dop_eop16	uc->acc.DAB.Dr,uc->eop16()
+#define _Dop_xbop16	uc->acc.DAB.Dr,uc->xbop16()
+
+#define _X_i16		uc->cIX,uc->i16()
+#define _X_dop16	uc->cIX,uc->dop16()
+#define _X_eop16	uc->cIX,uc->eop16()
+#define _X_xbop16	uc->cIX,uc->xbop16()
+
+#define _Xop_i16	uc->IX,uc->i16()
+#define _Xop_dop16	uc->IX,uc->dop16()
+#define _Xop_eop16	uc->IX,uc->eop16()
+#define _Xop_xbop16	uc->IX,uc->xbop16()
+
+#define _Y_i16		uc->cIY,uc->i16()
+#define _Y_dop16	uc->cIY,uc->dop16()
+#define _Y_eop16	uc->cIY,uc->eop16()
+#define _Y_xbop16	uc->cIY,uc->xbop16()
+
+#define _Yop_i16	uc->IY,uc->i16()
+#define _Yop_dop16	uc->IY,uc->dop16()
+#define _Yop_eop16	uc->IY,uc->eop16()
+#define _Yop_xbop16	uc->IY,uc->xbop16()
+
+#define _S_i16		uc->cSP,uc->i16()
+#define _S_dop16	uc->cSP,uc->dop16()
+#define _S_eop16	uc->cSP,uc->eop16()
+#define _S_xbop16	uc->cSP,uc->xbop16()
+
+#define _Sop_i16	uc->SP,uc->i16()
+#define _Sop_dop16	uc->SP,uc->dop16()
+#define _Sop_eop16	uc->SP,uc->eop16()
+#define _Sop_xbop16	uc->SP,uc->xbop16()
+
+extern int wrap_INV(class CL12 *uc, t_mem code);
+extern int wrap_TRAP(class CL12 *uc, t_mem code);
+
+class cl_wrap: public cl_base
+{
+public:
+  hcwrapper_fn page0[256], page0x18[256];
+public:
+  cl_wrap();
+  virtual void set_disass(int page, int code, const char *mnemo, char branch, int len);
+  virtual void set_ticks(int page, int code, int ticks);
+  virtual int init()
+  {
+    fill_0_00();
+    fill_0_01();
+    fill_0_02();
+    fill_0_03();
+    fill_0_04();
+    fill_0_05();
+    fill_0_06();
+    fill_0_07();
+    fill_0_08();
+    fill_0_09();
+    fill_0_0a();
+    fill_0_0b();
+    fill_0_0c();
+    fill_0_0d();
+    fill_0_0e();
+    fill_0_0f();
+    fill_0_10();
+    fill_0_11();
+    fill_0_12();
+    fill_0_13();
+    fill_0_14();
+    fill_0_15();
+    fill_0_16();
+    fill_0_17();
+    fill_0_18();
+    fill_0_19();
+    fill_0_1a();
+    fill_0_1b();
+    fill_0_1c();
+    fill_0_1d();
+    fill_0_1e();
+    fill_0_1f();
+    fill_0_20();
+    fill_0_21();
+    fill_0_22();
+    fill_0_23();
+    fill_0_24();
+    fill_0_25();
+    fill_0_26();
+    fill_0_27();
+    fill_0_28();
+    fill_0_29();
+    fill_0_2a();
+    fill_0_2b();
+    fill_0_2c();
+    fill_0_2d();
+    fill_0_2e();
+    fill_0_2f();
+    fill_0_30();
+    fill_0_31();
+    fill_0_32();
+    fill_0_33();
+    fill_0_34();
+    fill_0_35();
+    fill_0_36();
+    fill_0_37();
+    fill_0_38();
+    fill_0_39();
+    fill_0_3a();
+    fill_0_3b();
+    fill_0_3c();
+    fill_0_3d();
+    fill_0_3e();
+    fill_0_3f();
+    fill_0_40();
+    fill_0_41();
+    fill_0_42();
+    fill_0_43();
+    fill_0_44();
+    fill_0_45();
+    fill_0_46();
+    fill_0_47();
+    fill_0_48();
+    fill_0_49();
+    fill_0_4a();
+    fill_0_4b();
+    fill_0_4c();
+    fill_0_4d();
+    fill_0_4e();
+    fill_0_4f();
+    fill_0_50();
+    fill_0_51();
+    fill_0_52();
+    fill_0_53();
+    fill_0_54();
+    fill_0_55();
+    fill_0_56();
+    fill_0_57();
+    fill_0_58();
+    fill_0_59();
+    fill_0_5a();
+    fill_0_5b();
+    fill_0_5c();
+    fill_0_5d();
+    fill_0_5e();
+    fill_0_5f();
+    fill_0_60();
+    fill_0_61();
+    fill_0_62();
+    fill_0_63();
+    fill_0_64();
+    fill_0_65();
+    fill_0_66();
+    fill_0_67();
+    fill_0_68();
+    fill_0_69();
+    fill_0_6a();
+    fill_0_6b();
+    fill_0_6c();
+    fill_0_6d();
+    fill_0_6e();
+    fill_0_6f();
+    fill_0_70();
+    fill_0_71();
+    fill_0_72();
+    fill_0_73();
+    fill_0_74();
+    fill_0_75();
+    fill_0_76();
+    fill_0_77();
+    fill_0_78();
+    fill_0_79();
+    fill_0_7a();
+    fill_0_7b();
+    fill_0_7c();
+    fill_0_7d();
+    fill_0_7e();
+    fill_0_7f();
+    fill_0_80();
+    fill_0_81();
+    fill_0_82();
+    fill_0_83();
+    fill_0_84();
+    fill_0_85();
+    fill_0_86();
+    fill_0_87();
+    fill_0_88();
+    fill_0_89();
+    fill_0_8a();
+    fill_0_8b();
+    fill_0_8c();
+    fill_0_8d();
+    fill_0_8e();
+    fill_0_8f();
+    fill_0_90();
+    fill_0_91();
+    fill_0_92();
+    fill_0_93();
+    fill_0_94();
+    fill_0_95();
+    fill_0_96();
+    fill_0_97();
+    fill_0_98();
+    fill_0_99();
+    fill_0_9a();
+    fill_0_9b();
+    fill_0_9c();
+    fill_0_9d();
+    fill_0_9e();
+    fill_0_9f();
+    fill_0_a0();
+    fill_0_a1();
+    fill_0_a2();
+    fill_0_a3();
+    fill_0_a4();
+    fill_0_a5();
+    fill_0_a6();
+    fill_0_a7();
+    fill_0_a8();
+    fill_0_a9();
+    fill_0_aa();
+    fill_0_ab();
+    fill_0_ac();
+    fill_0_ad();
+    fill_0_ae();
+    fill_0_af();
+    fill_0_b0();
+    fill_0_b1();
+    fill_0_b2();
+    fill_0_b3();
+    fill_0_b4();
+    fill_0_b5();
+    fill_0_b6();
+    fill_0_b7();
+    fill_0_b8();
+    fill_0_b9();
+    fill_0_ba();
+    fill_0_bb();
+    fill_0_bc();
+    fill_0_bd();
+    fill_0_be();
+    fill_0_bf();
+    fill_0_c0();
+    fill_0_c1();
+    fill_0_c2();
+    fill_0_c3();
+    fill_0_c4();
+    fill_0_c5();
+    fill_0_c6();
+    fill_0_c7();
+    fill_0_c8();
+    fill_0_c9();
+    fill_0_ca();
+    fill_0_cb();
+    fill_0_cc();
+    fill_0_cd();
+    fill_0_ce();
+    fill_0_cf();
+    fill_0_d0();
+    fill_0_d1();
+    fill_0_d2();
+    fill_0_d3();
+    fill_0_d4();
+    fill_0_d5();
+    fill_0_d6();
+    fill_0_d7();
+    fill_0_d8();
+    fill_0_d9();
+    fill_0_da();
+    fill_0_db();
+    fill_0_dc();
+    fill_0_dd();
+    fill_0_de();
+    fill_0_df();
+    fill_0_e0();
+    fill_0_e1();
+    fill_0_e2();
+    fill_0_e3();
+    fill_0_e4();
+    fill_0_e5();
+    fill_0_e6();
+    fill_0_e7();
+    fill_0_e8();
+    fill_0_e9();
+    fill_0_ea();
+    fill_0_eb();
+    fill_0_ec();
+    fill_0_ed();
+    fill_0_ee();
+    fill_0_ef();
+    fill_0_f0();
+    fill_0_f1();
+    fill_0_f2();
+    fill_0_f3();
+    fill_0_f4();
+    fill_0_f5();
+    fill_0_f6();
+    fill_0_f7();
+    fill_0_f8();
+    fill_0_f9();
+    fill_0_fa();
+    fill_0_fb();
+    fill_0_fc();
+    fill_0_fd();
+    fill_0_fe();
+    fill_0_ff();
+
+    fill_0x18_00();
+    fill_0x18_01();
+    fill_0x18_02();
+    fill_0x18_03();
+    fill_0x18_04();
+    fill_0x18_05();
+    fill_0x18_06();
+    fill_0x18_07();
+    fill_0x18_08();
+    fill_0x18_09();
+    fill_0x18_0a();
+    fill_0x18_0b();
+    fill_0x18_0c();
+    fill_0x18_0d();
+    fill_0x18_0e();
+    fill_0x18_0f();
+    fill_0x18_10();
+    fill_0x18_11();
+    fill_0x18_12();
+    fill_0x18_13();
+    fill_0x18_14();
+    fill_0x18_15();
+    fill_0x18_16();
+    fill_0x18_17();
+    fill_0x18_18();
+    fill_0x18_19();
+    fill_0x18_1a();
+    fill_0x18_1b();
+    fill_0x18_1c();
+    fill_0x18_1d();
+    fill_0x18_1e();
+    fill_0x18_1f();
+    fill_0x18_20();
+    fill_0x18_21();
+    fill_0x18_22();
+    fill_0x18_23();
+    fill_0x18_24();
+    fill_0x18_25();
+    fill_0x18_26();
+    fill_0x18_27();
+    fill_0x18_28();
+    fill_0x18_29();
+    fill_0x18_2a();
+    fill_0x18_2b();
+    fill_0x18_2c();
+    fill_0x18_2d();
+    fill_0x18_2e();
+    fill_0x18_2f();
+    fill_0x18_30();
+    fill_0x18_31();
+    fill_0x18_32();
+    fill_0x18_33();
+    fill_0x18_34();
+    fill_0x18_35();
+    fill_0x18_36();
+    fill_0x18_37();
+    fill_0x18_38();
+    fill_0x18_39();
+    fill_0x18_3a();
+    fill_0x18_3b();
+    fill_0x18_3c();
+    fill_0x18_3d();
+    fill_0x18_3e();
+    fill_0x18_3f();
+    fill_0x18_40();
+    fill_0x18_41();
+    fill_0x18_42();
+    fill_0x18_43();
+    fill_0x18_44();
+    fill_0x18_45();
+    fill_0x18_46();
+    fill_0x18_47();
+    fill_0x18_48();
+    fill_0x18_49();
+    fill_0x18_4a();
+    fill_0x18_4b();
+    fill_0x18_4c();
+    fill_0x18_4d();
+    fill_0x18_4e();
+    fill_0x18_4f();
+    fill_0x18_50();
+    fill_0x18_51();
+    fill_0x18_52();
+    fill_0x18_53();
+    fill_0x18_54();
+    fill_0x18_55();
+    fill_0x18_56();
+    fill_0x18_57();
+    fill_0x18_58();
+    fill_0x18_59();
+    fill_0x18_5a();
+    fill_0x18_5b();
+    fill_0x18_5c();
+    fill_0x18_5d();
+    fill_0x18_5e();
+    fill_0x18_5f();
+    fill_0x18_60();
+    fill_0x18_61();
+    fill_0x18_62();
+    fill_0x18_63();
+    fill_0x18_64();
+    fill_0x18_65();
+    fill_0x18_66();
+    fill_0x18_67();
+    fill_0x18_68();
+    fill_0x18_69();
+    fill_0x18_6a();
+    fill_0x18_6b();
+    fill_0x18_6c();
+    fill_0x18_6d();
+    fill_0x18_6e();
+    fill_0x18_6f();
+    fill_0x18_70();
+    fill_0x18_71();
+    fill_0x18_72();
+    fill_0x18_73();
+    fill_0x18_74();
+    fill_0x18_75();
+    fill_0x18_76();
+    fill_0x18_77();
+    fill_0x18_78();
+    fill_0x18_79();
+    fill_0x18_7a();
+    fill_0x18_7b();
+    fill_0x18_7c();
+    fill_0x18_7d();
+    fill_0x18_7e();
+    fill_0x18_7f();
+    fill_0x18_80();
+    fill_0x18_81();
+    fill_0x18_82();
+    fill_0x18_83();
+    fill_0x18_84();
+    fill_0x18_85();
+    fill_0x18_86();
+    fill_0x18_87();
+    fill_0x18_88();
+    fill_0x18_89();
+    fill_0x18_8a();
+    fill_0x18_8b();
+    fill_0x18_8c();
+    fill_0x18_8d();
+    fill_0x18_8e();
+    fill_0x18_8f();
+    fill_0x18_90();
+    fill_0x18_91();
+    fill_0x18_92();
+    fill_0x18_93();
+    fill_0x18_94();
+    fill_0x18_95();
+    fill_0x18_96();
+    fill_0x18_97();
+    fill_0x18_98();
+    fill_0x18_99();
+    fill_0x18_9a();
+    fill_0x18_9b();
+    fill_0x18_9c();
+    fill_0x18_9d();
+    fill_0x18_9e();
+    fill_0x18_9f();
+    fill_0x18_a0();
+    fill_0x18_a1();
+    fill_0x18_a2();
+    fill_0x18_a3();
+    fill_0x18_a4();
+    fill_0x18_a5();
+    fill_0x18_a6();
+    fill_0x18_a7();
+    fill_0x18_a8();
+    fill_0x18_a9();
+    fill_0x18_aa();
+    fill_0x18_ab();
+    fill_0x18_ac();
+    fill_0x18_ad();
+    fill_0x18_ae();
+    fill_0x18_af();
+    fill_0x18_b0();
+    fill_0x18_b1();
+    fill_0x18_b2();
+    fill_0x18_b3();
+    fill_0x18_b4();
+    fill_0x18_b5();
+    fill_0x18_b6();
+    fill_0x18_b7();
+    fill_0x18_b8();
+    fill_0x18_b9();
+    fill_0x18_ba();
+    fill_0x18_bb();
+    fill_0x18_bc();
+    fill_0x18_bd();
+    fill_0x18_be();
+    fill_0x18_bf();
+    fill_0x18_c0();
+    fill_0x18_c1();
+    fill_0x18_c2();
+    fill_0x18_c3();
+    fill_0x18_c4();
+    fill_0x18_c5();
+    fill_0x18_c6();
+    fill_0x18_c7();
+    fill_0x18_c8();
+    fill_0x18_c9();
+    fill_0x18_ca();
+    fill_0x18_cb();
+    fill_0x18_cc();
+    fill_0x18_cd();
+    fill_0x18_ce();
+    fill_0x18_cf();
+    fill_0x18_d0();
+    fill_0x18_d1();
+    fill_0x18_d2();
+    fill_0x18_d3();
+    fill_0x18_d4();
+    fill_0x18_d5();
+    fill_0x18_d6();
+    fill_0x18_d7();
+    fill_0x18_d8();
+    fill_0x18_d9();
+    fill_0x18_da();
+    fill_0x18_db();
+    fill_0x18_dc();
+    fill_0x18_dd();
+    fill_0x18_de();
+    fill_0x18_df();
+    fill_0x18_e0();
+    fill_0x18_e1();
+    fill_0x18_e2();
+    fill_0x18_e3();
+    fill_0x18_e4();
+    fill_0x18_e5();
+    fill_0x18_e6();
+    fill_0x18_e7();
+    fill_0x18_e8();
+    fill_0x18_e9();
+    fill_0x18_ea();
+    fill_0x18_eb();
+    fill_0x18_ec();
+    fill_0x18_ed();
+    fill_0x18_ee();
+    fill_0x18_ef();
+    fill_0x18_f0();
+    fill_0x18_f1();
+    fill_0x18_f2();
+    fill_0x18_f3();
+    fill_0x18_f4();
+    fill_0x18_f5();
+    fill_0x18_f6();
+    fill_0x18_f7();
+    fill_0x18_f8();
+    fill_0x18_f9();
+    fill_0x18_fa();
+    fill_0x18_fb();
+    fill_0x18_fc();
+    fill_0x18_fd();
+    fill_0x18_fe();
+    fill_0x18_ff();
+
+    {
+      int i;
+      chars s;
+      for (i= 0; i<256; i++)
+	{
+	  s.format("TRAP $%02x", i);
+	  disass12p18[i].code= i;
+	  disass12p18[i].branch= ' ';
+	  disass12p18[i].length= 2;
+	  disass12p18[i].mnemonic= strdup(s.c_str());
+	  ticks12p18[i]= 11;
+	}
+    }
+    return 0;
+  }
+  virtual void fill_0_00() { page0[0x00]= wrap_INV; }
+  virtual void fill_0_01() { page0[0x01]= wrap_INV; }
+  virtual void fill_0_02() { page0[0x02]= wrap_INV; }
+  virtual void fill_0_03() { page0[0x03]= wrap_INV; }
+  virtual void fill_0_04() { page0[0x04]= wrap_INV; }
+  virtual void fill_0_05() { page0[0x05]= wrap_INV; }
+  virtual void fill_0_06() { page0[0x06]= wrap_INV; }
+  virtual void fill_0_07() { page0[0x07]= wrap_INV; }
+  virtual void fill_0_08() { page0[0x08]= wrap_INV; }
+  virtual void fill_0_09() { page0[0x09]= wrap_INV; }
+  virtual void fill_0_0a() { page0[0x0a]= wrap_INV; }
+  virtual void fill_0_0b() { page0[0x0b]= wrap_INV; }
+  virtual void fill_0_0c() { page0[0x0c]= wrap_INV; }
+  virtual void fill_0_0d() { page0[0x0d]= wrap_INV; }
+  virtual void fill_0_0e() { page0[0x0e]= wrap_INV; }
+  virtual void fill_0_0f() { page0[0x0f]= wrap_INV; }
+  virtual void fill_0_10() { page0[0x10]= wrap_INV; }
+  virtual void fill_0_11() { page0[0x11]= wrap_INV; }
+  virtual void fill_0_12() { page0[0x12]= wrap_INV; }
+  virtual void fill_0_13() { page0[0x13]= wrap_INV; }
+  virtual void fill_0_14() { page0[0x14]= wrap_INV; }
+  virtual void fill_0_15() { page0[0x15]= wrap_INV; }
+  virtual void fill_0_16() { page0[0x16]= wrap_INV; }
+  virtual void fill_0_17() { page0[0x17]= wrap_INV; }
+  virtual void fill_0_18() { page0[0x18]= wrap_INV; }
+  virtual void fill_0_19() { page0[0x19]= wrap_INV; }
+  virtual void fill_0_1a() { page0[0x1a]= wrap_INV; }
+  virtual void fill_0_1b() { page0[0x1b]= wrap_INV; }
+  virtual void fill_0_1c() { page0[0x1c]= wrap_INV; }
+  virtual void fill_0_1d() { page0[0x1d]= wrap_INV; }
+  virtual void fill_0_1e() { page0[0x1e]= wrap_INV; }
+  virtual void fill_0_1f() { page0[0x1f]= wrap_INV; }
+  virtual void fill_0_20() { page0[0x20]= wrap_INV; }
+  virtual void fill_0_21() { page0[0x21]= wrap_INV; }
+  virtual void fill_0_22() { page0[0x22]= wrap_INV; }
+  virtual void fill_0_23() { page0[0x23]= wrap_INV; }
+  virtual void fill_0_24() { page0[0x24]= wrap_INV; }
+  virtual void fill_0_25() { page0[0x25]= wrap_INV; }
+  virtual void fill_0_26() { page0[0x26]= wrap_INV; }
+  virtual void fill_0_27() { page0[0x27]= wrap_INV; }
+  virtual void fill_0_28() { page0[0x28]= wrap_INV; }
+  virtual void fill_0_29() { page0[0x29]= wrap_INV; }
+  virtual void fill_0_2a() { page0[0x2a]= wrap_INV; }
+  virtual void fill_0_2b() { page0[0x2b]= wrap_INV; }
+  virtual void fill_0_2c() { page0[0x2c]= wrap_INV; }
+  virtual void fill_0_2d() { page0[0x2d]= wrap_INV; }
+  virtual void fill_0_2e() { page0[0x2e]= wrap_INV; }
+  virtual void fill_0_2f() { page0[0x2f]= wrap_INV; }
+  virtual void fill_0_30() { page0[0x30]= wrap_INV; }
+  virtual void fill_0_31() { page0[0x31]= wrap_INV; }
+  virtual void fill_0_32() { page0[0x32]= wrap_INV; }
+  virtual void fill_0_33() { page0[0x33]= wrap_INV; }
+  virtual void fill_0_34() { page0[0x34]= wrap_INV; }
+  virtual void fill_0_35() { page0[0x35]= wrap_INV; }
+  virtual void fill_0_36() { page0[0x36]= wrap_INV; }
+  virtual void fill_0_37() { page0[0x37]= wrap_INV; }
+  virtual void fill_0_38() { page0[0x38]= wrap_INV; }
+  virtual void fill_0_39() { page0[0x39]= wrap_INV; }
+  virtual void fill_0_3a() { page0[0x3a]= wrap_INV; }
+  virtual void fill_0_3b() { page0[0x3b]= wrap_INV; }
+  virtual void fill_0_3c() { page0[0x3c]= wrap_INV; }
+  virtual void fill_0_3d() { page0[0x3d]= wrap_INV; }
+  virtual void fill_0_3e() { page0[0x3e]= wrap_INV; }
+  virtual void fill_0_3f() { page0[0x3f]= wrap_INV; }
+  virtual void fill_0_40() { page0[0x40]= wrap_INV; }
+  virtual void fill_0_41() { page0[0x41]= wrap_INV; }
+  virtual void fill_0_42() { page0[0x42]= wrap_INV; }
+  virtual void fill_0_43() { page0[0x43]= wrap_INV; }
+  virtual void fill_0_44() { page0[0x44]= wrap_INV; }
+  virtual void fill_0_45() { page0[0x45]= wrap_INV; }
+  virtual void fill_0_46() { page0[0x46]= wrap_INV; }
+  virtual void fill_0_47() { page0[0x47]= wrap_INV; }
+  virtual void fill_0_48() { page0[0x48]= wrap_INV; }
+  virtual void fill_0_49() { page0[0x49]= wrap_INV; }
+  virtual void fill_0_4a() { page0[0x4a]= wrap_INV; }
+  virtual void fill_0_4b() { page0[0x4b]= wrap_INV; }
+  virtual void fill_0_4c() { page0[0x4c]= wrap_INV; }
+  virtual void fill_0_4d() { page0[0x4d]= wrap_INV; }
+  virtual void fill_0_4e() { page0[0x4e]= wrap_INV; }
+  virtual void fill_0_4f() { page0[0x4f]= wrap_INV; }
+  virtual void fill_0_50() { page0[0x50]= wrap_INV; }
+  virtual void fill_0_51() { page0[0x51]= wrap_INV; }
+  virtual void fill_0_52() { page0[0x52]= wrap_INV; }
+  virtual void fill_0_53() { page0[0x53]= wrap_INV; }
+  virtual void fill_0_54() { page0[0x54]= wrap_INV; }
+  virtual void fill_0_55() { page0[0x55]= wrap_INV; }
+  virtual void fill_0_56() { page0[0x56]= wrap_INV; }
+  virtual void fill_0_57() { page0[0x57]= wrap_INV; }
+  virtual void fill_0_58() { page0[0x58]= wrap_INV; }
+  virtual void fill_0_59() { page0[0x59]= wrap_INV; }
+  virtual void fill_0_5a() { page0[0x5a]= wrap_INV; }
+  virtual void fill_0_5b() { page0[0x5b]= wrap_INV; }
+  virtual void fill_0_5c() { page0[0x5c]= wrap_INV; }
+  virtual void fill_0_5d() { page0[0x5d]= wrap_INV; }
+  virtual void fill_0_5e() { page0[0x5e]= wrap_INV; }
+  virtual void fill_0_5f() { page0[0x5f]= wrap_INV; }
+  virtual void fill_0_60() { page0[0x60]= wrap_INV; }
+  virtual void fill_0_61() { page0[0x61]= wrap_INV; }
+  virtual void fill_0_62() { page0[0x62]= wrap_INV; }
+  virtual void fill_0_63() { page0[0x63]= wrap_INV; }
+  virtual void fill_0_64() { page0[0x64]= wrap_INV; }
+  virtual void fill_0_65() { page0[0x65]= wrap_INV; }
+  virtual void fill_0_66() { page0[0x66]= wrap_INV; }
+  virtual void fill_0_67() { page0[0x67]= wrap_INV; }
+  virtual void fill_0_68() { page0[0x68]= wrap_INV; }
+  virtual void fill_0_69() { page0[0x69]= wrap_INV; }
+  virtual void fill_0_6a() { page0[0x6a]= wrap_INV; }
+  virtual void fill_0_6b() { page0[0x6b]= wrap_INV; }
+  virtual void fill_0_6c() { page0[0x6c]= wrap_INV; }
+  virtual void fill_0_6d() { page0[0x6d]= wrap_INV; }
+  virtual void fill_0_6e() { page0[0x6e]= wrap_INV; }
+  virtual void fill_0_6f() { page0[0x6f]= wrap_INV; }
+  virtual void fill_0_70() { page0[0x70]= wrap_INV; }
+  virtual void fill_0_71() { page0[0x71]= wrap_INV; }
+  virtual void fill_0_72() { page0[0x72]= wrap_INV; }
+  virtual void fill_0_73() { page0[0x73]= wrap_INV; }
+  virtual void fill_0_74() { page0[0x74]= wrap_INV; }
+  virtual void fill_0_75() { page0[0x75]= wrap_INV; }
+  virtual void fill_0_76() { page0[0x76]= wrap_INV; }
+  virtual void fill_0_77() { page0[0x77]= wrap_INV; }
+  virtual void fill_0_78() { page0[0x78]= wrap_INV; }
+  virtual void fill_0_79() { page0[0x79]= wrap_INV; }
+  virtual void fill_0_7a() { page0[0x7a]= wrap_INV; }
+  virtual void fill_0_7b() { page0[0x7b]= wrap_INV; }
+  virtual void fill_0_7c() { page0[0x7c]= wrap_INV; }
+  virtual void fill_0_7d() { page0[0x7d]= wrap_INV; }
+  virtual void fill_0_7e() { page0[0x7e]= wrap_INV; }
+  virtual void fill_0_7f() { page0[0x7f]= wrap_INV; }
+  virtual void fill_0_80() { page0[0x80]= wrap_INV; }
+  virtual void fill_0_81() { page0[0x81]= wrap_INV; }
+  virtual void fill_0_82() { page0[0x82]= wrap_INV; }
+  virtual void fill_0_83() { page0[0x83]= wrap_INV; }
+  virtual void fill_0_84() { page0[0x84]= wrap_INV; }
+  virtual void fill_0_85() { page0[0x85]= wrap_INV; }
+  virtual void fill_0_86() { page0[0x86]= wrap_INV; }
+  virtual void fill_0_87() { page0[0x87]= wrap_INV; }
+  virtual void fill_0_88() { page0[0x88]= wrap_INV; }
+  virtual void fill_0_89() { page0[0x89]= wrap_INV; }
+  virtual void fill_0_8a() { page0[0x8a]= wrap_INV; }
+  virtual void fill_0_8b() { page0[0x8b]= wrap_INV; }
+  virtual void fill_0_8c() { page0[0x8c]= wrap_INV; }
+  virtual void fill_0_8d() { page0[0x8d]= wrap_INV; }
+  virtual void fill_0_8e() { page0[0x8e]= wrap_INV; }
+  virtual void fill_0_8f() { page0[0x8f]= wrap_INV; }
+  virtual void fill_0_90() { page0[0x90]= wrap_INV; }
+  virtual void fill_0_91() { page0[0x91]= wrap_INV; }
+  virtual void fill_0_92() { page0[0x92]= wrap_INV; }
+  virtual void fill_0_93() { page0[0x93]= wrap_INV; }
+  virtual void fill_0_94() { page0[0x94]= wrap_INV; }
+  virtual void fill_0_95() { page0[0x95]= wrap_INV; }
+  virtual void fill_0_96() { page0[0x96]= wrap_INV; }
+  virtual void fill_0_97() { page0[0x97]= wrap_INV; }
+  virtual void fill_0_98() { page0[0x98]= wrap_INV; }
+  virtual void fill_0_99() { page0[0x99]= wrap_INV; }
+  virtual void fill_0_9a() { page0[0x9a]= wrap_INV; }
+  virtual void fill_0_9b() { page0[0x9b]= wrap_INV; }
+  virtual void fill_0_9c() { page0[0x9c]= wrap_INV; }
+  virtual void fill_0_9d() { page0[0x9d]= wrap_INV; }
+  virtual void fill_0_9e() { page0[0x9e]= wrap_INV; }
+  virtual void fill_0_9f() { page0[0x9f]= wrap_INV; }
+  virtual void fill_0_a0() { page0[0xa0]= wrap_INV; }
+  virtual void fill_0_a1() { page0[0xa1]= wrap_INV; }
+  virtual void fill_0_a2() { page0[0xa2]= wrap_INV; }
+  virtual void fill_0_a3() { page0[0xa3]= wrap_INV; }
+  virtual void fill_0_a4() { page0[0xa4]= wrap_INV; }
+  virtual void fill_0_a5() { page0[0xa5]= wrap_INV; }
+  virtual void fill_0_a6() { page0[0xa6]= wrap_INV; }
+  virtual void fill_0_a7() { page0[0xa7]= wrap_INV; }
+  virtual void fill_0_a8() { page0[0xa8]= wrap_INV; }
+  virtual void fill_0_a9() { page0[0xa9]= wrap_INV; }
+  virtual void fill_0_aa() { page0[0xaa]= wrap_INV; }
+  virtual void fill_0_ab() { page0[0xab]= wrap_INV; }
+  virtual void fill_0_ac() { page0[0xac]= wrap_INV; }
+  virtual void fill_0_ad() { page0[0xad]= wrap_INV; }
+  virtual void fill_0_ae() { page0[0xae]= wrap_INV; }
+  virtual void fill_0_af() { page0[0xaf]= wrap_INV; }
+  virtual void fill_0_b0() { page0[0xb0]= wrap_INV; }
+  virtual void fill_0_b1() { page0[0xb1]= wrap_INV; }
+  virtual void fill_0_b2() { page0[0xb2]= wrap_INV; }
+  virtual void fill_0_b3() { page0[0xb3]= wrap_INV; }
+  virtual void fill_0_b4() { page0[0xb4]= wrap_INV; }
+  virtual void fill_0_b5() { page0[0xb5]= wrap_INV; }
+  virtual void fill_0_b6() { page0[0xb6]= wrap_INV; }
+  virtual void fill_0_b7() { page0[0xb7]= wrap_INV; }
+  virtual void fill_0_b8() { page0[0xb8]= wrap_INV; }
+  virtual void fill_0_b9() { page0[0xb9]= wrap_INV; }
+  virtual void fill_0_ba() { page0[0xba]= wrap_INV; }
+  virtual void fill_0_bb() { page0[0xbb]= wrap_INV; }
+  virtual void fill_0_bc() { page0[0xbc]= wrap_INV; }
+  virtual void fill_0_bd() { page0[0xbd]= wrap_INV; }
+  virtual void fill_0_be() { page0[0xbe]= wrap_INV; }
+  virtual void fill_0_bf() { page0[0xbf]= wrap_INV; }
+  virtual void fill_0_c0() { page0[0xc0]= wrap_INV; }
+  virtual void fill_0_c1() { page0[0xc1]= wrap_INV; }
+  virtual void fill_0_c2() { page0[0xc2]= wrap_INV; }
+  virtual void fill_0_c3() { page0[0xc3]= wrap_INV; }
+  virtual void fill_0_c4() { page0[0xc4]= wrap_INV; }
+  virtual void fill_0_c5() { page0[0xc5]= wrap_INV; }
+  virtual void fill_0_c6() { page0[0xc6]= wrap_INV; }
+  virtual void fill_0_c7() { page0[0xc7]= wrap_INV; }
+  virtual void fill_0_c8() { page0[0xc8]= wrap_INV; }
+  virtual void fill_0_c9() { page0[0xc9]= wrap_INV; }
+  virtual void fill_0_ca() { page0[0xca]= wrap_INV; }
+  virtual void fill_0_cb() { page0[0xcb]= wrap_INV; }
+  virtual void fill_0_cc() { page0[0xcc]= wrap_INV; }
+  virtual void fill_0_cd() { page0[0xcd]= wrap_INV; }
+  virtual void fill_0_ce() { page0[0xce]= wrap_INV; }
+  virtual void fill_0_cf() { page0[0xcf]= wrap_INV; }
+  virtual void fill_0_d0() { page0[0xd0]= wrap_INV; }
+  virtual void fill_0_d1() { page0[0xd1]= wrap_INV; }
+  virtual void fill_0_d2() { page0[0xd2]= wrap_INV; }
+  virtual void fill_0_d3() { page0[0xd3]= wrap_INV; }
+  virtual void fill_0_d4() { page0[0xd4]= wrap_INV; }
+  virtual void fill_0_d5() { page0[0xd5]= wrap_INV; }
+  virtual void fill_0_d6() { page0[0xd6]= wrap_INV; }
+  virtual void fill_0_d7() { page0[0xd7]= wrap_INV; }
+  virtual void fill_0_d8() { page0[0xd8]= wrap_INV; }
+  virtual void fill_0_d9() { page0[0xd9]= wrap_INV; }
+  virtual void fill_0_da() { page0[0xda]= wrap_INV; }
+  virtual void fill_0_db() { page0[0xdb]= wrap_INV; }
+  virtual void fill_0_dc() { page0[0xdc]= wrap_INV; }
+  virtual void fill_0_dd() { page0[0xdd]= wrap_INV; }
+  virtual void fill_0_de() { page0[0xde]= wrap_INV; }
+  virtual void fill_0_df() { page0[0xdf]= wrap_INV; }
+  virtual void fill_0_e0() { page0[0xe0]= wrap_INV; }
+  virtual void fill_0_e1() { page0[0xe1]= wrap_INV; }
+  virtual void fill_0_e2() { page0[0xe2]= wrap_INV; }
+  virtual void fill_0_e3() { page0[0xe3]= wrap_INV; }
+  virtual void fill_0_e4() { page0[0xe4]= wrap_INV; }
+  virtual void fill_0_e5() { page0[0xe5]= wrap_INV; }
+  virtual void fill_0_e6() { page0[0xe6]= wrap_INV; }
+  virtual void fill_0_e7() { page0[0xe7]= wrap_INV; }
+  virtual void fill_0_e8() { page0[0xe8]= wrap_INV; }
+  virtual void fill_0_e9() { page0[0xe9]= wrap_INV; }
+  virtual void fill_0_ea() { page0[0xea]= wrap_INV; }
+  virtual void fill_0_eb() { page0[0xeb]= wrap_INV; }
+  virtual void fill_0_ec() { page0[0xec]= wrap_INV; }
+  virtual void fill_0_ed() { page0[0xed]= wrap_INV; }
+  virtual void fill_0_ee() { page0[0xee]= wrap_INV; }
+  virtual void fill_0_ef() { page0[0xef]= wrap_INV; }
+  virtual void fill_0_f0() { page0[0xf0]= wrap_INV; }
+  virtual void fill_0_f1() { page0[0xf1]= wrap_INV; }
+  virtual void fill_0_f2() { page0[0xf2]= wrap_INV; }
+  virtual void fill_0_f3() { page0[0xf3]= wrap_INV; }
+  virtual void fill_0_f4() { page0[0xf4]= wrap_INV; }
+  virtual void fill_0_f5() { page0[0xf5]= wrap_INV; }
+  virtual void fill_0_f6() { page0[0xf6]= wrap_INV; }
+  virtual void fill_0_f7() { page0[0xf7]= wrap_INV; }
+  virtual void fill_0_f8() { page0[0xf8]= wrap_INV; }
+  virtual void fill_0_f9() { page0[0xf9]= wrap_INV; }
+  virtual void fill_0_fa() { page0[0xfa]= wrap_INV; }
+  virtual void fill_0_fb() { page0[0xfb]= wrap_INV; }
+  virtual void fill_0_fc() { page0[0xfc]= wrap_INV; }
+  virtual void fill_0_fd() { page0[0xfd]= wrap_INV; }
+  virtual void fill_0_fe() { page0[0xfe]= wrap_INV; }
+  virtual void fill_0_ff() { page0[0xff]= wrap_INV; }
+
+  virtual void fill_0x18_00() { page0x18[0x00]= wrap_TRAP; }
+  virtual void fill_0x18_01() { page0x18[0x01]= wrap_TRAP; }
+  virtual void fill_0x18_02() { page0x18[0x02]= wrap_TRAP; }
+  virtual void fill_0x18_03() { page0x18[0x03]= wrap_TRAP; }
+  virtual void fill_0x18_04() { page0x18[0x04]= wrap_TRAP; }
+  virtual void fill_0x18_05() { page0x18[0x05]= wrap_TRAP; }
+  virtual void fill_0x18_06() { page0x18[0x06]= wrap_TRAP; }
+  virtual void fill_0x18_07() { page0x18[0x07]= wrap_TRAP; }
+  virtual void fill_0x18_08() { page0x18[0x08]= wrap_TRAP; }
+  virtual void fill_0x18_09() { page0x18[0x09]= wrap_TRAP; }
+  virtual void fill_0x18_0a() { page0x18[0x0a]= wrap_TRAP; }
+  virtual void fill_0x18_0b() { page0x18[0x0b]= wrap_TRAP; }
+  virtual void fill_0x18_0c() { page0x18[0x0c]= wrap_TRAP; }
+  virtual void fill_0x18_0d() { page0x18[0x0d]= wrap_TRAP; }
+  virtual void fill_0x18_0e() { page0x18[0x0e]= wrap_TRAP; }
+  virtual void fill_0x18_0f() { page0x18[0x0f]= wrap_TRAP; }
+  virtual void fill_0x18_10() { page0x18[0x10]= wrap_TRAP; }
+  virtual void fill_0x18_11() { page0x18[0x11]= wrap_TRAP; }
+  virtual void fill_0x18_12() { page0x18[0x12]= wrap_TRAP; }
+  virtual void fill_0x18_13() { page0x18[0x13]= wrap_TRAP; }
+  virtual void fill_0x18_14() { page0x18[0x14]= wrap_TRAP; }
+  virtual void fill_0x18_15() { page0x18[0x15]= wrap_TRAP; }
+  virtual void fill_0x18_16() { page0x18[0x16]= wrap_TRAP; }
+  virtual void fill_0x18_17() { page0x18[0x17]= wrap_TRAP; }
+  virtual void fill_0x18_18() { page0x18[0x18]= wrap_TRAP; }
+  virtual void fill_0x18_19() { page0x18[0x19]= wrap_TRAP; }
+  virtual void fill_0x18_1a() { page0x18[0x1a]= wrap_TRAP; }
+  virtual void fill_0x18_1b() { page0x18[0x1b]= wrap_TRAP; }
+  virtual void fill_0x18_1c() { page0x18[0x1c]= wrap_TRAP; }
+  virtual void fill_0x18_1d() { page0x18[0x1d]= wrap_TRAP; }
+  virtual void fill_0x18_1e() { page0x18[0x1e]= wrap_TRAP; }
+  virtual void fill_0x18_1f() { page0x18[0x1f]= wrap_TRAP; }
+  virtual void fill_0x18_20() { page0x18[0x20]= wrap_TRAP; }
+  virtual void fill_0x18_21() { page0x18[0x21]= wrap_TRAP; }
+  virtual void fill_0x18_22() { page0x18[0x22]= wrap_TRAP; }
+  virtual void fill_0x18_23() { page0x18[0x23]= wrap_TRAP; }
+  virtual void fill_0x18_24() { page0x18[0x24]= wrap_TRAP; }
+  virtual void fill_0x18_25() { page0x18[0x25]= wrap_TRAP; }
+  virtual void fill_0x18_26() { page0x18[0x26]= wrap_TRAP; }
+  virtual void fill_0x18_27() { page0x18[0x27]= wrap_TRAP; }
+  virtual void fill_0x18_28() { page0x18[0x28]= wrap_TRAP; }
+  virtual void fill_0x18_29() { page0x18[0x29]= wrap_TRAP; }
+  virtual void fill_0x18_2a() { page0x18[0x2a]= wrap_TRAP; }
+  virtual void fill_0x18_2b() { page0x18[0x2b]= wrap_TRAP; }
+  virtual void fill_0x18_2c() { page0x18[0x2c]= wrap_TRAP; }
+  virtual void fill_0x18_2d() { page0x18[0x2d]= wrap_TRAP; }
+  virtual void fill_0x18_2e() { page0x18[0x2e]= wrap_TRAP; }
+  virtual void fill_0x18_2f() { page0x18[0x2f]= wrap_TRAP; }
+  virtual void fill_0x18_30() { page0x18[0x30]= wrap_TRAP; }
+  virtual void fill_0x18_31() { page0x18[0x31]= wrap_TRAP; }
+  virtual void fill_0x18_32() { page0x18[0x32]= wrap_TRAP; }
+  virtual void fill_0x18_33() { page0x18[0x33]= wrap_TRAP; }
+  virtual void fill_0x18_34() { page0x18[0x34]= wrap_TRAP; }
+  virtual void fill_0x18_35() { page0x18[0x35]= wrap_TRAP; }
+  virtual void fill_0x18_36() { page0x18[0x36]= wrap_TRAP; }
+  virtual void fill_0x18_37() { page0x18[0x37]= wrap_TRAP; }
+  virtual void fill_0x18_38() { page0x18[0x38]= wrap_TRAP; }
+  virtual void fill_0x18_39() { page0x18[0x39]= wrap_TRAP; }
+  virtual void fill_0x18_3a() { page0x18[0x3a]= wrap_TRAP; }
+  virtual void fill_0x18_3b() { page0x18[0x3b]= wrap_TRAP; }
+  virtual void fill_0x18_3c() { page0x18[0x3c]= wrap_TRAP; }
+  virtual void fill_0x18_3d() { page0x18[0x3d]= wrap_TRAP; }
+  virtual void fill_0x18_3e() { page0x18[0x3e]= wrap_TRAP; }
+  virtual void fill_0x18_3f() { page0x18[0x3f]= wrap_TRAP; }
+  virtual void fill_0x18_40() { page0x18[0x40]= wrap_TRAP; }
+  virtual void fill_0x18_41() { page0x18[0x41]= wrap_TRAP; }
+  virtual void fill_0x18_42() { page0x18[0x42]= wrap_TRAP; }
+  virtual void fill_0x18_43() { page0x18[0x43]= wrap_TRAP; }
+  virtual void fill_0x18_44() { page0x18[0x44]= wrap_TRAP; }
+  virtual void fill_0x18_45() { page0x18[0x45]= wrap_TRAP; }
+  virtual void fill_0x18_46() { page0x18[0x46]= wrap_TRAP; }
+  virtual void fill_0x18_47() { page0x18[0x47]= wrap_TRAP; }
+  virtual void fill_0x18_48() { page0x18[0x48]= wrap_TRAP; }
+  virtual void fill_0x18_49() { page0x18[0x49]= wrap_TRAP; }
+  virtual void fill_0x18_4a() { page0x18[0x4a]= wrap_TRAP; }
+  virtual void fill_0x18_4b() { page0x18[0x4b]= wrap_TRAP; }
+  virtual void fill_0x18_4c() { page0x18[0x4c]= wrap_TRAP; }
+  virtual void fill_0x18_4d() { page0x18[0x4d]= wrap_TRAP; }
+  virtual void fill_0x18_4e() { page0x18[0x4e]= wrap_TRAP; }
+  virtual void fill_0x18_4f() { page0x18[0x4f]= wrap_TRAP; }
+  virtual void fill_0x18_50() { page0x18[0x50]= wrap_TRAP; }
+  virtual void fill_0x18_51() { page0x18[0x51]= wrap_TRAP; }
+  virtual void fill_0x18_52() { page0x18[0x52]= wrap_TRAP; }
+  virtual void fill_0x18_53() { page0x18[0x53]= wrap_TRAP; }
+  virtual void fill_0x18_54() { page0x18[0x54]= wrap_TRAP; }
+  virtual void fill_0x18_55() { page0x18[0x55]= wrap_TRAP; }
+  virtual void fill_0x18_56() { page0x18[0x56]= wrap_TRAP; }
+  virtual void fill_0x18_57() { page0x18[0x57]= wrap_TRAP; }
+  virtual void fill_0x18_58() { page0x18[0x58]= wrap_TRAP; }
+  virtual void fill_0x18_59() { page0x18[0x59]= wrap_TRAP; }
+  virtual void fill_0x18_5a() { page0x18[0x5a]= wrap_TRAP; }
+  virtual void fill_0x18_5b() { page0x18[0x5b]= wrap_TRAP; }
+  virtual void fill_0x18_5c() { page0x18[0x5c]= wrap_TRAP; }
+  virtual void fill_0x18_5d() { page0x18[0x5d]= wrap_TRAP; }
+  virtual void fill_0x18_5e() { page0x18[0x5e]= wrap_TRAP; }
+  virtual void fill_0x18_5f() { page0x18[0x5f]= wrap_TRAP; }
+  virtual void fill_0x18_60() { page0x18[0x60]= wrap_TRAP; }
+  virtual void fill_0x18_61() { page0x18[0x61]= wrap_TRAP; }
+  virtual void fill_0x18_62() { page0x18[0x62]= wrap_TRAP; }
+  virtual void fill_0x18_63() { page0x18[0x63]= wrap_TRAP; }
+  virtual void fill_0x18_64() { page0x18[0x64]= wrap_TRAP; }
+  virtual void fill_0x18_65() { page0x18[0x65]= wrap_TRAP; }
+  virtual void fill_0x18_66() { page0x18[0x66]= wrap_TRAP; }
+  virtual void fill_0x18_67() { page0x18[0x67]= wrap_TRAP; }
+  virtual void fill_0x18_68() { page0x18[0x68]= wrap_TRAP; }
+  virtual void fill_0x18_69() { page0x18[0x69]= wrap_TRAP; }
+  virtual void fill_0x18_6a() { page0x18[0x6a]= wrap_TRAP; }
+  virtual void fill_0x18_6b() { page0x18[0x6b]= wrap_TRAP; }
+  virtual void fill_0x18_6c() { page0x18[0x6c]= wrap_TRAP; }
+  virtual void fill_0x18_6d() { page0x18[0x6d]= wrap_TRAP; }
+  virtual void fill_0x18_6e() { page0x18[0x6e]= wrap_TRAP; }
+  virtual void fill_0x18_6f() { page0x18[0x6f]= wrap_TRAP; }
+  virtual void fill_0x18_70() { page0x18[0x70]= wrap_TRAP; }
+  virtual void fill_0x18_71() { page0x18[0x71]= wrap_TRAP; }
+  virtual void fill_0x18_72() { page0x18[0x72]= wrap_TRAP; }
+  virtual void fill_0x18_73() { page0x18[0x73]= wrap_TRAP; }
+  virtual void fill_0x18_74() { page0x18[0x74]= wrap_TRAP; }
+  virtual void fill_0x18_75() { page0x18[0x75]= wrap_TRAP; }
+  virtual void fill_0x18_76() { page0x18[0x76]= wrap_TRAP; }
+  virtual void fill_0x18_77() { page0x18[0x77]= wrap_TRAP; }
+  virtual void fill_0x18_78() { page0x18[0x78]= wrap_TRAP; }
+  virtual void fill_0x18_79() { page0x18[0x79]= wrap_TRAP; }
+  virtual void fill_0x18_7a() { page0x18[0x7a]= wrap_TRAP; }
+  virtual void fill_0x18_7b() { page0x18[0x7b]= wrap_TRAP; }
+  virtual void fill_0x18_7c() { page0x18[0x7c]= wrap_TRAP; }
+  virtual void fill_0x18_7d() { page0x18[0x7d]= wrap_TRAP; }
+  virtual void fill_0x18_7e() { page0x18[0x7e]= wrap_TRAP; }
+  virtual void fill_0x18_7f() { page0x18[0x7f]= wrap_TRAP; }
+  virtual void fill_0x18_80() { page0x18[0x80]= wrap_TRAP; }
+  virtual void fill_0x18_81() { page0x18[0x81]= wrap_TRAP; }
+  virtual void fill_0x18_82() { page0x18[0x82]= wrap_TRAP; }
+  virtual void fill_0x18_83() { page0x18[0x83]= wrap_TRAP; }
+  virtual void fill_0x18_84() { page0x18[0x84]= wrap_TRAP; }
+  virtual void fill_0x18_85() { page0x18[0x85]= wrap_TRAP; }
+  virtual void fill_0x18_86() { page0x18[0x86]= wrap_TRAP; }
+  virtual void fill_0x18_87() { page0x18[0x87]= wrap_TRAP; }
+  virtual void fill_0x18_88() { page0x18[0x88]= wrap_TRAP; }
+  virtual void fill_0x18_89() { page0x18[0x89]= wrap_TRAP; }
+  virtual void fill_0x18_8a() { page0x18[0x8a]= wrap_TRAP; }
+  virtual void fill_0x18_8b() { page0x18[0x8b]= wrap_TRAP; }
+  virtual void fill_0x18_8c() { page0x18[0x8c]= wrap_TRAP; }
+  virtual void fill_0x18_8d() { page0x18[0x8d]= wrap_TRAP; }
+  virtual void fill_0x18_8e() { page0x18[0x8e]= wrap_TRAP; }
+  virtual void fill_0x18_8f() { page0x18[0x8f]= wrap_TRAP; }
+  virtual void fill_0x18_90() { page0x18[0x90]= wrap_TRAP; }
+  virtual void fill_0x18_91() { page0x18[0x91]= wrap_TRAP; }
+  virtual void fill_0x18_92() { page0x18[0x92]= wrap_TRAP; }
+  virtual void fill_0x18_93() { page0x18[0x93]= wrap_TRAP; }
+  virtual void fill_0x18_94() { page0x18[0x94]= wrap_TRAP; }
+  virtual void fill_0x18_95() { page0x18[0x95]= wrap_TRAP; }
+  virtual void fill_0x18_96() { page0x18[0x96]= wrap_TRAP; }
+  virtual void fill_0x18_97() { page0x18[0x97]= wrap_TRAP; }
+  virtual void fill_0x18_98() { page0x18[0x98]= wrap_TRAP; }
+  virtual void fill_0x18_99() { page0x18[0x99]= wrap_TRAP; }
+  virtual void fill_0x18_9a() { page0x18[0x9a]= wrap_TRAP; }
+  virtual void fill_0x18_9b() { page0x18[0x9b]= wrap_TRAP; }
+  virtual void fill_0x18_9c() { page0x18[0x9c]= wrap_TRAP; }
+  virtual void fill_0x18_9d() { page0x18[0x9d]= wrap_TRAP; }
+  virtual void fill_0x18_9e() { page0x18[0x9e]= wrap_TRAP; }
+  virtual void fill_0x18_9f() { page0x18[0x9f]= wrap_TRAP; }
+  virtual void fill_0x18_a0() { page0x18[0xa0]= wrap_TRAP; }
+  virtual void fill_0x18_a1() { page0x18[0xa1]= wrap_TRAP; }
+  virtual void fill_0x18_a2() { page0x18[0xa2]= wrap_TRAP; }
+  virtual void fill_0x18_a3() { page0x18[0xa3]= wrap_TRAP; }
+  virtual void fill_0x18_a4() { page0x18[0xa4]= wrap_TRAP; }
+  virtual void fill_0x18_a5() { page0x18[0xa5]= wrap_TRAP; }
+  virtual void fill_0x18_a6() { page0x18[0xa6]= wrap_TRAP; }
+  virtual void fill_0x18_a7() { page0x18[0xa7]= wrap_TRAP; }
+  virtual void fill_0x18_a8() { page0x18[0xa8]= wrap_TRAP; }
+  virtual void fill_0x18_a9() { page0x18[0xa9]= wrap_TRAP; }
+  virtual void fill_0x18_aa() { page0x18[0xaa]= wrap_TRAP; }
+  virtual void fill_0x18_ab() { page0x18[0xab]= wrap_TRAP; }
+  virtual void fill_0x18_ac() { page0x18[0xac]= wrap_TRAP; }
+  virtual void fill_0x18_ad() { page0x18[0xad]= wrap_TRAP; }
+  virtual void fill_0x18_ae() { page0x18[0xae]= wrap_TRAP; }
+  virtual void fill_0x18_af() { page0x18[0xaf]= wrap_TRAP; }
+  virtual void fill_0x18_b0() { page0x18[0xb0]= wrap_TRAP; }
+  virtual void fill_0x18_b1() { page0x18[0xb1]= wrap_TRAP; }
+  virtual void fill_0x18_b2() { page0x18[0xb2]= wrap_TRAP; }
+  virtual void fill_0x18_b3() { page0x18[0xb3]= wrap_TRAP; }
+  virtual void fill_0x18_b4() { page0x18[0xb4]= wrap_TRAP; }
+  virtual void fill_0x18_b5() { page0x18[0xb5]= wrap_TRAP; }
+  virtual void fill_0x18_b6() { page0x18[0xb6]= wrap_TRAP; }
+  virtual void fill_0x18_b7() { page0x18[0xb7]= wrap_TRAP; }
+  virtual void fill_0x18_b8() { page0x18[0xb8]= wrap_TRAP; }
+  virtual void fill_0x18_b9() { page0x18[0xb9]= wrap_TRAP; }
+  virtual void fill_0x18_ba() { page0x18[0xba]= wrap_TRAP; }
+  virtual void fill_0x18_bb() { page0x18[0xbb]= wrap_TRAP; }
+  virtual void fill_0x18_bc() { page0x18[0xbc]= wrap_TRAP; }
+  virtual void fill_0x18_bd() { page0x18[0xbd]= wrap_TRAP; }
+  virtual void fill_0x18_be() { page0x18[0xbe]= wrap_TRAP; }
+  virtual void fill_0x18_bf() { page0x18[0xbf]= wrap_TRAP; }
+  virtual void fill_0x18_c0() { page0x18[0xc0]= wrap_TRAP; }
+  virtual void fill_0x18_c1() { page0x18[0xc1]= wrap_TRAP; }
+  virtual void fill_0x18_c2() { page0x18[0xc2]= wrap_TRAP; }
+  virtual void fill_0x18_c3() { page0x18[0xc3]= wrap_TRAP; }
+  virtual void fill_0x18_c4() { page0x18[0xc4]= wrap_TRAP; }
+  virtual void fill_0x18_c5() { page0x18[0xc5]= wrap_TRAP; }
+  virtual void fill_0x18_c6() { page0x18[0xc6]= wrap_TRAP; }
+  virtual void fill_0x18_c7() { page0x18[0xc7]= wrap_TRAP; }
+  virtual void fill_0x18_c8() { page0x18[0xc8]= wrap_TRAP; }
+  virtual void fill_0x18_c9() { page0x18[0xc9]= wrap_TRAP; }
+  virtual void fill_0x18_ca() { page0x18[0xca]= wrap_TRAP; }
+  virtual void fill_0x18_cb() { page0x18[0xcb]= wrap_TRAP; }
+  virtual void fill_0x18_cc() { page0x18[0xcc]= wrap_TRAP; }
+  virtual void fill_0x18_cd() { page0x18[0xcd]= wrap_TRAP; }
+  virtual void fill_0x18_ce() { page0x18[0xce]= wrap_TRAP; }
+  virtual void fill_0x18_cf() { page0x18[0xcf]= wrap_TRAP; }
+  virtual void fill_0x18_d0() { page0x18[0xd0]= wrap_TRAP; }
+  virtual void fill_0x18_d1() { page0x18[0xd1]= wrap_TRAP; }
+  virtual void fill_0x18_d2() { page0x18[0xd2]= wrap_TRAP; }
+  virtual void fill_0x18_d3() { page0x18[0xd3]= wrap_TRAP; }
+  virtual void fill_0x18_d4() { page0x18[0xd4]= wrap_TRAP; }
+  virtual void fill_0x18_d5() { page0x18[0xd5]= wrap_TRAP; }
+  virtual void fill_0x18_d6() { page0x18[0xd6]= wrap_TRAP; }
+  virtual void fill_0x18_d7() { page0x18[0xd7]= wrap_TRAP; }
+  virtual void fill_0x18_d8() { page0x18[0xd8]= wrap_TRAP; }
+  virtual void fill_0x18_d9() { page0x18[0xd9]= wrap_TRAP; }
+  virtual void fill_0x18_da() { page0x18[0xda]= wrap_TRAP; }
+  virtual void fill_0x18_db() { page0x18[0xdb]= wrap_TRAP; }
+  virtual void fill_0x18_dc() { page0x18[0xdc]= wrap_TRAP; }
+  virtual void fill_0x18_dd() { page0x18[0xdd]= wrap_TRAP; }
+  virtual void fill_0x18_de() { page0x18[0xde]= wrap_TRAP; }
+  virtual void fill_0x18_df() { page0x18[0xdf]= wrap_TRAP; }
+  virtual void fill_0x18_e0() { page0x18[0xe0]= wrap_TRAP; }
+  virtual void fill_0x18_e1() { page0x18[0xe1]= wrap_TRAP; }
+  virtual void fill_0x18_e2() { page0x18[0xe2]= wrap_TRAP; }
+  virtual void fill_0x18_e3() { page0x18[0xe3]= wrap_TRAP; }
+  virtual void fill_0x18_e4() { page0x18[0xe4]= wrap_TRAP; }
+  virtual void fill_0x18_e5() { page0x18[0xe5]= wrap_TRAP; }
+  virtual void fill_0x18_e6() { page0x18[0xe6]= wrap_TRAP; }
+  virtual void fill_0x18_e7() { page0x18[0xe7]= wrap_TRAP; }
+  virtual void fill_0x18_e8() { page0x18[0xe8]= wrap_TRAP; }
+  virtual void fill_0x18_e9() { page0x18[0xe9]= wrap_TRAP; }
+  virtual void fill_0x18_ea() { page0x18[0xea]= wrap_TRAP; }
+  virtual void fill_0x18_eb() { page0x18[0xeb]= wrap_TRAP; }
+  virtual void fill_0x18_ec() { page0x18[0xec]= wrap_TRAP; }
+  virtual void fill_0x18_ed() { page0x18[0xed]= wrap_TRAP; }
+  virtual void fill_0x18_ee() { page0x18[0xee]= wrap_TRAP; }
+  virtual void fill_0x18_ef() { page0x18[0xef]= wrap_TRAP; }
+  virtual void fill_0x18_f0() { page0x18[0xf0]= wrap_TRAP; }
+  virtual void fill_0x18_f1() { page0x18[0xf1]= wrap_TRAP; }
+  virtual void fill_0x18_f2() { page0x18[0xf2]= wrap_TRAP; }
+  virtual void fill_0x18_f3() { page0x18[0xf3]= wrap_TRAP; }
+  virtual void fill_0x18_f4() { page0x18[0xf4]= wrap_TRAP; }
+  virtual void fill_0x18_f5() { page0x18[0xf5]= wrap_TRAP; }
+  virtual void fill_0x18_f6() { page0x18[0xf6]= wrap_TRAP; }
+  virtual void fill_0x18_f7() { page0x18[0xf7]= wrap_TRAP; }
+  virtual void fill_0x18_f8() { page0x18[0xf8]= wrap_TRAP; }
+  virtual void fill_0x18_f9() { page0x18[0xf9]= wrap_TRAP; }
+  virtual void fill_0x18_fa() { page0x18[0xfa]= wrap_TRAP; }
+  virtual void fill_0x18_fb() { page0x18[0xfb]= wrap_TRAP; }
+  virtual void fill_0x18_fc() { page0x18[0xfc]= wrap_TRAP; }
+  virtual void fill_0x18_fd() { page0x18[0xfd]= wrap_TRAP; }
+  virtual void fill_0x18_fe() { page0x18[0xfe]= wrap_TRAP; }
+  virtual void fill_0x18_ff() { page0x18[0xff]= wrap_TRAP; }
+};
+
+#include "wdecls.h"
+
+class cl_12wrap: public cl_wrap
+{
+public:
+  cl_12wrap(): cl_wrap() {}
+
+#include "wfills.h"
+};
+
+
+#endif
+
+/* End of m68hc12.src/hcwrap.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m68hc12.src/ialu.cc sdcc-4.2.0+dfsg/sim/ucsim/m68hc12.src/ialu.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/m68hc12.src/ialu.cc	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m68hc12.src/ialu.cc	2022-01-30 11:45:58.000000000 +0000
@@ -0,0 +1,102 @@
+/*
+ * Simulator of microcontrollers (ialu.cc)
+ *
+ * Copyright (C) @@S@@,@@Y@@ Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+
+#include "m68hc12cl.h"
+
+
+int
+CL12::sub16(class cl_cell16 &dest, u16_t op)
+{
+  u8_t f= rF & ~(flagN|flagZ|flagV|flagC);
+  u16_t a= dest.R(), b= op, r;
+  r= a-b;
+  if (r&0x8000) f|= flagN;
+  if (!r) f|= flagZ;
+  if (( (~a&b)|(b&r)|(r&~a) ) & 0x8000) f|= flagC;
+  if (( (a&~b&~r)|(~a&b&r) ) & 0x8000) f|= flagV;
+  dest.W(r);
+  cF.W(f);
+  return resGO;
+}
+
+int
+CL12::add16(class cl_cell16 &dest, u16_t op)
+{
+  u8_t f= rF & ~(flagN|flagZ|flagV|flagC);
+  u16_t a= dest.R(), b= op, r;
+  r= a+b;
+  if (r&0x8000) f|= flagN;
+  if (!r) f|= flagZ;
+  if (( (a&b)|(b&~r)|(~r&a) ) & 0x8000) f|= flagC;
+  if (( (a&b&~r)|(~a&~b&r) ) & 0x8000) f|= flagV;
+  dest.W(r);
+  cF.W(f);
+  return resGO;
+}
+
+int
+CL12::cp16(u16_t op1, u16_t op2)
+{
+  u8_t f= rF & ~(flagN|flagZ|flagV|flagC);
+  u16_t a= op1, b= op2, r;
+  r= a-b;
+  if (r&0x8000) f|= flagN;
+  if (!r) f|= flagZ;
+  if (( (~a&b)|(b&r)|(r&~a) ) & 0x8000) f|= flagC;
+  if (( (a&~b&~r)|(~a&b&r) ) & 0x8000) f|= flagV;
+  cF.W(f);
+  return resGO;
+}
+
+int
+CL12::lsr16(class cl_memory_cell &dest)
+{
+  u16_t op= dest.R(), f= rF & ~(flagN|flagZ|flagV|flagC);
+  if (op&1) f|= flagC|flagV;
+  op>>= 1;
+  dest.W(op);
+  if (!op) f|= flagZ;
+  cCC.W(f);
+  return resGO;
+}
+
+int
+CL12::asl16(class cl_memory_cell &dest)
+{
+  u16_t op= dest.R();
+  u8_t f;
+  f= rF & ~(flagN|flagZ|flagV|flagC);
+  if (op&0x8000) f|= flagC;
+  op<<= 1;
+  dest.W(op);
+  if (!op) f|= flagZ;
+  if (op&0x8000) f|= flagN;
+  if (((f&flagN)?1:0) ^ ((f&flagC)?1:0)) f|= flagV;
+  cCC.W(f);
+  return resGO;
+}
+
+/* End of m68hc12.src/ialu.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m68hc12.src/ibranch.cc sdcc-4.2.0+dfsg/sim/ucsim/m68hc12.src/ibranch.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/m68hc12.src/ibranch.cc	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m68hc12.src/ibranch.cc	2022-02-02 07:13:37.000000000 +0000
@@ -0,0 +1,158 @@
+/*
+ * Simulator of microcontrollers (ibranch.cc)
+ *
+ * Copyright (C) @@S@@,@@Y@@ Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+
+#include "m68hc12cl.h"
+
+int
+CL12::call_e(void)
+{
+  u8_t h, l, p;
+  u16_t a;
+  h= fetch();
+  l= fetch();
+  p= fetch();
+  a= h*256+l;
+
+  h= PC>>8;
+  l= PC&0xff;
+  cSP.W(rSP-1);
+  rom->write(rSP, l);
+  cSP.W(rSP-1);
+  rom->write(rSP, h);
+  cSP.W(rSP-1);
+  rom->write(rSP, cpu12->ppage_read());
+  
+  cpu12->ppage_write(p);
+  PC= a;
+  
+  return resGO;
+}
+
+int
+CL12::call_id(void)
+{
+  u8_t p, xb, h, l;
+  xb= rom->read(PC);
+  u16_t a= naddr(NULL, &p);
+  if (!xb_indirect(xb))
+    p= fetch();
+  
+  h= PC>>8;
+  l= PC&0xff;
+  cSP.W(rSP-1);
+  rom->write(rSP, l);
+  cSP.W(rSP-1);
+  rom->write(rSP, h);
+  cSP.W(rSP-1);
+  rom->write(rSP, cpu12->ppage_read());
+  
+  cpu12->ppage_write(p);
+  PC= a;
+  
+  return resGO;
+}
+
+int
+CL12::brset(class cl_memory_cell &m)
+{
+  u8_t mask= fetch();
+  i8_t r= fetch();
+  if ((~(m.R()) & mask) == 0)
+    {
+      PC+= r;
+      PC&= 0xffff;
+    }
+  return resGO;
+}
+
+int
+CL12::brset_d(void)
+{
+  class cl_memory_cell &m= dir();
+  return brset(m);  
+}
+
+int
+CL12::brset_id(void)
+{
+  class cl_memory_cell &m= xb();
+  return brset(m);
+}
+
+int
+CL12::brset_e(void)
+{
+  class cl_memory_cell &m= ext();
+  return brset(m);
+}
+
+int
+CL12::brclr(class cl_memory_cell &m)
+{
+  u8_t mask= fetch();
+  i8_t r= fetch();
+  if (((m.R()) & mask) == 0)
+    {
+      PC+= r;
+      PC&= 0xffff;
+    }
+  return resGO;
+}
+
+int
+CL12::brclr_d(void)
+{
+  class cl_memory_cell &m= dir();
+  return brclr(m);  
+}
+
+int
+CL12::brclr_id(void)
+{
+  class cl_memory_cell &m= xb();
+  return brclr(m);
+}
+
+int
+CL12::brclr_e(void)
+{
+  class cl_memory_cell &m= ext();
+  return brclr(m);
+}
+
+int
+CL12::branch(t_addr a, bool cond)
+{
+  if (cond)
+    {
+      PC= a&0xffff;
+      extra_ticks+= 2;
+    }
+  return resGO;
+}
+
+
+/* ENd of m68hc12.src/ibranch.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m68hc12.src/imov.cc sdcc-4.2.0+dfsg/sim/ucsim/m68hc12.src/imov.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/m68hc12.src/imov.cc	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m68hc12.src/imov.cc	2022-02-08 09:07:34.000000000 +0000
@@ -0,0 +1,132 @@
+/*
+ * Simulator of microcontrollers (imov.cc)
+ *
+ * Copyright (C) @@S@@,@@Y@@ Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+
+#include "m68hc12cl.h"
+
+
+int
+CL12::exec_b7(void)
+{
+  u8_t pb= fetch();
+  u8_t ls= pb&0x7, ms=(pb>>4)&0x7, ws, wd;
+  class cl_memory_cell *cs, *cd;
+  u16_t src;
+  if (pb & 0x08)
+    return resINV;
+  cs= tex_cells[ms];
+  cd= (ls==3)?(&cTMP2):(tex_cells[ls]);
+  ws= cs->get_width();
+  wd= cd->get_width();
+  src= cs->get();
+  if (!(pb & 0x80))
+    {
+      // transfer
+      if (ws == wd)
+	;
+      else if (ws == 8)
+	{
+	  // 8bit -> 16bit SEX source
+	  src&= 0x00ff;
+	  if (src & 0x80)
+	    src|= 0xff00;
+	}
+      else
+	// 16bit -> 8bit
+	;
+      cd->W(src);
+    }
+  else
+    {
+      // exchange
+      if (ws == wd)
+	{
+	  cs->W(cd->get());
+	  cd->W(src);
+	}
+      else if (ws == 8)
+	{
+	  // 0L <-> 8
+	  src&= 0x00ff;
+	  cs->W(cd->get());
+	  cd->W(src);
+	}
+      else
+	{
+	  // 16 <-> 8
+	  if (ls & 3)
+	    cs->W(0xff00 | (cd->get()));
+	  else
+	    cs->W(cd->get());
+	  cd->W(src);
+	}
+    }
+  return resGO;
+}
+
+int
+CL12::i_psh8(u8_t op)
+{
+  cSP.W(rSP-1);
+  rom->write(rSP, op);
+  vc.wr+= 1;
+  return resGO;
+}
+
+int
+CL12::i_pul8(class cl_memory_cell &dest)
+{
+  u8_t v;
+  v= rom->read(rSP);
+  cSP.W(rSP+1);
+  dest.W(v);
+  vc.rd+= 1;
+  return resGO;
+}
+
+int
+CL12::i_psh16(u16_t op)
+{
+  cSP.W(rSP-1);
+  rom->write(rSP, op);
+  cSP.W(rSP-1);
+  rom->write(rSP, op>>8);
+  vc.wr+= 2;
+  return resGO;
+}
+
+int
+CL12::i_pul16(class cl_memory_cell &dest)
+{
+  u16_t v;
+  v= read_addr(rom, rSP);
+  cSP.W(rSP+2);
+  dest.W(v);
+  vc.rd+= 2;
+  return resGO;
+}
+
+
+/* End of m68hc12.src/imov.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m68hc12.src/m68hc12.cc sdcc-4.2.0+dfsg/sim/ucsim/m68hc12.src/m68hc12.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/m68hc12.src/m68hc12.cc	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m68hc12.src/m68hc12.cc	2022-02-02 07:13:37.000000000 +0000
@@ -0,0 +1,600 @@
+/*
+ * Simulator of microcontrollers (m68hc12.cc)
+ *
+ * Copyright (C) 2020,20 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#include 
+#include 
+#include 
+
+#include "globals.h"
+#include "utils.h"
+
+#include "dregcl.h"
+
+#include "wraps.h"
+#include "hcwrapcl.h"
+#include "glob12.h"
+#include "m68hc12cl.h"
+
+class cl_m68hc12 *uc;
+
+
+/*
+ * CCR
+ */
+
+t_mem
+cl_ccr::write(t_mem val)
+{
+  u8_t act= d();
+  act&= flagX;
+  if (act == 0)
+    val&= ~flagX;
+  return cl_cell8::write(val);
+}
+
+
+/*
+ * M68HC12 processor
+ */
+
+int
+cl_m68hc12::proba(int i, t_mem code)
+{
+  return i;
+}
+
+
+
+cl_m68hc12::cl_m68hc12(class cl_sim *asim):
+  cl_m68hcbase(asim)
+{
+  IRQ_AT	= 0xfff2;
+  XIRQ_AT	= 0xfff4;
+  SWI_AT	= 0xfff6;
+  TRAP_AT	= 0xfff8;
+  COP_AT	= 0xfffa;
+  CMR_AT	= 0xfffc;
+  RESET_AT	= 0xfffe;
+  class cl_ccr c;
+  memcpy((void*)&cCC, (void*)&c, sizeof(class cl_cell8));
+  hc12wrap= new cl_12wrap();
+  hc12wrap->init();
+  extra_ticks= 0;
+}
+
+int
+cl_m68hc12::init(void)
+{
+  int i;
+  
+  cl_m68hcbase::init();
+#define RCV(R) reg_cell_var(&c ## R , &r ## R , "" #R "" , "CPU register " #R "")
+  RCV(TMP2);
+  RCV(TMP3);
+  
+  set_xtal(8000000);
+
+  for (i= 0; i<=255; i++)
+    itab[i]= instruction_wrapper_invalid;
+
+  tex_cells[0]= &cA;
+  tex_cells[1]= &cB;
+  tex_cells[2]= &cCC;
+  tex_cells[3]= &cTMP3;
+  tex_cells[4]= &cD;
+  tex_cells[5]= &cX;
+  tex_cells[6]= &cY;
+  tex_cells[7]= &cSP;
+
+  tex_names[0]= "A";
+  tex_names[1]= "B";
+  tex_names[2]= "CCR";
+  tex_names[3]= "TMP3";
+  tex_names[4]= "D";
+  tex_names[5]= "X";
+  tex_names[6]= "Y";
+  tex_names[7]= "SP";
+  
+  return 0;
+}
+
+
+const char *
+cl_m68hc12::id_string(void)
+{
+  return "M68HC12";
+}
+
+void
+cl_m68hc12::reset(void)
+{
+  cl_m68hcbase::reset();
+  rCC= 0x80;
+  //post_inc_dec= 0;
+}
+
+void
+cl_m68hc12::make_memories(void)
+{
+  class cl_address_space *as;
+  class cl_address_decoder *ad;
+  class cl_memory_chip *chip;
+  
+  rom= as= new cl_address_space("rom", 0, 0x10000, 8);
+  as->init();
+  address_spaces->add(as);
+
+  chip= new cl_chip8("rom_chip", 0x400000, 8);
+  chip->init();
+  memchips->add(chip);
+  ad= new cl_address_decoder(as= rom,
+			     chip, 0, 0xffff, 0);
+  ad->init();
+  as->decoders->add(ad);
+  ad->activate(0);
+}
+
+void
+cl_m68hc12::make_cpu_hw(void)
+{
+  add_hw(cpu12= new cl_hc12_cpu(this));
+  cpu12->init();
+  cpu= cpu12;
+}
+
+int
+CL12::exec_inst(void)
+{
+  int res= resGO;
+  t_mem code;
+  hcwrapper_fn fn= NULL;
+  cI= &cIX;
+  code= fetch();
+  if (code==0x18)
+    {
+      code= fetch();
+      fn= hc12wrap->page0x18[code];
+    }
+  else
+    {
+      fn= hc12wrap->page0[code];
+    }
+  if (fn)
+    fn(this, code);
+  post_inst();
+  if (res != resNOT_DONE)
+    return res;
+
+  inst_unknown(rom->read(instPC));
+  return(res);
+}
+
+void
+CL12::post_inst(void)
+{
+  /*
+  if (post_inc_dec)
+    post_idx_reg->W(post_idx_reg->R() + post_inc_dec);
+  post_inc_dec= 0;
+  */
+  if (extra_ticks)
+    tick(extra_ticks), extra_ticks= 0;
+}
+
+i16_t
+CL12::s8_16(u8_t op)
+{
+  if (op&0x80)
+    return 0xff00 | op;
+  return op;
+}
+
+int
+CL12::xb_type(u8_t p)
+{
+  if ((p & 0x20) == 0)
+    // 1. rr0n nnnn n5,r rr={X,Y,SP,PC}
+    return 1;
+  if ((p&0xe7) == 0xe7)
+    // 6. 111r r111 [D,r] rr={X,Y,SP,PC}
+    return 6;
+  if ((p&0xe7) == 0xe3)
+    // 5. 111r r011 [n16,r] rr={X,Y,SP,PC}
+    return 5;
+  if ((p&0xc0) != 0xc0)
+    // 3. rr1p nnnn n4,+-r+- rr={X,Y,SP}
+    return 3;
+  if ((p&0xe4) == 0xe0)
+    // 2. 111r r0zs n9/16,r rr={X,Y,SP,PC}
+    return 2;
+  // if ((p&0xe4) == 0xe4)
+  // 4. 111r r1aa {A,B,D},r rr={X,Y,SP,PC}
+  return 4;
+}
+
+bool
+CL12::xb_indirect(u8_t p)
+{
+  if ((p & 0x20) == 0) return false;
+  if ((p&0xe7) == 0xe7) return true;
+  if ((p&0xe7) == 0xe3) return true;
+  return false;
+}
+
+t_addr
+CL12::naddr(t_addr *addr /* of xb */, u8_t *pg)
+{
+  u8_t p, h, l, n;
+  i16_t offset= 0;
+  u16_t ival= 0, a= 0;
+  //i8_t post_inc_dec= 0;
+  class cl_cell16 *post_idx_reg= NULL;
+
+  if (addr)
+    {
+      p= rom->read(*addr);
+      (*addr)++;
+    }
+  else
+    p= fetch();
+  
+  switch (xb_type(p))
+    {
+    case 1: // 1. rr0n nnnn n5,r rr={X,Y,SP,PC}
+      switch (p & 0xc0)
+	{
+	case 0x00: ival= rX; break;
+	case 0x40: ival= rY; break;
+	case 0x80: ival= rSP; break;
+	case 0xc0:
+	  if (addr)
+	    ival= (*addr)&0xffff;
+	  else
+	    ival= PC&0xffff;
+	  break;
+	}
+      offset= p&0x1f;
+      if (p&0x10) offset|= 0xffe0;
+      return ival+offset;
+      break;
+      
+    case 6: // 6. 111r r111 [D,r] rr={X,Y,SP,PC}
+      switch (p & 0x18)
+	{
+	case 0x00: ival= rX; break;
+	case 0x10: ival= rY; break;
+	case 0x08: ival= rSP; break;
+	case 0x18:
+	  if (addr)
+	    ival= (*addr)&0xffff;
+	  else
+	    ival= PC&0xffff;
+	  break;
+	}
+      offset= rD;
+      a= ival+offset;
+      if (pg)
+	*pg= rom->read(a+2);
+      return read_addr(rom, a);
+      break;
+  
+    case 5: // 5. 111r r011 [n16,r] rr={X,Y,SP,PC}
+      switch (p & 0x18)
+	{
+	case 0x00: ival= rX; break;
+	case 0x10: ival= rY; break;
+	case 0x08: ival= rSP; break;
+	case 0x18:
+	  if (addr)
+	    ival= (*addr)&0xffff;
+	  else
+	    ival= PC&0xffff;
+	  break;
+	}
+      if (addr)
+	{
+	  h= rom->read(*addr);
+	  (*addr)++;
+	  l= rom->read(*addr);
+	  (*addr)++;
+	}
+      else
+	{
+	  h= fetch();
+	  l= fetch();
+	}
+      offset= h*256+l;
+      a= ival+offset;
+      if (pg)
+	*pg= rom->read(a+2);
+      return read_addr(rom, a);
+      break;
+  
+    case 3: // 3. rr1p nnnn n4,+-r+- rr={X,Y,SP}
+      switch (p & 0xc0)
+	{
+	case 0x00: ival= rX; post_idx_reg= &cX; break;
+	case 0x40: ival= rY; post_idx_reg= &cY; break;
+	case 0x80: ival= rSP; post_idx_reg= &cSP; break;
+	}
+      n= p&0xf;
+      if (n&0x08) n|= 0xf0;
+      if (p&0x10)
+	{
+	  // post +-
+	  if (!addr)
+	    {
+	      //post_inc_dec= n;
+	      post_idx_reg->W(post_idx_reg->R() + n);
+	    }
+	}
+      else
+	{
+	  // pre +-
+	  ival= (post_idx_reg->R() + n);
+	  if (!addr)
+	    post_idx_reg->W(ival);
+	}
+      return ival;
+      break;
+      
+    case 2:  // 2. 111r r0zs n9/16,r rr={X,Y,SP,PC}
+      switch (p & 0x18)
+	{
+	case 0x00: ival= rX; break;
+	case 0x10: ival= rY; break;
+	case 0x08: ival= rSP; break;
+	case 0x18:
+	  if (addr)
+	    ival= (*addr)&0xffff;
+	  else
+	    ival= PC&0xffff;
+	  break;
+	}
+      if ((p&0x02) == 0x00)
+	{
+	  // 9 bit
+	  if (addr)
+	    {
+	      offset= rom->read(*addr);
+	      (*addr)++;
+	    }
+	  else
+	    offset= fetch();
+	  if (p&0x01) offset|= 0xff00;
+	}
+      else
+	{
+	  // 16 bit
+	  if (addr)
+	    {
+	      h= rom->read(*addr);
+	      (*addr)++;
+	      l= rom->read(*addr);
+	      (*addr)++;
+	    }
+	  else
+	    {
+	      h= fetch();
+	      l= fetch();
+	    }
+	  offset= h*256+l;
+	}
+      return ival+offset;
+      break;
+  
+    default: // 4. 111r r1aa {A,B,D},r rr={X,Y,SP,PC}
+      switch (p & 0x18)
+	{
+	case 0x00: ival= rX; break;
+	case 0x10: ival= rY; break;
+	case 0x08: ival= rSP; break;
+	case 0x18:
+	  if (addr)
+	    ival= (*addr)&0xffff;
+	  else
+	    ival= PC&0xffff;
+	  break;
+	}
+      switch (p&0x03)
+	{
+	case 0x00: offset= s8_16(rA); break;
+	case 0x01: offset= s8_16(rB); break;
+	case 0x02: offset= rD; break;
+	}
+      return ival+offset;
+      break;
+    }
+  
+  return a;
+}
+
+u8_t
+CL12::xbop8()
+{
+  u16_t a= naddr(NULL, NULL);
+  return rom->read(a);
+}
+
+u16_t
+CL12::xbop16()
+{
+  u16_t a= naddr(NULL, NULL);
+  u8_t h, l;
+  h= rom->read(a);
+  l= rom->read(a+1);
+  return h*256+l;
+}
+
+class cl_memory_cell &
+CL12::xb(void)
+{
+  t_addr a= naddr(NULL, NULL);
+  class cl_cell8 *c= (class cl_cell8 *)rom->get_cell(a);
+  return *c;
+}
+
+void
+CL12::push_regs(bool inst_part)
+{
+  rom->write(--rSP, PC&0xff);
+  rom->write(--rSP, PC>>8);
+  rom->write(--rSP, rIY&0xff);
+  rom->write(--rSP, rIY>>8);
+  rom->write(--rSP, rIX&0xff);
+  rom->write(--rSP, rIX>>8);
+  rom->write(--rSP, rA);
+  rom->write(--rSP, rB);
+  rom->write(--rSP, rCC);
+}
+
+void
+CL12::pull_regs(bool inst_part)
+{
+  u8_t l, h;
+  rCC= rom->read(rSP++);
+  rB= rom->read(rSP++);
+  rA= rom->read(rSP++);
+  h= rom->read(rSP++);
+  l= rom->read(rSP++);
+  rIX= h*256+l;
+  h= rom->read(rSP++);
+  l= rom->read(rSP++);
+  rIY= h*256+l;
+  h= rom->read(rSP++);
+  l= rom->read(rSP++);
+  PC= h*256+l;
+}
+
+int
+CL12::trap(t_mem code)
+{
+  push_regs(true);
+  PC= read_addr(rom, TRAP_AT);
+  return resGO;
+}
+
+
+void
+cl_m68hc12::print_regs(class cl_console_base *con)
+{
+  con->dd_color("answer");
+  con->dd_printf("A= $%02x %3d %+4d %c  ", rA, rA, (i8_t)rA, isprint(rA)?rA:'.');
+  con->dd_printf("B= $%02x %3d %+4d %c  ", rB, rB, (i8_t)rB, isprint(rB)?rB:'.');
+  con->dd_printf("   D= $%04x %5d %+5d ", rD, rD, (i16_t)rD);
+  con->dd_printf("\n");
+  con->dd_printf("CC= "); con->print_bin(rF, 8);
+  con->dd_printf("                          TMP2= $%04x %5d %+5d",
+		 rTMP2, rTMP2, rTMP2);
+  con->dd_printf("\n");
+  con->dd_printf("    SXHINZVC");
+  con->dd_printf("                          TMP3= $%04x %5d %+5d",
+		 rTMP3, rTMP3, rTMP3);
+  con->dd_printf("\n");
+
+  con->dd_printf("IX= ");
+  rom->dump(0, IX, IX+7, 8, con);
+  con->dd_color("answer");
+  
+  con->dd_printf("IY= ");
+  rom->dump(0, IY, IY+7, 8, con);
+  con->dd_color("answer");
+  
+  con->dd_printf("SP= ");
+  rom->dump(0, SP, SP+7, 8, con);
+  con->dd_color("answer");
+  
+  print_disass(PC, con);
+}
+
+
+/*
+ * CPU peripheral for HC12 cpu
+ */
+
+cl_hc12_cpu::cl_hc12_cpu(class cl_uc *auc):
+  cl_hw(auc, HW_CPU, 0, "cpu")
+{
+  muc= (class cl_m68hc12 *)auc;
+}
+
+int
+cl_hc12_cpu::init(void)
+{
+  class cl_cvar *v;
+  cl_hw::init();
+  
+  ppage= register_cell(muc->rom, 0x0035);
+  dpage= register_cell(muc->rom, 0x0034);
+  epage= register_cell(muc->rom, 0x0036);
+  windef= register_cell(muc->rom, 0x0037);
+
+  uc->vars->add(v= new cl_var("PPAGE", muc->rom, 0x0035,
+			      "Program page register"));
+  v->init();
+  uc->vars->add(v= new cl_var("DPAGE", muc->rom, 0x0034,
+			      "Data page register"));
+  v->init();
+  uc->vars->add(v= new cl_var("EPAGE", muc->rom, 0x0036,
+			      "Extra page register"));
+  v->init();
+  uc->vars->add(v= new cl_var("WINDEF", muc->rom, 0x0037,
+			      "Window definition register"));
+  v->init();
+  return 0;
+}
+
+void
+cl_hc12_cpu::reset(void)
+{
+  ppage->write(0);
+  dpage->write(0);
+  epage->write(0);
+  windef->write(0);
+}
+
+void
+cl_hc12_cpu::print_info(class cl_console_base *con)
+{
+  con->dd_color("answer");
+  con->dd_printf("PPAGE= $%02x\n", ppage->read());
+  con->dd_printf("DPAGE= $%02x\n", dpage->read());
+  con->dd_printf("EPAGE= $%02x\n", epage->read());
+  u8_t w= windef->read();
+  con->dd_printf("PWEN= %d\n", (w&0x40)?1:0);
+  con->dd_printf("DWEN= %d\n", (w&0x80)?1:0);
+  con->dd_printf("EWEN= %d\n", (w&0x20)?1:0);
+}
+
+t_mem
+cl_hc12_cpu::ppage_write(u8_t val)
+{
+  return ppage->write(val);
+}
+
+
+/* End of m68hc12.src/m68hc12.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m68hc12.src/m68hc12cl.h sdcc-4.2.0+dfsg/sim/ucsim/m68hc12.src/m68hc12cl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/m68hc12.src/m68hc12cl.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m68hc12.src/m68hc12cl.h	2022-02-08 09:07:34.000000000 +0000
@@ -0,0 +1,173 @@
+/*
+ * Simulator of microcontrollers (m68hc12cl.h)
+ *
+ * Copyright (C) 2020,20 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef M68HC12CL_HEADER
+#define M68HC12CL_HEADER
+
+#include "uccl.h"
+#include "memcl.h"
+
+#include "m68hc11cl.h"
+
+#define CL12 cl_m68hc12
+
+class CL12;
+class cl_hc12_cpu;
+
+typedef int (*hcwrapper_fn)(class CL12 *uc, t_mem code);
+
+enum {
+  flagS	= 0x80,
+  flagX	= 0x40
+};
+
+#define rTMP2 (TMP2)
+#define rTMP3 (TMP3)
+
+/*
+ * Special handling of CCR
+ */
+
+class cl_ccr: public cl_cell8
+{
+public:
+  virtual t_mem write(t_mem val);
+};
+
+
+/*
+ * Base of M68HC12 processor
+ *
+ * uc -> m6800         -> m68hcbase   -> m68hc12
+ *       A,B,CC,X,SP      D,Y
+ */
+
+class cl_m68hc12: public cl_m68hcbase
+{
+public:
+  //i8_t post_inc_dec;
+  //class cl_cell16 *post_idx_reg;
+  class cl_wrap *hc12wrap;
+  u16_t TMP2, TMP3;
+  class cl_cell16 cTMP2, cTMP3;
+  class cl_memory_cell *tex_cells[8];
+  const char *tex_names[8];
+  u16_t XIRQ_AT, COP_AT, TRAP_AT, CMR_AT;
+  class cl_hc12_cpu *cpu12;
+  int extra_ticks;
+public:
+  cl_m68hc12(class cl_sim *asim);
+  virtual int init(void);
+  virtual const char *id_string(void);
+  virtual void reset(void);
+  virtual void make_memories(void);
+  virtual void setup_ccr(void) {}
+  virtual void make_cpu_hw(void);
+  
+  virtual int proba(int,t_mem);
+  virtual int prob1(int,t_mem) {return 1;}
+
+  virtual struct dis_entry *dis_tbl(void);
+  virtual struct dis_entry *get_dis_entry(t_addr addr);
+  virtual char *disassc(t_addr addr, chars *comment=NULL);
+  virtual void disass_xb(t_addr *addr, chars *work, chars *comment);
+  virtual void disass_b7(t_addr *addr, chars *work, chars *comment);
+  virtual int inst_length(t_addr addr);
+  virtual int longest_inst(void) { return 6; }
+
+  virtual int exec_inst(void);
+  virtual void post_inst(void);
+  virtual i16_t s8_16(u8_t op); // sex 8->16
+  virtual int xb_type(u8_t p);
+  virtual bool xb_indirect(u8_t p);
+  virtual t_addr naddr(t_addr *addr, u8_t *pg);
+  virtual u8_t xbop8();
+  virtual u16_t xbop16();
+  virtual class cl_memory_cell &xb(void);
+  virtual class cl_memory_cell &xbdst(void) { vc.rd++; vc.wr++; return xb(); }
+  virtual t_addr xbaddr(void) { return naddr(NULL, NULL); }
+  virtual void print_regs(class cl_console_base *con);
+
+  virtual void push_regs(bool inst_part);
+  virtual void pull_regs(bool inst_part);
+  virtual int exec_b7(void);
+  virtual int trap(t_mem code);
+
+  // ALU
+  virtual int sub16(class cl_cell16 &dest, u16_t op);
+  virtual int add16(class cl_cell16 &dest, u16_t op);
+  virtual int cp16(u16_t op1, u16_t op2);
+  virtual int lsr16(class cl_memory_cell &dest);
+  virtual int asl16(class cl_memory_cell &dest);
+
+  // MOVE
+#define ld16 ldsx
+  virtual int i_psh8(u8_t op);
+  virtual int i_pul8(class cl_memory_cell &dest);
+  virtual int i_psh16(u16_t op);
+  virtual int i_pul16(class cl_memory_cell &dest);
+  
+  // BRANCH
+  virtual int call_e(void);
+  virtual int call_id(void);
+  virtual int brset(class cl_memory_cell &m);
+  virtual int brset_d(void);
+  virtual int brset_id(void);
+  virtual int brset_e(void);
+  virtual int brclr(class cl_memory_cell &m);
+  virtual int brclr_d(void);
+  virtual int brclr_id(void);
+  virtual int brclr_e(void);
+  virtual int branch(t_addr a, bool cond);
+
+  // OTHER
+  
+};
+
+
+enum hc12cpu_cfg {
+  hc12_cpu_nuof	= 0
+};
+
+class cl_hc12_cpu: public cl_hw
+{
+protected:
+  class cl_m68hc12 *muc;
+  class cl_memory_cell *dpage, *ppage, *epage, *windef;
+public:
+  cl_hc12_cpu(class cl_uc *auc);
+  virtual int init(void);
+  virtual void reset(void);
+  virtual void print_info(class cl_console_base *con);
+  virtual t_mem ppage_write(u8_t val);
+  virtual u8_t ppage_read(void) { return ppage->R(); }
+};
+
+
+#endif
+
+/* End of m68hc12.src/m68hc12cl.h */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m68hc12.src/Makefile.in sdcc-4.2.0+dfsg/sim/ucsim/m68hc12.src/Makefile.in
--- sdcc-4.0.0+dfsg/sim/ucsim/m68hc12.src/Makefile.in	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m68hc12.src/Makefile.in	2022-02-03 14:04:59.000000000 +0000
@@ -0,0 +1,216 @@
+#
+# uCsim m68hc12.src/Makefile
+#
+# (c) Drotos Daniel, Talker Bt. 1997
+#
+
+# tool name
+TN		= m68hc12
+
+STARTYEAR	= 1997
+
+SHELL		= /bin/sh
+CXX		= @CXX@
+CPP		= @CPP@
+CXXCPP		= @CXXCPP@
+RANLIB		= @RANLIB@
+INSTALL		= @INSTALL@
+STRIP		= @STRIP@
+MAKEDEP         = @MAKEDEP@
+
+top_builddir	= @top_builddir@
+top_srcdir	= @top_srcdir@
+
+transform	= @program_transform_name@
+
+DEFS            = $(subs -DHAVE_CONFIG_H,,@DEFS@)
+CPPFLAGS        = @CPPFLAGS@ -I$(srcdir) -I$(top_srcdir) -I$(top_builddir) \
+		  -I$(top_srcdir)/cmd.src -I$(top_srcdir)/sim.src \
+		  -I$(top_srcdir)/gui.src -I$(top_srcdir)/motorola.src \
+		  -I$(top_srcdir)/m6800.src -I$(top_srcdir)/m68hc11.src
+CFLAGS          = @WALL_FLAG@ @CFLAGS@
+CXXFLAGS        = @WALL_FLAG@ @CXXFLAGS@
+LDFLAGS         = @LDFLAGS@
+PICOPT		= @PICOPT@
+SHAREDLIB	= @SHAREDLIB@
+EXEEXT		= @EXEEXT@
+
+LIBS		= -L$(top_builddir) -lm68hc11 -lm6800 -lmotorola -lsim -lucsimutil -lguiucsim -lcmd -lsim @LIBS@
+DL		= @DL@
+dl_ok		= @dl_ok@
+
+prefix          = @prefix@
+exec_prefix     = @exec_prefix@
+bindir          = @bindir@
+libdir          = @libdir@
+datadir         = @datadir@
+datarootdir     = @datarootdir@
+includedir      = @includedir@
+mandir          = @mandir@
+man1dir         = $(mandir)/man1
+man2dir         = $(mandir)/man2
+infodir         = @infodir@
+srcdir          = @srcdir@
+VPATH           = @srcdir@
+
+OBJECTS_SHARED	= sim$(TN).o $(TN).o imov.o ialu.o ibranch.o \
+		  glob.o glob12.o dis.o \
+		  hcwrap.o
+
+OBJECTS_EXE	= s$(TN).o
+OBJECTS		= $(OBJECTS_SHARED) $(OBJECTS_EXE)
+
+# short/long exe and lib name
+SEN		= s$(TN)$(EXEEXT)
+LEN		= ucsim_$(TN)$(EXEEXT)
+SONAME		= libucsim_$(TN).so
+
+enable_dlso	= @enable_dlso@
+dlso_ok		= @dlso_ok@
+
+M68HC12ASM	=
+TEST_OBJ	= 
+
+
+# Compiling entire program or any subproject
+# ------------------------------------------
+all: checkconf otherlibs $(TN).src
+
+
+# Compiling and installing everything and runing test
+# ---------------------------------------------------
+install: all installdirs install_shared_lib
+	$(INSTALL) $(SEN) $(DESTDIR)$(bindir)/$(SEN)
+	$(STRIP) $(DESTDIR)$(bindir)/$(SEN)
+	$(INSTALL) $(LEN) $(DESTDIR)$(bindir)/$(LEN)
+	$(STRIP) $(DESTDIR)$(bindir)/$(LEN)
+
+
+# Deleting all the installed files
+# --------------------------------
+uninstall:
+	rm -f $(DESTDIR)$(bindir)/$(SEN)
+	rm -f $(DESTDIR)$(bindir)/$(LEN)
+	rm -f $(DESTDIR)$(libdir)/$(SONAME)
+
+
+# Performing self-test
+# --------------------
+check: $(TEST_OBJ)
+
+.PHONY:	test baseline
+test:
+	@$(MAKE) --no-print-directory -C test
+
+baseline:
+	@$(MAKE) --no-print-directory -C test baseline
+
+
+# Performing installation test
+# ----------------------------
+installcheck:
+
+
+# Creating installation directories
+# ---------------------------------
+installdirs:
+	test -d $(DESTDIR)$(bindir) || $(INSTALL) -d $(DESTDIR)$(bindir)
+
+
+# Creating dependencies
+# ---------------------
+dep: Makefile.dep
+
+Makefile.dep: $(srcdir)/*.cc $(srcdir)/*.h
+	$(MAKEDEP) $(CPPFLAGS) $(filter %.cc,$^) >Makefile.dep
+
+-include Makefile.dep
+include $(srcdir)/clean.mk
+
+# My rules
+# --------
+.SUFFIXES: .asm .hex
+
+$(TN).src: preped_headers $(SEN) $(LEN) shared_lib
+
+preped_headers: $(srcdir)/wfills.h $(srcdir)/wdecls.h $(srcdir)/wdefs.h
+
+$(srcdir)/wfills.h: $(srcdir)/decode.h $(srcdir)/gen.h
+	gcc -DGEN_F -E $< >$@
+
+#	gcc -E $< |sed '/^#/d'|sed 's/\__NL__/\
+#/g'|grep '^ *virtual' >$@
+
+$(srcdir)/wdecls.h: $(srcdir)/decode.h $(srcdir)/gen.h
+	gcc -DGEN_D -E $< >$@
+
+#	gcc -E $< |sed '/^#/d'|sed 's/__NL__/\
+#/g'|grep '^ *extern' >$@
+
+$(srcdir)/wdefs.h: $(srcdir)/decode.h $(srcdir)/gen.h
+	gcc -DGEN_W -E $< >$@
+
+#	gcc -E $< |sed '/^#/d'|sed 's/__NL__/\
+#/g'|grep '^ *int' >$@
+
+hcwrap.o: $(srcdir)/hcwrap.cc $(srcdir)/hcwrapcl.h $(srcdir)/wfills.h $(srcdir)/wdecls.h $(srcdir)/wdefs.h $(srcdir)/m68hc12cl.h
+
+$(SEN): $(OBJECTS) $(top_builddir)/libcmd.a $(top_builddir)/libguiucsim.a $(top_builddir)/libsim.a $(top_builddir)/libucsimutil.a $(top_builddir)/libmotorola.a $(top_builddir)/libm6800.a $(top_builddir)/libm68hc11.a
+	$(CXX) $(CXXFLAGS) $(LDFLAGS) $(OBJECTS) $(LIBS) -o $@
+
+$(LEN): $(SEN)
+	cp $< $@
+
+ifeq ($(dlso_ok),yes)
+shared_lib: $(top_builddir)/$(SONAME)
+install_shared_lib: shared_lib
+	test -d $(DESTDIR)$(libdir) || $(INSTALL) -d $(DESTDIR)$(libdir)
+	$(INSTALL) $(top_builddir)/$(SONAME) $(DESTDIR)$(libdir)/$(SONAME)
+else
+shared_lib:
+	@$(top_srcdir)/mkecho $(top_builddir) "No $(TN) shared lib made."
+	@$(top_srcdir)/mkecho $(top_builddir) "(SHAREDLIB="$(SHAREDLIB)",dl_ok="$(dl_ok)",enable_dlso="$(enable_dlso)")"
+install_shared_lib:
+endif
+
+$(top_builddir)/$(SONAME): $(OBJECTS_SHARED)
+	$(CXX) -shared $(LDFLAGS) $(OBJECTS_SHARED) -o $@
+
+otherlibs: $(top_builddir)/libcmd.a $(top_builddir)/libguiucsim.a $(top_builddir)/libsim.a $(top_builddir)/libucsimutil.a $(top_builddir)/libmotorola.a $(top_builddir)/libm6800.a $(top_builddir)/libm68hc11.a
+
+$(top_builddir)/libcmd.a:
+	$(MAKE) -C $(top_builddir)/cmd.src all
+
+$(top_builddir)/libguiucsim.a:
+	$(MAKE) -C $(top_builddir)/gui.src checkconf ucsim_lib
+
+$(top_builddir)/libsim.a:
+	$(MAKE) -C $(top_builddir)/sim.src all
+
+$(top_builddir)/libucsimutil.a:
+	$(MAKE) -C $(top_builddir) -f main.mk
+
+$(top_builddir)/libmotorola.a:
+	$(MAKE) -C $(top_builddir)/motorola.src all
+
+$(top_builddir)/libm6800.a:
+	$(MAKE) -C $(top_builddir)/m6800.src m6800lib
+
+$(top_builddir)/libm68hc11.a:
+	$(MAKE) -C $(top_builddir)/m68hc11.src m68hc11lib
+
+.cc.o:
+	$(CXX) $(CXXFLAGS) $(PICOPT) $(CPPFLAGS) $(TARGET_ARCH) -c $< -o $@
+
+.asm.hex:
+	$(M68HC12ASM) -l $< -o $@ -e $<.lst
+
+
+# Remaking configuration
+# ----------------------
+checkconf:
+	@if [ -f $(top_builddir)/devel ]; then\
+	  $(MAKE) -C $(top_builddir) -f conf.mk srcdir="$(srcdir)" top_builddir="$(top_builddir)" freshconf;\
+	fi
+
+# End of m68hc12.src/Makefile.in
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m68hc12.src/simm68hc12.cc sdcc-4.2.0+dfsg/sim/ucsim/m68hc12.src/simm68hc12.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/m68hc12.src/simm68hc12.cc	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m68hc12.src/simm68hc12.cc	2021-06-10 09:43:56.000000000 +0000
@@ -0,0 +1,73 @@
+/*
+ * Simulator of microcontrollers (simm68hc12.cc)
+ *
+ * Copyright (C) 2020,20 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+// local
+#include "glob.h"
+#include "simm68hc12cl.h"
+#include "m68hc12cl.h"
+
+
+cl_simm68hc12::cl_simm68hc12(class cl_app *the_app):
+  cl_sim(the_app)
+{}
+
+class cl_uc *
+cl_simm68hc12::mk_controller(void)
+{
+  int i;
+  const char *typ= 0;
+  class cl_optref type_option(this);
+
+  type_option.init();
+  type_option.use("cpu_type");
+  i= 0;
+  if ((typ= type_option.get_value(typ)) == 0)
+    typ= "HC12";
+  while ((cpus_hc12[i].type_str != NULL) &&
+	 (strcasecmp(typ, cpus_hc12[i].type_str) != 0))
+    i++;
+  if (cpus_hc12[i].type_str == NULL)
+    {
+      fprintf(stderr, "Unknown processor type. "
+	      "Use -H option to see known types.\n");
+      return(NULL);
+    }
+  switch (cpus_hc12[i].type)
+    {
+    case CPU_HC11:
+      return(new cl_m68hc11(this));
+    case CPU_HC12:
+      return(new cl_m68hc12(this));
+    default:
+      fprintf(stderr, "Unknown processor type\n");
+      return NULL;
+    }
+  return(NULL);
+}
+
+
+/* End of m68hc12.src/simm68hc12.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m68hc12.src/simm68hc12cl.h sdcc-4.2.0+dfsg/sim/ucsim/m68hc12.src/simm68hc12cl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/m68hc12.src/simm68hc12cl.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m68hc12.src/simm68hc12cl.h	2021-06-10 09:43:56.000000000 +0000
@@ -0,0 +1,45 @@
+/*
+ * Simulator of microcontrollers (simm68hc12cl.h)
+ *
+ * Copyright (C) 2020,20 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef SIMM68HC12CL_HEADER
+#define SIMM68HC12CL_HEADER
+
+#include "simcl.h"
+
+
+class cl_simm68hc12: public cl_sim
+{
+public:
+  cl_simm68hc12(class cl_app *the_app);
+
+  virtual class cl_uc *mk_controller(void);
+};
+
+
+#endif
+
+/* End of m68hc12.src/simm68hc12cl.h */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m68hc12.src/sm68hc12.cc sdcc-4.2.0+dfsg/sim/ucsim/m68hc12.src/sm68hc12.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/m68hc12.src/sm68hc12.cc	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m68hc12.src/sm68hc12.cc	2021-06-10 09:43:56.000000000 +0000
@@ -0,0 +1,56 @@
+/*
+ * Simulator of microcontrollers (sm68hc12.cc)
+ *
+ * Copyright (C) 2020,20 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+// prj
+#include "globals.h"
+
+// local
+#include "glob.h"
+#include "simm68hc12cl.h"
+
+
+int
+main(int argc, char *argv[])
+{
+  class cl_sim *sim;
+
+  cpus= cpus_hc12;
+  application= new cl_app();
+  application->set_name("sm68hc12");
+  application->init(argc, argv);
+  sim= new cl_simm68hc12(application);
+  if (sim->init())
+    sim->state|= SIM_QUIT;
+  application->set_simulator(sim);
+  //sim->main();
+  application->run();
+  application->done();
+  delete application;
+  return(0);
+}
+
+/* End of m68hc12.src/sm68hc12.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m68hc12.src/test/clean.mk sdcc-4.2.0+dfsg/sim/ucsim/m68hc12.src/test/clean.mk
--- sdcc-4.0.0+dfsg/sim/ucsim/m68hc12.src/test/clean.mk	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m68hc12.src/test/clean.mk	2021-06-10 09:43:56.000000000 +0000
@@ -0,0 +1,5 @@
+clean:
+
+distclean:
+	rm -f Makefile
+	find . -type d -name out -exec rm -rf {} \;
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m68hc12.src/test/config/baseline/HC12 sdcc-4.2.0+dfsg/sim/ucsim/m68hc12.src/test/config/baseline/HC12
--- sdcc-4.0.0+dfsg/sim/ucsim/m68hc12.src/test/config/baseline/HC12	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m68hc12.src/test/config/baseline/HC12	2022-02-08 21:21:05.000000000 +0000
@@ -0,0 +1,32 @@
+uCsim, Copyright (C)  Daniel Drotos.
+uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+This is free software, and you are welcome to redistribute it
+under certain conditions; type `show c' for details.
+Type of microcontroller: M68HC12
+Controller has 10 hardware element(s).
+   on cpu[0]
+   on simif[0]
+  off vcd[0]
+   on dreg[0]
+   on irq[0]
+   on uart[0]
+   on uart[1]
+   on pia[0]
+   on pia[1]
+   on dport[0]
+A= $00   0   +0 .  B= $00   0   +0 .     D= $0000     0    +0 
+CC= 10000000                          TMP2= $0000     0    +0
+    SXHINZVC                          TMP3= $0000     0    +0
+IX= 0x0000 08 70 d4 b2 8a 29 54 48 .p...)TH
+IY= 0x0000 08 70 d4 b2 8a 29 54 48 .p...)TH
+SP= 0x0000 08 70 d4 b2 8a 29 54 48 .p...)TH
+0x6c75  ? 96 4d             LDAA   $004d              ; [$004d]=$d3[0K
+Memory chips:
+  0x000000-0x0000ff      256 variable_storage (32,%08x,0x%02lx)
+  0x000000-0x3fffff  4194304 rom_chip (8,%02x,0x%06lx)
+Address spaces:
+  0x000000-0x0000ff      256 variables (32,%08x,0x%02lx)
+  0x000000-0x00ffff    65536 rom (8,%02x,0x%04lx)
+Address decoders:
+  variables 0x00 0xff -> variable_storage 0x00 activated
+  rom 0x0000 0xffff -> rom_chip 0x000000 activated
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m68hc12.src/test/config/Makefile sdcc-4.2.0+dfsg/sim/ucsim/m68hc12.src/test/config/Makefile
--- sdcc-4.0.0+dfsg/sim/ucsim/m68hc12.src/test/config/Makefile	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m68hc12.src/test/config/Makefile	2021-06-10 09:43:56.000000000 +0000
@@ -0,0 +1,7 @@
+OUTPUTS = $(filter-out Parameter, $(shell $(SIM) -H | sort -u -k2b | cut -d' ' -f1))
+
+$(OUTPUTS):
+	$(call run-sim, -e 'conf; info reg; info mem')
+
+
+include test-lib.mk
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m68hc12.src/test/Makefile.in sdcc-4.2.0+dfsg/sim/ucsim/m68hc12.src/test/Makefile.in
--- sdcc-4.0.0+dfsg/sim/ucsim/m68hc12.src/test/Makefile.in	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m68hc12.src/test/Makefile.in	2021-06-10 09:43:56.000000000 +0000
@@ -0,0 +1,9 @@
+# @configure_input@
+
+srcdir           = @abs_srcdir@
+
+abs_top_builddir = @abs_top_builddir@
+abs_top_srcdir   = @abs_top_srcdir@
+
+
+include $(abs_top_srcdir)/test-target.mk
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m68hc12.src/wdecls.h sdcc-4.2.0+dfsg/sim/ucsim/m68hc12.src/wdecls.h
--- sdcc-4.0.0+dfsg/sim/ucsim/m68hc12.src/wdecls.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m68hc12.src/wdecls.h	2022-02-08 09:07:34.000000000 +0000
@@ -0,0 +1,295 @@
+# 0 "decode.h"
+# 0 ""
+# 0 ""
+# 1 "/usr/include/stdc-predef.h" 1 3 4
+# 0 "" 2
+# 1 "decode.h"
+# 1 "gen.h" 1
+# 2 "decode.h" 2
+
+extern int wrap_0_89 (class CL12 *uc, t_mem code);
+extern int wrap_0_99 (class CL12 *uc, t_mem code);
+extern int wrap_0_a9 (class CL12 *uc, t_mem code);
+extern int wrap_0_b9 (class CL12 *uc, t_mem code);
+
+extern int wrap_0_c9 (class CL12 *uc, t_mem code);
+extern int wrap_0_d9 (class CL12 *uc, t_mem code);
+extern int wrap_0_e9 (class CL12 *uc, t_mem code);
+extern int wrap_0_f9 (class CL12 *uc, t_mem code);
+
+extern int wrap_0_8b (class CL12 *uc, t_mem code);
+extern int wrap_0_9b (class CL12 *uc, t_mem code);
+extern int wrap_0_ab (class CL12 *uc, t_mem code);
+extern int wrap_0_bb (class CL12 *uc, t_mem code);
+
+extern int wrap_0_cb (class CL12 *uc, t_mem code);
+extern int wrap_0_db (class CL12 *uc, t_mem code);
+extern int wrap_0_eb (class CL12 *uc, t_mem code);
+extern int wrap_0_fb (class CL12 *uc, t_mem code);
+
+extern int wrap_0_84 (class CL12 *uc, t_mem code);
+extern int wrap_0_94 (class CL12 *uc, t_mem code);
+extern int wrap_0_a4 (class CL12 *uc, t_mem code);
+extern int wrap_0_b4 (class CL12 *uc, t_mem code);
+
+extern int wrap_0_c4 (class CL12 *uc, t_mem code);
+extern int wrap_0_d4 (class CL12 *uc, t_mem code);
+extern int wrap_0_e4 (class CL12 *uc, t_mem code);
+extern int wrap_0_f4 (class CL12 *uc, t_mem code);
+
+extern int wrap_0_88 (class CL12 *uc, t_mem code);
+extern int wrap_0_98 (class CL12 *uc, t_mem code);
+extern int wrap_0_a8 (class CL12 *uc, t_mem code);
+extern int wrap_0_b8 (class CL12 *uc, t_mem code);
+
+extern int wrap_0_c8 (class CL12 *uc, t_mem code);
+extern int wrap_0_d8 (class CL12 *uc, t_mem code);
+extern int wrap_0_e8 (class CL12 *uc, t_mem code);
+extern int wrap_0_f8 (class CL12 *uc, t_mem code);
+
+extern int wrap_0_8a (class CL12 *uc, t_mem code);
+extern int wrap_0_9a (class CL12 *uc, t_mem code);
+extern int wrap_0_aa (class CL12 *uc, t_mem code);
+extern int wrap_0_ba (class CL12 *uc, t_mem code);
+
+extern int wrap_0_ca (class CL12 *uc, t_mem code);
+extern int wrap_0_da (class CL12 *uc, t_mem code);
+extern int wrap_0_ea (class CL12 *uc, t_mem code);
+extern int wrap_0_fa (class CL12 *uc, t_mem code);
+
+extern int wrap_0_85 (class CL12 *uc, t_mem code);
+extern int wrap_0_95 (class CL12 *uc, t_mem code);
+extern int wrap_0_a5 (class CL12 *uc, t_mem code);
+extern int wrap_0_b5 (class CL12 *uc, t_mem code);
+
+extern int wrap_0_c5 (class CL12 *uc, t_mem code);
+extern int wrap_0_d5 (class CL12 *uc, t_mem code);
+extern int wrap_0_e5 (class CL12 *uc, t_mem code);
+extern int wrap_0_f5 (class CL12 *uc, t_mem code);
+
+extern int wrap_0_81 (class CL12 *uc, t_mem code);
+extern int wrap_0_91 (class CL12 *uc, t_mem code);
+extern int wrap_0_a1 (class CL12 *uc, t_mem code);
+extern int wrap_0_b1 (class CL12 *uc, t_mem code);
+
+extern int wrap_0_c1 (class CL12 *uc, t_mem code);
+extern int wrap_0_d1 (class CL12 *uc, t_mem code);
+extern int wrap_0_e1 (class CL12 *uc, t_mem code);
+extern int wrap_0_f1 (class CL12 *uc, t_mem code);
+
+extern int wrap_0_80 (class CL12 *uc, t_mem code);
+extern int wrap_0_90 (class CL12 *uc, t_mem code);
+extern int wrap_0_a0 (class CL12 *uc, t_mem code);
+extern int wrap_0_b0 (class CL12 *uc, t_mem code);
+
+extern int wrap_0_c0 (class CL12 *uc, t_mem code);
+extern int wrap_0_d0 (class CL12 *uc, t_mem code);
+extern int wrap_0_e0 (class CL12 *uc, t_mem code);
+extern int wrap_0_f0 (class CL12 *uc, t_mem code);
+
+extern int wrap_0_82 (class CL12 *uc, t_mem code);
+extern int wrap_0_92 (class CL12 *uc, t_mem code);
+extern int wrap_0_a2 (class CL12 *uc, t_mem code);
+extern int wrap_0_b2 (class CL12 *uc, t_mem code);
+
+extern int wrap_0_c2 (class CL12 *uc, t_mem code);
+extern int wrap_0_d2 (class CL12 *uc, t_mem code);
+extern int wrap_0_e2 (class CL12 *uc, t_mem code);
+extern int wrap_0_f2 (class CL12 *uc, t_mem code);
+
+extern int wrap_0_86 (class CL12 *uc, t_mem code);
+extern int wrap_0_96 (class CL12 *uc, t_mem code);
+extern int wrap_0_a6 (class CL12 *uc, t_mem code);
+extern int wrap_0_b6 (class CL12 *uc, t_mem code);
+
+extern int wrap_0_c6 (class CL12 *uc, t_mem code);
+extern int wrap_0_d6 (class CL12 *uc, t_mem code);
+extern int wrap_0_e6 (class CL12 *uc, t_mem code);
+extern int wrap_0_f6 (class CL12 *uc, t_mem code);
+
+extern int wrap_0_83 (class CL12 *uc, t_mem code);
+extern int wrap_0_93 (class CL12 *uc, t_mem code);
+extern int wrap_0_a3 (class CL12 *uc, t_mem code);
+extern int wrap_0_b3 (class CL12 *uc, t_mem code);
+
+extern int wrap_0_8c (class CL12 *uc, t_mem code);
+extern int wrap_0_9c (class CL12 *uc, t_mem code);
+extern int wrap_0_ac (class CL12 *uc, t_mem code);
+extern int wrap_0_bc (class CL12 *uc, t_mem code);
+
+extern int wrap_0_8d (class CL12 *uc, t_mem code);
+extern int wrap_0_9d (class CL12 *uc, t_mem code);
+extern int wrap_0_ad (class CL12 *uc, t_mem code);
+extern int wrap_0_bd (class CL12 *uc, t_mem code);
+
+extern int wrap_0_8e (class CL12 *uc, t_mem code);
+extern int wrap_0_9e (class CL12 *uc, t_mem code);
+extern int wrap_0_ae (class CL12 *uc, t_mem code);
+extern int wrap_0_be (class CL12 *uc, t_mem code);
+
+extern int wrap_0_8f (class CL12 *uc, t_mem code);
+extern int wrap_0_9f (class CL12 *uc, t_mem code);
+extern int wrap_0_af (class CL12 *uc, t_mem code);
+extern int wrap_0_bf (class CL12 *uc, t_mem code);
+
+extern int wrap_0_c3 (class CL12 *uc, t_mem code);
+extern int wrap_0_d3 (class CL12 *uc, t_mem code);
+extern int wrap_0_e3 (class CL12 *uc, t_mem code);
+extern int wrap_0_f3 (class CL12 *uc, t_mem code);
+
+extern int wrap_0_cc (class CL12 *uc, t_mem code);
+extern int wrap_0_dc (class CL12 *uc, t_mem code);
+extern int wrap_0_ec (class CL12 *uc, t_mem code);
+extern int wrap_0_fc (class CL12 *uc, t_mem code);
+
+extern int wrap_0_ce (class CL12 *uc, t_mem code);
+extern int wrap_0_de (class CL12 *uc, t_mem code);
+extern int wrap_0_ee (class CL12 *uc, t_mem code);
+extern int wrap_0_fe (class CL12 *uc, t_mem code);
+
+extern int wrap_0_cd (class CL12 *uc, t_mem code);
+extern int wrap_0_dd (class CL12 *uc, t_mem code);
+extern int wrap_0_ed (class CL12 *uc, t_mem code);
+extern int wrap_0_fd (class CL12 *uc, t_mem code);
+
+extern int wrap_0_cf (class CL12 *uc, t_mem code);
+extern int wrap_0_df (class CL12 *uc, t_mem code);
+extern int wrap_0_ef (class CL12 *uc, t_mem code);
+extern int wrap_0_ff (class CL12 *uc, t_mem code);
+
+extern int wrap_0_87 (class CL12 *uc, t_mem code);
+extern int wrap_0_c7 (class CL12 *uc, t_mem code);
+extern int wrap_0_69 (class CL12 *uc, t_mem code);
+extern int wrap_0_79 (class CL12 *uc, t_mem code);
+
+extern int wrap_0_97 (class CL12 *uc, t_mem code);
+extern int wrap_0_d7 (class CL12 *uc, t_mem code);
+extern int wrap_0_e7 (class CL12 *uc, t_mem code);
+extern int wrap_0_f7 (class CL12 *uc, t_mem code);
+
+extern int wrap_0_40 (class CL12 *uc, t_mem code);
+extern int wrap_0_50 (class CL12 *uc, t_mem code);
+extern int wrap_0_60 (class CL12 *uc, t_mem code);
+extern int wrap_0_70 (class CL12 *uc, t_mem code);
+
+extern int wrap_0_41 (class CL12 *uc, t_mem code);
+extern int wrap_0_51 (class CL12 *uc, t_mem code);
+extern int wrap_0_61 (class CL12 *uc, t_mem code);
+extern int wrap_0_71 (class CL12 *uc, t_mem code);
+
+extern int wrap_0_42 (class CL12 *uc, t_mem code);
+extern int wrap_0_52 (class CL12 *uc, t_mem code);
+extern int wrap_0_62 (class CL12 *uc, t_mem code);
+extern int wrap_0_72 (class CL12 *uc, t_mem code);
+
+extern int wrap_0_43 (class CL12 *uc, t_mem code);
+extern int wrap_0_53 (class CL12 *uc, t_mem code);
+extern int wrap_0_63 (class CL12 *uc, t_mem code);
+extern int wrap_0_73 (class CL12 *uc, t_mem code);
+
+extern int wrap_0_44 (class CL12 *uc, t_mem code);
+extern int wrap_0_54 (class CL12 *uc, t_mem code);
+extern int wrap_0_64 (class CL12 *uc, t_mem code);
+extern int wrap_0_74 (class CL12 *uc, t_mem code);
+
+extern int wrap_0_45 (class CL12 *uc, t_mem code);
+extern int wrap_0_55 (class CL12 *uc, t_mem code);
+extern int wrap_0_65 (class CL12 *uc, t_mem code);
+extern int wrap_0_75 (class CL12 *uc, t_mem code);
+
+extern int wrap_0_46 (class CL12 *uc, t_mem code);
+extern int wrap_0_56 (class CL12 *uc, t_mem code);
+extern int wrap_0_66 (class CL12 *uc, t_mem code);
+extern int wrap_0_76 (class CL12 *uc, t_mem code);
+
+extern int wrap_0_47 (class CL12 *uc, t_mem code);
+extern int wrap_0_57 (class CL12 *uc, t_mem code);
+extern int wrap_0_67 (class CL12 *uc, t_mem code);
+extern int wrap_0_77 (class CL12 *uc, t_mem code);
+
+extern int wrap_0_48 (class CL12 *uc, t_mem code);
+extern int wrap_0_58 (class CL12 *uc, t_mem code);
+extern int wrap_0_68 (class CL12 *uc, t_mem code);
+extern int wrap_0_78 (class CL12 *uc, t_mem code);
+
+extern int wrap_0_49 (class CL12 *uc, t_mem code);
+extern int wrap_0_59 (class CL12 *uc, t_mem code);
+
+extern int wrap_0_4a (class CL12 *uc, t_mem code);
+extern int wrap_0_4b (class CL12 *uc, t_mem code);
+
+extern int wrap_0_5a (class CL12 *uc, t_mem code);
+extern int wrap_0_6a (class CL12 *uc, t_mem code);
+extern int wrap_0_7a (class CL12 *uc, t_mem code);
+
+extern int wrap_0_5b (class CL12 *uc, t_mem code);
+extern int wrap_0_6b (class CL12 *uc, t_mem code);
+extern int wrap_0_7b (class CL12 *uc, t_mem code);
+
+extern int wrap_0_5c (class CL12 *uc, t_mem code);
+extern int wrap_0_6c (class CL12 *uc, t_mem code);
+extern int wrap_0_7c (class CL12 *uc, t_mem code);
+
+extern int wrap_0_5e (class CL12 *uc, t_mem code);
+extern int wrap_0_6e (class CL12 *uc, t_mem code);
+extern int wrap_0_7e (class CL12 *uc, t_mem code);
+
+extern int wrap_0_5d (class CL12 *uc, t_mem code);
+extern int wrap_0_6d (class CL12 *uc, t_mem code);
+extern int wrap_0_7d (class CL12 *uc, t_mem code);
+
+extern int wrap_0_5f (class CL12 *uc, t_mem code);
+extern int wrap_0_6f (class CL12 *uc, t_mem code);
+extern int wrap_0_7f (class CL12 *uc, t_mem code);
+
+extern int wrap_0_4c (class CL12 *uc, t_mem code);
+extern int wrap_0_0c (class CL12 *uc, t_mem code);
+extern int wrap_0_1c (class CL12 *uc, t_mem code);
+
+extern int wrap_0_4d (class CL12 *uc, t_mem code);
+extern int wrap_0_0d (class CL12 *uc, t_mem code);
+extern int wrap_0_1d (class CL12 *uc, t_mem code);
+
+extern int wrap_0_4e (class CL12 *uc, t_mem code);
+extern int wrap_0_0e (class CL12 *uc, t_mem code);
+extern int wrap_0_1e (class CL12 *uc, t_mem code);
+
+extern int wrap_0_4f (class CL12 *uc, t_mem code);
+extern int wrap_0_0f (class CL12 *uc, t_mem code);
+extern int wrap_0_1f (class CL12 *uc, t_mem code);
+
+extern int wrap_0_20 (class CL12 *uc, t_mem code);
+extern int wrap_0_21 (class CL12 *uc, t_mem code);
+extern int wrap_0_22 (class CL12 *uc, t_mem code);
+extern int wrap_0_23 (class CL12 *uc, t_mem code);
+extern int wrap_0_24 (class CL12 *uc, t_mem code);
+extern int wrap_0_25 (class CL12 *uc, t_mem code);
+extern int wrap_0_26 (class CL12 *uc, t_mem code);
+extern int wrap_0_27 (class CL12 *uc, t_mem code);
+extern int wrap_0_28 (class CL12 *uc, t_mem code);
+extern int wrap_0_29 (class CL12 *uc, t_mem code);
+extern int wrap_0_2a (class CL12 *uc, t_mem code);
+extern int wrap_0_2b (class CL12 *uc, t_mem code);
+extern int wrap_0_2c (class CL12 *uc, t_mem code);
+extern int wrap_0_2d (class CL12 *uc, t_mem code);
+extern int wrap_0_2e (class CL12 *uc, t_mem code);
+extern int wrap_0_2f (class CL12 *uc, t_mem code);
+
+extern int wrap_0_30 (class CL12 *uc, t_mem code);
+extern int wrap_0_31 (class CL12 *uc, t_mem code);
+extern int wrap_0_32 (class CL12 *uc, t_mem code);
+extern int wrap_0_33 (class CL12 *uc, t_mem code);
+extern int wrap_0_34 (class CL12 *uc, t_mem code);
+extern int wrap_0_35 (class CL12 *uc, t_mem code);
+extern int wrap_0_36 (class CL12 *uc, t_mem code);
+extern int wrap_0_37 (class CL12 *uc, t_mem code);
+extern int wrap_0_38 (class CL12 *uc, t_mem code);
+extern int wrap_0_39 (class CL12 *uc, t_mem code);
+extern int wrap_0_3a (class CL12 *uc, t_mem code);
+extern int wrap_0_3b (class CL12 *uc, t_mem code);
+
+extern int wrap_0_a7 (class CL12 *uc, t_mem code);
+
+extern int wrap_0_b7 (class CL12 *uc, t_mem code);
+
+extern int wrap_0x18_06 (class CL12 *uc, t_mem code);
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m68hc12.src/wdefs.h sdcc-4.2.0+dfsg/sim/ucsim/m68hc12.src/wdefs.h
--- sdcc-4.0.0+dfsg/sim/ucsim/m68hc12.src/wdefs.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m68hc12.src/wdefs.h	2022-02-08 09:07:34.000000000 +0000
@@ -0,0 +1,295 @@
+# 0 "decode.h"
+# 0 ""
+# 0 ""
+# 1 "/usr/include/stdc-predef.h" 1 3 4
+# 0 "" 2
+# 1 "decode.h"
+# 1 "gen.h" 1
+# 2 "decode.h" 2
+
+int wrap_0_89(class CL12 *uc, t_mem code) { return uc-> adc ( _A_i8 ); }
+int wrap_0_99(class CL12 *uc, t_mem code) { return uc-> adc ( _A_dop ); }
+int wrap_0_a9(class CL12 *uc, t_mem code) { return uc-> adc ( _A_xbop8 ); }
+int wrap_0_b9(class CL12 *uc, t_mem code) { return uc-> adc ( _A_eop ); }
+
+int wrap_0_c9(class CL12 *uc, t_mem code) { return uc-> adc ( _B_i8 ); }
+int wrap_0_d9(class CL12 *uc, t_mem code) { return uc-> adc ( _B_dop ); }
+int wrap_0_e9(class CL12 *uc, t_mem code) { return uc-> adc ( _B_xbop8 ); }
+int wrap_0_f9(class CL12 *uc, t_mem code) { return uc-> adc ( _B_eop ); }
+
+int wrap_0_8b(class CL12 *uc, t_mem code) { return uc-> add ( _A_i8 ); }
+int wrap_0_9b(class CL12 *uc, t_mem code) { return uc-> add ( _A_dop ); }
+int wrap_0_ab(class CL12 *uc, t_mem code) { return uc-> add ( _A_xbop8 ); }
+int wrap_0_bb(class CL12 *uc, t_mem code) { return uc-> add ( _A_eop ); }
+
+int wrap_0_cb(class CL12 *uc, t_mem code) { return uc-> add ( _B_i8 ); }
+int wrap_0_db(class CL12 *uc, t_mem code) { return uc-> add ( _B_dop ); }
+int wrap_0_eb(class CL12 *uc, t_mem code) { return uc-> add ( _B_xbop8 ); }
+int wrap_0_fb(class CL12 *uc, t_mem code) { return uc-> add ( _B_eop ); }
+
+int wrap_0_84(class CL12 *uc, t_mem code) { return uc-> And ( _A_i8 ); }
+int wrap_0_94(class CL12 *uc, t_mem code) { return uc-> And ( _A_dop ); }
+int wrap_0_a4(class CL12 *uc, t_mem code) { return uc-> And ( _A_xbop8 ); }
+int wrap_0_b4(class CL12 *uc, t_mem code) { return uc-> And ( _A_eop ); }
+
+int wrap_0_c4(class CL12 *uc, t_mem code) { return uc-> And ( _B_i8 ); }
+int wrap_0_d4(class CL12 *uc, t_mem code) { return uc-> And ( _B_dop ); }
+int wrap_0_e4(class CL12 *uc, t_mem code) { return uc-> And ( _B_xbop8 ); }
+int wrap_0_f4(class CL12 *uc, t_mem code) { return uc-> And ( _B_eop ); }
+
+int wrap_0_88(class CL12 *uc, t_mem code) { return uc-> eor ( _A_i8 ); }
+int wrap_0_98(class CL12 *uc, t_mem code) { return uc-> eor ( _A_dop ); }
+int wrap_0_a8(class CL12 *uc, t_mem code) { return uc-> eor ( _A_xbop8 ); }
+int wrap_0_b8(class CL12 *uc, t_mem code) { return uc-> eor ( _A_eop ); }
+
+int wrap_0_c8(class CL12 *uc, t_mem code) { return uc-> eor ( _B_i8 ); }
+int wrap_0_d8(class CL12 *uc, t_mem code) { return uc-> eor ( _B_dop ); }
+int wrap_0_e8(class CL12 *uc, t_mem code) { return uc-> eor ( _B_xbop8 ); }
+int wrap_0_f8(class CL12 *uc, t_mem code) { return uc-> eor ( _B_eop ); }
+
+int wrap_0_8a(class CL12 *uc, t_mem code) { return uc-> Or ( _A_i8 ); }
+int wrap_0_9a(class CL12 *uc, t_mem code) { return uc-> Or ( _A_dop ); }
+int wrap_0_aa(class CL12 *uc, t_mem code) { return uc-> Or ( _A_xbop8 ); }
+int wrap_0_ba(class CL12 *uc, t_mem code) { return uc-> Or ( _A_eop ); }
+
+int wrap_0_ca(class CL12 *uc, t_mem code) { return uc-> Or ( _B_i8 ); }
+int wrap_0_da(class CL12 *uc, t_mem code) { return uc-> Or ( _B_dop ); }
+int wrap_0_ea(class CL12 *uc, t_mem code) { return uc-> Or ( _B_xbop8 ); }
+int wrap_0_fa(class CL12 *uc, t_mem code) { return uc-> Or ( _B_eop ); }
+
+int wrap_0_85(class CL12 *uc, t_mem code) { return uc-> bit ( _Aop_i8 ); }
+int wrap_0_95(class CL12 *uc, t_mem code) { return uc-> bit ( _Aop_dop ); }
+int wrap_0_a5(class CL12 *uc, t_mem code) { return uc-> bit ( _Aop_xbop8 ); }
+int wrap_0_b5(class CL12 *uc, t_mem code) { return uc-> bit ( _Aop_eop ); }
+
+int wrap_0_c5(class CL12 *uc, t_mem code) { return uc-> bit ( _Bop_i8 ); }
+int wrap_0_d5(class CL12 *uc, t_mem code) { return uc-> bit ( _Bop_dop ); }
+int wrap_0_e5(class CL12 *uc, t_mem code) { return uc-> bit ( _Bop_xbop8 ); }
+int wrap_0_f5(class CL12 *uc, t_mem code) { return uc-> bit ( _Bop_eop ); }
+
+int wrap_0_81(class CL12 *uc, t_mem code) { return uc-> cmp ( _Aop_i8 ); }
+int wrap_0_91(class CL12 *uc, t_mem code) { return uc-> cmp ( _Aop_dop ); }
+int wrap_0_a1(class CL12 *uc, t_mem code) { return uc-> cmp ( _Aop_xbop8 ); }
+int wrap_0_b1(class CL12 *uc, t_mem code) { return uc-> cmp ( _Aop_eop ); }
+
+int wrap_0_c1(class CL12 *uc, t_mem code) { return uc-> cmp ( _Bop_i8 ); }
+int wrap_0_d1(class CL12 *uc, t_mem code) { return uc-> cmp ( _Bop_dop ); }
+int wrap_0_e1(class CL12 *uc, t_mem code) { return uc-> cmp ( _Bop_xbop8 ); }
+int wrap_0_f1(class CL12 *uc, t_mem code) { return uc-> cmp ( _Bop_eop ); }
+
+int wrap_0_80(class CL12 *uc, t_mem code) { return uc-> sub ( _A_i8 ); }
+int wrap_0_90(class CL12 *uc, t_mem code) { return uc-> sub ( _A_dop ); }
+int wrap_0_a0(class CL12 *uc, t_mem code) { return uc-> sub ( _A_xbop8 ); }
+int wrap_0_b0(class CL12 *uc, t_mem code) { return uc-> sub ( _A_eop ); }
+
+int wrap_0_c0(class CL12 *uc, t_mem code) { return uc-> sub ( _B_i8 ); }
+int wrap_0_d0(class CL12 *uc, t_mem code) { return uc-> sub ( _B_dop ); }
+int wrap_0_e0(class CL12 *uc, t_mem code) { return uc-> sub ( _B_xbop8 ); }
+int wrap_0_f0(class CL12 *uc, t_mem code) { return uc-> sub ( _B_eop ); }
+
+int wrap_0_82(class CL12 *uc, t_mem code) { return uc-> sbc ( _A_i8 ); }
+int wrap_0_92(class CL12 *uc, t_mem code) { return uc-> sbc ( _A_dop ); }
+int wrap_0_a2(class CL12 *uc, t_mem code) { return uc-> sbc ( _A_xbop8 ); }
+int wrap_0_b2(class CL12 *uc, t_mem code) { return uc-> sbc ( _A_eop ); }
+
+int wrap_0_c2(class CL12 *uc, t_mem code) { return uc-> sbc ( _B_i8 ); }
+int wrap_0_d2(class CL12 *uc, t_mem code) { return uc-> sbc ( _B_dop ); }
+int wrap_0_e2(class CL12 *uc, t_mem code) { return uc-> sbc ( _B_xbop8 ); }
+int wrap_0_f2(class CL12 *uc, t_mem code) { return uc-> sbc ( _B_eop ); }
+
+int wrap_0_86(class CL12 *uc, t_mem code) { return uc-> lda ( _A_i8 ); }
+int wrap_0_96(class CL12 *uc, t_mem code) { return uc-> lda ( _A_dop ); }
+int wrap_0_a6(class CL12 *uc, t_mem code) { return uc-> lda ( _A_xbop8 ); }
+int wrap_0_b6(class CL12 *uc, t_mem code) { return uc-> lda ( _A_eop ); }
+
+int wrap_0_c6(class CL12 *uc, t_mem code) { return uc-> lda ( _B_i8 ); }
+int wrap_0_d6(class CL12 *uc, t_mem code) { return uc-> lda ( _B_dop ); }
+int wrap_0_e6(class CL12 *uc, t_mem code) { return uc-> lda ( _B_xbop8 ); }
+int wrap_0_f6(class CL12 *uc, t_mem code) { return uc-> lda ( _B_eop ); }
+
+int wrap_0_83(class CL12 *uc, t_mem code) { return uc-> sub16 ( _D_i16 ); }
+int wrap_0_93(class CL12 *uc, t_mem code) { return uc-> sub16 ( _D_dop16 ); }
+int wrap_0_a3(class CL12 *uc, t_mem code) { return uc-> sub16 ( _D_xbop16 ); }
+int wrap_0_b3(class CL12 *uc, t_mem code) { return uc-> sub16 ( _D_eop16 ); }
+
+int wrap_0_8c(class CL12 *uc, t_mem code) { return uc-> cp16 ( _Dop_i16 ); }
+int wrap_0_9c(class CL12 *uc, t_mem code) { return uc-> cp16 ( _Dop_dop16 ); }
+int wrap_0_ac(class CL12 *uc, t_mem code) { return uc-> cp16 ( _Dop_xbop16 ); }
+int wrap_0_bc(class CL12 *uc, t_mem code) { return uc-> cp16 ( _Dop_eop16 ); }
+
+int wrap_0_8d(class CL12 *uc, t_mem code) { return uc-> cp16 ( _Yop_i16 ); }
+int wrap_0_9d(class CL12 *uc, t_mem code) { return uc-> cp16 ( _Yop_dop16 ); }
+int wrap_0_ad(class CL12 *uc, t_mem code) { return uc-> cp16 ( _Yop_xbop16 ); }
+int wrap_0_bd(class CL12 *uc, t_mem code) { return uc-> cp16 ( _Yop_eop16 ); }
+
+int wrap_0_8e(class CL12 *uc, t_mem code) { return uc-> cp16 ( _Xop_i16 ); }
+int wrap_0_9e(class CL12 *uc, t_mem code) { return uc-> cp16 ( _Xop_dop16 ); }
+int wrap_0_ae(class CL12 *uc, t_mem code) { return uc-> cp16 ( _Xop_xbop16 ); }
+int wrap_0_be(class CL12 *uc, t_mem code) { return uc-> cp16 ( _Xop_eop16 ); }
+
+int wrap_0_8f(class CL12 *uc, t_mem code) { return uc-> cp16 ( _Sop_i16 ); }
+int wrap_0_9f(class CL12 *uc, t_mem code) { return uc-> cp16 ( _Sop_dop16 ); }
+int wrap_0_af(class CL12 *uc, t_mem code) { return uc-> cp16 ( _Sop_xbop16 ); }
+int wrap_0_bf(class CL12 *uc, t_mem code) { return uc-> cp16 ( _Sop_eop16 ); }
+
+int wrap_0_c3(class CL12 *uc, t_mem code) { return uc-> add16 ( _D_i16 ); }
+int wrap_0_d3(class CL12 *uc, t_mem code) { return uc-> add16 ( _D_dop16 ); }
+int wrap_0_e3(class CL12 *uc, t_mem code) { return uc-> add16 ( _D_xbop16 ); }
+int wrap_0_f3(class CL12 *uc, t_mem code) { return uc-> add16 ( _D_eop16 ); }
+
+int wrap_0_cc(class CL12 *uc, t_mem code) { return uc-> ld16 ( _D_i16 ); }
+int wrap_0_dc(class CL12 *uc, t_mem code) { return uc-> ld16 ( _D_dop16 ); }
+int wrap_0_ec(class CL12 *uc, t_mem code) { return uc-> ld16 ( _D_xbop16 ); }
+int wrap_0_fc(class CL12 *uc, t_mem code) { return uc-> ld16 ( _D_eop16 ); }
+
+int wrap_0_ce(class CL12 *uc, t_mem code) { return uc-> ld16 ( _X_i16 ); }
+int wrap_0_de(class CL12 *uc, t_mem code) { return uc-> ld16 ( _X_dop16 ); }
+int wrap_0_ee(class CL12 *uc, t_mem code) { return uc-> ld16 ( _X_xbop16 ); }
+int wrap_0_fe(class CL12 *uc, t_mem code) { return uc-> ld16 ( _X_eop16 ); }
+
+int wrap_0_cd(class CL12 *uc, t_mem code) { return uc-> ld16 ( _Y_i16 ); }
+int wrap_0_dd(class CL12 *uc, t_mem code) { return uc-> ld16 ( _Y_dop16 ); }
+int wrap_0_ed(class CL12 *uc, t_mem code) { return uc-> ld16 ( _Y_xbop16 ); }
+int wrap_0_fd(class CL12 *uc, t_mem code) { return uc-> ld16 ( _Y_eop16 ); }
+
+int wrap_0_cf(class CL12 *uc, t_mem code) { return uc-> ld16 ( _S_i16 ); }
+int wrap_0_df(class CL12 *uc, t_mem code) { return uc-> ld16 ( _S_dop16 ); }
+int wrap_0_ef(class CL12 *uc, t_mem code) { return uc-> ld16 ( _S_xbop16 ); }
+int wrap_0_ff(class CL12 *uc, t_mem code) { return uc-> ld16 ( _S_eop16 ); }
+
+int wrap_0_87(class CL12 *uc, t_mem code) { return uc-> clr ( _cA ); }
+int wrap_0_c7(class CL12 *uc, t_mem code) { return uc-> clr ( _cB ); }
+int wrap_0_69(class CL12 *uc, t_mem code) { return uc-> clr ( _xb ); }
+int wrap_0_79(class CL12 *uc, t_mem code) { return uc-> clr ( _e ); }
+
+int wrap_0_97(class CL12 *uc, t_mem code) { return uc-> tst ( _Aop ); }
+int wrap_0_d7(class CL12 *uc, t_mem code) { return uc-> tst ( _Bop ); }
+int wrap_0_e7(class CL12 *uc, t_mem code) { return uc-> tst ( _xbop8 ); }
+int wrap_0_f7(class CL12 *uc, t_mem code) { return uc-> tst ( _eop ); }
+
+int wrap_0_40(class CL12 *uc, t_mem code) { return uc-> neg ( _cA ); }
+int wrap_0_50(class CL12 *uc, t_mem code) { return uc-> neg ( _cB ); }
+int wrap_0_60(class CL12 *uc, t_mem code) { return uc-> neg ( _xb ); }
+int wrap_0_70(class CL12 *uc, t_mem code) { return uc-> neg ( _e ); }
+
+int wrap_0_41(class CL12 *uc, t_mem code) { return uc-> com ( _cA ); }
+int wrap_0_51(class CL12 *uc, t_mem code) { return uc-> com ( _cB ); }
+int wrap_0_61(class CL12 *uc, t_mem code) { return uc-> com ( _xb ); }
+int wrap_0_71(class CL12 *uc, t_mem code) { return uc-> com ( _e ); }
+
+int wrap_0_42(class CL12 *uc, t_mem code) { return uc-> inc ( _cA ); }
+int wrap_0_52(class CL12 *uc, t_mem code) { return uc-> inc ( _cB ); }
+int wrap_0_62(class CL12 *uc, t_mem code) { return uc-> inc ( _xb ); }
+int wrap_0_72(class CL12 *uc, t_mem code) { return uc-> inc ( _e ); }
+
+int wrap_0_43(class CL12 *uc, t_mem code) { return uc-> dec ( _cA ); }
+int wrap_0_53(class CL12 *uc, t_mem code) { return uc-> dec ( _cB ); }
+int wrap_0_63(class CL12 *uc, t_mem code) { return uc-> dec ( _xb ); }
+int wrap_0_73(class CL12 *uc, t_mem code) { return uc-> dec ( _e ); }
+
+int wrap_0_44(class CL12 *uc, t_mem code) { return uc-> lsr ( _cA ); }
+int wrap_0_54(class CL12 *uc, t_mem code) { return uc-> lsr ( _cB ); }
+int wrap_0_64(class CL12 *uc, t_mem code) { return uc-> lsr ( _xb ); }
+int wrap_0_74(class CL12 *uc, t_mem code) { return uc-> lsr ( _e ); }
+
+int wrap_0_45(class CL12 *uc, t_mem code) { return uc-> rol ( _cA ); }
+int wrap_0_55(class CL12 *uc, t_mem code) { return uc-> rol ( _cB ); }
+int wrap_0_65(class CL12 *uc, t_mem code) { return uc-> rol ( _xb ); }
+int wrap_0_75(class CL12 *uc, t_mem code) { return uc-> rol ( _e ); }
+
+int wrap_0_46(class CL12 *uc, t_mem code) { return uc-> ror ( _cA ); }
+int wrap_0_56(class CL12 *uc, t_mem code) { return uc-> ror ( _cB ); }
+int wrap_0_66(class CL12 *uc, t_mem code) { return uc-> ror ( _xb ); }
+int wrap_0_76(class CL12 *uc, t_mem code) { return uc-> ror ( _e ); }
+
+int wrap_0_47(class CL12 *uc, t_mem code) { return uc-> asr ( _cA ); }
+int wrap_0_57(class CL12 *uc, t_mem code) { return uc-> asr ( _cB ); }
+int wrap_0_67(class CL12 *uc, t_mem code) { return uc-> asr ( _xb ); }
+int wrap_0_77(class CL12 *uc, t_mem code) { return uc-> asr ( _e ); }
+
+int wrap_0_48(class CL12 *uc, t_mem code) { return uc-> asl ( _cA ); }
+int wrap_0_58(class CL12 *uc, t_mem code) { return uc-> asl ( _cB ); }
+int wrap_0_68(class CL12 *uc, t_mem code) { return uc-> asl ( _xb ); }
+int wrap_0_78(class CL12 *uc, t_mem code) { return uc-> asl ( _e ); }
+
+int wrap_0_49(class CL12 *uc, t_mem code) { return uc-> lsr16 ( _cD ); }
+int wrap_0_59(class CL12 *uc, t_mem code) { return uc-> asl16 ( _cD ); }
+
+int wrap_0_4a(class CL12 *uc, t_mem code) { return uc-> call_e ( _NONE ); }
+int wrap_0_4b(class CL12 *uc, t_mem code) { return uc-> call_id ( _NONE ); }
+
+int wrap_0_5a(class CL12 *uc, t_mem code) { return uc-> sta ( _d_Aop ); }
+int wrap_0_6a(class CL12 *uc, t_mem code) { return uc-> sta ( _xb_Aop ); }
+int wrap_0_7a(class CL12 *uc, t_mem code) { return uc-> sta ( _e_Aop ); }
+
+int wrap_0_5b(class CL12 *uc, t_mem code) { return uc-> sta ( _d_Bop ); }
+int wrap_0_6b(class CL12 *uc, t_mem code) { return uc-> sta ( _xb_Bop ); }
+int wrap_0_7b(class CL12 *uc, t_mem code) { return uc-> sta ( _e_Bop ); }
+
+int wrap_0_5c(class CL12 *uc, t_mem code) { return uc-> stsx ( _da_Dop ); }
+int wrap_0_6c(class CL12 *uc, t_mem code) { return uc-> stsx ( _xba_Dop ); }
+int wrap_0_7c(class CL12 *uc, t_mem code) { return uc-> stsx ( _ea_Dop ); }
+
+int wrap_0_5e(class CL12 *uc, t_mem code) { return uc-> stsx ( _da_Xop ); }
+int wrap_0_6e(class CL12 *uc, t_mem code) { return uc-> stsx ( _xba_Xop ); }
+int wrap_0_7e(class CL12 *uc, t_mem code) { return uc-> stsx ( _ea_Xop ); }
+
+int wrap_0_5d(class CL12 *uc, t_mem code) { return uc-> stsx ( _da_Yop ); }
+int wrap_0_6d(class CL12 *uc, t_mem code) { return uc-> stsx ( _xba_Yop ); }
+int wrap_0_7d(class CL12 *uc, t_mem code) { return uc-> stsx ( _ea_Yop ); }
+
+int wrap_0_5f(class CL12 *uc, t_mem code) { return uc-> stsx ( _da_Sop ); }
+int wrap_0_6f(class CL12 *uc, t_mem code) { return uc-> stsx ( _xba_Sop ); }
+int wrap_0_7f(class CL12 *uc, t_mem code) { return uc-> stsx ( _ea_Sop ); }
+
+int wrap_0_4c(class CL12 *uc, t_mem code) { return uc-> Or ( _d_i8 ); }
+int wrap_0_0c(class CL12 *uc, t_mem code) { return uc-> Or ( _xb_i8 ); }
+int wrap_0_1c(class CL12 *uc, t_mem code) { return uc-> Or ( _e_i8 ); }
+
+int wrap_0_4d(class CL12 *uc, t_mem code) { return uc-> And ( _d_i8n ); }
+int wrap_0_0d(class CL12 *uc, t_mem code) { return uc-> And ( _xb_i8n ); }
+int wrap_0_1d(class CL12 *uc, t_mem code) { return uc-> And ( _e_i8n ); }
+
+int wrap_0_4e(class CL12 *uc, t_mem code) { return uc-> brset_d ( _NONE ); }
+int wrap_0_0e(class CL12 *uc, t_mem code) { return uc-> brset_id ( _NONE ); }
+int wrap_0_1e(class CL12 *uc, t_mem code) { return uc-> brset_e ( _NONE ); }
+
+int wrap_0_4f(class CL12 *uc, t_mem code) { return uc-> brclr_d ( _NONE ); }
+int wrap_0_0f(class CL12 *uc, t_mem code) { return uc-> brclr_id ( _NONE ); }
+int wrap_0_1f(class CL12 *uc, t_mem code) { return uc-> brclr_e ( _NONE ); }
+
+int wrap_0_20(class CL12 *uc, t_mem code) { return uc-> BRA ( 0x20 ); }
+int wrap_0_21(class CL12 *uc, t_mem code) { return uc-> BRN ( 0x21 ); }
+int wrap_0_22(class CL12 *uc, t_mem code) { return uc-> BHI ( 0x22 ); }
+int wrap_0_23(class CL12 *uc, t_mem code) { return uc-> BLS ( 0x23 ); }
+int wrap_0_24(class CL12 *uc, t_mem code) { return uc-> BCC ( 0x24 ); }
+int wrap_0_25(class CL12 *uc, t_mem code) { return uc-> BCS ( 0x25 ); }
+int wrap_0_26(class CL12 *uc, t_mem code) { return uc-> BNE ( 0x26 ); }
+int wrap_0_27(class CL12 *uc, t_mem code) { return uc-> BEQ ( 0x27 ); }
+int wrap_0_28(class CL12 *uc, t_mem code) { return uc-> BVC ( 0x28 ); }
+int wrap_0_29(class CL12 *uc, t_mem code) { return uc-> BVS ( 0x29 ); }
+int wrap_0_2a(class CL12 *uc, t_mem code) { return uc-> BPL ( 0x2a ); }
+int wrap_0_2b(class CL12 *uc, t_mem code) { return uc-> BMI ( 0x2b ); }
+int wrap_0_2c(class CL12 *uc, t_mem code) { return uc-> BGE ( 0x2c ); }
+int wrap_0_2d(class CL12 *uc, t_mem code) { return uc-> BLT ( 0x2d ); }
+int wrap_0_2e(class CL12 *uc, t_mem code) { return uc-> BGT ( 0x2e ); }
+int wrap_0_2f(class CL12 *uc, t_mem code) { return uc-> BLE ( 0x2f ); }
+
+int wrap_0_30(class CL12 *uc, t_mem code) { return uc-> i_pul16 ( _cX ); }
+int wrap_0_31(class CL12 *uc, t_mem code) { return uc-> i_pul16 ( _cY ); }
+int wrap_0_32(class CL12 *uc, t_mem code) { return uc-> i_pul8 ( _cA ); }
+int wrap_0_33(class CL12 *uc, t_mem code) { return uc-> i_pul8 ( _cB ); }
+int wrap_0_34(class CL12 *uc, t_mem code) { return uc-> i_psh16 ( _Xop ); }
+int wrap_0_35(class CL12 *uc, t_mem code) { return uc-> i_psh16 ( _Yop ); }
+int wrap_0_36(class CL12 *uc, t_mem code) { return uc-> i_psh8 ( _Aop ); }
+int wrap_0_37(class CL12 *uc, t_mem code) { return uc-> i_psh8 ( _Bop ); }
+int wrap_0_38(class CL12 *uc, t_mem code) { return uc-> i_pul8 ( _cC ); }
+int wrap_0_39(class CL12 *uc, t_mem code) { return uc-> i_psh8 ( _Cop ); }
+int wrap_0_3a(class CL12 *uc, t_mem code) { return uc-> i_pul16 ( _cD ); }
+int wrap_0_3b(class CL12 *uc, t_mem code) { return uc-> i_psh16 ( _Dop ); }
+
+int wrap_0_a7(class CL12 *uc, t_mem code) { return uc-> NOP ( 0xa7 ); }
+
+int wrap_0_b7(class CL12 *uc, t_mem code) { return uc-> exec_b7 ( _NONE ); }
+
+int wrap_0x18_06(class CL12 *uc, t_mem code) { return uc-> add ( _A_B ); }
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/m68hc12.src/wfills.h sdcc-4.2.0+dfsg/sim/ucsim/m68hc12.src/wfills.h
--- sdcc-4.0.0+dfsg/sim/ucsim/m68hc12.src/wfills.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/m68hc12.src/wfills.h	2022-02-08 09:07:34.000000000 +0000
@@ -0,0 +1,295 @@
+# 0 "decode.h"
+# 0 ""
+# 0 ""
+# 1 "/usr/include/stdc-predef.h" 1 3 4
+# 0 "" 2
+# 1 "decode.h"
+# 1 "gen.h" 1
+# 2 "decode.h" 2
+
+virtual void fill_0_89() { page0[0x89 ]= wrap_0_89; set_disass(0, 0x89, "ADCA %b", ' ', 2); set_ticks(0, 0x89, 1); }
+virtual void fill_0_99() { page0[0x99 ]= wrap_0_99; set_disass(0, 0x99, "ADCA %d", ' ', 2); set_ticks(0, 0x99, 3); }
+virtual void fill_0_a9() { page0[0xa9 ]= wrap_0_a9; set_disass(0, 0xa9, "ADCA %p", ' ', -2); set_ticks(0, 0xa9, 0x66433); }
+virtual void fill_0_b9() { page0[0xb9 ]= wrap_0_b9; set_disass(0, 0xb9, "ADCA %e", ' ', 3); set_ticks(0, 0xb9, 3); }
+
+virtual void fill_0_c9() { page0[0xc9 ]= wrap_0_c9; set_disass(0, 0xc9, "ADCB %b", ' ', 2); set_ticks(0, 0xc9, 1); }
+virtual void fill_0_d9() { page0[0xd9 ]= wrap_0_d9; set_disass(0, 0xd9, "ADCB %d", ' ', 2); set_ticks(0, 0xd9, 3); }
+virtual void fill_0_e9() { page0[0xe9 ]= wrap_0_e9; set_disass(0, 0xe9, "ADCB %p", ' ', -2); set_ticks(0, 0xe9, 0x66433); }
+virtual void fill_0_f9() { page0[0xf9 ]= wrap_0_f9; set_disass(0, 0xf9, "ADCB %e", ' ', 3); set_ticks(0, 0xf9, 3); }
+
+virtual void fill_0_8b() { page0[0x8b ]= wrap_0_8b; set_disass(0, 0x8b, "ADDA %b", ' ', 2); set_ticks(0, 0x8b, 1); }
+virtual void fill_0_9b() { page0[0x9b ]= wrap_0_9b; set_disass(0, 0x9b, "ADDA %d", ' ', 2); set_ticks(0, 0x9b, 3); }
+virtual void fill_0_ab() { page0[0xab ]= wrap_0_ab; set_disass(0, 0xab, "ADDA %p", ' ', -2); set_ticks(0, 0xab, 0x66433); }
+virtual void fill_0_bb() { page0[0xbb ]= wrap_0_bb; set_disass(0, 0xbb, "ADDA %e", ' ', 3); set_ticks(0, 0xbb, 3); }
+
+virtual void fill_0_cb() { page0[0xcb ]= wrap_0_cb; set_disass(0, 0xcb, "ADDB %b", ' ', 2); set_ticks(0, 0xcb, 1); }
+virtual void fill_0_db() { page0[0xdb ]= wrap_0_db; set_disass(0, 0xdb, "ADDB %d", ' ', 2); set_ticks(0, 0xdb, 3); }
+virtual void fill_0_eb() { page0[0xeb ]= wrap_0_eb; set_disass(0, 0xeb, "ADDB %p", ' ', -2); set_ticks(0, 0xeb, 0x66433); }
+virtual void fill_0_fb() { page0[0xfb ]= wrap_0_fb; set_disass(0, 0xfb, "ADDB %e", ' ', 3); set_ticks(0, 0xfb, 3); }
+
+virtual void fill_0_84() { page0[0x84 ]= wrap_0_84; set_disass(0, 0x84, "ANDA %b", ' ', 2); set_ticks(0, 0x84, 1); }
+virtual void fill_0_94() { page0[0x94 ]= wrap_0_94; set_disass(0, 0x94, "ANDA %d", ' ', 2); set_ticks(0, 0x94, 3); }
+virtual void fill_0_a4() { page0[0xa4 ]= wrap_0_a4; set_disass(0, 0xa4, "ANDA %p", ' ', -2); set_ticks(0, 0xa4, 0x66433); }
+virtual void fill_0_b4() { page0[0xb4 ]= wrap_0_b4; set_disass(0, 0xb4, "ANDA %e", ' ', 3); set_ticks(0, 0xb4, 3); }
+
+virtual void fill_0_c4() { page0[0xc4 ]= wrap_0_c4; set_disass(0, 0xc4, "ANDB %b", ' ', 2); set_ticks(0, 0xc4, 1); }
+virtual void fill_0_d4() { page0[0xd4 ]= wrap_0_d4; set_disass(0, 0xd4, "ANDB %d", ' ', 2); set_ticks(0, 0xd4, 3); }
+virtual void fill_0_e4() { page0[0xe4 ]= wrap_0_e4; set_disass(0, 0xe4, "ANDB %p", ' ', -2); set_ticks(0, 0xe4, 0x66433); }
+virtual void fill_0_f4() { page0[0xf4 ]= wrap_0_f4; set_disass(0, 0xf4, "ANDB %e", ' ', 3); set_ticks(0, 0xf4, 3); }
+
+virtual void fill_0_88() { page0[0x88 ]= wrap_0_88; set_disass(0, 0x88, "EORA %b", ' ', 2); set_ticks(0, 0x88, 1); }
+virtual void fill_0_98() { page0[0x98 ]= wrap_0_98; set_disass(0, 0x98, "EORA %d", ' ', 2); set_ticks(0, 0x98, 3); }
+virtual void fill_0_a8() { page0[0xa8 ]= wrap_0_a8; set_disass(0, 0xa8, "EORA %p", ' ', -2); set_ticks(0, 0xa8, 0x66433); }
+virtual void fill_0_b8() { page0[0xb8 ]= wrap_0_b8; set_disass(0, 0xb8, "EORA %e", ' ', 3); set_ticks(0, 0xb8, 3); }
+
+virtual void fill_0_c8() { page0[0xc8 ]= wrap_0_c8; set_disass(0, 0xc8, "EORB %b", ' ', 2); set_ticks(0, 0xc8, 1); }
+virtual void fill_0_d8() { page0[0xd8 ]= wrap_0_d8; set_disass(0, 0xd8, "EORB %d", ' ', 2); set_ticks(0, 0xd8, 3); }
+virtual void fill_0_e8() { page0[0xe8 ]= wrap_0_e8; set_disass(0, 0xe8, "EORB %p", ' ', -2); set_ticks(0, 0xe8, 0x66433); }
+virtual void fill_0_f8() { page0[0xf8 ]= wrap_0_f8; set_disass(0, 0xf8, "EORB %e", ' ', 3); set_ticks(0, 0xf8, 3); }
+
+virtual void fill_0_8a() { page0[0x8a ]= wrap_0_8a; set_disass(0, 0x8a, "ORAA %b", ' ', 2); set_ticks(0, 0x8a, 1); }
+virtual void fill_0_9a() { page0[0x9a ]= wrap_0_9a; set_disass(0, 0x9a, "ORAA %d", ' ', 2); set_ticks(0, 0x9a, 3); }
+virtual void fill_0_aa() { page0[0xaa ]= wrap_0_aa; set_disass(0, 0xaa, "ORAA %p", ' ', -2); set_ticks(0, 0xaa, 0x66433); }
+virtual void fill_0_ba() { page0[0xba ]= wrap_0_ba; set_disass(0, 0xba, "ORAA %e", ' ', 3); set_ticks(0, 0xba, 3); }
+
+virtual void fill_0_ca() { page0[0xca ]= wrap_0_ca; set_disass(0, 0xca, "ORAB %b", ' ', 2); set_ticks(0, 0xca, 1); }
+virtual void fill_0_da() { page0[0xda ]= wrap_0_da; set_disass(0, 0xda, "ORAB %d", ' ', 2); set_ticks(0, 0xda, 3); }
+virtual void fill_0_ea() { page0[0xea ]= wrap_0_ea; set_disass(0, 0xea, "ORAB %p", ' ', -2); set_ticks(0, 0xea, 0x66433); }
+virtual void fill_0_fa() { page0[0xfa ]= wrap_0_fa; set_disass(0, 0xfa, "ORAB %e", ' ', 3); set_ticks(0, 0xfa, 3); }
+
+virtual void fill_0_85() { page0[0x85 ]= wrap_0_85; set_disass(0, 0x85, "BITA %b", ' ', 2); set_ticks(0, 0x85, 1); }
+virtual void fill_0_95() { page0[0x95 ]= wrap_0_95; set_disass(0, 0x95, "BITA %d", ' ', 2); set_ticks(0, 0x95, 3); }
+virtual void fill_0_a5() { page0[0xa5 ]= wrap_0_a5; set_disass(0, 0xa5, "BITA %p", ' ', -2); set_ticks(0, 0xa5, 0x66433); }
+virtual void fill_0_b5() { page0[0xb5 ]= wrap_0_b5; set_disass(0, 0xb5, "BITA %e", ' ', 3); set_ticks(0, 0xb5, 3); }
+
+virtual void fill_0_c5() { page0[0xc5 ]= wrap_0_c5; set_disass(0, 0xc5, "BITB %b", ' ', 2); set_ticks(0, 0xc5, 1); }
+virtual void fill_0_d5() { page0[0xd5 ]= wrap_0_d5; set_disass(0, 0xd5, "BITB %d", ' ', 2); set_ticks(0, 0xd5, 3); }
+virtual void fill_0_e5() { page0[0xe5 ]= wrap_0_e5; set_disass(0, 0xe5, "BITB %p", ' ', -2); set_ticks(0, 0xe5, 0x66433); }
+virtual void fill_0_f5() { page0[0xf5 ]= wrap_0_f5; set_disass(0, 0xf5, "BITB %e", ' ', 3); set_ticks(0, 0xf5, 3); }
+
+virtual void fill_0_81() { page0[0x81 ]= wrap_0_81; set_disass(0, 0x81, "CMPA %b", ' ', 2); set_ticks(0, 0x81, 1); }
+virtual void fill_0_91() { page0[0x91 ]= wrap_0_91; set_disass(0, 0x91, "CMPA %d", ' ', 2); set_ticks(0, 0x91, 3); }
+virtual void fill_0_a1() { page0[0xa1 ]= wrap_0_a1; set_disass(0, 0xa1, "CMPA %p", ' ', -2); set_ticks(0, 0xa1, 0x66433); }
+virtual void fill_0_b1() { page0[0xb1 ]= wrap_0_b1; set_disass(0, 0xb1, "CMPA %e", ' ', 3); set_ticks(0, 0xb1, 3); }
+
+virtual void fill_0_c1() { page0[0xc1 ]= wrap_0_c1; set_disass(0, 0xc1, "CMPB %b", ' ', 2); set_ticks(0, 0xc1, 1); }
+virtual void fill_0_d1() { page0[0xd1 ]= wrap_0_d1; set_disass(0, 0xd1, "CMPB %d", ' ', 2); set_ticks(0, 0xd1, 3); }
+virtual void fill_0_e1() { page0[0xe1 ]= wrap_0_e1; set_disass(0, 0xe1, "CMPB %p", ' ', -2); set_ticks(0, 0xe1, 0x66433); }
+virtual void fill_0_f1() { page0[0xf1 ]= wrap_0_f1; set_disass(0, 0xf1, "CMPB %e", ' ', 3); set_ticks(0, 0xf1, 3); }
+
+virtual void fill_0_80() { page0[0x80 ]= wrap_0_80; set_disass(0, 0x80, "SUBA %b", ' ', 2); set_ticks(0, 0x80, 1); }
+virtual void fill_0_90() { page0[0x90 ]= wrap_0_90; set_disass(0, 0x90, "SUBA %d", ' ', 2); set_ticks(0, 0x90, 3); }
+virtual void fill_0_a0() { page0[0xa0 ]= wrap_0_a0; set_disass(0, 0xa0, "SUBA %p", ' ', -2); set_ticks(0, 0xa0, 0x66433); }
+virtual void fill_0_b0() { page0[0xb0 ]= wrap_0_b0; set_disass(0, 0xb0, "SUBA %e", ' ', 3); set_ticks(0, 0xb0, 3); }
+
+virtual void fill_0_c0() { page0[0xc0 ]= wrap_0_c0; set_disass(0, 0xc0, "SUBB %b", ' ', 2); set_ticks(0, 0xc0, 1); }
+virtual void fill_0_d0() { page0[0xd0 ]= wrap_0_d0; set_disass(0, 0xd0, "SUBB %d", ' ', 2); set_ticks(0, 0xd0, 3); }
+virtual void fill_0_e0() { page0[0xe0 ]= wrap_0_e0; set_disass(0, 0xe0, "SUBB %p", ' ', -2); set_ticks(0, 0xe0, 0x66433); }
+virtual void fill_0_f0() { page0[0xf0 ]= wrap_0_f0; set_disass(0, 0xf0, "SUBB %e", ' ', 3); set_ticks(0, 0xf0, 3); }
+
+virtual void fill_0_82() { page0[0x82 ]= wrap_0_82; set_disass(0, 0x82, "SBCA %b", ' ', 2); set_ticks(0, 0x82, 1); }
+virtual void fill_0_92() { page0[0x92 ]= wrap_0_92; set_disass(0, 0x92, "SBCA %d", ' ', 2); set_ticks(0, 0x92, 3); }
+virtual void fill_0_a2() { page0[0xa2 ]= wrap_0_a2; set_disass(0, 0xa2, "SBCA %p", ' ', -2); set_ticks(0, 0xa2, 0x66433); }
+virtual void fill_0_b2() { page0[0xb2 ]= wrap_0_b2; set_disass(0, 0xb2, "SBCA %e", ' ', 3); set_ticks(0, 0xb2, 3); }
+
+virtual void fill_0_c2() { page0[0xc2 ]= wrap_0_c2; set_disass(0, 0xc2, "SBCB %b", ' ', 2); set_ticks(0, 0xc2, 1); }
+virtual void fill_0_d2() { page0[0xd2 ]= wrap_0_d2; set_disass(0, 0xd2, "SBCB %d", ' ', 2); set_ticks(0, 0xd2, 3); }
+virtual void fill_0_e2() { page0[0xe2 ]= wrap_0_e2; set_disass(0, 0xe2, "SBCB %p", ' ', -2); set_ticks(0, 0xe2, 0x66433); }
+virtual void fill_0_f2() { page0[0xf2 ]= wrap_0_f2; set_disass(0, 0xf2, "SBCB %e", ' ', 3); set_ticks(0, 0xf2, 3); }
+
+virtual void fill_0_86() { page0[0x86 ]= wrap_0_86; set_disass(0, 0x86, "LDAA %b", ' ', 2); set_ticks(0, 0x86, 1); }
+virtual void fill_0_96() { page0[0x96 ]= wrap_0_96; set_disass(0, 0x96, "LDAA %d", ' ', 2); set_ticks(0, 0x96, 3); }
+virtual void fill_0_a6() { page0[0xa6 ]= wrap_0_a6; set_disass(0, 0xa6, "LDAA %p", ' ', -2); set_ticks(0, 0xa6, 0x66433); }
+virtual void fill_0_b6() { page0[0xb6 ]= wrap_0_b6; set_disass(0, 0xb6, "LDAA %e", ' ', 3); set_ticks(0, 0xb6, 3); }
+
+virtual void fill_0_c6() { page0[0xc6 ]= wrap_0_c6; set_disass(0, 0xc6, "LDAB %b", ' ', 2); set_ticks(0, 0xc6, 1); }
+virtual void fill_0_d6() { page0[0xd6 ]= wrap_0_d6; set_disass(0, 0xd6, "LDAB %d", ' ', 2); set_ticks(0, 0xd6, 3); }
+virtual void fill_0_e6() { page0[0xe6 ]= wrap_0_e6; set_disass(0, 0xe6, "LDAB %p", ' ', -2); set_ticks(0, 0xe6, 0x66433); }
+virtual void fill_0_f6() { page0[0xf6 ]= wrap_0_f6; set_disass(0, 0xf6, "LDAB %e", ' ', 3); set_ticks(0, 0xf6, 3); }
+
+virtual void fill_0_83() { page0[0x83 ]= wrap_0_83; set_disass(0, 0x83, "SUBD %B", ' ', 3); set_ticks(0, 0x83, 2); }
+virtual void fill_0_93() { page0[0x93 ]= wrap_0_93; set_disass(0, 0x93, "SUBD %D", ' ', 2); set_ticks(0, 0x93, 3); }
+virtual void fill_0_a3() { page0[0xa3 ]= wrap_0_a3; set_disass(0, 0xa3, "SUBD %p", ' ', -2); set_ticks(0, 0xa3, 0x66433); }
+virtual void fill_0_b3() { page0[0xb3 ]= wrap_0_b3; set_disass(0, 0xb3, "SUBD %E", ' ', 3); set_ticks(0, 0xb3, 3); }
+
+virtual void fill_0_8c() { page0[0x8c ]= wrap_0_8c; set_disass(0, 0x8c, "CPD %B", ' ', 3); set_ticks(0, 0x8c, 2); }
+virtual void fill_0_9c() { page0[0x9c ]= wrap_0_9c; set_disass(0, 0x9c, "CPD %D", ' ', 2); set_ticks(0, 0x9c, 3); }
+virtual void fill_0_ac() { page0[0xac ]= wrap_0_ac; set_disass(0, 0xac, "CPD %p", ' ', -2); set_ticks(0, 0xac, 0x66433); }
+virtual void fill_0_bc() { page0[0xbc ]= wrap_0_bc; set_disass(0, 0xbc, "CPD %E", ' ', 3); set_ticks(0, 0xbc, 3); }
+
+virtual void fill_0_8d() { page0[0x8d ]= wrap_0_8d; set_disass(0, 0x8d, "CPY %B", ' ', 3); set_ticks(0, 0x8d, 2); }
+virtual void fill_0_9d() { page0[0x9d ]= wrap_0_9d; set_disass(0, 0x9d, "CPY %D", ' ', 2); set_ticks(0, 0x9d, 3); }
+virtual void fill_0_ad() { page0[0xad ]= wrap_0_ad; set_disass(0, 0xad, "CPY %p", ' ', -2); set_ticks(0, 0xad, 0x66433); }
+virtual void fill_0_bd() { page0[0xbd ]= wrap_0_bd; set_disass(0, 0xbd, "CPY %E", ' ', 3); set_ticks(0, 0xbd, 3); }
+
+virtual void fill_0_8e() { page0[0x8e ]= wrap_0_8e; set_disass(0, 0x8e, "CPX %B", ' ', 3); set_ticks(0, 0x8e, 2); }
+virtual void fill_0_9e() { page0[0x9e ]= wrap_0_9e; set_disass(0, 0x9e, "CPX %D", ' ', 2); set_ticks(0, 0x9e, 3); }
+virtual void fill_0_ae() { page0[0xae ]= wrap_0_ae; set_disass(0, 0xae, "CPX %p", ' ', -2); set_ticks(0, 0xae, 0x66433); }
+virtual void fill_0_be() { page0[0xbe ]= wrap_0_be; set_disass(0, 0xbe, "CPX %E", ' ', 3); set_ticks(0, 0xbe, 3); }
+
+virtual void fill_0_8f() { page0[0x8f ]= wrap_0_8f; set_disass(0, 0x8f, "CPS %B", ' ', 3); set_ticks(0, 0x8f, 2); }
+virtual void fill_0_9f() { page0[0x9f ]= wrap_0_9f; set_disass(0, 0x9f, "CPS %D", ' ', 2); set_ticks(0, 0x9f, 3); }
+virtual void fill_0_af() { page0[0xaf ]= wrap_0_af; set_disass(0, 0xaf, "CPS %p", ' ', -2); set_ticks(0, 0xaf, 0x66433); }
+virtual void fill_0_bf() { page0[0xbf ]= wrap_0_bf; set_disass(0, 0xbf, "CPS %E", ' ', 3); set_ticks(0, 0xbf, 3); }
+
+virtual void fill_0_c3() { page0[0xc3 ]= wrap_0_c3; set_disass(0, 0xc3, "ADDD %B", ' ', 3); set_ticks(0, 0xc3, 2); }
+virtual void fill_0_d3() { page0[0xd3 ]= wrap_0_d3; set_disass(0, 0xd3, "ADDD %D", ' ', 2); set_ticks(0, 0xd3, 3); }
+virtual void fill_0_e3() { page0[0xe3 ]= wrap_0_e3; set_disass(0, 0xe3, "ADDD %p", ' ', -2); set_ticks(0, 0xe3, 0x66433); }
+virtual void fill_0_f3() { page0[0xf3 ]= wrap_0_f3; set_disass(0, 0xf3, "ADDD %E", ' ', 3); set_ticks(0, 0xf3, 3); }
+
+virtual void fill_0_cc() { page0[0xcc ]= wrap_0_cc; set_disass(0, 0xcc, "LDD %B", ' ', 3); set_ticks(0, 0xcc, 2); }
+virtual void fill_0_dc() { page0[0xdc ]= wrap_0_dc; set_disass(0, 0xdc, "LDD %D", ' ', 2); set_ticks(0, 0xdc, 3); }
+virtual void fill_0_ec() { page0[0xec ]= wrap_0_ec; set_disass(0, 0xec, "LDD %p", ' ', -2); set_ticks(0, 0xec, 0x66433); }
+virtual void fill_0_fc() { page0[0xfc ]= wrap_0_fc; set_disass(0, 0xfc, "LDD %E", ' ', 3); set_ticks(0, 0xfc, 3); }
+
+virtual void fill_0_ce() { page0[0xce ]= wrap_0_ce; set_disass(0, 0xce, "LDX %B", ' ', 3); set_ticks(0, 0xce, 2); }
+virtual void fill_0_de() { page0[0xde ]= wrap_0_de; set_disass(0, 0xde, "LDX %D", ' ', 2); set_ticks(0, 0xde, 3); }
+virtual void fill_0_ee() { page0[0xee ]= wrap_0_ee; set_disass(0, 0xee, "LDX %p", ' ', -2); set_ticks(0, 0xee, 0x66433); }
+virtual void fill_0_fe() { page0[0xfe ]= wrap_0_fe; set_disass(0, 0xfe, "LDX %E", ' ', 3); set_ticks(0, 0xfe, 3); }
+
+virtual void fill_0_cd() { page0[0xcd ]= wrap_0_cd; set_disass(0, 0xcd, "LDY %B", ' ', 3); set_ticks(0, 0xcd, 2); }
+virtual void fill_0_dd() { page0[0xdd ]= wrap_0_dd; set_disass(0, 0xdd, "LDY %D", ' ', 2); set_ticks(0, 0xdd, 3); }
+virtual void fill_0_ed() { page0[0xed ]= wrap_0_ed; set_disass(0, 0xed, "LDY %p", ' ', -2); set_ticks(0, 0xed, 0x66433); }
+virtual void fill_0_fd() { page0[0xfd ]= wrap_0_fd; set_disass(0, 0xfd, "LDY %E", ' ', 3); set_ticks(0, 0xfd, 3); }
+
+virtual void fill_0_cf() { page0[0xcf ]= wrap_0_cf; set_disass(0, 0xcf, "LDS %B", ' ', 3); set_ticks(0, 0xcf, 2); }
+virtual void fill_0_df() { page0[0xdf ]= wrap_0_df; set_disass(0, 0xdf, "LDS %D", ' ', 2); set_ticks(0, 0xdf, 3); }
+virtual void fill_0_ef() { page0[0xef ]= wrap_0_ef; set_disass(0, 0xef, "LDS %p", ' ', -2); set_ticks(0, 0xef, 0x66433); }
+virtual void fill_0_ff() { page0[0xff ]= wrap_0_ff; set_disass(0, 0xff, "LDS %E", ' ', 3); set_ticks(0, 0xff, 3); }
+
+virtual void fill_0_87() { page0[0x87 ]= wrap_0_87; set_disass(0, 0x87, "CLRA", ' ', 1); set_ticks(0, 0x87, 1); }
+virtual void fill_0_c7() { page0[0xc7 ]= wrap_0_c7; set_disass(0, 0xc7, "CLRB", ' ', 1); set_ticks(0, 0xc7, 1); }
+virtual void fill_0_69() { page0[0x69 ]= wrap_0_69; set_disass(0, 0x69, "CLR %p", ' ', -2); set_ticks(0, 0x69, 0x55322); }
+virtual void fill_0_79() { page0[0x79 ]= wrap_0_79; set_disass(0, 0x79, "CLR %e", ' ', 3); set_ticks(0, 0x79, 3); }
+
+virtual void fill_0_97() { page0[0x97 ]= wrap_0_97; set_disass(0, 0x97, "TSTA", ' ', 1); set_ticks(0, 0x97, 1); }
+virtual void fill_0_d7() { page0[0xd7 ]= wrap_0_d7; set_disass(0, 0xd7, "TSTB", ' ', 1); set_ticks(0, 0xd7, 1); }
+virtual void fill_0_e7() { page0[0xe7 ]= wrap_0_e7; set_disass(0, 0xe7, "TST %p", ' ', -2); set_ticks(0, 0xe7, 0x55322); }
+virtual void fill_0_f7() { page0[0xf7 ]= wrap_0_f7; set_disass(0, 0xf7, "TST %e", ' ', 3); set_ticks(0, 0xf7, 3); }
+
+virtual void fill_0_40() { page0[0x40 ]= wrap_0_40; set_disass(0, 0x40, "NEGA", ' ', 1); set_ticks(0, 0x40, 1); }
+virtual void fill_0_50() { page0[0x50 ]= wrap_0_50; set_disass(0, 0x50, "NEGB", ' ', 1); set_ticks(0, 0x50, 1); }
+virtual void fill_0_60() { page0[0x60 ]= wrap_0_60; set_disass(0, 0x60, "NEG %p", ' ', -2); set_ticks(0, 0x60, 0x66433); }
+virtual void fill_0_70() { page0[0x70 ]= wrap_0_70; set_disass(0, 0x70, "NEG %e", ' ', 3); set_ticks(0, 0x70, 3); }
+
+virtual void fill_0_41() { page0[0x41 ]= wrap_0_41; set_disass(0, 0x41, "COMA", ' ', 1); set_ticks(0, 0x41, 1); }
+virtual void fill_0_51() { page0[0x51 ]= wrap_0_51; set_disass(0, 0x51, "COMB", ' ', 1); set_ticks(0, 0x51, 1); }
+virtual void fill_0_61() { page0[0x61 ]= wrap_0_61; set_disass(0, 0x61, "COM %p", ' ', -2); set_ticks(0, 0x61, 0x66433); }
+virtual void fill_0_71() { page0[0x71 ]= wrap_0_71; set_disass(0, 0x71, "COM %e", ' ', 3); set_ticks(0, 0x71, 3); }
+
+virtual void fill_0_42() { page0[0x42 ]= wrap_0_42; set_disass(0, 0x42, "INCA", ' ', 1); set_ticks(0, 0x42, 1); }
+virtual void fill_0_52() { page0[0x52 ]= wrap_0_52; set_disass(0, 0x52, "INCB", ' ', 1); set_ticks(0, 0x52, 1); }
+virtual void fill_0_62() { page0[0x62 ]= wrap_0_62; set_disass(0, 0x62, "INC %p", ' ', -2); set_ticks(0, 0x62, 0x66433); }
+virtual void fill_0_72() { page0[0x72 ]= wrap_0_72; set_disass(0, 0x72, "INC %e", ' ', 3); set_ticks(0, 0x72, 3); }
+
+virtual void fill_0_43() { page0[0x43 ]= wrap_0_43; set_disass(0, 0x43, "DECA", ' ', 1); set_ticks(0, 0x43, 1); }
+virtual void fill_0_53() { page0[0x53 ]= wrap_0_53; set_disass(0, 0x53, "DECB", ' ', 1); set_ticks(0, 0x53, 1); }
+virtual void fill_0_63() { page0[0x63 ]= wrap_0_63; set_disass(0, 0x63, "DEC %p", ' ', -2); set_ticks(0, 0x63, 0x66433); }
+virtual void fill_0_73() { page0[0x73 ]= wrap_0_73; set_disass(0, 0x73, "DEC %e", ' ', 3); set_ticks(0, 0x73, 3); }
+
+virtual void fill_0_44() { page0[0x44 ]= wrap_0_44; set_disass(0, 0x44, "LSRA", ' ', 1); set_ticks(0, 0x44, 1); }
+virtual void fill_0_54() { page0[0x54 ]= wrap_0_54; set_disass(0, 0x54, "LSRB", ' ', 1); set_ticks(0, 0x54, 1); }
+virtual void fill_0_64() { page0[0x64 ]= wrap_0_64; set_disass(0, 0x64, "LSR %p", ' ', -2); set_ticks(0, 0x64, 0x66433); }
+virtual void fill_0_74() { page0[0x74 ]= wrap_0_74; set_disass(0, 0x74, "LSR %e", ' ', 3); set_ticks(0, 0x74, 3); }
+
+virtual void fill_0_45() { page0[0x45 ]= wrap_0_45; set_disass(0, 0x45, "ROLA", ' ', 1); set_ticks(0, 0x45, 1); }
+virtual void fill_0_55() { page0[0x55 ]= wrap_0_55; set_disass(0, 0x55, "ROLB", ' ', 1); set_ticks(0, 0x55, 1); }
+virtual void fill_0_65() { page0[0x65 ]= wrap_0_65; set_disass(0, 0x65, "ROL %p", ' ', -2); set_ticks(0, 0x65, 0x66433); }
+virtual void fill_0_75() { page0[0x75 ]= wrap_0_75; set_disass(0, 0x75, "ROL %e", ' ', 3); set_ticks(0, 0x75, 3); }
+
+virtual void fill_0_46() { page0[0x46 ]= wrap_0_46; set_disass(0, 0x46, "RORA", ' ', 1); set_ticks(0, 0x46, 1); }
+virtual void fill_0_56() { page0[0x56 ]= wrap_0_56; set_disass(0, 0x56, "RORB", ' ', 1); set_ticks(0, 0x56, 1); }
+virtual void fill_0_66() { page0[0x66 ]= wrap_0_66; set_disass(0, 0x66, "ROR %p", ' ', -2); set_ticks(0, 0x66, 0x66433); }
+virtual void fill_0_76() { page0[0x76 ]= wrap_0_76; set_disass(0, 0x76, "ROR %e", ' ', 3); set_ticks(0, 0x76, 3); }
+
+virtual void fill_0_47() { page0[0x47 ]= wrap_0_47; set_disass(0, 0x47, "ASRA", ' ', 1); set_ticks(0, 0x47, 1); }
+virtual void fill_0_57() { page0[0x57 ]= wrap_0_57; set_disass(0, 0x57, "ASRB", ' ', 1); set_ticks(0, 0x57, 1); }
+virtual void fill_0_67() { page0[0x67 ]= wrap_0_67; set_disass(0, 0x67, "ASR %p", ' ', -2); set_ticks(0, 0x67, 0x66433); }
+virtual void fill_0_77() { page0[0x77 ]= wrap_0_77; set_disass(0, 0x77, "ASR %e", ' ', 3); set_ticks(0, 0x77, 3); }
+
+virtual void fill_0_48() { page0[0x48 ]= wrap_0_48; set_disass(0, 0x48, "ASLA", ' ', 1); set_ticks(0, 0x48, 1); }
+virtual void fill_0_58() { page0[0x58 ]= wrap_0_58; set_disass(0, 0x58, "ASLB", ' ', 1); set_ticks(0, 0x58, 1); }
+virtual void fill_0_68() { page0[0x68 ]= wrap_0_68; set_disass(0, 0x68, "ASL %p", ' ', -2); set_ticks(0, 0x68, 0x66433); }
+virtual void fill_0_78() { page0[0x78 ]= wrap_0_78; set_disass(0, 0x78, "ASL %e", ' ', 3); set_ticks(0, 0x78, 3); }
+
+virtual void fill_0_49() { page0[0x49 ]= wrap_0_49; set_disass(0, 0x49, "LSRD", ' ', 1); set_ticks(0, 0x49, 1); }
+virtual void fill_0_59() { page0[0x59 ]= wrap_0_59; set_disass(0, 0x59, "LSLD", ' ', 1); set_ticks(0, 0x59, 1); }
+
+virtual void fill_0_4a() { page0[0x4a ]= wrap_0_4a; set_disass(0, 0x4a, "CALL $ep$", ' ', 4); set_ticks(0, 0x4a, 7); }
+virtual void fill_0_4b() { page0[0x4b ]= wrap_0_4b; set_disass(0, 0x4b, "CALL $ip$", ' ', -2); set_ticks(0, 0x4b, 0xaa988); }
+
+virtual void fill_0_5a() { page0[0x5a ]= wrap_0_5a; set_disass(0, 0x5a, "STAA %d", ' ', 2); set_ticks(0, 0x5a, 2); }
+virtual void fill_0_6a() { page0[0x6a ]= wrap_0_6a; set_disass(0, 0x6a, "STAA %p", ' ', -2); set_ticks(0, 0x6a, 0x55332); }
+virtual void fill_0_7a() { page0[0x7a ]= wrap_0_7a; set_disass(0, 0x7a, "STAA %e", ' ', 3); set_ticks(0, 0x7a, 3); }
+
+virtual void fill_0_5b() { page0[0x5b ]= wrap_0_5b; set_disass(0, 0x5b, "STAB %d", ' ', 2); set_ticks(0, 0x5b, 2); }
+virtual void fill_0_6b() { page0[0x6b ]= wrap_0_6b; set_disass(0, 0x6b, "STAB %p", ' ', -2); set_ticks(0, 0x6b, 0x55332); }
+virtual void fill_0_7b() { page0[0x7b ]= wrap_0_7b; set_disass(0, 0x7b, "STAB %e", ' ', 3); set_ticks(0, 0x7b, 3); }
+
+virtual void fill_0_5c() { page0[0x5c ]= wrap_0_5c; set_disass(0, 0x5c, "STD %d", ' ', 2); set_ticks(0, 0x5c, 2); }
+virtual void fill_0_6c() { page0[0x6c ]= wrap_0_6c; set_disass(0, 0x6c, "STD %p", ' ', -2); set_ticks(0, 0x6c, 0x55332); }
+virtual void fill_0_7c() { page0[0x7c ]= wrap_0_7c; set_disass(0, 0x7c, "STD %e", ' ', 3); set_ticks(0, 0x7c, 3); }
+
+virtual void fill_0_5e() { page0[0x5e ]= wrap_0_5e; set_disass(0, 0x5e, "STX %d", ' ', 2); set_ticks(0, 0x5e, 2); }
+virtual void fill_0_6e() { page0[0x6e ]= wrap_0_6e; set_disass(0, 0x6e, "STX %p", ' ', -2); set_ticks(0, 0x6e, 0x55332); }
+virtual void fill_0_7e() { page0[0x7e ]= wrap_0_7e; set_disass(0, 0x7e, "STX %e", ' ', 3); set_ticks(0, 0x7e, 3); }
+
+virtual void fill_0_5d() { page0[0x5d ]= wrap_0_5d; set_disass(0, 0x5d, "STY %d", ' ', 2); set_ticks(0, 0x5d, 2); }
+virtual void fill_0_6d() { page0[0x6d ]= wrap_0_6d; set_disass(0, 0x6d, "STY %p", ' ', -2); set_ticks(0, 0x6d, 0x55332); }
+virtual void fill_0_7d() { page0[0x7d ]= wrap_0_7d; set_disass(0, 0x7d, "STY %e", ' ', 3); set_ticks(0, 0x7d, 3); }
+
+virtual void fill_0_5f() { page0[0x5f ]= wrap_0_5f; set_disass(0, 0x5f, "STS %d", ' ', 2); set_ticks(0, 0x5f, 2); }
+virtual void fill_0_6f() { page0[0x6f ]= wrap_0_6f; set_disass(0, 0x6f, "STS %p", ' ', -2); set_ticks(0, 0x6f, 0x55332); }
+virtual void fill_0_7f() { page0[0x7f ]= wrap_0_7f; set_disass(0, 0x7f, "STS %e", ' ', 3); set_ticks(0, 0x7f, 3); }
+
+virtual void fill_0_4c() { page0[0x4c ]= wrap_0_4c; set_disass(0, 0x4c, "BSET %d,%b", ' ', 3); set_ticks(0, 0x4c, 4); }
+virtual void fill_0_0c() { page0[0x0c ]= wrap_0_0c; set_disass(0, 0x0c, "BSET %p,%b", ' ', -4); set_ticks(0, 0x0c, 4); }
+virtual void fill_0_1c() { page0[0x1c ]= wrap_0_1c; set_disass(0, 0x1c, "BSET %e,%b", ' ', 4); set_ticks(0, 0x1c, 4); }
+
+virtual void fill_0_4d() { page0[0x4d ]= wrap_0_4d; set_disass(0, 0x4d, "BCLR %d,%b", ' ', 3); set_ticks(0, 0x4d, 4); }
+virtual void fill_0_0d() { page0[0x0d ]= wrap_0_0d; set_disass(0, 0x0d, "BCLR %p,%b", ' ', -4); set_ticks(0, 0x0d, 4); }
+virtual void fill_0_1d() { page0[0x1d ]= wrap_0_1d; set_disass(0, 0x1d, "BCLR %e,%b", ' ', 4); set_ticks(0, 0x1d, 4); }
+
+virtual void fill_0_4e() { page0[0x4e ]= wrap_0_4e; set_disass(0, 0x4e, "BRSET %d,%b,%r", ' ', 4); set_ticks(0, 0x4e, 5); }
+virtual void fill_0_0e() { page0[0x0e ]= wrap_0_0e; set_disass(0, 0x0e, "BRSET %p,%b,%r", ' ', -4); set_ticks(0, 0x0e, 5); }
+virtual void fill_0_1e() { page0[0x1e ]= wrap_0_1e; set_disass(0, 0x1e, "BRSET %e,%b,%r", ' ', 5); set_ticks(0, 0x1e, 5); }
+
+virtual void fill_0_4f() { page0[0x4f ]= wrap_0_4f; set_disass(0, 0x4f, "BRCLR %d,%b,%r", ' ', 4); set_ticks(0, 0x4f, 5); }
+virtual void fill_0_0f() { page0[0x0f ]= wrap_0_0f; set_disass(0, 0x0f, "BRCLR %p,%b,%r", ' ', -4); set_ticks(0, 0x0f, 5); }
+virtual void fill_0_1f() { page0[0x1f ]= wrap_0_1f; set_disass(0, 0x1f, "BRCLR %e,%b,%r", ' ', 5); set_ticks(0, 0x1f, 5); }
+
+virtual void fill_0_20() { page0[0x20 ]= wrap_0_20; set_disass(0, 0x20, "BRA %r", ' ', 2); set_ticks(0, 0x20, 1); }
+virtual void fill_0_21() { page0[0x21 ]= wrap_0_21; set_disass(0, 0x21, "BRN %r", ' ', 2); set_ticks(0, 0x21, 1); }
+virtual void fill_0_22() { page0[0x22 ]= wrap_0_22; set_disass(0, 0x22, "BHI %r", ' ', 2); set_ticks(0, 0x22, 1); }
+virtual void fill_0_23() { page0[0x23 ]= wrap_0_23; set_disass(0, 0x23, "BLS %r", ' ', 2); set_ticks(0, 0x23, 1); }
+virtual void fill_0_24() { page0[0x24 ]= wrap_0_24; set_disass(0, 0x24, "BCC %r", ' ', 2); set_ticks(0, 0x24, 1); }
+virtual void fill_0_25() { page0[0x25 ]= wrap_0_25; set_disass(0, 0x25, "BCS %r", ' ', 2); set_ticks(0, 0x25, 1); }
+virtual void fill_0_26() { page0[0x26 ]= wrap_0_26; set_disass(0, 0x26, "BNE %r", ' ', 2); set_ticks(0, 0x26, 1); }
+virtual void fill_0_27() { page0[0x27 ]= wrap_0_27; set_disass(0, 0x27, "BEQ %r", ' ', 2); set_ticks(0, 0x27, 1); }
+virtual void fill_0_28() { page0[0x28 ]= wrap_0_28; set_disass(0, 0x28, "BVC %r", ' ', 2); set_ticks(0, 0x28, 1); }
+virtual void fill_0_29() { page0[0x29 ]= wrap_0_29; set_disass(0, 0x29, "BVS %r", ' ', 2); set_ticks(0, 0x29, 1); }
+virtual void fill_0_2a() { page0[0x2a ]= wrap_0_2a; set_disass(0, 0x2a, "BPL %r", ' ', 2); set_ticks(0, 0x2a, 1); }
+virtual void fill_0_2b() { page0[0x2b ]= wrap_0_2b; set_disass(0, 0x2b, "BMI %r", ' ', 2); set_ticks(0, 0x2b, 1); }
+virtual void fill_0_2c() { page0[0x2c ]= wrap_0_2c; set_disass(0, 0x2c, "BGE %r", ' ', 2); set_ticks(0, 0x2c, 1); }
+virtual void fill_0_2d() { page0[0x2d ]= wrap_0_2d; set_disass(0, 0x2d, "BLT %r", ' ', 2); set_ticks(0, 0x2d, 1); }
+virtual void fill_0_2e() { page0[0x2e ]= wrap_0_2e; set_disass(0, 0x2e, "BGT %r", ' ', 2); set_ticks(0, 0x2e, 1); }
+virtual void fill_0_2f() { page0[0x2f ]= wrap_0_2f; set_disass(0, 0x2f, "BLE %r", ' ', 2); set_ticks(0, 0x2f, 1); }
+
+virtual void fill_0_30() { page0[0x30 ]= wrap_0_30; set_disass(0, 0x30, "PULX", ' ', 1); set_ticks(0, 0x30, 3); }
+virtual void fill_0_31() { page0[0x31 ]= wrap_0_31; set_disass(0, 0x31, "PULY", ' ', 1); set_ticks(0, 0x31, 3); }
+virtual void fill_0_32() { page0[0x32 ]= wrap_0_32; set_disass(0, 0x32, "PULA", ' ', 1); set_ticks(0, 0x32, 3); }
+virtual void fill_0_33() { page0[0x33 ]= wrap_0_33; set_disass(0, 0x33, "PULB", ' ', 1); set_ticks(0, 0x33, 3); }
+virtual void fill_0_34() { page0[0x34 ]= wrap_0_34; set_disass(0, 0x34, "PSHX", ' ', 1); set_ticks(0, 0x34, 2); }
+virtual void fill_0_35() { page0[0x35 ]= wrap_0_35; set_disass(0, 0x35, "PSHY", ' ', 1); set_ticks(0, 0x35, 2); }
+virtual void fill_0_36() { page0[0x36 ]= wrap_0_36; set_disass(0, 0x36, "PSHA", ' ', 1); set_ticks(0, 0x36, 2); }
+virtual void fill_0_37() { page0[0x37 ]= wrap_0_37; set_disass(0, 0x37, "PSHB", ' ', 1); set_ticks(0, 0x37, 2); }
+virtual void fill_0_38() { page0[0x38 ]= wrap_0_38; set_disass(0, 0x38, "PULC", ' ', 1); set_ticks(0, 0x38, 3); }
+virtual void fill_0_39() { page0[0x39 ]= wrap_0_39; set_disass(0, 0x39, "PSHC", ' ', 1); set_ticks(0, 0x39, 2); }
+virtual void fill_0_3a() { page0[0x3a ]= wrap_0_3a; set_disass(0, 0x3a, "PULD", ' ', 1); set_ticks(0, 0x3a, 3); }
+virtual void fill_0_3b() { page0[0x3b ]= wrap_0_3b; set_disass(0, 0x3b, "PSHD", ' ', 1); set_ticks(0, 0x3b, 2); }
+
+virtual void fill_0_a7() { page0[0xa7 ]= wrap_0_a7; set_disass(0, 0xa7, "NOP", ' ', 1); set_ticks(0, 0xa7, 1); }
+
+virtual void fill_0_b7() { page0[0xb7 ]= wrap_0_b7; set_disass(0, 0xb7, "%T", ' ', 2); set_ticks(0, 0xb7, 0); }
+
+virtual void fill_0x18_06() { page0x18[0x06 ]= wrap_0x18_06; set_disass(0x18, 0x06, "ABA", ' ', 2); set_ticks(0x18, 0x06, 2); }
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/main_in.mk sdcc-4.2.0+dfsg/sim/ucsim/main_in.mk
--- sdcc-4.0.0+dfsg/sim/ucsim/main_in.mk	2017-06-04 15:33:30.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/main_in.mk	2022-01-13 08:20:03.000000000 +0000
@@ -23,11 +23,12 @@
 
 DEFS            = $(subs -DHAVE_CONFIG_H,,@DEFS@)
 # FIXME: -Imcs51 must be removed!!!
+PICOPT		= @PICOPT@
 CPPFLAGS        = @CPPFLAGS@ -I$(top_builddir) -I$(srcdir) \
                   -I$(top_srcdir)/$(SIMDIR) \
 		  -I$(top_srcdir)/$(CMDDIR) -I$(top_srcdir)/$(GUIDIR)
-CFLAGS          = @CFLAGS@ -I$(top_builddir) @WALL_FLAG@
-CXXFLAGS        = @CXXFLAGS@ -I$(top_builddir) @WALL_FLAG@
+CFLAGS          = @WALL_FLAG@ @CFLAGS@ -I$(top_builddir)
+CXXFLAGS        = @WALL_FLAG@ @CXXFLAGS@ $(PICOPT) -I$(top_builddir)
 WINSOCK_AVAIL   = @WINSOCK_AVAIL@
 LDFLAGS		= @LDFLAGS@
 
@@ -92,6 +93,8 @@
 	rm -f $(DESTDIR)$(bindir)/portmon$(EXEEXT)
 	rm -f $(DESTDIR)$(bindir)/sstm8$(EXEEXT)
 	rm -f $(DESTDIR)$(bindir)/sst7$(EXEEXT)
+	rm -f $(DESTDIR)$(bindir)/sp1516$(EXEEXT)
+	rm -f $(DESTDIR)$(bindir)/sm6809$(EXEEXT)
 
 
 # Performing self-test
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/Makefile.in sdcc-4.2.0+dfsg/sim/ucsim/Makefile.in
--- sdcc-4.0.0+dfsg/sim/ucsim/Makefile.in	2019-03-14 16:34:34.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/Makefile.in	2021-10-04 11:31:43.000000000 +0000
@@ -9,7 +9,6 @@
 SHELL		= /bin/sh
 
 include packages.mk
-#PKGS		= cmd.src sim.src gui.src s51.src avr.src z80.src pdk.src doc
 
 VPATH		= @srcdir@
 srcdir		= @srcdir@
@@ -23,7 +22,7 @@
 	$(MAKE) libs
 	$(MAKE) apps
 
-libs: main_all cmd_src_all sim_src_all gui_src_all
+libs: main_all cmd_src_all sim_src_all gui_src_all motorola_src_all m6800lib
 
 main_all:
 	$(MAKE) -f main.mk all
@@ -37,6 +36,12 @@
 gui_src_all:
 	$(MAKE) -C gui.src gui.src
 
+motorola_src_all:
+	$(MAKE) -C motorola.src motorola.src
+
+m6800lib:
+	$(MAKE) -C m6800.src m6800lib
+
 
 apps: $(PKGS) main_app
 
@@ -77,7 +82,7 @@
 clean:
 	$(MAKE) -f $(srcdir)/clean.mk clean EXEEXT=$(EXEEXT)
 	@for pkg in $(PKGS_ALL); do\
-	  $(MAKE) -C $$pkg -f ../$(srcdir)/$$pkg/clean.mk clean EXEEXT=$(EXEEXT) ;\
+	  $(MAKE) -C $$pkg -f clean.mk clean EXEEXT=$(EXEEXT) ;\
 	done
 
 
@@ -86,14 +91,16 @@
 distclean: clean
 	$(MAKE) -f $(srcdir)/clean.mk distclean
 	@for pkg in $(PKGS_ALL); do\
-	  $(MAKE) -C $$pkg -f ../$(srcdir)/$$pkg/clean.mk distclean ;\
+	  $(MAKE) -C $$pkg -f clean.mk distclean ;\
+	done
+	@for pkg in $(PKGS) sim.src; do\
+		if test -d $$pkg/test; then \
+			$(MAKE) -C $$pkg/test clean ;\
+			if test -f $$pkg/test/Makefile.in; then rm -f $$pkg/test/Makefile; fi ;\
+		fi ;\
 	done
 	rm -rf doc/*~ doc/*.bak Makefile packages.mk libtool
 	$(MAKE) -C example clean
-	$(MAKE) -C s51.src/test clean
-	$(MAKE) -C stm8.src/test clean
-	$(MAKE) -C tlcs.src/test clean
-	$(MAKE) -C z80.src/test clean
 
 
 # Like clean but some files may still exist
@@ -101,17 +108,17 @@
 mostlyclean: clean
 	$(MAKE) -f clean.mk mostlyclean
 	@for pkg in $(PKGS_ALL); do\
-	  $(MAKE) -C $$pkg -f ../$(srcdir)/$$pkg/clean.mk mostlyclean ;\
+	  $(MAKE) -C $$pkg -f clean.mk mostlyclean ;\
 	done
 
 
 # Deleting everything that can reconstructed by this Makefile. It deletes
-# everything deleted by distclean plus files created by bison, stc.
+# everything deleted by distclean plus files created by bison, etc.
 # -----------------------------------------------------------------------
 realclean: distclean
 	$(MAKE) -f clean.mk realclean
 	@for pkg in $(PKGS_ALL); do\
-	  $(MAKE) -C $$pkg -f ../$(srcdir)/$$pkg/clean.mk realclean ;\
+	  $(MAKE) -C $$pkg -f clean.mk realclean ;\
 	done
 
 
@@ -123,11 +130,18 @@
 	  $(MAKE) -C $$pkg check ;\
 	done
 
-test:
-	$(MAKE) -f main.mk test
-	@for pkg in $(PKGS); do\
-	  $(MAKE) -C $$pkg test ;\
-	done
+# We want tests to be parallelizable so a simple shell loop is
+# not good enough.
+PKGS_TEST = $(foreach pkg, sim.src $(PKGS), $(pkg)/test)
+PKGS_BASELINE = $(patsubst %,%/baseline,$(PKGS_TEST))
+.PHONY:	test $(PKGS_TEST) baseline $(PKGS_BASELINE)
+test: $(PKGS_TEST)
+$(PKGS_TEST):
+	-@$(MAKE) --no-print-directory -C $(dir $@) test
+
+baseline: $(PKGS_BASELINE)
+$(PKGS_BASELINE):
+	-@$(MAKE) --no-print-directory -C $(patsubst %/test/baseline,%,$@) baseline
 
 
 # Performing installation test
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/mos6502.src/(c).1 sdcc-4.2.0+dfsg/sim/ucsim/mos6502.src/(c).1
--- sdcc-4.0.0+dfsg/sim/ucsim/mos6502.src/(c).1	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/mos6502.src/(c).1	2021-04-16 22:21:27.000000000 +0000
@@ -0,0 +1,25 @@
+/*
+ * Simulator of microcontrollers (@@F@@)
+ *
+ * Copyright (C) @@S@@,@@Y@@ Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/mos6502.src/clean.mk sdcc-4.2.0+dfsg/sim/ucsim/mos6502.src/clean.mk
--- sdcc-4.0.0+dfsg/sim/ucsim/mos6502.src/clean.mk	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/mos6502.src/clean.mk	2022-01-15 21:15:29.000000000 +0000
@@ -0,0 +1,34 @@
+# mos6502.src/clean.mk
+
+# Deleting all files created by building the program
+# --------------------------------------------------
+clean:
+	rm -f *core *[%~] *.[oa] *.map
+	rm -f .[a-z]*~
+	rm -f smos6502$(EXEEXT) smos6502.exe
+	rm -f smcs6502$(EXEEXT) smcs6502.exe
+	rm -f ucsim_mos6502$(EXEEXT) ucsim_mos6502.exe
+	rm -f ucsim_mcs6502$(EXEEXT) ucsim_mcs6502.exe
+	$(MAKE) -C test -f clean.mk clean
+
+
+# Deleting all files created by configuring or building the program
+# -----------------------------------------------------------------
+distclean: clean
+	rm -f config.cache config.log config.status
+	rm -f Makefile *.dep
+	rm -f *.obj *.list *.lst *.hex
+	$(MAKE) -C test -f clean.mk distclean
+
+
+# Like clean but some files may still exist
+# -----------------------------------------
+mostlyclean: clean
+
+
+# Deleting everything that can reconstructed by this Makefile. It deletes
+# everything deleted by distclean plus files created by bison, etc.
+# -----------------------------------------------------------------------
+realclean: distclean
+
+# End of mos6502.src/clean.mk
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/mos6502.src/conf.mk sdcc-4.2.0+dfsg/sim/ucsim/mos6502.src/conf.mk
--- sdcc-4.0.0+dfsg/sim/ucsim/mos6502.src/conf.mk	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/mos6502.src/conf.mk	2022-01-15 21:15:29.000000000 +0000
@@ -0,0 +1,11 @@
+# mos6502.src/conf.mk
+#
+# Makefile targets to remake configuration
+#
+
+freshconf: Makefile
+
+Makefile: $(srcdir)/Makefile.in $(top_srcdir)/configure.ac
+	cd $(top_builddir) && $(SHELL) ./config.status
+
+# End of mos6502.src/conf.mk
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/mos6502.src/decode.h sdcc-4.2.0+dfsg/sim/ucsim/mos6502.src/decode.h
--- sdcc-4.0.0+dfsg/sim/ucsim/mos6502.src/decode.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/mos6502.src/decode.h	2022-01-15 21:15:29.000000000 +0000
@@ -0,0 +1,205 @@
+/*
+ * Simulator of microcontrollers (decode.h)
+ *
+ * Copyright (C) 2020,20 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef DECODE_HEADER
+#define DECODE_HEADER
+
+#define NOP	instruction_ea
+#define BRK	instruction_00
+#define RTI	instruction_40
+#define CLI	instruction_58
+#define SEI	instruction_78
+#define PHP	instruction_08
+#define CLC	instruction_18
+#define PLP	instruction_28
+#define SEc	instruction_38
+#define PHA	instruction_48
+#define PLA	instruction_68
+#define DEY	instruction_88
+#define TYA	instruction_98
+#define TAY	instruction_a8
+#define CLV	instruction_b8
+#define INY	instruction_c8
+#define CLD	instruction_d8
+#define INX	instruction_e8
+#define SED	instruction_f8
+#define TXA	instruction_8a
+#define TXS	instruction_9a
+#define TAX	instruction_aa
+#define TSX	instruction_ba
+#define DEX	instruction_ca
+
+#define ORAix	instruction_01
+#define ORAiy	instruction_11
+#define ORAz	instruction_05
+#define ORAzx	instruction_15
+#define ORA8	instruction_09
+#define ORAay	instruction_19
+#define ORAa	instruction_0d
+#define ORAax	instruction_1d
+
+#define ANDix	instruction_21
+#define ANDiy	instruction_31
+#define ANDz	instruction_25
+#define ANDzx	instruction_35
+#define AND8	instruction_29
+#define ANDay	instruction_39
+#define ANDa	instruction_2d
+#define ANDax	instruction_3d
+
+#define EORix	instruction_41
+#define EORiy	instruction_51
+#define EORz	instruction_45
+#define EORzx	instruction_55
+#define EOR8	instruction_49
+#define EORay	instruction_59
+#define EORa	instruction_4d
+#define EORax	instruction_5d
+
+#define ADCix	instruction_61
+#define ADCiy	instruction_71
+#define ADCz	instruction_65
+#define ADCzx	instruction_75
+#define ADC8	instruction_69
+#define ADCay	instruction_79
+#define ADCa	instruction_6d
+#define ADCax	instruction_7d
+
+#define STAix	instruction_81
+#define STAiy	instruction_91
+#define STAz	instruction_85
+#define STAzx	instruction_95
+#define STAay	instruction_99
+#define STAa	instruction_8d
+#define STAax	instruction_9d
+
+#define LDAix	instruction_a1
+#define LDAiy	instruction_b1
+#define LDAz	instruction_a5
+#define LDAzx	instruction_b5
+#define LDA8	instruction_a9
+#define LDAay	instruction_b9
+#define LDAa	instruction_ad
+#define LDAax	instruction_bd
+
+#define CMPix	instruction_c1
+#define CMPiy	instruction_d1
+#define CMPz	instruction_c5
+#define CMPzx	instruction_d5
+#define CMP8	instruction_c9
+#define CMPay	instruction_d9
+#define CMPa	instruction_cd
+#define CMPax	instruction_dd
+
+#define SBCix	instruction_e1
+#define SBCiy	instruction_f1
+#define SBCz	instruction_e5
+#define SBCzx	instruction_f5
+#define SBC8	instruction_e9
+#define SBCay	instruction_f9
+#define SBCa	instruction_ed
+#define SBCax	instruction_fd
+
+#define STYz	instruction_84
+#define STYzx	instruction_94
+#define STYa    instruction_8c
+#define STXz	instruction_86
+#define STXzy	instruction_96
+#define STXa    instruction_8e
+
+#define LDY8    instruction_a0
+#define LDYz    instruction_a4
+#define LDYzx   instruction_b4
+#define LDYa	instruction_ac
+#define LDYax	instruction_bc
+#define LDX8    instruction_a2
+#define LDXz    instruction_a6
+#define LDXzy   instruction_b6
+#define LDXa	instruction_ae
+#define LDXay	instruction_be
+
+#define CPY8	instruction_c0
+#define CPYz	instruction_c4
+#define CPYa	instruction_cc
+#define CPX8	instruction_e0
+#define CPXz	instruction_e4
+#define CPXa	instruction_ec
+
+#define INCz	instruction_e6
+#define INCzx	instruction_f6
+#define INCa	instruction_ee
+#define INCax	instruction_fe
+#define DECz	instruction_c6
+#define DECzx	instruction_d6
+#define DECa	instruction_ce
+#define DECax	instruction_de
+
+#define ASLz	instruction_06
+#define ASLzx	instruction_16
+#define ASL	instruction_0a
+#define ASLa	instruction_0e
+#define ASLax	instruction_1e
+
+#define LSRz	instruction_46
+#define LSRzx	instruction_56
+#define LSR	instruction_4a
+#define LSRa	instruction_4e
+#define LSRax	instruction_5e
+
+#define ROLz	instruction_26
+#define ROLzx	instruction_36
+#define ROL	instruction_2a
+#define ROLa	instruction_2e
+#define ROLax	instruction_3e
+
+#define RORz	instruction_66
+#define RORzx	instruction_76
+#define ROR	instruction_6a
+#define RORa	instruction_6e
+#define RORax	instruction_7e
+
+#define BITz	instruction_24
+#define BITa	instruction_2c
+
+#define JMPa	instruction_4c
+#define JMPi	instruction_6c
+
+#define JSR	instruction_20
+#define RTS	instruction_60
+
+#define BPL	instruction_10
+#define BMI	instruction_30
+#define BVC	instruction_50
+#define BVS	instruction_70
+#define BCC	instruction_90
+#define BCS	instruction_b0
+#define BNE	instruction_d0
+#define BEQ	instruction_f0
+
+#endif
+
+/* End of mos6502.src/decode.h */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/mos6502.src/glob.cc sdcc-4.2.0+dfsg/sim/ucsim/mos6502.src/glob.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/mos6502.src/glob.cc	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/mos6502.src/glob.cc	2022-01-24 11:09:43.000000000 +0000
@@ -0,0 +1,241 @@
+/*
+ * Simulator of microcontrollers (glob.cc)
+ *
+ * Copyright (C) 2020,20 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#include "glob.h"
+
+
+instruction_wrapper_fn itab[256];
+
+/*	Formats
+	x (ind,X)
+	y (ind),Y
+	a abs
+	z zpg
+	X zpg,X
+	Y zpg,Y
+	i abs,X
+	p abs.Y
+	r rel
+	# imm8
+*/
+
+// code mask branch len mn call tick
+struct dis_entry disass_mos6502[]=
+  {
+    { 0xea, 0xff, ' ', 1, "NOP" },
+    { 0x00, 0xff, ' ', 1, "BRK" },
+    { 0x40, 0xff, 'x', 1, "RTI" },
+    { 0x58, 0xff, ' ', 1, "CLI" },
+    { 0x78, 0xff, ' ', 1, "SEI" },
+    { 0x08, 0xff, ' ', 1, "PHP" },
+    { 0x18, 0xff, ' ', 1, "CLC" },
+    { 0x28, 0xff, ' ', 1, "PLP" },
+    { 0x38, 0xff, ' ', 1, "SEC" },
+    { 0x48, 0xff, ' ', 1, "PHA" },
+    { 0x68, 0xff, ' ', 1, "PLA" },
+    { 0x88, 0xff, ' ', 1, "DEY" },
+    { 0x98, 0xff, ' ', 1, "TYA" },
+    { 0xa8, 0xff, ' ', 1, "TAY" },
+    { 0xb8, 0xff, ' ', 1, "CLV" },
+    { 0xc8, 0xff, ' ', 1, "INY" },
+    { 0xd8, 0xff, ' ', 1, "CLD" },
+    { 0xe8, 0xff, ' ', 1, "INX" },
+    { 0xf8, 0xff, ' ', 1, "SED" },
+    { 0x8a, 0xff, ' ', 1, "TXA" },
+    { 0x9a, 0xff, ' ', 1, "TXS" },
+    { 0xaa, 0xff, ' ', 1, "TAX" },
+    { 0xba, 0xff, ' ', 1, "TSX" },
+    { 0xca, 0xff, ' ', 1, "DEX" },
+
+    { 0x01, 0xff, ' ', 2, "ORA %x" },
+    { 0x11, 0xff, ' ', 2, "ORA %y" },
+    { 0x05, 0xff, ' ', 2, "ORA %z" },
+    { 0x15, 0xff, ' ', 2, "ORA %X" },
+    { 0x09, 0xff, ' ', 2, "ORA %#" },
+    { 0x19, 0xff, ' ', 3, "ORA %p" },
+    { 0x0d, 0xff, ' ', 3, "ORA %a" },
+    { 0x1d, 0xff, ' ', 3, "ORA %i" },
+
+    { 0x21, 0xff, ' ', 2, "AND %x" },
+    { 0x31, 0xff, ' ', 2, "AND %y" },
+    { 0x25, 0xff, ' ', 2, "AND %z" },
+    { 0x35, 0xff, ' ', 2, "AND %X" },
+    { 0x29, 0xff, ' ', 2, "AND %#" },
+    { 0x39, 0xff, ' ', 3, "AND %p" },
+    { 0x2d, 0xff, ' ', 3, "AND %a" },
+    { 0x3d, 0xff, ' ', 3, "AND %i" },
+
+    { 0x41, 0xff, ' ', 2, "EOR %x" },
+    { 0x51, 0xff, ' ', 2, "EOR %y" },
+    { 0x45, 0xff, ' ', 2, "EOR %z" },
+    { 0x55, 0xff, ' ', 2, "EOR %X" },
+    { 0x49, 0xff, ' ', 2, "EOR %#" },
+    { 0x59, 0xff, ' ', 3, "EOR %p" },
+    { 0x4d, 0xff, ' ', 3, "EOR %a" },
+    { 0x5d, 0xff, ' ', 3, "EOR %i" },
+
+    { 0x61, 0xff, ' ', 2, "ADC %x" },
+    { 0x71, 0xff, ' ', 2, "ADC %y" },
+    { 0x65, 0xff, ' ', 2, "ADC %z" },
+    { 0x75, 0xff, ' ', 2, "ADC %X" },
+    { 0x69, 0xff, ' ', 2, "ADC %#" },
+    { 0x79, 0xff, ' ', 3, "ADC %p" },
+    { 0x6d, 0xff, ' ', 3, "ADC %a" },
+    { 0x7d, 0xff, ' ', 3, "ADC %i" },
+
+    { 0x81, 0xff, ' ', 2, "STA %x" },
+    { 0x91, 0xff, ' ', 2, "STA %y" },
+    { 0x85, 0xff, ' ', 2, "STA %z" },
+    { 0x95, 0xff, ' ', 2, "STA %X" },
+    { 0x99, 0xff, ' ', 3, "STA %p" },
+    { 0x8d, 0xff, ' ', 3, "STA %a" },
+    { 0x9d, 0xff, ' ', 3, "STA %i" },
+
+    { 0xa1, 0xff, ' ', 2, "LDA %x" },
+    { 0xb1, 0xff, ' ', 2, "LDA %y" },
+    { 0xa5, 0xff, ' ', 2, "LDA %z" },
+    { 0xb5, 0xff, ' ', 2, "LDA %X" },
+    { 0xa9, 0xff, ' ', 2, "LDA %#" },
+    { 0xb9, 0xff, ' ', 3, "LDA %p" },
+    { 0xad, 0xff, ' ', 3, "LDA %a" },
+    { 0xbd, 0xff, ' ', 3, "LDA %i" },
+
+    { 0xc1, 0xff, ' ', 2, "CMP %x" },
+    { 0xd1, 0xff, ' ', 2, "CMP %y" },
+    { 0xc5, 0xff, ' ', 2, "CMP %z" },
+    { 0xd5, 0xff, ' ', 2, "CMP %X" },
+    { 0xc9, 0xff, ' ', 2, "CMP %#" },
+    { 0xd9, 0xff, ' ', 3, "CMP %p" },
+    { 0xcd, 0xff, ' ', 3, "CMP %a" },
+    { 0xdd, 0xff, ' ', 3, "CMP %i" },
+
+    { 0xe1, 0xff, ' ', 2, "SBC %x" },
+    { 0xf1, 0xff, ' ', 2, "SBC %y" },
+    { 0xe5, 0xff, ' ', 2, "SBC %z" },
+    { 0xf5, 0xff, ' ', 2, "SBC %X" },
+    { 0xe9, 0xff, ' ', 2, "SBC %#" },
+    { 0xf9, 0xff, ' ', 3, "SBC %p" },
+    { 0xed, 0xff, ' ', 3, "SBC %a" },
+    { 0xfd, 0xff, ' ', 3, "SBC %i" },
+
+    { 0x84, 0xff, ' ', 2, "STY %z" },
+    { 0x94, 0xff, ' ', 2, "STY %X" },
+    { 0x8c, 0xff, ' ', 3, "STY %a" },
+    { 0x86, 0xff, ' ', 2, "STX %z" },
+    { 0x96, 0xff, ' ', 2, "STX %Y" },
+    { 0x8e, 0xff, ' ', 3, "STX %a" },
+
+    { 0xa0, 0xff, ' ', 2, "LDY %#" },
+    { 0xa4, 0xff, ' ', 2, "LDY %z" },
+    { 0xb4, 0xff, ' ', 2, "LDY %X" },
+    { 0xac, 0xff, ' ', 3, "LDY %a" },
+    { 0xbc, 0xff, ' ', 3, "LDY %i" },
+    { 0xa2, 0xff, ' ', 2, "LDX %#" },
+    { 0xa6, 0xff, ' ', 2, "LDX %z" },
+    { 0xb6, 0xff, ' ', 2, "LDX %Y" },
+    { 0xae, 0xff, ' ', 3, "LDX %a" },
+    { 0xbe, 0xff, ' ', 3, "LDX %p" },
+
+    { 0xc0, 0xff, ' ', 2, "CPY %#" },
+    { 0xc4, 0xff, ' ', 2, "CPY %z" },
+    { 0xcc, 0xff, ' ', 3, "CPY %a" },
+    { 0xe0, 0xff, ' ', 2, "CPX %#" },
+    { 0xe4, 0xff, ' ', 2, "CPX %z" },
+    { 0xec, 0xff, ' ', 3, "CPX %a" },
+
+    { 0xe6, 0xff, ' ', 2, "INC %z" },
+    { 0xf6, 0xff, ' ', 2, "INC %X" },
+    { 0xee, 0xff, ' ', 3, "INC %a" },
+    { 0xfe, 0xff, ' ', 3, "INC %i" },
+    { 0xc6, 0xff, ' ', 2, "DEC %z" },
+    { 0xd6, 0xff, ' ', 2, "DEC %X" },
+    { 0xce, 0xff, ' ', 3, "DEC %a" },
+    { 0xde, 0xff, ' ', 3, "DEC %i" },
+
+    { 0x06, 0xff, ' ', 2, "ASL %z" },
+    { 0x16, 0xff, ' ', 2, "ASL %X" },
+    { 0x0a, 0xff, ' ', 1, "ASL A" },
+    { 0x0e, 0xff, ' ', 3, "ASL %a" },
+    { 0x1e, 0xff, ' ', 3, "ASL %i" },
+
+    { 0x46, 0xff, ' ', 2, "LSR %z" },
+    { 0x56, 0xff, ' ', 2, "LSR %X" },
+    { 0x4a, 0xff, ' ', 1, "LSR A" },
+    { 0x4e, 0xff, ' ', 3, "LSR %a" },
+    { 0x5e, 0xff, ' ', 3, "LSR %i" },
+
+    { 0x26, 0xff, ' ', 2, "ROL %z" },
+    { 0x36, 0xff, ' ', 2, "ROL %X" },
+    { 0x2a, 0xff, ' ', 1, "ROL A" },
+    { 0x2e, 0xff, ' ', 3, "ROL %a" },
+    { 0x3e, 0xff, ' ', 3, "ROL %i" },
+
+    { 0x66, 0xff, ' ', 2, "ROR %z" },
+    { 0x76, 0xff, ' ', 2, "ROR %X" },
+    { 0x6a, 0xff, ' ', 1, "ROR A" },
+    { 0x6e, 0xff, ' ', 3, "ROR %a" },
+    { 0x7e, 0xff, ' ', 3, "ROR %i" },
+
+    { 0x24, 0xff, ' ', 2, "BIT %z" },
+    { 0x2c, 0xff, ' ', 3, "BIT %a" },
+
+    { 0x4c, 0xff, 'j', 3, "JMP %j" },
+    { 0x6c, 0xff, 'x', 3, "JMP %J" },
+    
+    { 0x20, 0xff, 's', 3, "JSR %j" },
+    { 0x60, 0xff, 'x', 1, "RTS" },
+
+    { 0x10, 0xff, 'b', 2, "BPL %r" },
+    { 0x30, 0xff, 'b', 2, "BMI %r" },
+    { 0x50, 0xff, 'b', 2, "BVC %r" },
+    { 0x70, 0xff, 'b', 2, "BVS %r" },
+    { 0x90, 0xff, 'b', 2, "BCC %r" },
+    { 0xb0, 0xff, 'b', 2, "BCS %r" },
+    { 0xd0, 0xff, 'b', 2, "BNE %r" },
+    { 0xf0, 0xff, 'b', 2, "BEQ %r" },
+    
+    { 0, 0, 0, 0, 0, 0 }
+  };
+
+
+struct cpu_entry cpus_6502[]=
+  {
+    {"6502"	, CPU_6502, 0		, "MOS6502", ""},
+    {"02"	, CPU_6502, 0		, "MOS6502", ""},
+    {"65C02"	, CPU_65C02, 0		, "MOS65C02", ""},
+    {"C02"	, CPU_65C02, 0		, "MOS65C02", ""},
+    {"C"	, CPU_65C02, 0		, "MOS65C02", ""},
+    {"6510"	, CPU_6510, 0		, "MOS6510", ""},
+    {"10"	, CPU_6510, 0		, "MOS6510", ""},
+    {"65CE02"	, CPU_65CE02, 0		, "MOS65CE02", ""},
+    {"CE02"	, CPU_65CE02, 0		, "MOS65CE02", ""},
+    {"CE"	, CPU_65CE02, 0		, "MOS65CE02", ""},
+    
+    {NULL, CPU_NONE, 0, "", ""}
+  };
+
+/* End of mos6502.src/glob.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/mos6502.src/glob.h sdcc-4.2.0+dfsg/sim/ucsim/mos6502.src/glob.h
--- sdcc-4.0.0+dfsg/sim/ucsim/mos6502.src/glob.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/mos6502.src/glob.h	2022-01-16 21:17:11.000000000 +0000
@@ -0,0 +1,43 @@
+/*
+ * Simulator of microcontrollers (glob.h)
+ *
+ * Copyright (C) 2020,20 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef GLOB_HEADER
+#define GLOB_HEADER
+
+#include "stypes.h"
+#include "iwrap.h"
+
+
+extern instruction_wrapper_fn itab[256];
+
+extern struct dis_entry disass_mos6502[];
+
+extern struct cpu_entry cpus_6502[];
+
+#endif
+
+/* End of mos6502.src/glob.h */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/mos6502.src/ialu.cc sdcc-4.2.0+dfsg/sim/ucsim/mos6502.src/ialu.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/mos6502.src/ialu.cc	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/mos6502.src/ialu.cc	2022-01-15 21:15:29.000000000 +0000
@@ -0,0 +1,311 @@
+/*
+ * Simulator of microcontrollers (ialu.cc)
+ *
+ * Copyright (C) @@S@@,@@Y@@ Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+
+#include "mos6502cl.h"
+
+
+int
+cl_mos6502::INY(t_mem code)
+{
+  cY.W(rY+1);
+  rF&= ~(flagZ|flagS);
+  if (!rY) rF|= flagZ;
+  if (rY & 0x80) rF|= flagS;
+  cF.W(rF);
+  tick(1);
+  return resGO;
+}
+
+int
+cl_mos6502::INX(t_mem code)
+{
+  cX.W(rX+1);
+  rF&= ~(flagZ|flagS);
+  if (!rX) rF|= flagZ;
+  if (rX & 0x80) rF|= flagS;
+  cF.W(rF);
+  tick(1);
+  return resGO;
+}
+
+int
+cl_mos6502::inc(class cl_cell8 &op)
+{
+  u8_t v;
+  op.W(v= op.R()+1);
+  rF&= ~(flagZ|flagS);
+  if (!v) rF|= flagZ;
+  if (v & 0x80) rF|= flagS;
+  cF.W(rF);
+  return resGO;
+}
+
+int
+cl_mos6502::DEY(t_mem code)
+{
+  cY.W(rY-1);
+  rF&= ~(flagZ|flagS);
+  if (!rY) rF|= flagZ;
+  if (rY & 0x80) rF|= flagS;
+  cF.W(rF);
+  tick(1);
+  return resGO;
+}
+
+int
+cl_mos6502::DEX(t_mem code)
+{
+  cX.W(rX-1);
+  rF&= ~(flagZ|flagS);
+  if (!rX) rF|= flagZ;
+  if (rX & 0x80) rF|= flagS;
+  cF.W(rF);
+  tick(1);
+  return resGO;
+}
+
+int
+cl_mos6502::dec(class cl_cell8 &op)
+{
+  u8_t v;
+  op.W(v= op.R()-1);
+  rF&= ~(flagZ|flagS);
+  if (!v) rF|= flagZ;
+  if (v & 0x80) rF|= flagS;
+  cF.W(rF);
+  return resGO;
+}
+
+int
+cl_mos6502::ora(class cl_cell8 &op)
+{
+  u8_t f= rF & ~(flagZ|flagS);
+  cA.W(rA | op.R());
+  if (!rA) f|= flagZ;
+  if (rA&0x80) f|= flagS;
+  cF.W(f);
+  return resGO;
+}
+
+int
+cl_mos6502::And(class cl_cell8 &op)
+{
+  u8_t f= rF & ~(flagZ|flagS);
+  cA.W(rA & op.R());
+  if (!rA) f|= flagZ;
+  if (rA&0x80) f|= flagS;
+  cF.W(f);
+  return resGO;
+}
+
+int
+cl_mos6502::eor(class cl_cell8 &op)
+{
+  u8_t f= rF & ~(flagZ|flagS);
+  cA.W(rA ^ op.R());
+  if (!rA) f|= flagZ;
+  if (rA&0x80) f|= flagS;
+  cF.W(f);
+  return resGO;
+}
+
+int
+cl_mos6502::adc(class cl_cell8 &op)
+{
+  u8_t Op= op.R(), f, oA= rA;
+  u16_t res;
+  u8_t C= (rF&flagC)?1:0;
+  f= rF & ~(flagZ|flagC|flagN);
+
+  if (!(rF & flagD))
+    {
+      f&= ~flagV;
+      res= rA + Op + C;
+      cA.W(res);
+      if (!rA) f|= flagZ;
+      if (rA & 0x80) f|= flagN;
+      if (res > 255) f|= flagC;
+      if ( ((res^oA)&0x80) && !((oA^Op)&0x80) ) f|= flagV;
+    }
+  else
+    {
+      int opint= ((Op & 0xf0) >> 4) * 10;
+      opint+= (Op & 0x0f);
+      int accint= ((oA & 0xf0) >> 4) * 10;
+      accint+= (oA & 0x0f);
+      int sum= opint + accint + C;
+      if (sum > 99)
+	{
+	  f|= flagC;
+	  sum-= 100;
+	}
+      else
+	{
+	  f&= ~flagC;
+	}
+      u8_t resA= 0;
+      if (sum >= 0 && sum < 100)
+	{
+	  int tens= sum/10;
+	  int units= sum%10;
+	  resA= ((u8_t)tens << 4 | (u8_t)units);
+	}
+      cA.W(resA);
+      if (!resA) f|= flagZ;
+      if (resA&0x80) f|= flagN;
+    }
+  cF.W(f);
+  return resGO;
+}
+
+int
+cl_mos6502::sbc(class cl_cell8 &op)
+{
+  u8_t Op= op.R();
+  u16_t res;
+  u8_t C= (rF&flagC)?1:0;
+  u8_t f= rF & ~(flagC|flagZ|flagN);
+  
+  if (!(rF & flagD))
+    {
+      f&= ~flagV;
+      res= rA-Op-1+C;
+      if (0x80&( (res&Op&~rA) | (~res&~Op&rA) )) f|= flagV;
+      if (res < 0x100) f|= flagC;
+      if (!(res & 0xff)) f|= flagZ;
+      if (res & 0x80) f|= flagN;
+      cA.W(res);
+    }
+  else
+    {
+      int opint= ((Op & 0xf0) >> 4) * 10;
+      opint+= (Op & 0x0f);
+      int accint= ((rA & 0xf0) >> 4) * 10;
+      accint+= (rA & 0x0f);
+      int res= accint - opint - (C?0:1);
+      if (res < 0)
+	{
+	  f&= ~flagC;
+	  res+= 100;
+	}
+      else
+	f|= flagC;
+      u8_t resA= 0;
+      if (res >= 0 && res < 100)
+	{
+	  int tens= res / 10;
+	  int units= res % 10;
+	  resA= ((u8_t)tens << 4 | (u8_t)units);
+	}
+      if (!resA) f|= flagZ;
+      if (resA&0x80) f|= flagN;
+      cA.W(resA);
+    }
+  cF.W(f);
+  return resGO;
+}
+
+int
+cl_mos6502::cmp(class cl_cell8 &op1, class cl_cell8 &op2)
+{
+  u16_t res= op1.R() - op2.R();
+  u8_t f= rF & ~(flagZ|flagN|flagC);
+  if (res < 256) f|= flagC;
+  if (!(res&0xff)) f|= flagZ;
+  if (res&0x80) f|= flagN;
+  cF.W(f);
+  return resGO;
+}
+
+int
+cl_mos6502::asl(class cl_cell8 &op)
+{
+  u8_t f= rF & ~(flagZ|flagN|flagC);
+  u8_t v= op.R();
+  if (v&0x80) f|= flagC;
+  op.W(v<<=1);
+  if (!v) f|= flagZ;
+  if (v&0x80) f|= flagN;
+  cF.W(f);
+  return resGO;
+}
+
+int
+cl_mos6502::lsr(class cl_cell8 &op)
+{
+  u8_t f= rF & ~(flagZ|flagN|flagC);
+  u8_t v= op.R();
+  if (v&1) f|= flagC;
+  op.W(v>>=1);
+  if (!v) f|= flagZ;
+  cF.W(f);
+  return resGO;
+}
+
+int
+cl_mos6502::rol(class cl_cell8 &op)
+{
+  u8_t C= (rF&flagC)?1:0;
+  u8_t f= rF & ~(flagZ|flagN|flagC);
+  u8_t v= op.R();
+  if (v&0x80) f|= flagC;
+  v= (v<<1)|C;
+  op.W(v);
+  if (!v) f|= flagZ;
+  if (v&0x80) f|= flagN;
+  cF.W(f);
+  return resGO;
+}
+
+int
+cl_mos6502::ror(class cl_cell8 &op)
+{
+  u8_t C= (rF&flagC)?0x80:0;
+  u8_t f= rF & ~(flagZ|flagN|flagC);
+  u8_t v= op.R();
+  if (v&1) f|= flagC;
+  v= (v>>1)|C;
+  op.W(v);
+  if (!v) f|= flagZ;
+  if (v&0x80) f|= flagN;
+  cF.W(f);
+  return resGO;
+}
+
+int
+cl_mos6502::bit(class cl_cell8 &op)
+{
+  u8_t v= op.R();
+  u8_t f= rF & ~(flagZ|flagN|flagV);
+  if (v&0x80) f|= flagN;
+  if (v&0x40) f|= flagV;
+  if (!(rA & v)) f|= flagZ;
+  cF.W(f);
+  return resGO;
+}
+
+
+/* End of mos6502.src/ialu.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/mos6502.src/ibranch.cc sdcc-4.2.0+dfsg/sim/ucsim/mos6502.src/ibranch.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/mos6502.src/ibranch.cc	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/mos6502.src/ibranch.cc	2022-01-15 21:15:29.000000000 +0000
@@ -0,0 +1,103 @@
+/*
+ * Simulator of microcontrollers (ibranch.cc)
+ *
+ * Copyright (C) @@S@@,@@Y@@ Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+
+#include "appcl.h"
+
+#include "mos6502cl.h"
+
+
+int
+cl_mos6502::JMPa(t_mem code)
+{
+  u16_t a= i16();
+  PC= a;
+  tick(2);
+  return resGO;
+}
+
+int
+cl_mos6502::JMPi(t_mem code)
+{
+  u16_t a= i16();
+  a= read_addr(rom, a);
+  PC= a;
+  vc.rd+= 2;
+  tick(4);
+  return resGO;
+}
+
+int
+cl_mos6502::JSR(t_mem code)
+{
+  u16_t a= fetch(); // low
+  t_addr pc= PC;
+  t_addr spbef= rSP;
+  a+= (fetch()*256); // high
+  push_addr(pc);
+  class cl_stack_call *op= new cl_stack_call(instPC, a, PC, spbef, rSP);
+  op->init();
+  stack_write(op);
+  PC= a;
+  return resGO;
+}
+
+int
+cl_mos6502::RTS(t_mem code)
+{
+  t_addr spbef= rSP;
+  PC= pop_addr()+1;
+  class cl_stack_ret *op= new cl_stack_ret(instPC, PC, spbef, rSP);
+  op->init();
+  stack_read(op);
+  tick(3);
+  return resGO;
+}
+
+int
+cl_mos6502::branch(bool cond)
+{
+  i8_t rel;
+  u16_t a;
+  if (!jaj)
+    rel= fetch();
+  if (cond)
+    {
+      if (jaj)
+	rel= fetch();
+      a= PC+rel;
+      if ((PC&0xff00) != (a&0xff00))
+	tick(1);
+      PC= a;
+      tick(1);
+    }
+  else if (jaj)
+    PC++;
+  tick(1);
+  return resGO;
+}
+
+
+/* End of mos6502.src/ibranch.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/mos6502.src/imove.cc sdcc-4.2.0+dfsg/sim/ucsim/mos6502.src/imove.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/mos6502.src/imove.cc	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/mos6502.src/imove.cc	2022-01-15 21:15:29.000000000 +0000
@@ -0,0 +1,159 @@
+/*
+ * Simulator of microcontrollers (imove.cc)
+ *
+ * Copyright (C) @@S@@,@@Y@@ Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+
+#include "mos6502cl.h"
+
+
+int
+cl_mos6502::TYA(t_mem code)
+{
+  cA.W(rY);
+  if (rA)
+    rF&= ~flagZ;
+  else
+    rF|= flagZ;
+  if (rA & 0x80)
+    rF|= flagS;
+  else
+    rF&= ~flagS;
+  cF.W(rF);
+  tick(1);
+  return resGO;
+}
+
+int
+cl_mos6502::TAY(t_mem code)
+{
+  cY.W(rA);
+  if (rY)
+    rF&= ~flagZ;
+  else
+    rF|= flagZ;
+  if (rY & 0x80)
+    rF|= flagS;
+  else
+    rF&= ~flagS;
+  cF.W(rF);
+  tick(1);
+  return resGO;
+}
+
+int
+cl_mos6502::TXA(t_mem code)
+{
+  cA.W(rX);
+  if (rA)
+    rF&= ~flagZ;
+  else
+    rF|= flagZ;
+  if (rA & 0x80)
+    rF|= flagS;
+  else
+    rF&= ~flagS;
+  cF.W(rF);
+  tick(1);
+  return resGO;
+}
+
+int
+cl_mos6502::TXS(t_mem code)
+{
+  cSP.W(rX);
+  tick(1);
+  return resGO;
+}
+
+int
+cl_mos6502::TAX(t_mem code)
+{
+  cX.W(rA);
+  if (rX)
+    rF&= ~flagZ;
+  else
+    rF|= flagZ;
+  if (rX & 0x80)
+    rF|= flagS;
+  else
+    rF&= ~flagS;
+  cF.W(rF);
+  tick(1);
+  return resGO;
+}
+
+int
+cl_mos6502::TSX(t_mem code)
+{
+  cX.W(rSP);
+  if (rX)
+    rF&= ~flagZ;
+  else
+    rF|= flagZ;
+  if (rX & 0x80)
+    rF|= flagS;
+  else
+    rF&= ~flagS;
+  cF.W(rF);
+  tick(1);
+  return resGO;
+}
+
+int
+cl_mos6502::st(u8_t reg, class cl_cell8 &op)
+{
+  op.W(reg);
+  return resGO;
+}
+
+int
+cl_mos6502::sta(class cl_cell8 &op)
+{
+  op.W(rA);
+  return resGO;
+}
+
+int
+cl_mos6502::lda(class cl_cell8 &op)
+{
+  u8_t f= rF & ~(flagZ|flagN);
+  cA.W(op.R());
+  if (!rA) f|= flagZ;
+  if (rA & 0x80) f|= flagN;
+  cF.W(f);
+  return resGO;
+}
+
+int
+cl_mos6502::ld(class cl_cell8 ®, class cl_cell8 &op)
+{
+  u8_t v, f= rF & ~(flagZ|flagN);
+  reg.W(v= op.R());
+  if (!v) f|= flagZ;
+  if (v & 0x80) f|= flagN;
+  cF.W(f);
+  return resGO;
+}
+
+/* End of mos6502.src/imove.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/mos6502.src/inst.cc sdcc-4.2.0+dfsg/sim/ucsim/mos6502.src/inst.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/mos6502.src/inst.cc	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/mos6502.src/inst.cc	2022-01-15 21:15:29.000000000 +0000
@@ -0,0 +1,195 @@
+/*
+ * Simulator of microcontrollers (inst.cc)
+ *
+ * Copyright (C) @@S@@,@@Y@@ Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+
+#include "globals.h"
+
+#include "mos6502cl.h"
+
+int
+cl_mos6502::NOP(t_mem code)
+{
+  return resGO;
+}
+
+int
+cl_mos6502::BRK(t_mem code)
+{
+  set_b= true;
+  PC= (PC+1)&0xffff;//fetch();
+  cF.W(rF|flagB);
+  src_brk->request();
+  return resGO;
+}
+
+int
+cl_mos6502::RTI(t_mem code)
+{
+  u8_t f;
+  cSP.W(rSP+1);
+  f= rom->read(0x0100 + rSP);
+  f&= ~(0x20|flagB);
+  cF.W(f);
+  vc.rd+= 1;
+  /*cSP.W(rSP+1);
+  l= rom->read(0x0100 + rSP);
+  cSP.W(rSP+1);
+  h= rom->read(0x0100 + rSP);*/
+  PC= pop_addr();//h*256 + l;
+  {
+    class it_level *il= (class it_level *)(it_levels->top());
+    if (il &&
+	il->level >= 0)
+      {
+	il= (class it_level *)(it_levels->pop());
+	delete il;
+      }
+  }
+  tick(3);
+  return resGO;
+}
+
+int
+cl_mos6502::CLI(t_mem code)
+{
+  cF.W(rF&= ~flagI);
+  tick(1);
+  return resGO;
+}
+
+int
+cl_mos6502::SEI(t_mem code)
+{
+  cF.W(rF|= flagI);
+  tick(1);
+  return resGO;
+}
+
+int
+cl_mos6502::PHP(t_mem code)
+{
+  u8_t v= rF|0x20|flagB;
+  rom->write(0x0100 + rSP, v);
+  vc.wr++;
+  t_addr spbef= rSP;
+  cSP.W(rSP-1);
+  class cl_stack_push *op= new cl_stack_push(instPC, v, spbef, rSP);
+  op->init();
+  stack_write(op);
+  tick(2);
+  return resGO;
+}
+
+int
+cl_mos6502::CLC(t_mem code)
+{
+  cF.W(rF&= ~flagC);
+  tick(1);
+  return resGO;
+}
+
+int
+cl_mos6502::PLP(t_mem code)
+{
+  t_addr spbef= rSP;
+  cSP.W(rSP+1);
+  u8_t v= rom->read(0x0100 + rSP);
+  v&= ~(0x20|flagB);
+  class cl_stack_pop *op= new cl_stack_pop(instPC, v, spbef, rSP);
+  op->init();
+  stack_read(op);
+  cF.W(v);
+  vc.rd++;
+  tick(3);
+  return resGO;
+}
+
+int
+cl_mos6502::SEc(t_mem code)
+{
+  cF.W(rF|= flagC);
+  tick(1);
+  return resGO;
+}
+
+int
+cl_mos6502::PHA(t_mem code)
+{
+  rom->write(0x0100 + rSP, rA);
+  vc.wr++;
+  t_addr spbef= rSP;
+  cSP.W(rSP-1);
+  class cl_stack_push *op= new cl_stack_push(instPC, rA, spbef, rSP);
+  op->init();
+  stack_write(op);
+  tick(2);
+  return resGO;
+}
+
+int
+cl_mos6502::PLA(t_mem code)
+{
+  t_addr spbef= rSP;
+  cSP.W(rSP+1);
+  cA.W(rom->read(0x0100 + rSP));
+  class cl_stack_pop *op= new cl_stack_pop(instPC, rA, spbef, rSP);
+  op->init();
+  stack_read(op);
+  u8_t f= rF & ~(flagN|flagZ);
+  if (!rA) f|= flagZ;
+  if (rA&0x80) f|= flagN;
+  cF.W(f);
+  vc.rd++;
+  tick(3);
+  return resGO;
+}
+
+int
+cl_mos6502::CLV(t_mem code)
+{
+  cF.W(rF&= ~flagV);
+  tick(1);
+  return resGO;
+}
+
+int
+cl_mos6502::CLD(t_mem code)
+{
+  cF.W(rF&= ~flagD);
+  tick(1);
+  return resGO;
+}
+
+
+int
+cl_mos6502::SED(t_mem code)
+{
+  cF.W(rF|= flagD);
+  tick(1);
+  return resGO;
+}
+
+
+/* End of mos6502.src/inst.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/mos6502.src/irq.cc sdcc-4.2.0+dfsg/sim/ucsim/mos6502.src/irq.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/mos6502.src/irq.cc	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/mos6502.src/irq.cc	2022-01-15 21:15:29.000000000 +0000
@@ -0,0 +1,98 @@
+/*
+ * Simulator of microcontrollers (irq.cc)
+ *
+ * Copyright (C) @@S@@,@@Y@@ Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+
+#include "globals.h"
+#include "utils.h"
+
+#include "irqcl.h"
+
+
+/* IRQ handling peripheral */
+
+cl_irq_hw::cl_irq_hw(class cl_uc *auc):
+  cl_hw(auc, HW_INTERRUPT, 0, "irq")
+{
+  muc= (class cl_mos6502 *)auc;
+}
+
+int
+cl_irq_hw::init()
+{
+  class cl_var *v;
+
+  cl_hw::init();
+  uc->vars->add(v= new cl_var("NMI", cfg, m65_nmi, "NMI request/clear"));
+  v->init();
+  uc->vars->add(v= new cl_var("IRQ", cfg, m65_irq, "IRQ request/clear"));
+  v->init();
+  uc->vars->add(v= new cl_var("BRK", cfg, m65_brk, "BRK request/clear"));
+  v->init();
+
+  cfg_cell(m65_nmi_en)->set(1);
+  cfg_cell(m65_brk_en)->set(1);
+
+  return 0;
+}
+
+void
+cl_irq_hw::print_info(class cl_console_base *con)
+{
+  int i;
+  con->dd_printf("  Handler  ISR    En  Pr Req Act Name\n");
+  for (i= 0; i < uc->it_sources->count; i++)
+    {
+      class cl_it_src *is=
+	(class cl_it_src *)(uc->it_sources->at(i));
+      class cl_it_src *pa= is->get_parent();
+      class cl_it_src *isp= (pa)?pa:is;
+      t_addr a= uc->read_addr(uc->rom, isp->addr);
+      con->dd_printf("  [0x%04x] 0x%04x", AU(isp->addr), a);
+      con->dd_printf(" %-3s", (is->enabled())?"en":"dis");
+      con->dd_printf(" %2d", uc->priority_of(is->nuof));
+      con->dd_printf(" %-3s", (is->pending())?"YES":"no");
+      con->dd_printf(" %-3s", (is->active)?"act":"no");
+      con->dd_printf(" %s", object_name(is));
+      con->dd_printf("\n");
+    }
+  con->dd_printf("Active interrupt service(s):\n");
+  con->dd_printf("  Pr Handler  PC       Source\n");
+  for (i= 0; i < uc->it_levels->count; i++)
+    {
+      class it_level *il= (class it_level *)(uc->it_levels->at(i));
+      if (il->level >= 0)
+	{
+	  con->dd_printf("  %2d", il->level);
+	  con->dd_printf(" 0x%06x", AU(il->addr));
+	  con->dd_printf(" 0x%06x", AU(il->PC));
+	  con->dd_printf(" %s", (il->source)?(object_name(il->source)):
+			 "nothing");
+	  con->dd_printf("\n");
+	}
+    }
+}
+
+
+/* End of mos6502.src/irq.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/mos6502.src/irqcl.h sdcc-4.2.0+dfsg/sim/ucsim/mos6502.src/irqcl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/mos6502.src/irqcl.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/mos6502.src/irqcl.h	2022-01-15 21:15:29.000000000 +0000
@@ -0,0 +1,60 @@
+/*
+ * Simulator of microcontrollers (irqcl.h)
+ *
+ * Copyright (C) @@S@@,@@Y@@ Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+
+#ifndef IRQCL_HEADER
+#define IRQCL_HEADER
+
+#include "hwcl.h"
+
+#include "mos6502cl.h"
+
+enum irq_cfg
+  {
+    m65_nmi_en	= 0,
+    m65_nmi	= 1,
+    m65_irq_en	= 2,
+    m65_irq	= 3,
+    m65_brk_en	= 4,
+    m65_brk	= 5,
+    m65_nr	= 6
+  };
+
+// IRQ peripheral
+class cl_irq_hw: public cl_hw
+{
+ public:
+  class cl_mos6502 *muc;
+ public:
+  cl_irq_hw(class cl_uc *auc);
+  virtual int init(void);
+  virtual unsigned int cfg_size(void) { return m65_nr; }
+  virtual void print_info(class cl_console_base *con);  
+};
+
+
+#endif
+
+/* End of mos6502.src/irqcl.h */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/mos6502.src/Makefile.in sdcc-4.2.0+dfsg/sim/ucsim/mos6502.src/Makefile.in
--- sdcc-4.0.0+dfsg/sim/ucsim/mos6502.src/Makefile.in	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/mos6502.src/Makefile.in	2022-01-16 21:17:11.000000000 +0000
@@ -0,0 +1,192 @@
+#
+# uCsim mos6502.src/Makefile
+#
+# (c) Drotos Daniel, Talker Bt. 1997
+#
+
+# tool name
+TN		= mos6502
+
+STARTYEAR	= 1997
+
+SHELL		= /bin/sh
+CXX		= @CXX@
+CPP		= @CPP@
+CXXCPP		= @CXXCPP@
+RANLIB		= @RANLIB@
+INSTALL		= @INSTALL@
+STRIP		= @STRIP@
+MAKEDEP         = @MAKEDEP@
+
+top_builddir	= @top_builddir@
+top_srcdir	= @top_srcdir@
+
+transform	= @program_transform_name@
+
+DEFS            = $(subs -DHAVE_CONFIG_H,,@DEFS@)
+CPPFLAGS        = @CPPFLAGS@ -I$(srcdir) -I$(top_srcdir) -I$(top_builddir) \
+		  -I$(top_srcdir)/cmd.src -I$(top_srcdir)/sim.src \
+		  -I$(top_srcdir)/gui.src
+CFLAGS          = @WALL_FLAG@ @CFLAGS@
+CXXFLAGS        = @WALL_FLAG@ @CXXFLAGS@
+LDFLAGS         = @LDFLAGS@
+PICOPT		= @PICOPT@
+SHAREDLIB	= @SHAREDLIB@
+EXEEXT		= @EXEEXT@
+
+LIBS		= -L$(top_builddir) -lsim -lucsimutil -lguiucsim -lcmd -lsim @LIBS@
+DL		= @DL@
+dl_ok		= @dl_ok@
+
+prefix          = @prefix@
+exec_prefix     = @exec_prefix@
+bindir          = @bindir@
+libdir          = @libdir@
+datadir         = @datadir@
+datarootdir     = @datarootdir@
+includedir      = @includedir@
+mandir          = @mandir@
+man1dir         = $(mandir)/man1
+man2dir         = $(mandir)/man2
+infodir         = @infodir@
+srcdir          = @srcdir@
+VPATH           = @srcdir@
+
+OBJECTS_SHARED	= sim$(TN).o $(TN).o glob.o irq.o \
+		  inst.o ialu.o ibranch.o imove.o \
+		  mos65c02.o mos6510.o mos65ce02.o
+
+OBJECTS_EXE	= s$(TN).o
+OBJECTS		= $(OBJECTS_SHARED) $(OBJECTS_EXE)
+
+# short/long exe and lib name
+SEN		= s$(TN)$(EXEEXT)
+LEN		= ucsim_$(TN)$(EXEEXT)
+LENOLD		= ucsim_mcs6502$(EXEEXT)
+
+SONAME		= libucsim_$(TN).so
+
+enable_dlso	= @enable_dlso@
+dlso_ok		= @dlso_ok@
+
+MOS6502ASM	=
+TEST_OBJ	= 
+
+
+# Compiling entire program or any subproject
+# ------------------------------------------
+all: checkconf otherlibs $(TN).src
+
+
+# Compiling and installing everything and runing test
+# ---------------------------------------------------
+install: all installdirs install_shared_lib
+	$(INSTALL) $(SEN) $(DESTDIR)$(bindir)/$(SEN)
+	$(STRIP) $(DESTDIR)$(bindir)/$(SEN)
+	$(INSTALL) $(LEN) $(DESTDIR)$(bindir)/$(LEN)
+	$(INSTALL) $(LENOLD) $(DESTDIR)$(bindir)/$(LENOLD)
+	$(STRIP) $(DESTDIR)$(bindir)/$(LEN)
+	$(STRIP) $(DESTDIR)$(bindir)/$(LENOLD)
+
+
+# Deleting all the installed files
+# --------------------------------
+uninstall:
+	rm -f $(DESTDIR)$(bindir)/$(SEN)
+	rm -f $(DESTDIR)$(bindir)/$(LEN)
+	rm -f $(DESTDIR)$(bindir)/$(LENOLD)
+	rm -f $(DESTDIR)$(libdir)/$(SONAME)
+
+
+# Performing self-test
+# --------------------
+check: $(TEST_OBJ)
+
+.PHONY:	test baseline
+test:
+	@$(MAKE) --no-print-directory -C test
+
+baseline:
+	@$(MAKE) --no-print-directory -C test baseline
+
+
+# Performing installation test
+# ----------------------------
+installcheck:
+
+
+# Creating installation directories
+# ---------------------------------
+installdirs:
+	test -d $(DESTDIR)$(bindir) || $(INSTALL) -d $(DESTDIR)$(bindir)
+
+
+# Creating dependencies
+# ---------------------
+dep: Makefile.dep
+
+Makefile.dep: $(srcdir)/*.cc $(srcdir)/*.h
+	$(MAKEDEP) $(CPPFLAGS) $(filter %.cc,$^) >Makefile.dep
+
+-include Makefile.dep
+include $(srcdir)/clean.mk
+
+# My rules
+# --------
+.SUFFIXES: .asm .hex
+
+$(TN).src: $(SEN) $(LEN) $(LENOLD) shared_lib
+
+$(SEN): $(OBJECTS) $(top_builddir)/libcmd.a $(top_builddir)/libguiucsim.a $(top_builddir)/libsim.a $(top_builddir)/libucsimutil.a
+	$(CXX) $(CXXFLAGS) $(LDFLAGS) $(OBJECTS) $(LIBS) -o $@
+
+$(LEN): $(SEN)
+	cp $< $@
+
+$(LENOLD): $(SEN)
+	cp $< $@
+
+ifeq ($(dlso_ok),yes)
+shared_lib: $(top_builddir)/$(SONAME)
+install_shared_lib: shared_lib
+	test -d $(DESTDIR)$(libdir) || $(INSTALL) -d $(DESTDIR)$(libdir)
+	$(INSTALL) $(top_builddir)/$(SONAME) $(DESTDIR)$(libdir)/$(SONAME)
+else
+shared_lib:
+	@$(top_srcdir)/mkecho $(top_builddir) "No $(TN) shared lib made."
+	@$(top_srcdir)/mkecho $(top_builddir) "(SHAREDLIB="$(SHAREDLIB)",dl_ok="$(dl_ok)",enable_dlso="$(enable_dlso)")"
+install_shared_lib:
+endif
+
+$(top_builddir)/$(SONAME): $(OBJECTS_SHARED)
+	$(CXX) -shared $(LDFLAGS) $(OBJECTS_SHARED) -o $@
+
+otherlibs: $(top_builddir)/libcmd.a $(top_builddir)/libguiucsim.a $(top_builddir)/libsim.a $(top_builddir)/libucsimutil.a
+
+$(top_builddir)/libcmd.a:
+	$(MAKE) -C $(top_builddir)/cmd.src all
+
+$(top_builddir)/libguiucsim.a:
+	$(MAKE) -C $(top_builddir)/gui.src checkconf ucsim_lib
+
+$(top_builddir)/libsim.a:
+	$(MAKE) -C $(top_builddir)/sim.src all
+
+$(top_builddir)/libucsimutil.a:
+	$(MAKE) -C $(top_builddir) -f main.mk
+
+.cc.o:
+	$(CXX) $(CXXFLAGS) $(PICOPT) $(CPPFLAGS) $(TARGET_ARCH) -c $< -o $@
+
+.asm.hex:
+	$(MOS6502ASM) -l $< -o $@ -e $<.lst
+
+
+# Remaking configuration
+# ----------------------
+checkconf:
+	@if [ -f $(top_builddir)/devel ]; then\
+	  $(MAKE) -C $(top_builddir) -f conf.mk srcdir="$(srcdir)" top_builddir="$(top_builddir)" freshconf;\
+	fi
+
+# End of mos6502.src/Makefile.in
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/mos6502.src/mos6502.cc sdcc-4.2.0+dfsg/sim/ucsim/mos6502.src/mos6502.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/mos6502.src/mos6502.cc	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/mos6502.src/mos6502.cc	2022-01-24 11:09:43.000000000 +0000
@@ -0,0 +1,726 @@
+/*
+ * Simulator of microcontrollers (mos6502.cc)
+ *
+ * Copyright (C) 2020,20 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#include 
+#include 
+
+#include "appcl.h"
+#include "globals.h"
+#include "utils.h"
+
+#include "dregcl.h"
+
+#include "glob.h"
+#include "irqcl.h"
+
+#include "mos6502cl.h"
+
+
+static class cl_console_base *c;
+static u16_t dbg_a;
+
+static int
+con()
+{
+  if (!jaj) return 0;
+  c= application->get_commander()->frozen_console;
+  return c!=NULL;
+}
+
+int
+ccn(class cl_memory_cell *c)
+{
+  if (!jaj) return 0;
+  cl_address_space *rom= application->sim->uc->rom;
+  t_addr a;
+  if (!rom) return 0;
+  if (!rom->is_owned(c, &a)) return 0;
+  dbg_a= a;
+  return con();
+}
+
+static cl_c65 c65_tmpl;
+
+class cl_memory_cell *
+cl_as65::cell_template()
+{
+  return &c65_tmpl;
+}
+
+#ifdef DEVEL
+t_mem
+cl_c65::read(void)
+{
+  t_mem v= cl_cell8::read();
+  if (ccn(this)) c->dd_printf("R[%04x]-> %02x\n", dbg_a, u8_t(v));
+  return v;
+}
+#endif
+
+#ifdef DEVEL
+t_mem
+cl_c65::get(void)
+{
+  t_mem v= cl_cell8::get();
+  if (ccn(this)) c->dd_printf("R[%04x]-> %02x\n", dbg_a, u8_t(v));
+  return v;
+}
+#endif
+
+#ifdef DEVEL
+t_mem
+cl_c65::write(t_mem val)
+{
+  t_mem v= cl_cell8::get();
+  if (ccn(this)) c->dd_printf("W[%04x] %02x <- %02x\n", dbg_a, u8_t(v), u8_t(val));
+  v= cl_cell8::write(val);
+  return v;
+}
+#endif
+
+#ifdef DEVEL
+t_mem
+cl_c65::set(t_mem val)
+{
+  t_mem v= cl_cell8::get();
+  if (ccn(this)) c->dd_printf("W[%04x] %02x <- %02x\n", dbg_a, u8_t(v), u8_t(val));
+  v= cl_cell8::set(val);
+  return v;
+}
+#endif
+
+cl_mos6502::cl_mos6502(class cl_sim *asim):
+  cl_uc(asim)
+{
+}
+
+int
+cl_mos6502::init(void)
+{
+  cl_uc::init();
+  fill_def_wrappers(itab);
+
+  set_xtal(1000000);
+    
+#define RCV(R) reg_cell_var(&c ## R , &r ## R , "" #R "" , "CPU register " #R "")
+  RCV(A);
+  RCV(X);
+  RCV(Y);
+  RCV(SP);
+  RCV(P);
+#undef RCV
+  ci8.decode(&i8d);
+  
+  class cl_memory_operator *op= new cl_cc_operator(&cCC);
+  cCC.append_operator(op);
+
+  for (int i= 0; i<=0xffff; i++) rom->set(i,0);
+  
+  return 0;
+}
+
+
+const char *
+cl_mos6502::id_string(void)
+{
+  return "MOS6502";
+}
+
+void
+cl_mos6502::reset(void)
+{
+  cl_uc::reset();
+
+  CC= 0x00 | flagI;
+  PC= read_addr(rom, RESET_AT);
+  rSP= 0xfd;
+  
+  tick(7);
+}
+
+  
+void
+cl_mos6502::set_PC(t_addr addr)
+{
+  PC= addr;
+}
+
+void
+cl_mos6502::mk_hw_elements(void)
+{
+  class cl_hw *h;
+  
+  cl_uc::mk_hw_elements();
+
+  add_hw(h= new cl_dreg(this, 0, "dreg"));
+  h->init();
+
+  add_hw(h= new cl_irq_hw(this));
+  h->init();
+
+  src_irq= new cl_it_src(this,
+			 irq_irq,
+			 &cCC, flagI,
+			 h->cfg_cell(m65_irq), 1,
+			 IRQ_AT, false, true,
+			 "Interrupt request",
+			 0);
+  src_irq->set_cid('i');
+  src_irq->set_ie_value(0);
+  src_irq->init();
+  it_sources->add(src_irq);
+  
+  src_nmi= new cl_it_src(this,
+			 irq_nmi,
+			 h->cfg_cell(m65_nmi_en), 1,
+			 h->cfg_cell(m65_nmi), 1,
+			 NMI_AT, false, true,
+			 "Non-maskable interrupt request",
+			 0);
+  src_nmi->set_cid('n');
+  src_nmi->set_nmi(true);
+  src_nmi->init();
+  it_sources->add(src_nmi);
+  
+  src_brk= new cl_it_src(this,
+			 irq_brk,
+			 h->cfg_cell(m65_brk_en), 1,
+			 h->cfg_cell(m65_brk), 1,
+			 IRQ_AT, true, true,
+			 "BRK",
+			 0);
+  src_brk->set_cid('b');
+  src_brk->init();
+  src_brk->set_nmi(true);
+  it_sources->add(src_brk);
+}
+
+void
+cl_mos6502::make_cpu_hw(void)
+{
+}
+
+void
+cl_mos6502::make_memories(void)
+{
+  class cl_address_space *as;
+  class cl_address_decoder *ad;
+  class cl_memory_chip *chip;
+  
+  rom= as= new cl_as65("rom", 0, 0x10000, 8);
+  as->init();
+  address_spaces->add(as);
+
+  chip= new cl_chip8("rom_chip", 0x10000, 8);
+  chip->init();
+  memchips->add(chip);
+  ad= new cl_address_decoder(as= rom,
+			     chip, 0, 0xffff, 0);
+  ad->init();
+  as->decoders->add(ad);
+  ad->activate(0);
+}
+
+struct dis_entry *
+cl_mos6502::dis_tbl(void)
+{
+  return(disass_mos6502);
+}
+
+struct dis_entry *
+cl_mos6502::get_dis_entry(t_addr addr)
+{
+  t_mem code= rom->get(addr);
+
+  for (struct dis_entry *de = dis_tbl(); de && de->mnemonic; de++)
+    {
+      if ((code & de->mask) == de->code)
+        return de;
+    }
+
+  return NULL;
+}
+
+void
+cl_mos6502::analyze_start(void)
+{
+  struct {
+    const char *name;
+    t_addr vector, addr;
+  } vectors[] = {
+    { ".reset", RESET_AT },
+    { ".nmi",   NMI_AT },
+    { ".irq",   IRQ_AT },
+  };
+
+  for (size_t i = 0; i < sizeof(vectors) / sizeof(vectors[0]); i++)
+    {
+      vectors[i].addr = read_addr(rom, vectors[i].vector);
+      class cl_var *v = new cl_var(vectors[i].name, rom, vectors[i].addr, chars("Auto-generated by analyze"), -1, -1);
+      v->init();
+      vars->add(v);
+    }
+
+  for (size_t i = 0; i < sizeof(vectors) / sizeof(vectors[0]); i++)
+    analyze(vectors[i].addr);
+}
+
+void
+cl_mos6502::analyze(t_addr addr)
+{
+  struct dis_entry *de;
+
+  while (!inst_at(addr) && (de = get_dis_entry(addr)))
+    {
+      set_inst_at(addr);
+
+      if (de->branch != ' ')
+        {
+          t_addr target = addr;
+
+          switch (de->branch)
+            {
+              case 'x': // Returns or indirect jumps that end this execution path immediately
+                return;
+
+              case 's': // Subroutine calls
+              case 'j': // Unconditional jumps
+                target= rom->read(addr+1) + (rom->read(addr+2) << 8);
+                break;
+
+              case 'b': // Conditional branches
+                target= addr + 2 + (i8_t)rom->read(addr+1);
+                break;
+
+              default:
+                break;
+            }
+
+          analyze_jump(addr, target, de->branch);
+
+          // Unconditional jumps end this execution path
+          if (de->branch == 'j')
+            break;
+        }
+
+      addr= rom->validate_address(addr + de->length);
+    }
+}
+
+char *
+cl_mos6502::disassc(t_addr addr, chars *comment)
+{
+  chars work= chars(), temp= chars();
+  const char *b;
+  struct dis_entry *de;
+  int i;
+  bool first;
+  u8_t h, l;
+  u16_t a;
+
+  de= get_dis_entry(addr);
+
+  if (!de || !de->mnemonic)
+    return strdup("-- UNKNOWN/INVALID");
+
+  b= de->mnemonic;
+
+  first= true;
+  work= "";
+  for (i=0; b[i]; i++)
+    {
+      if ((b[i] == ' ') && first)
+	{
+	  first= false;
+	  while (work.len() < 6) work.append(' ');
+	}
+      if (b[i] == '%')
+	{
+	  i++;
+	  temp= "";
+	  switch (b[i])
+	    {
+	    case 'x': // (ind,X)
+	      l= rom->read(addr+1);
+	      work.appendf("($%02x", l);
+	      addr_name(l, rom, &work);
+	      work.append(",X)");
+	      l+= rX;
+	      a= read_addr(rom, l);
+	      temp.appendf("; [$%04x]=$%02x", a, rom->read(a));
+	      break;
+	    case 'y': // (ind),Y
+	      l= rom->read(addr+1);
+	      work.appendf("($%02x", l);
+	      addr_name(l, rom, &work);
+	      work.append(",Y)");
+	      a= read_addr(rom, l) + rY;
+	      temp.appendf("; [$%04x]=$%02x", a, rom->read(a));
+	      break;
+	    case 'a': // abs
+	      l= rom->read(addr+1);
+	      h= rom->read(addr+2);
+	      a= h*256+l;
+	      work.appendf("$%04x", a);
+	      addr_name(a, rom, &work);
+	      temp.appendf("; [$%04x]=$%02x", a, rom->read(a));
+	      break;
+	    case 'j': // JMP abs
+	      l= rom->read(addr+1);
+	      h= rom->read(addr+2);
+	      a= h*256+l;
+	      work.appendf("$%04x", a);
+	      addr_name(a, rom, &work);
+	      break;
+	    case 'J': // JMP (ind)
+	      l= rom->read(addr+1);
+	      h= rom->read(addr+2);
+	      a= h*256+l;
+	      work.appendf("($%04x", a);
+	      addr_name(a, rom, &work);
+	      work.append(")");
+	      temp.appendf("; [$%04x]=$%04x", a, read_addr(rom, a));
+	      break;
+	    case 'z': // zpg
+	      l= rom->read(addr+1);
+	      work.appendf("$%04x", a= l);
+	      addr_name(a, rom, &work);
+	      temp.appendf("; [$%04x]=$%02x", a, rom->read(a));
+	      break;
+	    case 'X': // zpg.X
+	      l= rom->read(addr+1);
+	      work.appendf("$%04x", l);
+	      addr_name(l, rom, &work);
+	      work.append(",X");
+	      l+= rX;
+	      a= l;
+	      temp.appendf("; [$%04x]=$%02x", a, rom->read(a));
+	      break;
+	    case 'Y': // zpg.Y
+	      l= rom->read(addr+1);
+	      work.appendf("$%04x", l);
+	      addr_name(l, rom, &work);
+	      work.append(",Y");
+	      l+= rY;
+	      a= l;
+	      temp.appendf("; [$%04x]=$%02x", a, rom->read(a));
+	      break;
+	    case 'i': // abs,X
+	      l= rom->read(addr+1);
+	      h= rom->read(addr+2);
+	      a= h*256+l;
+	      work.appendf("$%04x", a);
+	      addr_name(a, rom, &work);
+	      work.append(",X");
+	      a+= rX;
+	      temp.appendf("; [$%04x]=$%02x", a, rom->read(a));
+	      break;
+	    case 'p': // abs,Y
+	      l= rom->read(addr+1);
+	      h= rom->read(addr+2);
+	      a= h*256+l;
+	      work.appendf("$%04x", a);
+	      addr_name(a, rom, &work);
+	      work.append(",Y");
+	      a+= rY;
+	      temp.appendf("; [$%04x]=$%02x", a, rom->read(a));
+	      break;
+	    case 'r': // rel
+	      l= rom->read(addr+1);
+	      a= addr + (i8_t)l + 2;
+	      work.appendf("$%04x", a);
+	      addr_name(a, rom, &work);
+	      break;
+	    case '#': // imm8
+	      l= rom->read(addr+1);
+	      work.appendf("#$%02x", l);
+	      break;
+	    }
+	  if (comment && temp.nempty())
+	    comment->append(temp);
+	}
+      else
+	work+= b[i];
+    }
+
+  return(strdup(work.c_str()));
+}
+
+t_addr
+cl_mos6502::read_addr(class cl_memory *m, t_addr start_addr)
+{
+  u8_t h, l;
+  l= m->read(start_addr);
+  h= m->read(start_addr+1);
+  return h*256+l;
+}
+
+class cl_cell8 &
+cl_mos6502::imm8(void)
+{
+  //class cl_cell8 *c= (class cl_cell8 *)rom->get_cell(PC);
+  i8d= fetch();
+  tick(1);
+  return ci8;
+}
+
+class cl_cell8 &
+cl_mos6502::zpg(void)
+{
+  u8_t a= fetch();
+  class cl_cell8 *c= (class cl_cell8 *)rom->get_cell(a);
+  vc.rd++;
+  tick(2);
+  return *c;
+}
+
+class cl_cell8 &
+cl_mos6502::zpgX(void)
+{
+  u8_t a= fetch() + rX;
+  class cl_cell8 *c= (class cl_cell8 *)rom->get_cell(a);
+  vc.rd++;
+  tick(3);
+  return *c;
+}
+
+class cl_cell8 &
+cl_mos6502::zpgY(void)
+{
+  u8_t a= fetch() + rY;
+  class cl_cell8 *c= (class cl_cell8 *)rom->get_cell(a);
+  vc.rd++;
+  tick(3);
+  return *c;
+}
+
+class cl_cell8 &
+cl_mos6502::abs(void)
+{
+  u16_t a= i16();
+  class cl_cell8 *c= (class cl_cell8 *)rom->get_cell(a);
+  vc.rd++;
+  tick(3);
+  return *c;
+}
+
+class cl_cell8 &
+cl_mos6502::absX(void)
+{
+  u16_t a1= i16();
+  u16_t a2= a1 + rX;
+  class cl_cell8 *c= (class cl_cell8 *)rom->get_cell(a2);
+  vc.rd++;
+  tick(3);
+  if ((a1&0xff00) != (a2&0xff00))
+    tick(1);
+  return *c;
+}
+
+class cl_cell8 &
+cl_mos6502::absY(void)
+{
+  u16_t a1= i16();
+  u16_t a2= a1 + rY;
+  class cl_cell8 *c= (class cl_cell8 *)rom->get_cell(a2);
+  vc.rd++;
+  tick(3);
+  if ((a1&0xff00) != (a2&0xff00))
+    tick(1);
+  return *c;
+}
+
+class cl_cell8 &
+cl_mos6502::ind(void)
+{
+  u16_t a= i16();
+  a= read_addr(rom, a);
+  class cl_cell8 *c= (class cl_cell8 *)rom->get_cell(a);
+  vc.rd+= 3;
+  tick(3);
+  return *c;
+}
+
+class cl_cell8 &
+cl_mos6502::indX(void)
+{
+  u8_t a0= fetch() + rX;
+  u16_t a= read_addr(rom, a0);
+  class cl_cell8 *c= (class cl_cell8 *)rom->get_cell(a);
+  vc.rd+= 3;
+  tick(5);
+  return *c;
+}
+
+class cl_cell8 &
+cl_mos6502::indY(void)
+{
+  u16_t a1= read_addr(rom, fetch());
+  u16_t a2= a1 + rY;
+  class cl_cell8 *c= (class cl_cell8 *)rom->get_cell(a2);
+  vc.rd+= 3;
+  tick(4);
+  if ((a1&0xff00) != (a2&0xff00))
+    tick(1);
+  return *c;
+}
+
+void
+cl_mos6502::print_regs(class cl_console_base *con)
+{
+  int ojaj= jaj;
+  jaj= 0;
+  con->dd_color("answer");
+  con->dd_printf("A= $%02x %3d %+4d %c  ", A, A, (i8_t)A, isprint(A)?A:'.');
+  con->dd_printf("X= $%02x %3d %+4d %c  ", X, X, (i8_t)X, isprint(X)?X:'.');
+  con->dd_printf("Y= $%02x %3d %+4d %c  ", Y, Y, (i8_t)Y, isprint(Y)?Y:'.');
+  con->dd_printf("\n");
+  con->dd_printf("P= "); con->print_bin(CC, 8); con->dd_printf("\n");
+  con->dd_printf("   NV BDIZC\n");
+
+  con->dd_printf("S= ");
+  rom->dump(0, 0x100+SP, 0x100+SP+7, 8, con);
+  con->dd_color("answer");
+  
+  if (!ojaj)
+    print_disass(PC, con);
+  else
+    {
+      con->dd_printf(" ? 0x%04x ", PC);
+      {
+	int i, j, code= rom->read(PC), l= inst_length(PC);
+	struct dis_entry *dt= dis_tbl();
+	for (i=0;i<3;i++)
+	  if (idd_printf("%02x ",rom->get(PC+i));
+	  else
+	    con->dd_printf("   ");
+	i= 0;
+	while (((code & dt[i].mask) != dt[i].code) &&
+	       dt[i].mnemonic)
+	  i++;
+	if (dt[i].mnemonic)
+	  {
+	    for (j=0;j<3;j++)
+	      con->dd_printf("%c", dt[i].mnemonic[j]);
+	  }
+      }
+      con->dd_printf("\n");
+    }
+  jaj= ojaj;
+}
+
+int
+cl_mos6502::exec_inst(void)
+{
+  int res;
+
+  set_b= false;
+  if ((res= exec_inst_tab(itab)) != resNOT_DONE)
+    return res;
+
+  inst_unknown(rom->read(instPC));
+  return(resINV_INST);
+}
+
+int
+cl_mos6502::accept_it(class it_level *il)
+{
+  class cl_it_src *is= il->source;
+
+  tick(2);
+  push_addr(PC);
+  rom->write(0x0100 + rSP, rF|0x20);
+  if (set_b)
+    rF&= ~flagB;
+  cSP.W(rSP-1);
+  tick(1);
+  vc.wr++;
+  
+  t_addr a= read_addr(rom, is->addr);
+  tick(2);
+  vc.rd+= 2;
+  PC= a;
+
+  rF|= flagI;
+  is->clear();
+  it_levels->push(il);
+  
+  return resGO;
+}
+
+bool
+cl_mos6502::it_enabled(void)
+{
+  return !(rF & flagI);
+}
+
+void
+cl_mos6502::push_addr(t_addr a)
+{
+  rom->write(0x0100 + rSP, (a>>8));
+  cSP.W(rSP-1);
+  rom->write(0x0100 + rSP, (a));
+  cSP.W(rSP-1);
+  tick(2);
+  vc.wr+= 2;
+}
+
+t_addr
+cl_mos6502::pop_addr(void)
+{
+  u8_t h, l;
+  cSP.W(rSP+1);
+  l= rom->read(0x0100 + rSP);
+  cSP.W(rSP+1);
+  h= rom->read(0x0100 + rSP);
+  tick(2);
+  vc.rd+= 2;
+  return h*256+l;
+}
+
+void
+cl_mos6502::stack_check_overflow(class cl_stack_op *op)
+{
+  if (op)
+    {
+      if (op->get_op() & stack_write_operation)
+	{
+	  u8_t a= op->get_before();
+	  if (rSP > a)
+	    {
+	      class cl_error_stack_overflow *e=
+		new cl_error_stack_overflow(op);
+	      e->init();
+	      error(e);
+	    }
+	}
+    }
+}
+
+
+/* End of mos6502.src/mos6502.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/mos6502.src/mos6502cl.h sdcc-4.2.0+dfsg/sim/ucsim/mos6502.src/mos6502cl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/mos6502.src/mos6502cl.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/mos6502.src/mos6502cl.h	2022-01-24 11:09:43.000000000 +0000
@@ -0,0 +1,375 @@
+/*
+ * Simulator of microcontrollers (mos6502cl.h)
+ *
+ * Copyright (C) 2020,20 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef MOS6502CL_HEADER
+#define MOS6502CL_HEADER
+
+#include "uccl.h"
+#include "memcl.h"
+#include "decode.h"
+#include "itsrccl.h"
+
+
+#define rA  (A)
+#define rX  (X)
+#define rY  (Y)
+#define rSP (SP)
+#define rS  (SP)
+#define rCC (CC)
+#define rP  (CC)
+#define rF  (CC)
+#define cP  (cCC)
+#define cF  (cCC)
+#define cS  (cSP)
+
+enum {
+  mN	= 0x80,
+  flagN	= 0x80,
+  mS	= 0x80,
+  flagS	= 0x80,
+  mV	= 0x40,
+  flagV	= 0x40,
+  mO	= 0x40,
+  flagO	= 0x40,
+  mB	= 0x10,
+  flagB	= 0x10,
+  mD	= 0x08,
+  flagD	= 0x08,
+  mI	= 0x04,
+  flagI	= 0x04,
+  mZ	= 0x02,
+  flagZ	= 0x02,
+  mC	= 0x01,
+  flagC	= 0x01
+};
+
+// Vectors
+enum {
+  NMI_AT	= 0xfffa,
+  RESET_AT	= 0xfffc,
+  IRQ_AT	= 0xfffe
+};
+
+
+class cl_c65: public cl_cell8
+{
+#ifdef DEVEL
+  virtual t_mem read(void);
+  virtual t_mem get(void);
+  virtual t_mem write(t_mem val);
+  virtual t_mem set(t_mem val);
+#endif
+};
+
+class cl_as65: public cl_address_space
+{
+public:
+  cl_as65(const char *id, t_addr astart, t_addr asize, int awidth):
+    cl_address_space(id, astart, asize, awidth) {}
+  virtual class cl_memory_cell *cell_template();
+};
+
+
+/*
+ * Base of MOS6502 processor
+ */
+
+class cl_mos6502: public cl_uc  
+{
+public:
+  u8_t A, X, Y, SP, CC, i8d;
+  class cl_cell8 cA, cX, cY, cSP, cCC, ci8;
+  class cl_it_src *src_irq, *src_nmi, *src_brk;
+  bool set_b;
+public:
+  cl_mos6502(class cl_sim *asim);
+  virtual int init(void);
+  virtual const char *id_string(void);
+  virtual void reset(void);
+  virtual void set_PC(t_addr addr);
+
+  virtual void mk_hw_elements(void);
+  virtual void make_cpu_hw(void);
+  virtual void make_memories(void);
+
+  virtual int clock_per_cycle(void) { return 1; }
+  virtual struct dis_entry *dis_tbl(void);
+  virtual struct dis_entry *get_dis_entry(t_addr addr);
+  virtual void analyze_start(void);
+  virtual void analyze(t_addr addr);
+  virtual char *disassc(t_addr addr, chars *comment=NULL);
+  virtual t_addr read_addr(class cl_memory *m, t_addr start_addr);
+
+  virtual void print_regs(class cl_console_base *con);
+
+  virtual int exec_inst(void);
+  virtual int priority_of(uchar nuof_it) { return nuof_it; }
+  virtual int accept_it(class it_level *il);
+  virtual bool it_enabled(void);
+  virtual void push_addr(t_addr a);
+  virtual t_addr pop_addr(void);
+  virtual void stack_check_overflow(class cl_stack_op *op);
+  
+  virtual class cl_cell8 &imm8(void);
+  // read operands
+  virtual class cl_cell8 &zpg(void);
+  virtual class cl_cell8 &zpgX(void);
+  virtual class cl_cell8 &zpgY(void);
+  virtual class cl_cell8 &abs(void);
+  virtual class cl_cell8 &absX(void);
+  virtual class cl_cell8 &absY(void);
+  virtual class cl_cell8 &ind(void);
+  virtual class cl_cell8 &indX(void);
+  virtual class cl_cell8 &indY(void);
+  // write operands
+  virtual class cl_cell8 &dstzpg(void) { vc.wr++; return zpg(); }
+  virtual class cl_cell8 &dstzpgX(void) { vc.wr++; return zpgX(); }
+  virtual class cl_cell8 &dstzpgY(void) { vc.wr++; return zpgY(); }
+  virtual class cl_cell8 &dstabs(void) { vc.wr++; return abs(); }
+  virtual class cl_cell8 &dstabsX(void) { vc.wr++; return absX(); }
+  virtual class cl_cell8 &dstabsY(void) { vc.wr++; return absY(); }
+  virtual class cl_cell8 &dstind(void) { vc.wr++; return ind(); }
+  virtual class cl_cell8 &dstindX(void) { vc.wr++; return indX(); }
+  virtual class cl_cell8 &dstindY(void) { vc.wr++; return indY(); }
+  // read-modify-write operands
+  virtual class cl_cell8 &rmwzpg(void) { vc.rd++;vc.wr++;tick(2); return zpg(); }
+  virtual class cl_cell8 &rmwzpgX(void) { vc.rd++;vc.wr++;tick(2); return zpgX(); }
+  virtual class cl_cell8 &rmwzpgY(void) { vc.rd++;vc.wr++;tick(2); return zpgY(); }
+  virtual class cl_cell8 &rmwabs(void) { vc.rd++;vc.wr++;tick(2); return abs(); }
+  virtual class cl_cell8 &rmwabsX(void) { vc.rd++;vc.wr++;tick(3); return absX(); }
+  virtual class cl_cell8 &rmwabsY(void) { vc.rd++;vc.wr++;tick(3); return absY(); }
+  virtual class cl_cell8 &rmwind(void) { vc.rd++;vc.wr++;tick(1); return ind(); }
+  virtual class cl_cell8 &rmwindX(void) { vc.rd++;vc.wr++;tick(1); return indX(); }
+  virtual class cl_cell8 &rmwindY(void) { vc.rd++;vc.wr++;tick(1); return indY(); }
+  //virtual u8_t i8(void) { return fetch(); }
+  virtual u16_t i16(void) { u8_t h, l; l=fetch(); h= fetch(); return h*256+l; }
+
+  virtual int NOP(t_mem code);
+  virtual int BRK(t_mem code);
+  virtual int RTI(t_mem code);
+  virtual int CLI(t_mem code);
+  virtual int SEI(t_mem code);
+  virtual int PHP(t_mem code);
+  virtual int CLC(t_mem code);
+  virtual int PLP(t_mem code);
+  virtual int SEc(t_mem code);
+  virtual int PHA(t_mem code);
+  virtual int PLA(t_mem code);
+  virtual int DEY(t_mem code);
+  virtual int TYA(t_mem code);
+  virtual int TAY(t_mem code);
+  virtual int CLV(t_mem code);
+  virtual int INY(t_mem code);
+  virtual int CLD(t_mem code);
+  virtual int INX(t_mem code);
+  virtual int SED(t_mem code);
+  virtual int TXA(t_mem code);
+  virtual int TXS(t_mem code);
+  virtual int TAX(t_mem code);
+  virtual int TSX(t_mem code);
+  virtual int DEX(t_mem code);
+
+  virtual int ora(class cl_cell8 &op);
+  virtual int ORAix(t_mem code) { return ora(indX()); }
+  virtual int ORAiy(t_mem code) { return ora(indY()); }
+  virtual int ORAz (t_mem code) { return ora(zpg()); }
+  virtual int ORAzx(t_mem code) { return ora(zpgX()); }
+  virtual int ORA8 (t_mem code) { return ora(imm8()); }
+  virtual int ORAay(t_mem code) { return ora(absY()); }
+  virtual int ORAa (t_mem code) { return ora(abs()); }
+  virtual int ORAax(t_mem code) { return ora(absX()); }
+
+  virtual int And(class cl_cell8 &op);
+  virtual int ANDix(t_mem code) { return And(indX()); }
+  virtual int ANDiy(t_mem code) { return And(indY()); }
+  virtual int ANDz (t_mem code) { return And(zpg()); }
+  virtual int ANDzx(t_mem code) { return And(zpgX()); }
+  virtual int AND8 (t_mem code) { return And(imm8()); }
+  virtual int ANDay(t_mem code) { return And(absY()); }
+  virtual int ANDa (t_mem code) { return And(abs()); }
+  virtual int ANDax(t_mem code) { return And(absX()); }
+
+  virtual int eor(class cl_cell8 &op);
+  virtual int EORix(t_mem code) { return eor(indX()); }
+  virtual int EORiy(t_mem code) { return eor(indY()); }
+  virtual int EORz (t_mem code) { return eor(zpg()); }
+  virtual int EORzx(t_mem code) { return eor(zpgX()); }
+  virtual int EOR8 (t_mem code) { return eor(imm8()); }
+  virtual int EORay(t_mem code) { return eor(absY()); }
+  virtual int EORa (t_mem code) { return eor(abs()); }
+  virtual int EORax(t_mem code) { return eor(absX()); }
+
+  virtual int adc(class cl_cell8 &op);
+  virtual int ADCix(t_mem code) { return adc(indX()); }
+  virtual int ADCiy(t_mem code) { return adc(indY()); }
+  virtual int ADCz (t_mem code) { return adc(zpg()); }
+  virtual int ADCzx(t_mem code) { return adc(zpgX()); }
+  virtual int ADC8 (t_mem code) { return adc(imm8()); }
+  virtual int ADCay(t_mem code) { return adc(absY()); }
+  virtual int ADCa (t_mem code) { return adc(abs()); }
+  virtual int ADCax(t_mem code) { return adc(absX()); }
+
+  virtual int sta(class cl_cell8 &op);
+  virtual int STAix(t_mem code) { return sta(dstindX()); }
+  virtual int STAiy(t_mem code) { return sta(dstindY()); }
+  virtual int STAz (t_mem code) { return sta(dstzpg()); }
+  virtual int STAzx(t_mem code) { return sta(dstzpgX()); }
+  virtual int STAay(t_mem code) { return sta(dstabsY()); }
+  virtual int STAa (t_mem code) { return sta(dstabs()); }
+  virtual int STAax(t_mem code) { tick(1); return sta(dstabsX()); }
+
+  virtual int lda(class cl_cell8 &op);
+  virtual int LDAix(t_mem code) { return lda(indX()); }
+  virtual int LDAiy(t_mem code) { return lda(indY()); }
+  virtual int LDAz (t_mem code) { return lda(zpg()); }
+  virtual int LDAzx(t_mem code) { return lda(zpgX()); }
+  virtual int LDA8 (t_mem code) { return lda(imm8()); }
+  virtual int LDAay(t_mem code) { return lda(absY()); }
+  virtual int LDAa (t_mem code) { return lda(abs()); }
+  virtual int LDAax(t_mem code) { return lda(absX()); }
+
+  virtual int sbc(class cl_cell8 &op);
+  virtual int SBCix(t_mem code) { return sbc(indX()); }
+  virtual int SBCiy(t_mem code) { return sbc(indY()); }
+  virtual int SBCz (t_mem code) { return sbc(zpg()); }
+  virtual int SBCzx(t_mem code) { return sbc(zpgX()); }
+  virtual int SBC8 (t_mem code) { return sbc(imm8()); }
+  virtual int SBCay(t_mem code) { return sbc(absY()); }
+  virtual int SBCa (t_mem code) { return sbc(abs()); }
+  virtual int SBCax(t_mem code) { return sbc(absX()); }
+
+  virtual int cmp(class cl_cell8 &op1, class cl_cell8 &op2);
+  virtual int CMPix(t_mem code) { return cmp(cA, indX()); }
+  virtual int CMPiy(t_mem code) { return cmp(cA, indY()); }
+  virtual int CMPz (t_mem code) { return cmp(cA, zpg()); }
+  virtual int CMPzx(t_mem code) { return cmp(cA, zpgX()); }
+  virtual int CMP8 (t_mem code) { return cmp(cA, imm8()); }
+  virtual int CMPay(t_mem code) { return cmp(cA, absY()); }
+  virtual int CMPa (t_mem code) { return cmp(cA, abs()); }
+  virtual int CMPax(t_mem code) { return cmp(cA, absX()); }
+
+  virtual int CPY8(t_mem code) { return cmp(cY, imm8()); }
+  virtual int CPYz(t_mem code) { return cmp(cY, zpg()); }
+  virtual int CPYa(t_mem code) { return cmp(cY, abs()); }
+  virtual int CPX8(t_mem code) { return cmp(cX, imm8()); }
+  virtual int CPXz(t_mem code) { return cmp(cX, zpg()); }
+  virtual int CPXa(t_mem code) { return cmp(cX, abs()); }
+
+  virtual int st(u8_t reg, class cl_cell8 &op);
+  virtual int STYz (t_mem code) { return st(rY, dstzpg()); }
+  virtual int STYzx(t_mem code) { return st(rY, dstzpgX()); }
+  virtual int STYa (t_mem code) { return st(rY, dstabs()); }
+  virtual int STXz (t_mem code) { return st(rX, dstzpg()); }
+  virtual int STXzy(t_mem code) { return st(rX, dstzpgY()); }
+  virtual int STXa (t_mem code) { return st(rX, dstabs()); }
+
+  virtual int ld(class cl_cell8 ®, class cl_cell8 &op);
+  virtual int LDY8 (t_mem code) { return ld(cY, imm8()); }
+  virtual int LDYz (t_mem code) { return ld(cY, zpg()); }
+  virtual int LDYzx(t_mem code) { return ld(cY, zpgX()); }
+  virtual int LDYa (t_mem code) { return ld(cY, abs()); }
+  virtual int LDYax(t_mem code) { return ld(cY, absX()); }
+  virtual int LDX8 (t_mem code) { return ld(cX, imm8()); }
+  virtual int LDXz (t_mem code) { return ld(cX, zpg()); }
+  virtual int LDXzy(t_mem code) { return ld(cX, zpgY()); }
+  virtual int LDXa (t_mem code) { return ld(cX, abs()); }
+  virtual int LDXay(t_mem code) { return ld(cX, absY()); }
+
+  virtual int inc(class cl_cell8 &op);
+  virtual int dec(class cl_cell8 &op);
+  virtual int INCz (t_mem code) { return inc(rmwzpg()); }
+  virtual int INCzx(t_mem code) { return inc(rmwzpgX()); }
+  virtual int INCa (t_mem code) { return inc(rmwabs()); }
+  virtual int INCax(t_mem code) { return inc(rmwabsX()); }
+  virtual int DECz (t_mem code) { return dec(rmwzpg()); }
+  virtual int DECzx(t_mem code) { return dec(rmwzpgX()); }
+  virtual int DECa (t_mem code) { return dec(rmwabs()); }
+  virtual int DECax(t_mem code) { return dec(rmwabsX()); }
+  
+  virtual int asl(class cl_cell8 &op);
+  virtual int ASLz (t_mem code) { return asl(rmwzpg()); }
+  virtual int ASLzx(t_mem code) { return asl(rmwzpgX()); }
+  virtual int ASL  (t_mem code) { tick(1); return asl(cA); }
+  virtual int ASLa (t_mem code) { return asl(rmwabs()); }
+  virtual int ASLax(t_mem code) { return asl(rmwabsX()); }
+
+  virtual int lsr(class cl_cell8 &op);
+  virtual int LSRz (t_mem code) { return lsr(rmwzpg()); }
+  virtual int LSRzx(t_mem code) { return lsr(rmwzpgX()); }
+  virtual int LSR  (t_mem code) { tick(1); return lsr(cA); }
+  virtual int LSRa (t_mem code) { return lsr(rmwabs()); }
+  virtual int LSRax(t_mem code) { return lsr(rmwabsX()); }
+
+  virtual int rol(class cl_cell8 &op);
+  virtual int ROLz (t_mem code) { return rol(rmwzpg()); }
+  virtual int ROLzx(t_mem code) { return rol(rmwzpgX()); }
+  virtual int ROL  (t_mem code) { tick(1); return rol(cA); }
+  virtual int ROLa (t_mem code) { return rol(rmwabs()); }
+  virtual int ROLax(t_mem code) { return rol(rmwabsX()); }
+
+  virtual int ror(class cl_cell8 &op);
+  virtual int RORz (t_mem code) { return ror(rmwzpg()); }
+  virtual int RORzx(t_mem code) { return ror(rmwzpgX()); }
+  virtual int ROR  (t_mem code) { tick(1); return ror(cA); }
+  virtual int RORa (t_mem code) { return ror(rmwabs()); }
+  virtual int RORax(t_mem code) { return ror(rmwabsX()); }
+
+  virtual int bit(class cl_cell8 &op);
+  virtual int BITz(t_mem code) { return bit(zpg()); }
+  virtual int BITa(t_mem code) { return bit(abs()); }
+
+  virtual int JMPa(t_mem code);
+  virtual int JMPi(t_mem code);
+
+  virtual int JSR(t_mem code);
+  virtual int RTS(t_mem code);
+  
+  virtual int branch(bool cond);
+  virtual int BPL(t_mem code) { return branch(!(rF & flagN)); }
+  virtual int BMI(t_mem code) { return branch( (rF & flagN)); }
+  virtual int BVC(t_mem code) { return branch(!(rF & flagV)); }
+  virtual int BVS(t_mem code) { return branch( (rF & flagV)); }
+  virtual int BCC(t_mem code) { return branch(!(rF & flagC)); }
+  virtual int BCS(t_mem code) { return branch( (rF & flagC)); }
+  virtual int BNE(t_mem code) { return branch(!(rF & flagZ)); }
+  virtual int BEQ(t_mem code) { return branch( (rF & flagZ)); }
+};
+
+
+/* Unused bits of CC forced to be 1 */
+
+class cl_cc_operator: public cl_memory_operator
+{
+public:
+  cl_cc_operator(class cl_memory_cell *acell): cl_memory_operator(acell) {}
+  virtual t_mem write(t_mem val) { return val/*|= 0x20*/; }
+};
+
+
+#endif
+
+/* End of mos6502.src/mos6502.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/mos6502.src/mos6510.cc sdcc-4.2.0+dfsg/sim/ucsim/mos6502.src/mos6510.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/mos6502.src/mos6510.cc	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/mos6502.src/mos6510.cc	2022-01-16 21:17:11.000000000 +0000
@@ -0,0 +1,53 @@
+/*
+ * Simulator of microcontrollers (mos6510.cc)
+ *
+ * Copyright (C) 2020,20 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#include 
+#include 
+
+#include "mos6510cl.h"
+
+
+cl_mos6510::cl_mos6510(class cl_sim *asim):
+  cl_mos6502(asim)
+{
+}
+
+int
+cl_mos6510::init(void)
+{
+  cl_mos6502::init();
+  return 0;
+}
+
+const char *
+cl_mos6510::id_string(void)
+{
+  return "MOS6510";
+}
+
+
+/* End of mos6502.src/mos6510.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/mos6502.src/mos6510cl.h sdcc-4.2.0+dfsg/sim/ucsim/mos6502.src/mos6510cl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/mos6502.src/mos6510cl.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/mos6502.src/mos6510cl.h	2022-01-16 21:17:11.000000000 +0000
@@ -0,0 +1,45 @@
+/*
+ * Simulator of microcontrollers (mos6510cl.h)
+ *
+ * Copyright (C) 2020,20 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef MOS6510CL_HEADER
+#define MOS6510CL_HEADER
+
+#include "mos6502cl.h"
+
+
+class cl_mos6510: public cl_mos6502
+{
+ public:
+  cl_mos6510(class cl_sim *asim);
+  virtual int init(void);
+  virtual const char *id_string(void);
+};
+
+
+#endif
+
+/* End of mos6502.src/mos6510cl.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/mos6502.src/mos65c02.cc sdcc-4.2.0+dfsg/sim/ucsim/mos6502.src/mos65c02.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/mos6502.src/mos65c02.cc	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/mos6502.src/mos65c02.cc	2022-01-16 21:17:11.000000000 +0000
@@ -0,0 +1,53 @@
+/*
+ * Simulator of microcontrollers (mos65c02.cc)
+ *
+ * Copyright (C) 2020,20 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#include 
+#include 
+
+#include "mos65c02cl.h"
+
+
+cl_mos65c02::cl_mos65c02(class cl_sim *asim):
+  cl_mos6502(asim)
+{
+}
+
+int
+cl_mos65c02::init(void)
+{
+  cl_mos6502::init();
+  return 0;
+}
+
+const char *
+cl_mos65c02::id_string(void)
+{
+  return "MOS65C02";
+}
+
+
+/* End of mos6502.src/mos65c02.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/mos6502.src/mos65c02cl.h sdcc-4.2.0+dfsg/sim/ucsim/mos6502.src/mos65c02cl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/mos6502.src/mos65c02cl.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/mos6502.src/mos65c02cl.h	2022-01-16 21:17:11.000000000 +0000
@@ -0,0 +1,45 @@
+/*
+ * Simulator of microcontrollers (mos65c02cl.h)
+ *
+ * Copyright (C) 2020,20 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef MOS65C02CL_HEADER
+#define MOS65C02CL_HEADER
+
+#include "mos6502cl.h"
+
+
+class cl_mos65c02: public cl_mos6502
+{
+ public:
+  cl_mos65c02(class cl_sim *asim);
+  virtual int init(void);
+  virtual const char *id_string(void);
+};
+
+
+#endif
+
+/* End of mos6502.src/mos65c02.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/mos6502.src/mos65ce02.cc sdcc-4.2.0+dfsg/sim/ucsim/mos6502.src/mos65ce02.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/mos6502.src/mos65ce02.cc	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/mos6502.src/mos65ce02.cc	2022-01-16 21:17:11.000000000 +0000
@@ -0,0 +1,108 @@
+/*
+ * Simulator of microcontrollers (mos65ce02.cc)
+ *
+ * Copyright (C) 2020,20 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#include 
+#include 
+
+#include "appcl.h"
+
+#include "mos65ce02cl.h"
+
+
+cl_mos65ce02::cl_mos65ce02(class cl_sim *asim):
+  cl_mos65c02(asim)
+{
+}
+
+int
+cl_mos65ce02::init(void)
+{
+  cl_mos65c02::init();
+#define RCV(R) reg_cell_var(&c ## R , &r ## R , "" #R "" , "CPU register " #R "")
+  RCV(B);
+  RCV(Z);
+#undef RCV
+  return 0;
+}
+
+const char *
+cl_mos65ce02::id_string(void)
+{
+  return "MOS65CE02";
+}
+
+
+void
+cl_mos65ce02::print_regs(class cl_console_base *con)
+{
+  int ojaj= jaj;
+  jaj= 0;
+  con->dd_color("answer");
+  con->dd_printf("A= $%02x %3d %+4d %c  ", A, A, (i8_t)A, isprint(A)?A:'.');
+  con->dd_printf("X= $%02x %3d %+4d %c  ", X, X, (i8_t)X, isprint(X)?X:'.');
+  con->dd_printf("Y= $%02x %3d %+4d %c  ", Y, Y, (i8_t)Y, isprint(Y)?Y:'.');
+  con->dd_printf("Z= $%02x %3d %+4d %c  ", Z, Z, (i8_t)Z, isprint(Z)?Z:'.');
+  con->dd_printf("\n");
+  con->dd_printf("P= "); con->print_bin(CC, 8);
+  con->dd_printf("        B= $%02x", B);
+  con->dd_printf("\n");
+  con->dd_printf("   NV BDIZC\n");
+
+  con->dd_printf("S= ");
+  rom->dump(0, 0x100+SP, 0x100+SP+7, 8, con);
+  con->dd_color("answer");
+  
+  if (!ojaj)
+    print_disass(PC, con);
+  else
+    {
+      con->dd_printf(" ? 0x%04x ", PC);
+      {
+	int i, j, code= rom->read(PC), l= inst_length(PC);
+	struct dis_entry *dt= dis_tbl();
+	for (i=0;i<3;i++)
+	  if (idd_printf("%02x ",rom->get(PC+i));
+	  else
+	    con->dd_printf("   ");
+	i= 0;
+	while (((code & dt[i].mask) != dt[i].code) &&
+	       dt[i].mnemonic)
+	  i++;
+	if (dt[i].mnemonic)
+	  {
+	    for (j=0;j<3;j++)
+	      con->dd_printf("%c", dt[i].mnemonic[j]);
+	  }
+      }
+      con->dd_printf("\n");
+    }
+  jaj= ojaj;
+}
+
+
+/* End of mos6502.src/mos65ce02.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/mos6502.src/mos65ce02cl.h sdcc-4.2.0+dfsg/sim/ucsim/mos6502.src/mos65ce02cl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/mos6502.src/mos65ce02cl.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/mos6502.src/mos65ce02cl.h	2022-01-16 21:17:11.000000000 +0000
@@ -0,0 +1,53 @@
+/*
+ * Simulator of microcontrollers (mos65ce02cl.h)
+ *
+ * Copyright (C) 2020,20 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef MOS65CE02CL_HEADER
+#define MOS65CE02CL_HEADER
+
+#include "mos65c02cl.h"
+
+#define rB (B)
+#define rZ (Z)
+
+
+class cl_mos65ce02: public cl_mos65c02
+{
+public:
+  u8_t B, Z;
+  class cl_cell8 cB, cZ;
+public:
+  cl_mos65ce02(class cl_sim *asim);
+  virtual int init(void);
+  virtual const char *id_string(void);
+
+  virtual void print_regs(class cl_console_base *con);
+};
+
+
+#endif
+
+/* End of mos6502.src/mos65ce02.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/mos6502.src/simmos6502.cc sdcc-4.2.0+dfsg/sim/ucsim/mos6502.src/simmos6502.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/mos6502.src/simmos6502.cc	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/mos6502.src/simmos6502.cc	2022-01-16 21:17:11.000000000 +0000
@@ -0,0 +1,80 @@
+/*
+ * Simulator of microcontrollers (simmos6502.cc)
+ *
+ * Copyright (C) 2020,20 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+// local
+#include "simmos6502cl.h"
+#include "mos6502cl.h"
+#include "mos6510cl.h"
+#include "mos65c02cl.h"
+#include "mos65ce02cl.h"
+#include "glob.h"
+
+
+cl_simmos6502::cl_simmos6502(class cl_app *the_app):
+  cl_sim(the_app)
+{}
+
+class cl_uc *
+cl_simmos6502::mk_controller(void)
+{
+  int i;
+  const char *typ= 0;
+  class cl_optref type_option(this);
+
+  type_option.init();
+  type_option.use("cpu_type");
+  i= 0;
+  if ((typ= type_option.get_value(typ)) == 0)
+    typ= "6502";
+  while ((cpus_6502[i].type_str != NULL) &&
+	 (strcasecmp(typ, cpus_6502[i].type_str) != 0))
+    i++;
+  if (cpus_6502[i].type_str == NULL)
+    {
+      fprintf(stderr, "Unknown processor type. "
+	      "Use -H option to see known types.\n");
+      return(NULL);
+    }
+  switch (cpus_6502[i].type)
+    {
+    case CPU_6502:
+      return(new cl_mos6502(this));
+    case CPU_6510:
+      return(new cl_mos6510(this));
+    case CPU_65C02:
+      return(new cl_mos65c02(this));
+    case CPU_65CE02:
+      return(new cl_mos65ce02(this));
+    default:
+      fprintf(stderr, "Unknown processor type\n");
+      return NULL;
+    }
+  return NULL;
+}
+
+
+/* End of mos6502.src/simmos6502.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/mos6502.src/simmos6502cl.h sdcc-4.2.0+dfsg/sim/ucsim/mos6502.src/simmos6502cl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/mos6502.src/simmos6502cl.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/mos6502.src/simmos6502cl.h	2022-01-15 21:15:29.000000000 +0000
@@ -0,0 +1,45 @@
+/*
+ * Simulator of microcontrollers (simmos6502cl.h)
+ *
+ * Copyright (C) 2020,20 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef SIMMOS6502CL_HEADER
+#define SIMMOS6502CL_HEADER
+
+#include "simcl.h"
+
+
+class cl_simmos6502: public cl_sim
+{
+public:
+  cl_simmos6502(class cl_app *the_app);
+
+  virtual class cl_uc *mk_controller(void);
+};
+
+
+#endif
+
+/* End of mos6502.src/simmos6502cl.h */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/mos6502.src/smos6502.cc sdcc-4.2.0+dfsg/sim/ucsim/mos6502.src/smos6502.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/mos6502.src/smos6502.cc	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/mos6502.src/smos6502.cc	2022-01-16 21:17:11.000000000 +0000
@@ -0,0 +1,56 @@
+/*
+ * Simulator of microcontrollers (smos6502.cc)
+ *
+ * Copyright (C) 2020,20 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+// prj
+#include "globals.h"
+
+// local
+#include "simmos6502cl.h"
+#include "glob.h"
+
+
+int
+main(int argc, char *argv[])
+{
+  class cl_sim *sim;
+
+  cpus= cpus_6502;
+  application= new cl_app();
+  application->set_name("smos6502");
+  application->init(argc, argv);
+  sim= new cl_simmos6502(application);
+  if (sim->init())
+    sim->state|= SIM_QUIT;
+  application->set_simulator(sim);
+  //sim->main();
+  application->run();
+  application->done();
+  delete application;
+  return(0);
+}
+
+/* End of mos6502.src/smos6502.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/mos6502.src/test/clean.mk sdcc-4.2.0+dfsg/sim/ucsim/mos6502.src/test/clean.mk
--- sdcc-4.0.0+dfsg/sim/ucsim/mos6502.src/test/clean.mk	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/mos6502.src/test/clean.mk	2021-04-16 22:21:27.000000000 +0000
@@ -0,0 +1,5 @@
+clean:
+
+distclean:
+	rm -f Makefile
+	find . -type d -name out -exec rm -rf {} \;
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/mos6502.src/test/config/baseline/MOS6502 sdcc-4.2.0+dfsg/sim/ucsim/mos6502.src/test/config/baseline/MOS6502
--- sdcc-4.0.0+dfsg/sim/ucsim/mos6502.src/test/config/baseline/MOS6502	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/mos6502.src/test/config/baseline/MOS6502	2022-02-08 21:21:05.000000000 +0000
@@ -0,0 +1,24 @@
+uCsim, Copyright (C)  Daniel Drotos.
+uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+This is free software, and you are welcome to redistribute it
+under certain conditions; type `show c' for details.
+Type of microcontroller: MOS6502
+Controller has 4 hardware element(s).
+   on simif[0]
+  off vcd[0]
+   on dreg[0]
+   on irq[0]
+A= $00   0   +0 .  X= $00   0   +0 .  Y= $00   0   +0 .  
+P= 00000100
+   NV BDIZC
+S= 0x01fd 00 00 00 00 00 00 00 00 ........
+0xf719  ? 00       BRK[0K
+Memory chips:
+  0x000000-0x0000ff      256 variable_storage (32,%08x,0x%02lx)
+  0x000000-0x00ffff    65536 rom_chip (8,%02x,0x%04lx)
+Address spaces:
+  0x000000-0x0000ff      256 variables (32,%08x,0x%02lx)
+  0x000000-0x00ffff    65536 rom (8,%02x,0x%04lx)
+Address decoders:
+  variables 0x00 0xff -> variable_storage 0x00 activated
+  rom 0x0000 0xffff -> rom_chip 0x0000 activated
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/mos6502.src/test/config/Makefile sdcc-4.2.0+dfsg/sim/ucsim/mos6502.src/test/config/Makefile
--- sdcc-4.0.0+dfsg/sim/ucsim/mos6502.src/test/config/Makefile	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/mos6502.src/test/config/Makefile	2022-01-15 21:15:29.000000000 +0000
@@ -0,0 +1,8 @@
+OUTPUTS = MOS6502
+
+
+$(OUTPUTS):
+	$(call run-sim, -e 'conf; info reg; info mem')
+
+
+include test-lib.mk
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/mos6502.src/test/Makefile.in sdcc-4.2.0+dfsg/sim/ucsim/mos6502.src/test/Makefile.in
--- sdcc-4.0.0+dfsg/sim/ucsim/mos6502.src/test/Makefile.in	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/mos6502.src/test/Makefile.in	2021-04-16 22:21:27.000000000 +0000
@@ -0,0 +1,9 @@
+# @configure_input@
+
+srcdir           = @abs_srcdir@
+
+abs_top_builddir = @abs_top_builddir@
+abs_top_srcdir   = @abs_top_srcdir@
+
+
+include $(abs_top_srcdir)/test-target.mk
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/motorola.src/(c).1 sdcc-4.2.0+dfsg/sim/ucsim/motorola.src/(c).1
--- sdcc-4.0.0+dfsg/sim/ucsim/motorola.src/(c).1	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/motorola.src/(c).1	2021-05-20 07:49:29.000000000 +0000
@@ -0,0 +1,25 @@
+/*
+ * Simulator of microcontrollers (@@F@@)
+ *
+ * Copyright (C) @@S@@,@@Y@@ Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/motorola.src/cia.cc sdcc-4.2.0+dfsg/sim/ucsim/motorola.src/cia.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/motorola.src/cia.cc	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/motorola.src/cia.cc	2021-11-02 13:14:45.000000000 +0000
@@ -0,0 +1,499 @@
+/*
+ * Simulator of microcontrollers (motorola.src/cia.cc)
+ *
+ * Copyright (C) @@S@@,@@Y@@ Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#include "ddconfig.h"
+
+// sim
+#include "argcl.h"
+#include "itsrccl.h"
+
+#include "ciacl.h"
+
+enum reg_idx
+  {
+   sr = 0, // RO
+   cr = 0, // WO
+   rd = 1, // RO
+   td = 1, // WO
+   dr = 1, 
+  };
+
+cl_cia::cl_cia(class cl_uc *auc, int aid, t_addr abase):
+  cl_serial_hw(auc, aid, "uart")
+{
+  base= abase;
+}
+
+cl_cia::~cl_cia(void)
+{
+}
+
+int
+cl_cia::init(void)
+{
+  int i;
+  
+  set_name("6850");
+  cl_serial_hw::init();
+
+  r_cr= cfg_cell(acia_cfg_cr);
+  r_sr= cfg_cell(acia_cfg_sr);
+
+  for (i= 0; i < 2; i++)
+    regs[i]= register_cell(uc->rom, base+i);
+  regs[cr]->write(0x15);
+  //pick_div();
+  //pick_ctrl();
+
+  ten= true;
+  ren= true;
+  s_sending= false;
+  s_receiving= false;
+  
+  r_sr->set(0);//regs[sr]->set(0);
+  show_readable(false);
+  show_writable(true);
+  //cfg_set(acia_cfg_req, 'i');
+  
+  cl_var *v;
+  chars pn= chars("", "uart%d_", id);
+  uc->vars->add(v= new cl_var(pn+"base", cfg, acia_cfg_base, cfg_help(acia_cfg_base)));
+  v->init();
+  uc->vars->add(v= new cl_var(pn+"cr", cfg, acia_cfg_cr,
+			      cfg_help(acia_cfg_cr)));
+  v->init();
+  uc->vars->add(v= new cl_var(pn+"sr", cfg, acia_cfg_sr,
+			      cfg_help(acia_cfg_sr)));
+  v->init();
+  uc->vars->add(v= new cl_var(pn+"req", cfg, acia_cfg_req,
+			      cfg_help(acia_cfg_req)));
+  v->init();
+  
+  is_t= new cl_it_src(uc, 1,
+		      r_cr, 0x60, //0x20,
+		      r_sr, 2,
+		      0, false, false,
+		      pn+"tx",
+		      0);
+  is_t->set_ie_value(0x20);
+  is_t->init();
+  is_t->set_parent(uc->search_it_src('i'));
+  uc->it_sources->add(is_t);
+  is_r= new cl_it_src(uc, 2,
+		      r_cr, 0x80, //0x80,
+		      r_sr, 1,
+		      0, false, false,
+		      pn+"rx",
+		      0);
+  is_r->init();
+  is_r->set_ie_value(0x80);
+  is_r->set_parent(uc->search_it_src('i'));
+  uc->it_sources->add(is_r);
+  
+  return(0);
+}
+
+const char *
+cl_cia::cfg_help(t_addr addr)
+{
+  switch (addr)
+    {
+    case acia_cfg_base:
+      return "Base address of ACIA registers (int, RW)";
+    case acia_cfg_cr:
+      return "Copy of written CR value";
+    case acia_cfg_sr:
+      return "Simulated SR value";
+    case acia_cfg_req:
+      return "Req mode of ACIA 'i'=IRQ 'f'=FIRQ 'n'=NMI";
+    }
+  return cl_serial_hw::cfg_help(addr);
+}
+
+t_mem
+cl_cia::read(class cl_memory_cell *cell)
+{
+  if (cell == regs[dr])
+    {
+      cfg_set(serconf_able_receive, 1);
+      show_readable(false);
+      return s_in;
+    }
+  if (cell == regs[sr])
+    return r_sr->read();
+  conf(cell, NULL);
+  return cell->get();
+}
+
+void
+cl_cia::write(class cl_memory_cell *cell, t_mem *val)
+{
+  if (conf(cell, val))
+    return;
+  if (cell == regs[cr])
+    {
+      r_cr->set(*val);
+      pick_div();
+      pick_ctrl();
+      //*val= cell->get();
+      set_sr_irq();
+    }
+  else
+    {
+      cell->set(*val);
+      if (cell == regs[dr])
+	{
+	  s_txd= *val;
+	  s_tx_written= true;
+	  show_writable(false);
+	  if (!s_sending)
+	    {
+	      start_send();
+	    }      
+	}
+    }
+}
+
+t_mem
+cl_cia::conf_op(cl_memory_cell *cell, t_addr addr, t_mem *val)
+{
+  if (addr < serconf_common)
+    return cl_serial_hw::conf_op(cell, addr, val);
+  switch ((enum acia_cfg)addr)
+    {
+    case acia_cfg_base:
+      if (val)
+	{
+	  int i;
+	  if (uc->rom->valid_address(*val))
+	    {
+	      for (i= 0; i < 2; i++)
+		unregister_cell(regs[i]);
+	      base= *val;
+	      init();
+	    }
+	}
+      else
+	{
+	  cell->set(base);
+	}
+      break;
+    case acia_cfg_req:
+      if (val)
+	{
+	  //is_r->set_pass_to(*val);
+	  //is_t->set_pass_to(*val);
+	  is_r->set_parent(uc->search_it_src(*val));
+	  is_t->set_parent(uc->search_it_src(*val));
+	}
+      break;
+      
+    case acia_cfg_cr: break;
+    case acia_cfg_sr:
+      if (val)
+	{
+	  cell->set(*val&= 0x7f);
+	  set_sr_irq();
+	}
+      break;
+      
+    default:
+      break;
+    }
+  return cell->get();
+}
+
+void
+cl_cia::set_cmd(class cl_cmdline *cmdline,
+				class cl_console_base *con)
+{
+  class cl_cmd_arg *params[2]= {
+    cmdline->param(0),
+    cmdline->param(1)
+  };
+
+  if (cmdline->syntax_match(uc, NUMBER))
+    {
+      int i;
+      t_addr a= params[0]->value.number;
+      if (!uc->rom->valid_address(a))
+	{
+	  con->dd_printf("Address must be between 0x%x and 0x%x\n",
+			 AU(uc->rom->lowest_valid_address()),
+			 AU(uc->rom->highest_valid_address()));
+	  return;
+	}
+      for (i= 0; i < 2; i++)
+	unregister_cell(regs[i]);
+      base= a;
+      init();
+    }
+  else
+    con->dd_printf("set hardware uart[%d] address\n", id);
+}
+
+int
+cl_cia::tick(int cycles)
+{
+  char c;
+
+  if (!on)
+    return 0;
+
+  mcnt+= cycles;
+  if (mcnt >= div)
+    {
+      mcnt-= div;
+      if (ten)
+	s_tr_bit++;
+      if (ren)
+	s_rec_bit++;
+    }
+  else
+    return 0;
+  
+  if (s_sending &&
+      (s_tr_bit >= bits))
+    {
+      s_sending= false;
+      //io->dd_printf("%c", s_out);
+      io->write((char*)&s_out, 1);
+      s_tr_bit-= bits;
+      if (s_tx_written)
+	restart_send();
+      else
+	finish_send();
+    }
+  if ((ren) &&
+      io->get_fin() &&
+      !s_receiving)
+    {
+      if (cfg_get(serconf_check_often))
+	{
+	  if (io->input_avail())
+	    io->proc_input(0);
+	}
+      if (input_avail)
+	{
+	  s_receiving= true;
+	  s_rec_bit= 0;
+	}
+      else
+	show_idle(true);
+    }
+  if (s_receiving &&
+      (s_rec_bit >= bits))
+    {
+	{
+	  c= input;
+	  input_avail= false;
+	  s_in= c;
+	  received();
+	}
+      s_receiving= false;
+      s_rec_bit-= bits;
+    }
+  
+  return(0);
+}
+
+void
+cl_cia::start_send()
+{
+  if (ten)
+    {
+      s_out= s_txd;
+      s_tx_written= false;
+      s_sending= true;
+      s_tr_bit= 0;
+      show_writable(true);
+    }
+}
+
+void
+cl_cia::restart_send()
+{
+  if (ten)
+    {
+      s_out= s_txd;
+      s_tx_written= false;
+      s_sending= true;
+      s_tr_bit= 0;
+      show_writable(true);
+    }
+}
+
+void
+cl_cia::finish_send()
+{
+  show_writable(true);
+  show_tx_complete(true);
+}
+
+void
+cl_cia::received()
+{
+  set_dr(s_in);
+  cfg_write(serconf_received, s_in);
+  show_readable(true);
+}
+
+void
+cl_cia::reset(void)
+{
+  show_writable(true);
+  show_readable(false);
+}
+
+void
+cl_cia::happen(class cl_hw *where, enum hw_event he,
+		  void *params)
+{
+}
+
+
+void
+cl_cia::pick_div()
+{
+  switch (r_cr->get() & 0x03)
+    {
+    case 0x00: div= 1; break;
+    case 0x01: div= 16; break;
+    case 0x02: div= 64; break;
+    case 0x03: /*Master reset*/ div= 1; break;
+    }
+  mcnt= 0;
+}
+
+void
+cl_cia::pick_ctrl()
+{
+  switch ((r_cr->get() >> 2) & 7)
+    {
+    case 0: bits= 10; break;
+    case 1: bits= 10; break;
+    case 2: bits=  9; break;
+    case 3: bits=  9; break;
+    case 4: bits= 10; break;
+    case 5: bits=  9; break;
+    case 6: bits= 10; break;
+    case 7: bits= 10; break;
+    }
+  s_rec_bit= s_tr_bit= 0;
+  s_receiving= false;
+  s_tx_written= false;
+}
+
+
+void
+cl_cia::show_writable(bool val)
+{
+  // TDRE: Transmit Data Register Empty: sr.1
+  if (val)
+    r_sr->set(r_sr->get() | 2);
+  else
+    r_sr->set(r_sr->get() & ~2);
+  set_sr_irq();
+}
+
+void
+cl_cia::show_readable(bool val)
+{
+  // RDRF: Receive Data Register Full (sr.0)
+  if (val)
+    r_sr->set(r_sr->get() | 1);
+  else
+    r_sr->set(r_sr->get() & ~1);
+  set_sr_irq();
+}
+
+void
+cl_cia::show_tx_complete(bool val)
+{
+  show_writable(val);
+}
+
+void
+cl_cia::show_idle(bool val)
+{
+}
+
+void
+cl_cia::set_dr(t_mem val)
+{
+  regs[dr]->set(val);
+}
+
+void
+cl_cia::set_sr_irq(void)
+{
+  bool t= false, r= false;
+  u8_t c= r_cr->get(), s= r_sr->get();
+  t= ((c & 0x60) == 0x20) && (s & 2);
+  r= (c & 0x80) && (s & 1);
+  s&= 0x7f;
+  if (r || t)
+    s|= 0x80;
+  r_sr->set(s);
+}
+
+void
+cl_cia::print_info(class cl_console_base *con)
+{
+  u8_t u8= r_sr->get();//regs[sr]->get();
+  con->dd_printf("%s[%d] at 0x%06x %s\n", id_string, id, base, on?"on ":"off");
+  con->dd_printf("Input: ");
+  class cl_f *fin= io->get_fin(), *fout= io->get_fout();
+  if (fin)
+    con->dd_printf("%30s/%3d ", fin->get_file_name(), fin->file_id);
+  con->dd_printf("Output: ");
+  if (fout)
+    con->dd_printf("%30s/%3d", fout->get_file_name(), fout->file_id);
+  con->dd_printf("\n");
+  con->dd_printf("mcnt=%d\n", mcnt);
+  con->dd_printf("Sending: %s, %s, %2d/%2d bits\n",
+		 s_sending?"yes":"no ",
+		 ten?"en ":"dis",
+		 s_tr_bit, bits);
+  con->dd_printf("Receiving: %s, %s, %2d/%2d bits\n",
+		 s_receiving?"yes":"no ",
+		 ren?"en ":"dis",
+		 s_rec_bit, bits);
+  con->dd_printf("CR: ");
+  con->print_bin(r_cr->get(), 8);
+  con->dd_printf(" 0x%02x", r_cr->get());
+  con->dd_printf(" div=%8d bits=%2d\n", div, bits);
+  con->dd_printf("SR: ");
+  con->print_bin(u8, 8);
+  con->dd_printf(" 0x%02x", u8);
+  con->dd_printf(" RDRF=%d TDRE=%d\n",
+		 (u8&1)?1:0,
+		 (u8&2)?1:0);
+  //print_cfg_info(con);
+}
+
+/* End of motorola.src/cia.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/motorola.src/ciacl.h sdcc-4.2.0+dfsg/sim/ucsim/motorola.src/ciacl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/motorola.src/ciacl.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/motorola.src/ciacl.h	2021-10-29 17:39:15.000000000 +0000
@@ -0,0 +1,107 @@
+/*
+ * Simulator of microcontrollers (motorola.src/ciacl.h)
+ *
+ * Copyright (C) @@S@@,@@Y@@ Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef CIACL_HEADER
+#define CIACL_HEADER
+
+//#include "fiocl.h"
+//#include "stypes.h"
+//#include "pobjcl.h"
+
+#include "uccl.h"
+#include "serial_hwcl.h"
+
+//#include "newcmdposixcl.h"
+
+enum acia_cfg
+  {
+    acia_cfg_base	= serconf_nr+0,
+    acia_cfg_cr		= serconf_nr+1,
+    acia_cfg_sr		= serconf_nr+2,
+    acia_cfg_req	= serconf_nr+3,
+  };
+
+class cl_serial_listener;
+
+class cl_cia: public cl_serial_hw
+{
+ protected:
+  t_addr base;
+  class cl_memory_cell *regs[2];
+  int div;
+  int mcnt;
+  class cl_it_src *is_r, *is_t;
+  class cl_memory_cell *r_cr;         // Copy of written CR value
+  class cl_memory_cell *r_sr;         // Simulated SR value
+  u8_t  s_in;         // Serial channel input reg
+  u8_t  s_out;        // Serial channel output reg
+  u8_t  s_txd;	      // TX data register
+  bool  s_sending;    // Transmitter is working (s_out is not empty)
+  bool  s_receiving;  // Receiver is working (s_in is shifting)
+  bool  s_tx_written; // TX data reg has been written
+  int   s_rec_bit;    // Bit counter of receiver
+  int   s_tr_bit;     // Bit counter of transmitter
+  uchar bits;         // Nr of bits to send/receive
+  bool  ren;          // Receiving is enabled
+  bool  ten;          // Transmitter is enabled
+ public:
+  cl_cia(class cl_uc *auc, int aid, t_addr abase);
+  virtual ~cl_cia(void);
+  virtual int init(void);
+  virtual unsigned int cfg_size(void) { return 11; }
+  virtual const char *cfg_help(t_addr addr);
+
+  virtual t_mem read(class cl_memory_cell *cell);
+  virtual void write(class cl_memory_cell *cell, t_mem *val);
+  virtual t_mem conf_op(cl_memory_cell *cell, t_addr addr, t_mem *val);
+  virtual void set_cmd(class cl_cmdline *cmdline, class cl_console_base *con);
+
+  virtual int tick(int cycles);
+  virtual void start_send();
+  virtual void restart_send();
+  virtual void finish_send();
+  virtual void received();
+  virtual void reset(void);
+  virtual void happen(class cl_hw *where, enum hw_event he,
+                      void *params);
+
+  virtual void pick_div();
+  virtual void pick_ctrl();
+  virtual void show_writable(bool val);
+  virtual void show_readable(bool val);
+  virtual void show_tx_complete(bool val);
+  virtual void show_idle(bool vol);
+  virtual void set_dr(t_mem val);
+  virtual void set_sr_irq(void);
+  
+  virtual void print_info(class cl_console_base *con);
+};
+
+
+#endif
+
+/* End of motorola.src/ciacl.h */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/motorola.src/clean.mk sdcc-4.2.0+dfsg/sim/ucsim/motorola.src/clean.mk
--- sdcc-4.0.0+dfsg/sim/ucsim/motorola.src/clean.mk	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/motorola.src/clean.mk	2021-05-20 07:49:29.000000000 +0000
@@ -0,0 +1,28 @@
+#
+# ucsim motorola.src/clean.mk
+#
+
+# Deleting all files created by building the program
+# --------------------------------------------------
+clean:
+	rm -f *core *[%~] *.[oa]
+	rm -f .[a-z]*~
+
+# Deleting all files created by configuring or building the program
+# -----------------------------------------------------------------
+distclean: clean
+	rm -f config.cache config.log config.status
+	rm -f Makefile *.dep
+
+
+# Like clean but some files may still exist
+# -----------------------------------------
+mostlyclean: clean
+
+
+# Deleting everything that can reconstructed by this Makefile. It deletes
+# everything deleted by distclean plus files created by bison, etc.
+# -----------------------------------------------------------------------
+realclean: distclean
+
+# End of motorola.src/clean.mk
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/motorola.src/Makefile.in sdcc-4.2.0+dfsg/sim/ucsim/motorola.src/Makefile.in
--- sdcc-4.0.0+dfsg/sim/ucsim/motorola.src/Makefile.in	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/motorola.src/Makefile.in	2022-01-09 14:02:03.000000000 +0000
@@ -0,0 +1,119 @@
+#
+# ucsim motorola.src/Makefile
+#
+# (c) Drotos Daniel, Talker Bt. 1997
+#
+
+STARTYEAR	= 1997
+
+SHELL		= /bin/sh
+CXX		= @CXX@
+CPP		= @CPP@
+CXXCPP		= @CXXCPP@
+RANLIB		= @RANLIB@
+INSTALL	        = @INSTALL@
+MAKEDEP         = @MAKEDEP@
+AR		= @AR@
+
+LEX		= @LEX@
+YACC		= @YACC@
+
+top_builddir	= @top_builddir@
+top_srcdir	= @top_srcdir@
+
+DEFS            = $(subs -DHAVE_CONFIG_H,,@DEFS@)
+CPPFLAGS        = @CPPFLAGS@ -I$(srcdir) -I$(top_srcdir) -I$(top_builddir) \
+		  -I$(top_srcdir)/sim.src -I$(top_srcdir)/gui.src -I$(top_srcdir)/cmd.src
+CFLAGS          = @WALL_FLAG@ @CFLAGS@
+CXXFLAGS        = @WALL_FLAG@ @CXXFLAGS@
+WINSOCK_AVAIL   = @WINSOCK_AVAIL@
+
+prefix          = @prefix@
+exec_prefix     = @exec_prefix@
+bindir          = @bindir@
+libdir          = @libdir@
+datadir         = @datadir@
+datarootdir     = @datarootdir@
+includedir      = @includedir@
+mandir          = @mandir@
+man1dir         = $(mandir)/man1
+man2dir         = $(mandir)/man2
+infodir         = @infodir@
+srcdir          = @srcdir@
+VPATH           = @srcdir@
+
+OBJECTS         = pia.o cia.o
+
+LOCAL_OBJECTS   = 
+
+SOURCES         = $(addprefix $(srcdir)/, $(OBJECTS:.o=.cc))
+LOCAL_SOURCES   = $(LOCAL_OBJECTS:.o=.cc)
+
+# Compiling entire program or any subproject
+# ------------------------------------------
+all: checkconf motorolalib
+
+motorola.src: all
+
+
+# Compiling and installing everything and runing test
+# ---------------------------------------------------
+install: all installdirs
+
+
+# Deleting all the installed files
+# --------------------------------
+uninstall:
+
+
+# Performing self-test
+# --------------------
+check:
+
+test:
+
+baseline:
+
+
+# Performing installation test
+# ----------------------------
+installcheck:
+
+
+# Creating installation directories
+# ---------------------------------
+installdirs:
+
+
+# Creating dependencies
+# ---------------------
+dep: $(LOCAL_SOURCES) Makefile.dep
+
+Makefile.dep: $(SOURCES) $(LOCAL_SOURCES) $(srcdir)/*.h
+	$(MAKEDEP) $(CPPFLAGS) $(SOURCES) $(LOCAL_SOURCES) >Makefile.dep
+
+-include Makefile.dep
+include $(srcdir)/clean.mk
+
+
+# My rules
+# --------
+
+motorolalib: $(top_builddir)/libmotorola.a
+
+$(top_builddir)/libmotorola.a: $(OBJECTS) $(LOCAL_OBJECTS)
+	$(AR) -rc $@ $(OBJECTS) $(LOCAL_OBJECTS)
+	$(RANLIB) $@
+
+.cc.o:
+	$(CXX) $(CXXFLAGS) $(CPPFLAGS) $(TARGET_ARCH) -c $< -o $@
+
+
+# Remaking configuration
+# ----------------------
+checkconf:
+	@if [ -f $(top_builddir)/devel ]; then\
+	  $(MAKE) -C $(top_builddir) -f conf.mk srcdir="$(srcdir)" top_builddir="$(top_builddir)" freshconf;\
+	fi
+
+# End of motorola.src/Makefile.in
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/motorola.src/pia.cc sdcc-4.2.0+dfsg/sim/ucsim/motorola.src/pia.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/motorola.src/pia.cc	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/motorola.src/pia.cc	2021-08-24 15:42:16.000000000 +0000
@@ -0,0 +1,682 @@
+/*
+ * Simulator of microcontrollers (motorola.src/pia.cc)
+ *
+ * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#include 
+#include 
+
+// cmd
+#include "argcl.h"
+
+// sim
+#include "itsrccl.h"
+
+#include "piacl.h"
+
+
+cl_pia::cl_pia(class cl_uc *auc, int aid):
+  cl_hw(auc, HW_PORT, aid, "pia")
+{
+  base= 0xc010;
+}
+
+cl_pia::cl_pia(class cl_uc *auc, int aid, t_addr the_addr):
+  cl_hw(auc, HW_PORT, aid, "pia")
+{
+  base= the_addr;
+}
+
+int
+cl_pia::init(void)
+{
+  cl_hw::init();
+
+  rs[0]= register_cell(uc->rom, base+0);
+  rs[1]= register_cell(uc->rom, base+1);
+  rs[2]= register_cell(uc->rom, base+2);
+  rs[3]= register_cell(uc->rom, base+3);
+
+  cra = rs[1];
+  ddra= cfg_cell(cfg_ddra);
+  ora = cfg_cell(cfg_ora);
+  ina = cfg_cell(cfg_ina);
+  crb = rs[2];
+  ddrb= cfg_cell(cfg_ddrb);
+  orb = cfg_cell(cfg_orb);
+  inb = cfg_cell(cfg_inb);
+  
+  oca = cfg_cell(cfg_oca);
+  ddca= cfg_cell(cfg_ddca);
+  inca= cfg_cell(cfg_inca);
+  ocb = cfg_cell(cfg_ocb);
+  ddcb= cfg_cell(cfg_ddcb);
+  incb= cfg_cell(cfg_incb);
+
+  cfg_set(cfg_reqs, 0);
+  cfg_set(cfg_ca1_req, 'i');
+  cfg_set(cfg_ca2_req, 'i');
+  cfg_set(cfg_cb1_req, 'i');
+  cfg_set(cfg_cb2_req, 'i');
+  
+  chars pn= chars("", "pia%d_", id);
+
+  uc->vars->add(pn + "base", cfg, cfg_base, 7, 0, cfg_help(cfg_base));
+  uc->vars->add(pn + "on", cfg, cfg_on, 7, 0, cfg_help(cfg_on));
+  
+  uc->vars->add(pn + "cra", uc->rom, base+1, 7, 0, "CRA Control Register port A");
+  uc->vars->add(pn + "crb", uc->rom, base+3, 7, 0, "CRB Control Register port B");
+
+  uc->vars->add(pn + "ddra", cfg, cfg_ddra, 7, 0, cfg_help(cfg_ddra));
+  uc->vars->add(pn + "ora", cfg, cfg_ora, 7, 0, cfg_help(cfg_ora));
+  uc->vars->add(pn + "ina", cfg, cfg_ina, 7, 0, cfg_help(cfg_ina));
+  uc->vars->add(pn + "ira", cfg, cfg_ira, 7, 0, cfg_help(cfg_ira));
+
+  uc->vars->add(pn + "ddrb", cfg, cfg_ddrb, 7, 0, cfg_help(cfg_ddrb));
+  uc->vars->add(pn + "orb", cfg, cfg_orb, 7, 0, cfg_help(cfg_orb));
+  uc->vars->add(pn + "inb", cfg, cfg_inb, 7, 0, cfg_help(cfg_inb));
+  uc->vars->add(pn + "irb", cfg, cfg_irb, 7, 0, cfg_help(cfg_irb));
+
+  uc->vars->add(pn + "oca", cfg, cfg_oca, 7, 0, cfg_help(cfg_oca));
+  uc->vars->add(pn + "ddca", cfg, cfg_ddca, 7, 0, cfg_help(cfg_ddca));
+  uc->vars->add(pn + "inca", cfg, cfg_inca, 7, 0, cfg_help(cfg_inca));
+
+  uc->vars->add(pn + "ocb", cfg, cfg_ocb, 7, 0, cfg_help(cfg_ocb));
+  uc->vars->add(pn + "ddcb", cfg, cfg_ddcb, 7, 0, cfg_help(cfg_ddcb));
+  uc->vars->add(pn + "incb", cfg, cfg_incb, 7, 0, cfg_help(cfg_incb));
+
+  uc->vars->add(pn + "reqs", cfg, cfg_reqs, 7, 0, cfg_help(cfg_reqs));
+  uc->vars->add(pn + "ca1_req", cfg, cfg_ca1_req, 7, 0, cfg_help(cfg_ca1_req));
+  uc->vars->add(pn + "ca2_req", cfg, cfg_ca2_req, 7, 0, cfg_help(cfg_ca2_req));
+  uc->vars->add(pn + "cb1_req", cfg, cfg_cb1_req, 7, 0, cfg_help(cfg_cb1_req));
+  uc->vars->add(pn + "cb2_req", cfg, cfg_cb2_req, 7, 0, cfg_help(cfg_cb2_req));
+
+  is_ca1= new cl_it_src(uc, 1,
+			cra, 1, //1,
+			cra, 0x80,
+			0, false, false,
+			pn+"CA1",
+			0);
+  is_ca1->init();
+  is_ca1->set_ie_value(1);
+  is_ca1->set_parent(uc->search_it_src('i'));
+  uc->it_sources->add(is_ca1);
+  is_ca2= new cl_it_src(uc, 2,
+			cra, 0x28, //0x08,
+			cra, 0x40,
+			0, false, false,
+			pn+"CA2",
+			0);
+  is_ca2->init();
+  is_ca2->set_ie_value(0x08);
+  is_ca2->set_parent(uc->search_it_src('i'));
+  uc->it_sources->add(is_ca2);
+  is_cb1= new cl_it_src(uc, 3,
+			crb, 1, //1,
+			crb, 0x80,
+			0, false, false,
+			pn+"CB1",
+			0);
+  is_cb1->init();
+  is_cb1->set_ie_value(1);
+  is_cb1->set_parent(uc->search_it_src('i'));
+  uc->it_sources->add(is_cb1);
+  is_cb2= new cl_it_src(uc, 4,
+			crb, 0x28, //0x08,
+			crb, 0x40,
+			0, false, false,
+			pn+"CB2",
+			0);
+  is_cb2->init();
+  is_cb2->set_parent(uc->search_it_src('i'));
+  is_cb2->set_ie_value(0x08);
+  uc->it_sources->add(is_cb2);
+  
+  return(0);
+}
+
+void
+cl_pia::reset(void)
+{
+  cra->set(0);
+  cra->write(0);
+  ddra->write(0);
+  ora->write(0);
+  crb->set(0);
+  crb->write(0);
+  ddrb->write(0);
+  orb->write(0);
+
+  oca->write(2);
+  ocb->write(2);
+
+  prev_ca1= ca1();
+  prev_ca2= ca2();
+  prev_cb1= cb1();
+  prev_cb2= cb2();
+}
+
+const char *
+cl_pia::cfg_help(t_addr addr)
+{
+  switch ((enum pia_cfg)addr)
+    {
+    case cfg_on		: return "Turn/get on/off state (bool, RW)";
+    case cfg_reqs	: return "IRQS of CA2, CA1, CB2, CB1 (int, RW)";
+    case cfg_ca1_req	: return "Req mode of CA1 'i'=IRQ 'f'=FIRQ 'n'=NMI (int, RW)";
+    case cfg_ca2_req	: return "Req mode of CA2 'i'=IRQ 'f'=FIRQ 'n'=NMI (int, RW)";
+    case cfg_cb1_req	: return "Req mode of CB1 'i'=IRQ 'f'=FIRQ 'n'=NMI (int, RW)";
+    case cfg_cb2_req	: return "Req mode of CB2 'i'=IRQ 'f'=FIRQ 'n'=NMI (int, RW)";
+    case cfg_base	: return "Base address of the port (int, RW)";
+    case cfg_ddra	: return "DDRA - Data Direction Register A (int, RW)";
+    case cfg_ora	: return "ORA  - Peripheral Register A (int, RW)";
+    case cfg_ina	: return "ina  - Outside value of port A pins (int, RW)";
+    case cfg_ira	: return "ira  - Read value of port A (int RO)";
+    case cfg_ddrb	: return "DDRB - Data Direction Register B (int, RW)";
+    case cfg_orb	: return "ORB  - Peripheral Register B (int, RW)";
+    case cfg_inb	: return "inb  - Outside value of port B pins (int, RW)";
+    case cfg_irb	: return "irb  - Read value of port B (int RO)";
+    case cfg_oca	: return "oca  - Output value of port CA (int, RW)";
+    case cfg_ddca	: return "ddca - Direction of port CA (int, RW)";
+    case cfg_inca	: return "inca - Outside value of port CA pins (int, RW)";
+    case cfg_ocb	: return "ocb  - Output value of port CB (int, RW)";
+    case cfg_ddcb	: return "ddcb - Direction of port CB (int, RW)";
+    case cfg_incb	: return "incb - Outside value of port CB pins (int, RW)";
+    }
+  return "Not used";
+}
+
+class cl_memory_cell *
+cl_pia::reg(class cl_memory_cell *cell_rs)
+{
+  if (cell_rs == rs[0])
+    {
+      if (cra->get() & 4)
+	return ora;
+      else
+	return ddra;
+    }
+  else if (cell_rs == rs[1])
+    return cra;
+  else if (cell_rs == rs[2])
+    {
+      if (crb->get() & 4)
+	return orb;
+      else
+	return ddrb;
+    }
+  else if (cell_rs == rs[3])
+    return crb;
+  return NULL;
+}
+
+t_mem
+cl_pia::read(class cl_memory_cell *cell)
+{
+  class cl_memory_cell *r= reg(cell);
+  conf(cell, NULL);
+  if (r != NULL)
+    {
+      if (r == ora)
+	{
+	  cra->set(cra->get() & 0x3f);
+	  if ((cra->get() & 0x30) == 0x20)
+	    {
+	      oca->write(oca->get() & ~0x02);
+	    }
+	  return ira();
+	}
+      if (r == orb)
+	{
+	  crb->set(crb->get() & 0x3f);
+	  return irb();
+	}
+      return r->get();
+    }
+  return cell->get();
+}
+
+void
+cl_pia::write(class cl_memory_cell *cell, t_mem *val)
+{
+  class cl_memory_cell *r= reg(cell);
+  if (val)
+    {
+      if (r == cra || r == crb)
+	{
+	  *val&= 0x3f;
+	  *val|= (r->get() & 0xc0);
+
+	  if (r == cra)
+	    {
+	      if ((*val & 0x30) == 0x30)
+		{
+		  if (*val & 0x08)
+		    oca->write(oca->get() | 0x02);
+		  else
+		    oca->write(oca->get() & ~0x02);
+		}
+	    }
+	  if (r == crb)
+	    {
+	      if ((*val & 0x30) == 0x30)
+		{
+		  if (*val & 0x08)
+		    ocb->write(ocb->get() | 0x02);
+		  else
+		    ocb->write(ocb->get() & ~0x02);
+		}
+	    }
+	}
+      if (r == orb)
+	{
+	  if ((crb->get() & 0x30) == 0x20)
+	    ocb->write(ocb->get() & ~0x02);
+	}
+    }
+  conf(cell, val);
+  if (r)
+    r->set(*val);
+  check_edges();
+}
+
+t_mem
+cl_pia::conf_op(cl_memory_cell *cell, t_addr addr, t_mem *val)
+{
+  t_mem v;
+  class cl_memory_cell *r= NULL;
+  switch ((enum pia_cfg)addr)
+    {
+    case cfg_on	:  // turn this HW on/off
+      if (val)
+	{
+	  if (*val)
+	    on= true;
+	  else
+	    on= false;
+	}
+      v= on?1:0;
+      cell->set(v);
+      break;
+    case cfg_base:
+      if (val)
+	{
+	  int i;
+	  if (uc->rom->valid_address(*val))
+	    {
+	      for (i= 0; i < 3; i++)
+		unregister_cell(rs[i]);
+	      base= *val;
+	      init();
+	    }
+	}
+      cell->set(base);
+      break;
+    case cfg_reqs	:
+      if (val)
+	{
+	  u8_t ca= cra->get() & 0x3f;
+	  ca|= (*val&8)?0x40:0;
+	  ca|= (*val&4)?0x80:0;
+	  cra->set(ca);
+	  u8_t cb= crb->get() & 0x3f;
+	  ca|= (*val&2)?0x40:0;
+	  ca|= (*val&1)?0x80:0;
+	  crb->set(cb);
+	}
+      else
+	{
+	  u8_t ca= cra->get(), cb= crb->get();
+	  cell->set(
+		    ((ca&0x40)?8:0) |
+		    ((ca&0x80)?4:0) |
+		    ((cb&0x40)?2:0) |
+		    ((cb&0x80)?1:0)
+		    );
+	}
+      break;
+    case cfg_ca1_req	:
+      if (val)
+	if (is_ca1)
+	  //is_ca1->set_pass_to(*val);
+	  is_ca1->set_parent(uc->search_it_src(*val));
+      break;
+    case cfg_ca2_req	:
+      if (val)
+	if (is_ca2)
+	  //is_ca2->set_pass_to(*val);
+	  is_ca2->set_parent(uc->search_it_src(*val));
+      break;
+    case cfg_cb1_req	:
+      if (val)
+	if (is_cb1)
+	  //is_cb1->set_pass_to(*val);
+	  is_cb1->set_parent(uc->search_it_src(*val));
+      break;
+    case cfg_cb2_req	:
+      if (val)
+	if (is_cb2)
+	  //is_cb2->set_pass_to(*val);
+	  is_cb2->set_parent(uc->search_it_src(*val));
+      break;
+    case cfg_ddra	: r= ddra; break;
+    case cfg_ora	: r= ora; break;
+    case cfg_ina	: r= ina; break;
+    case cfg_ira	:
+      cell->set(ira());
+      if (val)
+	*val= cell->get();
+      break;
+    case cfg_ddrb	: r= ddrb; break;
+    case cfg_orb	: r= orb; break;
+    case cfg_inb	: r= inb; break;
+    case cfg_irb	:
+      cell->set(irb());
+      if (val)
+	*val= cell->get();
+      break;
+    case cfg_oca	: r= oca;
+      if (val)
+	*val&= 2;
+      break;
+    case cfg_ddca	: r= ddca;
+      if (val)
+	{
+	  *val&= 2;
+	  u8_t i= cra->get() & 0xdf;
+	  if (*val) i|= 0x20;
+	  cra->set(i);
+	}
+      else
+	r->set((cra->get() & 0x20)?2:0);
+      break;
+    case cfg_inca	: r= inca;
+      if (val)
+	*val&= 3;
+      break;
+    case cfg_ocb	: r= ocb;
+      if (val)
+	*val&= 2;
+      break;
+    case cfg_ddcb	: r= ddcb;
+      if (val)
+	{
+	  *val&= 2;
+	  u8_t i= crb->get() & 0xdf;
+	  if (*val) i|= 0x20;
+	  crb->set(i);
+	}
+      else
+	r->set((crb->get() & 0x20)?2:0);
+      break;
+    case cfg_incb	: r= incb;
+      if (val)
+	*val&= 3;
+      break;
+    }
+  if (r)
+    {
+      if (val)
+	r->set(*val);
+      v= r->get();
+      cell->set(v);
+    }
+  v= cell->get();
+  return v;
+}
+
+int
+cl_pia::ira()
+{
+  u8_t i, o, d;
+  d= ddra->get();
+  i= ina->get();
+  o= ora->get();
+  return (~d&i) | (d&o&i);
+}
+
+int
+cl_pia::irb()
+{
+  u8_t i, o, d;
+  d= ddrb->get();
+  i= inb->get();
+  o= orb->get();
+  return (~d&i) | (d&o);	    
+}
+
+int
+cl_pia::ca1()
+{
+  return inca->get() & 1;
+}
+
+int
+cl_pia::ca2(void)
+{
+  u8_t ca= cra->get();
+  if (ca & 0x20)
+    {
+      // out
+      return (oca->get() & 2)?1:0;
+    }
+  // input
+  return (inca->get() & 2)?1:0;
+  return 0;
+}
+
+int
+cl_pia::cb1()
+{
+  return incb->get() & 1;
+}
+
+int
+cl_pia::cb2(void)
+{
+  u8_t cb= crb->get();
+  if (cb & 0x20)
+    {
+      // out
+      return (ocb->get() & 2)?1:0;
+    }
+  // input
+  return (incb->get() & 2)?1:0;
+  return 0;
+}
+
+int
+cl_pia::check_edges(void)
+{
+  class cl_memory_cell *cr= cra;
+  int signal= ca1();
+  int edge= ((cr->get())&2)>>1;
+  int *prev= &prev_ca1;
+  
+  if (*prev != signal)
+    {
+      *prev= signal;
+      if (!(edge ^ signal))
+	{
+	  cr->set(cr->get() | 0x80);
+	  if ((cr->get() & 0x38) == 0x20)
+	    {
+	      oca->write(oca->get() | 0x02);
+	    }
+	}
+    }
+  if (!(cr->get() & 0x20))
+    {
+      signal= ca2();
+      edge= (cr->get() & 0x10) >> 4;
+      prev= &prev_ca2;
+      if (*prev != signal)
+	{
+	  *prev= signal;
+	  if (!(edge ^ signal))
+	    cr->set(cr->get() | 0x40);
+	}
+    }
+  
+  cr= crb;
+  signal= cb1();
+  edge= ((cr->get())&2)>>1;
+  prev= &prev_cb1;
+  if (*prev != signal)
+    {
+      *prev= signal;
+      if (!(edge ^ signal))
+	{
+	  cr->set(cr->get() | 0x80);
+	  if ((cr->get() & 0x38) == 0x20)
+	    {
+	      // TODO: CRB-b7 must first be cleared by a read of data.
+	      ocb->write(ocb->get() | 0x02);
+	    }
+	}
+    }
+  if (!(cr->get() & 0x20))
+    {
+      signal= cb2();
+      edge= (cr->get() & 0x10) >> 4;
+      prev= &prev_cb2;
+      if (*prev != signal)
+	{
+	  *prev= signal;
+	  if (!(edge ^ signal))
+	    cr->set(cr->get() | 0x40);
+	}
+    }
+  return 0;
+}
+
+int
+cl_pia::tick(int cycles)
+{
+  if ((cra->get() & 0x38) == 0x28)
+    {
+      oca->write(oca->get() | 0x02);
+    }
+  if ((crb->get() & 0x38) == 0x28)
+    {
+      ocb->write(ocb->get() | 0x02);
+    }
+  return 0;
+}
+
+void
+cl_pia::set_cmd(class cl_cmdline *cmdline, class cl_console_base *con)
+{
+  class cl_cmd_arg *params[2]= {
+    cmdline->param(0),
+    cmdline->param(1)
+  };
+
+  if (cmdline->syntax_match(uc, NUMBER))
+    {
+      int i;
+      t_addr a= params[0]->value.number;
+      if (!uc->rom->valid_address(a))
+	{
+	  con->dd_printf("Address must be between 0x%x and 0x%x\n",
+			 AU(uc->rom->lowest_valid_address()),
+			 AU(uc->rom->highest_valid_address()));
+	  return;
+	}
+      for (i= 0; i < 3; i++)
+	unregister_cell(rs[i]);
+      base= a;
+      init();
+    }
+  else
+    con->dd_printf("set hardware pia[%d] address\n", id);
+}
+
+void
+cl_pia::print_info(class cl_console_base *con)
+{
+  u8_t ca= cra->read();
+  u8_t cb= crb->read();
+  con->dd_printf("%s[%d] at 0x%06x %s\n", id_string, id, base, on?"on ":"off");
+  con->dd_printf("0x%04x ", base+0);
+  if (ca & 4)
+    con->dd_printf(" ORA 0x%02x", ora->get());
+  else
+    con->dd_printf("DDRA 0x%02x", ddra->get());
+  con->dd_printf("   IRA 0x%02x", ira());
+  con->dd_printf("\n");
+  con->dd_printf("0x%04x ", base+1);
+  con->dd_printf(" CRA 0x%02x", ca);
+  con->dd_printf("   IRQA1 %d", (ca&0x80)?1:0);
+  con->dd_printf("   EnA1 %d", (ca&0x01)?1:0);
+  con->dd_printf("   EdgA1 %c", (ca&0x02)?'R':'F');
+  con->dd_printf("   CA1 %d", ca1());
+  con->dd_printf("\n                ");
+  con->dd_printf("   IRQA2 %d", (ca&0x40)?1:0);
+  con->dd_printf("   EnA2 %d", ((ca&0x28)==0x08)?1:0);
+  con->dd_printf("   EdgA2 %c", (ca&0x10)?'R':'F');
+  con->dd_printf("   CA2 %d", ca2());
+  con->dd_printf("\n                ");
+  con->dd_printf("   DirA2 %s", (ca&0x20)?"Out":"In ");
+  con->dd_printf(" ModA2 ");
+       if ((ca&0x38) == 0x30) con->dd_printf("Output 0               ");
+  else if ((ca&0x38) == 0x38) con->dd_printf("Output 1               ");
+  else if ((ca&0x38) == 0x20) con->dd_printf("Read strobe, A1 restore");
+  else if ((ca&0x38) == 0x28) con->dd_printf("Read strobe,  E restore");
+  else                        con->dd_printf("Input                  ");
+  con->dd_printf("\n");
+  
+  con->dd_printf("0x%04x ", base+2);
+  if (cb & 4)
+    con->dd_printf(" ORB 0x%02x", orb->get());
+  else
+    con->dd_printf("DDRB 0x%02x", ddrb->get());
+  con->dd_printf("   IRB 0x%02x", irb());
+  con->dd_printf("\n");
+  con->dd_printf("0x%04x ", base+3);
+  con->dd_printf(" CRB 0x%02x", cb);
+  con->dd_printf("   IRQB1 %d", (cb&0x80)?1:0);
+  con->dd_printf("   EnB1 %d", (cb&0x01)?1:0);
+  con->dd_printf("   EdgB1 %c", (cb&0x02)?'R':'F');
+  con->dd_printf("   CB1 %d", cb1());
+  con->dd_printf("\n                ");
+  con->dd_printf("   IRQB2 %d", (cb&0x40)?1:0);
+  con->dd_printf("   EnB2 %d", ((cb&0x28)==0x08)?1:0);
+  con->dd_printf("   EdgB2 %c", (cb&0x10)?'R':'F');
+  con->dd_printf("   CB2 %d", cb2());
+  con->dd_printf("\n                ");
+  con->dd_printf("   DirB2 %s", (ca&0x20)?"Out":"In ");
+  con->dd_printf(" ModB2 ");
+       if ((cb&0x38) == 0x30) con->dd_printf("Output 0                ");
+  else if ((cb&0x38) == 0x38) con->dd_printf("Output 1                ");
+  else if ((cb&0x38) == 0x20) con->dd_printf("Write strobe, A1 restore");
+  else if ((cb&0x38) == 0x28) con->dd_printf("Write strobe,  E restore");
+  else                        con->dd_printf("Input                   ");
+  con->dd_printf("\n");
+
+  //print_cfg_info(con);
+}
+
+/* End of motorola.src/pia.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/motorola.src/piacl.h sdcc-4.2.0+dfsg/sim/ucsim/motorola.src/piacl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/motorola.src/piacl.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/motorola.src/piacl.h	2021-10-29 17:39:15.000000000 +0000
@@ -0,0 +1,111 @@
+/*
+ * Simulator of microcontrollers (motorola.srcpiacl.h)
+ *
+ * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef PIACL_HEADER
+#define PIACL_HEADER
+
+#include "hwcl.h"
+#include "port_hwcl.h"
+
+
+enum pia_cfg
+  {
+   cfg_on	= 0,
+   cfg_base	= 1,
+   cfg_reqs	= 2,
+   cfg_ca1_req	= 3,
+   cfg_ca2_req	= 4,
+   cfg_cb1_req	= 5,
+   cfg_cb2_req	= 6,
+   cfg_ddra	= 7,
+   cfg_ora	= 8,
+   cfg_ina	= 9,
+   cfg_ira	= 10,
+   cfg_ddrb	= 11,
+   cfg_orb	= 12,
+   cfg_inb	= 13,
+   cfg_irb	= 14,
+   cfg_oca	= 15, // out value of CA2
+   cfg_ddca	= 16, // data direction of CA2(,CA1)
+   cfg_inca	= 17, // input value for CA2,CA1
+   cfg_ocb	= 18, // out value of CB2
+   cfg_ddcb	= 19, // data direction of CB2(,CB1)
+   cfg_incb	= 20, // input value for CB2,CB1
+  };
+
+class cl_pia: public cl_hw
+{
+public:
+  t_addr base;
+  class cl_memory_cell *cra;
+  class cl_memory_cell *ddra;
+  class cl_memory_cell *ora;
+  class cl_memory_cell *ina;
+  class cl_memory_cell *crb;
+  class cl_memory_cell *ddrb;
+  class cl_memory_cell *orb;
+  class cl_memory_cell *inb;
+  class cl_memory_cell *oca;
+  class cl_memory_cell *ddca;
+  class cl_memory_cell *inca;
+  class cl_memory_cell *ocb;
+  class cl_memory_cell *ddcb;
+  class cl_memory_cell *incb;
+  class cl_memory_cell *rs[4];
+  int prev_ca1, prev_ca2, prev_cb1, prev_cb2;
+  class cl_it_src *is_ca1, *is_ca2, *is_cb1, *is_cb2;
+ public:
+  cl_pia(class cl_uc *auc, int aid);
+  cl_pia(class cl_uc *auc, int aid, t_addr the_addr);
+  virtual int init(void);
+  virtual unsigned int cfg_size(void) { return 21; }
+  virtual const char *cfg_help(t_addr addr);
+  virtual void set_cmd(class cl_cmdline *cmdline, class cl_console_base *con);
+
+  virtual class cl_memory_cell *reg(class cl_memory_cell *cell_rs);
+  virtual t_mem read(class cl_memory_cell *cell);
+  virtual void write(class cl_memory_cell *cell, t_mem *val);
+  virtual t_mem conf_op(cl_memory_cell *cell, t_addr addr, t_mem *val);
+
+  virtual int ira(void);
+  virtual int irb(void);
+  virtual int ca1(void);
+  virtual int ca2(void);
+  virtual int cb1(void);
+  virtual int cb2(void);
+  
+  virtual int check_edges(void);
+  virtual int tick(int cycles);
+  virtual void reset(void);
+  
+  virtual void print_info(class cl_console_base *con);
+};
+
+
+#endif
+
+/* End of motorola.src/piacl.h */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/NEWS sdcc-4.2.0+dfsg/sim/ucsim/NEWS
--- sdcc-4.0.0+dfsg/sim/ucsim/NEWS	2019-07-02 08:44:01.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/NEWS	2022-01-07 16:30:41.000000000 +0000
@@ -1,5 +1,17 @@
+0.6.2
+
+- Bugfixes for M6809 simulator.
+
+
+0.6.1
+
+- Bugfixes for MCS6502 simulator.
+
+
 0.6
 
+- New simulators: TLCS90, Padauk, M6809, PicoBlaze, MCS6502, MC6800
+
 - New commands: "memory info" (same as "info memory"), "get error"
   (same as "show error").
 
@@ -9,19 +21,17 @@
   (CTRL-x) but it is configurable for every uarts. Available functions
   are: start, stop, quit, reset, close.
 
-- Command line editing and history
-
-- More operators for expressions
+- Command line editing and history.
 
-- New simulators: TLCS90, Padauk
+- More operators for expressions.
 
-- VCD output
+- VCD output.
 
-- Read information from cdb and omf files
+- Read information from cdb and omf files.
 
-- Variables
+- Variables.
 
-- New option: "-e command" to specify startup command
+- New option: "-e command" to specify startup command.
 
 - Colors. New program option "-o colspec" to specify color values and
   -b to omit coloring. New options "color_XXX" to hold values.
@@ -29,15 +39,15 @@
 
 0.5
 
-- Bug fixes to run sdcc regression tests
+- Bug fixes to run sdcc regression tests.
 
-- Implementation of missing instruction ORL C,\bit of MCS51
+- Implementation of missing instruction ORL C,\bit of MCS51.
 
-- Fix of AVR instruction decoder
+- Fix of AVR instruction decoder.
 
-- Expressions
+- Expressions.
 
-- Memory simulation redesigned: address space, chip, address decoder
+- Memory simulation redesigned: address space, chip, address decoder.
 
 
 0.4
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/option.cc sdcc-4.2.0+dfsg/sim/ucsim/option.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/option.cc	2016-11-13 20:24:15.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/option.cc	2022-02-08 14:54:27.000000000 +0000
@@ -153,7 +153,7 @@
 }
 
 void
-cl_option::set_value(char *opt)
+cl_option::set_value(const char *opt)
 {
   //fprintf(stderr,"set_string_value (%s) to %p\"%s\"\n",opt,this,object_name(this));
   //fprintf(stderr,"old value=%p\"%s\"\n",value.sval,value.sval);
@@ -169,12 +169,6 @@
 }
 
 void
-cl_option::set_value(const char *opt)
-{
-  set_value(cchars(opt));
-}
-
-void
 cl_option::get_value(void **val)
 {
   if (val)
@@ -223,24 +217,20 @@
  * List of options
  */
 
-void *
-cl_options::key_of(void *item)
+const void *
+cl_options::key_of(const void *item) const
 {
-  return (void*)(((class cl_base *)item)->get_name());
+  return ((const class cl_base *)item)->get_name();
 }
 
 int
-cl_options::compare(void *key1, void *key2)
+cl_options::compare(const void *key1, const void *key2)
 {
-  //class cl_option *k1, *k2;
-  int i;
-  char *k1, *k2;
-
-  k1= /*(class cl_option *)*/(char *)key1;
-  k2= /*(class cl_option *)*/(char *)key2;
-  if ((i= strcmp(k1, k2)) != 0)
-    return(i);
-  return(i);
+  const char *k1, *k2;
+
+  k1= (const char *)key1;
+  k2= (const char *)key2;
+  return strcmp(k1, k2);
 }
 
 void
@@ -262,7 +252,7 @@
 {
   t_index idx;
 
-  if (search((void*)the_name, idx))
+  if (search(the_name, idx))
     return((class cl_option *)(at(idx)));
   return(0);
 }
@@ -273,71 +263,71 @@
   t_index idx;
   class cl_option *o;
 
-  if (!search((void*)the_name, idx))
+  if (!search(the_name, idx))
     return(0);
   if (idx > 0)
     {
       idx--;
       o= (class cl_option *)(at(idx));
-      while (compare((void*)the_name, key_of(o)) == 0 &&
+      while (compare(the_name, key_of(o)) == 0 &&
 	     idx > 0)
 	{
 	  idx--;
 	  o= (class cl_option *)(at(idx));
 	}
-      if (compare((void*)the_name, key_of(o)) != 0)
+      if (compare(the_name, key_of(o)) != 0)
 	idx++;
     }
   o= (class cl_option *)(at(idx));
-  while (compare((void*)the_name, key_of(o)) == 0 &&
+  while (compare(the_name, key_of(o)) == 0 &&
 	 o->get_creator() != creator &&
 	 idx < count)
     {
       idx++;
       o= (class cl_option *)(at(idx));
-      if (compare((void*)the_name, key_of(o)) == 0 &&
+      if (compare(the_name, key_of(o)) == 0 &&
 	  o->get_creator() == creator)
 	return(o);
     }
-  if (compare((void*)the_name, key_of(o)) == 0 &&
+  if (compare(the_name, key_of(o)) == 0 &&
       o->get_creator() == creator)
     return(o);
   return(0);
 }
 
 class cl_option *
-cl_options::get_option(const char *the_name, char *creator)
+cl_options::get_option(const char *the_name, const char *creator)
 {
   t_index idx;
   class cl_option *o;
 
-  if (!search((void*)the_name, idx))
+  if (!search(the_name, idx))
     return(0);
   if (idx > 0)
     {
       idx--;
       o= (class cl_option *)(at(idx));
-      while (compare((void*)the_name, key_of(o)) == 0 &&
+      while (compare(the_name, key_of(o)) == 0 &&
 	     idx > 0)
 	{
 	  idx--;
 	  o= (class cl_option *)(at(idx));
 	}
-      if (compare((void*)the_name, key_of(o)) != 0)
+      if (compare(the_name, key_of(o)) != 0)
 	idx++;
     }
   o= (class cl_option *)(at(idx));
-  while (compare((void*)the_name, key_of(o)) == 0 &&
+  while (compare(the_name, key_of(o)) == 0 &&
 	 strcmp(object_name(o->get_creator()), creator) != 0 &&
 	 idx < count)
     {
       idx++;
       o= (class cl_option *)(at(idx));
-      if (compare((void*)the_name, key_of(o)) == 0 &&
+      if (compare(the_name, key_of(o)) == 0 &&
 	  strcmp(object_name(o->get_creator()), creator) == 0)
 	return(o);
     }
-  if (compare((void*)the_name, key_of(o)) == 0 &&
+  if (compare(the_name, key_of(o)) == 0 &&
       strcmp(object_name(o->get_creator()), creator) == 0)
     return(o);
   return(0);
@@ -366,7 +356,7 @@
 }
 
 int
-cl_options::nuof_options(char *the_name, char *creator)
+cl_options::nuof_options(char *the_name, const char *creator)
 {
   int i, n= 0;
 
@@ -391,7 +381,7 @@
 }
 
 class cl_option *
-cl_options::set_value(const char *the_name, cl_base *creator, char *value)
+cl_options::set_value(const char *the_name, cl_base *creator, const char *value)
 {
   class cl_option *o= get_option(the_name, creator);
 
@@ -556,8 +546,6 @@
 {
   if (!option)
     {
-      fprintf(stderr, "Warning: \"%s\" is dereferencing a non-existent "
-	      "bool option: %s\n", object_name(owner), get_name());
       return(false);
     }
   else
@@ -573,10 +561,6 @@
 {
   if (!option)
     {
-      char *o= (char *)object_name(owner);
-      char *n= (char *)get_name();
-      fprintf(stderr, "Warning: \"%s\" is dereferencing a non-existent "
-	      "string option: %s\n", o, n?n:"?"); 
       return(0);
     }
   else
@@ -592,8 +576,6 @@
 {
   if (!option)
     {
-      fprintf(stderr, "Warning: \"%s\" is dereferencing a non-existent "
-	      "pointer option: %s\n", object_name(owner), get_name());
       return(0);
     }
   else
@@ -609,8 +591,6 @@
 {
   if (!option)
     {
-      fprintf(stderr, "Warning: \"%s\" is dereferencing a non-existent "
-	      "number option: %s\n", object_name(owner), get_name());
       return(0);
     }
   else
@@ -626,8 +606,6 @@
 {
   if (!option)
     {
-      fprintf(stderr, "Warning: \"%s\" is dereferencing a non-existent "
-	      "float option: %s\n", object_name(owner), get_name());
       return(0);
     }
   else
@@ -660,7 +638,7 @@
 }
 
 void
-cl_bool_option::set_value(char *s)
+cl_bool_option::set_value(const char *s)
 {
   char c;
 
@@ -779,7 +757,7 @@
 }
 
 void
-cl_cons_debug_opt::set_value(char *s)
+cl_cons_debug_opt::set_value(const char *s)
 {
   char c;
 
@@ -815,7 +793,7 @@
 }
 
 void
-cl_number_option::set_value(char *s)
+cl_number_option::set_value(const char *s)
 {
   if (s)
     value.ival= strtol(s, 0, 0);
@@ -841,7 +819,7 @@
 }
 
 void
-cl_float_option::set_value(char *s)
+cl_float_option::set_value(const char *s)
 {
   if (s)
     value.fval= strtod(s, 0);
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/optioncl.h sdcc-4.2.0+dfsg/sim/ucsim/optioncl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/optioncl.h	2017-07-01 16:16:20.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/optioncl.h	2020-09-17 09:34:03.000000000 +0000
@@ -80,7 +80,7 @@
   virtual void show(void) { hidden= false; }
 
   virtual void print(class cl_console_base *con) {}
-  virtual char *get_type_name(void) { return(cchars("non")); }
+  virtual const char *get_type_name(void) { return("none"); }
 
   virtual union option_value *get_value(void) { return(&value); }
   virtual void get_value(bool *val);
@@ -89,7 +89,6 @@
   virtual void get_value(long *val);
   virtual void get_value(double *val);
   virtual void set_value(bool opt);
-  virtual void set_value(char *opt);
   virtual void set_value(const char *opt);
   virtual void set_value(void *opt);
   virtual void set_value(long opt);
@@ -104,23 +103,23 @@
 class cl_options: public cl_sorted_list
 {
  public:
- cl_options(void): cl_sorted_list(2, 2, cchars("options"))
+ cl_options(void): cl_sorted_list(2, 2, "options")
     { Duplicates= true; }
-  virtual void *key_of(void *item);
-  virtual int compare(void *key1, void *key2);
+  virtual const void *key_of(const void *item) const;
+  virtual int compare(const void *key1, const void *key2);
   virtual void new_option(class cl_option *opt);
   virtual void del_option(class cl_option *opt);
   virtual class cl_option *get_option(const char *the_name);
   virtual class cl_option *get_option(const char *the_name, class cl_base *creator);
-  virtual class cl_option *get_option(const char *the_name, char *creator);
+  virtual class cl_option *get_option(const char *the_name, const char *creator);
   virtual class cl_option *get_option(int idx);
   virtual int nuof_options(char *the_name);
-  virtual int nuof_options(char *the_name, char *creator);
+  virtual int nuof_options(char *the_name, const char *creator);
 
   virtual class cl_option *set_value(const char *the_name, cl_base *creator,
 				     bool value);
   virtual class cl_option *set_value(const char *the_name, cl_base *creator,
-				     char *value);
+				     const char *value);
   virtual class cl_option *set_value(const char *the_name, cl_base *creator,
 				     void *value);
   virtual class cl_option *set_value(const char *the_name, cl_base *creator,
@@ -164,8 +163,8 @@
 public:
   cl_bool_option(class cl_base *the_creator, const char *aname, const char *Ihelp);
   virtual void print(class cl_console_base *con);
-  virtual char *get_type_name(void) { return(cchars("boolean")); }
-  virtual void set_value(char *s);
+  virtual const char *get_type_name(void) { return("boolean"); }
+  virtual void set_value(const char *s);
 };
 
 
@@ -175,7 +174,7 @@
   cl_string_option(class cl_base *the_creator, const char *aname, const char *Ihelp);
   virtual class cl_option &operator=(class cl_option &o);
   virtual void print(class cl_console_base *con);
-  virtual char *get_type_name(void) { return(cchars("string")); }
+  virtual const char *get_type_name(void) { return("string"); }
 };
 
 
@@ -185,7 +184,7 @@
   cl_pointer_option(class cl_base *the_creator, const char *aname, const char *Ihelp);
   virtual class cl_option &operator=(class cl_option &o);
   virtual void print(class cl_console_base *con);
-  virtual char *get_type_name(void) { return(cchars("pointer")); }
+  virtual const char *get_type_name(void) { return("pointer"); }
 };
 
 
@@ -194,8 +193,8 @@
 public:
   cl_number_option(class cl_base *the_creator, const char *aname, const char *Ihelp);
   virtual void print(class cl_console_base *con);
-  virtual char *get_type_name(void) { return(cchars("integer")); }
-  virtual void set_value(char *s);
+  virtual const char *get_type_name(void) { return("integer"); }
+  virtual void set_value(const char *s);
 };
 
 
@@ -204,8 +203,8 @@
 public:
   cl_float_option(class cl_base *the_creator, const char *aname, const char *Ihelp);
   virtual void print(class cl_console_base *con);
-  virtual char *get_type_name(void) { return(cchars("float")); }
-  virtual void set_value(char *s);
+  virtual const char *get_type_name(void) { return("float"); }
+  virtual void set_value(const char *s);
 };
 
 
@@ -221,7 +220,7 @@
   virtual void get_value(bool *val);
 
   virtual void set_value(bool);
-  virtual void set_value(char *s);
+  virtual void set_value(const char *s);
 };*/
 
 
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/p1516.src/(c).1 sdcc-4.2.0+dfsg/sim/ucsim/p1516.src/(c).1
--- sdcc-4.0.0+dfsg/sim/ucsim/p1516.src/(c).1	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/p1516.src/(c).1	2020-06-08 18:14:00.000000000 +0000
@@ -0,0 +1,25 @@
+/*
+ * Simulator of microcontrollers (@@F@@)
+ *
+ * Copyright (C) @@S@@,@@Y@@ Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/p1516.src/clean.mk sdcc-4.2.0+dfsg/sim/ucsim/p1516.src/clean.mk
--- sdcc-4.0.0+dfsg/sim/ucsim/p1516.src/clean.mk	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/p1516.src/clean.mk	2021-03-28 10:28:14.000000000 +0000
@@ -0,0 +1,32 @@
+# p1516.src/clean.mk
+
+# Deleting all files created by building the program
+# --------------------------------------------------
+clean:
+	rm -f *core *[%~] *.[oa] *.map
+	rm -f .[a-z]*~
+	rm -f sp1516$(EXEEXT) sp1516.exe
+	rm -f ucsim_p1516$(EXEEXT) ucsim_p1516.exe
+	$(MAKE) -C test -f clean.mk clean
+
+
+# Deleting all files created by configuring or building the program
+# -----------------------------------------------------------------
+distclean: clean
+	rm -f config.cache config.log config.status
+	rm -f Makefile *.dep
+	rm -f *.obj *.list *.lst *.hex
+	$(MAKE) -C test -f clean.mk distclean
+
+
+# Like clean but some files may still exist
+# -----------------------------------------
+mostlyclean: clean
+
+
+# Deleting everything that can reconstructed by this Makefile. It deletes
+# everything deleted by distclean plus files created by bison, etc.
+# -----------------------------------------------------------------------
+realclean: distclean
+
+# End of p1516.src/clean.mk
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/p1516.src/conf.mk sdcc-4.2.0+dfsg/sim/ucsim/p1516.src/conf.mk
--- sdcc-4.0.0+dfsg/sim/ucsim/p1516.src/conf.mk	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/p1516.src/conf.mk	2020-06-08 18:14:00.000000000 +0000
@@ -0,0 +1,11 @@
+# p1516.src/conf.mk
+#
+# Makefile targets to remake configuration
+#
+
+freshconf: Makefile
+
+Makefile: $(srcdir)/Makefile.in $(top_srcdir)/configure.ac
+	cd $(top_builddir) && $(SHELL) ./config.status
+
+# End of p1516.src/conf.mk
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/p1516.src/glob.cc sdcc-4.2.0+dfsg/sim/ucsim/p1516.src/glob.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/p1516.src/glob.cc	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/p1516.src/glob.cc	2022-01-13 16:56:10.000000000 +0000
@@ -0,0 +1,73 @@
+/*
+ * Simulator of microcontrollers (glob.cc)
+ *
+ * Copyright (C) 2020,20 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#include "glob.h"
+
+
+struct dis_entry disass_p1516[]=
+  {
+   { 0x08000000, 0x08000000, ' ', 1, "call  %A", false },
+
+   { 0xb4f00000, 0xfff00000, 'M', 1, "jz    %O", false },
+   { 0x94f00000, 0xfff00000, 'M', 1, "jnz   %O", false },
+   { 0x74f00000, 0xfff00000, 'M', 1, "jc    %O", false },
+   { 0x54f00000, 0xfff00000, 'M', 1, "jnc   %O", false },
+   { 0x04f00000, 0x1ff00000, 'M', 1, "jmp   %O", false },
+   { 0x04f00000, 0x0ff00000, ' ', 1, "jump  %O", false },
+
+   { 0x00000000, 0x0f000000, ' ', 1, "nop", false },
+   { 0x01000000, 0x0f000000, ' ', 1, "ld    %d:=mem[%R]", false },
+   { 0x02000000, 0x0f000000, ' ', 1, "st    mem[%R]:=%d", false },
+   { 0x03000000, 0x0f000000, ' ', 1, "mov   %d:=%a", false },
+   { 0x04000000, 0x0f000000, ' ', 1, "ldl0  %d:=%0", false },
+   { 0x05000000, 0x0f000000, ' ', 1, "ldl   %d:=%l", false },
+   { 0x06000000, 0x0f000000, ' ', 1, "ldh   %d:=%h", false },
+
+   { 0x07000000, 0x0f000f80, ' ', 1, "add   %d:=%a+%b", false },
+   { 0x07000080, 0x0f000f80, ' ', 1, "addc  %d:=%a+%b", false },
+   { 0x07000100, 0x0f000f80, ' ', 1, "sub   %d:=%a-%b", false },
+   { 0x07000180, 0x0f000f80, ' ', 1, "sbb   %d:=%a-%b", false },
+   { 0x07000200, 0x0f000f80, ' ', 1, "inc   %d:=%a+1", false },
+   { 0x07000280, 0x0f000f80, ' ', 1, "dec   %d:=%a-1", false },
+   { 0x07000300, 0x0f000f80, ' ', 1, "and   %d:=%a&%b", false },
+   { 0x07000380, 0x0f000f80, ' ', 1, "or    %d:=%a|%b", false },
+   { 0x07000400, 0x0f000f80, ' ', 1, "xor   %d:=%a^%b", false },
+   { 0x07000480, 0x0f000f80, ' ', 1, "shl   %d:=u(%a)<<1", false },
+   { 0x07000500, 0x0f000f80, ' ', 1, "shr   %d:=u(%a)>>1", false },
+   { 0x07000800, 0x0f000f80, ' ', 1, "sha   %d:=s(%a)>>1", false },
+   { 0x07000580, 0x0f000f80, ' ', 1, "rol   %d:=(C,%a)<<1", false },
+   { 0x07000600, 0x0f000f80, ' ', 1, "ror   %d:=(%a,C)>>1", false },
+   { 0x07000680, 0x0f000f80, ' ', 1, "mul   %d:=%a*%b", false },
+   { 0x07000700, 0x0f000f80, ' ', 1, "div   %d:=%a/%b", false },
+   { 0x07000780, 0x0f000f80, ' ', 1, "cmp   F:=%a-%b", false },
+   { 0x07000880, 0x0f000f80, ' ', 1, "setc", false },
+   { 0x07000900, 0x0f000f80, ' ', 1, "clrc", false },
+   
+   { 0, 0, 0, 0, 0, 0 }
+  };
+
+/* End of p1516.src/glob.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/p1516.src/glob.h sdcc-4.2.0+dfsg/sim/ucsim/p1516.src/glob.h
--- sdcc-4.0.0+dfsg/sim/ucsim/p1516.src/glob.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/p1516.src/glob.h	2020-09-17 06:45:33.000000000 +0000
@@ -0,0 +1,39 @@
+/*
+ * Simulator of microcontrollers (glob.h)
+ *
+ * Copyright (C) 2020,20 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef GLOB_HEADER
+#define GLOB_HEADER
+
+#include "stypes.h"
+
+
+extern struct dis_entry disass_p1516[];
+
+
+#endif
+
+/* End of p1516.src/glob.h */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/p1516.src/Makefile.in sdcc-4.2.0+dfsg/sim/ucsim/p1516.src/Makefile.in
--- sdcc-4.0.0+dfsg/sim/ucsim/p1516.src/Makefile.in	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/p1516.src/Makefile.in	2022-01-09 14:02:03.000000000 +0000
@@ -0,0 +1,182 @@
+#
+# uCsim p1516.src/Makefile
+#
+# (c) Drotos Daniel, Talker Bt. 1997
+#
+
+# tool name
+TN		= p1516
+
+STARTYEAR	= 1997
+
+SHELL		= /bin/sh
+CXX		= @CXX@
+CPP		= @CPP@
+CXXCPP		= @CXXCPP@
+RANLIB		= @RANLIB@
+INSTALL		= @INSTALL@
+STRIP		= @STRIP@
+MAKEDEP         = @MAKEDEP@
+
+top_builddir	= @top_builddir@
+top_srcdir	= @top_srcdir@
+
+transform	= @program_transform_name@
+
+DEFS            = $(subs -DHAVE_CONFIG_H,,@DEFS@)
+CPPFLAGS        = @CPPFLAGS@ -I$(srcdir) -I$(top_srcdir) -I$(top_builddir) \
+		  -I$(top_srcdir)/cmd.src -I$(top_srcdir)/sim.src \
+		  -I$(top_srcdir)/gui.src
+CFLAGS          = @WALL_FLAG@ @CFLAGS@
+CXXFLAGS        = @WALL_FLAG@ @CXXFLAGS@
+LDFLAGS         = @LDFLAGS@
+PICOPT		= @PICOPT@
+SHAREDLIB	= @SHAREDLIB@
+EXEEXT		= @EXEEXT@
+
+LIBS		= -L$(top_builddir) -lsim -lucsimutil -lguiucsim -lcmd -lsim @LIBS@
+DL		= @DL@
+dl_ok		= @dl_ok@
+
+prefix          = @prefix@
+exec_prefix     = @exec_prefix@
+bindir          = @bindir@
+libdir          = @libdir@
+datadir         = @datadir@
+datarootdir     = @datarootdir@
+includedir      = @includedir@
+mandir          = @mandir@
+man1dir         = $(mandir)/man1
+man2dir         = $(mandir)/man2
+infodir         = @infodir@
+srcdir          = @srcdir@
+VPATH           = @srcdir@
+
+OBJECTS_SHARED	= sim$(TN).o $(TN).o glob.o port.o
+
+OBJECTS_EXE	= s$(TN).o
+OBJECTS		= $(OBJECTS_SHARED) $(OBJECTS_EXE)
+
+# short/long exe and lib name
+SEN		= s$(TN)$(EXEEXT)
+LEN		= ucsim_$(TN)$(EXEEXT)
+SONAME		= libucsim_$(TN).so
+
+enable_dlso	= @enable_dlso@
+dlso_ok		= @dlso_ok@
+
+P1516ASM	=
+TEST_OBJ	= 
+
+
+# Compiling entire program or any subproject
+# ------------------------------------------
+all: checkconf otherlibs $(TN).src
+
+
+# Compiling and installing everything and runing test
+# ---------------------------------------------------
+install: all installdirs install_shared_lib
+	$(INSTALL) $(SEN) $(DESTDIR)$(bindir)/$(SEN)
+	$(STRIP) $(DESTDIR)$(bindir)/$(SEN)
+	$(INSTALL) $(LEN) $(DESTDIR)$(bindir)/$(LEN)
+	$(STRIP) $(DESTDIR)$(bindir)/$(LEN)
+
+
+# Deleting all the installed files
+# --------------------------------
+uninstall:
+	rm -f $(DESTDIR)$(bindir)/$(SEN)
+	rm -f $(DESTDIR)$(bindir)/$(LEN)
+	rm -f $(DESTDIR)$(libdir)/$(SONAME)
+
+
+# Performing self-test
+# --------------------
+check: $(TEST_OBJ)
+
+.PHONY:	test baseline
+test:
+	@$(MAKE) --no-print-directory -C test
+
+baseline:
+	@$(MAKE) --no-print-directory -C test baseline
+
+
+# Performing installation test
+# ----------------------------
+installcheck:
+
+
+# Creating installation directories
+# ---------------------------------
+installdirs:
+	test -d $(DESTDIR)$(bindir) || $(INSTALL) -d $(DESTDIR)$(bindir)
+
+
+# Creating dependencies
+# ---------------------
+dep: Makefile.dep
+
+Makefile.dep: $(srcdir)/*.cc $(srcdir)/*.h
+	$(MAKEDEP) $(CPPFLAGS) $(filter %.cc,$^) >Makefile.dep
+
+-include Makefile.dep
+include $(srcdir)/clean.mk
+
+# My rules
+# --------
+.SUFFIXES: .asm .hex
+
+$(TN).src: $(SEN) $(LEN) shared_lib
+
+$(SEN): $(OBJECTS) $(top_builddir)/libcmd.a $(top_builddir)/libguiucsim.a $(top_builddir)/libsim.a $(top_builddir)/libucsimutil.a
+	$(CXX) $(CXXFLAGS) $(LDFLAGS) $(OBJECTS) $(LIBS) -o $@
+
+$(LEN): $(SEN)
+	cp $< $@
+
+ifeq ($(dlso_ok),yes)
+shared_lib: $(top_builddir)/$(SONAME)
+install_shared_lib: shared_lib
+	test -d $(DESTDIR)$(libdir) || $(INSTALL) -d $(DESTDIR)$(libdir)
+	$(INSTALL) $(top_builddir)/$(SONAME) $(DESTDIR)$(libdir)/$(SONAME)
+else
+shared_lib:
+	@$(top_srcdir)/mkecho $(top_builddir) "No $(TN) shared lib made."
+	@$(top_srcdir)/mkecho $(top_builddir) "(SHAREDLIB="$(SHAREDLIB)",dl_ok="$(dl_ok)",enable_dlso="$(enable_dlso)")"
+install_shared_lib:
+endif
+
+$(top_builddir)/$(SONAME): $(OBJECTS_SHARED)
+	$(CXX) -shared $(LDFLAGS) $(OBJECTS_SHARED) -o $@
+
+otherlibs: $(top_builddir)/libcmd.a $(top_builddir)/libguiucsim.a $(top_builddir)/libsim.a $(top_builddir)/libucsimutil.a
+
+$(top_builddir)/libcmd.a:
+	$(MAKE) -C $(top_builddir)/cmd.src all
+
+$(top_builddir)/libguiucsim.a:
+	$(MAKE) -C $(top_builddir)/gui.src checkconf ucsim_lib
+
+$(top_builddir)/libsim.a:
+	$(MAKE) -C $(top_builddir)/sim.src all
+
+$(top_builddir)/libucsimutil.a:
+	$(MAKE) -C $(top_builddir) -f main.mk
+
+.cc.o:
+	$(CXX) $(CXXFLAGS) $(PICOPT) $(CPPFLAGS) $(TARGET_ARCH) -c $< -o $@
+
+.asm.hex:
+	$(P1516ASM) -l $< -o $@ -e $<.lst
+
+
+# Remaking configuration
+# ----------------------
+checkconf:
+	@if [ -f $(top_builddir)/devel ]; then\
+	  $(MAKE) -C $(top_builddir) -f conf.mk srcdir="$(srcdir)" top_builddir="$(top_builddir)" freshconf;\
+	fi
+
+# End of p1516.src/Makefile.in
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/p1516.src/p1516.cc sdcc-4.2.0+dfsg/sim/ucsim/p1516.src/p1516.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/p1516.src/p1516.cc	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/p1516.src/p1516.cc	2022-01-13 16:56:10.000000000 +0000
@@ -0,0 +1,557 @@
+/*
+ * Simulator of microcontrollers (p1516.cc)
+ *
+ * Copyright (C) 2020,20 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#include 
+
+#include "dregcl.h"
+
+#include "glob.h"
+#include "portcl.h"
+
+#include "p1516cl.h"
+
+
+cl_p1516::cl_p1516(class cl_sim *asim):
+  cl_uc(asim)
+{
+}
+
+int
+cl_p1516::init(void)
+{
+  int i;
+  cl_uc::init();
+  F= 0;
+  for (i=0; i<16; i++)
+    R[i]= 0;
+  return 0;
+}
+
+const char *
+cl_p1516::id_string(void)
+{
+  return "P1516";
+}
+
+void
+cl_p1516::reset(void)
+{
+  PC= R[15]= 0;
+}
+  
+void
+cl_p1516::set_PC(t_addr addr)
+{
+  PC= R[15]= addr;
+}
+
+void
+cl_p1516::mk_hw_elements(void)
+{
+  class cl_hw *h;
+  cl_uc::mk_hw_elements();
+
+  add_hw(h= new cl_dreg(this, 0, "dreg"));
+  h->init();
+  
+  add_hw(pa= new cl_porto(this, 0xf000, "pa"));
+  pa->init();
+  add_hw(pb= new cl_porto(this, 0xf001, "pb"));
+  pb->init();
+  add_hw(pc= new cl_porto(this, 0xf002, "pc"));
+  pc->init();
+  add_hw(pd= new cl_porto(this, 0xf003, "pd"));
+  pd->init();
+
+  add_hw(pi= new cl_porti(this, 0xe000, "pi"));
+  pi->init();
+  add_hw(pj= new cl_porti(this, 0xd000, "pj"));
+  pj->init();
+
+  class cl_port_ui *u= new cl_port_ui(this, 0, "dport");
+  u->init();
+  add_hw(u);
+  class cl_port_ui *uo= new cl_port_ui(this, 0, "oports");
+  uo->init();
+  add_hw(uo);
+  class cl_port_ui *ui= new cl_port_ui(this, 0, "iports");
+  ui->init();
+  add_hw(ui);
+
+  class cl_port_data d;
+  d.init();
+  d.cell_dir= NULL;
+  d.width= 32;
+  
+  d.set_name("PA");
+  d.cell_p = pa->dr;
+  d.cell_in= pa->dr;
+  d.keyset = NULL;
+  d.basx   = 15;
+  d.basy   = 4;
+  u->add_port(&d, 0);
+  uo->add_port(&d, 0);
+  
+  d.set_name("PB");
+  d.cell_p = pb->dr;
+  d.cell_in= pb->dr;
+  d.keyset = NULL;
+  d.basx   = 15;
+  d.basy   = 9;
+  u->add_port(&d, 1);
+  uo->add_port(&d, 1);
+
+  d.set_name("PC");
+  d.cell_p = pc->dr;
+  d.cell_in= pc->dr;
+  d.keyset = NULL;
+  d.basx   = 15;
+  d.basy   = 14;
+  u->add_port(&d, 2);
+  uo->add_port(&d, 2);
+
+  d.set_name("PD");
+  d.cell_p = pd->dr;
+  d.cell_in= pd->dr;
+  d.keyset = NULL;
+  d.basx   = 15;
+  d.basy   = 19;
+  u->add_port(&d, 3);
+  uo->add_port(&d, 3);
+
+  d.set_name("PI");
+  d.cell_p = pi->dr;
+  d.cell_in= pi->cfg_cell(port_pin);
+  d.keyset = chars("                qwertyui12345678");
+  d.basx   = 15;
+  d.basy   = 24;
+  u->add_port(&d, 4);
+  d.basy   = 4;
+  ui->add_port(&d, 0);
+
+  d.set_name("PJ");
+  d.cell_p = pj->dr;
+  d.cell_in= pj->cfg_cell(port_pin);
+  d.keyset = chars("                asdfghjkzxcvbnm,");
+  d.basx   = 15;
+  d.basy   = 29;
+  u->add_port(&d, 5);
+  d.basy   = 10;
+  ui->add_port(&d, 1);
+}
+
+void
+cl_p1516::make_memories(void)
+{
+  class cl_address_space *as;
+  int i;
+  
+  rom= as= new cl_address_space("rom"/*MEM_ROM_ID*/, 0, 0x10000, 32);
+  as->init();
+  address_spaces->add(as);
+
+  class cl_address_decoder *ad;
+  class cl_memory_chip *chip;
+
+  chip= new cl_chip32("rom_chip", 0x4000, 32);
+  chip->init();
+  memchips->add(chip);
+  ad= new cl_address_decoder(as= rom, chip, 0, 0x3fff, 0);
+  ad->init();
+  as->decoders->add(ad);
+  ad->activate(0);
+
+  regs= new cl_address_space("regs", 0, 16, 32);
+  regs->init();
+  for (i= 0; i<16; i++)
+    {
+      RC[i]= regs->get_cell(i);
+      RC[i]->decode((t_mem*)&R[i]);
+    }
+  address_spaces->add(regs);
+
+  chars n, d;
+  for (i=0; i<16; i++)
+    {
+      n.format("R%d", i);
+      d.format("CPU register %d", i);
+      vars->add(n, regs, i, d);
+    }
+}
+
+
+struct dis_entry *
+cl_p1516::dis_tbl(void)
+{
+  return(disass_p1516);
+}
+
+char *
+cl_p1516::disassc(t_addr addr, chars *comment)
+{
+  chars work= chars(), temp= chars();
+  const char *b;
+  t_mem code, data= 0;
+  int i;
+
+  code= rom->get(addr);
+  
+  i= 0;
+  while ((code & dis_tbl()[i].mask) != dis_tbl()[i].code &&
+	 dis_tbl()[i].mnemonic)
+    i++;
+  if (dis_tbl()[i].mnemonic == NULL)
+    {
+      return strdup("-- UNKNOWN/INVALID");
+    }
+  b= dis_tbl()[i].mnemonic;
+
+  data= (code&0xf0000000)>>28;
+  if (((data & 1) == 0) || (dis_tbl()[i].branch == 'M'))
+    work.append("   ");
+  else
+    {
+      switch (data>>2)
+	{
+	case 0: work.append("S"); break;
+	case 1: work.append("C"); break;
+	case 2: work.append("Z"); break;
+	case 3: work.append("O"); break;
+	}
+      if (data&2)
+	work.append("1 ");
+      else
+	work+= "0 ";
+    }
+
+  while (*b)
+    {
+      if (*b == '%')
+	{
+	  b++;
+	  switch (*(b++))
+	    {
+	    case 'd': // Rd
+	      data= (code & 0x00f00000)>>20;
+	      work.appendf("r%d", data);
+	      break;
+	    case 'a': // Ra
+	      data= (code & 0x000f0000)>>16;
+	      work.appendf("r%d", data);
+	      break;
+	    case 'R': // Ra in LD, ST
+	      data= (code & 0x000f0000)>>16;
+	      work.appendf("r%d", data);
+	      if (comment)
+		{
+		  chars n= "";
+		  addr_name(R[data], rom, &n);
+		  comment->format("; [%08x%s]= %08x",
+				  R[data],
+				  n.c_str(),
+				  rom->get(R[data]));
+		}
+	      break;
+	    case 'b': // Rb
+	      data= (code & 0x0000f000)>>12;
+	      work.appendf("r%d", data);
+	      break;
+	    case '0': // LDL0
+	      data= (code & 0x0000ffff);
+	      work.appendf("0x0000%04x", data);
+	      addr_name(data, rom, &work);
+	      break;
+	    case 'O': // LDL0 -> jump
+	      data= (code & 0x0000ffff);
+	      work.appendf("0x%04x", data);
+	      addr_name(data, rom, &work);
+	      break;
+	    case 'l': // LDL
+	      data= (code & 0x0000ffff);
+	      work.appendf("0x....%04x", data);
+	      break;
+	    case 'h': // LDH
+	      data= (code & 0x0000ffff);
+	      work.appendf("0x%04x....", data);
+	      break;
+	    case 'A': // CALL
+	      data= (code & 0x07ffffff);
+	      work.appendf("0x%x", data);
+	      addr_name(data, rom, &work);
+	      break;
+	    default:
+	      temp= "?";
+	      break;
+	    }
+	  if (comment && temp.nempty())
+	    comment->append(temp);
+	}
+      else
+	work.append(*(b++));
+    }
+
+  return strdup(work.c_str());
+}
+
+void
+cl_p1516::print_regs(class cl_console_base *con)
+{
+  int i;
+  con->dd_color("answer");
+  con->dd_printf("  F= 0x%x  ", F);
+  con->dd_printf("S=%c ", (F&S)?'1':'0');
+  con->dd_printf("C=%c ", (F&C)?'1':'0');
+  con->dd_printf("Z=%c ", (F&Z)?'1':'0');
+  con->dd_printf("O=%c ", (F&O)?'1':'0');
+  con->dd_printf("\n");
+  for (i= 0; i<16; i++)
+    {
+      if (i<10) con->dd_printf(" ");
+      con->dd_printf("R%d= 0x%08x ", i, R[i]);
+      if (i<10) con->dd_printf(" ");
+      con->dd_printf("[R%d]= 0x%08x", i, rom->get(R[i]));
+      if (i%2)
+	con->dd_printf("\n");
+      else
+	con->dd_printf(" ");
+    }
+  print_disass(PC, con);
+}
+
+
+t_mem
+cl_p1516::inst_ad(t_mem ra, t_mem rb, u32_t c)
+{
+  u64_t big;
+  u32_t rd;
+  
+  big= ra + rb + c;
+  F= 0;
+  if (big > 0xffffffff)
+    F|= C;
+  rd= big;
+  if (rd == 0)
+    F|= Z;
+  if (rd & 0x80000000)
+    F|= S;
+  big= (ra & 0x7fffffff) + (rb & 0x7fffffff) + c;
+  if ((big & 0x80000000) && !(F&C))
+    F|= O;
+  if (!(big & 0x80000000) && (F&C))
+    F|= O;
+  return rd;
+}
+
+int
+cl_p1516::inst_alu(t_mem code)
+{
+  u8_t d, a, b, Op;
+  u8_t c1, c2;
+  u64_t big;
+  
+  d= (code & 0x00f00000) >> 20;
+  a= (code & 0x000f0000) >> 16;
+  b= (code & 0x0000f000) >> 12;
+  Op=(code & 0x00000f80) >> 7;
+
+  switch (Op)
+    {
+    case 0: // ADD
+      RC[d]->W(inst_ad(RC[a]->R(), RC[b]->R(), 0));
+      break;
+    case 1: // ADC
+      RC[d]->W(inst_ad(RC[a]->R(), RC[b]->R(), (F&C)?1:0));
+      break;
+    case 2: // SUB
+      RC[d]->W(inst_ad(RC[a]->R(), ~(RC[b]->R()), 1));
+      break;
+    case 3: // SBB
+      RC[d]->W(inst_ad(RC[a]->R(), ~(RC[b]->R()), (F&C)?1:0));
+      break;
+
+    case 4: // INC
+      RC[d]->W(inst_ad(RC[a]->R(), 1, 0));
+      break;
+    case 5: // DEC
+      RC[d]->W(inst_ad(RC[a]->R(), ~(1), 1));
+      break;
+
+    case 6: // AND
+      RC[d]->W(RC[a]->R() & RC[b]->R());
+      SET_Z(R[d]);
+      break;
+    case 7: // OR
+      RC[d]->W(RC[a]->R() | RC[b]->R());
+      SET_Z(R[d]);
+      break;
+    case 8: // XOR
+      RC[d]->W(RC[a]->R() ^ RC[b]->R());
+      SET_Z(R[d]);
+      break;
+
+    case 9: // SHL
+      SET_C(R[a] & 0x80000000);
+      RC[d]->W(RC[a]->R() << 1);
+      SET_Z(R[d]);
+      break;
+    case 10: // SHR
+      SET_C(R[a] & 1);
+      RC[d]->W(RC[a]->R() >> 1);
+      SET_Z(R[d]);
+      break;
+    case 16: // SHA
+      SET_C(R[a] & 1);
+      RC[d]->W(((i32_t)(RC[a]->R())) >> 1);
+      SET_Z(R[d]);
+      break;
+    case 11: // ROL
+      c1= (F&C)?1:0;
+      c2= (R[a] & 0x80000000)?1:0;
+      RC[d]->W((RC[a]->R()<<1) + c1);
+      SET_C(c2);
+      SET_Z(R[d]);
+      break;
+    case 12: // ROR
+      c1= (F&C)?1:0;
+      c2= R[a] & 1;
+      RC[d]->W(RC[a]->R() >> 1);
+      if (c1)
+	R[d]|= 0x80000000;
+      SET_C(c2);
+      SET_Z(R[d]);
+      break;
+
+    case 13: // MUL
+      RC[d]->W(RC[a]->R() * RC[b]->R());
+      SET_Z(R[d]);
+      SET_S(R[d] & 0x80000000);
+      break;
+    case 19: // MUH
+      big= RC[a]->R() * RC[b]->R();
+      RC[d]->W(big >> 32);
+      SET_Z(R[d]);
+      SET_S(R[d] & 0x80000000);
+      break;
+    case 14: // DIV
+      break;
+
+    case 17: // SETC
+      SET_C(1);
+      break;
+    case 18: // CLRC
+      SET_C(0);
+      break;
+      
+    case 15: // CMP
+      inst_ad(RC[a]->R(), ~(RC[b]->R()), 1);
+      break;
+    }
+  
+  return resGO;
+}
+
+int
+cl_p1516::exec_inst(void)
+{
+  t_mem code;
+  u8_t inst;
+  u8_t cond;
+  bool fe;
+  
+  PC= R[15];
+  instPC= PC;
+  fe= fetch(&code);
+  tick(1);
+  R[15]= PC;
+  if (fe)
+    return(resBREAKPOINT);
+
+  cond= (code & 0xf0000000) >> 28;
+  if ((cond&1) == 1)
+    {
+      u8_t flag= 0, fv, v;
+      switch (cond>>2)
+	{
+	case 0: flag= F&S; break;
+	case 1: flag= F&C; break;
+	case 2: flag= F&Z; break;
+	case 3: flag= F&O; break;
+	}
+      fv= flag?1:0;
+      v= (cond&2)?1:0;
+      if (fv != v)
+	return resGO;
+    }
+  
+  inst= (code & 0x0f000000) >> 24;
+  if (code & 0x08000000)
+    {
+      // CALL
+      t_addr data= (code & 0x07ffffff);
+      RC[14]->W(R[15]);
+      RC[15]->W(PC= data);
+      return resGO;
+    }
+
+  u8_t d, a;
+  d= (code & 0x00f00000) >> 20;
+  a= (code & 0x000f0000) >> 16;
+  switch (inst)
+    {
+    case 0: // nop
+      break;
+    case 1: // LD Rd,Ra
+      R[d]= rom->read(R[a]);
+      vc.rd++;
+      break;
+    case 2: // ST Rd,Ra
+      rom->write(R[a], R[d]);
+      vc.wr++;
+      break;
+    case 3: // MOV Rd,Ra
+      R[d]= R[a];
+      break;
+    case 4: // LDL0 Rd,data
+      R[d]= code & 0x0000ffff;
+      break;
+    case 5: // LDL Rd,data
+      R[d]= (R[d] & 0xffff0000) | (code & 0x0000ffff);
+      break;
+    case 6: // LDH Rd,data
+      R[d]= (R[d] & 0x0000ffff) | (code << 16);
+      break;
+    case 7: // ALU
+      inst_alu(code);
+      break;
+    }
+  PC= R[15];
+  
+  return resGO;
+}
+
+
+/* End of p1516.src/p1516.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/p1516.src/p1516cl.h sdcc-4.2.0+dfsg/sim/ucsim/p1516.src/p1516cl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/p1516.src/p1516cl.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/p1516.src/p1516cl.h	2022-01-13 16:56:10.000000000 +0000
@@ -0,0 +1,84 @@
+/*
+ * Simulator of microcontrollers (p1516cl.h)
+ *
+ * Copyright (C) 2020,20 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef P1516CL_HEADER
+#define P1516CL_HEADER
+
+#include "uccl.h"
+#include "memcl.h"
+
+
+/*
+ * Base of P1516 processor
+ */
+
+enum flags
+  {
+   S= 1,
+   C= 2,
+   Z= 4,
+   O= 8
+  };
+
+class cl_p1516: public cl_uc
+{
+public:
+  u8_t F;
+  u32_t R[16];
+  cl_memory_cell *RC[16];
+  cl_address_space *regs;
+  class cl_porto *pa, *pb, *pc, *pd;
+  class cl_porti *pi, *pj;
+public:
+  class cl_address_space *rom;
+ public:
+  cl_p1516(class cl_sim *asim);
+  virtual int init(void);
+  virtual const char *id_string(void);
+  virtual void reset(void);
+  virtual void set_PC(t_addr addr);
+
+  virtual void mk_hw_elements(void);
+  virtual void make_memories(void);
+  virtual int clock_per_cycle(void) { return 4; }
+  
+  virtual struct dis_entry *dis_tbl(void);
+  virtual char *disassc(t_addr addr, chars *comment);
+  virtual void print_regs(class cl_console_base *con);
+
+  virtual t_mem inst_ad(t_mem ra, t_mem rb, u32_t c);
+  virtual int inst_alu(t_mem code);
+  virtual int exec_inst(void);
+};
+
+#define SET_C(v) ( F= (F&~C) | ((v)?C:0) )
+#define SET_Z(v) ( F= (F&~Z) | ((v==0)?Z:0) )
+#define SET_S(v) ( F= (F&~S) | ((v)?S:0) )
+
+#endif
+
+/* End of p1516.src/p1516.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/p1516.src/port.cc sdcc-4.2.0+dfsg/sim/ucsim/p1516.src/port.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/p1516.src/port.cc	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/p1516.src/port.cc	2021-04-01 17:52:48.000000000 +0000
@@ -0,0 +1,256 @@
+/*
+ * Simulator of microcontrollers (port.cc)
+ *
+ * Copyright (C) 2020,20 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#include "portcl.h"
+
+
+/* OUTPUT port */
+
+cl_porto::cl_porto(class cl_uc *auc, t_addr the_addr, const char *aname):
+  cl_hw(auc, HW_PORT, 0, aname)
+{
+  addr= the_addr;
+  set_name(aname);
+}
+
+int
+cl_porto::init(void)
+{
+  cl_hw::init();
+  dr= register_cell(uc->rom, addr);
+  dr->decode((t_mem*)&value);
+
+  uc->vars->add(get_name(), uc->rom, addr, 31, 0, chars("", "Data register of %s", get_name()));
+
+  cache= 0;
+  
+  return 0;
+}
+
+void
+cl_porto::reset(void)
+{
+  value= 0;
+}
+
+void
+cl_porto::write(class cl_memory_cell *cell, t_mem *val)
+{
+  if (cell == dr)
+    {
+      cell->set(*val);
+    }
+
+  conf(cell, val);
+}
+
+/*
+t_mem
+cl_porto::conf_op(cl_memory_cell *cell, t_addr addr, t_mem *val)
+{
+  switch ((enum port_cfg)addr)
+    {
+    case port_on: // turn this HW on/off
+      if (val)
+	{
+	  if (*val)
+	    on= true;
+	  else
+	    on= false;
+	}
+      else
+	{
+	  cell->set(on?1:0);
+	}
+      break;
+    case port_pin: // get/set PINS
+      break;
+    case port_value:
+      if (val)
+	*val= dr->get();//cell->set(*val);
+      break;
+    }
+  return cell->get();
+}
+*/
+
+void
+cl_porto::print(class cl_console_base *con)
+{
+  u32_t m;
+  t_mem d= value;//dr->get();
+  con->dd_printf("%s at %04x %08x\n", get_name(), addr, d);
+  for (m= 0x80000000; m; m>>= 1)
+    {
+      //if (d & m)
+	con->dd_printf("%c", (d & m)?'1':'0');
+	//else 	con->dd_printf("-");
+    }
+  con->dd_printf("\n");
+}
+
+void
+cl_porto::print_info(class cl_console_base *con)
+{
+  print(con);
+  //print_cfg_info(con);
+}
+
+void
+cl_porto::refresh_display(bool force)
+{
+  class cl_port_io *pio= (class cl_port_io *)io;
+  if (!io)
+    return;
+
+  t_mem d= value;
+  if (force || d != cache)
+    {
+      t_mem m;
+      int b, bv;
+      pio->tu_go(1,6);
+      pio->dd_color("answer");
+      pio->dd_printf("%s at %04x %08x\n", get_name(), addr, d);
+      cache= d;
+      pio->tu_go(1,8);
+      for (b=31; b>=0; b--)
+	{
+	  m= 1<dd_printf("%d", bv);
+	  if (b%8 == 0) pio->dd_printf(" ");
+	}
+      pio->tu_go(1,9);
+      for (b=31; b>=0; b--)
+	{
+	  m= 1<dd_cprintf("ui_bit1", "O");
+	    }
+	  else
+	    {
+	      pio->dd_cprintf("ui_bit0", ".");
+	    }
+	  if (b%8 == 0) pio->dd_printf(" ");
+	}
+    }
+  pio->dd_color("answer");
+  
+  draw_state_time(force);
+}
+
+void
+cl_porto::draw_display(void)
+{
+  class cl_port_io *pio= (class cl_port_io *)io;
+  if (!io)
+    return;
+  pio->tu_cls();
+
+  cl_hw::draw_display();
+
+  pio->tu_go(1,5);
+  pio->dd_printf("OPORT %s", get_name());
+
+  pio->tu_go(1,10);
+  int b;
+  for (b=31; b>=0; b--)
+    {
+      pio->dd_printf("%d", b/10);
+      if (b%8 == 0) pio->dd_printf(" ");
+    }
+  pio->tu_go(1,11);
+  for (b=31; b>=0; b--)
+    {
+      pio->dd_printf("%d", b%10);
+      if (b%8 == 0) pio->dd_printf(" ");
+    }
+  refresh_display(true);
+}
+
+
+/* INPUT port */
+
+cl_porti::cl_porti(class cl_uc *auc, t_addr the_addr, const char *aname):
+  cl_porto(auc, the_addr, aname)
+{
+  value= 0;
+}
+
+int
+cl_porti::init(void)
+{
+  cl_porto::init();
+
+  uc->vars->add(chars("", "%s_pins", get_name()), cfg, port_pin, 31, 0, cfg_help(port_pin));
+
+  return 0;
+}
+
+const char *
+cl_porti::cfg_help(t_addr addr)
+{
+  switch (addr)
+    {
+    case port_pin: return "Outside value of port pins (int, RW)";
+    }
+  return "Not used";
+}
+
+void
+cl_porti::write(class cl_memory_cell *cell, t_mem *val)
+{
+  if (cell == dr)
+    {
+      *val= value;
+    }
+
+  conf(cell, val);
+}
+
+
+t_mem
+cl_porti::conf_op(cl_memory_cell *cell, t_addr addr, t_mem *val)
+{
+  switch ((enum port_cfg)addr)
+    {
+    case port_pin: // get/set PINS
+      if (val)
+	value= *val;
+      else
+	return value;
+      break;
+    default:
+      return cl_porto::conf_op(cell, addr, val);
+    }
+  return cell->get();
+}
+
+/* End of p1516.src/port.cc */
+
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/p1516.src/portcl.h sdcc-4.2.0+dfsg/sim/ucsim/p1516.src/portcl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/p1516.src/portcl.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/p1516.src/portcl.h	2021-10-29 17:39:15.000000000 +0000
@@ -0,0 +1,78 @@
+/*
+ * Simulator of microcontrollers (portcl.h)
+ *
+ * Copyright (C) 2020,20 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef PORTCL_HEADER
+#define PORTCL_HEADER
+
+#include "port_hwcl.h"
+
+
+enum port_cfg
+  {
+   port_pin= 0 // RW
+  };
+
+
+class cl_porto: public cl_hw
+{
+ public:
+  class cl_memory_cell *dr;
+  t_addr addr;
+  u32_t value, cache;
+ public:
+  cl_porto(class cl_uc *auc, t_addr the_addr, const char *aname);
+  virtual int init(void);
+  virtual void reset(void);
+  virtual unsigned int cfg_size(void) { return 1; }
+  //virtual const char *cfg_help(t_addr addr);
+
+  virtual void write(class cl_memory_cell *cell, t_mem *val);
+  //virtual t_mem conf_op(cl_memory_cell *cell, t_addr addr, t_mem *val);
+
+  virtual void print(class cl_console_base *con);
+  virtual void print_info(class cl_console_base *con);
+  virtual void refresh_display(bool force);
+  virtual void draw_display(void);
+};
+
+class cl_porti: public cl_porto
+{
+public:
+  cl_porti(class cl_uc *auc, t_addr the_addr, const char *aname);
+public:
+  virtual int init(void);
+  virtual unsigned int cfg_size(void) { return 1; }
+  virtual const char *cfg_help(t_addr addr);
+
+  virtual void write(class cl_memory_cell *cell, t_mem *val);
+  virtual t_mem conf_op(cl_memory_cell *cell, t_addr addr, t_mem *val);
+};
+
+
+#endif
+
+/* End of p1516.src/portcl.h */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/p1516.src/simp1516.cc sdcc-4.2.0+dfsg/sim/ucsim/p1516.src/simp1516.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/p1516.src/simp1516.cc	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/p1516.src/simp1516.cc	2020-06-08 18:14:00.000000000 +0000
@@ -0,0 +1,44 @@
+/*
+ * Simulator of microcontrollers (simp1516.cc)
+ *
+ * Copyright (C) 2020,20 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+// local
+#include "simp1516cl.h"
+#include "p1516cl.h"
+
+
+cl_simp1516::cl_simp1516(class cl_app *the_app):
+  cl_sim(the_app)
+{}
+
+class cl_uc *
+cl_simp1516::mk_controller(void)
+{
+  return(new cl_p1516(this));
+}
+
+
+/* End of p1516.src/simp1516.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/p1516.src/simp1516cl.h sdcc-4.2.0+dfsg/sim/ucsim/p1516.src/simp1516cl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/p1516.src/simp1516cl.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/p1516.src/simp1516cl.h	2020-06-08 18:14:00.000000000 +0000
@@ -0,0 +1,45 @@
+/*
+ * Simulator of microcontrollers (simp1516cl.h)
+ *
+ * Copyright (C) 2020,20 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef SIMP1516CL_HEADER
+#define SIMP1516CL_HEADER
+
+#include "simcl.h"
+
+
+class cl_simp1516: public cl_sim
+{
+public:
+  cl_simp1516(class cl_app *the_app);
+
+  virtual class cl_uc *mk_controller(void);
+};
+
+
+#endif
+
+/* End of p1516.src/simp1516cl.h */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/p1516.src/sp1516.cc sdcc-4.2.0+dfsg/sim/ucsim/p1516.src/sp1516.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/p1516.src/sp1516.cc	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/p1516.src/sp1516.cc	2020-06-13 16:30:36.000000000 +0000
@@ -0,0 +1,54 @@
+/*
+ * Simulator of microcontrollers (sp1516.cc)
+ *
+ * Copyright (C) 2020,20 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+// prj
+#include "globals.h"
+
+// local
+#include "simp1516cl.h"
+
+
+int
+main(int argc, char *argv[])
+{
+  class cl_sim *sim;
+  
+  application= new cl_app();
+  application->set_name("sp1516");
+  application->init(argc, argv);
+  sim= new cl_simp1516(application);
+  if (sim->init())
+    sim->state|= SIM_QUIT;
+  application->set_simulator(sim);
+  //sim->main();
+  application->run();
+  application->done();
+  delete application;
+  return(0);
+}
+
+/* End of p1516.src/sp1516.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/p1516.src/test/clean.mk sdcc-4.2.0+dfsg/sim/ucsim/p1516.src/test/clean.mk
--- sdcc-4.0.0+dfsg/sim/ucsim/p1516.src/test/clean.mk	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/p1516.src/test/clean.mk	2021-04-01 17:52:48.000000000 +0000
@@ -0,0 +1,5 @@
+clean:
+
+distclean:
+	rm -f Makefile
+	find . -type d -name out -exec rm -rf {} \;
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/p1516.src/test/config/baseline/P1516 sdcc-4.2.0+dfsg/sim/ucsim/p1516.src/test/config/baseline/P1516
--- sdcc-4.0.0+dfsg/sim/ucsim/p1516.src/test/config/baseline/P1516	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/p1516.src/test/config/baseline/P1516	2022-02-08 21:21:05.000000000 +0000
@@ -0,0 +1,38 @@
+uCsim, Copyright (C)  Daniel Drotos.
+uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+This is free software, and you are welcome to redistribute it
+under certain conditions; type `show c' for details.
+Type of microcontroller: P1516
+Controller has 12 hardware element(s).
+   on simif[0]
+  off vcd[0]
+   on dreg[0]
+   on pa[0]
+   on pb[0]
+   on pc[0]
+   on pd[0]
+   on pi[0]
+   on pj[0]
+   on dport[0]
+   on oports[0]
+   on iports[0]
+  F= 0x0  S=0 C=0 Z=0 O=0 
+ R0= 0x00000000  [R0]= 0x5d888a08  R1= 0x00000000  [R1]= 0x5d888a08
+ R2= 0x00000000  [R2]= 0x5d888a08  R3= 0x00000000  [R3]= 0x5d888a08
+ R4= 0x00000000  [R4]= 0x5d888a08  R5= 0x00000000  [R5]= 0x5d888a08
+ R6= 0x00000000  [R6]= 0x5d888a08  R7= 0x00000000  [R7]= 0x5d888a08
+ R8= 0x00000000  [R8]= 0x5d888a08  R9= 0x00000000  [R9]= 0x5d888a08
+R10= 0x00000000 [R10]= 0x5d888a08 R11= 0x00000000 [R11]= 0x5d888a08
+R12= 0x00000000 [R12]= 0x5d888a08 R13= 0x00000000 [R13]= 0x5d888a08
+R14= 0x00000000 [R14]= 0x5d888a08 R15= 0x00000000 [R15]= 0x5d888a08
+0x0000  ? 5d888a08 C0 call  0x5888a08[0K
+Memory chips:
+  0x000000-0x0000ff      256 variable_storage (32,%08x,0x%02lx)
+  0x000000-0x003fff    16384 rom_chip (32,%08x,0x%04lx)
+Address spaces:
+  0x000000-0x0000ff      256 variables (32,%08x,0x%02lx)
+  0x000000-0x00ffff    65536 rom (32,%08x,0x%04lx)
+  0x000000-0x00000f       16 regs (32,%08x,0x%01lx)
+Address decoders:
+  variables 0x00 0xff -> variable_storage 0x00 activated
+  rom 0x0000 0x3fff -> rom_chip 0x0000 activated
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/p1516.src/test/config/Makefile sdcc-4.2.0+dfsg/sim/ucsim/p1516.src/test/config/Makefile
--- sdcc-4.0.0+dfsg/sim/ucsim/p1516.src/test/config/Makefile	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/p1516.src/test/config/Makefile	2021-03-21 12:01:19.000000000 +0000
@@ -0,0 +1,8 @@
+OUTPUTS = P1516
+
+
+$(OUTPUTS):
+	$(call run-sim, -e 'conf; info reg; info mem')
+
+
+include test-lib.mk
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/p1516.src/test/Makefile.in sdcc-4.2.0+dfsg/sim/ucsim/p1516.src/test/Makefile.in
--- sdcc-4.0.0+dfsg/sim/ucsim/p1516.src/test/Makefile.in	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/p1516.src/test/Makefile.in	2021-03-28 10:28:14.000000000 +0000
@@ -0,0 +1,9 @@
+# @configure_input@
+
+srcdir           = @abs_srcdir@
+
+abs_top_builddir = @abs_top_builddir@
+abs_top_srcdir   = @abs_top_srcdir@
+
+
+include $(abs_top_srcdir)/test-target.mk
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/packages_in.mk sdcc-4.2.0+dfsg/sim/ucsim/packages_in.mk
--- sdcc-4.0.0+dfsg/sim/ucsim/packages_in.mk	2019-03-14 16:34:34.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/packages_in.mk	2022-01-23 12:11:49.000000000 +0000
@@ -10,11 +10,19 @@
 enable_r3ka_port    = @enable_r3ka_port@
 enable_tlcs_port    = @enable_tlcs_port@
 enable_xa_port      = @enable_xa_port@
-enable_hc08_port    = @enable_hc08_port@
+enable_m68hc08_port = @enable_m68hc08_port@
 enable_s08_port     = @enable_s08_port@
 enable_stm8_port    = @enable_stm8_port@
 enable_st7_port     = @enable_st7_port@
-enable_pdk_port    =  @enable_pdk_port@
+enable_pdk_port     = @enable_pdk_port@
+enable_p1516_port   = @enable_p1516_port@
+enable_m6809_port   = @enable_m6809_port@
+enable_m6800_port   = @enable_m6800_port@
+enable_m68hc11_port = @enable_m68hc11_port@
+enable_m68hc12_port = @enable_m68hc12_port@
+enable_mos6502_port = @enable_mos6502_port@
+enable_rxk_port	    = @enable_rxk_port@
+enable_pblaze_port  = @enable_pblaze_port@
 
 ifeq ($(enable_mcs51_port),yes)
 S51		= s51.src
@@ -60,13 +68,13 @@
 TLCS		=
 endif
 
-ifeq ($(enable_hc08_port),yes)
-SHC08		= hc08.src
+ifeq ($(enable_m68hc08_port),yes)
+SM68HC08	= m68hc08.src
 else
 ifeq ($(enable_s08_port),yes)
-SS08		= hc08.src
+SS08		= m68hc08.src
 else
-SHC08		=
+SM68HC08	=
 endif
 endif
 
@@ -94,10 +102,65 @@
 PDKD   =
 endif
 
+ifeq ($(enable_p1516_port),yes)
+P1516      	= p1516.src
+else
+P1516      =
+endif
+
+ifeq ($(enable_m6809_port),yes)
+M6809      	= m6809.src
+else
+M6809      =
+endif
+
+ifeq ($(enable_m6800_port),yes)
+M6800      	= m6800.src
+else
+M6800      =
+endif
+
+ifeq ($(enable_m68hc11_port),yes)
+M68HC11      	= m68hc11.src
+else
+M68HC11    =
+endif
+
+ifeq ($(enable_m68hc12_port),yes)
+M68HC12      	= m68hc12.src
+else
+M68HC12    =
+endif
+
+ifeq ($(enable_mos6502_port),yes)
+MOS6502      	= mos6502.src
+else
+MOS6502      =
+endif
+
+ifeq ($(enable_rxk_port),yes)
+RXK      	= rxk.src
+else
+RXK      =
+endif
+
+ifeq ($(enable_pblaze_port),yes)
+PBLAZE      	= pblaze.src
+else
+PBLAZE	=
+endif
+
 PKGS		= $(S51) $(S390) \
 		  $(SAVR) $(SZ80) $(SZ180) $(SGBZ80) $(SR2K) $(SR3KA) \
 		  $(TLCS) \
-		  $(SHC08) $(SS08) $(XA) $(STM8) $(ST7) $(PDK) doc
-
-PKGS_ALL	= cmd.src sim.src gui.src s51.src avr.src z80.src tlcs.src xa.src \
-		  hc08.src stm8.src st7.src pdk.src doc
+		  $(SM68HC08) $(SS08) $(XA) $(STM8) $(ST7) $(PDK) $(P1516) \
+		  $(M6809) $(M6800) $(M68HC11) $(M68HC12) $(MOS6502) \
+		  $(RXK) $(PBLAZE) \
+		  doc gui.src
+
+PKGS_ALL	= cmd.src sim.src gui.src motorola.src \
+		  s51.src avr.src z80.src tlcs.src xa.src \
+		  m68hc08.src stm8.src st7.src pdk.src p1516.src \
+		  m6809.src m6800.src m68hc11.src m68hc12.src mos6502.src \
+		  rxk.src pblaze.src \
+		  doc
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/pblaze.src/apppblaze.cc sdcc-4.2.0+dfsg/sim/ucsim/pblaze.src/apppblaze.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/pblaze.src/apppblaze.cc	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/pblaze.src/apppblaze.cc	2022-01-27 21:35:29.000000000 +0000
@@ -0,0 +1,548 @@
+/*
+ * Copyright (C) 2012-2013 Jiří Šimek
+ * Copyright (C) 2013 Zbyněk Křivka 
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Library General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Library General Public License for more details.
+ *
+ * You should have received a copy of the GNU Library General Public License
+ * along with this library; see the file COPYING.LIB. If not, write to
+ * the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
+ * Boston, MA 02110-1301, USA.
+ */
+
+
+#include "ddconfig.h"
+
+#include 
+#include 
+#include 
+#ifdef HAVE_UNISTD_H
+# include 
+#endif
+#ifdef HAVE_GETOPT_H
+# include 
+#endif
+#ifdef SOCKET_AVAIL
+# include HEADER_SOCKET
+#endif
+#include 
+#include 
+#include "i_string.h"
+
+// prj
+#include "utils.h"
+#include "apppblazecl.h"
+#include "optioncl.h"
+#include "globals.h"
+
+// sim.src
+#include "simcl.h"
+
+// cmd.src
+#include "newcmdcl.h"
+#include "cmdutil.h"
+#include "cmd_confcl.h"
+#include "cmd_showcl.h"
+#include "cmd_getcl.h"
+#include "cmd_setcl.h"
+//#ifdef _WIN32
+//#include "newcmdwin32cl.h"
+//#else
+#include "newcmdposixcl.h"
+//#endif
+
+/* XXX */
+#define PORTVERSION "0.2.0"
+/*
+ * Interpretation of parameters
+ */
+
+static void
+print_help(const char *name)
+{
+  printf("%s: %s (uCsim %s)\n", name, PORTVERSION, VERSIONSTR);
+  printf("Usage: %s [-hHVvP] [-p prompt] [-t CPU] [-X freq[k|M]]\n"
+         "       [-c file] [-s file] [-S optionlist]"
+#ifdef SOCKET_AVAIL
+         " [-Z portnum] [-k portnum]"
+#endif
+         "\n"
+         "       [files...]\n", name);
+  printf
+    (
+     "Options:\n"
+     "  -t CPU       Type of CPU: kcpsm3 or kcpsm6\n"
+     "  -X freq[k|M] XTAL frequency\n"
+     "  -c file      Open command console on `file'\n"
+#ifdef SOCKET_AVAIL
+     "  -Z portnum   Use localhost:portnumber for command console\n"
+     "  -k portnum   Use localhost:portnum for serial I/O\n"
+#endif
+     "  -s file      Connect serial interface to `file'\n"
+     "  -S options   `options' is a comma separated list of options according to\n"
+     "               serial interface. Know options are:\n"
+     "                  in=file   serial input will be read from file named `file'\n"
+     "                  out=file  serial output will be written to `file'\n"
+     "  -p prompt    Specify string for prompt\n"
+     "  -P           Prompt is a null ('\\0') character\n"
+     "  -V           Verbose mode\n"
+     "  -v           Print out version number\n"
+     "  -H           Print out types of known CPUs\n"
+     "  -h           Print out this help\n"
+
+     "  -x           Input file format isn't Intel HEX file, but raw HEX file for PicoBlaze\n"
+     "  -i file      Read file with interrupts\n"
+     "  -I value     Address of interrupt vector\n"
+     "  -m value     Size of RAM (only for KCPSM6). Valid values are 64, 128 and 256.\n"
+     "  -M value     Size of ROM (only for KCPSM6). Valid values are 1024, 2048 and 4096.\n"
+     "  -n file      Loads file with inputs.\n"
+     "  -w value     Built-in hardware constant (only for KCPSM6).\n"
+     "  -o file      At the end of simulation saves PicoBlaze state and PicoBlaze outputs into files _state.xml and _outputs.xml.\n"
+     "\n"
+     "Authors: Jiri Simek and Zbynek Krivka (krivka@fit.vutbr.cz)\n"
+     "\n"
+     "Acknowledgement: This software tool has been elaborated in the\n"
+     "framework of the IT4Innovations Centre of Excellence project, \n"
+     "reg. no. CZ.1.05/1.1.00/02.0070 supported by Operational Programme\n"
+     "'Research and Development for Innovations' funded by Structural Funds\n" 
+     "of the European Union and state budget of the Czech Republic.\n"
+     );
+}
+
+enum {
+  SOPT_IN= 0,
+  SOPT_OUT
+};
+
+static const char *S_opts[]= {
+  /*[SOPT_IN]=*/ "in",
+  /*[SOPT_OUT]=*/ "out",
+  NULL
+};
+
+
+int
+cl_apppblaze::proc_arguments(int argc, char *argv[])
+{
+  int i, c;
+  char opts[100], *cp, *subopts, *value;
+  char *cpu_type= NULL;
+  bool s_done= false, k_done= false;
+  bool S_i_done= false, S_o_done= false;
+
+  strcpy(opts, "c:C:p:PX:vVt:s:S:hHk:xi:I:m:M:w:n:o:");
+#ifdef SOCKET_AVAIL
+  strcat(opts, "Z:r:");
+#endif
+
+  while((c= getopt(argc, argv, opts)) != -1)
+    switch (c)
+      {
+    /* ADDED by Jiri Simek */
+      case 'x':
+      {
+
+        class cl_option *o;
+        options->new_option(o= new cl_bool_option(this, "pblaze_hex","Read pblaze hex file"));
+        o->init();
+
+        if (!options->set_value("pblaze_hex", this, (bool)true))
+          fprintf(stderr, "Warning: Cannot set option -x");
+
+          o = options->get_option("pblaze_hex");
+          bool v;
+          o->get_value(&v);
+        break;
+      }
+      case 'i':
+      {
+        class cl_option *o;
+        options->new_option(o= new cl_string_option(this, "pblaze_interrupt_file","File with interrupts is specified"));
+        o->init();
+
+        if (!options->set_value("pblaze_interrupt_file", this, optarg))
+          fprintf(stderr, "Warning: No \"pblaze_interrupt_file\" option found to set "
+                  "parameter of -i as interrupt file\n");
+        break;
+      }
+      case 'I':
+      {
+        class cl_option *o;
+        options->new_option(o= new cl_number_option(this, "pblaze_interrupt_vector","Address of interrupt vector"));
+        o->init();
+
+        if (!options->set_value("pblaze_interrupt_vector", this, optarg))
+          fprintf(stderr, "Warning: No \"pblaze_interrupt_vector\" option found to set "
+                  "parameter of -I as interrupt vector\n");
+        break;
+      }
+      case 'm':
+      {
+        class cl_option *o;
+        options->new_option(o= new cl_number_option(this, "pblaze_ram_size","Set RAM size"));
+        o->init();
+
+        if (!options->set_value("pblaze_ram_size", this, strtol(optarg, NULL, 0)))
+          fprintf(stderr, "Warning: No \"pblaze_ram_size\" option found to set "
+                  "parameter of -m as RAM size\n");
+        break;
+      }
+      case 'n':
+      {
+        class cl_option *o;
+        options->new_option(o= new cl_string_option(this, "pblaze_input_file","File with inputs is specified"));
+        o->init();
+
+        if (!options->set_value("pblaze_input_file", this, optarg))
+          fprintf(stderr, "Warning: No \"pblaze_input_file\" option found to set "
+                  "parameter of -i as interrupt file\n");
+        break;
+      }
+      case 'M':
+      {
+        class cl_option *o;
+        options->new_option(o= new cl_number_option(this, "pblaze_rom_size","Set ROM size"));
+        o->init();
+
+        if (!options->set_value("pblaze_rom_size", this, strtol(optarg, NULL, 0)))
+          fprintf(stderr, "Warning: No \"pblaze_rom_size\" option found to set "
+                  "parameter of -M as ROM size\n");
+        break;
+      }
+      case 'w':
+      {
+        class cl_option *o;
+        options->new_option(o= new cl_number_option(this, "pblaze_hw_const","Builtin hardware constant"));
+        o->init();
+
+        if (!options->set_value("pblaze_hw_const", this, strtol(optarg, NULL, 0)))
+          fprintf(stderr, "Warning: No \"pblaze_hw_const\" option found to set "
+                  "parameter of -w as builtin hardware constant\n");
+        break;
+      }
+      case 'o':
+      {
+        class cl_option *o;
+        options->new_option(o= new cl_string_option(this, "pblaze_output_file","Part of file names with PicoBlaze state and outputs at the end of simulation"));
+        o->init();
+
+        if (!options->set_value("pblaze_output_file", this, optarg))
+          fprintf(stderr, "Warning: No \"pblaze_output_file\" option found to set "
+                  "parameter of -o as output files\n");
+        break;
+      }
+
+
+
+      // default parameters
+      case 'c':
+        if (!options->set_value("console_on", this, optarg))
+          fprintf(stderr, "Warning: No \"console_on\" option found "
+                  "to set by -c\n");
+        break;
+      case 'C':
+        if (!options->set_value("config_file", this, optarg))
+          fprintf(stderr, "Warning: No \"config_file\" option found to set "
+                  "parameter of -C as config file\n");
+        break;
+#ifdef SOCKET_AVAIL
+      case 'Z': case 'r':
+        {
+          // By Sandeep
+          // Modified by DD
+          class cl_option *o;
+          options->new_option(o= new cl_number_option(this, "port_number",
+                                                      "Listen on port (-Z)"));
+          o->init();
+          o->hide();
+          if (!options->set_value("port_number", this, strtol(optarg, NULL, 0)))
+            fprintf(stderr, "Warning: No \"port_number\" option found"
+                    " to set parameter of -Z as pot number to listen on\n");
+          break;
+        }
+#endif
+      case 'p': {
+        if (!options->set_value("prompt", this, optarg))
+          fprintf(stderr, "Warning: No \"prompt\" option found to set "
+                  "parameter of -p as default prompt\n");
+        break;
+      }
+      case 'P':
+        if (!options->set_value("null_prompt", this, bool(true)))
+          fprintf(stderr, "Warning: No \"null_prompt\" option found\n");
+        break;
+      case 'X':
+        {
+          double XTAL;
+          for (cp= optarg; *cp; *cp= toupper(*cp), cp++);
+          XTAL= strtod(optarg, &cp);
+          if (*cp == 'K')
+            XTAL*= 1e3;
+          if (*cp == 'M')
+            XTAL*= 1e6;
+          if (XTAL == 0)
+            {
+              fprintf(stderr, "Xtal frequency must be greater than 0\n");
+              exit(1);
+            }
+          if (!options->set_value("xtal", this, XTAL))
+            fprintf(stderr, "Warning: No \"xtal\" option found to set "
+                    "parameter of -X as XTAL frequency\n");
+          break;
+        }
+      case 'v':
+        printf("%s: %s\n", argv[0], VERSIONSTR);
+        exit(0);
+        break;
+      case 'V':
+        if (!options->set_value("debug", this, (bool)true))
+          fprintf(stderr, "Warning: No \"debug\" option found to set "
+                  "by -V parameter\n");
+        break;
+      case 't':
+        {
+          if (cpu_type)
+            free(cpu_type);
+          cpu_type= case_string(case_upper, optarg);
+          if (!options->set_value("cpu_type", this, /*optarg*/cpu_type))
+            fprintf(stderr, "Warning: No \"cpu_type\" option found to set "
+                    "parameter of -t as type of controller\n");
+          break;
+        }
+      case 's':
+      {
+#ifdef _WIN32
+        /* TODO: this code should be probably used for all platforms? */
+        FILE *Ser;
+        if (s_done)
+          {
+            fprintf(stderr, "-s option can not be used more than once.\n");
+            break;
+          }
+        s_done= true;
+        if ((Ser= fopen(optarg, "r+")) == NULL)
+          {
+            fprintf(stderr,
+                    "Can't open `%s': %s\n", optarg, strerror(errno));
+            return(4);
+          }
+        if (!options->set_value("serial_in_file", this, Ser))
+          fprintf(stderr, "Warning: No \"serial_in_file\" option found to set "
+                  "parameter of -s as serial input file\n");
+        if (!options->set_value("serial_out_file", this, Ser))
+          fprintf(stderr, "Warning: No \"serial_out_file\" option found "
+                  "to set parameter of -s as serial output file\n");
+#else
+        FILE *Ser_in, *Ser_out;
+        if (s_done)
+          {
+            fprintf(stderr, "-s option can not be used more than once.\n");
+            break;
+          }
+        s_done= true;
+        if ((Ser_in= fopen(optarg, "r")) == NULL)
+          {
+            fprintf(stderr,
+                    "Can't open `%s': %s\n", optarg, strerror(errno));
+            return(4);
+          }
+        if (!options->set_value("serial_in_file", this, Ser_in))
+          fprintf(stderr, "Warning: No \"serial_in_file\" option found to set "
+                  "parameter of -s as serial input file\n");
+        if ((Ser_out= fopen(optarg, "w")) == NULL)
+          {
+            fprintf(stderr,
+                    "Can't open `%s': %s\n", optarg, strerror(errno));
+            return(4);
+          }
+        if (!options->set_value("serial_out_file", this, Ser_out))
+          fprintf(stderr, "Warning: No \"serial_out_file\" option found "
+                  "to set parameter of -s as serial output file\n");
+#endif
+        break;
+      }
+#ifdef SOCKET_AVAIL
+      // socket serial I/O by Alexandre Frey 
+      case 'k':
+        {
+          FILE *Ser_in, *Ser_out;
+          UCSOCKET_T sock;
+          unsigned short serverport;
+          UCSOCKET_T client_sock;
+
+          if (k_done)
+            {
+              fprintf(stderr, "Serial input specified more than once.\n");
+            }
+          k_done= true;
+
+          serverport = atoi(optarg);
+          sock = make_server_socket(serverport);
+#ifdef _WIN32
+          if (SOCKET_ERROR == listen((SOCKET)sock, 1))
+            {
+              fprintf(stderr, "Listen on port %d: %d\n", serverport,
+                WSAGetLastError());
+              return (4);
+            }
+          fprintf(stderr, "Listening on port %d for a serial connection.\n",
+            serverport);
+          if (INVALID_SOCKET == (client_sock = accept(sock, NULL, NULL)))
+            {
+              fprintf(stderr, "accept: %d\n", WSAGetLastError());
+              return (4);
+            }
+          fprintf(stderr, "Serial connection established.\n");
+
+          int fh = _open_osfhandle((intptr_t)client_sock, 0);
+          if (-1 == fh)
+            {
+              perror("_open_osfhandle");
+              return (4);
+            }
+          if (NULL == (Ser_in = fdopen(fh, "r")))
+            {
+              fprintf(stderr, "Can't create input stream: %s\n", strerror(errno));
+              return (4);
+            }
+
+          fh = _open_osfhandle((intptr_t)client_sock, 0);
+          if (-1 == fh)
+            {
+              perror("_open_osfhandle");
+            }
+          if (NULL == (Ser_out = fdopen(fh, "w"))) {
+            fprintf(stderr, "Can't create output stream: %s\n", strerror(errno));
+            return (4);
+          }
+#else
+          if (listen(sock, 1) < 0) {
+            fprintf(stderr, "Listen on port %d: %s\n", serverport,
+                    strerror(errno));
+            return (4);
+          }
+          fprintf(stderr, "Listening on port %d for a serial connection.\n",
+                  serverport);
+          if ((client_sock= accept(sock, NULL, NULL)) < 0) {
+            fprintf(stderr, "accept: %s\n", strerror(errno));
+          }
+          fprintf(stderr, "Serial connection established.\n");
+
+          if ((Ser_in= fdopen(client_sock, "r")) == NULL) {
+            fprintf(stderr, "Can't create input stream: %s\n", strerror(errno));
+            return (4);
+          }
+          if ((Ser_out= fdopen(client_sock, "w")) == NULL) {
+            fprintf(stderr, "Can't create output stream: %s\n", strerror(errno));
+            return (4);
+          }
+#endif
+          if (!options->set_value("serial_in_file", this, (void*)Ser_in))
+            fprintf(stderr, "Warning: No \"serial_in_file\" option found to "
+                    "set parameter of -s as serial input file\n");
+          if (!options->set_value("serial_out_file", this, Ser_out))
+            fprintf(stderr, "Warning: No \"serial_out_file\" option found "
+                    "to set parameter of -s as serial output file\n");
+          break;
+        }
+#endif
+      case 'S':
+        subopts= optarg;
+        while (*subopts != '\0')
+          switch (get_sub_opt(&subopts, S_opts, &value))
+            {
+              FILE *Ser_in, *Ser_out;
+            case SOPT_IN:
+              if (value == NULL) {
+                fprintf(stderr, "No value for -S in\n");
+                exit(1);
+              }
+              if (S_i_done)
+                {
+                  fprintf(stderr, "Serial input specified more than once.\n");
+                  break;
+                }
+              S_i_done= true;
+              if ((Ser_in= fopen(value, "r")) == NULL)
+                {
+                  fprintf(stderr,
+                          "Can't open `%s': %s\n", value, strerror(errno));
+                  exit(4);
+                }
+              if (!options->set_value("serial_in_file", this, (void*)Ser_in))
+                fprintf(stderr, "Warning: No \"serial_in_file\" option found "
+                        "to set parameter of -s as serial input file\n");
+              break;
+            case SOPT_OUT:
+              if (value == NULL) {
+                fprintf(stderr, "No value for -S out\n");
+                exit(1);
+              }
+              if (S_o_done)
+                {
+                  fprintf(stderr, "Serial output specified more than once.\n");
+                  break;
+                }
+              if ((Ser_out= fopen(value, "w")) == NULL)
+                {
+                  fprintf(stderr,
+                          "Can't open `%s': %s\n", value, strerror(errno));
+                  exit(4);
+                }
+              if (!options->set_value("serial_out_file", this, Ser_out))
+                fprintf(stderr, "Warning: No \"serial_out_file\" option found "
+                        "to set parameter of -s as serial output file\n");
+              break;
+            default:
+              /* Unknown suboption. */
+              fprintf(stderr, "Unknown suboption `%s' for -S\n", value);
+              exit(1);
+              break;
+            }
+        break;
+      case 'h':
+        print_help("spblaze");
+        exit(0);
+        break;
+      case 'H':
+        {
+          if (!cpus)
+            {
+              fprintf(stderr, "CPU type is not selectable\n");
+              exit(0);
+            }
+          i= 0;
+          while (cpus[i].type_str != NULL)
+            {
+              printf("%s\n", cpus[i].type_str);
+              i++;
+            }
+          exit(0);
+          break;
+        }
+      case '?':
+        if (isprint(optopt))
+          fprintf(stderr, "Unknown option `-%c'.\n", optopt);
+        else
+          fprintf(stderr, "Unknown option character `\\x%x'.\n", optopt);
+        return(1);
+        break;
+      default:
+        exit(c);
+      }
+
+  for (i= optind; i < argc; i++)
+    in_files->add(argv[i]);
+
+  return(0);
+}
+
+
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/pblaze.src/apppblazecl.h sdcc-4.2.0+dfsg/sim/ucsim/pblaze.src/apppblazecl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/pblaze.src/apppblazecl.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/pblaze.src/apppblazecl.h	2021-05-11 11:08:48.000000000 +0000
@@ -0,0 +1,35 @@
+/*
+ * Copyright (C) 2012-2013 Jiří Šimek
+ * Copyright (C) 2013 Zbyněk Křivka 
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Library General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Library General Public License for more details.
+ *
+ * You should have received a copy of the GNU Library General Public License
+ * along with this library; see the file COPYING.LIB. If not, write to
+ * the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
+ * Boston, MA 02110-1301, USA.
+ */
+
+
+#ifndef APPPBLAZECL_HEADER
+#define APPPBLAZECL_HEADER
+
+// prj
+#include "appcl.h"
+
+class cl_apppblaze: public cl_app
+{
+public:
+  virtual int proc_arguments(int argc, char *argv[]);
+};
+
+
+#endif
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/pblaze.src/clean.mk sdcc-4.2.0+dfsg/sim/ucsim/pblaze.src/clean.mk
--- sdcc-4.0.0+dfsg/sim/ucsim/pblaze.src/clean.mk	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/pblaze.src/clean.mk	2021-09-19 19:38:05.000000000 +0000
@@ -0,0 +1,30 @@
+
+# Deleting all files created by building the program
+# --------------------------------------------------
+clean:
+	rm -f *core *[%~] *.[oa]
+	rm -f .[a-z]*~
+	rm -f spblaze spblaze.exe
+	rm -f ucsim_pblaze ucsim_pblaze.exe
+	rm -f ucsim_spblaze ucsim_spblaze.exe
+
+
+# Deleting all files created by configuring or building the program
+# -----------------------------------------------------------------
+distclean: clean
+	rm -f config.cache config.log config.status
+	rm -f Makefile *.dep
+	$(MAKE) -C test -f clean.mk distclean
+
+
+# Like clean but some files may still exist
+# -----------------------------------------
+mostlyclean: clean
+
+
+# Deleting everything that can reconstructed by this Makefile. It deletes
+# everything deleted by distclean plus files created by bison, etc.
+# -----------------------------------------------------------------------
+realclean: distclean
+
+# End of pblaze.src/clean.mk
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/pblaze.src/cmdpblaze.cc sdcc-4.2.0+dfsg/sim/ucsim/pblaze.src/cmdpblaze.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/pblaze.src/cmdpblaze.cc	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/pblaze.src/cmdpblaze.cc	2021-05-18 07:55:03.000000000 +0000
@@ -0,0 +1,137 @@
+/*
+ * Copyright (C) 2012-2013 Jiří Šimek
+ * Copyright (C) 2013 Zbyněk Křivka 
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Library General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Library General Public License for more details.
+ *
+ * You should have received a copy of the GNU Library General Public License
+ * along with this library; see the file COPYING.LIB. If not, write to
+ * the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
+ * Boston, MA 02110-1301, USA.
+ */
+
+
+// sim.src
+#include "simcl.h"
+
+// local
+#include "pblazecl.h"
+#include "cmdpblazecl.h"
+
+COMMAND_DO_WORK_UC(cl_pbstate_cmd)
+{
+  char *fname = NULL;
+  if (cmdline->param(0) != 0) {
+    fname = cmdline->param(0)->get_svalue();
+  }
+
+  ((cl_pblaze *) uc)->print_state(con, fname);
+  return(0);
+}
+
+CMDHELP(cl_pbstate_cmd,
+	"pbstate [\"file\"]",
+	"Prints PicoBlaze state to std output or specified file",
+	"long help of pbstate")
+
+COMMAND_DO_WORK_UC(cl_import_pbstate_cmd)
+{
+  char *fname = NULL;
+  if (cmdline->param(0) != 0) {
+    fname = cmdline->param(0)->get_svalue();
+    ((cl_pblaze *) uc)->load_state(con, fname);
+  }
+  else {
+    con->dd_printf("%s\n", short_help.c_str());
+  }
+
+  return(0);
+}
+
+CMDHELP(cl_import_pbstate_cmd,
+	"pbstate \"file\"",
+	"Loads Picoblaze state from xml file",
+	"long help of import pbstate")
+
+
+COMMAND_DO_WORK_UC(cl_import_interrupts_cmd)
+{
+  char *fname = NULL;
+  if (cmdline->param(0) != 0) {
+    fname = cmdline->param(0)->get_svalue();
+
+    cl_option * opt = uc->sim->app->options->get_option("pblaze_interrupt_file");
+    if (opt == NULL) {
+        uc->sim->app->options->new_option(opt = new cl_string_option(this, "pblaze_interrupt_file","File with interrupts is specified"));
+        opt->init();
+    }
+
+    opt->set_value(fname);
+
+    ((cl_pblaze *) uc)->read_interrupt_file();
+  }
+  else {
+    con->dd_printf("%s\n", short_help.c_str());
+  }
+
+  return(0);
+}
+
+CMDHELP(cl_import_interrupts_cmd,
+	"interrupts \"file\"",
+	"Loads interrupts from xml file",
+	"long help of import interrupts")
+
+
+COMMAND_DO_WORK_UC(cl_import_input_cmd)
+{
+  char *fname = NULL;
+  if (cmdline->param(0) != 0) {
+    fname = cmdline->param(0)->get_svalue();
+
+    cl_option * opt = uc->sim->app->options->get_option("pblaze_input_file");
+    if (opt == NULL) {
+        uc->sim->app->options->new_option(opt = new cl_string_option(this, "pblaze_input_file","File with inputs is specified"));
+        opt->init();
+    }
+    opt->set_value(fname);
+
+    ((cl_pblaze *) uc)->read_input_file();
+  }
+  else {
+    con->dd_printf("%s\n", short_help.c_str());
+  }
+
+  return(0);
+}
+
+CMDHELP(cl_import_input_cmd,
+	"input \"file\"",
+	"Loads input from xml file",
+	"long help of import input")
+
+
+COMMAND_DO_WORK_UC(cl_get_output_cmd)
+{
+  char *fname = NULL;
+  if (cmdline->param(0) != 0) {
+    fname = cmdline->param(0)->get_svalue();
+  }
+
+    ((cl_pblaze *) uc)->output_port->print_outputs(fname);
+
+  return(0);
+}
+
+CMDHELP(cl_get_output_cmd,
+	"output [\"file\"]",
+	"Prints realized outputs of PicoBlaze",
+	"long help of get output")
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/pblaze.src/cmdpblazecl.h sdcc-4.2.0+dfsg/sim/ucsim/pblaze.src/cmdpblazecl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/pblaze.src/cmdpblazecl.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/pblaze.src/cmdpblazecl.h	2021-05-11 11:08:48.000000000 +0000
@@ -0,0 +1,36 @@
+/*
+ * Copyright (C) 2012-2013 Jiří Šimek
+ * Copyright (C) 2013 Zbyněk Křivka 
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Library General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Library General Public License for more details.
+ *
+ * You should have received a copy of the GNU Library General Public License
+ * along with this library; see the file COPYING.LIB. If not, write to
+ * the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
+ * Boston, MA 02110-1301, USA.
+ */
+
+
+#ifndef CMD_PBLAZE_HEADER
+#define CMD_PBLAZE_HEADER
+
+#include "newcmdcl.h"
+
+
+// STATE
+COMMAND_ON(uc,cl_pbstate_cmd);
+COMMAND_ON(uc,cl_import_pbstate_cmd);
+COMMAND_ON(uc,cl_import_interrupts_cmd);
+COMMAND_ON(uc,cl_import_input_cmd);
+COMMAND_ON(uc,cl_get_output_cmd);
+
+
+#endif
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/pblaze.src/conf.mk sdcc-4.2.0+dfsg/sim/ucsim/pblaze.src/conf.mk
--- sdcc-4.0.0+dfsg/sim/ucsim/pblaze.src/conf.mk	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/pblaze.src/conf.mk	2021-05-11 11:08:48.000000000 +0000
@@ -0,0 +1,11 @@
+#
+# Makefile targets to remake configuration
+#
+
+freshconf: Makefile
+
+Makefile: $(srcdir)/Makefile.in $(top_srcdir)/configure.in
+	cd $(top_builddir) && $(SHELL) ./config.status
+
+# End of pblaze.src/conf.mk
+
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/pblaze.src/glob.cc sdcc-4.2.0+dfsg/sim/ucsim/pblaze.src/glob.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/pblaze.src/glob.cc	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/pblaze.src/glob.cc	2021-06-13 17:00:49.000000000 +0000
@@ -0,0 +1,295 @@
+/*
+ * Copyright (C) 2012-2013 Jiří Šimek
+ * Copyright (C) 2013 Zbyněk Křivka 
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Library General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Library General Public License for more details.
+ *
+ * You should have received a copy of the GNU Library General Public License
+ * along with this library; see the file COPYING.LIB. If not, write to
+ * the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
+ * Boston, MA 02110-1301, USA.
+ */
+
+#include 
+
+#include "stypes.h"
+#include "glob.h"
+#include "regspblaze.h"
+
+
+/*
+%a - 10b address (to ROM)
+%A - 12b address (to ROM); picoblaze6
+%k - immediate
+%K - immediate (at different position); picoblaze6
+%m - 6b address (to RAM)
+%M - 8b address (to RAM); picoblaze6
+%p - pc relative addressing
+%P - pc relative addressing; picoblaze6
+%r - register as first operand
+%s - register as second operand
+*/
+
+/*  uint  code, mask;  char  branch;  uchar length;  char  *mnemonic; */
+struct dis_entry disass_pblaze_x[]= {
+  { 0, 0, ' ', 1, "BAD_OPCODE" }};
+
+
+struct dis_entry_pblaze disass_pblaze3[]= {
+  { 0x18000, 0x3f000, ' ', 1, "ADD %r,%k", ADD,     REG_CONSTANT },     // 0 1 1 0 0 0 x x x x k k k k k k k k
+  { 0x19000, 0x3f00f, ' ', 1, "ADD %r,%s", ADD,     REG_REG },          // 0 1 1 0 0 1 x x x x y y y y 0 0 0 0
+  { 0x1a000, 0x3f000, ' ', 1, "ADDCY %r,%k", ADDCY,    REG_CONSTANT },     // 0 1 1 0 1 0 x x x x k k k k k k k k
+  { 0x1b000, 0x3f00f, ' ', 1, "ADDCY %r,%s", ADDCY,   REG_REG },          // 0 1 1 0 1 1 x x x x y y y y 0 0 0 0
+
+  { 0x0a000, 0x3f000, ' ', 1, "AND %r,%k", AND,     REG_CONSTANT },     // 0 0 1 0 1 0 x x x x k k k k k k k k
+  { 0x0b000, 0x3f00f, ' ', 1, "AND %r,%s", AND,     REG_REG },          // 0 0 1 0 1 1 x x x x y y y y 0 0 0 0
+
+  { 0x30000, 0x3fc00, ' ', 1, "CALL %a", CALL,          ADDRESS10 },         // 1 1 0 0 0 0 0 0 a a a a a a a a a a
+  { 0x31800, 0x3fc00, ' ', 1, "CALL C %a", CALL_C,        ADDRESS10 },        // 1 1 0 0 0 1 1 0 a a a a a a a a a a
+  { 0x31c00, 0x3fc00, ' ', 1, "CALL NC %a", CALL_NC,       ADDRESS10 },        // 1 1 0 0 0 1 1 1 a a a a a a a a a a
+  { 0x31400, 0x3fc00, ' ', 1, "CALL NZ %a", CALL_NZ,       ADDRESS10 },        // 1 1 0 0 0 1 0 1 a a a a a a a a a a
+  { 0x31000, 0x3fc00, ' ', 1, "CALL Z %a", CALL_Z,        ADDRESS10 },        // 1 1 0 0 0 1 0 0 a a a a a a a a a a
+
+  { 0x14000, 0x3f000, ' ', 1, "COMPARE %r,%k", COMPARE, REG_CONSTANT },        // 0 1 0 1 0 0 x x x x k k k k k k k k
+  { 0x15000, 0x3f00f, ' ', 1, "COMPARE %r,%s", COMPARE, REG_REG },        // 0 1 0 1 0 1 x x x x y y y y 0 0 0 0
+
+  { 0x3c000, 0x3ffff, ' ', 1, "DISABLE INTERRUPT", DISABLE_INTERRUPT, NO_OPERAND },        // 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+  { 0x3c001, 0x3ffff, ' ', 1, "ENABLE INTERRUPT", ENABLE_INTERRUPT, NO_OPERAND },        // 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1
+
+  { 0x06000, 0x3f0c0, ' ', 1, "FETCH %r, %m", FETCH,        REG_ADDRESS6 },        // 0 0 0 1 1 0 x x x x 0 0 s s s s s s
+  { 0x07000, 0x3f00f, ' ', 1, "FETCH %r,(%s)", FETCH,        REG_REG },        // 0 0 0 1 1 1 x x x x y y y y 0 0 0 0
+
+  { 0x05000, 0x3f00f, ' ', 1, "INPUT %r,(%s)", IINPUT,        REG_REG },        // 0 0 0 1 0 1 x x x x y y y y 0 0 0 0
+  { 0x04000, 0x3f000, ' ', 1, "INPUT %r,%p", IINPUT,        REG_PORT },        // 0 0 0 1 0 0 x x x x p p p p p p p p
+
+  { 0x34000, 0x3fc00, ' ', 1, "JUMP %a", JUMP,        ADDRESS10 },            // 1 1 0 1 0 0 0 0 a a a a a a a a a a
+  { 0x35800, 0x3fc00, ' ', 1, "JUMP C %a", JUMP_C,        ADDRESS10 },        // 1 1 0 1 0 1 1 0 a a a a a a a a a a
+  { 0x35c00, 0x3fc00, ' ', 1, "JUMP NC %a", JUMP_NC,        ADDRESS10 },        // 1 1 0 1 0 1 1 1 a a a a a a a a a a
+  { 0x35400, 0x3fc00, ' ', 1, "JUMP NZ %a", JUMP_NZ,        ADDRESS10 },        // 1 1 0 1 0 1 0 1 a a a a a a a a a a
+  { 0x35000, 0x3fc00, ' ', 1, "JUMP Z %a", JUMP_Z,        ADDRESS10 },        // 1 1 0 1 0 1 0 0 a a a a a a a a a a
+
+  { 0x00000, 0x3f000, ' ', 1, "LOAD %r,%k", LOAD,        REG_CONSTANT },        // 0 0 0 0 0 0 x x x x k k k k k k k k
+  { 0x01000, 0x3f00f, ' ', 1, "LOAD %r,%s", LOAD,        REG_REG },        // 0 0 0 0 0 1 x x x x y y y y 0 0 0 0
+
+  { 0x0c000, 0x3f000, ' ', 1, "OR %r,%k", OR,        REG_CONSTANT },        // 0 0 1 1 0 0 x x x x k k k k k k k k
+  { 0x0d000, 0x3f00f, ' ', 1, "OR %r,%s", OR,        REG_REG },        // 0 0 1 1 0 1 x x x x y y y y 0 0 0 0
+
+  { 0x2d000, 0x3f00f, ' ', 1, "OUTPUT %r,(%s)", OUTPUT,        REG_REG },        // 1 0 1 1 0 1 x x x x y y y y 0 0 0 0
+  { 0x2c000, 0x3f000, ' ', 1, "OUTPUT %r,%p", OUTPUT,        REG_PORT },        // 1 0 1 1 0 0 x x x x p p p p p p p p
+
+  { 0x2a000, 0x3ffff, ' ', 1, "RETURN", RETURN,        NO_OPERAND },        // 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
+  { 0x2b800, 0x3ffff, ' ', 1, "RETURN C", RETURN_C,        NO_OPERAND },        // 1 0 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0
+  { 0x2bc00, 0x3ffff, ' ', 1, "RETURN NC", RETURN_NC,        NO_OPERAND },        // 1 0 1 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0
+  { 0x2b400, 0x3ffff, ' ', 1, "RETURN NZ", RETURN_NZ,        NO_OPERAND },        // 1 0 1 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0
+  { 0x2b000, 0x3ffff, ' ', 1, "RETURN Z", RETURN_Z,        NO_OPERAND },        // 1 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0
+
+  { 0x38000, 0x3ffff, ' ', 1, "RETURNI DISABLE", RETURNI_DISABLE,        NO_OPERAND },        // 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+  { 0x38001, 0x3ffff, ' ', 1, "RETURNI ENABLE", RETURNI_ENABLE,        NO_OPERAND },        // 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
+
+  { 0x20002, 0x3f0ff, ' ', 1, "RL %r", RL,        REG },        // 1 0 0 0 0 0 x x x x 0 0 0 0 0 0 1 0
+  { 0x2000c, 0x3f0ff, ' ', 1, "RR %r", RR,        REG },        // 1 0 0 0 0 0 x x x x 0 0 0 0 1 1 0 0
+
+  { 0x20006, 0x3f0ff, ' ', 1, "SL0 %r", SL0,        REG },        // 1 0 0 0 0 0 x x x x 0 0 0 0 0 1 1 0
+  { 0x20007, 0x3f0ff, ' ', 1, "SL1 %r", SL1,        REG },        // 1 0 0 0 0 0 x x x x 0 0 0 0 0 1 1 1
+  { 0x20000, 0x3f0ff, ' ', 1, "SLA %r", SLA,        REG },        // 1 0 0 0 0 0 x x x x 0 0 0 0 0 0 0 0
+  { 0x20004, 0x3f0ff, ' ', 1, "SLX %r", SLX,        REG },        // 1 0 0 0 0 0 x x x x 0 0 0 0 0 1 0 0
+
+  { 0x2000e, 0x3f0ff, ' ', 1, "SR0 %r", SR0,        REG },        // 1 0 0 0 0 0 x x x x 0 0 0 0 1 1 1 0
+  { 0x2000f, 0x3f0ff, ' ', 1, "SR1 %r", SR1,        REG },        // 1 0 0 0 0 0 x x x x 0 0 0 0 1 1 1 1
+  { 0x20008, 0x3f0ff, ' ', 1, "SRA %r", SRA,        REG },        // 1 0 0 0 0 0 x x x x 0 0 0 0 1 0 0 0
+  { 0x2000a, 0x3f0ff, ' ', 1, "SRX %r", SRX,        REG },        // 1 0 0 0 0 0 x x x x 0 0 0 0 1 0 1 0
+
+  { 0x2e000, 0x3f0c0, ' ', 1, "STORE %r,%m", STORE,        REG_ADDRESS6 },        // 1 0 1 1 1 0 x x x x 0 0 s s s s s s
+  { 0x2f000, 0x3f00f, ' ', 1, "STORE %r,(%s)", STORE,        REG_REG },        // 1 0 1 1 1 1 x x x x y y y y 0 0 0 0
+  { 0x1c000, 0x3f000, ' ', 1, "SUB %r,%k", SUB,        REG_CONSTANT },        // 0 1 1 1 0 0 x x x x k k k k k k k k
+  { 0x1d000, 0x3f00f, ' ', 1, "SUB %r,%s", SUB,        REG_REG },        // 0 1 1 1 0 1 x x x x y y y y 0 0 0 0
+  { 0x1e000, 0x3f000, ' ', 1, "SUBCY %r,%k", SUBCY,        REG_CONSTANT },        // 0 1 1 1 1 0 x x x x k k k k k k k k
+  { 0x1f000, 0x3f00f, ' ', 1, "SUBCY %r,%s", SUBCY,        REG_REG },        // 0 1 1 1 1 1 x x x x y y y y 0 0 0 0
+  { 0x12000, 0x3f000, ' ', 1, "TEST %r,%k", TEST,        REG_CONSTANT },        // 0 1 0 0 1 0 x x x x k k k k k k k k
+  { 0x13000, 0x3f00f, ' ', 1, "TEST %r,%s", TEST,        REG_REG },        // 0 1 0 0 1 1 x x x x y y y y 0 0 0 0
+  { 0x0e000, 0x3f000, ' ', 1, "XOR %r,%k", XOR,        REG_CONSTANT },        // 0 0 1 1 1 0 x x x x k k k k k k k k
+  { 0x0f000, 0x3f00f, ' ', 1, "XOR %r,%s", XOR,        REG_REG },        // 0 0 1 1 1 1 x x x x y y y y 0 0 0 0
+
+  { 0, 0, ' ', 1, "BAD_OPCODE", BAD_OPCODE, NO_OPERAND }
+};
+
+struct dis_entry_pblaze disass_pblaze6[]= {
+  { 0x10000, 0x3f00f, ' ', 1, "ADD %r,%s", ADD,     REG_REG },
+  { 0x11000, 0x3f000, ' ', 1, "ADD %r,%k", ADD,     REG_CONSTANT },
+
+  { 0x12000, 0x3f00f, ' ', 1, "ADDCY %r,%s", ADDCY,   REG_REG },
+  { 0x13000, 0x3f000, ' ', 1, "ADDCY %r,%k", ADDCY,    REG_CONSTANT },
+
+  { 0x02000, 0x3f00f, ' ', 1, "AND %r,%s", AND,     REG_REG },
+  { 0x03000, 0x3f000, ' ', 1, "AND %r,%k", AND,     REG_CONSTANT },
+
+  { 0x20000, 0x3f000, ' ', 1, "CALL %A", CALL,          ADDRESS12 },
+  { 0x30000, 0x3f000, ' ', 1, "CALL C %A", CALL_Z,        ADDRESS12 },
+  { 0x34000, 0x3f000, ' ', 1, "CALL NZ %A", CALL_NZ,       ADDRESS12 },
+  { 0x38000, 0x3f000, ' ', 1, "CALL Z %A", CALL_C,        ADDRESS12 },
+  { 0x3c000, 0x3f000, ' ', 1, "CALL NC %A", CALL_NC,       ADDRESS12 },
+  { 0x24000, 0x3f00f, ' ', 1, "CALL@ (%r, %s)", CALL_AT,       REG_REG },
+
+  { 0x1c000, 0x3f00f, ' ', 1, "COMPARE %r,%s", COMPARE, REG_REG },
+  { 0x1d000, 0x3f000, ' ', 1, "COMPARE %r,%k", COMPARE, REG_CONSTANT },
+
+  { 0x1e000, 0x3f00f, ' ', 1, "COMPARECY %r,%s", COMPARECY, REG_REG },      //TEST
+  { 0x1f000, 0x3f000, ' ', 1, "COMPARECY %r,%k", COMPARECY, REG_CONSTANT }, //TEST
+
+  { 0x28000, 0x3ffff, ' ', 1, "DISABLE INTERRUPT", DISABLE_INTERRUPT, NO_OPERAND },
+  { 0x28001, 0x3ffff, ' ', 1, "ENABLE INTERRUPT", ENABLE_INTERRUPT, NO_OPERAND },
+
+  { 0x0a000, 0x3f00f, ' ', 1, "FETCH %r,(%s)", FETCH,        REG_REG },
+  { 0x0b000, 0x3f000, ' ', 1, "FETCH %r, %M", FETCH,        REG_ADDRESS8 },
+
+  { 0x14080, 0x3f0ff, ' ', 1, "HWBUILD %r", HWBUILD,        REG },
+
+  { 0x08000, 0x3f00f, ' ', 1, "INPUT %r,(%s)", IINPUT,        REG_REG },
+  { 0x09000, 0x3f000, ' ', 1, "INPUT %r,%p", IINPUT,        REG_PORT },
+
+  { 0x22000, 0x3f000, ' ', 1, "JUMP %A", JUMP,        ADDRESS12 },
+  { 0x32000, 0x3f000, ' ', 1, "JUMP Z %A", JUMP_Z,        ADDRESS12 },
+  { 0x36000, 0x3f000, ' ', 1, "JUMP NZ %A", JUMP_NZ,        ADDRESS12 },
+  { 0x3a000, 0x3f000, ' ', 1, "JUMP C %A", JUMP_C,        ADDRESS12 },
+  { 0x3e000, 0x3f000, ' ', 1, "JUMP NC %A", JUMP_NC,        ADDRESS12 },
+  { 0x26000, 0x3f00f, ' ', 1, "JUMP@ (%r, %s)", JUMP_AT,        REG_REG },
+
+  { 0x00000, 0x3f00f, ' ', 1, "LOAD %r,%s", LOAD,        REG_REG },
+  { 0x01000, 0x3f000, ' ', 1, "LOAD %r,%k", LOAD,        REG_CONSTANT },
+
+  { 0x04000, 0x3f00f, ' ', 1, "OR %r,%s", OR,        REG_REG },
+  { 0x05000, 0x3f000, ' ', 1, "OR %r,%k", OR,        REG_CONSTANT },
+
+  { 0x2c000, 0x3f00f, ' ', 1, "OUTPUT %r,(%s)", OUTPUT,        REG_REG },
+  { 0x2d000, 0x3f000, ' ', 1, "OUTPUT %r,%p", OUTPUT,        REG_PORT },
+  { 0x2b000, 0x3f000, ' ', 1, "OUTPUTK %K,%P", OUTPUTK,        CONSTANT_PORT },
+
+  { 0x37000, 0x3ffff, ' ', 1, "REGBANK A", REGBANK_A,        NO_OPERAND },
+  { 0x37001, 0x3ffff, ' ', 1, "REGBANK B", REGBANK_B,        NO_OPERAND },
+
+  { 0x25000, 0x3ffff, ' ', 1, "RETURN", RETURN,        NO_OPERAND },
+  { 0x31000, 0x3ffff, ' ', 1, "RETURN Z", RETURN_Z,        NO_OPERAND },
+  { 0x35000, 0x3ffff, ' ', 1, "RETURN NZ", RETURN_NZ,        NO_OPERAND },
+  { 0x39000, 0x3ffff, ' ', 1, "RETURN C", RETURN_C,        NO_OPERAND },
+  { 0x3d000, 0x3ffff, ' ', 1, "RETURN NC", RETURN_NC,        NO_OPERAND },
+  { 0x21000, 0x3f000, ' ', 1, "LOAD&RETURN %r,%k", LOAD_RETURN,        REG_CONSTANT },
+
+  { 0x29000, 0x3ffff, ' ', 1, "RETURNI DISABLE", RETURNI_DISABLE,        NO_OPERAND },
+  { 0x29001, 0x3ffff, ' ', 1, "RETURNI ENABLE", RETURNI_ENABLE,        NO_OPERAND },
+
+  { 0x14002, 0x3f0ff, ' ', 1, "RL %r", RL,        REG },
+  { 0x1400c, 0x3f0ff, ' ', 1, "RR %r", RR,        REG },
+
+  { 0x14006, 0x3f0ff, ' ', 1, "SL0 %r", SL0,        REG },
+  { 0x14007, 0x3f0ff, ' ', 1, "SL1 %r", SL1,        REG },
+  { 0x14004, 0x3f0ff, ' ', 1, "SLX %r", SLX,        REG },
+  { 0x14000, 0x3f0ff, ' ', 1, "SLA %r", SLA,        REG },
+
+  { 0x1400e, 0x3f0ff, ' ', 1, "SR0 %r", SR0,        REG },
+  { 0x1400f, 0x3f0ff, ' ', 1, "SR1 %r", SR1,        REG },
+  { 0x1400a, 0x3f0ff, ' ', 1, "SRX %r", SRX,        REG },
+  { 0x14008, 0x3f0ff, ' ', 1, "SRA %r", SRA,        REG },
+
+  { 0x16000, 0x3f00f, ' ', 1, "STAR %r,%s", STAR,        REG_REG },
+
+  { 0x2e000, 0x3f00f, ' ', 1, "STORE %r,(%s)", STORE,        REG_REG },
+  { 0x2f000, 0x3f000, ' ', 1, "STORE %r,%M", STORE,        REG_ADDRESS8 },
+
+  { 0x18000, 0x3f00f, ' ', 1, "SUB %r,%s", SUB,        REG_REG },
+  { 0x19000, 0x3f000, ' ', 1, "SUB %r,%k", SUB,        REG_CONSTANT },
+
+  { 0x1a000, 0x3f00f, ' ', 1, "SUBCY %r,%s", SUBCY,        REG_REG },
+  { 0x1b000, 0x3f000, ' ', 1, "SUBCY %r,%k", SUBCY,        REG_CONSTANT },
+
+  { 0x0c000, 0x3f00f, ' ', 1, "TEST %r,%s", TEST,        REG_REG },
+  { 0x0d000, 0x3f000, ' ', 1, "TEST %r,%k", TEST,        REG_CONSTANT },
+
+  { 0x0e000, 0x3f00f, ' ', 1, "TESTCY %r,%s", TESTCY,        REG_REG },     //TEST
+  { 0x0f000, 0x3f000, ' ', 1, "TESTCY %r,%k", TESTCY,        REG_CONSTANT },//TEST
+
+  { 0x06000, 0x3f00f, ' ', 1, "XOR %r,%s", XOR,        REG_REG },
+  { 0x07000, 0x3f000, ' ', 1, "XOR %r,%k", XOR,        REG_CONSTANT },
+
+  { 0, 0, ' ', 1, "BAD_OPCODE", BAD_OPCODE, NO_OPERAND }
+};
+
+
+
+/*
+ * Names of SFR cells
+ */
+
+struct name_entry sfr_tab[] =
+{
+  {CPU_ALL_PBLAZE, S0, "S0"},
+  {CPU_ALL_PBLAZE, S1, "S1"},
+  {CPU_ALL_PBLAZE, S2, "S2"},
+  {CPU_ALL_PBLAZE, S3, "S3"},
+  {CPU_ALL_PBLAZE, S4, "S4"},
+  {CPU_ALL_PBLAZE, S5, "S5"},
+  {CPU_ALL_PBLAZE, S6, "S6"},
+  {CPU_ALL_PBLAZE, S7, "S7"},
+  {CPU_ALL_PBLAZE, S8, "S8"},
+  {CPU_ALL_PBLAZE, S9, "S9"},
+  {CPU_ALL_PBLAZE, SA, "SA"},
+  {CPU_ALL_PBLAZE, SB, "SB"},
+  {CPU_ALL_PBLAZE, SC, "SC"},
+  {CPU_ALL_PBLAZE, SD, "SD"},
+  {CPU_ALL_PBLAZE, SE, "SE"},
+  {CPU_ALL_PBLAZE, SF, "SF"},
+
+  {CPU_PBLAZE_6, S0b, "S0b"},
+  {CPU_PBLAZE_6, S1b, "S1b"},
+  {CPU_PBLAZE_6, S2b, "S2b"},
+  {CPU_PBLAZE_6, S3b, "S3b"},
+  {CPU_PBLAZE_6, S4b, "S4b"},
+  {CPU_PBLAZE_6, S5b, "S5b"},
+  {CPU_PBLAZE_6, S6b, "S6b"},
+  {CPU_PBLAZE_6, S7b, "S7b"},
+  {CPU_PBLAZE_6, S8b, "S8b"},
+  {CPU_PBLAZE_6, S9b, "S9b"},
+  {CPU_PBLAZE_6, SAb, "SAb"},
+  {CPU_PBLAZE_6, SBb, "SBb"},
+  {CPU_PBLAZE_6, SCb, "SCb"},
+  {CPU_PBLAZE_6, SDb, "SDb"},
+  {CPU_PBLAZE_6, SEb, "SEb"},
+  {CPU_PBLAZE_6, SFb, "SFb"},
+
+  {CPU_ALL_PBLAZE, FLAGS, "FLAGS"},
+  {CPU_ALL_PBLAZE, SP, "SP"},
+
+  {0, 0, NULL}
+};
+
+// Second value indicates bitaddress.
+// Higher byte of bitaddress is address of FLAGS register (0x20)
+// Lower byte of bittaddress is position of bit in FLAGS register (see constants bmC, bmZ and bmI)
+struct name_entry bit_tab[] =
+{
+  {CPU_ALL_PBLAZE, 0x20, "C"},
+  {CPU_ALL_PBLAZE, 0x21, "Z"},
+  {CPU_ALL_PBLAZE, 0x22, "I"},
+
+  {0, 0, NULL}
+};
+
+
+struct cpu_entry cpus_pblaze[] =
+{
+  {"KCPSM3", CPU_PBLAZE_3, CPU_CMOS, "PicoBlaze 3", "fpga" },
+  {"KCPSM6", CPU_PBLAZE_6, CPU_CMOS, "PicoBlaze 6", "fpga" },
+  {"PB3"   , CPU_PBLAZE_3, CPU_CMOS, "PicoBlaze 3", "fpga" },
+  {"PB6"   , CPU_PBLAZE_6, CPU_CMOS, "PicoBlaze 6", "fpga" },
+  {"3"     , CPU_PBLAZE_3, CPU_CMOS, "PicoBlaze 3", "fpga" },
+  {"6"     , CPU_PBLAZE_6, CPU_CMOS, "PicoBlaze 6", "fpga" },
+
+  {NULL, CPU_NONE, 0, NULL, NULL}
+};
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/pblaze.src/glob.h sdcc-4.2.0+dfsg/sim/ucsim/pblaze.src/glob.h
--- sdcc-4.0.0+dfsg/sim/ucsim/pblaze.src/glob.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/pblaze.src/glob.h	2021-06-13 17:00:49.000000000 +0000
@@ -0,0 +1,116 @@
+/*
+ * Copyright (C) 2012-2013 Jiří Šimek
+ * Copyright (C) 2013 Zbyněk Křivka 
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Library General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Library General Public License for more details.
+ *
+ * You should have received a copy of the GNU Library General Public License
+ * along with this library; see the file COPYING.LIB. If not, write to
+ * the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
+ * Boston, MA 02110-1301, USA.
+ */
+
+#ifndef GLOB_HEADER
+#define GLOB_HEADER
+
+#include "stypes.h"
+
+extern struct cpu_entry cpus_pblaze[];
+
+extern struct dis_entry_pblaze disass_pblaze3[];
+extern struct dis_entry_pblaze disass_pblaze6[];
+extern struct dis_entry disass_pblaze_x[];
+
+extern struct name_entry sfr_tab[];
+extern struct name_entry bit_tab[];
+
+enum instructions_pblaze {
+    BAD_OPCODE = 0,
+    ADD,
+    ADDCY,
+    AND,
+    CALL,
+    CALL_C,
+    CALL_NC,
+    CALL_NZ,
+    CALL_Z,
+    CALL_AT,
+    COMPARE,
+    COMPARECY,
+    DISABLE_INTERRUPT,
+    ENABLE_INTERRUPT,
+    FETCH,
+    HWBUILD,
+    IINPUT,
+    JUMP,
+    JUMP_C,
+    JUMP_NC,
+    JUMP_NZ,
+    JUMP_Z,
+    JUMP_AT,
+    LOAD,
+    LOAD_RETURN,
+    OR,
+    OUTPUT,
+    OUTPUTK,
+    REGBANK_A,
+    REGBANK_B,
+    RETURN,
+    RETURN_C,
+    RETURN_NC,
+    RETURN_NZ,
+    RETURN_Z,
+    RETURNI_DISABLE,
+    RETURNI_ENABLE,
+    RL,
+    RR,
+    SL0,
+    SL1,
+    SLA,
+    SLX,
+    SR0,
+    SR1,
+    SRA,
+    SRX,
+    STAR,
+    STORE,
+    SUB,
+    SUBCY,
+    TEST,
+    TESTCY,
+    XOR
+};
+
+enum op_operands_pblaze {
+    NO_OPERAND = 0,
+    REG,
+    REG_REG,
+    REG_CONSTANT,
+    REG_PORT,
+    REG_ADDRESS6,
+    REG_ADDRESS8,
+    CONSTANT_PORT,
+    ADDRESS10,
+    ADDRESS12
+};
+
+struct dis_entry_pblaze
+{
+  uint  code;               /* bits in opcode used to match table entry(with mask) */
+  uint  mask;               /* mask used on .code to match up a common opcode */
+  char  branch;
+  uchar length;             /* total length of instruction */
+  const char *mnemonic;     /* type of opcode(ADD, ADDC...) */
+  uint instruction;          /* instruction (enum instructions_pblaze) */
+  uint operands;             /* clasification of operands (enum op_operands_pblaze) */
+};
+
+#endif
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/pblaze.src/inputport.cc sdcc-4.2.0+dfsg/sim/ucsim/pblaze.src/inputport.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/pblaze.src/inputport.cc	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/pblaze.src/inputport.cc	2021-05-11 11:08:48.000000000 +0000
@@ -0,0 +1,143 @@
+/*
+ * Copyright (C) 2012-2013 Jiří Šimek
+ * Copyright (C) 2013 Zbyněk Křivka 
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Library General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Library General Public License for more details.
+ *
+ * You should have received a copy of the GNU Library General Public License
+ * along with this library; see the file COPYING.LIB. If not, write to
+ * the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
+ * Boston, MA 02110-1301, USA.
+ */
+
+
+#include 
+#include 
+
+// local
+#include "pblazecl.h"
+#include "inputportcl.h"
+
+
+
+cl_input_port::cl_input_port(class cl_uc *auc) : cl_hw(auc, HW_PORT, 0, "input_port")
+{
+  value_set = false;
+}
+
+void
+cl_input_port::set_cmd(class cl_cmdline *cmdline, class cl_console_base *con)
+{
+  class cl_cmd_arg *params[1]= { cmdline->param(0) };
+
+  if (cmdline->syntax_match(uc, NUMBER))
+    {
+      value = params[0]->value.number;
+      value_set = true;
+    }
+  else
+    {
+      con->dd_printf("set hardware port[%d] value\n                   Set port value value\n", id);
+    }
+}
+
+void
+cl_input_port::print_info(class cl_console_base *con)
+{
+  con->dd_printf("Value on input port: %2X\n", value);
+}
+
+void
+cl_input_port::add_input(t_mem value, int port, long tick) {
+
+  if (inputs.find(port) == inputs.end()) {
+    inputs.insert(make_pair(port, input_tick_map()));
+  }
+  //input_tick_map ticks = inputs[port];
+
+  if (inputs[port].find(tick) == inputs[port].end()) {
+    inputs[port].insert(make_pair(tick, list() ));
+  }
+
+  inputs[port][tick].push_back(value);
+}
+
+t_mem
+cl_input_port::get_input(int port, long tick) {
+  if (value_set) {
+    value_set = false;
+    return value;
+  }
+
+  int p = port;
+  long t = tick;
+  // check for port:tick
+  if (!contains_input(p, t)) {
+    // not found, check for port:-1
+    if (!contains_input(p, -1)) {
+      // not found, check for -1:tick
+      p = -1;
+      if (!contains_input(p, t)) {
+        // not found, check for -1:-1
+        t = -1;
+        if (!contains_input(p, t)) {
+          // no input entry found
+          fprintf(stderr, "No input specified (port: %d, tick: %ld\n", port, tick);
+          return 0;
+        }
+      }
+    }
+    else {
+      t = -1;
+    }
+  }
+
+  t_mem value = inputs[p][t].front();
+  inputs[p][t].pop_front();
+
+  if (inputs[p][t].empty()) {
+    inputs[p].erase(t);
+  }
+  if (inputs[p].empty()) {
+    inputs.erase(p);
+  }
+
+// print inputs
+  for(input_port_map::iterator it = inputs.begin(); it != inputs.end(); it++) {
+    application->debug("port: %d\n", it->first);
+
+    for(input_tick_map::iterator it_inner = it->second.begin(); it_inner != it->second.end(); it_inner++) {
+      application->debug("\ttick: %ld\n", it_inner->first);
+
+      for(list::iterator it_list = it_inner->second.begin(); it_list != it_inner->second.end(); it_list++) {
+        application->debug("\t\t: %d\n", *it_list);
+      }
+    }
+  }
+
+  return value;
+}
+
+bool
+cl_input_port::contains_input(int port, long tick) {
+  // check for port
+  if (inputs.find(port) == inputs.end()) {
+    return false;
+  }
+
+  // check for tick
+  if (inputs[port].find(tick) == inputs[port].end()) {
+    return false;
+  }
+
+  return true;
+}
+
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/pblaze.src/inputportcl.h sdcc-4.2.0+dfsg/sim/ucsim/pblaze.src/inputportcl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/pblaze.src/inputportcl.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/pblaze.src/inputportcl.h	2021-05-14 21:19:53.000000000 +0000
@@ -0,0 +1,60 @@
+/*
+ * Copyright (C) 2012-2013 Jiří Šimek
+ * Copyright (C) 2013 Zbyněk Křivka 
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Library General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Library General Public License for more details.
+ *
+ * You should have received a copy of the GNU Library General Public License
+ * along with this library; see the file COPYING.LIB. If not, write to
+ * the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
+ * Boston, MA 02110-1301, USA.
+ */
+
+
+#ifndef INPUTPORTCL_HEADER
+#define INPUTPORTCL_HEADER
+
+#include 
+#include 
+
+#include "globals.h"
+#include "ddconfig.h"
+#include "stypes.h"
+#include "pobjcl.h"
+#include "uccl.h"
+
+using namespace std;
+
+typedef map > input_tick_map;
+typedef map input_port_map;
+
+class cl_input_port: public cl_hw
+{
+  public:
+    u8_t value;
+    bool value_set;
+    input_port_map inputs;
+
+    cl_input_port(class cl_uc *auc);
+    virtual void set_cmd(class cl_cmdline *cmdline, class cl_console_base *con);
+    virtual void print_info(class cl_console_base *con);
+
+    virtual void add_input(t_mem value, int port, long tick);
+    virtual t_mem get_input(int port, long tick);
+
+  private:
+    bool contains_input(int port, long tick);
+};
+
+
+#endif
+
+
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/pblaze.src/inst.cc sdcc-4.2.0+dfsg/sim/ucsim/pblaze.src/inst.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/pblaze.src/inst.cc	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/pblaze.src/inst.cc	2022-01-18 21:40:45.000000000 +0000
@@ -0,0 +1,1010 @@
+/*
+ * Copyright (C) 2012-2013 Jiří Šimek
+ * Copyright (C) 2013 Zbyněk Křivka 
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Library General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Library General Public License for more details.
+ *
+ * You should have received a copy of the GNU Library General Public License
+ * along with this library; see the file COPYING.LIB. If not, write to
+ * the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
+ * Boston, MA 02110-1301, USA.
+ */
+
+
+#include "stdio.h"
+#include 
+#include 
+
+#include "globals.h"
+#include "ddconfig.h"
+
+// sim
+#include "memcl.h"
+
+// local
+#include "glob.h"
+#include "pblazecl.h"
+#include "regspblaze.h"
+#include "pblazemac.h"
+
+cl_memory_cell *
+cl_pblaze::get_register(uint code, bool first_operand) {
+    unsigned char reg_code;
+
+    if (first_operand) {
+        reg_code = (code & 0x00f00) >> 8;
+    }
+    else {
+        reg_code = (code & 0x000f0) >> 4;
+    }
+
+    if (active_regbank == REGISTER_BANK_B) {
+      reg_code += 0x10;
+    }
+
+    return sfr->get_cell(reg_code);
+}
+
+uint
+cl_pblaze::get_constant(uint code) {
+    return code & 0x000ff;
+}
+
+uint
+cl_pblaze::get_address6(uint code) {
+    return code & 0x0003f;
+}
+
+uint
+cl_pblaze::get_address10(uint code) {
+    return code & 0x003ff;
+}
+
+uint
+cl_pblaze::get_address12(uint code) {
+    return code & 0x00fff;
+}
+
+/* ********** INSTRUCTIONS ********** */
+
+int
+cl_pblaze::inst_add(uint code, int operands)
+{
+  application->debug("ADD\n");
+
+  cl_memory_cell *r1 = get_register(code, true);
+  u8_t operand;
+  int result;
+
+  if (operands == REG_CONSTANT) {
+      operand = get_constant(code);
+  }
+  else if (operands == REG_REG) {
+      operand = get_register(code, false)->get();
+  }
+  else {
+    fprintf(stderr, "ADD: Unsuported operand type\n");
+    return (resERROR);
+  }
+
+  result = r1->get() + operand;
+
+  // carry flag
+  FLAGS_SET_C(result > 255);
+
+  result = result % 256;
+
+  //zero flag
+  FLAGS_SET_Z(result == 0);
+
+  r1->set(result);
+
+  return(resGO);
+}
+
+int
+cl_pblaze::inst_addcy(uint code, int operands)
+{
+  application->debug("ADDCY\n");
+
+  cl_memory_cell *r1 = get_register(code, true);
+  u8_t operand;
+  int result;
+
+  if (operands == REG_CONSTANT) {
+      operand = get_constant(code);
+  }
+  else if (operands == REG_REG) {
+      operand = get_register(code, false)->get();
+  }
+  else {
+    fprintf(stderr, "ADDCY: Unsuported operand type\n");
+    return (resERROR);
+  }
+
+  result = r1->get() + operand + (FLAGS_GET_C ? 1 : 0);
+
+  // carry flag
+  FLAGS_SET_C(result > 255);
+
+  result = result % 256;
+
+  //zero flag
+  if (type->type == CPU_PBLAZE_3) {
+    FLAGS_SET_Z(result == 0);
+  }
+  else if (type->type == CPU_PBLAZE_6) {
+    FLAGS_SET_Z(FLAGS_GET_Z && (result == 0));
+  }
+
+  r1->set(result);
+
+  return(resGO);
+}
+
+int
+cl_pblaze::inst_and(uint code, int operands)
+{
+  application->debug("AND\n");
+
+  cl_memory_cell *r1 = get_register(code, true);
+  u8_t operand;
+  int result;
+
+  if (operands == REG_CONSTANT) {
+      operand = get_constant(code);
+  }
+  else if (operands == REG_REG) {
+      operand = get_register(code, false)->get();
+  }
+  else {
+    fprintf(stderr, "ADDCY: Unsuported operand type\n");
+    return (resERROR);
+  }
+
+  result = r1->get() & operand;
+
+  // carry flag
+  FLAGS_SET_C(0);
+  //zero flag
+  FLAGS_SET_Z(result == 0);
+
+  r1->set(result);
+
+  return(resGO);
+}
+
+int
+cl_pblaze::inst_call(uint code, int inst, int operands)
+{
+  bool jump = false;
+
+  uint address;
+
+  if (operands == ADDRESS10)
+    address = get_address10(code);
+  else if (operands == ADDRESS12)
+    address = get_address12(code);
+  else if (operands == REG_REG) {
+    cl_memory_cell *r1 = get_register(code, true);
+    cl_memory_cell *r2 = get_register(code, false);
+    address = ((r1->get() & 0x0f) << 8) | r2->get();
+  }
+  else {
+    application->debug("CALL: Unsuported operand type\n");
+    return (resERROR);
+  }
+
+  switch (inst) {
+    case CALL:
+      application->debug("CALL\n");
+      jump = true;
+      break;
+
+    case CALL_AT:
+      application->debug("CALL@\n");
+      jump = true;
+      break;
+
+    case CALL_C:
+      application->debug("CALL C\n");
+      jump = FLAGS_GET_C;
+      break;
+
+    case CALL_NC:
+      application->debug("CALL NC\n");
+      jump = !FLAGS_GET_C;
+      break;
+
+    case CALL_Z:
+      application->debug("CALL Z\n");
+      jump = FLAGS_GET_Z;
+      break;
+
+    case CALL_NZ:
+      application->debug("CALL NZ\n");
+      jump = !FLAGS_GET_Z;
+      break;
+
+    default:
+      fprintf(stderr, "Unsuported CALL instruction\n");
+      return (resERROR);
+  }
+
+  if (jump) {
+    if (stack_push(PC-1)) {
+      fprintf(stderr, "Call stack overflow.\n");
+
+      if (type->type == CPU_PBLAZE_6)
+        reset();
+      //return (resERROR);
+    }
+    PC = address;
+  }
+
+  return(resGO);
+}
+
+int
+cl_pblaze::inst_compare(uint code, int operands)
+{
+  application->debug("COMPARE\n");
+
+  u8_t operand1 = get_register(code, true)->get();
+  u8_t operand2;
+
+  if (operands == REG_CONSTANT) {
+      operand2 = get_constant(code);
+  }
+  else if (operands == REG_REG) {
+      operand2 = get_register(code, false)->get();
+  }
+  else {
+    fprintf(stderr, "COMPARE: Unsuported operand type\n");
+    return (resERROR);
+  }
+
+  FLAGS_SET_C(operand2 > operand1);
+  FLAGS_SET_Z(operand1 == operand2);
+
+  return(resGO);
+}
+
+int
+cl_pblaze::inst_comparecy(uint code, int operands)
+{
+  application->debug("COMPARECY\n");
+
+  u8_t operand1 = get_register(code, true)->get();
+  u8_t operand2;
+
+  if (operands == REG_CONSTANT) {
+      operand2 = get_constant(code);
+  }
+  else if (operands == REG_REG) {
+      operand2 = get_register(code, false)->get();
+  }
+  else {
+    fprintf(stderr, "COMPARECY: Unsuported operand type\n");
+    return (resERROR);
+  }
+
+  FLAGS_SET_Z((operand1 == (operand2 + FLAGS_GET_C)) && FLAGS_GET_Z);
+  FLAGS_SET_C((operand2 + FLAGS_GET_C) > operand1);
+
+  return(resGO);
+}
+
+int
+cl_pblaze::inst_fetch(uint code, int operands)
+{
+  application->debug("FETCH\n");
+
+  cl_memory_cell *r1 = get_register(code, true);
+  u8_t addr;
+
+  if (operands == REG_ADDRESS6) {
+    addr = get_constant(code) & 0x3f; // only bits 5..0 are used for addressing
+  }
+  else if (operands == REG_ADDRESS8) {
+    addr = get_constant(code);
+  }
+  else if (operands == REG_REG) {
+    addr = get_register(code, false)->get();
+  }
+  else {
+    fprintf(stderr, "FETCH: Unsuported operand type\n");
+    return (resERROR);
+  }
+
+  r1->set(ram->read(addr));
+
+  return (resGO);
+}
+
+int
+cl_pblaze::inst_hwbuild(uint code, int operands)
+{
+  application->debug("HWBUILD\n");
+
+
+  if (operands == REG) {
+    cl_memory_cell *r1 = get_register(code, true);
+    r1->set(hw_constant);
+  }
+  else {
+    fprintf(stderr, "HWBUILD: Unsuported operand type\n");
+    return (resERROR);
+  }
+
+  FLAGS_SET_C(1);
+  FLAGS_SET_Z(hw_constant == 0);
+
+  return (resGO);
+}
+
+int
+cl_pblaze::inst_input(uint code, int operands)
+{
+  application->debug("INPUT\n");
+
+  t_mem port;
+
+  if (operands == REG_REG) {
+    cl_memory_cell *r2 = get_register(code, false);
+    port = r2->get();
+  }
+  else if (operands == REG_PORT) {
+    port = get_constant(code);
+  }
+  else {
+    fprintf(stderr, "INPUT: Unsuported operand type\n");
+    return (resERROR);
+  }
+
+  cl_memory_cell *r1 = get_register(code, true);
+  r1->set(input_port->get_input(port, ticks->get_ticks() / clock_per_cycle()));
+
+  input_port->value = r1->get();
+  port_id->value = port;
+
+  return (resGO);
+}
+
+int
+cl_pblaze::inst_interrupt(bool value)
+{
+  if (value)
+    application->debug("ENABLE INTERRUPT\n");
+  else
+    application->debug("DISABLE INTERRUPT\n");
+
+  FLAGS_SET_I(value);
+
+  return (resGO);
+}
+
+int
+cl_pblaze::inst_jump(uint code, int inst, int operands)
+{
+  bool jump = false;
+
+  uint address;
+  if (operands == ADDRESS10)
+    address = get_address10(code);
+  else if (operands == ADDRESS12)
+    address = get_address12(code);
+  else if (operands == REG_REG) {
+    cl_memory_cell *r1 = get_register(code, true);
+    cl_memory_cell *r2 = get_register(code, false);
+    address = ((r1->get() & 0x0f) << 8) | r2->get();
+  }
+  else {
+    fprintf(stderr, "JUMP: Unsuported operand type\n");
+    return (resERROR);
+  }
+
+  switch (inst) {
+    case JUMP:
+      application->debug("JUMP\n");
+      jump = true;
+      break;
+
+    case JUMP_AT:
+      application->debug("JUMP@\n");
+      jump = true;
+      break;
+
+    case JUMP_C:
+      application->debug("JUMP C\n");
+      jump = FLAGS_GET_C;
+      break;
+
+    case JUMP_NC:
+      application->debug("JUMP NC\n");
+      jump = !FLAGS_GET_C;
+      break;
+
+    case JUMP_Z:
+      application->debug("JUMP Z\n");
+      jump = FLAGS_GET_Z;
+      break;
+
+    case JUMP_NZ:
+      application->debug("JUMP NZ\n");
+      jump = !FLAGS_GET_Z;
+      break;
+
+    default:
+      fprintf(stderr, "Unsuported JUMP instruction\n");
+      return (resERROR);
+  }
+
+  if (jump) {
+    PC = address;
+  }
+
+  return (resGO);
+}
+
+int
+cl_pblaze::inst_load(uint code, int operands)
+{
+  application->debug("LOAD\n");
+
+  cl_memory_cell *r1 = get_register(code, true);
+
+  if (operands == REG_CONSTANT) {
+      r1->set(get_constant(code));
+  }
+  else if (operands == REG_REG) {
+      r1->set(get_register(code, false)->get());
+  }
+  else {
+    fprintf(stderr, "LOAD: Unsuported operand type\n");
+    return (resERROR);
+  }
+
+  return (resGO);
+}
+
+int
+cl_pblaze::inst_load_return(uint code, int operands)
+{
+  application->debug("LOAD&RETURN\n");
+
+  if (operands == REG_CONSTANT) {
+    cl_memory_cell *r1 = get_register(code, true);
+    r1->set(get_constant(code));
+
+    u32_t addr;
+    if (stack_pop(&addr)) {
+      fprintf(stderr, "Call stack underflow.\n");
+
+      if (type->type == CPU_PBLAZE_6)
+        reset();
+
+      //return (resERROR);
+    }
+    PC = addr+1;
+  }
+  else {
+    fprintf(stderr, "LOAD&RETURN: Unsuported operand type\n");
+    return (resERROR);
+  }
+
+  return (resGO);
+}
+
+int
+cl_pblaze::inst_or(uint code, int operands)
+{
+  application->debug("OR\n");
+
+  cl_memory_cell *r1 = get_register(code, true);
+  u8_t operand;
+  u8_t result;
+
+  if (operands == REG_CONSTANT) {
+    operand = get_constant(code);
+  }
+  else if (operands == REG_REG) {
+    operand = get_register(code, false)->get();
+  }
+  else {
+    fprintf(stderr, "OR: Unsuported operand type\n");
+    return (resERROR);
+  }
+
+  result = r1->get() | operand;
+
+  FLAGS_SET_C(0);
+  FLAGS_SET_Z(result == 0);
+
+  r1->set(result);
+
+  return (resGO);
+}
+
+int
+cl_pblaze::inst_output(uint code, int operands)
+{
+  application->debug("OUTPUT\n");
+
+  cl_memory_cell *r1 = get_register(code, true);
+  int port;
+  if (operands == REG_REG) {
+    cl_memory_cell *r2 = get_register(code, false);
+    port = r2->get();
+  }
+  else if (operands == REG_PORT) {
+    port = get_constant(code);
+  }
+  else {
+    fprintf(stderr, "OUTPUT: Unsuported operand type\n");
+    return (resERROR);
+  }
+  t_mem value = r1->get();
+  application->dd_printf("Output on port %d: %2x %3d %c\n", port, value, value, isprint(value) ? value : '.');
+  output_port->add_output(port, ticks->get_ticks() / clock_per_cycle(), value);
+
+  output_port->value = value;
+  port_id->value = port;
+
+  return (resGO);
+}
+
+int
+cl_pblaze::inst_outputk(uint code, int operands)
+{
+  application->debug("OUTPUTK\n");
+
+  u8_t constant;
+  u8_t port;
+
+  if (operands == CONSTANT_PORT) {
+    constant = (code & 0x00ff0) >> 8;
+    port = code & 0x0000f;
+  }
+  else {
+    fprintf(stderr, "OUTPUTK: Unsuported operand type\n");
+    return (resERROR);
+  }
+
+  application->dd_printf("Output on port %d: %2x %3d %c\n", port, constant, constant, isprint(constant) ? constant : '.');
+  output_port->add_output(port, ticks->get_ticks() / clock_per_cycle(), constant);
+
+  output_port->value = constant;
+  port_id->value = port;
+
+  return (resGO);
+}
+
+int
+cl_pblaze::inst_regbank(int regbank)
+{
+  active_regbank = regbank;
+
+  return (resGO);
+}
+
+int
+cl_pblaze::inst_return(uint code, int inst)
+{
+  bool jump = false;
+
+  switch (inst) {
+    case RETURN:
+      application->debug("RETURN\n");
+      jump = true;
+      break;
+
+    case RETURN_C:
+      application->debug("RETURN C\n");
+      jump = FLAGS_GET_C;
+      break;
+
+    case RETURN_NC:
+      application->debug("RETURN NC\n");
+      jump = !FLAGS_GET_C;
+      break;
+
+    case RETURN_Z:
+      application->debug("RETURN Z\n");
+      jump = FLAGS_GET_Z;
+      break;
+
+    case RETURN_NZ:
+      application->debug("RETURN NZ\n");
+      jump = !FLAGS_GET_Z;
+      break;
+
+    default:
+      fprintf(stderr, "Unsuported RETURN instruction\n");
+      return (resERROR);
+  }
+
+  if (jump) {
+    u32_t addr;
+    if (stack_pop(&addr)) {
+      fprintf(stderr, "Call stack underflow.\n");
+
+      if (type->type == CPU_PBLAZE_6)
+        reset();
+
+      //return (resERROR);
+    }
+    PC = addr+1;
+  }
+
+  return(resGO);
+}
+
+int
+cl_pblaze::inst_returni(bool interrupt_enable)
+{
+  u32_t addr;
+  if (stack_pop(&addr)) {
+    fprintf(stderr, "Call stack underflow.\n");
+
+    if (type->type == CPU_PBLAZE_6)
+      reset();
+
+    //return (resERROR);
+  }
+  PC = addr+1;
+
+  FLAGS_SET_C(interrupt->preserved_flag_c);
+  FLAGS_SET_Z(interrupt->preserved_flag_z);
+  FLAGS_SET_I(interrupt_enable);
+
+  return (resGO);
+}
+
+int
+cl_pblaze::inst_rl(uint code, int operands)
+{
+  application->debug("RL\n");
+
+  cl_memory_cell *r1 = get_register(code, true);
+  u8_t value = r1->get();
+  u8_t result;
+
+  result = (value << 1) /*||*/ | (value >> 7);
+  r1->set(result);
+
+  FLAGS_SET_C(value & 0x80);
+  FLAGS_SET_Z(result == 0);
+
+  return (resGO);
+}
+
+int
+cl_pblaze::inst_rr(uint code, int operands)
+{
+  application->debug("RR\n");
+
+  cl_memory_cell *r1 = get_register(code, true);
+  u8_t value = r1->get();
+  u8_t result;
+
+  result = (value >> 1) | (value << 7);
+  r1->set(result);
+
+  FLAGS_SET_C(value & 0x01);
+  FLAGS_SET_Z(result == 0);
+
+  return (resGO);
+}
+
+int
+cl_pblaze::inst_sl(uint code, int inst)
+{
+  cl_memory_cell *r1 = get_register(code, true);
+  u8_t value = r1->get();
+  u8_t result;
+
+  result = (value << 1);
+
+  switch (inst) {
+    case SL0:
+      application->debug("SL0\n");
+      break;
+    case SL1:
+      application->debug("SL1\n");
+      result |= 0x01;
+      break;
+    case SLA:
+      application->debug("SLA\n");
+      result |= (FLAGS_GET_C ? 0x01 : 0x00);
+      break;
+    case SLX:
+      application->debug("SLX\n");
+      result |= (value & 0x01);
+      break;
+  }
+
+  r1->set(result);
+
+  FLAGS_SET_C(value & 0x80);
+  FLAGS_SET_Z(result == 0);
+
+  return (resGO);
+}
+
+int
+cl_pblaze::inst_sr(uint code, int inst)
+{
+  cl_memory_cell *r1 = get_register(code, true);
+  u8_t value = r1->get();
+  u8_t result;
+
+  result = (value >> 1);
+
+  switch (inst) {
+    case SR0:
+      application->debug("SR0\n");
+      break;
+    case SR1:
+      application->debug("SR1\n");
+      result |= 0x80;
+      break;
+    case SRA:
+      application->debug("SRA\n");
+      result |= (FLAGS_GET_C ? 0x80 : 0x00);
+      break;
+    case SRX:
+      application->debug("SRX\n");
+      result |= (value & 0x80);
+      break;
+  }
+
+  r1->set(result);
+
+  FLAGS_SET_C(value & 0x01);
+  FLAGS_SET_Z(result == 0);
+
+  return (resGO);
+}
+
+int
+cl_pblaze::inst_star(uint code, int operands)
+{
+  application->debug("STAR\n");
+
+  cl_memory_cell *r1;
+  cl_memory_cell *r2 = get_register(code, false);
+
+  if (operands == REG_REG) {
+    // getting register from inactive register bank
+    unsigned char reg_code = (code & 0x000f0) >> 4;
+    if (active_regbank == REGISTER_BANK_A)
+      reg_code += 0x10;
+
+    r1 = sfr->get_cell(reg_code);
+
+    r1->set(r2->get());
+  }
+  else {
+    fprintf(stderr, "STAR: Unsuported operand type\n");
+    return (resERROR);
+  }
+
+
+  return (resGO);
+}
+
+int
+cl_pblaze::inst_store(uint code, int operands)
+{
+  application->debug("STORE\n");
+
+  cl_memory_cell *r1 = get_register(code, true);
+  u8_t addr;
+
+  if (operands == REG_ADDRESS6) {
+    addr = get_constant(code) & 0x3f; // only bits 5..0 are used for addressing
+  }
+  else if (operands == REG_ADDRESS8) {
+    addr = get_constant(code);
+  }
+  else if (operands == REG_REG) {
+    addr = get_register(code, false)->get();
+  }
+  else {
+    fprintf(stderr, "STORE: Unsuported operand type\n");
+    return (resERROR);
+  }
+
+  ram->write(addr, r1->get());
+
+  return (resGO);
+}
+
+int
+cl_pblaze::inst_sub(uint code, int operands)
+{
+  application->debug("SUB\n");
+
+  cl_memory_cell *r1 = get_register(code, true);
+  u8_t operand;
+  int result;
+
+  if (operands == REG_CONSTANT) {
+      operand = get_constant(code);
+  }
+  else if (operands == REG_REG) {
+      operand = get_register(code, false)->get();
+  }
+  else {
+    fprintf(stderr, "SUB: Unsuported operand type\n");
+    return (resERROR);
+  }
+
+  result = r1->get() - operand;
+
+  // carry flag
+  FLAGS_SET_C(result < 0);
+
+  result = result % 256;
+
+  //zero flag
+  FLAGS_SET_Z(result == 0);
+
+  r1->set(result);
+
+  return(resGO);
+}
+
+int
+cl_pblaze::inst_subcy(uint code, int operands)
+{
+  application->debug("SUBCY\n");
+
+  cl_memory_cell *r1 = get_register(code, true);
+  u8_t operand;
+  int result;
+
+  if (operands == REG_CONSTANT) {
+      operand = get_constant(code);
+  }
+  else if (operands == REG_REG) {
+      operand = get_register(code, false)->get();
+  }
+  else {
+    fprintf(stderr, "SUBCY: Unsuported operand type\n");
+    return (resERROR);
+  }
+
+  result = r1->get() - operand - (FLAGS_GET_C ? 1 : 0);
+
+  // carry flag
+  FLAGS_SET_C(result < 0);
+
+  result = result % 256;
+
+  //zero flag
+  if (type->type == CPU_PBLAZE_3) {
+    FLAGS_SET_Z(result == 0);
+  }
+  else if (type->type == CPU_PBLAZE_6) {
+    FLAGS_SET_Z(FLAGS_GET_Z && (result == 0));
+  }
+
+  r1->set(result);
+
+  return(resGO);
+}
+
+int
+cl_pblaze::inst_test(uint code, int operands)
+{
+  application->debug("TEST\n");
+
+  cl_memory_cell *r1 = get_register(code, true);
+  u8_t operand;
+  u8_t result;
+
+  if (operands == REG_CONSTANT) {
+      operand = get_constant(code);
+  }
+  else if (operands == REG_REG) {
+      operand = get_register(code, false)->get();
+  }
+  else {
+    fprintf(stderr, "TEST: Unsuported operand type\n");
+    return (resERROR);
+  }
+
+  result = r1->get() & operand;
+  //zero flag
+  FLAGS_SET_Z(result == 0);
+
+  // algorith source: http://graphics.stanford.edu/~seander/bithacks.html#ParityNaive
+  bool parity = false;
+  while (result)
+  {
+    parity = !parity;
+    result = result & (result - 1);
+  }
+
+  // carry flag
+  FLAGS_SET_C(parity);
+
+  return(resGO);
+}
+
+int
+cl_pblaze::inst_testcy(uint code, int operands)
+{
+  application->debug("TESTCY\n");
+
+  cl_memory_cell *r1 = get_register(code, true);
+  u8_t operand;
+  u8_t result;
+
+  if (operands == REG_CONSTANT) {
+      operand = get_constant(code);
+  }
+  else if (operands == REG_REG) {
+      operand = get_register(code, false)->get();
+  }
+  else {
+    fprintf(stderr, "TESTCY: Unsuported operand type\n");
+    return (resERROR);
+  }
+
+  result = r1->get() & operand;
+  //zero flag
+  FLAGS_SET_Z((result == 0) && FLAGS_GET_Z);
+
+  // algorith source: http://graphics.stanford.edu/~seander/bithacks.html#ParityNaive
+  bool parity = false;
+  while (result)
+  {
+    parity = !parity;
+    result = result & (result - 1);
+  }
+
+  // carry flag
+  FLAGS_SET_C(parity ^ FLAGS_GET_C);
+
+  return(resGO);
+}
+
+int
+cl_pblaze::inst_xor(uint code, int operands)
+{
+  application->debug("XOR\n");
+
+  cl_memory_cell *r1 = get_register(code, true);
+  u8_t operand;
+  u8_t result;
+
+  if (operands == REG_CONSTANT) {
+      operand = get_constant(code);
+  }
+  else if (operands == REG_REG) {
+      operand = get_register(code, false)->get();
+  }
+  else {
+    fprintf(stderr, "XOR: Unsuported operand type\n");
+    return (resERROR);
+  }
+
+  result = r1->get() ^ operand;
+  r1->set(result);
+
+  FLAGS_SET_C(0);
+  FLAGS_SET_Z(result == 0);
+
+  return(resGO);
+}
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/pblaze.src/instcl.h sdcc-4.2.0+dfsg/sim/ucsim/pblaze.src/instcl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/pblaze.src/instcl.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/pblaze.src/instcl.h	2021-05-11 11:08:48.000000000 +0000
@@ -0,0 +1,57 @@
+/*
+ * Copyright (C) 2012-2013 Jiří Šimek
+ * Copyright (C) 2013 Zbyněk Křivka 
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Library General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Library General Public License for more details.
+ *
+ * You should have received a copy of the GNU Library General Public License
+ * along with this library; see the file COPYING.LIB. If not, write to
+ * the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
+ * Boston, MA 02110-1301, USA.
+ */
+
+
+  cl_memory_cell * get_register(uint code, bool first_operand);
+  uint get_constant(uint code);
+  uint get_address6(uint code);
+  uint get_address10(uint code);
+  uint get_address12(uint code);
+
+  virtual int inst_add(uint code, int operands);
+  virtual int inst_addcy(uint code, int operands);
+  virtual int inst_and(uint code, int operands);
+  virtual int inst_call(uint code, int inst, int operands);
+  virtual int inst_compare(uint code, int operands);
+  virtual int inst_comparecy(uint code, int operands);
+  virtual int inst_interrupt(bool value);
+  virtual int inst_fetch(uint code, int inst);
+  virtual int inst_hwbuild(uint code, int inst);
+  virtual int inst_input(uint code, int operands);
+  virtual int inst_jump(uint code, int inst, int operands);
+  virtual int inst_load(uint code, int operands);
+  virtual int inst_load_return(uint code, int operands);
+  virtual int inst_or(uint code, int operands);
+  virtual int inst_output(uint code, int operands);
+  virtual int inst_outputk(uint code, int operands);
+  virtual int inst_regbank(int regbank);
+  virtual int inst_return(uint code, int inst);
+  virtual int inst_returni(bool interrupt_enable);
+  virtual int inst_rl(uint code, int operands);
+  virtual int inst_rr(uint code, int operands);
+  virtual int inst_sl(uint code, int inst);
+  virtual int inst_sr(uint code, int inst);
+  virtual int inst_star(uint code, int operands);
+  virtual int inst_store(uint code, int operands);
+  virtual int inst_sub(uint code, int operands);
+  virtual int inst_subcy(uint code, int operands);
+  virtual int inst_test(uint code, int operands);
+  virtual int inst_testcy(uint code, int operands);
+  virtual int inst_xor(uint code, int operands);
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/pblaze.src/interrupt.cc sdcc-4.2.0+dfsg/sim/ucsim/pblaze.src/interrupt.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/pblaze.src/interrupt.cc	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/pblaze.src/interrupt.cc	2021-05-11 11:08:48.000000000 +0000
@@ -0,0 +1,62 @@
+/*
+ * Copyright (C) 2012-2013 Jiří Šimek
+ * Copyright (C) 2013 Zbyněk Křivka 
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Library General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Library General Public License for more details.
+ *
+ * You should have received a copy of the GNU Library General Public License
+ * along with this library; see the file COPYING.LIB. If not, write to
+ * the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
+ * Boston, MA 02110-1301, USA.
+ */
+
+
+// sim
+#include "itsrccl.h"
+
+// local
+#include "pblazecl.h"
+#include "interruptcl.h"
+#include "regspblaze.h"
+
+
+
+cl_interrupt::cl_interrupt(class cl_uc *auc) : cl_hw(auc, HW_INTERRUPT, 0, "irq")
+{
+}
+
+int
+cl_interrupt::init(void)
+{
+  interrupt_request = false;
+  return(0);
+}
+
+void
+cl_interrupt::set_cmd(class cl_cmdline *cmdline, class cl_console_base *con)
+{
+  class cl_cmd_arg *params[1]= { cmdline->param(0) };
+
+  if (cmdline->syntax_match(uc, NUMBER))
+    {
+      interrupt_request = params[0]->value.number != 0 ? true : false;
+    }
+  else
+    {
+      con->dd_printf("set hardware irq[%d] irq_value\n                   Set interrupt request value\n", id);
+    }
+}
+
+void
+cl_interrupt::print_info(class cl_console_base *con)
+{
+  con->dd_printf("Interrupt request %s, interrupts %s\n", (interrupt_request ? "active" : "inactive"), ((class cl_pblaze *) uc)->sfr->get(FLAGS) & bmI ? "enabled":"disabled");
+}
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/pblaze.src/interruptcl.h sdcc-4.2.0+dfsg/sim/ucsim/pblaze.src/interruptcl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/pblaze.src/interruptcl.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/pblaze.src/interruptcl.h	2021-05-11 11:08:48.000000000 +0000
@@ -0,0 +1,46 @@
+/*
+ * Copyright (C) 2012-2013 Jiří Šimek
+ * Copyright (C) 2013 Zbyněk Křivka 
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Library General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Library General Public License for more details.
+ *
+ * You should have received a copy of the GNU Library General Public License
+ * along with this library; see the file COPYING.LIB. If not, write to
+ * the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
+ * Boston, MA 02110-1301, USA.
+ */
+
+
+#ifndef INTERRUPTCL_HEADER
+#define INTERRUPTCL_HEADER
+
+
+#include "stypes.h"
+#include "pobjcl.h"
+#include "uccl.h"
+
+
+class cl_interrupt: public cl_hw
+{
+  public:
+    bool interrupt_request;
+
+    bool preserved_flag_c;
+    bool preserved_flag_z;
+  public:
+    cl_interrupt(class cl_uc *auc);
+    virtual int init(void);
+    virtual void set_cmd(class cl_cmdline *cmdline, class cl_console_base *con);
+    virtual void print_info(class cl_console_base *con);
+};
+
+
+#endif
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/pblaze.src/Makefile.in sdcc-4.2.0+dfsg/sim/ucsim/pblaze.src/Makefile.in
--- sdcc-4.0.0+dfsg/sim/ucsim/pblaze.src/Makefile.in	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/pblaze.src/Makefile.in	2022-01-09 14:02:03.000000000 +0000
@@ -0,0 +1,191 @@
+#
+# uCsim pblaze.src/Makefile
+#
+# (c) Drotos Daniel, Talker Bt. 1997
+# (c) Simek Jiri, 2012
+#
+
+# tool name
+TN		= pblaze
+
+STARTYEAR	= 2012
+
+SHELL		= /bin/sh
+CXX		= @CXX@
+CPP		= @CPP@
+CXXCPP		= @CXXCPP@
+RANLIB		= @RANLIB@
+INSTALL		= @INSTALL@
+STRIP		= @STRIP@
+MAKEDEP         = @MAKEDEP@
+
+top_builddir	= @top_builddir@
+top_srcdir	= @top_srcdir@
+
+transform	= @program_transform_name@
+
+DEFS            = $(subs -DHAVE_CONFIG_H,,@DEFS@)
+CPPFLAGS        = @CPPFLAGS@ -I$(srcdir) -I$(top_srcdir) -I$(top_builddir) \
+		  -I$(top_srcdir)/cmd.src -I$(top_srcdir)/sim.src \
+		  -I$(top_srcdir)/gui.src
+CFLAGS          = @WALL_FLAG@ @CFLAGS@
+CXXFLAGS        = @WALL_FLAG@ @CXXFLAGS@
+LDFLAGS         = @LDFLAGS@
+PICOPT		= @PICOPT@
+SHAREDLIB	= @SHAREDLIB@
+EXEEXT          = @EXEEXT@
+
+LIBS		= -L$(top_builddir) -lsim -lucsimutil -lguiucsim -lcmd -lsim @LIBS@
+DL		= @DL@
+dl_ok		= @dl_ok@
+
+prefix          = @prefix@
+exec_prefix     = @exec_prefix@
+bindir          = @bindir@
+libdir          = @libdir@
+datadir         = @datadir@
+datarootdir     = @datarootdir@
+includedir      = @includedir@
+mandir          = @mandir@
+man1dir         = $(mandir)/man1
+man2dir         = $(mandir)/man2
+infodir         = @infodir@
+srcdir          = @srcdir@
+VPATH           = @srcdir@
+
+OBJECTS_SHARED	= tinyxml.o tinystr.o tinyxmlerror.o tinyxmlparser.o \
+		  sim$(TN).o $(TN).o cmd$(TN).o \
+		  glob.o inst.o stack.o interrupt.o \
+		  portid.o inputport.o outputport.o
+OBJECTS_EXE	= s$(TN).o
+OBJECTS		= $(OBJECTS_SHARED) $(OBJECTS_EXE)
+
+# short/long exe and lib name
+SEN		= s$(TN)$(EXEEXT)
+LEN		= ucsim_$(TN)$(EXEEXT)
+SONAME		= libucsim_$(TN).so
+
+enable_dlso	= @enable_dlso@
+dlso_ok		= @dlso_ok@
+
+PBLAZEASM		=
+#TEST_OBJ	= test_bit.hex test_dis.hex test_mov.hex test_jmp.hex \
+#		  test_arith.hex
+
+# Compiling entire program or any subproject
+# ------------------------------------------
+all: checkconf otherlibs $(TN).src
+
+tests: $(TEST_OBJ)
+
+
+# Compiling and installing everything and runing test
+# ---------------------------------------------------
+install: all installdirs install_shared_lib
+	$(INSTALL) $(SEN) $(DESTDIR)$(bindir)/$(SEN)
+	$(STRIP) $(DESTDIR)$(bindir)/$(SEN)
+	$(INSTALL) $(LEN) $(DESTDIR)$(bindir)/$(LEN)
+	$(STRIP) $(DESTDIR)$(bindir)/$(LEN)
+
+
+# Deleting all the installed files
+# --------------------------------
+uninstall:
+	rm -f $(DESTDIR)$(bindir)/$(SEN)
+	rm -f $(DESTDIR)$(bindir)/$(LEN)
+	rm -f $(DESTDIR)$(libdir)/$(SONAME)
+
+
+# Performing self-test
+# --------------------
+check: test
+
+.PHONY:	test baseline
+test:
+	@$(MAKE) --no-print-directory -C test
+
+baseline:
+	@$(MAKE) --no-print-directory -C test baseline
+
+
+# Performing installation test
+# ----------------------------
+installcheck:
+
+
+# Creating installation directories
+# ---------------------------------
+installdirs:
+	test -d $(DESTDIR)$(bindir) || $(INSTALL) -d $(DESTDIR)$(bindir)
+
+
+# Creating dependencies
+# ---------------------
+dep: Makefile.dep
+
+Makefile.dep: $(srcdir)/*.cc $(srcdir)/*.h
+	$(MAKEDEP) $(CPPFLAGS) $(filter %.cc,$^) >Makefile.dep
+
+-include Makefile.dep
+include $(srcdir)/clean.mk
+
+# My rules
+# --------
+.SUFFIXES: .asm .hex
+
+$(TN).src: $(SEN) $(LEN) shared_lib
+
+$(SEN): $(OBJECTS) $(top_builddir)/libcmd.a $(top_builddir)/libguiucsim.a $(top_builddir)/libsim.a $(top_builddir)/libucsimutil.a
+	$(CXX) $(CXXFLAGS) $(LDFLAGS) $(OBJECTS) $(LIBS) -o $@
+
+$(LEN): $(SEN)
+	cp $< $@
+
+ifeq ($(dlso_ok),yes)
+shared_lib: $(top_builddir)/$(SONAME)
+install_shared_lib: shared_lib
+	test -d $(DESTDIR)$(libdir) || $(INSTALL) -d $(DESTDIR)$(libdir)
+	$(INSTALL) $(top_builddir)/$(SONAME) $(DESTDIR)$(libdir)/$(SONAME)
+else
+shared_lib:
+	@$(top_srcdir)/mkecho $(top_builddir) "No s$(TN) shared lib made."
+	@$(top_srcdir)/mkecho $(top_builddir) "(SHAREDLIB="$(SHAREDLIB)",dl_ok="$(dl_ok)",enable_dlso="$(enable_dlso)")"
+install_shared_lib:
+endif
+
+$(top_builddir)/$(SONAME): $(OBJECTS_SHARED)
+	$(CXX) -shared $(LDFLAGS) $(OBJECTS_SHARED) -o $@
+
+otherlibs: $(top_builddir)/libcmd.a $(top_builddir)/libguiucsim.a $(top_builddir)/libsim.a $(top_builddir)/libucsimutil.a
+
+$(top_builddir)/libcmd.a:
+	$(MAKE) -C $(top_builddir)/cmd.src all
+
+$(top_builddir)/libguiucsim.a:
+	$(MAKE) -C $(top_builddir)/gui.src checkconf ucsim_lib
+
+$(top_builddir)/libsim.a:
+	$(MAKE) -C $(top_builddir)/sim.src all
+
+$(top_builddir)/libucsimutil.a:
+	$(MAKE) -C $(top_builddir) -f main.mk
+
+.cc.o:
+	$(CXX) $(CXXFLAGS) $(PICOPT) $(CPPFLAGS) $(TARGET_ARCH) -c $< -o $@
+
+.cpp.o:
+	$(CXX) $(CXXFLAGS) $(PICOPT) $(CPPFLAGS) $(TARGET_ARCH) -c $< -o $@
+
+.asm.hex:
+	$(PBLAZEASM) -l $< -o $@ -e $<.lst
+
+
+# Remaking configuration
+# ----------------------
+checkconf:
+	@if [ -f $(top_builddir)/devel ]; then\
+	  $(MAKE) -f conf.mk srcdir="$(srcdir)" top_builddir="$(top_builddir)" freshconf;\
+	fi
+
+# End of $(TN).src/Makefile.in
+
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/pblaze.src/outputport.cc sdcc-4.2.0+dfsg/sim/ucsim/pblaze.src/outputport.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/pblaze.src/outputport.cc	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/pblaze.src/outputport.cc	2021-05-11 11:08:48.000000000 +0000
@@ -0,0 +1,117 @@
+/*
+ * Copyright (C) 2012-2013 Jiří Šimek
+ * Copyright (C) 2013 Zbyněk Křivka 
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Library General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Library General Public License for more details.
+ *
+ * You should have received a copy of the GNU Library General Public License
+ * along with this library; see the file COPYING.LIB. If not, write to
+ * the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
+ * Boston, MA 02110-1301, USA.
+ */
+
+
+#include 
+#include 
+
+// local
+#include "pblazecl.h"
+#include "outputportcl.h"
+
+#include "tinyxml.h"
+
+
+cl_output_port::cl_output_port(class cl_uc *auc) : cl_hw(auc, HW_PORT, 0, "output_port")
+{
+}
+
+
+void
+cl_output_port::set_cmd(class cl_cmdline *cmdline, class cl_console_base *con)
+{
+    con->dd_printf("Output port is read-only\n", id);
+}
+
+void
+cl_output_port::print_info(class cl_console_base *con)
+{
+  con->dd_printf("Value on output port: %2X\n", value);
+}
+
+
+
+void
+cl_output_port::add_output(int port, long tick, t_mem value) {
+  if (outputs.find(port) == outputs.end()) {
+    outputs.insert(make_pair(port, list()));
+  }
+
+  struct output o;
+  o.tick = tick;
+  o.value = value;
+
+  outputs[port].push_back(o);
+}
+
+void
+cl_output_port::print_outputs(char *file_name) {
+  /*
+  if (file_name == NULL) {
+    for (output_map::iterator it = outputs.begin(); it != outputs.end(); it++) {
+      application->dd_printf("port %d:\n", it->first);
+
+      for (list::iterator it2 = it->second.begin(); it2 != it->second.end(); it2++) {
+        application->dd_printf("\ttick %d: %2x\n", (*it2).tick, (*it2).value);
+      }
+    }
+  }
+  else {*/
+    char buffer[8];
+
+    TiXmlDocument doc;
+    TiXmlElement *root;
+    TiXmlElement *port, *element;
+    TiXmlText * text;
+
+    TiXmlDeclaration * decl = new TiXmlDeclaration( "1.0", "", "" );
+    doc.LinkEndChild( decl );
+    root = new TiXmlElement( "outputs" );
+    doc.LinkEndChild( root );
+
+
+    for (output_map::iterator it = outputs.begin(); it != outputs.end(); it++) {
+      port = new TiXmlElement( "port" );
+      port->SetAttribute("id", it->first);
+      root->LinkEndChild( port );
+
+      for (list::iterator it2 = it->second.begin(); it2 != it->second.end(); it2++) {
+        element = new TiXmlElement( "output" );
+        element->SetAttribute("tick", (*it2).tick);
+        sprintf(buffer, "%2x", (*it2).value);
+        text = new TiXmlText(buffer);
+        element->LinkEndChild( text );
+        port->LinkEndChild( element );
+      }
+    }
+
+
+  if (file_name == NULL) {
+    TiXmlPrinter printer;
+    doc.Accept(&printer);
+    application->dd_printf("%s", printer.CStr());
+  }
+  else {
+    doc.SaveFile( file_name );
+  }
+}
+
+
+
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/pblaze.src/outputportcl.h sdcc-4.2.0+dfsg/sim/ucsim/pblaze.src/outputportcl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/pblaze.src/outputportcl.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/pblaze.src/outputportcl.h	2021-05-14 21:19:53.000000000 +0000
@@ -0,0 +1,59 @@
+/*
+ * Copyright (C) 2012-2013 Jiří Šimek
+ * Copyright (C) 2013 Zbyněk Křivka 
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Library General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Library General Public License for more details.
+ *
+ * You should have received a copy of the GNU Library General Public License
+ * along with this library; see the file COPYING.LIB. If not, write to
+ * the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
+ * Boston, MA 02110-1301, USA.
+ */
+
+
+#ifndef OUTPUTPORTCL_HEADER
+#define OUTPUTPORTCL_HEADER
+
+#include 
+#include 
+
+#include "ddconfig.h"
+#include "stypes.h"
+#include "pobjcl.h"
+#include "uccl.h"
+
+using namespace std;
+
+struct output {
+  long tick;
+  t_mem value;
+};
+typedef map > output_map;
+
+class cl_output_port: public cl_hw
+{
+  public:
+    u8_t value;
+    output_map outputs;
+
+    cl_output_port(class cl_uc *auc);
+    virtual void set_cmd(class cl_cmdline *cmdline, class cl_console_base *con);
+    virtual void print_info(class cl_console_base *con);
+
+
+    virtual void add_output(int port, long tick, t_mem value);
+    virtual void print_outputs(char *file_name);
+};
+
+
+#endif
+
+
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/pblaze.src/pblaze.cc sdcc-4.2.0+dfsg/sim/ucsim/pblaze.src/pblaze.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/pblaze.src/pblaze.cc	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/pblaze.src/pblaze.cc	2022-01-27 21:35:29.000000000 +0000
@@ -0,0 +1,1572 @@
+/*
+ * Copyright (C) 2012-2013 Jiří Šimek
+ * Copyright (C) 2013 Zbyněk Křivka 
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Library General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Library General Public License for more details.
+ *
+ * You should have received a copy of the GNU Library General Public License
+ * along with this library; see the file COPYING.LIB. If not, write to
+ * the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
+ * Boston, MA 02110-1301, USA.
+ */
+
+
+#include "ddconfig.h"
+
+#include  /* for va_list */
+#include 
+#include 
+#include 
+#include 
+#include "i_string.h"
+#include 
+#include 
+
+#include "tinyxml.h"
+
+// prj
+#include "globals.h"
+#include "utils.h"
+#include "pobjcl.h"
+
+// sim
+#include "simcl.h"
+#include "dregcl.h"
+
+//cmd
+#include "cmd_uccl.h"
+
+// local
+#include "pblazecl.h"
+#include "glob.h"
+#include "regspblaze.h"
+#include "pblazemac.h"
+#include "interruptcl.h"
+#include "portidcl.h"
+#include "inputportcl.h"
+#include "outputportcl.h"
+#include "cmdpblazecl.h"
+
+#define uint32 t_addr
+#define uint8 unsigned char
+
+using namespace std;
+/*******************************************************************/
+
+
+/*
+ * Base type of PicoBlaze controllers
+ */
+
+cl_pblaze::cl_pblaze(struct cpu_entry *cputype, class cl_sim *asim):
+  cl_uc(asim)
+{
+  type = cputype;
+}
+
+cl_pblaze::~cl_pblaze(void) {
+  // if option -o was specified, at the end of simulation state and outputs are saved into file
+  cl_option * opt = sim->app->options->get_option("pblaze_output_file");
+  if (opt != NULL) {
+    char *file_prefix;
+    opt->get_value(&file_prefix);
+    char file_name[256];
+
+    sprintf(file_name, "%s_state.xml", file_prefix);
+    print_state(NULL, file_name);
+
+    sprintf(file_name, "%s_outputs.xml", file_prefix);
+    output_port->print_outputs(file_name);
+  }
+}
+
+int
+cl_pblaze::init(void)
+{
+  // inits RAM and ROM size and interrupt vector
+  init_uc_parameters();
+
+  cl_uc::init(); /* Memories now exist */
+
+  set_xtal(8000000);
+
+  // loading file with interrupts
+  read_interrupt_file();
+  read_input_file();
+
+  return(0);
+}
+
+
+void
+cl_pblaze::reset(void)
+{
+  cl_uc::reset();
+
+  sfr->set(FLAGS, 0);
+  sfr->set(SP, 0);
+
+  active_regbank = REGISTER_BANK_A;
+}
+
+
+const char *
+cl_pblaze::id_string(void)
+{
+  int i = 0;
+  while ((cpus_pblaze[i].type != 0) && (type->type != cpus_pblaze[i].type))
+    i++;
+
+  return(cpus_pblaze[i].type_str);
+}
+
+
+/*
+ * Making elements of the controller
+ */
+t_addr
+cl_pblaze::get_mem_size(enum mem_class type)
+{
+  switch(type)
+    {
+    case MEM_ROM: return rom_size;
+    case MEM_IRAM: return ram_size;
+    case MEM_STACK: return stack_size;
+    default: return(0);
+    }
+}
+
+
+void
+cl_pblaze::mk_hw_elements(void)
+{
+  class cl_hw *h;
+  cl_uc::mk_hw_elements();
+
+  add_hw(h= new cl_dreg(this, 0, "dreg"));
+  h->init();
+  
+  hws->add(interrupt = new cl_interrupt(this));
+  interrupt->init();
+
+  hws->add(port_id = new cl_port_id(this));
+  port_id->init();
+
+  hws->add(output_port = new cl_output_port(this));
+  output_port->init();
+
+  hws->add(input_port = new cl_input_port(this));
+  input_port->init();
+}
+
+void
+cl_pblaze::make_memories(void)
+{
+  class cl_address_space *as;
+
+
+  // REGISTERS simulated in SFR memory
+  sfr= as= new cl_address_space(MEM_SFR_ID, 0, 0x22, 8);
+  as->init();
+  address_spaces->add(as);
+
+  // ROM 1k 18b
+  rom = as = new cl_address_space(MEM_ROM_ID, 0, rom_size, 18); // picoblaze ma 18b sirokou pamet. kvuli kompatibilite s ucsim (cleneni po bytech) musi byt zvetstena na 24b = 3B
+  as->init();
+  address_spaces->add(as);
+
+
+  // RAM 8b (size for KCPSM3 is 64, for KCPSM6
+  ram = as= new cl_address_space(MEM_IRAM_ID, 0, ram_size, 8);
+  as->init();
+  address_spaces->add(as);
+
+  // stack 31 10b
+  stack = as = new cl_address_space(MEM_STACK_ID, 0, stack_size, 12);
+  as->init();
+  address_spaces->add(as);
+
+  class cl_address_decoder *ad;
+  class cl_memory_chip *chip;
+
+  // sfr chip init
+  chip = new cl_chip8("sfr_chip", 0x22, 8);
+  chip->init();
+  memchips->add(chip);
+  ad = new cl_address_decoder(as = address_space(MEM_SFR_ID), chip, 0, 0x21, 0);
+  ad->init();
+  as->decoders->add(ad);
+  ad->activate(0);
+
+  // rom chip init
+  chip = new cl_chip32("rom_chip", rom_size, 18);
+  chip->init();
+  memchips->add(chip);
+  ad = new cl_address_decoder(as = address_space(MEM_ROM_ID), chip, 0, rom_size-1, 0);
+  ad->init();
+  as->decoders->add(ad);
+  ad->activate(0);
+
+  // ram chip init
+  chip= new cl_chip8("ram_chip", ram_size, 8);
+  chip->init();
+  memchips->add(chip);
+  ad= new cl_address_decoder(as = address_space(MEM_IRAM_ID), chip, 0, ram_size-1, 0);
+  ad->init();
+  as->decoders->add(ad);
+  ad->activate(0);
+
+  // stack chip
+  chip = new cl_chip8("stack_chip", stack_size, 12);
+  chip->init();
+  memchips->add(chip);
+  ad= new cl_address_decoder(as = address_space(MEM_STACK_ID), chip, 0, stack_size-1, 0);
+  ad->init();
+  as->decoders->add(ad);
+  ad->activate(0);
+}
+
+void
+cl_pblaze::build_cmdset(class cl_cmdset *cmdset)
+{
+  class cl_cmd *cmd;
+  class cl_cmdset *inner_cmd_set;
+  class cl_super_cmd *super_cmd;
+
+  cl_uc::build_cmdset(cmdset);
+  /*
+  cmdset->add(cmd= new cl_dc_cmd("dc", true,
+"dc [start [stop]]  Dump ROM",
+"long help of dc"));
+  cmd->init();
+
+  cmdset->add(cmd= new cl_di_cmd("di", true,
+"di [start [stop]]  Dump Internal RAM",
+"long help of di"));
+  cmd->init();
+
+  cmdset->add(cmd= new cl_dx_cmd("dx", true,
+"dx [start [stop]]  Dump External RAM",
+"long help of dx"));
+  cmd->init();
+
+  cmdset->add(cmd= new cl_ds_cmd("ds", true,
+"ds [start [stop]]  Dump SFR",
+"long help of ds"));
+  cmd->init();
+  */
+
+  cmdset->add(cmd= new cl_pbstate_cmd("pbstate", 0));//true,
+	      //"pbstate [\"file\"]   Prints PicoBlaze state to std output or specified file",
+	      //"long help of pbstate"));
+  cmd->init();
+  
+
+  { // import
+    super_cmd= (class cl_super_cmd *)(cmdset->get_cmd("import"));
+    if (super_cmd)
+      inner_cmd_set= super_cmd->get_subcommands();
+    else {
+      inner_cmd_set= new cl_cmdset();
+      inner_cmd_set->init();
+    }
+
+    inner_cmd_set->add(cmd= new cl_import_pbstate_cmd("pbstate", 0));//,
+    //"import pbstate \"file\" Loads Picoblaze state from xml file",
+    //"long help of import pbstate"));
+    cmd->add_name("pbstate");
+    cmd->init();
+
+    inner_cmd_set->add(cmd= new cl_import_interrupts_cmd("interrupts", 0));//,
+    //"import interrupts \"file\" Loads interrupts from xml file",
+    //"long help of import interrupts"));
+    cmd->add_name("interrupts");
+    cmd->init();
+
+    inner_cmd_set->add(cmd= new cl_import_input_cmd("input", 0));//,
+    //"import input \"file\" Loads input from xml file",
+    //"long help of import input"));
+    cmd->add_name("input");
+    cmd->init();
+    
+    if (!super_cmd) {
+      cmdset->add(cmd= new cl_super_cmd("import", 0, inner_cmd_set));//,
+      //"import subcommand  Import, see `import' command for more help",
+      //"long help of import", inner_cmd_set));
+      cmd->init();
+    }
+  }
+
+  // print output
+  super_cmd = (class cl_super_cmd *)(cmdset->get_cmd("get"));
+  if (super_cmd)
+    inner_cmd_set= super_cmd->get_subcommands();
+  else {
+    inner_cmd_set= new cl_cmdset();
+    inner_cmd_set->init();
+  }
+  inner_cmd_set->add(cmd= new cl_get_output_cmd("output", 0));//,
+  //"get output [\"file\"] Prints realized outputs of PicoBlaze",
+  //"long help of get output"));
+    cmd->add_name("output");
+    cmd->init();
+}
+
+
+
+
+/*
+ * Help command interpreter
+ */
+
+struct dis_entry *
+cl_pblaze::dis_tbl(void)
+{
+      return disass_pblaze_x;
+    //TODO doimplementovat, osetrit;
+  //return(disass_pblaze);
+}
+
+struct name_entry *
+cl_pblaze::sfr_tbl(void)
+{
+  return(sfr_tab);
+}
+
+struct name_entry *
+cl_pblaze::bit_tbl(void)
+{
+  return(bit_tab);
+}
+
+// Returns length of instruction at given address
+int
+cl_pblaze::inst_length(t_addr addr)
+{
+  int len = 0;
+
+  get_disasm_info(addr, &len, NULL, NULL);
+
+  return len;
+}
+
+int
+cl_pblaze::inst_branch(t_addr addr)
+{
+  int b;
+
+  get_disasm_info(addr, NULL, &b, NULL);
+
+  return b;
+}
+
+int
+cl_pblaze::longest_inst(void)
+{
+  return 1;
+}
+
+
+const char *
+cl_pblaze::get_disasm_info(t_addr addr,
+                        int *ret_len,
+                        int *ret_branch,
+                        int *immed_offset)
+{
+  const char *b = NULL;
+  uint code;
+  int len = 0;
+  int immed_n = 0;
+  int i;
+  int start_addr = addr;
+  struct dis_entry_pblaze *dis_e;
+
+  code= get_mem(MEM_ROM_ID, addr++);
+  dis_e = NULL;
+
+  i = 0;
+
+  dis_entry_pblaze * disass_pblaze = (type->type == CPU_PBLAZE_3 ? disass_pblaze3 : disass_pblaze6);
+  while ((code & disass_pblaze[i].mask) != disass_pblaze[i].code && disass_pblaze[i].instruction != BAD_OPCODE)
+    i++;
+
+  // found instruction record
+  dis_e = &disass_pblaze[i];
+
+  b = dis_e->mnemonic;
+  if (b != NULL)
+    len += (dis_e->length);
+
+  if (ret_branch) {
+    *ret_branch = dis_e->branch;
+  }
+
+  if (immed_offset) {
+    if (immed_n > 0)
+      *immed_offset = immed_n;
+    else
+      *immed_offset = (addr - start_addr);
+  }
+
+  if (len == 0)
+    len = 1;
+
+  if (ret_len)
+    *ret_len = len;
+
+  return b;
+}
+
+char *
+cl_pblaze::disass(t_addr addr)
+{
+  chars work, temp;
+  const char *b;
+  int len = 0;
+  int immed_offset = 0;
+  bool first= true;
+  
+  work= "";
+
+  b = get_disasm_info(addr, &len, NULL, &immed_offset);
+
+  if (b == NULL)
+    {
+      return strdup("UNKNOWN/INVALID");
+    }
+
+  while (*b)
+    {
+      if ((*b == ' ') && first)
+	{
+	  first= false;
+	  while (work.len() < 6) work.append(' ');
+	}
+      if (*b == '%')
+        {
+          b++;
+	  temp= "";
+          switch (*(b++))
+            {
+            case 'a': // 10b address
+              temp.format("0x%x", (rom->get(addr) & 0x3ff));
+              break;
+            case 'A': // 12b address
+              temp.format("0x%x", (rom->get(addr) & 0xfff));
+              break;
+            case 'k': // immediate value (constant)
+              temp.format("0x%x", (rom->get(addr) & 0xff));
+              break;
+            case 'K': // immediate value (constant)
+              temp.format("0x%x", (rom->get(addr) & 0xff0) >> 4);
+              break;
+            case 'm': // 6b address to RAM
+              temp.format("0x%x", (rom->get(addr) & 0x3f));
+              break;
+            case 'M': // 8b address to RAM
+              temp.format("0x%x", (rom->get(addr) & 0xff));
+              break;
+            case 'p': // 8b port number
+              temp.format("%d", (rom->get(addr) & 0xff));
+              break;
+            case 'P': // 4b port number
+              temp.format("%d", (rom->get(addr) & 0xf));
+              break;
+            case 'r': // register as first operand
+              temp.format("s%x", (rom->get(addr) & 0xf00) >> 8);
+              break;
+            case 's': // register as second operand
+              temp.format("s%x", (rom->get(addr) & 0xf0) >> 4);
+              break;
+            default:
+              temp= "?";
+              break;
+            }
+	  work+= temp;
+        }
+      else
+	work+= *(b++);
+    }
+
+  return(strdup(work.c_str()));
+}
+
+
+void
+cl_pblaze::print_regs(class cl_console_base *con)
+{
+  if (type->type == CPU_PBLAZE_6)
+    con->dd_printf("Regbank A\n");
+
+  for (int i=0; i<16; i++) {
+    con->dd_printf("S%x= 0x%02x %3d %c\n",i, sfr->get(i), sfr->get(i), isprint(sfr->get(i))?sfr->get(i):'.');
+  }
+
+  if (type->type == CPU_PBLAZE_6) {
+    con->dd_printf("Regbank B\n");
+
+    for (int i=16; i<32; i++) {
+      con->dd_printf("S%x= 0x%02x %3d %c\n",i, sfr->get(i), sfr->get(i), isprint(sfr->get(i))?sfr->get(i):'.');
+    }
+  }
+
+  if (type->type == CPU_PBLAZE_6)
+    con->dd_printf("Active regbank= %c\n", active_regbank == REGISTER_BANK_A ? 'A' : 'B');
+
+  con->dd_printf("PC= 0x%06x\n", PC);
+  con->dd_printf("SP= 0x%06x\n", sfr->get(SP));
+  con->dd_printf("C= %d, Z= %d, I= %d\n", FLAGS_GET_C, FLAGS_GET_Z, FLAGS_GET_I);
+
+  print_disass(PC, con);
+}
+
+/*
+ * If file name is not specified, PicoBlaze state is printed to console. Otherwise state is saved into specified file
+ */
+void
+cl_pblaze::print_state(class cl_console_base *con, char *file_name)
+{
+  const int buffer_size = 4096;
+  char buffer[buffer_size];
+  int written = 0;
+
+  TiXmlDocument doc;
+  TiXmlElement * root;
+  TiXmlElement * element;
+  TiXmlText * text;
+
+	TiXmlDeclaration * decl = new TiXmlDeclaration( "1.0", "", "" );
+	doc.LinkEndChild( decl );
+  root = new TiXmlElement( "picoblaze" );
+	root->SetAttribute("type", id_string());
+	doc.LinkEndChild( root );
+
+	// RAM
+  element = new TiXmlElement( "ram" );
+	element->SetAttribute("size", ram_size);
+	element->SetAttribute("bytes", 1);
+  for (unsigned int i = 0; iget(i));
+	text = new TiXmlText(buffer);
+	element->LinkEndChild( text );
+	root->LinkEndChild( element );
+
+	// STACK
+  element = new TiXmlElement( "stack" );
+	element->SetAttribute("size", stack_size);
+	element->SetAttribute("bytes", 2);
+	written = 0;
+  for (unsigned int i = 0; iget(i));
+	text = new TiXmlText(buffer);
+	element->LinkEndChild( text );
+	root->LinkEndChild( element );
+
+	// REGISTERS
+  TiXmlElement * registers = new TiXmlElement( "registers" );
+	if (type->type == CPU_PBLAZE_6) {
+    registers->SetAttribute("activeRegbank", active_regbank == REGISTER_BANK_A ? "A" : "B");
+  }
+	root->LinkEndChild( registers );
+
+  // REGBANK A
+  element = new TiXmlElement( "regbank" );
+  if (type->type == CPU_PBLAZE_6) {
+    element->SetAttribute("name", "A");
+  }
+	written = 0;
+  for (unsigned int i = 0; i<16; i++)
+    written += snprintf(buffer + written, buffer_size - written - 1, "%02x", sfr->get(i));
+	text = new TiXmlText(buffer);
+	element->LinkEndChild( text );
+	registers->LinkEndChild( element );
+
+  // REGBANK B
+  if (type->type == CPU_PBLAZE_6) {
+    element = new TiXmlElement( "regbank" );
+      element->SetAttribute("name", "B");
+    written = 0;
+    for (unsigned int i = 16; i<32; i++)
+    written += snprintf(buffer + written, buffer_size - written - 1, "%02x", sfr->get(i));
+    text = new TiXmlText(buffer);
+    element->LinkEndChild( text );
+    registers->LinkEndChild( element );
+  }
+
+  // PC
+  element = new TiXmlElement( "pc" );
+  snprintf(buffer, buffer_size - 1, "%x", AU(PC));
+  text = new TiXmlText(buffer);
+  element->LinkEndChild( text );
+  registers->LinkEndChild( element );
+
+  // SP
+  element = new TiXmlElement( "sp" );
+  snprintf(buffer, buffer_size - 1, "%x", sfr->get(SP));
+  text = new TiXmlText(buffer);
+  element->LinkEndChild( text );
+  registers->LinkEndChild( element );
+
+  // FLAGS
+  TiXmlElement * flags = new TiXmlElement( "flags" );
+  registers->LinkEndChild( flags );
+
+  // Carry
+  element = new TiXmlElement( "carry" );
+  snprintf(buffer, buffer_size - 1, "%x", FLAGS_GET_C ? 1:0);
+  text = new TiXmlText(buffer);
+  element->LinkEndChild( text );
+  flags->LinkEndChild( element );
+  // Zero
+  element = new TiXmlElement( "zero" );
+  snprintf(buffer, buffer_size - 1, "%x", FLAGS_GET_Z ? 1:0);
+  text = new TiXmlText(buffer);
+  element->LinkEndChild( text );
+  flags->LinkEndChild( element );
+  // IE
+  element = new TiXmlElement( "interruptEnable" );
+  snprintf(buffer, buffer_size - 1, "%x", FLAGS_GET_I ? 1:0);
+  text = new TiXmlText(buffer);
+  element->LinkEndChild( text );
+  flags->LinkEndChild( element );
+
+
+  if (file_name == NULL) {
+    TiXmlPrinter printer;
+    doc.Accept(&printer);
+    con->dd_printf("%s", printer.CStr());
+  }
+  else {
+    doc.SaveFile( file_name );
+  }
+
+
+    /*
+  const int buffer_size = 4096;
+  char buffer[buffer_size];
+  int written;
+
+  written = snprintf(buffer, buffer_size, "RAM:");
+  for (unsigned int i = 0; iget(i));
+  written += snprintf(buffer + written, buffer_size - written - 1, "\n");
+
+  written += snprintf(buffer + written, buffer_size - written - 1,"STACK:");
+  for (unsigned int i = 0; iget(i));
+  written += snprintf(buffer + written, buffer_size - written - 1, "\n");
+
+  if (type->type == CPU_PBLAZE_6) {
+    written += snprintf(buffer + written, buffer_size - written - 1, "ACTIVE_REGBANK:%s\n", active_regbank == REGISTER_BANK_A ? "A" : "B");
+  }
+
+  written += snprintf(buffer + written, buffer_size - written - 1, "REGBANK_A:");
+  for (unsigned int i = 0; i<16; i++)
+    written += snprintf(buffer + written, buffer_size - written - 1, "%02x", sfr->get(i));
+  written += snprintf(buffer + written, buffer_size - written - 1, "\n");
+
+  if (type->type == CPU_PBLAZE_6) {
+    written += snprintf(buffer + written, buffer_size - written - 1, "REGBANK_B:");
+    for (unsigned int i = 16; i<32; i++)
+      written += snprintf(buffer + written, buffer_size - written - 1, "%02x", sfr->get(i));
+    written += snprintf(buffer + written, buffer_size - written - 1, "\n");
+  }
+
+  written += snprintf(buffer + written, buffer_size - written - 1, "PC:%x\n", PC);
+  written += snprintf(buffer + written, buffer_size - written - 1, "SP:%x\n", sfr->get(INTERNAL_SP));
+  written += snprintf(buffer + written, buffer_size - written - 1, "FLAG_Z:%x\n", FLAGS_GET_Z ? 1:0);
+  written += snprintf(buffer + written, buffer_size - written - 1, "FLAG_C:%x\n", FLAGS_GET_C ? 1:0);
+  written += snprintf(buffer + written, buffer_size - written - 1, "FLAG_I:%x\n", FLAGS_GET_I ? 1:0);
+
+  if (file_name == NULL) {
+    con->dd_printf("%s", buffer);
+  }
+  else {
+    FILE *f = fopen(file_name, "w");
+    if (f == NULL) {
+      con->dd_printf("Cannot create file '%s'", file_name);
+      return;
+    }
+
+    fprintf(f, "%s", buffer);
+    fclose(f);
+  }*/
+}
+
+void
+cl_pblaze::load_state(class cl_console_base *con, char *file_name)
+{
+  TiXmlDocument doc( file_name );
+  if (!doc.LoadFile()) {
+    con->dd_printf("Cannot load file.");
+    return;
+  }
+
+  TiXmlElement *root = doc.FirstChildElement("picoblaze");
+  TiXmlElement *element;
+
+  // TODO lover/uppper case
+  if (strcmp(root->Attribute("type"), id_string()) != 0) {
+    con->dd_printf("Error: types of Picoblaze don't match current configuration.");
+    return;
+  }
+
+  // IMPORT RAM
+  element = root->FirstChildElement("ram");
+  if ((unsigned long int)strtol(element->Attribute("size"), NULL, 0) != ram_size) {
+    con->dd_printf("Error: RAM size doesn't match current configuration.");
+    return;
+  }
+  else {
+    int size = strtol(element->Attribute("bytes"), NULL, 0) * 2; // chars ( bytes * 2 = chars for one value) per one memory cell
+    const char * text = element->GetText();
+
+    // format string for sscanf - depends on bytes per memory cell
+    char format[5];
+    sprintf(format,"%%%ds", size);
+
+    for (unsigned int i=0; iset(i, strtol(cell, NULL, 16));
+    }
+  }
+  // IMPORT STACK
+  element = root->FirstChildElement("stack");
+  if ((unsigned long int)strtol(element->Attribute("size"), NULL, 0) != stack_size) {
+    con->dd_printf("Error: Stack size doesn't match current configuration.");
+    return;
+  }
+  else {
+    int size = strtol(element->Attribute("bytes"), NULL, 0) * 2; // chars ( bytes * 2 = chars for one value) per one memory cell
+    const char * text = element->GetText();
+
+    // format string for sscanf - depends on bytes per memory cell
+    char format[5];
+    sprintf(format,"%%%ds", size);
+
+    for (unsigned int i=0; iset(i, strtol(cell, NULL, 16));
+    }
+  }
+
+  TiXmlElement *registers = root->FirstChildElement("registers");
+
+  // active regbank
+	if (type->type == CPU_PBLAZE_6) {
+    const char *ar = registers->Attribute("activeRegbank"); //, active_regbank == REGISTER_BANK_A ? "A" : "B");
+    if (strcmp(ar, "A") == 0) { // TODO lower/upper case
+      active_regbank = REGISTER_BANK_A;
+    }
+    else if (strcmp(ar, "B") == 0) {
+      active_regbank = REGISTER_BANK_B;
+    }
+  }
+
+  // register bank
+  element = registers->FirstChildElement("regbank");
+  {
+    int addr = S0;
+    if (type->type == CPU_PBLAZE_6) {
+      const char *n = element->Attribute("name");
+      if (strcmp(n, "B") == 0) {
+        addr = S0b;
+      }
+    }
+    const char * text = element->GetText();
+    for (int i=0; i<16; i++) {
+      char cell[3];
+      sscanf(text + i*2, "%2s", cell);
+      sfr->set(addr+i, strtol(cell, NULL, 16));
+    }
+  }
+
+  // secong register bank (only for kcpsm6)
+  if (type->type == CPU_PBLAZE_6) {
+    int addr = S0b;
+    element = element->NextSiblingElement("regbank");
+    const char *n = element->Attribute("name");
+    if (strcmp(n, "A") == 0) {
+      addr = S0;
+    }
+    const char *text = element->GetText();
+    for (int i=0; i<16; i++) {
+      char cell[3];
+      sscanf(text + i*2, "%2s", cell);
+      sfr->set(addr+i, strtol(cell, NULL, 16));
+    }
+  }
+
+  // PC
+  element = registers->FirstChildElement("pc");
+  PC = strtol(element->GetText(), NULL, 16);
+
+  // SP
+  element = registers->FirstChildElement("sp");
+  sfr->set(SP, strtol(element->GetText(), NULL, 16));
+
+  TiXmlElement *flags = registers->FirstChildElement("flags");
+
+  element = flags->FirstChildElement("carry");
+  FLAGS_SET_C(strtol(element->GetText(), NULL, 0));
+
+  element = flags->FirstChildElement("zero");
+  FLAGS_SET_Z(strtol(element->GetText(), NULL, 0));
+
+  element = flags->FirstChildElement("interruptEnable");
+  FLAGS_SET_I(strtol(element->GetText(), NULL, 0));
+}
+
+
+
+
+/*
+ * Execution
+ */
+
+
+
+int
+cl_pblaze::do_inst(int step)
+{
+  t_addr PCsave = PC;
+  int result = resGO;
+
+  if (step < 0)
+    step= 1;
+  while (step-- &&
+         result == resGO)
+    {
+      pre_inst();
+      result = exec_inst();
+      post_inst();
+
+      if (result == resINV_INST)
+        /* backup to start of instruction */
+        PC = PCsave;
+      else if (result == resGO) {
+          if (!inst_at(PCsave))
+            analyze(PCsave);
+
+          int res;
+          if ((res = do_interrupt()) != resGO)
+            result = res;
+      }
+    }
+  if (result != resGO && result != resINTERRUPT)
+    sim->stop(result);
+  return(result);
+}
+
+
+int
+cl_pblaze::exec_inst(void)
+{
+  t_mem code;
+
+  if (fetch(&code))
+    return(resBREAKPOINT);
+
+  tick(1);
+
+  int i = 0;
+  dis_entry_pblaze * disass_pblaze = (type->type == CPU_PBLAZE_3 ? disass_pblaze3 : disass_pblaze6);
+  while (((code & disass_pblaze[i].mask) != disass_pblaze[i].code) && disass_pblaze[i].instruction != BAD_OPCODE) {
+    i++;
+  }
+
+  dis_entry_pblaze instruction = disass_pblaze[i];
+
+    switch (instruction.instruction) {
+        case ADD: return (inst_add(code, instruction.operands));
+        case ADDCY: return (inst_addcy(code, instruction.operands));
+        case AND: return (inst_and(code, instruction.operands));
+        case CALL:
+        case CALL_AT:
+        case CALL_C:
+        case CALL_Z:
+        case CALL_NC:
+        case CALL_NZ:
+          return (inst_call(code, instruction.instruction, instruction.operands));
+        case COMPARE:
+          return (inst_compare(code, instruction.operands));
+        case COMPARECY:
+          return (inst_comparecy(code, instruction.operands));
+        case DISABLE_INTERRUPT:
+          return (inst_interrupt(false));
+        case ENABLE_INTERRUPT:
+          return (inst_interrupt(true));
+        case FETCH:
+          return (inst_fetch(code, instruction.operands));
+        case HWBUILD:
+          return (inst_hwbuild(code, instruction.operands));
+        case IINPUT:
+          return (inst_input(code, instruction.operands));
+        case JUMP:
+        case JUMP_AT:
+        case JUMP_C:
+        case JUMP_NC:
+        case JUMP_NZ:
+        case JUMP_Z:
+          return (inst_jump(code, instruction.instruction, instruction.operands));
+        case LOAD:
+          return (inst_load(code, instruction.operands));
+        case LOAD_RETURN:
+          return (inst_load_return(code, instruction.operands));
+        case OR:
+          return (inst_or(code, instruction.operands));
+        case OUTPUT:
+          return (inst_output(code, instruction.operands));
+        case OUTPUTK:
+          return (inst_outputk(code, instruction.operands));
+        case REGBANK_A:
+          return (inst_regbank(REGISTER_BANK_A));
+        case REGBANK_B:
+          return (inst_regbank(REGISTER_BANK_B));
+        case RETURN:
+        case RETURN_C:
+        case RETURN_NC:
+        case RETURN_NZ:
+        case RETURN_Z:
+          return (inst_return(code, instruction.instruction));
+        case RETURNI_DISABLE:
+          return (inst_returni(false));
+        case RETURNI_ENABLE:
+          return (inst_returni(true));
+        case RL:
+          return (inst_rl(code, instruction.operands));
+        case RR:
+          return (inst_rr(code, instruction.operands));
+        case SL0:
+        case SL1:
+        case SLA:
+        case SLX:
+          return (inst_sl(code, instruction.instruction));
+        case SR0:
+        case SR1:
+        case SRA:
+        case SRX:
+          return (inst_sr(code, instruction.instruction));
+        case STAR:
+          return (inst_star(code, instruction.operands));
+        case STORE:
+          return (inst_store(code, instruction.operands));
+        case SUB:
+          return (inst_sub(code, instruction.operands));
+        case SUBCY:
+          return (inst_subcy(code, instruction.operands));
+        case TEST:
+          return (inst_test(code, instruction.operands));
+        case TESTCY:
+          return (inst_testcy(code, instruction.operands));
+        case XOR:
+          return (inst_xor(code, instruction.operands));
+
+        case BAD_OPCODE:
+        default:
+            break;
+    }
+
+  // this shouldnt be executed. If so, something bad happend in simulated program
+  PC = rom->inc_address(PC, -1);
+
+  sim->stop(resINV_INST);
+  return(resINV_INST);
+}
+
+/*
+ * Checking for interrupt requests and accept one if needed
+ */
+
+int
+cl_pblaze::do_interrupt(void)
+{
+  // is interrupt enabled?
+  if (!FLAGS_GET_I)
+    return(resGO);
+
+  // check in stored interrupts, if at actual cycle irq is set
+  if (find(stored_interrupts.begin(), stored_interrupts.end(), ticks->get_ticks() / clock_per_cycle()) != stored_interrupts.end())
+    interrupt->interrupt_request = true;
+
+  if (interrupt->interrupt_request) {
+    printf("%g sec (%ld clks): Accepting interrupt, PC= 0x%06x\n",
+	   ticks->get_rtime(), (long int)(ticks->get_ticks()), AU(PC));
+
+    tick(1);
+
+    //stack_push(PC);
+    interrupt->preserved_flag_c = FLAGS_GET_C;
+    interrupt->preserved_flag_z = FLAGS_GET_Z;
+    FLAGS_SET_I(0);
+    interrupt->interrupt_request = false;
+
+
+    int res = resERROR;
+
+    if (type->type == CPU_PBLAZE_3)
+      res = inst_call(0x30000 /* isntruction call */ | (interrupt_vector & 0x003ff) /* masked interrupt vector */, CALL, ADDRESS10);
+    else if (type->type == CPU_PBLAZE_6)
+      res = inst_call(0x20000 /* isntruction call */ | (interrupt_vector & 0x00fff) /* masked interrupt vector */, CALL, ADDRESS12);
+
+
+    if (res != resGO)
+      return(res);
+    else
+      return(resINTERRUPT);
+  }
+
+  return(resGO);
+}
+
+
+/*
+ * Converting bit address into real memory
+ */
+
+class cl_address_space *
+cl_pblaze::bit2mem(t_addr bitaddr, t_addr *memaddr, t_mem *bitmask)
+{
+  // bits can be set only for flags C, Z and I simulated in FLAGS (address) register in SFR
+
+  // address in SFR indicates higher byte of bitaddr
+  if (memaddr)
+    *memaddr = bitaddr & 0xf0;
+
+  // bit position indicates lower byte in bitaddr
+  if (bitmask)
+    *bitmask= 1 << (bitaddr & 0xf);
+
+  return sfr;
+}
+
+
+
+
+/* ******
+ * Redefined functions from general uc
+ * ******/
+
+
+static long
+ReadInt(FILE *f, bool *ok, int bytes)
+{
+  char s2[3];
+  long l= 0;
+
+  *ok= false;
+  while (bytes)
+    {
+      if (fscanf(f, "%2c", &s2[0]) == EOF)
+        return(0);
+      s2[2]= '\0';
+      l= l*256 + strtol(s2, NULL, 16);
+      bytes--;
+    }
+  *ok= true;
+  return(l);
+}
+
+static long
+ReadPblazeRomHex(FILE *f, bool *ok)
+{
+  char rec[6];
+  long l= 0;
+
+  *ok= false;
+
+  // read 5 character representim one record (one instruction) in rom
+  if (fscanf(f, "%5c", rec) == EOF)
+    return(0);
+
+  rec[5]= '\0';
+  l= strtol(rec, NULL, 16);
+
+  *ok= true;
+  return(l);
+}
+
+long
+cl_pblaze::read_hex_file(const char *nam)
+{
+  cl_option * opt = sim->app->options->get_option("pblaze_hex");
+  bool value = false;
+  if (opt != NULL) {
+    opt->get_value(&value);
+  }
+
+  long ret;
+  if (value)
+    ret = pblaze_read_hex_file(nam);
+  else
+    ret = std_read_hex_file(nam);
+
+  analyze_init();
+  return ret;
+}
+
+
+long
+cl_pblaze::pblaze_read_hex_file(const char *nam)
+{
+  FILE *f;
+  uint  addr= 0;  // address
+  long written= 0, record = 0;
+  bool ok = true;
+
+  if (!rom)
+    {
+      sim->app->get_commander()->
+        dd_printf("No ROM address space to read in.\n");
+      return(-1);
+    }
+
+  if (!nam)
+    {
+      sim->app->get_commander()->
+        dd_printf("cl_uc::read_hex_file File name not specified\n");
+      return(-1);
+    }
+  else
+    if ((f= fopen(nam, "r")) == NULL)
+      {
+        fprintf(stderr, "Can't open `%s': %s\n", nam, strerror(errno));
+        return(-1);
+      }
+
+  while (ok)
+  {
+    record = ReadPblazeRomHex(f, &ok);
+
+    if (ok) {
+      rom->set(addr, record);
+      addr++;
+      written++;
+
+      // skip unnecesary characters (white space etc)
+      if (fscanf(f, "%*[ \n\r\t]"))
+        {} // if statement only for prevent warning during compilation
+    }
+  }
+
+  // if read wasn't ok and not at the and of file, read error has occurred
+  if (!ok && getc(f) != EOF)
+  {
+      application->debug("Read error in record %ld.\n", written);
+  }
+
+  if (nam)
+    fclose(f);
+  application->debug("%ld records have been read\n", written);
+  return(written);
+}
+
+
+long
+cl_pblaze::std_read_hex_file(const char *nam)
+{
+  FILE *f;
+  int c;
+  long written= 0, recnum= 0;
+
+  uchar dnum;     // data number
+  uchar rtyp=0;   // record type
+  uint  addr= 0;  // address
+  uchar rec[300]; // data record
+  uchar sum ;     // checksum
+  uchar chk ;     // check
+  int  i;
+  bool ok, get_low= 1, get_middle = 0;
+  uchar low= 0, middle=0, high=0;
+
+  if (!rom)
+    {
+      sim->app->get_commander()->
+        dd_printf("No ROM address space to read in.\n");
+      return(-1);
+    }
+
+  if (!nam)
+    {
+      sim->app->get_commander()->
+        dd_printf("cl_uc::read_hex_file File name not specified\n");
+      return(-1);
+    }
+  else
+    if ((f= fopen(nam, "r")) == NULL)
+      {
+        fprintf(stderr, "Can't open `%s': %s\n", nam, strerror(errno));
+        return(-1);
+      }
+
+  //memset(inst_map, '\0', sizeof(inst_map));
+  ok= true;
+  while (ok &&
+         rtyp != 1)
+    {
+      while (((c= getc(f)) != ':') &&
+             (c != EOF)) ;
+      if (c != ':')
+        {fprintf(stderr, ": not found\n");break;}
+      recnum++;
+      dnum= ReadInt(f, &ok, 1);//printf("dnum=%02x",dnum);
+      chk = dnum;
+      addr= ReadInt(f, &ok, 2);//printf("addr=%04x",addr);
+      chk+= (addr & 0xff);
+      chk+= ((addr >> 8) & 0xff);
+      rtyp= ReadInt(f, &ok, 1);//printf("rtyp=%02x ",rtyp);
+      chk+= rtyp;
+      for (i= 0; ok && (i < dnum); i++)
+        {
+          rec[i]= ReadInt(f, &ok, 1);//printf("%02x",rec[i]);
+          chk+= rec[i];
+        }
+      if (ok)
+        {
+          sum= ReadInt(f, &ok, 1);//printf(" sum=%02x\n",sum);
+          if (ok)
+            {
+              if (((sum + chk) & 0xff) == 0)
+                {
+                  if (rtyp == 0)
+                    {
+                      if (rom->width > 8)
+                        addr/= 2;
+                      for (i= 0; i < dnum; i++)
+                        {
+                          if (rom->width <= 8)
+                            {
+                              rom->set(addr, rec[i]);
+                              addr++;
+                              written++;
+                            }
+                          else if (rom->width <= 16)
+                            {
+                              if (get_low)
+                                {
+                                  low= rec[i];
+                                  get_low= 0;
+                                }
+                              else
+                                {
+                                  high= rec[i];
+                                  rom->set(addr, (high*256)+low);
+                                  addr++;
+                                  written++;
+                                  get_low= 1;
+                                }
+                            }
+                          else if (rom->width <= 24)
+                            {
+                              if (get_low)
+                                {
+                                  low= rec[i];
+                                  get_low= 0;
+                                  get_middle = 1;
+                                }
+                              else if (get_middle)
+                                {
+                                    middle = rec[i];
+                                    get_middle = 0;
+                                }
+                              else
+                                {
+                                  high= rec[i];
+                                  rom->set(addr, (high*256*256)+(middle*256)+low);
+                                  addr++;
+                                  written++;
+                                  get_low= 1;
+                                }
+                            }
+                        }
+                    }
+                  else
+                    if (rtyp != 1)
+                      application->debug("Unknown record type %d(0x%x)\n",
+                                         rtyp, rtyp);
+                }
+              else
+                application->debug("Checksum error (%x instead of %x) in "
+                                   "record %ld.\n", chk, sum, recnum);
+            }
+          else
+            application->debug("Read error in record %ld.\n", recnum);
+        }
+    }
+  if (rom->width > 8 &&
+      !get_low)
+    rom->set(addr, low);
+
+  if (nam)
+    fclose(f);
+  application->debug("%ld records have been read\n", recnum);
+  return(written);
+}
+
+
+void
+cl_pblaze::read_interrupt_file(void)
+{
+  cl_option * opt = sim->app->options->get_option("pblaze_interrupt_file");
+  if (opt != NULL) {
+    char *file = 0;
+    opt->get_value(&file);
+
+    TiXmlDocument doc(file);
+
+    if (!doc.LoadFile()) {
+      fprintf(stderr, "Can't open file with interrupts `%s',=.\n", file);
+      return;
+    }
+
+    TiXmlElement *root = doc.FirstChildElement("interrupts");
+    TiXmlElement *element;
+
+    for(element = root->FirstChildElement("interrupt"); element; element = element->NextSiblingElement()) {
+      long interrupt_tick = strtol(element->GetText(), NULL, 0);
+      stored_interrupts.push_back(interrupt_tick);
+    }
+
+    /*
+    char *file = 0;
+    opt->get_value(&file);
+
+    FILE *f;
+    if ((f = fopen(file, "r")) == NULL)
+    {
+      fprintf(stderr, "Can't open file with interrupts `%s': %s\n", file, strerror(errno));
+    }
+    else {
+      while (true)
+      {
+        int i;
+        int res = fscanf(f, "%d", &i);
+        if (res == EOF)
+          break;
+        else if (res == 0) {
+          fprintf(stderr, "Error during reading file with interrupts `%s'\n", file);
+          break;
+        }
+
+        stored_interrupts.insert(i);
+
+        // skip white characters
+        res = fscanf(f, "*[ \n\r\t]");
+      }
+      fclose(f);
+    } */
+  }
+}
+
+void
+cl_pblaze::read_input_file(void)
+{
+  cl_option * opt = sim->app->options->get_option("pblaze_input_file");
+  if (opt != NULL) {
+    char *file = 0;
+    opt->get_value(&file);
+
+    TiXmlDocument doc(file);
+
+    if (!doc.LoadFile()) {
+      fprintf(stderr, "Can't open file with inputs `%s'.\n", file);
+      return;
+    }
+
+    TiXmlElement *root = doc.FirstChildElement("inputs");
+    TiXmlElement *element;
+
+    for(element = root->FirstChildElement("input"); element; element = element->NextSiblingElement()) {
+
+      const char *at_port = element->Attribute("port");
+      int in_port = -1;
+      if (at_port != NULL) {
+        in_port = strtol(at_port, NULL, 0);
+      }
+
+      const char *at_tick = element->Attribute("tick");
+      long in_tick = -1;
+      if (at_tick != NULL) {
+        in_tick = strtol(at_tick, NULL, 0);
+      }
+
+      const char *at_type = element->Attribute("type") != NULL ? element->Attribute("type") : "hex"; // default input type
+
+      const char *input = element->GetText();
+
+      if (strcmp(at_type, "int") == 0) {
+        t_mem value = strtol(input, NULL, 10);
+
+        // set input
+        input_port->add_input(value, in_port, in_tick);
+      }
+      else if (strcmp(at_type, "hex") == 0) {
+        int start = 0;
+        int length = strlen(input);
+
+        while (start < length) {
+          t_mem value;
+          sscanf(input + start, "%2x", &value);
+
+          // if tick is specified, only first value is loaded
+          if (in_tick != -1)
+            break;
+
+          start += 2;
+
+          // set input
+          input_port->add_input(value, in_port, in_tick);
+        }
+      }
+      else if (strcmp(at_type, "char") == 0) {
+        int start = 0;
+        int length = strlen(input);
+
+        while (start < length) {
+          char value;
+          sscanf(input + start, "%1c", &value);
+
+          // if tick is specified, only first value is loaded
+          if (in_tick != -1)
+            break;
+
+          start++;
+
+          // set input
+          input_port->add_input(value, in_port, in_tick);
+        }
+      }
+    }
+  }
+
+  // DEBUG print inputs
+  for(input_port_map::iterator it = input_port->inputs.begin(); it != input_port->inputs.end(); it++) {
+    application->debug("port: %d\n", it->first);
+
+    for(input_tick_map::iterator it_inner = it->second.begin(); it_inner != it->second.end(); it_inner++) {
+      application->debug("\ttick: %ld\n", it_inner->first);
+
+      for(list::iterator it_list = it_inner->second.begin(); it_list != it_inner->second.end(); it_list++) {
+        application->debug("\t\t: %d\n", *it_list);
+      }
+    }
+  }
+
+}
+
+
+
+void
+cl_pblaze::init_uc_parameters(void)
+{
+  // default values
+  active_regbank = REGISTER_BANK_A;
+  rom_size = 1024;
+  ram_size = 64;
+  interrupt_vector = 0x3ff;
+
+  if (type->type == CPU_PBLAZE_3)
+    stack_size = 31;
+  else if (type->type == CPU_PBLAZE_6)
+    stack_size = 30;
+
+  // ram size
+  cl_option * opt = sim->app->options->get_option("pblaze_ram_size");
+  if (opt != NULL) {
+    if (type->type == CPU_PBLAZE_6) {
+      long size = -1;
+      opt->get_value(&size);
+
+      if (size <= 0 || (size != 64 && size != 128 && size != 256))
+      {
+        fprintf(stderr, "Invalid RAM size. Valid values are 64 (default), 128 and 256.\n");
+      }
+      else
+      {
+        ram_size = (unsigned int) size;
+      }
+    }
+    else
+    {
+      fprintf(stderr, "RAM size can be specified only for KCPSM6. Using default size 64b.\n");
+    }
+  }
+
+  // rom size
+  opt = sim->app->options->get_option("pblaze_rom_size");
+  if (opt != NULL) {
+    if (type->type == CPU_PBLAZE_6) {
+      long size = -1;
+      opt->get_value(&size);
+
+      if (size <= 0)
+      {
+        fprintf(stderr, "Invalid ROM size.\n");
+      }
+      else
+      {
+        rom_size = (unsigned int) size;
+      }
+    }
+    else
+    {
+      fprintf(stderr, "ROM size can be specified only for KCPSM6.\n");
+    }
+  }
+
+  // interrupt vector
+  opt = sim->app->options->get_option("pblaze_interrupt_vector");
+  if (opt != NULL) {
+    if (type->type == CPU_PBLAZE_6) {
+      long iv = -1;
+      opt->get_value(&iv);
+
+      if (iv <= 0 || (unsigned int) iv >= rom_size)
+      {
+        fprintf(stderr, "Invalid interrupt vector. %ld\n", iv);
+      }
+      else
+      {
+        interrupt_vector = (unsigned int) iv;
+      }
+    }
+    else
+    {
+      fprintf(stderr, "Interrupt vector can be specified only for KCPSM6.\n");
+    }
+  }
+
+  // built-in hardware constant
+  opt = sim->app->options->get_option("pblaze_hw_const");
+  if (opt != NULL) {
+    if (type->type == CPU_PBLAZE_6) {
+      long value = -1;
+      opt->get_value(&value);
+
+      if (value <= 0 || value >= 256)
+      {
+        fprintf(stderr, "Invalid built-in hardware constant. %ld\n", value);
+      }
+      else
+      {
+        hw_constant = value;
+      }
+    }
+    else
+    {
+      fprintf(stderr, "Built-in hardware constant can be specified only for KCPSM6.\n");
+    }
+  }
+}
+
+
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/pblaze.src/pblazecl.h sdcc-4.2.0+dfsg/sim/ucsim/pblaze.src/pblazecl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/pblaze.src/pblazecl.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/pblaze.src/pblazecl.h	2021-05-20 07:49:29.000000000 +0000
@@ -0,0 +1,119 @@
+/*
+ * Copyright (C) 2012-2013 Jiří Šimek
+ * Copyright (C) 2013 Zbyněk Křivka 
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Library General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Library General Public License for more details.
+ *
+ * You should have received a copy of the GNU Library General Public License
+ * along with this library; see the file COPYING.LIB. If not, write to
+ * the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
+ * Boston, MA 02110-1301, USA.
+ */
+
+
+
+#ifndef PBLAZECL_HEADER
+#define PBLAZECL_HEADER
+
+#include 
+
+#include "uccl.h"
+
+#include "regspblaze.h"
+#include "interruptcl.h"
+#include "portidcl.h"
+#include "inputportcl.h"
+#include "outputportcl.h"
+
+using namespace std;
+
+
+
+
+/*
+ * Base type of PicoBlaze microcontrollers
+ */
+
+class cl_pblaze: public cl_uc
+{
+public:
+ unsigned int ram_size;
+ unsigned int rom_size;
+ unsigned int stack_size;
+ unsigned int interrupt_vector;
+ u8_t hw_constant;
+ int active_regbank;
+
+public:
+  class cl_address_space *ram;
+  class cl_address_space *rom;
+  class cl_address_space *stack;
+  class cl_address_space *sfr;
+
+  // Simulation of interrupt system
+  class cl_interrupt *interrupt;
+  list stored_interrupts;
+
+  class cl_port_id *port_id;
+  class cl_output_port *output_port;
+  class cl_input_port *input_port;
+
+public:
+  cl_pblaze(struct cpu_entry *cputype, class cl_sim *asim);
+  virtual ~cl_pblaze(void);
+  virtual int init(void);
+  virtual const char *id_string(void);
+
+  virtual cl_address_space * bit2mem(t_addr bitaddr, t_addr *memaddr, t_mem *bitmask);
+  virtual t_addr get_mem_size(enum mem_class type);
+  virtual void mk_hw_elements(void);
+  virtual void make_memories(void);
+  virtual void build_cmdset(class cl_cmdset *cmdset);
+
+  virtual long read_hex_file(const char *nam);
+
+  virtual struct dis_entry *dis_tbl(void);
+  virtual struct name_entry *sfr_tbl(void);
+  virtual struct name_entry *bit_tbl(void);
+
+  virtual int clock_per_cycle(void) { return(2); }
+  virtual int inst_length(t_addr addr);
+  virtual int inst_branch(t_addr addr);
+  virtual int longest_inst(void);
+  virtual char *disass(t_addr addr);
+  virtual void print_regs(class cl_console_base *con);
+  virtual void print_state(class cl_console_base *con, char *file_name);
+  virtual void load_state(class cl_console_base *con, char *file_name);
+  virtual void read_interrupt_file(void);
+  virtual void read_input_file(void);
+
+  virtual int do_inst(int step);
+  virtual int exec_inst(void);
+  virtual int do_interrupt(void);
+
+  virtual const char *get_disasm_info(t_addr addr,
+                        int *ret_len,
+                        int *ret_branch,
+                        int *immed_offset);
+
+  virtual void reset(void);
+#include "instcl.h"
+#include "stackcl.h"
+
+private:
+  void init_uc_parameters(void);
+  virtual long std_read_hex_file(const char *nam);
+  virtual long pblaze_read_hex_file(const char *nam);
+
+};
+
+#endif
+
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/pblaze.src/pblazemac.h sdcc-4.2.0+dfsg/sim/ucsim/pblaze.src/pblazemac.h
--- sdcc-4.0.0+dfsg/sim/ucsim/pblaze.src/pblazemac.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/pblaze.src/pblazemac.h	2021-05-11 11:08:48.000000000 +0000
@@ -0,0 +1,47 @@
+/*
+ * Copyright (C) 2012-2013 Jiří Šimek
+ * Copyright (C) 2013 Zbyněk Křivka 
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Library General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Library General Public License for more details.
+ *
+ * You should have received a copy of the GNU Library General Public License
+ * along with this library; see the file COPYING.LIB. If not, write to
+ * the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
+ * Boston, MA 02110-1301, USA.
+ */
+
+
+/*
+#define store2(addr, val) { ram->set((t_addr) (addr), (val >> 8) & 0xff); \
+                            ram->set((t_addr) (addr+1), val & 0xff); }
+#define store1(addr, val) ram->set((t_addr) (addr), val)
+#define get1(addr) ram->get((t_addr) (addr))
+#define get2(addr) ((ram->get((t_addr) (addr)) << 8) | ram->get((t_addr) (addr+1)) )
+#define fetch2() ((fetch() << 8) | fetch() )
+#define fetch1() fetch()
+*
+#define push(val) { stack->set(regs.internal_sp, val); regs.internal_sp = (regs.internal_sp + 1) % 31; }
+#define pop(var) {var = ram->get(regs.internal_sp); regs.SP+=1;}
+
+/
+#define FLAG_SET(f) {regs.P |= f;}
+#define FLAG_CLEAR(f) {regs.P &= ~(f);}
+#define FLAG_ASSIGN(f,c) {regs.P = (c) ? regs.P | (f) : regs.P & ~(f);}
+#define FLAG_NZ(f) { \
+      regs.P = (regs.P & ~(BIT_N|BIT_Z)) \
+      | (((f) & 0xff) ? 0 : BIT_Z) \
+      | (((f) & 0x80) ? BIT_N : 0) \
+      ; }
+#define EA_IMM(c) ((((c) >> 4) & 0xf)==0xa)
+#define OPERAND(code) (EA_IMM(code) ? fetch() : get1(fetchea(code)))
+*/
+
+
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/pblaze.src/pb_pobjt.h sdcc-4.2.0+dfsg/sim/ucsim/pblaze.src/pb_pobjt.h
--- sdcc-4.0.0+dfsg/sim/ucsim/pblaze.src/pb_pobjt.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/pblaze.src/pb_pobjt.h	2021-10-29 17:39:15.000000000 +0000
@@ -0,0 +1,42 @@
+/*
+ * Simulator of microcontrollers (pobjt.h)
+ *
+ * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
+ *
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef POBJT_HEADER
+#define POBJT_HEADER
+
+#include "ddconfig.h"
+
+typedef int	t_index;
+typedef int	(*match_func)(void *, const void *);
+typedef void	(*iterator_func)(void *, void *);
+
+#define max_list_size (0x10000/sizeof(void *))
+#define ccNotFound -1
+
+#endif
+
+/* End of pobjt.h */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/pblaze.src/pb_stypes.h sdcc-4.2.0+dfsg/sim/ucsim/pblaze.src/pb_stypes.h
--- sdcc-4.0.0+dfsg/sim/ucsim/pblaze.src/pb_stypes.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/pblaze.src/pb_stypes.h	2022-01-27 21:35:29.000000000 +0000
@@ -0,0 +1,243 @@
+/*
+ * Simulator of microcontrollers (stypes.h)
+ *
+ * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
+ *
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef STYPES_HEADER
+#define STYPES_HEADER
+
+#include "ddconfig.h"
+
+
+typedef unsigned char	uchar;
+typedef unsigned int	uint;
+typedef unsigned long	ulong;
+typedef TYPE_DWORD	t_addr;		/* 32 bit max */
+typedef TYPE_DWORD	t_mem;		/* 16 bit max */
+typedef TYPE_WORD	t_smem;		/* signed 16 bit memory */
+
+struct id_element
+{
+  int id;
+  const char *id_string;
+};
+
+enum error_type {
+  err_unknown  = 0x01,
+  err_error    = 0x02,
+  err_warning  = 0x04
+};
+
+// table of disassembled instructions
+struct dis_entry
+{
+  uint  code, mask;
+  char  branch;
+  uchar length;
+  const char *mnemonic;
+};
+
+// table entry of SFR and BIT names
+struct name_entry
+{
+  int cpu_type;
+  t_addr addr;
+  const char *name;
+};
+
+
+struct cpu_entry
+{
+  const char *type_str;
+  int  type;
+  int  technology;
+};
+
+#define CPU_51		0x0001
+#define CPU_31		0x0002
+#define CPU_52		0x0004
+#define CPU_32		0x0008
+#define CPU_51R		0x0010
+#define CPU_89C51R	0x0020
+#define CPU_251		0x0040
+#define CPU_DS390	0x0080
+#define CPU_DS390F	0x0100
+#define CPU_ALL_51	(CPU_51|CPU_31)
+#define CPU_ALL_52	(CPU_52|CPU_32|CPU_51R|CPU_89C51R|CPU_251|CPU_DS390|CPU_DS390F)
+
+#define CPU_AVR		0x0001
+#define CPU_ALL_AVR	(CPU_AVR)
+
+#define CPU_Z80		0x0001
+#define CPU_ALL_Z80	(CPU_Z80)
+
+#define CPU_XA		0x0001
+#define CPU_ALL_XA	(CPU_XA)
+
+#define CPU_HC08       0x0001
+#define CPU_ALL_HC08   (CPU_HC08)
+
+#define CPU_PBLAZE_3       0x0001
+#define CPU_PBLAZE_6       0x0002
+#define CPU_ALL_PBLAZE   (CPU_PBLAZE_3|CPU_PBLAZE_6)
+
+#define CPU_CMOS	0x0001
+#define CPU_HMOS	0x0002
+
+/* Classes of memories, this is index on the list */
+enum mem_class
+{
+  MEM_ROM= 0,
+  MEM_XRAM,
+  MEM_IRAM,
+  MEM_SFR,
+  MEM_DUMMY,
+  MEM_IXRAM,
+  MEM_TYPES,
+  MEM_STACK
+};
+
+#define MEM_ROM_ID	"rom"
+#define MEM_SFR_ID	"sfr"
+#define MEM_XRAM_ID	"xram"
+#define MEM_IXRAM_ID	"ixram"
+#define MEM_IRAM_ID	"iram"
+#define MEM_STACK_ID	"stack"
+
+// States of simulator
+#define SIM_NONE	0
+#define SIM_GO		0x01	// Processor is running
+#define SIM_QUIT	0x02	// Program must exit
+
+/* States of CPU */
+#define stGO		0	/* Normal state */
+#define stIDLE		1	/* Idle mode is active */
+#define stPD		2	/* Power Down mode is active */
+
+/* Result of instruction simulation */
+#define resGO		0	/* OK, go on */
+#define resWDTRESET	1	/* Reseted by WDT */
+#define resINTERRUPT	2	/* Interrupt accepted */
+#define resSTOP		100	/* Stop if result greater then this */
+#define resHALT		101	/* Serious error, halt CPU */
+#define resINV_ADDR	102	/* Invalid indirect address */
+#define resSTACK_OV	103	/* Stack overflow */
+#define resBREAKPOINT	104	/* Breakpoint */
+#define resUSER		105	/* Stopped by user */
+#define resINV_INST	106	/* Invalid instruction */
+#define resBITADDR	107	/* Bit address is uninterpretable */
+#define resERROR	108	/* Error happened during instruction exec */
+
+#define BIT_MASK(bitaddr) (1 << (bitaddr & 0x07))
+
+//#define IRAM_SIZE 256	  /* Size of Internal RAM */
+//#define SFR_SIZE  256     /* Size of SFR area */
+//#define SFR_START 128     /* Start address of SFR area */
+//#define ERAM_SIZE 256     /* Size of ERAM in 51R */
+//#define XRAM_SIZE 0x10000 /* Size of External RAM */
+//#define IROM_SIZE 0x1000  /* Size of Internal ROM */
+//#define EROM_SIZE 0x10000 /* Size of External ROM */
+
+
+/* Type of breakpoints */
+enum brk_perm
+{
+  brkFIX,	/* f */
+  brkDYNAMIC	/* d */
+};
+
+enum brk_type
+{
+  brkFETCH,	/* f */
+  brkEVENT	/* e */
+};
+
+enum brk_event
+{
+  brkNONE,
+  brkWXRAM,	/* wx */
+  brkRXRAM,	/* rx */
+  brkRCODE,	/* rc */
+  brkWIRAM,	/* wi */
+  brkRIRAM,	/* ri */
+  brkWSFR,	/* ws */
+  brkRSFR,	/* rs */
+  brkREAD,
+  brkWRITE,
+  brkACCESS
+};
+
+//struct event_rec
+//{
+//  t_addr wx; /* write to XRAM at this address, else -1 */
+//  t_addr rx; /* read from XRAM at this address, else -1 */
+//  t_addr wi; /* write to IRAM at this address, else -1 */
+//  t_addr ri; /* read from IRAM at this address, else -1 */
+//  t_addr ws; /* write to SFR at this address, else -1 */
+//  t_addr rs; /* read from SFR at this address, else -1 */
+//  t_addr rc; /* read from ROM at this address, else -1 */
+//};
+
+/* Interrupt levels */
+//#define IT_NO		-1 /* not in interrupt service */
+#define IT_LOW		1 /* low level interrupt service */
+#define IT_HIGH		2 /* service of high priority interrupt */
+
+/* cathegories of hw elements (peripherials) */
+enum hw_cath {
+  HW_DUMMY	= 0x0000,
+  HW_TIMER	= 0x0002,
+  HW_UART	= 0x0004,
+  HW_PORT	= 0x0008,
+  HW_PCA	= 0x0010,
+  HW_INTERRUPT	= 0x0020,
+  HW_WDT	= 0x0040
+};
+
+// Events that can happen in peripherals
+enum hw_event {
+  EV_OVERFLOW,
+  EV_PORT_CHANGED,
+  EV_T2_MODE_CHANGED
+};
+
+// flags of hw units
+#define HWF_NONE	0
+#define HWF_INSIDE	0x0001
+#define HWF_OUTSIDE	0x0002
+#define HWF_MISC	0x0004
+
+
+/* Letter cases */
+enum letter_case {
+  case_upper,  /* all is upper case */
+  case_lower,  /* all is lower case */
+  case_case    /* first letter is upper, others are lower case */
+};
+
+
+#endif
+
+/* End of stypes.h */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/pblaze.src/portid.cc sdcc-4.2.0+dfsg/sim/ucsim/pblaze.src/portid.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/pblaze.src/portid.cc	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/pblaze.src/portid.cc	2021-05-11 11:08:48.000000000 +0000
@@ -0,0 +1,61 @@
+/*
+ * Copyright (C) 2012-2013 Jiří Šimek
+ * Copyright (C) 2013 Zbyněk Křivka 
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Library General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Library General Public License for more details.
+ *
+ * You should have received a copy of the GNU Library General Public License
+ * along with this library; see the file COPYING.LIB. If not, write to
+ * the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
+ * Boston, MA 02110-1301, USA.
+ */
+
+
+
+// local
+#include "pblazecl.h"
+#include "portidcl.h"
+
+
+
+cl_port_id::cl_port_id(class cl_uc *auc) : cl_hw(auc, HW_PORT, 0, "port_id")
+{
+}
+
+/*
+int
+cl_port::init(void)
+{
+  return(0);
+}
+*/
+
+void
+cl_port_id::set_cmd(class cl_cmdline *cmdline, class cl_console_base *con)
+{
+  class cl_cmd_arg *params[1]= { cmdline->param(0) };
+
+  if (cmdline->syntax_match(uc, NUMBER))
+    {
+      value = params[0]->value.number;
+    }
+  else
+    {
+      con->dd_printf("set hardware port_id[%d] value\n                   Set port id value value\n", id);
+    }
+}
+
+void
+cl_port_id::print_info(class cl_console_base *con)
+{
+  con->dd_printf("Port ID value: %d\n", value);
+}
+
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/pblaze.src/portidcl.h sdcc-4.2.0+dfsg/sim/ucsim/pblaze.src/portidcl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/pblaze.src/portidcl.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/pblaze.src/portidcl.h	2021-05-14 21:19:53.000000000 +0000
@@ -0,0 +1,47 @@
+/*
+ * Copyright (C) 2012-2013 Jiří Šimek
+ * Copyright (C) 2013 Zbyněk Křivka 
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Library General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Library General Public License for more details.
+ *
+ * You should have received a copy of the GNU Library General Public License
+ * along with this library; see the file COPYING.LIB. If not, write to
+ * the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
+ * Boston, MA 02110-1301, USA.
+ */
+
+
+#ifndef PORTIDCL_HEADER
+#define PORTIDCL_HEADER
+
+
+#include "ddconfig.h"
+#include "stypes.h"
+#include "pobjcl.h"
+#include "uccl.h"
+
+
+class cl_port_id: public cl_hw
+{
+  public:
+    u8_t value;
+
+    cl_port_id(class cl_uc *auc);
+    /*virtual int init(void);*/
+    virtual void set_cmd(class cl_cmdline *cmdline, class cl_console_base *con);
+    virtual void print_info(class cl_console_base *con);
+};
+
+
+#endif
+
+
+
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/pblaze.src/regspblaze.h sdcc-4.2.0+dfsg/sim/ucsim/pblaze.src/regspblaze.h
--- sdcc-4.0.0+dfsg/sim/ucsim/pblaze.src/regspblaze.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/pblaze.src/regspblaze.h	2021-05-14 21:19:53.000000000 +0000
@@ -0,0 +1,94 @@
+/*
+ * Copyright (C) 2012-2013 Jiří Šimek
+ * Copyright (C) 2013 Zbyněk Křivka 
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Library General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Library General Public License for more details.
+ *
+ * You should have received a copy of the GNU Library General Public License
+ * along with this library; see the file COPYING.LIB. If not, write to
+ * the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
+ * Boston, MA 02110-1301, USA.
+ */
+
+
+
+#ifndef REGPBLAZE_HEADER
+#define REGPBLAZE_HEADER
+
+#include "ddconfig.h"
+
+#define REGISTER_BANK_A 0x01
+#define REGISTER_BANK_B 0x02
+
+#define FLAGS_GET(bit_position) (sfr->get(FLAGS) & bit_position)
+#define FLAGS_GET_C (sfr->get(FLAGS) & bmC)
+#define FLAGS_GET_Z (sfr->get(FLAGS) & bmZ)
+#define FLAGS_GET_I (sfr->get(FLAGS) & bmI)
+/*
+#define FLAGS_SET(flag_value, bit_position) \
+  if (flag_value) \
+    sfr->set_bit1(FLAGS, bit_position); \
+  else \
+    sfr->set_bit0(FLAGS, bit_position);
+*/
+#define FLAGS_SET(flag_value, bit_position) \
+  if (flag_value) \
+    sfr->write(FLAGS, sfr->read(FLAGS) | bit_position);	\
+  else \
+    sfr->write(FLAGS, sfr->read(FLAGS) & ~bit_position);
+#define FLAGS_SET_C(flag_value) FLAGS_SET(flag_value, bmC)
+#define FLAGS_SET_Z(flag_value) FLAGS_SET(flag_value, bmZ)
+#define FLAGS_SET_I(flag_value) FLAGS_SET(flag_value, bmI)
+
+
+#define S0 0x00
+#define S1 0x01
+#define S2 0x02
+#define S3 0x03
+#define S4 0x04
+#define S5 0x05
+#define S6 0x06
+#define S7 0x07
+#define S8 0x08
+#define S9 0x09
+#define SA 0x0a
+#define SB 0x0b
+#define SC 0x0c
+#define SD 0x0d
+#define SE 0x0e
+#define SF 0x0f
+
+#define S0b 0x10
+#define S1b 0x11
+#define S2b 0x12
+#define S3b 0x13
+#define S4b 0x14
+#define S5b 0x15
+#define S6b 0x16
+#define S7b 0x17
+#define S8b 0x18
+#define S9b 0x19
+#define SAb 0x1a
+#define SBb 0x1b
+#define SCb 0x1c
+#define SDb 0x1d
+#define SEb 0x1e
+#define SFb 0x1f
+
+#define FLAGS 0x20
+#define SP 0x21
+
+// bit position of each flag in FLAGS register
+#define bmC 0x01
+#define bmZ 0x02
+#define bmI 0x04
+
+#endif
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/pblaze.src/simpblaze.cc sdcc-4.2.0+dfsg/sim/ucsim/pblaze.src/simpblaze.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/pblaze.src/simpblaze.cc	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/pblaze.src/simpblaze.cc	2021-10-29 17:39:15.000000000 +0000
@@ -0,0 +1,60 @@
+/*
+ * Copyright (C) 2012-2013 Jiří Šimek
+ * Copyright (C) 2013 Zbyněk Křivka 
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Library General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Library General Public License for more details.
+ *
+ * You should have received a copy of the GNU Library General Public License
+ * along with this library; see the file COPYING.LIB. If not, write to
+ * the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
+ * Boston, MA 02110-1301, USA.
+ */
+
+#include "simpblazecl.h"
+#include "pblazecl.h"
+#include "glob.h"
+
+/**
+ * Contructor
+ */
+cl_simpblaze::cl_simpblaze(class cl_app *the_app):
+  cl_sim(the_app)
+{}
+
+/**
+ * Creates new microcontroller instance
+ */
+class cl_uc *
+cl_simpblaze::mk_controller(void)
+{
+  int i = 0;
+  const char *type= NULL;
+  class cl_optref type_option(this);
+
+  type_option.init();
+  type_option.use("cpu_type");
+
+  if ((type = type_option.get_value(type)) == NULL)
+    type = "KCPSM3"; // default cpu type
+
+  while ((cpus_pblaze[i].type_str != NULL) && (strcmp(type, cpus_pblaze[i].type_str) != 0))
+    i++;
+
+  if (cpus_pblaze[i].type_str == NULL)
+  {
+      fprintf(stderr, "Unknown processor type. "
+	      "Use -H option to see known types.\n");
+
+      return(NULL);
+  }
+
+  return(new cl_pblaze(&cpus_pblaze[i], this));
+}
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/pblaze.src/simpblazecl.h sdcc-4.2.0+dfsg/sim/ucsim/pblaze.src/simpblazecl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/pblaze.src/simpblazecl.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/pblaze.src/simpblazecl.h	2021-05-11 11:08:48.000000000 +0000
@@ -0,0 +1,38 @@
+/*
+ * Copyright (C) 2012-2013 Jiří Šimek
+ * Copyright (C) 2013 Zbyněk Křivka 
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Library General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Library General Public License for more details.
+ *
+ * You should have received a copy of the GNU Library General Public License
+ * along with this library; see the file COPYING.LIB. If not, write to
+ * the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
+ * Boston, MA 02110-1301, USA.
+ */
+
+
+
+#ifndef SIMPBLAZECL_HEADER
+#define SIMPBLAZECL_HEADER
+
+#include "simcl.h"
+
+
+class cl_simpblaze: public cl_sim
+{
+public:
+  cl_simpblaze(class cl_app *the_app);
+
+  virtual class cl_uc *mk_controller(void);
+};
+
+
+#endif
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/pblaze.src/spblaze.cc sdcc-4.2.0+dfsg/sim/ucsim/pblaze.src/spblaze.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/pblaze.src/spblaze.cc	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/pblaze.src/spblaze.cc	2021-05-14 21:19:53.000000000 +0000
@@ -0,0 +1,53 @@
+/*
+ * Copyright (C) 2012-2013 Jiří Šimek
+ * Copyright (C) 2013 Zbyněk Křivka 
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Library General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Library General Public License for more details.
+ *
+ * You should have received a copy of the GNU Library General Public License
+ * along with this library; see the file COPYING.LIB. If not, write to
+ * the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
+ * Boston, MA 02110-1301, USA.
+ */
+
+
+// prj
+#include "appcl.h"
+#include "globals.h"
+
+// sim.src
+//#include "apppblazecl.h"
+
+// local
+#include "simpblazecl.h"
+#include "glob.h"
+
+
+int
+main(int argc, char *argv[])
+{
+  class cl_sim *sim;
+
+  cpus= cpus_pblaze;
+  application= new cl_app();
+  application->init(argc, argv);
+  sim= new cl_simpblaze(application);
+  if (sim->init())
+    return(1);
+
+  application->set_simulator(sim);
+  application->run();
+  delete application;
+  return(0);
+}
+
+
+
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/pblaze.src/stack.cc sdcc-4.2.0+dfsg/sim/ucsim/pblaze.src/stack.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/pblaze.src/stack.cc	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/pblaze.src/stack.cc	2021-05-14 21:19:53.000000000 +0000
@@ -0,0 +1,65 @@
+/*
+ * Copyright (C) 2012-2013 Jiří Šimek
+ * Copyright (C) 2013 Zbyněk Křivka 
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Library General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Library General Public License for more details.
+ *
+ * You should have received a copy of the GNU Library General Public License
+ * along with this library; see the file COPYING.LIB. If not, write to
+ * the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
+ * Boston, MA 02110-1301, USA.
+ */
+
+#include 
+/*
+#include "ddconfig.h"
+#include "glob.h"*/
+#include "pblazecl.h"
+//#include "regspblaze.h"
+
+
+/* returns true if stack overflows */
+bool
+cl_pblaze::stack_push(u32_t value) {
+  cl_memory_cell *sp = sfr->get_cell(SP);
+  int sp_value = sp->get();
+
+  stack->set(sp_value, value);
+
+  sp_value++;
+  sp->set(sp_value % 31);
+
+  if (sp_value > 30)
+    return true;
+  else
+    return false;
+}
+
+/* returns true if stack underflows */
+bool
+cl_pblaze::stack_pop(u32_t *value) {
+  cl_memory_cell *sp = sfr->get_cell(SP);
+  int sp_value = sp->get();
+
+  if (sp_value == 0)
+    sp_value = 30;
+  else
+    sp_value--;
+
+  sp->set(sp_value);
+
+  *value = stack->get(sp_value);
+
+  if (sp_value == 30)
+    return true;
+  else
+    return false;
+}
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/pblaze.src/stackcl.h sdcc-4.2.0+dfsg/sim/ucsim/pblaze.src/stackcl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/pblaze.src/stackcl.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/pblaze.src/stackcl.h	2021-05-14 21:19:53.000000000 +0000
@@ -0,0 +1,23 @@
+/*
+ * Copyright (C) 2012-2013 Jiří Šimek
+ * Copyright (C) 2013 Zbyněk Křivka 
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Library General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Library General Public License for more details.
+ *
+ * You should have received a copy of the GNU Library General Public License
+ * along with this library; see the file COPYING.LIB. If not, write to
+ * the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
+ * Boston, MA 02110-1301, USA.
+ */
+
+
+virtual bool stack_push(u32_t value);
+virtual bool stack_pop(u32_t *value);
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/pblaze.src/test/clean.mk sdcc-4.2.0+dfsg/sim/ucsim/pblaze.src/test/clean.mk
--- sdcc-4.0.0+dfsg/sim/ucsim/pblaze.src/test/clean.mk	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/pblaze.src/test/clean.mk	2021-05-11 11:08:48.000000000 +0000
@@ -0,0 +1,5 @@
+clean:
+
+distclean:
+	rm -f Makefile
+	find . -type d -name out -exec rm -rf {} \;
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/pblaze.src/test/config/baseline/KCPSM3 sdcc-4.2.0+dfsg/sim/ucsim/pblaze.src/test/config/baseline/KCPSM3
--- sdcc-4.0.0+dfsg/sim/ucsim/pblaze.src/test/config/baseline/KCPSM3	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/pblaze.src/test/config/baseline/KCPSM3	2022-02-08 21:21:05.000000000 +0000
@@ -0,0 +1,51 @@
+uCsim, Copyright (C)  Daniel Drotos.
+uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+This is free software, and you are welcome to redistribute it
+under certain conditions; type `show c' for details.
+Type of microcontroller: KCPSM3 fpga
+Controller has 7 hardware element(s).
+   on simif[0]
+  off vcd[0]
+   on dreg[0]
+  off irq[0]
+   on port_id[0]
+   on output_port[0]
+   on input_port[0]
+S0= 0x08   8 .
+S1= 0x70 112 p
+S2= 0xd4 212 .
+S3= 0xb2 178 .
+S4= 0x8a 138 .
+S5= 0x29  41 )
+S6= 0x54  84 T
+S7= 0x48  72 H
+S8= 0x9a 154 .
+S9= 0x0a  10 .
+Sa= 0xbc 188 .
+Sb= 0xd5 213 .
+Sc= 0x0e  14 .
+Sd= 0x18  24 .
+Se= 0xa8 168 .
+Sf= 0x44  68 D
+PC= 0x000000
+SP= 0x000000
+C= 0, Z= 0, I= 0
+0x000  ? 19e7f BAD_OPCODE[0K
+Memory chips:
+  0x000000-0x0000ff      256 variable_storage (32,%08x,0x%02lx)
+  0x000000-0x000021       34 sfr_chip (8,%02x,0x%02lx)
+  0x000000-0x0003ff     1024 rom_chip (18,%05x,0x%03lx)
+  0x000000-0x00003f       64 ram_chip (8,%02x,0x%02lx)
+  0x000000-0x00001e       31 stack_chip (12,%03x,0x%02lx)
+Address spaces:
+  0x000000-0x0000ff      256 variables (32,%08x,0x%02lx)
+  0x000000-0x000021       34 sfr (8,%02x,0x%02lx)
+  0x000000-0x0003ff     1024 rom (18,%05x,0x%03lx)
+  0x000000-0x00003f       64 iram (8,%02x,0x%02lx)
+  0x000000-0x00001e       31 stack (12,%03x,0x%02lx)
+Address decoders:
+  variables 0x00 0xff -> variable_storage 0x00 activated
+  sfr 0x00 0x21 -> sfr_chip 0x00 activated
+  rom 0x000 0x3ff -> rom_chip 0x000 activated
+  iram 0x00 0x3f -> ram_chip 0x00 activated
+  stack 0x00 0x1e -> stack_chip 0x00 activated
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/pblaze.src/test/config/baseline/KCPSM6 sdcc-4.2.0+dfsg/sim/ucsim/pblaze.src/test/config/baseline/KCPSM6
--- sdcc-4.0.0+dfsg/sim/ucsim/pblaze.src/test/config/baseline/KCPSM6	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/pblaze.src/test/config/baseline/KCPSM6	2022-02-08 21:21:05.000000000 +0000
@@ -0,0 +1,70 @@
+uCsim, Copyright (C)  Daniel Drotos.
+uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+This is free software, and you are welcome to redistribute it
+under certain conditions; type `show c' for details.
+Type of microcontroller: KCPSM6 fpga
+Controller has 7 hardware element(s).
+   on simif[0]
+  off vcd[0]
+   on dreg[0]
+  off irq[0]
+   on port_id[0]
+   on output_port[0]
+   on input_port[0]
+Regbank A
+S0= 0x08   8 .
+S1= 0x70 112 p
+S2= 0xd4 212 .
+S3= 0xb2 178 .
+S4= 0x8a 138 .
+S5= 0x29  41 )
+S6= 0x54  84 T
+S7= 0x48  72 H
+S8= 0x9a 154 .
+S9= 0x0a  10 .
+Sa= 0xbc 188 .
+Sb= 0xd5 213 .
+Sc= 0x0e  14 .
+Sd= 0x18  24 .
+Se= 0xa8 168 .
+Sf= 0x44  68 D
+Regbank B
+S10= 0xac 172 .
+S11= 0x5b  91 [
+S12= 0xf3 243 .
+S13= 0x8e 142 .
+S14= 0x4c  76 L
+S15= 0xd7 215 .
+S16= 0x2d  45 -
+S17= 0x9b 155 .
+S18= 0x09   9 .
+S19= 0x42  66 B
+S1a= 0xe5 229 .
+S1b= 0x06   6 .
+S1c= 0xc4 196 .
+S1d= 0x33  51 3
+S1e= 0xaf 175 .
+S1f= 0xcd 205 .
+Active regbank= A
+PC= 0x000000
+SP= 0x000000
+C= 0, Z= 0, I= 0
+0x000  ? 19e7f SUB    se,0x7f[0K
+Memory chips:
+  0x000000-0x0000ff      256 variable_storage (32,%08x,0x%02lx)
+  0x000000-0x000021       34 sfr_chip (8,%02x,0x%02lx)
+  0x000000-0x0003ff     1024 rom_chip (18,%05x,0x%03lx)
+  0x000000-0x00003f       64 ram_chip (8,%02x,0x%02lx)
+  0x000000-0x00001d       30 stack_chip (12,%03x,0x%02lx)
+Address spaces:
+  0x000000-0x0000ff      256 variables (32,%08x,0x%02lx)
+  0x000000-0x000021       34 sfr (8,%02x,0x%02lx)
+  0x000000-0x0003ff     1024 rom (18,%05x,0x%03lx)
+  0x000000-0x00003f       64 iram (8,%02x,0x%02lx)
+  0x000000-0x00001d       30 stack (12,%03x,0x%02lx)
+Address decoders:
+  variables 0x00 0xff -> variable_storage 0x00 activated
+  sfr 0x00 0x21 -> sfr_chip 0x00 activated
+  rom 0x000 0x3ff -> rom_chip 0x000 activated
+  iram 0x00 0x3f -> ram_chip 0x00 activated
+  stack 0x00 0x1d -> stack_chip 0x00 activated
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/pblaze.src/test/config/Makefile sdcc-4.2.0+dfsg/sim/ucsim/pblaze.src/test/config/Makefile
--- sdcc-4.0.0+dfsg/sim/ucsim/pblaze.src/test/config/Makefile	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/pblaze.src/test/config/Makefile	2021-05-20 07:49:29.000000000 +0000
@@ -0,0 +1,8 @@
+OUTPUTS = $(filter-out Parameter, $(shell $(SIM) -H | sort -u -k2b | cut -d' ' -f1))
+
+
+$(OUTPUTS):
+	$(call run-sim, -t $(@F) -e 'conf; info reg; info mem')
+
+
+include test-lib.mk
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/pblaze.src/test/Makefile.in sdcc-4.2.0+dfsg/sim/ucsim/pblaze.src/test/Makefile.in
--- sdcc-4.0.0+dfsg/sim/ucsim/pblaze.src/test/Makefile.in	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/pblaze.src/test/Makefile.in	2021-05-11 11:08:48.000000000 +0000
@@ -0,0 +1,9 @@
+# @configure_input@
+
+srcdir           = @abs_srcdir@
+
+abs_top_builddir = @abs_top_builddir@
+abs_top_srcdir   = @abs_top_srcdir@
+
+
+include $(abs_top_srcdir)/test-target.mk
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/pblaze.src/tinystr.cpp sdcc-4.2.0+dfsg/sim/ucsim/pblaze.src/tinystr.cpp
--- sdcc-4.0.0+dfsg/sim/ucsim/pblaze.src/tinystr.cpp	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/pblaze.src/tinystr.cpp	2021-05-11 11:08:48.000000000 +0000
@@ -0,0 +1,111 @@
+/*
+www.sourceforge.net/projects/tinyxml
+
+This software is provided 'as-is', without any express or implied
+warranty. In no event will the authors be held liable for any
+damages arising from the use of this software.
+
+Permission is granted to anyone to use this software for any
+purpose, including commercial applications, and to alter it and
+redistribute it freely, subject to the following restrictions:
+
+1. The origin of this software must not be misrepresented; you must
+not claim that you wrote the original software. If you use this
+software in a product, an acknowledgment in the product documentation
+would be appreciated but is not required.
+
+2. Altered source versions must be plainly marked as such, and
+must not be misrepresented as being the original software.
+
+3. This notice may not be removed or altered from any source
+distribution.
+*/
+
+
+#ifndef TIXML_USE_STL
+
+#include "tinystr.h"
+
+// Error value for find primitive
+const TiXmlString::size_type TiXmlString::npos = static_cast< TiXmlString::size_type >(-1);
+
+
+// Null rep.
+TiXmlString::Rep TiXmlString::nullrep_ = { 0, 0, { '\0' } };
+
+
+void TiXmlString::reserve (size_type cap)
+{
+	if (cap > capacity())
+	{
+		TiXmlString tmp;
+		tmp.init(length(), cap);
+		memcpy(tmp.start(), data(), length());
+		swap(tmp);
+	}
+}
+
+
+TiXmlString& TiXmlString::assign(const char* str, size_type len)
+{
+	size_type cap = capacity();
+	if (len > cap || cap > 3*(len + 8))
+	{
+		TiXmlString tmp;
+		tmp.init(len);
+		memcpy(tmp.start(), str, len);
+		swap(tmp);
+	}
+	else
+	{
+		memmove(start(), str, len);
+		set_size(len);
+	}
+	return *this;
+}
+
+
+TiXmlString& TiXmlString::append(const char* str, size_type len)
+{
+	size_type newsize = length() + len;
+	if (newsize > capacity())
+	{
+		reserve (newsize + capacity());
+	}
+	memmove(finish(), str, len);
+	set_size(newsize);
+	return *this;
+}
+
+
+TiXmlString operator + (const TiXmlString & a, const TiXmlString & b)
+{
+	TiXmlString tmp;
+	tmp.reserve(a.length() + b.length());
+	tmp += a;
+	tmp += b;
+	return tmp;
+}
+
+TiXmlString operator + (const TiXmlString & a, const char* b)
+{
+	TiXmlString tmp;
+	TiXmlString::size_type b_len = static_cast( strlen(b) );
+	tmp.reserve(a.length() + b_len);
+	tmp += a;
+	tmp.append(b, b_len);
+	return tmp;
+}
+
+TiXmlString operator + (const char* a, const TiXmlString & b)
+{
+	TiXmlString tmp;
+	TiXmlString::size_type a_len = static_cast( strlen(a) );
+	tmp.reserve(a_len + b.length());
+	tmp.append(a, a_len);
+	tmp += b;
+	return tmp;
+}
+
+
+#endif	// TIXML_USE_STL
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/pblaze.src/tinystr.h sdcc-4.2.0+dfsg/sim/ucsim/pblaze.src/tinystr.h
--- sdcc-4.0.0+dfsg/sim/ucsim/pblaze.src/tinystr.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/pblaze.src/tinystr.h	2021-05-11 11:08:48.000000000 +0000
@@ -0,0 +1,305 @@
+/*
+www.sourceforge.net/projects/tinyxml
+
+This software is provided 'as-is', without any express or implied
+warranty. In no event will the authors be held liable for any
+damages arising from the use of this software.
+
+Permission is granted to anyone to use this software for any
+purpose, including commercial applications, and to alter it and
+redistribute it freely, subject to the following restrictions:
+
+1. The origin of this software must not be misrepresented; you must
+not claim that you wrote the original software. If you use this
+software in a product, an acknowledgment in the product documentation
+would be appreciated but is not required.
+
+2. Altered source versions must be plainly marked as such, and
+must not be misrepresented as being the original software.
+
+3. This notice may not be removed or altered from any source
+distribution.
+*/
+
+
+#ifndef TIXML_USE_STL
+
+#ifndef TIXML_STRING_INCLUDED
+#define TIXML_STRING_INCLUDED
+
+#include 
+#include 
+
+/*	The support for explicit isn't that universal, and it isn't really
+	required - it is used to check that the TiXmlString class isn't incorrectly
+	used. Be nice to old compilers and macro it here:
+*/
+#if defined(_MSC_VER) && (_MSC_VER >= 1200 )
+	// Microsoft visual studio, version 6 and higher.
+	#define TIXML_EXPLICIT explicit
+#elif defined(__GNUC__) && (__GNUC__ >= 3 )
+	// GCC version 3 and higher.s
+	#define TIXML_EXPLICIT explicit
+#else
+	#define TIXML_EXPLICIT
+#endif
+
+
+/*
+   TiXmlString is an emulation of a subset of the std::string template.
+   Its purpose is to allow compiling TinyXML on compilers with no or poor STL support.
+   Only the member functions relevant to the TinyXML project have been implemented.
+   The buffer allocation is made by a simplistic power of 2 like mechanism : if we increase
+   a string and there's no more room, we allocate a buffer twice as big as we need.
+*/
+class TiXmlString
+{
+  public :
+	// The size type used
+  	typedef size_t size_type;
+
+	// Error value for find primitive
+	static const size_type npos; // = -1;
+
+
+	// TiXmlString empty constructor
+	TiXmlString () : rep_(&nullrep_)
+	{
+	}
+
+	// TiXmlString copy constructor
+	TiXmlString ( const TiXmlString & copy) : rep_(0)
+	{
+		init(copy.length());
+		memcpy(start(), copy.data(), length());
+	}
+
+	// TiXmlString constructor, based on a string
+	TIXML_EXPLICIT TiXmlString ( const char * copy) : rep_(0)
+	{
+		init( static_cast( strlen(copy) ));
+		memcpy(start(), copy, length());
+	}
+
+	// TiXmlString constructor, based on a string
+	TIXML_EXPLICIT TiXmlString ( const char * str, size_type len) : rep_(0)
+	{
+		init(len);
+		memcpy(start(), str, len);
+	}
+
+	// TiXmlString destructor
+	~TiXmlString ()
+	{
+		quit();
+	}
+
+	TiXmlString& operator = (const char * copy)
+	{
+		return assign( copy, (size_type)strlen(copy));
+	}
+
+	TiXmlString& operator = (const TiXmlString & copy)
+	{
+		return assign(copy.start(), copy.length());
+	}
+
+
+	// += operator. Maps to append
+	TiXmlString& operator += (const char * suffix)
+	{
+		return append(suffix, static_cast( strlen(suffix) ));
+	}
+
+	// += operator. Maps to append
+	TiXmlString& operator += (char single)
+	{
+		return append(&single, 1);
+	}
+
+	// += operator. Maps to append
+	TiXmlString& operator += (const TiXmlString & suffix)
+	{
+		return append(suffix.data(), suffix.length());
+	}
+
+
+	// Convert a TiXmlString into a null-terminated char *
+	const char * c_str () const { return rep_->str; }
+
+	// Convert a TiXmlString into a char * (need not be null terminated).
+	const char * data () const { return rep_->str; }
+
+	// Return the length of a TiXmlString
+	size_type length () const { return rep_->size; }
+
+	// Alias for length()
+	size_type size () const { return rep_->size; }
+
+	// Checks if a TiXmlString is empty
+	bool empty () const { return rep_->size == 0; }
+
+	// Return capacity of string
+	size_type capacity () const { return rep_->capacity; }
+
+
+	// single char extraction
+	const char& at (size_type index) const
+	{
+		assert( index < length() );
+		return rep_->str[ index ];
+	}
+
+	// [] operator
+	char& operator [] (size_type index) const
+	{
+		assert( index < length() );
+		return rep_->str[ index ];
+	}
+
+	// find a char in a string. Return TiXmlString::npos if not found
+	size_type find (char lookup) const
+	{
+		return find(lookup, 0);
+	}
+
+	// find a char in a string from an offset. Return TiXmlString::npos if not found
+	size_type find (char tofind, size_type offset) const
+	{
+		if (offset >= length()) return npos;
+
+		for (const char* p = c_str() + offset; *p != '\0'; ++p)
+		{
+		   if (*p == tofind) return static_cast< size_type >( p - c_str() );
+		}
+		return npos;
+	}
+
+	void clear ()
+	{
+		//Lee:
+		//The original was just too strange, though correct:
+		//	TiXmlString().swap(*this);
+		//Instead use the quit & re-init:
+		quit();
+		init(0,0);
+	}
+
+	/*	Function to reserve a big amount of data when we know we'll need it. Be aware that this
+		function DOES NOT clear the content of the TiXmlString if any exists.
+	*/
+	void reserve (size_type cap);
+
+	TiXmlString& assign (const char* str, size_type len);
+
+	TiXmlString& append (const char* str, size_type len);
+
+	void swap (TiXmlString& other)
+	{
+		Rep* r = rep_;
+		rep_ = other.rep_;
+		other.rep_ = r;
+	}
+
+  private:
+
+	void init(size_type sz) { init(sz, sz); }
+	void set_size(size_type sz) { rep_->str[ rep_->size = sz ] = '\0'; }
+	char* start() const { return rep_->str; }
+	char* finish() const { return rep_->str + rep_->size; }
+
+	struct Rep
+	{
+		size_type size, capacity;
+		char str[1];
+	};
+
+	void init(size_type sz, size_type cap)
+	{
+		if (cap)
+		{
+			// Lee: the original form:
+			//	rep_ = static_cast(operator new(sizeof(Rep) + cap));
+			// doesn't work in some cases of new being overloaded. Switching
+			// to the normal allocation, although use an 'int' for systems
+			// that are overly picky about structure alignment.
+			const size_type bytesNeeded = sizeof(Rep) + cap;
+			const size_type intsNeeded = ( bytesNeeded + sizeof(int) - 1 ) / sizeof( int ); 
+			rep_ = reinterpret_cast( new int[ intsNeeded ] );
+
+			rep_->str[ rep_->size = sz ] = '\0';
+			rep_->capacity = cap;
+		}
+		else
+		{
+			rep_ = &nullrep_;
+		}
+	}
+
+	void quit()
+	{
+		if (rep_ != &nullrep_)
+		{
+			// The rep_ is really an array of ints. (see the allocator, above).
+			// Cast it back before delete, so the compiler won't incorrectly call destructors.
+			delete [] ( reinterpret_cast( rep_ ) );
+		}
+	}
+
+	Rep * rep_;
+	static Rep nullrep_;
+
+} ;
+
+
+inline bool operator == (const TiXmlString & a, const TiXmlString & b)
+{
+	return    ( a.length() == b.length() )				// optimization on some platforms
+	       && ( strcmp(a.c_str(), b.c_str()) == 0 );	// actual compare
+}
+inline bool operator < (const TiXmlString & a, const TiXmlString & b)
+{
+	return strcmp(a.c_str(), b.c_str()) < 0;
+}
+
+inline bool operator != (const TiXmlString & a, const TiXmlString & b) { return !(a == b); }
+inline bool operator >  (const TiXmlString & a, const TiXmlString & b) { return b < a; }
+inline bool operator <= (const TiXmlString & a, const TiXmlString & b) { return !(b < a); }
+inline bool operator >= (const TiXmlString & a, const TiXmlString & b) { return !(a < b); }
+
+inline bool operator == (const TiXmlString & a, const char* b) { return strcmp(a.c_str(), b) == 0; }
+inline bool operator == (const char* a, const TiXmlString & b) { return b == a; }
+inline bool operator != (const TiXmlString & a, const char* b) { return !(a == b); }
+inline bool operator != (const char* a, const TiXmlString & b) { return !(b == a); }
+
+TiXmlString operator + (const TiXmlString & a, const TiXmlString & b);
+TiXmlString operator + (const TiXmlString & a, const char* b);
+TiXmlString operator + (const char* a, const TiXmlString & b);
+
+
+/*
+   TiXmlOutStream is an emulation of std::ostream. It is based on TiXmlString.
+   Only the operators that we need for TinyXML have been developped.
+*/
+class TiXmlOutStream : public TiXmlString
+{
+public :
+
+	// TiXmlOutStream << operator.
+	TiXmlOutStream & operator << (const TiXmlString & in)
+	{
+		*this += in;
+		return *this;
+	}
+
+	// TiXmlOutStream << operator.
+	TiXmlOutStream & operator << (const char * in)
+	{
+		*this += in;
+		return *this;
+	}
+
+} ;
+
+#endif	// TIXML_STRING_INCLUDED
+#endif	// TIXML_USE_STL
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/pblaze.src/tinyxml.cpp sdcc-4.2.0+dfsg/sim/ucsim/pblaze.src/tinyxml.cpp
--- sdcc-4.0.0+dfsg/sim/ucsim/pblaze.src/tinyxml.cpp	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/pblaze.src/tinyxml.cpp	2021-05-11 11:08:48.000000000 +0000
@@ -0,0 +1,1886 @@
+/*
+www.sourceforge.net/projects/tinyxml
+Original code by Lee Thomason (www.grinninglizard.com)
+
+This software is provided 'as-is', without any express or implied
+warranty. In no event will the authors be held liable for any
+damages arising from the use of this software.
+
+Permission is granted to anyone to use this software for any
+purpose, including commercial applications, and to alter it and
+redistribute it freely, subject to the following restrictions:
+
+1. The origin of this software must not be misrepresented; you must
+not claim that you wrote the original software. If you use this
+software in a product, an acknowledgment in the product documentation
+would be appreciated but is not required.
+
+2. Altered source versions must be plainly marked as such, and
+must not be misrepresented as being the original software.
+
+3. This notice may not be removed or altered from any source
+distribution.
+*/
+
+#include 
+
+#ifdef TIXML_USE_STL
+#include 
+#include 
+#endif
+
+#include "tinyxml.h"
+
+FILE* TiXmlFOpen( const char* filename, const char* mode );
+
+bool TiXmlBase::condenseWhiteSpace = true;
+
+// Microsoft compiler security
+FILE* TiXmlFOpen( const char* filename, const char* mode )
+{
+	#if defined(_MSC_VER) && (_MSC_VER >= 1400 )
+		FILE* fp = 0;
+		errno_t err = fopen_s( &fp, filename, mode );
+		if ( !err && fp )
+			return fp;
+		return 0;
+	#else
+		return fopen( filename, mode );
+	#endif
+}
+
+void TiXmlBase::EncodeString( const TIXML_STRING& str, TIXML_STRING* outString )
+{
+	int i=0;
+
+	while( i<(int)str.length() )
+	{
+		unsigned char c = (unsigned char) str[i];
+
+		if (    c == '&' 
+		     && i < ( (int)str.length() - 2 )
+			 && str[i+1] == '#'
+			 && str[i+2] == 'x' )
+		{
+			// Hexadecimal character reference.
+			// Pass through unchanged.
+			// ©	-- copyright symbol, for example.
+			//
+			// The -1 is a bug fix from Rob Laveaux. It keeps
+			// an overflow from happening if there is no ';'.
+			// There are actually 2 ways to exit this loop -
+			// while fails (error case) and break (semicolon found).
+			// However, there is no mechanism (currently) for
+			// this function to return an error.
+			while ( i<(int)str.length()-1 )
+			{
+				outString->append( str.c_str() + i, 1 );
+				++i;
+				if ( str[i] == ';' )
+					break;
+			}
+		}
+		else if ( c == '&' )
+		{
+			outString->append( entity[0].str, entity[0].strLength );
+			++i;
+		}
+		else if ( c == '<' )
+		{
+			outString->append( entity[1].str, entity[1].strLength );
+			++i;
+		}
+		else if ( c == '>' )
+		{
+			outString->append( entity[2].str, entity[2].strLength );
+			++i;
+		}
+		else if ( c == '\"' )
+		{
+			outString->append( entity[3].str, entity[3].strLength );
+			++i;
+		}
+		else if ( c == '\'' )
+		{
+			outString->append( entity[4].str, entity[4].strLength );
+			++i;
+		}
+		else if ( c < 32 )
+		{
+			// Easy pass at non-alpha/numeric/symbol
+			// Below 32 is symbolic.
+			char buf[ 32 ];
+			
+			#if defined(TIXML_SNPRINTF)		
+				TIXML_SNPRINTF( buf, sizeof(buf), "&#x%02X;", (unsigned) ( c & 0xff ) );
+			#else
+				sprintf( buf, "&#x%02X;", (unsigned) ( c & 0xff ) );
+			#endif		
+
+			//*ME:	warning C4267: convert 'size_t' to 'int'
+			//*ME:	Int-Cast to make compiler happy ...
+			outString->append( buf, (int)strlen( buf ) );
+			++i;
+		}
+		else
+		{
+			//char realc = (char) c;
+			//outString->append( &realc, 1 );
+			*outString += (char) c;	// somewhat more efficient function call.
+			++i;
+		}
+	}
+}
+
+
+TiXmlNode::TiXmlNode( NodeType _type ) : TiXmlBase()
+{
+	parent = 0;
+	type = _type;
+	firstChild = 0;
+	lastChild = 0;
+	prev = 0;
+	next = 0;
+}
+
+
+TiXmlNode::~TiXmlNode()
+{
+	TiXmlNode* node = firstChild;
+	TiXmlNode* temp = 0;
+
+	while ( node )
+	{
+		temp = node;
+		node = node->next;
+		delete temp;
+	}	
+}
+
+
+void TiXmlNode::CopyTo( TiXmlNode* target ) const
+{
+	target->SetValue (value.c_str() );
+	target->userData = userData; 
+	target->location = location;
+}
+
+
+void TiXmlNode::Clear()
+{
+	TiXmlNode* node = firstChild;
+	TiXmlNode* temp = 0;
+
+	while ( node )
+	{
+		temp = node;
+		node = node->next;
+		delete temp;
+	}	
+
+	firstChild = 0;
+	lastChild = 0;
+}
+
+
+TiXmlNode* TiXmlNode::LinkEndChild( TiXmlNode* node )
+{
+	assert( node->parent == 0 || node->parent == this );
+	assert( node->GetDocument() == 0 || node->GetDocument() == this->GetDocument() );
+
+	if ( node->Type() == TiXmlNode::TINYXML_DOCUMENT )
+	{
+		delete node;
+		if ( GetDocument() ) 
+			GetDocument()->SetError( TIXML_ERROR_DOCUMENT_TOP_ONLY, 0, 0, TIXML_ENCODING_UNKNOWN );
+		return 0;
+	}
+
+	node->parent = this;
+
+	node->prev = lastChild;
+	node->next = 0;
+
+	if ( lastChild )
+		lastChild->next = node;
+	else
+		firstChild = node;			// it was an empty list.
+
+	lastChild = node;
+	return node;
+}
+
+
+TiXmlNode* TiXmlNode::InsertEndChild( const TiXmlNode& addThis )
+{
+	if ( addThis.Type() == TiXmlNode::TINYXML_DOCUMENT )
+	{
+		if ( GetDocument() ) 
+			GetDocument()->SetError( TIXML_ERROR_DOCUMENT_TOP_ONLY, 0, 0, TIXML_ENCODING_UNKNOWN );
+		return 0;
+	}
+	TiXmlNode* node = addThis.Clone();
+	if ( !node )
+		return 0;
+
+	return LinkEndChild( node );
+}
+
+
+TiXmlNode* TiXmlNode::InsertBeforeChild( TiXmlNode* beforeThis, const TiXmlNode& addThis )
+{	
+	if ( !beforeThis || beforeThis->parent != this ) {
+		return 0;
+	}
+	if ( addThis.Type() == TiXmlNode::TINYXML_DOCUMENT )
+	{
+		if ( GetDocument() ) 
+			GetDocument()->SetError( TIXML_ERROR_DOCUMENT_TOP_ONLY, 0, 0, TIXML_ENCODING_UNKNOWN );
+		return 0;
+	}
+
+	TiXmlNode* node = addThis.Clone();
+	if ( !node )
+		return 0;
+	node->parent = this;
+
+	node->next = beforeThis;
+	node->prev = beforeThis->prev;
+	if ( beforeThis->prev )
+	{
+		beforeThis->prev->next = node;
+	}
+	else
+	{
+		assert( firstChild == beforeThis );
+		firstChild = node;
+	}
+	beforeThis->prev = node;
+	return node;
+}
+
+
+TiXmlNode* TiXmlNode::InsertAfterChild( TiXmlNode* afterThis, const TiXmlNode& addThis )
+{
+	if ( !afterThis || afterThis->parent != this ) {
+		return 0;
+	}
+	if ( addThis.Type() == TiXmlNode::TINYXML_DOCUMENT )
+	{
+		if ( GetDocument() ) 
+			GetDocument()->SetError( TIXML_ERROR_DOCUMENT_TOP_ONLY, 0, 0, TIXML_ENCODING_UNKNOWN );
+		return 0;
+	}
+
+	TiXmlNode* node = addThis.Clone();
+	if ( !node )
+		return 0;
+	node->parent = this;
+
+	node->prev = afterThis;
+	node->next = afterThis->next;
+	if ( afterThis->next )
+	{
+		afterThis->next->prev = node;
+	}
+	else
+	{
+		assert( lastChild == afterThis );
+		lastChild = node;
+	}
+	afterThis->next = node;
+	return node;
+}
+
+
+TiXmlNode* TiXmlNode::ReplaceChild( TiXmlNode* replaceThis, const TiXmlNode& withThis )
+{
+	if ( !replaceThis )
+		return 0;
+
+	if ( replaceThis->parent != this )
+		return 0;
+
+	if ( withThis.ToDocument() ) {
+		// A document can never be a child.	Thanks to Noam.
+		TiXmlDocument* document = GetDocument();
+		if ( document ) 
+			document->SetError( TIXML_ERROR_DOCUMENT_TOP_ONLY, 0, 0, TIXML_ENCODING_UNKNOWN );
+		return 0;
+	}
+
+	TiXmlNode* node = withThis.Clone();
+	if ( !node )
+		return 0;
+
+	node->next = replaceThis->next;
+	node->prev = replaceThis->prev;
+
+	if ( replaceThis->next )
+		replaceThis->next->prev = node;
+	else
+		lastChild = node;
+
+	if ( replaceThis->prev )
+		replaceThis->prev->next = node;
+	else
+		firstChild = node;
+
+	delete replaceThis;
+	node->parent = this;
+	return node;
+}
+
+
+bool TiXmlNode::RemoveChild( TiXmlNode* removeThis )
+{
+	if ( !removeThis ) {
+		return false;
+	}
+
+	if ( removeThis->parent != this )
+	{	
+		assert( 0 );
+		return false;
+	}
+
+	if ( removeThis->next )
+		removeThis->next->prev = removeThis->prev;
+	else
+		lastChild = removeThis->prev;
+
+	if ( removeThis->prev )
+		removeThis->prev->next = removeThis->next;
+	else
+		firstChild = removeThis->next;
+
+	delete removeThis;
+	return true;
+}
+
+const TiXmlNode* TiXmlNode::FirstChild( const char * _value ) const
+{
+	const TiXmlNode* node;
+	for ( node = firstChild; node; node = node->next )
+	{
+		if ( strcmp( node->Value(), _value ) == 0 )
+			return node;
+	}
+	return 0;
+}
+
+
+const TiXmlNode* TiXmlNode::LastChild( const char * _value ) const
+{
+	const TiXmlNode* node;
+	for ( node = lastChild; node; node = node->prev )
+	{
+		if ( strcmp( node->Value(), _value ) == 0 )
+			return node;
+	}
+	return 0;
+}
+
+
+const TiXmlNode* TiXmlNode::IterateChildren( const TiXmlNode* previous ) const
+{
+	if ( !previous )
+	{
+		return FirstChild();
+	}
+	else
+	{
+		assert( previous->parent == this );
+		return previous->NextSibling();
+	}
+}
+
+
+const TiXmlNode* TiXmlNode::IterateChildren( const char * val, const TiXmlNode* previous ) const
+{
+	if ( !previous )
+	{
+		return FirstChild( val );
+	}
+	else
+	{
+		assert( previous->parent == this );
+		return previous->NextSibling( val );
+	}
+}
+
+
+const TiXmlNode* TiXmlNode::NextSibling( const char * _value ) const 
+{
+	const TiXmlNode* node;
+	for ( node = next; node; node = node->next )
+	{
+		if ( strcmp( node->Value(), _value ) == 0 )
+			return node;
+	}
+	return 0;
+}
+
+
+const TiXmlNode* TiXmlNode::PreviousSibling( const char * _value ) const
+{
+	const TiXmlNode* node;
+	for ( node = prev; node; node = node->prev )
+	{
+		if ( strcmp( node->Value(), _value ) == 0 )
+			return node;
+	}
+	return 0;
+}
+
+
+void TiXmlElement::RemoveAttribute( const char * name )
+{
+    #ifdef TIXML_USE_STL
+	TIXML_STRING str( name );
+	TiXmlAttribute* node = attributeSet.Find( str );
+	#else
+	TiXmlAttribute* node = attributeSet.Find( name );
+	#endif
+	if ( node )
+	{
+		attributeSet.Remove( node );
+		delete node;
+	}
+}
+
+const TiXmlElement* TiXmlNode::FirstChildElement() const
+{
+	const TiXmlNode* node;
+
+	for (	node = FirstChild();
+			node;
+			node = node->NextSibling() )
+	{
+		if ( node->ToElement() )
+			return node->ToElement();
+	}
+	return 0;
+}
+
+
+const TiXmlElement* TiXmlNode::FirstChildElement( const char * _value ) const
+{
+	const TiXmlNode* node;
+
+	for (	node = FirstChild( _value );
+			node;
+			node = node->NextSibling( _value ) )
+	{
+		if ( node->ToElement() )
+			return node->ToElement();
+	}
+	return 0;
+}
+
+
+const TiXmlElement* TiXmlNode::NextSiblingElement() const
+{
+	const TiXmlNode* node;
+
+	for (	node = NextSibling();
+			node;
+			node = node->NextSibling() )
+	{
+		if ( node->ToElement() )
+			return node->ToElement();
+	}
+	return 0;
+}
+
+
+const TiXmlElement* TiXmlNode::NextSiblingElement( const char * _value ) const
+{
+	const TiXmlNode* node;
+
+	for (	node = NextSibling( _value );
+			node;
+			node = node->NextSibling( _value ) )
+	{
+		if ( node->ToElement() )
+			return node->ToElement();
+	}
+	return 0;
+}
+
+
+const TiXmlDocument* TiXmlNode::GetDocument() const
+{
+	const TiXmlNode* node;
+
+	for( node = this; node; node = node->parent )
+	{
+		if ( node->ToDocument() )
+			return node->ToDocument();
+	}
+	return 0;
+}
+
+
+TiXmlElement::TiXmlElement (const char * _value)
+	: TiXmlNode( TiXmlNode::TINYXML_ELEMENT )
+{
+	firstChild = lastChild = 0;
+	value = _value;
+}
+
+
+#ifdef TIXML_USE_STL
+TiXmlElement::TiXmlElement( const std::string& _value ) 
+	: TiXmlNode( TiXmlNode::TINYXML_ELEMENT )
+{
+	firstChild = lastChild = 0;
+	value = _value;
+}
+#endif
+
+
+TiXmlElement::TiXmlElement( const TiXmlElement& copy)
+	: TiXmlNode( TiXmlNode::TINYXML_ELEMENT )
+{
+	firstChild = lastChild = 0;
+	copy.CopyTo( this );	
+}
+
+
+TiXmlElement& TiXmlElement::operator=( const TiXmlElement& base )
+{
+	ClearThis();
+	base.CopyTo( this );
+	return *this;
+}
+
+
+TiXmlElement::~TiXmlElement()
+{
+	ClearThis();
+}
+
+
+void TiXmlElement::ClearThis()
+{
+	Clear();
+	while( attributeSet.First() )
+	{
+		TiXmlAttribute* node = attributeSet.First();
+		attributeSet.Remove( node );
+		delete node;
+	}
+}
+
+
+const char* TiXmlElement::Attribute( const char* name ) const
+{
+	const TiXmlAttribute* node = attributeSet.Find( name );
+	if ( node )
+		return node->Value();
+	return 0;
+}
+
+
+#ifdef TIXML_USE_STL
+const std::string* TiXmlElement::Attribute( const std::string& name ) const
+{
+	const TiXmlAttribute* attrib = attributeSet.Find( name );
+	if ( attrib )
+		return &attrib->ValueStr();
+	return 0;
+}
+#endif
+
+
+const char* TiXmlElement::Attribute( const char* name, int* i ) const
+{
+	const TiXmlAttribute* attrib = attributeSet.Find( name );
+	const char* result = 0;
+
+	if ( attrib ) {
+		result = attrib->Value();
+		if ( i ) {
+			attrib->QueryIntValue( i );
+		}
+	}
+	return result;
+}
+
+
+#ifdef TIXML_USE_STL
+const std::string* TiXmlElement::Attribute( const std::string& name, int* i ) const
+{
+	const TiXmlAttribute* attrib = attributeSet.Find( name );
+	const std::string* result = 0;
+
+	if ( attrib ) {
+		result = &attrib->ValueStr();
+		if ( i ) {
+			attrib->QueryIntValue( i );
+		}
+	}
+	return result;
+}
+#endif
+
+
+const char* TiXmlElement::Attribute( const char* name, double* d ) const
+{
+	const TiXmlAttribute* attrib = attributeSet.Find( name );
+	const char* result = 0;
+
+	if ( attrib ) {
+		result = attrib->Value();
+		if ( d ) {
+			attrib->QueryDoubleValue( d );
+		}
+	}
+	return result;
+}
+
+
+#ifdef TIXML_USE_STL
+const std::string* TiXmlElement::Attribute( const std::string& name, double* d ) const
+{
+	const TiXmlAttribute* attrib = attributeSet.Find( name );
+	const std::string* result = 0;
+
+	if ( attrib ) {
+		result = &attrib->ValueStr();
+		if ( d ) {
+			attrib->QueryDoubleValue( d );
+		}
+	}
+	return result;
+}
+#endif
+
+
+int TiXmlElement::QueryIntAttribute( const char* name, int* ival ) const
+{
+	const TiXmlAttribute* attrib = attributeSet.Find( name );
+	if ( !attrib )
+		return TIXML_NO_ATTRIBUTE;
+	return attrib->QueryIntValue( ival );
+}
+
+
+int TiXmlElement::QueryUnsignedAttribute( const char* name, unsigned* value ) const
+{
+	const TiXmlAttribute* node = attributeSet.Find( name );
+	if ( !node )
+		return TIXML_NO_ATTRIBUTE;
+
+	int ival = 0;
+	int result = node->QueryIntValue( &ival );
+	*value = (unsigned)ival;
+	return result;
+}
+
+
+int TiXmlElement::QueryBoolAttribute( const char* name, bool* bval ) const
+{
+	const TiXmlAttribute* node = attributeSet.Find( name );
+	if ( !node )
+		return TIXML_NO_ATTRIBUTE;
+	
+	int result = TIXML_WRONG_TYPE;
+	if (    StringEqual( node->Value(), "true", true, TIXML_ENCODING_UNKNOWN ) 
+		 || StringEqual( node->Value(), "yes", true, TIXML_ENCODING_UNKNOWN ) 
+		 || StringEqual( node->Value(), "1", true, TIXML_ENCODING_UNKNOWN ) ) 
+	{
+		*bval = true;
+		result = TIXML_SUCCESS;
+	}
+	else if (    StringEqual( node->Value(), "false", true, TIXML_ENCODING_UNKNOWN ) 
+			  || StringEqual( node->Value(), "no", true, TIXML_ENCODING_UNKNOWN ) 
+			  || StringEqual( node->Value(), "0", true, TIXML_ENCODING_UNKNOWN ) ) 
+	{
+		*bval = false;
+		result = TIXML_SUCCESS;
+	}
+	return result;
+}
+
+
+
+#ifdef TIXML_USE_STL
+int TiXmlElement::QueryIntAttribute( const std::string& name, int* ival ) const
+{
+	const TiXmlAttribute* attrib = attributeSet.Find( name );
+	if ( !attrib )
+		return TIXML_NO_ATTRIBUTE;
+	return attrib->QueryIntValue( ival );
+}
+#endif
+
+
+int TiXmlElement::QueryDoubleAttribute( const char* name, double* dval ) const
+{
+	const TiXmlAttribute* attrib = attributeSet.Find( name );
+	if ( !attrib )
+		return TIXML_NO_ATTRIBUTE;
+	return attrib->QueryDoubleValue( dval );
+}
+
+
+#ifdef TIXML_USE_STL
+int TiXmlElement::QueryDoubleAttribute( const std::string& name, double* dval ) const
+{
+	const TiXmlAttribute* attrib = attributeSet.Find( name );
+	if ( !attrib )
+		return TIXML_NO_ATTRIBUTE;
+	return attrib->QueryDoubleValue( dval );
+}
+#endif
+
+
+void TiXmlElement::SetAttribute( const char * name, int val )
+{	
+	TiXmlAttribute* attrib = attributeSet.FindOrCreate( name );
+	if ( attrib ) {
+		attrib->SetIntValue( val );
+	}
+}
+
+
+#ifdef TIXML_USE_STL
+void TiXmlElement::SetAttribute( const std::string& name, int val )
+{	
+	TiXmlAttribute* attrib = attributeSet.FindOrCreate( name );
+	if ( attrib ) {
+		attrib->SetIntValue( val );
+	}
+}
+#endif
+
+
+void TiXmlElement::SetDoubleAttribute( const char * name, double val )
+{	
+	TiXmlAttribute* attrib = attributeSet.FindOrCreate( name );
+	if ( attrib ) {
+		attrib->SetDoubleValue( val );
+	}
+}
+
+
+#ifdef TIXML_USE_STL
+void TiXmlElement::SetDoubleAttribute( const std::string& name, double val )
+{	
+	TiXmlAttribute* attrib = attributeSet.FindOrCreate( name );
+	if ( attrib ) {
+		attrib->SetDoubleValue( val );
+	}
+}
+#endif 
+
+
+void TiXmlElement::SetAttribute( const char * cname, const char * cvalue )
+{
+	TiXmlAttribute* attrib = attributeSet.FindOrCreate( cname );
+	if ( attrib ) {
+		attrib->SetValue( cvalue );
+	}
+}
+
+
+#ifdef TIXML_USE_STL
+void TiXmlElement::SetAttribute( const std::string& _name, const std::string& _value )
+{
+	TiXmlAttribute* attrib = attributeSet.FindOrCreate( _name );
+	if ( attrib ) {
+		attrib->SetValue( _value );
+	}
+}
+#endif
+
+
+void TiXmlElement::Print( FILE* cfile, int depth ) const
+{
+	int i;
+	assert( cfile );
+	for ( i=0; iNext() )
+	{
+		fprintf( cfile, " " );
+		attrib->Print( cfile, depth );
+	}
+
+	// There are 3 different formatting approaches:
+	// 1) An element without children is printed as a  node
+	// 2) An element with only a text child is printed as  text 
+	// 3) An element with children is printed on multiple lines.
+	TiXmlNode* node;
+	if ( !firstChild )
+	{
+		fprintf( cfile, " />" );
+	}
+	else if ( firstChild == lastChild && firstChild->ToText() )
+	{
+		fprintf( cfile, ">" );
+		firstChild->Print( cfile, depth + 1 );
+		fprintf( cfile, "", value.c_str() );
+	}
+	else
+	{
+		fprintf( cfile, ">" );
+
+		for ( node = firstChild; node; node=node->NextSibling() )
+		{
+			if ( !node->ToText() )
+			{
+				fprintf( cfile, "\n" );
+			}
+			node->Print( cfile, depth+1 );
+		}
+		fprintf( cfile, "\n" );
+		for( i=0; i", value.c_str() );
+	}
+}
+
+
+void TiXmlElement::CopyTo( TiXmlElement* target ) const
+{
+	// superclass:
+	TiXmlNode::CopyTo( target );
+
+	// Element class: 
+	// Clone the attributes, then clone the children.
+	const TiXmlAttribute* attribute = 0;
+	for(	attribute = attributeSet.First();
+	attribute;
+	attribute = attribute->Next() )
+	{
+		target->SetAttribute( attribute->Name(), attribute->Value() );
+	}
+
+	TiXmlNode* node = 0;
+	for ( node = firstChild; node; node = node->NextSibling() )
+	{
+		target->LinkEndChild( node->Clone() );
+	}
+}
+
+bool TiXmlElement::Accept( TiXmlVisitor* visitor ) const
+{
+	if ( visitor->VisitEnter( *this, attributeSet.First() ) ) 
+	{
+		for ( const TiXmlNode* node=FirstChild(); node; node=node->NextSibling() )
+		{
+			if ( !node->Accept( visitor ) )
+				break;
+		}
+	}
+	return visitor->VisitExit( *this );
+}
+
+
+TiXmlNode* TiXmlElement::Clone() const
+{
+	TiXmlElement* clone = new TiXmlElement( Value() );
+	if ( !clone )
+		return 0;
+
+	CopyTo( clone );
+	return clone;
+}
+
+
+const char* TiXmlElement::GetText() const
+{
+	const TiXmlNode* child = this->FirstChild();
+	if ( child ) {
+		const TiXmlText* childText = child->ToText();
+		if ( childText ) {
+			return childText->Value();
+		}
+	}
+	return 0;
+}
+
+
+TiXmlDocument::TiXmlDocument() : TiXmlNode( TiXmlNode::TINYXML_DOCUMENT )
+{
+	tabsize = 4;
+	useMicrosoftBOM = false;
+	ClearError();
+}
+
+TiXmlDocument::TiXmlDocument( const char * documentName ) : TiXmlNode( TiXmlNode::TINYXML_DOCUMENT )
+{
+	tabsize = 4;
+	useMicrosoftBOM = false;
+	value = documentName;
+	ClearError();
+}
+
+
+#ifdef TIXML_USE_STL
+TiXmlDocument::TiXmlDocument( const std::string& documentName ) : TiXmlNode( TiXmlNode::TINYXML_DOCUMENT )
+{
+	tabsize = 4;
+	useMicrosoftBOM = false;
+    value = documentName;
+	ClearError();
+}
+#endif
+
+
+TiXmlDocument::TiXmlDocument( const TiXmlDocument& copy ) : TiXmlNode( TiXmlNode::TINYXML_DOCUMENT )
+{
+	copy.CopyTo( this );
+}
+
+
+TiXmlDocument& TiXmlDocument::operator=( const TiXmlDocument& copy )
+{
+	Clear();
+	copy.CopyTo( this );
+	return *this;
+}
+
+
+bool TiXmlDocument::LoadFile( TiXmlEncoding encoding )
+{
+	return LoadFile( Value(), encoding );
+}
+
+
+bool TiXmlDocument::SaveFile() const
+{
+	return SaveFile( Value() );
+}
+
+bool TiXmlDocument::LoadFile( const char* _filename, TiXmlEncoding encoding )
+{
+	TIXML_STRING filename( _filename );
+	value = filename;
+
+	// reading in binary mode so that tinyxml can normalize the EOL
+	FILE* file = TiXmlFOpen( value.c_str (), "rb" );	
+
+	if ( file )
+	{
+		bool result = LoadFile( file, encoding );
+		fclose( file );
+		return result;
+	}
+	else
+	{
+		SetError( TIXML_ERROR_OPENING_FILE, 0, 0, TIXML_ENCODING_UNKNOWN );
+		return false;
+	}
+}
+
+bool TiXmlDocument::LoadFile( FILE* file, TiXmlEncoding encoding )
+{
+	if ( !file ) 
+	{
+		SetError( TIXML_ERROR_OPENING_FILE, 0, 0, TIXML_ENCODING_UNKNOWN );
+		return false;
+	}
+
+	// Delete the existing data:
+	Clear();
+	location.Clear();
+
+	// Get the file size, so we can pre-allocate the string. HUGE speed impact.
+	long length = 0;
+	fseek( file, 0, SEEK_END );
+	length = ftell( file );
+	fseek( file, 0, SEEK_SET );
+
+	// Strange case, but good to handle up front.
+	if ( length <= 0 )
+	{
+		SetError( TIXML_ERROR_DOCUMENT_EMPTY, 0, 0, TIXML_ENCODING_UNKNOWN );
+		return false;
+	}
+
+	// Subtle bug here. TinyXml did use fgets. But from the XML spec:
+	// 2.11 End-of-Line Handling
+	// 
+	// 
+	// ...the XML processor MUST behave as if it normalized all line breaks in external 
+	// parsed entities (including the document entity) on input, before parsing, by translating 
+	// both the two-character sequence #xD #xA and any #xD that is not followed by #xA to 
+	// a single #xA character.
+	// 
+	//
+	// It is not clear fgets does that, and certainly isn't clear it works cross platform. 
+	// Generally, you expect fgets to translate from the convention of the OS to the c/unix
+	// convention, and not work generally.
+
+	/*
+	while( fgets( buf, sizeof(buf), file ) )
+	{
+		data += buf;
+	}
+	*/
+
+	char* buf = new char[ length+1 ];
+	buf[0] = 0;
+
+	if ( fread( buf, length, 1, file ) != 1 ) {
+		delete [] buf;
+		SetError( TIXML_ERROR_OPENING_FILE, 0, 0, TIXML_ENCODING_UNKNOWN );
+		return false;
+	}
+
+	// Process the buffer in place to normalize new lines. (See comment above.)
+	// Copies from the 'p' to 'q' pointer, where p can advance faster if
+	// a newline-carriage return is hit.
+	//
+	// Wikipedia:
+	// Systems based on ASCII or a compatible character set use either LF  (Line feed, '\n', 0x0A, 10 in decimal) or 
+	// CR (Carriage return, '\r', 0x0D, 13 in decimal) individually, or CR followed by LF (CR+LF, 0x0D 0x0A)...
+	//		* LF:    Multics, Unix and Unix-like systems (GNU/Linux, AIX, Xenix, Mac OS X, FreeBSD, etc.), BeOS, Amiga, RISC OS, and others
+    //		* CR+LF: DEC RT-11 and most other early non-Unix, non-IBM OSes, CP/M, MP/M, DOS, OS/2, Microsoft Windows, Symbian OS
+    //		* CR:    Commodore 8-bit machines, Apple II family, Mac OS up to version 9 and OS-9
+
+	const char* p = buf;	// the read head
+	char* q = buf;			// the write head
+	const char CR = 0x0d;
+	const char LF = 0x0a;
+
+	buf[length] = 0;
+	while( *p ) {
+		assert( p < (buf+length) );
+		assert( q <= (buf+length) );
+		assert( q <= p );
+
+		if ( *p == CR ) {
+			*q++ = LF;
+			p++;
+			if ( *p == LF ) {		// check for CR+LF (and skip LF)
+				p++;
+			}
+		}
+		else {
+			*q++ = *p++;
+		}
+	}
+	assert( q <= (buf+length) );
+	*q = 0;
+
+	Parse( buf, 0, encoding );
+
+	delete [] buf;
+	return !Error();
+}
+
+
+bool TiXmlDocument::SaveFile( const char * filename ) const
+{
+	// The old c stuff lives on...
+	FILE* fp = TiXmlFOpen( filename, "w" );
+	if ( fp )
+	{
+		bool result = SaveFile( fp );
+		fclose( fp );
+		return result;
+	}
+	return false;
+}
+
+
+bool TiXmlDocument::SaveFile( FILE* fp ) const
+{
+	if ( useMicrosoftBOM ) 
+	{
+		const unsigned char TIXML_UTF_LEAD_0 = 0xefU;
+		const unsigned char TIXML_UTF_LEAD_1 = 0xbbU;
+		const unsigned char TIXML_UTF_LEAD_2 = 0xbfU;
+
+		fputc( TIXML_UTF_LEAD_0, fp );
+		fputc( TIXML_UTF_LEAD_1, fp );
+		fputc( TIXML_UTF_LEAD_2, fp );
+	}
+	Print( fp, 0 );
+	return (ferror(fp) == 0);
+}
+
+
+void TiXmlDocument::CopyTo( TiXmlDocument* target ) const
+{
+	TiXmlNode::CopyTo( target );
+
+	target->error = error;
+	target->errorId = errorId;
+	target->errorDesc = errorDesc;
+	target->tabsize = tabsize;
+	target->errorLocation = errorLocation;
+	target->useMicrosoftBOM = useMicrosoftBOM;
+
+	TiXmlNode* node = 0;
+	for ( node = firstChild; node; node = node->NextSibling() )
+	{
+		target->LinkEndChild( node->Clone() );
+	}	
+}
+
+
+TiXmlNode* TiXmlDocument::Clone() const
+{
+	TiXmlDocument* clone = new TiXmlDocument();
+	if ( !clone )
+		return 0;
+
+	CopyTo( clone );
+	return clone;
+}
+
+
+void TiXmlDocument::Print( FILE* cfile, int depth ) const
+{
+	assert( cfile );
+	for ( const TiXmlNode* node=FirstChild(); node; node=node->NextSibling() )
+	{
+		node->Print( cfile, depth );
+		fprintf( cfile, "\n" );
+	}
+}
+
+
+bool TiXmlDocument::Accept( TiXmlVisitor* visitor ) const
+{
+	if ( visitor->VisitEnter( *this ) )
+	{
+		for ( const TiXmlNode* node=FirstChild(); node; node=node->NextSibling() )
+		{
+			if ( !node->Accept( visitor ) )
+				break;
+		}
+	}
+	return visitor->VisitExit( *this );
+}
+
+
+const TiXmlAttribute* TiXmlAttribute::Next() const
+{
+	// We are using knowledge of the sentinel. The sentinel
+	// have a value or name.
+	if ( next->value.empty() && next->name.empty() )
+		return 0;
+	return next;
+}
+
+/*
+TiXmlAttribute* TiXmlAttribute::Next()
+{
+	// We are using knowledge of the sentinel. The sentinel
+	// have a value or name.
+	if ( next->value.empty() && next->name.empty() )
+		return 0;
+	return next;
+}
+*/
+
+const TiXmlAttribute* TiXmlAttribute::Previous() const
+{
+	// We are using knowledge of the sentinel. The sentinel
+	// have a value or name.
+	if ( prev->value.empty() && prev->name.empty() )
+		return 0;
+	return prev;
+}
+
+/*
+TiXmlAttribute* TiXmlAttribute::Previous()
+{
+	// We are using knowledge of the sentinel. The sentinel
+	// have a value or name.
+	if ( prev->value.empty() && prev->name.empty() )
+		return 0;
+	return prev;
+}
+*/
+
+void TiXmlAttribute::Print( FILE* cfile, int /*depth*/, TIXML_STRING* str ) const
+{
+	TIXML_STRING n, v;
+
+	EncodeString( name, &n );
+	EncodeString( value, &v );
+
+	if (value.find ('\"') == TIXML_STRING::npos) {
+		if ( cfile ) {
+			fprintf (cfile, "%s=\"%s\"", n.c_str(), v.c_str() );
+		}
+		if ( str ) {
+			(*str) += n; (*str) += "=\""; (*str) += v; (*str) += "\"";
+		}
+	}
+	else {
+		if ( cfile ) {
+			fprintf (cfile, "%s='%s'", n.c_str(), v.c_str() );
+		}
+		if ( str ) {
+			(*str) += n; (*str) += "='"; (*str) += v; (*str) += "'";
+		}
+	}
+}
+
+
+int TiXmlAttribute::QueryIntValue( int* ival ) const
+{
+	if ( TIXML_SSCANF( value.c_str(), "%d", ival ) == 1 )
+		return TIXML_SUCCESS;
+	return TIXML_WRONG_TYPE;
+}
+
+int TiXmlAttribute::QueryDoubleValue( double* dval ) const
+{
+	if ( TIXML_SSCANF( value.c_str(), "%lf", dval ) == 1 )
+		return TIXML_SUCCESS;
+	return TIXML_WRONG_TYPE;
+}
+
+void TiXmlAttribute::SetIntValue( int _value )
+{
+	char buf [64];
+	#if defined(TIXML_SNPRINTF)		
+		TIXML_SNPRINTF(buf, sizeof(buf), "%d", _value);
+	#else
+		sprintf (buf, "%d", _value);
+	#endif
+	SetValue (buf);
+}
+
+void TiXmlAttribute::SetDoubleValue( double _value )
+{
+	char buf [256];
+	#if defined(TIXML_SNPRINTF)		
+		TIXML_SNPRINTF( buf, sizeof(buf), "%g", _value);
+	#else
+		sprintf (buf, "%g", _value);
+	#endif
+	SetValue (buf);
+}
+
+int TiXmlAttribute::IntValue() const
+{
+	return atoi (value.c_str ());
+}
+
+double  TiXmlAttribute::DoubleValue() const
+{
+	return atof (value.c_str ());
+}
+
+
+TiXmlComment::TiXmlComment( const TiXmlComment& copy ) : TiXmlNode( TiXmlNode::TINYXML_COMMENT )
+{
+	copy.CopyTo( this );
+}
+
+
+TiXmlComment& TiXmlComment::operator=( const TiXmlComment& base )
+{
+	Clear();
+	base.CopyTo( this );
+	return *this;
+}
+
+
+void TiXmlComment::Print( FILE* cfile, int depth ) const
+{
+	assert( cfile );
+	for ( int i=0; i", value.c_str() );
+}
+
+
+void TiXmlComment::CopyTo( TiXmlComment* target ) const
+{
+	TiXmlNode::CopyTo( target );
+}
+
+
+bool TiXmlComment::Accept( TiXmlVisitor* visitor ) const
+{
+	return visitor->Visit( *this );
+}
+
+
+TiXmlNode* TiXmlComment::Clone() const
+{
+	TiXmlComment* clone = new TiXmlComment();
+
+	if ( !clone )
+		return 0;
+
+	CopyTo( clone );
+	return clone;
+}
+
+
+void TiXmlText::Print( FILE* cfile, int depth ) const
+{
+	assert( cfile );
+	if ( cdata )
+	{
+		int i;
+		fprintf( cfile, "\n" );
+		for ( i=0; i\n", value.c_str() );	// unformatted output
+	}
+	else
+	{
+		TIXML_STRING buffer;
+		EncodeString( value, &buffer );
+		fprintf( cfile, "%s", buffer.c_str() );
+	}
+}
+
+
+void TiXmlText::CopyTo( TiXmlText* target ) const
+{
+	TiXmlNode::CopyTo( target );
+	target->cdata = cdata;
+}
+
+
+bool TiXmlText::Accept( TiXmlVisitor* visitor ) const
+{
+	return visitor->Visit( *this );
+}
+
+
+TiXmlNode* TiXmlText::Clone() const
+{	
+	TiXmlText* clone = 0;
+	clone = new TiXmlText( "" );
+
+	if ( !clone )
+		return 0;
+
+	CopyTo( clone );
+	return clone;
+}
+
+
+TiXmlDeclaration::TiXmlDeclaration( const char * _version,
+									const char * _encoding,
+									const char * _standalone )
+	: TiXmlNode( TiXmlNode::TINYXML_DECLARATION )
+{
+	version = _version;
+	encoding = _encoding;
+	standalone = _standalone;
+}
+
+
+#ifdef TIXML_USE_STL
+TiXmlDeclaration::TiXmlDeclaration(	const std::string& _version,
+									const std::string& _encoding,
+									const std::string& _standalone )
+	: TiXmlNode( TiXmlNode::TINYXML_DECLARATION )
+{
+	version = _version;
+	encoding = _encoding;
+	standalone = _standalone;
+}
+#endif
+
+
+TiXmlDeclaration::TiXmlDeclaration( const TiXmlDeclaration& copy )
+	: TiXmlNode( TiXmlNode::TINYXML_DECLARATION )
+{
+	copy.CopyTo( this );	
+}
+
+
+TiXmlDeclaration& TiXmlDeclaration::operator=( const TiXmlDeclaration& copy )
+{
+	Clear();
+	copy.CopyTo( this );
+	return *this;
+}
+
+
+void TiXmlDeclaration::Print( FILE* cfile, int /*depth*/, TIXML_STRING* str ) const
+{
+	if ( cfile ) fprintf( cfile, "" );
+	if ( str )	 (*str) += "?>";
+}
+
+
+void TiXmlDeclaration::CopyTo( TiXmlDeclaration* target ) const
+{
+	TiXmlNode::CopyTo( target );
+
+	target->version = version;
+	target->encoding = encoding;
+	target->standalone = standalone;
+}
+
+
+bool TiXmlDeclaration::Accept( TiXmlVisitor* visitor ) const
+{
+	return visitor->Visit( *this );
+}
+
+
+TiXmlNode* TiXmlDeclaration::Clone() const
+{	
+	TiXmlDeclaration* clone = new TiXmlDeclaration();
+
+	if ( !clone )
+		return 0;
+
+	CopyTo( clone );
+	return clone;
+}
+
+
+void TiXmlUnknown::Print( FILE* cfile, int depth ) const
+{
+	for ( int i=0; i", value.c_str() );
+}
+
+
+void TiXmlUnknown::CopyTo( TiXmlUnknown* target ) const
+{
+	TiXmlNode::CopyTo( target );
+}
+
+
+bool TiXmlUnknown::Accept( TiXmlVisitor* visitor ) const
+{
+	return visitor->Visit( *this );
+}
+
+
+TiXmlNode* TiXmlUnknown::Clone() const
+{
+	TiXmlUnknown* clone = new TiXmlUnknown();
+
+	if ( !clone )
+		return 0;
+
+	CopyTo( clone );
+	return clone;
+}
+
+
+TiXmlAttributeSet::TiXmlAttributeSet()
+{
+	sentinel.next = &sentinel;
+	sentinel.prev = &sentinel;
+}
+
+
+TiXmlAttributeSet::~TiXmlAttributeSet()
+{
+	assert( sentinel.next == &sentinel );
+	assert( sentinel.prev == &sentinel );
+}
+
+
+void TiXmlAttributeSet::Add( TiXmlAttribute* addMe )
+{
+    #ifdef TIXML_USE_STL
+	assert( !Find( TIXML_STRING( addMe->Name() ) ) );	// Shouldn't be multiply adding to the set.
+	#else
+	assert( !Find( addMe->Name() ) );	// Shouldn't be multiply adding to the set.
+	#endif
+
+	addMe->next = &sentinel;
+	addMe->prev = sentinel.prev;
+
+	sentinel.prev->next = addMe;
+	sentinel.prev      = addMe;
+}
+
+void TiXmlAttributeSet::Remove( TiXmlAttribute* removeMe )
+{
+	TiXmlAttribute* node;
+
+	for( node = sentinel.next; node != &sentinel; node = node->next )
+	{
+		if ( node == removeMe )
+		{
+			node->prev->next = node->next;
+			node->next->prev = node->prev;
+			node->next = 0;
+			node->prev = 0;
+			return;
+		}
+	}
+	assert( 0 );		// we tried to remove a non-linked attribute.
+}
+
+
+#ifdef TIXML_USE_STL
+TiXmlAttribute* TiXmlAttributeSet::Find( const std::string& name ) const
+{
+	for( TiXmlAttribute* node = sentinel.next; node != &sentinel; node = node->next )
+	{
+		if ( node->name == name )
+			return node;
+	}
+	return 0;
+}
+
+TiXmlAttribute* TiXmlAttributeSet::FindOrCreate( const std::string& _name )
+{
+	TiXmlAttribute* attrib = Find( _name );
+	if ( !attrib ) {
+		attrib = new TiXmlAttribute();
+		Add( attrib );
+		attrib->SetName( _name );
+	}
+	return attrib;
+}
+#endif
+
+
+TiXmlAttribute* TiXmlAttributeSet::Find( const char* name ) const
+{
+	for( TiXmlAttribute* node = sentinel.next; node != &sentinel; node = node->next )
+	{
+		if ( strcmp( node->name.c_str(), name ) == 0 )
+			return node;
+	}
+	return 0;
+}
+
+
+TiXmlAttribute* TiXmlAttributeSet::FindOrCreate( const char* _name )
+{
+	TiXmlAttribute* attrib = Find( _name );
+	if ( !attrib ) {
+		attrib = new TiXmlAttribute();
+		Add( attrib );
+		attrib->SetName( _name );
+	}
+	return attrib;
+}
+
+
+#ifdef TIXML_USE_STL	
+std::istream& operator>> (std::istream & in, TiXmlNode & base)
+{
+	TIXML_STRING tag;
+	tag.reserve( 8 * 1000 );
+	base.StreamIn( &in, &tag );
+
+	base.Parse( tag.c_str(), 0, TIXML_DEFAULT_ENCODING );
+	return in;
+}
+#endif
+
+
+#ifdef TIXML_USE_STL	
+std::ostream& operator<< (std::ostream & out, const TiXmlNode & base)
+{
+	TiXmlPrinter printer;
+	printer.SetStreamPrinting();
+	base.Accept( &printer );
+	out << printer.Str();
+
+	return out;
+}
+
+
+std::string& operator<< (std::string& out, const TiXmlNode& base )
+{
+	TiXmlPrinter printer;
+	printer.SetStreamPrinting();
+	base.Accept( &printer );
+	out.append( printer.Str() );
+
+	return out;
+}
+#endif
+
+
+TiXmlHandle TiXmlHandle::FirstChild() const
+{
+	if ( node )
+	{
+		TiXmlNode* child = node->FirstChild();
+		if ( child )
+			return TiXmlHandle( child );
+	}
+	return TiXmlHandle( 0 );
+}
+
+
+TiXmlHandle TiXmlHandle::FirstChild( const char * value ) const
+{
+	if ( node )
+	{
+		TiXmlNode* child = node->FirstChild( value );
+		if ( child )
+			return TiXmlHandle( child );
+	}
+	return TiXmlHandle( 0 );
+}
+
+
+TiXmlHandle TiXmlHandle::FirstChildElement() const
+{
+	if ( node )
+	{
+		TiXmlElement* child = node->FirstChildElement();
+		if ( child )
+			return TiXmlHandle( child );
+	}
+	return TiXmlHandle( 0 );
+}
+
+
+TiXmlHandle TiXmlHandle::FirstChildElement( const char * value ) const
+{
+	if ( node )
+	{
+		TiXmlElement* child = node->FirstChildElement( value );
+		if ( child )
+			return TiXmlHandle( child );
+	}
+	return TiXmlHandle( 0 );
+}
+
+
+TiXmlHandle TiXmlHandle::Child( int count ) const
+{
+	if ( node )
+	{
+		int i;
+		TiXmlNode* child = node->FirstChild();
+		for (	i=0;
+				child && iNextSibling(), ++i )
+		{
+			// nothing
+		}
+		if ( child )
+			return TiXmlHandle( child );
+	}
+	return TiXmlHandle( 0 );
+}
+
+
+TiXmlHandle TiXmlHandle::Child( const char* value, int count ) const
+{
+	if ( node )
+	{
+		int i;
+		TiXmlNode* child = node->FirstChild( value );
+		for (	i=0;
+				child && iNextSibling( value ), ++i )
+		{
+			// nothing
+		}
+		if ( child )
+			return TiXmlHandle( child );
+	}
+	return TiXmlHandle( 0 );
+}
+
+
+TiXmlHandle TiXmlHandle::ChildElement( int count ) const
+{
+	if ( node )
+	{
+		int i;
+		TiXmlElement* child = node->FirstChildElement();
+		for (	i=0;
+				child && iNextSiblingElement(), ++i )
+		{
+			// nothing
+		}
+		if ( child )
+			return TiXmlHandle( child );
+	}
+	return TiXmlHandle( 0 );
+}
+
+
+TiXmlHandle TiXmlHandle::ChildElement( const char* value, int count ) const
+{
+	if ( node )
+	{
+		int i;
+		TiXmlElement* child = node->FirstChildElement( value );
+		for (	i=0;
+				child && iNextSiblingElement( value ), ++i )
+		{
+			// nothing
+		}
+		if ( child )
+			return TiXmlHandle( child );
+	}
+	return TiXmlHandle( 0 );
+}
+
+
+bool TiXmlPrinter::VisitEnter( const TiXmlDocument& )
+{
+	return true;
+}
+
+bool TiXmlPrinter::VisitExit( const TiXmlDocument& )
+{
+	return true;
+}
+
+bool TiXmlPrinter::VisitEnter( const TiXmlElement& element, const TiXmlAttribute* firstAttribute )
+{
+	DoIndent();
+	buffer += "<";
+	buffer += element.Value();
+
+	for( const TiXmlAttribute* attrib = firstAttribute; attrib; attrib = attrib->Next() )
+	{
+		buffer += " ";
+		attrib->Print( 0, 0, &buffer );
+	}
+
+	if ( !element.FirstChild() ) 
+	{
+		buffer += " />";
+		DoLineBreak();
+	}
+	else 
+	{
+		buffer += ">";
+		if (    element.FirstChild()->ToText()
+			  && element.LastChild() == element.FirstChild()
+			  && element.FirstChild()->ToText()->CDATA() == false )
+		{
+			simpleTextPrint = true;
+			// no DoLineBreak()!
+		}
+		else
+		{
+			DoLineBreak();
+		}
+	}
+	++depth;	
+	return true;
+}
+
+
+bool TiXmlPrinter::VisitExit( const TiXmlElement& element )
+{
+	--depth;
+	if ( !element.FirstChild() ) 
+	{
+		// nothing.
+	}
+	else 
+	{
+		if ( simpleTextPrint )
+		{
+			simpleTextPrint = false;
+		}
+		else
+		{
+			DoIndent();
+		}
+		buffer += "";
+		DoLineBreak();
+	}
+	return true;
+}
+
+
+bool TiXmlPrinter::Visit( const TiXmlText& text )
+{
+	if ( text.CDATA() )
+	{
+		DoIndent();
+		buffer += "";
+		DoLineBreak();
+	}
+	else if ( simpleTextPrint )
+	{
+		TIXML_STRING str;
+		TiXmlBase::EncodeString( text.ValueTStr(), &str );
+		buffer += str;
+	}
+	else
+	{
+		DoIndent();
+		TIXML_STRING str;
+		TiXmlBase::EncodeString( text.ValueTStr(), &str );
+		buffer += str;
+		DoLineBreak();
+	}
+	return true;
+}
+
+
+bool TiXmlPrinter::Visit( const TiXmlDeclaration& declaration )
+{
+	DoIndent();
+	declaration.Print( 0, 0, &buffer );
+	DoLineBreak();
+	return true;
+}
+
+
+bool TiXmlPrinter::Visit( const TiXmlComment& comment )
+{
+	DoIndent();
+	buffer += "";
+	DoLineBreak();
+	return true;
+}
+
+
+bool TiXmlPrinter::Visit( const TiXmlUnknown& unknown )
+{
+	DoIndent();
+	buffer += "<";
+	buffer += unknown.Value();
+	buffer += ">";
+	DoLineBreak();
+	return true;
+}
+
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/pblaze.src/tinyxmlerror.cpp sdcc-4.2.0+dfsg/sim/ucsim/pblaze.src/tinyxmlerror.cpp
--- sdcc-4.0.0+dfsg/sim/ucsim/pblaze.src/tinyxmlerror.cpp	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/pblaze.src/tinyxmlerror.cpp	2022-01-26 16:35:40.000000000 +0000
@@ -0,0 +1,52 @@
+/*
+www.sourceforge.net/projects/tinyxml
+Original code (2.0 and earlier )copyright (c) 2000-2006 Lee Thomason (www.grinninglizard.com)
+
+This software is provided 'as-is', without any express or implied 
+warranty. In no event will the authors be held liable for any 
+damages arising from the use of this software.
+
+Permission is granted to anyone to use this software for any 
+purpose, including commercial applications, and to alter it and 
+redistribute it freely, subject to the following restrictions:
+
+1. The origin of this software must not be misrepresented; you must
+not claim that you wrote the original software. If you use this
+software in a product, an acknowledgment in the product documentation
+would be appreciated but is not required.
+
+2. Altered source versions must be plainly marked as such, and
+must not be misrepresented as being the original software.
+
+3. This notice may not be removed or altered from any source
+distribution.
+*/
+
+#include "tinyxml.h"
+
+// The goal of the separate error file is to make the first
+// step towards localization. tinyxml (currently) only supports
+// english error messages, but the could now be translated.
+//
+// It also cleans up the code a bit.
+//
+
+const char* TiXmlBase::errorString[ TiXmlBase::TIXML_ERROR_STRING_COUNT ] =
+{
+	"No error",
+	"Error",
+	"Failed to open file",
+	"Error parsing Element.",
+	"Failed to read Element name",
+	"Error reading Element value.",
+	"Error reading Attributes.",
+	"Error: empty tag.",
+	"Error reading end tag.",
+	"Error parsing Unknown.",
+	"Error parsing Comment.",
+	"Error parsing Declaration.",
+	"Error document empty.",
+	"Error null (0) or unexpected EOF found in input stream.",
+	"Error parsing CDATA.",
+	"Error when TiXmlDocument added to document, because TiXmlDocument can only be at the root.",
+};
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/pblaze.src/tinyxml.h sdcc-4.2.0+dfsg/sim/ucsim/pblaze.src/tinyxml.h
--- sdcc-4.0.0+dfsg/sim/ucsim/pblaze.src/tinyxml.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/pblaze.src/tinyxml.h	2022-01-27 21:35:29.000000000 +0000
@@ -0,0 +1,1805 @@
+/*
+www.sourceforge.net/projects/tinyxml
+Original code by Lee Thomason (www.grinninglizard.com)
+
+This software is provided 'as-is', without any express or implied
+warranty. In no event will the authors be held liable for any
+damages arising from the use of this software.
+
+Permission is granted to anyone to use this software for any
+purpose, including commercial applications, and to alter it and
+redistribute it freely, subject to the following restrictions:
+
+1. The origin of this software must not be misrepresented; you must
+not claim that you wrote the original software. If you use this
+software in a product, an acknowledgment in the product documentation
+would be appreciated but is not required.
+
+2. Altered source versions must be plainly marked as such, and
+must not be misrepresented as being the original software.
+
+3. This notice may not be removed or altered from any source
+distribution.
+*/
+
+
+#ifndef TINYXML_INCLUDED
+#define TINYXML_INCLUDED
+
+#ifdef _MSC_VER
+#pragma warning( push )
+#pragma warning( disable : 4530 )
+#pragma warning( disable : 4786 )
+#endif
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+// Help out windows:
+#if defined( _DEBUG ) && !defined( DEBUG )
+#define DEBUG
+#endif
+
+#ifdef TIXML_USE_STL
+	#include 
+ 	#include 
+	#include 
+	#define TIXML_STRING		std::string
+#else
+	#include "tinystr.h"
+	#define TIXML_STRING		TiXmlString
+#endif
+
+// Deprecated library function hell. Compilers want to use the
+// new safe versions. This probably doesn't fully address the problem,
+// but it gets closer. There are too many compilers for me to fully
+// test. If you get compilation troubles, undefine TIXML_SAFE
+#define TIXML_SAFE
+
+#ifdef TIXML_SAFE
+	#if defined(_MSC_VER) && (_MSC_VER >= 1400 )
+		// Microsoft visual studio, version 2005 and higher.
+		#define TIXML_SNPRINTF _snprintf_s
+		#define TIXML_SSCANF   sscanf_s
+	#elif defined(_MSC_VER) && (_MSC_VER >= 1200 )
+		// Microsoft visual studio, version 6 and higher.
+		//#pragma message( "Using _sn* functions." )
+		#define TIXML_SNPRINTF _snprintf
+		#define TIXML_SSCANF   sscanf
+	#elif defined(__GNUC__) && (__GNUC__ >= 3 )
+		// GCC version 3 and higher.s
+		//#warning( "Using sn* functions." )
+		#define TIXML_SNPRINTF snprintf
+		#define TIXML_SSCANF   sscanf
+	#else
+		#define TIXML_SNPRINTF snprintf
+		#define TIXML_SSCANF   sscanf
+	#endif
+#endif	
+
+class TiXmlDocument;
+class TiXmlElement;
+class TiXmlComment;
+class TiXmlUnknown;
+class TiXmlAttribute;
+class TiXmlText;
+class TiXmlDeclaration;
+class TiXmlParsingData;
+
+const int TIXML_MAJOR_VERSION = 2;
+const int TIXML_MINOR_VERSION = 6;
+const int TIXML_PATCH_VERSION = 2;
+
+/*	Internal structure for tracking location of items 
+	in the XML file.
+*/
+struct TiXmlCursor
+{
+	TiXmlCursor()		{ Clear(); }
+	void Clear()		{ row = col = -1; }
+
+	int row;	// 0 based.
+	int col;	// 0 based.
+};
+
+
+/**
+	Implements the interface to the "Visitor pattern" (see the Accept() method.)
+	If you call the Accept() method, it requires being passed a TiXmlVisitor
+	class to handle callbacks. For nodes that contain other nodes (Document, Element)
+	you will get called with a VisitEnter/VisitExit pair. Nodes that are always leaves
+	are simply called with Visit().
+
+	If you return 'true' from a Visit method, recursive parsing will continue. If you return
+	false, no children of this node or its sibilings will be Visited.
+
+	All flavors of Visit methods have a default implementation that returns 'true' (continue 
+	visiting). You need to only override methods that are interesting to you.
+
+	Generally Accept() is called on the TiXmlDocument, although all nodes suppert Visiting.
+
+	You should never change the document from a callback.
+
+	@sa TiXmlNode::Accept()
+*/
+class TiXmlVisitor
+{
+public:
+	virtual ~TiXmlVisitor() {}
+
+	/// Visit a document.
+	virtual bool VisitEnter( const TiXmlDocument& /*doc*/ )			{ return true; }
+	/// Visit a document.
+	virtual bool VisitExit( const TiXmlDocument& /*doc*/ )			{ return true; }
+
+	/// Visit an element.
+	virtual bool VisitEnter( const TiXmlElement& /*element*/, const TiXmlAttribute* /*firstAttribute*/ )	{ return true; }
+	/// Visit an element.
+	virtual bool VisitExit( const TiXmlElement& /*element*/ )		{ return true; }
+
+	/// Visit a declaration
+	virtual bool Visit( const TiXmlDeclaration& /*declaration*/ )	{ return true; }
+	/// Visit a text node
+	virtual bool Visit( const TiXmlText& /*text*/ )					{ return true; }
+	/// Visit a comment node
+	virtual bool Visit( const TiXmlComment& /*comment*/ )			{ return true; }
+	/// Visit an unknown node
+	virtual bool Visit( const TiXmlUnknown& /*unknown*/ )			{ return true; }
+};
+
+// Only used by Attribute::Query functions
+enum 
+{ 
+	TIXML_SUCCESS,
+	TIXML_NO_ATTRIBUTE,
+	TIXML_WRONG_TYPE
+};
+
+
+// Used by the parsing routines.
+enum TiXmlEncoding
+{
+	TIXML_ENCODING_UNKNOWN,
+	TIXML_ENCODING_UTF8,
+	TIXML_ENCODING_LEGACY
+};
+
+const TiXmlEncoding TIXML_DEFAULT_ENCODING = TIXML_ENCODING_UNKNOWN;
+
+/** TiXmlBase is a base class for every class in TinyXml.
+	It does little except to establish that TinyXml classes
+	can be printed and provide some utility functions.
+
+	In XML, the document and elements can contain
+	other elements and other types of nodes.
+
+	@verbatim
+	A Document can contain:	Element	(container or leaf)
+							Comment (leaf)
+							Unknown (leaf)
+							Declaration( leaf )
+
+	An Element can contain:	Element (container or leaf)
+							Text	(leaf)
+							Attributes (not on tree)
+							Comment (leaf)
+							Unknown (leaf)
+
+	A Declaration contains: Attributes (not on tree)
+	@endverbatim
+*/
+class TiXmlBase
+{
+	friend class TiXmlNode;
+	friend class TiXmlElement;
+	friend class TiXmlDocument;
+
+public:
+	TiXmlBase()	:	userData(0)		{}
+	virtual ~TiXmlBase()			{}
+
+	/**	All TinyXml classes can print themselves to a filestream
+		or the string class (TiXmlString in non-STL mode, std::string
+		in STL mode.) Either or both cfile and str can be null.
+		
+		This is a formatted print, and will insert 
+		tabs and newlines.
+		
+		(For an unformatted stream, use the << operator.)
+	*/
+	virtual void Print( FILE* cfile, int depth ) const = 0;
+
+	/**	The world does not agree on whether white space should be kept or
+		not. In order to make everyone happy, these global, static functions
+		are provided to set whether or not TinyXml will condense all white space
+		into a single space or not. The default is to condense. Note changing this
+		value is not thread safe.
+	*/
+	static void SetCondenseWhiteSpace( bool condense )		{ condenseWhiteSpace = condense; }
+
+	/// Return the current white space setting.
+	static bool IsWhiteSpaceCondensed()						{ return condenseWhiteSpace; }
+
+	/** Return the position, in the original source file, of this node or attribute.
+		The row and column are 1-based. (That is the first row and first column is
+		1,1). If the returns values are 0 or less, then the parser does not have
+		a row and column value.
+
+		Generally, the row and column value will be set when the TiXmlDocument::Load(),
+		TiXmlDocument::LoadFile(), or any TiXmlNode::Parse() is called. It will NOT be set
+		when the DOM was created from operator>>.
+
+		The values reflect the initial load. Once the DOM is modified programmatically
+		(by adding or changing nodes and attributes) the new values will NOT update to
+		reflect changes in the document.
+
+		There is a minor performance cost to computing the row and column. Computation
+		can be disabled if TiXmlDocument::SetTabSize() is called with 0 as the value.
+
+		@sa TiXmlDocument::SetTabSize()
+	*/
+	int Row() const			{ return location.row + 1; }
+	int Column() const		{ return location.col + 1; }	///< See Row()
+
+	void  SetUserData( void* user )			{ userData = user; }	///< Set a pointer to arbitrary user data.
+	void* GetUserData()						{ return userData; }	///< Get a pointer to arbitrary user data.
+	const void* GetUserData() const 		{ return userData; }	///< Get a pointer to arbitrary user data.
+
+	// Table that returs, for a given lead byte, the total number of bytes
+	// in the UTF-8 sequence.
+	static const int utf8ByteTable[256];
+
+	virtual const char* Parse(	const char* p, 
+								TiXmlParsingData* data, 
+								TiXmlEncoding encoding /*= TIXML_ENCODING_UNKNOWN */ ) = 0;
+
+	/** Expands entities in a string. Note this should not contian the tag's '<', '>', etc, 
+		or they will be transformed into entities!
+	*/
+	static void EncodeString( const TIXML_STRING& str, TIXML_STRING* out );
+
+	enum
+	{
+		TIXML_NO_ERROR = 0,
+		TIXML_ERROR,
+		TIXML_ERROR_OPENING_FILE,
+		TIXML_ERROR_PARSING_ELEMENT,
+		TIXML_ERROR_FAILED_TO_READ_ELEMENT_NAME,
+		TIXML_ERROR_READING_ELEMENT_VALUE,
+		TIXML_ERROR_READING_ATTRIBUTES,
+		TIXML_ERROR_PARSING_EMPTY,
+		TIXML_ERROR_READING_END_TAG,
+		TIXML_ERROR_PARSING_UNKNOWN,
+		TIXML_ERROR_PARSING_COMMENT,
+		TIXML_ERROR_PARSING_DECLARATION,
+		TIXML_ERROR_DOCUMENT_EMPTY,
+		TIXML_ERROR_EMBEDDED_NULL,
+		TIXML_ERROR_PARSING_CDATA,
+		TIXML_ERROR_DOCUMENT_TOP_ONLY,
+
+		TIXML_ERROR_STRING_COUNT
+	};
+
+protected:
+
+	static const char* SkipWhiteSpace( const char*, TiXmlEncoding encoding );
+
+	inline static bool IsWhiteSpace( char c )		
+	{ 
+		return ( isspace( (unsigned char) c ) || c == '\n' || c == '\r' ); 
+	}
+	inline static bool IsWhiteSpace( int c )
+	{
+		if ( c < 256 )
+			return IsWhiteSpace( (char) c );
+		return false;	// Again, only truly correct for English/Latin...but usually works.
+	}
+
+	#ifdef TIXML_USE_STL
+	static bool	StreamWhiteSpace( std::istream * in, TIXML_STRING * tag );
+	static bool StreamTo( std::istream * in, int character, TIXML_STRING * tag );
+	#endif
+
+	/*	Reads an XML name into the string provided. Returns
+		a pointer just past the last character of the name,
+		or 0 if the function has an error.
+	*/
+	static const char* ReadName( const char* p, TIXML_STRING* name, TiXmlEncoding encoding );
+
+	/*	Reads text. Returns a pointer past the given end tag.
+		Wickedly complex options, but it keeps the (sensitive) code in one place.
+	*/
+	static const char* ReadText(	const char* in,				// where to start
+									TIXML_STRING* text,			// the string read
+									bool ignoreWhiteSpace,		// whether to keep the white space
+									const char* endTag,			// what ends this text
+									bool ignoreCase,			// whether to ignore case in the end tag
+									TiXmlEncoding encoding );	// the current encoding
+
+	// If an entity has been found, transform it into a character.
+	static const char* GetEntity( const char* in, char* value, int* length, TiXmlEncoding encoding );
+
+	// Get a character, while interpreting entities.
+	// The length can be from 0 to 4 bytes.
+	inline static const char* GetChar( const char* p, char* _value, int* length, TiXmlEncoding encoding )
+	{
+		assert( p );
+		if ( encoding == TIXML_ENCODING_UTF8 )
+		{
+			*length = utf8ByteTable[ *((const unsigned char*)p) ];
+			assert( *length >= 0 && *length < 5 );
+		}
+		else
+		{
+			*length = 1;
+		}
+
+		if ( *length == 1 )
+		{
+			if ( *p == '&' )
+				return GetEntity( p, _value, length, encoding );
+			*_value = *p;
+			return p+1;
+		}
+		else if ( *length )
+		{
+			//strncpy( _value, p, *length );	// lots of compilers don't like this function (unsafe),
+												// and the null terminator isn't needed
+			for( int i=0; p[i] && i<*length; ++i ) {
+				_value[i] = p[i];
+			}
+			return p + (*length);
+		}
+		else
+		{
+			// Not valid text.
+			return 0;
+		}
+	}
+
+	// Return true if the next characters in the stream are any of the endTag sequences.
+	// Ignore case only works for english, and should only be relied on when comparing
+	// to English words: StringEqual( p, "version", true ) is fine.
+	static bool StringEqual(	const char* p,
+								const char* endTag,
+								bool ignoreCase,
+								TiXmlEncoding encoding );
+
+	static const char* errorString[ TIXML_ERROR_STRING_COUNT ];
+
+	TiXmlCursor location;
+
+    /// Field containing a generic user pointer
+	void*			userData;
+	
+	// None of these methods are reliable for any language except English.
+	// Good for approximation, not great for accuracy.
+	static int IsAlpha( unsigned char anyByte, TiXmlEncoding encoding );
+	static int IsAlphaNum( unsigned char anyByte, TiXmlEncoding encoding );
+	inline static int ToLower( int v, TiXmlEncoding encoding )
+	{
+		if ( encoding == TIXML_ENCODING_UTF8 )
+		{
+			if ( v < 128 ) return tolower( v );
+			return v;
+		}
+		else
+		{
+			return tolower( v );
+		}
+	}
+	static void ConvertUTF32ToUTF8( unsigned long input, char* output, int* length );
+
+private:
+	TiXmlBase( const TiXmlBase& );				// not implemented.
+	void operator=( const TiXmlBase& base );	// not allowed.
+
+	struct Entity
+	{
+		const char*     str;
+		unsigned int	strLength;
+		char		    chr;
+	};
+	enum
+	{
+		NUM_ENTITY = 5,
+		MAX_ENTITY_LENGTH = 6
+
+	};
+	static Entity entity[ NUM_ENTITY ];
+	static bool condenseWhiteSpace;
+};
+
+
+/** The parent class for everything in the Document Object Model.
+	(Except for attributes).
+	Nodes have siblings, a parent, and children. A node can be
+	in a document, or stand on its own. The type of a TiXmlNode
+	can be queried, and it can be cast to its more defined type.
+*/
+class TiXmlNode : public TiXmlBase
+{
+	friend class TiXmlDocument;
+	friend class TiXmlElement;
+
+public:
+	#ifdef TIXML_USE_STL	
+
+	    /** An input stream operator, for every class. Tolerant of newlines and
+		    formatting, but doesn't expect them.
+	    */
+	    friend std::istream& operator >> (std::istream& in, TiXmlNode& base);
+
+	    /** An output stream operator, for every class. Note that this outputs
+		    without any newlines or formatting, as opposed to Print(), which
+		    includes tabs and new lines.
+
+		    The operator<< and operator>> are not completely symmetric. Writing
+		    a node to a stream is very well defined. You'll get a nice stream
+		    of output, without any extra whitespace or newlines.
+		    
+		    But reading is not as well defined. (As it always is.) If you create
+		    a TiXmlElement (for example) and read that from an input stream,
+		    the text needs to define an element or junk will result. This is
+		    true of all input streams, but it's worth keeping in mind.
+
+		    A TiXmlDocument will read nodes until it reads a root element, and
+			all the children of that root element.
+	    */	
+	    friend std::ostream& operator<< (std::ostream& out, const TiXmlNode& base);
+
+		/// Appends the XML node or attribute to a std::string.
+		friend std::string& operator<< (std::string& out, const TiXmlNode& base );
+
+	#endif
+
+	/** The types of XML nodes supported by TinyXml. (All the
+			unsupported types are picked up by UNKNOWN.)
+	*/
+	enum NodeType
+	{
+		TINYXML_DOCUMENT,
+		TINYXML_ELEMENT,
+		TINYXML_COMMENT,
+		TINYXML_UNKNOWN,
+		TINYXML_TEXT,
+		TINYXML_DECLARATION,
+		TINYXML_TYPECOUNT
+	};
+
+	virtual ~TiXmlNode();
+
+	/** The meaning of 'value' changes for the specific type of
+		TiXmlNode.
+		@verbatim
+		Document:	filename of the xml file
+		Element:	name of the element
+		Comment:	the comment text
+		Unknown:	the tag contents
+		Text:		the text string
+		@endverbatim
+
+		The subclasses will wrap this function.
+	*/
+	const char *Value() const { return value.c_str (); }
+
+    #ifdef TIXML_USE_STL
+	/** Return Value() as a std::string. If you only use STL,
+	    this is more efficient than calling Value().
+		Only available in STL mode.
+	*/
+	const std::string& ValueStr() const { return value; }
+	#endif
+
+	const TIXML_STRING& ValueTStr() const { return value; }
+
+	/** Changes the value of the node. Defined as:
+		@verbatim
+		Document:	filename of the xml file
+		Element:	name of the element
+		Comment:	the comment text
+		Unknown:	the tag contents
+		Text:		the text string
+		@endverbatim
+	*/
+	void SetValue(const char * _value) { value = _value;}
+
+    #ifdef TIXML_USE_STL
+	/// STL std::string form.
+	void SetValue( const std::string& _value )	{ value = _value; }
+	#endif
+
+	/// Delete all the children of this node. Does not affect 'this'.
+	void Clear();
+
+	/// One step up the DOM.
+	TiXmlNode* Parent()							{ return parent; }
+	const TiXmlNode* Parent() const				{ return parent; }
+
+	const TiXmlNode* FirstChild()	const		{ return firstChild; }	///< The first child of this node. Will be null if there are no children.
+	TiXmlNode* FirstChild()						{ return firstChild; }
+	const TiXmlNode* FirstChild( const char * value ) const;			///< The first child of this node with the matching 'value'. Will be null if none found.
+	/// The first child of this node with the matching 'value'. Will be null if none found.
+	TiXmlNode* FirstChild( const char * _value ) {
+		// Call through to the const version - safe since nothing is changed. Exiting syntax: cast this to a const (always safe)
+		// call the method, cast the return back to non-const.
+		return const_cast< TiXmlNode* > ((const_cast< const TiXmlNode* >(this))->FirstChild( _value ));
+	}
+	const TiXmlNode* LastChild() const	{ return lastChild; }		/// The last child of this node. Will be null if there are no children.
+	TiXmlNode* LastChild()	{ return lastChild; }
+	
+	const TiXmlNode* LastChild( const char * value ) const;			/// The last child of this node matching 'value'. Will be null if there are no children.
+	TiXmlNode* LastChild( const char * _value ) {
+		return const_cast< TiXmlNode* > ((const_cast< const TiXmlNode* >(this))->LastChild( _value ));
+	}
+
+    #ifdef TIXML_USE_STL
+	const TiXmlNode* FirstChild( const std::string& _value ) const	{	return FirstChild (_value.c_str ());	}	///< STL std::string form.
+	TiXmlNode* FirstChild( const std::string& _value )				{	return FirstChild (_value.c_str ());	}	///< STL std::string form.
+	const TiXmlNode* LastChild( const std::string& _value ) const	{	return LastChild (_value.c_str ());	}	///< STL std::string form.
+	TiXmlNode* LastChild( const std::string& _value )				{	return LastChild (_value.c_str ());	}	///< STL std::string form.
+	#endif
+
+	/** An alternate way to walk the children of a node.
+		One way to iterate over nodes is:
+		@verbatim
+			for( child = parent->FirstChild(); child; child = child->NextSibling() )
+		@endverbatim
+
+		IterateChildren does the same thing with the syntax:
+		@verbatim
+			child = 0;
+			while( child = parent->IterateChildren( child ) )
+		@endverbatim
+
+		IterateChildren takes the previous child as input and finds
+		the next one. If the previous child is null, it returns the
+		first. IterateChildren will return null when done.
+	*/
+	const TiXmlNode* IterateChildren( const TiXmlNode* previous ) const;
+	TiXmlNode* IterateChildren( const TiXmlNode* previous ) {
+		return const_cast< TiXmlNode* >( (const_cast< const TiXmlNode* >(this))->IterateChildren( previous ) );
+	}
+
+	/// This flavor of IterateChildren searches for children with a particular 'value'
+	const TiXmlNode* IterateChildren( const char * value, const TiXmlNode* previous ) const;
+	TiXmlNode* IterateChildren( const char * _value, const TiXmlNode* previous ) {
+		return const_cast< TiXmlNode* >( (const_cast< const TiXmlNode* >(this))->IterateChildren( _value, previous ) );
+	}
+
+    #ifdef TIXML_USE_STL
+	const TiXmlNode* IterateChildren( const std::string& _value, const TiXmlNode* previous ) const	{	return IterateChildren (_value.c_str (), previous);	}	///< STL std::string form.
+	TiXmlNode* IterateChildren( const std::string& _value, const TiXmlNode* previous ) {	return IterateChildren (_value.c_str (), previous);	}	///< STL std::string form.
+	#endif
+
+	/** Add a new node related to this. Adds a child past the LastChild.
+		Returns a pointer to the new object or NULL if an error occurred.
+	*/
+	TiXmlNode* InsertEndChild( const TiXmlNode& addThis );
+
+
+	/** Add a new node related to this. Adds a child past the LastChild.
+
+		NOTE: the node to be added is passed by pointer, and will be
+		henceforth owned (and deleted) by tinyXml. This method is efficient
+		and avoids an extra copy, but should be used with care as it
+		uses a different memory model than the other insert functions.
+
+		@sa InsertEndChild
+	*/
+	TiXmlNode* LinkEndChild( TiXmlNode* addThis );
+
+	/** Add a new node related to this. Adds a child before the specified child.
+		Returns a pointer to the new object or NULL if an error occurred.
+	*/
+	TiXmlNode* InsertBeforeChild( TiXmlNode* beforeThis, const TiXmlNode& addThis );
+
+	/** Add a new node related to this. Adds a child after the specified child.
+		Returns a pointer to the new object or NULL if an error occurred.
+	*/
+	TiXmlNode* InsertAfterChild(  TiXmlNode* afterThis, const TiXmlNode& addThis );
+
+	/** Replace a child of this node.
+		Returns a pointer to the new object or NULL if an error occurred.
+	*/
+	TiXmlNode* ReplaceChild( TiXmlNode* replaceThis, const TiXmlNode& withThis );
+
+	/// Delete a child of this node.
+	bool RemoveChild( TiXmlNode* removeThis );
+
+	/// Navigate to a sibling node.
+	const TiXmlNode* PreviousSibling() const			{ return prev; }
+	TiXmlNode* PreviousSibling()						{ return prev; }
+
+	/// Navigate to a sibling node.
+	const TiXmlNode* PreviousSibling( const char * ) const;
+	TiXmlNode* PreviousSibling( const char *_prev ) {
+		return const_cast< TiXmlNode* >( (const_cast< const TiXmlNode* >(this))->PreviousSibling( _prev ) );
+	}
+
+    #ifdef TIXML_USE_STL
+	const TiXmlNode* PreviousSibling( const std::string& _value ) const	{	return PreviousSibling (_value.c_str ());	}	///< STL std::string form.
+	TiXmlNode* PreviousSibling( const std::string& _value ) 			{	return PreviousSibling (_value.c_str ());	}	///< STL std::string form.
+	const TiXmlNode* NextSibling( const std::string& _value) const		{	return NextSibling (_value.c_str ());	}	///< STL std::string form.
+	TiXmlNode* NextSibling( const std::string& _value) 					{	return NextSibling (_value.c_str ());	}	///< STL std::string form.
+	#endif
+
+	/// Navigate to a sibling node.
+	const TiXmlNode* NextSibling() const				{ return next; }
+	TiXmlNode* NextSibling()							{ return next; }
+
+	/// Navigate to a sibling node with the given 'value'.
+	const TiXmlNode* NextSibling( const char * ) const;
+	TiXmlNode* NextSibling( const char* _next ) {
+		return const_cast< TiXmlNode* >( (const_cast< const TiXmlNode* >(this))->NextSibling( _next ) );
+	}
+
+	/** Convenience function to get through elements.
+		Calls NextSibling and ToElement. Will skip all non-Element
+		nodes. Returns 0 if there is not another element.
+	*/
+	const TiXmlElement* NextSiblingElement() const;
+	TiXmlElement* NextSiblingElement() {
+		return const_cast< TiXmlElement* >( (const_cast< const TiXmlNode* >(this))->NextSiblingElement() );
+	}
+
+	/** Convenience function to get through elements.
+		Calls NextSibling and ToElement. Will skip all non-Element
+		nodes. Returns 0 if there is not another element.
+	*/
+	const TiXmlElement* NextSiblingElement( const char * ) const;
+	TiXmlElement* NextSiblingElement( const char *_next ) {
+		return const_cast< TiXmlElement* >( (const_cast< const TiXmlNode* >(this))->NextSiblingElement( _next ) );
+	}
+
+    #ifdef TIXML_USE_STL
+	const TiXmlElement* NextSiblingElement( const std::string& _value) const	{	return NextSiblingElement (_value.c_str ());	}	///< STL std::string form.
+	TiXmlElement* NextSiblingElement( const std::string& _value)				{	return NextSiblingElement (_value.c_str ());	}	///< STL std::string form.
+	#endif
+
+	/// Convenience function to get through elements.
+	const TiXmlElement* FirstChildElement()	const;
+	TiXmlElement* FirstChildElement() {
+		return const_cast< TiXmlElement* >( (const_cast< const TiXmlNode* >(this))->FirstChildElement() );
+	}
+
+	/// Convenience function to get through elements.
+	const TiXmlElement* FirstChildElement( const char * _value ) const;
+	TiXmlElement* FirstChildElement( const char * _value ) {
+		return const_cast< TiXmlElement* >( (const_cast< const TiXmlNode* >(this))->FirstChildElement( _value ) );
+	}
+
+    #ifdef TIXML_USE_STL
+	const TiXmlElement* FirstChildElement( const std::string& _value ) const	{	return FirstChildElement (_value.c_str ());	}	///< STL std::string form.
+	TiXmlElement* FirstChildElement( const std::string& _value )				{	return FirstChildElement (_value.c_str ());	}	///< STL std::string form.
+	#endif
+
+	/** Query the type (as an enumerated value, above) of this node.
+		The possible types are: TINYXML_DOCUMENT, TINYXML_ELEMENT, TINYXML_COMMENT,
+								TINYXML_UNKNOWN, TINYXML_TEXT, and TINYXML_DECLARATION.
+	*/
+	int Type() const	{ return type; }
+
+	/** Return a pointer to the Document this node lives in.
+		Returns null if not in a document.
+	*/
+	const TiXmlDocument* GetDocument() const;
+	TiXmlDocument* GetDocument() {
+		return const_cast< TiXmlDocument* >( (const_cast< const TiXmlNode* >(this))->GetDocument() );
+	}
+
+	/// Returns true if this node has no children.
+	bool NoChildren() const						{ return !firstChild; }
+
+	virtual const TiXmlDocument*    ToDocument()    const { return 0; } ///< Cast to a more defined type. Will return null if not of the requested type.
+	virtual const TiXmlElement*     ToElement()     const { return 0; } ///< Cast to a more defined type. Will return null if not of the requested type.
+	virtual const TiXmlComment*     ToComment()     const { return 0; } ///< Cast to a more defined type. Will return null if not of the requested type.
+	virtual const TiXmlUnknown*     ToUnknown()     const { return 0; } ///< Cast to a more defined type. Will return null if not of the requested type.
+	virtual const TiXmlText*        ToText()        const { return 0; } ///< Cast to a more defined type. Will return null if not of the requested type.
+	virtual const TiXmlDeclaration* ToDeclaration() const { return 0; } ///< Cast to a more defined type. Will return null if not of the requested type.
+
+	virtual TiXmlDocument*          ToDocument()    { return 0; } ///< Cast to a more defined type. Will return null if not of the requested type.
+	virtual TiXmlElement*           ToElement()	    { return 0; } ///< Cast to a more defined type. Will return null if not of the requested type.
+	virtual TiXmlComment*           ToComment()     { return 0; } ///< Cast to a more defined type. Will return null if not of the requested type.
+	virtual TiXmlUnknown*           ToUnknown()	    { return 0; } ///< Cast to a more defined type. Will return null if not of the requested type.
+	virtual TiXmlText*	            ToText()        { return 0; } ///< Cast to a more defined type. Will return null if not of the requested type.
+	virtual TiXmlDeclaration*       ToDeclaration() { return 0; } ///< Cast to a more defined type. Will return null if not of the requested type.
+
+	/** Create an exact duplicate of this node and return it. The memory must be deleted
+		by the caller. 
+	*/
+	virtual TiXmlNode* Clone() const = 0;
+
+	/** Accept a hierchical visit the nodes in the TinyXML DOM. Every node in the 
+		XML tree will be conditionally visited and the host will be called back
+		via the TiXmlVisitor interface.
+
+		This is essentially a SAX interface for TinyXML. (Note however it doesn't re-parse
+		the XML for the callbacks, so the performance of TinyXML is unchanged by using this
+		interface versus any other.)
+
+		The interface has been based on ideas from:
+
+		- http://www.saxproject.org/
+		- http://c2.com/cgi/wiki?HierarchicalVisitorPattern 
+
+		Which are both good references for "visiting".
+
+		An example of using Accept():
+		@verbatim
+		TiXmlPrinter printer;
+		tinyxmlDoc.Accept( &printer );
+		const char* xmlcstr = printer.CStr();
+		@endverbatim
+	*/
+	virtual bool Accept( TiXmlVisitor* visitor ) const = 0;
+
+protected:
+	TiXmlNode( NodeType _type );
+
+	// Copy to the allocated object. Shared functionality between Clone, Copy constructor,
+	// and the assignment operator.
+	void CopyTo( TiXmlNode* target ) const;
+
+	#ifdef TIXML_USE_STL
+	    // The real work of the input operator.
+	virtual void StreamIn( std::istream* in, TIXML_STRING* tag ) = 0;
+	#endif
+
+	// Figure out what is at *p, and parse it. Returns null if it is not an xml node.
+	TiXmlNode* Identify( const char* start, TiXmlEncoding encoding );
+
+	TiXmlNode*		parent;
+	NodeType		type;
+
+	TiXmlNode*		firstChild;
+	TiXmlNode*		lastChild;
+
+	TIXML_STRING	value;
+
+	TiXmlNode*		prev;
+	TiXmlNode*		next;
+
+private:
+	TiXmlNode( const TiXmlNode& );				// not implemented.
+	void operator=( const TiXmlNode& base );	// not allowed.
+};
+
+
+/** An attribute is a name-value pair. Elements have an arbitrary
+	number of attributes, each with a unique name.
+
+	@note The attributes are not TiXmlNodes, since they are not
+		  part of the tinyXML document object model. There are other
+		  suggested ways to look at this problem.
+*/
+class TiXmlAttribute : public TiXmlBase
+{
+	friend class TiXmlAttributeSet;
+
+public:
+	/// Construct an empty attribute.
+	TiXmlAttribute() : TiXmlBase()
+	{
+		document = 0;
+		prev = next = 0;
+	}
+
+	#ifdef TIXML_USE_STL
+	/// std::string constructor.
+	TiXmlAttribute( const std::string& _name, const std::string& _value )
+	{
+		name = _name;
+		value = _value;
+		document = 0;
+		prev = next = 0;
+	}
+	#endif
+
+	/// Construct an attribute with a name and value.
+	TiXmlAttribute( const char * _name, const char * _value )
+	{
+		name = _name;
+		value = _value;
+		document = 0;
+		prev = next = 0;
+	}
+
+	const char*		Name()  const		{ return name.c_str(); }		///< Return the name of this attribute.
+	const char*		Value() const		{ return value.c_str(); }		///< Return the value of this attribute.
+	#ifdef TIXML_USE_STL
+	const std::string& ValueStr() const	{ return value; }				///< Return the value of this attribute.
+	#endif
+	int				IntValue() const;									///< Return the value of this attribute, converted to an integer.
+	double			DoubleValue() const;								///< Return the value of this attribute, converted to a double.
+
+	// Get the tinyxml string representation
+	const TIXML_STRING& NameTStr() const { return name; }
+
+	/** QueryIntValue examines the value string. It is an alternative to the
+		IntValue() method with richer error checking.
+		If the value is an integer, it is stored in 'value' and 
+		the call returns TIXML_SUCCESS. If it is not
+		an integer, it returns TIXML_WRONG_TYPE.
+
+		A specialized but useful call. Note that for success it returns 0,
+		which is the opposite of almost all other TinyXml calls.
+	*/
+	int QueryIntValue( int* _value ) const;
+	/// QueryDoubleValue examines the value string. See QueryIntValue().
+	int QueryDoubleValue( double* _value ) const;
+
+	void SetName( const char* _name )	{ name = _name; }				///< Set the name of this attribute.
+	void SetValue( const char* _value )	{ value = _value; }				///< Set the value.
+
+	void SetIntValue( int _value );										///< Set the value from an integer.
+	void SetDoubleValue( double _value );								///< Set the value from a double.
+
+    #ifdef TIXML_USE_STL
+	/// STL std::string form.
+	void SetName( const std::string& _name )	{ name = _name; }	
+	/// STL std::string form.	
+	void SetValue( const std::string& _value )	{ value = _value; }
+	#endif
+
+	/// Get the next sibling attribute in the DOM. Returns null at end.
+	const TiXmlAttribute* Next() const;
+	TiXmlAttribute* Next() {
+		return const_cast< TiXmlAttribute* >( (const_cast< const TiXmlAttribute* >(this))->Next() ); 
+	}
+
+	/// Get the previous sibling attribute in the DOM. Returns null at beginning.
+	const TiXmlAttribute* Previous() const;
+	TiXmlAttribute* Previous() {
+		return const_cast< TiXmlAttribute* >( (const_cast< const TiXmlAttribute* >(this))->Previous() ); 
+	}
+
+	bool operator==( const TiXmlAttribute& rhs ) const { return rhs.name == name; }
+	bool operator<( const TiXmlAttribute& rhs )	 const { return name < rhs.name; }
+	bool operator>( const TiXmlAttribute& rhs )  const { return name > rhs.name; }
+
+	/*	Attribute parsing starts: first letter of the name
+						 returns: the next char after the value end quote
+	*/
+	virtual const char* Parse( const char* p, TiXmlParsingData* data, TiXmlEncoding encoding );
+
+	// Prints this Attribute to a FILE stream.
+	virtual void Print( FILE* cfile, int depth ) const {
+		Print( cfile, depth, 0 );
+	}
+	void Print( FILE* cfile, int depth, TIXML_STRING* str ) const;
+
+	// [internal use]
+	// Set the document pointer so the attribute can report errors.
+	void SetDocument( TiXmlDocument* doc )	{ document = doc; }
+
+private:
+	TiXmlAttribute( const TiXmlAttribute& );				// not implemented.
+	void operator=( const TiXmlAttribute& base );	// not allowed.
+
+	TiXmlDocument*	document;	// A pointer back to a document, for error reporting.
+	TIXML_STRING name;
+	TIXML_STRING value;
+	TiXmlAttribute*	prev;
+	TiXmlAttribute*	next;
+};
+
+
+/*	A class used to manage a group of attributes.
+	It is only used internally, both by the ELEMENT and the DECLARATION.
+	
+	The set can be changed transparent to the Element and Declaration
+	classes that use it, but NOT transparent to the Attribute
+	which has to implement a next() and previous() method. Which makes
+	it a bit problematic and prevents the use of STL.
+
+	This version is implemented with circular lists because:
+		- I like circular lists
+		- it demonstrates some independence from the (typical) doubly linked list.
+*/
+class TiXmlAttributeSet
+{
+public:
+	TiXmlAttributeSet();
+	~TiXmlAttributeSet();
+
+	void Add( TiXmlAttribute* attribute );
+	void Remove( TiXmlAttribute* attribute );
+
+	const TiXmlAttribute* First()	const	{ return ( sentinel.next == &sentinel ) ? 0 : sentinel.next; }
+	TiXmlAttribute* First()					{ return ( sentinel.next == &sentinel ) ? 0 : sentinel.next; }
+	const TiXmlAttribute* Last() const		{ return ( sentinel.prev == &sentinel ) ? 0 : sentinel.prev; }
+	TiXmlAttribute* Last()					{ return ( sentinel.prev == &sentinel ) ? 0 : sentinel.prev; }
+
+	TiXmlAttribute*	Find( const char* _name ) const;
+	TiXmlAttribute* FindOrCreate( const char* _name );
+
+#	ifdef TIXML_USE_STL
+	TiXmlAttribute*	Find( const std::string& _name ) const;
+	TiXmlAttribute* FindOrCreate( const std::string& _name );
+#	endif
+
+
+private:
+	//*ME:	Because of hidden/disabled copy-construktor in TiXmlAttribute (sentinel-element),
+	//*ME:	this class must be also use a hidden/disabled copy-constructor !!!
+	TiXmlAttributeSet( const TiXmlAttributeSet& );	// not allowed
+	void operator=( const TiXmlAttributeSet& );	// not allowed (as TiXmlAttribute)
+
+	TiXmlAttribute sentinel;
+};
+
+
+/** The element is a container class. It has a value, the element name,
+	and can contain other elements, text, comments, and unknowns.
+	Elements also contain an arbitrary number of attributes.
+*/
+class TiXmlElement : public TiXmlNode
+{
+public:
+	/// Construct an element.
+	TiXmlElement (const char * in_value);
+
+	#ifdef TIXML_USE_STL
+	/// std::string constructor.
+	TiXmlElement( const std::string& _value );
+	#endif
+
+	TiXmlElement( const TiXmlElement& );
+
+	TiXmlElement& operator=( const TiXmlElement& base );
+
+	virtual ~TiXmlElement();
+
+	/** Given an attribute name, Attribute() returns the value
+		for the attribute of that name, or null if none exists.
+	*/
+	const char* Attribute( const char* name ) const;
+
+	/** Given an attribute name, Attribute() returns the value
+		for the attribute of that name, or null if none exists.
+		If the attribute exists and can be converted to an integer,
+		the integer value will be put in the return 'i', if 'i'
+		is non-null.
+	*/
+	const char* Attribute( const char* name, int* i ) const;
+
+	/** Given an attribute name, Attribute() returns the value
+		for the attribute of that name, or null if none exists.
+		If the attribute exists and can be converted to an double,
+		the double value will be put in the return 'd', if 'd'
+		is non-null.
+	*/
+	const char* Attribute( const char* name, double* d ) const;
+
+	/** QueryIntAttribute examines the attribute - it is an alternative to the
+		Attribute() method with richer error checking.
+		If the attribute is an integer, it is stored in 'value' and 
+		the call returns TIXML_SUCCESS. If it is not
+		an integer, it returns TIXML_WRONG_TYPE. If the attribute
+		does not exist, then TIXML_NO_ATTRIBUTE is returned.
+	*/	
+	int QueryIntAttribute( const char* name, int* _value ) const;
+	/// QueryUnsignedAttribute examines the attribute - see QueryIntAttribute().
+	int QueryUnsignedAttribute( const char* name, unsigned* _value ) const;
+	/** QueryBoolAttribute examines the attribute - see QueryIntAttribute(). 
+		Note that '1', 'true', or 'yes' are considered true, while '0', 'false'
+		and 'no' are considered false.
+	*/
+	int QueryBoolAttribute( const char* name, bool* _value ) const;
+	/// QueryDoubleAttribute examines the attribute - see QueryIntAttribute().
+	int QueryDoubleAttribute( const char* name, double* _value ) const;
+	/// QueryFloatAttribute examines the attribute - see QueryIntAttribute().
+	int QueryFloatAttribute( const char* name, float* _value ) const {
+		double d;
+		int result = QueryDoubleAttribute( name, &d );
+		if ( result == TIXML_SUCCESS ) {
+			*_value = (float)d;
+		}
+		return result;
+	}
+
+    #ifdef TIXML_USE_STL
+	/// QueryStringAttribute examines the attribute - see QueryIntAttribute().
+	int QueryStringAttribute( const char* name, std::string* _value ) const {
+		const char* cstr = Attribute( name );
+		if ( cstr ) {
+			*_value = std::string( cstr );
+			return TIXML_SUCCESS;
+		}
+		return TIXML_NO_ATTRIBUTE;
+	}
+
+	/** Template form of the attribute query which will try to read the
+		attribute into the specified type. Very easy, very powerful, but
+		be careful to make sure to call this with the correct type.
+		
+		NOTE: This method doesn't work correctly for 'string' types that contain spaces.
+
+		@return TIXML_SUCCESS, TIXML_WRONG_TYPE, or TIXML_NO_ATTRIBUTE
+	*/
+	template< typename T > int QueryValueAttribute( const std::string& name, T* outValue ) const
+	{
+		const TiXmlAttribute* node = attributeSet.Find( name );
+		if ( !node )
+			return TIXML_NO_ATTRIBUTE;
+
+		std::stringstream sstream( node->ValueStr() );
+		sstream >> *outValue;
+		if ( !sstream.fail() )
+			return TIXML_SUCCESS;
+		return TIXML_WRONG_TYPE;
+	}
+
+	int QueryValueAttribute( const std::string& name, std::string* outValue ) const
+	{
+		const TiXmlAttribute* node = attributeSet.Find( name );
+		if ( !node )
+			return TIXML_NO_ATTRIBUTE;
+		*outValue = node->ValueStr();
+		return TIXML_SUCCESS;
+	}
+	#endif
+
+	/** Sets an attribute of name to a given value. The attribute
+		will be created if it does not exist, or changed if it does.
+	*/
+	void SetAttribute( const char* name, const char * _value );
+
+    #ifdef TIXML_USE_STL
+	const std::string* Attribute( const std::string& name ) const;
+	const std::string* Attribute( const std::string& name, int* i ) const;
+	const std::string* Attribute( const std::string& name, double* d ) const;
+	int QueryIntAttribute( const std::string& name, int* _value ) const;
+	int QueryDoubleAttribute( const std::string& name, double* _value ) const;
+
+	/// STL std::string form.
+	void SetAttribute( const std::string& name, const std::string& _value );
+	///< STL std::string form.
+	void SetAttribute( const std::string& name, int _value );
+	///< STL std::string form.
+	void SetDoubleAttribute( const std::string& name, double value );
+	#endif
+
+	/** Sets an attribute of name to a given value. The attribute
+		will be created if it does not exist, or changed if it does.
+	*/
+	void SetAttribute( const char * name, int value );
+
+	/** Sets an attribute of name to a given value. The attribute
+		will be created if it does not exist, or changed if it does.
+	*/
+	void SetDoubleAttribute( const char * name, double value );
+
+	/** Deletes an attribute with the given name.
+	*/
+	void RemoveAttribute( const char * name );
+    #ifdef TIXML_USE_STL
+	void RemoveAttribute( const std::string& name )	{	RemoveAttribute (name.c_str ());	}	///< STL std::string form.
+	#endif
+
+	const TiXmlAttribute* FirstAttribute() const	{ return attributeSet.First(); }		///< Access the first attribute in this element.
+	TiXmlAttribute* FirstAttribute() 				{ return attributeSet.First(); }
+	const TiXmlAttribute* LastAttribute()	const 	{ return attributeSet.Last(); }		///< Access the last attribute in this element.
+	TiXmlAttribute* LastAttribute()					{ return attributeSet.Last(); }
+
+	/** Convenience function for easy access to the text inside an element. Although easy
+		and concise, GetText() is limited compared to getting the TiXmlText child
+		and accessing it directly.
+	
+		If the first child of 'this' is a TiXmlText, the GetText()
+		returns the character string of the Text node, else null is returned.
+
+		This is a convenient method for getting the text of simple contained text:
+		@verbatim
+		This is text
+		const char* str = fooElement->GetText();
+		@endverbatim
+
+		'str' will be a pointer to "This is text". 
+		
+		Note that this function can be misleading. If the element foo was created from
+		this XML:
+		@verbatim
+		This is text 
+		@endverbatim
+
+		then the value of str would be null. The first child node isn't a text node, it is
+		another element. From this XML:
+		@verbatim
+		This is text 
+		@endverbatim
+		GetText() will return "This is ".
+
+		WARNING: GetText() accesses a child node - don't become confused with the 
+				 similarly named TiXmlHandle::Text() and TiXmlNode::ToText() which are 
+				 safe type casts on the referenced node.
+	*/
+	const char* GetText() const;
+
+	/// Creates a new Element and returns it - the returned element is a copy.
+	virtual TiXmlNode* Clone() const;
+	// Print the Element to a FILE stream.
+	virtual void Print( FILE* cfile, int depth ) const;
+
+	/*	Attribtue parsing starts: next char past '<'
+						 returns: next char past '>'
+	*/
+	virtual const char* Parse( const char* p, TiXmlParsingData* data, TiXmlEncoding encoding );
+
+	virtual const TiXmlElement*     ToElement()     const { return this; } ///< Cast to a more defined type. Will return null not of the requested type.
+	virtual TiXmlElement*           ToElement()	          { return this; } ///< Cast to a more defined type. Will return null not of the requested type.
+
+	/** Walk the XML tree visiting this node and all of its children. 
+	*/
+	virtual bool Accept( TiXmlVisitor* visitor ) const;
+
+protected:
+
+	void CopyTo( TiXmlElement* target ) const;
+	void ClearThis();	// like clear, but initializes 'this' object as well
+
+	// Used to be public [internal use]
+	#ifdef TIXML_USE_STL
+	virtual void StreamIn( std::istream * in, TIXML_STRING * tag );
+	#endif
+	/*	[internal use]
+		Reads the "value" of the element -- another element, or text.
+		This should terminate with the current end tag.
+	*/
+	const char* ReadValue( const char* in, TiXmlParsingData* prevData, TiXmlEncoding encoding );
+
+private:
+	TiXmlAttributeSet attributeSet;
+};
+
+
+/**	An XML comment.
+*/
+class TiXmlComment : public TiXmlNode
+{
+public:
+	/// Constructs an empty comment.
+	TiXmlComment() : TiXmlNode( TiXmlNode::TINYXML_COMMENT ) {}
+	/// Construct a comment from text.
+	TiXmlComment( const char* _value ) : TiXmlNode( TiXmlNode::TINYXML_COMMENT ) {
+		SetValue( _value );
+	}
+	TiXmlComment( const TiXmlComment& );
+	TiXmlComment& operator=( const TiXmlComment& base );
+
+	virtual ~TiXmlComment()	{}
+
+	/// Returns a copy of this Comment.
+	virtual TiXmlNode* Clone() const;
+	// Write this Comment to a FILE stream.
+	virtual void Print( FILE* cfile, int depth ) const;
+
+	/*	Attribtue parsing starts: at the ! of the !--
+						 returns: next char past '>'
+	*/
+	virtual const char* Parse( const char* p, TiXmlParsingData* data, TiXmlEncoding encoding );
+
+	virtual const TiXmlComment*  ToComment() const	{ return this; } ///< Cast to a more defined type. Will return null not of the requested type.
+	virtual		  TiXmlComment*  ToComment()		{ return this; } ///< Cast to a more defined type. Will return null not of the requested type.
+
+	/** Walk the XML tree visiting this node and all of its children. 
+	*/
+	virtual bool Accept( TiXmlVisitor* visitor ) const;
+
+protected:
+	void CopyTo( TiXmlComment* target ) const;
+
+	// used to be public
+	#ifdef TIXML_USE_STL
+	virtual void StreamIn( std::istream * in, TIXML_STRING * tag );
+	#endif
+//	virtual void StreamOut( TIXML_OSTREAM * out ) const;
+
+private:
+
+};
+
+
+/** XML text. A text node can have 2 ways to output the next. "normal" output 
+	and CDATA. It will default to the mode it was parsed from the XML file and
+	you generally want to leave it alone, but you can change the output mode with 
+	SetCDATA() and query it with CDATA().
+*/
+class TiXmlText : public TiXmlNode
+{
+	friend class TiXmlElement;
+public:
+	/** Constructor for text element. By default, it is treated as 
+		normal, encoded text. If you want it be output as a CDATA text
+		element, set the parameter _cdata to 'true'
+	*/
+	TiXmlText (const char * initValue ) : TiXmlNode (TiXmlNode::TINYXML_TEXT)
+	{
+		SetValue( initValue );
+		cdata = false;
+	}
+	virtual ~TiXmlText() {}
+
+	#ifdef TIXML_USE_STL
+	/// Constructor.
+	TiXmlText( const std::string& initValue ) : TiXmlNode (TiXmlNode::TINYXML_TEXT)
+	{
+		SetValue( initValue );
+		cdata = false;
+	}
+	#endif
+
+	TiXmlText( const TiXmlText& copy ) : TiXmlNode( TiXmlNode::TINYXML_TEXT )	{ copy.CopyTo( this ); }
+	TiXmlText& operator=( const TiXmlText& base )							 	{ base.CopyTo( this ); return *this; }
+
+	// Write this text object to a FILE stream.
+	virtual void Print( FILE* cfile, int depth ) const;
+
+	/// Queries whether this represents text using a CDATA section.
+	bool CDATA() const				{ return cdata; }
+	/// Turns on or off a CDATA representation of text.
+	void SetCDATA( bool _cdata )	{ cdata = _cdata; }
+
+	virtual const char* Parse( const char* p, TiXmlParsingData* data, TiXmlEncoding encoding );
+
+	virtual const TiXmlText* ToText() const { return this; } ///< Cast to a more defined type. Will return null not of the requested type.
+	virtual TiXmlText*       ToText()       { return this; } ///< Cast to a more defined type. Will return null not of the requested type.
+
+	/** Walk the XML tree visiting this node and all of its children. 
+	*/
+	virtual bool Accept( TiXmlVisitor* content ) const;
+
+protected :
+	///  [internal use] Creates a new Element and returns it.
+	virtual TiXmlNode* Clone() const;
+	void CopyTo( TiXmlText* target ) const;
+
+	bool Blank() const;	// returns true if all white space and new lines
+	// [internal use]
+	#ifdef TIXML_USE_STL
+	virtual void StreamIn( std::istream * in, TIXML_STRING * tag );
+	#endif
+
+private:
+	bool cdata;			// true if this should be input and output as a CDATA style text element
+};
+
+
+/** In correct XML the declaration is the first entry in the file.
+	@verbatim
+		
+	@endverbatim
+
+	TinyXml will happily read or write files without a declaration,
+	however. There are 3 possible attributes to the declaration:
+	version, encoding, and standalone.
+
+	Note: In this version of the code, the attributes are
+	handled as special cases, not generic attributes, simply
+	because there can only be at most 3 and they are always the same.
+*/
+class TiXmlDeclaration : public TiXmlNode
+{
+public:
+	/// Construct an empty declaration.
+	TiXmlDeclaration()   : TiXmlNode( TiXmlNode::TINYXML_DECLARATION ) {}
+
+#ifdef TIXML_USE_STL
+	/// Constructor.
+	TiXmlDeclaration(	const std::string& _version,
+						const std::string& _encoding,
+						const std::string& _standalone );
+#endif
+
+	/// Construct.
+	TiXmlDeclaration(	const char* _version,
+						const char* _encoding,
+						const char* _standalone );
+
+	TiXmlDeclaration( const TiXmlDeclaration& copy );
+	TiXmlDeclaration& operator=( const TiXmlDeclaration& copy );
+
+	virtual ~TiXmlDeclaration()	{}
+
+	/// Version. Will return an empty string if none was found.
+	const char *Version() const			{ return version.c_str (); }
+	/// Encoding. Will return an empty string if none was found.
+	const char *Encoding() const		{ return encoding.c_str (); }
+	/// Is this a standalone document?
+	const char *Standalone() const		{ return standalone.c_str (); }
+
+	/// Creates a copy of this Declaration and returns it.
+	virtual TiXmlNode* Clone() const;
+	// Print this declaration to a FILE stream.
+	virtual void Print( FILE* cfile, int depth, TIXML_STRING* str ) const;
+	virtual void Print( FILE* cfile, int depth ) const {
+		Print( cfile, depth, 0 );
+	}
+
+	virtual const char* Parse( const char* p, TiXmlParsingData* data, TiXmlEncoding encoding );
+
+	virtual const TiXmlDeclaration* ToDeclaration() const { return this; } ///< Cast to a more defined type. Will return null not of the requested type.
+	virtual TiXmlDeclaration*       ToDeclaration()       { return this; } ///< Cast to a more defined type. Will return null not of the requested type.
+
+	/** Walk the XML tree visiting this node and all of its children. 
+	*/
+	virtual bool Accept( TiXmlVisitor* visitor ) const;
+
+protected:
+	void CopyTo( TiXmlDeclaration* target ) const;
+	// used to be public
+	#ifdef TIXML_USE_STL
+	virtual void StreamIn( std::istream * in, TIXML_STRING * tag );
+	#endif
+
+private:
+
+	TIXML_STRING version;
+	TIXML_STRING encoding;
+	TIXML_STRING standalone;
+};
+
+
+/** Any tag that tinyXml doesn't recognize is saved as an
+	unknown. It is a tag of text, but should not be modified.
+	It will be written back to the XML, unchanged, when the file
+	is saved.
+
+	DTD tags get thrown into TiXmlUnknowns.
+*/
+class TiXmlUnknown : public TiXmlNode
+{
+public:
+	TiXmlUnknown() : TiXmlNode( TiXmlNode::TINYXML_UNKNOWN )	{}
+	virtual ~TiXmlUnknown() {}
+
+	TiXmlUnknown( const TiXmlUnknown& copy ) : TiXmlNode( TiXmlNode::TINYXML_UNKNOWN )		{ copy.CopyTo( this ); }
+	TiXmlUnknown& operator=( const TiXmlUnknown& copy )										{ copy.CopyTo( this ); return *this; }
+
+	/// Creates a copy of this Unknown and returns it.
+	virtual TiXmlNode* Clone() const;
+	// Print this Unknown to a FILE stream.
+	virtual void Print( FILE* cfile, int depth ) const;
+
+	virtual const char* Parse( const char* p, TiXmlParsingData* data, TiXmlEncoding encoding );
+
+	virtual const TiXmlUnknown*     ToUnknown()     const	{ return this; } ///< Cast to a more defined type. Will return null not of the requested type.
+	virtual TiXmlUnknown*           ToUnknown()				{ return this; } ///< Cast to a more defined type. Will return null not of the requested type.
+
+	/** Walk the XML tree visiting this node and all of its children. 
+	*/
+	virtual bool Accept( TiXmlVisitor* content ) const;
+
+protected:
+	void CopyTo( TiXmlUnknown* target ) const;
+
+	#ifdef TIXML_USE_STL
+	virtual void StreamIn( std::istream * in, TIXML_STRING * tag );
+	#endif
+
+private:
+
+};
+
+
+/** Always the top level node. A document binds together all the
+	XML pieces. It can be saved, loaded, and printed to the screen.
+	The 'value' of a document node is the xml file name.
+*/
+class TiXmlDocument : public TiXmlNode
+{
+public:
+	/// Create an empty document, that has no name.
+	TiXmlDocument();
+	/// Create a document with a name. The name of the document is also the filename of the xml.
+	TiXmlDocument( const char * documentName );
+
+	#ifdef TIXML_USE_STL
+	/// Constructor.
+	TiXmlDocument( const std::string& documentName );
+	#endif
+
+	TiXmlDocument( const TiXmlDocument& copy );
+	TiXmlDocument& operator=( const TiXmlDocument& copy );
+
+	virtual ~TiXmlDocument() {}
+
+	/** Load a file using the current document value.
+		Returns true if successful. Will delete any existing
+		document data before loading.
+	*/
+	bool LoadFile( TiXmlEncoding encoding = TIXML_DEFAULT_ENCODING );
+	/// Save a file using the current document value. Returns true if successful.
+	bool SaveFile() const;
+	/// Load a file using the given filename. Returns true if successful.
+	bool LoadFile( const char * filename, TiXmlEncoding encoding = TIXML_DEFAULT_ENCODING );
+	/// Save a file using the given filename. Returns true if successful.
+	bool SaveFile( const char * filename ) const;
+	/** Load a file using the given FILE*. Returns true if successful. Note that this method
+		doesn't stream - the entire object pointed at by the FILE*
+		will be interpreted as an XML file. TinyXML doesn't stream in XML from the current
+		file location. Streaming may be added in the future.
+	*/
+	bool LoadFile( FILE*, TiXmlEncoding encoding = TIXML_DEFAULT_ENCODING );
+	/// Save a file using the given FILE*. Returns true if successful.
+	bool SaveFile( FILE* ) const;
+
+	#ifdef TIXML_USE_STL
+	bool LoadFile( const std::string& filename, TiXmlEncoding encoding = TIXML_DEFAULT_ENCODING )			///< STL std::string version.
+	{
+		return LoadFile( filename.c_str(), encoding );
+	}
+	bool SaveFile( const std::string& filename ) const		///< STL std::string version.
+	{
+		return SaveFile( filename.c_str() );
+	}
+	#endif
+
+	/** Parse the given null terminated block of xml data. Passing in an encoding to this
+		method (either TIXML_ENCODING_LEGACY or TIXML_ENCODING_UTF8 will force TinyXml
+		to use that encoding, regardless of what TinyXml might otherwise try to detect.
+	*/
+	virtual const char* Parse( const char* p, TiXmlParsingData* data = 0, TiXmlEncoding encoding = TIXML_DEFAULT_ENCODING );
+
+	/** Get the root element -- the only top level element -- of the document.
+		In well formed XML, there should only be one. TinyXml is tolerant of
+		multiple elements at the document level.
+	*/
+	const TiXmlElement* RootElement() const		{ return FirstChildElement(); }
+	TiXmlElement* RootElement()					{ return FirstChildElement(); }
+
+	/** If an error occurs, Error will be set to true. Also,
+		- The ErrorId() will contain the integer identifier of the error (not generally useful)
+		- The ErrorDesc() method will return the name of the error. (very useful)
+		- The ErrorRow() and ErrorCol() will return the location of the error (if known)
+	*/	
+	bool Error() const						{ return error; }
+
+	/// Contains a textual (english) description of the error if one occurs.
+	const char * ErrorDesc() const	{ return errorDesc.c_str (); }
+
+	/** Generally, you probably want the error string ( ErrorDesc() ). But if you
+		prefer the ErrorId, this function will fetch it.
+	*/
+	int ErrorId()	const				{ return errorId; }
+
+	/** Returns the location (if known) of the error. The first column is column 1, 
+		and the first row is row 1. A value of 0 means the row and column wasn't applicable
+		(memory errors, for example, have no row/column) or the parser lost the error. (An
+		error in the error reporting, in that case.)
+
+		@sa SetTabSize, Row, Column
+	*/
+	int ErrorRow() const	{ return errorLocation.row+1; }
+	int ErrorCol() const	{ return errorLocation.col+1; }	///< The column where the error occurred. See ErrorRow()
+
+	/** SetTabSize() allows the error reporting functions (ErrorRow() and ErrorCol())
+		to report the correct values for row and column. It does not change the output
+		or input in any way.
+		
+		By calling this method, with a tab size
+		greater than 0, the row and column of each node and attribute is stored
+		when the file is loaded. Very useful for tracking the DOM back in to
+		the source file.
+
+		The tab size is required for calculating the location of nodes. If not
+		set, the default of 4 is used. The tabsize is set per document. Setting
+		the tabsize to 0 disables row/column tracking.
+
+		Note that row and column tracking is not supported when using operator>>.
+
+		The tab size needs to be enabled before the parse or load. Correct usage:
+		@verbatim
+		TiXmlDocument doc;
+		doc.SetTabSize( 8 );
+		doc.Load( "myfile.xml" );
+		@endverbatim
+
+		@sa Row, Column
+	*/
+	void SetTabSize( int _tabsize )		{ tabsize = _tabsize; }
+
+	int TabSize() const	{ return tabsize; }
+
+	/** If you have handled the error, it can be reset with this call. The error
+		state is automatically cleared if you Parse a new XML block.
+	*/
+	void ClearError()						{	error = false; 
+												errorId = 0; 
+												errorDesc = ""; 
+												errorLocation.row = errorLocation.col = 0; 
+												//errorLocation.last = 0; 
+											}
+
+	/** Write the document to standard out using formatted printing ("pretty print"). */
+	void Print() const						{ Print( stdout, 0 ); }
+
+	/* Write the document to a string using formatted printing ("pretty print"). This
+		will allocate a character array (new char[]) and return it as a pointer. The
+		calling code pust call delete[] on the return char* to avoid a memory leak.
+	*/
+	//char* PrintToMemory() const; 
+
+	/// Print this Document to a FILE stream.
+	virtual void Print( FILE* cfile, int depth = 0 ) const;
+	// [internal use]
+	void SetError( int err, const char* errorLocation, TiXmlParsingData* prevData, TiXmlEncoding encoding );
+
+	virtual const TiXmlDocument*    ToDocument()    const { return this; } ///< Cast to a more defined type. Will return null not of the requested type.
+	virtual TiXmlDocument*          ToDocument()          { return this; } ///< Cast to a more defined type. Will return null not of the requested type.
+
+	/** Walk the XML tree visiting this node and all of its children. 
+	*/
+	virtual bool Accept( TiXmlVisitor* content ) const;
+
+protected :
+	// [internal use]
+	virtual TiXmlNode* Clone() const;
+	#ifdef TIXML_USE_STL
+	virtual void StreamIn( std::istream * in, TIXML_STRING * tag );
+	#endif
+
+private:
+	void CopyTo( TiXmlDocument* target ) const;
+
+	bool error;
+	int  errorId;
+	TIXML_STRING errorDesc;
+	int tabsize;
+	TiXmlCursor errorLocation;
+	bool useMicrosoftBOM;		// the UTF-8 BOM were found when read. Note this, and try to write.
+};
+
+
+/**
+	A TiXmlHandle is a class that wraps a node pointer with null checks; this is
+	an incredibly useful thing. Note that TiXmlHandle is not part of the TinyXml
+	DOM structure. It is a separate utility class.
+
+	Take an example:
+	@verbatim
+	
+		
+			
+			
+		
+	
+	@endverbatim
+
+	Assuming you want the value of "attributeB" in the 2nd "Child" element, it's very 
+	easy to write a *lot* of code that looks like:
+
+	@verbatim
+	TiXmlElement* root = document.FirstChildElement( "Document" );
+	if ( root )
+	{
+		TiXmlElement* element = root->FirstChildElement( "Element" );
+		if ( element )
+		{
+			TiXmlElement* child = element->FirstChildElement( "Child" );
+			if ( child )
+			{
+				TiXmlElement* child2 = child->NextSiblingElement( "Child" );
+				if ( child2 )
+				{
+					// Finally do something useful.
+	@endverbatim
+
+	And that doesn't even cover "else" cases. TiXmlHandle addresses the verbosity
+	of such code. A TiXmlHandle checks for null	pointers so it is perfectly safe 
+	and correct to use:
+
+	@verbatim
+	TiXmlHandle docHandle( &document );
+	TiXmlElement* child2 = docHandle.FirstChild( "Document" ).FirstChild( "Element" ).Child( "Child", 1 ).ToElement();
+	if ( child2 )
+	{
+		// do something useful
+	@endverbatim
+
+	Which is MUCH more concise and useful.
+
+	It is also safe to copy handles - internally they are nothing more than node pointers.
+	@verbatim
+	TiXmlHandle handleCopy = handle;
+	@endverbatim
+
+	What they should not be used for is iteration:
+
+	@verbatim
+	int i=0; 
+	while ( true )
+	{
+		TiXmlElement* child = docHandle.FirstChild( "Document" ).FirstChild( "Element" ).Child( "Child", i ).ToElement();
+		if ( !child )
+			break;
+		// do something
+		++i;
+	}
+	@endverbatim
+
+	It seems reasonable, but it is in fact two embedded while loops. The Child method is 
+	a linear walk to find the element, so this code would iterate much more than it needs 
+	to. Instead, prefer:
+
+	@verbatim
+	TiXmlElement* child = docHandle.FirstChild( "Document" ).FirstChild( "Element" ).FirstChild( "Child" ).ToElement();
+
+	for( child; child; child=child->NextSiblingElement() )
+	{
+		// do something
+	}
+	@endverbatim
+*/
+class TiXmlHandle
+{
+public:
+	/// Create a handle from any node (at any depth of the tree.) This can be a null pointer.
+	TiXmlHandle( TiXmlNode* _node )					{ this->node = _node; }
+	/// Copy constructor
+	TiXmlHandle( const TiXmlHandle& ref )			{ this->node = ref.node; }
+	TiXmlHandle operator=( const TiXmlHandle& ref ) { if ( &ref != this ) this->node = ref.node; return *this; }
+
+	/// Return a handle to the first child node.
+	TiXmlHandle FirstChild() const;
+	/// Return a handle to the first child node with the given name.
+	TiXmlHandle FirstChild( const char * value ) const;
+	/// Return a handle to the first child element.
+	TiXmlHandle FirstChildElement() const;
+	/// Return a handle to the first child element with the given name.
+	TiXmlHandle FirstChildElement( const char * value ) const;
+
+	/** Return a handle to the "index" child with the given name. 
+		The first child is 0, the second 1, etc.
+	*/
+	TiXmlHandle Child( const char* value, int index ) const;
+	/** Return a handle to the "index" child. 
+		The first child is 0, the second 1, etc.
+	*/
+	TiXmlHandle Child( int index ) const;
+	/** Return a handle to the "index" child element with the given name. 
+		The first child element is 0, the second 1, etc. Note that only TiXmlElements
+		are indexed: other types are not counted.
+	*/
+	TiXmlHandle ChildElement( const char* value, int index ) const;
+	/** Return a handle to the "index" child element. 
+		The first child element is 0, the second 1, etc. Note that only TiXmlElements
+		are indexed: other types are not counted.
+	*/
+	TiXmlHandle ChildElement( int index ) const;
+
+	#ifdef TIXML_USE_STL
+	TiXmlHandle FirstChild( const std::string& _value ) const				{ return FirstChild( _value.c_str() ); }
+	TiXmlHandle FirstChildElement( const std::string& _value ) const		{ return FirstChildElement( _value.c_str() ); }
+
+	TiXmlHandle Child( const std::string& _value, int index ) const			{ return Child( _value.c_str(), index ); }
+	TiXmlHandle ChildElement( const std::string& _value, int index ) const	{ return ChildElement( _value.c_str(), index ); }
+	#endif
+
+	/** Return the handle as a TiXmlNode. This may return null.
+	*/
+	TiXmlNode* ToNode() const			{ return node; } 
+	/** Return the handle as a TiXmlElement. This may return null.
+	*/
+	TiXmlElement* ToElement() const		{ return ( ( node && node->ToElement() ) ? node->ToElement() : 0 ); }
+	/**	Return the handle as a TiXmlText. This may return null.
+	*/
+	TiXmlText* ToText() const			{ return ( ( node && node->ToText() ) ? node->ToText() : 0 ); }
+	/** Return the handle as a TiXmlUnknown. This may return null.
+	*/
+	TiXmlUnknown* ToUnknown() const		{ return ( ( node && node->ToUnknown() ) ? node->ToUnknown() : 0 ); }
+
+	/** @deprecated use ToNode. 
+		Return the handle as a TiXmlNode. This may return null.
+	*/
+	TiXmlNode* Node() const			{ return ToNode(); } 
+	/** @deprecated use ToElement. 
+		Return the handle as a TiXmlElement. This may return null.
+	*/
+	TiXmlElement* Element() const	{ return ToElement(); }
+	/**	@deprecated use ToText()
+		Return the handle as a TiXmlText. This may return null.
+	*/
+	TiXmlText* Text() const			{ return ToText(); }
+	/** @deprecated use ToUnknown()
+		Return the handle as a TiXmlUnknown. This may return null.
+	*/
+	TiXmlUnknown* Unknown() const	{ return ToUnknown(); }
+
+private:
+	TiXmlNode* node;
+};
+
+
+/** Print to memory functionality. The TiXmlPrinter is useful when you need to:
+
+	-# Print to memory (especially in non-STL mode)
+	-# Control formatting (line endings, etc.)
+
+	When constructed, the TiXmlPrinter is in its default "pretty printing" mode.
+	Before calling Accept() you can call methods to control the printing
+	of the XML document. After TiXmlNode::Accept() is called, the printed document can
+	be accessed via the CStr(), Str(), and Size() methods.
+
+	TiXmlPrinter uses the Visitor API.
+	@verbatim
+	TiXmlPrinter printer;
+	printer.SetIndent( "\t" );
+
+	doc.Accept( &printer );
+	fprintf( stdout, "%s", printer.CStr() );
+	@endverbatim
+*/
+class TiXmlPrinter : public TiXmlVisitor
+{
+public:
+	TiXmlPrinter() : depth( 0 ), simpleTextPrint( false ),
+					 buffer(), indent( "    " ), lineBreak( "\n" ) {}
+
+	virtual bool VisitEnter( const TiXmlDocument& doc );
+	virtual bool VisitExit( const TiXmlDocument& doc );
+
+	virtual bool VisitEnter( const TiXmlElement& element, const TiXmlAttribute* firstAttribute );
+	virtual bool VisitExit( const TiXmlElement& element );
+
+	virtual bool Visit( const TiXmlDeclaration& declaration );
+	virtual bool Visit( const TiXmlText& text );
+	virtual bool Visit( const TiXmlComment& comment );
+	virtual bool Visit( const TiXmlUnknown& unknown );
+
+	/** Set the indent characters for printing. By default 4 spaces
+		but tab (\t) is also useful, or null/empty string for no indentation.
+	*/
+	void SetIndent( const char* _indent )			{ indent = _indent ? _indent : "" ; }
+	/// Query the indention string.
+	const char* Indent()							{ return indent.c_str(); }
+	/** Set the line breaking string. By default set to newline (\n). 
+		Some operating systems prefer other characters, or can be
+		set to the null/empty string for no indenation.
+	*/
+	void SetLineBreak( const char* _lineBreak )		{ lineBreak = _lineBreak ? _lineBreak : ""; }
+	/// Query the current line breaking string.
+	const char* LineBreak()							{ return lineBreak.c_str(); }
+
+	/** Switch over to "stream printing" which is the most dense formatting without 
+		linebreaks. Common when the XML is needed for network transmission.
+	*/
+	void SetStreamPrinting()						{ indent = "";
+													  lineBreak = "";
+													}	
+	/// Return the result.
+	const char* CStr()								{ return buffer.c_str(); }
+	/// Return the length of the result string.
+	size_t Size()									{ return buffer.size(); }
+
+	#ifdef TIXML_USE_STL
+	/// Return the result.
+	const std::string& Str()						{ return buffer; }
+	#endif
+
+private:
+	void DoIndent()	{
+		for( int i=0; i
+#include 
+
+#include "tinyxml.h"
+
+//#define DEBUG_PARSER
+#if defined( DEBUG_PARSER )
+#	if defined( DEBUG ) && defined( _MSC_VER )
+#		include 
+#		define TIXML_LOG OutputDebugString
+#	else
+#		define TIXML_LOG printf
+#	endif
+#endif
+
+// Note tha "PutString" hardcodes the same list. This
+// is less flexible than it appears. Changing the entries
+// or order will break putstring.	
+TiXmlBase::Entity TiXmlBase::entity[ TiXmlBase::NUM_ENTITY ] = 
+{
+	{ "&",  5, '&' },
+	{ "<",   4, '<' },
+	{ ">",   4, '>' },
+	{ """, 6, '\"' },
+	{ "'", 6, '\'' }
+};
+
+// Bunch of unicode info at:
+//		http://www.unicode.org/faq/utf_bom.html
+// Including the basic of this table, which determines the #bytes in the
+// sequence from the lead byte. 1 placed for invalid sequences --
+// although the result will be junk, pass it through as much as possible.
+// Beware of the non-characters in UTF-8:	
+//				ef bb bf (Microsoft "lead bytes")
+//				ef bf be
+//				ef bf bf 
+
+const unsigned char TIXML_UTF_LEAD_0 = 0xefU;
+const unsigned char TIXML_UTF_LEAD_1 = 0xbbU;
+const unsigned char TIXML_UTF_LEAD_2 = 0xbfU;
+
+const int TiXmlBase::utf8ByteTable[256] = 
+{
+	//	0	1	2	3	4	5	6	7	8	9	a	b	c	d	e	f
+		1,	1,	1,	1,	1,	1,	1,	1,	1,	1,	1,	1,	1,	1,	1,	1,	// 0x00
+		1,	1,	1,	1,	1,	1,	1,	1,	1,	1,	1,	1,	1,	1,	1,	1,	// 0x10
+		1,	1,	1,	1,	1,	1,	1,	1,	1,	1,	1,	1,	1,	1,	1,	1,	// 0x20
+		1,	1,	1,	1,	1,	1,	1,	1,	1,	1,	1,	1,	1,	1,	1,	1,	// 0x30
+		1,	1,	1,	1,	1,	1,	1,	1,	1,	1,	1,	1,	1,	1,	1,	1,	// 0x40
+		1,	1,	1,	1,	1,	1,	1,	1,	1,	1,	1,	1,	1,	1,	1,	1,	// 0x50
+		1,	1,	1,	1,	1,	1,	1,	1,	1,	1,	1,	1,	1,	1,	1,	1,	// 0x60
+		1,	1,	1,	1,	1,	1,	1,	1,	1,	1,	1,	1,	1,	1,	1,	1,	// 0x70	End of ASCII range
+		1,	1,	1,	1,	1,	1,	1,	1,	1,	1,	1,	1,	1,	1,	1,	1,	// 0x80 0x80 to 0xc1 invalid
+		1,	1,	1,	1,	1,	1,	1,	1,	1,	1,	1,	1,	1,	1,	1,	1,	// 0x90 
+		1,	1,	1,	1,	1,	1,	1,	1,	1,	1,	1,	1,	1,	1,	1,	1,	// 0xa0 
+		1,	1,	1,	1,	1,	1,	1,	1,	1,	1,	1,	1,	1,	1,	1,	1,	// 0xb0 
+		1,	1,	2,	2,	2,	2,	2,	2,	2,	2,	2,	2,	2,	2,	2,	2,	// 0xc0 0xc2 to 0xdf 2 byte
+		2,	2,	2,	2,	2,	2,	2,	2,	2,	2,	2,	2,	2,	2,	2,	2,	// 0xd0
+		3,	3,	3,	3,	3,	3,	3,	3,	3,	3,	3,	3,	3,	3,	3,	3,	// 0xe0 0xe0 to 0xef 3 byte
+		4,	4,	4,	4,	4,	1,	1,	1,	1,	1,	1,	1,	1,	1,	1,	1	// 0xf0 0xf0 to 0xf4 4 byte, 0xf5 and higher invalid
+};
+
+
+void TiXmlBase::ConvertUTF32ToUTF8( unsigned long input, char* output, int* length )
+{
+	const unsigned long BYTE_MASK = 0xBF;
+	const unsigned long BYTE_MARK = 0x80;
+	const unsigned long FIRST_BYTE_MARK[7] = { 0x00, 0x00, 0xC0, 0xE0, 0xF0, 0xF8, 0xFC };
+
+	if (input < 0x80) 
+		*length = 1;
+	else if ( input < 0x800 )
+		*length = 2;
+	else if ( input < 0x10000 )
+		*length = 3;
+	else if ( input < 0x200000 )
+		*length = 4;
+	else
+		{ *length = 0; return; }	// This code won't covert this correctly anyway.
+
+	output += *length;
+
+	// Scary scary fall throughs.
+	switch (*length) 
+	{
+		case 4:
+			--output; 
+			*output = (char)((input | BYTE_MARK) & BYTE_MASK); 
+			input >>= 6;
+			/* Fall through */
+		case 3:
+			--output; 
+			*output = (char)((input | BYTE_MARK) & BYTE_MASK); 
+			input >>= 6;
+			/* Fall through */
+		case 2:
+			--output; 
+			*output = (char)((input | BYTE_MARK) & BYTE_MASK); 
+			input >>= 6;
+			/* Fall through */
+		case 1:
+			--output; 
+			*output = (char)(input | FIRST_BYTE_MARK[*length]);
+			break;
+	}
+}
+
+
+/*static*/ int TiXmlBase::IsAlpha( unsigned char anyByte, TiXmlEncoding /*encoding*/ )
+{
+	// This will only work for low-ascii, everything else is assumed to be a valid
+	// letter. I'm not sure this is the best approach, but it is quite tricky trying
+	// to figure out alphabetical vs. not across encoding. So take a very 
+	// conservative approach.
+
+//	if ( encoding == TIXML_ENCODING_UTF8 )
+//	{
+		if ( anyByte < 127 )
+			return isalpha( anyByte );
+		else
+			return 1;	// What else to do? The unicode set is huge...get the english ones right.
+//	}
+//	else
+//	{
+//		return isalpha( anyByte );
+//	}
+}
+
+
+/*static*/ int TiXmlBase::IsAlphaNum( unsigned char anyByte, TiXmlEncoding /*encoding*/ )
+{
+	// This will only work for low-ascii, everything else is assumed to be a valid
+	// letter. I'm not sure this is the best approach, but it is quite tricky trying
+	// to figure out alphabetical vs. not across encoding. So take a very 
+	// conservative approach.
+
+//	if ( encoding == TIXML_ENCODING_UTF8 )
+//	{
+		if ( anyByte < 127 )
+			return isalnum( anyByte );
+		else
+			return 1;	// What else to do? The unicode set is huge...get the english ones right.
+//	}
+//	else
+//	{
+//		return isalnum( anyByte );
+//	}
+}
+
+
+class TiXmlParsingData
+{
+	friend class TiXmlDocument;
+  public:
+	void Stamp( const char* now, TiXmlEncoding encoding );
+
+	const TiXmlCursor& Cursor() const	{ return cursor; }
+
+  private:
+	// Only used by the document!
+	TiXmlParsingData( const char* start, int _tabsize, int row, int col )
+	{
+		assert( start );
+		stamp = start;
+		tabsize = _tabsize;
+		cursor.row = row;
+		cursor.col = col;
+	}
+
+	TiXmlCursor		cursor;
+	const char*		stamp;
+	int				tabsize;
+};
+
+
+void TiXmlParsingData::Stamp( const char* now, TiXmlEncoding encoding )
+{
+	assert( now );
+
+	// Do nothing if the tabsize is 0.
+	if ( tabsize < 1 )
+	{
+		return;
+	}
+
+	// Get the current row, column.
+	int row = cursor.row;
+	int col = cursor.col;
+	const char* p = stamp;
+	assert( p );
+
+	while ( p < now )
+	{
+		// Treat p as unsigned, so we have a happy compiler.
+		const unsigned char* pU = (const unsigned char*)p;
+
+		// Code contributed by Fletcher Dunn: (modified by lee)
+		switch (*pU) {
+			case 0:
+				// We *should* never get here, but in case we do, don't
+				// advance past the terminating null character, ever
+				return;
+
+			case '\r':
+				// bump down to the next line
+				++row;
+				col = 0;				
+				// Eat the character
+				++p;
+
+				// Check for \r\n sequence, and treat this as a single character
+				if (*p == '\n') {
+					++p;
+				}
+				break;
+
+			case '\n':
+				// bump down to the next line
+				++row;
+				col = 0;
+
+				// Eat the character
+				++p;
+
+				// Check for \n\r sequence, and treat this as a single
+				// character.  (Yes, this bizarre thing does occur still
+				// on some arcane platforms...)
+				if (*p == '\r') {
+					++p;
+				}
+				break;
+
+			case '\t':
+				// Eat the character
+				++p;
+
+				// Skip to next tab stop
+				col = (col / tabsize + 1) * tabsize;
+				break;
+
+			case TIXML_UTF_LEAD_0:
+				if ( encoding == TIXML_ENCODING_UTF8 )
+				{
+					if ( *(p+1) && *(p+2) )
+					{
+						// In these cases, don't advance the column. These are
+						// 0-width spaces.
+						if ( *(pU+1)==TIXML_UTF_LEAD_1 && *(pU+2)==TIXML_UTF_LEAD_2 )
+							p += 3;	
+						else if ( *(pU+1)==0xbfU && *(pU+2)==0xbeU )
+							p += 3;	
+						else if ( *(pU+1)==0xbfU && *(pU+2)==0xbfU )
+							p += 3;	
+						else
+							{ p +=3; ++col; }	// A normal character.
+					}
+				}
+				else
+				{
+					++p;
+					++col;
+				}
+				break;
+
+			default:
+				if ( encoding == TIXML_ENCODING_UTF8 )
+				{
+					// Eat the 1 to 4 byte utf8 character.
+					int step = TiXmlBase::utf8ByteTable[*((const unsigned char*)p)];
+					if ( step == 0 )
+						step = 1;		// Error case from bad encoding, but handle gracefully.
+					p += step;
+
+					// Just advance one column, of course.
+					++col;
+				}
+				else
+				{
+					++p;
+					++col;
+				}
+				break;
+		}
+	}
+	cursor.row = row;
+	cursor.col = col;
+	assert( cursor.row >= -1 );
+	assert( cursor.col >= -1 );
+	stamp = p;
+	assert( stamp );
+}
+
+
+const char* TiXmlBase::SkipWhiteSpace( const char* p, TiXmlEncoding encoding )
+{
+	if ( !p || !*p )
+	{
+		return 0;
+	}
+	if ( encoding == TIXML_ENCODING_UTF8 )
+	{
+		while ( *p )
+		{
+			const unsigned char* pU = (const unsigned char*)p;
+			
+			// Skip the stupid Microsoft UTF-8 Byte order marks
+			if (	*(pU+0)==TIXML_UTF_LEAD_0
+				 && *(pU+1)==TIXML_UTF_LEAD_1 
+				 && *(pU+2)==TIXML_UTF_LEAD_2 )
+			{
+				p += 3;
+				continue;
+			}
+			else if(*(pU+0)==TIXML_UTF_LEAD_0
+				 && *(pU+1)==0xbfU
+				 && *(pU+2)==0xbeU )
+			{
+				p += 3;
+				continue;
+			}
+			else if(*(pU+0)==TIXML_UTF_LEAD_0
+				 && *(pU+1)==0xbfU
+				 && *(pU+2)==0xbfU )
+			{
+				p += 3;
+				continue;
+			}
+
+			if ( IsWhiteSpace( *p ) )		// Still using old rules for white space.
+				++p;
+			else
+				break;
+		}
+	}
+	else
+	{
+		while ( *p && IsWhiteSpace( *p ) )
+			++p;
+	}
+
+	return p;
+}
+
+#ifdef TIXML_USE_STL
+/*static*/ bool TiXmlBase::StreamWhiteSpace( std::istream * in, TIXML_STRING * tag )
+{
+	for( ;; )
+	{
+		if ( !in->good() ) return false;
+
+		int c = in->peek();
+		// At this scope, we can't get to a document. So fail silently.
+		if ( !IsWhiteSpace( c ) || c <= 0 )
+			return true;
+
+		*tag += (char) in->get();
+	}
+}
+
+/*static*/ bool TiXmlBase::StreamTo( std::istream * in, int character, TIXML_STRING * tag )
+{
+	//assert( character > 0 && character < 128 );	// else it won't work in utf-8
+	while ( in->good() )
+	{
+		int c = in->peek();
+		if ( c == character )
+			return true;
+		if ( c <= 0 )		// Silent failure: can't get document at this scope
+			return false;
+
+		in->get();
+		*tag += (char) c;
+	}
+	return false;
+}
+#endif
+
+// One of TinyXML's more performance demanding functions. Try to keep the memory overhead down. The
+// "assign" optimization removes over 10% of the execution time.
+//
+const char* TiXmlBase::ReadName( const char* p, TIXML_STRING * name, TiXmlEncoding encoding )
+{
+	// Oddly, not supported on some compilers,
+	//name->clear();
+	// So use this:
+	*name = "";
+	assert( p );
+
+	// Names start with letters or underscores.
+	// Of course, in unicode, tinyxml has no idea what a letter *is*. The
+	// algorithm is generous.
+	//
+	// After that, they can be letters, underscores, numbers,
+	// hyphens, or colons. (Colons are valid only for namespaces,
+	// but tinyxml can't tell namespaces from names.)
+	if (    p && *p 
+		 && ( IsAlpha( (unsigned char) *p, encoding ) || *p == '_' ) )
+	{
+		const char* start = p;
+		while(		p && *p
+				&&	(		IsAlphaNum( (unsigned char ) *p, encoding ) 
+						 || *p == '_'
+						 || *p == '-'
+						 || *p == '.'
+						 || *p == ':' ) )
+		{
+			//(*name) += *p; // expensive
+			++p;
+		}
+		if ( p-start > 0 ) {
+			name->assign( start, p-start );
+		}
+		return p;
+	}
+	return 0;
+}
+
+const char* TiXmlBase::GetEntity( const char* p, char* value, int* length, TiXmlEncoding encoding )
+{
+	// Presume an entity, and pull it out.
+    TIXML_STRING ent;
+	int i;
+	*length = 0;
+
+	if ( *(p+1) && *(p+1) == '#' && *(p+2) )
+	{
+		unsigned long ucs = 0;
+		ptrdiff_t delta = 0;
+		unsigned mult = 1;
+
+		if ( *(p+2) == 'x' )
+		{
+			// Hexadecimal.
+			if ( !*(p+3) ) return 0;
+
+			const char* q = p+3;
+			q = strchr( q, ';' );
+
+			if ( !q || !*q ) return 0;
+
+			delta = q-p;
+			--q;
+
+			while ( *q != 'x' )
+			{
+				if ( *q >= '0' && *q <= '9' )
+					ucs += mult * (*q - '0');
+				else if ( *q >= 'a' && *q <= 'f' )
+					ucs += mult * (*q - 'a' + 10);
+				else if ( *q >= 'A' && *q <= 'F' )
+					ucs += mult * (*q - 'A' + 10 );
+				else 
+					return 0;
+				mult *= 16;
+				--q;
+			}
+		}
+		else
+		{
+			// Decimal.
+			if ( !*(p+2) ) return 0;
+
+			const char* q = p+2;
+			q = strchr( q, ';' );
+
+			if ( !q || !*q ) return 0;
+
+			delta = q-p;
+			--q;
+
+			while ( *q != '#' )
+			{
+				if ( *q >= '0' && *q <= '9' )
+					ucs += mult * (*q - '0');
+				else 
+					return 0;
+				mult *= 10;
+				--q;
+			}
+		}
+		if ( encoding == TIXML_ENCODING_UTF8 )
+		{
+			// convert the UCS to UTF-8
+			ConvertUTF32ToUTF8( ucs, value, length );
+		}
+		else
+		{
+			*value = (char)ucs;
+			*length = 1;
+		}
+		return p + delta + 1;
+	}
+
+	// Now try to match it.
+	for( i=0; iappend( cArr, len );
+		}
+	}
+	else
+	{
+		bool whitespace = false;
+
+		// Remove leading white space:
+		p = SkipWhiteSpace( p, encoding );
+		while (	   p && *p
+				&& !StringEqual( p, endTag, caseInsensitive, encoding ) )
+		{
+			if ( *p == '\r' || *p == '\n' )
+			{
+				whitespace = true;
+				++p;
+			}
+			else if ( IsWhiteSpace( *p ) )
+			{
+				whitespace = true;
+				++p;
+			}
+			else
+			{
+				// If we've found whitespace, add it before the
+				// new character. Any whitespace just becomes a space.
+				if ( whitespace )
+				{
+					(*text) += ' ';
+					whitespace = false;
+				}
+				int len;
+				char cArr[4] = { 0, 0, 0, 0 };
+				p = GetChar( p, cArr, &len, encoding );
+				if ( len == 1 )
+					(*text) += cArr[0];	// more efficient
+				else
+					text->append( cArr, len );
+			}
+		}
+	}
+	if ( p && *p )
+		p += strlen( endTag );
+	return ( p && *p ) ? p : 0;
+}
+
+#ifdef TIXML_USE_STL
+
+void TiXmlDocument::StreamIn( std::istream * in, TIXML_STRING * tag )
+{
+	// The basic issue with a document is that we don't know what we're
+	// streaming. Read something presumed to be a tag (and hope), then
+	// identify it, and call the appropriate stream method on the tag.
+	//
+	// This "pre-streaming" will never read the closing ">" so the
+	// sub-tag can orient itself.
+
+	if ( !StreamTo( in, '<', tag ) ) 
+	{
+		SetError( TIXML_ERROR_PARSING_EMPTY, 0, 0, TIXML_ENCODING_UNKNOWN );
+		return;
+	}
+
+	while ( in->good() )
+	{
+		int tagIndex = (int) tag->length();
+		while ( in->good() && in->peek() != '>' )
+		{
+			int c = in->get();
+			if ( c <= 0 )
+			{
+				SetError( TIXML_ERROR_EMBEDDED_NULL, 0, 0, TIXML_ENCODING_UNKNOWN );
+				break;
+			}
+			(*tag) += (char) c;
+		}
+
+		if ( in->good() )
+		{
+			// We now have something we presume to be a node of 
+			// some sort. Identify it, and call the node to
+			// continue streaming.
+			TiXmlNode* node = Identify( tag->c_str() + tagIndex, TIXML_DEFAULT_ENCODING );
+
+			if ( node )
+			{
+				node->StreamIn( in, tag );
+				bool isElement = node->ToElement() != 0;
+				delete node;
+				node = 0;
+
+				// If this is the root element, we're done. Parsing will be
+				// done by the >> operator.
+				if ( isElement )
+				{
+					return;
+				}
+			}
+			else
+			{
+				SetError( TIXML_ERROR, 0, 0, TIXML_ENCODING_UNKNOWN );
+				return;
+			}
+		}
+	}
+	// We should have returned sooner.
+	SetError( TIXML_ERROR, 0, 0, TIXML_ENCODING_UNKNOWN );
+}
+
+#endif
+
+const char* TiXmlDocument::Parse( const char* p, TiXmlParsingData* prevData, TiXmlEncoding encoding )
+{
+	ClearError();
+
+	// Parse away, at the document level. Since a document
+	// contains nothing but other tags, most of what happens
+	// here is skipping white space.
+	if ( !p || !*p )
+	{
+		SetError( TIXML_ERROR_DOCUMENT_EMPTY, 0, 0, TIXML_ENCODING_UNKNOWN );
+		return 0;
+	}
+
+	// Note that, for a document, this needs to come
+	// before the while space skip, so that parsing
+	// starts from the pointer we are given.
+	location.Clear();
+	if ( prevData )
+	{
+		location.row = prevData->cursor.row;
+		location.col = prevData->cursor.col;
+	}
+	else
+	{
+		location.row = 0;
+		location.col = 0;
+	}
+	TiXmlParsingData data( p, TabSize(), location.row, location.col );
+	location = data.Cursor();
+
+	if ( encoding == TIXML_ENCODING_UNKNOWN )
+	{
+		// Check for the Microsoft UTF-8 lead bytes.
+		const unsigned char* pU = (const unsigned char*)p;
+		if (	*(pU+0) && *(pU+0) == TIXML_UTF_LEAD_0
+			 && *(pU+1) && *(pU+1) == TIXML_UTF_LEAD_1
+			 && *(pU+2) && *(pU+2) == TIXML_UTF_LEAD_2 )
+		{
+			encoding = TIXML_ENCODING_UTF8;
+			useMicrosoftBOM = true;
+		}
+	}
+
+    p = SkipWhiteSpace( p, encoding );
+	if ( !p )
+	{
+		SetError( TIXML_ERROR_DOCUMENT_EMPTY, 0, 0, TIXML_ENCODING_UNKNOWN );
+		return 0;
+	}
+
+	while ( p && *p )
+	{
+		TiXmlNode* node = Identify( p, encoding );
+		if ( node )
+		{
+			p = node->Parse( p, &data, encoding );
+			LinkEndChild( node );
+		}
+		else
+		{
+			break;
+		}
+
+		// Did we get encoding info?
+		if (    encoding == TIXML_ENCODING_UNKNOWN
+			 && node->ToDeclaration() )
+		{
+			TiXmlDeclaration* dec = node->ToDeclaration();
+			const char* enc = dec->Encoding();
+			assert( enc );
+
+			if ( *enc == 0 )
+				encoding = TIXML_ENCODING_UTF8;
+			else if ( StringEqual( enc, "UTF-8", true, TIXML_ENCODING_UNKNOWN ) )
+				encoding = TIXML_ENCODING_UTF8;
+			else if ( StringEqual( enc, "UTF8", true, TIXML_ENCODING_UNKNOWN ) )
+				encoding = TIXML_ENCODING_UTF8;	// incorrect, but be nice
+			else 
+				encoding = TIXML_ENCODING_LEGACY;
+		}
+
+		p = SkipWhiteSpace( p, encoding );
+	}
+
+	// Was this empty?
+	if ( !firstChild ) {
+		SetError( TIXML_ERROR_DOCUMENT_EMPTY, 0, 0, encoding );
+		return 0;
+	}
+
+	// All is well.
+	return p;
+}
+
+void TiXmlDocument::SetError( int err, const char* pError, TiXmlParsingData* data, TiXmlEncoding encoding )
+{	
+	// The first error in a chain is more accurate - don't set again!
+	if ( error )
+		return;
+
+	assert( err > 0 && err < TIXML_ERROR_STRING_COUNT );
+	error   = true;
+	errorId = err;
+	errorDesc = errorString[ errorId ];
+
+	errorLocation.Clear();
+	if ( pError && data )
+	{
+		data->Stamp( pError, encoding );
+		errorLocation = data->Cursor();
+	}
+}
+
+
+TiXmlNode* TiXmlNode::Identify( const char* p, TiXmlEncoding encoding )
+{
+	TiXmlNode* returnNode = 0;
+
+	p = SkipWhiteSpace( p, encoding );
+	if( !p || !*p || *p != '<' )
+	{
+		return 0;
+	}
+
+	p = SkipWhiteSpace( p, encoding );
+
+	if ( !p || !*p )
+	{
+		return 0;
+	}
+
+	// What is this thing? 
+	// - Elements start with a letter or underscore, but xml is reserved.
+	// - Comments: ";
+
+	if ( !StringEqual( p, startTag, false, encoding ) )
+	{
+		if ( document )
+			document->SetError( TIXML_ERROR_PARSING_COMMENT, p, data, encoding );
+		return 0;
+	}
+	p += strlen( startTag );
+
+	// [ 1475201 ] TinyXML parses entities in comments
+	// Oops - ReadText doesn't work, because we don't want to parse the entities.
+	// p = ReadText( p, &value, false, endTag, false, encoding );
+	//
+	// from the XML spec:
+	/*
+	 [Definition: Comments may appear anywhere in a document outside other markup; in addition, 
+	              they may appear within the document type declaration at places allowed by the grammar. 
+				  They are not part of the document's character data; an XML processor MAY, but need not, 
+				  make it possible for an application to retrieve the text of comments. For compatibility, 
+				  the string "--" (double-hyphen) MUST NOT occur within comments.] Parameter entity 
+				  references MUST NOT be recognized within comments.
+
+				  An example of a comment:
+
+				  
+	*/
+
+    value = "";
+	// Keep all the white space.
+	while (	p && *p && !StringEqual( p, endTag, false, encoding ) )
+	{
+		value.append( p, 1 );
+		++p;
+	}
+	if ( p && *p ) 
+		p += strlen( endTag );
+
+	return p;
+}
+
+
+const char* TiXmlAttribute::Parse( const char* p, TiXmlParsingData* data, TiXmlEncoding encoding )
+{
+	p = SkipWhiteSpace( p, encoding );
+	if ( !p || !*p ) return 0;
+
+	if ( data )
+	{
+		data->Stamp( p, encoding );
+		location = data->Cursor();
+	}
+	// Read the name, the '=' and the value.
+	const char* pErr = p;
+	p = ReadName( p, &name, encoding );
+	if ( !p || !*p )
+	{
+		if ( document ) document->SetError( TIXML_ERROR_READING_ATTRIBUTES, pErr, data, encoding );
+		return 0;
+	}
+	p = SkipWhiteSpace( p, encoding );
+	if ( !p || !*p || *p != '=' )
+	{
+		if ( document ) document->SetError( TIXML_ERROR_READING_ATTRIBUTES, p, data, encoding );
+		return 0;
+	}
+
+	++p;	// skip '='
+	p = SkipWhiteSpace( p, encoding );
+	if ( !p || !*p )
+	{
+		if ( document ) document->SetError( TIXML_ERROR_READING_ATTRIBUTES, p, data, encoding );
+		return 0;
+	}
+	
+	const char* end;
+	const char SINGLE_QUOTE = '\'';
+	const char DOUBLE_QUOTE = '\"';
+
+	if ( *p == SINGLE_QUOTE )
+	{
+		++p;
+		end = "\'";		// single quote in string
+		p = ReadText( p, &value, false, end, false, encoding );
+	}
+	else if ( *p == DOUBLE_QUOTE )
+	{
+		++p;
+		end = "\"";		// double quote in string
+		p = ReadText( p, &value, false, end, false, encoding );
+	}
+	else
+	{
+		// All attribute values should be in single or double quotes.
+		// But this is such a common error that the parser will try
+		// its best, even without them.
+		value = "";
+		while (    p && *p											// existence
+				&& !IsWhiteSpace( *p )								// whitespace
+				&& *p != '/' && *p != '>' )							// tag end
+		{
+			if ( *p == SINGLE_QUOTE || *p == DOUBLE_QUOTE ) {
+				// [ 1451649 ] Attribute values with trailing quotes not handled correctly
+				// We did not have an opening quote but seem to have a 
+				// closing one. Give up and throw an error.
+				if ( document ) document->SetError( TIXML_ERROR_READING_ATTRIBUTES, p, data, encoding );
+				return 0;
+			}
+			value += *p;
+			++p;
+		}
+	}
+	return p;
+}
+
+#ifdef TIXML_USE_STL
+void TiXmlText::StreamIn( std::istream * in, TIXML_STRING * tag )
+{
+	while ( in->good() )
+	{
+		int c = in->peek();	
+		if ( !cdata && (c == '<' ) ) 
+		{
+			return;
+		}
+		if ( c <= 0 )
+		{
+			TiXmlDocument* document = GetDocument();
+			if ( document )
+				document->SetError( TIXML_ERROR_EMBEDDED_NULL, 0, 0, TIXML_ENCODING_UNKNOWN );
+			return;
+		}
+
+		(*tag) += (char) c;
+		in->get();	// "commits" the peek made above
+
+		if ( cdata && c == '>' && tag->size() >= 3 ) {
+			size_t len = tag->size();
+			if ( (*tag)[len-2] == ']' && (*tag)[len-3] == ']' ) {
+				// terminator of cdata.
+				return;
+			}
+		}    
+	}
+}
+#endif
+
+const char* TiXmlText::Parse( const char* p, TiXmlParsingData* data, TiXmlEncoding encoding )
+{
+	value = "";
+	TiXmlDocument* document = GetDocument();
+
+	if ( data )
+	{
+		data->Stamp( p, encoding );
+		location = data->Cursor();
+	}
+
+	const char* const startTag = "";
+
+	if ( cdata || StringEqual( p, startTag, false, encoding ) )
+	{
+		cdata = true;
+
+		if ( !StringEqual( p, startTag, false, encoding ) )
+		{
+			if ( document )
+				document->SetError( TIXML_ERROR_PARSING_CDATA, p, data, encoding );
+			return 0;
+		}
+		p += strlen( startTag );
+
+		// Keep all the white space, ignore the encoding, etc.
+		while (	   p && *p
+				&& !StringEqual( p, endTag, false, encoding )
+			  )
+		{
+			value += *p;
+			++p;
+		}
+
+		TIXML_STRING dummy; 
+		p = ReadText( p, &dummy, false, endTag, false, encoding );
+		return p;
+	}
+	else
+	{
+		bool ignoreWhite = true;
+
+		const char* end = "<";
+		p = ReadText( p, &value, ignoreWhite, end, false, encoding );
+		if ( p && *p )
+			return p-1;	// don't truncate the '<'
+		return 0;
+	}
+}
+
+#ifdef TIXML_USE_STL
+void TiXmlDeclaration::StreamIn( std::istream * in, TIXML_STRING * tag )
+{
+	while ( in->good() )
+	{
+		int c = in->get();
+		if ( c <= 0 )
+		{
+			TiXmlDocument* document = GetDocument();
+			if ( document )
+				document->SetError( TIXML_ERROR_EMBEDDED_NULL, 0, 0, TIXML_ENCODING_UNKNOWN );
+			return;
+		}
+		(*tag) += (char) c;
+
+		if ( c == '>' )
+		{
+			// All is well.
+			return;
+		}
+	}
+}
+#endif
+
+const char* TiXmlDeclaration::Parse( const char* p, TiXmlParsingData* data, TiXmlEncoding _encoding )
+{
+	p = SkipWhiteSpace( p, _encoding );
+	// Find the beginning, find the end, and look for
+	// the stuff in-between.
+	TiXmlDocument* document = GetDocument();
+	if ( !p || !*p || !StringEqual( p, "SetError( TIXML_ERROR_PARSING_DECLARATION, 0, 0, _encoding );
+		return 0;
+	}
+	if ( data )
+	{
+		data->Stamp( p, _encoding );
+		location = data->Cursor();
+	}
+	p += 5;
+
+	version = "";
+	encoding = "";
+	standalone = "";
+
+	while ( p && *p )
+	{
+		if ( *p == '>' )
+		{
+			++p;
+			return p;
+		}
+
+		p = SkipWhiteSpace( p, _encoding );
+		if ( StringEqual( p, "version", true, _encoding ) )
+		{
+			TiXmlAttribute attrib;
+			p = attrib.Parse( p, data, _encoding );		
+			version = attrib.Value();
+		}
+		else if ( StringEqual( p, "encoding", true, _encoding ) )
+		{
+			TiXmlAttribute attrib;
+			p = attrib.Parse( p, data, _encoding );		
+			encoding = attrib.Value();
+		}
+		else if ( StringEqual( p, "standalone", true, _encoding ) )
+		{
+			TiXmlAttribute attrib;
+			p = attrib.Parse( p, data, _encoding );		
+			standalone = attrib.Value();
+		}
+		else
+		{
+			// Read over whatever it is.
+			while( p && *p && *p != '>' && !IsWhiteSpace( *p ) )
+				++p;
+		}
+	}
+	return 0;
+}
+
+bool TiXmlText::Blank() const
+{
+	for ( unsigned i=0; iget(addr);
+  return regs8->read(addr);
 }
 
-void cl_pdk::store_io(t_addr addr, unsigned char value) {
-  regs8->set(addr, value);
-  if (get_SP() > sp_max)
-    sp_max = get_SP();
+int cl_pdk::store_io(t_addr addr, int value) {
+  
+  regs8->write(addr, value & 0xFF);
+  if (addr == 0x02)
+    {
+      if (get_SP() > sp_max)
+        sp_max = get_SP();
+      if (!ram->valid_address(value))
+        return resSTACK_OV;
+    }
+  return resGO;
 }
 
 unsigned char cl_pdk::get_SP() {
@@ -76,7 +83,7 @@
 }
 
 void cl_pdk::set_flags(unsigned char flags) {
-    return store_io(0x00, flags);
+    store_io(0x00, flags);
 }
 
 int cl_pdk::get_flag(flag n) {
@@ -92,6 +99,7 @@
 }
 
 void cl_pdk::store_flag(flag n, int value) {
+  value= value?1:0;
   switch (n) {
   case flag_z: set_flags((get_flags() & ~1) | value); break;
   case flag_c: set_flags((get_flags() & ~2) | (value << 1)); break;
@@ -111,28 +119,31 @@
   case CPU_PDK15:
     return(execute_pdk15(code));
   default:
-    __builtin_unreachable();
+    return 0;//__builtin_unreachable();
   }
 }
 
 int cl_pdk::execute_pdk14(unsigned int code) {
+  int write_result = resGO;
   if (code == 0x0000) {
     // nop
   } else if (CODE_MASK(0x0200, 0xFF)) {
     // ret k
     regs.a = code & 0xFF;
-    store_io(0x2, get_SP() - 2);
-    PC = get_mem(get_SP()) | (get_mem(get_SP() + 1) << 8);
+    write_result = store_io(0x2, get_SP() - 2);
+    if (write_result == resGO)
+      PC = get_mem(get_SP()) | (get_mem(get_SP() + 1) << 8);
   } else if (code == 0x007A) {
     // ret
-    store_io(0x2, get_SP() - 2);
-    PC = get_mem(get_SP()) | (get_mem(get_SP() + 1) << 8);
+    write_result = store_io(0x2, get_SP() - 2);
+    if (write_result == resGO)
+      PC = get_mem(get_SP()) | (get_mem(get_SP() + 1) << 8);
   } else if (CODE_MASK(0x2F00, 0xFF)) {
     // mov a, k
     regs.a = code & 0xFF;
   } else if (CODE_MASK(0x0180, 0x3F)) {
     // mov i, a
-    store_io(code & 0x3F, regs.a);
+    write_result = store_io(code & 0x3F, regs.a);
   } else if (CODE_MASK(0x01C0, 0x3F)) {
     // mov a, i
     regs.a = get_io(code & 0x3F);
@@ -161,12 +172,12 @@
     // pushaf
     ram->write(get_SP(), regs.a);
     ram->write(get_SP() + 1, get_flags());
-    store_io(0x2, get_SP() + 2);
+    write_result = store_io(0x2, get_SP() + 2);
   } else if (code == 0x0073) {
     // popaf
     set_flags(get_mem(get_SP() - 1));
     regs.a = get_mem(get_SP() - 2);
-    store_io(0x2, get_SP() - 2);
+    write_result = store_io(0x2, get_SP() - 2);
   } else if (CODE_MASK(0x2800, 0xFF)) {
     // add a, k
     regs.a = add_to(regs.a, code & 0xFF);
@@ -309,7 +320,7 @@
     ram->write(code & 0x7F, store);
   } else if (CODE_MASK(0x00C0, 0x3F)) {
     // xor io, a
-    store_io(code & 0x3F, regs.a ^ get_io(code & 0x3F));
+    write_result = store_io(code & 0x3F, regs.a ^ get_io(code & 0x3F));
   } else if (code == 0x0068) {
     // not a
     regs.a = ~regs.a;
@@ -326,7 +337,7 @@
     // set0 io, k
     const u8_t bit = (code & 0x1C0) >> 6;
     const u8_t addr = code & 0x3F;
-    store_io(addr, get_io(addr) & ~(1 << bit));
+    write_result = store_io(addr, get_io(addr) & ~(1 << bit));
   } else if (CODE_MASK(0x2400, 0x1FF)) {
     // set0 m, k
     const u8_t bit = (code & 0x1C0) >> 6;
@@ -336,7 +347,7 @@
     // set1 io, k
     const u8_t bit = (code & 0x1C0) >> 6;
     const u8_t addr = code & 0x3F;
-    store_io(addr, get_io(addr) | (1 << bit));
+    write_result = store_io(addr, get_io(addr) | (1 << bit));
   } else if (CODE_MASK(0x2600, 0x1FF)) {
     // set1 m, k
     const u8_t bit = (code & 0x1C0) >> 6;
@@ -413,7 +424,7 @@
     ram->write(get_SP(), PC);
     ram->write(get_SP() + 1, PC >> 8);
     PC = code & 0x7FF;
-    store_io(0x2, get_SP() + 2);
+    write_result = store_io(0x2, get_SP() + 2);
   } else if (CODE_MASK(0x3000, 0x7FF)) {
     // goto k
     PC = code & 0x7FF;
@@ -458,7 +469,7 @@
     // mul
     unsigned result = regs.a * get_io(0x08);
     regs.a = result & 0xFF;
-    store_io(0x08, (result & 0xFF00) >> 8);
+    write_result = store_io(0x08, (result & 0xFF00) >> 8);
   } else if (code == 0xFF00) {
     // putchar - usim specific instruction
     putchar(regs.a);
@@ -466,27 +477,30 @@
   } else {
     return (resINV_INST);
   }
-  return (resGO);
+  return (write_result);
 }
 
 int cl_pdk::execute_pdk13(unsigned int code) {
+  int write_result = resGO;
   if (code == 0x0000) {
     // nop
   } else if (CODE_MASK(0x0100, 0xFF)) {
     // ret k
     regs.a = code & 0xFF;
-    store_io(0x2, get_SP() - 2);
-    PC = get_mem(get_SP()) | (get_mem(get_SP() + 1) << 8);
+    write_result = store_io(0x2, get_SP() - 2);
+    if (write_result == resGO)
+      PC = get_mem(get_SP()) | (get_mem(get_SP() + 1) << 8);
   } else if (code == 0x003A) {
     // ret
-    store_io(0x2, get_SP() - 2);
-    PC = get_mem(get_SP()) | (get_mem(get_SP() + 1) << 8);
+    write_result = store_io(0x2, get_SP() - 2);
+    if (write_result == resGO)
+      PC = get_mem(get_SP()) | (get_mem(get_SP() + 1) << 8);
   } else if (CODE_MASK(0x1700, 0xFF)) {
     // mov a, k
     regs.a = code & 0xFF;
   } else if (CODE_MASK(0x0080, 0x1F)) {
     // mov i, a
-    store_io(code & 0x1F, regs.a);
+    write_result = store_io(code & 0x1F, regs.a);
   } else if (CODE_MASK(0x00A0, 0x1F)) {
     // mov a, i
     regs.a = get_io(code & 0x1F);
@@ -498,7 +512,7 @@
     regs.a = get_mem(code & 0x3F);
   } else if (CODE_MASK(0x00C1, 0x1E)) {
     // TODO: ldt16
-  } else if (CODE_MASK(0x0C00, 0x1E)) {
+  } else if (CODE_MASK(0x00C0, 0x1E)) {
     // TODO: stt16
   } else if ((CODE_MASK(0x0E1, 0x1E))) {
     // idxm a, m
@@ -515,12 +529,12 @@
     // pushaf
     ram->write(get_SP(), regs.a);
     ram->write(get_SP() + 1, get_flags());
-    store_io(0x2, get_SP() + 2);
+    write_result = store_io(0x2, get_SP() + 2);
   } else if (code == 0x0033) {
     // popaf
     set_flags(get_mem(get_SP() - 1));
     regs.a = get_mem(get_SP() - 2);
-    store_io(0x2, get_SP() - 2);
+    write_result = store_io(0x2, get_SP() - 2);
   } else if (CODE_MASK(0x1000, 0xFF)) {
     // add a, k
     regs.a = add_to(regs.a, code & 0xFF);
@@ -663,7 +677,7 @@
     ram->write(code & 0x3F, store);
   } else if (CODE_MASK(0x0060, 0x1F)) {
     // xor io, a
-    store_io(code & 0x1F, regs.a ^ get_io(code & 0x1F));
+    write_result = store_io(code & 0x1F, regs.a ^ get_io(code & 0x1F));
   } else if (code == 0x0018) {
     // not a
     regs.a = ~regs.a;
@@ -680,41 +694,41 @@
     // set0 io, k
     const u8_t bit = (code & 0xE0) >> 5;
     const u8_t addr = code & 0x1F;
-    store_io(addr, get_io(addr) & ~(1 << bit));
-  } else if (CODE_MASK(0x0300, 0xFE)) {
+    write_result = store_io(addr, get_io(addr) & ~(1 << bit));
+  } else if (CODE_MASK(0x0300, 0xEF)) {
     // set0 m, k
     const u8_t bit = (code & 0xE0) >> 5;
-    const u8_t addr = (code & 0xFE) >> 1;
+    const u8_t addr = code & 0x0F;
     ram->write(addr, get_mem(addr) & ~(1 << bit));
   } else if (CODE_MASK(0x0F00, 0xFF)) {
     // set1 io, k
     const u8_t bit = (code & 0xE0) >> 5;
     const u8_t addr = code & 0x1F;
-    store_io(addr, get_io(addr) | (1 << bit));
-  } else if (CODE_MASK(0x0301, 0xFE)) {
+    write_result = store_io(addr, get_io(addr) | (1 << bit));
+  } else if (CODE_MASK(0x0310, 0xEF)) {
     // set1 m, k
     const u8_t bit = (code & 0xE0) >> 5;
-    const u8_t addr = (code & 0x1E) >> 1;
+    const u8_t addr = code & 0x0F;
     ram->write(addr, get_mem(addr) | (1 << bit));
   } else if (CODE_MASK(0x0C00, 0xFF)) {
     // t0sn io, k
     int n = (code & 0xE0) >> 5;
     if (!(get_io(code & 0x1F) & (1 << n)))
       ++PC;
-  } else if (CODE_MASK(0x0200, 0xFE)) {
+  } else if (CODE_MASK(0x0200, 0xEF)) {
     // t0sn m, k
     int n = (code & 0xE0) >> 5;
-    if (!(get_mem((code & 0xFE) >> 1) & (1 << n)))
+    if (!(get_mem(code & 0x0F) & (1 << n)))
       ++PC;
   } else if (CODE_MASK(0x0D00, 0xFF)) {
     // t1sn io, k
     int n = (code & 0xE0) >> 5;
     if (get_io(code & 0x1F) & (1 << n))
       ++PC;
-  } else if (CODE_MASK(0x0201, 0xFE)) {
+  } else if (CODE_MASK(0x0210, 0xEF)) {
     // t1sn m, k
     int n = (code & 0xE0) >> 5;
-    if (get_mem((code & 0xFE) >> 1) & (1 << n))
+    if (get_mem(code & 0x0F) & (1 << n))
       ++PC;
   } else if (CODE_MASK(0x1200, 0xFF)) {
     // ceqsn a, k
@@ -756,7 +770,7 @@
     ram->write(get_SP(), PC);
     ram->write(get_SP() + 1, PC >> 8);
     PC = code & 0x3FF;
-    store_io(0x2, get_SP() + 2);
+    write_result = store_io(0x2, get_SP() + 2);
   } else if (CODE_MASK(0x1800, 0x3FF)) {
     // goto k
     PC = code & 0x3FF;
@@ -788,7 +802,7 @@
     // mul
     unsigned result = regs.a * get_io(0x08);
     regs.a = result & 0xFF;
-    store_io(0x08, (result & 0xFF00) >> 8);
+    write_result = store_io(0x08, (result & 0xFF00) >> 8);
   } else if (code == 0xFF00) {
     // putchar - usim specific instruction
     putchar(regs.a);
@@ -796,27 +810,30 @@
   } else {
     return (resINV_INST);
   }
-  return (resGO);
+  return (write_result);
 }
 
 int cl_pdk::execute_pdk15(unsigned int code) {
+  int write_result = resGO;
   if (code == 0x0000) {
     // nop
   } else if (CODE_MASK(0x0200, 0xFF)) {
     // ret k
     regs.a = code & 0xFF;
-    store_io(0x2, get_SP() - 2);
-    PC = get_mem(get_SP()) | (get_mem(get_SP() + 1) << 8);
+    write_result = store_io(0x2, get_SP() - 2);
+    if (write_result == resGO)
+      PC = get_mem(get_SP()) | (get_mem(get_SP() + 1) << 8);
   } else if (code == 0x007A) {
     // ret
-    store_io(0x2, get_SP() - 2);
-    PC = get_mem(get_SP()) | (get_mem(get_SP() + 1) << 8);
+    write_result = store_io(0x2, get_SP() - 2);
+    if (write_result == resGO)
+      PC = get_mem(get_SP()) | (get_mem(get_SP() + 1) << 8);
   } else if (CODE_MASK(0x5700, 0xFF)) {
     // mov a, k
     regs.a = code & 0xFF;
   } else if (CODE_MASK(0x0100, 0x7F)) {
     // mov i, a
-    store_io(code & 0x7F, regs.a);
+    write_result = store_io(code & 0x7F, regs.a);
   } else if (CODE_MASK(0x0180, 0x7F)) {
     // mov a, i
     regs.a = get_io(code & 0x7F);
@@ -845,12 +862,12 @@
     // pushaf
     ram->write(get_SP(), regs.a);
     ram->write(get_SP() + 1, get_flags());
-    store_io(0x2, get_SP() + 2);
+    write_result = store_io(0x2, get_SP() + 2);
   } else if (code == 0x0073) {
     // popaf
     set_flags(get_mem(get_SP() - 1));
     regs.a = get_mem(get_SP() - 2);
-    store_io(0x2, get_SP() - 2);
+    write_result = store_io(0x2, get_SP() - 2);
   } else if (CODE_MASK(0x5000, 0xFF)) {
     // add a, k
     regs.a = add_to(regs.a, code & 0xFF);
@@ -993,7 +1010,7 @@
     ram->write(code & 0xFF, store);
   } else if (CODE_MASK(0x0080, 0x7F)) {
     // xor io, a
-    store_io(code & 0x3F, regs.a ^ get_io(code & 0x3F));
+    write_result = store_io(code & 0x3F, regs.a ^ get_io(code & 0x3F));
   } else if (code == 0x0068) {
     // not a
     regs.a = ~regs.a;
@@ -1010,7 +1027,7 @@
     // set0 io, k
     const u8_t bit = (code & 0x380) >> 7;
     const u8_t addr = code & 0x7F;
-    store_io(addr, get_io(addr) & ~(1 << bit));
+    write_result = store_io(addr, get_io(addr) & ~(1 << bit));
   } else if (CODE_MASK(0x4800, 0x3FF)) {
     // set0 m, k
     const u8_t bit = (code & 0x380) >> 7;
@@ -1020,7 +1037,7 @@
     // set1 io, k
     const u8_t bit = (code & 0x380) >> 7;
     const u8_t addr = code & 0x7F;
-    store_io(addr, get_io(addr) | (1 << bit));
+    write_result = store_io(addr, get_io(addr) | (1 << bit));
   } else if (CODE_MASK(0x4C00, 0x3FF)) {
     // set1 m, k
     const u8_t bit = (code & 0x380) >> 7;
@@ -1097,7 +1114,7 @@
     ram->write(get_SP(), PC);
     ram->write(get_SP() + 1, PC >> 8);
     PC = code & 0xFFF;
-    store_io(0x2, get_SP() + 2);
+    write_result = store_io(0x2, get_SP() + 2);
   } else if (CODE_MASK(0x6000, 0xFFF)) {
     // goto k
     PC = code & 0xFFF;
@@ -1142,7 +1159,7 @@
     // mul
     unsigned result = regs.a * get_io(0x08);
     regs.a = result & 0xFF;
-    store_io(0x08, (result & 0xFF00) >> 8);
+    write_result = store_io(0x08, (result & 0xFF00) >> 8);
   } else if (code == 0xFF00) {
     // putchar - usim specific instruction
     putchar(regs.a);
@@ -1150,8 +1167,8 @@
   } else {
     return (resINV_INST);
   }
-  return (resGO);
+  return (write_result);
 }
 
 /* End of pdk.src/inst.cc */
-/* End of pdk.src/inst.cc */
+
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/pdk.src/instcl.h sdcc-4.2.0+dfsg/sim/ucsim/pdk.src/instcl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/pdk.src/instcl.h	2019-08-22 08:12:50.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/pdk.src/instcl.h	2021-07-25 22:17:14.000000000 +0000
@@ -1,26 +1,26 @@
-/* pdk.src/instcl.h */
-
-int get_mem(unsigned int addr);
-unsigned char add_to(unsigned char initial, int value, bool carry = false);
-unsigned char sub_to(unsigned char initial, int value, bool carry = false);
-unsigned char get_io(t_addr addr);
-void store_io(t_addr addr, unsigned char value);
-unsigned char get_SP();
-unsigned char get_flags();
-void set_flags(unsigned char flags);
-
-enum flag {
-  flag_z,
-  flag_c,
-  flag_ac,
-  flag_ov,
-};
-int get_flag(flag n);
-void store_flag(flag n, int value);
-
-int execute(unsigned int code);
-int execute_pdk13(unsigned int code);
-int execute_pdk14(unsigned int code);
-int execute_pdk15(unsigned int code);
-
-/* End of pdk.src/instcl.h */
+/* pdk.src/instcl.h */
+
+int get_mem(unsigned int addr);
+unsigned char add_to(unsigned char initial, int value, bool carry = false);
+unsigned char sub_to(unsigned char initial, int value, bool carry = false);
+unsigned char get_io(t_addr addr);
+int store_io(t_addr addr, int value);
+unsigned char get_SP();
+unsigned char get_flags();
+void set_flags(unsigned char flags);
+
+enum flag {
+  flag_z,
+  flag_c,
+  flag_ac,
+  flag_ov,
+};
+int get_flag(flag n);
+void store_flag(flag n, int value);
+
+int execute(unsigned int code);
+int execute_pdk13(unsigned int code);
+int execute_pdk14(unsigned int code);
+int execute_pdk15(unsigned int code);
+
+/* End of pdk.src/instcl.h */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/pdk.src/Makefile.in sdcc-4.2.0+dfsg/sim/ucsim/pdk.src/Makefile.in
--- sdcc-4.0.0+dfsg/sim/ucsim/pdk.src/Makefile.in	2019-03-04 15:36:05.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/pdk.src/Makefile.in	2022-01-09 14:02:03.000000000 +0000
@@ -4,6 +4,9 @@
 # (c) Drotos Daniel, Talker Bt. 1997
 #
 
+# tool name
+TN		= pdk
+
 STARTYEAR	= 2019
 
 SHELL		= /bin/sh
@@ -14,7 +17,6 @@
 INSTALL		= @INSTALL@
 STRIP		= @STRIP@
 MAKEDEP         = @MAKEDEP@
-SREC_CAT	= @SREC_CAT@
 
 top_builddir	= @top_builddir@
 top_srcdir	= @top_srcdir@
@@ -23,8 +25,8 @@
 CPPFLAGS        = @CPPFLAGS@ -I$(srcdir) -I$(top_srcdir) -I$(top_builddir) \
 		  -I$(top_srcdir)/cmd.src -I$(top_srcdir)/sim.src \
 		  -I$(top_srcdir)/gui.src
-CFLAGS          = @CFLAGS@ @WALL_FLAG@
-CXXFLAGS        = @CXXFLAGS@ @WALL_FLAG@
+CFLAGS          = @WALL_FLAG@ @CFLAGS@
+CXXFLAGS        = @WALL_FLAG@ @CXXFLAGS@
 LDFLAGS         = @LDFLAGS@
 PICOPT		= @PICOPT@
 SHAREDLIB	= @SHAREDLIB@
@@ -51,43 +53,56 @@
 
 OBJECTS_SHARED	= glob.o port.o \
 		  inst.o \
-		  simpdk.o pdk.o
-OBJECTS_EXE	= spdk.o
+		  sim$(TN).o $(TN).o
+OBJECTS_EXE	= s$(TN).o
 OBJECTS		= $(OBJECTS_SHARED) $(OBJECTS_EXE)
 
-STM8ASM		= 
+# short/long exe and lib name
+SEN		= s$(TN)$(EXEEXT)
+LEN		= ucsim_$(TN)$(EXEEXT)
+SONAME		= libucsim_$(TN).so
 
 enable_dlso	= @enable_dlso@
 dlso_ok		= @dlso_ok@
 
+STM8ASM		= 
 #TEST_OBJ	= test_bit.hex test_dis.hex test_mov.hex test_jmp.hex \
 #		  test_arith.hex
 
 # Compiling entire program or any subproject
 # ------------------------------------------
-all: checkconf otherlibs pdk.src
+all: checkconf otherlibs $(TN).src
 
 tests: $(TEST_OBJ)
 
 
 # Compiling and installing everything and runing test
 # ---------------------------------------------------
-install: all installdirs
-	$(INSTALL) spdk$(EXEEXT) $(DESTDIR)$(bindir)/`echo spdk|sed '$(transform)'`$(EXEEXT)
-	$(STRIP) $(DESTDIR)$(bindir)/`echo spdk|sed '$(transform)'`$(EXEEXT)
+install: all installdirs install_shared_lib
+	$(INSTALL) $(SEN) $(DESTDIR)$(bindir)/$(SEN)
+	$(STRIP) $(DESTDIR)$(bindir)/$(SEN)
+	$(INSTALL) $(LEN) $(DESTDIR)$(bindir)/$(LEN)
+	$(STRIP) $(DESTDIR)$(bindir)/$(LEN)
 
 
 # Deleting all the installed files
 # --------------------------------
 uninstall:
-	rm -f $(DESTDIR)$(bindir)/`echo spdk|sed '$(transform)'`$(EXEEXT)
+	rm -f $(DESTDIR)$(bindir)/$(SEN)
+	rm -f $(DESTDIR)$(bindir)/$(LEN)
+	rm -f $(DESTDIR)$(libdir)/$(SONAME)
 
 
 # Performing self-test
 # --------------------
 check: test
 
+.PHONY:	test baseline
 test:
+	@$(MAKE) --no-print-directory -C test
+
+baseline:
+	@$(MAKE) --no-print-directory -C test baseline
 
 
 # Performing installation test
@@ -115,21 +130,28 @@
 # --------
 .SUFFIXES: .asm .hex
 
-pdk.src: spdk$(EXEEXT) shared_lib
+$(TN).src: $(SEN) $(LEN) shared_lib
 
-spdk$(EXEEXT): $(OBJECTS) $(top_builddir)/libcmd.a $(top_builddir)/libguiucsim.a $(top_builddir)/libsim.a $(top_builddir)/libucsimutil.a
+$(SEN): $(OBJECTS) $(top_builddir)/libcmd.a $(top_builddir)/libguiucsim.a $(top_builddir)/libsim.a $(top_builddir)/libucsimutil.a
 	$(CXX) $(CXXFLAGS) $(LDFLAGS) $(OBJECTS) $(LIBS) -o $@
 
+$(LEN): s$(TN)$(EXEEXT)
+	cp $< $@
+
 ifeq ($(dlso_ok),yes)
-shared_lib: $(top_builddir)/spdk.so
+shared_lib: $(top_builddir)/$(SONAME)
+install_shared_lib: shared_lib
+	test -d $(DESTDIR)$(libdir) || $(INSTALL) -d $(DESTDIR)$(libdir)
+	$(INSTALL) $(top_builddir)/$(SONAME) $(DESTDIR)$(libdir)/$(SONAME)
 else
 shared_lib:
-	@$(top_srcdir)/mkecho $(top_builddir) "No pdk shared lib made."
+	@$(top_srcdir)/mkecho $(top_builddir) "No $(TN) shared lib made."
 	@$(top_srcdir)/mkecho $(top_builddir) "(SHAREDLIB="$(SHAREDLIB)",dl_ok="$(dl_ok)",enable_dlso="$(enable_dlso)")"
+install_shared_lib:
 endif
 
-$(top_builddir)/spdk.so: $(OBJECTS_SHARED)
-	$(CXX) -shared $(LDFLAGS) $(OBJECTS_SHARED) -o $(top_builddir)/spdk.so
+$(top_builddir)/$(SONAME): $(OBJECTS_SHARED)
+	$(CXX) -shared $(LDFLAGS) $(OBJECTS_SHARED) -o $(top_builddir)/s$(TN).so
 
 otherlibs: $(top_builddir)/libcmd.a $(top_builddir)/libguiucsim.a $(top_builddir)/libsim.a $(top_builddir)/libucsimutil.a
 
@@ -159,24 +181,5 @@
 	  $(MAKE) -C $(top_builddir) -f conf.mk srcdir="$(srcdir)" top_builddir="$(top_builddir)" freshconf;\
 	fi
 
-#bl_l15x46.hex: bl_l15x46.asc
-#	$(SREC_CAT) $< -Ascii_Hex -Output $@ -Intel
-
-#bl_l15x46.cc: bl_l15x46.asc
-#	$(SREC_CAT) $< -Ascii_Hex -Output $@ -C-Array bl_l15x46 -INClude -No-CONST
-
-#bl_s105.hex: bl_s105.asc
-#	$(SREC_CAT) $< -Ascii_Hex -Output $@ -Intel
-
-#bl_s105.cc: bl_s105.asc
-#	$(SREC_CAT) $< -Ascii_Hex -Output $@ -C-Array bl_s105 -INClude -No-CONST
-
-#bl_source: bl.cc bl.h
-
-#bl.cc: bl_head.cc bl_l15x46.cc bl_s105.cc
-#	cat bl_head.cc bl_l15x46.cc bl_s105.cc|sed 's/unsigned char/t_mem/' >$@
-
-#bl.h: bl_l15x46.h bl_s105.h
-#	cat bl_l15x46.h bl_s105.h|sed 's/unsigned char/t_mem/' >$@
 
 # End of pdk.src/Makefile.in
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/pdk.src/pdk.cc sdcc-4.2.0+dfsg/sim/ucsim/pdk.src/pdk.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/pdk.src/pdk.cc	2019-08-22 08:12:50.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/pdk.src/pdk.cc	2022-01-18 21:40:45.000000000 +0000
@@ -25,27 +25,29 @@
 02111-1307, USA. */
 /*@1@*/
 
-#include "ddconfig.h"
+//#include "ddconfig.h"
 
-#include 
-#include  /* for va_list */
-#include 
+//#include 
+//#include  /* for va_list */
+//#include 
 #include 
 #include 
-#include "i_string.h"
+#include 
+//#include "i_string.h"
 
 // prj
 #include "globals.h"
-#include "pobjcl.h"
+//#include "pobjcl.h"
 
 // sim
-#include "simcl.h"
+//#include "simcl.h"
+#include "dregcl.h"
 
 // local
 #include "glob.h"
 #include "pdkcl.h"
-#include "portcl.h"
-#include "regspdk.h"
+//#include "portcl.h"
+//#include "regspdk.h"
 
 /*******************************************************************/
 
@@ -60,7 +62,7 @@
 int cl_pdk::init(void) {
   cl_uc::init(); /* Memories now exist */
 
-  xtal = 8000000;
+  set_xtal(8000000);
   sp_max = 0x00;
 
   // rom = address_space(MEM_ROM_ID);
@@ -80,21 +82,21 @@
 
   PC = 0x0000;
   regs.a = 0;
-  for (size_t i = 0; i < io_size; ++i) {
+  for (t_addr i = 0; i < io_size; ++i) {
     store_io(i, 0);
   }
 }
 
-char *cl_pdk::id_string(void) {
+const char *cl_pdk::id_string(void) {
   switch (type->type) {
     case CPU_PDK13:
-      return((char *)"pdk13");
+      return("pdk13");
     case CPU_PDK14:
-      return((char *)"pdk14");
+      return("pdk14");
     case CPU_PDK15:
-      return((char *)"pdk15");
+      return("pdk15");
     default:
-      return((char*)"unknown pdk");
+      return("unknown pdk");
   }
 }
 
@@ -115,9 +117,14 @@
 }
 */
 
-void cl_pdk::mk_hw_elements(void) {
+void cl_pdk::mk_hw_elements(void)
+{
   // TODO: Add hardware stuff here.
+  class cl_hw *h;
   cl_uc::mk_hw_elements();
+
+  add_hw(h= new cl_dreg(this, 0, "dreg"));
+  h->init();
 }
 
 class cl_memory_chip *c;
@@ -140,7 +147,7 @@
     ram_storage = 0x100;
     break;
   default:
-    __builtin_unreachable();
+    return;//__builtin_unreachable();
   }
   rom = as = new cl_address_space("rom", 0, rom_storage, 16);
   as->init();
@@ -156,7 +163,7 @@
     class cl_address_decoder *ad;
     class cl_memory_chip *chip;
 
-    chip = new cl_memory_chip("rom_chip", rom_storage, 16);
+    chip = new cl_chip16("rom_chip", rom_storage, 16);
     chip->init();
     memchips->add(chip);
 
@@ -170,11 +177,8 @@
     regs8->get_cell(io_size)->decode(&(regs._a));
   }
 
-  class cl_var *v;
-  vars->add(v = new cl_var(cchars("flag"), regs8, 0, ""));
-  v->init();
-  vars->add(v = new cl_var(cchars("sp"), regs8, 1, ""));
-  v->init();
+  vars->add("flag", regs8, 0, 7, 0, "Flags");
+  vars->add("sp", regs8, 1, 7, 0, "Stack Pointer");
 }
 
 /*
@@ -190,7 +194,7 @@
   case CPU_PDK15:
     return (disass_pdk_15);
   default:
-    __builtin_unreachable();
+    return NULL;//__builtin_unreachable();
   }
 }
 
@@ -251,7 +255,7 @@
         break;
 
       default:
-        __builtin_unreachable();
+        return "";//__builtin_unreachable();
   }
 
   uint code = rom->get(addr++);
@@ -280,109 +284,113 @@
   return b;
 }
 
-char *cl_pdk::disass(t_addr addr, const char *sep) {
-  char work[256], temp[20];
+char *cl_pdk::disass(t_addr addr)
+{
+  chars work, temp;
   const char *b;
-  char *buf, *p, *t;
   int len = 0;
   int immed_offset = 0;
   struct dis_entry *dis_e;
-
-  p = work;
+  bool first= true;
+  
+  work= "";
 
   b = get_disasm_info(addr, &len, NULL, &immed_offset, &dis_e);
 
-  if (b == NULL) {
-    buf = (char *)malloc(30);
-    strcpy(buf, "UNKNOWN/INVALID");
-    return (buf);
-  }
+  if (b == NULL)
+    {
+      return (strdup("UNKNOWN/INVALID"));
+    }
 
-  while (*b) {
-    if (*b == '%') {
-      b++;
-      uint code = rom->get(addr) & ~(uint)dis_e->mask;
-      switch (*(b++)) {
-        case 'k':  // k    immediate addressing
-          sprintf(temp, "#%u", code);
-          break;
-        case 'm':  // m    memory addressing
-          if (*b == 'n') {
-            code &= 0x3F;
-            ++b;
-          }
-          sprintf(temp, "%u", code);
-          break;
-        case 'i':  // i    IO addressing
-          // TODO: Maybe add pretty printing.
-          if (*b == 'n') {
-            switch (type->type) {
-            case CPU_PDK13:
-              code &= 0x1F;
-              break;
-            case CPU_PDK14:
-              code &= 0x3F;
-              break;
-            case CPU_PDK15:
-              code &= 0x7F;
-              break;
-            default:
-              __builtin_unreachable();
-           }
-
-            ++b;
-          }
-          sprintf(temp, "[%u]", code);
-          break;
-        case 'n':  // n    N-bit addressing
-          uint n;
-          switch (type->type) {
-          case CPU_PDK13:
-            n = (code & 0xE0) >> 5;
-            break;
-          case CPU_PDK14:
-            n = (code & 0x1C0) >> 6;
-            break;
-          case CPU_PDK15:
-            n = (code & 0x380) >> 7;
-            break;
-          default:
-            __builtin_unreachable();
-          }
-          sprintf(temp, "#%u", n);
-          break;
-        default:
-          strcpy(temp, "%?");
-          break;
-      }
-      t = temp;
-      while (*t) *(p++) = *(t++);
-    } else
-      *(p++) = *(b++);
-  }
-  *p = '\0';
+  while (*b)
+    {
+      if ((*b == ' ') && first)
+	{
+	  first= false;
+	  while (work.len() < 6) work.append(' ');
+	}
+      if (*b == '%')
+	{
+	  temp= "";
+	  b++;
+	  uint code = rom->get(addr) & ~(uint)dis_e->mask;
+	  switch (*(b++))
+	    {
+	    case 'k':  // k    immediate addressing
+	      temp.format("#0x%x", code);
+	      break;
+	    case 'm':  // m    memory addressing
+	      if (*b == 'n') {
+		switch (type->type) {
+		case CPU_PDK13:
+		  code &= 0x0F;
+		  break;
+		case CPU_PDK14:
+		  code &= 0x3F;
+		  break;
+		case CPU_PDK15:
+		  code &= 0x7F;
+		  break;
+		default:
+		  ;//__builtin_unreachable();
+		}
+		++b;
+	      }
+	      temp.format("0x%x", code);
+	      break;
+	    case 'i':  // i    IO addressing
+	      // TODO: Maybe add pretty printing.
+	      if (*b == 'n') {
+		switch (type->type) {
+		case CPU_PDK13:
+		  code &= 0x1F;
+		  break;
+		case CPU_PDK14:
+		  code &= 0x3F;
+		  break;
+		case CPU_PDK15:
+		  code &= 0x7F;
+		  break;
+		default:
+		  ;//__builtin_unreachable();
+		}
+		
+		++b;
+	      }
+	      temp.format("[0x%x]", code);
+	      break;
+	    case 'n':  // n    N-bit addressing
+	      uint n;
+	      switch (type->type) {
+	      case CPU_PDK13:
+		n = (code & 0xE0) >> 5;
+		break;
+	      case CPU_PDK14:
+		n = (code & 0x1C0) >> 6;
+		break;
+	      case CPU_PDK15:
+		n = (code & 0x380) >> 7;
+		break;
+	      default:
+		n= 0;//__builtin_unreachable();
+	      }
+	      temp.format("#0x%x", n);
+	      break;
+	    default:
+	      temp= "%?";
+	      break;
+	    }
+	  work+= temp;
+	}
+      else
+	work+= *(b++);
+    }
 
-  p = strchr(work, ' ');
-  if (!p) {
-    buf = strdup(work);
-    return (buf);
-  }
-  if (sep == NULL)
-    buf = (char *)malloc(6 + strlen(p) + 1);
-  else
-    buf = (char *)malloc((p - work) + strlen(sep) + strlen(p) + 1);
-  for (p = work, t = buf; *p != ' '; p++, t++) *t = *p;
-  p++;
-  *t = '\0';
-  if (sep == NULL) {
-    while (strlen(buf) < 6) strcat(buf, " ");
-  } else
-    strcat(buf, sep);
-  strcat(buf, p);
-  return (buf);
+  return strdup(work.c_str());
 }
 
 void cl_pdk::print_regs(class cl_console_base *con) {
+  con->dd_color("answer");
   con->dd_printf("A= 0x%02x(%3d)\n", regs.a, regs.a);
   con->dd_printf("Flag= 0x%02x(%3d)  \n", get_flags(), get_flags());
   con->dd_printf("SP= 0x%02x(%3d)\n", get_SP(), get_SP());
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/pdk.src/pdkcl.h sdcc-4.2.0+dfsg/sim/ucsim/pdk.src/pdkcl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/pdk.src/pdkcl.h	2019-08-22 08:12:50.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/pdk.src/pdkcl.h	2021-10-29 17:39:15.000000000 +0000
@@ -48,7 +48,7 @@
 public:
   cl_pdk(struct cpu_entry *IType, class cl_sim *asim);
   virtual int init(void);
-  virtual char *id_string(void);
+  virtual const char *id_string(void);
 
   //virtual t_addr get_mem_size(enum mem_class type);
   //virtual void mk_port(t_addr base, chars n);
@@ -59,7 +59,7 @@
   virtual int inst_length(t_addr addr);
   virtual int inst_branch(t_addr addr);
   virtual int longest_inst(void);
-  virtual char *disass(t_addr addr, const char *sep);
+  virtual char *disass(t_addr addr);
   virtual void print_regs(class cl_console_base *con);
 
   virtual int exec_inst(void);
@@ -76,7 +76,7 @@
 #include "instcl.h"
 };
 
-
+/*
 class cl_pdk_cpu: public cl_hw
 {
  protected:
@@ -84,13 +84,13 @@
  public:
   cl_pdk_cpu(class cl_uc *auc);
   virtual int init(void);
-  virtual int cfg_size(void) { return 2; }
+  virtual unsigned int cfg_size(void) { return 2; }
 
   virtual void write(class cl_memory_cell *cell, t_mem *val);
   virtual t_mem read(class cl_memory_cell *cell);
   virtual t_mem conf_op(cl_memory_cell *cell, t_addr addr, t_mem *val);
 };
-
+*/
 
 #endif
 
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/pdk.src/port.cc sdcc-4.2.0+dfsg/sim/ucsim/pdk.src/port.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/pdk.src/port.cc	2019-04-02 10:46:33.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/pdk.src/port.cc	2021-04-01 17:52:48.000000000 +0000
@@ -45,24 +45,18 @@
   // DDR: 0=input, 1=output
   cell_dir= register_cell(uc->rom, base + 2);
 
-  cl_var *v;
-  chars pn= cchars(get_name());
-  uc->vars->add(v= new cl_var(pn+chars("_ddr"), uc->rom, base+2,
-			      "Direction register"));
-  v->init();
-  uc->vars->add(v= new cl_var(pn+chars("_odr"), uc->rom, base+0,
-			      "Output data register"));
-  v->init();
-  uc->vars->add(v= new cl_var(pn+chars("_idr"), uc->rom, base+1,
-			      "Input data register (outside value of port pins)"));
-  v->init();
-  uc->vars->add(v= new cl_var(pn+chars("_pin"), uc->rom, base+1,
-			      "Outside value of port pins"));
-  v->init();
-  uc->vars->add(v= new cl_var(pn+chars("_pins"), uc->rom, base+1,
-			      "Outside value of port pins"));
-  v->init();
-  
+  chars pn= get_name();
+  uc->vars->add(pn+"_ddr", uc->rom, base+2, 7, 0,
+                         "Direction register");
+  uc->vars->add(pn+"_odr", uc->rom, base+0, 7, 0,
+                         "Output data register");
+  uc->vars->add(pn+"_idr", uc->rom, base+1, 7, 0,
+                         "Input data register (outside value of port pins)");
+  uc->vars->add(pn+"_pin", uc->rom, base+1, 7, 0,
+                         "Outside value of port pins");
+  uc->vars->add(pn+"_pins", uc->rom, base+1, 7, 0,
+                         "Outside value of port pins");
+
   return 0;
 }
 
@@ -123,7 +117,7 @@
 	//con->dd_printf("-");
     }
   con->dd_printf("\n");
-  print_cfg_info(con);
+  //print_cfg_info(con);
 }
 
 
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/pdk.src/regspdk.h sdcc-4.2.0+dfsg/sim/ucsim/pdk.src/regspdk.h
--- sdcc-4.0.0+dfsg/sim/ucsim/pdk.src/regspdk.h	2019-08-22 08:12:50.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/pdk.src/regspdk.h	2020-07-01 13:56:56.000000000 +0000
@@ -31,7 +31,7 @@
 #include "ddconfig.h"
 
 
-const int io_size = 64;
+const t_addr io_size = 64;
 union t_regs
 {
   u8_t a;
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/pdk.src/simpdk.cc sdcc-4.2.0+dfsg/sim/ucsim/pdk.src/simpdk.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/pdk.src/simpdk.cc	2019-04-16 10:04:43.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/pdk.src/simpdk.cc	2020-08-22 10:25:08.000000000 +0000
@@ -25,6 +25,9 @@
 02111-1307, USA. */
 /*@1@*/
 
+#include 
+#include 
+
 // prj
 #include "globals.h"
 
@@ -41,14 +44,14 @@
 cl_simpdk::mk_controller(void)
 {
   int i;
-  char *typ= 0;
+  const char *typ= 0;
   class cl_optref type_option(this);
 
   type_option.init();
-  type_option.use(cchars("cpu_type"));
+  type_option.use("cpu_type");
   i= 0;
   if ((typ= type_option.get_value(typ)) == 0)
-    typ= cchars("PDK14");
+    typ= "PDK14";
   while ((cpus_pdk[i].type_str != NULL) &&
 	 (strcasecmp(typ, cpus_pdk[i].type_str) != 0))
     i++;
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/pdk.src/spdk.cc sdcc-4.2.0+dfsg/sim/ucsim/pdk.src/spdk.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/pdk.src/spdk.cc	2019-03-04 15:36:05.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/pdk.src/spdk.cc	2020-06-13 16:30:36.000000000 +0000
@@ -29,7 +29,7 @@
 #include "globals.h"
 
 // sim.src
-#include "appcl.h"
+//#include "appcl.h"
 
 // local
 #include "simpdkcl.h"
@@ -42,6 +42,7 @@
 
   cpus= cpus_pdk;
   application= new cl_app();
+  application->set_name("spdk");
   application->init(argc, argv);
   sim= new cl_simpdk(application);
   if (sim->init())
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/pdk.src/test/clean.mk sdcc-4.2.0+dfsg/sim/ucsim/pdk.src/test/clean.mk
--- sdcc-4.0.0+dfsg/sim/ucsim/pdk.src/test/clean.mk	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/pdk.src/test/clean.mk	2021-04-01 17:52:48.000000000 +0000
@@ -0,0 +1,5 @@
+clean:
+
+distclean:
+	rm -f Makefile
+	find . -type d -name out -exec rm -rf {} \;
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/pdk.src/test/config/baseline/PDK13 sdcc-4.2.0+dfsg/sim/ucsim/pdk.src/test/config/baseline/PDK13
--- sdcc-4.0.0+dfsg/sim/ucsim/pdk.src/test/config/baseline/PDK13	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/pdk.src/test/config/baseline/PDK13	2022-02-08 21:21:05.000000000 +0000
@@ -0,0 +1,24 @@
+uCsim, Copyright (C)  Daniel Drotos.
+uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+This is free software, and you are welcome to redistribute it
+under certain conditions; type `show c' for details.
+Type of microcontroller: pdk13
+Controller has 3 hardware element(s).
+   on simif[0]
+  off vcd[0]
+   on dreg[0]
+A= 0x00(  0)
+Flag= 0x00(  0)  
+SP= 0x00(  0)
+0x000  ? 0000 nop[0K
+Memory chips:
+  0x000000-0x0000ff      256 variable_storage (32,%08x,0x%02lx)
+  0x000000-0x0003ff     1024 rom_chip (16,%04x,0x%03lx)
+Address spaces:
+  0x000000-0x0000ff      256 variables (32,%08x,0x%02lx)
+  0x000000-0x0003ff     1024 rom (16,%04x,0x%03lx)
+  0x000000-0x00003f       64 ram (8,%02x,0x%02lx)
+  0x000000-0x000040       65 regs8 (8,%02x,0x%02lx)
+Address decoders:
+  variables 0x00 0xff -> variable_storage 0x00 activated
+  rom 0x000 0x400 -> rom_chip 0x000 inactive
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/pdk.src/test/config/baseline/PDK14 sdcc-4.2.0+dfsg/sim/ucsim/pdk.src/test/config/baseline/PDK14
--- sdcc-4.0.0+dfsg/sim/ucsim/pdk.src/test/config/baseline/PDK14	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/pdk.src/test/config/baseline/PDK14	2022-02-08 21:21:05.000000000 +0000
@@ -0,0 +1,24 @@
+uCsim, Copyright (C)  Daniel Drotos.
+uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+This is free software, and you are welcome to redistribute it
+under certain conditions; type `show c' for details.
+Type of microcontroller: pdk14
+Controller has 3 hardware element(s).
+   on simif[0]
+  off vcd[0]
+   on dreg[0]
+A= 0x00(  0)
+Flag= 0x00(  0)  
+SP= 0x00(  0)
+0x000  ? 0000 nop[0K
+Memory chips:
+  0x000000-0x0000ff      256 variable_storage (32,%08x,0x%02lx)
+  0x000000-0x0007ff     2048 rom_chip (16,%04x,0x%03lx)
+Address spaces:
+  0x000000-0x0000ff      256 variables (32,%08x,0x%02lx)
+  0x000000-0x0007ff     2048 rom (16,%04x,0x%03lx)
+  0x000000-0x00007f      128 ram (8,%02x,0x%02lx)
+  0x000000-0x000040       65 regs8 (8,%02x,0x%02lx)
+Address decoders:
+  variables 0x00 0xff -> variable_storage 0x00 activated
+  rom 0x000 0x800 -> rom_chip 0x000 inactive
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/pdk.src/test/config/baseline/PDK15 sdcc-4.2.0+dfsg/sim/ucsim/pdk.src/test/config/baseline/PDK15
--- sdcc-4.0.0+dfsg/sim/ucsim/pdk.src/test/config/baseline/PDK15	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/pdk.src/test/config/baseline/PDK15	2022-02-08 21:21:05.000000000 +0000
@@ -0,0 +1,24 @@
+uCsim, Copyright (C)  Daniel Drotos.
+uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+This is free software, and you are welcome to redistribute it
+under certain conditions; type `show c' for details.
+Type of microcontroller: pdk15
+Controller has 3 hardware element(s).
+   on simif[0]
+  off vcd[0]
+   on dreg[0]
+A= 0x00(  0)
+Flag= 0x00(  0)  
+SP= 0x00(  0)
+0x000  ? 0000 nop[0K
+Memory chips:
+  0x000000-0x0000ff      256 variable_storage (32,%08x,0x%02lx)
+  0x000000-0x000fff     4096 rom_chip (16,%04x,0x%03lx)
+Address spaces:
+  0x000000-0x0000ff      256 variables (32,%08x,0x%02lx)
+  0x000000-0x000fff     4096 rom (16,%04x,0x%03lx)
+  0x000000-0x0000ff      256 ram (8,%02x,0x%02lx)
+  0x000000-0x000040       65 regs8 (8,%02x,0x%02lx)
+Address decoders:
+  variables 0x00 0xff -> variable_storage 0x00 activated
+  rom 0x000 0x1000 -> rom_chip 0x000 inactive
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/pdk.src/test/config/Makefile sdcc-4.2.0+dfsg/sim/ucsim/pdk.src/test/config/Makefile
--- sdcc-4.0.0+dfsg/sim/ucsim/pdk.src/test/config/Makefile	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/pdk.src/test/config/Makefile	2021-03-21 12:01:19.000000000 +0000
@@ -0,0 +1,8 @@
+OUTPUTS = $(filter-out Parameter, $(shell $(SIM) -H | sort -u -k2b | cut -d' ' -f1))
+
+
+$(OUTPUTS):
+	$(call run-sim, -t $(@F) -e 'conf; info reg; info mem')
+
+
+include test-lib.mk
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/pdk.src/test/Makefile.in sdcc-4.2.0+dfsg/sim/ucsim/pdk.src/test/Makefile.in
--- sdcc-4.0.0+dfsg/sim/ucsim/pdk.src/test/Makefile.in	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/pdk.src/test/Makefile.in	2021-03-28 10:28:14.000000000 +0000
@@ -0,0 +1,9 @@
+# @configure_input@
+
+srcdir           = @abs_srcdir@
+
+abs_top_builddir = @abs_top_builddir@
+abs_top_srcdir   = @abs_top_srcdir@
+
+
+include $(abs_top_srcdir)/test-target.mk
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/pdk.src/test/symdis/baseline/stdout sdcc-4.2.0+dfsg/sim/ucsim/pdk.src/test/symdis/baseline/stdout
--- sdcc-4.0.0+dfsg/sim/ucsim/pdk.src/test/symdis/baseline/stdout	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/pdk.src/test/symdis/baseline/stdout	2022-02-08 21:21:05.000000000 +0000
@@ -0,0 +1,57 @@
+uCsim, Copyright (C)  Daniel Drotos.
+uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+This is free software, and you are welcome to redistribute it
+under certain conditions; type `show c' for details.
+var __interrupt_vect rom[0x20]
+var __sdcc_external_startup rom[0x1f]
+var __sdcc_program_startup rom[0x11]
+var __sdcc_gs_init_startup rom[0x12]
+var __sdcc_init_data rom[0x12]
+var _main rom[0x1d]
+dc 0x0000 0x0020 
+
+0x000    <.reset>:
+0x000    0000 nop[0K
+0x001  ? 2601 clear  0x1[0K
+0x002  ? 5702 mov    a, #0x2[0K
+0x003  ? 5001 add    #0x1[0K
+0x004  ? 54fe and    #0xfe[0K
+0x005  ? 0102 mov    [0x2], a[0K
+0x006  ? 701f call   #0x1f[0K
+0x007  ? 6012 goto   #0x12[0K
+0x008  ? 0000 nop[0K
+0x009  ? 0000 nop[0K
+0x00a  ? 0000 nop[0K
+0x00b  ? 0000 nop[0K
+0x00c  ? 0000 nop[0K
+0x00d  ? 0000 nop[0K
+0x00e  ? 0000 nop[0K
+0x00f  ? 0000 nop[0K
+0x010  ? 007b reti[0K
+
+0x011    <__sdcc_program_startup>:
+0x011  ? 601d goto   #0x1d[0K
+
+0x012    <__sdcc_gs_init_startup>:
+0x012    <__sdcc_init_data>:
+0x012  ? 5702 mov    a, #0x2[0K
+0x013  ? 1700 mov    0x0, a[0K
+0x014  ? 5702 mov    a, #0x2[0K
+0x015  ? 5000 add    #0x0[0K
+0x016  ? 2f00 cneqsn 0x0[0K
+0x017  ? 601c goto   #0x1c[0K
+0x018  ? 5700 mov    a, #0x0[0K
+0x019  ? 0700 idxm   0x0, a[0K
+0x01a  ? 2400 inc    0x0[0K
+0x01b  ? 6014 goto   #0x14[0K
+0x01c  ? 6011 goto   #0x11[0K
+
+0x01d    <_main>:
+0x01d  ? 601d goto   #0x1d[0K
+0x01e  ? 007a ret[0K
+
+0x01f    <__sdcc_external_startup>:
+0x01f  ? 0200 ret    #0x0[0K
+
+0x020    <__interrupt_vect>:
+0x020  ? 007a ret[0K
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/pdk.src/test/symdis/Makefile sdcc-4.2.0+dfsg/sim/ucsim/pdk.src/test/symdis/Makefile
--- sdcc-4.0.0+dfsg/sim/ucsim/pdk.src/test/symdis/Makefile	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/pdk.src/test/symdis/Makefile	2021-05-07 16:21:16.000000000 +0000
@@ -0,0 +1,15 @@
+OUTPUTS = stdout
+
+
+# Ignore changes in white space. The field widths for labels
+# depends on the length of the longest label. This will be
+# different for different simulators and should not be assumed
+# to be constant for any given simulator.
+DIFF_OPTS += -b
+
+
+$(OUTPUTS):	test.ihx test.cmd
+	$(call run-sim, -t PDK15)
+
+
+include test-lib.mk
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/pdk.src/test/symdis/test.c sdcc-4.2.0+dfsg/sim/ucsim/pdk.src/test/symdis/test.c
--- sdcc-4.0.0+dfsg/sim/ucsim/pdk.src/test/symdis/test.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/pdk.src/test/symdis/test.c	2021-05-07 16:21:16.000000000 +0000
@@ -0,0 +1,4 @@
+main()
+{
+	for (;;);
+}
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/pdk.src/test/symdis/test.cmd sdcc-4.2.0+dfsg/sim/ucsim/pdk.src/test/symdis/test.cmd
--- sdcc-4.0.0+dfsg/sim/ucsim/pdk.src/test/symdis/test.cmd	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/pdk.src/test/symdis/test.cmd	2021-05-07 16:21:16.000000000 +0000
@@ -0,0 +1,7 @@
+var __interrupt_vect rom[0x20]
+var __sdcc_external_startup rom[0x1f]
+var __sdcc_program_startup rom[0x11]
+var __sdcc_gs_init_startup rom[0x12]
+var __sdcc_init_data rom[0x12]
+var _main rom[0x1d]
+dc 0x0000 0x0020 
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/pdk.src/test/symdis/test.ihx sdcc-4.2.0+dfsg/sim/ucsim/pdk.src/test/symdis/test.ihx
--- sdcc-4.0.0+dfsg/sim/ucsim/pdk.src/test/symdis/test.ihx	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/pdk.src/test/symdis/test.ihx	2021-05-07 16:21:16.000000000 +0000
@@ -0,0 +1,7 @@
+:020020007B0063
+:100000000000012602570150FE5402011F701260C9
+:160024000257001702570050002F1C60005700070024146011609B
+:020022001D605F
+:04003A001D607A00CB
+:04003E0000027A0042
+:00000001FF
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/pdk.src/test/test-conf.mk sdcc-4.2.0+dfsg/sim/ucsim/pdk.src/test/test-conf.mk
--- sdcc-4.0.0+dfsg/sim/ucsim/pdk.src/test/test-conf.mk	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/pdk.src/test/test-conf.mk	2021-03-21 12:01:19.000000000 +0000
@@ -0,0 +1,3 @@
+CC = sdcc -mpdk15
+AS = sdaspdk15
+LD = sdldpdk
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/pobj.cc sdcc-4.2.0+dfsg/sim/ucsim/pobj.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/pobj.cc	2017-06-19 20:29:56.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/pobj.cc	2021-04-01 17:52:48.000000000 +0000
@@ -25,7 +25,11 @@
 02111-1307, USA. */
 /*@1@*/
 
-#include "ddconfig.h"
+#include 
+#include 
+#include 
+
+//#include "ddconfig.h"
 
 #include 
 #include 
@@ -55,7 +59,7 @@
 
 
 /*
- * Destructing the object: calling hte virtual Done method
+ * Destructing the object: calling the virtual Done method
  */
 
 cl_base::~cl_base(void)
@@ -76,7 +80,7 @@
 int cl_base::init(void) {return(0);}
 
 const char *
-cl_base::get_name(const char *def)
+cl_base::get_name(const char *def) const
 {
   if (!name)
     return(def);
@@ -103,25 +107,16 @@
 const char *
 cl_base::set_name(const char *new_name, const char *def_name)
 {
-  char *def;
-
-  if (!def_name ||
-      *def_name == '\0')
-    def= /*strdup*/cchars("");
-  else
-    def= /*strdup*/cchars(def_name);
-  // if (name) free((void*)name);
-  if (!new_name)
-    name= def;
-  else if (*new_name)
-    name= /*strdup*/(new_name);
+  if (new_name && *new_name)
+    name= chars(new_name);
   else
-    name= def;
+    name= chars(def_name ? def_name : "");
+
   return(name);
 }
 
 bool
-cl_base::is_named(const char *the_name)
+cl_base::is_named(const char *the_name) const
 {
   /*
   if (!name ||
@@ -133,7 +128,7 @@
 }
 
 bool
-cl_base::is_inamed(const char *the_name)
+cl_base::is_inamed(const char *the_name) const
 {
   if (/*!name ||
       !*name ||
@@ -270,17 +265,6 @@
  * Initializing a collection
  */
 
-cl_list::cl_list(t_index alimit, t_index adelta, char *aname):
-  cl_base()
-{
-  count= 0;
-  Items= 0;
-  Limit= 0;
-  Delta= adelta;
-  set_limit(alimit);
-  set_name(aname, "unnamed list");
-}
-
 cl_list::cl_list(t_index alimit, t_index adelta, const char *aname):
   cl_base()
 {
@@ -356,7 +340,7 @@
  */
 
 void
-cl_list::disconn(void *item)
+cl_list::disconn(const void *item)
 {
   t_index i;
 
@@ -449,7 +433,7 @@
 
 
 /*
- * Action taken when an error occure
+ * Action taken when an error occurred
  */
 
 void
@@ -468,7 +452,7 @@
  */
 
 void *
-cl_list::first_that(match_func test, void *arg)
+cl_list::first_that(match_func test, const void *arg)
 {
   for (t_index i= 0; i < count; i++)
     {
@@ -538,7 +522,7 @@
  */
 
 t_index
-cl_list::index_of(void *item)
+cl_list::index_of(const void *item)
 {
   for (t_index i= 0; i < count; i++)
     if (item == Items[i])
@@ -548,7 +532,7 @@
 }
 
 bool
-cl_list::index_of(void *item, t_index *idx)
+cl_list::index_of(const void *item, t_index *idx)
 {
   for (t_index i= 0; i < count; i++)
     if (item == Items[i])
@@ -611,7 +595,7 @@
  */
 
 void *
-cl_list::last_that(match_func test, void *arg)
+cl_list::last_that(match_func test, const void *arg)
 {
   for(t_index i= count; i > 0; i--)
     if (test(Items[i-1], arg))
@@ -683,15 +667,9 @@
 */
 
 /*
- * Initilizing the sorted collection
+ * Initializing the sorted collection
  */
 
-cl_sorted_list::cl_sorted_list(t_index alimit, t_index adelta, char *aname):
-  cl_list(alimit, adelta, aname)
-{
-  Duplicates= false;
-}
-
 cl_sorted_list::cl_sorted_list(t_index alimit, t_index adelta, const char *aname):
   cl_list(alimit, adelta, aname)
 {
@@ -706,8 +684,8 @@
  * Get the address of the key field in an item.
  */
 
-void *
-cl_sorted_list::key_of(void *item)
+const void *
+cl_sorted_list::key_of(const void *item) const
 {
   return(item);
 }
@@ -718,7 +696,7 @@
  */
 
 t_index
-cl_sorted_list::index_of(void *item)
+cl_sorted_list::index_of(const void *item)
 {
   t_index	i;
 
@@ -761,7 +739,7 @@
  */
 
 bool
-cl_sorted_list::search(void *key, t_index &index)
+cl_sorted_list::search(const void *key, t_index &index)
 {
   t_index l  = 0;
   t_index h  = count - 1;
@@ -796,15 +774,9 @@
 */
 
 /*
- * Initilizing the string collection
+ * Initializing the string collection
  */
 
-cl_strings::cl_strings(t_index alimit, t_index adelta, char *aname):
-  cl_sorted_list(alimit, adelta, aname)
-{
-  Duplicates= true;
-}
-
 cl_strings::cl_strings(t_index alimit, t_index adelta, const char *aname):
   cl_sorted_list(alimit, adelta, aname)
 {
@@ -816,13 +788,13 @@
 
 
 /*
- * Comapare two string from the collection
+ * Compare two string from the collection
  */
 
 int
-cl_strings::compare(void *key1, void *key2)
+cl_strings::compare(const void *key1, const void *key2)
 {
-  return(strcmp((char *)key1, (char *)key2));
+  return strcmp((const char *)key1, (const char *)key2);
 }
 
 
@@ -833,7 +805,7 @@
 void
 cl_strings::free_item(void* item)
 {
-  delete (char*)item;
+  free((char*)item);
 }
 
 
@@ -845,13 +817,9 @@
 */
 
 /*
- * Initilizing the unsorted string collection
+ * Initializing the unsorted string collection
  */
 
-cl_ustrings::cl_ustrings(t_index alimit, t_index adelta, char *aname):
-  cl_strings(alimit, adelta, aname)
-{}
-
 cl_ustrings::cl_ustrings(t_index alimit, t_index adelta, const char *aname):
   cl_strings(alimit, adelta, aname)
 {}
@@ -860,11 +828,11 @@
 
 
 /*
- * Comapare two string from the collection
+ * Compare two string from the collection
  */
 
 int
-cl_ustrings::compare(void *key1, void *key2)
+cl_ustrings::compare(const void *key1, const void *key2)
 {
   return(-1);
 }
@@ -875,11 +843,11 @@
  */
 
 bool
-cl_ustrings::search(void *key, t_index& index)
+cl_ustrings::search(const void *key, t_index& index)
 {
   t_index i    = 0;
   bool    found= false;
-  void    *Actual;
+  const void *Actual;
 
   if ((count) && key)
     {
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/pobjcl.h sdcc-4.2.0+dfsg/sim/ucsim/pobjcl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/pobjcl.h	2016-11-05 14:33:30.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/pobjcl.h	2021-04-01 17:52:48.000000000 +0000
@@ -61,14 +61,14 @@
   virtual ~cl_base(void);
 
   virtual int init(void);
-  virtual const char *get_name(void) { return(name); }
-  virtual const char *get_name(const char *def);
+  virtual const char *get_name(void) const { return(name); }
+  virtual const char *get_name(const char *def) const;
   virtual bool have_name(void) { return/*(name != 0)*/ !name.is_null(); }
   virtual bool have_real_name(void) { return/*(name != 0 && *name != '\0')*/ !name.empty(); }
   const char *set_name(const char *new_name);
   const char *set_name(const char *new_name, const char *def_name);
-  bool is_named(const char *the_name);
-  bool is_inamed(const char *the_name);
+  bool is_named(const char *the_name) const;
+  bool is_inamed(const char *the_name) const;
 
   class cl_base *get_parent(void) { return(parent); }
   int nuof_children(void);
@@ -121,7 +121,6 @@
   t_index	   Delta;
 
 public:
-  cl_list(t_index alimit, t_index adelta, char *aname);
   cl_list(t_index alimit, t_index adelta, const char *aname);
   virtual ~cl_list(void);
 
@@ -132,8 +131,8 @@
     return (Items[index]);
   }
   class cl_base *object_at(t_index index);
-  virtual t_index  index_of(void *item);
-  virtual bool     index_of(void *item, t_index *idx);
+  virtual t_index  index_of(const void *item);
+  virtual bool     index_of(const void *item, t_index *idx);
   virtual void     *next(void *item);
   	  int	   get_count(void);
   virtual void     *pop(void);
@@ -145,7 +144,7 @@
 	  void	   free_at(t_index index);
           void     free_all(void);
 	  void	   disconn_at(t_index index);
-	  void	   disconn(void *item);
+	  void	   disconn(const void *item);
 	  void	   disconn_all(void);
 
 	  void	   add_at(t_index index, void *item);
@@ -154,8 +153,8 @@
   virtual t_index  add(class cl_base *item, class cl_base *parent);
   virtual void     push(void *item);
 
-	  void	   *first_that(match_func test, void *arg);
-	  void	   *last_that(match_func test, void *arg);
+	  void	   *first_that(match_func test, const void *arg);
+	  void	   *last_that(match_func test, const void *arg);
 	  void	   for_each(iterator_func action, void *arg);
 
 	  void	   error(t_index code, t_index info);
@@ -176,16 +175,15 @@
 public:
   bool		   Duplicates;
 public:
-  cl_sorted_list(t_index alimit, t_index adelta, char *aname);
   cl_sorted_list(t_index alimit, t_index adelta, const char *aname);
   virtual ~cl_sorted_list(void);
   
-  virtual bool	   search(void *key, t_index& index);
-  virtual t_index  index_of(void *item);
+  virtual bool	   search(const void *key, t_index& index);
+  virtual t_index  index_of(const void *item);
   virtual t_index  add(void *item);
-  virtual void	   *key_of(void *item);
+  virtual const void *key_of(const void *item) const;
 private:
-  virtual int	   compare(void *key1, void *key2)= 0;
+  virtual int	   compare(const void *key1, const void *key2)= 0;
 };
 
 
@@ -199,12 +197,12 @@
 class cl_strings: public cl_sorted_list
 {
 public:
-  cl_strings(t_index alimit, t_index adelta, char *aname);
   cl_strings(t_index alimit, t_index adelta, const char *aname);
   virtual ~cl_strings(void);
+  inline  const char *at(t_index index) { return (char *)cl_sorted_list::at(index); }
   
 private:
-  virtual int	   compare(void *key1, void *key2);
+  virtual int	   compare(const void *key1, const void *key2);
   virtual void	   free_item(void *item);
 };
 
@@ -219,13 +217,12 @@
 class cl_ustrings: public cl_strings
 {
 public:
-  cl_ustrings(t_index alimit, t_index adelta, char *aname);
   cl_ustrings(t_index alimit, t_index adelta, const char *aname);
   virtual ~cl_ustrings(void);
   
 private:
-  virtual int	   compare(void *key1, void *key2);
-  virtual bool	   search(void *key, t_index &index);
+  virtual int	   compare(const void *key1, const void *key2);
+  virtual bool	   search(const void *key, t_index &index);
 };
 
 
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/pobjt.h sdcc-4.2.0+dfsg/sim/ucsim/pobjt.h
--- sdcc-4.0.0+dfsg/sim/ucsim/pobjt.h	2016-10-04 10:51:37.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/pobjt.h	2020-09-17 09:34:03.000000000 +0000
@@ -32,8 +32,8 @@
 
 
 typedef int	t_index;
-typedef int	(*match_func)(void *, void *);
-typedef void	(*iterator_func)(void *, void *);
+typedef int	(*match_func)(const void *, const void *);
+typedef void	(*iterator_func)(const void *, const void *);
 
 #define max_list_size (0x10000/sizeof(void *))
 #define ccNotFound -1
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/README sdcc-4.2.0+dfsg/sim/ucsim/README
--- sdcc-4.0.0+dfsg/sim/ucsim/README	2019-03-26 06:58:18.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/README	2021-09-19 19:38:05.000000000 +0000
@@ -9,7 +9,8 @@
 
 uCsim is a micro-controller simulator. It is extensible to support
 different micro-controller families. Currently it supports Intel MCS51
-family, Z80, ST7, STM8, HC08, XA, TLCS90, and some AVR processors.
+family, XA, Z80, TLCS90, ST7, STM8, PDK, MC6800, MC6809, HC08, MCS6502,
+Rabbit, PicoBlaze and some AVR processors.
 
 
 How to get uCsim?
@@ -112,6 +113,14 @@
 Davide Zanni 
 Anton Persson 
 Nicolas Lesser <>
+Mike Jagdis <>
+Jiri Simek <>
+Zbynek Krivka 
+Vaclav Peroutka 
+Valentin Dudouyt 
+Erik Petrich 
+Leland Morrison <>
+Johan Knol 
 
 Maintainer of serialview: Timothy Hurman 
 Maintainer of other parts: Daniel Drotos 
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/relay.cc sdcc-4.2.0+dfsg/sim/ucsim/relay.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/relay.cc	2017-06-04 15:33:30.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/relay.cc	2021-09-01 06:57:19.000000000 +0000
@@ -1,4 +1,5 @@
-#include 
+//#include 
+#include 
 
 #include "fiocl.h"
 
@@ -47,8 +48,8 @@
 int
 main(int argc, char *argv[])
 {
-  single_in= cp_io(0, "r");
-  single_out= cp_io(1, "w");
+  single_in= cp_io(0, (const char *)"r");
+  single_out= cp_io(1, (const char *)"w");
   single_in->raw();
   single_out->raw();
   
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/7fwrap.cc sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/7fwrap.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/7fwrap.cc	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/7fwrap.cc	2021-08-16 10:12:33.000000000 +0000
@@ -0,0 +1,285 @@
+/*
+ * Simulator of microcontrollers (7fwrap.cc)
+ *
+ * Copyright (C) 2020,2021 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#include "rxkcl.h"
+
+#include "7fwrap.h"
+
+int instruction_wrapper_7f_none(class cl_uc *uc, t_mem code) { return resINV_INST; }
+
+int instruction_wrapper_7f_40(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_40(code); }
+int instruction_wrapper_7f_41(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_41(code); }
+int instruction_wrapper_7f_42(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_42(code); }
+int instruction_wrapper_7f_43(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_43(code); }
+int instruction_wrapper_7f_44(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_44(code); }
+int instruction_wrapper_7f_45(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_45(code); }
+int instruction_wrapper_7f_47(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_47(code); }
+int instruction_wrapper_7f_48(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_48(code); }
+int instruction_wrapper_7f_49(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_49(code); }
+int instruction_wrapper_7f_4a(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_4a(code); }
+int instruction_wrapper_7f_4b(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_4b(code); }
+int instruction_wrapper_7f_4c(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_4c(code); }
+int instruction_wrapper_7f_4d(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_4d(code); }
+int instruction_wrapper_7f_4f(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_4f(code); }
+
+int instruction_wrapper_7f_50(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_50(code); }
+int instruction_wrapper_7f_51(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_51(code); }
+int instruction_wrapper_7f_52(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_52(code); }
+int instruction_wrapper_7f_53(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_53(code); }
+int instruction_wrapper_7f_54(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_54(code); }
+int instruction_wrapper_7f_55(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_55(code); }
+int instruction_wrapper_7f_57(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_57(code); }
+int instruction_wrapper_7f_58(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_58(code); }
+int instruction_wrapper_7f_59(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_59(code); }
+int instruction_wrapper_7f_5a(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_5a(code); }
+int instruction_wrapper_7f_5b(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_5b(code); }
+int instruction_wrapper_7f_5c(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_5c(code); }
+int instruction_wrapper_7f_5d(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_5d(code); }
+int instruction_wrapper_7f_5f(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_5f(code); }
+
+int instruction_wrapper_7f_60(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_60(code); }
+int instruction_wrapper_7f_61(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_61(code); }
+int instruction_wrapper_7f_62(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_62(code); }
+int instruction_wrapper_7f_63(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_63(code); }
+int instruction_wrapper_7f_64(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_64(code); }
+int instruction_wrapper_7f_65(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_65(code); }
+int instruction_wrapper_7f_67(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_67(code); }
+int instruction_wrapper_7f_68(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_68(code); }
+int instruction_wrapper_7f_69(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_69(code); }
+int instruction_wrapper_7f_6a(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_6a(code); }
+int instruction_wrapper_7f_6b(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_6b(code); }
+int instruction_wrapper_7f_6c(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_6c(code); }
+int instruction_wrapper_7f_6d(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_6d(code); }
+int instruction_wrapper_7f_6f(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_6f(code); }
+
+int instruction_wrapper_7f_78(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_78(code); }
+int instruction_wrapper_7f_79(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_79(code); }
+int instruction_wrapper_7f_7a(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_7a(code); }
+int instruction_wrapper_7f_7b(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_7b(code); }
+int instruction_wrapper_7f_7c(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_7c(code); }
+int instruction_wrapper_7f_7d(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_7d(code); }
+int instruction_wrapper_7f_7f(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_7f(code); }
+
+int instruction_wrapper_7f_80(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_80(code); }
+int instruction_wrapper_7f_81(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_81(code); }
+int instruction_wrapper_7f_82(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_82(code); }
+int instruction_wrapper_7f_83(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_83(code); }
+int instruction_wrapper_7f_84(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_84(code); }
+int instruction_wrapper_7f_85(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_85(code); }
+int instruction_wrapper_7f_86(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_86(code); }
+int instruction_wrapper_7f_87(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_87(code); }
+int instruction_wrapper_7f_88(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_88(code); }
+int instruction_wrapper_7f_89(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_89(code); }
+int instruction_wrapper_7f_8a(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_8a(code); }
+int instruction_wrapper_7f_8b(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_8b(code); }
+int instruction_wrapper_7f_8c(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_8c(code); }
+int instruction_wrapper_7f_8d(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_8d(code); }
+int instruction_wrapper_7f_8e(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_8e(code); }
+int instruction_wrapper_7f_8f(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_8f(code); }
+
+int instruction_wrapper_7f_90(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_90(code); }
+int instruction_wrapper_7f_91(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_91(code); }
+int instruction_wrapper_7f_92(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_92(code); }
+int instruction_wrapper_7f_93(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_93(code); }
+int instruction_wrapper_7f_94(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_94(code); }
+int instruction_wrapper_7f_95(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_95(code); }
+int instruction_wrapper_7f_96(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_96(code); }
+int instruction_wrapper_7f_97(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_97(code); }
+int instruction_wrapper_7f_98(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_98(code); }
+int instruction_wrapper_7f_99(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_99(code); }
+int instruction_wrapper_7f_9a(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_9a(code); }
+int instruction_wrapper_7f_9b(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_9b(code); }
+int instruction_wrapper_7f_9c(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_9c(code); }
+int instruction_wrapper_7f_9d(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_9d(code); }
+int instruction_wrapper_7f_9e(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_9e(code); }
+int instruction_wrapper_7f_9f(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_9f(code); }
+
+int instruction_wrapper_7f_a0(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_a0(code); }
+int instruction_wrapper_7f_a1(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_a1(code); }
+int instruction_wrapper_7f_a2(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_a2(code); }
+int instruction_wrapper_7f_a3(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_a3(code); }
+int instruction_wrapper_7f_a4(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_a4(code); }
+int instruction_wrapper_7f_a5(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_a5(code); }
+int instruction_wrapper_7f_a6(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_a6(code); }
+int instruction_wrapper_7f_a7(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_a7(code); }
+int instruction_wrapper_7f_a8(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_a8(code); }
+int instruction_wrapper_7f_a9(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_a9(code); }
+int instruction_wrapper_7f_aa(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_aa(code); }
+int instruction_wrapper_7f_ab(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ab(code); }
+int instruction_wrapper_7f_ac(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ac(code); }
+int instruction_wrapper_7f_ad(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ad(code); }
+int instruction_wrapper_7f_ae(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ae(code); }
+int instruction_wrapper_7f_af(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_af(code); }
+
+int instruction_wrapper_7f_b0(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_b0(code); }
+int instruction_wrapper_7f_b1(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_b1(code); }
+int instruction_wrapper_7f_b2(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_b2(code); }
+int instruction_wrapper_7f_b3(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_b3(code); }
+int instruction_wrapper_7f_b4(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_b4(code); }
+int instruction_wrapper_7f_b5(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_b5(code); }
+int instruction_wrapper_7f_b6(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_b6(code); }
+int instruction_wrapper_7f_b7(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_b7(code); }
+int instruction_wrapper_7f_b8(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_b8(code); }
+int instruction_wrapper_7f_b9(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_b9(code); }
+int instruction_wrapper_7f_ba(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ba(code); }
+int instruction_wrapper_7f_bb(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_bb(code); }
+int instruction_wrapper_7f_bc(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_bc(code); }
+int instruction_wrapper_7f_bd(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_bd(code); }
+int instruction_wrapper_7f_be(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_be(code); }
+int instruction_wrapper_7f_bf(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_bf(code); }
+
+
+void fill_7f_wrappers(instruction_wrapper_fn itab[])
+{
+  int i;
+  for (i=0; i<256; i++)
+    {
+      itab[i]= instruction_wrapper_7f_none;
+    }
+  itab[0x40]= instruction_wrapper_7f_40;
+  itab[0x41]= instruction_wrapper_7f_41;
+  itab[0x42]= instruction_wrapper_7f_42;
+  itab[0x43]= instruction_wrapper_7f_43;
+  itab[0x44]= instruction_wrapper_7f_44;
+  itab[0x45]= instruction_wrapper_7f_45;
+  itab[0x47]= instruction_wrapper_7f_47;
+  itab[0x48]= instruction_wrapper_7f_48;
+  itab[0x49]= instruction_wrapper_7f_49;
+  itab[0x4a]= instruction_wrapper_7f_4a;
+  itab[0x4b]= instruction_wrapper_7f_4b;
+  itab[0x4c]= instruction_wrapper_7f_4c;
+  itab[0x4d]= instruction_wrapper_7f_4d;
+  itab[0x4f]= instruction_wrapper_7f_4f;
+
+  itab[0x50]= instruction_wrapper_7f_50;
+  itab[0x51]= instruction_wrapper_7f_51;
+  itab[0x52]= instruction_wrapper_7f_52;
+  itab[0x53]= instruction_wrapper_7f_53;
+  itab[0x54]= instruction_wrapper_7f_54;
+  itab[0x55]= instruction_wrapper_7f_55;
+  itab[0x57]= instruction_wrapper_7f_57;
+  itab[0x58]= instruction_wrapper_7f_58;
+  itab[0x59]= instruction_wrapper_7f_59;
+  itab[0x5a]= instruction_wrapper_7f_5a;
+  itab[0x5b]= instruction_wrapper_7f_5b;
+  itab[0x5c]= instruction_wrapper_7f_5c;
+  itab[0x5d]= instruction_wrapper_7f_5d;
+  itab[0x5f]= instruction_wrapper_7f_5f;
+
+  itab[0x60]= instruction_wrapper_7f_60;
+  itab[0x61]= instruction_wrapper_7f_61;
+  itab[0x62]= instruction_wrapper_7f_62;
+  itab[0x63]= instruction_wrapper_7f_63;
+  itab[0x64]= instruction_wrapper_7f_64;
+  itab[0x65]= instruction_wrapper_7f_65;
+  itab[0x67]= instruction_wrapper_7f_67;
+  itab[0x68]= instruction_wrapper_7f_68;
+  itab[0x69]= instruction_wrapper_7f_69;
+  itab[0x6a]= instruction_wrapper_7f_6a;
+  itab[0x6b]= instruction_wrapper_7f_6b;
+  itab[0x6c]= instruction_wrapper_7f_6c;
+  itab[0x6d]= instruction_wrapper_7f_6d;
+  itab[0x6f]= instruction_wrapper_7f_6f;
+
+  itab[0x78]= instruction_wrapper_7f_78;
+  itab[0x79]= instruction_wrapper_7f_79;
+  itab[0x7a]= instruction_wrapper_7f_7a;
+  itab[0x7b]= instruction_wrapper_7f_7b;
+  itab[0x7c]= instruction_wrapper_7f_7c;
+  itab[0x7d]= instruction_wrapper_7f_7d;
+  itab[0x7f]= instruction_wrapper_7f_7f;
+
+  itab[0x80]= instruction_wrapper_7f_80;
+  itab[0x81]= instruction_wrapper_7f_81;
+  itab[0x82]= instruction_wrapper_7f_82;
+  itab[0x83]= instruction_wrapper_7f_83;
+  itab[0x84]= instruction_wrapper_7f_84;
+  itab[0x85]= instruction_wrapper_7f_85;
+  itab[0x86]= instruction_wrapper_7f_86;
+  itab[0x87]= instruction_wrapper_7f_87;
+  itab[0x88]= instruction_wrapper_7f_88;
+  itab[0x89]= instruction_wrapper_7f_89;
+  itab[0x8a]= instruction_wrapper_7f_8a;
+  itab[0x8b]= instruction_wrapper_7f_8b;
+  itab[0x8c]= instruction_wrapper_7f_8c;
+  itab[0x8d]= instruction_wrapper_7f_8d;
+  itab[0x8e]= instruction_wrapper_7f_8e;
+  itab[0x8f]= instruction_wrapper_7f_8f;
+
+  itab[0x90]= instruction_wrapper_7f_90;
+  itab[0x91]= instruction_wrapper_7f_91;
+  itab[0x92]= instruction_wrapper_7f_92;
+  itab[0x93]= instruction_wrapper_7f_93;
+  itab[0x94]= instruction_wrapper_7f_94;
+  itab[0x95]= instruction_wrapper_7f_95;
+  itab[0x96]= instruction_wrapper_7f_96;
+  itab[0x97]= instruction_wrapper_7f_97;
+  itab[0x98]= instruction_wrapper_7f_98;
+  itab[0x99]= instruction_wrapper_7f_99;
+  itab[0x9a]= instruction_wrapper_7f_9a;
+  itab[0x9b]= instruction_wrapper_7f_9b;
+  itab[0x9c]= instruction_wrapper_7f_9c;
+  itab[0x9d]= instruction_wrapper_7f_9d;
+  itab[0x9e]= instruction_wrapper_7f_9e;
+  itab[0x9f]= instruction_wrapper_7f_9f;
+
+  itab[0xa0]= instruction_wrapper_7f_a0;
+  itab[0xa1]= instruction_wrapper_7f_a1;
+  itab[0xa2]= instruction_wrapper_7f_a2;
+  itab[0xa3]= instruction_wrapper_7f_a3;
+  itab[0xa4]= instruction_wrapper_7f_a4;
+  itab[0xa5]= instruction_wrapper_7f_a5;
+  itab[0xa6]= instruction_wrapper_7f_a6;
+  itab[0xa7]= instruction_wrapper_7f_a7;
+  itab[0xa8]= instruction_wrapper_7f_a8;
+  itab[0xa9]= instruction_wrapper_7f_a9;
+  itab[0xaa]= instruction_wrapper_7f_aa;
+  itab[0xab]= instruction_wrapper_7f_ab;
+  itab[0xac]= instruction_wrapper_7f_ac;
+  itab[0xad]= instruction_wrapper_7f_ad;
+  itab[0xae]= instruction_wrapper_7f_ae;
+  itab[0xaf]= instruction_wrapper_7f_af;
+
+  itab[0xb0]= instruction_wrapper_7f_b0;
+  itab[0xb1]= instruction_wrapper_7f_b1;
+  itab[0xb2]= instruction_wrapper_7f_b2;
+  itab[0xb3]= instruction_wrapper_7f_b3;
+  itab[0xb4]= instruction_wrapper_7f_b4;
+  itab[0xb5]= instruction_wrapper_7f_b5;
+  itab[0xb6]= instruction_wrapper_7f_b6;
+  itab[0xb7]= instruction_wrapper_7f_b7;
+  itab[0xb8]= instruction_wrapper_7f_b8;
+  itab[0xb9]= instruction_wrapper_7f_b9;
+  itab[0xba]= instruction_wrapper_7f_ba;
+  itab[0xbb]= instruction_wrapper_7f_bb;
+  itab[0xbc]= instruction_wrapper_7f_bc;
+  itab[0xbd]= instruction_wrapper_7f_bd;
+  itab[0xbe]= instruction_wrapper_7f_be;
+  itab[0xbf]= instruction_wrapper_7f_bf;
+}
+
+/* End of rxk.src/7fwrap.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/7fwrap.h sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/7fwrap.h
--- sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/7fwrap.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/7fwrap.h	2021-08-16 10:12:33.000000000 +0000
@@ -0,0 +1,37 @@
+/*
+ * Simulator of microcontrollers (7fwrap.h)
+ *
+ * Copyright (C) 2020,2021 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef _7FWRAP_HEADER
+#define _7FWRAP_HEADER
+
+#include "iwrap.h"
+
+extern void fill_7f_wrappers(instruction_wrapper_fn itab[]);
+
+#endif
+
+/* End of rxk.src/7fwrap.h */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/(c).1 sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/(c).1
--- sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/(c).1	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/(c).1	2021-04-23 13:47:20.000000000 +0000
@@ -0,0 +1,25 @@
+/*
+ * Simulator of microcontrollers (@@F@@)
+ *
+ * Copyright (C) @@S@@,@@Y@@ Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/clean.mk sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/clean.mk
--- sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/clean.mk	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/clean.mk	2021-09-01 06:57:19.000000000 +0000
@@ -0,0 +1,33 @@
+# rxk.src/clean.mk
+
+# Deleting all files created by building the program
+# --------------------------------------------------
+clean:
+	rm -f *core *[%~] *.[oa] *.map
+	rm -f .[a-z]*~
+	rm -f srxk$(EXEEXT) srxk.exe
+	rm -f ucsim_rxk$(EXEEXT) ucsim_rxk.exe
+	rm -f gen_insts gen_wrap
+	$(MAKE) -C test -f clean.mk clean
+
+
+# Deleting all files created by configuring or building the program
+# -----------------------------------------------------------------
+distclean: clean
+	rm -f config.cache config.log config.status
+	rm -f Makefile *.dep
+	rm -f *.obj *.list *.lst *.hex
+	$(MAKE) -C test -f clean.mk distclean
+
+
+# Like clean but some files may still exist
+# -----------------------------------------
+mostlyclean: clean
+
+
+# Deleting everything that can reconstructed by this Makefile. It deletes
+# everything deleted by distclean plus files created by bison, etc.
+# -----------------------------------------------------------------------
+realclean: distclean
+
+# End of rxk.src/clean.mk
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/conf.mk sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/conf.mk
--- sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/conf.mk	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/conf.mk	2021-04-23 13:47:20.000000000 +0000
@@ -0,0 +1,11 @@
+# rxk.src/conf.mk
+#
+# Makefile targets to remake configuration
+#
+
+freshconf: Makefile
+
+Makefile: $(srcdir)/Makefile.in $(top_srcdir)/configure.ac
+	cd $(top_builddir) && $(SHELL) ./config.status
+
+# End of rxk.src/conf.mk
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/dd_instructions.h sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/dd_instructions.h
--- sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/dd_instructions.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/dd_instructions.h	2021-08-23 11:54:00.000000000 +0000
@@ -0,0 +1,148 @@
+virtual int instruction_dd_06(t_mem code) { return resINV; }
+virtual int instruction_dd_09(t_mem code) { return resNOT_DONE; }
+virtual int instruction_dd_0a(t_mem code) { return resINV; }
+virtual int instruction_dd_0b(t_mem code) { return resINV; }
+virtual int instruction_dd_0c(t_mem code) { return resINV; }
+virtual int instruction_dd_0d(t_mem code) { return resINV; }
+virtual int instruction_dd_0e(t_mem code) { return resINV; }
+virtual int instruction_dd_0f(t_mem code) { return resINV; }
+
+virtual int instruction_dd_19(t_mem code) { return resNOT_DONE; }
+virtual int instruction_dd_1a(t_mem code) { return resINV; }
+virtual int instruction_dd_1b(t_mem code) { return resINV; }
+virtual int instruction_dd_1c(t_mem code) { return resINV; }
+virtual int instruction_dd_1d(t_mem code) { return resINV; }
+virtual int instruction_dd_1e(t_mem code) { return resINV; }
+virtual int instruction_dd_1f(t_mem code) { return resINV; }
+
+virtual int instruction_dd_21(t_mem code) { return resNOT_DONE; }
+virtual int instruction_dd_22(t_mem code) { return resNOT_DONE; }
+virtual int instruction_dd_23(t_mem code) { return resNOT_DONE; }
+virtual int instruction_dd_29(t_mem code) { return resNOT_DONE; }
+virtual int instruction_dd_2a(t_mem code) { return resNOT_DONE; }
+virtual int instruction_dd_2b(t_mem code) { return resNOT_DONE; }
+virtual int instruction_dd_2c(t_mem code) { return resINV; }
+virtual int instruction_dd_2d(t_mem code) { return resINV; }
+virtual int instruction_dd_2e(t_mem code) { return resINV; }
+virtual int instruction_dd_2f(t_mem code) { return resINV; }
+
+virtual int instruction_dd_34(t_mem code) { return resNOT_DONE; }
+virtual int instruction_dd_35(t_mem code) { return resNOT_DONE; }
+virtual int instruction_dd_36(t_mem code) { return resNOT_DONE; }
+virtual int instruction_dd_39(t_mem code) { return resNOT_DONE; }
+virtual int instruction_dd_3c(t_mem code) { return resINV; }
+virtual int instruction_dd_3d(t_mem code) { return resINV; }
+virtual int instruction_dd_3e(t_mem code) { return resINV; }
+virtual int instruction_dd_3f(t_mem code) { return resINV; }
+
+virtual int instruction_dd_46(t_mem code) { return resNOT_DONE; }
+virtual int instruction_dd_48(t_mem code) { return resNOT_DONE; }
+virtual int instruction_dd_49(t_mem code) { return resNOT_DONE; }
+virtual int instruction_dd_4b(t_mem code) { return resNOT_DONE; }
+virtual int instruction_dd_4c(t_mem code) { return resINV; }
+virtual int instruction_dd_4d(t_mem code) { return resINV; }
+virtual int instruction_dd_4e(t_mem code) { return resNOT_DONE; }
+virtual int instruction_dd_4f(t_mem code) { return resINV; }
+
+virtual int instruction_dd_56(t_mem code) { return resNOT_DONE; }
+virtual int instruction_dd_58(t_mem code) { return resINV; }
+virtual int instruction_dd_59(t_mem code) { return resINV; }
+virtual int instruction_dd_5b(t_mem code) { return resINV; }
+virtual int instruction_dd_5c(t_mem code) { return resINV; }
+virtual int instruction_dd_5e(t_mem code) { return resNOT_DONE; }
+virtual int instruction_dd_5f(t_mem code) { return resINV; }
+
+virtual int instruction_dd_64(t_mem code) { return resNOT_DONE; }
+virtual int instruction_dd_65(t_mem code) { return resNOT_DONE; }
+virtual int instruction_dd_66(t_mem code) { return resNOT_DONE; }
+virtual int instruction_dd_68(t_mem code) { return resINV; }
+virtual int instruction_dd_69(t_mem code) { return resINV; }
+virtual int instruction_dd_6b(t_mem code) { return resINV; }
+virtual int instruction_dd_6c(t_mem code) { return resNOT_DONE; }
+virtual int instruction_dd_6d(t_mem code) { return resNOT_DONE; }
+virtual int instruction_dd_6e(t_mem code) { return resNOT_DONE; }
+virtual int instruction_dd_6f(t_mem code) { return resINV; }
+
+virtual int instruction_dd_70(t_mem code) { return resNOT_DONE; }
+virtual int instruction_dd_71(t_mem code) { return resNOT_DONE; }
+virtual int instruction_dd_72(t_mem code) { return resNOT_DONE; }
+virtual int instruction_dd_73(t_mem code) { return resNOT_DONE; }
+virtual int instruction_dd_74(t_mem code) { return resNOT_DONE; }
+virtual int instruction_dd_75(t_mem code) { return resNOT_DONE; }
+virtual int instruction_dd_77(t_mem code) { return resNOT_DONE; }
+virtual int instruction_dd_78(t_mem code) { return resINV; }
+virtual int instruction_dd_79(t_mem code) { return resINV; }
+virtual int instruction_dd_7b(t_mem code) { return resINV; }
+virtual int instruction_dd_7c(t_mem code) { return resNOT_DONE; }
+virtual int instruction_dd_7d(t_mem code) { return resNOT_DONE; }
+virtual int instruction_dd_7e(t_mem code) { return resNOT_DONE; }
+virtual int instruction_dd_7f(t_mem code) { return resINV; }
+
+virtual int instruction_dd_86(t_mem code) { return resNOT_DONE; }
+virtual int instruction_dd_88(t_mem code) { return resINV; }
+virtual int instruction_dd_89(t_mem code) { return resINV; }
+virtual int instruction_dd_8b(t_mem code) { return resINV; }
+virtual int instruction_dd_8c(t_mem code) { return resINV; }
+virtual int instruction_dd_8d(t_mem code) { return resINV; }
+virtual int instruction_dd_8e(t_mem code) { return resNOT_DONE; }
+virtual int instruction_dd_8f(t_mem code) { return resINV; }
+
+virtual int instruction_dd_96(t_mem code) { return resNOT_DONE; }
+virtual int instruction_dd_98(t_mem code) { return resINV; }
+virtual int instruction_dd_99(t_mem code) { return resINV; }
+virtual int instruction_dd_9b(t_mem code) { return resINV; }
+virtual int instruction_dd_9c(t_mem code) { return resINV; }
+virtual int instruction_dd_9d(t_mem code) { return resINV; }
+virtual int instruction_dd_9e(t_mem code) { return resNOT_DONE; }
+virtual int instruction_dd_9f(t_mem code) { return resINV; }
+
+virtual int instruction_dd_a6(t_mem code) { return resNOT_DONE; }
+virtual int instruction_dd_a8(t_mem code) { return resINV; }
+virtual int instruction_dd_a9(t_mem code) { return resINV; }
+virtual int instruction_dd_ab(t_mem code) { return resINV; }
+virtual int instruction_dd_ac(t_mem code) { return resINV; }
+virtual int instruction_dd_ad(t_mem code) { return resINV; }
+virtual int instruction_dd_ae(t_mem code) { return resNOT_DONE; }
+virtual int instruction_dd_af(t_mem code) { return resINV; }
+
+virtual int instruction_dd_b6(t_mem code) { return resNOT_DONE; }
+virtual int instruction_dd_b8(t_mem code) { return resINV; }
+virtual int instruction_dd_b9(t_mem code) { return resINV; }
+virtual int instruction_dd_bb(t_mem code) { return resINV; }
+virtual int instruction_dd_bc(t_mem code) { return resINV; }
+virtual int instruction_dd_bd(t_mem code) { return resINV; }
+virtual int instruction_dd_be(t_mem code) { return resNOT_DONE; }
+virtual int instruction_dd_bf(t_mem code) { return resINV; }
+
+virtual int instruction_dd_c4(t_mem code) { return resNOT_DONE; }
+virtual int instruction_dd_cb(t_mem code) { return resNOT_DONE; }
+virtual int instruction_dd_cc(t_mem code) { return resNOT_DONE; }
+virtual int instruction_dd_cd(t_mem code) { return resINV; }
+virtual int instruction_dd_ce(t_mem code) { return resINV; }
+virtual int instruction_dd_cf(t_mem code) { return resINV; }
+
+virtual int instruction_dd_d4(t_mem code) { return resNOT_DONE; }
+virtual int instruction_dd_dc(t_mem code) { return resNOT_DONE; }
+virtual int instruction_dd_dd(t_mem code) { return resINV; }
+virtual int instruction_dd_de(t_mem code) { return resINV; }
+virtual int instruction_dd_df(t_mem code) { return resINV; }
+
+virtual int instruction_dd_e1(t_mem code) { return resNOT_DONE; }
+virtual int instruction_dd_e3(t_mem code) { return resNOT_DONE; }
+virtual int instruction_dd_e4(t_mem code) { return resNOT_DONE; }
+virtual int instruction_dd_e5(t_mem code) { return resNOT_DONE; }
+virtual int instruction_dd_e9(t_mem code) { return resNOT_DONE; }
+virtual int instruction_dd_ea(t_mem code) { return resINV; }
+virtual int instruction_dd_ec(t_mem code) { return resNOT_DONE; }
+virtual int instruction_dd_ed(t_mem code) { return resINV; }
+virtual int instruction_dd_ee(t_mem code) { return resINV; }
+virtual int instruction_dd_ef(t_mem code) { return resINV; }
+
+virtual int instruction_dd_f1(t_mem code) { return resNOT_DONE; }
+virtual int instruction_dd_f4(t_mem code) { return resNOT_DONE; }
+virtual int instruction_dd_f5(t_mem code) { return resINV; }
+virtual int instruction_dd_f9(t_mem code) { return resNOT_DONE; }
+virtual int instruction_dd_fc(t_mem code) { return resNOT_DONE; }
+virtual int instruction_dd_fd(t_mem code) { return resINV; }
+virtual int instruction_dd_fe(t_mem code) { return resINV; }
+virtual int instruction_dd_ff(t_mem code) { return resINV; }
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/ddwrap.cc sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/ddwrap.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/ddwrap.cc	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/ddwrap.cc	2021-07-16 14:31:13.000000000 +0000
@@ -0,0 +1,341 @@
+/*
+ * Simulator of microcontrollers (ddwrap.cc)
+ *
+ * Copyright (C) 2020,2021 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#include "rxkcl.h"
+
+#include "ddwrap.h"
+
+int instruction_wrapper_dd_none(class cl_uc *uc, t_mem code) { return resINV_INST; }
+
+int instruction_wrapper_dd_06(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_06(code); }
+int instruction_wrapper_dd_09(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_09(code); }
+int instruction_wrapper_dd_0a(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_0a(code); }
+int instruction_wrapper_dd_0b(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_0b(code); }
+int instruction_wrapper_dd_0c(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_0c(code); }
+int instruction_wrapper_dd_0d(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_0d(code); }
+int instruction_wrapper_dd_0e(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_0e(code); }
+int instruction_wrapper_dd_0f(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_0f(code); }
+
+int instruction_wrapper_dd_19(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_19(code); }
+int instruction_wrapper_dd_1a(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_1a(code); }
+int instruction_wrapper_dd_1b(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_1b(code); }
+int instruction_wrapper_dd_1c(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_1c(code); }
+int instruction_wrapper_dd_1d(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_1d(code); }
+int instruction_wrapper_dd_1e(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_1e(code); }
+int instruction_wrapper_dd_1f(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_1f(code); }
+
+int instruction_wrapper_dd_21(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_21(code); }
+int instruction_wrapper_dd_22(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_22(code); }
+int instruction_wrapper_dd_23(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_23(code); }
+int instruction_wrapper_dd_29(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_29(code); }
+int instruction_wrapper_dd_2a(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_2a(code); }
+int instruction_wrapper_dd_2b(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_2b(code); }
+int instruction_wrapper_dd_2c(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_2c(code); }
+int instruction_wrapper_dd_2d(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_2d(code); }
+int instruction_wrapper_dd_2e(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_2e(code); }
+int instruction_wrapper_dd_2f(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_2f(code); }
+
+int instruction_wrapper_dd_34(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_34(code); }
+int instruction_wrapper_dd_35(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_35(code); }
+int instruction_wrapper_dd_36(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_36(code); }
+int instruction_wrapper_dd_39(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_39(code); }
+int instruction_wrapper_dd_3c(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_3c(code); }
+int instruction_wrapper_dd_3d(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_3d(code); }
+int instruction_wrapper_dd_3e(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_3e(code); }
+int instruction_wrapper_dd_3f(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_3f(code); }
+
+int instruction_wrapper_dd_46(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_46(code); }
+int instruction_wrapper_dd_48(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_48(code); }
+int instruction_wrapper_dd_49(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_49(code); }
+int instruction_wrapper_dd_4b(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_4b(code); }
+int instruction_wrapper_dd_4c(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_4c(code); }
+int instruction_wrapper_dd_4d(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_4d(code); }
+int instruction_wrapper_dd_4e(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_4e(code); }
+int instruction_wrapper_dd_4f(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_4f(code); }
+
+int instruction_wrapper_dd_56(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_56(code); }
+int instruction_wrapper_dd_58(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_58(code); }
+int instruction_wrapper_dd_59(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_59(code); }
+int instruction_wrapper_dd_5b(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_5b(code); }
+int instruction_wrapper_dd_5c(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_5c(code); }
+int instruction_wrapper_dd_5e(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_5e(code); }
+int instruction_wrapper_dd_5f(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_5f(code); }
+
+int instruction_wrapper_dd_64(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_64(code); }
+int instruction_wrapper_dd_65(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_65(code); }
+int instruction_wrapper_dd_66(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_66(code); }
+int instruction_wrapper_dd_68(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_68(code); }
+int instruction_wrapper_dd_69(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_69(code); }
+int instruction_wrapper_dd_6b(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_6b(code); }
+int instruction_wrapper_dd_6c(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_6c(code); }
+int instruction_wrapper_dd_6d(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_6d(code); }
+int instruction_wrapper_dd_6e(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_6e(code); }
+int instruction_wrapper_dd_6f(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_6f(code); }
+
+int instruction_wrapper_dd_70(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_70(code); }
+int instruction_wrapper_dd_71(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_71(code); }
+int instruction_wrapper_dd_72(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_72(code); }
+int instruction_wrapper_dd_73(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_73(code); }
+int instruction_wrapper_dd_74(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_74(code); }
+int instruction_wrapper_dd_75(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_75(code); }
+int instruction_wrapper_dd_77(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_77(code); }
+int instruction_wrapper_dd_78(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_78(code); }
+int instruction_wrapper_dd_79(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_79(code); }
+int instruction_wrapper_dd_7b(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_7b(code); }
+int instruction_wrapper_dd_7c(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_7c(code); }
+int instruction_wrapper_dd_7d(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_7d(code); }
+int instruction_wrapper_dd_7e(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_7e(code); }
+int instruction_wrapper_dd_7f(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_7f(code); }
+
+int instruction_wrapper_dd_86(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_86(code); }
+int instruction_wrapper_dd_88(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_88(code); }
+int instruction_wrapper_dd_89(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_89(code); }
+int instruction_wrapper_dd_8b(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_8b(code); }
+int instruction_wrapper_dd_8c(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_8c(code); }
+int instruction_wrapper_dd_8d(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_8d(code); }
+int instruction_wrapper_dd_8e(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_8e(code); }
+int instruction_wrapper_dd_8f(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_8f(code); }
+
+int instruction_wrapper_dd_96(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_96(code); }
+int instruction_wrapper_dd_98(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_98(code); }
+int instruction_wrapper_dd_99(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_99(code); }
+int instruction_wrapper_dd_9b(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_9b(code); }
+int instruction_wrapper_dd_9c(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_9c(code); }
+int instruction_wrapper_dd_9d(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_9d(code); }
+int instruction_wrapper_dd_9e(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_9e(code); }
+int instruction_wrapper_dd_9f(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_9f(code); }
+
+int instruction_wrapper_dd_a6(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_a6(code); }
+int instruction_wrapper_dd_a8(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_a8(code); }
+int instruction_wrapper_dd_a9(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_a9(code); }
+int instruction_wrapper_dd_ab(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_ab(code); }
+int instruction_wrapper_dd_ac(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_ac(code); }
+int instruction_wrapper_dd_ad(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_ad(code); }
+int instruction_wrapper_dd_ae(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_ae(code); }
+int instruction_wrapper_dd_af(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_af(code); }
+
+int instruction_wrapper_dd_b6(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_b6(code); }
+int instruction_wrapper_dd_b8(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_b8(code); }
+int instruction_wrapper_dd_b9(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_b9(code); }
+int instruction_wrapper_dd_bb(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_bb(code); }
+int instruction_wrapper_dd_bc(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_bc(code); }
+int instruction_wrapper_dd_bd(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_bd(code); }
+int instruction_wrapper_dd_be(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_be(code); }
+int instruction_wrapper_dd_bf(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_bf(code); }
+
+int instruction_wrapper_dd_c4(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_c4(code); }
+int instruction_wrapper_dd_cb(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_cb(code); }
+int instruction_wrapper_dd_cc(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_cc(code); }
+int instruction_wrapper_dd_cd(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_cd(code); }
+int instruction_wrapper_dd_ce(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_ce(code); }
+int instruction_wrapper_dd_cf(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_cf(code); }
+
+int instruction_wrapper_dd_d4(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_d4(code); }
+int instruction_wrapper_dd_dc(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_dc(code); }
+int instruction_wrapper_dd_dd(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_dd(code); }
+int instruction_wrapper_dd_de(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_de(code); }
+int instruction_wrapper_dd_df(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_df(code); }
+
+int instruction_wrapper_dd_e1(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_e1(code); }
+int instruction_wrapper_dd_e3(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_e3(code); }
+int instruction_wrapper_dd_e4(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_e4(code); }
+int instruction_wrapper_dd_e5(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_e5(code); }
+int instruction_wrapper_dd_e9(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_e9(code); }
+int instruction_wrapper_dd_ea(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_ea(code); }
+int instruction_wrapper_dd_ec(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_ec(code); }
+int instruction_wrapper_dd_ed(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_ed(code); }
+int instruction_wrapper_dd_ee(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_ee(code); }
+int instruction_wrapper_dd_ef(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_ef(code); }
+
+int instruction_wrapper_dd_f1(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_f1(code); }
+int instruction_wrapper_dd_f4(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_f4(code); }
+int instruction_wrapper_dd_f5(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_f5(code); }
+int instruction_wrapper_dd_f9(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_f9(code); }
+int instruction_wrapper_dd_fc(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_fc(code); }
+int instruction_wrapper_dd_fd(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_fd(code); }
+int instruction_wrapper_dd_fe(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_fe(code); }
+int instruction_wrapper_dd_ff(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_dd_ff(code); }
+
+
+void fill_dd_wrappers(instruction_wrapper_fn itab[])
+{
+  int i;
+  for (i=0; i<256; i++)
+    {
+      itab[i]= instruction_wrapper_dd_none;
+    }
+  itab[0x06]= instruction_wrapper_dd_06;
+  itab[0x09]= instruction_wrapper_dd_09;
+  itab[0x0a]= instruction_wrapper_dd_0a;
+  itab[0x0b]= instruction_wrapper_dd_0b;
+  itab[0x0c]= instruction_wrapper_dd_0c;
+  itab[0x0d]= instruction_wrapper_dd_0d;
+  itab[0x0e]= instruction_wrapper_dd_0e;
+  itab[0x0f]= instruction_wrapper_dd_0f;
+
+  itab[0x19]= instruction_wrapper_dd_19;
+  itab[0x1a]= instruction_wrapper_dd_1a;
+  itab[0x1b]= instruction_wrapper_dd_1b;
+  itab[0x1c]= instruction_wrapper_dd_1c;
+  itab[0x1d]= instruction_wrapper_dd_1d;
+  itab[0x1e]= instruction_wrapper_dd_1e;
+  itab[0x1f]= instruction_wrapper_dd_1f;
+
+  itab[0x21]= instruction_wrapper_dd_21;
+  itab[0x22]= instruction_wrapper_dd_22;
+  itab[0x23]= instruction_wrapper_dd_23;
+  itab[0x29]= instruction_wrapper_dd_29;
+  itab[0x2a]= instruction_wrapper_dd_2a;
+  itab[0x2b]= instruction_wrapper_dd_2b;
+  itab[0x2c]= instruction_wrapper_dd_2c;
+  itab[0x2d]= instruction_wrapper_dd_2d;
+  itab[0x2e]= instruction_wrapper_dd_2e;
+  itab[0x2f]= instruction_wrapper_dd_2f;
+
+  itab[0x34]= instruction_wrapper_dd_34;
+  itab[0x35]= instruction_wrapper_dd_35;
+  itab[0x36]= instruction_wrapper_dd_36;
+  itab[0x39]= instruction_wrapper_dd_39;
+  itab[0x3c]= instruction_wrapper_dd_3c;
+  itab[0x3d]= instruction_wrapper_dd_3d;
+  itab[0x3e]= instruction_wrapper_dd_3e;
+  itab[0x3f]= instruction_wrapper_dd_3f;
+
+  itab[0x46]= instruction_wrapper_dd_46;
+  itab[0x48]= instruction_wrapper_dd_48;
+  itab[0x49]= instruction_wrapper_dd_49;
+  itab[0x4b]= instruction_wrapper_dd_4b;
+  itab[0x4c]= instruction_wrapper_dd_4c;
+  itab[0x4d]= instruction_wrapper_dd_4d;
+  itab[0x4e]= instruction_wrapper_dd_4e;
+  itab[0x4f]= instruction_wrapper_dd_4f;
+
+  itab[0x56]= instruction_wrapper_dd_56;
+  itab[0x58]= instruction_wrapper_dd_58;
+  itab[0x59]= instruction_wrapper_dd_59;
+  itab[0x5b]= instruction_wrapper_dd_5b;
+  itab[0x5c]= instruction_wrapper_dd_5c;
+  itab[0x5e]= instruction_wrapper_dd_5e;
+  itab[0x5f]= instruction_wrapper_dd_5f;
+
+  itab[0x64]= instruction_wrapper_dd_64;
+  itab[0x65]= instruction_wrapper_dd_65;
+  itab[0x66]= instruction_wrapper_dd_66;
+  itab[0x68]= instruction_wrapper_dd_68;
+  itab[0x69]= instruction_wrapper_dd_69;
+  itab[0x6b]= instruction_wrapper_dd_6b;
+  itab[0x6c]= instruction_wrapper_dd_6c;
+  itab[0x6d]= instruction_wrapper_dd_6d;
+  itab[0x6e]= instruction_wrapper_dd_6e;
+  itab[0x6f]= instruction_wrapper_dd_6f;
+
+  itab[0x70]= instruction_wrapper_dd_70;
+  itab[0x71]= instruction_wrapper_dd_71;
+  itab[0x72]= instruction_wrapper_dd_72;
+  itab[0x73]= instruction_wrapper_dd_73;
+  itab[0x74]= instruction_wrapper_dd_74;
+  itab[0x75]= instruction_wrapper_dd_75;
+  itab[0x77]= instruction_wrapper_dd_77;
+  itab[0x78]= instruction_wrapper_dd_78;
+  itab[0x79]= instruction_wrapper_dd_79;
+  itab[0x7b]= instruction_wrapper_dd_7b;
+  itab[0x7c]= instruction_wrapper_dd_7c;
+  itab[0x7d]= instruction_wrapper_dd_7d;
+  itab[0x7e]= instruction_wrapper_dd_7e;
+  itab[0x7f]= instruction_wrapper_dd_7f;
+
+  itab[0x86]= instruction_wrapper_dd_86;
+  itab[0x88]= instruction_wrapper_dd_88;
+  itab[0x89]= instruction_wrapper_dd_89;
+  itab[0x8b]= instruction_wrapper_dd_8b;
+  itab[0x8c]= instruction_wrapper_dd_8c;
+  itab[0x8d]= instruction_wrapper_dd_8d;
+  itab[0x8e]= instruction_wrapper_dd_8e;
+  itab[0x8f]= instruction_wrapper_dd_8f;
+
+  itab[0x96]= instruction_wrapper_dd_96;
+  itab[0x98]= instruction_wrapper_dd_98;
+  itab[0x99]= instruction_wrapper_dd_99;
+  itab[0x9b]= instruction_wrapper_dd_9b;
+  itab[0x9c]= instruction_wrapper_dd_9c;
+  itab[0x9d]= instruction_wrapper_dd_9d;
+  itab[0x9e]= instruction_wrapper_dd_9e;
+  itab[0x9f]= instruction_wrapper_dd_9f;
+
+  itab[0xa6]= instruction_wrapper_dd_a6;
+  itab[0xa8]= instruction_wrapper_dd_a8;
+  itab[0xa9]= instruction_wrapper_dd_a9;
+  itab[0xab]= instruction_wrapper_dd_ab;
+  itab[0xac]= instruction_wrapper_dd_ac;
+  itab[0xad]= instruction_wrapper_dd_ad;
+  itab[0xae]= instruction_wrapper_dd_ae;
+  itab[0xaf]= instruction_wrapper_dd_af;
+
+  itab[0xb6]= instruction_wrapper_dd_b6;
+  itab[0xb8]= instruction_wrapper_dd_b8;
+  itab[0xb9]= instruction_wrapper_dd_b9;
+  itab[0xbb]= instruction_wrapper_dd_bb;
+  itab[0xbc]= instruction_wrapper_dd_bc;
+  itab[0xbd]= instruction_wrapper_dd_bd;
+  itab[0xbe]= instruction_wrapper_dd_be;
+  itab[0xbf]= instruction_wrapper_dd_bf;
+
+  itab[0xc4]= instruction_wrapper_dd_c4;
+  itab[0xcb]= instruction_wrapper_dd_cb;
+  itab[0xcc]= instruction_wrapper_dd_cc;
+  itab[0xcd]= instruction_wrapper_dd_cd;
+  itab[0xce]= instruction_wrapper_dd_ce;
+  itab[0xcf]= instruction_wrapper_dd_cf;
+
+  itab[0xd4]= instruction_wrapper_dd_d4;
+  itab[0xdc]= instruction_wrapper_dd_dc;
+  itab[0xdd]= instruction_wrapper_dd_dd;
+  itab[0xde]= instruction_wrapper_dd_de;
+  itab[0xdf]= instruction_wrapper_dd_df;
+
+  itab[0xe1]= instruction_wrapper_dd_e1;
+  itab[0xe3]= instruction_wrapper_dd_e3;
+  itab[0xe4]= instruction_wrapper_dd_e4;
+  itab[0xe5]= instruction_wrapper_dd_e5;
+  itab[0xe9]= instruction_wrapper_dd_e9;
+  itab[0xea]= instruction_wrapper_dd_ea;
+  itab[0xec]= instruction_wrapper_dd_ec;
+  itab[0xed]= instruction_wrapper_dd_ed;
+  itab[0xee]= instruction_wrapper_dd_ee;
+  itab[0xef]= instruction_wrapper_dd_ef;
+
+  itab[0xf1]= instruction_wrapper_dd_f1;
+  itab[0xf4]= instruction_wrapper_dd_f4;
+  itab[0xf5]= instruction_wrapper_dd_f5;
+  itab[0xf9]= instruction_wrapper_dd_f9;
+  itab[0xfc]= instruction_wrapper_dd_fc;
+  itab[0xfd]= instruction_wrapper_dd_fd;
+  itab[0xfe]= instruction_wrapper_dd_fe;
+  itab[0xff]= instruction_wrapper_dd_ff;
+}
+
+/* End of rxk.src/ddwrap.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/ddwrap.h sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/ddwrap.h
--- sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/ddwrap.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/ddwrap.h	2021-07-16 14:31:13.000000000 +0000
@@ -0,0 +1,37 @@
+/*
+ * Simulator of microcontrollers (ddwrap.h)
+ *
+ * Copyright (C) 2020,2021 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef DDWRAP_HEADER
+#define DDWRAP_HEADER
+
+#include "iwrap.h"
+
+extern void fill_dd_wrappers(instruction_wrapper_fn itab[]);
+
+#endif
+
+/* End of rxk.src/ddwrap.h */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/decode.h sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/decode.h
--- sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/decode.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/decode.h	2021-08-16 10:12:33.000000000 +0000
@@ -0,0 +1,193 @@
+/*
+ * Simulator of microcontrollers (decode.h)
+ *
+ * Copyright (C) 2020,2021 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef DECODE_HEADER
+#define DECODE_HEADER
+
+#define ALTD		instruction_76
+#define IOI		instruction_d3
+#define IOE		instruction_db
+
+#define NOP		instruction_00
+#define LD_BC_mn	instruction_01
+#define LD_DE_mn	instruction_11
+#define LD_HL_mn	instruction_21
+#define LD_SP_mn	instruction_31
+#define LD_imn_HL	instruction_22
+#define LD_HL_imn	instruction_2a
+#define INC_BC		instruction_03
+#define INC_DE		instruction_13
+#define INC_HL		instruction_23
+#define INC_SP		instruction_33
+#define INC_A		instruction_3c
+#define INC_B		instruction_04
+#define INC_C		instruction_0c
+#define INC_D		instruction_14
+#define INC_E		instruction_1c
+#define INC_H		instruction_24
+#define INC_L		instruction_2c
+#define DEC_BC		instruction_0b
+#define DEC_DE		instruction_1b
+#define DEC_HL		instruction_2b
+#define DEC_SP		instruction_3b
+#define DEC_A		instruction_3d
+#define DEC_B		instruction_05
+#define DEC_C		instruction_0d
+#define DEC_D		instruction_15
+#define DEC_E		instruction_1d
+#define DEC_H		instruction_25
+#define DEC_L		instruction_2d
+#define LD_A_n		instruction_3e
+#define LD_B_n		instruction_06
+#define LD_C_n		instruction_0e
+#define LD_D_n		instruction_16
+#define LD_E_n		instruction_1e
+#define LD_H_n		instruction_26
+#define LD_L_n		instruction_2e
+#define RLCA		instruction_07
+#define RLA		instruction_17
+#define RRCA		instruction_0f
+#define RRA		instruction_1f
+#define LD_iBC_A	instruction_02
+#define LD_iDE_A	instruction_12
+#define LD_iHL_A	instruction_77
+#define LD_iHL_B	instruction_70
+#define LD_iHL_C	instruction_71
+#define LD_iHL_D	instruction_72
+#define LD_iHL_E	instruction_73
+#define LD_iHL_H	instruction_74
+#define LD_iHL_L	instruction_75
+#define LD_iMN_A	instruction_32
+#define LD_A_iBC	instruction_0a
+#define LD_A_iDE	instruction_1a
+#define LD_A_iMN	instruction_3a
+#define LD_A_iHL	instruction_7e
+#define LD_B_iHL	instruction_46
+#define LD_C_iHL	instruction_4e
+#define LD_D_iHL	instruction_56
+#define LD_E_iHL	instruction_5e
+#define LD_H_iHL	instruction_66
+#define LD_L_iHL	instruction_6e
+#define SCF		instruction_37
+#define CPL		instruction_2f
+#define CCF		instruction_3f
+#define EX_AF_aAF	instruction_08
+#define ADD_HL_BC	instruction_09
+#define ADD_HL_DE	instruction_19
+#define ADD_HL_HL	instruction_29
+#define ADD_HL_SP	instruction_39
+#define DJNZ		instruction_10
+#define JR		instruction_18
+#define JR_NZ		instruction_20
+#define JR_Z		instruction_28
+#define JR_NC		instruction_30
+#define JR_C		instruction_38
+#define ADD_SP_d	instruction_27
+#define INC_iHL		instruction_34
+#define DEC_iHL		instruction_35
+#define LD_iHL_n	instruction_36
+#define LD_B_A		instruction_47
+#define LD_C_A		instruction_4f
+#define LD_D_A		instruction_57
+#define LD_E_E		instruction_5b
+#define LD_E_A		instruction_5f
+#define LD_L_A		instruction_6f
+#define LD_L_L		instruction_6d
+#define LD_H_A		instruction_67
+#define LD_A_B		instruction_78
+#define LD_A_C		instruction_79
+#define LD_A_D		instruction_7a
+#define LD_A_E		instruction_7b
+#define LD_A_H		instruction_7c
+#define LD_A_L		instruction_7d
+#define LD_A_A		instruction_7f
+#define XOR_A		instruction_af
+#define OR_A		instruction_b7
+#define RET_NZ		instruction_c0
+#define RET_Z		instruction_c8
+#define RET		instruction_c9
+#define RET_NC		instruction_d0
+#define RET_C		instruction_d8
+#define RET_LZ		instruction_e0
+#define RET_LO		instruction_e8
+#define RET_P		instruction_f0
+#define RET_M		instruction_f8
+#define POP_AF		instruction_f1
+#define POP_BC		instruction_c1
+#define POP_DE		instruction_d1
+#define POP_HL		instruction_e1
+#define JP_NZ_mn	instruction_c2
+#define JP_Z_mn		instruction_ca
+#define JP_NC_mn	instruction_d2
+#define JP_C_mn		instruction_da
+#define JP_LZ_mn	instruction_e2
+#define JP_LO_mn	instruction_ea
+#define JP_P_mn		instruction_f2
+#define JP_M_mn		instruction_fa
+#define JP_mn		instruction_c3
+#define LD_HL_iSPn	instruction_c4
+#define PUSH_AF		instruction_f5
+#define PUSH_BC		instruction_c5
+#define PUSH_DE		instruction_d5
+#define PUSH_HL		instruction_e5
+#define ADD_A_n		instruction_c6
+#define LJP		instruction_c7
+#define BOOL_HL		instruction_cc
+#define CALL_mn		instruction_cd
+#define ADC_A_n		instruction_ce
+#define LCALL_lmn	instruction_cf
+#define LD_iSPn_HL	instruction_d4
+#define SUB_A_n		instruction_d6
+#define RST_10		instruction_d7
+#define RST_18		instruction_df
+#define RST_20		instruction_e7
+#define RST_28		instruction_ef
+#define RST_38		instruction_ff
+#define EXX		instruction_d9
+#define AND_HL_DE	instruction_dc
+#define OR_HL_DE	instruction_ec
+#define SBC_A_n		instruction_de
+#define EX_aDE_HL	instruction_e3
+#define EX_DE_HL	instruction_eb
+#define LD_HL_iIXd	instruction_e4
+#define LD_iIXd_HL	instruction_f4
+#define AND_n		instruction_e6
+#define JP_HL		instruction_e9
+#define XOR_n		instruction_ee
+#define RL_DE		instruction_f3
+#define OR_n		instruction_f6
+#define MUL		instruction_f7
+#define LD_SP_HL	instruction_f9
+#define RR_DE		instruction_fb
+#define RR_HL		instruction_fc
+#define CP_n		instruction_fe
+
+#define PAGE_CB		instruction_cb
+
+#endif
+
+/* End of rxk.src/decode.h */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/dp0m3.h sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/dp0m3.h
--- sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/dp0m3.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/dp0m3.h	2021-07-16 14:31:13.000000000 +0000
@@ -0,0 +1,150 @@
+/*
+ * Simulator of microcontrollers (dp0m3.h)
+ *
+ * Copyright (C) 2020,2021 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef DP0M3_HEADER
+#define DP0M3_HEADER
+
+// opcodes valid in 3k mode only
+
+#define LD_B_B		instruction_40
+#define LD_B_C		instruction_41
+#define LD_B_E		instruction_43
+#define LD_B_H		instruction_44
+#define LD_C_C		instruction_49
+#define LD_C_D		instruction_4a
+#define LD_C_E		instruction_4b
+
+#define LD_D_D		instruction_52
+#define LD_D_E		instruction_53
+#define LD_E_B		instruction_58
+#define LD_E_C		instruction_59
+#define LD_E_D		instruction_5a
+#define LD_E_H		instruction_5c
+#define LD_E_L		instruction_5d
+
+#define LD_H_H		instruction_64
+#define LD_L_B		instruction_68
+#define LD_L_C		instruction_69
+#define LD_L_D		instruction_6a
+#define LD_L_E		instruction_6b
+#define LD_L_H		instruction_6c
+
+#define ADD_A_B		instruction_80
+#define ADC_A_B		instruction_88
+
+#define SUB_A_B		instruction_90
+
+
+// opcodes mean different insts in 3k/4k modes
+// meaning of 3k mode follows
+
+#define LD_B_D		instruction_42
+#define LD_B_L		instruction_45
+#define LD_C_B		instruction_48
+#define LD_C_H		instruction_4c
+#define LD_C_L		instruction_4d
+
+#define LD_D_B		instruction_50
+#define LD_D_C		instruction_51
+#define LD_D_H		instruction_54
+#define LD_D_L		instruction_55
+
+#define LD_H_B		instruction_60
+#define LD_H_C		instruction_61
+#define LD_H_D		instruction_62
+#define LD_H_E		instruction_63
+#define LD_H_L		instruction_65
+#define LD_L_L		instruction_6d
+
+#define LD_A_A		instruction_7f
+
+#define ADD_A_C		instruction_81
+#define ADD_A_D		instruction_82
+#define ADD_A_E		instruction_83
+#define ADD_A_H		instruction_84
+#define ADD_A_L		instruction_85
+#define ADD_A_iHL	instruction_86
+#define ADD_A_A		instruction_87
+#define ADC_A_C		instruction_89
+#define ADC_A_D		instruction_8a
+#define ADC_A_E		instruction_8b
+#define ADC_A_H		instruction_8c
+#define ADC_A_L		instruction_8d
+#define ADC_A_iHL	instruction_8e
+#define ADC_A_A		instruction_8f
+
+#define SUB_A_C		instruction_91
+#define SUB_A_D		instruction_92
+#define SUB_A_E		instruction_93
+#define SUB_A_H		instruction_94
+#define SUB_A_L		instruction_95
+#define SUB_A_iHL	instruction_96
+#define SUB_A_A		instruction_97
+#define SBC_A_B		instruction_98
+#define SBC_A_C		instruction_99
+#define SBC_A_D		instruction_9a
+#define SBC_A_E		instruction_9b
+#define SBC_A_H		instruction_9c
+#define SBC_A_L		instruction_9d
+#define SBC_A_iHL	instruction_9e
+#define SBC_A_A		instruction_9f
+
+#define AND_A_B		instruction_a0
+#define AND_A_C		instruction_a1
+#define AND_A_D		instruction_a2
+#define AND_A_E		instruction_a3
+#define AND_A_H		instruction_a4
+#define AND_A_L		instruction_a5
+#define AND_A_iHL	instruction_a6
+#define AND_A_A		instruction_a7
+#define XOR_A_B		instruction_a8
+#define XOR_A_C		instruction_a9
+#define XOR_A_D		instruction_aa
+#define XOR_A_E		instruction_ab
+#define XOR_A_H		instruction_ac
+#define XOR_A_L		instruction_ad
+#define XOR_A_iHL	instruction_ae
+
+#define OR_A_B		instruction_b0
+#define OR_A_C		instruction_b1
+#define OR_A_D		instruction_b2
+#define OR_A_E		instruction_b3
+#define OR_A_H		instruction_b4
+#define OR_A_L		instruction_b5
+#define OR_A_iHL	instruction_b6
+#define CP_A_B		instruction_b8
+#define CP_A_C		instruction_b9
+#define CP_A_D		instruction_ba
+#define CP_A_E		instruction_bb
+#define CP_A_H		instruction_bc
+#define CP_A_L		instruction_bd
+#define CP_A_iHL	instruction_be
+#define CP_A_A		instruction_bf
+
+#endif
+
+/* End of rxk.src/dp0m3.h */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/dp0m4.h sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/dp0m4.h
--- sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/dp0m4.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/dp0m4.h	2021-09-12 15:51:43.000000000 +0000
@@ -0,0 +1,115 @@
+/*
+ * Simulator of microcontrollers (dp0m4.h)
+ *
+ * Copyright (C) 2020,2021 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef DP0M4_HEADER
+#define DP0M4_HEADER
+
+// opcodes valid in 4k mode only
+
+// opcodes mean different insts in 3k/4k modes
+// meaning of 4k mode follows
+
+#define PAGE_4K6D	instruction_4k6d
+#define PAGE_4K7F	instruction_4k7f
+
+#define RL_HL		instruction_4k42
+#define RL_BC		instruction_4k62
+#define SUB_HL_JK	instruction_4k45
+#define SUB_HL_DE	instruction_4k55
+#define TEST_HL		instruction_4k4c
+#define CP_HL_D		instruction_4k48
+#define RLC_BC		instruction_4k60
+#define RLC_DE		instruction_4k50
+#define RRC_BC		instruction_4k61
+#define RRC_DE		instruction_4k51
+#define XOR_HL_DE	instruction_4k54
+#define RR_BC		instruction_4k63
+#define ADD_HL_JK	instruction_4k65
+
+#define LD_HL_BC	instruction_4k81
+#define LD_BC_HL	instruction_4k91
+#define LD_HL_DE	instruction_4ka1
+#define LD_iLMN_HL	instruction_4k82
+#define LD_HL_iLMN	instruction_4k92
+#define LD_iMN_BCDE	instruction_4k83
+#define LD_iMN_JKHL	instruction_4k84
+#define LD_BCDE_iMN	instruction_4k93
+#define LD_JKHL_iMN	instruction_4k94
+#define LD_HL_iPWd	instruction_4k85
+#define LD_HL_iPXd	instruction_4k95
+#define LD_HL_iPYd	instruction_4ka5
+#define LD_HL_iPZd	instruction_4kb5
+#define LD_iPWd_HL	instruction_4k86
+#define LD_iPXd_HL	instruction_4k96
+#define LD_iPYd_HL	instruction_4ka6
+#define LD_iPZd_HL	instruction_4kb6
+#define LLJP_lxpcmn	instruction_4k87
+#define LD_imn_JK	instruction_4k89
+#define LD_JK_imn	instruction_4k99
+#define LDF_ilmn_A	instruction_4k8a
+#define LDF_A_ilmn	instruction_4k9a
+#define LD_A_iPWHL	instruction_4k8b
+#define LD_A_iPXHL	instruction_4k9b
+#define LD_A_iPYHL	instruction_4kab
+#define LD_A_iPZHL	instruction_4kbb
+#define LD_iPWHL_A	instruction_4k8c
+#define LD_iPXHL_A	instruction_4k9c
+#define LD_iPYHL_A	instruction_4kac
+#define LD_iPZHL_A	instruction_4kbc
+#define LD_A_iPWd	instruction_4k8d
+#define LD_A_iPXd	instruction_4k9d
+#define LD_A_iPYd	instruction_4kad
+#define LD_A_iPZd	instruction_4kbd
+#define LD_iPWd_A	instruction_4k8e
+#define LD_iPXd_A	instruction_4k9e
+#define LD_iPYd_A	instruction_4kae
+#define LD_iPZd_A	instruction_4kbe
+#define LLCALL_lxpcmn	instruction_4k8f
+#define LD_LXPC_HL	instruction_4k97
+#define LD_HL_LXPC	instruction_4k9f
+#define JRE_ee		instruction_4k98
+#define JR_GT_e		instruction_4ka0
+#define JR_LT_e		instruction_4kb0
+#define JR_GTU_e	instruction_4ka8
+#define JR_V_e		instruction_4kb8
+#define JP_GT_mn	instruction_4ka2
+#define JP_LT_mn	instruction_4kb2
+#define JP_GTU_mn	instruction_4kaa
+#define JP_V_mn		instruction_4kba
+#define LD_BCDE_d	instruction_4ka3
+#define LD_JKHL_d	instruction_4ka4
+#define MULU		instruction_4ka7
+#define LD_JK_mn	instruction_4ka9
+#define LD_DE_HL	instruction_4kb1
+#define EX_BC_HL	instruction_4kb3
+#define EX_JKHL_BCDE	instruction_4kb4
+#define EX_JK_HL	instruction_4kb9
+#define CLR_HL		instruction_4kbf
+
+#endif
+
+/* End of rxk.src/dp0m4.h */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/dpddm3.h sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/dpddm3.h
--- sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/dpddm3.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/dpddm3.h	2021-08-24 15:43:48.000000000 +0000
@@ -0,0 +1,96 @@
+/*
+ * Simulator of microcontrollers (dpddm3.h)
+ *
+ * Copyright (C) 2020,2021 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef DPDDM3_HEADER
+#define DPDDM3_HEADER
+
+#define LD_IR_mn	instruction_dd_21
+
+#define ADD_IR_BC	instruction_dd_09
+#define ADD_IR_DE	instruction_dd_19
+#define ADD_IR_IR	instruction_dd_29
+#define ADD_IR_SP	instruction_dd_39
+#define INC_iIRd	instruction_dd_34
+#define DEC_iIRd	instruction_dd_35
+#define CP_A_iIRd	instruction_dd_be
+#define SBC_A_iIRd	instruction_dd_9e
+#define SUB_A_iIRd	instruction_dd_96
+#define ADD_A_iIRd	instruction_dd_86
+#define ADC_A_iIRd	instruction_dd_8e
+#define INC_IR		instruction_dd_23
+#define DEC_IR		instruction_dd_2b
+#define RR_IR		instruction_dd_fc
+
+#define XOR_A_iIRd	instruction_dd_ae
+#define AND_A_iIRd	instruction_dd_a6
+#define OR_A_iIRd	instruction_dd_b6
+#define BOOL_IR		instruction_dd_cc
+#define AND_IR_DE	instruction_dd_dc
+#define OR_IR_DE	instruction_dd_ec
+
+#define POP_IR		instruction_dd_e1
+#define PUSH_IR		instruction_dd_e5
+#define EX_iSP_IR	instruction_dd_e3
+
+#define LD_iIRd_A	instruction_dd_77
+#define LD_iIRd_B	instruction_dd_70
+#define LD_iIRd_C	instruction_dd_71
+#define LD_iIRd_D	instruction_dd_72
+#define LD_iIRd_E	instruction_dd_73
+#define LD_iIRd_H	instruction_dd_74
+#define LD_iIRd_L	instruction_dd_75
+#define LD_A_iIRd	instruction_dd_7e
+#define LD_B_iIRd	instruction_dd_46
+#define LD_C_iIRd	instruction_dd_4e
+#define LD_D_iIRd	instruction_dd_56
+#define LD_E_iIRd	instruction_dd_5e
+#define LD_H_iIRd	instruction_dd_66
+#define LD_L_iIRd	instruction_dd_6e
+
+#define LD_SP_IR	instruction_dd_f9
+#define LD_IR_iSPn 	instruction_dd_c4
+#define LD_iSPn_IR 	instruction_dd_d4
+#define LD_HL_iIRd	instruction_dd_e4
+#define LD_iIRd_n	instruction_dd_36
+#define LD_imn_IR	instruction_dd_22
+#define LD_IR_imn	instruction_dd_2a
+#define LD_HL_IR	instruction_dd_7c
+#define LD_IR_HL	instruction_dd_7d
+#define LD_iHLd_HL	instruction_dd_f4
+
+#define LDP_iIR_HL	instruction_dd_64
+#define LDP_imn_IR	instruction_dd_65
+#define LDP_HL_iIR	instruction_dd_6c
+#define LDP_IR_imn	instruction_dd_6d
+
+#define JP_IR		instruction_dd_e9
+
+#define PAGE_DD_CB	instruction_dd_cb
+
+#endif
+
+/* End of rxk.src/dpddm3.h */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/dpddm4.h sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/dpddm4.h
--- sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/dpddm4.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/dpddm4.h	2021-09-12 16:03:34.000000000 +0000
@@ -0,0 +1,114 @@
+/*
+ * Simulator of microcontrollers (dpddm4.h)
+ *
+ * Copyright (C) 2020,2021 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef DPDDM4_HEADER
+#define DPDDM4_HEADER
+
+#define LD_A_iIRA	instruction_dd_06
+#define TEST_IR		instruction_dd_4c
+#define LD_IRR_iHL	instruction_dd_1a
+#define LD_IRR_iIXd	instruction_dd_ce
+#define LD_IRR_iIYd	instruction_dd_de
+#define LD_IRR_iSPn	instruction_dd_ee
+#define LD_iHL_IRR	instruction_dd_1b
+#define LD_iIXd_IRR	instruction_dd_cf
+#define LD_iIYd_IRR	instruction_dd_df
+#define LD_iSPn_IRR	instruction_dd_ef
+#define NEG_IRR		instruction_dd_4d
+#define POP_IRR		instruction_dd_f1
+#define PUSH_IRR	instruction_dd_f5
+#define RL_1_IRR	instruction_dd_68
+#define RL_2_IRR	instruction_dd_69
+#define RL_4_IRR	instruction_dd_6b
+#define RLC_1_IRR	instruction_dd_48
+#define RLC_2_IRR	instruction_dd_49
+#define RLC_4_IRR	instruction_dd_4b
+#define RLC_8_IRR	instruction_dd_4f
+#define RLB_A_IRR	instruction_dd_6f
+#define SLA_1_IRR	instruction_dd_88
+#define SLA_2_IRR	instruction_dd_89
+#define SLA_4_IRR	instruction_dd_8b
+#define SLL_1_IRR	instruction_dd_a8
+#define SLL_2_IRR	instruction_dd_a9
+#define SLL_4_IRR	instruction_dd_ab
+#define TEST_IRR	instruction_dd_5c
+#define RR_1_IRR	instruction_dd_78
+#define RR_2_IRR	instruction_dd_79
+#define RR_4_IRR	instruction_dd_7b
+#define RRC_1_IRR	instruction_dd_58
+#define RRC_2_IRR	instruction_dd_59
+#define RRC_4_IRR	instruction_dd_5b
+#define RRC_8_IRR	instruction_dd_5f
+#define RRB_A_IRR	instruction_dd_7f
+#define SRA_1_IRR	instruction_dd_98
+#define SRA_2_IRR	instruction_dd_99
+#define SRA_4_IRR	instruction_dd_9b
+#define SRL_1_IRR	instruction_dd_b8
+#define SRL_2_IRR	instruction_dd_b9
+#define SRL_4_IRR	instruction_dd_bb
+
+#define LDF_IRR_iLMN	instruction_dd_0a
+#define LDF_iLMN_IRR	instruction_dd_0b
+#define LD_IRR_iPW_HL	instruction_dd_0c
+#define LD_IRR_iPX_HL	instruction_dd_1c
+#define LD_IRR_iPY_HL	instruction_dd_2c
+#define LD_IRR_iPZ_HL	instruction_dd_3c
+#define LD_iPW_HL_IRR	instruction_dd_0d
+#define LD_iPX_HL_IRR	instruction_dd_1d
+#define LD_iPY_HL_IRR	instruction_dd_2d
+#define LD_iPZ_HL_IRR	instruction_dd_3d
+#define LD_IRR_iPW_D	instruction_dd_0e
+#define LD_IRR_iPX_D	instruction_dd_1e
+#define LD_IRR_iPY_D	instruction_dd_2e
+#define LD_IRR_iPZ_D	instruction_dd_3e
+#define LD_iPW_D_IRR	instruction_dd_0f
+#define LD_iPX_D_IRR	instruction_dd_1f
+#define LD_iPY_D_IRR	instruction_dd_2f
+#define LD_iPZ_D_IRR	instruction_dd_3f
+#define LDL_PW_IR	instruction_dd_8c
+#define LDL_PX_IR	instruction_dd_9c
+#define LDL_PY_IR	instruction_dd_ac
+#define LDL_PZ_IR	instruction_dd_bc
+#define LD_PW_IRR	instruction_dd_8d
+#define LD_PX_IRR	instruction_dd_9d
+#define LD_PY_IRR	instruction_dd_ad
+#define LD_PZ_IRR	instruction_dd_bd
+#define LDL_PW_IRRL	instruction_dd_8f
+#define LDL_PX_IRRL	instruction_dd_9f
+#define LDL_PY_IRRL	instruction_dd_af
+#define LDL_PZ_IRRL	instruction_dd_bf
+#define LD_IRR_PW	instruction_dd_cd
+#define LD_IRR_PX	instruction_dd_dd
+#define LD_IRR_PY	instruction_dd_ed
+#define LD_IRR_PZ	instruction_dd_fd
+#define LD_iSP_HL_IRR	instruction_dd_ff
+#define CALL_iIR	instruction_dd_ea
+#define LD_IRR_iSP_HL	instruction_dd_fe
+
+#endif
+
+/* End of rxk.src/dpddm4.h */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/dpedm3a.h sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/dpedm3a.h
--- sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/dpedm3a.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/dpedm3a.h	2021-07-31 15:17:57.000000000 +0000
@@ -0,0 +1,48 @@
+/*
+ * Simulator of microcontrollers (dpedm3a.h)
+ *
+ * Copyright (C) 2020,2021 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef DPEDM3A_HEADER
+#define DPEDM3A_HEADER
+
+#define PUSH_SU		instruction_ed_66
+#define POP_SU		instruction_ed_6e
+#define SETUSR		instruction_ed_6f
+#define SURES		instruction_ed_7d
+#define RDMODE		instruction_ed_7f
+#define SYSCALL		instruction_ed_75
+#define LDDSR		instruction_ed_98
+#define LDISR		instruction_ed_90
+#define LSDDR		instruction_ed_d8
+#define LSIDR		instruction_ed_d0
+#define LSDR		instruction_ed_f8
+#define LSIR		instruction_ed_f0
+#define UMA		instruction_ed_c0
+#define UMS		instruction_ed_c8
+
+#endif
+
+/* End of rxk.src/dpedm3a.h */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/dpedm3.h sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/dpedm3.h
--- sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/dpedm3.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/dpedm3.h	2021-07-31 09:28:22.000000000 +0000
@@ -0,0 +1,82 @@
+/*
+ * Simulator of microcontrollers (dpedm3.h)
+ *
+ * Copyright (C) 2020,2021 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef DPEDM3_HEADER
+#define DPEDM3_HEADER
+
+#define LD_EIR_A	instruction_ed_47
+#define LD_IIR_A	instruction_ed_4f
+#define LD_A_EIR	instruction_ed_57
+#define LD_A_IIR	instruction_ed_5f
+#define LDI		instruction_ed_a0
+#define LDD		instruction_ed_a8
+#define LDDR		instruction_ed_b8
+#define LDIR		instruction_ed_b0
+#define EXX_iSP_HL	instruction_ed_54
+#define LD_BC_imn	instruction_ed_4b
+#define LD_DE_imn	instruction_ed_5b
+#define LD_HL_imn_ped	instruction_ed_6b
+#define LD_SP_imn	instruction_ed_7b
+#define LD_aBC_BC	instruction_ed_49
+#define LD_aDE_BC	instruction_ed_59
+#define LD_aHL_BC	instruction_ed_69
+#define LD_aBC_DE	instruction_ed_41
+#define LD_aDE_DE	instruction_ed_51
+#define LD_aHL_DE	instruction_ed_61
+#define LD_imn_BC	instruction_ed_43
+#define LD_imn_DE	instruction_ed_53
+#define LD_imn_HL_ed	instruction_ed_63
+#define LD_imn_SP	instruction_ed_73
+#define NEG		instruction_ed_44
+#define LRET		instruction_ed_45
+#define IPSET_0		instruction_ed_46
+#define IPSET_1		instruction_ed_56
+#define IPSET_2		instruction_ed_4e
+#define IPSET_3		instruction_ed_5e
+#define RETI		instruction_ed_4d
+#define IPRES		instruction_ed_5d
+#define LDP_iHL_HL	instruction_ed_64
+#define LDP_imn_HL	instruction_ed_65
+#define LDP_HL_iHL	instruction_ed_6c
+#define LDP_HL_imn	instruction_ed_6d
+#define LD_XPC_A	instruction_ed_67
+#define LD_A_XPC	instruction_ed_77
+#define PUSH_IP		instruction_ed_76
+#define POP_IP		instruction_ed_7e
+
+#define SBC_HL_BC	instruction_ed_42
+#define SBC_HL_DE	instruction_ed_52
+#define SBC_HL_HL	instruction_ed_62
+#define SBC_HL_SP	instruction_ed_72
+#define ADC_HL_BC	instruction_ed_4a
+#define ADC_HL_DE	instruction_ed_5a
+#define ADC_HL_HL	instruction_ed_6a
+#define ADC_HL_SP	instruction_ed_7a
+
+#endif
+
+/* End of rxk.src/dpedm3.h */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/dpedm4.h sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/dpedm4.h
--- sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/dpedm4.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/dpedm4.h	2021-09-13 16:16:27.000000000 +0000
@@ -0,0 +1,151 @@
+/*
+ * Simulator of microcontrollers (dpedm4.h)
+ *
+ * Copyright (C) 2020,2021 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef DPEDM4_HEADER
+#define DPEDM4_HEADER
+
+#define CBM_N		instruction_ed_00
+#define LD_PW_iHTR_HL	instruction_ed_01
+#define LD_PX_iHTR_HL	instruction_ed_11
+#define LD_PY_iHTR_HL	instruction_ed_21
+#define LD_PZ_iHTR_HL	instruction_ed_31
+#define SBOX_A		instruction_ed_02
+#define IBOX_A		instruction_ed_12
+#define DWJNZ		instruction_ed_10
+#define CP_HL_DE	instruction_ed_48
+#define TEST_BC		instruction_ed_4c
+#define LLJP_GT_LXPC_MN	instruction_ed_a2
+#define LLJP_GTU_LXPC_MN instruction_ed_aa
+#define LLJP_LT_LXPC_MN	instruction_ed_b2
+#define LLJP_V_LXPC_MN	instruction_ed_ba
+#define LLJP_NZ_LXPC_MN	instruction_ed_c2
+#define LLJP_Z_LXPC_MN	instruction_ed_ca
+#define LLJP_NC_LXPC_MN	instruction_ed_d2
+#define LLJP_C_LXPC_MN	instruction_ed_da
+#define PUSH_MN		instruction_ed_a5
+#define JRE_GT_EE	instruction_ed_a3
+#define JRE_LT_EE	instruction_ed_b3
+#define JRE_GTU_EE	instruction_ed_ab
+#define JRE_V_EE	instruction_ed_bb
+#define JRE_NZ_EE	instruction_ed_c3
+#define JRE_Z_EE	instruction_ed_cb
+#define JRE_NC_EE	instruction_ed_d3
+#define JRE_C_EE	instruction_ed_db
+#define FLAG_NZ_HL	instruction_ed_c4
+#define FLAG_Z_HL	instruction_ed_cc
+#define FLAG_NC_HL	instruction_ed_d4
+#define FLAG_C_HL	instruction_ed_dc
+#define FLAG_GT_HL	instruction_ed_a4
+#define FLAG_LT_HL	instruction_ed_b4
+#define FLAG_GTU_HL	instruction_ed_ac
+#define FLAG_V_HL	instruction_ed_bc
+#define CALL_iHL	instruction_ed_ea
+#define LLRET		instruction_ed_8b
+#define EXP		instruction_ed_d9
+#define LD_HTR_A	instruction_ed_40
+#define LD_A_HTR	instruction_ed_50
+#define FSYSCALL	instruction_ed_55
+#define SYSRET		instruction_ed_83
+#define SETUSRP		instruction_ed_b5
+#define SETSYSP		instruction_ed_b1
+#define LLCALL_iJKHL	instruction_ed_fa
+#define LDL_PW_iSPn	instruction_ed_03
+#define LDL_PX_iSPn	instruction_ed_13
+#define LDL_PY_iSPn	instruction_ed_23
+#define LDL_PZ_iSPn	instruction_ed_33
+#define LD_PW_iSPn	instruction_ed_04
+#define LD_PX_iSPn	instruction_ed_14
+#define LD_PY_iSPn	instruction_ed_24
+#define LD_PZ_iSPn	instruction_ed_34
+#define LD_iSPn_PW	instruction_ed_05
+#define LD_iSPn_PX	instruction_ed_15
+#define LD_iSPn_PY	instruction_ed_25
+#define LD_iSPn_PZ	instruction_ed_35
+#define LD_HL_iPWBC	instruction_ed_06
+#define LD_HL_iPXBC	instruction_ed_16
+#define LD_HL_iPYBC	instruction_ed_26
+#define LD_HL_iPZBC	instruction_ed_36
+#define LD_iPWBC_HL	instruction_ed_07
+#define LD_iPXBC_HL	instruction_ed_17
+#define LD_iPYBC_HL	instruction_ed_27
+#define LD_iPZBC_HL	instruction_ed_37
+#define LDF_PW_ilmn	instruction_ed_08
+#define LDF_PX_ilmn	instruction_ed_18
+#define LDF_PY_ilmn	instruction_ed_28
+#define LDF_PZ_ilmn	instruction_ed_38
+#define LDF_ilmn_PW	instruction_ed_09
+#define LDF_ilmn_PX	instruction_ed_19
+#define LDF_ilmn_PY	instruction_ed_29
+#define LDF_ilmn_PZ	instruction_ed_39
+#define LDF_BC_ilmn	instruction_ed_0a
+#define LDF_DE_ilmn	instruction_ed_1a
+#define LDF_IX_ilmn	instruction_ed_2a
+#define LDF_IY_ilmn	instruction_ed_3a
+#define LDF_ilmn_BC	instruction_ed_0b
+#define LDF_ilmn_DE	instruction_ed_1b
+#define LDF_ilmn_IX	instruction_ed_2b
+#define LDF_ilmn_IY	instruction_ed_3b
+#define LD_PW_klmn	instruction_ed_0c
+#define LD_PX_klmn	instruction_ed_1c
+#define LD_PY_klmn	instruction_ed_2c
+#define LD_PZ_klmn	instruction_ed_3c
+#define LDL_PW_mn	instruction_ed_0d
+#define LDL_PX_mn	instruction_ed_1d
+#define LDL_PY_mn	instruction_ed_2d
+#define LDL_PZ_mn	instruction_ed_3d
+#define CONVC_PW	instruction_ed_0e
+#define CONVC_PX	instruction_ed_1e
+#define CONVC_PY	instruction_ed_2e
+#define CONVC_PZ	instruction_ed_3e
+#define CONVD_PW	instruction_ed_0f
+#define CONVD_PX	instruction_ed_1f
+#define CONVD_PY	instruction_ed_2f
+#define CONVD_PZ	instruction_ed_3f
+#define CP_JKHL_BCDE	instruction_ed_58
+#define EX_aBC_HL	instruction_ed_74
+#define EX_aJK_HL	instruction_ed_7c
+#define COPY		instruction_ed_80
+#define COPYR		instruction_ed_88
+#define POP_PW		instruction_ed_c1
+#define POP_PX		instruction_ed_d1
+#define POP_PY		instruction_ed_e1
+#define POP_PZ		instruction_ed_f1
+#define PUSH_PW		instruction_ed_c5
+#define PUSH_PX		instruction_ed_d5
+#define PUSH_PY		instruction_ed_e5
+#define PUSH_PZ		instruction_ed_f5
+#define ADD_JKHL_BCDE	instruction_ed_c6
+#define SUB_JKHL_BCDE	instruction_ed_d6
+#define AND_JKHL_BCDE	instruction_ed_e6
+#define OR_JKHL_BCDE	instruction_ed_f6
+#define XOR_JKHL_BCDE	instruction_ed_ee
+#define LD_HL_iSPHL	instruction_ed_fe
+
+
+#endif
+
+/* End of rxk.src/dpedm4.h */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/ed_instructions.h sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/ed_instructions.h
--- sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/ed_instructions.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/ed_instructions.h	2021-08-16 10:12:33.000000000 +0000
@@ -0,0 +1,194 @@
+
+virtual int instruction_ed_00(t_mem code) { return resINV; }
+virtual int instruction_ed_01(t_mem code) { return resINV; }
+virtual int instruction_ed_02(t_mem code) { return resINV; }
+virtual int instruction_ed_03(t_mem code) { return resINV; }
+virtual int instruction_ed_04(t_mem code) { return resINV; }
+virtual int instruction_ed_05(t_mem code) { return resINV; }
+virtual int instruction_ed_06(t_mem code) { return resINV; }
+virtual int instruction_ed_07(t_mem code) { return resINV; }
+virtual int instruction_ed_08(t_mem code) { return resINV; }
+virtual int instruction_ed_09(t_mem code) { return resINV; }
+virtual int instruction_ed_0a(t_mem code) { return resINV; }
+virtual int instruction_ed_0b(t_mem code) { return resINV; }
+virtual int instruction_ed_0c(t_mem code) { return resINV; }
+virtual int instruction_ed_0d(t_mem code) { return resINV; }
+virtual int instruction_ed_0e(t_mem code) { return resINV; }
+virtual int instruction_ed_0f(t_mem code) { return resINV; }
+
+virtual int instruction_ed_10(t_mem code) { return resINV; }
+virtual int instruction_ed_11(t_mem code) { return resINV; }
+virtual int instruction_ed_12(t_mem code) { return resINV; }
+virtual int instruction_ed_13(t_mem code) { return resINV; }
+virtual int instruction_ed_14(t_mem code) { return resINV; }
+virtual int instruction_ed_15(t_mem code) { return resINV; }
+virtual int instruction_ed_16(t_mem code) { return resINV; }
+virtual int instruction_ed_17(t_mem code) { return resINV; }
+virtual int instruction_ed_18(t_mem code) { return resINV; }
+virtual int instruction_ed_19(t_mem code) { return resINV; }
+virtual int instruction_ed_1a(t_mem code) { return resINV; }
+virtual int instruction_ed_1b(t_mem code) { return resINV; }
+virtual int instruction_ed_1c(t_mem code) { return resINV; }
+virtual int instruction_ed_1d(t_mem code) { return resINV; }
+virtual int instruction_ed_1e(t_mem code) { return resINV; }
+virtual int instruction_ed_1f(t_mem code) { return resINV; }
+
+virtual int instruction_ed_21(t_mem code) { return resINV; }
+virtual int instruction_ed_23(t_mem code) { return resINV; }
+virtual int instruction_ed_24(t_mem code) { return resINV; }
+virtual int instruction_ed_25(t_mem code) { return resINV; }
+virtual int instruction_ed_26(t_mem code) { return resINV; }
+virtual int instruction_ed_27(t_mem code) { return resINV; }
+virtual int instruction_ed_28(t_mem code) { return resINV; }
+virtual int instruction_ed_29(t_mem code) { return resINV; }
+virtual int instruction_ed_2a(t_mem code) { return resINV; }
+virtual int instruction_ed_2b(t_mem code) { return resINV; }
+virtual int instruction_ed_2c(t_mem code) { return resINV; }
+virtual int instruction_ed_2d(t_mem code) { return resINV; }
+virtual int instruction_ed_2e(t_mem code) { return resINV; }
+virtual int instruction_ed_2f(t_mem code) { return resINV; }
+
+virtual int instruction_ed_31(t_mem code) { return resINV; }
+virtual int instruction_ed_33(t_mem code) { return resINV; }
+virtual int instruction_ed_34(t_mem code) { return resINV; }
+virtual int instruction_ed_35(t_mem code) { return resINV; }
+virtual int instruction_ed_36(t_mem code) { return resINV; }
+virtual int instruction_ed_37(t_mem code) { return resINV; }
+virtual int instruction_ed_38(t_mem code) { return resINV; }
+virtual int instruction_ed_39(t_mem code) { return resINV; }
+virtual int instruction_ed_3a(t_mem code) { return resINV; }
+virtual int instruction_ed_3b(t_mem code) { return resINV; }
+virtual int instruction_ed_3c(t_mem code) { return resINV; }
+virtual int instruction_ed_3d(t_mem code) { return resINV; }
+virtual int instruction_ed_3e(t_mem code) { return resINV; }
+virtual int instruction_ed_3f(t_mem code) { return resINV; }
+
+virtual int instruction_ed_40(t_mem code) { return resINV; }
+virtual int instruction_ed_41(t_mem code) { return resNOT_DONE; }
+virtual int instruction_ed_42(t_mem code) { return resNOT_DONE; }
+virtual int instruction_ed_43(t_mem code) { return resNOT_DONE; }
+virtual int instruction_ed_44(t_mem code) { return resNOT_DONE; }
+virtual int instruction_ed_45(t_mem code) { return resNOT_DONE; }
+virtual int instruction_ed_46(t_mem code) { return resNOT_DONE; }
+virtual int instruction_ed_47(t_mem code) { return resNOT_DONE; }
+virtual int instruction_ed_48(t_mem code) { return resNOT_DONE; }
+virtual int instruction_ed_49(t_mem code) { return resNOT_DONE; }
+virtual int instruction_ed_4a(t_mem code) { return resNOT_DONE; }
+virtual int instruction_ed_4b(t_mem code) { return resNOT_DONE; }
+virtual int instruction_ed_4c(t_mem code) { return resNOT_DONE; }
+virtual int instruction_ed_4d(t_mem code) { return resNOT_DONE; }
+virtual int instruction_ed_4e(t_mem code) { return resNOT_DONE; }
+virtual int instruction_ed_4f(t_mem code) { return resNOT_DONE; }
+
+virtual int instruction_ed_50(t_mem code) { return resINV; }
+virtual int instruction_ed_51(t_mem code) { return resNOT_DONE; }
+virtual int instruction_ed_52(t_mem code) { return resNOT_DONE; }
+virtual int instruction_ed_53(t_mem code) { return resNOT_DONE; }
+virtual int instruction_ed_54(t_mem code) { return resNOT_DONE; }
+virtual int instruction_ed_55(t_mem code) { return resINV; }
+virtual int instruction_ed_56(t_mem code) { return resNOT_DONE; }
+virtual int instruction_ed_57(t_mem code) { return resNOT_DONE; }
+virtual int instruction_ed_58(t_mem code) { return resINV; }
+virtual int instruction_ed_59(t_mem code) { return resNOT_DONE; }
+virtual int instruction_ed_5a(t_mem code) { return resNOT_DONE; }
+virtual int instruction_ed_5b(t_mem code) { return resNOT_DONE; }
+virtual int instruction_ed_5d(t_mem code) { return resNOT_DONE; }
+virtual int instruction_ed_5e(t_mem code) { return resNOT_DONE; }
+virtual int instruction_ed_5f(t_mem code) { return resNOT_DONE; }
+
+virtual int instruction_ed_61(t_mem code) { return resNOT_DONE; }
+virtual int instruction_ed_62(t_mem code) { return resNOT_DONE; }
+virtual int instruction_ed_63(t_mem code) { return resNOT_DONE; }
+virtual int instruction_ed_64(t_mem code) { return resNOT_DONE; }
+virtual int instruction_ed_65(t_mem code) { return resNOT_DONE; }
+virtual int instruction_ed_66(t_mem code) { return resINV; }
+virtual int instruction_ed_67(t_mem code) { return resNOT_DONE; }
+virtual int instruction_ed_69(t_mem code) { return resNOT_DONE; }
+virtual int instruction_ed_6a(t_mem code) { return resNOT_DONE; }
+virtual int instruction_ed_6b(t_mem code) { return resNOT_DONE; }
+virtual int instruction_ed_6c(t_mem code) { return resNOT_DONE; }
+virtual int instruction_ed_6d(t_mem code) { return resNOT_DONE; }
+virtual int instruction_ed_6e(t_mem code) { return resINV; }
+virtual int instruction_ed_6f(t_mem code) { return resINV; }
+
+virtual int instruction_ed_72(t_mem code) { return resNOT_DONE; }
+virtual int instruction_ed_73(t_mem code) { return resNOT_DONE; }
+virtual int instruction_ed_74(t_mem code) { return resINV; }
+virtual int instruction_ed_75(t_mem code) { return resINV; }
+virtual int instruction_ed_76(t_mem code) { return resNOT_DONE; }
+virtual int instruction_ed_77(t_mem code) { return resNOT_DONE; }
+virtual int instruction_ed_7a(t_mem code) { return resNOT_DONE; }
+virtual int instruction_ed_7b(t_mem code) { return resNOT_DONE; }
+virtual int instruction_ed_7c(t_mem code) { return resNOT_DONE; }
+virtual int instruction_ed_7d(t_mem code) { return resINV; }
+virtual int instruction_ed_7e(t_mem code) { return resNOT_DONE; }
+virtual int instruction_ed_7f(t_mem code) { return resINV; }
+
+virtual int instruction_ed_80(t_mem code) { return resINV; }
+virtual int instruction_ed_83(t_mem code) { return resINV; }
+virtual int instruction_ed_88(t_mem code) { return resINV; }
+virtual int instruction_ed_8b(t_mem code) { return resINV; }
+
+virtual int instruction_ed_90(t_mem code) { return resINV; }
+virtual int instruction_ed_98(t_mem code) { return resINV; }
+
+virtual int instruction_ed_a0(t_mem code) { return resINV; }
+virtual int instruction_ed_a2(t_mem code) { return resINV; }
+virtual int instruction_ed_a3(t_mem code) { return resINV; }
+virtual int instruction_ed_a4(t_mem code) { return resINV; }
+virtual int instruction_ed_a5(t_mem code) { return resINV; }
+virtual int instruction_ed_a8(t_mem code) { return resNOT_DONE; }
+virtual int instruction_ed_aa(t_mem code) { return resINV; }
+virtual int instruction_ed_ab(t_mem code) { return resINV; }
+virtual int instruction_ed_ac(t_mem code) { return resINV; }
+
+virtual int instruction_ed_b0(t_mem code) { return resNOT_DONE; }
+virtual int instruction_ed_b1(t_mem code) { return resINV; }
+virtual int instruction_ed_b2(t_mem code) { return resINV; }
+virtual int instruction_ed_b3(t_mem code) { return resINV; }
+virtual int instruction_ed_b4(t_mem code) { return resINV; }
+virtual int instruction_ed_b5(t_mem code) { return resINV; }
+virtual int instruction_ed_b8(t_mem code) { return resNOT_DONE; }
+virtual int instruction_ed_ba(t_mem code) { return resINV; }
+virtual int instruction_ed_bb(t_mem code) { return resINV; }
+virtual int instruction_ed_bc(t_mem code) { return resINV; }
+
+virtual int instruction_ed_c0(t_mem code) { return resINV; }
+virtual int instruction_ed_c1(t_mem code) { return resINV; }
+virtual int instruction_ed_c2(t_mem code) { return resINV; }
+virtual int instruction_ed_c3(t_mem code) { return resINV; }
+virtual int instruction_ed_c4(t_mem code) { return resINV; }
+virtual int instruction_ed_c5(t_mem code) { return resINV; }
+virtual int instruction_ed_c6(t_mem code) { return resINV; }
+virtual int instruction_ed_c8(t_mem code) { return resINV; }
+virtual int instruction_ed_ca(t_mem code) { return resINV; }
+virtual int instruction_ed_cb(t_mem code) { return resINV; }
+virtual int instruction_ed_cc(t_mem code) { return resINV; }
+
+virtual int instruction_ed_d0(t_mem code) { return resINV; }
+virtual int instruction_ed_d1(t_mem code) { return resINV; }
+virtual int instruction_ed_d2(t_mem code) { return resINV; }
+virtual int instruction_ed_d3(t_mem code) { return resINV; }
+virtual int instruction_ed_d4(t_mem code) { return resINV; }
+virtual int instruction_ed_d5(t_mem code) { return resINV; }
+virtual int instruction_ed_d6(t_mem code) { return resINV; }
+virtual int instruction_ed_d8(t_mem code) { return resINV; }
+virtual int instruction_ed_d9(t_mem code) { return resINV; }
+virtual int instruction_ed_da(t_mem code) { return resINV; }
+virtual int instruction_ed_db(t_mem code) { return resINV; }
+virtual int instruction_ed_dc(t_mem code) { return resINV; }
+
+virtual int instruction_ed_e1(t_mem code) { return resINV; }
+virtual int instruction_ed_e5(t_mem code) { return resINV; }
+virtual int instruction_ed_e6(t_mem code) { return resINV; }
+virtual int instruction_ed_ea(t_mem code) { return resINV; }
+virtual int instruction_ed_ee(t_mem code) { return resINV; }
+
+virtual int instruction_ed_f0(t_mem code) { return resINV; }
+virtual int instruction_ed_f1(t_mem code) { return resINV; }
+virtual int instruction_ed_f5(t_mem code) { return resINV; }
+virtual int instruction_ed_f6(t_mem code) { return resINV; }
+virtual int instruction_ed_f8(t_mem code) { return resINV; }
+virtual int instruction_ed_fa(t_mem code) { return resINV; }
+virtual int instruction_ed_fe(t_mem code) { return resINV; }
+
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/edwrap.cc sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/edwrap.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/edwrap.cc	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/edwrap.cc	2021-07-16 14:31:13.000000000 +0000
@@ -0,0 +1,430 @@
+/*
+ * Simulator of microcontrollers (edwrap.cc)
+ *
+ * Copyright (C) 2020,2021 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#include "rxkcl.h"
+
+#include "edwrap.h"
+
+int instruction_wrapper_ed_none(class cl_uc *uc, t_mem code) { return resINV_INST; }
+
+int instruction_wrapper_ed_00(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_00(code); }
+int instruction_wrapper_ed_01(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_01(code); }
+int instruction_wrapper_ed_02(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_02(code); }
+int instruction_wrapper_ed_03(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_03(code); }
+int instruction_wrapper_ed_04(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_04(code); }
+int instruction_wrapper_ed_05(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_05(code); }
+int instruction_wrapper_ed_06(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_06(code); }
+int instruction_wrapper_ed_07(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_07(code); }
+int instruction_wrapper_ed_08(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_08(code); }
+int instruction_wrapper_ed_09(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_09(code); }
+int instruction_wrapper_ed_0a(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_0a(code); }
+int instruction_wrapper_ed_0b(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_0b(code); }
+int instruction_wrapper_ed_0c(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_0c(code); }
+int instruction_wrapper_ed_0d(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_0d(code); }
+int instruction_wrapper_ed_0e(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_0e(code); }
+int instruction_wrapper_ed_0f(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_0f(code); }
+
+int instruction_wrapper_ed_10(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_10(code); }
+int instruction_wrapper_ed_11(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_11(code); }
+int instruction_wrapper_ed_12(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_12(code); }
+int instruction_wrapper_ed_13(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_13(code); }
+int instruction_wrapper_ed_14(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_14(code); }
+int instruction_wrapper_ed_15(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_15(code); }
+int instruction_wrapper_ed_16(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_16(code); }
+int instruction_wrapper_ed_17(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_17(code); }
+int instruction_wrapper_ed_18(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_18(code); }
+int instruction_wrapper_ed_19(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_19(code); }
+int instruction_wrapper_ed_1a(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_1a(code); }
+int instruction_wrapper_ed_1b(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_1b(code); }
+int instruction_wrapper_ed_1c(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_1c(code); }
+int instruction_wrapper_ed_1d(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_1d(code); }
+int instruction_wrapper_ed_1e(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_1e(code); }
+int instruction_wrapper_ed_1f(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_1f(code); }
+
+int instruction_wrapper_ed_21(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_21(code); }
+int instruction_wrapper_ed_23(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_23(code); }
+int instruction_wrapper_ed_24(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_24(code); }
+int instruction_wrapper_ed_25(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_25(code); }
+int instruction_wrapper_ed_26(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_26(code); }
+int instruction_wrapper_ed_27(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_27(code); }
+int instruction_wrapper_ed_28(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_28(code); }
+int instruction_wrapper_ed_29(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_29(code); }
+int instruction_wrapper_ed_2a(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_2a(code); }
+int instruction_wrapper_ed_2b(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_2b(code); }
+int instruction_wrapper_ed_2c(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_2c(code); }
+int instruction_wrapper_ed_2d(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_2d(code); }
+int instruction_wrapper_ed_2e(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_2e(code); }
+int instruction_wrapper_ed_2f(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_2f(code); }
+
+int instruction_wrapper_ed_31(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_31(code); }
+int instruction_wrapper_ed_33(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_33(code); }
+int instruction_wrapper_ed_34(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_34(code); }
+int instruction_wrapper_ed_35(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_35(code); }
+int instruction_wrapper_ed_36(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_36(code); }
+int instruction_wrapper_ed_37(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_37(code); }
+int instruction_wrapper_ed_38(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_38(code); }
+int instruction_wrapper_ed_39(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_39(code); }
+int instruction_wrapper_ed_3a(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_3a(code); }
+int instruction_wrapper_ed_3b(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_3b(code); }
+int instruction_wrapper_ed_3c(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_3c(code); }
+int instruction_wrapper_ed_3d(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_3d(code); }
+int instruction_wrapper_ed_3e(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_3e(code); }
+int instruction_wrapper_ed_3f(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_3f(code); }
+
+int instruction_wrapper_ed_40(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_40(code); }
+int instruction_wrapper_ed_41(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_41(code); }
+int instruction_wrapper_ed_42(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_42(code); }
+int instruction_wrapper_ed_43(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_43(code); }
+int instruction_wrapper_ed_44(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_44(code); }
+int instruction_wrapper_ed_45(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_45(code); }
+int instruction_wrapper_ed_46(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_46(code); }
+int instruction_wrapper_ed_47(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_47(code); }
+int instruction_wrapper_ed_48(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_48(code); }
+int instruction_wrapper_ed_49(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_49(code); }
+int instruction_wrapper_ed_4a(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_4a(code); }
+int instruction_wrapper_ed_4b(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_4b(code); }
+int instruction_wrapper_ed_4c(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_4c(code); }
+int instruction_wrapper_ed_4d(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_4d(code); }
+int instruction_wrapper_ed_4e(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_4e(code); }
+int instruction_wrapper_ed_4f(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_4f(code); }
+
+int instruction_wrapper_ed_50(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_50(code); }
+int instruction_wrapper_ed_51(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_51(code); }
+int instruction_wrapper_ed_52(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_52(code); }
+int instruction_wrapper_ed_53(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_53(code); }
+int instruction_wrapper_ed_54(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_54(code); }
+int instruction_wrapper_ed_55(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_55(code); }
+int instruction_wrapper_ed_56(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_56(code); }
+int instruction_wrapper_ed_57(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_57(code); }
+int instruction_wrapper_ed_58(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_58(code); }
+int instruction_wrapper_ed_59(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_59(code); }
+int instruction_wrapper_ed_5a(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_5a(code); }
+int instruction_wrapper_ed_5b(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_5b(code); }
+int instruction_wrapper_ed_5d(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_5d(code); }
+int instruction_wrapper_ed_5e(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_5e(code); }
+int instruction_wrapper_ed_5f(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_5f(code); }
+
+int instruction_wrapper_ed_61(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_61(code); }
+int instruction_wrapper_ed_62(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_62(code); }
+int instruction_wrapper_ed_63(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_63(code); }
+int instruction_wrapper_ed_64(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_64(code); }
+int instruction_wrapper_ed_65(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_65(code); }
+int instruction_wrapper_ed_66(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_66(code); }
+int instruction_wrapper_ed_67(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_67(code); }
+int instruction_wrapper_ed_69(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_69(code); }
+int instruction_wrapper_ed_6a(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_6a(code); }
+int instruction_wrapper_ed_6b(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_6b(code); }
+int instruction_wrapper_ed_6c(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_6c(code); }
+int instruction_wrapper_ed_6d(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_6d(code); }
+int instruction_wrapper_ed_6e(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_6e(code); }
+int instruction_wrapper_ed_6f(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_6f(code); }
+
+int instruction_wrapper_ed_72(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_72(code); }
+int instruction_wrapper_ed_73(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_73(code); }
+int instruction_wrapper_ed_74(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_74(code); }
+int instruction_wrapper_ed_75(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_75(code); }
+int instruction_wrapper_ed_76(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_76(code); }
+int instruction_wrapper_ed_77(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_77(code); }
+int instruction_wrapper_ed_7a(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_7a(code); }
+int instruction_wrapper_ed_7b(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_7b(code); }
+int instruction_wrapper_ed_7c(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_7c(code); }
+int instruction_wrapper_ed_7d(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_7d(code); }
+int instruction_wrapper_ed_7e(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_7e(code); }
+int instruction_wrapper_ed_7f(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_7f(code); }
+
+int instruction_wrapper_ed_80(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_80(code); }
+int instruction_wrapper_ed_83(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_83(code); }
+int instruction_wrapper_ed_88(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_88(code); }
+int instruction_wrapper_ed_8b(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_8b(code); }
+
+int instruction_wrapper_ed_90(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_90(code); }
+int instruction_wrapper_ed_98(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_98(code); }
+
+int instruction_wrapper_ed_a0(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_a0(code); }
+int instruction_wrapper_ed_a2(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_a2(code); }
+int instruction_wrapper_ed_a3(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_a3(code); }
+int instruction_wrapper_ed_a4(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_a4(code); }
+int instruction_wrapper_ed_a5(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_a5(code); }
+int instruction_wrapper_ed_a8(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_a8(code); }
+int instruction_wrapper_ed_aa(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_aa(code); }
+int instruction_wrapper_ed_ab(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_ab(code); }
+int instruction_wrapper_ed_ac(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_ac(code); }
+
+int instruction_wrapper_ed_b0(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_b0(code); }
+int instruction_wrapper_ed_b1(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_b1(code); }
+int instruction_wrapper_ed_b2(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_b2(code); }
+int instruction_wrapper_ed_b3(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_b3(code); }
+int instruction_wrapper_ed_b4(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_b4(code); }
+int instruction_wrapper_ed_b5(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_b5(code); }
+int instruction_wrapper_ed_b8(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_b8(code); }
+int instruction_wrapper_ed_ba(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_ba(code); }
+int instruction_wrapper_ed_bb(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_bb(code); }
+int instruction_wrapper_ed_bc(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_bc(code); }
+
+int instruction_wrapper_ed_c0(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_c0(code); }
+int instruction_wrapper_ed_c1(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_c1(code); }
+int instruction_wrapper_ed_c2(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_c2(code); }
+int instruction_wrapper_ed_c3(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_c3(code); }
+int instruction_wrapper_ed_c4(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_c4(code); }
+int instruction_wrapper_ed_c5(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_c5(code); }
+int instruction_wrapper_ed_c6(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_c6(code); }
+int instruction_wrapper_ed_c8(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_c8(code); }
+int instruction_wrapper_ed_ca(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_ca(code); }
+int instruction_wrapper_ed_cb(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_cb(code); }
+int instruction_wrapper_ed_cc(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_cc(code); }
+
+int instruction_wrapper_ed_d0(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_d0(code); }
+int instruction_wrapper_ed_d1(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_d1(code); }
+int instruction_wrapper_ed_d2(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_d2(code); }
+int instruction_wrapper_ed_d3(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_d3(code); }
+int instruction_wrapper_ed_d4(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_d4(code); }
+int instruction_wrapper_ed_d5(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_d5(code); }
+int instruction_wrapper_ed_d6(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_d6(code); }
+int instruction_wrapper_ed_d8(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_d8(code); }
+int instruction_wrapper_ed_d9(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_d9(code); }
+int instruction_wrapper_ed_da(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_da(code); }
+int instruction_wrapper_ed_db(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_db(code); }
+int instruction_wrapper_ed_dc(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_dc(code); }
+
+int instruction_wrapper_ed_e1(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_e1(code); }
+int instruction_wrapper_ed_e5(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_e5(code); }
+int instruction_wrapper_ed_e6(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_e6(code); }
+int instruction_wrapper_ed_ea(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_ea(code); }
+int instruction_wrapper_ed_ee(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_ee(code); }
+
+int instruction_wrapper_ed_f0(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_f0(code); }
+int instruction_wrapper_ed_f1(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_f1(code); }
+int instruction_wrapper_ed_f5(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_f5(code); }
+int instruction_wrapper_ed_f6(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_f6(code); }
+int instruction_wrapper_ed_f8(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_f8(code); }
+int instruction_wrapper_ed_fa(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_fa(code); }
+int instruction_wrapper_ed_fe(class cl_uc *uc, t_mem code) { return ((class cl_rxk *)uc)->instruction_ed_fe(code); }
+
+
+void fill_ed_wrappers(instruction_wrapper_fn itab[])
+{
+  int i;
+  for (i=0; i<256; i++)
+    {
+      itab[i]= instruction_wrapper_ed_none;
+    }
+
+  itab[0x00]= instruction_wrapper_ed_00;
+  itab[0x01]= instruction_wrapper_ed_01;
+  itab[0x02]= instruction_wrapper_ed_02;
+  itab[0x03]= instruction_wrapper_ed_03;
+  itab[0x04]= instruction_wrapper_ed_04;
+  itab[0x05]= instruction_wrapper_ed_05;
+  itab[0x06]= instruction_wrapper_ed_06;
+  itab[0x07]= instruction_wrapper_ed_07;
+  itab[0x08]= instruction_wrapper_ed_08;
+  itab[0x09]= instruction_wrapper_ed_09;
+  itab[0x0a]= instruction_wrapper_ed_0a;
+  itab[0x0b]= instruction_wrapper_ed_0b;
+  itab[0x0c]= instruction_wrapper_ed_0c;
+  itab[0x0d]= instruction_wrapper_ed_0d;
+  itab[0x0e]= instruction_wrapper_ed_0e;
+  itab[0x0f]= instruction_wrapper_ed_0f;
+
+  itab[0x10]= instruction_wrapper_ed_10;
+  itab[0x11]= instruction_wrapper_ed_11;
+  itab[0x12]= instruction_wrapper_ed_12;
+  itab[0x13]= instruction_wrapper_ed_13;
+  itab[0x14]= instruction_wrapper_ed_14;
+  itab[0x15]= instruction_wrapper_ed_15;
+  itab[0x16]= instruction_wrapper_ed_16;
+  itab[0x17]= instruction_wrapper_ed_17;
+  itab[0x18]= instruction_wrapper_ed_18;
+  itab[0x19]= instruction_wrapper_ed_19;
+  itab[0x1a]= instruction_wrapper_ed_1a;
+  itab[0x1b]= instruction_wrapper_ed_1b;
+  itab[0x1c]= instruction_wrapper_ed_1c;
+  itab[0x1d]= instruction_wrapper_ed_1d;
+  itab[0x1e]= instruction_wrapper_ed_1e;
+  itab[0x1f]= instruction_wrapper_ed_1f;
+
+  itab[0x21]= instruction_wrapper_ed_21;
+  itab[0x23]= instruction_wrapper_ed_23;
+  itab[0x24]= instruction_wrapper_ed_24;
+  itab[0x25]= instruction_wrapper_ed_25;
+  itab[0x26]= instruction_wrapper_ed_26;
+  itab[0x27]= instruction_wrapper_ed_27;
+  itab[0x28]= instruction_wrapper_ed_28;
+  itab[0x29]= instruction_wrapper_ed_29;
+  itab[0x2a]= instruction_wrapper_ed_2a;
+  itab[0x2b]= instruction_wrapper_ed_2b;
+  itab[0x2c]= instruction_wrapper_ed_2c;
+  itab[0x2d]= instruction_wrapper_ed_2d;
+  itab[0x2e]= instruction_wrapper_ed_2e;
+  itab[0x2f]= instruction_wrapper_ed_2f;
+
+  itab[0x31]= instruction_wrapper_ed_31;
+  itab[0x33]= instruction_wrapper_ed_33;
+  itab[0x34]= instruction_wrapper_ed_34;
+  itab[0x35]= instruction_wrapper_ed_35;
+  itab[0x36]= instruction_wrapper_ed_36;
+  itab[0x37]= instruction_wrapper_ed_37;
+  itab[0x38]= instruction_wrapper_ed_38;
+  itab[0x39]= instruction_wrapper_ed_39;
+  itab[0x3a]= instruction_wrapper_ed_3a;
+  itab[0x3b]= instruction_wrapper_ed_3b;
+  itab[0x3c]= instruction_wrapper_ed_3c;
+  itab[0x3d]= instruction_wrapper_ed_3d;
+  itab[0x3e]= instruction_wrapper_ed_3e;
+  itab[0x3f]= instruction_wrapper_ed_3f;
+
+  itab[0x40]= instruction_wrapper_ed_40;
+  itab[0x41]= instruction_wrapper_ed_41;
+  itab[0x42]= instruction_wrapper_ed_42;
+  itab[0x43]= instruction_wrapper_ed_43;
+  itab[0x44]= instruction_wrapper_ed_44;
+  itab[0x45]= instruction_wrapper_ed_45;
+  itab[0x46]= instruction_wrapper_ed_46;
+  itab[0x47]= instruction_wrapper_ed_47;
+  itab[0x48]= instruction_wrapper_ed_48;
+  itab[0x49]= instruction_wrapper_ed_49;
+  itab[0x4a]= instruction_wrapper_ed_4a;
+  itab[0x4b]= instruction_wrapper_ed_4b;
+  itab[0x4c]= instruction_wrapper_ed_4c;
+  itab[0x4d]= instruction_wrapper_ed_4d;
+  itab[0x4e]= instruction_wrapper_ed_4e;
+  itab[0x4f]= instruction_wrapper_ed_4f;
+
+  itab[0x50]= instruction_wrapper_ed_50;
+  itab[0x51]= instruction_wrapper_ed_51;
+  itab[0x52]= instruction_wrapper_ed_52;
+  itab[0x53]= instruction_wrapper_ed_53;
+  itab[0x54]= instruction_wrapper_ed_54;
+  itab[0x55]= instruction_wrapper_ed_55;
+  itab[0x56]= instruction_wrapper_ed_56;
+  itab[0x57]= instruction_wrapper_ed_57;
+  itab[0x58]= instruction_wrapper_ed_58;
+  itab[0x59]= instruction_wrapper_ed_59;
+  itab[0x5a]= instruction_wrapper_ed_5a;
+  itab[0x5b]= instruction_wrapper_ed_5b;
+  itab[0x5d]= instruction_wrapper_ed_5d;
+  itab[0x5e]= instruction_wrapper_ed_5e;
+  itab[0x5f]= instruction_wrapper_ed_5f;
+
+  itab[0x61]= instruction_wrapper_ed_61;
+  itab[0x62]= instruction_wrapper_ed_62;
+  itab[0x63]= instruction_wrapper_ed_63;
+  itab[0x64]= instruction_wrapper_ed_64;
+  itab[0x65]= instruction_wrapper_ed_65;
+  itab[0x66]= instruction_wrapper_ed_66;
+  itab[0x67]= instruction_wrapper_ed_67;
+  itab[0x69]= instruction_wrapper_ed_69;
+  itab[0x6a]= instruction_wrapper_ed_6a;
+  itab[0x6b]= instruction_wrapper_ed_6b;
+  itab[0x6c]= instruction_wrapper_ed_6c;
+  itab[0x6d]= instruction_wrapper_ed_6d;
+  itab[0x6e]= instruction_wrapper_ed_6e;
+  itab[0x6f]= instruction_wrapper_ed_6f;
+
+  itab[0x72]= instruction_wrapper_ed_72;
+  itab[0x73]= instruction_wrapper_ed_73;
+  itab[0x74]= instruction_wrapper_ed_74;
+  itab[0x75]= instruction_wrapper_ed_75;
+  itab[0x76]= instruction_wrapper_ed_76;
+  itab[0x77]= instruction_wrapper_ed_77;
+  itab[0x7a]= instruction_wrapper_ed_7a;
+  itab[0x7b]= instruction_wrapper_ed_7b;
+  itab[0x7c]= instruction_wrapper_ed_7c;
+  itab[0x7d]= instruction_wrapper_ed_7d;
+  itab[0x7e]= instruction_wrapper_ed_7e;
+  itab[0x7f]= instruction_wrapper_ed_7f;
+
+  itab[0x80]= instruction_wrapper_ed_80;
+  itab[0x83]= instruction_wrapper_ed_83;
+  itab[0x88]= instruction_wrapper_ed_88;
+  itab[0x8b]= instruction_wrapper_ed_8b;
+
+  itab[0x90]= instruction_wrapper_ed_90;
+  itab[0x98]= instruction_wrapper_ed_98;
+
+  itab[0xa0]= instruction_wrapper_ed_a0;
+  itab[0xa2]= instruction_wrapper_ed_a2;
+  itab[0xa3]= instruction_wrapper_ed_a3;
+  itab[0xa4]= instruction_wrapper_ed_a4;
+  itab[0xa5]= instruction_wrapper_ed_a5;
+  itab[0xa8]= instruction_wrapper_ed_a8;
+  itab[0xaa]= instruction_wrapper_ed_aa;
+  itab[0xab]= instruction_wrapper_ed_ab;
+  itab[0xac]= instruction_wrapper_ed_ac;
+
+  itab[0xb0]= instruction_wrapper_ed_b0;
+  itab[0xb1]= instruction_wrapper_ed_b1;
+  itab[0xb2]= instruction_wrapper_ed_b2;
+  itab[0xb3]= instruction_wrapper_ed_b3;
+  itab[0xb4]= instruction_wrapper_ed_b4;
+  itab[0xb5]= instruction_wrapper_ed_b5;
+  itab[0xb8]= instruction_wrapper_ed_b8;
+  itab[0xba]= instruction_wrapper_ed_ba;
+  itab[0xbb]= instruction_wrapper_ed_bb;
+  itab[0xbc]= instruction_wrapper_ed_bc;
+
+  itab[0xc0]= instruction_wrapper_ed_c0;
+  itab[0xc1]= instruction_wrapper_ed_c1;
+  itab[0xc2]= instruction_wrapper_ed_c2;
+  itab[0xc3]= instruction_wrapper_ed_c3;
+  itab[0xc4]= instruction_wrapper_ed_c4;
+  itab[0xc5]= instruction_wrapper_ed_c5;
+  itab[0xc6]= instruction_wrapper_ed_c6;
+  itab[0xc8]= instruction_wrapper_ed_c8;
+  itab[0xca]= instruction_wrapper_ed_ca;
+  itab[0xcb]= instruction_wrapper_ed_cb;
+  itab[0xcc]= instruction_wrapper_ed_cc;
+
+  itab[0xd0]= instruction_wrapper_ed_d0;
+  itab[0xd1]= instruction_wrapper_ed_d1;
+  itab[0xd2]= instruction_wrapper_ed_d2;
+  itab[0xd3]= instruction_wrapper_ed_d3;
+  itab[0xd4]= instruction_wrapper_ed_d4;
+  itab[0xd5]= instruction_wrapper_ed_d5;
+  itab[0xd6]= instruction_wrapper_ed_d6;
+  itab[0xd8]= instruction_wrapper_ed_d8;
+  itab[0xd9]= instruction_wrapper_ed_d9;
+  itab[0xda]= instruction_wrapper_ed_da;
+  itab[0xdb]= instruction_wrapper_ed_db;
+  itab[0xdc]= instruction_wrapper_ed_dc;
+
+  itab[0xe1]= instruction_wrapper_ed_e1;
+  itab[0xe5]= instruction_wrapper_ed_e5;
+  itab[0xe6]= instruction_wrapper_ed_e6;
+  itab[0xea]= instruction_wrapper_ed_ea;
+  itab[0xee]= instruction_wrapper_ed_ee;
+
+  itab[0xf0]= instruction_wrapper_ed_f0;
+  itab[0xf1]= instruction_wrapper_ed_f1;
+  itab[0xf5]= instruction_wrapper_ed_f5;
+  itab[0xf6]= instruction_wrapper_ed_f6;
+  itab[0xf8]= instruction_wrapper_ed_f8;
+  itab[0xfa]= instruction_wrapper_ed_fa;
+  itab[0xfe]= instruction_wrapper_ed_fe;
+}
+
+/* End of rxk.src/edwrap.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/edwrap.h sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/edwrap.h
--- sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/edwrap.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/edwrap.h	2021-07-16 14:31:13.000000000 +0000
@@ -0,0 +1,37 @@
+/*
+ * Simulator of microcontrollers (edwrap.h)
+ *
+ * Copyright (C) 2020,2021 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef EDWRAP_HEADER
+#define EDWRAP_HEADER
+
+#include "iwrap.h"
+
+extern void fill_ed_wrappers(instruction_wrapper_fn itab[]);
+
+#endif
+
+/* End of rxk.src/edwrap.h */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/fre714.txt sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/fre714.txt
--- sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/fre714.txt	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/fre714.txt	2021-10-03 12:24:27.000000000 +0000
@@ -0,0 +1,44 @@
+and iy, de		+ fd dc
+or iy, de		+ fd ec
+test iy			+ fd 4c
+
+cbm 			+ ed 00 n
+sbox a 			+ ed 02
+dwjnz label		+ ed 10 e
+ibox a	 		+ ed 12
+cp hl, de		+ ed 48
+test bc			+ ed 4c
+lljp cx, lxpc, mn	+ ed a2,aa,b2,ba n m
+jre cx, label		+ ed a3,b3,ab,bb n m
+push mn			+ ed a5 n m
+lljp cc, lxpc, mn	+ ed c2,ca,d2,da n m
+jre cc, label		+ ed c3,cb,d3,db n m
+flag cc, hl		+ ed c4,cc,d4,dc,a4,b4,ac,bc
+
+ld bcde, (hl)		+ dd 1a
+ld bcde, d(ix)		+ dd ce d
+ld bcde, d(iy)		+ dd de d
+ld bcde, n(sp)		+ dd ee n
+ld (hl), bcde		+ dd 1b
+ld d(ix), bcde		+ dd cf d
+ld d(iy), bcde		+ dd df d
+ld n(sp), bcde		+ dd ef n
+neg bcde       		+ dd 4d
+pop bcde		+ dd f1
+push bcde		+ dd f5
+
+rl bb, bcde		+ dd 68,69,6b
+rlc bb, bcde		+ dd 48,49,4b
+rlc 8, bcde		+ dd 4f
+rlb a, bcde		+ dd 6f
+sla bb, bcde		+ dd 88,89,8b
+sll bb, bcde		+ dd a8,a9,ab
+
+rr bb, bcde		+ dd 78,79,7b
+rrc bb, bcde		+ dd 58,59,5b
+rrc 8, bcde		+ dd 5f
+rrb a, bcde		+ dd 7f
+sra bb, bcde		+ dd 98,99,9b
+srl bb, bcde		+ dd b8,b9,bb
+
+test bcde		+ dd 5c
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/glob.cc sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/glob.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/glob.cc	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/glob.cc	2021-08-23 11:54:00.000000000 +0000
@@ -0,0 +1,243 @@
+/*
+ * Simulator of microcontrollers (glob.cc)
+ *
+ * Copyright (C) 2020,2021 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+//#include 
+
+#include "glob.h"
+
+
+instruction_wrapper_fn itab[256];
+instruction_wrapper_fn itab_dd[256];
+instruction_wrapper_fn itab_ed[256];
+instruction_wrapper_fn itab_fd[256];
+instruction_wrapper_fn itab_7f[256];
+
+u8_t sbox_tab[256];
+u8_t ibox_tab[256];
+
+/* 
+%d - signed compl.,byte jump 
+%w - 2-byte jump or imm. value
+%b - byte imm. value
+*/
+// code mask branch len mn call tick
+struct dis_entry disass_rxk[]=
+  {
+    { 0x76, 0xff, ' ', 1, "ALTD" },
+    { 0xd3, 0xff, ' ', 1, "IOI" },
+    { 0xdb, 0xff, ' ', 1, "IOE" },
+
+    { 0x00, 0xff, ' ', 1, "NOP" },
+    { 0x01, 0xff, ' ', 3, "LD BC,%w" },
+    { 0x11, 0xff, ' ', 3, "LD DE,%w" },
+    { 0x21, 0xff, ' ', 3, "LD HL,%w" },
+    { 0x31, 0xff, ' ', 3, "LD SP,%w" },
+    { 0x22, 0xff, ' ', 3, "LD (%w),HL" },
+    { 0x2a, 0xff, ' ', 3, "LD HL,(%w)" },
+    { 0x03, 0xff, ' ', 1, "INC BC" },
+    { 0x13, 0xff, ' ', 1, "INC DE" },
+    { 0x23, 0xff, ' ', 1, "INC HL" },
+    { 0x33, 0xff, ' ', 1, "INC SP" },
+    { 0x3c, 0xff, ' ', 1, "INC A" },
+    { 0x04, 0xff, ' ', 1, "INC B" },
+    { 0x0c, 0xff, ' ', 1, "INC C" },
+    { 0x14, 0xff, ' ', 1, "INC D" },
+    { 0x1c, 0xff, ' ', 1, "INC E" },
+    { 0x24, 0xff, ' ', 1, "INC H" },
+    { 0x2c, 0xff, ' ', 1, "INC L" },
+    { 0x0b, 0xff, ' ', 1, "DEC BC" },
+    { 0x1b, 0xff, ' ', 1, "DEC DE" },
+    { 0x2b, 0xff, ' ', 1, "DEC HL" },
+    { 0x3b, 0xff, ' ', 1, "DEC SP" },
+    { 0x3d, 0xff, ' ', 1, "DEC A" },
+    { 0x05, 0xff, ' ', 1, "DEC B" },
+    { 0x0d, 0xff, ' ', 1, "DEC C" },
+    { 0x15, 0xff, ' ', 1, "DEC D" },
+    { 0x1d, 0xff, ' ', 1, "DEC E" },
+    { 0x25, 0xff, ' ', 1, "DEC H" },
+    { 0x2d, 0xff, ' ', 1, "DEC L" },
+    { 0x3e, 0xff, ' ', 2, "LD A,%b" },
+    { 0x06, 0xff, ' ', 2, "LD B,%b" },
+    { 0x0e, 0xff, ' ', 2, "LD C,%b" },
+    { 0x16, 0xff, ' ', 2, "LD D,%b" },
+    { 0x1e, 0xff, ' ', 2, "LD E,%b" },
+    { 0x26, 0xff, ' ', 2, "LD H,%b" },
+    { 0x2e, 0xff, ' ', 2, "LD L,%b" },
+    { 0x07, 0xff, ' ', 1, "RLCA" },
+    { 0x17, 0xff, ' ', 1, "RLA" },
+    { 0x0f, 0xff, ' ', 1, "RRCA" },
+    { 0x1f, 0xff, ' ', 1, "RRA" },
+    { 0x02, 0xff, ' ', 1, "LD (BC),A" },
+    { 0x12, 0xff, ' ', 1, "LD (DE),A" },
+    { 0x77, 0xff, ' ', 1, "LD (HL),A" },
+    { 0x70, 0xff, ' ', 1, "LD (HL),B" },
+    { 0x71, 0xff, ' ', 1, "LD (HL),C" },
+    { 0x72, 0xff, ' ', 1, "LD (HL),D" },
+    { 0x73, 0xff, ' ', 1, "LD (HL),E" },
+    { 0x74, 0xff, ' ', 1, "LD (HL),H" },
+    { 0x75, 0xff, ' ', 1, "LD (HL),L" },
+    { 0x32, 0xff, ' ', 3, "LD (%w),A" },
+    { 0x0a, 0xff, ' ', 1, "LD A,(BC)" },
+    { 0x1a, 0xff, ' ', 1, "LD A,(DE)" },
+    { 0x3a, 0xff, ' ', 3, "LD A,(%w)" },
+    { 0x7e, 0xff, ' ', 1, "LD A,(HL)" },
+    { 0x46, 0xff, ' ', 1, "LD B,(HL)" },
+    { 0x4e, 0xff, ' ', 1, "LD C,(HL)" },
+    { 0x56, 0xff, ' ', 1, "LD D,(HL)" },
+    { 0x5e, 0xff, ' ', 1, "LD E,(HL)" },
+    { 0x66, 0xff, ' ', 1, "LD H,(HL)" },
+    { 0x6e, 0xff, ' ', 1, "LD L,(HL)" },
+    { 0x37, 0xff, ' ', 1, "SCF" },
+    { 0x2f, 0xff, ' ', 1, "CPL" },
+    { 0x3f, 0xff, ' ', 1, "CCF" },
+    { 0x08, 0xff, ' ', 1, "EX AF,AF'" }, // '
+    { 0x09, 0xff, ' ', 1, "ADD HL,BC" },
+    { 0x19, 0xff, ' ', 1, "ADD HL,DE" },
+    { 0x29, 0xff, ' ', 1, "ADD HL,HL" },
+    { 0x39, 0xff, ' ', 1, "ADD HL,SP" },
+    { 0x10, 0xff, ' ', 2, "DJNZ %r" },
+    { 0x18, 0xff, ' ', 2, "JR %r" },
+    { 0x20, 0xff, ' ', 2, "JR NZ,%r" },
+    { 0x28, 0xff, ' ', 2, "JR Z,%r" },
+    { 0x30, 0xff, ' ', 2, "JR NC,%r" },
+    { 0x38, 0xff, ' ', 2, "JR C,%r" },
+    { 0x27, 0xff, ' ', 2, "ADD SP,%b" },
+    { 0x34, 0xff, ' ', 1, "INC (HL)" },
+    { 0x35, 0xff, ' ', 1, "DEC (HL)" },
+    { 0x36, 0xff, ' ', 2, "LD (HL),%b" },
+    { 0x47, 0xff, ' ', 1, "LD B,A" },
+    { 0x4f, 0xff, ' ', 1, "LD C,A" },
+    { 0x57, 0xff, ' ', 1, "LD D,A" },
+    { 0x5b, 0xff, ' ', 1, "LD E,E" },
+    { 0x5f, 0xff, ' ', 1, "LD E,A" },
+    { 0x6f, 0xff, ' ', 1, "LD L,A" },
+    { 0x6d, 0xff, ' ', 1, "LD L,L" },
+    { 0x67, 0xff, ' ', 1, "LD H,A" },
+    { 0x78, 0xff, ' ', 1, "LD A,B" },
+    { 0x79, 0xff, ' ', 1, "LD A,C" },
+    { 0x7a, 0xff, ' ', 1, "LD A,D" },
+    { 0x7b, 0xff, ' ', 1, "LD A,E" },
+    { 0x7c, 0xff, ' ', 1, "LD A,H" },
+    { 0x7d, 0xff, ' ', 1, "LD A,L" },
+    { 0x7f, 0xff, ' ', 1, "LD A,A" },
+    { 0xaf, 0xff, ' ', 1, "XOR A" },
+    { 0xb7, 0xff, ' ', 1, "OR A" },
+    { 0xc0, 0xff, ' ', 1, "RET NZ" },
+    { 0xc8, 0xff, ' ', 1, "RET Z" },
+    { 0xc9, 0xff, ' ', 1, "RET" },
+    { 0xd0, 0xff, ' ', 1, "RET NC" },
+    { 0xd8, 0xff, ' ', 1, "RET C" },
+    { 0xe0, 0xff, ' ', 1, "RET LZ" },
+    { 0xe8, 0xff, ' ', 1, "RET LO" },
+    { 0xf0, 0xff, ' ', 1, "RET P" },
+    { 0xf8, 0xff, ' ', 1, "RET M" },
+    { 0xf1, 0xff, ' ', 1, "POP AF" },
+    { 0xc1, 0xff, ' ', 1, "POP BC" },
+    { 0xd1, 0xff, ' ', 1, "POP DE" },
+    { 0xe1, 0xff, ' ', 1, "POP HL" },
+    { 0xc2, 0xff, ' ', 3, "JP NZ,%w" },
+    { 0xca, 0xff, ' ', 3, "JP Z,%w" },
+    { 0xd2, 0xff, ' ', 3, "JP NC,%w" },
+    { 0xda, 0xff, ' ', 3, "JP C,%w" },
+    { 0xe2, 0xff, ' ', 3, "JP LZ,%w" },
+    { 0xea, 0xff, ' ', 3, "JP LO,%w" },
+    { 0xf2, 0xff, ' ', 3, "JP P,%w" },
+    { 0xfa, 0xff, ' ', 3, "JP M,%w" },
+    { 0xc3, 0xff, ' ', 3, "JP %w" },
+    { 0xc4, 0xff, ' ', 2, "LD HL,(SP+%b)" },
+    { 0xf5, 0xff, ' ', 1, "PUSH AF" },
+    { 0xc5, 0xff, ' ', 1, "PUSH BC" },
+    { 0xd5, 0xff, ' ', 1, "PUSH DE" },
+    { 0xe5, 0xff, ' ', 1, "PUSH HL" },
+    { 0xc6, 0xff, ' ', 2, "ADD A,%b" },
+    { 0xc7, 0xff, ' ', 4, "LJP %l" },
+    { 0xcc, 0xff, ' ', 1, "BOOL HL" },
+    { 0xcd, 0xff, ' ', 3, "CALL %w" },
+    { 0xce, 0xff, ' ', 2, "ADC A,%b" },
+    { 0xcf, 0xff, ' ', 4, "LCALL %l" },
+    { 0xd4, 0xff, ' ', 2, "LD (SP+%b),HL" },
+    { 0xd6, 0xff, ' ', 2, "SUB A,%b" },
+    { 0xd7, 0xff, ' ', 1, "RST 10" },
+    { 0xdf, 0xff, ' ', 1, "RST 18" },
+    { 0xe7, 0xff, ' ', 1, "RST 20" },
+    { 0xef, 0xff, ' ', 1, "RST 28" },
+    { 0xff, 0xff, ' ', 1, "RST 38" },
+    { 0xd9, 0xff, ' ', 1, "EXX" },
+    { 0xdc, 0xff, ' ', 1, "AND HL,DE" },
+    { 0xec, 0xff, ' ', 1, "OR HL,DE" },
+    { 0xde, 0xff, ' ', 2, "SBC A,%b" },
+    { 0xe3, 0xff, ' ', 1, "EX DE',HL" }, // '
+    { 0xeb, 0xff, ' ', 1, "EX DE,HL" },
+    { 0xe4, 0xff, ' ', 2, "LD HL,(IX%d)" },
+    { 0xf4, 0xff, ' ', 2, "LD (IX%d),HL" },
+    { 0xe6, 0xff, ' ', 2, "AND A,%b" },
+    { 0xe9, 0xff, ' ', 1, "JP HL" },
+    { 0xee, 0xff, ' ', 2, "XOR %b" },
+    { 0xf3, 0xff, ' ', 1, "RL DE" },
+    { 0xf6, 0xff, ' ', 2, "OR %b" },
+    { 0xf7, 0xff, ' ', 1, "MUL" },
+    { 0xf9, 0xff, ' ', 1, "LD SP,HL" },
+    { 0xfb, 0xff, ' ', 1, "RR DE" },
+    { 0xfc, 0xff, ' ', 1, "RR HL" },
+    { 0xfe, 0xff, ' ', 2, "CP A,%b" },
+    
+    { 0, 0, 0, 0, 0, 0, 0 }
+  };
+
+
+#define ROTL8(x,shift) ((/*uint8_t*/u8_t) ((x) << (shift)) | ((x) >> (8 - (shift))))
+
+void init_sbox()
+{
+  /*uint8_t*/u8_t p = 1, q = 1;
+	
+  /* loop invariant: p * q == 1 in the Galois field */
+  do
+    {
+      /* multiply p by 3 */
+      p = p ^ (p << 1) ^ (p & 0x80 ? 0x1B : 0);
+      
+      /* divide q by 3 (equals multiplication by 0xf6) */
+      q ^= q << 1;
+      q ^= q << 2;
+      q ^= q << 4;
+      q ^= q & 0x80 ? 0x09 : 0;
+      
+      /* compute the affine transformation */
+      /*uint8_t*/u8_t xformed = q ^ ROTL8(q, 1) ^ ROTL8(q, 2) ^ ROTL8(q, 3) ^ ROTL8(q, 4);
+      u8_t val= xformed ^ 0x63;
+      sbox_tab[p] = val;
+      ibox_tab[val]= p;
+    }
+  while (p != 1);
+  
+  /* 0 is a special case since it has no inverse */
+  sbox_tab[0] = 0x63;
+  ibox_tab[0x63]= 0;
+}
+
+/* End of rxk.src/glob.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/glob.h sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/glob.h
--- sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/glob.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/glob.h	2021-08-16 10:12:33.000000000 +0000
@@ -0,0 +1,51 @@
+/*
+ * Simulator of microcontrollers (glob.h)
+ *
+ * Copyright (C) 2020,2021 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef GLOB_HEADER
+#define GLOB_HEADER
+
+#include "stypes.h"
+#include "iwrap.h"
+
+
+extern instruction_wrapper_fn itab[256];
+extern instruction_wrapper_fn itab_dd[256];
+extern instruction_wrapper_fn itab_ed[256];
+extern instruction_wrapper_fn itab_fd[256];
+extern instruction_wrapper_fn itab_7f[256];
+
+extern u8_t sbox_tab[256];
+extern u8_t ibox_tab[256];
+
+extern struct dis_entry disass_rxk[];
+
+extern void init_sbox();
+
+
+#endif
+
+/* End of rxk.src/glob.h */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/gp0m3.cc sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/gp0m3.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/gp0m3.cc	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/gp0m3.cc	2021-08-23 11:54:00.000000000 +0000
@@ -0,0 +1,146 @@
+/*
+ * Simulator of microcontrollers (gp0m3.cc)
+ *
+ * Copyright (C) 2020,20 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#include "gp0m3.h"
+
+struct dis_entry disass_p0m3[]=
+  {
+    { 0x40, 0xff, ' ', 1, "LD B,B" },
+    { 0x41, 0xff, ' ', 1, "LD B,C" },
+    { 0x43, 0xff, ' ', 1, "LD B,E" },
+    { 0x44, 0xff, ' ', 1, "LD B,H" },
+    { 0x49, 0xff, ' ', 1, "LD C,C" },
+    { 0x4a, 0xff, ' ', 1, "LD C,D" },
+    { 0x4b, 0xff, ' ', 1, "LD C,E" },
+
+    { 0x52, 0xff, ' ', 1, "LD D,D" },
+    { 0x53, 0xff, ' ', 1, "LD D,E" },
+    { 0x58, 0xff, ' ', 1, "LD E,B" },
+    { 0x59, 0xff, ' ', 1, "LD E,C" },
+    { 0x5a, 0xff, ' ', 1, "LD E,D" },
+    { 0x5c, 0xff, ' ', 1, "LD E,H" },
+    { 0x5d, 0xff, ' ', 1, "LD E,L" },
+
+    { 0x64, 0xff, ' ', 1, "LD H,H" },
+    { 0x68, 0xff, ' ', 1, "LD L,B" },
+    { 0x69, 0xff, ' ', 1, "LD L,C" },
+    { 0x6a, 0xff, ' ', 1, "LD L,D" },
+    { 0x6b, 0xff, ' ', 1, "LD L,E" },
+    { 0x6c, 0xff, ' ', 1, "LD L,H" },
+
+    { 0x80, 0xff, ' ', 1, "ADD A,B" },
+    { 0x88, 0xff, ' ', 1, "ADC A,B" },
+
+    { 0x90, 0xff, ' ', 1, "SUB A,B" },
+
+    { 0x42, 0xff, ' ', 1, "LD B,D" },
+    { 0x45, 0xff, ' ', 1, "LD B,L" },
+    { 0x48, 0xff, ' ', 1, "LD C,B" },
+    { 0x4c, 0xff, ' ', 1, "LD C,H" },
+    { 0x4d, 0xff, ' ', 1, "LD C,L" },
+
+    { 0x50, 0xff, ' ', 1, "LD D,B" },
+    { 0x51, 0xff, ' ', 1, "LD D,C" },
+    { 0x54, 0xff, ' ', 1, "LD D,H" },
+    { 0x55, 0xff, ' ', 1, "LD D,L" },
+
+    { 0x60, 0xff, ' ', 1, "LD H,B" },
+    { 0x61, 0xff, ' ', 1, "LD H,C" },
+    { 0x62, 0xff, ' ', 1, "LD H,D" },
+    { 0x63, 0xff, ' ', 1, "LD H,E" },
+    { 0x65, 0xff, ' ', 1, "LD H,L" },
+    { 0x6d, 0xff, ' ', 1, "LD L,L" },
+
+    { 0x7f, 0xff, ' ', 1, "LD A,A" },
+
+    { 0x81, 0xff, ' ', 1, "ADD A,C" },
+    { 0x82, 0xff, ' ', 1, "ADD A,D" },
+    { 0x83, 0xff, ' ', 1, "ADD A,E" },
+    { 0x84, 0xff, ' ', 1, "ADD A,H" },
+    { 0x85, 0xff, ' ', 1, "ADD A,L" },
+    { 0x86, 0xff, ' ', 1, "ADD A,(HL)" },
+    { 0x87, 0xff, ' ', 1, "ADD A,A" },
+    { 0x89, 0xff, ' ', 1, "ADC A,C" },
+    { 0x8a, 0xff, ' ', 1, "ADC A,D" },
+    { 0x8b, 0xff, ' ', 1, "ADC A,E" },
+    { 0x8c, 0xff, ' ', 1, "ADC A,H" },
+    { 0x8d, 0xff, ' ', 1, "ADC A,L" },
+    { 0x8e, 0xff, ' ', 1, "ADC A,(HL)" },
+    { 0x8f, 0xff, ' ', 1, "ADC A,A" },
+    
+    { 0x91, 0xff, ' ', 1, "SUB A,C" },
+    { 0x92, 0xff, ' ', 1, "SUB A,D" },
+    { 0x93, 0xff, ' ', 1, "SUB A,E" },
+    { 0x94, 0xff, ' ', 1, "SUB A,H" },
+    { 0x95, 0xff, ' ', 1, "SUB A,L" },
+    { 0x96, 0xff, ' ', 1, "SUB A,(HL)" },
+    { 0x97, 0xff, ' ', 1, "SUB A,A" },
+    { 0x98, 0xff, ' ', 1, "SBC A,B" },
+    { 0x99, 0xff, ' ', 1, "SBC A,C" },
+    { 0x9a, 0xff, ' ', 1, "SBC A,D" },
+    { 0x9b, 0xff, ' ', 1, "SBC A,E" },
+    { 0x9c, 0xff, ' ', 1, "SBC A,H" },
+    { 0x9d, 0xff, ' ', 1, "SBC A,L" },
+    { 0x9e, 0xff, ' ', 1, "SBC A,(HL)" },
+    { 0x9f, 0xff, ' ', 1, "SBC A,A" },
+    
+    { 0xa0, 0xff, ' ', 1, "AND A,B" },
+    { 0xa1, 0xff, ' ', 1, "AND A,C" },
+    { 0xa2, 0xff, ' ', 1, "AND A,D" },
+    { 0xa3, 0xff, ' ', 1, "AND A,E" },
+    { 0xa4, 0xff, ' ', 1, "AND A,H" },
+    { 0xa5, 0xff, ' ', 1, "AND A,L" },
+    { 0xa6, 0xff, ' ', 1, "AND A,(HL)" },
+    { 0xa7, 0xff, ' ', 1, "AND A,A" },
+    { 0xa8, 0xff, ' ', 1, "XOR A,B" },
+    { 0xa9, 0xff, ' ', 1, "XOR A,C" },
+    { 0xaa, 0xff, ' ', 1, "XOR A,D" },
+    { 0xab, 0xff, ' ', 1, "XOR A,E" },
+    { 0xac, 0xff, ' ', 1, "XOR A,H" },
+    { 0xad, 0xff, ' ', 1, "XOR A,L" },
+    { 0xae, 0xff, ' ', 1, "XOR A,(HL)" },
+
+    { 0xb0, 0xff, ' ', 1, "OR A,B" },
+    { 0xb1, 0xff, ' ', 1, "OR A,C" },
+    { 0xb2, 0xff, ' ', 1, "OR A,D" },
+    { 0xb3, 0xff, ' ', 1, "OR A,E" },
+    { 0xb4, 0xff, ' ', 1, "OR A,H" },
+    { 0xb5, 0xff, ' ', 1, "OR A,L" },
+    { 0xb6, 0xff, ' ', 1, "OR A,(HL)" },
+    { 0xb8, 0xff, ' ', 1, "CP A,B" },
+    { 0xb9, 0xff, ' ', 1, "CP A,C" },
+    { 0xba, 0xff, ' ', 1, "CP A,D" },
+    { 0xbb, 0xff, ' ', 1, "CP A,E" },
+    { 0xbc, 0xff, ' ', 1, "CP A,H" },
+    { 0xbd, 0xff, ' ', 1, "CP A,L" },
+    { 0xbe, 0xff, ' ', 1, "CP A,(HL)" },
+    { 0xbf, 0xff, ' ', 1, "CP A,A" },
+
+    { 0, 0, 0, 0, 0, 0, 0 }
+  };
+  
+/* End of rxk.src/gp0m3.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/gp0m3.h sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/gp0m3.h
--- sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/gp0m3.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/gp0m3.h	2021-07-16 14:31:13.000000000 +0000
@@ -0,0 +1,39 @@
+/*
+ * Simulator of microcontrollers (gp0m3.h)
+ *
+ * Copyright (C) 2020,20 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef GP0M3_HEADER
+#define GP0M3_HEADER
+
+#include "stypes.h"
+
+
+extern struct dis_entry disass_p0m3[];
+
+
+#endif
+
+/* End of rxk.src/gp0m3.h */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/gp0m4.cc sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/gp0m4.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/gp0m4.cc	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/gp0m4.cc	2021-09-12 15:51:43.000000000 +0000
@@ -0,0 +1,108 @@
+/*
+ * Simulator of microcontrollers (gp0m4.cc)
+ *
+ * Copyright (C) 2020,20 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#include "gp0m4.h"
+
+struct dis_entry disass_p0m4[]=
+  {
+    { 0x42, 0xff, ' ', 1, "RL HL" },
+    { 0x62, 0xff, ' ', 1, "RL BC" },
+    { 0x45, 0xff, ' ', 1, "SUB HL,JK" },
+    { 0x55, 0xff, ' ', 1, "SUB HL,DE" },
+    { 0x4c, 0xff, ' ', 1, "TEST HL" },
+    { 0x48, 0xff, ' ', 2, "CP HL,%d" },
+    { 0x60, 0xff, ' ', 1, "RLC BC" },
+    { 0x50, 0xff, ' ', 1, "RLC DE" },
+    { 0x61, 0xff, ' ', 1, "RRC BC" },
+    { 0x51, 0xff, ' ', 1, "RRC DE" },
+    { 0x54, 0xff, ' ', 1, "XOR HL,DE" },
+    { 0x63, 0xff, ' ', 1, "RR BC" },
+    { 0x65, 0xff, ' ', 1, "ADD HL,JK" },
+    { 0x81, 0xff, ' ', 1, "LD HL,BC" },
+    { 0x91, 0xff, ' ', 1, "LD BC,HL" },
+    { 0xa1, 0xff, ' ', 1, "LD HL,DE" },
+    { 0x82, 0xff, ' ', 4, "LD (%l),HL" },
+    { 0x82, 0xff, ' ', 4, "LD HL,(%l)" },
+    { 0x83, 0xff, ' ', 3, "LD (%w),BCDE" },
+    { 0x84, 0xff, ' ', 3, "LD (%w),JKHL" },
+    { 0x93, 0xff, ' ', 3, "LD BCDE,(%w)" },
+    { 0x94, 0xff, ' ', 3, "LD JKHL,(%w)" },
+    { 0x85, 0xff, ' ', 2, "LD HL,(PW%d)" },
+    { 0x95, 0xff, ' ', 2, "LD HL,(PX%d)" },
+    { 0xa5, 0xff, ' ', 2, "LD HL,(PY%d)" },
+    { 0xb5, 0xff, ' ', 2, "LD HL,(PZ%d)" },
+    { 0x86, 0xff, ' ', 2, "LD (PW%d),HL" },
+    { 0x96, 0xff, ' ', 2, "LD (PX%d),HL" },
+    { 0xa6, 0xff, ' ', 2, "LD (PY%d),HL" },
+    { 0xb6, 0xff, ' ', 2, "LD (PZ%d),HL" },
+    { 0x87, 0xff, ' ', 5, "LLJP %w,%w" },
+    { 0x89, 0xff, ' ', 3, "LD (%w),JK" },
+    { 0x99, 0xff, ' ', 3, "LD JK,(%w)" },
+    { 0x8a, 0xff, ' ', 4, "LDF (%l),A" },
+    { 0x9a, 0xff, ' ', 4, "LDF A,(%l)" },
+    { 0x8b, 0xff, ' ', 1, "LD A,(PW+HL)" },
+    { 0x9b, 0xff, ' ', 1, "LD A,(PX+HL)" },
+    { 0xab, 0xff, ' ', 1, "LD A,(PY+HL)" },
+    { 0xbb, 0xff, ' ', 1, "LD A,(PZ+HL)" },
+    { 0x8c, 0xff, ' ', 1, "LD (PW+HL),A" },
+    { 0x9c, 0xff, ' ', 1, "LD (PX+HL),A" },
+    { 0xac, 0xff, ' ', 1, "LD (PY+HL),A" },
+    { 0xbc, 0xff, ' ', 1, "LD (PZ+HL),A" },
+    { 0x8d, 0xff, ' ', 1, "LD A,(PW%d)" },
+    { 0x9d, 0xff, ' ', 1, "LD A,(PX%d)" },
+    { 0xad, 0xff, ' ', 1, "LD A,(PY%d)" },
+    { 0xbd, 0xff, ' ', 1, "LD A,(PZ%d)" },
+    { 0x8d, 0xff, ' ', 1, "LD (PW%d),A" },
+    { 0x9d, 0xff, ' ', 1, "LD (PX%d),A" },
+    { 0xad, 0xff, ' ', 1, "LD (PY%d),A" },
+    { 0xbd, 0xff, ' ', 1, "LD (PZ%d),A" },
+    { 0x8f, 0xff, ' ', 5, "LLCALL %w,%w" },
+    { 0x97, 0xff, ' ', 1, "LD LXPC,HL" },
+    { 0x9f, 0xff, ' ', 1, "LD HL,LXPC" },
+    { 0x98, 0xff, ' ', 3, "JRE %R" },
+    { 0xa0, 0xff, ' ', 2, "JR GT,%r" },
+    { 0xb0, 0xff, ' ', 2, "JR LT,%r" },
+    { 0xa8, 0xff, ' ', 2, "JR GTU,%r" },
+    { 0xb8, 0xff, ' ', 2, "JR V,%r" },
+    { 0xa2, 0xff, ' ', 3, "JR GT,%w" },
+    { 0xb2, 0xff, ' ', 3, "JR LT,%w" },
+    { 0xaa, 0xff, ' ', 3, "JR GTU,%w" },
+    { 0xba, 0xff, ' ', 3, "JR V,%w" },
+    { 0xa3, 0xff, ' ', 2, "LD BCDE,%d" },
+    { 0xa4, 0xff, ' ', 2, "LD JKHL,%d" },
+    { 0xa7, 0xff, ' ', 1, "MULU" },
+    { 0xa9, 0xff, ' ', 3, "LD JK,%w" },
+    { 0xb1, 0xff, ' ', 1, "LD DE,HL" },
+    { 0xb3, 0xff, ' ', 1, "EX BC,HL" },
+    { 0xb4, 0xff, ' ', 1, "EX JKHL,BCDE" },
+    { 0xb9, 0xff, ' ', 1, "EX JK,HL" },
+    { 0xbf, 0xff, ' ', 1, "CLR HL" },
+    
+    { 0, 0, 0, 0, 0, 0, 0 }
+  };
+  
+/* End of rxk.src/gp0m4.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/gp0m4.h sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/gp0m4.h
--- sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/gp0m4.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/gp0m4.h	2021-08-16 10:12:33.000000000 +0000
@@ -0,0 +1,39 @@
+/*
+ * Simulator of microcontrollers (gp0m4.h)
+ *
+ * Copyright (C) 2020,20 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef GP0M4_HEADER
+#define GP0M4_HEADER
+
+#include "stypes.h"
+
+
+extern struct dis_entry disass_p0m4[];
+
+
+#endif
+
+/* End of rxk.src/gp0m4.h */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/gpddm3.cc sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/gpddm3.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/gpddm3.cc	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/gpddm3.cc	2021-08-24 15:43:48.000000000 +0000
@@ -0,0 +1,97 @@
+/*
+ * Simulator of microcontrollers (gpddm3.cc)
+ *
+ * Copyright (C) 2020,20 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#include "gpddm3.h"
+
+struct dis_entry disass_pddm3[]=
+  {
+    { 0x21, 0xff, ' ', 4, "LD %I,%w" },
+    
+    { 0x09, 0xff, ' ', 2, "ADD %I,BC" },
+    { 0x19, 0xff, ' ', 2, "ADD %I,DE" },
+    { 0x29, 0xff, ' ', 2, "ADD %I,%I" },
+    { 0x39, 0xff, ' ', 2, "ADD %I,SP" },
+    { 0x34, 0xff, ' ', 3, "INC (%I%d)" },
+    { 0x35, 0xff, ' ', 3, "DEC (%I%d)" },
+    { 0xbe, 0xff, ' ', 3, "CP (%I%d)" },
+    { 0x9e, 0xff, ' ', 3, "SBC A,(%I%d)" },
+    { 0x96, 0xff, ' ', 3, "SUB A,(%I%d)" },
+    { 0x86, 0xff, ' ', 3, "ADD A,(%I%d)" },
+    { 0x8e, 0xff, ' ', 3, "ADC A,(%I%d)" },
+    { 0x23, 0xff, ' ', 2, "INC %I" },
+    { 0x2b, 0xff, ' ', 2, "DEC %I" },
+    { 0xfc, 0xff, ' ', 2, "RR %I" },
+
+    { 0xae, 0xff, ' ', 3, "XOR A,(%I%d)" },
+    { 0xa6, 0xff, ' ', 3, "AND A,(%I%d)" },
+    { 0xb6, 0xff, ' ', 3, "OR A,(%I%d)" },
+    { 0xcc, 0xff, ' ', 2, "BOOL %I" },
+    { 0xdc, 0xff, ' ', 2, "AND %I,DE" },
+    { 0xec, 0xff, ' ', 2, "OR %I,DE" },
+
+    { 0xe1, 0xff, ' ', 2, "POP %I" },
+    { 0xe5, 0xff, ' ', 2, "PUSH %I" },
+    { 0xe3, 0xff, ' ', 2, "EX (SP),%I" },
+
+    { 0x77, 0xff, ' ', 3, "LD (%I%d),A" },
+    { 0x70, 0xff, ' ', 3, "LD (%I%d),B" },
+    { 0x71, 0xff, ' ', 3, "LD (%I%d),C" },
+    { 0x72, 0xff, ' ', 3, "LD (%I%d),D" },
+    { 0x73, 0xff, ' ', 3, "LD (%I%d),E" },
+    { 0x74, 0xff, ' ', 3, "LD (%I%d),H" },
+    { 0x75, 0xff, ' ', 3, "LD (%I%d),L" },
+    { 0x7e, 0xff, ' ', 3, "LD A,(%I%d)" },
+    { 0x46, 0xff, ' ', 3, "LD B,(%I%d)" },
+    { 0x4e, 0xff, ' ', 3, "LD C,(%I%d)" },
+    { 0x56, 0xff, ' ', 3, "LD D,(%I%d)" },
+    { 0x5e, 0xff, ' ', 3, "LD E,(%I%d)" },
+    { 0x66, 0xff, ' ', 3, "LD H,(%I%d)" },
+    { 0x6e, 0xff, ' ', 3, "LD L,(%I%d)" },
+
+    { 0xf9, 0xff, ' ', 2, "LD SP,%I" },
+    { 0xc4, 0xff, ' ', 3, "LD %I,(SP+%b)" },
+    { 0xd4, 0xff, ' ', 3, "LD (SP+%b),%I" },
+    { 0xe4, 0xff, ' ', 3, "LD HL,(%J%d)" },
+    { 0x36, 0xff, ' ', 4, "LD (%I%d),%b" },
+    { 0x06, 0xff, ' ', 2, "LD A,(%I+A)" },
+    { 0x22, 0xff, ' ', 4, "LD (%w),%I" },
+    { 0x2a, 0xff, ' ', 4, "LD %I,(%w)" },
+    { 0x7c, 0xff, ' ', 2, "LD HL,%I" },
+    { 0x7d, 0xff, ' ', 2, "LD %I,HL" },
+    { 0xf4, 0xff, ' ', 3, "LD (HL%d),HL" },
+    
+    { 0x64, 0xff, ' ', 2, "LDP (%I),HL" },
+    { 0x64, 0xff, ' ', 4, "LDP (%w),%I" },
+    { 0x6c, 0xff, ' ', 2, "LDP HL,(%I)" },
+    { 0x6d, 0xff, ' ', 2, "LDP %I,(%w)" },
+
+    { 0xe9, 0xff, ' ', 2, "JP (%I)" },
+
+    { 0, 0, 0, 0, 0, 0, 0 }
+  };
+  
+/* End of rxk.src/gpddm3.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/gpddm3.h sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/gpddm3.h
--- sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/gpddm3.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/gpddm3.h	2021-07-16 14:31:13.000000000 +0000
@@ -0,0 +1,39 @@
+/*
+ * Simulator of microcontrollers (gpddm3.h)
+ *
+ * Copyright (C) 2020,20 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef GPDDM3_HEADER
+#define GPDDM3_HEADER
+
+#include "stypes.h"
+
+
+extern struct dis_entry disass_pddm3[];
+
+
+#endif
+
+/* End of rxk.src/gpddm3.h */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/gpddm4.cc sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/gpddm4.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/gpddm4.cc	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/gpddm4.cc	2021-09-12 16:03:34.000000000 +0000
@@ -0,0 +1,116 @@
+/*
+ * Simulator of microcontrollers (gpddm4.cc)
+ *
+ * Copyright (C) 2020,20 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#include "gpddm4.h"
+
+struct dis_entry disass_pddm4[]=
+  {
+    { 0x06, 0xff, ' ', 2, "LD A,(%I+A)" },
+    { 0x4c, 0xff, ' ', 2, "TEST %I" },
+    { 0x1a, 0xff, ' ', 2, "LD %3,(HL)" },
+    { 0xce, 0xff, ' ', 3, "LD %3,(IX%d)" },
+    { 0xde, 0xff, ' ', 3, "LD %3,(IY%d)" },
+    { 0xee, 0xff, ' ', 3, "LD %3,(SP+%b)" },
+    { 0x1b, 0xff, ' ', 2, "LD (HL),%3" },
+    { 0xcf, 0xff, ' ', 3, "LD (IX%d),%3" },
+    { 0xdf, 0xff, ' ', 3, "LD (IY%d),%3" },
+    { 0xef, 0xff, ' ', 3, "LD (SP+%b),%3" },
+    { 0x4d, 0xff, ' ', 2, "NEG %3" },
+    { 0xf1, 0xff, ' ', 2, "POP %3" },
+    { 0xf5, 0xff, ' ', 2, "PUSH %3" },
+    { 0x68, 0xff, ' ', 2, "RL 1,%3" },
+    { 0x69, 0xff, ' ', 2, "RL 2,%3" },
+    { 0x6b, 0xff, ' ', 2, "RL 4,%3" },
+    { 0x48, 0xff, ' ', 2, "RLC 1,%3" },
+    { 0x49, 0xff, ' ', 2, "RLC 2,%3" },
+    { 0x4b, 0xff, ' ', 2, "RLC 4,%3" },
+    { 0x4f, 0xff, ' ', 2, "RLC 8,%3" },
+    { 0x6f, 0xff, ' ', 2, "RLB A,%3" },
+    { 0x88, 0xff, ' ', 2, "SLA 1,%3" },
+    { 0x89, 0xff, ' ', 2, "SLA 2,%3" },
+    { 0x8b, 0xff, ' ', 2, "SLA 4,%3" },
+    { 0xa8, 0xff, ' ', 2, "SLL 1,%3" },
+    { 0xa9, 0xff, ' ', 2, "SLL 2,%3" },
+    { 0xab, 0xff, ' ', 2, "SLL 4,%3" },
+    { 0x5c, 0xff, ' ', 2, "TEST %3" },
+    { 0x78, 0xff, ' ', 2, "RR 1,%3" },
+    { 0x79, 0xff, ' ', 2, "RR 2,%3" },
+    { 0x7b, 0xff, ' ', 2, "RR 4,%3" },
+    { 0x58, 0xff, ' ', 2, "RRC 1,%3" },
+    { 0x59, 0xff, ' ', 2, "RRC 2,%3" },
+    { 0x5b, 0xff, ' ', 2, "RRC 4,%3" },
+    { 0x5f, 0xff, ' ', 2, "RRC 8,%3" },
+    { 0x7f, 0xff, ' ', 2, "RRB A,%3" },
+    { 0x98, 0xff, ' ', 2, "SRA 1,%3" },
+    { 0x99, 0xff, ' ', 2, "SRA 2,%3" },
+    { 0x9b, 0xff, ' ', 2, "SRA 4,%3" },
+    { 0xb8, 0xff, ' ', 2, "SRL 1,%3" },
+    { 0xb9, 0xff, ' ', 2, "SRL 2,%3" },
+    { 0xbb, 0xff, ' ', 2, "SRL 4,%3" },
+    
+    { 0x0a, 0xff, ' ', 5, "LDF %3,(%l)" },
+    { 0x0b, 0xff, ' ', 5, "LDF (%l),%3" },
+    { 0x0c, 0xff, ' ', 2, "LD %3,(PW+HL)" },
+    { 0x1c, 0xff, ' ', 2, "LD %3,(PX+HL)" },
+    { 0x2c, 0xff, ' ', 2, "LD %3,(PY+HL)" },
+    { 0x3c, 0xff, ' ', 2, "LD %3,(PZ+HL)" },
+    { 0x0d, 0xff, ' ', 2, "LD (PW+HL),%3" },
+    { 0x1d, 0xff, ' ', 2, "LD (PX+HL),%3" },
+    { 0x2d, 0xff, ' ', 2, "LD (PY+HL),%3" },
+    { 0x3d, 0xff, ' ', 2, "LD (PZ+HL),%3" },
+    { 0x0e, 0xff, ' ', 2, "LD %3,(PW%d)" },
+    { 0x1e, 0xff, ' ', 2, "LD %3,(PX%d)" },
+    { 0x2e, 0xff, ' ', 2, "LD %3,(PY%d)" },
+    { 0x3e, 0xff, ' ', 2, "LD %3,(PZ%d)" },
+    { 0x0f, 0xff, ' ', 2, "LD (PW%d),%3" },
+    { 0x1f, 0xff, ' ', 2, "LD (PX%d),%3" },
+    { 0x2f, 0xff, ' ', 2, "LD (PY%d),%3" },
+    { 0x3f, 0xff, ' ', 2, "LD (PZ%d),%3" },
+    { 0x8c, 0xff, ' ', 2, "LDL PW,%I" },
+    { 0x9c, 0xff, ' ', 2, "LDL PX,%I" },
+    { 0xac, 0xff, ' ', 2, "LDL PY,%I" },
+    { 0xbc, 0xff, ' ', 2, "LDL PZ,%I" },
+    { 0x8d, 0xff, ' ', 2, "LD PW,%3" },
+    { 0x9d, 0xff, ' ', 2, "LD PX,%3" },
+    { 0xad, 0xff, ' ', 2, "LD PY,%3" },
+    { 0xbd, 0xff, ' ', 2, "LD PZ,%3" },
+    { 0x8f, 0xff, ' ', 2, "LDL PW,%n" },
+    { 0x9f, 0xff, ' ', 2, "LDL PX,%n" },
+    { 0xaf, 0xff, ' ', 2, "LDL PY,%n" },
+    { 0xbf, 0xff, ' ', 2, "LDL PZ,%n" },
+    { 0xcd, 0xff, ' ', 2, "LD %3,PW" },
+    { 0xdd, 0xff, ' ', 2, "LD %3,PX" },
+    { 0xed, 0xff, ' ', 2, "LD %3,PY" },
+    { 0xfd, 0xff, ' ', 2, "LD %3,PZ" },
+    { 0xff, 0xff, ' ', 2, "LD (SP+HL),%3" },
+    { 0xea, 0xff, ' ', 2, "CALL (%I)" },
+    { 0xfe, 0xff, ' ', 2, "LD %3,(SP+HL)" },
+
+    { 0, 0, 0, 0, 0, 0, 0 }
+  };
+  
+/* End of rxk.src/gpddm4.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/gpddm4.h sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/gpddm4.h
--- sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/gpddm4.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/gpddm4.h	2021-07-31 09:28:22.000000000 +0000
@@ -0,0 +1,39 @@
+/*
+ * Simulator of microcontrollers (gpddm4.h)
+ *
+ * Copyright (C) 2020,20 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef GPDDM4_HEADER
+#define GPDDM4_HEADER
+
+#include "stypes.h"
+
+
+extern struct dis_entry disass_pddm4[];
+
+
+#endif
+
+/* End of rxk.src/gpddm4.h */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/gpedm3a.cc sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/gpedm3a.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/gpedm3a.cc	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/gpedm3a.cc	2021-08-23 11:54:00.000000000 +0000
@@ -0,0 +1,50 @@
+/*
+ * Simulator of microcontrollers (gpedm3a.cc)
+ *
+ * Copyright (C) 2020,20 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#include "gpedm3a.h"
+
+struct dis_entry disass_pedm3a[]=
+  {
+    { 0x66, 0xff, ' ', 2, "PUSH SU" },
+    { 0x6e, 0xff, ' ', 2, "POP SU" },
+    { 0x6f, 0xff, ' ', 2, "SETUSR" },
+    { 0x7d, 0xff, ' ', 2, "SURES" },
+    { 0x7f, 0xff, ' ', 2, "RDMODE" },
+    { 0x75, 0xff, ' ', 2, "SYSCALL" },
+    { 0x98, 0xff, ' ', 2, "LDDSR" },
+    { 0x90, 0xff, ' ', 2, "LDISR" },
+    { 0xd8, 0xff, ' ', 2, "LSDDR" },
+    { 0xd0, 0xff, ' ', 2, "LSIDR" },
+    { 0xf8, 0xff, ' ', 2, "LSDR" },
+    { 0xf0, 0xff, ' ', 2, "LSIR" },
+    { 0xc0, 0xff, ' ', 2, "UMA" },
+    { 0xc8, 0xff, ' ', 2, "UMS" },
+
+    { 0, 0, 0, 0, 0, 0, 0 }
+  };
+  
+/* End of rxk.src/gpedm3a.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/gpedm3a.h sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/gpedm3a.h
--- sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/gpedm3a.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/gpedm3a.h	2021-07-31 09:28:22.000000000 +0000
@@ -0,0 +1,39 @@
+/*
+ * Simulator of microcontrollers (gpedm3a.h)
+ *
+ * Copyright (C) 2020,20 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef GPEDM3A_HEADER
+#define GPEDM3A_HEADER
+
+#include "stypes.h"
+
+
+extern struct dis_entry disass_pedm3a[];
+
+
+#endif
+
+/* End of rxk.src/gpedm3a.h */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/gpedm3.cc sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/gpedm3.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/gpedm3.cc	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/gpedm3.cc	2021-08-23 11:54:00.000000000 +0000
@@ -0,0 +1,84 @@
+/*
+ * Simulator of microcontrollers (gpedm3.cc)
+ *
+ * Copyright (C) 2020,20 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#include "gpedm3.h"
+
+struct dis_entry disass_pedm3[]=
+  {
+    { 0x47, 0xff, ' ', 2, "LD EIR,A" },
+    { 0x4f, 0xff, ' ', 2, "LD IIR,A" },
+    { 0x57, 0xff, ' ', 2, "LD A,EIR" },
+    { 0x5f, 0xff, ' ', 2, "LD A,IIR" },
+    { 0xa0, 0xff, ' ', 2, "LDI" },
+    { 0xa8, 0xff, ' ', 2, "LDD" },
+    { 0xb8, 0xff, ' ', 2, "LDDR" },
+    { 0xb0, 0xff, ' ', 2, "LDIR" },
+    { 0x54, 0xff, ' ', 2, "EXX (SP),HL" },
+    { 0x4b, 0xff, ' ', 4, "LD BC,(%w)" },
+    { 0x5b, 0xff, ' ', 4, "LD DE,(%w)" },
+    { 0x6b, 0xff, ' ', 4, "LD HL,(%w)" },
+    { 0x7b, 0xff, ' ', 4, "LD SP,(%w)" },
+    { 0x49, 0xff, ' ', 2, "LD BC',BC" }, // '
+    { 0x59, 0xff, ' ', 2, "LD DE',BC" }, // '
+    { 0x69, 0xff, ' ', 2, "LD HL',BC" }, // '
+    { 0x41, 0xff, ' ', 2, "LD BC',DE" }, // '
+    { 0x51, 0xff, ' ', 2, "LD DE',DE" }, // '
+    { 0x61, 0xff, ' ', 2, "LD HL',DE" }, // '
+    { 0x43, 0xff, ' ', 4, "LD (%w),BC" },
+    { 0x53, 0xff, ' ', 4, "LD (%w),DE" },
+    { 0x63, 0xff, ' ', 4, "LD (%w),HL" },
+    { 0x73, 0xff, ' ', 4, "LD (%w),SP" },
+    { 0x44, 0xff, ' ', 2, "NEG" },
+    { 0x45, 0xff, ' ', 2, "LRET" },
+    { 0x46, 0xff, ' ', 2, "IPSET 0" },
+    { 0x56, 0xff, ' ', 2, "IPSET 1" },
+    { 0x4e, 0xff, ' ', 2, "IPSET 2" },
+    { 0x5e, 0xff, ' ', 2, "IPSET 3" },
+    { 0x4d, 0xff, ' ', 2, "RETI" },
+    { 0x5d, 0xff, ' ', 2, "IPRES" },
+    { 0x64, 0xff, ' ', 2, "LDP (HL),HL" },
+    { 0x65, 0xff, ' ', 4, "LDP (%w),HL" },
+    { 0x6c, 0xff, ' ', 2, "LDP HL,(HL)" },
+    { 0x6d, 0xff, ' ', 4, "LDP HL,(%w)" },
+    { 0x67, 0xff, ' ', 2, "LD XPC,A" },
+    { 0x77, 0xff, ' ', 2, "LD A,XPC" },
+    { 0x76, 0xff, ' ', 2, "PUSH IP" },
+    { 0x7e, 0xff, ' ', 2, "POP IP" },
+    
+    { 0x42, 0xff, ' ', 2, "SBC HL,BC" },
+    { 0x52, 0xff, ' ', 2, "SBC HL,DE" },
+    { 0x62, 0xff, ' ', 2, "SBC HL,HL" },
+    { 0x72, 0xff, ' ', 2, "SBC HL,SP" },
+    { 0x4a, 0xff, ' ', 2, "ADC HL,BC" },
+    { 0x5a, 0xff, ' ', 2, "ADC HL,DE" },
+    { 0x6a, 0xff, ' ', 2, "ADC HL,HL" },
+    { 0x7a, 0xff, ' ', 2, "ADC HL,SP" },
+
+    { 0, 0, 0, 0, 0, 0, 0 }
+  };
+  
+/* End of rxk.src/gpedm3.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/gpedm3.h sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/gpedm3.h
--- sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/gpedm3.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/gpedm3.h	2021-07-16 14:31:13.000000000 +0000
@@ -0,0 +1,39 @@
+/*
+ * Simulator of microcontrollers (gpedm3.h)
+ *
+ * Copyright (C) 2020,20 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef GPEDM3_HEADER
+#define GPEDM3_HEADER
+
+#include "stypes.h"
+
+
+extern struct dis_entry disass_pedm3[];
+
+
+#endif
+
+/* End of rxk.src/gpedm3.h */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/gpedm4.cc sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/gpedm4.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/gpedm4.cc	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/gpedm4.cc	2021-09-13 16:16:27.000000000 +0000
@@ -0,0 +1,152 @@
+/*
+ * Simulator of microcontrollers (gpedm4.cc)
+ *
+ * Copyright (C) 2020,20 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#include "gpedm4.h"
+
+struct dis_entry disass_pedm4[]=
+  {
+    { 0x00, 0xff, ' ', 3, "CBM %b" },
+    { 0x01, 0xff, ' ', 2, "LD PW,(HTR+HL)" },
+    { 0x11, 0xff, ' ', 2, "LD PX,(HTR+HL)" },
+    { 0x21, 0xff, ' ', 2, "LD PY,(HTR+HL)" },
+    { 0x31, 0xff, ' ', 2, "LD PZ,(HTR+HL)" },
+    { 0x02, 0xff, ' ', 2, "SBOX A" },
+    { 0x12, 0xff, ' ', 2, "IBOX A" },
+    { 0x10, 0xff, ' ', 3, "DWJNZ %r" },
+    { 0x48, 0xff, ' ', 2, "CP HL,DE" },
+    { 0x4c, 0xff, ' ', 2, "TEST BC" },
+    { 0xa2, 0xff, ' ', 6, "LLJP GT,%X,%w" },
+    { 0xaa, 0xff, ' ', 6, "LLJP GTU,%X,%w" },
+    { 0xb2, 0xff, ' ', 6, "LLJP LT,%X,%w" },
+    { 0xba, 0xff, ' ', 6, "LLJP V,%X,%w" },
+    { 0xc2, 0xff, ' ', 6, "LLJP NZ,%X,%w" },
+    { 0xca, 0xff, ' ', 6, "LLJP Z,%X,%w" },
+    { 0xd2, 0xff, ' ', 6, "LLJP NC,%X,%w" },
+    { 0xda, 0xff, ' ', 6, "LLJP C,%X,%w" },
+    { 0xa5, 0xff, ' ', 4, "PUSH %w" },
+    { 0xa3, 0xff, ' ', 4, "JRE GT,%R" },
+    { 0xb3, 0xff, ' ', 4, "JRE LT,%R" },
+    { 0xab, 0xff, ' ', 4, "JRE GTU,%R" },
+    { 0xbb, 0xff, ' ', 4, "JRE V,%R" },
+    { 0xc3, 0xff, ' ', 4, "JRE NZ,%R" },
+    { 0xcb, 0xff, ' ', 4, "JRE Z,%R" },
+    { 0xd3, 0xff, ' ', 4, "JRE NC,%R" },
+    { 0xdb, 0xff, ' ', 4, "JRE C,%R" },
+    { 0xc4, 0xff, ' ', 2, "FLAG NZ,HL" },
+    { 0xcc, 0xff, ' ', 2, "FLAG Z,HL" },
+    { 0xd4, 0xff, ' ', 2, "FLAG NC,HL" },
+    { 0xdc, 0xff, ' ', 2, "FLAG C,HL" },
+    { 0xa4, 0xff, ' ', 2, "FLAG GT,HL" },
+    { 0xb4, 0xff, ' ', 2, "FLAG LT,HL" },
+    { 0xac, 0xff, ' ', 2, "FLAG GTU,HL" },
+    { 0xbc, 0xff, ' ', 2, "FLAG V,HL" },
+    { 0xea, 0xff, ' ', 2, "CALL (HL)" },
+    { 0x8b, 0xff, ' ', 2, "LLRET" },
+    { 0xd9, 0xff, ' ', 2, "EXP" },
+    { 0x40, 0xff, ' ', 2, "LD HTR,A" },
+    { 0x50, 0xff, ' ', 2, "LD A,HTR" },
+    { 0x55, 0xff, ' ', 2, "SCALL" },
+    { 0x83, 0xff, ' ', 2, "SRET" },
+    { 0xb5, 0xff, ' ', 4, "SETUSRP %w" },
+    { 0xb1, 0xff, ' ', 4, "SETSYSP %w" },
+    { 0xfa, 0xff, ' ', 2, "LLCALL (JKHL)" },
+    { 0x03, 0xff, ' ', 2, "LDL PW,(SP+%b)" },
+    { 0x13, 0xff, ' ', 2, "LDL PX,(SP+%b)" },
+    { 0x23, 0xff, ' ', 2, "LDL PY,(SP+%b)" },
+    { 0x33, 0xff, ' ', 2, "LDL PZ,(SP+%b)" },
+    { 0x04, 0xff, ' ', 2, "LD PW,(SP+%b)" },
+    { 0x14, 0xff, ' ', 2, "LD PX,(SP+%b)" },
+    { 0x24, 0xff, ' ', 2, "LD PY,(SP+%b)" },
+    { 0x34, 0xff, ' ', 2, "LD PZ,(SP+%b)" },
+    { 0x05, 0xff, ' ', 2, "LD (SP+%b),PW" },
+    { 0x15, 0xff, ' ', 2, "LD (SP+%b),PX" },
+    { 0x25, 0xff, ' ', 2, "LD (SP+%b),PY" },
+    { 0x35, 0xff, ' ', 2, "LD (SP+%b),PZ" },
+    { 0x06, 0xff, ' ', 2, "LD HL,(PW+BC)" },
+    { 0x16, 0xff, ' ', 2, "LD HL,(PX+BC)" },
+    { 0x26, 0xff, ' ', 2, "LD HL,(PY+BC)" },
+    { 0x36, 0xff, ' ', 2, "LD HL,(PZ+BC)" },
+    { 0x07, 0xff, ' ', 2, "LD (PW+BC),HL" },
+    { 0x17, 0xff, ' ', 2, "LD (PX+BC),HL" },
+    { 0x27, 0xff, ' ', 2, "LD (PY+BC),HL" },
+    { 0x37, 0xff, ' ', 2, "LD (PZ+BC),HL" },
+    { 0x08, 0xff, ' ', 5, "LDF PW,(%l)" },
+    { 0x18, 0xff, ' ', 5, "LDF PX,(%l)" },
+    { 0x28, 0xff, ' ', 5, "LDF PY,(%l)" },
+    { 0x38, 0xff, ' ', 5, "LDF PZ,(%l)" },
+    { 0x09, 0xff, ' ', 5, "LDF (%l),PW" },
+    { 0x19, 0xff, ' ', 5, "LDF (%l),PX" },
+    { 0x29, 0xff, ' ', 5, "LDF (%l),PY" },
+    { 0x39, 0xff, ' ', 5, "LDF (%l),PZ" },
+    { 0x08, 0xff, ' ', 5, "LDF BC,(%l)" },
+    { 0x18, 0xff, ' ', 5, "LDF DE,(%l)" },
+    { 0x28, 0xff, ' ', 5, "LDF IX,(%l)" },
+    { 0x38, 0xff, ' ', 5, "LDF IY,(%l)" },
+    { 0x0b, 0xff, ' ', 5, "LDF (%l),BC" },
+    { 0x1b, 0xff, ' ', 5, "LDF (%l),DE" },
+    { 0x2b, 0xff, ' ', 5, "LDF (%l),IX" },
+    { 0x3b, 0xff, ' ', 5, "LDF (%l),IY" },
+    { 0x0c, 0xff, ' ', 6, "LD PW,%x" },
+    { 0x1c, 0xff, ' ', 6, "LD PX,%x" },
+    { 0x2c, 0xff, ' ', 6, "LD PW,%x" },
+    { 0x3c, 0xff, ' ', 6, "LD PZ,%x" },
+    { 0x0d, 0xff, ' ', 4, "LDL PW,%w" },
+    { 0x1d, 0xff, ' ', 4, "LDL PX,%w" },
+    { 0x2d, 0xff, ' ', 4, "LDL PW,%w" },
+    { 0x3d, 0xff, ' ', 4, "LDL PZ,%w" },
+    { 0x0e, 0xff, ' ', 2, "CONVC PW" },
+    { 0x1e, 0xff, ' ', 2, "CONVC PX" },
+    { 0x2e, 0xff, ' ', 2, "CONVC PY" },
+    { 0x3e, 0xff, ' ', 2, "CONVC PZ" },
+    { 0x0f, 0xff, ' ', 2, "CONVD PW" },
+    { 0x1f, 0xff, ' ', 2, "CONVD PX" },
+    { 0x2f, 0xff, ' ', 2, "CONVD PY" },
+    { 0x3f, 0xff, ' ', 2, "CONVD PZ" },
+    { 0x58, 0xff, ' ', 2, "CP JKHL,BCDE" },
+    { 0x74, 0xff, ' ', 2, "EX BC',HL" }, //'
+    { 0x7c, 0xff, ' ', 2, "EX JK',HL" }, //'
+    { 0x80, 0xff, ' ', 2, "COPY" },
+    { 0x88, 0xff, ' ', 2, "COPYR" },
+    { 0xc1, 0xff, ' ', 2, "POP PW" },
+    { 0xd1, 0xff, ' ', 2, "POP PX" },
+    { 0xe1, 0xff, ' ', 2, "POP PY" },
+    { 0xf1, 0xff, ' ', 2, "POP PZ" },
+    { 0xc5, 0xff, ' ', 2, "PUSH PW" },
+    { 0xd5, 0xff, ' ', 2, "PUSH PX" },
+    { 0xe5, 0xff, ' ', 2, "PUSH PY" },
+    { 0xf5, 0xff, ' ', 2, "PUSH PZ" },
+    { 0xc6, 0xff, ' ', 2, "ADD JKHL,BCDE" },
+    { 0xd6, 0xff, ' ', 2, "SUB JKHL,BCDE" },
+    { 0xe6, 0xff, ' ', 2, "AND JKHL,BCDE" },
+    { 0xf6, 0xff, ' ', 2, "OR JKHL,BCDE" },
+    { 0xee, 0xff, ' ', 2, "XOR JKHL,BCDE" },
+    { 0xfe, 0xff, ' ', 2, "LD HL,(SP+HL)" },
+
+    { 0, 0, 0, 0, 0, 0, 0 }
+  };
+  
+/* End of rxk.src/gpedm4.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/gpedm4.h sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/gpedm4.h
--- sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/gpedm4.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/gpedm4.h	2021-08-16 10:12:33.000000000 +0000
@@ -0,0 +1,39 @@
+/*
+ * Simulator of microcontrollers (gpedm4.h)
+ *
+ * Copyright (C) 2020,20 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef GPEDM4_HEADER
+#define GPEDM4_HEADER
+
+#include "stypes.h"
+
+
+extern struct dis_entry disass_pedm4[];
+
+
+#endif
+
+/* End of rxk.src/gpedm4.h */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/ialu.cc sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/ialu.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/ialu.cc	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/ialu.cc	2021-09-13 16:16:27.000000000 +0000
@@ -0,0 +1,1498 @@
+/*
+ * Simulator of microcontrollers (ialu.cc)
+ *
+ * Copyright (C) 2020,2021 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+
+#include "rxkcl.h"
+#include "r3kacl.h"
+#include "r4kcl.h"
+
+
+/*
+ *                                                   Increment, decrement
+ */
+
+int
+cl_rxk::inc_ss(class cl_cell16 &rp, u16_t op)
+{
+  rp.W(op+1);
+  tick(1);
+  return resGO;
+}
+
+int
+cl_rxk::inc_r(class cl_cell8 &cr, u8_t op)
+{
+  class cl_cell8 &rf= destF();
+  u8_t r, f= rF & ~(flagS|flagZ|flagV), na7, r7;
+  na7= (op&0x80)^0x80;
+  cr.W(r= op+1);
+  r7= r&0x80;
+  if (r & 0x80) f|= flagS;
+  if (!r) f|= flagZ;
+  if (na7 & r7) f|= flagV;
+  rf.W(f);
+  tick(1);
+  return resGO;
+}
+
+int
+cl_rxk::INC_iIRd(t_mem code)
+{
+  i8_t d= fetch();
+  class cl_cell8 &dest= dest8iIRd(d);
+  u8_t op= dest.read();
+  vc.wr++;
+  vc.rd++;
+  tick5p1(10);
+  return inc_r(dest, op);
+}
+
+int
+cl_rxk::dec_ss(class cl_cell16 &rp, u16_t op)
+{
+  rp.W(op-1);
+  tick(1);
+  return resGO;
+}
+
+int
+cl_rxk::dec_r(class cl_cell8 &cr, u8_t op)
+{
+  class cl_cell8 &rf= destF();
+  u8_t r, f= rF & ~(flagS|flagZ|flagV), a7, nr7;
+  a7= op&0x80;
+  cr.W(r= op-1);
+  nr7= (r&0x80)^0x80;
+  if (r & 0x80) f|= flagS;
+  if (!r) f|= flagZ;
+  if (a7 & nr7) f|= flagV;
+  rf.W(f);
+  tick(1);
+  return resGO;
+}
+
+
+int
+cl_rxk::DEC_iIRd(t_mem code)
+{
+  i8_t d= fetch();
+  class cl_cell8 &dest= dest8iIRd(d);
+  u8_t op= dest.read();
+  vc.wr++;
+  vc.rd++;
+  tick5p1(10);
+  return dec_r(dest, op);
+}
+
+int
+cl_rxk::inc_i8(t_addr addr)
+{
+  class cl_cell8 &f= destF();
+  u8_t forg= f.R() & ~(flagS|flagZ|flagV);
+  class cl_memory_cell *dest= rwas->get_cell(addr);
+  u8_t org= dest->R();
+  u8_t res= org+1;
+  if (res & 0x80) forg|= flagS;
+  if (!res) forg|= flagZ;
+  if (!(org&0x80) && (res&0x80)) forg|= flagV;
+  f.W(forg);
+  dest->W(res);
+  vc.rd++;
+  vc.wr++;
+  tick(7);
+  return resGO;
+}
+
+int
+cl_rxk::INC_IR(t_mem code)
+{
+  u16_t v= cIR->get();
+  cIR->write(v+1);
+  tick(3);
+  return resGO;
+}
+
+int
+cl_rxk::DEC_IR(t_mem code)
+{
+  u16_t v= cIR->get();
+  cIR->write(v-1);
+  tick(3);
+  return resGO;
+}
+
+int
+cl_rxk::dec_i8(t_addr addr)
+{
+  class cl_cell8 &f= destF();
+  u8_t forg= f.R() & ~(flagS|flagZ|flagV);
+  class cl_memory_cell *dest= rwas->get_cell(addr);
+  u8_t org= dest->R();
+  u8_t res= org-1;
+  if (res & 0x80) forg|= flagS;
+  if (!res) forg|= flagZ;
+  if (org&res&0x80) forg|= flagV;
+  f.W(forg);
+  dest->W(res);
+  vc.rd++;
+  vc.wr++;
+  tick(7);
+  return resGO;
+}
+
+int
+cl_rxk::add_ir_xy(u16_t op)
+{
+  u16_t op1= cIR->get();
+  u32_t res= op1 + op;
+  class cl_cell8 &f= destF();
+  u8_t forg= rF & ~flagC;
+  if (res > 0xffff) forg|= flagC;
+  cIR->write(res);
+  f.W(forg);
+  tick(3);
+  return resGO;
+}
+
+
+/*
+ *                                                             Rotate, shift
+ */
+
+/*
+     C <-- 7..<-...0 <--+
+        |               |
+        +---------------+
+ */
+int
+cl_rxk::rot8left(class cl_cell8 &dest, u8_t op)
+{
+  class cl_cell8 &f= destF();
+  u8_t a7;
+  a7= op&0x80;
+  dest.W((op<<1) | (a7?1:0));
+  f.W((rF & ~flagC) | (a7?flagC:0));
+  tick(1);
+  return resGO;
+}
+
+int
+cl_rxk::rlc(class cl_cell8 &dest, u8_t op)
+{
+  class cl_cell8 &f= destF();
+  u8_t a7, res, forg= rF & ~flagAll;
+  a7= op&0x80;
+  dest.W(res= ((op<<1) | (a7?1:0)));
+  if (!res) forg|= flagZ;
+  if (res&0x80) forg|= flagS;
+  if (res&0xf0) forg|= flagL;
+  if (a7) forg|= flagC;
+  f.W(forg);
+  tick(3);
+  return resGO;
+}
+
+
+/*
+     C <-- 15..<-...0 <--+
+         |               |
+         +---------------+
+ */
+int
+cl_rxk::rot16left(class cl_cell16 &dest, u16_t op)
+{
+  u32_t cf;
+  cf= op & 0x8000;
+  op<<= 1;
+  if (cf) op|= 1;
+  
+  class cl_cell8 &f= destF();
+  u8_t forg= rF & ~flagAll;
+  if (op & 0x8000) forg|= flagS;
+  if (!op) forg|= flagZ;
+  if (op & 0xf000) forg|= flagL;
+  if (cf) forg|= flagC;
+  f.W(forg);
+  dest.W(op);
+  tick(1);
+  return resGO;
+}
+
+
+/*
+     C <-- 31..<-...0 <--+
+         |               |
+         +---------------+
+ */
+int
+cl_rxk::rot32left(class cl_cell32 &dest, u32_t op, int nr)
+{
+  u32_t cf= 0;
+  while (nr)
+    {
+      cf= op & 0x80000000;
+      op<<= 1;
+      if (cf) op|= 1;
+      nr--;
+    }
+  class cl_cell8 &f= destF();
+  u8_t forg= rF & ~flagAll;
+  if (op & 0x80000000) forg|= flagS;
+  if (!op) forg|= flagZ;
+  if (op & 0xf0000000) forg|= flagL;
+  if (cf) forg|= flagC;
+  f.W(forg);
+  dest.W(op);
+  tick(3);
+  return resGO;
+}
+
+
+/*
+     C <-- 7..<-...0 <--+
+     |                  |
+     +------------------+
+ */
+int
+cl_rxk::rot9left(class cl_cell8 &dest, u8_t op)
+{
+  class cl_cell8 &f= destF();
+  u8_t a7, c= rF&flagC;
+  a7= op&0x80;
+  dest.W((op<<1) | (c?1:0));
+  f.W((rF & ~flagC) | (a7?flagC:0));
+  tick(1);
+  return resGO;
+}
+
+int
+cl_rxk::rl(class cl_cell8 &dest, u8_t op)
+{
+  class cl_cell8 &f= destF();
+  u8_t a7, c= rF&flagC, res, forg;
+  a7= op&0x80;
+  dest.W(res= ((op<<1) | (c?1:0)));
+  forg= rF & ~flagAll;
+  if (!res) forg|= flagZ;
+  if (res&0x80) forg|= flagS;
+  if (res&0xf0) forg|= flagL;
+  if (a7) forg|= flagC;
+  f.W(forg);
+  tick(3);
+  return resGO;
+}
+
+
+/*
+     C <-- 15..<-...0 <--+
+     |                   |
+     +-------------------+
+ */
+int
+cl_rxk::rot17left(class cl_cell16 &dest, u16_t op)
+{
+  class cl_cell8 &f= destF();
+  u8_t forg;
+  u16_t a15, c= rF & flagC, res;
+  forg= rF & ~flagAll;
+  a15= op&0x8000;
+  dest.W(res= (op<<1) | (c?1:0));
+  if (a15) forg|= flagC;
+  if (res & 0x8000) forg|= flagS;
+  if (!res) forg|= flagZ;
+  if (res & 0xf000) forg|= flagL;
+  f.W(forg);
+  tick(1);
+  return resGO;
+}
+
+/*
+     C <-- 31..<-...0 <--+
+     |                   |
+     +-------------------+
+ */
+int
+cl_rxk::rot33left(class cl_cell32 &dest, u32_t op, int nr)
+{
+  class cl_cell8 &f= destF();
+  u8_t forg= rF;
+  bool cf= forg & flagC;;
+  while (nr)
+    {
+      bool msb= op & 0x80000000;
+      op<<= 1;
+      if (cf) op|= 1;
+      cf= msb;
+      nr--;
+    }
+  forg&= ~flagAll;
+  if (cf) forg|= flagC;
+  if (!op) forg|= flagZ;
+  if (op & 0x80000000) forg|= flagS;
+  if (op & 0xf0000000) forg|= flagL;
+  f.W(forg);
+  dest.W(op);
+  tick(3);
+  return resGO;
+}
+
+/*   7..->...0 --> C
+     |         |
+     +---------+
+ */
+int
+cl_rxk::rot8right(class cl_cell8 &dest, u8_t op)
+{
+  class cl_cell8 &f= destF();
+  u8_t a0;
+  a0= op&0x01;
+  dest.W((op>>1) | (a0?0x80:0));
+  f.W((rF & ~flagC) | (a0?flagC:0));
+  tick(1);
+  return resGO;
+}
+
+
+/*   15...->.....0 --> C
+     |           |
+     +-----------+
+ */
+int
+cl_rxk::rot16right(class cl_cell16 &dest, u16_t op)
+{
+  class cl_cell8 &f= destF();
+  u8_t forg;
+  bool cf= false;
+  cf= op & 1;
+  op>>= 1;
+  if (cf) op|= 0x8000;
+    
+  forg= rF & ~flagAll;
+  if (cf) forg|= flagC;
+  if (!op) forg|= flagZ;
+  if (op & 0x8000) forg|= flagS;
+  if (op & 0xf000) forg|= flagL;
+  f.W(forg);
+  dest.W(op);
+  tick(1);
+  return resGO;
+}
+
+
+/*   31.....->......0 --> C
+     |              |
+     +--------------+
+ */
+int
+cl_rxk::rot32right(class cl_cell32 &dest, u32_t op, int nr)
+{
+  class cl_cell8 &f= destF();
+  u8_t forg;
+  bool cf= false;
+  while (nr)
+    {
+      cf= op & 1;
+      op>>= 1;
+      if (cf) op|= 0x80000000;
+      nr--;
+    }
+  forg= rF & ~flagAll;
+  if (cf) forg|= flagC;
+  if (!op) forg|= flagZ;
+  if (op & 0x80000000) forg|= flagS;
+  if (op & 0xf0000000) forg|= flagL;
+  f.W(forg);
+  dest.W(op);
+  tick(3);
+  return resGO;
+}
+
+int
+cl_rxk::rrc(class cl_cell8 &dest, u8_t op)
+{
+  class cl_cell8 &f= destF();
+  u8_t a0, res, forg= rF & ~flagAll;
+  a0= op&0x01;
+  dest.W(res= ((op>>1) | (a0?0x80:0)));
+  if (!res) forg|= flagZ;
+  if (res&0x80) forg|= flagS;
+  if (res&0xf0) forg|= flagL;
+  if (a0) forg|= flagC;
+  f.W(forg);
+  tick(3);
+  return resGO;
+}
+
+
+/*
+     7..->...0 --> C
+     |             |
+     +-------------+
+ */
+int
+cl_rxk::rot9right(class cl_cell8 &dest, u8_t op)
+{
+  class cl_cell8 &f= destF();
+  u8_t a0, c= rF&flagC;
+  a0= op&0x01;
+  dest.W((op>>1) | (c?0x80:0));
+  f.W((rF & ~flagC) | (a0?flagC:0));
+  tick(1);
+  return resGO;
+}
+
+int
+cl_rxk::rr(class cl_cell8 &dest, u8_t op)
+{
+  class cl_cell8 &f= destF();
+  u8_t a0, c= rF&flagC, res, forg;
+  a0= op&0x01;
+  dest.W(res= ((op>>1) | (c?0x80:0)));
+  forg= rF & ~flagAll;
+  if (!res) forg|= flagZ;
+  if (res&0x80) forg|= flagS;
+  if (res&0xf0) forg|= flagL;
+  if (a0) forg|= flagC;
+  f.W(forg);
+  tick(3);
+  return resGO;
+}
+
+
+/*
+     C --> 15..->...0 -->+
+     |                   |
+     +<------------------+
+ */
+int
+cl_rxk::rot17right(class cl_cell16 &dest, u16_t op)
+{
+  class cl_cell8 &f= destF();
+  u8_t forg;
+  u16_t a0, c= rF & flagC, res;
+  forg= rF & ~flagAll;
+  a0= op&1;
+  dest.W(res= (c?0x8000:0) | (op>>1));
+  if (a0) forg|= flagC;
+  if (res & 0x8000) forg|= flagS;
+  if (!res) forg|= flagZ;
+  if (res & 0xf000) forg|= flagL;
+  f.W(forg);
+  tick(1);
+  return resGO;
+}
+
+
+/*
+     C --> 31..->...0 -->+
+     |                   |
+     +<------------------+
+ */
+int
+cl_rxk::rot33right(class cl_cell32 &dest, u32_t op, int nr)
+{
+  class cl_cell8 &f= destF();
+  u8_t forg;
+  u32_t cf= rF & flagC;
+  while (nr)
+    {
+      op>>= 1;
+      if (cf) op|= 0x80000000;
+      cf= op & 1;
+      nr--;
+    }
+  forg= rF & ~flagAll;
+  if (cf) forg|= flagC;
+  if (!op) forg|= flagZ;
+  if (op & 0x80000000) forg|= flagS;
+  if (op & 0xf0000000) forg|= flagL;
+  f.W(forg);
+  dest.W(op);
+  tick(3);
+  return resGO;
+}
+
+
+/*
+   C <--  7..<-..0  <-- 0
+*/
+int
+cl_rxk::sla8(class cl_cell8 &dest, u8_t op)
+{
+  class cl_cell8 &f= destF();
+  u8_t res, forg= rF & ~flagAll;
+  if (op & 0x80) forg|= flagC;
+  dest.W(res= (op<<1));
+  if (res & 0x80) forg|= flagS;
+  if (!res) forg|= flagZ;
+  if (res & 0xf0) forg|= flagL;
+  f.W(forg);
+  tick(3);
+  return resGO;
+}
+
+/*
+   C <--  31..<-..0  <-- 0
+*/
+int
+cl_rxk::sla32(class cl_cell32 &dest, u32_t op, int nr)
+{
+  class cl_cell8 &f= destF();
+  u32_t forg= rF & ~flagAll;
+  u32_t cf= 0;
+  while (nr)
+    {
+      cf= op & 0x80000000;
+      op<<= 1;
+      nr--;
+    }
+  if (cf) forg|= flagC;
+  if (op & 0x80000000) forg|= flagS;
+  if (!op) forg|= flagZ;
+  if (op & 0xf0000000) forg|= flagL;
+  f.W(forg);
+  tick(3);
+  return resGO;
+}
+
+
+/*
+  +--> 7..->..0  --> C
+  |    |
+  +----+  
+*/
+int
+cl_rxk::sra8(class cl_cell8 &dest, i8_t op)
+{
+  class cl_cell8 &f= destF();
+  i8_t res, forg= rF & ~flagAll;
+  if (op & 1) forg|= flagC;
+  dest.W(res= (op>>1));
+  if (res & 0x8000) forg|= flagS;
+  if (!res) forg|= flagZ;
+  if (res & 0xf000) forg|= flagL;
+  f.W(forg);
+  tick(3);
+  return resGO;
+}
+
+/*
+  +--> 31......->......0  --> C
+  |     |
+  +-----+  
+*/
+int
+cl_rxk::sra32(class cl_cell32 &dest, i32_t op, int nr)
+{
+  class cl_cell8 &f= destF();
+  i8_t forg= rF & ~flagAll;
+  bool cf= false;
+  while (nr)
+    {
+      cf= op & 1;
+      op>>= 1;
+      nr--;
+    }
+  if (op & 0x80000000) forg|= flagS;
+  if (!op) forg|= flagZ;
+  if (op & 0xf0000000) forg|= flagL;
+  if (cf) forg|= flagC;
+  f.W(forg);
+  dest.W(op);
+  tick(3);
+  return resGO;
+}
+
+/*
+  0-->  7..->..0  --> C
+*/
+int
+cl_rxk::srl8(class cl_cell8 &dest, u8_t op)
+{
+  class cl_cell8 &f= destF();
+  u8_t res, forg= rF & ~flagAll;
+  if (op & 1) forg|= flagC;
+  dest.W(res= (op>>1));
+  if (res & 0x8000) forg|= flagS;
+  if (!res) forg|= flagZ;
+  if (res & 0xf000) forg|= flagL;
+  f.W(forg);
+  tick(3);
+  return resGO;
+}
+
+/*
+  0-->  31.....->.....0  --> C
+*/
+int
+cl_rxk::srl32(class cl_cell32 &dest, u32_t op, int nr)
+{
+  class cl_cell8 &f= destF();
+  u8_t forg= rF & ~flagAll;
+  bool cf= false;
+  while (nr)
+    {
+      cf= op & 1;
+      op>>= 1;
+      nr--;
+    }
+  if (op & 0x80000000) forg|= flagS;
+  if (!op) forg|= flagZ;
+  if (op & 0xf0000000) forg|= flagL;
+  if (cf) forg|= flagC;
+  f.W(forg);
+  dest.W(op);
+  tick(3);
+  return resGO;
+}
+
+int
+cl_rxk::bit_r(u8_t b, u8_t op)
+{
+  class cl_cell8 &f= destF();
+  u8_t forg= rF & ~flagZ, res;
+  res= (1<read(rHL);
+  vc.rd++;
+  res= (1<read(cIR->get()+d);
+  vc.rd++;
+  res= (1<read(rHL);
+  vc.rd++;
+  res= ~(1<write(rHL, res);
+  vc.wr++;
+  tick(9);
+  return resGO;
+}
+
+int
+cl_rxk::res_iIRd(u8_t b, i8_t d)
+{
+  u8_t res, op;
+  t_addr a= cIR->get()+d;
+  op= rwas->read(a);
+  vc.rd++;
+  res= ~(1<write(a, res);
+  vc.wr++;
+  tick5p1(12);
+  return resGO;
+}
+
+
+int
+cl_rxk::set_r(u8_t b, class cl_cell8 &dest, u8_t op)
+{
+  u8_t res;
+  res= (1<read(rHL);
+  vc.rd++;
+  res= (1<write(rHL, res);
+  vc.wr++;
+  tick(9);
+  return resGO;
+}
+
+int
+cl_rxk::set_iIRd(u8_t b, i8_t d)
+{
+  u8_t res, op;
+  t_addr a= cIR->get()+d;
+  op= rwas->read(a);
+  vc.rd++;
+  res= (1<write(a, res);
+  vc.wr++;
+  tick5m1(11);
+  return resGO;
+}
+
+
+/*
+ *                                                           Bitwise, logical
+ */
+
+int
+cl_rxk::BOOL_HL(t_mem code)
+{
+  class cl_cell16 &dhl= destHL();
+  class cl_cell8 &f= destF();
+  u8_t forg= rF & ~flagAll;
+  if (rHL)
+    dhl.W(1);
+  else
+    forg|= flagZ;
+  f.W(forg);
+  tick(1);
+  return resGO;
+}
+
+int
+cl_rxk::xor8(class cl_cell8 &dest, u8_t op1, u8_t op2)
+{
+  class cl_cell8 &f= destF();
+  u8_t forg= f.R() & ~flagAll;
+  u8_t res= op1 ^ op2;
+  dest.W(res);
+  if (res & 0x80) forg|= flagS;
+  if (!res) forg|= flagZ;
+  if (res&0xf0) forg|= flagL;
+  f.W(forg);
+  tick(1);
+  return resGO;
+}
+
+int
+cl_rxk::xor16(class cl_cell16 &dest, u16_t op1, u16_t op2)
+{
+  class cl_cell8 &f= destF();
+  u8_t forg= f.R() & ~flagAll;
+  u16_t res= op1 ^ op2;
+  dest.W(res);
+  if (res & 0x8000) forg|= flagS;
+  if (!res) forg|= flagZ;
+  if (res&0xf000) forg|= flagL;
+  f.W(forg);
+  tick5m2(3);
+  return resGO;
+}
+
+int
+cl_rxk::or8(class cl_cell8 &dest, u8_t op1, u8_t op2)
+{
+  class cl_cell8 &f= destF();
+  u8_t forg= f.R() & ~flagAll;
+  u8_t res= op1 | op2;
+  dest.W(res);
+  if (res & 0x80) forg|= flagS;
+  if (!res) forg|= flagZ;
+  if (res&0xf0) forg|= flagL;
+  f.W(forg);
+  tick(1);
+  return resGO;
+}
+
+int
+cl_rxk::or16(class cl_cell16 &dest, u16_t op1, u16_t op2)
+{
+  class cl_cell8 &f= destF();
+  //class cl_cell16 &dhl= destHL();
+  u16_t res= op1/*rHL*/ | op2/*rDE*/;
+  u8_t forg= rF & ~flagAll;
+  dest.W(res);
+  if (res & 0x8000)
+    forg|= flagS;
+  if (!res)
+    forg|= flagZ;
+  // flagL?
+  if (res & 0xf000)
+    forg|= flagL;
+  f.W(forg);
+  tick(1);
+  return resGO;
+}
+
+int
+cl_rxk::and8(class cl_cell8 &dest, u8_t op1, u8_t op2)
+{
+  class cl_cell8 &f= destF();
+  u8_t res= op1 & op2, forg= rF & ~flagAll;
+  if (!res) forg|= flagZ;
+  if (res&0x80) forg|= flagS;
+  if (res&0xf0) forg|= flagL;
+  dest.W(res);
+  f.W(forg);
+  tick(1);
+  return resGO;
+}
+
+int
+cl_rxk::and16(class cl_cell16 &dest, u16_t op1, u16_t op2)
+{
+  class cl_cell8 &f= destF();
+  //class cl_cell16 &dhl= destHL();
+  u16_t res= op1/*rHL*/ & op2/*rDE*/;
+  u8_t forg= rF & ~flagAll;
+  dest.W(res);
+  if (res & 0x8000)
+    forg|= flagS;
+  if (!res)
+    forg|= flagZ;
+  // flagL?
+  if (res & 0xf000)
+    forg|= flagL;
+  f.W(forg);
+  tick(1);
+  return resGO;
+}
+
+int
+cl_rxk::XOR_A_iIRd(t_mem code)
+{
+  i8_t d= fetch();
+  class cl_cell8 &a= destA(), &f= destF();
+  u8_t forg= rF & ~flagAll, res= rA ^ rwas->read(cIR->get() + d);
+  vc.rd++;
+  if (!res) forg|= flagZ;
+  if (res & 0x80) forg|= flagS;
+  if (res & 0xf0) forg|= flagL;
+  a.W(res);
+  f.W(forg);
+  tick5p1(8);
+  return resGO;
+}
+
+int
+cl_rxk::OR_A_iIRd(t_mem code)
+{
+  i8_t d= fetch();
+  class cl_cell8 &a= destA(), &f= destF();
+  u8_t forg= rF & ~flagAll, res= rA | rwas->read(cIR->get() + d);
+  vc.rd++;
+  if (!res) forg|= flagZ;
+  if (res & 0x80) forg|= flagS;
+  if (res & 0xf0) forg|= flagL;
+  a.W(res);
+  f.W(forg);
+  tick5p1(8);
+  return resGO;
+}
+
+int
+cl_rxk::AND_A_iIRd(t_mem code)
+{
+  i8_t d= fetch();
+  class cl_cell8 &a= destA(), &f= destF();
+  u8_t forg= rF & ~flagAll, res= rA & rwas->read(cIR->get() + d);
+  vc.rd++;
+  if (!res) forg|= flagZ;
+  if (res & 0x80) forg|= flagS;
+  if (res & 0xf0) forg|= flagL;
+  a.W(res);
+  f.W(forg);
+  tick5p1(8);
+  return resGO;
+}
+
+int
+cl_rxk::BOOL_IR(t_mem code)
+{
+  u16_t v= cIR->get();
+  if (v)
+    cIR->W(v=1);
+  u8_t f= rF & ~flagAll;
+  //if (v&0x8000) f|= flagS;
+  if (!v) f|= flagZ;
+  cF.W(f);
+  tick(3);
+  return resGO;
+}
+
+int
+cl_rxk::AND_IR_DE(t_mem code)
+{
+  class cl_cell8 &f= destF();
+  u8_t forg= rF & ~flagAll;
+  u16_t v;
+  cIR->W(v= cIR->get() & rDE);
+  if (!v) forg|= flagZ;
+  if (v&0x8000) forg|= flagS;
+  if (v^0xf000) forg|= flagL;
+  f.W(forg);
+  tick(3);
+  return resGO;
+}
+
+int
+cl_rxk::OR_IR_DE(t_mem code)
+{
+  class cl_cell8 &f= destF();
+  u8_t forg= rF & ~flagAll;
+  u16_t v;
+  cIR->W(v= cIR->get() | rDE);
+  if (!v) forg|= flagZ;
+  if (v&0x8000) forg|= flagS;
+  if (v^0xf000) forg|= flagL;
+  f.W(forg);
+  tick(3);
+  return resGO;
+}
+
+
+/*
+ *                                                                Arithmetic
+ */
+
+int
+cl_rxk::CPL(t_mem code)
+{
+  destA().W(~rA);
+  tick(1);
+  return resGO;
+}
+
+int
+cl_rxk::add_hl_ss(u16_t op)
+{
+  class cl_cell16 &hl= destHL();
+  class cl_cell8 &f= destF();
+  u8_t forg= rF;
+  u32_t res= rHL + op;
+  hl.W(res);
+  if (res > 0xffff)
+    f.W(forg|= flagC);
+  else
+    f.W(forg&= ~flagC);
+  tick(1);
+  return resGO;
+}
+
+int
+cl_rxk::adc_hl_ss(u16_t op)
+{
+  class cl_cell16 &hl= destHL();
+  class cl_cell8 &f= destF();
+  u32_t res= rHL + op + ((rF&flagC)?1:0);
+  u8_t forg= rF & ~flagAll;
+  u16_t c1= 0, c2;
+  if (res > 0xffff)
+    {
+      forg|= flagC;
+      c1= 0x8000;
+    }
+  if (!res) forg|= flagZ;
+  if (res & 0x8000) forg|= flagS;
+  res= (rHL&0x7fff)+(op&0x7fff)+((rF&flagC)?1:0);
+  c2= res&0x8000;
+  if (c1^c2) forg|= flagV;
+  f.W(forg);
+  hl.W(res);
+  tick(3);
+  return resGO;
+}
+
+int
+cl_rxk::add8(u8_t op2, bool cy)
+{
+  class cl_cell8 &a= destA(), &f= destF();
+  u8_t v1= rA, forg;
+  u16_t res= v1+op2+(cy?((rF&flagC)?1:0):0);
+  u8_t a7, b7, r7, na7, nb7, nr7;
+  forg= rF & ~flagAll;
+  a7= v1&0x80; na7= a7^0x80;
+  b7= op2&0x80; nb7= b7^0x80;
+  r7= res&0x80; nr7= r7^0x80;
+  if ((a7&b7&nr7) | (na7&nb7&r7)) forg|= flagV;
+  if (res > 0xff) forg|= flagC;
+  if (!(res & 0xff)) forg|= flagZ;
+  if (res & 0x80) forg|= flagS;
+  a.W(res);
+  f.W(forg);
+  tick(3);
+  return resGO;
+}
+
+int
+cl_rxk::sub8(u8_t op2, bool cy)
+{
+  class cl_cell8 &a= destA(), &f= destF();
+  u8_t v1= rA, forg;
+  u16_t res= v1+(~op2)+(cy?((rF&flagC)?1:0):1);
+  u8_t a7, b7, r7, na7, nb7, nr7;
+  i8_t op1= rA;
+  i8_t o2= op2;
+  i8_t r= op1-o2;
+  if (cy && (rF&flagC)) r--;
+  res= r;
+  forg= rF & ~(flagS|flagZ|flagV);
+  a7= v1&0x80; na7= a7^0x80;
+  b7= op2&0x80; nb7= b7^0x80;
+  r7= res&0x80; nr7= r7^0x80;
+  if ((a7&nb7&nr7) | (na7&b7&r7)) forg|= flagV;
+  //if (res > 0xff) forg|= flagC;
+  if (rAop2) || (!cy && (rA==op2))) forg&= ~flagC;
+  if (!(res & 0xff)) forg|= flagZ;
+  if (res & 0x80) forg|= flagS;
+  a.W(res);
+  f.W(forg);
+  tick(3);
+  return resGO;
+}
+
+int
+cl_rxk::NEG(t_mem code)
+{
+  u8_t org= destA().get();
+  destA().set(0);
+  sub8(org, false);
+  tick5p9(0);
+  return resGO;
+}
+
+int
+cl_rxk::sub16(u16_t op2, bool cy)
+{
+  class cl_cell16 &hl= destHL();
+  class cl_cell8 &f= destF();
+  u16_t v1= rHL;
+  u8_t forg;
+  u32_t res;//= //v1+(~op2)+(cy?((rF&flagC)?1:0):1);
+  u16_t a15, b15, r15, na15, nb15, nr15;
+  i16_t op1= rHL;
+  i16_t o2= op2;
+  i16_t r= op1-o2;
+  if (cy && (rF&flagC)) r--;
+  res= r;
+  forg= rF & ~(flagS|flagZ|flagV);
+  a15= v1&0x8000; na15= a15^0x8000;
+  b15= op2&0x8000; nb15= b15^0x8000;
+  r15= res&0x8000; nr15= r15^0x8000;
+  if ((a15&nb15&nr15) | (na15&b15&r15)) forg|= flagV;
+  //if (res > 0xffff) forg|= flagC;
+  if (rHLop2) || (!cy && (rA==op2))) forg&= ~flagC;
+  if (!(res & 0xffff)) forg|= flagZ;
+  if (res & 0x8000) forg|= flagS;
+  hl.W(res);
+  f.W(forg);
+  tick(3);
+  return resGO;
+}
+
+int
+cl_rxk::sub32(u32_t op1, u32_t op2, class cl_cell32 &cRes, bool cy)
+{
+  class cl_cell8 &f= destF();
+  u32_t v1= op1;
+  u8_t forg;
+  u32_t res;
+  u32_t a31, b31, r31, na31, nb31, nr31;
+  i32_t o2= op2;
+  i32_t r= op1-o2;
+  if (cy && (rF&flagC)) r--;
+  res= r;
+  forg= rF & ~(flagZ|flagS|flagV);
+  a31=  v1&0x80000000; na31= a31^0x80000000;
+  b31= op2&0x80000000; nb31= b31^0x80000000;
+  r31= res&0x80000000; nr31= r31^0x80000000;
+  if ((a31&nb31&nr31) | (na31&b31&r31)) forg|= flagV;
+  if (op1op2) || (!cy && (op1==op2))) forg&= ~flagC;
+  if (!res) forg|= flagZ;
+  if (res & 0x80000000) forg|= flagS;
+  cRes.W(res);
+  f.W(forg);
+  tick(3);
+  return resGO;
+}
+
+int
+cl_rxk::cp8(u8_t op1, u8_t op2)
+{
+  class cl_cell8 &f= destF();
+  u8_t forg= rF & ~flagAll;
+  u8_t res= op1-op2;
+  if (op1 0xffff)
+    f.W(forg|= flagC);
+  else
+    f.W(forg&= ~flagC);
+  tick(3);
+  return resGO;
+}
+
+int
+cl_rxk::MUL(t_mem code)
+{
+  i16_t op1= rBC, op2= rDE;
+  i32_t res= op1*op2;
+  cHL.W((res>>16)&0xffff);
+  cBC.W(res);
+  tick(11);
+  return resGO;
+}
+
+
+/*
+ *                                                    R3000A,R4000,R5000
+ */
+
+int
+cl_r3ka::UMx(bool add)
+{
+  u32_t v1, v2;
+
+  tick(7);
+  do
+  {
+    v1= rom->read(rIX);
+    vc.rd++;
+    v2= rom->read(rIY);
+    vc.rd++;
+    v2= v2*rDE;
+    v2+= raDE;
+    if (rF & flagC) v2++;
+    if (add)
+      v1+= v2;
+    else
+      v1-= v2;
+
+    rom->write(rHL, v1);
+    vc.wr++;
+    caDE.W(v1>>8);
+    u8_t f= rF & ~flagC;
+    if (v1>>24) f|= flagC;
+    cF.W(f);
+
+    cBC.W(rBC-1);
+    cIX.W(rIX+1);
+    cIY.W(rIY+1);
+    cHL.W(rHL+1);
+    tick(8);
+  }
+  while (rBC);
+  return resGO;
+}
+
+int
+cl_r4k::subhl(class cl_cell16 &dest, u16_t op)
+{
+  i32_t v, o;
+  u8_t forg= rF & ~flagC;
+  v= rHL;
+  o= op;
+  v= v - o;
+  if (v & 0xffff0000) forg|= flagC;
+  destF().W(forg);
+  dest.W(v);
+  tick(1);
+  return resGO;
+}
+
+int
+cl_r4k::test8(u8_t op)
+{
+  u8_t forg= rF & ~flagAll;
+  if (!op) forg|= flagZ;
+  if (op & 0x80) forg|= flagS;
+  if (op & 0xf0) forg|= flagL;
+  destF().W(forg);
+  tick(1);
+  return resGO;
+}
+
+int
+cl_r4k::test16(u16_t op)
+{
+  u8_t forg= rF & ~flagAll;
+  if (!op) forg|= flagZ;
+  if (op & 0x8000) forg|= flagS;
+  if (op & 0xf000) forg|= flagL;
+  destF().W(forg);
+  tick(1);
+  return resGO;
+}
+
+int
+cl_r4k::test32(u32_t op)
+{
+  u8_t forg= rF & ~flagAll;
+  if (!op) forg|= flagZ;
+  if (op & 0x80000000) forg|= flagS;
+  if (op & 0xf0000000) forg|= flagL;
+  destF().W(forg);
+  tick(1);
+  return resGO;
+}
+
+int
+cl_r4k::flag_cc_hl(t_mem code)
+{
+  bool cond= false;
+  if ((code & 0x60) == 0x40)
+    {
+      switch ((code >> 3) & 3)
+	{
+	case 0: cond= !(rF & flagZ); break;
+	case 1: cond= rF & flagZ; break;
+	case 2: cond= !(rF & flagC); break;
+	case 3: cond= rF & flagC; break;
+	}
+    }
+  else if ((code & 0x60) == 0x20)
+    {
+      switch ((code >> 3) & 3)
+	{
+	case 0: cond= cond_GT(rF); break;
+	case 1: cond= cond_LT(rF); break;
+	case 2: cond= cond_GTU(rF); break;
+	case 3: cond= rF & flagV; break;
+	}
+    }
+  cHL.W(cond?1:0);
+  tick(3);
+  return resGO;
+}
+
+int
+cl_r4k::RLC_8_IRR(t_mem code)
+{
+  u32_t op= cIRR->get();
+  u32_t msb= op >> 24;
+  op<<= 8;
+  op|= msb;
+  cIRR->write(op);
+  tick(3);
+  return resGO;
+}
+
+int
+cl_r4k::RLB_A_IRR(t_mem code)
+{
+  u32_t op= cIRR->get();
+  u32_t msb= op >> 24;
+  op<<= 8;
+  op|= rA;
+  cA.W(msb);
+  cIRR->write(op);
+  tick(3);
+  return resGO;
+}
+
+int
+cl_r4k::RRC_8_IRR(t_mem code)
+{
+  u32_t op= cIRR->get();
+  u32_t lsb= op & 0xff;
+  op>>= 8;
+  op|= lsb<<24;
+  cIRR->write(op);
+  tick(3);
+  return resGO;
+}
+
+int
+cl_r4k::RRB_A_IRR(t_mem code)
+{
+  u32_t op= cIRR->get();
+  u32_t lsb= op & 0xff;
+  op>>= 8;
+  op|= (u32_t)rA << 24;
+  cA.W(lsb);
+  cIRR->write(op);
+  tick(3);
+  return resGO;
+}
+
+int
+cl_r4k::CP_HL_D(t_mem code)
+{
+  i8_t d= fetch();
+  i16_t d16;
+  d16= d;
+  return cp16(rHL, d16);
+}
+
+int
+cl_r4k::MULU(t_mem code)
+{
+  u32_t v= rBC * rDE;
+  cBC.W(v);
+  cHL.W(v>>16);
+  tick(11);
+  return resGO;
+}
+
+int
+cl_r4k::ADD_JKHL_BCDE(t_mem code)
+{
+  class cl_cell8 &f= destF();
+  u8_t forg= rF & ~flagC;
+  u64_t v= rJKHL + rBCDE;
+  destJKHL().W(v);
+  if (v > 0xffffffff)
+    forg|= flagC;
+  f.W(forg);
+  tick(3);
+  return resGO;
+}
+
+int
+cl_r4k::SUB_JKHL_BCDE(t_mem code)
+{
+  class cl_cell8 &f= destF();
+  u8_t forg= rF & ~flagC;
+  u32_t v= rJKHL - rBCDE;
+  if (rJKHL < rBCDE)
+    forg|= flagC;
+  destJKHL().W(v);
+  f.W(forg);
+  tick(3);
+  return resGO;
+}
+
+int
+cl_r4k::AND_JKHL_BCDE(t_mem code)
+{
+  class cl_cell8 &f= destF();
+  u8_t forg= rF & ~flagAll;
+  u32_t v= rJKHL & rBCDE;
+  if (v & 0x80000000) forg|= flagS;
+  if (v & 0xf0000000) forg|= flagL;
+  if (!v) forg|= flagZ;
+  destJKHL().W(v);
+  f.W(forg);
+  tick(3);
+  return resGO;
+}
+  
+int
+cl_r4k::OR_JKHL_BCDE(t_mem code)
+{
+  class cl_cell8 &f= destF();
+  u8_t forg= rF & ~flagAll;
+  u32_t v= rJKHL | rBCDE;
+  if (v & 0x80000000) forg|= flagS;
+  if (v & 0xf0000000) forg|= flagL;
+  if (!v) forg|= flagZ;
+  destJKHL().W(v);
+  f.W(forg);
+  tick(3);
+  return resGO;
+}
+  
+int
+cl_r4k::XOR_JKHL_BCDE(t_mem code)
+{
+  class cl_cell8 &f= destF();
+  u8_t forg= rF & ~flagAll;
+  u32_t v= rJKHL ^ rBCDE;
+  if (v & 0x80000000) forg|= flagS;
+  if (v & 0xf0000000) forg|= flagL;
+  if (!v) forg|= flagZ;
+  destJKHL().W(v);
+  f.W(forg);
+  tick(3);
+  return resGO;
+}
+  
+
+/* End of rxk.src/ialu.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/ibranch.cc sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/ibranch.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/ibranch.cc	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/ibranch.cc	2021-09-12 15:51:43.000000000 +0000
@@ -0,0 +1,475 @@
+/*
+ * Simulator of microcontrollers (ibranch.cc)
+ *
+ * Copyright (C) 2020,2021 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+
+#include "appcl.h"
+
+#include "rxkcl.h"
+#include "r3kacl.h"
+#include "r4kcl.h"
+
+
+int
+cl_rxk::DJNZ(t_mem code)
+{
+  u8_t v= rB - 1;
+  i8_t r= fetch();
+  destB().W(v);
+  if (v)
+    PC= (PC + r) & 0xffff;
+  tick5p1(4);
+  return resGO;
+}
+
+int
+cl_rxk::JR(t_mem code)
+{
+  i8_t r= fetch();
+  PC= (PC + r) & 0xffff;
+  tick5p1(4);
+  return resGO;
+}
+
+int
+cl_rxk::LJP(t_mem code)
+{
+  u8_t x, h, l;
+  l= fetch();
+  h= fetch();
+  x= fetch();
+  cXPC.W(x);
+  PC= h*256+l;
+  tick(9);
+  return resGO;
+}
+
+int
+cl_rxk::CALL_mn(t_mem code)
+{
+  u8_t h, l;
+  l= fetch();
+  h= fetch();
+  rom->write(--rSP, PC>>8);
+  rom->write(--rSP, PC);
+  PC= h*256+l;
+  cSP.W(rSP);
+  tick5p1(11);
+  vc.wr+= 2;
+  return resGO;
+}
+
+int
+cl_rxk::LCALL_lmn(t_mem code)
+{
+  u8_t h, l, x;
+  l= fetch();
+  h= fetch();
+  x= fetch();
+  cSP.W(rSP-1);
+  rom->write(rSP, rXPC);
+  cSP.W(rSP-1);
+  rom->write(rSP, PC>>8);
+  cSP.W(rSP-1);
+  rom->write(rSP, PC);
+  PC= h*256+l;
+  cXPC.W(x);
+  tick5p1(18);
+  vc.wr+= 3;
+  return resGO;
+}
+
+int
+cl_rxk::rst_v(t_mem code)
+{
+  if ((jaj || (juj&1)) && (code == 0xef)) return resGO;
+  u8_t l= (code&0x38) << 1;
+  cSP.W(rSP-1);
+  rom->write(rSP, PC>>8);
+  cSP.W(rSP-1);
+  rom->write(rSP, PC);
+  PC= rIIR * 256 + l;
+  vc.wr+= 2;
+  tick5p3(7);
+  return resGO;
+}
+
+
+int
+cl_rxk::jr_cc(bool cond)
+{
+  i8_t r= fetch();
+  if (cond)
+    PC= (PC + r) & 0xffff;
+  tick5p1(4);
+  return resGO;
+}
+
+int
+cl_rxk::ret_f(bool f)
+{
+  if (f)
+    {
+      u8_t l, h;
+      l= mem->read(rSP);
+      cSP.W(++rSP);
+      h= mem->read(rSP);
+      cSP.W(++rSP);
+      vc.rd+= 2;
+      PC= h*256 + l;
+    }
+  tick(7);
+  return resGO;
+}
+
+int
+cl_rxk::jp_f_mn(bool f)
+{
+  u8_t l, h;
+  l= fetch();
+  h= fetch();
+  if (f)
+    {
+      PC= h*256+l;
+    }
+  tick(6);
+  return resGO;
+}
+
+int
+cl_rxk::LRET(t_mem code)
+{
+  u8_t l, h, x;
+  l= mem->read(rSP);
+  cSP.W(++rSP);
+  h= mem->read(rSP);
+  cSP.W(++rSP);
+  PC= h*256+l;
+  x= mem->read(rSP);
+  cSP.W(++rSP);
+  cXPC.W(x);
+  tick(12);
+  return resGO;
+}
+
+int
+cl_rxk::RETI(t_mem code)
+{
+  u8_t l, h, x;
+  x= mem->read(rSP);
+  cSP.W(++rSP);
+  l= mem->read(rSP);
+  cSP.W(++rSP);
+  h= mem->read(rSP);
+  cSP.W(++rSP);
+  PC= h*256+l;
+  cIP.W(x);
+  tick(11);
+  return resGO;
+}
+
+
+/*
+ *                                                    R3000A,R4000,R5000
+ */
+
+int
+cl_r3ka::SYSCALL(t_mem code)
+{
+  cSP.W(rSP-1);
+  rom->write(rSP, PC>>8);
+  cSP.W(rSP-1);
+  rom->write(rSP, PC);
+  PC= rIIR * 256 + 0x60;
+  vc.wr+= 2;
+  tick5p3(9);
+  return resGO;
+}
+
+int
+cl_r4k::DWJNZ(t_mem code)
+{
+  i8_t e= fetch();
+  u16_t v= rBC-1;
+  destBC().W(v);
+  if (v)
+    PC= (PC + e) & 0xffff;
+  tick5p1(6);
+  return resGO;
+}
+
+int
+cl_r4k::lljp_cx(t_mem code)
+{
+  u8_t cx= (code>>3) & 0x3;
+  bool cond= false, z, s, v, c, sxv;
+  s= rF & flagS;
+  v= rF & flagV;
+  z= rF & flagZ;
+  c= rF & flagC;
+  sxv= (!s && v) || (s && !v);
+  switch (cx)
+    {
+    case 0: // GT: (Z or (S xor V))=0
+      cond= !(z || (sxv));
+      break;
+    case 1: // GTU: ((C=0) and (Z=0))=1
+      cond= !c && !z;
+      break;
+    case 2: // LT: (S xor V)=1
+      cond= sxv;
+      break;
+    case 3: // V: V=1
+      cond= rF & flagV;
+      break;
+    }
+  u16_t mn, lxpc;
+  mn= fetch();
+  mn+= fetch() * 256;
+  lxpc= fetch();
+  lxpc+= fetch() * 256;
+  lxpc&= 0xfff;
+  if (cond)
+    {
+      PC= mn;
+      LXPC->W(lxpc);
+    }
+  tick(13);
+  return resGO;
+}
+
+int
+cl_r4k::lljp_cc(t_mem code)
+{
+  u8_t cc= (code>>3) & 0x3;
+  bool cond= false, z, c;
+  z= rF & flagZ;
+  c= rF & flagC;
+  switch (cc)
+    {
+    case 0: // NZ
+      cond= !z;
+      break;
+    case 1: // Z
+      cond= z;
+      break;
+    case 2: // NC
+      cond= !c;
+      break;
+    case 3: // C
+      cond= c;
+      break;
+    }
+  u16_t mn, lxpc;
+  mn= fetch();
+  mn+= fetch() * 256;
+  lxpc= fetch();
+  lxpc+= fetch() * 256;
+  lxpc&= 0xfff;
+  if (cond)
+    {
+      PC= mn;
+      LXPC->W(lxpc);
+    }
+  tick(13);
+  return resGO;
+}
+
+int
+cl_r4k::jre_cx_cc(bool cond)
+{
+  u8_t el, eh;
+  el= fetch();
+  eh= fetch();
+  i16_t ee= eh*256+el;
+  if (cond)
+    PC= (PC + ee) & 0xffff;
+  tick5p1(8);
+  return resGO;
+}
+
+int
+cl_r4k::CALL_iIR(t_mem code)
+{
+  u16_t a= rSP;
+  rom->write(--a, PC>>8);
+  rom->write(--a, PC);
+  vc.wr+= 2;
+  cSP.W(a);
+  PC= cIR->get();
+  tick5p1(11);
+  return resGO;
+}
+
+int
+cl_r4k::CALL_iHL(t_mem code)
+{
+  u16_t a= rSP;
+  rom->write(--a, PC>>8);
+  rom->write(--a, PC);
+  vc.wr+= 2;
+  cSP.W(a);
+  PC= rHL;
+  tick5p1(11);
+  return resGO;
+}
+
+int
+cl_r4k::LLRET(t_mem code)
+{
+  u16_t h= 0, l= 0;
+  u16_t a= rSP;
+  l= rom->read(a++);
+  l+= rom->read(a++)*256;
+  h= rom->read(a++);
+  h+= rom->read(a++)*256;
+  vc.rd+= 4;
+  cSP.W(a);
+  PC= l;
+  LXPC->write(h);
+  tick(13);
+  return resGO;
+}
+
+int
+cl_r4k::FSYSCALL(t_mem code)
+{
+  u16_t a= rSP;
+  rom->write(--a, PC>>8);
+  rom->write(--a, PC);
+  rom->write(--a, rSU);
+  cSP.W(a);
+  vc.wr+= 3;
+  PC= rIIR*256+0x60;
+  cSU.W(rSU<<2);
+  tick5p1(14);
+  destF().W(rF|flagC);
+  return resGO;
+}
+
+int
+cl_r4k::SYSRET(t_mem code)
+{
+  u16_t a= rSP, v;
+  cSU.W(rom->read(a++));
+  v= rom->read(a++);
+  v+= rom->read(a++)*256;
+  vc.rd+= 3;
+  cSP.W(a);
+  tick(11);
+  PC= v;
+  return resGO;
+}
+
+int
+cl_r4k::LLCALL_iJKHL(t_mem code)
+{
+  u16_t a= rSP, x= LXPC->get();
+  rom->write(--a, x>>8);
+  rom->write(--a, x);
+  rom->write(--a, PC>>8);
+  rom->write(--a, PC);
+  PC= rHL;
+  LXPC->W(rJK);
+  cSP.W(a);
+  tick5p1(18);
+  return resGO;
+}
+
+int
+cl_r4k::LLJP_lxpcmn(t_mem code)
+{
+  u16_t mn, lxpc;
+  mn= fetch();
+  mn+= fetch()*256;
+  lxpc= fetch();
+  lxpc+= fetch()*256;
+  LXPC->W(lxpc);
+  PC= mn;
+  tick(11);
+  return resGO;
+}
+
+int
+cl_r4k::LLCALL_lxpcmn(t_mem code)
+{
+  u16_t mn, lxpc;
+  u16_t a= rSP;
+  
+  lxpc= rXPC;
+  rom->write(--a, lxpc>>8);
+  rom->write(--a, lxpc);
+  mn= PC;
+  rom->write(--a, mn>>8);
+  rom->write(--a, mn);
+  cSP.W(a);
+  vc.wr+= 4;
+  
+  mn= fetch();
+  mn+= fetch()*256;
+  lxpc= fetch();
+  lxpc+= fetch()*256;
+
+  LXPC->W(lxpc);
+  PC= mn;
+  tick(11);
+  return resGO;
+}
+
+int
+cl_r4k::JRE_ee(t_mem code)
+{
+  u16_t ee;
+  ee= fetch();
+  ee+= fetch()*256;
+  i16_t offset= ee;
+  PC+= offset;
+  PC&= 0xffff;
+  tick5p1(6);
+  return resGO;
+}
+
+int
+cl_r4k::jr_cx_e(bool cond)
+{
+  i8_t e= fetch();
+  if (cond)
+    PC= (PC + e) & 0xffff;
+  tick5p1(4);
+  return resGO;
+}
+
+int
+cl_r4k::jp_cx_mn(bool cond)
+{
+  u16_t mn= fetch();
+  mn+= fetch()*256;
+  if (cond)
+    PC= mn;
+  tick(6);
+  return resGO;
+}
+
+
+/* End of rxk.src/ibranch.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/imove.cc sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/imove.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/imove.cc	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/imove.cc	2021-09-13 16:16:27.000000000 +0000
@@ -0,0 +1,1740 @@
+/*
+ * Simulator of microcontrollers (imove.cc)
+ *
+ * Copyright (C) 2020,2021 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+
+#include "glob.h"
+#include "rxkcl.h"
+#include "r4kcl.h"
+
+
+int
+cl_rxk::ld_dd_mn(class cl_cell16 &dd)
+{
+  u8_t l, h;
+  l= fetch();
+  h= fetch();
+  dd.W(h*256+l);
+  tick(5);
+  return resGO;
+}
+
+int
+cl_rxk::LD_imn_HL(t_mem code)
+{
+  u8_t l, h;
+  l= fetch();
+  h= fetch();
+  t_addr a= h*256+l;
+  rwas->write(a, rL);
+  rwas->write(a+1, rH);
+  vc.wr+= 2;
+  tick(12);
+  return resGO;
+}
+
+int
+cl_rxk::LD_HL_imn(t_mem code)
+{
+  u8_t l, h;
+  l= fetch();
+  h= fetch();
+  t_addr a= h*256+l;
+  l= rwas->read(a);
+  h= rwas->read(a+1);
+  vc.rd+= 2;
+  destH().W(h);
+  destL().W(l);
+  tick(10);
+  return resGO;
+}
+
+int
+cl_rxk::ld_r_n(class cl_cell8 &r)
+{
+  r.W(fetch());
+  tick(3);
+  return resGO;
+}
+
+int
+cl_rxk::ld_ihl_r(u8_t op)
+{
+  class cl_cell8 &c= dest8iHL();
+  c.W(op);
+  vc.wr++;
+  tick(5);
+  return resGO;
+}
+
+int
+cl_rxk::ld_r_ihl(class cl_cell8 &destr)
+{
+  u8_t v= read8(rHL);
+  destr.W(v);
+  tick(4);
+  return resGO;
+}
+
+int
+cl_rxk::ld_r_g(class cl_cell8 &dest, u8_t op)
+{
+  dest.W(op);
+  tick(1);
+  return resGO;
+}
+
+int
+cl_rxk::pop_zz(class cl_cell16 &dest)
+{
+  u8_t l, h;
+  l= rom->read(rSP);
+  cSP.W(rSP+1);
+  h= rom->read(rSP);
+  cSP.W(rSP+1);
+  dest.W(h*256+l);
+  vc.rd+= 2;
+  tick(6);
+  return resGO;
+}
+
+int
+cl_rxk::push_zz(u16_t op)
+{
+  u8_t h, l;
+  h= op>>8;
+  l= op&0xff;
+  cSP.W(rSP-1);
+  rom->write(rSP, h);
+  cSP.W(rSP-1);
+  rom->write(rSP, l);
+  vc.wr+= 2;
+  tick5p1(9);
+  return resGO;
+}
+
+int
+cl_rxk::ld_d_i(int dif)
+{
+  int t= 9;
+  if (rwas == ioi)
+    t+= 1;
+  else if (rwas == ioe)
+    t+= 2;
+  rwas->write(rDE, rom->read(rHL));
+  vc.rd++;
+  vc.wr++;
+  cBC.W(rBC-1);
+  cDE.W(rDE+dif);
+  cHL.W(rHL+dif);
+  tick(t);
+  if (rBC == 0)
+    cF.W(rF & ~flagV);
+  else
+    cF.W(rF | flagV);
+  return resGO;
+}
+
+int
+cl_rxk::LDxR(int dif)
+{
+  int t= 7;
+  if (rwas == ioi)
+    t+= 1;
+  else if (rwas == ioe)
+    t+= 2;
+  tick(5);
+  do
+    {
+      rwas->write(rDE, rom->read(rHL));
+      vc.rd++;
+      vc.wr++;
+      cBC.W(rBC-1);
+      cDE.W(rDE+dif);
+      cHL.W(rHL+dif);
+      tick(t);
+    }
+  while (rBC != 0);
+  cF.W(rF & ~flagV);
+  return resGO;
+}
+
+int
+cl_rxk::ld_iIRd_r(u8_t op)
+{
+  i8_t d= fetch();
+  t_addr a= cIR->get();
+  a+= d;
+  rwas->write(a, op);
+  vc.wr++;
+  tick5p1(9);
+  return resGO;
+}
+
+int
+cl_rxk::ld_r_iIRd(class cl_cell8 &op)
+{
+  i8_t d= fetch();
+  t_addr a= cIR->get() + d;
+  op.W(rwas->read(a));
+  vc.rd++;
+  tick5p1(8);
+  return resGO;
+}
+
+int
+cl_rxk::ld_hl_op(u16_t op)
+{
+  destHL().W(op);
+  tick(1);
+  return resGO;
+}
+
+int
+cl_rxk::LD_iBC_A(t_mem code)
+{
+  class cl_cell8 &c= dest8iBC();
+  c.W(rA);
+  vc.wr++;
+  tick(6);
+  return resGO;
+}
+
+int
+cl_rxk::LD_iDE_A(t_mem code)
+{
+  class cl_cell8 &c= dest8iDE();
+  c.W(rA);
+  vc.wr++;
+  tick(6);
+  return resGO;
+}
+
+int
+cl_rxk::LD_iMN_A(t_mem code)
+{
+  class cl_cell8 &c= dest8imn();
+  c.W(rA);
+  vc.wr++;
+  tick(9);
+  return resGO;
+}
+
+int
+cl_rxk::LD_A_iBC(t_mem code)
+{
+  destA().W(read8(rBC));
+  tick(5);
+  return resGO;
+}
+
+int
+cl_rxk::LD_A_iDE(t_mem code)
+{
+  destA().W(read8(rDE));
+  tick(5);
+  return resGO;
+}
+
+int
+cl_rxk::LD_A_iMN(t_mem code)
+{
+  destA().W(read8(fetch16()));
+  tick(8);
+  return resGO;
+}
+
+int
+cl_rxk::EX_AF_aAF(t_mem code)
+{
+  u16_t temp= rAF;
+  cAF.W(raAF);
+  caAF.W(temp);
+  tick(1);
+  return resGO;
+}
+
+int
+cl_rxk::EX_aDE_HL(t_mem code)
+{
+  class cl_cell16 &dhl= destHL();
+  u16_t t= raDE;
+  caDE.W(dhl.get());
+  dhl.W(t);
+  tick(1);
+  return resGO;
+}
+
+int
+cl_rxk::EX_DE_HL(t_mem code)
+{
+  class cl_cell16 &dhl= destHL();
+  u16_t t= rDE;
+  cDE.W(dhl.get());
+  dhl.W(t);
+  tick(1);
+  return resGO;
+}
+
+int
+cl_rxk::LD_HL_iSPn(t_mem code)
+{
+  class cl_cell16 &dest= destHL();
+  u8_t n= fetch(), l, h;
+  u16_t addr= rSP+n;
+  l= rom->read(addr);
+  addr++;
+  h= rom->read(addr);
+  dest.W(h*256+l);
+  vc.rd+= 2;
+  tick5p1(8);
+  return resGO;
+}
+
+int
+cl_rxk::LD_HL_iIXd(t_mem code)
+{
+  i8_t d= fetch();
+  class cl_cell16 &dhl= destHL();
+  u16_t a= rIX+d;
+  u8_t h, l;
+  l= rwas->read(a);
+  h= rwas->read(a+1);
+  dhl.W(h*256+l);
+  vc.rd+= 2;
+  tick5p1(8);
+  return resGO;
+}
+
+int
+cl_rxk::LD_iIXd_HL(t_mem code)
+{
+  i8_t d= fetch();
+  u16_t a= rIX+d;
+  rwas->write(a, rL);
+  rwas->write(a+1, rH);
+  vc.wr+= 2;
+  tick5p1(10);
+  return resGO;
+}
+
+int
+cl_rxk::LD_iSPn_HL(t_mem code)
+{
+  u8_t n= fetch();
+  u16_t addr= rSP+n;
+  rom->write(addr, rL);
+  addr++;
+  rom->write(addr, rH);
+  vc.wr+= 2;
+  tick5p1(10);
+  return resGO;
+}
+
+int
+cl_rxk::LD_EIR_A(t_mem code)
+{
+  cEIR.W(rA);
+  tick(3);
+  return resGO;
+}
+
+int
+cl_rxk::LD_IIR_A(t_mem code)
+{
+  cIIR.W(rA);
+  tick(3);
+  return resGO;
+}
+
+int
+cl_rxk::LD_A_EIR(t_mem code)
+{
+  class cl_cell8 &f= destF();
+  u8_t res= rEIR, forg= rF & ~(flagS|flagZ);
+  destA().W(res);
+  if (!res) forg|= flagZ;
+  if (res&0x80) forg|= flagS;
+  f.W(forg);
+  tick(3);
+  return resGO;
+}
+
+int
+cl_rxk::LD_A_IIR(t_mem code)
+{
+  class cl_cell8 &f= destF();
+  u8_t res= rIIR, forg= rF & ~(flagS|flagZ);
+  destA().W(res);
+  if (!res) forg|= flagZ;
+  if (res&0x80) forg|= flagS;
+  f.W(forg);
+  tick(3);
+  return resGO;
+}
+
+int
+cl_rxk::LD_IR_mn(t_mem code)
+{
+  u8_t h, l;
+  l= fetch();
+  h= fetch();
+  cIR->W(h*256+l);
+  tick(7);
+  return resGO;
+}
+
+int
+cl_rxk::POP_IR(t_mem code)
+{
+  u8_t h, l;
+  l= rom->read(rSP);
+  cSP.W(rSP+1);
+  h= rom->read(rSP);
+  cSP.W(rSP+1);
+  vc.rd+= 2;
+  cIR->write(h*256+l);
+  tick(8);
+  return resGO;
+}
+
+int
+cl_rxk::PUSH_IR(t_mem code)
+{
+  u16_t v= cIR->get();
+  u8_t h, l;
+  h= v>>8;
+  l= v;
+  cSP.W(rSP-1);
+  rom->write(rSP, h);
+  cSP.W(rSP-1);
+  rom->write(rSP, l);
+  vc.wr+= 2;
+  tick5p1(11);
+  return resGO;
+}
+
+int
+cl_rxk::EX_iSP_IR(t_mem code)
+{
+  u16_t temp;
+  temp= rom->read(rSP+1) * 256 + rom->read(rSP);
+  vc.rd+= 2;
+  rom->write(rSP, cIR->get());
+  rom->write(rSP+1, cIR->get()>>8);
+  vc.wr+= 2;
+  cIR->write(temp);
+  tick(14);
+  return resGO;
+}
+
+int
+cl_rxk::LD_SP_IR(t_mem code)
+{
+  cSP.W(cIR->get());
+  tick5p2(1);
+  return resGO;
+}
+
+int
+cl_rxk::LD_IR_iSPn(t_mem code)
+{
+  u8_t n= fetch(), h, l;
+  u16_t addr= rSP+n;
+  l= rom->read(addr);
+  addr++;
+  h= rom->read(addr);
+  vc.rd+= 2;
+  cIR->write(h*256+l);
+  tick5p1(10);
+  return resGO;
+}
+
+int
+cl_rxk::LD_iSPn_IR(t_mem code)
+{
+  u16_t v= cIR->get();
+  u8_t n= fetch();
+  u16_t addr= rSP+n;
+  rom->write(addr, v);
+  addr++;
+  rom->write(addr, v>>8);
+  vc.wr+= 2;
+  tick5p1(12);
+  return resGO;
+}
+
+int
+cl_rxk::LD_HL_iIRd(t_mem code)
+{
+  class cl_cell16 *ir= cIR;
+  if (cIR == &cIX)
+    ir= &cHL;
+  i8_t d= fetch();
+  t_addr a= ir->get() + d;
+  destHL().W(read16io(a));
+  tick5p1(10);
+  return resGO;
+}
+
+int
+cl_rxk::LD_iIRd_n(t_mem code)
+{
+  i8_t d= fetch();
+  u8_t n= fetch();
+  t_addr a= cIR->get()+d;
+  rwas->write(a, n);
+  tick5p1(10);
+  vc.wr++;
+  return resGO;
+}
+
+int
+cl_rxk::ld_dd_imn(class cl_cell16 &dest)
+{
+  u16_t a= fetch16();
+  dest.W(read16io(a));
+  tick(12);
+  return resGO;
+}
+
+int
+cl_rxk::EXX_iSP_HL(t_mem code)
+{
+  class cl_cell16 &hl= destHL();
+  u16_t temp= read16(rSP);
+  write16(rSP, rHL);
+  hl.W(temp);
+  tick(14);
+  return resGO;
+}
+
+int
+cl_rxk::ld_add_BC_DE(class cl_cell16 &dest, u16_t src)
+{
+  dest.W(src);
+  tick(3);
+  return resGO;
+}
+
+int
+cl_rxk::ld_imn_ss(u16_t src)
+{
+  u8_t l, h;
+  l= fetch();
+  h= fetch();
+  u16_t a= h*256+l;
+  l= src;
+  h= src>>8;
+  rwas->write(a, l);
+  a++;
+  rwas->write(a, h);
+  vc.wr+= 2;
+  tick(14);
+  return resGO;
+}
+
+int
+cl_rxk::ldp_irp_rp(u16_t addr, u16_t src)
+{
+  t_addr a= ((u32_t)rA << 16) + addr;
+  mem->phwrite(a, src&0xff);
+  addr++;
+  a= ((u32_t)rA << 16) + addr; // LDP wraps around 64k page boundary
+  mem->phwrite(a, (src>>8)&0xff);
+  vc.wr+= 2;
+  tick(11);
+  return resGO;
+}
+
+int
+cl_rxk::ldp_rp_irp(class cl_cell16 &dest, u16_t addr)
+{
+  t_addr a= ((u32_t)rA >> 16) + addr;
+  u8_t l= mem->phread(a);
+  addr++;
+  a= ((u32_t)rA >> 16) + addr;
+  u8_t h= mem->phread(a);
+  dest.W(h*256+l);
+  vc.rd+= 2;
+  tick(9);
+  return resGO;
+}
+
+int
+cl_rxk::LD_XPC_A(t_mem code)
+{
+  cXPC.W(rA);
+  atomic= true;
+  tick(3);
+  return resGO;
+}
+
+int
+cl_rxk::LD_A_XPC(t_mem code)
+{
+  destA().W(rXPC);
+  atomic= true;
+  tick(3);
+  return resGO;
+}
+
+int
+cl_rxk::PUSH_IP(t_mem code)
+{
+  cSP.W(rSP-1);
+  rom->write(rSP, rIP);
+  vc.wr++;
+  tick5p1(8);
+  return resGO;
+}
+
+int
+cl_rxk::POP_IP(t_mem code)
+{
+  cIP.W(rom->read(rSP));
+  cSP.W(rSP+1);
+  vc.rd++;
+  tick(6);
+  atomic= true;
+  return resGO;
+}
+
+int
+cl_rxk::LD_imn_IR(t_mem code)
+{
+  u8_t h, l;
+  l= fetch();
+  h= fetch();
+  u16_t addr= h*256+l;
+  u16_t v= cIR->get();
+  h= v>>8;
+  l= v;
+  rwas->write(addr, l);
+  addr++;
+  rwas->write(addr, h);
+  vc.wr+= 2;
+  tick(14);
+  return resGO;
+}
+
+int
+cl_rxk::LD_IR_imn(t_mem code)
+{
+  u8_t h, l;
+  l= fetch();
+  h= fetch();
+  u16_t addr= h*256+l;
+  l= rwas->read(addr);
+  addr++;
+  h= rwas->read(addr);
+  cIR->write(h*256+l);
+  vc.rd+= 2;
+  tick(12);
+  return resGO;
+}
+
+int
+cl_rxk::LD_HL_IR(t_mem code)
+{
+  destHL().W(cIR->get());
+  tick(3);
+  return resGO;
+}
+
+int
+cl_rxk::LD_IR_HL(t_mem code)
+{
+  cIR->write(rHL);
+  tick(3);
+  return resGO;
+}
+
+int
+cl_rxk::LD_iHLd_HL(t_mem code)
+{
+  i8_t d= fetch();
+  u16_t addr= rHL+d;
+  rwas->write(addr, rL);
+  addr++;
+  rwas->write(addr, rH);
+  tick5p1(12);
+  return resGO;
+}
+
+
+/*
+ *                                                Rabbit 3000A,4000,5000
+ */
+
+int
+cl_r3ka::LDxSR(int dif)
+{
+  int t= 7;
+  if (rwas == ioi)
+    t+= 1;
+  else if (rwas == ioe)
+    t+= 2;
+  tick(5);
+  do
+    {
+      rwas->write(rDE, rom->read(rHL));
+      vc.rd++;
+      vc.wr++;
+      cBC.W(rBC-1);
+      cHL.W(rHL+dif);
+      tick(t);
+    }
+  while (rBC != 0);
+  cF.W(rF & ~flagV);
+  return resGO;
+}
+
+int
+cl_r3ka::LSxDR(int dif)
+{
+  int t= 7;
+  if (rwas == ioi)
+    t+= 1;
+  else if (rwas == ioe)
+    t+= 2;
+  tick(5);
+  do
+    {
+      rom->write(rDE, rwas->read(rHL));
+      vc.rd++;
+      vc.wr++;
+      cBC.W(rBC-1);
+      cDE.W(rDE+dif);
+      tick(t);
+    }
+  while (rBC != 0);
+  cF.W(rF & ~flagV);
+  return resGO;
+}
+
+int
+cl_r3ka::LSxR(int dif)
+{
+  int t= 7;
+  if (rwas == ioi)
+    t+= 1;
+  else if (rwas == ioe)
+    t+= 2;
+  tick(5);
+  do
+    {
+      rom->write(rDE, rwas->read(rHL));
+      vc.rd++;
+      vc.wr++;
+      cBC.W(rBC-1);
+      cDE.W(rDE+dif);
+      cHL.W(rHL+dif);
+      tick(t);
+    }
+  while (rBC != 0);
+  cF.W(rF & ~flagV);
+  return resGO;
+}
+
+int
+cl_r3ka::PUSH_SU(t_mem code)
+{
+  cSP.W(rSP-1);
+  rom->write(rSP, rSU);
+  vc.wr++;
+  tick5p1(8);
+  atomic= true;
+  return resGO;
+}
+
+int
+cl_r3ka::POP_SU(t_mem code)
+{
+  cSU.W(rom->read(rSP));
+  cSP.W(rSP+1);
+  vc.rd++;
+  atomic= true;
+  tick5p1(8);
+  return resGO;
+}
+
+
+/*
+ *                                                     Rabbit 4000, 5000
+ */
+
+int
+cl_r4k::LD_A_iIRA(t_mem code)
+{
+  class cl_cell8 &a= destA();
+  u16_t addr= cIR->get() + rA;
+  a.W(rwas->read(addr));
+  vc.rd++;
+  tick5p1(7);
+  return resGO;
+}
+
+int
+cl_r4k::CBM_N(t_mem code)
+{
+  u8_t n= fetch();
+  u8_t temp;
+
+  temp= rom->read(rHL);
+  vc.rd++;
+  temp&= ~n;
+  temp|= (rA & n);
+  rom->write(rHL, temp);
+  vc.wr++;
+
+  rwas->write(rDE, temp);
+  vc.wr++;
+
+  tick(14);
+  return resGO;
+}
+
+int
+cl_r4k::ld_pd_ihtr_hl(class cl_cell32 &dest)
+{
+  dest.W(read32(rHTR+rHL));
+  tick5p1(13);
+  return resGO;
+}
+
+int
+cl_r4k::ld_irr_iird(class cl_cell16 &ir)
+{
+  u32_t v= 0;
+  u16_t a= ir.get();
+  i8_t d= fetch();
+  a+= d;
+  v= (v>>8) + rwas->read(a++);
+  v= (v>>8) + rwas->read(a++);
+  v= (v>>8) + rwas->read(a++);
+  v= (v>>8) + rwas->read(a);
+  vc.rd+= 4;
+  destIRR()->W(v);
+  tick5p1(14);
+  return resGO;
+}
+
+int
+cl_r4k::ld_iird_irr(class cl_cell16 &ir)
+{
+  u32_t v= cIRR->get();
+  u16_t a= ir.get();
+  i8_t d= fetch();
+  a+= d;
+  rwas->write(a++, v); v>>= 8;
+  rwas->write(a++, v); v>>= 8;
+  rwas->write(a++, v); v>>= 8;
+  rwas->write(a  , v);
+  vc.wr+= 4;
+  tick5p1(18);
+  return resGO;
+}
+
+int
+cl_r4k::SBOX_A(t_mem code)
+{
+  destA().W(sbox_tab[rA]);
+  tick(3);
+  return resGO;
+}
+
+int
+cl_r4k::IBOX_A(t_mem code)
+{
+  destA().W(ibox_tab[rA]);
+  tick(3);
+  return resGO;
+}
+
+int
+cl_r4k::PUSH_MN(t_mem code)
+{
+  u8_t m, n;
+  n= fetch();
+  m= fetch();
+  cSP.W(rSP-1);
+  rom->write(rSP, m);
+  cSP.W(rSP-1);
+  rom->write(rSP, n);
+  vc.wr+= 2;
+  tick5p1(14);
+  return resGO;
+}
+
+int
+cl_r4k::LD_IRR_iHL(t_mem code)
+{
+  u32_t v= 0;
+  u16_t a= rHL;
+  v+= rwas->read(a++);
+  v+= rwas->read(a++) << 8;
+  v+= rwas->read(a++) << 16;
+  v+= rwas->read(a  ) << 24;
+  vc.rd+= 4;
+  destIRR()->W(v);
+  tick(13);
+  return resGO;
+}
+
+int
+cl_r4k::LD_iHL_IRR(t_mem code)
+{
+  u32_t v= cIRR->get();
+  u16_t a= rHL;
+  rwas->write(a++, v); v>>= 8;
+  rwas->write(a++, v); v>>= 8;
+  rwas->write(a++, v); v>>= 8;
+  rwas->write(a  , v);
+  vc.wr+= 4;
+  tick(17);
+  return resGO;
+}
+
+int
+cl_r4k::LD_IRR_iSPn(t_mem code)
+{
+  u32_t v= 0;
+  u16_t a= rSP;
+  u8_t n= fetch();
+  a+= n;
+  v+= rwas->read(a++);
+  v+= rwas->read(a++) << 8;
+  v+= rwas->read(a++) << 16;
+  v+= rwas->read(a  ) << 24;
+  vc.rd+= 4;
+  destIRR()->W(v);
+  tick5p1(14);
+  return resGO;
+}
+
+int
+cl_r4k::LD_iSPn_IRR(t_mem code)
+{
+  u32_t v= cIRR->get();
+  u16_t a= rSP;
+  u8_t n= fetch();
+  a+= n;
+  rwas->write(a++, v); v>>= 8;
+  rwas->write(a++, v); v>>= 8;
+  rwas->write(a++, v); v>>= 8;
+  rwas->write(a  , v);
+  vc.wr+= 4;
+  tick5p1(18);
+  return resGO;
+}
+
+int
+cl_r4k::POP_IRR(t_mem code)
+{
+  u32_t v= 0;
+  u16_t a= rSP;
+  v+= rom->read(a++);
+  v+= rom->read(a++) << 8;
+  v+= rom->read(a++) << 16;
+  v+= rom->read(a++) << 24;
+  cSP.W(a);
+  destIRR()->W(v);
+  tick(12);
+  return resGO;
+}
+
+int
+cl_r4k::PUSH_IRR(t_mem code)
+{
+  u32_t v= cIRR->get();
+  u16_t a= rSP;
+  rom->write(--a, v>>24);
+  rom->write(--a, v>>16);
+  rom->write(--a, v>>8 );
+  rom->write(--a, v    );
+  cSP.W(a);
+  vc.wr+= 4;
+  tick5p1(17);
+  return resGO;
+}
+
+int
+cl_r4k::LDF_IRR_iLMN(t_mem code)
+{
+  u32_t v= 0;
+  t_addr a= fetch();
+  a<<= 8; a+= fetch();
+  a<<= 8; a+= fetch();
+  v+= mem->phread(a); a= (a+1)&0xffffff;
+  v<<= 8; v+= mem->phread(a); a= (a+1)&0xffffff;
+  v<<= 8; v+= mem->phread(a); a= (a+1)&0xffffff;
+  v<<= 8; v+= mem->phread(a);
+  vc.rd+= 4;
+  destIRR()->write(v);
+  tick(18);
+  return resGO;
+}
+
+int
+cl_r4k::LDF_iLMN_IRR(t_mem code)
+{
+  u32_t v= cIRR->get();
+  t_addr a= fetch();
+  a<<= 8; a+= fetch();
+  a<<= 8; a+= fetch();
+  mem->phwrite(a++, v>>24); a&= 0xffffff;
+  mem->phwrite(a++, v>>16); a&= 0xffffff;
+  mem->phwrite(a++, v>>8 ); a&= 0xffffff;
+  mem->phwrite(a  , v    );
+  vc.wr+= 4;
+  tick(22);
+  return resGO;
+}
+
+int
+cl_r4k::LDF_iLMN_HL(t_mem code)
+{
+  u16_t v= rHL;
+  t_addr a= fetch();
+  a<<= 8; a+= fetch();
+  a<<= 8; a+= fetch();
+  mem->phwrite(a++, v>>8 ); a&= 0xffffff;
+  mem->phwrite(a  , v    );
+  vc.wr+= 2;
+  tick5m2(14);
+  return resGO;
+}
+
+int
+cl_r4k::LDF_HL_iLMN(t_mem code)
+{
+  u16_t v= 0;
+  t_addr a= fetch();
+  a<<= 8; a+= fetch();
+  a<<= 8; a+= fetch();
+  v+= mem->phread(a); a= (a+1)&0xffffff;
+  v<<= 8; v+= mem->phread(a);
+  vc.rd+= 2;
+  destHL().W(v);
+  tick(12);
+  return resGO;
+}
+
+int
+cl_r4k::LDF_ilmn_A(t_mem code)
+{
+  u32_t a= fetch();
+  a+= fetch()*256;
+  a+= fetch()*256*256;
+  mem->phwrite(a, rA);
+  tick(11);
+  return resGO;
+}
+
+int
+cl_r4k::LDF_A_ilmn(t_mem code)
+{
+  u32_t a= fetch();
+  a+= fetch()*256;
+  a+= fetch()*256*256;
+  u8_t v= mem->phread(a);
+  destA().W(v);
+  tick(10);
+  return resGO;
+}
+
+int
+cl_r4k::ldf_pd_ilmn(class cl_cell32 &pd)
+{
+  u32_t a= fetch();
+  a+= fetch()*256;
+  a+= fetch()*256*256;
+  u32_t v= mem->phread(a++);
+  v+= mem->phread(a++)<<8;
+  v+= mem->phread(a++)<<16;
+  v+= mem->phread(a  )<<24;
+  vc.rd+= 4;
+  pd.W(v);
+  tick(18);
+  return resGO;
+}
+
+int
+cl_r4k::ldf_ilmn_ps(u32_t ps)
+{
+  u32_t a= fetch();
+  a+= fetch()*256;
+  a+= fetch()*256*256;
+  mem->phwrite(a++, ps);
+  mem->phwrite(a++, ps>>8);
+  mem->phwrite(a++, ps>>16);
+  mem->phwrite(a  , ps>>24);
+  vc.wr+= 4;
+  tick(22);
+  return resGO;
+}
+
+int
+cl_r4k::ldf_rr_ilmn(class cl_cell16 &rr)
+{
+  u32_t a= fetch();
+  a+= fetch()*256;
+  a+= fetch()*256*256;
+  u16_t v= mem->phread(a++);
+  v+= mem->phread(a++)<<8;
+  vc.rd+= 2;
+  rr.W(v);
+  tick(14);
+  return resGO;
+}
+
+int
+cl_r4k::ldf_ilmn_rr(u16_t rr)
+{
+  u32_t a= fetch();
+  a+= fetch()*256;
+  a+= fetch()*256*256;
+  mem->phwrite(a++, rr);
+  mem->phwrite(a  , rr>>8);
+  vc.wr+= 2;
+  tick(16);
+  return resGO;
+}
+
+int
+cl_r4k::ld_irr_ips_hl(t_mem code)
+{
+  class cl_cell32 *ps= &cPW;
+  switch (code & 0x30)
+    {
+    case 0x00: ps= &cPW; break;
+    case 0x10: ps= &cPX; break;
+    case 0x20: ps= &cPY; break;
+    case 0x30: ps= &cPZ; break;
+    }
+  u32_t p= ps->get();
+  u32_t v   = mem->pxread(px16se(p, rHL+0));
+  v<<= 8; v+= mem->pxread(px16se(p, rHL+1));
+  v<<= 8; v+= mem->pxread(px16se(p, rHL+2));
+  v<<= 8; v+= mem->pxread(px16se(p, rHL+3));
+  vc.rd+= 4;
+  destIRR()->write(v);
+  tick5p1(13);
+  return resGO;
+}
+
+
+int
+cl_r4k::ld_irr_ips_d(t_mem code)
+{
+  class cl_cell32 *ps= &cPW;
+  switch (code & 0x30)
+    {
+    case 0x00: ps= &cPW; break;
+    case 0x10: ps= &cPX; break;
+    case 0x20: ps= &cPY; break;
+    case 0x30: ps= &cPZ; break;
+    }
+  u32_t p= ps->get();
+  u8_t d= fetch();
+  u32_t v   = mem->pxread(px8se(p, d)+0);
+  v<<= 8; v+= mem->pxread(px8se(p, d)+1);
+  v<<= 8; v+= mem->pxread(px8se(p, d)+2);
+  v<<= 8; v+= mem->pxread(px8se(p, d)+3);
+  vc.rd+= 4;
+  destIRR()->write(v);
+  tick5p1(13);
+  return resGO;
+}
+
+int
+cl_r4k::ld_ips_hl_irr(t_mem code)
+{
+  class cl_cell32 *ps= &cPW;
+  switch (code & 0x30)
+    {
+    case 0x00: ps= &cPW; break;
+    case 0x10: ps= &cPX; break;
+    case 0x20: ps= &cPY; break;
+    case 0x30: ps= &cPZ; break;
+    }
+  u32_t p= ps->get();
+  u32_t v= cIRR->get();
+  mem->pxwrite(px16se(p, rHL+0), v);
+  mem->pxwrite(px16se(p, rHL+1), v>>8);
+  mem->pxwrite(px16se(p, rHL+2), v>>16);
+  mem->pxwrite(px16se(p, rHL+3), v>>24);
+  vc.wr+= 4;
+  tick5p1(17);
+  return resGO;
+}
+
+int
+cl_r4k::ld_ips_d_irr(t_mem code)
+{
+  class cl_cell32 *ps= &cPW;
+  switch (code & 0x30)
+    {
+    case 0x00: ps= &cPW; break;
+    case 0x10: ps= &cPX; break;
+    case 0x20: ps= &cPY; break;
+    case 0x30: ps= &cPZ; break;
+    }
+  u32_t p= ps->get();
+  u32_t v= cIRR->get();
+  u8_t d= fetch();
+  mem->pxwrite(px16se(p, d)+0, v);
+  mem->pxwrite(px16se(p, d)+1, v>>8);
+  mem->pxwrite(px16se(p, d)+2, v>>16);
+  mem->pxwrite(px16se(p, d)+3, v>>24);
+  vc.wr+= 4;
+  tick5p1(18);
+  return resGO;
+}
+
+int
+cl_r4k::ldl_px_ir(t_mem code)
+{
+  switch (code & 0x30)
+    {
+    case 0x00: destPW().W(0xffff0000+cIR->get()); break;
+    case 0x10: destPX().W(0xffff0000+cIR->get()); break;
+    case 0x20: destPY().W(0xffff0000+cIR->get()); break;
+    case 0x30: destPZ().W(0xffff0000+cIR->get()); break;
+    }
+  tick(3);
+  return resGO;
+}
+
+int
+cl_r4k::ldl_px_irrl(t_mem code)
+{
+  switch (code & 0x30)
+    {
+    case 0x00: destPW().W(0xffff0000|cIRR->get()); break;
+    case 0x10: destPX().W(0xffff0000|cIRR->get()); break;
+    case 0x20: destPY().W(0xffff0000|cIRR->get()); break;
+    case 0x30: destPZ().W(0xffff0000|cIRR->get()); break;
+    }
+  tick(3);
+  return resGO;
+}
+
+int
+cl_r4k::ld_px_irr(t_mem code)
+{
+  switch (code & 0x30)
+    {
+    case 0x00: cPW.W(cIRR->get()); break;
+    case 0x10: cPX.W(cIRR->get()); break;
+    case 0x20: cPY.W(cIRR->get()); break;
+    case 0x30: cPZ.W(cIRR->get()); break;
+    }
+  tick(3);
+  return resGO;
+}
+
+int
+cl_r4k::ld_irr_px(t_mem code)
+{
+  switch (code & 0x30)
+    {
+    case 0x00: destIRR()->W(rPW); break;
+    case 0x10: destIRR()->W(rPX); break;
+    case 0x20: destIRR()->W(rPY); break;
+    case 0x30: destIRR()->W(rPZ); break;
+    }
+  tick(3);
+  return resGO;
+}
+
+int
+cl_r4k::LD_iSP_HL_IRR(t_mem code)
+{
+  u16_t a= rSP + rHL;
+  u32_t v= cIRR->get();
+  mem->write(a++, v); v>>= 8;
+  mem->write(a++, v); v>>= 8;
+  mem->write(a++, v); v>>= 8;
+  mem->write(a  , v);
+  vc.wr+= 4;
+  tick5p1(17);
+  return resGO;
+}
+
+int
+cl_r4k::EXP(t_mem code)
+{
+  u32_t temp;
+  temp= rPW; cPW.W(raPW); caPW.W(temp);
+  temp= rPX; cPX.W(raPX); caPX.W(temp);
+  temp= rPY; cPY.W(raPY); caPY.W(temp);
+  temp= rPZ; cPZ.W(raPZ); caPZ.W(temp);
+  tick(3);
+  return resGO;
+}
+
+int
+cl_r4k::LD_HTR_A(t_mem code)
+{
+  cHTR.W(rA);
+  tick(3);
+  return resGO;
+}
+
+int
+cl_r4k::LD_A_HTR(t_mem code)
+{
+  cA.W(rHTR);
+  tick(3);
+  return resGO;
+}
+
+int
+cl_r4k::LD_BC_HL(t_mem code)
+{
+  destBC().W(rHL);
+  tick(1);
+  return resGO;
+}
+
+int
+cl_r4k::ld32_imn(u32_t op)
+{
+  u16_t a= fetch();
+  a+= 256*fetch();
+  rwas->write(a++, op); op>>= 8;
+  rwas->write(a++, op); op>>= 8;
+  rwas->write(a++, op); op>>= 8;
+  rwas->write(a  , op);
+  vc.wr+= 4;
+  tick(18);
+  return resGO;
+}
+
+int
+cl_r4k::ld_r32_imn(class cl_cell32 &dest)
+{
+  u16_t a= fetch();
+  a+= 256*fetch();
+  u32_t v= 0;
+  u8_t b;
+  b= rwas->read(a++); v|= b<<0;
+  b= rwas->read(a++); v|= b<<8;
+  b= rwas->read(a++); v|= b<<16;
+  b= rwas->read(a  ); v|= b<<24;
+  dest.write(v);
+  vc.rd+= 4;
+  tick(14);
+  return resGO;
+}
+
+int
+cl_r4k::ld_hl_ipsd(u32_t ps)
+{
+  u8_t d= fetch();
+  u32_t a= px8se(ps, d);
+  u8_t h, l;
+  l= mem->pxread(a);
+  a= px8se(ps, d+1);
+  h= mem->pxread(a);
+  destHL().W(h*256+l);
+  vc.rd+= 2;
+  tick5p1(8);
+  return resGO;
+}
+
+int
+cl_r4k::ld_ipsd_hl(u32_t ps)
+{
+  u8_t d= fetch();
+  u32_t a= px8se(ps, d);
+  mem->pxwrite(a, rHL);
+  a= px8se(ps, d+1);
+  mem->pxwrite(a, rHL>>8);
+  vc.wr+= 2;
+  tick5p1(10);
+  return resGO;
+}
+
+int
+cl_r4k::LD_imn_JK(t_mem code)
+{
+  u16_t a= fetch();
+  a+= fetch()*256;
+  rwas->write(a, rK);
+  a++;
+  rwas->write(a, rJ);
+  vc.wr+= 2;
+  tick(12);
+  return resGO;
+}
+
+int
+cl_r4k::LD_JK_imn(t_mem code)
+{
+  u16_t a= fetch(), v;
+  a+= fetch()*256;
+  v= rwas->read(a);
+  v+= rwas->read(++a)*256;
+  destJK().W(v);
+  vc.rd+= 2;
+  tick(10);
+  return resGO;
+}
+
+int
+cl_r4k::ld_a_ipshl(u32_t ps)
+{
+  u32_t a= px16se(ps, rHL);
+  u8_t v= mem->pxread(a);
+  vc.rd++;
+  destA().W(v);
+  tick5p1(5);
+  return resGO;
+}
+
+int
+cl_r4k::ld_ipshl_a(u32_t ps)
+{
+  u32_t a= px16se(ps, rHL);
+  mem->pxwrite(a, rA);
+  vc.wr++;
+  tick5p1(6);
+  return resGO;
+}
+
+int
+cl_r4k::ld_a_ipsd(u32_t ps)
+{
+  u8_t d= fetch();
+  u32_t a= px8se(ps, d);
+  u8_t v= mem->pxread(a);
+  vc.rd++;
+  destA().W(v);
+  tick5p1(6);
+  return resGO;
+}
+
+int
+cl_r4k::ld_ipsd_a(u32_t ps)
+{
+  u8_t d= fetch();
+  u32_t a= px8se(ps, d);
+  mem->pxwrite(a, rA);
+  vc.wr++;
+  tick5p1(7);
+  return resGO;
+}
+
+int
+cl_r4k::LD_LXPC_HL(t_mem code)
+{
+  LXPC->W(rHL);
+  atomic= true;
+  tick(1);
+  return resGO;
+}
+
+int
+cl_r4k::LD_HL_LXPC(t_mem code)
+{
+  destHL().W(rXPC);
+  atomic= true;
+  tick(1);
+  return resGO;
+}
+
+int
+cl_r4k::LD_BCDE_d(t_mem code)
+{
+  i8_t d= fetch();
+  i32_t v;
+  v= d;
+  destBCDE().W(v);
+  tick(3);
+  return resGO;
+}
+
+int
+cl_r4k::LD_JKHL_d(t_mem code)
+{
+  i8_t d= fetch();
+  i32_t v;
+  v= d;
+  destJKHL().W(v);
+  tick(3);
+  return resGO;
+}
+
+int
+cl_r4k::LD_JK_mn(t_mem code)
+{
+  u16_t v= fetch();
+  v+= fetch()*256;
+  destJK().W(v);
+  tick(5);
+  return resGO;
+}
+
+int
+cl_r4k::LD_DE_HL(t_mem code)
+{
+  destDE().W(rHL);
+  tick(1);
+  return resGO;
+}
+
+int
+cl_r4k::EX_BC_HL(t_mem code)
+{
+  class cl_cell16 &hl= destHL();
+  u16_t t;
+  t= rBC;
+  cBC.W(hl.read());
+  hl.W(t);
+  tick5p12(1);
+  return resGO;
+}
+
+int
+cl_r4k::EX_JKHL_BCDE(t_mem code)
+{
+  u32_t t;
+  t= rJKHL;
+  cJKHL.W(rBCDE);
+  cBCDE.W(t);
+  tick(1);
+  return resGO;
+}
+
+int
+cl_r4k::EX_JK_HL(t_mem code)
+{
+  class cl_cell16 &hl= destHL();
+  u16_t t;
+  t= rJK;
+  cJK.W(hl.read());
+  hl.W(t);
+  tick(1);
+  return resGO;
+}
+
+int
+cl_r4k::CLR_HL(t_mem code)
+{
+  destHL().W(0);
+  tick(1);
+  return resGO;
+}
+
+int
+cl_r4k::LD_IRR_iSP_HL(t_mem code)
+{
+  u32_t v;
+  u16_t a= rSP+rHL;
+  v= rom->read(a++);
+  v+= rom->read(a++)*256;
+  v+= rom->read(a++)*256*256;
+  v+= rom->read(a)*256*256*256;
+  destIRR()->W(v);
+  tick5p1(13);
+  return resGO;
+}
+
+int
+cl_r4k::ldl_pd_ispn(class cl_cell32 &pd)
+{
+  u16_t a= rSP+fetch();
+  u16_t v= rom->read(a++);
+  v+= rom->read(a)*256;
+  vc.rd+= 2;
+  pd.W(0xffff0000 + v);
+  tick5p1(10);
+  return resGO;
+}
+
+int
+cl_r4k::ld_pd_ispn(class cl_cell32 &pd)
+{
+  u16_t a= rSP+fetch();
+  u32_t v= rom->read(a++);
+  v+= rom->read(a++)*256;
+  v+= rom->read(a++)*256*256;
+  v+= rom->read(a++)*256*256*256;
+  vc.rd+= 4;
+  pd.W(v);
+  tick5p1(14);
+  return resGO;
+}
+
+int
+cl_r4k::ld_ispn_ps(u32_t ps)
+{
+  u16_t a= rSP + fetch();
+  rom->write(a++, ps);
+  rom->write(a++, ps>>8);
+  rom->write(a++, ps>>16);
+  rom->write(a  , ps>>24);
+  vc.wr+= 4;
+  tick5p1(18);
+  return resGO;
+}
+
+int
+cl_r4k::ld_hl_ipsbc(u32_t ps)
+{
+  u16_t v;
+  u32_t a= px16(ps, rBC);
+  v= mem->pxread(a);
+  a= px16(ps, rBC+1);
+  v+= mem->pxread(a)*256;
+  vc.rd+= 2;
+  destHL().W(v);
+  tick5p1(9);
+  return resGO;
+}
+
+int
+cl_r4k::ld_ipdbc_hl(u32_t pd)
+{
+  u32_t a= px16(pd, rBC);
+  mem->pxwrite(a, rHL);
+  a= px16(pd, rBC+1);
+  mem->pxwrite(a, rHL>>8);
+  vc.wr+= 2;
+  tick5p1(11);
+  return resGO;
+}
+
+int
+cl_r4k::ld_pd_klmn(class cl_cell32 &pd)
+{
+  u32_t v= fetch();
+  v+= fetch()<<8;
+  v+= fetch()<<16;
+  v+= fetch()<<24;
+  pd.W(v);
+  tick(11);
+  return resGO;
+}
+
+int
+cl_r4k::ldl_pd_mn(class cl_cell32 &pd)
+{
+  u32_t v= fetch();
+  v+= fetch()<<8;
+  pd.W(0xffff+v);
+  tick(7);
+  return resGO;
+}
+
+int
+cl_r4k::EX_aBC_HL(t_mem code)
+{
+  class cl_cell16 &hl= destHL();
+  u16_t t;
+  t= raBC;
+  caBC.W(hl.read());
+  hl.W(t);
+  tick(3);
+  return resGO;
+}
+
+int
+cl_r4k::EX_aJK_HL(t_mem code)
+{
+  class cl_cell16 &hl= destHL();
+  u16_t t;
+  t= raJK;
+  caJK.W(hl.read());
+  hl.W(t);
+  tick(3);
+  return resGO;
+}
+
+int
+cl_r4k::copy(int dir)
+{
+  u8_t v;
+  do
+    {
+      v= mem->phread(rPX);
+      mem->phwrite(rPY, v);
+      vc.rd++;
+      vc.wr++;
+      tick(7);
+      cPX.W(rPX+dir);
+      cPY.W(rPY+dir);
+      cBC.W(rBC-1);
+    }
+  while (rBC);
+  tick(5);
+  return resGO;
+}
+
+int
+cl_r4k::pop_pd(class cl_cell32 &pd)
+{
+  u16_t a= rSP;
+  u32_t v;
+  v= rom->read(a++);
+  v+= rom->read(a++)>>8;
+  v+= rom->read(a++)>>16;
+  v+= rom->read(a++)>>24;
+  vc.rd+= 4;
+  pd.W(v);
+  cSP.W(a);
+  tick(12);
+  return resGO;
+}
+
+int
+cl_r4k::push_ps(u32_t ps)
+{
+  u16_t a= rSP;
+  rom->write(--a, ps>>24);
+  rom->write(--a, ps>>16);
+  rom->write(--a, ps>>8);
+  rom->write(--a, ps);
+  vc.wr+= 4;
+  cSP.W(a);
+  tick5p1(17);
+  return resGO; 
+}
+
+int
+cl_r4k::LD_HL_iSPHL(t_mem code)
+{
+  u16_t a= rSP + rHL;
+  u16_t v= rom->read(a++);
+  v+= rom->read(a)*256;
+  destHL().W(v);
+  tick5p1(9);
+  return resGO;
+}
+
+
+/* End of rxk.src/imove.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/inst.cc sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/inst.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/inst.cc	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/inst.cc	2021-09-13 16:16:27.000000000 +0000
@@ -0,0 +1,312 @@
+/*
+ * Simulator of microcontrollers (inst.cc)
+ *
+ * Copyright (C) 2020,2021 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+
+#include "rxkcl.h"
+#include "r3kacl.h"
+#include "r4kcl.h"
+
+
+int
+cl_rxk::ALTD(t_mem code)
+{
+  altd= prefix= true;
+  tick(1);
+  return resGO;
+}
+
+int
+cl_rxk::IOI(t_mem code)
+{
+  prefix= true;
+  rwas= ioi;
+  tick(1);
+  return resGO;
+}
+
+int
+cl_rxk::IOE(t_mem code)
+{
+  prefix= true;
+  rwas= ioe;
+  tick(1);
+  return resGO;
+}
+
+int
+cl_rxk::NOP(t_mem code)
+{
+  tick(1);
+  return resGO;
+}
+
+int
+cl_rxk::SCF(t_mem code)
+{
+  destF().W(destF().R() | flagC);
+  tick(1);
+  return resGO;
+}
+
+int
+cl_rxk::CCF(t_mem code)
+{
+  destF().W(destF().R() ^ flagC);
+  tick(1);
+  return resGO;
+}
+
+int
+cl_rxk::EXX(t_mem code)
+{
+  u16_t t;
+  t= rBC;
+  cBC.W(raBC);
+  caBC.W(t);
+
+  t= rDE;
+  cBC.W(raDE);
+  caDE.W(t);
+  
+  t= rHL;
+  cBC.W(raHL);
+  caHL.W(t);
+  
+  tick(1);
+  return resGO;
+}
+
+int
+cl_rxk::ipset(u8_t n)
+{
+  u8_t v= rIP << 2;
+  v|= (n&3);
+  cIP.W(v);
+  tick(3);
+  return resGO;
+}
+
+int
+cl_rxk::IPRES(t_mem code)
+{
+  u8_t v= (rIP >> 2) & 0x3f;
+  u8_t l= rIP << 6;
+  cIP.W(v|l);
+  tick(3);
+  return resGO;
+}
+
+
+int
+cl_rxk::PAGE_CB(t_mem code)
+{
+  u8_t x, y, z;
+  code= fetch();
+  x= code>>6;
+  y= (code>>3)&7;
+  z= code&7;
+  switch (x)
+    {
+    case 0:
+      if (z == 6)
+	{
+	  vc.rd++;
+	  vc.wr++;
+	  tick(6);
+	}
+      switch (y)
+	{
+	case 0: return rlc (*destR(z), rR(z));
+	case 1: return rrc (*destR(z), rR(z));
+	case 2: return rl  (*destR(z), rR(z));
+	case 3: return rr  (*destR(z), rR(z));
+	case 4: return sla8(*destR(z), rR(z));
+	case 5: return sra8(*destR(z), rR(z));
+	case 6: return resINV_INST;
+	case 7: return srl8(*destR(z), rR(z));
+	}
+      break;
+    case 1: // BIT y,r
+      if (z == 6)
+	return bit_iHL(y);
+      return bit_r(y, rR(z));
+      break;
+    case 2: // RES y,r
+      if (z == 6)
+	return res_iHL(y);
+      return res_r(y, *destR(z), rR(z));
+      break;
+    case 3: // SET y,r
+      if (z == 6)
+	return set_iHL(y);
+      return set_r(y, *destR(z), rR(z));
+      break;
+    }
+  return resGO;
+}
+
+int
+cl_rxk::PAGE_DD_CB(t_mem code)
+{
+  u8_t x, y, z, d;
+  d= fetch();
+  class cl_cell8 &dest= dest8iIRd(d);
+  code= fetch();
+  x= code>>6;
+  y= (code>>3)&7;
+  z= code&7;
+  if (z != 6)
+    return resINV_INST;
+  switch (x)
+    {
+    case 0:
+      switch (y)
+	{
+	case 0: return rlc (dest, dest.get());
+	case 1: return rrc (dest, dest.get());
+	case 2: return rl  (dest, dest.get());
+	case 3: return rr  (dest, dest.get());
+	case 4: return sla8(dest, dest.get());
+	case 5: return sra8(dest, dest.get());
+	case 6: return resINV_INST;
+	case 7: return srl8(dest, dest.get());
+	}
+      break;
+    case 1:
+      return bit_iIRd(y, d);
+      break;
+    case 2:
+      return res_iIRd(y, d);
+      break;
+    case 3:
+      return set_iIRd(y, d);
+      break;
+    }
+  return resGO;
+}
+
+
+/*
+ *                                                    R3000A,R4000,R5000
+ */
+
+int
+cl_r3ka::SETUSR(t_mem code)
+{
+  u8_t v= rSU << 2;
+  v|= 1;
+  atomic= true;
+  tick(3);
+  return resGO;
+}
+
+int
+cl_r3ka::SURES(t_mem code)
+{
+  u8_t v= ((rSU >> 2) /*& 0x3f*/) | ((rSU << 6) /*& 0xc0*/);
+  cSU.W(v);
+  atomic= true;
+  tick(3);
+  return resGO;
+}
+
+int
+cl_r3ka::RDMODE(t_mem code)
+{
+  u8_t v= rF & ~flagC;
+  if (rSU & 1) v|= flagC;
+  cF.W(v);
+  tick(3);
+  return resGO;
+}
+
+int
+cl_r3ka::instruction_5b(t_mem code)
+{
+  ld_r_g(destE(), rE);
+  if (!altd)
+    {
+      if ((edmr&1) && (rSU&1))
+	{
+	  // TODO: set System Violation interrupt flag
+	}
+    }
+  return resGO;
+}
+
+int
+cl_r4k::SETUSRP(t_mem code)
+{
+  u8_t n, m;
+  rSU&= 0xfc;
+  rSU|= 0x01;
+  cSU.W(rSU);
+  n= fetch();
+  m= fetch();
+  u16_t a= rSP;
+  rom->write(--a, m);
+  rom->write(--a, n);
+  cSP.W(rSP);
+  tick5p1(14);
+  atomic= true;
+  return resGO;
+}
+
+int
+cl_r4k::SETSYSP(t_mem code)
+{
+  cSU.W((rSU>>2) | (rSU<<6));
+  u8_t tl, th, n, m;
+  n= fetch();
+  m= fetch();
+  u16_t a= rSP;
+  tl= rom->read(a++);
+  th= rom->read(a++);
+  vc.rd+= 2;
+  cSP.W(rSP);
+  atomic= true;
+  if ((th!=m) && (tl!=n))
+    return resERROR;
+  return resGO;
+}
+
+int
+cl_r4k::convc_pp(class cl_cell32 &pp)
+{
+  pp.W(mem->log2phy(pp.read()));
+  tick(7);
+  return resGO;
+}
+
+int
+cl_r4k::convd_pp(class cl_cell32 &pp)
+{
+  pp.W(mem->log2phy(pp.read()));
+  tick(7);
+  return resGO;
+}
+
+
+/* End of m6800.src/inst.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/Makefile.in sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/Makefile.in
--- sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/Makefile.in	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/Makefile.in	2022-01-09 14:02:03.000000000 +0000
@@ -0,0 +1,188 @@
+#
+# uCsim rxk.src/Makefile
+#
+# (c) Drotos Daniel, Talker Bt. 2020,2021
+#
+
+# tool name
+TN		= rxk
+
+STARTYEAR	= 1997
+
+SHELL		= /bin/sh
+CXX		= @CXX@
+CPP		= @CPP@
+CXXCPP		= @CXXCPP@
+RANLIB		= @RANLIB@
+INSTALL		= @INSTALL@
+STRIP		= @STRIP@
+MAKEDEP         = @MAKEDEP@
+
+top_builddir	= @top_builddir@
+top_srcdir	= @top_srcdir@
+
+transform	= @program_transform_name@
+
+DEFS            = $(subs -DHAVE_CONFIG_H,,@DEFS@)
+CPPFLAGS        = @CPPFLAGS@ -I$(srcdir) -I$(top_srcdir) -I$(top_builddir) \
+		  -I$(top_srcdir)/cmd.src -I$(top_srcdir)/sim.src \
+		  -I$(top_srcdir)/gui.src
+CFLAGS          = @WALL_FLAG@ @CFLAGS@
+CXXFLAGS        = @WALL_FLAG@ @CXXFLAGS@
+LDFLAGS         = @LDFLAGS@
+PICOPT		= @PICOPT@
+SHAREDLIB	= @SHAREDLIB@
+EXEEXT		= @EXEEXT@
+
+LIBS		= -L$(top_builddir) -lsim -lucsimutil -lguiucsim -lcmd -lsim @LIBS@
+DL		= @DL@
+dl_ok		= @dl_ok@
+
+prefix          = @prefix@
+exec_prefix     = @exec_prefix@
+bindir          = @bindir@
+libdir          = @libdir@
+datadir         = @datadir@
+datarootdir     = @datarootdir@
+includedir      = @includedir@
+mandir          = @mandir@
+man1dir         = $(mandir)/man1
+man2dir         = $(mandir)/man2
+infodir         = @infodir@
+srcdir          = @srcdir@
+VPATH           = @srcdir@
+
+OBJECTS_SHARED	= sim$(TN).o $(TN).o rmem.o \
+		  glob.o gp0m3.o gp0m4.o \
+		  gpedm3.o gpedm3a.o gpedm4.o \
+		  gpddm3.o gpddm4.o \
+		  inst.o ialu.o ibranch.o imove.o \
+		  r2k.o r3k.o r3ka.o r4k.o r5k.o r6k.o \
+		  r4kwrap.o ddwrap.o edwrap.o 7fwrap.o
+
+OBJECTS_EXE	= s$(TN).o
+OBJECTS		= $(OBJECTS_SHARED) $(OBJECTS_EXE)
+
+# short/long exe and lib name
+SEN		= s$(TN)$(EXEEXT)
+LEN		= ucsim_$(TN)$(EXEEXT)
+SONAME		= libucsim_$(TN).so
+
+enable_dlso	= @enable_dlso@
+dlso_ok		= @dlso_ok@
+
+RXKASM		=
+TEST_OBJ	= 
+
+
+# Compiling entire program or any subproject
+# ------------------------------------------
+all: checkconf otherlibs $(TN).src
+
+
+# Compiling and installing everything and runing test
+# ---------------------------------------------------
+install: all installdirs install_shared_lib
+	$(INSTALL) $(SEN) $(DESTDIR)$(bindir)/$(SEN)
+	$(STRIP) $(DESTDIR)$(bindir)/$(SEN)
+	$(INSTALL) $(LEN) $(DESTDIR)$(bindir)/$(LEN)
+	$(STRIP) $(DESTDIR)$(bindir)/$(LEN)
+
+
+# Deleting all the installed files
+# --------------------------------
+uninstall:
+	rm -f $(DESTDIR)$(bindir)/$(SEN)
+	rm -f $(DESTDIR)$(bindir)/$(LEN)
+	rm -f $(DESTDIR)$(libdir)/$(SONAME)
+
+
+# Performing self-test
+# --------------------
+check: $(TEST_OBJ)
+
+.PHONY:	test baseline
+test:
+	@$(MAKE) --no-print-directory -C test
+
+baseline:
+	@$(MAKE) --no-print-directory -C test baseline
+
+
+# Performing installation test
+# ----------------------------
+installcheck:
+
+
+# Creating installation directories
+# ---------------------------------
+installdirs:
+	test -d $(DESTDIR)$(bindir) || $(INSTALL) -d $(DESTDIR)$(bindir)
+
+
+# Creating dependencies
+# ---------------------
+dep: Makefile.dep
+
+Makefile.dep: $(srcdir)/*.cc $(srcdir)/*.h
+	$(MAKEDEP) $(CPPFLAGS) $(filter %.cc,$^) >Makefile.dep
+
+-include Makefile.dep
+include $(srcdir)/clean.mk
+
+# My rules
+# --------
+.SUFFIXES: .asm .hex
+
+$(TN).src: $(SEN) $(LEN) shared_lib
+
+$(SEN): $(OBJECTS) $(top_builddir)/libcmd.a $(top_builddir)/libguiucsim.a $(top_builddir)/libsim.a $(top_builddir)/libucsimutil.a
+	$(CXX) $(CXXFLAGS) $(LDFLAGS) $(OBJECTS) $(LIBS) -o $@
+
+$(LEN): $(SEN)
+	cp $< $@
+
+ifeq ($(dlso_ok),yes)
+shared_lib: $(top_builddir)/$(SONAME)
+install_shared_lib: shared_lib
+	test -d $(DESTDIR)$(libdir) || $(INSTALL) -d $(DESTDIR)$(libdir)
+	$(INSTALL) $(top_builddir)/$(SONAME) $(DESTDIR)$(libdir)/$(SONAME)
+else
+shared_lib:
+	@$(top_srcdir)/mkecho $(top_builddir) "No $(TN) shared lib made."
+	@$(top_srcdir)/mkecho $(top_builddir) "(SHAREDLIB="$(SHAREDLIB)",dl_ok="$(dl_ok)",enable_dlso="$(enable_dlso)")"
+install_shared_lib:
+endif
+
+$(top_builddir)/$(SONAME): $(OBJECTS_SHARED)
+	$(CXX) -shared $(LDFLAGS) $(OBJECTS_SHARED) -o $@
+
+otherlibs: $(top_builddir)/libcmd.a $(top_builddir)/libguiucsim.a $(top_builddir)/libsim.a $(top_builddir)/libucsimutil.a
+
+$(top_builddir)/libcmd.a:
+	$(MAKE) -C $(top_builddir)/cmd.src all
+
+$(top_builddir)/libguiucsim.a:
+	$(MAKE) -C $(top_builddir)/gui.src checkconf ucsim_lib
+
+$(top_builddir)/libsim.a:
+	$(MAKE) -C $(top_builddir)/sim.src all
+
+$(top_builddir)/libucsimutil.a:
+	$(MAKE) -C $(top_builddir) -f main.mk
+
+.cc.o:
+	$(CXX) $(CXXFLAGS) $(PICOPT) $(CPPFLAGS) $(TARGET_ARCH) -c $< -o $@
+
+.asm.hex:
+	$(RXKASM) -l $< -o $@ -e $<.lst
+
+
+# Remaking configuration
+# ----------------------
+checkconf:
+	@if [ -f $(top_builddir)/devel ]; then\
+	  $(MAKE) -C $(top_builddir) -f conf.mk srcdir="$(srcdir)" top_builddir="$(top_builddir)" freshconf;\
+	fi
+
+# End of rxk.src/Makefile.in
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/r2k.cc sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/r2k.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/r2k.cc	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/r2k.cc	2021-07-16 14:31:13.000000000 +0000
@@ -0,0 +1,43 @@
+/*
+ * Simulator of microcontrollers (r2k.cc)
+ *
+ * Copyright (C) 2020,2021 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#include "r2kcl.h"
+
+
+cl_r2k::cl_r2k(class cl_sim *asim):
+  cl_rxk(asim)
+{
+}
+
+const char *
+cl_r2k::id_string(void)
+{
+  return "R2K";
+}
+
+
+/* End of rxk.src/r2k.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/r2kcl.h sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/r2kcl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/r2kcl.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/r2kcl.h	2021-07-16 14:31:13.000000000 +0000
@@ -0,0 +1,44 @@
+/*
+ * Simulator of microcontrollers (r2kcl.h)
+ *
+ * Copyright (C) 2020,2021 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef R2KCL_HEADER
+#define R2KCL_HEADER
+
+#include "rxkcl.h"
+
+
+class cl_r2k: public cl_rxk
+{
+ public:
+  cl_r2k(class cl_sim *asim);
+  virtual const char *id_string(void);
+};
+
+
+#endif
+
+/* End of rxk.src/r2kcl.h */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/r3ka.cc sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/r3ka.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/r3ka.cc	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/r3ka.cc	2021-07-31 15:17:57.000000000 +0000
@@ -0,0 +1,229 @@
+/*
+ * Simulator of microcontrollers (r3ka.cc)
+ *
+ * Copyright (C) 2020,2021 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#include 
+
+#include "appcl.h"
+
+#include "glob.h"
+#include "gp0m3.h"
+#include "gpddm3.h"
+#include "gpedm3.h"
+#include "gpedm3a.h"
+
+#include "r3kacl.h"
+
+
+cl_r3ka::cl_r3ka(class cl_sim *asim):
+  cl_r3k(asim)
+{
+}
+
+int
+cl_r3ka::init(void)
+{
+  cl_r3k::init();
+#define RCV(R) reg_cell_var(&c ## R , &r ## R , "" #R "" , "CPU register " #R "")
+  RCV(SU);
+#undef RCV
+  return 0;
+}
+
+const char *
+cl_r3ka::id_string(void)
+{
+  return "R3KA";
+}
+
+void
+cl_r3ka::reset(void)
+{
+  cl_r3k::reset();
+  edmr= 0;
+  //mode3k();  
+}
+
+struct dis_entry *
+cl_r3ka::dis_entry(t_addr addr)
+{
+  u8_t code= rom->get(addr);
+  int i;
+  struct dis_entry *dt;
+
+  if (code == 0xed)
+    {
+      code= rom->get(addr+1);
+
+      dt= disass_pedm3;
+      i= 0;
+      while (((code & dt[i].mask) != dt[i].code) &&
+	     dt[i].mnemonic)
+	i++;
+      if (dt[i].mnemonic != NULL)
+	return &dt[i];
+
+      dt= disass_pedm3a;
+      i= 0;
+      while (((code & dt[i].mask) != dt[i].code) &&
+	     dt[i].mnemonic)
+	i++;
+      if (dt[i].mnemonic != NULL)
+	return &dt[i];
+
+      return NULL;
+    }
+  if ((code & 0xdd) == 0xdd)
+    {
+      if (code == 0xdd)
+	{
+	  cIR= &cIX;
+	}
+      else
+	{
+	  cIR= &cIY;
+	}
+      code= rom->get(addr+1);
+      dt= disass_pddm3;
+      i= 0;
+      while (((code & dt[i].mask) != dt[i].code) &&
+	     dt[i].mnemonic)
+	i++;
+      if (dt[i].mnemonic != NULL)
+	return &dt[i];
+      return NULL;
+    }
+  
+  dt= disass_rxk;
+  i= 0;
+  while (((code & dt[i].mask) != dt[i].code) &&
+	 dt[i].mnemonic)
+    i++;
+  if (dt[i].mnemonic != NULL)
+    return &dt[i];
+
+  dt= disass_p0m3;
+  i= 0;
+  while (((code & dt[i].mask) != dt[i].code) &&
+	 dt[i].mnemonic)
+    i++;
+  if (dt[i].mnemonic != NULL)
+    return &dt[i];
+  
+  return &dt[i];
+}
+
+char *
+cl_r3ka::disassc(t_addr addr, chars *comment)
+{
+  t_mem code= rom->get(addr);
+  if (code == 0x5b)
+    {
+      if (rom->get(addr-1) != 0x76)
+	return strdup("IDET");
+    }
+  return cl_r3k::disassc(addr, comment);
+}
+
+void
+cl_r3ka::print_regs(class cl_console_base *con)
+{
+  if (jaj)
+    {
+      con->dd_color("answer");
+      con->dd_printf("SZ-A-PNC  Flags= 0x%02x %3d %c  ",
+		     rF, rF, isprint(rF)?rF:'.');
+      con->dd_printf("A= 0x%02x %3d %c\n",
+		     rA, rA, isprint(rA)?rA:'.');
+      con->dd_printf("%c%c-%c-%c%c%c\n",
+		     (rF&flagS)?'1':'0',
+		     (rF&flagZ)?'1':'0',
+		     'x',//(rF&flagA)?'1':'0',
+		     (rF&flagV)?'1':'0',
+		     'x',//(rF&BIT_N)?'1':'0',
+		     (rF&flagC)?'1':'0');
+      con->dd_printf("BC= 0x%04x [BC]= %02x %3d %c  ",
+		     rBC, rom->get(rBC), rom->get(rBC),
+		     isprint(rom->get(rBC))?rom->get(rBC):'.');
+      con->dd_printf("DE= 0x%04x [DE]= %02x %3d %c  ",
+		     rDE, rom->get(rDE), rom->get(rDE),
+		     isprint(rom->get(rDE))?rom->get(rDE):'.');
+      con->dd_printf("HL= 0x%04x [HL]= %02x %3d %c\n",
+		     rHL, rom->get(rHL), rom->get(rHL),
+		     isprint(rom->get(rHL))?rom->get(rHL):'.');
+      con->dd_printf("IX= 0x%04x [IX]= %02x %3d %c  ",
+		     rIX, rom->get(rIX), rom->get(rIX),
+		     isprint(rom->get(rIX))?rom->get(rIX):'.');
+      con->dd_printf("IY= 0x%04x [IY]= %02x %3d %c  ",
+		     rIY, rom->get(rIY), rom->get(rIY),
+		     isprint(rom->get(rIY))?rom->get(rIY):'.');
+      con->dd_printf("SP= 0x%04x [SP]= %02x %3d %c\n",
+		     rSP, rom->get(rSP), rom->get(rSP),
+		     isprint(rom->get(rSP))?rom->get(rSP):'.');
+      //con->dd_printf("SP limit= 0x%04x\n", AU(sp_limit));
+      print_disass(PC, con);
+      return;
+    }
+  con->dd_color("answer");
+  con->dd_printf("A= 0x%02x %3d %c  ",
+                 rA, rA, isprint(rA)?rA:'.');
+  con->dd_printf("F= "); con->print_bin(rF, 8);
+  con->dd_printf(" 0x%02x %3d %c", rF, rF, isprint(rF)?rF:'.');
+  con->dd_printf("\n");
+  con->dd_printf("                  SZxxxVxC\n");
+
+  con->dd_printf("XPC= 0x%02x IP= 0x%02x IIR= 0x%02x EIR= 0x%02x SU= 0x%02x\n",
+		 mem->get_xpc(), rIP, rIIR, rEIR, rSU);
+  
+  con->dd_printf("BC= ");
+  rom->dump(0, rBC, rBC+7, 8, con);
+  con->dd_color("answer");
+  con->dd_printf("DE= ");
+  rom->dump(0, rDE, rDE+7, 8, con);
+  con->dd_color("answer");
+  con->dd_printf("HL= ");
+  rom->dump(0, rHL, rHL+7, 8, con);
+  con->dd_color("answer");
+  con->dd_printf("IX= ");
+  rom->dump(0, rIX, rIX+7, 8, con);
+  con->dd_color("answer");
+  con->dd_printf("IY= ");
+  rom->dump(0, rIY, rIY+7, 8, con);
+  con->dd_color("answer");
+  con->dd_printf("SP= ");
+  rom->dump(0, rSP, rSP+7, 8, con);
+  con->dd_color("answer");
+
+  con->dd_printf("aAF= 0x%02x-0x%02x  ", raA, raF);
+  con->dd_printf("aBC= 0x%02x-0x%02x  ", raB, raC);
+  con->dd_printf("aDE= 0x%02x-0x%02x  ", raD, raE);
+  con->dd_printf("aHL= 0x%02x-0x%02x  ", raH, raL);
+  con->dd_printf("\n");
+  
+  print_disass(PC, con);
+}
+
+/* End of rxk.src/r3ka.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/r3kacl.h sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/r3kacl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/r3kacl.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/r3kacl.h	2021-07-31 15:17:57.000000000 +0000
@@ -0,0 +1,79 @@
+/*
+ * Simulator of microcontrollers (r3kacl.h)
+ *
+ * Copyright (C) 2020,2021 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef R3KACL_HEADER
+#define R3KACL_HEADER
+
+#include "dpedm3a.h"
+
+#include "r3kcl.h"
+
+
+class cl_r3ka: public cl_r3k
+{
+public:
+  u8_t rSU;
+  u8_t edmr;
+  class cl_cell8 cSU;
+public:
+  cl_r3ka(class cl_sim *asim);
+  virtual int init();
+  virtual const char *id_string(void);
+  virtual void reset(void);
+
+  virtual struct dis_entry *dis_entry(t_addr addr);
+  virtual char *disassc(t_addr addr, chars *comment= NULL);
+
+  virtual void print_regs(class cl_console_base *con);
+
+  virtual int LDxSR(int dif);
+  virtual int LSxDR(int dif);
+  virtual int LSxR(int dif);
+  virtual int UMx(bool add);
+  
+  virtual int PUSH_SU(t_mem code);
+  virtual int POP_SU(t_mem code);
+  virtual int SETUSR(t_mem code);
+  virtual int SURES(t_mem code);
+  virtual int RDMODE(t_mem code);
+  virtual int SYSCALL(t_mem code);
+  virtual int LDDSR(t_mem code) { return LDxSR(-1); }
+  virtual int LDISR(t_mem code) { return LDxSR(+1); }
+  virtual int LSDDR(t_mem code) { return LSxDR(-1); }
+  virtual int LSIDR(t_mem code) { return LSxDR(+1); }
+  virtual int LSDR(t_mem code) { return LSxR(-1); }
+  virtual int LSIR(t_mem code) { return LSxR(+1); }
+  virtual int UMA(t_mem code) { return UMx(true); }
+  virtual int UMS(t_mem code) { return UMx(false); }
+
+  virtual int instruction_5b(t_mem code);
+};
+
+
+#endif
+
+/* End of rxk.src/r3kacl.h */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/r3k.cc sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/r3k.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/r3k.cc	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/r3k.cc	2021-07-16 14:31:13.000000000 +0000
@@ -0,0 +1,43 @@
+/*
+ * Simulator of microcontrollers (r3k.cc)
+ *
+ * Copyright (C) 2020,2021 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#include "r3kcl.h"
+
+
+cl_r3k::cl_r3k(class cl_sim *asim):
+  cl_r2k(asim)
+{
+}
+
+const char *
+cl_r3k::id_string(void)
+{
+  return "R3K";
+}
+
+
+/* End of rxk.src/r3k.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/r3kcl.h sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/r3kcl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/r3kcl.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/r3kcl.h	2021-07-16 14:31:13.000000000 +0000
@@ -0,0 +1,44 @@
+/*
+ * Simulator of microcontrollers (r3kcl.h)
+ *
+ * Copyright (C) 2020,2021 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef R3KCL_HEADER
+#define R3KCL_HEADER
+
+#include "r2kcl.h"
+
+
+class cl_r3k: public cl_r2k
+{
+ public:
+  cl_r3k(class cl_sim *asim);
+  virtual const char *id_string(void);
+};
+
+
+#endif
+
+/* End of rxk.src/r3kcl.h */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/r4k.cc sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/r4k.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/r4k.cc	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/r4k.cc	2021-09-01 06:57:19.000000000 +0000
@@ -0,0 +1,943 @@
+/*
+ * Simulator of microcontrollers (r4k.cc)
+ *
+ * Copyright (C) 2020,2021 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#include 
+#include 
+
+#include "globals.h"
+#include "utils.h"
+
+#include "r4kwrap.h"
+#include "7fwrap.h"
+#include "glob.h"
+#include "gp0m3.h"
+#include "gp0m4.h"
+#include "gpddm3.h"
+#include "gpedm3a.h"
+#include "gpddm4.h"
+#include "gpedm3.h"
+#include "gpedm4.h"
+
+#include "r4kcl.h"
+
+
+u32_t
+px8(u32_t px, u8_t offset)
+{
+  bool log= ((px & 0xffff0000) == 0xffff0000);
+  px+= offset;
+  if (log) px|= 0xffff0000;
+  return px;
+}
+
+u32_t
+px8se(u32_t px, u8_t offset)
+{
+  bool log= ((px & 0xffff0000) == 0xffff0000);
+  i32_t o= (i8_t)offset;
+  px+= o;
+  if (log) px|= 0xffff0000;
+  return px;
+}
+
+u32_t
+px16(u32_t px, u16_t offset)
+{
+  bool log= ((px & 0xffff0000) == 0xffff0000);
+  px+= offset;
+  if (log) px|= 0xffff0000;
+  return px;
+}
+
+u32_t
+px16se(u32_t px, u16_t offset)
+{
+  bool log= ((px & 0xffff0000) == 0xffff0000);
+  i32_t o= (i16_t)offset;
+  px+= o;
+  if (log) px|= 0xffff0000;
+  return px;
+}
+
+
+cl_r4k::cl_r4k(class cl_sim *asim):
+  cl_r3ka(asim)
+{
+}
+
+int
+cl_r4k::init(void)
+{
+  cl_r3ka::init();
+#define RCV(R) reg_cell_var(&c ## R , &r ## R , "" #R "" , "CPU register " #R "")
+  RCV(BCDE);
+  RCV(JKHL);
+  RCV(aBCDE);
+  RCV(aJKHL);
+  RCV(J);
+  RCV(K);
+  RCV(JK);
+  RCV(aJ);
+  RCV(aK);
+  RCV(aJK);
+  RCV(PW);
+  RCV(PX);
+  RCV(PY);
+  RCV(PZ);
+  RCV(aPW);
+  RCV(aPX);
+  RCV(aPY);
+  RCV(aPZ);
+  RCV(HTR);
+#undef RCV
+  //mode2k();
+  fill_7f_wrappers(itab_7f);
+
+  LXPC= new cl_cell16(12);
+  reg_cell_var(LXPC, mem->aof_lxpc(),
+  	       "LXPC", "MMU register: LXPC");
+  cpu->register_cell(LXPC);
+  cIRR= &cBCDE;
+  
+  return 0;
+}
+
+const char *
+cl_r4k::id_string(void)
+{
+  return "R4K";
+}
+
+void
+cl_r4k::reset(void)
+{
+  cl_r3ka::reset();
+  //edmr= 0;
+  mode3k();  
+}
+
+void
+cl_r4k::make_cpu_hw(void)
+{
+  add_hw(cpu= new cl_r4k_cpu(this));
+  cpu->init();
+}
+
+static struct dis_entry de7f;
+
+struct dis_entry *
+cl_r4k::dis_entry(t_addr addr)
+{
+  u8_t code= rom->get(addr);
+  int i;
+  struct dis_entry *dt;
+  
+  if (code == 0xed)
+    {
+      code= rom->get(addr+1);
+      
+      dt= disass_pedm3;
+      i= 0;
+      while (((code & dt[i].mask) != dt[i].code) &&
+	     dt[i].mnemonic)
+	i++;
+      if (dt[i].mnemonic != NULL)
+	return &dt[i];
+      
+      dt= disass_pedm3a;
+      i= 0;
+      while (((code & dt[i].mask) != dt[i].code) &&
+	     dt[i].mnemonic)
+	i++;
+      if (dt[i].mnemonic != NULL)
+	return &dt[i];
+      
+      dt= disass_pedm4;
+      i= 0;
+      while (((code & dt[i].mask) != dt[i].code) &&
+	     dt[i].mnemonic)
+	i++;
+      if (dt[i].mnemonic != NULL)
+	return &dt[i];
+      
+      return NULL;
+    }
+  if ((code & 0xdd) == 0xdd)
+    {
+      if (code == 0xdd)
+	{
+	  cIR= &cIX;
+	}
+      else
+	{
+	  cIR= &cIY;
+	}
+      code= rom->get(addr+1);
+      dt= disass_pddm3;
+      i= 0;
+      while (((code & dt[i].mask) != dt[i].code) &&
+	     dt[i].mnemonic)
+	i++;
+      if (dt[i].mnemonic != NULL)
+	return &dt[i];
+      dt= disass_pddm4;
+      i= 0;
+      while (((code & dt[i].mask) != dt[i].code) &&
+	     dt[i].mnemonic)
+	i++;
+      if (dt[i].mnemonic != NULL)
+	return &dt[i];
+      return NULL;
+    }
+
+  if ((code == 0x6d) && (edmr & 0xc0))
+    {
+      // 6d page exists in 4k mode only!
+      return dis_6d_entry(addr);
+    }
+
+  if ((code == 0x7f) && (edmr & 0xc0))
+    {
+      // 7f page is special in 4k mode
+      code= rom->get(addr+1);
+      if ((code <= 0x3f) || (code >= 0xc0))
+	return NULL;
+      if ((code >= 0x40) && (code <= 0x6f))
+	{
+	  if ((code & 0x0f) == 0x06)
+	    return NULL;
+	  if ((code & 0x0f) == 0x0e)
+	    return NULL;
+	}
+      if ((code & 0xf0) == 0x70)
+	{
+	  if ((code == 0x7e) || (code <= 0x77))
+	    return NULL;
+	}
+      // pick from standard page0 table
+      dt= disass_p0m3;
+      i= 0;
+      while (((code & dt[i].mask) != dt[i].code) &&
+	     dt[i].mnemonic)
+	i++;
+      if (dt[i].mnemonic != NULL)
+	{
+	  memcpy(&de7f, &dt[i], sizeof(struct dis_entry));
+	  de7f.length++;
+	  return &de7f;
+	}
+      return NULL;
+    }
+  
+  dt= disass_rxk;
+  i= 0;
+  while (((code & dt[i].mask) != dt[i].code) &&
+	 dt[i].mnemonic)
+    i++;
+  if (dt[i].mnemonic != NULL)
+    return &dt[i];
+
+  if (edmr & 0xc0)
+    {
+      // mode: 4k
+      dt= disass_p0m4;
+      i= 0;
+      while (((code & dt[i].mask) != dt[i].code) &&
+	     dt[i].mnemonic)
+	i++;
+      if (dt[i].mnemonic != NULL)
+	return &dt[i];
+    }
+  else
+    {
+      // mode: 3k
+      dt= disass_p0m3;
+      i= 0;
+      while (((code & dt[i].mask) != dt[i].code) &&
+	     dt[i].mnemonic)
+	i++;
+      if (dt[i].mnemonic != NULL)
+	return &dt[i];
+    }
+  
+  return NULL;
+}
+
+struct dis_entry disass_6d[]= {
+  /* 0 */ {    0,    0, ' ', 0, NULL },
+  /* 1 */ { 0x6d, 0xff, ' ', 2, "LD L,L" },
+  /* 2 */ { 0x7f, 0xff, ' ', 2, "LD A,A" },
+  /* 3 */ {    0,    0, ' ', 0, 0, 0, 0 }
+};
+char mnemo[100];
+
+struct dis_entry *
+cl_r4k::dis_6d_entry(t_addr addr)
+{
+  u8_t h, l, code= rom->get(addr+1);
+  chars op, idx, offset;
+  
+  if (code == 0x6d)
+    return &disass_6d[1];
+  if (code == 0x7f)
+    return &disass_6d[2];
+  
+  h= code >> 4;
+  l= code & 15;
+  if ((l == 0xd) || (l == 0xf))
+    return &disass_6d[3];
+
+  disass_6d[0].length= 2;
+  switch (h&3)
+    {
+    case 0: idx= "PW"; break;
+    case 1: idx= "PX"; break;
+    case 2: idx= "PY"; break;
+    case 3: idx= "PZ"; break;
+    }
+  switch (h&0xc)
+    {
+    case 0x0:
+      if (l<=3)
+	op= "BC";
+      else
+	op= "PW";
+      break;
+    case 0x4:
+      if (l<=3)
+	op= "DE";
+      else
+	op= "PX";
+      break;
+    case 0x8: if (l<=3) op= "IX"; else op= "PY"; break;
+    case 0xc: if (l<=3) op= "IY"; else op= "PZ"; break;
+    }
+  switch (l&6)
+    {
+    case 0:
+      {
+	u8_t d= rom->get(addr+2);
+	disass_6d[0].length= 3;
+	if (l&1)
+	  offset.format("+%u", d);
+	else
+	  {
+	    i8_t io= d;
+	    //offset= (io<0)?"-":"+";
+	    offset.format("%+d", io);
+	  }
+	break;
+      }
+    case 2: offset= "+HL"; break;
+    case 3: offset= (l&1)?"IY":"IX"; break;
+    case 6: offset= "";
+    }
+
+  chars mn= "LD ";
+  if (l&4)
+    {
+      mn+= op+","+idx+offset;
+    }
+  else
+    {
+      if (l&1)
+	{
+	  mn+= "(";
+	  mn+= idx+offset+"),"+op;
+	}
+      else
+	{
+	  mn+= op+",("+idx+offset+")";
+	}
+    }
+  strcpy(mnemo, mn.c_str());
+  disass_6d[0].mnemonic= mnemo;
+  
+  return &disass_6d[0];
+}
+
+void
+cl_r4k::disass_irr(chars *work, bool dd)
+{
+  work->appendf("%s", dd?"BCDE":"JKHL");
+}
+
+void
+cl_r4k::disass_irrl(chars *work, bool dd)
+{
+  work->appendf("%s", dd?"DE":"HL");
+}
+
+void
+cl_r4k::select_IRR(bool dd)
+{
+  cIRR = dd?&cBCDE :&cJKHL;
+  caIRR= dd?&caBCDE:&caJKHL;
+}
+
+void
+cl_r4k::print_regs(class cl_console_base *con)
+{
+  con->dd_color("answer");
+  con->dd_printf("A= 0x%02x %3d %c  ",
+                 rA, rA, isprint(rA)?rA:'.');
+  con->dd_printf("F= "); con->print_bin(rF, 8);
+  con->dd_printf(" 0x%02x %3d %c  ", rF, rF, isprint(rF)?rF:'.');
+  if (edmr & 0xc0)
+    {
+      con->dd_color("ui_mkey");
+      con->dd_printf("Mode:4k");
+    }
+  else
+    {
+      con->dd_color("ui_title");
+      con->dd_printf("Mode:3k");
+    }
+  con->dd_printf("\n");
+  con->dd_color("answer");
+  con->dd_printf("                  SZxxxVxC\n");
+
+  con->dd_printf("XPC= 0x%03x IP= 0x%02x IIR= 0x%02x EIR= 0x%02x\n",
+		 mem->get_xpc(), rIP, rIIR, rEIR);
+  
+  con->dd_printf("BC= ");
+  rom->dump(0, rBC, rBC+7, 8, con);
+  con->dd_color("answer");
+  con->dd_printf("DE= ");
+  rom->dump(0, rDE, rDE+7, 8, con);
+  con->dd_color("answer");
+  con->dd_printf("HL= ");
+  rom->dump(0, rHL, rHL+7, 8, con);
+  con->dd_color("answer");
+  con->dd_printf("IX= ");
+  rom->dump(0, rIX, rIX+7, 8, con);
+  con->dd_color("answer");
+  con->dd_printf("IY= ");
+  rom->dump(0, rIY, rIY+7, 8, con);
+  con->dd_color("answer");
+  con->dd_printf("JK= ");
+  rom->dump(0, rJK, rJK+7, 8, con);
+  con->dd_color("answer");
+  con->dd_printf("SP= ");
+  rom->dump(0, rSP, rSP+7, 8, con);
+  con->dd_color("answer");
+
+  con->dd_printf("aAF= 0x%02x-%02x  ", raA, raF);
+  con->dd_printf("aBC= 0x%02x-%02x  ", raB, raC);
+  con->dd_printf("aDE= 0x%02x-%02x  ", raD, raE);
+  con->dd_printf("aHL= 0x%02x-%02x  ", raH, raL);
+  con->dd_printf("aJK= 0x%02x-%02x  ", raJ, raK);
+  con->dd_printf("\n");
+
+  con->dd_printf(" PW= 0x%04x-%04x  ", rPW>>16, rPW&0xffff);
+  con->dd_printf(" PX= 0x%04x-%04x  ", rPX>>16, rPX&0xffff);
+  con->dd_printf(" PY= 0x%04x-%04x  ", rPY>>16, rPY&0xffff);
+  con->dd_printf(" PZ= 0x%04x-%04x  ", rPZ>>16, rPZ&0xffff);
+  con->dd_printf("\n");
+  con->dd_printf("aPW= 0x%04x-%04x  ", raPW>>16, raPW&0xffff);
+  con->dd_printf("aPX= 0x%04x-%04x  ", raPX>>16, raPX&0xffff);
+  con->dd_printf("aPY= 0x%04x-%04x  ", raPY>>16, raPY&0xffff);
+  con->dd_printf("aPZ= 0x%04x-%04x  ", raPZ>>16, raPZ&0xffff);
+  con->dd_printf("\n");
+    
+  print_disass(PC, con);
+}
+
+void
+cl_r4k::mode3k(void)
+{
+  itab[0x40]= instruction_wrapper_40;
+  itab[0x41]= instruction_wrapper_41;
+  itab[0x43]= instruction_wrapper_43;
+  itab[0x44]= instruction_wrapper_44;
+  itab[0x49]= instruction_wrapper_49;
+  itab[0x4a]= instruction_wrapper_4a;
+  itab[0x4b]= instruction_wrapper_4b;
+  itab[0x52]= instruction_wrapper_52;
+  itab[0x53]= instruction_wrapper_53;
+  itab[0x58]= instruction_wrapper_58;
+  itab[0x59]= instruction_wrapper_59;
+  itab[0x5a]= instruction_wrapper_5a;
+  itab[0x5c]= instruction_wrapper_5c;
+  itab[0x5d]= instruction_wrapper_5d;
+  itab[0x64]= instruction_wrapper_64;
+  itab[0x67]= instruction_wrapper_67;
+  itab[0x68]= instruction_wrapper_68;
+  itab[0x69]= instruction_wrapper_69;
+  itab[0x6a]= instruction_wrapper_6a;
+  itab[0x6b]= instruction_wrapper_6b;
+  itab[0x6c]= instruction_wrapper_6c;
+  itab[0x80]= instruction_wrapper_80;
+  itab[0x88]= instruction_wrapper_88;
+  itab[0x90]= instruction_wrapper_90;
+
+  itab[0x45]= instruction_wrapper_45;
+  itab[0x48]= instruction_wrapper_48;
+  itab[0x4c]= instruction_wrapper_4c;
+  itab[0x4d]= instruction_wrapper_4d;
+
+  itab[0x50]= instruction_wrapper_50;
+  itab[0x51]= instruction_wrapper_51;
+  itab[0x54]= instruction_wrapper_54;
+  itab[0x55]= instruction_wrapper_55;
+
+  itab[0x60]= instruction_wrapper_60;
+  itab[0x61]= instruction_wrapper_61;
+  itab[0x62]= instruction_wrapper_62;
+  itab[0x63]= instruction_wrapper_63;
+  itab[0x65]= instruction_wrapper_65;
+  itab[0x6d]= instruction_wrapper_6d;
+
+  itab[0x7f]= instruction_wrapper_7f;
+
+  itab[0x81]= instruction_wrapper_81;
+  itab[0x82]= instruction_wrapper_82;
+  itab[0x83]= instruction_wrapper_83;
+  itab[0x84]= instruction_wrapper_84;
+  itab[0x85]= instruction_wrapper_85;
+  itab[0x86]= instruction_wrapper_86;
+  itab[0x87]= instruction_wrapper_87;
+  itab[0x89]= instruction_wrapper_89;
+  itab[0x8a]= instruction_wrapper_8a;
+  itab[0x8b]= instruction_wrapper_8b;
+  itab[0x8c]= instruction_wrapper_8c;
+  itab[0x8d]= instruction_wrapper_8d;
+  itab[0x8e]= instruction_wrapper_8e;
+  itab[0x8f]= instruction_wrapper_8f;
+
+  itab[0x91]= instruction_wrapper_91;
+  itab[0x92]= instruction_wrapper_92;
+  itab[0x93]= instruction_wrapper_93;
+  itab[0x94]= instruction_wrapper_94;
+  itab[0x95]= instruction_wrapper_95;
+  itab[0x96]= instruction_wrapper_96;
+  itab[0x97]= instruction_wrapper_97;
+  itab[0x98]= instruction_wrapper_98;
+  itab[0x99]= instruction_wrapper_99;
+  itab[0x9a]= instruction_wrapper_9a;
+  itab[0x9b]= instruction_wrapper_9b;
+  itab[0x9c]= instruction_wrapper_9c;
+  itab[0x9d]= instruction_wrapper_9d;
+  itab[0x9e]= instruction_wrapper_9e;
+  itab[0x9f]= instruction_wrapper_9f;
+
+  itab[0xa0]= instruction_wrapper_a0;
+  itab[0xa1]= instruction_wrapper_a1;
+  itab[0xa2]= instruction_wrapper_a2;
+  itab[0xa3]= instruction_wrapper_a3;
+  itab[0xa4]= instruction_wrapper_a4;
+  itab[0xa5]= instruction_wrapper_a5;
+  itab[0xa6]= instruction_wrapper_a6;
+  itab[0xa7]= instruction_wrapper_a7;
+  itab[0xa8]= instruction_wrapper_a8;
+  itab[0xa9]= instruction_wrapper_a9;
+  itab[0xaa]= instruction_wrapper_aa;
+  itab[0xab]= instruction_wrapper_ab;
+  itab[0xac]= instruction_wrapper_ac;
+  itab[0xad]= instruction_wrapper_ad;
+  itab[0xae]= instruction_wrapper_ae;
+
+  itab[0xb0]= instruction_wrapper_b0;
+  itab[0xb1]= instruction_wrapper_b1;
+  itab[0xb2]= instruction_wrapper_b2;
+  itab[0xb3]= instruction_wrapper_b3;
+  itab[0xb4]= instruction_wrapper_b4;
+  itab[0xb5]= instruction_wrapper_b5;
+  itab[0xb6]= instruction_wrapper_b6;
+  itab[0xb8]= instruction_wrapper_b8;
+  itab[0xb9]= instruction_wrapper_b9;
+  itab[0xba]= instruction_wrapper_ba;
+  itab[0xbb]= instruction_wrapper_bb;
+  itab[0xbc]= instruction_wrapper_bc;
+  itab[0xbd]= instruction_wrapper_bd;
+  itab[0xbe]= instruction_wrapper_be;
+  itab[0xbf]= instruction_wrapper_bf;
+}
+
+void
+cl_r4k::mode4k(void)
+{
+  itab[0x40]= instruction_wrapper_4knone;
+  itab[0x41]= instruction_wrapper_4knone;
+  itab[0x43]= instruction_wrapper_4knone;
+  itab[0x44]= instruction_wrapper_4knone;
+  itab[0x49]= instruction_wrapper_4knone;
+  itab[0x4a]= instruction_wrapper_4knone;
+  itab[0x4b]= instruction_wrapper_4knone;
+  itab[0x52]= instruction_wrapper_4knone;
+  itab[0x53]= instruction_wrapper_4knone;
+  itab[0x58]= instruction_wrapper_4knone;
+  itab[0x59]= instruction_wrapper_4knone;
+  itab[0x5a]= instruction_wrapper_4knone;
+  itab[0x5c]= instruction_wrapper_4knone;
+  itab[0x5d]= instruction_wrapper_4knone;
+  itab[0x64]= instruction_wrapper_4knone;
+  itab[0x67]= instruction_wrapper_4knone;
+  itab[0x68]= instruction_wrapper_4knone;
+  itab[0x69]= instruction_wrapper_4knone;
+  itab[0x6a]= instruction_wrapper_4knone;
+  itab[0x6b]= instruction_wrapper_4knone;
+  itab[0x6c]= instruction_wrapper_4knone;
+  itab[0x80]= instruction_wrapper_4knone;
+  itab[0x88]= instruction_wrapper_4knone;
+  itab[0x90]= instruction_wrapper_4knone;
+  
+  itab[0x45]= instruction_wrapper_4k45;
+  itab[0x48]= instruction_wrapper_4k48;
+  itab[0x4c]= instruction_wrapper_4k4c;
+  itab[0x4d]= instruction_wrapper_4k4d;
+
+  itab[0x50]= instruction_wrapper_4k50;
+  itab[0x51]= instruction_wrapper_4k51;
+  itab[0x54]= instruction_wrapper_4k54;
+  itab[0x55]= instruction_wrapper_4k55;
+
+  itab[0x60]= instruction_wrapper_4k60;
+  itab[0x61]= instruction_wrapper_4k61;
+  itab[0x62]= instruction_wrapper_4k62;
+  itab[0x63]= instruction_wrapper_4k63;
+  itab[0x65]= instruction_wrapper_4k65;
+  itab[0x6d]= instruction_wrapper_4k6d;
+
+  itab[0x7f]= instruction_wrapper_4k7f;
+
+  itab[0x81]= instruction_wrapper_4k81;
+  itab[0x82]= instruction_wrapper_4k82;
+  itab[0x83]= instruction_wrapper_4k83;
+  itab[0x84]= instruction_wrapper_4k84;
+  itab[0x85]= instruction_wrapper_4k85;
+  itab[0x86]= instruction_wrapper_4k86;
+  itab[0x87]= instruction_wrapper_4k87;
+  itab[0x89]= instruction_wrapper_4k89;
+  itab[0x8a]= instruction_wrapper_4k8a;
+  itab[0x8b]= instruction_wrapper_4k8b;
+  itab[0x8c]= instruction_wrapper_4k8c;
+  itab[0x8d]= instruction_wrapper_4k8d;
+  itab[0x8e]= instruction_wrapper_4k8e;
+  itab[0x8f]= instruction_wrapper_4k8f;
+
+  itab[0x91]= instruction_wrapper_4k91;
+  itab[0x92]= instruction_wrapper_4k92;
+  itab[0x93]= instruction_wrapper_4k93;
+  itab[0x94]= instruction_wrapper_4k94;
+  itab[0x95]= instruction_wrapper_4k95;
+  itab[0x96]= instruction_wrapper_4k96;
+  itab[0x97]= instruction_wrapper_4k97;
+  itab[0x98]= instruction_wrapper_4k98;
+  itab[0x99]= instruction_wrapper_4k99;
+  itab[0x9a]= instruction_wrapper_4k9a;
+  itab[0x9b]= instruction_wrapper_4k9b;
+  itab[0x9c]= instruction_wrapper_4k9c;
+  itab[0x9d]= instruction_wrapper_4k9d;
+  itab[0x9e]= instruction_wrapper_4k9e;
+  itab[0x9f]= instruction_wrapper_4k9f;
+
+  itab[0xa0]= instruction_wrapper_4ka0;
+  itab[0xa1]= instruction_wrapper_4ka1;
+  itab[0xa2]= instruction_wrapper_4ka2;
+  itab[0xa3]= instruction_wrapper_4ka3;
+  itab[0xa4]= instruction_wrapper_4ka4;
+  itab[0xa5]= instruction_wrapper_4ka5;
+  itab[0xa6]= instruction_wrapper_4ka6;
+  itab[0xa7]= instruction_wrapper_4ka7;
+  itab[0xa8]= instruction_wrapper_4ka8;
+  itab[0xa9]= instruction_wrapper_4ka9;
+  itab[0xaa]= instruction_wrapper_4kaa;
+  itab[0xab]= instruction_wrapper_4kab;
+  itab[0xac]= instruction_wrapper_4kac;
+  itab[0xad]= instruction_wrapper_4kad;
+  itab[0xae]= instruction_wrapper_4kae;
+
+  itab[0xb0]= instruction_wrapper_4kb0;
+  itab[0xb1]= instruction_wrapper_4kb1;
+  itab[0xb2]= instruction_wrapper_4kb2;
+  itab[0xb3]= instruction_wrapper_4kb3;
+  itab[0xb4]= instruction_wrapper_4kb4;
+  itab[0xb5]= instruction_wrapper_4kb5;
+  itab[0xb6]= instruction_wrapper_4kb6;
+  itab[0xb8]= instruction_wrapper_4kb8;
+  itab[0xb9]= instruction_wrapper_4kb9;
+  itab[0xba]= instruction_wrapper_4kba;
+  itab[0xbb]= instruction_wrapper_4kbb;
+  itab[0xbc]= instruction_wrapper_4kbc;
+  itab[0xbd]= instruction_wrapper_4kbd;
+  itab[0xbe]= instruction_wrapper_4kbe;
+  itab[0xbf]= instruction_wrapper_4kbf;
+}
+
+int
+cl_r4k::EXX(t_mem code)
+{
+  u16_t t;
+
+  cl_rxk::EXX(code);
+  
+  t= rJK;
+  cBC.W(raJK);
+  caJK.W(t);
+
+  return resGO;
+}
+
+int
+cl_r4k::PAGE_4K7F(t_mem code)
+{
+  code= fetch();
+  return itab_7f[code](this, code);
+}
+
+int
+cl_r4k::PAGE_4K6D(t_mem code)
+{
+  u8_t h, l;
+  class cl_memory_cell *op= &cPX, *idx= &cPW;
+  t_addr addr;
+  
+  code= fetch();
+  if (code == 0x6d)
+    return ld_r_g(destL(), rL);
+  if (code == 0x7f)
+    return ld_r_g(destA(), rA);
+  
+  h= code>>4;
+  l= code&0xf;
+  if ((l == 0xd) || (l == 0xf))
+    return resINV;
+  
+  switch (h&3)
+    {
+    case 0: idx= &cPW; break;
+    case 1: idx= &cPX; break;
+    case 2: idx= &cPY; break;
+    case 3: idx= &cPZ; break;
+    }
+  switch (h&0xc)
+    {
+    case 0x0:
+      if (l<=3)
+	op= (l&1)?(&cBC):&destBC();
+      else
+	op= &cPW;
+      break;
+    case 0x4:
+      if (l<=3)
+	op= (l&1)?(&cDE):&destDE();
+      else
+	op= &cPX;
+      break;
+    case 0x8: if (l<=3) op= &cIX; else op= &cPY; break;
+    case 0xc: if (l<=3) op= &cIY; else op= &cPZ; break;
+    }
+  addr= idx->get();
+  switch (l&6)
+    {
+    case 0:
+      {
+	u8_t d= fetch();
+	if (l&1)
+	  {
+	    u8_t offset= d;
+	    addr= px8(addr, offset);
+	  }
+	else
+	  {
+	    i8_t offset= d;
+	    addr= px8se(addr, offset);
+	  }
+	break;
+      }
+    case 2: addr= px16(addr, rHL); break;
+    case 4: addr= px16(addr, (l&1)?rIY:rIX); break;
+    case 6: break;
+    }
+
+  if (l&4)
+    {
+      // reg->reg
+      op->W(addr);
+    }
+  else
+    {
+      // mem rd/wr
+      u32_t v;
+      if (l&1)
+	{
+	  v= op->get();
+	  // Write
+	  mem->pxwrite(addr, v); addr++; v>>= 8; vc.wr++;
+	  mem->pxwrite(addr, v); addr++; v>>= 8; vc.wr++;
+	  if (op->get_width() > 16)
+	    {
+	      mem->pxwrite(addr, v); addr++; v>>= 8; vc.wr++;
+	      mem->pxwrite(addr, v); addr++; v>>= 8; vc.wr++;
+	    }
+	}
+      else
+	{
+	  // Read
+	  u8_t b;
+	  v= 0;
+	  b= mem->pxread(addr); addr++; v= (v<<8)|b; vc.rd++;
+	  b= mem->pxread(addr); addr++; v= (v<<8)|b; vc.rd++;
+	  if (op->get_width() > 16)
+	    {
+	      b= mem->pxread(addr); addr++; v= (v<<8)|b; vc.rd++;
+	      b= mem->pxread(addr); addr++; v= (v<<8)|b; vc.rd++;
+	    }
+	  op->W(v);
+	}
+    }
+  
+  return resGO;
+}
+
+
+/*
+ * CPU peripheral for r4k
+ */
+
+cl_r4k_cpu::cl_r4k_cpu(class cl_uc *auc):
+  cl_rxk_cpu(auc)
+{
+  r4uc= (class cl_r4k *)auc;
+  edmr= new cl_cell8();
+}
+
+int
+cl_r4k_cpu::init(void)
+{
+  cl_rxk_cpu::init();
+
+  uc->reg_cell_var(edmr, &(r4uc->edmr),
+		   "EDMR", "Enable dual-mode register");
+  edmr->add_hw(this);
+
+  stacksegl= register_cell(ruc->ioi, 0x1a,
+			   "STACKSEGL", "MMU register STACKSEGL");
+  stacksegh= register_cell(ruc->ioi, 0x1b,
+			   "STACKSEGH", "MMU register STACKSEGH");
+  datasegl= register_cell(ruc->ioi, 0x1e,
+			  "DATASEGL", "MMU register DATASEGL");
+  datasegh= register_cell(ruc->ioi, 0x1f,
+			  "DATASEGH", "MMU register DATASEGH");
+  return 0;
+}
+
+t_mem
+cl_r4k_cpu::read(class cl_memory_cell *cell)
+{
+  if (cell == edmr)
+    return edmr->get();
+  return cell->get();
+}
+
+void
+cl_r4k_cpu::write(class cl_memory_cell *cell, t_mem *val)
+{
+  if (cell == edmr)
+    {
+      if (*val & 0xc0)
+	r4uc->mode4k();
+      else
+	r4uc->mode3k();
+    }
+  
+  if (cell == dataseg)
+    {
+      (*val)&= 0xff;
+      datasegl->set(*val);
+      ruc->mem->set_dataseg(datasegh->read() * 256 + *val);
+    }
+  else if (cell == datasegl)
+    {
+      (*val)&= 0xff;
+      dataseg->set(*val);
+      ruc->mem->set_dataseg(datasegh->read() * 256 + *val);
+    }
+  else if (cell == datasegh)
+    {
+      (*val)&= 0x0f;
+      ruc->mem->set_dataseg((*val) * 256 + datasegl->read());
+    }
+  
+  else if (cell == stackseg)
+    {
+      (*val)&= 0xff;
+      stacksegl->set(*val);
+      ruc->mem->set_stackseg(stacksegh->read() * 256 + *val);
+    }
+  else if (cell == stacksegl)
+    {
+      (*val)&= 0xff;
+      stackseg->set(*val);
+      ruc->mem->set_stackseg(stacksegh->read() * 256 + *val);
+    }
+  else if (cell == stacksegh)
+    {
+      (*val)&= 0x0f;
+      ruc->mem->set_stackseg((*val) * 256 + stacksegl->read());
+    }
+
+  else if (cell == segsize)
+    {
+      (*val)&= 0xff;
+      ruc->mem->set_segsize(*val);
+    }
+
+  else if (cell == ruc->XPC)
+    {
+      (*val)&= 0xff;
+      ruc->mem->set_xpc(*val);
+    }
+  else if (cell == r4uc->LXPC)
+    {
+      (*val)&= 0xfff;
+      ruc->mem->set_lxpc(*val);
+    }
+}
+
+const char *
+cl_r4k_cpu::cfg_help(t_addr addr)
+{
+  switch (addr)
+    {
+      //case rxk_cpu_xpc: return "MMU register: XPC";
+      //case rxk_cpu_nuof: return "";
+    }
+  return "Not used";
+}
+
+
+void
+cl_r4k_cpu::print_info(class cl_console_base *con)
+{
+  cl_rxk_cpu::print_info(con);
+  con->dd_printf("EDMR    : 0x%02x\n", edmr->read());
+}
+
+
+/* End of rxk.src/r4k.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/r4kcl.h sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/r4kcl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/r4kcl.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/r4kcl.h	2021-09-13 16:16:27.000000000 +0000
@@ -0,0 +1,483 @@
+/*
+ * Simulator of microcontrollers (r4kcl.h)
+ *
+ * Copyright (C) 2020,2021 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef R4KCL_HEADER
+#define R4KCL_HEADER
+
+#include "r3kacl.h"
+#include "dp0m4.h"
+#include "dpedm4.h"
+#include "dpddm4.h"
+
+
+extern u32_t px8(u32_t px, u8_t offset);
+extern u32_t px8se(u32_t px, u8_t offset);
+extern u32_t px16(u32_t px, u16_t offset);
+extern u32_t px16se(u32_t px, u16_t offset);
+
+//#define raJ	(aJK.r.J)
+//#define raK	(aJK.r.K)
+//#define raJK	(aJK.JK)
+//#define raJKHL	(((u32_t)aJK.JK<<16)+aHL.HL)
+//#define raBCDE	(((u32_t)aBC.BC<<16)+aDE.DE)
+
+class cl_r4k: public cl_r3ka
+{
+public:
+  RP(aJK,JK,J,K);
+  u32_t rPW, rPX, rPY, rPZ;
+  u32_t raPW, raPX, raPY, raPZ;
+  u8_t rHTR;
+  class cl_cell8 cJ, caJ, cK, caK;
+  class cl_cell16 cJK, caJK;
+  class cl_cell32 cJKHL, cPW, cPX, cPY, cPZ;
+  class cl_cell32 caJKHL, caPW, caPX, caPY, caPZ;
+  class cl_cell8 cHTR;
+  class cl_cell16 *LXPC;
+  class cl_cell32 *cIRR, *caIRR;
+ public:
+  cl_r4k(class cl_sim *asim);
+  virtual int init();
+  virtual const char *id_string(void);
+  virtual void reset(void);
+  
+  virtual void make_cpu_hw(void);
+  virtual t_addr chip_size() { return 0x1000000; }
+
+  virtual struct dis_entry *dis_entry(t_addr addr);
+  virtual struct dis_entry *dis_6d_entry(t_addr addr);
+  virtual int longest_inst(void) { return 6; }
+  virtual void disass_irr(chars *work, bool dd);
+  virtual void disass_irrl(chars *work, bool dd);
+  
+  virtual void select_IRR(bool dd);
+  virtual class cl_cell32 *destIRR(void) { return altd?caIRR:cIRR; }
+  virtual class cl_cell32 &destPW(void) { return altd?caPW:cPW; }
+  virtual class cl_cell32 &destPX(void) { return altd?caPX:cPX; }
+  virtual class cl_cell32 &destPY(void) { return altd?caPY:cPY; }
+  virtual class cl_cell32 &destPZ(void) { return altd?caPZ:cPZ; }
+  virtual class cl_cell32 &destBCDE(void) { return altd?caBCDE:cBCDE; }
+  virtual class cl_cell32 &destJKHL(void) { return altd?caJKHL:cJKHL; }
+  virtual class cl_cell16 &destJK(void) { return altd?caJK:cJK; }
+  
+  virtual void print_regs(class cl_console_base *con);
+
+  virtual int convc_pp(class cl_cell32 &pp);
+  virtual int convd_pp(class cl_cell32 &pp);
+  
+  // move
+  virtual int ld_pd_ihtr_hl(class cl_cell32 &dest);
+  virtual int ld_irr_iird(class cl_cell16 &ir);			// 1f,14t,0w,4r
+  virtual int ld_iird_irr(class cl_cell16 &ir);			// 1f,19t,4w,0r
+  virtual int ld_irr_ips_hl(t_mem code);			// 0f,14t,4r,0w
+  virtual int ld_irr_ips_d(t_mem code);				// 1f,14t,4r,0w
+  virtual int ld_ips_hl_irr(t_mem code);			// 0f,18t,0r,4w
+  virtual int ld_ips_d_irr(t_mem code);				// 1f,19t,0r,4w
+  virtual int ldl_px_ir(t_mem code);				// 0f,4t,0r,0w
+  virtual int ldl_px_irrl(t_mem code);				// 0f,4t,0r,0w
+  virtual int ld_px_irr(t_mem code);				// 0f,4t,0r,0w
+  virtual int ld_irr_px(t_mem code);				// 0f,4t,0r,0w
+  virtual int ld32_imn(u32_t op);				// 2f,19t,0r,4w
+  virtual int ld_r32_imn(class cl_cell32 &dest);		// 2f,15t,4r,0w
+  virtual int ld_hl_ipsd(u32_t ps);				// 1f,9t,2r,0w
+  virtual int ld_ipsd_hl(u32_t ps);				// 1f,10t,0r,2w
+  virtual int ld_a_ipshl(u32_t ps);				// 0f,6t,1r,0w
+  virtual int ld_ipshl_a(u32_t ps);				// 0f,7t,0r,1w
+  virtual int ld_a_ipsd(u32_t ps);				// 1f,6t,1r,0w
+  virtual int ld_ipsd_a(u32_t ps);				// 1f,8t,0r,1w
+  virtual int ldl_pd_ispn(class cl_cell32 &pd);			// 1f,11t,2r,0w
+  virtual int ld_pd_ispn(class cl_cell32 &pd);			// 1f,15t,4r,0w
+  virtual int ld_ispn_ps(u32_t ps);				// 1f,19t,0r,4w
+  virtual int ld_hl_ipsbc(u32_t ps);				// 0f,10t,2r,0w
+  virtual int ld_ipdbc_hl(u32_t pd);				// 0f,12t,0r,2w
+  virtual int ldf_pd_ilmn(class cl_cell32 &pd);			// 3f,19t,4r,0w
+  virtual int ldf_ilmn_ps(u32_t ps);				// 3f,23t,0r,4w
+  virtual int ldf_rr_ilmn(class cl_cell16 &rr);			// 3f,15t,2r,0w
+  virtual int ldf_ilmn_rr(u16_t rr);				// 3f,17t,0r,2w
+  virtual int ld_pd_klmn(class cl_cell32 &pd);			// 4f,12t,0r,0w
+  virtual int ldl_pd_mn(class cl_cell32 &pd);			// 2f,8t,0r,0w
+  virtual int copy(int dir);					// 0f,5t,xr,xw
+  virtual int pop_pd(class cl_cell32 &pd);			// 0f,13t,4r,0w
+  virtual int push_ps(u32_t ps);				// 0f,18t,0r,4w
+  
+  // arith
+  virtual int subhl(class cl_cell16 &dest, u16_t op);
+  virtual int test8(u8_t op);					// 0f,2t,0w,0r
+  virtual int test16(u16_t op);					// 0f,2t,0w,0r
+  virtual int test32(u32_t op);					// 0f,2t,0w,0r
+  virtual int flag_cc_hl(t_mem code);				// 0f,4t,0w,0r
+  
+  // brach
+  virtual int lljp_cx(t_mem code);				// 4f,14t,0w,0r
+  virtual int lljp_cc(t_mem code);				// 4f,14t,0w,0r
+  virtual int jre_cx_cc(bool cond);				// 2f,9t,0w,0r
+  virtual int jr_cx_e(bool cond);				// 1f,4t,0w,0r
+  virtual int jp_cx_mn(bool cond);				// 2f,7t,0w,0r
+  
+  virtual void mode3k(void);
+  virtual void mode4k(void);
+
+  virtual int EXX(t_mem code);
+
+  // Page 0, m4 mode
+  virtual int RL_HL(t_mem code) { return rot17left(destHL(), rHL); }
+  virtual int RL_BC(t_mem code) { return rot17left(destBC(), rBC); }
+  virtual int SUB_HL_JK(t_mem code) { return subhl(destHL(), rJK); }
+  virtual int SUB_HL_DE(t_mem code) { return subhl(destHL(), rDE); }
+  virtual int TEST_HL(t_mem code) { return test16(rHL); }
+  virtual int CP_HL_D(t_mem code);
+  virtual int RLC_BC(t_mem code) { return rot16left(destBC(), rBC); }
+  virtual int RLC_DE(t_mem code) { return rot16left(destDE(), rDE); }
+  virtual int RRC_BC(t_mem code) { return rot16right(destBC(), rBC); }
+  virtual int RRC_DE(t_mem code) { return rot16right(destDE(), rDE); }
+  virtual int XOR_HL_DE(t_mem code) { return xor16(destHL(), rHL, rDE); }
+  virtual int RR_BC(t_mem code) { return rot17right(destBC(), rBC); }
+  virtual int ADD_HL_JK(t_mem code) { return add_hl_ss(rJK); }
+  virtual int LD_HL_BC(t_mem code) { return ld_hl_op(rBC); }
+  virtual int LD_BC_HL(t_mem code);
+  virtual int LD_HL_DE(t_mem code) { return ld_hl_op(rDE); }
+  virtual int LDF_iLMN_HL(t_mem code);
+  virtual int LDF_HL_iLMN(t_mem code);
+  virtual int LD_iMN_BCDE(t_mem code) { return ld32_imn(rBCDE); }
+  virtual int LD_iMN_JKHL(t_mem code) { return ld32_imn(rJKHL); }
+  virtual int LD_BCDE_iMN(t_mem code) { return ld_r32_imn(destBCDE()); }
+  virtual int LD_JKHL_iMN(t_mem code) { return ld_r32_imn(destJKHL()); }
+  virtual int LD_HL_iPWd(t_mem code) { return ld_hl_ipsd(rPW); }
+  virtual int LD_HL_iPXd(t_mem code) { return ld_hl_ipsd(rPX); }
+  virtual int LD_HL_iPYd(t_mem code) { return ld_hl_ipsd(rPY); }
+  virtual int LD_HL_iPZd(t_mem code) { return ld_hl_ipsd(rPZ); }
+  virtual int LD_iPWd_HL(t_mem code) { return ld_ipsd_hl(rPW); }
+  virtual int LD_iPXd_HL(t_mem code) { return ld_ipsd_hl(rPX); }
+  virtual int LD_iPYd_HL(t_mem code) { return ld_ipsd_hl(rPY); }
+  virtual int LD_iPZd_HL(t_mem code) { return ld_ipsd_hl(rPZ); }
+  virtual int LLJP_lxpcmn(t_mem code);
+  virtual int LD_imn_JK(t_mem code);
+  virtual int LD_JK_imn(t_mem code);
+  virtual int LDF_ilmn_A(t_mem code);
+  virtual int LDF_A_ilmn(t_mem code);
+  virtual int LD_A_iPWHL(t_mem code) { return ld_a_ipshl(rPW); }
+  virtual int LD_A_iPXHL(t_mem code) { return ld_a_ipshl(rPX); }
+  virtual int LD_A_iPYHL(t_mem code) { return ld_a_ipshl(rPY); }
+  virtual int LD_A_iPZHL(t_mem code) { return ld_a_ipshl(rPZ); }
+  virtual int LD_iPWHL_HL(t_mem code) { return ld_ipshl_a(rPW); }
+  virtual int LD_iPXHL_HL(t_mem code) { return ld_ipshl_a(rPX); }
+  virtual int LD_iPYHL_HL(t_mem code) { return ld_ipshl_a(rPY); }
+  virtual int LD_iPZHL_HL(t_mem code) { return ld_ipshl_a(rPZ); }
+  virtual int LD_A_iPWd(t_mem code) { return ld_a_ipsd(rPW); }
+  virtual int LD_A_iPXd(t_mem code) { return ld_a_ipsd(rPX); }
+  virtual int LD_A_iPYd(t_mem code) { return ld_a_ipsd(rPY); }
+  virtual int LD_A_iPZd(t_mem code) { return ld_a_ipsd(rPZ); }
+  virtual int LD_iPWd_A(t_mem code) { return ld_ipsd_a(rPW); }
+  virtual int LD_iPXd_A(t_mem code) { return ld_ipsd_a(rPX); }
+  virtual int LD_iPYd_A(t_mem code) { return ld_ipsd_a(rPY); }
+  virtual int LD_iPZd_A(t_mem code) { return ld_ipsd_a(rPZ); }
+  virtual int LLCALL_lxpcmn(t_mem code);
+  virtual int LD_LXPC_HL(t_mem code);
+  virtual int LD_HL_LXPC(t_mem code);
+  virtual int JRE_ee(t_mem code);
+  virtual int JR_GT_e(t_mem code) { return jr_cx_e(cond_GT(rF)); }
+  virtual int JR_LT_e(t_mem code) { return jr_cx_e(cond_LT(rF)); }
+  virtual int JR_GTU_e(t_mem code) { return jr_cx_e(cond_GTU(rF)); }
+  virtual int JR_V_e(t_mem code) { return jr_cx_e(cond_V(rF)); }
+  virtual int JP_GT_mn(t_mem code) { return jp_cx_mn(cond_GT(rF)); }
+  virtual int JP_LT_mn(t_mem code) { return jp_cx_mn(cond_LT(rF)); }
+  virtual int JP_GTU_mn(t_mem code) { return jp_cx_mn(cond_GTU(rF)); }
+  virtual int JP_V_mn(t_mem code) { return jp_cx_mn(cond_V(rF)); }
+  virtual int LD_BCDE_d(t_mem code);
+  virtual int LD_JKHL_d(t_mem code);
+  virtual int MULU(t_mem code);
+  virtual int LD_JK_mn(t_mem code);
+  virtual int LD_DE_HL(t_mem code);
+  virtual int EX_BC_HL(t_mem code);
+  virtual int EX_JKHL_BCDE(t_mem code);
+  virtual int EX_JK_HL(t_mem code);
+  virtual int CLR_HL(t_mem code);
+  
+  // Page ED, m4 mode
+  virtual int CBM_N(t_mem code);
+  virtual int LD_PW_iHTR_HL(t_mem code) { return ld_pd_ihtr_hl(cPW); }
+  virtual int LD_PX_iHTR_HL(t_mem code) { return ld_pd_ihtr_hl(cPX); }
+  virtual int LD_PY_iHTR_HL(t_mem code) { return ld_pd_ihtr_hl(cPY); }
+  virtual int LD_PZ_iHTR_HL(t_mem code) { return ld_pd_ihtr_hl(cPZ); }
+  virtual int SBOX_A(t_mem code);
+  virtual int IBOX_A(t_mem code);
+  virtual int DWJNZ(t_mem code);
+  virtual int CP_HL_DE(t_mem code) { return cp16(rHL, rDE); }
+  virtual int TEST_BC(t_mem code) { tick(2); return test16(rBC); }
+  virtual int LLJP_GT_LXPC_MN(t_mem code)  { return lljp_cx(code); }
+  virtual int LLJP_GTU_LXPC_MN(t_mem code) { return lljp_cx(code); }
+  virtual int LLJP_LT_LXPC_MN(t_mem code)  { return lljp_cx(code); }
+  virtual int LLJP_V_LXPC_MN(t_mem code)   { return lljp_cx(code); }
+  virtual int LLJP_NZ_LXPC_MN(t_mem code)  { return lljp_cc(code); }
+  virtual int LLJP_Z_LXPC_MN(t_mem code)   { return lljp_cc(code); }
+  virtual int LLJP_NC_LXPC_MN(t_mem code)  { return lljp_cc(code); }
+  virtual int LLJP_C_LXPC_MN(t_mem code)   { return lljp_cc(code); }
+  virtual int PUSH_MN(t_mem code);
+  virtual int JRE_GT_EE(t_mem code)  { return jre_cx_cc(cond_GT(rF)); }
+  virtual int JRE_LT_EE(t_mem code)  { return jre_cx_cc(cond_LT(rF)); }
+  virtual int JRE_GTU_EE(t_mem code) { return jre_cx_cc(cond_GTU(rF)); }
+  virtual int JRE_V_EE(t_mem code)   { return jre_cx_cc(rF&flagV); }
+  virtual int JRE_NZ_EE(t_mem code)  { return jre_cx_cc(!(rF&flagZ)); }
+  virtual int JRE_Z_EE(t_mem code)   { return jre_cx_cc(rF&flagZ); }
+  virtual int JRE_NC_EE(t_mem code)  { return jre_cx_cc(!(rF&flagC)); }
+  virtual int JRE_C_EE(t_mem code)   { return jre_cx_cc(rF&flagC); }
+  virtual int FLAG_NZ_HL(t_mem code) { return flag_cc_hl(code); }
+  virtual int FLAG_Z_HL(t_mem code)   { return flag_cc_hl(code); }
+  virtual int FLAG_NC_HL(t_mem code)  { return flag_cc_hl(code); }
+  virtual int FLAG_C_HL(t_mem code)   { return flag_cc_hl(code); }
+  virtual int FLAG_GT_HL(t_mem code)  { return flag_cc_hl(code); }
+  virtual int FLAG_LT_HL(t_mem code)  { return flag_cc_hl(code); }
+  virtual int FLAG_GTU_HL(t_mem code) { return flag_cc_hl(code); }
+  virtual int FLAG_V_HL(t_mem code)   { return flag_cc_hl(code); }
+  virtual int CALL_iHL(t_mem code);
+  virtual int LLRET(t_mem code);
+  virtual int EXP(t_mem code);
+  virtual int LD_HTR_A(t_mem code);
+  virtual int LD_A_HTR(t_mem code);
+  virtual int FSYSCALL(t_mem code);
+  virtual int SYSRET(t_mem code);
+  virtual int SETUSRP(t_mem code);
+  virtual int SETSYSP(t_mem code);
+  virtual int LLCALL_iJKHL(t_mem code);
+  virtual int LDL_PW_iSPn(t_mem code) { return ldl_pd_ispn(destPW()); }
+  virtual int LDL_PX_iSPn(t_mem code) { return ldl_pd_ispn(destPX()); }
+  virtual int LDL_PY_iSPn(t_mem code) { return ldl_pd_ispn(destPY()); }
+  virtual int LDL_PZ_iSPn(t_mem code) { return ldl_pd_ispn(destPZ()); }
+  virtual int LD_PW_iSPn(t_mem code) { return ld_pd_ispn(cPW); }
+  virtual int LD_PX_iSPn(t_mem code) { return ld_pd_ispn(cPX); }
+  virtual int LD_PY_iSPn(t_mem code) { return ld_pd_ispn(cPY); }
+  virtual int LD_PZ_iSPn(t_mem code) { return ld_pd_ispn(cPZ); }
+  virtual int LD_iSPn_PW(t_mem code) { return ld_ispn_ps(rPW); }
+  virtual int LD_iSPn_PX(t_mem code) { return ld_ispn_ps(rPX); }
+  virtual int LD_iSPn_PY(t_mem code) { return ld_ispn_ps(rPY); }
+  virtual int LD_iSPn_PZ(t_mem code) { return ld_ispn_ps(rPZ); }
+  virtual int LD_HL_iPWBC(t_mem code) { return ld_hl_ipsbc(rPW); }
+  virtual int LD_HL_iPXBC(t_mem code) { return ld_hl_ipsbc(rPX); }
+  virtual int LD_HL_iPYBC(t_mem code) { return ld_hl_ipsbc(rPY); }
+  virtual int LD_HL_iPZBC(t_mem code) { return ld_hl_ipsbc(rPZ); }
+  virtual int LD_iPWBC_HL(t_mem code) { return ld_ipdbc_hl(rPW); }
+  virtual int LD_iPXBC_HL(t_mem code) { return ld_ipdbc_hl(rPX); }
+  virtual int LD_iPYBC_HL(t_mem code) { return ld_ipdbc_hl(rPY); }
+  virtual int LD_iPZBC_HL(t_mem code) { return ld_ipdbc_hl(rPZ); }
+  virtual int LDF_PW_ilmn(t_mem code) { return ldf_pd_ilmn(destPW()); }
+  virtual int LDF_PX_ilmn(t_mem code) { return ldf_pd_ilmn(destPX()); }
+  virtual int LDF_PY_ilmn(t_mem code) { return ldf_pd_ilmn(destPY()); }
+  virtual int LDF_PZ_ilmn(t_mem code) { return ldf_pd_ilmn(destPZ()); }
+  virtual int LDF_ilmn_PW(t_mem code) { return ldf_ilmn_ps(rPW); }
+  virtual int LDF_ilmn_PX(t_mem code) { return ldf_ilmn_ps(rPX); }
+  virtual int LDF_ilmn_PY(t_mem code) { return ldf_ilmn_ps(rPY); }
+  virtual int LDF_ilmn_PZ(t_mem code) { return ldf_ilmn_ps(rPZ); }
+  virtual int LDF_BC_ilmn(t_mem code) { return ldf_rr_ilmn(destBC()); }
+  virtual int LDF_DE_ilmn(t_mem code) { return ldf_rr_ilmn(destDE()); }
+  virtual int LDF_IX_ilmn(t_mem code) { return ldf_rr_ilmn(cIX); }
+  virtual int LDF_IY_ilmn(t_mem code) { return ldf_rr_ilmn(cIY); }
+  virtual int LDF_ilmn_BC(t_mem code) { return ldf_ilmn_rr(rBC); }
+  virtual int LDF_ilmn_DE(t_mem code) { return ldf_ilmn_rr(rDE); }
+  virtual int LDF_ilmn_IX(t_mem code) { return ldf_ilmn_rr(rIX); }
+  virtual int LDF_ilmn_IY(t_mem code) { return ldf_ilmn_rr(rIY); }
+  virtual int LD_PW_klmn(t_mem code) { return ld_pd_klmn(cPW); }
+  virtual int LD_PX_klmn(t_mem code) { return ld_pd_klmn(cPX); }
+  virtual int LD_PY_klmn(t_mem code) { return ld_pd_klmn(cPY); }
+  virtual int LD_PZ_klmn(t_mem code) { return ld_pd_klmn(cPZ); }
+  virtual int LDL_PW_mn(t_mem code) { return ldl_pd_mn(destPW()); }
+  virtual int LDL_PX_mn(t_mem code) { return ldl_pd_mn(destPX()); }
+  virtual int LDL_PY_mn(t_mem code) { return ldl_pd_mn(destPY()); }
+  virtual int LDL_PZ_mn(t_mem code) { return ldl_pd_mn(destPZ()); }
+  virtual int CONVC_PW(t_mem code) { return convc_pp(cPW); }
+  virtual int CONVC_PX(t_mem code) { return convc_pp(cPX); }
+  virtual int CONVC_PY(t_mem code) { return convc_pp(cPY); }
+  virtual int CONVC_PZ(t_mem code) { return convc_pp(cPZ); }
+  virtual int CONVD_PW(t_mem code) { return convd_pp(cPW); }
+  virtual int CONVD_PX(t_mem code) { return convd_pp(cPX); }
+  virtual int CONVD_PY(t_mem code) { return convd_pp(cPY); }
+  virtual int CONVD_PZ(t_mem code) { return convd_pp(cPZ); }
+  virtual int CP_JKHL_BCDE(t_mem code) { return cp32(rJKHL, rBCDE); }
+  virtual int EX_aBC_HL(t_mem code);
+  virtual int EX_aJK_HL(t_mem code);
+  virtual int COPY(t_mem code) { return copy(+1); }
+  virtual int COPYR(t_mem code) { return copy(-1); }
+  virtual int POP_PW(t_mem code) { return pop_pd(destPW()); }
+  virtual int POP_PX(t_mem code) { return pop_pd(destPX()); }
+  virtual int POP_PY(t_mem code) { return pop_pd(destPY()); }
+  virtual int POP_PZ(t_mem code) { return pop_pd(destPZ()); }
+  virtual int PUSH_PW(t_mem code) { return push_ps(rPW); }
+  virtual int PUSH_PX(t_mem code) { return push_ps(rPX); }
+  virtual int PUSH_PY(t_mem code) { return push_ps(rPY); }
+  virtual int PUSH_PZ(t_mem code) { return push_ps(rPZ); }
+  virtual int ADD_JKHL_BCDE(t_mem code);
+  virtual int SUB_JKHL_BCDE(t_mem code);
+  virtual int AND_JKHL_BCDE(t_mem code);
+  virtual int OR_JKHL_BCDE(t_mem code);
+  virtual int XOR_JKHL_BCDE(t_mem code);
+  virtual int LD_HL_iSPHL(t_mem code);
+  
+  // Page DD/FD
+  virtual int LD_A_iIRA(t_mem code);
+  virtual int TEST_IR(t_mem code) { tick(2); return test16(cIR->get()); }
+  virtual int LD_IRR_iHL(t_mem code);
+  virtual int LD_IRR_iIXd(t_mem code) { return ld_irr_iird(cIX); }
+  virtual int LD_IRR_iIYd(t_mem code) { return ld_irr_iird(cIY); }
+  virtual int LD_IRR_iSPn(t_mem code);
+  virtual int LD_iHL_IRR(t_mem code);
+  virtual int LD_iIXd_IRR(t_mem code) { return ld_iird_irr(cIX); }
+  virtual int LD_iIYd_IRR(t_mem code) { return ld_iird_irr(cIY); }
+  virtual int LD_iSPn_IRR(t_mem code);
+  virtual int NEG_IRR(t_mem coed) { return sub32(0, cIRR->get(),
+						 *cIRR, false); }
+  virtual int POP_IRR(t_mem code);
+  virtual int PUSH_IRR(t_mem code);
+  virtual int RL_1_IRR(t_mem code) { return rot33left(*destIRR(),
+						      cIRR->get(),
+						      1); }
+  virtual int RL_2_IRR(t_mem code) { return rot33left(*destIRR(),
+						      cIRR->get(),
+						      2); }
+  virtual int RL_4_IRR(t_mem code) { return rot33left(*destIRR(),
+						      cIRR->get(),
+						      4); }
+  virtual int RLC_1_IRR(t_mem code) { return rot32left(*destIRR(),
+						       cIRR->get(),
+						       1); }
+  virtual int RLC_2_IRR(t_mem code) { return rot32left(*destIRR(),
+						       cIRR->get(),
+						       2); }
+  virtual int RLC_4_IRR(t_mem code) { return rot32left(*destIRR(),
+						       cIRR->get(),
+						       4); }
+  virtual int RLC_8_IRR(t_mem code);
+  virtual int RLB_A_IRR(t_mem code);
+  virtual int SLA_1_IRR(t_mem code) { return sla32(*destIRR(), cIRR->get(), 1); }
+  virtual int SLA_2_IRR(t_mem code) { return sla32(*destIRR(), cIRR->get(), 2); }
+  virtual int SLA_4_IRR(t_mem code) { return sla32(*destIRR(), cIRR->get(), 4); }
+  virtual int SLL_1_IRR(t_mem code) { return sla32(*destIRR(), cIRR->get(), 1); }
+  virtual int SLL_2_IRR(t_mem code) { return sla32(*destIRR(), cIRR->get(), 2); }
+  virtual int SLL_4_IRR(t_mem code) { return sla32(*destIRR(), cIRR->get(), 4); }
+  virtual int TEST_IRR(t_mem code) { tick(2); return test32(cIRR->get()); }
+  virtual int RR_1_IRR(t_mem code) { return rot33right(*destIRR(),
+						       cIRR->get(),
+						       1); }
+  virtual int RR_2_IRR(t_mem code) { return rot33right(*destIRR(),
+						       cIRR->get(),
+						       2); }
+  virtual int RR_4_IRR(t_mem code) { return rot33right(*destIRR(),
+						       cIRR->get(),
+						       4); }
+  virtual int RRC_1_IRR(t_mem code) { return rot32right(*destIRR(),
+							cIRR->get(),
+							1); }
+  virtual int RRC_2_IRR(t_mem code) { return rot32right(*destIRR(),
+							cIRR->get(),
+							2); }
+  virtual int RRC_4_IRR(t_mem code) { return rot32right(*destIRR(),
+							cIRR->get(),
+							4); }
+  virtual int RRC_8_IRR(t_mem code);
+  virtual int RRB_A_IRR(t_mem code);
+  virtual int SRA_1_IRR(t_mem code) { return sra32(*destIRR(),
+						   cIRR->get(),
+						   1); }
+  virtual int SRA_2_IRR(t_mem code) { return sra32(*destIRR(),
+						   cIRR->get(),
+						   2); }
+  virtual int SRA_4_IRR(t_mem code) { return sra32(*destIRR(),
+						   cIRR->get(),
+						   4); }
+  virtual int SRL_1_IRR(t_mem code) { return srl32(*destIRR(),
+						   cIRR->get(),
+						   1); }
+  virtual int SRL_2_IRR(t_mem code) { return srl32(*destIRR(),
+						   cIRR->get(),
+						   2); }
+  virtual int SRL_4_IRR(t_mem code) { return srl32(*destIRR(),
+						   cIRR->get(),
+						   4); }
+  virtual int LDF_IRR_iLMN(t_mem code);
+  virtual int LDF_iLMN_IRR(t_mem code);
+  virtual int LD_IRR_iPW_HL(t_mem code) { return ld_irr_ips_hl(code); }
+  virtual int LD_IRR_iPX_HL(t_mem code) { return ld_irr_ips_hl(code); }
+  virtual int LD_IRR_iPY_HL(t_mem code) { return ld_irr_ips_hl(code); }
+  virtual int LD_IRR_iPZ_HL(t_mem code) { return ld_irr_ips_hl(code); }
+  virtual int LD_iPW_HL_IRR(t_mem code) { return ld_ips_hl_irr(code); }
+  virtual int LD_iPX_HL_IRR(t_mem code) { return ld_ips_hl_irr(code); }
+  virtual int LD_iPY_HL_IRR(t_mem code) { return ld_ips_hl_irr(code); }
+  virtual int LD_iPZ_HL_IRR(t_mem code) { return ld_ips_hl_irr(code); }
+  virtual int LD_IRR_iPW_D(t_mem code) { return ld_irr_ips_d(code); }
+  virtual int LD_IRR_iPX_D(t_mem code) { return ld_irr_ips_d(code); }
+  virtual int LD_IRR_iPY_D(t_mem code) { return ld_irr_ips_d(code); }
+  virtual int LD_IRR_iPZ_D(t_mem code) { return ld_irr_ips_d(code); }
+  virtual int LD_iPW_D_IRR(t_mem code) { return ld_ips_d_irr(code); }
+  virtual int LD_iPX_D_IRR(t_mem code) { return ld_ips_d_irr(code); }
+  virtual int LD_iPY_D_IRR(t_mem code) { return ld_ips_d_irr(code); }
+  virtual int LD_iPZ_D_IRR(t_mem code) { return ld_ips_d_irr(code); }
+  virtual int LDL_PW_IR(t_mem code) { return ldl_px_ir(code); }
+  virtual int LDL_PX_IR(t_mem code) { return ldl_px_ir(code); }
+  virtual int LDL_PY_IR(t_mem code) { return ldl_px_ir(code); }
+  virtual int LDL_PZ_IR(t_mem code) { return ldl_px_ir(code); }
+  virtual int LD_PW_IRR(t_mem code) { return ld_px_irr(code); }
+  virtual int LD_PX_IRR(t_mem code) { return ld_px_irr(code); }
+  virtual int LD_PY_IRR(t_mem code) { return ld_px_irr(code); }
+  virtual int LD_PZ_IRR(t_mem code) { return ld_px_irr(code); }
+  virtual int LDL_PW_IRRL(t_mem code) { return ldl_px_irrl(code); }
+  virtual int LDL_PX_IRRL(t_mem code) { return ldl_px_irrl(code); }
+  virtual int LDL_PY_IRRL(t_mem code) { return ldl_px_irrl(code); }
+  virtual int LDL_PZ_IRRL(t_mem code) { return ldl_px_irrl(code); }
+  virtual int LD_IRR_PW(t_mem code) { return ld_irr_px(code); }
+  virtual int LD_IRR_PX(t_mem code) { return ld_irr_px(code); }
+  virtual int LD_IRR_PY(t_mem code) { return ld_irr_px(code); }
+  virtual int LD_IRR_PZ(t_mem code) { return ld_irr_px(code); }
+  virtual int LD_iSP_HL_IRR(t_mem code);
+  virtual int CALL_iIR(t_mem code);
+  virtual int LD_IRR_iSP_HL(t_mem code);
+  
+  // Starter of extra pages
+  virtual int PAGE_4K6D(t_mem code);
+  virtual int PAGE_4K7F(t_mem code);
+};
+
+class cl_r4k_cpu: public cl_rxk_cpu
+{
+protected:
+  class cl_r4k *r4uc;
+  class cl_cell8 *edmr;
+  class cl_memory_cell *stacksegl, *stacksegh;
+  class cl_memory_cell *datasegl , *datasegh;
+public:
+  cl_r4k_cpu(class cl_uc *auc);
+  virtual int init(void);
+  virtual t_mem read(class cl_memory_cell *cell);
+  virtual void write(class cl_memory_cell *cell, t_mem *val);
+  virtual const char *cfg_help(t_addr addr);
+  
+  //virtual t_mem conf_op(cl_memory_cell *cell, t_addr addr, t_mem *val);
+
+  virtual void print_info(class cl_console_base *con);
+};
+
+
+#endif
+
+/* End of rxk.src/r4kcl.h */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/r4kcl_instructions.h sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/r4kcl_instructions.h
--- sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/r4kcl_instructions.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/r4kcl_instructions.h	2021-08-16 10:12:33.000000000 +0000
@@ -0,0 +1,82 @@
+virtual int instruction_4k42(t_mem code) { return resNOT_DONE; }
+virtual int instruction_4k45(t_mem code) { return resNOT_DONE; }
+virtual int instruction_4k48(t_mem code) { return resNOT_DONE; }
+virtual int instruction_4k4c(t_mem code) { return resNOT_DONE; }
+virtual int instruction_4k4d(t_mem code) { return resNOT_DONE; }
+
+virtual int instruction_4k50(t_mem code) { return resNOT_DONE; }
+virtual int instruction_4k51(t_mem code) { return resNOT_DONE; }
+virtual int instruction_4k54(t_mem code) { return resNOT_DONE; }
+virtual int instruction_4k55(t_mem code) { return resNOT_DONE; }
+
+virtual int instruction_4k60(t_mem code) { return resNOT_DONE; }
+virtual int instruction_4k61(t_mem code) { return resNOT_DONE; }
+virtual int instruction_4k62(t_mem code) { return resNOT_DONE; }
+virtual int instruction_4k63(t_mem code) { return resNOT_DONE; }
+virtual int instruction_4k65(t_mem code) { return resNOT_DONE; }
+virtual int instruction_4k6d(t_mem code) { return resNOT_DONE; }
+
+virtual int instruction_4k7f(t_mem code) { return resNOT_DONE; }
+
+virtual int instruction_4k81(t_mem code) { return resNOT_DONE; }
+virtual int instruction_4k82(t_mem code) { return resNOT_DONE; }
+virtual int instruction_4k83(t_mem code) { return resNOT_DONE; }
+virtual int instruction_4k84(t_mem code) { return resNOT_DONE; }
+virtual int instruction_4k85(t_mem code) { return resNOT_DONE; }
+virtual int instruction_4k86(t_mem code) { return resNOT_DONE; }
+virtual int instruction_4k87(t_mem code) { return resNOT_DONE; }
+virtual int instruction_4k89(t_mem code) { return resNOT_DONE; }
+virtual int instruction_4k8a(t_mem code) { return resNOT_DONE; }
+virtual int instruction_4k8b(t_mem code) { return resNOT_DONE; }
+virtual int instruction_4k8c(t_mem code) { return resNOT_DONE; }
+virtual int instruction_4k8d(t_mem code) { return resNOT_DONE; }
+virtual int instruction_4k8e(t_mem code) { return resNOT_DONE; }
+virtual int instruction_4k8f(t_mem code) { return resNOT_DONE; }
+
+virtual int instruction_4k91(t_mem code) { return resNOT_DONE; }
+virtual int instruction_4k92(t_mem code) { return resNOT_DONE; }
+virtual int instruction_4k93(t_mem code) { return resNOT_DONE; }
+virtual int instruction_4k94(t_mem code) { return resNOT_DONE; }
+virtual int instruction_4k95(t_mem code) { return resNOT_DONE; }
+virtual int instruction_4k96(t_mem code) { return resNOT_DONE; }
+virtual int instruction_4k97(t_mem code) { return resNOT_DONE; }
+virtual int instruction_4k98(t_mem code) { return resNOT_DONE; }
+virtual int instruction_4k99(t_mem code) { return resNOT_DONE; }
+virtual int instruction_4k9a(t_mem code) { return resNOT_DONE; }
+virtual int instruction_4k9b(t_mem code) { return resNOT_DONE; }
+virtual int instruction_4k9c(t_mem code) { return resNOT_DONE; }
+virtual int instruction_4k9d(t_mem code) { return resNOT_DONE; }
+virtual int instruction_4k9e(t_mem code) { return resNOT_DONE; }
+virtual int instruction_4k9f(t_mem code) { return resNOT_DONE; }
+
+virtual int instruction_4ka0(t_mem code) { return resNOT_DONE; }
+virtual int instruction_4ka1(t_mem code) { return resNOT_DONE; }
+virtual int instruction_4ka2(t_mem code) { return resNOT_DONE; }
+virtual int instruction_4ka3(t_mem code) { return resNOT_DONE; }
+virtual int instruction_4ka4(t_mem code) { return resNOT_DONE; }
+virtual int instruction_4ka5(t_mem code) { return resNOT_DONE; }
+virtual int instruction_4ka6(t_mem code) { return resNOT_DONE; }
+virtual int instruction_4ka7(t_mem code) { return resNOT_DONE; }
+virtual int instruction_4ka8(t_mem code) { return resNOT_DONE; }
+virtual int instruction_4ka9(t_mem code) { return resNOT_DONE; }
+virtual int instruction_4kaa(t_mem code) { return resNOT_DONE; }
+virtual int instruction_4kab(t_mem code) { return resNOT_DONE; }
+virtual int instruction_4kac(t_mem code) { return resNOT_DONE; }
+virtual int instruction_4kad(t_mem code) { return resNOT_DONE; }
+virtual int instruction_4kae(t_mem code) { return resNOT_DONE; }
+
+virtual int instruction_4kb0(t_mem code) { return resNOT_DONE; }
+virtual int instruction_4kb1(t_mem code) { return resNOT_DONE; }
+virtual int instruction_4kb2(t_mem code) { return resNOT_DONE; }
+virtual int instruction_4kb3(t_mem code) { return resNOT_DONE; }
+virtual int instruction_4kb4(t_mem code) { return resNOT_DONE; }
+virtual int instruction_4kb5(t_mem code) { return resNOT_DONE; }
+virtual int instruction_4kb6(t_mem code) { return resNOT_DONE; }
+virtual int instruction_4kb8(t_mem code) { return resNOT_DONE; }
+virtual int instruction_4kb9(t_mem code) { return resNOT_DONE; }
+virtual int instruction_4kba(t_mem code) { return resNOT_DONE; }
+virtual int instruction_4kbb(t_mem code) { return resNOT_DONE; }
+virtual int instruction_4kbc(t_mem code) { return resNOT_DONE; }
+virtual int instruction_4kbd(t_mem code) { return resNOT_DONE; }
+virtual int instruction_4kbe(t_mem code) { return resNOT_DONE; }
+virtual int instruction_4kbf(t_mem code) { return resNOT_DONE; }
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/r4kwrap.cc sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/r4kwrap.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/r4kwrap.cc	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/r4kwrap.cc	2021-08-16 10:12:33.000000000 +0000
@@ -0,0 +1,115 @@
+/*
+ * Simulator of microcontrollers (r4kwrap.h)
+ *
+ * Copyright (C) 2020,2021 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#include "r4kwrap.h"
+
+int instruction_wrapper_4knone(class cl_uc *uc, t_mem code) { return resINV_INST; }
+
+int instruction_wrapper_4k42(class cl_uc *uc, t_mem code) { return ((class cl_r4k *)uc)->instruction_4k45(code); }
+int instruction_wrapper_4k45(class cl_uc *uc, t_mem code) { return ((class cl_r4k *)uc)->instruction_4k45(code); }
+int instruction_wrapper_4k48(class cl_uc *uc, t_mem code) { return ((class cl_r4k *)uc)->instruction_4k48(code); }
+int instruction_wrapper_4k4c(class cl_uc *uc, t_mem code) { return ((class cl_r4k *)uc)->instruction_4k4c(code); }
+int instruction_wrapper_4k4d(class cl_uc *uc, t_mem code) { return ((class cl_r4k *)uc)->instruction_4k4d(code); }
+
+int instruction_wrapper_4k50(class cl_uc *uc, t_mem code) { return ((class cl_r4k *)uc)->instruction_4k50(code); }
+int instruction_wrapper_4k51(class cl_uc *uc, t_mem code) { return ((class cl_r4k *)uc)->instruction_4k51(code); }
+int instruction_wrapper_4k54(class cl_uc *uc, t_mem code) { return ((class cl_r4k *)uc)->instruction_4k54(code); }
+int instruction_wrapper_4k55(class cl_uc *uc, t_mem code) { return ((class cl_r4k *)uc)->instruction_4k55(code); }
+
+int instruction_wrapper_4k60(class cl_uc *uc, t_mem code) { return ((class cl_r4k *)uc)->instruction_4k60(code); }
+int instruction_wrapper_4k61(class cl_uc *uc, t_mem code) { return ((class cl_r4k *)uc)->instruction_4k61(code); }
+int instruction_wrapper_4k62(class cl_uc *uc, t_mem code) { return ((class cl_r4k *)uc)->instruction_4k62(code); }
+int instruction_wrapper_4k63(class cl_uc *uc, t_mem code) { return ((class cl_r4k *)uc)->instruction_4k63(code); }
+int instruction_wrapper_4k65(class cl_uc *uc, t_mem code) { return ((class cl_r4k *)uc)->instruction_4k65(code); }
+int instruction_wrapper_4k6d(class cl_uc *uc, t_mem code) { return ((class cl_r4k *)uc)->instruction_4k6d(code); }
+
+int instruction_wrapper_4k7f(class cl_uc *uc, t_mem code) { return ((class cl_r4k *)uc)->instruction_4k7f(code); }
+
+int instruction_wrapper_4k81(class cl_uc *uc, t_mem code) { return ((class cl_r4k *)uc)->instruction_4k81(code); }
+int instruction_wrapper_4k82(class cl_uc *uc, t_mem code) { return ((class cl_r4k *)uc)->instruction_4k82(code); }
+int instruction_wrapper_4k83(class cl_uc *uc, t_mem code) { return ((class cl_r4k *)uc)->instruction_4k83(code); }
+int instruction_wrapper_4k84(class cl_uc *uc, t_mem code) { return ((class cl_r4k *)uc)->instruction_4k84(code); }
+int instruction_wrapper_4k85(class cl_uc *uc, t_mem code) { return ((class cl_r4k *)uc)->instruction_4k85(code); }
+int instruction_wrapper_4k86(class cl_uc *uc, t_mem code) { return ((class cl_r4k *)uc)->instruction_4k86(code); }
+int instruction_wrapper_4k87(class cl_uc *uc, t_mem code) { return ((class cl_r4k *)uc)->instruction_4k87(code); }
+int instruction_wrapper_4k89(class cl_uc *uc, t_mem code) { return ((class cl_r4k *)uc)->instruction_4k89(code); }
+int instruction_wrapper_4k8a(class cl_uc *uc, t_mem code) { return ((class cl_r4k *)uc)->instruction_4k8a(code); }
+int instruction_wrapper_4k8b(class cl_uc *uc, t_mem code) { return ((class cl_r4k *)uc)->instruction_4k8b(code); }
+int instruction_wrapper_4k8c(class cl_uc *uc, t_mem code) { return ((class cl_r4k *)uc)->instruction_4k8c(code); }
+int instruction_wrapper_4k8d(class cl_uc *uc, t_mem code) { return ((class cl_r4k *)uc)->instruction_4k8d(code); }
+int instruction_wrapper_4k8e(class cl_uc *uc, t_mem code) { return ((class cl_r4k *)uc)->instruction_4k8e(code); }
+int instruction_wrapper_4k8f(class cl_uc *uc, t_mem code) { return ((class cl_r4k *)uc)->instruction_4k8f(code); }
+
+int instruction_wrapper_4k91(class cl_uc *uc, t_mem code) { return ((class cl_r4k *)uc)->instruction_4k91(code); }
+int instruction_wrapper_4k92(class cl_uc *uc, t_mem code) { return ((class cl_r4k *)uc)->instruction_4k92(code); }
+int instruction_wrapper_4k93(class cl_uc *uc, t_mem code) { return ((class cl_r4k *)uc)->instruction_4k93(code); }
+int instruction_wrapper_4k94(class cl_uc *uc, t_mem code) { return ((class cl_r4k *)uc)->instruction_4k94(code); }
+int instruction_wrapper_4k95(class cl_uc *uc, t_mem code) { return ((class cl_r4k *)uc)->instruction_4k95(code); }
+int instruction_wrapper_4k96(class cl_uc *uc, t_mem code) { return ((class cl_r4k *)uc)->instruction_4k96(code); }
+int instruction_wrapper_4k97(class cl_uc *uc, t_mem code) { return ((class cl_r4k *)uc)->instruction_4k97(code); }
+int instruction_wrapper_4k98(class cl_uc *uc, t_mem code) { return ((class cl_r4k *)uc)->instruction_4k98(code); }
+int instruction_wrapper_4k99(class cl_uc *uc, t_mem code) { return ((class cl_r4k *)uc)->instruction_4k99(code); }
+int instruction_wrapper_4k9a(class cl_uc *uc, t_mem code) { return ((class cl_r4k *)uc)->instruction_4k9a(code); }
+int instruction_wrapper_4k9b(class cl_uc *uc, t_mem code) { return ((class cl_r4k *)uc)->instruction_4k9b(code); }
+int instruction_wrapper_4k9c(class cl_uc *uc, t_mem code) { return ((class cl_r4k *)uc)->instruction_4k9c(code); }
+int instruction_wrapper_4k9d(class cl_uc *uc, t_mem code) { return ((class cl_r4k *)uc)->instruction_4k9d(code); }
+int instruction_wrapper_4k9e(class cl_uc *uc, t_mem code) { return ((class cl_r4k *)uc)->instruction_4k9e(code); }
+int instruction_wrapper_4k9f(class cl_uc *uc, t_mem code) { return ((class cl_r4k *)uc)->instruction_4k9f(code); }
+
+int instruction_wrapper_4ka0(class cl_uc *uc, t_mem code) { return ((class cl_r4k *)uc)->instruction_4ka0(code); }
+int instruction_wrapper_4ka1(class cl_uc *uc, t_mem code) { return ((class cl_r4k *)uc)->instruction_4ka1(code); }
+int instruction_wrapper_4ka2(class cl_uc *uc, t_mem code) { return ((class cl_r4k *)uc)->instruction_4ka2(code); }
+int instruction_wrapper_4ka3(class cl_uc *uc, t_mem code) { return ((class cl_r4k *)uc)->instruction_4ka3(code); }
+int instruction_wrapper_4ka4(class cl_uc *uc, t_mem code) { return ((class cl_r4k *)uc)->instruction_4ka4(code); }
+int instruction_wrapper_4ka5(class cl_uc *uc, t_mem code) { return ((class cl_r4k *)uc)->instruction_4ka5(code); }
+int instruction_wrapper_4ka6(class cl_uc *uc, t_mem code) { return ((class cl_r4k *)uc)->instruction_4ka6(code); }
+int instruction_wrapper_4ka7(class cl_uc *uc, t_mem code) { return ((class cl_r4k *)uc)->instruction_4ka7(code); }
+int instruction_wrapper_4ka8(class cl_uc *uc, t_mem code) { return ((class cl_r4k *)uc)->instruction_4ka8(code); }
+int instruction_wrapper_4ka9(class cl_uc *uc, t_mem code) { return ((class cl_r4k *)uc)->instruction_4ka9(code); }
+int instruction_wrapper_4kaa(class cl_uc *uc, t_mem code) { return ((class cl_r4k *)uc)->instruction_4kaa(code); }
+int instruction_wrapper_4kab(class cl_uc *uc, t_mem code) { return ((class cl_r4k *)uc)->instruction_4kab(code); }
+int instruction_wrapper_4kac(class cl_uc *uc, t_mem code) { return ((class cl_r4k *)uc)->instruction_4kac(code); }
+int instruction_wrapper_4kad(class cl_uc *uc, t_mem code) { return ((class cl_r4k *)uc)->instruction_4kad(code); }
+int instruction_wrapper_4kae(class cl_uc *uc, t_mem code) { return ((class cl_r4k *)uc)->instruction_4kae(code); }
+
+int instruction_wrapper_4kb0(class cl_uc *uc, t_mem code) { return ((class cl_r4k *)uc)->instruction_4kb0(code); }
+int instruction_wrapper_4kb1(class cl_uc *uc, t_mem code) { return ((class cl_r4k *)uc)->instruction_4kb1(code); }
+int instruction_wrapper_4kb2(class cl_uc *uc, t_mem code) { return ((class cl_r4k *)uc)->instruction_4kb2(code); }
+int instruction_wrapper_4kb3(class cl_uc *uc, t_mem code) { return ((class cl_r4k *)uc)->instruction_4kb3(code); }
+int instruction_wrapper_4kb4(class cl_uc *uc, t_mem code) { return ((class cl_r4k *)uc)->instruction_4kb4(code); }
+int instruction_wrapper_4kb5(class cl_uc *uc, t_mem code) { return ((class cl_r4k *)uc)->instruction_4kb5(code); }
+int instruction_wrapper_4kb6(class cl_uc *uc, t_mem code) { return ((class cl_r4k *)uc)->instruction_4kb6(code); }
+int instruction_wrapper_4kb8(class cl_uc *uc, t_mem code) { return ((class cl_r4k *)uc)->instruction_4kb8(code); }
+int instruction_wrapper_4kb9(class cl_uc *uc, t_mem code) { return ((class cl_r4k *)uc)->instruction_4kb9(code); }
+int instruction_wrapper_4kba(class cl_uc *uc, t_mem code) { return ((class cl_r4k *)uc)->instruction_4kba(code); }
+int instruction_wrapper_4kbb(class cl_uc *uc, t_mem code) { return ((class cl_r4k *)uc)->instruction_4kbb(code); }
+int instruction_wrapper_4kbc(class cl_uc *uc, t_mem code) { return ((class cl_r4k *)uc)->instruction_4kbc(code); }
+int instruction_wrapper_4kbd(class cl_uc *uc, t_mem code) { return ((class cl_r4k *)uc)->instruction_4kbd(code); }
+int instruction_wrapper_4kbe(class cl_uc *uc, t_mem code) { return ((class cl_r4k *)uc)->instruction_4kbe(code); }
+int instruction_wrapper_4kbf(class cl_uc *uc, t_mem code) { return ((class cl_r4k *)uc)->instruction_4kbf(code); }
+
+/* End of rxk.src/r4kwrap.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/r4kwrap.h sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/r4kwrap.h
--- sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/r4kwrap.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/r4kwrap.h	2021-07-16 14:31:13.000000000 +0000
@@ -0,0 +1,119 @@
+/*
+ * Simulator of microcontrollers (r4kwrap.h)
+ *
+ * Copyright (C) 2020,2021 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef R4KWRAP_HEADER
+#define R4KWRAP_HEADER
+
+#include "r4kcl.h"
+
+extern int instruction_wrapper_4knone(class cl_uc *uc, t_mem code);
+
+extern int instruction_wrapper_4k45(class cl_uc *uc, t_mem code);
+extern int instruction_wrapper_4k48(class cl_uc *uc, t_mem code);
+extern int instruction_wrapper_4k4c(class cl_uc *uc, t_mem code);
+extern int instruction_wrapper_4k4d(class cl_uc *uc, t_mem code);
+
+extern int instruction_wrapper_4k50(class cl_uc *uc, t_mem code);
+extern int instruction_wrapper_4k51(class cl_uc *uc, t_mem code);
+extern int instruction_wrapper_4k54(class cl_uc *uc, t_mem code);
+extern int instruction_wrapper_4k55(class cl_uc *uc, t_mem code);
+
+extern int instruction_wrapper_4k60(class cl_uc *uc, t_mem code);
+extern int instruction_wrapper_4k61(class cl_uc *uc, t_mem code);
+extern int instruction_wrapper_4k62(class cl_uc *uc, t_mem code);
+extern int instruction_wrapper_4k63(class cl_uc *uc, t_mem code);
+extern int instruction_wrapper_4k65(class cl_uc *uc, t_mem code);
+extern int instruction_wrapper_4k6d(class cl_uc *uc, t_mem code);
+
+extern int instruction_wrapper_4k7f(class cl_uc *uc, t_mem code);
+
+extern int instruction_wrapper_4k81(class cl_uc *uc, t_mem code);
+extern int instruction_wrapper_4k82(class cl_uc *uc, t_mem code);
+extern int instruction_wrapper_4k83(class cl_uc *uc, t_mem code);
+extern int instruction_wrapper_4k84(class cl_uc *uc, t_mem code);
+extern int instruction_wrapper_4k85(class cl_uc *uc, t_mem code);
+extern int instruction_wrapper_4k86(class cl_uc *uc, t_mem code);
+extern int instruction_wrapper_4k87(class cl_uc *uc, t_mem code);
+extern int instruction_wrapper_4k89(class cl_uc *uc, t_mem code);
+extern int instruction_wrapper_4k8a(class cl_uc *uc, t_mem code);
+extern int instruction_wrapper_4k8b(class cl_uc *uc, t_mem code);
+extern int instruction_wrapper_4k8c(class cl_uc *uc, t_mem code);
+extern int instruction_wrapper_4k8d(class cl_uc *uc, t_mem code);
+extern int instruction_wrapper_4k8e(class cl_uc *uc, t_mem code);
+extern int instruction_wrapper_4k8f(class cl_uc *uc, t_mem code);
+
+extern int instruction_wrapper_4k91(class cl_uc *uc, t_mem code);
+extern int instruction_wrapper_4k92(class cl_uc *uc, t_mem code);
+extern int instruction_wrapper_4k93(class cl_uc *uc, t_mem code);
+extern int instruction_wrapper_4k94(class cl_uc *uc, t_mem code);
+extern int instruction_wrapper_4k95(class cl_uc *uc, t_mem code);
+extern int instruction_wrapper_4k96(class cl_uc *uc, t_mem code);
+extern int instruction_wrapper_4k97(class cl_uc *uc, t_mem code);
+extern int instruction_wrapper_4k98(class cl_uc *uc, t_mem code);
+extern int instruction_wrapper_4k99(class cl_uc *uc, t_mem code);
+extern int instruction_wrapper_4k9a(class cl_uc *uc, t_mem code);
+extern int instruction_wrapper_4k9b(class cl_uc *uc, t_mem code);
+extern int instruction_wrapper_4k9c(class cl_uc *uc, t_mem code);
+extern int instruction_wrapper_4k9d(class cl_uc *uc, t_mem code);
+extern int instruction_wrapper_4k9e(class cl_uc *uc, t_mem code);
+extern int instruction_wrapper_4k9f(class cl_uc *uc, t_mem code);
+
+extern int instruction_wrapper_4ka0(class cl_uc *uc, t_mem code);
+extern int instruction_wrapper_4ka1(class cl_uc *uc, t_mem code);
+extern int instruction_wrapper_4ka2(class cl_uc *uc, t_mem code);
+extern int instruction_wrapper_4ka3(class cl_uc *uc, t_mem code);
+extern int instruction_wrapper_4ka4(class cl_uc *uc, t_mem code);
+extern int instruction_wrapper_4ka5(class cl_uc *uc, t_mem code);
+extern int instruction_wrapper_4ka6(class cl_uc *uc, t_mem code);
+extern int instruction_wrapper_4ka7(class cl_uc *uc, t_mem code);
+extern int instruction_wrapper_4ka8(class cl_uc *uc, t_mem code);
+extern int instruction_wrapper_4ka9(class cl_uc *uc, t_mem code);
+extern int instruction_wrapper_4kaa(class cl_uc *uc, t_mem code);
+extern int instruction_wrapper_4kab(class cl_uc *uc, t_mem code);
+extern int instruction_wrapper_4kac(class cl_uc *uc, t_mem code);
+extern int instruction_wrapper_4kad(class cl_uc *uc, t_mem code);
+extern int instruction_wrapper_4kae(class cl_uc *uc, t_mem code);
+
+extern int instruction_wrapper_4kb0(class cl_uc *uc, t_mem code);
+extern int instruction_wrapper_4kb1(class cl_uc *uc, t_mem code);
+extern int instruction_wrapper_4kb2(class cl_uc *uc, t_mem code);
+extern int instruction_wrapper_4kb3(class cl_uc *uc, t_mem code);
+extern int instruction_wrapper_4kb4(class cl_uc *uc, t_mem code);
+extern int instruction_wrapper_4kb5(class cl_uc *uc, t_mem code);
+extern int instruction_wrapper_4kb6(class cl_uc *uc, t_mem code);
+extern int instruction_wrapper_4kb8(class cl_uc *uc, t_mem code);
+extern int instruction_wrapper_4kb9(class cl_uc *uc, t_mem code);
+extern int instruction_wrapper_4kba(class cl_uc *uc, t_mem code);
+extern int instruction_wrapper_4kbb(class cl_uc *uc, t_mem code);
+extern int instruction_wrapper_4kbc(class cl_uc *uc, t_mem code);
+extern int instruction_wrapper_4kbd(class cl_uc *uc, t_mem code);
+extern int instruction_wrapper_4kbe(class cl_uc *uc, t_mem code);
+extern int instruction_wrapper_4kbf(class cl_uc *uc, t_mem code);
+
+#endif
+
+/* End of rxk.src/r4kwrap.h */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/r5k.cc sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/r5k.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/r5k.cc	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/r5k.cc	2021-07-16 14:31:13.000000000 +0000
@@ -0,0 +1,43 @@
+/*
+ * Simulator of microcontrollers (r5k.cc)
+ *
+ * Copyright (C) 2020,2021 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#include "r5kcl.h"
+
+
+cl_r5k::cl_r5k(class cl_sim *asim):
+  cl_r4k(asim)
+{
+}
+
+const char *
+cl_r5k::id_string(void)
+{
+  return "R5K";
+}
+
+
+/* End of rxk.src/r5k.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/r5kcl.h sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/r5kcl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/r5kcl.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/r5kcl.h	2021-09-12 15:51:43.000000000 +0000
@@ -0,0 +1,52 @@
+/*
+ * Simulator of microcontrollers (r5kcl.h)
+ *
+ * Copyright (C) 2020,2021 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef R5KCL_HEADER
+#define R5KCL_HEADER
+
+#include "r4kcl.h"
+
+
+class cl_r5k: public cl_r4k
+{
+ public:
+  cl_r5k(class cl_sim *asim);
+  virtual const char *id_string(void);
+
+  virtual void tick5p1(int n) { tick(n+1); }
+  virtual void tick5p2(int n) { tick(n+2); }
+  virtual void tick5p3(int n) { tick(n+3); }
+  virtual void tick5p9(int n) { tick(n+9); }
+  virtual void tick5p12(int n) { tick(n+12); }
+  virtual void tick5m1(int n) { tick(n  ); }
+  virtual void tick5m2(int n) { tick(n  ); }
+};
+
+
+#endif
+
+/* End of rxk.src/r5kcl.h */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/r6k.cc sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/r6k.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/r6k.cc	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/r6k.cc	2021-07-16 14:31:13.000000000 +0000
@@ -0,0 +1,43 @@
+/*
+ * Simulator of microcontrollers (r6k.cc)
+ *
+ * Copyright (C) 2020,2021 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#include "r6kcl.h"
+
+
+cl_r6k::cl_r6k(class cl_sim *asim):
+  cl_r5k(asim)
+{
+}
+
+const char *
+cl_r6k::id_string(void)
+{
+  return "R6K";
+}
+
+
+/* End of rxk.src/r6k.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/r6kcl.h sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/r6kcl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/r6kcl.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/r6kcl.h	2021-07-16 14:31:13.000000000 +0000
@@ -0,0 +1,44 @@
+/*
+ * Simulator of microcontrollers (r6kcl.h)
+ *
+ * Copyright (C) 2020,2021 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef R6KCL_HEADER
+#define R6KCL_HEADER
+
+#include "r5kcl.h"
+
+
+class cl_r6k: public cl_r5k
+{
+ public:
+  cl_r6k(class cl_sim *asim);
+  virtual const char *id_string(void);
+};
+
+
+#endif
+
+/* End of rxk.src/r6kcl.h */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/rmem.cc sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/rmem.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/rmem.cc	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/rmem.cc	2021-10-29 17:39:15.000000000 +0000
@@ -0,0 +1,289 @@
+/*
+ * Simulator of microcontrollers (@@F@@)
+ *
+ * Copyright (C) 2020,2021 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+
+#include "rmemcl.h"
+
+
+cl_ras::cl_ras(chars id, class cl_memory_chip *achip):
+  cl_address_space(id, 0, 0x10000, 8)
+{
+  chip= achip;
+  segsize= 0xff;
+  dataseg= 0;
+  stackseg= 0;
+}
+
+int
+cl_ras::init(void)
+{
+  cl_address_space::init();
+  return 0;
+}
+
+
+/* 
+ * Convert LA (logical addr) into PA (physical addr)
+ */
+
+t_addr
+cl_ras::log2phy(t_addr log)
+{
+  t_addr x, y;
+  x= segsize>>4;
+  y= segsize&0xf;
+  if (log >= 0xe000)
+    // extended program space
+    return log + (xpc.lxpc<<12);
+  else if (log >= (x<<12))
+    // stack space
+    return log + (stackseg<<12);
+  else if (log >= (y<<12))
+      // data space
+      return log + (dataseg<<12);
+  else
+    // code space
+    return log;
+}
+
+
+/*
+ * Convert Px register content into PA (physical addr)
+ */
+
+t_addr
+cl_ras::px2phy(u32_t px)
+{
+  if ((px & 0xffff0000) == 0xffff0000)
+    {
+      return log2phy(px & 0xffff);
+    }
+  return px;
+}
+
+
+/*
+ * Read from logical addr
+ */
+
+t_mem
+cl_ras::read(t_addr addr)
+{
+  if (addr >= size)
+    {
+      err_inv_addr(addr);
+      return dummy->read();
+    }
+  return cella[addr].read();
+}
+
+
+/*
+ * Read from content of Px reg
+ */
+
+t_mem
+cl_ras::pxread(t_addr pxaddr)
+{
+  if ((pxaddr & 0xffff0000) == 0xffff0000)
+    return read(pxaddr & 0xffff);
+  return phread(pxaddr);
+}
+
+t_mem
+cl_ras::get(t_addr addr)
+{
+  if (addr >= size)
+    {
+      err_inv_addr(addr);
+      return dummy->get();
+    }
+  return cella[addr].get();
+}
+
+
+/*
+ * Get data at physical address
+ */
+
+t_mem
+cl_ras::phget(t_addr phaddr)
+{
+  if (phaddr >= chip->get_size())
+    {
+      err_inv_addr(phaddr);
+      return dummy->read();
+    }
+  u8_t *slot= (u8_t*)(chip->get_slot(phaddr));
+  return *slot;
+}
+
+
+/* 
+ * Write at logical address
+ */
+
+t_mem
+cl_ras::write(t_addr addr, t_mem val)
+{
+  if (addr >= size)
+    {
+      err_inv_addr(addr);
+      return dummy->write(val);
+    }
+  return cella[addr].write(val);
+}
+
+
+/*
+ * Write at content of Px reg
+ */
+
+t_mem
+cl_ras::pxwrite(t_addr pxaddr, t_mem val)
+{
+  if ((pxaddr & 0xffff0000) == 0xffff0000)
+    return write(pxaddr & 0xffff, val);
+  return phwrite(pxaddr, val);
+}
+
+
+/*
+ * Set at LA
+ */
+
+void
+cl_ras::set(t_addr addr, t_mem val)
+{
+  if (addr >= size)
+    {
+      err_inv_addr(addr);
+      dummy->set(val);
+    }
+  cella[addr].set(val);
+}
+
+
+/*
+ * Set at PA
+ */
+
+void
+cl_ras::phset(t_addr phaddr, t_mem val)
+{
+  if (phaddr >- chip->get_size())
+    {
+      err_inv_addr(phaddr);
+      dummy->set(val);
+    }
+  u8_t *slot= (u8_t*)(chip->get_slot(phaddr));
+  *slot= val;
+}
+
+
+/*
+ * Download at PA
+ */
+
+void
+cl_ras::download(t_addr phaddr, t_mem val)
+{
+  if (phaddr >= chip->get_size())
+    {
+      err_inv_addr(phaddr);
+      dummy->set(val);
+    }
+  chip->set(phaddr, val);
+}
+
+
+/*
+ * Decode all logical slots
+ */
+
+void
+cl_ras::re_decode(void)
+{
+  t_addr a;
+  for (a= 0; a < get_size(); a++)
+    {
+      t_addr ph= log2phy(a);
+      void *slot= chip->get_slot(ph);
+      cella[a].decode(slot);
+    }
+}
+
+
+/*
+ * Set segment registers: xpc, segsize, dataseg, stackseg
+ */
+
+void
+cl_ras::set_xpc(u8_t val)
+{
+  xpc.r.xpc= val;
+  re_decode();
+}
+
+void
+cl_ras::set_lxpc(u16_t val)
+{
+  xpc.lxpc= val;
+  re_decode();
+}
+
+void
+cl_ras::set_segsize(u8_t val)
+{
+  if (segsize != val)
+    {
+      segsize= val;
+      re_decode();
+    }
+}
+
+void
+cl_ras::set_dataseg(u16_t val)
+{
+  val&= 0xfff;
+  if (dataseg != val)
+    {
+      dataseg= val&0xfff;
+      re_decode();
+    }
+}
+
+void
+cl_ras::set_stackseg(u16_t val)
+{
+  val&= 0xfff;
+  if (stackseg != val)
+    {
+      stackseg= val;
+      re_decode();
+    }
+}
+
+/* End of rxk.src/rmem.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/rmemcl.h sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/rmemcl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/rmemcl.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/rmemcl.h	2021-08-20 12:29:31.000000000 +0000
@@ -0,0 +1,77 @@
+/*
+ * Simulator of microcontrollers (@@F@@)
+ *
+ * Copyright (C) 2021,2021 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+
+#ifndef RMEMCL_HEADER
+#define RMEMCL_HEADER
+
+#include "rtypes.h"
+#include "memcl.h"
+
+
+class cl_ras: public cl_address_space
+{
+public:
+  class cl_memory_chip *chip;
+protected:
+  RP(xpc,lxpc,hxpc,xpc);
+protected:
+  u8_t segsize;
+  u16_t dataseg, stackseg;
+public:
+  cl_ras(chars id, class cl_memory_chip *achip);
+  virtual int init(void);
+public:
+  virtual t_addr log2phy(t_addr log);
+  virtual t_addr px2phy(u32_t px);
+  virtual t_mem read(t_addr addr);
+  virtual t_mem phread(t_addr phaddr) { return phget(phaddr); }
+  virtual t_mem pxread(t_addr pxaddr);
+  virtual t_mem get(t_addr addr);
+  virtual t_mem phget(t_addr phaddr);
+  virtual t_mem write(t_addr addr, t_mem val);
+  virtual t_mem phwrite(t_addr phaddr, t_mem val) { set(phaddr, val); return val; }
+  virtual t_mem pxwrite(t_addr pxaddr, t_mem val);
+  virtual void set(t_addr addr, t_mem val);
+  virtual void phset(t_addr phaddr, t_mem val);
+  virtual void download(t_addr phaddr, t_mem val);
+
+  virtual void re_decode(void);
+  virtual u8_t *aof_xpc(void) { return &(xpc.r.xpc); }
+  virtual u16_t *aof_lxpc(void) { return &(xpc.lxpc); }
+  virtual u16_t get_xpc() { return (xpc.lxpc); }
+  virtual void set_xpc(u8_t val);
+  virtual void set_lxpc(u16_t val);
+  virtual void set_segsize(u8_t val);
+  virtual void set_dataseg(u16_t val);
+  virtual void set_stackseg(u16_t val);
+  virtual u16_t get_dataseg() { return dataseg; }
+  virtual u16_t get_stackseg() { return stackseg; }
+  virtual u8_t get_segsize() { return segsize; }
+};
+
+#endif
+
+/* End of rxk.src/rmemcl.h */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/rtypes.h sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/rtypes.h
--- sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/rtypes.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/rtypes.h	2021-08-20 18:40:35.000000000 +0000
@@ -0,0 +1,71 @@
+/*
+ * Simulator of microcontrollers (rtypes.h)
+ *
+ * Copyright (C) 2020,2021 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef RTYPES_HEADER
+#define RTYPES_HEADER
+
+#ifdef WORDS_BIGENDIAN
+#define RP(N,N16,NH,NL) union			\
+		      {				\
+			u16_t N16;		\
+			struct {		\
+			  u8_t NH;		\
+			  u8_t NL;		\
+			} r;			\
+  } N
+#define R32(N,N32,N16H,N16L,NHH,NHL,NLH,NLL)	\
+  union						\
+  {						\
+  u32_t N32;					\
+  struct {					\
+    RP(r16h,N16H,NHH,NHL);			\
+    RP(r16l,N16L,NLH,NLL);			\
+  } r32;					\
+  } N
+#else
+#define RP(N,N16,NH,NL) union			\
+		      {				\
+			u16_t N16;		\
+			struct {		\
+			  u8_t NL;		\
+			  u8_t NH;		\
+			} r;			\
+  } N
+#define R32(N,N32,N16H,N16L,NHH,NHL,NLH,NLL)	\
+  union						\
+  {						\
+  u32_t N32;					\
+  struct {					\
+    RP(r16l,N16L,NLH,NLL);			\
+    RP(r16h,N16H,NHH,NHL);			\
+  } r32;					\
+  } N
+#endif
+
+#endif
+
+/* End of rxk.src/rtypes.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/rxk.cc sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/rxk.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/rxk.cc	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/rxk.cc	2022-01-18 21:40:45.000000000 +0000
@@ -0,0 +1,979 @@
+/*
+ * Simulator of microcontrollers (rxk.cc)
+ *
+ * Copyright (C) 2020,2021 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#include 
+#include 
+
+#include "globals.h"
+#include "utils.h"
+
+#include "dregcl.h"
+
+#include "glob.h"
+#include "gp0m3.h"
+#include "gpedm3.h"
+#include "gpddm3.h"
+#include "rmemcl.h"
+#include "ddwrap.h"
+#include "edwrap.h"
+
+#include "rxkcl.h"
+
+
+cl_rxk_base::cl_rxk_base(class cl_sim *asim):
+  cl_uc(asim)
+{
+}
+
+cl_rxk::cl_rxk(class cl_sim *asim):
+  cl_rxk_base(asim)
+{
+  altd= 0;
+  cRtab[0]= &cB;
+  cRtab[1]= &cC;
+  cRtab[2]= &cD;
+  cRtab[3]= &cE;
+  cRtab[4]= &cH;
+  cRtab[5]= &cL;
+  cRtab[7]= &cA;
+  caRtab[0]= &caB;
+  caRtab[1]= &caC;
+  caRtab[2]= &caD;
+  caRtab[3]= &caE;
+  caRtab[4]= &caH;
+  caRtab[5]= &caL;
+  caRtab[7]= &caA;
+}
+
+int
+cl_rxk::init(void)
+{
+  cl_uc::init();
+  altd= prefix= false;
+  fill_def_wrappers(itab);
+  fill_dd_wrappers(itab_dd);
+  fill_ed_wrappers(itab_ed);
+  
+  set_xtal(1000000);
+
+#define RCV(R) reg_cell_var(&c ## R , &r ## R , "" #R "" , "CPU register " #R "")
+  RCV(A);
+  RCV(aA);
+  RCV(F);
+  RCV(aF);
+  RCV(AF);
+  RCV(aAF);
+  RCV(B);
+  RCV(aB);
+  RCV(C);
+  RCV(aC);
+  RCV(BC);
+  RCV(aBC);
+  RCV(D);
+  RCV(aD);
+  RCV(E);
+  RCV(aE);
+  RCV(DE);
+  RCV(aDE);
+  RCV(H);
+  RCV(aH);
+  RCV(L);
+  RCV(aL);
+  RCV(HL);
+  RCV(aHL);
+
+  RCV(IX);
+  RCV(IY);
+  RCV(SP);
+
+  RCV(IP);
+  RCV(IIR);
+  RCV(EIR);
+#undef RCV
+
+  XPC= new cl_cell8(8);
+  reg_cell_var(XPC, mem->aof_xpc(),
+  	       "XPC", "MMU register: XPC");
+  cpu->register_cell(XPC);
+  
+  cIR= &cIX;
+  
+  ioi->set(0x11, 0); // stackseg
+  ioi->set(0x12, 0); // dataseg
+  ioi->set(0x13, 0xff); // segsize
+  mem->re_decode();
+  
+  return 0;
+}
+
+
+const char *
+cl_rxk::id_string(void)
+{
+  return "RXK";
+}
+
+void
+cl_rxk::reset(void)
+{
+  cl_uc::reset();
+
+  // MMU reset
+  mem->set_dataseg(0);
+  mem->set_segsize(0xff);
+  mem->set_stackseg(0);
+  mem->set_xpc(0);
+
+  rIP= 0xff;
+  rIIR= 0;
+  rEIR= 0;
+  rSP= 0;
+}
+
+  
+void
+cl_rxk::set_PC(t_addr addr)
+{
+  PC= addr;
+}
+
+void
+cl_rxk::mk_hw_elements(void)
+{
+  class cl_hw *h;
+  
+  cl_uc::mk_hw_elements();
+
+  add_hw(h= new cl_dreg(this, 0, "dreg"));
+  h->init();
+}
+
+void
+cl_rxk::make_cpu_hw(void)
+{
+  add_hw(cpu= new cl_rxk_cpu(this));
+  cpu->init();
+}
+
+void
+cl_rxk::make_memories(void)
+{
+  class cl_memory_chip *chip;
+  class cl_address_space *as;
+  class cl_address_decoder *ad;
+
+  chip= new cl_chip8("rom_chip", chip_size(), 8, 0);
+  chip->init();
+  memchips->add(chip);
+
+  rwas= rom= as= mem= new cl_ras("rom", chip);
+  as->init();
+  address_spaces->add(as);
+
+  /* IO */
+  ioi= as= new cl_address_space("ioi", 0, 0x10000, 8);
+  as->init();
+  address_spaces->add(as);
+
+  chip= new cl_chip8("ioi_chip", 0x10000, 8);
+  chip->init();
+  memchips->add(chip);
+  ad= new cl_address_decoder(as,
+			     chip, 0, 0xffff, 0);
+  ad->init();
+  as->decoders->add(ad);
+  ad->activate(0);
+
+  ioe= as= new cl_address_space("ioe", 0, 0x10000, 8);
+  as->init();
+  address_spaces->add(as);
+
+  chip= new cl_chip8("ioe_chip", 0x10000, 8);
+  chip->init();
+  memchips->add(chip);
+  ad= new cl_address_decoder(as,
+			     chip, 0, 0xffff, 0);
+  ad->init();
+  as->decoders->add(ad);
+  ad->activate(0);
+}
+
+/*
+struct dis_entry *
+cl_rxk::dis_tbl(void)
+{
+  return(disass_rxk);
+}
+*/
+
+struct dis_entry *
+cl_rxk::dis_entry(t_addr addr)
+{
+  u8_t code= rom->get(addr);
+  int i;
+  struct dis_entry *dt;
+  i= 0;
+
+  if (code == 0xed)
+    {
+      dt= disass_pedm3;
+      code= rom->get(addr+1);
+      while (((code & dt[i].mask) != dt[i].code) &&
+	     dt[i].mnemonic)
+	i++;
+      if (dt[i].mnemonic != NULL)
+	return &dt[i];
+      return NULL;
+    }
+  if ((code & 0xdd) == 0xdd)
+    {
+      if (code == 0xdd)
+	{
+	  cIR= &cIX;
+	}
+      else
+	{
+	  cIR= &cIY;
+	}
+      dt= disass_pddm3;
+      code= rom->get(addr+1);
+      while (((code & dt[i].mask) != dt[i].code) &&
+	     dt[i].mnemonic)
+	i++;
+      if (dt[i].mnemonic != NULL)
+	return &dt[i];
+      return NULL;
+    }
+  
+  dt= disass_rxk;
+  while (((code & dt[i].mask) != dt[i].code) &&
+	 dt[i].mnemonic)
+    i++;
+  if (dt[i].mnemonic != NULL)
+    return &dt[i];
+
+  dt= disass_p0m3;
+  i= 0;
+  while (((code & dt[i].mask) != dt[i].code) &&
+	 dt[i].mnemonic)
+    i++;
+  if (dt[i].mnemonic != NULL)
+    return &dt[i];
+  
+  return &dt[i];
+}
+
+char *
+cl_rxk::disassc(t_addr addr, chars *comment)
+{
+  chars work, temp;
+  const char *b, *nIR;
+  t_mem code= rom->get(addr);
+  struct dis_entry *dt;//= dis_tbl();//, *dis_e;
+  int i;
+  bool first, dd;
+  unsigned int x, h, l;
+  //t_addr start_at= addr;
+  
+  if (code == 0xcb)
+    return disassc_cb(addr, comment);
+  
+  dt= dis_entry(addr);
+  if (code == 0xed)
+    code= rom->get(++addr);
+  else if ((code == 0xdd) || (code == 0xfd))
+    {
+      code= rom->get(++addr);
+      if (code == 0xcb)
+	return disassc_dd_cb(addr-1, comment);
+    }
+  if (!dt)
+    return strdup("-- unknown");
+
+  if (dt->mnemonic == NULL)
+    return strdup("-- UNKNOWN/INVALID");
+  b= dt->mnemonic;
+
+  nIR= (cIR==&cIX)?"IX":"IY";
+  dd = (cIR==&cIX);
+  first= true;
+  work= "";
+  for (i=0; b[i]; i++)
+    {
+      if ((b[i] == ' ') && first)
+	{
+	  first= false;
+	  while (work.len() < 6) work.append(' ');
+	}
+      if (b[i] == '%')
+	{
+	  temp= "";
+	  i++;
+	  switch (b[i])
+	    {
+	    case 'l': // 24 bit unsigned
+	      l= rom->get(++addr);
+	      h= rom->get(++addr);
+	      x= rom->get(++addr);
+	      work.appendf("0x%06x", x*0x10000+h*256+l);
+	      break;
+	    case 'w': // 16 bit unsigned
+	      l= rom->get(++addr);
+	      h= rom->get(++addr);
+	      work.appendf("0x%04x", h*256+l);
+	      break;
+	    case 'b': // 8 bit unsigned
+	      l= rom->get(++addr);
+	      work.appendf("0x%02x", l);
+	      break;
+	    case 'd': // 8 bit signed
+	      {
+		i8_t r= rom->read(++addr);
+		work.appendf("%+d", r);
+	      }
+	      break;
+	    case 'r': // 8 bit relative jump
+	      {
+		i8_t r= rom->get(++addr);
+		t_addr a= addr + 1 + r;
+		work.appendf("0x%04x", AU16(a));
+	      }
+	      break;
+	    case 'R': // 16 bit signed PC relative
+	      {
+		u8_t el, eh;
+		el= rom->get(++addr);
+		eh= rom->get(++addr);
+		i16_t ee= eh*256+el;
+		t_addr a= (addr+1 + ee) & 0xffff;
+		work.appendf("0x%04x", a);
+		break;
+	      }
+	    case 'I':
+	      work.appendf("%s", nIR);
+	      break;
+	    case '3':
+	      disass_irr(&work, dd);
+	      break;
+	    case 'n':
+	      disass_irrl(&work, dd);
+	      break;
+	    case 'J':
+	      if (cIR == &cIX)
+		work.append("HL");
+	      else
+		work.append("IY");
+	      break;
+	    case 'X': // LXPC 0 1 2 3 xpl xph
+	      {
+		u16_t x;
+		x= rom->read(addr+4) * 256;
+		x+= rom->read(addr+3);
+		work.appendf("0x%03x", x);
+		break;
+	      }
+	    case 'x': // 32 bit unsigned
+	      {
+		u32_t n, m, l, h;
+		n= rom->get(++addr);
+		m= rom->get(++addr);
+		l= rom->get(++addr);
+		h= rom->get(++addr);
+		work.appendf("0x%08x", (h<<24)+(l<<16)+(m<<8)+n);
+	      }
+	    }
+	  if (comment && temp.nempty())
+	    comment->append(temp);
+	}
+      else
+	work+= b[i];
+    }
+
+  return(strdup(work.c_str()));
+}
+
+char *
+cl_rxk::disassc_cb(t_addr addr, chars *comment)
+{
+  u8_t code= rom->get(++addr);
+  u8_t x, y, z;
+  chars work, temp;
+  char b[100];
+  bool first= true;
+  int i;
+  const char *r[8]= { "B","C","D","E","H","L","(HL)","A" };
+
+  x= code>>6;
+  y= (code>>3)&7;
+  z= code&7;
+  switch (x)
+    {
+    case 0:
+      switch (y)
+	{
+	case 0: strcpy(b, "RLC %r"); break;
+	case 1: strcpy(b, "RRC %r"); break;
+	case 2: strcpy(b, "RL %r"); break;
+	case 3: strcpy(b, "RR %r"); break;
+	case 4: strcpy(b, "SLA %r"); break;
+	case 5: strcpy(b, "SRA %r"); break;
+	case 6: return strdup("-- UNKNOWN/INVALID");
+	case 7: strcpy(b, "SRL %r"); break;
+	}
+      break;
+    case 1:
+      strcpy(b, "BIT %y,%r");
+      break;
+    case 2:
+      strcpy(b, "RES %y,%r");
+      break;
+    case 3:
+      strcpy(b, "SET %y,%r");
+      break;
+    }
+  temp= "";
+  work= "";
+  for (i= 0; b[i]; i++)
+    {
+      if ((b[i] == ' ') && first)
+	{
+	  first= false;
+	  while (work.len() < 6) work.append(' ');
+	}
+      if (b[i] == '%')
+	{
+	  temp= "";
+	  i++;
+	  switch (b[i])
+	    {
+	    case 'y': work.appendf("%d", y); break;
+	    case 'r': work.append(r[z]); break;
+	    }
+	  if (comment && temp.nempty())
+	    comment->append(temp);
+	}
+      else
+	work+= b[i];
+    }
+
+  return(strdup(work.c_str()));
+}
+
+char *
+cl_rxk::disassc_dd_cb(t_addr addr, chars *comment)
+{
+  u8_t d, code;
+  u8_t x, y, z;
+  chars work, temp;
+  char b[100];
+  bool first= true;
+  int i;
+  t_addr a;
+  
+  a= addr+2;
+  d= rom->get(a);
+  a++;
+  code= rom->get(a);
+  
+  x= code>>6;
+  y= (code>>3)&7;
+  z= code&7;
+  if ((z != 6) || (code == 0x36))
+    {
+      temp.appendf("-- dd/cb (addr=%x,d=%02x,code=%02x,a=%x) UNKNOWN/INVALID", addr, d, code, a);
+      return strdup(temp.c_str());
+    }
+
+  switch (x)
+    {
+    case 0:
+      switch (y)
+	{
+	case 0: strcpy(b, "RLC (%I+%d)"); break;
+	case 1: strcpy(b, "RRC (%I+%d)"); break;
+	case 2: strcpy(b, "RL (%I+%d)"); break;
+	case 3: strcpy(b, "RR (%I+%d)"); break;
+	case 4: strcpy(b, "SLA (%I+%d)"); break;
+	case 5: strcpy(b, "SRA (%I+%d)"); break;
+	case 6: return strdup("-- dd/cb UNKNOWN/INVALID");
+	case 7: strcpy(b, "SRL (%I+%d)"); break;
+	}
+      break;
+    case 1:
+      strcpy(b, "BIT %y,(%I+%d)");
+      break;
+    case 2:
+      strcpy(b, "RES %y,(%I+%d)");
+      break;
+    case 3:
+      strcpy(b, "SET %y,(%I+%d)");
+      break;
+    }
+  temp= "";
+  work= "";
+  for (i= 0; b[i]; i++)
+    {
+      if ((b[i] == ' ') && first)
+	{
+	  first= false;
+	  while (work.len() < 6) work.append(' ');
+	}
+      if (b[i] == '%')
+	{
+	  temp= "";
+	  i++;
+	  switch (b[i])
+	    {
+	    case 'y': work.appendf("%d", y); break;
+	    case 'I':
+	      if (cIR == &cIX)
+		work+= "IX";
+	      else
+		work+= "IY";
+	      break;
+	    case 'b':
+	      work.appendf("0x%02x", d);
+	      break;
+	    case 'd':
+	      work.appendf("%d", d);
+	      break;
+	    }
+	  if (comment && temp.nempty())
+	    comment->append(temp);
+	}
+      else
+	work+= b[i];
+    }
+  return strdup(work.c_str());
+}
+
+
+int
+cl_rxk::inst_length(t_addr addr)
+{
+  u8_t code= rom->get(addr);
+  if (code == 0xcb)
+    return 2;
+  if ((code == 0xdd) || (code == 0xfd))
+    {
+      if (rom->get(addr+1) == 0xcb)
+	return 4;
+    }
+  struct dis_entry *dt= dis_entry(addr);
+  if (!dt) return 1;
+  if (dt->mnemonic == NULL) return 1;
+  return dt->length;
+}
+
+
+static FILE *log_file= NULL;
+static unsigned int cyc= 0;
+
+void
+cl_rxk::save_hist()
+{
+  cl_uc::save_hist();
+  if (juj&2)
+    {
+      if (log_file==NULL && PC==0x16) log_file= fopen("log.txt","w");
+      if (log_file!=NULL) {
+	fprintf(log_file, "%6u %06x ", cyc, AU(PC));
+	fprintf(log_file, "%02x %02x ", rA, rF&0xc1);
+	fprintf(log_file, "%04x %04x %04x ", rBC, rDE, rHL);
+	fprintf(log_file, "%04x %04x %04x ", rIX, rIY, rSP);
+	fprintf(log_file, "\n");
+	cyc++;
+      }
+    }
+}
+
+void
+cl_rxk::print_regs(class cl_console_base *con)
+{
+  if (jaj)
+    {
+      con->dd_color("answer");
+      con->dd_printf("SZ-A-PNC  Flags= 0x%02x %3d %c  ",
+		     rF, rF, isprint(rF)?rF:'.');
+      con->dd_printf("A= 0x%02x %3d %c\n",
+		     rA, rA, isprint(rA)?rA:'.');
+      con->dd_printf("%c%c-%c-%c%c%c\n",
+		     (rF&flagS)?'1':'0',
+		     (rF&flagZ)?'1':'0',
+		     'x',//(rF&flagA)?'1':'0',
+		     (rF&flagV)?'1':'0',
+		     'x',//(rF&BIT_N)?'1':'0',
+		     (rF&flagC)?'1':'0');
+      con->dd_printf("BC= 0x%04x [BC]= %02x %3d %c  ",
+		     rBC, rom->get(rBC), rom->get(rBC),
+		     isprint(rom->get(rBC))?rom->get(rBC):'.');
+      con->dd_printf("DE= 0x%04x [DE]= %02x %3d %c  ",
+		     rDE, rom->get(rDE), rom->get(rDE),
+		     isprint(rom->get(rDE))?rom->get(rDE):'.');
+      con->dd_printf("HL= 0x%04x [HL]= %02x %3d %c\n",
+		     rHL, rom->get(rHL), rom->get(rHL),
+		     isprint(rom->get(rHL))?rom->get(rHL):'.');
+      con->dd_printf("IX= 0x%04x [IX]= %02x %3d %c  ",
+		     rIX, rom->get(rIX), rom->get(rIX),
+		     isprint(rom->get(rIX))?rom->get(rIX):'.');
+      con->dd_printf("IY= 0x%04x [IY]= %02x %3d %c  ",
+		     rIY, rom->get(rIY), rom->get(rIY),
+		     isprint(rom->get(rIY))?rom->get(rIY):'.');
+      con->dd_printf("SP= 0x%04x [SP]= %02x %3d %c\n",
+		     rSP, rom->get(rSP), rom->get(rSP),
+		     isprint(rom->get(rSP))?rom->get(rSP):'.');
+      //con->dd_printf("SP limit= 0x%04x\n", AU(sp_limit));
+      print_disass(PC, con);
+      return;
+    }
+  con->dd_color("answer");
+  con->dd_printf("A= 0x%02x %3d %c  ",
+                 rA, rA, isprint(rA)?rA:'.');
+  con->dd_printf("F= "); con->print_bin(rF, 8);
+  con->dd_printf(" 0x%02x %3d %c", rF, rF, isprint(rF)?rF:'.');
+  con->dd_printf("\n");
+  con->dd_printf("                  SZxxxVxC\n");
+
+  con->dd_printf("XPC= 0x%02x IP= 0x%02x IIR= 0x%02x EIR= 0x%02x\n",
+		 mem->get_xpc(), rIP, rIIR, rEIR);
+  
+  con->dd_printf("BC= ");
+  rom->dump(0, rBC, rBC+7, 8, con);
+  con->dd_color("answer");
+  con->dd_printf("DE= ");
+  rom->dump(0, rDE, rDE+7, 8, con);
+  con->dd_color("answer");
+  con->dd_printf("HL= ");
+  rom->dump(0, rHL, rHL+7, 8, con);
+  con->dd_color("answer");
+  con->dd_printf("IX= ");
+  rom->dump(0, rIX, rIX+7, 8, con);
+  con->dd_color("answer");
+  con->dd_printf("IY= ");
+  rom->dump(0, rIY, rIY+7, 8, con);
+  con->dd_color("answer");
+  con->dd_printf("SP= ");
+  rom->dump(0, rSP, rSP+7, 8, con);
+  con->dd_color("answer");
+
+  con->dd_printf("aAF= 0x%02x-0x%02x  ", raA, raF);
+  con->dd_printf("aBC= 0x%02x-0x%02x  ", raB, raC);
+  con->dd_printf("aDE= 0x%02x-0x%02x  ", raD, raE);
+  con->dd_printf("aHL= 0x%02x-0x%02x  ", raH, raL);
+  con->dd_printf("\n");
+
+  print_disass(PC, con);
+}
+
+class cl_cell8 *
+cl_rxk::cR(u8_t z)
+{
+  if (z == 6)
+    return ((cl_cell8*)(rom->get_cell(rHL)));
+  return cRtab[z];
+}
+
+u8_t
+cl_rxk::rR(u8_t z)
+{
+  class cl_cell8 *c= cR(z);
+  u8_t v= c->get();
+  return v;//cR(z).get();
+}
+
+class cl_cell8 *
+cl_rxk::destR(u8_t z)
+{
+  if (z == 6)
+    {
+      return ((cl_cell8*)(rwas->get_cell(rHL)));
+    }
+  if (altd)
+    return caRtab[z];
+  return cRtab[z];
+}
+
+int
+cl_rxk::exec_inst(void)
+{
+  t_mem code;
+  int res= resGO;
+
+  if (!prefix)
+    {
+      rwas= rom;
+      altd= false;
+    }
+  prefix= false;
+  atomic= false;
+  
+  instPC= PC;
+  if (fetch(&code))
+    return resBREAKPOINT;
+  tick(1);
+  if (code == 0xed)
+    {
+      code= fetch();
+      return itab_ed[code](this, code);
+    }
+  if ((code & 0xdd) == 0xdd)
+    {
+      if (code == 0xdd)
+	{
+	  cIR= &cIX;
+	  select_IRR(true);
+	}
+      else
+	{
+	  cIR= &cIY;
+	  select_IRR(false);
+	}
+      {
+      code= fetch();
+      return itab_dd[code](this, code);
+    }
+    }
+  res= itab[code](this, code);
+  if (res == resNOT_DONE)
+    {
+      PC= instPC;
+      code= rom->read(PC);
+      res= inst_unknown(code);
+    }
+  
+  return res;
+}
+
+int
+cl_rxk::inst_unknown(t_mem code)
+{
+  cl_uc::inst_unknown(code);
+  return resINV_INST;
+}
+
+u8_t
+cl_rxk::op8_BC(void)
+{
+  u8_t v= rom->read(rBC);
+  vc.rd++;
+  return v;
+}
+
+u8_t
+cl_rxk::op8_DE(void)
+{
+  u8_t v= rom->read(rDE);
+  vc.rd++;
+  return v;
+}
+
+
+u8_t
+cl_rxk::op8_HL(void)
+{
+  u8_t v= rom->read(rHL);
+  vc.rd++;
+  return v;
+}
+
+u16_t
+cl_rxk::op16_BC(void)
+{
+  u8_t l, h;
+  l= rom->read(rBC);
+  h= rom->read(rBC+1);
+  vc.rd+= 2;
+  return h*256+l;
+}
+
+u16_t
+cl_rxk::op16_DE(void)
+{
+  u8_t l, h;
+  l= rom->read(rDE);
+  h= rom->read(rDE+1);
+  vc.rd+= 2;
+  return h*256+l;
+}
+
+u16_t
+cl_rxk::op16_HL(void)
+{
+  u8_t l, h;
+  l= rom->read(rHL);
+  h= rom->read(rHL+1);
+  vc.rd+= 2;
+  return h*256+l;
+}
+
+
+/*
+ * CPU peripheral: MMU functions
+ */
+
+cl_rxk_cpu::cl_rxk_cpu(class cl_uc *auc):
+  cl_hw(auc, HW_CPU, 0, "cpu")
+{
+  ruc= (class cl_rxk *)auc;
+}
+
+int
+cl_rxk_cpu::init(void)
+{
+  class cl_cvar *v;
+  cl_hw::init();
+  
+  //stackseg= (cl_cell8*)ruc->ioi->get_cell(0x11);
+  //dataseg = (cl_cell8*)ruc->ioi->get_cell(0x12);
+  //segsize = (cl_cell8*)ruc->ioi->get_cell(0x13);
+
+  stackseg= register_cell(ruc->ioi, 0x11);
+  dataseg = register_cell(ruc->ioi, 0x12);
+  segsize = register_cell(ruc->ioi, 0x13);
+  
+  uc->vars->add(v= new cl_cvar("STACKSEG", stackseg,
+			       "MMU register: STACKSEG"));
+  v->init();
+  uc->vars->add(v= new cl_cvar("DATASEG", dataseg,
+			       "MMU register: DATASEG"));
+  v->init();
+  uc->vars->add(v= new cl_cvar("SEGSIZE", segsize,
+			       "MMU register: SEGSIZE"));
+  v->init();
+
+  return 0;
+}
+
+const char *
+cl_rxk_cpu::cfg_help(t_addr addr)
+{
+  switch (addr)
+    {
+      //case rxk_cpu_xpc: return "MMU register: XPC";
+      //case rxk_cpu_nuof: return "";
+    }
+  return "Not used";
+}
+
+void
+cl_rxk_cpu::write(class cl_memory_cell *cell, t_mem *val)
+{
+  if (cell == segsize)
+    {
+      ruc->mem->set_segsize(*val);
+    }
+  else if (cell == dataseg)
+    {
+      ruc->mem->set_dataseg(*val);
+    }
+  else if (cell == stackseg)
+    {
+      ruc->mem->set_stackseg(*val);
+    }
+  
+  else if (cell == ruc->XPC)
+    {
+      (*val)&= 0xfff;
+      ruc->mem->set_lxpc(*val);
+    }
+}
+
+/*
+t_mem
+cl_rxk_cpu::conf_op(cl_memory_cell *cell, t_addr addr, t_mem *val)
+{
+  switch ((enum rxkcpu_cfg)addr)
+    {
+    case rxk_cpu_xpc:
+      if (val) cell->set(ruc->mem->xpc= *val);
+      return ruc->mem->xpc;
+    case rxk_cpu_nuof:
+      return 0;
+    }
+  return 0;
+
+  if (val)
+    cell->set(*val);
+  return cell->get();
+}
+*/
+
+void
+cl_rxk_cpu::print_info(class cl_console_base *con)
+{
+  u8_t ss= ruc->mem->get_segsize();
+  t_addr x, y;
+  x= ss>>4;
+  y= ss&0x0f;
+  con->dd_color("answer");
+  con->dd_printf("%s[%d]\n", id_string, id);
+  con->dd_printf("(L)XPC  : 0x%03x\n", ruc->mem->get_xpc());
+  con->dd_printf("SEGSIZE : 0x%03x\n", segsize->read());
+  con->dd_printf("DATASEG : 0x%03x\n", ruc->mem->get_dataseg());
+  con->dd_printf("STACKSEG: 0x%03x\n", ruc->mem->get_stackseg());
+  //con->dd_printf("XPC     : 0x%02x\n", xpc->read());
+  con->dd_printf("Prefix  : %s\n", ruc->prefix?"true":"false");
+  con->dd_printf("ALTD    : %s\n", ruc->altd?"true":"false");
+  con->dd_printf("Mem op  : %s\n", ruc->rwas->get_name());
+
+  con->dd_printf("Segments: ");
+  con->dd_cprintf("answer", "C=code ");
+  con->dd_cprintf("dump_label", "D=data ");
+  con->dd_cprintf("ui_title", "S=stack ");
+  con->dd_cprintf("error", "X=xmem");
+  con->dd_cprintf("answer", "\n");
+  int l, r;
+  t_addr la, pa;
+  class cl_memory_cell *c;
+  char t;
+  for (l= 0, r= 8; l<8; l++, r++)
+    {
+      la= l*0x1000;
+      if (la >= 0xe000) t= 'X', con->dd_color("error");
+      else if (la >= (x<<12)) t= 'S', con->dd_color("ui_title");
+      else if (la >= (y<<12)) t= 'D', con->dd_color("dump_label");
+      else t= 'C', con->dd_color("answer");
+      c= ruc->mem->get_cell(la);
+      pa= ruc->mem->chip->is_slot(c->get_data());
+      con->dd_printf("0x%xxxx -> 0x%03xxxx %c", l, pa>>12, t);
+      con->dd_printf("   ");
+      la= r*0x1000;
+      if (la >= 0xe000) t= 'X', con->dd_color("error");
+      else if (la >= (x<<12)) t= 'S', con->dd_color("ui_title");
+      else if (la >= (y<<12)) t= 'D', con->dd_color("dump_label");
+      else t= 'C', con->dd_color("answer");
+      c= ruc->mem->get_cell(la);
+      pa= ruc->mem->chip->is_slot(c->get_data());
+      con->dd_printf("0x%xxxx -> 0x%03xxxx %c", r, pa>>12, t);
+      con->dd_color("answer");
+      con->dd_printf("\n");
+    }
+  
+}
+
+
+/* End of rxk.src/rxk.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/rxkcl.h sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/rxkcl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/rxkcl.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/rxkcl.h	2021-10-29 17:39:15.000000000 +0000
@@ -0,0 +1,727 @@
+/*
+ * Simulator of microcontrollers (rxkcl.h)
+ *
+ * Copyright (C) 2020,2021 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef RXKCL_HEADER
+#define RXKCL_HEADER
+
+#include "uccl.h"
+#include "rmemcl.h"
+#include "decode.h"
+#include "dp0m3.h"
+#include "dpedm3.h"
+#include "dpddm3.h"
+
+
+/*
+ * Base of RXK processor
+ */
+
+
+#define rA (AF.r.A)
+#define rF (AF.r.F)
+#define rAF (AF.AF)
+#define rXPC (mem->get_xpc())
+#define cXPC (*XPC)
+
+#define rBCDE (BCDE.BCDE)
+#define rBC   (BCDE.r32.r16h.BC)
+#define rDE   (BCDE.r32.r16l.DE)
+#define rB    (BCDE.r32.r16h.r.B)
+#define rC    (BCDE.r32.r16h.r.C)
+#define rD    (BCDE.r32.r16l.r.D)
+#define rE    (BCDE.r32.r16l.r.E)
+
+#define rJKHL (JKHL.JKHL)
+#define rJK   (JKHL.r32.r16h.JK)
+#define rHL   (JKHL.r32.r16l.HL)
+#define rJ    (JKHL.r32.r16h.r.J)
+#define rK    (JKHL.r32.r16h.r.K)
+#define rH    (JKHL.r32.r16l.r.H)
+#define rL    (JKHL.r32.r16l.r.L)
+
+#define raA (aAF.r.A)
+#define raF (aAF.r.F)
+#define raAF (aAF.AF)
+
+#define raBCDE (aBCDE.BCDE)
+#define raBC   (aBCDE.r32.r16h.BC)
+#define raDE   (aBCDE.r32.r16l.DE)
+#define raB    (aBCDE.r32.r16h.r.B)
+#define raC    (aBCDE.r32.r16h.r.C)
+#define raD    (aBCDE.r32.r16l.r.D)
+#define raE    (aBCDE.r32.r16l.r.E)
+
+#define raJKHL (aJKHL.JKHL)
+#define raJK   (aJKHL.r32.r16h.JK)
+#define raHL   (aJKHL.r32.r16l.HL)
+#define raJ    (aJKHL.r32.r16h.r.J)
+#define raK    (aJKHL.r32.r16h.r.K)
+#define raH    (aJKHL.r32.r16l.r.H)
+#define raL    (aJKHL.r32.r16l.r.L)
+
+enum {
+  flagS = 0x80,
+  flagZ = 0x40,
+  flagL = 0x04,
+  flagV = 0x04,
+  flagC = 0x01,
+  flagAll = flagS|flagZ|flagL|flagC,
+  flagsAll= flagS|flagZ|flagL|flagC,
+  allFlag = flagS|flagZ|flagL|flagC,
+  allFlags= flagS|flagZ|flagL|flagC
+};
+
+#define cond_GT(f)	( !(( ((f) ^ ((f)<<5)) | ((f)<<1)) & 0x80) )
+#define cond_GTU(f)	( !((f)&flagC) && !((f)&flagZ) )
+#define cond_LT(f)	( ((f) ^ ((f)<<5)) & 0x80 )
+#define cond_LTU(f)	( (f)&flagC )
+#define cond_V(f)	( (f)&flagV )
+
+#define CPU ((class cl_rxk_cpu *)cpu)
+
+
+class cl_rxk_base: public cl_uc
+{
+public:
+  cl_rxk_base(class cl_sim *asim);
+#include "r4kcl_instructions.h"
+#include "dd_instructions.h"
+#include "ed_instructions.h"
+};
+  
+class cl_rxk: public cl_rxk_base
+{
+public:
+  RP(AF,AF,A,F);
+  RP(aAF,AF,A,F);
+  RP(aBC,BC,B,C);
+  RP(aDE,DE,D,E);
+  RP(aHL,HL,H,L);
+  R32(BCDE,BCDE,BC,DE,B,C,D,E);
+  R32(JKHL,JKHL,JK,HL,J,K,H,L);
+  R32(aBCDE,BCDE,BC,DE,B,C,D,E);
+  R32(aJKHL,JKHL,JK,HL,J,K,H,L);
+  class cl_cell32 cBCDE, caBCDE;
+  u8_t rIP, rIIR, rEIR;
+  u16_t rIX, rIY, rSP;
+  class cl_cell8 cIP, cIIR, cEIR;
+  class cl_cell8 cA, cF, cB, cC, cD, cE, cH, cL;
+  class cl_cell8 caA, caF, caB, caC, caD, caE, caH, caL;
+  class cl_cell8 *cRtab[8], *caRtab[8];
+  class cl_cell16 cAF, cBC, cDE, cHL, cIX, cIY, cSP;
+  class cl_cell16 caAF, caBC, caDE, caHL;
+  class cl_cell16 *cIR;
+  class cl_memory_cell *XPC;
+  class cl_ras *mem;
+  class cl_address_space *ioi, *ioe;
+  class cl_address_space *rwas;
+  bool prefix, altd, atomic;
+public:
+  cl_rxk(class cl_sim *asim);
+  virtual int init(void);
+  virtual const char *id_string(void);
+  virtual void reset(void);
+  virtual void set_PC(t_addr addr);
+
+  virtual void mk_hw_elements(void);
+  virtual void make_cpu_hw(void);
+  virtual void make_memories(void);
+  virtual t_addr chip_size() { return 0x100000; }
+  
+  virtual int clock_per_cycle(void) { return 1; }
+  //virtual struct dis_entry *dis_tbl(void);
+  virtual struct dis_entry *dis_entry(t_addr addr);
+  virtual char *disassc(t_addr addr, chars *comment= NULL);
+  virtual char *disassc_cb(t_addr addr, chars *comment= NULL);
+  virtual char *disassc_dd_cb(t_addr addr, chars *comment= NULL);
+  virtual int inst_length(t_addr addr);
+  virtual int longest_inst(void) { return 4; }
+  virtual void disass_irr(chars *work, bool dd) {}
+  virtual void disass_irrl(chars *work, bool dd) {}
+  
+  virtual void save_hist();
+  virtual void print_regs(class cl_console_base *con);
+
+  virtual class cl_cell8 *cR(u8_t z);
+  virtual class cl_cell8 *destR(u8_t z);
+  virtual u8_t rR(u8_t z);
+  virtual int exec_inst(void);
+  virtual int inst_unknown(t_mem code);
+  virtual void tick5p1(int n) { tick(n); }
+  virtual void tick5p2(int n) { tick(n); }
+  virtual void tick5p3(int n) { tick(n); }
+  virtual void tick5p9(int n) { tick(n); }
+  virtual void tick5p12(int n) { tick(n); }
+  virtual void tick5m1(int n) { tick(n+2); }
+  virtual void tick5m2(int n) { tick(n+2); }
+  virtual void select_IRR(bool dd) {}
+  
+  class cl_cell16 &destAF(void) { return altd?caAF:cAF; }
+  class cl_cell16 &destBC(void) { return altd?caBC:cBC; }
+  class cl_cell16 &destDE(void) { return altd?caDE:cDE; }
+  class cl_cell16 &destHL(void) { return altd?caHL:cHL; }
+  class cl_cell8  &destA(void)  { return altd?caA:cA; }
+  class cl_cell8  &destF(void)  { return altd?caF:cF; }
+  class cl_cell8  &destB(void)  { return altd?caB:cB; }
+  class cl_cell8  &destC(void)  { return altd?caC:cC; }
+  class cl_cell8  &destD(void)  { return altd?caD:cD; }
+  class cl_cell8  &destE(void)  { return altd?caE:cE; }
+  class cl_cell8  &destH(void)  { return altd?caH:cH; }
+  class cl_cell8  &destL(void)  { return altd?caL:cL; }
+  class cl_cell8  &dest8iBC(void) { return *((cl_cell8*)rwas->get_cell(rBC)); }
+  class cl_cell8  &dest8iDE(void) { return *((cl_cell8*)rwas->get_cell(rDE)); }
+  class cl_cell8  &dest8iHL(void) { return *((cl_cell8*)rwas->get_cell(rHL)); }
+  class cl_cell8  &dest8imn(void) { u8_t l, h;
+    l= fetch(); h= fetch();
+    return *((cl_cell8*)rwas->get_cell(h*256+l));
+  }
+  class cl_cell8 &dest8iIRd(i8_t d) { return *((cl_cell8*)rwas->get_cell(cIR->get()+d)); }
+  
+  u8_t op8_BC(void);
+  u8_t op8_DE(void);
+  u8_t op8_HL(void);
+  u16_t op16_BC(void);
+  u16_t op16_DE(void);
+  u16_t op16_HL(void);
+  void write8(u16_t a, u8_t v) { vc.wr++; rom->write(a, v); }
+  void write8io(u16_t a, u8_t v) { vc.wr++; rwas->write(a, v); }
+  void write16(u16_t a, u16_t v) { vc.wr+=2;
+    rom->write(a, v); rom->write(a+1, v>>8);
+  }
+  void write16io(u16_t a, u16_t v) { vc.wr+=2;
+    rwas->write(a, v); rwas->write(a+1, v>>8);
+  }
+  u8_t read8(u16_t a) { vc.rd++; return rom->read(a); }
+  u8_t read8io(u16_t a) { vc.rd++; return rwas->read(a); }
+  u16_t read16(u16_t a) { u8_t l, h; vc.rd+=2;
+    l= rom->read(a); h= rom->read(a+1);
+    return h*256+l;
+  }
+  u16_t read16io(u16_t a) { u8_t l, h; vc.rd+=2;
+    l= rwas->read(a); h= rwas->read(a+1);
+    return h*256+l;
+  }
+  u32_t read32(u16_t a) { u16_t l, h; vc.rd+=4;
+    l= read16(a); h= read16(a+2);
+    return (h<<16)+l;
+  }
+  u32_t read32io(u16_t a) { u16_t l, h; vc.rd+=4;
+    l= read16io(a); h= read16io(a+2);
+    return (h<<16)+l;
+  }
+  u16_t fetch16(void) { u8_t l, h;
+    l= fetch(); h= fetch();
+    return h*256 + l;
+  }
+
+  virtual int ipset(u8_t n);					// 0f,4t,0r,0w
+  
+  virtual int ld_dd_mn(class cl_cell16 &dd);			// 2f,6t,0r,0w
+  virtual int ld_r_n(class cl_cell8 &r);			// 1f,4t,0r,0w
+  virtual int ld_ihl_r(u8_t op);				// 0f,6t,0r,1w
+  virtual int ld_r_ihl(class cl_cell8 &destr);			// 0f,5t,1r,0w
+  virtual int ld_r_g(class cl_cell8 &dest, u8_t op);		// 0f,2t,0r,0w
+  virtual int pop_zz(class cl_cell16 &dest);			// 0f,6t,2r,0w
+  virtual int push_zz(u16_t op);				// 0f,9t,0r,2w
+  virtual int ld_d_i(int dif);					// 0f,10t,1r,1w
+  virtual int LDxR(int dif);					// 0f,6t,1r,1w
+  virtual int ld_iIRd_r(u8_t op);				// 1f,10t,0r,1w
+  virtual int ld_r_iIRd(class cl_cell8 &op);			// 1f,9t,1r,0w
+  virtual int ld_hl_op(u16_t op);				// 0f,2t,0r,0w
+  virtual int ld_dd_imn(class cl_cell16 &dest);			// 2f,13t,2r,0w
+  virtual int ld_add_BC_DE(class cl_cell16 &dest, u16_t src);	// 0f,4t,0r,0w
+  virtual int ld_imn_ss(u16_t src);				// 2f,15t,0r,2w
+  virtual int ldp_irp_rp(u16_t addr, u16_t src);		// 0f,12t,0r,2w
+  virtual int ldp_rp_irp(class cl_cell16 &dest, u16_t addr);	// 0f,10t,2r,0w
+  
+  virtual int inc_ss(class cl_cell16 &rp, u16_t op);
+  virtual int inc_r(class cl_cell8 &cr, u8_t op);
+  virtual int dec_ss(class cl_cell16 &rp, u16_t op);
+  virtual int dec_r(class cl_cell8 &cr, u8_t op);
+  virtual int rot8left(class cl_cell8 &dest, u8_t op);		// 0f,1t,0r,0w
+  virtual int rlc(class cl_cell8 &dest, u8_t op);		// 0f,4t,0r,0w
+  virtual int rot16left(class cl_cell16 &dest, u16_t op);	// 0f,1t,0r,0w
+  virtual int rot32left(class cl_cell32 &dest, u32_t op, int nr);//0f,4t,0r,0w
+  virtual int rot9left(class cl_cell8 &dest, u8_t op);		// 0f,1t,0r,0w
+  virtual int rl(class cl_cell8 &dest, u8_t op);		// 0f,4t,0r,0w
+  virtual int rot17left(class cl_cell16 &dest, u16_t op);	// 0f,1t,0r,0w
+  virtual int rot33left(class cl_cell32 &dest, u32_t op, int nr);//0f,4t,0r,0w
+  virtual int rot8right(class cl_cell8 &dest, u8_t op);		// 0f,1t,0r,0w
+  virtual int rot16right(class cl_cell16 &dest, u16_t op);	// 0f,1t,0r,0w
+  virtual int rot32right(class cl_cell32 &dest, u32_t op,int nr);//0f,4t,0r,0w
+  virtual int rrc(class cl_cell8 &dest, u8_t op);		// 0f,4t,0r,0w
+  virtual int rot9right(class cl_cell8 &dest, u8_t op);		// 0f,1t,0r,0w
+  virtual int rr(class cl_cell8 &dest, u8_t op);		// 0f,4t,0r,0w
+  virtual int rot17right(class cl_cell16 &dest, u16_t op);	// 0f,1t,0r,0w
+  virtual int rot33right(class cl_cell32 &dest, u32_t op,int nr);//0f,4t,0r,0w
+  virtual int sla8(class cl_cell8 &dest, u8_t op);		// 0f,4t,0r,0w
+  virtual int sla32(class cl_cell32 &dest, u32_t op, int nr);	// 0f,4t,0r,0w
+  virtual int sra8(class cl_cell8 &dest, i8_t op);		// 0f,4t,0r,0w
+  virtual int sra32(class cl_cell32 &dest, i32_t op, int nr);	// 0f,4t,0r,0w
+  virtual int srl8(class cl_cell8 &dest, u8_t op);		// 0f,4t,0r,0w
+  virtual int srl32(class cl_cell32 &dest, u32_t op, int nr);	// 0f,4t,0r,0w
+  virtual int bit_r(u8_t b, u8_t op);				// 0f,4t,0r,0w
+  virtual int bit_iHL(u8_t b);					// 0f,7t,1r,0w
+  virtual int bit_iIRd(u8_t b, i8_t d);				// 0f,10t,1r,0w
+  virtual int res_r(u8_t b, class cl_cell8 &dest, u8_t op);	// 0f,4t,0r,0w
+  virtual int res_iHL(u8_t b);					// 0f,10t,1r,1w
+  virtual int res_iIRd(u8_t b, i8_t d);				// 0f,13t,1r,1w
+  virtual int set_r(u8_t b, class cl_cell8 &dest, u8_t op);	// 0f,4t,0r,0w
+  virtual int set_iHL(u8_t b);					// 0f,10t,1r,1w
+  virtual int set_iIRd(u8_t b, i8_t d);				// 0f,12t,1r,1w
+  
+  virtual int add_hl_ss(u16_t op);
+  virtual int adc_hl_ss(u16_t op);
+  virtual int add8(u8_t op2, bool cy);				// 0f,4t,0r,0w
+  virtual int sub8(u8_t op2, bool cy);				// 0f,4t,0r,0w
+  virtual int sub16(u16_t op2, bool cy);			// 0f,4t,0r,0w
+  virtual int sub32(u32_t op1, u32_t op2, class cl_cell32 &cRes, bool cy);
+  
+  virtual int inc_i8(t_addr addr);
+  virtual int dec_i8(t_addr addr);
+  virtual int add_ir_xy(u16_t op);				// 0f,4t,0r,0r
+  virtual int xor8(class cl_cell8 &dest, u8_t op1, u8_t op2);	// 0f,1t,0r,0w
+  virtual int xor16(class cl_cell16 &dest, u16_t op1,u16_t op2);// 0f,4t,0r,0w
+  virtual int or8(class cl_cell8 &dest, u8_t op1, u8_t op2);	// 0f,1t,0r,0w
+  virtual int or16(class cl_cell16 &dest,
+		    u16_t op1, u16_t op2);			// 0f,1t,0r,0w
+  virtual int and8(class cl_cell8 &dest, u8_t op1, u8_t op2);	// 0f,1t,0r,0w
+  virtual int and16(class cl_cell16 &dest,
+		    u16_t op1, u16_t op2);			// 0f,1t,0r,0w
+  virtual int cp8(u8_t op1, u8_t op2);				// 0f,3t,0r,0w
+  virtual int cp16(u16_t op1, u16_t op2);			// 0f,4t,0r,0w
+  virtual int cp32(u32_t op1, u32_t op2);			// 0f,4t,0r,0w
+  
+  virtual int jr_cc(bool cond);
+  virtual int ret_f(bool f);					// 0f,7t,2r,0w
+  virtual int jp_f_mn(bool f);					// 2f,6t,2r,0w
+  virtual int rst_v(t_mem code);				// 0f,7t,0r,2w
+  
+  virtual int ALTD(t_mem code);
+  virtual int IOI(t_mem code);
+  virtual int IOE(t_mem code);
+
+  virtual int NOP(t_mem code);
+  virtual int LD_BC_mn(t_mem code) { return ld_dd_mn(destBC()); }
+  virtual int LD_DE_mn(t_mem code) { return ld_dd_mn(destDE()); }
+  virtual int LD_HL_mn(t_mem code) { return ld_dd_mn(destHL()); }
+  virtual int LD_SP_mn(t_mem code) { return ld_dd_mn(cSP     ); }
+  virtual int LD_imn_HL(t_mem code);
+  virtual int LD_HL_imn(t_mem code);
+  virtual int INC_BC(t_mem code) { return inc_ss(destBC(), rBC); }
+  virtual int INC_DE(t_mem code) { return inc_ss(destDE(), rDE); }
+  virtual int INC_HL(t_mem code) { return inc_ss(destHL(), rHL); }
+  virtual int INC_SP(t_mem code) { return inc_ss(cSP     , rSP); }
+  virtual int INC_A(t_mem code) { return inc_r(destA(), rA); }
+  virtual int INC_B(t_mem code) { return inc_r(destB(), rB); }
+  virtual int INC_C(t_mem code) { return inc_r(destC(), rC); }
+  virtual int INC_D(t_mem code) { return inc_r(destD(), rD); }
+  virtual int INC_E(t_mem code) { return inc_r(destE(), rE); }
+  virtual int INC_H(t_mem code) { return inc_r(destH(), rH); }
+  virtual int INC_L(t_mem code) { return inc_r(destL(), rL); }
+  virtual int DEC_BC(t_mem code) { return dec_ss(destBC(), rBC); }
+  virtual int DEC_DE(t_mem code) { return dec_ss(destDE(), rDE); }
+  virtual int DEC_HL(t_mem code) { return dec_ss(destHL(), rHL); }
+  virtual int DEC_SP(t_mem code) { return dec_ss(cSP     , rSP); }
+  virtual int DEC_A(t_mem code) { return dec_r(destA(), rA); }
+  virtual int DEC_B(t_mem code) { return dec_r(destB(), rB); }
+  virtual int DEC_C(t_mem code) { return dec_r(destC(), rC); }
+  virtual int DEC_D(t_mem code) { return dec_r(destD(), rD); }
+  virtual int DEC_E(t_mem code) { return dec_r(destE(), rE); }
+  virtual int DEC_H(t_mem code) { return dec_r(destH(), rH); }
+  virtual int DEC_L(t_mem code) { return dec_r(destL(), rL); }
+  virtual int LD_A_n(t_mem code) { return ld_r_n(destA()); }
+  virtual int LD_B_n(t_mem code) { return ld_r_n(destB()); }
+  virtual int LD_C_n(t_mem code) { return ld_r_n(destC()); }
+  virtual int LD_D_n(t_mem code) { return ld_r_n(destD()); }
+  virtual int LD_E_n(t_mem code) { return ld_r_n(destE()); }
+  virtual int LD_H_n(t_mem code) { return ld_r_n(destH()); }
+  virtual int LD_L_n(t_mem code) { return ld_r_n(destL()); }
+  virtual int RLCA(t_mem code) { return rot8left(destA(), rA); }
+  virtual int RLA(t_mem code) { return rot9left(destA(), rA); }
+  virtual int RRCA(t_mem code) { return rot8right(destA(), rA); }
+  virtual int RRA(t_mem code) { return rot9right(destA(), rA); }
+  virtual int LD_iBC_A(t_mem code);
+  virtual int LD_iDE_A(t_mem code);
+  virtual int LD_iHL_A(t_mem code) { return ld_ihl_r(rA); }
+  virtual int LD_iHL_B(t_mem code) { return ld_ihl_r(rB); }
+  virtual int LD_iHL_C(t_mem code) { return ld_ihl_r(rC); }
+  virtual int LD_iHL_D(t_mem code) { return ld_ihl_r(rD); }
+  virtual int LD_iHL_E(t_mem code) { return ld_ihl_r(rE); }
+  virtual int LD_iHL_H(t_mem code) { return ld_ihl_r(rH); }
+  virtual int LD_iHL_L(t_mem code) { return ld_ihl_r(rL); }
+  virtual int LD_iMN_A(t_mem code);
+  virtual int LD_A_iBC(t_mem code);
+  virtual int LD_A_iDE(t_mem code);
+  virtual int LD_A_iMN(t_mem code);
+  virtual int LD_A_iHL(t_mem code) { return ld_r_ihl(destA()); }
+  virtual int LD_B_iHL(t_mem code) { return ld_r_ihl(destB()); }
+  virtual int LD_C_iHL(t_mem code) { return ld_r_ihl(destC()); }
+  virtual int LD_D_iHL(t_mem code) { return ld_r_ihl(destD()); }
+  virtual int LD_E_iHL(t_mem code) { return ld_r_ihl(destE()); }
+  virtual int LD_H_iHL(t_mem code) { return ld_r_ihl(destH()); }
+  virtual int LD_L_iHL(t_mem code) { return ld_r_ihl(destL()); }
+  virtual int SCF(t_mem code);
+  virtual int CPL(t_mem code);
+  virtual int CCF(t_mem code);
+  virtual int EX_AF_aAF(t_mem code);
+  virtual int ADD_HL_BC(t_mem code) { return add_hl_ss(rBC); }
+  virtual int ADD_HL_DE(t_mem code) { return add_hl_ss(rDE); }
+  virtual int ADD_HL_HL(t_mem code) { return add_hl_ss(rHL); }
+  virtual int ADD_HL_SP(t_mem code) { return add_hl_ss(rSP); }
+  virtual int DJNZ(t_mem code);
+  virtual int JR(t_mem code);
+  virtual int JR_NZ(t_mem code) { return jr_cc(!(rF&flagZ)); }
+  virtual int JR_Z (t_mem code) { return jr_cc( (rF&flagZ)); }
+  virtual int JR_NC(t_mem code) { return jr_cc(!(rF&flagC)); }
+  virtual int JR_C (t_mem code) { return jr_cc( (rF&flagC)); }
+  virtual int ADD_SP_d(t_mem code);
+  virtual int INC_iHL(t_mem code) { return inc_i8(rHL); }
+  virtual int DEC_iHL(t_mem code) { return dec_i8(rHL); }
+  virtual int LD_iHL_n(t_mem code) { tick(6);write8io(rHL, fetch());return resGO; }
+  virtual int LD_B_A(t_mem code) { return ld_r_g(destB(), rA); }
+  virtual int LD_C_A(t_mem code) { return ld_r_g(destC(), rA); }
+  virtual int LD_D_A(t_mem code) { return ld_r_g(destD(), rA); }
+  virtual int LD_E_E(t_mem code) { return ld_r_g(destE(), rE); }
+  virtual int LD_E_A(t_mem code) { return ld_r_g(destE(), rA); }
+  virtual int LD_L_A(t_mem code) { return ld_r_g(destL(), rA); }
+  virtual int LD_H_A(t_mem code) { return ld_r_g(destH(), rA); }
+  virtual int LD_A_B(t_mem code) { return ld_r_g(destA(), rB); }
+  virtual int LD_A_C(t_mem code) { return ld_r_g(destA(), rC); }
+  virtual int LD_A_D(t_mem code) { return ld_r_g(destA(), rD); }
+  virtual int LD_A_E(t_mem code) { return ld_r_g(destA(), rE); }
+  virtual int LD_A_H(t_mem code) { return ld_r_g(destA(), rH); }
+  virtual int LD_A_L(t_mem code) { return ld_r_g(destA(), rL); }
+  virtual int XOR_A(t_mem code) { return xor8(destA(), rA, rA); }
+  virtual int OR_A(t_mem code) { return or8(destA(), rA, rA); }
+  virtual int RET_NZ(t_mem code) { return ret_f(!(rF&flagZ)); }
+  virtual int RET_Z (t_mem code) { return ret_f( (rF&flagZ)); }
+  virtual int RET   (t_mem code) { return ret_f( (true    )); }
+  virtual int RET_NC(t_mem code) { return ret_f(!(rF&flagC)); }
+  virtual int RET_C (t_mem code) { return ret_f( (rF&flagC)); }
+  virtual int RET_LZ(t_mem code) { return ret_f(!(rF&flagV)); } // NV
+  virtual int RET_LO(t_mem code) { return ret_f( (rF&flagV)); } // V
+  virtual int RET_P (t_mem code) { return ret_f(!(rF&flagS)); }
+  virtual int RET_M (t_mem code) { return ret_f( (rF&flagS)); }
+  virtual int POP_AF(t_mem code) { return pop_zz(destAF()); }
+  virtual int POP_BC(t_mem code) { return pop_zz(destBC()); }
+  virtual int POP_DE(t_mem code) { return pop_zz(destDE()); }
+  virtual int POP_HL(t_mem code) { return pop_zz(destHL()); }
+  virtual int JP_NZ_mn(t_mem code) { return jp_f_mn(!(rF&flagZ)); }
+  virtual int JP_Z_mn (t_mem code) { return jp_f_mn( (rF&flagZ)); }
+  virtual int JP_NC_mn(t_mem code) { return jp_f_mn(!(rF&flagC)); }
+  virtual int JP_C_mn (t_mem code) { return jp_f_mn( (rF&flagC)); }
+  virtual int JP_LZ_mn(t_mem code) { return jp_f_mn(!(rF&flagV)); }
+  virtual int JP_LO_mn(t_mem code) { return jp_f_mn( (rF&flagV)); }
+  virtual int JP_P_mn (t_mem code) { return jp_f_mn(!(rF&flagS)); }
+  virtual int JP_M_mn (t_mem code) { return jp_f_mn( (rF&flagS)); }
+  virtual int JP_mn   (t_mem code) { return jp_f_mn( (true    )); }
+  virtual int LD_HL_iSPn(t_mem code);
+  virtual int PUSH_AF(t_mem code) { return push_zz(rAF); }
+  virtual int PUSH_BC(t_mem code) { return push_zz(rBC); }
+  virtual int PUSH_DE(t_mem code) { return push_zz(rDE); }
+  virtual int PUSH_HL(t_mem code) { return push_zz(rHL); }
+  virtual int ADD_A_n(t_mem code) { return add8(fetch(), false); }
+  virtual int LJP(t_mem code);
+  virtual int BOOL_HL(t_mem code);
+  virtual int CALL_mn(t_mem code);
+  virtual int ADC_A_n(t_mem code) { return add8(fetch(), true); }
+  virtual int LCALL_lmn(t_mem code);
+  virtual int LD_iSPn_HL(t_mem code);
+  virtual int SUB_A_n(t_mem code) { return sub8(fetch(), false); }
+  virtual int RST_10(t_mem code) { return rst_v(code); }
+  virtual int RST_18(t_mem code) { return rst_v(code); }
+  virtual int RST_20(t_mem code) { return rst_v(code); }
+  virtual int RST_28(t_mem code) { return rst_v(code); }
+  virtual int RST_38(t_mem code) { return rst_v(code); }
+  virtual int EXX(t_mem code);
+  virtual int AND_HL_DE(t_mem code) { return and16(destHL(), rHL, rDE); }
+  virtual int OR_HL_DE (t_mem code) { return or16 (destHL(), rHL, rDE); }
+  virtual int SBC_A_n(t_mem code) { return sub8(fetch(), true); }
+  virtual int EX_aDE_HL(t_mem code);
+  virtual int EX_DE_HL(t_mem code);
+  virtual int LD_HL_iIXd(t_mem code);
+  virtual int LD_iIXd_HL(t_mem code);
+  virtual int AND_n(t_mem code) { tick(2); return and8(destA(), rA, fetch()); }
+  virtual int JP_HL(t_mem code) { tick(3); PC= rHL; return resGO; }
+  virtual int XOR_n(t_mem code) { tick(3); return xor8(destA(), rA, fetch()); }
+  virtual int RL_DE(t_mem code) { return rot17left(destDE(), rDE); }
+  virtual int OR_n(t_mem code) { tick(3); return or8(destA(), rA, fetch()); }
+  virtual int MUL(t_mem code);
+  virtual int LD_SP_HL(t_mem code) { tick(1); cSP.W(rHL); return resGO; }
+  virtual int RR_DE(t_mem code) { return rot17right(destDE(), rDE); }
+  virtual int RR_HL(t_mem code) { return rot17right(destHL(), rHL); }
+  virtual int CP_n(t_mem code) { return cp8(rA, fetch()); }
+
+  // Page0, mode 3k only, invalid in 4k mode
+  virtual int LD_B_B(t_mem code) { return ld_r_g(destB(), rB); }
+  virtual int LD_B_C(t_mem code) { return ld_r_g(destB(), rC); }
+  virtual int LD_B_E(t_mem code) { return ld_r_g(destB(), rE); }
+  virtual int LD_B_H(t_mem code) { return ld_r_g(destB(), rH); }
+  virtual int LD_C_C(t_mem code) { return ld_r_g(destC(), rC); }
+  virtual int LD_C_D(t_mem code) { return ld_r_g(destC(), rD); }
+  virtual int LD_C_E(t_mem code) { return ld_r_g(destC(), rE); }
+
+  virtual int LD_D_D(t_mem code) { return ld_r_g(destD(), rD); }
+  virtual int LD_D_E(t_mem code) { return ld_r_g(destD(), rE); }
+  virtual int LD_E_B(t_mem code) { return ld_r_g(destE(), rB); }
+  virtual int LD_E_C(t_mem code) { return ld_r_g(destE(), rC); }
+  virtual int LD_E_D(t_mem code) { return ld_r_g(destE(), rD); }
+  virtual int LD_E_H(t_mem code) { return ld_r_g(destE(), rH); }
+  virtual int LD_E_L(t_mem code) { return ld_r_g(destE(), rL); }
+
+  virtual int LD_H_H(t_mem code) { return ld_r_g(destH(), rH); }
+  virtual int LD_L_B(t_mem code) { return ld_r_g(destL(), rB); }
+  virtual int LD_L_C(t_mem code) { return ld_r_g(destL(), rC); }
+  virtual int LD_L_D(t_mem code) { return ld_r_g(destL(), rD); }
+  virtual int LD_L_E(t_mem code) { return ld_r_g(destL(), rE); }
+  virtual int LD_L_H(t_mem code) { return ld_r_g(destL(), rH); }
+
+  virtual int ADD_A_B(t_mem code) { return add8(rB, false); }
+  virtual int ADC_A_B(t_mem code) { return add8(rB, true ); }
+
+  virtual int SUB_A_B(t_mem code) { return sub8(rB, false); }
+
+  virtual int LD_B_D(t_mem code) { return ld_r_g(destB(), rD); }
+  virtual int LD_B_L(t_mem code) { return ld_r_g(destB(), rL); }
+  virtual int LD_C_B(t_mem code) { return ld_r_g(destC(), rB); }
+  virtual int LD_C_H(t_mem code) { return ld_r_g(destC(), rH); }
+  virtual int LD_C_L(t_mem code) { return ld_r_g(destC(), rL); }
+
+  virtual int LD_D_B(t_mem code) { return ld_r_g(destD(), rB); }
+  virtual int LD_D_C(t_mem code) { return ld_r_g(destD(), rC); }
+  virtual int LD_D_H(t_mem code) { return ld_r_g(destD(), rH); }
+  virtual int LD_D_L(t_mem code) { return ld_r_g(destD(), rL); }
+
+  virtual int LD_H_B(t_mem code) { return ld_r_g(destH(), rB); }
+  virtual int LD_H_C(t_mem code) { return ld_r_g(destH(), rC); }
+  virtual int LD_H_D(t_mem code) { return ld_r_g(destH(), rD); }
+  virtual int LD_H_E(t_mem code) { return ld_r_g(destH(), rE); }
+  virtual int LD_H_L(t_mem code) { return ld_r_g(destH(), rL); }
+  virtual int LD_L_L(t_mem code) { return ld_r_g(destL(), rL); }
+
+  virtual int LD_A_A(t_mem code) { return ld_r_g(destA(), rA); }
+
+  virtual int ADD_A_C(t_mem code) { return add8(rC, false); }
+  virtual int ADD_A_D(t_mem code) { return add8(rD, false); }
+  virtual int ADD_A_E(t_mem code) { return add8(rE, false); }
+  virtual int ADD_A_H(t_mem code) { return add8(rH, false); }
+  virtual int ADD_A_L(t_mem code) { return add8(rL, false); }
+  virtual int ADD_A_iHL(t_mem code) { tick(3); return add8(read8io(rHL), false); }
+  virtual int ADD_A_A(t_mem code) { return add8(rA, false); }
+  virtual int ADC_A_C(t_mem code) { return add8(rC, true); }
+  virtual int ADC_A_D(t_mem code) { return add8(rD, true); }
+  virtual int ADC_A_E(t_mem code) { return add8(rE, true); }
+  virtual int ADC_A_H(t_mem code) { return add8(rH, true); }
+  virtual int ADC_A_L(t_mem code) { return add8(rL, true); }
+  virtual int ADC_A_iHL(t_mem code) { tick(3); return add8(read8io(rHL), true); }
+  virtual int ADC_A_A(t_mem code) { return add8(rA, true); }
+
+  virtual int SUB_A_C(t_mem code) { return sub8(rC, false); }
+  virtual int SUB_A_D(t_mem code) { return sub8(rD, false); }
+  virtual int SUB_A_E(t_mem code) { return sub8(rE, false); }
+  virtual int SUB_A_H(t_mem code) { return sub8(rH, false); }
+  virtual int SUB_A_L(t_mem code) { return sub8(rL, false); }
+  virtual int SUB_A_iHL(t_mem code) { tick(3); return sub8(read8io(rHL), false); }
+  virtual int SUB_A_A(t_mem code) { return sub8(rA, false); }
+  virtual int SBC_A_B(t_mem code) { return sub8(rB, true); }
+  virtual int SBC_A_C(t_mem code) { return sub8(rC, true); }
+  virtual int SBC_A_D(t_mem code) { return sub8(rD, true); }
+  virtual int SBC_A_E(t_mem code) { return sub8(rE, true); }
+  virtual int SBC_A_H(t_mem code) { return sub8(rH, true); }
+  virtual int SBC_A_L(t_mem code) { return sub8(rL, true); }
+  virtual int SBC_A_iHL(t_mem code) { tick(3); return sub8(read8io(rHL), true); }
+  virtual int SBC_A_A(t_mem code) { return sub8(rA, true); }
+
+  virtual int AND_A_B(t_mem code) { return and8(destA(), rA, rB); }
+  virtual int AND_A_C(t_mem code) { return and8(destA(), rA, rC); }
+  virtual int AND_A_D(t_mem code) { return and8(destA(), rA, rD); }
+  virtual int AND_A_E(t_mem code) { return and8(destA(), rA, rE); }
+  virtual int AND_A_H(t_mem code) { return and8(destA(), rA, rH); }
+  virtual int AND_A_L(t_mem code) { return and8(destA(), rA, rL); }
+  virtual int AND_A_iHL(t_mem code) { tick(3); return and8(destA(), rA, read8io(rHL)); }
+  virtual int AND_A_A(t_mem code) { return and8(destA(), rA, rA); }
+  virtual int XOR_A_B(t_mem code) { return xor8(destA(), rA, rB); }
+  virtual int XOR_A_C(t_mem code) { return xor8(destA(), rA, rC); }
+  virtual int XOR_A_D(t_mem code) { return xor8(destA(), rA, rD); }
+  virtual int XOR_A_E(t_mem code) { return xor8(destA(), rA, rE); }
+  virtual int XOR_A_H(t_mem code) { return xor8(destA(), rA, rH); }
+  virtual int XOR_A_L(t_mem code) { return xor8(destA(), rA, rL); }
+  virtual int XOR_A_iHL(t_mem code) { tick(3); return xor8(destA(), rA, read8io(rHL)); }
+
+  virtual int OR_A_B(t_mem code) { return or8(destA(), rA, rB); }
+  virtual int OR_A_C(t_mem code) { return or8(destA(), rA, rC); }
+  virtual int OR_A_D(t_mem code) { return or8(destA(), rA, rD); }
+  virtual int OR_A_E(t_mem code) { return or8(destA(), rA, rE); }
+  virtual int OR_A_H(t_mem code) { return or8(destA(), rA, rH); }
+  virtual int OR_A_L(t_mem code) { return or8(destA(), rA, rL); }
+  virtual int OR_A_iHL(t_mem code) { tick(3); return or8(destA(), rA, read8io(rHL)); }
+  virtual int CP_A_B(t_mem code) { return cp8(rA, rB); }
+  virtual int CP_A_C(t_mem code) { return cp8(rA, rC); }
+  virtual int CP_A_D(t_mem code) { return cp8(rA, rD); }
+  virtual int CP_A_E(t_mem code) { return cp8(rA, rE); }
+  virtual int CP_A_H(t_mem code) { return cp8(rA, rH); }
+  virtual int CP_A_L(t_mem code) { return cp8(rA, rL); }
+  virtual int CP_A_iHL(t_mem code) { tick(3); return cp8(rA, read8io(rHL)); }
+  virtual int CP_A_A(t_mem code) { return cp8(rA, rA); }
+
+  virtual int PAGE_CB(t_mem code);
+
+  // Page ED, 3k mode
+  virtual int LD_EIR_A(t_mem code);
+  virtual int LD_IIR_A(t_mem code);
+  virtual int LD_A_EIR(t_mem code);
+  virtual int LD_A_IIR(t_mem code);
+  virtual int LDD(t_mem code) { return ld_d_i(-1); }
+  virtual int LDI(t_mem code) { return ld_d_i(+1); }
+  virtual int LDDR(t_mem code) { return LDxR(-1); }
+  virtual int LDIR(t_mem code) { return LDxR(+1); }
+  virtual int EXX_iSP_HL(t_mem code);
+  virtual int LD_BC_imn(t_mem code) { return ld_dd_imn(destBC()); }
+  virtual int LD_DE_imn(t_mem code) { return ld_dd_imn(destDE()); }
+  virtual int LD_HL_imn_ped(t_mem code) { return ld_dd_imn(destHL()); }
+  virtual int LD_SP_imn(t_mem code) { return ld_dd_imn(cSP); }
+  virtual int SBC_HL_BC(t_mem code) { return sub16(rBC, true); }
+  virtual int SBC_HL_DE(t_mem code) { return sub16(rDE, true); }
+  virtual int SBC_HL_HL(t_mem code) { return sub16(rHL, true); }
+  virtual int SBC_HL_SP(t_mem code) { return sub16(rSP, true); }
+  virtual int ADC_HL_BC(t_mem code) { return adc_hl_ss(rBC); }
+  virtual int ADC_HL_DE(t_mem code) { return adc_hl_ss(rDE); }
+  virtual int ADC_HL_HL(t_mem code) { return adc_hl_ss(rHL); }
+  virtual int ADC_HL_SP(t_mem code) { return adc_hl_ss(rSP); }
+  virtual int LD_aBC_BC(t_mem code) { return ld_add_BC_DE(caBC, rBC); }
+  virtual int LD_aDE_BC(t_mem code) { return ld_add_BC_DE(caDE, rBC); }
+  virtual int LD_aHL_BC(t_mem code) { return ld_add_BC_DE(caHL, rBC); }
+  virtual int LD_aBC_DE(t_mem code) { return ld_add_BC_DE(caBC, rDE); }
+  virtual int LD_aDE_DE(t_mem code) { return ld_add_BC_DE(caDE, rDE); }
+  virtual int LD_aHL_DE(t_mem code) { return ld_add_BC_DE(caHL, rDE); }
+  virtual int LD_imn_BC(t_mem code) { return ld_imn_ss(rBC); }
+  virtual int LD_imn_DE(t_mem code) { return ld_imn_ss(rDE); }
+  virtual int LD_imn_HL_ed(t_mem code) { return ld_imn_ss(rHL); }
+  virtual int LD_imn_SP(t_mem code) { return ld_imn_ss(rSP); }
+  virtual int NEG(t_mem code);
+  virtual int LRET(t_mem code);
+  virtual int IPSET_0(t_mem code) { return ipset(0); }
+  virtual int IPSET_1(t_mem code) { return ipset(1); }
+  virtual int IPSET_2(t_mem code) { return ipset(2); }
+  virtual int IPSET_3(t_mem code) { return ipset(3); }
+  virtual int RETI(t_mem code);
+  virtual int IPRES(t_mem code);
+  virtual int LDP_iHL_HL(t_mem code) { return ldp_irp_rp(rHL, rHL); }
+  virtual int LDP_imn_HL(t_mem code) { tick(3); return ldp_irp_rp(fetch16(), rHL); }
+  virtual int LDP_HL_iHL(t_mem code) { return ldp_rp_irp(cHL, rHL); }
+  virtual int LDP_HL_imn(t_mem code) { tick(3); return ldp_rp_irp(cHL, fetch16()); }
+  virtual int LD_XPC_A(t_mem code);
+  virtual int LD_A_XPC(t_mem code);
+  virtual int PUSH_IP(t_mem code);
+  virtual int POP_IP(t_mem code);
+    
+  // Page DD/FD, 3k mode
+  virtual int LD_IR_mn(t_mem code);
+  virtual int ADD_IR_BC(t_mem code) { return add_ir_xy(rBC); }
+  virtual int ADD_IR_DE(t_mem code) { return add_ir_xy(rDE); }
+  virtual int ADD_IR_IR(t_mem code) { return add_ir_xy(cIR->get()); }
+  virtual int ADD_IR_SP(t_mem code) { return add_ir_xy(rSP); }
+  virtual int INC_iIRd(t_mem code);
+  virtual int DEC_iIRd(t_mem code);
+  virtual int CP_A_iIRd(t_mem code) { tick5p1(7); vc.rd++; return cp8(rA, dest8iIRd(fetch()).R()); }
+  virtual int SBC_A_iIRd(t_mem code) { tick5p1(5); vc.rd++; return sub8(dest8iIRd(fetch()).R(), true); }
+  virtual int SUB_A_iIRd(t_mem code) { tick5p1(5); vc.rd++; return sub8(dest8iIRd(fetch()).R(), false); }
+  virtual int ADD_A_iIRd(t_mem code) { tick5p1(5); vc.rd++; return add8(dest8iIRd(fetch()).R(), false); }
+  virtual int ADC_A_iIRd(t_mem code) { tick5p1(5); vc.rd++; return add8(dest8iIRd(fetch()).R(), true); }
+  virtual int INC_IR(t_mem code);
+  virtual int DEC_IR(t_mem code);
+  virtual int RR_IR(t_mem code) { tick(2); return rot17right(*cIR, cIR->get()); }
+  virtual int XOR_A_iIRd(t_mem code);
+  virtual int OR_A_iIRd(t_mem code);
+  virtual int AND_A_iIRd(t_mem code);
+  virtual int BOOL_IR(t_mem code);
+  virtual int AND_IR_DE(t_mem code);
+  virtual int OR_IR_DE(t_mem code);
+  virtual int POP_IR(t_mem code);
+  virtual int PUSH_IR(t_mem code);
+  virtual int EX_iSP_IR(t_mem code);
+  virtual int LD_iIRd_A(t_mem code) { return ld_iIRd_r(rA); }
+  virtual int LD_iIRd_B(t_mem code) { return ld_iIRd_r(rB); }
+  virtual int LD_iIRd_C(t_mem code) { return ld_iIRd_r(rC); }
+  virtual int LD_iIRd_D(t_mem code) { return ld_iIRd_r(rD); }
+  virtual int LD_iIRd_E(t_mem code) { return ld_iIRd_r(rE); }
+  virtual int LD_iIRd_H(t_mem code) { return ld_iIRd_r(rH); }
+  virtual int LD_iIRd_L(t_mem code) { return ld_iIRd_r(rL); }
+  virtual int LD_A_iIRd(t_mem code) { return ld_r_iIRd(destA()); }
+  virtual int LD_B_iIRd(t_mem code) { return ld_r_iIRd(destB()); }
+  virtual int LD_C_iIRd(t_mem code) { return ld_r_iIRd(destC()); }
+  virtual int LD_D_iIRd(t_mem code) { return ld_r_iIRd(destD()); }
+  virtual int LD_E_iIRd(t_mem code) { return ld_r_iIRd(destE()); }
+  virtual int LD_H_iIRd(t_mem code) { return ld_r_iIRd(destH()); }
+  virtual int LD_L_iIRd(t_mem code) { return ld_r_iIRd(destL()); }
+  virtual int LD_SP_IR(t_mem code);
+  virtual int LD_IR_iSPn(t_mem code);
+  virtual int LD_iSPn_IR(t_mem code);
+  virtual int LD_HL_iIRd(t_mem code);
+  virtual int LD_iIRd_n(t_mem code);
+  virtual int LD_imn_IR(t_mem code);
+  virtual int LD_IR_imn(t_mem code);
+  virtual int LD_HL_IR(t_mem code);
+  virtual int LD_IR_HL(t_mem code);
+  virtual int LD_iHLd_HL(t_mem code);
+  virtual int LDP_iIR_HL(t_mem code) { return ldp_irp_rp(cIR->get(), rHL); }
+  virtual int LDP_imn_IR(t_mem code) { tick(3); return ldp_irp_rp(fetch16(), cIR->get()); }
+  virtual int LDP_HL_iIR(t_mem code) { return ldp_rp_irp(cHL, cIR->get()); }
+  virtual int LDP_IR_imn(t_mem code) { tick(3); return ldp_rp_irp(*cIR, fetch16()); }
+  virtual int JP_IR(t_mem code) { tick(5); PC= cIR->get(); return resGO; }
+  virtual int PAGE_DD_CB(t_mem code);
+};
+
+
+enum rxkcpu_cfg {
+  //rxk_cpu_xpc		= 0,
+
+  rxk_cpu_nuof	= 0
+};
+
+class cl_rxk_cpu: public cl_hw
+{
+protected:
+  class cl_rxk *ruc;
+  class cl_memory_cell *segsize, *dataseg, *stackseg;
+public:
+  cl_rxk_cpu(class cl_uc *auc);
+  virtual int init(void);
+  //virtual unsigned int cfg_size() { return rxk_cpu_nuof; }
+  virtual const char *cfg_help(t_addr addr);
+  
+  virtual void write(class cl_memory_cell *cell, t_mem *val);
+  //virtual t_mem conf_op(cl_memory_cell *cell, t_addr addr, t_mem *val);
+
+  virtual void print_info(class cl_console_base *con);
+};
+
+
+#endif
+
+/* End of rxk.src/rxk.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/simrxk.cc sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/simrxk.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/simrxk.cc	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/simrxk.cc	2021-08-16 10:12:33.000000000 +0000
@@ -0,0 +1,105 @@
+/*
+ * Simulator of microcontrollers (simrxk.cc)
+ *
+ * Copyright (C) 2020,2021 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+// local
+#include "simrxkcl.h"
+#include "r6kcl.h"
+
+
+struct cpu_entry cpus_rxk[]=
+  {
+    {"R2K"	, CPU_R2K , 0, "Rabbit 2000", ""},
+    {"2K"	, CPU_R2K , 0, "Rabbit 2000", ""},
+    {"2"	, CPU_R2K , 0, "Rabbit 2000", ""},
+    {"R3KA"	, CPU_R3KA, 0, "Rabbit 3000A", ""},
+    {"3KA"	, CPU_R3KA, 0, "Rabbit 3000A", ""},
+    {"3A"	, CPU_R3KA, 0, "Rabbit 3000A", ""},
+    {"R3K"	, CPU_R3K , 0, "Rabbit 3000", ""},
+    {"3K"	, CPU_R3K , 0, "Rabbit 3000", ""},
+    {"3"	, CPU_R3K , 0, "Rabbit 3000", ""},
+    {"R4K"	, CPU_R4K , 0, "Rabbit 4000", ""},
+    {"4K"	, CPU_R4K , 0, "Rabbit 4000", ""},
+    {"4"	, CPU_R4K , 0, "Rabbit 4000", ""},
+    {"R5K"	, CPU_R5K , 0, "Rabbit 5000", ""},
+    {"5K"	, CPU_R5K , 0, "Rabbit 5000", ""},
+    {"5"	, CPU_R5K , 0, "Rabbit 5000", ""},
+    {"R6K"	, CPU_R6K , 0, "Rabbit 6000", ""},
+    {"6K"	, CPU_R6K , 0, "Rabbit 6000", ""},
+    {"6"	, CPU_R6K , 0, "Rabbit 6000", ""},
+    {NULL, CPU_NONE, 0, "", ""}
+  };
+
+
+cl_simrxk::cl_simrxk(class cl_app *the_app):
+  cl_sim(the_app)
+{}
+
+class cl_uc *
+cl_simrxk::mk_controller(void)
+{
+  int i;
+  const char *typ= 0;
+  class cl_optref type_option(this);
+  
+  type_option.init();
+  type_option.use("cpu_type");
+  i= 0;
+  if ((typ= type_option.get_value(typ)) == 0)
+    typ= "R2K";
+
+  while ((cpus_rxk[i].type_str != NULL) &&
+	 (strcasecmp(typ, cpus_rxk[i].type_str) != 0))
+    i++;
+  if (cpus_rxk[i].type_str == NULL)
+    {
+      fprintf(stderr, "Unknown processor type. "
+	      "Use -H option to see known types.\n");
+      return(NULL);
+    }
+  switch (cpus_rxk[i].type)
+    {
+    case CPU_R2K:
+      return(new cl_r2k(this));
+    case CPU_R3K:
+      return(new cl_r3k(this));
+    case CPU_R3KA:
+      return(new cl_r3ka(this));
+    case CPU_R4K:
+      return(new cl_r4k(this));
+    case CPU_R5K:
+      return(new cl_r5k(this));
+    case CPU_R6K:
+      return(new cl_r6k(this));
+    default:
+      fprintf(stderr, "Unknown processor type\n");
+      return NULL;
+    }
+  return NULL;
+}
+
+
+/* End of rxk.src/simrxk.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/simrxkcl.h sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/simrxkcl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/simrxkcl.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/simrxkcl.h	2021-07-16 14:31:13.000000000 +0000
@@ -0,0 +1,46 @@
+/*
+ * Simulator of microcontrollers (simrxkcl.h)
+ *
+ * Copyright (C) 2020,2021 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef SIMRXKCL_HEADER
+#define SIMRXKCL_HEADER
+
+#include "simcl.h"
+
+
+extern struct cpu_entry cpus_rxk[];
+
+class cl_simrxk: public cl_sim
+{
+public:
+  cl_simrxk(class cl_app *the_app);
+  virtual class cl_uc *mk_controller(void);
+};
+
+
+#endif
+
+/* End of rxk.src/simrxkcl.h */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/srxk.cc sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/srxk.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/srxk.cc	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/srxk.cc	2021-08-16 10:12:33.000000000 +0000
@@ -0,0 +1,57 @@
+/*
+ * Simulator of microcontrollers (srxk.cc)
+ *
+ * Copyright (C) 2020,2021 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+// prj
+#include "globals.h"
+
+// local
+#include "glob.h"
+#include "simrxkcl.h"
+
+
+int
+main(int argc, char *argv[])
+{
+  class cl_sim *sim;
+
+  init_sbox();
+  cpus= cpus_rxk;
+  application= new cl_app();
+  application->set_name("srxk");
+  application->init(argc, argv);
+  sim= new cl_simrxk(application);
+  if (sim->init())
+    sim->state|= SIM_QUIT;
+  application->set_simulator(sim);
+  //sim->main();
+  application->run();
+  application->done();
+  delete application;
+  return(0);
+}
+
+/* End of rxk.src/srxk.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/test/clean.mk sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/test/clean.mk
--- sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/test/clean.mk	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/test/clean.mk	2021-04-23 13:47:20.000000000 +0000
@@ -0,0 +1,5 @@
+clean:
+
+distclean:
+	rm -f Makefile
+	find . -type d -name out -exec rm -rf {} \;
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/test/config/baseline/R2K sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/test/config/baseline/R2K
--- sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/test/config/baseline/R2K	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/test/config/baseline/R2K	2022-02-08 21:21:05.000000000 +0000
@@ -0,0 +1,35 @@
+uCsim, Copyright (C)  Daniel Drotos.
+uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+This is free software, and you are welcome to redistribute it
+under certain conditions; type `show c' for details.
+Type of microcontroller: R2K
+Controller has 4 hardware element(s).
+   on cpu[0]
+   on simif[0]
+  off vcd[0]
+   on dreg[0]
+A= 0x00   0 .  F= 00000000 0x00   0 .
+                  SZxxxVxC
+XPC= 0x00 IP= 0xff IIR= 0x00 EIR= 0x00
+BC= 0x0000 00 00 00 00 00 00 00 00 ........
+DE= 0x0000 00 00 00 00 00 00 00 00 ........
+HL= 0x0000 00 00 00 00 00 00 00 00 ........
+IX= 0x0000 00 00 00 00 00 00 00 00 ........
+IY= 0x0000 00 00 00 00 00 00 00 00 ........
+SP= 0x0000 00 00 00 00 00 00 00 00 ........
+aAF= 0x00-0x00  aBC= 0x00-0x00  aDE= 0x00-0x00  aHL= 0x00-0x00  
+0x0000  ? 00          NOP[0K
+Memory chips:
+  0x000000-0x0000ff      256 variable_storage (32,%08x,0x%02lx)
+  0x000000-0x0fffff  1048576 rom_chip (8,%02x,0x%05lx)
+  0x000000-0x00ffff    65536 ioi_chip (8,%02x,0x%04lx)
+  0x000000-0x00ffff    65536 ioe_chip (8,%02x,0x%04lx)
+Address spaces:
+  0x000000-0x0000ff      256 variables (32,%08x,0x%02lx)
+  0x000000-0x00ffff    65536 rom (8,%02x,0x%04lx)
+  0x000000-0x00ffff    65536 ioi (8,%02x,0x%04lx)
+  0x000000-0x00ffff    65536 ioe (8,%02x,0x%04lx)
+Address decoders:
+  variables 0x00 0xff -> variable_storage 0x00 activated
+  ioi 0x0000 0xffff -> ioi_chip 0x0000 activated
+  ioe 0x0000 0xffff -> ioe_chip 0x0000 activated
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/test/config/baseline/R3K sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/test/config/baseline/R3K
--- sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/test/config/baseline/R3K	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/test/config/baseline/R3K	2022-02-08 21:21:05.000000000 +0000
@@ -0,0 +1,35 @@
+uCsim, Copyright (C)  Daniel Drotos.
+uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+This is free software, and you are welcome to redistribute it
+under certain conditions; type `show c' for details.
+Type of microcontroller: R3K
+Controller has 4 hardware element(s).
+   on cpu[0]
+   on simif[0]
+  off vcd[0]
+   on dreg[0]
+A= 0x00   0 .  F= 00000000 0x00   0 .
+                  SZxxxVxC
+XPC= 0x00 IP= 0xff IIR= 0x00 EIR= 0x00
+BC= 0x0000 00 00 00 00 00 00 00 00 ........
+DE= 0x0000 00 00 00 00 00 00 00 00 ........
+HL= 0x0000 00 00 00 00 00 00 00 00 ........
+IX= 0x0000 00 00 00 00 00 00 00 00 ........
+IY= 0x0000 00 00 00 00 00 00 00 00 ........
+SP= 0x0000 00 00 00 00 00 00 00 00 ........
+aAF= 0x00-0x00  aBC= 0x00-0x00  aDE= 0x00-0x00  aHL= 0x00-0x00  
+0x0000  ? 00          NOP[0K
+Memory chips:
+  0x000000-0x0000ff      256 variable_storage (32,%08x,0x%02lx)
+  0x000000-0x0fffff  1048576 rom_chip (8,%02x,0x%05lx)
+  0x000000-0x00ffff    65536 ioi_chip (8,%02x,0x%04lx)
+  0x000000-0x00ffff    65536 ioe_chip (8,%02x,0x%04lx)
+Address spaces:
+  0x000000-0x0000ff      256 variables (32,%08x,0x%02lx)
+  0x000000-0x00ffff    65536 rom (8,%02x,0x%04lx)
+  0x000000-0x00ffff    65536 ioi (8,%02x,0x%04lx)
+  0x000000-0x00ffff    65536 ioe (8,%02x,0x%04lx)
+Address decoders:
+  variables 0x00 0xff -> variable_storage 0x00 activated
+  ioi 0x0000 0xffff -> ioi_chip 0x0000 activated
+  ioe 0x0000 0xffff -> ioe_chip 0x0000 activated
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/test/config/baseline/R3KA sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/test/config/baseline/R3KA
--- sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/test/config/baseline/R3KA	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/test/config/baseline/R3KA	2022-02-08 21:21:05.000000000 +0000
@@ -0,0 +1,35 @@
+uCsim, Copyright (C)  Daniel Drotos.
+uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+This is free software, and you are welcome to redistribute it
+under certain conditions; type `show c' for details.
+Type of microcontroller: R3KA
+Controller has 4 hardware element(s).
+   on cpu[0]
+   on simif[0]
+  off vcd[0]
+   on dreg[0]
+A= 0x00   0 .  F= 00000000 0x00   0 .
+                  SZxxxVxC
+XPC= 0x00 IP= 0xff IIR= 0x00 EIR= 0x00 SU= 0x00
+BC= 0x0000 00 00 00 00 00 00 00 00 ........
+DE= 0x0000 00 00 00 00 00 00 00 00 ........
+HL= 0x0000 00 00 00 00 00 00 00 00 ........
+IX= 0x0000 00 00 00 00 00 00 00 00 ........
+IY= 0x0000 00 00 00 00 00 00 00 00 ........
+SP= 0x0000 00 00 00 00 00 00 00 00 ........
+aAF= 0x00-0x00  aBC= 0x00-0x00  aDE= 0x00-0x00  aHL= 0x00-0x00  
+0x0000  ? 00          NOP[0K
+Memory chips:
+  0x000000-0x0000ff      256 variable_storage (32,%08x,0x%02lx)
+  0x000000-0x0fffff  1048576 rom_chip (8,%02x,0x%05lx)
+  0x000000-0x00ffff    65536 ioi_chip (8,%02x,0x%04lx)
+  0x000000-0x00ffff    65536 ioe_chip (8,%02x,0x%04lx)
+Address spaces:
+  0x000000-0x0000ff      256 variables (32,%08x,0x%02lx)
+  0x000000-0x00ffff    65536 rom (8,%02x,0x%04lx)
+  0x000000-0x00ffff    65536 ioi (8,%02x,0x%04lx)
+  0x000000-0x00ffff    65536 ioe (8,%02x,0x%04lx)
+Address decoders:
+  variables 0x00 0xff -> variable_storage 0x00 activated
+  ioi 0x0000 0xffff -> ioi_chip 0x0000 activated
+  ioe 0x0000 0xffff -> ioe_chip 0x0000 activated
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/test/config/baseline/R4K sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/test/config/baseline/R4K
--- sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/test/config/baseline/R4K	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/test/config/baseline/R4K	2022-02-08 21:21:05.000000000 +0000
@@ -0,0 +1,38 @@
+uCsim, Copyright (C)  Daniel Drotos.
+uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+This is free software, and you are welcome to redistribute it
+under certain conditions; type `show c' for details.
+Type of microcontroller: R4K
+Controller has 4 hardware element(s).
+   on cpu[0]
+   on simif[0]
+  off vcd[0]
+   on dreg[0]
+A= 0x00   0 .  F= 00000000 0x00   0 .  Mode:3k
+                  SZxxxVxC
+XPC= 0x000 IP= 0xff IIR= 0x00 EIR= 0x00
+BC= 0x0000 00 00 00 00 00 00 00 00 ........
+DE= 0x0000 00 00 00 00 00 00 00 00 ........
+HL= 0x0000 00 00 00 00 00 00 00 00 ........
+IX= 0x0000 00 00 00 00 00 00 00 00 ........
+IY= 0x0000 00 00 00 00 00 00 00 00 ........
+JK= 0x0000 00 00 00 00 00 00 00 00 ........
+SP= 0x0000 00 00 00 00 00 00 00 00 ........
+aAF= 0x00-00  aBC= 0x00-00  aDE= 0x00-00  aHL= 0x00-00  aJK= 0x00-00  
+ PW= 0x0000-0000   PX= 0x0000-0000   PY= 0x0000-0000   PZ= 0x0000-0000  
+aPW= 0x0000-0000  aPX= 0x0000-0000  aPY= 0x0000-0000  aPZ= 0x0000-0000  
+0x0000  ? 00                NOP[0K
+Memory chips:
+  0x000000-0x0000ff      256 variable_storage (32,%08x,0x%02lx)
+  0x000000-0xffffff 16777216 rom_chip (8,%02x,0x%06lx)
+  0x000000-0x00ffff    65536 ioi_chip (8,%02x,0x%04lx)
+  0x000000-0x00ffff    65536 ioe_chip (8,%02x,0x%04lx)
+Address spaces:
+  0x000000-0x0000ff      256 variables (32,%08x,0x%02lx)
+  0x000000-0x00ffff    65536 rom (8,%02x,0x%04lx)
+  0x000000-0x00ffff    65536 ioi (8,%02x,0x%04lx)
+  0x000000-0x00ffff    65536 ioe (8,%02x,0x%04lx)
+Address decoders:
+  variables 0x00 0xff -> variable_storage 0x00 activated
+  ioi 0x0000 0xffff -> ioi_chip 0x0000 activated
+  ioe 0x0000 0xffff -> ioe_chip 0x0000 activated
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/test/config/baseline/R5K sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/test/config/baseline/R5K
--- sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/test/config/baseline/R5K	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/test/config/baseline/R5K	2022-02-08 21:21:05.000000000 +0000
@@ -0,0 +1,38 @@
+uCsim, Copyright (C)  Daniel Drotos.
+uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+This is free software, and you are welcome to redistribute it
+under certain conditions; type `show c' for details.
+Type of microcontroller: R5K
+Controller has 4 hardware element(s).
+   on cpu[0]
+   on simif[0]
+  off vcd[0]
+   on dreg[0]
+A= 0x00   0 .  F= 00000000 0x00   0 .  Mode:3k
+                  SZxxxVxC
+XPC= 0x000 IP= 0xff IIR= 0x00 EIR= 0x00
+BC= 0x0000 00 00 00 00 00 00 00 00 ........
+DE= 0x0000 00 00 00 00 00 00 00 00 ........
+HL= 0x0000 00 00 00 00 00 00 00 00 ........
+IX= 0x0000 00 00 00 00 00 00 00 00 ........
+IY= 0x0000 00 00 00 00 00 00 00 00 ........
+JK= 0x0000 00 00 00 00 00 00 00 00 ........
+SP= 0x0000 00 00 00 00 00 00 00 00 ........
+aAF= 0x00-00  aBC= 0x00-00  aDE= 0x00-00  aHL= 0x00-00  aJK= 0x00-00  
+ PW= 0x0000-0000   PX= 0x0000-0000   PY= 0x0000-0000   PZ= 0x0000-0000  
+aPW= 0x0000-0000  aPX= 0x0000-0000  aPY= 0x0000-0000  aPZ= 0x0000-0000  
+0x0000  ? 00                NOP[0K
+Memory chips:
+  0x000000-0x0000ff      256 variable_storage (32,%08x,0x%02lx)
+  0x000000-0xffffff 16777216 rom_chip (8,%02x,0x%06lx)
+  0x000000-0x00ffff    65536 ioi_chip (8,%02x,0x%04lx)
+  0x000000-0x00ffff    65536 ioe_chip (8,%02x,0x%04lx)
+Address spaces:
+  0x000000-0x0000ff      256 variables (32,%08x,0x%02lx)
+  0x000000-0x00ffff    65536 rom (8,%02x,0x%04lx)
+  0x000000-0x00ffff    65536 ioi (8,%02x,0x%04lx)
+  0x000000-0x00ffff    65536 ioe (8,%02x,0x%04lx)
+Address decoders:
+  variables 0x00 0xff -> variable_storage 0x00 activated
+  ioi 0x0000 0xffff -> ioi_chip 0x0000 activated
+  ioe 0x0000 0xffff -> ioe_chip 0x0000 activated
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/test/config/baseline/R6K sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/test/config/baseline/R6K
--- sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/test/config/baseline/R6K	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/test/config/baseline/R6K	2022-02-08 21:21:05.000000000 +0000
@@ -0,0 +1,38 @@
+uCsim, Copyright (C)  Daniel Drotos.
+uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+This is free software, and you are welcome to redistribute it
+under certain conditions; type `show c' for details.
+Type of microcontroller: R6K
+Controller has 4 hardware element(s).
+   on cpu[0]
+   on simif[0]
+  off vcd[0]
+   on dreg[0]
+A= 0x00   0 .  F= 00000000 0x00   0 .  Mode:3k
+                  SZxxxVxC
+XPC= 0x000 IP= 0xff IIR= 0x00 EIR= 0x00
+BC= 0x0000 00 00 00 00 00 00 00 00 ........
+DE= 0x0000 00 00 00 00 00 00 00 00 ........
+HL= 0x0000 00 00 00 00 00 00 00 00 ........
+IX= 0x0000 00 00 00 00 00 00 00 00 ........
+IY= 0x0000 00 00 00 00 00 00 00 00 ........
+JK= 0x0000 00 00 00 00 00 00 00 00 ........
+SP= 0x0000 00 00 00 00 00 00 00 00 ........
+aAF= 0x00-00  aBC= 0x00-00  aDE= 0x00-00  aHL= 0x00-00  aJK= 0x00-00  
+ PW= 0x0000-0000   PX= 0x0000-0000   PY= 0x0000-0000   PZ= 0x0000-0000  
+aPW= 0x0000-0000  aPX= 0x0000-0000  aPY= 0x0000-0000  aPZ= 0x0000-0000  
+0x0000  ? 00                NOP[0K
+Memory chips:
+  0x000000-0x0000ff      256 variable_storage (32,%08x,0x%02lx)
+  0x000000-0xffffff 16777216 rom_chip (8,%02x,0x%06lx)
+  0x000000-0x00ffff    65536 ioi_chip (8,%02x,0x%04lx)
+  0x000000-0x00ffff    65536 ioe_chip (8,%02x,0x%04lx)
+Address spaces:
+  0x000000-0x0000ff      256 variables (32,%08x,0x%02lx)
+  0x000000-0x00ffff    65536 rom (8,%02x,0x%04lx)
+  0x000000-0x00ffff    65536 ioi (8,%02x,0x%04lx)
+  0x000000-0x00ffff    65536 ioe (8,%02x,0x%04lx)
+Address decoders:
+  variables 0x00 0xff -> variable_storage 0x00 activated
+  ioi 0x0000 0xffff -> ioi_chip 0x0000 activated
+  ioe 0x0000 0xffff -> ioe_chip 0x0000 activated
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/test/config/Makefile sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/test/config/Makefile
--- sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/test/config/Makefile	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/test/config/Makefile	2021-05-20 07:49:29.000000000 +0000
@@ -0,0 +1,8 @@
+OUTPUTS = $(filter-out Parameter, $(shell $(SIM) -H | sort -u -k2b | cut -d' ' -f1))
+
+
+$(OUTPUTS):
+	$(call run-sim, -t $(@F) -e 'conf; info reg; info mem')
+
+
+include test-lib.mk
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/test/Makefile.in sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/test/Makefile.in
--- sdcc-4.0.0+dfsg/sim/ucsim/rxk.src/test/Makefile.in	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/rxk.src/test/Makefile.in	2021-04-23 13:47:20.000000000 +0000
@@ -0,0 +1,9 @@
+# @configure_input@
+
+srcdir           = @abs_srcdir@
+
+abs_top_builddir = @abs_top_builddir@
+abs_top_srcdir   = @abs_top_srcdir@
+
+
+include $(abs_top_srcdir)/test-target.mk
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/arith.cc sdcc-4.2.0+dfsg/sim/ucsim/s51.src/arith.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/arith.cc	2017-06-04 15:33:30.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/arith.cc	2020-11-05 14:35:58.000000000 +0000
@@ -25,9 +25,9 @@
 02111-1307, USA. */
 /*@1@*/
 
-#include "ddconfig.h"
+//#include "ddconfig.h"
 
-#include 
+//#include 
 
 // local
 #include "uc51cl.h"
@@ -366,16 +366,18 @@
 
   pw= psw->get();
   pw&= ~bmCY;
+  ac= acc->get();
   if (!(b= sfr->get(B)))
     pw|= bmOV;
   else
     {
       pw&= ~bmOV;
-      temp= (ac= acc->get()) / b;
+      temp= (ac) / b;
       sfr->write(B, ac % b);
-      acc->write(temp);
+      ac= temp;
     }
   psw->write(pw);
+  acc->write(ac);
   tick(3);
   vc.rd++;//= 2;
   vc.wr++;//= 2;
@@ -400,13 +402,13 @@
   pw= psw->get();
   if ((c= (pw & bmCY)?1:0))
     result--;
+  psw->set((pw & ~(bmCY|bmOV|bmAC)) |
+	   (((unsigned int)ac < (unsigned int)(data+c))?bmCY:0) |
+	   (((ac<0x80 && data>0x7f && result>0x7f) ||
+	     (ac>0x7f && data<0x80 && result<0x80))?bmOV:0) |
+	   (((ac&0x0f) < ((data+c)&0x0f) ||
+	     (c && ((data&0x0f)==0x0f)))?bmAC:0));
   acc->write(result);
-  psw->write((pw & ~(bmCY|bmOV|bmAC)) |
-	     (((unsigned int)ac < (unsigned int)(data+c))?bmCY:0) |
-	     (((ac<0x80 && data>0x7f && result>0x7f) ||
-	       (ac>0x7f && data<0x80 && result<0x80))?bmOV:0) |
-	     (((ac&0x0f) < ((data+c)&0x0f) ||
-	       (c && ((data&0x0f)==0x0f)))?bmAC:0));
   //vc.rd++;
   //vc.wr++;
   return(resGO);
@@ -432,13 +434,13 @@
   pw= psw->get();
   if ((c= (pw & bmCY)?1:0))
     result--;
-  acc->write(result);
   psw->set((pw & ~(bmCY|bmOV|bmAC)) |
 	   (((unsigned int)ac < (unsigned int)(data+c))?bmCY:0) |
 	   (((ac<0x80 && data>0x7f && result>0x7f) ||
 	     (ac>0x7f && data<0x80 && result<0x80))?bmOV:0) |
 	   (((ac&0x0f) < ((data+c)&0x0f) ||
 	     (c && ((data&0x0f)==0x0f)))?bmAC:0));
+  acc->write(result);
   vc.rd++;//= 2;
   //vc.rd++;
   return(resGO);
@@ -464,13 +466,13 @@
   pw= psw->get();
   if ((c= (pw & bmCY)?1:0))
     result--;
-  acc->write(result);
   psw->write((pw & ~(bmCY|bmOV|bmAC)) |
 	     (((unsigned int)ac < (unsigned int)(data+c))?bmCY:0) |
 	     (((ac<0x80 && data>0x7f && result>0x7f) ||
 	       (ac>0x7f && data<0x80 && result<0x80))?bmOV:0) |
 	     (((ac&0x0f) < ((data+c)&0x0f) ||
 	       (c && ((data&0x0f)==0x0f)))?bmAC:0));
+  acc->write(result);
   vc.rd++;//= 3;
   //vc.wr++;
   return(resGO);
@@ -494,13 +496,13 @@
   pw= psw->get();
   if ((c= (pw & bmCY)?1:0))
     result--;
-  acc->write(result);
   psw->write((pw & ~(bmCY|bmOV|bmAC)) |
 	     (((unsigned int)ac < (unsigned int)(data+c))?bmCY:0) |
 	     (((ac<0x80 && data>0x7f && result>0x7f) ||
 	       (ac>0x7f && data<0x80 && result<0x80))?bmOV:0) |
 	     (((ac&0x0f) < ((data+c)&0x0f) ||
 	       (c && ((data&0x0f)==0x0f)))?bmAC:0));
+  acc->write(result);
   //vc.rd+= 2;
   //vc.wr++;
   return(resGO);
@@ -559,8 +561,8 @@
 	pw|= bmCY;
       ac+= 0x60;
     }
-  acc->write(ac);
   psw->write(pw);
+  acc->write(ac);
   //vc.rd++;
   //vc.wr++;
   return(resGO);
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/bit.cc sdcc-4.2.0+dfsg/sim/ucsim/s51.src/bit.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/bit.cc	2017-02-24 11:48:49.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/bit.cc	2020-03-27 20:18:53.000000000 +0000
@@ -25,12 +25,12 @@
 02111-1307, USA. */
 /*@1@*/
 
-#include "ddconfig.h"
+//#include "ddconfig.h"
 
 // local
 #include "uc51cl.h"
-#include "regs51.h"
-#include "types51.h"
+//#include "regs51.h"
+//#include "types51.h"
 
 
 /*
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/clean.mk sdcc-4.2.0+dfsg/sim/ucsim/s51.src/clean.mk
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/clean.mk	2017-02-24 11:48:49.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/clean.mk	2021-09-19 19:38:05.000000000 +0000
@@ -6,7 +6,9 @@
 	rm -f *core *[%~] *.[oa]
 	rm -f test_*.??* '(null).cdb' *.lnk *.ihx
 	rm -f .[a-z]*~
-	rm -f s51$(EXEEXT)
+	rm -f s51 s51.exe
+	rm -f ucsim_51 ucsim_51.exe
+	$(MAKE) -C test -f clean.mk clean
 
 
 # Deleting all files created by configuring or building the program
@@ -14,6 +16,7 @@
 distclean: clean
 	rm -f config.cache config.log config.status
 	rm -f Makefile *.dep
+	$(MAKE) -C test -f clean.mk distclean
 
 
 # Like clean but some files may still exist
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/inc.cc sdcc-4.2.0+dfsg/sim/ucsim/s51.src/inc.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/inc.cc	2017-02-24 11:48:49.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/inc.cc	2021-04-25 20:38:36.000000000 +0000
@@ -25,11 +25,11 @@
 02111-1307, USA. */
 /*@1@*/
 
-#include "ddconfig.h"
+//#include "ddconfig.h"
 
 // local
 #include "uc51cl.h"
-#include "regs51.h"
+//#include "regs51.h"
 
 
 /*
@@ -41,7 +41,7 @@
 int
 cl_51core::instruction_04/*inst_inc_a*/(t_mem/*uchar*/ code)
 {
-  acc->wadd(1);
+  acc->write(acc->read() + 1);
   return(resGO);
   //vc.rd++;
   //vc.wr++;
@@ -79,7 +79,7 @@
   class cl_memory_cell *cell;
 
   cell= iram->get_cell(R[code & 0x01]->read());
-  cell->wadd(1);
+  cell->write(cell->read() + 1);
   vc.rd++;//= 2;
   vc.wr++;
   return(resGO);
@@ -97,7 +97,7 @@
 {
   class cl_memory_cell *reg= R[code & 0x07];
 
-  reg->wadd(1);
+  reg->write(reg->read() + 1);
   //vc.rd++;
   //vc.wr++;
   return(resGO);
@@ -113,7 +113,7 @@
 int
 cl_51core::instruction_14/*inst_dec_a*/(t_mem/*uchar*/ code)
 {
-  acc->wadd(-1);
+  acc->write(acc->read() - 1);
   //vc.rd++;
   //vc.wr++;
   return(resGO);
@@ -152,7 +152,7 @@
   class cl_memory_cell *cell;
 
   cell= iram->get_cell(R[code & 0x01]->read());
-  cell->add(-1);
+  cell->set(cell->get() - 1);
   vc.rd++;//= 2;
   vc.wr++;
   return(resGO);
@@ -170,7 +170,7 @@
 {
   class cl_memory_cell *reg= R[code & 0x07];
 
-  reg->wadd(-1);
+  reg->write(reg->read() - 1);
   //vc.rd++;
   //vc.wr++;
   return(resGO);
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/interrupt.cc sdcc-4.2.0+dfsg/sim/ucsim/s51.src/interrupt.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/interrupt.cc	2019-04-02 10:46:33.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/interrupt.cc	2022-01-26 16:35:40.000000000 +0000
@@ -25,8 +25,9 @@
 02111-1307, USA. */
 /*@1@*/
 
+//#include 
+
 // prj
-#include 
 #include "utils.h"
 
 // sim
@@ -109,9 +110,9 @@
 cl_interrupt::tick(int cycles)
 {
   if (!bit_IT0 && !bit_INT0)
-    cell_tcon->set_bit1(bmIE0);
+    cell_tcon->set(cell_tcon->get() | bmIE0);
   if (!bit_IT1 && !bit_INT1)
-    cell_tcon->set_bit1(bmIE1);
+    cell_tcon->set(cell_tcon->get() | bmIE1);
   return(resGO);
 }
 
@@ -126,7 +127,7 @@
 {
   struct ev_port_changed *ep= (struct ev_port_changed *)params;
 
-  if (where->cathegory == HW_PORT &&
+  if (where->category == HW_PORT &&
       he == EV_PORT_CHANGED &&
       ep->id == 3)
     {
@@ -135,11 +136,11 @@
       if (bit_IT0 &&
 	  !(p3n & bm_INT0) &&
 	  (p3o & bm_INT0))
-	cell_tcon->set_bit1(bmIE0);
+	cell_tcon->set(cell_tcon->get() | bmIE0);
       if (bit_IT1 &&
 	  !(p3n & bm_INT1) &&
 	  (p3o & bm_INT1))
-	cell_tcon->set_bit1(bmIE1);
+	cell_tcon->set(cell_tcon->get() | bmIE1);
       bit_INT0= p3n & bm_INT0;
       bit_INT1= p3n & bm_INT1;
     }
@@ -181,7 +182,7 @@
 	  con->dd_printf("\n");
 	}
     }
-  print_cfg_info(con);
+  //print_cfg_info(con);
 }
 
 
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/interruptcl.h sdcc-4.2.0+dfsg/sim/ucsim/s51.src/interruptcl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/interruptcl.h	2019-04-02 10:46:33.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/interruptcl.h	2020-08-22 10:25:08.000000000 +0000
@@ -44,7 +44,7 @@
 public:
   cl_interrupt(class cl_uc *auc);
   virtual int init(void);
-  //virtual char *cfg_help(t_addr addr);
+  //virtual const char *cfg_help(t_addr addr);
   
   virtual void added_to_uc(void);
 
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/jmp.cc sdcc-4.2.0+dfsg/sim/ucsim/s51.src/jmp.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/jmp.cc	2017-02-24 11:48:49.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/jmp.cc	2021-04-25 20:38:36.000000000 +0000
@@ -29,16 +29,16 @@
  *	relative<->absolute jump in "jmp @a+dptr"
  */
 
-#include "ddconfig.h"
+//#include "ddconfig.h"
 
-#include 
-#include 
+//#include 
+//#include 
 
 // local
 #include "uc51cl.h"
 #include "regs51.h"
-#include "types51.h"
-#include "interruptcl.h"
+//#include "types51.h"
+//#include "interruptcl.h"
 
 
 /*
@@ -123,13 +123,13 @@
   h= (code >> 5) & 0x07;
   l= fetch();
   sp_before= sfr->get(SP);
-  sp= sfr->wadd(SP, 1);
+  sp= sfr->write(SP, sfr->read(SP) + 1);
   //proc_write_sp(sp);
   stck= iram->get_cell(sp);
   stck->write(PC & 0xff); // push low byte
   tick(1);
 
-  sp= /*sp_after*= */sfr->wadd(SP, 1);
+  sp= /*sp_after*= */sfr->write(SP, sfr->read(SP) + 1);
   //proc_write_sp(sp);
   stck= iram->get_cell(sp);
   stck->write((PC >> 8) & 0xff); // push high byte
@@ -162,14 +162,14 @@
       l= fetch();
     }
   sp_before= sfr->get(SP);
-  sp= sfr->wadd(SP, 1);
+  sp= sfr->write(SP, sfr->read(SP) + 1);
   //proc_write_sp(sp);
   stck= iram->get_cell(sp);
   stck->write(PC & 0xff); // push low byte
   if (!addr)
     tick(1);
 
-  sp= sfr->wadd(SP, 1);
+  sp= sfr->write(SP, sfr->read(SP) + 1);
   //proc_write_sp(sp);
   stck= iram->get_cell(sp);
   stck->write((PC >> 8) & 0xff); // push high byte
@@ -233,12 +233,12 @@
   sp= sp_before= sfr->read(SP);
   stck= iram->get_cell(sp);
   h= stck->read();
-  sp= sfr->wadd(SP, -1);
+  sp= sfr->write(SP, sfr->read(SP) - 1);
   tick(1);
 
   stck= iram->get_cell(sp);
   l= stck->read();
-  sp= sfr->wadd(SP, -1);
+  sp= sfr->write(SP, sfr->read(SP)  - 1);
   PC= h*256 + l;
   class cl_stack_op *so= new cl_stack_ret(instPC, PC, sp_before, sp/*_after*/);
   so->init();
@@ -291,12 +291,12 @@
   sp= sp_before= sfr->read(SP);
   stck= iram->get_cell(sp);
   h= stck->read();
-  sp= sfr->wadd(SP, -1);
+  sp= sfr->write(SP, sfr->read(SP) - 1);
   tick(1);
 
   stck= iram->get_cell(sp);
   l= stck->read();
-  sp= sp_after= sfr->wadd(SP, -1);
+  sp= sp_after= sfr->write(SP, sfr->read(SP) - 1);
   PC= h*256 + l;
 
   interrupt->was_reti= true;
@@ -564,7 +564,7 @@
   reg  = R[code & 0x07];
   jaddr= fetch();
   tick(1);
-  t_mem r= reg->wadd(-1);
+  t_mem r= reg->write(reg->read() - 1);
   if (r)
     PC= rom->validate_address(PC + (signed char)jaddr);
   //vc.rd++;
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/logic.cc sdcc-4.2.0+dfsg/sim/ucsim/s51.src/logic.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/logic.cc	2017-02-24 11:48:49.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/logic.cc	2020-03-27 20:18:53.000000000 +0000
@@ -25,14 +25,14 @@
 02111-1307, USA. */
 /*@1@*/
 
-#include "ddconfig.h"
+//#include "ddconfig.h"
 
 // prj
-#include "stypes.h"
+//#include "stypes.h"
 
 // local
 #include "uc51cl.h"
-#include "regs51.h"
+//#include "regs51.h"
 
 
 /*
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/Makefile.in sdcc-4.2.0+dfsg/sim/ucsim/s51.src/Makefile.in
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/Makefile.in	2018-01-25 13:48:09.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/Makefile.in	2022-01-13 08:20:03.000000000 +0000
@@ -4,6 +4,9 @@
 # (c) Drotos Daniel, Talker Bt. 1997
 #
 
+# tool name
+TN		= 51
+
 STARTYEAR	= 1997
 
 SHELL		= /bin/sh
@@ -21,13 +24,13 @@
 transform	= @program_transform_name@
 
 DEFS            = $(subs -DHAVE_CONFIG_H,,@DEFS@)
+PICOPT		= @PICOPT@
 CPPFLAGS        = @CPPFLAGS@ -I$(srcdir) -I$(top_srcdir) -I$(top_builddir) \
 		  -I$(top_srcdir)/cmd.src -I$(top_srcdir)/sim.src \
 		  -I$(top_srcdir)/gui.src
-CFLAGS          = @CFLAGS@ @WALL_FLAG@
-CXXFLAGS        = @CXXFLAGS@ @WALL_FLAG@
+CFLAGS          = @WALL_FLAG@ @CFLAGS@
+CXXFLAGS        = @WALL_FLAG@ @CXXFLAGS@ $(PICOPT)
 LDFLAGS         = @LDFLAGS@
-PICOPT		= @PICOPT@
 SHAREDLIB	= @SHAREDLIB@
 
 SDCC		= sdcc
@@ -54,45 +57,57 @@
 
 EXEEXT		= @EXEEXT@
 
-OBJECTS_SHARED	= glob.o sim51.o \
+OBJECTS_SHARED	= glob.o sim$(TN).o \
 		  inc.o jmp.o mov.o logic.o arith.o bit.o \
 		  timer0.o timer1.o timer2.o serial.o port.o interrupt.o \
 		  wdt.o pca.o mdu.o \
 		  uc51.o uc52.o uc51r.o uc89c51r.o uc251.o uc517.o \
 		  uc390.o uc390hw.o uc521.o uc88x.o uc320.o uc380.o
-OBJECTS_EXE	= s51.o 
+OBJECTS_EXE	= s$(TN).o 
 OBJECTS		= $(OBJECTS_SHARED) $(OBJECTS_EXE)
 
+# short/long exe and lib name
+SEN		= s$(TN)$(EXEEXT)
+LEN		= ucsim_$(TN)$(EXEEXT)
+SONAME		= libucsim_$(TN).so
+
 enable_dlso	= @enable_dlso@
 dlso_ok		= @dlso_ok@
 
 
 # Compiling entire program or any subproject
 # ------------------------------------------
-all: checkconf otherlibs s51.src
+all: checkconf otherlibs s$(TN).src
 
 
 # Compiling and installing everything and runing test
 # ---------------------------------------------------
-install: all installdirs
-	$(INSTALL) s51$(EXEEXT) $(DESTDIR)$(bindir)/`echo s51|sed '$(transform)'`$(EXEEXT)
-	$(STRIP) $(DESTDIR)$(bindir)/`echo s51|sed '$(transform)'`$(EXEEXT)
+install: all installdirs install_shared_lib
+	$(INSTALL) $(SEN) $(DESTDIR)$(bindir)/$(SEN)
+	$(STRIP) $(DESTDIR)$(bindir)/$(SEN)
+	$(INSTALL) $(LEN) $(DESTDIR)$(bindir)/$(LEN)
+	$(STRIP) $(DESTDIR)$(bindir)/$(LEN)
 
 
 # Deleting all the installed files
 # --------------------------------
 uninstall:
-	rm -f $(DESTDIR)$(bindir)/`echo s51|sed '$(transform)'`$(EXEEXT)
+	rm -f $(DESTDIR)$(bindir)/$(SEN)
+	rm -f $(DESTDIR)$(bindir)/$(LEN)
+	rm -f $(DESTDIR)$(libdir)/$(SONAME)
 
 
 # Performing self-test
 # --------------------
 check: test
 
-test: test_ser.ihx
+.PHONY:	test baseline
+test:
+	@$(MAKE) --no-print-directory -C test
+
+baseline:
+	@$(MAKE) --no-print-directory -C test baseline
 
-test_ser.ihx: test_ser.rel
-	$(SDCC) $(SDCFLAGS) $<
 
 # Performing installation test
 # ----------------------------
@@ -123,20 +138,27 @@
 # --------
 .SUFFIXES: .rel
 
-s51.src: s51$(EXEEXT) shared_lib
+s$(TN).src: $(SEN) $(LEN) shared_lib
 
-s51$(EXEEXT): $(OBJECTS) $(top_builddir)/libcmd.a $(top_builddir)/libguiucsim.a $(top_builddir)/libsim.a $(top_builddir)/libucsimutil.a
+$(SEN): $(OBJECTS) $(top_builddir)/libcmd.a $(top_builddir)/libguiucsim.a $(top_builddir)/libsim.a $(top_builddir)/libucsimutil.a
 	$(CXX) $(CXXFLAGS) $(LDFLAGS) $(OBJECTS) $(LIBS) -o $@
 
+$(LEN): s$(TN)$(EXEEXT)
+	cp $< $@
+
 ifeq ($(dlso_ok),yes)
-shared_lib: $(top_builddir)/s51.so
+shared_lib: $(top_builddir)/$(SONAME)
+install_shared_lib: shared_lib
+	test -d $(DESTDIR)$(libdir) || $(INSTALL) -d $(DESTDIR)$(libdir)
+	$(INSTALL) $(top_builddir)/$(SONAME) $(DESTDIR)$(libdir)/$(SONAME)
 else
 shared_lib:
-	@$(top_srcdir)/mkecho $(top_builddir) "No 51 shared lib made."
+	@$(top_srcdir)/mkecho $(top_builddir) "No $(TN) shared lib made."
 	@$(top_srcdir)/mkecho $(top_builddir) "(SHAREDLIB="$(SHAREDLIB)",dl_ok="$(dl_ok)",enable_dlso="$(enable_dlso)")"
+install_shared_lib:
 endif
 
-$(top_builddir)/s51.so: $(OBJECTS_SHARED)
+$(top_builddir)/$(SONAME): $(OBJECTS_SHARED)
 	$(CXX) -shared $(LDFLAGS) $(OBJECTS_SHARED) -o $@
 
 otherlibs: $(top_builddir)/libcmd.a $(top_builddir)/libguiucsim.a $(top_builddir)/libsim.a $(top_builddir)/libucsimutil.a
@@ -154,7 +176,7 @@
 	$(MAKE) -C $(top_builddir) -f main.mk
 
 .cc.o:
-	$(CXX) $(CXXFLAGS) $(PICOPT) $(CPPFLAGS) -c $< -o $@
+	$(CXX) $(CXXFLAGS) $(CPPFLAGS) -c $< -o $@
 
 .c.rel:
 	$(SDCC) $(SDCFLAGS) $(SDCPPFLAGS) -c $<
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/mdu.cc sdcc-4.2.0+dfsg/sim/ucsim/s51.src/mdu.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/mdu.cc	2017-02-24 11:48:49.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/mdu.cc	2021-04-25 20:38:36.000000000 +0000
@@ -25,6 +25,8 @@
 02111-1307, USA. */
 /*@1@*/
 
+#include 
+
 #include "uc51cl.h"
 
 #include "mducl.h"
@@ -329,18 +331,18 @@
 cl_mdu517::set_ovr(bool val)
 {
   if (val)
-    con->set_bit1(0x40);
+    con->set(con->get() | 0x40);
   else
-    con->set_bit0(0x40);
+    con->set(con->get() | 0x40);
 }
 
 void
 cl_mdu517::set_err(bool val)
 {
   if (val)
-    con->set_bit1(0x80);
+    con->set(con->get() | 0x80);
   else
-    con->set_bit0(0x80);
+    con->set(con->get() & ~0x80);
 }
 
 t_mem
@@ -392,8 +394,8 @@
   else if (sfr->is_owned(cell, &a))
     {
       a-= 0xb2;
-      if ((a < 0) ||
-	  (a > 5))
+      if (((a < 0) ||
+	   (a > 5)))
 	{
 	  if (con->get() & 0x20)
 	    val= regs[a]->get();
@@ -625,18 +627,18 @@
 cl_mdu88x::set_err(bool val)
 {
   if (val)
-    stat->set_bit1(0x02);
+    stat->set(stat->get() | 0x02);
   else
-    stat->set_bit0(0x02);
+    stat->set(stat->get() & ~0x02);
 }
 
 void
 cl_mdu88x::set_bsy(bool val)
 {
   if (val)
-    stat->set_bit1(0x04);
+    stat->set(stat->get() | 0x04);
   else
-    stat->set_bit0(0x04);
+    stat->set(stat->get() & ~0x04);
 }
 
 bool
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/mov.cc sdcc-4.2.0+dfsg/sim/ucsim/s51.src/mov.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/mov.cc	2017-02-24 11:48:49.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/mov.cc	2021-05-02 15:29:48.000000000 +0000
@@ -30,12 +30,12 @@
  *	get register in "mov @ri,address"
  */
  
-#include "ddconfig.h"
+//#include "ddconfig.h"
 
-#include 
+//#include 
 
 // sim
-#include "memcl.h"
+//#include "memcl.h"
 
 // local
 #include "uc51cl.h"
@@ -287,7 +287,7 @@
 
   cell= get_direct(fetch());
   sp_before= sfr->get(SP);
-  sp= /*sp_after= */sfr->wadd(SP, 1);
+  sp= /*sp_after= */sfr->write(SP, sfr->read(SP) + 1);
   stck= iram->get_cell(sp);
   stck->write(data= cell->read());
   class cl_stack_op *so=
@@ -385,7 +385,7 @@
   stck= iram->get_cell(/*sfr->get(SP)*/sp_before);
   /* Order of decrement and write changed to fix POP SP, reported by
      Alexis Pavlov  */
-  sp= sfr->wadd(SP, -1);
+  sp= sfr->write(SP, sfr->read(SP) - 1);
   cell->write(data= stck->read());
   tick(1);
   class cl_stack_op *so=
@@ -449,9 +449,10 @@
 cl_51core::instruction_e2/*inst_movx_a_Sri*/(t_mem/*uchar*/ code)
 {
   t_mem d;
-
+  int ah= high_movxri();
+  
   d= R[code & 0x01]->read();
-  acc->write(xram->read(sfr->read(P2)*256 + d));
+  acc->write(xram->read(ah*256 + d));
   tick(1);
   vc.rd++;//= 2;
   //vc.wr++;
@@ -476,7 +477,7 @@
     {
       //sim->app->get_commander()->
       //debug("Invalid Instruction : E5 E0  MOV A,ACC  at  %06x\n", PC);
-      inst_unknown();
+      inst_unknown(code);
     }
   else
     {
@@ -555,9 +556,11 @@
 {
   t_mem d, v;
   t_addr a;
+  int ah;
   
   d= R[code & 0x01]->read();
-  a= sfr->read(P2)*256 + d;
+  ah= high_movxri();
+  a= ah*256 + d;
   v= acc->read();
   xram->write(a, v);
   tick(1);
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/pca.cc sdcc-4.2.0+dfsg/sim/ucsim/s51.src/pca.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/pca.cc	2019-04-02 10:46:33.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/pca.cc	2022-01-26 16:35:40.000000000 +0000
@@ -25,7 +25,8 @@
 02111-1307, USA. */
 /*@1@*/
 
-#include 
+#include 
+//#include 
 
 // sim.src
 #include "itsrccl.h"
@@ -161,12 +162,12 @@
 	      {
 		if (cell == cell_ccapl[i])
 		  {
-		    cell_ccapm[i]->set_bit0(bmECOM);
+		    cell_ccapm[i]->set(cell_ccapm[i]->get() & ~bmECOM);
 		    ccapm[i]= cell_ccapm[i]->get();
 		  }
 		else if (cell == cell_ccaph[i])
 		  {
-		    cell_ccapm[i]->set_bit1(bmECOM);
+		    cell_ccapm[i]->set(cell_ccapm[i]->get() | bmECOM);
 		    ccapm[i]= cell_ccapm[i]->get();
 		  }
 	      }
@@ -229,16 +230,16 @@
 
   while (cycles--)
     {
-      if (cell_cl->add(1) == 0)
+      if (cell_cl->set(cell_cl->get() + 1) == 0)
 	{
 	  int i;
 	  for (i= 0; i < 5; i++)
 	    if (ccapm[i] & bmPWM)
 	      cell_ccapl[i]->set(cell_ccaph[i]->get());
-	  if (cell_ch->add(1) == 0)
+	  if (cell_ch->set(cell_ch->get() + 1) == 0)
 	    {
 	      // CH,CL overflow
-	      cell_ccon->set_bit1(bmCF);
+	      cell_ccon->set(cell_ccon->get() | bmCF);
 	      do_pca_module(0);
 	      do_pca_module(1);
 	      do_pca_module(2);
@@ -274,7 +275,7 @@
       // Capture
       cell_ccapl[nr]->set(cell_cl->get());
       cell_ccaph[nr]->set(cell_ch->get());
-      cell_ccon->set_bit1(bmCCF[nr]);
+      cell_ccon->set(cell_ccon->get() | bmCCF[nr]);
     }
 
   if (ccapm[nr] & bmECOM)
@@ -290,7 +291,7 @@
 	      reset();
 	      return;
 	    }
-	  cell_ccon->set_bit1(bmCCF[nr]);
+	  cell_ccon->set(cell_ccon->get() | bmCCF[nr]);
 	  if (ccapm[nr] & bmTOG)
 	    {
 	      // Toggle
@@ -300,13 +301,10 @@
       if (ccapm[nr] & bmPWM)
 	{
 	  // PWM
-	  /*if (cell_cl->get() == 0)
-	    cell_ccapl[nr]->set(cell_ccaph[nr]->get());*/
 	  if (cell_cl->get() < cell_ccapl[nr]->get())
-	    //sfr->set(P1, sfr->get(P1) & ~(bmCEX[nr]));
-	    sfr->set_bit1(P1, bmCEX[nr]);
+	    sfr->set(P1, sfr->get(P1) | bmCEX[nr]);
 	  else
-	    sfr->set_bit1(P1, bmCEX[nr]);
+	    sfr->set(P1, sfr->get(P1) | bmCEX[nr]);
 	}
     }
 }
@@ -325,7 +323,7 @@
   struct ev_port_changed *ep= (struct ev_port_changed *)params;
   uchar bmCEX[5]= {bmCEX0, bmCEX1, bmCEX2, bmCEX3, bmCEX4};
 
-  if (where->cathegory == HW_PORT &&
+  if (where->category == HW_PORT &&
       he == EV_PORT_CHANGED &&
       ep->id == 1)
     {
@@ -345,7 +343,7 @@
 	    cex_pos[i]= true;
 	}
     }
-  else if (where->cathegory == HW_TIMER &&
+  else if (where->category == HW_TIMER &&
 	   he == EV_OVERFLOW &&
 	   where->id == 0)
     {
@@ -358,7 +356,7 @@
 cl_pca::print_info(class cl_console_base *con)
 {
   con->dd_printf("%s[%d] FIXME\n", id_string, id);
-  print_cfg_info(con);
+  //print_cfg_info(con);
 }
 
 
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/pcacl.h sdcc-4.2.0+dfsg/sim/ucsim/s51.src/pcacl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/pcacl.h	2019-04-02 10:46:33.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/pcacl.h	2020-08-22 10:25:08.000000000 +0000
@@ -52,7 +52,7 @@
 public:
   cl_pca(class cl_uc *auc, int aid);
   virtual int init(void);
-  //virtual char *cfg_help(t_addr addr);
+  //virtual const char *cfg_help(t_addr addr);
   
   virtual void added_to_uc(void);
 
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/port.cc sdcc-4.2.0+dfsg/sim/ucsim/s51.src/port.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/port.cc	2019-04-02 10:46:33.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/port.cc	2021-04-01 17:52:48.000000000 +0000
@@ -25,6 +25,7 @@
 02111-1307, USA. */
 /*@1@*/
 
+#include 
 #include 
 
 // cmd
@@ -102,47 +103,34 @@
   prev= cell_p->get();
   cell_in= cfg->get_cell(port_pin);
   cfg->set(port_value, prev & cell_in->get());
-  
-  cl_var *v;
-  chars pn;
-  pn= cchars("port");
-  pn.append("%d_", id);
-  uc->vars->add(v= new cl_var(pn+chars("on"), cfg, port_on,
-			      cfg_help(port_on)));
-  v->init();
-  uc->vars->add(v= new cl_var(pn+chars("pin"), cfg, port_pin,
-			      cfg_help(port_pin)));
-  v->init();
-  uc->vars->add(v= new cl_var(pn+chars("pins"), cfg, port_pin,
-			      cfg_help(port_pin)));
-  v->init();
-  uc->vars->add(v= new cl_var(pn+chars("value"), cfg, port_value,
-			      cfg_help(port_value)));
-  v->init();
-  chars p= chars("pin");
-  p.append("%d", id);
-  uc->vars->add(v= new cl_var(p, cfg, port_pin,
-			      cfg_help(port_pin)));
-  v->init();
-  p= chars("pins");
-  p.append("%d", id);
-  uc->vars->add(v= new cl_var(p, cfg, port_pin,
-			      cfg_help(port_pin)));
-  v->init();
-  
+
+  chars pn= chars("", "port%d_", id);
+  uc->vars->add(pn+"on", cfg, port_on, cfg_help(port_on));
+  uc->vars->add(pn+"pin", cfg, port_pin, cfg_help(port_pin));
+  uc->vars->add(pn+"pins", cfg, port_pin, cfg_help(port_pin));
+  uc->vars->add(pn+"value", cfg, port_value, cfg_help(port_value));
+  uc->vars->add(pn+"odr", cfg, port_odr, cfg_help(port_odr));
+
+  pn= chars("", "pin%d", id);
+  uc->vars->add(pn, cfg, port_pin, cfg_help(port_pin));
+
+  pn= chars("", "pins%d", id);
+  uc->vars->add(pn, cfg, port_pin, cfg_help(port_pin));
+
   return(0);
 }
 
-char *
+const char *
 cl_port::cfg_help(t_addr addr)
 {
   switch (addr)
     {
-    case port_on: return (char*)"Turn/get on/off state (bool, RW)";
-    case port_pin: return (char*)"Outside value of port pins (int, RW)";
-    case port_value: return (char*)"Value of the port (int, RO)";
+    case port_on: return "Turn/get on/off state (bool, RW)";
+    case port_pin: return "Outside value of port pins (int, RW)";
+    case port_value: return "Value of the port (int, RO)";
+    case port_odr: return "Value of output register (int, RW)";
     }
-  return (char*)"Not used";
+  return "Not used";
 }
 
 t_mem
@@ -228,7 +216,13 @@
       break;
     case port_value:
       if (val)
-	*val= cell->get();//cell->set(*val);
+	//*val= cell->get();
+	cell->set(*val);
+      break;
+    case port_odr:
+      if (val)
+	cell_p->write(*val);
+      cell->set(cell_p->get());
       break;
     }
   return cell->get();
@@ -292,7 +286,7 @@
   con->print_bin(data, 8);
   con->dd_printf(" 0x%02x %3d %c (Value on the port pins)\n",
 		 data, data, isprint(data)?data:'.');
-  print_cfg_info(con);
+  //print_cfg_info(con);
 }
 
 
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/portcl.h sdcc-4.2.0+dfsg/sim/ucsim/s51.src/portcl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/portcl.h	2019-04-02 10:46:33.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/portcl.h	2021-10-29 17:39:15.000000000 +0000
@@ -41,6 +41,7 @@
   port_on		= 0, // RW
   port_pin		= 1, // RW
   port_value		= 2, // RO
+  port_odr		= 3,
 };
 
 class cl_port: public cl_hw
@@ -55,8 +56,8 @@
   cl_port(class cl_uc *auc, int aid);
   cl_port(class cl_uc *auc, int aid, t_addr the_addr);
   virtual int init(void);
-  virtual int cfg_size(void) { return 3; }
-  virtual char *cfg_help(t_addr addr);
+  virtual unsigned int cfg_size(void) { return 4; }
+  virtual const char *cfg_help(t_addr addr);
   
   virtual t_mem read(class cl_memory_cell *cell);
   virtual void write(class cl_memory_cell *cell, t_mem *val);
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/regs51.h sdcc-4.2.0+dfsg/sim/ucsim/s51.src/regs51.h
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/regs51.h	2018-01-25 13:48:09.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/regs51.h	2022-01-26 16:35:40.000000000 +0000
@@ -32,7 +32,7 @@
 /* Address of SFR registers */
 
 #define ACC	0xe0 /* Accumulator */
-#define B	0xf0 /* B register (scondary accumulator) */
+#define B	0xf0 /* B register (secondary accumulator) */
 #define PSW	0xd0 /* Program Status Word */
 #define SP	0x81 /* Stack Pointer */
 #define DPL	0x82 /* Data Pointer Low byte */
@@ -44,7 +44,7 @@
 #define P1	0x90 /* Port #1 */
 #define P2	0xa0 /* Port #2 */
 #define P3	0xb0 /* Port #3 */
-#define IP	0xb8 /* Intrrupt Priority */
+#define IP	0xb8 /* Interrupt Priority */
 #define IE	0xa8 /* Interrupt Enable */
 #define TMOD	0x89 /* Timer MODe */
 #define TCON	0x88 /* Timer CONtrol */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/s51.cc sdcc-4.2.0+dfsg/sim/ucsim/s51.src/s51.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/s51.cc	2017-01-06 07:36:33.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/s51.cc	2020-08-01 16:50:18.000000000 +0000
@@ -25,16 +25,17 @@
 02111-1307, USA. */
 /*@1@*/
 
-#include "ddconfig.h"
+//#include "ddconfig.h"
 
 // prj
 #include "globals.h"
 
 // sim.src
-#include "appcl.h"
+//#include "appcl.h"
 
 // local
 #include "sim51cl.h"
+#include "portcl.h"
 
 
 /*
@@ -49,6 +50,7 @@
 
   cpus= cpus_51;
   application= new cl_app();
+  application->set_name("s51");
   application->init(argc, argv);
   sim= new cl_sim51(application);
   if (sim->init())
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/serial.cc sdcc-4.2.0+dfsg/sim/ucsim/s51.src/serial.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/serial.cc	2019-04-02 10:46:33.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/serial.cc	2022-01-26 16:35:40.000000000 +0000
@@ -25,22 +25,22 @@
 02111-1307, USA. */
 /*@1@*/
 
-#include "ddconfig.h"
+//#include "ddconfig.h"
 
-#include 
-#include 
+//#include 
+//#include 
 #include 
-#include 
-#include 
-#include 
-#include 
+//#include 
+//#include 
+//#include 
+//#include 
 
 // prj
 #include "globals.h"
-#include "utils.h"
+//#include "utils.h"
 
 // cmd
-#include "cmdutil.h"
+//#include "cmdutil.h"
 
 // local
 #include "serialcl.h"
@@ -77,7 +77,7 @@
     }
 
   class cl_hw *t2= uc->get_hw(HW_TIMER, 2, 0);
-  if ((there_is_t2= t2 != 0))
+  if (((there_is_t2= t2) != 0))
     {
       t_mem d= sfr->get(T2CON);
       t2_baud= d & (bmRCLK | bmTCLK);
@@ -85,12 +85,10 @@
   else
     t2_baud= false;
   /*
-  cl_var *v;
   chars pn(id_string);
   pn.append("%d_", id);
-  uc->vars->add(v= new cl_var(pn+chars("on"), cfg, serconf_on));
-  uc->vars->add(v= new cl_var(pn+chars("check_often"), cfg, serconf_check_often));
-  v->init();
+  uc->vars->add(pn+chars("on"), cfg, serconf_on);
+  uc->vars->add(pn+chars("check_often"), cfg, serconf_check_often);
   */
   return(0);
 }
@@ -98,7 +96,7 @@
 void
 cl_serial::new_hw_added(class cl_hw *new_hw)
 {
-  if (new_hw->cathegory == HW_TIMER &&
+  if (new_hw->category == HW_TIMER &&
       new_hw->id == 2)
     {
       there_is_t2= true;
@@ -295,7 +293,8 @@
       (s_tr_bit >= _bits))
     {
       s_sending= false;
-      scon->set_bit1(bmTI);
+      //scon->set(scon->get() | bmTI);
+      scon_bits[1]->write(1);
       io->write((char*)(&s_out), 1);
       s_tr_bit-= _bits;
     }
@@ -341,7 +340,8 @@
 void
 cl_serial::received(int c)
 {
-  scon->set_bit1(bmRI);
+  //scon->set(scon->get() | bmRI);
+  scon_bits[0]->write(1);
   cfg_write(serconf_received, c);
 }
 
@@ -363,7 +363,7 @@
 void
 cl_serial::happen(class cl_hw *where, enum hw_event he, void *params)
 {
-  if (where->cathegory == HW_TIMER)
+  if (where->category == HW_TIMER)
     {
       if (where->id == 1)
 	{
@@ -425,18 +425,20 @@
   con->dd_printf(" %s", (sc&bmREN)?"ON":"OFF");
   con->dd_printf(" RB8=%c", (sc&bmRB8)?'1':'0');
   con->dd_printf(" irq=%c", (sc&bmRI)?'1':'0');
+  con->dd_printf(" buf=0x%02x", s_in);
   con->dd_printf("\n");
 
   con->dd_printf("Transmitter");
   con->dd_printf(" TB8=%c", (sc&bmTB8)?'1':'0');
   con->dd_printf(" irq=%c", (sc&bmTI)?'1':'0');
+  con->dd_printf(" buf=0x%02x", s_out);
   con->dd_printf("\n");
   /*con->dd_printf("s_rec_t1=%d s_rec_bit=%d s_rec_tick=%d\n",
 		 s_rec_t1, s_rec_bit, s_rec_tick);
   con->dd_printf("s_tr_t1=%d s_tr_bit=%d s_tr_tick=%d\n",
 		 s_tr_t1, s_tr_bit, s_tr_tick);
 		 con->dd_printf("divby=%d bits=%d\n", _divby, _bits);*/
-  print_cfg_info(con);
+  //print_cfg_info(con);
 }
 
 
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/serialcl.h sdcc-4.2.0+dfsg/sim/ucsim/s51.src/serialcl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/serialcl.h	2016-10-04 10:51:37.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/serialcl.h	2021-10-29 17:39:15.000000000 +0000
@@ -66,7 +66,7 @@
   cl_serial(class cl_uc *auc);
   virtual ~cl_serial(void);
   virtual int init(void);
-  virtual int cfg_size(void) { return 10; }
+  virtual unsigned int cfg_size(void) { return 10; }
 
   virtual void new_hw_added(class cl_hw *new_hw);
   virtual void added_to_uc(void);
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/sim51.cc sdcc-4.2.0+dfsg/sim/ucsim/s51.src/sim51.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/sim51.cc	2018-01-25 13:48:09.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/sim51.cc	2020-08-22 10:25:08.000000000 +0000
@@ -25,33 +25,34 @@
 02111-1307, USA. */
 /*@1@*/
 
-#include "ddconfig.h"
+//#include "ddconfig.h"
 
 #include 
-#include 
-#include 
-#include 
-#include "i_string.h"
+//#include 
+//#include 
+//#include 
+#include 
+//#include "i_string.h"
 
 #include "globals.h"
-#include "utils.h"
-#include "cmdutil.h"
-#include "charscl.h"
+//#include "utils.h"
+//#include "cmdutil.h"
+//#include "charscl.h"
 
 #include "sim51cl.h"
 //#include "cmd51cl.h"
-#include "uc51cl.h"
-#include "uc52cl.h"
-#include "uc521cl.h"
+//#include "uc51cl.h"
+//#include "uc52cl.h"
+//#include "uc521cl.h"
 #include "uc517cl.h"
-#include "uc51rcl.h"
-#include "uc89c51rcl.h"
+//#include "uc51rcl.h"
+//#include "uc89c51rcl.h"
 #include "uc251cl.h"
 #include "uc390cl.h"
 #include "uc88xcl.h"
 #include "uc320cl.h"
 #include "uc380cl.h"
-#include "glob.h"
+//#include "glob.h"
 
 
 cl_sim51::cl_sim51(class cl_app *the_app):
@@ -63,14 +64,14 @@
 cl_sim51::mk_controller(void)
 {
   int i;
-  char *typ= 0;
+  const char *typ= 0;
   class cl_optref type_option(this);
 
   type_option.init();
-  type_option.use(cchars("cpu_type"));
+  type_option.use("cpu_type");
   i= 0;
   if ((typ= type_option.get_value(typ)) == 0)
-    typ= cchars("C52");
+    typ= "C52";
   while ((cpus_51[i].type_str != NULL) &&
 	 (strcasecmp(typ, cpus_51[i].type_str) != 0))
     i++;
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/bander/baseline/51 sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/bander/baseline/51
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/bander/baseline/51	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/bander/baseline/51	2022-02-08 21:21:05.000000000 +0000
@@ -0,0 +1,145 @@
+uCsim, Copyright (C)  Daniel Drotos.
+uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+This is free software, and you are welcome to redistribute it
+under certain conditions; type `show c' for details.
+# Bander maps bits one at a time starting from iram_chip[0x20] into
+# the bits address space starting at 0x00
+info mem
+Memory chips:
+  0x000000-0x0000ff      256 variable_storage (32,%08x,0x%02lx)
+  0x000000-0x00ffff    65536 rom_chip (8,%02x,0x%04lx)
+  0x000000-0x0000ff      256 iram_chip (8,%02x,0x%02lx)
+  0x000000-0x00ffff    65536 xram_chip (8,%02x,0x%04lx)
+  0x000000-0x00007f      128 sfr_chip (8,%02x,0x%02lx)
+Address spaces:
+  0x000000-0x0000ff      256 variables (32,%08x,0x%02lx)
+  0x000000-0x00ffff    65536 rom (8,%02x,0x%04lx)
+  0x000000-0x00007f      128 iram (8,%02x,0x%02lx)
+  0x000080-0x0000ff      128 sfr (8,%02x,0x%02lx)
+  0x000000-0x00ffff    65536 xram (8,%02x,0x%04lx)
+  0x000000-0x000007        8 regs (8,%02x,0x%01lx)
+  0x000000-0x0000ff      256 bits (1,%01x,0x%02lx)
+  0x000000-0x000001        2 dptr (8,%02x,0x%01lx)
+Address decoders:
+  variables 0x00 0xff -> variable_storage 0x00 activated
+  rom 0x0000 0xffff -> rom_chip 0x0000 activated
+  iram 0x00 0x7f -> iram_chip 0x00 activated
+  sfr 0x80 0xff -> sfr_chip 0x00 activated
+  xram 0x0000 0xffff -> xram_chip 0x0000 activated
+  regs 0x0 0x7 -> banked
+    bank selector: sfr[0xd0] mask=0x18 banks=4 act=0
+    banks:
+      *  0. iram_chip 0x00
+         1. iram_chip 0x08
+         2. iram_chip 0x10
+         3. iram_chip 0x18
+  bits 0x00 0x7f -> bander(8/1) iram_chip 0x20 activated
+  bits 0x80 0xff -> bander(8/8) sfr_chip 0x00 activated
+  dptr 0x0 0x1 -> sfr_chip 0x02 activated
+
+# Set iram_chip[0x20] and iram_chip[0x21] to 0xff
+set mem iram_chip 0x20 0xff 0xff
+0x20                      ff ff ..
+
+# First 16 addresses of bits should all read as 0x01
+dump bits 0 15
+0x00                      1 1 1 1 1 1 1 1 ........
+0x08                      1 1 1 1 1 1 1 1 ........
+
+# Set iram_chip[0x20] and iram_chip[0x21] to 0x00
+set mem iram_chip 0x20 0x00 0x00
+0x20                      00 00 ..
+
+# First 16 addresses of bits should all read as 0x00
+dump bits 0 15
+0x00                      0 0 0 0 0 0 0 0 ........
+0x08                      0 0 0 0 0 0 0 0 ........
+
+# Now set bits in turn starting with the lowest and the
+# corresponding location in bits should change to 0x01
+set mem iram_chip[0x20].0 1
+0x20.0                              0b-------1 0x01 '.'   1
+dump bits 0 15
+0x00                      1 0 0 0 0 0 0 0 ........
+0x08                      0 0 0 0 0 0 0 0 ........
+set mem iram_chip[0x20].1 1
+0x20.1                              0b------1- 0x01 '.'   1
+dump bits 0 15
+0x00                      1 1 0 0 0 0 0 0 ........
+0x08                      0 0 0 0 0 0 0 0 ........
+set mem iram_chip[0x20].2 1
+0x20.2                              0b-----1-- 0x01 '.'   1
+dump bits 0 15
+0x00                      1 1 1 0 0 0 0 0 ........
+0x08                      0 0 0 0 0 0 0 0 ........
+set mem iram_chip[0x20].3 1
+0x20.3                              0b----1--- 0x01 '.'   1
+dump bits 0 15
+0x00                      1 1 1 1 0 0 0 0 ........
+0x08                      0 0 0 0 0 0 0 0 ........
+set mem iram_chip[0x20].4 1
+0x20.4                              0b---1---- 0x01 '.'   1
+dump bits 0 15
+0x00                      1 1 1 1 1 0 0 0 ........
+0x08                      0 0 0 0 0 0 0 0 ........
+set mem iram_chip[0x20].5 1
+0x20.5                              0b--1----- 0x01 '.'   1
+dump bits 0 15
+0x00                      1 1 1 1 1 1 0 0 ........
+0x08                      0 0 0 0 0 0 0 0 ........
+set mem iram_chip[0x20].6 1
+0x20.6                              0b-1------ 0x01 '.'   1
+dump bits 0 15
+0x00                      1 1 1 1 1 1 1 0 ........
+0x08                      0 0 0 0 0 0 0 0 ........
+set mem iram_chip[0x20].7 1
+0x20.7                              0b1------- 0x01 '.'   1
+dump bits 0 15
+0x00                      1 1 1 1 1 1 1 1 ........
+0x08                      0 0 0 0 0 0 0 0 ........
+set mem iram_chip[0x21].0 1
+0x21.0                              0b-------1 0x01 '.'   1
+dump bits 0 15
+0x00                      1 1 1 1 1 1 1 1 ........
+0x08                      1 0 0 0 0 0 0 0 ........
+set mem iram_chip[0x21].1 1
+0x21.1                              0b------1- 0x01 '.'   1
+dump bits 0 15
+0x00                      1 1 1 1 1 1 1 1 ........
+0x08                      1 1 0 0 0 0 0 0 ........
+set mem iram_chip[0x21].2 1
+0x21.2                              0b-----1-- 0x01 '.'   1
+dump bits 0 15
+0x00                      1 1 1 1 1 1 1 1 ........
+0x08                      1 1 1 0 0 0 0 0 ........
+set mem iram_chip[0x21].3 1
+0x21.3                              0b----1--- 0x01 '.'   1
+dump bits 0 15
+0x00                      1 1 1 1 1 1 1 1 ........
+0x08                      1 1 1 1 0 0 0 0 ........
+set mem iram_chip[0x21].4 1
+0x21.4                              0b---1---- 0x01 '.'   1
+dump bits 0 15
+0x00                      1 1 1 1 1 1 1 1 ........
+0x08                      1 1 1 1 1 0 0 0 ........
+set mem iram_chip[0x21].5 1
+0x21.5                              0b--1----- 0x01 '.'   1
+dump bits 0 15
+0x00                      1 1 1 1 1 1 1 1 ........
+0x08                      1 1 1 1 1 1 0 0 ........
+set mem iram_chip[0x21].6 1
+0x21.6                              0b-1------ 0x01 '.'   1
+dump bits 0 15
+0x00                      1 1 1 1 1 1 1 1 ........
+0x08                      1 1 1 1 1 1 1 0 ........
+set mem iram_chip[0x21].7 1
+0x21.7                              0b1------- 0x01 '.'   1
+dump bits 0 15
+0x00                      1 1 1 1 1 1 1 1 ........
+0x08                      1 1 1 1 1 1 1 1 ........
+
+# If we set bits[0x08] to 0 that should clear bit 0 of iram_chip[0x21]
+set mem bits[0x08] 0
+0x08                      0 .
+dump iram_chip 0x20 0x21
+0x20                      ff fe ..
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/bander/Makefile sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/bander/Makefile
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/bander/Makefile	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/bander/Makefile	2021-06-13 15:54:41.000000000 +0000
@@ -0,0 +1,8 @@
+OUTPUTS = 51
+
+
+$(OUTPUTS): %:	test-%.cmd
+	$(call run-sim, -t $@)
+
+
+include test-lib.mk
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/bander/test-51.cmd sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/bander/test-51.cmd
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/bander/test-51.cmd	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/bander/test-51.cmd	2021-06-13 15:54:41.000000000 +0000
@@ -0,0 +1,54 @@
+# Bander maps bits one at a time starting from iram_chip[0x20] into
+# the bits address space starting at 0x00
+info mem
+
+# Set iram_chip[0x20] and iram_chip[0x21] to 0xff
+set mem iram_chip 0x20 0xff 0xff
+
+# First 16 addresses of bits should all read as 0x01
+dump bits 0 15
+
+# Set iram_chip[0x20] and iram_chip[0x21] to 0x00
+set mem iram_chip 0x20 0x00 0x00
+
+# First 16 addresses of bits should all read as 0x00
+dump bits 0 15
+
+# Now set bits in turn starting with the lowest and the
+# corresponding location in bits should change to 0x01
+set mem iram_chip[0x20].0 1
+dump bits 0 15
+set mem iram_chip[0x20].1 1
+dump bits 0 15
+set mem iram_chip[0x20].2 1
+dump bits 0 15
+set mem iram_chip[0x20].3 1
+dump bits 0 15
+set mem iram_chip[0x20].4 1
+dump bits 0 15
+set mem iram_chip[0x20].5 1
+dump bits 0 15
+set mem iram_chip[0x20].6 1
+dump bits 0 15
+set mem iram_chip[0x20].7 1
+dump bits 0 15
+set mem iram_chip[0x21].0 1
+dump bits 0 15
+set mem iram_chip[0x21].1 1
+dump bits 0 15
+set mem iram_chip[0x21].2 1
+dump bits 0 15
+set mem iram_chip[0x21].3 1
+dump bits 0 15
+set mem iram_chip[0x21].4 1
+dump bits 0 15
+set mem iram_chip[0x21].5 1
+dump bits 0 15
+set mem iram_chip[0x21].6 1
+dump bits 0 15
+set mem iram_chip[0x21].7 1
+dump bits 0 15
+
+# If we set bits[0x08] to 0 that should clear bit 0 of iram_chip[0x21]
+set mem bits[0x08] 0
+dump iram_chip 0x20 0x21
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/banker/baseline/517 sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/banker/baseline/517
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/banker/baseline/517	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/banker/baseline/517	2022-02-08 21:21:05.000000000 +0000
@@ -0,0 +1,143 @@
+uCsim, Copyright (C)  Daniel Drotos.
+uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+This is free software, and you are welcome to redistribute it
+under certain conditions; type `show c' for details.
+# Banker tests for s51 -t 517
+
+# Registers are banked under control of sfr[0xd0][4:3] as standard.
+# See test-C51.cmd for tests.
+
+# There are 8 dptr banks under control of sfr[0x92][2:0] each consisting
+# of two successive bytes from dptr_chip. Each pair of bytes is mapped
+# to both sfr[0x82]..sfr[0x83] and dptr[0x00]..dptr[0x01].
+info mem
+Memory chips:
+  0x000000-0x0000ff      256 variable_storage (32,%08x,0x%02lx)
+  0x000000-0x00ffff    65536 rom_chip (8,%02x,0x%04lx)
+  0x000000-0x0000ff      256 iram_chip (8,%02x,0x%02lx)
+  0x000000-0x00ffff    65536 xram_chip (8,%02x,0x%04lx)
+  0x000000-0x00007f      128 sfr_chip (8,%02x,0x%02lx)
+  0x000000-0x000017       24 dptr_chip (8,%02x,0x%02lx)
+Address spaces:
+  0x000000-0x0000ff      256 variables (32,%08x,0x%02lx)
+  0x000000-0x00ffff    65536 rom (8,%02x,0x%04lx)
+  0x000000-0x0000ff      256 iram (8,%02x,0x%02lx)
+  0x000080-0x0000ff      128 sfr (8,%02x,0x%02lx)
+  0x000000-0x00ffff    65536 xram (8,%02x,0x%04lx)
+  0x000000-0x000007        8 regs (8,%02x,0x%01lx)
+  0x000000-0x0000ff      256 bits (1,%01x,0x%02lx)
+  0x000000-0x000001        2 dptr (8,%02x,0x%01lx)
+Address decoders:
+  variables 0x00 0xff -> variable_storage 0x00 activated
+  rom 0x0000 0xffff -> rom_chip 0x0000 activated
+  iram 0x00 0xff -> iram_chip 0x00 activated
+  sfr 0x80 0xff -> sfr_chip 0x00 activated
+  sfr 0x82 0x83 -> banked
+    bank selector: sfr[0x92] mask=0x7 banks=8 act=0
+    banks:
+      *  0. dptr_chip 0x00
+         1. dptr_chip 0x02
+         2. dptr_chip 0x04
+         3. dptr_chip 0x06
+         4. dptr_chip 0x08
+         5. dptr_chip 0x0a
+         6. dptr_chip 0x0c
+         7. dptr_chip 0x0e
+  xram 0x0000 0xffff -> xram_chip 0x0000 activated
+  regs 0x0 0x7 -> banked
+    bank selector: sfr[0xd0] mask=0x18 banks=4 act=0
+    banks:
+      *  0. iram_chip 0x00
+         1. iram_chip 0x08
+         2. iram_chip 0x10
+         3. iram_chip 0x18
+  bits 0x00 0x7f -> bander(8/1) iram_chip 0x20 activated
+  bits 0x80 0xff -> bander(8/8) sfr_chip 0x00 activated
+  dptr 0x0 0x1 -> banked
+    bank selector: sfr[0x92] mask=0x7 banks=8 act=0
+    banks:
+      *  0. dptr_chip 0x00
+         1. dptr_chip 0x02
+         2. dptr_chip 0x04
+         3. dptr_chip 0x06
+         4. dptr_chip 0x08
+         5. dptr_chip 0x0a
+         6. dptr_chip 0x0c
+         7. dptr_chip 0x0e
+
+# Label and fill
+var bank sfr[0x92][2:0]
+var sfr_curr sfr[0x82]
+var dptr_curr dptr[0x00]
+var dptr0 dptr_chip[0x00]
+dptr_chip is not address space
+var dptr1 dptr_chip[0x02]
+dptr_chip is not address space
+var dptr2 dptr_chip[0x04]
+dptr_chip is not address space
+var dptr3 dptr_chip[0x06]
+dptr_chip is not address space
+var dptr4 dptr_chip[0x08]
+dptr_chip is not address space
+var dptr5 dptr_chip[0x0a]
+dptr_chip is not address space
+var dptr6 dptr_chip[0x0c]
+dptr_chip is not address space
+var dptr7 dptr_chip[0x0e]
+dptr_chip is not address space
+set mem dptr_chip 0x00 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07
+0x00                      00 01 02 03 04 05 06 07 ........
+set mem dptr_chip 0x08 0x08 0x09 0x0a 0x0b 0x0c 0x0d 0x0e 0x0f
+0x08                      08 09 0a 0b 0c 0d 0e 0f ........
+
+# Bank 0 should be current
+dump bank
+0x92[2:0] bank:                     0b-----000 0x00 '.'   0
+
+# Contents should be 0x00 0x01
+dump sfr 0x82 0x83
+0x82 sfr_curr:            00 01 ..
+#dump dptr 0x00 0x01
+
+# Check all the other banks
+set mem bank 1
+0x92[2:0] bank:                     0b-----001 0x01 '.'   1
+dump sfr 0x82 0x83
+0x82 sfr_curr:            02 03 ..
+#dump dptr 0x00 0x01
+
+set mem bank 2
+0x92[2:0] bank:                     0b-----010 0x02 '.'   2
+dump sfr 0x82 0x83
+0x82 sfr_curr:            04 05 ..
+#dump dptr 0x00 0x01
+
+set mem bank 3
+0x92[2:0] bank:                     0b-----011 0x03 '.'   3
+dump sfr 0x82 0x83
+0x82 sfr_curr:            06 07 ..
+#dump dptr 0x00 0x01
+
+set mem bank 4
+0x92[2:0] bank:                     0b-----100 0x04 '.'   4
+dump sfr 0x82 0x83
+0x82 sfr_curr:            08 09 ..
+#dump dptr 0x00 0x01
+
+set mem bank 5
+0x92[2:0] bank:                     0b-----101 0x05 '.'   5
+dump sfr 0x82 0x83
+0x82 sfr_curr:            0a 0b ..
+#dump dptr 0x00 0x01
+
+set mem bank 6
+0x92[2:0] bank:                     0b-----110 0x06 '.'   6
+dump sfr 0x82 0x83
+0x82 sfr_curr:            0c 0d ..
+#dump dptr 0x00 0x01
+
+set mem bank 7
+0x92[2:0] bank:                     0b-----111 0x07 '.'   7
+dump sfr 0x82 0x83
+0x82 sfr_curr:            0e 0f ..
+#dump dptr 0x00 0x01
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/banker/baseline/C51 sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/banker/baseline/C51
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/banker/baseline/C51	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/banker/baseline/C51	2022-02-08 21:21:05.000000000 +0000
@@ -0,0 +1,237 @@
+uCsim, Copyright (C)  Daniel Drotos.
+uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+This is free software, and you are welcome to redistribute it
+under certain conditions; type `show c' for details.
+# There are four banks of registers available. Which bank is
+# currently in use is selected via two bits in sfr[0xd0]
+info mem
+Memory chips:
+  0x000000-0x0000ff      256 variable_storage (32,%08x,0x%02lx)
+  0x000000-0x00ffff    65536 rom_chip (8,%02x,0x%04lx)
+  0x000000-0x0000ff      256 iram_chip (8,%02x,0x%02lx)
+  0x000000-0x00ffff    65536 xram_chip (8,%02x,0x%04lx)
+  0x000000-0x00007f      128 sfr_chip (8,%02x,0x%02lx)
+Address spaces:
+  0x000000-0x0000ff      256 variables (32,%08x,0x%02lx)
+  0x000000-0x00ffff    65536 rom (8,%02x,0x%04lx)
+  0x000000-0x00007f      128 iram (8,%02x,0x%02lx)
+  0x000080-0x0000ff      128 sfr (8,%02x,0x%02lx)
+  0x000000-0x00ffff    65536 xram (8,%02x,0x%04lx)
+  0x000000-0x000007        8 regs (8,%02x,0x%01lx)
+  0x000000-0x0000ff      256 bits (1,%01x,0x%02lx)
+  0x000000-0x000001        2 dptr (8,%02x,0x%01lx)
+Address decoders:
+  variables 0x00 0xff -> variable_storage 0x00 activated
+  rom 0x0000 0xffff -> rom_chip 0x0000 activated
+  iram 0x00 0x7f -> iram_chip 0x00 activated
+  sfr 0x80 0xff -> sfr_chip 0x00 activated
+  xram 0x0000 0xffff -> xram_chip 0x0000 activated
+  regs 0x0 0x7 -> banked
+    bank selector: sfr[0xd0] mask=0x18 banks=4 act=0
+    banks:
+      *  0. iram_chip 0x00
+         1. iram_chip 0x08
+         2. iram_chip 0x10
+         3. iram_chip 0x18
+  bits 0x00 0x7f -> bander(8/1) iram_chip 0x20 activated
+  bits 0x80 0xff -> bander(8/8) sfr_chip 0x00 activated
+  dptr 0x0 0x1 -> sfr_chip 0x02 activated
+
+# The bank switcher should have an operator on sfr[0xd0]
+memory cell sfr[0xd0]
+sfr[0xd0] sfr_0000d0
+cell width=8 mask=ff flags=0
+  decoded to sfr_chip[80]
+Operators:
+
+# Define the control bits
+var bank sfr[0xd0][4:3]
+
+# Now the current bank is 0 and we have a set of registers
+#dump regs 0 7
+
+# Note that the R vars are defined on the "regs" space
+info var R3
+R3 regs[0x3][7:0] = 0b10110010,178U,178
+
+# Let's label the banks in the underlying chip
+var bank0 iram_chip[0x00]
+iram_chip is not address space
+var bank1 iram_chip[0x08]
+iram_chip is not address space
+var bank2 iram_chip[0x10]
+iram_chip is not address space
+var bank3 iram_chip[0x18]
+iram_chip is not address space
+
+# and prime the banks with recognisable data
+set mem iram_chip 0x00 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07
+0x00                      00 01 02 03 04 05 06 07 ........
+set mem iram_chip 0x08 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17
+0x08                      10 11 12 13 14 15 16 17 ........
+set mem iram_chip 0x10 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27
+0x10                      20 21 22 23 24 25 26 27  !"#$%&'
+set mem iram_chip 0x18 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37
+0x18                      30 31 32 33 34 35 36 37 01234567
+
+# Now when we dump the regs we can see the label on the
+# current bank of the underlying chip as well
+#dump regs 0 7
+
+# Change to bank 1
+set mem bank 1
+0xd0[4:3] bank:                     0b---01--- 0x01 '.'   1
+
+# and check the state
+info mem
+Memory chips:
+  0x000000-0x0000ff      256 variable_storage (32,%08x,0x%02lx)
+  0x000000-0x00ffff    65536 rom_chip (8,%02x,0x%04lx)
+  0x000000-0x0000ff      256 iram_chip (8,%02x,0x%02lx)
+  0x000000-0x00ffff    65536 xram_chip (8,%02x,0x%04lx)
+  0x000000-0x00007f      128 sfr_chip (8,%02x,0x%02lx)
+Address spaces:
+  0x000000-0x0000ff      256 variables (32,%08x,0x%02lx)
+  0x000000-0x00ffff    65536 rom (8,%02x,0x%04lx)
+  0x000000-0x00007f      128 iram (8,%02x,0x%02lx)
+  0x000080-0x0000ff      128 sfr (8,%02x,0x%02lx)
+  0x000000-0x00ffff    65536 xram (8,%02x,0x%04lx)
+  0x000000-0x000007        8 regs (8,%02x,0x%01lx)
+  0x000000-0x0000ff      256 bits (1,%01x,0x%02lx)
+  0x000000-0x000001        2 dptr (8,%02x,0x%01lx)
+Address decoders:
+  variables 0x00 0xff -> variable_storage 0x00 activated
+  rom 0x0000 0xffff -> rom_chip 0x0000 activated
+  iram 0x00 0x7f -> iram_chip 0x00 activated
+  sfr 0x80 0xff -> sfr_chip 0x00 activated
+  xram 0x0000 0xffff -> xram_chip 0x0000 activated
+  regs 0x0 0x7 -> banked
+    bank selector: sfr[0xd0] mask=0x18 banks=4 act=1
+    banks:
+         0. iram_chip 0x00
+      *  1. iram_chip 0x08
+         2. iram_chip 0x10
+         3. iram_chip 0x18
+  bits 0x00 0x7f -> bander(8/1) iram_chip 0x20 activated
+  bits 0x80 0xff -> bander(8/8) sfr_chip 0x00 activated
+  dptr 0x0 0x1 -> sfr_chip 0x02 activated
+
+# If we dump regs again we still see the R labels because
+# they are on the address space however "bank0" has changed
+# to "bank1" because they are on the underlying chip.
+#dump regs 0 7
+
+# Repeat for banks 2 and 3
+set mem bank 2
+0xd0[4:3] bank:                     0b---10--- 0x02 '.'   2
+info mem
+Memory chips:
+  0x000000-0x0000ff      256 variable_storage (32,%08x,0x%02lx)
+  0x000000-0x00ffff    65536 rom_chip (8,%02x,0x%04lx)
+  0x000000-0x0000ff      256 iram_chip (8,%02x,0x%02lx)
+  0x000000-0x00ffff    65536 xram_chip (8,%02x,0x%04lx)
+  0x000000-0x00007f      128 sfr_chip (8,%02x,0x%02lx)
+Address spaces:
+  0x000000-0x0000ff      256 variables (32,%08x,0x%02lx)
+  0x000000-0x00ffff    65536 rom (8,%02x,0x%04lx)
+  0x000000-0x00007f      128 iram (8,%02x,0x%02lx)
+  0x000080-0x0000ff      128 sfr (8,%02x,0x%02lx)
+  0x000000-0x00ffff    65536 xram (8,%02x,0x%04lx)
+  0x000000-0x000007        8 regs (8,%02x,0x%01lx)
+  0x000000-0x0000ff      256 bits (1,%01x,0x%02lx)
+  0x000000-0x000001        2 dptr (8,%02x,0x%01lx)
+Address decoders:
+  variables 0x00 0xff -> variable_storage 0x00 activated
+  rom 0x0000 0xffff -> rom_chip 0x0000 activated
+  iram 0x00 0x7f -> iram_chip 0x00 activated
+  sfr 0x80 0xff -> sfr_chip 0x00 activated
+  xram 0x0000 0xffff -> xram_chip 0x0000 activated
+  regs 0x0 0x7 -> banked
+    bank selector: sfr[0xd0] mask=0x18 banks=4 act=2
+    banks:
+         0. iram_chip 0x00
+         1. iram_chip 0x08
+      *  2. iram_chip 0x10
+         3. iram_chip 0x18
+  bits 0x00 0x7f -> bander(8/1) iram_chip 0x20 activated
+  bits 0x80 0xff -> bander(8/8) sfr_chip 0x00 activated
+  dptr 0x0 0x1 -> sfr_chip 0x02 activated
+#dump regs 0 7
+set mem bank 3
+0xd0[4:3] bank:                     0b---11--- 0x03 '.'   3
+info mem
+Memory chips:
+  0x000000-0x0000ff      256 variable_storage (32,%08x,0x%02lx)
+  0x000000-0x00ffff    65536 rom_chip (8,%02x,0x%04lx)
+  0x000000-0x0000ff      256 iram_chip (8,%02x,0x%02lx)
+  0x000000-0x00ffff    65536 xram_chip (8,%02x,0x%04lx)
+  0x000000-0x00007f      128 sfr_chip (8,%02x,0x%02lx)
+Address spaces:
+  0x000000-0x0000ff      256 variables (32,%08x,0x%02lx)
+  0x000000-0x00ffff    65536 rom (8,%02x,0x%04lx)
+  0x000000-0x00007f      128 iram (8,%02x,0x%02lx)
+  0x000080-0x0000ff      128 sfr (8,%02x,0x%02lx)
+  0x000000-0x00ffff    65536 xram (8,%02x,0x%04lx)
+  0x000000-0x000007        8 regs (8,%02x,0x%01lx)
+  0x000000-0x0000ff      256 bits (1,%01x,0x%02lx)
+  0x000000-0x000001        2 dptr (8,%02x,0x%01lx)
+Address decoders:
+  variables 0x00 0xff -> variable_storage 0x00 activated
+  rom 0x0000 0xffff -> rom_chip 0x0000 activated
+  iram 0x00 0x7f -> iram_chip 0x00 activated
+  sfr 0x80 0xff -> sfr_chip 0x00 activated
+  xram 0x0000 0xffff -> xram_chip 0x0000 activated
+  regs 0x0 0x7 -> banked
+    bank selector: sfr[0xd0] mask=0x18 banks=4 act=3
+    banks:
+         0. iram_chip 0x00
+         1. iram_chip 0x08
+         2. iram_chip 0x10
+      *  3. iram_chip 0x18
+  bits 0x00 0x7f -> bander(8/1) iram_chip 0x20 activated
+  bits 0x80 0xff -> bander(8/8) sfr_chip 0x00 activated
+  dptr 0x0 0x1 -> sfr_chip 0x02 activated
+#dump regs 0 7
+
+# And finally check that the registers follow the bank switching correctly
+set mem bank 0
+0xd0[4:3] bank:                     0b---00--- 0x00 '.'   0
+info reg
+     R0 R1 R2 R3 R4 R5 R6 R7
+     00 01 02 03 04 05 06 07
+@R0 00 .  ACC= 0x00   0 .  B= 0x00
+@R1 01 .  PSW= 0x00 CY=0 AC=0 OV=0 P=0
+SP 0x07 -> 07 06 05 04 03 02 01 00
+   DPTR= 0x0000 @DPTR= 0x95 149 .
+0x0000  ? ff       MOV    R7,A[0K
+set mem bank 1
+0xd0[4:3] bank:                     0b---01--- 0x01 '.'   1
+info reg
+     R0 R1 R2 R3 R4 R5 R6 R7
+     10 11 12 13 14 15 16 17
+@R0 20    ACC= 0x00   0 .  B= 0x00
+@R1 21 !  PSW= 0x08 CY=0 AC=0 OV=0 P=0
+SP 0x07 -> 07 06 05 04 03 02 01 00
+   DPTR= 0x0000 @DPTR= 0x95 149 .
+0x0000  ? ff       MOV    R7,A[0K
+set mem bank 2
+0xd0[4:3] bank:                     0b---10--- 0x02 '.'   2
+info reg
+     R0 R1 R2 R3 R4 R5 R6 R7
+     20 21 22 23 24 25 26 27
+@R0 a3 .  ACC= 0x00   0 .  B= 0x00
+@R1 84 .  PSW= 0x10 CY=0 AC=0 OV=0 P=0
+SP 0x07 -> 07 06 05 04 03 02 01 00
+   DPTR= 0x0000 @DPTR= 0x95 149 .
+0x0000  ? ff       MOV    R7,A[0K
+set mem bank 3
+0xd0[4:3] bank:                     0b---11--- 0x03 '.'   3
+info reg
+     R0 R1 R2 R3 R4 R5 R6 R7
+     30 31 32 33 34 35 36 37
+@R0 20    ACC= 0x00   0 .  B= 0x00
+@R1 23 #  PSW= 0x18 CY=0 AC=0 OV=0 P=0
+SP 0x07 -> 07 06 05 04 03 02 01 00
+   DPTR= 0x0000 @DPTR= 0x95 149 .
+0x0000  ? ff       MOV    R7,A[0K
+  00. bank_switcher
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/banker/Makefile sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/banker/Makefile
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/banker/Makefile	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/banker/Makefile	2021-06-13 15:54:41.000000000 +0000
@@ -0,0 +1,8 @@
+OUTPUTS = C51 517
+
+
+$(OUTPUTS): %:	test-%.cmd
+	$(call run-sim, -t $@)
+
+
+include test-lib.mk
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/banker/test-517.cmd sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/banker/test-517.cmd
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/banker/test-517.cmd	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/banker/test-517.cmd	2021-11-24 08:18:17.000000000 +0000
@@ -0,0 +1,60 @@
+# Banker tests for s51 -t 517
+
+# Registers are banked under control of sfr[0xd0][4:3] as standard.
+# See test-C51.cmd for tests.
+
+# There are 8 dptr banks under control of sfr[0x92][2:0] each consisting
+# of two successive bytes from dptr_chip. Each pair of bytes is mapped
+# to both sfr[0x82]..sfr[0x83] and dptr[0x00]..dptr[0x01].
+info mem
+
+# Label and fill
+var bank sfr[0x92][2:0]
+var sfr_curr sfr[0x82]
+var dptr_curr dptr[0x00]
+var dptr0 dptr_chip[0x00]
+var dptr1 dptr_chip[0x02]
+var dptr2 dptr_chip[0x04]
+var dptr3 dptr_chip[0x06]
+var dptr4 dptr_chip[0x08]
+var dptr5 dptr_chip[0x0a]
+var dptr6 dptr_chip[0x0c]
+var dptr7 dptr_chip[0x0e]
+set mem dptr_chip 0x00 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07
+set mem dptr_chip 0x08 0x08 0x09 0x0a 0x0b 0x0c 0x0d 0x0e 0x0f
+
+# Bank 0 should be current
+dump bank
+
+# Contents should be 0x00 0x01
+dump sfr 0x82 0x83
+#dump dptr 0x00 0x01
+
+# Check all the other banks
+set mem bank 1
+dump sfr 0x82 0x83
+#dump dptr 0x00 0x01
+
+set mem bank 2
+dump sfr 0x82 0x83
+#dump dptr 0x00 0x01
+
+set mem bank 3
+dump sfr 0x82 0x83
+#dump dptr 0x00 0x01
+
+set mem bank 4
+dump sfr 0x82 0x83
+#dump dptr 0x00 0x01
+
+set mem bank 5
+dump sfr 0x82 0x83
+#dump dptr 0x00 0x01
+
+set mem bank 6
+dump sfr 0x82 0x83
+#dump dptr 0x00 0x01
+
+set mem bank 7
+dump sfr 0x82 0x83
+#dump dptr 0x00 0x01
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/banker/test-C51.cmd sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/banker/test-C51.cmd
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/banker/test-C51.cmd	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/banker/test-C51.cmd	2021-11-24 08:18:17.000000000 +0000
@@ -0,0 +1,60 @@
+# There are four banks of registers available. Which bank is
+# currently in use is selected via two bits in sfr[0xd0]
+info mem
+
+# The bank switcher should have an operator on sfr[0xd0]
+memory cell sfr[0xd0]
+
+# Define the control bits
+var bank sfr[0xd0][4:3]
+
+# Now the current bank is 0 and we have a set of registers
+#dump regs 0 7
+
+# Note that the R vars are defined on the "regs" space
+info var R3
+
+# Let's label the banks in the underlying chip
+var bank0 iram_chip[0x00]
+var bank1 iram_chip[0x08]
+var bank2 iram_chip[0x10]
+var bank3 iram_chip[0x18]
+
+# and prime the banks with recognisable data
+set mem iram_chip 0x00 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07
+set mem iram_chip 0x08 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17
+set mem iram_chip 0x10 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27
+set mem iram_chip 0x18 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37
+
+# Now when we dump the regs we can see the label on the
+# current bank of the underlying chip as well
+#dump regs 0 7
+
+# Change to bank 1
+set mem bank 1
+
+# and check the state
+info mem
+
+# If we dump regs again we still see the R labels because
+# they are on the address space however "bank0" has changed
+# to "bank1" because they are on the underlying chip.
+#dump regs 0 7
+
+# Repeat for banks 2 and 3
+set mem bank 2
+info mem
+#dump regs 0 7
+set mem bank 3
+info mem
+#dump regs 0 7
+
+# And finally check that the registers follow the bank switching correctly
+set mem bank 0
+info reg
+set mem bank 1
+info reg
+set mem bank 2
+info reg
+set mem bank 3
+info reg
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/c517.h sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/c517.h
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/c517.h	2016-12-31 19:31:10.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/c517.h	1970-01-01 00:00:00.000000000 +0000
@@ -1,13 +0,0 @@
-#ifndef C517_HEADER
-#define C517_HEADER
-
-__sfr __at (0xE9) MD0;
-__sfr __at (0xEA) MD1;
-__sfr __at (0xEB) MD2;
-__sfr __at (0xEC) MD3;
-__sfr __at (0xED) MD4;
-__sfr __at (0xEE) MD5;
-
-__sfr __at (0xEF) ARCON;
-
-#endif
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/clean.mk sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/clean.mk
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/clean.mk	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/clean.mk	2021-04-01 17:52:48.000000000 +0000
@@ -0,0 +1,5 @@
+clean:
+
+distclean:
+	rm -f Makefile
+	find . -type d -name out -exec rm -rf {} \;
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/conf.cmd sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/conf.cmd
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/conf.cmd	2016-12-31 19:31:10.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/conf.cmd	1970-01-01 00:00:00.000000000 +0000
@@ -1 +0,0 @@
-set hw simif xram 0xffff
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/config/baseline/251 sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/config/baseline/251
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/config/baseline/251	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/config/baseline/251	2022-02-08 21:21:05.000000000 +0000
@@ -0,0 +1,77 @@
+uCsim, Copyright (C)  Daniel Drotos.
+uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+This is free software, and you are welcome to redistribute it
+under certain conditions; type `show c' for details.
+Type of microcontroller: 251 CMOS cmos
+Controller has 16 hardware element(s).
+   on cpu[0]
+   on simif[0]
+  off vcd[0]
+   on timer0[0]
+   on timer1[1]
+   on uart[0]
+   on dreg[0]
+   on dport[0]
+   on port[0]
+   on port[1]
+   on port[2]
+   on port[3]
+   on irq[0]
+   on timer2[2]
+   on wdt[0]
+   on pca[0]
+     R0 R1 R2 R3 R4 R5 R6 R7
+     08 70 d4 b2 8a 29 54 48
+@R0 9a .  ACC= 0x00   0 .  B= 0x00
+@R1 84 .  PSW= 0x00 CY=0 AC=0 OV=0 P=0
+SP 0x07 -> 48 54 29 8a b2 d4 70 08
+  *DPTR0= 0xb053 @DPTR0= 0x94 148 .
+   DPTR1= 0xe0f8 @DPTR1= 0x4f  79 O
+0x0000  ? ff       MOV    R7,A[0K
+Memory chips:
+  0x000000-0x0000ff      256 variable_storage (32,%08x,0x%02lx)
+  0x000000-0x00ffff    65536 rom_chip (8,%02x,0x%04lx)
+  0x000000-0x0000ff      256 iram_chip (8,%02x,0x%02lx)
+  0x000000-0x00ffff    65536 xram_chip (8,%02x,0x%04lx)
+  0x000000-0x00007f      128 sfr_chip (8,%02x,0x%02lx)
+  0x000000-0x0000ff      256 eram_chip (8,%02x,0x%02lx)
+  0x000000-0x000017       24 dptr_chip (8,%02x,0x%02lx)
+Address spaces:
+  0x000000-0x0000ff      256 variables (32,%08x,0x%02lx)
+  0x000000-0x00ffff    65536 rom (8,%02x,0x%04lx)
+  0x000000-0x0000ff      256 iram (8,%02x,0x%02lx)
+  0x000080-0x0000ff      128 sfr (8,%02x,0x%02lx)
+  0x000000-0x00ffff    65536 xram (8,%02x,0x%04lx)
+  0x000000-0x000007        8 regs (8,%02x,0x%01lx)
+  0x000000-0x0000ff      256 bits (1,%01x,0x%02lx)
+  0x000000-0x000001        2 dptr (8,%02x,0x%01lx)
+Address decoders:
+  variables 0x00 0xff -> variable_storage 0x00 activated
+  rom 0x0000 0xffff -> rom_chip 0x0000 activated
+  iram 0x00 0xff -> iram_chip 0x00 activated
+  sfr 0x80 0xff -> sfr_chip 0x00 activated
+  sfr 0x82 0x83 -> banked
+    bank selector: sfr[0xa2] mask=0x1 banks=2 act=0
+    banks:
+      *  0. dptr_chip 0x00
+         1. dptr_chip 0x02
+  xram 0x0000 0x00ff -> banked
+    bank selector: sfr[0x8e] mask=0x2 banks=2 act=0
+    banks:
+      *  0. eram_chip 0x00
+         1. xram_chip 0x0000
+  xram 0x0100 0xffff -> xram_chip 0x0100 activated
+  regs 0x0 0x7 -> banked
+    bank selector: sfr[0xd0] mask=0x18 banks=4 act=0
+    banks:
+      *  0. iram_chip 0x00
+         1. iram_chip 0x08
+         2. iram_chip 0x10
+         3. iram_chip 0x18
+  bits 0x00 0x7f -> bander(8/1) iram_chip 0x20 activated
+  bits 0x80 0xff -> bander(8/8) sfr_chip 0x00 activated
+  dptr 0x0 0x1 -> banked
+    bank selector: sfr[0xa2] mask=0x1 banks=2 act=0
+    banks:
+      *  0. dptr_chip 0x00
+         1. dptr_chip 0x02
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/config/baseline/51 sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/config/baseline/51
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/config/baseline/51	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/config/baseline/51	2022-02-08 21:21:05.000000000 +0000
@@ -0,0 +1,57 @@
+uCsim, Copyright (C)  Daniel Drotos.
+uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+This is free software, and you are welcome to redistribute it
+under certain conditions; type `show c' for details.
+Type of microcontroller: 51 HMOS hmos
+Controller has 13 hardware element(s).
+   on cpu[0]
+   on simif[0]
+  off vcd[0]
+   on timer0[0]
+   on timer1[1]
+   on uart[0]
+   on dreg[0]
+   on dport[0]
+   on port[0]
+   on port[1]
+   on port[2]
+   on port[3]
+   on irq[0]
+     R0 R1 R2 R3 R4 R5 R6 R7
+     08 70 d4 b2 8a 29 54 48
+@R0 9a .  ACC= 0x00   0 .  B= 0x00
+@R1 84 .  PSW= 0x00 CY=0 AC=0 OV=0 P=0
+SP 0x07 -> 48 54 29 8a b2 d4 70 08
+   DPTR= 0x0000 @DPTR= 0x95 149 .
+0x0000  ? ff       MOV    R7,A[0K
+Memory chips:
+  0x000000-0x0000ff      256 variable_storage (32,%08x,0x%02lx)
+  0x000000-0x00ffff    65536 rom_chip (8,%02x,0x%04lx)
+  0x000000-0x0000ff      256 iram_chip (8,%02x,0x%02lx)
+  0x000000-0x00ffff    65536 xram_chip (8,%02x,0x%04lx)
+  0x000000-0x00007f      128 sfr_chip (8,%02x,0x%02lx)
+Address spaces:
+  0x000000-0x0000ff      256 variables (32,%08x,0x%02lx)
+  0x000000-0x00ffff    65536 rom (8,%02x,0x%04lx)
+  0x000000-0x00007f      128 iram (8,%02x,0x%02lx)
+  0x000080-0x0000ff      128 sfr (8,%02x,0x%02lx)
+  0x000000-0x00ffff    65536 xram (8,%02x,0x%04lx)
+  0x000000-0x000007        8 regs (8,%02x,0x%01lx)
+  0x000000-0x0000ff      256 bits (1,%01x,0x%02lx)
+  0x000000-0x000001        2 dptr (8,%02x,0x%01lx)
+Address decoders:
+  variables 0x00 0xff -> variable_storage 0x00 activated
+  rom 0x0000 0xffff -> rom_chip 0x0000 activated
+  iram 0x00 0x7f -> iram_chip 0x00 activated
+  sfr 0x80 0xff -> sfr_chip 0x00 activated
+  xram 0x0000 0xffff -> xram_chip 0x0000 activated
+  regs 0x0 0x7 -> banked
+    bank selector: sfr[0xd0] mask=0x18 banks=4 act=0
+    banks:
+      *  0. iram_chip 0x00
+         1. iram_chip 0x08
+         2. iram_chip 0x10
+         3. iram_chip 0x18
+  bits 0x00 0x7f -> bander(8/1) iram_chip 0x20 activated
+  bits 0x80 0xff -> bander(8/8) sfr_chip 0x00 activated
+  dptr 0x0 0x1 -> sfr_chip 0x02 activated
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/config/baseline/517 sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/config/baseline/517
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/config/baseline/517	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/config/baseline/517	2022-02-08 21:21:05.000000000 +0000
@@ -0,0 +1,88 @@
+uCsim, Copyright (C)  Daniel Drotos.
+uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+This is free software, and you are welcome to redistribute it
+under certain conditions; type `show c' for details.
+Type of microcontroller: 517 CMOS cmos
+Controller has 15 hardware element(s).
+   on cpu[0]
+   on simif[0]
+  off vcd[0]
+   on timer0[0]
+   on timer1[1]
+   on uart[0]
+   on dreg[0]
+   on dport[0]
+   on port[0]
+   on port[1]
+   on port[2]
+   on port[3]
+   on irq[0]
+   on timer2[2]
+   on mdu[0]
+     R0 R1 R2 R3 R4 R5 R6 R7
+     08 70 d4 b2 8a 29 54 48
+@R0 9a .  ACC= 0x00   0 .  B= 0x00
+@R1 84 .  PSW= 0x00 CY=0 AC=0 OV=0 P=0
+SP 0x07 -> 48 54 29 8a b2 d4 70 08
+  *DPTR0= 0xcc77 @DPTR0= 0x64 100 d
+   DPTR1= 0x4440 @DPTR1= 0x78 120 x
+   DPTR2= 0xc3d3 @DPTR2= 0xcf 207 .
+   DPTR3= 0x3b50 @DPTR3= 0x12  18 .
+   DPTR4= 0xcc46 @DPTR4= 0xe6 230 .
+   DPTR5= 0xf1cb @DPTR5= 0x9b 155 .
+   DPTR6= 0xbaa3 @DPTR6= 0x29  41 )
+   DPTR7= 0xf5dd @DPTR7= 0x42  66 B
+0x0000  ? ff       MOV    R7,A[0K
+Memory chips:
+  0x000000-0x0000ff      256 variable_storage (32,%08x,0x%02lx)
+  0x000000-0x00ffff    65536 rom_chip (8,%02x,0x%04lx)
+  0x000000-0x0000ff      256 iram_chip (8,%02x,0x%02lx)
+  0x000000-0x00ffff    65536 xram_chip (8,%02x,0x%04lx)
+  0x000000-0x00007f      128 sfr_chip (8,%02x,0x%02lx)
+  0x000000-0x000017       24 dptr_chip (8,%02x,0x%02lx)
+Address spaces:
+  0x000000-0x0000ff      256 variables (32,%08x,0x%02lx)
+  0x000000-0x00ffff    65536 rom (8,%02x,0x%04lx)
+  0x000000-0x0000ff      256 iram (8,%02x,0x%02lx)
+  0x000080-0x0000ff      128 sfr (8,%02x,0x%02lx)
+  0x000000-0x00ffff    65536 xram (8,%02x,0x%04lx)
+  0x000000-0x000007        8 regs (8,%02x,0x%01lx)
+  0x000000-0x0000ff      256 bits (1,%01x,0x%02lx)
+  0x000000-0x000001        2 dptr (8,%02x,0x%01lx)
+Address decoders:
+  variables 0x00 0xff -> variable_storage 0x00 activated
+  rom 0x0000 0xffff -> rom_chip 0x0000 activated
+  iram 0x00 0xff -> iram_chip 0x00 activated
+  sfr 0x80 0xff -> sfr_chip 0x00 activated
+  sfr 0x82 0x83 -> banked
+    bank selector: sfr[0x92] mask=0x7 banks=8 act=0
+    banks:
+      *  0. dptr_chip 0x00
+         1. dptr_chip 0x02
+         2. dptr_chip 0x04
+         3. dptr_chip 0x06
+         4. dptr_chip 0x08
+         5. dptr_chip 0x0a
+         6. dptr_chip 0x0c
+         7. dptr_chip 0x0e
+  xram 0x0000 0xffff -> xram_chip 0x0000 activated
+  regs 0x0 0x7 -> banked
+    bank selector: sfr[0xd0] mask=0x18 banks=4 act=0
+    banks:
+      *  0. iram_chip 0x00
+         1. iram_chip 0x08
+         2. iram_chip 0x10
+         3. iram_chip 0x18
+  bits 0x00 0x7f -> bander(8/1) iram_chip 0x20 activated
+  bits 0x80 0xff -> bander(8/8) sfr_chip 0x00 activated
+  dptr 0x0 0x1 -> banked
+    bank selector: sfr[0x92] mask=0x7 banks=8 act=0
+    banks:
+      *  0. dptr_chip 0x00
+         1. dptr_chip 0x02
+         2. dptr_chip 0x04
+         3. dptr_chip 0x06
+         4. dptr_chip 0x08
+         5. dptr_chip 0x0a
+         6. dptr_chip 0x0c
+         7. dptr_chip 0x0e
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/config/baseline/51R sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/config/baseline/51R
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/config/baseline/51R	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/config/baseline/51R	2022-02-08 21:21:05.000000000 +0000
@@ -0,0 +1,65 @@
+uCsim, Copyright (C)  Daniel Drotos.
+uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+This is free software, and you are welcome to redistribute it
+under certain conditions; type `show c' for details.
+Type of microcontroller: 51R CMOS cmos
+Controller has 15 hardware element(s).
+   on cpu[0]
+   on simif[0]
+  off vcd[0]
+   on timer0[0]
+   on timer1[1]
+   on uart[0]
+   on dreg[0]
+   on dport[0]
+   on port[0]
+   on port[1]
+   on port[2]
+   on port[3]
+   on irq[0]
+   on timer2[2]
+   on wdt[0]
+     R0 R1 R2 R3 R4 R5 R6 R7
+     08 70 d4 b2 8a 29 54 48
+@R0 9a .  ACC= 0x00   0 .  B= 0x00
+@R1 84 .  PSW= 0x00 CY=0 AC=0 OV=0 P=0
+SP 0x07 -> 48 54 29 8a b2 d4 70 08
+   DPTR= 0x0000 @DPTR= 0x77 119 w
+0x0000  ? ff       MOV    R7,A[0K
+Memory chips:
+  0x000000-0x0000ff      256 variable_storage (32,%08x,0x%02lx)
+  0x000000-0x00ffff    65536 rom_chip (8,%02x,0x%04lx)
+  0x000000-0x0000ff      256 iram_chip (8,%02x,0x%02lx)
+  0x000000-0x00ffff    65536 xram_chip (8,%02x,0x%04lx)
+  0x000000-0x00007f      128 sfr_chip (8,%02x,0x%02lx)
+  0x000000-0x0000ff      256 eram_chip (8,%02x,0x%02lx)
+Address spaces:
+  0x000000-0x0000ff      256 variables (32,%08x,0x%02lx)
+  0x000000-0x00ffff    65536 rom (8,%02x,0x%04lx)
+  0x000000-0x0000ff      256 iram (8,%02x,0x%02lx)
+  0x000080-0x0000ff      128 sfr (8,%02x,0x%02lx)
+  0x000000-0x00ffff    65536 xram (8,%02x,0x%04lx)
+  0x000000-0x000007        8 regs (8,%02x,0x%01lx)
+  0x000000-0x0000ff      256 bits (1,%01x,0x%02lx)
+  0x000000-0x000001        2 dptr (8,%02x,0x%01lx)
+Address decoders:
+  variables 0x00 0xff -> variable_storage 0x00 activated
+  rom 0x0000 0xffff -> rom_chip 0x0000 activated
+  iram 0x00 0xff -> iram_chip 0x00 activated
+  sfr 0x80 0xff -> sfr_chip 0x00 activated
+  xram 0x0000 0x00ff -> banked
+    bank selector: sfr[0x8e] mask=0x2 banks=2 act=0
+    banks:
+      *  0. eram_chip 0x00
+         1. xram_chip 0x0000
+  xram 0x0100 0xffff -> xram_chip 0x0100 activated
+  regs 0x0 0x7 -> banked
+    bank selector: sfr[0xd0] mask=0x18 banks=4 act=0
+    banks:
+      *  0. iram_chip 0x00
+         1. iram_chip 0x08
+         2. iram_chip 0x10
+         3. iram_chip 0x18
+  bits 0x00 0x7f -> bander(8/1) iram_chip 0x20 activated
+  bits 0x80 0xff -> bander(8/8) sfr_chip 0x00 activated
+  dptr 0x0 0x1 -> sfr_chip 0x02 activated
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/config/baseline/52 sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/config/baseline/52
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/config/baseline/52	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/config/baseline/52	2022-02-08 21:21:05.000000000 +0000
@@ -0,0 +1,58 @@
+uCsim, Copyright (C)  Daniel Drotos.
+uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+This is free software, and you are welcome to redistribute it
+under certain conditions; type `show c' for details.
+Type of microcontroller: C52 HMOS hmos
+Controller has 14 hardware element(s).
+   on cpu[0]
+   on simif[0]
+  off vcd[0]
+   on timer0[0]
+   on timer1[1]
+   on uart[0]
+   on dreg[0]
+   on dport[0]
+   on port[0]
+   on port[1]
+   on port[2]
+   on port[3]
+   on irq[0]
+   on timer2[2]
+     R0 R1 R2 R3 R4 R5 R6 R7
+     08 70 d4 b2 8a 29 54 48
+@R0 9a .  ACC= 0x00   0 .  B= 0x00
+@R1 84 .  PSW= 0x00 CY=0 AC=0 OV=0 P=0
+SP 0x07 -> 48 54 29 8a b2 d4 70 08
+   DPTR= 0x0000 @DPTR= 0x95 149 .
+0x0000  ? ff       MOV    R7,A[0K
+Memory chips:
+  0x000000-0x0000ff      256 variable_storage (32,%08x,0x%02lx)
+  0x000000-0x00ffff    65536 rom_chip (8,%02x,0x%04lx)
+  0x000000-0x0000ff      256 iram_chip (8,%02x,0x%02lx)
+  0x000000-0x00ffff    65536 xram_chip (8,%02x,0x%04lx)
+  0x000000-0x00007f      128 sfr_chip (8,%02x,0x%02lx)
+Address spaces:
+  0x000000-0x0000ff      256 variables (32,%08x,0x%02lx)
+  0x000000-0x00ffff    65536 rom (8,%02x,0x%04lx)
+  0x000000-0x0000ff      256 iram (8,%02x,0x%02lx)
+  0x000080-0x0000ff      128 sfr (8,%02x,0x%02lx)
+  0x000000-0x00ffff    65536 xram (8,%02x,0x%04lx)
+  0x000000-0x000007        8 regs (8,%02x,0x%01lx)
+  0x000000-0x0000ff      256 bits (1,%01x,0x%02lx)
+  0x000000-0x000001        2 dptr (8,%02x,0x%01lx)
+Address decoders:
+  variables 0x00 0xff -> variable_storage 0x00 activated
+  rom 0x0000 0xffff -> rom_chip 0x0000 activated
+  iram 0x00 0xff -> iram_chip 0x00 activated
+  sfr 0x80 0xff -> sfr_chip 0x00 activated
+  xram 0x0000 0xffff -> xram_chip 0x0000 activated
+  regs 0x0 0x7 -> banked
+    bank selector: sfr[0xd0] mask=0x18 banks=4 act=0
+    banks:
+      *  0. iram_chip 0x00
+         1. iram_chip 0x08
+         2. iram_chip 0x10
+         3. iram_chip 0x18
+  bits 0x00 0x7f -> bander(8/1) iram_chip 0x20 activated
+  bits 0x80 0xff -> bander(8/8) sfr_chip 0x00 activated
+  dptr 0x0 0x1 -> sfr_chip 0x02 activated
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/config/baseline/88X sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/config/baseline/88X
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/config/baseline/88X	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/config/baseline/88X	2022-02-08 21:21:05.000000000 +0000
@@ -0,0 +1,70 @@
+uCsim, Copyright (C)  Daniel Drotos.
+uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+This is free software, and you are welcome to redistribute it
+under certain conditions; type `show c' for details.
+Type of microcontroller: 88X CMOS cmos
+Controller has 15 hardware element(s).
+   on cpu[0]
+   on simif[0]
+  off vcd[0]
+   on timer0[0]
+   on timer1[1]
+   on uart[0]
+   on dreg[0]
+   on dport[0]
+   on port[0]
+   on port[1]
+   on port[2]
+   on port[3]
+   on irq[0]
+   on timer2[2]
+   on mdu[0]
+     R0 R1 R2 R3 R4 R5 R6 R7
+     08 70 d4 b2 8a 29 54 48
+@R0 9a .  ACC= 0x00   0 .  B= 0x00
+@R1 84 .  PSW= 0x00 CY=0 AC=0 OV=0 P=0
+SP 0x07 -> 48 54 29 8a b2 d4 70 08
+  *DPTR0= 0xcc77 @DPTR0= 0x64 100 d
+   DPTR1= 0x4440 @DPTR1= 0x78 120 x
+0x0000  ? ff       MOV    R7,A[0K
+Memory chips:
+  0x000000-0x0000ff      256 variable_storage (32,%08x,0x%02lx)
+  0x000000-0x00ffff    65536 rom_chip (8,%02x,0x%04lx)
+  0x000000-0x0000ff      256 iram_chip (8,%02x,0x%02lx)
+  0x000000-0x00ffff    65536 xram_chip (8,%02x,0x%04lx)
+  0x000000-0x00007f      128 sfr_chip (8,%02x,0x%02lx)
+  0x000000-0x000017       24 dptr_chip (8,%02x,0x%02lx)
+Address spaces:
+  0x000000-0x0000ff      256 variables (32,%08x,0x%02lx)
+  0x000000-0x00ffff    65536 rom (8,%02x,0x%04lx)
+  0x000000-0x0000ff      256 iram (8,%02x,0x%02lx)
+  0x000080-0x0000ff      128 sfr (8,%02x,0x%02lx)
+  0x000000-0x00ffff    65536 xram (8,%02x,0x%04lx)
+  0x000000-0x000007        8 regs (8,%02x,0x%01lx)
+  0x000000-0x0000ff      256 bits (1,%01x,0x%02lx)
+  0x000000-0x000001        2 dptr (8,%02x,0x%01lx)
+Address decoders:
+  variables 0x00 0xff -> variable_storage 0x00 activated
+  rom 0x0000 0xffff -> rom_chip 0x0000 activated
+  iram 0x00 0xff -> iram_chip 0x00 activated
+  sfr 0x80 0xff -> sfr_chip 0x00 activated
+  sfr 0x82 0x83 -> banked
+    bank selector: sfr[0xa2] mask=0x1 banks=2 act=0
+    banks:
+      *  0. dptr_chip 0x00
+         1. dptr_chip 0x02
+  xram 0x0000 0xffff -> xram_chip 0x0000 activated
+  regs 0x0 0x7 -> banked
+    bank selector: sfr[0xd0] mask=0x18 banks=4 act=0
+    banks:
+      *  0. iram_chip 0x00
+         1. iram_chip 0x08
+         2. iram_chip 0x10
+         3. iram_chip 0x18
+  bits 0x00 0x7f -> bander(8/1) iram_chip 0x20 activated
+  bits 0x80 0xff -> bander(8/8) sfr_chip 0x00 activated
+  dptr 0x0 0x1 -> banked
+    bank selector: sfr[0xa2] mask=0x1 banks=2 act=0
+    banks:
+      *  0. dptr_chip 0x00
+         1. dptr_chip 0x02
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/config/baseline/89C51R sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/config/baseline/89C51R
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/config/baseline/89C51R	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/config/baseline/89C51R	2022-02-08 21:21:05.000000000 +0000
@@ -0,0 +1,77 @@
+uCsim, Copyright (C)  Daniel Drotos.
+uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+This is free software, and you are welcome to redistribute it
+under certain conditions; type `show c' for details.
+Type of microcontroller: 89C51R CMOS cmos
+Controller has 16 hardware element(s).
+   on cpu[0]
+   on simif[0]
+  off vcd[0]
+   on timer0[0]
+   on timer1[1]
+   on uart[0]
+   on dreg[0]
+   on dport[0]
+   on port[0]
+   on port[1]
+   on port[2]
+   on port[3]
+   on irq[0]
+   on timer2[2]
+   on wdt[0]
+   on pca[0]
+     R0 R1 R2 R3 R4 R5 R6 R7
+     08 70 d4 b2 8a 29 54 48
+@R0 9a .  ACC= 0x00   0 .  B= 0x00
+@R1 84 .  PSW= 0x00 CY=0 AC=0 OV=0 P=0
+SP 0x07 -> 48 54 29 8a b2 d4 70 08
+  *DPTR0= 0xb053 @DPTR0= 0x94 148 .
+   DPTR1= 0xe0f8 @DPTR1= 0x4f  79 O
+0x0000  ? ff       MOV    R7,A[0K
+Memory chips:
+  0x000000-0x0000ff      256 variable_storage (32,%08x,0x%02lx)
+  0x000000-0x00ffff    65536 rom_chip (8,%02x,0x%04lx)
+  0x000000-0x0000ff      256 iram_chip (8,%02x,0x%02lx)
+  0x000000-0x00ffff    65536 xram_chip (8,%02x,0x%04lx)
+  0x000000-0x00007f      128 sfr_chip (8,%02x,0x%02lx)
+  0x000000-0x0000ff      256 eram_chip (8,%02x,0x%02lx)
+  0x000000-0x000017       24 dptr_chip (8,%02x,0x%02lx)
+Address spaces:
+  0x000000-0x0000ff      256 variables (32,%08x,0x%02lx)
+  0x000000-0x00ffff    65536 rom (8,%02x,0x%04lx)
+  0x000000-0x0000ff      256 iram (8,%02x,0x%02lx)
+  0x000080-0x0000ff      128 sfr (8,%02x,0x%02lx)
+  0x000000-0x00ffff    65536 xram (8,%02x,0x%04lx)
+  0x000000-0x000007        8 regs (8,%02x,0x%01lx)
+  0x000000-0x0000ff      256 bits (1,%01x,0x%02lx)
+  0x000000-0x000001        2 dptr (8,%02x,0x%01lx)
+Address decoders:
+  variables 0x00 0xff -> variable_storage 0x00 activated
+  rom 0x0000 0xffff -> rom_chip 0x0000 activated
+  iram 0x00 0xff -> iram_chip 0x00 activated
+  sfr 0x80 0xff -> sfr_chip 0x00 activated
+  sfr 0x82 0x83 -> banked
+    bank selector: sfr[0xa2] mask=0x1 banks=2 act=0
+    banks:
+      *  0. dptr_chip 0x00
+         1. dptr_chip 0x02
+  xram 0x0000 0x00ff -> banked
+    bank selector: sfr[0x8e] mask=0x2 banks=2 act=0
+    banks:
+      *  0. eram_chip 0x00
+         1. xram_chip 0x0000
+  xram 0x0100 0xffff -> xram_chip 0x0100 activated
+  regs 0x0 0x7 -> banked
+    bank selector: sfr[0xd0] mask=0x18 banks=4 act=0
+    banks:
+      *  0. iram_chip 0x00
+         1. iram_chip 0x08
+         2. iram_chip 0x10
+         3. iram_chip 0x18
+  bits 0x00 0x7f -> bander(8/1) iram_chip 0x20 activated
+  bits 0x80 0xff -> bander(8/8) sfr_chip 0x00 activated
+  dptr 0x0 0x1 -> banked
+    bank selector: sfr[0xa2] mask=0x1 banks=2 act=0
+    banks:
+      *  0. dptr_chip 0x00
+         1. dptr_chip 0x02
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/config/baseline/C51 sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/config/baseline/C51
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/config/baseline/C51	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/config/baseline/C51	2022-02-08 21:21:05.000000000 +0000
@@ -0,0 +1,57 @@
+uCsim, Copyright (C)  Daniel Drotos.
+uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+This is free software, and you are welcome to redistribute it
+under certain conditions; type `show c' for details.
+Type of microcontroller: 51 CMOS cmos
+Controller has 13 hardware element(s).
+   on cpu[0]
+   on simif[0]
+  off vcd[0]
+   on timer0[0]
+   on timer1[1]
+   on uart[0]
+   on dreg[0]
+   on dport[0]
+   on port[0]
+   on port[1]
+   on port[2]
+   on port[3]
+   on irq[0]
+     R0 R1 R2 R3 R4 R5 R6 R7
+     08 70 d4 b2 8a 29 54 48
+@R0 9a .  ACC= 0x00   0 .  B= 0x00
+@R1 84 .  PSW= 0x00 CY=0 AC=0 OV=0 P=0
+SP 0x07 -> 48 54 29 8a b2 d4 70 08
+   DPTR= 0x0000 @DPTR= 0x95 149 .
+0x0000  ? ff       MOV    R7,A[0K
+Memory chips:
+  0x000000-0x0000ff      256 variable_storage (32,%08x,0x%02lx)
+  0x000000-0x00ffff    65536 rom_chip (8,%02x,0x%04lx)
+  0x000000-0x0000ff      256 iram_chip (8,%02x,0x%02lx)
+  0x000000-0x00ffff    65536 xram_chip (8,%02x,0x%04lx)
+  0x000000-0x00007f      128 sfr_chip (8,%02x,0x%02lx)
+Address spaces:
+  0x000000-0x0000ff      256 variables (32,%08x,0x%02lx)
+  0x000000-0x00ffff    65536 rom (8,%02x,0x%04lx)
+  0x000000-0x00007f      128 iram (8,%02x,0x%02lx)
+  0x000080-0x0000ff      128 sfr (8,%02x,0x%02lx)
+  0x000000-0x00ffff    65536 xram (8,%02x,0x%04lx)
+  0x000000-0x000007        8 regs (8,%02x,0x%01lx)
+  0x000000-0x0000ff      256 bits (1,%01x,0x%02lx)
+  0x000000-0x000001        2 dptr (8,%02x,0x%01lx)
+Address decoders:
+  variables 0x00 0xff -> variable_storage 0x00 activated
+  rom 0x0000 0xffff -> rom_chip 0x0000 activated
+  iram 0x00 0x7f -> iram_chip 0x00 activated
+  sfr 0x80 0xff -> sfr_chip 0x00 activated
+  xram 0x0000 0xffff -> xram_chip 0x0000 activated
+  regs 0x0 0x7 -> banked
+    bank selector: sfr[0xd0] mask=0x18 banks=4 act=0
+    banks:
+      *  0. iram_chip 0x00
+         1. iram_chip 0x08
+         2. iram_chip 0x10
+         3. iram_chip 0x18
+  bits 0x00 0x7f -> bander(8/1) iram_chip 0x20 activated
+  bits 0x80 0xff -> bander(8/8) sfr_chip 0x00 activated
+  dptr 0x0 0x1 -> sfr_chip 0x02 activated
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/config/baseline/C52 sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/config/baseline/C52
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/config/baseline/C52	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/config/baseline/C52	2022-02-08 21:21:05.000000000 +0000
@@ -0,0 +1,58 @@
+uCsim, Copyright (C)  Daniel Drotos.
+uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+This is free software, and you are welcome to redistribute it
+under certain conditions; type `show c' for details.
+Type of microcontroller: C52 CMOS cmos
+Controller has 14 hardware element(s).
+   on cpu[0]
+   on simif[0]
+  off vcd[0]
+   on timer0[0]
+   on timer1[1]
+   on uart[0]
+   on dreg[0]
+   on dport[0]
+   on port[0]
+   on port[1]
+   on port[2]
+   on port[3]
+   on irq[0]
+   on timer2[2]
+     R0 R1 R2 R3 R4 R5 R6 R7
+     08 70 d4 b2 8a 29 54 48
+@R0 9a .  ACC= 0x00   0 .  B= 0x00
+@R1 84 .  PSW= 0x00 CY=0 AC=0 OV=0 P=0
+SP 0x07 -> 48 54 29 8a b2 d4 70 08
+   DPTR= 0x0000 @DPTR= 0x95 149 .
+0x0000  ? ff       MOV    R7,A[0K
+Memory chips:
+  0x000000-0x0000ff      256 variable_storage (32,%08x,0x%02lx)
+  0x000000-0x00ffff    65536 rom_chip (8,%02x,0x%04lx)
+  0x000000-0x0000ff      256 iram_chip (8,%02x,0x%02lx)
+  0x000000-0x00ffff    65536 xram_chip (8,%02x,0x%04lx)
+  0x000000-0x00007f      128 sfr_chip (8,%02x,0x%02lx)
+Address spaces:
+  0x000000-0x0000ff      256 variables (32,%08x,0x%02lx)
+  0x000000-0x00ffff    65536 rom (8,%02x,0x%04lx)
+  0x000000-0x0000ff      256 iram (8,%02x,0x%02lx)
+  0x000080-0x0000ff      128 sfr (8,%02x,0x%02lx)
+  0x000000-0x00ffff    65536 xram (8,%02x,0x%04lx)
+  0x000000-0x000007        8 regs (8,%02x,0x%01lx)
+  0x000000-0x0000ff      256 bits (1,%01x,0x%02lx)
+  0x000000-0x000001        2 dptr (8,%02x,0x%01lx)
+Address decoders:
+  variables 0x00 0xff -> variable_storage 0x00 activated
+  rom 0x0000 0xffff -> rom_chip 0x0000 activated
+  iram 0x00 0xff -> iram_chip 0x00 activated
+  sfr 0x80 0xff -> sfr_chip 0x00 activated
+  xram 0x0000 0xffff -> xram_chip 0x0000 activated
+  regs 0x0 0x7 -> banked
+    bank selector: sfr[0xd0] mask=0x18 banks=4 act=0
+    banks:
+      *  0. iram_chip 0x00
+         1. iram_chip 0x08
+         2. iram_chip 0x10
+         3. iram_chip 0x18
+  bits 0x00 0x7f -> bander(8/1) iram_chip 0x20 activated
+  bits 0x80 0xff -> bander(8/8) sfr_chip 0x00 activated
+  dptr 0x0 0x1 -> sfr_chip 0x02 activated
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/config/baseline/C521 sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/config/baseline/C521
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/config/baseline/C521	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/config/baseline/C521	2022-02-08 21:21:05.000000000 +0000
@@ -0,0 +1,68 @@
+uCsim, Copyright (C)  Daniel Drotos.
+uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+This is free software, and you are welcome to redistribute it
+under certain conditions; type `show c' for details.
+Type of microcontroller: C521 CMOS cmos
+Controller has 14 hardware element(s).
+   on cpu[0]
+   on simif[0]
+  off vcd[0]
+   on timer0[0]
+   on timer1[1]
+   on uart[0]
+   on dreg[0]
+   on dport[0]
+   on port[0]
+   on port[1]
+   on port[2]
+   on port[3]
+   on irq[0]
+   on timer2[2]
+     R0 R1 R2 R3 R4 R5 R6 R7
+     08 70 d4 b2 8a 29 54 48
+@R0 9a .  ACC= 0x00   0 .  B= 0x00
+@R1 84 .  PSW= 0x00 CY=0 AC=0 OV=0 P=0
+SP 0x07 -> 48 54 29 8a b2 d4 70 08
+  *DPTR0= 0x0000 @DPTR0= 0x95 149 .
+   DPTR1= 0x0000 @DPTR1= 0x95 149 .
+0x0000  ? ff       MOV    R7,A[0K
+Memory chips:
+  0x000000-0x0000ff      256 variable_storage (32,%08x,0x%02lx)
+  0x000000-0x00ffff    65536 rom_chip (8,%02x,0x%04lx)
+  0x000000-0x0000ff      256 iram_chip (8,%02x,0x%02lx)
+  0x000000-0x00ffff    65536 xram_chip (8,%02x,0x%04lx)
+  0x000000-0x00007f      128 sfr_chip (8,%02x,0x%02lx)
+Address spaces:
+  0x000000-0x0000ff      256 variables (32,%08x,0x%02lx)
+  0x000000-0x00ffff    65536 rom (8,%02x,0x%04lx)
+  0x000000-0x0000ff      256 iram (8,%02x,0x%02lx)
+  0x000080-0x0000ff      128 sfr (8,%02x,0x%02lx)
+  0x000000-0x00ffff    65536 xram (8,%02x,0x%04lx)
+  0x000000-0x000007        8 regs (8,%02x,0x%01lx)
+  0x000000-0x0000ff      256 bits (1,%01x,0x%02lx)
+  0x000000-0x000001        2 dptr (8,%02x,0x%01lx)
+Address decoders:
+  variables 0x00 0xff -> variable_storage 0x00 activated
+  rom 0x0000 0xffff -> rom_chip 0x0000 activated
+  iram 0x00 0xff -> iram_chip 0x00 activated
+  sfr 0x80 0xff -> sfr_chip 0x00 activated
+  xram 0x0000 0xffff -> xram_chip 0x0000 activated
+  regs 0x0 0x7 -> banked
+    bank selector: sfr[0xd0] mask=0x18 banks=4 act=0
+    banks:
+      *  0. iram_chip 0x00
+         1. iram_chip 0x08
+         2. iram_chip 0x10
+         3. iram_chip 0x18
+  bits 0x00 0x7f -> bander(8/1) iram_chip 0x20 activated
+  bits 0x80 0xff -> bander(8/8) sfr_chip 0x00 activated
+  dptr 0x0 0x0 -> banked
+    bank selector: sfr[0x86] mask=0x1 banks=2 act=0
+    banks:
+      *  0. sfr_chip 0x02
+         1. sfr_chip 0x04
+  dptr 0x1 0x1 -> banked
+    bank selector: sfr[0x86] mask=0x1 banks=2 act=0
+    banks:
+      *  0. sfr_chip 0x03
+         1. sfr_chip 0x05
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/config/baseline/DS320 sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/config/baseline/DS320
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/config/baseline/DS320	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/config/baseline/DS320	2022-02-08 21:21:05.000000000 +0000
@@ -0,0 +1,68 @@
+uCsim, Copyright (C)  Daniel Drotos.
+uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+This is free software, and you are welcome to redistribute it
+under certain conditions; type `show c' for details.
+Type of microcontroller: DS320 CMOS cmos
+Controller has 14 hardware element(s).
+   on cpu[0]
+   on simif[0]
+  off vcd[0]
+   on timer0[0]
+   on timer1[1]
+   on uart[0]
+   on dreg[0]
+   on dport[0]
+   on port[0]
+   on port[1]
+   on port[2]
+   on port[3]
+   on irq[0]
+   on timer2[2]
+     R0 R1 R2 R3 R4 R5 R6 R7
+     08 70 d4 b2 8a 29 54 48
+@R0 9a .  ACC= 0x00   0 .  B= 0x00
+@R1 84 .  PSW= 0x00 CY=0 AC=0 OV=0 P=0
+SP 0x07 -> 48 54 29 8a b2 d4 70 08
+  *DPTR0= 0x0000 @DPTR0= 0x95 149 .
+   DPTR1= 0x0000 @DPTR1= 0x95 149 .
+0x0000  ? ff       MOV    R7,A[0K
+Memory chips:
+  0x000000-0x0000ff      256 variable_storage (32,%08x,0x%02lx)
+  0x000000-0x00ffff    65536 rom_chip (8,%02x,0x%04lx)
+  0x000000-0x0000ff      256 iram_chip (8,%02x,0x%02lx)
+  0x000000-0x00ffff    65536 xram_chip (8,%02x,0x%04lx)
+  0x000000-0x00007f      128 sfr_chip (8,%02x,0x%02lx)
+Address spaces:
+  0x000000-0x0000ff      256 variables (32,%08x,0x%02lx)
+  0x000000-0x00ffff    65536 rom (8,%02x,0x%04lx)
+  0x000000-0x0000ff      256 iram (8,%02x,0x%02lx)
+  0x000080-0x0000ff      128 sfr (8,%02x,0x%02lx)
+  0x000000-0x00ffff    65536 xram (8,%02x,0x%04lx)
+  0x000000-0x000007        8 regs (8,%02x,0x%01lx)
+  0x000000-0x0000ff      256 bits (1,%01x,0x%02lx)
+  0x000000-0x000001        2 dptr (8,%02x,0x%01lx)
+Address decoders:
+  variables 0x00 0xff -> variable_storage 0x00 activated
+  rom 0x0000 0xffff -> rom_chip 0x0000 activated
+  iram 0x00 0xff -> iram_chip 0x00 activated
+  sfr 0x80 0xff -> sfr_chip 0x00 activated
+  xram 0x0000 0xffff -> xram_chip 0x0000 activated
+  regs 0x0 0x7 -> banked
+    bank selector: sfr[0xd0] mask=0x18 banks=4 act=0
+    banks:
+      *  0. iram_chip 0x00
+         1. iram_chip 0x08
+         2. iram_chip 0x10
+         3. iram_chip 0x18
+  bits 0x00 0x7f -> bander(8/1) iram_chip 0x20 activated
+  bits 0x80 0xff -> bander(8/8) sfr_chip 0x00 activated
+  dptr 0x0 0x0 -> banked
+    bank selector: sfr[0x86] mask=0x1 banks=2 act=0
+    banks:
+      *  0. sfr_chip 0x02
+         1. sfr_chip 0x04
+  dptr 0x1 0x1 -> banked
+    bank selector: sfr[0x86] mask=0x1 banks=2 act=0
+    banks:
+      *  0. sfr_chip 0x03
+         1. sfr_chip 0x05
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/config/baseline/DS390 sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/config/baseline/DS390
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/config/baseline/DS390	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/config/baseline/DS390	2022-02-08 21:21:05.000000000 +0000
@@ -0,0 +1,60 @@
+uCsim, Copyright (C)  Daniel Drotos.
+uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+This is free software, and you are welcome to redistribute it
+under certain conditions; type `show c' for details.
+Type of microcontroller: DS390 CMOS cmos
+Controller has 15 hardware element(s).
+   on cpu[0]
+   on simif[0]
+  off vcd[0]
+   on timer0[0]
+   on timer1[1]
+   on uart[0]
+   on dreg[0]
+   on dport[0]
+   on port[0]
+   on port[1]
+   on port[2]
+   on port[3]
+   on irq[0]
+   on timer2[2]
+   on ds390hw[0]
+     R0 R1 R2 R3 R4 R5 R6 R7
+     00 00 00 00 00 00 00 00
+@R0 00 .  ACC= 0x00   0 .  B= 0x00
+@R1 00 .  PSW= 0x00 CY=0 AC=0 OV=0 P=0
+SP 0x07 -> 00 00 00 00 00 00 00 00
+   DPTR= 0x0000 @DPTR= 0x00   0 .
+0x00000  ? ff       MOV    R7,A[0K
+Memory chips:
+  0x000000-0x0000ff      256 variable_storage (32,%08x,0x%02lx)
+  0x000000-0x01ffff   131072 rom_chip (8,%02x,0x%05lx)
+  0x000000-0x0000ff      256 iram_chip (8,%02x,0x%02lx)
+  0x000000-0x10007f  1048704 xram_chip (8,%02x,0x%06lx)
+  0x000000-0x000fff     4096 ixram_chip (8,%02x,0x%03lx)
+  0x000000-0x00007f      128 sfr_chip (8,%02x,0x%02lx)
+Address spaces:
+  0x000000-0x0000ff      256 variables (32,%08x,0x%02lx)
+  0x000000-0x01ffff   131072 rom (8,%02x,0x%05lx)
+  0x000000-0x0000ff      256 iram (8,%02x,0x%02lx)
+  0x000080-0x0000ff      128 sfr (8,%02x,0x%02lx)
+  0x000000-0x10007f  1048704 xram (8,%02x,0x%06lx)
+  0x000000-0x000fff     4096 ixram (8,%02x,0x%03lx)
+  0x000000-0x000007        8 regs (8,%02x,0x%01lx)
+  0x000000-0x0000ff      256 bits (1,%01x,0x%02lx)
+Address decoders:
+  variables 0x00 0xff -> variable_storage 0x00 activated
+  rom 0x00000 0x1ffff -> rom_chip 0x00000 activated
+  iram 0x00 0xff -> iram_chip 0x00 activated
+  sfr 0x80 0xff -> sfr_chip 0x00 activated
+  xram 0x000000 0x10007f -> xram_chip 0x000000 activated
+  ixram 0x000 0xfff -> ixram_chip 0x000 activated
+  regs 0x0 0x7 -> banked
+    bank selector: sfr[0xd0] mask=0x18 banks=4 act=0
+    banks:
+      *  0. iram_chip 0x00
+         1. iram_chip 0x08
+         2. iram_chip 0x10
+         3. iram_chip 0x18
+  bits 0x00 0x7f -> bander(8/1) iram_chip 0x20 activated
+  bits 0x80 0xff -> bander(8/8) sfr_chip 0x00 activated
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/config/baseline/DS390F sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/config/baseline/DS390F
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/config/baseline/DS390F	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/config/baseline/DS390F	2022-02-08 21:21:05.000000000 +0000
@@ -0,0 +1,59 @@
+uCsim, Copyright (C)  Daniel Drotos.
+uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+This is free software, and you are welcome to redistribute it
+under certain conditions; type `show c' for details.
+Type of microcontroller: DS390F CMOS cmos
+Controller has 15 hardware element(s).
+   on cpu[0]
+   on simif[0]
+  off vcd[0]
+   on timer0[0]
+   on timer1[1]
+   on uart[0]
+   on dreg[0]
+   on dport[0]
+   on port[0]
+   on port[1]
+   on port[2]
+   on port[3]
+   on irq[0]
+   on timer2[2]
+   on ds390hw[0]
+0x00                      00 00 00 00 00 00 00 00 ........
+     R0 R1 R2 R3 R4 R5 R6 R7
+@R0 00 .  ACC= 0x00   0 .  B= 0x00  *DPTR0= 0x000000 @DPTR0= 0x00   0 .   DPTR1= 0x000000 @DPTR1= 0x00   0 .
+@R1 00 .  AP= 0x00  PSW= 0x00 CY=0 AC=0 OV=0 P=0    SP 0x07                      00 00 00 00 00 00 00 00 ........
+0x00000  ? ff          MOV    R7,A[0K
+Memory chips:
+  0x000000-0x0000ff      256 variable_storage (32,%08x,0x%02lx)
+  0x000000-0x01ffff   131072 rom_chip (8,%02x,0x%05lx)
+  0x000000-0x0000ff      256 iram_chip (8,%02x,0x%02lx)
+  0x000000-0x10007f  1048704 xram_chip (8,%02x,0x%06lx)
+  0x000000-0x000fff     4096 ixram_chip (8,%02x,0x%03lx)
+  0x000000-0x00007f      128 sfr_chip (8,%02x,0x%02lx)
+Address spaces:
+  0x000000-0x0000ff      256 variables (32,%08x,0x%02lx)
+  0x000000-0x01ffff   131072 rom (8,%02x,0x%05lx)
+  0x000000-0x0000ff      256 iram (8,%02x,0x%02lx)
+  0x000080-0x0000ff      128 sfr (8,%02x,0x%02lx)
+  0x000000-0x10007f  1048704 xram (8,%02x,0x%06lx)
+  0x000000-0x000fff     4096 ixram (8,%02x,0x%03lx)
+  0x000000-0x000007        8 regs (8,%02x,0x%01lx)
+  0x000000-0x0000ff      256 bits (1,%01x,0x%02lx)
+Address decoders:
+  variables 0x00 0xff -> variable_storage 0x00 activated
+  rom 0x00000 0x1ffff -> rom_chip 0x00000 activated
+  iram 0x00 0xff -> iram_chip 0x00 activated
+  sfr 0x80 0xff -> sfr_chip 0x00 activated
+  xram 0x000000 0x10007f -> xram_chip 0x000000 activated
+  ixram 0x000 0xfff -> ixram_chip 0x000 activated
+  regs 0x0 0x7 -> banked
+    bank selector: sfr[0xd0] mask=0x18 banks=4 act=0
+    banks:
+      *  0. iram_chip 0x00
+         1. iram_chip 0x08
+         2. iram_chip 0x10
+         3. iram_chip 0x18
+  bits 0x00 0x7f -> bander(8/1) iram_chip 0x20 activated
+  bits 0x80 0xff -> bander(8/8) sfr_chip 0x00 activated
+24-bit flat mode, warning: lots of sfr-functions not implemented!
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/config/baseline/F380 sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/config/baseline/F380
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/config/baseline/F380	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/config/baseline/F380	2022-02-08 21:21:05.000000000 +0000
@@ -0,0 +1,200 @@
+uCsim, Copyright (C)  Daniel Drotos.
+uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+This is free software, and you are welcome to redistribute it
+under certain conditions; type `show c' for details.
+Type of microcontroller: F380 CMOS cmos
+Controller has 15 hardware element(s).
+   on cpu[0]
+   on simif[0]
+  off vcd[0]
+   on timer0[0]
+   on timer1[1]
+   on uart[0]
+   on dreg[0]
+   on dport[0]
+   on port[0]
+   on port[1]
+   on port[2]
+   on port[3]
+   on irq[0]
+   on timer2[2]
+   on port[4]
+     R0 R1 R2 R3 R4 R5 R6 R7
+     08 70 d4 b2 8a 29 54 48
+@R0 9a .  ACC= 0x00   0 .  B= 0x00
+@R1 84 .  PSW= 0x00 CY=0 AC=0 OV=0 P=0
+SP 0x07 -> 48 54 29 8a b2 d4 70 08
+   DPTR= 0x0000 @DPTR= 0x95 149 .
+0x0000  ? ff       MOV    R7,A[0K
+Memory chips:
+  0x000000-0x0000ff      256 variable_storage (32,%08x,0x%02lx)
+  0x000000-0x00ffff    65536 rom_chip (8,%02x,0x%04lx)
+  0x000000-0x0000ff      256 iram_chip (8,%02x,0x%02lx)
+  0x000000-0x00ffff    65536 xram_chip (8,%02x,0x%04lx)
+  0x000000-0x00007f      128 sfr_0_chip (8,%02x,0x%02lx)
+  0x000000-0x00007f      128 sfr_f_chip (8,%02x,0x%02lx)
+Address spaces:
+  0x000000-0x0000ff      256 variables (32,%08x,0x%02lx)
+  0x000000-0x00ffff    65536 rom (8,%02x,0x%04lx)
+  0x000000-0x0000ff      256 iram (8,%02x,0x%02lx)
+  0x000080-0x0000ff      128 sfr (8,%02x,0x%02lx)
+  0x000000-0x00ffff    65536 xram (8,%02x,0x%04lx)
+  0x000000-0x000007        8 regs (8,%02x,0x%01lx)
+  0x000000-0x0000ff      256 bits (1,%01x,0x%02lx)
+  0x000000-0x000001        2 dptr (8,%02x,0x%01lx)
+Address decoders:
+  variables 0x00 0xff -> variable_storage 0x00 activated
+  rom 0x0000 0xffff -> rom_chip 0x0000 activated
+  iram 0x00 0xff -> iram_chip 0x00 activated
+  sfr 0x80 0x90 -> sfr_0_chip 0x00 activated
+  sfr 0x91 0x95 -> banked
+    bank selector: sfr[0xbf] mask=0xf banks=16 act=0
+    banks:
+      *  0. sfr_0_chip 0x11
+         1. -
+         2. -
+         3. -
+         4. -
+         5. -
+         6. -
+         7. -
+         8. -
+         9. -
+        10. -
+        11. -
+        12. -
+        13. -
+        14. -
+        15. sfr_f_chip 0x11
+  sfr 0x96 0xb8 -> sfr_0_chip 0x16 activated
+  sfr 0xb9 0xb9 -> banked
+    bank selector: sfr[0xbf] mask=0xf banks=16 act=0
+    banks:
+      *  0. sfr_0_chip 0x39
+         1. -
+         2. -
+         3. -
+         4. -
+         5. -
+         6. -
+         7. -
+         8. -
+         9. -
+        10. -
+        11. -
+        12. -
+        13. -
+        14. -
+        15. sfr_f_chip 0x39
+  sfr 0xba 0xbb -> sfr_0_chip 0x3a activated
+  sfr 0xbc 0xbc -> banked
+    bank selector: sfr[0xbf] mask=0xf banks=16 act=0
+    banks:
+      *  0. sfr_0_chip 0x3c
+         1. -
+         2. -
+         3. -
+         4. -
+         5. -
+         6. -
+         7. -
+         8. -
+         9. -
+        10. -
+        11. -
+        12. -
+        13. -
+        14. -
+        15. sfr_f_chip 0x3c
+  sfr 0xbd 0xbf -> sfr_0_chip 0x3d activated
+  sfr 0xc0 0xc2 -> banked
+    bank selector: sfr[0xbf] mask=0xf banks=16 act=0
+    banks:
+      *  0. sfr_0_chip 0x40
+         1. -
+         2. -
+         3. -
+         4. -
+         5. -
+         6. -
+         7. -
+         8. -
+         9. -
+        10. -
+        11. -
+        12. -
+        13. -
+        14. -
+        15. sfr_f_chip 0x40
+  sfr 0xc3 0xc7 -> sfr_0_chip 0x43 activated
+  sfr 0xc8 0xc8 -> banked
+    bank selector: sfr[0xbf] mask=0xf banks=16 act=0
+    banks:
+      *  0. sfr_0_chip 0x48
+         1. -
+         2. -
+         3. -
+         4. -
+         5. -
+         6. -
+         7. -
+         8. -
+         9. -
+        10. -
+        11. -
+        12. -
+        13. -
+        14. -
+        15. sfr_f_chip 0x48
+  sfr 0xc9 0xc9 -> sfr_0_chip 0x49 activated
+  sfr 0xca 0xcf -> banked
+    bank selector: sfr[0xbf] mask=0xf banks=16 act=0
+    banks:
+      *  0. sfr_0_chip 0x4a
+         1. -
+         2. -
+         3. -
+         4. -
+         5. -
+         6. -
+         7. -
+         8. -
+         9. -
+        10. -
+        11. -
+        12. -
+        13. -
+        14. -
+        15. sfr_f_chip 0x4a
+  sfr 0xd0 0xe3 -> sfr_0_chip 0x50 activated
+  sfr 0xe4 0xe4 -> banked
+    bank selector: sfr[0xbf] mask=0xf banks=16 act=0
+    banks:
+      *  0. sfr_0_chip 0x64
+         1. -
+         2. -
+         3. -
+         4. -
+         5. -
+         6. -
+         7. -
+         8. -
+         9. -
+        10. -
+        11. -
+        12. -
+        13. -
+        14. -
+        15. sfr_f_chip 0x64
+  sfr 0xe5 0xff -> sfr_0_chip 0x65 activated
+  xram 0x0000 0xffff -> xram_chip 0x0000 activated
+  regs 0x0 0x7 -> banked
+    bank selector: sfr[0xd0] mask=0x18 banks=4 act=0
+    banks:
+      *  0. iram_chip 0x00
+         1. iram_chip 0x08
+         2. iram_chip 0x10
+         3. iram_chip 0x18
+  bits 0x00 0x7f -> bander(8/1) iram_chip 0x20 activated
+  bits 0x80 0xff -> bander(8/8) sfr_0_chip 0x00 activated
+  dptr 0x0 0x1 -> sfr_0_chip 0x02 activated
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/config/Makefile sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/config/Makefile
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/config/Makefile	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/config/Makefile	2021-03-21 12:01:19.000000000 +0000
@@ -0,0 +1,8 @@
+OUTPUTS = $(filter-out Parameter, $(shell $(SIM) -H | sort -u -k2b | cut -d' ' -f1))
+
+
+$(OUTPUTS):
+	$(call run-sim, -t $(@F) -e 'conf; info reg; info mem')
+
+
+include test-lib.mk
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/hw.h sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/hw.h
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/hw.h	2016-12-31 19:31:10.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/hw.h	1970-01-01 00:00:00.000000000 +0000
@@ -1,47 +0,0 @@
-#ifndef HW_HEADER
-#define HW_HEADER
-
-
-#if defined __SDCC || defined SDCC
-#include 
-#elif defined __C51__
-#include 
-#else /* IAR4 */
-#include 
-#endif
-
-
-#if defined __SDCC || defined SDCC
-#define bit __bit
-#define CODE_PTR(TYPE) __code TYPE *
-#define XRAM_PTR(TYPE) __xdata TYPE *
-#elif defined __C51__
-#define __bit bit
-#define CODE_PTR(TYPE) TYPE code *
-#define XRAM_PTR(TYPE) TYPE xdata *
-#else /* IAR4 */
-#define __bit bit
-#endif
-
-#ifndef FALSE
-#define FALSE 0
-#endif
-#ifndef TRUE
-#define TRUE 1
-#endif
-
-#define XRAM_SIZE (0x1000)
-#define PAGE_SIZE (0x0200)
-#define RESERVED_SPACE (2*PAGE_SIZE)
-
-#define LOADER_START (0xe000)
-#define LOADER_SIZE (0x10000 - LOADER_START)
-
-#define INFO_BLOCK_SIZE (0x0040)
-
-#define BOARD_INFO ((LOADER_START - RESERVED_SPACE - PAGE_SIZE - INFO_BLOCK_SIZE) + LOADER_SIZE)
-
-
-#endif
-
-/* End of hw.h */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/Makefile sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/Makefile
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/Makefile	2019-03-14 11:32:41.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/Makefile	1970-01-01 00:00:00.000000000 +0000
@@ -1,16 +0,0 @@
-PRJ		= test_mdu517 test_mdu88x \
-		  stn stp strr sts stt stxr stxrw stxw \
-		  stt_small stt_large \
-		  monitor test_ser tim_ser
-
-all:
-	for p in $(PRJ); do \
-		$(MAKE) -f $$p.mk clean all ;\
-	done
-
-clean:
-	for p in $(PRJ); do \
-		$(MAKE) -f $$p.mk clean ;\
-	done
-	rm -f *.out *.sout *.tim *.csv *.sim
-	rm -f st*[56][0-9][0-9].cmd st*[56]*.txt
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/Makefile.in sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/Makefile.in
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/Makefile.in	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/Makefile.in	2021-03-28 10:28:14.000000000 +0000
@@ -0,0 +1,9 @@
+# @configure_input@
+
+srcdir           = @abs_srcdir@
+
+abs_top_builddir = @abs_top_builddir@
+abs_top_srcdir   = @abs_top_srcdir@
+
+
+include $(abs_top_srcdir)/test-target.mk
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/mdu/baseline/517 sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/mdu/baseline/517
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/mdu/baseline/517	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/mdu/baseline/517	2022-02-08 21:21:05.000000000 +0000
@@ -0,0 +1,116 @@
+uCsim, Copyright (C)  Daniel Drotos.
+uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+This is free software, and you are welcome to redistribute it
+under certain conditions; type `show c' for details.
+# Test of the 8xC5x7 MDU
+
+# MDU is mapped at sfr 0xe9 to 0xef
+dump sfr 0xe9 0xef
+0xe9                      00 00 00 00 00 00 00 .......
+
+# All cells should have hw operators attached
+memory cell sfr 0xe9
+sfr[0xe9] sfr_0000e9
+cell width=8 mask=ff flags=0
+  decoded to sfr_chip[105]
+Operators:
+memory cell sfr 0xea
+sfr[0xea] sfr_0000ea
+cell width=8 mask=ff flags=0
+  decoded to sfr_chip[106]
+Operators:
+memory cell sfr 0xeb
+sfr[0xeb] sfr_0000eb
+cell width=8 mask=ff flags=0
+  decoded to sfr_chip[107]
+Operators:
+memory cell sfr 0xec
+sfr[0xec] sfr_0000ec
+cell width=8 mask=ff flags=0
+  decoded to sfr_chip[108]
+Operators:
+memory cell sfr 0xed
+sfr[0xed] sfr_0000ed
+cell width=8 mask=ff flags=0
+  decoded to sfr_chip[109]
+Operators:
+memory cell sfr 0xee
+sfr[0xee] sfr_0000ee
+cell width=8 mask=ff flags=0
+  decoded to sfr_chip[110]
+Operators:
+memory cell sfr 0xef
+sfr[0xef] sfr_0000ef
+cell width=8 mask=ff flags=0
+  decoded to sfr_chip[111]
+Operators:
+
+# 0x12345678 / 0x4321 = 0x456c r 0x1f8c
+set mem sfr 0xe9 0x78 0x56 0x34 0x12
+0xe9                      00 00 00 00 ....
+set mem sfr 0xed 0x21 0x43
+0xed                      8c 1f ..
+# Quotient
+dump sfr 0xe9 0xec
+0xe9                      6c 45 00 00 lE..
+# Remainder
+dump sfr 0xed 0xee
+0xed                      8c 1f ..
+
+# 0x8765 / 0x1234 = 0x7 r 0x7f9
+set mem sfr 0xe9 0x65 0x87
+0xe9                      6c 45 lE
+set mem sfr 0xed 0x34 0x12
+0xed                      f9 07 ..
+# Quotient
+dump sfr 0xe9 0xea
+0xe9                      07 00 ..
+# Remainder
+dump sfr 0xed 0xee
+0xed                      f9 07 ..
+
+#  0xdead * 0xbeef
+set mem sfr 0xe9 0xad
+0xe9                      07 .
+set mem sfr 0xed 0xef
+0xed                      f9 .
+set mem sfr 0xea 0xde
+0xea                      00 .
+set mem sfr 0xee 0xbe
+0xee                      be .
+# Product
+dump sfr 0xe9 0xec
+0xe9                      83 49 14 a6 .I..
+
+# 0x87654321 << 1
+set mem sfr 0xe9 0x21 0x43 0x65 0x87
+0xe9                      83 49 14 a6 .I..
+set mem sfr 0xef 0x01
+0xef                      01 .
+dump sfr 0xe9 0xec
+0xe9                      90 a1 b2 43 ...C
+
+# >> 1
+set mem sfr 0xef 0x21
+0xef                      21 !
+dump sfr 0xe9 0xec
+0xe9                      42 86 ca 0e B...
+
+# << 4
+set mem sfr 0xef 0x04
+0xef                      04 .
+dump sfr 0xe9 0xec
+0xe9                      32 54 76 08 2Tv.
+
+# << 8
+set mem sfr 0xef 0x08
+0xef                      08 .
+dump sfr 0xe9 0xec
+0xe9                      43 65 87 00 Ce..
+  00. hw:mdu
+  00. hw:mdu
+  00. hw:mdu
+  00. hw:mdu
+  00. hw:mdu
+  00. hw:mdu
+  00. hw:mdu
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/mdu/Makefile sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/mdu/Makefile
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/mdu/Makefile	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/mdu/Makefile	2021-06-13 15:54:41.000000000 +0000
@@ -0,0 +1,8 @@
+OUTPUTS = 517
+
+
+$(OUTPUTS): %:	test-%.cmd
+	$(call run-sim, -t $@)
+
+
+include test-lib.mk
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/mdu/test-517.cmd sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/mdu/test-517.cmd
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/mdu/test-517.cmd	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/mdu/test-517.cmd	2021-06-13 15:54:41.000000000 +0000
@@ -0,0 +1,54 @@
+# Test of the 8xC5x7 MDU
+
+# MDU is mapped at sfr 0xe9 to 0xef
+dump sfr 0xe9 0xef
+
+# All cells should have hw operators attached
+memory cell sfr 0xe9
+memory cell sfr 0xea
+memory cell sfr 0xeb
+memory cell sfr 0xec
+memory cell sfr 0xed
+memory cell sfr 0xee
+memory cell sfr 0xef
+
+# 0x12345678 / 0x4321 = 0x456c r 0x1f8c
+set mem sfr 0xe9 0x78 0x56 0x34 0x12
+set mem sfr 0xed 0x21 0x43
+# Quotient
+dump sfr 0xe9 0xec
+# Remainder
+dump sfr 0xed 0xee
+
+# 0x8765 / 0x1234 = 0x7 r 0x7f9
+set mem sfr 0xe9 0x65 0x87
+set mem sfr 0xed 0x34 0x12
+# Quotient
+dump sfr 0xe9 0xea
+# Remainder
+dump sfr 0xed 0xee
+
+#  0xdead * 0xbeef
+set mem sfr 0xe9 0xad
+set mem sfr 0xed 0xef
+set mem sfr 0xea 0xde
+set mem sfr 0xee 0xbe
+# Product
+dump sfr 0xe9 0xec
+
+# 0x87654321 << 1
+set mem sfr 0xe9 0x21 0x43 0x65 0x87
+set mem sfr 0xef 0x01
+dump sfr 0xe9 0xec
+
+# >> 1
+set mem sfr 0xef 0x21
+dump sfr 0xe9 0xec
+
+# << 4
+set mem sfr 0xef 0x04
+dump sfr 0xe9 0xec
+
+# << 8
+set mem sfr 0xef 0x08
+dump sfr 0xe9 0xec
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/mdu517.c sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/mdu517.c
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/mdu517.c	2017-01-06 07:36:33.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/mdu517.c	1970-01-01 00:00:00.000000000 +0000
@@ -1,124 +0,0 @@
-#include "c517.h"
-
-#include "mdu517.h"
-
-static uint16_t v;
-static uint32_t d;
-
-uint8_t
-mdu_32udiv16(uint32_t op1, uint16_t op2, uint32_t *res, uint16_t *rem)
-  __reentrant
-{
-  MD0= op1 & 0xff;
-  MD1= (op1 >> 8) & 0xff;
-  MD2= (op1 >> 16) & 0xff;
-  MD3= (op1 >> 24) & 0xff;
-
-  MD4= op2 & 0xff;
-  MD5= (op2 >> 8) & 0xff;
-
-  __asm__ ("nop");
-
-  d= (uint32_t)MD0 + (uint32_t)MD1*256l + (uint32_t)MD2*256l*256l + (uint32_t)MD3*256l*256l*256l;
-  if (res)
-    *res= d;
-  v= MD5*256 + MD4;
-  if (rem)
-    *rem= v;
-
-  return ARCON & 0xc0;
-}
-
-uint8_t
-mdu_16udiv16(uint16_t op1, uint16_t op2, uint16_t *res, uint16_t *rem)
-  __reentrant
-{
-  MD0= op1 & 0xff;
-  MD1= (op1 >> 8) & 0xff;
-  MD4= op2 & 0xff;
-  MD5= (op2 >> 8) & 0xff;
-
-  __asm__ ("nop");
-
-  v= MD1*256 + MD0;
-  if (res)
-    *res= v;
-  v= MD5*256 + MD4;
-  if (rem)
-    *rem= v;
-
-  return ARCON & 0xc0;
-}
-
-uint8_t
-mdu_16umul16(uint16_t op1, uint16_t op2, uint32_t *res)
-  __reentrant
-{
-  MD0= op1 & 0xff;
-  MD4= op2 & 0xff;
-  MD1= (op1 >> 8) & 0xff;
-  MD5= (op2 >> 8) & 0xff;
-
-  __asm__ ("nop");
-
-  d= (uint32_t)MD0 + (uint32_t)MD1*256l + (uint32_t)MD2*256l*256l + (uint32_t)MD3*256l*256l*256l;
-  if (res)
-    *res= d;
-
-  return ARCON & 0x80;
-}
-
-uint8_t
-mdu_norm(uint32_t op, uint32_t *res, uint8_t *nuof_shifts)
-  __reentrant
-{
-  uint8_t a;
-  
-  MD0= op & 0xff;
-  MD1= (op >> 8) & 0xff;
-  MD2= (op >> 16) & 0xff;
-  MD3= (op >> 24) & 0xff;
-  ARCON= 0;
-  
-  __asm__ ("nop");
-
-  d= (uint32_t)MD0 + (uint32_t)MD1*256l + (uint32_t)MD2*256l*256l + (uint32_t)MD3*256l*256l*256l;
-  if (res)
-    *res= d;
-  a= ARCON;
-  if (nuof_shifts)
-    *nuof_shifts= a & 0x1f;
-  return a & 0xc0;
-}
-
-uint8_t
-mdu_lshift(uint32_t op, uint8_t shifts, uint8_t right, uint32_t *res)
-  __reentrant
-{
-  MD0= op & 0xff;
-  MD1= (op >> 8) & 0xff;
-  MD2= (op >> 16) & 0xff;
-  MD3= (op >> 24) & 0xff;
-  ARCON= (right?0x20:0) + (shifts&0x1f);
-  
-  __asm__ ("nop");
-
-  d= (uint32_t)MD0 + (uint32_t)MD1*256l + (uint32_t)MD2*256l*256l + (uint32_t)MD3*256l*256l*256l;
-  if (res)
-    *res= d;
-  return ARCON & 0x80;
-}
-
-uint8_t
-mdu_lshift_left(uint32_t op, uint8_t shifts, uint32_t *res)
-  __reentrant
-{
-  return mdu_lshift(op, shifts, 0, res);
-}
-
-uint8_t
-mdu_lshift_right(uint32_t op, uint8_t shifts, uint32_t *res)
-  __reentrant
-{
-  return mdu_lshift(op, shifts, 1, res);
-}
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/mdu517.h sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/mdu517.h
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/mdu517.h	2017-01-06 07:36:33.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/mdu517.h	1970-01-01 00:00:00.000000000 +0000
@@ -1,28 +0,0 @@
-#ifndef MDU517_HEADER
-#define MDU517_HEADER
-
-#include 
-
-extern uint8_t mdu_32udiv16(uint32_t op1, uint16_t op2,
-			    uint32_t *res, uint16_t *rem)
-  __reentrant;
-extern uint8_t mdu_16udiv16(uint16_t op1, uint16_t op2,
-			    uint16_t *res, uint16_t *rem)
-    __reentrant;
-extern uint8_t mdu_16umul16(uint16_t op1, uint16_t op2,
-			    uint32_t *res)
-    __reentrant;
-extern uint8_t mdu_norm(uint32_t op,
-			uint32_t *res, uint8_t *nuof_shifts)
-    __reentrant;
-extern uint8_t mdu_lshift(uint32_t op, uint8_t shifts, uint8_t right,
-			  uint32_t *res)
-    __reentrant;
-extern uint8_t mdu_lshift_left(uint32_t op, uint8_t shifts,
-			       uint32_t *res)
-    __reentrant;
-extern uint8_t mdu_lshift_right(uint32_t op, uint8_t shifts,
-				uint32_t *res)
-    __reentrant;
-
-#endif
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/mdu88x.c sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/mdu88x.c
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/mdu88x.c	2017-01-06 07:36:33.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/mdu88x.c	1970-01-01 00:00:00.000000000 +0000
@@ -1,234 +0,0 @@
-#include "xc88x.h"
-
-#include "mdu88x.h"
-
-static uint16_t v;
-static uint32_t d;
-
-/* unsigned OPs */
-
-uint8_t
-mdu_32udiv16(uint32_t op1, uint16_t op2, uint32_t *res, uint16_t *rem)
-  __reentrant
-{
-  MD0= op1 & 0xff;
-  MD1= (op1 >> 8) & 0xff;
-  MD2= (op1 >> 16) & 0xff;
-  MD3= (op1 >> 24) & 0xff;
-
-  MD4= op2 & 0xff;
-  MD5= (op2 >> 8) & 0xff;
-
-  MDUCON= 0x10 + 0x02;
-  while (MDUSTAT & 0x04) ;
-  
-  d= (uint32_t)MD0 + (uint32_t)MD1*256l + (uint32_t)MD2*256l*256l + (uint32_t)MD3*256l*256l*256l;
-  if (res)
-    *res= d;
-  v= MD5*256 + MD4;
-  if (rem)
-    *rem= v;
-
-  return MDUSTAT & 0x02;
-}
-
-uint8_t
-mdu_16udiv16(uint16_t op1, uint16_t op2, uint16_t *res, uint16_t *rem)
-  __reentrant
-{
-  MD0= op1 & 0xff;
-  MD1= (op1 >> 8) & 0xff;
-  MD4= op2 & 0xff;
-  MD5= (op2 >> 8) & 0xff;
-
-  MDUCON= 0x10 + 0x01;
-  while (MDUSTAT & 0x04) ;
-  
-  v= MD1*256 + MD0;
-  if (res)
-    *res= v;
-  v= MD5*256 + MD4;
-  if (rem)
-    *rem= v;
-
-  return MDUSTAT & 0x02;
-}
-
-uint8_t
-mdu_16umul16(uint16_t op1, uint16_t op2, uint32_t *res)
-  __reentrant
-{
-  MD0= op1 & 0xff;
-  MD4= op2 & 0xff;
-  MD1= (op1 >> 8) & 0xff;
-  MD5= (op2 >> 8) & 0xff;
-
-  MDUCON= 0x10 + 0x00;
-  while (MDUSTAT & 0x04) ;
-  
-  d= (uint32_t)MD0 + (uint32_t)MD1*256l + (uint32_t)MD2*256l*256l + (uint32_t)MD3*256l*256l*256l;
-  if (res)
-    *res= d;
-
-  return MDUSTAT & 0x02;
-}
-
-/* signed OPs */
-
-uint8_t
-mdu_32sdiv16(int32_t op1, int16_t op2, int32_t *res, int16_t *rem)
-  __reentrant
-{
-  MD0= op1 & 0xff;
-  MD1= (op1 >> 8) & 0xff;
-  MD2= (op1 >> 16) & 0xff;
-  MD3= (op1 >> 24) & 0xff;
-
-  MD4= op2 & 0xff;
-  MD5= (op2 >> 8) & 0xff;
-
-  MDUCON= 0x10 + 0x06;
-  while (MDUSTAT & 0x04) ;
-  
-  d= (uint32_t)MD0 + (uint32_t)MD1*256l + (uint32_t)MD2*256l*256l + (uint32_t)MD3*256l*256l*256l;
-  if (res)
-    *res= d;
-  v= MD5*256 + MD4;
-  if (rem)
-    *rem= v;
-
-  return MDUSTAT & 0x02;
-}
-
-uint8_t
-mdu_16sdiv16(int16_t op1, int16_t op2, int16_t *res, int16_t *rem)
-  __reentrant
-{
-  MD0= op1 & 0xff;
-  MD1= (op1 >> 8) & 0xff;
-  MD4= op2 & 0xff;
-  MD5= (op2 >> 8) & 0xff;
-
-  MDUCON= 0x10 + 0x05;
-  while (MDUSTAT & 0x04) ;
-  
-  v= MD1*256 + MD0;
-  if (res)
-    *res= v;
-  v= MD5*256 + MD4;
-  if (rem)
-    *rem= v;
-
-  return MDUSTAT & 0x02;
-}
-
-uint8_t
-mdu_16smul16(int16_t op1, int16_t op2, int32_t *res)
-  __reentrant
-{
-  MD0= op1 & 0xff;
-  MD4= op2 & 0xff;
-  MD1= (op1 >> 8) & 0xff;
-  MD5= (op2 >> 8) & 0xff;
-
-  MDUCON= 0x10 + 0x04;
-  while (MDUSTAT & 0x04) ;
-  
-  d= (uint32_t)MD0 + (uint32_t)MD1*256l + (uint32_t)MD2*256l*256l + (uint32_t)MD3*256l*256l*256l;
-  if (res)
-    *res= d;
-
-  return MDUSTAT & 0x02;
-}
-
-/* normalize */
-
-uint8_t
-mdu_norm(uint32_t op, uint32_t *res, uint8_t *nuof_shifts)
-  __reentrant
-{
-  MD0= op & 0xff;
-  MD1= (op >> 8) & 0xff;
-  MD2= (op >> 16) & 0xff;
-  MD3= (op >> 24) & 0xff;
-  
-  MDUCON= 0x10 + 0x08;
-  while (MDUSTAT & 0x04) ;
-
-  d= (uint32_t)MD0 + (uint32_t)MD1*256l + (uint32_t)MD2*256l*256l + (uint32_t)MD3*256l*256l*256l;
-  if (res)
-    *res= d;
-  if (nuof_shifts)
-    *nuof_shifts= MD4 & 0x1f;
-  return MDUSTAT & 0x02;
-}
-
-/* logical shifts */
-
-uint8_t
-mdu_lshift(uint32_t op, uint8_t shifts, uint8_t right, uint32_t *res)
-  __reentrant
-{
-  MD0= op & 0xff;
-  MD1= (op >> 8) & 0xff;
-  MD2= (op >> 16) & 0xff;
-  MD3= (op >> 24) & 0xff;
-  MD4= (right?0x20:0) + (shifts&0x1f);
-  
-  MDUCON= 0x10 + 0x03;
-  while (MDUSTAT & 0x04) ;
-
-  d= (uint32_t)MD0 + (uint32_t)MD1*256l + (uint32_t)MD2*256l*256l + (uint32_t)MD3*256l*256l*256l;
-  if (res)
-    *res= d;
-  return MDUSTAT & 0x02;
-}
-
-uint8_t
-mdu_lshift_left(uint32_t op, uint8_t shifts, uint32_t *res)
-  __reentrant
-{
-  return mdu_lshift(op, shifts, 0, res);
-}
-
-uint8_t
-mdu_lshift_right(uint32_t op, uint8_t shifts, uint32_t *res)
-  __reentrant
-{
-  return mdu_lshift(op, shifts, 1, res);
-}
-
-/* arithmetic shifts */
-
-uint8_t
-mdu_ashift(int32_t op, int8_t shifts, int8_t right, int32_t *res)
-  __reentrant
-{
-  MD0= op & 0xff;
-  MD1= (op >> 8) & 0xff;
-  MD2= (op >> 16) & 0xff;
-  MD3= (op >> 24) & 0xff;
-  MD4= (right?0x20:0) + (shifts&0x1f);
-  
-  MDUCON= 0x10 + 0x07;
-  while (MDUSTAT & 0x04) ;
-
-  d= (uint32_t)MD0 + (uint32_t)MD1*256l + (uint32_t)MD2*256l*256l + (uint32_t)MD3*256l*256l*256l;
-  if (res)
-    *res= d;
-  return MDUSTAT & 0x02;
-}
-
-uint8_t
-mdu_ashift_left(int32_t op, int8_t shifts, int32_t *res)
-  __reentrant
-{
-  return mdu_lshift(op, shifts, 0, res);
-}
-
-uint8_t
-mdu_ashift_right(int32_t op, int8_t shifts, int32_t *res)
-  __reentrant
-{
-  return mdu_lshift(op, shifts, 1, res);
-}
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/mdu88x.h sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/mdu88x.h
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/mdu88x.h	2017-01-06 07:36:33.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/mdu88x.h	1970-01-01 00:00:00.000000000 +0000
@@ -1,60 +0,0 @@
-#ifndef MDU88X_HEADER
-#define MDU88X_HEADER
-
-#include 
-
-/* unsigned OPs */
-
-extern uint8_t mdu_32udiv16(uint32_t op1, uint16_t op2,
-			    uint32_t *res, uint16_t *rem)
-  __reentrant;
-extern uint8_t mdu_16udiv16(uint16_t op1, uint16_t op2,
-			    uint16_t *res, uint16_t *rem)
-    __reentrant;
-extern uint8_t mdu_16umul16(uint16_t op1, uint16_t op2,
-			    uint32_t *res)
-    __reentrant;
-
-/* signed OPs */
-
-extern uint8_t mdu_32sdiv16(int32_t op1, int16_t op2,
-			    int32_t *res, int16_t *rem)
-  __reentrant;
-extern uint8_t mdu_16sdiv16(int16_t op1, int16_t op2,
-			    int16_t *res, int16_t *rem)
-    __reentrant;
-extern uint8_t mdu_16smul16(int16_t op1, int16_t op2,
-			    int32_t *res)
-    __reentrant;
-
-/* normalize */
-
-extern uint8_t mdu_norm(uint32_t op,
-			uint32_t *res, uint8_t *nuof_shifts)
-    __reentrant;
-
-/* logical shifts */
-
-extern uint8_t mdu_lshift(uint32_t op, uint8_t shifts, uint8_t right,
-			  uint32_t *res)
-    __reentrant;
-extern uint8_t mdu_lshift_left(uint32_t op, uint8_t shifts,
-			       uint32_t *res)
-    __reentrant;
-extern uint8_t mdu_lshift_right(uint32_t op, uint8_t shifts,
-				uint32_t *res)
-    __reentrant;
-
-/* arithmetic shifts */
-
-extern uint8_t mdu_ashift(int32_t op, int8_t shifts, int8_t right,
-			  int32_t *res)
-    __reentrant;
-extern uint8_t mdu_ashift_left(int32_t op, int8_t shifts,
-			       int32_t *res)
-    __reentrant;
-extern uint8_t mdu_ashift_right(int32_t op, int8_t shifts,
-				int32_t *res)
-    __reentrant;
-
-#endif
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/monitor.c sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/monitor.c
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/monitor.c	2019-01-07 14:30:39.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/monitor.c	1970-01-01 00:00:00.000000000 +0000
@@ -1,65 +0,0 @@
-#include 
-#include "hw.h"
-
-#include "serial.h"
-#include "print.h"
-
-__xdata char *simif;
-
-int cnt;
-
-void process(char *cmd)
-{
-  if (strstr(cmd, "test") == cmd)
-    {
-      cnt++;
-      print_c('_');print(cmd);print_c('_');
-      print_f("This is a test %d\n", cnt);
-    }
-  else if (strstr(cmd, "dump") == cmd)
-    {
-      int i;
-      print_c('_');print(cmd);print_c('_');
-      for (i= 0; i<100; i++)
-	{
-	  print_cx(i);
-	  print(" ");
-	}
-      print("\n----\n");
-    }
-  else
-    {
-      print("Unknown command: \"");print(cmd);print("\"\n");
-    }
-}
-
-__xdata char cmd[40];
-char ptr;
-
-void main(void)
-{
-  simif= (__xdata char *)0xffff;
-  serial_init(9600);
-  cmd[ptr=0]= 0;
-  print("Hello World!\n");
-  P1= 0;
-  while (1)
-    {
-      if (serial_received())
-	{
-	  char c= serial_receive();
-	  if ((c == '\n') ||
-	      (c == '\r'))
-	    {
-	      process(cmd);
-	      cmd[ptr=0]= 0;
-	    }
-	  else if (ptr < 39)
-	    {
-	      cmd[ptr++]= c;
-	      cmd[ptr]= 0;
-	      print("cmd=");print(cmd);print_c('\n');
-	    }
-	}
-    }
-}
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/monitor.mk sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/monitor.mk
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/monitor.mk	2018-12-18 08:22:48.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/monitor.mk	1970-01-01 00:00:00.000000000 +0000
@@ -1,7 +0,0 @@
-MAIN		= monitor
-
-OTHERS		= serial print
-
-include sdcc.mk
-
-MODEL		= small
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/print.c sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/print.c
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/print.c	2017-01-06 07:36:33.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/print.c	1970-01-01 00:00:00.000000000 +0000
@@ -1,189 +0,0 @@
-#if defined __SDCC || defined SDCC
-#include 
-#elif defined __C51__
-#include 
-#endif
-
-#include "print.h"
-
-void
-print(char *s) __reentrant
-{
-  if (s)
-    for (; *s; putchar(*s++)) ;
-}
-
-void
-print_form(char *s, long l, void *p) __reentrant
-{
-  if (s)
-    for (; *s; s++)
-      if (*s != '%')
-	putchar(*s);
-      else
-	{
-	  s++;
-	  if (*s)
-	    switch (*s)
-	      {
-	      case 'u': print_u(l); break;
-	      case 'd': print_d(l); break;
-	      case 'p': print_p(p); break;
-	      case 'x': print_x(l); break;
-	      case '2': print_cx(l); break;
-	      case '4': print_lx(l); break;
-	      }
-	}
-}
-
-/* signed integer in decimal */
-
-void
-print_d(long i) __reentrant
-{
-  long x= 1000000000;
-  char in= 0;
-  if (i<0)
-    {
-      putchar('-');
-      i= -i;
-    }
-  while (x)
-    {
-      int j= i/x;
-      if (in || j || (x==1))
-	putchar(j+'0');
-      in= in || j;
-      i%= x;
-      x/= 10;
-    }
-}
-
-
-/* unsigned integer in decimal */
-
-void
-print_u(unsigned int i) __reentrant
-{
-  int x= 10000;
-  while (x)
-    {
-      int j= i/x;
-      putchar(j+'0');
-      i%= x;
-      x/= 10;
-    }
-}
-
-
-/* unsigned int in hex */
-
-void
-print_cx(unsigned char i)
-{
-  putchar((i/16)+(((i/16)<10)?'0':('A'-10)));
-  putchar((i&15)+(((i&15)<10)?'0':('A'-10)));
-}
-
-void
-print_x(unsigned int i) __reentrant
-{
-/*
-  unsigned char j;
-  for (j= 0; j<4; j++)
-    {
-      char v= (i&0xf000)>>12;
-      putchar(v+((v<10)?'0':('A'-10)));
-      i<<= 4;
-    }
-*/
-  print_cx(i/256);
-  print_cx(i&0xff);
-}
-
-void
-print_lx(unsigned long i) __reentrant
-{
-  print_x(i >> 16);
-  print_x(i & 0xffff);
-}
-
-void
-print_p(void *p) __reentrant
-{
-  unsigned char t= ((long)p)/0x10000;
-  if (t>=0x80)
-    putchar('C');
-  else if (t>=0x60)
-    putchar('P');
-  else if (t>=0x40)
-    putchar('I');
-  else
-    putchar('X');
-  putchar(':');
-  print_x(((long)p)&0xffff);
-}
-
-
-void
-print_c(char c)
-{
-  putchar(c);
-}
-
-
-void
-term_cls()
-{
-  print("\033[2J");
-}
-
-
-void
-term_xy(char x1, char y1)
-{
-  putchar('\033');
-  putchar('[');
-  print_u(y1);
-  putchar(';');
-  print_u(x1);
-  putchar('H');
-}
-
-
-void
-term_save()
-{
-  print("\033[s");
-}
-
-
-void
-term_restore()
-{
-  print("\033[u");
-}
-
-
-void
-term_hide()
-{
-  print("\033[?25l");
-}
-
-
-void
-term_show()
-{
-  print("\033[?25h");
-}
-
-
-void
-term_color(int bg, int fg) __reentrant
-{
-  if (bg >= 0)
-    print_form("\033[%um", bg+40, NULL);
-  if (fg >= 0)
-    print_form("\033[%um", fg+30, NULL);
-}
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/print.h sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/print.h
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/print.h	2017-01-06 07:36:33.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/print.h	1970-01-01 00:00:00.000000000 +0000
@@ -1,26 +0,0 @@
-#ifndef PRINT_HEADER
-#define PRINT_HEADER
-
-
-extern void print(char *s) __reentrant;
-extern void print_form(char *s, long l, void *p) __reentrant;
-#define print_f(A,B) print_form((A),(B),0)
-#define print_fp(A,B) print_form((A),0,(B))
-extern void print_d(long i) __reentrant;
-extern void print_u(unsigned int i) __reentrant;
-extern void print_cx(unsigned char i);
-extern void print_x(unsigned int i) __reentrant;
-extern void print_lx(unsigned long i) __reentrant;
-extern void print_p(void *p) __reentrant;
-extern void print_c(char c);
-
-extern void term_cls();
-extern void term_xy(char x1, char y1);
-extern void term_save();
-extern void term_restore();
-extern void term_hide();
-extern void term_show();
-extern void term_color(int bg, int fg) __reentrant;
-
-  
-#endif
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/run.cmd sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/run.cmd
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/run.cmd	2016-12-31 19:31:10.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/run.cmd	1970-01-01 00:00:00.000000000 +0000
@@ -1,2 +0,0 @@
-run
-state
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/run.sh sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/run.sh
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/run.sh	2017-02-24 11:48:49.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/run.sh	1970-01-01 00:00:00.000000000 +0000
@@ -1,30 +0,0 @@
-PRJ=$1
-
-if [ -z "$PRJ" ]; then
-   PRJ=test_mdu88x
-fi
-
-if [ -f ${PRJ}.ihx ]; then
-    if [ -f ${PRJ}_conf.cmd ]; then
-	CONF="-C ${PRJ}_conf.cmd"
-    elif [ -f conf.cmd ]; then
-	CONF="-C conf.cmd"
-    else
-	CONF=""
-    fi
-    if [ -f ${PRJ}.type ]; then
-	TYPE="-t $(cat ${PRJ}.type)"
-    else
-	TYPE="-t 52"
-    fi
-    if [ -f ${PRJ}.cmd ]; then
-	CMD="../s51 ${TYPE} ${CONF} -S in=/dev/null,out=${PRJ}.out ${PRJ}.ihx"
-	echo $CMD
-	$CMD <${PRJ}.cmd | tee ${PRJ}.sim
-    else
-	CMD="../s51 ${TYPE} ${CONF} -Z6666 -S in=/dev/null,out=${PRJ}.out -G ${PRJ}.ihx"
-	echo $CMD
-	$CMD|tee ${PRJ}.sim
-    fi
-    cat ${PRJ}.out
-fi
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/sdcc.mk sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/sdcc.mk
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/sdcc.mk	2017-03-24 14:15:01.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/sdcc.mk	1970-01-01 00:00:00.000000000 +0000
@@ -1,46 +0,0 @@
-CC		= sdcc 
-
-MODEL		= large
-CPPFLAGS	=
-CFLAGS		= --debug --model-$(MODEL)
-LDFLAGS		=
-LIBS		=
-
-ALL		= $(MAIN) $(OTHERS)
-OBJECTS		= $(MAIN).rel $(OTHERS:=.rel)
-
-APP		?= $(MAIN)
-
-all: $(APP).hex
-
-dep: $(APP).dep
-
-$(APP).dep: $(OBJECTS:.rel=.c) *.h
-	@>$(APP).dep
-	@for c in $(OBJECTS:.rel=.c); do \
-		$(CC) -MM $(CPPFALGS) $$c >>$(APP).dep ;\
-	done
-
-include $(APP).dep
-
-$(APP).ihx: $(OBJECTS)
-	$(CC) $(CFLAGS) $(LDFLAGS) $(OBJECTS) -o $@
-
-.SUFFIXES: .rel .ihx .hex
-
-.c.rel:
-	$(CC) -c $(CPPFLAGS) $(CFLAGS) $<
-
-.ihx.hex:
-	packihx $< >$@
-
-clean:
-	rm -f $(ALL:=.rel) $(ALL:=.asm) $(ALL:=.lst) $(ALL:=.rst) $(ALL:=.sym) $(ALL:=.adb)
-	rm -f $(MAIN).ihx $(MAIN).hex $(MAIN).lk $(MAIN).map $(MAIN).mem $(MAIN).cdb $(MAIN).omf $(MAIN).noi
-	rm -f $(APP).ihx $(APP).hex $(APP).lk $(APP).map $(APP).mem $(APP).cdb $(APP).omf $(APP).noi
-	rm -f *~
-	rm -f $(MAIN).dep $(APP).dep
-	rm -f $(MAIN).sim $(APP).sim
-
-
-# End of sdcc.mk
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/serial.c sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/serial.c
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/serial.c	2019-01-07 14:30:39.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/serial.c	1970-01-01 00:00:00.000000000 +0000
@@ -1,216 +0,0 @@
-#include "hw.h"
-
-#if defined __SDCC || defined SDCC
-#elif defined __C51__
-
-#else /* IAR4 */
-#include 
-#endif
-
-#include "serial.h"
-
-extern __xdata char *simif;
-
-volatile unsigned char serial_buffer[SERIAL_BUFFER_SIZE];
-volatile unsigned char first_occupied, first_free;
-volatile bit serial_sent;
-
-unsigned char
-serial_nuof_received()
-{
-  if (first_free == first_occupied)
-    return 0;
-  else if (first_free > first_occupied)
-    return first_free - first_occupied;
-  else
-    return SERIAL_BUFFER_SIZE - (first_occupied - first_free);
-}
-
-/* Serial line ISR puts received chars into a ring buffer */
-
-#if defined __SDCC || defined SDCC
-void serial_isr(void) __interrupt (4)
-#elif defined __C51__
-void serial_isr(void) interrupt 4
-#else /* IAR4 */
-interrupt void SCON_int(void)
-#endif
-{
-  if (RI)
-    {
-      unsigned char c;
-      unsigned char new, nr;
-      c= SBUF;
-      new= first_free+1;
-      new= new % SERIAL_BUFFER_SIZE;
-      *simif= 'p';*simif= '|';
-      *simif= 'p';*simif= c;
-      *simif= 'p';*simif= '|';
-      if (new != first_occupied)
-	{
-	  serial_buffer[first_free]= c;
-	  first_free= new;
-	}
-      else
-	{
-	  *simif= 'p';*simif= '*';
-	  *simif= 'p';*simif= c;
-	  *simif= 'p';*simif= '*';
-	  P1++;
-	}
-      nr= serial_nuof_received();
-      *simif= 'p';*simif= '/';
-      *simif= 'p';*simif= nr+'0';
-      *simif= 'p';*simif= '/';
-      RI= 0;
-      P0= first_free<<4 + first_occupied;
-    }
-  else if (TI)
-    {
-      serial_sent= 1;
-      TI= 0;
-    }
-}
-
-
-#if defined __SDCC || defined SDCC
-static __sfr __at(0x97) s97;
-#elif defined __C51__
-static sfr s97= 0x97;
-#endif
-
-/* Initialization of serial line */
-
-void
-serial_init(long int br)
-{
-  /* Set  variables */
-  first_free= first_occupied= 0;
-  if (!(serial_sent= 1))
-    serial_dummy();
-  
-  /* Set USART mode: 8 bit variable speed */
-  SCON= 0x40;
-  ES= 1;
-  REN= 1;
-
-  s97= 0xf0;
-  s97= 0x55;
-  if (s97 == 0x55)
-    {
-      beallitas();
-      return;
-    }
-
-  /* Set Timer2 as baudrate generator, XTAL=11.0592MHz */
-  C_T2= 0;
-  CP_RL2= 0;
-  {
-    long int l= (3*115200)/br;
-    TL2= RCAP2L= (65536-l)&0xff; /* 3=115200,6=57600,9=38400,18=19200,36=9600 */
-    TH2= RCAP2H= (65536-l)/256;
-  }
-  RCLK= 1;
-  TCLK= 1;
-  TR2= 1;
-
-  /* Start */
-  EA= 1; /* Enable interrupts */
-}
-
-
-void
-beallitas(void)
-{
-  /* Valtozok beallitasa */
-  if (first_occupied= 0)
-    ;/*serial_dummy();*/
-  first_free= 0;
-  serial_sent= 1;
-
-  /* Timer1 beallitasa 9600 baud-os sebesseg generalasahoz */
-  TMOD= (TMOD & 0x0f) | 0x20;
-  TH1= 0xfd;
-  TL1= 0xfd;
-  PCON&= 0x7f; /* SMOD=0 */
-  ET1= 0;
-  
-  /* Soros vonal beallitasa, 8 bites valtoztathato sebessegu mod */
-  SCON= 0x40;
-  ES= 1;
-  REN= 1;
-  
-  /* Start */
-  TR1= 1;	/* Idozito indul */
-  EA= 1;	/* Megszakitasok engedelyezese */
-}
-
-
-/************************************************** Low level line handling */
-
-/* Blocking send */
-
-unsigned char
-serial_send(unsigned char c)
-{
-  while (!serial_sent) ;
-  SBUF= c;
-  serial_sent= 0;
-  return c;
-}
-
-void
-putchar(char c)
-{
-  serial_send(c);
-}
-
-
-/* Check for recived chars */
-
-unsigned char
-serial_received(void)
-{
-  return first_free != first_occupied;
-}
-
-
-/* Blocking receive */
-
-unsigned char
-serial_receive(void)
-{
-  unsigned char c, nr;
-  
-  while (!serial_received()) ;
-  ES= 0;
-  c= serial_buffer[first_occupied++];
-  first_occupied%= SERIAL_BUFFER_SIZE;
-  nr= serial_nuof_received();
-  *simif= 'p';*simif= '@';
-  *simif= 'p';*simif= nr+'0';
-  *simif= 'p';*simif= '@';
-  ES= 1;
-  return c;
-}
-
-char
-getchar(void)
-{
-  return serial_send(serial_receive());
-}
-
-
-void
-serial_dummy(void)
-{
-  serial_init(0);
-  beallitas();
-  serial_send(0);
-  serial_received();
-  putchar(0);
-  getchar();
-}
-
-
-/* End of serial.c */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/serial.h sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/serial.h
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/serial.h	2018-12-18 08:22:48.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/serial.h	1970-01-01 00:00:00.000000000 +0000
@@ -1,32 +0,0 @@
-#ifndef SERIAL_HEADER
-#define SERIAL_HEADER
-
-
-#define SERIAL_BUFFER_SIZE 8
-
-#if defined __SDCC || defined SDCC
-extern void serial_isr(void) __interrupt(4);
-#elif defined __C51__
-extern void serial_isr(void);
-#else /* IAR4 */
-interrupt void SCON_int(void);
-#endif
-
-extern void serial_init(long int br);
-extern void beallitas(void);
-
-extern unsigned char serial_send(unsigned char c);
-extern unsigned char serial_received(void);
-extern unsigned char serial_receive(void);
-extern unsigned char serial_nuof_received();
-
-#define kikuld(c) serial_send(c)
-#define vetel_volt() serial_received()
-#define vett() serial_receive()
-
-extern void serial_dummy(void);
-
-
-#endif
-
-/* End of serial.h */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/st.cmd sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/st.cmd
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/st.cmd	2017-03-12 13:28:55.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/st.cmd	1970-01-01 00:00:00.000000000 +0000
@@ -1,4 +0,0 @@
-break xram r 0xfffe
-run
-state
-quit
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/stest.sh sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/stest.sh
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/stest.sh	2019-03-14 11:32:41.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/stest.sh	1970-01-01 00:00:00.000000000 +0000
@@ -1,51 +0,0 @@
-VERS="504 505 606 610 615 620 625 645"
-
-TESTS=$(cat st_list.txt)
-
-rm -f *.csv
-echo -n "versions " >st_e.csv
-echo -n "versions " >st_st.csv
-echo -n "versions " >st_s.csv
-for v in $VERS; do
-    echo -n ", v${v}" >>st_e.csv
-    echo -n ", v${v}" >>st_st.csv
-    echo -n ", v${v}" >>st_s.csv
-done
-echo >>st_e.csv
-echo >>st_st.csv
-echo >>st_s.csv
-
-for t in $TESTS; do
-    for v in $VERS; do
-	make -f st${t}.mk clean all
-	./st.sh -v $v $t
-    done
-
-    (
-	echo -n "st${t} "
-	for v in $VERS; do
-	     echo -n ", $(cat st${t}${v}_e.txt) "
-	done
-	echo
-    ) >st${t}_e.csv
-    cat st${t}_e.csv >>st_e.csv
-    
-    (
-	echo -n "st${t} "
-	for v in $VERS; do
-	     echo -n ", $(cat st${t}${v}_st.txt) "
-	done
-	echo
-    ) >st${t}_st.csv
-    cat st${t}_st.csv >>st_st.csv
-    
-    (
-	echo -n "st${t} "
-	for v in $VERS; do
-	     echo -n ", $(cat st${t}${v}_s.txt) "
-	done
-	echo
-    ) >st${t}_s.csv
-    cat st${t}_s.csv >>st_s.csv
-
-done
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/st_list.txt sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/st_list.txt
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/st_list.txt	2017-03-12 13:28:55.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/st_list.txt	1970-01-01 00:00:00.000000000 +0000
@@ -1,8 +0,0 @@
-n
-p
-rr
-s
-t
-xr
-xrw
-xw
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/stn.c sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/stn.c
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/stn.c	2017-03-12 13:28:55.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/stn.c	1970-01-01 00:00:00.000000000 +0000
@@ -1,35 +0,0 @@
-char c1;
-char *ptr1_data;
-char *ptr2_idata;
-char *ptr3_pdata;
-char *ptr4_xdata;
-char *ptr5_code;
-char c2;
-
-unsigned char __xdata * volatile sif;
-
-void
-main(void)
-{
-  volatile unsigned int i, j;
-  volatile __xdata int xi;
-  volatile int __xdata xii;
-  
-  sif= (unsigned char __xdata *)0xffff;
-  xi= 1;
-  xii= 2;
-  c1= 'A';
-  c2= 'B';
-  
-  for (j= 0; j<10; j++)
-    for (i= 0; i<0xfff0; i++)
-      {
-	ptr1_data = (__data  char *)(0x1122); // 22 00 40
-	ptr2_idata= (__idata char *)(0x3344); // 44 00 40
-	ptr3_pdata= (__pdata char *)(0x5566); // 66 00 60
-	ptr4_xdata= (__xdata char *)(0x7788); // 88 77 00
-	ptr5_code = (__code  char *)(0x99aa); // aa 99 80
-      }
-  * (char __idata *) 0 = * (char __xdata *) 0xfffe;
-  *sif= 's';
-}
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/stn.mk sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/stn.mk
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/stn.mk	2017-03-12 13:28:55.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/stn.mk	1970-01-01 00:00:00.000000000 +0000
@@ -1,5 +0,0 @@
-MAIN		= stn
-
-include sdcc.mk
-
-MODEL		= small
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/stp.c sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/stp.c
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/stp.c	2017-03-12 13:28:55.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/stp.c	1970-01-01 00:00:00.000000000 +0000
@@ -1,20 +0,0 @@
-#include "hw.h"
-
-unsigned char __xdata * volatile sif;
-
-void
-main(void)
-{
-  volatile unsigned int i, j;
-  sif= (unsigned char __xdata *)0xffff;
-  for (j= 0; j<10; j++)
-    for (i= 0; i<0xfff0; i++)
-      {
-	P0= P1+1;
-	P1++;
-	P2= P3+1;
-	P3++;
-      }
-  * (char __idata *) 0 = * (char __xdata *) 0xfffe;
-  *sif= 's';
-}
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/stp.mk sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/stp.mk
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/stp.mk	2017-03-12 13:28:55.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/stp.mk	1970-01-01 00:00:00.000000000 +0000
@@ -1,5 +0,0 @@
-MAIN		= stp
-
-include sdcc.mk
-
-MODEL		= small
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/strr.c sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/strr.c
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/strr.c	2017-03-12 13:28:55.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/strr.c	1970-01-01 00:00:00.000000000 +0000
@@ -1,16 +0,0 @@
-
-unsigned char __xdata * volatile sif;
-
-void
-main(void)
-{
-  volatile unsigned int i, j, x;
-  __code char *p= (__code char *)0;
-
-  sif= (unsigned char __xdata *)0xffff;
-  for (j= 0; j<10; j++)
-    for (i= 0; i<0xfff0; i++)
-      x= p[i];
-  * (char __idata *) 0 = * (char __xdata *) 0xfffe;
-  *sif= 's';
-}
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/strr.mk sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/strr.mk
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/strr.mk	2017-03-12 13:28:55.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/strr.mk	1970-01-01 00:00:00.000000000 +0000
@@ -1,5 +0,0 @@
-MAIN		= strr
-
-include sdcc.mk
-
-MODEL		= small
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/sts.c sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/sts.c
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/sts.c	2017-03-12 13:28:55.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/sts.c	1970-01-01 00:00:00.000000000 +0000
@@ -1,22 +0,0 @@
-#include 
-#include "serial.h"
-#include "print.h"
-
-unsigned char __xdata * volatile sif;
-
-void
-main(void)
-{
-  volatile unsigned int i;
-  __code char *p= (__code char *)0;
-
-  sif= (unsigned char __xdata *)0xffff;
-  serial_init(19200);
-  for (i= 1; i<0x4000; i++)
-    {
-      print_cx(p[i]);
-      putchar('\n');
-    }
-  * (char __idata *) 0 = * (char __xdata *) 0xfffe;
-  *sif= 's';
-}
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/st.sh sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/st.sh
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/st.sh	2019-03-14 11:32:41.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/st.sh	1970-01-01 00:00:00.000000000 +0000
@@ -1,108 +0,0 @@
-TEST=""
-S51v5=s515
-S51v6=s516
-VER=6
-S51=$S51v6
-
-PROF=""
-
-while [ -n "$1" ]; do
-    case "$1" in
-	-6)
-	    S51=$S51v6
-	    VER=6
-	    shift
-	    ;;
-	-5)
-	    S51=$S51v5
-	    VER=5
-	    shift
-	    ;;
-	-v)
-	    shift
-	    S51=s51-${1}
-	    VER="${1}"
-	    shift
-	    ;;
-	-X)
-	    S51=$S51vX
-	    VER=X
-	    shift
-	    ;;
-	-p)
-	    PROF="p"
-	    shift
-	    ;;
-	-P)
-	    shift
-	    TEST="$1"
-	    CMD="gprof ${S51}p st${TEST}_v${VER}_gmon.out"
-	    echo $CMD
-	    $CMD
-	    exit 0
-	    ;;
-	*)
-	    TEST="$1"
-	    shift
-	    ;;
-    esac
-done
-
-if [ -n "$PROF" ]; then
-    S51=${S51}p
-fi
-
-echo -e "*\n* st${TEST}\n*\n"
-
-make -f st${TEST}.mk clean all
-
-SIM=st${TEST}${VER}.sim
-OUT=st${TEST}${VER}.out
-TIM=st${TEST}${VER}.tim
-CSV=st${TEST}${VER}.csv
-CMD=st${TEST}${VER}.cmd
-
-rm -f $SIM $OUT $TIM $CSV
-
->$CMD
-echo "set hardware simif xram 0xffff" >>$CMD
-echo "set hardware simif fout \"st${TEST}${VER}.sout\"" >>$CMD
-cat st.cmd >>$CMD
-
-ls -l st${TEST}.ihx
-
-/usr/bin/time -o $TIM -f '
-Elapsed\t%e
-Kernel\t%S
-User\t%U
-In\t%I
-Out\t%O
-SwT\t%c
-SwIO\t%w
-MaxFlt\t%F
-MinFlt\t%R
-Swaps\t%W
-Mem\t%M
-Unshr\t%D
-' $S51 -tC52 -Sin=/dev/null,out=$OUT st${TEST}.ihx <$CMD|tee $SIM
-tee -a $SIM <$TIM
-
-if [ -n "$PROF" ]; then
-    mv gmon.out st${TEST}_v${VER}_gmon.out
-fi
-
-E=$(grep Elapsed $SIM)
-#echo
-#echo $E
-
-E=$(echo $E|cut -d ' ' -f 2)
-C=$(grep 'Total time' $SIM|sed 's/^[^(]*(//'|sed 's/ .*//')
-S=$(echo "scale=3;${C}/${E}/1000000"|bc)
-ST=$(grep 'Simulated ' $SIM|cut -d' ' -f5)
-echo "st${TEST} speed= $S Mclk/sec"|tee -a $SIM
-
-echo "st${TEST},${VER},${E},${S}"|tee $CSV
-
-echo $E >st${TEST}${VER}_e.txt
-echo $ST >st${TEST}${VER}_st.txt
-echo $S >st${TEST}${VER}_s.txt
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/sts.mk sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/sts.mk
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/sts.mk	2017-03-12 13:28:55.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/sts.mk	1970-01-01 00:00:00.000000000 +0000
@@ -1,7 +0,0 @@
-MAIN		= sts
-
-OTHERS		= serial print
-
-include sdcc.mk
-
-MODEL		= small
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/stt.c sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/stt.c
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/stt.c	2017-03-29 15:20:04.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/stt.c	1970-01-01 00:00:00.000000000 +0000
@@ -1,68 +0,0 @@
-#include "hw.h"
-#include "timer.h"
-#include "t0.h"
-
-unsigned char __xdata * volatile sif;
-
-volatile unsigned int tr;
-
-void t0_isr(void) __interrupt (1)
-{
-  T0set(tr);
-}
-
-int var;
-__data  int dvar;
-__idata int ivar;
-__xdata int xvar;
-__pdata int pvar;
-__code  int cvar;
-__sfr   __at(0x81) svar;
-__bit   bvar;
-
-void
-fn(void)
-{
-  volatile int fn_local;
-  volatile int fn_hide;
-  fn_local= fn_hide= 1;
-  {
-    volatile int fn_blocked, fn_hide;
-    fn_blocked= fn_hide= 2;
-  }
-}
-
-void
-sfun(void)
-{
-  return ;
-}
-
-void
-main(void)
-{
-  volatile unsigned int i, x= 0, j;
-  __xdata char *p= (__xdata char *)0;
-
-  bvar= 1;
-  sif= (unsigned char __xdata *)0xffff;
-  tr= T_kezdoertek(10);
-  T0idozito1(0);
-  T0beallit(tr);
-  T0start();
-  ET0= 1;
-  EA= 1;
-
-  for (j=0; j<10; j++)
-    for (i= 0; i<0xfff0; i++)
-      {
-	char c= p[i];
-	unsigned int t= TL0 + (TH0*256);
-	p[i]= t&0xff;
-	if (p[i] != t&0xff)
-	  x++;
-	p[i]= c;
-      }
-  * (char __idata *) 0 = * (char __xdata *) 0xfffe;
-  *sif= 's';
-}
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/stt_large.mk sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/stt_large.mk
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/stt_large.mk	2017-03-24 14:15:01.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/stt_large.mk	1970-01-01 00:00:00.000000000 +0000
@@ -1,8 +0,0 @@
-APP		= stt_large
-MAIN		= stt
-
-OTHERS		= timer t0 serial
-
-include sdcc.mk
-
-MODEL		= large
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/stt.mk sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/stt.mk
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/stt.mk	2017-03-12 13:28:55.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/stt.mk	1970-01-01 00:00:00.000000000 +0000
@@ -1,7 +0,0 @@
-MAIN		= stt
-
-OTHERS		= timer t0 serial
-
-include sdcc.mk
-
-MODEL		= small
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/stt_small.mk sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/stt_small.mk
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/stt_small.mk	2017-03-24 14:15:01.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/stt_small.mk	1970-01-01 00:00:00.000000000 +0000
@@ -1,8 +0,0 @@
-APP		= stt_small
-MAIN		= stt
-
-OTHERS		= timer t0 serial
-
-include sdcc.mk
-
-MODEL		= small
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/stxr.c sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/stxr.c
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/stxr.c	2017-03-12 13:28:55.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/stxr.c	1970-01-01 00:00:00.000000000 +0000
@@ -1,25 +0,0 @@
-#include 
-
-unsigned char __xdata * volatile sif;
-
-int putchar(int c)
-{
-  *sif='p';*sif=c;
-}
-
-void
-main(void)
-{
-  volatile unsigned int i, x, j;
-  __xdata char *p= (__xdata char *)0;
-
-  sif= (unsigned char __xdata *)0xffff;
-  for (j= 0; j<10; j++)
-    for (i= 0; i<0xfff0; i++)
-      {
-	//printf("j=%4x i=%4x\n", j, i);
-	x= p[i];
-      }
-  * (char __idata *) 0 = * (char __xdata *) 0xfffe;
-  *sif= 's';
-}
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/stxr.mk sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/stxr.mk
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/stxr.mk	2017-03-12 13:28:55.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/stxr.mk	1970-01-01 00:00:00.000000000 +0000
@@ -1,5 +0,0 @@
-MAIN		= stxr
-
-include sdcc.mk
-
-MODEL		= small
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/stxrw.c sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/stxrw.c
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/stxrw.c	2017-03-12 13:28:55.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/stxrw.c	1970-01-01 00:00:00.000000000 +0000
@@ -1,22 +0,0 @@
-
-unsigned char __xdata * volatile sif;
-
-void
-main(void)
-{
-  volatile unsigned int i, x= 0, j;
-  __xdata char *p= (__xdata char *)0;
-
-  sif= (unsigned char __xdata *)0xffff;
-  for (j=0; j<10; j++)
-    for (i= 0; i<0xfff0; i++)
-      {
-	char c= p[i];
-	p[i]= i&0xff;
-	if (p[i] != i&0xff)
-	  x++;
-	p[i]= c;
-      }
-  * (char __idata *) 0 = * (char __xdata *) 0xfffe;
-  *sif= 's';
-}
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/stxrw.mk sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/stxrw.mk
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/stxrw.mk	2017-03-12 13:28:55.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/stxrw.mk	1970-01-01 00:00:00.000000000 +0000
@@ -1,3 +0,0 @@
-MAIN		= stxrw
-
-include sdcc.mk
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/stxw.c sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/stxw.c
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/stxw.c	2017-03-12 13:28:55.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/stxw.c	1970-01-01 00:00:00.000000000 +0000
@@ -1,16 +0,0 @@
-
-unsigned char __xdata * volatile sif;
-
-void
-main(void)
-{
-  volatile unsigned int i, j;
-  __xdata char *p= (__xdata char *)0;
-
-  sif= (unsigned char __xdata *)0xffff;
-  for (j=0; j<10; j++)
-    for (i= 0; i<0xfff0; i++)
-      p[i]= i&0xff;
-  * (char __idata *) 0 = * (char __xdata *) 0xfffe;
-  *sif= 's';
-}
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/stxw.mk sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/stxw.mk
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/stxw.mk	2017-03-12 13:28:55.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/stxw.mk	1970-01-01 00:00:00.000000000 +0000
@@ -1,5 +0,0 @@
-MAIN		= stxw
-
-include sdcc.mk
-
-MODEL		= small
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/symdis/baseline/8751 sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/symdis/baseline/8751
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/symdis/baseline/8751	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/symdis/baseline/8751	2022-02-08 21:21:05.000000000 +0000
@@ -0,0 +1,82 @@
+uCsim, Copyright (C)  Daniel Drotos.
+uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+This is free software, and you are welcome to redistribute it
+under certain conditions; type `show c' for details.
+var __sdcc_program_startup rom[0x0003]
+var __sdcc_gsinit_startup rom[0x0006]
+var __mcs51_genXINIT rom[0x0013]
+var __mcs51_genRAMCLEAR rom[0x0035]
+var __mcs51_genXRAMCLEAR rom[0x003b]
+var _main rom[0x0062]
+var __sdcc_external_startup rom[0x0064]
+dc 0x0000 0x00067
+
+0x0000    <.reset>:
+0x0000    02 00 06 LJMP   0x0006 <__sdcc_gsinit_startup>[0K
+
+0x0003    <__sdcc_program_startup>:
+0x0003  ? 02 00 62 LJMP   0x0062 <_main>[0K
+
+0x0006    <__sdcc_gsinit_startup>:
+0x0006    75 81 0a MOV    0x81 ,#0x0a[0K
+0x0009  ? 12 00 64 LCALL  0x0064 <__sdcc_external_startup>[0K
+0x000c  ? e5 82    MOV    A,0x82 [0K
+0x000e  ? 60 03    JZ     0x0013 <__mcs51_genXINIT>[0K
+0x0010  ? 02 00 03 LJMP   0x0003 <__sdcc_program_startup>[0K
+
+0x0013    <__mcs51_genXINIT>:
+0x0013  ? 79 00    MOV    R1,#0x00[0K
+0x0015  ? e9       MOV    A,R1[0K
+0x0016  ? 44 00    ORL    A,#0x00[0K
+0x0018  ? 60 1b    JZ     0x0035 <__mcs51_genRAMCLEAR>[0K
+0x001a  ? 7a 00    MOV    R2,#0x00[0K
+0x001c  ? 90 00 68 MOV    DPTR,#0x0068[0K
+0x001f  ? 78 01    MOV    R0,#0x01[0K
+0x0021  ? 75 a0 00 MOV    0xa0 ,#0x00[0K
+0x0024  ? e4       CLR    A[0K
+0x0025  ? 93       MOVC   A,@A+DPTR[0K
+0x0026  ? f2       MOVX   @R0,A[0K
+0x0027  ? a3       INC    DPTR[0K
+0x0028  ? 08       INC    R0[0K
+0x0029  ? b8 00 02 CJNE   R0,#0x00,0x002e[0K
+0x002c  ? 05 a0    INC    0xa0 [0K
+0x002e  ? d9 f4    DJNZ   R1,0x0024[0K
+0x0030  ? da f2    DJNZ   R2,0x0024[0K
+0x0032  ? 75 a0 ff MOV    0xa0 ,#0xff[0K
+
+0x0035    <__mcs51_genRAMCLEAR>:
+0x0035  ? e4       CLR    A[0K
+0x0036  ? 78 ff    MOV    R0,#0xff[0K
+0x0038  ? f6       MOV    @R0,A[0K
+0x0039  ? d8 fd    DJNZ   R0,0x0038[0K
+
+0x003b    <__mcs51_genXRAMCLEAR>:
+0x003b  ? 78 00    MOV    R0,#0x00[0K
+0x003d  ? e8       MOV    A,R0[0K
+0x003e  ? 44 00    ORL    A,#0x00[0K
+0x0040  ? 60 0a    JZ     0x004c[0K
+0x0042  ? 79 01    MOV    R1,#0x01[0K
+0x0044  ? 75 a0 00 MOV    0xa0 ,#0x00[0K
+0x0047  ? e4       CLR    A[0K
+0x0048  ? f3       MOVX   @R1,A[0K
+0x0049  ? 09       INC    R1[0K
+0x004a  ? d8 fc    DJNZ   R0,0x0048[0K
+0x004c  ? 78 00    MOV    R0,#0x00[0K
+0x004e  ? e8       MOV    A,R0[0K
+0x004f  ? 44 00    ORL    A,#0x00[0K
+0x0051  ? 60 0c    JZ     0x005f[0K
+0x0053  ? 79 00    MOV    R1,#0x00[0K
+0x0055  ? 90 00 01 MOV    DPTR,#0x0001[0K
+0x0058  ? e4       CLR    A[0K
+0x0059  ? f0       MOVX   @DPTR,A[0K
+0x005a  ? a3       INC    DPTR[0K
+0x005b  ? d8 fc    DJNZ   R0,0x0059[0K
+0x005d  ? d9 fa    DJNZ   R1,0x0059[0K
+0x005f  ? 02 00 03 LJMP   0x0003 <__sdcc_program_startup>[0K
+
+0x0062    <_main>:
+0x0062  ? 80 fe    SJMP   0x0062 <_main>[0K
+
+0x0064    <__sdcc_external_startup>:
+0x0064  ? 75 82 00 MOV    0x82 ,#0x00[0K
+0x0067  ? 22       RET[0K
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/symdis/baseline/DS390F sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/symdis/baseline/DS390F
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/symdis/baseline/DS390F	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/symdis/baseline/DS390F	2022-02-08 21:21:05.000000000 +0000
@@ -0,0 +1,91 @@
+uCsim, Copyright (C)  Daniel Drotos.
+uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+This is free software, and you are welcome to redistribute it
+under certain conditions; type `show c' for details.
+var __interrupt_vect rom[0x0000]
+var __reset_vect rom[0x0003]
+var __sdcc_gsinit_startup rom[0x0023]
+var __sdcc_init_data rom[0x002f]
+var __sdcc_program_startup rom[0x001f]
+var _main rom[0x008e]
+dc 0x0000 0x00090
+
+0x00000    <__interrupt_vect>:
+0x00000    02 00 03 75 LJMP   0x00375[0K
+0x00004  ? 00          NOP[0K
+0x00005  ? aa 75       MOV    R2,0x75[0K
+0x00007  ? 00          NOP[0K
+0x00008  ? 55 75       ANL    A,0x75[0K
+0x0000a  ? 9d          SUBB   A,R5[0K
+0x0000b  ? 06          INC    @R0[0K
+0x0000c  ? 75 00 aa    MOV    0x00 ,#0xaa[0K
+0x0000f  ? 75 00 55    MOV    0x00 ,#0x55[0K
+0x00012  ? 75 c6 90    MOV    0xc6 ,#0x90[0K
+0x00015  ? 75 00 00    MOV    0x00 ,#0x00[0K
+0x00018  ? 75 00 00    MOV    0x00 ,#0x00[0K
+0x0001b  ? 02 00 00 23 LJMP   0x00023 <__sdcc_gsinit_startup>[0K
+
+0x0001f    <__sdcc_program_startup>:
+0x0001f  ? 02 00 00 8e LJMP   0x0008e <_main>[0K
+
+0x00023    <__sdcc_gsinit_startup>:
+0x00023  ? 12 00 00 91 LCALL  0x00091[0K
+0x00027  ? e5 82       MOV    A,0x82 [0K
+0x00029  ? 60 04       JZ     0x0002f <__sdcc_init_data>[0K
+0x0002b  ? 02 00 00 1f LJMP   0x0001f <__sdcc_program_startup>[0K
+
+0x0002f    <__sdcc_init_data>:
+0x0002f  ? 74 0a       MOV    A,#0x0a[0K
+0x00031  ? 44 00       ORL    A,#0x00[0K
+0x00033  ? 60 27       JZ     0x0005c[0K
+0x00035  ? 74 30       MOV    A,#0x30[0K
+0x00037  ? 24 0a       ADD    A,#0x0a[0K
+0x00039  ? f9          MOV    R1,A[0K
+0x0003a  ? 74 08       MOV    A,#0x08[0K
+0x0003c  ? 34 00       ADDC   A,#0x00[0K
+0x0003e  ? fa          MOV    R2,A[0K
+0x0003f  ? 90 00 08 30 MOV    DPTR,#0x00830[0K
+0x00043  ? 75 86 21    MOV    0x86 ,#0x21[0K
+0x00046  ? 90 00 04 4d MOV    DPTR,#0x0044d[0K
+0x0004a  ? e4          CLR    A[0K
+0x0004b  ? 93          MOVC   A,@A+DPTR[0K
+0x0004c  ? f0          MOVX   @DPTR,A[0K
+0x0004d  ? a3          INC    DPTR[0K
+0x0004e  ? a3          INC    DPTR[0K
+0x0004f  ? e5 82       MOV    A,0x82 [0K
+0x00051  ? b5 01 f6    CJNE   A,0x01 ,0x0004a[0K
+0x00054  ? e5 83       MOV    A,0x83 [0K
+0x00056  ? b5 02 f1    CJNE   A,0x02 ,0x0004a[0K
+0x00059  ? 75 86 00    MOV    0x86 ,#0x00[0K
+0x0005c  ? 78 00       MOV    R0,#0x00[0K
+0x0005e  ? e8          MOV    A,R0[0K
+0x0005f  ? 44 00       ORL    A,#0x00[0K
+0x00061  ? 60 0a       JZ     0x0006d[0K
+0x00063  ? 79 01       MOV    R1,#0x01[0K
+0x00065  ? 75 00 00    MOV    0x00 ,#0x00[0K
+0x00068  ? e4          CLR    A[0K
+0x00069  ? f3          MOVX   @R1,A[0K
+0x0006a  ? 09          INC    R1[0K
+0x0006b  ? d8 fc       DJNZ   R0,0x00069[0K
+0x0006d  ? 78 4c       MOV    R0,#0x4c[0K
+0x0006f  ? e8          MOV    A,R0[0K
+0x00070  ? 44 04       ORL    A,#0x04[0K
+0x00072  ? 60 0d       JZ     0x00081[0K
+0x00074  ? 79 05       MOV    R1,#0x05[0K
+0x00076  ? 90 00 00 01 MOV    DPTR,#0x00001[0K
+0x0007a  ? e4          CLR    A[0K
+0x0007b  ? f0          MOVX   @DPTR,A[0K
+0x0007c  ? a3          INC    DPTR[0K
+0x0007d  ? d8 fc       DJNZ   R0,0x0007b[0K
+0x0007f  ? d9 fa       DJNZ   R1,0x0007b[0K
+0x00081  ? e4          CLR    A[0K
+0x00082  ? f5 0a       MOV    0x0a,A[0K
+0x00084  ? f5 0b       MOV    0x0b,A[0K
+0x00086  ? f5 0c       MOV    0x0c,A[0K
+0x00088  ? f5 0d       MOV    0x0d,A[0K
+0x0008a  ? 02 00 00 1f LJMP   0x0001f <__sdcc_program_startup>[0K
+
+0x0008e    <_main>:
+0x0008e  ? 80 fe       SJMP   0x0008e <_main>[0K
+0x00090  ? 22          RET[0K
+24-bit flat mode, warning: lots of sfr-functions not implemented!
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/symdis/Makefile sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/symdis/Makefile
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/symdis/Makefile	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/symdis/Makefile	2021-05-07 16:21:16.000000000 +0000
@@ -0,0 +1,15 @@
+OUTPUTS = 8751 DS390F
+
+
+# Ignore changes in white space. The field widths for labels
+# depends on the length of the longest label. This will be
+# different for different simulators and should not be assumed
+# to be constant for any given simulator.
+DIFF_OPTS += -b
+
+
+$(OUTPUTS): %:	test-%.ihx test-%.cmd
+	$(call run-sim, -t '$@')
+
+
+include test-lib.mk
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/symdis/test-8751.cmd sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/symdis/test-8751.cmd
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/symdis/test-8751.cmd	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/symdis/test-8751.cmd	2021-05-07 16:21:16.000000000 +0000
@@ -0,0 +1,8 @@
+var __sdcc_program_startup rom[0x0003]
+var __sdcc_gsinit_startup rom[0x0006]
+var __mcs51_genXINIT rom[0x0013]
+var __mcs51_genRAMCLEAR rom[0x0035]
+var __mcs51_genXRAMCLEAR rom[0x003b]
+var _main rom[0x0062]
+var __sdcc_external_startup rom[0x0064]
+dc 0x0000 0x00067
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/symdis/test-8751.ihx sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/symdis/test-8751.ihx
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/symdis/test-8751.ihx	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/symdis/test-8751.ihx	2021-05-07 16:21:16.000000000 +0000
@@ -0,0 +1,12 @@
+:03000000020006F5
+:03005F0002000399
+:0300030002006296
+:0200620080FE1E
+:06003500E478FFF6D8FD9F
+:200013007900E94400601B7A00900068780175A000E493F2A308B8000205A0D9F4DAF2752B
+:02003300A0FF2C
+:20003B007800E84400600A790175A000E4F309D8FC7800E84400600C7900900001E4F0A3C3
+:04005B00D8FCD9FAFA
+:0D00060075810A120064E5826003020003A8
+:04006400758200227F
+:00000001FF
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/symdis/test.c sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/symdis/test.c
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/symdis/test.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/symdis/test.c	2021-05-07 16:21:16.000000000 +0000
@@ -0,0 +1,4 @@
+int main(int argc, char *argv[])
+{
+	for (;;);
+}
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/symdis/test-DS390F.cmd sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/symdis/test-DS390F.cmd
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/symdis/test-DS390F.cmd	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/symdis/test-DS390F.cmd	2021-05-07 16:21:16.000000000 +0000
@@ -0,0 +1,7 @@
+var __interrupt_vect rom[0x0000]
+var __reset_vect rom[0x0003]
+var __sdcc_gsinit_startup rom[0x0023]
+var __sdcc_init_data rom[0x002f]
+var __sdcc_program_startup rom[0x001f]
+var _main rom[0x008e]
+dc 0x0000 0x00090
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/symdis/test-DS390F.ihx sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/symdis/test-DS390F.ihx
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/symdis/test-DS390F.ihx	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/symdis/test-DS390F.ihx	2021-05-07 16:21:16.000000000 +0000
@@ -0,0 +1,71 @@
+:1F0000000200037500AA750055759D067500AA75005575C6907500007500000200002318
+:2000230012000091E58260040200001F740A440060277430240AF974083400FA90000830A8
+:200043007586219000044DE493F0A3A3E582B501F6E583B502F17586007800E84400600AC7
+:1E0063007901750000E4F309D8FC784CE84404600D790590000001E4F0A3D8FCD9FA4E
+:04008A000200001F51
+:04001F000200008E4D
+:03008E0080FE22CF
+:09008100E4F50AF50BF50CF50D90
+:2000910075A80075C7AA75C75575923F75C7AA75C75575A227C2D9758EF975C7AA75C755B2
+:2000B10075C6AF900000021200010CC093C083C082C086C0F0C0E07586009001000005860F
+:2000D1009010000075F0800586E0A30586F0A3D5F0F5D0E0D0F0D086D082D083D09375A8B9
+:2000F10080900004077401F09001C20075F000120001961200071275820022858284858337
+:200111008575C480E584B40107E585B400028024E584B40207E585B400028034E584B4048C
+:2001310007E585B400028041E584B40057E585B40452804275C48875C498AC91EC30E3FA54
+:2001510075C41890000005E584F0A3E585F0803475C490AC91EC30E3FA75C41090000005C1
+:20017100E584F0A3E585F0801B90000005E584F0A3E585F0800E75C4C090000005E584F01D
+:20019100A3E585F022AA82AB83AC93ADF0EA4B4C4D7007C2AC5398EF8037C2ACC2CA7598AE
+:2001B10050438780438E2075C90075C8348A828B838C938DF0120001E390000407E0FA8A49
+:2001D10008600AC299A2999298D2AC8004C298D29922AA82AB83AC93ADF0C2CA8C00EDC4F4
+:2001F1002354E0C8C423C868C854E0C868F9EBC423541F48F88A06EBC42354E0CEC423CEF5
+:200211006ECE54E0CE6EFF90000000EEF0A3EFF0A3E8F0A3E9F09019400075F001120000DA
+:2002310000AE82AF83A893A9F0C3E49EFAE49FFBE498FCE499FD8A068ECA8ECC8B027B007E
+:200251008ACB8ACDC2CFD2CA22C0E0C0F0C082C083C093C086758600C084C085C095C09CEF
+:20027100C002C003C004C005C0D075D000209804020003059000044DE0FAA3E0FBE03395E3
+:20029100E0FCFDEA2407F584EB3400F585EC3400F595E5990586F07586009000044DE024CA
+:2002B10001FAA3E03400FB9000044DEAF074035BA3F09000044F7586019000044DE07586C5
+:2002D10000F5F0E0B5F011758601A3E0758600F5F0A3E0B5F002800280189000044FE02408
+:2002F10001FAA3E03400FB9000044FEAF074035BA3F0C298109902800690000451E4F0D00A
+:20031100D0D005D004D003D002D09CD095D085D084D086D093D083D082D0F0D0E032E50847
+:20033100604F9000044F7586019000044DE0758600F5F0E0B5F011758601A3E0758600F578
+:20035100F0A3E0B5F00280309000044FE0FAA3E0FBE03395E0FCFDEA2407F584EB3400F564
+:2003710085EC3400F5950586E0FA7586008A82800A3098048599822275820022AA82E50887
+:20039100601290000451E070F9900004517401F08A9980073099FD8A99C29922E50860699C
+:2003B1009000044F7586019000044DE0758600F5F0E0B5F011758601A3E0758600F5F0A314
+:2003D100E0B5F00280DA9000044FE0FAA3E0FBE03395E0FCFDEA2407F584EB3400F585EC5C
+:2003F1003400F5950586E0FA758600C2AC9000044FE02401FBA3E03400FC9000044FEBF00C
+:2004110074035CA3F0D2AC80073098FDAA99C2988A822253B0FD9000000275F000120007C0
+:20043100B943B00222C2AC9000044FE4F0A3F09000044DE4F0A3F0C298E5086006C299D201
+:20045100AC8002D29922AA82AB83AC93ADF0EA4B4C4D7007C2AE53C0EF803BC2AEC28E75F3
+:20047100C05043D880438E10AE8953060F74204EF5898A828B838C938DF0120004A89000DC
+:200491000448E0FA8A09600AC2C1A2C192C0D2AE8004C2C0D2C122AA82AB83AC93ADF0C2BD
+:2004B1008E8C00EDC42354E0C8C423C868C854E0C868F9EBC423541F48F88A06EBC42354CA
+:2004D100E0CEC423CE6ECE54E0CE6EFF90000000EEF0A3EFF0A3E8F0A3E9F09019400075B8
+:2004F100F00112000000AE82AF83A893A9F0C3E49EFAE49FFBE498FCE499FD8A8D8A8BC215
+:200511008FD28E22C0E0C0F0C082C083C093C086758600C084C085C095C09CC002C003C0D1
+:2005310004C005C0D075D00020C004020005C090000452E0FAA3E0FBE03395E0FCFDEA2494
+:2005510008F584EB3404F585EC3400F595E5C10586F075860090000452E02401FAA3E0340A
+:2005710000FB90000452743F5AF0A3E4F09000045475860190000452E0758600F5F0E0B5F6
+:20059100F011758601A3E0758600F5F0A3E0B5F0028002801890000454E02401FAA3E03408
+:2005B10000FB90000454743F5AF0A3E4F0C2C010C102800690000456E4F0D0D0D005D004F1
+:2005D100D003D002D09CD095D085D084D086D093D083D082D0F0D0E032E509604F900004BA
+:2005F1005475860190000452E0758600F5F0E0B5F011758601A3E0758600F5F0A3E0B5F0D7
+:2006110002803090000454E0FAA3E0FBE03395E0FCFDEA2408F584EB3404F585EC3400F515
+:20063100950586E0FA7586008A82800A30C00485C1822275820022AA82E509601290000407
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+:20069100DA90000454E0FAA3E0FBE03395E0FCFDEA2408F584EB3404F585EC3400F59505D3
+:2006B10086E0FA758600C2AE90000454E02401FBA3E03400FC90000454743F5BF0A3E4F066
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+:2006F100C2AE90000454E4F0A3F090000452E4F0A3F0C2C0E5096006C2C1D2AE8002D2C1EF
+:200711002290000005E0B40107A3E0B40002802A90000005E0B40207A3E0B40002801B90FC
+:20073100000005E0B40407A3E0B400028002800A7A007B127C007D0080087A007B247C00A2
+:200751007D00EAF4FAEBF4FBECF4FCEDF4FD8A0E8B0FC2A95388CCAA895302F074014AF52F
+:2007710089438E08850E8AAA0F7B008A8CD2A9D28C22C0E0C0D0850E8A850F8CE4050AB58F
+:200791000A0C050BB50B07050CB50C02050DD0D0D0E032C2A9AA0AAB0BAC0CAD0DD2A98AA7
+:2007B100828B838C938DF022AA82AB83AC93ADF0C002C003C004C005120007A4AE82AF8377
+:2007D100A893A9F0D005D004D003D00290000449EA2EF0EB3FA3F0EC38A3F0ED39A3F012C2
+:2007F1000007A4AE82AF83A893A9F090000449E0FAA3E0FBA3E0FCA3E0FDC3EE9AEF9BE816
+:200811009CE99D40DA22A882A983E849601009B800011900000000000000D8F7D9F52200D8
+:09083100000000000000000000BE
+:00000001FF
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/t0.c sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/t0.c
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/t0.c	2017-03-12 13:28:55.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/t0.c	1970-01-01 00:00:00.000000000 +0000
@@ -1,89 +0,0 @@
-/*
-  t0.c
-  Segedlet a T0 idozito/szamlalo kezelesehez
-  (c) Drotos Daniel, 2005
-*/
-
-#include "hw.h"
-#include 
-
-#include "timer.h"
-#include "t0.h"
-
-
-
-/* Adott idoziteshez szukseges szamlalo kezdoerteket szamolja ki.
-   A parametert msec-ben kell megadni (kb 0.02-71 kozott) */
-
-unsigned int T0kezdoertek(float ido /* msec */)
-{
-  return T_kezdoertek(ido);
-}
-
-
-/* Idozito uzemmod */
-
-void T0idozito1(bool kapuzott)
-{
-  TR0= 0;
-  TMOD&= 0xf0;
-  TMOD|= 0x01;
-  if (kapuzott)
-    TMOD|= 0x08;
-}
-
-
-/* Szamlalo uzemmod */
-
-void T0szamlalo(bool kapuzott)
-{
-  TR0= 0;
-  TMOD&= 0xf0;
-  TMOD|= 0x01;
-  TMOD|= 0x04;
-  if (kapuzott)
-    TMOD|= 0x08;
-}
-
-
-/* Szamlalo ertek beallitasa */
-
-void T0beallit(unsigned int kezdoertek)
-{
-  TH0= kezdoertek >> 8;
-  TL0= kezdoertek & 0xff;
-}
-
-
-/* Szamlalo ertek beallitasa */
-
-void T0ujratolt(unsigned int kezdoertek)
-{
-  TH0= kezdoertek >> 8;
-  TL0= kezdoertek & 0xff;
-}
-
-
-/* A szamlalo aktualis allapota usec-ben */
-
-float T0eltelt_us(void)
-{
-  unsigned char h, l;
-  h= TH0;
-  l= TL0;
-  return (12.0/Fosc) * ((unsigned int)(h*256+l));
-}
-
-
-/* A szamlalo tulcsordulasaig hatralevo ido usec-ben */
-
-float T0hatravan_us(void)
-{
-  unsigned char h, l;
-  h= TH0;
-  l= TL0;
-  return (12.0/Fosc) * (0x10000 - (unsigned int)(h*256+l));
-}
-
-
-/* End of t0.c */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/t0.h sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/t0.h
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/t0.h	2017-03-12 13:28:55.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/t0.h	1970-01-01 00:00:00.000000000 +0000
@@ -1,82 +0,0 @@
-/*
-  T0.h
-  Segedlet a T0 idozito hasznalatahoz
-  (c) Drotos Daniel, 2005
-*/
-
-#ifndef T0_HEADER
-#define T0_HEADER
-
-#ifndef bool
-#define bool char
-#endif
-
-#ifndef FALSE
-#define FALSE 0
-#endif
-
-#ifndef TRUE
-#define TRUE 1
-#endif
-
-
-/*
-  A megadott ideig tarto idoziteshez szukseges
-  szamlalo kezdoerteket szamolja ki. Az idot
-  msec-ben kell megadni, kb 0.02-71.1 kozott.
-  Felhasznalja az Fosc erteket a szamitashoz.
-*/
-extern unsigned int T0kezdoertek(float ido);
-
-
-/*
-  Beallitja a T0-t idozito 1 uzemmodba (leallitja
-  a szamlalot)
-*/
-extern void T0idozito1(bool kapuzott);
-
-
-/*
-  Beallitja a T0-t szamlalo uzemmodba (leallitja
-  a szamlalot.
-*/
-extern void T0szamlalo(bool kapuzott);
-
-
-/*
-  Ez a ket fuggveny a szamlalo aktualis erteket
-  modositja. Egyforma a ketto, az egyik pl a foprogrambol,
-  mig a masik a megszakitas kezelobol hivhato.
-*/
-extern void T0beallit(unsigned int kezdoertek);
-extern void T0ujratolt(unsigned int kezdoertek);
-
-#define T0set(x) { TH0=(x)>>8;TL0=(x)&0xff; }
-
-
-/*
-  A szamlalo elinditasahoz es leallitasahoz hasznalhato
-  makrok
-*/
-#define T0start() TR0=1
-#define T0stop() TR0=0
-
-
-/*
-  A szamlalo aktualis allapota es a tulcsordulasig hatralevo
-  ido usec-ben
-*/
-extern float T0eltelt_us(void);
-extern float T0hatravan_us(void);
-
-/*
-  A szamlalo aktualis allapota es a tulcsordulasig hatralevo
-  ido msec-ben
-*/
-#define T0eltelt() (T0eltelt_us()/1000.0)
-#define T0hatravan() (T0hatravan_us()/1000.0)
-
-
-#endif
-
-/* End of T0.h */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/test-conf.mk sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/test-conf.mk
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/test-conf.mk	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/test-conf.mk	2021-03-21 12:01:19.000000000 +0000
@@ -0,0 +1,3 @@
+CC = sdcc -mmcs51
+AS = sdas8051
+LD = sdld
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/test_extit.c sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/test_extit.c
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/test_extit.c	2016-12-31 19:31:10.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/test_extit.c	1970-01-01 00:00:00.000000000 +0000
@@ -1,15 +0,0 @@
-#include 
-
-sfr at 0xa6 WDTRST;
-
-void jaj() interrupt 0 { P2= P0; P0++; }
-
-void main()
-{
-	IT0=0; /* low level triggered */
-	IT0=1; /* falling edge triggered */
-	EX0=1; /* enable ex #0 */
-	EA=1;
-	P0=0;
-	for(;;);
-}
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/test_idlepd.c sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/test_idlepd.c
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/test_idlepd.c	2016-12-31 19:31:10.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/test_idlepd.c	1970-01-01 00:00:00.000000000 +0000
@@ -1,35 +0,0 @@
-#include 
-
-sfr at 0xa6 WDTRST;
-
-void jaj_ex0() interrupt 0 { P2= P0; }
-
-void jaj_t0() interrupt 1 { P2= P0; }
-
-void main()
-{
-  TH0= 0x80;
-  TL0= 0x80;
-  TMOD= 0x02;
-
-  IT0=0; /* low level triggered */
-  IT0=1; /* falling edge triggered */
-  EX0=1; /* enable ex #0 */
-  ET0=1; /* en t0 */
-  
-  TR0= 1;
-
-  EA=1;
-  P0=0;
-  while (1)
-    {
-      P0= 0;
-      PCON|= 1;/*idle*/
-      P0++;
-      P0++;
-      P0++;
-    }
-  WDTRST= 0x1e;
-  WDTRST= 0xe1;
-  PCON|= 2;/*pd*/
-}
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/test_mdu517.c sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/test_mdu517.c
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/test_mdu517.c	2017-01-06 07:36:33.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/test_mdu517.c	1970-01-01 00:00:00.000000000 +0000
@@ -1,284 +0,0 @@
-#include 
-#include 
-#include 
-
-#include "hw.h"
-#include "serial.h"
-#include "print.h"
-
-#include "c517.h"
-
-#include "mdu517.h"
-
-__xdata char *simif;
-
-unsigned long lop1, lop2, lres, mdu_lres;
-unsigned int iop1, iop2, ires1, ires2, mdu_ires1, mdu_ires2;
-
-int ok, fail, i;
-uint8_t r, shifts;
-
-void
-test_32div16(char verbose)
-{
-  ok= fail= 0;
-  for (i= 0; i<100; i++)
-    {
-      lop1= labs(rand()) * abs(rand());
-      do {
-	iop2= abs(rand()) * abs(rand()%3);
-      }
-      while (!iop2);
-
-      lres= lop1 / iop2;
-      ires1= lop1 % iop2;
-
-      if (verbose)
-	printf("%8lx/%4x %10lu/%5u=%10lu,%5u ", lop1, iop2, lop1, iop2, lres, ires1);
-      r= mdu_32udiv16(lop1, iop2, &mdu_lres, &mdu_ires1);
-      if (verbose)
-	printf("mdu=%10lu,%5u ", mdu_lres, mdu_ires1);
-      if ((lres != mdu_lres) ||
-	  (ires1 != mdu_ires1))
-	{
-	  if (verbose)
-	    printf("fail ");
-	  fail++;
-	}
-      else
-	{
-	  if (verbose)
-	    printf("ok ");
-	  ok++;
-	}
-      if (r &&
-	  verbose)
-	{
-	  if (r&0x80)
-	    printf("err ");
-	  if (r&0x40)
-	    printf("ovr ");
-	}
-      if (verbose)
-	printf("\n");
-    }
-  printf("32div16 test: succ=%d fails=%d\n\n", ok, fail);
-}
-
-void
-test_16div16(char verbose)
-{
-  ok= fail= 0;
-  for (i= 0; i<100; i++)
-    {
-      iop1= abs(rand()) * 1+abs(rand()%2);
-      do {
-	iop2= abs(rand());
-      }
-      while (!iop2);
-
-      ires1= iop1 / iop2;
-      ires2= iop1 % iop2;
-
-      if (verbose)
-	printf("%4x/%4x %5u/%5u=%5u,%5u ", iop1, iop2, iop1, iop2, ires1, ires2);
-      r= mdu_16udiv16(iop1, iop2, &mdu_ires1, &mdu_ires2);
-      if (verbose)
-	printf("mdu=%5u,%5u ", mdu_ires1, mdu_ires2);
-      if ((ires1 != mdu_ires1) ||
-	  (ires2 != mdu_ires2))
-	{
-	  if (verbose)
-	    printf("fail ");
-	  fail++;
-	}
-      else
-	{
-	  if (verbose)
-	    printf("ok ");
-	  ok++;
-	}
-      if (r &&
-	  verbose)
-	{
-	  if (r&0x80)
-	    printf("err ");
-	  if (r&0x40)
-	    printf("ovr ");
-	}
-      if (verbose)
-	printf("\n");
-    }
-  printf("16div16 test: succ=%d fails=%d\n\n", ok, fail);
-}
-
-void
-test_16mul16(char verbose)
-{
-  ok= fail= 0;
-  for (i= 0; i<100; i++)
-    {
-      iop1= abs(rand()) /*+abs(rand())*/;
-      iop2= abs(rand()) /*+abs(rand())*/;
-
-      lres= (unsigned long)iop1 * (unsigned long)iop2;
-
-      if (verbose)
-	printf("%4x*%4x %5u*%5u=%10lu ", iop1, iop2, iop1, iop2, lres);
-      r= mdu_16umul16(iop1, iop2, &mdu_lres);
-      if (verbose)
-	printf("mdu=%10lu ", mdu_lres);
-      if (lres != mdu_lres)
-	{
-	  if (verbose)
-	    printf("fail ");
-	  fail++;
-	}
-      else
-	{
-	  if (verbose)
-	    printf("ok ");
-	  ok++;
-	}
-      if (r &&
-	  verbose)
-	{
-	  if (r&0x80)
-	    printf("err ");
-	}
-      if (verbose)
-	printf("\n");
-    }
-  printf("16mul16 test: succ=%d fails=%d\n\n", ok, fail);
-}
-
-void
-test_norm(char verbose)
-{
-  uint8_t mdu_shifts;
-  
-  ok= fail= 0;
-  for (i= 0; i<100; i++)
-    {
-      do
-	{
-	  lop1= labs(rand()) * abs(rand());
-	}
-      while (lop1 == 0);
-
-      if (lop1 & 0x80000000)
-	{
-	  lres= lop1;
-	  shifts= 0;
-	}
-      else
-	{
-	  shifts= 0;
-	  lres= lop1;
-	  while ((lres & 0x80000000) == 0)
-	    {
-	      lres<<= 1;
-	      shifts++;
-	    }
-	}
-      
-      if (verbose)
-	printf("%8lx< %10lu=%8lx,%2d ", lop1, lop1, lres, shifts);
-      r= mdu_norm(lop1, &mdu_lres, &mdu_shifts);
-      if (verbose)
-	printf("mdu=%8lx,%2d ", mdu_lres, mdu_shifts);
-      if ((lres != mdu_lres) ||
-	  (shifts != mdu_shifts))
-	{
-	  if (verbose)
-	    printf("fail ");
-	  fail++;
-	}
-      else
-	{
-	  if (verbose)
-	    printf("ok ");
-	  ok++;
-	}
-      if (r &&
-	  verbose)
-	{
-	  if (r&0x80)
-	    printf("err ");
-	  if (r&0x40)
-	    printf("ovr ");
-	}
-      if (verbose)
-	printf("\n");
-    }
-  printf("norm test: succ=%d fails=%d\n\n", ok, fail);
-}
-
-void
-test_shift(char verbose)
-{
-  ok= fail= 0;
-  for (i= 0; i<100; i++)
-    {
-      do
-	{
-	  lop1= labs(rand()) * abs(rand());
-	}
-      while (lop1 == 0);
-      do {
-	shifts= rand() & 0x1f;
-      }
-      while (shifts==0);
-      
-      r= rand() & 1;
-
-      if (r)
-	lres= lop1 << shifts;
-      else
-	lres= lop1 >> shifts;
-      
-      if (verbose)
-	printf("%8lx%c%2d=%8lx ", lop1, r?'<':'>', shifts, lres);
-      r= mdu_lshift(lop1, shifts, r, &mdu_lres);
-      if (verbose)
-	printf("mdu=%8lx ", mdu_lres);
-      if (lres != mdu_lres)
-	{
-	  if (verbose)
-	    printf("fail ");
-	  fail++;
-	}
-      else
-	{
-	  if (verbose)
-	    printf("ok ");
-	  ok++;
-	}
-      if (r &&
-	  verbose)
-	{
-	  if (r&0x80)
-	    printf("err ");
-	}
-      if (verbose)
-	printf("\n");
-    }
-  printf("shift test: succ=%d fails=%d\n\n", ok, fail);
-}
-
-void main(void)
-{
-  simif= (__xdata char *)0xffff;
-  serial_init(9600);
-
-  test_32div16(0);
-  test_16div16(0);
-  test_16mul16(0);
-  test_norm(0);
-  test_shift(0);
-  
-  *simif= 's';
-  while (1)
-    {
-    }
-}
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/test_mdu517.mk sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/test_mdu517.mk
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/test_mdu517.mk	2017-03-12 13:28:55.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/test_mdu517.mk	1970-01-01 00:00:00.000000000 +0000
@@ -1,7 +0,0 @@
-MAIN		= test_mdu517
-
-OTHERS		= serial print mdu517
-
-include sdcc.mk
-
-MODEL		= large
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/test_mdu517.type sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/test_mdu517.type
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/test_mdu517.type	2017-01-06 07:36:33.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/test_mdu517.type	1970-01-01 00:00:00.000000000 +0000
@@ -1 +0,0 @@
-517
\ No newline at end of file
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/test_mdu88x.c sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/test_mdu88x.c
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/test_mdu88x.c	2017-01-06 07:36:33.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/test_mdu88x.c	1970-01-01 00:00:00.000000000 +0000
@@ -1,488 +0,0 @@
-#include 
-#include 
-#include 
-
-#include "hw.h"
-#include "serial.h"
-#include "print.h"
-
-#include "xc88x.h"
-
-#include "mdu88x.h"
-
-__xdata char *simif;
-
-unsigned long lop1, lop2, lres, mdu_lres;
-unsigned int iop1, iop2, ires1, ires2, mdu_ires1, mdu_ires2;
-
-signed long slop1, slop2, slres, mdu_slres;
-signed int siop1, siop2, sires1, sires2, mdu_sires1, mdu_sires2;
-
-int ok, fail, i;
-uint8_t r, shifts;
-
-void
-test_32div16(char verbose)
-{
-  ok= fail= 0;
-  for (i= 0; i<100; i++)
-    {
-      lop1= labs(rand()) * abs(rand());
-      do {
-	iop2= abs(rand()) * abs(rand()%3);
-      }
-      while (!iop2);
-
-      lres= lop1 / iop2;
-      ires1= lop1 % iop2;
-
-      if (verbose)
-	printf("%8lx/%4x %10lu/%5u=%10lu,%5u ", lop1, iop2, lop1, iop2, lres, ires1);
-      r= mdu_32udiv16(lop1, iop2, &mdu_lres, &mdu_ires1);
-      if (verbose)
-	printf("mdu=%10lu,%5u ", mdu_lres, mdu_ires1);
-      if ((lres != mdu_lres) ||
-	  (ires1 != mdu_ires1))
-	{
-	  if (verbose)
-	    printf("fail ");
-	  fail++;
-	}
-      else
-	{
-	  if (verbose)
-	    printf("ok ");
-	  ok++;
-	}
-      if (r &&
-	  verbose)
-	{
-	  if (r&0x20)
-	    printf("err ");
-	}
-      if (verbose)
-	printf("\n");
-    }
-  printf("32udiv16 test: succ=%d fails=%d\n\n", ok, fail);
-}
-
-void
-test_32sdiv16(char verbose)
-{
-  ok= fail= 0;
-  for (i= 0; i<100; i++)
-    {
-      do {
-	slop1= (long)rand() * rand() * (rand()%3-1);
-      }
-      while (!slop1);
-      do {
-	siop2= rand() * (rand()%3-1);
-      }
-      while (!siop2);
-
-      slres= slop1 / siop2;
-      sires1= slop1 % siop2;
-
-      if (verbose)
-	printf("%8lx/%4x %+11ld/%+6d=%+11ld,%+6d ",
-	       slop1, siop2,
-	       slop1, siop2,
-	       slres, sires1);
-      r= mdu_32sdiv16(slop1, siop2, &mdu_slres, &mdu_sires1);
-      if (verbose)
-	printf("mdu=%+11ld,%+6d ",
-	       mdu_slres, mdu_sires1);
-      if ((slres != mdu_slres) ||
-	  (sires1 != mdu_sires1))
-	{
-	  if (verbose)
-	    printf("fail ");
-	  fail++;
-	}
-      else
-	{
-	  if (verbose)
-	    printf("ok ");
-	  ok++;
-	}
-      if (r &&
-	  verbose)
-	{
-	  if (r&0x20)
-	    printf("err ");
-	}
-      if (verbose)
-	printf("\n");
-    }
-  printf("32sdiv16 test: succ=%d fails=%d\n\n", ok, fail);
-}
-
-void
-test_16div16(char verbose)
-{
-  ok= fail= 0;
-  for (i= 0; i<100; i++)
-    {
-      iop1= abs(rand()) * 1+abs(rand()%2);
-      do {
-	iop2= abs(rand());
-      }
-      while (!iop2);
-
-      ires1= iop1 / iop2;
-      ires2= iop1 % iop2;
-
-      if (verbose)
-	printf("%4x/%4x %5u/%5u=%5u,%5u ", iop1, iop2, iop1, iop2, ires1, ires2);
-      r= mdu_16udiv16(iop1, iop2, &mdu_ires1, &mdu_ires2);
-      if (verbose)
-	printf("mdu=%5u,%5u ", mdu_ires1, mdu_ires2);
-      if ((ires1 != mdu_ires1) ||
-	  (ires2 != mdu_ires2))
-	{
-	  if (verbose)
-	    printf("fail ");
-	  fail++;
-	}
-      else
-	{
-	  if (verbose)
-	    printf("ok ");
-	  ok++;
-	}
-      if (r &&
-	  verbose)
-	{
-	  if (r&0x20)
-	    printf("err ");
-	}
-      if (verbose)
-	printf("\n");
-    }
-  printf("16udiv16 test: succ=%d fails=%d\n\n", ok, fail);
-}
-
-void
-test_16sdiv16(char verbose)
-{
-  ok= fail= 0;
-  for (i= 0; i<100; i++)
-    {
-      do {
-	siop1= rand() * (rand()%3-2);
-      }
-      while (!siop1);
-      do {
-	siop2= rand()/8 * (rand()%3-2);
-      }
-      while (!siop2);
-
-      sires1= siop1 / siop2;
-      sires2= siop1 % siop2;
-
-      if (verbose)
-	printf("%4x/%4x %+6d/%+6d=%+6d,%+6d ",
-	       siop1, siop2,
-	       siop1, siop2,
-	       sires1, sires2);
-      r= mdu_16sdiv16(siop1, siop2, &mdu_sires1, &mdu_sires2);
-      if (verbose)
-	printf("mdu=%+6d,%+6d ", mdu_sires1, mdu_sires2);
-      if ((sires1 != mdu_sires1) ||
-	  (sires2 != mdu_sires2))
-	{
-	  if (verbose)
-	    printf("fail ");
-	  fail++;
-	}
-      else
-	{
-	  if (verbose)
-	    printf("ok ");
-	  ok++;
-	}
-      if (r &&
-	  verbose)
-	{
-	  if (r&0x20)
-	    printf("err ");
-	}
-      if (verbose)
-	printf("\n");
-    }
-  printf("16sdiv16 test: succ=%d fails=%d\n\n", ok, fail);
-}
-
-void
-test_16mul16(char verbose)
-{
-  ok= fail= 0;
-  for (i= 0; i<100; i++)
-    {
-      iop1= abs(rand()) /*+abs(rand())*/;
-      iop2= abs(rand()) /*+abs(rand())*/;
-
-      lres= (unsigned long)iop1 * (unsigned long)iop2;
-
-      if (verbose)
-	printf("%4x*%4x %5u*%5u=%10lu ", iop1, iop2, iop1, iop2, lres);
-      r= mdu_16umul16(iop1, iop2, &mdu_lres);
-      if (verbose)
-	printf("mdu=%10lu ", mdu_lres);
-      if (lres != mdu_lres)
-	{
-	  if (verbose)
-	    printf("fail ");
-	  fail++;
-	}
-      else
-	{
-	  if (verbose)
-	    printf("ok ");
-	  ok++;
-	}
-      if (r &&
-	  verbose)
-	{
-	  if (r&0x80)
-	    printf("err ");
-	}
-      if (verbose)
-	printf("\n");
-    }
-  printf("16umul16 test: succ=%d fails=%d\n\n", ok, fail);
-}
-
-void
-test_16smul16(char verbose)
-{
-  ok= fail= 0;
-  for (i= 0; i<100; i++)
-    {
-      siop1= rand() * (rand()%3-2);
-      do {
-	siop2= rand()/8 * (rand()%3-2);
-      }
-      while (!siop2);
-
-      slres= siop1 * (signed long)siop2;
-
-      if (verbose)
-	printf("%4x*%4x %+6d*%+6d=%+11ld ",
-	       siop1, siop2,
-	       siop1, siop2,
-	       slres);
-      r= mdu_16smul16(siop1, siop2, &mdu_slres);
-      if (verbose)
-	printf("mdu=%+11ld ", mdu_slres);
-      if (slres != mdu_slres)
-	{
-	  if (verbose)
-	    printf("fail ");
-	  fail++;
-	}
-      else
-	{
-	  if (verbose)
-	    printf("ok ");
-	  ok++;
-	}
-      if (r &&
-	  verbose)
-	{
-	  if (r&0x20)
-	    printf("err ");
-	}
-      if (verbose)
-	printf("\n");
-    }
-  printf("16sumul16 test: succ=%d fails=%d\n\n", ok, fail);
-}
-
-void
-test_norm(char verbose)
-{
-  uint8_t mdu_shifts;
-  
-  ok= fail= 0;
-  for (i= 0; i<100; i++)
-    {
-      do
-	{
-	  lop1= labs(rand()) * abs(rand());
-	}
-      while (lop1 == 0);
-
-      if (lop1 & 0x80000000)
-	{
-	  lres= lop1;
-	  shifts= 0;
-	}
-      else
-	{
-	  shifts= 0;
-	  lres= lop1;
-	  while ((lres & 0x80000000) == 0)
-	    {
-	      lres<<= 1;
-	      shifts++;
-	    }
-	}
-      
-      if (verbose)
-	printf("%8lx< %10lu=%8lx,%2d ", lop1, lop1, lres, shifts);
-      r= mdu_norm(lop1, &mdu_lres, &mdu_shifts);
-      if (verbose)
-	printf("mdu=%8lx,%2d ", mdu_lres, mdu_shifts);
-      if ((lres != mdu_lres) ||
-	  (shifts != mdu_shifts))
-	{
-	  if (verbose)
-	    printf("fail ");
-	  fail++;
-	}
-      else
-	{
-	  if (verbose)
-	    printf("ok ");
-	  ok++;
-	}
-      if (r &&
-	  verbose)
-	{
-	  if (r&0x80)
-	    printf("err ");
-	  if (r&0x40)
-	    printf("ovr ");
-	}
-      if (verbose)
-	printf("\n");
-    }
-  printf("norm test: succ=%d fails=%d\n\n", ok, fail);
-}
-
-void
-test_lshift(char verbose)
-{
-  ok= fail= 0;
-  for (i= 0; i<100; i++)
-    {
-      do
-	{
-	  lop1= labs(rand()) * abs(rand());
-	}
-      while (lop1 == 0);
-      do {
-	shifts= rand() & 0x1f;
-      }
-      while (shifts==0);
-      
-      r= rand() & 1;
-
-      if (r)
-	lres= lop1 << shifts;
-      else
-	lres= lop1 >> shifts;
-      
-      if (verbose)
-	printf("%8lx%c%2d=%8lx ", lop1, r?'<':'>', shifts, lres);
-      r= mdu_lshift(lop1, shifts, r, &mdu_lres);
-      if (verbose)
-	printf("mdu=%8lx ", mdu_lres);
-      if (lres != mdu_lres)
-	{
-	  if (verbose)
-	    printf("fail ");
-	  fail++;
-	}
-      else
-	{
-	  if (verbose)
-	    printf("ok ");
-	  ok++;
-	}
-      if (r &&
-	  verbose)
-	{
-	  if (r&0x80)
-	    printf("err ");
-	}
-      if (verbose)
-	printf("\n");
-    }
-  printf("lshift test: succ=%d fails=%d\n\n", ok, fail);
-}
-
-void
-test_ashift(char verbose)
-{
-  ok= fail= 0;
-  for (i= 0; i<100; i++)
-    {
-      do
-	{
-	  slop1= (long)rand()/64 * rand()/64 * (rand()%3-2+i%2);
-	}
-      while (slop1 == 0);
-      do {
-	shifts= rand() & 0x1f;
-      }
-      while (shifts==0);
-      
-      r= rand() & 1;
-
-      if (r)
-	slres= slop1 << shifts;
-      else
-	slres= slop1 >> shifts;
-      
-      if (verbose)
-	printf("%8lx%c%2d=%8lx ", slop1, r?'<':'>', shifts, slres);
-      r= mdu_ashift(slop1, shifts, r, &mdu_slres);
-      if (verbose)
-	printf("mdu=%8lx ", mdu_slres);
-      if (slres != mdu_slres)
-	{
-	  if (verbose)
-	    printf("fail ");
-	  fail++;
-	}
-      else
-	{
-	  if (verbose)
-	    printf("ok ");
-	  ok++;
-	}
-      if (r &&
-	  verbose)
-	{
-	  if (r&0x20)
-	    printf("err ");
-	}
-      if (verbose)
-	printf("\n");
-    }
-  printf("ashift test: succ=%d fails=%d\n\n", ok, fail);
-}
-
-void main(void)
-{
-  simif= (__xdata char *)0xffff;
-  serial_init(9600);
-
-  test_32div16(0);
-  test_32sdiv16(0);
-  test_16div16(0);
-  test_16sdiv16(0);
-  test_16mul16(0);
-  test_16smul16(0);
-  test_norm(0);
-  test_lshift(0);
-  test_ashift(0);
-  
-  *simif= 's';
-  while (1)
-    {
-    }
-}
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/test_mdu88x.cmd sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/test_mdu88x.cmd
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/test_mdu88x.cmd	2017-02-24 11:48:49.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/test_mdu88x.cmd	1970-01-01 00:00:00.000000000 +0000
@@ -1,3 +0,0 @@
-run
-state
-kill
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/test_mdu88x.mk sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/test_mdu88x.mk
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/test_mdu88x.mk	2017-03-12 13:28:55.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/test_mdu88x.mk	1970-01-01 00:00:00.000000000 +0000
@@ -1,7 +0,0 @@
-MAIN		= test_mdu88x
-
-OTHERS		= serial print mdu88x
-
-include sdcc.mk
-
-MODEL		= large
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/test_mdu88x.type sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/test_mdu88x.type
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/test_mdu88x.type	2017-01-06 07:36:33.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/test_mdu88x.type	1970-01-01 00:00:00.000000000 +0000
@@ -1 +0,0 @@
-xc88x
\ No newline at end of file
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/test_ser.c sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/test_ser.c
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/test_ser.c	2019-03-11 07:48:17.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/test_ser.c	1970-01-01 00:00:00.000000000 +0000
@@ -1,114 +0,0 @@
-#include "hw.h"
-
-#define BUFSIZE 16
-#define T0H 0xfc
-#define T0L 0x67
-
-unsigned char buf[BUFSIZE];
-unsigned char first_free= 0, last_occupied= 0;
-bit transmitting, overflow;
-volatile int t0cnt;
-
-void ser_it(void) __interrupt (4)
-{
-  unsigned char temp;
-  if (RI) {
-    buf[first_free]= SBUF;
-    first_free= ((temp= first_free)+1) % BUFSIZE;
-    if (first_free == last_occupied) {
-      first_free= temp;
-      overflow= 1;
-    }
-    RI= 0;
-  }
-  if (TI) {
-    transmitting= 0;
-    TI= 0;
-  }
-}
-
-void t0_it(void) __interrupt (1)
-{
-  TL0= T0L;
-  TH0= T0H;
-  if (t0cnt)
-    t0cnt--;
-}
-
-char empty(void)
-{
-  return(first_free == last_occupied);
-}
-
-unsigned char get_ch(void)
-{
-  unsigned char c;
-  c= buf[last_occupied];
-  last_occupied= (last_occupied+1) % BUFSIZE;
-  overflow= 0;
-  return(c);
-}
-
-void send_ch(unsigned char c)
-{
-  while (transmitting) ;
-  transmitting= 1;
-  SBUF= c;
-}
-
-void send_str(char *str)
-{
-  while (*str) {
-    send_ch(*str);
-    str++;
-  }
-}
-
-void process(void)
-{
-  unsigned char c;
-  c= get_ch();
-  if ((c >= 'a' && c <= 'z') ||
-      (c >= 'A' && c <= 'Z'))
-    c^= 0x20;
-  send_ch(c);
-}
-
-void wait(int delay)
-{
-  t0cnt= delay;
-  while (t0cnt)
-    PCON|= 1;
-}
-
-char test(char c)
-{
-  return(c+1);
-}
-
-void main(void)
-{
-  t0cnt= 0;
-  transmitting= overflow= 0;
-  SCON= 0x7c;
-  TL1= TH1= 250; /* 9600 baud */
-  TH0= T0H;
-  TL0= T0L;
-  TMOD= 0x21;
-  TR0= TR1= 1;
-  ES= ET0= 1;
-  EA= 1;
-  send_str("\nOK\n");
-  test(0);
-  wait(1000);
-  test(1);
-  send_str("delay off\n");
-  for (;;) {
-    if (!empty()) {
-      if (overflow) {
-	send_str("Overflow!\n");
-      }
-      process();
-    }
-  }
-}
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/test_ser.mk sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/test_ser.mk
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/test_ser.mk	2019-03-11 07:48:17.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/test_ser.mk	1970-01-01 00:00:00.000000000 +0000
@@ -1,7 +0,0 @@
-MAIN		= test_ser
-
-OTHERS		= 
-
-include sdcc.mk
-
-MODEL		= small
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/test_stack.c sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/test_stack.c
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/test_stack.c	2016-12-31 19:31:10.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/test_stack.c	1970-01-01 00:00:00.000000000 +0000
@@ -1,9 +0,0 @@
-void jaj(void)
-{
-	jaj();
-}
-
-void main(void)
-{
-	jaj();
-}
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/timer.c sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/timer.c
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/timer.c	2017-03-12 13:28:55.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/timer.c	1970-01-01 00:00:00.000000000 +0000
@@ -1,27 +0,0 @@
-#include "timer.h"
-
-
-float Fosc= 11.0592; /* MHz, Oszcillator orajel */
-
-
-/* Adott idoziteshez szukseges szamlalo kezdoerteket szamolja ki.
-   A parametert msec-ben kell megadni (kb 0.02-71 kozott) */
-
-unsigned int T_kezdoertek(float ido /* msec */)
-{
-  float tper;	/* szamlalo periodusideje */
-  //float per;	/* szukseges periodusok szama */
-
-  tper= 12.0/Fosc;
-  /* atvaltas usec-be */
-  ido*= 1000.0;
-  /* Max 65529 lepes */
-  if (ido > tper*65529.0)
-    return 0;
-  /* Min 20 lepes */
-  if (ido < tper*20.0)
-    return 0xffff-20;
-  //per= ido/tper;
-  return (unsigned int)(65541.0-ido/tper);
-}
-
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/timer.h sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/timer.h
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/timer.h	2017-03-12 13:28:55.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/timer.h	1970-01-01 00:00:00.000000000 +0000
@@ -1,17 +0,0 @@
-#ifndef TIMER_HEADER
-#define TIMER_HEADER
-
-/*
-  Oszcillator orajele MHz-ben. Kezdoerteke 11.0592
-*/
-extern float Fosc;
-
-/*
-  A megadott ideig tarto idoziteshez szukseges
-  szamlalo kezdoerteket szamolja ki. Az idot
-  msec-ben kell megadni, kb 0.02-71.1 kozott.
-  Felhasznalja az Fosc erteket a szamitashoz.
-*/
-extern unsigned int T_kezdoertek(float ido);
-
-#endif
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/tim_ser.c sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/tim_ser.c
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/tim_ser.c	2019-04-02 10:46:33.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/tim_ser.c	1970-01-01 00:00:00.000000000 +0000
@@ -1,73 +0,0 @@
-#include "hw.h"
-
-#include "serial.h"
-#include "t0.h"
-#include "timer.h"
-#include "print.h"
-
-#define T0H 0xfc
-#define T0L 0x67
-
-unsigned int t0cnt;
-__xdata char *simif;
-
-void t0_it(void) __interrupt (1)
-{
-  TL0= T0L;
-  TH0= T0H;
-  if (t0cnt)
-    t0cnt--;
-}
-
-char min='a', max='z';
-
-void process(void)
-{
-  unsigned char c;
-  c= serial_receive();
-  if ((c >= 'a' && c <= 'z') ||
-      (c >= 'A' && c <= 'Z'))
-    {
-      c^= 0x20;
-      min= 'a';
-      max= 'z';
-      P1= 1;
-    }
-  if ((c >= '0') && (c <= '9'))
-    {
-      min= '0';
-      max= '9';
-      P1= 2;
-    }
-  print_c(c);
-}
-
-void main(void)
-{
-  char c= 'a';
-  beallitas();
-  
-  t0cnt= T_kezdoertek(1);
-  TL0= t0cnt & 0xff;
-  TH0= t0cnt >> 8;
-  T0idozito1(0);
-  T0beallit(t0cnt);
-  ET0= 1;
-  T0start();
-  EA= 1;
-  print("\nStart\n");
-
-  t0cnt= 10;
-  for (;;)
-    {
-      if (serial_received())
-	process();
-      if (!t0cnt)
-	{
-	  print_c(c);
-	  if (++c > max)
-	    c= min;
-	  t0cnt= 10;
-	}
-    }
-}
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/tim_ser.mk sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/tim_ser.mk
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/tim_ser.mk	2019-03-14 14:43:24.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/tim_ser.mk	1970-01-01 00:00:00.000000000 +0000
@@ -1,7 +0,0 @@
-MAIN		= tim_ser
-
-OTHERS		= timer t0 serial print
-
-include sdcc.mk
-
-MODEL		= small
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/xc88x.h sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/xc88x.h
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/test/xc88x.h	2017-01-06 07:36:33.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/test/xc88x.h	1970-01-01 00:00:00.000000000 +0000
@@ -1,14 +0,0 @@
-#ifndef XC88X_HEADER
-#define XC88X_HEADER
-
-__sfr __at (0xB2) MD0;
-__sfr __at (0xB3) MD1;
-__sfr __at (0xB4) MD2;
-__sfr __at (0xB5) MD3;
-__sfr __at (0xB6) MD4;
-__sfr __at (0xB7) MD5;
-
-__sfr __at (0xB1) MDUCON;
-__sfr __at (0xB0) MDUSTAT;
-
-#endif
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/timer0.cc sdcc-4.2.0+dfsg/sim/ucsim/s51.src/timer0.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/timer0.cc	2019-04-02 10:46:33.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/timer0.cc	2022-01-26 16:35:40.000000000 +0000
@@ -25,10 +25,12 @@
 02111-1307, USA. */
 /*@1@*/
 
+#include 
+
 #include "timer0cl.h"
 #include "regs51.h"
 #include "types51.h"
-#include "uc51cl.h"
+//#include "uc51cl.h"
 
 
 cl_timer0::cl_timer0(class cl_uc *auc, int aid, const char *aid_string):
@@ -239,13 +241,13 @@
   while (cycles--)
     {
       // mod 0, TH= 8 bit t/c, TL= 5 bit precounter
-      t_mem tl= cell_tl->add(1);
+      t_mem tl= cell_tl->set(cell_tl->get() + 1);
       if ((tl & 0x1f) == 0)
 	{
 	  cell_tl->set(0);
-	  if (!cell_th->add(1))
+	  if (!cell_th->set(cell_th->get() + 1))
 	    {
-	      cell_tcon->set_bit1(mask_TF);
+	      cell_tcon->set(cell_tcon->get() | mask_TF);
 	      overflow();
 	    }
 	}
@@ -280,11 +282,11 @@
   while (cycles--)
     {
       // mod 1 TH+TL= 16 bit t/c
-      if (!cell_tl->add(1))
+      if (!cell_tl->set(cell_tl->get() + 1))
 	{
-	  if (!cell_th->add(1))
+	  if (!cell_th->set(cell_th->get() + 1))
 	    {
-	      cell_tcon->set_bit1(mask_TF);
+	      cell_tcon->set(cell_tcon->get() | mask_TF);
 	      overflow();
 	    }
 	}
@@ -320,10 +322,10 @@
   while (cycles--)
     {
       // mod 2 TL= 8 bit t/c auto reload from TH
-      if (!cell_tl->add(1))
+      if (!cell_tl->set(cell_tl->get() + 1))
 	{
 	  cell_tl->set(cell_th->get());
-	  cell_tcon->set_bit1(mask_TF);
+	  cell_tcon->set(cell_tcon->get() | mask_TF);
 	  //printf("timer%d overflow %d (%d) %d\n",id,uc->ticks->ticks,i,startt+(i*12));
 	  overflow();
 	}
@@ -359,9 +361,9 @@
 
   while (cycles--)
     {
-      if (!cell_tl->add(1))
+      if (!cell_tl->set(cell_tl->get() + 1))
 	{
-	  cell_tcon->set_bit1(mask_TF);
+	  cell_tcon->set(cell_tcon->get() | mask_TF);
 	  overflow();
 	}
     }
@@ -370,8 +372,8 @@
   if ((cell_tcon->get() & bmTR1) != 0)
     while (cyc--)
       {
-	if (!cell_th->add(1))
-	  cell_tcon->set_bit1(bmTF1);
+	if (!cell_th->set(cell_th->get() + 1))
+	  cell_tcon->set(cell_tcon->get() | bmTF1);
       }
   return(0);
 }
@@ -387,7 +389,7 @@
 {
   struct ev_port_changed *ep= (struct ev_port_changed *)params;
 
-  if (where->cathegory == HW_PORT &&
+  if (where->category == HW_PORT &&
       he == EV_PORT_CHANGED &&
       ep->id == 3)
     {
@@ -421,12 +423,16 @@
     }
   else
     on= TR;
+  class cl_memory_cell *iec= NULL;
+  if (sfr) iec= sfr->get_cell(IE);
+  u8_t ier= 0;
+  if (iec) ier= iec->get();
   con->dd_printf(" %s", on?"ON":"OFF");
   con->dd_printf(" irq=%c", (cell_tcon->get()&mask_TF)?'1':'0');
-  con->dd_printf(" %s", sfr?"?":((sfr->get(IE)&bmET0)?"en":"dis"));
+  con->dd_printf(" %s", (ier&bmET0)?"en":"dis");
   con->dd_printf(" prio=%d", uc->priority_of(bmPT0));
   con->dd_printf("\n");
-  print_cfg_info(con);
+  //print_cfg_info(con);
 }
 
 
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/timer0cl.h sdcc-4.2.0+dfsg/sim/ucsim/s51.src/timer0cl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/timer0cl.h	2019-04-02 10:46:33.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/timer0cl.h	2020-08-22 10:25:08.000000000 +0000
@@ -50,7 +50,7 @@
 public:
   cl_timer0(class cl_uc *auc, int aid, const char *aid_string);
   virtual int init(void);
-  //virtual char *cfg_help(t_addr addr);
+  //virtual const char *cfg_help(t_addr addr);
   
   virtual void added_to_uc(void);
 
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/timer1.cc sdcc-4.2.0+dfsg/sim/ucsim/s51.src/timer1.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/timer1.cc	2019-04-02 10:46:33.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/timer1.cc	2022-01-26 16:35:40.000000000 +0000
@@ -42,12 +42,6 @@
   return(0);
 }*/
 
-/*void
-cl_timer1::added(class cl_hw *new_hw)
-{
-  if (new_hw->cathegory == HW_UART)
-    hws_to_inform->add(new_hw);
-}*/
 
 int
 cl_timer1::do_mode3(int cycles)
@@ -68,7 +62,9 @@
   //int tmod= cell_tmod->get();
   int on;
   class cl_address_space *sfr= uc->address_space(MEM_SFR_ID);
-
+  class cl_memory_cell *iec= NULL;
+  u8_t ier= 0;
+  
   con->dd_printf("%s[%d] 0x%04x", id_string, id,
 		 256*cell_th->get()+cell_tl->get());
   //int mode= (tmod & (bmM11|bmM01)) >> 4;
@@ -81,12 +77,14 @@
     }
   else
     on= cell_tcon->get() & mask_TR;
+  if (sfr) iec= sfr->get_cell(IE);
+  if (iec) ier= iec->get();
   con->dd_printf(" %s", on?"ON":"OFF");
   con->dd_printf(" irq=%c", (cell_tcon->get()&mask_TF)?'1':'0');
-  con->dd_printf(" %s", sfr?"?":((sfr->get(IE)&bmET1)?"en":"dis"));
+  con->dd_printf(" %s", (ier&bmET1)?"en":"dis");
   con->dd_printf(" prio=%d", uc->priority_of(bmPT1));
   con->dd_printf("\n");
-  print_cfg_info(con);
+  //print_cfg_info(con);
 }
 
 
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/timer1cl.h sdcc-4.2.0+dfsg/sim/ucsim/s51.src/timer1cl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/timer1cl.h	2019-04-02 10:46:33.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/timer1cl.h	2020-08-22 10:25:08.000000000 +0000
@@ -41,7 +41,7 @@
 public:
   cl_timer1(class cl_uc *auc, int aid, const char *aid_string);
   //virtual int init(void);
-  //virtual char *cfg_help(t_addr addr);
+  //virtual const char *cfg_help(t_addr addr);
 
   //virtual void new_hw_added(class cl_hw *new_hw);
   //virtual ulong read(class cl_mem *mem, long addr);
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/timer2.cc sdcc-4.2.0+dfsg/sim/ucsim/s51.src/timer2.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/timer2.cc	2019-04-02 10:46:33.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/timer2.cc	2022-01-26 16:35:40.000000000 +0000
@@ -178,7 +178,7 @@
 {
   if (EXEN2 && t2ex_edge)
     {
-      cell_tcon->set_bit1(bmEXF2);
+      cell_tcon->set(cell_tcon->get() | bmEXF2);
       t2ex_edge= 0;
     }
 
@@ -192,8 +192,8 @@
 
   while (cycles--)
     {
-      if (!cell_tl->add(1))
-	if (!cell_th->add(1))
+      if (!cell_tl->set(cell_tl->get() + 1))
+	if (!cell_th->set(cell_th->get() + 1))
 	  {
 	    cell_th->set(cell_rcap2h->get());
 	    cell_tl->set(cell_rcap2l->get());
@@ -213,7 +213,7 @@
 {
   if (EXEN2 && t2ex_edge)
     {
-      cell_tcon->set_bit1(bmEXF2);
+      cell_tcon->set(cell_tcon->get() | bmEXF2);
       cell_rcap2h->set(cell_th->get());
       cell_rcap2l->set(cell_tl->get());
       t2ex_edge= 0;
@@ -225,10 +225,10 @@
   if (C_T)
     (cycles= T_edge), T_edge= 0;
 
-  if (!cell_tl->add(1))
+  if (!cell_tl->set(cell_tl->get() + 1))
     {
-      if (!cell_th->add(1))
-	cell_tcon->set_bit1(bmTF2);
+      if (!cell_th->set(cell_th->get() + 1))
+	cell_tcon->set(cell_tcon->get() | bmTF2);
     }
 }
 
@@ -242,7 +242,7 @@
 {
   if (EXEN2 && t2ex_edge)
     {
-      cell_tcon->set_bit1(bmEXF2);
+      cell_tcon->set(cell_tcon->get() | bmEXF2);
       cell_th->set(cell_rcap2h->get());
       cell_tl->set(cell_rcap2l->get());
       t2ex_edge= 0;
@@ -254,11 +254,11 @@
   if (C_T)
     (cycles= T_edge), T_edge= 0;
 
-  if (!cell_tl->add(1))
+  if (!cell_tl->set(cell_tl->get() + 1))
     {
-      if (!cell_th->add(1))
+      if (!cell_th->set(cell_th->get() + 1))
 	{
-	  cell_tcon->set_bit1(mask_TF);
+	  cell_tcon->set(cell_tcon->get() | mask_TF);
 	  cell_th->set(cell_rcap2h->get());
 	  cell_tl->set(cell_rcap2l->get());
 	}
@@ -280,11 +280,11 @@
     {
       // UP
       while (cycles--)
-	if (!cell_tl->add(1))
+	if (!cell_tl->set(cell_tl->get() + 1))
 	  {
-	    if (!cell_th->add(1))
+	    if (!cell_th->set(cell_th->get() + 1))
 	      {
-		cell_tcon->set_bit1(mask_TF);
+		cell_tcon->set(cell_tcon->get() | mask_TF);
 		cell_th->set(cell_rcap2h->get());
 		cell_tl->set(cell_rcap2l->get());
 		toggle= true;
@@ -297,14 +297,14 @@
       while (cycles--)
 	{
 	  t_mem l, h;
-	  if ((l= cell_tl->add(-1)) == 0xff)
-	    h= cell_th->add(-1);
+	  if ((l= cell_tl->set(cell_tl->get() - 1)) == 0xff)
+	    h= cell_th->set(cell_th->get() - 1);
 	  else
 	    h= cell_th->get();
 	  if ((u16_t)(h*256+l) <
 	      (u16_t)(cell_rcap2h->get()*256+cell_rcap2l->get()))
 	    {
-	      cell_tcon->set_bit1(mask_TF);
+	      cell_tcon->set(cell_tcon->get() | mask_TF);
 	      cell_th->set(0xff);
 	      cell_tl->set(0xff);
 	      toggle= true;
@@ -325,7 +325,7 @@
 {
   if (EXEN2 && t2ex_edge)
     {
-      cell_tcon->set_bit1(bmEXF2);
+      cell_tcon->set(cell_tcon->get() | bmEXF2);
       t2ex_edge= 0;
     }
 
@@ -339,8 +339,8 @@
 
   while (cycles--)
     {
-      if (!cell_tl->add(1))
-	if (!cell_th->add(1))
+      if (!cell_tl->set(cell_tl->get() + 1))
+	if (!cell_th->set(cell_th->get() + 1))
 	  {
 	    cell_th->set(cell_rcap2h->get());
 	    cell_tl->set(cell_rcap2l->get());
@@ -362,7 +362,7 @@
 {
   struct ev_port_changed *ep= (struct ev_port_changed *)params;
 
-  if (where->cathegory == HW_PORT &&
+  if (where->category == HW_PORT &&
       he == EV_PORT_CHANGED &&
       ep->id == 1)
     {
@@ -382,7 +382,9 @@
 cl_timer2::print_info(class cl_console_base *con)
 {
   int t2con= cell_tcon->get();
-
+  class cl_memory_cell *iec= sfr?(sfr->get_cell(IE)):NULL;
+  u8_t ier= iec?(iec->get()):0;
+  
   con->dd_printf("%s[%d] 0x%04x", id_string, id,
 		 256*cell_th->get()+cell_tl->get());
   if (RCLK || TCLK)
@@ -400,10 +402,10 @@
   con->dd_printf(" %s", (C_T)?"counter":"timer");
   con->dd_printf(" %s", (TR)?"ON":"OFF");
   con->dd_printf(" irq=%c", (t2con&bmTF2)?'1':'0');
-  con->dd_printf(" %s", sfr?"?":((sfr->get(IE)&bmET2)?"en":"dis"));
+  con->dd_printf(" %s", (ier&bmET2)?"en":"dis");
   con->dd_printf(" prio=%d", uc->priority_of(bmPT2));
   con->dd_printf("\n");
-  print_cfg_info(con);
+  //print_cfg_info(con);
 }
 
 
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/timer2cl.h sdcc-4.2.0+dfsg/sim/ucsim/s51.src/timer2cl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/timer2cl.h	2019-04-02 10:46:33.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/timer2cl.h	2020-08-22 10:25:08.000000000 +0000
@@ -65,7 +65,7 @@
 public:
   cl_timer2(class cl_uc *auc, int aid, const char *aid_string, int afeautres);
   virtual int init(void);
-  //virtual char *cfg_help(t_addr addr);
+  //virtual const char *cfg_help(t_addr addr);
 
   virtual void added_to_uc(void);
   //virtual void new_hw_added(class cl_hw *new_hw);
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/types51.h sdcc-4.2.0+dfsg/sim/ucsim/s51.src/types51.h
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/types51.h	2016-07-26 21:10:26.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/types51.h	2021-04-25 20:38:36.000000000 +0000
@@ -30,17 +30,30 @@
 
 #include "ddconfig.h"
 
-
+/*
 #define SET_BIT(newbit, reg, bitmask) \
 if (newbit) \
   (mem(MEM_SFR))->set_bit1((reg), (bitmask)); \
 else \
   (mem(MEM_SFR))->set_bit0((reg), (bitmask));
+*/
+#define SET_BIT(newbit, reg, bitmask)				\
+  if (newbit)							\
+    (mem(MEM_SFR))->set(mem(MEM_SFR)->get(reg) | (bitmask));	\
+  else								\
+    (mem(MEM_SFR))->set(mem(MEM_SFR)->get(reg) & ~(bitmask));
+/*
 #define SFR_SET_BIT(newbit, reg, bitmask) \
 if (newbit) \
   sfr->set_bit1((reg), (bitmask)); \
 else \
   sfr->set_bit0((reg), (bitmask));
+*/
+#define SFR_SET_BIT(newbit, reg, bitmask)	\
+  if (newbit)					\
+    sfr->set(reg, sfr->get(reg) | (bitmask));	\
+  else						\
+    sfr->set(reg, sfr->get(reg) & ~(bitmask));
 //#define GET_C     (get_mem(MEM_SFR, PSW) & bmCY)
 //#define SFR_GET_C (sfr->get(PSW) & bmCY)
 //#define SET_C(newC) SET_BIT((newC), PSW, bmCY)
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/uc251.cc sdcc-4.2.0+dfsg/sim/ucsim/s51.src/uc251.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/uc251.cc	2017-01-24 13:53:15.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/uc251.cc	2020-03-27 20:18:53.000000000 +0000
@@ -25,9 +25,9 @@
 02111-1307, USA. */
 /*@1@*/
 
-#include "ddconfig.h"
+//#include "ddconfig.h"
 
-#include 
+//#include 
 
 #include "uc251cl.h"
 
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/uc320.cc sdcc-4.2.0+dfsg/sim/ucsim/s51.src/uc320.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/uc320.cc	2019-05-24 06:44:15.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/uc320.cc	2020-03-27 20:18:53.000000000 +0000
@@ -24,14 +24,14 @@
 02111-1307, USA. */
 /*@1@*/
 
-#include "ddconfig.h"
+//#include "ddconfig.h"
 
-#include 
-#include 
-#include 
-#include "i_string.h"
+//#include 
+//#include 
+//#include 
+//#include "i_string.h"
 
-#include "glob.h"
+//#include "glob.h"
 #include "uc320cl.h"
 #include "regs51.h"
 
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/uc380.cc sdcc-4.2.0+dfsg/sim/ucsim/s51.src/uc380.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/uc380.cc	2017-04-07 20:59:49.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/uc380.cc	2021-04-25 20:38:36.000000000 +0000
@@ -25,6 +25,8 @@
 02111-1307, USA. */
 /*@1@*/
 
+//#include 
+
 #include "portcl.h"
 
 #include "uc380cl.h"
@@ -54,7 +56,7 @@
   add_hw(p4);
   p4->init();
 
-  class cl_port_ui *d= (class cl_port_ui *)get_hw(cchars("dport"), NULL);
+  class cl_port_ui *d= (class cl_port_ui *)get_hw("dport", NULL);
   if (d)
     {
       class cl_port_data pd;
@@ -64,7 +66,7 @@
       pd.set_name("P4");
       pd.cell_p  = p4->cell_p;
       pd.cell_in = p4->cell_in;
-      pd.keyset  = chars(keysets[4]);
+      pd.keyset  = keysets[4];
       pd.basx    = 1;
       pd.basy    = 4+7;
       d->add_port(&pd, 4);
@@ -76,7 +78,7 @@
 {
   cl_uc52::make_chips();
   sfr_chip->set_name("sfr_0_chip");
-  sfr_f_chip= new cl_memory_chip("sfr_f_chip", 0x80, 8, 0);
+  sfr_f_chip= new cl_chip8("sfr_f_chip", 0x80, 8, 0);
   sfr_f_chip->init();
   memchips->add(sfr_f_chip);
 }
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/uc390.cc sdcc-4.2.0+dfsg/sim/ucsim/s51.src/uc390.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/uc390.cc	2019-07-02 08:44:01.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/uc390.cc	2021-05-07 20:42:18.000000000 +0000
@@ -35,22 +35,22 @@
 // strcpy (mem(MEM_ROM) ->addr_format, "0x%06x");
 // strcpy (mem(MEM_XRAM)->addr_format, "0x%06x");
 
-#include "ddconfig.h"
+//#include "ddconfig.h"
 
 #include 
 #include 
 #include 
-#include "i_string.h"
+#include 
+//#include "i_string.h"
 
 #include "glob.h"
 #include "uc390cl.h"
 #include "regs51.h"
 #include "uc390hwcl.h"
 
-
-#include "uc52cl.h"
+//#include "uc52cl.h"
 #include "regs51.h"
-#include "timer2cl.h"
+//#include "timer2cl.h"
 
 /*
  * Names of instructions
@@ -403,23 +403,23 @@
 void
 cl_uc390::make_chips(void)
 {
-  rom_chip= new cl_memory_chip("rom_chip", 0x20000, 8, 0xff);
+  rom_chip= new cl_chip8("rom_chip", 0x20000, 8, 0xff);
   rom_chip->init();
   memchips->add(rom_chip);
 
-  iram_chip= new cl_memory_chip("iram_chip", 0x100, 8, 0);
+  iram_chip= new cl_chip8("iram_chip", 0x100, 8, 0);
   iram_chip->init();
   memchips->add(iram_chip);
 
-  xram_chip= new cl_memory_chip("xram_chip", 0x100000+128, 8, 0);
+  xram_chip= new cl_chip8("xram_chip", 0x100000+128, 8, 0);
   xram_chip->init();
   memchips->add(xram_chip);
 
-  ixram_chip= new cl_memory_chip("ixram_chip", 0x1000, 8);
+  ixram_chip= new cl_chip8("ixram_chip", 0x1000, 8);
   ixram_chip->init();
   memchips->add(ixram_chip);
 
-  sfr_chip= new cl_memory_chip("sfr_chip", 0x80, 8, 0);
+  sfr_chip= new cl_chip8("sfr_chip", 0x80, 8, 0);
   sfr_chip->init();
   memchips->add(sfr_chip);
 }
@@ -448,15 +448,10 @@
 void
 cl_uc390::decode_dptr(void)
 {
-  cl_var *v;
-  vars->add(v= new cl_var(chars("dpl"), sfr, 0x82, ""));
-  v->init();
-  vars->add(v= new cl_var(chars("DPL"), sfr, 0x82, ""));
-  v->init();
-  vars->add(v= new cl_var(chars("dph"), sfr, 0x83, ""));
-  v->init();
-  vars->add(v= new cl_var(chars("DPH"), sfr, 0x83, ""));
-  v->init();
+  vars->add("dpl", sfr, 0x82, 7, 0, "");
+  vars->add("DPL", sfr, 0x82, 7, 0, "");
+  vars->add("dph", sfr, 0x83, 7, 0, "");
+  vars->add("DPH", sfr, 0x83, 7, 0, "");
 }
 
 
@@ -498,7 +493,7 @@
 
 
 t_mem
-cl_uc390::read_mem(char *id/*enum mem_class type*/, t_addr addr)
+cl_uc390::read_mem(const char *id/*enum mem_class type*/, t_addr addr)
 {
 
   if (strcmp(/*type*/id,/* == */MEM_XRAM_ID)==0 &&
@@ -512,7 +507,7 @@
 }
 
 t_mem
-cl_uc390::get_mem (char *id/*enum mem_class type*/, t_addr addr)
+cl_uc390::get_mem (const char *id/*enum mem_class type*/, t_addr addr)
 {
   if (strcmp(/*type*/id/* == */,MEM_XRAM_ID)==0 &&
       addr >= 0x400000 &&
@@ -525,7 +520,7 @@
 }
 
 void
-cl_uc390::write_mem (char *id/*enum mem_class type*/, t_addr addr, t_mem val)
+cl_uc390::write_mem (const char *id/*enum mem_class type*/, t_addr addr, t_mem val)
 {
   if (strcmp(/*type ==*/id, MEM_XRAM_ID)==0 &&
       addr >= 0x400000 &&
@@ -538,7 +533,7 @@
 }
 
 void
-cl_uc390::set_mem (/*enum mem_class type*/char *id, t_addr addr, t_mem val)
+cl_uc390::set_mem (/*enum mem_class type*/const char *id, t_addr addr, t_mem val)
 {
   if (/*type == */strcmp(id,MEM_XRAM_ID)==0 &&
       addr >= 0x400000 &&
@@ -559,11 +554,11 @@
 {
   t_addr sp;
 
-  sp = sfr->wadd (SP, 1);
+  sp = sfr->write(SP, sfr->read(SP) + 1);
   if (sfr->get (ACON) & 0x04) /* SA: 10 bit stack */
     {
       if (sp == 0) /* overflow SP */
-        sfr->wadd (R51_ESP, 1);
+        sfr->write(R51_ESP, sfr->read(R51_ESP) + 1);
       sp += (sfr->read (R51_ESP) & 0x3) * 256;
       write_mem (MEM_IXRAM_ID, sp, uc); // fixme
     }
@@ -587,9 +582,9 @@
       sp = sfr->read (SP);
       sp += (sfr->read (R51_ESP) & 0x3) * 256;
       temp = read_mem (MEM_IXRAM_ID, sp); // fixme
-      sp = sfr->wadd (SP, -1);
+      sp = sfr->write(SP, sfr->read(SP) - 1);
       if (sp == 0xff) /* underflow SP */
-        sfr->wadd (R51_ESP, -1);
+        sfr->write(R51_ESP, sfr->read(R51_ESP) - 1);
       return temp;
     }
   else
@@ -598,7 +593,7 @@
 
       stck = iram->get_cell (sfr->get (SP));
       temp = stck->read();
-      sp = sfr->wadd (SP, -1);
+      sp = sfr->write(SP, sfr->read(SP) - 1);
       return temp;
     }
 }
@@ -979,11 +974,11 @@
 
       h = (code >> 5) & 0x07;
       l = fetch();
-      sp = sfr->wadd (SP, 1);
+      sp = sfr->write(SP, sfr->read(SP) + 1);
       stck = iram->get_cell (sp);
       stck->write (PC & 0xff); // push low byte
 
-      sp = sfr->wadd (SP, 1);
+      sp = sfr->write(SP, sfr->read(SP) + 1);
       stck = iram->get_cell (sp);
       stck->write ((PC >> 8) & 0xff); // push high byte
       PC = (PC & 0xf800) | (h*256 + l);
@@ -1137,24 +1132,32 @@
 }
 
 char *
-cl_uc390::disass (t_addr addr, const char *sep)
+cl_uc390::disass (t_addr addr)
 {
-  char work[256], temp[200]/*, c[2]*/;
-  char *buf, *p, *b, *t, *org_b;
+  chars work= chars(), temp= chars();
+  const char *b;
+  t_addr operand;
   t_mem code;
   uchar dps;
-
+  bool first= true;
+  
   if (! (sfr->get (ACON) & 0x02)) /* AM1 set: 24-bit flat? */
-    return cl_51core::disass (addr, sep);
+    return cl_51core::disass (addr);
   code = rom->get(addr);
 
-  p = work;
-  b = org_b = strdup(dis_tbl()[code].mnemonic);
+  work= "";
+  b = dis_tbl()[code].mnemonic;
   while (*b)
     {
+      if ((*b == ' ') && first)
+	{
+	  first= false;
+	  while (work.len() < 6) work.append(' ');
+	}
       if (*b == '%')
         {
           b++;
+	  temp= "";
           switch (*(b++))
             {
             case 'A': // absolute address
@@ -1164,94 +1167,68 @@
               //          (((code >> 5) & 0x07) * 256 +
               //          rom->get (addr + 1)));
 
-              sprintf (temp, /*"%06lx"*/rom->addr_format,
-                       (addr & 0xf80000L) |
-                       (((code >> 5) & 0x07) * (256 * 256) +
-                       (rom->get (addr + 1) * 256) +
-                        rom->get (addr + 2)));
+	      operand= (addr & 0xf80000L) |
+		       (((code >> 5) & 0x07) * (256 * 256) +
+		        (rom->get (addr + 1) * 256) +
+		        rom->get (addr + 2));
+              temp.format(rom->addr_format, operand);
+	      addr_name(operand, rom, &temp);
               break;
             case 'l': // long address
-              sprintf (temp, "%06lx",
-                       rom->get (addr + 1) * (256*256L) +
-                       rom->get (addr + 2) * 256 +
-                       rom->get (addr + 3));
-                       // rom->get (addr + 1) * 256 + rom->get (addr + 2));
+	      operand= rom->get (addr + 1) * (256*256L) +
+		       rom->get (addr + 2) * 256 +
+		       rom->get (addr + 3);
+              temp.format(rom->addr_format, operand);
+	      addr_name(operand, rom, &temp);
               break;
             case 'a': // addr8 (direct address) at 2nd byte
-	      daddr_name(rom->get(addr+1), temp);
+	      daddr_name(rom->get(addr+1), &temp);
               break;
             case '8': // addr8 (direct address) at 3rd byte
-	      daddr_name(rom->get(addr+2), temp);
+	      daddr_name(rom->get(addr+2), &temp);
               break;
             case 'b': // bitaddr at 2nd byte
 	      {
 		t_addr ba = rom->get (addr+1);
-		/*if (get_name (ba, bit_tbl(), temp))
-		  break;
-		if (ba<128)
-		  addr_name((ba/8)+32,iram,temp);
-		else
-		  addr_name(ba&0xf8,sfr,temp);
-		strcat (temp, ".");
-		sprintf (c, "%1d", (int)(ba & 0x07));
-		strcat (temp, c);
-		break;*/
-		baddr_name(ba, temp);
+		baddr_name(ba, &temp);
 		break;
 	      }
             case 'r': // rel8 address at 2nd byte
-              sprintf (temp, "%04x",
-                       /*t_addr*/int (addr + 2 + (signed char) (rom->get (addr + 1))));
+	      operand= (u16_t)(addr + 2 + (i8_t)(rom->get(addr + 1)));
+              temp.format(rom->addr_format, operand);
+	      addr_name(operand, rom, &temp);
               break;
             case 'R': // rel8 address at 3rd byte
-              sprintf (temp, "%04x",
-                       /*t_addr*/int (addr + 3 + (signed char) (rom->get (addr + 2))));
+	      operand= (u16_t)(addr + 3 + (i8_t)(rom->get(addr + 2)));
+              temp.format(rom->addr_format, operand);
+	      addr_name(operand, rom, &temp);
               break;
             case 'd': // data8 at 2nd byte
-              sprintf (temp, "%02x", (int)rom->get (addr + 1));
+              temp.format("0x%02x", (int)rom->get (addr + 1));
               break;
             case 'D': // data8 at 3rd byte
-              sprintf (temp, "%02x", (int)rom->get (addr + 2));
+              temp.format("0x%02x", (int)rom->get (addr + 2));
               break;
             case 'i': // inc/dec dptr
+              // N.B. The direction depends on DPS at the time the instruction is
+              // executed NOT the time we disassemble it. This is only going to
+              // be guaranteed correct when disassembling on break.
+              // The correct assembler mnemonic here is INC even if it decrements
+              // when executed!
               dps = sfr->get(DPS);
-              sprintf (temp, ((dps & 0x01) ? (dps & 0x80) : (dps & 0x40)) ? "DEC" : "INC");
+              temp.format(((dps & 0x01) ? (dps & 0x80) : (dps & 0x40)) ? "DEC" : "INC");
               break;
             default:
-              strcpy (temp, "?");
+	    temp= "?";
               break;
             }
-          t = temp;
-          while (*t)
-            *p++ = *t++;
+	  work+= temp;
         }
       else
-        *p++ = *b++;
+        work+= *b++;
     }
-  *p = '\0';
 
-  p = strchr (work, ' ');
-  if (!p)
-    {
-      buf = strdup (work);
-      return buf;
-    }
-  if (sep == NULL)
-    buf = (char *) malloc (6 + strlen (p) + 1);
-  else
-    buf = (char *) malloc ((p - work) + strlen (sep) + strlen (p) + 1);
-  for (p = work, b = buf; *p != ' '; p++, b++)
-    *b = *p;
-  p++;
-  *b = '\0';
-  if (sep == NULL)
-    while (strlen (buf) < 6)
-      strcat (buf, " ");
-  else
-    strcat (buf, sep);
-  strcat (buf, p);
-  free(org_b);
-  return buf;
+  return strdup(work.c_str());
 }
 
 void
@@ -1261,6 +1238,7 @@
   t_mem data;
   uchar dps;
 
+  con->dd_color("answer");
   if (! (sfr->get (ACON) & 0x02)) /* AM1 set: 24-bit flat? */
     {
       cl_51core::print_regs (con);
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/uc390cl.h sdcc-4.2.0+dfsg/sim/ucsim/s51.src/uc390cl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/uc390cl.h	2017-02-24 11:48:49.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/uc390cl.h	2021-05-02 15:29:48.000000000 +0000
@@ -55,10 +55,10 @@
   //virtual t_addr get_mem_size (enum mem_class type);
 
   // manipulating memories
-  virtual t_mem read_mem (char *id/*enum mem_class type*/, t_addr addr);
-  virtual t_mem get_mem (char *id/*enum mem_class type*/, t_addr addr);
-  virtual void  write_mem (char *id/*enum mem_class type*/, t_addr addr, t_mem val);
-  virtual void  set_mem (char *id/*enum mem_class type*/, t_addr addr, t_mem val);
+  virtual t_mem read_mem (const char *id/*enum mem_class type*/, t_addr addr);
+  virtual t_mem get_mem (const char *id/*enum mem_class type*/, t_addr addr);
+  virtual void  write_mem (const char *id/*enum mem_class type*/, t_addr addr, t_mem val);
+  virtual void  set_mem (const char *id/*enum mem_class type*/, t_addr addr, t_mem val);
 
   /* mods for dual-dptr */
   virtual int instruction_a3/*inst_inc_dptr*/(t_mem/*uchar*/ code);		// a3
@@ -82,7 +82,7 @@
 
   /* mods for disassembly of flat24 */
   virtual struct dis_entry *dis_tbl(void);
-  virtual char * disass(t_addr addr, const char *sep);
+  virtual char * disass(t_addr addr);
   virtual void   print_regs(class cl_console_base *con);
 
 protected:
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/uc390hw.cc sdcc-4.2.0+dfsg/sim/ucsim/s51.src/uc390hw.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/uc390hw.cc	2019-04-02 10:46:33.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/uc390hw.cc	2022-01-18 21:40:45.000000000 +0000
@@ -25,15 +25,15 @@
 02111-1307, USA. */
 /*@1@*/
 
-#include "ddconfig.h"
+//#include "ddconfig.h"
 
-#include 
-#include 
+//#include 
+//#include 
 
 // local
 #include "uc390hwcl.h"
 #include "regs51.h"
-#include "uc51cl.h"
+//#include "uc51cl.h"
 
 
 cl_uc390_hw::cl_uc390_hw (class cl_uc *auc):
@@ -76,7 +76,7 @@
   if (cell == cell_exif)
     {
       if (ctm_ticks &&
-          uc390->ticks->ticks >= ctm_ticks + 65535)
+          uc390->ticks->get_ticks() >= ctm_ticks + 65535)
 	{
 	  ctm_ticks = 0;
 	  cell->set (cell->get() | 0x08); /* set CKRDY */
@@ -94,7 +94,7 @@
     {
       /* Bit 0 (BGS) is TA-protected */
       if (timed_access_state != 2 ||
-          timed_access_ticks + 2*12 < uc390->ticks->ticks) // fixme: 3 cycles
+          timed_access_ticks + 2*12 < uc390->ticks->get_ticks()) // fixme: 3 cycles
 	*val = (*val & ~0x01) | (cell_exif->get() & 0x01);
 
       /* CKRDY and RGMD are read-only */
@@ -104,7 +104,7 @@
     {
       /* P4CNT is TA-protected */
       if (timed_access_state != 2 ||
-          timed_access_ticks + 2*12 < uc390->ticks->ticks) // fixme: 3 cycles
+          timed_access_ticks + 2*12 < uc390->ticks->get_ticks()) // fixme: 3 cycles
         *val = cell_p4cnt->get();
       *val |= 0x80; /* always 1 */
     }
@@ -112,7 +112,7 @@
     {
       /* ACON is TA-protected */
       if (timed_access_state != 2 ||
-          timed_access_ticks + 2*12 < uc390->ticks->ticks) // fixme: 3 cycles
+          timed_access_ticks + 2*12 < uc390->ticks->get_ticks()) // fixme: 3 cycles
         *val = cell_acon->get();
       else
         {
@@ -126,14 +126,14 @@
     {
       /* Bits 0...2 are TA-protected */
       if (timed_access_state != 2 ||
-          timed_access_ticks + 2*12 < uc390->ticks->ticks) // fixme: 3 cycles
+          timed_access_ticks + 2*12 < uc390->ticks->get_ticks()) // fixme: 3 cycles
 	*val = (*val & ~0x07) | (cell_p5cnt->get() & 0x07);
     }
   else if (cell == cell_c0c)
     {
       /* Bit 3 (CRST) is TA-protected */
       if (timed_access_state != 2 ||
-          timed_access_ticks + 2*12 < uc390->ticks->ticks) // fixme: 3 cycles
+          timed_access_ticks + 2*12 < uc390->ticks->get_ticks()) // fixme: 3 cycles
 	*val = (*val & ~0x08) | (cell_c0c->get() & 0x08);
     }
   else if (cell == cell_pmr)
@@ -141,7 +141,7 @@
       /* fixme: check previous state */
       if ((*val & 0xd0) == 0x90) /* CD1:CD0 set to 10, CTM set */
         {
-	  ctm_ticks = uc390->ticks->ticks;
+	  ctm_ticks = uc390->ticks->get_ticks();
 	  cell_exif->set (cell_exif->get() & ~0x08); /* clear CKRDY */
         }
       else
@@ -152,7 +152,7 @@
     {
       /* MCON is TA-protected */
       if (timed_access_state != 2 ||
-          timed_access_ticks + 2*12 < uc390->ticks->ticks) // fixme: 3 cycles
+          timed_access_ticks + 2*12 < uc390->ticks->get_ticks()) // fixme: 3 cycles
         *val = cell_mcon->get();
       else
         /* lockout: IDM1:IDM0 and SA can't be set at the same time */
@@ -166,14 +166,14 @@
       if (*val == 0xAA)
         {
           timed_access_state = 1;
-          timed_access_ticks = uc390->ticks->ticks;
+          timed_access_ticks = uc390->ticks->get_ticks();
         }
       else if (*val == 0x55 &&
                timed_access_state == 1 &&
-               timed_access_ticks + 2*12 >= uc390->ticks->ticks) // fixme: 3 cycles
+               timed_access_ticks + 2*12 >= uc390->ticks->get_ticks()) // fixme: 3 cycles
         {
           timed_access_state = 2;
-          timed_access_ticks = uc390->ticks->ticks;
+          timed_access_ticks = uc390->ticks->get_ticks();
         }
       else
         timed_access_state = 0;
@@ -182,7 +182,7 @@
     {
       /* COR is TA-protected */
       if (timed_access_state != 2 ||
-          timed_access_ticks + 2*12 < uc390->ticks->ticks) // fixme: 3 cycles
+          timed_access_ticks + 2*12 < uc390->ticks->get_ticks()) // fixme: 3 cycles
 	*val = cell_cor->get();
     }
   else if (cell == cell_mcnt0)
@@ -209,14 +209,14 @@
     {
       /* Bits 0, 1, 3 and 6 are TA-protected */
       if (timed_access_state != 2 ||
-          timed_access_ticks + 2*12 < uc390->ticks->ticks) // fixme: 3 cycles
+          timed_access_ticks + 2*12 < uc390->ticks->get_ticks()) // fixme: 3 cycles
 	*val = (*val & ~0x4b) | (cell_wdcon->get() & 0x4b);
     }
   else if (cell == cell_c1c)
     {
       /* Bit 3 (CRST) is TA-protected */
       if (timed_access_state != 2 ||
-          timed_access_ticks + 2*12 < uc390->ticks->ticks) // fixme: 3 cycles
+          timed_access_ticks + 2*12 < uc390->ticks->get_ticks()) // fixme: 3 cycles
 	*val = (*val & ~0x08) | (cell_c1c->get() & 0x08);
     }
 }
@@ -262,7 +262,7 @@
       sfr->get (DPH1) * 256 +
       sfr->get (DPL1);
   con->dd_printf ("\tDPTR1 0x%06lx\n", l);
-  print_cfg_info(con);
+  //print_cfg_info(con);
 }
 
 /* End of s51.src/uc390hw.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/uc390hwcl.h sdcc-4.2.0+dfsg/sim/ucsim/s51.src/uc390hwcl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/uc390hwcl.h	2019-04-02 10:46:33.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/uc390hwcl.h	2020-08-22 10:25:08.000000000 +0000
@@ -48,7 +48,7 @@
 public:
   cl_uc390_hw (class cl_uc *auc);
   virtual int init (void);
-  //virtual char *cfg_help(t_addr addr);
+  //virtual const char *cfg_help(t_addr addr);
 
   virtual t_mem read (class cl_memory_cell *cell);
   virtual void write (class cl_memory_cell *cell, t_mem *val);
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/uc517.cc sdcc-4.2.0+dfsg/sim/ucsim/s51.src/uc517.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/uc517.cc	2017-01-24 13:53:15.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/uc517.cc	2021-04-25 20:38:36.000000000 +0000
@@ -44,7 +44,7 @@
   cpu->cfg_set(uc51cpu_aof_mdpc, 0x92);
   cpu->cfg_set(uc51cpu_mask_mdpc, 7);
   class cl_memory_chip *dptr_chip=
-    new cl_memory_chip("dptr_chip", 3*8, 8);
+    new cl_chip8("dptr_chip", 3*8, 8);
   dptr_chip->init();
   memchips->add(dptr_chip);
   decode_dptr();
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/uc51.cc sdcc-4.2.0+dfsg/sim/ucsim/s51.src/uc51.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/uc51.cc	2019-07-02 08:44:01.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/uc51.cc	2022-01-26 16:35:40.000000000 +0000
@@ -25,28 +25,21 @@
 02111-1307, USA. */
 /*@1@*/
 
-#include "ddconfig.h"
+//#include "ddconfig.h"
 
 #include 
-#include 
 #include 
 #include 
-#include 
-#include 
-#include 
-#include 
-//#if FD_HEADER_OK
-//# include HEADER_FD
-//#endif
-#include "i_string.h"
+#include 
 
 // prj
 #include "utils.h"
 #include "globals.h"
 
 // sim
-#include "optioncl.h"
+//#include "optioncl.h"
 #include "iwrap.h"
+#include "dregcl.h"
 
 //cmd.src
 #include "cmd_uccl.h"
@@ -55,12 +48,12 @@
 #include "uc51cl.h"
 #include "glob.h"
 #include "regs51.h"
-#include "timer0cl.h"
+//#include "timer0cl.h"
 #include "timer1cl.h"
 #include "serialcl.h"
 #include "portcl.h"
-#include "interruptcl.h"
-#include "types51.h"
+//#include "interruptcl.h"
+//#include "types51.h"
 
 
 
@@ -482,6 +475,7 @@
 {
   cl_optref::init();
   create(uc51, bool_opt, "irq_stop", "Stop when IRQ accepted");
+  
   return(0);
 }
 
@@ -714,7 +708,7 @@
 
 static char id_string_51[100];
 
-char *
+const char *
 cl_51core::id_string(void)
 {
   int i;
@@ -732,7 +726,7 @@
 void
 cl_51core::make_cpu_hw(void)
 {
-  cpu= new cl_uc51_cpu(this);
+  add_hw(cpu= new cl_uc51_cpu(this));
   cpu->init();
 }
 
@@ -753,6 +747,9 @@
   add_hw(h= new cl_serial(this));
   h->init();
 
+  add_hw(h= new cl_dreg(this, 0, "dreg"));
+  h->init();
+
   class cl_port_ui *d;
   add_hw(d= new cl_port_ui(this, 0, "dport"));
   d->init();
@@ -770,37 +767,37 @@
   class cl_port_data pd;
   pd.init();
   pd.cell_dir= NULL;
-
+  
   pd.set_name("P0");
   pd.cell_p  = p0->cell_p;
   pd.cell_in = p0->cell_in;
-  pd.keyset  = chars(keysets[0]);
+  pd.keyset  = keysets[0];
   pd.basx    = 1;
-  pd.basy    = 4;
+  pd.basy    = 5;
   d->add_port(&pd, 0);
   
   pd.set_name("P1");
   pd.cell_p  = p1->cell_p;
   pd.cell_in = p1->cell_in;
-  pd.keyset  = chars(keysets[1]);
+  pd.keyset  = keysets[1];
   pd.basx    = 20;
-  pd.basy    = 4;
+  pd.basy    = 5;
   d->add_port(&pd, 1);
   
   pd.set_name("P2");
   pd.cell_p  = p2->cell_p;
   pd.cell_in = p2->cell_in;
-  pd.keyset  = chars(keysets[2]);
+  pd.keyset  = keysets[2];
   pd.basx    = 40;
-  pd.basy    = 4;
+  pd.basy    = 5;
   d->add_port(&pd, 2);
   
   pd.set_name("P3");
   pd.cell_p  = p3->cell_p;
   pd.cell_in = p3->cell_in;
-  pd.keyset  = chars(keysets[3]);
+  pd.keyset  = keysets[3];
   pd.basx    = 60;
-  pd.basy    = 4;
+  pd.basy    = 5;
   d->add_port(&pd, 3);
   
   add_hw(interrupt= new cl_interrupt(this));
@@ -879,19 +876,19 @@
 void
 cl_51core::make_chips(void)
 {
-  rom_chip= new cl_memory_chip("rom_chip", 0x10000, 8, 0/*, 0xff*/);
+  rom_chip= new cl_chip8("rom_chip", 0x10000, 8, 0xff);
   rom_chip->init();
   memchips->add(rom_chip);
   
-  iram_chip= new cl_memory_chip("iram_chip", 0x100, 8);
+  iram_chip= new cl_chip8("iram_chip", 0x100, 8);
   iram_chip->init();
   memchips->add(iram_chip);
 
-  xram_chip= new cl_memory_chip("xram_chip", 0x10000, 8);
+  xram_chip= new cl_chip8("xram_chip", 0x10000, 8);
   xram_chip->init();
   memchips->add(xram_chip);
 
-  sfr_chip= new cl_memory_chip("sfr_chip", 0x80, 8);
+  sfr_chip= new cl_chip8("sfr_chip", 0x80, 8);
   sfr_chip->init();
   memchips->add(sfr_chip);
 }
@@ -1033,7 +1030,7 @@
 	  class cl_memory_chip *dptr_chip= (cl_memory_chip*)memory("dptr_chip");
 	  if (dptr_chip == 0)
 	    {
-	      dptr_chip= new cl_memory_chip("dptr_chip", 3*8, 8);
+	      dptr_chip= new cl_chip8("dptr_chip", 3*8, 8);
 	      dptr_chip->init();
 	      memchips->add(dptr_chip);
 	    }
@@ -1076,59 +1073,34 @@
       ad->activate(0);
     }
   
-  cl_var *v;
-  vars->add(v= new cl_var(chars("dpl"), dptr, 0, ""));
-  v->init();
-  vars->add(v= new cl_var(chars("DPL"), dptr, 0, ""));
-  v->init();
-  vars->add(v= new cl_var(chars("dph"), dptr, 1, ""));
-  v->init();
-  vars->add(v= new cl_var(chars("DPH"), dptr, 1, ""));
-  v->init();
+  vars->add("dpl", dptr, 0, "");
+  vars->add("DPL", dptr, 0, "");
+  vars->add("dph", dptr, 1, "");
+  vars->add("DPH", dptr, 1, "");
 }
 
 void
 cl_51core::make_vars(void)
 {
-  cl_var *v;
-
-  vars->add(v= new cl_var(cchars("R0"), regs, 0, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("R1"), regs, 1, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("R2"), regs, 2, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("R3"), regs, 3, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("R4"), regs, 4, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("R5"), regs, 5, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("R6"), regs, 6, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("R7"), regs, 7, ""));
-  v->init();
+  vars->add("R0", regs, 0, 7, 0, "");
+  vars->add("R1", regs, 1, 7, 0, "");
+  vars->add("R2", regs, 2, 7, 0, "");
+  vars->add("R3", regs, 3, 7, 0, "");
+  vars->add("R4", regs, 4, 7, 0, "");
+  vars->add("R5", regs, 5, 7, 0, "");
+  vars->add("R6", regs, 6, 7, 0, "");
+  vars->add("R7", regs, 7, 7, 0, "");
 
   int i;
   for (i= 0; sfr_tab51[i].name != NULL; i++)
     {
       if (type->type & sfr_tab51[i].cpu_type)
-	{
-	  vars->add(v= new cl_var(chars(sfr_tab51[i].name),
-				  sfr,
-				  sfr_tab51[i].addr, ""));
-	  v->init();
-	}
+        vars->add(sfr_tab51[i].name, sfr, sfr_tab51[i].addr, 7, 0, "");
     }
   for (i= 0; bit_tab51[i].name != NULL; i++)
     {
       if (type->type & bit_tab51[i].cpu_type)
-	{
-	  vars->add(v= new cl_var(chars(bit_tab51[i].name),
-				  bits,
-				  bit_tab51[i].addr, ""));
-	  v->init();
-	}
+        vars->add(bit_tab51[i].name, bits, bit_tab51[i].addr, 7, 0, "");
     }
 }
 
@@ -1159,92 +1131,99 @@
 }
 
 char *
-cl_51core::disass(t_addr addr, const char *sep)
+cl_51core::disass(t_addr addr)
 {
-  char work[256], temp[200]/*, c[2]*/;
-  char *buf, *p, *t, *s;
+  chars work= chars(), temp= chars();
   const char *b;
+  t_addr operand;
   t_mem code= rom->get(addr);
+  struct dis_entry *dt;//= &(dis_tbl()[code]);
+  bool first;
 
-  p= work;
-  b= dis_tbl()[code].mnemonic;
+  dt= dis_tbl();
+  if (!dt) return NULL;
+  dt= &dt[code];
+  
+  //p= work;
+  work= ""; first= true;
+  b= dt->mnemonic;
   while (*b)
     {
+      if ((*b == ' ') && first)
+	{
+	  first= false;
+	  while (work.len() < 6) work.append(' ');
+	}
       if (*b == '%')
 	{
+	  temp= "";
 	  b++;
 	  switch (*(b++))
 	    {
 	    case 'A': // absolute address
-	      sprintf(temp, "%04x",
-		      /*t_addr*/int((addr&0xf800)|
-				    (((code>>5)&0x07)*256 +
-				     rom->get(addr+1))));
+	      operand= (addr&0xf800)|
+		       (((code>>5)&0x07)*256 +
+			rom->get(addr+1));
+	      temp.appendf(rom->addr_format, operand);
+	      addr_name(operand, rom, &temp);
 	      break;
 	    case 'l': // long address
-	      sprintf(temp, "%04x",
-		      /*t_addr*/int(rom->get(addr+1)*256 +
-				    rom->get(addr+2)));
+	      operand= rom->get(addr+1)*256 + rom->get(addr+2);
+	      temp.appendf(rom->addr_format, operand);
+	      addr_name(operand, rom, &temp);
 	      break;
 	    case 'a': // addr8 (direct address) at 2nd byte
-	      daddr_name(rom->get(addr+1), temp);
+	      daddr_name(rom->get(addr+1), &temp);
 	      break;
 	    case '8': // addr8 (direct address) at 3rd byte
-	      daddr_name(rom->get(addr+2), temp);
+	      daddr_name(rom->get(addr+2), &temp);
 	      break;
 	    case 'b': // bitaddr at 2nd byte
 	      {
 		t_addr ba= rom->get(addr+1);
-		/*if (get_name(ba, bit_tbl(), temp))
-		  break;
-		if (ba<128)
-		  addr_name((ba/8)+32,iram,temp);
-		else
-		  addr_name(ba&0xf8,sfr,temp);
-		strcat(temp, ".");
-		sprintf(c, "%1d", (int)(ba & 0x07));
-		strcat(temp, c);*/
-		baddr_name(ba, temp);
+		baddr_name(ba, &temp);
 		break;
 	      }
 	    case 'r': // rel8 address at 2nd byte
-	      sprintf(temp, "%04x",
-		      /*t_addr*/int(addr+2+(signed char)(rom->get(addr+1))));
+	      operand= (u16_t)(addr+2 + (i8_t)rom->get(addr+1));
+	      temp.appendf(rom->addr_format, operand);
+	      addr_name(operand, rom, &temp);
 	      break;
 	    case 'R': // rel8 address at 3rd byte
-	      sprintf(temp, "%04x",
-		      /*t_addr*/int(addr+3+(signed char)(rom->get(addr+2))));
+	      operand= (u16_t)(addr+3 + (i8_t)rom->get(addr+2));
+	      temp.appendf(rom->addr_format, operand);
+	      addr_name(operand, rom, &temp);
 	      break;
 	    case 'd': // data8 at 2nd byte
-	      sprintf(temp, "%02x", (int)rom->get(addr+1));
+	      temp.appendf("0x%02x", (int)rom->get(addr+1));
 	      break;
 	    case 'D': // data8 at 3rd byte
-	      sprintf(temp, "%02x", (int)rom->get(addr+2));
+	      temp.appendf("0x%02x", (int)rom->get(addr+2));
 	      break;
 	    case '6': // data16 at 2nd(H)-3rd(L) byte
-	      sprintf(temp, "%04x",
-		      /*t_addr*/int(rom->get(addr+1)*256 +
-				    rom->get(addr+2)));
+	      temp.appendf("0x%04x",
+			   int(rom->get(addr+1)*256 +
+			       rom->get(addr+2)));
 	      break;
 	    default:
-	      strcpy(temp, "?");
+	      temp= "?";
 	      break;
 	    }
-	  t= temp;
-	  while (*t)
-	    *(p++)= *(t++);
+	  work+= temp;
 	}
       else
-	*(p++)= *(b++);
+	work+= *(b++);
     }
-  *p= '\0';
-
+  //*p= '\0';
+  /*
   p= strchr(work, ' ');
   if (!p)
     {
       buf= strdup(work);
       return(buf);
     }
+  */
+  /*
   if (sep == NULL)
     buf= (char *)malloc(6+strlen(p)+1);
   else
@@ -1261,21 +1240,25 @@
   else
     strcat(buf, sep);
   strcat(buf, p);
-  return(buf);
+  */
+  return(/*buf*/strdup(work.c_str()));
 }
 
 
 void
 cl_51core::print_regs(class cl_console_base *con)
 {
-  t_addr start;
+  int start, stop;
   t_mem data;
-  t_mem dp;
-  
+  u16_t dp;
+
   // show regs
   start= psw->get() & 0x18;
-  con->dd_printf("     R0 R1 R2 R3 R4 R5 R6 R7\n");
-  iram->dump(start, start+7, 8, con/*->get_fout()*/);
+  con->dd_color("answer");
+  con->dd_printf("     R0 R1 R2 R3 R4 R5 R6 R7\n    ");
+  for (t_addr i= 0; i < 8; i++)
+    con->dd_cprintf("dump_number", " %02x", iram->get(start + i));
+  con->dd_printf("\n");
   con->dd_color("answer");
   // show indirectly addressed IRAM and some basic regs
   data= iram->get(iram->get(start));
@@ -1291,8 +1274,16 @@
               (data&bmOV)?'1':'0', (data&bmP)?'1':'0');
   /* show stack pointer */
   start = sfr->get (SP);
+  if (start >= 7)
+    stop = start-7;
+  else
+    stop= 0;
   con->dd_printf ("SP ", start);
-  iram->dump (start, start - 7, 8, con/*->get_fout()*/);
+  con->dd_cprintf("dump_address", iram->addr_format, start);
+  con->dd_printf (" ->");
+  for (; start >= stop; start--)
+    con->dd_cprintf("dump_number", " %02x", iram->get(start));
+  con->dd_printf("\n");
   con->dd_color("answer");
   // show DPTR(s)
   if (dptr)
@@ -1323,7 +1314,7 @@
 		  for (di= dptr->get_size()-1; di >= 0; di--)
 		    dp= (dp*256) + dptr_chip->get(a+di);
 		  con->dd_printf("  %cDPTR%d= ", (i==act)?'*':' ', i);
-		  con->dd_printf(xram->addr_format, dp);
+		  con->dd_printf("0x%04x", dp);
 		  data= xram->read(dp);
 		  con->dd_printf(" @DPTR%d= ", i);
 		  con->dd_printf("0x%02x %3d %c\n", data, data,
@@ -1347,7 +1338,7 @@
 	  dp= (sfr_chip->get(DPL-0x80) +
 	       sfr_chip->get(DPH-0x80) * 256) & 0xffff;
 	  con->dd_printf("  %cDPTR%d= ", (i==act)?'*':' ', i);
-	  con->dd_printf(xram->addr_format, dp);
+	  con->dd_printf("0x%04x", dp);
 	  data= xram->read(dp);
 	  con->dd_printf(" @DPTR%d= ", i);
 	  con->dd_printf("0x%02x %3d %c\n", data, data,
@@ -1376,7 +1367,7 @@
 	  f.format("0x%%0%dx",a*2);
 	  data= xram->get(dp);
 	  con->dd_printf("   DPTR= ");
-	  con->dd_printf(/*xram->addr_format*/(char*)f, dp);
+	  con->dd_printf(/*xram->addr_format*/f.c_str(), dp);
 	  con->dd_printf(" @DPTR= 0x%02x %3d %c\n",
 			 data, data, isprint(data)?data:'.');
 	}
@@ -1400,7 +1391,7 @@
  */
 
 class cl_address_space *
-cl_51core::bit2mem(t_addr bitaddr, t_addr *memaddr, t_mem *bitmask)
+cl_51core::bit2mem(t_addr bitaddr, t_addr *memaddr, int *bitnr_high, int *bitnr_low)
 {
   class cl_address_space *m;
   t_addr ma;
@@ -1418,8 +1409,12 @@
     }
   if (memaddr)
     *memaddr= ma;
-  if (bitmask)
-    *bitmask= 1 << (bitaddr & 0x7);
+  if (bitnr_low)
+    {
+      *bitnr_low= (bitaddr & 0x7);
+      if (bitnr_high)
+        *bitnr_high = *bitnr_low;
+    }
   return(m);
 }
 
@@ -1457,51 +1452,66 @@
 
 /* Get name of directly addressed iram/sfr cell */
 
-void
-cl_51core::daddr_name(t_addr addr, char *buf)
+bool
+cl_51core::daddr_name(t_addr addr, chars *buf)
 {
   if (!buf)
-    return;
+    return false;
+
+  buf->format("0x%02x", addr);
+
   if (addr < 128)
     {
       // register?
       if (addr_name(addr, regs, buf))
-	return;
+	{
+	  return true;
+	}
       // variale?
       if (addr_name(addr, iram, buf))
-	return;
+	{
+	  return true;
+	}
     }
   else
     {
       // dptr?
-      if (addr_name(addr-0x82, dptr, buf))
-	return;
+      if (dptr && addr_name(addr-0x82, dptr, buf))
+	{
+	  return true;
+	}
       // sfr?
       if (addr_name(addr, sfr, buf))
-	return;
+	{
+	  return true;
+	}
     }
-  unsigned int a= addr;
-  sprintf(buf, "%02x", a);
+
+  return false;
 }
 
 /* Get name of a bit cell */
 
 void
-cl_51core::baddr_name(t_addr addr, char *buf)
+cl_51core::baddr_name(t_addr addr, chars *buf)
 {
   t_addr ma;
-  
+
   if (!buf)
     return;
+
+  buf->appendf("0x%02x", addr);
+
   if (addr_name(addr, bits, buf))
     return;
   if (addr < 128)
     ma= 32+(addr/8);
   else
     ma= addr&0xf8;
-  daddr_name(ma, buf);
-  chars c= chars("", "%s.%d", buf, (int)(addr & 7));
-  strcpy(buf, (char*)c);
+
+  chars temp;
+  if (daddr_name(ma, &temp))
+    buf->appendf("%s.%d", temp.c_str(), (int)(addr & 7));
 }
 
 
@@ -1562,7 +1572,7 @@
 
 
 /*
- * Analyzing code and settig up instruction map
+ * Analyzing code and setting up instruction map
  */
 
 void
@@ -1570,7 +1580,8 @@
 {
   uint code;
   struct dis_entry *tabl;
-
+  t_addr a;
+  
   code= rom->get(addr);
   tabl= &(dis_tbl()[code]);
   while (!inst_at(addr) &&
@@ -1580,44 +1591,44 @@
       switch (tabl->branch)
 	{
 	case 'a': // acall
-	  analyze((addr & 0xf800)|
-		  ((rom->get(addr+1)&0x07)*256+
-		   rom->get(addr+2)));
-	  analyze(addr+tabl->length);
+	  a= (addr & 0xf800)|
+	    ((rom->get(addr+1)&0x07)*256+
+	     rom->get(addr+2));
+	  analyze_jump(addr, a, 's');
 	  break;
 	case 'A': // ajmp
-	  addr= (addr & 0xf800)|
-	    ((rom->get(addr+1) & 0x07)*256 + rom->get(addr+2));
-	  break;
+	  a= (addr & 0xf800)|
+	    (((rom->get(addr)>>5) & 0x07)*256 + rom->get(addr+1));
+	  analyze_jump(addr, a, 'j');
+	  return;
 	case 'l': // lcall
-	  analyze(rom->get(addr+1)*256 + rom->get(addr+2));
-	  analyze(addr+tabl->length);
+	  a= rom->get(addr+1)*256 + rom->get(addr+2);
+	  analyze_jump(addr, a, 's');
 	  break;
 	case 'L': // ljmp
-	  addr= rom->get(addr+1)*256 + rom->get(addr+2);
-	  break;
+	  a= rom->get(addr+1)*256 + rom->get(addr+2);
+	  analyze_jump(addr, a, 'j');
+	  return;
 	case 'r': // reljmp (2nd byte)
-	  analyze(rom->validate_address(addr+(signed char)(rom->get(addr+1))));
-	  analyze(addr+tabl->length);
+	  a= rom->validate_address(addr+2+(signed char)(rom->get(addr+1)));
+	  analyze_jump(addr, a, 'j');
 	  break;
 	case 'R': // reljmp (3rd byte)
-	  analyze(rom->validate_address(addr+(signed char)(rom->get(addr+2))));
-	  analyze(addr+tabl->length);
+	  a= rom->validate_address(addr+3+(signed char)(rom->get(addr+2)));
+	  analyze_jump(addr, a, 'j');
 	  break;
 	case 's': // sjmp
 	  {
-	    signed char target;
-	    target= rom->get(addr+1);
-	    addr+= 2;
-	    addr= rom->validate_address(addr+target);
-	    break;
+	    a= rom->validate_address(addr+(signed char)(rom->get(addr+1)));
+	    analyze_jump(addr, a, 'j');
+	    return;
 	  }
 	case '_':
 	  return;
 	default:
-	  addr= rom->validate_address(addr+tabl->length);
-	  break;
+	  return;
 	}
+      addr= rom->validate_address(addr+tabl->length);
       code= rom->get(addr);
       tabl= &(dis_tbl()[code]);
     }
@@ -1673,15 +1684,45 @@
   t_mem code;
   int res= resGO;
 
-  if ((res= exec_inst_tab(itab51)) != resNOT_DONE)
-    return res;
+  if ((res= exec_inst_tab(itab51)) == resNOT_DONE)
+    {
+      fetch(&code);
+      res= inst_unknown(code);
+    }
+  
+  return res;
+}
+
 
-  instPC= PC;
-  if (fetch(&code))
-    return(resBREAKPOINT);
-  tick(1);
-  res= inst_unknown();
-  return(res);
+int
+cl_51core::high_movxri(void)
+{
+  t_mem mode= cpu->cfg_read(uc51cpu_movxri_mode);
+
+  if (mode == 'm')
+    {
+      t_addr addr= cpu->cfg_read(uc51cpu_movxri_addr);
+      switch (cpu->cfg_read(uc51cpu_movxri_as))
+	{
+	case 's': return sfr->read(addr);
+	case 'c':
+	case 'r': return rom->read(addr);
+	case 'i': return iram->read(addr);
+	default: return xram->read(addr);
+	}
+    }
+  else if (mode == 'e')
+    {
+      t_mem v;
+      class cl_uc51_cpu *c= (class cl_uc51_cpu *)cpu;
+      v= application->eval(c->movxri_expr);
+      return v & 0xff;
+    }
+  else
+    {
+      return sfr->read(P2);
+    }
+  return 0;
 }
 
 
@@ -1691,16 +1732,17 @@
  * This is an endless loop if requested number of steps is negative.
  * In this case execution is stopped if an instruction results other
  * status than GO. Execution can be stopped if `cmd_in' is not NULL
- * and there is input available on that file. It is usefull if the
+ * and there is input available on that file. It is useful if the
  * command console is on a terminal. If input is available then a
  * complete line is read and dropped out because input is buffered
  * (inp_avail will be TRUE if ENTER is pressed) and it can confuse
- * command interepter.
+ * command interpreter.
  */
 //static class cl_console *c= NULL;
 int
 cl_51core::do_inst(int step)
 {
+  t_addr PCsave= PC;
   result= resGO;
   while ((result == resGO) &&
 	 (state != stPD) &&
@@ -1712,16 +1754,25 @@
 	{
 	  interrupt->was_reti= false;
 	  pre_inst();
+	  PCsave= PC;
 	  result= exec_inst();
+	  if (result == resGO && !inst_at(PCsave))
+            analyze(PCsave);
 	  post_inst();
 	}
       else
 	{
 	  // tick hw in idle state
-	  inst_ticks= 1;
-	  post_inst();
 	  tick(1);
 	}
+
+      if ((result == resGO) && (PC == PCsave) && stop_selfjump)
+	{
+	  result= resSELFJUMP;
+	  sim->stop(result);
+	  break;
+	}
+
       if (result == resGO)
 	{
 	  int res;
@@ -1787,14 +1838,14 @@
 	  if (state == stIDLE)
 	    {
 	      state= stGO;
-	      sfr->set_bit0(PCON, bmIDL);
+	      sfr->set(PCON, sfr->get(PCON) & ~bmIDL);
 	      interrupt->was_reti= true;
 	      return(resGO);
 	    }
 	  is->clear();
 	  sim->app->get_commander()->
 	    debug("%g sec (%d clks): Accepting interrupt `%s' PC= 0x%06x\n",
-			  get_rtime(), ticks->ticks, object_name(is), PC);
+			  ticks->get_rtime(), ticks->get_ticks(), object_name(is), PC);
 	  IL= new it_level(pr, is->addr, PC, is);
 	  return(accept_it(IL));
 	}
@@ -1819,7 +1870,7 @@
 cl_51core::accept_it(class it_level *il)
 {
   state= stGO;
-  sfr->set_bit0(PCON, bmIDL);
+  sfr->set(PCON, sfr->get(PCON) & ~bmIDL);
   it_levels->push(il);
   tick(1);
   int res= inst_lcall(0, il->addr, true);
@@ -1840,6 +1891,26 @@
 }
 
 
+/* 
+ * Check SP validity after stack (write) operation
+ */
+
+void
+cl_51core::stack_check_overflow(class cl_stack_op *op)
+{
+  t_addr b, a;
+  b= op->get_before();
+  a= op->get_after();
+  if (a < b)
+    {
+      class cl_error_stack_overflow *e=
+	new cl_error_stack_overflow(op);
+      e->init();
+      error(e);
+    }
+}
+
+
 /*
  * Checking if Idle or PowerDown mode should be activated
  */
@@ -1856,7 +1927,7 @@
       if (state != stIDLE)
 	sim->app->get_commander()->
 	  debug("%g sec (%d clks): CPU in Idle mode (PC=0x%x, PCON=0x%x)\n",
-		get_rtime(), ticks->ticks, PC, pcon);
+		ticks->get_rtime(), ticks->get_ticks(), PC, pcon);
       state= stIDLE;
       //was_reti= 1;
     }
@@ -1865,7 +1936,7 @@
       if (state != stPD)
 	sim->app->get_commander()->
 	  debug("%g sec (%d clks): CPU in PowerDown mode\n",
-			get_rtime(), ticks->ticks);
+			ticks->get_rtime(), ticks->get_ticks());
       state= stPD;
     }
   return(resGO);
@@ -1873,23 +1944,6 @@
 
 
 /*
- * Simulating an unknown instruction
- *
- * Normally this function is called for unimplemented instructions, because
- * every instruction must be known!
- */
-
-int
-cl_51core::inst_unknown(void)
-{
-  //PC--;
-  class cl_error_unknown_code *e= new cl_error_unknown_code(this);
-  error(e);
-  return(resGO);
-}
-
-
-/*
  * 0x00 1 12 NOP
  */
 
@@ -1952,48 +2006,53 @@
   for (i= 0; i < 8; i++)
     acc_bits[i]= register_cell(bas, ACC+i);
 
-  cl_var *v;
-  uc->vars->add(v= new cl_var(cchars("cpu_aof_mdps"), cfg, uc51cpu_aof_mdps,
-			      cfg_help(uc51cpu_aof_mdps)));
-  v->init();
-  uc->vars->add(v= new cl_var(cchars("cpu_mask_mdps"), cfg, uc51cpu_mask_mdps,
-			      cfg_help(uc51cpu_mask_mdps)));
-  v->init();
-  uc->vars->add(v= new cl_var(cchars("cpu_aof_mdps1l"), cfg, uc51cpu_aof_mdps1l,
-			      cfg_help(uc51cpu_aof_mdps1l)));
-  v->init();
-  uc->vars->add(v= new cl_var(cchars("cpu_aof_mdps1h"), cfg, uc51cpu_aof_mdps1h,
-			      cfg_help(uc51cpu_aof_mdps1h)));
-  v->init();
-  uc->vars->add(v= new cl_var(cchars("cpu_aof_mdpc"), cfg, uc51cpu_aof_mdpc,
-			      cfg_help(uc51cpu_aof_mdpc)));
-  v->init();
-  uc->vars->add(v= new cl_var(cchars("cpu_mask_mdpc"), cfg, uc51cpu_mask_mdpc,
-			      cfg_help(uc51cpu_mask_mdpc)));
-  v->init();
-  
+  uc->vars->add("cpu_aof_mdps", cfg, uc51cpu_aof_mdps, cfg_help(uc51cpu_aof_mdps));
+  uc->vars->add("cpu_mask_mdps", cfg, uc51cpu_mask_mdps, cfg_help(uc51cpu_mask_mdps));
+  uc->vars->add("cpu_aof_mdps1l", cfg, uc51cpu_aof_mdps1l, cfg_help(uc51cpu_aof_mdps1l));
+  uc->vars->add("cpu_aof_mdps1h", cfg, uc51cpu_aof_mdps1h, cfg_help(uc51cpu_aof_mdps1h));
+  uc->vars->add("cpu_aof_mdpc", cfg, uc51cpu_aof_mdpc, cfg_help(uc51cpu_aof_mdpc));
+  uc->vars->add("cpu_mask_mdpc", cfg, uc51cpu_mask_mdpc, cfg_help(uc51cpu_mask_mdpc));
+  uc->vars->add("cpu_mdp_mode", cfg, uc51cpu_mdp_mode, cfg_help(uc51cpu_mdp_mode));
+  class cl_cvar *v;
+  v = uc->vars->add("cpu_movxri_mode", cfg, uc51cpu_movxri_mode, cfg_help(uc51cpu_movxri_mode));
+  v->write('m');
+  v = uc->vars->add("cpu_movxri_as", cfg, uc51cpu_movxri_as, cfg_help(uc51cpu_movxri_as));
+  v->write('s');
+  v = uc->vars->add("cpu_movxri_addr", cfg, uc51cpu_movxri_addr, cfg_help(uc51cpu_movxri_addr));
+  v->write(0xa0);
+
+  movxri_expr= "port2_odr";
+
   return(0);
 }
 
-char *
+const char *
 cl_uc51_cpu::cfg_help(t_addr addr)
 {
   switch (addr)
     {
     case uc51cpu_aof_mdps:
-      return (char*)"Address of multi_DPTR_sfr selector, WR selects this style of multi_DPTR (int, RW)";
+      return "Address of multi_DPTR_sfr selector, WR selects this style of multi_DPTR (int, RW)";
     case uc51cpu_mask_mdps:
-      return (char*)"Mask in multi_DPTR_srf selector (int, RW)";
+      return "Mask in multi_DPTR_srf selector (int, RW)";
     case uc51cpu_aof_mdps1l:
-      return (char*)"Address of multi_DPTR_sfr DPL1 (int, RW)";
+      return "Address of multi_DPTR_sfr DPL1 (int, RW)";
     case uc51cpu_aof_mdps1h:
-      return (char*)"Address of multi_DPTR_sfr DPH1 (int, RW)";
+      return "Address of multi_DPTR_sfr DPH1 (int, RW)";
     case uc51cpu_aof_mdpc:
-      return (char*)"Address of multi_DPTR_chip selector, WR selects this stlye of multi_DPTR (int, RW)";
+      return "Address of multi_DPTR_chip selector, WR selects this stlye of multi_DPTR (int, RW)";
     case uc51cpu_mask_mdpc:
-      return (char*)"Mask in multi_DPTR_chip selector (int, RW)";
+      return "Mask in multi_DPTR_chip selector (int, RW)";
+    case uc51cpu_mdp_mode:
+      return "Multi DPTR simulation mode 's'=sfr, 'c'=chip, 'n'=none (int, RO)";
+    case uc51cpu_movxri_mode:
+      return "Calc mode of high address for MOVX @Ri, 'm'=memory, 'e'=expr  (int, RW)";
+    case uc51cpu_movxri_as:
+      return "Address space where high address is in 'm' mode, 'i','s','x','c' (int, RW)";
+    case uc51cpu_movxri_addr:
+      return "Address where high address is in 'm' mode (int, RW)";
     }
-  return (char*)"Not used";
+  return "Not used";
 }
 
 void
@@ -2027,9 +2086,9 @@
 	  uc>>= 1;
 	}
       if (p)
-	cell_psw->set_bit1(bmP);
+	cell_psw->set(cell_psw->get() | bmP);
       else
-	cell_psw->set_bit0(bmP);
+	cell_psw->set(cell_psw->get() & ~bmP);
     }
   /*else if (cell == cell_pcon)
     {
@@ -2062,11 +2121,55 @@
       break;
     case uc51cpu_mask_mdpc: // mask in multi_DPTR_chip selector
       break;
-  
+
+    case uc51cpu_mdp_mode: // mode of dual dptr simulation
+      {
+	t_mem adps= cfg_get(uc51cpu_aof_mdps),
+	  dpl1= cfg_get(uc51cpu_aof_mdps1l),
+	  dph1= cfg_get(uc51cpu_aof_mdps1h),
+	  adpc= cfg_get(uc51cpu_aof_mdpc);;
+	if (adps > 0x7f &&
+	    dpl1 > 0x7f &&
+	    dph1 > 0x7f)
+	  cell->set('s');
+	else if (adpc > 0x7f)
+	  cell->set('c');
+	else
+	  cell->set('n');
+	break;
+      }
+
+    case uc51cpu_movxri_mode:
+      break;
+    case uc51cpu_movxri_as:
+      break;
+    case uc51cpu_movxri_addr:
+      break;
+      
     case uc51cpu_nuof:
       break;
     }
   return cell->get();
 }
 
+
+void
+cl_uc51_cpu::set_cmd(class cl_cmdline *cmdline, class cl_console_base *con)
+{
+  class cl_cmd_arg *params[1]= { cmdline->param(0) };
+
+  if (cmdline->syntax_match(uc, STRING))
+    {
+      movxri_expr= params[0]->value.string.string;
+    }
+}
+
+void
+cl_uc51_cpu::print_info(class cl_console_base *con)
+{
+  con->dd_printf("%s[%d]\n", id_string, id);
+  con->dd_printf("Expression for MOVX @Ri: \"%s\"\n", movxri_expr.c_str());
+  //print_cfg_info(con);
+}
+
 /* End of s51.src/uc51.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/uc51cl.h sdcc-4.2.0+dfsg/sim/ucsim/s51.src/uc51cl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/uc51cl.h	2019-04-02 10:46:33.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/uc51cl.h	2021-10-29 17:39:15.000000000 +0000
@@ -90,7 +90,7 @@
   cl_51core(struct cpu_entry *Itype, class cl_sim *asim);
   virtual ~cl_51core(void);
   virtual int    init(void);
-  virtual char  *id_string(void);
+  virtual const char *id_string(void);
   virtual void make_cpu_hw(void);
   virtual void mk_hw_elements(void);
   virtual void build_cmdset(class cl_cmdset *cmdset);
@@ -110,15 +110,17 @@
   virtual int clock_per_cycle(void) { return(12); }
   virtual struct dis_entry *dis_tbl(void);
   virtual struct name_entry *bit_tbl(void);
-  virtual char *disass(t_addr addr, const char *sep);
+  virtual char *disass(t_addr addr);
   virtual void   print_regs(class cl_console_base *con);
   virtual class cl_address_space *bit2mem(t_addr bitaddr,
-					  t_addr *memaddr, t_mem *bitmask);
+					  t_addr *memaddr,
+					  int *bitnr_high,
+					  int *bitnr_low);
   virtual t_addr bit_address(class cl_memory *mem,
 			     t_addr mem_address,
 			     int bit_number);
-  virtual void   daddr_name(t_addr addr, char *buf);
-  virtual void   baddr_name(t_addr addr, char *buf);
+  virtual bool   daddr_name(t_addr addr, chars *buf);
+  virtual void   baddr_name(t_addr addr, chars *buf);
   
   virtual void   reset(void);
   virtual void   clear_sfr(void);
@@ -132,6 +134,8 @@
   virtual int  do_interrupt(void);
   virtual int  accept_it(class it_level *il);
   virtual bool it_enabled(void);
+
+  virtual void stack_check_overflow(class cl_stack_op *op);
   
 protected:
   virtual int  idle_pd(void);
@@ -140,8 +144,8 @@
 
   virtual int   exec_inst(void);
   //virtual void  post_inst(void);
-
-  virtual int inst_unknown(void);
+  virtual int high_movxri(void);
+  
   virtual int instruction_00/*inst_nop*/(t_mem/*uchar*/ code);		/* 00 */
   virtual int instruction_01/*inst_ajmp_addr*/(t_mem/*uchar*/ code);	/* [02468ace]1 */
   virtual int instruction_02/*inst_ljmp*/(t_mem/*uchar*/ code);		/* 02 */
@@ -262,26 +266,35 @@
   uc51cpu_mask_mdps	= 1, // mask in mutli_DPTR_sfr selector
   uc51cpu_aof_mdps1l	= 2, // addr of multi_DPTR_sfr DPL1
   uc51cpu_aof_mdps1h	= 3, // addr of multi_DPTR_sfr DPH1
-
   uc51cpu_aof_mdpc	= 4, // addr of multi_DPTR_chip selector
   uc51cpu_mask_mdpc	= 5, // mask in multi_DPTR_chip selector
+  uc51cpu_mdp_mode	= 6, // 's': sfr mode, 'c': chip_mode
+
+  uc51cpu_movxri_mode	= 7, // 'm': memory, 'e': expr
+  uc51cpu_movxri_as	= 8, // 's': sfr, 'i': iram, 'x': xram, 'c','r': code
+  uc51cpu_movxri_addr	= 9, // address of memory
   
   uc51cpu_nuof		= 16
 };
 
 class cl_uc51_cpu: public cl_hw
 {
- protected:
+protected:
   class cl_memory_cell *cell_acc, *cell_sp, *cell_psw;
   class cl_memory_cell *acc_bits[8];
+public:
+  chars movxri_expr;
  public:
   cl_uc51_cpu(class cl_uc *auc);
   virtual int init(void);
-  virtual int cfg_size(void) { return uc51cpu_nuof; }
-  virtual char *cfg_help(t_addr addr);
+  virtual unsigned int cfg_size(void) { return uc51cpu_nuof; }
+  virtual const char *cfg_help(t_addr addr);
   
   virtual void write(class cl_memory_cell *cell, t_mem *val);
   virtual t_mem conf_op(cl_memory_cell *cell, t_addr addr, t_mem *val);
+
+  virtual void set_cmd(class cl_cmdline *cmdline, class cl_console_base *con);
+  virtual void print_info(class cl_console_base *con);
 };
 
 
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/uc51r.cc sdcc-4.2.0+dfsg/sim/ucsim/s51.src/uc51r.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/uc51r.cc	2017-04-07 20:59:49.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/uc51r.cc	2021-04-25 20:38:36.000000000 +0000
@@ -25,14 +25,14 @@
 02111-1307, USA. */
 /*@1@*/
 
-#include "ddconfig.h"
+//#include "ddconfig.h"
 
-#include 
+//#include 
 
 // local
 #include "uc51rcl.h"
 #include "regs51.h"
-#include "types51.h"
+//#include "types51.h"
 #include "wdtcl.h"
 
 
@@ -72,7 +72,7 @@
 {
   cl_uc52::make_chips();
   
-  eram_chip= new cl_memory_chip("eram_chip", 0x100, 8);
+  eram_chip= new cl_chip8("eram_chip", 0x100, 8);
   eram_chip->init();
   memchips->add(eram_chip);
 }
@@ -136,10 +136,10 @@
 	  ||
 	  /* Check for broadcast address */
 	  (br == (br & c)))
-	sfr->set_bit1(SCON, bmRI);
+	sfr->set(SCON, sfr->get(SCON) | bmRI);
       return;
     }
-  sfr->set_bit1(SCON, bmRI);
+  sfr->set(SCON, sfr->get(SCON) | bmRI);
 }
 
 
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/uc52.cc sdcc-4.2.0+dfsg/sim/ucsim/s51.src/uc52.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/uc52.cc	2017-01-24 13:53:15.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/uc52.cc	2020-03-27 20:18:53.000000000 +0000
@@ -25,16 +25,16 @@
 02111-1307, USA. */
 /*@1@*/
 
-#include "ddconfig.h"
+//#include "ddconfig.h"
 
-#include 
+//#include 
 
 // local
 #include "uc52cl.h"
 #include "regs51.h"
 #include "timer2cl.h"
-#include "portcl.h"
-#include "mducl.h"
+//#include "portcl.h"
+//#include "mducl.h"
 
 
 /*
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/uc88x.cc sdcc-4.2.0+dfsg/sim/ucsim/s51.src/uc88x.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/uc88x.cc	2017-01-24 13:53:15.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/uc88x.cc	2021-04-25 20:38:36.000000000 +0000
@@ -44,7 +44,7 @@
   cpu->cfg_set(uc51cpu_aof_mdpc, 0xA2);
   cpu->cfg_set(uc51cpu_mask_mdpc, 1);
   class cl_memory_chip *dptr_chip=
-    new cl_memory_chip("dptr_chip", 3*8, 8);
+    new cl_chip8("dptr_chip", 3*8, 8);
   dptr_chip->init();
   memchips->add(dptr_chip);
   decode_dptr();
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/uc89c51r.cc sdcc-4.2.0+dfsg/sim/ucsim/s51.src/uc89c51r.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/uc89c51r.cc	2017-01-24 13:53:15.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/uc89c51r.cc	2021-04-25 20:38:36.000000000 +0000
@@ -25,10 +25,10 @@
 02111-1307, USA. */
 /*@1@*/
 
-#include "ddconfig.h"
+//#include "ddconfig.h"
 
-#include 
-#include 
+//#include 
+//#include 
 
 // local
 #include "uc89c51rcl.h"
@@ -50,7 +50,7 @@
   cpu->cfg_set(uc51cpu_aof_mdpc, 0xA2);
   cpu->cfg_set(uc51cpu_mask_mdpc, 1);
   class cl_memory_chip *dptr_chip=
-    new cl_memory_chip("dptr_chip", 3*8, 8);
+    new cl_chip8("dptr_chip", 3*8, 8);
   dptr_chip->init();
   memchips->add(dptr_chip);
   decode_dptr();
@@ -80,11 +80,11 @@
 cl_uc89c51r::reset(void)
 {
   cl_uc51r::reset();
-  sfr->set_bit1(CCAPM0, bmECOM);
-  sfr->set_bit1(CCAPM1, bmECOM);
-  sfr->set_bit1(CCAPM2, bmECOM);
-  sfr->set_bit1(CCAPM3, bmECOM);
-  sfr->set_bit1(CCAPM4, bmECOM);
+  sfr->set(CCAPM0, sfr->get(CCAPM0) | bmECOM);
+  sfr->set(CCAPM1, sfr->get(CCAPM1) | bmECOM);
+  sfr->set(CCAPM2, sfr->get(CCAPM2) | bmECOM);
+  sfr->set(CCAPM3, sfr->get(CCAPM3) | bmECOM);
+  sfr->set(CCAPM4, sfr->get(CCAPM4) | bmECOM);
   sfr->write(IPH, 0);
 }
 
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/wdt.cc sdcc-4.2.0+dfsg/sim/ucsim/s51.src/wdt.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/wdt.cc	2019-04-02 10:46:33.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/wdt.cc	2020-12-27 23:03:09.000000000 +0000
@@ -25,7 +25,8 @@
 02111-1307, USA. */
 /*@1@*/
 
-#include 
+#include 
+//#include 
 
 // local
 #include "wdtcl.h"
@@ -94,7 +95,7 @@
 {
   con->dd_printf("%s[%d] %s counter=%d (remains=%d)\n", id_string, id,
 		 (wdt>=0)?"ON":"OFF", wdt, (wdt>=0)?(reset_value-wdt):0);
-  print_cfg_info(con);
+  //print_cfg_info(con);
 }
 
 
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/s51.src/wdtcl.h sdcc-4.2.0+dfsg/sim/ucsim/s51.src/wdtcl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/s51.src/wdtcl.h	2019-04-02 10:46:33.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/s51.src/wdtcl.h	2020-08-22 10:25:08.000000000 +0000
@@ -47,7 +47,7 @@
 public:
   cl_wdt(class cl_uc *auc, long resetvalue);
   virtual int init(void);
-  //virtual char *cfg_help(t_addr addr);
+  //virtual const char *cfg_help(t_addr addr);
 
   //virtual t_mem read(class cl_memory_cell *cell);
   virtual void write(class cl_memory_cell *cell, t_mem *val);
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/sim.src/arg.cc sdcc-4.2.0+dfsg/sim/ucsim/sim.src/arg.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/sim.src/arg.cc	2017-03-29 15:20:04.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/sim.src/arg.cc	2021-05-07 15:25:25.000000000 +0000
@@ -25,20 +25,21 @@
 02111-1307, USA. */
 /*@1@*/
 
-#include "ddconfig.h"
+//#include "ddconfig.h"
 
 #include 
 #include 
-#include "i_string.h"
+#include 
+//#include "i_string.h"
 
 // prj
 #include "globals.h"
 
 // sim
-#include "simcl.h"
+//#include "simcl.h"
 
 // cmd
-#include "cmdutil.h"
+//#include "cmdutil.h"
 
 // local
 #include "argcl.h"
@@ -127,6 +128,12 @@
     }
 }
 
+int
+cl_cmd_arg::init(void)
+{
+  return 0;
+}
+
 bool
 cl_cmd_arg::as_address(class cl_uc *uc)
 {
@@ -197,17 +204,25 @@
 bool
 cl_cmd_arg::as_bit(class cl_uc *uc)
 {
+  if (interpreted_as_string)
+    {
+      interpreted_as_string= false;
+      if (value.string.string)
+        free(value.string.string);
+    }
+
   return(get_bit_address(uc,
-			 &(value.bit.mem),
-			 &(value.bit.mem_address),
-			 &(value.bit.mask)));
+                         &(value.bit.mem),
+                         &(value.bit.mem_address),
+                         &(value.bit.bitnr_high),
+                         &(value.bit.bitnr_low)));
 }
 
 
-/* Interger number */
+/* Integer number */
 
-cl_cmd_int_arg::cl_cmd_int_arg(/*class cl_uc *iuc,*/ long addr):
-  cl_cmd_arg(/*iuc,*/ addr)
+cl_cmd_int_arg::cl_cmd_int_arg(long addr):
+  cl_cmd_arg(addr)
 {}
 
 bool
@@ -223,18 +238,26 @@
 
 bool
 cl_cmd_int_arg::get_bit_address(class cl_uc *uc, // input
-				class cl_address_space **mem, // outputs
-				t_addr *mem_addr,
-				t_mem *bit_mask)
+                                class cl_memory **mem, // outputs
+                                t_addr *mem_addr,
+                                int *bitnr_high,
+                                int *bitnr_low)
 {
   t_addr bit_addr;
 
   if (!get_address(uc, &bit_addr))
     return(false);
   
+  if (bitnr_high)
+    *bitnr_high = -1;
+  if (bitnr_low)
+    *bitnr_low = -1;
+
   if (mem)
-    *mem= uc->bit2mem(bit_addr, mem_addr, bit_mask);
-  return(mem && *mem);
+    if (!(*mem= uc->bit2mem(bit_addr, mem_addr, bitnr_high, bitnr_low)))
+      *mem = uc->rom;
+
+  return(true);
 }
 
 bool
@@ -280,38 +303,23 @@
 
 bool
 cl_cmd_sym_arg::get_bit_address(class cl_uc *uc, // input
-				class cl_address_space **mem, // outputs
-				t_addr *mem_addr,
-				t_mem *bit_mask)
+                                class cl_memory **mem, // outputs
+                                t_addr *mem_addr,
+                                int *bitnr_high,
+                                int *bitnr_low)
 {
-  /*
-  struct name_entry *ne;
-
-  ne= uc->get_name_entry(uc->bit_tbl(), get_svalue());
-  if (ne == NULL)
-    return(false);
-  if (mem)
-    *mem= uc->bit2mem(ne->addr, mem_addr, bit_mask);
-  return(mem && *mem);
-  */
-  class cl_var *v= uc->var(get_svalue());
-  if (v)
+  t_index i;
+  if (uc->vars->by_name.search(get_svalue(), i))
     {
+      class cl_var *v= (cl_var*)uc->vars->by_name.at(i);
       if (mem)
-	*mem= v->as;
+        *mem= v->get_mem();
       if (mem_addr)
-	*mem_addr= v->addr;
-      if (bit_mask)
-	{
-	  if (v->bitnr < 0)
-	    {
-	      *bit_mask= 1;
-	    }
-	  else
-	    {
-	      *bit_mask= 1 << v->bitnr;
-	    }
-	}
+        *mem_addr= v->get_addr();
+      if (bitnr_high)
+        *bitnr_high= v->bitnr_high;
+      if (bitnr_low)
+        *bitnr_low= v->bitnr_low;
       return true;
     }
   return false;
@@ -338,6 +346,8 @@
   hw= found= uc->get_hw(get_svalue(), &i);
   if (!hw)
     return(false);
+  if (hw && (strcmp(get_svalue(), "cpu")==0))
+    return value.hw= hw, true;
   i++;
   found= uc->get_hw(get_svalue(), &i);
   if (found)
@@ -349,12 +359,13 @@
 bool
 cl_cmd_sym_arg::as_cell(class cl_uc *uc)
 {
-  class cl_address_space *as;
+  class cl_memory *mem;
   t_addr addr;
   
-  if (uc->symbol2address(get_svalue(), &as, &addr))
+  if (uc->symbol2address(get_svalue(), &mem, &addr) &&
+      mem->is_address_space())
     {
-      value.cell= as->get_cell(addr);
+      value.cell= ((cl_address_space *)mem)->get_cell(addr);
       return value.cell != NULL;
     }
   return false;
@@ -371,20 +382,22 @@
 
 /* Bit */
 
-cl_cmd_bit_arg::cl_cmd_bit_arg(/*class cl_uc *iuc,*/
-			       class cl_cmd_arg *asfr, class cl_cmd_arg *abit):
-  cl_cmd_arg(/*iuc,*/ (long)0)
+cl_cmd_bit_arg::cl_cmd_bit_arg(class cl_cmd_arg *asfr, class cl_cmd_arg *abit_low, class cl_cmd_arg *abit_high):
+  cl_cmd_arg((long)0)
 {
   sfr= asfr;
-  bit= abit;
+  bit_low= abit_low;
+  bit_high= abit_high;
 }
 
 cl_cmd_bit_arg::~cl_cmd_bit_arg(void)
 {
   if (sfr)
     delete sfr;
-  if (bit)
-    delete bit;
+  if (bit_low)
+    delete bit_low;
+  if (bit_high)
+    delete bit_high;
 }
 
 bool
@@ -397,42 +410,51 @@
 
 bool
 cl_cmd_bit_arg::get_bit_address(class cl_uc *uc, // input
-				class cl_address_space **mem, // outputs
-				t_addr *mem_addr,
-				t_mem *bit_mask)
+                                class cl_memory **mem, // outputs
+                                t_addr *mem_addr,
+                                int *bitnr_high,
+                                int *bitnr_low)
 {
-  if (mem)
-    {
-      *mem= uc->address_space(MEM_SFR_ID);
-      if (!*mem)
-	return(false);
-    }
-  if (mem_addr)
+  if (!sfr || !bitnr_high || !bitnr_low)
+    return(false);
+
+  if ((mem || mem_addr) && !sfr->get_bit_address(uc, mem, mem_addr, NULL, NULL))
+    return(false);
+
+  long l;
+
+  if (!bit_low ||
+      !bit_low->get_ivalue(&l) ||
+      l < 0 ||
+      l >= (long)sizeof(t_mem)*8)
+    return(false);
+  *bitnr_low = *bitnr_high = l;
+
+  if (bit_high)
     {
-      if (!sfr ||
-	  !sfr->get_address(uc, mem_addr))
-	return(false);
+      if (!bit_high->get_ivalue(&l) ||
+          l < 0 ||
+          l >= (long)sizeof(t_mem)*8)
+        return(false);
+      *bitnr_high = l;
     }
-  if (bit_mask)
+
+  if (*bitnr_low > *bitnr_high)
     {
-      if (!bit)
-	return(false);
-      long l;
-      if (!bit->get_ivalue(&l) ||
-	  l > 7)
-	return(false);
-      *bit_mask= 1 << l;
+      int t = *bitnr_low;
+      *bitnr_low = *bitnr_high;
+      *bitnr_high = t;
     }
+
   return(true);
 }
 
 
 /* Array */
 
-cl_cmd_array_arg::cl_cmd_array_arg(/*class cl_uc *iuc,*/
-				   class cl_cmd_arg *aname,
+cl_cmd_array_arg::cl_cmd_array_arg(class cl_cmd_arg *aname,
 				   class cl_cmd_arg *aindex):
-  cl_cmd_arg(/*iuc,*/ (long)0)
+  cl_cmd_arg((long)0)
 {
   name_arg= aname;
   index= aindex;
@@ -447,189 +469,65 @@
 }
 
 bool
-cl_cmd_array_arg::as_hw(class cl_uc *uc)
+cl_cmd_array_arg::get_bit_address(class cl_uc *uc, // input
+                                class cl_memory **mem, // outputs
+                                t_addr *mem_addr,
+                                int *bitnr_high,
+                                int *bitnr_low)
 {
+  // address_space[address]
   char *n;
   t_addr a;
-
   if (name_arg == 0 ||
       index == 0 ||
       (n= name_arg->get_svalue()) == NULL ||
       !index->get_address(uc, &a))
-    return(false);
-  
-  value.hw= uc->get_hw(n, a, NULL);
-  return(value.hw != NULL);
+    return false;
+  class cl_memory *m= uc->memory(n);
+  if (!m ||
+      !m->valid_address(a))
+    return false;
+  if (mem)
+    *mem = m;
+  if (mem_addr)
+    *mem_addr = a;
+  if (bitnr_high)
+    *bitnr_high = -1;
+  if (bitnr_low)
+    *bitnr_low = -1;
+  return true;
 }
 
 bool
-cl_cmd_array_arg::as_cell(class cl_uc *uc)
+cl_cmd_array_arg::as_hw(class cl_uc *uc)
 {
-  // address_space[address]
   char *n;
   t_addr a;
+
   if (name_arg == 0 ||
       index == 0 ||
       (n= name_arg->get_svalue()) == NULL ||
       !index->get_address(uc, &a))
-    return false;
-  class cl_memory *m= uc->memory(n);
-  if (!m)
-    return false;
-  if (!m->is_address_space())
-    return false;
-  value.cell= ((cl_address_space*)m)->get_cell(a);
-  return value.cell != NULL;
-}
-
-
-/*
- * Program arguments
- *----------------------------------------------------------------------------
- */
-/*
-cl_prg_arg::cl_prg_arg(char sn, char *ln, long lv):
-  cl_arg(lv)
-{
-  short_name= sn;
-  long_name = ln?strdup(ln):0;
-}
-
-cl_prg_arg::cl_prg_arg(char sn, char *ln, char *sv):
-  cl_arg(sv)
-{
-  short_name= sn;
-  long_name = ln?strdup(ln):0;
-}
-
-cl_prg_arg::cl_prg_arg(char sn, char *ln, double fv):
-  cl_arg(fv)
-{
-  short_name= sn;
-  long_name = ln?strdup(ln):0;
-}
-
-cl_prg_arg::cl_prg_arg(char sn, char *ln, void *pv):
-  cl_arg(pv)
-{
-  short_name= sn;
-  long_name = ln?strdup(ln):0;
-}
-
-cl_prg_arg::~cl_prg_arg(void)
-{
-  if (long_name)
-    free(long_name);
-}
-*/
-
-/*
- * List of arguments
- *----------------------------------------------------------------------------
- */
-/*
-int
-cl_arguments::arg_avail(char nam)
-{
-  class cl_prg_arg *a;
-  int i;
-
-  for (i= 0; i < count; i++)
-    {
-      a= (class cl_prg_arg *)(at(i));
-      if (a->short_name == nam)
-	return(1);
-    }
-  return(0);
-}
-
-int
-cl_arguments::arg_avail(char *nam)
-{
-  class cl_prg_arg *a;
-  int i;
-
-  for (i= 0; i < count; i++)
-    {
-      a= (class cl_prg_arg *)(at(i));
-      if (a->long_name &&
-	  strcmp(a->long_name, nam) == 0)
-	return(1);
-    }
-  return(0);
-}
-
-long
-cl_arguments::get_iarg(char sname, char *lname)
-{
-  class cl_prg_arg *a;
-  int i;
-
-  for (i= 0; i < count; i++)
-    {
-      a= (class cl_prg_arg *)(at(i));
-      if ((sname && a->short_name == sname) ||
-	  (lname && a->long_name && strcmp(a->long_name, lname) == 0))
-	{
-	  long iv;
-	  if (a->get_ivalue(&iv))
-	    return(iv);
-	  else
-	    //FIXME
-	    return(0);
-	}
-    }
-  return(0);
+    return(false);
+  
+  value.hw= uc->get_hw(n, a, NULL);
+  return(value.hw != NULL);
 }
 
-char *
-cl_arguments::get_sarg(char sname, char *lname)
+bool
+cl_cmd_array_arg::as_cell(class cl_uc *uc)
 {
-  class cl_prg_arg *a;
-  int i;
-
-  for (i= 0; i < count; i++)
-    {
-      a= (class cl_prg_arg *)(at(i));
-      if ((sname && a->short_name == sname) ||
-	  (lname && a->long_name && strcmp(a->long_name, lname) == 0))
-	return(a->get_svalue());
-    }
-  return(0);
-}
+  class cl_memory *mem;
+  t_addr addr;
 
+  value.cell = NULL;
 
-double
-cl_arguments::get_farg(char sname, char *lname)
-{
-  class cl_prg_arg *a;
-  int i;
+  if (get_bit_address(uc, &mem, &addr, NULL, NULL) &&
+      mem->is_address_space())
+    value.cell= ((cl_address_space *)mem)->get_cell(addr);
 
-  for (i= 0; i < count; i++)
-    {
-      a= (class cl_prg_arg *)(at(i));
-      if ((sname && a->short_name == sname) ||
-	  (lname && a->long_name && strcmp(a->long_name, lname) == 0))
-	return(a->get_fvalue());
-    }
-  return(0);
+  return value.cell != NULL;
 }
 
-void *
-cl_arguments::get_parg(char sname, char *lname)
-{
-  class cl_prg_arg *a;
-  int i;
-
-  for (i= 0; i < count; i++)
-    {
-      a= (class cl_prg_arg *)(at(i));
-      if ((sname && a->short_name == sname) ||
-	  (lname && a->long_name && strcmp(a->long_name, lname) == 0))
-	return(a->get_pvalue());
-    }
-  return(0);
-}
-*/
 
 /* End of arg.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/sim.src/argcl.h sdcc-4.2.0+dfsg/sim/ucsim/sim.src/argcl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/sim.src/argcl.h	2017-03-20 09:22:55.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/sim.src/argcl.h	2021-04-01 17:52:48.000000000 +0000
@@ -59,9 +59,10 @@
   virtual double get_fvalue(void);
   virtual void *get_pvalue(void);
   virtual bool get_bit_address(class cl_uc *uc, // input
-			       class cl_address_space **mem, // outputs
-			       t_addr *mem_addr,
-			       t_mem *bit_mask) { return(false); }
+                               class cl_memory **mem, // outputs
+                               t_addr *mem_addr,
+                               int *bitnr_high,
+                               int *bitnr_low) { return(false); }
 };
 
 
@@ -93,9 +94,9 @@
       int len;
     } data_list;
     struct {
-      class cl_address_space *mem;
+      class cl_memory *mem;
       t_addr mem_address;
-      t_mem mask;
+      int bitnr_high, bitnr_low;
     } bit;
     class cl_memory_cell *cell;
   } value;
@@ -106,7 +107,8 @@
   cl_cmd_arg(const char *s): cl_arg(s)
   { interpreted_as_string= false; }
   virtual ~cl_cmd_arg(void);
-
+  virtual int init(void);
+  
   virtual int is_string(void) { return(false); }
   virtual bool get_address(class cl_uc *uc, t_addr *addr) { return(false); }
   virtual bool as_address(class cl_uc *uc);
@@ -126,9 +128,10 @@
 
   virtual bool get_address(class cl_uc *uc, t_addr *addr);
   virtual bool get_bit_address(class cl_uc *uc, // input
-			       class cl_address_space **mem, // outputs
-			       t_addr *mem_addr,
-			       t_mem *bit_mask);
+                               class cl_memory **mem, // outputs
+                               t_addr *mem_addr,
+                               int *bitnr_high,
+                               int *bitnr_low);
   virtual bool as_string(void);
 };
 
@@ -139,9 +142,10 @@
 
   virtual bool get_address(class cl_uc *uc, t_addr *addr);
   virtual bool get_bit_address(class cl_uc *uc, // input
-			       class cl_address_space **mem, // outputs
-			       t_addr *mem_addr,
-			       t_mem *bit_mask);
+                               class cl_memory **mem, // outputs
+                               t_addr *mem_addr,
+                               int *bitnr_high,
+                               int *bitnr_low);
   virtual bool as_address(class cl_uc *uc);
   virtual bool as_number(void) { return(false); }
   virtual bool as_string(void);
@@ -161,17 +165,18 @@
 class cl_cmd_bit_arg: public cl_cmd_arg
 {
 public:
-  class cl_cmd_arg *sfr, *bit;
+  class cl_cmd_arg *sfr, *bit_low, *bit_high;
 
 public:
-  cl_cmd_bit_arg(class cl_cmd_arg *asfr, class cl_cmd_arg *abit);
+  cl_cmd_bit_arg(class cl_cmd_arg *asfr, class cl_cmd_arg *abit_low, class cl_cmd_arg *abit_high);
   virtual ~cl_cmd_bit_arg(void);
 
   virtual bool get_address(class cl_uc *uc, t_addr *addr);
   virtual bool get_bit_address(class cl_uc *uc, // input
-			       class cl_address_space **mem, // outputs
-			       t_addr *mem_addr,
-			       t_mem *bit_mask);
+                               class cl_memory **mem, // outputs
+                               t_addr *mem_addr,
+                               int *bitnr_high,
+                               int *bitnr_low);
 };
 
 class cl_cmd_array_arg: public cl_cmd_arg
@@ -181,6 +186,11 @@
 
 public:
   cl_cmd_array_arg(class cl_cmd_arg *aname, class cl_cmd_arg *aindex);
+  virtual bool get_bit_address(class cl_uc *uc, // input
+                               class cl_memory **mem, // outputs
+                               t_addr *mem_addr,
+                               int *bitnr_high,
+                               int *bitnr_low);
   virtual ~cl_cmd_array_arg(void);
   virtual bool as_hw(class cl_uc *uc);
   virtual bool as_cell(class cl_uc *uc);
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/sim.src/brk.cc sdcc-4.2.0+dfsg/sim/ucsim/sim.src/brk.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/sim.src/brk.cc	2019-03-12 12:45:22.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/sim.src/brk.cc	2020-09-17 09:34:03.000000000 +0000
@@ -25,12 +25,12 @@
 02111-1307, USA. */
 /*@1@*/
 
-#include "ddconfig.h"
+//#include "ddconfig.h"
 
 #include 
 #include 
 
-#include "pobjcl.h"
+//#include "pobjcl.h"
 #include "globals.h"
 
 #include "brkcl.h"
@@ -64,7 +64,7 @@
     return true;
   long l;
   l= application->eval(cond);
-  //fprintf(stderr,"BP[%d]EVAL: %s =%ld\n", nr, (char*)cond, l);
+  //fprintf(stderr,"BP[%d]EVAL: %s =%ld\n", nr, cond.c_str(), l);
   return l!=0;
 }
 
@@ -176,28 +176,26 @@
   rom= arom;
 }
 
-void *
-brk_coll::key_of(void *item)
+const void *
+brk_coll::key_of(const void *item) const
 {
-  return((void *)&(((class cl_brk *)(item))->nr));
+  return &(((const class cl_brk *)item)->nr);
 }
 
 
 int
-brk_coll::compare(void *key1, void *key2)
+brk_coll::compare(const void *key1, const void *key2)
 {
   int k1, k2;
 
-  k1= *(int *)key1;
-  k2= *(int *)key2;
+  k1= *(const int *)key1;
+  k2= *(const int *)key2;
 
   if (k1 == k2)
     return(0);
-  else
-    if (k1 < k2)
-      return(-1);
-    else
-      return(+1);
+  else if (k1 < k2)
+    return(-1);
+  return(1);
 }
 
 
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/sim.src/brkcl.h sdcc-4.2.0+dfsg/sim/ucsim/sim.src/brkcl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/sim.src/brkcl.h	2017-06-19 20:29:56.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/sim.src/brkcl.h	2020-09-17 09:34:03.000000000 +0000
@@ -119,8 +119,8 @@
   class cl_address_space/*rom*/ *rom;
 public:
   brk_coll(t_index alimit, t_index adelta, class cl_address_space/*rom*/*arom);
-  virtual void *key_of(void *item);
-  virtual int  compare(void *key1, void *key2);
+  virtual const void *key_of(const void *item) const;
+  virtual int  compare(const void *key1, const void *key2);
 
   virtual bool there_is_event(enum brk_event ev);
   //virtual int make_new_nr(void);
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/sim.src/clean.mk sdcc-4.2.0+dfsg/sim/ucsim/sim.src/clean.mk
--- sdcc-4.0.0+dfsg/sim/ucsim/sim.src/clean.mk	2001-07-02 10:39:19.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/sim.src/clean.mk	2021-03-28 10:28:14.000000000 +0000
@@ -3,12 +3,14 @@
 clean:
 	rm -f *core *[%~] *.[oa] test_mem_speed
 	rm -f .[a-z]*~
+	$(MAKE) -C test -f clean.mk clean
 
 
 # Deleting all files created by configuring or building the program
 # -----------------------------------------------------------------
 distclean: clean
 	rm -f Makefile *.dep
+	$(MAKE) -C test -f clean.mk distclean
 
 
 # Like clean but some files may still exist
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/sim.src/dreg.cc sdcc-4.2.0+dfsg/sim/ucsim/sim.src/dreg.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/sim.src/dreg.cc	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/sim.src/dreg.cc	2021-03-18 13:53:28.000000000 +0000
@@ -0,0 +1,52 @@
+/*
+ * Simulator of microcontrollers (sim.src/dreg.cc)
+ *
+ * Copyright (C) 2020,20 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/*
+  This file is part of microcontroller simulator: ucsim.
+
+  UCSIM is free software; you can redistribute it and/or modify
+  it under the terms of the GNU General Public License as published by
+  the Free Software Foundation; either version 2 of the License, or
+  (at your option) any later version.
+
+  UCSIM is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+  GNU General Public License for more details.
+
+  You should have received a copy of the GNU General Public License
+  along with UCSIM; see the file COPYING.  If not, write to the Free
+  Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+  02111-1307, USA.
+*/
+/*@1@*/
+
+#include "dregcl.h"
+
+
+cl_dreg::cl_dreg(class cl_uc *auc, int aid, const char *aid_string):
+  cl_hw(auc, HW_DUMMY, aid, aid_string)
+{
+}
+
+/*
+void
+cl_dreg::refresh_display(bool force)
+{
+}
+*/
+
+void
+cl_dreg::print_info(class cl_console_base *con)
+{
+  if (uc) uc->print_regs(con);
+}
+
+
+/* End of sim.src/dreg.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/sim.src/dregcl.h sdcc-4.2.0+dfsg/sim/ucsim/sim.src/dregcl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/sim.src/dregcl.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/sim.src/dregcl.h	2021-03-18 13:53:28.000000000 +0000
@@ -0,0 +1,48 @@
+/*
+ * Simulator of microcontrollers (sim.src/dregcl.h)
+ *
+ * Copyright (C) 2020,20 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/*
+  This file is part of microcontroller simulator: ucsim.
+
+  UCSIM is free software; you can redistribute it and/or modify
+  it under the terms of the GNU General Public License as published by
+  the Free Software Foundation; either version 2 of the License, or
+  (at your option) any later version.
+
+  UCSIM is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+  GNU General Public License for more details.
+
+  You should have received a copy of the GNU General Public License
+  along with UCSIM; see the file COPYING.  If not, write to the Free
+  Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+  02111-1307, USA.
+*/
+/*@1@*/
+
+#ifndef DREG_HEADER
+#define DREG_HEADER
+
+#include "hwcl.h"
+
+
+class cl_dreg: public cl_hw
+{
+ public:
+  cl_dreg(class cl_uc *auc, int aid, const char *aid_string);
+ public:
+  //virtual void refresh_display(bool force);
+  virtual void print_info(class cl_console_base *con);
+};
+
+
+#endif
+
+/* End of sim.src/dregcl.h */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/sim.src/hw.cc sdcc-4.2.0+dfsg/sim/ucsim/sim.src/hw.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/sim.src/hw.cc	2019-07-02 08:44:01.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/sim.src/hw.cc	2022-02-03 14:06:06.000000000 +0000
@@ -25,13 +25,15 @@
 02111-1307, USA. */
 /*@1@*/
 
-#include "ddconfig.h"
+//#include "ddconfig.h"
 
+#include 
 #include 
 #include 
-#include "i_string.h"
+#include 
+//#include "i_string.h"
 
-#include "stypes.h"
+//#include "stypes.h"
 #include "globals.h"
 
 #include "hwcl.h"
@@ -46,7 +48,7 @@
 {
   flags= HWF_INSIDE;
   uc= auc;
-  cathegory= cath;
+  category= cath;
   id= aid;
   if (aid_string &&
       *aid_string)
@@ -61,11 +63,12 @@
   free(s);
   cfg= 0;
   io= 0;
+  active= false;
 }
 
 cl_hw::~cl_hw(void)
 {
-  free((void*)id_string);
+  free(const_cast(id_string));
   delete partners;
 }
 
@@ -74,23 +77,28 @@
 {
   chars n(id_string);
   char s[100];
-  int i;
+  t_addr a;
 
   on= true;
   
   snprintf(s, 99, "%d", id);
   n+= '_';
   n+= s;
-  n+= cchars("_cfg");
-
-  cfg= new cl_address_space(n, 0, cfg_size(), sizeof(t_mem)*8);
-  cfg->init();
-  cfg->hidden= true;
-  uc->address_spaces->add(cfg);
+  n+= "_cfg";
 
-  for (i= 0; i < cfg_size(); i++)
+  if (cfg_size())
     {
-      cfg->register_hw(i, this, false);
+      cfg= new cl_address_space(n, 0, cfg_size(), sizeof(t_mem)*8);
+      cfg->init();
+      cfg->hidden= true;
+      uc->address_spaces->add(cfg);
+
+      for (a= 0; a < cfg_size(); a++)
+        {
+	  class cl_memory_cell *c= cfg->get_cell(a);
+	  c->decode(&(c->def_data));
+          cfg->register_hw(a, this, false);
+        }
     }
 
   cache_run= -1;
@@ -144,7 +152,7 @@
 cl_hw::conf(class cl_memory_cell *cell, t_mem *val)
 {
   t_addr a;
-  if (cfg->is_owned(cell, &a))
+  if (cfg && cfg->is_owned(cell, &a))
     {
       conf_op(cell, a, val);
       if (val)
@@ -160,6 +168,14 @@
   return cell->get();
 }
 
+class cl_memory_cell *
+cl_hw::cfg_cell(t_addr addr)
+{
+  if (addr >= cfg_size())
+    return 0;
+  return cfg->get_cell(addr);
+}
+
 void
 cl_hw::cfg_set(t_addr addr, t_mem val)
 {
@@ -184,10 +200,10 @@
   return cfg->read(addr);
 }
 
-char *
+const char *
 cl_hw::cfg_help(t_addr addr)
 {
-  return (char*)"N/A";
+  return "N/A";
 }
 
 void
@@ -207,6 +223,27 @@
 }
 
 class cl_memory_cell *
+cl_hw::register_cell(class cl_address_space *mem, t_addr addr,
+		     chars vname, chars vdesc)
+{
+  if (mem)
+    mem->register_hw(addr, this, false);
+  else
+    printf("regcell JAJ no mem\n");
+  class cl_memory_cell *c= mem->get_cell(addr);
+  if (c)
+    {
+      if (vname.nempty())
+	{
+	  class cl_cvar *v;
+	  uc->vars->add(v= new cl_var(vname, mem, addr, vdesc, c->get_width() - 1, 0));
+	  v->init();
+	}
+    }
+  return c;
+}
+
+class cl_memory_cell *
 cl_hw::register_cell(class cl_memory_cell *cell)
 {
   if (cell)
@@ -403,10 +440,8 @@
 }
 
 void
-cl_hw::refresh_display(bool force)
+cl_hw::draw_state_time(bool force)
 {
-  if (!io)
-    return ;
   int n= uc->sim->state & SIM_GO;
   if ((n != cache_run) ||
       force)
@@ -418,7 +453,7 @@
 	io->dd_cprintf("ui_stop", "%s", "Stop");
       cache_run= n;
     }
-  unsigned int t= (unsigned int)(uc->get_rtime()) * 500;
+  unsigned int t= (unsigned int)(uc->ticks->get_rtime()) * 1000;
   if ((t != cache_time) ||
       force)
     {
@@ -431,6 +466,20 @@
 }
 
 void
+cl_hw::refresh_display(bool force)
+{
+  if (!io)
+    return ;
+
+  io->tu_hide();
+  io->tu_go(1,4);
+  io->dd_color("answer");
+  print_info(io);
+  draw_state_time(force);
+  io->tu_show();
+}
+
+void
 cl_hw::draw_display(void)
 {
   if (!io)
@@ -451,7 +500,12 @@
   io->dd_cprintf("ui_label", "Time: ");
   io->tu_go(66,2);
   chars s("", "%s[%d]", id_string, id);
-  io->dd_cprintf("ui_title", "%-13s", (char*)s);
+  io->dd_cprintf("ui_title", "%-13s", s.c_str());
+
+  io->tu_go(1,3);
+  io->dd_printf("\033[2K"); // entire line
+  io->dd_printf("\033[0J"); // from cursor to end of screen
+  io->dd_printf("\n");
 }
 
 class cl_hw *
@@ -467,7 +521,7 @@
 cl_hw::print_info(class cl_console_base *con)
 {
   con->dd_printf("%s[%d]\n", id_string, id);
-  print_cfg_info(con);
+  //print_cfg_info(con);
 }
 
 void
@@ -475,11 +529,11 @@
 {
   t_mem v;
   t_addr a, s, e;
-  con->dd_printf("Configuration memory of %s\n", get_name());
   if (cfg)
-    {      
+    {
+      con->dd_printf("Configuration memory of %s\n", get_name());
       s= cfg->get_start_address();
-      e= s + cfg->get_size();
+      e= s + cfg->get_size()-1;
       for (a= s; a <= e; a++)
 	{
 	  v= cfg->read(a);
@@ -571,9 +625,9 @@
   cl_base()
 {
   uc= auc;
-  cathegory= cath;
+  category= cath;
   id= aid;
-  partner= uc->get_hw(cathegory, id, 0);
+  partner= uc->get_hw(category, id, 0);
 }
 
 class cl_hw *
@@ -585,7 +639,7 @@
 void
 cl_partner_hw::refresh(void)
 {
-  class cl_hw *hw= uc->get_hw(cathegory, id, 0);
+  class cl_hw *hw= uc->get_hw(category, id, 0);
 
   if (!hw)
     return;
@@ -608,7 +662,7 @@
 {
   if (!new_hw)
     return;
-  if (cathegory == new_hw->cathegory &&
+  if (category == new_hw->category &&
       id == new_hw->id)
     {
       if (partner)
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/sim.src/hwcl.h sdcc-4.2.0+dfsg/sim/ucsim/sim.src/hwcl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/sim.src/hwcl.h	2019-04-02 10:46:33.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/sim.src/hwcl.h	2022-02-03 14:06:06.000000000 +0000
@@ -67,7 +67,7 @@
  public:
   int flags;
   class cl_uc *uc;
-  enum hw_cath cathegory;
+  enum hw_cath category;
   int id;
   const char *id_string;
   bool on;
@@ -77,13 +77,16 @@
   class cl_hw_io *io;
   int cache_run;
   unsigned int cache_time;
+ private:
+  bool active;
+  friend class cl_hw_operator;
  public:
   cl_hw(class cl_uc *auc, enum hw_cath cath, int aid, const char *aid_string);
   virtual ~cl_hw(void);
 
   virtual int init(void);
-  virtual int cfg_size(void) { return 1; }
-  
+  virtual unsigned int cfg_size(void) { return 0; }
+
   virtual void new_hw_adding(class cl_hw *new_hw);
   virtual void new_hw_added(class cl_hw *new_hw);
   virtual void added_to_uc(void) {}
@@ -93,15 +96,17 @@
   virtual void write(class cl_memory_cell *cell, t_mem *val);
   virtual bool conf(class cl_memory_cell *cell, t_mem *val);
   virtual t_mem conf_op(cl_memory_cell *cell, t_addr addr, t_mem *val);
+  virtual class cl_memory_cell *cfg_cell(t_addr addr);
   virtual void cfg_set(t_addr addr, t_mem val);
   virtual void cfg_write(t_addr addr, t_mem val);
   virtual t_mem cfg_get(t_addr addr);
   virtual t_mem cfg_read(t_addr addr);
-  virtual char *cfg_help(t_addr addr);
+  virtual const char *cfg_help(t_addr addr);
   
   virtual void set_cmd(class cl_cmdline *cmdline, class cl_console_base *con);
-  virtual class cl_memory_cell *register_cell(class cl_address_space *mem,
-					      t_addr addr);
+
+  virtual class cl_memory_cell *register_cell(class cl_address_space *mem, t_addr addr);
+  virtual class cl_memory_cell *register_cell(class cl_address_space *mem, t_addr addr, chars vname, chars vdesc);
   virtual class cl_memory_cell *register_cell(class cl_memory_cell *cell);
   virtual void unregister_cell(class cl_memory_cell *cell);
 
@@ -120,6 +125,7 @@
   virtual bool proc_input(void);
   virtual bool handle_input(int c);
   virtual void refresh_display(bool force);
+  virtual void draw_state_time(bool force);
   virtual void draw_display(void);
   virtual cl_hw *next_displayer(void);
   
@@ -130,7 +136,7 @@
 class cl_hws: public cl_list
 {
  public:
- cl_hws(void): cl_list(2, 2, cchars("hws")) {}
+ cl_hws(void): cl_list(2, 2, "hws") {}
   virtual t_index add(void *item);
   virtual cl_hw *next_displayer(class cl_hw *hw);
 };
@@ -140,7 +146,7 @@
 {
  protected:
   class cl_uc *uc;
-  enum hw_cath cathegory;
+  enum hw_cath category;
   int id;
   class cl_hw *partner;
  public:
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/sim.src/itsrc.cc sdcc-4.2.0+dfsg/sim/ucsim/sim.src/itsrc.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/sim.src/itsrc.cc	2017-03-12 13:28:55.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/sim.src/itsrc.cc	2022-02-03 14:06:06.000000000 +0000
@@ -25,16 +25,18 @@
 02111-1307, USA. */
 /*@1@*/
 
-#include "ddconfig.h"
+//#include "ddconfig.h"
 
 #include 
-#include 
-#include "i_string.h"
+//#include 
+//#include "i_string.h"
+
+#include "globals.h"
 
 #include "itsrccl.h"
-#include "pobjcl.h"
-#include "stypes.h"
-#include "memcl.h"
+//#include "pobjcl.h"
+//#include "stypes.h"
+//#include "memcl.h"
 
 
 /*
@@ -58,19 +60,23 @@
 {
   uc= Iuc;
   poll_priority= apoll_priority;
-  nuof    = Inuof;
-  ie_cell = Iie_cell;
-  ie_mask = Iie_mask;
-  src_cell= Isrc_cell;
-  src_mask= Isrc_mask;
-  addr    = Iaddr;
-  clr_bit = Iclr_bit;
-  indirect= Iindirect;
+  nuof     = Inuof;
+  cid      = 0;
+  ie_cell  = Iie_cell;
+  ie_mask  = Iie_mask;
+  ie_value = Iie_mask;
+  src_cell = Isrc_cell;
+  src_mask = Isrc_mask;
+  src_value= Isrc_mask;
+  addr     = Iaddr;
+  clr_bit  = Iclr_bit;
+  indirect = Iindirect;
   if (Iname != NULL)
     set_name(Iname);
   else
     set_name("unknown");
   active= true;
+  parent= NULL;
 }
 
 cl_it_src::~cl_it_src(void) {}
@@ -107,6 +113,19 @@
   set_active_status(false);
 }
 
+void
+cl_it_src::pass_over(void)
+{
+  if (is_slave())
+    {
+      if (pending() && enabled())
+	{
+	  parent->request();
+	  clear();
+	}
+    }
+}
+
 
 bool
 cl_it_src::enabled(void)
@@ -115,7 +134,7 @@
     return false;
   t_mem e= ie_cell->get();
   e&= ie_mask;
-  return e != 0;
+  return e == ie_value;
 }
 
 bool
@@ -125,14 +144,32 @@
     return false;
   t_mem s= src_cell->get();
   s&= src_mask;
-  return s != 0;
+  return s == src_value;
+}
+
+void
+cl_it_src::request(void)
+{
+  if (!src_cell)
+    return;
+  if (src_value)
+    src_cell->write(src_cell->get() | src_mask);
+  else
+    src_cell->write(src_cell->get() & ~src_mask);
 }
 
 void
 cl_it_src::clear(void)
 {
+  if (!src_cell)
+    return;
   if (clr_bit)
-    src_cell->set_bit0(src_mask);
+    {
+      if (src_value)
+        src_cell->write(src_cell->get() & ~src_mask);
+      else
+        src_cell->write(src_cell->get() | src_mask);
+    }
 }
 
 void
@@ -144,30 +181,23 @@
   
   if (cell == ie_cell)
     {
-      //printf("ITSRC ie=%x\n", *val);
       iev= *val;
     }
   if (cell == src_cell)
     {
-      //printf("ITSRC src=%x\n", *val);
       srcv= *val;
     }
-  ier= iev&ie_mask;
-  srcr= srcv&src_mask;
-  /*
-  printf("%2d iev =%x & %x = %x\n", nuof, iev, ie_mask, ier);
-  printf("%2d srcv=%x & %x = %x\n", nuof, srcv, src_mask, srcr);
-  printf("%2d ie=%s src=%s req=%s\n", nuof,
-	 ier?"true":"false",
-	 srcr?"true":"false",
-	 (ier&&srcr)?"TRUE":"FALSE");
-  */
-  if (ier)
+  ier= (iev&ie_mask) == ie_value;
+  srcr= (srcv&src_mask) == src_value;
+
+  if (!is_slave())
     {
-      if (srcr)
+      if (ier)
 	{
-	  //printf("%2d IRQ\n", nuof);
-	  uc->irq= true;
+	  if (srcr)
+	    {
+	      uc->irq= true;
+	    }
 	}
     }
 }
@@ -189,21 +219,22 @@
   Duplicates= true;
 }
 
-void *
-cl_irqs::key_of(void *item)
+const void *
+cl_irqs::key_of(const void *item) const
 {
-  class cl_it_src *itsrc= (class cl_it_src *)item;
+  const class cl_it_src *itsrc= (const class cl_it_src *)item;
   return(&itsrc->poll_priority);
 }
 
 int
-cl_irqs::compare(void *key1, void *key2)
+cl_irqs::compare(const void *key1, const void *key2)
 {
-  int *k1= (int*)key1, *k2= (int*)key2;
+  int k1= *(const int *)key1;
+  int k2= *(const int *)key2;
 
-  if (*k1 == *k2)
+  if (k1 == k2)
     return(0);
-  else if (*k1 < *k2)
+  else if (k1 < k2)
     return(-1);
   return(1);
 }
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/sim.src/itsrccl.h sdcc-4.2.0+dfsg/sim/ucsim/sim.src/itsrccl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/sim.src/itsrccl.h	2017-03-12 13:28:55.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/sim.src/itsrccl.h	2021-05-20 07:49:29.000000000 +0000
@@ -33,6 +33,7 @@
 
 #include "uccl.h"
 #include "memcl.h"
+#include "itsrccl.h"
 
 
 /*
@@ -43,14 +44,19 @@
 {
  private:
   class cl_uc *uc;
+  bool nmi;
  protected:
   class cl_memory_cell *ie_cell;
   class cl_memory_cell *src_cell;
+  class cl_it_src *parent; // slave will pass request to this
 public:
   int poll_priority;
   int    nuof;	   // Number of IT to check priority
+  int    cid;	   // identification character
   t_mem  ie_mask;  // Mask in IE register
+  t_mem  ie_value; // Enabled when masked cell equals to this
   t_mem  src_mask; // Mask of source bit in src_reg
+  t_mem  src_value;// Requested when masked cell equals to this
   t_addr addr;     // Address of service routine
   bool   clr_bit;  // Request bit must be cleared when IT accepted
   bool   active;   // Acceptance can be disabled
@@ -69,27 +75,50 @@
 	    int    apoll_priority);
   virtual ~cl_it_src(void);
   virtual int init(void);
+  virtual void set_ie_value(t_mem iv) { ie_value= iv; }
+  virtual void set_src_value(t_mem sv) { src_value= sv; }
+  virtual void set_cid(int acid) { cid= acid; }
+  virtual void set_parent(class cl_it_src *aparent) { parent= aparent; }
+  virtual void set_nmi(bool anmi) { nmi= anmi; }
+  virtual class cl_it_src *get_parent(void) { return parent; }
+  virtual bool is_nmi(void) { return nmi; }
+  virtual bool is_slave(void) { return parent != NULL; }
   
           bool is_active(void);
   virtual void set_active_status(bool Aactive);
   virtual void activate(void);
   virtual void deactivate(void);
-
+  virtual void pass_over(void);
+  
   virtual bool enabled(void);
   virtual bool pending(void);
+  virtual void request(void);
   virtual void clear(void);
 
   virtual void write(class cl_memory_cell *cell, t_mem *val);
   virtual t_mem read(class cl_memory_cell *cell);
 };
 
+/* Somehow specialized base which is used by several simulators */
+
+enum irq_nr {
+  irq_none= 0,
+  irq_nmi= 1,
+  irq_firq= 2,
+  irq_irq= 3,
+  irq_brk= 4,
+  irq_swi= 5
+};
+
+
+/* IRQ list */
 
 class cl_irqs: public cl_sorted_list
 {
 public:
   cl_irqs(t_index alimit, t_index adelta);
-  virtual void *key_of(void *item); 
-  virtual int compare(void *key1, void *key2);
+  virtual const void *key_of(const void *item) const;
+  virtual int compare(const void *key1, const void *key2);
 };
 
 
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/sim.src/iwrap.cc sdcc-4.2.0+dfsg/sim/ucsim/sim.src/iwrap.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/sim.src/iwrap.cc	2017-02-24 11:48:49.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/sim.src/iwrap.cc	2021-10-03 12:24:27.000000000 +0000
@@ -1,5 +1,8 @@
 #include "iwrap.h"
 
+int instruction_wrapper_invalid(class cl_uc *uc, t_mem code) { return resINV; }
+int instruction_wrapper_go(class cl_uc *uc, t_mem code) { return resGO; }
+
 int instruction_wrapper_00(class cl_uc *uc, t_mem code) { return uc->instruction_00(code); }
 int instruction_wrapper_01(class cl_uc *uc, t_mem code) { return uc->instruction_01(code); }
 int instruction_wrapper_02(class cl_uc *uc, t_mem code) { return uc->instruction_02(code); }
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/sim.src/iwrap.h sdcc-4.2.0+dfsg/sim/ucsim/sim.src/iwrap.h
--- sdcc-4.0.0+dfsg/sim/ucsim/sim.src/iwrap.h	2017-02-24 11:48:49.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/sim.src/iwrap.h	2021-10-03 12:24:27.000000000 +0000
@@ -3,6 +3,8 @@
 
 #include "uccl.h"
 
+extern int instruction_wrapper_invalid(class cl_uc *uc, t_mem code);
+extern int instruction_wrapper_go(class cl_uc *uc, t_mem code);
 
 extern int instruction_wrapper_00(class cl_uc *uc, t_mem code);
 extern int instruction_wrapper_00(class cl_uc *uc, t_mem code);
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/sim.src/Makefile.in sdcc-4.2.0+dfsg/sim/ucsim/sim.src/Makefile.in
--- sdcc-4.0.0+dfsg/sim/ucsim/sim.src/Makefile.in	2017-03-20 09:22:55.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/sim.src/Makefile.in	2022-01-13 08:20:03.000000000 +0000
@@ -19,10 +19,11 @@
 top_srcdir	= @top_srcdir@
 
 DEFS            = $(subs -DHAVE_CONFIG_H,,@DEFS@)
+PICOPT		= @PICOPT@
 CPPFLAGS        = @CPPFLAGS@ -I$(srcdir) -I$(top_srcdir) -I$(top_builddir) \
 		  -I$(top_srcdir)/cmd.src -I$(top_srcdir)/gui.src
-CFLAGS          = @CFLAGS@ @WALL_FLAG@
-CXXFLAGS        = @CXXFLAGS@ @WALL_FLAG@
+CFLAGS          = @WALL_FLAG@ @CFLAGS@
+CXXFLAGS        = @WALL_FLAG@ @CXXFLAGS@ $(PICOPT)
 
 prefix          = @prefix@
 exec_prefix     = @exec_prefix@
@@ -39,7 +40,7 @@
 VPATH           = @srcdir@
 
 OBJECTS         = stack.o mem.o sim.o itsrc.o brk.o arg.o \
-		  guiobj.o uc.o hw.o simif.o serial_hw.o port_hw.o \
+		  guiobj.o uc.o hw.o simif.o serial_hw.o port_hw.o dreg.o \
 		  iwrap.o var.o vcd.o
 
 
@@ -68,7 +69,12 @@
 check: test
 	./test_mem_speed
 
-test: test_mem_speed
+.PHONY:	test baseline
+test:
+	@$(MAKE) --no-print-directory -C test
+
+baseline:
+	@$(MAKE) --no-print-directory -C test baseline
 
 # Performing installation test
 # ----------------------------
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/sim.src/mem.cc sdcc-4.2.0+dfsg/sim/ucsim/sim.src/mem.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/sim.src/mem.cc	2019-07-02 08:44:01.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/sim.src/mem.cc	2022-02-03 14:06:06.000000000 +0000
@@ -30,26 +30,26 @@
 #include 
 #include 
 #include 
-#include 
-#include "i_string.h"
+//#include 
+#include 
+//#include "i_string.h"
 
 // prj
-#include "utils.h"
 #include "globals.h"
 
 // sim
-#include "simcl.h"
+//#include "simcl.h"
 
 // cmd
-#include "newcmdcl.h"
-#include "cmdutil.h"
+//#include "newcmdcl.h"
+//#include "cmdutil.h"
 
 // local
 #include "memcl.h"
-#include "hwcl.h"
 
 
 static class cl_mem_error_registry mem_error_registry;
+static unsigned int mem_uids= 0;
 
 /*
  *                                                3rd version of memory system
@@ -66,6 +66,7 @@
   start_address= 0;
   uc= 0;
   hidden= false;
+  uid= mem_uids++;
 }
 
 cl_memory::~cl_memory(void)
@@ -89,20 +90,20 @@
 	     (size-1<=0xfffff?5:
 	      (size-1<=0xffffff?6:12))))));
   if (sizeof(t_addr) > sizeof(long))
-    c+= cchars("L");//strcat(addr_format, "L");
+    c+= "L";
   else if (sizeof(t_addr) > sizeof(int))
-    c+= cchars("l");//strcat(addr_format, "l");
-  c+= cchars("x");//strcat(addr_format, "x");
-  addr_format= strdup((char*)c);
-  //data_format= (char *)malloc(10);
-  c= cchars("");
-  /*sprintf(data_*/c.format(/*"0x"*/"%%0%d", width/4+((width%4)?1:0));
+    c+= "l";
+  c+= "x";
+  addr_format = strdup(c);
+
+  c.format("%%0%d", width/4+((width%4)?1:0));
   if (sizeof(t_mem) > sizeof(long))
-    c+= cchars("L");//strcat(data_format, "L");
+    c+= "L";
   else if (sizeof(t_mem) > sizeof(int))
-    c+= cchars("l");//strcat(data_format, "l");
-  c+= cchars("x");//strcat(data_format, "x");
-  data_format= strdup((char*)c);
+    c+= "l";
+  c+= "x";
+  data_format= strdup(c);
+
   data_mask= 1;
   int w= width;
   for (--w; w; w--)
@@ -179,26 +180,42 @@
   uc->error(e);
 }
 
-
 t_addr
-cl_memory::dump(t_addr start, t_addr stop, int bpl, /*class cl_f *f*/class cl_console_base *con)
+cl_memory::dump(int smart, t_addr start, t_addr stop, int bitnr_high, int bitnr_low, int bpl, class cl_console_base *con)
 {
-  int i, step;
+  if (!con->get_fout())
+    return dump_finished;
+
+  if (bpl < 0)
+    {
+      bpl= 8;
+      if (width > 16)
+	bpl= 4;
+    }
+
+  if (start < 0)
+    start= dump_finished;
+
   t_addr lva= lowest_valid_address();
   t_addr hva= highest_valid_address();
-  class cl_f *f= con->get_fout();
-  
-  if (!f)
-    return dump_finished;
-  
+
   if (start < lva)
     start= lva;
   if (start > hva)
     return dump_finished;
+
+  int lines= -1;
+  if (stop < 0)
+    {
+      stop= hva;
+      lines= 10;
+    }
   if (stop > hva)
     stop= hva;
   if (stop < lva)
     return dump_finished;
+
+  int i, step;
   if (stop >= start)
     {
       step= +1;
@@ -213,53 +230,260 @@
       if (start - bpl < stop)
         bpl= start - stop;
     }
+
+  long label_width = -1;
+  cl_option *o = application->options->get_option("label_width");
+  if (o)
+    o->get_value(&label_width);
+  if (label_width < 0)
+    label_width = uc->vars->get_max_name_len();
+
+  bool bitmode = (smart == 2 || (smart && bitnr_high >= 0));
+
+  cl_vars_iterator vi(uc->vars);
+  const class cl_var *var = NULL;
+  const class cl_var *var_next = NULL;
+
+  int state = 0;
+
   while ((step>0)?(start < stop):(start > stop))
     {
-      // 1. field: address
-      /*f->prntf*/con->dd_cprintf("dump_address", addr_format, start);
-      /*f->write_str*/con->dd_printf(" ");
-      // 2. field: hex list
-      for (i= 0;
-           (i < bpl) &&
-             (start+i*step >= lva) &&
-             (start+i*step <= hva) &&
-             (start+i*step != stop);
-           i++)
+      if (smart && step > 0 && this == uc->rom && uc->inst_at(start))
         {
-          /*f->prntf*/con->dd_cprintf("dump_number", data_format, read/*get*/(start+i*step));
-	  /*f->write_str*/con->dd_printf(" ");
+          uc->print_disass(start, con, true);
+          start += uc->inst_length(start);
+          dump_finished = start;
+          if (lines > 0 && --lines == 0)
+            break;
+          continue;
         }
-      // 3. field: char list
-      while (i < bpl)
+
+      int n;
+
+      con->dd_color("dump_address");
+      if (state == 0)
+        con->dd_printf(addr_format, start);
+      else
+        con->dd_printf("  %-*s", atoi(addr_format+4), "");
+
+      if (smart)
         {
-	  int j;
-	  j= width/4 + ((width%4)?1:0) + 1;
-	  while (j)
-	    {
-	      /*f->write_str*/con->dd_printf(" ");
-	      j--;
-	    }
-          i++;
+          if (state != 0)
+            {
+              if (bitnr_high >= 0 || smart == 2)
+                con->dd_printf("     ");
+            }
+          else
+            {
+              if (bitnr_high >= 0 && bitnr_high == bitnr_low)
+                con->dd_printf(".%d   ", bitnr_high);
+              else if (bitnr_low > 0 || (bitnr_high > 0 && bitnr_high < width - 1))
+                con->dd_printf("[%d:%d]", bitnr_high, bitnr_low);
+              else if (smart == 2)
+                con->dd_printf("     ");
+
+              state = 1;
+
+              // Find the first var for this location.
+              //fprintf(stderr, "Find first var for %s -> %s[0x%04x][%d:%d]\n", this->get_name(), this->get_name(), start, bitnr_high, bitnr_low);
+             var = vi.first(this, start);
+             while (var)
+                {
+                  // If _any_ var for this location names bits we output in bitmode
+                  // regardless of whether the named bits are in the requested range.
+                  if (var->bitnr_high >= 0)
+                    bitmode = true;
+
+                  // If the var names bits then we skip it unless all the bits are
+                  // contained within the requested range.
+                  if (bitnr_high < 0 || var->bitnr_high < 0 || (var->bitnr_high <= bitnr_high && var->bitnr_low >= bitnr_low))
+                    break;
+
+                  //fprintf(stderr, "    skip %s -> %s[0x%04x][%d:%d]\n", var->get_name(), var->mem->get_name(), var->addr, var->bitnr_high, var->bitnr_low);
+                  var = vi.next();
+                }
+            }
+
+          //if (var_i < uc->vars->by_addr.count && var)
+            //fprintf(stderr, "state = %d, %s -> %s[0x%04x][%d:%d]\n", state, var->get_name(), var->mem->get_name(), var->addr, var->bitnr_high, var->bitnr_low);
+
+          if (var &&
+              (var->bitnr_high < 0 ||
+	       (state < 2 && ((var->bitnr_high == bitnr_high && var->bitnr_low == bitnr_low) ||
+                              (bitnr_high < 0 && var->bitnr_high == width - 1 && var->bitnr_low == 0))) ||
+	       (state == 2 && (bitnr_high < 0 || (var->bitnr_high <= bitnr_high && var->bitnr_low >= bitnr_low)))))
+            {
+              con->dd_color("dump_label");
+
+              // If we wanted specific bits but the var is just a label we need to qualify it.
+              if (bitnr_high >= 0 && var->bitnr_high < 0)
+                {
+                  if (bitnr_high == bitnr_low)
+                    con->dd_printf(" %s.%d:   %*s", var->get_name(), bitnr_high, label_width - strlen(var->get_name()), "");
+                  else
+                    con->dd_printf(" %s[%d:%d]:%*s", var->get_name(), bitnr_high, bitnr_low, label_width - strlen(var->get_name()), "");
+                }
+              else
+                con->dd_printf(" %s:%*s", var->get_name(), label_width - strlen(var->get_name()) + (smart == 2 ? 5 : 0), "");
+
+              // Find the next relevant var.
+              while ((var_next = vi.next()))
+                {
+                  // If _any_ var for this location names bits we output in bitmode
+                  // regardless of whether the named bits are in the requested range.
+                  if (var_next->bitnr_high >= 0)
+                    bitmode = true;
+
+                  // If the var names bits then we skip it unless all the bits are
+                  // contained within the requested range.
+                  if (bitnr_high < 0 || var_next->bitnr_high < 0 || (var_next->bitnr_high <= bitnr_high && var_next->bitnr_low >= bitnr_low))
+                    break;
+
+                  //fprintf(stderr, "    skip next %s -> %s[0x%04x][%d:%d]\n", var_next->get_name(), var_next->mem->get_name(), var_next->addr, var_next->bitnr_high, var_next->bitnr_low);
+                }
+              //if (var_i < uc->vars->by_addr.count && var_next)
+                  //fprintf(stderr, "    next  is %s -> %s[0x%04x][%d:%d]\n", var_next->get_name(), var_next->mem->get_name(), var_next->addr, var_next->bitnr_high, var_next->bitnr_low);
+
+              if (var_next)
+                {
+                  // If it aliases the previous we do not need to output data now.
+                  if ((var_next->bitnr_high == var->bitnr_high && var_next->bitnr_low == var->bitnr_low) ||
+                      (state == 1 &&
+                       (var->bitnr_high < 0 &&
+                        ((var_next->bitnr_high == width - 1 && var_next->bitnr_low == 0) ||
+                         (bitnr_high >= 0 && var_next->bitnr_high == bitnr_high && var_next->bitnr_low >= bitnr_low)))))
+                    {
+                      con->dd_printf("\n");
+                      if (lines > 0)
+                        lines--;
+                      var = var_next;
+                      var_next = NULL;
+                      continue;
+                    }
+                }
+            }
+          else
+            {
+              var_next = var;
+              con->dd_printf(" %-*s %s", label_width, "", (smart == 2 ? "     " : ""));
+            }
+
+          con->dd_color("dump_number");
+
+          if (bitmode)
+            {
+              int b_high, b_low;
+
+              if (var && state == 2 && var->bitnr_high >= 0)
+                b_high = var->bitnr_high, b_low = var->bitnr_low;
+              else if (bitnr_high >= 0)
+                b_high = bitnr_high, b_low = bitnr_low;
+              else
+                b_high = width - 1, b_low = 0;
+
+              con->dd_printf(" ");
+
+              /*t_mem*/u64_t m= read(start);
+
+              int i;
+              con->dd_printf("0b");
+              for (i= width - 1; i > b_high; i--)
+                con->dd_printf("-");
+              for (; i >= b_low; i--)
+                con->dd_printf("%c", (m & (1U << i)) ? '1' : '0');
+              for (; i >= 0; i--)
+                con->dd_printf("-");
+
+              int nbits = b_high - b_low + 1;
+
+              m = (m >> b_low) & (((u64_t)1U << nbits) - 1);
+
+              con->dd_printf(" 0x%0*x", (nbits > 16 ? 8 : (nbits > 8 ? 4 : 2)), m);
+
+              con->dd_color("dump_char");
+              con->dd_printf(" '");
+	      // FIXME: endian assumption: low byte first - should be a uc flag or option?
+              for (int i= 0; i <= (nbits - 1) - ((nbits - 1) % 8); i += 8)
+                con->dd_printf("%c", (isprint((m >> i) & 255) ? (m >> i) & 255 : '.'));
+              con->dd_printf("'");
+              con->dd_color("dump_number");
+
+              con->dd_printf(" %*u", (nbits > 16 ? 10 : (nbits > 8 ? 5 : 3)), m);
+
+              if (nbits == width && (m & (1U << (nbits - 1))))
+                con->dd_printf(" (%*d)", (nbits > 16 ? 10 : (nbits > 8 ? 5 : 3)), 0 - ((1U << nbits) - m));
+
+              con->dd_printf("\n");
+              if (lines > 0)
+                lines--;
+
+              state = 2;
+
+              // Only advance if there is no more to say about this location.
+              if (var_next)
+                var = var_next;
+              else
+                {
+                  start += step;
+                  dump_finished= start;
+
+                  if (lines == 0)
+                    break;
+
+                  bitmode = (smart == 2 || (smart && bitnr_high >= 0));
+                  state = 0;
+                }
+
+              continue;
+            }
+
+            // Not bit-formatted so drop through to normal output.
         }
-      for (i= 0; (i < bpl) &&
-             (start+i*step >= lva) &&
-             (start+i*step <= hva) &&
-             (start+i*step != stop);
+
+      state = 2;
+      con->dd_color("dump_number");
+
+      for (n= 0;
+           (n < bpl) &&
+             (start+n*step >= lva) &&
+             (start+n*step <= hva) &&
+             (start+n*step != stop);
+           n++)
+        {
+          if (smart && n)
+            {
+              if (uc->inst_at(start+n*step) || (var = vi.first(this, start+n*step)))
+                break;
+            }
+          con->dd_printf(" ");
+          con->dd_printf(data_format, read(start+n*step));
+        }
+      con->dd_printf("%-*s", (bpl - n) * (width/4 + ((width%4)?1:0) + 1) + 1, " ");
+
+      con->dd_color("dump_char");
+      for (i= 0; i < n &&
+             start+i*step >= lva &&
+             start+i*step <= hva &&
+             start+i*step != stop;
            i++)
         {
           long c= read(start+i*step);
-          /*f->prntf*/con->dd_cprintf("dump_char", "%c", isprint(255&c)?(255&c):'.');
-          if (width > 8)
-            /*f->prntf*/con->dd_cprintf("dump_char", "%c", isprint(255&(c>>8))?(255&(c>>8)):'.');
-          if (width > 16)
-            /*f->prntf*/con->dd_cprintf("dump_char", "%c", isprint(255&(c>>16))?(255&(c>>16)):'.');
-          if (width > 24)
-            /*f->prntf*/con->dd_cprintf("dump_char", "%c", isprint(255&(c>>24))?(255&(c>>24)):'.');
+	  // FIXME: endian assumption: low byte first - should be a uc flag or option?
+          for (int i= 0; i <= (width - 1) - ((width - 1) % 8); i += 8)
+            con->dd_printf("%c", (isprint((c >> i) & 255) ? (c >> i) & 255 : '.'));
         }
-      /*f->prntf*/con->dd_printf("\n");
-      dump_finished= start+i*step;
-      start+= i*step;
+      con->dd_printf("\n");
+
+      start+= n*step;
+      dump_finished= start;
+      state = 0;
+      if (lines > 0 && --lines == 0)
+        break;
     }
+
+  if (dump_finished >= hva)
+    dump_finished= lva;
+
   return(dump_finished);
 }
 
@@ -270,57 +494,37 @@
   t_addr hva= highest_valid_address();
   class cl_f *f= con->get_fout();
 
-  if (!f)
-    return dump_finished;
-  if (start < 0)
-    start= dump_finished;
-  if (stop < 0)
-    stop= start + 10*8 - 1;
-  
-  if (start < lva)
-    start= lva;
-  if (start > hva)
-    return dump_finished;
-  if (stop > hva)
-    stop= hva;
-  if (stop < lva)
-    return dump_finished;
-  
-  if (bpl < 0)
-    bpl= 8;
   t_addr a= start;
   t_mem d= read(a);
   char last= '\n';
-  con->dd_printf("%s", (char*)(con->get_color_ansiseq("dump_char")));
-  while ((a <= stop) &&
-	 (d != 0) &&
+  con->dd_printf("%s", con->get_color_ansiseq("dump_char").c_str());
+  while ((d != 0) &&
 	 (a <= hva))
     {
       char c= d;
-      int i= d;
-      chars s;
+      int i= d & 0xff;
       if (a >= lva)
 	{
 	  switch (c)
 	    { // ' " ? \ a b f n r t v
-	    case '\'': s= (char*)"\\\'"; f->write((char*)s, s.len()); break;
-	    case '\"': s= (char*)"\\\""; f->write((char*)s, s.len()); break;
-	    case '\?': s= (char*)"\\\?"; f->write((char*)s, s.len()); break;
-	    case '\\': s= (char*)"\\\\"; f->write((char*)s, s.len()); break;
-	    case '\a': s= (char*)"\\a"; f->write((char*)s, s.len()); break;
-	    case '\b': s= (char*)"\\b"; f->write((char*)s, s.len()); break;
-	    case '\f': s= (char*)"\\f"; f->write((char*)s, s.len()); break;
-	    case '\n': s= (char*)"\\n"; f->write((char*)s, s.len()); break;
-	    case '\r': s= (char*)"\\r"; f->write((char*)s, s.len()); break;
-	    case '\t': s= (char*)"\\t"; f->write((char*)s, s.len()); break;
-	    case '\v': s= (char*)"\\v"; f->write((char*)s, s.len()); break;
+	    case '\'': f->write("\\\'", 2); break;
+	    case '\"': f->write("\\\"", 2); break;
+	    case '\?': f->write("\\\?", 2); break;
+	    case '\\': f->write("\\\\", 2); break;
+	    case '\a': f->write("\\a", 2); break;
+	    case '\b': f->write("\\b", 2); break;
+	    case '\f': f->write("\\f", 2); break;
+	    case '\n': f->write("\\n", 2); break;
+	    case '\r': f->write("\\r", 2); break;
+	    case '\t': f->write("\\t", 2); break;
+	    case '\v': f->write("\\v", 2); break;
 	    default:
 	      if (isprint(i))
 		f->write(&c, 1);
 	      else
 		{
-		  s.format("\\%03o", i);
-		  f->write((char*)s, s.len());
+		  chars s = chars("", "\\%03o", i);
+		  f->write(s.c_str(), s.len());
 		}
 	    }
 	  last= c;
@@ -329,7 +533,12 @@
     }
   if (last != '\n')
     f->write_str("\n");
-  return dump_finished= a;
+
+  dump_finished= a;
+  if (dump_finished >= hva)
+    dump_finished= lva;
+
+  return dump_finished;
 }
 
 t_addr
@@ -339,24 +548,9 @@
   t_addr hva= highest_valid_address();
   class cl_f *f= con->get_fout();
 
-  if (!f)
-    return dump_finished;
-  if (start < 0)
-    start= dump_finished;
   if (stop < 0)
-    stop= start + 10*8 - 1;
+    stop= start + 10 * bpl - 1;
 
-  if (start < lva)
-    start= lva;
-  if (start > hva)
-    return dump_finished;
-  if (stop > hva)
-    stop= hva;
-  if (stop < lva)
-    return dump_finished;
-
-  if (bpl < 0)
-    bpl= 8;
   t_addr a= start;
   t_mem d= read(a);
   while ((a <= stop) &&
@@ -369,7 +563,12 @@
 	}
       d= read(++a);
     }
-  return dump_finished= a;
+
+  dump_finished= a;
+  if (dump_finished >= hva)
+    dump_finished= lva;
+
+  return dump_finished;
 }
 
 t_addr
@@ -381,14 +580,11 @@
   t_addr start_line;
   class cl_f *f= con->get_fout();
   
-  if (!f)
-    return dump_finished;
-  if (start < 0)
-    start= dump_finished;
+  if (stop < 0)
+    stop= start + 10 * bpl - 1;
+
   if (start < lva)
     start= lva;
-  if (stop < 0)
-    stop= start + 10*8 - 1;
   if (stop > hva)
     stop= hva;
 
@@ -403,9 +599,6 @@
   
   if (start > stop)
     return dump_finished= stop;
-  
-  if (bpl < 0)
-    bpl= 16;
   if (bpl > 32)
     bpl= 32;
   t_addr a= start;
@@ -429,7 +622,7 @@
 	      sum+= c;
 	      c= start_line & 0xff;
 	      sum+= c;
-	      int i;
+	      unsigned int i;
 	      for (i= 0; i < a-start_line; i++)
 		{
 		  c= read(start_line + i);
@@ -444,56 +637,11 @@
 	}
     }
   f->write_str(":00000001FF\r\n");
-  return dump_finished= a;
-}
 
-t_addr
-cl_memory::dump(/*class cl_f *f*/class cl_console_base *con)
-{
-  if (con->get_fout() == NULL)
-    return dump_finished;
-  return(dump(dump_finished, dump_finished+10*8-1, 8, /*f*/con));
-}
-
-t_addr
-cl_memory::dump(enum dump_format fmt,
-		t_addr start, t_addr stop, int bpl,
-		/*class cl_f *f*/class cl_console_base *con)
-{
-  t_addr lva= lowest_valid_address();
-  t_addr hva= highest_valid_address();
-
-  //if (!f)
-  //return dump_finished;
-  if (start < 0)
-    start= dump_finished;
-  if (stop < 0)
-    stop= start + 10*8 - 1;
+  dump_finished= a;
+  if (dump_finished >= hva)
+    dump_finished= lva;
 
-  if (start < lva)
-    start= lva;
-  if (start > hva)
-    return dump_finished;
-  if (stop > hva)
-    stop= hva;
-  if (stop < lva)
-    return dump_finished;
-  
-  if (bpl < 0)
-    bpl= 8;
-  switch (fmt & df_format)
-    {
-    case df_hex:
-      return dump(start, stop, bpl, /*f*/con);
-    case df_string:
-      return dump_s(start, stop, bpl, /*f*/con);
-    case df_ihex:
-      return dump_i(start, stop, bpl, /*f*/con);
-    case df_binary:
-      return dump_b(start, stop, bpl, /*f*/con);
-    default:
-      return dump(start, stop, bpl, /*f*/con);
-    }
   return dump_finished;
 }
 
@@ -543,16 +691,15 @@
 }
 
 void
-cl_memory::print_info(chars pre, class cl_console_base *con)
+cl_memory::print_info(const char *pre, class cl_console_base *con)
 {
-  char *n= (char*)(get_name());
   if (!hidden)
     {
-      con->dd_printf("%s0x%06x-0x%06x %8d %s (%d,%s,%s)\n", (char*)pre,
+      con->dd_printf("%s0x%06x-0x%06x %8d %s (%d,%s,%s)\n", pre,
 		     AU(get_start_address()),
 		     AU(highest_valid_address()),
 		     AU(get_size()),
-		     n,
+		     get_name(),
 		     width, data_format, addr_format);
     }
 }
@@ -562,45 +709,20 @@
  *                                                             Memory operators
  */
 
-cl_memory_operator::cl_memory_operator(class cl_memory_cell *acell/*,
-								    t_addr addr*/):
+cl_memory_operator::cl_memory_operator(class cl_memory_cell *acell):
   cl_base()
 {
   cell= acell;
   if (cell)
     {
-      //data= cell->data;
       mask= cell->mask;
     }
   else
     {
-      //data= 0;
       mask= ~0;
     }
   next_operator= 0;
-  //address= addr;
 }
-/*
-cl_memory_operator::cl_memory_operator(class cl_memory_cell *acell,
-				       t_addr addr,
-				       t_mem *data_place, t_mem the_mask):
-  cl_base()
-{
-  cell= acell;
-  //data= data_place;
-  mask= the_mask;
-  next_operator= 0;
-  address= addr;
-}
-*/
-/*
-void
-cl_memory_operator::set_data(t_mem *data_place, t_mem the_mask)
-{
-  data= data_place;
-  mask= the_mask;
-}
-*/
 
 t_mem
 cl_memory_operator::read(void)
@@ -608,7 +730,7 @@
   if (next_operator)
     return(next_operator->read());
   else if (cell)
-    return(/* *data*/cell->get());
+    return(cell->get());
   return 0;
 }
 
@@ -618,7 +740,7 @@
   if (next_operator)
     return(next_operator->write(val));
   else if (cell)
-    return(/* *data=*/cell->set(val & mask));
+    return(cell->set(val));
   return val;
 }
 
@@ -626,9 +748,8 @@
 /* Memory operator for bank switcher */
 
 cl_bank_switcher_operator::cl_bank_switcher_operator(class cl_memory_cell *acell,
-						     /*t_addr addr,*/
 						     class cl_banker *the_banker):
-  cl_memory_operator(acell/*, addr*/)
+  cl_memory_operator(acell)
 {
   banker= the_banker;
   set_name("bank_switcher");
@@ -639,20 +760,20 @@
 {
   if (next_operator)
     next_operator->write(val);
-  if (cell) /* *data=*/ cell->set(val & mask);
+  if (cell)
+    cell->set(val);
   banker->activate(NULL);
   if (cell)
     return cell->get();
-  return /* *data*/ 0;  
+  return 0;  
 }
 
 
 /* Memory operator for hw callbacks */
 
-cl_hw_operator::cl_hw_operator(class cl_memory_cell *acell/*, t_addr addr*/,
-			       //t_mem *data_place, t_mem the_mask,
+cl_hw_operator::cl_hw_operator(class cl_memory_cell *acell,
 			       class cl_hw *ahw):
-  cl_memory_operator(acell/*, addr*//*, data_place, the_mask*/)
+  cl_memory_operator(acell)
 {
   hw= ahw;
   set_name(chars("hw:")+hw->get_name());
@@ -664,24 +785,32 @@
 {
   t_mem d1= 0, d2= 0;
 
-  if (hw)
-    d1= hw->read(cell);
+  if (hw && !hw->active)
+    {
+      hw->active = true;
+      d1= hw->read(cell);
+      hw->active = false;
+    }
 
   if (next_operator)
     d2= next_operator->read();
 
-  return(hw?d1:d2);
+  return(hw && !hw->active ? d1 : d2);
 }
 
 t_mem
 cl_hw_operator::read(enum hw_cath skip)
 {
-  t_mem d1= 0/* *data*/, d2= d1;
+  t_mem d1= 0, d2= d1;
   bool use= false;
 
-  if (hw &&
-      hw->cathegory != skip)
-    use= true, d1= hw->read(cell);
+  if (hw && hw->category != skip && !hw->active)
+    {
+      use= true;
+      hw->active= true;
+      d1= hw->read(cell);
+      hw->active= false;
+    }
 
   if (next_operator)
     d2= next_operator->read();
@@ -696,21 +825,24 @@
 t_mem
 cl_hw_operator::write(t_mem val)
 {
-  if (hw)
-    hw->write(cell, &val);
+  if (hw && !hw->active)
+    {
+      hw->active= true;
+      hw->write(cell, &val);
+      hw->active= false;
+    }
+
   if (next_operator)
     val= next_operator->write(val);
-  //if (cell) return(/* *data=*//*cell->set(val & mask)*/val);
   return val;
 }
 
 
 /* Write event break on cell */
 
-cl_write_operator::cl_write_operator(class cl_memory_cell *acell/*, t_addr addr*/,
-				     //t_mem *data_place, t_mem the_mask,
+cl_write_operator::cl_write_operator(class cl_memory_cell *acell,
 				     class cl_uc *auc, class cl_brk *the_bp):
-  cl_event_break_operator(acell/*, addr*//*, data_place, the_mask*/, auc, the_bp)
+  cl_event_break_operator(acell, auc, the_bp)
 {
   uc= auc;
   bp= the_bp;
@@ -720,23 +852,21 @@
 t_mem
 cl_write_operator::write(t_mem val)
 {
-  //printf("write event at 0x%x bp=%p\n",address,bp);
   if (bp->do_hit())
     uc->events->add(bp);
   if (next_operator)
     return(next_operator->write(val));
   else if (cell)
-    return(/* *data=*/cell->set(val & mask));
+    return(cell->set(val));
   return val;
 }
 
 
 /* Read event break on cell */
 
-cl_read_operator::cl_read_operator(class cl_memory_cell *acell/*, t_addr addr*/,
-				   //t_mem *data_place, t_mem the_mask,
+cl_read_operator::cl_read_operator(class cl_memory_cell *acell,
 				   class cl_uc *auc, class cl_brk *the_bp):
-  cl_event_break_operator(acell/*, addr*//*, data_place, the_mask*/, auc, the_bp)
+  cl_event_break_operator(acell, auc, the_bp)
 {
   uc= auc;
   bp= the_bp;
@@ -746,13 +876,12 @@
 t_mem
 cl_read_operator::read(void)
 {
-  //printf("read event at 0x%x bp=%p\n",address,bp);
   if (bp->do_hit())
     uc->events->add(bp);
   if (next_operator)
     return(next_operator->read());
   else if (cell)
-    return(/* *data*/cell->get());
+    return(cell->get());
   return 0;
 }
 
@@ -761,116 +890,134 @@
  *                                                                  Cell data
  */
 
+// 8 bit cell;
+
 t_mem
-cl_cell_data::d()
+cl_cell8::d()
 {
-  return data?(*data):0;
+  return data?(*((u8_t*)data)):0;
 }
 
 void
-cl_cell_data::d(t_mem v)
+cl_cell8::d(t_mem v)
 {
-  data?(*data=v):0;
+  data?(*((u8_t*)data)=(u8_t)v):0;
 }
 
 void
-cl_cell_data::dl(t_mem v)
+cl_cell8::dl(t_mem v)
 {
-  data?(*data=v):0;
+  data?(*((u8_t*)data)=(u8_t)v):0;
 }
 
-// bit cell for bit spaces
+// 8 bit cell for bit spaces
 
 t_mem
-cl_bit_cell::d()
+cl_bit_cell8::d()
 {
   if (!data)
     return 0;
-  return (*data&mask)?1:0;
+  u8_t x= *((u8_t*)data);
+  x&= mask;
+  return x?1:0;
 }
 
 void
-cl_bit_cell::d(t_mem v)
+cl_bit_cell8::d(t_mem v)
 {
   if (!data)
     return;
   if (v)
-    *data|= mask;
+    *((u8_t*)data) |= (u8_t)mask;
   else
-    *data&= ~mask;
+    *((u8_t*)data) &= ~((u8_t)mask);
 }
 
 
-// 8 bit cell;
+// 16 bit cell;
 
 t_mem
-cl_cell8::d()
+cl_cell16::d()
 {
-  return data?((/*u8_t*/uchar)*data):0;
+  return data?(*((u16_t*)data)):0;
 }
 
 void
-cl_cell8::d(t_mem v)
+cl_cell16::d(t_mem v)
 {
-  data?(*data=(/*u8_t*/uchar)v):0;
+  data?(*((u16_t*)data)=(u16_t)v):0;
 }
 
-// 8 bit cell for bit spaces
+void
+cl_cell16::dl(t_mem v)
+{
+  data?(*((u16_t*)data)=(u16_t)v):0;
+}
+
+// 16 bit cell for bit spaces
 
 t_mem
-cl_bit_cell8::d()
+cl_bit_cell16::d()
 {
   if (!data)
     return 0;
-  /*u8_t*/uchar x= (/*u8_t*/uchar) *data;
+  u16_t x= *((u16_t*)data);
   x&= mask;
   return x?1:0;
 }
 
 void
-cl_bit_cell8::d(t_mem v)
+cl_bit_cell16::d(t_mem v)
 {
   if (!data)
     return;
   if (v)
-    *data |= (/*u8_t*/uchar)mask;
+    *((u16_t*)data) |= (u16_t)mask;
   else
-    *data &= ~(/*u8_t*/uchar)mask;
+    *((u16_t*)data) &= ~((u16_t)mask);
 }
 
-// 16 bit cell;
+// 32 bit cell;
 
 t_mem
-cl_cell16::d()
+cl_cell32::d()
 {
-  return data?((u16_t)*data):0;
+  return data?(*((u32_t*)data)):0;
 }
 
 void
-cl_cell16::d(t_mem v)
+cl_cell32::d(t_mem v)
 {
-  data?(*data=(u16_t)v):0;
+  data?(*((u32_t*)data)=(u32_t)v):0;
 }
 
-// 16 bit cell for bit spaces
+void
+cl_cell32::dl(t_mem v)
+{
+  data?(*((u32_t*)data)=(u32_t)v):0;
+}
+
+// 32 bit cell for bit spaces
 
 t_mem
-cl_bit_cell16::d()
+cl_bit_cell32::d()
 {
   if (!data)
     return 0;
-  return (((u16_t)*data)&((u16_t)mask))?1:0;
+  u32_t x= *((u32_t*)data);
+  x&= mask;
+  return x?1:0;
 }
 
 void
-cl_bit_cell16::d(t_mem v)
+cl_bit_cell32::d(t_mem v)
 {
   if (!data)
     return;
   if (v)
-    *data |= (u16_t)mask;
+    *((u32_t*)data) |= (u32_t)mask;
   else
-    *data &= ~(u16_t)mask;
+    *((u32_t*)data) &= ~((u32_t)mask);
 }
 
 
@@ -878,16 +1025,32 @@
  *                                                                  Memory cell
  */
 
-cl_memory_cell::cl_memory_cell(uchar awidth)//: cl_base()
+cl_memory_cell::cl_memory_cell()
+{
+  data= 0;
+  flags= CELL_NON_DECODED;
+  width= 8;
+  def_data= 0;
+  operators= NULL;
+#ifdef STATISTIC
+  nuof_writes= nuof_reads= 0;
+#endif
+  mask= 1;
+  int w= width;
+  for (--w; w; w--)
+    {
+      mask<<= 1;
+      mask|= 1;
+    }
+}
+
+cl_memory_cell::cl_memory_cell(uchar awidth)
 {
   data= 0;
   flags= CELL_NON_DECODED;
   width= awidth;
-  //*data= 0;
   def_data= 0;
   operators= NULL;
-  //bank= 0;
-  //banked_data_ptrs= 0;
 #ifdef STATISTIC
   nuof_writes= nuof_reads= 0;
 #endif
@@ -902,29 +1065,28 @@
 
 cl_memory_cell::~cl_memory_cell(void)
 {
-  if ((flags & CELL_NON_DECODED) &&
-      data)
-    ;//free(data);
 }
 
 int
 cl_memory_cell::init(void)
 {
-  //cl_base::init();
   data= &def_data;
-  //flags= CELL_NON_DECODED;
-  /*mask= 1;
+  return(0);
+}
+
+void
+cl_memory_cell::set_width(uchar awidth)
+{
+  width= awidth;
+  mask= 1;
   int w= width;
   for (--w; w; w--)
     {
       mask<<= 1;
       mask|= 1;
-      }*/
-  //set(0/*rand()*/);
-  return(0);
+    }
 }
 
-
 uchar
 cl_memory_cell::get_flags(void)
 {
@@ -958,7 +1120,7 @@
 {
   if ((flags & CELL_NON_DECODED) == 0)
     {
-      data= &def_data;//(t_mem *)malloc(sizeof(t_mem));
+      data= &def_data;
       flags|= CELL_NON_DECODED;
     }
 }
@@ -966,12 +1128,10 @@
 void
 cl_memory_cell::decode(class cl_memory_chip *chip, t_addr addr)
 {
-  if (flags & CELL_NON_DECODED)
-    ;//free(data);
   data= chip->get_slot(addr);
   if (!data)
     {
-      data= &def_data;//(t_mem *)malloc(sizeof(t_mem));
+      data= &def_data;
       flags|= CELL_NON_DECODED;
     }
   else
@@ -979,7 +1139,7 @@
 }
 
 void
-cl_memory_cell::decode(t_mem *data_ptr)
+cl_memory_cell::decode(void *data_ptr)
 {
   if (data_ptr == NULL)
     {
@@ -994,7 +1154,7 @@
 }
 
 void
-cl_memory_cell::decode(t_mem *data_ptr, t_mem bit_mask)
+cl_memory_cell::decode(void *data_ptr, t_mem bit_mask)
 {
   if (data_ptr == NULL)
     {
@@ -1017,7 +1177,7 @@
 #endif
   if (operators)
     return(operators->read());
-  return /* *data*/d();
+  return d();
 }
 
 t_mem
@@ -1028,13 +1188,13 @@
 #endif
   if (operators)
     return(operators->read(skip));
-  return /* *data*/d();
+  return d();
 }
 
 t_mem
 cl_memory_cell::get(void)
 {
-  return /* *data*/d();
+  return d();
 }
 
 t_mem
@@ -1062,8 +1222,8 @@
   if (width == 1)
     d(val);
   else
-    /* *data=*/d(val & mask);
-  return /* *data*/d();
+    d(val & mask);
+  return d();
 }
 
 t_mem
@@ -1072,142 +1232,72 @@
   if (width == 1)
     dl(val);
   else
-    /* *data=*/dl(val & mask);
-  return /* *data*/d();
-}
-
-t_mem
-cl_memory_cell::add(long what)
-{
-  /* *data=*/ d( (*data + what) & mask);
-  return(/* *data*/d());
-}
-
-t_mem
-cl_memory_cell::wadd(long what)
-{
-  t_mem d= (*data + what) & mask;
-  return(write(d));
-}
-
-void
-cl_memory_cell::set_bit1(t_mem bits)
-{
-  bits&= mask;
-  /*(*data)|=*//*d*/set(d()| bits);
-}
-
-void
-cl_memory_cell::write_bit1(t_mem bits)
-{
-  bits&= mask;
-  /*(*data)|=*//*d*/write(d()| bits);
-}
-
-void
-cl_memory_cell::set_bit0(t_mem bits)
-{
-  bits&= mask;
-  /*(*data)&=*//*d*/set(d()& ~bits);
-}
-
-void
-cl_memory_cell::write_bit0(t_mem bits)
-{
-  bits&= mask;
-  /*(*data)&=*//*d*/write(d()& ~bits);
+    dl(val & mask);
+  return d();
 }
 
 void
-cl_memory_cell::toggle_bits(t_mem bits)
+cl_memory_cell::append_operator(class cl_memory_operator *op)
 {
-  bits&= mask;
-  /*d*/set(d() ^ bits);
-}
+  class cl_memory_operator **op_p;
 
-void
-cl_memory_cell::wtoggle_bits(t_mem bits)
-{
-  bits&= mask;
-  /*d*/write(d() ^ bits);
+  for (op_p = &operators; *op_p; op_p = &(*op_p)->next_operator)
+    ;
+  op->next_operator = NULL;
+  *op_p = op;
 }
 
-
 void
-cl_memory_cell::append_operator(class cl_memory_operator *op)
+cl_memory_cell::prepend_operator(class cl_memory_operator *op)
 {
-  if (!operators)
-    operators= op;
-  else
+  if (op)
     {
-      class cl_memory_operator *o= operators, *n;
-      n= o->get_next();
-      while (n)
-	{
-	  o= n;
-	  n= o->get_next();
-	}
-      o->set_next(op);
+      op->next_operator = operators;
+      operators = op;
     }
 }
 
 void
-cl_memory_cell::prepend_operator(class cl_memory_operator *op)
+cl_memory_cell::remove_operator(class cl_memory_operator *op)
 {
-  if (op)
+  for (class cl_memory_operator **op_p = &operators; *op_p; op_p = &(*op_p)->next_operator)
     {
-      op->set_next(operators);
-      operators= op;
+      if (*op_p == op)
+        {
+          *op_p = op->next_operator;
+          op->next_operator = NULL;
+          break;
+        }
     }
 }
 
 void
 cl_memory_cell::del_operator(class cl_brk *brk)
 {
-  if (!operators)
-    return;
-  class cl_memory_operator *op= operators;
-  if (operators->match(brk))
-    {
-      operators= op->get_next();
-      delete op;
-    }
-  else
+  for (class cl_memory_operator **op_p = &operators; *op_p; op_p = &(*op_p)->next_operator)
     {
-      while (op->get_next() &&
-	     !op->get_next()->match(brk))
-	op= op->get_next();
-      if (op->get_next())
-	{
-	  class cl_memory_operator *m= op->get_next();
-	  op->set_next(m->get_next());;
-	  delete m;
-	}
+      if ((*op_p)->match(brk))
+        {
+          class cl_memory_operator *old = *op_p;
+          *op_p = (*op_p)->next_operator;
+          delete old;
+          break;
+        }
     }
 }
 
 void 	 
 cl_memory_cell::del_operator(class cl_hw *hw)
 {
-  if (!operators)
-    return;
-  class cl_memory_operator *op= operators;
-  if (operators->match(hw))
+  for (class cl_memory_operator **op_p = &operators; *op_p; op_p = &(*op_p)->next_operator)
     {
-      operators= op->get_next();
-      delete op;
-    }
-  else
-    {
-      while (op->get_next() &&
-	     !op->get_next()->match(hw))
-	op= op->get_next();
-      if (op->get_next())
-	{
-	  class cl_memory_operator *m= op->get_next();
-	  op->set_next(m->get_next());
-	  delete m;
-	}
+      if ((*op_p)->match(hw))
+        {
+          class cl_memory_operator *old = *op_p;
+          *op_p = (*op_p)->next_operator;
+          delete old;
+          break;
+        }
     }
 }
 
@@ -1228,9 +1318,9 @@
 }
 
 class cl_memory_cell *
-cl_memory_cell::add_hw(class cl_hw *hw/*, t_addr addr*/)
+cl_memory_cell::add_hw(class cl_hw *hw)
 {
-  class cl_hw_operator *o= new cl_hw_operator(this/*, addr*//*, data, mask*/, hw);
+  class cl_hw_operator *o= new cl_hw_operator(this, hw);
   append_operator(o);
   return(this);
 }
@@ -1241,12 +1331,6 @@
   del_operator(hw); 	 
 }
 
-/*class cl_hw *
-cl_memory_cell::get_hw(int ith)
-{
-  return(0);
-}*/
-
 class cl_event_handler *
 cl_memory_cell::get_event_handler(void)
 {
@@ -1254,11 +1338,9 @@
 }
 
 void
-cl_memory_cell::print_info(chars pre, class cl_console_base *con)
+cl_memory_cell::print_info(const char *pre, class cl_console_base *con)
 {
-  con->dd_printf("%sFlags:", (char*)pre);
-  if (flags & CELL_VAR)
-    con->dd_printf(" VAR");
+  con->dd_printf("%sFlags:", pre);
   if (flags & CELL_INST)
     con->dd_printf(" INST");
   if (flags & CELL_FETCH_BRK)
@@ -1272,7 +1354,7 @@
 }
 
 void
-cl_memory_cell::print_operators(chars pre, class cl_console_base *con)
+cl_memory_cell::print_operators(const char *pre, class cl_console_base *con)
 {
   class cl_memory_operator *o= operators;
   if (!operators)
@@ -1280,7 +1362,7 @@
   int i= 0;
   while (o)
     {
-      printf("%s %02d. %s\n", (char*)pre, i, o->get_name("?"));
+      printf("%s %02d. %s\n", pre, i, o->get_name("?"));
       i++;
       o= o->get_next();
     }
@@ -1292,20 +1374,32 @@
  */
 
 t_mem
+cl_dummy_cell::d()
+{
+  return data?(*((u32_t*)data)):0;
+}
+
+void
+cl_dummy_cell::d(t_mem v)
+{
+  *((u32_t*)data)= (u32_t)v;
+}
+
+t_mem
 cl_dummy_cell::write(t_mem val)
 {
 #ifdef STATISTIC
   nuof_writes++;
 #endif
-  *data= rand() & mask;
-  return(*data);
+  *((u32_t*)data)= rand() & mask;
+  return(*((u32_t*)data));
 }
 
 t_mem
 cl_dummy_cell::set(t_mem val)
 {
-  *data= rand() & mask;
-  return(*data);
+  *((u32_t*)data)= rand() & mask;
+  return(*((u32_t*)data));
 }
 
 
@@ -1317,37 +1411,52 @@
 				   t_addr astart, t_addr asize, int awidth):
   cl_memory(id, asize, awidth)
 {
-  class cl_memory_cell c(awidth);
-  class cl_bit_cell8 bc8(awidth);
-  class cl_cell8 c8(awidth);
-  class cl_cell16 c16(awidth);
-  class cl_memory_cell *cell= &c;
   start_address= astart;
   decoders= new cl_decoder_list(2, 2, false);
   cella= (class cl_memory_cell *)malloc(size * sizeof(class cl_memory_cell));
-  if (awidth == 1)
-    cell= &bc8;
-  else if (awidth <= 8)
-    cell= &c8;
-  else if (awidth <= 16)
-    cell= &c16;
-  //cell->init();
-  int i;
+  dummy= new cl_dummy_cell(awidth);
+  dummy->init();
+}
+
+int
+cl_address_space::init(void)
+{
+  cl_memory::init();
+  class cl_memory_cell *cell= cell_template();
+  unsigned int i;
   for (i= 0; i < size; i++)
     {
       void *p1= &(cella[i]);
       void *p2= cell;
-      memcpy(p1, p2, sizeof(c));
+      memcpy(p1, p2, sizeof(class cl_cell32));
       cella[i].init();
     }
-  dummy= new cl_dummy_cell(awidth);
-  dummy->init();
+  return 0;
+}
+
+static class cl_bit_cell8 bc8_tmpl;
+static class cl_cell8 c8_tmpl;
+static class cl_cell16 c16_tmpl;
+static class cl_cell32 c32_tmpl;
+
+class cl_memory_cell *
+cl_address_space::cell_template()
+{
+  class cl_memory_cell *cell= &c32_tmpl;
+  if (width == 1)
+    cell= &bc8_tmpl;
+  else if (width <= 8)
+    cell= &c8_tmpl;
+  else if (width <= 16)
+    cell= &c16_tmpl;
+  if (cell) cell->set_width(width);
+  return cell;
 }
 
 cl_address_space::~cl_address_space(void)
 {
   delete decoders;
-  int i;
+  unsigned int i;
   for (i= 0; i < size; i++)
     {
       cella[i].~cl_memory_cell();
@@ -1437,7 +1546,7 @@
     }
   /* *(cella[idx].data)=*/cella[idx].download( val/*&(data_mask)*/);
 }
-
+/*
 t_mem
 cl_address_space::wadd(t_addr addr, long what)
 {
@@ -1449,30 +1558,7 @@
     }
   return(cella[idx].wadd(what));
 }
-
-/* Set or clear bits, without callbacks */
-
-void
-cl_address_space::set_bit1(t_addr addr, t_mem bits)
-{
-  t_addr idx= addr-start_address;
-  if (idx >= size ||
-      addr < start_address)
-    return;
-  class cl_memory_cell *cell= &(cella[idx]);
-  cell->set_bit1(bits);
-}
-
-void
-cl_address_space::set_bit0(t_addr addr, t_mem bits)
-{
-  t_addr idx= addr-start_address;
-  if (idx >= size ||
-      addr < start_address)
-    return;
-  class cl_memory_cell *cell= &(cella[idx]);
-  cell->set_bit0(bits);
-}
+*/
 
 
 class cl_memory_cell *
@@ -1541,7 +1627,7 @@
 class cl_memory_cell *
 cl_address_space::search_cell(enum cell_flag flag, bool value, t_addr *addr)
 {
-  int i;
+  unsigned int i;
 
   for (i= 0; i < size; i++)
     {
@@ -1662,8 +1748,8 @@
 	}
       else if (d->is_in(begin, end))
 	{
-	  // decoder sould shrink
-	  D("    Sould shrink\n");
+	  // decoder should shrink
+	  D("    Should shrink\n");
 	  if (d->shrink_out_of(begin, end))
 	    {
 	      D("    Can be removed after shrink\n");
@@ -1695,7 +1781,9 @@
   class cl_memory_cell *cell= &cella[idx];
   cell->add_hw(hw/*, addr*/);
   if (announce)
-    ;//uc->sim->/*app->*/mem_cell_changed(this, addr);//FIXME
+    {
+      //uc->sim->/*app->*/mem_cell_changed(this, addr);//FIXME
+    }
   return(cell);
 }
 
@@ -1771,16 +1859,15 @@
 }
 
 void
-cl_address_space::print_info(chars pre, class cl_console_base *con)
+cl_address_space::print_info(const char *pre, class cl_console_base *con)
 {
-  char *n= (char*)(get_name());
   if (!hidden)
     {
-      con->dd_printf("%s0x%06x-0x%06x %8d %s (%d,%s,%s)\n", (char*)pre,
+      con->dd_printf("%s0x%06x-0x%06x %8d %s (%d,%s,%s)\n", pre,
 		     AU(get_start_address()),
 		     AU(highest_valid_address()),
 		     AU(get_size()),
-		     n,
+		     get_name(),
 		     width, data_format, addr_format);
     }
 }
@@ -1790,20 +1877,20 @@
  * List of address spaces
  */
 
-cl_address_space_list::cl_address_space_list(class cl_uc *the_uc):
-  cl_list(2, 2, "address spaces")
+cl_memory_list::cl_memory_list(class cl_uc *the_uc, const char *name):
+  cl_list(2, 2, name)
 {
   uc= the_uc;
 }
 
 t_index
-cl_address_space_list::add(class cl_address_space *mem)
+cl_memory_list::add(class cl_memory *mem)
 {
-  mem->set_uc(uc);
   t_index ret= cl_list::add(mem);
-  if (uc)
+  mem->set_uc(uc);
+  if (uc && mem->is_address_space())
     {
-      class cl_event_address_space_added e(mem);
+      class cl_event_address_space_added e((cl_address_space *)mem);
       uc->handle_event(e);
     }
   return(ret);
@@ -1814,13 +1901,27 @@
  *                                                                  Memory chip
  */
 
+cl_chip_data::cl_chip_data(const char *id, t_addr asize, int awidth):
+  cl_memory(id, asize, awidth)
+{
+}
+
 cl_memory_chip::cl_memory_chip(const char *id,
 			       int asize,
 			       int awidth,
 			       int initial):
-  cl_memory(id, asize, awidth)
+  cl_chip_data(id, asize, awidth)
 {
-  array= (t_mem *)malloc(size * sizeof(t_mem));
+  if (awidth > 32)
+    width= 32;
+  if (width <= 8)
+    bwidth= 1;
+  else if (width <= 16)
+    bwidth= 2;
+  else
+    bwidth= 4;
+  alloc_size= size * sizeof(t_mem);
+  array= (t_mem *)malloc(alloc_size);
   init_value= initial;
   array_is_mine= true;
 }
@@ -1828,9 +1929,18 @@
 cl_memory_chip::cl_memory_chip(const char *id,
 			       int asize,
 			       int awidth,
-			       t_mem *aarray):
-  cl_memory(id, asize, awidth)
+			       void *aarray, int arrsize):
+  cl_chip_data(id, asize, awidth)
 {
+if (awidth > 32)
+    width= 32;
+  if (width <= 8)
+    bwidth= 1;
+  else if (width <= 16)
+    bwidth= 2;
+  else
+    bwidth= 4;
+  alloc_size= arrsize;
   array= aarray;
   init_value= 0;
   array_is_mine= false;
@@ -1847,7 +1957,7 @@
 cl_memory_chip::init(void)
 {
   cl_memory::init();
-  int i;
+  t_addr i;
   if (array_is_mine)
     {
       for (i= 0; i < size; i++)
@@ -1859,25 +1969,35 @@
 }
 
 
-t_mem *
+void *
 cl_memory_chip::get_slot(t_addr addr)
 {
+  u8_t *a= (u8_t*)array;
   if (!array ||
       size <= addr)
     return(0);
-  return(&array[addr]);
+  return(a+(addr*bwidth));
 }
 
 t_addr
-cl_memory_chip::is_slot(t_mem *data_ptr)
+cl_memory_chip::is_slot(/*t_mem*/void *data_ptr)
 {
-  if (data_ptr < &(array[0]))
+  u8_t *p= (u8_t *)data_ptr;
+  u8_t *a= (u8_t *)array;
+  if (p < &(a[0]))
     return -1;
-  if (data_ptr > &(array[size-1]))
+  if (p > &(a[alloc_size-1]))
     return -2;
-  return data_ptr - &(array[0]);
+  t_addr i= p - a;
+  if (width <= 8)
+    return i;
+  if (width <= 16)
+    return i/2;
+  if (width <= 32)
+    return i/4;
+  return i;
 }
-
+/*
 t_mem
 cl_memory_chip::get(t_addr addr)
 {
@@ -1886,7 +2006,8 @@
     return(0);
   return(array[addr]);
 }
-
+*/
+/*
 void
 cl_memory_chip::set(t_addr addr, t_mem val)
 {
@@ -1895,39 +2016,133 @@
     return;
   array[addr]= val & data_mask;
 }
+*/
+void
+cl_memory_chip::print_info(const char *pre, class cl_console_base *con)
+{
+  if (!hidden)
+    {
+      //con->dd_printf(pre0);
+      con->dd_printf("%s0x%06x-0x%06x %8d %s (%d,%s,%s)\n", pre,
+		     AU(get_start_address()),
+		     AU(highest_valid_address()),
+		     AU(get_size()),
+		     get_name(),
+		     width, data_format, addr_format);
+    }
+}
+
+
+// Chip with 1 byte slots
+
+cl_chip8::cl_chip8(const char *id, int asize, int awidth, int initial):
+  cl_memory_chip(id, asize, awidth, initial)
+{}
+
+cl_chip8::cl_chip8(const char *id, int asize, int awidth, void *aarray, int arrsize):
+  cl_memory_chip(id, asize, awidth, aarray, arrsize)
+{}
+
+t_mem
+cl_chip8::d(t_addr addr)
+{
+  if (!array ||
+      size <= addr)
+    return 0;
+  return (((u8_t*)array)[addr]) & data_mask;
+}
 
 void
-cl_memory_chip::set_bit1(t_addr addr, t_mem bits)
+cl_chip8::d(t_addr addr, t_mem v)
 {
   if (!array ||
       size <= addr)
     return;
-  array[addr]|= (bits & data_mask);
+  v&= data_mask;
+  ((u8_t*)array)[addr]= v;
+}
+
+
+// Chip with 2 byte slots
+
+cl_chip16::cl_chip16(const char *id, int asize, int awidth, int initial):
+  cl_memory_chip(id, asize, awidth, initial)
+{}
+
+cl_chip16::cl_chip16(const char *id, int asize, int awidth, void *aarray, int arrsize):
+  cl_memory_chip(id, asize, awidth, aarray, arrsize)
+{}
+
+t_mem
+cl_chip16::d(t_addr addr)
+{
+  if (!array ||
+      size <= addr)
+    return 0;
+  return (((u16_t*)array)[addr]) & data_mask;
 }
 
 void
-cl_memory_chip::set_bit0(t_addr addr, t_mem bits)
+cl_chip16::d(t_addr addr, t_mem v)
 {
   if (!array ||
       size <= addr)
     return;
-  array[addr]&= ((~bits) & data_mask);
+  v&= data_mask;
+  ((u16_t*)array)[addr]= v;
+}
+
+
+// Chip with 4 byte slots
+
+cl_chip32::cl_chip32(const char *id, int asize, int awidth, int initial):
+  cl_memory_chip(id, asize, awidth, initial)
+{}
+
+cl_chip32::cl_chip32(const char *id, int asize, int awidth, void *aarray, int arrsize):
+  cl_memory_chip(id, asize, awidth, aarray, arrsize)
+{}
+
+t_mem
+cl_chip32::d(t_addr addr)
+{
+  if (!array ||
+      size <= addr)
+    return 0;
+  return (((u32_t*)array)[addr]) & data_mask;
 }
 
 void
-cl_memory_chip::print_info(chars pre, class cl_console_base *con)
+cl_chip32::d(t_addr addr, t_mem v)
 {
-  char *n= (char*)(get_name());
-  if (!hidden)
-    {
-      //con->dd_printf(pre0);
-      con->dd_printf("%s0x%06x-0x%06x %8d %s (%d,%s,%s)\n", (char*)pre,
-		     AU(get_start_address()),
-		     AU(highest_valid_address()),
-		     AU(get_size()),
-		     n,
-		     width, data_format, addr_format);
-    }
+  if (!array ||
+      size <= addr)
+    return;
+  v&= data_mask;
+  ((u32_t*)array)[addr]= v;
+}
+
+class cl_memory_chip *
+new_chip(const char *id, int asize, int awidth, int initial)
+{
+  class cl_memory_chip *c= 0;
+  
+  if (awidth < 1)
+    awidth= 1;
+  if (awidth > 32)
+    awidth= 32;
+
+  if (awidth <= 8)
+    c= new cl_chip8(id, asize, awidth, initial);
+  else if (awidth <= 16)
+    c= new cl_chip16(id, asize, awidth, initial);
+  else
+    c= new cl_chip32(id, asize, awidth, initial);
+
+  if (c)
+    c->init();
+
+  return c;
 }
 
 
@@ -2144,7 +2359,7 @@
 }
 
 void
-cl_address_decoder::print_info(chars pre, class cl_console_base *con)
+cl_address_decoder::print_info(const char *pre, class cl_console_base *con)
 {
   if (address_space &&
       address_space->hidden)
@@ -2371,7 +2586,7 @@
 {
   int b= actual_bank();
   t_addr i, s;
-  t_mem *data;
+  void *data;
   class cl_memory_cell *c;
 
   if (b == bank)
@@ -2396,7 +2611,7 @@
 {
   int b= bank_nr;//actual_bank();
   t_addr i, s;
-  t_mem *data;
+  void *data;
   class cl_memory_cell *c;
 
   if (b == bank)
@@ -2417,7 +2632,7 @@
 }
 
 void
-cl_banker::print_info(chars pre, class cl_console_base *con)
+cl_banker::print_info(const char *pre, class cl_console_base *con)
 {
   int b;
   con->dd_printf(pre);
@@ -2501,7 +2716,7 @@
 	  b= 0;
 	  m= 1;
 	}
-      t_mem *slot= memchip->get_slot(ca);
+      void *slot= memchip->get_slot(ca);
       cl_memory_cell *c= address_space->get_cell(asa);
       c->decode(slot, m);
       b++;
@@ -2511,7 +2726,7 @@
 }
 
 void
-cl_bander::print_info(chars pre, class cl_console_base *con)
+cl_bander::print_info(const char *pre, class cl_console_base *con)
 {
   if (address_space &&
       address_space->hidden)
@@ -2552,10 +2767,10 @@
   by_chip= bychip;
 }
 
-void *
-cl_decoder_list::key_of(void *item)
+const void *
+cl_decoder_list::key_of(const void *item) const
 {
-  class cl_address_decoder *d= (class cl_address_decoder *)item;
+  const class cl_address_decoder *d= (const class cl_address_decoder *)item;
   if (by_chip)
     return(&(d->chip_begin));
   else
@@ -2563,14 +2778,16 @@
 }
 
 int
-cl_decoder_list::compare(void *key1, void *key2)
+cl_decoder_list::compare(const void *key1, const void *key2)
 {
-  t_addr k1= *((t_addr*)key1), k2= *((t_addr*)key2);
+  t_addr k1= *(const t_addr *)key1;
+  t_addr k2= *(const t_addr *)key2;
+
   if (k1 == k2)
     return(0);
-  else if (k1 > k2)
-    return(1);
-  return(-1);
+  else if (k1 < k2)
+    return(-1);
+  return(1);
 }
 
 
@@ -2599,10 +2816,9 @@
 void
 cl_error_mem_invalid_address::print(class cl_commander_base *c)
 {
-  //FILE *f= c->get_fout();
-  /*cmd_fprintf(f,*/c->dd_printf("%s: invalid address ", get_type_name());
-  /*cmd_fprintf(f,*/c->dd_printf(mem->addr_format, addr);
-  /*cmd_fprintf(f,*/c->dd_printf(" in memory %s.\n", mem->get_name());
+  c->dd_printf("%s: invalid address ", get_type_name());
+  c->dd_printf(mem->addr_format, addr);
+  c->dd_printf(" in memory %s.\n", mem->get_name());
 }
 
 /* Non-decoded address space access */
@@ -2617,10 +2833,9 @@
 void
 cl_error_mem_non_decoded::print(class cl_commander_base *c)
 {
-  //FILE *f= c->get_fout();
-  /*cmd_fprintf(f,*/c->dd_printf("%s: access of non-decoded address ", get_type_name());
-  /*cmd_fprintf(f,*/c->dd_printf(mem->addr_format, addr);
-  /*cmd_fprintf(f,*/c->dd_printf(" in memory %s.\n", mem->get_name());
+  c->dd_printf("%s: access of non-decoded address ", get_type_name());
+  c->dd_printf(mem->addr_format, addr);
+  c->dd_printf(" in memory %s.\n", mem->get_name());
 }
 
 cl_mem_error_registry::cl_mem_error_registry(void)
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/sim.src/memcl.h sdcc-4.2.0+dfsg/sim/ucsim/sim.src/memcl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/sim.src/memcl.h	2019-07-02 08:44:01.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/sim.src/memcl.h	2022-01-15 17:47:32.000000000 +0000
@@ -45,31 +45,12 @@
 // Cell flags
 enum cell_flag {
   CELL_NONE		= 0x00,
-  CELL_VAR		= 0x01, /* At least one variable points to it */
   CELL_INST		= 0x04,	/* Marked as instruction */
   CELL_FETCH_BRK	= 0x08,	/* Fetch breakpoint */
   CELL_READ_ONLY	= 0x10, /* Cell is readonly */
   CELL_NON_DECODED	= 0x40	/* Cell is not decoded (yet) */
 };
 
-enum dump_format {
-  // main formats
-  df_format	= 0x000f,
-  df_hex	= 0x0001,
-  df_string	= 0x0002,
-  df_ihex	= 0x0003,
-  df_binary	= 0x0004,
-  // modifiers
-  df_data_size	= 0x00f0,
-  df_1		= 0x0010,
-  df_2		= 0x0020,
-  df_4		= 0x0040,
-  df_8		= 0x0080,
-  // endianes
-  df_endian	= 0x0100,
-  df_little	= 0x0000,
-  df_big	= 0x0100,
-};
 
 #define CELL_GENERAL	(CELL_NORMAL|CELL_INST|CELL_FETCH_BRK)
 
@@ -80,6 +61,8 @@
 
 class cl_memory: public cl_base
 {
+private:
+  unsigned int uid;
 public:
   t_addr start_address;
 protected:
@@ -99,6 +82,7 @@
 
   t_addr get_start_address(void) { return(start_address); }
   t_addr get_size(void) { return(size); }
+  unsigned int get_uid() { return uid; }
   virtual void set_uc(class cl_uc *auc) { uc= auc; }
   virtual bool valid_address(t_addr addr);
   virtual t_addr inc_address(t_addr addr, int val);
@@ -111,14 +95,18 @@
   virtual void err_inv_addr(t_addr addr);
   virtual void err_non_decoded(t_addr addr);
 
-  virtual t_addr dump(t_addr start, t_addr stop, int bpl, /*class cl_f *f*/class cl_console_base *con);
-  virtual t_addr dump_s(t_addr start, t_addr stop, int bpl, /*class cl_f *f*/class cl_console_base *con);
-  virtual t_addr dump_b(t_addr start, t_addr stop, int bpl, /*class cl_f *f*/class cl_console_base *con);
-  virtual t_addr dump_i(t_addr start, t_addr stop, int bpl, /*class cl_f *f*/class cl_console_base *con);
-  virtual t_addr dump(/*class cl_f *f*/class cl_console_base *con);
-  virtual t_addr dump(enum dump_format fmt,
-		      t_addr start, t_addr stop, int bpl,
-		      /*class cl_f *f*/class cl_console_base *con);
+  virtual t_addr dump(int smart, t_addr start, t_addr stop, int bitnr_high, int bitnr_low, int bpl, class cl_console_base *con);
+  virtual t_addr dump(int smart, t_addr start, t_addr stop, int bpl, class cl_console_base *con) {
+    return dump(smart, start, stop, -1, -1, bpl, con);
+  }
+  virtual t_addr dump(t_addr addr, int bitnr_high, int bitnr_low, class cl_console_base *con) {
+    return dump(2, addr, addr, bitnr_high, bitnr_low, -1, con);
+  }
+  virtual t_addr dump_s(t_addr start, t_addr stop, int bpl, class cl_console_base *con);
+  virtual t_addr dump_b(t_addr start, t_addr stop, int bpl, class cl_console_base *con);
+  virtual t_addr dump_i(t_addr start, t_addr stop, int bpl, class cl_console_base *con);
+  virtual t_addr dump(t_addr start, t_addr stop, int bpl, class cl_console_base *con) { return dump(1, start, stop, bpl, con); }
+  //virtual t_addr dump(class cl_console_base *con) { return(dump(df_smart, -1, -1, -1, con)); }
   virtual bool search_next(bool case_sensitive,
 			   t_mem *array, int len, t_addr *addr);
 
@@ -129,12 +117,12 @@
   virtual t_mem read(t_addr addr)=0;
   virtual t_mem read(t_addr addr, enum hw_cath skip)=0;
   virtual t_mem get(t_addr addr)=0;
+  //virtual t_mem get8(t_addr addr)=0;
+  //virtual t_mem get16(t_addr addr)=0;
   virtual t_mem write(t_addr addr, t_mem val)=0;
   virtual void set(t_addr addr, t_mem val)=0;
-  virtual void set_bit1(t_addr addr, t_mem bits)=0;
-  virtual void set_bit0(t_addr addr, t_mem bits)=0;
 
-  virtual void print_info(chars pre, class cl_console_base *con);
+  virtual void print_info(const char *pre, class cl_console_base *con);
 };
 
 
@@ -146,8 +134,7 @@
 
 class cl_memory_operator: public cl_base
 {
-protected:
-  //t_addr address;
+public:
   t_mem mask;
   class cl_memory_operator *next_operator;
   class cl_memory_cell *cell;
@@ -172,7 +159,7 @@
  protected:
   class cl_banker *banker;
  public:
-  cl_bank_switcher_operator(class cl_memory_cell *acell/*, t_addr addr*/,
+  cl_bank_switcher_operator(class cl_memory_cell *acell,
 			    class cl_banker *the_banker);
   
   virtual t_mem write(t_mem val);
@@ -184,8 +171,8 @@
 protected:
   class cl_hw *hw;
 public:
-  cl_hw_operator(class cl_memory_cell *acell/*, t_addr addr*/,
-		 /*t_mem *data_place, t_mem the_mask,*/ class cl_hw *ahw);
+  cl_hw_operator(class cl_memory_cell *acell,
+		 class cl_hw *ahw);
 
   virtual bool match(class cl_hw *the_hw) { return(hw == the_hw); }
 
@@ -200,9 +187,9 @@
   class cl_uc *uc;
   class cl_brk *bp;
 public:
- cl_event_break_operator(class cl_memory_cell *acell/*, t_addr addr*/,
+  cl_event_break_operator(class cl_memory_cell *acell,
 			  class cl_uc *auc, class cl_brk *the_bp):
-  cl_memory_operator(acell/*, addr*/)
+  cl_memory_operator(acell)
   {
     uc= auc;
     bp= the_bp;
@@ -214,7 +201,7 @@
 class cl_write_operator: public cl_event_break_operator
 {
 public:
-  cl_write_operator(class cl_memory_cell *acell/*, t_addr addr*/,
+  cl_write_operator(class cl_memory_cell *acell,
 		    class cl_uc *auc, class cl_brk *the_bp);
 
   virtual t_mem write(t_mem val);
@@ -223,7 +210,7 @@
 class cl_read_operator: public cl_event_break_operator
 {
 public:
-  cl_read_operator(class cl_memory_cell *acell/*, t_addr addr*/,
+  cl_read_operator(class cl_memory_cell *acell,
 		   class cl_uc *auc, class cl_brk *the_bp);
 
   virtual t_mem read(void);
@@ -237,10 +224,10 @@
 class cl_cell_data: public cl_abs_base
 {
  protected:
-  t_mem *data;
-  virtual t_mem d();
-  virtual void d(t_mem v);
-  virtual void dl(t_mem v);
+  /*t_mem*/void *data;
+  virtual t_mem d()=0;
+  virtual void d(t_mem v)=0;
+  virtual void dl(t_mem v) { d(v); };
 };
 
 class cl_memory_cell: public cl_cell_data
@@ -254,46 +241,41 @@
   t_mem def_data;
  protected:
   uchar width;
-  /*TYPE_UBYTE*/uchar flags;
+  uchar flags;
   class cl_memory_operator *operators;
  public:
+  cl_memory_cell();
   cl_memory_cell(uchar awidth);
   virtual ~cl_memory_cell(void);
   virtual int init(void);
-
-  virtual t_mem *get_data(void) { return(data); }
+  virtual void set_width(uchar awidth);
+  
+  virtual /*t_mem*/void *get_data(void) { return(data); }
   virtual t_mem get_mask(void) { return(mask); }
   virtual void set_mask(t_mem m) { mask= m; }
-  virtual /*TYPE_UBYTE*/uchar get_flags(void);
+  virtual uchar get_flags(void);
   virtual bool get_flag(enum cell_flag flag);
-  virtual void set_flags(/*TYPE_UBYTE*/uchar what);
+  virtual void set_flags(uchar what);
   virtual void set_flag(enum cell_flag flag, bool val);
   virtual uchar get_width(void) { return width; }
   
   virtual void un_decode(void);
   virtual void decode(class cl_memory_chip *chip, t_addr addr);
-  virtual void decode(t_mem *data_ptr);
-  virtual void decode(t_mem *data_ptr, t_mem bit_mask);
+  virtual void decode(void *data_ptr);
+  virtual void decode(void *data_ptr, t_mem bit_mask);
   
   virtual t_mem read(void);
+  virtual t_mem R(void) { return read(); }
   virtual t_mem read(enum hw_cath skip);
   virtual t_mem get(void);
   virtual t_mem write(t_mem val);
+  virtual t_mem W(t_mem val) { return write(val); }
   virtual t_mem set(t_mem val);
   virtual t_mem download(t_mem val);
   
-  virtual t_mem add(long what);
-  virtual t_mem wadd(long what);
-
-  virtual void set_bit1(t_mem bits);
-  virtual void write_bit1(t_mem bits);
-  virtual void set_bit0(t_mem bits);
-  virtual void write_bit0(t_mem bits);
-  virtual void toggle_bits(t_mem bits);
-  virtual void wtoggle_bits(t_mem bits);
-  
   virtual void append_operator(class cl_memory_operator *op);
   virtual void prepend_operator(class cl_memory_operator *op);
+  virtual void remove_operator(class cl_memory_operator *op);
   virtual void del_operator(class cl_brk *brk);
   virtual void del_operator(class cl_hw *hw);
   virtual class cl_banker *get_banker(void);
@@ -302,56 +284,109 @@
   virtual void remove_hw(class cl_hw *hw);
   virtual class cl_event_handler *get_event_handler(void);
 
-  virtual void print_info(chars pre, class cl_console_base *con);
-  virtual void print_operators(cchars pre, class cl_console_base *con);
+  virtual void print_info(const char *pre, class cl_console_base *con);
+  virtual void print_operators(const char *pre, class cl_console_base *con);
 };
 
+/*
 class cl_bit_cell: public cl_memory_cell
 {
  public:
- cl_bit_cell(uchar awidth): cl_memory_cell(awidth) {}
+  cl_bit_cell(uchar awidth): cl_memory_cell(awidth) {}
   virtual t_mem d();
   virtual void d(t_mem v);
 };
+*/
+
+/* Cell for 1 byte storage */
 
 class cl_cell8: public cl_memory_cell
 {
  public:
- cl_cell8(uchar awidth): cl_memory_cell(awidth) {}
+  cl_cell8(uchar awidth): cl_memory_cell(awidth) {}
+  cl_cell8(): cl_memory_cell(8) {}
   virtual t_mem d();
   virtual void d(t_mem v);
+  virtual void dl(t_mem v);
 };
 
 class cl_bit_cell8: public cl_memory_cell
 {
  public:
- cl_bit_cell8(uchar awidth): cl_memory_cell(awidth) {}
+  cl_bit_cell8(uchar awidth): cl_memory_cell(awidth) {}
+  cl_bit_cell8(): cl_memory_cell(8) {}
   virtual t_mem d();
   virtual void d(t_mem v);
 };
 
+
+/* Cell for 2 byte storage */
+
 class cl_cell16: public cl_memory_cell
 {
  public:
- cl_cell16(uchar awidth): cl_memory_cell(awidth) {}
+  cl_cell16(uchar awidth): cl_memory_cell(awidth) {}
+  cl_cell16(): cl_memory_cell(16) {}
   virtual t_mem d();
   virtual void d(t_mem v);
+  virtual void dl(t_mem v);
 };
 
 class cl_bit_cell16: public cl_memory_cell
 {
  public:
- cl_bit_cell16(uchar awidth): cl_memory_cell(awidth) {}
+  cl_bit_cell16(uchar awidth): cl_memory_cell(awidth) {}
   virtual t_mem d();
   virtual void d(t_mem v);
 };
 
 
+/* Cell for 4 byte storage */
+
+class cl_cell32: public cl_memory_cell
+{
+ public:
+  cl_cell32(uchar awidth): cl_memory_cell(awidth) {}
+  cl_cell32(): cl_memory_cell(32) {}
+  virtual t_mem d();
+  virtual void d(t_mem v);
+  virtual void dl(t_mem v);
+};
+
+class cl_mc32: public cl_cell32
+{
+public:
+  cl_mc32(uchar awidth): cl_cell32(awidth)
+  {
+    data= &def_data;
+    flags&= ~CELL_NON_DECODED;
+  }
+  cl_mc32(): cl_cell32(32)
+  {
+    data= &def_data;
+    flags&= ~CELL_NON_DECODED;
+  }
+};
+
+class cl_bit_cell32: public cl_memory_cell
+{
+ public:
+  cl_bit_cell32(uchar awidth): cl_memory_cell(awidth) {}
+  virtual t_mem d();
+  virtual void d(t_mem v);
+};
+
+
+/* Dummy cell */
+
 class cl_dummy_cell: public cl_memory_cell
 {
 public:
+  cl_dummy_cell(): cl_memory_cell() {}
   cl_dummy_cell(uchar awidth): cl_memory_cell(awidth) {}
 
+  virtual t_mem d();
+  virtual void d(t_mem v);
   virtual t_mem write(t_mem val);
   virtual t_mem set(t_mem val);
 };
@@ -374,20 +409,20 @@
  public:
   cl_address_space(const char *id, t_addr astart, t_addr asize, int awidth);
   virtual ~cl_address_space(void);
-
+  virtual int init(void);
+  virtual class cl_memory_cell *cell_template();
+  
   virtual bool is_address_space(void) { return(true); }
 
   virtual t_mem read(t_addr addr);
   virtual t_mem read(t_addr addr, enum hw_cath skip);
   virtual t_mem get(t_addr addr);
+  //virtual t_mem get8(t_addr addr) { return get(addr)&0xff; }
+  //virtual t_mem get16(t_addr addr) { return get(addr)&0xffff; }
   virtual t_mem write(t_addr addr, t_mem val);
   virtual void set(t_addr addr, t_mem val);
   virtual void download(t_addr, t_mem val);
   
-  virtual t_mem wadd(t_addr addr, long what);
-  virtual void set_bit1(t_addr addr, t_mem bits);
-  virtual void set_bit0(t_addr addr, t_mem bits);
-  
   virtual class cl_memory_cell *get_cell(t_addr addr);
   virtual int get_cell_flag(t_addr addr);
   virtual bool get_cell_flag(t_addr addr, enum cell_flag flag);
@@ -418,16 +453,16 @@
   virtual void set_nuof_writes(unsigned long value) {}
 #endif
 
-  virtual void print_info(chars pre, class cl_console_base *con);
+  virtual void print_info(const char *pre, class cl_console_base *con);
 };
 
-class cl_address_space_list: public cl_list
+class cl_memory_list: public cl_list
 {
 protected:
   class cl_uc *uc;
 public:
-  cl_address_space_list(class cl_uc *the_uc);
-  virtual t_index add(class cl_address_space *mem);
+  cl_memory_list(class cl_uc *the_uc, const char *name);
+  virtual t_index add(class cl_memory *mem);
 };
 
 
@@ -435,35 +470,78 @@
  * Memory chip (storage)
  */
 
-class cl_memory_chip: public cl_memory
+class cl_chip_data: public cl_memory
+{
+public:
+  cl_chip_data(const char *id, t_addr asize, int awidth);
+  virtual t_mem d(t_addr addr)= 0;
+  virtual void d(t_addr addr, t_mem v)= 0;
+};
+
+class cl_memory_chip: public cl_chip_data
 {
 protected:
-  t_mem *array;
+  void *array;
   int init_value;
   bool array_is_mine;
+  int alloc_size;
+  int bwidth; // size of array elements, in bytes
 public:
   cl_memory_chip(const char *id, int asize, int awidth, int initial= -1);
-  cl_memory_chip(const char *id, int asize, int awidth, t_mem *aarray);
+  cl_memory_chip(const char *id, int asize, int awidth, void *aarray, int arrsize);
   virtual ~cl_memory_chip(void);
   virtual int init(void);
 
   virtual bool is_chip(void) { return(true); }
 
-  virtual t_mem *get_slot(t_addr addr);
-  virtual t_addr is_slot(t_mem *data_ptr);
+  virtual void *get_slot(t_addr addr);
+  virtual t_addr is_slot(/*t_mem*/void *data_ptr);
   
-  virtual t_mem read(t_addr addr) { return(get(addr)); }
-  virtual t_mem read(t_addr addr, enum hw_cath skip) { return(get(addr)); }
-  virtual t_mem get(t_addr addr);
-  virtual t_mem write(t_addr addr, t_mem val) { set(addr, val); return(val); }
-  virtual void set(t_addr addr, t_mem val);
-  virtual void set_bit1(t_addr addr, t_mem bits);
-  virtual void set_bit0(t_addr addr, t_mem bits);
+  virtual t_mem read(t_addr addr) { return d(addr); }
+  virtual t_mem read(t_addr addr, enum hw_cath skip) { return d(addr); }
+  virtual t_mem get(t_addr addr) { return d(addr); }
+  virtual t_mem write(t_addr addr, t_mem val) { d(addr, val); return(val); }
+  virtual void set(t_addr addr, t_mem val) { d(addr, val); }
 
-  virtual void print_info(chars pre, class cl_console_base *con);
+  virtual void print_info(const char *pre, class cl_console_base *con);
 };
 
-  
+class cl_chip8: public cl_memory_chip
+{
+public:
+  cl_chip8(const char *id, int asize, int awidth, int initial= -1);
+  cl_chip8(const char *id, int asize, int awidth, void *aarray, int arrsize);
+public:
+  virtual t_mem d(t_addr addr);
+  virtual void d(t_addr addr, t_mem v);
+};
+
+class cl_chip16: public cl_memory_chip
+{
+public:
+  cl_chip16(const char *id, int asize, int awidth, int initial= -1);
+  cl_chip16(const char *id, int asize, int awidth, void *aarray, int arrsize);
+public:
+  virtual t_mem d(t_addr addr);
+  virtual void d(t_addr addr, t_mem v);
+};
+
+class cl_chip32: public cl_memory_chip
+{
+public:
+  cl_chip32(const char *id, int asize, int awidth, int initial= -1);
+  cl_chip32(const char *id, int asize, int awidth, void *aarray, int arrsize);
+public:
+  virtual t_mem d(t_addr addr);
+  virtual void d(t_addr addr, t_mem v);
+};
+
+extern class cl_memory_chip *new_chip(const char *id,
+				      int asize,
+				      int awidth,
+				      int initial= -1);
+
+
 /*
  * Address decoder
  */
@@ -486,6 +564,9 @@
 
   virtual bool activate(class cl_console_base *con);
 
+  t_addr as_to_chip(t_addr addr) { return addr - as_begin + chip_begin; }
+  t_addr chip_to_as(t_addr addr) { return addr - chip_begin + as_begin; }
+
   virtual bool fully_covered_by(t_addr begin, t_addr end);
   virtual bool is_in(t_addr begin, t_addr end);
   virtual bool covers(t_addr begin, t_addr end);
@@ -493,7 +574,7 @@
   virtual bool shrink_out_of(t_addr begin, t_addr end);
   virtual class cl_address_decoder *split(t_addr begin, t_addr end);
 
-  virtual void print_info(chars pre, class cl_console_base *con);
+  virtual void print_info(const char *pre, class cl_console_base *con);
 };
 
 
@@ -542,7 +623,7 @@
   virtual bool activate(class cl_console_base *con);
   virtual bool switch_to(int bank_nr, class cl_console_base *con);
   
-  virtual void print_info(chars pre, class cl_console_base *con);
+  virtual void print_info(const char *pre, class cl_console_base *con);
 };
 
 
@@ -567,7 +648,7 @@
   virtual bool is_bander() { return true; }
 
   virtual bool activate(class cl_console_base *con);
-  virtual void print_info(chars pre, class cl_console_base *con);
+  virtual void print_info(const char *pre, class cl_console_base *con);
 };
 
 
@@ -580,8 +661,8 @@
 public:
   cl_decoder_list(t_index alimit, t_index adelta, bool bychip);
 
-  virtual void *key_of(void *item);
-  virtual int compare(void *key1, void *key2);
+  virtual const void *key_of(const void *item) const;
+  virtual int compare(const void *key1, const void *key2);
 };
 
 
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/sim.src/obsolete.cc sdcc-4.2.0+dfsg/sim/ucsim/sim.src/obsolete.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/sim.src/obsolete.cc	2016-12-13 10:53:09.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/sim.src/obsolete.cc	2022-01-26 16:35:40.000000000 +0000
@@ -51,11 +51,11 @@
 /*cl_memloc_coll::cl_memloc_coll(void):
   cl_sorted_list(2, 2)
 {
-  Duplicates= DD_FALSE;
+  Duplicates= false;
 }*/
 
-/*void *
-cl_memloc_coll::key_of(void *item)
+/*const void *
+cl_memloc_coll::key_of(const void *item)
 {
   return(&(((class cl_memloc *)item)->address));
 }*/
@@ -217,12 +217,12 @@
   return(0);
 }
 
-char *
+const char *
 cl_mem::id_string(void)
 {
-  char *s= get_id_string(mem_ids, type);
+  const char *s= get_id_string(mem_ids, type);
 
-  return(s?s:(char*)"NONE");
+  return(s?s:"NONE");
 }
 
 t_mem
@@ -514,12 +514,12 @@
   return(0);
 }
 
-char *
+const char *
 cl_m::id_string(void)
 {
-  char *s= get_id_string(mem_ids, type);
+  const char *s= get_id_string(mem_ids, type);
 
-  return(s?s:(char*)"NONE");
+  return(s?s:"NONE");
 }
 
 /*void
@@ -728,13 +728,13 @@
     a= *addr;
   
   if (a+len > size)
-    return(DD_FALSE);
+    return(false);
 
-  found= DD_FALSE;
+  found= false;
   while (!found &&
 	 a+len <= size)
     {
-      bool match= DD_TRUE;
+      bool match= true;
       for (i= 0; i < len && match; i++)
 	{
 	  t_mem d1, d2;
@@ -834,7 +834,7 @@
       e= 'R';
       break;
     case brkNONE:
-      set_cell_flag(addr, DD_TRUE, CELL_FETCH_BRK);
+      set_cell_flag(addr, true, CELL_FETCH_BRK);
       return;
       break;
     default: e= '.'; break;	  
@@ -915,7 +915,7 @@
       e= 'R';
       break;
     case brkNONE:
-      set_cell_flag(addr, DD_FALSE, CELL_FETCH_BRK);
+      set_cell_flag(addr, false, CELL_FETCH_BRK);
       return;
       break;
     default: e= '.'; break;
@@ -1137,7 +1137,7 @@
   if (nuof_hws)
     for (i= 0; i < nuof_hws; i++)
       {
-	if ((skip & hardwares[i]->cathegory) == 0)
+	if ((skip & hardwares[i]->category) == 0)
 	  d= hardwares[i]->read(this);
 	;
       }
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/sim.src/obsolete.h sdcc-4.2.0+dfsg/sim/ucsim/sim.src/obsolete.h
--- sdcc-4.0.0+dfsg/sim/ucsim/sim.src/obsolete.h	2016-07-26 21:10:26.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/sim.src/obsolete.h	2021-10-29 17:39:15.000000000 +0000
@@ -21,13 +21,13 @@
 	 class cl_uc *auc);
   virtual ~cl_mem(void);
   virtual int init(void);
-  virtual char *id_string(void);
+  virtual const char *id_string(void);
   virtual int get_cell_flag(t_addr //addr
 			    ) { return(CELL_NORMAL); }
   virtual bool get_cell_flag(t_addr //addr
 			     , int //flag
 			     )
-  { return(DD_FALSE); }
+  { return(false); }
   virtual void set_cell_flag(t_addr addr, bool set_to, int flag) {}
 
   virtual t_mem read(t_addr addr);
@@ -108,7 +108,7 @@
   cl_m(t_addr asize, int awidth);
   virtual ~cl_m(void);
   virtual int init(void);
-  virtual char *id_string(void);
+  virtual const char *id_string(void);
 
   virtual int get_cell_flag(t_addr addr);
   virtual bool get_cell_flag(t_addr addr, int flag);
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/sim.src/port_hw.cc sdcc-4.2.0+dfsg/sim/ucsim/sim.src/port_hw.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/sim.src/port_hw.cc	2019-07-02 08:44:01.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/sim.src/port_hw.cc	2020-12-27 23:03:09.000000000 +0000
@@ -25,6 +25,7 @@
 02111-1307, USA. */
 /*@1@*/
 
+#include 
 #include 
 
 #include "globals.h"
@@ -81,7 +82,8 @@
   pd[nr].keyset  = p->keyset;
   pd[nr].basx    = p->basx;
   pd[nr].basy    = p->basy;
-
+  pd[nr].width   = p->width;
+  
   pd[nr].set_name(p->get_name());
 
   if (act_port < 0)
@@ -137,15 +139,17 @@
 	{
 	  if (pd[i].cell_p == NULL)
 	    continue;
+	  int w= //pd[i].cell_p->get_width();
+	    pd[i].width;
 	  
 	  if (pd[i].keyset != NULL)
 	    {
-	      int bit;
-	      for (bit= 0; pd[i].keyset[bit]; bit++)
-		if (pd[i].keyset[bit] == c)
+	      int bit, l= strlen(pd[i].keyset), bc= 0;
+	      for (bit= 0; (bit < l) && (bc < w) && pd[i].keyset[bit]; bit++, bc++)
+		if ((pd[i].keyset[bit]!=' ') && (pd[i].keyset[bit] == c))
 		  {
 		    t_mem m= pd[i].cell_in->read();
-		    pd[i].cell_in->write(m ^ (1<<(7-bit)));
+		    pd[i].cell_in->write(m ^ (1<<((w-1)-bit)));
 		    pio->tu_go(1,1);
 		    return true;
 		  }
@@ -159,7 +163,7 @@
   //pio->tu_cll();
   if (!ret)
     {
-      u8_t u= c;
+      //u8_t u= c;
       //fprintf(stderr, "Unknown command: %c (%d,0x%x)\n", isprint(u)?u:'?', i8, c);
     }
   return ret;
@@ -172,13 +176,17 @@
   if (!io)
     return;
 
-  int i, m;
+  int i, w;
+  t_mem m;
   bool pc= false, ic= false;
+  chars fmt= chars();
   pio->tu_hide();
   for (i= 0; i < NUOF_PORT_UIS; i++)
     {
       if (pd[i].cell_p == NULL)
 	continue;
+      //w= pd[i].cell_p->get_width();
+      w= pd[i].width;
       // name
       pio->tu_go(pd[i].basx, pd[i].basy);
       pio->dd_printf("\033[%dm", (act_port == i)?7:0);
@@ -202,7 +210,7 @@
 	  // Out
 	  pd[i].cache_p= pd[i].cell_p->get();
 	  pio->tu_go(pd[i].basx+4, pd[i].basy+1);
-	  m= 0x80;
+	  m= 1 << (w-1);
 	  for ( ; m; m>>= 1)
 	    {
 	      char v= (pd[i].cache_p&m)?'*':'-';
@@ -213,8 +221,9 @@
 		}
 	      pio->dd_printf("%c", v);		
 	    }
-	  pio->tu_go(pd[i].basx+4+8+1, pd[i].basy+1);
-	  pio->dd_printf("%02x", pd[i].cache_p);
+	  pio->tu_go(pd[i].basx+4+w+1, pd[i].basy+1);
+	  fmt.format("%%0%dx", w/4);
+	  pio->dd_printf(fmt, pd[i].cache_p);
 	  pc= true;
 	}
       if (force ||
@@ -224,11 +233,12 @@
 	  // In
 	  pd[i].cache_in= pd[i].cell_in->get();
 	  pio->tu_go(pd[i].basx+4, pd[i].basy+3);
-	  m= 0x80;
+	  m= 1 << (w-1);
 	  for ( ; m; m>>= 1)
 	    pio->dd_printf("%c", (pd[i].cache_in&m)?'*':'-');
-	  pio->tu_go(pd[i].basx+4+8+1, pd[i].basy+3);
-	  pio->dd_printf("%02x", pd[i].cache_in);
+	  pio->tu_go(pd[i].basx+4+w+1, pd[i].basy+3);
+	  fmt.format("%%0%dx", w/4);
+	  pio->dd_printf(fmt, pd[i].cache_in);
 	  ic= true;
 	}
       if (force ||
@@ -236,23 +246,25 @@
 			pd[i].cell_dir == NULL*/))
 	{
 	  // port value on "Bits" line
-	  int b, val, pval= pd[i].cache_in;
+	  int disp, b, val, pval= pd[i].cache_in;
 	  pio->tu_go(pd[i].basx+4, pd[i].basy+2);
-	  for (b= 7; b>=0; b--)
+	  for (b= w-1; b>=0; b--)
 	    {
 	      m= 1<dd_printf("\033[%dm", val?7:0);
+	      disp= b%8;
+	      pio->dd_printf("\033[%dm", val?7:0);
 		//else
 		//pio->dd_printf("\033[0m");
-	      pio->dd_printf("%d", b);
+	      pio->dd_printf("%d", disp);
 	    }
 	  if (!pd[i].cell_dir)
 	    pval&= pd[i].cache_p;
-	  pio->dd_printf("\033[0m %02x", pval);
+	  fmt.format("%%0%dx", w/4);
+	  pio->dd_printf(chars("\033[0m ")+fmt, pval);
 	}
     }
   pio->tu_show();
@@ -282,12 +294,23 @@
       pio->tu_go(pd[i].basx, pd[i].basy+1);
       pio->dd_printf("Out ");
       pio->tu_go(pd[i].basx, pd[i].basy+2);
-      pio->dd_printf("Bit 76543210");
+      pio->dd_printf("Bit ");
+      int m;
+      m= pd[i].width;
+      while (m)
+	{
+	  pio->dd_printf("%d", 7-(m%8));
+	  m--;
+	}
       pio->tu_go(pd[i].basx, pd[i].basy+3);
       pio->dd_printf("In  ");
       pio->tu_go(pd[i].basx, pd[i].basy+4);
+      pio->dd_printf("Key ");
       if (pd[i].keyset)
-	pio->dd_printf("Key %s", pd[i].keyset);
+	{
+	  for (m= 0; m < pd[i].width; m++)
+	    pio->dd_printf("%c", pd[i].keyset[m]);
+	}
 
       pd[i].cache_p= pd[i].cell_p->get();
       pd[i].cache_in= pd[i].cell_in->read();
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/sim.src/port_hwcl.h sdcc-4.2.0+dfsg/sim/ucsim/sim.src/port_hwcl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/sim.src/port_hwcl.h	2019-07-02 08:44:01.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/sim.src/port_hwcl.h	2020-10-28 18:51:38.000000000 +0000
@@ -49,8 +49,9 @@
  public:
   class cl_memory_cell *cell_p, *cell_in, *cell_dir;
   t_mem cache_p, cache_in, cache_dir, cache_value;
-  char *keyset;
-  int basx, basy;
+  const char *keyset;
+  int basx, basy, width;
+  virtual int init(void) { width=8; return 0; }
 };
 
 enum { NUOF_PORT_UIS= 16 };
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/sim.src/serial_hw.cc sdcc-4.2.0+dfsg/sim/ucsim/sim.src/serial_hw.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/sim.src/serial_hw.cc	2019-07-02 08:44:01.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/sim.src/serial_hw.cc	2022-02-08 14:54:27.000000000 +0000
@@ -31,7 +31,7 @@
 
 #include "utils.h"
 #include "globals.h"
-#include "fiocl.h"
+//#include "fiocl.h"
 
 #include "serial_hwcl.h"
 
@@ -53,6 +53,7 @@
 {
   delete serial_in_file_option;
   delete serial_out_file_option;
+  delete serial_ifirst_option;
   delete io;
 }
 
@@ -76,6 +77,11 @@
   serial_out_file_option->init();
   serial_out_file_option->use(s);
   free(s);
+  s= format_string("serial%d_ifirst", id);
+  serial_ifirst_option= new cl_optref(this);
+  serial_ifirst_option->init();
+  serial_ifirst_option->use(s);
+  free(s);
 
   s= format_string("serial%d_port", id);
   serial_port_option= new cl_optref(this);
@@ -88,7 +94,7 @@
     {
       port= serial_port_option->get_value((long)0);
       if (port < 0)
-	;
+        {}
     }
   if (port > 0)
     {
@@ -110,7 +116,7 @@
     {
       port= serial_iport_option->get_value((long)0);
       if (port < 0)
-	;
+        {}
     }
   if (port > 0)
     {
@@ -132,7 +138,7 @@
     {
       port= serial_oport_option->get_value((long)0);
       if (port < 0)
-	;
+        {}
     }
   if (port > 0)
     {
@@ -142,34 +148,67 @@
       c->add_console(listener);
     }
 
-  char *f_serial_in = (char*)serial_in_file_option->get_value((char*)0);
-  char *f_serial_out= (char*)serial_out_file_option->get_value((char*)0);
+  const char *f_serial_in = serial_in_file_option->get_value("");
+  const char *f_serial_out= serial_out_file_option->get_value("");
+  bool ifirst= false;
+  ifirst= serial_ifirst_option->get_value(ifirst);
   class cl_f *fi, *fo;
-  if (f_serial_in)
+
+  if (ifirst)
     {
-      if (f_serial_in[0] == '\001')
-	fi= (class cl_f *)(strtoll(&f_serial_in[1], 0, 0));
+      if (f_serial_in && *f_serial_in)
+	{
+	  if (f_serial_in[0] == '\001')
+	    fi= (class cl_f *)(strtoll(&f_serial_in[1], 0, 0));
+	  else
+	    fi= mk_io(f_serial_in, "r");
+	  if (!fi->tty)
+	    fprintf(stderr, "Warning: serial input interface connected to a "
+		    "non-terminal file.\n");
+	}
       else
-	fi= mk_io(chars(f_serial_in), cchars("r"));
-      if (!fi->tty)
-	fprintf(stderr, "Warning: serial input interface connected to a "
-		"non-terminal file.\n");
+	fi= 0;//mk_io(chars(""), chars(""));
+      if (f_serial_out && *f_serial_out)
+	{
+	  if (f_serial_out[0] == '\001')
+	    fo= (class cl_f *)(strtoll(&f_serial_out[1], 0, 0));
+	  else
+	    fo= mk_io(chars(f_serial_out), "w");
+	  if (!fo->tty)
+	    fprintf(stderr, "Warning: serial output interface connected to a "
+		    "non-terminal file.\n");
+	}
+      else
+	fo= 0;//mk_io(chars(""), chars(""));
     }
   else
-    fi= 0;//mk_io(chars(""), chars(""));
-  if (f_serial_out)
     {
-      if (f_serial_out[0] == '\001')
-	fo= (class cl_f *)(strtoll(&f_serial_out[1], 0, 0));
+      if (f_serial_out && *f_serial_out)
+	{
+	  if (f_serial_out[0] == '\001')
+	    fo= (class cl_f *)(strtoll(&f_serial_out[1], 0, 0));
+	  else
+	    fo= mk_io(chars(f_serial_out), "w");
+	  if (!fo->tty)
+	    fprintf(stderr, "Warning: serial output interface connected to a "
+		    "non-terminal file.\n");
+	}
       else
-	fo= mk_io(chars(f_serial_out), "w");
-      if (!fo->tty)
-	fprintf(stderr, "Warning: serial output interface connected to a "
-		"non-terminal file.\n");
+	fo= 0;//mk_io(chars(""), chars(""));
+      if (f_serial_in && *f_serial_in)
+	{
+	  if (f_serial_in[0] == '\001')
+	    fi= (class cl_f *)(strtoll(&f_serial_in[1], 0, 0));
+	  else
+	    fi= mk_io(f_serial_in, "r");
+	  if (!fi->tty)
+	    fprintf(stderr, "Warning: serial input interface connected to a "
+		    "non-terminal file.\n");
+	}
+      else
+	fi= 0;//mk_io(chars(""), chars(""));
     }
-  else
-    fo= 0;//mk_io(chars(""), chars(""));
-
+  
   io->replace_files(true, fi, fo);
   
   if (fi)
@@ -185,56 +224,39 @@
   cfg_set(serconf_check_often, false);
   cfg_set(serconf_escape, 'x'-'a'+1);
 
-  cl_var *v;
-  chars pn(id_string);
-  pn.append("%d_", id);
-  uc->vars->add(v= new cl_var(pn+chars("on"), cfg, serconf_on,
-			      cfg_help(serconf_on)));
-  v->init();
-  uc->vars->add(v= new cl_var(pn+chars("check_often"), cfg, serconf_check_often,
-			      cfg_help(serconf_check_often)));
-  v->init();
-  uc->vars->add(v= new cl_var(pn+chars("esc_char"), cfg, serconf_escape,
-			      cfg_help(serconf_escape)));
-  v->init();
-
-  uc->vars->add(v= new cl_var(pn+chars("received_char"), cfg, serconf_received,
-			      cfg_help(serconf_received)));
-  v->init();
-		
-  uc->vars->add(v= new cl_var(pn+chars("flowctrl"), cfg, serconf_flowctrl,
-			      cfg_help(serconf_flowctrl)));
-  v->init();
-
-  uc->vars->add(v= new cl_var(pn+chars("able_receive"), cfg, serconf_able_receive,
-			      cfg_help(serconf_able_receive)));
-  v->init();
+  chars pn("", "%s%d_", id_string, id);
+  uc->vars->add(pn+"on", cfg, serconf_on, cfg_help(serconf_on));
+  uc->vars->add(pn+"check_often", cfg, serconf_check_often, cfg_help(serconf_check_often));
+  uc->vars->add(pn+"esc_char", cfg, serconf_escape, cfg_help(serconf_escape));
+  uc->vars->add(pn+"received_char", cfg, serconf_received, cfg_help(serconf_received));
+  uc->vars->add(pn+"flowctrl", cfg, serconf_flowctrl, cfg_help(serconf_flowctrl));
+  uc->vars->add(pn+"able_receive", cfg, serconf_able_receive, cfg_help(serconf_able_receive));
 
   cfg_set(serconf_able_receive, 1);
   return 0;
 }
 
-char *
+const char *
 cl_serial_hw::cfg_help(t_addr addr)
 {
   switch (addr)
     {
     case serconf_on:
-      return (char*)"Turn simulation of UART on or off (bool, RW)";
+      return "Turn simulation of UART on or off (bool, RW)";
     case serconf_check_often:
-      return (char*)"Check input file at every cycle (bool, RW)";
+      return "Check input file at every cycle (bool, RW)";
     case serconf_escape:
-      return (char*)"Escape char on display (int, RW)";
+      return "Escape char on display (int, RW)";
     case serconf_common:
-      return (char*)"Not used";
+      return "Not used";
     case serconf_received:
-      return (char*)"Received char written by simulator (int, R)";
+      return "Received char written by simulator (int, R)";
     case serconf_flowctrl:
-      return (char*)"Flow-control simulation on/off (bool, RW)";
+      return "Flow-control simulation on/off (bool, RW)";
     case serconf_able_receive:
-      return (char*)"UART enabled to receive by flow-control (bool, RW)";
+      return "UART enabled to receive by flow-control (bool, RW)";
     }
-  return (char*)"Not used";
+  return "Not used";
 }
 
 t_mem
@@ -387,7 +409,7 @@
 		  if (run && !input_avail)
 		    {
 		      input= esc, input_avail= true;
-		      io->dd_printf("^%c enterted.\n", 'a'+esc-1);
+		      io->dd_printf("^%c entered.\n", 'a'+esc-1);
 		    }
 		  else
 		    io->dd_printf("Control menu exited.\n");
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/sim.src/serial_hwcl.h sdcc-4.2.0+dfsg/sim/ucsim/sim.src/serial_hwcl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/sim.src/serial_hwcl.h	2019-04-02 10:46:33.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/sim.src/serial_hwcl.h	2022-02-08 14:54:27.000000000 +0000
@@ -63,6 +63,7 @@
   class cl_optref *serial_port_option;
   class cl_optref *serial_iport_option;
   class cl_optref *serial_oport_option;
+  class cl_optref *serial_ifirst_option;
   class cl_serial_listener *listener;
   //class cl_hw_io *io;
   char input;
@@ -72,8 +73,8 @@
   cl_serial_hw(class cl_uc *auc, int aid, chars aid_string);
   virtual ~cl_serial_hw(void);
   virtual int init(void);
-  virtual int cfg_size(void) { return serconf_nr; }
-  virtual char *cfg_help(t_addr addr);
+  virtual unsigned int cfg_size(void) { return serconf_nr; }
+  virtual const char *cfg_help(t_addr addr);
   
   virtual t_mem conf_op(cl_memory_cell *cell, t_addr addr, t_mem *val);
 
@@ -81,6 +82,7 @@
   virtual void new_io(class cl_f *f_in, class cl_f *f_out);
   virtual bool proc_input(void);
   virtual void refresh_display(bool force) {}
+  virtual void draw_state_time(bool force) {}
   virtual void draw_display(void) {}
 
   virtual void reset(void);
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/sim.src/sim.cc sdcc-4.2.0+dfsg/sim/ucsim/sim.src/sim.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/sim.src/sim.cc	2019-07-02 08:44:01.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/sim.src/sim.cc	2022-01-18 21:40:45.000000000 +0000
@@ -25,12 +25,13 @@
 02111-1307, USA. */
 /*@1@*/
 
-#include "ddconfig.h"
+//#include "ddconfig.h"
 
 #include 
 #include 
-#include 
-#include "i_string.h"
+//#include 
+#include 
+//#include "i_string.h"
 
 // prj
 #include "globals.h"
@@ -38,11 +39,10 @@
 
 // cmd
 #include "cmd_execcl.h"
-#include "cmd_guicl.h"
 
 // local, sim.src
-#include "simcl.h"
-#include "appcl.h"
+//#include "simcl.h"
+//#include "appcl.h"
 #include "simifcl.h"
 
 
@@ -69,7 +69,7 @@
   if (!(uc= mk_controller()))
     return(1);
   uc->init();
-  simif= uc->get_hw(cchars("simif"), 0);
+  simif= uc->get_hw("simif", 0);
   return(0);
 }
 
@@ -95,6 +95,7 @@
 	{
 	  start_at= dnow();
 	}
+      uc->save_hist();
       if (uc->do_inst(1) == resGO)
 	steps_done++;
       if ((steps_todo > 0) &&
@@ -133,7 +134,7 @@
       app->get_commander()->update_active();
     }
   if (uc)
-    start_tick= uc->ticks->ticks;
+    start_tick= uc->ticks->get_ticks();
   steps_done= 0;
   steps_todo= steps_to_do;
 }
@@ -144,6 +145,7 @@
   class cl_commander_base *cmd= app->get_commander();
   class cl_option *o= app->options->get_option("quit");
   bool q_opt= false;
+  unsigned long dt= uc?(uc->ticks->get_ticks() - start_tick):0;
 
   if (o)
     o->get_value(&q_opt);
@@ -164,27 +166,37 @@
     }
   if (b)
     {
+      class cl_option *o;
+      o= app->options->get_option("beep_break");
+      bool e= false;
+      if (o) o->get_value(&e);
+      if (e)
+	cmd->frozen_console->dd_printf("\007");
+    
       if (!(b->commands.empty()))
 	{
-	  class cl_option *o= app->options->get_option("echo_script");
-	  bool e= false;
+	  o= app->options->get_option("echo_script");
+	  e= false;
 	  if (o) o->get_value(&e);
 	  if (e)
-	    cmd->dd_printf("%s\n", (char*)(b->commands));
-		  application->exec(b->commands);
-		  steps_done= 0;
+	    cmd->dd_cprintf("answer", "%s\n", b->commands.c_str());
+	  application->exec(b->commands);
+	  steps_done= 0;
 	}
     }
   
   if (!(state & SIM_GO) &&
       cmd->frozen_console)
     {
+      fflush(stdout); // Needed to make sure we get the right simulator output order
+      
       if (reason == resUSER &&
 	  cmd->frozen_console->input_avail())
 	cmd->frozen_console->read_line();
       cmd->frozen_console->un_redirect();
       cmd->frozen_console->dd_color("debug");
-      cmd->frozen_console->dd_printf("Stop at 0x%06x: (%d) ", AU(uc->PC), reason);
+      // Stop message should start with a newline, to avoid mixing this line with previous output from simulated program
+      cmd->frozen_console->dd_printf("\nStop at 0x%06x: (%d) ", AU(uc->PC), reason);
       switch (reason)
 	{
 	case resHALT:
@@ -208,11 +220,11 @@
 	    {
 	      class cl_ev_brk *eb= (cl_ev_brk*)b;
 	      class cl_address_space *m= eb->get_mem();
-	      cmd->frozen_console->dd_printf("Event `%s' at %s[0x%x]: 0x%x %s\n",
+	      cmd->frozen_console->dd_printf("Event `%s' at %s[0x%x]: 0x%x ",
 					     eb->id, m?(m->get_name()):"mem?",
 					     AU(eb->addr),
-					     AU(uc->instPC),
-					     uc->disass(uc->instPC, " "));
+					     AU(uc->instPC));
+	      uc->print_disass(uc->instPC, cmd->frozen_console);
     	    }
 	  break;
 	case resINTERRUPT:
@@ -233,7 +245,7 @@
 	  }
          break;
 	case resSTEP:
-	  cmd->frozen_console->dd_printf("\n");
+	  cmd->frozen_console->dd_printf("stepped %ld ticks\n", dt);
 	  uc->print_regs(cmd->frozen_console);
 	  break;
 	case resERROR:
@@ -242,18 +254,27 @@
 	case resSIMIF:
 	  cmd->frozen_console->dd_printf("Program stopped itself\n");
 	  break;
+	case resSELFJUMP:
+	  cmd->frozen_console->dd_printf("Jump to itself\n");
+	  break;
+        case resNOT_DONE:
+          cmd->frozen_console->dd_printf("Instruction is still executing\n");
+          break;
 	default:
 	  cmd->frozen_console->dd_printf("Unknown reason\n");
 	  break;
 	}
-      cmd->frozen_console->dd_printf("F 0x%06x\n", AU(uc->PC)); // for sdcdb
-      unsigned long dt= uc?(uc->ticks->ticks - start_tick):0;
+      cmd->frozen_console->dd_cprintf("answer", "F 0x%06x\n", AU(uc->PC)); // for sdcdb
       if ((reason != resSTEP) ||
 	  (steps_done > 1))
-	cmd->frozen_console->dd_printf("Simulated %lu ticks in %f sec, rate=%f\n",
-				       dt,
-				       stop_at - start_at,
-				       (dt*(1/uc->xtal)) / (stop_at - start_at));
+	{
+	  cmd->frozen_console->dd_printf("Simulated %lu ticks (%.3e sec)\n",
+					 dt,
+					 dt*(1/uc->get_xtal()));
+	  cmd->frozen_console->dd_printf("Host usage: %f sec, rate=%f\n",
+					 stop_at - start_at,
+					 (dt*(1/uc->get_xtal())) / (stop_at - start_at));
+	}
       //if (cmd->actual_console != cmd->frozen_console)
       cmd->frozen_console->set_flag(CONS_FROZEN, false);
       //cmd->frozen_console->dd_printf("_s_");
@@ -265,45 +286,6 @@
     state|= SIM_QUIT;
   cmd->update_active();
 }
-/*
-void
-cl_sim::stop(class cl_ev_brk *brk)
-{
-  class cl_commander_base *cmd= app->get_commander();
-  class cl_option *o= app->options->get_option("quit");
-  bool q_opt= false;
-
-  if (o)
-    o->get_value(&q_opt);
-
-  //state&= ~SIM_GO;
-  if (simif)
-    simif->cfg_set(simif_reason, resEVENTBREAK);
-
-  if (brk)
-    {
-      if (!(brk->commands.empty()))
-	{
-	  application->exec(brk->commands);
-	  steps_done= 0;
-	  printf("event brk PC=%ld, simgo=%d\n",uc->PC,state&SIM_GO);
-	}
-    }
-
-  if (!(state & SIM_GO) &&
-      cmd->frozen_console)
-    {
-      class cl_console_base *con= cmd->frozen_console;
-      con->dd_printf("Event `%s' at %s[0x%x]: 0x%x %s\n",
-		     brk->id, brk->get_mem()->get_name(), (int)brk->addr,
-		     (int)uc->instPC,
-		     uc->disass(uc->instPC, " "));
-    }
-  if (!(state & SIM_GO) &&
-      q_opt)
-    state|= SIM_QUIT;
-}
-*/
 
 void
 cl_sim::change_run(int reason)
@@ -321,7 +303,6 @@
 cl_sim::build_cmdset(class cl_cmdset *cmdset)
 {
   class cl_cmd *cmd;
-  //class cl_cmdset *cset;
 
   cmdset->add(cmd= new cl_run_cmd("run", 0));
   cmd->init();
@@ -340,17 +321,24 @@
   cmd->init();
   cmd->add_name("n");
 
-  /*{
-    cset= new cl_cmdset();
-    cset->init();
-    cset->add(cmd= new cl_gui_start_cmd("start", 0));
-    cmd->init();
-    cset->add(cmd= new cl_gui_stop_cmd("stop", 0));
+  //class cl_super_cmd *super_cmd;
+  //class cl_cmdset *cset;
+  /*
+    {
+    // info
+    super_cmd= (class cl_super_cmd *)(cmdset->get_cmd("info"));
+    if (super_cmd)
+      cset= super_cmd->get_subcommands();
+    else {
+      cset= new cl_cmdset();
+      cset->init();
+    }
+    if (!super_cmd) {
+    cmdset->add(cmd= new cl_super_cmd("info", 0, cset));
     cmd->init();
-  }
-  cmdset->add(cmd= new cl_super_cmd("gui", 0, cset));
-  cmd->init();
-  set_gui_help();
+    set_info_help(cmd);
+    }
+    }
   */
 }
 
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/sim.src/simcl.h sdcc-4.2.0+dfsg/sim/ucsim/sim.src/simcl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/sim.src/simcl.h	2019-07-02 08:44:01.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/sim.src/simcl.h	2020-12-08 20:50:59.000000000 +0000
@@ -43,7 +43,6 @@
 #include "uccl.h"
 #include "argcl.h"
 
-
 class cl_sim: public cl_base
 {
 public:
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/sim.src/simif.cc sdcc-4.2.0+dfsg/sim/ucsim/sim.src/simif.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/sim.src/simif.cc	2019-04-02 10:46:33.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/sim.src/simif.cc	2022-01-18 21:40:45.000000000 +0000
@@ -25,16 +25,17 @@
 02111-1307, USA. */
 /*@1@*/
 
+#include 
 #include 
 #include 
 #include 
-#include "i_string.h"
+//#include "i_string.h"
 
 // prj
 #include "globals.h"
 
 // sim
-#include "simcl.h"
+//#include "simcl.h"
 
 #include "simifcl.h"
 
@@ -472,7 +473,7 @@
 cl_simulator_interface::~cl_simulator_interface(void)
 {
   if (as_name)
-    free((void*)as_name);
+    free(const_cast(as_name));
   delete commands;
 }
 
@@ -496,7 +497,7 @@
 	  (strlen(oas_v) > 0))
 	{
 	  if (as_name)
-	    free((void*)as_name);
+	    free(const_cast(as_name));
 	  as_name= strdup(oas_v);
 	  addr= oa_v;
 	}
@@ -567,79 +568,48 @@
   commands->add(c= new cl_sif_write(this));
   c->init();
 
-  cl_var *v;
-  uc->vars->add(v= new cl_var(cchars("simif_on"), cfg, simif_on,
-			      cfg_help(simif_on)));
-  v->init();
+  uc->vars->add("simif_on", cfg, simif_on, cfg_help(simif_on));
   cfg_set(simif_on, 1);
-  uc->vars->add(v= new cl_var(cchars("sim_run"), cfg, simif_run,
-			      cfg_help(simif_run)));
-  v->init();
-  uc->vars->add(v= new cl_var(cchars("sim_start"), cfg, simif_start,
-			      cfg_help(simif_start)));
-  v->init();
-  uc->vars->add(v= new cl_var(cchars("sim_stop"), cfg, simif_stop,
-			      cfg_help(simif_stop)));
-  v->init();
-  uc->vars->add(v= new cl_var(cchars("sim_quit"), cfg, simif_quit,
-			      cfg_help(simif_quit)));
-  v->init();
-  uc->vars->add(v= new cl_var(cchars("sim_reason"), cfg, simif_reason,
-			      cfg_help(simif_reason)));
-  v->init();
-  uc->vars->add(v= new cl_var(cchars("sim_xtal"), cfg, simif_xtal,
-			      cfg_help(simif_xtal)));
-  v->init();
-  uc->vars->add(v= new cl_var(cchars("sim_ticks"), cfg, simif_ticks,
-			      cfg_help(simif_ticks)));
-  v->init();
-  uc->vars->add(v= new cl_var(cchars("sim_isr_ticks"), cfg, simif_isr_ticks,
-			      cfg_help(simif_isr_ticks)));
-  v->init();
-  uc->vars->add(v= new cl_var(cchars("sim_idle_ticks"), cfg, simif_idle_ticks,
-			      cfg_help(simif_idle_ticks)));
-  v->init();
-  uc->vars->add(v= new cl_var(cchars("sim_real_time"), cfg, simif_real_time,
-			      cfg_help(simif_real_time)));
-  v->init();
-  uc->vars->add(v= new cl_var(cchars("sim_vclk"), cfg, simif_vclk,
-			      cfg_help(simif_vclk)));
-  v->init();
-  uc->vars->add(v= new cl_var(cchars("PC"), cfg, simif_pc,
-			      cfg_help(simif_pc)));
-  v->init();
-  uc->vars->add(v= new cl_var(cchars("sim_print"), cfg, simif_print,
-			      cfg_help(simif_print)));
-  v->init();
-  uc->vars->add(v= new cl_var(cchars("sim_write"), cfg, simif_write,
-			      cfg_help(simif_write)));
-  v->init();
+  uc->vars->add("sim_run", cfg, simif_run, cfg_help(simif_run));
+  uc->vars->add("sim_start", cfg, simif_start, cfg_help(simif_start));
+  uc->vars->add("sim_stop", cfg, simif_stop, cfg_help(simif_stop));
+  uc->vars->add("sim_quit", cfg, simif_quit, cfg_help(simif_quit));
+  uc->vars->add("sim_reason", cfg, simif_reason, cfg_help(simif_reason));
+  uc->vars->add("sim_xtal", cfg, simif_xtal, cfg_help(simif_xtal));
+  uc->vars->add("sim_ticks", cfg, simif_ticks, cfg_help(simif_ticks));
+  uc->vars->add("sim_isr_ticks", cfg, simif_isr_ticks, cfg_help(simif_isr_ticks));
+  uc->vars->add("sim_idle_ticks", cfg, simif_idle_ticks, cfg_help(simif_idle_ticks));
+  uc->vars->add("sim_real_time", cfg, simif_real_time, cfg_help(simif_real_time));
+  uc->vars->add("sim_vclk", cfg, simif_vclk, cfg_help(simif_vclk));
+  uc->vars->add("PC", cfg, simif_pc, cfg_help(simif_pc));
+  uc->vars->add("sim_print", cfg, simif_print, cfg_help(simif_print));
+  uc->vars->add("sim_write", cfg, simif_write, cfg_help(simif_write));
 
   return(0);
 }
 
-char *
+const char *
 cl_simulator_interface::cfg_help(t_addr addr)
 {
   switch (addr)
     {
-    case simif_on	: return (char*)"Turn simif on/off (bool, RW)";
-    case simif_run	: return (char*)"WR: sets running state, RD: check if simulation is running";
-    case simif_start	: return (char*)"WR: start simulation, RD: true if running";
-    case simif_stop	: return (char*)"WR: stop simulation, RD: true if stopped";
-    case simif_quit	: return (char*)"Quit simulator (any, WO)";
-    case simif_reason	: return (char*)"Reason of last stop (int, RO)";
-    case simif_xtal	: return (char*)"Xtal frequency in Hz (int, RW)";
-    case simif_ticks	: return (char*)"Nuof ticks simulated so far (int, RO)";
-    case simif_isr_ticks: return (char*)"Ticks spent in ISR (int, RO)";
-    case simif_idle_ticks:return (char*)"Ticks spent in idle state (int, RO)";
-    case simif_real_time: return (char*)"Real time since reset in msec (int, RO)";
-    case simif_vclk	: return (char*)"Nuof simulated virtual clocks (int, RO)";
-    case simif_pc	: return (char*)"PC register (int, RW)";
-    case simif_print	: return (char*)"Print char on stdout (int, WO)";
-    case simif_write	: return (char*)"Write char to simif output (int, WO)";
+    case simif_on	: return "Turn simif on/off (bool, RW)";
+    case simif_run	: return "WR: sets running state, RD: check if simulation is running";
+    case simif_start	: return "WR: start simulation, RD: true if running";
+    case simif_stop	: return "WR: stop simulation, RD: true if stopped";
+    case simif_quit	: return "Quit simulator (any, WO)";
+    case simif_reason	: return "Reason of last stop (int, RO)";
+    case simif_xtal	: return "Xtal frequency in Hz (int, RW)";
+    case simif_ticks	: return "Nuof ticks simulated so far (int, RO)";
+    case simif_isr_ticks: return "Ticks spent in ISR (int, RO)";
+    case simif_idle_ticks:return "Ticks spent in idle state (int, RO)";
+    case simif_real_time: return "Real time since reset in msec (int, RO)";
+    case simif_vclk	: return "Nuof simulated virtual clocks (int, RO)";
+    case simif_pc	: return "PC register (int, RW)";
+    case simif_print	: return "Print char on stdout (int, WO)";
+    case simif_write	: return "Write char to simif output (int, WO)";
     }
-  return (char*)"Not used";
+  return "Not used";
 }
 
 void
@@ -667,7 +637,7 @@
 			 AU(mem->highest_valid_address()));
 	  return;
 	}
-      as_name= strdup((char*)mem->get_name());
+      as_name= strdup(mem->get_name());
       addr= a;
       if ((as= dynamic_cast(mem)) != 0)
 	{
@@ -827,28 +797,28 @@
       break;
     case simif_xtal: // xtal frequ
       if (val)
-	uc->xtal= *val;
-      cell->set(uc->xtal);
+	uc->set_xtal(*val);
+      cell->set(uc->get_xtal());
       break;
     case simif_ticks: // tick counter
       if (val)
 	*val= cell->get();
-      cell->set(uc->ticks->ticks);
+      cell->set(uc->ticks->get_ticks());
       break;
     case simif_isr_ticks: // isr tick counter
       if (val)
 	*val= cell->get();
-      cell->set(uc->isr_ticks->ticks);
+      cell->set(uc->isr_ticks->get_ticks());
       break;
     case simif_idle_ticks: // idle tick counter
       if (val)
 	*val= cell->get();
-      cell->set(uc->idle_ticks->ticks);
+      cell->set(uc->idle_ticks->get_ticks());
       break;
     case simif_real_time: // real time in msec
       if (val)
 	*val= cell->get();
-      cell->set(uc->get_rtime() * 1000);
+      cell->set(uc->ticks->get_rtime() * 1000);
       break;
     case simif_vclk: // virtual clock
       if (val)
@@ -965,7 +935,7 @@
     con->dd_printf("%s", fout->get_file_name());
   con->dd_printf("\n");
 
-  print_cfg_info(con);
+  //print_cfg_info(con);
 }
 
 
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/sim.src/simifcl.h sdcc-4.2.0+dfsg/sim/ucsim/sim.src/simifcl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/sim.src/simifcl.h	2019-04-02 10:46:33.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/sim.src/simifcl.h	2021-10-29 17:39:15.000000000 +0000
@@ -363,8 +363,8 @@
   cl_simulator_interface(class cl_uc *auc);
   virtual ~cl_simulator_interface(void);
   virtual int init(void);
-  virtual int cfg_size(void) { return simif_nuof; }
-  virtual char *cfg_help(t_addr addr);
+  virtual unsigned int cfg_size(void) { return simif_nuof; }
+  virtual const char *cfg_help(t_addr addr);
     
   virtual void set_cmd(class cl_cmdline *cmdline, class cl_console_base *con);
   virtual t_mem read(class cl_memory_cell *cel);
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/sim.src/stack.cc sdcc-4.2.0+dfsg/sim/ucsim/sim.src/stack.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/sim.src/stack.cc	2019-04-02 10:46:33.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/sim.src/stack.cc	2020-03-27 20:18:53.000000000 +0000
@@ -25,10 +25,11 @@
 02111-1307, USA. */
 /*@1@*/
 
+#include 
 #include 
 
 // cmd.src
-#include "newcmdcl.h"
+//#include "newcmdcl.h"
 
 // sim.src
 #include "uccl.h"
@@ -432,7 +433,25 @@
 
 cl_error_stack::cl_error_stack(void)
 {
-classification = stack_error_registry.find("stack");
+  classification = stack_error_registry.find("stack");
+}
+
+/*
+ * Stack overflow error
+ */
+
+cl_error_stack_overflow::cl_error_stack_overflow(class cl_stack_op *op):
+  cl_error_stack()
+{
+  PC= op->get_pc();
+  SP_before= op->get_before();
+  SP_after= op->get_after();
+}
+
+void
+cl_error_stack_overflow::print(class cl_commander_base *c)
+{
+  c->dd_cprintf("error", "Stack overflow, PC=0x%x\n", AU(PC));
 }
 
 /* Stack Tracker Errors */
@@ -454,8 +473,9 @@
 void
 cl_error_stack_tracker_wrong_handle::print(class cl_commander_base *c)
 {
-  c->dd_printf("%s: wrong stack tracker handle called for %s operation\n",
-	       get_type_name(), write_operation?"write":"read");
+  c->dd_cprintf("error",
+		"%s: wrong stack tracker handle called for %s operation\n",
+		get_type_name(), write_operation?"write":"read");
 }
 
 /* Stack Tracker: operation on empty stack */
@@ -476,13 +496,14 @@
 void
 cl_error_stack_tracker_empty::print(class cl_commander_base *c)
 {
-  c->dd_printf("%s(0x%06x): %s on empty stack, PC="
-	       "0x06x, SP=0x%06x->0x%06x\n",
-	       get_type_name(), AU(operation->get_pc()),
-	       operation->get_op_name(),
-	       AU(operation->get_pc()),
-	       AU(operation->get_before()),
-	       AU(operation->get_after()));
+  c->dd_cprintf("error",
+		"%s(0x%06x): %s on empty stack, PC="
+		"0x06x, SP=0x%06x->0x%06x\n",
+		get_type_name(), AU(operation->get_pc()),
+		operation->get_op_name(),
+		AU(operation->get_pc()),
+		AU(operation->get_before()),
+		AU(operation->get_after()));
 }
 
 /* Stack Tracker: operation on empty stack */
@@ -517,12 +538,12 @@
 void
 cl_error_stack_tracker_unmatch::print(class cl_commander_base *c)
 {
-  c->dd_printf("%s(0x%06x): %s when %s expected, "
-	       "SP=0x%06x->0x%06x\n",
-	       get_type_name(), AU(operation->get_pc()),
-	       operation->get_op_name(), top->get_matching_name(),
-	       AU(operation->get_before()),
-	       AU(operation->get_after()));
+  c->dd_cprintf("error", "%s(0x%06x): %s when %s expected, "
+		"SP=0x%06x->0x%06x\n",
+		get_type_name(), AU(operation->get_pc()),
+		operation->get_op_name(), top->get_matching_name(),
+		AU(operation->get_before()),
+		AU(operation->get_after()));
 }
 
 /* Stack Tracker: stack is inconsistent */
@@ -544,7 +565,7 @@
 void
 cl_error_stack_tracker_inconsistent::print(class cl_commander_base *c)
 {
-  c->dd_printf("%s(0x%06x): %d byte(s) unread from the stack\n",
+  c->dd_cprintf("error",  "%s(0x%06x): %d byte(s) unread from the stack\n",
 	       get_type_name(), AU(operation->get_pc()),
 	       unread_data_size);
 }
@@ -552,12 +573,13 @@
 cl_stack_error_registry::cl_stack_error_registry(void)
 {
   class cl_error_class *prev = stack_error_registry.find("non-classified");
-  prev = register_error(new cl_error_class(err_error, "stack", prev, ERROR_OFF));
-  prev = register_error(new cl_error_class(err_error, "stack_tracker", prev));
-  prev = register_error(new cl_error_class(err_error, "stack_tracker_wrong_handle", prev));
-  prev = register_error(new cl_error_class(err_error, "operation_on_empty_stack", prev));
-  prev = register_error(new cl_error_class(err_warning, "stack_operation_unmatched_to_top_of_stack", prev));
-  prev = register_error(new cl_error_class(err_warning, "stack_looks_corrupted", prev));
+  prev = register_error(new cl_error_class(err_error, "stack", prev, ERROR_ON));
+  /*prev =*/register_error(new cl_error_class(err_error, "stack_overflow", prev));
+  //prev = register_error(new cl_error_class(err_error, "stack_tracker", prev));
+  //prev = register_error(new cl_error_class(err_error, "stack_tracker_wrong_handle", prev));
+  //prev = register_error(new cl_error_class(err_error, "operation_on_empty_stack", prev));
+  //prev = register_error(new cl_error_class(err_warning, "stack_operation_unmatched_to_top_of_stack", prev));
+  //prev = register_error(new cl_error_class(err_warning, "stack_looks_corrupted", prev));
 }
 
 
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/sim.src/stackcl.h sdcc-4.2.0+dfsg/sim/ucsim/sim.src/stackcl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/sim.src/stackcl.h	2016-07-26 21:10:26.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/sim.src/stackcl.h	2022-01-27 21:35:29.000000000 +0000
@@ -64,7 +64,7 @@
   virtual void print_info(class cl_console_base *con);
 public:
   virtual const char *get_op_name(void);
-  virtual const char *get_matching_name(void) { return(cchars("unknown")); }
+  virtual const char *get_matching_name(void) { return("unknown"); }
   virtual bool sp_increased(void);
   virtual int data_size(void);
   virtual bool match(class cl_stack_op *op);
@@ -76,7 +76,7 @@
   virtual bool can_removed(class cl_stack_op *op);
 };
 
-/* Call of a subrutine, must match with RET */
+/* Call of a subroutine, must match with RET */
 class cl_stack_call: public cl_stack_op
 {
 protected:
@@ -183,6 +183,18 @@
 };
 
 /*
+ * Stack overflow error
+ */
+class cl_error_stack_overflow: public cl_error_stack
+{
+protected:
+  t_addr PC, SP_before, SP_after;
+public:
+  cl_error_stack_overflow(class cl_stack_op *op);
+  virtual void print(class cl_commander_base *c);
+};
+  
+/*
  * All kind of stack tracker errors
  */
 class cl_error_stack_tracker: public cl_error_stack
@@ -197,7 +209,6 @@
   bool write_operation;
 public:
   cl_error_stack_tracker_wrong_handle(bool write_op);
-
   virtual void print(class cl_commander_base *c);
 };
 
@@ -208,7 +219,6 @@
 public:
   cl_error_stack_tracker_empty(class cl_stack_op *op);
   virtual ~cl_error_stack_tracker_empty(void);
-
   virtual void print(class cl_commander_base *c);
 };
 
@@ -220,7 +230,6 @@
   cl_error_stack_tracker_unmatch(class cl_stack_op *Top,
                                 class cl_stack_op *op);
   virtual ~cl_error_stack_tracker_unmatch(void);
-
   virtual void print(class cl_commander_base *c);
 };
 
@@ -233,7 +242,6 @@
   cl_error_stack_tracker_inconsistent(class cl_stack_op *op,
 				      int the_unread_data_size);
   virtual ~cl_error_stack_tracker_inconsistent(void);
-
   virtual void print(class cl_commander_base *c);
 };
 
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/sim.src/test/clean.mk sdcc-4.2.0+dfsg/sim/ucsim/sim.src/test/clean.mk
--- sdcc-4.0.0+dfsg/sim/ucsim/sim.src/test/clean.mk	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/sim.src/test/clean.mk	2021-04-01 17:52:48.000000000 +0000
@@ -0,0 +1,5 @@
+clean:
+
+distclean:
+	rm -f Makefile
+	find . -type d -name out -exec rm -rf {} \;
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/sim.src/test/legal/baseline/legal sdcc-4.2.0+dfsg/sim/ucsim/sim.src/test/legal/baseline/legal
--- sdcc-4.0.0+dfsg/sim/ucsim/sim.src/test/legal/baseline/legal	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/sim.src/test/legal/baseline/legal	2022-02-08 21:21:05.000000000 +0000
@@ -0,0 +1,285 @@
+uCsim, Copyright (C)  Daniel Drotos.
+uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+This is free software, and you are welcome to redistribute it
+under certain conditions; type `show c' for details.
+show copying
+		    GNU GENERAL PUBLIC LICENSE
+		       Version 2, June 1991
+
+ Copyright (C) 1989, 1991 Free Software Foundation, Inc.
+ 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ Everyone is permitted to copy and distribute verbatim copies
+ of this license document, but changing it is not allowed.
+
+			    Preamble
+
+  The licenses for most software are designed to take away your
+freedom to share and change it.  By contrast, the GNU General Public
+License is intended to guarantee your freedom to share and change free
+software--to make sure the software is free for all its users.  This
+General Public License applies to most of the Free Software
+Foundation's software and to any other program whose authors commit to
+using it.  (Some other Free Software Foundation software is covered by
+the GNU Library General Public License instead.)  You can apply it to
+your programs, too.
+
+  When we speak of free software, we are referring to freedom, not
+price.  Our General Public Licenses are designed to make sure that you
+have the freedom to distribute copies of free software (and charge for
+this service if you wish), that you receive source code or can get it
+if you want it, that you can change the software or use pieces of it
+in new free programs; and that you know you can do these things.
+
+  To protect your rights, we need to make restrictions that forbid
+anyone to deny you these rights or to ask you to surrender the rights.
+These restrictions translate to certain responsibilities for you if you
+distribute copies of the software, or if you modify it.
+
+  For example, if you distribute copies of such a program, whether
+gratis or for a fee, you must give the recipients all the rights that
+you have.  You must make sure that they, too, receive or can get the
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+rights.
+
+  We protect your rights with two steps: (1) copyright the software, and
+(2) offer you this license which gives you legal permission to copy,
+distribute and/or modify the software.
+
+  Also, for each author's protection and ours, we want to make certain
+that everyone understands that there is no warranty for this free
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+want its recipients to know that what they have is not the original, so
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+
+  Finally, any free program is threatened constantly by software
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+  The precise terms and conditions for copying, distribution and
+modification follow.
+
+		    GNU GENERAL PUBLIC LICENSE
+   TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION
+
+  0. This License applies to any program or other work which contains
+a notice placed by the copyright holder saying it may be distributed
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+Activities other than copying, distribution and modification are not
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+running the Program is not restricted, and the output from the Program
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+  1. You may copy and distribute verbatim copies of the Program's
+source code as you receive it, in any medium, provided that you
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+
+You may charge a fee for the physical act of transferring a copy, and
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+  2. You may modify your copy or copies of the Program or any portion
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+be a consequence of the rest of this License.
+
+  8. If the distribution and/or use of the Program is restricted in
+certain countries either by patents or by copyrighted interfaces, the
+original copyright holder who places the Program under this License
+may add an explicit geographical distribution limitation excluding
+those countries, so that distribution is permitted only in or among
+countries not thus excluded.  In such case, this License incorporates
+the limitation as if written in the body of this License.
+
+  9. The Free Software Foundation may publish revised and/or new versions
+of the General Public License from time to time.  Such new versions will
+be similar in spirit to the present version, but may differ in detail to
+address new problems or concerns.
+
+Each version is given a distinguishing version number.  If the Program
+specifies a version number of this License which applies to it and "any
+later version", you have the option of following the terms and conditions
+either of that version or of any later version published by the Free
+Software Foundation.  If the Program does not specify a version number of
+this License, you may choose any version ever published by the Free Software
+Foundation.
+
+  10. If you wish to incorporate parts of the Program into other free
+programs whose distribution conditions are different, write to the author
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+make exceptions for this.  Our decision will be guided by the two goals
+of preserving the free status of all derivatives of our free software and
+of promoting the sharing and reuse of software generally.
+
+show warranty
+                            NO WARRANTY
+
+  11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY
+FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW.  EXCEPT WHEN
+OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES
+PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED
+OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.  THE ENTIRE RISK AS
+TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU.  SHOULD THE
+PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING,
+REPAIR OR CORRECTION.
+
+  12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING
+WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR
+REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES,
+INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING
+OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED
+TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY
+YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER
+PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGES.
+
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/sim.src/test/legal/legal.cmd sdcc-4.2.0+dfsg/sim/ucsim/sim.src/test/legal/legal.cmd
--- sdcc-4.0.0+dfsg/sim/ucsim/sim.src/test/legal/legal.cmd	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/sim.src/test/legal/legal.cmd	2021-03-21 12:01:19.000000000 +0000
@@ -0,0 +1,2 @@
+show copying
+show warranty
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/sim.src/test/legal/Makefile sdcc-4.2.0+dfsg/sim/ucsim/sim.src/test/legal/Makefile
--- sdcc-4.0.0+dfsg/sim/ucsim/sim.src/test/legal/Makefile	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/sim.src/test/legal/Makefile	2021-03-21 12:01:19.000000000 +0000
@@ -0,0 +1,8 @@
+OUTPUTS = legal
+
+
+legal: legal.cmd
+	$(call run-sim)
+
+
+include test-lib.mk
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/sim.src/test/Makefile.in sdcc-4.2.0+dfsg/sim/ucsim/sim.src/test/Makefile.in
--- sdcc-4.0.0+dfsg/sim/ucsim/sim.src/test/Makefile.in	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/sim.src/test/Makefile.in	2021-03-28 10:28:14.000000000 +0000
@@ -0,0 +1,9 @@
+# @configure_input@
+
+srcdir           = @abs_srcdir@
+
+abs_top_builddir = @abs_top_builddir@
+abs_top_srcdir   = @abs_top_srcdir@
+
+
+include $(abs_top_srcdir)/test-target.mk
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/sim.src/uc.cc sdcc-4.2.0+dfsg/sim/ucsim/sim.src/uc.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/sim.src/uc.cc	2019-07-02 08:44:01.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/sim.src/uc.cc	2022-02-08 14:54:27.000000000 +0000
@@ -25,21 +25,22 @@
 02111-1307, USA. */
 /*@1@*/
 
-#include "ddconfig.h"
+//#include "ddconfig.h"
 
 #include 
 #include 
 #include 
 #include 
-#include "i_string.h"
+#include 
+//#include "i_string.h"
 
 // prj
 #include "globals.h"
 #include "utils.h"
 
 // cmd.src
-#include "newcmdcl.h"
-#include "cmdutil.h"
+//#include "newcmdcl.h"
+//#include "cmdutil.h"
 #include "cmd_uccl.h"
 #include "cmd_bpcl.h"
 #include "cmd_getcl.h"
@@ -48,12 +49,13 @@
 #include "cmd_timercl.h"
 #include "cmd_statcl.h"
 #include "cmd_memcl.h"
+#include "cmd_execcl.h"
 
 // local, sim.src
 #include "uccl.h"
-#include "hwcl.h"
-#include "memcl.h"
-#include "simcl.h"
+//#include "hwcl.h"
+//#include "memcl.h"
+//#include "simcl.h"
 #include "itsrccl.h"
 #include "simifcl.h"
 #include "vcdcl.h"
@@ -65,43 +67,43 @@
  * Clock counter
  */
 
-cl_ticker::cl_ticker(int adir, int in_isr, const char *aname)
+cl_ticker::cl_ticker(int adir, enum ticker_type atype, const char *aname, bool auser)
 {
-  options= TICK_RUN;
-  if (in_isr)
-    options|= TICK_INISR;
   dir= adir;
+  type= atype;
   ticks= 0;
+  run = true;
   set_name(aname);
+  user= auser;
 }
 
 cl_ticker::~cl_ticker(void) {}
 
-int
-cl_ticker::tick(int nr)
-{
-  if (options&TICK_RUN)
-    ticks+= dir*nr;
-  return(ticks);
-}
-
-double
-cl_ticker::get_rtime(double xtal)
+void
+cl_ticker::tick(int nr, double time)
 {
-  double d;
-
-  d= (double)ticks/xtal;
-  return(d);
+  if (dir >= 0)
+    {
+      ticks+= nr;
+      rtime+= time;
+    }
+  else
+    {
+      ticks-= nr;
+      rtime-= time;
+    }
 }
 
 void
-cl_ticker::dump(int nr, double xtal, class cl_console_base *con)
+cl_ticker::dump(int nr, class cl_console_base *con)
 {
-  con->dd_printf("timer #%d(\"%s\") %s%s: %g sec (%lu clks)\n",
+  const char *type_names[] = { "", ",ISR", ",IDLE", ",HALT" };
+
+  con->dd_printf("timer #%d(\"%s\") %s%s %.15f sec (%lu clks)\n",
 		 nr, get_name("unnamed"),
-		 (options&TICK_RUN)?"ON":"OFF",
-		 (options&TICK_INISR)?",ISR":"",
-		 get_rtime(xtal), ticks);
+		 (run ? "ON" : "OFF"),
+		 type_names[type],
+		 rtime, ticks);
 }
 
 
@@ -122,9 +124,54 @@
     return;
   double d;
   option->get_value(&d);
-  uc->xtal= d;
+  uc->set_xtal(d);
 }
 
+cl_stop_selfjump_option::cl_stop_selfjump_option(class cl_uc *the_uc):
+  cl_optref(the_uc)
+{
+  uc= the_uc;
+}
+
+int
+cl_stop_selfjump_option::init(void)
+{
+  cl_optref::init();
+  create(uc, bool_opt, "selfjump_stop", "Stop when jump branches to itself");
+  return 0;
+}
+
+void
+cl_stop_selfjump_option::option_changed(void)
+{
+  bool b;
+  option->get_value(&b);
+  uc->stop_selfjump= b;
+}
+
+cl_analyzer_option::cl_analyzer_option(class cl_uc *the_uc):
+  cl_optref(the_uc)
+{
+  uc= the_uc;
+}
+
+int
+cl_analyzer_option::init(void)
+{
+  cl_optref::init();
+  create(uc, bool_opt, "analyzer", "Analyze and label code");
+  return 0;
+}
+
+void
+cl_analyzer_option::option_changed(void)
+{
+  bool b;
+  option->get_value(&b);
+  uc->analyzer= b;
+  if (uc->rom)
+    uc->analyze_init();
+}
 
 /* Time measurer */
 
@@ -167,7 +214,7 @@
 cl_time_clk::now()
 {
   if (!uc) return 0;
-  return uc->ticks->ticks;
+  return uc->ticks->get_ticks();
 }
 
 
@@ -292,12 +339,10 @@
     return false;
   c= g(f);
   l= c;
-  //printf("l=%02x\n", c);
   if (f->eof())
     return false;
   c= g(f);
   h= c;
-  //printf("h=%02x\n", c);
   if (f->eof())
     return false;
   len= h*256+l-1;
@@ -315,6 +360,152 @@
 
 
 /*
+ * Execution history
+ */
+
+cl_exec_hist::cl_exec_hist(class cl_uc *auc):
+  cl_base()
+{
+  uc= auc;
+  len= 10001;
+  hist= (struct t_hist_elem*)malloc(sizeof(struct t_hist_elem) * len);
+  t= h= 0;
+}
+
+cl_exec_hist::~cl_exec_hist(void)
+{
+  if (hist)
+    free(hist);
+}
+
+int
+cl_exec_hist::init(void)
+{
+  return 0;
+}
+
+void
+cl_exec_hist::put(void)
+{
+  t_addr pc;
+  if (!uc)
+    return;
+  pc= uc->PC;
+  if (t != h)
+    {
+      if (hist[h].addr == pc)
+	{
+	  hist[h].nr++;
+	  return;
+	}
+    }
+  int nh= (h+1)%len;
+  if (t == nh)
+    t= (t+1)%len;
+  h= nh;
+  hist[h].addr= pc;
+  hist[h].nr= 1;
+}
+
+void
+cl_exec_hist::list(class cl_console_base *con, bool inc, int nr)
+{
+  int s, p, ta, l;
+  if (!con)
+    return;
+  if (t==h)
+    return;
+  if (nr > len-1)
+    nr= len-1;
+  if (nr > get_used())
+    nr= get_used();
+  s= h-nr+1;
+  if (s<0)
+    s+= len;
+  //s%= len;
+  ta= (t+1)%len;
+
+  p= inc?s:h;
+  do
+    {
+      if (!uc)
+	{
+	  l= con->dd_cprintf("dump_address", "0x%06x", AU(hist[p].addr));
+	}
+      else
+	{
+	  l= uc->print_disass(hist[p].addr, con, false);
+	}
+      if (hist[p].nr > 1)
+	{
+	  l++; con->dd_printf(" ");
+	  while (l%8 != 0)
+	    l++, con->dd_printf(" ");
+	  con->dd_printf("(%d times)", hist[p].nr);
+	}
+      con->dd_printf("\n");
+      if (inc)
+	{
+	  if (p==h)
+	    break;
+	  p= (p+1)%len;
+	}
+      else
+	{
+	  if (p==ta)
+	    break;
+	  if (p==0)
+	    p=len-1;
+	  else
+	    p= (p-1)%len;
+	}
+      con->dd_color("answer");
+    }
+  while (1);
+}
+
+void
+cl_exec_hist::keep(int nr)
+{
+  if (nr < 0)
+    nr= 0;
+  if (t==h)
+    return;
+  while (get_used() > nr)
+    t= (t+1)%len;
+}
+
+int
+cl_exec_hist::get_used()
+{
+  if (t==h)
+    return 0;
+  if (h>t)
+    return h-t;
+  return len-t + h;
+}
+
+unsigned int
+cl_exec_hist::get_insts()
+{
+  unsigned int i= 0;
+  int p;
+  if (t==h)
+    return 0;
+  p= (t+1)%len;
+  do
+    {
+      i+= hist[p].nr;
+      if (p==h)
+	break;
+      p= (p+1)%len;
+    }
+  while (1);
+  return i;
+}
+
+
+/*
  * Abstract microcontroller
  ******************************************************************************
  */
@@ -326,8 +517,8 @@
   //int i;
   sim = asim;
   //mems= new cl_list(MEM_TYPES, 1);
-  memchips= new cl_list(2, 2, "memchips");
-  address_spaces= new cl_address_space_list(this);
+  memchips= new cl_memory_list(this, "memchips");
+  address_spaces= new cl_memory_list(this, "address_spaces");
   //address_decoders= new cl_list(2, 2);
   rom= 0;
 
@@ -336,10 +527,19 @@
   //for (i= MEM_ROM; i < MEM_TYPES; i++) mems->add(0);
   xtal_option= new cl_xtal_option(this);
   xtal_option->init();
-  ticks= new cl_ticker(+1, 0, "time");
-  isr_ticks= new cl_ticker(+1, TICK_INISR, "isr");
-  idle_ticks= new cl_ticker(+1, TICK_IDLE, "idle");
+  stop_selfjump_option= new cl_stop_selfjump_option(this);
+  stop_selfjump_option->init();
+  analyzer_option= new cl_analyzer_option(this);
+  analyzer_option->init();
   counters= new cl_list(2, 2, "counters");
+  ticks= new cl_ticker(+1, TICK_ANY, "time", false);
+  add_counter(ticks, ticks->get_name());
+  isr_ticks= new cl_ticker(+1, TICK_INISR, "isr", false);
+  add_counter(isr_ticks, isr_ticks->get_name());
+  idle_ticks= new cl_ticker(+1, TICK_IDLE, "idle", false);
+  add_counter(idle_ticks, idle_ticks->get_name());
+  halt_ticks= new cl_ticker(+1, TICK_HALT, "halt", false);
+  add_counter(halt_ticks, halt_ticks->get_name());
   it_levels= new cl_list(2, 2, "it levels");
   it_sources= new cl_irqs(2, 2);
   class it_level *il= new it_level(-1, 0, 0, 0);
@@ -350,6 +550,7 @@
   sp_max= 0;
   sp_avg= 0;
   inst_exec= false;
+  hist= new cl_exec_hist(this);
 }
 
 
@@ -361,6 +562,7 @@
   delete ticks;
   delete isr_ticks;
   delete idle_ticks;
+  delete halt_ticks;
   delete counters;
   events->disconn_all();
   delete events;
@@ -375,6 +577,7 @@
   delete address_spaces;
   delete memchips;
   //delete address_decoders;
+  delete hist;
 }
 
 
@@ -386,14 +589,18 @@
   set_name("controller");
   cl_base::init();
   if (xtal_option->use("xtal"))
-    xtal= xtal_option->get_value(xtal);
+    set_xtal(xtal_option->get_value(xtal));
   else
-    xtal= 11059200;
+    set_xtal(11059200);
+  stop_selfjump= false;
+  stop_selfjump_option->option->set_value(stop_selfjump);
+  analyzer= true;
+  analyzer_option->option->set_value(analyzer);
   vars= new cl_var_list();
   make_variables();
   make_memories();
   if (rom == NULL)
-    rom= address_space(cchars("rom")/*MEM_ROM_ID*/);
+    rom= address_space("rom"/*MEM_ROM_ID*/);
   ebrk= new brk_coll(2, 2, rom);
   fbrk= new brk_coll(2, 2, rom);
   fbrk->Duplicates= false;
@@ -404,12 +611,13 @@
   class cl_cmdset *cs= sim->app->get_commander()->cmdset;
   build_cmdset(cs);
   irq= false;
+  vcd_break= false;
   reset();
 
   return 0;
   for (i= 0; i < sim->app->in_files->count; i++)
     {
-      char *fname= (char *)(sim->app->in_files->at(i));
+      const char *fname= (const char *)(sim->app->in_files->at(i));
       long l;
       if ((l= read_hex_file(fname)) >= 0)
 	{
@@ -420,10 +628,10 @@
   return(0);
 }
 
-char *
+const char *
 cl_uc::id_string(void)
 {
-  return((char*)"unknown microcontroller");
+  return("unknown microcontroller");
 }
 
 void
@@ -434,9 +642,10 @@
   irq= false;
   instPC= PC= 0;
   state = stGO;
-  ticks->ticks= 0;
-  isr_ticks->ticks= 0;
-  idle_ticks->ticks= 0;
+  ticks->set(0, 0);
+  isr_ticks->set(0, 0);
+  idle_ticks->set(0, 0);
+  halt_ticks->set(0, 0);
   vc.inst= vc.fetch= vc.rd= vc.wr= 0;
   /*FIXME should we clear user counters?*/
   il= (class it_level *)(it_levels->top());
@@ -460,6 +669,26 @@
     }
 }
 
+void
+cl_uc::reg_cell_var(class cl_memory_cell *cell,
+		    void *store,
+		    chars vname, chars vdesc)
+{
+  if (cell)
+    {
+      cell->init();
+      if (store)
+	cell->decode(store);
+      if (vname.nempty())
+	{
+	  class cl_cvar *v;
+	  vars->add(v= new cl_cvar(vname, cell, vdesc));
+	  v->init();
+	}
+    }
+}
+
+
 /*
  * Making elements
  */
@@ -490,7 +719,7 @@
       as->init();
       address_spaces->add(as);
 
-      chip= new cl_memory_chip("variable_storage", l, 32);
+      chip= new cl_chip32("variable_storage", l, 32);
       chip->init();
       memchips->add(chip);
       ad= new cl_address_decoder(variables, chip, 0, l-1, 0);
@@ -563,8 +792,12 @@
   cmdset->add(cmd= new cl_reset_cmd("reset", 0));
   cmd->init();
 
+  cmdset->add(cmd= new cl_tick_cmd("tick", 0));
+  cmd->init();
+
   cmdset->add(cmd= new cl_dump_cmd("dump", true));
   cmd->init();
+  cmd->add_name("d");
 
   cmdset->add(cmd= new cl_dch_cmd("dch", true));
   cmd->init();
@@ -614,13 +847,13 @@
     cmd->init();
     /*cset->add(cmd= new cl_get_option_cmd("option", 0));
       cmd->init();*/
+    if (!super_cmd)
+      {
+	cmdset->add(cmd= new cl_super_cmd("get", 0, cset));
+	cmd->init();
+	set_get_help(cmd);
+      }
   }
-  if (!super_cmd)
-    {
-      cmdset->add(cmd= new cl_super_cmd("get", 0, cset));
-      cmd->init();
-      set_get_help(cmd);
-    }
 
   {
     super_cmd= (class cl_super_cmd *)(cmdset->get_cmd("set"));
@@ -631,19 +864,18 @@
       cset->init();
     }
     cset->add(cmd= new cl_set_mem_cmd("memory", 0));
-    cmd->init();
-    cset->add(cmd= new cl_set_bit_cmd("bit", 0));
+    cmd->add_name("bits");
     cmd->init();
     cset->add(cmd= new cl_set_hw_cmd("hardware", 0));
     cmd->add_name("hw");
     cmd->init();
+    if (!super_cmd)
+      {
+	cmdset->add(cmd= new cl_super_cmd("set", 0, cset));
+	cmd->init();
+	set_set_help(cmd);
+      }
   }
-  if (!super_cmd)
-    {
-      cmdset->add(cmd= new cl_super_cmd("set", 0, cset));
-      cmd->init();
-      set_set_help(cmd);
-    }
 
   { // info
     super_cmd= (class cl_super_cmd *)(cmdset->get_cmd("info"));
@@ -660,6 +892,7 @@
     cmd->init();
     cset->add(cmd= new cl_info_hw_cmd("hardware", 0));
     cmd->add_name("hw");
+    cmd->add_name("h");
     cmd->init();
     /*
     cset->add(cmd= new cl_info_stack_cmd("stack", 0,
@@ -672,11 +905,13 @@
     cset->add(cmd= new cl_info_var_cmd("variables", 0));
     cmd->init();
     cmd->add_name("vars");
-  }
-  if (!super_cmd) {
-    cmdset->add(cmd= new cl_super_cmd("info", 0, cset));
+    cset->add(cmd= new cl_hist_info_cmd("history", 0));
     cmd->init();
-    set_info_help(cmd);
+    if (!super_cmd) {
+      cmdset->add(cmd= new cl_super_cmd("info", 0, cset));
+      cmd->init();
+      set_info_help(cmd);
+    }
   }
 
   {
@@ -704,16 +939,16 @@
     cset->add(cmd= new cl_timer_value_cmd("set", 0));
     cmd->init();
     cmd->add_name("value");
-  }
-  if (!super_cmd) {
-    cmdset->add(cmd= new cl_super_cmd("timer", 0, cset));
-    cmd->init();
-    set_timer_help(cmd);
+    if (!super_cmd) {
+      cmdset->add(cmd= new cl_super_cmd("timer", 0, cset));
+      cmd->init();
+      set_timer_help(cmd);
+    }
   }
 
   {
-    class cl_super_cmd *mem_create;
-    class cl_cmdset *mem_create_cset;
+    class cl_super_cmd *mem_create, *mem_remove;
+    class cl_cmdset *mem_create_cset, *mem_remove_cset;
     super_cmd= (class cl_super_cmd *)(cmdset->get_cmd("memory"));
     if (super_cmd)
       cset= super_cmd->get_subcommands();
@@ -780,16 +1015,59 @@
     cmd->init();
     cset->add(cmd= new cl_memory_cell_cmd("cell", 0));
     cmd->init();
-  }
-  if (!super_cmd) {
-    cmdset->add(cmd= new cl_super_cmd("memory", 0, cset));
+    if (!super_cmd) {
+      cmdset->add(cmd= new cl_super_cmd("memory", 0, cset));
+      cmd->init();
+      set_memory_help(cmd);
+    }
+
+    mem_remove= (class cl_super_cmd *)cset->get_cmd("remove");
+    if (mem_remove)
+      mem_remove_cset= mem_remove->get_subcommands();
+    else {
+      mem_remove_cset= new cl_cmdset();
+      mem_remove_cset->init();
+    }
+    
+    mem_remove_cset->add(cmd= new cl_memory_remove_chip_cmd("chip", 0));
     cmd->init();
-    set_memory_help(cmd);
+
+    if (!mem_remove)
+      cset->add(mem_remove= new cl_super_cmd("remove", 0, mem_remove_cset));
+    mem_remove->init();
+    mem_remove->add_name("del");
+    mem_remove->add_name("rm");
+    set_memory_remove_help(mem_remove);
   }
 
+  super_cmd= (class cl_super_cmd *)(cmdset->get_cmd("history"));
+  if (super_cmd)
+    cset= super_cmd->get_subcommands();
+  else
+    {
+      cset= new cl_cmdset();
+      cset->init();
+      cmdset->add(cmd= new cl_super_cmd("history", 0, cset));
+      cmd->init();	
+    }
+  cset->add(cmd= new cl_hist_cmd("_no_parameters_", 0));
+  cmd->init();
+  cset->add(cmd= new cl_hist_info_cmd("information", 0));
+  cmd->init();
+  cset->add(cmd= new cl_hist_clear_cmd("clear", 0));
+  cmd->init();
+  cset->add(cmd= new cl_hist_list_cmd("list", 0));
+  cmd->add_name("print");
+  cmd->init();
+    
   cmdset->add(cmd= new cl_var_cmd("var", 0));
   cmd->init();
   cmd->add_name("variable");
+  cmdset->add(cmd= new cl_rmvar_cmd("rmvar", 0));
+  cmd->init();
+
+  cmdset->add(cmd= new cl_analyze_cmd("analyze", 0));
+  cmd->init();
 }
 
 
@@ -798,7 +1076,7 @@
  */
 
 t_mem
-cl_uc::read_mem(char *id, t_addr addr)
+cl_uc::read_mem(const char *id, t_addr addr)
 {
   class cl_address_space *m= address_space(id);
 
@@ -806,7 +1084,7 @@
 }
 
 t_mem
-cl_uc::get_mem(char *id, t_addr addr)
+cl_uc::get_mem(const char *id, t_addr addr)
 {
   class cl_address_space *m= address_space(id);
 
@@ -814,7 +1092,7 @@
 }
 
 void
-cl_uc::write_mem(char *id, t_addr addr, t_mem val)
+cl_uc::write_mem(const char *id, t_addr addr, t_mem val)
 {
   class cl_address_space *m= address_space(id);
 
@@ -823,7 +1101,7 @@
 }
 
 void
-cl_uc::set_mem(char *id, t_addr addr, t_mem val)
+cl_uc::set_mem(const char *id, t_addr addr, t_mem val)
 {
   class cl_address_space *m= address_space(id);
 
@@ -918,6 +1196,40 @@
   return(0);
 }
 
+void
+cl_uc::remove_chip(class cl_memory *chip)
+{
+  class cl_address_space *as;
+  class cl_address_decoder *ad;
+  int i, j;
+  t_index idx;
+  i= memchips->index_of(chip, &idx);
+  if (!i)
+    return;
+  for (i= 0; i < address_spaces->get_count(); i++)
+    {
+      as= (class cl_address_space *)(address_spaces->at(i));
+      j= 0;
+      while (j < as->decoders->get_count())
+	{
+	  for (j= 0; j < as->decoders->get_count(); j++)
+	    {
+	      t_addr as_start, as_end;
+	      ad= (class cl_address_decoder *)(as->decoders->at(j));
+	      as_start= ad->as_begin;
+	      as_end= ad->as_end;
+	      if (ad->memchip == chip)
+		{
+		  as->undecode_area(NULL, as_start, as_end, NULL);
+		  break;
+		}
+	    }
+	}
+    }
+  memchips->disconn(chip);
+  delete chip;
+}
+
 
 static long
 ReadInt(cl_f *f, bool *ok, int bytes)
@@ -965,7 +1277,6 @@
 void
 cl_uc::set_rom(t_addr addr, t_mem val)
 {
-  //printf("rom[%06lx]=%02x\n", addr, val);
   t_addr size= rom->get_size();
   if (addr < size)
     {
@@ -975,22 +1286,20 @@
   t_addr bank, caddr;
   bank= addr / size;
   caddr= addr % size;
-  //printf("getting decoder of %ld/%lx\n", bank, caddr);
   class cl_banker *d= (class cl_banker *)(rom->get_decoder_of(caddr));
   if (d)
     {
       if (!d->is_banker())
 	{
-	  //printf("cell at %lx has no banker\n", caddr);
 	  return;
 	}
-      //printf("setting %ld/rom[%lx]=%x\n", bank, caddr, val);
       d->switch_to(bank, NULL);
       rom->download(caddr, val);
       d->activate(NULL);
     }
   else
-    ;//printf("no decoder at %lx\n", caddr);
+    {
+    }
 }
 
 long
@@ -1041,8 +1350,9 @@
   uchar sum ;     // checksum
   uchar chk ;     // check
   int  i;
-  bool ok, get_low= 1;
-  uchar low= 0, high;
+  bool ok;
+  int get_low= 0;
+  uchar lows[4]= { 0, 0, 0, 0 };
 
   if (!rom)
     {
@@ -1057,25 +1367,28 @@
 	 rtyp != 1)
     {
       while (((c= /*getc(f)*/f->get_c()) != ':') &&
-	     (/*c != EOF*/!f->eof())) /*printf("search_record=%c\n",c)*/;
+	     (/*c != EOF*/!f->eof()));
       if (c != ':')
-	{fprintf(stderr, ": not found\n");break;}
+	{
+	  fprintf(stderr, ": not found\n");
+	  break;
+	}
       recnum++;
-      dnum= ReadInt(f, &ok, 1);//printf("%ld:dnum=%02x ",recnum,dnum);
+      dnum= ReadInt(f, &ok, 1);
       chk = dnum;
-      addr= ReadInt(f, &ok, 2);//printf("%ld:addr=%04x ",recnum,addr);
+      addr= ReadInt(f, &ok, 2);
       chk+= (addr & 0xff);
       chk+= ((addr >> 8) & 0xff);
-      rtyp= ReadInt(f, &ok, 1);//printf("%ld:rtyp=%02x ",recnum,rtyp);
+      rtyp= ReadInt(f, &ok, 1);
       chk+= rtyp;
       for (i= 0; ok && (i < dnum); i++)
 	{
-	  rec[i]= ReadInt(f, &ok, 1);//printf("%02x",rec[i]);
+	  rec[i]= ReadInt(f, &ok, 1);
 	  chk+= rec[i];
 	}
       if (ok)
 	{
-	  sum= ReadInt(f, &ok, 1);//printf(" %ld:sum=%02x\n",recnum,sum);
+	  sum= ReadInt(f, &ok, 1);
 	  if (ok)
 	    {
 	      if (((sum + chk) & 0xff) == 0)
@@ -1094,49 +1407,70 @@
 			    }
 			  else if (rom->width <= 16)
 			    {
-			      if (get_low)
+			      switch (get_low)
 				{
-				  low= rec[i];
+				case 0: lows[0]= rec[i]; get_low++; break;
+				case 1: lows[1]= rec[i];
+				  set_rom(base+addr, (lows[1]*256)+lows[0]);
+				  addr++;
+				  written++;
 				  get_low= 0;
+				  break;
 				}
-			      else
+			    }
+			  else if (rom->width <= 32)
+			    {
+			      switch (get_low)
 				{
-				  high= rec[i];
-				  set_rom(base+addr, (high*256)+low);
+				case 0: lows[0]= rec[i]; get_low++; break;
+				case 1: lows[1]= rec[i]; get_low++; break;
+				case 2: lows[2]= rec[i]; get_low++; break;
+				case 3: lows[3]= rec[i];
+				  set_rom(base+addr,
+					  (lows[3]<<24)+
+					  (lows[2]<<16)+
+					  (lows[1]<<8)+
+					  (lows[0]));
+				  get_low= 0;
+				  lows[3]= lows[2]= lows[1]= lows[0]= 0;
 				  addr++;
 				  written++;
-				  get_low= 1;
+				  break;
 				}
 			    }
 			}
 		    }
 		  else if (rtyp == 4)
 		    {
-		      //printf("hex record type=4\n");
 		      if (dnum >= 2)
 			{
 			  base= (rec[0]*256+rec[1]) << 16;
-			  //printf("hex base=%x\n", base);
 			}
 		    }
 		  else
 		    if (rtyp != 1)
-		      /*application->debug*/fprintf(stderr, "Unknown record type %d(0x%x)\n",
-					 rtyp, rtyp);
+		      fprintf(stderr, "Unknown record type %d(0x%x)\n",
+			      rtyp, rtyp);
 		}
 	      else
-		/*application->debug*/fprintf(stderr, "Checksum error (%x instead of %x) in "
-				   "record %ld.\n", chk, sum, recnum);
+		fprintf(stderr, "Checksum error (%x instead of %x) in "
+			"record %ld.\n", chk, sum, recnum);
 	    }
 	  else
-	    /*application->debug*/fprintf(stderr, "Read error in record %ld.\n", recnum);
+	    fprintf(stderr, "Read error in record %ld.\n", recnum);
 	}
     }
-  if (rom->width > 8 &&
-      !get_low)
-    rom->set(addr, low);
-
-  analyze(0);
+  if (rom->width > 8)
+    {
+      for (i= get_low; i<4; i++)
+	lows[i]= 0;
+      rom->set(addr,
+	       (lows[3]<<24)+
+	       (lows[2]<<16)+
+	       (lows[1]<<8)+
+	       (lows[0]));
+    }
+  
   return(written);
 }
 
@@ -1164,20 +1498,69 @@
 }
 
 long
+cl_uc::read_asc_file(cl_f *f)
+{
+  int c;
+  chars line= chars();
+  bool in;
+  t_addr addr= 0;
+  
+  in= true;
+  while ((c= f->get_c()) &&
+	 (!f->eof()))
+    {
+      if (in)
+	{
+	  if ((c=='\n') || (c=='\r'))
+	    {
+	      in= false;
+	      {
+		chars word= chars();
+		const char *s;
+		// process
+		line.trim();
+		line.start_parse();
+		word= line.token(" ");
+		s= word.c_str();
+		if (isxdigit(*s))
+		  {
+		    t_mem d= strtoll(s, 0, 16);
+		    set_rom(addr, d);
+		    addr++;
+		  }
+		line= "";
+	      }
+	    }
+	  else
+	    line.append(c);
+	}
+      else // out
+	{
+	  if ((c=='\n') || (c=='\r'))
+	    ;
+	  else
+	    {
+	      in= true;
+	      line.append(c);
+	    }
+	}
+    }
+  return addr;
+}
+  
+long
 cl_uc::read_cdb_file(cl_f *f)
 {
   class cl_cdb_recs *fns= new cl_cdb_recs();
   chars ln;
-  char *lc;
+  const char *lc;
   long cnt= 0;
   class cl_cdb_rec *r;
-  class cl_var *v;
-  
+
   ln= f->get_s();
   while (!ln.empty())
     {
-      //printf("CBD LN=%s\n",(char*)ln);
-      lc= (char*)ln;
+      lc= ln.c_str();
       if (lc[0] == 'F')
 	{
 	  if (ln.len() > 5)
@@ -1189,8 +1572,7 @@
 		  chars n= ln.token("$");
 		  if ((r= fns->rec(n)) != NULL)
 		    {
-		      vars->add(v= new cl_var(n, rom, r->addr, ""));
-		      v->init();
+		      vars->add(n, rom, r->addr, "");
 		      fns->del(n);
 		      cnt++;
 		    }
@@ -1210,12 +1592,11 @@
 		  chars n= ln.token("$");
 		  chars t= ln.token(":");
 		  t= ln.token(" ");
-		  t_addr a= strtol((char*)t, 0, 16);
+		  t_addr a= strtol(t.c_str(), 0, 16);
 		  if ((r= fns->rec(n)) != NULL)
 		    {
 		      fns->del(n);
-		      vars->add(v= new cl_var(n, rom, a, ""));
-		      v->init();
+		      vars->add(n, rom, a, "");
 		      cnt++;
 		    }
 		  else
@@ -1242,24 +1623,29 @@
   if (o)
     return f;
 
-  c= chars("", "%s.ihx", (char*)nam);
-  f->open(c, chars("r"));
+  c= chars("", "%s.asc", nam.c_str());
+  f->open(c, "r");
   o= (f->opened());
   if (o)
     return f;
-  c= chars("", "%s.hex", (char*)nam);
-  f->open(c, chars("r"));
+  c= chars("", "%s.ihx", nam.c_str());
+  f->open(c, "r");
   o= (f->opened());
   if (o)
     return f;
-  c= chars("", "%s.ihex", (char*)nam);
-  f->open(c, chars("r"));
+  c= chars("", "%s.hex", nam.c_str());
+  f->open(c, "r");
+  o= (f->opened());
+  if (o)
+    return f;
+  c= chars("", "%s.ihex", nam.c_str());
+  f->open(c, "r");
   o= (f->opened());
   if (o)
     return f;
 
-  c= chars("", "%s.omf", (char*)nam);
-  f->open(c, chars("r"));
+  c= chars("", "%s.omf", nam.c_str());
+  f->open(c, "r");
   o= (f->opened());
   if (o)
     return f;
@@ -1276,48 +1662,166 @@
   
   if (!f)
     {
-      if (con) con->dd_printf("no loadable file found\n");
+      if (con)
+	con->dd_printf("no loadable file found (%s)\n", nam.c_str());
+      else
+	printf("no loadable file found (%s)\n", nam.c_str());
       return 0;
     }
-  /*if (con) con->dd_*/printf("Loading from %s\n", f->get_file_name());
+  if (!application->quiet)
+    printf("Loading from %s\n", f->get_file_name());
+  if (is_asc_file(f))
+    {
+      l= read_asc_file(f);
+      if (!application->quiet)
+	printf("%ld words read from %s\n", l, f->get_fname());
+    }
   if (is_hex_file(f))
     {
       l= read_hex_file(f);
-      printf("%ld words read from %s\n", l, f->get_fname());
+      if (!application->quiet)
+	printf("%ld words read from %s\n", l, f->get_fname());
     }
   else if (is_omf_file(f))
     {
       l= read_omf_file(f);
-      printf("%ld words read from %s\n", l, f->get_fname());
+      if (!application->quiet)
+	printf("%ld words read from %s\n", l, f->get_fname());
     }
   else if (is_cdb_file(f))
     {
       l= read_cdb_file(f);
-      printf("%ld symbols read from %s\n", l, f->get_fname());
+      if (!application->quiet)
+	printf("%ld symbols read from %s\n", l, f->get_fname());
     }
   if (strcmp(nam, f->get_fname()) != 0)
     {
       chars n= nam;
-      n+= (char*)".cdb";
+      n+= ".cdb";
       cl_f *c= mk_io(n, "r");
       if (c->opened())
 	{
 	  l= read_cdb_file(c);
-	  printf("%ld symbols read from %s\n", l, c->get_fname());
+	  if (!application->quiet)
+	    printf("%ld symbols read from %s\n", l, c->get_fname());
 	}
       delete c;
     }
   delete f;
+
+  analyze_init();
   return l;
 }
 
 
+void
+cl_uc::analyze_init(void)
+{
+  // Forget everything we knew previously.
+  for (t_addr addr = rom->get_start_address(); addr < rom->highest_valid_address(); addr++)
+    del_inst_at(addr);
+
+  t_index i = 0;
+  while (i < vars->by_name.count)
+    {
+      class cl_cvar *v = vars->by_name.at(i);
+      if (*(v->get_name()) == '.')
+        vars->del(v->get_name());
+      else
+        i++;
+    }
+
+  if (analyzer)
+    analyze_start();
+}
+
+void
+cl_uc::analyze_start(void)
+{
+  class cl_var *v = new cl_var(".reset", rom, 0, chars("Auto-generated by analyze"), -1, -1);
+  v->init();
+  vars->add(v);
+
+  analyze(0);
+}
+
+void
+cl_uc::analyze(t_addr addr)
+{
+  set_inst_at(addr);
+
+  // If we jumped we should make sure its labeled. However we don't know if the
+  // target has a valid instruction and only a microprocessor specific analyze
+  // implementation can follow the execution path. So we tell a white lie.
+  bool was_inst = inst_at(PC);
+  set_inst_at(PC);
+
+  if (PC != addr + inst_length(addr))
+    analyze_jump(addr, PC, 'j');
+
+  if (!was_inst)
+    del_inst_at(PC);
+}
+
+void
+cl_uc::analyze_jump(t_addr addr, t_addr target, char type, unsigned int bit)
+{
+  // If the target isn't already labeled we'll create one ourselves.
+  t_index var_i;
+  if (!vars->by_addr.search(rom, target, -1, -1, var_i) &&
+      !vars->by_addr.search(rom, target, rom->width, 0, var_i))
+    {
+      const char *var_name = "";
+      const char *suffix = "";
+
+      switch (type)
+        {
+          case 's': // subroutine call
+            var_name = "func";
+            break;
+
+          case 't':
+          case 'f':
+            suffix = (type == 't' ? "_isset" : "_unset");
+            switch (bit)
+              {
+                default:
+                case 0: var_name= "bit0"; break;
+                case 1: var_name= "bit1"; break;
+                case 2: var_name= "bit2"; break;
+                case 3: var_name= "bit3"; break;
+                case 4: var_name= "bit4"; break;
+                case 5: var_name= "bit5"; break;
+                case 6: var_name= "bit6"; break;
+                case 7: var_name= "bit7"; break;
+              }
+            break;
+
+          default:
+            var_name = (target <= addr ? "loop" : "label");
+            break;
+        }
+
+      chars label("", ".%s%s$%u", var_name, suffix, label_index++);
+      class cl_var *v = new cl_var(label, rom, target, chars("Auto-generated by analyze"), -1, -1);
+      v->init();
+      vars->add(v);
+    }
+
+  // If we didn't know the target was code we do now, but don't cross
+  // into bankers - we don't know what bank would be selected at
+  // execution time.
+  class cl_address_decoder *ad;
+  if (!inst_at(target) && (ad = rom->get_decoder_of(target)) && !ad->is_banker())
+    analyze(target);
+}
+
 /*
  * Handling instruction map
  *
  * `inst_at' is checking if the specified address is in instruction
  * map and `set_inst_at' marks the address in the map and
- * `del_inst_at' deletes the mark. `there_is_inst' cheks if there is
+ * `del_inst_at' deletes the mark. `there_is_inst' checks if there is
  * any mark in the map
  */
 
@@ -1433,7 +1937,7 @@
   for (; i < hws->count; i++)
     {
       hw= (class cl_hw *)(hws->at(i));
-      if (hw->cathegory == cath)
+      if (hw->category == cath)
 	break;
     }
   if (i >= hws->count)
@@ -1444,13 +1948,15 @@
 }
 
 class cl_hw *
-cl_uc::get_hw(char *id_string, int *idx)
+cl_uc::get_hw(const char *id_string, int *idx)
 {
   class cl_hw *hw= 0;
   int i= 0;
 
   if (idx)
     i= *idx;
+  if (strcmp(id_string, "cpu") == 0)
+    return cpu;
   for (; i < hws->count; i++)
     {
       hw= (class cl_hw *)(hws->at(i));
@@ -1486,7 +1992,7 @@
 }
 
 class cl_hw *
-cl_uc::get_hw(char *id_string, int hwid, int *idx)
+cl_uc::get_hw(const char *id_string, int hwid, int *idx)
 {
   class cl_hw *hw;
   int i= 0;
@@ -1533,52 +2039,77 @@
 }
 
 char *
-cl_uc::disass(t_addr addr, const char *sep)
+cl_uc::disass(t_addr addr)
 {
-  char *buf;
-
-  buf= (char*)malloc(100);
-  strcpy(buf, "uc::disass() unimplemented\n");
-  return(buf);
+  return strdup("uc::disass() unimplemented\n");
 }
 
-void
-cl_uc::print_disass(t_addr addr, class cl_console_base *con)
+int
+cl_uc::print_disass(t_addr addr, class cl_console_base *con, bool nl)
 {
   char *dis;
+  chars cdis, comment;
   class cl_brk *b;
-  int i, l;
-
+  int i, l, len= 0;
+  class cl_option *o= sim->app->options->get_option("black_and_white");
+  bool bw= false;
+  if (o) o->get_value(&bw);
+  
   if (!rom)
-    return;
+    return 0;
+
+  cl_vars_iterator vi(vars);
+  const class cl_var *var = NULL;
+  if ((var = vi.first(rom, addr)))
+    {
+      len+= con->dd_printf("\n");
+
+      do {
+        len+= con->dd_cprintf("dump_address", rom->addr_format, addr);
+        len+= con->dd_cprintf("answer", "   ");
+        len+= con->dd_cprintf("dump_label", " <%s>:\n", var->get_name());
+      } while ((var = vi.next()));
+    }
 
-  t_mem code= rom->get(addr);
   b= fbrk_at(addr);
-  dis= disass(addr, NULL);
-  if (b)
-    con->dd_cprintf("answer", "%c", (b->perm == brkFIX)?'F':'D');
-  else
-    con->dd_printf(" ");
-  con->dd_cprintf("answer", "%c ", inst_at(addr)?' ':'?');
-  con->dd_cprintf("dump_address", rom->addr_format, addr); con->dd_printf(" ");
-  con->dd_cprintf("dump_number", rom->data_format, code);
+  dis= disassc(addr, &comment);
+  cdis= dis;
+  len+= con->dd_cprintf("dump_address", rom->addr_format, addr);
+  len+= con->dd_cprintf("answer", " %c", (b ? (b->perm == brkFIX ? 'F' : 'D') : ' '));
+  len+= con->dd_cprintf("answer", "%c", inst_at(addr)?' ':'?');
   l= inst_length(addr);
-  for (i= 1; i < l; i++)
+  for (i= 0; i < l; i++)
     {
-      con->dd_printf(" ");
-      con->dd_cprintf("dump_number", rom->data_format, rom->get(addr+i));
+      len+= con->dd_printf(" ");
+      len+= con->dd_cprintf("dump_number", rom->data_format, rom->get(addr+i));
     }
-  int li= longest_inst();
-  while (i < li)
+  int padding= (longest_inst() - i) * ((rom->width + 3) / 4 + 1);
+  len+= con->dd_printf("%*.*s", padding, padding, "");
+  if (comment.nempty())
+    while (cdis.len() < 25) cdis.append(' ');
+  len+= con->dd_cprintf("dump_char", " %s", cdis.c_str());
+  if (comment.nempty())
+    len+= con->dd_cprintf("comment", " %s", comment.c_str());
+  if (nl)
     {
-      int j;
-      j= rom->width/4 + ((rom->width%4)?1:0) + 1;
-      while (j)
-	con->dd_printf(" "), j--;
-      i++;
+      if (!bw)
+	{
+	  con->dd_printf("\033[0K");
+	}
+      else
+	{
+	  while (++len < 70) con->dd_printf(" ");
+	}
+      con->dd_printf("\n");
     }
-  con->dd_cprintf("dump_char", " %s\n", dis);
   free((char *)dis);
+  return len;
+}
+
+int
+cl_uc::print_disass(t_addr addr, class cl_console_base *con)
+{
+  return print_disass(addr, con, true);
 }
 
 void
@@ -1650,102 +2181,115 @@
   return(max);
 }
 
-bool
-cl_uc::addr_name(t_addr addr, class cl_address_space *as, char *buf)
+const class cl_var *
+cl_uc::addr_name(t_addr addr,
+		 class cl_memory *mem,
+		 int bitnr_high,
+		 int bitnr_low,
+		 chars *buf,
+		 const class cl_var *context)
 {
   t_index i;
-  
-  for (i= 0; i < vars->count; i++)
-    {
-      class cl_var *v= (cl_var *)(vars->at(i));
-      if ((v->as == as) &&
-	  (v->addr == addr))
-	{
-	  strcpy(buf, v->get_name());
-	  return true;
-	}
+  const cl_var *var = NULL;
+
+  if (!mem)
+    return NULL;
+
+  if (vars->by_addr.search(mem, addr, bitnr_high, bitnr_low, i))
+    var = vars->by_addr.at(i);
+  else if (vars->by_addr.search(mem, addr, mem->width - 1, 0, i))
+    var = vars->by_addr.at(i);
+  else if (bitnr_high >= 0 && vars->by_addr.search(mem, addr, -1, -1, i))
+    var = vars->by_addr.at(i);
+  else if (mem->is_address_space())
+    {
+      cl_address_decoder *ad = ((cl_address_space *)mem)->get_decoder_of(addr);
+      if (ad)
+        {
+          mem = ad->memchip;
+          addr = ad->as_to_chip(addr);
+
+          if (vars->by_addr.search(mem, addr, bitnr_high, bitnr_low, i))
+            var = vars->by_addr.at(i);
+          else if (vars->by_addr.search(mem, addr, mem->width - 1, 0, i))
+            var = vars->by_addr.at(i);
+          else if (bitnr_high >= 0 && vars->by_addr.search(mem, addr, -1, -1, i))
+            var = vars->by_addr.at(i);
+        }
     }
-  unsigned int a= addr;
-  sprintf(buf, "%02x", a);
-  return false;
-}
 
-bool
-cl_uc::addr_name(t_addr addr, class cl_address_space *as, int bitnr, char *buf)
-{
-  t_index i;
-  
-  for (i= 0; i < vars->count; i++)
+  if (var)
     {
-      class cl_var *v= (cl_var *)(vars->at(i));
-      if ((v->as == as) &&
-	  (v->addr == addr) &&
-	  (v->bitnr == bitnr))
-	{
-	  strcpy(buf, v->get_name());
-	  return true;
-	}
+      const char *name = var->get_name();
+
+      // If there is a context var and its name prefixes the var for this
+      // addr we strip the prefix off.
+      size_t len;
+      if (context && (len = strlen(context->get_name())) &&
+          !strncmp(name, context->get_name(), len) &&
+          (name[len] == '\0' || name[len] == '_'))
+        {
+          if (name[len] == '\0')
+            {
+              // Same as context, nothing more to add
+              return var;
+            }
+          else if (name[len] == '_')
+            {
+              // We don't need the prefix - we already had the context
+              if (buf) buf->appendf(" <%s", &name[len + 1]);
+            }
+        }
+      else
+        {
+          // It's all significant, nothing to do with context
+          if (buf) buf->appendf(" <%s", name);
+        }
+
+      if (bitnr_high >= 0 &&
+          (var->bitnr_high != bitnr_high || var->bitnr_low != bitnr_low))
+        {
+          if (bitnr_high == bitnr_low)
+            {
+	      if (buf) buf->appendf(".%d", bitnr_high);
+	    }
+          else
+            {
+	      if (buf) buf->appendf("[%d:%d]", bitnr_high, bitnr_low);
+	    }
+        }
+
+      if (buf) buf->appendf(">");
     }
-  unsigned int a= addr;
-  sprintf(buf, "%02x.%d", a, bitnr);
-  return false;
+
+  return var;
 }
 
 bool
 cl_uc::symbol2address(char *sym,
-		      class cl_address_space **as,
+		      class cl_memory **mem,
 		      t_addr *addr)
 {
-  class cl_var *v;
   t_index i;
 
   if (!sym ||
       !*sym)
     return false;
-  if (vars->search(sym, i))
+  if (vars->by_name.search(sym, i))
     {
-      v= (class cl_var *)(vars->at(i));
-      if (v->bitnr >= 0)
+      class cl_cvar *v= vars->by_name.at(i);
+      /*if (v->bitnr_low >= 0)
+	return false;*/
+      if (!v->is_mem_var())
 	return false;
-      if (as)
-	*as= v->as;
+      if (mem)
+	*mem= v->get_mem();
       if (addr)
-	*addr= v->addr;
+	*addr= v->get_addr();
       return true;
     }
   return false;
 }
-  
-char *
-cl_uc::symbolic_bit_name(t_addr bit_address,
-			 class cl_memory *mem,
-			 t_addr mem_addr,
-			 t_mem bit_mask)
-{
-  //char *sym_name= 0;
-  int i;
-  chars c= chars("", mem?(mem->addr_format):"0x%06lx", (unsigned long)mem_addr);
-  /*if (!sym_name)
-    {
-      sym_name= (char *)malloc(16);
-      sprintf(sym_name, mem?(mem->addr_format):"0x%06lx", (unsigned long)mem_addr);
-      }*/
-  /*sym_name= (char *)realloc(sym_name, strlen(sym_name)+2);
-    strcat(sym_name, ".");*/
-  c+= cchars(".");
-  i= 0;
-  while (bit_mask > 1)
-    {
-      bit_mask>>=1;
-      i++;
-    }
-  //char bitnumstr[10];
-  /*sprintf(bitnumstr, "%1d", i);
-    strcat(sym_name, bitnumstr);*/
-  c.append("%d", i);
-  return(/*sym_name*/strdup((char*)c));
-}
-
 
 /*
  * Searching for a name in the specified table
@@ -1766,7 +2310,6 @@
 	 (!(tabl[i].cpu_type & type->type) ||
 	 (strcmp(tabl[i].name, name) != 0)))
     {
-      //printf("tabl[%d].name=%s <-> %s\n",i,tabl[i].name,name);
       i++;
     }
   if (tabl[i].name != NULL)
@@ -1776,42 +2319,42 @@
 }
 
 chars
-cl_uc::cell_name(class cl_memory_cell *cell)
+cl_uc::cell_name(class cl_memory_cell *cell, int bitnr_high, int bitnr_low)
 {
-  if (cell == NULL)
+  class cl_address_space *as;
+  t_addr addr;
+  int i;
+
+  if (!cell || !(as = address_space(cell, &addr)))
     return chars("");
-  if (cell->get_flag(CELL_VAR))
+
+  if (vars->by_addr.search(as, addr, bitnr_high, bitnr_low, i))
+    return chars(vars->by_addr.at(i)->get_name());
+
+  if (bitnr_high != - 1 && vars->by_addr.search(as, addr, -1, -1, i))
     {
-      int i;
-      for (i= 0; i < vars->count; i++)
-	{
-	  class cl_var *v= (cl_var*)(vars->at(i));
-	  if (v->get_cell() &&
-	      (cell == v->get_cell()))
-	    return chars(v->get_name());
-	}
+      if (bitnr_high != bitnr_low)
+        return chars("", "%s[%d:%d]", vars->by_addr.at(i)->get_name(), bitnr_high, bitnr_low);
+      else
+        return chars("", "%s.%d", vars->by_addr.at(i)->get_name(), bitnr_low);
     }
-  class cl_address_space *as;
-  t_addr a;
-  as= address_space(cell, &a);
-  if (as == NULL)
-    return chars("");
-  return chars("", "%s_%06x", as->get_name(), a);
+
+  if (bitnr_high == -1)
+    return chars("", "%s_%06x", as->get_name(), addr);
+  else if (bitnr_high != bitnr_low)
+    return chars("", "%s_%06x[%d:%d]", as->get_name(), addr, bitnr_high, bitnr_low);
+  else
+    return chars("", "%s_%06x.%d", as->get_name(), addr, bitnr_high);
 }
 
-class cl_var *
-cl_uc::var(char *nam)
+t_addr
+cl_uc::read_addr(class cl_memory *m, t_addr start_addr)
 {
-  if (!vars)
-    return NULL;
-  t_index i;
-  if (!vars->search(nam, i))
-    return NULL;
-  class cl_var *v= (cl_var*)(vars->at(i));
-  return v;
+  if (!m) return 0;
+  // 16 bit little endian, by default
+  return m->read(start_addr) + 256*m->read(start_addr+1);
 }
 
-
 /*
  * Messages to broadcast
  */
@@ -1878,7 +2421,6 @@
 void
 cl_uc::error(class cl_error *error)
 {
-  //printf("error adding: %s...\n", error->get_class()->get_name());
   errors->add(error);
   if ((error->inst= inst_exec))
     error->PC= instPC;
@@ -1893,7 +2435,6 @@
 
   if (c)
     {
-      //printf("error list: %d items\n", errors->count);
       for (i= 0; i < errors->count; i++)
 	{
 	  class cl_error *error= (class cl_error *)(errors->at(i));
@@ -1909,7 +2450,7 @@
 		con= c->frozen_console;
 	      if (con)
 		{
-		  con->dd_printf("Erronouse instruction: ");
+		  con->dd_printf("Erroneous instruction: ");
 		  print_disass(error->PC, con);
 		}
 	    }
@@ -1928,13 +2469,12 @@
  */
 
 class cl_address_space *
-cl_uc::bit2mem(t_addr bitaddr, t_addr *memaddr, t_mem *bitmask)
+cl_uc::bit2mem(t_addr bitaddr, t_addr *memaddr, int *bitnr_high, int *bitnr_low)
 {
   if (memaddr)
     *memaddr= bitaddr;
-  if (bitmask)
-    *bitmask= 1 << (bitaddr & 0x7);
-  return(0); // abstract...
+
+  return rom;
 }
 
 
@@ -1949,12 +2489,15 @@
   int i;//, cpc= clock_per_cycle();
 
   // tick hws
-  for (i= 0; i < hws->count; i++)
+  while (cycles-- > 0)
     {
-      hw= (class cl_hw *)(hws->at(i));
-      if ((hw->flags & HWF_INSIDE) &&
-	  (hw->on))
-	hw->tick(cycles);
+      for (i= 0; i < hws->count; i++)
+        {
+          hw= (class cl_hw *)(hws->at(i));
+          if ((hw->flags & HWF_INSIDE) &&
+              (hw->on))
+            hw->tick(1);
+        }
     }
   do_extra_hw(cycles);
   return(0);
@@ -1968,31 +2511,41 @@
 cl_uc::tick(int cycles)
 {
   //class cl_hw *hw;
-  int i, cpc= clock_per_cycle();
+  int i, clocks= cycles * clock_per_cycle();
+  double time = clocks * xtal_tick;
 
   // increase time
-  ticks->tick(cycles * cpc);
   class it_level *il= (class it_level *)(it_levels->top());
-  if (il->level >= 0)
-    isr_ticks->tick(cycles * cpc);
-  if (state == stIDLE)
-    idle_ticks->tick(cycles * cpc);
   for (i= 0; i < counters->count; i++)
     {
       class cl_ticker *t= (class cl_ticker *)(counters->at(i));
-      if (t)
-	{
-	  if ((t->options&TICK_INISR) ||
-	      il->level < 0)
-	    t->tick(cycles * cpc);
-	}
+      if (t && t->run)
+        {
+          if (t->get_type() == TICK_ANY ||
+              (il->level >= 0 && (t->get_type() == TICK_INISR)) ||
+              (state == stIDLE && (t->get_type() == TICK_IDLE)) ||
+              (state == stPD && (t->get_type() == TICK_HALT)))
+            t->tick(clocks, time);
+        }
     }
 
-  // tick for hardwares
-  inst_ticks+= cycles;
+  tick_hw(cycles);
+
   return(0);
 }
 
+int
+cl_uc::tickt(t_mem code)
+{
+  int8_t *tt= tick_tab(code);
+  if (tt == NULL)
+    return tick(1);
+  int t= tt[code];
+  if (t)
+    return tick(t);
+  return 0;
+}
+
 class cl_ticker *
 cl_uc::get_counter(int nr)
 {
@@ -2103,55 +2656,85 @@
  */
 
 bool
-cl_uc::fetch(t_mem *code)
+cl_uc::do_brk(void)
 {
   class cl_brk *brk;
   int idx;
+  bool ret= false;
 
-  if (!code)
-    return(0);
   if ((sim->state & SIM_GO) &&
       rom &&
       (sim->steps_done > 0))
     {
+      if (vcd_break)
+        {
+          vcd_break = false;
+          ret= true;
+        }
       if (rom->get_cell_flag(PC, CELL_FETCH_BRK))
 	if ((brk= fbrk->get_bp(PC, &idx)))
 	  if (brk->do_hit())
 	    {
 	      if (brk->perm == brkDYNAMIC)
 		fbrk->del_bp(PC);
-	      return(1);
+	      ret= true;
 	    }
     }
-  *code= fetch();
-  return(0);
+
+  return ret;
+}
+
+bool
+cl_uc::fetch(t_mem *code)
+{
+  bool ret = do_brk();
+
+  if (!ret)
+    *code= fetch();
+
+  return ret;
 }
 
 int
 cl_uc::do_inst(int step)
 {
-  t_addr PCsave;
+  t_addr PCsave= PC;
   int res= resGO;
 
   if (step < 0)
     step= 1;
   while (step-- &&
-         res == resGO)
-    {
-      pre_inst();
-      PCsave = PC;
-      res= exec_inst();
-
-      if (res == resINV_INST)
-	/* backup to start of instruction */
-	PC = PCsave;
-      
+         res == resGO &&
+	 (
+	  (state == stGO) || (state == stIDLE)
+	  )
+	 )
+    {
+      if (state == stGO)
+	{
+	  pre_inst();
+	  PCsave = PC;
+	  res= exec_inst();
+
+	  if (res == resINV_INST)
+	    /* backup to start of instruction */
+	    PC = PCsave;
+	  else if (res == resGO && !inst_at(PCsave) && analyzer)
+            analyze(PCsave);
+	}
+
       post_inst();
 
-      if ((res == resGO) &&
-	  irq)
+      if ((res == resGO) && (PC == PCsave) && stop_selfjump)
+	{
+	  res= resSELFJUMP;
+	  sim->stop(res);
+	  break;
+	}
+      
+      if ((res == resGO || res == resNOT_DONE) &&
+	  1/*irq*/)
 	{
-	  //printf("DO INTERRUPT PC=%lx\n", PC);
 	  int r= do_interrupt();
 	  if (r != resGO)
 	    res= r;
@@ -2165,7 +2748,7 @@
 	  res= resBREAKPOINT;
 	}
     }
-  if (res != resGO)
+  if (res != resGO && res != resNOT_DONE)
     sim->stop(res);
   return(res);
 }
@@ -2174,7 +2757,6 @@
 cl_uc::pre_inst(void)
 {
   inst_exec= true;
-  inst_ticks= 0;
   events->disconn_all();
   vc.inst++;
 }
@@ -2199,13 +2781,14 @@
       PC= instPC;
       return resNOT_DONE;
     }
+  tickt(c);
   res= itab[c](this, c);
   if (res == resNOT_DONE)
     {
       PC= instPC;
       return res;
     }
-  tick(1);
+  //tick(1);
   return res;
 }
 
@@ -2213,7 +2796,6 @@
 void
 cl_uc::post_inst(void)
 {
-  tick_hw(inst_ticks);
   if (errors->count)
     check_errors();
   if (events->count)
@@ -2222,6 +2804,33 @@
 }
 
 
+static FILE *pc_dump= NULL;
+
+void
+cl_uc::save_hist()
+{
+  if (juj & 1)
+    {
+      if (pc_dump==NULL) pc_dump= fopen("addr.txt","w");
+      if (pc_dump!=NULL)
+	{
+	  fprintf(pc_dump,"0x%06x\n",AU(PC));
+	  fflush(pc_dump);
+	}
+    }
+  hist->put();
+}
+
+int
+cl_uc::inst_unknown(t_mem code)
+{
+  //PC--;
+  class cl_error_unknown_code *e= new cl_error_unknown_code(this);
+  error(e);
+  return(resGO);
+}
+
+
 /*
  * Interrupt processing
  */
@@ -2230,38 +2839,56 @@
 cl_uc::do_interrupt(void)
 {
   int i;
-  // NMI?
+  bool is_en= it_enabled();
+  class it_level *il= (class it_level *)(it_levels->top()), *IL= 0;
 
-  // Maskable interrupts
-  if (!it_enabled())
+  irq= false;
+  for (i= 0; i < it_sources->count; i++)
     {
-      //printf("do_interrupt skip (it disabled)\n");
-      return resGO;
+      class cl_it_src *is= (class cl_it_src *)(it_sources->at(i));
+      is->pass_over();
     }
-  class it_level *il= (class it_level *)(it_levels->top()), *IL= 0;
-  irq= false;
-  //printf("Checking IRQs...\n");
   for (i= 0; i < it_sources->count; i++)
     {
       class cl_it_src *is= (class cl_it_src *)(it_sources->at(i));
-       if (is->is_active() &&
-	  is->enabled() &&
-	  is->pending())
+      if (is->is_slave())
+	{
+	  continue;
+	}
+      if (!is->is_nmi())
+	{
+	  if (!is_en)
+	    {
+	      continue;
+	    }
+	}
+      bool A= is->is_active();
+      bool E= is->enabled();
+      bool P= is->pending();
+      if (A && E && P)
 	{
 	  int pr= priority_of(is->nuof);
 	  int ap;
 	  irq= true;
 	  if (il &&
 	      il->level >= 0)
-	    ap= il->level;
+	    {
+	      ap= il->level;
+	    }
 	  else
-	    ap= priority_main();
+	    {
+	      ap= priority_main();
+	    }
 	  if (ap >= pr)
-	    continue;
+	    {
+	      continue;
+	    }
+	  if (state == stIDLE)
+	    state= stGO;
 	  is->clear();
 	  sim->app->get_commander()->
 	    debug("%g sec (%d clks): Accepting interrupt `%s' PC= 0x%06x\n",
-			  get_rtime(), ticks->ticks, object_name(is), PC);
+			  ticks->get_rtime(), ticks->get_ticks(), object_name(is), PC);
 	  IL= new it_level(pr, is->addr, PC, is);
 	  return(accept_it(IL));
 	}
@@ -2276,21 +2903,31 @@
   return resGO;
 }
 
+class cl_it_src *
+cl_uc::search_it_src(int cid_or_nr)
+{
+  class cl_it_src *it;
+  int i;
+  for (i= 0; iget_count(); i++)
+    {
+      it= (class cl_it_src *)(it_sources->at(i));
+      if (it &&
+	  (
+	   (it->cid != 0 && it->cid == cid_or_nr) ||
+	   (it->cid != 0 && toupper(it->cid) == toupper(cid_or_nr)) ||
+	   (it->nuof == cid_or_nr)
+	   )
+	  )
+	return it;
+    }
+  return NULL;
+}
 
+  
 /*
  * Time related functions
  */
 
-double
-cl_uc::get_rtime(void)
-{
-  /*  double d;
-
-  d= (double)ticks/xtal;
-  return(d);*/
-  return(ticks->get_rtime(xtal));
-}
-
 unsigned long
 cl_uc::clocks_of_time(double t)
 {
@@ -2323,6 +2960,7 @@
 void
 cl_uc::stack_write(class cl_stack_op *op)
 {
+  stack_check_overflow(op);
   delete op;
   return ;
   if (op->get_op() & stack_read_operation)
@@ -2418,6 +3056,12 @@
   delete op;
 }
 
+void
+cl_uc::stack_check_overflow(class cl_stack_op *op)
+{
+}
+
+  
 /*
  * Breakpoint handling
  */
@@ -2592,18 +3236,17 @@
 void
 cl_error_unknown_code::print(class cl_commander_base *c)
 {
-  //FILE *f= c->get_out();
-  /*cmd_fprintf(f,*/c->dd_printf("%s: unknown instruction code at ", get_type_name());
+  c->dd_printf("%s: unknown instruction code at ", get_type_name());
   if (uc->rom)
     {
-      /*cmd_fprintf(f,*/c->dd_printf(uc->rom->addr_format, PC);
-      /*cmd_fprintf(f,*/c->dd_printf(" (");
-      /*cmd_fprintf(f,*/c->dd_printf(uc->rom->data_format, uc->rom->get(PC));
-      /*cmd_fprintf(f,*/c->dd_printf(")");
+      c->dd_printf(uc->rom->addr_format, PC);
+      c->dd_printf(" (");
+      c->dd_printf(uc->rom->data_format, uc->rom->get(PC));
+      c->dd_printf(")");
     }
   else
-    /*cmd_fprintf(f,*/c->dd_printf("0x%06x", AU(PC));
-  /*cmd_fprintf(f,*/c->dd_printf("\n");
+    c->dd_printf("0x%06x", AU(PC));
+  c->dd_printf("\n");
 }
 
 
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/sim.src/uccl.h sdcc-4.2.0+dfsg/sim/ucsim/sim.src/uccl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/sim.src/uccl.h	2019-02-26 14:40:39.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/sim.src/uccl.h	2022-02-02 07:12:49.000000000 +0000
@@ -47,24 +47,34 @@
 
 /* Counter to count clock ticks */
 
-#define TICK_RUN	0x01
-#define TICK_INISR	0x02
-#define TICK_IDLE	0x03
+enum ticker_type {
+   TICK_ANY = 0,
+   TICK_INISR,
+   TICK_IDLE,
+   TICK_HALT
+};
 
 class cl_ticker: public cl_base
 {
-public:
+private:
+  enum ticker_type type;
+  double rtime;
   unsigned long ticks;
-  int options; // see TICK_XXX above
+public:
   int dir;
-  //char *name;
+  bool run, user;
 
-  cl_ticker(int adir, int in_isr, const char *aname);
+  cl_ticker(int adir, enum ticker_type type, const char *aname, bool auser = true);
   virtual ~cl_ticker(void);
-  
-  virtual int tick(int nr);
-  virtual double get_rtime(double xtal);
-  virtual void dump(int nr, double xtal, class cl_console_base *con);
+
+  enum ticker_type get_type(void) { return type; }
+  unsigned long get_ticks(void) { return ticks; }
+  double get_rtime(void) { return rtime; }
+
+  void set(int nr, double time) { ticks = nr; rtime = time; }
+
+  void tick(int nr, double time);
+  void dump(int nr, class cl_console_base *con);
 };
 
 
@@ -78,6 +88,26 @@
   virtual void option_changed(void);
 };
 
+class cl_stop_selfjump_option: public cl_optref
+{
+protected:
+  class cl_uc *uc;
+public:
+  cl_stop_selfjump_option(class cl_uc *the_uc);
+  virtual int init(void);
+  virtual void option_changed(void);
+};
+
+class cl_analyzer_option: public cl_optref
+{
+protected:
+  class cl_uc *uc;
+public:
+  cl_analyzer_option(class cl_uc *the_uc);
+  virtual int init(void);
+  virtual void option_changed(void);
+};
+
 struct vcounter_t {
   t_mem inst;
   t_mem fetch;
@@ -166,28 +196,60 @@
 {
  public:
  cl_cdb_recs(): cl_sorted_list(2,2,"cdb_recs_list") {}
-  virtual void *key_of(void *item)
-  { return (char*)(((cl_cdb_rec *)item)->fname); }
-  virtual int compare(void *k1, void *k2) {
-    return strcmp((char*)k1,(char*)k2);
+  virtual const void *key_of(const void *item) const
+  { return (((const cl_cdb_rec *)item)->fname); }
+  virtual int compare(const void *k1, const void *k2) {
+    return strcmp((const char*)k1,(const char*)k2);
   }
   virtual cl_cdb_rec *rec(chars n) {
     t_index i;
-    if (search((char*)n, i))
+    if (search(n, i))
       return (cl_cdb_rec*)(at(i));
     return NULL;
   }
   virtual void del(chars n) {
     t_index i;
-    if (search((char*)n,i))
+    if (search(n,i))
       free_at(i);
   }
 };
 
+struct t_hist_elem
+{
+  int nr;
+  t_addr addr;
+};
+
+class cl_exec_hist: public cl_base
+{
+protected:
+  int len;
+  int h, t;
+  struct t_hist_elem *hist;
+  class cl_uc *uc;
+public:
+  cl_exec_hist(class cl_uc *auc);
+  virtual ~cl_exec_hist(void);
+  virtual int init(void);
+  virtual void put(void);
+  virtual void list(class cl_console_base *con, bool inc, int nr);
+  virtual void clear() { keep(0); }
+  virtual void keep(int nr);
+  
+  virtual int get_len(void) { return len-1; }
+  virtual int get_used();
+  virtual unsigned int get_insts();
+};
+  
+
 /* Abstract microcontroller */
 
 class cl_uc: public cl_base
 {
+private:
+  double xtal;			// Clock speed
+  double xtal_tick;		// Length of a clock tick in seconds
+  unsigned int label_index;	// Counter for labels auto-generated by analyze
 public:
   struct cpu_entry *type;
   //enum cpu_type type;			// CPU family
@@ -195,16 +257,19 @@
   int state;			// GO, IDLE, PD
   //class cl_list *options;
   class cl_xtal_option *xtal_option;
-
+  class cl_stop_selfjump_option *stop_selfjump_option;
+  class cl_analyzer_option *analyzer_option;
+  
   t_addr PC, instPC;		// Program Counter
   bool inst_exec;		// Instruction is executed
   class cl_ticker *ticks;	// Nr of XTAL clocks
   class cl_ticker *isr_ticks;	// Time in ISRs
   class cl_ticker *idle_ticks;	// Time in idle mode
+  class cl_ticker *halt_ticks;	// Time in power down mode
   class cl_list *counters;	// User definable timers (tickers)
-  int inst_ticks;		// ticks of an instruction
-  double xtal;			// Clock speed
   struct vcounter_t vc;		// Virtual clk counter
+  bool stop_selfjump;		// Whether it should stop on selfjump
+  bool analyzer;		// Whether the code analyzer is enabled
   
   int brk_counter;		// Number of breakpoints
   class brk_coll *fbrk;		// Collection of FETCH break-points
@@ -215,10 +280,11 @@
  public:
   class cl_hw *cpu;
   class cl_hws *hws;
+  class cl_exec_hist *hist;
 
  public:
-  class cl_list *memchips;      // v3
-  class cl_address_space_list *address_spaces;
+  class cl_memory_list *memchips;      // v3
+  class cl_memory_list *address_spaces;
   class cl_address_space *rom;  // Required for almost every uc
   //class cl_list *address_decoders;
   class cl_address_space *variables;
@@ -235,12 +301,22 @@
   t_addr sp_max;
   t_addr sp_avg;
 
+  bool vcd_break;
+
 public:
   cl_uc(class cl_sim *asim);
   virtual ~cl_uc(void);
   virtual int init(void);
-  virtual char *id_string(void);
+  virtual const char *id_string(void);
   virtual void reset(void);
+  virtual void set_PC(t_addr addr) { PC= addr; }
+  virtual void reg_cell_var(class cl_memory_cell *cell,
+			    void *store,
+			    chars vname, chars vdesc);
+
+  double get_xtal(void) { return xtal; }
+  double get_xtal_tick(void) { return xtal_tick; }
+  void set_xtal(double freq) { xtal= freq; xtal_tick = 1 / freq; }
 
   // making objects
   virtual void make_memories(void);
@@ -250,27 +326,32 @@
   virtual void build_cmdset(class cl_cmdset *cmdset);
 
   // manipulating memories
-  virtual t_mem read_mem(char *id, t_addr addr);
-  virtual t_mem get_mem(char *id, t_addr addr);
-  virtual void write_mem(char *id, t_addr addr, t_mem val);
-  virtual void set_mem(char *id, t_addr addr, t_mem val);
+  virtual t_mem read_mem(const char *id, t_addr addr);
+  virtual t_mem get_mem(const char *id, t_addr addr);
+  virtual void write_mem(const char *id, t_addr addr, t_mem val);
+  virtual void set_mem(const char *id, t_addr addr, t_mem val);
   virtual class cl_address_space *address_space(const char *id);
   virtual class cl_address_space *address_space(class cl_memory_cell *cell);
   virtual class cl_address_space *address_space(class cl_memory_cell *cell, t_addr *addr);
   virtual class cl_memory *memory(const char *id);
-
+  virtual void remove_chip(class cl_memory *chip);
+  
   // file handling
   virtual void set_rom(t_addr addr, t_mem val);
   virtual long read_hex_file(const char *nam);
   virtual long read_hex_file(cl_console_base *con);
   virtual long read_hex_file(cl_f *f);
   virtual long read_omf_file(cl_f *f);
+  virtual long read_asc_file(cl_f *f);
   virtual long read_cdb_file(cl_f *f);
   virtual cl_f *find_loadable_file(chars nam);
   virtual long read_file(chars nam, class cl_console_base *con);
   
   // instructions, code analyzer
-  virtual void analyze(t_addr addr) {}
+  void analyze_init(void);
+  virtual void analyze_start(void);
+  virtual void analyze(t_addr addr);
+  virtual void analyze_jump(t_addr addr, t_addr target, char type, unsigned int bit = 0);
   virtual bool inst_at(t_addr addr);
   virtual void set_inst_at(t_addr addr);
   virtual void del_inst_at(t_addr addr);
@@ -281,47 +362,55 @@
   virtual int nuof_hws(void);
   virtual class cl_hw *get_hw(int idx);
   virtual class cl_hw *get_hw(enum hw_cath cath, int *idx);
-  virtual class cl_hw *get_hw(char *id_string, int *idx);
+  virtual class cl_hw *get_hw(const char *id_string, int *idx);
   virtual class cl_hw *get_hw(enum hw_cath cath, int hwid, int *idx);
-  virtual class cl_hw *get_hw(char *id_string, int hwid, int *idx);
+  virtual class cl_hw *get_hw(const char *id_string, int hwid, int *idx);
   virtual int get_max_hw_id(enum hw_cath cath);
   
   // "virtual" timers
   virtual int tick_hw(int cycles);
   virtual void do_extra_hw(int cycles);
   virtual int tick(int cycles);
+  virtual int8_t *tick_tab(t_mem code) { return NULL; }
+  virtual int tickt(t_mem code);
   virtual class cl_ticker *get_counter(int nr);
   virtual class cl_ticker *get_counter(const char *nam);
   virtual void add_counter(class cl_ticker *ticker, int nr);
   virtual void add_counter(class cl_ticker *ticker, const char *nam);
   virtual void del_counter(int nr);
   virtual void del_counter(const char *nam);
-  virtual double get_rtime(void);
   virtual unsigned long clocks_of_time(double t);
   virtual int clock_per_cycle(void);
   virtual void touch(void);
   
   // execution
+  virtual bool do_brk(void);
   virtual t_mem fetch(void);
+  virtual u8_t fetch8(void) { return (u8_t)fetch(); }
+  virtual i8_t fetchi8(void) { return (i8_t)fetch(); }
   virtual bool fetch(t_mem *code);
   virtual int do_inst(int step);
   virtual void pre_inst(void);
   virtual int exec_inst(void);
   virtual int exec_inst_tab(instruction_wrapper_fn itab[]);
   virtual void post_inst(void);
-
+  virtual void save_hist();
+  virtual int inst_unknown(t_mem code);
+  
   virtual int do_interrupt(void);
   virtual int priority_of(uchar nuof_it) {return(0);}
   virtual int priority_main() { return 0; }
   virtual int accept_it(class it_level *il);
   virtual bool it_enabled(void) { return false; }
-
+  virtual class cl_it_src *search_it_src(int cid_or_nr);
+  
 #include "uccl_instructions.h"
   
   // stack tracking
   virtual void stack_write(class cl_stack_op *op);
   virtual void stack_read(class cl_stack_op *op);
-
+  virtual void stack_check_overflow(class cl_stack_op *op);
+  
   // breakpoints
   virtual class cl_fetch_brk *fbrk_at(t_addr addr);
   virtual class cl_ev_brk *ebrk_at(t_addr addr, char *id);
@@ -339,32 +428,50 @@
   virtual void stop_when(class cl_time_measurer *t);
   
   // disassembling and symbol recognition
-  virtual char *disass(t_addr addr, const char *sep);
+  virtual char *disass(t_addr addr);
+  virtual char *disassc(t_addr addr, chars *comment= NULL) { return disass(addr); }
   virtual struct dis_entry *dis_tbl(void);
-  virtual void print_disass(t_addr addr, class cl_console_base *con);
+  virtual int print_disass(t_addr addr, class cl_console_base *con, bool nl);
+  virtual int print_disass(t_addr addr, class cl_console_base *con);
   virtual void print_regs(class cl_console_base *con);
   virtual int inst_length(t_addr addr);
   virtual int inst_branch(t_addr addr);
   virtual bool is_call(t_addr addr);
   virtual int longest_inst(void);
-  virtual bool addr_name(t_addr addr, class cl_address_space *as, char *buf);
-  virtual bool addr_name(t_addr addr, class cl_address_space *as, int bitnr, char *buf);
+  virtual const class cl_var *addr_name(t_addr addr,
+					class cl_memory *mem,
+					int bitnr_high,
+					int bitnr_low,
+					chars *buf,
+					const class cl_var *context/* = 0*/);
+  const class cl_var *addr_name(t_addr addr,
+				class cl_memory *mem,
+				int bitnr,
+				chars *buf,
+				const class cl_var *context/* = 0*/)
+  {
+    return addr_name(addr, mem, bitnr, bitnr, buf, context);
+  }
+  const class cl_var *addr_name(t_addr addr,
+				class cl_memory *mem,
+				chars *buf)
+  {
+    return addr_name(addr, mem, -1, -1, buf, NULL);
+  }
   virtual bool symbol2address(char *sym,
-			      class cl_address_space **as,
+			      class cl_memory **mem,
 			      t_addr *addr);
-  virtual char *symbolic_bit_name(t_addr bit_address,
-				  class cl_memory *mem,
-				  t_addr mem_addr,
-				  t_mem bit_mask);
   virtual name_entry *get_name_entry(struct name_entry tabl[],
 				     char *name);
-  virtual chars cell_name(class cl_memory_cell *cell);
-  virtual class cl_var *var(char *nam);
+  virtual chars cell_name(class cl_memory_cell *cell, int bitnr_high, int bitnr_low);
+  virtual chars cell_name(class cl_memory_cell *cell) { return cell_name(cell, -1, -1); }
+  virtual t_addr read_addr(class cl_memory *m, t_addr start_addr);
   
   /* Converting abstract address spaces into real ones */
   virtual class cl_address_space *bit2mem(t_addr bitaddr,
 					  t_addr *memaddr,
-					  t_mem *bitmask);
+					  int *bitnr_high,
+					  int *bitnr_low);
   virtual t_addr bit_address(class cl_memory *mem,
                              t_addr mem_address,
                              int bit_number) { return(-1); }
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/sim.src/var.cc sdcc-4.2.0+dfsg/sim/ucsim/sim.src/var.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/sim.src/var.cc	2019-02-07 18:28:18.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/sim.src/var.cc	2022-01-24 11:09:43.000000000 +0000
@@ -27,82 +27,564 @@
 */
 /*@1@*/
 
+#include 
+#include 
+
 #include "varcl.h"
 
 
-cl_var::cl_var(const char *iname, class cl_address_space *ias, t_addr iaddr, chars adesc, int ibitnr):
+/* Cell only variable */
+
+cl_cvar::cl_cvar(chars iname, class cl_memory_cell *icell, chars adesc, int ibitnr_high, int ibitnr_low):
   cl_base()
 {
-  as= ias;
-  addr= iaddr;
-  bitnr= ibitnr;
+  if (ibitnr_low < ibitnr_high)
+    {
+      bitnr_low= ibitnr_low;
+      bitnr_high= ibitnr_high;
+    }
+  else
+    {
+      bitnr_low= ibitnr_high;
+      bitnr_high= ibitnr_low;
+    }
   desc= adesc;
   
   set_name(iname);
   
-  cell= NULL;
+  cell= icell;
 }
 
 int
-cl_var::init(void)
+cl_cvar::init(void)
 {
-  if (!as ||
-      !as->is_address_space() ||
-      !as->valid_address(addr))
-    return 0;
-  cell= as->get_cell(addr);
-  if (cell && (bitnr < 0))
-    cell->set_flag(CELL_VAR, true);
   return 0;
 }
 
+t_mem
+cl_cvar::write(t_mem val)
+{
+  if (!cell)
+    return 0;
+  return cell->write(val);
+}
+
+t_mem
+cl_cvar::read()
+{
+  if (!cell)
+    return 0;
+  return cell->read();
+}
+
+t_mem
+cl_cvar::set(t_mem val)
+{
+  if (!cell)
+    return 0;
+  return cell->set(val);
+}
 
 void
-cl_var::print_info(cl_console_base *con)
+cl_cvar::print_info(cl_console_base *con) const
 {
   con->dd_printf("%s ", get_name("?"));
-  if (cell)
+  t_mem m= cell->get();
+  if (bitnr_high >= 0)
     {
-      t_mem v= cell->read();
-      con->dd_printf("%s", as->get_name("?"));
-      con->dd_printf("[");
-      con->dd_printf(as->addr_format, addr);
-      con->dd_printf("] ");
-      if (bitnr >= 0)
-	{
-	  con->dd_printf(".%d", bitnr);
-	  con->dd_printf("= %d", (v & (1<dd_printf("[%u:%u] = 0b", bitnr_high, bitnr_low);
+          for (int i= bitnr_high; i >= bitnr_low; i--)
+            con->dd_printf("%c", (m & (1U << i)) ? '1' : '0');
+          m &= ((1U << (bitnr_high - bitnr_low + 1)) - 1) << bitnr_low;
+        }
       else
-	{
-	  con->dd_printf("= ");
-	  con->dd_printf(as->data_format, v);
-	}
+        {
+          m &= (1U << bitnr_low);
+          con->dd_printf(".%u = %c", bitnr_low, m ? '1' : '0');
+        }
     }
+  else
+    {
+      con->dd_printf(" = 0x");
+      con->dd_printf(/*mem->data_format*/"%08x", m);
+    }
+  con->dd_printf(",%uU", MU(m));
+  con->dd_printf(",%d", MI(m));
+  if ((MU(m) < 0x100) && isprint(MI(m)))
+    con->dd_printf(",'%c'", MI(m));
   con->dd_printf("\n");
-  if (!desc.empty())
-    con->dd_printf("  %s\n", (char*)desc);
+  if (desc && desc[0])
+    con->dd_printf("  %s\n", desc.c_str());
 }
 
 
-void *
-cl_var_list::key_of(void *item)
+/* Variable pointing to memory location */
+
+cl_var::cl_var(chars iname, class cl_memory *imem, t_addr iaddr, chars adesc, int ibitnr_high, int ibitnr_low):
+  cl_cvar(iname, NULL, adesc, ibitnr_high, ibitnr_low)
 {
-  class cl_var *v= (class cl_var *)item;
-  return (void*)v->get_name();
+  mem= imem;
+  addr= iaddr;
 }
 
 int
-cl_var_list::compare(void *key1, void *key2)
+cl_var::init(void)
+{
+  if (!mem ||
+      !mem->is_address_space() ||
+      !mem->valid_address(addr))
+    return 0;
+  cell= static_cast(mem)->get_cell(addr);
+  return 0;
+}
+
+void
+cl_var::print_info(cl_console_base *con) const
+{
+  con->dd_printf("%s ", get_name("?"));
+  con->dd_printf("%s", mem->get_name("?"));
+  con->dd_printf("[");
+  con->dd_printf(mem->addr_format, addr);
+  con->dd_printf("]");
+  t_mem m= mem->get(addr);
+  if (bitnr_high >= 0)
+    {
+      if (bitnr_high != bitnr_low)
+        {
+          con->dd_printf("[%u:%u] = 0b", bitnr_high, bitnr_low);
+          for (int i= bitnr_high; i >= bitnr_low; i--)
+            con->dd_printf("%c", (m & (1U << i)) ? '1' : '0');
+          m &= ((1U << (bitnr_high - bitnr_low + 1)) - 1) << bitnr_low;
+        }
+      else
+        {
+          m &= (1U << bitnr_low);
+          con->dd_printf(".%u = %c", bitnr_low, m ? '1' : '0');
+        }
+    }
+  else
+    {
+      con->dd_printf(" = 0x");
+      con->dd_printf(mem->data_format, m);
+    }
+  con->dd_printf(",%uU", MU(m));
+  con->dd_printf(",%d", MI(m));
+  if ((MU(m) < 0x100) && isprint(MI(m)))
+    con->dd_printf(",'%c'", MI(m));
+  con->dd_printf("\n");
+  if (desc && desc[0])
+    con->dd_printf("  %s\n", desc.c_str());
+}
+
+
+cl_var_by_name_list::~cl_var_by_name_list(void)
+{
+}
+
+const void *
+cl_var_by_name_list::key_of(const void *item) const
 {
-  char *k1, *k2;
+  return static_cast(item)->get_name();
+}
 
-  k1= (char*)key1;
-  k2= (char*)key2;
-  if (k1 && k2)
-    return strcmp(k1, k2);
+int
+cl_var_by_name_list::compare(const void *key1, const void *key2)
+{
+  if (key1 && key2)
+    return strcmp(static_cast(key1), static_cast(key2));
   return 0;
 }
 
 
+cl_var_by_addr_list::~cl_var_by_addr_list(void)
+{
+}
+
+int
+cl_var_by_addr_list::compare_addr(class cl_var *var, class cl_memory *mem, t_addr addr)
+{
+  int ret;
+  class cl_memory *vmem= var->get_mem();
+  t_addr vaddr= var->get_addr();
+  if (!vmem)
+    return 0;
+  
+  if (!(ret = vmem->get_uid() - mem->get_uid()))
+    ret = vaddr - addr;
+
+  return ret;
+}
+
+int
+cl_var_by_addr_list::compare_addr_and_bits(class cl_var *var, class cl_memory *mem, t_addr addr, int bitnr_high, int bitnr_low)
+{
+  int ret;
+  class cl_memory *vmem= var->get_mem();
+  t_addr vaddr= var->get_addr();
+  if (!vmem)
+    return 0;
+  
+  if (!(ret = vmem->get_uid() - mem->get_uid()) &&
+     !(ret = vaddr - addr) &&
+     (!(ret = (var->bitnr_high < 0
+               ? (bitnr_high < 0 ? 0 : -1)
+               : (bitnr_high < 0
+                  ? 1
+                  : bitnr_high - var->bitnr_high)))))
+    ret = (var->bitnr_low < 0
+           ? (bitnr_low < 0 ? 0 : -1)
+           : (bitnr_low < 0
+              ? 1
+              : var->bitnr_low - bitnr_low));
+
+  return ret;
+}
+
+int
+cl_var_by_addr_list::compare(const void *key1, const void *key2)
+{
+  class cl_var *k1 = (cl_var*)(key1);
+  class cl_var *k2 = (cl_var*)(key2);
+  int ret;
+
+  // An addr may have multiple names as long as they are all different.
+  if (!(ret = compare_addr_and_bits(k1, k2->get_mem(), k2->get_addr(), k2->bitnr_high, k2->bitnr_low)))
+    ret = strcmp(k1->get_name(), k2->get_name());
+
+  return ret;
+}
+
+bool
+cl_var_by_addr_list::search(class cl_memory *mem, t_addr addr, t_index &index)
+{
+  t_index l  = 0;
+  t_index h  = count - 1;
+  bool    res= false;
+
+  while (l <= h)
+    {
+      t_index i= (l + h) >> 1;
+      t_index c= compare_addr((cl_var *)(key_of(Items[i])), mem, addr);
+      if (c < 0) l= i + 1;
+      else
+        {
+          h= i - 1;
+          if (c == 0)
+            {
+              res= true;
+              // We want the _first_ name for the given addr.
+              for (l = i; l > 0 && !compare_addr((cl_var *)(key_of(Items[l-1])), mem, addr); l--);
+            }
+        }
+    }
+
+  index= l;
+  return(res);
+}
+
+bool
+cl_var_by_addr_list::search(class cl_memory *mem, t_addr addr, int bitnr_high, int bitnr_low, t_index &index)
+{
+  t_index l  = 0;
+  t_index h  = count - 1;
+  bool    res= false;
+
+  while (l <= h)
+    {
+      t_index i= (l + h) >> 1;
+      t_index c= compare_addr_and_bits((cl_var *)(key_of(Items[i])), mem, addr, bitnr_high, bitnr_low);
+      if (c < 0) l= i + 1;
+      else
+        {
+          h= i - 1;
+          if (c == 0)
+            {
+              res= true;
+              // We want the _first_ name for the given addr.
+              for (l = i; l > 0 && !compare_addr_and_bits((cl_var *)(key_of(Items[l-1])), mem, addr, bitnr_high, bitnr_low); l--);
+            }
+        }
+    }
+
+  index= l;
+  return(res);
+}
+
+size_t
+cl_var_list::get_max_name_len(void)
+{
+  if (!max_name_len_known)
+    {
+      max_name_len = 0;
+
+      for (t_index i = 0; i < by_name.count; i++)
+        {
+          size_t l = strlen(by_name.at(i)->get_name());
+          if (l > max_name_len)
+            max_name_len = l;
+        }
+
+      max_name_len_known = true;
+    }
+
+  return max_name_len;
+}
+
+bool
+cl_var_list::del(const char *name)
+{
+  t_index name_i;
+  bool found = by_name.search(name, name_i);
+
+  if (found)
+    {
+      cl_cvar *var = by_name.at(name_i);
+
+      by_addr.disconn(var);
+      by_name.disconn_at(name_i);
+      delete var;
+
+      max_name_len_known = false;
+    }
+
+  return found;
+}
+
+class cl_cvar *
+cl_var_list::add(class cl_cvar *item)
+{
+  const char *name = item->get_name();
+
+  if (!del(name))
+    {
+      size_t l = strlen(name);
+      if (l > max_name_len)
+        max_name_len = l;
+    }
+  else
+    {
+      // We're replacing with the same name so we still know the max length really
+      max_name_len_known = true;
+    }
+
+  by_name.add(item);
+  if (item->is_mem_var())
+    {
+      class cl_var *var = static_cast(item);
+
+      // If analyze put a variable at this location in the past it is no
+      // longer needed and can be removed.
+      t_index i;
+      if (by_addr.search(var->get_mem(), var->get_addr(), var->bitnr_high, var->bitnr_low, i))
+        {
+          class cl_var *v;
+          while (i < by_addr.count && (v = by_addr.at(i)) &&
+                 v->get_mem() == var->get_mem() && v->get_addr() == var->get_addr() &&
+                 v->bitnr_high == var->bitnr_high && v->bitnr_low == var->bitnr_low)
+            {
+              if (*(v->get_name()) == '.')
+                {
+                  by_addr.disconn_at(i);
+                  by_name.disconn(v);
+
+                  if (strlen(v->get_name()) == max_name_len &&
+                      strlen(item->get_name()) < max_name_len)
+                    max_name_len_known = false;
+
+                  delete v;
+
+                  // There should be at most 1.
+                  break;
+                }
+
+                i++;
+            }
+        }
+
+      by_addr.add(item);
+    }
+
+  return item;
+}
+
+class cl_cvar *
+cl_var_list::add(chars name, class cl_memory *mem, t_addr addr, int bitnr_high, int bitnr_low, chars desc)
+{
+  class cl_cvar *var;
+
+  var = new cl_var(name, mem, addr, desc, bitnr_high, bitnr_low);
+  var->init();
+  return add(var);
+}
+
+class cl_cvar *
+cl_var_list::add(chars name, const char *cellname, int bitnr_high, int bitnr_low, chars desc)
+{
+  int i;
+  if (by_name.search(cellname, i))
+    {
+      class cl_cvar *var = (cl_var*)by_name.at(i);
+      return add(name, var->get_mem(), var->get_addr(), bitnr_high, bitnr_low, desc);
+    }
+
+  return NULL;
+}
+
+void
+cl_var_list::add(chars prefix, class cl_memory *mem, t_addr base, const struct var_def *def, size_t n)
+{
+  chars regname = chars("");
+  t_addr offset = 0;
+
+  for (; n; def++, n--)
+    {
+      class cl_var *var;
+
+      if (def->bitnr_high < 0)
+        {
+          regname = prefix + def->name;
+
+          if (def->bitnr_low < 0)
+            {
+              offset = -1;
+
+              int i;
+              if (by_name.search(regname, i))
+                {
+                  cl_var *var = (cl_var*)by_name.at(i);
+                  if (var->get_mem() == mem)
+                    offset = var->get_addr() - base;
+                }
+            }
+          else
+            {
+              offset = def->bitnr_low;
+
+              var = new cl_var(regname, mem, base + offset, def->desc, -1, -1);
+              var->init();
+              add(var);
+
+              regname += "_";
+            }
+        }
+      else if (mem && offset >= 0)
+        {
+          var = new cl_var(regname + def->name, mem, base + offset, def->desc, def->bitnr_high, def->bitnr_low);
+          var->init();
+          add(var);
+        }
+    }
+}
+
+t_mem
+cl_var_list::read(chars name)
+{
+  bool found;
+  t_index i;
+  class cl_cvar *v;
+  found= by_name.search(name, i);
+  if (found)
+    {
+      v= by_name.at(i);
+      return v->read();
+    }
+  return 0;
+}
+
+int
+cl_vars_iterator::compare_bits(const class cl_var *var1, const class cl_var *var2)
+{
+  int ret;
+
+  if ((!(ret = (var1->bitnr_high < 0
+               ? (var2->bitnr_high < 0 ? 0 : -1)
+               : (var2->bitnr_high < 0
+                  ? 1
+                  : var2->bitnr_high - var1->bitnr_high)))))
+    ret = (var1->bitnr_low < 0
+           ? (var2->bitnr_low < 0 ? 0 : -1)
+           : (var2->bitnr_low < 0
+              ? 1
+              : var1->bitnr_low - var2->bitnr_low));
+
+  return ret;
+}
+const cl_var *
+cl_vars_iterator::first(cl_memory *mem, t_addr addr)
+{
+  const cl_var *space_var = NULL;
+  space_mem = mem;
+  space_addr = addr;
+
+
+  if (vars->by_addr.search(space_mem, space_addr, space_i))
+    space_var = vars->by_addr.at(space_i);
+
+  const cl_var *chip_var = NULL;
+  chip_mem = NULL;
+
+  cl_address_decoder *ad;
+  if (space_mem->is_address_space() &&
+      (ad = ((cl_address_space *)space_mem)->get_decoder_of(space_addr)))
+    {
+      chip_mem = ad->memchip;
+      chip_addr = ad->as_to_chip(space_addr);
+
+      if (vars->by_addr.search(chip_mem, chip_addr, chip_i))
+        chip_var = vars->by_addr.at(chip_i);
+    }
+
+  if (chip_var && (!space_var || compare_bits(chip_var, space_var) < 0))
+    {
+      chip_i++;
+      return chip_var;
+    }
+
+  space_i++;
+  return space_var;
+}
+
+const cl_var *
+cl_vars_iterator::next(void)
+{
+  const cl_var *space_var = NULL;
+  const cl_var *chip_var = NULL;
+
+  if (space_i >= 0 && space_i < vars->by_addr.count)
+    {
+      space_var = vars->by_addr.at(space_i);
+      if (space_var->get_mem() != space_mem || space_var->get_addr() != space_addr)
+        {
+          space_i = -1;
+          space_var = NULL;
+        }
+    }
+
+  if (chip_i >= 0 && chip_i < vars->by_addr.count)
+    {
+      chip_var = vars->by_addr.at(chip_i);
+      if (chip_var->get_mem() != chip_mem || chip_var->get_addr() != chip_addr)
+        {
+          chip_i = -1;
+          chip_var = NULL;
+        }
+    }
+
+  if (chip_var && (!space_var || compare_bits(chip_var, space_var) < 0))
+    {
+      chip_i++;
+      return chip_var;
+    }
+
+  if (space_var)
+    {
+      space_i++;
+      return space_var;
+    }
+
+  return NULL;
+}
+
 /* End of sim.src/var.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/sim.src/varcl.h sdcc-4.2.0+dfsg/sim/ucsim/sim.src/varcl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/sim.src/varcl.h	2019-02-07 18:28:18.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/sim.src/varcl.h	2022-01-27 21:35:29.000000000 +0000
@@ -38,33 +38,158 @@
 #include "memcl.h"
 
 
-class cl_var: public cl_base
+class cl_cvar: public cl_base
 {
  public:
-  class cl_address_space *as; // reference
-  t_addr addr;
-  int bitnr;
+  int bitnr_high, bitnr_low;
   chars desc;
  protected:
   class cl_memory_cell *cell;
  public:
-  cl_var(const char *iname, class cl_address_space *ias, t_addr iaddr, chars adesc, int ibitnr= -1);
+  cl_cvar(chars iname, class cl_memory_cell *icell, chars adesc, int ibitnr_high= -1, int ibitnr_low= -1);
   virtual int init(void);
-  virtual class cl_memory_cell *get_cell(void) { return cell; }
-  
-  virtual void print_info(cl_console_base *con);
+  virtual class cl_memory_cell *get_cell(void) const { return cell; }
+  virtual class cl_memory *get_mem() const { return NULL; }
+  virtual t_addr get_addr() const { return 0; }
+  virtual bool is_mem_var() const { return false; }
+
+  virtual t_mem write(t_mem val);
+  virtual t_mem read();
+  virtual t_mem set(t_mem val);
+
+  virtual void print_info(cl_console_base *con) const;
+};
+
+class cl_var: public cl_cvar
+{
+protected:
+  class cl_memory *mem;
+  t_addr addr;
+public:
+  cl_var(chars iname, class cl_memory *imem, t_addr iaddr, chars adesc, int ibitnr_high= -1, int ibitnr_low= -1);
+  virtual int init(void);
+  virtual class cl_memory *get_mem() const { return mem; }
+  virtual t_addr get_addr() const { return addr; }
+  virtual bool is_mem_var() const { return true; }
+
+  virtual void print_info(cl_console_base *con) const;
+};
+
+
+class cl_var_by_name_list: public cl_sorted_list
+{
+ public:
+  cl_var_by_name_list(): cl_sorted_list(10, 10, "symlist") {}
+  ~cl_var_by_name_list(void);
+
+  class cl_cvar *at(t_index index)
+  {
+    const void *a= cl_sorted_list::at(index);
+    class cl_cvar *v= (class cl_cvar *)a;
+    return v;
+  }
+
+ private:
+  virtual const void *key_of(const void *item) const;
+  virtual int compare(const void *key1, const void *key2);
+};
+
+class cl_var_by_addr_list: public cl_sorted_list
+{
+ public:
+  cl_var_by_addr_list(): cl_sorted_list(10, 10, "symlist_by_addr") {}
+  ~cl_var_by_addr_list(void);
+
+  class cl_var *at(t_index index)
+  {
+    const void *a= cl_sorted_list::at(index);
+    class cl_var *v= (class cl_var *)a;
+    return v;
+  }
+  bool search(class cl_memory *mem, t_addr addr, t_index &index);
+  bool search(class cl_memory *mem, t_addr addr, int bitnr_high, int bitnr_low, t_index &index);
+
+  int compare(const void *key1, const void *key2);
+
+ private:
+  int compare_addr(class cl_var *var, class cl_memory *mem, t_addr addr);
+  int compare_addr_and_bits(class cl_var *var, class cl_memory *mem, t_addr addr, int bitnr_high, int bitnr_low);
 };
 
+struct var_def {
+  const char *name;
+  int bitnr_high, bitnr_low;
+  const char *desc;
+};
+
+#define var_thiscell()	-1, -1
+#define var_offset(N)	-1, N
+#define var_bit(N)	N, N
+#define var_bitset(H,L)	H, L
 
-class cl_var_list: public cl_sorted_list
+class cl_var_list: public cl_base
 {
+ private:
+  size_t max_name_len;
+  bool max_name_len_known;
+
  public:
- cl_var_list(): cl_sorted_list(10, 10, "symlist") {}
+  class cl_var_by_name_list by_name;
+  class cl_var_by_addr_list by_addr;
+
  public:
-  virtual void *key_of(void *item);
-  virtual int compare(void *key1, void *key2);
+  cl_var_list() { max_name_len = 0; max_name_len_known = true; }
+
+  /*! \brief Add the given cl_var replacing any that already exist with the same name.
+   */
+  class cl_cvar *add(class cl_cvar *item);
+
+  /*! \brief Create and add (or replace) a var naming a set of bits in the cell given by mem and addr.
+   */
+  class cl_cvar *add(chars name, class cl_memory *mem, t_addr addr, int bitnr_high, int bitnr_low, chars desc);
+
+  /*! \brief Create and add (or replace) a var naming a set of bits in the cell given by a named var.
+   */
+  class cl_cvar *add(chars name, const char *cellname, int bitnr_high, int bitnr_low, chars desc);
+
+  /*! \brief Create and add (or replace) a var labeling a cell.
+   */
+  class cl_cvar *add(chars name, class cl_memory *mem, t_addr addr, chars desc) {
+    return add(name, mem, addr, -1, -1, desc);
+  }
+
+  /*! \brief Create and add (or replace) vars using the given list of definitions.
+   */
+  void add(chars prefix, class cl_memory *mem, t_addr base, const struct var_def *def, size_t n);
+
+  /*! \brief Delete the var with the given name.
+   */
+  bool del(const char *name);
+
+  
+  /*! \brief Return the length of the longest var name.
+   */
+  size_t get_max_name_len(void);
+
+  virtual t_mem read(chars name);
 };
 
+class cl_vars_iterator {
+  private:
+    cl_var_list *vars;
+    cl_memory *space_mem, *chip_mem;
+    t_addr space_addr, chip_addr;
+    t_index space_i, chip_i;
+
+  public:
+    cl_vars_iterator(cl_var_list *vars) { this->vars = vars; };
+
+    const cl_var *first(cl_memory *mem, t_addr addr);
+    const cl_var *next(void);
+
+  private:
+    int compare_bits(const class cl_var *var1, const class cl_var *var2);
+};
 
 #endif
 
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/sim.src/vcd.cc sdcc-4.2.0+dfsg/sim/ucsim/sim.src/vcd.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/sim.src/vcd.cc	2019-04-02 10:46:33.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/sim.src/vcd.cc	2022-02-08 21:21:05.000000000 +0000
@@ -25,439 +25,1163 @@
 02111-1307, USA. */
 /*@1@*/
 
+#include "ddconfig.h"
+
+#include 
+#include 
+#ifdef HAVE_SYS_WAIT_H
+#include 
+#endif
+#include 
+#include 
+#include 
+#include 
 #include 
+#include 
+#include 
 
 // prj
+#include "stypes.h"
 #include "utils.h"
+#include "globals.h"
 
 // sim
+#include "appcl.h"
 #include "argcl.h"
+#include "simcl.h"
 
 // local
 #include "vcdcl.h"
 
 
+static i64_t ULPs(double d1, double d2)
+{
+  i64_t i1, i2;
+
+  memcpy(&i1, &d1, sizeof(d1));
+  memcpy(&i2, &d2, sizeof(d2));
+
+  if ((i1 < 0) != (i2 < 0))
+    return
+#ifdef INT64_MAX
+      INT64_MAX
+#else
+      ((u64_t)-1)>>1
+#endif
+      ;
+
+  return (i1 > i2 ? i1 - i2 : i2 - i1);
+}
+
+
+#if defined(HAVE_WORKING_FORK) && defined(HAVE_DUP2) && defined(HAVE_PIPE) && defined(HAVE_WAITPID)
+
+#  if !defined(HAVE__EXIT)
+static void _exit(int status) { exit(status); }
+#  endif
+
+#  if !defined(O_CLOEXEC)
+#    define O_CLOEXEC 0
+#  endif
+
+/*
+#  if !defined(HAVE_DUP3)
+static int dup3(int oldfd, int newfd, int flags) { return dup2(oldfd, newfd); }
+#  endif
+*/
+
+static int spipe2(int pipefd[2], int flags) { return pipe(pipefd); }
+
+#endif
+
+class cl_vcd_var: public cl_memory_operator
+{
+ public:
+  class cl_vcd_var *next_var;
+  class cl_vcd *vcd;
+  int bitnr_high, bitnr_low;
+  t_mem bitmask;
+  char var_id;
+
+  cl_vcd_var(class cl_vcd *vcd, char vcd_id, class cl_memory_cell *cell, int bitnr_high, int bitnr_low);
+  ~cl_vcd_var(void);
+
+  t_mem write(t_mem val);
+};
+
+
+cl_vcd_var::cl_vcd_var(class cl_vcd *vcd, char var_id, class cl_memory_cell *cell, int bitnr_high, int bitnr_low):
+  cl_memory_operator(cell)
+{
+  set_name(vcd->get_name());
+
+  this->next_var = NULL;
+  this->vcd = vcd;
+  this->bitnr_high = bitnr_high;
+  this->bitnr_low = bitnr_low;
+
+  bitmask = ((1U << (bitnr_high - bitnr_low + 1)) - 1) << bitnr_low;
+
+  if (!(this->var_id = var_id))
+    {
+      this->var_id = vcd->get_next_var_id();
+      cell->append_operator(this);
+    }
+}
+
+
+cl_vcd_var::~cl_vcd_var(void)
+{
+  cell->remove_operator(this);
+}
+
+
+t_mem
+cl_vcd_var::write(t_mem val)
+{
+  if (vcd->is_running() /*&& (val & bitmask) != (cell->get() & bitmask)*/)
+    vcd->report(this, val);
+
+  return cl_memory_operator::write(val);
+}
+
+
 cl_vcd::cl_vcd(class cl_uc *auc, int aid, chars aid_string):
        cl_hw(auc, HW_DUMMY, aid, aid_string)
 {
-  locs= new cl_list(2, 2, "vcd_locs");
+  filename= NULL;
+  fd= 0;
+  vars= NULL;
+  reset_next_var_id();
+  starttime= 0;
+  timescale= 0;
+  event= 0;
+  pausetime= -1;
+  state= -1;
   started= false;
   paused= false;
-  fout= 0;
-  change= 0;
+  dobreak= false;
   modul= chars("", "ucsim_vcd_%d", id);
 }
 
+int
+cl_vcd::init(void)
+{
+  cl_hw::init();
+  on= false;
+
+  return 0;
+}
+
 void
-cl_vcd::add(class cl_memory_cell *cell)
+cl_vcd::clear_vars(void)
 {
-  if (!cell)
-    return;
-  if (!locs->index_of(cell, NULL))
+  while (vars)
     {
-      locs->add(cell);
-      register_cell(cell);
+      class cl_vcd_var *old = vars;
+      vars = vars->next_var;
+      delete old;
     }
 }
 
 void
-cl_vcd::del(class cl_memory_cell *cell)
+cl_vcd::add_var(class cl_console_base *con, char var_id, class cl_memory_cell *cell, int bitnr_high, int bitnr_low)
 {
   if (!cell)
     return;
-  if (locs->index_of(cell, NULL))
+
+  if (cell->get_flag(CELL_NON_DECODED))
+    {
+      if (con) con->dd_printf("Cell is not decoded\n");
+      return;
+    }
+
+  if (started)
     {
-      unregister_cell(cell);
-      locs->disconn(cell);
+      if (con) con->dd_printf("Already started\n");
+      return;
     }
+
+  if (bitnr_high == -1)
+    bitnr_high = cell->get_width() - 1;
+
+  if (bitnr_low == -1)
+    bitnr_low = 0;
+
+  class cl_vcd_var **var_p;
+
+  for (var_p = &vars; *var_p; var_p = &((*var_p)->next_var))
+    {
+      if ((*var_p)->cell == cell &&
+          (*var_p)->bitnr_high == bitnr_high && (*var_p)->bitnr_low == bitnr_low)
+        {
+          if (con) con->dd_printf("Already exists\n");
+          return;
+        }
+    }
+
+  *var_p = new cl_vcd_var(this, var_id, cell, bitnr_high, bitnr_low);
 }
 
-bool
-cl_vcd::add(class cl_memory *m, t_addr a, class cl_console_base *con)
+void
+cl_vcd::del_var(class cl_console_base *con, class cl_memory_cell *cell, int bitnr_low, int bitnr_high)
+{
+  for (class cl_vcd_var **var_p = &vars; *var_p; var_p = &((*var_p)->next_var))
+    {
+      if ((*var_p)->cell == cell)
+        {
+          if ((*var_p)->bitnr_high == bitnr_high && (*var_p)->bitnr_low == bitnr_low)
+            {
+              class cl_vcd_var *old = *var_p;
+              *var_p = (*var_p)->next_var;
+              delete old;
+
+              if (vars == NULL && !started)
+                reset_next_var_id();
+
+              return;
+            }
+        }
+    }
+
+  if (con) con->dd_printf("Not found\n");
+}
+
+void
+cl_vcd::add_var(class cl_console_base *con, class cl_memory *m, t_addr a, int bitnr_high, int bitnr_low)
 {
   if (!m->is_address_space())
     {
-      if (con) con->dd_printf("%s is not an address space\n");
-      return false;
+      if (con) con->dd_printf("Not an address space\n");
+      return;
     }
   if (!m->valid_address(a))
     {
       if (con) con->dd_printf("Address must be between 0x%x and 0x%x\n",
-			      AU(m->lowest_valid_address()),
-			      AU(m->highest_valid_address()));
-      return false;
+                              AU(m->lowest_valid_address()),
+                              AU(m->highest_valid_address()));
+      return;
     }
   cl_memory_cell *c= ((cl_address_space*)m)->get_cell(a);
-  if (c->get_flag(CELL_NON_DECODED))
-    {
-      if (con) con->dd_printf("Cell is not decoded\n");
-      return false;
-    }
-  add(c);
-  return true;
+  add_var(con, 0, c, bitnr_high, bitnr_low);
 }
 
-bool
-cl_vcd::del(class cl_memory *m, t_addr a, class cl_console_base *con)
+void
+cl_vcd::del_var(class cl_console_base *con, class cl_memory *m, t_addr a, int bitnr_low, int bitnr_high)
 {
   if (!m->is_address_space())
     {
       if (con) con->dd_printf("%s is not an address space\n");
-      return false;
+      return;
     }
   if (!m->valid_address(a))
     {
       if (con) con->dd_printf("Address must be between 0x%x and 0x%x\n",
-			      AU(m->lowest_valid_address()),
-			      AU(m->highest_valid_address()));
-      return false;
+                              AU(m->lowest_valid_address()),
+                              AU(m->highest_valid_address()));
+      return;
+    }
+  del_var(con, ((cl_address_space*)m)->get_cell(a), bitnr_low, bitnr_high);
+}
+
+FILE *
+cl_vcd::open_vcd(class cl_console_base *con)
+{
+  if (state != -1)
+    {
+      if (filename)
+        {
+          if ((fd= fopen(filename, "re")) == NULL)
+            con->dd_printf("%s: %s\n", filename, strerror(errno));
+        }
+      else
+        con->dd_printf("No file specified\n");
+    }
+  else if (filename && filename[0] != '|')
+    {
+      if ((fd= fopen(filename, "we")) == NULL)
+        con->dd_printf("%s: %s\n", filename, strerror(errno));
+    }
+  else
+    {
+#if defined(HAVE_WORKING_FORK) && defined(HAVE_DUP2) && defined(HAVE_PIPE) && defined(HAVE_WAITPID)
+      int p[2];
+      pid_t pid;
+
+      if (!spipe2(p, O_CLOEXEC))
+        {
+          if ((pid = fork()) > 0)
+            {
+              // Parent
+              if (!(fd = fdopen(p[1], "we")))
+                {
+                  close(p[1]);
+                  con->dd_printf("fdopen: %s\n", strerror(errno));
+                }
+              close(p[0]);
+
+              // Reap the intermediate child. The real child is no longer
+              // under our control.
+              waitpid(pid, NULL, 0);
+            }
+          else if (pid == 0)
+            {
+              // Child
+              // Double fork to break the parent-child relationship
+              if (fork() != 0)
+                _exit(0);
+
+              dup2(p[0], 0);
+              close(p[0]);
+              close(p[1]);
+
+              const char *cmd = filename;
+              if (!cmd)
+                cmd = "exec > /dev/null 2>&1; shmidcat | gtkwave -v -I";
+              else if (cmd[0] == '|')
+                cmd++;
+
+              execl("/bin/sh", "sh", "-c", cmd, (char*)NULL);
+              perror("execl");
+              _exit(1);
+            }
+          else
+            {
+              con->dd_printf("fork: %s\n", strerror(errno));
+              close(p[0]);
+              close(p[1]);
+            }
+        }
+      else
+        con->dd_printf("pipe: %s\n", strerror(errno));
+#else
+      con->dd_printf("Piped output (e.g. to gtkwave) is not supported on this platform\n");
+#endif
+    }
+
+  return fd;
+}
+
+void
+cl_vcd::close_vcd(void)
+{
+  fclose(fd);
+}
+
+bool
+cl_vcd::parse_header(cl_console_base *con)
+{
+  int width = 0;
+  char id = 0;
+
+  clear_vars();
+  state = 0;
+  word[0] = 'X';
+  word[1] = ' ';
+  char *token = &word[2];
+
+  while (read_word(2U))
+    {
+      if (!strcmp(token, "$end"))
+        state = 0;
+      else if (state == 0)
+        {
+          if (token[0] == '#')
+            {
+              event = starttime + timescale * strtod(&token[1], NULL);
+              //uc->sim->app->debug("vcd[%d]: first event at %.15f\n", cl_hw::id, event);
+              break;
+            }
+          else if (!strcmp(token, "$timescale"))
+            state = 2;
+          else if (!strcmp(token, "$dumpvars"))
+            state = 3;
+          else if (!strcmp(token, "$var"))
+             state = 4;
+        }
+      else if (state == 2) // $timescale
+        {
+          int i = 0;
+          if (token[0] >= '0' && token[0] <= '9')
+            sscanf(token, "%lf%n", ×cale, &i);
+          if (!strcmp(&token[i], "fs"))
+            timescale *= 1e-15;
+          else if (!strcmp(&token[i], "ps"))
+            timescale *= 1e-12;
+          else if (!strcmp(&token[i], "ns"))
+            timescale *= 1e-09;
+          else if (!strcmp(&token[i], "us"))
+            timescale *= 1e-06;
+          else if (!strcmp(&token[i], "ms"))
+            timescale *= 1e-03;
+        }
+      else if (state == 3) // $dumpvars
+        // FIXME: does it make sense to set the initial state of all vars?
+        ; // set_mem_from_var(token); // FIXME: not implemented yet
+      else if (state == 4) // $var [type]
+        state = (!strcmp(token, "wire") ? 5 : 8);
+      else if (state == 5) // $var [type] [bitwidth]
+        {
+          width = strtol(token, NULL, 0);
+          state = 6;
+        }
+      else if (state == 6) // $var [type] [bitwidth] [id]
+        {
+          id = token[0];
+          state = 7;
+        }
+      else if (state == 7) // $var [type] [bitwidth] [id] [name]
+        {
+          class cl_cmdline *cmdline = new cl_cmdline(NULL, word, con);
+          cmdline->init();
+
+          if (cmdline->params->count != 1)
+            {
+              con->dd_printf("Unable to interpret %s, ignoring\n", token);
+              continue;
+            }
+
+          class cl_cmd_arg *param = (class cl_cmd_arg *)(cmdline->params->at(0));
+
+          if (param->as_bit(uc))
+            {
+              if (param->value.bit.mem->is_address_space())
+                add_var(con, id, ((cl_address_space *)param->value.bit.mem)->get_cell(param->value.bit.mem_address), param->value.bit.bitnr_low + width - 1, param->value.bit.bitnr_low);
+              else
+                con->dd_printf("Unable to interpret %s as a memory/bit reference in an address space\n", token);
+            }
+          else if (param->as_cell(uc))
+            add_var(con, id, param->value.cell, width - 1, 0);
+          else
+            con->dd_printf("Unable to interpret %s as a memory/bit reference\n", token);
+
+          state = 8;
+        }
     }
-  del(((cl_address_space*)m)->get_cell(a));
+
   return true;
 }
 
+bool
+cl_vcd::read_word(unsigned int i)
+{
+  int c;
+
+  do
+    {
+      c = getc(fd);
+    }
+  while (c != EOF && strchr(" \n\r\t", c));
+
+  if (c != EOF)
+    {
+      do
+        {
+          if (i < sizeof(word) - 1)
+            word[i++] = c;
+          c = getc(fd);
+        }
+      while (c > 0 && !strchr(" \n\r\t", c));
+    }
+  else
+    on = false;
+
+  word[i] = '\0';
+  return (c != EOF);
+}
+
 void
 cl_vcd::set_cmd(class cl_cmdline *cmdline, class cl_console_base *con)
 {
-  class cl_cmd_arg *params[3]= {
+  class cl_cmd_arg *params[5]= {
     cmdline->param(0),
     cmdline->param(1),
-    cmdline->param(2)
+    cmdline->param(2),
+    cmdline->param(3),
+    cmdline->param(4)
   };
 
-  if (cmdline->syntax_match(uc, MEMORY ADDRESS)) // ADD
+  if (cmdline->syntax_match(uc, BIT)) // ADD
     {
-      if (started)
-	{
-	  con->dd_printf("Already started\n");
-	  return;
-	}
-      class cl_memory *mem= params[0]->value.memory.memory;
-      t_addr a= params[1]->value.address;
-      if (!mem->is_address_space())
-	{
-	  con->dd_printf("%s is not an address space\n");
-	  return;
-	}
-      if (!mem->valid_address(a))
-	{
-	  con->dd_printf("Address must be between 0x%x and 0x%x\n",
-			 AU(mem->lowest_valid_address()),
-			 AU(mem->highest_valid_address()));
-	  return;
-	}
-      add(mem, a, con);
+      add_var(con, params[0]->value.bit.mem, params[0]->value.bit.mem_address, params[0]->value.bit.bitnr_high, params[0]->value.bit.bitnr_low);
+      return;
+    }
+  else if (cmdline->syntax_match(uc, MEMORY ADDRESS NUMBER NUMBER)) // ADD
+    {
+      add_var(con, params[0]->value.memory.memory, params[1]->value.address, params[2]->value.number, params[3]->value.number);
+      return;
+    }
+  else if (cmdline->syntax_match(uc, MEMORY ADDRESS NUMBER)) // ADD
+    {
+      add_var(con, params[0]->value.memory.memory, params[1]->value.address, params[2]->value.number, params[2]->value.number);
+      return;
+    }
+  else if (cmdline->syntax_match(uc, MEMORY ADDRESS)) // ADD
+    {
+      add_var(con, params[0]->value.memory.memory, params[1]->value.address, -1, -1);
+      return;
+    }
+  else if (cmdline->syntax_match(uc, CELL NUMBER NUMBER)) // ADD
+    {
+      add_var(con, params[0]->value.cell, params[1]->value.number, params[2]->value.number);
+      return;
+    }
+  else if (cmdline->syntax_match(uc, CELL NUMBER)) // ADD
+    {
+      add_var(con, params[0]->value.cell, params[1]->value.number, params[1]->value.number);
       return;
     }
   else if (cmdline->syntax_match(uc, CELL)) // ADD
     {
-      if (started)
-	{
-	  con->dd_printf("Already started\n");
-	  return;
-	}
-      if (params[0]->value.cell->get_flag(CELL_NON_DECODED))
-	con->dd_printf("Cell is not decoded\n");
-      else
-	add(params[0]->value.cell);
+      add_var(con, params[0]->value.cell, -1, -1);
       return;
     }
+  else if (cmdline->syntax_match(uc, STRING BIT)) // DEL|ADD
+    {
+      char *p1= params[0]->value.string.string;
+      if (p1 && *p1)
+        {
+          if (strcmp(p1, "add") == 0)
+            {
+              add_var(con, params[1]->value.bit.mem, params[1]->value.bit.mem_address, params[1]->value.bit.bitnr_high, params[1]->value.bit.bitnr_low);
+              return;
+            }
+          else if (strstr(p1, "del") == p1)
+            {
+              del_var(con, params[1]->value.bit.mem, params[1]->value.bit.mem_address, params[1]->value.bit.bitnr_low, params[1]->value.bit.bitnr_high);
+              return;
+            }
+          else if (strcmp(p1, "new") == 0)
+            {
+              int nid= params[1]->as_number();
+              if (uc->get_hw(id_string, nid, NULL) != NULL)
+                {
+                  con->dd_printf("Already exists\n");
+                  return;
+                }
+              cl_hw *h= new cl_vcd(uc, nid, id_string);
+              h->init();
+              uc->add_hw(h);
+              return;
+            }
+        }
+    }
+  else if (cmdline->syntax_match(uc, STRING MEMORY ADDRESS NUMBER NUMBER)) // DEL|ADD
+    {
+      char *p1= params[0]->value.string.string;
+      if (p1 && *p1)
+        {
+          if (strcmp(p1, "add") == 0)
+            add_var(con, params[1]->value.memory.memory, params[2]->value.address, params[3]->value.number, params[4]->value.number);
+          else if (strstr(p1, "del") == p1)
+            del_var(con, params[1]->value.memory.memory, params[2]->value.address, params[3]->value.number, params[4]->value.number);
+          return;
+        }
+    }
+  else if (cmdline->syntax_match(uc, STRING MEMORY ADDRESS NUMBER)) // DEL|ADD
+    {
+      char *p1= params[0]->value.string.string;
+      if (p1 && *p1)
+        {
+          if (strcmp(p1, "add") == 0)
+            add_var(con, params[1]->value.memory.memory, params[2]->value.address, params[3]->value.number, params[3]->value.number);
+          else if (strstr(p1, "del") == p1)
+            del_var(con, params[1]->value.memory.memory, params[2]->value.address, params[3]->value.number, params[3]->value.number);
+          return;
+        }
+    }
   else if (cmdline->syntax_match(uc, STRING MEMORY ADDRESS)) // DEL|ADD
     {
-      if (started)
-	{
-	  con->dd_printf("Already started\n");
-	  return;
-	}
-      params[0]->as_string();
       char *p1= params[0]->value.string.string;
       if (p1 && *p1)
-	{
-	  if (strcmp(p1, "add") == 0)
-	    {
-	      if (add(params[1]->value.memory.memory, params[2]->value.address, con))
-		return;
-	    }
-	  if (strstr(p1, "del") == p1)
-	    {
-	      if (del(params[1]->value.memory.memory, params[2]->value.address, con))
-		return;
-	    }
-	}
+        {
+          if (strcmp(p1, "add") == 0)
+            add_var(con, params[1]->value.memory.memory, params[2]->value.address, -1, -1);
+          else if (strstr(p1, "del") == p1)
+            del_var(con, params[1]->value.memory.memory, params[2]->value.address, -1, -1);
+          return;
+        }
+    }
+  else if (cmdline->syntax_match(uc, STRING CELL NUMBER NUMBER)) // DEL|ADD
+    {
+      char *p1= params[0]->value.string.string;
+      if (p1 && *p1)
+        {
+          if (strcmp(p1, "add") == 0)
+            add_var(con, params[1]->value.cell, params[2]->value.number, params[3]->value.number);
+          else if (strstr(p1, "del") == p1)
+            del_var(con, params[1]->value.cell, params[2]->value.number, params[3]->value.number);
+          return;
+        }
+    }
+  else if (cmdline->syntax_match(uc, STRING CELL NUMBER)) // DEL|ADD
+    {
+      char *p1= params[0]->value.string.string;
+      if (p1 && *p1)
+        {
+          if (strcmp(p1, "add") == 0)
+            add_var(con, params[1]->value.cell, params[2]->value.number, params[2]->value.number);
+          else if (strstr(p1, "del") == p1)
+            del_var(con, params[1]->value.cell, params[2]->value.number, params[2]->value.number);
+          return;
+        }
     }
   else if (cmdline->syntax_match(uc, STRING CELL)) // DEL|ADD
     {
-      if (started)
-	{
-	  con->dd_printf("Already started\n");
-	  return;
-	}
-      params[0]->as_string();
       char *p1= params[0]->value.string.string;
       if (p1 && *p1)
-	{
-	  if (strcmp(p1, "add") == 0)
-	    {
-	      if (params[1]->value.cell->get_flag(CELL_NON_DECODED))
-		con->dd_printf("Cell is not decoded\n");
-	      else
-		add(params[1]->value.cell);
-	      return;
-	    }
-	  if (strstr(p1, "del") == p1)
-	    {
-	      del(params[1]->value.cell);
-	      return;
-	    }
-	}
+        {
+          if (strcmp(p1, "add") == 0)
+            add_var(con, params[1]->value.cell, -1, -1);
+          else if (strstr(p1, "del") == p1)
+            del_var(con, params[1]->value.cell, -1, -1);
+          return;
+        }
     }
-  else if (cmdline->syntax_match(uc, STRING NUMBER)) // NEW id
+  else if (cmdline->syntax_match(uc, STRING NUMBER STRING)) // TIMESCALE, PAUSETIME, STARTTIME
     {
-      params[0]->as_string();
       char *p1= params[0]->value.string.string;
       if (p1 && *p1 &&
-	  (strcmp(p1, "new") == 0))
-	{
-	  params[1]->as_number();
-	  int nid= params[1]->value.number;
-	  if (uc->get_hw((char*)id_string, nid, NULL) != NULL)
-	    {
-	      con->dd_printf("Already exists\n");
-	      return;
-	    }
-	  cl_hw *h= new cl_vcd(uc, nid, id_string);
-	  h->init();
-	  uc->add_hw(h);
-	  return;
-	}
+          (strcmp(p1, "timescale") == 0 ||
+           strcmp(p1, "pausetime") == 0 ||
+           strcmp(p1, "starttime") == 0))
+        {
+          double time = params[1]->value.number;
+          char *p2= params[2]->value.string.string;
+          if (!strcmp(p2, "fs"))
+            time /= 1e15;
+          else if (!strcmp(p2, "ps"))
+            time /= 1e12;
+          else if (!strcmp(p2, "ns"))
+            time /= 1e9;
+          else if (!strcmp(p2, "us") || !strcmp(p2, "µs"))
+            time /= 1e6;
+          else if (!strcmp(p2, "ms"))
+            time /= 1e3;
+          else
+            con->dd_printf("Units must be ms, us, ns, ps or fs\n");
+          if (p1[0] == 't')
+            timescale = time;
+          else if (p1[0] == 'p')
+            {
+              pausetime = time;
+              if (state == -1 && started && paused &&
+                  (!filename || filename[0] == '|'))
+                on = (uc->ticks->get_rtime() - event < pausetime);
+            }
+          else
+            {
+              starttime += time;
+              event += time;
+              //uc->sim->app->debug("vcd[%d]: event rescheduled to %.15f\n", cl_hw::id, event);
+            }
+          return;
+        }
     }
-  else if (cmdline->syntax_match(uc, STRING STRING)) // FILE, MOD
+  else if (cmdline->syntax_match(uc, STRING STRING)) // TIMESCALE AUTO, FILE, MOD
     {
-      params[0]->as_string();
-      params[1]->as_string();
       char *p1= params[0]->value.string.string;
       char *p2= params[1]->value.string.string;
+      if (p1 && p2 &&
+          !strcmp(p1, "timescale") &&
+          !strcmp(p2, "auto"))
+        {
+          timescale = 0;
+          return;
+        }
       if (started)
-	{
-	  con->dd_printf("Already started\n");
-	  return;
-	}
+        {
+          con->dd_printf("Already started\n");
+          return;
+        }
       if (p1 && *p1)
-	{
-	  if (!p2 || !*p2)
-	    {
-	      con->dd_printf("Name missing\n");
-	      return;
-	    }
-	  if ((strcmp(p1, "fout") == 0) ||
-	      (strcmp(p1, "file") == 0))
-	    {
-	      if ((fout= mk_io(p2, "w")) == NULL)
-		con->dd_printf("File open error\n");
-	      return;
-	    }
-	  if (strstr(p1, "mod") == p1)
-	    {
-	      modul= chars(p2);
-	      return;
-	    }
-	}
+        {
+          if (strstr(p1, "mod") == p1)
+            {
+              if (p2 && *p2)
+                modul= chars(p2);
+              else
+                con->dd_printf("Name missing\n");
+              return;
+            }
+          if ((strstr(p1, "out") == p1) ||
+              (strstr(p1, "file") == p1) ||
+              (strstr(p1, "in") == p1))
+            {
+              if (filename)
+                free(filename);
+              filename = NULL;
+              state = (!strcmp(p1, "input") ? 0 : -1);
+              if (!state && (!p2 || !*p2))
+                con->dd_printf("Name missing\n");
+              else if (p2 && *p2)
+                filename = strdup(p2);
+              return;
+            }
+        }
     }
   else if (cmdline->syntax_match(uc, STRING)) // [RE]START, PAUSE, STOP
     {
-      params[0]->as_string();
       char *p1= params[0]->value.string.string;
       if (p1 && *p1)
-	{
-	  if ((strstr(p1, "re") == p1) ||
-	      (strcmp(p1, "start") == 0))
-	    {
-	      if (started)
-		paused= false;
-	      else
-		{
-		  if (!fout)
-		    con->dd_printf("Output unspecified\n");
-		  else
-		    {
-		      // generate vcd file header
-		      time_t t= time(NULL);
-		      fout->write_str("$date\n");
-		      fout->write_str(ctime(&t));
-		      fout->write_str("$end\n");
-		      fout->write_str("$version\n");
-		      fout->prntf("ucsim\n");
-		      fout->write_str("$end\n");
-		      fout->write_str("$timescale 1ns $end\n");
-		      fout->prntf("$scope module %s $end\n", (char*)modul);
-		      int i;
-		      for (i= 0; i < locs->count; i++)
-			{
-			  cl_memory_cell *c= (cl_memory_cell *)
-			    (locs->at(i));
-			  chars n= uc->cell_name(c);
-			  fout->prntf("$var wire %d %c %s $end\n",
-				      c->get_width(), 33+i,
-				      (char*)n);
-			}
-		      fout->write_str("$upscope $end\n");
-		      fout->write_str("$enddefinitions $end\n");
-		      fout->write_str("$dumpvars\n");
-		      for (i= 0; i < locs->count; i++)
-			{
-			  cl_memory_cell *c= (cl_memory_cell *)
-			    (locs->at(i));
-			  report(c, i);
-			}
-		      fout->write_str("$end\n");
-		      started= true;
-		      paused= false;
-		      change= false;
-		    }
-		}
-	      return;
-	    }
-	  if (strstr(p1, "paus") == p1)
-	    {
-	      if (started)
-		paused= !paused;
-	      return;
-	    }
-	  if (strcmp(p1, "stop") == 0)
-	    {
-	      if (started)
-		{
-		  if (fout)
-		    delete fout;
-		  fout= NULL;
-		}
-	      started= paused= change= false;
-	      return;
-	    }
-	  if (strcmp(p1, "info") == 0)
-	    {
-	      print_info(con);
-	      return;
-	    }
-	}
-    }
-  //else
-    {
-      con->dd_printf("set hardware vcd[id] [add] memory address\n");
-      con->dd_printf("set hardware vcd[id] del[ete] memory address\n");
-      con->dd_printf("set hardware vcd[id] fout|file \"vcd_file_name\"|gtkwave\n");
-      con->dd_printf("set hardware vcd[id] mod[ule] module_name\n");
-      con->dd_printf("set hardware vcd[id] start\n");
-      con->dd_printf("set hardware vcd[id] pause\n");
-      con->dd_printf("set hardware vcd[id] [re]start\n");
-      con->dd_printf("set hardware vcd[id] stop\n");
-      con->dd_printf("set hardware vcd[id] new id\n");
+        {
+          if ((strstr(p1, "out") == p1) ||
+              (strstr(p1, "file") == p1) ||
+              (strstr(p1, "view") == p1))
+            {
+              if (filename)
+                free(filename);
+              filename = NULL;
+              state = -1;
+              return;
+            }
+          if (strstr(p1, "re") == p1 ||
+              strcmp(p1, "start") == 0 ||
+              (paused && strstr(p1, "paus") == p1))
+            {
+              if (!started)
+                {
+                  if ((fd= open_vcd(con)) == NULL)
+                    return;
+
+                  if (state != -1)
+                    {
+                      if (!parse_header(con))
+                        return;
+                    }
+                  else
+                    {
+                      starttime += uc->ticks->get_rtime();
+                      event += uc->ticks->get_rtime();
+
+                      if (!timescale)
+                        {
+                          timescale = 1e3;
+                          while (timescale * 1.0 / uc->get_xtal() < 1.0)
+                            timescale *= 1000.0;
+                          if (fmod(timescale * 1.0 / uc->get_xtal(), 1.0) > 0.0)
+                            timescale *= 1000.0;
+                        }
+
+                      // generate vcd file header
+                      time_t now = time(NULL);
+		      if (application->quiet)
+			now= (time_t)0;
+                      fprintf(fd, "$date\n\t%s$end\n$version\n\tucsim\n$end\n$timescale ", ctime(&now));
+                      if (timescale >= 1e15)
+                        fprintf(fd, "%.0ffs", timescale * 1e-15);
+                      else if (timescale >= 1e12)
+                        fprintf(fd, "%.0fps", timescale * 1e-12);
+                      else if (timescale >= 1e9)
+                        fprintf(fd, "%.0fns", timescale * 1e-9);
+                      else if (timescale >= 1e6)
+                        fprintf(fd, "%.0fus", timescale * 1e-6);
+                      else if (timescale >= 1e3)
+                        fprintf(fd, "%.0fms", timescale * 1e-3);
+                      else
+                        fprintf(fd, "%.0fms", timescale * 1e3);
+
+                      fprintf(fd, " $end\n$scope module %s $end\n", modul.c_str());
+
+                      for (class cl_vcd_var *var = vars; var; var = var->next_var)
+                        {
+                          fprintf(fd, "$var wire %d %c ",
+                                      (var->bitnr_low >= 0 ? var->bitnr_high - var->bitnr_low + 1 : var->cell->get_width()),
+                                      var->var_id);
+
+                          t_addr addr = 0;
+                          cl_address_space *as = uc->address_space(var->cell, &addr);
+                          t_index i;
+
+                          if (var->bitnr_high >= 0)
+                            {
+                              if (uc->vars->by_addr.search(as, addr, var->bitnr_high, var->bitnr_low, i))
+                                {
+                                  fprintf(fd, "%s $end\n", uc->vars->by_addr.at(i)->get_name());
+                                  continue;
+                                }
+                            }
+
+                          if (uc->vars->by_addr.search(as, addr, -1, -1, i) ||
+                              uc->vars->by_addr.search(as, addr, var->cell->get_width() - 1, 0, i))
+                            fprintf(fd, "%s", uc->vars->by_addr.at(i)->get_name());
+                          else
+                            {
+                              fprintf(fd, "%s_", (as ? as->get_name() : "?"));
+                              fprintf(fd, (as ? as->addr_format : "0x06x"), addr);
+                            }
+
+                          if (var->bitnr_high == var->bitnr_low)
+                            fprintf(fd, ".%d", var->bitnr_low);
+                          else if (var->bitnr_low != 0 || var->bitnr_high != var->cell->get_width() - 1)
+                            fprintf(fd, "[%d:%d]", var->bitnr_high, var->bitnr_low);
+
+                          fprintf(fd, " $end\n");
+                        }
+
+                      fputs("$upscope $end\n$enddefinitions $end\n", fd);
+                      if (!filename || filename[0] == '|') fflush(fd);
+                    }
+                }
+
+              if (!started || paused)
+                {
+                  if (paused)
+                    con->dd_printf("Unpaused\n");
+                  if (state == -1)
+                    {
+                      double now = uc->ticks->get_rtime();
+                      double d =  now - event;
+                      d = event + (pausetime >= 0 && d > pausetime ? pausetime : d);
+                      starttime = now - (d - starttime);
+                      fprintf(fd, "#%.0f\n", (now - starttime) * timescale);
+                      if (started)
+                        {
+                          if (pausetime < 0)
+                            fprintf(fd, "$comment Unpaused $end\n$dumpon\n");
+                          else
+                            fprintf(fd, "$comment Unpaused. Real duration was %.15f seconds $end\n$dumpon\n", now - event);
+                        }
+                      else
+                        fprintf(fd, "$dumpvars\n");
+                      event = now;
+                      for (class cl_vcd_var *var = vars; var; var = var->next_var)
+                        report(var, var->cell->get());
+                      fprintf(fd, "$end\n");
+                      if (!filename || filename[0] == '|') fflush(fd);
+                    }
+                  else
+                    {
+                      starttime = uc->ticks->get_rtime() + starttime;
+                      event = starttime + event;
+                    }
+                }
+
+              started = true;
+              paused = false;
+              if (state >= 0 || !filename || filename[0] == '|')
+                on = true;
+
+              return;
+            }
+          if (strstr(p1, "paus") == p1)
+            {
+              if (started)
+                {
+                  paused = true;
+
+                  if (state != -1 || pausetime < 0)
+                    con->dd_printf("Paused\n");
+                  else
+                    con->dd_printf("Paused (pause limit %.15f s)\n", pausetime);
+
+                  if (state == -1)
+                    {
+                      event = uc->ticks->get_rtime();
+                      fprintf(fd, "#%.0f\n$comment Paused $end\n$dumpoff\n", (event - starttime) * timescale);
+                      for (class cl_vcd_var *var = vars; var; var = var->next_var)
+                        {
+                          if (var->bitnr_low == var->bitnr_high)
+                            fprintf(fd, "x%c\n", var->var_id);
+                          else
+                            {
+                              putc('b', fd);
+                              for (int i = var->bitnr_high; i >= var->bitnr_low; i--)
+                                putc('x', fd);
+                              fprintf(fd, " %c\n", var->var_id);
+                            }
+                        }
+                      fprintf(fd, "$end\n");
+                      if (!filename || filename[0] == '|') fflush(fd);
+                      on = ((!filename || filename[0] == '|') || pausetime >= 0);
+                    }
+                  else
+                    {
+                      event = event - starttime;
+                      starttime = starttime - uc->ticks->get_rtime();
+                      on = false;
+                    }
+                }
+              else
+                con->dd_printf("Not started");
+              return;
+            }
+          if (strcmp(p1, "stop") == 0)
+            {
+              if (started)
+                {
+                  if (fd)
+                    {
+                      if (state == -1)
+                        fprintf(fd, "#%.0f\n", (uc->ticks->get_rtime() - starttime) * timescale);
+                      close_vcd();
+                    }
+                  fd= NULL;
+                  on = false;
+                  starttime = 0.0;
+                  event = 0.0;
+                  if (state != -1)
+                    clear_vars();
+                  else if (!vars)
+                    reset_next_var_id();
+                }
+              started= paused= false;
+              return;
+            }
+          if (strcmp(p1, "break") == 0)
+            {
+              dobreak= !dobreak;
+              con->dd_printf("Break on events %s\n", (dobreak ? "enabled" : "disabled"));
+              return;
+            }
+          if (strcmp(p1, "info") == 0)
+            {
+              print_info(con);
+              return;
+            }
+        }
     }
-}
 
-t_mem
-cl_vcd::read(class cl_memory_cell *cell)
-{
-
-  conf(cell, NULL);
-  return cell->get();
+    con->dd_printf("set hardware vcd[id] add memory address [ [bit_high] bit_low]\n");
+    con->dd_printf("set hardware vcd[id] del[ete] memory address [ [bit_high] bit_low]\n");
+    con->dd_printf("set hardware vcd[id] timescale n [ms|us|ns|ps|fs]\n");
+    con->dd_printf("set hardware vcd[id] starttime n [ms|us|ns|ps|fs]\n");
+    con->dd_printf("set hardware vcd[id] input \"vcd_file_name\"\n");
+    con->dd_printf("set hardware vcd[id] output|file \"vcd_file_name\"\n");
+    con->dd_printf("set hardware vcd[id] mod[ule] module_name\n");
+    con->dd_printf("set hardware vcd[id] start\n");
+    con->dd_printf("set hardware vcd[id] pause\n");
+    con->dd_printf("set hardware vcd[id] [re]start\n");
+    con->dd_printf("set hardware vcd[id] stop\n");
+    con->dd_printf("set hardware vcd[id] break\n");
+    con->dd_printf("set hardware vcd[id] new id\n");
 }
 
 void
-cl_vcd::write(class cl_memory_cell *cell, t_mem *val)
+cl_vcd::report(class cl_vcd_var *var, t_mem v)
 {
-  if (started &&
-      !paused)
+  double now = uc->ticks->get_rtime();
+  //uc->sim->app->debug("vcd[%d]: '%c' changed at %.15f\n",
+  //                    cl_hw::id, var->var_id, uc->ticks->get_rtime());
+  if (event != now)
     {
-      if (cell->def_data != *val)
-	{
-	  //change_time= uc->get_rtime();
-	  change= true;
-	}
-    }      
-  if (conf(cell, val))
-    return;
-}
+      event = now;
+      fprintf(fd, "#%.0f\n", (event - starttime) * timescale);
+    }
 
-t_mem
-cl_vcd::conf_op(cl_memory_cell *cell, t_addr addr, t_mem *val)
-{
-  if (addr >= 1)
-    return cell->get();
-  switch (addr)
+  if (var->bitnr_low == var->bitnr_high)
     {
+      fprintf(fd, "%c%c\n", ((v & var->bitmask) ? '1' : '0'), var->var_id);
     }
-  return cell->get();
-}
-
-char *
-cl_vcd::cfg_help(t_addr addr)
-{
-  return (char*)"Not used";
-}
-
-void
-cl_vcd::report(class cl_memory_cell *cell, int nr)
-{
-  t_mem v= cell->get();
-  if (fout)
+  else
     {
-      int w= cell->get_width();
-      if (w == 1)
-	{
-	  fout->prntf("%d%c\n", v?1:0, nr+33);
-	}
-      else
-	{
-	  fout->write((char*)"b", 1);
-	  fout->prntf("%s %c\n", (char*)cbin(v, w), nr+33);
-	}
+      putc('b', fd);
+      for (int i = var->bitnr_high; i >= var->bitnr_low; i--)
+        putc((v & (1U << i)) ? '1' : '0', fd);
+      fprintf(fd, " %c\n", var->var_id);
     }
-  cell->def_data= v;
+
+  fflush(fd);
 }
 
 int
 cl_vcd::tick(int cycles)
 {
-  if (change)
+  if (!fd || !started)
+    return 0;
+
+  double now = uc->ticks->get_rtime();
+
+  if (state == -1)
     {
-      int i;
-      change_time= uc->get_rtime();
-      if (fout)
-	fout->prntf("#%lu\n", (unsigned long)(change_time * 1000000000));
-      for (i= 0; i < locs->count; i++)
-	{
-	  class cl_memory_cell *c= (cl_memory_cell*)(locs->at(i));
-	  if (c->get() != c->def_data)
-	    {
-	      report(c, i);
-	    }
-	}
-      change= false;
+      if (pausetime >= 0 && now - event >= pausetime)
+        on = false;
+      else if (!filename || filename[0] == '|')
+        {
+          fprintf(fd, "#%.0f\n", (now - starttime) * timescale);
+          fflush(fd);
+        }
+      return 0;
     }
+
+  bool event_occurred = false;
+  bool more_data = true;
+
+  while (more_data && event < now && ULPs(now, event) > 100000)
+    {
+      t_mem value = 0;
+      while ((more_data = read_word(0U)))
+        {
+          if (state == 0 && word[0] != '1' && word[0] != '0')
+            {
+              if (word[0] == '#')
+                {
+                  event = starttime + timescale * strtod(&word[1], NULL);
+                  //uc->sim->app->debug("vcd[%d]: next event at %.15f\n", cl_hw::id, event);
+                  if (event < now && ULPs(now, event) > 100000)
+                    continue;
+                  break;
+                }
+              else if (word[0] == 'b' || word[0] == 'B')
+                {
+                  // Bit-vector value, next word is ID
+                  for (char *ptr = word; *ptr; ptr++)
+                    value = (value << 1) | (*ptr == '1' ? 1 : 0);
+                  state = 1;
+                }
+              else if (word[0] == 'r' || word[0] == 'R')
+                {
+                  // Real value, next word is ID
+                  // Unsupported
+                  state = 1;
+                }
+            }
+          else if (state == 1 || word[0] == '1' || word[0] == '0')
+            {
+              // ID for preceding value or bit followed by ID
+              char id;
+              if (word[0] == '1')
+                {
+                  value = 1;
+                  id = word[1];
+                }
+              else if (word[0] == '0')
+                {
+                  value = 0;
+                  id = word[1];
+                }
+              else
+                id = word[0];
+
+              for (class cl_vcd_var *var = vars; var; var = var->next_var)
+                {
+                  if (var->var_id == id)
+                    {
+                      unsigned long ticks = uc->ticks->get_ticks();
+                      uc->ticks->set(ticks, event);
+                      //uc->sim->app->debug("vcd[%d]: set '%c' to 0x%u at %.15f now %.15f isless %s ULPs %u\n",
+                      //                    cl_hw::id, id, (value << var->bitnr_low) & var->bitmask, uc->ticks->get_rtime(), now, ULPs(now, event));
+                      var->cell->write((var->cell->get() & (~var->bitmask)) | ((value << var->bitnr_low) & var->bitmask));
+                      uc->ticks->set(ticks, now);
+                      event_occurred = true;
+                      break;
+                    }
+                }
+
+              state = 0;
+            }
+          else if (state == 2)
+            {
+              // ID for preceding value
+              // Unsupported
+              state = 0;
+            }
+        }
+    }
+
+  if (event_occurred && dobreak)
+    uc->vcd_break = true;
+
   return 0;
 }
 
 void
 cl_vcd::print_info(class cl_console_base *con)
 {
-  int i;
   con->dd_printf("%s[%d] value change dump\n", id_string, id);
-  con->dd_printf("Started: %s Paused: %s\n",
-		 started?"YES":"no",
-		 paused?"YES":"no");
-  const char *fn= fout?(fout->get_file_name()):"(none)";
-  con->dd_printf("Modul: %s File: %s\n", (char*)modul, fn);
-  con->dd_printf("Memory cells:\n");
-  for (i= 0; i < locs->count; i++)
+  con->dd_printf("  Modul:      %s\n", modul.c_str());
+  con->dd_printf("  Started:    %s\n", (started ? "YES" : "no"));
+  con->dd_printf("  Paused:     %s\n", (paused ? "YES" : "no"));
+  if (!application->quiet)
+    con->dd_printf("  File:       %s\n", (filename ? filename : "(none)"));
+
+  if (state != -1)
+    {
+      con->dd_printf("  Mode:       input\n");
+      con->dd_printf("  Break:      %s\n", (dobreak ? "enabled" : "disabled"));
+
+      if (timescale >= 1e-3)
+        con->dd_printf("  Time scale: %.0f ms\n", timescale * 1e3);
+      else if (timescale >= 1e-6)
+        con->dd_printf("  Time scale: %.0f us\n", timescale * 1e6);
+      else if (timescale >= 1e-9)
+        con->dd_printf("  Time scale: %.0f ns\n", timescale * 1e9);
+      else if (timescale >= 1e-12)
+        con->dd_printf("  Time scale: %.0f ps\n", timescale * 1e12);
+      else
+        con->dd_printf("  Time scale: %.0f fs\n", timescale * 1e15);
+    }
+  else
+    {
+      con->dd_printf("  Mode:       output\n");
+
+      if (!timescale)
+        con->dd_printf("  Time scale: auto set on start\n");
+      else
+        {
+          if (timescale >= 1e15)
+            con->dd_printf("  Time scale: %.0f fs\n", timescale * 1e-15);
+          else if (timescale >= 1e12)
+            con->dd_printf("  Time scale: %.0f ps\n", timescale * 1e-12);
+          else if (timescale >= 1e9)
+            con->dd_printf("  Time scale: %.0f ns\n", timescale * 1e-9);
+          else if (timescale >= 1e6)
+            con->dd_printf("  Time scale: %.0f us\n", timescale * 1e-6);
+          else
+            con->dd_printf("  Time scale: %.0f ms\n", timescale * 1e-3);
+        }
+    }
+
+  con->dd_printf("  Start time: %.15f s\n", starttime);
+  con->dd_printf("  %s event: %.15f s\n", (state != -1 ? "Next" : "Last"), event);
+  con->dd_printf("  Pause time: ");
+  if (pausetime >= 0)
+    con->dd_printf("%.15f s", pausetime);
+  con->dd_printf("\n  Simul time: %.15f s\n", uc->ticks->get_rtime());
+
+  con->dd_printf("  Variables:\n");
+  con->dd_printf("    Address           Symbol\n");
+  for (class cl_vcd_var *var = vars; var; var = var->next_var)
     {
-      cl_memory_cell *c= (cl_memory_cell*)(locs->at(i));
-      cl_address_space *as;
       t_addr a= 0;
-      as= uc->address_space(c, &a);
-      con->dd_printf("  %s[0x%x] %s\n", as?(as->get_name()):"?", AU(a), (char*)(uc->cell_name(c)));
+      cl_address_space *as = uc->address_space(var->cell, &a);
+
+      con->dd_printf("    %s[", (as ? as->get_name() : "?"));
+      con->dd_printf((as ? as->addr_format : "0x06x"), a);
+      con->dd_printf("]");
+      if (var->bitnr_high < 0)
+        con->dd_printf("      ");
+      else if (var->bitnr_high == var->bitnr_low)
+        con->dd_printf(".%d    ", var->bitnr_high);
+      else if (var->bitnr_low != 0 || var->bitnr_high != var->cell->get_width() - 1)
+        con->dd_printf("[%d:%d] ", var->bitnr_high, var->bitnr_low);
+      else
+        con->dd_printf("      ");
+
+      int i;
+
+      if (uc->vars->by_addr.search(as, a, var->bitnr_high, var->bitnr_low, i))
+        con->dd_printf("%s\n", uc->vars->by_addr.at(i)->get_name());
+      else
+        {
+          if (uc->vars->by_addr.search(as, a, -1, -1, i) ||
+              uc->vars->by_addr.search(as, a, var->cell->get_width() - 1, 0, i))
+            {
+              const char *cname = uc->vars->by_addr.at(i)->get_name();
+              con->dd_printf("%s", cname);
+              if (var->bitnr_high >= 0)
+                {
+                  if (var->bitnr_high == var->bitnr_low)
+                    con->dd_printf(".%d", var->bitnr_high);
+                  else if (var->bitnr_low != 0 || var->bitnr_high != var->cell->get_width() - 1)
+                    con->dd_printf("[%d:%d]", var->bitnr_high, var->bitnr_low);
+                }
+            }
+          con->dd_printf("\n");
+        }
     }
-  print_cfg_info(con);
+
+  //print_cfg_info(con);
 }
 
 
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/sim.src/vcdcl.h sdcc-4.2.0+dfsg/sim/ucsim/sim.src/vcdcl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/sim.src/vcdcl.h	2019-04-02 10:46:33.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/sim.src/vcdcl.h	2022-01-09 14:14:40.000000000 +0000
@@ -31,33 +31,53 @@
 #include "hwcl.h"
 
 
+class cl_vcd_var;
+
 class cl_vcd: public cl_hw
 {
- protected:
-  class cl_list *locs;
-  bool started, paused;
-  class cl_f *fout;
-  bool change;
-  double change_time;
+ private:
+  char var_id;
+  char *filename;
+  FILE *fd;
+  class cl_vcd_var *vars;
+  double starttime, timescale, event, pausetime;
+  int state;
+  bool started, paused, dobreak;
   chars modul;
+  char word[64];
+
  public:
   cl_vcd(class cl_uc *auc, int aid, chars aid_string);
+  int init(void);
+
+  inline bool is_running(void) const { return started && !paused; }
+
+  inline char get_next_var_id(void) { return var_id++; }
+
+  void set_cmd(class cl_cmdline *cmdline, class cl_console_base *con);
+
+  int tick(int cycles);
+
+  void report(class cl_vcd_var *var, t_mem v);
+  void print_info(class cl_console_base *con);
+
+ private:
+  inline void reset_next_var_id(void) { var_id = 33; }
+  void add_var(class cl_console_base *con, class cl_memory_cell *cell, int bitnr_low, int bitnr_high)
+    {
+      add_var(con, 0, cell, bitnr_low, bitnr_high);
+    }
+  void add_var(class cl_console_base *con, char id, class cl_memory_cell *cell, int bitnr_low, int bitnr_high);
+  void add_var(class cl_console_base *con, class cl_memory *m, t_addr a, int bitnr_low, int bitnr_high);
+  void del_var(class cl_console_base *con, class cl_memory_cell *cell, int bitnr_low, int bitnr_high);
+  void del_var(class cl_console_base *con, class cl_memory *m, t_addr a, int bitnr_low, int bitnr_high);
 
-  virtual void add(class cl_memory_cell *cell);
-  virtual bool add(class cl_memory *m, t_addr a, class cl_console_base *con);
-  virtual void del(class cl_memory_cell *cell);
-  virtual bool del(class cl_memory *m, t_addr a, class cl_console_base *con);
-  virtual void set_cmd(class cl_cmdline *cmdline, class cl_console_base *con);
-
-  virtual t_mem read(class cl_memory_cell *cell);
-  virtual void write(class cl_memory_cell *cell, t_mem *val);
-  virtual t_mem conf_op(cl_memory_cell *cell, t_addr addr, t_mem *val);
-  virtual char *cfg_help(t_addr addr);
-  
-  virtual void report(class cl_memory_cell *cell, int nr);
-  virtual int tick(int cycles);
+  FILE *open_vcd(class cl_console_base *con);
+  void close_vcd(void);
 
-  virtual void print_info(class cl_console_base *con);
+  bool read_word(unsigned int i);
+  void clear_vars(void);
+  bool parse_header(cl_console_base *con);
 };
 
 
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/st7.src/(c).1 sdcc-4.2.0+dfsg/sim/ucsim/st7.src/(c).1
--- sdcc-4.0.0+dfsg/sim/ucsim/st7.src/(c).1	2012-12-23 20:32:49.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/st7.src/(c).1	2020-09-17 06:45:33.000000000 +0000
@@ -1,25 +1,25 @@
-/*
- * Simulator of microcontrollers (@@F@@)
- *
- * Copyright (C) @@S@@,@@Y@@ Drotos Daniel, Talker Bt.
- * 
- * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
- *
- */
-
-/* This file is part of microcontroller simulator: ucsim.
-
-UCSIM is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2 of the License, or
-(at your option) any later version.
-
-UCSIM is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with UCSIM; see the file COPYING.  If not, write to the Free
-Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-02111-1307, USA. */
+/*
+ * Simulator of microcontrollers (@@F@@)
+ *
+ * Copyright (C) @@S@@,@@Y@@ Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/st7.src/clean.mk sdcc-4.2.0+dfsg/sim/ucsim/st7.src/clean.mk
--- sdcc-4.0.0+dfsg/sim/ucsim/st7.src/clean.mk	2012-12-23 20:32:49.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/st7.src/clean.mk	2021-09-19 19:38:05.000000000 +0000
@@ -1,26 +1,29 @@
-# Deleting all files created by building the program
-# --------------------------------------------------
-clean:
-	rm -f *core *[%~] *.[oa]
-	rm -f .[a-z]*~
-	rm -f sst7$(EXEEXT)
-
-
-# Deleting all files created by configuring or building the program
-# -----------------------------------------------------------------
-distclean: clean
-	rm -f config.cache config.log config.status
-	rm -f Makefile *.dep
-
-
-# Like clean but some files may still exist
-# -----------------------------------------
-mostlyclean: clean
-
-
-# Deleting everything that can reconstructed by this Makefile. It deletes
-# everything deleted by distclean plus files created by bison, etc.
-# -----------------------------------------------------------------------
-realclean: distclean
-
-# End of st7.src/clean.mk
+# Deleting all files created by building the program
+# --------------------------------------------------
+clean:
+	rm -f *core *[%~] *.[oa]
+	rm -f .[a-z]*~
+	rm -f sst7 sst7.exe
+	rm -f ucsim_st7 ucsim_st7.exe
+	$(MAKE) -C test -f clean.mk clean
+
+
+# Deleting all files created by configuring or building the program
+# -----------------------------------------------------------------
+distclean: clean
+	rm -f config.cache config.log config.status
+	rm -f Makefile *.dep
+	$(MAKE) -C test -f clean.mk distclean
+
+
+# Like clean but some files may still exist
+# -----------------------------------------
+mostlyclean: clean
+
+
+# Deleting everything that can reconstructed by this Makefile. It deletes
+# everything deleted by distclean plus files created by bison, etc.
+# -----------------------------------------------------------------------
+realclean: distclean
+
+# End of st7.src/clean.mk
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/st7.src/conf.mk sdcc-4.2.0+dfsg/sim/ucsim/st7.src/conf.mk
--- sdcc-4.0.0+dfsg/sim/ucsim/st7.src/conf.mk	2016-07-29 14:28:30.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/st7.src/conf.mk	2020-09-17 06:45:33.000000000 +0000
@@ -1,10 +1,10 @@
-#
-# Makefile targets to remake configuration
-#
-
-freshconf: Makefile
-
-Makefile: $(srcdir)/Makefile.in $(top_srcdir)/configure.ac
-	cd $(top_builddir) && $(SHELL) ./config.status
-
-# End of st7.src/conf.mk
+#
+# Makefile targets to remake configuration
+#
+
+freshconf: Makefile
+
+Makefile: $(srcdir)/Makefile.in $(top_srcdir)/configure.ac
+	cd $(top_builddir) && $(SHELL) ./config.status
+
+# End of st7.src/conf.mk
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/st7.src/glob.cc sdcc-4.2.0+dfsg/sim/ucsim/st7.src/glob.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/st7.src/glob.cc	2016-07-26 21:10:26.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/st7.src/glob.cc	2020-09-17 06:45:33.000000000 +0000
@@ -1,763 +1,763 @@
-/*
- * Simulator of microcontrollers (glob.cc)
- *
- * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
- * 
- * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
- *
- */
-
-/* This file is part of microcontroller simulator: ucsim.
-
-UCSIM is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2 of the License, or
-(at your option) any later version.
-
-UCSIM is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with UCSIM; see the file COPYING.  If not, write to the Free
-Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-02111-1307, USA. */
-/*@1@*/
-
-#include 
-
-#include "stypes.h"
-
-/* ST7 instructions described in PM0044
- *
- * 19.12.2012 - initial - ready for testing
- *
- */
-
-
-/*
-%d - direct addressing
-%x - extended addressing
-%p - pc relative addressing
-%b - unsigned byte immediate addressing
-%w - unsigned word immediate addressing
-%e - unsigned 24bit immediate addressing (extmem)
-%s - signed byte immediate
-%1 - unsigned byte index offset
-%2 - unsigned word index offset
-%3 - unsigned 24bit index offset
-*/
-
-/*  uint  code, mask;  char  branch;  uchar length;  char  *mnemonic; */
-
-/* vaclavpe - commented out is stuff from STM8 */
-
-struct dis_entry disass_st7[]= {
-//  { 0x0019, 0x00ff, ' ', 2, "adc A,(%1,SP)" },
-  { 0x00a9, 0x00ff, ' ', 2, "adc A,%b" },
-  { 0x00b9, 0x00ff, ' ', 2, "adc A,%d" },
-  { 0x00c9, 0x00ff, ' ', 3, "adc A,%x" },
-  { 0x00d9, 0x00ff, ' ', 3, "adc A,(%2,X)" },
-  { 0x00e9, 0x00ff, ' ', 2, "adc A,(%1,X)" },
-  { 0x00f9, 0x00ff, ' ', 1, "adc A,(X)" },
-
-//  { 0x001b, 0x00ff, ' ', 2, "add A,(%1,SP)" },
-  { 0x00ab, 0x00ff, ' ', 2, "add A,%b" },
-  { 0x00bb, 0x00ff, ' ', 2, "add A,%d" },
-  { 0x00cb, 0x00ff, ' ', 3, "add A,%x" },
-  { 0x00db, 0x00ff, ' ', 3, "add A,(%2,X)" },
-  { 0x00eb, 0x00ff, ' ', 2, "add A,(%1,X)" },
-  { 0x00fb, 0x00ff, ' ', 1, "add A,(X)" },
-//  { 0x005b, 0x00ff, ' ', 2, "add SP,%b" },
-
-//  { 0x001c, 0x00ff, ' ', 3, "addw X,%w" },
-
-//  { 0x0014, 0x00ff, ' ', 2, "and A,(%1,SP)" },
-  { 0x00a4, 0x00ff, ' ', 2, "and A,%b" },
-  { 0x00b4, 0x00ff, ' ', 2, "and A,%d" },
-  { 0x00c4, 0x00ff, ' ', 3, "and A,%x" },
-  { 0x00d4, 0x00ff, ' ', 3, "and A,(%2,X)" },
-  { 0x00e4, 0x00ff, ' ', 2, "and A,(%1,X)" },
-  { 0x00f4, 0x00ff, ' ', 1, "and A,(X)" },
-
-//  { 0x0015, 0x00ff, ' ', 2, "bcp A,(%1,SP)" },
-  { 0x00a5, 0x00ff, ' ', 2, "bcp A,%b" },
-  { 0x00b5, 0x00ff, ' ', 2, "bcp A,%d" },
-  { 0x00c5, 0x00ff, ' ', 3, "bcp A,%x" },
-  { 0x00d5, 0x00ff, ' ', 3, "bcp A,(%2,X)" },
-  { 0x00e5, 0x00ff, ' ', 2, "bcp A,(%1,X)" },
-  { 0x00f5, 0x00ff, ' ', 1, "bcp A,(X)" },
-
-  { 0x0011, 0x00ff, ' ', 2, "bres %d,#0" },
-  { 0x0013, 0x00ff, ' ', 2, "bres %d,#1" },
-  { 0x0015, 0x00ff, ' ', 2, "bres %d,#2" },
-  { 0x0017, 0x00ff, ' ', 2, "bres %d,#3" },
-  { 0x0019, 0x00ff, ' ', 2, "bres %d,#4" },
-  { 0x001b, 0x00ff, ' ', 2, "bres %d,#5" },
-  { 0x001d, 0x00ff, ' ', 2, "bres %d,#6" },
-  { 0x001f, 0x00ff, ' ', 2, "bres %d,#7" },
-
-  { 0x0010, 0x00ff, ' ', 2, "bset %d,#0" },
-  { 0x0012, 0x00ff, ' ', 2, "bset %d,#1" },
-  { 0x0014, 0x00ff, ' ', 2, "bset %d,#2" },
-  { 0x0016, 0x00ff, ' ', 2, "bset %d,#3" },
-  { 0x0018, 0x00ff, ' ', 2, "bset %d,#4" },
-  { 0x001a, 0x00ff, ' ', 2, "bset %d,#5" },
-  { 0x001c, 0x00ff, ' ', 2, "bset %d,#6" },
-  { 0x001e, 0x00ff, ' ', 2, "bset %d,#7" },
-
-  { 0x0001, 0x00ff, ' ', 3, "bjtf %d,#0,%p" },
-  { 0x0003, 0x00ff, ' ', 3, "bjtf %d,#1,%p" },
-  { 0x0005, 0x00ff, ' ', 3, "bjtf %d,#2,%p" },
-  { 0x0007, 0x00ff, ' ', 3, "bjtf %d,#3,%p" },
-  { 0x0009, 0x00ff, ' ', 3, "bjtf %d,#4,%p" },
-  { 0x000b, 0x00ff, ' ', 3, "bjtf %d,#5,%p" },
-  { 0x000d, 0x00ff, ' ', 3, "bjtf %d,#6,%p" },
-  { 0x000f, 0x00ff, ' ', 3, "bjtf %d,#7,%p" },
-
-  { 0x0000, 0x00ff, ' ', 3, "btjt %d,#0,%p" },
-  { 0x0002, 0x00ff, ' ', 3, "btjt %d,#1,%p" },
-  { 0x0004, 0x00ff, ' ', 3, "btjt %d,#2,%p" },
-  { 0x0006, 0x00ff, ' ', 3, "btjt %d,#3,%p" },
-  { 0x0008, 0x00ff, ' ', 3, "btjt %d,#4,%p" },
-  { 0x000a, 0x00ff, ' ', 3, "btjt %d,#5,%p" },
-  { 0x000c, 0x00ff, ' ', 3, "btjt %d,#6,%p" },

-  { 0x000e, 0x00ff, ' ', 3, "btjt %d,#7,%p" },

-

-  { 0x00bd, 0x00ff, ' ', 2, "call %d", true },

-  { 0x00cd, 0x00ff, ' ', 3, "call %x", true },

-  { 0x00dd, 0x00ff, ' ', 3, "call (%2,X)", true },

-  { 0x00ed, 0x00ff, ' ', 2, "call (%1,X)", true },

-  { 0x00fd, 0x00ff, ' ', 1, "call (X)", true },

-//  { 0x008d, 0x00ff, ' ', 4, "callf %e" },

-  { 0x00ad, 0x00ff, ' ', 2, "callr %p", true },

-

-//  { 0x008c, 0x00ff, ' ', 1, "ccf" },

-

-//  { 0x000f, 0x00ff, ' ', 2, "clr (%1,SP)" },
-  { 0x003f, 0x00ff, ' ', 2, "clr %d" },
-  { 0x004f, 0x00ff, ' ', 1, "clr A" },
-  { 0x006f, 0x00ff, ' ', 2, "clr (%1,X)" },
-  { 0x007f, 0x00ff, ' ', 1, "clr (X)" },
-  { 0x005f, 0x00ff, ' ', 1, "clr X" },
-
-//  { 0x0011, 0x00ff, ' ', 2, "cp A,(%1,SP)" },
-  { 0x00a1, 0x00ff, ' ', 2, "cp A,%b" },
-  { 0x00b1, 0x00ff, ' ', 2, "cp A,%d" },
-  { 0x00c1, 0x00ff, ' ', 3, "cp A,%x" },
-  { 0x00d1, 0x00ff, ' ', 3, "cp A,(%2,X)" },
-  { 0x00e1, 0x00ff, ' ', 2, "cp A,(%1,X)" },
-  { 0x00f1, 0x00ff, ' ', 1, "cp A,(X)" },
-//  { 0x0013, 0x00ff, ' ', 2, "cpw X,(%1,SP)" },
-  { 0x00a3, 0x00ff, ' ', 3, "cp X,%w" },
-  { 0x00b3, 0x00ff, ' ', 2, "cp X,%d" },
-  { 0x00c3, 0x00ff, ' ', 3, "cp X,%x" },
-  { 0x00d3, 0x00ff, ' ', 3, "cp X,(%2,X)" },
-  { 0x00e3, 0x00ff, ' ', 2, "cp X,(%1,X)" },
-  { 0x00f3, 0x00ff, ' ', 1, "cp X,(X)" },
-
-//  { 0x0003, 0x00ff, ' ', 2, "cpl (%1,SP)" },
-  { 0x0033, 0x00ff, ' ', 2, "cpl %d" },
-  { 0x0043, 0x00ff, ' ', 1, "cpl A" },
-  { 0x0063, 0x00ff, ' ', 2, "cpl (%1,X)" },
-  { 0x0073, 0x00ff, ' ', 1, "cpl (X)" },
-  { 0x0053, 0x00ff, ' ', 1, "cpl X" },
-
-//  { 0x000a, 0x00ff, ' ', 2, "dec (%1,SP)" },
-  { 0x003a, 0x00ff, ' ', 2, "dec %d" },
-  { 0x004a, 0x00ff, ' ', 1, "dec A" },
-  { 0x006a, 0x00ff, ' ', 2, "dec (%1,X)" },
-  { 0x007a, 0x00ff, ' ', 1, "dec (X)" },
-  { 0x005a, 0x00ff, ' ', 1, "dec X" },
-
-//  { 0x0062, 0x00ff, ' ', 1, "div X,A" },
-//  { 0x0065, 0x00ff, ' ', 1, "divw X,Y" },
-//  { 0x0031, 0x00ff, ' ', 3, "exg A,%x" },
-//  { 0x0041, 0x00ff, ' ', 1, "exg A,XL" },
-//  { 0x0051, 0x00ff, ' ', 1, "exgw X,Y" },
-//  { 0x0061, 0x00ff, ' ', 1, "exg A,YL" },
-  { 0x008e, 0x00ff, ' ', 1, "halt" },
-
-//  { 0x000c, 0x00ff, ' ', 2, "inc (%1,SP)" },
-  { 0x003c, 0x00ff, ' ', 2, "inc %d" },
-  { 0x004c, 0x00ff, ' ', 1, "inc A" },
-  { 0x006c, 0x00ff, ' ', 2, "inc (%1,X)" },
-  { 0x007c, 0x00ff, ' ', 1, "inc (X)" },
-  { 0x005c, 0x00ff, ' ', 1, "inc X" },
-
-  { 0x0080, 0x00ff, ' ', 1, "iret" },
-
-  { 0x00bc, 0x00ff, ' ', 2, "jp %d" },
-  { 0x00cc, 0x00ff, ' ', 3, "jp %x" },
-  { 0x00dc, 0x00ff, ' ', 3, "jp (%2,X)" },
-  { 0x00ec, 0x00ff, ' ', 2, "jp (%1,X)" },
-  { 0x00fc, 0x00ff, ' ', 1, "jp (X)" },
-//  { 0x00ad, 0x00ff, ' ', 4, "jpf %e" },
-  { 0x0020, 0x00ff, ' ', 2, "jra %p" },
-
-  { 0x0021, 0x00ff, ' ', 2, "jrf %p" },
-  { 0x0022, 0x00ff, ' ', 2, "jrugt %p" },
-  { 0x0023, 0x00ff, ' ', 2, "jrule %p" },
-  { 0x0024, 0x00ff, ' ', 2, "jruge %p" },
-  { 0x0025, 0x00ff, ' ', 2, "jrult %p" },
-  { 0x0026, 0x00ff, ' ', 2, "jrne %p" },
-  { 0x0027, 0x00ff, ' ', 2, "jreq %p" },
-  { 0x0028, 0x00ff, ' ', 2, "jrnh %p" },
-  { 0x0029, 0x00ff, ' ', 2, "jrh %p" },
-  { 0x002a, 0x00ff, ' ', 2, "jrpl %p" },
-  { 0x002b, 0x00ff, ' ', 2, "jrmi %p" },
-  { 0x002c, 0x00ff, ' ', 2, "jrnm %p" },
-  { 0x002d, 0x00ff, ' ', 2, "jrm %p" },
-  { 0x002e, 0x00ff, ' ', 2, "jril %p" },
-  { 0x002f, 0x00ff, ' ', 2, "jrih %p" },
-
-//  { 0x007b, 0x00ff, ' ', 2, "ld A,(%1,SP)" },
-  { 0x00a6, 0x00ff, ' ', 2, "ld A,%b" },
-  { 0x00b6, 0x00ff, ' ', 2, "ld A,%d" },
-  { 0x00c6, 0x00ff, ' ', 3, "ld A,%x" },
-  { 0x00d6, 0x00ff, ' ', 3, "ld A,(%2,X)" },
-  { 0x00e6, 0x00ff, ' ', 2, "ld A,(%1,X)" },
-  { 0x00f6, 0x00ff, ' ', 1, "ld A,(X)" },
-//  { 0x006b, 0x00ff, ' ', 2, "ld (%1,SP),A" },
-//  { 0x00a7, 0x00ff, ' ', 2, "ld %b,A" },
-  { 0x00b7, 0x00ff, ' ', 2, "ld %d,A" },
-  { 0x00c7, 0x00ff, ' ', 3, "ld %x,A" },
-  { 0x00d7, 0x00ff, ' ', 3, "ld (%2,X),A" },
-  { 0x00e7, 0x00ff, ' ', 2, "ld (%1,X),A" },
-  { 0x00f7, 0x00ff, ' ', 1, "ld (X),A" },
-  { 0x0093, 0x00ff, ' ', 1, "ld X,Y" },
-  { 0x0094, 0x00ff, ' ', 1, "ld S,X" },
-  { 0x0095, 0x00ff, ' ', 1, "ld S,A" },
-  { 0x0096, 0x00ff, ' ', 1, "ld X,S" },
-  { 0x0097, 0x00ff, ' ', 1, "ld X,A" },
-  { 0x009e, 0x00ff, ' ', 1, "ld A,S" },
-  { 0x009f, 0x00ff, ' ', 1, "ld A,X" },
-
-//  { 0x00a7, 0x00ff, ' ', 2, "ldf (%3,X),A" },
-//  { 0x00af, 0x00ff, ' ', 2, "ldf A,(%3,X)" },
-//  { 0x00bd, 0x00ff, ' ', 2, "ldf %e,A" },
-//  { 0x00bc, 0x00ff, ' ', 2, "ldf A,%e" },
-//  { 0x001e, 0x00ff, ' ', 2, "ldw X,(%1,SP)" },
-  { 0x00ae, 0x00ff, ' ', 2, "ld X,%b" },
-  { 0x00be, 0x00ff, ' ', 2, "ld X,%d" },
-  { 0x00ce, 0x00ff, ' ', 3, "ld X,%x" },
-  { 0x00de, 0x00ff, ' ', 3, "ld X,(%2,X)" },
-  { 0x00ee, 0x00ff, ' ', 2, "ld X,(%1,X)" },
-  { 0x00fe, 0x00ff, ' ', 1, "ld X,(X)" },
-//  { 0x001f, 0x00ff, ' ', 2, "ldw (%1,SP),X" },
-  { 0x00bf, 0x00ff, ' ', 2, "ld %d,X" },
-  { 0x00cf, 0x00ff, ' ', 3, "ld %x,X" },
-  { 0x00df, 0x00ff, ' ', 3, "ld (%2,X),Y" },
-  { 0x00ef, 0x00ff, ' ', 2, "ld (%1,X),Y" },
-  { 0x00ff, 0x00ff, ' ', 1, "ld (X),Y" },
-//  { 0x0016, 0x00ff, ' ', 2, "ldw Y,(%1,SP)" },
-//  { 0x0017, 0x00ff, ' ', 2, "ldw (%1,SP),Y" },
-
-//  { 0x0035, 0x00ff, ' ', 4, "mov %x,%b" },
-//  { 0x0045, 0x00ff, ' ', 3, "mov %d,%d" },
-//  { 0x0055, 0x00ff, ' ', 5, "mov %x,%x" },
-  { 0x0042, 0x00ff, ' ', 1, "mul X,A" },
-
-//  { 0x0000, 0x00ff, ' ', 2, "neg (%1,SP)" },
-  { 0x0030, 0x00ff, ' ', 2, "neg %d" },
-  { 0x0040, 0x00ff, ' ', 1, "neg A" },
-  { 0x0060, 0x00ff, ' ', 2, "neg (%1,X)" },
-  { 0x0070, 0x00ff, ' ', 1, "neg (X)" },
-  { 0x0050, 0x00ff, ' ', 1, "neg X" },
-
-  { 0x009d, 0x00ff, ' ', 1, "nop" },
-
-//  { 0x001a, 0x00ff, ' ', 2, "or A,(%1,SP)" },
-  { 0x00aa, 0x00ff, ' ', 2, "or A,%b" },
-  { 0x00ba, 0x00ff, ' ', 2, "or A,%d" },
-  { 0x00ca, 0x00ff, ' ', 3, "or A,%x" },
-  { 0x00da, 0x00ff, ' ', 3, "or A,(%2,X)" },
-  { 0x00ea, 0x00ff, ' ', 2, "or A,(%1,X)" },
-  { 0x00fa, 0x00ff, ' ', 1, "or A,(X)" },
-
-  { 0x0084, 0x00ff, ' ', 1, "pop A" },
-  { 0x0085, 0x00ff, ' ', 1, "pop X" },
-  { 0x0086, 0x00ff, ' ', 1, "pop CC" },
-//  { 0x0032, 0x00ff, ' ', 3, "pop %x" },
-  { 0x0088, 0x00ff, ' ', 1, "push A" },
-  { 0x0089, 0x00ff, ' ', 1, "push X" },
-  { 0x008a, 0x00ff, ' ', 1, "push CC" },
-//  { 0x003b, 0x00ff, ' ', 3, "push %x" },
-//  { 0x004b, 0x00ff, ' ', 2, "push %b" },
-
-  { 0x0098, 0x00ff, ' ', 1, "rcf" },
-  { 0x0081, 0x00ff, ' ', 1, "ret" },
-//  { 0x0087, 0x00ff, ' ', 1, "retf" },
-  { 0x009a, 0x00ff, ' ', 1, "rim" },
-
-//  { 0x0009, 0x00ff, ' ', 2, "rlc (%1,SP)" },
-  { 0x0039, 0x00ff, ' ', 2, "rlc %d" },
-  { 0x0049, 0x00ff, ' ', 1, "rlc A" },
-  { 0x0069, 0x00ff, ' ', 2, "rlc (%1,X)" },
-  { 0x0079, 0x00ff, ' ', 1, "rlc (X)" },
-  { 0x0059, 0x00ff, ' ', 1, "rlc X" },
-//  { 0x0002, 0x00ff, ' ', 1, "rlwa X,A" },
-//  { 0x0006, 0x00ff, ' ', 2, "rrc (%1,SP)" },
-  { 0x0036, 0x00ff, ' ', 2, "rrc %d" },
-  { 0x0046, 0x00ff, ' ', 1, "rrc A" },
-  { 0x0066, 0x00ff, ' ', 2, "rrc (%1,X)" },
-  { 0x0076, 0x00ff, ' ', 1, "rrc (X)" },
-  { 0x0056, 0x00ff, ' ', 1, "rrc X" },
-//  { 0x0001, 0x00ff, ' ', 1, "rrwa X,A" },
-
-  { 0x009c, 0x00ff, ' ', 1, "rsp" },
-
-//  { 0x0012, 0x00ff, ' ', 2, "sbc A,(%1,SP)" },
-  { 0x00a2, 0x00ff, ' ', 2, "sbc A,%b" },
-  { 0x00b2, 0x00ff, ' ', 2, "sbc A,%d" },
-  { 0x00c2, 0x00ff, ' ', 3, "sbc A,%x" },
-  { 0x00d2, 0x00ff, ' ', 3, "sbc A,(%2,X)" },
-  { 0x00e2, 0x00ff, ' ', 2, "sbc A,(%1,X)" },
-  { 0x00f2, 0x00ff, ' ', 1, "sbc A,(X)" },
-
-  { 0x0099, 0x00ff, ' ', 1, "scf" },
-  { 0x009b, 0x00ff, ' ', 1, "sim" },
-
-//  { 0x0008, 0x00ff, ' ', 2, "sla (%1,SP)" },
-  { 0x0038, 0x00ff, ' ', 2, "sla %d" },
-  { 0x0048, 0x00ff, ' ', 1, "sla A" },
-  { 0x0068, 0x00ff, ' ', 2, "sla (%1,X)" },
-  { 0x0078, 0x00ff, ' ', 1, "sla (X)" },
-  { 0x0058, 0x00ff, ' ', 1, "sla X" },
-//  { 0x0007, 0x00ff, ' ', 2, "sra (%1,SP)" },
-  { 0x0037, 0x00ff, ' ', 2, "sra %d" },
-  { 0x0047, 0x00ff, ' ', 1, "sra A" },
-  { 0x0067, 0x00ff, ' ', 2, "sra (%1,X)" },
-  { 0x0077, 0x00ff, ' ', 1, "sra (X)" },
-  { 0x0057, 0x00ff, ' ', 1, "sra X" },
-//  { 0x0004, 0x00ff, ' ', 2, "srl (%1,SP)" },
-  { 0x0034, 0x00ff, ' ', 2, "srl %d" },
-  { 0x0044, 0x00ff, ' ', 1, "srl A" },
-  { 0x0064, 0x00ff, ' ', 2, "srl (%1,X)" },
-  { 0x0074, 0x00ff, ' ', 1, "srl (X)" },
-  { 0x0054, 0x00ff, ' ', 1, "srl X" },
-
-//  { 0x0010, 0x00ff, ' ', 2, "sub A,(%1,SP)" },
-  { 0x00a0, 0x00ff, ' ', 2, "sub A,%b" },
-  { 0x00b0, 0x00ff, ' ', 2, "sub A,%d" },
-  { 0x00c0, 0x00ff, ' ', 3, "sub A,%x" },
-  { 0x00d0, 0x00ff, ' ', 3, "sub A,(%2,X)" },
-  { 0x00e0, 0x00ff, ' ', 2, "sub A,(%1,X)" },
-  { 0x00f0, 0x00ff, ' ', 1, "sub A,(X)" },
-//  { 0x0052, 0x00ff, ' ', 2, "sub SP,%b" },
-
-//  { 0x001d, 0x00ff, ' ', 3, "subw X,%w" },
-
-//  { 0x000e, 0x00ff, ' ', 2, "swap (%1,SP)" },
-  { 0x003e, 0x00ff, ' ', 2, "swap %d" },
-  { 0x004e, 0x00ff, ' ', 1, "swap A" },
-  { 0x006e, 0x00ff, ' ', 2, "swap (%1,X)" },
-  { 0x007e, 0x00ff, ' ', 1, "swap (X)" },
-  { 0x005e, 0x00ff, ' ', 1, "swapw X" },
-
-//  { 0x000d, 0x00ff, ' ', 2, "tnz (%1,SP)" },
-  { 0x003d, 0x00ff, ' ', 2, "tnz %d" },
-  { 0x004d, 0x00ff, ' ', 1, "tnz A" },
-  { 0x006d, 0x00ff, ' ', 2, "tnz (%1,X)" },
-  { 0x007d, 0x00ff, ' ', 1, "tnz (X)" },

-  { 0x005d, 0x00ff, ' ', 1, "tnz X" },

-

-  { 0x0083, 0x00ff, ' ', 1, "trap", true },

-  { 0x008f, 0x00ff, ' ', 1, "wfi" },

-

-//  { 0x0018, 0x00ff, ' ', 2, "xor A,(%1,SP)" },

-  { 0x00a8, 0x00ff, ' ', 2, "xor A,%b" },
-  { 0x00b8, 0x00ff, ' ', 2, "xor A,%d" },
-  { 0x00c8, 0x00ff, ' ', 3, "xor A,%x" },
-  { 0x00d8, 0x00ff, ' ', 3, "xor A,(%2,X)" },
-  { 0x00e8, 0x00ff, ' ', 2, "xor A,(%1,X)" },
-  { 0x00f8, 0x00ff, ' ', 1, "xor A,(X)" },
-
-  { 0, 0, 0, 0, NULL }
-};
-
-struct dis_entry disass_st7_90[]= {
-
-  { 0x00d9, 0x00ff, ' ', 3, "adc A,(%2,Y)" },
-  { 0x00e9, 0x00ff, ' ', 2, "adc A,(%1,Y)" },
-  { 0x00f9, 0x00ff, ' ', 1, "adc A,(Y)" },
-  { 0x00db, 0x00ff, ' ', 3, "add A,(%2,Y)" },
-  { 0x00eb, 0x00ff, ' ', 2, "add A,(%1,Y)" },
-  { 0x00fb, 0x00ff, ' ', 1, "add A,(Y)" },
-  { 0x00d4, 0x00ff, ' ', 3, "and A,(%2,Y)" },
-  { 0x00e4, 0x00ff, ' ', 2, "and A,(%1,Y)" },
-  { 0x00f4, 0x00ff, ' ', 1, "and A,(Y)" },
-  { 0x00d5, 0x00ff, ' ', 3, "bcp A,(%2,Y)" },
-  { 0x00e5, 0x00ff, ' ', 2, "bcp A,(%1,Y)" },
-  { 0x00f5, 0x00ff, ' ', 1, "bcp A,(Y)" },
-
-//  { 0x0011, 0x00ff, ' ', 3, "bccm %d,#0" },
-//  { 0x0013, 0x00ff, ' ', 3, "bccm %d,#1" },
-//  { 0x0015, 0x00ff, ' ', 3, "bccm %d,#2" },
-//  { 0x0017, 0x00ff, ' ', 3, "bccm %d,#3" },
-//  { 0x0019, 0x00ff, ' ', 3, "bccm %d,#4" },
-//  { 0x001b, 0x00ff, ' ', 3, "bccm %d,#5" },
-//  { 0x001d, 0x00ff, ' ', 3, "bccm %d,#6" },
-//  { 0x001f, 0x00ff, ' ', 3, "bccm %d,#7" },
-
-//  { 0x0010, 0x00ff, ' ', 3, "bcpl %d,#0" },
-//  { 0x0012, 0x00ff, ' ', 3, "bcpl %d,#1" },
-//  { 0x0014, 0x00ff, ' ', 3, "bcpl %d,#2" },
-//  { 0x0016, 0x00ff, ' ', 3, "bcpl %d,#3" },
-//  { 0x0018, 0x00ff, ' ', 3, "bcpl %d,#4" },
-//  { 0x001a, 0x00ff, ' ', 3, "bcpl %d,#5" },
-//  { 0x001c, 0x00ff, ' ', 3, "bcpl %d,#6" },

-//  { 0x001e, 0x00ff, ' ', 3, "bcpl %d,#7" },

-

-  { 0x00dd, 0x00ff, ' ', 3, "call (%2,Y)", true },

-  { 0x00ed, 0x00ff, ' ', 2, "call (%1,Y)", true },

-  { 0x00fd, 0x00ff, ' ', 1, "call (Y)", true },

-

-//  { 0x004f, 0x00ff, ' ', 3, "clr (%2,Y)" },

-  { 0x006f, 0x00ff, ' ', 2, "clr (%1,Y)" },

-  { 0x007f, 0x00ff, ' ', 1, "clr (Y)" },
-  { 0x005f, 0x00ff, ' ', 1, "clr Y" },
-
-  { 0x00d1, 0x00ff, ' ', 3, "cp A,(%2,Y)" },
-  { 0x00e1, 0x00ff, ' ', 2, "cp A,(%1,Y)" },
-  { 0x00f1, 0x00ff, ' ', 1, "cp A,(Y)" },
-  { 0x00a3, 0x00ff, ' ', 2, "cp Y,%b" },
-  { 0x00b3, 0x00ff, ' ', 2, "cp Y,%d" },
-  { 0x00c3, 0x00ff, ' ', 3, "cp Y,%x" },
-  { 0x00d3, 0x00ff, ' ', 3, "cp Y,(%2,Y)" },
-  { 0x00e3, 0x00ff, ' ', 2, "cp Y,(%1,Y)" },
-  { 0x00f3, 0x00ff, ' ', 1, "cp Y,(Y)" },
-
-//  { 0x0043, 0x00ff, ' ', 3, "cpl (%2,Y)" },
-  { 0x0063, 0x00ff, ' ', 2, "cpl (%1,Y)" },
-  { 0x0073, 0x00ff, ' ', 1, "cpl (Y)" },
-  { 0x0053, 0x00ff, ' ', 1, "cpl Y" },
-
-//  { 0x004a, 0x00ff, ' ', 3, "dec (%2,Y)" },
-  { 0x006a, 0x00ff, ' ', 2, "dec (%1,Y)" },
-  { 0x007a, 0x00ff, ' ', 1, "dec (Y)" },
-  { 0x005a, 0x00ff, ' ', 1, "dec Y" },
-
-//  { 0x0062, 0x00ff, ' ', 1, "div Y,A" },
-
-//  { 0x004c, 0x00ff, ' ', 3, "inc (%2,Y)" },
-  { 0x006c, 0x00ff, ' ', 2, "inc (%1,Y)" },
-  { 0x007c, 0x00ff, ' ', 1, "inc (Y)" },
-  { 0x005c, 0x00ff, ' ', 1, "inc Y" },
-
-  { 0x00dc, 0x00ff, ' ', 3, "jp (%2,Y)" },
-  { 0x00ec, 0x00ff, ' ', 2, "jp (%1,Y)" },
-  { 0x00fc, 0x00ff, ' ', 1, "jp (Y)" },
-
-  //{ 0x0028, 0x00ff, ' ', 2, "jrnh %p" },
-  //{ 0x0029, 0x00ff, ' ', 2, "jrh %p" },
-  //{ 0x002c, 0x00ff, ' ', 2, "jrnm %p" },
-  //{ 0x002d, 0x00ff, ' ', 2, "jrm %p" },
-  //{ 0x002e, 0x00ff, ' ', 2, "jril %p" },
-  //{ 0x002f, 0x00ff, ' ', 2, "jrih %p" },
-
-  { 0x00d6, 0x00ff, ' ', 3, "ld A,(%2,Y)" },
-  { 0x00e6, 0x00ff, ' ', 2, "ld A,(%1,Y)" },
-  { 0x00f6, 0x00ff, ' ', 1, "ld A,(Y)" },
-  { 0x00d7, 0x00ff, ' ', 3, "ld (%2,Y),A" },
-  { 0x00e7, 0x00ff, ' ', 2, "ld (%1,Y),A" },
-  { 0x00f7, 0x00ff, ' ', 1, "ld (Y),A" },
-
-  { 0x0093, 0x00ff, ' ', 1, "ld Y,X" },
-  { 0x0094, 0x00ff, ' ', 1, "ld S,Y" },
-  { 0x0096, 0x00ff, ' ', 1, "ld Y,S" },
-  { 0x0097, 0x00ff, ' ', 1, "ld Y,A" },
-  { 0x009f, 0x00ff, ' ', 1, "ld A,Y" },
-//  { 0x00a7, 0x00ff, ' ', 2, "ldf (%e,Y),A" },
-//  { 0x00af, 0x00ff, ' ', 2, "ldf A,(%e,Y)" },
-  { 0x00ae, 0x00ff, ' ', 2, "ld Y,%b" },
-  { 0x00be, 0x00ff, ' ', 2, "ld Y,%d" },
-  { 0x00ce, 0x00ff, ' ', 3, "ld Y,%x" },
-  { 0x00de, 0x00ff, ' ', 3, "ld Y,(%2,Y)" },
-  { 0x00ee, 0x00ff, ' ', 2, "ld Y,(%1,Y)" },
-  { 0x00fe, 0x00ff, ' ', 1, "ld Y,(Y)" },
-
-  { 0x00bf, 0x00ff, ' ', 2, "ld %d,Y" },
-  { 0x00cf, 0x00ff, ' ', 3, "ld %x,Y" },
-  { 0x00df, 0x00ff, ' ', 3, "ld (%2,Y),Y" },
-  { 0x00ef, 0x00ff, ' ', 2, "ld (%1,Y),Y" },
-  { 0x00ff, 0x00ff, ' ', 1, "ld (Y),Y" },
-
-  { 0x0042, 0x00ff, ' ', 1, "mul Y,A" },
-
-//  { 0x0040, 0x00ff, ' ', 3, "neg (%2,Y)" },
-  { 0x0060, 0x00ff, ' ', 2, "neg (%1,Y)" },
-  { 0x0070, 0x00ff, ' ', 1, "neg (Y)" },
-  { 0x0050, 0x00ff, ' ', 1, "neg Y" },
-
-  { 0x00da, 0x00ff, ' ', 3, "or A,(%2,Y)" },
-  { 0x00ea, 0x00ff, ' ', 2, "or A,(%1,Y)" },
-  { 0x00fa, 0x00ff, ' ', 1, "or A,(Y)" },
-
-  { 0x0085, 0x00ff, ' ', 1, "pop Y" },
-  { 0x0089, 0x00ff, ' ', 1, "push Y" },
-
-//  { 0x0049, 0x00ff, ' ', 3, "rlc (%2,Y)" },
-  { 0x0069, 0x00ff, ' ', 2, "rlc (%1,Y)" },
-  { 0x0079, 0x00ff, ' ', 1, "rlc (Y)" },
-  { 0x0059, 0x00ff, ' ', 1, "rlc Y" },
-//  { 0x0002, 0x00ff, ' ', 1, "rlwa Y,A" },
-//  { 0x0046, 0x00ff, ' ', 3, "rrc (%2,Y)" },
-  { 0x0066, 0x00ff, ' ', 2, "rrc (%1,Y)" },
-  { 0x0076, 0x00ff, ' ', 1, "rrc (Y)" },
-  { 0x0056, 0x00ff, ' ', 1, "rrc Y" },
-//  { 0x0001, 0x00ff, ' ', 1, "rrwa Y,A" },
-  
-  { 0x00d2, 0x00ff, ' ', 3, "sbc A,(%2,Y)" },
-  { 0x00e2, 0x00ff, ' ', 2, "sbc A,(%1,Y)" },
-  { 0x00f2, 0x00ff, ' ', 1, "sbc A,(Y)" },
-
-//  { 0x0048, 0x00ff, ' ', 3, "sla (%2,Y)" },
-  { 0x0068, 0x00ff, ' ', 2, "sla (%1,Y)" },
-  { 0x0078, 0x00ff, ' ', 1, "sla (Y)" },
-  { 0x0058, 0x00ff, ' ', 1, "sla Y" },
-//  { 0x0047, 0x00ff, ' ', 3, "sra (%2,Y)" },
-  { 0x0067, 0x00ff, ' ', 2, "sra (%1,Y)" },
-  { 0x0077, 0x00ff, ' ', 1, "sra (Y)" },
-  { 0x0057, 0x00ff, ' ', 1, "sra Y" },
-//  { 0x0044, 0x00ff, ' ', 3, "srl (%2,Y)" },
-  { 0x0064, 0x00ff, ' ', 2, "srl (%1,Y)" },
-  { 0x0074, 0x00ff, ' ', 1, "srl (Y)" },
-  { 0x0054, 0x00ff, ' ', 1, "srl Y" },
-
-  { 0x00d0, 0x00ff, ' ', 3, "sub A,(%2,Y)" },
-  { 0x00e0, 0x00ff, ' ', 2, "sub A,(%1,Y)" },
-  { 0x00f0, 0x00ff, ' ', 1, "sub A,(Y)" },
-
-//  { 0x004e, 0x00ff, ' ', 3, "swap (%2,Y)" },
-  { 0x006e, 0x00ff, ' ', 2, "swap (%1,Y)" },
-  { 0x007e, 0x00ff, ' ', 1, "swap (Y)" },
-  { 0x005e, 0x00ff, ' ', 1, "swap Y" },
-
-//  { 0x004d, 0x00ff, ' ', 3, "tnz (%2,Y)" },
-  { 0x006d, 0x00ff, ' ', 2, "tnz (%1,Y)" },
-  { 0x007d, 0x00ff, ' ', 1, "tnz (Y)" },
-  { 0x005d, 0x00ff, ' ', 1, "tnz Y" },
-
-  { 0x00d8, 0x00ff, ' ', 3, "xor A,(%2,Y)" },
-  { 0x00e8, 0x00ff, ' ', 2, "xor A,(%1,Y)" },
-  { 0x00f8, 0x00ff, ' ', 1, "xor A,(Y)" },
-
-  { 0, 0, 0, 0, NULL }
-};
-
-struct dis_entry disass_st7_91[]= {
-
-  { 0x00d9, 0x00ff, ' ', 2, "adc A,([%1.w],Y)" },
-  { 0x00e9, 0x00ff, ' ', 2, "adc A,([%1],Y)" },
-  { 0x00db, 0x00ff, ' ', 2, "add A,([%1.w],Y)" },
-  { 0x00eb, 0x00ff, ' ', 2, "add A,([%1],Y)" },
-  { 0x00d4, 0x00ff, ' ', 2, "and A,([%1.w],Y)" },
-  { 0x00e4, 0x00ff, ' ', 2, "and A,([%1],Y)" },

-  { 0x00d5, 0x00ff, ' ', 2, "bcp A,([%1.w],Y)" },

-  { 0x00e5, 0x00ff, ' ', 2, "bcp A,([%1],Y)" },

-  { 0x00dd, 0x00ff, ' ', 2, "call ([%1.w],Y)", true },

-  { 0x00ed, 0x00ff, ' ', 2, "call ([%1],Y)", true },

-  { 0x006f, 0x00ff, ' ', 2, "clr ([%1],Y)" },

-  { 0x00d1, 0x00ff, ' ', 2, "cp A,([%1.w],Y)" },

-  { 0x00e1, 0x00ff, ' ', 2, "cp A,([%1],Y)" },

-  { 0x00b3, 0x00ff, ' ', 2, "cp Y,[%1]" },
-  { 0x00c3, 0x00ff, ' ', 2, "cp Y,[%1.w]" },
-  { 0x00d3, 0x00ff, ' ', 2, "cp Y,([%1.w],Y)" },
-  { 0x00e3, 0x00ff, ' ', 2, "cp Y,([%1],Y)" },
-  { 0x0063, 0x00ff, ' ', 2, "cpl ([%1],Y)" },
-  { 0x006a, 0x00ff, ' ', 2, "dec ([%1],Y)" },
-  { 0x006c, 0x00ff, ' ', 2, "inc ([%1],Y)" },
-  { 0x00dc, 0x00ff, ' ', 2, "jp ([%1.w],Y)" },
-  { 0x00ec, 0x00ff, ' ', 2, "jp ([%1],Y)" },
-  { 0x00d6, 0x00ff, ' ', 2, "ld A,([%1.w],Y)" },
-  { 0x00e6, 0x00ff, ' ', 2, "ld A,([%1],Y)" },
-  { 0x00d7, 0x00ff, ' ', 2, "ld ([%1.w],Y),A" },
-  { 0x00e7, 0x00ff, ' ', 2, "ld ([%1],Y),A" },
-//  { 0x00a7, 0x00ff, ' ', 2, "ldf ([%2.e],Y),A" },
-//  { 0x00af, 0x00ff, ' ', 2, "ldf A,([%2.e],Y)" },
-  { 0x00be, 0x00ff, ' ', 3, "ld Y,[%1]" },
-  { 0x00ce, 0x00ff, ' ', 3, "ld Y,[%1.w]" },
-  { 0x00de, 0x00ff, ' ', 3, "ld Y,([%1.w],Y)" },
-  { 0x00ee, 0x00ff, ' ', 3, "ld Y,([%1],Y)" },
-  { 0x00bf, 0x00ff, ' ', 3, "ld [%1],Y" },
-  { 0x00cf, 0x00ff, ' ', 3, "ld [%1.w],Y" },
-  { 0x00df, 0x00ff, ' ', 3, "ld ([%1.w],Y),Y" },
-  { 0x00ef, 0x00ff, ' ', 3, "ld ([%1],Y),Y" },
-  { 0x0060, 0x00ff, ' ', 2, "neg ([%1],Y)" },
-  { 0x00da, 0x00ff, ' ', 2, "or A,([%1.w],Y)" },
-  { 0x00ea, 0x00ff, ' ', 2, "or A,([%1],Y)" },
-  { 0x0069, 0x00ff, ' ', 2, "rlc ([%1],Y)" },
-  { 0x0066, 0x00ff, ' ', 2, "rrc ([%1],Y)" },
-  { 0x00d2, 0x00ff, ' ', 2, "sbc A,([%1.w],Y)" },
-  { 0x00e2, 0x00ff, ' ', 2, "sbc A,([%1],Y)" },
-  { 0x0068, 0x00ff, ' ', 2, "sla ([%1],Y)" },
-  { 0x0067, 0x00ff, ' ', 2, "sra ([%1],Y)" },
-  { 0x0064, 0x00ff, ' ', 2, "srl ([%1],Y)" },
-  { 0x00d0, 0x00ff, ' ', 2, "sub A,([%1.w],Y)" },
-  { 0x00e0, 0x00ff, ' ', 2, "sub A,([%1],Y)" },
-  { 0x006e, 0x00ff, ' ', 2, "swap ([%1],Y)" },
-  { 0x006d, 0x00ff, ' ', 2, "tnz ([%1],Y)" },
-  { 0x00d8, 0x00ff, ' ', 2, "xor A,([%1.w],Y)" },
-  { 0x00e8, 0x00ff, ' ', 2, "xor A,([%1],Y)" },
-
-  { 0, 0, 0, 0, NULL }
-};
-
-struct dis_entry disass_st7_92[]= {
-
-  { 0x00b9, 0x00ff, ' ', 2, "adc A,[%1]" },
-  { 0x00c9, 0x00ff, ' ', 2, "adc A,[%1.w]" },
-  { 0x00d9, 0x00ff, ' ', 2, "adc A,([%1.w],X)" },
-  { 0x00e9, 0x00ff, ' ', 2, "adc A,([%1],X)" },
-  { 0x00bb, 0x00ff, ' ', 2, "add A,[%1]" },
-  { 0x00cb, 0x00ff, ' ', 2, "add A,[%1.w]" },
-  { 0x00db, 0x00ff, ' ', 2, "add A,([%1.w],X)" },
-  { 0x00eb, 0x00ff, ' ', 2, "add A,([%1],X)" },
-  { 0x00b4, 0x00ff, ' ', 2, "and A,[%1]" },
-  { 0x00c4, 0x00ff, ' ', 2, "and A,[%1.w]" },
-  { 0x00d4, 0x00ff, ' ', 2, "and A,([%1.w],X)" },
-  { 0x00e4, 0x00ff, ' ', 2, "and A,([%1],X)" },
-  { 0x00b5, 0x00ff, ' ', 2, "bcp A,[%1]" },
-  { 0x00c5, 0x00ff, ' ', 2, "bcp A,[%1.w]" },
-  { 0x00d5, 0x00ff, ' ', 2, "bcp A,([%1.w],X)" },
-  { 0x00e5, 0x00ff, ' ', 2, "bcp A,([%1],X)" },
-
-  { 0x0011, 0x00ff, ' ', 2, "bres [%1],#0" },
-  { 0x0013, 0x00ff, ' ', 2, "bres [%1],#1" },
-  { 0x0015, 0x00ff, ' ', 2, "bres [%1],#2" },
-  { 0x0017, 0x00ff, ' ', 2, "bres [%1],#3" },
-  { 0x0019, 0x00ff, ' ', 2, "bres [%1],#4" },
-  { 0x001b, 0x00ff, ' ', 2, "bres [%1],#5" },
-  { 0x001d, 0x00ff, ' ', 2, "bres [%1],#6" },
-  { 0x001f, 0x00ff, ' ', 2, "bres [%1],#7" },
-
-  { 0x0010, 0x00ff, ' ', 2, "bset [%1],#0" },
-  { 0x0012, 0x00ff, ' ', 2, "bset [%1],#1" },
-  { 0x0014, 0x00ff, ' ', 2, "bset [%1],#2" },
-  { 0x0016, 0x00ff, ' ', 2, "bset [%1],#3" },
-  { 0x0018, 0x00ff, ' ', 2, "bset [%1],#4" },
-  { 0x001a, 0x00ff, ' ', 2, "bset [%1],#5" },
-  { 0x001c, 0x00ff, ' ', 2, "bset [%1],#6" },
-  { 0x001e, 0x00ff, ' ', 2, "bset [%1],#7" },
-
-  { 0x0001, 0x00ff, ' ', 3, "bjtf [%1],#0,%p" },
-  { 0x0003, 0x00ff, ' ', 3, "bjtf [%1],#1,%p" },
-  { 0x0005, 0x00ff, ' ', 3, "bjtf [%1],#2,%p" },
-  { 0x0007, 0x00ff, ' ', 3, "bjtf [%1],#3,%p" },
-  { 0x0009, 0x00ff, ' ', 3, "bjtf [%1],#4,%p" },
-  { 0x000b, 0x00ff, ' ', 3, "bjtf [%1],#5,%p" },
-  { 0x000d, 0x00ff, ' ', 3, "bjtf [%1],#6,%p" },
-  { 0x000f, 0x00ff, ' ', 3, "bjtf [%1],#7,%p" },
-
-  { 0x0000, 0x00ff, ' ', 3, "btjt [%1],#0,%p" },
-  { 0x0002, 0x00ff, ' ', 3, "btjt [%1],#1,%p" },
-  { 0x0004, 0x00ff, ' ', 3, "btjt [%1],#2,%p" },
-  { 0x0006, 0x00ff, ' ', 3, "btjt [%1],#3,%p" },
-  { 0x0008, 0x00ff, ' ', 3, "btjt [%1],#4,%p" },
-  { 0x000a, 0x00ff, ' ', 3, "btjt [%1],#5,%p" },
-  { 0x000c, 0x00ff, ' ', 3, "btjt [%1],#6,%p" },

-  { 0x000e, 0x00ff, ' ', 3, "btjt [%1],#7,%p" },

-

-  { 0x00cd, 0x00ff, ' ', 2, "call [%1]", true },

-  { 0x00cd, 0x00ff, ' ', 2, "call [%1.w]", true },

-  { 0x00dd, 0x00ff, ' ', 2, "call ([%1.w],X)", true },

-  { 0x00dd, 0x00ff, ' ', 2, "call ([%1],X)", true },

-  { 0x00ad, 0x00ff, ' ', 2, "callr [%1]", true },

-//  { 0x008d, 0x00ff, ' ', 3, "callf [%2.e]", true },

-  { 0x003f, 0x00ff, ' ', 2, "clr [%1]" },

-  { 0x006f, 0x00ff, ' ', 2, "clr ([%1],X)" },

-  { 0x00b1, 0x00ff, ' ', 2, "cp A,[%1]" },

-  { 0x00c1, 0x00ff, ' ', 2, "cp A,[%1.w]" },
-  { 0x00d1, 0x00ff, ' ', 2, "cp A,([%1.w],X)" },
-  { 0x00e1, 0x00ff, ' ', 2, "cp A,([%1],X)" },
-  { 0x00b3, 0x00ff, ' ', 2, "cp X,[%1.w]" },
-  { 0x00c3, 0x00ff, ' ', 2, "cp X,[%1.w]" },
-  { 0x00d3, 0x00ff, ' ', 2, "cp X,([%1.w],X)" },
-  { 0x00e3, 0x00ff, ' ', 2, "cp X,([%1.w],X)" },
-  { 0x0033, 0x00ff, ' ', 2, "cpl [%1]" },
-  { 0x0063, 0x00ff, ' ', 2, "cpl ([%1],X)" },
-  { 0x003a, 0x00ff, ' ', 2, "dec [%1]" },
-  { 0x006a, 0x00ff, ' ', 2, "dec ([%1],X)" },
-  { 0x003c, 0x00ff, ' ', 2, "inc [%1]" },
-  { 0x006c, 0x00ff, ' ', 2, "inc ([%1],X)" },
-  { 0x00bc, 0x00ff, ' ', 2, "jp [%1]" },
-  { 0x00cc, 0x00ff, ' ', 2, "jp [%1.w]" },
-  { 0x00dc, 0x00ff, ' ', 2, "jp ([%1.w],X)" },
-  { 0x00ec, 0x00ff, ' ', 2, "jp ([%1],X)" },
-//  { 0x00ac, 0x00ff, ' ', 3, "jpf [%2.e]" },
-  { 0x0020, 0x00ff, ' ', 2, "jra [%1]" },
-
-  { 0x0021, 0x00ff, ' ', 2, "jrf [%1]" },
-  { 0x0022, 0x00ff, ' ', 2, "jrugt [%1]" },
-  { 0x0023, 0x00ff, ' ', 2, "jrule [%1]" },
-  { 0x0024, 0x00ff, ' ', 2, "jruge [%1]" },
-  { 0x0025, 0x00ff, ' ', 2, "jrult [%1]" },
-  { 0x0026, 0x00ff, ' ', 2, "jrne [%1]" },
-  { 0x0027, 0x00ff, ' ', 2, "jreq [%1]" },
-  { 0x0028, 0x00ff, ' ', 2, "jrnh [%1]" },
-  { 0x0029, 0x00ff, ' ', 2, "jrh [%1]" },
-  { 0x002a, 0x00ff, ' ', 2, "jrpl [%1]" },
-  { 0x002b, 0x00ff, ' ', 2, "jrmi [%1]" },
-  { 0x002c, 0x00ff, ' ', 2, "jrnm [%1]" },
-  { 0x002d, 0x00ff, ' ', 2, "jrm [%1]" },
-  { 0x002e, 0x00ff, ' ', 2, "jril [%1]" },
-  { 0x002f, 0x00ff, ' ', 2, "jrih [%1]" },
-
-  { 0x00b6, 0x00ff, ' ', 2, "ld A,[%1]" },
-  { 0x00c6, 0x00ff, ' ', 2, "ld A,[%1.w]" },
-  { 0x00d6, 0x00ff, ' ', 2, "ld A,([%1.w],X)" },
-  { 0x00e6, 0x00ff, ' ', 2, "ld A,([%1],X)" },
-  { 0x00b7, 0x00ff, ' ', 2, "ld [%1],A" },
-  { 0x00c7, 0x00ff, ' ', 2, "ld [%1.w],A" },
-  { 0x00d7, 0x00ff, ' ', 2, "ld ([%1.w],X),A" },
-  { 0x00e7, 0x00ff, ' ', 2, "ld ([%1],X),A" },
-//  { 0x00a7, 0x00ff, ' ', 2, "ldf ([%2.e],X),A" },
-//  { 0x00af, 0x00ff, ' ', 2, "ldf A,([%2.e],X)" },
-  { 0x00be, 0x00ff, ' ', 2, "ld X,[%1]" },
-  { 0x00ce, 0x00ff, ' ', 2, "ld X,[%1.w]" },
-  { 0x00de, 0x00ff, ' ', 2, "ld X,([%1.w],X)" },
-  { 0x00ee, 0x00ff, ' ', 2, "ld X,([%1],X)" },
-  { 0x00bf, 0x00ff, ' ', 2, "ld [%1],X" },
-  { 0x00cf, 0x00ff, ' ', 2, "ld [%1.w],X" },
-  { 0x00df, 0x00ff, ' ', 2, "ld ([%1.w],X),X" },
-  { 0x00ef, 0x00ff, ' ', 2, "ld ([%1],X),X" },
-
-  { 0x0030, 0x00ff, ' ', 2, "neg [%1]" },
-  { 0x0060, 0x00ff, ' ', 2, "neg ([%1],X)" },
-  { 0x00ba, 0x00ff, ' ', 2, "or A,[%1]" },
-  { 0x00ca, 0x00ff, ' ', 2, "or A,[%1.w]" },
-  { 0x00da, 0x00ff, ' ', 2, "or A,([%1.w],X)" },
-  { 0x00ea, 0x00ff, ' ', 2, "or A,([%1],X)" },
-  { 0x0039, 0x00ff, ' ', 2, "rlc [%1]" },
-  { 0x0069, 0x00ff, ' ', 2, "rlc ([%1],X)" },
-  { 0x0036, 0x00ff, ' ', 2, "rrc [%1]" },
-  { 0x0066, 0x00ff, ' ', 2, "rrc ([%1],X)" },
-  { 0x00b2, 0x00ff, ' ', 2, "sbc A,[%1]" },
-  { 0x00c2, 0x00ff, ' ', 2, "sbc A,[%1.w]" },
-  { 0x00d2, 0x00ff, ' ', 2, "sbc A,([%1.w],X)" },
-  { 0x00e2, 0x00ff, ' ', 2, "sbc A,([%1],X)" },
-  { 0x0038, 0x00ff, ' ', 2, "sla [%1]" },
-  { 0x0068, 0x00ff, ' ', 2, "sla ([%1],X)" },
-  { 0x0037, 0x00ff, ' ', 2, "sra [%1]" },
-  { 0x0067, 0x00ff, ' ', 2, "sra ([%1],X)" },
-  { 0x0034, 0x00ff, ' ', 2, "srl [%1]" },
-  { 0x0064, 0x00ff, ' ', 2, "srl ([%1],X)" },
-  { 0x00b0, 0x00ff, ' ', 2, "sub A,[%1]" },
-  { 0x00c0, 0x00ff, ' ', 2, "sub A,[%1.w]" },
-  { 0x00d0, 0x00ff, ' ', 2, "sub A,([%1.w],X)" },
-  { 0x00e0, 0x00ff, ' ', 2, "sub A,([%1],X)" },
-  { 0x003e, 0x00ff, ' ', 2, "swap [%1]" },
-  { 0x006e, 0x00ff, ' ', 2, "swap ([%1],X)" },
-  { 0x003d, 0x00ff, ' ', 2, "tnz [%1]" },
-  { 0x006d, 0x00ff, ' ', 2, "tnz ([%1],X)" },
-  { 0x00b8, 0x00ff, ' ', 2, "xor A,[%1]" },
-  { 0x00c8, 0x00ff, ' ', 2, "xor A,[%1.w]" },
-  { 0x00d8, 0x00ff, ' ', 2, "xor A,([%1.w],X)" },
-  { 0x00e8, 0x00ff, ' ', 2, "xor A,([%1],X)" },
-
-  { 0, 0, 0, 0, NULL }
-};
-
-/* glob.cc */
+/*
+ * Simulator of microcontrollers (glob.cc)
+ *
+ * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#include 
+
+#include "stypes.h"
+
+/* ST7 instructions described in PM0044
+ *
+ * 19.12.2012 - initial - ready for testing
+ *
+ */
+
+
+/*
+%d - direct addressing
+%x - extended addressing
+%p - pc relative addressing
+%b - unsigned byte immediate addressing
+%w - unsigned word immediate addressing
+%e - unsigned 24bit immediate addressing (extmem)
+%s - signed byte immediate
+%1 - unsigned byte index offset
+%2 - unsigned word index offset
+%3 - unsigned 24bit index offset
+*/
+
+/*  uint  code, mask;  char  branch;  uchar length;  char  *mnemonic; */
+
+/* vaclavpe - commented out is stuff from STM8 */
+
+struct dis_entry disass_st7[]= {
+//  { 0x0019, 0x00ff, ' ', 2, "adc A,(%1,SP)" },
+  { 0x00a9, 0x00ff, ' ', 2, "adc A,%b" },
+  { 0x00b9, 0x00ff, ' ', 2, "adc A,%d" },
+  { 0x00c9, 0x00ff, ' ', 3, "adc A,%x" },
+  { 0x00d9, 0x00ff, ' ', 3, "adc A,(%2,X)" },
+  { 0x00e9, 0x00ff, ' ', 2, "adc A,(%1,X)" },
+  { 0x00f9, 0x00ff, ' ', 1, "adc A,(X)" },
+
+//  { 0x001b, 0x00ff, ' ', 2, "add A,(%1,SP)" },
+  { 0x00ab, 0x00ff, ' ', 2, "add A,%b" },
+  { 0x00bb, 0x00ff, ' ', 2, "add A,%d" },
+  { 0x00cb, 0x00ff, ' ', 3, "add A,%x" },
+  { 0x00db, 0x00ff, ' ', 3, "add A,(%2,X)" },
+  { 0x00eb, 0x00ff, ' ', 2, "add A,(%1,X)" },
+  { 0x00fb, 0x00ff, ' ', 1, "add A,(X)" },
+//  { 0x005b, 0x00ff, ' ', 2, "add SP,%b" },
+
+//  { 0x001c, 0x00ff, ' ', 3, "addw X,%w" },
+
+//  { 0x0014, 0x00ff, ' ', 2, "and A,(%1,SP)" },
+  { 0x00a4, 0x00ff, ' ', 2, "and A,%b" },
+  { 0x00b4, 0x00ff, ' ', 2, "and A,%d" },
+  { 0x00c4, 0x00ff, ' ', 3, "and A,%x" },
+  { 0x00d4, 0x00ff, ' ', 3, "and A,(%2,X)" },
+  { 0x00e4, 0x00ff, ' ', 2, "and A,(%1,X)" },
+  { 0x00f4, 0x00ff, ' ', 1, "and A,(X)" },
+
+//  { 0x0015, 0x00ff, ' ', 2, "bcp A,(%1,SP)" },
+  { 0x00a5, 0x00ff, ' ', 2, "bcp A,%b" },
+  { 0x00b5, 0x00ff, ' ', 2, "bcp A,%d" },
+  { 0x00c5, 0x00ff, ' ', 3, "bcp A,%x" },
+  { 0x00d5, 0x00ff, ' ', 3, "bcp A,(%2,X)" },
+  { 0x00e5, 0x00ff, ' ', 2, "bcp A,(%1,X)" },
+  { 0x00f5, 0x00ff, ' ', 1, "bcp A,(X)" },
+
+  { 0x0011, 0x00ff, ' ', 2, "bres %d,#0" },
+  { 0x0013, 0x00ff, ' ', 2, "bres %d,#1" },
+  { 0x0015, 0x00ff, ' ', 2, "bres %d,#2" },
+  { 0x0017, 0x00ff, ' ', 2, "bres %d,#3" },
+  { 0x0019, 0x00ff, ' ', 2, "bres %d,#4" },
+  { 0x001b, 0x00ff, ' ', 2, "bres %d,#5" },
+  { 0x001d, 0x00ff, ' ', 2, "bres %d,#6" },
+  { 0x001f, 0x00ff, ' ', 2, "bres %d,#7" },
+
+  { 0x0010, 0x00ff, ' ', 2, "bset %d,#0" },
+  { 0x0012, 0x00ff, ' ', 2, "bset %d,#1" },
+  { 0x0014, 0x00ff, ' ', 2, "bset %d,#2" },
+  { 0x0016, 0x00ff, ' ', 2, "bset %d,#3" },
+  { 0x0018, 0x00ff, ' ', 2, "bset %d,#4" },
+  { 0x001a, 0x00ff, ' ', 2, "bset %d,#5" },
+  { 0x001c, 0x00ff, ' ', 2, "bset %d,#6" },
+  { 0x001e, 0x00ff, ' ', 2, "bset %d,#7" },
+
+  { 0x0001, 0x00ff, ' ', 3, "bjtf %d,#0,%p" },
+  { 0x0003, 0x00ff, ' ', 3, "bjtf %d,#1,%p" },
+  { 0x0005, 0x00ff, ' ', 3, "bjtf %d,#2,%p" },
+  { 0x0007, 0x00ff, ' ', 3, "bjtf %d,#3,%p" },
+  { 0x0009, 0x00ff, ' ', 3, "bjtf %d,#4,%p" },
+  { 0x000b, 0x00ff, ' ', 3, "bjtf %d,#5,%p" },
+  { 0x000d, 0x00ff, ' ', 3, "bjtf %d,#6,%p" },
+  { 0x000f, 0x00ff, ' ', 3, "bjtf %d,#7,%p" },
+
+  { 0x0000, 0x00ff, ' ', 3, "btjt %d,#0,%p" },
+  { 0x0002, 0x00ff, ' ', 3, "btjt %d,#1,%p" },
+  { 0x0004, 0x00ff, ' ', 3, "btjt %d,#2,%p" },
+  { 0x0006, 0x00ff, ' ', 3, "btjt %d,#3,%p" },
+  { 0x0008, 0x00ff, ' ', 3, "btjt %d,#4,%p" },
+  { 0x000a, 0x00ff, ' ', 3, "btjt %d,#5,%p" },
+  { 0x000c, 0x00ff, ' ', 3, "btjt %d,#6,%p" },
+  { 0x000e, 0x00ff, ' ', 3, "btjt %d,#7,%p" },
+
+  { 0x00bd, 0x00ff, ' ', 2, "call %d", true },
+  { 0x00cd, 0x00ff, ' ', 3, "call %x", true },
+  { 0x00dd, 0x00ff, ' ', 3, "call (%2,X)", true },
+  { 0x00ed, 0x00ff, ' ', 2, "call (%1,X)", true },
+  { 0x00fd, 0x00ff, ' ', 1, "call (X)", true },
+//  { 0x008d, 0x00ff, ' ', 4, "callf %e" },
+  { 0x00ad, 0x00ff, ' ', 2, "callr %p", true },
+
+//  { 0x008c, 0x00ff, ' ', 1, "ccf" },
+
+//  { 0x000f, 0x00ff, ' ', 2, "clr (%1,SP)" },
+  { 0x003f, 0x00ff, ' ', 2, "clr %d" },
+  { 0x004f, 0x00ff, ' ', 1, "clr A" },
+  { 0x006f, 0x00ff, ' ', 2, "clr (%1,X)" },
+  { 0x007f, 0x00ff, ' ', 1, "clr (X)" },
+  { 0x005f, 0x00ff, ' ', 1, "clr X" },
+
+//  { 0x0011, 0x00ff, ' ', 2, "cp A,(%1,SP)" },
+  { 0x00a1, 0x00ff, ' ', 2, "cp A,%b" },
+  { 0x00b1, 0x00ff, ' ', 2, "cp A,%d" },
+  { 0x00c1, 0x00ff, ' ', 3, "cp A,%x" },
+  { 0x00d1, 0x00ff, ' ', 3, "cp A,(%2,X)" },
+  { 0x00e1, 0x00ff, ' ', 2, "cp A,(%1,X)" },
+  { 0x00f1, 0x00ff, ' ', 1, "cp A,(X)" },
+//  { 0x0013, 0x00ff, ' ', 2, "cpw X,(%1,SP)" },
+  { 0x00a3, 0x00ff, ' ', 3, "cp X,%w" },
+  { 0x00b3, 0x00ff, ' ', 2, "cp X,%d" },
+  { 0x00c3, 0x00ff, ' ', 3, "cp X,%x" },
+  { 0x00d3, 0x00ff, ' ', 3, "cp X,(%2,X)" },
+  { 0x00e3, 0x00ff, ' ', 2, "cp X,(%1,X)" },
+  { 0x00f3, 0x00ff, ' ', 1, "cp X,(X)" },
+
+//  { 0x0003, 0x00ff, ' ', 2, "cpl (%1,SP)" },
+  { 0x0033, 0x00ff, ' ', 2, "cpl %d" },
+  { 0x0043, 0x00ff, ' ', 1, "cpl A" },
+  { 0x0063, 0x00ff, ' ', 2, "cpl (%1,X)" },
+  { 0x0073, 0x00ff, ' ', 1, "cpl (X)" },
+  { 0x0053, 0x00ff, ' ', 1, "cpl X" },
+
+//  { 0x000a, 0x00ff, ' ', 2, "dec (%1,SP)" },
+  { 0x003a, 0x00ff, ' ', 2, "dec %d" },
+  { 0x004a, 0x00ff, ' ', 1, "dec A" },
+  { 0x006a, 0x00ff, ' ', 2, "dec (%1,X)" },
+  { 0x007a, 0x00ff, ' ', 1, "dec (X)" },
+  { 0x005a, 0x00ff, ' ', 1, "dec X" },
+
+//  { 0x0062, 0x00ff, ' ', 1, "div X,A" },
+//  { 0x0065, 0x00ff, ' ', 1, "divw X,Y" },
+//  { 0x0031, 0x00ff, ' ', 3, "exg A,%x" },
+//  { 0x0041, 0x00ff, ' ', 1, "exg A,XL" },
+//  { 0x0051, 0x00ff, ' ', 1, "exgw X,Y" },
+//  { 0x0061, 0x00ff, ' ', 1, "exg A,YL" },
+  { 0x008e, 0x00ff, ' ', 1, "halt" },
+
+//  { 0x000c, 0x00ff, ' ', 2, "inc (%1,SP)" },
+  { 0x003c, 0x00ff, ' ', 2, "inc %d" },
+  { 0x004c, 0x00ff, ' ', 1, "inc A" },
+  { 0x006c, 0x00ff, ' ', 2, "inc (%1,X)" },
+  { 0x007c, 0x00ff, ' ', 1, "inc (X)" },
+  { 0x005c, 0x00ff, ' ', 1, "inc X" },
+
+  { 0x0080, 0x00ff, ' ', 1, "iret" },
+
+  { 0x00bc, 0x00ff, ' ', 2, "jp %d" },
+  { 0x00cc, 0x00ff, ' ', 3, "jp %x" },
+  { 0x00dc, 0x00ff, ' ', 3, "jp (%2,X)" },
+  { 0x00ec, 0x00ff, ' ', 2, "jp (%1,X)" },
+  { 0x00fc, 0x00ff, ' ', 1, "jp (X)" },
+//  { 0x00ad, 0x00ff, ' ', 4, "jpf %e" },
+  { 0x0020, 0x00ff, ' ', 2, "jra %p" },
+
+  { 0x0021, 0x00ff, ' ', 2, "jrf %p" },
+  { 0x0022, 0x00ff, ' ', 2, "jrugt %p" },
+  { 0x0023, 0x00ff, ' ', 2, "jrule %p" },
+  { 0x0024, 0x00ff, ' ', 2, "jruge %p" },
+  { 0x0025, 0x00ff, ' ', 2, "jrult %p" },
+  { 0x0026, 0x00ff, ' ', 2, "jrne %p" },
+  { 0x0027, 0x00ff, ' ', 2, "jreq %p" },
+  { 0x0028, 0x00ff, ' ', 2, "jrnh %p" },
+  { 0x0029, 0x00ff, ' ', 2, "jrh %p" },
+  { 0x002a, 0x00ff, ' ', 2, "jrpl %p" },
+  { 0x002b, 0x00ff, ' ', 2, "jrmi %p" },
+  { 0x002c, 0x00ff, ' ', 2, "jrnm %p" },
+  { 0x002d, 0x00ff, ' ', 2, "jrm %p" },
+  { 0x002e, 0x00ff, ' ', 2, "jril %p" },
+  { 0x002f, 0x00ff, ' ', 2, "jrih %p" },
+
+//  { 0x007b, 0x00ff, ' ', 2, "ld A,(%1,SP)" },
+  { 0x00a6, 0x00ff, ' ', 2, "ld A,%b" },
+  { 0x00b6, 0x00ff, ' ', 2, "ld A,%d" },
+  { 0x00c6, 0x00ff, ' ', 3, "ld A,%x" },
+  { 0x00d6, 0x00ff, ' ', 3, "ld A,(%2,X)" },
+  { 0x00e6, 0x00ff, ' ', 2, "ld A,(%1,X)" },
+  { 0x00f6, 0x00ff, ' ', 1, "ld A,(X)" },
+//  { 0x006b, 0x00ff, ' ', 2, "ld (%1,SP),A" },
+//  { 0x00a7, 0x00ff, ' ', 2, "ld %b,A" },
+  { 0x00b7, 0x00ff, ' ', 2, "ld %d,A" },
+  { 0x00c7, 0x00ff, ' ', 3, "ld %x,A" },
+  { 0x00d7, 0x00ff, ' ', 3, "ld (%2,X),A" },
+  { 0x00e7, 0x00ff, ' ', 2, "ld (%1,X),A" },
+  { 0x00f7, 0x00ff, ' ', 1, "ld (X),A" },
+  { 0x0093, 0x00ff, ' ', 1, "ld X,Y" },
+  { 0x0094, 0x00ff, ' ', 1, "ld S,X" },
+  { 0x0095, 0x00ff, ' ', 1, "ld S,A" },
+  { 0x0096, 0x00ff, ' ', 1, "ld X,S" },
+  { 0x0097, 0x00ff, ' ', 1, "ld X,A" },
+  { 0x009e, 0x00ff, ' ', 1, "ld A,S" },
+  { 0x009f, 0x00ff, ' ', 1, "ld A,X" },
+
+//  { 0x00a7, 0x00ff, ' ', 2, "ldf (%3,X),A" },
+//  { 0x00af, 0x00ff, ' ', 2, "ldf A,(%3,X)" },
+//  { 0x00bd, 0x00ff, ' ', 2, "ldf %e,A" },
+//  { 0x00bc, 0x00ff, ' ', 2, "ldf A,%e" },
+//  { 0x001e, 0x00ff, ' ', 2, "ldw X,(%1,SP)" },
+  { 0x00ae, 0x00ff, ' ', 2, "ld X,%b" },
+  { 0x00be, 0x00ff, ' ', 2, "ld X,%d" },
+  { 0x00ce, 0x00ff, ' ', 3, "ld X,%x" },
+  { 0x00de, 0x00ff, ' ', 3, "ld X,(%2,X)" },
+  { 0x00ee, 0x00ff, ' ', 2, "ld X,(%1,X)" },
+  { 0x00fe, 0x00ff, ' ', 1, "ld X,(X)" },
+//  { 0x001f, 0x00ff, ' ', 2, "ldw (%1,SP),X" },
+  { 0x00bf, 0x00ff, ' ', 2, "ld %d,X" },
+  { 0x00cf, 0x00ff, ' ', 3, "ld %x,X" },
+  { 0x00df, 0x00ff, ' ', 3, "ld (%2,X),Y" },
+  { 0x00ef, 0x00ff, ' ', 2, "ld (%1,X),Y" },
+  { 0x00ff, 0x00ff, ' ', 1, "ld (X),Y" },
+//  { 0x0016, 0x00ff, ' ', 2, "ldw Y,(%1,SP)" },
+//  { 0x0017, 0x00ff, ' ', 2, "ldw (%1,SP),Y" },
+
+//  { 0x0035, 0x00ff, ' ', 4, "mov %x,%b" },
+//  { 0x0045, 0x00ff, ' ', 3, "mov %d,%d" },
+//  { 0x0055, 0x00ff, ' ', 5, "mov %x,%x" },
+  { 0x0042, 0x00ff, ' ', 1, "mul X,A" },
+
+//  { 0x0000, 0x00ff, ' ', 2, "neg (%1,SP)" },
+  { 0x0030, 0x00ff, ' ', 2, "neg %d" },
+  { 0x0040, 0x00ff, ' ', 1, "neg A" },
+  { 0x0060, 0x00ff, ' ', 2, "neg (%1,X)" },
+  { 0x0070, 0x00ff, ' ', 1, "neg (X)" },
+  { 0x0050, 0x00ff, ' ', 1, "neg X" },
+
+  { 0x009d, 0x00ff, ' ', 1, "nop" },
+
+//  { 0x001a, 0x00ff, ' ', 2, "or A,(%1,SP)" },
+  { 0x00aa, 0x00ff, ' ', 2, "or A,%b" },
+  { 0x00ba, 0x00ff, ' ', 2, "or A,%d" },
+  { 0x00ca, 0x00ff, ' ', 3, "or A,%x" },
+  { 0x00da, 0x00ff, ' ', 3, "or A,(%2,X)" },
+  { 0x00ea, 0x00ff, ' ', 2, "or A,(%1,X)" },
+  { 0x00fa, 0x00ff, ' ', 1, "or A,(X)" },
+
+  { 0x0084, 0x00ff, ' ', 1, "pop A" },
+  { 0x0085, 0x00ff, ' ', 1, "pop X" },
+  { 0x0086, 0x00ff, ' ', 1, "pop CC" },
+//  { 0x0032, 0x00ff, ' ', 3, "pop %x" },
+  { 0x0088, 0x00ff, ' ', 1, "push A" },
+  { 0x0089, 0x00ff, ' ', 1, "push X" },
+  { 0x008a, 0x00ff, ' ', 1, "push CC" },
+//  { 0x003b, 0x00ff, ' ', 3, "push %x" },
+//  { 0x004b, 0x00ff, ' ', 2, "push %b" },
+
+  { 0x0098, 0x00ff, ' ', 1, "rcf" },
+  { 0x0081, 0x00ff, ' ', 1, "ret" },
+//  { 0x0087, 0x00ff, ' ', 1, "retf" },
+  { 0x009a, 0x00ff, ' ', 1, "rim" },
+
+//  { 0x0009, 0x00ff, ' ', 2, "rlc (%1,SP)" },
+  { 0x0039, 0x00ff, ' ', 2, "rlc %d" },
+  { 0x0049, 0x00ff, ' ', 1, "rlc A" },
+  { 0x0069, 0x00ff, ' ', 2, "rlc (%1,X)" },
+  { 0x0079, 0x00ff, ' ', 1, "rlc (X)" },
+  { 0x0059, 0x00ff, ' ', 1, "rlc X" },
+//  { 0x0002, 0x00ff, ' ', 1, "rlwa X,A" },
+//  { 0x0006, 0x00ff, ' ', 2, "rrc (%1,SP)" },
+  { 0x0036, 0x00ff, ' ', 2, "rrc %d" },
+  { 0x0046, 0x00ff, ' ', 1, "rrc A" },
+  { 0x0066, 0x00ff, ' ', 2, "rrc (%1,X)" },
+  { 0x0076, 0x00ff, ' ', 1, "rrc (X)" },
+  { 0x0056, 0x00ff, ' ', 1, "rrc X" },
+//  { 0x0001, 0x00ff, ' ', 1, "rrwa X,A" },
+
+  { 0x009c, 0x00ff, ' ', 1, "rsp" },
+
+//  { 0x0012, 0x00ff, ' ', 2, "sbc A,(%1,SP)" },
+  { 0x00a2, 0x00ff, ' ', 2, "sbc A,%b" },
+  { 0x00b2, 0x00ff, ' ', 2, "sbc A,%d" },
+  { 0x00c2, 0x00ff, ' ', 3, "sbc A,%x" },
+  { 0x00d2, 0x00ff, ' ', 3, "sbc A,(%2,X)" },
+  { 0x00e2, 0x00ff, ' ', 2, "sbc A,(%1,X)" },
+  { 0x00f2, 0x00ff, ' ', 1, "sbc A,(X)" },
+
+  { 0x0099, 0x00ff, ' ', 1, "scf" },
+  { 0x009b, 0x00ff, ' ', 1, "sim" },
+
+//  { 0x0008, 0x00ff, ' ', 2, "sla (%1,SP)" },
+  { 0x0038, 0x00ff, ' ', 2, "sla %d" },
+  { 0x0048, 0x00ff, ' ', 1, "sla A" },
+  { 0x0068, 0x00ff, ' ', 2, "sla (%1,X)" },
+  { 0x0078, 0x00ff, ' ', 1, "sla (X)" },
+  { 0x0058, 0x00ff, ' ', 1, "sla X" },
+//  { 0x0007, 0x00ff, ' ', 2, "sra (%1,SP)" },
+  { 0x0037, 0x00ff, ' ', 2, "sra %d" },
+  { 0x0047, 0x00ff, ' ', 1, "sra A" },
+  { 0x0067, 0x00ff, ' ', 2, "sra (%1,X)" },
+  { 0x0077, 0x00ff, ' ', 1, "sra (X)" },
+  { 0x0057, 0x00ff, ' ', 1, "sra X" },
+//  { 0x0004, 0x00ff, ' ', 2, "srl (%1,SP)" },
+  { 0x0034, 0x00ff, ' ', 2, "srl %d" },
+  { 0x0044, 0x00ff, ' ', 1, "srl A" },
+  { 0x0064, 0x00ff, ' ', 2, "srl (%1,X)" },
+  { 0x0074, 0x00ff, ' ', 1, "srl (X)" },
+  { 0x0054, 0x00ff, ' ', 1, "srl X" },
+
+//  { 0x0010, 0x00ff, ' ', 2, "sub A,(%1,SP)" },
+  { 0x00a0, 0x00ff, ' ', 2, "sub A,%b" },
+  { 0x00b0, 0x00ff, ' ', 2, "sub A,%d" },
+  { 0x00c0, 0x00ff, ' ', 3, "sub A,%x" },
+  { 0x00d0, 0x00ff, ' ', 3, "sub A,(%2,X)" },
+  { 0x00e0, 0x00ff, ' ', 2, "sub A,(%1,X)" },
+  { 0x00f0, 0x00ff, ' ', 1, "sub A,(X)" },
+//  { 0x0052, 0x00ff, ' ', 2, "sub SP,%b" },
+
+//  { 0x001d, 0x00ff, ' ', 3, "subw X,%w" },
+
+//  { 0x000e, 0x00ff, ' ', 2, "swap (%1,SP)" },
+  { 0x003e, 0x00ff, ' ', 2, "swap %d" },
+  { 0x004e, 0x00ff, ' ', 1, "swap A" },
+  { 0x006e, 0x00ff, ' ', 2, "swap (%1,X)" },
+  { 0x007e, 0x00ff, ' ', 1, "swap (X)" },
+  { 0x005e, 0x00ff, ' ', 1, "swapw X" },
+
+//  { 0x000d, 0x00ff, ' ', 2, "tnz (%1,SP)" },
+  { 0x003d, 0x00ff, ' ', 2, "tnz %d" },
+  { 0x004d, 0x00ff, ' ', 1, "tnz A" },
+  { 0x006d, 0x00ff, ' ', 2, "tnz (%1,X)" },
+  { 0x007d, 0x00ff, ' ', 1, "tnz (X)" },
+  { 0x005d, 0x00ff, ' ', 1, "tnz X" },
+
+  { 0x0083, 0x00ff, ' ', 1, "trap", true },
+  { 0x008f, 0x00ff, ' ', 1, "wfi" },
+
+//  { 0x0018, 0x00ff, ' ', 2, "xor A,(%1,SP)" },
+  { 0x00a8, 0x00ff, ' ', 2, "xor A,%b" },
+  { 0x00b8, 0x00ff, ' ', 2, "xor A,%d" },
+  { 0x00c8, 0x00ff, ' ', 3, "xor A,%x" },
+  { 0x00d8, 0x00ff, ' ', 3, "xor A,(%2,X)" },
+  { 0x00e8, 0x00ff, ' ', 2, "xor A,(%1,X)" },
+  { 0x00f8, 0x00ff, ' ', 1, "xor A,(X)" },
+
+  { 0, 0, 0, 0, NULL }
+};
+
+struct dis_entry disass_st7_90[]= {
+
+  { 0x00d9, 0x00ff, ' ', 3, "adc A,(%2,Y)" },
+  { 0x00e9, 0x00ff, ' ', 2, "adc A,(%1,Y)" },
+  { 0x00f9, 0x00ff, ' ', 1, "adc A,(Y)" },
+  { 0x00db, 0x00ff, ' ', 3, "add A,(%2,Y)" },
+  { 0x00eb, 0x00ff, ' ', 2, "add A,(%1,Y)" },
+  { 0x00fb, 0x00ff, ' ', 1, "add A,(Y)" },
+  { 0x00d4, 0x00ff, ' ', 3, "and A,(%2,Y)" },
+  { 0x00e4, 0x00ff, ' ', 2, "and A,(%1,Y)" },
+  { 0x00f4, 0x00ff, ' ', 1, "and A,(Y)" },
+  { 0x00d5, 0x00ff, ' ', 3, "bcp A,(%2,Y)" },
+  { 0x00e5, 0x00ff, ' ', 2, "bcp A,(%1,Y)" },
+  { 0x00f5, 0x00ff, ' ', 1, "bcp A,(Y)" },
+
+//  { 0x0011, 0x00ff, ' ', 3, "bccm %d,#0" },
+//  { 0x0013, 0x00ff, ' ', 3, "bccm %d,#1" },
+//  { 0x0015, 0x00ff, ' ', 3, "bccm %d,#2" },
+//  { 0x0017, 0x00ff, ' ', 3, "bccm %d,#3" },
+//  { 0x0019, 0x00ff, ' ', 3, "bccm %d,#4" },
+//  { 0x001b, 0x00ff, ' ', 3, "bccm %d,#5" },
+//  { 0x001d, 0x00ff, ' ', 3, "bccm %d,#6" },
+//  { 0x001f, 0x00ff, ' ', 3, "bccm %d,#7" },
+
+//  { 0x0010, 0x00ff, ' ', 3, "bcpl %d,#0" },
+//  { 0x0012, 0x00ff, ' ', 3, "bcpl %d,#1" },
+//  { 0x0014, 0x00ff, ' ', 3, "bcpl %d,#2" },
+//  { 0x0016, 0x00ff, ' ', 3, "bcpl %d,#3" },
+//  { 0x0018, 0x00ff, ' ', 3, "bcpl %d,#4" },
+//  { 0x001a, 0x00ff, ' ', 3, "bcpl %d,#5" },
+//  { 0x001c, 0x00ff, ' ', 3, "bcpl %d,#6" },
+//  { 0x001e, 0x00ff, ' ', 3, "bcpl %d,#7" },
+
+  { 0x00dd, 0x00ff, ' ', 3, "call (%2,Y)", true },
+  { 0x00ed, 0x00ff, ' ', 2, "call (%1,Y)", true },
+  { 0x00fd, 0x00ff, ' ', 1, "call (Y)", true },
+
+//  { 0x004f, 0x00ff, ' ', 3, "clr (%2,Y)" },
+  { 0x006f, 0x00ff, ' ', 2, "clr (%1,Y)" },
+  { 0x007f, 0x00ff, ' ', 1, "clr (Y)" },
+  { 0x005f, 0x00ff, ' ', 1, "clr Y" },
+
+  { 0x00d1, 0x00ff, ' ', 3, "cp A,(%2,Y)" },
+  { 0x00e1, 0x00ff, ' ', 2, "cp A,(%1,Y)" },
+  { 0x00f1, 0x00ff, ' ', 1, "cp A,(Y)" },
+  { 0x00a3, 0x00ff, ' ', 2, "cp Y,%b" },
+  { 0x00b3, 0x00ff, ' ', 2, "cp Y,%d" },
+  { 0x00c3, 0x00ff, ' ', 3, "cp Y,%x" },
+  { 0x00d3, 0x00ff, ' ', 3, "cp Y,(%2,Y)" },
+  { 0x00e3, 0x00ff, ' ', 2, "cp Y,(%1,Y)" },
+  { 0x00f3, 0x00ff, ' ', 1, "cp Y,(Y)" },
+
+//  { 0x0043, 0x00ff, ' ', 3, "cpl (%2,Y)" },
+  { 0x0063, 0x00ff, ' ', 2, "cpl (%1,Y)" },
+  { 0x0073, 0x00ff, ' ', 1, "cpl (Y)" },
+  { 0x0053, 0x00ff, ' ', 1, "cpl Y" },
+
+//  { 0x004a, 0x00ff, ' ', 3, "dec (%2,Y)" },
+  { 0x006a, 0x00ff, ' ', 2, "dec (%1,Y)" },
+  { 0x007a, 0x00ff, ' ', 1, "dec (Y)" },
+  { 0x005a, 0x00ff, ' ', 1, "dec Y" },
+
+//  { 0x0062, 0x00ff, ' ', 1, "div Y,A" },
+
+//  { 0x004c, 0x00ff, ' ', 3, "inc (%2,Y)" },
+  { 0x006c, 0x00ff, ' ', 2, "inc (%1,Y)" },
+  { 0x007c, 0x00ff, ' ', 1, "inc (Y)" },
+  { 0x005c, 0x00ff, ' ', 1, "inc Y" },
+
+  { 0x00dc, 0x00ff, ' ', 3, "jp (%2,Y)" },
+  { 0x00ec, 0x00ff, ' ', 2, "jp (%1,Y)" },
+  { 0x00fc, 0x00ff, ' ', 1, "jp (Y)" },
+
+  //{ 0x0028, 0x00ff, ' ', 2, "jrnh %p" },
+  //{ 0x0029, 0x00ff, ' ', 2, "jrh %p" },
+  //{ 0x002c, 0x00ff, ' ', 2, "jrnm %p" },
+  //{ 0x002d, 0x00ff, ' ', 2, "jrm %p" },
+  //{ 0x002e, 0x00ff, ' ', 2, "jril %p" },
+  //{ 0x002f, 0x00ff, ' ', 2, "jrih %p" },
+
+  { 0x00d6, 0x00ff, ' ', 3, "ld A,(%2,Y)" },
+  { 0x00e6, 0x00ff, ' ', 2, "ld A,(%1,Y)" },
+  { 0x00f6, 0x00ff, ' ', 1, "ld A,(Y)" },
+  { 0x00d7, 0x00ff, ' ', 3, "ld (%2,Y),A" },
+  { 0x00e7, 0x00ff, ' ', 2, "ld (%1,Y),A" },
+  { 0x00f7, 0x00ff, ' ', 1, "ld (Y),A" },
+
+  { 0x0093, 0x00ff, ' ', 1, "ld Y,X" },
+  { 0x0094, 0x00ff, ' ', 1, "ld S,Y" },
+  { 0x0096, 0x00ff, ' ', 1, "ld Y,S" },
+  { 0x0097, 0x00ff, ' ', 1, "ld Y,A" },
+  { 0x009f, 0x00ff, ' ', 1, "ld A,Y" },
+//  { 0x00a7, 0x00ff, ' ', 2, "ldf (%e,Y),A" },
+//  { 0x00af, 0x00ff, ' ', 2, "ldf A,(%e,Y)" },
+  { 0x00ae, 0x00ff, ' ', 2, "ld Y,%b" },
+  { 0x00be, 0x00ff, ' ', 2, "ld Y,%d" },
+  { 0x00ce, 0x00ff, ' ', 3, "ld Y,%x" },
+  { 0x00de, 0x00ff, ' ', 3, "ld Y,(%2,Y)" },
+  { 0x00ee, 0x00ff, ' ', 2, "ld Y,(%1,Y)" },
+  { 0x00fe, 0x00ff, ' ', 1, "ld Y,(Y)" },
+
+  { 0x00bf, 0x00ff, ' ', 2, "ld %d,Y" },
+  { 0x00cf, 0x00ff, ' ', 3, "ld %x,Y" },
+  { 0x00df, 0x00ff, ' ', 3, "ld (%2,Y),Y" },
+  { 0x00ef, 0x00ff, ' ', 2, "ld (%1,Y),Y" },
+  { 0x00ff, 0x00ff, ' ', 1, "ld (Y),Y" },
+
+  { 0x0042, 0x00ff, ' ', 1, "mul Y,A" },
+
+//  { 0x0040, 0x00ff, ' ', 3, "neg (%2,Y)" },
+  { 0x0060, 0x00ff, ' ', 2, "neg (%1,Y)" },
+  { 0x0070, 0x00ff, ' ', 1, "neg (Y)" },
+  { 0x0050, 0x00ff, ' ', 1, "neg Y" },
+
+  { 0x00da, 0x00ff, ' ', 3, "or A,(%2,Y)" },
+  { 0x00ea, 0x00ff, ' ', 2, "or A,(%1,Y)" },
+  { 0x00fa, 0x00ff, ' ', 1, "or A,(Y)" },
+
+  { 0x0085, 0x00ff, ' ', 1, "pop Y" },
+  { 0x0089, 0x00ff, ' ', 1, "push Y" },
+
+//  { 0x0049, 0x00ff, ' ', 3, "rlc (%2,Y)" },
+  { 0x0069, 0x00ff, ' ', 2, "rlc (%1,Y)" },
+  { 0x0079, 0x00ff, ' ', 1, "rlc (Y)" },
+  { 0x0059, 0x00ff, ' ', 1, "rlc Y" },
+//  { 0x0002, 0x00ff, ' ', 1, "rlwa Y,A" },
+//  { 0x0046, 0x00ff, ' ', 3, "rrc (%2,Y)" },
+  { 0x0066, 0x00ff, ' ', 2, "rrc (%1,Y)" },
+  { 0x0076, 0x00ff, ' ', 1, "rrc (Y)" },
+  { 0x0056, 0x00ff, ' ', 1, "rrc Y" },
+//  { 0x0001, 0x00ff, ' ', 1, "rrwa Y,A" },
+  
+  { 0x00d2, 0x00ff, ' ', 3, "sbc A,(%2,Y)" },
+  { 0x00e2, 0x00ff, ' ', 2, "sbc A,(%1,Y)" },
+  { 0x00f2, 0x00ff, ' ', 1, "sbc A,(Y)" },
+
+//  { 0x0048, 0x00ff, ' ', 3, "sla (%2,Y)" },
+  { 0x0068, 0x00ff, ' ', 2, "sla (%1,Y)" },
+  { 0x0078, 0x00ff, ' ', 1, "sla (Y)" },
+  { 0x0058, 0x00ff, ' ', 1, "sla Y" },
+//  { 0x0047, 0x00ff, ' ', 3, "sra (%2,Y)" },
+  { 0x0067, 0x00ff, ' ', 2, "sra (%1,Y)" },
+  { 0x0077, 0x00ff, ' ', 1, "sra (Y)" },
+  { 0x0057, 0x00ff, ' ', 1, "sra Y" },
+//  { 0x0044, 0x00ff, ' ', 3, "srl (%2,Y)" },
+  { 0x0064, 0x00ff, ' ', 2, "srl (%1,Y)" },
+  { 0x0074, 0x00ff, ' ', 1, "srl (Y)" },
+  { 0x0054, 0x00ff, ' ', 1, "srl Y" },
+
+  { 0x00d0, 0x00ff, ' ', 3, "sub A,(%2,Y)" },
+  { 0x00e0, 0x00ff, ' ', 2, "sub A,(%1,Y)" },
+  { 0x00f0, 0x00ff, ' ', 1, "sub A,(Y)" },
+
+//  { 0x004e, 0x00ff, ' ', 3, "swap (%2,Y)" },
+  { 0x006e, 0x00ff, ' ', 2, "swap (%1,Y)" },
+  { 0x007e, 0x00ff, ' ', 1, "swap (Y)" },
+  { 0x005e, 0x00ff, ' ', 1, "swap Y" },
+
+//  { 0x004d, 0x00ff, ' ', 3, "tnz (%2,Y)" },
+  { 0x006d, 0x00ff, ' ', 2, "tnz (%1,Y)" },
+  { 0x007d, 0x00ff, ' ', 1, "tnz (Y)" },
+  { 0x005d, 0x00ff, ' ', 1, "tnz Y" },
+
+  { 0x00d8, 0x00ff, ' ', 3, "xor A,(%2,Y)" },
+  { 0x00e8, 0x00ff, ' ', 2, "xor A,(%1,Y)" },
+  { 0x00f8, 0x00ff, ' ', 1, "xor A,(Y)" },
+
+  { 0, 0, 0, 0, NULL }
+};
+
+struct dis_entry disass_st7_91[]= {
+
+  { 0x00d9, 0x00ff, ' ', 2, "adc A,([%1.w],Y)" },
+  { 0x00e9, 0x00ff, ' ', 2, "adc A,([%1],Y)" },
+  { 0x00db, 0x00ff, ' ', 2, "add A,([%1.w],Y)" },
+  { 0x00eb, 0x00ff, ' ', 2, "add A,([%1],Y)" },
+  { 0x00d4, 0x00ff, ' ', 2, "and A,([%1.w],Y)" },
+  { 0x00e4, 0x00ff, ' ', 2, "and A,([%1],Y)" },
+  { 0x00d5, 0x00ff, ' ', 2, "bcp A,([%1.w],Y)" },
+  { 0x00e5, 0x00ff, ' ', 2, "bcp A,([%1],Y)" },
+  { 0x00dd, 0x00ff, ' ', 2, "call ([%1.w],Y)", true },
+  { 0x00ed, 0x00ff, ' ', 2, "call ([%1],Y)", true },
+  { 0x006f, 0x00ff, ' ', 2, "clr ([%1],Y)" },
+  { 0x00d1, 0x00ff, ' ', 2, "cp A,([%1.w],Y)" },
+  { 0x00e1, 0x00ff, ' ', 2, "cp A,([%1],Y)" },
+  { 0x00b3, 0x00ff, ' ', 2, "cp Y,[%1]" },
+  { 0x00c3, 0x00ff, ' ', 2, "cp Y,[%1.w]" },
+  { 0x00d3, 0x00ff, ' ', 2, "cp Y,([%1.w],Y)" },
+  { 0x00e3, 0x00ff, ' ', 2, "cp Y,([%1],Y)" },
+  { 0x0063, 0x00ff, ' ', 2, "cpl ([%1],Y)" },
+  { 0x006a, 0x00ff, ' ', 2, "dec ([%1],Y)" },
+  { 0x006c, 0x00ff, ' ', 2, "inc ([%1],Y)" },
+  { 0x00dc, 0x00ff, ' ', 2, "jp ([%1.w],Y)" },
+  { 0x00ec, 0x00ff, ' ', 2, "jp ([%1],Y)" },
+  { 0x00d6, 0x00ff, ' ', 2, "ld A,([%1.w],Y)" },
+  { 0x00e6, 0x00ff, ' ', 2, "ld A,([%1],Y)" },
+  { 0x00d7, 0x00ff, ' ', 2, "ld ([%1.w],Y),A" },
+  { 0x00e7, 0x00ff, ' ', 2, "ld ([%1],Y),A" },
+//  { 0x00a7, 0x00ff, ' ', 2, "ldf ([%2.e],Y),A" },
+//  { 0x00af, 0x00ff, ' ', 2, "ldf A,([%2.e],Y)" },
+  { 0x00be, 0x00ff, ' ', 3, "ld Y,[%1]" },
+  { 0x00ce, 0x00ff, ' ', 3, "ld Y,[%1.w]" },
+  { 0x00de, 0x00ff, ' ', 3, "ld Y,([%1.w],Y)" },
+  { 0x00ee, 0x00ff, ' ', 3, "ld Y,([%1],Y)" },
+  { 0x00bf, 0x00ff, ' ', 3, "ld [%1],Y" },
+  { 0x00cf, 0x00ff, ' ', 3, "ld [%1.w],Y" },
+  { 0x00df, 0x00ff, ' ', 3, "ld ([%1.w],Y),Y" },
+  { 0x00ef, 0x00ff, ' ', 3, "ld ([%1],Y),Y" },
+  { 0x0060, 0x00ff, ' ', 2, "neg ([%1],Y)" },
+  { 0x00da, 0x00ff, ' ', 2, "or A,([%1.w],Y)" },
+  { 0x00ea, 0x00ff, ' ', 2, "or A,([%1],Y)" },
+  { 0x0069, 0x00ff, ' ', 2, "rlc ([%1],Y)" },
+  { 0x0066, 0x00ff, ' ', 2, "rrc ([%1],Y)" },
+  { 0x00d2, 0x00ff, ' ', 2, "sbc A,([%1.w],Y)" },
+  { 0x00e2, 0x00ff, ' ', 2, "sbc A,([%1],Y)" },
+  { 0x0068, 0x00ff, ' ', 2, "sla ([%1],Y)" },
+  { 0x0067, 0x00ff, ' ', 2, "sra ([%1],Y)" },
+  { 0x0064, 0x00ff, ' ', 2, "srl ([%1],Y)" },
+  { 0x00d0, 0x00ff, ' ', 2, "sub A,([%1.w],Y)" },
+  { 0x00e0, 0x00ff, ' ', 2, "sub A,([%1],Y)" },
+  { 0x006e, 0x00ff, ' ', 2, "swap ([%1],Y)" },
+  { 0x006d, 0x00ff, ' ', 2, "tnz ([%1],Y)" },
+  { 0x00d8, 0x00ff, ' ', 2, "xor A,([%1.w],Y)" },
+  { 0x00e8, 0x00ff, ' ', 2, "xor A,([%1],Y)" },
+
+  { 0, 0, 0, 0, NULL }
+};
+
+struct dis_entry disass_st7_92[]= {
+
+  { 0x00b9, 0x00ff, ' ', 2, "adc A,[%1]" },
+  { 0x00c9, 0x00ff, ' ', 2, "adc A,[%1.w]" },
+  { 0x00d9, 0x00ff, ' ', 2, "adc A,([%1.w],X)" },
+  { 0x00e9, 0x00ff, ' ', 2, "adc A,([%1],X)" },
+  { 0x00bb, 0x00ff, ' ', 2, "add A,[%1]" },
+  { 0x00cb, 0x00ff, ' ', 2, "add A,[%1.w]" },
+  { 0x00db, 0x00ff, ' ', 2, "add A,([%1.w],X)" },
+  { 0x00eb, 0x00ff, ' ', 2, "add A,([%1],X)" },
+  { 0x00b4, 0x00ff, ' ', 2, "and A,[%1]" },
+  { 0x00c4, 0x00ff, ' ', 2, "and A,[%1.w]" },
+  { 0x00d4, 0x00ff, ' ', 2, "and A,([%1.w],X)" },
+  { 0x00e4, 0x00ff, ' ', 2, "and A,([%1],X)" },
+  { 0x00b5, 0x00ff, ' ', 2, "bcp A,[%1]" },
+  { 0x00c5, 0x00ff, ' ', 2, "bcp A,[%1.w]" },
+  { 0x00d5, 0x00ff, ' ', 2, "bcp A,([%1.w],X)" },
+  { 0x00e5, 0x00ff, ' ', 2, "bcp A,([%1],X)" },
+
+  { 0x0011, 0x00ff, ' ', 2, "bres [%1],#0" },
+  { 0x0013, 0x00ff, ' ', 2, "bres [%1],#1" },
+  { 0x0015, 0x00ff, ' ', 2, "bres [%1],#2" },
+  { 0x0017, 0x00ff, ' ', 2, "bres [%1],#3" },
+  { 0x0019, 0x00ff, ' ', 2, "bres [%1],#4" },
+  { 0x001b, 0x00ff, ' ', 2, "bres [%1],#5" },
+  { 0x001d, 0x00ff, ' ', 2, "bres [%1],#6" },
+  { 0x001f, 0x00ff, ' ', 2, "bres [%1],#7" },
+
+  { 0x0010, 0x00ff, ' ', 2, "bset [%1],#0" },
+  { 0x0012, 0x00ff, ' ', 2, "bset [%1],#1" },
+  { 0x0014, 0x00ff, ' ', 2, "bset [%1],#2" },
+  { 0x0016, 0x00ff, ' ', 2, "bset [%1],#3" },
+  { 0x0018, 0x00ff, ' ', 2, "bset [%1],#4" },
+  { 0x001a, 0x00ff, ' ', 2, "bset [%1],#5" },
+  { 0x001c, 0x00ff, ' ', 2, "bset [%1],#6" },
+  { 0x001e, 0x00ff, ' ', 2, "bset [%1],#7" },
+
+  { 0x0001, 0x00ff, ' ', 3, "bjtf [%1],#0,%p" },
+  { 0x0003, 0x00ff, ' ', 3, "bjtf [%1],#1,%p" },
+  { 0x0005, 0x00ff, ' ', 3, "bjtf [%1],#2,%p" },
+  { 0x0007, 0x00ff, ' ', 3, "bjtf [%1],#3,%p" },
+  { 0x0009, 0x00ff, ' ', 3, "bjtf [%1],#4,%p" },
+  { 0x000b, 0x00ff, ' ', 3, "bjtf [%1],#5,%p" },
+  { 0x000d, 0x00ff, ' ', 3, "bjtf [%1],#6,%p" },
+  { 0x000f, 0x00ff, ' ', 3, "bjtf [%1],#7,%p" },
+
+  { 0x0000, 0x00ff, ' ', 3, "btjt [%1],#0,%p" },
+  { 0x0002, 0x00ff, ' ', 3, "btjt [%1],#1,%p" },
+  { 0x0004, 0x00ff, ' ', 3, "btjt [%1],#2,%p" },
+  { 0x0006, 0x00ff, ' ', 3, "btjt [%1],#3,%p" },
+  { 0x0008, 0x00ff, ' ', 3, "btjt [%1],#4,%p" },
+  { 0x000a, 0x00ff, ' ', 3, "btjt [%1],#5,%p" },
+  { 0x000c, 0x00ff, ' ', 3, "btjt [%1],#6,%p" },
+  { 0x000e, 0x00ff, ' ', 3, "btjt [%1],#7,%p" },
+
+  { 0x00cd, 0x00ff, ' ', 2, "call [%1]", true },
+  { 0x00cd, 0x00ff, ' ', 2, "call [%1.w]", true },
+  { 0x00dd, 0x00ff, ' ', 2, "call ([%1.w],X)", true },
+  { 0x00dd, 0x00ff, ' ', 2, "call ([%1],X)", true },
+  { 0x00ad, 0x00ff, ' ', 2, "callr [%1]", true },
+//  { 0x008d, 0x00ff, ' ', 3, "callf [%2.e]", true },
+  { 0x003f, 0x00ff, ' ', 2, "clr [%1]" },
+  { 0x006f, 0x00ff, ' ', 2, "clr ([%1],X)" },
+  { 0x00b1, 0x00ff, ' ', 2, "cp A,[%1]" },
+  { 0x00c1, 0x00ff, ' ', 2, "cp A,[%1.w]" },
+  { 0x00d1, 0x00ff, ' ', 2, "cp A,([%1.w],X)" },
+  { 0x00e1, 0x00ff, ' ', 2, "cp A,([%1],X)" },
+  { 0x00b3, 0x00ff, ' ', 2, "cp X,[%1.w]" },
+  { 0x00c3, 0x00ff, ' ', 2, "cp X,[%1.w]" },
+  { 0x00d3, 0x00ff, ' ', 2, "cp X,([%1.w],X)" },
+  { 0x00e3, 0x00ff, ' ', 2, "cp X,([%1.w],X)" },
+  { 0x0033, 0x00ff, ' ', 2, "cpl [%1]" },
+  { 0x0063, 0x00ff, ' ', 2, "cpl ([%1],X)" },
+  { 0x003a, 0x00ff, ' ', 2, "dec [%1]" },
+  { 0x006a, 0x00ff, ' ', 2, "dec ([%1],X)" },
+  { 0x003c, 0x00ff, ' ', 2, "inc [%1]" },
+  { 0x006c, 0x00ff, ' ', 2, "inc ([%1],X)" },
+  { 0x00bc, 0x00ff, ' ', 2, "jp [%1]" },
+  { 0x00cc, 0x00ff, ' ', 2, "jp [%1.w]" },
+  { 0x00dc, 0x00ff, ' ', 2, "jp ([%1.w],X)" },
+  { 0x00ec, 0x00ff, ' ', 2, "jp ([%1],X)" },
+//  { 0x00ac, 0x00ff, ' ', 3, "jpf [%2.e]" },
+  { 0x0020, 0x00ff, ' ', 2, "jra [%1]" },
+
+  { 0x0021, 0x00ff, ' ', 2, "jrf [%1]" },
+  { 0x0022, 0x00ff, ' ', 2, "jrugt [%1]" },
+  { 0x0023, 0x00ff, ' ', 2, "jrule [%1]" },
+  { 0x0024, 0x00ff, ' ', 2, "jruge [%1]" },
+  { 0x0025, 0x00ff, ' ', 2, "jrult [%1]" },
+  { 0x0026, 0x00ff, ' ', 2, "jrne [%1]" },
+  { 0x0027, 0x00ff, ' ', 2, "jreq [%1]" },
+  { 0x0028, 0x00ff, ' ', 2, "jrnh [%1]" },
+  { 0x0029, 0x00ff, ' ', 2, "jrh [%1]" },
+  { 0x002a, 0x00ff, ' ', 2, "jrpl [%1]" },
+  { 0x002b, 0x00ff, ' ', 2, "jrmi [%1]" },
+  { 0x002c, 0x00ff, ' ', 2, "jrnm [%1]" },
+  { 0x002d, 0x00ff, ' ', 2, "jrm [%1]" },
+  { 0x002e, 0x00ff, ' ', 2, "jril [%1]" },
+  { 0x002f, 0x00ff, ' ', 2, "jrih [%1]" },
+
+  { 0x00b6, 0x00ff, ' ', 2, "ld A,[%1]" },
+  { 0x00c6, 0x00ff, ' ', 2, "ld A,[%1.w]" },
+  { 0x00d6, 0x00ff, ' ', 2, "ld A,([%1.w],X)" },
+  { 0x00e6, 0x00ff, ' ', 2, "ld A,([%1],X)" },
+  { 0x00b7, 0x00ff, ' ', 2, "ld [%1],A" },
+  { 0x00c7, 0x00ff, ' ', 2, "ld [%1.w],A" },
+  { 0x00d7, 0x00ff, ' ', 2, "ld ([%1.w],X),A" },
+  { 0x00e7, 0x00ff, ' ', 2, "ld ([%1],X),A" },
+//  { 0x00a7, 0x00ff, ' ', 2, "ldf ([%2.e],X),A" },
+//  { 0x00af, 0x00ff, ' ', 2, "ldf A,([%2.e],X)" },
+  { 0x00be, 0x00ff, ' ', 2, "ld X,[%1]" },
+  { 0x00ce, 0x00ff, ' ', 2, "ld X,[%1.w]" },
+  { 0x00de, 0x00ff, ' ', 2, "ld X,([%1.w],X)" },
+  { 0x00ee, 0x00ff, ' ', 2, "ld X,([%1],X)" },
+  { 0x00bf, 0x00ff, ' ', 2, "ld [%1],X" },
+  { 0x00cf, 0x00ff, ' ', 2, "ld [%1.w],X" },
+  { 0x00df, 0x00ff, ' ', 2, "ld ([%1.w],X),X" },
+  { 0x00ef, 0x00ff, ' ', 2, "ld ([%1],X),X" },
+
+  { 0x0030, 0x00ff, ' ', 2, "neg [%1]" },
+  { 0x0060, 0x00ff, ' ', 2, "neg ([%1],X)" },
+  { 0x00ba, 0x00ff, ' ', 2, "or A,[%1]" },
+  { 0x00ca, 0x00ff, ' ', 2, "or A,[%1.w]" },
+  { 0x00da, 0x00ff, ' ', 2, "or A,([%1.w],X)" },
+  { 0x00ea, 0x00ff, ' ', 2, "or A,([%1],X)" },
+  { 0x0039, 0x00ff, ' ', 2, "rlc [%1]" },
+  { 0x0069, 0x00ff, ' ', 2, "rlc ([%1],X)" },
+  { 0x0036, 0x00ff, ' ', 2, "rrc [%1]" },
+  { 0x0066, 0x00ff, ' ', 2, "rrc ([%1],X)" },
+  { 0x00b2, 0x00ff, ' ', 2, "sbc A,[%1]" },
+  { 0x00c2, 0x00ff, ' ', 2, "sbc A,[%1.w]" },
+  { 0x00d2, 0x00ff, ' ', 2, "sbc A,([%1.w],X)" },
+  { 0x00e2, 0x00ff, ' ', 2, "sbc A,([%1],X)" },
+  { 0x0038, 0x00ff, ' ', 2, "sla [%1]" },
+  { 0x0068, 0x00ff, ' ', 2, "sla ([%1],X)" },
+  { 0x0037, 0x00ff, ' ', 2, "sra [%1]" },
+  { 0x0067, 0x00ff, ' ', 2, "sra ([%1],X)" },
+  { 0x0034, 0x00ff, ' ', 2, "srl [%1]" },
+  { 0x0064, 0x00ff, ' ', 2, "srl ([%1],X)" },
+  { 0x00b0, 0x00ff, ' ', 2, "sub A,[%1]" },
+  { 0x00c0, 0x00ff, ' ', 2, "sub A,[%1.w]" },
+  { 0x00d0, 0x00ff, ' ', 2, "sub A,([%1.w],X)" },
+  { 0x00e0, 0x00ff, ' ', 2, "sub A,([%1],X)" },
+  { 0x003e, 0x00ff, ' ', 2, "swap [%1]" },
+  { 0x006e, 0x00ff, ' ', 2, "swap ([%1],X)" },
+  { 0x003d, 0x00ff, ' ', 2, "tnz [%1]" },
+  { 0x006d, 0x00ff, ' ', 2, "tnz ([%1],X)" },
+  { 0x00b8, 0x00ff, ' ', 2, "xor A,[%1]" },
+  { 0x00c8, 0x00ff, ' ', 2, "xor A,[%1.w]" },
+  { 0x00d8, 0x00ff, ' ', 2, "xor A,([%1.w],X)" },
+  { 0x00e8, 0x00ff, ' ', 2, "xor A,([%1],X)" },
+
+  { 0, 0, 0, 0, NULL }
+};
+
+/* glob.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/st7.src/glob.h sdcc-4.2.0+dfsg/sim/ucsim/st7.src/glob.h
--- sdcc-4.0.0+dfsg/sim/ucsim/st7.src/glob.h	2012-12-23 20:32:49.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/st7.src/glob.h	2020-09-17 06:45:33.000000000 +0000
@@ -1,44 +1,44 @@
-/*
- * Simulator of microcontrollers (glob.h)
- *
- * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
- * 
- * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
- *
- */
-
-/* This file is part of microcontroller simulator: ucsim.
-
-UCSIM is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2 of the License, or
-(at your option) any later version.
-
-UCSIM is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with UCSIM; see the file COPYING.  If not, write to the Free
-Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-02111-1307, USA. */
-/*@1@*/
-
-#ifndef GLOB_HEADER
-#define GLOB_HEADER
-
-#include "stypes.h"
-
-
-extern struct dis_entry disass_st7[];
-
-extern struct dis_entry disass_st7_90[];
-
-extern struct dis_entry disass_st7_91[];
-
-extern struct dis_entry disass_st7_92[];
-
-#endif
-
-/* End of st7.src/glob.h */
+/*
+ * Simulator of microcontrollers (glob.h)
+ *
+ * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef GLOB_HEADER
+#define GLOB_HEADER
+
+#include "stypes.h"
+
+
+extern struct dis_entry disass_st7[];
+
+extern struct dis_entry disass_st7_90[];
+
+extern struct dis_entry disass_st7_91[];
+
+extern struct dis_entry disass_st7_92[];
+
+#endif
+
+/* End of st7.src/glob.h */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/st7.src/inst.cc sdcc-4.2.0+dfsg/sim/ucsim/st7.src/inst.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/st7.src/inst.cc	2014-07-30 04:48:15.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/st7.src/inst.cc	2020-09-17 06:45:33.000000000 +0000
@@ -1,1023 +1,1023 @@
-/*
- * Simulator of microcontrollers (inst.cc)
- *
- * st7 code base from Vaclav Peroutka vaclavpe@users.sourceforge.net
- *
- * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
- * 
- * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
- *
- */
-
-/* This file is part of microcontroller simulator: ucsim.
-
-UCSIM is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2 of the License, or
-(at your option) any later version.
-
-UCSIM is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with UCSIM; see the file COPYING.  If not, write to the Free
-Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-02111-1307, USA. */
-/*@1@*/
-
-#include "ddconfig.h"
-#include "stdio.h"
-#include 
-
-// local
-#include "st7cl.h"
-#include "regsst7.h"
-#include "st7mac.h"
-
-unsigned int
-cl_st7::fetchea(t_mem code, unsigned char prefix)
-{
-   unsigned int resaddr;
-   unsigned int ftc; //because of get2() MACRO!!!!!!
-//   unsigned int ftc, gt;
-//       ftc = fetch();
-//       gt = get1(ftc);
-
-//  printf("******************** fetchea() start PC= 0x%04x, prefix = 0x%02x, code = 0x%02x \n", PC, prefix, code);
-
-  switch ((code >> 4) & 0x0f) {
-	
-    case 0xb:
-	  if ( 0 == prefix) {              // short direct
-		 resaddr = fetch();
-     } else if ( 0x92 == prefix) {    // short indirect - pointer
-       resaddr = get1(fetch());
-	  } else {
-	    resaddr = ( resHALT);
-	  }
-     break;
-     
-    case 0xc:
-	  if ( 0 == prefix) {              // long direct
-		resaddr = fetch2();
-	  } else if ( 0x92 == prefix) {    // long indirect - pointer is under 0x100
-       ftc = fetch();
-       resaddr = get2(ftc);
-	  } else {
-	    resaddr = ( resHALT);
-	  }
-     break;
-
-    case 0xd:
-	  if ( 0 == prefix) {              // long offset with X reg
-        resaddr = (fetch2()+regs.X);
-	  } else if ( 0x90 == prefix) {    // long offset with Y reg
-        resaddr = (fetch2()+regs.Y);
-	  } else if ( 0x91 == prefix) {    // pointer to long offset with Y
-      ftc = fetch();
-	    resaddr = (get2(ftc)+regs.Y);
-	  } else if ( 0x92 == prefix) {    // pointer to long offset with X
-       ftc = fetch();
-	    resaddr = (get2(ftc)+regs.X);
-	  } else {
-	    resaddr =( resHALT);
-	  }
-     break;
-
-    case 0xe:
-	  if ( 0 == prefix) {              // short offset with X
-		resaddr = (fetch()+regs.X);
-	  } else if ( 0x90 == prefix) {    // short offset with Y
-	    resaddr = (fetch()+regs.Y);
-	  } else if ( 0x91 == prefix) {    // pointer to short offset with Y
-	    resaddr = (get1(fetch())+regs.Y);
-	  } else if ( 0x92 == prefix) {    // pointer to short offset with X
-	    resaddr = (get1(fetch())+regs.X);
-	  } else {
-	    resaddr =( resHALT);
-	  }
-     break;
-
-    case 0xf:
-	  if ( 0 == prefix) {
-		resaddr = regs.X;  // X index
-	  } else if ( 0x90 == prefix) {
-	    resaddr = regs.Y;  // Y index
-	  } else {
-	    resaddr =( resHALT);
-	  }
-     break;
-
-    default:
-      resaddr =(resHALT);
-      break;
-  }
-//  printf("******************** fetchea() end - resaddr=0x%04x, PC=0x%04x\n", resaddr, PC);
-  return resaddr;
-}
-
-
-int
-cl_st7::get_dest(t_mem code, unsigned char prefix)
-{
-   int resaddr;
-//  printf("******************** get_dest() start PC= 0x%04x, prefix = 0x%02x, code = 0x%02x \n", PC, prefix, code);
-
-  switch ((code >> 4) & 0x0f) {
-	
-    case 0x3:
-	  if ( 0 == prefix) {              // short direct
-		 resaddr = fetch();
-     } else if ( 0x92 == prefix) {    // short indirect - pointer
-       resaddr = get1(fetch());
-	  } else {
-	    resaddr = ( resHALT);
-	  }
-     break;
-     
-    case 0x6:
-	  if ( 0 == prefix) {              // short offset with X
-		resaddr = (fetch()+regs.X);
-	  } else if ( 0x90 == prefix) {    // short offset with Y
-	    resaddr = (fetch()+regs.Y);
-	  } else if ( 0x91 == prefix) {    // pointer to short offset with Y
-	    resaddr = (get1(fetch())+regs.Y);
-	  } else if ( 0x92 == prefix) {    // pointer to short offset with X
-	    resaddr = (get1(fetch())+regs.X);
-	  } else {
-	    resaddr =( resHALT);
-	  }
-     break;
-
-    case 0x7:
-	  if ( 0 == prefix) {              // X index
-		resaddr = regs.X;
-	  } else if ( 0x90 == prefix) {    // Y index
-	    resaddr = regs.Y;
-	  } else {
-	    resaddr =( resHALT);
-	  }
-     break;
-
-    default:
-      resaddr =(resHALT);
-      break;
-  }
-//  printf("******************** get_dest() end - resaddr=0x%04x, PC=0x%04x\n", resaddr, PC);
-  return resaddr;
-}
-
-/*****************************************************************************
- *
- *
- *
- *****************************************************************************
- */
-
-int
-cl_st7::inst_adc(t_mem code, unsigned char prefix)
-{
-  int result, operand1, operand2;
-  int carryin = (regs.CC & BIT_C)!=0;
-
-  operand1 = regs.A;
-  operand2 = OPERAND(code, prefix);
-  result = operand1 + operand2 + carryin;
-
-//  printf("******************** adc() op1 = 0x%02x, op2=0x%02x , res=0x%02x \n", operand1, operand2, result);
-
-  FLAG_ASSIGN (BIT_Z, (result & 0xff) == 0);
-  FLAG_ASSIGN (BIT_C, 0x100 & result);
-  FLAG_ASSIGN (BIT_N, 0x80 & result);
-  FLAG_ASSIGN (BIT_H, 0x10 & (operand1 ^ operand2 ^ result));
-
-  regs.A = result & 0xff;
-  return(resGO);
-}
-
-int
-cl_st7::inst_add(t_mem code, unsigned char prefix)
-{
-  int result, operand1, operand2;
-
-  operand1 = regs.A;
-  operand2 = OPERAND(code, prefix);
-  result = operand1 + operand2;
-
-//  printf("******************** adc() op1 = 0x%02x, op2=0x%02x , res=0x%02x \n", operand1, operand2, result);
-
-  FLAG_ASSIGN (BIT_Z, (result & 0xff) == 0);
-  FLAG_ASSIGN (BIT_C, 0x100 & result);
-  FLAG_ASSIGN (BIT_N, 0x80 & result);
-  FLAG_ASSIGN (BIT_H, 0x10 & (operand1 ^ operand2 ^ result));
-
-  regs.A = result & 0xff;
-  return(resGO);
-}
-
-int
-cl_st7::inst_and(t_mem code, unsigned char prefix)
-{
-  int operand2;
-
-  operand2 = OPERAND(code, prefix);
-  regs.A = regs.A & operand2;
-
-  FLAG_ASSIGN (BIT_Z, (regs.A & 0xff) == 0);
-  FLAG_ASSIGN (BIT_N, 0x80 & regs.A);
-
-  return(resGO);
-}
-
-int
-cl_st7::inst_bcp(t_mem code, unsigned char prefix)
-{
-  int operand2, opresult;
-
-  operand2 = OPERAND(code, prefix);
-  opresult = regs.A & operand2;
-
-  FLAG_ASSIGN (BIT_Z, (opresult & 0xff) == 0);
-  FLAG_ASSIGN (BIT_N, 0x80 & opresult);
-
-  return(resGO);
-}
-
-int
-cl_st7::inst_bresbset(t_mem code, unsigned char prefix)
-{
-  int ea = fetch();
-  unsigned char dbyte = get1( ea);
-  
-  if (code & 0x01) { // bres  
-	char pos = (code - 0x11) >> 1;
-	dbyte = dbyte & (~(1<> 1;
-	dbyte = dbyte | (1<> 1;
-	if(!( dbyte & (1<> 1;
-	if ( dbyte & (1<>1) & 7) {
-      case 0: // JRA / JRF
-        taken = 1;
-        break;
-      case 1: // JRUGT / JRULE
-        taken = !(regs.CC & (BIT_C | BIT_Z));
-        break;
-      case 2: // JRUGE / JRC
-        taken = !(regs.CC & BIT_C);
-        break;
-      case 3: // JRNE / JREQ
-        taken = !(regs.CC & BIT_Z);
-        break;
-      case 4: // JRNH / JRH
-        taken = !(regs.CC & BIT_H);
-        break;
-      case 5: // JRPL / JRMI
-        taken = !(regs.CC & BIT_N);
-        break;
-      case 6: // JRNM / JRM
-        taken = !(regs.CC & BIT_I);
+/*
+ * Simulator of microcontrollers (inst.cc)
+ *
+ * st7 code base from Vaclav Peroutka vaclavpe@users.sourceforge.net
+ *
+ * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+//#include "ddconfig.h"
+
+//#include "stdio.h"
+//#include 
+
+// local
+#include "st7cl.h"
+//#include "regsst7.h"
+#include "st7mac.h"
+
+unsigned int
+cl_st7::fetchea(t_mem code, unsigned char prefix)
+{
+   unsigned int resaddr;
+   unsigned int ftc; //because of get2() MACRO!!!!!!
+//   unsigned int ftc, gt;
+//       ftc = fetch();
+//       gt = get1(ftc);
+
+//  printf("******************** fetchea() start PC= 0x%04x, prefix = 0x%02x, code = 0x%02x \n", PC, prefix, code);
+
+  switch ((code >> 4) & 0x0f) {
+	
+    case 0xb:
+	  if ( 0 == prefix) {              // short direct
+		 resaddr = fetch();
+     } else if ( 0x92 == prefix) {    // short indirect - pointer
+       resaddr = get1(fetch());
+	  } else {
+	    resaddr = ( resHALT);
+	  }
+     break;
+     
+    case 0xc:
+	  if ( 0 == prefix) {              // long direct
+		resaddr = fetch2();
+	  } else if ( 0x92 == prefix) {    // long indirect - pointer is under 0x100
+       ftc = fetch();
+       resaddr = get2(ftc);
+	  } else {
+	    resaddr = ( resHALT);
+	  }
+     break;
+
+    case 0xd:
+	  if ( 0 == prefix) {              // long offset with X reg
+        resaddr = (fetch2()+regs.X);
+	  } else if ( 0x90 == prefix) {    // long offset with Y reg
+        resaddr = (fetch2()+regs.Y);
+	  } else if ( 0x91 == prefix) {    // pointer to long offset with Y
+      ftc = fetch();
+	    resaddr = (get2(ftc)+regs.Y);
+	  } else if ( 0x92 == prefix) {    // pointer to long offset with X
+       ftc = fetch();
+	    resaddr = (get2(ftc)+regs.X);
+	  } else {
+	    resaddr =( resHALT);
+	  }
+     break;
+
+    case 0xe:
+	  if ( 0 == prefix) {              // short offset with X
+		resaddr = (fetch()+regs.X);
+	  } else if ( 0x90 == prefix) {    // short offset with Y
+	    resaddr = (fetch()+regs.Y);
+	  } else if ( 0x91 == prefix) {    // pointer to short offset with Y
+	    resaddr = (get1(fetch())+regs.Y);
+	  } else if ( 0x92 == prefix) {    // pointer to short offset with X
+	    resaddr = (get1(fetch())+regs.X);
+	  } else {
+	    resaddr =( resHALT);
+	  }
+     break;
+
+    case 0xf:
+	  if ( 0 == prefix) {
+		resaddr = regs.X;  // X index
+	  } else if ( 0x90 == prefix) {
+	    resaddr = regs.Y;  // Y index
+	  } else {
+	    resaddr =( resHALT);
+	  }
+     break;
+
+    default:
+      resaddr =(resHALT);
+      break;
+  }
+//  printf("******************** fetchea() end - resaddr=0x%04x, PC=0x%04x\n", resaddr, PC);
+  return resaddr;
+}
+
+
+int
+cl_st7::get_dest(t_mem code, unsigned char prefix)
+{
+   int resaddr;
+//  printf("******************** get_dest() start PC= 0x%04x, prefix = 0x%02x, code = 0x%02x \n", PC, prefix, code);
+
+  switch ((code >> 4) & 0x0f) {
+	
+    case 0x3:
+	  if ( 0 == prefix) {              // short direct
+		 resaddr = fetch();
+     } else if ( 0x92 == prefix) {    // short indirect - pointer
+       resaddr = get1(fetch());
+	  } else {
+	    resaddr = ( resHALT);
+	  }
+     break;
+     
+    case 0x6:
+	  if ( 0 == prefix) {              // short offset with X
+		resaddr = (fetch()+regs.X);
+	  } else if ( 0x90 == prefix) {    // short offset with Y
+	    resaddr = (fetch()+regs.Y);
+	  } else if ( 0x91 == prefix) {    // pointer to short offset with Y
+	    resaddr = (get1(fetch())+regs.Y);
+	  } else if ( 0x92 == prefix) {    // pointer to short offset with X
+	    resaddr = (get1(fetch())+regs.X);
+	  } else {
+	    resaddr =( resHALT);
+	  }
+     break;
+
+    case 0x7:
+	  if ( 0 == prefix) {              // X index
+		resaddr = regs.X;
+	  } else if ( 0x90 == prefix) {    // Y index
+	    resaddr = regs.Y;
+	  } else {
+	    resaddr =( resHALT);
+	  }
+     break;
+
+    default:
+      resaddr =(resHALT);
+      break;
+  }
+//  printf("******************** get_dest() end - resaddr=0x%04x, PC=0x%04x\n", resaddr, PC);
+  return resaddr;
+}
+
+/*****************************************************************************
+ *
+ *
+ *
+ *****************************************************************************
+ */
+
+int
+cl_st7::inst_adc(t_mem code, unsigned char prefix)
+{
+  int result, operand1, operand2;
+  int carryin = (regs.CC & BIT_C)!=0;
+
+  operand1 = regs.A;
+  operand2 = OPERAND(code, prefix);
+  result = operand1 + operand2 + carryin;
+
+//  printf("******************** adc() op1 = 0x%02x, op2=0x%02x , res=0x%02x \n", operand1, operand2, result);
+
+  FLAG_ASSIGN (BIT_Z, (result & 0xff) == 0);
+  FLAG_ASSIGN (BIT_C, 0x100 & result);
+  FLAG_ASSIGN (BIT_N, 0x80 & result);
+  FLAG_ASSIGN (BIT_H, 0x10 & (operand1 ^ operand2 ^ result));
+
+  regs.A = result & 0xff;
+  return(resGO);
+}
+
+int
+cl_st7::inst_add(t_mem code, unsigned char prefix)
+{
+  int result, operand1, operand2;
+
+  operand1 = regs.A;
+  operand2 = OPERAND(code, prefix);
+  result = operand1 + operand2;
+
+//  printf("******************** adc() op1 = 0x%02x, op2=0x%02x , res=0x%02x \n", operand1, operand2, result);
+
+  FLAG_ASSIGN (BIT_Z, (result & 0xff) == 0);
+  FLAG_ASSIGN (BIT_C, 0x100 & result);
+  FLAG_ASSIGN (BIT_N, 0x80 & result);
+  FLAG_ASSIGN (BIT_H, 0x10 & (operand1 ^ operand2 ^ result));
+
+  regs.A = result & 0xff;
+  return(resGO);
+}
+
+int
+cl_st7::inst_and(t_mem code, unsigned char prefix)
+{
+  int operand2;
+
+  operand2 = OPERAND(code, prefix);
+  regs.A = regs.A & operand2;
+
+  FLAG_ASSIGN (BIT_Z, (regs.A & 0xff) == 0);
+  FLAG_ASSIGN (BIT_N, 0x80 & regs.A);
+
+  return(resGO);
+}
+
+int
+cl_st7::inst_bcp(t_mem code, unsigned char prefix)
+{
+  int operand2, opresult;
+
+  operand2 = OPERAND(code, prefix);
+  opresult = regs.A & operand2;
+
+  FLAG_ASSIGN (BIT_Z, (opresult & 0xff) == 0);
+  FLAG_ASSIGN (BIT_N, 0x80 & opresult);
+
+  return(resGO);
+}
+
+int
+cl_st7::inst_bresbset(t_mem code, unsigned char prefix)
+{
+  int ea = fetch();
+  unsigned char dbyte = get1( ea);
+  
+  if (code & 0x01) { // bres  
+	char pos = (code - 0x11) >> 1;
+	dbyte = dbyte & (~(1<> 1;
+	dbyte = dbyte | (1<> 1;
+	if(!( dbyte & (1<> 1;
+	if ( dbyte & (1<>1) & 7) {
+      case 0: // JRA / JRF
+        taken = 1;
+        break;
+      case 1: // JRUGT / JRULE
+        taken = !(regs.CC & (BIT_C | BIT_Z));
+        break;
+      case 2: // JRUGE / JRC
+        taken = !(regs.CC & BIT_C);
+        break;
+      case 3: // JRNE / JREQ
+        taken = !(regs.CC & BIT_Z);
+        break;
+      case 4: // JRNH / JRH
+        taken = !(regs.CC & BIT_H);
+        break;
+      case 5: // JRPL / JRMI
+        taken = !(regs.CC & BIT_N);
+        break;
+      case 6: // JRNM / JRM
+        taken = !(regs.CC & BIT_I);
         break;
       case 7: // JRIL - interrupt low - no means to test this ???
         taken = 1; 
-        
+        break;
       default:
         return(resHALT);
     } 
-  
-  if (code & 1)
-    taken = ! taken;
-  
-   if (prefix == 0x00) { // direct jump relative
-      ofs = fetch();
-   } else if (prefix == 0x92) { // pointer jump relative
-      ofs = get1(fetch());
-   } else {
-      return (resHALT);
-   }
-
-  if (taken)
-    PC += ofs;
-
-  return(resGO);
-}
-
-int
-cl_st7::inst_ldxy(t_mem code, unsigned char prefix)
-{
-  int operand;
-
-  operand = OPERAND(code, prefix);
-
-//  FLAG_ASSIGN (BIT_Z, (result & 0xff) == 0);
-//  FLAG_ASSIGN (BIT_C, 0x100 & result);
-//  FLAG_ASSIGN (BIT_N, 0x80 & result);
-//  FLAG_ASSIGN (BIT_H, 0x10 & (operand1 ^ operand2 ^ result));
-
-   if ((prefix == 0x90) || (prefix == 0x91)) {
-     regs.Y = operand;
-   } else {
-     regs.X = operand;
-   }
-   
-  return(resGO);
-}
-
-int
-cl_st7::inst_lda(t_mem code, unsigned char prefix)
-{
-  int operand;
-
-  operand = OPERAND(code, prefix);
-
-//  FLAG_ASSIGN (BIT_Z, (result & 0xff) == 0);
-//  FLAG_ASSIGN (BIT_C, 0x100 & result);
-//  FLAG_ASSIGN (BIT_N, 0x80 & result);
-//  FLAG_ASSIGN (BIT_H, 0x10 & (operand1 ^ operand2 ^ result));
-
-  regs.A = operand;
-   
-  return(resGO);
-}
-
-int
-cl_st7::inst_lddst(t_mem code, unsigned char prefix)
-{
-  unsigned int opaddr;
-
-   opaddr = fetchea(code,prefix);
-
-   FLAG_ASSIGN (BIT_Z, (regs.A & 0xff) == 0);
-   FLAG_ASSIGN (BIT_N, 0x80 & regs.A);
-
-   store1(opaddr, regs.A);
-  
-   return(resGO);
-}
-
-int
-cl_st7::inst_ldxydst(t_mem code, unsigned char prefix)
-{
-  unsigned int opaddr;
-
-   opaddr = fetchea(code,prefix);
-
-   if ((prefix == 0x90) || (prefix == 0x91)) {
-      FLAG_ASSIGN (BIT_Z, (regs.Y & 0xff) == 0);
-      FLAG_ASSIGN (BIT_N, 0x80 & regs.Y);
-
-      store1(opaddr, regs.Y);
-   } else {
-      FLAG_ASSIGN (BIT_Z, (regs.X & 0xff) == 0);
-      FLAG_ASSIGN (BIT_N, 0x80 & regs.X);
-
-      store1(opaddr, regs.X);
-   }
-   
-   return(resGO);
-}
-
-
-
-int
-cl_st7::inst_neg(t_mem code, unsigned char prefix)
-{
-  int operand;
-  unsigned int opaddr = 0xffff;
-
-   if ((code&0xf0)==0x40) {
-      operand = regs.A;
-   } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) {
-      operand = regs.X;
-   } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) {
-      operand = regs.Y;
-   } else {
-      opaddr = get_dest(code,prefix);
-      operand = get1(opaddr);
-   }
-   
-   operand ^= 0xff;
-   operand++;
-  
-   FLAG_ASSIGN (BIT_Z, (operand & 0xff) == 0);
-   FLAG_ASSIGN (BIT_C, operand);
-   if (operand == 0x80) {
-	   FLAG_SET (BIT_N);
-   } else {
-      FLAG_CLEAR (BIT_N);
-   }
-
-   if ((code&0xf0)==0x40) {
-      regs.A = operand;
-   } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) {
-      regs.X = operand;
-   } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) {
-      regs.Y = operand;
-   } else {
-      //printf("******************** inst_neg() end - addr=0x%04x, val=0x%02x\n", opaddr, operand);
-      store1(opaddr, operand);
-   }
-  
-   return(resGO);
-}
-
-int
-cl_st7::inst_or(t_mem code, unsigned char prefix)
-{
-  int result, operand1, operand2;
-
-  operand1 = regs.A;
-  operand2 = OPERAND(code, prefix);
-  result = operand1 | operand2;
-
-  FLAG_ASSIGN (BIT_Z, (result & 0xff) == 0);
-  //FLAG_ASSIGN (BIT_C, 0x100 & result);
-  FLAG_ASSIGN (BIT_N, 0x80 & result);
-  //FLAG_ASSIGN (BIT_H, 0x10 & (operand1 ^ operand2 ^ result));
-
-  regs.A = result & 0xff;
-  return(resGO);
-}
-
-int
-cl_st7::inst_rlc(t_mem code, unsigned char prefix)
-{
-  int operand;
-  unsigned int opaddr = 0xffff;
-
-   if ((code&0xf0)==0x40) {
-      operand = regs.A;
-   } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) {
-      operand = regs.X;
-   } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) {
-      operand = regs.Y;
-   } else {
-      opaddr = get_dest(code,prefix);
-      operand = get1(opaddr);
-   }
-   
-   operand <<= 0x1;
-   
-   if (regs.CC & BIT_C) {
-      operand++;
-   }
-  
-   FLAG_ASSIGN (BIT_Z, (operand & 0xff) == 0);
-   FLAG_ASSIGN (BIT_C, (operand & 0x100));
-   if (operand == 0x80) {
-	   FLAG_SET (BIT_N);
-   } else {
-      FLAG_CLEAR (BIT_N);
-   }
-
-   if ((code&0xf0)==0x40) {
-      regs.A = operand;
-   } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) {
-      regs.X = operand;
-   } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) {
-      regs.Y = operand;
-   } else {
-      store1(opaddr, operand);
-   }
-  
-   return(resGO);
-}
-
-int
-cl_st7::inst_rrc(t_mem code, unsigned char prefix)
-{
-  int operand, opres;
-  unsigned int opaddr = 0xffff;
-
-   if ((code&0xf0)==0x40) {
-      operand = regs.A;
-   } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) {
-      operand = regs.X;
-   } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) {
-      operand = regs.Y;
-   } else {
-      opaddr = get_dest(code,prefix);
-      operand = get1(opaddr);
-   }
-   
-   opres = operand >> 1;
-   
-   if (regs.CC & BIT_C) {
-      opres |= 0x80;
-   }
-  
-   FLAG_ASSIGN (BIT_Z, (opres & 0xff) == 0);
-   FLAG_ASSIGN (BIT_C, (operand & 0x1));
-   if (opres == 0x80) {
-	   FLAG_SET (BIT_N);
-   } else {
-      FLAG_CLEAR (BIT_N);
-   }
-
-   if ((code&0xf0)==0x40) {
-      regs.A = opres;
-   } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) {
-      regs.X = opres;
-   } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) {
-      regs.Y = opres;
-   } else {
-      store1(opaddr, opres);
-   }
-  
-   return(resGO);
-}
-
-int
-cl_st7::inst_sbc(t_mem code, unsigned char prefix)
-{
-  int result, operand1, operand2;
-
-  operand1 = regs.A;
-  operand2 = OPERAND(code, prefix);
-  result = operand1 - operand2;
-
-   if (regs.CC & BIT_C) {
-      result--;
-   }
-
-  FLAG_ASSIGN (BIT_Z, (result & 0xff) == 0);
-  FLAG_ASSIGN (BIT_C, 0x100 & result);
-  FLAG_ASSIGN (BIT_N, 0x80 & result);
-  //FLAG_ASSIGN (BIT_H, 0x10 & (operand1 ^ operand2 ^ result));
-
-  regs.A = result & 0xff;
-  return(resGO);
-}
-
-int
-cl_st7::inst_sll(t_mem code, unsigned char prefix)
-{
-  int operand, opres;
-  unsigned int opaddr = 0xffff;
-
-   if ((code&0xf0)==0x40) {
-      operand = regs.A;
-   } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) {
-      operand = regs.X;
-   } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) {
-      operand = regs.Y;
-   } else {
-      opaddr = get_dest(code,prefix);
-      operand = get1(opaddr);
-   }
-   
-   opres = operand << 1;
-   
-   FLAG_ASSIGN (BIT_Z, (opres & 0xff) == 0);
-   FLAG_ASSIGN (BIT_C, (opres & 0x100));
-   if (opres == 0x80) {
-	   FLAG_SET (BIT_N);
-   } else {
-      FLAG_CLEAR (BIT_N);
-   }
-
-   if ((code&0xf0)==0x40) {
-      regs.A = opres;
-   } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) {
-      regs.X = opres;
-   } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) {
-      regs.Y = opres;
-   } else {
-      store1(opaddr, opres);
-   }
-  
-   return(resGO);
-}
-
-int
-cl_st7::inst_sra(t_mem code, unsigned char prefix)
-{
-  int operand, opres;
-  unsigned int opaddr = 0xffff;
-
-   if ((code&0xf0)==0x40) {
-      operand = regs.A;
-   } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) {
-      operand = regs.X;
-   } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) {
-      operand = regs.Y;
-   } else {
-      opaddr = get_dest(code,prefix);
-      operand = get1(opaddr);
-   }
-   
-   opres = operand >> 1;
-   
-   if (opres > 0x3f) { // copy bit6 to bit7
-      opres |= 0x80;
-   }
-  
-   FLAG_ASSIGN (BIT_Z, (opres & 0xff) == 0);
-   FLAG_ASSIGN (BIT_C, (operand & 0x1));
-   if (opres == 0x80) {
-	   FLAG_SET (BIT_N);
-   } else {
-      FLAG_CLEAR (BIT_N);
-   }
-
-   if ((code&0xf0)==0x40) {
-      regs.A = opres;
-   } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) {
-      regs.X = opres;
-   } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) {
-      regs.Y = opres;
-   } else {
-      store1(opaddr, opres);
-   }
-  
-   return(resGO);
-}
-
-int
-cl_st7::inst_srl(t_mem code, unsigned char prefix)
-{
-  int operand, opres;
-  unsigned int opaddr = 0xffff;
-
-   if ((code&0xf0)==0x40) {
-      operand = regs.A;
-   } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) {
-      operand = regs.X;
-   } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) {
-      operand = regs.Y;
-   } else {
-      opaddr = get_dest(code,prefix);
-      operand = get1(opaddr);
-   }
-   
-   opres = operand >> 1;
-   
-   FLAG_ASSIGN (BIT_Z, (opres & 0xff) == 0);
-   FLAG_ASSIGN (BIT_C, (operand & 0x1));
-   if (opres == 0x80) {
-	   FLAG_SET (BIT_N);
-   } else {
-      FLAG_CLEAR (BIT_N);
-   }
-
-   if ((code&0xf0)==0x40) {
-      regs.A = opres;
-   } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) {
-      regs.X = opres;
-   } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) {
-      regs.Y = opres;
-   } else {
-      store1(opaddr, opres);
-   }
-  
-   return(resGO);
-}
-
-int
-cl_st7::inst_sub(t_mem code, unsigned char prefix)
-{
-  int result, operand1, operand2;
-
-  operand1 = regs.A;
-  operand2 = OPERAND(code, prefix);
-  result = operand1 - operand2;
-
-  FLAG_ASSIGN (BIT_Z, (result & 0xff) == 0);
-  FLAG_ASSIGN (BIT_C, 0x100 & result);
-  FLAG_ASSIGN (BIT_N, 0x80 & result);
-  //FLAG_ASSIGN (BIT_H, 0x10 & (operand1 ^ operand2 ^ result));
-
-  regs.A = result & 0xff;
-  return(resGO);
-}
-
-int
-cl_st7::inst_swap(t_mem code, unsigned char prefix)
-{
-  int operand, opres;
-  unsigned int opaddr = 0xffff;
-
-   if ((code&0xf0)==0x40) {
-      operand = regs.A;
-   } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) {
-      operand = regs.X;
-   } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) {
-      operand = regs.Y;
-   } else {
-      opaddr = get_dest(code,prefix);
-      operand = get1(opaddr);
-   }
-   
-   opres = operand << 4;
-   opres |= (operand >> 4);
-   
-   
-   FLAG_ASSIGN (BIT_Z, (opres & 0xff) == 0);
-   if (opres == 0x80) {
-	   FLAG_SET (BIT_N);
-   } else {
-      FLAG_CLEAR (BIT_N);
-   }
-
-   if ((code&0xf0)==0x40) {
-      regs.A = opres;
-   } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) {
-      regs.X = opres;
-   } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) {
-      regs.Y = opres;
-   } else {
-      store1(opaddr, opres);
-   }
-  
-   return(resGO);
-}
-
-int
-cl_st7::inst_tnz(t_mem code, unsigned char prefix)
-{
-  int operand;
-  unsigned int opaddr = 0xffff;
-
-   if ((code&0xf0)==0x40) {
-      operand = regs.A;
-   } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) {
-      operand = regs.X;
-   } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) {
-      operand = regs.Y;
-   } else {
-      opaddr = get_dest(code,prefix);
-      operand = get1(opaddr);
-   }
-   
-   FLAG_ASSIGN (BIT_Z, (operand & 0xff) == 0);
-   if (operand == 0x80) {
-	   FLAG_SET (BIT_N);
-   } else {
-      FLAG_CLEAR (BIT_N);
-   }
-
-   return(resGO);
-}
-
-int
-cl_st7::inst_xor(t_mem code, unsigned char prefix)
-{
-  int result, operand1, operand2;
-
-  operand1 = regs.A;
-  operand2 = OPERAND(code, prefix);
-  result = operand1 ^ operand2;
-
-  FLAG_ASSIGN (BIT_Z, (result & 0xff) == 0);
-  FLAG_ASSIGN (BIT_N, 0x80 & result);
-
-  regs.A = result & 0xff;
-  return(resGO);
-}
-
-/* End of st7.src/inst.cc */
+  if (code & 1)
+    taken = ! taken;
+  
+   if (prefix == 0x00) { // direct jump relative
+      ofs = fetch();
+   } else if (prefix == 0x92) { // pointer jump relative
+      ofs = get1(fetch());
+   } else {
+      return (resHALT);
+   }
+
+  if (taken)
+    PC += ofs;
+
+  return(resGO);
+}
+
+int
+cl_st7::inst_ldxy(t_mem code, unsigned char prefix)
+{
+  int operand;
+
+  operand = OPERAND(code, prefix);
+
+//  FLAG_ASSIGN (BIT_Z, (result & 0xff) == 0);
+//  FLAG_ASSIGN (BIT_C, 0x100 & result);
+//  FLAG_ASSIGN (BIT_N, 0x80 & result);
+//  FLAG_ASSIGN (BIT_H, 0x10 & (operand1 ^ operand2 ^ result));
+
+   if ((prefix == 0x90) || (prefix == 0x91)) {
+     regs.Y = operand;
+   } else {
+     regs.X = operand;
+   }
+   
+  return(resGO);
+}
+
+int
+cl_st7::inst_lda(t_mem code, unsigned char prefix)
+{
+  int operand;
+
+  operand = OPERAND(code, prefix);
+
+//  FLAG_ASSIGN (BIT_Z, (result & 0xff) == 0);
+//  FLAG_ASSIGN (BIT_C, 0x100 & result);
+//  FLAG_ASSIGN (BIT_N, 0x80 & result);
+//  FLAG_ASSIGN (BIT_H, 0x10 & (operand1 ^ operand2 ^ result));
+
+  regs.A = operand;
+   
+  return(resGO);
+}
+
+int
+cl_st7::inst_lddst(t_mem code, unsigned char prefix)
+{
+  unsigned int opaddr;
+
+   opaddr = fetchea(code,prefix);
+
+   FLAG_ASSIGN (BIT_Z, (regs.A & 0xff) == 0);
+   FLAG_ASSIGN (BIT_N, 0x80 & regs.A);
+
+   store1(opaddr, regs.A);
+  
+   return(resGO);
+}
+
+int
+cl_st7::inst_ldxydst(t_mem code, unsigned char prefix)
+{
+  unsigned int opaddr;
+
+   opaddr = fetchea(code,prefix);
+
+   if ((prefix == 0x90) || (prefix == 0x91)) {
+      FLAG_ASSIGN (BIT_Z, (regs.Y & 0xff) == 0);
+      FLAG_ASSIGN (BIT_N, 0x80 & regs.Y);
+
+      store1(opaddr, regs.Y);
+   } else {
+      FLAG_ASSIGN (BIT_Z, (regs.X & 0xff) == 0);
+      FLAG_ASSIGN (BIT_N, 0x80 & regs.X);
+
+      store1(opaddr, regs.X);
+   }
+   
+   return(resGO);
+}
+
+
+
+int
+cl_st7::inst_neg(t_mem code, unsigned char prefix)
+{
+  int operand;
+  unsigned int opaddr = 0xffff;
+
+   if ((code&0xf0)==0x40) {
+      operand = regs.A;
+   } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) {
+      operand = regs.X;
+   } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) {
+      operand = regs.Y;
+   } else {
+      opaddr = get_dest(code,prefix);
+      operand = get1(opaddr);
+   }
+   
+   operand ^= 0xff;
+   operand++;
+  
+   FLAG_ASSIGN (BIT_Z, (operand & 0xff) == 0);
+   FLAG_ASSIGN (BIT_C, operand);
+   if (operand == 0x80) {
+	   FLAG_SET (BIT_N);
+   } else {
+      FLAG_CLEAR (BIT_N);
+   }
+
+   if ((code&0xf0)==0x40) {
+      regs.A = operand;
+   } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) {
+      regs.X = operand;
+   } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) {
+      regs.Y = operand;
+   } else {
+      //printf("******************** inst_neg() end - addr=0x%04x, val=0x%02x\n", opaddr, operand);
+      store1(opaddr, operand);
+   }
+  
+   return(resGO);
+}
+
+int
+cl_st7::inst_or(t_mem code, unsigned char prefix)
+{
+  int result, operand1, operand2;
+
+  operand1 = regs.A;
+  operand2 = OPERAND(code, prefix);
+  result = operand1 | operand2;
+
+  FLAG_ASSIGN (BIT_Z, (result & 0xff) == 0);
+  //FLAG_ASSIGN (BIT_C, 0x100 & result);
+  FLAG_ASSIGN (BIT_N, 0x80 & result);
+  //FLAG_ASSIGN (BIT_H, 0x10 & (operand1 ^ operand2 ^ result));
+
+  regs.A = result & 0xff;
+  return(resGO);
+}
+
+int
+cl_st7::inst_rlc(t_mem code, unsigned char prefix)
+{
+  int operand;
+  unsigned int opaddr = 0xffff;
+
+   if ((code&0xf0)==0x40) {
+      operand = regs.A;
+   } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) {
+      operand = regs.X;
+   } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) {
+      operand = regs.Y;
+   } else {
+      opaddr = get_dest(code,prefix);
+      operand = get1(opaddr);
+   }
+   
+   operand <<= 0x1;
+   
+   if (regs.CC & BIT_C) {
+      operand++;
+   }
+  
+   FLAG_ASSIGN (BIT_Z, (operand & 0xff) == 0);
+   FLAG_ASSIGN (BIT_C, (operand & 0x100));
+   if (operand == 0x80) {
+	   FLAG_SET (BIT_N);
+   } else {
+      FLAG_CLEAR (BIT_N);
+   }
+
+   if ((code&0xf0)==0x40) {
+      regs.A = operand;
+   } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) {
+      regs.X = operand;
+   } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) {
+      regs.Y = operand;
+   } else {
+      store1(opaddr, operand);
+   }
+  
+   return(resGO);
+}
+
+int
+cl_st7::inst_rrc(t_mem code, unsigned char prefix)
+{
+  int operand, opres;
+  unsigned int opaddr = 0xffff;
+
+   if ((code&0xf0)==0x40) {
+      operand = regs.A;
+   } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) {
+      operand = regs.X;
+   } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) {
+      operand = regs.Y;
+   } else {
+      opaddr = get_dest(code,prefix);
+      operand = get1(opaddr);
+   }
+   
+   opres = operand >> 1;
+   
+   if (regs.CC & BIT_C) {
+      opres |= 0x80;
+   }
+  
+   FLAG_ASSIGN (BIT_Z, (opres & 0xff) == 0);
+   FLAG_ASSIGN (BIT_C, (operand & 0x1));
+   if (opres == 0x80) {
+	   FLAG_SET (BIT_N);
+   } else {
+      FLAG_CLEAR (BIT_N);
+   }
+
+   if ((code&0xf0)==0x40) {
+      regs.A = opres;
+   } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) {
+      regs.X = opres;
+   } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) {
+      regs.Y = opres;
+   } else {
+      store1(opaddr, opres);
+   }
+  
+   return(resGO);
+}
+
+int
+cl_st7::inst_sbc(t_mem code, unsigned char prefix)
+{
+  int result, operand1, operand2;
+
+  operand1 = regs.A;
+  operand2 = OPERAND(code, prefix);
+  result = operand1 - operand2;
+
+   if (regs.CC & BIT_C) {
+      result--;
+   }
+
+  FLAG_ASSIGN (BIT_Z, (result & 0xff) == 0);
+  FLAG_ASSIGN (BIT_C, 0x100 & result);
+  FLAG_ASSIGN (BIT_N, 0x80 & result);
+  //FLAG_ASSIGN (BIT_H, 0x10 & (operand1 ^ operand2 ^ result));
+
+  regs.A = result & 0xff;
+  return(resGO);
+}
+
+int
+cl_st7::inst_sll(t_mem code, unsigned char prefix)
+{
+  int operand, opres;
+  unsigned int opaddr = 0xffff;
+
+   if ((code&0xf0)==0x40) {
+      operand = regs.A;
+   } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) {
+      operand = regs.X;
+   } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) {
+      operand = regs.Y;
+   } else {
+      opaddr = get_dest(code,prefix);
+      operand = get1(opaddr);
+   }
+   
+   opres = operand << 1;
+   
+   FLAG_ASSIGN (BIT_Z, (opres & 0xff) == 0);
+   FLAG_ASSIGN (BIT_C, (opres & 0x100));
+   if (opres == 0x80) {
+	   FLAG_SET (BIT_N);
+   } else {
+      FLAG_CLEAR (BIT_N);
+   }
+
+   if ((code&0xf0)==0x40) {
+      regs.A = opres;
+   } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) {
+      regs.X = opres;
+   } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) {
+      regs.Y = opres;
+   } else {
+      store1(opaddr, opres);
+   }
+  
+   return(resGO);
+}
+
+int
+cl_st7::inst_sra(t_mem code, unsigned char prefix)
+{
+  int operand, opres;
+  unsigned int opaddr = 0xffff;
+
+   if ((code&0xf0)==0x40) {
+      operand = regs.A;
+   } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) {
+      operand = regs.X;
+   } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) {
+      operand = regs.Y;
+   } else {
+      opaddr = get_dest(code,prefix);
+      operand = get1(opaddr);
+   }
+   
+   opres = operand >> 1;
+   
+   if (opres > 0x3f) { // copy bit6 to bit7
+      opres |= 0x80;
+   }
+  
+   FLAG_ASSIGN (BIT_Z, (opres & 0xff) == 0);
+   FLAG_ASSIGN (BIT_C, (operand & 0x1));
+   if (opres == 0x80) {
+	   FLAG_SET (BIT_N);
+   } else {
+      FLAG_CLEAR (BIT_N);
+   }
+
+   if ((code&0xf0)==0x40) {
+      regs.A = opres;
+   } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) {
+      regs.X = opres;
+   } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) {
+      regs.Y = opres;
+   } else {
+      store1(opaddr, opres);
+   }
+  
+   return(resGO);
+}
+
+int
+cl_st7::inst_srl(t_mem code, unsigned char prefix)
+{
+  int operand, opres;
+  unsigned int opaddr = 0xffff;
+
+   if ((code&0xf0)==0x40) {
+      operand = regs.A;
+   } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) {
+      operand = regs.X;
+   } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) {
+      operand = regs.Y;
+   } else {
+      opaddr = get_dest(code,prefix);
+      operand = get1(opaddr);
+   }
+   
+   opres = operand >> 1;
+   
+   FLAG_ASSIGN (BIT_Z, (opres & 0xff) == 0);
+   FLAG_ASSIGN (BIT_C, (operand & 0x1));
+   if (opres == 0x80) {
+	   FLAG_SET (BIT_N);
+   } else {
+      FLAG_CLEAR (BIT_N);
+   }
+
+   if ((code&0xf0)==0x40) {
+      regs.A = opres;
+   } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) {
+      regs.X = opres;
+   } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) {
+      regs.Y = opres;
+   } else {
+      store1(opaddr, opres);
+   }
+  
+   return(resGO);
+}
+
+int
+cl_st7::inst_sub(t_mem code, unsigned char prefix)
+{
+  int result, operand1, operand2;
+
+  operand1 = regs.A;
+  operand2 = OPERAND(code, prefix);
+  result = operand1 - operand2;
+
+  FLAG_ASSIGN (BIT_Z, (result & 0xff) == 0);
+  FLAG_ASSIGN (BIT_C, 0x100 & result);
+  FLAG_ASSIGN (BIT_N, 0x80 & result);
+  //FLAG_ASSIGN (BIT_H, 0x10 & (operand1 ^ operand2 ^ result));
+
+  regs.A = result & 0xff;
+  return(resGO);
+}
+
+int
+cl_st7::inst_swap(t_mem code, unsigned char prefix)
+{
+  int operand, opres;
+  unsigned int opaddr = 0xffff;
+
+   if ((code&0xf0)==0x40) {
+      operand = regs.A;
+   } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) {
+      operand = regs.X;
+   } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) {
+      operand = regs.Y;
+   } else {
+      opaddr = get_dest(code,prefix);
+      operand = get1(opaddr);
+   }
+   
+   opres = operand << 4;
+   opres |= (operand >> 4);
+   
+   
+   FLAG_ASSIGN (BIT_Z, (opres & 0xff) == 0);
+   if (opres == 0x80) {
+	   FLAG_SET (BIT_N);
+   } else {
+      FLAG_CLEAR (BIT_N);
+   }
+
+   if ((code&0xf0)==0x40) {
+      regs.A = opres;
+   } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) {
+      regs.X = opres;
+   } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) {
+      regs.Y = opres;
+   } else {
+      store1(opaddr, opres);
+   }
+  
+   return(resGO);
+}
+
+int
+cl_st7::inst_tnz(t_mem code, unsigned char prefix)
+{
+  int operand;
+  unsigned int opaddr = 0xffff;
+
+   if ((code&0xf0)==0x40) {
+      operand = regs.A;
+   } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) {
+      operand = regs.X;
+   } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) {
+      operand = regs.Y;
+   } else {
+      opaddr = get_dest(code,prefix);
+      operand = get1(opaddr);
+   }
+   
+   FLAG_ASSIGN (BIT_Z, (operand & 0xff) == 0);
+   if (operand == 0x80) {
+	   FLAG_SET (BIT_N);
+   } else {
+      FLAG_CLEAR (BIT_N);
+   }
+
+   return(resGO);
+}
+
+int
+cl_st7::inst_xor(t_mem code, unsigned char prefix)
+{
+  int result, operand1, operand2;
+
+  operand1 = regs.A;
+  operand2 = OPERAND(code, prefix);
+  result = operand1 ^ operand2;
+
+  FLAG_ASSIGN (BIT_Z, (result & 0xff) == 0);
+  FLAG_ASSIGN (BIT_N, 0x80 & result);
+
+  regs.A = result & 0xff;
+  return(resGO);
+}
+
+/* End of st7.src/inst.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/st7.src/instcl.h sdcc-4.2.0+dfsg/sim/ucsim/st7.src/instcl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/st7.src/instcl.h	2012-12-23 20:32:49.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/st7.src/instcl.h	2020-09-17 06:45:33.000000000 +0000
@@ -1,39 +1,39 @@
-/* st7.src/instcl.h */
-
-  //virtual void incx(void);
-  virtual unsigned int fetchea(t_mem code, unsigned char prefix);
-  virtual int get_dest(t_mem code, unsigned char prefix);
-
-  virtual int inst_adc(t_mem code, unsigned char prefix);
-  virtual int inst_add(t_mem code, unsigned char prefix);
-  virtual int inst_and(t_mem code, unsigned char prefix);
-  virtual int inst_bcp(t_mem code, unsigned char prefix);
-  virtual int inst_bresbset(t_mem code, unsigned char prefix);
-  virtual int inst_btjfbtjt(t_mem code, unsigned char prefix);
-  virtual int inst_call(t_mem code, unsigned char prefix);
-  virtual int inst_callr(t_mem code, unsigned char prefix);
-  virtual int inst_clr(t_mem code, unsigned char prefix);
-  virtual int inst_cp(t_mem code, unsigned char prefix);
-  virtual int inst_cpxy(t_mem code, unsigned char prefix);
-  virtual int inst_cpl(t_mem code, unsigned char prefix);
-  virtual int inst_dec(t_mem code, unsigned char prefix);
-  virtual int inst_inc(t_mem code, unsigned char prefix);
-  virtual int inst_jr(t_mem code, unsigned char prefix);
-  virtual int inst_lda(t_mem code, unsigned char prefix);
-  virtual int inst_ldxy(t_mem code, unsigned char prefix);
-  virtual int inst_lddst(t_mem code, unsigned char prefix);
-  virtual int inst_ldxydst(t_mem code, unsigned char prefix);
-  virtual int inst_neg(t_mem code, unsigned char prefix);
-  virtual int inst_or(t_mem code, unsigned char prefix);
-  virtual int inst_rlc(t_mem code, unsigned char prefix);
-  virtual int inst_rrc(t_mem code, unsigned char prefix);
-  virtual int inst_sbc(t_mem code, unsigned char prefix);
-  virtual int inst_sll(t_mem code, unsigned char prefix);
-  virtual int inst_sra(t_mem code, unsigned char prefix);
-  virtual int inst_srl(t_mem code, unsigned char prefix);
-  virtual int inst_sub(t_mem code, unsigned char prefix);
-  virtual int inst_swap(t_mem code, unsigned char prefix);
-  virtual int inst_tnz(t_mem code, unsigned char prefix);
-  virtual int inst_xor(t_mem code, unsigned char prefix);
-  
-/* End of st7.src/instcl.h */
+/* st7.src/instcl.h */
+
+  //virtual void incx(void);
+  virtual unsigned int fetchea(t_mem code, unsigned char prefix);
+  virtual int get_dest(t_mem code, unsigned char prefix);
+
+  virtual int inst_adc(t_mem code, unsigned char prefix);
+  virtual int inst_add(t_mem code, unsigned char prefix);
+  virtual int inst_and(t_mem code, unsigned char prefix);
+  virtual int inst_bcp(t_mem code, unsigned char prefix);
+  virtual int inst_bresbset(t_mem code, unsigned char prefix);
+  virtual int inst_btjfbtjt(t_mem code, unsigned char prefix);
+  virtual int inst_call(t_mem code, unsigned char prefix);
+  virtual int inst_callr(t_mem code, unsigned char prefix);
+  virtual int inst_clr(t_mem code, unsigned char prefix);
+  virtual int inst_cp(t_mem code, unsigned char prefix);
+  virtual int inst_cpxy(t_mem code, unsigned char prefix);
+  virtual int inst_cpl(t_mem code, unsigned char prefix);
+  virtual int inst_dec(t_mem code, unsigned char prefix);
+  virtual int inst_inc(t_mem code, unsigned char prefix);
+  virtual int inst_jr(t_mem code, unsigned char prefix);
+  virtual int inst_lda(t_mem code, unsigned char prefix);
+  virtual int inst_ldxy(t_mem code, unsigned char prefix);
+  virtual int inst_lddst(t_mem code, unsigned char prefix);
+  virtual int inst_ldxydst(t_mem code, unsigned char prefix);
+  virtual int inst_neg(t_mem code, unsigned char prefix);
+  virtual int inst_or(t_mem code, unsigned char prefix);
+  virtual int inst_rlc(t_mem code, unsigned char prefix);
+  virtual int inst_rrc(t_mem code, unsigned char prefix);
+  virtual int inst_sbc(t_mem code, unsigned char prefix);
+  virtual int inst_sll(t_mem code, unsigned char prefix);
+  virtual int inst_sra(t_mem code, unsigned char prefix);
+  virtual int inst_srl(t_mem code, unsigned char prefix);
+  virtual int inst_sub(t_mem code, unsigned char prefix);
+  virtual int inst_swap(t_mem code, unsigned char prefix);
+  virtual int inst_tnz(t_mem code, unsigned char prefix);
+  virtual int inst_xor(t_mem code, unsigned char prefix);
+  
+/* End of st7.src/instcl.h */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/st7.src/Makefile.in sdcc-4.2.0+dfsg/sim/ucsim/st7.src/Makefile.in
--- sdcc-4.0.0+dfsg/sim/ucsim/st7.src/Makefile.in	2017-03-12 13:28:55.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/st7.src/Makefile.in	2022-01-09 14:02:03.000000000 +0000
@@ -1,163 +1,187 @@
-#
-# uCsim st7.src/Makefile
-#
-# (c) Drotos Daniel, Talker Bt. 1997
-#
-
-STARTYEAR	= 1997
-
-SHELL		= /bin/sh
-CXX		= @CXX@
-CPP		= @CPP@
-CXXCPP		= @CXXCPP@
-RANLIB		= @RANLIB@
-INSTALL		= @INSTALL@
-STRIP		= @STRIP@
-MAKEDEP         = @MAKEDEP@
-
-top_builddir	= @top_builddir@
-top_srcdir	= @top_srcdir@
-
-transform	= @program_transform_name@
-
-DEFS            = $(subs -DHAVE_CONFIG_H,,@DEFS@)
-CPPFLAGS        = @CPPFLAGS@ -I$(srcdir) -I$(top_srcdir) -I$(top_builddir) \
-		  -I$(top_srcdir)/cmd.src -I$(top_srcdir)/sim.src \
-		  -I$(top_srcdir)/gui.src
-CFLAGS          = @CFLAGS@ @WALL_FLAG@
-CXXFLAGS        = @CXXFLAGS@ @WALL_FLAG@
-LDFLAGS         = @LDFLAGS@
-PICOPT		= @PICOPT@
-SHAREDLIB	= @SHAREDLIB@
-
-EXEEXT          = @EXEEXT@
-
-LIBS		= -L$(top_builddir) -lsim -lucsimutil -lguiucsim -lcmd -lsim @LIBS@
-DL		= @DL@
-dl_ok		= @dl_ok@
-
-prefix          = @prefix@
-exec_prefix     = @exec_prefix@
-bindir          = @bindir@
-libdir          = @libdir@
-datadir         = @datadir@
-datarootdir     = @datarootdir@
-includedir      = @includedir@
-mandir          = @mandir@
-man1dir         = $(mandir)/man1
-man2dir         = $(mandir)/man2
-infodir         = @infodir@
-srcdir          = @srcdir@
-VPATH           = @srcdir@
-
-OBJECTS_SHARED	= glob.o \
-		  inst.o \
-		  simst7.o st7.o
-OBJECTS_EXE	= sst7.o
-OBJECTS		= $(OBJECTS_SHARED) $(OBJECTS_EXE)
-
-ST7ASM		= 
-
-enable_dlso	= @enable_dlso@
-dlso_ok		= @dlso_ok@
-
-#TEST_OBJ	= test_bit.hex test_dis.hex test_mov.hex test_jmp.hex \
-#		  test_arith.hex
-
-# Compiling entire program or any subproject
-# ------------------------------------------
-all: checkconf otherlibs st7.src tests
-
-tests: $(TEST_OBJ)
-
-
-# Compiling and installing everything and runing test
-# ---------------------------------------------------
-install: all installdirs
-	$(INSTALL) sst7$(EXEEXT) $(DESTDIR)$(bindir)/`echo sst7|sed '$(transform)'`$(EXEEXT)
-	$(STRIP) $(DESTDIR)$(bindir)/`echo sst7|sed '$(transform)'`$(EXEEXT)
-
-
-# Deleting all the installed files
-# --------------------------------
-uninstall:
-	rm -f $(DESTDIR)$(bindir)/`echo sst7|sed '$(transform)'`$(EXEEXT)
-
-
-# Performing self-test
-# --------------------
-check: test
-
-test:
-
-
-# Performing installation test
-# ----------------------------
-installcheck:
-
-
-# Creating installation directories
-# ---------------------------------
-installdirs:
-	test -d $(DESTDIR)$(bindir) || $(INSTALL) -d $(DESTDIR)$(bindir)
-
-
-# Creating dependencies
-# ---------------------
-dep: Makefile.dep
-
-Makefile.dep: $(srcdir)/*.cc $(srcdir)/*.h
-	$(MAKEDEP) $(CPPFLAGS) $(filter %.cc,$^) >Makefile.dep
-
--include Makefile.dep
-include $(srcdir)/clean.mk
-
-# My rules
-# --------
-.SUFFIXES: .asm .hex
-
-st7.src: sst7$(EXEEXT)  shared_lib
-
-sst7$(EXEEXT): $(OBJECTS) $(top_builddir)/libcmd.a $(top_builddir)/libguiucsim.a $(top_builddir)/libsim.a $(top_builddir)/libucsimutil.a
-	$(CXX) $(CXXFLAGS) $(LDFLAGS) $(OBJECTS) $(LIBS) -o $@
-
-ifeq ($(dlso_ok),yes)
-shared_lib: $(top_builddir)/sst7.so
-else
-shared_lib:
-	@$(top_srcdir)/mkecho $(top_builddir) "No st7 shared lib made."
-	@$(top_srcdir)/mkecho $(top_builddir) "(SHAREDLIB="$(SHAREDLIB)",dl_ok="$(dl_ok)",enable_dlso="$(enable_dlso)")"
-endif
-
-$(top_builddir)/sst7.so: $(OBJECTS_SHARED)
-	$(CXX) -shared $(LDFLAGS) $(OBJECTS_SHARED) -o $(top_builddir)/sst7.so
-
-otherlibs: $(top_builddir)/libcmd.a $(top_builddir)/libguiucsim.a $(top_builddir)/libsim.a $(top_builddir)/libucsimutil.a
-
-$(top_builddir)/libcmd.a:
-	$(MAKE) -C $(top_builddir)/cmd.src all
-
-$(top_builddir)/libguiucsim.a:
-	$(MAKE) -C $(top_builddir)/gui.src checkconf ucsim_lib
-
-$(top_builddir)/libsim.a:
-	$(MAKE) -C $(top_builddir)/sim.src all
-
-$(top_builddir)/libucsimutil.a:
-	$(MAKE) -C $(top_builddir) -f main.mk
-
-.cc.o:
-	$(CXX) $(CXXFLAGS) $(CPPFLAGS) $(TARGET_ARCH) -c $< -o $@
-
-.asm.hex:
-	$(ST7ASM) -l $< -o $@ -e $<.lst
-
-
-# Remaking configuration
-# ----------------------
-checkconf:
-	@if [ -f $(top_builddir)/devel ]; then\
-	  $(MAKE) -f conf.mk srcdir="$(srcdir)" top_builddir="$(top_builddir)" freshconf;\
-	fi
-
-# End of st7.src/Makefile.in
+#
+# uCsim st7.src/Makefile
+#
+# (c) Drotos Daniel, Talker Bt. 1997
+#
+
+# tool name
+TN		= st7
+
+STARTYEAR	= 1997
+
+SHELL		= /bin/sh
+CXX		= @CXX@
+CPP		= @CPP@
+CXXCPP		= @CXXCPP@
+RANLIB		= @RANLIB@
+INSTALL		= @INSTALL@
+STRIP		= @STRIP@
+MAKEDEP         = @MAKEDEP@
+
+top_builddir	= @top_builddir@
+top_srcdir	= @top_srcdir@
+
+transform	= @program_transform_name@
+
+DEFS            = $(subs -DHAVE_CONFIG_H,,@DEFS@)
+CPPFLAGS        = @CPPFLAGS@ -I$(srcdir) -I$(top_srcdir) -I$(top_builddir) \
+		  -I$(top_srcdir)/cmd.src -I$(top_srcdir)/sim.src \
+		  -I$(top_srcdir)/gui.src
+CFLAGS          = @WALL_FLAG@ @CFLAGS@
+CXXFLAGS        = @WALL_FLAG@ @CXXFLAGS@
+LDFLAGS         = @LDFLAGS@
+PICOPT		= @PICOPT@
+SHAREDLIB	= @SHAREDLIB@
+
+EXEEXT          = @EXEEXT@
+
+LIBS		= -L$(top_builddir) -lsim -lucsimutil -lguiucsim -lcmd -lsim @LIBS@
+DL		= @DL@
+dl_ok		= @dl_ok@
+
+prefix          = @prefix@
+exec_prefix     = @exec_prefix@
+bindir          = @bindir@
+libdir          = @libdir@
+datadir         = @datadir@
+datarootdir     = @datarootdir@
+includedir      = @includedir@
+mandir          = @mandir@
+man1dir         = $(mandir)/man1
+man2dir         = $(mandir)/man2
+infodir         = @infodir@
+srcdir          = @srcdir@
+VPATH           = @srcdir@
+
+OBJECTS_SHARED	= glob.o \
+		  inst.o \
+		  sim$(TN).o $(TN).o
+OBJECTS_EXE	= s$(TN).o
+OBJECTS		= $(OBJECTS_SHARED) $(OBJECTS_EXE)
+
+ST7ASM		= 
+
+# short/long exe and lib name
+SEN		= s$(TN)$(EXEEXT)
+LEN		= ucsim_$(TN)$(EXEEXT)
+SONAME		= libucsim_$(TN).so
+
+enable_dlso	= @enable_dlso@
+dlso_ok		= @dlso_ok@
+
+#TEST_OBJ	= test_bit.hex test_dis.hex test_mov.hex test_jmp.hex \
+#		  test_arith.hex
+
+# Compiling entire program or any subproject
+# ------------------------------------------
+all: checkconf otherlibs $(TN).src tests
+
+tests: $(TEST_OBJ)
+
+
+# Compiling and installing everything and runing test
+# ---------------------------------------------------
+install: all installdirs install_shared_lib
+	$(INSTALL) $(SEN) $(DESTDIR)$(bindir)/$(SEN)
+	$(STRIP) $(DESTDIR)$(bindir)/$(SEN)
+	$(INSTALL) $(LEN) $(DESTDIR)$(bindir)/$(LEN)
+	$(STRIP) $(DESTDIR)$(bindir)/$(LEN)
+
+
+# Deleting all the installed files
+# --------------------------------
+uninstall:
+	rm -f $(DESTDIR)$(bindir)/$(SEN)
+	rm -f $(DESTDIR)$(bindir)/$(LEN)
+	rm -f $(DESTDIR)$(libdir)/$(SONAME)
+
+
+# Performing self-test
+# --------------------
+check: test
+
+.PHONY:	test baseline
+test:
+	@$(MAKE) --no-print-directory -C test
+
+baseline:
+	@$(MAKE) --no-print-directory -C test baseline
+
+
+# Performing installation test
+# ----------------------------
+installcheck:
+
+
+# Creating installation directories
+# ---------------------------------
+installdirs:
+	test -d $(DESTDIR)$(bindir) || $(INSTALL) -d $(DESTDIR)$(bindir)
+
+
+# Creating dependencies
+# ---------------------
+dep: Makefile.dep
+
+Makefile.dep: $(srcdir)/*.cc $(srcdir)/*.h
+	$(MAKEDEP) $(CPPFLAGS) $(filter %.cc,$^) >Makefile.dep
+
+-include Makefile.dep
+include $(srcdir)/clean.mk
+
+# My rules
+# --------
+.SUFFIXES: .asm .hex
+
+$(TN).src: $(SEN) $(LEN) shared_lib
+
+$(SEN): $(OBJECTS) $(top_builddir)/libcmd.a $(top_builddir)/libguiucsim.a $(top_builddir)/libsim.a $(top_builddir)/libucsimutil.a
+	$(CXX) $(CXXFLAGS) $(LDFLAGS) $(OBJECTS) $(LIBS) -o $@
+
+$(LEN): s$(TN)$(EXEEXT)
+	cp $< $@
+
+ifeq ($(dlso_ok),yes)
+shared_lib: $(top_builddir)/$(SONAME)
+install_shared_lib: shared_lib
+	test -d $(DESTDIR)$(libdir) || $(INSTALL) -d $(DESTDIR)$(libdir)
+	$(INSTALL) $(top_builddir)/$(SONAME) $(DESTDIR)$(libdir)/$(SONAME)
+else
+shared_lib:
+	@$(top_srcdir)/mkecho $(top_builddir) "No $(TN) shared lib made."
+	@$(top_srcdir)/mkecho $(top_builddir) "(SHAREDLIB="$(SHAREDLIB)",dl_ok="$(dl_ok)",enable_dlso="$(enable_dlso)")"
+install_shared_lib:
+endif
+
+$(top_builddir)/$(SONAME): $(OBJECTS_SHARED)
+	$(CXX) -shared $(LDFLAGS) $(OBJECTS_SHARED) -o $(top_builddir)/s$(TN).so
+
+otherlibs: $(top_builddir)/libcmd.a $(top_builddir)/libguiucsim.a $(top_builddir)/libsim.a $(top_builddir)/libucsimutil.a
+
+$(top_builddir)/libcmd.a:
+	$(MAKE) -C $(top_builddir)/cmd.src all
+
+$(top_builddir)/libguiucsim.a:
+	$(MAKE) -C $(top_builddir)/gui.src checkconf ucsim_lib
+
+$(top_builddir)/libsim.a:
+	$(MAKE) -C $(top_builddir)/sim.src all
+
+$(top_builddir)/libucsimutil.a:
+	$(MAKE) -C $(top_builddir) -f main.mk
+
+.cc.o:
+	$(CXX) $(CXXFLAGS) $(PICOPT) $(CPPFLAGS) $(TARGET_ARCH) -c $< -o $@
+
+.asm.hex:
+	$(ST7ASM) -l $< -o $@ -e $<.lst
+
+
+# Remaking configuration
+# ----------------------
+checkconf:
+	@if [ -f $(top_builddir)/devel ]; then\
+	  $(MAKE) -f conf.mk srcdir="$(srcdir)" top_builddir="$(top_builddir)" freshconf;\
+	fi
+
+# End of st7.src/Makefile.in
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/st7.src/regsst7.h sdcc-4.2.0+dfsg/sim/ucsim/st7.src/regsst7.h
--- sdcc-4.0.0+dfsg/sim/ucsim/st7.src/regsst7.h	2016-11-13 16:22:34.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/st7.src/regsst7.h	2020-09-17 06:45:33.000000000 +0000
@@ -1,61 +1,61 @@
-/*
- * Simulator of microcontrollers (regsst7.h)
- *
- * some z80 code base from Karl Bongers karl@turbobit.com
- *
- * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
- * 
- * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
- *
- */
-
-/* This file is part of microcontroller simulator: ucsim.
-
-UCSIM is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2 of the License, or
-(at your option) any later version.
-
-UCSIM is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with UCSIM; see the file COPYING.  If not, write to the Free
-Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-02111-1307, USA. */
-/*@1@*/
-
-#ifndef REGST7_HEADER
-#define REGST7_HEADER
-
-#include "ddconfig.h"
-
-
-struct t_regs
-{
-  u8_t A;
-  u8_t X;
-  u8_t Y;
-  u16_t SP;
-  u8_t CC;
-  u8_t VECTOR;
-};
-
-#define BIT_C	0x01  // carry status(out of bit 7)
-#define BIT_Z	0x02  // zero status, 1=zero, 0=nonzero
-#define BIT_N	0x04  // sign, 1=negative, 0=positive (or zero)
-#define BIT_I	0x08  // interrupt mask, 1=disabled, 0=enabled
-#define BIT_H	0x10  // half carry status(out of bit 3)
-#define BIT_ALL	(BIT_C |BIT_Z |BIT_N |BIT_I |BIT_H)  // all bits
-
-#define BITPOS_C 0    // 1
-#define BITPOS_Z 1    // 2H
-#define BITPOS_N 2    // 4H
-#define BITPOS_I 3    // 8H
-#define BITPOS_H 4    // 10H
-
-#endif
-
-/* End of st7.src/regsst7.h */
+/*
+ * Simulator of microcontrollers (regsst7.h)
+ *
+ * some z80 code base from Karl Bongers karl@turbobit.com
+ *
+ * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef REGST7_HEADER
+#define REGST7_HEADER
+
+#include "ddconfig.h"
+
+
+struct t_regs
+{
+  u8_t A;
+  u8_t X;
+  u8_t Y;
+  u16_t SP;
+  u8_t CC;
+  u8_t VECTOR;
+};
+
+#define BIT_C	0x01  // carry status(out of bit 7)
+#define BIT_Z	0x02  // zero status, 1=zero, 0=nonzero
+#define BIT_N	0x04  // sign, 1=negative, 0=positive (or zero)
+#define BIT_I	0x08  // interrupt mask, 1=disabled, 0=enabled
+#define BIT_H	0x10  // half carry status(out of bit 3)
+#define BIT_ALL	(BIT_C |BIT_Z |BIT_N |BIT_I |BIT_H)  // all bits
+
+#define BITPOS_C 0    // 1
+#define BITPOS_Z 1    // 2H
+#define BITPOS_N 2    // 4H
+#define BITPOS_I 3    // 8H
+#define BITPOS_H 4    // 10H
+
+#endif
+
+/* End of st7.src/regsst7.h */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/st7.src/simst7.cc sdcc-4.2.0+dfsg/sim/ucsim/st7.src/simst7.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/st7.src/simst7.cc	2012-12-23 20:32:49.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/st7.src/simst7.cc	2020-09-17 06:45:33.000000000 +0000
@@ -1,45 +1,45 @@
-/*
- * Simulator of microcontrollers (simst7.cc)
- *
- * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
- * 
- * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
- *
- */
-
-/* This file is part of microcontroller simulator: ucsim.
-
-UCSIM is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2 of the License, or
-(at your option) any later version.
-
-UCSIM is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with UCSIM; see the file COPYING.  If not, write to the Free
-Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-02111-1307, USA. */
-/*@1@*/
-
-
-// local
-#include "simst7cl.h"
-#include "st7cl.h"
-
-
-cl_simst7::cl_simst7(class cl_app *the_app):
-  cl_sim(the_app)
-{}
-
-class cl_uc *
-cl_simst7::mk_controller(void)
-{
-  return(new cl_st7(this));
-}
-
-
-/* End of st7.src/simst7.cc */
+/*
+ * Simulator of microcontrollers (simst7.cc)
+ *
+ * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+
+// local
+#include "simst7cl.h"
+#include "st7cl.h"
+
+
+cl_simst7::cl_simst7(class cl_app *the_app):
+  cl_sim(the_app)
+{}
+
+class cl_uc *
+cl_simst7::mk_controller(void)
+{
+  return(new cl_st7(this));
+}
+
+
+/* End of st7.src/simst7.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/st7.src/simst7cl.h sdcc-4.2.0+dfsg/sim/ucsim/st7.src/simst7cl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/st7.src/simst7cl.h	2012-12-23 20:32:49.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/st7.src/simst7cl.h	2020-09-17 06:45:33.000000000 +0000
@@ -1,45 +1,45 @@
-/*
- * Simulator of microcontrollers (simstm8cl.h)
- *
- * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
- * 
- * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
- *
- */
-
-/* This file is part of microcontroller simulator: ucsim.
-
-UCSIM is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2 of the License, or
-(at your option) any later version.
-
-UCSIM is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with UCSIM; see the file COPYING.  If not, write to the Free
-Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-02111-1307, USA. */
-/*@1@*/
-
-#ifndef SIMST7CL_HEADER
-#define SIMST7CL_HEADER
-
-#include "simcl.h"
-
-
-class cl_simst7: public cl_sim
-{
-public:
-  cl_simst7(class cl_app *the_app);
-
-  virtual class cl_uc *mk_controller(void);
-};
-
-
-#endif
-
-/* End of st7.src/simst7cl.h */
+/*
+ * Simulator of microcontrollers (simstm8cl.h)
+ *
+ * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef SIMST7CL_HEADER
+#define SIMST7CL_HEADER
+
+#include "simcl.h"
+
+
+class cl_simst7: public cl_sim
+{
+public:
+  cl_simst7(class cl_app *the_app);
+
+  virtual class cl_uc *mk_controller(void);
+};
+
+
+#endif
+
+/* End of st7.src/simst7cl.h */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/st7.src/sst7.cc sdcc-4.2.0+dfsg/sim/ucsim/st7.src/sst7.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/st7.src/sst7.cc	2017-01-06 07:36:33.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/st7.src/sst7.cc	2020-09-17 06:45:33.000000000 +0000
@@ -1,56 +1,57 @@
-/*
- * Simulator of microcontrollers (sst7.cc)
- *
- * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
- * 
- * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
- *
- */
-
-/* This file is part of microcontroller simulator: ucsim.
-
-UCSIM is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2 of the License, or
-(at your option) any later version.
-
-UCSIM is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with UCSIM; see the file COPYING.  If not, write to the Free
-Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-02111-1307, USA. */
-/*@1@*/
-  
-// prj
-#include "globals.h"
-
-// sim.src
-#include "appcl.h"
-
-// local
-#include "simst7cl.h"
-
-
-int
-main(int argc, char *argv[])
-{
-  class cl_sim *sim;
-
-  application= new cl_app();
-  application->init(argc, argv);
-  sim= new cl_simst7(application);
-  if (sim->init())
-    sim->state|= SIM_QUIT;
-  application->set_simulator(sim);
-  application->run();
-  application->done();
-  delete application;
-  return(0);
-}
-
-
-/* End of st7.src/sst7.cc */
+/*
+ * Simulator of microcontrollers (sst7.cc)
+ *
+ * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+  
+// prj
+#include "globals.h"
+
+// sim.src
+//#include "appcl.h"
+
+// local
+#include "simst7cl.h"
+
+
+int
+main(int argc, char *argv[])
+{
+  class cl_sim *sim;
+
+  application= new cl_app();
+  application->set_name("sst7");
+  application->init(argc, argv);
+  sim= new cl_simst7(application);
+  if (sim->init())
+    sim->state|= SIM_QUIT;
+  application->set_simulator(sim);
+  application->run();
+  application->done();
+  delete application;
+  return(0);
+}
+
+
+/* End of st7.src/sst7.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/st7.src/st7.cc sdcc-4.2.0+dfsg/sim/ucsim/st7.src/st7.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/st7.src/st7.cc	2019-05-06 09:55:43.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/st7.src/st7.cc	2022-01-18 21:40:45.000000000 +0000
@@ -27,24 +27,25 @@
 02111-1307, USA. */
 /*@1@*/
 
-#include "ddconfig.h"
+//#include "ddconfig.h"
 
-#include  /* for va_list */
+//#include  /* for va_list */
 #include 
 #include 
 #include 
-#include "i_string.h"
+#include 
 
 // prj
-#include "pobjcl.h"
+//#include "pobjcl.h"
 
 // sim
 #include "simcl.h"
+#include "dregcl.h"
 
 // local
 #include "st7cl.h"
 #include "glob.h"
-#include "regsst7.h"
+//#include "regsst7.h"
 #include "st7mac.h"
 
 #define uint32 t_addr
@@ -69,7 +70,7 @@
 {
   cl_uc::init(); /* Memories now exist */
 
-  xtal = 8000000;
+  set_xtal(8000000);
 
   //rom = address_space(MEM_ROM_ID);
 //  ram = mem(MEM_XRAM);
@@ -100,10 +101,10 @@
 }
 
 
-char *
+const char *
 cl_st7::id_string(void)
 {
-  return((char*)"unspecified ST7");
+  return("unspecified ST7");
 }
 
 
@@ -123,11 +124,23 @@
  return(cl_uc::get_mem_size(type));
 }
 */
+
+void
+cl_st7::make_cpu_hw(void)
+{
+  add_hw(cpu= new cl_st7_cpu(this));
+  cpu->init();
+}
+
 void
 cl_st7::mk_hw_elements(void)
 {
   //class cl_base *o;
+  class cl_hw *h;
   cl_uc::mk_hw_elements();
+
+  add_hw(h= new cl_dreg(this, 0, "dreg"));
+  h->init();
 }
 
 void
@@ -142,7 +155,7 @@
   class cl_address_decoder *ad;
   class cl_memory_chip *chip;
 
-  chip= new cl_memory_chip("rom_chip", 0x10000, 8);
+  chip= new cl_chip8("rom_chip", 0x10000, 8);
   chip->init();
   memchips->add(chip);
   ad= new cl_address_decoder(as= address_space("rom"), chip, 0, 0xffff, 0);
@@ -165,18 +178,17 @@
   address_spaces->add(regs8);
   address_spaces->add(regs16);
 
-  class cl_var *v;
-  vars->add(v= new cl_var(cchars("A"), regs8, 0, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("CC"), regs8, 1, ""));
-  v->init();
-  
-  vars->add(v= new cl_var(cchars("X"), regs16, 0, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("Y"), regs16, 1, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("SP"), regs16, 2, ""));
-  v->init();
+  vars->add("A",  regs8, 0, 7, 0, "Accumulator");
+  vars->add("CC", regs8, 1, 7, 0, "Condition Code Register");
+  vars->add("CC_C", regs8, 1, BITPOS_C, BITPOS_C, "Carry");
+  vars->add("CC_Z", regs8, 1, BITPOS_Z, BITPOS_Z, "Zero");
+  vars->add("CC_N", regs8, 1, BITPOS_N, BITPOS_N, "Negative");
+  vars->add("CC_I", regs8, 1, BITPOS_I, BITPOS_I, "Interrupt Mask");
+  vars->add("CC_H", regs8, 1, BITPOS_H, BITPOS_H, "Half Carry");
+
+  vars->add("X",  regs16, 0, 15, 0, "X Index Register");
+  vars->add("Y",  regs16, 1, 15, 0, "Y Index Register");
+  vars->add("SP", regs16, 2, 15, 0, "Stack Pointer");
 }
 
 
@@ -331,137 +343,96 @@
 }
 
 char *
-cl_st7::disass(t_addr addr, const char *sep)
+cl_st7::disass(t_addr addr)
 {
-  char work[256], temp[20];
+  chars work, temp;
   const char *b;
-  char *buf, *p, *t;
+  t_addr operand;
   int len = 0;
   int immed_offset = 0;
+  bool first= true;
 
-
-  p= work;
+  work= "";
 
   b = get_disasm_info(addr, &len, NULL, &immed_offset, NULL);
 
-  if (b == NULL) {
-    buf= (char*)malloc(30);
-    strcpy(buf, "UNKNOWN/INVALID");
-    return(buf);
-  }
+  if (b == NULL)
+    {
+      return strdup("UNKNOWN/INVALID");
+    }
 
   while (*b)
     {
+      if ((*b == ' ') && first)
+	{
+	  first= false;
+	  while (work.len() < 6) work.append(' ');
+	}
       if (*b == '%')
         {
           b++;
           switch (*(b++))
             {
-            //case 's': // s    signed byte immediate
-            //  sprintf(temp, "#%d", (char)rom->get(addr+immed_offset));
-            //  ++immed_offset;
-            //  break;
-            //case 'e': // e    extended 24bit immediate operand
-            //  sprintf(temp, "#0x%06lx",
-            //     (ulong)((rom->get(addr+immed_offset)<<16) |
-            //            (rom->get(addr+immed_offset+1)<<8) |
-            //            (rom->get(addr+immed_offset+2))) );
-            //  ++immed_offset;
-            //  ++immed_offset;
-            //  ++immed_offset;
-            //  break;
-            //case 'w': // w    word immediate operand
-            //  sprintf(temp, "#0x%04x",
-            //     (uint)((rom->get(addr+immed_offset)<<8) |
-            //            (rom->get(addr+immed_offset+1))) );
-            //  ++immed_offset;
-            //  ++immed_offset;
-            //  break;
             case 'b': // b    byte immediate operand
-              sprintf(temp, "#0x%02x", (uint)rom->get(addr+immed_offset));
+              temp.format("#0x%02x", rom->get(addr+immed_offset));
               ++immed_offset;
               break;
             case 'd': // d    short direct addressing
-              sprintf(temp, "$0x%02x", (uint)rom->get(addr+immed_offset));
+              operand= rom->get(addr+immed_offset);
+              temp.format("$0x%02x", operand);
+              addr_name(operand, rom, &temp);
               ++immed_offset;
               break;
             case 'x': // x    long direct
-              sprintf(temp, "$0x%04x",
-                 (uint)((rom->get(addr+immed_offset)<<8) |
-                        (rom->get(addr+immed_offset+1))) );
+              operand= (rom->get(addr+immed_offset)<<8) |
+                       (rom->get(addr+immed_offset+1));
+              temp.format("$0x%04x", operand);
+              addr_name(operand, rom, &temp);
               ++immed_offset;
               ++immed_offset;
               break;
-            //case '3': // 3    24bit index offset
-            //  sprintf(temp, "0x%06lx",
-            //     (ulong)((rom->get(addr+immed_offset)<<16) |
-            //            (rom->get(addr+immed_offset+1)<<8) |
-            //            (rom->get(addr+immed_offset+2))) );
-            //  ++immed_offset;
-            //  ++immed_offset;
-            //  ++immed_offset;
-            // break;
             case '2': // 2    word index offset
-              sprintf(temp, "0x%04x",
-                 (uint)((rom->get(addr+immed_offset)<<8) |
-                        (rom->get(addr+immed_offset+1))) );
+              // Assumption: the word offset address is the address of a
+              // fixed table and the index register selects an entry.
+              operand= (rom->get(addr+immed_offset)<<8) |
+                       (rom->get(addr+immed_offset+1));
+              temp.format("0x%04x", operand);
+              addr_name(operand, rom, &temp);
               ++immed_offset;
               ++immed_offset;
               break;
             case '1': // b    byte index offset
-              sprintf(temp, "0x%02x", (uint)rom->get(addr+immed_offset));
+              // Assumption: the index register points to a struct/record
+              // and the byte offset selects an entry.
+              temp.format("0x%02x", rom->get(addr+immed_offset));
               ++immed_offset;
               break;
-            case 'p': // b    byte index offset
+            case 'p': // p    pc relative
 	      {
-		int i= (int)(addr+immed_offset+1
-			     +(char)rom->get(addr+immed_offset)); 
-		sprintf(temp, "0x%04x", i&0xffff);
+		operand= ((addr+immed_offset+1 + (i8_t)rom->get(addr+immed_offset))) & 0xffff;
+		temp.format("0x%04x", operand);
+		addr_name(operand, rom, &temp);
 		++immed_offset;
 		break;
 	      }
             default:
-              strcpy(temp, "?");
+              temp= "?";
               break;
             }
-          t= temp;
-          while (*t)
-            *(p++)= *(t++);
+	  work+= temp;
         }
       else
-        *(p++)= *(b++);
+        work+= *(b++);
     }
-  *p= '\0';
 
-  p= strchr(work, ' ');
-  if (!p)
-    {
-      buf= strdup(work);
-      return(buf);
-    }
-  if (sep == NULL)
-    buf= (char *)malloc(6+strlen(p)+1);
-  else
-    buf= (char *)malloc((p-work)+strlen(sep)+strlen(p)+1);
-  for (p= work, t= buf; *p != ' '; p++, t++)
-    *t= *p;
-  p++;
-  *t= '\0';
-  if (sep == NULL)
-    {
-      while (strlen(buf) < 6)
-        strcat(buf, " ");
-    }
-  else
-    strcat(buf, sep);
-  strcat(buf, p);
-  return(buf);
+  return strdup(work.c_str());
 }
 
 
 void
 cl_st7::print_regs(class cl_console_base *con)
 {
+  con->dd_color("answer");
   con->dd_printf("---HINZC  Flags= 0x%02x %3d %c  ",
                  regs.CC, regs.CC, isprint(regs.CC)?regs.CC:'.');
   con->dd_printf("A= 0x%02x %3d %c\n",
@@ -476,10 +447,10 @@
                  regs.X, regs.X, isprint(regs.X)?regs.X:'.');
   con->dd_printf("Y= 0x%02x %3d %c\n",
                  regs.Y, regs.Y, isprint(regs.Y)?regs.Y:'.');
-  con->dd_printf("SP= 0x%04x [SP+1]= %02x %3d %c\n",
+  con->dd_printf("SP= 0x%04x [SP+1]= %02x %3d %c",
                  regs.SP, ram->get(regs.SP+1), ram->get(regs.SP+1),
                  isprint(ram->get(regs.SP+1))?ram->get(regs.SP+1):'.');
-
+  con->dd_printf("  Limit= 0x%04x\n", AU(sp_limit));
   print_disass(PC, con);
 }
 
@@ -1203,6 +1174,26 @@
   return(resINV_INST);
 }
 
+
+void
+cl_st7::stack_check_overflow(class cl_stack_op *op)
+{
+  if (op)
+    {
+      if (op->get_op() & stack_write_operation)
+	{
+	  t_addr a= op->get_after();
+	  if (a < sp_limit)
+	    {
+	      class cl_error_stack_overflow *e=
+		new cl_error_stack_overflow(op);
+	      e->init();
+	      error(e);
+	    }
+	}
+    }
+}
+
 t_mem
 cl_st7::get_1(t_addr addr)
 {
@@ -1226,4 +1217,54 @@
     (ram->read(addr+2));
 }
 
+
+cl_st7_cpu::cl_st7_cpu(class cl_uc *auc):
+  cl_hw(auc, HW_CPU, 0, "cpu")
+{
+}
+
+int
+cl_st7_cpu::init(void)
+{
+  cl_hw::init();
+
+  cl_var *v;
+  uc->vars->add(v= new cl_var("sp_limit", cfg, st7cpu_sp_limit,
+			      cfg_help(st7cpu_sp_limit)));
+  v->init();
+
+  return 0;
+}
+
+const char *
+cl_st7_cpu::cfg_help(t_addr addr)
+{
+  switch (addr)
+    {
+    case st7cpu_sp_limit:
+      return "Stack overflows when SP is below this limit";
+    }
+  return "Not used";
+}
+
+t_mem
+cl_st7_cpu::conf_op(cl_memory_cell *cell, t_addr addr, t_mem *val)
+{
+  class cl_st7 *u= (class cl_st7 *)uc;
+  if (val)
+    cell->set(*val);
+  switch ((enum st7cpu_confs)addr)
+    {
+    case st7cpu_sp_limit:
+      if (val)
+	u->sp_limit= *val & 0xffff;
+      else
+	cell->set(u->sp_limit);
+      break;
+    case st7cpu_nuof: break;
+    }
+  return cell->get();
+}
+
+
 /* End of st7.src/st7.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/st7.src/st7cl.h sdcc-4.2.0+dfsg/sim/ucsim/st7.src/st7cl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/st7.src/st7cl.h	2016-12-13 10:53:09.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/st7.src/st7cl.h	2021-10-29 17:39:15.000000000 +0000
@@ -44,12 +44,14 @@
   class cl_memory *rom;
   class cl_address_space *regs8, *regs16;
   struct t_regs regs;
+  t_addr sp_limit;
 public:
   cl_st7(class cl_sim *asim);
   virtual int init(void);
-  virtual char *id_string(void);
+  virtual const char *id_string(void);
 
   //virtual t_addr get_mem_size(enum mem_class type);
+  virtual void make_cpu_hw(void);
   virtual void mk_hw_elements(void);
   virtual void make_memories(void);
 
@@ -57,11 +59,13 @@
   virtual int inst_length(t_addr addr);
   virtual int inst_branch(t_addr addr);
   virtual int longest_inst(void);
-  virtual char *disass(t_addr addr, const char *sep);
+  virtual char *disass(t_addr addr);
   virtual void print_regs(class cl_console_base *con);
 
   virtual int exec_inst(void);
 
+  virtual void stack_check_overflow(class cl_stack_op *op);
+
   virtual const char *get_disasm_info(t_addr addr,
                                       int *ret_len,
                                       int *ret_branch,
@@ -77,6 +81,23 @@
 };
 
 
+enum st7cpu_confs
+  {
+   st7cpu_sp_limit	= 0,
+   st7cpu_nuof		= 1
+  };
+
+class cl_st7_cpu: public cl_hw
+{
+public:
+  cl_st7_cpu(class cl_uc *auc);
+  virtual int init(void);
+  virtual unsigned int cfg_size(void) { return st7cpu_nuof; }
+  virtual const char *cfg_help(t_addr addr);
+
+  virtual t_mem conf_op(cl_memory_cell *cell, t_addr addr, t_mem *val);
+};
+
 #endif
 
 /* End of st7.src/st7cl.h */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/st7.src/st7mac.h sdcc-4.2.0+dfsg/sim/ucsim/st7.src/st7mac.h
--- sdcc-4.0.0+dfsg/sim/ucsim/st7.src/st7mac.h	2017-03-02 10:01:56.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/st7.src/st7mac.h	2020-09-17 06:45:33.000000000 +0000
@@ -1,42 +1,58 @@
-/*
- * Simulator of microcontrollers (st7mac.h)
- *
- * some z80 code base from Karl Bongers karl@turbobit.com
- *
- * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
- * 
- * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
- *
- */
-
-// shift positions
-#define BITPOS_C 0  // 1
-#define BITPOS_Z 1  // 2H
-#define BITPOS_N 2  // 4H
-#define BITPOS_I 3  // 8H
-#define BITPOS_H 4  // 10H
-
-#define store2(addr, val) { ram->write((t_addr) (addr), (val >> 8) & 0xff); ram->write((t_addr) (addr+1), val & 0xff); vc.wr+= 2; }
-#define store1(addr, val) { ram->write((t_addr) (addr), val); vc.wr++; }
-#define get1(addr) get_1(addr)
-//ram->get((t_addr) (addr))
-#define get2(addr) get_2(addr)
-//((ram->get((t_addr) (addr)) << 8) | ram->get((t_addr) (addr+1)) )
-#define get3(addr) get_3(addr)
-//((ram->get((t_addr) (addr)) << 16) | (ram->get((t_addr) (addr+1)) << 8) |ram->get((t_addr) (addr+2)) )
-#define fetch2() ((fetch() << 8) | fetch() )
-#define fetch1() fetch()
-#define push2(val) {store2(regs.SP-1,(val)); regs.SP-=2; }
-#define push1(val) {store1(regs.SP,(val)); regs.SP-=1; }
-#define pop2(var) {var=get2(regs.SP+1); regs.SP+=2;}
-#define pop1(var) {var=get1(regs.SP+1); regs.SP+=1;}
-
-
-#define FLAG_SET(f) {regs.CC |= f;}
-#define FLAG_CLEAR(f) {regs.CC &= ~(f);}
-#define FLAG_ASSIGN(f,c) {regs.CC = (c) ? regs.CC | (f) : regs.CC & ~(f);}
-#define EA_IMM(c) ((((c) >> 4) & 0xf)==0xa)
-#define OPERAND(code,prefix) (EA_IMM(code) ? fetch() : get1(fetchea(code,prefix)))
-
-
-
+/*
+ * Simulator of microcontrollers (st7mac.h)
+ *
+ * some z80 code base from Karl Bongers karl@turbobit.com
+ *
+ * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+// shift positions
+#define BITPOS_C 0  // 1
+#define BITPOS_Z 1  // 2H
+#define BITPOS_N 2  // 4H
+#define BITPOS_I 3  // 8H
+#define BITPOS_H 4  // 10H
+
+#define store2(addr, val) { ram->write((t_addr) (addr), (val >> 8) & 0xff); ram->write((t_addr) (addr+1), val & 0xff); vc.wr+= 2; }
+#define store1(addr, val) { ram->write((t_addr) (addr), val); vc.wr++; }
+#define get1(addr) get_1(addr)
+//ram->get((t_addr) (addr))
+#define get2(addr) get_2(addr)
+//((ram->get((t_addr) (addr)) << 8) | ram->get((t_addr) (addr+1)) )
+#define get3(addr) get_3(addr)
+//((ram->get((t_addr) (addr)) << 16) | (ram->get((t_addr) (addr+1)) << 8) |ram->get((t_addr) (addr+2)) )
+#define fetch2() ((fetch() << 8) | fetch() )
+#define fetch1() fetch()
+#define push2(val) {					\
+    t_addr sp_before= regs.SP;				\
+    store2(regs.SP-1,(val));				\
+    regs.SP-=2;						\
+    class cl_stack_op *so=				\
+      new cl_stack_push(instPC,val,sp_before,regs.SP);	\
+    so->init();						\
+    stack_write(so);					\
+  }
+#define push1(val) {					\
+    t_addr sp_before= regs.SP;				\
+    store1(regs.SP,(val));				\
+    regs.SP-=1;						\
+    class cl_stack_op *so=				\
+      new cl_stack_push(instPC,val,sp_before,regs.SP);	\
+    so->init();						\
+    stack_write(so);					\
+  }
+#define pop2(var) {var=get2(regs.SP+1); regs.SP+=2;}
+#define pop1(var) {var=get1(regs.SP+1); regs.SP+=1;}
+
+
+#define FLAG_SET(f) {regs.CC |= f;}
+#define FLAG_CLEAR(f) {regs.CC &= ~(f);}
+#define FLAG_ASSIGN(f,c) {regs.CC = (c) ? regs.CC | (f) : regs.CC & ~(f);}
+#define EA_IMM(c) ((((c) >> 4) & 0xf)==0xa)
+#define OPERAND(code,prefix) (EA_IMM(code) ? fetch() : get1(fetchea(code,prefix)))
+
+
+
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/st7.src/test/clean.mk sdcc-4.2.0+dfsg/sim/ucsim/st7.src/test/clean.mk
--- sdcc-4.0.0+dfsg/sim/ucsim/st7.src/test/clean.mk	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/st7.src/test/clean.mk	2021-04-01 17:52:48.000000000 +0000
@@ -0,0 +1,5 @@
+clean:
+
+distclean:
+	rm -f Makefile
+	find . -type d -name out -exec rm -rf {} \;
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/st7.src/test/config/baseline/ST7 sdcc-4.2.0+dfsg/sim/ucsim/st7.src/test/config/baseline/ST7
--- sdcc-4.0.0+dfsg/sim/ucsim/st7.src/test/config/baseline/ST7	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/st7.src/test/config/baseline/ST7	2022-02-08 21:21:05.000000000 +0000
@@ -0,0 +1,25 @@
+uCsim, Copyright (C)  Daniel Drotos.
+uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+This is free software, and you are welcome to redistribute it
+under certain conditions; type `show c' for details.
+Type of microcontroller: unspecified ST7
+Controller has 4 hardware element(s).
+   on cpu[0]
+   on simif[0]
+  off vcd[0]
+   on dreg[0]
+---HINZC  Flags= 0x00   0 .  A= 0x00   0 .
+---00000  X= 0x00   0     .  Y= 0x00   0 .
+SP= 0x017f [SP+1]= 02   2 .  Limit= 0x0000
+0x0000  ? 08 70 d4       btjt   $0x70,#4,0xffd7[0K
+Memory chips:
+  0x000000-0x0000ff      256 variable_storage (32,%08x,0x%02lx)
+  0x000000-0x00ffff    65536 rom_chip (8,%02x,0x%04lx)
+Address spaces:
+  0x000000-0x0000ff      256 variables (32,%08x,0x%02lx)
+  0x000000-0x00ffff    65536 rom (8,%02x,0x%04lx)
+  0x000000-0x000001        2 regs8 (8,%02x,0x%01lx)
+  0x000000-0x000002        3 regs16 (16,%04x,0x%01lx)
+Address decoders:
+  variables 0x00 0xff -> variable_storage 0x00 activated
+  rom 0x0000 0xffff -> rom_chip 0x0000 activated
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/st7.src/test/config/Makefile sdcc-4.2.0+dfsg/sim/ucsim/st7.src/test/config/Makefile
--- sdcc-4.0.0+dfsg/sim/ucsim/st7.src/test/config/Makefile	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/st7.src/test/config/Makefile	2021-03-21 12:01:19.000000000 +0000
@@ -0,0 +1,8 @@
+OUTPUTS = ST7
+
+
+$(OUTPUTS):
+	$(call run-sim, -e 'conf; info reg; info mem')
+
+
+include test-lib.mk
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/st7.src/test/Makefile.in sdcc-4.2.0+dfsg/sim/ucsim/st7.src/test/Makefile.in
--- sdcc-4.0.0+dfsg/sim/ucsim/st7.src/test/Makefile.in	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/st7.src/test/Makefile.in	2021-03-28 10:28:14.000000000 +0000
@@ -0,0 +1,9 @@
+# @configure_input@
+
+srcdir           = @abs_srcdir@
+
+abs_top_builddir = @abs_top_builddir@
+abs_top_srcdir   = @abs_top_srcdir@
+
+
+include $(abs_top_srcdir)/test-target.mk
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/st7.src/test/symdis/baseline/stdout sdcc-4.2.0+dfsg/sim/ucsim/st7.src/test/symdis/baseline/stdout
--- sdcc-4.0.0+dfsg/sim/ucsim/st7.src/test/symdis/baseline/stdout	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/st7.src/test/symdis/baseline/stdout	2022-01-24 11:09:43.000000000 +0000
@@ -0,0 +1,21 @@
+uCsim [ELIDED], Copyright (C) [ELIDED] Daniel Drotos.
+uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+This is free software, and you are welcome to redistribute it
+under certain conditions; type `show c' for details.
+var init rom[0x0000]
+var main rom[0x0002]
+var forever rom[0x0008]
+dc 0x0000 0x0008 
+
+0x0000    :
+0x0000    bc 02          jp     $0x02 [0K
+
+0x0002    :
+0x0002  ? a6 00          ld     A,#0x00[0K
+0x0004  ? 27 02          jreq   0x0008 [0K
+0x0006  ? a6 01          ld     A,#0x01[0K
+
+0x0008    :
+0x0008  ? 20 fe          jra    0x0008 [0K
+Loading from [ELIDED]
+10 words read from [ELIDED]
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/st7.src/test/symdis/Makefile sdcc-4.2.0+dfsg/sim/ucsim/st7.src/test/symdis/Makefile
--- sdcc-4.0.0+dfsg/sim/ucsim/st7.src/test/symdis/Makefile	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/st7.src/test/symdis/Makefile	2021-05-07 16:21:16.000000000 +0000
@@ -0,0 +1,15 @@
+OUTPUTS = stdout
+
+
+# Ignore changes in white space. The field widths for labels
+# depends on the length of the longest label. This will be
+# different for different simulators and should not be assumed
+# to be constant for any given simulator.
+DIFF_OPTS += -b
+
+
+stdout:	test.ihx test.cmd
+	$(call run-sim)
+
+
+include test-lib.mk
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/st7.src/test/symdis/test.asm sdcc-4.2.0+dfsg/sim/ucsim/st7.src/test/symdis/test.asm
--- sdcc-4.0.0+dfsg/sim/ucsim/st7.src/test/symdis/test.asm	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/st7.src/test/symdis/test.asm	2021-05-07 16:21:16.000000000 +0000
@@ -0,0 +1,9 @@
+	cpu ST7
+
+init:	jp main
+
+main:	ld a,#0
+	jreq forever
+	ld a,#1
+forever:
+	jra forever
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/st7.src/test/symdis/test.cmd sdcc-4.2.0+dfsg/sim/ucsim/st7.src/test/symdis/test.cmd
--- sdcc-4.0.0+dfsg/sim/ucsim/st7.src/test/symdis/test.cmd	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/st7.src/test/symdis/test.cmd	2021-05-07 16:21:16.000000000 +0000
@@ -0,0 +1,4 @@
+var init rom[0x0000]
+var main rom[0x0002]
+var forever rom[0x0008]
+dc 0x0000 0x0008 
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/st7.src/test/symdis/test.ihx sdcc-4.2.0+dfsg/sim/ucsim/st7.src/test/symdis/test.ihx
--- sdcc-4.0.0+dfsg/sim/ucsim/st7.src/test/symdis/test.ihx	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/st7.src/test/symdis/test.ihx	2021-05-07 16:21:16.000000000 +0000
@@ -0,0 +1,2 @@
+:0A000000BC02A6002702A60120FEA4
+:00000001FF
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/st7.src/test/test-conf.mk sdcc-4.2.0+dfsg/sim/ucsim/st7.src/test/test-conf.mk
--- sdcc-4.0.0+dfsg/sim/ucsim/st7.src/test/test-conf.mk	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/st7.src/test/test-conf.mk	2021-05-07 16:21:16.000000000 +0000
@@ -0,0 +1,10 @@
+# For asl see: http://john.ccac.rwth-aachen.de:8000/as/
+
+AS = asl
+ASFLAGS = -L -h -U
+
+%p:	%.asm
+	$(AS) $(ASFLAGS) -olist '$*.lst' -o '$@' '$<'
+
+%.ihx:	%.p
+	p2hex -F Intel '$<' '$@'
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/bl.cc sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/bl.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/bl.cc	2017-02-21 09:48:05.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/bl.cc	2021-04-26 19:46:10.000000000 +0000
@@ -1,7 +1,7 @@
 #include "stypes.h"
 #include "bl.h"
 /* http://srecord.sourceforge.net/ */
-t_mem bl_l15x46[] =
+u8_t bl_l15x46[] =
 {
 0x9B, 0xC6, 0x80, 0x00, 0xA1, 0x82, 0x27, 0x06, 0xA1, 0xAC, 0x27, 0x02,
 0x20, 0x0C, 0xCE, 0x48, 0x0B, 0xA3, 0x55, 0xAA, 0x27, 0x04, 0xAC, 0x00,
@@ -185,7 +185,7 @@
 #define BL_L15X46_FINISH      0x00006800
 #define BL_L15X46_LENGTH      0x00000800
 /* http://srecord.sourceforge.net/ */
-t_mem bl_s105[] =
+u8_t bl_s105[] =
 {
 0x9B, 0xC6, 0x80, 0x00, 0xA1, 0x82, 0x27, 0x06, 0xA1, 0xAC, 0x27, 0x02,
 0x20, 0x0A, 0xCE, 0x48, 0x7E, 0xA3, 0x55, 0xAA, 0x27, 0x02, 0x20, 0x07,
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/bl.h sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/bl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/bl.h	2017-02-21 09:48:05.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/bl.h	2021-04-26 19:46:10.000000000 +0000
@@ -5,7 +5,7 @@
 extern unsigned long bl_l15x46_start;
 extern unsigned long bl_l15x46_finish;
 extern unsigned long bl_l15x46_length;
-extern t_mem bl_l15x46[];
+extern u8_t bl_l15x46[];
 
 #endif /* BL_L15X46_H */
 #ifndef BL_S105_H
@@ -15,6 +15,6 @@
 extern unsigned long bl_s105_start;
 extern unsigned long bl_s105_finish;
 extern unsigned long bl_s105_length;
-extern t_mem bl_s105[];
+extern u8_t bl_s105[];
 
 #endif /* BL_S105_H */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/bl_head.cc sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/bl_head.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/bl_head.cc	2017-02-21 09:48:05.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/bl_head.cc	2020-03-27 20:18:53.000000000 +0000
@@ -1,2 +1,2 @@
-#include "stypes.h"
+//#include "stypes.h"
 #include "bl.h"
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/bl_l15x46.h sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/bl_l15x46.h
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/bl_l15x46.h	2017-02-21 09:48:05.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/bl_l15x46.h	2021-04-26 19:46:10.000000000 +0000
@@ -5,6 +5,6 @@
 extern unsigned long bl_l15x46_start;
 extern unsigned long bl_l15x46_finish;
 extern unsigned long bl_l15x46_length;
-extern unsigned char bl_l15x46[];
+extern u8_t bl_l15x46[];
 
 #endif /* BL_L15X46_H */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/bl_s105.cc sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/bl_s105.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/bl_s105.cc	2017-02-21 09:48:05.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/bl_s105.cc	2021-04-26 19:46:10.000000000 +0000
@@ -1,5 +1,5 @@
 /* http://srecord.sourceforge.net/ */
-unsigned char bl_s105[] =
+u8_t bl_s105[] =
 {
 0x9B, 0xC6, 0x80, 0x00, 0xA1, 0x82, 0x27, 0x06, 0xA1, 0xAC, 0x27, 0x02,
 0x20, 0x0A, 0xCE, 0x48, 0x7E, 0xA3, 0x55, 0xAA, 0x27, 0x02, 0x20, 0x07,
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/bl_s105.h sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/bl_s105.h
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/bl_s105.h	2017-02-21 09:48:05.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/bl_s105.h	2021-04-26 19:46:10.000000000 +0000
@@ -5,6 +5,6 @@
 extern unsigned long bl_s105_start;
 extern unsigned long bl_s105_finish;
 extern unsigned long bl_s105_length;
-extern unsigned char bl_s105[];
+extern u8_t bl_s105[];
 
 #endif /* BL_S105_H */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/clean.mk sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/clean.mk
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/clean.mk	2017-02-24 11:48:49.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/clean.mk	2021-09-19 19:38:05.000000000 +0000
@@ -3,7 +3,9 @@
 clean:
 	rm -f *core *[%~] *.[oa]
 	rm -f .[a-z]*~
-	rm -f sstm8$(EXEEXT)
+	rm -f sstm8 sstm8.exe
+	rm -f ucsim_stm8 ucsim_stm8.exe
+	$(MAKE) -C test -f clean.mk clean
 
 
 # Deleting all files created by configuring or building the program
@@ -11,6 +13,7 @@
 distclean: clean
 	rm -f config.cache config.log config.status
 	rm -f Makefile *.dep
+	$(MAKE) -C test -f clean.mk distclean
 
 
 # Like clean but some files may still exist
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/clk.cc sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/clk.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/clk.cc	2017-03-12 13:28:55.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/clk.cc	2022-01-20 15:57:08.000000000 +0000
@@ -25,19 +25,46 @@
 02111-1307, USA. */
 /*@1@*/
 
+#include "utils.h"
+
 #include "stm8cl.h"
 
 #include "clkcl.h"
 
 
+// FIXME: there needs to be some way to set the value of a cell ignoring
+// the CELL_READ_ONLY flag.
+static void
+write_ro(class cl_memory_cell *cell, t_mem val)
+{
+  cell->set_flag(CELL_READ_ONLY, false);
+  cell->write(val);
+  cell->set_flag(CELL_READ_ONLY, true);
+}
+
+
 cl_clk::cl_clk(class cl_uc *auc):
        cl_hw(auc, HW_CLOCK, 0, "clk")
 {
+  f_LSI = 0;
+  f_LSE = 0;
+
+  CLK_SOURCE_HSI = 0;
+  CLK_SOURCE_LSI = 0;
+  CLK_SOURCE_HSE = 0;
+  CLK_SOURCE_LSE = 0;
+
   base= 0x50C0;
+
+  cmsr= NULL;
+  swr= NULL;
+  swcr= NULL;
   ckdivr= NULL;
   pckenr1= NULL;
   pckenr2= NULL;
   pckenr3= NULL;
+
+  cpudiv = false;
 }
 
 int
@@ -45,6 +72,8 @@
 {
   cl_hw::init();
 
+  uc->set_xtal(f_OSC = f_HSI);
+
   make_partner(HW_TIMER, 1);
   make_partner(HW_TIMER, 2);
   make_partner(HW_TIMER, 3);
@@ -60,143 +89,439 @@
   return 0;
 }
 
+int
+cl_clk::clock_per_cycle(void)
+{
+  return 1;
+}
+
+int
+cl_clk::xtal_per_clock(t_mem ckdivr_val)
+{
+  return (1 << (ckdivr_val & 0x03));
+}
+
+void
+cl_clk::set_osc(t_mem osc)
+{
+  if (osc == CLK_SOURCE_HSI)
+    {
+      if (ickr)
+        ickr->write((ickr->get() | CLK_ICKR_HSIRDY));
+      write_ro(cmsr, CLK_SOURCE_HSI);
+      f_OSC = f_HSI;
+    }
+  else if (osc == CLK_SOURCE_HSE)
+    {
+      if (eckr)
+        eckr->write((eckr->get() | CLK_ECKR_HSERDY));
+      write_ro(cmsr, CLK_SOURCE_HSE);
+      f_OSC= uc->xtal_option->get_value(0.0);
+    }
+  else if (osc == CLK_SOURCE_LSI)
+    {
+      // FIXME: if LSI_EN option bit is set after SWEN is set and SWBSY is clear
+      // should it trigger a clock change?
+      class cl_stm8 *stm8 = static_cast(uc);
+      if ((stm8->option_chip->get(0x05) & 0x08) && (~stm8->option_chip->get(0x06) & 0x08))
+        {
+          if (ickr)
+            ickr->write((ickr->get() | CLK_ICKR_LSIRDY));
+          write_ro(cmsr, CLK_SOURCE_LSI);
+          f_OSC = f_LSI;
+        }
+    }
+  else if (osc == CLK_SOURCE_LSE)
+    {
+      if (eckr)
+        eckr->write((eckr->get() | CLK_ECKR_LSERDY));
+      write_ro(cmsr, CLK_SOURCE_LSE);
+      f_OSC = f_LSE;
+    }
+
+  uc->set_xtal((ckdivr ? f_OSC / xtal_per_clock(ckdivr->get()) : f_OSC));
+}
+
 void
 cl_clk::write(class cl_memory_cell *cell, t_mem *val)
 {
-  cl_clk_event e;
-  hw_event ev;
-  
-  if ((cell == pckenr1) ||
+  if (ckdivr && cell == ckdivr)
+    {
+      // FIXME: this changes xtal before we tick. But what length should
+      // the current tick be? Do we need to fudge the tickers here?
+      uc->set_xtal(f_OSC / xtal_per_clock(*val));
+    }
+  else if (swr && cell == swr)
+    {
+      swcr->write(swcr->get() | CLK_SWCR_SWBSY);
+
+      // If the new clock was not already active we should now wait for the oscillator
+      // to stabilize (<1μs for HSI) then clear SWBSY (and do the change if SWEN is set)
+      // however it is rare that oscillators are stopped and restarted (and not possible
+      // for HSI according to the erratas) so we assume it is ready.
+      // N.B. Manually clearing SWBSY cancels a pending oscillator change so this should
+      // ONLY happen if SWBSY is still set. The check is redundant here but would be
+      // required if we add a stabilization delay.
+      t_mem v = swcr->get();
+      if (v & CLK_SWCR_SWBSY)
+        {
+          if (v & CLK_SWCR_SWEN)
+            set_osc(*val);
+          swcr->write(v & ~CLK_SWCR_SWBSY);
+        }
+    }
+  else if (swcr && cell == swcr)
+    {
+      // Setting SWEN when SWBSY is clear triggers a clock change
+      if ((swcr->get() & (CLK_SWCR_SWEN|CLK_SWCR_SWBSY)) == 0x00 && (*val & (CLK_SWCR_SWEN|CLK_SWCR_SWBSY)) == CLK_SWCR_SWEN)
+        set_osc(swr->get());
+    }
+  else if ((cell == pckenr1) ||
       (cell == pckenr2) ||
       (cell == pckenr3))
     {
-      cell->set(*val);
+      cl_clk_event e;
+      hw_event ev;
 
       e.set(HW_TIMER, 1);
-      ev= tim(e.id)?EV_CLK_ON:EV_CLK_OFF;
+      ev= tim(e.id, val)?EV_CLK_ON:EV_CLK_OFF;
       inform_partners(ev, &e);
 
       e.id= 2;
-      ev= tim(e.id)?EV_CLK_ON:EV_CLK_OFF;
+      ev= tim(e.id, val)?EV_CLK_ON:EV_CLK_OFF;
       inform_partners(ev, &e);
 
       e.id= 3;
-      ev= tim(e.id)?EV_CLK_ON:EV_CLK_OFF;
+      ev= tim(e.id, val)?EV_CLK_ON:EV_CLK_OFF;
       inform_partners(ev, &e);
 
       e.id= 4;
-      ev= tim(e.id)?EV_CLK_ON:EV_CLK_OFF;
+      ev= tim(e.id, val)?EV_CLK_ON:EV_CLK_OFF;
       inform_partners(ev, &e);
 
       e.id= 5;
-      ev= tim(e.id)?EV_CLK_ON:EV_CLK_OFF;
+      ev= tim(e.id, val)?EV_CLK_ON:EV_CLK_OFF;
       inform_partners(ev, &e);
 
       e.id= 6;
-      ev= tim(e.id)?EV_CLK_ON:EV_CLK_OFF;
+      ev= tim(e.id, val)?EV_CLK_ON:EV_CLK_OFF;
       inform_partners(ev, &e);
 
       e.set(HW_UART, 1);
-      ev= usart(e.id)?EV_CLK_ON:EV_CLK_OFF;
+      ev= usart(e.id, val)?EV_CLK_ON:EV_CLK_OFF;
       inform_partners(ev, &e);
 
       e.id= 2;
-      ev= usart(e.id)?EV_CLK_ON:EV_CLK_OFF;
+      ev= usart(e.id, val)?EV_CLK_ON:EV_CLK_OFF;
       inform_partners(ev, &e);
 
       e.id= 3;
-      ev= usart(e.id)?EV_CLK_ON:EV_CLK_OFF;
+      ev= usart(e.id, val)?EV_CLK_ON:EV_CLK_OFF;
       inform_partners(ev, &e);
 
       e.id= 4;
-      ev= usart(e.id)?EV_CLK_ON:EV_CLK_OFF;
+      ev= usart(e.id, val)?EV_CLK_ON:EV_CLK_OFF;
       inform_partners(ev, &e);
     }
 }
 
+void
+cl_clk::print_info(class cl_console_base *con)
+{
+  con->dd_printf("%s[%d] at 0x%06x\n", id_string, id, base);
+
+  if (cmsr)
+    {
+      t_mem curr = cmsr->get();
+
+      if (curr == CLK_SOURCE_HSI)
+          con->dd_printf("  HSI");
+      else if (curr == CLK_SOURCE_HSE)
+          con->dd_printf("  HSE");
+      else if (curr == CLK_SOURCE_LSI)
+          con->dd_printf("  LSI");
+      else if (curr == CLK_SOURCE_LSE)
+          con->dd_printf("  LSE");
+
+      t_mem want = swr->get();
+      if (want != curr)
+        {
+          if (want == CLK_SOURCE_HSI)
+            con->dd_printf(" (pending change to HSI)");
+	  else if (want == CLK_SOURCE_HSE)
+            con->dd_printf(" (pending change to HSE)");
+	  else if (want == CLK_SOURCE_LSI)
+            con->dd_printf(" (pending change to LSI)");
+	  else if (want == CLK_SOURCE_LSE)
+            con->dd_printf(" (pending change to LSE)");
+        }
+
+      con->dd_printf("\n");
+    }
+
+  con->dd_printf("  f_OSC:    %.0f Hz\n", f_OSC);
+
+  if (ckdivr)
+    {
+      con->dd_printf("  HSIDIV:   %d\n", xtal_per_clock(ckdivr->get()));
+      con->dd_printf("  f_MASTER: %.0f Hz\n", uc->get_xtal());
+      if (cpudiv)
+        con->dd_printf("  CPUDIV:   %d\n", clock_per_cycle());
+      con->dd_printf("  f_CPU:    %.0f Hz\n", uc->get_xtal() / clock_per_cycle());
+    }
+
+  if (pckenr1)
+    con->dd_printf("  PCKENR1:  0x%02x\n", pckenr1->get());
+  if (pckenr2)
+    con->dd_printf("  PCKENR2:  0x%02x\n", pckenr2->get());
+  if (pckenr3)
+    con->dd_printf("  PCKENR3:  0x%02x\n", pckenr3->get());
+}
+
 
 /* SAF */
 
 cl_clk_saf::cl_clk_saf(class cl_uc *auc):
   cl_clk(auc)
 {
+  f_LSI = 128000;
+
+  CLK_SOURCE_HSI = 0xe1;
+  CLK_SOURCE_LSI = 0xd2;
+  CLK_SOURCE_HSE = 0xb4;
+
+  cpudiv = true;
 }
 
 int
 cl_clk_saf::init(void)
 {
+  static const struct var_def vars[] = {
+    { "ICKR",     var_offset(0), "Internal clock register" },
+      { "REGAH",  var_bit(5), "Regulator power off in Active-halt mode" },
+      { "LSIRDY", var_bit(4), "Low speed internal oscillator ready" },
+      { "LSIEN",  var_bit(3), "Low speed internal RC oscillator enable" },
+      { "FHWU",   var_bit(2), "Fast wakeup from Halt/Active-halt modes" },
+      { "HSIRDY", var_bit(1), "High speed internal oscillator ready" },
+      { "HSIEN",  var_bit(0), "High speed internal RC oscillator enable" },
+
+    { "ECKR",        var_offset(1), "External clock register" },
+      { "HSERDY", var_bit(1), "High speed external crystal oscillator ready" },
+      { "HSEEN",  var_bit(0), "High speed external crystal oscillator enable" },
+
+    { "CMSR", var_offset(3), "Clock master status register" },
+      { "CKM", var_bitset(7,  0), "Clock master status bits" },
+
+    { "SWR", var_offset(4), "Clock master switch register" },
+      { "SWI", var_bitset(7,  0), "Clock master selection bits" },
+
+    { "SWCR", var_offset(5), "Clock switch control register" },
+      { "SWIF",  var_bit(3), "Clock switch interrupt flag" },
+      { "SWIEN", var_bit(2), "Clock switch interrupt enable" },
+      { "SWEN",  var_bit(1), "Switch start/stop" },
+      { "SWBSY", var_bit(0), "Switch busy" },
+
+    { "CKDIVR", var_offset(6), "Clock divider register" },
+      { "HSIDIV", var_bitset(4,  3), "High speed internal clock prescalar" },
+      { "CPUDIV", var_bitset(2,  0), "CPU clock prescalar" },
+
+    { "PCKENR1", var_offset(7), "Peripheral clock gating register 1" },
+      { "TIM1",     var_bit(7), "Peripheral clock enable TIM1" },
+      { "TIM3",     var_bit(6), "Peripheral clock enable TIM3" },
+      { "TIM25",    var_bit(5), "Peripheral clock enable TIM2/TIM5" },
+      { "TIM46",    var_bit(4), "Peripheral clock enable TIM4/TIM6" },
+      { "UART1234", var_bit(3), "Peripheral clock enable UART1/2/3/4" },
+      { "UART1234", var_bit(2), "Peripheral clock enable UART1/2/3/4" },
+      { "SPI",      var_bit(1), "Peripheral clock enable SPI" },
+      { "I2C",      var_bit(0), "Peripheral clock enable I2C" },
+
+    { "CSSR", var_offset(8), "Clock security system register" },
+      { "CSSD",   var_bit(3), "Clock security system detection" },
+      { "CSSDIE", var_bit(2), "Clock security system detection interrupt enable" },
+      { "AUX",    var_bit(1), "Auxiliary oscillator connected to master clock" },
+      { "CSSEN",  var_bit(0), "Clock security system enable" },
+
+    { "CCOR", var_offset(9), "Configurable clock output register" },
+      { "CCOBSY", var_bit(6), "Configurable clock output busy" },
+      { "CCORDY", var_bit(5), "Configurable clock output ready" },
+      { "CCOSEL", var_bit(4), "Configurable clock output selection" },
+      { "CCOEN",  var_bit(0), "Configurable clock output enable" },
+
+    { "PCKENR2", var_offset(10), "Peripheral clock gating register 2" },
+      { "CAN", var_bit(7), "Peripheral clock enable CAN" },
+      { "ADC", var_bit(3), "Peripheral clock enable ADC" },
+      { "AWU", var_bit(2), "Peripheral clock enable AWU" },
+
+    { "HSITRIMR", var_offset(12), "HSI clock calibration trimming register" },
+      { "HSITRIM", var_bitset(3,  0), "HSI trimming value" },
+
+    { "SWIMCCR", var_offset(13), "SWIM clock control register" },
+      { "SWIMCLK", var_bit(0), "SWIM clock divider" },
+  };
+
   cl_clk::init();
-  ckdivr= register_cell(uc->rom, base+6);
-  pckenr1= register_cell(uc->rom, base+7);
-  pckenr2= register_cell(uc->rom, base+10);
+
+  uc->vars->add(chars(get_name()).uppercase() + "_", uc->rom, base, vars, sizeof(vars)/sizeof(vars[0]));
+
+  ickr = register_cell(uc->rom, base+0);
+  eckr = register_cell(uc->rom, base+1);
+  cmsr = register_cell(uc->rom, base+3);
+  cmsr->set_flag(CELL_READ_ONLY, true);
+  swr = register_cell(uc->rom, base+4);
+  swcr = register_cell(uc->rom, base+5);
+  ckdivr = register_cell(uc->rom, base+6);
+  pckenr1 = register_cell(uc->rom, base+7);
+  // cssr = register_cell(uc->rom, base+8);
+  // ccor = register_cell(uc->rom, base+9);
+  pckenr2 = register_cell(uc->rom, base+10);
+  // hsitrimr = register_cell(uc->rom, base+12);
+  // swimccr = register_cell(uc->rom, base+13);
+
   return 0;
 }
 
+int
+cl_clk_saf::clock_per_cycle(void)
+{
+  return (1 << (ckdivr->get() & 0x07));
+}
+
+int
+cl_clk_saf::xtal_per_clock(t_mem ckdivr_val)
+{
+  if (cmsr->get() == CLK_SOURCE_HSI)
+    return (1 << ((ckdivr_val >> 3) & 0x03));
+  else
+    return 1;
+}
+
 void
 cl_clk_saf::reset(void)
 {
-  //ickr->write(0x01);
-  //eckr->write(0);
-  //cmsr->write(0xe1);
-  //swr->write(0xe1);
-  //swcr->write(0);
+  ickr->write(0x01);
+  eckr->write(0x00);
   ckdivr->write(0x18);
+  swr->write(CLK_SOURCE_HSI);
+  swcr->write(0x00);
   pckenr1->write(0xff);
-  //cssr->write(0);
-  //ccor->write(0);
+  uc->rom->write(base+8, 0x00); //cssr->write(0x00);
+  uc->rom->write(base+9, 0x00); //ccor->write(0x00);
   pckenr2->write(0xff);
-  //hsitrimr->write(0);
-  //swimccr->write(0);
+  uc->rom->write(base+12, 0x00); //hsitrimr->write(0x00);
+  uc->rom->write(base+13, 0x00); //swimccr->write(0x00);
+
+  set_osc(CLK_SOURCE_HSI);
+}
+
+void
+cl_clk_saf::write(class cl_memory_cell *cell, t_mem *val)
+{
+  if (cell == eckr)
+    {
+      t_mem preserve = 0xfc;
+
+      // RM0016: 9.9.2: HSERDY: This bit is set and cleared by hardware.
+      preserve |= CLK_ECKR_HSERDY;
+
+      // RM0016 9.9.2: It [HSEEN] cannot be cleared when HSE is selected as clock
+      // master (CLK_CMSR register) or as the active CCO source.
+      // FIXME: CCO is not yet implemented.
+      if (cmsr->get() == CLK_SOURCE_HSE)
+        preserve |= CLK_ECKR_HSEEN;
+
+      *val = (*val & (~preserve)) | (eckr->get() & preserve);
+    }
+  else if (cell == ickr)
+    {
+      t_mem preserve = 0;
+
+      // RM0016: 9.9.1: HSIRDY: This bit is set and cleared by hardware.
+      // RM0016: 9.9.1: LSIRDY: This bit is set and cleared by hardware.
+      preserve = CLK_ICKR_HSIRDY | CLK_ICKR_LSIRDY;
+
+      // RM0016 9.9.1: It [LSIEN] cannot be cleared when LSI is selected as clock
+      // master (CLK_CMSR register), as the active CCO source or as a clock source
+      // for the AWU peripheral or independent Watchdog.
+      // FIXME: CCO, AWU and IWDG are not yet implemented.
+      if (cmsr->get() == CLK_SOURCE_LSI)
+        preserve |= CLK_ICKR_LSIEN;
+
+      // RM0016 9.9.1: It [HSIEN] cannot be cleared when HSI is selected as clock
+      // master (CLK_CMSR register), as the active CCO source or if the safe oscillator
+      // (AUX) is enabled.
+      // FIXME: CCO and AUX are not yet implemented.
+      if (cmsr->get() == CLK_SOURCE_HSI)
+        preserve |= CLK_ICKR_HSIEN;
+
+      *val = (*val & (~preserve)) | (ickr->get() & preserve);
+    }
+  else if (cell == swr)
+    {
+      if (*val == CLK_SOURCE_LSI)
+        {
+          // RM0016 9.9.1: It [LSIEN] is set by hardware whenever the LSI oscillator is
+          // required, for example: [...] When switching to LSI clock (see CLK_SWR register).
+          ickr->write(ickr->get() | CLK_ICKR_LSIEN);
+        }
+      if (*val == CLK_SOURCE_HSI)
+        {
+          // RM0016 9.9.1: It [HSIEN] is set by hardware whenever the HSI oscillator is
+          // required, for example: [...] When switching to HSI clock (see CLK_SWR register).
+          ickr->write(ickr->get() | CLK_ICKR_HSIEN);
+        }
+    }
+
+  cl_clk::write(cell, val);
 }
 
 bool
-cl_clk_saf::tim(int id)
+cl_clk_saf::tim(int id, t_mem *val)
 {
   switch (id)
     {
     case 1:
-      return pckenr1 && (pckenr1->get() & 0x80);
+      return pckenr1 && (*val & 0x80);
     case 2: case 5:
-      return pckenr1 && (pckenr1->get() & 0x20);
+      return pckenr1 && (*val & 0x20);
     case 3:
-      return pckenr1 && (pckenr1->get() & 0x40);
+      return pckenr1 && (*val & 0x40);
     case 4: case 6:
-      return pckenr1 && (pckenr1->get() & 0x10);
+      return pckenr1 && (*val & 0x10);
     }
   return false;
 }
 
 bool
-cl_clk_saf::usart(int id)
+cl_clk_saf::usart(int id, t_mem *val)
 {
   cl_stm8 *u= (cl_stm8 *)uc;
   if (id == 1)
     switch (u->type->subtype)
       {
       case DEV_STM8S003: case DEV_STM8S103: case DEV_STM8S903:
-	return pckenr1 && (pckenr1->get() & 0x08);
+	return pckenr1 && (*val & 0x08);
       case DEV_STM8S007: case DEV_STM8S207: case DEV_STM8S208:
       case DEV_STM8AF52:
-	return pckenr1 && (pckenr1->get() & 0x04);
+	return pckenr1 && (*val & 0x04);
       }
   else if (id == 2)
     switch (u->type->subtype)
       {
       case DEV_STM8S005: case DEV_STM8S105: case DEV_STM8AF62_46:
-	return pckenr1 && (pckenr1->get() & 0x08);
+	return pckenr1 && (*val & 0x08);
       }
   else if (id == 3)
     switch (u->type->subtype)
       {
       case DEV_STM8S007: case DEV_STM8S207: case DEV_STM8S208:
       case DEV_STM8AF52:
-	return pckenr1 && (pckenr1->get() & 0x08);
+	return pckenr1 && (*val & 0x08);
       }
   else if (id == 4)
     switch (u->type->subtype)
       {
       case DEV_STM8AF62_12:
-	return pckenr1 && (pckenr1->get() & 0x08);
+	return pckenr1 && (*val & 0x08);
       }
   return false;
 }
@@ -206,58 +531,296 @@
 cl_clk_all::cl_clk_all(class cl_uc *auc):
   cl_clk(auc)
 {
+  f_LSI = 38000;
+  f_LSE = 32768;
+
+  CLK_SOURCE_HSI = 0x01;
+  CLK_SOURCE_LSI = 0x02;
+  CLK_SOURCE_HSE = 0x04;
+  CLK_SOURCE_LSE = 0x08;
 }
 
 int
 cl_clk_all::init(void)
 {
+  static const struct var_def vars[] = {
+    { "CKDIVR",     var_offset(0), "Clock divider register" },
+      { "CKM", var_bitset(2,  0), "System clock prescalar" },
+
+    { "CRTCR",          var_offset(1), "Clock RTC register" },
+      { "RTCDIV",   var_bitset(7,  5), "Clock RTC prescalar" },
+      { "RTCSEL",   var_bitset(4,  1), "Configurable RTC clock source selection" },
+      { "RTCSWBSY", var_bit(0),         "RTC clock busy" },
+
+    { "ICKCR",          var_offset(2), "Internal clock register" },
+      { "BEEPHALT", var_bit(6), "BEEP clock Halt/Active-halt mode" },
+      { "FHWU",     var_bit(5), "Fast wakeup from Halt/Active-halt modes" },
+      { "SAHALT",   var_bit(4), "Slow Halt/Active-halt mode" },
+      { "LSIRDY",   var_bit(3), "Low speed internal oscillator ready" },
+      { "LSION",    var_bit(2), "Low speed internal oscillator enable" },
+      { "HSIRDY",   var_bit(1), "High speed internal oscillator ready" },
+      { "HSION",    var_bit(0), "High speed internal oscillator enable" },
+
+    { "PCKENR1", var_offset(3), "Peripheral clock gating register 1" },
+      { "DAC",    var_bit(7), "Peripheral clock enable DAC" },
+      { "BEEP",   var_bit(6), "Peripheral clock enable BEEP" },
+      { "USART1", var_bit(5), "Peripheral clock enable USART1" },
+      { "SPI",    var_bit(4), "Peripheral clock enable SPI1" },
+      { "I2C1",   var_bit(3), "Peripheral clock enable I2C1" },
+      { "TIM4",   var_bit(2), "Peripheral clock enable TIM4" },
+      { "TIM3",   var_bit(1), "Peripheral clock enable TIM3" },
+      { "TIM2",   var_bit(0), "Peripheral clock enable TIM2" },
+
+    { "PCKENR2", var_offset(4), "Peripheral clock gating register 2" },
+      { "BOOTROM", var_bit(7), "Peripheral clock enable boot ROM" },
+      { "COMP12",  var_bit(5), "Peripheral clock enable COMP1 and COMP2" },
+      { "DMA1",    var_bit(4), "Peripheral clock enable DMA1" },
+      { "LCD",     var_bit(3), "Peripheral clock enable LCD" },
+      { "RTC",     var_bit(2), "Peripheral clock enable RTC" },
+      { "TIM1",    var_bit(1), "Peripheral clock enable TIM1" },
+      { "ADC1",    var_bit(0), "Peripheral clock enable ADC1" },
+
+    { "CCOR", var_offset(5), "Configurable clock output register" },
+      { "CCODIV",   var_bitset(7, 5), "Configurable clock output prescalar" },
+      { "CCOSEL",   var_bitset(4, 1), "Configurable clock output selection" },
+      { "CCOSWBSY", var_bit(0), "Configurable clock output switch busy" },
+
+    { "ECKCR", var_offset(6), "External clock register" },
+      { "LSEBYP", var_bit(5), "Low speed external clock bypass" },
+      { "HSEBYP", var_bit(4), "High speed external clock bypass" },
+      { "LSERDY", var_bit(3), "Low speed external crystal oscillator ready" },
+      { "LSEON",  var_bit(2), "Low speed external crystal oscillator enable" },
+      { "HSERDY", var_bit(1), "High speed external crystal oscillator ready" },
+      { "HSEON",  var_bit(0), "High speed external crystal oscillator enable" },
+
+    { "SCSR", var_offset(7), "System clock status register" },
+      { "CKM", var_bitset(7, 0), "System clock status bits" },
+
+    { "SWR", var_offset(8), "System clock switch register" },
+      { "SWI", var_bitset(7, 0), "System clock selection bits" },
+
+    { "SWCR", var_offset(9), "Switch control register" },
+      { "SWIF",  var_bit(3), "Clock switch interrupt flag" },
+      { "SWIEN", var_bit(2), "Clock switch interrupt enable" },
+      { "SWEN",  var_bit(1), "Switch start/stop" },
+      { "SWBSY", var_bit(0), "Switch busy" },
+
+    { "CSSR", var_offset(10), "Clock security system register" },
+      { "CSSDGON", var_bit(4), "Clock security system deglitcher system" },
+      { "CSSD",    var_bit(3), "Clock security system detection" },
+      { "CSSDIE",  var_bit(2), "Clock security system detection interrupt enable" },
+      { "AUX",     var_bit(1), "Auxiliary oscillator connected to master clock" },
+      { "CSSEN",   var_bit(0), "Clock security system enable" },
+
+    { "CBEEPR", var_offset(11), "Clock BEEP register" },
+      { "CLKBEEPSEL", var_bitset(2, 1), "Configurable BEEP clock source selection" },
+      { "BEEPSWBSY",  var_bit(0), "System busy during BEEP clock change" },
+
+    { "HSICALR", var_offset(12), "HSI calibration register" },
+      { "HSICAL", var_bitset(7, 0), "HSI calibration" },
+
+    { "HSITRIMR", var_offset(13), "HSI clock calibration trimming register" },
+      { "HSITRIM", var_bitset(7, 0), "HSI trimming value" },
+
+    { "HSIUNLCKR", var_offset(14), "HSI unlock register" },
+      { "HSIUNLCK", var_bitset(7, 0), "HSI unlock mechanism" },
+
+    { "REGCSR", var_offset(15), "Main regulator control status register" },
+      { "EEREADY",  var_bit(7), "Flash program memory and data EEPROM ready" },
+      { "EEBUSY",   var_bit(6), "Flash program memory and data EEPROM busy" },
+      { "LSEPD",    var_bit(5), "LSE power-down" },
+      { "HSEPD",    var_bit(4), "HSE power-down" },
+      { "LSIPD",    var_bit(3), "LSI power-down" },
+      { "HSIPD",    var_bit(2), "HSI power-down" },
+      { "REGOFF",   var_bit(1), "Main regulator OFF" },
+      { "REGREADY", var_bit(0), "Main regulator ready" },
+
+    { "PCKENR3", var_offset(16), "Peripheral clock gating register 3" },
+      { "CSS_LSE", var_bit(5), "Peripheral clock enable CSS_LSE" },
+      { "USART3",  var_bit(4), "Peripheral clock enable USART3" },
+      { "USART2",  var_bit(3), "Peripheral clock enable USART2" },
+      { "SPI2",    var_bit(2), "Peripheral clock enable SPI2" },
+      { "TIM5",    var_bit(1), "Peripheral clock enable TIM5" },
+      { "AES",     var_bit(0), "Peripheral clock enable AES" },
+  };
+
   cl_clk::init();
-  ckdivr= register_cell(uc->rom, base+0);
-  pckenr1= register_cell(uc->rom, base+3);
-  pckenr2= register_cell(uc->rom, base+4);
-  pckenr3= register_cell(uc->rom, base+16);
+
+  uc->vars->add(chars(get_name()).uppercase() + "_", uc->rom, base, vars, sizeof(vars)/sizeof(vars[0]));
+
+  ckdivr = register_cell(uc->rom, base+0);
+  //crtcr = register_cell(uc->rom, base+1);
+  ickr = register_cell(uc->rom, base+2);
+  pckenr1 = register_cell(uc->rom, base+3);
+  pckenr2 = register_cell(uc->rom, base+4);
+  //ccor = register_cell(uc->rom, base+5);
+  eckr = register_cell(uc->rom, base+6);
+  cmsr = register_cell(uc->rom, base+7);
+  uc->rom->set_cell_flag(base+7, true, CELL_READ_ONLY);
+  swr = register_cell(uc->rom, base+8);
+  swcr = register_cell(uc->rom, base+9);
+  //cssr = register_cell(uc->rom, base+10);
+  //cbeepr = register_cell(uc->rom, base+11);
+  //hsicalr = register_cell(uc->rom, base+12);
+  //hsitrimr = register_cell(uc->rom, base+13);
+  //hsiunlckr = register_cell(uc->rom, base+14);
+  //regcsr = register_cell(uc->rom, base+15);
+  pckenr3 = register_cell(uc->rom, base+16);
+
   return 0;
 }
 
+int
+cl_clk_all::xtal_per_clock(t_mem ckdivr_val)
+{
+  return (1 << (ckdivr_val & 0x07));
+}
+
 void
 cl_clk_all::reset(void)
 {
-  ckdivr->write(3);
-  pckenr1->write(0);
+  ckdivr->write(0x03);
+  uc->rom->write(base+1, 0x00); //crtcr->write(0x00);
+  ickr->write(0x11);
+  uc->rom->write(base+5, 0x00); //ccor->write(0x00);
+  eckr->write(0x00);
+  swr->write(CLK_SOURCE_HSI);
+  swcr->write(0x00);
+  uc->rom->write(base+10, 0x00); //cssr->write(0x00);
+  uc->rom->write(base+11, 0x00); //cbeepr->write(0x00);
+  uc->rom->write(base+12, 0x00); //hsicalr->write(0x00); // Actually a factory calibration value...
+  uc->rom->write(base+13, 0x00); //hsitrimr->write(0x00);
+  uc->rom->write(base+14, 0x00); //hsiunlckr->write(0x00);
+  // FIXME: CLKREGCSR should reset to 0xb9 but that means LSE, HSE and LSI are powered down.
+  // Since we don't emulate the auto-power up behaviour and reflect that in CLKREGCSR
+  // we had best pretend they are always powered up.
+  uc->rom->write(base+15, 0x81); //clkregcsr->write(0x81);
+  pckenr1->write(0x00);
   pckenr2->write(0x80);
-  pckenr3->write(0);
+  pckenr3->write(0x00);
+
+  set_osc(CLK_SOURCE_HSI);
+}
+
+void
+cl_clk_all::write(class cl_memory_cell *cell, t_mem *val)
+{
+  if (cell == eckr)
+    {
+      t_mem preserve = 0xc0;
+
+      // RM0031: 9.14.8: HSERDY: This bit is set and cleared by hardware.
+      preserve |= CLK_ECKR_HSERDY;
+
+      t_mem clk = cmsr->get();
+      if (clk == CLK_SOURCE_HSE)
+        {
+          // RM0031 9.14.8: It [HSEON] cannot be cleared when HSE is selected as system
+          // clock (CLK_SCSR register) or as the active CCO source or as active RTC
+          // clock source.
+          // FIXME: CCO and RTC are not yet implemented.
+          preserve |= CLK_ECKR_HSEEN;
+        }
+      else if (clk == CLK_SOURCE_LSE)
+        {
+          // RM0031 9.14.8: It [LSEON] cannot be cleared when LSE is selected as system
+          // clock (CLK_SCSR register), as active CCO source, as clock source for the
+          // BEEP peripheral and BEEPAHALT is set or as active RTC.
+          // FIXME: CCO, BEEP and RTC are not yet implemented.
+          preserve |= CLK_ECKR_LSEEN;
+        }
+
+      *val = (*val & (~preserve)) | (eckr->get() & preserve);
+    }
+  else if (cell == ickr)
+    {
+      t_mem preserve = 0;
+
+      // RM0031: 9.14.3: HSIRDY: This bit is set and cleared by hardware.
+      // RM0031: 9.14.3: LSIRDY: This bit is set and cleared by hardware.
+      preserve = CLK_ICKR_HSIRDY | CLK_ICKR_LSIRDY;
+
+      t_mem clk = cmsr->get();
+      if (clk == CLK_SOURCE_LSI)
+        {
+          // RM0031 9.14.3: It [LSION] cannot be cleared when LSI is selected as clock
+          // master (CLK_SCSR register), as active CCO source, as clock source for the
+          // BEEP peripheral while BEEPAHALT is set or as active clock source for RTC.
+          // FIXME: CCO, BEEP and RTC are not yet implemented.
+          preserve |= CLK_ICKR_LSIEN;
+        }
+      else if (clk == CLK_SOURCE_HSI)
+        {
+          // RM0031 9.14.3: It [HSIEN] cannot be cleared when HSI is selected as clock
+          // master (CLK_CMSR register), as the active CCO source or if the safe oscillator
+          // (AUX) is enabled.
+          // FIXME: CCO and AUX are not yet implemented.
+          preserve |= CLK_ICKR_HSIEN;
+        }
+
+      *val = (*val & (~preserve)) | (ickr->get() & preserve);
+    }
+  else if (cell == swr)
+    {
+      if (*val == CLK_SOURCE_LSE)
+        {
+          // RM0031 9.14.8: It [LSEON] is set by hardware whenever the LSE oscillator is
+          // required, for example: [...] When switching to LSI clock (see CLK_SWR register).
+          eckr->write(eckr->get() | CLK_ECKR_LSEEN);
+        }
+      else if (*val == CLK_SOURCE_HSE)
+        {
+          // RM0031 9.14.8: It [HSEON] is set by hardware whenever the HSE oscillator is
+          // required, for example: [...] When switching to HSI clock (see CLK_SWR register).
+          eckr->write(eckr->get() | CLK_ECKR_HSEEN);
+        }
+      else if (*val == CLK_SOURCE_LSI)
+        {
+          // RM0031 9.14.3: It [LSION] is set by hardware whenever the LSI oscillator is
+          // required, for example: [...] When switching to LSI clock (see CLK_SWR register).
+          ickr->write(ickr->get() | CLK_ICKR_LSIEN);
+        }
+      else if (*val == CLK_SOURCE_HSI)
+        {
+          // RM0031 9.14.3: It [HSION] is set by hardware whenever the HSI oscillator is
+          // required, for example: [...] When switching to HSI clock (see CLK_SWR register).
+          ickr->write(ickr->get() | CLK_ICKR_HSIEN);
+        }
+    }
+
+  cl_clk::write(cell, val);
 }
 
 bool
-cl_clk_all::tim(int id)
+cl_clk_all::tim(int id, t_mem *val)
 {
   switch (id)
     {
     case 1:
-      return pckenr2 && (pckenr2->get() & 0x02);
+      return pckenr2 && (*val & 0x02);
     case 2:
-      return pckenr1 && (pckenr1->get() & 0x01);
+      return pckenr1 && (*val & 0x01);
     case 3:
-      return pckenr1 && (pckenr1->get() & 0x02);
+      return pckenr1 && (*val & 0x02);
     case 4:
-      return pckenr1 && (pckenr1->get() & 0x04);
+      return pckenr1 && (*val & 0x04);
     case 5:
-      return pckenr3 && (pckenr3->get() & 0x02);
+      return pckenr3 && (*val & 0x02);
     }
   return false;
 }
 
 bool
-cl_clk_all::usart(int id)
+cl_clk_all::usart(int id, t_mem *val)
 {
   switch (id)
     {
     case 1:
-      return pckenr1 && (pckenr1->get() & 0x20);
+      return pckenr1 && (*val & 0x20);
     case 2:
-      return pckenr3 && (pckenr3->get() & 0x08);
+      return pckenr3 && (*val & 0x08);
     case 3:
-      return pckenr3 && (pckenr3->get() & 0x10);
+      return pckenr3 && (*val & 0x10);
     }
   return false;
 }
@@ -273,41 +836,71 @@
 int
 cl_clk_l101::init(void)
 {
+  static const struct var_def vars[] = {
+    { "CKDIVR", var_offset(0), "Clock divider register" },
+      { "HSIDIV", var_bitset(1, 0), "High speed internal clock prescalar" },
+
+    { "PCKENR", var_offset(3), "Peripheral clock gating register" },
+      { "AWU_BEEP", var_bit(6), "Peripheral clock enable AWU+BEEP" },
+      { "USART",    var_bit(5), "Peripheral clock enable USART" },
+      { "SPI",      var_bit(4), "Peripheral clock enable SPI" },
+      { "I2C",      var_bit(3), "Peripheral clock enable I2C" },
+      { "TIM4",     var_bit(2), "Peripheral clock enable TIM4" },
+      { "TIM3",     var_bit(1), "Peripheral clock enable TIM3" },
+      { "TIM2",     var_bit(0), "Peripheral clock enable TIM2" },
+
+    { "CCOR", var_offset(5), "Configurable clock output register" },
+      { "CCOSEL", var_bitset(2, 1), "Configurable clock output selection" },
+      { "CCOEN",  var_bit(0), "Configurable clock output enable" },
+  };
+
   cl_clk::init();
-  ckdivr= register_cell(uc->rom, base+0);
-  pckenr1= register_cell(uc->rom, base+3);
+
+  uc->vars->add(chars(get_name()).uppercase() + "_", uc->rom, base, vars, sizeof(vars)/sizeof(vars[0]));
+
+  ckdivr = register_cell(uc->rom, base+0);
+  pckenr1 = register_cell(uc->rom, base+3);
+  //ccor = register_cell(uc->rom, base+5);
+
   return 0;
 }
 
+int
+cl_clk_l101::xtal_per_clock(t_mem ckdivr_val)
+{
+  return (1 << (ckdivr_val & 0x03));
+}
+
 void
 cl_clk_l101::reset(void)
 {
-  ckdivr->write(3);
-  pckenr1->write(0);
+  ckdivr->write(0x03);
+  pckenr1->write(0x00);
+  uc->rom->write(base+5, 0x00); //ccor->write(0x00);
 }
 
 bool
-cl_clk_l101::tim(int id)
+cl_clk_l101::tim(int id, t_mem *val)
 {
   switch (id)
     {
     case 2:
-      return pckenr1 && (pckenr1->get() & 0x01);
+      return pckenr1 && (*val & 0x01);
     case 3:
-      return pckenr1 && (pckenr1->get() & 0x02);
+      return pckenr1 && (*val & 0x02);
     case 4:
-      return pckenr1 && (pckenr1->get() & 0x04);
+      return pckenr1 && (*val & 0x04);
     }
   return false;
 }
 
 bool
-cl_clk_l101::usart(int id)
+cl_clk_l101::usart(int id, t_mem *val)
 {
   switch (id)
     {
     case 1:
-      return pckenr1 && (pckenr1->get() & 0x20);
+      return pckenr1 && (*val & 0x20);
     }
   return false;
 }
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/clkcl.h sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/clkcl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/clkcl.h	2017-02-03 18:14:56.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/clkcl.h	2022-01-20 15:57:08.000000000 +0000
@@ -45,57 +45,114 @@
 class cl_clk: public cl_hw
 {
  protected:
+  static const unsigned long f_HSI = 16000000;
+
+  static const t_mem CLK_ECKR_LSERDY = (1 << 3);
+  static const t_mem CLK_ECKR_LSEEN = (1 << 2);
+  static const t_mem CLK_ECKR_HSERDY = (1 << 1);
+  static const t_mem CLK_ECKR_HSEEN = (1 << 0);
+
+  static const t_mem CLK_ICKR_LSIRDY = (1 << 4);
+  static const t_mem CLK_ICKR_LSIEN = (1 << 3);
+  static const t_mem CLK_ICKR_HSIRDY = (1 << 1);
+  static const t_mem CLK_ICKR_HSIEN = (1 << 0);
+
+  static const t_mem CLK_SWCR_SWBSY = 0x01;
+  static const t_mem CLK_SWCR_SWEN = 0x02;
+
+  unsigned long f_LSI;
+  unsigned long f_LSE;
+
+  t_mem CLK_SOURCE_HSI;
+  t_mem CLK_SOURCE_LSI;
+  t_mem CLK_SOURCE_HSE;
+  t_mem CLK_SOURCE_LSE;
+
+  double f_OSC;
   t_addr base;
+
   class cl_memory_cell
+    *cmsr,
+    *eckr,
+    *ickr,
+    *swr,
+    *swcr,
     *ckdivr,
     *pckenr1,
     *pckenr2,
     *pckenr3;
+
+  bool cpudiv;
+
+  void set_osc(t_mem osc);
+
  public:
   cl_clk(class cl_uc *auc);
+
   virtual int init(void);
+  virtual void reset(void) {}
+
+  virtual int clock_per_cycle(void);
+  virtual int xtal_per_clock(t_mem ckdivr_val);
 
   virtual void write(class cl_memory_cell *cell, t_mem *val);
-  virtual bool tim(int id) { return false; }
-  virtual bool usart(int id) { return false; }
-  
-  virtual void reset(void) {}
+  virtual bool tim(int id, t_mem *val) { return false; }
+  virtual bool usart(int id, t_mem *val) { return false; }
+
+  virtual void print_info(class cl_console_base *con);
 };
 
 class cl_clk_saf: public cl_clk
 {
+private:
+  static const t_mem CLK_ICKR_FHWU = (1 << 2);
+  static const t_mem CLK_ICKR_REGAH = (1 << 5);
+
  public:
   cl_clk_saf(class cl_uc *auc);
-  virtual int init(void);
 
+  virtual int init(void);
   virtual void reset(void);
 
-  virtual bool tim(int id);
-  virtual bool usart(int id);
+  virtual int clock_per_cycle(void);
+  virtual int xtal_per_clock(t_mem ckdivr_val);
+
+  virtual void write(class cl_memory_cell *cell, t_mem *val);
+  virtual bool tim(int id, t_mem *val);
+  virtual bool usart(int id, t_mem *val);
 };
 
 class cl_clk_all: public cl_clk
 {
+private:
+  static const t_mem CLK_ICKR_FHWU = (1 << 5);
+  static const t_mem CLK_ICKR_SAHALT = (1 << 4);
+
  public:
   cl_clk_all(class cl_uc *auc);
   virtual int init(void);
 
   virtual void reset(void);
 
-  virtual bool tim(int id);
-  virtual bool usart(int id);
+  virtual int xtal_per_clock(t_mem ckdivr_val);
+
+  virtual void write(class cl_memory_cell *cell, t_mem *val);
+  virtual bool tim(int id, t_mem *val);
+  virtual bool usart(int id, t_mem *val);
 };
 
 class cl_clk_l101: public cl_clk
 {
  public:
   cl_clk_l101(class cl_uc *auc);
-  virtual int init(void);
 
+  virtual int init(void);
   virtual void reset(void);
 
-  virtual bool tim(int id);
-  virtual bool usart(int id);
+  virtual int xtal_per_clock(t_mem ckdivr_val);
+
+  virtual bool tim(int id, t_mem *val);
+  virtual bool usart(int id, t_mem *val);
 };
 
 
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/flash.cc sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/flash.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/flash.cc	2019-04-02 10:46:33.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/flash.cc	2022-01-24 11:09:43.000000000 +0000
@@ -26,6 +26,7 @@
 /*@1@*/
 
 #include 
+#include 
 
 #include "globals.h"
 
@@ -65,11 +66,11 @@
   decoders= new cl_decoder_list(2, 2, false);
   cella= (class cl_memory_cell *)malloc(size * sizeof(class cl_memory_cell));
   //cell->init();
-  int i;
+  t_addr i;
   for (i= 0; i < size; i++)
     {
       void *p= &(cella[i]);
-      memcpy(p, cell, sizeof(class cl_memory_cell));
+      memcpy(p, (void*)cell, sizeof(class cl_memory_cell));
       cella[i].init();
     }
   dummy= new cl_dummy_cell(8);
@@ -104,14 +105,14 @@
   return 0;
 }
 
-char *
+const char *
 cl_flash::cfg_help(t_addr addr)
 {
   switch (addr)
     {
-    case stm8_flash_on: return (char*)"Turn simulation of flash on/off (bool, RW)";
+    case stm8_flash_on: return "Turn simulation of flash on/off (bool, RW)";
     }
-  return (char*)"Not used";
+  return "Not used";
 }
 
 int
@@ -119,7 +120,7 @@
 {
   if (state & fs_busy)
     {
-      double now= uc->get_rtime();
+      double now= uc->ticks->get_rtime();
       double elapsed= (now - start_time) * 10e6;
 
       if ((state == fs_pre_erase) &&
@@ -164,9 +165,9 @@
 cl_flash::finish_program(bool ok)
 {
   if (ok)
-    iapsr->set_bit1(0x04);
+    iapsr->set(iapsr->get() | 0x04);
   else
-    iapsr->set_bit1(0x01);
+    iapsr->set(iapsr->get() | 0x01);
   state= fs_wait_mode;
 }
 
@@ -494,7 +495,7 @@
 {
   uc->sim->app->debug("FLASH start prg %d\n", start_state);
   state= start_state;
-  start_time= uc->get_rtime();
+  start_time= uc->ticks->get_rtime();
 }
 
 const char *
@@ -538,7 +539,7 @@
   con->dd_printf("\n");
 
   con->dd_printf("State: %s\n", state_name(state));
-  print_cfg_info(con);
+  //print_cfg_info(con);
 }
 
 
@@ -565,12 +566,12 @@
 					cr1r,0x02,
 					iapsr,0x04,
 					0x8008+24*4, false, false,
-					chars("end of flash programming"), 20*20+0));
+					"FLASH_EOP", 20*20+0));
   uc->it_sources->add(is= new cl_it_src(uc, 24,
 					cr1r,0x02,
 					iapsr,0x01,
 					0x8008+24*4, false, false,
-					chars("write attempted to protected page"), 20*20+1));
+					"FLASH_RO", 20*20+1));
   is->init();
 }
 
@@ -598,12 +599,12 @@
 					cr1r,0x02,
 					iapsr,0x04,
 					0x8008+1*4, false, false,
-					chars("end of flash programming"), 20*20+0));
+					"FLASH_EOP", 20*20+0));
   uc->it_sources->add(is= new cl_it_src(uc, 1,
 					cr1r,0x02,
 					iapsr,0x01,
 					0x8008+1*4, false, false,
-					chars("write attempted to protected page"), 20*20+1));
+					"FLASH_RO", 20*20+1));
   is->init();
 }
 
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/flashcl.h sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/flashcl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/flashcl.h	2019-04-02 10:46:33.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/flashcl.h	2021-04-26 19:46:10.000000000 +0000
@@ -37,7 +37,7 @@
 class cl_flash_cell: public cl_cell8
 {
  public:
- cl_flash_cell(uchar awidth): cl_cell8(awidth) {}
+  cl_flash_cell(uchar awidth): cl_cell8(awidth) {}
   virtual t_mem write(t_mem val);
 };
 
@@ -106,7 +106,7 @@
   virtual t_mem read(class cl_memory_cell *cell);
   virtual void write(class cl_memory_cell *cell, t_mem *val);
   virtual t_mem conf_op(cl_memory_cell *cell, t_addr addr, t_mem *val);
-  virtual char *cfg_help(t_addr addr);
+  virtual const char *cfg_help(t_addr addr);
 
   virtual void flash_write(t_addr a, t_mem val);
   virtual void set_flash_mode(t_mem cr2val);
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/glob.cc sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/glob.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/glob.cc	2019-02-07 18:28:18.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/glob.cc	2022-01-24 11:09:43.000000000 +0000
@@ -47,6 +47,7 @@
 %1 - unsigned byte index offset
 %2 - unsigned word index offset
 %3 - unsigned 24bit index offset
+%B - bit number (must only occur after some other operand-setting format option)
 */
 
 /*  uint  code, mask;  char  branch;  uchar length;  char  *mnemonic; */
@@ -87,12 +88,12 @@
   { 0x00e5, 0x00ff, ' ', 2, "bcp A,(%1,X)" },
   { 0x00f5, 0x00ff, ' ', 1, "bcp A,(X)" },
 
-  { 0x00cd, 0x00ff, ' ', 3, "call %x", true },
+  { 0x00cd, 0x00ff, 's', 3, "call %x", true },
   { 0x00dd, 0x00ff, ' ', 3, "call (%2,X)", true },
   { 0x00ed, 0x00ff, ' ', 2, "call (%1,X)", true },
   { 0x00fd, 0x00ff, ' ', 1, "call (X)", true },
-  { 0x008d, 0x00ff, ' ', 4, "callf %e", true },
-  { 0x00ad, 0x00ff, ' ', 2, "callr %p", true },
+  { 0x008d, 0x00ff, 's', 4, "callf %e", true },
+  { 0x00ad, 0x00ff, 's', 2, "callr %p", true },
 
   { 0x008c, 0x00ff, ' ', 1, "ccf" },
 
@@ -139,8 +140,8 @@
   { 0x0051, 0x00ff, ' ', 1, "exgw X,Y" },
   { 0x0061, 0x00ff, ' ', 1, "exg A,YL" },
   { 0x008e, 0x00ff, ' ', 1, "halt" },
-  { 0x0082, 0x00ff, ' ', 4, "int %e" },
-  
+  { 0x0082, 0x00ff, 'j', 4, "int %e" },
+
   { 0x000c, 0x00ff, ' ', 2, "inc (%1,SP)" },
   { 0x003c, 0x00ff, ' ', 2, "inc %d" },
   { 0x004c, 0x00ff, ' ', 1, "inc A" },
@@ -148,30 +149,30 @@
   { 0x007c, 0x00ff, ' ', 1, "inc (X)" },
   { 0x005c, 0x00ff, ' ', 1, "incw X" },
 
-  { 0x0080, 0x00ff, ' ', 1, "iret" },
+  { 0x0080, 0x00ff, 'x', 1, "iret" },
 
-  { 0x00cc, 0x00ff, ' ', 3, "jp %x" },
-  { 0x00dc, 0x00ff, ' ', 3, "jp (%2,X)" },
-  { 0x00ec, 0x00ff, ' ', 2, "jp (%1,X)" },
-  { 0x00fc, 0x00ff, ' ', 1, "jp (X)" },
-  { 0x00ac, 0x00ff, ' ', 4, "jpf %e" },
-  { 0x0020, 0x00ff, ' ', 2, "jra %p" },
+  { 0x00cc, 0x00ff, 'j', 3, "jp %x" },
+  { 0x00dc, 0x00ff, 'x', 3, "jp (%2,X)" },
+  { 0x00ec, 0x00ff, 'x', 2, "jp (%1,X)" },
+  { 0x00fc, 0x00ff, 'x', 1, "jp (X)" },
+  { 0x00ac, 0x00ff, 'j', 4, "jpf %e" },
+  { 0x0020, 0x00ff, 'j', 2, "jra %p" },
 
   { 0x0021, 0x00ff, ' ', 2, "jrf %p" },
-  { 0x0022, 0x00ff, ' ', 2, "jrugt %p" },
-  { 0x0023, 0x00ff, ' ', 2, "jrule %p" },
-  { 0x0024, 0x00ff, ' ', 2, "jruge %p" },
-  { 0x0025, 0x00ff, ' ', 2, "jrult %p" },
-  { 0x0026, 0x00ff, ' ', 2, "jrne %p" },
-  { 0x0027, 0x00ff, ' ', 2, "jreq %p" },
-  { 0x0028, 0x00ff, ' ', 2, "jrnv %p" },
-  { 0x0029, 0x00ff, ' ', 2, "jrv %p" },
-  { 0x002a, 0x00ff, ' ', 2, "jrpl %p" },
-  { 0x002b, 0x00ff, ' ', 2, "jrmi %p" },
-  { 0x002c, 0x00ff, ' ', 2, "jrsgt %p" },
-  { 0x002d, 0x00ff, ' ', 2, "jrsle %p" },
-  { 0x002e, 0x00ff, ' ', 2, "jrsge %p" },
-  { 0x002f, 0x00ff, ' ', 2, "jrslt %p" },
+  { 0x0022, 0x00ff, 'b', 2, "jrugt %p" },
+  { 0x0023, 0x00ff, 'b', 2, "jrule %p" },
+  { 0x0024, 0x00ff, 'b', 2, "jruge %p" }, // aka jrnc
+  { 0x0025, 0x00ff, 'b', 2, "jrult %p" }, // aka jrc
+  { 0x0026, 0x00ff, 'b', 2, "jrne %p" },
+  { 0x0027, 0x00ff, 'b', 2, "jreq %p" },
+  { 0x0028, 0x00ff, 'b', 2, "jrnv %p" },
+  { 0x0029, 0x00ff, 'b', 2, "jrv %p" },
+  { 0x002a, 0x00ff, 'b', 2, "jrpl %p" },
+  { 0x002b, 0x00ff, 'b', 2, "jrmi %p" },
+  { 0x002c, 0x00ff, 'b', 2, "jrsgt %p" },
+  { 0x002d, 0x00ff, 'b', 2, "jrsle %p" },
+  { 0x002e, 0x00ff, 'b', 2, "jrsge %p" },
+  { 0x002f, 0x00ff, 'b', 2, "jrslt %p" },
 
   { 0x007b, 0x00ff, ' ', 2, "ld A,(%1,SP)" },
   { 0x00a6, 0x00ff, ' ', 2, "ld A,%b" },
@@ -194,8 +195,8 @@
 
   { 0x00a7, 0x00ff, ' ', /*2*/4, "ldf (%3,X),A" },
   { 0x00af, 0x00ff, ' ', /*2*/4, "ldf A,(%3,X)" },
-  { 0x00bd, 0x00ff, ' ', /*2*/4, "ldf %e,A" },
-  { 0x00bc, 0x00ff, ' ', /*2*/4, "ldf A,%e" },
+  { 0x00bd, 0x00ff, ' ', /*2*/4, "ldf %3,A" },
+  { 0x00bc, 0x00ff, ' ', /*2*/4, "ldf A,%3" },
   { 0x001e, 0x00ff, ' ', 2, "ldw X,(%1,SP)" },
   { 0x00ae, 0x00ff, ' ', 3, "ldw X,%w" },
   { 0x00be, 0x00ff, ' ', 2, "ldw X,%d" },
@@ -215,7 +216,7 @@
   { 0x0094, 0x00ff, ' ', 1, "ldw SP,X" },
   { 0x0096, 0x00ff, ' ', 1, "ldw X,SP" },
 
-  { 0x0035, 0x00ff, ' ', 4, "mov %b,%x" },
+  { 0x0035, 0x00ff, ' ', 4, "mov %x,%b" },
   { 0x0045, 0x00ff, ' ', 3, "mov %d,%d" },
   { 0x0055, 0x00ff, ' ', 5, "mov %x,%x" },
   { 0x0042, 0x00ff, ' ', 1, "mul X,A" },
@@ -248,8 +249,8 @@
   { 0x004b, 0x00ff, ' ', 2, "push %b" },
 
   { 0x0098, 0x00ff, ' ', 1, "rcf" },
-  { 0x0081, 0x00ff, ' ', 1, "ret" },
-  { 0x0087, 0x00ff, ' ', 1, "retf" },
+  { 0x0081, 0x00ff, 'x', 1, "ret" },
+  { 0x0087, 0x00ff, 'x', 1, "retf" },
   { 0x009a, 0x00ff, ' ', 1, "rim" },
 
   { 0x0009, 0x00ff, ' ', 2, "rlc (%1,SP)" },
@@ -258,14 +259,14 @@
   { 0x0069, 0x00ff, ' ', 2, "rlc (%1,X)" },
   { 0x0079, 0x00ff, ' ', 1, "rlc (X)" },
   { 0x0059, 0x00ff, ' ', 1, "rlcw X" },
-  { 0x0002, 0x00ff, ' ', 1, "rlwa X,A" },
+  { 0x0002, 0x00ff, ' ', 1, "rlwa X" },
   { 0x0006, 0x00ff, ' ', 2, "rrc (%1,SP)" },
   { 0x0036, 0x00ff, ' ', 2, "rrc %d" },
   { 0x0046, 0x00ff, ' ', 1, "rrc A" },
   { 0x0066, 0x00ff, ' ', 2, "rrc (%1,X)" },
   { 0x0076, 0x00ff, ' ', 1, "rrc (X)" },
   { 0x0056, 0x00ff, ' ', 1, "rrcw X" },
-  { 0x0001, 0x00ff, ' ', 1, "rrwa X,A" },
+  { 0x0001, 0x00ff, ' ', 1, "rrwa X" },
 
   { 0x009c, 0x00ff, ' ', 1, "rvf" },
 
@@ -365,41 +366,41 @@
   { 0x00c5, 0x00ff, ' ', 3, "bcp A,[%2.w]" },
   { 0x00d5, 0x00ff, ' ', 3, "bcp A,([%2.w],X)" },
 
-  { 0x0011, 0x00ff, ' ', 3, "bres %x,#0" },
-  { 0x0013, 0x00ff, ' ', 3, "bres %x,#1" },
-  { 0x0015, 0x00ff, ' ', 3, "bres %x,#2" },
-  { 0x0017, 0x00ff, ' ', 3, "bres %x,#3" },
-  { 0x0019, 0x00ff, ' ', 3, "bres %x,#4" },
-  { 0x001b, 0x00ff, ' ', 3, "bres %x,#5" },
-  { 0x001d, 0x00ff, ' ', 3, "bres %x,#6" },
-  { 0x001f, 0x00ff, ' ', 3, "bres %x,#7" },
-
-  { 0x0010, 0x00ff, ' ', 3, "bset %x,#0" },
-  { 0x0012, 0x00ff, ' ', 3, "bset %x,#1" },
-  { 0x0014, 0x00ff, ' ', 3, "bset %x,#2" },
-  { 0x0016, 0x00ff, ' ', 3, "bset %x,#3" },
-  { 0x0018, 0x00ff, ' ', 3, "bset %x,#4" },
-  { 0x001a, 0x00ff, ' ', 3, "bset %x,#5" },
-  { 0x001c, 0x00ff, ' ', 3, "bset %x,#6" },
-  { 0x001e, 0x00ff, ' ', 3, "bset %x,#7" },
-
-  { 0x0001, 0x00ff, ' ', 4, "btjf %x,#0,%p" },
-  { 0x0003, 0x00ff, ' ', 4, "btjf %x,#1,%p" },
-  { 0x0005, 0x00ff, ' ', 4, "btjf %x,#2,%p" },
-  { 0x0007, 0x00ff, ' ', 4, "btjf %x,#3,%p" },
-  { 0x0009, 0x00ff, ' ', 4, "btjf %x,#4,%p" },
-  { 0x000b, 0x00ff, ' ', 4, "btjf %x,#5,%p" },
-  { 0x000d, 0x00ff, ' ', 4, "btjf %x,#6,%p" },
-  { 0x000f, 0x00ff, ' ', 4, "btjf %x,#7,%p" },
-
-  { 0x0000, 0x00ff, ' ', 4, "btjt %x,#0,%p" },
-  { 0x0002, 0x00ff, ' ', 4, "btjt %x,#1,%p" },
-  { 0x0004, 0x00ff, ' ', 4, "btjt %x,#2,%p" },
-  { 0x0006, 0x00ff, ' ', 4, "btjt %x,#3,%p" },
-  { 0x0008, 0x00ff, ' ', 4, "btjt %x,#4,%p" },
-  { 0x000a, 0x00ff, ' ', 4, "btjt %x,#5,%p" },
-  { 0x000c, 0x00ff, ' ', 4, "btjt %x,#6,%p" },
-  { 0x000e, 0x00ff, ' ', 4, "btjt %x,#7,%p" },
+  { 0x0011, 0x00ff, ' ', 3, "bres %x,#%B" },
+  { 0x0013, 0x00ff, ' ', 3, "bres %x,#%B" },
+  { 0x0015, 0x00ff, ' ', 3, "bres %x,#%B" },
+  { 0x0017, 0x00ff, ' ', 3, "bres %x,#%B" },
+  { 0x0019, 0x00ff, ' ', 3, "bres %x,#%B" },
+  { 0x001b, 0x00ff, ' ', 3, "bres %x,#%B" },
+  { 0x001d, 0x00ff, ' ', 3, "bres %x,#%B" },
+  { 0x001f, 0x00ff, ' ', 3, "bres %x,#%B" },
+
+  { 0x0010, 0x00ff, ' ', 3, "bset %x,#%B" },
+  { 0x0012, 0x00ff, ' ', 3, "bset %x,#%B" },
+  { 0x0014, 0x00ff, ' ', 3, "bset %x,#%B" },
+  { 0x0016, 0x00ff, ' ', 3, "bset %x,#%B" },
+  { 0x0018, 0x00ff, ' ', 3, "bset %x,#%B" },
+  { 0x001a, 0x00ff, ' ', 3, "bset %x,#%B" },
+  { 0x001c, 0x00ff, ' ', 3, "bset %x,#%B" },
+  { 0x001e, 0x00ff, ' ', 3, "bset %x,#%B" },
+
+  { 0x0001, 0x00ff, 'f', 4, "btjf %x,#%B,%p" },
+  { 0x0003, 0x00ff, 'f', 4, "btjf %x,#%B,%p" },
+  { 0x0005, 0x00ff, 'f', 4, "btjf %x,#%B,%p" },
+  { 0x0007, 0x00ff, 'f', 4, "btjf %x,#%B,%p" },
+  { 0x0009, 0x00ff, 'f', 4, "btjf %x,#%B,%p" },
+  { 0x000b, 0x00ff, 'f', 4, "btjf %x,#%B,%p" },
+  { 0x000d, 0x00ff, 'f', 4, "btjf %x,#%B,%p" },
+  { 0x000f, 0x00ff, 'f', 4, "btjf %x,#%B,%p" },
+
+  { 0x0000, 0x00ff, 't', 4, "btjt %x,#%B,%p" },
+  { 0x0002, 0x00ff, 't', 4, "btjt %x,#%B,%p" },
+  { 0x0004, 0x00ff, 't', 4, "btjt %x,#%B,%p" },
+  { 0x0006, 0x00ff, 't', 4, "btjt %x,#%B,%p" },
+  { 0x0008, 0x00ff, 't', 4, "btjt %x,#%B,%p" },
+  { 0x000a, 0x00ff, 't', 4, "btjt %x,#%B,%p" },
+  { 0x000c, 0x00ff, 't', 4, "btjt %x,#%B,%p" },
+  { 0x000e, 0x00ff, 't', 4, "btjt %x,#%B,%p" },
 
   { 0x00cd, 0x00ff, ' ', 3, "call [%2.w]", true },
   { 0x00dd, 0x00ff, ' ', 3, "call ([%2.w],X)", true },
@@ -429,8 +430,8 @@
   { 0x005c, 0x00ff, ' ', 3, "inc %x" },
   { 0x006c, 0x00ff, ' ', 3, "inc ([%2.w],X)" },
 
-  { 0x00cc, 0x00ff, ' ', 3, "jp [%2.w]" },
-  { 0x00dc, 0x00ff, ' ', 3, "jp ([%2.w],X)" },
+  { 0x00cc, 0x00ff, 'x', 3, "jp [%2.w]" },
+  { 0x00dc, 0x00ff, 'x', 3, "jp ([%2.w],X)" },
 
   { 0x00c6, 0x00ff, ' ', 3, "ld A,[%2.w]" },
   { 0x00d6, 0x00ff, ' ', 3, "ld A,([%2.w],X)" },
@@ -570,16 +571,16 @@
   { 0x007c, 0x00ff, ' ', 1, "inc (Y)" },
   { 0x005c, 0x00ff, ' ', 1, "incw Y" },
   // 90
-  { 0x00dc, 0x00ff, ' ', 3, "jp (%2,Y)" },
-  { 0x00ec, 0x00ff, ' ', 2, "jp (%1,Y)" },
-  { 0x00fc, 0x00ff, ' ', 1, "jp (Y)" },
-  // 90
-  { 0x0028, 0x00ff, ' ', 2, "jrnh %p" },
-  { 0x0029, 0x00ff, ' ', 2, "jrh %p" },
-  { 0x002c, 0x00ff, ' ', 2, "jrnm %p" },
-  { 0x002d, 0x00ff, ' ', 2, "jrm %p" },
-  { 0x002e, 0x00ff, ' ', 2, "jril %p" },
-  { 0x002f, 0x00ff, ' ', 2, "jrih %p" },
+  { 0x00dc, 0x00ff, 'x', 3, "jp (%2,Y)" },
+  { 0x00ec, 0x00ff, 'x', 2, "jp (%1,Y)" },
+  { 0x00fc, 0x00ff, 'x', 1, "jp (Y)" },
+  // 90
+  { 0x0028, 0x00ff, 'b', 2, "jrnh %p" },
+  { 0x0029, 0x00ff, 'b', 2, "jrh %p" },
+  { 0x002c, 0x00ff, 'b', 2, "jrnm %p" },
+  { 0x002d, 0x00ff, 'b', 2, "jrm %p" },
+  { 0x002e, 0x00ff, 'b', 2, "jril %p" },
+  { 0x002f, 0x00ff, 'b', 2, "jrih %p" },
   // 90
   { 0x00d6, 0x00ff, ' ', 3, "ld A,(%2,Y)" },
   { 0x00e6, 0x00ff, ' ', 2, "ld A,(%1,Y)" },
@@ -591,8 +592,8 @@
   { 0x0097, 0x00ff, ' ', 1, "ld YL,A" },
   { 0x009e, 0x00ff, ' ', 1, "ld A,YH" },
   { 0x009f, 0x00ff, ' ', 1, "ld A,YL" },
-  { 0x00a7, 0x00ff, ' ', /*2*/4, "ldf (%e,Y),A" }, // 90
-  { 0x00af, 0x00ff, ' ', /*2*/4, "ldf A,(%e,Y)" },
+  { 0x00a7, 0x00ff, ' ', /*2*/4, "ldf (%3,Y),A" }, // 90
+  { 0x00af, 0x00ff, ' ', /*2*/4, "ldf A,(%3,Y)" },
   { 0x00ae, 0x00ff, ' ', 3, "ldw Y,%w" },
   { 0x00be, 0x00ff, ' ', 2, "ldw Y,%d" },
   { 0x00ce, 0x00ff, ' ', 3, "ldw Y,%x" },
@@ -626,12 +627,12 @@
   { 0x0069, 0x00ff, ' ', 2, "rlc (%1,Y)" },
   { 0x0079, 0x00ff, ' ', 1, "rlc (Y)" },
   { 0x0059, 0x00ff, ' ', 1, "rlcw Y" },
-  { 0x0002, 0x00ff, ' ', 1, "rlwa Y,A" },
+  { 0x0002, 0x00ff, ' ', 1, "rlwa Y" },
   { 0x0046, 0x00ff, ' ', 3, "rrc (%2,Y)" },
   { 0x0066, 0x00ff, ' ', 2, "rrc (%1,Y)" },
   { 0x0076, 0x00ff, ' ', 1, "rrc (Y)" },
   { 0x0056, 0x00ff, ' ', 1, "rrcw Y" },
-  { 0x0001, 0x00ff, ' ', 1, "rrwa Y,A" },
+  { 0x0001, 0x00ff, ' ', 1, "rrwa Y" },
   
   { 0x00d2, 0x00ff, ' ', 3, "sbc A,(%2,Y)" },
   { 0x00e2, 0x00ff, ' ', 2, "sbc A,(%1,Y)" },
@@ -685,7 +686,7 @@
   { 0x0063, 0x00ff, ' ', 2, "cpl ([%1.w],Y)" },
   { 0x006a, 0x00ff, ' ', 2, "dec ([%1.w],Y)" },
   { 0x006c, 0x00ff, ' ', 2, "inc ([%1.w],Y)" },
-  { 0x00dc, 0x00ff, ' ', 2, "jp ([%1.w],Y)" },
+  { 0x00dc, 0x00ff, 'x', 2, "jp ([%1.w],Y)" },
   { 0x00d6, 0x00ff, ' ', 2, "ld A,([%1.w],Y)" },
   { 0x00d7, 0x00ff, ' ', 2, "ld ([%1.w],Y),A" },
   { 0x00a7, 0x00ff, ' ', /*2*/3, "ldf ([%2.e],Y),A" }, // 91
@@ -736,15 +737,16 @@
   { 0x006a, 0x00ff, ' ', 2, "dec ([%1.w],X)" },
   { 0x003c, 0x00ff, ' ', 2, "inc [%1.w]" },
   { 0x006c, 0x00ff, ' ', 2, "inc ([%1.w],X)" },
-  { 0x00cc, 0x00ff, ' ', 2, "jp [%1.w]" },
-  { 0x00dc, 0x00ff, ' ', 2, "jp ([%1.w],X)" },
-  { 0x00ac, 0x00ff, ' ', 3, "jpf [%2.e]" },
+  { 0x00cc, 0x00ff, 'x', 2, "jp [%1.w]" },
+  { 0x00dc, 0x00ff, 'x', 2, "jp ([%1.w],X)" },
+  { 0x00ac, 0x00ff, 'x', 3, "jpf [%2.e]" },
   { 0x00c6, 0x00ff, ' ', 2, "ld A,[%1.w]" },
   { 0x00d6, 0x00ff, ' ', 2, "ld A,([%1.w],X)" },
   { 0x00c7, 0x00ff, ' ', 2, "ld [%1.w],A" },
   { 0x00d7, 0x00ff, ' ', 2, "ld ([%1.w],X),A" },
   { 0x00a7, 0x00ff, ' ', /*2*/3, "ldf ([%2.e],X),A" },
   { 0x00af, 0x00ff, ' ', /*2*/3, "ldf A,([%2.e],X)" },
+  { 0x00bc, 0x00ff, ' ', 2, "ldf A,[%1.e]" },
   { 0x00ce, 0x00ff, ' ', 2, "ldw X,[%1.w]" },
   { 0x00de, 0x00ff, ' ', 2, "ldw X,([%1.w],X)" },
   { 0x00cf, 0x00ff, ' ', 2, "ldw [%1.w],X" },
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/inst.cc sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/inst.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/inst.cc	2018-12-18 09:27:50.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/inst.cc	2022-01-18 09:48:32.000000000 +0000
@@ -1,1403 +1,1802 @@
-/*
- * Simulator of microcontrollers (inst.cc)
- *
- * stm8 code base from Vaclav Peroutka vaclavpe@users.sourceforge.net
- * and Valentin Dudouyt valentin.dudouyt@gmail.com
- *
- * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
- *
- * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
- *
- */
-/* This file is part of microcontroller simulator: ucsim.
-
-UCSIM is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2 of the License, or
-(at your option) any later version.
-
-UCSIM is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with UCSIM; see the file COPYING.  If not, write to the Free
-Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-02111-1307, USA. */
-/*@1@*/
-
-#include "ddconfig.h"
-#include "stdio.h"
-#include 
-
-// local
-#include "stm8cl.h"
-#include "regsstm8.h"
-#include "stm8mac.h"
-
-int
-cl_stm8::fetchea(t_mem code, unsigned char prefix)
-{
-   int ftc;
-
-   switch ((code >> 4) & 0x0f) {
-   case 0x1: return (unsigned char)fetch()+regs.SP;  // SP indexed
-
-   case 0xb: return fetch();           // direct short
-
-
-   case 0xc:
-      if ( 0 == prefix) {              // direct long
-         return fetch2();
-      } else if ( 0x72 == prefix) {    // long pointer
-         ftc = fetch2();
-         return get2(ftc);
-      } else if ( 0x92 == prefix) {    // short pointer
-         ftc = fetch();
-         return get2(ftc);
-      } else {
-         printf("************* bad prefix !!!!\n");
-         return (resHALT);
-      }
-
-   case 0xd:
-      if ( 0 == prefix) {              // long offset with X reg
-         return fetch2()+regs.X;
-      } else if ( 0x72 == prefix) {    // long pointer to offset with X reg
-         ftc = fetch2();
-         return get2(ftc)+regs.X;
-      } else if ( 0x90 == prefix) {    // long offset with Y reg
-         return fetch2()+regs.Y;
-      } else if ( 0x91 == prefix) {    // short pointer to offset with Y reg
-         ftc = fetch();
-         return get2(ftc)+regs.Y;
-      } else if ( 0x92 == prefix) {    // short pointer to offset with X reg
-         ftc = fetch();
-         return get2(ftc)+regs.X;
-      } else {
-         return( resHALT);
-      }
-
-
-   case 0xe:
-      if ( 0 == prefix) {               // short offset with X reg
-         return fetch()+regs.X;
-      } else if ( 0x90 == prefix) {     // short offset with Y reg
-         return fetch()+regs.Y;
-      } else {
-         return( resHALT);
-      }
-
-   case 0xf:
-      if ( 0 == prefix) {               // X index
-         return regs.X;
-      } else if ( 0x90 == prefix) {     // Y index
-         return regs.Y;
-      } else {
-         return( resHALT);
-      }
-
-   default:
-      return(resHALT);
-   }
-}
-
-int
-cl_stm8::get_dest(t_mem code, unsigned char prefix)
-{
-  int resaddr, ftc;
-
-  switch ((code >> 4) & 0x0f) {
-    case 0x0:
-	  if ( 0 == prefix) {              // short offset with SP
-		 resaddr = fetch()+regs.SP;
-	  } else {
-	    resaddr = ( resHALT);
-	  }
-     break;
-
-    case 0x3:
-	  if ( 0 == prefix) {              // short direct
-		 resaddr = fetch();
-     } else if ( 0x72 == prefix) {    // long indirect - pointer
-         ftc = fetch2();
-       resaddr = get2(ftc);
-     } else if ( 0x92 == prefix) {    // short indirect - pointer
-         ftc = fetch();
-       resaddr = get2(ftc);
-	  } else {
-	    resaddr = ( resHALT);
-	  }
-     break;
-
-    case 0x4:
-	  if ( 0x72 == prefix) {           // long offset with X
-         ftc = fetch2();
-         resaddr = ftc + regs.X;
-     } else if ( 0x90 == prefix) {    // long offset with Y
-         ftc = fetch2();
-         resaddr = ftc + regs.Y;
-	  } else {
-         resaddr = ( resHALT);
-	  }
-     break;
-
-    case 0x5:
-	  if ( 0x72 == prefix) {           // long direct
-         resaddr = fetch2();
-	  } else {
-         resaddr = ( resHALT);
-	  }
-     break;
-
-    case 0x6:
-          if ( 0 == prefix) {              // short offset with X
-		resaddr = (fetch()+regs.X);
-	  } else if ( 0x72 == prefix) {    // long pointer to offset with X
-          ftc = fetch2();
-	  resaddr = (get2(ftc)+regs.X);
-	  } else if ( 0x90 == prefix) {    // short offset with Y
-	    resaddr = (fetch()+regs.Y);
-	  } else if ( 0x91 == prefix) {    // short pointer to offset with Y
-          ftc = fetch();
-	    resaddr = (get2(ftc)+regs.Y);
-	  } else if ( 0x92 == prefix) {    // short pointer to offset with X
-          ftc = fetch();
-	    resaddr = (get2(ftc)+regs.X);
-	  } else {
-	    resaddr =( resHALT);
-	  }
-     break;
-
-    case 0x7:
-	  if ( 0 == prefix) {              // X index
-		resaddr = regs.X;
-	  } else if ( 0x90 == prefix) {    // Y index
-	    resaddr = regs.Y;
-	  } else {
-	    resaddr =( resHALT);
-	  }
-     break;
-
-    default:
-      resaddr =(resHALT);
-      break;
-  }
-
-  return resaddr;
-}
-
-void
-cl_stm8::flag_cvh(int x, int m, int r, bool byte, bool add, int mask)
-{
-  bool xt, xs, xh, mt, ms, mh, rt, rs, rh;
-
-  if (byte)
-    {
-      xt = !!(x & 0x80);
-      xs = !!(x & 0x40);
-      xh = !!(x & 0x08);
-      mt = !!(m & 0x80);
-      ms = !!(m & 0x40);
-      mh = !!(m & 0x08);
-      rt = !!(r & 0x80);
-      rs = !!(r & 0x40);
-      rh = !!(r & 0x08);
-    }
-  else
-    {
-      xt = !!(x & 0x8000);
-      xs = !!(x & 0x4000);
-      xh = !!(x & 0x0080);
-      mt = !!(m & 0x8000);
-      ms = !!(m & 0x4000);
-      mh = !!(m & 0x0080);
-      rt = !!(r & 0x8000);
-      rs = !!(r & 0x4000);
-      rh = !!(r & 0x0080);
-    }
-
-  if (add)
-    {
-      if (mask & BIT_V)
-        FLAG_ASSIGN (BIT_V, ((xt && mt) || (mt && !rt) || (!rt && xt)) ^ ((xs && ms) || (ms && !rs) || (!rs && xs)));
-      if (mask & BIT_C)
-        FLAG_ASSIGN (BIT_C, (xt && mt) || (mt && !rt) || (!rt && xt));
-      if (mask & BIT_H)
-        FLAG_ASSIGN (BIT_H, (xh && mh) || (mh && !rh) || (!rh && xh));
-    }
-  else
-    {
-      if (mask & BIT_V)
-        FLAG_ASSIGN (BIT_V, ((!xt && mt) || (!xt && rt) || (xt && mt && rt)) ^ ((!xs && ms) || (!xs && rs) || (xs && ms && rs)));
-      if (mask & BIT_H)
-        FLAG_ASSIGN (BIT_H, (!xh && mh) || (!xh && rh) || (xh && mh && rh));
-      if (mask & BIT_C)
-        FLAG_ASSIGN (BIT_C, (!xt && mt) || (!xt && rt) || (xt && mt && rt));
-    }
-}
-
-#define FLAG_CVH_BYTE_ADD(x, m, r, mask) flag_cvh(x, m, r, true, true, mask)
-#define FLAG_CVH_BYTE_SUB(x, m, r, mask) flag_cvh(x, m, r, true, false, mask)
-#define FLAG_CVH_WORD_ADD(x, m, r, mask) flag_cvh(x, m, r, false, true, mask)
-#define FLAG_CVH_WORD_SUB(x, m, r, mask) flag_cvh(x, m, r, false, false, mask)
-
-int
-cl_stm8::inst_adc(t_mem code, unsigned char prefix)
-{
-  int result, operand1, operand2;
-  int carryin = !!(regs.CC & BIT_C);
-
-  operand1 = regs.A;
-  operand2 = OPERAND(code, prefix);
-  result = operand1 + operand2 + carryin;
-
-  FLAG_NZ (result);
-  FLAG_CVH_BYTE_ADD(operand1, operand2, result, BIT_C | BIT_V | BIT_H);
-
-  regs.A = result & 0xff;
-  return(resGO);
-}
-
-int
-cl_stm8::inst_add(t_mem code, unsigned char prefix)
-{
-  FLAG_CLEAR(BIT_C);
-  return inst_adc(code, prefix);
-}
-
-int
-cl_stm8::get_1(unsigned int addr)
-{
-  vc.rd++;
-  return ram->read((t_addr) (addr));
-}
-
-int
-cl_stm8::get2(unsigned int addr)
-{
-  vc.rd+= 2;
-  return((ram->read((t_addr) (addr)) << 8) | ram->read((t_addr) (addr+1)));
-}
-
-int
-cl_stm8::get3(unsigned int addr)
-{
-  vc.rd+= 3;
-  return((ram->read((t_addr) (addr)) << 16) | (ram->read((t_addr) (addr+1)) << 8) |ram->read((t_addr) (addr+2)));
-}
-
-int
-cl_stm8::inst_addw(t_mem code, unsigned char prefix)
-{
-  long int result, operand1, operand2, nibble_high, nibble_low;
-  u16_t *dest_ptr;
-  bool sub;
-
-  nibble_high = (code >> 4) & 0x0f;
-  nibble_low = code & 0x0f;
-  dest_ptr = nibble_low == 0x09 || nibble_low == 0x02 ? ®s.Y : ®s.X;
-  operand1 = *dest_ptr;
-
-  switch(nibble_high)
-  {
-    case 0x1:
-    case 0xa: operand2 = fetch2(); break; // Immediate
-    case 0xb: operand2 = get2(fetch2()); break; // Long
-    case 0xf: operand2 = get2(regs.SP + fetch()); break; // sp-indexed
-    default: return(resHALT);
-  }
-
-  switch(nibble_low)
-  {
-    case 0x0:
-    case 0x2:
-    case 0xd: sub = true; break;
-    case 0x9:
-    case 0xb:
-    case 0xc: sub = false; break;
-    default: return(resHALT);
-  }
-
-  if (sub)
-    result = operand1 - operand2;
-  else
-    result = operand1 + operand2;
-
-  FLAG_ASSIGN (BIT_N, 0x8000 & result);
-  FLAG_ASSIGN (BIT_Z, (result & 0xffff) == 0);
-  if (sub)
-    FLAG_CVH_WORD_SUB(operand1, operand2, result, BIT_C | BIT_H | BIT_V);
-  else
-    FLAG_CVH_WORD_ADD(operand1, operand2, result, BIT_C | BIT_H | BIT_V);
-
-  *dest_ptr = result & 0xffff;
-  return(resGO);
-}
-
-int
-cl_stm8::inst_and(t_mem code, unsigned char prefix)
-{
-  int result, operand1, operand2;
-
-  operand1 = regs.A;
-  operand2 = OPERAND(code, prefix);
-  result = operand1 & operand2;
-  FLAG_NZ (result);
-
-  regs.A = result & 0xff;
-  return(resGO);
-}
-
-int
-cl_stm8::inst_bccmbcpl(t_mem code, unsigned char prefix)
-{
-   int ea = fetch2();
-   unsigned char dbyte;
-   dbyte= get1( ea);
-
-   if (code & 0x01)  { // bccm
-      char pos = (code - 0x11) >> 1;
-      dbyte = dbyte & (~(1<> 1;
-      dbyte = dbyte ^ (1<> 1;
-	dbyte = dbyte & (~(1<> 1;
-	dbyte = dbyte | (1<> 1;
-	if(!( dbyte & (1<> 1;
-	if ( dbyte & (1<> 4) {
-    /* clr */
-    case 0x004: regs.A = 0; return(resGO);
-    case 0x003: opaddr = fetch(); break;
-    case 0x725: opaddr = fetch2(); break;
-    case 0x007: opaddr = regs.X; break;
-    case 0x006: opaddr = regs.X + fetch(); break;
-    case 0x724: opaddr = regs.X + fetch2(); break;
-    case 0x907: opaddr = regs.Y; break;
-    case 0x906: opaddr = regs.Y + fetch(); break;
-    case 0x904: opaddr = regs.Y + fetch2(); break;
-    case 0x000: opaddr = regs.SP + fetch(); break;
-    case 0x923: opaddr = get2(fetch()); break; // short indirect
-    case 0x723: opaddr = get2(fetch2()); break; // long indirect
-    case 0x926: opaddr = get2(fetch()) + regs.X; break; // short x-indexed indirect
-    case 0x726: opaddr = get2(fetch2()) + regs.X; break; // long x-indexed indirect
-    case 0x916: opaddr = get2(fetch()) + regs.Y; break; // short y-indexed indirect
-    /* clrw */
-    case 0x005: regs.X = 0; return(resGO);
-    case 0x905: regs.Y = 0; return(resGO);
-    default: return(resHALT);
-  }
-
-  store1(opaddr, 0);
-  return(resGO);
-}
-
-int
-cl_stm8::inst_cp(t_mem code, unsigned char prefix)
-{
-  int result, operand1, operand2;
-
-  operand1 = regs.A;
-  operand2 = OPERAND(code, prefix);
-  result = (operand1 - operand2) & 0xff;
-
-  FLAG_NZ (result);
-  FLAG_CVH_BYTE_SUB(operand1, operand2, result, BIT_C | BIT_V);
-
-  return(resGO);
-}
-
-int
-cl_stm8::inst_cpw(t_mem code, unsigned char prefix)
-{
-  long int operand1, operand2, result;
-  int reversed = 0;
-
-  operand1 = prefix == 0x90 ? regs.Y : regs.X;
-  operand2 = prefix == 0x90 ? regs.X : regs.Y;
-
-  switch((code & 0xf0) >> 4)
-  {
-    case 0xa: operand2 = fetch2(); break; // Immediate
-    case 0xb: operand2 = get2(fetch()); break; // Short
-    case 0xc:
-      switch (prefix)
-      {
-        case 0x00:
-        case 0x90: operand2 = get2(fetch2()); break; // Long direct
-        case 0x92: operand2 = get2(get2(fetch())); break; // short indirect
-        case 0x72: operand2 = get2(get2(fetch2())); break; // long indirect
-        case 0x91: operand2 = get2(get2(fetch())); operand1 = regs.Y; break; // short indirect
-        default: return(resHALT);
-      }
-      break;
-    case 0x1: operand2 = get2(regs.SP + fetch()); break; // SP-indexed
-    case 0xf: operand1 = get2(operand1); reversed = 1; break; // cpw X|Y, (Y|X)
-    case 0xe: operand1 = get2(operand1 + fetch()); reversed = 1; break; // short indexed direct
-    case 0xd:
-      switch (prefix)
-      {
-        case 0x00:
-        case 0x90: operand1 = get2(operand1 + fetch2()); break; // short indexed direct
-        case 0x91: operand1 = get2(regs.Y + get2(fetch())); operand2 = regs.X; break; // short y-indexed indirect
-        case 0x92: operand1 = get2(operand1 + get2(fetch())); break; // short x-indexed indirect
-        case 0x72: operand1 = get2(operand1 + get2(fetch2())); break; // long x-indexed indirect
-        default: return(resHALT);
-      }
-      reversed = 1;
-      break;
-    default: return(resHALT);
-  }
-
-  if (!reversed)
-    result = (operand1 - operand2) & 0xffff;
-  else
-    result = (operand2 - operand1) & 0xffff;
-
-  FLAG_ASSIGN (BIT_Z, (result & 0xffff) == 0);
-  FLAG_ASSIGN (BIT_N, 0x8000 & result);
-  if (!reversed)
-    FLAG_CVH_WORD_SUB(operand1, operand2, result, BIT_C | BIT_V);
-  else
-    FLAG_CVH_WORD_SUB(operand2, operand1, result, BIT_C | BIT_V);
-
-  return(resGO);
-}
-
-int
-cl_stm8::inst_cpl(t_mem code, unsigned char prefix)
-{
-  long int operand;
-  unsigned int opaddr = 0;
-
-   if (((code&0xf0)==0x40) &&(prefix == 0x00)) {
-      operand = regs.A;
-   } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) {
-      operand = regs.X;
-   } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) {
-      operand = regs.Y;
-   } else {
-      opaddr = get_dest(code,prefix);
-      operand = get1(opaddr);
-   }
-
-   operand ^= 0xffff;
-
-   FLAG_SET (BIT_C);
-
-   if (((code&0xf0)==0x40) &&(prefix == 0x00)) {
-      regs.A = operand&0xff;
-      FLAG_ASSIGN (BIT_Z, (operand & 0xff) == 0);
-      FLAG_ASSIGN (BIT_N, 0x80 & operand);
-   } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) {
-      regs.X = operand & 0xffff;
-      FLAG_ASSIGN (BIT_Z, (operand & 0xffff) == 0);
-      FLAG_ASSIGN (BIT_N, 0x8000 & operand);
-   } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) {
-      regs.Y = operand & 0xffff;
-      FLAG_ASSIGN (BIT_Z, (operand & 0xffff) == 0);
-      FLAG_ASSIGN (BIT_N, 0x8000 & operand);
-   } else {
-      store1(opaddr, operand &0xff);
-      FLAG_ASSIGN (BIT_Z, (operand & 0xff) == 0);
-      FLAG_ASSIGN (BIT_N, 0x80 & operand);
-   }
-
-   return(resGO);
-}
-
-int
-cl_stm8::inst_dec(t_mem code, unsigned char prefix)
-{
-  long int operand, resval;
-  unsigned int opaddr = 0;
-
-   if (((code&0xf0)==0x40) &&(prefix == 0x00)) {
-      operand = regs.A;
-   } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) {
-      operand = regs.X;
-   } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) {
-      operand = regs.Y;
-   } else {
-      opaddr = get_dest(code,prefix);
-      operand = get1(opaddr);
-   }
-
-   resval = operand - 1;
-
-   if (((code&0xf0)==0x40) &&(prefix == 0x00)) {
-      regs.A = resval&0xff;
-      FLAG_ASSIGN (BIT_Z, (resval & 0xff) == 0);
-      FLAG_ASSIGN (BIT_N, 0x80 & resval);
-      FLAG_CVH_BYTE_ADD(operand, 0xff, resval, BIT_V);
-   } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) {
-      regs.X = resval & 0xffff;
-      FLAG_ASSIGN (BIT_Z, (resval & 0xffff) == 0);
-      FLAG_ASSIGN (BIT_N, 0x8000 & resval);
-      FLAG_CVH_WORD_ADD(operand, 0xffff, resval, BIT_V);
-   } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) {
-      regs.Y = resval & 0xffff;
-      FLAG_ASSIGN (BIT_Z, (resval & 0xffff) == 0);
-      FLAG_ASSIGN (BIT_N, 0x8000 & resval);
-      FLAG_CVH_WORD_ADD(operand, 0xffff, resval, BIT_V);
-   } else {
-      store1(opaddr, resval &0xff);
-      FLAG_ASSIGN (BIT_Z, (resval & 0xff) == 0);
-      FLAG_ASSIGN (BIT_N, 0x80 & resval);
-      FLAG_CVH_BYTE_ADD(operand, 0xff, resval, BIT_V);
-   }
-
-   return(resGO);
-}
-
-int
-cl_stm8::inst_div(t_mem code, unsigned char prefix)
-{
-   unsigned int quot, remi;
-
-   FLAG_CLEAR(BIT_N);
-   FLAG_CLEAR(BIT_H);
-   FLAG_CLEAR(BIT_V);
-
-   if( code == 0x65) { // divw
-      if (regs.Y == 0x00) {
-         FLAG_SET(BIT_C);
-      } else {
-         FLAG_CLEAR(BIT_C);
-         quot = regs.X / regs.Y;
-         remi = regs.X % regs.Y;
-         regs.X = quot;
-         regs.Y = remi;
-         FLAG_ASSIGN (BIT_Z, (quot & 0xffff) == 0);
-      }
-   } else { //div
-      if (regs.A == 0x00) {
-         FLAG_SET(BIT_C);
-      } else {
-         FLAG_CLEAR(BIT_C);
-         if (prefix == 0x00) {
-            quot = regs.X / regs.A;
-            remi = regs.X % regs.A;
-            regs.X = quot;
-            regs.A = remi;
-         } else if (prefix == 0x90) {
-            quot = regs.Y / regs.A;
-            remi = regs.Y % regs.A;
-            regs.Y = quot;
-            regs.A = remi;
-         } else {
-            return (resHALT);
-         }
-         FLAG_ASSIGN (BIT_Z, (quot & 0xffff) == 0);
-      }
-   }
-
-  return(resGO);
-}
-
-int
-cl_stm8::inst_inc(t_mem code, unsigned char prefix)
-{
-  long int operand, resval;
-  unsigned int opaddr = 0;
-
-   if (((code&0xf0)==0x40) &&(prefix == 0x00)) {
-      operand = regs.A;
-   } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) {
-      operand = regs.X;
-   } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) {
-      operand = regs.Y;
-   } else {
-      opaddr = get_dest(code,prefix);
-      operand = get1(opaddr);
-   }
-
-   resval = operand + 1;
-
-   if (((code&0xf0)==0x40) &&(prefix == 0x00)) {
-      regs.A = resval&0xff;
-      FLAG_ASSIGN (BIT_Z, (resval & 0xff) == 0);
-      FLAG_ASSIGN (BIT_N, 0x80 & resval);
-      FLAG_CVH_BYTE_ADD(operand, 0x01, resval, BIT_V);
-   } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) {
-      regs.X = resval & 0xffff;
-      FLAG_ASSIGN (BIT_Z, (resval & 0xffff) == 0);
-      FLAG_ASSIGN (BIT_N, 0x8000 & resval);
-      FLAG_CVH_WORD_ADD(operand, 0x0001, resval, BIT_V);
-   } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) {
-      regs.Y = resval & 0xffff;
-      FLAG_ASSIGN (BIT_Z, (resval & 0xffff) == 0);
-      FLAG_ASSIGN (BIT_N, 0x8000 & resval);
-      FLAG_CVH_WORD_ADD(operand, 0x0001, resval, BIT_V);
-   } else {
-      store1(opaddr, resval &0xff);
-      FLAG_ASSIGN (BIT_Z, (resval & 0xff) == 0);
-      FLAG_ASSIGN (BIT_N, 0x80 & resval);
-      FLAG_CVH_BYTE_ADD(operand, 0x01, resval, BIT_V);
-   }
-
-   return(resGO);
-}
-
-int
-cl_stm8::inst_jp(t_mem code, unsigned char prefix)
-{
-  t_addr newPC = (PC & 0xff0000ul) + fetchea(code, prefix);
-  PC = newPC;
-  return(resGO);
-}
-
-int
-cl_stm8::inst_jr(t_mem code, unsigned char prefix)
-{
-  bool taken;
-  signed char ofs;
-  unsigned char bz, bn, bv;
-
-  if (prefix ==0x00) {
-    switch ((code>>1) & 7) {
-      case 0: // JRT - JRA (20) / JRF (21)
-        taken = 1;
-        break;
-      case 1: // JRUGT (22) / JRULE (23)
-        taken = !(regs.CC & (BIT_C | BIT_Z));
-        break;
-      case 2: // JRUGE (24) / JRULT (25)
-        taken = !(regs.CC & BIT_C);
-        break;
-      case 3: // JRNE (26) / JREQ (27)
-        taken = !(regs.CC & BIT_Z);
-        break;
-      case 4: // JRNV (28) / JRV (29)
-        taken = !(regs.CC & BIT_V);
-        break;
-      case 5: // JRPL (2A) / JRMI (2B)
-        taken = !(regs.CC & BIT_N);
-        break;
-      case 6: // JRSGT (2C) - Z or (N xor V) = 0 / JRSLE (2D) - Z or (N xor V) = 1
-        bz = !!(regs.CC & BIT_Z);
-        bn = !!(regs.CC & BIT_N);
-        bv = !!(regs.CC & BIT_V);
-        taken = !(bz | (bn ^ bv));
-        break;
-      case 7: // JRSGE (2E) - N xor V = 0 / / JRSLT(2F) N xor V = 1
-        bn = !!(regs.CC & BIT_N);
-        bv = !!(regs.CC & BIT_V);
-        taken = !(bn ^ bv);
-        break;
-      default:
-        return(resHALT);
-    }
-  }
-  else if (prefix==0x90) {
-    switch ((code>>1) & 7) {
-      case 4: // JRNH (28) / JRH (29)
-         taken = !(regs.CC & BIT_H);
-       break;
-      case 6: // JRNM (2C) / JRM (2D)
-        taken = !(regs.CC & (BIT_I1|BIT_I0));
+/*
+ * Simulator of microcontrollers (inst.cc)
+ *
+ * stm8 code base from Vaclav Peroutka vaclavpe@users.sourceforge.net
+ * and Valentin Dudouyt valentin.dudouyt@gmail.com
+ *
+ * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
+ *
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+//#include "ddconfig.h"
+
+#include 
+//#include 
+
+// local
+#include "stm8cl.h"
+//#include "regsstm8.h"
+#include "stm8mac.h"
+
+int
+cl_stm8::fetchea(t_mem code, unsigned char prefix)
+{
+   int ret = resHALT;
+   int ftc;
+
+   switch ((code >> 4) & 0x0f) {
+   case 0x1: {
+     unsigned char index = fetch();
+     get_regs();
+     ret = index+regs.SP;  // SP indexed
+     break;
+   }
+
+   case 0xb:
+     ret = fetch();           // direct short
+     break;
+
+
+   case 0xc:
+      if ( 0 == prefix) {              // direct long
+         ret = fetch2();
+      } else if ( 0x72 == prefix) {    // long pointer
+         ftc = fetch2();
+         ret = get2(ftc);
+         decode_cycle();
+      } else if ( 0x92 == prefix) {    // short pointer
+         ftc = fetch();
+         ret = get2(ftc);
+         decode_cycle();
+      }
+      break;
+
+   case 0xd:
+      if ( 0 == prefix) {              // long offset with X reg
+         int offset = fetch2();
+         get_regs();
+         ret = offset+regs.X;
+      } else if ( 0x72 == prefix) {    // long pointer to offset with X reg
+         ftc = get2(fetch2());
+         decode_cycle();
+         ret = ftc+regs.X;
+      } else if ( 0x90 == prefix) {    // long offset with Y reg
+         int offset = fetch2();
+         get_regs();
+         ret = offset+regs.Y;
+      } else if ( 0x91 == prefix) {    // short pointer to offset with Y reg
+         ftc = get2(fetch());
+         decode_cycle();
+         ret = ftc+regs.Y;
+      } else if ( 0x92 == prefix) {    // short pointer to offset with X reg
+         ftc = get2(fetch());
+         decode_cycle();
+         ret = ftc+regs.X;
+      }
+      break;
+
+
+   case 0xe: {
+      int offset = fetch();
+      get_regs();
+      if ( 0 == prefix) {               // short offset with X reg
+         ret = offset+regs.X;
+      } else if ( 0x90 == prefix) {     // short offset with Y reg
+         ret = offset+regs.Y;
+      }
+      break;
+   }
+
+   case 0xf:
+      get_regs();
+      if ( 0 == prefix) {               // X index
+         ret = regs.X;
+      } else if ( 0x90 == prefix) {     // Y index
+         ret = regs.Y;
+      }
+      break;
+   }
+
+   return ret;
+}
+
+int
+cl_stm8::get_dest(t_mem code, unsigned char prefix)
+{
+  int resaddr, ftc;
+
+  switch ((code >> 4) & 0x0f) {
+    case 0x0:
+	  if ( 0 == prefix) {              // short offset with SP
+		 resaddr = fetch();
+		 get_regs();
+		 resaddr += regs.SP;
+	  } else {
+	    resaddr = ( resHALT);
+	  }
+     break;
+
+    case 0x3:
+	  if ( 0 == prefix) {              // short direct
+		 resaddr = fetch();
+     } else if ( 0x72 == prefix) {    // long indirect - pointer
+         ftc = fetch2();
+         resaddr = get2(ftc);
+         decode_cycle();
+     } else if ( 0x92 == prefix) {    // short indirect - pointer
+         ftc = fetch();
+         resaddr = get2(ftc);
+         decode_cycle();
+	  } else {
+	    resaddr = ( resHALT);
+	  }
+     break;
+
+    case 0x4:
+	  if ( 0x72 == prefix) {           // long offset with X
+         ftc = fetch2();
+         get_regs();
+         resaddr = ftc + regs.X;
+     } else if ( 0x90 == prefix) {    // long offset with Y
+         ftc = fetch2();
+         get_regs();
+         resaddr = ftc + regs.Y;
+	  } else {
+         resaddr = ( resHALT);
+	  }
+     break;
+
+    case 0x5:
+	  if ( 0x72 == prefix) {           // long direct
+         resaddr = fetch2();
+	  } else {
+         resaddr = ( resHALT);
+	  }
+     break;
+
+    case 0x6:
+          if ( 0 == prefix) {              // short offset with X
+		resaddr = fetch();
+		get_regs();
+		resaddr += regs.X;
+	  } else if ( 0x72 == prefix) {    // long pointer to offset with X
+          ftc = get2(fetch2());
+          decode_cycle();
+	  resaddr = ftc+regs.X;
+	  } else if ( 0x90 == prefix) {    // short offset with Y
+	    resaddr = fetch();
+	    get_regs();
+	    resaddr += regs.Y;
+	  } else if ( 0x91 == prefix) {    // short pointer to offset with Y
+          ftc = get2(fetch());
+          decode_cycle();
+	    resaddr = ftc+regs.Y;
+	  } else if ( 0x92 == prefix) {    // short pointer to offset with X
+          ftc = get2(fetch());
+          decode_cycle();
+	    resaddr = ftc+regs.X;
+	  } else {
+	    resaddr =( resHALT);
+	  }
+     break;
+
+    case 0x7:
+	  if ( 0 == prefix) {              // X index
+		get_regs();
+		resaddr = regs.X;
+	  } else if ( 0x90 == prefix) {    // Y index
+	    get_regs();
+	    resaddr = regs.Y;
+	  } else {
+	    resaddr =( resHALT);
+	  }
+     break;
+
+    default:
+      resaddr =(resHALT);
+      break;
+  }
+
+  return resaddr;
+}
+
+void
+cl_stm8::flag_cvh(int x, int m, int r, bool byte, bool add, int mask)
+{
+  bool xt, xs, xh, mt, ms, mh, rt, rs, rh;
+
+  if (byte)
+    {
+      xt = !!(x & 0x80);
+      xs = !!(x & 0x40);
+      xh = !!(x & 0x08);
+      mt = !!(m & 0x80);
+      ms = !!(m & 0x40);
+      mh = !!(m & 0x08);
+      rt = !!(r & 0x80);
+      rs = !!(r & 0x40);
+      rh = !!(r & 0x08);
+    }
+  else
+    {
+      xt = !!(x & 0x8000);
+      xs = !!(x & 0x4000);
+      xh = !!(x & 0x0080);
+      mt = !!(m & 0x8000);
+      ms = !!(m & 0x4000);
+      mh = !!(m & 0x0080);
+      rt = !!(r & 0x8000);
+      rs = !!(r & 0x4000);
+      rh = !!(r & 0x0080);
+    }
+
+  if (add)
+    {
+      if (mask & BIT_V)
+        FLAG_ASSIGN (BIT_V, ((xt && mt) || (mt && !rt) || (!rt && xt)) ^ ((xs && ms) || (ms && !rs) || (!rs && xs)));
+      if (mask & BIT_C)
+        FLAG_ASSIGN (BIT_C, (xt && mt) || (mt && !rt) || (!rt && xt));
+      if (mask & BIT_H)
+        FLAG_ASSIGN (BIT_H, (xh && mh) || (mh && !rh) || (!rh && xh));
+    }
+  else
+    {
+      if (mask & BIT_V)
+        FLAG_ASSIGN (BIT_V, ((!xt && mt) || (!xt && rt) || (xt && mt && rt)) ^ ((!xs && ms) || (!xs && rs) || (xs && ms && rs)));
+      if (mask & BIT_H)
+        FLAG_ASSIGN (BIT_H, (!xh && mh) || (!xh && rh) || (xh && mh && rh));
+      if (mask & BIT_C)
+        FLAG_ASSIGN (BIT_C, (!xt && mt) || (!xt && rt) || (xt && mt && rt));
+    }
+}
+
+#define FLAG_CVH_BYTE_ADD(x, m, r, mask) flag_cvh(x, m, r, true, true, mask)
+#define FLAG_CVH_BYTE_SUB(x, m, r, mask) flag_cvh(x, m, r, true, false, mask)
+#define FLAG_CVH_WORD_ADD(x, m, r, mask) flag_cvh(x, m, r, false, true, mask)
+#define FLAG_CVH_WORD_SUB(x, m, r, mask) flag_cvh(x, m, r, false, false, mask)
+
+int
+cl_stm8::inst_adc(t_mem code, unsigned char prefix)
+{
+  int result, operand1, operand2;
+  int carryin = !!(regs.CC & BIT_C);
+
+  operand1 = regs.A;
+  operand2 = OPERAND(code, prefix);
+  result = operand1 + operand2 + carryin;
+
+  store_regs();
+
+  FLAG_NZ (result);
+  FLAG_CVH_BYTE_ADD(operand1, operand2, result, BIT_C | BIT_V | BIT_H);
+
+  regs.A = result & 0xff;
+  return(resGO);
+}
+
+int
+cl_stm8::inst_add(t_mem code, unsigned char prefix)
+{
+  FLAG_CLEAR(BIT_C);
+  return inst_adc(code, prefix);
+}
+
+void
+cl_stm8::pipeline_flush(bool need_exec)
+{
+  pipetrace_type("X");
+
+  if (!pipeline_busy.instr)
+    pipeline_busy.instr = true;
+
+  pipeline_index = PC & 3;
+  pipeline_bytes = 0;
+
+  // Suppress all fetches in the flush cycle
+  pipeline_busy.program = pipeline_busy.data = true;
+
+  if (need_exec)
+    exec_cycle();
+
+  pipeline_busy.flush = true;
+
+  if (pipetrace_fold)
+    pipetrace_ticks = 0;
+}
+
+void
+cl_stm8::decode_cycle(void)
+{
+  tick(1);
+  pipetrace_type("D");
+  //pipeline_busy.instr = true;
+}
+
+void
+cl_stm8::get_regs(void)
+{
+  if (pipeline_busy.regs)
+    {
+      error(new cl_error_stm8_pipeline_fetch_stall());
+      pipetrace_type("Sraw");
+      decode_cycle();
+    }
+
+  //pipeline_busy.instr = true;
+  //pipeline_busy.regs = true;
+}
+
+int
+cl_stm8::get_1(unsigned int addr)
+{
+  class cl_address_decoder *d = rom->get_decoder_of(addr);
+  bool *busy = (d && d->memchip != flash_chip ? &pipeline_busy.data : &pipeline_busy.program);
+
+  if (*busy && !pipeline_busy.instr)
+    pipetrace_type("Sbus");
+
+  if (*busy || pipeline_busy.instr)
+    decode_cycle();
+
+  pipeline_busy.instr = true;
+
+  vc.rd++;
+  int v = ram->read((t_addr) (addr));
+  *busy = true;
+
+  return v;
+}
+
+int
+cl_stm8::get2(unsigned int addr)
+{
+  class cl_address_decoder *d = rom->get_decoder_of(addr);
+  bool *busy = (d && d->memchip != flash_chip ? &pipeline_busy.data : &pipeline_busy.program);
+
+  if (*busy && !pipeline_busy.instr)
+    pipetrace_type("Sbus");
+
+  if (*busy || pipeline_busy.instr)
+    decode_cycle();
+
+  pipeline_busy.instr = true;
+
+  vc.rd++;
+  int lo = ram->read((t_addr)addr+1);
+  *busy = true;
+
+  decode_cycle();
+
+  vc.rd++;
+  int hi = ram->read((t_addr)addr);
+  *busy = true;
+
+  return((hi << 8) | lo);
+}
+
+int
+cl_stm8::get3(unsigned int addr)
+{
+  class cl_address_decoder *d = rom->get_decoder_of(addr);
+  bool *busy = (d && d->memchip != flash_chip ? &pipeline_busy.data : &pipeline_busy.program);
+
+  if (*busy && !pipeline_busy.instr)
+    pipetrace_type("Sbus");
+
+  if (*busy || pipeline_busy.instr)
+    decode_cycle();
+
+  pipeline_busy.instr = true;
+
+  vc.rd++;
+  int lo = ram->read((t_addr)addr+2);
+  *busy = true;
+
+  decode_cycle();
+
+  vc.rd++;
+  int hi = ram->read((t_addr)addr+1);
+  *busy = true;
+
+  decode_cycle();
+
+  vc.rd++;
+  int ex = ram->read((t_addr)addr);
+  *busy = true;
+
+  return((ex << 16) | (hi << 8) | lo);
+}
+
+void
+cl_stm8::exec_cycle(void)
+{
+  // Fully consumed 32bit words in the prefetch buffer are discarded
+  // once we pass into the execute phase.
+  // Note that the discard happens early enough that a fetch can happen
+  // in the decode cycle (as seen in PM0044 table 6).
+  pipeline_bytes -= pipeline_index & (~3);
+  pipeline_index &= 3;
+
+  tick(1);
+  pipetrace_type("E");
+  pipeline_busy.instr = true;
+}
+
+void
+cl_stm8::store_regs(void)
+{
+  exec_cycle();
+  pipeline_busy.regs = true;
+}
+
+void
+cl_stm8::store1(unsigned int addr, unsigned int val)
+{
+  class cl_address_decoder *d = rom->get_decoder_of(addr);
+  bool *busy = (d && d->memchip != flash_chip ? &pipeline_busy.data : &pipeline_busy.program);
+
+  exec_cycle();
+  vc.wr++;
+  ram->write((t_addr) (addr), val);
+  *busy = true;
+}
+
+void
+cl_stm8::store2(unsigned int addr, unsigned int val)
+{
+  class cl_address_decoder *d = rom->get_decoder_of(addr);
+  bool *busy = (d && d->memchip != flash_chip ? &pipeline_busy.data : &pipeline_busy.program);
+
+  // RM0016 17.3.3 Prescalar
+  // "Do not use the LDW instruction for this purpose as it writes the LSB first"
+  //
+  // Writing words LSB first allows any second ALU cycle to be overlapped
+  // with the write of the LSB effectively reducing the cycle count by one
+  // for word-wide arithmetic operations.
+  exec_cycle();
+  vc.wr++;
+  ram->write((t_addr)addr+1, val & 0xff);
+  *busy = true;
+
+  exec_cycle();
+  vc.wr++;
+  ram->write((t_addr)addr, (val >> 8) & 0xff);
+  *busy = true;
+}
+
+int
+cl_stm8::inst_addw(t_mem code, unsigned char prefix)
+{
+  long int result, operand1, operand2, nibble_high, nibble_low;
+  u16_t *dest_ptr;
+  bool sub;
+
+  nibble_high = (code >> 4) & 0x0f;
+  nibble_low = code & 0x0f;
+  dest_ptr = nibble_low == 0x09 || nibble_low == 0x02 ? ®s.Y : ®s.X;
+  operand1 = *dest_ptr;
+
+  switch(nibble_high)
+  {
+    case 0x1:
+    case 0xa: // Immediate
+      {
+        operand2 = fetch2();
+        // We have the data so we only need two ALU execution cycles
+        // but cannot overlap the first with the previous decode cycle.
+        exec_cycle();
+        break;
+      }
+    case 0xb: // Long
+      {
+        operand2 = get2(fetch2());
+        // The data is fetched LSB first and the first ALU execution
+        // overlaps with the MSB fetch so we only have the final ALU
+        // execution to account for.
+        break;
+      }
+    case 0xf: // sp-indexed
+      {
+        operand2 = get2(regs.SP + fetch());
+        // The data is fetched LSB first and the first ALU execution
+        // overlaps with the MSB fetch so we only have the final ALU
+        // execution to account for.
+        break;
+      }
+    default: return(resHALT);
+  }
+
+  switch(nibble_low)
+  {
+    case 0x0:
+    case 0x2:
+    case 0xd: sub = true; break;
+    case 0x9:
+    case 0xb:
+    case 0xc: sub = false; break;
+    default: return(resHALT);
+  }
+
+  if (sub)
+    result = operand1 - operand2;
+  else
+    result = operand1 + operand2;
+
+  store_regs();
+
+  FLAG_ASSIGN (BIT_N, 0x8000 & result);
+  FLAG_ASSIGN (BIT_Z, (result & 0xffff) == 0);
+  if (sub)
+    FLAG_CVH_WORD_SUB(operand1, operand2, result, BIT_C | BIT_H | BIT_V);
+  else
+    FLAG_CVH_WORD_ADD(operand1, operand2, result, BIT_C | BIT_H | BIT_V);
+
+  *dest_ptr = result & 0xffff;
+  return(resGO);
+}
+
+int
+cl_stm8::inst_and(t_mem code, unsigned char prefix)
+{
+  int result, operand1, operand2;
+
+  operand1 = regs.A;
+  operand2 = OPERAND(code, prefix);
+
+  store_regs();
+  result = operand1 & operand2;
+  FLAG_NZ (result);
+
+  regs.A = result & 0xff;
+  return(resGO);
+}
+
+int
+cl_stm8::inst_bccmbcpl(t_mem code, unsigned char prefix)
+{
+   int ea = fetch2();
+   unsigned char dbyte;
+   dbyte= get1( ea);
+
+   if (code & 0x01)  { // bccm
+      char pos = (code - 0x11) >> 1;
+      dbyte = dbyte & (~(1<> 1;
+      dbyte = dbyte ^ (1<> 1;
+	dbyte = dbyte & (~(1<> 1;
+	dbyte = dbyte | (1<> 1; // No need to pick out bits 3:1 - the others are all 0
+  unsigned char dbyte = get1(ea);
+
+  store_regs();
+
+  FLAG_ASSIGN(BIT_C, (dbyte >> pos) & 1);
+
+  if ((regs.CC & BIT_C) ^ (code & 1)) { // Bit 0 of code selects branch on true (0) or false (1)
+    PC += reljump;
+
+    // PM0044 5.4.3 Pipeline with Call/Jump
+    // For a JP instruction, the fetch [of the next instruction] can start
+    // during the first cycle of the "dummy" execution.
+    pipeline_flush(true);
+  }
+
+  return(resGO);
+}
+
+int
+cl_stm8::inst_call(t_mem code, unsigned char prefix)
+{
+  t_addr newPC = (PC & 0xff0000ul) + fetchea(code, prefix);
+  push2(PC);
+  // PM0044 5.4.3 Pipeline with Call/Jump
+  // "For the CALL instruction, it [the fetch of the next instruction] starts
+  // after the last cycle of the CALL execution."
+  PC = newPC;
+  pipeline_flush(false);
+
+  return(resGO);
+}
+
+int
+cl_stm8::inst_clr(t_mem code, unsigned char prefix)
+{
+  unsigned int opaddr = 0;
+
+
+  FLAG_SET (BIT_Z);
+  FLAG_CLEAR (BIT_N);
+
+  switch(((code & 0xf0) | (prefix << 8)) >> 4) {
+    /* clr */
+    case 0x004: regs.A = 0; return(resGO);
+    case 0x003: opaddr = fetch(); break;
+    case 0x725: opaddr = fetch2(); break;
+    case 0x007: get_regs(); opaddr = regs.X; break;
+    case 0x006: opaddr = fetch(); get_regs(); opaddr += regs.X; break;
+    case 0x724: opaddr = fetch2(); get_regs(); opaddr += regs.X; break;
+    case 0x907: get_regs(); opaddr = regs.Y; break;
+    case 0x906: opaddr = fetch(); get_regs(); opaddr += regs.Y; break;
+    case 0x904: opaddr = fetch2(); get_regs(); opaddr += regs.Y; break;
+    case 0x000: opaddr = fetch(); get_regs(); opaddr += regs.SP; break;
+    case 0x923: opaddr = get2(fetch()); decode_cycle(); break; // short indirect
+    case 0x723: opaddr = get2(fetch2()); decode_cycle(); break; // long indirect
+    case 0x926: opaddr = get2(fetch()); decode_cycle(); opaddr += regs.X; break; // short x-indexed indirect
+    case 0x726: opaddr = get2(fetch2()); decode_cycle(); opaddr += regs.X; break; // long x-indexed indirect
+    case 0x916: opaddr = get2(fetch()); decode_cycle(); opaddr += regs.Y; break; // short y-indexed indirect
+    /* clrw */
+    case 0x005: regs.X = 0; exec_cycle(); return(resGO);
+    case 0x905: regs.Y = 0; exec_cycle(); return(resGO);
+    default: return(resHALT);
+  }
+
+  get1(opaddr);
+  store1(opaddr, 0);
+  return(resGO);
+}
+
+int
+cl_stm8::inst_cp(t_mem code, unsigned char prefix)
+{
+  int result, operand1, operand2;
+
+  operand1 = regs.A;
+  operand2 = OPERAND(code, prefix);
+
+  store_regs();
+
+  result = (operand1 - operand2) & 0xff;
+
+  FLAG_NZ (result);
+  FLAG_CVH_BYTE_SUB(operand1, operand2, result, BIT_C | BIT_V);
+
+  return(resGO);
+}
+
+int
+cl_stm8::inst_cpw(t_mem code, unsigned char prefix)
+{
+  long int operand1, operand2, result;
+  int reversed = 0;
+
+  operand1 = prefix == 0x90 ? regs.Y : regs.X;
+  operand2 = prefix == 0x90 ? regs.X : regs.Y;
+
+  switch((code & 0xf0) >> 4)
+  {
+    case 0xa: operand2 = fetch2(); exec_cycle(); break; // Immediate
+    case 0xb: operand2 = get2(fetch()); break; // Short
+    case 0xc:
+      switch (prefix)
+      {
+        case 0x00:
+        case 0x90: operand2 = get2(fetch2()); break; // Long direct
+        case 0x92: operand2 = get2(fetch()); decode_cycle(); operand2 = get2(operand2); break; // short indirect
+        case 0x72: operand2 = get2(fetch2()); decode_cycle(); operand2 = get2(operand2); break; // long indirect
+        case 0x91: operand2 = get2(fetch()); decode_cycle(); operand2 = get2(operand2); operand1 = regs.Y; break; // short indirect
+        default: return(resHALT);
+      }
+      break;
+    case 0x1: operand2 = get2(fetch() + regs.SP); break; // SP-indexed
+    case 0xf: get_regs(); operand1 = get2(operand1); reversed = 1; break; // cpw X|Y, (Y|X)
+    case 0xe: get_regs(); operand1 = get2(operand1 + fetch()); reversed = 1; break; // short indexed direct
+    case 0xd:
+      switch (prefix)
+      {
+        case 0x00:
+        case 0x90: get_regs(); operand1 = get2(fetch2() + operand1); break; // short indexed direct
+        case 0x91: operand1 = regs.Y + get2(fetch()); decode_cycle(); operand1 = get2(operand1); operand2 = regs.X; break; // short y-indexed indirect
+        case 0x92: { operand1 += get2(fetch()); decode_cycle(); operand1 = get2(operand1); break; } // short x-indexed indirect
+        case 0x72: { operand1 += get2(fetch2()); decode_cycle(); operand1 = get2(operand1); break; } // long x-indexed indirect
+        default: return(resHALT);
+      }
+      reversed = 1;
+      break;
+    default: return(resHALT);
+  }
+
+  if (!reversed)
+    result = (operand1 - operand2) & 0xffff;
+  else
+    result = (operand2 - operand1) & 0xffff;
+
+  store_regs();
+
+  FLAG_ASSIGN (BIT_Z, (result & 0xffff) == 0);
+  FLAG_ASSIGN (BIT_N, 0x8000 & result);
+  if (!reversed)
+    FLAG_CVH_WORD_SUB(operand1, operand2, result, BIT_C | BIT_V);
+  else
+    FLAG_CVH_WORD_SUB(operand2, operand1, result, BIT_C | BIT_V);
+
+  return(resGO);
+}
+
+int
+cl_stm8::inst_cpl(t_mem code, unsigned char prefix)
+{
+  long int operand;
+  unsigned int opaddr = 0;
+
+   if (((code&0xf0)==0x40) &&(prefix == 0x00)) {
+      operand = regs.A;
+   } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) {
+      operand = regs.X;
+   } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) {
+      operand = regs.Y;
+   } else {
+      opaddr = get_dest(code,prefix);
+      operand = get1(opaddr);
+   }
+
+   operand ^= 0xffff;
+
+   FLAG_SET (BIT_C);
+
+   if (((code&0xf0)==0x40) &&(prefix == 0x00)) {
+      store_regs();
+      regs.A = operand&0xff;
+      FLAG_ASSIGN (BIT_Z, (operand & 0xff) == 0);
+      FLAG_ASSIGN (BIT_N, 0x80 & operand);
+   } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) {
+      exec_cycle();
+      store_regs();
+      regs.X = operand & 0xffff;
+      FLAG_ASSIGN (BIT_Z, (operand & 0xffff) == 0);
+      FLAG_ASSIGN (BIT_N, 0x8000 & operand);
+   } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) {
+      exec_cycle();
+      store_regs();
+      regs.Y = operand & 0xffff;
+      FLAG_ASSIGN (BIT_Z, (operand & 0xffff) == 0);
+      FLAG_ASSIGN (BIT_N, 0x8000 & operand);
+   } else {
+      store1(opaddr, operand &0xff);
+      FLAG_ASSIGN (BIT_Z, (operand & 0xff) == 0);
+      FLAG_ASSIGN (BIT_N, 0x80 & operand);
+   }
+
+   return(resGO);
+}
+
+int
+cl_stm8::inst_dec(t_mem code, unsigned char prefix)
+{
+  long int operand, resval;
+  unsigned int opaddr = 0;
+
+   if (((code&0xf0)==0x40) &&(prefix == 0x00)) {
+      operand = regs.A;
+   } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) {
+      operand = regs.X;
+   } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) {
+      operand = regs.Y;
+   } else {
+      opaddr = get_dest(code,prefix);
+      operand = get1(opaddr);
+   }
+
+   resval = operand - 1;
+
+   if (((code&0xf0)==0x40) &&(prefix == 0x00)) {
+      store_regs();
+      regs.A = resval&0xff;
+      FLAG_ASSIGN (BIT_Z, (resval & 0xff) == 0);
+      FLAG_ASSIGN (BIT_N, 0x80 & resval);
+      FLAG_CVH_BYTE_ADD(operand, 0xff, resval, BIT_V);
+   } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) {
+      store_regs();
+      regs.X = resval & 0xffff;
+      FLAG_ASSIGN (BIT_Z, (resval & 0xffff) == 0);
+      FLAG_ASSIGN (BIT_N, 0x8000 & resval);
+      FLAG_CVH_WORD_ADD(operand, 0xffff, resval, BIT_V);
+   } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) {
+      store_regs();
+      regs.Y = resval & 0xffff;
+      FLAG_ASSIGN (BIT_Z, (resval & 0xffff) == 0);
+      FLAG_ASSIGN (BIT_N, 0x8000 & resval);
+      FLAG_CVH_WORD_ADD(operand, 0xffff, resval, BIT_V);
+   } else {
+      store1(opaddr, resval &0xff);
+      FLAG_ASSIGN (BIT_Z, (resval & 0xff) == 0);
+      FLAG_ASSIGN (BIT_N, 0x80 & resval);
+      FLAG_CVH_BYTE_ADD(operand, 0xff, resval, BIT_V);
+   }
+
+   return(resGO);
+}
+
+int
+cl_stm8::inst_div(t_mem code, unsigned char prefix)
+{
+  if (div_cycle == 0) { // Starting or restarting a division
+    dividend = regs.X;
+    divisor = regs.A;
+    if (code == 0x65)
+      divisor = regs.Y;
+    else if (prefix == 0x90)
+      dividend = regs.Y;
+    else if (prefix != 0x00)
+      return resINV_INST;
+
+    //printf("init:   ");
+    //for (int i = 31; i >= 0; i--)
+    //  printf("%c%s", (dividend & (1 << i)) ? '1' : '0', (i % 4) == 0 ? " " : "");
+    //printf(" / ");
+    //for (int i = 15; i >= 0; i--)
+    //  printf("%c%s", (divisor & (1 << i)) ? '1' : '0', (i % 4) == 0 ? " " : "");
+    //printf(" (%u / %u)\n", dividend, divisor);
+
+    store_regs();
+    FLAG_CLEAR(BIT_C);
+
+    if (divisor == 0x00) {
+      FLAG_SET(BIT_C);
+      return resGO;
+    }
+
+    div_cycle = 16;
+
+    PC = instPC;
+    return resNOT_DONE;
+  }
+
+#if 0
+  // SRT division
+
+  exec_cycle();
+  while (--div_cycle && ((dividend & 0xe0000000) == 0 || (dividend & 0x0e0000000) == 0x0e0000000))
+    dividend <<= 1;
+
+  if (div_cycle) {
+    if ((dividend & 0x80000000) == 0x80000000) {
+      quotient = quotient - (1 << div_cycle);
+      dividend <<= 1;
+      dividend = (((dividend >> 16) + divisor) << 16) | (dividend & 0xffff);
+    } else {
+      quotient |= (1 << div_cycle);
+      dividend <<= 1;
+      dividend = (((dividend >> 16) - divisor) << 16) | (dividend & 0xffff);
+    }
+  }
+  //printf("%2d: ", div_cycle);
+  //for (int i = 31; i >= 0; i--)
+  //  printf("%c%s", (dividend & (1 << i)) ? '1' : '0', (i % 4) == 0 ? " " : "");
+  //printf("\n");
+
+  if (div_cycle == 0) {
+    if ((dividend & 0x80000000) == 0x80000000) {
+      dividend = ((dividend >> 16) + divisor) << 16;
+      quotient--;
+    }
+    dividend |= quotient;
+  }
+#else
+  // Restoring algorithm with collapsed shifting
+
+  exec_cycle();
+  while (div_cycle) {
+    div_cycle--;
+
+    dividend <<= 1;
+
+    //printf("%2d: << 1: ", div_cycle);
+    //for (int i = 31; i >= 0; i--)
+    //  printf("%c%s", (dividend & (1 << i)) ? '1' : '0', (i % 4) == 0 ? " " : "");
+    //printf("\n");
+
+    if ((dividend >> 16) >= divisor) {
+      dividend = (((dividend >> 16) - divisor) << 16) | (dividend & 0xffff) | 1;
+
+      //printf("%2d: sub : ", div_cycle);
+      //for (int i = 31; i >= 0; i--)
+      //  printf("%c%s", (dividend & (1 << i)) ? '1' : '0', (i % 4) == 0 ? " " : "");
+      //printf("\n");
+
+      break;
+    }
+  }
+#endif
+
+  if (div_cycle) {
+    PC = instPC;
+    return resNOT_DONE;
+  }
+
+  //printf("res : %u r %u\n", (dividend & 0xffff), (dividend >> 16));
+
+  if (code == 0x65)
+    regs.Y = (dividend >> 16);
+  else
+    regs.A = (dividend >> 16);
+
+  if (prefix == 0x90) {
+    FLAG_ASSIGN(BIT_Z, (regs.Y = (dividend & 0xffff)));
+  } else {
+    FLAG_ASSIGN(BIT_Z, (regs.X = (dividend & 0xffff)));
+  }
+
+  FLAG_CLEAR(BIT_N);
+  FLAG_CLEAR(BIT_H);
+  FLAG_CLEAR(BIT_V);
+
+  pipeline_busy.regs = true;
+  return resGO;
+}
+
+int
+cl_stm8::inst_inc(t_mem code, unsigned char prefix)
+{
+  long int operand, resval;
+  unsigned int opaddr = 0;
+
+   if (((code&0xf0)==0x40) &&(prefix == 0x00)) {
+      operand = regs.A;
+   } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) {
+      operand = regs.X;
+   } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) {
+      operand = regs.Y;
+   } else {
+      opaddr = get_dest(code,prefix);
+      operand = get1(opaddr);
+   }
+
+   resval = operand + 1;
+
+   if (((code&0xf0)==0x40) &&(prefix == 0x00)) {
+      store_regs();
+      regs.A = resval&0xff;
+      FLAG_ASSIGN (BIT_Z, (resval & 0xff) == 0);
+      FLAG_ASSIGN (BIT_N, 0x80 & resval);
+      FLAG_CVH_BYTE_ADD(operand, 0x01, resval, BIT_V);
+   } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) {
+      store_regs();
+      regs.X = resval & 0xffff;
+      FLAG_ASSIGN (BIT_Z, (resval & 0xffff) == 0);
+      FLAG_ASSIGN (BIT_N, 0x8000 & resval);
+      FLAG_CVH_WORD_ADD(operand, 0x0001, resval, BIT_V);
+   } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) {
+      store_regs();
+      regs.Y = resval & 0xffff;
+      FLAG_ASSIGN (BIT_Z, (resval & 0xffff) == 0);
+      FLAG_ASSIGN (BIT_N, 0x8000 & resval);
+      FLAG_CVH_WORD_ADD(operand, 0x0001, resval, BIT_V);
+   } else {
+      store1(opaddr, resval &0xff);
+      FLAG_ASSIGN (BIT_Z, (resval & 0xff) == 0);
+      FLAG_ASSIGN (BIT_N, 0x80 & resval);
+      FLAG_CVH_BYTE_ADD(operand, 0x01, resval, BIT_V);
+   }
+
+   return(resGO);
+}
+
+int
+cl_stm8::inst_jp(t_mem code, unsigned char prefix)
+{
+  t_addr newPC = (PC & 0xff0000ul) + fetchea(code, prefix);
+  // PM0044 5.4.3 Pipeline with Call/Jump
+  // For a JP instruction, the fetch [of the next instruction] can start
+  // during the first cycle of the "dummy" execution.
+  PC = newPC;
+  pipeline_flush(true);
+  return(resGO);
+}
+
+int
+cl_stm8::inst_jr(t_mem code, unsigned char prefix)
+{
+  bool taken;
+  signed char ofs;
+  unsigned char bz, bn, bv;
+
+  if (prefix ==0x00) {
+    switch ((code>>1) & 7) {
+      case 0: // JRT - JRA (20) / JRF (21)
+        taken = 1;
+        break;
+      case 1: // JRUGT (22) / JRULE (23)
+        taken = !(regs.CC & (BIT_C | BIT_Z));
+        break;
+      case 2: // JRUGE (24) / JRULT (25)
+        taken = !(regs.CC & BIT_C);
+        break;
+      case 3: // JRNE (26) / JREQ (27)
+        taken = !(regs.CC & BIT_Z);
+        break;
+      case 4: // JRNV (28) / JRV (29)
+        taken = !(regs.CC & BIT_V);
+        break;
+      case 5: // JRPL (2A) / JRMI (2B)
+        taken = !(regs.CC & BIT_N);
+        break;
+      case 6: // JRSGT (2C) - Z or (N xor V) = 0 / JRSLE (2D) - Z or (N xor V) = 1
+        bz = !!(regs.CC & BIT_Z);
+        bn = !!(regs.CC & BIT_N);
+        bv = !!(regs.CC & BIT_V);
+        taken = !(bz | (bn ^ bv));
+        break;
+      case 7: // JRSGE (2E) - N xor V = 0 / / JRSLT(2F) N xor V = 1
+        bn = !!(regs.CC & BIT_N);
+        bv = !!(regs.CC & BIT_V);
+        taken = !(bn ^ bv);
+        break;
+      default:
+        return(resHALT);
+    }
+  }
+  else if (prefix==0x90) {
+    switch ((code>>1) & 7) {
+      case 4: // JRNH (28) / JRH (29)
+         taken = !(regs.CC & BIT_H);
+       break;
+      case 6: // JRNM (2C) / JRM (2D)
+        taken = !(regs.CC & (BIT_I1|BIT_I0));
         break;
       case 7: // JRIL (2E) / JRIH (2F), no means to test this ???
         taken = 0;
-      default:
-        return(resHALT);
-    }
-  }
-  else
-    return(resHALT);
-
-  if (code & 1)
-    taken = ! taken;
-
-

-  ofs = fetch();

-  if (taken)

-    {

-      PC += ofs;

-      tick(1);

-    }

-  return(resGO);

-}

-

-int
-cl_stm8::inst_lda(t_mem code, unsigned char prefix)
-{
-  int operand;
-  operand = OPERAND(code, prefix);
-  FLAG_NZ (operand);
-  regs.A = operand;
-  return(resGO);
-}
-
-int
-cl_stm8::operandw(t_mem code, unsigned char prefix)
-{
-       if(EA_IMM(code)) {
-               return(fetch2());
-       } else {
-               int addr = fetchea(code,prefix);
-               int result = get2(addr);
-               return(result);
-       }
-}
-
-int
-cl_stm8::inst_ldxy(t_mem code, unsigned char prefix)
-{

-  unsigned int operand;

-  u16_t *dest_ptr;

-

-  tick(1);

-

-  dest_ptr = (prefix == 0x90) ? ®s.Y : ®s.X;

-  if((prefix == 0x00 && code == 0x16) || (prefix == 0x91 && code == 0xce) || (prefix == 0x91 && code == 0xde)) dest_ptr = ®s.Y;

-

-  switch((code & 0xf0) >> 4) {
-     case 0xa: operand = fetch2(); break; // Immediate
-     case 0xb: operand = get2(fetch()); break; // Short
-     case 0xc:
-       switch (prefix) {
-       case 0x90:
-       case 0x00:
-         operand = get2(fetch2()); // Long direct
-         break;
-       case 0x92:
-       case 0x91:
-         operand = get2(get2(fetch())); // short indirect
-         break;
-       case 0x72:
-         operand = get2(get2(fetch2())); // long indirect
-         break;
-       default:
-         return(resHALT);
-       }
-       break;
-     case 0xf: operand = get2(*dest_ptr); break;
-     case 0xe: operand = get2(*dest_ptr + fetch()); break;
-     case 0xd:
-       switch (prefix) {
-       case 0x90:
-       case 0x00:
-         operand = get2(*dest_ptr + fetch2()); // Long x/y-indexed direct
-         break;
-       case 0x92:
-       case 0x91:
-         operand = get2(*dest_ptr + get2(fetch())); // short x/y-indexed indirect
-         break;
-       case 0x72:
-         operand = get2(*dest_ptr + get2(fetch2())); // long x-indexed indirect
-         break;
-       default:
-         return(resHALT);
-       }
-       break;
-     case 0x1: operand = get2(regs.SP + fetch()); break;
-     default:  return(resHALT);
-  }
-
-  if ((code & 0xf0) != 0x90)
-    {
-      FLAG_ASSIGN (BIT_Z, (operand & 0xffff) == 0);
-      FLAG_ASSIGN (BIT_N, 0x8000 & operand);
-    }
-
-  *dest_ptr = operand;
-
-  return(resGO);
-}
-
-int
-cl_stm8::inst_lddst(t_mem code, unsigned char prefix)
-{
-  unsigned int opaddr;
-
-   opaddr = fetchea(code,prefix);
-
-   FLAG_ASSIGN (BIT_Z, (regs.A & 0xff) == 0);
-   FLAG_ASSIGN (BIT_N, 0x80 & regs.A);
-
-   store1(opaddr, regs.A);
-
-   return(resGO);
-}
-
-int
-cl_stm8::inst_ldxydst(t_mem code, unsigned char prefix)
-{
-  /* ldw dst, REG */

-  unsigned int opaddr, operand;

-

-  tick(1);

-

-  switch ((((code & 0xf0) | (prefix << 8)) >> 4) & 0xfff)

-    {

-      case 0x00b:

-      case 0x00c:
-      case 0x92c:
-      case 0x72c:
-      case 0x90f:
-      case 0x90e:
-      case 0x90d:
-      case 0x91d:
-        operand = regs.X;
-        break;
-      case 0x00f:
-      case 0x00e:
-      case 0x00d:
-      case 0x92d:
-      case 0x72d:
-      case 0x90b:
-      case 0x90c:
-      case 0x91c:
-        operand = regs.Y;
-        break;
-      case 0x001:
-        switch (code)
-          {
-            case 0x17:
-              operand = regs.Y;
-              break;
-            case 0x1f:
-              operand = regs.X;
-              break;
-            default:
-              return resHALT;
-          }
         break;
       default:
-        return resHALT;
+        return(resHALT);
     }
-
-  switch((code & 0xf0) >> 4) {
-    case 0x1: opaddr = regs.SP + fetch(); break;
-    case 0xb: opaddr = fetch(); break;
-    case 0xc:
-      switch (prefix) {
-      case 0x00:
-      case 0x90:
-        opaddr = fetch2(); // long direct
-        break;
-      case 0x91:
-      case 0x92:
-        opaddr = get2(fetch()); // short indirect
-        break;
-      case 0x72:
-        opaddr = get2(fetch2()); // long indirect
-        break;
-      default:
-        return (resHALT);
-      }
-      break;
-    case 0xf: opaddr = (prefix == 0x90) ? regs.Y : regs.X; break;
-    case 0xe: opaddr = ((prefix == 0x90) ? regs.Y : regs.X) + fetch(); break;
-    case 0xd:
-      switch (prefix) {
-      case 0x90:
-        opaddr = regs.Y + fetch2(); // long y-indexed direct
-        break;
-      case 0x00:
-        opaddr = regs.X + fetch2(); // long x-indexed direct
-        break;
-      case 0x92:
-        opaddr = regs.X + get2(fetch()); // short x-indexed indirect
-        break;
-      case 0x91:
-        opaddr = regs.Y + get2(fetch()); // short y-indexed indirect
-        break;
-      case 0x72:
-        opaddr = regs.X + get2(fetch2()); // long x-indexed indirect
-        break;
-      default:
-        return (resHALT);
-      }
-      break;
-    default: return(resHALT);
-  }
-
-  FLAG_ASSIGN (BIT_Z, (operand & 0xffff) == 0);
-  FLAG_ASSIGN (BIT_N, 0x8000 & operand);
-
-  store2(opaddr, operand);
-
-  return(resGO);
-}
-
-int
-cl_stm8::inst_neg(t_mem code, unsigned char prefix)
-{
-  long int operand, resval;
-  unsigned int opaddr = 0;
-
-   if (((code&0xf0)==0x40) &&(prefix == 0x00)) {
-      operand = regs.A;
-   } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) {
-      operand = regs.X;
-   } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) {
-      operand = regs.Y;
-   } else {
-      opaddr = get_dest(code,prefix);
-      operand = get1(opaddr);
-   }
-
-   resval = 0 - operand;
-
-   if (((code&0xf0)==0x40) &&(prefix == 0x00)) {
-      regs.A = resval&0xff;
-      FLAG_ASSIGN (BIT_Z, (resval & 0xff) == 0);
-      FLAG_ASSIGN (BIT_N, 0x80 & resval);
-      FLAG_ASSIGN (BIT_V, (0x80 == operand));
-      FLAG_ASSIGN (BIT_C, 0x100 & resval);
-   } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) {
-      regs.X = resval&0xffff;
-      FLAG_ASSIGN (BIT_Z, (resval & 0xffff) == 0);
-      FLAG_ASSIGN (BIT_N, 0x8000 & resval);
-      FLAG_ASSIGN (BIT_V, (0x8000 == operand));
-      FLAG_ASSIGN (BIT_C, 0x10000 & resval);
-   } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) {
-      regs.Y = resval&0xffff;
-      FLAG_ASSIGN (BIT_Z, (resval & 0xffff) == 0);
-      FLAG_ASSIGN (BIT_N, 0x8000 & resval);
-      FLAG_ASSIGN (BIT_V, (0x8000 == operand));
-      FLAG_ASSIGN (BIT_C, 0x10000 & resval);
-   } else {
-      store1(opaddr, resval &0xff);
-      FLAG_ASSIGN (BIT_Z, (resval & 0xff) == 0);
-      FLAG_ASSIGN (BIT_N, 0x80 & resval);
-      FLAG_ASSIGN (BIT_V, (0x80 == operand));
-      FLAG_ASSIGN (BIT_C, 0x100 & resval);
-   }
-
-   return(resGO);
-}
-
-int
-cl_stm8::inst_or(t_mem code, unsigned char prefix)
-{
-  int result, operand1, operand2;
-
-  operand1 = regs.A;
-  operand2 = OPERAND(code, prefix);
-  result = (operand1 | operand2) & 0xff;
-  FLAG_NZ (result);
-
-  regs.A = result & 0xff;
-  return(resGO);
-}
-
-int
-cl_stm8::inst_rlc(t_mem code, unsigned char prefix)
-{
-  long int operand, resval;
-  unsigned int opaddr = 0;
-
-   if (((code&0xf0)==0x40) && (prefix == 0x00)) {
-      operand = regs.A;
-   } else if (((code&0xf0)==0x50) && (prefix == 0x00)) {
-      operand = regs.X;
-   } else if (((code&0xf0)==0x50) && (prefix == 0x90)) {
-      operand = regs.Y;
-   } else {
-      opaddr = get_dest (code, prefix);
-      operand = get1 (opaddr);
-   }
-
-   resval = operand << 0x1;
-
-   if (regs.CC & BIT_C) {
-      resval++;
-   }
-
-   if (((code&0xf0)==0x40) &&(prefix == 0x00)) {
-      regs.A = resval&0xff;
-      FLAG_ASSIGN (BIT_Z, (resval & 0xff) == 0);
-      FLAG_ASSIGN (BIT_N, 0x80 & resval);
-      FLAG_ASSIGN (BIT_C, (resval & 0x100));
-   } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) {
-      regs.X = resval & 0xffff;
-      FLAG_ASSIGN (BIT_Z, (resval & 0xffff) == 0);
-      FLAG_ASSIGN (BIT_N, 0x8000 & resval);
-      FLAG_ASSIGN (BIT_C, (resval & 0x10000));
-   } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) {
-      regs.Y = resval & 0xffff;
-      FLAG_ASSIGN (BIT_Z, (resval & 0xffff) == 0);
-      FLAG_ASSIGN (BIT_N, 0x8000 & resval);
-      FLAG_ASSIGN (BIT_C, (resval & 0x10000));
-   } else {
-      store1(opaddr, resval &0xff);
-      FLAG_ASSIGN (BIT_Z, (resval & 0xff) == 0);
-      FLAG_ASSIGN (BIT_N, 0x80 & resval);
-      FLAG_ASSIGN (BIT_C, (resval & 0x100));
-   }
-
-   return (resGO);
-}
-
-int
-cl_stm8::inst_rrc(t_mem code, unsigned char prefix)
-{
-  long int operand, resval;
-  unsigned int opaddr = 0;
-
-   if (((code&0xf0)==0x40) &&(prefix == 0x00)) {
-      operand = regs.A;
-   } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) {
-      operand = regs.X;
-   } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) {
-      operand = regs.Y;
-   } else {
-      opaddr = get_dest(code,prefix);
-      operand = get1(opaddr);
-   }
-
-   resval = operand >> 1;
-
-   if (((code&0xf0)==0x40) &&(prefix == 0x00)) {
-      if (regs.CC & BIT_C) {      resval |= 0x80;   }
-      regs.A = resval&0xff;
-      FLAG_ASSIGN (BIT_Z, (resval & 0xff) == 0);
-      FLAG_ASSIGN (BIT_N, 0x80 & resval);
-      FLAG_ASSIGN (BIT_C, (operand & 0x1));
-   } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) {
-      if (regs.CC & BIT_C) {      resval |= 0x8000;   }
-      regs.X = resval & 0xffff;
-      FLAG_ASSIGN (BIT_Z, (resval & 0xffff) == 0);
-      FLAG_ASSIGN (BIT_N, 0x8000 & resval);
-      FLAG_ASSIGN (BIT_C, (operand & 0x1));
-   } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) {
-      if (regs.CC & BIT_C) {      resval |= 0x8000;   }
-      regs.Y = resval & 0xffff;
-      FLAG_ASSIGN (BIT_Z, (resval & 0xffff) == 0);
-      FLAG_ASSIGN (BIT_N, 0x8000 & resval);
-      FLAG_ASSIGN (BIT_C, (operand & 0x1));
-   } else {
-      if (regs.CC & BIT_C) {      resval |= 0x80;   }
-      store1(opaddr, resval &0xff);
-      FLAG_ASSIGN (BIT_Z, (resval & 0xff) == 0);
-      FLAG_ASSIGN (BIT_N, 0x80 & resval);
-      FLAG_ASSIGN (BIT_C, (operand & 0x1));
-   }
-
-   return(resGO);
-}
-
-int
-cl_stm8::inst_sbc(t_mem code, unsigned char prefix)
-{
-  int result, operand1, operand2;
-  int carryin = !!(regs.CC & BIT_C);
-
-  operand1 = regs.A;
-  operand2 = OPERAND(code, prefix);
-  result = (operand1 - operand2 - carryin) & 0xff;
-
-  FLAG_NZ (result);
-  FLAG_CVH_BYTE_SUB(operand1, operand2, result, BIT_C | BIT_V);
-
-  regs.A = result;
-  return(resGO);
-}
-
-int
-cl_stm8::inst_sll(t_mem code, unsigned char prefix)
-{
-  long int operand, resval;
-  unsigned int opaddr = 0;
-
-   if (((code&0xf0)==0x40) &&(prefix == 0x00)) {
-      operand = regs.A;
-   } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) {
-      operand = regs.X;
-   } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) {
-      operand = regs.Y;
-   } else {
-      opaddr = get_dest(code,prefix);
-      operand = get1(opaddr);
-   }
-
-   resval = operand << 0x1;
-
-   if (((code&0xf0)==0x40) &&(prefix == 0x00)) {
-      regs.A = resval&0xff;
-      FLAG_ASSIGN (BIT_Z, (resval & 0xff) == 0);
-      FLAG_ASSIGN (BIT_N, 0x80 & resval);
-      FLAG_ASSIGN (BIT_C, (resval & 0x100));
-   } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) {
-      regs.X = resval & 0xffff;
-      FLAG_ASSIGN (BIT_Z, (resval & 0xffff) == 0);
-      FLAG_ASSIGN (BIT_N, 0x8000 & resval);
-      FLAG_ASSIGN (BIT_C, (resval & 0x10000));
-   } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) {
-      regs.Y = resval & 0xffff;
-      FLAG_ASSIGN (BIT_Z, (resval & 0xffff) == 0);
-      FLAG_ASSIGN (BIT_N, 0x8000 & resval);
-      FLAG_ASSIGN (BIT_C, (resval & 0x10000));
-   } else {
-      store1(opaddr, resval &0xff);
-      FLAG_ASSIGN (BIT_Z, (resval & 0xff) == 0);
-      FLAG_ASSIGN (BIT_N, 0x80 & resval);
-      FLAG_ASSIGN (BIT_C, (resval & 0x100));
-   }
-
-   return(resGO);
-}
-
-int
-cl_stm8::inst_sra(t_mem code, unsigned char prefix)
-{
-  long int operand, resval;
-  unsigned int opaddr = 0;
-
-   if (((code&0xf0)==0x40) &&(prefix == 0x00)) {
-      operand = regs.A;
-   } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) {
-      operand = regs.X;
-   } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) {
-      operand = regs.Y;
-   } else {
-      opaddr = get_dest(code,prefix);
-      operand = get1(opaddr);
-   }
-
-   resval = operand >> 1;
-
-   if (((code&0xf0)==0x40) &&(prefix == 0x00)) {
-      if (operand & 0x80) {      resval |= 0x80;   }
-      regs.A = resval&0xff;
-      FLAG_ASSIGN (BIT_Z, (resval & 0xff) == 0);
-      FLAG_ASSIGN (BIT_N, 0x80 & resval);
-      FLAG_ASSIGN (BIT_C, (operand & 0x1));
-   } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) {
-      if (operand & 0x8000) {      resval |= 0x8000;   }
-      regs.X = resval & 0xffff;
-      FLAG_ASSIGN (BIT_Z, (resval & 0xffff) == 0);
-      FLAG_ASSIGN (BIT_N, 0x8000 & resval);
-      FLAG_ASSIGN (BIT_C, (operand & 0x1));
-   } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) {
-      if (operand & 0x8000) {      resval |= 0x8000;   }
-      regs.Y = resval & 0xffff;
-      FLAG_ASSIGN (BIT_Z, (resval & 0xffff) == 0);
-      FLAG_ASSIGN (BIT_N, 0x8000 & resval);
-      FLAG_ASSIGN (BIT_C, (operand & 0x1));
-   } else {
-      if (operand & 0x80) {      resval |= 0x80;   }
-      store1(opaddr, resval &0xff);
-      FLAG_ASSIGN (BIT_Z, (resval & 0xff) == 0);
-      FLAG_ASSIGN (BIT_N, 0x80 & resval);
-      FLAG_ASSIGN (BIT_C, (operand & 0x1));
-   }
-
-   return(resGO);
-}
-
-int
-cl_stm8::inst_srl(t_mem code, unsigned char prefix)
-{
-  long int operand, resval;
-  unsigned int opaddr = 0;
-
-   if (((code&0xf0)==0x40) &&(prefix == 0x00)) {
-      operand = regs.A;
-   } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) {
-      operand = regs.X;
-   } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) {
-      operand = regs.Y;
-   } else {
-      opaddr = get_dest(code,prefix);
-      operand = get1(opaddr);
-   }
-
-   resval = operand >> 1;
-
-   if (((code&0xf0)==0x40) &&(prefix == 0x00)) {
-      regs.A = resval&0xff;
-      FLAG_ASSIGN (BIT_Z, (resval & 0xff) == 0);
-      FLAG_ASSIGN (BIT_N, 0x80 & resval);
-      FLAG_ASSIGN (BIT_C, (operand & 0x1));
-   } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) {
-      regs.X = resval & 0xffff;
-      FLAG_ASSIGN (BIT_Z, (resval & 0xffff) == 0);
-      FLAG_ASSIGN (BIT_N, 0x8000 & resval);
-      FLAG_ASSIGN (BIT_C, (operand & 0x1));
-   } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) {
-      regs.Y = resval & 0xffff;
-      FLAG_ASSIGN (BIT_Z, (resval & 0xffff) == 0);
-      FLAG_ASSIGN (BIT_N, 0x8000 & resval);
-      FLAG_ASSIGN (BIT_C, (operand & 0x1));
-   } else {
-      store1(opaddr, resval &0xff);
-      FLAG_ASSIGN (BIT_Z, (resval & 0xff) == 0);
-      FLAG_ASSIGN (BIT_N, 0x80 & resval);
-      FLAG_ASSIGN (BIT_C, (operand & 0x1));
-   }
-
-   return(resGO);
-}
-
-int
-cl_stm8::inst_sub(t_mem code, unsigned char prefix)
-{
-  FLAG_CLEAR(BIT_C);
-  return inst_sbc(code, prefix);
-}
-
-int
-cl_stm8::inst_swap(t_mem code, unsigned char prefix)
-{
-  long int operand, resval;
-  unsigned int opaddr = 0;
-
-   if (((code&0xf0)==0x40) &&(prefix == 0x00)) {
-      operand = regs.A;
-      resval = (operand << 4) | (operand >> 4);
-      regs.A = resval&0xff;
-      FLAG_ASSIGN (BIT_Z, (resval & 0xff) == 0);
-      FLAG_ASSIGN (BIT_N, 0x80 & resval);
-   } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) {
-      operand = regs.X;
-      resval = (operand << 8) | (operand >> 8);
-      regs.X = resval&0xffff;
-      FLAG_ASSIGN (BIT_Z, (resval & 0xffff) == 0);
-      FLAG_ASSIGN (BIT_N, 0x8000 & resval);
-   } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) {
-      operand = regs.Y;
-      resval = (operand << 8) | (operand >> 8);
-      regs.Y = resval&0xffff;
-      FLAG_ASSIGN (BIT_Z, (resval & 0xffff) == 0);
-      FLAG_ASSIGN (BIT_N, 0x8000 & resval);
-   } else {
-      opaddr = get_dest(code,prefix);
-      operand = get1(opaddr);
-      resval = (operand << 4) | (operand >> 4);
-      store1(opaddr, resval &0xff);
-      FLAG_ASSIGN (BIT_Z, (resval & 0xff) == 0);
-      FLAG_ASSIGN (BIT_N, 0x80 & resval);
-   }
-
-   return(resGO);
-}
-
-int
-cl_stm8::inst_tnz(t_mem code, unsigned char prefix)
-{
-  unsigned int resval;
-  unsigned int opaddr = 0;
-
-   if (((code&0xf0)==0x40) &&(prefix == 0x00)) {
-      resval = regs.A;
-      FLAG_ASSIGN (BIT_Z, (resval & 0xff) == 0);
-      FLAG_ASSIGN (BIT_N, 0x80 & resval);
-   } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) {
-      resval = regs.X;
-      FLAG_ASSIGN (BIT_Z, (resval & 0xffff) == 0);
-      FLAG_ASSIGN (BIT_N, 0x8000 & resval);
-   } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) {
-      resval = regs.Y;
-      FLAG_ASSIGN (BIT_Z, (resval & 0xffff) == 0);
-      FLAG_ASSIGN (BIT_N, 0x8000 & resval);
-   } else {
-      opaddr = get_dest(code,prefix);
-      resval = get1(opaddr);
-      FLAG_ASSIGN (BIT_Z, (resval & 0xff) == 0);
-      FLAG_ASSIGN (BIT_N, 0x80 & resval);
-   }
- 
-   return(resGO);
-}
-
-int
-cl_stm8::inst_xor(t_mem code, unsigned char prefix)
-{
-  int result, operand1, operand2;
-
-  operand1 = regs.A;
-  operand2 = OPERAND(code, prefix);
-  result = operand1 ^ operand2;
-  FLAG_NZ (result);
-
-  regs.A = result & 0xff;
-  return(resGO);
-}
-
-/* End of stm8.src/inst.cc */
+  }
+  else
+    return(resHALT);
+
+  if (code & 1)
+    taken = ! taken;
+
+  ofs = fetch();
+
+  if (taken)
+    {
+      // PM0044 5.4.3 Pipeline with Call/Jump
+      // For a JP instruction, the fetch [of the next instruction] can start
+      // during the first cycle of the "dummy" execution.
+      PC += ofs;
+      pipeline_flush(true);
+    }
+  else
+    exec_cycle();
+
+  return(resGO);
+}
+
+int
+cl_stm8::inst_lda(t_mem code, unsigned char prefix)
+{
+  int operand;
+  operand = OPERAND(code, prefix);
+  store_regs();
+  FLAG_NZ (operand);
+  regs.A = operand;
+  return(resGO);
+}
+
+int
+cl_stm8::operandw(t_mem code, unsigned char prefix)
+{
+       if(EA_IMM(code)) {
+               return(fetch2());
+       } else {
+               int addr = fetchea(code,prefix);
+               int result = get2(addr);
+               return(result);
+       }
+}
+
+int
+cl_stm8::inst_ldxy(t_mem code, unsigned char prefix)
+{
+  unsigned int operand;
+  u16_t *dest_ptr;
+
+  dest_ptr = (prefix == 0x90) ? ®s.Y : ®s.X;
+  if((prefix == 0x00 && code == 0x16) || (prefix == 0x91 && code == 0xce) || (prefix == 0x91 && code == 0xde)) dest_ptr = ®s.Y;
+
+  switch((code & 0xf0) >> 4) {
+     case 0xa: operand = fetch2(); exec_cycle(); break; // Immediate
+     case 0xb: operand = get2(fetch()); break; // Short
+     case 0xc:
+       switch (prefix) {
+       case 0x90:
+       case 0x00:
+         operand = get2(fetch2()); // Long direct
+         break;
+       case 0x92:
+       case 0x91:
+         operand = get2(fetch()); // short indirect
+         decode_cycle();
+         operand = get2(operand);
+         break;
+       case 0x72:
+         operand = get2(fetch2()); // long indirect
+         decode_cycle();
+         operand = get2(operand);
+         break;
+       default:
+         return(resHALT);
+       }
+       break;
+     case 0xf: get_regs(); operand = get2(*dest_ptr); break;
+     case 0xe: get_regs(); operand = get2(*dest_ptr + fetch()); break;
+     case 0xd:
+       switch (prefix) {
+       case 0x90:
+       case 0x00:
+         get_regs();
+         operand = get2(*dest_ptr + fetch2()); // Long x/y-indexed direct
+         break;
+       case 0x92:
+       case 0x91:
+         operand = get2(fetch()); // short x/y-indexed indirect
+         decode_cycle();
+         operand = get2(operand + *dest_ptr);
+         break;
+       case 0x72:
+         operand = get2(fetch2()); // long x-indexed indirect
+         decode_cycle();
+         operand = get2(operand + *dest_ptr);
+         break;
+       default:
+         return(resHALT);
+       }
+       break;
+     case 0x1: operand = get2(regs.SP + fetch()); break;
+     default:  return(resHALT);
+  }
+
+  store_regs();
+
+  if ((code & 0xf0) != 0x90)
+    {
+      FLAG_ASSIGN (BIT_Z, (operand & 0xffff) == 0);
+      FLAG_ASSIGN (BIT_N, 0x8000 & operand);
+    }
+
+  *dest_ptr = operand;
+
+  return(resGO);
+}
+
+int
+cl_stm8::inst_lddst(t_mem code, unsigned char prefix)
+{
+  unsigned int opaddr;
+
+   opaddr = fetchea(code,prefix);
+
+   get1(opaddr);
+
+   FLAG_ASSIGN (BIT_Z, (regs.A & 0xff) == 0);
+   FLAG_ASSIGN (BIT_N, 0x80 & regs.A);
+
+   store1(opaddr, regs.A);
+
+   return(resGO);
+}
+
+int
+cl_stm8::inst_ldxydst(t_mem code, unsigned char prefix)
+{
+  /* ldw dst, REG */
+  unsigned int opaddr, operand;
+
+  switch ((((code & 0xf0) | (prefix << 8)) >> 4) & 0xfff)
+    {
+      case 0x00b:
+      case 0x00c:
+      case 0x92c:
+      case 0x72c:
+      case 0x90f:
+      case 0x90e:
+      case 0x90d:
+      case 0x91d:
+        operand = regs.X;
+        break;
+      case 0x00f:
+      case 0x00e:
+      case 0x00d:
+      case 0x92d:
+      case 0x72d:
+      case 0x90b:
+      case 0x90c:
+      case 0x91c:
+        operand = regs.Y;
+        break;
+      case 0x001:
+        switch (code)
+          {
+            case 0x17:
+              operand = regs.Y;
+              break;
+            case 0x1f:
+              operand = regs.X;
+              break;
+            default:
+              return resHALT;
+          }
+        break;
+      default:
+        return resHALT;
+    }
+
+  switch((code & 0xf0) >> 4) {
+    case 0x1: opaddr = regs.SP + fetch(); break;
+    case 0xb: opaddr = fetch(); break;
+    case 0xc:
+      switch (prefix) {
+      case 0x00:
+      case 0x90:
+        opaddr = fetch2(); // long direct
+        break;
+      case 0x91:
+      case 0x92:
+        opaddr = get2(fetch()); // short indirect
+        decode_cycle();
+        opaddr += 0;
+        decode_cycle();
+        break;
+      case 0x72:
+        opaddr = get2(fetch2()); // long indirect
+        decode_cycle();
+        opaddr += 0;
+        decode_cycle();
+        break;
+      default:
+        return (resHALT);
+      }
+      break;
+    case 0xf: get_regs(); opaddr = (prefix == 0x90) ? regs.Y : regs.X; break;
+    case 0xe: get_regs(); opaddr = ((prefix == 0x90) ? regs.Y : regs.X) + fetch(); break;
+    case 0xd:
+      switch (prefix) {
+      case 0x90:
+        get_regs();
+        opaddr = regs.Y + fetch2(); // long y-indexed direct
+        break;
+      case 0x00:
+        get_regs();
+        opaddr = regs.X + fetch2(); // long x-indexed direct
+        break;
+      case 0x92:
+        opaddr = get2(fetch()); // short x-indexed indirect
+        decode_cycle();
+        opaddr += regs.X;
+        decode_cycle();
+        break;
+      case 0x91:
+        opaddr = get2(fetch()); // short y-indexed indirect
+        decode_cycle();
+        opaddr += regs.Y;
+        decode_cycle();
+        break;
+      case 0x72:
+        opaddr = get2(fetch2()); // long x-indexed indirect
+        decode_cycle();
+        opaddr += regs.X;
+        decode_cycle();
+        break;
+      default:
+        return (resHALT);
+      }
+      break;
+    default: return(resHALT);
+  }
+
+  FLAG_ASSIGN (BIT_Z, (operand & 0xffff) == 0);
+  FLAG_ASSIGN (BIT_N, 0x8000 & operand);
+
+  store2(opaddr, operand);
+
+  return(resGO);
+}
+
+int
+cl_stm8::inst_neg(t_mem code, unsigned char prefix)
+{
+  long int operand, resval;
+  unsigned int opaddr = 0;
+
+   if (((code&0xf0)==0x40) &&(prefix == 0x00)) {
+      operand = regs.A;
+   } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) {
+      operand = regs.X;
+   } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) {
+      operand = regs.Y;
+   } else {
+      opaddr = get_dest(code,prefix);
+      operand = get1(opaddr);
+   }
+
+   resval = 0 - operand;
+
+   if (((code&0xf0)==0x40) &&(prefix == 0x00)) {
+      store_regs();
+      regs.A = resval&0xff;
+      FLAG_ASSIGN (BIT_Z, (resval & 0xff) == 0);
+      FLAG_ASSIGN (BIT_N, 0x80 & resval);
+      FLAG_ASSIGN (BIT_V, (0x80 == operand));
+      FLAG_ASSIGN (BIT_C, 0x100 & resval);
+   } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) {
+      exec_cycle();
+      store_regs();
+      regs.X = resval&0xffff;
+      FLAG_ASSIGN (BIT_Z, (resval & 0xffff) == 0);
+      FLAG_ASSIGN (BIT_N, 0x8000 & resval);
+      FLAG_ASSIGN (BIT_V, (0x8000 == operand));
+      FLAG_ASSIGN (BIT_C, 0x10000 & resval);
+   } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) {
+      exec_cycle();
+      store_regs();
+      regs.Y = resval&0xffff;
+      FLAG_ASSIGN (BIT_Z, (resval & 0xffff) == 0);
+      FLAG_ASSIGN (BIT_N, 0x8000 & resval);
+      FLAG_ASSIGN (BIT_V, (0x8000 == operand));
+      FLAG_ASSIGN (BIT_C, 0x10000 & resval);
+   } else {
+      store1(opaddr, resval &0xff);
+      FLAG_ASSIGN (BIT_Z, (resval & 0xff) == 0);
+      FLAG_ASSIGN (BIT_N, 0x80 & resval);
+      FLAG_ASSIGN (BIT_V, (0x80 == operand));
+      FLAG_ASSIGN (BIT_C, 0x100 & resval);
+   }
+
+   return(resGO);
+}
+
+int
+cl_stm8::inst_or(t_mem code, unsigned char prefix)
+{
+  int result, operand1, operand2;
+
+  operand1 = regs.A;
+  operand2 = OPERAND(code, prefix);
+  result = (operand1 | operand2) & 0xff;
+  FLAG_NZ (result);
+
+  store_regs();
+
+  regs.A = result & 0xff;
+  return(resGO);
+}
+
+int
+cl_stm8::inst_rlc(t_mem code, unsigned char prefix)
+{
+  long int operand, resval;
+  unsigned int opaddr = 0;
+
+   if (((code&0xf0)==0x40) && (prefix == 0x00)) {
+      operand = regs.A;
+   } else if (((code&0xf0)==0x50) && (prefix == 0x00)) {
+      operand = regs.X;
+   } else if (((code&0xf0)==0x50) && (prefix == 0x90)) {
+      operand = regs.Y;
+   } else {
+      opaddr = get_dest (code, prefix);
+      operand = get1 (opaddr);
+   }
+
+   resval = operand << 0x1;
+
+   if (regs.CC & BIT_C) {
+      resval++;
+   }
+
+   if (((code&0xf0)==0x40) &&(prefix == 0x00)) {
+      store_regs();
+      regs.A = resval&0xff;
+      FLAG_ASSIGN (BIT_Z, (resval & 0xff) == 0);
+      FLAG_ASSIGN (BIT_N, 0x80 & resval);
+      FLAG_ASSIGN (BIT_C, (resval & 0x100));
+   } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) {
+      exec_cycle();
+      store_regs();
+      regs.X = resval & 0xffff;
+      FLAG_ASSIGN (BIT_Z, (resval & 0xffff) == 0);
+      FLAG_ASSIGN (BIT_N, 0x8000 & resval);
+      FLAG_ASSIGN (BIT_C, (resval & 0x10000));
+   } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) {
+      exec_cycle();
+      store_regs();
+      regs.Y = resval & 0xffff;
+      FLAG_ASSIGN (BIT_Z, (resval & 0xffff) == 0);
+      FLAG_ASSIGN (BIT_N, 0x8000 & resval);
+      FLAG_ASSIGN (BIT_C, (resval & 0x10000));
+   } else {
+      store1(opaddr, resval &0xff);
+      FLAG_ASSIGN (BIT_Z, (resval & 0xff) == 0);
+      FLAG_ASSIGN (BIT_N, 0x80 & resval);
+      FLAG_ASSIGN (BIT_C, (resval & 0x100));
+   }
+
+   return (resGO);
+}
+
+int
+cl_stm8::inst_rrc(t_mem code, unsigned char prefix)
+{
+  long int operand, resval;
+  unsigned int opaddr = 0;
+
+   if (((code&0xf0)==0x40) &&(prefix == 0x00)) {
+      operand = regs.A;
+   } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) {
+      operand = regs.X;
+   } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) {
+      operand = regs.Y;
+   } else {
+      opaddr = get_dest(code,prefix);
+      operand = get1(opaddr);
+   }
+
+   resval = operand >> 1;
+
+   if (((code&0xf0)==0x40) &&(prefix == 0x00)) {
+      store_regs();
+      if (regs.CC & BIT_C) {      resval |= 0x80;   }
+      regs.A = resval&0xff;
+      FLAG_ASSIGN (BIT_Z, (resval & 0xff) == 0);
+      FLAG_ASSIGN (BIT_N, 0x80 & resval);
+      FLAG_ASSIGN (BIT_C, (operand & 0x1));
+   } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) {
+      exec_cycle();
+      store_regs();
+      if (regs.CC & BIT_C) {      resval |= 0x8000;   }
+      regs.X = resval & 0xffff;
+      FLAG_ASSIGN (BIT_Z, (resval & 0xffff) == 0);
+      FLAG_ASSIGN (BIT_N, 0x8000 & resval);
+      FLAG_ASSIGN (BIT_C, (operand & 0x1));
+   } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) {
+      exec_cycle();
+      store_regs();
+      if (regs.CC & BIT_C) {      resval |= 0x8000;   }
+      regs.Y = resval & 0xffff;
+      FLAG_ASSIGN (BIT_Z, (resval & 0xffff) == 0);
+      FLAG_ASSIGN (BIT_N, 0x8000 & resval);
+      FLAG_ASSIGN (BIT_C, (operand & 0x1));
+   } else {
+      if (regs.CC & BIT_C) {      resval |= 0x80;   }
+      store1(opaddr, resval &0xff);
+      FLAG_ASSIGN (BIT_Z, (resval & 0xff) == 0);
+      FLAG_ASSIGN (BIT_N, 0x80 & resval);
+      FLAG_ASSIGN (BIT_C, (operand & 0x1));
+   }
+
+   return(resGO);
+}
+
+int
+cl_stm8::inst_sbc(t_mem code, unsigned char prefix)
+{
+  int result, operand1, operand2;
+  int carryin = !!(regs.CC & BIT_C);
+
+  operand1 = regs.A;
+  operand2 = OPERAND(code, prefix);
+
+  store_regs();
+
+  result = (operand1 - operand2 - carryin) & 0xff;
+
+  FLAG_NZ (result);
+  FLAG_CVH_BYTE_SUB(operand1, operand2, result, BIT_C | BIT_V);
+
+  regs.A = result;
+  return(resGO);
+}
+
+int
+cl_stm8::inst_sll(t_mem code, unsigned char prefix)
+{
+  long int operand, resval;
+  unsigned int opaddr = 0;
+
+   if (((code&0xf0)==0x40) &&(prefix == 0x00)) {
+      operand = regs.A;
+   } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) {
+      operand = regs.X;
+   } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) {
+      operand = regs.Y;
+   } else {
+      opaddr = get_dest(code,prefix);
+      operand = get1(opaddr);
+   }
+
+   resval = operand << 0x1;
+
+   if (((code&0xf0)==0x40) &&(prefix == 0x00)) {
+      store_regs();
+      regs.A = resval&0xff;
+      FLAG_ASSIGN (BIT_Z, (resval & 0xff) == 0);
+      FLAG_ASSIGN (BIT_N, 0x80 & resval);
+      FLAG_ASSIGN (BIT_C, (resval & 0x100));
+   } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) {
+      exec_cycle();
+      store_regs();
+      regs.X = resval & 0xffff;
+      FLAG_ASSIGN (BIT_Z, (resval & 0xffff) == 0);
+      FLAG_ASSIGN (BIT_N, 0x8000 & resval);
+      FLAG_ASSIGN (BIT_C, (resval & 0x10000));
+   } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) {
+      exec_cycle();
+      store_regs();
+      regs.Y = resval & 0xffff;
+      FLAG_ASSIGN (BIT_Z, (resval & 0xffff) == 0);
+      FLAG_ASSIGN (BIT_N, 0x8000 & resval);
+      FLAG_ASSIGN (BIT_C, (resval & 0x10000));
+   } else {
+      store1(opaddr, resval &0xff);
+      FLAG_ASSIGN (BIT_Z, (resval & 0xff) == 0);
+      FLAG_ASSIGN (BIT_N, 0x80 & resval);
+      FLAG_ASSIGN (BIT_C, (resval & 0x100));
+   }
+
+   return(resGO);
+}
+
+int
+cl_stm8::inst_sra(t_mem code, unsigned char prefix)
+{
+  long int operand, resval;
+  unsigned int opaddr = 0;
+
+   if (((code&0xf0)==0x40) &&(prefix == 0x00)) {
+      operand = regs.A;
+   } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) {
+      operand = regs.X;
+   } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) {
+      operand = regs.Y;
+   } else {
+      opaddr = get_dest(code,prefix);
+      operand = get1(opaddr);
+   }
+
+   resval = operand >> 1;
+
+   if (((code&0xf0)==0x40) &&(prefix == 0x00)) {
+      store_regs();
+      if (operand & 0x80) {      resval |= 0x80;   }
+      regs.A = resval&0xff;
+      FLAG_ASSIGN (BIT_Z, (resval & 0xff) == 0);
+      FLAG_ASSIGN (BIT_N, 0x80 & resval);
+      FLAG_ASSIGN (BIT_C, (operand & 0x1));
+   } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) {
+      exec_cycle();
+      store_regs();
+      if (operand & 0x8000) {      resval |= 0x8000;   }
+      regs.X = resval & 0xffff;
+      FLAG_ASSIGN (BIT_Z, (resval & 0xffff) == 0);
+      FLAG_ASSIGN (BIT_N, 0x8000 & resval);
+      FLAG_ASSIGN (BIT_C, (operand & 0x1));
+   } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) {
+      exec_cycle();
+      store_regs();
+      if (operand & 0x8000) {      resval |= 0x8000;   }
+      regs.Y = resval & 0xffff;
+      FLAG_ASSIGN (BIT_Z, (resval & 0xffff) == 0);
+      FLAG_ASSIGN (BIT_N, 0x8000 & resval);
+      FLAG_ASSIGN (BIT_C, (operand & 0x1));
+   } else {
+      if (operand & 0x80) {      resval |= 0x80;   }
+      store1(opaddr, resval &0xff);
+      FLAG_ASSIGN (BIT_Z, (resval & 0xff) == 0);
+      FLAG_ASSIGN (BIT_N, 0x80 & resval);
+      FLAG_ASSIGN (BIT_C, (operand & 0x1));
+   }
+
+   return(resGO);
+}
+
+int
+cl_stm8::inst_srl(t_mem code, unsigned char prefix)
+{
+  long int operand, resval;
+  unsigned int opaddr = 0;
+
+   if (((code&0xf0)==0x40) &&(prefix == 0x00)) {
+      operand = regs.A;
+   } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) {
+      operand = regs.X;
+   } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) {
+      operand = regs.Y;
+   } else {
+      opaddr = get_dest(code,prefix);
+      operand = get1(opaddr);
+   }
+
+   resval = operand >> 1;
+
+   if (((code&0xf0)==0x40) &&(prefix == 0x00)) {
+      store_regs();
+      regs.A = resval&0xff;
+      FLAG_ASSIGN (BIT_Z, (resval & 0xff) == 0);
+      FLAG_ASSIGN (BIT_N, 0x80 & resval);
+      FLAG_ASSIGN (BIT_C, (operand & 0x1));
+   } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) {
+      exec_cycle();
+      store_regs();
+      regs.X = resval & 0xffff;
+      FLAG_ASSIGN (BIT_Z, (resval & 0xffff) == 0);
+      FLAG_ASSIGN (BIT_N, 0x8000 & resval);
+      FLAG_ASSIGN (BIT_C, (operand & 0x1));
+   } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) {
+      exec_cycle();
+      store_regs();
+      regs.Y = resval & 0xffff;
+      FLAG_ASSIGN (BIT_Z, (resval & 0xffff) == 0);
+      FLAG_ASSIGN (BIT_N, 0x8000 & resval);
+      FLAG_ASSIGN (BIT_C, (operand & 0x1));
+   } else {
+      store1(opaddr, resval &0xff);
+      FLAG_ASSIGN (BIT_Z, (resval & 0xff) == 0);
+      FLAG_ASSIGN (BIT_N, 0x80 & resval);
+      FLAG_ASSIGN (BIT_C, (operand & 0x1));
+   }
+
+   return(resGO);
+}
+
+int
+cl_stm8::inst_sub(t_mem code, unsigned char prefix)
+{
+  FLAG_CLEAR(BIT_C);
+  return inst_sbc(code, prefix);
+}
+
+int
+cl_stm8::inst_swap(t_mem code, unsigned char prefix)
+{
+  long int operand, resval;
+  unsigned int opaddr = 0;
+
+   if (((code&0xf0)==0x40) &&(prefix == 0x00)) {
+      store_regs();
+      operand = regs.A;
+      resval = (operand << 4) | (operand >> 4);
+      regs.A = resval&0xff;
+      FLAG_ASSIGN (BIT_Z, (resval & 0xff) == 0);
+      FLAG_ASSIGN (BIT_N, 0x80 & resval);
+   } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) {
+      store_regs();
+      operand = regs.X;
+      resval = (operand << 8) | (operand >> 8);
+      regs.X = resval&0xffff;
+      FLAG_ASSIGN (BIT_Z, (resval & 0xffff) == 0);
+      FLAG_ASSIGN (BIT_N, 0x8000 & resval);
+   } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) {
+      store_regs();
+      operand = regs.Y;
+      resval = (operand << 8) | (operand >> 8);
+      regs.Y = resval&0xffff;
+      FLAG_ASSIGN (BIT_Z, (resval & 0xffff) == 0);
+      FLAG_ASSIGN (BIT_N, 0x8000 & resval);
+   } else {
+      opaddr = get_dest(code,prefix);
+      operand = get1(opaddr);
+      resval = (operand << 4) | (operand >> 4);
+      store1(opaddr, resval &0xff);
+      FLAG_ASSIGN (BIT_Z, (resval & 0xff) == 0);
+      FLAG_ASSIGN (BIT_N, 0x80 & resval);
+   }
+
+   return(resGO);
+}
+
+int
+cl_stm8::inst_tnz(t_mem code, unsigned char prefix)
+{
+  unsigned int resval;
+  unsigned int opaddr = 0;
+
+   if (((code&0xf0)==0x40) &&(prefix == 0x00)) {
+      store_regs();
+      resval = regs.A;
+      FLAG_ASSIGN (BIT_Z, (resval & 0xff) == 0);
+      FLAG_ASSIGN (BIT_N, 0x80 & resval);
+   } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) {
+      exec_cycle();
+      store_regs();
+      resval = regs.X;
+      FLAG_ASSIGN (BIT_Z, (resval & 0xffff) == 0);
+      FLAG_ASSIGN (BIT_N, 0x8000 & resval);
+   } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) {
+      exec_cycle();
+      store_regs();
+      resval = regs.Y;
+      FLAG_ASSIGN (BIT_Z, (resval & 0xffff) == 0);
+      FLAG_ASSIGN (BIT_N, 0x8000 & resval);
+   } else {
+      opaddr = get_dest(code,prefix);
+      resval = get1(opaddr);
+      exec_cycle();
+      FLAG_ASSIGN (BIT_Z, (resval & 0xff) == 0);
+      FLAG_ASSIGN (BIT_N, 0x80 & resval);
+   }
+
+   return(resGO);
+}
+
+int
+cl_stm8::inst_xor(t_mem code, unsigned char prefix)
+{
+  int result, operand1, operand2;
+
+  operand1 = regs.A;
+  operand2 = OPERAND(code, prefix);
+  result = operand1 ^ operand2;
+
+  store_regs();
+
+  FLAG_NZ (result);
+
+  regs.A = result & 0xff;
+  return(resGO);
+}
+
+/* End of stm8.src/inst.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/instcl.h sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/instcl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/instcl.h	2018-12-18 09:27:50.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/instcl.h	2022-01-18 09:48:32.000000000 +0000
@@ -1,48 +1,54 @@
-
-/* stm8.src/instcl.h */
-
-   //virtual void incx(void);
-   virtual int fetchea(t_mem code, unsigned char prefix);
-   virtual int get_1(unsigned int addr);
-   virtual int get2(unsigned int addr);
-   virtual int get3(unsigned int addr);
-   virtual int get_dest(t_mem code, unsigned char prefix);
-   virtual int operandw(t_mem code, unsigned char prefix);
-   virtual void flag_cvh(int x, int m, int r, bool byte, bool add, int mask);
-  
-   virtual int inst_adc(t_mem code, unsigned char prefix);
-   virtual int inst_add(t_mem code, unsigned char prefix);
-   virtual int inst_addw(t_mem code, unsigned char prefix);
-   virtual int inst_and(t_mem code, unsigned char prefix);
-   virtual int inst_bccmbcpl(t_mem code, unsigned char prefix);
-   virtual int inst_bcp(t_mem code, unsigned char prefix);
-   virtual int inst_bresbset(t_mem code, unsigned char prefix);
-   virtual int inst_btjfbtjt(t_mem code, unsigned char prefix);
-   virtual int inst_call(t_mem code, unsigned char prefix);
-   virtual int inst_clr(t_mem code, unsigned char prefix);
-   virtual int inst_cp(t_mem code, unsigned char prefix);
-   virtual int inst_cpw(t_mem code, unsigned char prefix);
-   virtual int inst_cpl(t_mem code, unsigned char prefix);
-   virtual int inst_dec(t_mem code, unsigned char prefix);
-   virtual int inst_div(t_mem code, unsigned char prefix);
-   virtual int inst_inc(t_mem code, unsigned char prefix);
-   virtual int inst_jp(t_mem code, unsigned char prefix);
-   virtual int inst_jr(t_mem code, unsigned char prefix);
-   virtual int inst_lda(t_mem code, unsigned char prefix);
-   virtual int inst_ldxy(t_mem code, unsigned char prefix);
-   virtual int inst_lddst(t_mem code, unsigned char prefix);
-   virtual int inst_ldxydst(t_mem code, unsigned char prefix);
-   virtual int inst_neg(t_mem code, unsigned char prefix);
-   virtual int inst_or(t_mem code, unsigned char prefix);
-   virtual int inst_rlc(t_mem code, unsigned char prefix);
-   virtual int inst_rrc(t_mem code, unsigned char prefix);
-   virtual int inst_sbc(t_mem code, unsigned char prefix);
-   virtual int inst_sll(t_mem code, unsigned char prefix);
-   virtual int inst_sra(t_mem code, unsigned char prefix);
-   virtual int inst_srl(t_mem code, unsigned char prefix);
-   virtual int inst_sub(t_mem code, unsigned char prefix);
-   virtual int inst_swap(t_mem code, unsigned char prefix);
-   virtual int inst_tnz(t_mem code, unsigned char prefix);
-   virtual int inst_xor(t_mem code, unsigned char prefix);
-
-/* End of stm8.src/instcl.h */
+
+/* stm8.src/instcl.h */
+
+   //virtual void incx(void);
+   virtual int fetchea(t_mem code, unsigned char prefix);
+   virtual void get_regs(void);
+   virtual int get_1(unsigned int addr);
+   virtual int get2(unsigned int addr);
+   virtual int get3(unsigned int addr);
+   virtual void decode_cycle(void);
+   virtual void exec_cycle(void);
+   virtual void store_regs(void);
+   virtual void store1(unsigned int addr, unsigned int val);
+   virtual void store2(unsigned int addr, unsigned int val);
+   virtual int get_dest(t_mem code, unsigned char prefix);
+   virtual int operandw(t_mem code, unsigned char prefix);
+   virtual void flag_cvh(int x, int m, int r, bool byte, bool add, int mask);
+  
+   virtual int inst_adc(t_mem code, unsigned char prefix);
+   virtual int inst_add(t_mem code, unsigned char prefix);
+   virtual int inst_addw(t_mem code, unsigned char prefix);
+   virtual int inst_and(t_mem code, unsigned char prefix);
+   virtual int inst_bccmbcpl(t_mem code, unsigned char prefix);
+   virtual int inst_bcp(t_mem code, unsigned char prefix);
+   virtual int inst_bresbset(t_mem code, unsigned char prefix);
+   virtual int inst_btjfbtjt(t_mem code, unsigned char prefix);
+   virtual int inst_call(t_mem code, unsigned char prefix);
+   virtual int inst_clr(t_mem code, unsigned char prefix);
+   virtual int inst_cp(t_mem code, unsigned char prefix);
+   virtual int inst_cpw(t_mem code, unsigned char prefix);
+   virtual int inst_cpl(t_mem code, unsigned char prefix);
+   virtual int inst_dec(t_mem code, unsigned char prefix);
+   virtual int inst_div(t_mem code, unsigned char prefix);
+   virtual int inst_inc(t_mem code, unsigned char prefix);
+   virtual int inst_jp(t_mem code, unsigned char prefix);
+   virtual int inst_jr(t_mem code, unsigned char prefix);
+   virtual int inst_lda(t_mem code, unsigned char prefix);
+   virtual int inst_ldxy(t_mem code, unsigned char prefix);
+   virtual int inst_lddst(t_mem code, unsigned char prefix);
+   virtual int inst_ldxydst(t_mem code, unsigned char prefix);
+   virtual int inst_neg(t_mem code, unsigned char prefix);
+   virtual int inst_or(t_mem code, unsigned char prefix);
+   virtual int inst_rlc(t_mem code, unsigned char prefix);
+   virtual int inst_rrc(t_mem code, unsigned char prefix);
+   virtual int inst_sbc(t_mem code, unsigned char prefix);
+   virtual int inst_sll(t_mem code, unsigned char prefix);
+   virtual int inst_sra(t_mem code, unsigned char prefix);
+   virtual int inst_srl(t_mem code, unsigned char prefix);
+   virtual int inst_sub(t_mem code, unsigned char prefix);
+   virtual int inst_swap(t_mem code, unsigned char prefix);
+   virtual int inst_tnz(t_mem code, unsigned char prefix);
+   virtual int inst_xor(t_mem code, unsigned char prefix);
+
+/* End of stm8.src/instcl.h */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/itc.cc sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/itc.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/itc.cc	2019-04-02 10:46:33.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/itc.cc	2022-02-03 14:06:06.000000000 +0000
@@ -27,7 +27,7 @@
 
 // prj
 
-#include 
+//#include 
 #include "utils.h"
 
 // sim
@@ -40,9 +40,6 @@
 cl_itc::cl_itc(class cl_uc *auc):
   cl_hw(auc, HW_INTERRUPT, 0, "itc")
 {
-  int i;
-  for (i= 0; i < 8; i++)
-    spr[i]= 0;
 }
 
 int
@@ -51,11 +48,68 @@
   int i;
   cl_hw::init();
   for (i= 0; i < 8; i++)
+    spr[i]= register_cell(uc->rom, 0x7f70+i);
+
+  exti_cr1= uc->rom->get_cell(0x50a0);
+  exti_cr2= uc->rom->get_cell(0x50a1);
+  exti_cr3= uc->rom->get_cell(0x50a2);
+  exti_cr4= uc->rom->get_cell(0x50aa);
+
+  exti_sr1= uc->rom->get_cell(0x50a3);
+  exti_sr2= uc->rom->get_cell(0x50a4);
+
+  exti_conf1= uc->rom->get_cell(0x50a5);
+  exti_conf2= uc->rom->get_cell(0x50ab);
+
+  // Although we set up all registers above not all STM8 variants
+  // use or expose them all. We only add vars for those that are
+  // user-visible on this particular MCU.
+  cl_var *v;
+  char name[] = "ITC_SPR1";
+  char desc[] = "Software priority register 1";
+  for (i= 0; i < 8; i++, name[7]++, desc[27]++)
     {
-      if (spr[i])
-	unregister_cell(spr[i]);
-      spr[i]= register_cell(uc->rom, 0x7f70+i);
+      uc->vars->add(v= new cl_var(name, uc->rom, 0x7f70+i, desc, 7, 0));
+      v->init();
     }
+
+    uc->vars->add(v= new cl_var("EXTI_CR1", uc->rom, 0x50a0,
+                                "External interrupt control register 1", 7, 0));
+    v->init();
+    uc->vars->add(v= new cl_var("EXTI_CR2", uc->rom, 0x50a1,
+                                "External interrupt control register 2", 7, 0));
+    v->init();
+
+    if (uc->type->type == CPU_STM8L ||
+        uc->type->type == CPU_STM8L101)
+      {
+        uc->vars->add(v= new cl_var("EXTI_CR3", uc->rom, 0x50a2,
+                                    "External interrupt control register 3", 7, 0));
+        v->init();
+
+        uc->vars->add(v= new cl_var("EXTI_SR1", uc->rom, 0x50a3,
+                                    "External interrupt status register 1", 7, 0));
+        v->init();
+        uc->vars->add(v= new cl_var("EXTI_SR2", uc->rom, 0x50a4,
+                                    "External interrupt status register 2", 7, 0));
+        v->init();
+
+        uc->vars->add(v= new cl_var("EXTI_CONF", uc->rom, 0x50a5,
+                                    "External interrupt port select register", 7, 0));
+        v->init();
+      }
+
+    if (uc->type->type == CPU_STM8L)
+      {
+        uc->vars->add(v= new cl_var("EXTI_CR4", uc->rom, 0x50aa,
+                                    "External interrupt control register 4", 7, 0));
+        v->init();
+
+        uc->vars->add(v= new cl_var("EXTI_CONF2", uc->rom, 0x50ab,
+                                    "External interrupt port select register 2", 7, 0));
+        v->init();
+      }
+
   return(0);
 }
 
@@ -117,6 +171,16 @@
   int i;
   for (i= 0; i < 8; i++)
     spr[i]->write(0xff);
+
+  // These belong to the ITC but are normally handled in cl_port.
+  exti_cr1->set(0);
+  exti_cr2->set(0);
+  exti_cr3->set(0);
+  exti_cr4->set(0);
+  exti_conf1->set(0);
+  exti_conf2->set(0);
+  exti_sr1->set(0);
+  exti_sr2->set(0);
 }
 
 void
@@ -159,7 +223,7 @@
 	  con->dd_printf("\n");
 	}
     }
-  print_cfg_info(con);
+  //print_cfg_info(con);
 }
 
 
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/itccl.h sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/itccl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/itccl.h	2018-12-18 09:27:50.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/itccl.h	2022-02-03 14:06:06.000000000 +0000
@@ -39,6 +39,9 @@
 {
  public:
   class cl_memory_cell *spr[8];
+  class cl_memory_cell *exti_cr1, *exti_cr2, *exti_cr3, *exti_cr4;
+  class cl_memory_cell *exti_sr1, *exti_sr2;
+  class cl_memory_cell *exti_conf1, *exti_conf2;
  public:
   cl_itc(class cl_uc *auc);
   virtual int init(void);
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/Makefile.in sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/Makefile.in
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/Makefile.in	2017-06-11 19:03:42.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/Makefile.in	2022-01-09 14:02:03.000000000 +0000
@@ -4,6 +4,9 @@
 # (c) Drotos Daniel, Talker Bt. 1997
 #
 
+# tool name
+TN		= stm8
+
 STARTYEAR	= 1997
 
 SHELL		= /bin/sh
@@ -14,7 +17,6 @@
 INSTALL		= @INSTALL@
 STRIP		= @STRIP@
 MAKEDEP         = @MAKEDEP@
-SREC_CAT	= @SREC_CAT@
 
 top_builddir	= @top_builddir@
 top_srcdir	= @top_srcdir@
@@ -23,8 +25,8 @@
 CPPFLAGS        = @CPPFLAGS@ -I$(srcdir) -I$(top_srcdir) -I$(top_builddir) \
 		  -I$(top_srcdir)/cmd.src -I$(top_srcdir)/sim.src \
 		  -I$(top_srcdir)/gui.src
-CFLAGS          = @CFLAGS@ @WALL_FLAG@
-CXXFLAGS        = @CXXFLAGS@ @WALL_FLAG@
+CFLAGS          = @WALL_FLAG@ @CFLAGS@
+CXXFLAGS        = @WALL_FLAG@ @CXXFLAGS@
 LDFLAGS         = @LDFLAGS@
 PICOPT		= @PICOPT@
 SHAREDLIB	= @SHAREDLIB@
@@ -52,43 +54,56 @@
 OBJECTS_SHARED	= glob.o itc.o serial.o rst.o timer.o port.o clk.o \
 		  uid.o bl.o flash.o \
 		  inst.o \
-		  simstm8.o stm8.o
-OBJECTS_EXE	= sstm8.o
+		  sim$(TN).o $(TN).o
+OBJECTS_EXE	= s$(TN).o
 OBJECTS		= $(OBJECTS_SHARED) $(OBJECTS_EXE)
 
-STM8ASM		= 
+# short/long exe and lib name
+SEN		= s$(TN)$(EXEEXT)
+LEN		= ucsim_$(TN)$(EXEEXT)
+SONAME		= libucsim_$(TN).so
 
 enable_dlso	= @enable_dlso@
 dlso_ok		= @dlso_ok@
 
+STM8ASM		= 
 #TEST_OBJ	= test_bit.hex test_dis.hex test_mov.hex test_jmp.hex \
 #		  test_arith.hex
 
 # Compiling entire program or any subproject
 # ------------------------------------------
-all: checkconf otherlibs stm8.src
+all: checkconf otherlibs $(TN).src
 
 tests: $(TEST_OBJ)
 
 
 # Compiling and installing everything and runing test
 # ---------------------------------------------------
-install: all installdirs
-	$(INSTALL) sstm8$(EXEEXT) $(DESTDIR)$(bindir)/`echo sstm8|sed '$(transform)'`$(EXEEXT)
-	$(STRIP) $(DESTDIR)$(bindir)/`echo sstm8|sed '$(transform)'`$(EXEEXT)
+install: all installdirs install_shared_lib
+	$(INSTALL) $(SEN) $(DESTDIR)$(bindir)/$(SEN)
+	$(STRIP) $(DESTDIR)$(bindir)/$(SEN)
+	$(INSTALL) $(LEN) $(DESTDIR)$(bindir)/$(LEN)
+	$(STRIP) $(DESTDIR)$(bindir)/$(LEN)
 
 
 # Deleting all the installed files
 # --------------------------------
 uninstall:
-	rm -f $(DESTDIR)$(bindir)/`echo sstm8|sed '$(transform)'`$(EXEEXT)
+	rm -f $(DESTDIR)$(bindir)/$(SEN)
+	rm -f $(DESTDIR)$(bindir)/$(LEN)
+	rm -f $(DESTDIR)$(libdir)/$(SONAME)
 
 
 # Performing self-test
 # --------------------
 check: test
 
+.PHONY:	test baseline
 test:
+	@$(MAKE) --no-print-directory -C test
+
+baseline:
+	@$(MAKE) --no-print-directory -C test baseline
 
 
 # Performing installation test
@@ -116,21 +131,28 @@
 # --------
 .SUFFIXES: .asm .hex
 
-stm8.src: sstm8$(EXEEXT) shared_lib
+$(TN).src: $(SEN) $(LEN) shared_lib
 
-sstm8$(EXEEXT): $(OBJECTS) $(top_builddir)/libcmd.a $(top_builddir)/libguiucsim.a $(top_builddir)/libsim.a $(top_builddir)/libucsimutil.a
+$(SEN): $(OBJECTS) $(top_builddir)/libcmd.a $(top_builddir)/libguiucsim.a $(top_builddir)/libsim.a $(top_builddir)/libucsimutil.a
 	$(CXX) $(CXXFLAGS) $(LDFLAGS) $(OBJECTS) $(LIBS) -o $@
 
+$(LEN): s$(TN)$(EXEEXT)
+	cp $< $@
+
 ifeq ($(dlso_ok),yes)
-shared_lib: $(top_builddir)/sstm8.so
+shared_lib: $(top_builddir)/$(SONAME)
+install_shared_lib: shared_lib
+	test -d $(DESTDIR)$(libdir) || $(INSTALL) -d $(DESTDIR)$(libdir)
+	$(INSTALL) $(top_builddir)/$(SONAME) $(DESTDIR)$(libdir)/$(SONAME)
 else
 shared_lib:
-	@$(top_srcdir)/mkecho $(top_builddir) "No stm8 shared lib made."
+	@$(top_srcdir)/mkecho $(top_builddir) "No $(TN) shared lib made."
 	@$(top_srcdir)/mkecho $(top_builddir) "(SHAREDLIB="$(SHAREDLIB)",dl_ok="$(dl_ok)",enable_dlso="$(enable_dlso)")"
+install_shared_lib:
 endif
 
-$(top_builddir)/sstm8.so: $(OBJECTS_SHARED)
-	$(CXX) -shared $(LDFLAGS) $(OBJECTS_SHARED) -o $(top_builddir)/sstm8.so
+$(top_builddir)/$(SONAME): $(OBJECTS_SHARED)
+	$(CXX) -shared $(LDFLAGS) $(OBJECTS_SHARED) -o $(top_builddir)/s$(TN).so
 
 otherlibs: $(top_builddir)/libcmd.a $(top_builddir)/libguiucsim.a $(top_builddir)/libsim.a $(top_builddir)/libucsimutil.a
 
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/port.cc sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/port.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/port.cc	2019-04-02 10:46:33.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/port.cc	2022-02-03 14:06:06.000000000 +0000
@@ -25,71 +25,407 @@
 02111-1307, USA. */
 /*@1@*/
 
+#include "stm8cl.h"
+#include "itsrccl.h"
 #include "portcl.h"
 
-cl_port::cl_port(class cl_uc *auc, t_addr abase/*, int aid*/, const char *aname):
+
+struct state {
+  t_mem pins, odr, idr, ddr, cr1, cr2;
+  t_mem exti_conf1, exti_conf2;
+  t_mem exti_cr1, exti_cr2, exti_cr3, exti_cr4;
+  t_mem exti_sr1, exti_sr2;
+};
+
+
+cl_port::cl_port(class cl_uc *auc, int iportnr/*, int aid*/, const char *aname):
 	cl_hw(auc, HW_PORT, /*aid*/0, aname)
 {
-  base = abase;
-  set_name(aname);
+  base = 0x5000 + iportnr * 5;
+  portnr = iportnr;
 }
 
 int
 cl_port::init(void)
 {
   cl_hw::init();
-  // ODR
-  cell_p= register_cell(uc->rom, base + 0);
-  // IDR
-  cell_in= register_cell(uc->rom, base + 1);
-  // DDR: 0=input, 1=output
-  cell_dir= register_cell(uc->rom, base + 2);
-
-  cl_var *v;
-  chars pn= cchars(get_name());
-  uc->vars->add(v= new cl_var(pn+chars("_ddr"), uc->rom, base+2,
-			      "Direction register"));
-  v->init();
-  uc->vars->add(v= new cl_var(pn+chars("_odr"), uc->rom, base+0,
-			      "Output data register"));
-  v->init();
-  uc->vars->add(v= new cl_var(pn+chars("_idr"), uc->rom, base+1,
-			      "Input data register (outside value of port pins)"));
-  v->init();
-  uc->vars->add(v= new cl_var(pn+chars("_pin"), uc->rom, base+1,
-			      "Outside value of port pins"));
-  v->init();
-  uc->vars->add(v= new cl_var(pn+chars("_pins"), uc->rom, base+1,
-			      "Outside value of port pins"));
-  v->init();
-  
+
+  class cl_stm8 *stm8 = static_cast(uc);
+
+  chars pn= chars(get_name());
+
+  cell_pins = register_cell(stm8->ports, portnr, pn+"_pins", "Outside value of port pins");
+  // Compat alias
+  uc->vars->add(pn+"_pin", stm8->ports, portnr, 7, 0, "Outside value of port pins");
+
+  pn.uppercase();
+
+  cell_odr = register_cell(uc->rom, base + 0, pn+"_ODR", "Output Data Register");
+  cell_idr = register_cell(uc->rom, base + 1, pn+"_IDR", "Input Data Register");
+  cell_ddr = register_cell(uc->rom, base + 2, pn+"_DDR", "Data Direction Register");
+  cell_cr1 = register_cell(uc->rom, base + 3, pn+"_CR1", "Control Register 1");
+  cell_cr2 = register_cell(uc->rom, base + 4, pn+"_CR2", "Control Register 2");
+
+  class cl_itc *itc = stm8->itc;
+
+  // We need to hook EXTI_CR* because changing interrupt sensitivity
+  // may lead to an immediate interrupt.
+  register_cell(itc->exti_cr1);
+  register_cell(itc->exti_cr2);
+  register_cell(itc->exti_cr3);
+  register_cell(itc->exti_cr4);
+
+  // We need to hook EXTI_CR* because changing them may change what
+  // interrupts are presented.
+  // N.B. We assume the presentation of edge-triggered interrupts
+  // is fixed at the time the event is handled. Documentation is
+  // not clear on this point but it seems reasonable?
+  register_cell(itc->exti_conf1);
+  register_cell(itc->exti_conf2);
+
+  // We need to hook EXTI_SR* because a level-triggered interrupt
+  // may come straight back when cleared.
+  register_cell(itc->exti_sr1);
+  register_cell(itc->exti_sr2);
+
   return 0;
 }
 
 void
 cl_port::reset(void)
 {
-  cell_dir->write(0);
-  cell_p->write(0);
-  cell_in->write(0);
+  cell_cr2->write(0);
+  if (uc->type->type == CPU_STM8S)
+    cell_cr1->write(base == 0x500f ? 0x02: 0); // PD_CR1 reset value is 0x02 (RM0016: 11.9.5)
+  else
+    cell_cr1->write(base == 0x5000 ? 0x01: 0); // PA_CR1 reset value is 0x01 (RM0013: 10.9.4 and RM0031: 10.9.4)
+  cell_ddr->write(0);
+  cell_odr->write(0);
+  cell_idr->write(0);
+}
+
+bool
+cl_port::high_bits_are_port_interrupt(const struct state *s)
+{
+  if (uc->type->type != CPU_STM8S)
+    {
+      switch (portnr)
+        {
+          case 0: // Port A
+            return false;
+          case 1: // Port B
+            return (s->exti_conf1 & (1U << 1));
+          case 2: // Port C
+            return false;
+          case 3: // Port D
+            return (s->exti_conf1 & (1U << 3));
+          case 4: // Port E
+            return (s->exti_conf1 & (1U << 5));
+          case 5: // Port F
+            return (s->exti_conf2 & (1U << 0));
+          case 6: // Port G
+            return (s->exti_conf2 & (1U << 2));
+          case 7: // Port H
+            return (s->exti_conf2 & (1U << 4));
+          case 8: // Port I
+            return false;
+        }
+    }
+
+  return true;
+}
+
+bool
+cl_port::low_bits_are_port_interrupt(const struct state *s)
+{
+  class cl_stm8 *stm8 = static_cast(uc);
+
+  if (uc->type->type != CPU_STM8S)
+    {
+      switch (portnr)
+        {
+          case 0: // Port A
+            return false;
+          case 1: // Port B
+            return (s->exti_conf1 & (1U << 0));
+          case 2: // Port C
+            return false;
+          case 3: // Port D
+            return (s->exti_conf1 & (1U << 2));
+          case 4: // Port E
+            return (s->exti_conf1 & (1U << 4));
+          case 5: // Port F
+            return (s->exti_conf1 & (1U << 6));
+          case 6: // Port G
+            return (s->exti_conf2 & (1U << 1));
+          case 7: // Port H
+            return (s->exti_conf2 & (1U << 3));
+          case 8: // Port I
+            return false;
+        }
+    }
+
+  return true;
+}
+
+bool
+cl_port::port_used_for_interrupt(const struct state *s)
+{
+  switch (portnr)
+    {
+      case 0: // Port A
+        return (uc->type->type == CPU_STM8S);
+      case 1: // Port B
+        return (uc->type->type == CPU_STM8S) || !(s->exti_conf2 & (1U << 5));
+      case 2: // Port C
+        return (uc->type->type == CPU_STM8S);
+      case 3: // Port D
+        return (uc->type->type == CPU_STM8S) || !(s->exti_conf2 & (1U << 6));
+      case 4: // Port E
+        return (uc->type->type == CPU_STM8S) || !(s->exti_conf1 & (1U << 7));
+      case 5: // Port F
+        return (uc->type->type != CPU_STM8S) && (s->exti_conf1 & (1U << 7));
+      case 6: // Port G
+        return (s->exti_conf2 & (1U << 5));
+      case 7: // Port H
+        return (s->exti_conf2 & (1U << 6));
+      case 8: // Port I
+        break;
+    }
+  return false;
+}
+
+int
+cl_port::port_sensitivity(const struct state *s)
+{
+  if (uc->type->type == CPU_STM8S)
+    {
+      switch (portnr)
+        {
+          case 0: // Port A
+            return ((s->exti_cr1 >> 0) & 3);
+          case 1: // Port B
+            return ((s->exti_cr1 >> 2) & 3);
+          case 2: // Port C
+            return ((s->exti_cr1 >> 4) & 3);
+          case 3: // Port D
+            return ((s->exti_cr1 >> 6) & 3);
+          case 4: // Port E
+            return ((s->exti_cr2 >> 0) & 3);
+        }
+    }
+  else
+    {
+      switch (portnr)
+        {
+          case 0: // Port A
+            break;
+          case 1: // Port B
+            return ((s->exti_cr3 >> 0) & 3);
+          case 2: // Port C
+            break;
+          case 3: // Port D
+            return ((s->exti_cr3 >> 2) & 3);
+          case 4: // Port E
+            return ((s->exti_cr3 >> 4) & 3);
+          case 5: // Port F
+            return ((s->exti_cr3 >> 6) & 3);
+          case 6: // Port G
+            return ((s->exti_cr4 >> 0) & 3);
+          case 7: // Port H
+            return ((s->exti_cr4 >> 2) & 3);
+          case 8: // Port I
+            break;
+        }
+    }
+
+  return 0;
+}
+
+void
+cl_port::port_interrupt(struct state *s)
+{
+  if (uc->type->type == CPU_STM8S)
+      s->exti_sr1 |= (1U << portnr);
+  else if (portnr == 1)
+      s->exti_sr2 |= (1U << 0);
+  else if (portnr >= 3 && portnr <= 5)
+      s->exti_sr2 |= (1U << (portnr - 2));
+}
+
+void
+cl_port::port_check_interrupt(struct state *s, t_mem bitmask, int bithigh, int bitlow)
+{
+  t_mem input_and_enabled = (~s->ddr) & s->cr2;
+
+  switch (port_sensitivity(s))
+    {
+      case 0: // Falling edge and low level
+        for (int i = bitlow; i <= bithigh; i++)
+          {
+            if ((input_and_enabled & (1U << i)) && !(s->idr & (1U << i)))
+              {
+                port_interrupt(s);
+                break;
+              }
+          }
+        break;
+
+      case 1: // Rising edge only
+        for (int i = bitlow; i <= bithigh; i++)
+          {
+            if ((input_and_enabled & (1U << i)) && !(last_idr & (1U << i)) && (s->idr & (1U << i)))
+              {
+                port_interrupt(s);
+                break;
+              }
+          }
+        break;
+
+      case 2: // Falling edge only
+        for (int i = bitlow; i <= bithigh; i++)
+          {
+            if ((input_and_enabled & (1U << i)) && (last_idr & (1U << i)) && !(s->idr & (1U << i)))
+              {
+                port_interrupt(s);
+                break;
+              }
+          }
+        break;
+
+      case 3: // Rising and falling edge
+        for (int i = bitlow; i <= bithigh; i++)
+          {
+            if ((input_and_enabled & (1U << i)) && (last_idr & (1U << i)) != (s->idr & (1U << i)))
+              {
+                port_interrupt(s);
+                break;
+              }
+          }
+        break;
+    }
+}
+
+void
+cl_port::pin_check_interrupt(struct state *s, t_mem exti_cr, int bithigh, int bitlow)
+{
+  t_mem input_and_enabled = (~s->ddr) & s->cr2;
+
+  for (int i = bitlow; i <= bithigh; i++)
+    {
+      t_mem bit = 1U << i;
+
+      if ((input_and_enabled & bit))
+        {
+          switch (exti_cr >> ((i - bitlow) * 2) & 3)
+            {
+              case 0: // Falling edge and low level
+                if (!(s->idr & bit))
+                  s->exti_sr1 |= bit;
+                break;
+
+              case 1: // Rising edge only
+                if (!(last_idr & bit) && (s->idr & bit))
+                  s->exti_sr1 |= bit;
+                break;
+
+              case 2: // Falling edge only
+                if ((last_idr & bit) && !(s->idr & bit))
+                  s->exti_sr1 |= bit;
+                break;
+
+              case 3: // Rising and falling edge
+                if ((last_idr & bit) != (s->idr & bit))
+                  s->exti_sr1 |= bit;
+                break;
+            }
+        }
+    }
 }
 
 void
 cl_port::write(class cl_memory_cell *cell, t_mem *val)
 {
-  if ((cell == cell_p) ||
-      (cell == cell_in) ||
-      (cell == cell_dir))
-    {
-      cell->set(*val);
-      t_mem p= cell_p->get();
-      t_mem i= cell_in->get();
-      t_mem d= cell_dir->get();
-      i&= ~d;
-      i|= (p & d);
-      cell_in->set(i);
-      if (cell == cell_in)
-	*val= i;
+  // IDR is not writeable except by us
+  if (cell == cell_idr)
+    {
+      *val = cell_idr->get();
+      return;
+    }
+
+  class cl_stm8 *stm8 = static_cast(uc);
+  class cl_itc *itc = stm8->itc;
+
+  struct state s;
+  s.pins = (cell == cell_pins ? *val : cell_pins->get()),
+  s.odr = (cell == cell_odr ? *val : cell_odr->get()),
+  s.idr = (cell == cell_idr ? *val : cell_idr->get()),
+  s.ddr = (cell == cell_ddr ? *val : cell_ddr->get()),
+  s.cr1 = (cell == cell_cr1 ? *val : cell_cr1->get()),
+  s.cr2 = (cell == cell_cr2 ? *val : cell_cr2->get()),
+
+  s.exti_conf1 = (cell == itc->exti_conf1 ? *val : itc->exti_conf1->get()),
+  s.exti_conf2 = (cell == itc->exti_conf2 ? *val : itc->exti_conf2->get()),
+
+  s.exti_cr1 = (cell == itc->exti_cr1 ? *val : itc->exti_cr1->get()),
+  s.exti_cr2 = (cell == itc->exti_cr2 ? *val : itc->exti_cr2->get()),
+  s.exti_cr3 = (cell == itc->exti_cr3 ? *val : itc->exti_cr3->get()),
+  s.exti_cr4 = (cell == itc->exti_cr4 ? *val : itc->exti_cr4->get()),
+
+  s.exti_sr1 = (cell == itc->exti_sr1 ? *val : itc->exti_sr1->get()),
+  s.exti_sr2 = (cell == itc->exti_sr2 ? *val : itc->exti_sr2->get()),
+
+  // Output bits are mirrored in the input so IDR and pins are the same
+  // except that pins are writeable externally and that's where we get
+  // the inputs from.
+  s.pins = s.idr = (s.pins & (~s.ddr)) | (s.odr & s.ddr);
+
+  if (cell == cell_pins)
+    {
+      *val = s.pins;
+      cell_idr->write(s.pins);
+    }
+  else if (cell == cell_odr || cell == cell_ddr)
+    {
+      cell_pins->write(s.pins);
+      cell_idr->write(s.pins);
+    }
+
+  t_mem orig_sr1 = s.exti_sr1;
+  t_mem orig_sr2 = s.exti_sr2;
+
+  if (high_bits_are_port_interrupt(&s))
+    {
+      if (port_used_for_interrupt(&s))
+        port_check_interrupt(&s, 0xf0, 7, 4);
+    }
+  else
+    pin_check_interrupt(&s, s.exti_cr2, 7, 4);
+
+  if (low_bits_are_port_interrupt(&s))
+    {
+      if (port_used_for_interrupt(&s))
+        port_check_interrupt(&s, 0x0f, 3, 0);
+    }
+  else
+    pin_check_interrupt(&s, s.exti_cr1, 3, 0);
+
+  last_idr = s.idr;
+
+  if (s.exti_sr1 != orig_sr1)
+    {
+      if (cell == itc->exti_sr1)
+        *val = s.exti_sr1;
+      else
+        itc->exti_sr1->write(s.exti_sr1);
+    }
+
+  if (s.exti_sr2 != orig_sr2)
+    {
+      if (cell == itc->exti_sr2)
+        *val = s.exti_sr2;
+      else
+        itc->exti_sr2->write(s.exti_sr2);
     }
 }
 
@@ -97,9 +433,9 @@
 cl_port::print_info(class cl_console_base *con)
 {
   int m;
-  t_mem o= cell_p->get(),
-    i= cell_in->get(),
-    d= cell_dir->get();
+  t_mem o= cell_odr->get(),
+    i= cell_idr->get(),
+    d= cell_ddr->get();
   con->dd_printf("%s at 0x%04x\n", get_name(), base);
   con->dd_printf("dir: 0x%02x ", d);
   for (m= 0x80; m; m>>= 1)
@@ -123,6 +459,16 @@
 	//con->dd_printf("-");
     }
   con->dd_printf("\n");
+  i= cell_cr1->get();
+  con->dd_printf("cr1: 0x%02x ", i);
+  for (m= 0x80; m; m>>= 1)
+    con->dd_printf("%c", (i & m)?'1':'0');
+  con->dd_printf("\n");
+  i= cell_cr2->get();
+  con->dd_printf("cr2: 0x%02x ", i);
+  for (m= 0x80; m; m>>= 1)
+    con->dd_printf("%c", (i & m)?'1':'0');
+  con->dd_printf("\n");
   print_cfg_info(con);
 }
 
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/portcl.h sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/portcl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/portcl.h	2017-02-21 09:48:05.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/portcl.h	2022-02-03 14:06:06.000000000 +0000
@@ -33,17 +33,29 @@
 
 class cl_port: public cl_hw
 {
- public:
-  class cl_memory_cell *cell_p, *cell_in, *cell_dir;
+ private:
   t_addr base;
+  int portnr;
+  t_mem last_idr;
+ public:
+  class cl_memory_cell *cell_pins, *cell_odr, *cell_idr, *cell_ddr, *cell_cr1, *cell_cr2;
  public:
-  cl_port(class cl_uc *auc, t_addr abase/*, int aid*/, const char *aname);
+  cl_port(class cl_uc *auc, int iportnr/*, int aid*/, const char *aname);
   virtual int init(void);
   virtual void reset(void);
 
   virtual void write(class cl_memory_cell *cell, t_mem *val);
 
   virtual void print_info(class cl_console_base *con);
+
+ private:
+  bool high_bits_are_port_interrupt(const struct state *s);
+  bool low_bits_are_port_interrupt(const struct state *s);
+  bool port_used_for_interrupt(const struct state *s);
+  int port_sensitivity(const struct state *s);
+  void port_interrupt(struct state *s);
+  void port_check_interrupt(struct state *s, t_mem bitmask, int bithigh, int bitlow);
+  void pin_check_interrupt(struct state *s, t_mem exti_cr, int bithigh, int bitlow);
 };
 
 
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/serial.cc sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/serial.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/serial.cc	2019-04-02 10:46:33.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/serial.cc	2022-01-24 11:09:43.000000000 +0000
@@ -27,20 +27,20 @@
 
 #include "ddconfig.h"
 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
+//#include 
+//#include 
+//#include 
+//#include 
+//#include 
+//#include 
+//#include 
 
 // prj
-#include "globals.h"
-#include "utils.h"
+//#include "globals.h"
+//#include "utils.h"
 
 // cmd
-#include "cmdutil.h"
+//#include "cmdutil.h"
 
 // sim
 #include "itsrccl.h"
@@ -102,19 +102,19 @@
 					regs[cr2], 0x80,
 					regs[sr], 0x80,
 					0x8008+txit*4, false, false,
-					chars("", "usart%d transmit register empty", id), 20*10+1));
+					chars("", "USART%d_TXE", id), 20*10+1));
   is->init();
   uc->it_sources->add(is= new cl_it_src(uc, txit,
 					regs[cr2], 0x40,
 					regs[sr], 0x40,
 					0x8008+txit*4, false, false,
-					chars("", "usart%d transmit complete", id), 20*10+2));
+					chars("", "USART%d_TC", id), 20*10+2));
   is->init();
   uc->it_sources->add(is= new cl_it_src(uc, rxit,
 					regs[cr2], 0x20,
 					regs[sr], 0x20,
 					0x8008+rxit*4, false, false,
-					chars("", "usart%d receive", id), 20*10+3));
+					chars("", "USART%d_RX", id), 20*10+3));
   is->init();
 
   sr_read= false;
@@ -139,8 +139,8 @@
   if (cell == regs[dr])
     {
       if (sr_read)
-	regs[sr]->set_bit0(0x1f);
-      regs[sr]->set_bit0(0x20);
+	regs[sr]->set(regs[sr]->get() | 0x1f);
+      regs[sr]->set(regs[sr]->get() & ~0x20);
       cfg_set(serconf_able_receive, 1);
       return s_in;
     }
@@ -326,7 +326,7 @@
   set_dr(s_in);
   cfg_write(serconf_received, s_in);
   if (regs[sr]->get() & 0x20)
-    regs[sr]->set_bit1(0x08); // overrun
+    regs[sr]->set(regs[sr]->get() | 0x08); // overrun
   show_readable(true);
 }
 
@@ -381,37 +381,37 @@
 {
   if (val)
     // TXE=1
-    regs[sr]->write_bit1(0x80);
+    regs[sr]->write(regs[sr]->read() | 0x80);
   else
     // TXE=0
-    regs[sr]->write_bit0(0x80);
+    regs[sr]->write(regs[sr]->read() & ~0x80);
 }
 
 void
 cl_serial::show_readable(bool val)
 {
   if (val)
-    regs[sr]->write_bit1(0x20);
+    regs[sr]->write(regs[sr]->read() | 0x20);
   else
-    regs[sr]->write_bit0(0x20);
+    regs[sr]->write(regs[sr]->read() & ~0x20);
 }
 
 void
 cl_serial::show_tx_complete(bool val)
 {
   if (val)
-    regs[sr]->write_bit1(0x40);
+    regs[sr]->write(regs[sr]->read() | 0x40);
   else
-    regs[sr]->write_bit0(0x40);
+    regs[sr]->write(regs[sr]->read() & ~0x40);
 }
 
 void
 cl_serial::show_idle(bool val)
 {
   if (val)
-    regs[sr]->write_bit1(0x10);
+    regs[sr]->write(regs[sr]->read() | 0x10);
   else
-    regs[sr]->write_bit0(0x10);
+    regs[sr]->write(regs[sr]->read() & ~0x10);
 }
 
 void
@@ -433,7 +433,7 @@
   if (fout)
     con->dd_printf("%s/%d", fout->get_file_name(), fout->file_id);
   con->dd_printf("\n");
-  print_cfg_info(con);
+  //print_cfg_info(con);
 }
 
 
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/serialcl.h sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/serialcl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/serialcl.h	2018-12-18 09:27:50.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/serialcl.h	2021-10-29 17:39:15.000000000 +0000
@@ -68,7 +68,7 @@
 	    int ttype, int atxit, int arxit);
   virtual ~cl_serial(void);
   virtual int init(void);
-  virtual int cfg_size(void) { return 10; }
+  virtual unsigned int cfg_size(void) { return 10; }
 
   virtual void new_hw_added(class cl_hw *new_hw);
   virtual void added_to_uc(void);
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/simstm8.cc sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/simstm8.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/simstm8.cc	2018-12-18 09:27:50.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/simstm8.cc	2020-08-22 10:25:08.000000000 +0000
@@ -25,6 +25,9 @@
 02111-1307, USA. */
 /*@1@*/
 
+#include 
+#include 
+
 // prj
 #include "globals.h"
 
@@ -41,14 +44,14 @@
 cl_simstm8::mk_controller(void)
 {
   int i;
-  char *typ= 0;
+  const char *typ= 0;
   class cl_optref type_option(this);
 
   type_option.init();
-  type_option.use(cchars("cpu_type"));
+  type_option.use("cpu_type");
   i= 0;
   if ((typ= type_option.get_value(typ)) == 0)
-    typ= cchars("STM8S");
+    typ= "STM8S";
   while ((cpus_stm8[i].type_str != NULL) &&
 	 (strcasecmp(typ, cpus_stm8[i].type_str) != 0))
     i++;
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/sstm8.cc sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/sstm8.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/sstm8.cc	2018-12-18 09:27:50.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/sstm8.cc	2020-06-13 16:30:36.000000000 +0000
@@ -29,7 +29,7 @@
 #include "globals.h"
 
 // sim.src
-#include "appcl.h"
+//#include "appcl.h"
 
 // local
 #include "simstm8cl.h"
@@ -42,6 +42,7 @@
 
   cpus= cpus_stm8;
   application= new cl_app();
+  application->set_name("sstm8");
   application->init(argc, argv);
   sim= new cl_simstm8(application);
   if (sim->init())
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/stm8.cc sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/stm8.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/stm8.cc	2019-07-02 08:44:01.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/stm8.cc	2022-02-03 20:00:33.000000000 +0000
@@ -28,27 +28,29 @@
 02111-1307, USA. */
 /*@1@*/
 
-#include "ddconfig.h"
+//#include "ddconfig.h"
 
-#include  /* for va_list */
+//#include  /* for va_list */
+#include 
 #include 
 #include 
 #include 
-#include "i_string.h"
+#include 
 
 // prj
-#include "pobjcl.h"
+//#include "pobjcl.h"
 #include "globals.h"
 
 // sim
-#include "simcl.h"
+//#include "simcl.h"
+#include "dregcl.h"
 
 // local
 #include "stm8cl.h"
 #include "glob.h"
-#include "regsstm8.h"
+//#include "regsstm8.h"
 #include "stm8mac.h"
-#include "itccl.h"
+//#include "itccl.h"
 #include "serialcl.h"
 #include "rstcl.h"
 #include "timercl.h"
@@ -60,6 +62,8 @@
 
 /*******************************************************************/
 
+static class cl_stm8_error_registry stm8_error_registry;
+
 
 /*
  * Base type of STM8 controllers
@@ -76,8 +80,11 @@
 cl_stm8::init(void)
 {
   cl_uc::init(); /* Memories now exist */
+  sp_limit= 0x1500;
 
-  xtal = 8000000;
+  pipetrace_file = NULL;
+  pipetrace_fd = NULL;
+  pipetrace_fold = true;
 
   //rom = address_space(MEM_ROM_ID);
   //ram = mem(MEM_XRAM);
@@ -112,22 +119,26 @@
   regs.CC = 0x28;
   //regs.VECTOR = 1;
   PC= 0x8000;
+
+  div_cycle = 0;
+
+  pipeline_flush(false);
 }
 
 
-char *
+const char *
 cl_stm8::id_string(void)
 {
   switch (type->type)
     {
     case CPU_STM8S:
-      return((char*)"STM8 S,AF");
+      return("STM8 S,AF");
     case CPU_STM8L:
-      return((char*)"STM8 AL,L");
+      return("STM8 AL,L");
     case CPU_STM8L101:
-      return((char*)"STM8 L101");
+      return("STM8 L101");
     default:
-      return((char*)"STM8");
+      return("STM8");
     }
 }
 
@@ -155,24 +166,24 @@
 
 static class cl_port_ui *d= NULL;
 static int puix= 1;
-static int puiy= 4;
+static int puiy= 5;
 static int puik= 0;
 static int puis= 1;
 static const char *puiks= keysets[puik];
 static class cl_port_data pd;
 
 void
-cl_stm8::mk_port(t_addr base, chars n)
+cl_stm8::mk_port(int portnr, chars n)
 {
   class cl_port *p;
-  add_hw(p= new cl_port(this, base, n));
+  add_hw(p= new cl_port(this, portnr, n));
   p->init();
 
   pd.set_name(n);
-  pd.cell_p  = p->cell_p;
-  pd.cell_in = p->cell_in;
-  pd.cell_dir= p->cell_dir;
-  pd.keyset  = chars(puiks);
+  pd.cell_p  = p->cell_odr;
+  pd.cell_in = p->cell_idr;
+  pd.cell_dir= p->cell_ddr;
+  pd.keyset  = puiks;
   pd.basx    = puix;
   pd.basy    = puiy;
   d->add_port(&pd, puis++);
@@ -181,7 +192,7 @@
     {
       puix= 1;
       if ((puiy+= 7) > 20)
-	;
+        {}
     }
   if ((puik+= 1) > 7)
     puiks= NULL;
@@ -190,9 +201,17 @@
 }
 
 void
+cl_stm8::make_cpu_hw(void)
+{
+  add_hw(cpu= new cl_stm8_cpu(this));
+  cpu->init();
+}
+
+void
 cl_stm8::mk_hw_elements(void)
 {
   class cl_hw *h;
+  class cl_it_src *is;
   cl_uc::mk_hw_elements();
   class cl_option *o;
 
@@ -264,17 +283,17 @@
       o->hide();
     }
   
+  add_hw(h= new cl_dreg(this, 0, "dreg"));
+  h->init();
+
   add_hw(d= new cl_port_ui(this, 0, "dport"));
   d->init();
   pd.init();
   
-  add_hw(h= new cl_stm8_cpu(this));
-  h->init();
-  
   if (type->type == CPU_STM8S)
     {
-      add_hw(h= new cl_clk_saf(this));
-      h->init();
+      add_hw(clk= new cl_clk_saf(this));
+      clk->init();
       if (type->subtype & (DEV_STM8S003|
 			   DEV_STM8S007|
 			   DEV_STM8S103|
@@ -309,8 +328,8 @@
     }
   if (type->type == CPU_STM8L)
     {
-      add_hw(h= new cl_clk_all(this));
-      h->init();
+      add_hw(clk= new cl_clk_all(this));
+      clk->init();
       add_hw(h= new cl_serial(this, 0x5230, 1, 27, 28));
       h->init();
       if (type->subtype & (DEV_STM8AL3xE|
@@ -334,27 +353,91 @@
     }
   if (type->type == CPU_STM8L101)
     {
-      add_hw(h= new cl_clk_l101(this));
-      h->init();
+      add_hw(clk= new cl_clk_l101(this));
+      clk->init();
       add_hw(h= new cl_serial(this, 0x5230, 1, 27, 28));
       h->init();
     }
 
+  int n_ports = 4;
+
+  if (type->type == CPU_STM8S)
+    {
+      switch (type->subtype)
+        {
+          case DEV_STM8AF62_46:
+            n_ports += 3;
+            break;
+
+          case DEV_STM8S005:
+          case DEV_STM8S007:
+          case DEV_STM8S105:
+          case DEV_STM8S207:
+          case DEV_STM8S208:
+          case DEV_STM8AF52:
+            n_ports += 1;
+            break;
+        }
+    }
+  else if (type->type == CPU_STM8L)
+    {
+      if (type->subtype != DEV_STM8L051)
+        n_ports += 2;
+
+      if (type->subtype & (DEV_STM8AL3xE|
+                           DEV_STM8AL3x8|
+                           DEV_STM8L052R|
+                           DEV_STM8L15x8|
+                           DEV_STM8L162))
+        {
+          n_ports += 1;
+
+          if (type->subtype != DEV_STM8L052R)
+            n_ports += 2;
+        }
+    }
+
+  ports= new cl_address_space("ports", 0, n_ports, 8);
+  ports->init();
+  address_spaces->add(ports);
+
+  ports_chip= new cl_chip8("ports_chip", n_ports, 8);
+  ports_chip->init();
+  memchips->add(ports_chip);
+
+  class cl_address_decoder *ad= new cl_address_decoder(ports, ports_chip, 0, n_ports - 1, 0);
+  ad->init();
+  ports->decoders->add(ad);
+  ad->activate(0);
+
   add_hw(itc= new cl_itc(this));
   itc->init();
 
-  {
-    mk_port(0x5000, "pa");
-    mk_port(0x5005, "pb");
-    mk_port(0x500a, "pc");
-    mk_port(0x500f, "pd");
-  }
+  mk_port(0, "pa");
+  mk_port(1, "pb");
+  mk_port(2, "pc");
+  mk_port(3, "pd");
   
   if (type->type == CPU_STM8S)
     {
       // all S and AF
-      mk_port(0x5014, "pe");
-      mk_port(0x5019, "pf");
+      mk_port(4, "pe");
+      mk_port(5, "pf");
+
+      char name[] = "EXTI0";
+      for (int i= 0; i <= 4; i++, name[4]++)
+        {
+          it_sources->add(is= new cl_it_src(this, 3 + i,
+                    itc->exti_sr1, 1 << i,
+                    itc->exti_sr1, 1 << i,
+                    0x8014 + i * 4,
+                    true, // STM8S has no EXTI_SR[12] so port interrupts autoclear and are not ack'd.
+                    false,
+                    strdup(name),
+                    25*10+i));
+          is->init();
+        }
+
       if (type->subtype & (DEV_STM8S005|
 			   DEV_STM8S007|
 			   DEV_STM8S105|
@@ -363,11 +446,11 @@
 			   DEV_STM8AF52|
 			   DEV_STM8AF62_46))
 	{
-	  mk_port(0x501e, "pg");
+	  mk_port(6, "pg");
 	  if (type->subtype != DEV_STM8AF62_46)
 	    {
-	      mk_port(0x5023, "ph");
-	      mk_port(0x5028, "pi");
+	      mk_port(7, "ph");
+	      mk_port(8, "pi");
 	    }
 	}
       add_hw(h= new cl_rst(this, 0x50b3, 0x1f));
@@ -408,70 +491,173 @@
 	  h->init();
 	}
     }
-  else if (type->type == CPU_STM8L)
+  else
     {
-      if (type->subtype != DEV_STM8L051)
-	{
-	  mk_port(0x5014, "pe");
-	  mk_port(0x5019, "pf");
-	}
-      if (type->subtype & (DEV_STM8AL3xE|
-			   DEV_STM8AL3x8|
-			   DEV_STM8L052R|
-			   DEV_STM8L15x8|
-			   DEV_STM8L162))
-	{
-	  mk_port(0x501e, "pg");
-	  if (type->subtype != DEV_STM8L052R)
+      char name[] = "EXTI0";
+      for (int i= 0; i <= 7; i++, name[4]++)
+        {
+          it_sources->add(is= new cl_it_src(this, 8 + i,
+                    itc->exti_sr1, 1 << i,
+                    itc->exti_sr1, 1 << i,
+                    0x8028 + i * 4,
+                    false,
+                    false,
+                    strdup(name),
+                    25*10+i));
+          is->init();
+        }
+
+      if (type->type == CPU_STM8L)
+        {
+          if (type->subtype != DEV_STM8L051)
 	    {
-	      mk_port(0x5023, "ph");
-	      mk_port(0x5028, "pi");
+	      mk_port(0x5014, "pe");
+	      mk_port(0x5019, "pf");
+
+              it_sources->add(is= new cl_it_src(this, 5,
+                        itc->exti_sr2, (1 << 3) | (1 << 2),
+                        itc->exti_sr2, (1 << 3) | (1 << 2),
+                        0x801c,
+                        false,
+                        false,
+                        "EXTIE/F/PVD",
+                        25*10+5));
+              is->init();
 	    }
-	}
-      add_hw(h= new cl_rst(this, 0x50b0+1, 0x3f));
-      h->init();
-      add_hw(h= new cl_tim2_all(this, 2, 0x5250));
-      h->init();
-      add_hw(h= new cl_tim3_all(this, 3, 0x5280));
-      h->init();
-      add_hw(h= new cl_tim4_all(this, 4, 0x52E0));
-      h->init();
-      // all AL
-      if (type->subtype & DEV_STM8AL)
-	{
-	  add_hw(h= new cl_tim1_all(this, 1, 0x52b0));
-	  h->init();
-	}
-      // some L
-      if (type->subtype & (DEV_STM8L052C |
-			   DEV_STM8L052R |
-			   DEV_STM8L15x46 |
-			   DEV_STM8L15x8 |
-			   DEV_STM8L162))
-	{
-	  add_hw(h= new cl_tim1_all(this, 1, 0x52b0));
-	  h->init();
-	}
-      if (type->subtype & (DEV_STM8AL3xE |
-			   DEV_STM8AL3x8 |
-			   DEV_STM8L052R |
-			   DEV_STM8L15x8 |
-			   DEV_STM8L162))
-	{
-	  add_hw(h= new cl_tim5_all(this, 5, 0x5300));
-	  h->init();
-	}
-    }
-  else if (type->type == CPU_STM8L101)
-    {
-      add_hw(h= new cl_rst(this, 0x50b0+1, 0x0f));
-      h->init();
-      add_hw(h= new cl_tim2_l101(this, 2, 0x5250));
-      h->init();
-      add_hw(h= new cl_tim3_l101(this, 2, 0x5280));
-      h->init();
-      add_hw(h= new cl_tim4_l101(this, 4, 0x52E0));
-      h->init();
+
+          if (type->subtype & (DEV_STM8AL3xE|
+			       DEV_STM8AL3x8|
+			       DEV_STM8L052R|
+			       DEV_STM8L15x8|
+			       DEV_STM8L162))
+	    {
+	      mk_port(0x501e, "pg");
+
+              it_sources->add(is= new cl_it_src(this, 6,
+                        itc->exti_sr2, (1 << 4) | (1 << 0),
+                        itc->exti_sr2, (1 << 4) | (1 << 0),
+                        0x8020,
+                        false,
+                        false,
+                        "EXTIB/G",
+                        25*10+6));
+              is->init();
+
+	      if (type->subtype != DEV_STM8L052R)
+	        {
+	          mk_port(0x5023, "ph");
+	          mk_port(0x5028, "pi");
+
+                  it_sources->add(is= new cl_it_src(this, 7,
+                            itc->exti_sr2, (1 << 5) | (1 << 1),
+                            itc->exti_sr2, (1 << 5) | (1 << 1),
+                            0x8024,
+                            false,
+                            false,
+                            "EXTID/H",
+                            25*10+7));
+                  is->init();
+	        }
+              else
+                {
+                  it_sources->add(is= new cl_it_src(this, 7,
+                            itc->exti_sr2, (1 << 1),
+                            itc->exti_sr2, (1 << 1),
+                            0x8024,
+                            false,
+                            false,
+                            "EXTID",
+                            25*10+7));
+                  is->init();
+                }
+	    }
+          else
+            {
+              it_sources->add(is= new cl_it_src(this, 6,
+                        itc->exti_sr2, (1 << 0),
+                        itc->exti_sr2, (1 << 0),
+                        0x8020,
+                        false,
+                        false,
+                        "EXTIB",
+                        25*10+6));
+              is->init();
+
+              it_sources->add(is= new cl_it_src(this, 7,
+                        itc->exti_sr2, (1 << 1),
+                        itc->exti_sr2, (1 << 1),
+                        0x8024,
+                        false,
+                        false,
+                        "EXTID",
+                        25*10+7));
+              is->init();
+            }
+
+          add_hw(h= new cl_rst(this, 0x50b0+1, 0x3f));
+          h->init();
+          add_hw(h= new cl_tim2_all(this, 2, 0x5250));
+          h->init();
+          add_hw(h= new cl_tim3_all(this, 3, 0x5280));
+          h->init();
+          add_hw(h= new cl_tim4_all(this, 4, 0x52E0));
+          h->init();
+          // all AL
+          if (type->subtype & DEV_STM8AL)
+	    {
+	      add_hw(h= new cl_tim1_all(this, 1, 0x52b0));
+	      h->init();
+	    }
+          // some L
+          if (type->subtype & (DEV_STM8L052C |
+			       DEV_STM8L052R |
+			       DEV_STM8L15x46 |
+			       DEV_STM8L15x8 |
+			       DEV_STM8L162))
+	    {
+	      add_hw(h= new cl_tim1_all(this, 1, 0x52b0));
+	      h->init();
+	    }
+          if (type->subtype & (DEV_STM8AL3xE |
+			       DEV_STM8AL3x8 |
+			       DEV_STM8L052R |
+			       DEV_STM8L15x8 |
+			       DEV_STM8L162))
+	    {
+	      add_hw(h= new cl_tim5_all(this, 5, 0x5300));
+	      h->init();
+	    }
+        }
+      else if (type->type == CPU_STM8L101)
+        {
+          add_hw(h= new cl_rst(this, 0x50b0+1, 0x0f));
+          h->init();
+          add_hw(h= new cl_tim2_l101(this, 2, 0x5250));
+          h->init();
+          add_hw(h= new cl_tim3_l101(this, 2, 0x5280));
+          h->init();
+          add_hw(h= new cl_tim4_l101(this, 4, 0x52E0));
+          h->init();
+
+          it_sources->add(is= new cl_it_src(this, 6,
+                    itc->exti_sr2, (1 << 0),
+                    itc->exti_sr2, (1 << 0),
+                    0x8020,
+                    false,
+                    false,
+                    "EXTIB",
+                    25*10+6));
+          is->init();
+          it_sources->add(is= new cl_it_src(this, 7,
+                    itc->exti_sr2, (1 << 1),
+                    itc->exti_sr2, (1 << 1),
+                    0x8024,
+                    false,
+                    false,
+                    "EXTID",
+                    25*10+7));
+          is->init();
+        }
     }
 
   // UID
@@ -533,32 +719,34 @@
   rom_chip->init();
   memchips->add(rom_chip);*/
 
-  ram_chip= new cl_memory_chip("ram_chip", 0x1800, 8);
+  ram_chip= new cl_chip8("ram_chip", 0x1800, 8);
   ram_chip->init();
   memchips->add(ram_chip);
-  eeprom_chip= new cl_memory_chip("eeprom_chip", 0x0800, 8, 0);
+  eeprom_chip= new cl_chip8("eeprom_chip", 0x0800, 8, 0);
   eeprom_chip->init();
   memchips->add(eeprom_chip);
-  option_chip= new cl_memory_chip("option_chip", 0x0800, 8, 0);
+  option_chip= new cl_chip8("option_chip", 0x0800, 8, 0);
   option_chip->init();
   memchips->add(option_chip);
-  io_chip= new cl_memory_chip("io_chip", 0x0800, 8);
+  io_chip= new cl_chip8("io_chip", 0x0800, 8);
   io_chip->init();
   memchips->add(io_chip);
   if (type->subtype & DEV_STM8S105)
-    boot_chip= new cl_memory_chip("boot_chip_s105", bl_s105_length, 8, bl_s105);
+    boot_chip= new cl_chip8("boot_chip_s105",
+			    bl_s105_length, 8, bl_s105, bl_s105_length);
   else if (type->subtype & DEV_STM8L15x46)
-    boot_chip= new cl_memory_chip("boot_chip_l15x46", bl_l15x46_length, 8, bl_l15x46);
+    boot_chip= new cl_chip8("boot_chip_l15x46",
+			    bl_l15x46_length, 8, bl_l15x46, bl_l15x46_length);
   /*else if (type->subtype & DEV_STM8L101)
     boot_chip= new cl_memory_chip("boot_chip_l101", bl_l15x46_length, 8, bl_l15x46);*/
   else
-    boot_chip= new cl_memory_chip("boot_chip", 0x0800, 8);
+    boot_chip= new cl_chip8("boot_chip", 0x0800, 8);
   boot_chip->init();
   memchips->add(boot_chip);
-  cpu_chip= new cl_memory_chip("cpu_chip", 0x0100, 8);
+  cpu_chip= new cl_chip8("cpu_chip", 0x0100, 8);
   cpu_chip->init();
   memchips->add(cpu_chip);
-  flash_chip= new cl_memory_chip("flash_chip", 0x20000, 8, 0);
+  flash_chip= new cl_chip8("flash_chip", 0x20000, 8, 0);
   flash_chip->init();
   memchips->add(flash_chip);
   /*
@@ -624,18 +812,19 @@
   address_spaces->add(regs8);
   address_spaces->add(regs16);
 
-  class cl_var *v;
-  vars->add(v= new cl_var(cchars("A"), regs8, 0, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("CC"), regs8, 1, ""));
-  v->init();
+  vars->add("A",     regs8, 0, 7, 0, "Accumulator");
+  vars->add("CC",    regs8, 1, -1, -1, "Condition Code");
+  vars->add("CC_C",  regs8, 1, BITPOS_C,  BITPOS_C,  "Carry");
+  vars->add("CC_Z",  regs8, 1, BITPOS_Z,  BITPOS_Z,  "Zero");
+  vars->add("CC_N",  regs8, 1, BITPOS_N,  BITPOS_N,  "Negative");
+  vars->add("CC_I0", regs8, 1, BITPOS_I0, BITPOS_I0, "Interrupt mask level 0");
+  vars->add("CC_H",  regs8, 1, BITPOS_H,  BITPOS_H,  "Half carry");
+  vars->add("CC_I1", regs8, 1, BITPOS_I1, BITPOS_I1, "Interrupt mask level 1");
+  vars->add("CC_V",  regs8, 1, BITPOS_V,  BITPOS_V,  "Overflow");
   
-  vars->add(v= new cl_var(cchars("X"), regs16, 0, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("Y"), regs16, 1, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("SP"), regs16, 2, ""));
-  v->init();
+  vars->add("X",  regs16, 0, 15, 0, "X index register");
+  vars->add("Y",  regs16, 1, 15, 0, "Y index register");
+  vars->add("SP", regs16, 2, 15, 0, "Stack pointer");
 }
 
 
@@ -709,7 +898,6 @@
   const char *b = NULL;
   uint code;
   int len = 0;
-  int immed_n = 0;
   int i;
   int start_addr = addr;
   struct dis_entry *dis_e;
@@ -796,11 +984,8 @@
     *ret_branch = dis_e->branch;
   }
 
-  if (immed_offset) {
-    if (immed_n > 0)
-         *immed_offset = immed_n;
-    else *immed_offset = (addr - start_addr);
-  }
+  if (immed_offset)
+    *immed_offset = (addr - start_addr);
 
   if (len == 0)
     len = 1;
@@ -814,145 +999,320 @@
   return b;
 }
 
+void
+cl_stm8::analyze_start(void)
+{
+  // Look for interrupts that _are_ interrupts. Nothing stops you from
+  // using the space for other code or data if the interrupts aren't needed.
+
+  // First those for elements that are implemented in the simulator
+  for (t_index i = 0; i < it_sources->count; i++)
+    {
+      class cl_it_src *is= (class cl_it_src *)(it_sources->at(i));
+
+      t_addr addr = is->addr;
+
+      if (rom->get(addr) == 0x82) // int
+        {
+          addr = (rom->get(is->addr+1)<<16) |
+                  (rom->get(is->addr+2)<<8) |
+                  (rom->get(is->addr+3));
+
+          t_index var_i;
+          if (!vars->by_addr.search(rom, addr, -1, -1, var_i))
+            {
+              chars label;
+
+              if (rom->get(addr) == 0x80) // jumps straight to iret
+                label.format("%s", ".isr_unused");
+              else
+                label.format(".%s", is->get_name());
+
+              class cl_var *v = new cl_var(label.subst(" ", '_'), rom, addr, chars("Auto-generated by analyze"), -1, -1);
+              v->init();
+              vars->add(v);
+            }
+
+          analyze(is->addr);
+        }
+    }
+
+  // And now for everything else. One day this will be nothing but reset :-)
+  for (t_addr is_addr = 0x8000; is_addr <= 0x807c; is_addr += 4)
+    {
+      if (!inst_at(is_addr) && rom->get(is_addr) == 0x82) // int
+        {
+          t_addr addr = (rom->get(is_addr+1)<<16) |
+                    (rom->get(is_addr+2)<<8) |
+                    (rom->get(is_addr+3));
+
+          t_index var_i;
+          if (!vars->by_addr.search(rom, addr, -1, -1, var_i))
+            {
+              chars label;
+
+              if (is_addr == 0x8000)
+                label.format("%s", ".reset");
+              else if (rom->get(addr) == 0x80) // jumps straight to iret
+                label.format("%s", ".isr_unused");
+              else if (is_addr == 0x8004)
+                label.format("%s", ".trap");
+              else
+                label.format("%s%lu", ".interrupt", ((unsigned long)is_addr - 0x8008) / 4);
+
+              class cl_var *v = new cl_var(label, rom, addr, chars("Auto-generated by analyze"), -1, -1);
+              v->init();
+              vars->add(v);
+            }
+
+          analyze(is_addr);
+        }
+    }
+}
+
+void
+cl_stm8::analyze(t_addr addr)
+{
+  const char *mnemonic;
+  int length = 0, branch = 0, immed_offset = 0;
+
+  while (!inst_at(addr) && (mnemonic = get_disasm_info(addr, &length, &branch, &immed_offset, NULL)))
+    {
+      set_inst_at(addr);
+
+      // Returns or indirect jumps end this execution path immediately
+      if (branch == 'x')
+        break;
+
+      if (branch != ' ')
+        {
+          t_addr target = 0;
+          unsigned int bit= 0;
+
+          // With jumps, branches and calls the target address is always
+          // given by the last operand. We just need to find it.
+          for (const char *b = mnemonic; *b; b++)
+            {
+              if (b[0] == '%' && b[1])
+                {
+                  b++;
+                  switch (*b)
+                    {
+                      case '3': // 3    24bit index offset
+                        ++immed_offset;
+                       // Fall through
+                      case '2': // 2    word index offset
+                      case 'w': // w    word immediate operand
+                        ++immed_offset;
+                        // Fall through
+                      case '1': // b    byte index offset
+                      case 'b': // b    byte immediate operand
+                      case 'd': // d    direct addressing
+                      case 's': // s    signed byte immediate
+                        ++immed_offset;
+                        break;
+
+                      case 'B': // B    bit number
+                        bit = (rom->get(addr+1) & 0xf) >> 1;
+                        break;
+
+                      case 'e': // e    extended 24bit immediate operand
+                        target= ((rom->get(addr+immed_offset)<<16) |
+                                  (rom->get(addr+immed_offset+1)<<8) |
+                                  (rom->get(addr+immed_offset+2)));
+                        ++immed_offset;
+                        ++immed_offset;
+                        ++immed_offset;
+                        break;
+                      case 'x': // x    extended addressing
+                        target= ((rom->get(addr+immed_offset)<<8) |
+                                  (rom->get(addr+immed_offset+1)));
+                        ++immed_offset;
+                        ++immed_offset;
+                        break;
+                      case 'p': // p    pc relative
+                        {
+                          long int base;
+                          i8_t offs;
+                          base= addr+immed_offset+1;
+                          offs= rom->get(addr+immed_offset);
+                          target= base+offs;
+                          ++immed_offset;
+                        }
+                        break;
+                      default:
+                        break;
+                    }
+                }
+            }
+
+          analyze_jump(addr, target, branch, bit);
+
+          // Unconditional jumps end this execution path
+          if (branch == 'j')
+            break;
+        }
+
+      addr= rom->validate_address(addr + length);
+    }
+}
+
 char *
-cl_stm8::disass(t_addr addr, const char *sep)
+cl_stm8::disass(t_addr addr)
 {
-  char work[256], temp[20];
+  const class cl_var *context = 0;
+  chars work, temp;
   const char *b;
-  char *buf, *p, *t;
   int len = 0;
   int immed_offset = 0;
+  t_addr operand= 0;
+  bool first= true;
 
-
-  p= work;
+  work= "";
 
   b = get_disasm_info(addr, &len, NULL, &immed_offset, NULL);
 
-  if (b == NULL) {
-    buf= (char*)malloc(30);
-    strcpy(buf, "UNKNOWN/INVALID");
-    return(buf);
-  }
+  if (b == NULL)
+    {
+      return strdup("UNKNOWN/INVALID");
+    }
 
+  int operand_n = 0;
   while (*b)
     {
+      if ((*b == ' ') && first)
+	{
+	  first= false;
+	  while (work.len() < 6) work.append(' ');
+	}
       if (*b == '%')
         {
+
           b++;
           switch (*(b++))
             {
             case 's': // s    signed byte immediate
-              sprintf(temp, "#%d", (char)rom->get(addr+immed_offset));
+              temp.format("#%d", (i8_t)rom->get(addr+immed_offset));
               ++immed_offset;
               break;
             case 'e': // e    extended 24bit immediate operand
-              sprintf(temp, "#0x%06lx",
-                 (ulong)((rom->get(addr+immed_offset)<<16) |
-                        (rom->get(addr+immed_offset+1)<<8) |
-                        (rom->get(addr+immed_offset+2))) );
+	      operand= ((rom->get(addr+immed_offset)<<16) |
+			  (rom->get(addr+immed_offset+1)<<8) |
+			  (rom->get(addr+immed_offset+2)));
+              temp.format("#0x%06lx", operand);
+              addr_name(operand, rom, &temp);
               ++immed_offset;
               ++immed_offset;
               ++immed_offset;
               break;
             case 'w': // w    word immediate operand
-              sprintf(temp, "#0x%04x",
-                 (uint)((rom->get(addr+immed_offset)<<8) |
-                        (rom->get(addr+immed_offset+1))) );
+	      operand=  ((rom->get(addr+immed_offset)<<8) |
+			 (rom->get(addr+immed_offset+1)));
+              temp.format("#0x%04x", operand);
+              addr_name(operand, rom, &temp);
               ++immed_offset;
               ++immed_offset;
               break;
             case 'b': // b    byte immediate operand
-              sprintf(temp, "#0x%02x", (uint)rom->get(addr+immed_offset));
+              operand= (uint)rom->get(addr+immed_offset);
+              temp.format("#0x%02x", operand);
+              addr_name(operand, rom, &temp);
               ++immed_offset;
               break;
             case 'x': // x    extended addressing
-              sprintf(temp, "0x%04x",
-                 (uint)((rom->get(addr+immed_offset)<<8) |
-                        (rom->get(addr+immed_offset+1))) );
-              ++immed_offset;
-              ++immed_offset;
+              if (rom->get(addr) == 0x35) // mov %x,%b - mov $8000,#$ff is 35 ff 80 00
+                operand= (uint)((rom->get(addr+immed_offset+1)<<8) |
+                           (rom->get(addr+immed_offset+2)));
+              else if (rom->get(addr) == 0x55 && operand_n == 0) // mov %x,%x - mov $8000,$9fff is 9f ff 80 00
+                operand= (uint)((rom->get(addr+immed_offset+2)<<8) |
+                           (rom->get(addr+immed_offset+3)));
+              else
+                {
+                  operand= (uint)((rom->get(addr+immed_offset)<<8) |
+                             (rom->get(addr+immed_offset+1)));
+                  ++immed_offset;
+                  ++immed_offset;
+                }
+              temp.format("0x%04x", operand);
+              context = addr_name(operand, rom, &temp);
               break;
             case 'd': // d    direct addressing
-              sprintf(temp, "0x%02x", (uint)rom->get(addr+immed_offset));
-              ++immed_offset;
+              if (rom->get(addr) == 0x45 && operand_n == 0) // mov %d,%d - mov $80,$10 is 45 10 80
+                  operand= (uint)rom->get(addr+immed_offset+1);
+              else
+                {
+                  operand= (uint)rom->get(addr+immed_offset);
+                  ++immed_offset;
+                }
+              temp.format("0x%02x", operand);
               break;
             case '3': // 3    24bit index offset
-              sprintf(temp, "0x%06lx",
-                 (ulong)((rom->get(addr+immed_offset)<<16) |
-                        (rom->get(addr+immed_offset+1)<<8) |
-                        (rom->get(addr+immed_offset+2))) );
+              // Assumption: the 24bit offset address is the address of a
+              // fixed table and the index register selects an entry.
+	      operand= (ulong)((rom->get(addr+immed_offset)<<16) |
+			  (rom->get(addr+immed_offset+1)<<8) |
+			  (rom->get(addr+immed_offset+2)));
+              temp.format("0x%06lx", operand);
+              addr_name(operand, rom, &temp);
               ++immed_offset;
               ++immed_offset;
               ++immed_offset;
-             break;
+              break;
             case '2': // 2    word index offset
-              sprintf(temp, "0x%04x",
-                 (uint)((rom->get(addr+immed_offset)<<8) |
-                        (rom->get(addr+immed_offset+1))) );
+              // Assumption: the word offset address is the address of a
+              // fixed table and the index register selects an entry.
+	      operand= (uint)((rom->get(addr+immed_offset)<<8) |
+			 (rom->get(addr+immed_offset+1)));
+              temp.format("0x%04x", operand);
+              addr_name(operand, rom, &temp);
               ++immed_offset;
               ++immed_offset;
               break;
             case '1': // b    byte index offset
-              sprintf(temp, "0x%02x", (uint)rom->get(addr+immed_offset));
+              // Assumption: the index register points to a struct/record
+              // and the byte offset selects an entry.
+              operand= (uint)rom->get(addr+immed_offset);
+              temp.format("0x%02x", operand);
+              addr_name(operand, rom, &temp);
               ++immed_offset;
               break;
-            case 'p': // b    byte index offset
-	      {
-		long int base;
-		i8_t offs;
-		base= addr+immed_offset+1;
-		offs= rom->get(addr+immed_offset);
-		long int res= base+offs;
-		sprintf(temp, "0x%04lx",
-			/*(long int)(addr+immed_offset+1
-			  +(int)rom->get(addr+immed_offset))*/
-			res
-			);
-		++immed_offset;
-	      }
+            case 'p': // p    pc relative
+              operand = (addr+immed_offset+1 + (i8_t)rom->get(addr+immed_offset)) & 0xffff;
+              temp.format("0x%04lx", operand);
+              addr_name(operand, rom, &temp);
+              ++immed_offset;
+              break;
+            case 'B': // B    bit number
+              {
+                uint bit = (rom->get(addr+1) & 0xf) >> 1;
+                temp.format("%u", bit);
+                // N.B. The address comes before the bit so operand has already
+                // been set to the address when we get here.
+                addr_name(operand, rom, bit, bit, &temp, context);
+              }
               break;
             default:
-              strcpy(temp, "?");
+	      temp= "?";
               break;
             }
-          t= temp;
-          while (*t)
-            *(p++)= *(t++);
+	  work+= temp;
         }
       else
-        *(p++)= *(b++);
+        {
+          if (*b == ',')
+            operand_n++;
+          work+= *(b++);
+        }
     }
-  *p= '\0';
 
-  p= strchr(work, ' ');
-  if (!p)
-    {
-      buf= strdup(work);
-      return(buf);
-    }
-  if (sep == NULL)
-    buf= (char *)malloc(6+strlen(p)+1);
-  else
-    buf= (char *)malloc((p-work)+strlen(sep)+strlen(p)+1);
-  for (p= work, t= buf; *p != ' '; p++, t++)
-    *t= *p;
-  p++;
-  *t= '\0';
-  if (sep == NULL)
-    {
-      while (strlen(buf) < 6)
-        strcat(buf, " ");
-    }
-  else
-    strcat(buf, sep);
-  strcat(buf, p);
-  return(buf);
+  return strdup(work.c_str());
 }
 
 
 void
 cl_stm8::print_regs(class cl_console_base *con)
 {
+  con->dd_color("answer");
   con->dd_printf("V-IHINZC  Flags= 0x%02x %3d %c  ",
                  regs.CC, regs.CC, isprint(regs.CC)?regs.CC:'.');
   con->dd_printf("A= 0x%02x %3d %c\n",
@@ -969,9 +1329,10 @@
                  regs.X, regs.X, isprint(regs.X)?regs.X:'.');
   con->dd_printf("Y= 0x%04x %3d %c\n",
                  regs.Y, regs.Y, isprint(regs.Y)?regs.Y:'.');
-  con->dd_printf("SP= 0x%04x [SP+1]= %02x %3d %c\n",
+  con->dd_printf("SP= 0x%04x [SP+1]= %02x %3d %c  Limit= 0x%04x\n",
                  regs.SP, ram->get(regs.SP+1), ram->get(regs.SP+1),
-                 isprint(ram->get(regs.SP+1))?ram->get(regs.SP+1):'.');
+                 isprint(ram->get(regs.SP+1))?ram->get(regs.SP+1):'.',
+		 AU(sp_limit));
 
   print_disass(PC, con);
 }
@@ -980,6 +1341,99 @@
  * Execution
  */
 
+// There are three clocks derived from each other. f_OSC is
+// the oscillator frequency. This is then scaled down to give
+// the master clock, f_MASTER, which is the clock used to drive
+// the hardware elements. This, in turn, is further scaled down
+// to give the CPU clock, f_CPU, which is used to drive the CPU.
+// Only some variants of STM8 support both scaling factors and
+// both factors and f_OSC can be changed programmatically.
+
+int
+cl_stm8::clock_per_cycle(void)
+{
+  return clk->clock_per_cycle();
+}
+
+int
+cl_stm8::tick_hw(int cycles_cpu)
+{
+  if (state != stPD)
+    cl_uc::tick_hw(cycles_cpu * clock_per_cycle());
+
+  return 0;
+}
+
+int
+cl_stm8::tick(int cycles_cpu)
+{
+  if (state != stPD)
+    {
+      for (int i = 0; i < cycles_cpu; i++, pipetrace_ticks++)
+        {
+          // Refill the pipeline if there is space and we didn't use the memory this tick.
+          if (pipeline_bytes >= 9)
+              pipetrace_tick(NULL);
+          else
+            {
+              class cl_address_decoder *d = rom->get_decoder_of(PC);
+              if (d && !(d->memchip != flash_chip ? pipeline_busy.data : pipeline_busy.program))
+                {
+                  int step = (d->memchip != flash_chip ? 1 : 4);
+                  pipetrace_tick("F");
+                  pipeline_bytes += step;
+                }
+              // If the other bus is not busy this is a genuine stall due to running out of fetch data
+              else if (!pipeline_busy.program || !pipeline_busy.data)
+                {
+                  error(new cl_error_stm8_pipeline_fetch_stall());
+                  pipetrace_tick("FS");
+                }
+              // Otherwise if both buses are busy there was a flush and the stall is expected
+              else
+                pipetrace_tick(NULL);
+            }
+        }
+
+      pipeline_busy.program = false;
+      pipeline_busy.data = false;
+      pipeline_busy.regs = false;
+      if (pipetrace_ticks > pipetrace_max_ticks)
+        pipetrace_max_ticks = pipetrace_ticks;
+    }
+
+  return cl_uc::tick(cycles_cpu);
+}
+
+t_mem
+cl_stm8::fetch(void)
+{
+  if (!div_cycle)
+    {
+      if (pipeline_bytes - (pipeline_index & ~3) < 4)
+        {
+          // We have to have a full word before we can use any of it.
+          while (pipeline_bytes - (pipeline_index & ~3) < 4)
+            {
+              error(new cl_error_stm8_pipeline_decode_stall());
+              pipetrace_type("Sfetch");
+              tick(1);
+              pipetrace_type("D");
+            }
+        }
+
+      pipeline_index++;
+    }
+
+  return cl_uc::fetch();
+}
+
+bool
+cl_stm8::fetch(t_mem *code)
+{
+  return cl_uc::fetch(code);
+}
+
 int
 cl_stm8::exec_inst(void)
 {
@@ -1001,11 +1455,26 @@
 
   instPC= PC;
 
-  if (fetch(&code)) {
-    //printf("******************** break \n");
-	  return(resBREAKPOINT);
-  }
-  tick(1);
+  if (do_brk())
+    return(resBREAKPOINT);
+
+  if (!div_cycle)
+    {
+      pipetrace_instr_end();
+      pipetrace_instr_start(instPC);
+
+      // If there was a flush in this cycle nothing happens in the overlapped cycle
+      if (pipeline_busy.flush)
+        tick(1);
+
+      pipeline_busy.flush = false;
+      pipetrace_type("D");
+    }
+
+  code = fetch();
+
+  if (!div_cycle)
+    pipeline_busy.instr = false;
 
   switch (code)
     { // get prefix
@@ -1014,17 +1483,25 @@
     case 0x91:
     case 0x92:
       cprefix = code;
-      fetch(&code);
+      code = fetch();
       break;
-    case 0x82:
+    case 0x82: // INT
       {
 	int ce= fetch();
 	int ch= fetch();
 	int cl= fetch();
+	// Documentation is unclear but we treat it as JP and allow
+	// the prefetch of the next instruction to occur during the
+	// execute tick.
+	pipeline_flush(true);
 	PC= ce*0x10000 + ch*0x100 + cl;
 	return resGO;
       }
-    case 0x8b: return resSTOP; // BREAK instruction
+    case 0x8b: // BREAK
+      {
+        store_regs();
+        return resSTOP;
+      }
     default:
       cprefix = 0x00;
       break;
@@ -1086,6 +1563,7 @@
                pop2( regs.Y);
                pop1( tempi);
                pop2( PC);
+               store_regs();
                PC += (tempi <<16); //Add PCE to PC
 	       {
 		 class it_level *il= (class it_level *)(it_levels->top());
@@ -1096,6 +1574,8 @@
 		     delete il;
 		   }
 	       }
+	       div_cycle = 0;
+	       pipeline_flush(false);
                return(resGO);
             case 0x10: 
             case 0xA0:
@@ -1113,6 +1593,7 @@
       case 0x1:
          switch ( code & 0xf0) {
             case 0x00: // RRWA
+               store_regs();
                if (cprefix == 0x00) { // rrwa X,A
                   tempi = regs.X;
                   regs.X >>= 8;
@@ -1135,20 +1616,27 @@
             case 0x30: // exg A,longmem
                opaddr = fetch2();
                tempi = get1(opaddr);
+               // FIXME: PM0044 says 3 cycles so the stores are in separate cycles
+               // rather than overlapped. But which comes first?
                store1( opaddr, regs.A);
+               exec_cycle();
+               store_regs();
                regs.A = tempi;
                return(resGO);
             case 0x40: // exg A,XL
+               store_regs();
                tempi = regs.X;
                regs.X = (regs.X &0xff00) | regs.A;
                regs.A = tempi & 0xff;
                return(resGO);
             case 0x50: // exgw X,Y
+               store_regs();
                tempi = regs.Y;
                regs.Y = regs.X;
                regs.X = tempi;
                return(resGO);
             case 0x60: // exg A,YL
+               store_regs();
                tempi = regs.Y;
                regs.Y = (regs.Y &0xff00) | regs.A;
                regs.A = tempi & 0xff;
@@ -1156,14 +1644,20 @@
             case 0x70: // special opcodes
                code = fetch();
                switch(code) {
-                  case 0xEC: return(resHALT);
-                  case 0xED: putchar(regs.A); fflush(stdout); return(resGO);
+                  case 0xEC: exec_cycle(); return(resHALT);
+                  case 0xED: exec_cycle(); putchar(regs.A); fflush(stdout); return(resGO);
                   default:
 		    //printf("************* bad code !!!!\n");
                      return(resINV_INST);
                }
             case 0x80: // ret
                pop2( PC);
+               // PM0044: 5.4.3: For the CALL instruction, it [the fetch of the next
+               // instruction] starts after the last cycle of the CALL execution.
+               // Although nothing is mentioned for RET PM0044 says it takes 4 cycles
+               // which implies the fetch follows the last execute cycle.
+               exec_cycle();
+               pipeline_flush(false);
                return(resGO);
             case 0x10: 
             case 0xA0:
@@ -1183,6 +1677,7 @@
          switch ( code & 0xf0) {
             case 0x00: // RLWA
                if (cprefix == 0x00) { // rlwa X,A
+                  store_regs();
                   tempi = regs.X;
                   regs.X <<= 8;
                   regs.X |= regs.A ;
@@ -1190,6 +1685,7 @@
                   FLAG_ASSIGN (BIT_N, 0x8000 & regs.X);
                   FLAG_ASSIGN (BIT_Z, regs.X == 0x0000);
                } else if (cprefix == 0x90) { // rlwa Y,A
+                  store_regs();
                   tempi = regs.Y;
                   regs.Y <<= 8;
                   regs.Y |= regs.A ;
@@ -1207,7 +1703,13 @@
                store1(opaddr, tempi);
                return(resGO);
             case 0x40: // mul
-               tick(3);
+               // mul low, [store low, mul high], add carry, store high
+               // with the store of the low byte result and the multiply of the
+               // high byte overlapped.
+               exec_cycle();
+               exec_cycle();
+               exec_cycle();
+               store_regs();
                if(cprefix==0x90) {
                   regs.Y = (regs.Y&0xff) * regs.A;
                } else if(cprefix==0x00) {
@@ -1220,8 +1722,12 @@
                return(resGO);
                break;
             case 0x50: // sub sp,#val
-               regs.SP -= fetch();
-               return(resGO);
+               {
+                 t_mem v = fetch();
+                 store_regs();
+                 regs.SP -= v;
+                 return(resGO);
+               }
                break;            
             case 0x60: //div
                return(inst_div(code, cprefix));
@@ -1256,7 +1762,9 @@
 		 accept_it(il);
 	       }
                return(/*resHALT*/resGO);
-            case 0x90:
+            case 0x90: // EXGW
+               get_regs();
+               store_regs();
                if(cprefix==0x90) {
                   regs.Y = regs.X;
                } else if(cprefix==0x00) {
@@ -1290,10 +1798,12 @@
             case 0x70: // SRL
                return( inst_srl( code, cprefix));
                break;
-            case 0x80: 
-               pop1( regs.A);
+            case 0x80: // POP A
+	       get_regs();
+               pop1(regs.A);
                return(resGO);
-            case 0x90:
+            case 0x90: // LDW SP,[XY]
+               store_regs();
                if(cprefix==0x90) {
                   regs.SP = regs.Y;
                } else if(cprefix==0x00) {
@@ -1350,7 +1860,8 @@
                }
                return(resGO);
                break;
-            case 0x90:
+            case 0x90: // LD [XY]H,A
+               store_regs();
                if(cprefix==0x90) {
                   regs.Y = (regs.Y & 0xff) | (regs.A<<8);
                } else if(cprefix==0x00) {
@@ -1390,7 +1901,8 @@
             case 0x80: 
                pop1( regs.CC);
                return(resGO);
-            case 0x90:
+            case 0x90: // LDW [XY],SP
+               store_regs();
                if(cprefix==0x90) {
                   regs.Y = regs.SP;
                } else if(cprefix==0x00) {
@@ -1434,8 +1946,15 @@
                pop1( tempi);
                pop2( PC);
                PC += (tempi <<16); //Add PCE to PC
+               // PM0044: 5.4.3: For the CALL instruction, it [the fetch of the next
+               // instruction] starts after the last cycle of the CALL execution.
+               // Although nothing is mentioned for RETF PM0044 says it takes 5 cycles
+               // which implies the fetch follows the last execute cycle.
+               exec_cycle();
+               pipeline_flush(false);
                return(resGO);
-            case 0x90:
+            case 0x90: // LD[XY]L,A
+	       store_regs();
                if(cprefix==0x90) {
                   regs.Y = (regs.Y & 0xff00) | regs.A;
                } else if(cprefix==0x00) {
@@ -1448,13 +1967,17 @@
             case 0xA0:
                opaddr = fetch2();
                if (cprefix == 0x92) {
-                  store1(get3(opaddr)+regs.X,regs.A);
+                  opaddr = get3(opaddr);
+                  store1(opaddr + regs.X,regs.A);
                } else if(cprefix==0x91) {
-                  store1(get3(opaddr)+regs.Y,regs.A);
+                  opaddr = get3(opaddr);
+                  store1(opaddr + regs.Y,regs.A);
                } else if(cprefix==0x90) {
-                  store1((opaddr << 8) + fetch() + regs.Y, regs.A);
+                  opaddr = (opaddr << 8) + fetch();
+                  store1(opaddr + regs.Y, regs.A);
                } else if(cprefix==0x00) {
-                  store1((opaddr << 8) + fetch() + regs.X, regs.A);
+                  opaddr = (opaddr << 8) + fetch();
+                  store1(opaddr + regs.X, regs.A);
                } else {
                   return(resHALT);
                }
@@ -1486,6 +2009,7 @@
                push1( regs.A);
                return(resGO);
             case 0x90: // RCF
+               exec_cycle();
                FLAG_CLEAR(BIT_C);
                return(resGO);
             case 0x10: 
@@ -1523,6 +2047,7 @@
                return(resGO);
                break;
             case 0x90: // SCF
+               exec_cycle();
                FLAG_SET(BIT_C);
                return(resGO);
             case 0x10: 
@@ -1553,6 +2078,7 @@
                push1( regs.CC);
                return(resGO);
             case 0x90: // RIM
+               exec_cycle();
                FLAG_CLEAR(BIT_I0);
                FLAG_SET(BIT_I1);
                return(resGO);
@@ -1573,28 +2099,43 @@
       case 0xb:
          switch ( code & 0xf0) {
             case 0x30: // push longmem
-               push1( get1(fetch2()));
-               return(resGO);
+	      {
+		t_addr a= fetch2();
+		t_mem v= get1(a);
+		push1( v /*get1(fetch2())*/);
+		return(resGO);
+	      }
             case 0x40: // push #byte
-               push1( fetch1());
-               return(resGO);
+	      {
+		t_mem v= fetch1();
+		push1(v);
+		return(resGO);
+	      }
             case 0x50: // addw sp,#val
-               regs.SP += fetch1();
+               tempi = fetch1();
+               exec_cycle();
+               store_regs();
+               regs.SP += tempi;
                return(resGO);
                break;
             case 0x60: // ld (shortoff,SP),A
-               store1(fetch1()+regs.SP, regs.A);
+               tempi = fetch1();
+               store1(tempi + regs.SP, regs.A);
                FLAG_NZ(regs.A);
                return(resGO);
                break;
             case 0x70: // ld A,(shortoff,SP)
-               regs.A = get1(fetch1()+regs.SP);
+               tempi = get1(fetch1()+regs.SP);
+               store_regs();
+               regs.A = tempi;
                FLAG_NZ(regs.A);
                return(resGO);
                break;
             case 0x80: // BREAK
+               exec_cycle();
                return(resSTOP);
             case 0x90: // SIM - disable INT
+               exec_cycle();
                FLAG_SET(BIT_I0);
                FLAG_SET(BIT_I1);
                return(resGO);
@@ -1626,28 +2167,37 @@
                return( inst_addw( code, cprefix));
                break;
             case 0x80: // CCF
+               exec_cycle();
                regs.CC ^= BIT_C;
                return(resGO);
                break;            
             case 0x90: // RVF
+               exec_cycle();
                FLAG_CLEAR(BIT_V);
                return(resGO);
             case 0xA0: // JPF
                opaddr = fetch2();
+               // PM0044: 5.4.3: For a JP instruction, the fetch [of the next
+               // instruction] can start during the first cycle of the "dummy"
+               // execution.
                if (cprefix == 0x92) {
                   PC = get3(opaddr);
                } else {
                   PC = (opaddr << 8) + fetch();
                }
+               pipeline_flush(false);
                return(resGO);
                break;
-            case 0xb0: // LDF
+            case 0xb0: // LDF A,$eehhll or LDF A,[$eehhll.e]
                opaddr = fetch2();
                if (cprefix == 0x92) {
-                  regs.A = get1(get3(opaddr));
+                  tempi = get1(get3(opaddr));
+                  decode_cycle();
                } else {
-                  regs.A = get1((opaddr << 8) + fetch());
+                  tempi = get1((opaddr << 8) + fetch());
                }
+               store_regs();
+               regs.A = tempi;
                FLAG_NZ (regs.A);
                return(resGO);
                break;
@@ -1687,25 +2237,36 @@
                    push1(PC >> 16);
                    PC = (opaddr << 8) + c;
                }
+               // PM0044: 5.4.3: For the CALL instruction, it [the fetch of the next
+               // instruction] starts after the last cycle of the CALL execution.
+               exec_cycle();
+               pipeline_flush(false);
                return(resGO);
                break;
             case 0x90: // NOP
+               exec_cycle();
                return(resGO);
                break;
             case 0xA0: // CALLR
              {
                signed char c = (signed char) fetch1();
                push2(PC);
+               // PM0044: 5.4.3: For the CALL instruction, it [the fetch of the next
+               // instruction] starts after the last cycle of the CALL execution.
                PC += c;
+               exec_cycle();
+               pipeline_flush(false);
                return(resGO);
              }
                break;            
             case 0xb0: // LDF
                opaddr = fetch2();
                if (cprefix == 0x92) {
-                  store1(get3(opaddr),regs.A);
+                  tempi = get3(opaddr);
+                  store1(tempi, regs.A);
                } else {
-                  store1((opaddr << 8) + fetch(), regs.A);
+                  tempi = (opaddr << 8) + fetch();
+                  store1(tempi, regs.A);
                }
                FLAG_NZ (regs.A);
                return(resGO);
@@ -1733,15 +2294,18 @@
                break;
             case 0x80: 
 	      //printf("************* HALT instruction reached !!!!\n");
+               exec_cycle();
                return(resHALT);
             case 0x90: // LD A, YH / XH
                if(cprefix==0x90) {
-                  regs.A = (regs.Y >> 8) & 0xff;
+                  tempi = (regs.Y >> 8) & 0xff;
                } else if(cprefix==0x00) {
-                  regs.A = (regs.X >> 8) & 0xff;
+                  tempi = (regs.X >> 8) & 0xff;
                } else {
                   return(resHALT);
                }
+               store_regs();
+               regs.A = tempi;
                return(resGO);
                break;
             case 0x10: 
@@ -1775,21 +2339,25 @@
             case 0x80: 
 	      //printf("************* WFI/WFE instruction not implemented !!!!\n");
                return(resINV_INST);
-            case 0x90:
+            case 0x90: // LD A,[XY]L
                if(cprefix==0x90) {
-                  regs.A = (regs.Y & 0xff);
+                  tempi = (regs.Y & 0xff);
                } else if(cprefix==0x00) {
-                  regs.A = (regs.X & 0xff);
+                  tempi = (regs.X & 0xff);
                } else {
                   return(resHALT);
                }
+               store_regs();
+               regs.A = tempi;
                return(resGO);
             case 0xA0: // LDF
                opaddr = fetch2();
                if (cprefix == 0x92) {
                   regs.A = get1(get3(opaddr)+regs.X);
+                  decode_cycle();
                } else if(cprefix==0x91) {
                   regs.A = get1(get3(opaddr)+regs.Y);
+                  decode_cycle();
                } else if(cprefix==0x90) {
                   regs.A = get1((opaddr << 8) + fetch() + regs.Y);
                } else if(cprefix==0x00) {
@@ -1797,6 +2365,7 @@
                } else {
                   return(resHALT);
                }
+               store_regs();
                FLAG_NZ (regs.A);
                return(resGO);
             case 0xB0:
@@ -1895,7 +2464,9 @@
     { FLAG_CLEAR(BIT_I1) FLAG_CLEAR(BIT_I0) }
   else // 3
     { FLAG_SET(BIT_I1) FLAG_SET(BIT_I0) }
+
   PC = il->addr;
+  pipeline_flush(false);
 
   it_levels->push(il);
   return resGO;//resINTERRUPT;
@@ -1911,6 +2482,120 @@
   return !(regs.CC & BIT_I0) || !(regs.CC & BIT_I1);
 }
 
+void
+cl_stm8::stack_check_overflow(class cl_stack_op *op)
+{
+  if (op)
+    {
+      if (op->get_op() & stack_write_operation)
+	{
+	  t_addr a= op->get_after();
+	  if (a < sp_limit)
+	    {
+	      class cl_error_stack_overflow *e=
+		new cl_error_stack_overflow(op);
+	      e->init();
+	      error(e);
+	    }
+	}
+    }
+}
+
+void
+cl_stm8::pipetrace_end_table(void)
+{
+  fputs("\" />\n"
+        "    \n"
+        "    \n"
+        "        AddressInstruction",
+        pipetrace_fd);
+
+  for (unsigned int i = 1; i <= pipetrace_max_ticks + 1; i++)
+    fprintf(pipetrace_fd, "%u", i);
+
+  fputs("\n"
+        "    \n"
+        "\n"
+        "\n\n",
+        pipetrace_fd);
+
+  pipetrace_in_table = false;
+}
+
+void
+cl_stm8::pipetrace_instr_start(t_addr addr)
+{
+  if (pipetrace_running)
+    {
+      if (!pipetrace_in_table)
+        {
+          fputs("\n"
+                "\n"
+                "    \n",
+                pipetrace_fd);
+          pipetrace_in_table = true;
+          pipetrace_max_ticks = 0;
+        }
+
+      if (pipeline_busy.flush)
+        fputs("        \n", pipetrace_fd);
+
+      fputs("        \n", pipetrace_fd);
+}
+
+void
+cl_stm8::pipetrace_tick(const char *aux)
+{
+  if (pipetrace_running)
+    {
+      fputs("\">", pipetrace_fd);
+      if (aux) fprintf(pipetrace_fd, "", aux);
+      fputs(" 
", pipetrace_fd);
+      fprintf(pipetrace_fd, rom->addr_format, addr);
+      fprintf(pipetrace_fd, " ");
+      const char *s = disass(addr);
+      while (*s)
+        {
+          int n = strcspn(s, "<>");
+          fprintf(pipetrace_fd, "%*.*s", n, n, s);
+          s += n;
+
+          switch (*s) {
+            case '<':
+              fprintf(pipetrace_fd, "<");
+              s++;
+              break;
+
+            case '>':
+              fprintf(pipetrace_fd, ">");
+              s++;
+              break;
+
+            default:
+              // Not possible
+              break;
+          }
+        }
+      fprintf(pipetrace_fd, " 
rom, 0x7f00+i);
     }
+  cl_var *v;
+  uc->vars->add(v= new cl_var(chars("sp_limit"), cfg, cpuconf_sp_limit,
+			      cfg_help(cpuconf_sp_limit)));
+  v->init();
+  
   return 0;
 }
 
 void
+cl_stm8_cpu::set_cmd(class cl_cmdline *cmdline, class cl_console_base *con)
+{
+  class cl_stm8 *stm8 = static_cast(uc);
+  const char *p1, *p2;
+
+  if (cmdline->syntax_match(uc, STRING STRING))
+    {
+      if ((p1 = cmdline->param(0)->value.string.string) &&
+          strstr(p1, "pi") == p1 &&
+          (p1 = cmdline->param(1)->value.string.string))
+        {
+          if (strstr(p1, "paus") == p1)
+            {
+              if (stm8->pipetrace_running)
+                {
+                  if (stm8->pipetrace_in_table)
+                    stm8->pipetrace_end_table();
+                  stm8->pipetrace_running = false;
+                }
+              else if (!stm8->pipetrace_fd)
+                con->dd_printf("Not currently tracing pipeline acivity\n");
+              return;
+            }
+          else if (strstr(p1, "re") == p1)
+            {
+              if (!stm8->pipetrace_running)
+                {
+                  if (stm8->pipetrace_fd)
+                    {
+                      stm8->pipetrace_ticks = 0;
+                      stm8->pipetrace_running = true;
+                    }
+                  else
+                    con->dd_printf("Not currently tracing pipeline acivity\n");
+                }
+              return;
+            }
+          else if (!strcmp(p1, "stop") || !strcmp(p1, "close"))
+            {
+              if (stm8->pipetrace_running)
+                {
+                  if (stm8->pipetrace_in_table)
+                    stm8->pipetrace_end_table();
+                  stm8->pipetrace_running = false;
+                }
+              if (stm8->pipetrace_fd)
+                {
+                  fputs("\n\n", stm8->pipetrace_fd);
+                  fclose(stm8->pipetrace_fd);
+                }
+              if (stm8->pipetrace_file)
+                free(stm8->pipetrace_file);
+              stm8->pipetrace_fd = NULL;
+              stm8->pipetrace_file= NULL;
+              return;
+            }
+        }
+    }
+  else if (cmdline->syntax_match(uc, STRING STRING STRING))
+    {
+      if ((p1 = cmdline->param(0)->value.string.string) &&
+          !strcmp(p1, "pipetrace") &&
+          (p1 = cmdline->param(1)->value.string.string) &&
+          (p2 = cmdline->param(2)->value.string.string))
+        {
+          if (!strcmp(p1, "fold") || !strcmp(p1, "folding"))
+            {
+              if (!strcmp(p2, "on"))
+                {
+                  stm8->pipetrace_fold = true;
+                  return;
+                }
+              else if (!strcmp(p2, "off"))
+                {
+                  stm8->pipetrace_fold = false;
+                  return;
+                }
+            }
+          else if (!strcmp(p1, "title"))
+            {
+              if (stm8->pipetrace_title)
+                free(stm8->pipetrace_title);
+              stm8->pipetrace_title = strdup(p2);
+              return;
+            }
+	  else if (!strcmp(p1, "style"))
+            {
+              if (stm8->pipetrace_style)
+                free(stm8->pipetrace_style);
+              stm8->pipetrace_style = strdup(p2);
+              return;
+            }
+          else if (!strcmp(p1, "data") || !strcmp(p1, "text"))
+            {
+              if (stm8->pipetrace_fd)
+                {
+                  if (stm8->pipetrace_in_table)
+                    stm8->pipetrace_end_table();
+                  fputs(p2, stm8->pipetrace_fd);
+                  putc('\n', stm8->pipetrace_fd);
+                  stm8->pipetrace_ticks = 0;
+                }
+              else
+                  con->dd_printf("Not currently tracing pipeline acivity\n");
+              return;
+            }
+          else if (!strcmp(p1, "start") || !strcmp(p1, "output") || !strcmp(p1, "file"))
+            {
+              if (stm8->pipetrace_fd)
+                {
+                  con->dd_printf("Already writing pipeline trace to \"%s\". Close this first.\n", stm8->pipetrace_file);
+                  return;
+                }
+
+              if (stm8->pipetrace_file)
+                {
+                  free(stm8->pipetrace_file);
+                  stm8->pipetrace_file = NULL;
+                }
+              stm8->pipetrace_file = NULL;
+
+              if ((stm8->pipetrace_fd = fopen(p2, "w")) == NULL)
+                con->dd_printf("Can't open `%s': %s\n", p2, strerror(errno));
+              else
+                stm8->pipetrace_file = strdup(p2);
+
+              fprintf(stm8->pipetrace_fd, "\n\n");
+
+              if (stm8->pipetrace_title && stm8->pipetrace_title[0])
+                fprintf(stm8->pipetrace_fd, "%s\n", stm8->pipetrace_title);
+
+              if (stm8->pipetrace_style && stm8->pipetrace_style[0])
+                fprintf(stm8->pipetrace_fd, "\n", stm8->pipetrace_style);
+              else
+                fprintf(stm8->pipetrace_fd,
+                  "\n"
+                  "\n"
+                  "\n");
+
+              fputs(
+                "\n"
+                "\n"
+                "\n",
+                stm8->pipetrace_fd);
+
+              if (stm8->pipetrace_title)
+                fprintf(stm8->pipetrace_fd, "\n%s\n", stm8->pipetrace_title);
+
+              fputs("\n"
+                "\n"
+                "    \n"
+                "    \n"
+                "    \n"
+                "    \n"
+                "    \n"
+                "    \n"
+                "    \n"
+                "    \n"
+                "    \n"
+                "Legend
Decode
Execute
Fetch
Flush
Fetch Stall - space in prefetch buffer but bus busy
Decode Stall - bus busy
Decode Stall - insufficient data in prefetch buffer
Decode Stall - read after write\n"
+                "\n",
+                stm8->pipetrace_fd);
+
+              stm8->pipetrace_ticks = 0;
+              stm8->pipetrace_running = true;
+              stm8->pipetrace_in_table = false;
+              return;
+            }
+        }
+    }
+
+    con->dd_printf("set hardware cpu[id] pipetrace title \"title\"\n");
+    con->dd_printf("set hardware cpu[id] pipetrace style \"url\"\n");
+    con->dd_printf("set hardware cpu[id] pipetrace start|output|file \"filename\"\n");
+    con->dd_printf("set hardware cpu[id] pipetrace pause\n");
+    con->dd_printf("set hardware cpu[id] pipetrace resume|restart\n");
+    con->dd_printf("set hardware cpu[id] pipetrace data \"html...\"\n");
+    con->dd_printf("set hardware cpu[id] pipetrace stop|close\n");
+    con->dd_printf("set hardware cpu[id] pipetrace fold on|off\n");
+}
+
+void
+cl_stm8_cpu::print_info(class cl_console_base *con)
+{
+  class cl_stm8 *stm8 = static_cast(uc);
+
+  con->dd_printf("%s[%d]\n", id_string, id);
+  con->dd_printf("  Pipetrace title: %s\n", (stm8->pipetrace_title ? stm8->pipetrace_title : ""));
+  con->dd_printf("  Pipetrace style: %s\n", (stm8->pipetrace_style ? stm8->pipetrace_style : ""));
+  con->dd_printf("  Pipetrace file: %s\n", (stm8->pipetrace_file ? stm8->pipetrace_file : ""));
+  con->dd_printf("  Pipetrace folding: %s\n", (stm8->pipetrace_fold ? "on" : "off"));
+
+  con->dd_printf("\n");
+  print_cfg_info(con);
+}
+
+
+void
 cl_stm8_cpu::write(class cl_memory_cell *cell, t_mem *val)
 {
   t_addr a;
@@ -2045,10 +2969,83 @@
 t_mem
 cl_stm8_cpu::conf_op(cl_memory_cell *cell, t_addr addr, t_mem *val)
 {
+  class cl_stm8 *u= (class cl_stm8 *)uc;
   if (val)
     cell->set(*val);
+  switch ((enum stm8_cpu_cfg)addr)
+    {
+    case cpuconf_sp_limit:
+      if (val)
+	u->sp_limit= *val & 0xffff;
+      else
+	cell->set(u->sp_limit);
+      break;
+    }
   return cell->get();
 }
 
+const char *
+cl_stm8_cpu::cfg_help(t_addr addr)
+{
+  switch (addr)
+    {
+    case cpuconf_sp_limit:
+      return "Stack overflows when SP is below this limit";
+    }
+  return "Not used";
+}
+
+/*
+ * Errors in STM8 execution
+ */
+
+/* All of memory errors */
+
+cl_error_stm8::cl_error_stm8(void)
+{
+  classification= stm8_error_registry.find("stm8");
+}
+
+cl_error_stm8_pipeline::
+cl_error_stm8_pipeline(void):
+  cl_error_stm8()
+{
+  classification= stm8_error_registry.find("pipeline");
+}
+
+cl_error_stm8_pipeline_decode_stall::
+cl_error_stm8_pipeline_decode_stall(void):
+  cl_error_stm8_pipeline()
+{
+  classification= stm8_error_registry.find("decode_stall");
+}
+
+void
+cl_error_stm8_pipeline_decode_stall::print(class cl_commander_base *c)
+{
+  c->dd_printf("%s: decode stalled\n", get_type_name());
+}
+
+cl_error_stm8_pipeline_fetch_stall::
+cl_error_stm8_pipeline_fetch_stall(void):
+  cl_error_stm8_pipeline()
+{
+  classification= stm8_error_registry.find("fetch_stall");
+}
+
+void
+cl_error_stm8_pipeline_fetch_stall::print(class cl_commander_base *c)
+{
+  c->dd_printf("%s: fetch stalled\n", get_type_name());
+}
+
+cl_stm8_error_registry::cl_stm8_error_registry(void)
+{
+  class cl_error_class *prev = stm8_error_registry.find("non-classified");
+  prev = register_error(new cl_error_class(err_error, "stm8", prev, ERROR_OFF));
+  prev = register_error(new cl_error_class(err_warning, "pipeline", prev));
+  register_error(new cl_error_class(err_warning, "decode_stall", prev));
+  register_error(new cl_error_class(err_warning, "fetch_stall", prev));
+}
 
 /* End of stm8.src/stm8.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/stm8cl.h sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/stm8cl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/stm8cl.h	2019-04-02 10:46:33.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/stm8cl.h	2022-02-03 14:06:06.000000000 +0000
@@ -45,7 +45,9 @@
   class cl_address_space *ram;
   class cl_address_space *regs8;
   class cl_address_space *regs16;
+  class cl_address_space *ports;
   class cl_memory_chip
+    *ports_chip,
     *ram_chip, // max 6k
     *eeprom_chip, // max 2k
     *option_chip, // 128 bytes
@@ -55,16 +57,41 @@
     *flash_chip; // max 128k
   //class cl_memory *rom;
   struct t_regs regs;
+  class cl_clk *clk;
   class cl_itc *itc;
   class cl_it_src *trap_src;
   class cl_flash *flash_ctrl;
+  t_addr sp_limit;
+
+  char *pipetrace_title, *pipetrace_style, *pipetrace_file;
+  FILE *pipetrace_fd;
+  bool pipetrace_in_table, pipetrace_running, pipetrace_fold;
+  unsigned int pipetrace_ticks, pipetrace_max_ticks;
+private:
+  int div_cycle;
+  u32_t dividend, divisor, quotient;
+  int pipeline_index, pipeline_bytes;
+  struct
+    {
+      bool instr, program, data, regs, flush;
+    } pipeline_busy;
+  void pipeline_flush(bool need_exec);
+
+  void pipetrace_instr_start(t_addr addr);
+  void pipetrace_instr_end(void);
+  void pipetrace_tick(const char *aux);
+  void pipetrace_type(const char *event);
+public:
+  void pipetrace_end_table(void);
+
 public:
   cl_stm8(struct cpu_entry *IType, class cl_sim *asim);
   virtual int init(void);
-  virtual char *id_string(void);
+  virtual const char *id_string(void);
 
   //virtual t_addr get_mem_size(enum mem_class type);
-  virtual void mk_port(t_addr base, chars n);
+  virtual void mk_port(int portnr, chars n);
+  virtual void make_cpu_hw(void);
   virtual void mk_hw_elements(void);
   virtual void make_memories(void);
 
@@ -72,10 +99,17 @@
   virtual int inst_length(t_addr addr);
   virtual int inst_branch(t_addr addr);
   virtual int longest_inst(void);
-  virtual char *disass(t_addr addr, const char *sep);
+  virtual void analyze_start(void);
+  virtual void analyze(t_addr addr);
+  virtual char *disass(t_addr addr);
   virtual void print_regs(class cl_console_base *con);
 
+  virtual int clock_per_cycle(void);
+  virtual int tick_hw(int cycles_cpu);
+  virtual int tick(int cycles_cpu);
   virtual int exec_inst(void);
+  virtual t_mem fetch(void);
+  virtual bool fetch(t_mem *code);
 
   virtual const char *get_disasm_info(t_addr addr,
                                       int *ret_len,
@@ -92,10 +126,17 @@
   virtual int  accept_it(class it_level *il);
   virtual bool it_enabled(void);
 
+  virtual void stack_check_overflow(class cl_stack_op *op);
+
 #include "instcl.h"
 };
 
 
+enum stm8_cpu_cfg
+  {
+   cpuconf_sp_limit	= 0,
+  };
+
 class cl_stm8_cpu: public cl_hw
 {
  protected:
@@ -103,12 +144,51 @@
  public:
   cl_stm8_cpu(class cl_uc *auc);
   virtual int init(void);
-  virtual int cfg_size(void) { return 2; }
-  //virtual char *cfg_help(t_addr addr);
+  virtual unsigned int cfg_size(void) { return 2; }
+  virtual void set_cmd(class cl_cmdline *cmdline, class cl_console_base *con);
+  virtual void print_info(class cl_console_base *con);
 
   virtual void write(class cl_memory_cell *cell, t_mem *val);
   virtual t_mem read(class cl_memory_cell *cell);
   virtual t_mem conf_op(cl_memory_cell *cell, t_addr addr, t_mem *val);
+  virtual const char *cfg_help(t_addr addr);
+};
+
+
+#include "errorcl.h"
+
+class cl_error_stm8: public cl_error
+{
+public:
+  cl_error_stm8(void);
+};
+
+class cl_error_stm8_pipeline: public cl_error_stm8
+{
+public:
+  cl_error_stm8_pipeline(void);
+};
+
+class cl_error_stm8_pipeline_decode_stall: public cl_error_stm8_pipeline
+{
+public:
+  cl_error_stm8_pipeline_decode_stall(void);
+
+  virtual void print(class cl_commander_base *c);
+};
+
+class cl_error_stm8_pipeline_fetch_stall: public cl_error_stm8_pipeline
+{
+public:
+  cl_error_stm8_pipeline_fetch_stall(void);
+
+  virtual void print(class cl_commander_base *c);
+};
+
+class cl_stm8_error_registry: public cl_error_registry
+{
+public:
+  cl_stm8_error_registry(void);
 };
 
 
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/stm8mac.h sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/stm8mac.h
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/stm8mac.h	2018-12-18 09:27:50.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/stm8mac.h	2022-01-18 09:48:32.000000000 +0000
@@ -18,16 +18,28 @@
 #define BITPOS_I1 5  // 20H
 #define BITPOS_V 7  // 80H
 
-#define store2(addr, val) { ram->write((t_addr) (addr), (val >> 8) & 0xff); \
-                            ram->write((t_addr) (addr+1), val & 0xff); \
-  			    vc.wr+= 2; }
-#define store1(addr, val) { ram->write((t_addr) (addr), val); vc.wr++; }
 //#define get1(addr) ram->read((t_addr) (addr))
 #define get1(addr) get_1(addr)
 #define fetch2() ((fetch() << 8) | fetch() )
 #define fetch1() fetch()
-#define push2(val) {store2(regs.SP-1,(val)); regs.SP-=2; }
-#define push1(val) {store1(regs.SP,(val)); regs.SP-=1; }
+#define push2(val) {							\
+    t_addr sp_before= regs.SP;						\
+    store2(regs.SP-1,(val));						\
+    regs.SP-=2;								\
+    class cl_stack_op *so=						\
+      new cl_stack_push(instPC,val,sp_before,regs.SP);			\
+    so->init();								\
+    stack_write(so);							\
+  }
+#define push1(val) {							\
+    t_addr sp_before= regs.SP;						\
+    store1(regs.SP,(val));						\
+    regs.SP-=1;								\
+    class cl_stack_op *so=						\
+      new cl_stack_push(instPC,val,sp_before,regs.SP);			\
+    so->init();								\
+    stack_write(so);							\
+  }
 #define pop2(var) {var=get2(regs.SP+1); regs.SP+=2;}
 #define pop1(var) {var=get1(regs.SP+1); regs.SP+=1;}
 
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/bitaddr/baseline/stdout sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/bitaddr/baseline/stdout
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/bitaddr/baseline/stdout	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/bitaddr/baseline/stdout	2022-02-08 21:21:05.000000000 +0000
@@ -0,0 +1,193 @@
+uCsim, Copyright (C)  Daniel Drotos.
+uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+This is free software, and you are welcome to redistribute it
+under certain conditions; type `show c' for details.
+# Memory contents are random initially so set some recognizable content.
+set mem rom 0x1000 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80
+0x01000                       01 02 04 08 10 20 40 80 ..... @.
+
+# Dump using old format   
+dump rom 0x1000 0x1007
+0x01000                       01 02 04 08 10 20 40 80 ..... @.
+
+# Dump using new format [] 
+dump rom[0x1000] 0x1007
+0x01000                       01 02 04 08 10 20 40 80 ..... @.
+
+# We can use new format for both start and end
+dump rom[0x1000] rom[0x1007]
+0x01000                       01 02 04 08 10 20 40 80 ..... @.
+
+# But we can't cross address spaces!
+dump rom[0x1000] regs8[0x1007]
+dump [/format] memory_type [start [stop [bytes_per_line]]] | dump bit...
+                    Dump memory of specified type or bit(s)
+
+# Bits can be expressed individually
+dump rom[0x1003].1
+0x01003.1                               0b------0- 0x00 '.'   0
+
+# Or as sets
+dump rom[0x1003][3:1]
+0x01003[3:1]                            0b----100- 0x04 '.'   4
+
+# We can set bits individually
+set mem rom[0x1000].7 1
+0x01000.7                               0b1------- 0x01 '.'   1
+
+# Or in groups
+set mem rom[0x1001][6:5] 0b11
+0x01001[6:5]                            0b-11----- 0x03 '.'   3
+
+# Vars can be set...
+set mem rom 0x1100 0xff
+0x01100                       ff .
+var test rom[0x1100]
+info var test
+test rom[0x01100] = 0xff,255U,255
+
+# ...and changed...
+var test rom[0x1100][3:0]
+info var test
+test rom[0x01100][3:0] = 0b1111,15U,15
+var test rom[0x1100][5:4]
+info var test
+test rom[0x01100][5:4] = 0b11,48U,48,'0'
+var test rom[0x1100][7:6]
+info var test
+test rom[0x01100][7:6] = 0b11,192U,192
+var test rom[0x1100][6:2]
+info var test
+test rom[0x01100][6:2] = 0b11111,124U,124,'|'
+
+# ...and deleted
+rmvar test
+info var test
+
+# Add some labels
+var test0 rom[0x1000]
+var test2 rom[0x1002]
+var test3a rom[0x1003]
+var test3b rom[0x1003]
+
+# And name some bits
+var set0  rom[0x1003][0:1]
+var set1  rom[0x1003].1
+var set2  rom[0x1003].2
+var set3  rom[0x1003].3
+var set4  rom[0x1003].4
+var set5  rom[0x1003].5
+var set6  rom[0x1003].6
+var set7  rom[0x1003].7
+
+var test4bit0  rom[0x1004].0
+var test4bit2  rom[0x1004].2
+var test4bit4  rom[0x1004].4
+var test4bit6  rom[0x1004].6
+
+# And name an odd bit in a location between two locations
+# that have neither labels nor named bits
+var lone1 rom[0x1006].6
+
+# Now when we dump the region the labels for addresses are shown,
+# breaking up the lines of hex data. Where there are names for
+# bits we automatically switch to displaying the data in binary.
+dump rom[0x1000] 0x100f
+0x01000 test0:                81 62                   .b
+0x01002 test2:                04                      .
+0x01003 test3a:              
+        test3b:               0b00001000 0x08 '.'   8
+        set7:                 0b0------- 0x00 '.'   0
+        set6:                 0b-0------ 0x00 '.'   0
+        set5:                 0b--0----- 0x00 '.'   0
+        set4:                 0b---0---- 0x00 '.'   0
+        set3:                 0b----1--- 0x01 '.'   1
+        set2:                 0b-----0-- 0x00 '.'   0
+        set0:                 0b------00 0x00 '.'   0
+        set1:                 0b------0- 0x00 '.'   0
+0x01004                       0b00010000 0x10 '.'  16
+        test4bit6:            0b-0------ 0x00 '.'   0
+        test4bit4:            0b---1---- 0x01 '.'   1
+        test4bit2:            0b-----0-- 0x00 '.'   0
+        test4bit0:            0b-------0 0x00 '.'   0
+0x01005                       20                       
+0x01006                       0b01000000 0x40 '@'  64
+        lone1:                0b-1------ 0x01 '.'   1
+0x01007                       80 6a 30 dd 9a b0 19 b7 .j0.....
+0x0100f                       0f                      .
+
+# Dumping some specific bits from a location works
+dump rom[0x1003][6:2]
+0x01003[6:2] test3a[6:2]:              
+             test3b[6:2]:              
+                                        0b-00010-- 0x02 '.'   2
+             set6:                      0b-0------ 0x00 '.'   0
+             set5:                      0b--0----- 0x00 '.'   0
+             set4:                      0b---0---- 0x00 '.'   0
+             set3:                      0b----1--- 0x01 '.'   1
+             set2:                      0b-----0-- 0x00 '.'   0
+
+# Specifying a format disables all the smarts
+dump /h rom[0x1000] 0x100f
+0x01000 81 62 04 08 10 20 40 80 .b... @.
+0x01008 6a 30 dd 9a b0 19 b7 0f j0......
+
+# Dumping a region with every other bit labeled...
+dump 0x1004
+0x01004                       0b00010000 0x10 '.'  16
+        test4bit6:            0b-0------ 0x00 '.'   0
+        test4bit4:            0b---1---- 0x01 '.'   1
+        test4bit2:            0b-----0-- 0x00 '.'   0
+        test4bit0:            0b-------0 0x00 '.'   0
+0x01005                       20                       
+0x01006                       0b01000000 0x40 '@'  64
+        lone1:                0b-1------ 0x01 '.'   1
+0x01007                       80 6a 30 dd 9a b0 19 b7 .j0.....
+0x0100f                       0f 36 cf f5 b9 1e d5 d1 .6......
+
+# And with partial views...
+dump 0x1004[6:4]
+0x01004[6:4]                            0b-001---- 0x01 '.'   1
+             test4bit6:                 0b-0------ 0x00 '.'   0
+             test4bit4:                 0b---1---- 0x01 '.'   1
+dump 0x1004[5:3]
+0x01004[5:3]                            0b--010--- 0x02 '.'   2
+             test4bit4:                 0b---1---- 0x01 '.'   1
+dump 0x1004[7:2]
+0x01004[7:2]                            0b000100-- 0x04 '.'   4
+             test4bit6:                 0b-0------ 0x00 '.'   0
+             test4bit4:                 0b---1---- 0x01 '.'   1
+             test4bit2:                 0b-----0-- 0x00 '.'   0
+
+# If the first label was qualified due to a request for a bit
+# range subsequent labels may be considered identical even if
+# they aren't strictly identical.
+var some_bits test0[5:3]
+d some_bits
+0x01000[5:3] test0[5:3]:               
+             some_bits:                 0b--000--- 0x00 '.'   0
+var more_bits test0[6:2]
+d some_bits
+0x01000[5:3] test0[5:3]:               
+             some_bits:                 0b--000--- 0x00 '.'   0
+var less_bits test0.4
+d some_bits
+0x01000[5:3] test0[5:3]:               
+             some_bits:                 0b--000--- 0x00 '.'   0
+             less_bits:                 0b---0---- 0x00 '.'   0
+d less_bits
+0x01000.4    test0.4:                  
+             less_bits:                 0b---0---- 0x00 '.'   0
+d more_bits
+0x01000[6:2] test0[6:2]:               
+             more_bits:                 0b-00000-- 0x00 '.'   0
+             some_bits:                 0b--000--- 0x00 '.'   0
+             less_bits:                 0b---0---- 0x00 '.'   0
+
+# Finally the expression evaluater handles bits in the same way
+rom[0x1000]
+129
+rom[0x1000].7
+1
+rom[0x1001][6:5]
+3
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/bitaddr/Makefile sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/bitaddr/Makefile
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/bitaddr/Makefile	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/bitaddr/Makefile	2021-04-01 17:52:48.000000000 +0000
@@ -0,0 +1,15 @@
+OUTPUTS = stdout
+
+
+# Ignore changes in white space. The field widths for labels
+# depends on the length of the longest label. This will be
+# different for different simulators and should not be assumed
+# to be constant for any given simulator.
+DIFF_OPTS += -b
+
+
+stdout: test.cmd
+	@$(call run-sim)
+
+
+include test-lib.mk
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/bitaddr/test.cmd sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/bitaddr/test.cmd
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/bitaddr/test.cmd	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/bitaddr/test.cmd	2022-01-26 16:35:40.000000000 +0000
@@ -0,0 +1,106 @@
+# Memory contents are random initially so set some recognizable content.
+set mem rom 0x1000 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80
+
+# Dump using old format   
+dump rom 0x1000 0x1007
+
+# Dump using new format [] 
+dump rom[0x1000] 0x1007
+
+# We can use new format for both start and end
+dump rom[0x1000] rom[0x1007]
+
+# But we can't cross address spaces!
+dump rom[0x1000] regs8[0x1007]
+
+# Bits can be expressed individually
+dump rom[0x1003].1
+
+# Or as sets
+dump rom[0x1003][3:1]
+
+# We can set bits individually
+set mem rom[0x1000].7 1
+
+# Or in groups
+set mem rom[0x1001][6:5] 0b11
+
+# Vars can be set...
+set mem rom 0x1100 0xff
+var test rom[0x1100]
+info var test
+
+# ...and changed...
+var test rom[0x1100][3:0]
+info var test
+var test rom[0x1100][5:4]
+info var test
+var test rom[0x1100][7:6]
+info var test
+var test rom[0x1100][6:2]
+info var test
+
+# ...and deleted
+rmvar test
+info var test
+
+# Add some labels
+var test0 rom[0x1000]
+var test2 rom[0x1002]
+var test3a rom[0x1003]
+var test3b rom[0x1003]
+
+# And name some bits
+var set0  rom[0x1003][0:1]
+var set1  rom[0x1003].1
+var set2  rom[0x1003].2
+var set3  rom[0x1003].3
+var set4  rom[0x1003].4
+var set5  rom[0x1003].5
+var set6  rom[0x1003].6
+var set7  rom[0x1003].7
+
+var test4bit0  rom[0x1004].0
+var test4bit2  rom[0x1004].2
+var test4bit4  rom[0x1004].4
+var test4bit6  rom[0x1004].6
+
+# And name an odd bit in a location between two locations
+# that have neither labels nor named bits
+var lone1 rom[0x1006].6
+
+# Now when we dump the region the labels for addresses are shown,
+# breaking up the lines of hex data. Where there are names for
+# bits we automatically switch to displaying the data in binary.
+dump rom[0x1000] 0x100f
+
+# Dumping some specific bits from a location works
+dump rom[0x1003][6:2]
+
+# Specifying a format disables all the smarts
+dump /h rom[0x1000] 0x100f
+
+# Dumping a region with every other bit labeled...
+dump 0x1004
+
+# And with partial views...
+dump 0x1004[6:4]
+dump 0x1004[5:3]
+dump 0x1004[7:2]
+
+# If the first label was qualified due to a request for a bit
+# range subsequent labels may be considered identical even if
+# they aren't strictly identical.
+var some_bits test0[5:3]
+d some_bits
+var more_bits test0[6:2]
+d some_bits
+var less_bits test0.4
+d some_bits
+d less_bits
+d more_bits
+
+# Finally the expression evaluater handles bits in the same way
+rom[0x1000]
+rom[0x1000].7
+rom[0x1001][6:5]
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/clean.mk sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/clean.mk
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/clean.mk	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/clean.mk	2021-04-26 19:46:10.000000000 +0000
@@ -0,0 +1,7 @@
+clean:
+
+distclean:
+	rm -f Makefile
+	find . -type d -name out -exec rm -rf {} \;
+	rm -rf vcd-in/*.ihx vcd-in/*.lst vcd-in/*.sym
+	rm -rf vcd-out/*.ihx vcd-out/*.lst vcd-out/*.sym
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/clk/baseline/stdout sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/clk/baseline/stdout
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/clk/baseline/stdout	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/clk/baseline/stdout	2022-02-08 21:21:05.000000000 +0000
@@ -0,0 +1,712 @@
+uCsim, Copyright (C)  Daniel Drotos.
+uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+This is free software, and you are welcome to redistribute it
+under certain conditions; type `show c' for details.
+step
+
+Stop at 0x008004: (109) stepped 3 ticks
+V-IHINZC  Flags= 0x28  40 (  A= 0x00   0 .
+0-101000  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17ff [SP+1]= 00   0 .  Limit= 0x1500
+
+0x08004    <.reset>:
+0x08004    35 00 50 c6    mov    0x50c6 ,#0x00[0K
+F 0x008004
+timer get
+timer #1("time") ON 0.000001500000000 sec (3 clks)
+timer #2("isr") ON,ISR 0.000000000000000 sec (0 clks)
+timer #3("idle") ON,IDLE 0.000000000000000 sec (0 clks)
+timer #4("halt") ON,HALT 0.000000000000000 sec (0 clks)
+dump CLK_CKDIVR[7:0]
+0x050c6      CLK_CKDIVR[7:0]:           0b00011000 0x18 '.'  24
+             CLK_CKDIVR_HSIDIV:         0b---11--- 0x03 '.'   3
+             CLK_CKDIVR_CPUDIV:         0b-----000 0x00 '.'   0
+info hw clk
+clk[0] at 0x0050c0
+  HSI
+  f_OSC:    16000000 Hz
+  HSIDIV:   8
+  f_MASTER: 2000000 Hz
+  CPUDIV:   1
+  f_CPU:    2000000 Hz
+  PCKENR1:  0xff
+  PCKENR2:  0xff
+step
+
+Stop at 0x008008: (109) stepped 2 ticks
+V-IHINZC  Flags= 0x28  40 (  A= 0x00   0 .
+0-101000  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17ff [SP+1]= 00   0 .  Limit= 0x1500
+0x08008    35 08 50 c6    mov    0x50c6 ,#0x08[0K
+F 0x008008
+timer get
+timer #1("time") ON 0.000002500000000 sec (5 clks)
+timer #2("isr") ON,ISR 0.000000000000000 sec (0 clks)
+timer #3("idle") ON,IDLE 0.000000000000000 sec (0 clks)
+timer #4("halt") ON,HALT 0.000000000000000 sec (0 clks)
+dump CLK_CKDIVR[7:0]
+0x050c6      CLK_CKDIVR[7:0]:           0b00000000 0x00 '.'   0
+             CLK_CKDIVR_HSIDIV:         0b---00--- 0x00 '.'   0
+             CLK_CKDIVR_CPUDIV:         0b-----000 0x00 '.'   0
+info hw clk
+clk[0] at 0x0050c0
+  HSI
+  f_OSC:    16000000 Hz
+  HSIDIV:   1
+  f_MASTER: 16000000 Hz
+  CPUDIV:   1
+  f_CPU:    16000000 Hz
+  PCKENR1:  0xff
+  PCKENR2:  0xff
+step
+
+Stop at 0x00800c: (109) stepped 1 ticks
+V-IHINZC  Flags= 0x28  40 (  A= 0x00   0 .
+0-101000  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17ff [SP+1]= 00   0 .  Limit= 0x1500
+0x0800c    35 10 50 c6    mov    0x50c6 ,#0x10[0K
+F 0x00800c
+timer get
+timer #1("time") ON 0.000002562500000 sec (6 clks)
+timer #2("isr") ON,ISR 0.000000000000000 sec (0 clks)
+timer #3("idle") ON,IDLE 0.000000000000000 sec (0 clks)
+timer #4("halt") ON,HALT 0.000000000000000 sec (0 clks)
+dump CLK_CKDIVR[7:0]
+0x050c6      CLK_CKDIVR[7:0]:           0b00001000 0x08 '.'   8
+             CLK_CKDIVR_HSIDIV:         0b---01--- 0x01 '.'   1
+             CLK_CKDIVR_CPUDIV:         0b-----000 0x00 '.'   0
+info hw clk
+clk[0] at 0x0050c0
+  HSI
+  f_OSC:    16000000 Hz
+  HSIDIV:   2
+  f_MASTER: 8000000 Hz
+  CPUDIV:   1
+  f_CPU:    8000000 Hz
+  PCKENR1:  0xff
+  PCKENR2:  0xff
+step
+
+Stop at 0x008010: (109) stepped 1 ticks
+V-IHINZC  Flags= 0x28  40 (  A= 0x00   0 .
+0-101000  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17ff [SP+1]= 00   0 .  Limit= 0x1500
+0x08010    35 18 50 c6    mov    0x50c6 ,#0x18[0K
+F 0x008010
+timer get
+timer #1("time") ON 0.000002687500000 sec (7 clks)
+timer #2("isr") ON,ISR 0.000000000000000 sec (0 clks)
+timer #3("idle") ON,IDLE 0.000000000000000 sec (0 clks)
+timer #4("halt") ON,HALT 0.000000000000000 sec (0 clks)
+dump CLK_CKDIVR[7:0]
+0x050c6      CLK_CKDIVR[7:0]:           0b00010000 0x10 '.'  16
+             CLK_CKDIVR_HSIDIV:         0b---10--- 0x02 '.'   2
+             CLK_CKDIVR_CPUDIV:         0b-----000 0x00 '.'   0
+info hw clk
+clk[0] at 0x0050c0
+  HSI
+  f_OSC:    16000000 Hz
+  HSIDIV:   4
+  f_MASTER: 4000000 Hz
+  CPUDIV:   1
+  f_CPU:    4000000 Hz
+  PCKENR1:  0xff
+  PCKENR2:  0xff
+step
+
+Stop at 0x008014: (109) stepped 1 ticks
+V-IHINZC  Flags= 0x28  40 (  A= 0x00   0 .
+0-101000  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17ff [SP+1]= 00   0 .  Limit= 0x1500
+0x08014    35 00 50 c6    mov    0x50c6 ,#0x00[0K
+F 0x008014
+timer get
+timer #1("time") ON 0.000002937500000 sec (8 clks)
+timer #2("isr") ON,ISR 0.000000000000000 sec (0 clks)
+timer #3("idle") ON,IDLE 0.000000000000000 sec (0 clks)
+timer #4("halt") ON,HALT 0.000000000000000 sec (0 clks)
+dump CLK_CKDIVR[7:0]
+0x050c6      CLK_CKDIVR[7:0]:           0b00011000 0x18 '.'  24
+             CLK_CKDIVR_HSIDIV:         0b---11--- 0x03 '.'   3
+             CLK_CKDIVR_CPUDIV:         0b-----000 0x00 '.'   0
+info hw clk
+clk[0] at 0x0050c0
+  HSI
+  f_OSC:    16000000 Hz
+  HSIDIV:   8
+  f_MASTER: 2000000 Hz
+  CPUDIV:   1
+  f_CPU:    2000000 Hz
+  PCKENR1:  0xff
+  PCKENR2:  0xff
+step
+
+Stop at 0x008018: (109) stepped 1 ticks
+V-IHINZC  Flags= 0x28  40 (  A= 0x00   0 .
+0-101000  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17ff [SP+1]= 00   0 .  Limit= 0x1500
+0x08018    35 01 50 c6    mov    0x50c6 ,#0x01[0K
+F 0x008018
+timer get
+timer #1("time") ON 0.000003437500000 sec (9 clks)
+timer #2("isr") ON,ISR 0.000000000000000 sec (0 clks)
+timer #3("idle") ON,IDLE 0.000000000000000 sec (0 clks)
+timer #4("halt") ON,HALT 0.000000000000000 sec (0 clks)
+dump CLK_CKDIVR[7:0]
+0x050c6      CLK_CKDIVR[7:0]:           0b00000000 0x00 '.'   0
+             CLK_CKDIVR_HSIDIV:         0b---00--- 0x00 '.'   0
+             CLK_CKDIVR_CPUDIV:         0b-----000 0x00 '.'   0
+info hw clk
+clk[0] at 0x0050c0
+  HSI
+  f_OSC:    16000000 Hz
+  HSIDIV:   1
+  f_MASTER: 16000000 Hz
+  CPUDIV:   1
+  f_CPU:    16000000 Hz
+  PCKENR1:  0xff
+  PCKENR2:  0xff
+step
+
+Stop at 0x00801c: (109) stepped 1 ticks
+V-IHINZC  Flags= 0x28  40 (  A= 0x00   0 .
+0-101000  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17ff [SP+1]= 00   0 .  Limit= 0x1500
+0x0801c    35 02 50 c6    mov    0x50c6 ,#0x02[0K
+F 0x00801c
+timer get
+timer #1("time") ON 0.000003500000000 sec (10 clks)
+timer #2("isr") ON,ISR 0.000000000000000 sec (0 clks)
+timer #3("idle") ON,IDLE 0.000000000000000 sec (0 clks)
+timer #4("halt") ON,HALT 0.000000000000000 sec (0 clks)
+dump CLK_CKDIVR[7:0]
+0x050c6      CLK_CKDIVR[7:0]:           0b00000001 0x01 '.'   1
+             CLK_CKDIVR_HSIDIV:         0b---00--- 0x00 '.'   0
+             CLK_CKDIVR_CPUDIV:         0b-----001 0x01 '.'   1
+info hw clk
+clk[0] at 0x0050c0
+  HSI
+  f_OSC:    16000000 Hz
+  HSIDIV:   1
+  f_MASTER: 16000000 Hz
+  CPUDIV:   2
+  f_CPU:    8000000 Hz
+  PCKENR1:  0xff
+  PCKENR2:  0xff
+step
+
+Stop at 0x008020: (109) stepped 2 ticks
+V-IHINZC  Flags= 0x28  40 (  A= 0x00   0 .
+0-101000  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17ff [SP+1]= 00   0 .  Limit= 0x1500
+0x08020    35 03 50 c6    mov    0x50c6 ,#0x03[0K
+F 0x008020
+timer get
+timer #1("time") ON 0.000003625000000 sec (12 clks)
+timer #2("isr") ON,ISR 0.000000000000000 sec (0 clks)
+timer #3("idle") ON,IDLE 0.000000000000000 sec (0 clks)
+timer #4("halt") ON,HALT 0.000000000000000 sec (0 clks)
+dump CLK_CKDIVR[7:0]
+0x050c6      CLK_CKDIVR[7:0]:           0b00000010 0x02 '.'   2
+             CLK_CKDIVR_HSIDIV:         0b---00--- 0x00 '.'   0
+             CLK_CKDIVR_CPUDIV:         0b-----010 0x02 '.'   2
+info hw clk
+clk[0] at 0x0050c0
+  HSI
+  f_OSC:    16000000 Hz
+  HSIDIV:   1
+  f_MASTER: 16000000 Hz
+  CPUDIV:   4
+  f_CPU:    4000000 Hz
+  PCKENR1:  0xff
+  PCKENR2:  0xff
+step
+
+Stop at 0x008024: (109) stepped 4 ticks
+V-IHINZC  Flags= 0x28  40 (  A= 0x00   0 .
+0-101000  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17ff [SP+1]= 00   0 .  Limit= 0x1500
+0x08024    35 04 50 c6    mov    0x50c6 ,#0x04[0K
+F 0x008024
+timer get
+timer #1("time") ON 0.000003875000000 sec (16 clks)
+timer #2("isr") ON,ISR 0.000000000000000 sec (0 clks)
+timer #3("idle") ON,IDLE 0.000000000000000 sec (0 clks)
+timer #4("halt") ON,HALT 0.000000000000000 sec (0 clks)
+dump CLK_CKDIVR[7:0]
+0x050c6      CLK_CKDIVR[7:0]:           0b00000011 0x03 '.'   3
+             CLK_CKDIVR_HSIDIV:         0b---00--- 0x00 '.'   0
+             CLK_CKDIVR_CPUDIV:         0b-----011 0x03 '.'   3
+info hw clk
+clk[0] at 0x0050c0
+  HSI
+  f_OSC:    16000000 Hz
+  HSIDIV:   1
+  f_MASTER: 16000000 Hz
+  CPUDIV:   8
+  f_CPU:    2000000 Hz
+  PCKENR1:  0xff
+  PCKENR2:  0xff
+step
+
+Stop at 0x008028: (109) stepped 8 ticks
+V-IHINZC  Flags= 0x28  40 (  A= 0x00   0 .
+0-101000  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17ff [SP+1]= 00   0 .  Limit= 0x1500
+0x08028    35 05 50 c6    mov    0x50c6 ,#0x05[0K
+F 0x008028
+timer get
+timer #1("time") ON 0.000004375000000 sec (24 clks)
+timer #2("isr") ON,ISR 0.000000000000000 sec (0 clks)
+timer #3("idle") ON,IDLE 0.000000000000000 sec (0 clks)
+timer #4("halt") ON,HALT 0.000000000000000 sec (0 clks)
+dump CLK_CKDIVR[7:0]
+0x050c6      CLK_CKDIVR[7:0]:           0b00000100 0x04 '.'   4
+             CLK_CKDIVR_HSIDIV:         0b---00--- 0x00 '.'   0
+             CLK_CKDIVR_CPUDIV:         0b-----100 0x04 '.'   4
+info hw clk
+clk[0] at 0x0050c0
+  HSI
+  f_OSC:    16000000 Hz
+  HSIDIV:   1
+  f_MASTER: 16000000 Hz
+  CPUDIV:   16
+  f_CPU:    1000000 Hz
+  PCKENR1:  0xff
+  PCKENR2:  0xff
+step
+
+Stop at 0x00802c: (109) stepped 16 ticks
+V-IHINZC  Flags= 0x28  40 (  A= 0x00   0 .
+0-101000  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17ff [SP+1]= 00   0 .  Limit= 0x1500
+0x0802c    35 06 50 c6    mov    0x50c6 ,#0x06[0K
+F 0x00802c
+timer get
+timer #1("time") ON 0.000005375000000 sec (40 clks)
+timer #2("isr") ON,ISR 0.000000000000000 sec (0 clks)
+timer #3("idle") ON,IDLE 0.000000000000000 sec (0 clks)
+timer #4("halt") ON,HALT 0.000000000000000 sec (0 clks)
+dump CLK_CKDIVR[7:0]
+0x050c6      CLK_CKDIVR[7:0]:           0b00000101 0x05 '.'   5
+             CLK_CKDIVR_HSIDIV:         0b---00--- 0x00 '.'   0
+             CLK_CKDIVR_CPUDIV:         0b-----101 0x05 '.'   5
+info hw clk
+clk[0] at 0x0050c0
+  HSI
+  f_OSC:    16000000 Hz
+  HSIDIV:   1
+  f_MASTER: 16000000 Hz
+  CPUDIV:   32
+  f_CPU:    500000 Hz
+  PCKENR1:  0xff
+  PCKENR2:  0xff
+step
+
+Stop at 0x008030: (109) stepped 32 ticks
+V-IHINZC  Flags= 0x28  40 (  A= 0x00   0 .
+0-101000  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17ff [SP+1]= 00   0 .  Limit= 0x1500
+0x08030    35 07 50 c6    mov    0x50c6 ,#0x07[0K
+F 0x008030
+timer get
+timer #1("time") ON 0.000007375000000 sec (72 clks)
+timer #2("isr") ON,ISR 0.000000000000000 sec (0 clks)
+timer #3("idle") ON,IDLE 0.000000000000000 sec (0 clks)
+timer #4("halt") ON,HALT 0.000000000000000 sec (0 clks)
+dump CLK_CKDIVR[7:0]
+0x050c6      CLK_CKDIVR[7:0]:           0b00000110 0x06 '.'   6
+             CLK_CKDIVR_HSIDIV:         0b---00--- 0x00 '.'   0
+             CLK_CKDIVR_CPUDIV:         0b-----110 0x06 '.'   6
+info hw clk
+clk[0] at 0x0050c0
+  HSI
+  f_OSC:    16000000 Hz
+  HSIDIV:   1
+  f_MASTER: 16000000 Hz
+  CPUDIV:   64
+  f_CPU:    250000 Hz
+  PCKENR1:  0xff
+  PCKENR2:  0xff
+step
+
+Stop at 0x008034: (109) stepped 64 ticks
+V-IHINZC  Flags= 0x28  40 (  A= 0x00   0 .
+0-101000  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17ff [SP+1]= 00   0 .  Limit= 0x1500
+0x08034    72 16 48 05    bset   0x4805,#3[0K
+F 0x008034
+timer get
+timer #1("time") ON 0.000011375000000 sec (136 clks)
+timer #2("isr") ON,ISR 0.000000000000000 sec (0 clks)
+timer #3("idle") ON,IDLE 0.000000000000000 sec (0 clks)
+timer #4("halt") ON,HALT 0.000000000000000 sec (0 clks)
+dump CLK_CKDIVR[7:0]
+0x050c6      CLK_CKDIVR[7:0]:           0b00000111 0x07 '.'   7
+             CLK_CKDIVR_HSIDIV:         0b---00--- 0x00 '.'   0
+             CLK_CKDIVR_CPUDIV:         0b-----111 0x07 '.'   7
+info hw clk
+clk[0] at 0x0050c0
+  HSI
+  f_OSC:    16000000 Hz
+  HSIDIV:   1
+  f_MASTER: 16000000 Hz
+  CPUDIV:   128
+  f_CPU:    125000 Hz
+  PCKENR1:  0xff
+  PCKENR2:  0xff
+
+step 5
+
+Stop at 0x008049: (109) stepped 1152 ticks
+V-IHINZC  Flags= 0x28  40 (  A= 0x00   0 .
+0-101000  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17ff [SP+1]= 00   0 .  Limit= 0x1500
+0x08049    35 00 50 c6    mov    0x50c6 ,#0x00[0K
+F 0x008049
+Simulated 1152 ticks [ELIDED]
+Host usage: [ELIDED]
+
+timer get
+timer #1("time") ON 0.002067375000000 sec (1288 clks)
+timer #2("isr") ON,ISR 0.000000000000000 sec (0 clks)
+timer #3("idle") ON,IDLE 0.000000000000000 sec (0 clks)
+timer #4("halt") ON,HALT 0.000000000000000 sec (0 clks)
+dump CLK_CKDIVR[7:0]
+0x050c6      CLK_CKDIVR[7:0]:           0b00000111 0x07 '.'   7
+             CLK_CKDIVR_HSIDIV:         0b---00--- 0x00 '.'   0
+             CLK_CKDIVR_CPUDIV:         0b-----111 0x07 '.'   7
+info hw clk
+clk[0] at 0x0050c0
+  LSI
+  f_OSC:    128000 Hz
+  HSIDIV:   1
+  f_MASTER: 128000 Hz
+  CPUDIV:   128
+  f_CPU:    1000 Hz
+  PCKENR1:  0xff
+  PCKENR2:  0xff
+step
+
+Stop at 0x00804d: (109) stepped 128 ticks
+V-IHINZC  Flags= 0x28  40 (  A= 0x00   0 .
+0-101000  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17ff [SP+1]= 00   0 .  Limit= 0x1500
+0x0804d    35 08 50 c6    mov    0x50c6 ,#0x08[0K
+F 0x00804d
+timer get
+timer #1("time") ON 0.003067375000000 sec (1416 clks)
+timer #2("isr") ON,ISR 0.000000000000000 sec (0 clks)
+timer #3("idle") ON,IDLE 0.000000000000000 sec (0 clks)
+timer #4("halt") ON,HALT 0.000000000000000 sec (0 clks)
+dump CLK_CKDIVR[7:0]
+0x050c6      CLK_CKDIVR[7:0]:           0b00000000 0x00 '.'   0
+             CLK_CKDIVR_HSIDIV:         0b---00--- 0x00 '.'   0
+             CLK_CKDIVR_CPUDIV:         0b-----000 0x00 '.'   0
+info hw clk
+clk[0] at 0x0050c0
+  LSI
+  f_OSC:    128000 Hz
+  HSIDIV:   1
+  f_MASTER: 128000 Hz
+  CPUDIV:   1
+  f_CPU:    128000 Hz
+  PCKENR1:  0xff
+  PCKENR2:  0xff
+step
+
+Stop at 0x008051: (109) stepped 1 ticks
+V-IHINZC  Flags= 0x28  40 (  A= 0x00   0 .
+0-101000  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17ff [SP+1]= 00   0 .  Limit= 0x1500
+0x08051    35 10 50 c6    mov    0x50c6 ,#0x10[0K
+F 0x008051
+timer get
+timer #1("time") ON 0.003075187500000 sec (1417 clks)
+timer #2("isr") ON,ISR 0.000000000000000 sec (0 clks)
+timer #3("idle") ON,IDLE 0.000000000000000 sec (0 clks)
+timer #4("halt") ON,HALT 0.000000000000000 sec (0 clks)
+dump CLK_CKDIVR[7:0]
+0x050c6      CLK_CKDIVR[7:0]:           0b00001000 0x08 '.'   8
+             CLK_CKDIVR_HSIDIV:         0b---01--- 0x01 '.'   1
+             CLK_CKDIVR_CPUDIV:         0b-----000 0x00 '.'   0
+info hw clk
+clk[0] at 0x0050c0
+  LSI
+  f_OSC:    128000 Hz
+  HSIDIV:   1
+  f_MASTER: 128000 Hz
+  CPUDIV:   1
+  f_CPU:    128000 Hz
+  PCKENR1:  0xff
+  PCKENR2:  0xff
+step
+
+Stop at 0x008055: (109) stepped 1 ticks
+V-IHINZC  Flags= 0x28  40 (  A= 0x00   0 .
+0-101000  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17ff [SP+1]= 00   0 .  Limit= 0x1500
+0x08055    35 18 50 c6    mov    0x50c6 ,#0x18[0K
+F 0x008055
+timer get
+timer #1("time") ON 0.003083000000000 sec (1418 clks)
+timer #2("isr") ON,ISR 0.000000000000000 sec (0 clks)
+timer #3("idle") ON,IDLE 0.000000000000000 sec (0 clks)
+timer #4("halt") ON,HALT 0.000000000000000 sec (0 clks)
+dump CLK_CKDIVR[7:0]
+0x050c6      CLK_CKDIVR[7:0]:           0b00010000 0x10 '.'  16
+             CLK_CKDIVR_HSIDIV:         0b---10--- 0x02 '.'   2
+             CLK_CKDIVR_CPUDIV:         0b-----000 0x00 '.'   0
+info hw clk
+clk[0] at 0x0050c0
+  LSI
+  f_OSC:    128000 Hz
+  HSIDIV:   1
+  f_MASTER: 128000 Hz
+  CPUDIV:   1
+  f_CPU:    128000 Hz
+  PCKENR1:  0xff
+  PCKENR2:  0xff
+step
+
+Stop at 0x008059: (109) stepped 1 ticks
+V-IHINZC  Flags= 0x28  40 (  A= 0x00   0 .
+0-101000  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17ff [SP+1]= 00   0 .  Limit= 0x1500
+0x08059    35 00 50 c6    mov    0x50c6 ,#0x00[0K
+F 0x008059
+timer get
+timer #1("time") ON 0.003090812500000 sec (1419 clks)
+timer #2("isr") ON,ISR 0.000000000000000 sec (0 clks)
+timer #3("idle") ON,IDLE 0.000000000000000 sec (0 clks)
+timer #4("halt") ON,HALT 0.000000000000000 sec (0 clks)
+dump CLK_CKDIVR[7:0]
+0x050c6      CLK_CKDIVR[7:0]:           0b00011000 0x18 '.'  24
+             CLK_CKDIVR_HSIDIV:         0b---11--- 0x03 '.'   3
+             CLK_CKDIVR_CPUDIV:         0b-----000 0x00 '.'   0
+info hw clk
+clk[0] at 0x0050c0
+  LSI
+  f_OSC:    128000 Hz
+  HSIDIV:   1
+  f_MASTER: 128000 Hz
+  CPUDIV:   1
+  f_CPU:    128000 Hz
+  PCKENR1:  0xff
+  PCKENR2:  0xff
+step
+
+Stop at 0x00805d: (109) stepped 1 ticks
+V-IHINZC  Flags= 0x28  40 (  A= 0x00   0 .
+0-101000  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17ff [SP+1]= 00   0 .  Limit= 0x1500
+0x0805d    35 01 50 c6    mov    0x50c6 ,#0x01[0K
+F 0x00805d
+timer get
+timer #1("time") ON 0.003098625000000 sec (1420 clks)
+timer #2("isr") ON,ISR 0.000000000000000 sec (0 clks)
+timer #3("idle") ON,IDLE 0.000000000000000 sec (0 clks)
+timer #4("halt") ON,HALT 0.000000000000000 sec (0 clks)
+dump CLK_CKDIVR[7:0]
+0x050c6      CLK_CKDIVR[7:0]:           0b00000000 0x00 '.'   0
+             CLK_CKDIVR_HSIDIV:         0b---00--- 0x00 '.'   0
+             CLK_CKDIVR_CPUDIV:         0b-----000 0x00 '.'   0
+info hw clk
+clk[0] at 0x0050c0
+  LSI
+  f_OSC:    128000 Hz
+  HSIDIV:   1
+  f_MASTER: 128000 Hz
+  CPUDIV:   1
+  f_CPU:    128000 Hz
+  PCKENR1:  0xff
+  PCKENR2:  0xff
+step
+
+Stop at 0x008061: (109) stepped 1 ticks
+V-IHINZC  Flags= 0x28  40 (  A= 0x00   0 .
+0-101000  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17ff [SP+1]= 00   0 .  Limit= 0x1500
+0x08061    35 02 50 c6    mov    0x50c6 ,#0x02[0K
+F 0x008061
+timer get
+timer #1("time") ON 0.003106437500000 sec (1421 clks)
+timer #2("isr") ON,ISR 0.000000000000000 sec (0 clks)
+timer #3("idle") ON,IDLE 0.000000000000000 sec (0 clks)
+timer #4("halt") ON,HALT 0.000000000000000 sec (0 clks)
+dump CLK_CKDIVR[7:0]
+0x050c6      CLK_CKDIVR[7:0]:           0b00000001 0x01 '.'   1
+             CLK_CKDIVR_HSIDIV:         0b---00--- 0x00 '.'   0
+             CLK_CKDIVR_CPUDIV:         0b-----001 0x01 '.'   1
+info hw clk
+clk[0] at 0x0050c0
+  LSI
+  f_OSC:    128000 Hz
+  HSIDIV:   1
+  f_MASTER: 128000 Hz
+  CPUDIV:   2
+  f_CPU:    64000 Hz
+  PCKENR1:  0xff
+  PCKENR2:  0xff
+step
+
+Stop at 0x008065: (109) stepped 2 ticks
+V-IHINZC  Flags= 0x28  40 (  A= 0x00   0 .
+0-101000  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17ff [SP+1]= 00   0 .  Limit= 0x1500
+0x08065    35 03 50 c6    mov    0x50c6 ,#0x03[0K
+F 0x008065
+timer get
+timer #1("time") ON 0.003122062500000 sec (1423 clks)
+timer #2("isr") ON,ISR 0.000000000000000 sec (0 clks)
+timer #3("idle") ON,IDLE 0.000000000000000 sec (0 clks)
+timer #4("halt") ON,HALT 0.000000000000000 sec (0 clks)
+dump CLK_CKDIVR[7:0]
+0x050c6      CLK_CKDIVR[7:0]:           0b00000010 0x02 '.'   2
+             CLK_CKDIVR_HSIDIV:         0b---00--- 0x00 '.'   0
+             CLK_CKDIVR_CPUDIV:         0b-----010 0x02 '.'   2
+info hw clk
+clk[0] at 0x0050c0
+  LSI
+  f_OSC:    128000 Hz
+  HSIDIV:   1
+  f_MASTER: 128000 Hz
+  CPUDIV:   4
+  f_CPU:    32000 Hz
+  PCKENR1:  0xff
+  PCKENR2:  0xff
+step
+
+Stop at 0x008069: (109) stepped 4 ticks
+V-IHINZC  Flags= 0x28  40 (  A= 0x00   0 .
+0-101000  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17ff [SP+1]= 00   0 .  Limit= 0x1500
+0x08069    35 04 50 c6    mov    0x50c6 ,#0x04[0K
+F 0x008069
+timer get
+timer #1("time") ON 0.003153312500000 sec (1427 clks)
+timer #2("isr") ON,ISR 0.000000000000000 sec (0 clks)
+timer #3("idle") ON,IDLE 0.000000000000000 sec (0 clks)
+timer #4("halt") ON,HALT 0.000000000000000 sec (0 clks)
+dump CLK_CKDIVR[7:0]
+0x050c6      CLK_CKDIVR[7:0]:           0b00000011 0x03 '.'   3
+             CLK_CKDIVR_HSIDIV:         0b---00--- 0x00 '.'   0
+             CLK_CKDIVR_CPUDIV:         0b-----011 0x03 '.'   3
+info hw clk
+clk[0] at 0x0050c0
+  LSI
+  f_OSC:    128000 Hz
+  HSIDIV:   1
+  f_MASTER: 128000 Hz
+  CPUDIV:   8
+  f_CPU:    16000 Hz
+  PCKENR1:  0xff
+  PCKENR2:  0xff
+step
+
+Stop at 0x00806d: (109) stepped 8 ticks
+V-IHINZC  Flags= 0x28  40 (  A= 0x00   0 .
+0-101000  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17ff [SP+1]= 00   0 .  Limit= 0x1500
+0x0806d    35 05 50 c6    mov    0x50c6 ,#0x05[0K
+F 0x00806d
+timer get
+timer #1("time") ON 0.003215812500000 sec (1435 clks)
+timer #2("isr") ON,ISR 0.000000000000000 sec (0 clks)
+timer #3("idle") ON,IDLE 0.000000000000000 sec (0 clks)
+timer #4("halt") ON,HALT 0.000000000000000 sec (0 clks)
+dump CLK_CKDIVR[7:0]
+0x050c6      CLK_CKDIVR[7:0]:           0b00000100 0x04 '.'   4
+             CLK_CKDIVR_HSIDIV:         0b---00--- 0x00 '.'   0
+             CLK_CKDIVR_CPUDIV:         0b-----100 0x04 '.'   4
+info hw clk
+clk[0] at 0x0050c0
+  LSI
+  f_OSC:    128000 Hz
+  HSIDIV:   1
+  f_MASTER: 128000 Hz
+  CPUDIV:   16
+  f_CPU:    8000 Hz
+  PCKENR1:  0xff
+  PCKENR2:  0xff
+step
+
+Stop at 0x008071: (109) stepped 16 ticks
+V-IHINZC  Flags= 0x28  40 (  A= 0x00   0 .
+0-101000  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17ff [SP+1]= 00   0 .  Limit= 0x1500
+0x08071    35 06 50 c6    mov    0x50c6 ,#0x06[0K
+F 0x008071
+timer get
+timer #1("time") ON 0.003340812500000 sec (1451 clks)
+timer #2("isr") ON,ISR 0.000000000000000 sec (0 clks)
+timer #3("idle") ON,IDLE 0.000000000000000 sec (0 clks)
+timer #4("halt") ON,HALT 0.000000000000000 sec (0 clks)
+dump CLK_CKDIVR[7:0]
+0x050c6      CLK_CKDIVR[7:0]:           0b00000101 0x05 '.'   5
+             CLK_CKDIVR_HSIDIV:         0b---00--- 0x00 '.'   0
+             CLK_CKDIVR_CPUDIV:         0b-----101 0x05 '.'   5
+info hw clk
+clk[0] at 0x0050c0
+  LSI
+  f_OSC:    128000 Hz
+  HSIDIV:   1
+  f_MASTER: 128000 Hz
+  CPUDIV:   32
+  f_CPU:    4000 Hz
+  PCKENR1:  0xff
+  PCKENR2:  0xff
+step
+
+Stop at 0x008075: (109) stepped 32 ticks
+V-IHINZC  Flags= 0x28  40 (  A= 0x00   0 .
+0-101000  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17ff [SP+1]= 00   0 .  Limit= 0x1500
+0x08075    35 07 50 c6    mov    0x50c6 ,#0x07[0K
+F 0x008075
+timer get
+timer #1("time") ON 0.003590812500000 sec (1483 clks)
+timer #2("isr") ON,ISR 0.000000000000000 sec (0 clks)
+timer #3("idle") ON,IDLE 0.000000000000000 sec (0 clks)
+timer #4("halt") ON,HALT 0.000000000000000 sec (0 clks)
+dump CLK_CKDIVR[7:0]
+0x050c6      CLK_CKDIVR[7:0]:           0b00000110 0x06 '.'   6
+             CLK_CKDIVR_HSIDIV:         0b---00--- 0x00 '.'   0
+             CLK_CKDIVR_CPUDIV:         0b-----110 0x06 '.'   6
+info hw clk
+clk[0] at 0x0050c0
+  LSI
+  f_OSC:    128000 Hz
+  HSIDIV:   1
+  f_MASTER: 128000 Hz
+  CPUDIV:   64
+  f_CPU:    2000 Hz
+  PCKENR1:  0xff
+  PCKENR2:  0xff
+step
+
+Stop at 0x008079: (109) stepped 64 ticks
+V-IHINZC  Flags= 0x28  40 (  A= 0x00   0 .
+0-101000  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17ff [SP+1]= 00   0 .  Limit= 0x1500
+0x08079    00 00          neg    (0x00,SP)[0K
+F 0x008079
+timer get
+timer #1("time") ON 0.004090812500000 sec (1547 clks)
+timer #2("isr") ON,ISR 0.000000000000000 sec (0 clks)
+timer #3("idle") ON,IDLE 0.000000000000000 sec (0 clks)
+timer #4("halt") ON,HALT 0.000000000000000 sec (0 clks)
+dump CLK_CKDIVR[7:0]
+0x050c6      CLK_CKDIVR[7:0]:           0b00000111 0x07 '.'   7
+             CLK_CKDIVR_HSIDIV:         0b---00--- 0x00 '.'   0
+             CLK_CKDIVR_CPUDIV:         0b-----111 0x07 '.'   7
+info hw clk
+clk[0] at 0x0050c0
+  LSI
+  f_OSC:    128000 Hz
+  HSIDIV:   1
+  f_MASTER: 128000 Hz
+  CPUDIV:   128
+  f_CPU:    1000 Hz
+  PCKENR1:  0xff
+  PCKENR2:  0xff
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/clk/Makefile sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/clk/Makefile
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/clk/Makefile	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/clk/Makefile	2022-01-20 15:57:08.000000000 +0000
@@ -0,0 +1,10 @@
+OUTPUTS = stdout
+
+TYPE = S005
+
+
+stdout:	test.cmd test.ihx
+	$(call run-sim)
+
+
+include test-lib.mk
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/clk/test.asm sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/clk/test.asm
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/clk/test.asm	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/clk/test.asm	2022-01-20 15:57:08.000000000 +0000
@@ -0,0 +1,70 @@
+	; For an STM8S005
+
+	CLK_SWR               =: 0x50c4
+	CLK_SWR_HSI           =: 0xE1 ; VALUE: HSI selected as master clock source (reset value)
+	CLK_SWR_LSI           =: 0xD2 ; VALUE: LSI selected as master clock source
+
+	CLK_SWCR              =: 0x50c5
+	CLK_SWCR_SWEN         =: 1 ; Switch start/stop
+	CLK_SWCR_SWBSY        =: 0 ; Switch busy
+
+	CLK_CKDIVR            =: 0x50c6
+	CLK_CKDIVR_HSIDIV     =: 3 ; Bits [4:3]: High speed internal clock prescaler
+	CLK_CKDIVR_HSIDIV_1   =: (0b00 << CLK_CKDIVR_HSIDIV) ; f_HSI = f_HSI RC output
+	CLK_CKDIVR_HSIDIV_2   =: (0b01 << CLK_CKDIVR_HSIDIV) ; f_HSI = f_HSI RC output / 2
+	CLK_CKDIVR_HSIDIV_4   =: (0b10 << CLK_CKDIVR_HSIDIV) ; f_HSI = f_HSI RC output / 4
+	CLK_CKDIVR_HSIDIV_8   =: (0b11 << CLK_CKDIVR_HSIDIV) ; f_HSI = f_HSI RC output / 8
+
+        CLK_CKDIVR_CPUDIV     =: 0 ; Bits [2:0]: CPU clock prescaler
+	CLK_CKDIVR_CPUDIV_1   =: (0b000 << CLK_CKDIVR_CPUDIV) ; f_CPU = f_MASTER RC output
+	CLK_CKDIVR_CPUDIV_2   =: (0b001 << CLK_CKDIVR_CPUDIV) ; f_CPU = f_MASTER RC output / 2
+	CLK_CKDIVR_CPUDIV_4   =: (0b010 << CLK_CKDIVR_CPUDIV) ; f_CPU = f_MASTER RC output / 4
+	CLK_CKDIVR_CPUDIV_8   =: (0b011 << CLK_CKDIVR_CPUDIV) ; f_CPU = f_MASTER RC output / 8
+	CLK_CKDIVR_CPUDIV_16  =: (0b100 << CLK_CKDIVR_CPUDIV) ; f_CPU = f_MASTER RC output / 16
+	CLK_CKDIVR_CPUDIV_32  =: (0b101 << CLK_CKDIVR_CPUDIV) ; f_CPU = f_MASTER RC output / 32
+	CLK_CKDIVR_CPUDIV_64  =: (0b110 << CLK_CKDIVR_CPUDIV) ; f_CPU = f_MASTER RC output / 64
+	CLK_CKDIVR_CPUDIV_128 =: (0b111 << CLK_CKDIVR_CPUDIV) ; f_CPU = f_MASTER RC output / 128
+
+	.area _DATA
+loc1:	.ds 1
+loc2:	.ds 1
+
+	.area _CODE
+	int reset
+
+reset:
+	mov CLK_CKDIVR, #(CLK_CKDIVR_HSIDIV_1 | CLK_CKDIVR_CPUDIV_1)
+	mov CLK_CKDIVR, #(CLK_CKDIVR_HSIDIV_2 | CLK_CKDIVR_CPUDIV_1)
+	mov CLK_CKDIVR, #(CLK_CKDIVR_HSIDIV_4 | CLK_CKDIVR_CPUDIV_1)
+	mov CLK_CKDIVR, #(CLK_CKDIVR_HSIDIV_8 | CLK_CKDIVR_CPUDIV_1)
+
+	mov CLK_CKDIVR, #(CLK_CKDIVR_HSIDIV_1 | CLK_CKDIVR_CPUDIV_1)
+	mov CLK_CKDIVR, #(CLK_CKDIVR_HSIDIV_1 | CLK_CKDIVR_CPUDIV_2)
+	mov CLK_CKDIVR, #(CLK_CKDIVR_HSIDIV_1 | CLK_CKDIVR_CPUDIV_4)
+	mov CLK_CKDIVR, #(CLK_CKDIVR_HSIDIV_1 | CLK_CKDIVR_CPUDIV_8)
+	mov CLK_CKDIVR, #(CLK_CKDIVR_HSIDIV_1 | CLK_CKDIVR_CPUDIV_16)
+	mov CLK_CKDIVR, #(CLK_CKDIVR_HSIDIV_1 | CLK_CKDIVR_CPUDIV_32)
+	mov CLK_CKDIVR, #(CLK_CKDIVR_HSIDIV_1 | CLK_CKDIVR_CPUDIV_64)
+	mov CLK_CKDIVR, #(CLK_CKDIVR_HSIDIV_1 | CLK_CKDIVR_CPUDIV_128)
+
+	; Now change to the LSI clock
+	bset 0x4805, #3
+	bres 0x4806, #3
+	bset CLK_SWCR, #CLK_SWCR_SWEN
+	mov  CLK_SWR, #CLK_SWR_LSI
+wait:	btjt CLK_SWCR, #CLK_SWCR_SWBSY, wait
+
+	; And do it all again
+	mov CLK_CKDIVR, #(CLK_CKDIVR_HSIDIV_1 | CLK_CKDIVR_CPUDIV_1)
+	mov CLK_CKDIVR, #(CLK_CKDIVR_HSIDIV_2 | CLK_CKDIVR_CPUDIV_1)
+	mov CLK_CKDIVR, #(CLK_CKDIVR_HSIDIV_4 | CLK_CKDIVR_CPUDIV_1)
+	mov CLK_CKDIVR, #(CLK_CKDIVR_HSIDIV_8 | CLK_CKDIVR_CPUDIV_1)
+
+	mov CLK_CKDIVR, #(CLK_CKDIVR_HSIDIV_1 | CLK_CKDIVR_CPUDIV_1)
+	mov CLK_CKDIVR, #(CLK_CKDIVR_HSIDIV_1 | CLK_CKDIVR_CPUDIV_2)
+	mov CLK_CKDIVR, #(CLK_CKDIVR_HSIDIV_1 | CLK_CKDIVR_CPUDIV_4)
+	mov CLK_CKDIVR, #(CLK_CKDIVR_HSIDIV_1 | CLK_CKDIVR_CPUDIV_8)
+	mov CLK_CKDIVR, #(CLK_CKDIVR_HSIDIV_1 | CLK_CKDIVR_CPUDIV_16)
+	mov CLK_CKDIVR, #(CLK_CKDIVR_HSIDIV_1 | CLK_CKDIVR_CPUDIV_32)
+	mov CLK_CKDIVR, #(CLK_CKDIVR_HSIDIV_1 | CLK_CKDIVR_CPUDIV_64)
+	mov CLK_CKDIVR, #(CLK_CKDIVR_HSIDIV_1 | CLK_CKDIVR_CPUDIV_128)
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/clk/test.cmd sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/clk/test.cmd
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/clk/test.cmd	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/clk/test.cmd	2022-01-20 15:57:08.000000000 +0000
@@ -0,0 +1,106 @@
+step
+timer get
+dump CLK_CKDIVR[7:0]
+info hw clk
+step
+timer get
+dump CLK_CKDIVR[7:0]
+info hw clk
+step
+timer get
+dump CLK_CKDIVR[7:0]
+info hw clk
+step
+timer get
+dump CLK_CKDIVR[7:0]
+info hw clk
+step
+timer get
+dump CLK_CKDIVR[7:0]
+info hw clk
+step
+timer get
+dump CLK_CKDIVR[7:0]
+info hw clk
+step
+timer get
+dump CLK_CKDIVR[7:0]
+info hw clk
+step
+timer get
+dump CLK_CKDIVR[7:0]
+info hw clk
+step
+timer get
+dump CLK_CKDIVR[7:0]
+info hw clk
+step
+timer get
+dump CLK_CKDIVR[7:0]
+info hw clk
+step
+timer get
+dump CLK_CKDIVR[7:0]
+info hw clk
+step
+timer get
+dump CLK_CKDIVR[7:0]
+info hw clk
+step
+timer get
+dump CLK_CKDIVR[7:0]
+info hw clk
+
+step 5
+
+timer get
+dump CLK_CKDIVR[7:0]
+info hw clk
+step
+timer get
+dump CLK_CKDIVR[7:0]
+info hw clk
+step
+timer get
+dump CLK_CKDIVR[7:0]
+info hw clk
+step
+timer get
+dump CLK_CKDIVR[7:0]
+info hw clk
+step
+timer get
+dump CLK_CKDIVR[7:0]
+info hw clk
+step
+timer get
+dump CLK_CKDIVR[7:0]
+info hw clk
+step
+timer get
+dump CLK_CKDIVR[7:0]
+info hw clk
+step
+timer get
+dump CLK_CKDIVR[7:0]
+info hw clk
+step
+timer get
+dump CLK_CKDIVR[7:0]
+info hw clk
+step
+timer get
+dump CLK_CKDIVR[7:0]
+info hw clk
+step
+timer get
+dump CLK_CKDIVR[7:0]
+info hw clk
+step
+timer get
+dump CLK_CKDIVR[7:0]
+info hw clk
+step
+timer get
+dump CLK_CKDIVR[7:0]
+info hw clk
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/clk/test.ihx sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/clk/test.ihx
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/clk/test.ihx	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/clk/test.ihx	2022-01-20 15:57:08.000000000 +0000
@@ -0,0 +1,5 @@
+:2080000082008004350050C6350850C6351050C6351850C6350050C6350150C6350250C61A
+:20802000350350C6350450C6350550C6350650C6350750C67216480572174806721250C56B
+:2080400035D250C4720050C5FB350050C6350850C6351050C6351850C6350050C635015056
+:19806000C6350250C6350350C6350450C6350550C6350650C6350750C664
+:00000001FF
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/conf.cmd sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/conf.cmd
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/conf.cmd	2016-07-26 21:10:26.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/conf.cmd	1970-01-01 00:00:00.000000000 +0000
@@ -1,2 +0,0 @@
-set hw simif rom 0x7fff
-set opt debug 1
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/config/baseline/AF52 sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/config/baseline/AF52
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/config/baseline/AF52	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/config/baseline/AF52	2022-02-08 21:21:05.000000000 +0000
@@ -0,0 +1,60 @@
+uCsim, Copyright (C)  Daniel Drotos.
+uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+This is free software, and you are welcome to redistribute it
+under certain conditions; type `show c' for details.
+Type of microcontroller: STM8 S,AF 52
+Controller has 24 hardware element(s).
+   on cpu[0]
+   on simif[0]
+  off vcd[0]
+   on dreg[0]
+   on dport[0]
+   on clk[0]
+   on uart[1]
+   on uart[3]
+   on itc[0]
+   on pa[0]
+   on pb[0]
+   on pc[0]
+   on pd[0]
+   on pe[0]
+   on pf[0]
+   on pg[0]
+   on ph[0]
+   on pi[0]
+   on rst[0]
+   on tim1[1]
+   on tim2[2]
+   on tim3[3]
+   on tim4[4]
+   on flash[0]
+V-IHINZC  Flags= 0x28  40 (  A= 0x00   0 .
+0-101000  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17ff [SP+1]= 00   0 .  Limit= 0x1500
+0x08000  ? 00 00          neg    (0x00,SP)[0K
+Memory chips:
+  0x000000-0x0000ff      256 variable_storage (32,%08x,0x%02lx)
+  0x000000-0x0017ff     6144 ram_chip (8,%02x,0x%04lx)
+  0x000000-0x0007ff     2048 eeprom_chip (8,%02x,0x%03lx)
+  0x000000-0x0007ff     2048 option_chip (8,%02x,0x%03lx)
+  0x000000-0x0007ff     2048 io_chip (8,%02x,0x%03lx)
+  0x000000-0x0007ff     2048 boot_chip (8,%02x,0x%03lx)
+  0x000000-0x0000ff      256 cpu_chip (8,%02x,0x%02lx)
+  0x000000-0x01ffff   131072 flash_chip (8,%02x,0x%05lx)
+  0x000000-0x000004        5 ports_chip (8,%02x,0x%01lx)
+Address spaces:
+  0x000000-0x0000ff      256 variables (32,%08x,0x%02lx)
+  0x000000-0x027fff   163840 rom (8,%02x,0x%05lx)
+  0x000000-0x000001        2 regs8 (8,%02x,0x%01lx)
+  0x000000-0x000002        3 regs16 (16,%04x,0x%01lx)
+  0x000000-0x000004        5 ports (8,%02x,0x%01lx)
+Address decoders:
+  variables 0x00 0xff -> variable_storage 0x00 activated
+  rom 0x00000 0x017ff -> ram_chip 0x0000 activated
+  rom 0x04000 0x047ff -> eeprom_chip 0x000 activated
+  rom 0x04800 0x04fff -> option_chip 0x000 activated
+  rom 0x05000 0x057ff -> io_chip 0x000 activated
+  rom 0x06000 0x067ff -> boot_chip 0x000 activated
+  rom 0x07f00 0x07fff -> cpu_chip 0x00 activated
+  rom 0x08000 0x27fff -> flash_chip 0x00000 activated
+  ports 0x0 0x4 -> ports_chip 0x0 activated
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/config/baseline/AF62 sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/config/baseline/AF62
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/config/baseline/AF62	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/config/baseline/AF62	2022-02-08 21:21:05.000000000 +0000
@@ -0,0 +1,57 @@
+uCsim, Copyright (C)  Daniel Drotos.
+uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+This is free software, and you are welcome to redistribute it
+under certain conditions; type `show c' for details.
+Type of microcontroller: STM8 S,AF 624[68], 626[68]
+Controller has 21 hardware element(s).
+   on cpu[0]
+   on simif[0]
+  off vcd[0]
+   on dreg[0]
+   on dport[0]
+   on clk[0]
+   on uart[2]
+   on itc[0]
+   on pa[0]
+   on pb[0]
+   on pc[0]
+   on pd[0]
+   on pe[0]
+   on pf[0]
+   on pg[0]
+   on rst[0]
+   on tim1[1]
+   on tim2[2]
+   on tim3[3]
+   on tim4[4]
+   on flash[0]
+V-IHINZC  Flags= 0x28  40 (  A= 0x00   0 .
+0-101000  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17ff [SP+1]= 00   0 .  Limit= 0x1500
+0x08000  ? 00 00          neg    (0x00,SP)[0K
+Memory chips:
+  0x000000-0x0000ff      256 variable_storage (32,%08x,0x%02lx)
+  0x000000-0x0017ff     6144 ram_chip (8,%02x,0x%04lx)
+  0x000000-0x0007ff     2048 eeprom_chip (8,%02x,0x%03lx)
+  0x000000-0x0007ff     2048 option_chip (8,%02x,0x%03lx)
+  0x000000-0x0007ff     2048 io_chip (8,%02x,0x%03lx)
+  0x000000-0x0007ff     2048 boot_chip (8,%02x,0x%03lx)
+  0x000000-0x0000ff      256 cpu_chip (8,%02x,0x%02lx)
+  0x000000-0x01ffff   131072 flash_chip (8,%02x,0x%05lx)
+  0x000000-0x000006        7 ports_chip (8,%02x,0x%01lx)
+Address spaces:
+  0x000000-0x0000ff      256 variables (32,%08x,0x%02lx)
+  0x000000-0x027fff   163840 rom (8,%02x,0x%05lx)
+  0x000000-0x000001        2 regs8 (8,%02x,0x%01lx)
+  0x000000-0x000002        3 regs16 (16,%04x,0x%01lx)
+  0x000000-0x000006        7 ports (8,%02x,0x%01lx)
+Address decoders:
+  variables 0x00 0xff -> variable_storage 0x00 activated
+  rom 0x00000 0x017ff -> ram_chip 0x0000 activated
+  rom 0x04000 0x047ff -> eeprom_chip 0x000 activated
+  rom 0x04800 0x04fff -> option_chip 0x000 activated
+  rom 0x05000 0x057ff -> io_chip 0x000 activated
+  rom 0x06000 0x067ff -> boot_chip 0x000 activated
+  rom 0x07f00 0x07fff -> cpu_chip 0x00 activated
+  rom 0x08000 0x27fff -> flash_chip 0x00000 activated
+  ports 0x0 0x6 -> ports_chip 0x0 activated
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/config/baseline/AF62_12 sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/config/baseline/AF62_12
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/config/baseline/AF62_12	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/config/baseline/AF62_12	2022-02-08 21:21:05.000000000 +0000
@@ -0,0 +1,56 @@
+uCsim, Copyright (C)  Daniel Drotos.
+uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+This is free software, and you are welcome to redistribute it
+under certain conditions; type `show c' for details.
+Type of microcontroller: STM8 S,AF 62[12]3, 622[36]A
+Controller has 20 hardware element(s).
+   on cpu[0]
+   on simif[0]
+  off vcd[0]
+   on dreg[0]
+   on dport[0]
+   on clk[0]
+   on uart[4]
+   on itc[0]
+   on pa[0]
+   on pb[0]
+   on pc[0]
+   on pd[0]
+   on pe[0]
+   on pf[0]
+   on rst[0]
+   on tim1[1]
+   on tim5[5]
+   on tim6[6]
+   on uid[0]
+   on flash[0]
+V-IHINZC  Flags= 0x28  40 (  A= 0x00   0 .
+0-101000  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17ff [SP+1]= 00   0 .  Limit= 0x1500
+0x08000  ? 00 00          neg    (0x00,SP)[0K
+Memory chips:
+  0x000000-0x0000ff      256 variable_storage (32,%08x,0x%02lx)
+  0x000000-0x0017ff     6144 ram_chip (8,%02x,0x%04lx)
+  0x000000-0x0007ff     2048 eeprom_chip (8,%02x,0x%03lx)
+  0x000000-0x0007ff     2048 option_chip (8,%02x,0x%03lx)
+  0x000000-0x0007ff     2048 io_chip (8,%02x,0x%03lx)
+  0x000000-0x0007ff     2048 boot_chip (8,%02x,0x%03lx)
+  0x000000-0x0000ff      256 cpu_chip (8,%02x,0x%02lx)
+  0x000000-0x01ffff   131072 flash_chip (8,%02x,0x%05lx)
+  0x000000-0x000003        4 ports_chip (8,%02x,0x%01lx)
+Address spaces:
+  0x000000-0x0000ff      256 variables (32,%08x,0x%02lx)
+  0x000000-0x027fff   163840 rom (8,%02x,0x%05lx)
+  0x000000-0x000001        2 regs8 (8,%02x,0x%01lx)
+  0x000000-0x000002        3 regs16 (16,%04x,0x%01lx)
+  0x000000-0x000003        4 ports (8,%02x,0x%01lx)
+Address decoders:
+  variables 0x00 0xff -> variable_storage 0x00 activated
+  rom 0x00000 0x017ff -> ram_chip 0x0000 activated
+  rom 0x04000 0x047ff -> eeprom_chip 0x000 activated
+  rom 0x04800 0x04fff -> option_chip 0x000 activated
+  rom 0x05000 0x057ff -> io_chip 0x000 activated
+  rom 0x06000 0x067ff -> boot_chip 0x000 activated
+  rom 0x07f00 0x07fff -> cpu_chip 0x00 activated
+  rom 0x08000 0x27fff -> flash_chip 0x00000 activated
+  ports 0x0 0x3 -> ports_chip 0x0 activated
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/config/baseline/AL3x346 sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/config/baseline/AL3x346
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/config/baseline/AL3x346	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/config/baseline/AL3x346	2022-02-08 21:21:05.000000000 +0000
@@ -0,0 +1,57 @@
+uCsim, Copyright (C)  Daniel Drotos.
+uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+This is free software, and you are welcome to redistribute it
+under certain conditions; type `show c' for details.
+Type of microcontroller: STM8 AL,L 31[346]x, 3L[46]x
+Controller has 21 hardware element(s).
+   on cpu[0]
+   on simif[0]
+  off vcd[0]
+   on dreg[0]
+   on dport[0]
+   on clk[0]
+   on uart[1]
+   on itc[0]
+   on pa[0]
+   on pb[0]
+   on pc[0]
+   on pd[0]
+   on pe[0]
+   on pf[0]
+   on rst[0]
+   on tim2[2]
+   on tim3[3]
+   on tim4[4]
+   on tim1[1]
+   on uid[0]
+   on flash[0]
+V-IHINZC  Flags= 0x28  40 (  A= 0x00   0 .
+0-101000  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17ff [SP+1]= 00   0 .  Limit= 0x1500
+0x08000  ? 00 00          neg    (0x00,SP)[0K
+Memory chips:
+  0x000000-0x0000ff      256 variable_storage (32,%08x,0x%02lx)
+  0x000000-0x0017ff     6144 ram_chip (8,%02x,0x%04lx)
+  0x000000-0x0007ff     2048 eeprom_chip (8,%02x,0x%03lx)
+  0x000000-0x0007ff     2048 option_chip (8,%02x,0x%03lx)
+  0x000000-0x0007ff     2048 io_chip (8,%02x,0x%03lx)
+  0x000000-0x0007ff     2048 boot_chip (8,%02x,0x%03lx)
+  0x000000-0x0000ff      256 cpu_chip (8,%02x,0x%02lx)
+  0x000000-0x01ffff   131072 flash_chip (8,%02x,0x%05lx)
+  0x000000-0x000005        6 ports_chip (8,%02x,0x%01lx)
+Address spaces:
+  0x000000-0x0000ff      256 variables (32,%08x,0x%02lx)
+  0x000000-0x027fff   163840 rom (8,%02x,0x%05lx)
+  0x000000-0x000001        2 regs8 (8,%02x,0x%01lx)
+  0x000000-0x000002        3 regs16 (16,%04x,0x%01lx)
+  0x000000-0x000005        6 ports (8,%02x,0x%01lx)
+Address decoders:
+  variables 0x00 0xff -> variable_storage 0x00 activated
+  rom 0x00000 0x017ff -> ram_chip 0x0000 activated
+  rom 0x04000 0x047ff -> eeprom_chip 0x000 activated
+  rom 0x04800 0x04fff -> option_chip 0x000 activated
+  rom 0x05000 0x057ff -> io_chip 0x000 activated
+  rom 0x06000 0x067ff -> boot_chip 0x000 activated
+  rom 0x07f00 0x07fff -> cpu_chip 0x00 activated
+  rom 0x08000 0x27fff -> flash_chip 0x00000 activated
+  ports 0x0 0x5 -> ports_chip 0x0 activated
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/config/baseline/AL3x8 sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/config/baseline/AL3x8
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/config/baseline/AL3x8	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/config/baseline/AL3x8	2022-02-08 21:21:05.000000000 +0000
@@ -0,0 +1,63 @@
+uCsim, Copyright (C)  Daniel Drotos.
+uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+This is free software, and you are welcome to redistribute it
+under certain conditions; type `show c' for details.
+Type of microcontroller: STM8 AL,L 318x, 3L8x
+Controller has 27 hardware element(s).
+   on cpu[0]
+   on simif[0]
+  off vcd[0]
+   on dreg[0]
+   on dport[0]
+   on clk[0]
+   on uart[1]
+   on uart[2]
+   on uart[3]
+   on itc[0]
+   on pa[0]
+   on pb[0]
+   on pc[0]
+   on pd[0]
+   on pe[0]
+   on pf[0]
+   on pg[0]
+   on ph[0]
+   on pi[0]
+  off rst[0]
+   on tim2[2]
+   on tim3[3]
+   on tim4[4]
+   on tim1[1]
+   on tim5[5]
+   on uid[0]
+   on flash[0]
+V-IHINZC  Flags= 0x28  40 (  A= 0x00   0 .
+0-101000  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17ff [SP+1]= 00   0 .  Limit= 0x1500
+0x08000  ? 00 00          neg    (0x00,SP)[0K
+Memory chips:
+  0x000000-0x0000ff      256 variable_storage (32,%08x,0x%02lx)
+  0x000000-0x0017ff     6144 ram_chip (8,%02x,0x%04lx)
+  0x000000-0x0007ff     2048 eeprom_chip (8,%02x,0x%03lx)
+  0x000000-0x0007ff     2048 option_chip (8,%02x,0x%03lx)
+  0x000000-0x0007ff     2048 io_chip (8,%02x,0x%03lx)
+  0x000000-0x0007ff     2048 boot_chip (8,%02x,0x%03lx)
+  0x000000-0x0000ff      256 cpu_chip (8,%02x,0x%02lx)
+  0x000000-0x01ffff   131072 flash_chip (8,%02x,0x%05lx)
+  0x000000-0x000008        9 ports_chip (8,%02x,0x%01lx)
+Address spaces:
+  0x000000-0x0000ff      256 variables (32,%08x,0x%02lx)
+  0x000000-0x027fff   163840 rom (8,%02x,0x%05lx)
+  0x000000-0x000001        2 regs8 (8,%02x,0x%01lx)
+  0x000000-0x000002        3 regs16 (16,%04x,0x%01lx)
+  0x000000-0x000008        9 ports (8,%02x,0x%01lx)
+Address decoders:
+  variables 0x00 0xff -> variable_storage 0x00 activated
+  rom 0x00000 0x017ff -> ram_chip 0x0000 activated
+  rom 0x04000 0x047ff -> eeprom_chip 0x000 activated
+  rom 0x04800 0x04fff -> option_chip 0x000 activated
+  rom 0x05000 0x057ff -> io_chip 0x000 activated
+  rom 0x06000 0x067ff -> boot_chip 0x000 activated
+  rom 0x07f00 0x07fff -> cpu_chip 0x00 activated
+  rom 0x08000 0x27fff -> flash_chip 0x00000 activated
+  ports 0x0 0x8 -> ports_chip 0x0 activated
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/config/baseline/AL3xE sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/config/baseline/AL3xE
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/config/baseline/AL3xE	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/config/baseline/AL3xE	2022-02-08 21:21:05.000000000 +0000
@@ -0,0 +1,63 @@
+uCsim, Copyright (C)  Daniel Drotos.
+uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+This is free software, and you are welcome to redistribute it
+under certain conditions; type `show c' for details.
+Type of microcontroller: STM8 AL,L 31E8x, 3LE8x
+Controller has 27 hardware element(s).
+   on cpu[0]
+   on simif[0]
+  off vcd[0]
+   on dreg[0]
+   on dport[0]
+   on clk[0]
+   on uart[1]
+   on uart[2]
+   on uart[3]
+   on itc[0]
+   on pa[0]
+   on pb[0]
+   on pc[0]
+   on pd[0]
+   on pe[0]
+   on pf[0]
+   on pg[0]
+   on ph[0]
+   on pi[0]
+  off rst[0]
+   on tim2[2]
+   on tim3[3]
+   on tim4[4]
+   on tim1[1]
+   on tim5[5]
+   on uid[0]
+   on flash[0]
+V-IHINZC  Flags= 0x28  40 (  A= 0x00   0 .
+0-101000  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17ff [SP+1]= 00   0 .  Limit= 0x1500
+0x08000  ? 00 00          neg    (0x00,SP)[0K
+Memory chips:
+  0x000000-0x0000ff      256 variable_storage (32,%08x,0x%02lx)
+  0x000000-0x0017ff     6144 ram_chip (8,%02x,0x%04lx)
+  0x000000-0x0007ff     2048 eeprom_chip (8,%02x,0x%03lx)
+  0x000000-0x0007ff     2048 option_chip (8,%02x,0x%03lx)
+  0x000000-0x0007ff     2048 io_chip (8,%02x,0x%03lx)
+  0x000000-0x0007ff     2048 boot_chip (8,%02x,0x%03lx)
+  0x000000-0x0000ff      256 cpu_chip (8,%02x,0x%02lx)
+  0x000000-0x01ffff   131072 flash_chip (8,%02x,0x%05lx)
+  0x000000-0x000008        9 ports_chip (8,%02x,0x%01lx)
+Address spaces:
+  0x000000-0x0000ff      256 variables (32,%08x,0x%02lx)
+  0x000000-0x027fff   163840 rom (8,%02x,0x%05lx)
+  0x000000-0x000001        2 regs8 (8,%02x,0x%01lx)
+  0x000000-0x000002        3 regs16 (16,%04x,0x%01lx)
+  0x000000-0x000008        9 ports (8,%02x,0x%01lx)
+Address decoders:
+  variables 0x00 0xff -> variable_storage 0x00 activated
+  rom 0x00000 0x017ff -> ram_chip 0x0000 activated
+  rom 0x04000 0x047ff -> eeprom_chip 0x000 activated
+  rom 0x04800 0x04fff -> option_chip 0x000 activated
+  rom 0x05000 0x057ff -> io_chip 0x000 activated
+  rom 0x06000 0x067ff -> boot_chip 0x000 activated
+  rom 0x07f00 0x07fff -> cpu_chip 0x00 activated
+  rom 0x08000 0x27fff -> flash_chip 0x00000 activated
+  ports 0x0 0x8 -> ports_chip 0x0 activated
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/config/baseline/L sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/config/baseline/L
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/config/baseline/L	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/config/baseline/L	2022-02-08 21:21:05.000000000 +0000
@@ -0,0 +1,63 @@
+uCsim, Copyright (C)  Daniel Drotos.
+uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+This is free software, and you are welcome to redistribute it
+under certain conditions; type `show c' for details.
+Type of microcontroller: STM8 AL,L 162[RM]8
+Controller has 27 hardware element(s).
+   on cpu[0]
+   on simif[0]
+  off vcd[0]
+   on dreg[0]
+   on dport[0]
+   on clk[0]
+   on uart[1]
+   on uart[2]
+   on uart[3]
+   on itc[0]
+   on pa[0]
+   on pb[0]
+   on pc[0]
+   on pd[0]
+   on pe[0]
+   on pf[0]
+   on pg[0]
+   on ph[0]
+   on pi[0]
+  off rst[0]
+   on tim2[2]
+   on tim3[3]
+   on tim4[4]
+   on tim1[1]
+   on tim5[5]
+   on uid[0]
+   on flash[0]
+V-IHINZC  Flags= 0x28  40 (  A= 0x00   0 .
+0-101000  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17ff [SP+1]= 00   0 .  Limit= 0x1500
+0x08000  ? 00 00          neg    (0x00,SP)[0K
+Memory chips:
+  0x000000-0x0000ff      256 variable_storage (32,%08x,0x%02lx)
+  0x000000-0x0017ff     6144 ram_chip (8,%02x,0x%04lx)
+  0x000000-0x0007ff     2048 eeprom_chip (8,%02x,0x%03lx)
+  0x000000-0x0007ff     2048 option_chip (8,%02x,0x%03lx)
+  0x000000-0x0007ff     2048 io_chip (8,%02x,0x%03lx)
+  0x000000-0x0007ff     2048 boot_chip (8,%02x,0x%03lx)
+  0x000000-0x0000ff      256 cpu_chip (8,%02x,0x%02lx)
+  0x000000-0x01ffff   131072 flash_chip (8,%02x,0x%05lx)
+  0x000000-0x000008        9 ports_chip (8,%02x,0x%01lx)
+Address spaces:
+  0x000000-0x0000ff      256 variables (32,%08x,0x%02lx)
+  0x000000-0x027fff   163840 rom (8,%02x,0x%05lx)
+  0x000000-0x000001        2 regs8 (8,%02x,0x%01lx)
+  0x000000-0x000002        3 regs16 (16,%04x,0x%01lx)
+  0x000000-0x000008        9 ports (8,%02x,0x%01lx)
+Address decoders:
+  variables 0x00 0xff -> variable_storage 0x00 activated
+  rom 0x00000 0x017ff -> ram_chip 0x0000 activated
+  rom 0x04000 0x047ff -> eeprom_chip 0x000 activated
+  rom 0x04800 0x04fff -> option_chip 0x000 activated
+  rom 0x05000 0x057ff -> io_chip 0x000 activated
+  rom 0x06000 0x067ff -> boot_chip 0x000 activated
+  rom 0x07f00 0x07fff -> cpu_chip 0x00 activated
+  rom 0x08000 0x27fff -> flash_chip 0x00000 activated
+  ports 0x0 0x8 -> ports_chip 0x0 activated
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/config/baseline/L051 sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/config/baseline/L051
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/config/baseline/L051	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/config/baseline/L051	2022-02-08 21:21:05.000000000 +0000
@@ -0,0 +1,53 @@
+uCsim, Copyright (C)  Daniel Drotos.
+uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+This is free software, and you are welcome to redistribute it
+under certain conditions; type `show c' for details.
+Type of microcontroller: STM8 AL,L 051F3
+Controller has 17 hardware element(s).
+   on cpu[0]
+   on simif[0]
+  off vcd[0]
+   on dreg[0]
+   on dport[0]
+   on clk[0]
+   on uart[1]
+   on itc[0]
+   on pa[0]
+   on pb[0]
+   on pc[0]
+   on pd[0]
+   on rst[0]
+   on tim2[2]
+   on tim3[3]
+   on tim4[4]
+   on flash[0]
+V-IHINZC  Flags= 0x28  40 (  A= 0x00   0 .
+0-101000  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17ff [SP+1]= 00   0 .  Limit= 0x1500
+0x08000  ? 00 00          neg    (0x00,SP)[0K
+Memory chips:
+  0x000000-0x0000ff      256 variable_storage (32,%08x,0x%02lx)
+  0x000000-0x0017ff     6144 ram_chip (8,%02x,0x%04lx)
+  0x000000-0x0007ff     2048 eeprom_chip (8,%02x,0x%03lx)
+  0x000000-0x0007ff     2048 option_chip (8,%02x,0x%03lx)
+  0x000000-0x0007ff     2048 io_chip (8,%02x,0x%03lx)
+  0x000000-0x0007ff     2048 boot_chip (8,%02x,0x%03lx)
+  0x000000-0x0000ff      256 cpu_chip (8,%02x,0x%02lx)
+  0x000000-0x01ffff   131072 flash_chip (8,%02x,0x%05lx)
+  0x000000-0x000003        4 ports_chip (8,%02x,0x%01lx)
+Address spaces:
+  0x000000-0x0000ff      256 variables (32,%08x,0x%02lx)
+  0x000000-0x027fff   163840 rom (8,%02x,0x%05lx)
+  0x000000-0x000001        2 regs8 (8,%02x,0x%01lx)
+  0x000000-0x000002        3 regs16 (16,%04x,0x%01lx)
+  0x000000-0x000003        4 ports (8,%02x,0x%01lx)
+Address decoders:
+  variables 0x00 0xff -> variable_storage 0x00 activated
+  rom 0x00000 0x017ff -> ram_chip 0x0000 activated
+  rom 0x04000 0x047ff -> eeprom_chip 0x000 activated
+  rom 0x04800 0x04fff -> option_chip 0x000 activated
+  rom 0x05000 0x057ff -> io_chip 0x000 activated
+  rom 0x06000 0x067ff -> boot_chip 0x000 activated
+  rom 0x07f00 0x07fff -> cpu_chip 0x00 activated
+  rom 0x08000 0x27fff -> flash_chip 0x00000 activated
+  ports 0x0 0x3 -> ports_chip 0x0 activated
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/config/baseline/L052C sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/config/baseline/L052C
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/config/baseline/L052C	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/config/baseline/L052C	2022-02-08 21:21:05.000000000 +0000
@@ -0,0 +1,56 @@
+uCsim, Copyright (C)  Daniel Drotos.
+uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+This is free software, and you are welcome to redistribute it
+under certain conditions; type `show c' for details.
+Type of microcontroller: STM8 AL,L 052C6
+Controller has 20 hardware element(s).
+   on cpu[0]
+   on simif[0]
+  off vcd[0]
+   on dreg[0]
+   on dport[0]
+   on clk[0]
+   on uart[1]
+   on itc[0]
+   on pa[0]
+   on pb[0]
+   on pc[0]
+   on pd[0]
+   on pe[0]
+   on pf[0]
+   on rst[0]
+   on tim2[2]
+   on tim3[3]
+   on tim4[4]
+   on tim1[1]
+   on flash[0]
+V-IHINZC  Flags= 0x28  40 (  A= 0x00   0 .
+0-101000  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17ff [SP+1]= 00   0 .  Limit= 0x1500
+0x08000  ? 00 00          neg    (0x00,SP)[0K
+Memory chips:
+  0x000000-0x0000ff      256 variable_storage (32,%08x,0x%02lx)
+  0x000000-0x0017ff     6144 ram_chip (8,%02x,0x%04lx)
+  0x000000-0x0007ff     2048 eeprom_chip (8,%02x,0x%03lx)
+  0x000000-0x0007ff     2048 option_chip (8,%02x,0x%03lx)
+  0x000000-0x0007ff     2048 io_chip (8,%02x,0x%03lx)
+  0x000000-0x0007ff     2048 boot_chip (8,%02x,0x%03lx)
+  0x000000-0x0000ff      256 cpu_chip (8,%02x,0x%02lx)
+  0x000000-0x01ffff   131072 flash_chip (8,%02x,0x%05lx)
+  0x000000-0x000005        6 ports_chip (8,%02x,0x%01lx)
+Address spaces:
+  0x000000-0x0000ff      256 variables (32,%08x,0x%02lx)
+  0x000000-0x027fff   163840 rom (8,%02x,0x%05lx)
+  0x000000-0x000001        2 regs8 (8,%02x,0x%01lx)
+  0x000000-0x000002        3 regs16 (16,%04x,0x%01lx)
+  0x000000-0x000005        6 ports (8,%02x,0x%01lx)
+Address decoders:
+  variables 0x00 0xff -> variable_storage 0x00 activated
+  rom 0x00000 0x017ff -> ram_chip 0x0000 activated
+  rom 0x04000 0x047ff -> eeprom_chip 0x000 activated
+  rom 0x04800 0x04fff -> option_chip 0x000 activated
+  rom 0x05000 0x057ff -> io_chip 0x000 activated
+  rom 0x06000 0x067ff -> boot_chip 0x000 activated
+  rom 0x07f00 0x07fff -> cpu_chip 0x00 activated
+  rom 0x08000 0x27fff -> flash_chip 0x00000 activated
+  ports 0x0 0x5 -> ports_chip 0x0 activated
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/config/baseline/L052R sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/config/baseline/L052R
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/config/baseline/L052R	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/config/baseline/L052R	2022-02-08 21:21:05.000000000 +0000
@@ -0,0 +1,60 @@
+uCsim, Copyright (C)  Daniel Drotos.
+uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+This is free software, and you are welcome to redistribute it
+under certain conditions; type `show c' for details.
+Type of microcontroller: STM8 AL,L 052R8
+Controller has 24 hardware element(s).
+   on cpu[0]
+   on simif[0]
+  off vcd[0]
+   on dreg[0]
+   on dport[0]
+   on clk[0]
+   on uart[1]
+   on uart[2]
+   on uart[3]
+   on itc[0]
+   on pa[0]
+   on pb[0]
+   on pc[0]
+   on pd[0]
+   on pe[0]
+   on pf[0]
+   on pg[0]
+   on rst[0]
+   on tim2[2]
+   on tim3[3]
+   on tim4[4]
+   on tim1[1]
+   on tim5[5]
+   on flash[0]
+V-IHINZC  Flags= 0x28  40 (  A= 0x00   0 .
+0-101000  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17ff [SP+1]= 00   0 .  Limit= 0x1500
+0x08000  ? 00 00          neg    (0x00,SP)[0K
+Memory chips:
+  0x000000-0x0000ff      256 variable_storage (32,%08x,0x%02lx)
+  0x000000-0x0017ff     6144 ram_chip (8,%02x,0x%04lx)
+  0x000000-0x0007ff     2048 eeprom_chip (8,%02x,0x%03lx)
+  0x000000-0x0007ff     2048 option_chip (8,%02x,0x%03lx)
+  0x000000-0x0007ff     2048 io_chip (8,%02x,0x%03lx)
+  0x000000-0x0007ff     2048 boot_chip (8,%02x,0x%03lx)
+  0x000000-0x0000ff      256 cpu_chip (8,%02x,0x%02lx)
+  0x000000-0x01ffff   131072 flash_chip (8,%02x,0x%05lx)
+  0x000000-0x000006        7 ports_chip (8,%02x,0x%01lx)
+Address spaces:
+  0x000000-0x0000ff      256 variables (32,%08x,0x%02lx)
+  0x000000-0x027fff   163840 rom (8,%02x,0x%05lx)
+  0x000000-0x000001        2 regs8 (8,%02x,0x%01lx)
+  0x000000-0x000002        3 regs16 (16,%04x,0x%01lx)
+  0x000000-0x000006        7 ports (8,%02x,0x%01lx)
+Address decoders:
+  variables 0x00 0xff -> variable_storage 0x00 activated
+  rom 0x00000 0x017ff -> ram_chip 0x0000 activated
+  rom 0x04000 0x047ff -> eeprom_chip 0x000 activated
+  rom 0x04800 0x04fff -> option_chip 0x000 activated
+  rom 0x05000 0x057ff -> io_chip 0x000 activated
+  rom 0x06000 0x067ff -> boot_chip 0x000 activated
+  rom 0x07f00 0x07fff -> cpu_chip 0x00 activated
+  rom 0x08000 0x27fff -> flash_chip 0x00000 activated
+  ports 0x0 0x6 -> ports_chip 0x0 activated
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/config/baseline/L101 sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/config/baseline/L101
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/config/baseline/L101	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/config/baseline/L101	2022-02-08 21:21:05.000000000 +0000
@@ -0,0 +1,54 @@
+uCsim, Copyright (C)  Daniel Drotos.
+uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+This is free software, and you are welcome to redistribute it
+under certain conditions; type `show c' for details.
+Type of microcontroller: STM8 L101 L101xx
+Controller has 18 hardware element(s).
+   on cpu[0]
+   on simif[0]
+  off vcd[0]
+   on dreg[0]
+   on dport[0]
+   on clk[0]
+   on uart[1]
+   on itc[0]
+   on pa[0]
+   on pb[0]
+   on pc[0]
+   on pd[0]
+   on rst[0]
+   on tim2[2]
+   on tim2[2]
+   on tim4[4]
+   on uid[0]
+   on flash[0]
+V-IHINZC  Flags= 0x28  40 (  A= 0x00   0 .
+0-101000  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17ff [SP+1]= 00   0 .  Limit= 0x1500
+0x08000  ? 00 00          neg    (0x00,SP)[0K
+Memory chips:
+  0x000000-0x0000ff      256 variable_storage (32,%08x,0x%02lx)
+  0x000000-0x0017ff     6144 ram_chip (8,%02x,0x%04lx)
+  0x000000-0x0007ff     2048 eeprom_chip (8,%02x,0x%03lx)
+  0x000000-0x0007ff     2048 option_chip (8,%02x,0x%03lx)
+  0x000000-0x0007ff     2048 io_chip (8,%02x,0x%03lx)
+  0x000000-0x0007ff     2048 boot_chip (8,%02x,0x%03lx)
+  0x000000-0x0000ff      256 cpu_chip (8,%02x,0x%02lx)
+  0x000000-0x01ffff   131072 flash_chip (8,%02x,0x%05lx)
+  0x000000-0x000003        4 ports_chip (8,%02x,0x%01lx)
+Address spaces:
+  0x000000-0x0000ff      256 variables (32,%08x,0x%02lx)
+  0x000000-0x027fff   163840 rom (8,%02x,0x%05lx)
+  0x000000-0x000001        2 regs8 (8,%02x,0x%01lx)
+  0x000000-0x000002        3 regs16 (16,%04x,0x%01lx)
+  0x000000-0x000003        4 ports (8,%02x,0x%01lx)
+Address decoders:
+  variables 0x00 0xff -> variable_storage 0x00 activated
+  rom 0x00000 0x017ff -> ram_chip 0x0000 activated
+  rom 0x04000 0x047ff -> eeprom_chip 0x000 activated
+  rom 0x04800 0x04fff -> option_chip 0x000 activated
+  rom 0x05000 0x057ff -> io_chip 0x000 activated
+  rom 0x06000 0x067ff -> boot_chip 0x000 activated
+  rom 0x07f00 0x07fff -> cpu_chip 0x00 activated
+  rom 0x08000 0x27fff -> flash_chip 0x00000 activated
+  ports 0x0 0x3 -> ports_chip 0x0 activated
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/config/baseline/L151x23 sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/config/baseline/L151x23
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/config/baseline/L151x23	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/config/baseline/L151x23	2022-02-08 21:21:05.000000000 +0000
@@ -0,0 +1,56 @@
+uCsim, Copyright (C)  Daniel Drotos.
+uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+This is free software, and you are welcome to redistribute it
+under certain conditions; type `show c' for details.
+Type of microcontroller: STM8 AL,L 151[CKGF][23]
+Controller has 20 hardware element(s).
+   on cpu[0]
+   on simif[0]
+  off vcd[0]
+   on dreg[0]
+   on dport[0]
+   on clk[0]
+   on uart[1]
+   on itc[0]
+   on pa[0]
+   on pb[0]
+   on pc[0]
+   on pd[0]
+   on pe[0]
+   on pf[0]
+   on rst[0]
+   on tim2[2]
+   on tim3[3]
+   on tim4[4]
+   on uid[0]
+   on flash[0]
+V-IHINZC  Flags= 0x28  40 (  A= 0x00   0 .
+0-101000  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17ff [SP+1]= 00   0 .  Limit= 0x1500
+0x08000  ? 00 00          neg    (0x00,SP)[0K
+Memory chips:
+  0x000000-0x0000ff      256 variable_storage (32,%08x,0x%02lx)
+  0x000000-0x0017ff     6144 ram_chip (8,%02x,0x%04lx)
+  0x000000-0x0007ff     2048 eeprom_chip (8,%02x,0x%03lx)
+  0x000000-0x0007ff     2048 option_chip (8,%02x,0x%03lx)
+  0x000000-0x0007ff     2048 io_chip (8,%02x,0x%03lx)
+  0x000000-0x0007ff     2048 boot_chip (8,%02x,0x%03lx)
+  0x000000-0x0000ff      256 cpu_chip (8,%02x,0x%02lx)
+  0x000000-0x01ffff   131072 flash_chip (8,%02x,0x%05lx)
+  0x000000-0x000005        6 ports_chip (8,%02x,0x%01lx)
+Address spaces:
+  0x000000-0x0000ff      256 variables (32,%08x,0x%02lx)
+  0x000000-0x027fff   163840 rom (8,%02x,0x%05lx)
+  0x000000-0x000001        2 regs8 (8,%02x,0x%01lx)
+  0x000000-0x000002        3 regs16 (16,%04x,0x%01lx)
+  0x000000-0x000005        6 ports (8,%02x,0x%01lx)
+Address decoders:
+  variables 0x00 0xff -> variable_storage 0x00 activated
+  rom 0x00000 0x017ff -> ram_chip 0x0000 activated
+  rom 0x04000 0x047ff -> eeprom_chip 0x000 activated
+  rom 0x04800 0x04fff -> option_chip 0x000 activated
+  rom 0x05000 0x057ff -> io_chip 0x000 activated
+  rom 0x06000 0x067ff -> boot_chip 0x000 activated
+  rom 0x07f00 0x07fff -> cpu_chip 0x00 activated
+  rom 0x08000 0x27fff -> flash_chip 0x00000 activated
+  ports 0x0 0x5 -> ports_chip 0x0 activated
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/config/baseline/L15x46 sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/config/baseline/L15x46
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/config/baseline/L15x46	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/config/baseline/L15x46	2022-02-08 21:21:05.000000000 +0000
@@ -0,0 +1,57 @@
+uCsim, Copyright (C)  Daniel Drotos.
+uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+This is free software, and you are welcome to redistribute it
+under certain conditions; type `show c' for details.
+Type of microcontroller: STM8 AL,L 151x[46], 152x[46]
+Controller has 21 hardware element(s).
+   on cpu[0]
+   on simif[0]
+  off vcd[0]
+   on dreg[0]
+   on dport[0]
+   on clk[0]
+   on uart[1]
+   on itc[0]
+   on pa[0]
+   on pb[0]
+   on pc[0]
+   on pd[0]
+   on pe[0]
+   on pf[0]
+   on rst[0]
+   on tim2[2]
+   on tim3[3]
+   on tim4[4]
+   on tim1[1]
+   on uid[0]
+   on flash[0]
+V-IHINZC  Flags= 0x28  40 (  A= 0x00   0 .
+0-101000  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17ff [SP+1]= 00   0 .  Limit= 0x1500
+0x08000  ? 00 00          neg    (0x00,SP)[0K
+Memory chips:
+  0x000000-0x0000ff      256 variable_storage (32,%08x,0x%02lx)
+  0x000000-0x0017ff     6144 ram_chip (8,%02x,0x%04lx)
+  0x000000-0x0007ff     2048 eeprom_chip (8,%02x,0x%03lx)
+  0x000000-0x0007ff     2048 option_chip (8,%02x,0x%03lx)
+  0x000000-0x0007ff     2048 io_chip (8,%02x,0x%03lx)
+  0x000000-0x0007ff     2048 boot_chip_l15x46 (8,%02x,0x%03lx)
+  0x000000-0x0000ff      256 cpu_chip (8,%02x,0x%02lx)
+  0x000000-0x01ffff   131072 flash_chip (8,%02x,0x%05lx)
+  0x000000-0x000005        6 ports_chip (8,%02x,0x%01lx)
+Address spaces:
+  0x000000-0x0000ff      256 variables (32,%08x,0x%02lx)
+  0x000000-0x027fff   163840 rom (8,%02x,0x%05lx)
+  0x000000-0x000001        2 regs8 (8,%02x,0x%01lx)
+  0x000000-0x000002        3 regs16 (16,%04x,0x%01lx)
+  0x000000-0x000005        6 ports (8,%02x,0x%01lx)
+Address decoders:
+  variables 0x00 0xff -> variable_storage 0x00 activated
+  rom 0x00000 0x017ff -> ram_chip 0x0000 activated
+  rom 0x04000 0x047ff -> eeprom_chip 0x000 activated
+  rom 0x04800 0x04fff -> option_chip 0x000 activated
+  rom 0x05000 0x057ff -> io_chip 0x000 activated
+  rom 0x06000 0x067ff -> boot_chip_l15x46 0x000 activated
+  rom 0x07f00 0x07fff -> cpu_chip 0x00 activated
+  rom 0x08000 0x27fff -> flash_chip 0x00000 activated
+  ports 0x0 0x5 -> ports_chip 0x0 activated
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/config/baseline/L15x8 sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/config/baseline/L15x8
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/config/baseline/L15x8	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/config/baseline/L15x8	2022-02-08 21:21:05.000000000 +0000
@@ -0,0 +1,63 @@
+uCsim, Copyright (C)  Daniel Drotos.
+uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+This is free software, and you are welcome to redistribute it
+under certain conditions; type `show c' for details.
+Type of microcontroller: STM8 AL,L 151x[68], 152x[68]
+Controller has 27 hardware element(s).
+   on cpu[0]
+   on simif[0]
+  off vcd[0]
+   on dreg[0]
+   on dport[0]
+   on clk[0]
+   on uart[1]
+   on uart[2]
+   on uart[3]
+   on itc[0]
+   on pa[0]
+   on pb[0]
+   on pc[0]
+   on pd[0]
+   on pe[0]
+   on pf[0]
+   on pg[0]
+   on ph[0]
+   on pi[0]
+  off rst[0]
+   on tim2[2]
+   on tim3[3]
+   on tim4[4]
+   on tim1[1]
+   on tim5[5]
+   on uid[0]
+   on flash[0]
+V-IHINZC  Flags= 0x28  40 (  A= 0x00   0 .
+0-101000  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17ff [SP+1]= 00   0 .  Limit= 0x1500
+0x08000  ? 00 00          neg    (0x00,SP)[0K
+Memory chips:
+  0x000000-0x0000ff      256 variable_storage (32,%08x,0x%02lx)
+  0x000000-0x0017ff     6144 ram_chip (8,%02x,0x%04lx)
+  0x000000-0x0007ff     2048 eeprom_chip (8,%02x,0x%03lx)
+  0x000000-0x0007ff     2048 option_chip (8,%02x,0x%03lx)
+  0x000000-0x0007ff     2048 io_chip (8,%02x,0x%03lx)
+  0x000000-0x0007ff     2048 boot_chip (8,%02x,0x%03lx)
+  0x000000-0x0000ff      256 cpu_chip (8,%02x,0x%02lx)
+  0x000000-0x01ffff   131072 flash_chip (8,%02x,0x%05lx)
+  0x000000-0x000008        9 ports_chip (8,%02x,0x%01lx)
+Address spaces:
+  0x000000-0x0000ff      256 variables (32,%08x,0x%02lx)
+  0x000000-0x027fff   163840 rom (8,%02x,0x%05lx)
+  0x000000-0x000001        2 regs8 (8,%02x,0x%01lx)
+  0x000000-0x000002        3 regs16 (16,%04x,0x%01lx)
+  0x000000-0x000008        9 ports (8,%02x,0x%01lx)
+Address decoders:
+  variables 0x00 0xff -> variable_storage 0x00 activated
+  rom 0x00000 0x017ff -> ram_chip 0x0000 activated
+  rom 0x04000 0x047ff -> eeprom_chip 0x000 activated
+  rom 0x04800 0x04fff -> option_chip 0x000 activated
+  rom 0x05000 0x057ff -> io_chip 0x000 activated
+  rom 0x06000 0x067ff -> boot_chip 0x000 activated
+  rom 0x07f00 0x07fff -> cpu_chip 0x00 activated
+  rom 0x08000 0x27fff -> flash_chip 0x00000 activated
+  ports 0x0 0x8 -> ports_chip 0x0 activated
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/config/baseline/S sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/config/baseline/S
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/config/baseline/S	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/config/baseline/S	2022-02-08 21:21:05.000000000 +0000
@@ -0,0 +1,60 @@
+uCsim, Copyright (C)  Daniel Drotos.
+uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+This is free software, and you are welcome to redistribute it
+under certain conditions; type `show c' for details.
+Type of microcontroller: STM8 S,AF 208
+Controller has 24 hardware element(s).
+   on cpu[0]
+   on simif[0]
+  off vcd[0]
+   on dreg[0]
+   on dport[0]
+   on clk[0]
+   on uart[1]
+   on uart[3]
+   on itc[0]
+   on pa[0]
+   on pb[0]
+   on pc[0]
+   on pd[0]
+   on pe[0]
+   on pf[0]
+   on pg[0]
+   on ph[0]
+   on pi[0]
+   on rst[0]
+   on tim1[1]
+   on tim2[2]
+   on tim3[3]
+   on tim4[4]
+   on flash[0]
+V-IHINZC  Flags= 0x28  40 (  A= 0x00   0 .
+0-101000  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17ff [SP+1]= 00   0 .  Limit= 0x1500
+0x08000  ? 00 00          neg    (0x00,SP)[0K
+Memory chips:
+  0x000000-0x0000ff      256 variable_storage (32,%08x,0x%02lx)
+  0x000000-0x0017ff     6144 ram_chip (8,%02x,0x%04lx)
+  0x000000-0x0007ff     2048 eeprom_chip (8,%02x,0x%03lx)
+  0x000000-0x0007ff     2048 option_chip (8,%02x,0x%03lx)
+  0x000000-0x0007ff     2048 io_chip (8,%02x,0x%03lx)
+  0x000000-0x0007ff     2048 boot_chip (8,%02x,0x%03lx)
+  0x000000-0x0000ff      256 cpu_chip (8,%02x,0x%02lx)
+  0x000000-0x01ffff   131072 flash_chip (8,%02x,0x%05lx)
+  0x000000-0x000004        5 ports_chip (8,%02x,0x%01lx)
+Address spaces:
+  0x000000-0x0000ff      256 variables (32,%08x,0x%02lx)
+  0x000000-0x027fff   163840 rom (8,%02x,0x%05lx)
+  0x000000-0x000001        2 regs8 (8,%02x,0x%01lx)
+  0x000000-0x000002        3 regs16 (16,%04x,0x%01lx)
+  0x000000-0x000004        5 ports (8,%02x,0x%01lx)
+Address decoders:
+  variables 0x00 0xff -> variable_storage 0x00 activated
+  rom 0x00000 0x017ff -> ram_chip 0x0000 activated
+  rom 0x04000 0x047ff -> eeprom_chip 0x000 activated
+  rom 0x04800 0x04fff -> option_chip 0x000 activated
+  rom 0x05000 0x057ff -> io_chip 0x000 activated
+  rom 0x06000 0x067ff -> boot_chip 0x000 activated
+  rom 0x07f00 0x07fff -> cpu_chip 0x00 activated
+  rom 0x08000 0x27fff -> flash_chip 0x00000 activated
+  ports 0x0 0x4 -> ports_chip 0x0 activated
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/config/baseline/S003 sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/config/baseline/S003
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/config/baseline/S003	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/config/baseline/S003	2022-02-08 21:21:05.000000000 +0000
@@ -0,0 +1,55 @@
+uCsim, Copyright (C)  Daniel Drotos.
+uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+This is free software, and you are welcome to redistribute it
+under certain conditions; type `show c' for details.
+Type of microcontroller: STM8 S,AF 003
+Controller has 19 hardware element(s).
+   on cpu[0]
+   on simif[0]
+  off vcd[0]
+   on dreg[0]
+   on dport[0]
+   on clk[0]
+   on uart[1]
+   on itc[0]
+   on pa[0]
+   on pb[0]
+   on pc[0]
+   on pd[0]
+   on pe[0]
+   on pf[0]
+   on rst[0]
+   on tim1[1]
+   on tim2[2]
+   on tim4[4]
+   on flash[0]
+V-IHINZC  Flags= 0x28  40 (  A= 0x00   0 .
+0-101000  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17ff [SP+1]= 00   0 .  Limit= 0x1500
+0x08000  ? 00 00          neg    (0x00,SP)[0K
+Memory chips:
+  0x000000-0x0000ff      256 variable_storage (32,%08x,0x%02lx)
+  0x000000-0x0017ff     6144 ram_chip (8,%02x,0x%04lx)
+  0x000000-0x0007ff     2048 eeprom_chip (8,%02x,0x%03lx)
+  0x000000-0x0007ff     2048 option_chip (8,%02x,0x%03lx)
+  0x000000-0x0007ff     2048 io_chip (8,%02x,0x%03lx)
+  0x000000-0x0007ff     2048 boot_chip (8,%02x,0x%03lx)
+  0x000000-0x0000ff      256 cpu_chip (8,%02x,0x%02lx)
+  0x000000-0x01ffff   131072 flash_chip (8,%02x,0x%05lx)
+  0x000000-0x000003        4 ports_chip (8,%02x,0x%01lx)
+Address spaces:
+  0x000000-0x0000ff      256 variables (32,%08x,0x%02lx)
+  0x000000-0x027fff   163840 rom (8,%02x,0x%05lx)
+  0x000000-0x000001        2 regs8 (8,%02x,0x%01lx)
+  0x000000-0x000002        3 regs16 (16,%04x,0x%01lx)
+  0x000000-0x000003        4 ports (8,%02x,0x%01lx)
+Address decoders:
+  variables 0x00 0xff -> variable_storage 0x00 activated
+  rom 0x00000 0x017ff -> ram_chip 0x0000 activated
+  rom 0x04000 0x047ff -> eeprom_chip 0x000 activated
+  rom 0x04800 0x04fff -> option_chip 0x000 activated
+  rom 0x05000 0x057ff -> io_chip 0x000 activated
+  rom 0x06000 0x067ff -> boot_chip 0x000 activated
+  rom 0x07f00 0x07fff -> cpu_chip 0x00 activated
+  rom 0x08000 0x27fff -> flash_chip 0x00000 activated
+  ports 0x0 0x3 -> ports_chip 0x0 activated
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/config/baseline/S005 sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/config/baseline/S005
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/config/baseline/S005	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/config/baseline/S005	2022-02-08 21:21:05.000000000 +0000
@@ -0,0 +1,59 @@
+uCsim, Copyright (C)  Daniel Drotos.
+uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+This is free software, and you are welcome to redistribute it
+under certain conditions; type `show c' for details.
+Type of microcontroller: STM8 S,AF 005
+Controller has 23 hardware element(s).
+   on cpu[0]
+   on simif[0]
+  off vcd[0]
+   on dreg[0]
+   on dport[0]
+   on clk[0]
+   on uart[2]
+   on itc[0]
+   on pa[0]
+   on pb[0]
+   on pc[0]
+   on pd[0]
+   on pe[0]
+   on pf[0]
+   on pg[0]
+   on ph[0]
+   on pi[0]
+   on rst[0]
+   on tim1[1]
+   on tim2[2]
+   on tim3[3]
+   on tim4[4]
+   on flash[0]
+V-IHINZC  Flags= 0x28  40 (  A= 0x00   0 .
+0-101000  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17ff [SP+1]= 00   0 .  Limit= 0x1500
+0x08000  ? 00 00          neg    (0x00,SP)[0K
+Memory chips:
+  0x000000-0x0000ff      256 variable_storage (32,%08x,0x%02lx)
+  0x000000-0x0017ff     6144 ram_chip (8,%02x,0x%04lx)
+  0x000000-0x0007ff     2048 eeprom_chip (8,%02x,0x%03lx)
+  0x000000-0x0007ff     2048 option_chip (8,%02x,0x%03lx)
+  0x000000-0x0007ff     2048 io_chip (8,%02x,0x%03lx)
+  0x000000-0x0007ff     2048 boot_chip (8,%02x,0x%03lx)
+  0x000000-0x0000ff      256 cpu_chip (8,%02x,0x%02lx)
+  0x000000-0x01ffff   131072 flash_chip (8,%02x,0x%05lx)
+  0x000000-0x000004        5 ports_chip (8,%02x,0x%01lx)
+Address spaces:
+  0x000000-0x0000ff      256 variables (32,%08x,0x%02lx)
+  0x000000-0x027fff   163840 rom (8,%02x,0x%05lx)
+  0x000000-0x000001        2 regs8 (8,%02x,0x%01lx)
+  0x000000-0x000002        3 regs16 (16,%04x,0x%01lx)
+  0x000000-0x000004        5 ports (8,%02x,0x%01lx)
+Address decoders:
+  variables 0x00 0xff -> variable_storage 0x00 activated
+  rom 0x00000 0x017ff -> ram_chip 0x0000 activated
+  rom 0x04000 0x047ff -> eeprom_chip 0x000 activated
+  rom 0x04800 0x04fff -> option_chip 0x000 activated
+  rom 0x05000 0x057ff -> io_chip 0x000 activated
+  rom 0x06000 0x067ff -> boot_chip 0x000 activated
+  rom 0x07f00 0x07fff -> cpu_chip 0x00 activated
+  rom 0x08000 0x27fff -> flash_chip 0x00000 activated
+  ports 0x0 0x4 -> ports_chip 0x0 activated
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/config/baseline/S007 sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/config/baseline/S007
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/config/baseline/S007	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/config/baseline/S007	2022-02-08 21:21:05.000000000 +0000
@@ -0,0 +1,60 @@
+uCsim, Copyright (C)  Daniel Drotos.
+uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+This is free software, and you are welcome to redistribute it
+under certain conditions; type `show c' for details.
+Type of microcontroller: STM8 S,AF 007
+Controller has 24 hardware element(s).
+   on cpu[0]
+   on simif[0]
+  off vcd[0]
+   on dreg[0]
+   on dport[0]
+   on clk[0]
+   on uart[1]
+   on uart[3]
+   on itc[0]
+   on pa[0]
+   on pb[0]
+   on pc[0]
+   on pd[0]
+   on pe[0]
+   on pf[0]
+   on pg[0]
+   on ph[0]
+   on pi[0]
+   on rst[0]
+   on tim1[1]
+   on tim2[2]
+   on tim3[3]
+   on tim4[4]
+   on flash[0]
+V-IHINZC  Flags= 0x28  40 (  A= 0x00   0 .
+0-101000  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17ff [SP+1]= 00   0 .  Limit= 0x1500
+0x08000  ? 00 00          neg    (0x00,SP)[0K
+Memory chips:
+  0x000000-0x0000ff      256 variable_storage (32,%08x,0x%02lx)
+  0x000000-0x0017ff     6144 ram_chip (8,%02x,0x%04lx)
+  0x000000-0x0007ff     2048 eeprom_chip (8,%02x,0x%03lx)
+  0x000000-0x0007ff     2048 option_chip (8,%02x,0x%03lx)
+  0x000000-0x0007ff     2048 io_chip (8,%02x,0x%03lx)
+  0x000000-0x0007ff     2048 boot_chip (8,%02x,0x%03lx)
+  0x000000-0x0000ff      256 cpu_chip (8,%02x,0x%02lx)
+  0x000000-0x01ffff   131072 flash_chip (8,%02x,0x%05lx)
+  0x000000-0x000004        5 ports_chip (8,%02x,0x%01lx)
+Address spaces:
+  0x000000-0x0000ff      256 variables (32,%08x,0x%02lx)
+  0x000000-0x027fff   163840 rom (8,%02x,0x%05lx)
+  0x000000-0x000001        2 regs8 (8,%02x,0x%01lx)
+  0x000000-0x000002        3 regs16 (16,%04x,0x%01lx)
+  0x000000-0x000004        5 ports (8,%02x,0x%01lx)
+Address decoders:
+  variables 0x00 0xff -> variable_storage 0x00 activated
+  rom 0x00000 0x017ff -> ram_chip 0x0000 activated
+  rom 0x04000 0x047ff -> eeprom_chip 0x000 activated
+  rom 0x04800 0x04fff -> option_chip 0x000 activated
+  rom 0x05000 0x057ff -> io_chip 0x000 activated
+  rom 0x06000 0x067ff -> boot_chip 0x000 activated
+  rom 0x07f00 0x07fff -> cpu_chip 0x00 activated
+  rom 0x08000 0x27fff -> flash_chip 0x00000 activated
+  ports 0x0 0x4 -> ports_chip 0x0 activated
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/config/baseline/S103 sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/config/baseline/S103
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/config/baseline/S103	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/config/baseline/S103	2022-02-08 21:21:05.000000000 +0000
@@ -0,0 +1,56 @@
+uCsim, Copyright (C)  Daniel Drotos.
+uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+This is free software, and you are welcome to redistribute it
+under certain conditions; type `show c' for details.
+Type of microcontroller: STM8 S,AF 103
+Controller has 20 hardware element(s).
+   on cpu[0]
+   on simif[0]
+  off vcd[0]
+   on dreg[0]
+   on dport[0]
+   on clk[0]
+   on uart[1]
+   on itc[0]
+   on pa[0]
+   on pb[0]
+   on pc[0]
+   on pd[0]
+   on pe[0]
+   on pf[0]
+   on rst[0]
+   on tim1[1]
+   on tim2[2]
+   on tim4[4]
+   on uid[0]
+   on flash[0]
+V-IHINZC  Flags= 0x28  40 (  A= 0x00   0 .
+0-101000  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17ff [SP+1]= 00   0 .  Limit= 0x1500
+0x08000  ? 00 00          neg    (0x00,SP)[0K
+Memory chips:
+  0x000000-0x0000ff      256 variable_storage (32,%08x,0x%02lx)
+  0x000000-0x0017ff     6144 ram_chip (8,%02x,0x%04lx)
+  0x000000-0x0007ff     2048 eeprom_chip (8,%02x,0x%03lx)
+  0x000000-0x0007ff     2048 option_chip (8,%02x,0x%03lx)
+  0x000000-0x0007ff     2048 io_chip (8,%02x,0x%03lx)
+  0x000000-0x0007ff     2048 boot_chip (8,%02x,0x%03lx)
+  0x000000-0x0000ff      256 cpu_chip (8,%02x,0x%02lx)
+  0x000000-0x01ffff   131072 flash_chip (8,%02x,0x%05lx)
+  0x000000-0x000003        4 ports_chip (8,%02x,0x%01lx)
+Address spaces:
+  0x000000-0x0000ff      256 variables (32,%08x,0x%02lx)
+  0x000000-0x027fff   163840 rom (8,%02x,0x%05lx)
+  0x000000-0x000001        2 regs8 (8,%02x,0x%01lx)
+  0x000000-0x000002        3 regs16 (16,%04x,0x%01lx)
+  0x000000-0x000003        4 ports (8,%02x,0x%01lx)
+Address decoders:
+  variables 0x00 0xff -> variable_storage 0x00 activated
+  rom 0x00000 0x017ff -> ram_chip 0x0000 activated
+  rom 0x04000 0x047ff -> eeprom_chip 0x000 activated
+  rom 0x04800 0x04fff -> option_chip 0x000 activated
+  rom 0x05000 0x057ff -> io_chip 0x000 activated
+  rom 0x06000 0x067ff -> boot_chip 0x000 activated
+  rom 0x07f00 0x07fff -> cpu_chip 0x00 activated
+  rom 0x08000 0x27fff -> flash_chip 0x00000 activated
+  ports 0x0 0x3 -> ports_chip 0x0 activated
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/config/baseline/S105 sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/config/baseline/S105
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/config/baseline/S105	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/config/baseline/S105	2022-02-08 21:21:05.000000000 +0000
@@ -0,0 +1,59 @@
+uCsim, Copyright (C)  Daniel Drotos.
+uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+This is free software, and you are welcome to redistribute it
+under certain conditions; type `show c' for details.
+Type of microcontroller: STM8 S,AF 105
+Controller has 23 hardware element(s).
+   on cpu[0]
+   on simif[0]
+  off vcd[0]
+   on dreg[0]
+   on dport[0]
+   on clk[0]
+   on uart[2]
+   on itc[0]
+   on pa[0]
+   on pb[0]
+   on pc[0]
+   on pd[0]
+   on pe[0]
+   on pf[0]
+   on pg[0]
+   on ph[0]
+   on pi[0]
+   on rst[0]
+   on tim1[1]
+   on tim2[2]
+   on tim3[3]
+   on tim4[4]
+   on flash[0]
+V-IHINZC  Flags= 0x28  40 (  A= 0x00   0 .
+0-101000  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17ff [SP+1]= 00   0 .  Limit= 0x1500
+0x08000  ? 00 00          neg    (0x00,SP)[0K
+Memory chips:
+  0x000000-0x0000ff      256 variable_storage (32,%08x,0x%02lx)
+  0x000000-0x0017ff     6144 ram_chip (8,%02x,0x%04lx)
+  0x000000-0x0007ff     2048 eeprom_chip (8,%02x,0x%03lx)
+  0x000000-0x0007ff     2048 option_chip (8,%02x,0x%03lx)
+  0x000000-0x0007ff     2048 io_chip (8,%02x,0x%03lx)
+  0x000000-0x0007ff     2048 boot_chip_s105 (8,%02x,0x%03lx)
+  0x000000-0x0000ff      256 cpu_chip (8,%02x,0x%02lx)
+  0x000000-0x01ffff   131072 flash_chip (8,%02x,0x%05lx)
+  0x000000-0x000004        5 ports_chip (8,%02x,0x%01lx)
+Address spaces:
+  0x000000-0x0000ff      256 variables (32,%08x,0x%02lx)
+  0x000000-0x027fff   163840 rom (8,%02x,0x%05lx)
+  0x000000-0x000001        2 regs8 (8,%02x,0x%01lx)
+  0x000000-0x000002        3 regs16 (16,%04x,0x%01lx)
+  0x000000-0x000004        5 ports (8,%02x,0x%01lx)
+Address decoders:
+  variables 0x00 0xff -> variable_storage 0x00 activated
+  rom 0x00000 0x017ff -> ram_chip 0x0000 activated
+  rom 0x04000 0x047ff -> eeprom_chip 0x000 activated
+  rom 0x04800 0x04fff -> option_chip 0x000 activated
+  rom 0x05000 0x057ff -> io_chip 0x000 activated
+  rom 0x06000 0x067ff -> boot_chip_s105 0x000 activated
+  rom 0x07f00 0x07fff -> cpu_chip 0x00 activated
+  rom 0x08000 0x27fff -> flash_chip 0x00000 activated
+  ports 0x0 0x4 -> ports_chip 0x0 activated
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/config/baseline/S207 sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/config/baseline/S207
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/config/baseline/S207	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/config/baseline/S207	2022-02-08 21:21:05.000000000 +0000
@@ -0,0 +1,60 @@
+uCsim, Copyright (C)  Daniel Drotos.
+uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+This is free software, and you are welcome to redistribute it
+under certain conditions; type `show c' for details.
+Type of microcontroller: STM8 S,AF 207
+Controller has 24 hardware element(s).
+   on cpu[0]
+   on simif[0]
+  off vcd[0]
+   on dreg[0]
+   on dport[0]
+   on clk[0]
+   on uart[1]
+   on uart[3]
+   on itc[0]
+   on pa[0]
+   on pb[0]
+   on pc[0]
+   on pd[0]
+   on pe[0]
+   on pf[0]
+   on pg[0]
+   on ph[0]
+   on pi[0]
+   on rst[0]
+   on tim1[1]
+   on tim2[2]
+   on tim3[3]
+   on tim4[4]
+   on flash[0]
+V-IHINZC  Flags= 0x28  40 (  A= 0x00   0 .
+0-101000  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17ff [SP+1]= 00   0 .  Limit= 0x1500
+0x08000  ? 00 00          neg    (0x00,SP)[0K
+Memory chips:
+  0x000000-0x0000ff      256 variable_storage (32,%08x,0x%02lx)
+  0x000000-0x0017ff     6144 ram_chip (8,%02x,0x%04lx)
+  0x000000-0x0007ff     2048 eeprom_chip (8,%02x,0x%03lx)
+  0x000000-0x0007ff     2048 option_chip (8,%02x,0x%03lx)
+  0x000000-0x0007ff     2048 io_chip (8,%02x,0x%03lx)
+  0x000000-0x0007ff     2048 boot_chip (8,%02x,0x%03lx)
+  0x000000-0x0000ff      256 cpu_chip (8,%02x,0x%02lx)
+  0x000000-0x01ffff   131072 flash_chip (8,%02x,0x%05lx)
+  0x000000-0x000004        5 ports_chip (8,%02x,0x%01lx)
+Address spaces:
+  0x000000-0x0000ff      256 variables (32,%08x,0x%02lx)
+  0x000000-0x027fff   163840 rom (8,%02x,0x%05lx)
+  0x000000-0x000001        2 regs8 (8,%02x,0x%01lx)
+  0x000000-0x000002        3 regs16 (16,%04x,0x%01lx)
+  0x000000-0x000004        5 ports (8,%02x,0x%01lx)
+Address decoders:
+  variables 0x00 0xff -> variable_storage 0x00 activated
+  rom 0x00000 0x017ff -> ram_chip 0x0000 activated
+  rom 0x04000 0x047ff -> eeprom_chip 0x000 activated
+  rom 0x04800 0x04fff -> option_chip 0x000 activated
+  rom 0x05000 0x057ff -> io_chip 0x000 activated
+  rom 0x06000 0x067ff -> boot_chip 0x000 activated
+  rom 0x07f00 0x07fff -> cpu_chip 0x00 activated
+  rom 0x08000 0x27fff -> flash_chip 0x00000 activated
+  ports 0x0 0x4 -> ports_chip 0x0 activated
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/config/baseline/S903 sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/config/baseline/S903
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/config/baseline/S903	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/config/baseline/S903	2022-02-08 21:21:05.000000000 +0000
@@ -0,0 +1,56 @@
+uCsim, Copyright (C)  Daniel Drotos.
+uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+This is free software, and you are welcome to redistribute it
+under certain conditions; type `show c' for details.
+Type of microcontroller: STM8 S,AF 903
+Controller has 20 hardware element(s).
+   on cpu[0]
+   on simif[0]
+  off vcd[0]
+   on dreg[0]
+   on dport[0]
+   on clk[0]
+   on uart[1]
+   on itc[0]
+   on pa[0]
+   on pb[0]
+   on pc[0]
+   on pd[0]
+   on pe[0]
+   on pf[0]
+   on rst[0]
+   on tim1[1]
+   on tim5[5]
+   on tim6[6]
+   on uid[0]
+   on flash[0]
+V-IHINZC  Flags= 0x28  40 (  A= 0x00   0 .
+0-101000  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17ff [SP+1]= 00   0 .  Limit= 0x1500
+0x08000  ? 00 00          neg    (0x00,SP)[0K
+Memory chips:
+  0x000000-0x0000ff      256 variable_storage (32,%08x,0x%02lx)
+  0x000000-0x0017ff     6144 ram_chip (8,%02x,0x%04lx)
+  0x000000-0x0007ff     2048 eeprom_chip (8,%02x,0x%03lx)
+  0x000000-0x0007ff     2048 option_chip (8,%02x,0x%03lx)
+  0x000000-0x0007ff     2048 io_chip (8,%02x,0x%03lx)
+  0x000000-0x0007ff     2048 boot_chip (8,%02x,0x%03lx)
+  0x000000-0x0000ff      256 cpu_chip (8,%02x,0x%02lx)
+  0x000000-0x01ffff   131072 flash_chip (8,%02x,0x%05lx)
+  0x000000-0x000003        4 ports_chip (8,%02x,0x%01lx)
+Address spaces:
+  0x000000-0x0000ff      256 variables (32,%08x,0x%02lx)
+  0x000000-0x027fff   163840 rom (8,%02x,0x%05lx)
+  0x000000-0x000001        2 regs8 (8,%02x,0x%01lx)
+  0x000000-0x000002        3 regs16 (16,%04x,0x%01lx)
+  0x000000-0x000003        4 ports (8,%02x,0x%01lx)
+Address decoders:
+  variables 0x00 0xff -> variable_storage 0x00 activated
+  rom 0x00000 0x017ff -> ram_chip 0x0000 activated
+  rom 0x04000 0x047ff -> eeprom_chip 0x000 activated
+  rom 0x04800 0x04fff -> option_chip 0x000 activated
+  rom 0x05000 0x057ff -> io_chip 0x000 activated
+  rom 0x06000 0x067ff -> boot_chip 0x000 activated
+  rom 0x07f00 0x07fff -> cpu_chip 0x00 activated
+  rom 0x08000 0x27fff -> flash_chip 0x00000 activated
+  ports 0x0 0x3 -> ports_chip 0x0 activated
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/config/Makefile sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/config/Makefile
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/config/Makefile	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/config/Makefile	2021-03-21 12:01:19.000000000 +0000
@@ -0,0 +1,8 @@
+OUTPUTS = $(filter-out Parameter, $(shell $(SIM) -H | sort -u -k2b | cut -d' ' -f1))
+
+
+$(OUTPUTS):
+	$(call run-sim, -t $(@F) -e 'conf; info reg; info mem')
+
+
+include test-lib.mk
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/dl_ldisc.sh sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/dl_ldisc.sh
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/dl_ldisc.sh	2017-02-21 09:48:05.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/dl_ldisc.sh	1970-01-01 00:00:00.000000000 +0000
@@ -1,3 +0,0 @@
-#!/bin/bash
-
-stm8flash -c stlink -p stm8l152c6 -w ${1}
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/dl_sdic.sh sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/dl_sdic.sh
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/dl_sdic.sh	2017-02-03 18:14:56.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/dl_sdic.sh	1970-01-01 00:00:00.000000000 +0000
@@ -1,3 +0,0 @@
-#!/bin/bash
-
-stm8flash -c stlink -p stm8s105c6 -w ${1}
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/flash.c sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/flash.c
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/flash.c	2018-01-25 13:48:09.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/flash.c	1970-01-01 00:00:00.000000000 +0000
@@ -1,141 +0,0 @@
-/* */
-
-#include 
-
-#include "stm8.h"
-
-#include "flash.h"
-
-
-// Lock, unklock
-
-void
-flash_punlock(void)
-{
-  FLASH->pukr= 0x56;
-  FLASH->pukr= 0xae;
-}
-
-void
-flash_dunlock(void)
-{
-  FLASH->pukr= 0xae;
-  FLASH->pukr= 0x56;
-}
-
-void
-flash_plock(void)
-{
-  FLASH->iapsr&= ~0x02;
-}
-
-void
-flash_dlock(void)
-{
-  FLASH->iapsr&= ~0x08;
-}
-
-void
-flash_lock(void)
-{
-  FLASH->iapsr&= ~0x0a;
-}
-
-
-// Set programing mode
-
-void
-flash_byte_mode(void)
-{
-  FLASH->cr2= 0;
-#if (DEVICE & DEV_STM8SAF)
-  FLASH->ncr2= 0xff;
-#endif
-}
-
-void
-flash_word_mode(void)
-{
-  FLASH->cr2= 0x40;
-#if (DEVICE & DEV_STM8SAF)
-  FLASH->ncr2= 0xbf;
-#endif
-}
-
-void
-flash_erase_mode(void)
-{
-  FLASH->cr2= 0x20;
-#if (DEVICE & DEV_STM8SAF)
-  FLASH->ncr2= 0xdf;
-#endif
-}
-
-
-// Check the result
-
-uint8_t
-flash_wait_finish(void)
-{
-  unsigned long int timeout= 0xfffff;
-  //volatile
-  uint8_t r;
-
-  r= FLASH->iapsr;
-  while (((r & 0x05) == 0) &&
-	 (timeout != 0))
-    {
-      timeout--;
-      r= FLASH->iapsr;
-    }
-  if (r & 0x04)
-    return 0;
-  if (r & 0x01)
-    return 1;
-  if (timeout == 0)
-    return 2;
-  return 3;
-}
-
-uint8_t
-flash_erase_fn(volatile uint8_t *addr, volatile uint8_t *iapsr)
-{
-  volatile uint8_t r;
-  unsigned long timeout= 0xfffff;
-  flash_erase_mode();
-  *(addr++)= 0;
-  *(addr++)= 0;
-  *(addr++)= 0;
-  *(addr)= 0;
-  r= *iapsr;
-  while (((r & 0x05) == 0) &&
-	 (timeout != 0))
-    {
-      timeout--;
-      r= *iapsr;
-      GPIOD->odr^= 1;
-    }
-  if (r & 0x04)
-    return 0;
-  if (r & 0x01)
-    return 1;
-  if (timeout == 0)
-    return 2;
-  return 3;
-}
-
-uint8_t flash_op_in_ram[120];
-
-uint8_t
-flash_erase(volatile uint8_t *addr, volatile uint8_t *iapsr)
-{
-  uint8_t r;
-  typedef uint8_t (*ft)(volatile uint8_t *addr, volatile uint8_t *iapsr);
-  ft f= (ft)flash_op_in_ram;
-  memcpy(flash_op_in_ram, &flash_erase_fn, 119);
-  r= (*f)(addr, iapsr);
-  return r;
-}
-
-
-/* End of stm8.src/test/flash.c */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/flash.h sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/flash.h
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/flash.h	2018-01-25 13:48:09.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/flash.h	1970-01-01 00:00:00.000000000 +0000
@@ -1,23 +0,0 @@
-/* */
-
-#ifndef FLASH_HEADER
-#define FLASH_HEADER
-
-#include 
-
-extern void flash_punlock(void);
-extern void flash_dunlock(void);
-extern void flash_plock(void);
-extern void flash_dlock(void);
-extern void flash_lock(void);
-
-extern void flash_byte_mode(void);
-extern void flash_word_mode(void);
-extern void flash_erase_mode(void);
-
-extern uint8_t flash_wait_finish(void);
-extern uint8_t flash_erase(volatile uint8_t *addr, volatile uint8_t *iapsr);
-
-#endif
-
-/* End of stm8.src/test/flash.h */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/getbl.c sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/getbl.c
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/getbl.c	2018-12-18 08:22:48.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/getbl.c	1970-01-01 00:00:00.000000000 +0000
@@ -1,63 +0,0 @@
-// Source code under CC0 1.0
-#include 
-#include 
-
-#include "stm8.h"
-
-#include "serial.h"
-
-volatile unsigned char *sif= (unsigned char *)0x7fff;
-
-void
-print_bl()
-{
-  int a, l;
-  uint8_t *p= (uint8_t *)0x6000;
-  printf("%c\n", 2);
-  printf("$A%04x,\n", 0x6000);
-  for (a= 0, l= 0; a < 0x800; a++)
-    {
-      printf("%02x ", p[a]);
-      l++;
-      if ((l % 16) == 0)
-	{
-	  l= 0;
-	  printf("\n");
-	}
-    }
-  printf("%c\n", 3);
-}
-	 
-void main(void)
-{
-  unsigned long i = 0;
-  
-  CLK->ckdivr = 0x00; // Set the frequency to 16 MHz
-  CLK->pckenr1 = 0xFF; // Enable peripherals
-
-  USART->cr2 = USART_CR2_TEN | USART_CR2_REN; // Allow TX and RX
-  USART->cr3 &= ~(USART_CR3_STOP1 | USART_CR3_STOP2); // 1 stop bit
-  USART->brr2 = 0x03;
-  USART->brr1 = 0x68; // 9600 baud
-
-  USART->cr2|= USART_CR2_RIEN;
-  EI;
-
-  for(;;)
-    {
-      if (serial_received())
-	{
-	  char c= getchar();
-	  if (c == '=')
-	    {
-	      print_bl();
-	    }
-	  else if (c == '*')
-	    {
-	      printf("0x%04x\n", 0x6000);
-	    }
-	  else
-	    printf("%c", c);
-	}
-    }
-}
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/getbl.mk sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/getbl.mk
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/getbl.mk	2018-01-25 13:48:09.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/getbl.mk	1970-01-01 00:00:00.000000000 +0000
@@ -1,3 +0,0 @@
-DEVICES		= SDISC LDISC
-
-OTHERS		= serial
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/lled.c sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/lled.c
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/lled.c	2018-01-25 13:48:09.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/lled.c	1970-01-01 00:00:00.000000000 +0000
@@ -1,47 +0,0 @@
-// Source code under CC0 1.0
-#include 
-
-#include "stm8.h"
-
-#define PC GPIOC
-#define PE GPIOE
-
-unsigned int clock(void)
-{
-  unsigned char h, l;
-  h = TIM1->cntrh;
-  l = TIM1->cntrl;
-  return((unsigned int)(h) << 8 | l);
-}
-
-void main(void)
-{
-  CLK->ckdivr = 0x00; // Set the frequency to 16 MHz
-  CLK->pckenr2 |= 0x02; // Enable clock to timer
-
-  // Configure timer
-  // 1000 ticks per second
-  TIM1->pscrh = 0x3e;
-  TIM1->pscrl = 0x80;
-  // Enable timer
-  TIM1->cr1 = TIM_CR1_CEN;
-
-  // Configure pins
-  PE->ddr = 0x80;
-  PE->cr1 = 0x80;
-
-  PC->ddr = 0x80;
-  PC->cr1 = 0x80;
-
-  for(;;)
-    {
-      if (clock() % 1000 <= 500)
-	PE->odr |= 0x80;
-      else
-	PE->odr &= 0x7f;
-      if (clock() % 2000 <= 1000)
-	PC->odr |= 0x80;
-      else
-	PC->odr &= 0x7f;
-    }
-}
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/lled.mk sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/lled.mk
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/lled.mk	2018-01-25 13:48:09.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/lled.mk	1970-01-01 00:00:00.000000000 +0000
@@ -1 +0,0 @@
-DEVICES		= LDISC
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/ltim.c sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/ltim.c
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/ltim.c	2018-01-25 13:48:09.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/ltim.c	1970-01-01 00:00:00.000000000 +0000
@@ -1,84 +0,0 @@
-// Source code under CC0 1.0
-#include 
-
-#include "stm8.h"
-
-#define PC GPIOC
-#define PE GPIOE
-
-volatile unsigned long clk= 0;
-
-void tim1_up_isr(void) __interrupt(TIM1_UP_IRQ)
-{
-  TIM1->sr1&= ~TIM_SR1_UIF;
-  clk++;
-  //PE->odr^= 0x80;
-}
-
-unsigned long clock(void)
-{
-  unsigned long c;
-  TIM1->ier&= ~TIM_IER_UIE;
-  c= clk;
-  TIM1->ier|= TIM_IER_UIE;
-  return c;
-}
-
-unsigned long last_tick1= 0;
-
-void tick1(unsigned long c)
-{
-  //unsigned long c= clock();
-  if (c - last_tick1 > 500)
-    {
-      last_tick1= c;
-      PE->odr^= 0x80;
-    }
-}
-
-unsigned long last_tick2= 0;
-
-void tick2(unsigned long c)
-{
-  //unsigned long c= clock();
-  if (c - last_tick2 > 1000)
-    {
-      last_tick2= c;
-      PC->odr^= 0x80;
-    }
-}
-
-void main(void)
-{
-  CLK->ckdivr = 0x00; // Set the frequency to 16 MHz
-  CLK->pckenr2 |= 0x02; // Enable clock to timer
-
-  // Configure timer
-  // 16 MHz clock for timer
-  TIM1->pscrh = 0;//0x3e;
-  TIM1->pscrl = 0;//0x80;
-  // Update event at every 1 ms (16000 count)
-  #define AR 16000
-  TIM1->arrh = AR >> 8;
-  TIM1->arrl = AR & 0xff;
-  // Enable timer
-  TIM1->cr1 = TIM_CR1_CEN;
-
-  // Enable interrupt for timer1 update
-  TIM1->ier|= TIM_IER_UIE;
-  EI;
-  
-  // Configure pins
-  PE->ddr = 0x80;
-  PE->cr1 = 0x80;
-
-  PC->ddr = 0x80;
-  PC->cr1 = 0x80;
-
-  for(;;)
-    {
-      unsigned long c= clock();
-      tick1(c);
-      tick2(c);
-    }
-}
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/ltim.mk sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/ltim.mk
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/ltim.mk	2018-01-25 13:48:09.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/ltim.mk	1970-01-01 00:00:00.000000000 +0000
@@ -1 +0,0 @@
-DEVICES		= LDISC
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/Makefile sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/Makefile
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/Makefile	2018-12-05 12:13:25.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/Makefile	1970-01-01 00:00:00.000000000 +0000
@@ -1,18 +0,0 @@
-PROJECTS	= s0 s1 s2 s3 t1 t2 t3 t4 xtest \
-		  sl ss lled sled ltim stim sertest \
-		  getbl \
-		  monitor
-
-.PHONY: projects $(PROJECTS)
-
-projects: $(PROJECTS)
-
-$(PROJECTS):
-	$(MAKE) MAIN=$@ -f sdcc.mk
-
-clean:
-	for p in $(PROJECTS); do \
-		$(MAKE) MAIN=$$p -f sdcc.mk clean ;\
-		rm -rf $$p*.hex ;\
-		rm -rf $$p*.cdb ;\
-	done
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/Makefile.in sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/Makefile.in
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/Makefile.in	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/Makefile.in	2021-03-28 10:28:14.000000000 +0000
@@ -0,0 +1,29 @@
+# @configure_input@
+
+srcdir           = @abs_srcdir@
+
+abs_top_builddir = @abs_top_builddir@
+abs_top_srcdir   = @abs_top_srcdir@
+
+
+include $(abs_top_srcdir)/test-target.mk
+
+
+# The old *.mk tests here work slightly differently to those for all the
+# other simulators so we can't just use the test-target.mk default rules.
+
+PROJECTS	= s0 s1 s2 s3 t1 t2 t3 t4 $(TESTS_OLD)
+
+.PHONY: $(PROJECTS)
+
+all_old:: $(PROJECTS)
+
+$(PROJECTS):
+	@$(MAKE) --no-print-directory MAIN=$@ srcdir='$(srcdir)' -f '$(srcdir)'/sdcc.mk
+
+clean_old::
+	@for p in $(PROJECTS); do \
+		$(MAKE) --no-print-directory MAIN=$$p srcdir='$(srcdir)' -f '$(srcdir)'/sdcc.mk clean ;\
+		rm -rf $$p*.hex ;\
+		rm -rf $$p*.cdb ;\
+	done
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/monitor.c sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/monitor.c
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/monitor.c	2018-12-18 08:22:48.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/monitor.c	1970-01-01 00:00:00.000000000 +0000
@@ -1,282 +0,0 @@
-// Source code under CC0 1.0
-#include 
-#include 
-#include 
-#include 
-#include 
-
-#include "stm8.h"
-
-#include "serial.h"
-#include "flash.h"
-
-#if (DEVICE & DEV_SDISC)
-#define LED_PORT GPIOD
-#define LED_MASK 0x01
-#else
-#define LED_PORT GPIOC
-#define LED_MASK 0x80
-#endif
-
-volatile unsigned char *sif= (unsigned char *)0x7fff;
-
-void
-print_bl()
-{
-  int a, l;
-  uint8_t *p= (uint8_t *)0x6000;
-  printf("%c\n", 2);
-  printf("$A%04x,\n", 0x6000);
-  for (a= 0, l= 0; a < 0x800; a++)
-    {
-      printf("%02x ", p[a]);
-      l++;
-      if ((l % 16) == 0)
-	{
-	  l= 0;
-	  printf("\n");
-	}
-    }
-  printf("%c\n", 3);
-}
-
-void
-dump(unsigned long int start, unsigned long int len)
-{
-  uint8_t *p= (uint8_t *)0;
-  int i= 0;
-  
-  printf("%06lx ", start);
-  while (i= 'a') && (*s <= 'f'))
-	r= r*16 + *s-'a'+10;
-      else if ((*s >= 'A') && (*s <= 'F'))
-	r= r*16 + *s-'A'+10;
-      s++;
-    }
-  return r;
-}
-
-unsigned long int
-xtol(char *s)
-{
-  unsigned long int r= 0;
-  while (*s)
-    {
-      if (isdigit(*s))
-	r= r*16 + *s-'0';
-      else if ((*s >= 'a') && (*s <= 'f'))
-	r= r*16 + *s-'a'+10;
-      else if ((*s >= 'A') && (*s <= 'F'))
-	r= r*16 + *s-'A'+10;
-      s++;
-    }
-  return r;
-}
-
-void f1() {}
-void f2() {}
-
-void
-proc_cmd(char *cmd)
-{
-  char *w= strtok(cmd, DELIM);
-  char *s;
-  uint8_t res;
-  uint8_t *rom= (uint8_t *)0;
-  unsigned long addr;
-  
-  if (w)
-    {
-      if (strcmp(w, "bl") == 0)
-	print_bl();
-      else if (strcmp(w, "uid") == 0)
-	{
-#if defined UID
-	  int i;
-	  uint8_t *p= UID;
-	  printf("0x%04x ", p);
-	  for (i= 0; i < 12; i++)
-	    printf("%02x ", p[i]);
-	  printf("\n");
-#else
-	  printf("no uid\n");
-#endif
-	}
-      else if (strstr(w, "dump") == w)
-	{
-	  s= strtok(NULL, DELIM);
-	  if (s)
-	    {
-	      unsigned long int start= xtol(s);
-	      unsigned long int len= 32;
-	      s= strtok(NULL, DELIM);
-	      if (s)
-		len= xtol(s);
-	      dump(start, len);
-	    }
-	}
-      else if (strcmp(w, "fb") == 0)
-	{
-	  addr= 0xa000;
-	  printf("Before:\n");
-	  dump(addr, 1);
-	  f1();
-	  flash_byte_mode();
-	  flash_punlock();
-	  rom[addr]= 0xa5;
-	  res= flash_wait_finish();
-	  f2();
-	  flash_plock();
-	  printf("After (%s,%d):\n", (res==0)?"succ":"fail", res);
-	  dump(addr, 1);
-	}
-      else if (strcmp(w, "fw") == 0)
-	{
-	  LED_PORT->odr|= LED_MASK;
-	  addr= 0xa0a0;
-	  printf("Before:\n");
-	  dump(addr, 4);
-	  f1();
-	  flash_word_mode();
-	  flash_punlock();
-	  rom[addr+0]= 0x12;
-	  rom[addr+1]= 0x34;
-	  rom[addr+2]= 0x56;
-	  rom[addr+3]= 0x78;
-	  res= flash_wait_finish();
-	  f2();
-	  flash_plock();
-	  printf("After (%s,%d):\n", (res==0)?"succ":"fail", res);
-	  dump(addr, 4);
-	  LED_PORT->odr&= ~LED_MASK;
-	}
-      else if (strcmp(w, "fe") == 0)
-	{
-	  LED_PORT->odr|= LED_MASK;
-	  addr= 0xa000;
-	  printf("Before:\n");
-	  dump(addr, 64);
-	  f1();
-	  flash_punlock();
-	  /*
-	  rom[addr+0]= 0;
-	  rom[addr+1]= 0;
-	  rom[addr+2]= 0;
-	  rom[addr+3]= 0;
-	  res= flash_wait_finish();
-	  */
-	  res= flash_erase((uint8_t*)0xa000, &(FLASH->iapsr));	  
-	  f2();
-	  flash_plock();
-	  printf("After (%s,%d):\n", (res==0)?"succ":"fail", res);
-	  dump(addr, 64);
-	  LED_PORT->odr&= ~LED_MASK;
-	}
-      else if (strstr(w, "test") == w)
-	{
-	  printf("%d\n", sizeof(flash_erase));
-	}
-      else
-	printf("Unknown command: \"%s\"\n", w);
-    }
-  else
-    printf("What?\n");
-}
-
-char cmd[100];
-
-void
-proc_input(char c)
-{
-  int l= strlen(cmd);
-
-  printf("%c", c);
-  if ((c == '\n') ||
-      (c == '\r'))
-    {
-      proc_cmd(cmd);
-      cmd[0]= 0;
-    }
-  else
-    {
-      if (l < 99)
-	{
-	  cmd[l++]= c;
-	  cmd[l]= 0;
-	}
-    }
-}
-  
-void main(void)
-{
-  unsigned long i = 0;
-  unsigned int a= 0;
-
-  CLK->ckdivr = 0x00; // Set the frequency to 16 MHz
-  CLK->pckenr1 = 0xFF; // Enable peripherals
-
-  LED_PORT->ddr= LED_MASK;
-  LED_PORT->cr1= LED_MASK;
-  
-  // USART2
-  // TX: PD5, CN4.10
-  // RX: PD6, CN4.11
-  USART->cr2 = USART_CR2_TEN | USART_CR2_REN; // Allow TX and RX
-  USART->cr3 &= ~(USART_CR3_STOP1 | USART_CR3_STOP2); // 1 stop bit
-  // 0 68 3 0x0683=1667 16MHz-> 9600 baud
-  //USART->brr2 = 0x03;
-  //USART->brr1 = 0x68;
-  // 0 08 b 0x008b=139  16MHz-> 115200 baud
-  USART->brr2 = 0x0b;
-  USART->brr1 = 0x08;
-
-  USART->cr2|= USART_CR2_RIEN;
-  EI;
-
-  printf("%d discovery monitor\n", DEVICE);
-  /*{
-      uint8_t *p= (uint8_t *)0x123456;
-      printf("sizeof p=%d\n", sizeof(p));
-      *p= 0;
-      }*/
-  cmd[0]= 0;
-  {/*
-    struct st {
-      volatile uint8_t v;
-    };
-    struct st s;*/
-    uint8_t r= FLASH->iapsr;
-    while (FLASH->iapsr == 0)
-      ;//r= FLASH->iapsr;
-  }
-  for(;;)
-    {
-      if (serial_received())
-	{
-	  char c= getchar();
-	  proc_input(c);
-	}
-    }
-}
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/monitor.mk sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/monitor.mk
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/monitor.mk	2018-01-25 13:48:09.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/monitor.mk	1970-01-01 00:00:00.000000000 +0000
@@ -1,3 +0,0 @@
-OTHERS		= serial flash
-
-DEVICES		= SDISC LDISC
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/port/baseline/stdout sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/port/baseline/stdout
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/port/baseline/stdout	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/port/baseline/stdout	2022-02-08 21:21:05.000000000 +0000
@@ -0,0 +1,438 @@
+uCsim, Copyright (C)  Daniel Drotos.
+uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+This is free software, and you are welcome to redistribute it
+under certain conditions; type `show c' for details.
+#dump 0x5000 0x501d
+
+# Ports are set to input on reset so if we zero the pins then set
+# the ODR both pins and IDR should remain zero.
+set mem pa_pins 0x00
+0x0      pa_pin:                   
+         pa_pins:                   0b00000000 0x00 '.'   0
+set mem PA_ODR 0xff
+0x05000      PA_ODR:                    0b11111111 0xff '.' 255 ( -1)
+dump pa_pins PA_IDR
+0x0      pa_pin:                   
+         pa_pins:                   0b00000000 0x00 '.'   0
+0x05001      PA_IDR:                    0b00000000 0x00 '.'   0
+
+# Now set all the pins then set every other bit of the data direction register.
+set mem pa_pins 0xff
+0x0      pa_pin:                   
+         pa_pins:                   0b11111111 0xff '.' 255 ( -1)
+set mem PA_DDR 0b10101010
+0x05002      PA_DDR:                    0b10101010 0xaa '.' 170 (-86)
+
+# For the pins set to output the pins and IDR bits shadow the ODR data...
+dump pa_pins PA_IDR
+0x0      pa_pin:                   
+         pa_pins:                   0b11111111 0xff '.' 255 ( -1)
+0x05001      PA_IDR:                    0b11111111 0xff '.' 255 ( -1)
+set mem pa_pins 0x00
+0x0      pa_pin:                   
+         pa_pins:                   0b10101010 0xaa '.' 170 (-86)
+dump pa_pins PA_IDR
+0x0      pa_pin:                   
+         pa_pins:                   0b10101010 0xaa '.' 170 (-86)
+0x05001      PA_IDR:                    0b10101010 0xaa '.' 170 (-86)
+
+# ...and cannot be changed via the IDR...
+set mem PA_IDR 0x00
+0x05001      PA_IDR:                    0b10101010 0xaa '.' 170 (-86)
+
+# ...but can be via the ODR.
+set mem PA_ODR 0x00
+0x05000      PA_ODR:                    0b00000000 0x00 '.'   0
+dump pa_pins
+0x0      pa_pin:                   
+         pa_pins:                   0b00000000 0x00 '.'   0
+
+# Reset back to defaults. Note that only the pa_pins output are affected.
+reset
+dump pa_pins PA_ODR PA_IDR PA_DDR PA_CR1 PA_CR2
+0x0      pa_pin:                   
+         pa_pins:                   0b00000000 0x00 '.'   0
+0x05000      PA_ODR:                    0b00000000 0x00 '.'   0
+0x05001      PA_IDR:                    0b00000000 0x00 '.'   0
+0x05002      PA_DDR:                    0b00000000 0x00 '.'   0
+0x05003      PA_CR1:                    0b00000000 0x00 '.'   0
+0x05004      PA_CR2:                    0b00000000 0x00 '.'   0
+
+
+# Adjust the clock to a suitable speed
+set mem CLK_CKDIVR 0b00000001
+0x050c6 CLK_CKDIVR:           0b00000001 0x01 '.'   1
+        CLK_CKDIVR_HSIDIV:    0b---00--- 0x00 '.'   0
+        CLK_CKDIVR_CPUDIV:    0b-----001 0x01 '.'   1
+
+# Our test VCD provides input on pc_pins.2 and pc_pins.5
+# (these should already be inputs after reset, of course)
+set mem pc_pins.2 0
+0x2.2                               0b-----0-- 0x00 '.'   0
+set mem pc_pins.5 0
+0x2.5                               0b--0----- 0x00 '.'   0
+
+# For which we'll take interrupts on either edge initially
+set mem EXTI_CR1[5:4] 0b11
+0x050a0[5:4]                            0b--11---- 0x03 '.'   3
+set mem PC_CR2.2 1
+0x0500e.2                               0b-----1-- 0x01 '.'   1
+set mem PC_CR2.5 1
+0x0500e.5                               0b--1----- 0x01 '.'   1
+
+# So this is our state now
+dump pc_pins PC_ODR PC_IDR PC_DDR PC_CR1 PC_CR2 EXTI_CR1 EXTI_CR2 rom[0x50a3][7:0]
+0x2      pc_pin:                   
+         pc_pins:                   0b01011010 0x5a 'Z'  90
+0x0500a      PC_ODR:                    0b00000000 0x00 '.'   0
+0x0500b      PC_IDR:                    0b01011010 0x5a 'Z'  90
+0x0500c      PC_DDR:                    0b00000000 0x00 '.'   0
+0x0500d      PC_CR1:                    0b00000000 0x00 '.'   0
+0x0500e      PC_CR2:                    0b00100100 0x24 '$'  36
+0x050a0      EXTI_CR1:                  0b00110000 0x30 '0'  48
+0x050a1      EXTI_CR2:                  0b00000000 0x00 '.'   0
+0x050a3                                 0b00000000 0x00 '.'   0
+
+# Start the vcd (we set the input file via the Makefile) and
+# have it stop execution each time an event occurs.
+set hw vcd[0] start
+set hw vcd[0] break
+Break on events enabled
+
+# The VCD data starts at time 0 which will, by default, align
+# with the current simulator time. We can adjust that by setting
+# starttime. This can be done before or after starting the vcd,
+# even part way through. Here we push the vcd 50 µs into the
+# future.
+set hw vcd[0] starttime 50000 ns
+
+# Set up a vcd to monitor what happens
+set hw vcd new 1
+set hw vcd[1] output "out/test.vcd"
+set hw vcd[1] add PC_IDR.5
+set hw vcd[1] add PC_IDR.2
+set hw vcd[1] add 0x0000
+set hw vcd[1] add rom[0x50a3].2
+set hw vcd[1] add EXTI_CR1[5:4]
+set hw vcd[1] start
+
+# Firstly either edge
+run
+Simulation started, PC=0x008000
+
+Stop at 0x00801c: (104) Breakpoint
+V-IHINZC  Flags= 0x2a  42 *  A= 0x00   0 .
+0-101010  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17f6 [SP+1]= 22  34 "  Limit= 0x1500
+0x0801c    82 00 80 21    int    #0x008021 <.EXTI2>[0K
+F 0x00801c
+Simulated 882 ticks [ELIDED]
+Host usage: [ELIDED]
+cont
+Simulation started, PC=0x00801c
+
+Stop at 0x00801c: (104) Breakpoint
+V-IHINZC  Flags= 0x2a  42 *  A= 0x00   0 .
+0-101010  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17f6 [SP+1]= 22  34 "  Limit= 0x1500
+0x0801c    82 00 80 21    int    #0x008021 <.EXTI2>[0K
+F 0x00801c
+Simulated 194 ticks [ELIDED]
+Host usage: [ELIDED]
+cont
+Simulation started, PC=0x00801c
+
+Stop at 0x00801c: (104) Breakpoint
+V-IHINZC  Flags= 0x2a  42 *  A= 0x00   0 .
+0-101010  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17f6 [SP+1]= 22  34 "  Limit= 0x1500
+0x0801c    82 00 80 21    int    #0x008021 <.EXTI2>[0K
+F 0x00801c
+Simulated 550 ticks [ELIDED]
+Host usage: [ELIDED]
+cont
+Simulation started, PC=0x00801c
+
+Stop at 0x00801c: (104) Breakpoint
+V-IHINZC  Flags= 0x2a  42 *  A= 0x00   0 .
+0-101010  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17f6 [SP+1]= 22  34 "  Limit= 0x1500
+0x0801c    82 00 80 21    int    #0x008021 <.EXTI2>[0K
+F 0x00801c
+Simulated 138 ticks [ELIDED]
+Host usage: [ELIDED]
+cont
+Simulation started, PC=0x00801c
+
+Stop at 0x00801c: (104) Breakpoint
+V-IHINZC  Flags= 0x2a  42 *  A= 0x00   0 .
+0-101010  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17f6 [SP+1]= 22  34 "  Limit= 0x1500
+0x0801c    82 00 80 21    int    #0x008021 <.EXTI2>[0K
+F 0x00801c
+Simulated 278 ticks [ELIDED]
+Host usage: [ELIDED]
+
+# Then on the rising edge
+set mem EXTI_CR1[5:4] 0b01
+0x050a0[5:4]                            0b--01---- 0x01 '.'   1
+cont
+Simulation started, PC=0x00801c
+
+Stop at 0x00802c: (104) Breakpoint
+V-IHINZC  Flags= 0x22  34 "  A= 0x00   0 .
+0-100010  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17ff [SP+1]= 00   0 .  Limit= 0x1500
+
+0x0802c    <.loop$0>:
+0x0802c    cc 80 2c       jp     0x802c <.loop$0>[0K
+F 0x00802c
+Simulated 120 ticks [ELIDED]
+Host usage: [ELIDED]
+cont
+Simulation started, PC=0x00802c
+
+Stop at 0x00801c: (104) Breakpoint
+V-IHINZC  Flags= 0x2a  42 *  A= 0x00   0 .
+0-101010  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17f6 [SP+1]= 22  34 "  Limit= 0x1500
+0x0801c    82 00 80 21    int    #0x008021 <.EXTI2>[0K
+F 0x00801c
+Simulated 154 ticks [ELIDED]
+Host usage: [ELIDED]
+cont
+Simulation started, PC=0x00801c
+
+Stop at 0x00802c: (104) Breakpoint
+V-IHINZC  Flags= 0x22  34 "  A= 0x00   0 .
+0-100010  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17ff [SP+1]= 00   0 .  Limit= 0x1500
+
+0x0802c    <.loop$0>:
+0x0802c    cc 80 2c       jp     0x802c <.loop$0>[0K
+F 0x00802c
+Simulated 132 ticks [ELIDED]
+Host usage: [ELIDED]
+cont
+Simulation started, PC=0x00802c
+
+Stop at 0x00801c: (104) Breakpoint
+V-IHINZC  Flags= 0x2a  42 *  A= 0x00   0 .
+0-101010  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17f6 [SP+1]= 22  34 "  Limit= 0x1500
+0x0801c    82 00 80 21    int    #0x008021 <.EXTI2>[0K
+F 0x00801c
+Simulated 150 ticks [ELIDED]
+Host usage: [ELIDED]
+
+# Then on the falling edge
+set mem EXTI_CR1[5:4] 0b10
+0x050a0[5:4]                            0b--10---- 0x02 '.'   2
+cont
+Simulation started, PC=0x00801c
+
+Stop at 0x00801c: (104) Breakpoint
+V-IHINZC  Flags= 0x2a  42 *  A= 0x00   0 .
+0-101010  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17f6 [SP+1]= 22  34 "  Limit= 0x1500
+0x0801c    82 00 80 21    int    #0x008021 <.EXTI2>[0K
+F 0x00801c
+Simulated 138 ticks [ELIDED]
+Host usage: [ELIDED]
+cont
+Simulation started, PC=0x00801c
+
+Stop at 0x00802c: (104) Breakpoint
+V-IHINZC  Flags= 0x22  34 "  A= 0x00   0 .
+0-100010  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17ff [SP+1]= 00   0 .  Limit= 0x1500
+
+0x0802c    <.loop$0>:
+0x0802c    cc 80 2c       jp     0x802c <.loop$0>[0K
+F 0x00802c
+Simulated 260 ticks [ELIDED]
+Host usage: [ELIDED]
+cont
+Simulation started, PC=0x00802c
+
+Stop at 0x00801c: (104) Breakpoint
+V-IHINZC  Flags= 0x2a  42 *  A= 0x00   0 .
+0-101010  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17f6 [SP+1]= 22  34 "  Limit= 0x1500
+0x0801c    82 00 80 21    int    #0x008021 <.EXTI2>[0K
+F 0x00801c
+Simulated 158 ticks [ELIDED]
+Host usage: [ELIDED]
+cont
+Simulation started, PC=0x00801c
+
+Stop at 0x00802c: (104) Breakpoint
+V-IHINZC  Flags= 0x22  34 "  A= 0x00   0 .
+0-100010  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17ff [SP+1]= 00   0 .  Limit= 0x1500
+
+0x0802c    <.loop$0>:
+0x0802c    cc 80 2c       jp     0x802c <.loop$0>[0K
+F 0x00802c
+Simulated 120 ticks [ELIDED]
+Host usage: [ELIDED]
+cont
+Simulation started, PC=0x00802c
+
+Stop at 0x00801c: (104) Breakpoint
+V-IHINZC  Flags= 0x2a  42 *  A= 0x00   0 .
+0-101010  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17f6 [SP+1]= 22  34 "  Limit= 0x1500
+0x0801c    82 00 80 21    int    #0x008021 <.EXTI2>[0K
+F 0x00801c
+Simulated 298 ticks [ELIDED]
+Host usage: [ELIDED]
+
+# The rest as level (0) triggered
+set mem EXTI_CR1[5:4] 0b00
+0x050a0[5:4]                            0b--00---- 0x00 '.'   0
+cont
+Simulation started, PC=0x00801c
+
+Stop at 0x00801c: (104) Breakpoint
+V-IHINZC  Flags= 0x2a  42 *  A= 0x00   0 .
+0-101010  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17f6 [SP+1]= 22  34 "  Limit= 0x1500
+0x0801c    82 00 80 21    int    #0x008021 <.EXTI2>[0K
+F 0x00801c
+Simulated 144 ticks [ELIDED]
+Host usage: [ELIDED]
+cont
+Simulation started, PC=0x00801c
+
+Stop at 0x00801c: (104) Breakpoint
+V-IHINZC  Flags= 0x2a  42 *  A= 0x00   0 .
+0-101010  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17f6 [SP+1]= 22  34 "  Limit= 0x1500
+0x0801c    82 00 80 21    int    #0x008021 <.EXTI2>[0K
+F 0x00801c
+Simulated 138 ticks [ELIDED]
+Host usage: [ELIDED]
+cont
+Simulation started, PC=0x00801c
+
+Stop at 0x00801c: (104) Breakpoint
+V-IHINZC  Flags= 0x2a  42 *  A= 0x00   0 .
+0-101010  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17f6 [SP+1]= 22  34 "  Limit= 0x1500
+0x0801c    82 00 80 21    int    #0x008021 <.EXTI2>[0K
+F 0x00801c
+Simulated 144 ticks [ELIDED]
+Host usage: [ELIDED]
+cont
+Simulation started, PC=0x00801c
+
+Stop at 0x00801c: (104) Breakpoint
+V-IHINZC  Flags= 0x2a  42 *  A= 0x00   0 .
+0-101010  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17f6 [SP+1]= 22  34 "  Limit= 0x1500
+0x0801c    82 00 80 21    int    #0x008021 <.EXTI2>[0K
+F 0x00801c
+Simulated 144 ticks [ELIDED]
+Host usage: [ELIDED]
+cont
+Simulation started, PC=0x00801c
+
+Stop at 0x008025: (104) Breakpoint
+V-IHINZC  Flags= 0x28  40 (  A= 0x00   0 .
+0-101000  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17f6 [SP+1]= 22  34 "  Limit= 0x1500
+0x08025    80             iret[0K
+F 0x008025
+Simulated 106 ticks [ELIDED]
+Host usage: [ELIDED]
+cont
+Simulation started, PC=0x008025
+
+Stop at 0x00801c: (104) Breakpoint
+V-IHINZC  Flags= 0x2a  42 *  A= 0x00   0 .
+0-101010  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17f6 [SP+1]= 22  34 "  Limit= 0x1500
+0x0801c    82 00 80 21    int    #0x008021 <.EXTI2>[0K
+F 0x00801c
+Simulated 278 ticks [ELIDED]
+Host usage: [ELIDED]
+cont
+Simulation started, PC=0x00801c
+
+Stop at 0x00801c: (104) Breakpoint
+V-IHINZC  Flags= 0x2a  42 *  A= 0x00   0 .
+0-101010  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17f6 [SP+1]= 22  34 "  Limit= 0x1500
+0x0801c    82 00 80 21    int    #0x008021 <.EXTI2>[0K
+F 0x00801c
+Simulated 576 ticks [ELIDED]
+Host usage: [ELIDED]
+cont
+Simulation started, PC=0x00801c
+
+Stop at 0x00801c: (104) Breakpoint
+V-IHINZC  Flags= 0x2a  42 *  A= 0x00   0 .
+0-101010  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17f6 [SP+1]= 22  34 "  Limit= 0x1500
+0x0801c    82 00 80 21    int    #0x008021 <.EXTI2>[0K
+F 0x00801c
+Simulated 142 ticks [ELIDED]
+Host usage: [ELIDED]
+cont
+Simulation started, PC=0x00801c
+
+Stop at 0x00801c: (104) Breakpoint
+V-IHINZC  Flags= 0x2a  42 *  A= 0x00   0 .
+0-101010  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17f6 [SP+1]= 22  34 "  Limit= 0x1500
+0x0801c    82 00 80 21    int    #0x008021 <.EXTI2>[0K
+F 0x00801c
+Simulated 288 ticks [ELIDED]
+Host usage: [ELIDED]
+cont
+Simulation started, PC=0x00801c
+
+Stop at 0x008025: (104) Breakpoint
+V-IHINZC  Flags= 0x28  40 (  A= 0x00   0 .
+0-101000  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17f6 [SP+1]= 22  34 "  Limit= 0x1500
+0x08025    80             iret[0K
+F 0x008025
+Simulated 106 ticks [ELIDED]
+Host usage: [ELIDED]
+cont
+Simulation started, PC=0x008025
+
+Stop at 0x008021: (104) Breakpoint
+V-IHINZC  Flags= 0x2a  42 *  A= 0x00   0 .
+0-101010  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17f6 [SP+1]= 22  34 "  Limit= 0x1500
+
+0x08021    <.EXTI2>:
+0x08021    72 5c 00 00    inc    0x0000[0K
+F 0x008021
+Simulated 140 ticks [ELIDED]
+Host usage: [ELIDED]
+cont
+Simulation started, PC=0x008021
+
+Stop at 0x00801c: (104) Breakpoint
+V-IHINZC  Flags= 0x2a  42 *  A= 0x00   0 .
+0-101010  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17f6 [SP+1]= 22  34 "  Limit= 0x1500
+0x0801c    82 00 80 21    int    #0x008021 <.EXTI2>[0K
+F 0x00801c
+Simulated 138 ticks [ELIDED]
+Host usage: [ELIDED]
+cont
+Simulation started, PC=0x00801c
+
+Stop at 0x00801c: (104) Breakpoint
+V-IHINZC  Flags= 0x2a  42 *  A= 0x00   0 .
+0-101010  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17f6 [SP+1]= 22  34 "  Limit= 0x1500
+0x0801c    82 00 80 21    int    #0x008021 <.EXTI2>[0K
+F 0x00801c
+Simulated 576 ticks [ELIDED]
+Host usage: [ELIDED]
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/port/baseline/test.vcd sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/port/baseline/test.vcd
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/port/baseline/test.vcd	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/port/baseline/test.vcd	2022-02-08 21:21:05.000000000 +0000
@@ -0,0 +1,428 @@
+$date
+	[ELIDED]
+$end
+$version
+	ucsim
+$end
+$timescale 1ps $end
+$scope module ucsim_vcd_1 $end
+$var wire 1 ! PC_IDR.5 $end
+$var wire 1 " PC_IDR.2 $end
+$var wire 8 # rom_0x00000 $end
+$var wire 1 $ rom_0x050a3.2 $end
+$var wire 2 % EXTI_CR1[5:4] $end
+$upscope $end
+$enddefinitions $end
+#0
+$dumpvars
+0!
+0"
+b00001000 #
+0$
+b11 %
+$end
+#750000
+b00000000 #
+#53875000
+1!
+0"
+1$
+#54000000
+0$
+#54812000
+1!
+1"
+1$
+#55750000
+b00000001 #
+#57000000
+0$
+#58750000
+b00000010 #
+#65937000
+0!
+1"
+1$
+#66000000
+0!
+0"
+#66125000
+0$
+#67875000
+b00000011 #
+#100250000
+0!
+1"
+1$
+#100500000
+0$
+#102250000
+b00000100 #
+#109000000
+0!
+0"
+1$
+#109125000
+0$
+#110875000
+b00000101 #
+#126312000
+0!
+1"
+1$
+#126500000
+0$
+#127625000
+b01 %
+#128250000
+b00000110 #
+#135062000
+0!
+0"
+#143562000
+1!
+0"
+1$
+#143625000
+0$
+#143625000
+1!
+1"
+1$
+#145375000
+b00000111 #
+#146625000
+0$
+#148375000
+b00001000 #
+#152812000
+0!
+1"
+#152875000
+0!
+0"
+#161062000
+0!
+1"
+1$
+#161250000
+0$
+#162375000
+b10 %
+#163000000
+b00001001 #
+#169812000
+0!
+0"
+1$
+#169875000
+0$
+#171625000
+b00001010 #
+#187125000
+0!
+1"
+#195875000
+0!
+0"
+1$
+#196000000
+0$
+#197750000
+b00001011 #
+#204500000
+0!
+1"
+#221937000
+0!
+0"
+1$
+#222125000
+0$
+#223250000
+1$
+b00 %
+#223875000
+b00001100 #
+#225125000
+1$
+#226875000
+b00001101 #
+#228125000
+1$
+#229875000
+b00001110 #
+#230437000
+1!
+0"
+#230500000
+1!
+1"
+#231125000
+0$
+#232875000
+b00001111 #
+#239687000
+0!
+1"
+1$
+#239750000
+1$
+#239750000
+0!
+0"
+#241500000
+b00010000 #
+#242750000
+1$
+#244500000
+b00010001 #
+#245750000
+1$
+#247500000
+b00010010 #
+#247937000
+0!
+1"
+#248750000
+1$
+#250500000
+b00010011 #
+#251750000
+1$
+#253500000
+b00010100 #
+#254750000
+1$
+#256500000
+b00010101 #
+#256687000
+0!
+0"
+#257750000
+1$
+#259500000
+b00010110 #
+#260750000
+1$
+#262500000
+b00010111 #
+#263750000
+1$
+#265312000
+0!
+1"
+#265500000
+b00011000 #
+#266750000
+1$
+#268500000
+b00011001 #
+#269750000
+1$
+#271500000
+b00011010 #
+#272750000
+1$
+#274500000
+b00011011 #
+#275750000
+1$
+#277500000
+b00011100 #
+#278750000
+1$
+#280500000
+b00011101 #
+#281750000
+1$
+#282750000
+0!
+0"
+#283500000
+b00011110 #
+#284750000
+1$
+#286500000
+b00011111 #
+#287750000
+1$
+#289500000
+b00100000 #
+#290750000
+1$
+#292500000
+b00100001 #
+#293750000
+1$
+#295500000
+b00100010 #
+#296750000
+1$
+#298500000
+b00100011 #
+#299750000
+1$
+#301500000
+b00100100 #
+#302750000
+1$
+#304500000
+b00100101 #
+#305750000
+1$
+#307500000
+b00100110 #
+#308750000
+1$
+#310500000
+b00100111 #
+#311750000
+1$
+#313500000
+b00101000 #
+#314750000
+1$
+#316500000
+b00101001 #
+#317312000
+1!
+0"
+#317375000
+1!
+1"
+#317750000
+0$
+#319500000
+b00101010 #
+#326562000
+0!
+1"
+1$
+#326625000
+1$
+#326625000
+0!
+0"
+#328375000
+b00101011 #
+#329625000
+1$
+#331375000
+b00101100 #
+#332625000
+1$
+#334375000
+b00101101 #
+#335625000
+1$
+#337375000
+b00101110 #
+#338625000
+1$
+#340375000
+b00101111 #
+#341625000
+1$
+#343375000
+b00110000 #
+#343500000
+0!
+1"
+#344625000
+1$
+#346375000
+b00110001 #
+#347625000
+1$
+#349375000
+b00110010 #
+#350625000
+1$
+#352250000
+0!
+0"
+#352375000
+b00110011 #
+#353625000
+1$
+#355375000
+b00110100 #
+#356625000
+1$
+#358375000
+b00110101 #
+#359625000
+1$
+#360875000
+0!
+1"
+#361375000
+b00110110 #
+#362625000
+1$
+#364375000
+b00110111 #
+#365625000
+1$
+#367375000
+b00111000 #
+#368625000
+1$
+#369625000
+0!
+0"
+#370375000
+b00111001 #
+#371625000
+1$
+#373375000
+b00111010 #
+#374625000
+1$
+#376375000
+b00111011 #
+#377625000
+1$
+#379375000
+b00111100 #
+#380625000
+1$
+#382375000
+b00111101 #
+#383625000
+1$
+#385375000
+b00111110 #
+#386625000
+1$
+#388375000
+b00111111 #
+#389625000
+1$
+#391375000
+b01000000 #
+#392625000
+1$
+#394375000
+b01000001 #
+#395625000
+1$
+#397375000
+b01000010 #
+#398625000
+1$
+#400375000
+b01000011 #
+#401625000
+1$
+#403375000
+b01000100 #
+#404187000
+1!
+0"
+#404250000
+1!
+1"
+#404625000
+0$
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/port/Makefile sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/port/Makefile
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/port/Makefile	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/port/Makefile	2022-02-08 21:21:05.000000000 +0000
@@ -0,0 +1,10 @@
+OUTPUTS = stdout
+
+
+# N.B. We name and open the input VCD file here because if this
+# is an out-of-tree build we want make to tell us the pathname.
+$(OUTPUTS):	test.cmd test.ihx test-in.vcd
+	$(call run-sim, -t S003 -e 'set hw vcd input "$(filter %.vcd,$+)"')
+
+
+include test-lib.mk
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/port/test.asm sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/port/test.asm
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/port/test.asm	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/port/test.asm	2022-02-08 21:21:05.000000000 +0000
@@ -0,0 +1,27 @@
+	.area _DATA
+count:	.ds 1
+
+	.area _CODE
+	int reset
+	int unused
+	int unused
+	int unused
+	int unused
+	int unused
+	int unused
+	int irq_exti2 ; Port C external interrupts
+
+unused:
+	iret
+
+irq_exti2:
+	inc count
+	iret
+
+reset:
+	ld a, #0
+	ld count, a
+	rim
+
+loop:
+	jp loop
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/port/test.cmd sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/port/test.cmd
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/port/test.cmd	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/port/test.cmd	2022-02-08 21:21:05.000000000 +0000
@@ -0,0 +1,104 @@
+#dump 0x5000 0x501d
+
+# Ports are set to input on reset so if we zero the pins then set
+# the ODR both pins and IDR should remain zero.
+set mem pa_pins 0x00
+set mem PA_ODR 0xff
+dump pa_pins PA_IDR
+
+# Now set all the pins then set every other bit of the data direction register.
+set mem pa_pins 0xff
+set mem PA_DDR 0b10101010
+
+# For the pins set to output the pins and IDR bits shadow the ODR data...
+dump pa_pins PA_IDR
+set mem pa_pins 0x00
+dump pa_pins PA_IDR
+
+# ...and cannot be changed via the IDR...
+set mem PA_IDR 0x00
+
+# ...but can be via the ODR.
+set mem PA_ODR 0x00
+dump pa_pins
+
+# Reset back to defaults. Note that only the pa_pins output are affected.
+reset
+dump pa_pins PA_ODR PA_IDR PA_DDR PA_CR1 PA_CR2
+
+
+# Adjust the clock to a suitable speed
+set mem CLK_CKDIVR 0b00000001
+
+# Our test VCD provides input on pc_pins.2 and pc_pins.5
+# (these should already be inputs after reset, of course)
+set mem pc_pins.2 0
+set mem pc_pins.5 0
+
+# For which we'll take interrupts on either edge initially
+set mem EXTI_CR1[5:4] 0b11
+set mem PC_CR2.2 1
+set mem PC_CR2.5 1
+
+# So this is our state now
+dump pc_pins PC_ODR PC_IDR PC_DDR PC_CR1 PC_CR2 EXTI_CR1 EXTI_CR2 rom[0x50a3][7:0]
+
+# Start the vcd (we set the input file via the Makefile) and
+# have it stop execution each time an event occurs.
+set hw vcd[0] start
+set hw vcd[0] break
+
+# The VCD data starts at time 0 which will, by default, align
+# with the current simulator time. We can adjust that by setting
+# starttime. This can be done before or after starting the vcd,
+# even part way through. Here we push the vcd 50 µs into the
+# future.
+set hw vcd[0] starttime 50000 ns
+
+# Set up a vcd to monitor what happens
+set hw vcd new 1
+set hw vcd[1] output "out/test.vcd"
+set hw vcd[1] add PC_IDR.5
+set hw vcd[1] add PC_IDR.2
+set hw vcd[1] add 0x0000
+set hw vcd[1] add rom[0x50a3].2
+set hw vcd[1] add EXTI_CR1[5:4]
+set hw vcd[1] start
+
+# Firstly either edge
+run
+cont
+cont
+cont
+cont
+
+# Then on the rising edge
+set mem EXTI_CR1[5:4] 0b01
+cont
+cont
+cont
+cont
+
+# Then on the falling edge
+set mem EXTI_CR1[5:4] 0b10
+cont
+cont
+cont
+cont
+cont
+
+# The rest as level (0) triggered
+set mem EXTI_CR1[5:4] 0b00
+cont
+cont
+cont
+cont
+cont
+cont
+cont
+cont
+cont
+cont
+cont
+cont
+cont
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/port/test.ihx sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/port/test.ihx
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/port/test.ihx	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/port/test.ihx	2022-02-08 21:21:05.000000000 +0000
@@ -0,0 +1,3 @@
+:20800000820080268200802082008020820080208200802082008020820080208200802149
+:0F80200080725C000080A600C700009ACC802C04
+:00000001FF
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/port/test-in.vcd sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/port/test-in.vcd
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/port/test-in.vcd	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/port/test-in.vcd	2022-02-08 21:21:05.000000000 +0000
@@ -0,0 +1,88 @@
+$date
+Wed Sep  5 21:01:53 2018
+$end
+$version
+ucsim
+$end
+$timescale 1ns $end
+$scope module ucsim_vcd_0 $end
+$var wire 1 ! pc_pins.5 $end
+$var wire 1 " pc_pins.2 $end
+$upscope $end
+$enddefinitions $end
+$dumpvars
+0!
+0"
+$end
+#3875
+1!
+#4812
+1"
+#15937
+0!
+#16000
+0"
+#50250
+1"
+#59000
+0"
+#76312
+1"
+#85062
+0"
+#93562
+1!
+#93625
+1"
+#102812
+0!
+#102875
+0"
+#111062
+1"
+#119812
+0"
+#137125
+1"
+#145875
+0"
+#154500
+1"
+#171937
+0"
+#180437
+1!
+#180500
+1"
+#189687
+0!
+#189750
+0"
+#197937
+1"
+#206687
+0"
+#215312
+1"
+#232750
+0"
+#267312
+1!
+#267375
+1"
+#276562
+0!
+#276625
+0"
+#293500
+1"
+#302250
+0"
+#310875
+1"
+#319625
+0"
+#354187
+1!
+#354250
+1"
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/s0.c sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/s0.c
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/s0.c	2017-02-21 09:48:05.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/s0.c	1970-01-01 00:00:00.000000000 +0000
@@ -1,33 +0,0 @@
-#include 
-#include 
-
-#define DEVICE DEV_STM8S208
-
-#include "stm8.h"
-
-int putchar(int c)
-{
-  while(!(USART->sr & USART_SR_TXE));
-
-  USART->dr = c;
-  return c;
-}
-
-void main(void)
-{
-  unsigned long i = 0;
-
-  CLK->ckdivr = 0x00; // Set the frequency to 16 MHz
-  CLK->pckenr1 = 0xFF; // Enable peripherals
-
-  USART->cr2 = USART_CR2_TEN; // Allow TX and RX
-  USART->cr3 &= ~(USART_CR3_STOP1 | USART_CR3_STOP2); // 1 stop bit
-  USART->brr2 = 0x03;
-  USART->brr1 = 0x68; // 9600 baud
-  
-  for(;;)
-    {
-      printf("Hello World!\n");
-      for(i = 0; i < 147456; i++); // Sleep
-    }
-}
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/s1.c sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/s1.c
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/s1.c	2017-02-21 09:48:05.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/s1.c	1970-01-01 00:00:00.000000000 +0000
@@ -1,29 +0,0 @@
-#include 
-#include 
-
-#define DEVICE DEV_STM8S208
-
-#include "stm8.h"
-
-int putchar(int c)
-{
-  while(!(USART->sr & USART_SR_TXE));
-  USART->dr = c;
-  return c;
-}
-
-void main(void)
-{
-  unsigned long i = 0;
-
-  CLK->ckdivr = 0x00; // Set the frequency to 16 MHz
-  CLK->pckenr1 = 0xFF; // Enable peripherals
-
-  USART->cr2 = USART_CR2_TEN; // Allow TX and RX
-  USART->cr3 &= ~(USART_CR3_STOP1 | USART_CR3_STOP2); // 1 stop bit
-  USART->brr2 = 0x03;
-  USART->brr1 = 0x68; // 9600 baud
-
-  printf("Hello World!\n");
-  for (;;) ;
-}
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/s2.c sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/s2.c
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/s2.c	2018-01-25 13:48:09.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/s2.c	1970-01-01 00:00:00.000000000 +0000
@@ -1,78 +0,0 @@
-#include 
-#include 
-#include 
-
-#define DEVICE DEV_STM8S208
-
-#include "stm8.h"
-
-volatile unsigned char *sif= (unsigned char *)0x7fff;
-
-int sifchar(int c)
-{
-  *sif= 'p';
-  *sif= c;
-  return c;
-}
-
-void waitsend()
-{
-  while(!(USART->sr & USART_SR_TXE));
-}
-
-int putchar(int c)
-{
-  while(!(USART->sr & USART_SR_TXE));
-  USART->dr = c;
-  return c;
-}
-
-char received()
-{
-  return USART->sr & USART_SR_RXNE;
-}
-
-char getchar()
-{
-  while (!received())
-    ;
-  return USART->dr;
-}
-
-void prints(char *s)
-{
-  char i= 0;
-  while (s[i])
-    {
-      putchar(s[i]);
-      i++;
-    }
-}
-
-void main(void)
-{
-  unsigned long i = 0;
-
-  CLK->ckdivr = 0x00; // Set the frequency to 16 MHz
-  CLK->pckenr1 = 0xFF; // Enable peripherals
-
-  USART->cr2 = USART_CR2_TEN; // Allow TX only yet
-  USART->cr3 &= ~(USART_CR3_STOP1 | USART_CR3_STOP2); // 1 stop bit
-  USART->brr2 = 0x03;
-  USART->brr1 = 0x68; // 9600 baud
-  
-  printf("Hello World!\n");
-  waitsend();
-  USART->cr2 = USART_CR2_TEN | USART_CR2_REN; // Allow TX and RX
-  for (;;)
-    {
-      if (received())
-	{
-	  char c= getchar();
-	  *sif= 'x';*sif= c;
-	  putchar(toupper(c));
-	  if (c == 'Z')
-	    *sif= 's';
-	}
-    }
-}
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/s3.c sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/s3.c
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/s3.c	2017-02-21 09:48:05.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/s3.c	1970-01-01 00:00:00.000000000 +0000
@@ -1,98 +0,0 @@
-#include 
-#include 
-#include 
-
-#define DEVICE DEV_STM8S208
-
-#include "stm8.h"
-
-volatile unsigned char *sif= (unsigned char *)0x7fff;
-
-int sifchar(int c)
-{
-  *sif= 'p';
-  *sif= c;
-  return c;
-}
-
-int putchar(int c)
-{
-  while(!(USART->sr & USART_SR_TXE));
-  USART->dr = c;
-  return c;
-}
-
-volatile uint8_t rx_buf[8];
-volatile uint8_t first_free= 0;
-volatile uint8_t last_used= 0;
-
-void isr_rx(void) __interrupt(USART_RX_IRQ)
-{
-  volatile uint8_t d;
-  *sif='p';*sif='I';
-  if (USART->sr & USART_SR_RXNE)
-    {
-      uint8_t n;
-      d= USART->dr;
-      n= (first_free+1)%8;
-      if (n != last_used)
-	{
-	  rx_buf[first_free]= d;
-	  first_free= n;
-	}
-    }
-}
-
-char received()
-{
-  //return UART2_SR & UART_SR_RXNE;
-  return first_free != last_used;
-}
-
-char getchar()
-{
-  uint8_t o;
-  while (!received())
-    ;
-  o= last_used;
-  last_used= (last_used+1)%8;
-  return rx_buf[o];
-}
-
-void prints(char *s)
-{
-  char i= 0;
-  while (s[i])
-    {
-      putchar(s[i]);
-      i++;
-    }
-}
-
-
-void main(void)
-{
-  unsigned long i = 0;
-
-  CLK->ckdivr = 0x00; // Set the frequency to 16 MHz
-  CLK->pckenr1 = 0xFF; // Enable peripherals
-
-  USART->cr2 = USART_CR2_TEN | USART_CR2_REN; // Allow TX and RX
-  USART->cr3 &= ~(USART_CR3_STOP1 | USART_CR3_STOP2); // 1 stop bit
-  USART->brr2 = 0x03;
-  USART->brr1 = 0x68; // 9600 baud
-
-  USART->cr2|= USART_CR2_RIEN;
-  EI;
-  
-  printf("Hello World!\n");
-  for (;;)
-    {
-      if (received())
-	{
-	  char c= getchar();
-	  *sif= 'x';*sif= c;
-	  putchar(toupper(c));
-	}
-    }
-}
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/sdcc.mk sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/sdcc.mk
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/sdcc.mk	2018-01-25 13:48:09.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/sdcc.mk	1970-01-01 00:00:00.000000000 +0000
@@ -1,67 +0,0 @@
-VPATH		= ..
-
-vpath		%.mk $(VPATH)
-
-TARGET		= stm8
-
-CC		= sdcc -m$(TARGET) --std-c99
-
-CPPFLAGS	=
-CFLAGS		= --debug
-LDFLAGS		=
-LIBS		=
-
--include	$(MAIN).mk
-
-DEVICES		?= S208
-
-ALL		= $(MAIN) $(OTHERS)
-
-OBJECTS		= $(MAIN).rel $(OTHERS:=.rel)
-
-CPPFLAGS	= -DDEVICE=DEV_STM8$(DEVICE) -I$(VPATH)
-
-.SUFFIXES: .rel .ihx .hex
-
-.PHONY: $(DEVICES)
-
-all: $(DEVICES)
-
-$(DEVICES):
-	test -d $@ || mkdir $@
-	$(MAKE) -C $@ DEVICE=$@ REAL=yes MAIN=$(MAIN) -I$(VPATH) -f$(VPATH)/sdcc.mk compile copy_result
-
-copy_result: $(VPATH)/$(MAIN)_$(DEVICE).hex $(VPATH)/$(MAIN)_$(DEVICE).cdb
-
-$(VPATH)/$(MAIN)_$(DEVICE).hex: $(MAIN).hex
-	cp $< $@
-
-$(VPATH)/$(MAIN)_$(DEVICE).cdb: $(MAIN).cdb
-	cp $(MAIN).cdb $@
-
-compile: dep $(MAIN).hex
-
-.c.rel:
-	$(CC) $(CPPFLAGS) $(CFLAGS) -o $@ -c $<
-
-.ihx.hex:
-	packihx $< >$@
-
-$(MAIN).ihx: $(OBJECTS)
-	$(CC) $(CFLAGS) $(LDFLAAGS) $(OBJECTS) -o $@
-
-$(MAIN).cdb: $(MAIN).hex
-
-dep: $(MAIN).dep
-
-$(MAIN).dep: $(addprefix ../,$(OBJECTS:.rel=.c)) ../*.h
-	for c in $(addprefix ../,$(OBJECTS:.rel=.c)); do \
-		$(CC) -MM $(CPPFLAGS) $$c >>$@; \
-	done
-
-clean:
-	rm -rf $(DEVICES)
-
-ifeq ($(REAL),yes)
-include $(MAIN).dep
-endif
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/serial/baseline/stdout sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/serial/baseline/stdout
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/serial/baseline/stdout	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/serial/baseline/stdout	2022-02-08 21:21:05.000000000 +0000
@@ -0,0 +1,367 @@
+uCsim, Copyright (C)  Daniel Drotos.
+uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+This is free software, and you are welcome to redistribute it
+under certain conditions; type `show c' for details.
+var __interrupt_vect rom[0x8000]
+var _isr_unused rom[0x807c]
+var tx_bit_1 rom[0x8115]
+var tx_stop rom[0x811b]
+var tx_done rom[0x8121]
+var tx_idle rom[0x8145]
+var rx rom[0x8153]
+var rx_have_a rom[0x8156]
+var rx_active rom[0x8158]
+var rx_sample_1 rom[0x8165]
+var rx_next_bit rom[0x8169]
+var rx_done rom[0x817b]
+var rx_data rom[0x817c]
+var rx_idle rom[0x8189]
+var rx_stop rom[0x818e]
+var vuart_tx_put rom[0x81ba]
+var _boot rom[0x81db]
+var forever rom[0x82a1]
+var uart1_tx_buf rom[0x1]
+var vuart_tx_state rom[0x21]
+var vuart_tx rom[0x22]
+var vuart_rx_state rom[0x23]
+var vuart_rx rom[0x24]
+var vuart_rx_bit rom[0x25]
+var vuart_tx_buf rom[0x26]
+var uart1_tx_w rom[0x36]
+var uart1_tx_r rom[0x38]
+var vuart_tx_w rom[0x3a]
+var vuart_tx_r rom[0x3c]
+var IRQ_EXTI3 rom[0x80d3]
+var IRQ_TIM2 rom[0x80f5]
+var IRQ_UART1_TX rom[0x80a5]
+var IRQ_UART1_RX rom[0x807d]
+# Set some core vars
+var CLK_PCKENR1       rom[0x50c7][7:0]
+var CLK_PCKENR1_UART1 rom[0x50c7].3
+var CLK_PCKENR1_TIM2  rom[0x50c7].5
+var UART1_SR          rom[0x5230]
+var UART1_SR_TXE      rom[0x5230].7
+var UART1_SR_TC       rom[0x5230].6
+var UART1_SR_RXNE     rom[0x5230].5
+
+dump rom[0x00] 0x3d
+0x00000                       08                      .
+0x00001 uart1_tx_buf:         70 d4 b2 8a 29 54 48 9a p...)TH.
+0x00009                       0a bc d5 0e 18 a8 44 ac ......D.
+0x00011                       5b f3 8e 4c d7 2d 9b 09 [..L.-..
+0x00019                       42 e5 06 c4 33 af cd a3 B...3...
+0x00021 vuart_tx_state:       84                      .
+0x00022 vuart_tx:             7f                      .
+0x00023 vuart_rx_state:       2d                      -
+0x00024 vuart_rx:             ad                      .
+0x00025 vuart_rx_bit:         d4                      .
+0x00026 vuart_tx_buf:         76 47 de 32 1c ec 4a c4 vG.2..J.
+0x0002e                       30 f6 20 23 85 6c fb b2 0. #.l..
+0x00036 uart1_tx_w:           07 04                   ..
+0x00038 uart1_tx_r:           f4 ec                   ..
+0x0003a vuart_tx_w:           0b b9                   ..
+0x0003c vuart_tx_r:           20 ba                    .
+dc 0x8000 0x082a4 
+
+0x08000    <__interrupt_vect>:
+0x08000    82 00 81 db    int    #0x0081db <_boot>[0K
+0x08004    82 00 80 7c    int    #0x00807c <_isr_unused>[0K
+0x08008    82 00 80 7c    int    #0x00807c <_isr_unused>[0K
+0x0800c    82 00 80 7c    int    #0x00807c <_isr_unused>[0K
+0x08010    82 00 80 7c    int    #0x00807c <_isr_unused>[0K
+0x08014    82 00 80 7c    int    #0x00807c <_isr_unused>[0K
+0x08018    82 00 80 7c    int    #0x00807c <_isr_unused>[0K
+0x0801c    82 00 80 7c    int    #0x00807c <_isr_unused>[0K
+0x08020    82 00 80 d3    int    #0x0080d3 [0K
+0x08024    82 00 80 7c    int    #0x00807c <_isr_unused>[0K
+0x08028    82 00 80 7c    int    #0x00807c <_isr_unused>[0K
+0x0802c    82 00 80 7c    int    #0x00807c <_isr_unused>[0K
+0x08030    82 00 80 7c    int    #0x00807c <_isr_unused>[0K
+0x08034    82 00 80 7c    int    #0x00807c <_isr_unused>[0K
+0x08038    82 00 80 7c    int    #0x00807c <_isr_unused>[0K
+0x0803c    82 00 80 f5    int    #0x0080f5 [0K
+0x08040    82 00 80 7c    int    #0x00807c <_isr_unused>[0K
+0x08044    82 00 80 7c    int    #0x00807c <_isr_unused>[0K
+0x08048    82 00 80 7c    int    #0x00807c <_isr_unused>[0K
+0x0804c    82 00 80 a5    int    #0x0080a5 [0K
+0x08050    82 00 80 7d    int    #0x00807d [0K
+0x08054    82 00 80 7c    int    #0x00807c <_isr_unused>[0K
+0x08058    82 00 80 7c    int    #0x00807c <_isr_unused>[0K
+0x0805c    82 00 80 7c    int    #0x00807c <_isr_unused>[0K
+0x08060    82 00 80 7c    int    #0x00807c <_isr_unused>[0K
+0x08064    82 00 80 7c    int    #0x00807c <_isr_unused>[0K
+0x08068    82 00 80 7c    int    #0x00807c <_isr_unused>[0K
+0x0806c    82 00 80 7c    int    #0x00807c <_isr_unused>[0K
+0x08070    82 00 80 7c    int    #0x00807c <_isr_unused>[0K
+0x08074    82 00 80 7c    int    #0x00807c <_isr_unused>[0K
+0x08078    82 00 80 7c    int    #0x00807c <_isr_unused>[0K
+
+0x0807c    <_isr_unused>:
+0x0807c    80             iret[0K
+
+0x0807d    :
+0x0807d    4b 00          push   #0x00[0K
+0x0807f    86             pop    CC[0K
+0x08080    9b             sim[0K
+0x08081    c6 52 31       ld     A,0x5231[0K
+0x08084    ce 00 3a       ldw    X,0x003a [0K
+0x08087    d7 00 26       ld     (0x0026 ,X),A[0K
+0x0808a    5a             decw   X[0K
+0x0808b    2a 03          jrpl   0x8090 <.label$32>[0K
+0x0808d    ae 00 0f       ldw    X,#0x000f[0K
+
+0x08090    <.label$32>:
+0x08090    cf 00 3a       ldw    0x003a ,X[0K
+0x08093    72 00 53 00 0c btjt   0x5300,#0,0x80a4 <.bit0_isset$33>[0K
+0x08098    72 1a 50 c7    bset   0x50c7 ,#5 [0K
+0x0809c    72 10 53 00    bset   0x5300,#0[0K
+0x080a0    72 10 53 06    bset   0x5306,#0[0K
+
+0x080a4    <.bit0_isset$33>:
+0x080a4    80             iret[0K
+
+0x080a5    :
+0x080a5    4b 08          push   #0x08[0K
+0x080a7    86             pop    CC[0K
+0x080a8    9b             sim[0K
+0x080a9    72 0c 52 30 20 btjt   0x5230 ,#6 ,0x80ce <.bit6_isset$29>[0K
+0x080ae    ce 00 38       ldw    X,0x0038 [0K
+0x080b1    c3 00 36       cpw    X,0x0036 [0K
+0x080b4    27 13          jreq   0x80c9 <.label$30>[0K
+0x080b6    ce 00 38       ldw    X,0x0038 [0K
+0x080b9    d6 00 01       ld     A,(0x0001 ,X)[0K
+0x080bc    5a             decw   X[0K
+0x080bd    2a 03          jrpl   0x80c2 <.label$31>[0K
+0x080bf    ae 00 1f       ldw    X,#0x001f[0K
+
+0x080c2    <.label$31>:
+0x080c2    cf 00 38       ldw    0x0038 ,X[0K
+0x080c5    c7 52 31       ld     0x5231,A[0K
+0x080c8    80             iret[0K
+
+0x080c9    <.label$30>:
+0x080c9    72 1f 52 35    bres   0x5235,#7[0K
+0x080cd    80             iret[0K
+
+0x080ce    <.bit6_isset$29>:
+0x080ce    72 1d 52 30    bres   0x5230 ,#6 [0K
+0x080d2    80             iret[0K
+
+0x080d3    :
+0x080d3    4b 28          push   #0x28[0K
+0x080d5    86             pop    CC[0K
+0x080d6    9b             sim[0K
+0x080d7    72 17 50 13    bres   0x5013 ,#3[0K
+0x080db    35 0a 00 23    mov    0x0023 ,#0x0a[0K
+0x080df    35 ff 00 25    mov    0x0025 ,#0xff[0K
+0x080e3    72 00 53 00 0c btjt   0x5300,#0,0x80f4 <.bit0_isset$34>[0K
+0x080e8    72 1a 50 c7    bset   0x50c7 ,#5 [0K
+0x080ec    72 10 53 00    bset   0x5300,#0[0K
+0x080f0    72 10 53 06    bset   0x5306,#0[0K
+
+0x080f4    <.bit0_isset$34>:
+0x080f4    80             iret[0K
+
+0x080f5    :
+0x080f5    4b 28          push   #0x28[0K
+0x080f7    86             pop    CC[0K
+0x080f8    9b             sim[0K
+0x080f9    72 11 53 04    bres   0x5304,#0[0K
+0x080fd    c6 00 21       ld     A,0x0021 [0K
+0x08100    2b 1f          jrmi   0x8121 [0K
+0x08102    72 5a 00 21    dec    0x0021 [0K
+0x08106    2b 13          jrmi   0x811b [0K
+0x08108    72 56 00 22    rrc    0x0022 [0K
+0x0810c    25 07          jrult  0x8115 [0K
+0x0810e    9d             nop[0K
+0x0810f    72 15 50 0f    bres   0x500f ,#2[0K
+0x08113    20 3e          jra    0x8153 [0K
+
+0x08115    :
+0x08115    72 14 50 0f    bset   0x500f ,#2[0K
+0x08119    20 38          jra    0x8153 [0K
+
+0x0811b    :
+0x0811b    72 14 50 0f    bset   0x500f ,#2[0K
+0x0811f    20 32          jra    0x8153 [0K
+
+0x08121    :
+0x08121    ce 00 3c       ldw    X,0x003c [0K
+0x08124    c3 00 3a       cpw    X,0x003a [0K
+0x08127    27 1c          jreq   0x8145 [0K
+0x08129    72 15 50 0f    bres   0x500f ,#2[0K
+0x0812d    ce 00 3c       ldw    X,0x003c [0K
+0x08130    d6 00 26       ld     A,(0x0026 ,X)[0K
+0x08133    5a             decw   X[0K
+0x08134    2a 03          jrpl   0x8139 <.label$46>[0K
+0x08136    ae 00 0f       ldw    X,#0x000f[0K
+
+0x08139    <.label$46>:
+0x08139    cf 00 3c       ldw    0x003c ,X[0K
+0x0813c    c7 00 22       ld     0x0022 ,A[0K
+0x0813f    35 08 00 21    mov    0x0021 ,#0x08[0K
+0x08143    20 0e          jra    0x8153 [0K
+
+0x08145    :
+0x08145    c6 00 23       ld     A,0x0023 [0K
+0x08148    2a 0c          jrpl   0x8156 [0K
+0x0814a    72 11 53 00    bres   0x5300,#0[0K
+0x0814e    72 1b 50 c7    bres   0x50c7 ,#5 [0K
+0x08152    80             iret[0K
+
+0x08153    :
+0x08153    c6 00 23       ld     A,0x0023 [0K
+
+0x08156    :
+0x08156    2b 23          jrmi   0x817b [0K
+
+0x08158    :
+0x08158    72 07 50 10 08 btjf   0x5010 ,#3,0x8165 [0K
+0x0815d    72 5a 00 25    dec    0x0025 [0K
+0x08161    72 5a 00 25    dec    0x0025 [0K
+
+0x08165    :
+0x08165    72 5c 00 25    inc    0x0025 [0K
+
+0x08169    :
+0x08169    4a             dec    A[0K
+0x0816a    c7 00 23       ld     0x0023 ,A[0K
+0x0816d    2b 1a          jrmi   0x8189 [0K
+0x0816f    27 1d          jreq   0x818e [0K
+0x08171    a1 0a          cp     A,#0x0a[0K
+0x08173    26 07          jrne   0x817c [0K
+0x08175    72 59 00 25    rlc    0x0025 [0K
+0x08179    25 0e          jrult  0x8189 [0K
+
+0x0817b    :
+0x0817b    80             iret[0K
+
+0x0817c    :
+0x0817c    72 59 00 25    rlc    0x0025 [0K
+0x08180    72 56 00 24    rrc    0x0024 [0K
+0x08184    72 5f 00 25    clr    0x0025 [0K
+0x08188    80             iret[0K
+
+0x08189    :
+0x08189    72 16 50 13    bset   0x5013 ,#3[0K
+0x0818d    80             iret[0K
+
+0x0818e    :
+0x0818e    c6 00 24       ld     A,0x0024 [0K
+0x08191    8a             push   CC[0K
+0x08192    9b             sim[0K
+0x08193    ce 00 38       ldw    X,0x0038 [0K
+0x08196    c3 00 36       cpw    X,0x0036 [0K
+0x08199    26 0e          jrne   0x81a9 <.label$42>[0K
+0x0819b    72 0f 52 30 09 btjf   0x5230 ,#7 ,0x81a9 <.label$42>[0K
+0x081a0    c7 52 31       ld     0x5231,A[0K
+0x081a3    72 1e 52 35    bset   0x5235,#7[0K
+0x081a7    20 0f          jra    0x81b8 <.label$44>[0K
+
+0x081a9    <.label$42>:
+0x081a9    ce 00 36       ldw    X,0x0036 [0K
+0x081ac    d7 00 01       ld     (0x0001 ,X),A[0K
+0x081af    5a             decw   X[0K
+0x081b0    2a 03          jrpl   0x81b5 <.label$43>[0K
+0x081b2    ae 00 1f       ldw    X,#0x001f[0K
+
+0x081b5    <.label$43>:
+0x081b5    cf 00 36       ldw    0x0036 ,X[0K
+
+0x081b8    <.label$44>:
+0x081b8    86             pop    CC[0K
+0x081b9    80             iret[0K
+
+0x081ba    :
+0x081ba    ce 00 3a       ldw    X,0x003a [0K
+0x081bd    d7 00 26       ld     (0x0026 ,X),A[0K
+0x081c0    5a             decw   X[0K
+0x081c1    2a 03          jrpl   0x81c6 <.label$53>[0K
+0x081c3    ae 00 0f       ldw    X,#0x000f[0K
+
+0x081c6    <.label$53>:
+0x081c6    cf 00 3a       ldw    0x003a ,X[0K
+0x081c9    72 00 53 00 0c btjt   0x5300,#0,0x81da <.bit0_isset$54>[0K
+0x081ce    72 1a 50 c7    bset   0x50c7 ,#5 [0K
+0x081d2    72 10 53 00    bset   0x5300,#0[0K
+0x081d6    72 10 53 06    bset   0x5306,#0[0K
+
+0x081da    <.bit0_isset$54>:
+0x081da    81             ret[0K
+
+0x081db    <_boot>:
+0x081db    35 00 50 c6    mov    0x50c6 ,#0x00[0K
+0x081df    35 00 50 c7    mov    0x50c7 ,#0x00[0K
+0x081e3    35 00 50 ca    mov    0x50ca ,#0x00[0K
+0x081e7    ae 00 08       ldw    X,#0x0008[0K
+0x081ea    27 07          jreq   0x81f3 <.label$50>[0K
+
+0x081ec    <.loop$57>:
+0x081ec    72 4f 00 35    clr    (0x0035,X)[0K
+0x081f0    5a             decw   X[0K
+0x081f1    26 f9          jrne   0x81ec <.loop$57>[0K
+
+0x081f3    <.label$50>:
+0x081f3    ae 00 00       ldw    X,#0x0000[0K
+0x081f6    27 09          jreq   0x8201 <.label$51>[0K
+
+0x081f8    <.loop$56>:
+0x081f8    d6 81 da       ld     A,(0x81da <.bit0_isset$54>,X)[0K
+0x081fb    d7 00 3d       ld     (0x003d,X),A[0K
+0x081fe    5a             decw   X[0K
+0x081ff    26 f7          jrne   0x81f8 <.loop$56>[0K
+
+0x08201    <.label$51>:
+0x08201    c6 7f 74       ld     A,0x7f74 [0K
+0x08204    a4 f3          and    A,#0xf3[0K
+0x08206    aa 04          or     A,#0x04[0K
+0x08208    c7 7f 74       ld     0x7f74 ,A[0K
+0x0820b    c6 7f 74       ld     A,0x7f74 [0K
+0x0820e    a4 cf          and    A,#0xcf[0K
+0x08210    aa 00          or     A,#0x00[0K
+0x08212    c7 7f 74       ld     0x7f74 ,A[0K
+0x08215    c6 7f 73       ld     A,0x7f73 [0K
+0x08218    a4 f3          and    A,#0xf3[0K
+0x0821a    aa 0c          or     A,#0x0c[0K
+0x0821c    c7 7f 73       ld     0x7f73 ,A[0K
+0x0821f    35 20 52 34    mov    0x5234,#0x20[0K
+0x08223    35 2c 52 35    mov    0x5235,#0x2c[0K
+0x08227    35 00 52 36    mov    0x5236,#0x00[0K
+0x0822b    35 0b 52 33    mov    0x5233,#0x0b[0K
+0x0822f    35 08 52 32    mov    0x5232,#0x08[0K
+0x08233    72 16 50 c7    bset   0x50c7 ,#3 [0K
+0x08237    72 1b 52 34    bres   0x5234,#5[0K
+0x0823b    35 0f 00 3c    mov    0x003c ,#0x0f[0K
+0x0823f    35 0f 00 3a    mov    0x003a ,#0x0f[0K
+0x08243    35 ff 00 21    mov    0x0021 ,#0xff[0K
+0x08247    35 ff 00 23    mov    0x0023 ,#0xff[0K
+0x0824b    72 14 50 11    bset   0x5011 ,#2[0K
+0x0824f    72 14 50 12    bset   0x5012 ,#2[0K
+0x08253    72 15 50 13    bres   0x5013 ,#2[0K
+0x08257    72 14 50 0f    bset   0x500f ,#2[0K
+0x0825b    72 17 50 11    bres   0x5011 ,#3[0K
+0x0825f    72 17 50 12    bres   0x5012 ,#3[0K
+0x08263    72 16 50 13    bset   0x5013 ,#3[0K
+0x08267    c6 50 a1       ld     A,0x50a1 [0K
+0x0826a    a4 fc          and    A,#0xfc[0K
+0x0826c    aa 02          or     A,#0x02[0K
+0x0826e    c7 50 a1       ld     0x50a1 ,A[0K
+0x08271    35 00 53 0e    mov    0x530e,#0x00[0K
+0x08275    35 00 53 0f    mov    0x530f,#0x00[0K
+0x08279    35 8b 53 10    mov    0x5310,#0x8b[0K
+0x0827d    72 15 53 00    bres   0x5300,#2[0K
+0x08281    72 10 53 03    bset   0x5303,#0[0K
+0x08285    a6 48          ld     A,#0x48[0K
+0x08287    cd 81 ba       call   0x81ba [0K
+0x0828a    a6 69          ld     A,#0x69[0K
+0x0828c    cd 81 ba       call   0x81ba [0K
+0x0828f    a6 0d          ld     A,#0x0d[0K
+0x08291    cd 81 ba       call   0x81ba [0K
+0x08294    a6 0a          ld     A,#0x0a[0K
+0x08296    cd 81 ba       call   0x81ba [0K
+0x08299    72 12 7f 60    bset   0x7f60,#1[0K
+0x0829d    72 16 50 5a    bset   0x505a,#3[0K
+
+0x082a1    :
+0x082a1    8f             wfi[0K
+0x082a2    cc 82 a1       jp     0x82a1 [0K
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/serial/Makefile sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/serial/Makefile
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/serial/Makefile	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/serial/Makefile	2022-01-24 11:09:43.000000000 +0000
@@ -0,0 +1,15 @@
+OUTPUTS = stdout
+
+
+# Ignore changes in white space. The field widths for labels
+# depends on the length of the longest label. This will be
+# different for different simulators and should not be assumed
+# to be constant for any given simulator.
+DIFF_OPTS += -b
+
+
+stdout:	xconnect.ihx xconnect.vars test.cmd
+	@$(call run-sim, -t S003 '$(srcdir)/xconnect.ihx' -e 'exec "$(srcdir)/xconnect.vars"')
+
+
+include test-lib.mk
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/serial/test.cmd sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/serial/test.cmd
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/serial/test.cmd	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/serial/test.cmd	2022-01-24 11:09:43.000000000 +0000
@@ -0,0 +1,11 @@
+# Set some core vars
+var CLK_PCKENR1       rom[0x50c7][7:0]
+var CLK_PCKENR1_UART1 rom[0x50c7].3
+var CLK_PCKENR1_TIM2  rom[0x50c7].5
+var UART1_SR          rom[0x5230]
+var UART1_SR_TXE      rom[0x5230].7
+var UART1_SR_TC       rom[0x5230].6
+var UART1_SR_RXNE     rom[0x5230].5
+
+dump rom[0x00] 0x3d
+dc 0x8000 0x082a4 
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/serial/xconnect.ihx sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/serial/xconnect.ihx
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/serial/xconnect.ihx	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/serial/xconnect.ihx	2022-01-24 11:09:43.000000000 +0000
@@ -0,0 +1,32 @@
+:20800000820081DB8200807C8200807C8200807C8200807C8200807C8200807C8200807C10
+:208020008200807C8200807C8200807C8200807C8200807C8200807C8200807C8200807C50
+:208040008200807C8200807C8200807C8200807C8200807C8200807C8200807C8200807C30
+:1D8060008200807C8200807C8200807C8200807C8200807C8200807C8200807C8011
+:048050008200807DAD
+:20807D004B00869BC65231CE003AD700265A2A03AE000FCF003A720053000C721A50C772F6
+:08809D0010530072105306801D
+:04804C00820080A589
+:2080A5004B08869B720C523020CE0038C300362713CE0038D600015A2A03AE001FCF0038B6
+:0E80C500C7523180721F523580721D523080BA
+:04800000820081DB9E
+:2081DB00350050C6350050C7350050CAAE00082707724F00355A26F9AE00002709D681DA3C
+:2081FB00D7003D5A26F7C67F74A4F3AA04C77F74C67F74A4CFAA00C77F74C67F73A4F3AA98
+:20821B000CC77F7335205234352C523535005236350B523335085232721650C7721B5234C6
+:20823B00350F003C350F003A35FF002135FF00237214501172145012721550137214500FDB
+:20825B00721750117217501272165013C650A1A4FCAA02C750A13500530E3500530F358B9B
+:0A827B0053107215530072105303E4
+:04802000820080D387
+:2080D3004B28869B72175013350A002335FF0025720053000C721A50C77210530072105334
+:0280F300068005
+:04803C00820080F549
+:2080F5004B28869B72115304C600212B1F725A00212B137256002225079D7215500F203EAA
+:208115007214500F20387214500F2032CE003CC3003A271C7215500FCE003CD600265A2A1C
+:2081350003AE000FCF003CC7002235080021200EC600232A0C72115300721B50C780C6000B
+:20815500232B237207501008725A0025725A0025725C00254AC700232B1A271DA10A26074E
+:2081750072590025250E807259002572560024725F0025807216501380C600248A9BCE00AD
+:2081950038C30036260E720F523009C75231721E5235200FCE0036D700015A2A03AE001F99
+:0581B500CF00368680BA
+:20828500A648CD81BAA669CD81BAA60DCD81BAA60ACD81BA72127F607216505A8FCC82A146
+:2081BA00CE003AD700265A2A03AE000FCF003A720053000C721A50C772105300721053062F
+:0181DA008123
+:00000001FF
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/serial/xconnect.vars sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/serial/xconnect.vars
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/serial/xconnect.vars	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/serial/xconnect.vars	2022-01-24 11:09:43.000000000 +0000
@@ -0,0 +1,33 @@
+var __interrupt_vect rom[0x8000]
+var _isr_unused rom[0x807c]
+var tx_bit_1 rom[0x8115]
+var tx_stop rom[0x811b]
+var tx_done rom[0x8121]
+var tx_idle rom[0x8145]
+var rx rom[0x8153]
+var rx_have_a rom[0x8156]
+var rx_active rom[0x8158]
+var rx_sample_1 rom[0x8165]
+var rx_next_bit rom[0x8169]
+var rx_done rom[0x817b]
+var rx_data rom[0x817c]
+var rx_idle rom[0x8189]
+var rx_stop rom[0x818e]
+var vuart_tx_put rom[0x81ba]
+var _boot rom[0x81db]
+var forever rom[0x82a1]
+var uart1_tx_buf rom[0x1]
+var vuart_tx_state rom[0x21]
+var vuart_tx rom[0x22]
+var vuart_rx_state rom[0x23]
+var vuart_rx rom[0x24]
+var vuart_rx_bit rom[0x25]
+var vuart_tx_buf rom[0x26]
+var uart1_tx_w rom[0x36]
+var uart1_tx_r rom[0x38]
+var vuart_tx_w rom[0x3a]
+var vuart_tx_r rom[0x3c]
+var IRQ_EXTI3 rom[0x80d3]
+var IRQ_TIM2 rom[0x80f5]
+var IRQ_UART1_TX rom[0x80a5]
+var IRQ_UART1_RX rom[0x807d]
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/serial.c sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/serial.c
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/serial.c	2018-12-18 08:22:48.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/serial.c	1970-01-01 00:00:00.000000000 +0000
@@ -1,114 +0,0 @@
-#include 
-
-#include "stm8.h"
-
-#include "serial.h"
-
-extern volatile unsigned char *sif;
-
-int
-putchar(int c)
-{
-  while(!(USART->sr & USART_SR_TXE));
-  
-  USART->dr = c;
-  return c;
-}
-
-volatile uint8_t rx_buf[UART_BUF_SIZE];
-volatile uint8_t first_free= 0;
-volatile uint8_t last_used= 0;
-
-unsigned char
-serial_nuof_received()
-{
-  if (first_free == last_used)
-    return 0;
-  else if (first_free > last_used)
-    return first_free - last_used;
-  else
-    return UART_BUF_SIZE - (last_used - first_free);
-}
-
-void isr_rx(void) __interrupt(USART_RX_IRQ)
-{
-  volatile uint8_t d;
-  if (USART->sr & USART_SR_RXNE)
-    {
-      uint8_t n;
-      d= USART->dr;
-      n= (first_free+1)%UART_BUF_SIZE;
-      *sif= 'p';*sif= '|';
-      *sif= 'p';*sif= d;
-      *sif= 'p';*sif= '|';
-      if (n != last_used)
-	{
-	  rx_buf[first_free]= d;
-	  first_free= n;
-	}
-      else
-	{
-	  *sif= 'p';*sif= '*';
-	  *sif= 'p';*sif= d;
-	  *sif= 'p';*sif= '*';
-	}
-      d= serial_nuof_received();
-      *sif= 'p';*sif= '/';
-      *sif= 'p';*sif= d+'0';
-      *sif= 'p';*sif= '/';
-    }
-}
-
-char
-serial_received()
-{
-  //return UART2_SR & UART_SR_RXNE;
-  return first_free != last_used;
-}
-
-char getchar()
-{
-  uint8_t o, nr;
-  while (!serial_received())
-    ;
-  o= last_used;
-  last_used= (last_used+1)%UART_BUF_SIZE;
-  o= rx_buf[o];
-  nr= serial_nuof_received();
-  *sif= 'p';*sif= '@';
-  *sif= 'p';*sif= nr+'0';
-  *sif= 'p';*sif= '@';
-  return o;
-}
-
-void
-print_cx1(char c)
-{
-  if (c > 9)
-    printf("%c", c-10+'A');
-  else
-    printf("%c", c+'0');
-}
-
-void
-print_cx2(char c)
-{
-  int d;
-  d= (c>>4) & 0xf;
-  print_cx1(d);
-  d= c & 0xf;
-  print_cx1(d);
-}
-
-void
-print_ix4(int i)
-{
-  int d= i>>12;
-  print_cx1(d);
-  d= (i>>8) & 0xf;
-  print_cx1(d);
-  d= (i>>4) & 0xf;
-  print_cx1(d);
-  d= i & 0xf;
-  print_cx1(d);
-}
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/serial.h sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/serial.h
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/serial.h	2018-12-18 08:22:48.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/serial.h	1970-01-01 00:00:00.000000000 +0000
@@ -1,16 +0,0 @@
-#ifndef SERIAL_HEADER
-#define SERIAL_HEADER
-
-#include "stm8.h"
-
-#define UART_BUF_SIZE 8
-
-extern void isr_rx(void) __interrupt(USART_RX_IRQ);
-
-extern char serial_received();
-
-extern void print_cx1(char c);
-extern void print_cx2(char c);
-extern void print_ix4(int i);
-
-#endif
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/sertest.c sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/sertest.c
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/sertest.c	2018-12-18 08:22:48.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/sertest.c	1970-01-01 00:00:00.000000000 +0000
@@ -1,51 +0,0 @@
-// Source code under CC0 1.0
-#include 
-#include 
-
-#include "stm8.h"
-
-#include "serial.h"
-
-volatile unsigned char *sif= (unsigned char *)0x7fff;
-
-
-void main(void)
-{
-  unsigned long i = 0;
-  unsigned int a= 0;
-
-  CLK->ckdivr = 0x00; // Set the frequency to 16 MHz
-  CLK->pckenr1 = 0xFF; // Enable peripherals
-
-  // USART2
-  // TX: PD5, CN4.10
-  // RX: PD6, CN4.11
-  USART->cr2 = USART_CR2_TEN | USART_CR2_REN; // Allow TX and RX
-  USART->cr3 &= ~(USART_CR3_STOP1 | USART_CR3_STOP2); // 1 stop bit
-  USART->brr2 = 0x03;
-  USART->brr1 = 0x68; // 9600 baud
-
-  USART->cr2|= USART_CR2_RIEN;
-  EI;
-
-  for(;;)
-    {
-      i++;
-      if (serial_received())
-	{
-	  char c= getchar();
-	  if (c == '*')
-	    {
-	      printf("0x%04x\n", a);
-	    }
-	  printf("%c", c);
-	  i= 0;
-	}
-      if (i > 147456*2)
-	{
-	  printf("tick %u 0x%04x Hello World!\n", a, a);
-	  i= 0;
-	  a++;
-	}
-    }
-}
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/sertest.mk sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/sertest.mk
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/sertest.mk	2018-01-25 13:48:09.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/sertest.mk	1970-01-01 00:00:00.000000000 +0000
@@ -1,3 +0,0 @@
-DEVICES		= LDISC SDISC
-
-OTHERS		= serial
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/sl.c sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/sl.c
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/sl.c	2017-02-03 18:14:56.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/sl.c	1970-01-01 00:00:00.000000000 +0000
@@ -1,59 +0,0 @@
-// Source code under CC0 1.0
-#include 
-#include 
-
-#define PC_DDR	(*(volatile uint8_t *)0x500c)
-#define PC_CR1	(*(volatile uint8_t *)0x500d)
-
-#define CLK_DIVR	(*(volatile uint8_t *)0x50c0)
-#define CLK_PCKENR1	(*(volatile uint8_t *)0x50c3)
-
-#define USART1_SR	(*(volatile uint8_t *)0x5230)
-#define USART1_DR	(*(volatile uint8_t *)0x5231)
-#define USART1_BRR1	(*(volatile uint8_t *)0x5232)
-#define USART1_BRR2	(*(volatile uint8_t *)0x5233)
-#define USART1_CR2	(*(volatile uint8_t *)0x5235)
-#define USART1_CR3	(*(volatile uint8_t *)0x5236)
-
-#define USART_CR2_TEN (1 << 3)
-#define USART_CR3_STOP2 (1 << 5)
-#define USART_CR3_STOP1 (1 << 4)
-#define USART_SR_TXE (1 << 7)
-
-int putchar(int c)
-{
-  while(!(USART1_SR & USART_SR_TXE));
-
-  USART1_DR = c;
-  return c;
-}
-
-char dbuf[10];
-char xbuf[10];
-
-void main(void)
-{
-  unsigned long i = 0;
-  int a= 0;
-	
-  CLK_DIVR = 0x00; // Set the frequency to 16 MHz
-  CLK_PCKENR1 = 0xFF; // Enable peripherals
-
-  PC_DDR = 0x08; // Put TX line on
-  PC_CR1 = 0x08;
-
-  USART1_CR2 = USART_CR2_TEN; // Allow TX and RX
-  USART1_CR3 &= ~(USART_CR3_STOP1 | USART_CR3_STOP2); // 1 stop bit
-  USART1_BRR2 = 0x03; USART1_BRR1 = 0x68; // 9600 baud
-
-  sprintf(dbuf, "%d", 1234);
-  printf("%s\n", dbuf);
-  sprintf(xbuf, "%x", 0x1234);
-  printf("%s\n", xbuf);
-  for(;;)
-    {
-      printf("Hello World %d %x!\n", a, a);
-      for(i = 0; i < 147456; i++); // Sleep
-      a++;
-    }
-}
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/sled.c sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/sled.c
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/sled.c	2019-03-07 08:39:41.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/sled.c	1970-01-01 00:00:00.000000000 +0000
@@ -1,44 +0,0 @@
-// Source code under CC0 1.0
-#include 
-
-#include "stm8.h"
-
-#define PD GPIOD
-
-unsigned int clock(void)
-{
-  unsigned char h = TIM1->cntrh;
-  unsigned char l = TIM1->cntrl;
-  return((unsigned int)(h) << 8 | l);
-}
-
-unsigned int last= 0;
-
-void main(void)
-{
-  unsigned int now;
-  CLK->ckdivr = 0x00; // Set the frequency to 16 MHz
-
-  // Configure timer
-  // 1000 ticks per second
-  TIM1->pscrh = 0x3e;
-  TIM1->pscrl = 0x80;
-  // Enable timer
-  TIM1->cr1 = 0x01;
-  
-  PD->ddr = 0x01;
-  PD->cr1 = 0x01;
-
-  for(;;)
-    {
-      now= clock();
-      if (now - last > 500)
-	{
-	  if (PD->odr & 1)
-	    PD->odr&= ~1;
-	  else
-	    PD->odr|= 1;
-	  last= now;
-	}
-    }
-}
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/sled.mk sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/sled.mk
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/sled.mk	2018-01-25 13:48:09.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/sled.mk	1970-01-01 00:00:00.000000000 +0000
@@ -1 +0,0 @@
-DEVICES		= SDISC
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/sl.mk sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/sl.mk
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/sl.mk	2018-01-25 13:48:09.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/sl.mk	1970-01-01 00:00:00.000000000 +0000
@@ -1 +0,0 @@
-DEVICES		= LDISC
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/ss.c sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/ss.c
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/ss.c	2017-02-03 18:14:56.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/ss.c	1970-01-01 00:00:00.000000000 +0000
@@ -1,46 +0,0 @@
-// Source code under CC0 1.0
-#include 
-#include 
-
-#define CLK_DIVR	(*(volatile uint8_t *)0x50c6)
-#define CLK_PCKENR1	(*(volatile uint8_t *)0x50c7)
-
-#define UART2_SR	(*(volatile uint8_t *)0x5240)
-#define UART2_DR	(*(volatile uint8_t *)0x5241)
-#define UART2_BRR1	(*(volatile uint8_t *)0x5242)
-#define UART2_BRR2	(*(volatile uint8_t *)0x5243)
-#define UART2_CR2	(*(volatile uint8_t *)0x5245)
-#define UART2_CR3	(*(volatile uint8_t *)0x5246)
-
-#define UART_CR2_TEN (1 << 3)
-#define UART_CR3_STOP2 (1 << 5)
-#define UART_CR3_STOP1 (1 << 4)
-#define UART_SR_TXE (1 << 7)
-
-int putchar(int c)
-{
-  while(!(UART2_SR & UART_SR_TXE));
-  
-  UART2_DR = c;
-  return c;
-}
-
-void main(void)
-{
-  unsigned long i = 0;
-  int a= 0;
-  
-  CLK_DIVR = 0x00; // Set the frequency to 16 MHz
-  CLK_PCKENR1 = 0xFF; // Enable peripherals
-
-  UART2_CR2 = UART_CR2_TEN; // Allow TX and RX
-  UART2_CR3 &= ~(UART_CR3_STOP1 | UART_CR3_STOP2); // 1 stop bit
-  UART2_BRR2 = 0x03; UART2_BRR1 = 0x68; // 9600 baud
-
-  for(;;)
-    {
-      printf("Hello World %d %x!\n", a, a);
-      for(i = 0; i < 147456; i++); // Sleep
-      a++;
-    }
-}
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/ss.mk sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/ss.mk
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/ss.mk	2018-01-25 13:48:09.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/ss.mk	1970-01-01 00:00:00.000000000 +0000
@@ -1 +0,0 @@
-DEVICES		= SDISC
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/stim.c sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/stim.c
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/stim.c	2018-01-25 13:48:09.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/stim.c	1970-01-01 00:00:00.000000000 +0000
@@ -1,66 +0,0 @@
-// Source code under CC0 1.0
-#include 
-
-#include "stm8.h"
-
-#define PD GPIOD
-
-volatile unsigned long clk= 0;
-
-void tim1_up_isr(void) __interrupt(TIM1_UP_IRQ)
-{
-  TIM1->sr1&= ~TIM_SR1_UIF;
-  clk++;
-  //PE->odr^= 0x80;
-}
-
-unsigned int clock(void)
-{
-  unsigned long c;
-  TIM1->ier&= ~TIM_IER_UIE;
-  c= clk;
-  TIM1->ier|= TIM_IER_UIE;
-  return c;
-}
-
-unsigned long last_tick1= 0;
-
-void tick1(unsigned long c)
-{
-  //unsigned long c= clock();
-  if (c - last_tick1 > 500)
-    {
-      last_tick1= c;
-      PD->odr^= 1;
-    }
-}
-
-void main(void)
-{
-  CLK->ckdivr = 0x00; // Set the frequency to 16 MHz
-
-  // Configure timer
-  // 1000 ticks per second
-  TIM1->pscrh = 0; //0x3e;
-  TIM1->pscrl = 0; //0x80;
-  // Update event at every 1 ms (16000 count)
-  #define AR 16000
-  TIM1->arrh = AR >> 8;
-  TIM1->arrl = AR & 0xff;
-  // Enable timer
-  TIM1->cr1 = 0x01;
-  
-  // Enable interrupt for timer1 update
-  TIM1->ier|= TIM_IER_UIE;
-  EI;
-
-  // Configure pin
-  PD->ddr = 0x01;
-  PD->cr1 = 0x01;
-
-  for(;;)
-    {
-      unsigned long c= clock();
-      tick1(c);
-    }
-}
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/stim.mk sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/stim.mk
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/stim.mk	2018-01-25 13:48:09.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/stim.mk	1970-01-01 00:00:00.000000000 +0000
@@ -1 +0,0 @@
-DEVICES		= SDISC
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/stm8-cycles/baseline/stdout sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/stm8-cycles/baseline/stdout
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/stm8-cycles/baseline/stdout	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/stm8-cycles/baseline/stdout	2022-02-08 21:21:05.000000000 +0000
@@ -0,0 +1,848 @@
+uCsim, Copyright (C)  Daniel Drotos.
+uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+This is free software, and you are welcome to redistribute it
+under certain conditions; type `show c' for details.
+# We don't want auto-generated labels in the output.
+set option analyzer false
+
+step
+
+Stop at 0x008088: (109) stepped 3 ticks
+V-IHINZC  Flags= 0x28  40 (  A= 0x00   0 .
+0-101000  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17ff [SP+1]= 00   0 .  Limit= 0x1500
+0x08088  ? 20 02          jra    0x808c[0K
+F 0x008088
+
+# The pipelined examples from PM0044 5.4 are run with fold-on-flush off
+# so that they can be compared with the documentation easily.
+set hw cpu pipetrace fold off
+
+step
+
+Stop at 0x00808c: (109) stepped 2 ticks
+V-IHINZC  Flags= 0x28  40 (  A= 0x00   0 .
+0-101000  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17ff [SP+1]= 00   0 .  Limit= 0x1500
+0x0808c  ? 92 ce 50       ldw    X,[0x50.w][0K
+F 0x00808c
+set hw cpu pipetrace title "PM0044 5.4 Conventions, table 3"
+set hw cpu pipetrace start "out/test.table3.html"
+set hw cpu pipetrace data "Errata"
+set hw cpu pipetrace data ""
+set hw cpu pipetrace data "The LDW shown in PM0044 table 3 is missing a decode cycle."
+set hw cpu pipetrace data "    
"
+set hw cpu pipetrace data "    (Confirmed on HW)"
+set hw cpu pipetrace data "    "
+set hw cpu pipetrace data "The ADDW shown in PM0044 table 3 has one too many decode cycles."
+set hw cpu pipetrace data "    
"
+set hw cpu pipetrace data "    (Confirmed on HW)"
+set hw cpu pipetrace data "    "
+set hw cpu pipetrace data "The LD shown in PM0044 table 3 is missing a decode cycle."
+set hw cpu pipetrace data ""
+step 3
+
+Stop at 0x008095: (109) stepped 12 ticks
+V-IHINZC  Flags= 0x2a  42 *  A= 0x00   0 .
+0-101010  X= 0x0014  20 .    Y= 0x0000   0 .
+SP= 0x17ff [SP+1]= 00   0 .  Limit= 0x1500
+0x08095  ? 20 01          jra    0x8098[0K
+F 0x008095
+Simulated 12 ticks [ELIDED]
+Host usage: [ELIDED]
+set hw cpu pipetrace stop
+
+step
+
+Stop at 0x008098: (109) stepped 1 ticks
+V-IHINZC  Flags= 0x2a  42 *  A= 0x00   0 .
+0-101010  X= 0x0014  20 .    Y= 0x0000   0 .
+SP= 0x17ff [SP+1]= 00   0 .  Limit= 0x1500
+0x08098  ? 40             neg    A[0K
+F 0x008098
+set hw cpu pipetrace title "PM0044 5.4.1 Optimized pipeline example - execution from flash, table 6"
+set hw cpu pipetrace start "out/test.table6.html"
+step 12
+
+Stop at 0x0080b0: (109) stepped 13 ticks
+V-IHINZC  Flags= 0x2d  45 -  A= 0xf0 240 .
+0-101101  X= 0x001e  30 .    Y= 0x0000   0 .
+SP= 0x17ff [SP+1]= 00   0 .  Limit= 0x1500
+0x080b0  ? ae 00 15       ldw    X,#0x0015[0K
+F 0x0080b0
+Simulated 13 ticks [ELIDED]
+Host usage: [ELIDED]
+set hw cpu pipetrace stop
+
+break 0x0100
+Breakpoint 1 at 0x000100: 0x00100 F? 0b             UNKNOWN/INVALID (cond="")
+cont
+Simulation started, PC=0x0080b0
+
+Stop at 0x000100: (104) Breakpoint
+V-IHINZC  Flags= 0x2b  43 +  A= 0x20  32  
+0-101011  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17fd [SP+1]= 80 128 .  Limit= 0x1500
+0x00100 F? 20 02          jra    0x0104[0K
+F 0x000100
+Simulated 130 ticks [ELIDED]
+Host usage: [ELIDED]
+
+step
+
+Stop at 0x000104: (109) stepped 6 ticks
+V-IHINZC  Flags= 0x2b  43 +  A= 0x20  32  
+0-101011  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17fd [SP+1]= 80 128 .  Limit= 0x1500
+0x00104  ? 40             neg    A[0K
+F 0x000104
+set hw cpu pipetrace title "PM0044 5.4.2 Optimize pipeline example - execution from RAM, table 8"
+set hw cpu pipetrace start "out/test.table8.html"
+step 10
+
+Stop at 0x000114: (109) stepped 20 ticks
+V-IHINZC  Flags= 0x2d  45 -  A= 0xf0 240 .
+0-101101  X= 0x001e  30 .    Y= 0x0000   0 .
+SP= 0x17fd [SP+1]= 80 128 .  Limit= 0x1500
+0x00114  ? 81             ret[0K
+F 0x000114
+Simulated 20 ticks [ELIDED]
+Host usage: [ELIDED]
+set hw cpu pipetrace stop
+step
+
+Stop at 0x0080c0: (109) stepped 6 ticks
+V-IHINZC  Flags= 0x2d  45 -  A= 0xf0 240 .
+0-101101  X= 0x001e  30 .    Y= 0x0000   0 .
+SP= 0x17ff [SP+1]= 00   0 .  Limit= 0x1500
+0x080c0  ? 20 02          jra    0x80c4[0K
+F 0x0080c0
+
+
+step
+
+Stop at 0x0080c4: (109) stepped 3 ticks
+V-IHINZC  Flags= 0x2d  45 -  A= 0xf0 240 .
+0-101101  X= 0x001e  30 .    Y= 0x0000   0 .
+SP= 0x17ff [SP+1]= 00   0 .  Limit= 0x1500
+0x080c4  ? 4c             inc    A[0K
+F 0x0080c4
+set hw cpu pipetrace title "PM0044 5.4.3 Pipeline with Call/Jump, table 10"
+set hw cpu pipetrace start "out/test.table10.html"
+set hw cpu pipetrace data "PM0044 table 10 shows a fetch stall in the first execution cycle"
+set hw cpu pipetrace data "of the call (cycle 7) however it should be possible for a fetch"
+set hw cpu pipetrace data "to take place since pushing the return address only busies the"
+set hw cpu pipetrace data "data bus (and STM8 is a Harvard architecture with unified address"
+set hw cpu pipetrace data "space so the data and program are separate buses)."
+set hw cpu pipetrace data "Also note that since the flush happens on the last execute cycle"
+set hw cpu pipetrace data "of the call (unlike the jp) there is no overlap and we mark"
+set hw cpu pipetrace data "the following cycle as a decode stall. Technically this is correct"
+set hw cpu pipetrace data "but table 10 does not and says the call takes 3 cycles which"
+set hw cpu pipetrace data "ignores the unavoidable stall cycle. The later instruction documentation"
+set hw cpu pipetrace data "for call says it takes 4 cycles which is presumed to include the"
+set hw cpu pipetrace data "stall cycle that follows it."
+step 5
+
+Stop at 0x0080d9: (109) stepped 10 ticks
+V-IHINZC  Flags= 0x29  41 )  A= 0x0f  15 .
+0-101001  X= 0x001f  31 .    Y= 0x0000   0 .
+SP= 0x17fd [SP+1]= 80 128 .  Limit= 0x1500
+0x080d9  ? 4f             clr    A[0K
+F 0x0080d9
+Simulated 10 ticks [ELIDED]
+Host usage: [ELIDED]
+set hw cpu pipetrace stop
+
+
+step 4
+
+Stop at 0x0080e0: (109) stepped 4 ticks
+V-IHINZC  Flags= 0x2b  43 +  A= 0x00   0 .
+0-101011  X= 0x001f  31 .    Y= 0x0000   0 .
+SP= 0x17fd [SP+1]= 80 128 .  Limit= 0x1500
+0x080e0  ? 52 14          sub    SP,#0x14[0K
+F 0x0080e0
+Simulated 4 ticks [ELIDED]
+Host usage: [ELIDED]
+set hw cpu pipetrace title "PM0044 5.4.4 Pipeline stalled, table 12"
+set hw cpu pipetrace start "out/test.table12.html"
+set hw cpu pipetrace data "Errata"
+set hw cpu pipetrace data ""
+set hw cpu pipetrace data "Table 12 shows the BTJT as taking 1 decode, 2 execute cycles but the"
+set hw cpu pipetrace data "    later documention for the instruction implies the second execution"
+set hw cpu pipetrace data "    cycle is only used if the branch is taken - and this isn't."
+set hw cpu pipetrace data "    "
+set hw cpu pipetrace data "Table 12 has a jump in time (cycles) from 4 straight to 7."
+set hw cpu pipetrace data "    "
+set hw cpu pipetrace data "The last instruction is shown one cycle early in table 12. The decode stall"
+set hw cpu pipetrace data "    should line up with the execution cycle of the previous instruction"
+set hw cpu pipetrace data "    as the description above the table says."
+set hw cpu pipetrace data "    "
+set hw cpu pipetrace data ""
+step 7
+
+Stop at 0x0080fb: (109) stepped 11 ticks
+V-IHINZC  Flags= 0x2c  44 ,  A= 0xcd 205 .
+0-101100  X= 0x001f  31 .    Y= 0x0001   1 .
+SP= 0x17e9 [SP+1]= 9d 157 .  Limit= 0x1500
+0x080fb  ? 20 03          jra    0x8100[0K
+F 0x0080fb
+Simulated 11 ticks [ELIDED]
+Host usage: [ELIDED]
+set hw cpu pipetrace stop
+
+
+# Everything else needs to be folded on flush or it could go sideways very quickly.
+set hw cpu pipetrace fold on
+
+set hw cpu pipetrace title "DIV tests - available ST docs simply say '2-17 cycles'"
+set hw cpu pipetrace start "out/test.div.html"
+set hw cpu pipetrace data "The stated cycle count would seem to imply binary long division and"
+set hw cpu pipetrace data "   this is how the STM8 emulator in ucsim currently treats div for."
+set hw cpu pipetrace data "   cycle counting. However the cycles measured on actual hardware
+Unterminated string
+Unterminated string
+Unterminated string
+set hw cpu pipetrace data "   suggest this is not correct."
+set hw cpu pipetrace data ""
+
+set hw cpu pipetrace pause
+step
+
+Stop at 0x008100: (109) stepped 1 ticks
+V-IHINZC  Flags= 0x2c  44 ,  A= 0xcd 205 .
+0-101100  X= 0x001f  31 .    Y= 0x0001   1 .
+SP= 0x17e9 [SP+1]= 9d 157 .  Limit= 0x1500
+0x08100  ? ae 80 00       ldw    X,#0x8000[0K
+F 0x008100
+set hw cpu pipetrace resume
+step 3
+
+Stop at 0x008106: (109) stepped 7 ticks
+V-IHINZC  Flags= 0x2a  42 *  A= 0x00   0 .
+0-101010  X= 0x0100 256 .    Y= 0x0001   1 .
+SP= 0x17e9 [SP+1]= 9d 157 .  Limit= 0x1500
+0x08106  ? 20 00          jra    0x8108[0K
+F 0x008106
+Simulated 7 ticks [ELIDED]
+Host usage: [ELIDED]
+set hw cpu pipetrace pause
+step
+
+Stop at 0x008108: (109) stepped 1 ticks
+V-IHINZC  Flags= 0x2a  42 *  A= 0x00   0 .
+0-101010  X= 0x0100 256 .    Y= 0x0001   1 .
+SP= 0x17e9 [SP+1]= 9d 157 .  Limit= 0x1500
+0x08108  ? ae 80 00       ldw    X,#0x8000[0K
+F 0x008108
+set hw cpu pipetrace resume
+step 3
+
+Stop at 0x00810e: (109) stepped 7 ticks
+V-IHINZC  Flags= 0x2a  42 *  A= 0x00   0 .
+0-101010  X= 0x0200 512 .    Y= 0x0001   1 .
+SP= 0x17e9 [SP+1]= 9d 157 .  Limit= 0x1500
+0x0810e  ? 20 00          jra    0x8110[0K
+F 0x00810e
+Simulated 7 ticks [ELIDED]
+Host usage: [ELIDED]
+set hw cpu pipetrace pause
+step
+
+Stop at 0x008110: (109) stepped 1 ticks
+V-IHINZC  Flags= 0x2a  42 *  A= 0x00   0 .
+0-101010  X= 0x0200 512 .    Y= 0x0001   1 .
+SP= 0x17e9 [SP+1]= 9d 157 .  Limit= 0x1500
+0x08110  ? ae 80 00       ldw    X,#0x8000[0K
+F 0x008110
+set hw cpu pipetrace resume
+step 3
+
+Stop at 0x008116: (109) stepped 7 ticks
+V-IHINZC  Flags= 0x2a  42 *  A= 0x00   0 .
+0-101010  X= 0x0400 1024 .    Y= 0x0001   1 .
+SP= 0x17e9 [SP+1]= 9d 157 .  Limit= 0x1500
+0x08116  ? 20 00          jra    0x8118[0K
+F 0x008116
+Simulated 7 ticks [ELIDED]
+Host usage: [ELIDED]
+set hw cpu pipetrace pause
+step
+
+Stop at 0x008118: (109) stepped 1 ticks
+V-IHINZC  Flags= 0x2a  42 *  A= 0x00   0 .
+0-101010  X= 0x0400 1024 .    Y= 0x0001   1 .
+SP= 0x17e9 [SP+1]= 9d 157 .  Limit= 0x1500
+0x08118  ? ae 80 00       ldw    X,#0x8000[0K
+F 0x008118
+set hw cpu pipetrace resume
+step 3
+
+Stop at 0x00811e: (109) stepped 7 ticks
+V-IHINZC  Flags= 0x2a  42 *  A= 0x00   0 .
+0-101010  X= 0x0800 2048 .    Y= 0x0001   1 .
+SP= 0x17e9 [SP+1]= 9d 157 .  Limit= 0x1500
+0x0811e  ? 20 00          jra    0x8120[0K
+F 0x00811e
+Simulated 7 ticks [ELIDED]
+Host usage: [ELIDED]
+set hw cpu pipetrace pause
+step
+
+Stop at 0x008120: (109) stepped 1 ticks
+V-IHINZC  Flags= 0x2a  42 *  A= 0x00   0 .
+0-101010  X= 0x0800 2048 .    Y= 0x0001   1 .
+SP= 0x17e9 [SP+1]= 9d 157 .  Limit= 0x1500
+0x08120  ? ae 80 00       ldw    X,#0x8000[0K
+F 0x008120
+set hw cpu pipetrace resume
+step 3
+
+Stop at 0x008126: (109) stepped 7 ticks
+V-IHINZC  Flags= 0x2a  42 *  A= 0x00   0 .
+0-101010  X= 0x1000 4096 .    Y= 0x0001   1 .
+SP= 0x17e9 [SP+1]= 9d 157 .  Limit= 0x1500
+0x08126  ? 20 00          jra    0x8128[0K
+F 0x008126
+Simulated 7 ticks [ELIDED]
+Host usage: [ELIDED]
+set hw cpu pipetrace pause
+step
+
+Stop at 0x008128: (109) stepped 1 ticks
+V-IHINZC  Flags= 0x2a  42 *  A= 0x00   0 .
+0-101010  X= 0x1000 4096 .    Y= 0x0001   1 .
+SP= 0x17e9 [SP+1]= 9d 157 .  Limit= 0x1500
+0x08128  ? ae 80 00       ldw    X,#0x8000[0K
+F 0x008128
+set hw cpu pipetrace resume
+step 3
+
+Stop at 0x00812e: (109) stepped 7 ticks
+V-IHINZC  Flags= 0x2a  42 *  A= 0x00   0 .
+0-101010  X= 0x2000 8192 .    Y= 0x0001   1 .
+SP= 0x17e9 [SP+1]= 9d 157 .  Limit= 0x1500
+0x0812e  ? 20 00          jra    0x8130[0K
+F 0x00812e
+Simulated 7 ticks [ELIDED]
+Host usage: [ELIDED]
+set hw cpu pipetrace pause
+step
+
+Stop at 0x008130: (109) stepped 1 ticks
+V-IHINZC  Flags= 0x2a  42 *  A= 0x00   0 .
+0-101010  X= 0x2000 8192 .    Y= 0x0001   1 .
+SP= 0x17e9 [SP+1]= 9d 157 .  Limit= 0x1500
+0x08130  ? ae 80 00       ldw    X,#0x8000[0K
+F 0x008130
+set hw cpu pipetrace resume
+step 3
+
+Stop at 0x008136: (109) stepped 7 ticks
+V-IHINZC  Flags= 0x2a  42 *  A= 0x00   0 .
+0-101010  X= 0x4000 16384 .    Y= 0x0001   1 .
+SP= 0x17e9 [SP+1]= 9d 157 .  Limit= 0x1500
+0x08136  ? 20 00          jra    0x8138[0K
+F 0x008136
+Simulated 7 ticks [ELIDED]
+Host usage: [ELIDED]
+set hw cpu pipetrace pause
+step
+
+Stop at 0x008138: (109) stepped 1 ticks
+V-IHINZC  Flags= 0x2a  42 *  A= 0x00   0 .
+0-101010  X= 0x4000 16384 .    Y= 0x0001   1 .
+SP= 0x17e9 [SP+1]= 9d 157 .  Limit= 0x1500
+0x08138  ? ae 80 00       ldw    X,#0x8000[0K
+F 0x008138
+set hw cpu pipetrace resume
+step 3
+
+Stop at 0x00813e: (109) stepped 7 ticks
+V-IHINZC  Flags= 0x2a  42 *  A= 0x00   0 .
+0-101010  X= 0x8000 32768 .    Y= 0x0001   1 .
+SP= 0x17e9 [SP+1]= 9d 157 .  Limit= 0x1500
+0x0813e  ? 20 00          jra    0x8140[0K
+F 0x00813e
+Simulated 7 ticks [ELIDED]
+Host usage: [ELIDED]
+
+set hw cpu pipetrace pause
+step
+
+Stop at 0x008140: (109) stepped 1 ticks
+V-IHINZC  Flags= 0x2a  42 *  A= 0x00   0 .
+0-101010  X= 0x8000 32768 .    Y= 0x0001   1 .
+SP= 0x17e9 [SP+1]= 9d 157 .  Limit= 0x1500
+0x08140  ? ae 80 00       ldw    X,#0x8000[0K
+F 0x008140
+set hw cpu pipetrace resume
+step 3
+
+Stop at 0x008146: (109) stepped 7 ticks
+V-IHINZC  Flags= 0x2a  42 *  A= 0x00   0 .
+0-101010  X= 0x0100 256 .    Y= 0x0001   1 .
+SP= 0x17e9 [SP+1]= 9d 157 .  Limit= 0x1500
+0x08146  ? 20 00          jra    0x8148[0K
+F 0x008146
+Simulated 7 ticks [ELIDED]
+Host usage: [ELIDED]
+set hw cpu pipetrace pause
+step
+
+Stop at 0x008148: (109) stepped 1 ticks
+V-IHINZC  Flags= 0x2a  42 *  A= 0x00   0 .
+0-101010  X= 0x0100 256 .    Y= 0x0001   1 .
+SP= 0x17e9 [SP+1]= 9d 157 .  Limit= 0x1500
+0x08148  ? ae 40 00       ldw    X,#0x4000[0K
+F 0x008148
+set hw cpu pipetrace resume
+step 3
+
+Stop at 0x00814e: (109) stepped 7 ticks
+V-IHINZC  Flags= 0x2a  42 *  A= 0x00   0 .
+0-101010  X= 0x0080 128 .    Y= 0x0001   1 .
+SP= 0x17e9 [SP+1]= 9d 157 .  Limit= 0x1500
+0x0814e  ? 20 00          jra    0x8150[0K
+F 0x00814e
+Simulated 7 ticks [ELIDED]
+Host usage: [ELIDED]
+set hw cpu pipetrace pause
+step
+
+Stop at 0x008150: (109) stepped 1 ticks
+V-IHINZC  Flags= 0x2a  42 *  A= 0x00   0 .
+0-101010  X= 0x0080 128 .    Y= 0x0001   1 .
+SP= 0x17e9 [SP+1]= 9d 157 .  Limit= 0x1500
+0x08150  ? ae 20 00       ldw    X,#0x2000[0K
+F 0x008150
+set hw cpu pipetrace resume
+step 3
+
+Stop at 0x008156: (109) stepped 7 ticks
+V-IHINZC  Flags= 0x2a  42 *  A= 0x00   0 .
+0-101010  X= 0x0040  64 @    Y= 0x0001   1 .
+SP= 0x17e9 [SP+1]= 9d 157 .  Limit= 0x1500
+0x08156  ? 20 00          jra    0x8158[0K
+F 0x008156
+Simulated 7 ticks [ELIDED]
+Host usage: [ELIDED]
+set hw cpu pipetrace pause
+step
+
+Stop at 0x008158: (109) stepped 1 ticks
+V-IHINZC  Flags= 0x2a  42 *  A= 0x00   0 .
+0-101010  X= 0x0040  64 @    Y= 0x0001   1 .
+SP= 0x17e9 [SP+1]= 9d 157 .  Limit= 0x1500
+0x08158  ? ae 10 00       ldw    X,#0x1000[0K
+F 0x008158
+set hw cpu pipetrace resume
+step 3
+
+Stop at 0x00815e: (109) stepped 7 ticks
+V-IHINZC  Flags= 0x2a  42 *  A= 0x00   0 .
+0-101010  X= 0x0020  32      Y= 0x0001   1 .
+SP= 0x17e9 [SP+1]= 9d 157 .  Limit= 0x1500
+0x0815e  ? 20 00          jra    0x8160[0K
+F 0x00815e
+Simulated 7 ticks [ELIDED]
+Host usage: [ELIDED]
+set hw cpu pipetrace pause
+step
+
+Stop at 0x008160: (109) stepped 1 ticks
+V-IHINZC  Flags= 0x2a  42 *  A= 0x00   0 .
+0-101010  X= 0x0020  32      Y= 0x0001   1 .
+SP= 0x17e9 [SP+1]= 9d 157 .  Limit= 0x1500
+0x08160  ? ae 08 00       ldw    X,#0x0800[0K
+F 0x008160
+set hw cpu pipetrace resume
+step 3
+
+Stop at 0x008166: (109) stepped 7 ticks
+V-IHINZC  Flags= 0x2a  42 *  A= 0x00   0 .
+0-101010  X= 0x0010  16 .    Y= 0x0001   1 .
+SP= 0x17e9 [SP+1]= 9d 157 .  Limit= 0x1500
+0x08166  ? 20 00          jra    0x8168[0K
+F 0x008166
+Simulated 7 ticks [ELIDED]
+Host usage: [ELIDED]
+set hw cpu pipetrace pause
+step
+
+Stop at 0x008168: (109) stepped 1 ticks
+V-IHINZC  Flags= 0x2a  42 *  A= 0x00   0 .
+0-101010  X= 0x0010  16 .    Y= 0x0001   1 .
+SP= 0x17e9 [SP+1]= 9d 157 .  Limit= 0x1500
+0x08168  ? ae 04 00       ldw    X,#0x0400[0K
+F 0x008168
+set hw cpu pipetrace resume
+step 3
+
+Stop at 0x00816e: (109) stepped 7 ticks
+V-IHINZC  Flags= 0x2a  42 *  A= 0x00   0 .
+0-101010  X= 0x0008   8 .    Y= 0x0001   1 .
+SP= 0x17e9 [SP+1]= 9d 157 .  Limit= 0x1500
+0x0816e  ? 20 00          jra    0x8170[0K
+F 0x00816e
+Simulated 7 ticks [ELIDED]
+Host usage: [ELIDED]
+set hw cpu pipetrace pause
+step
+
+Stop at 0x008170: (109) stepped 1 ticks
+V-IHINZC  Flags= 0x2a  42 *  A= 0x00   0 .
+0-101010  X= 0x0008   8 .    Y= 0x0001   1 .
+SP= 0x17e9 [SP+1]= 9d 157 .  Limit= 0x1500
+0x08170  ? ae 02 00       ldw    X,#0x0200[0K
+F 0x008170
+set hw cpu pipetrace resume
+step 3
+
+Stop at 0x008176: (109) stepped 7 ticks
+V-IHINZC  Flags= 0x2a  42 *  A= 0x00   0 .
+0-101010  X= 0x0004   4 .    Y= 0x0001   1 .
+SP= 0x17e9 [SP+1]= 9d 157 .  Limit= 0x1500
+0x08176  ? 20 00          jra    0x8178[0K
+F 0x008176
+Simulated 7 ticks [ELIDED]
+Host usage: [ELIDED]
+set hw cpu pipetrace pause
+step
+
+Stop at 0x008178: (109) stepped 1 ticks
+V-IHINZC  Flags= 0x2a  42 *  A= 0x00   0 .
+0-101010  X= 0x0004   4 .    Y= 0x0001   1 .
+SP= 0x17e9 [SP+1]= 9d 157 .  Limit= 0x1500
+0x08178  ? ae 01 00       ldw    X,#0x0100[0K
+F 0x008178
+set hw cpu pipetrace resume
+step 3
+
+Stop at 0x00817e: (109) stepped 7 ticks
+V-IHINZC  Flags= 0x2a  42 *  A= 0x00   0 .
+0-101010  X= 0x0002   2 .    Y= 0x0001   1 .
+SP= 0x17e9 [SP+1]= 9d 157 .  Limit= 0x1500
+0x0817e  ? 20 00          jra    0x8180[0K
+F 0x00817e
+Simulated 7 ticks [ELIDED]
+Host usage: [ELIDED]
+set hw cpu pipetrace pause
+step
+
+Stop at 0x008180: (109) stepped 1 ticks
+V-IHINZC  Flags= 0x2a  42 *  A= 0x00   0 .
+0-101010  X= 0x0002   2 .    Y= 0x0001   1 .
+SP= 0x17e9 [SP+1]= 9d 157 .  Limit= 0x1500
+0x08180  ? ae 00 80       ldw    X,#0x0080[0K
+F 0x008180
+set hw cpu pipetrace resume
+step 3
+
+Stop at 0x008186: (109) stepped 6 ticks
+V-IHINZC  Flags= 0x2a  42 *  A= 0x00   0 .
+0-101010  X= 0x0001   1 .    Y= 0x0001   1 .
+SP= 0x17e9 [SP+1]= 9d 157 .  Limit= 0x1500
+0x08186  ? 20 00          jra    0x8188[0K
+F 0x008186
+Simulated 6 ticks [ELIDED]
+Host usage: [ELIDED]
+set hw cpu pipetrace pause
+step
+
+Stop at 0x008188: (109) stepped 1 ticks
+V-IHINZC  Flags= 0x2a  42 *  A= 0x00   0 .
+0-101010  X= 0x0001   1 .    Y= 0x0001   1 .
+SP= 0x17e9 [SP+1]= 9d 157 .  Limit= 0x1500
+0x08188  ? ae 00 40       ldw    X,#0x0040[0K
+F 0x008188
+set hw cpu pipetrace resume
+step 3
+
+Stop at 0x00818e: (109) stepped 6 ticks
+V-IHINZC  Flags= 0x28  40 (  A= 0x40  64 @
+0-101000  X= 0x0000   0 .    Y= 0x0001   1 .
+SP= 0x17e9 [SP+1]= 9d 157 .  Limit= 0x1500
+0x0818e  ? 20 00          jra    0x8190[0K
+F 0x00818e
+Simulated 6 ticks [ELIDED]
+Host usage: [ELIDED]
+set hw cpu pipetrace pause
+step
+
+Stop at 0x008190: (109) stepped 1 ticks
+V-IHINZC  Flags= 0x28  40 (  A= 0x40  64 @
+0-101000  X= 0x0000   0 .    Y= 0x0001   1 .
+SP= 0x17e9 [SP+1]= 9d 157 .  Limit= 0x1500
+0x08190  ? ae 00 20       ldw    X,#0x0020[0K
+F 0x008190
+set hw cpu pipetrace resume
+step 3
+
+Stop at 0x008196: (109) stepped 6 ticks
+V-IHINZC  Flags= 0x28  40 (  A= 0x20  32  
+0-101000  X= 0x0000   0 .    Y= 0x0001   1 .
+SP= 0x17e9 [SP+1]= 9d 157 .  Limit= 0x1500
+0x08196  ? 20 00          jra    0x8198[0K
+F 0x008196
+Simulated 6 ticks [ELIDED]
+Host usage: [ELIDED]
+set hw cpu pipetrace pause
+step
+
+Stop at 0x008198: (109) stepped 1 ticks
+V-IHINZC  Flags= 0x28  40 (  A= 0x20  32  
+0-101000  X= 0x0000   0 .    Y= 0x0001   1 .
+SP= 0x17e9 [SP+1]= 9d 157 .  Limit= 0x1500
+0x08198  ? ae 00 10       ldw    X,#0x0010[0K
+F 0x008198
+set hw cpu pipetrace resume
+step 3
+
+Stop at 0x00819e: (109) stepped 6 ticks
+V-IHINZC  Flags= 0x28  40 (  A= 0x10  16 .
+0-101000  X= 0x0000   0 .    Y= 0x0001   1 .
+SP= 0x17e9 [SP+1]= 9d 157 .  Limit= 0x1500
+0x0819e  ? 20 00          jra    0x81a0[0K
+F 0x00819e
+Simulated 6 ticks [ELIDED]
+Host usage: [ELIDED]
+set hw cpu pipetrace pause
+step
+
+Stop at 0x0081a0: (109) stepped 1 ticks
+V-IHINZC  Flags= 0x28  40 (  A= 0x10  16 .
+0-101000  X= 0x0000   0 .    Y= 0x0001   1 .
+SP= 0x17e9 [SP+1]= 9d 157 .  Limit= 0x1500
+0x081a0  ? ae 00 08       ldw    X,#0x0008[0K
+F 0x0081a0
+set hw cpu pipetrace resume
+step 3
+
+Stop at 0x0081a6: (109) stepped 6 ticks
+V-IHINZC  Flags= 0x28  40 (  A= 0x08   8 .
+0-101000  X= 0x0000   0 .    Y= 0x0001   1 .
+SP= 0x17e9 [SP+1]= 9d 157 .  Limit= 0x1500
+0x081a6  ? 20 00          jra    0x81a8[0K
+F 0x0081a6
+Simulated 6 ticks [ELIDED]
+Host usage: [ELIDED]
+set hw cpu pipetrace pause
+step
+
+Stop at 0x0081a8: (109) stepped 1 ticks
+V-IHINZC  Flags= 0x28  40 (  A= 0x08   8 .
+0-101000  X= 0x0000   0 .    Y= 0x0001   1 .
+SP= 0x17e9 [SP+1]= 9d 157 .  Limit= 0x1500
+0x081a8  ? ae 00 04       ldw    X,#0x0004[0K
+F 0x0081a8
+set hw cpu pipetrace resume
+step 3
+
+Stop at 0x0081ae: (109) stepped 6 ticks
+V-IHINZC  Flags= 0x28  40 (  A= 0x04   4 .
+0-101000  X= 0x0000   0 .    Y= 0x0001   1 .
+SP= 0x17e9 [SP+1]= 9d 157 .  Limit= 0x1500
+0x081ae  ? 20 00          jra    0x81b0[0K
+F 0x0081ae
+Simulated 6 ticks [ELIDED]
+Host usage: [ELIDED]
+set hw cpu pipetrace pause
+step
+
+Stop at 0x0081b0: (109) stepped 1 ticks
+V-IHINZC  Flags= 0x28  40 (  A= 0x04   4 .
+0-101000  X= 0x0000   0 .    Y= 0x0001   1 .
+SP= 0x17e9 [SP+1]= 9d 157 .  Limit= 0x1500
+0x081b0  ? ae 00 02       ldw    X,#0x0002[0K
+F 0x0081b0
+set hw cpu pipetrace resume
+step 3
+
+Stop at 0x0081b6: (109) stepped 6 ticks
+V-IHINZC  Flags= 0x28  40 (  A= 0x02   2 .
+0-101000  X= 0x0000   0 .    Y= 0x0001   1 .
+SP= 0x17e9 [SP+1]= 9d 157 .  Limit= 0x1500
+0x081b6  ? 20 00          jra    0x81b8[0K
+F 0x0081b6
+Simulated 6 ticks [ELIDED]
+Host usage: [ELIDED]
+set hw cpu pipetrace pause
+step
+
+Stop at 0x0081b8: (109) stepped 1 ticks
+V-IHINZC  Flags= 0x28  40 (  A= 0x02   2 .
+0-101000  X= 0x0000   0 .    Y= 0x0001   1 .
+SP= 0x17e9 [SP+1]= 9d 157 .  Limit= 0x1500
+0x081b8  ? ae 00 01       ldw    X,#0x0001[0K
+F 0x0081b8
+set hw cpu pipetrace resume
+step 3
+
+Stop at 0x0081be: (109) stepped 6 ticks
+V-IHINZC  Flags= 0x28  40 (  A= 0x01   1 .
+0-101000  X= 0x0000   0 .    Y= 0x0001   1 .
+SP= 0x17e9 [SP+1]= 9d 157 .  Limit= 0x1500
+0x081be  ? 20 00          jra    0x81c0[0K
+F 0x0081be
+Simulated 6 ticks [ELIDED]
+Host usage: [ELIDED]
+set hw cpu pipetrace pause
+step
+
+Stop at 0x0081c0: (109) stepped 1 ticks
+V-IHINZC  Flags= 0x28  40 (  A= 0x01   1 .
+0-101000  X= 0x0000   0 .    Y= 0x0001   1 .
+SP= 0x17e9 [SP+1]= 9d 157 .  Limit= 0x1500
+0x081c0  ? ae 00 00       ldw    X,#0x0000[0K
+F 0x0081c0
+set hw cpu pipetrace resume
+step 3
+
+Stop at 0x0081c6: (109) stepped 6 ticks
+V-IHINZC  Flags= 0x28  40 (  A= 0x00   0 .
+0-101000  X= 0x0000   0 .    Y= 0x0001   1 .
+SP= 0x17e9 [SP+1]= 9d 157 .  Limit= 0x1500
+0x081c6  ? 20 00          jra    0x81c8[0K
+F 0x0081c6
+Simulated 6 ticks [ELIDED]
+Host usage: [ELIDED]
+
+set hw cpu pipetrace pause
+step
+
+Stop at 0x0081c8: (109) stepped 1 ticks
+V-IHINZC  Flags= 0x28  40 (  A= 0x00   0 .
+0-101000  X= 0x0000   0 .    Y= 0x0001   1 .
+SP= 0x17e9 [SP+1]= 9d 157 .  Limit= 0x1500
+0x081c8  ? ae 00 3f       ldw    X,#0x003f[0K
+F 0x0081c8
+set hw cpu pipetrace resume
+step 3
+
+Stop at 0x0081ce: (109) stepped 8 ticks
+V-IHINZC  Flags= 0x2a  42 *  A= 0x07   7 .
+0-101010  X= 0x0007   7 .    Y= 0x0001   1 .
+SP= 0x17e9 [SP+1]= 9d 157 .  Limit= 0x1500
+0x081ce  ? 20 00          jra    0x81d0[0K
+F 0x0081ce
+Simulated 8 ticks [ELIDED]
+Host usage: [ELIDED]
+set hw cpu pipetrace pause
+step
+
+Stop at 0x0081d0: (109) stepped 1 ticks
+V-IHINZC  Flags= 0x2a  42 *  A= 0x07   7 .
+0-101010  X= 0x0007   7 .    Y= 0x0001   1 .
+SP= 0x17e9 [SP+1]= 9d 157 .  Limit= 0x1500
+0x081d0  ? ae 00 40       ldw    X,#0x0040[0K
+F 0x0081d0
+set hw cpu pipetrace resume
+step 3
+
+Stop at 0x0081d6: (109) stepped 7 ticks
+V-IHINZC  Flags= 0x2a  42 *  A= 0x00   0 .
+0-101010  X= 0x0008   8 .    Y= 0x0001   1 .
+SP= 0x17e9 [SP+1]= 9d 157 .  Limit= 0x1500
+0x081d6  ? 20 00          jra    0x81d8[0K
+F 0x0081d6
+Simulated 7 ticks [ELIDED]
+Host usage: [ELIDED]
+set hw cpu pipetrace pause
+step
+
+Stop at 0x0081d8: (109) stepped 1 ticks
+V-IHINZC  Flags= 0x2a  42 *  A= 0x00   0 .
+0-101010  X= 0x0008   8 .    Y= 0x0001   1 .
+SP= 0x17e9 [SP+1]= 9d 157 .  Limit= 0x1500
+0x081d8  ? ae 00 41       ldw    X,#0x0041[0K
+F 0x0081d8
+set hw cpu pipetrace resume
+step 3
+
+Stop at 0x0081de: (109) stepped 7 ticks
+V-IHINZC  Flags= 0x2a  42 *  A= 0x01   1 .
+0-101010  X= 0x0008   8 .    Y= 0x0001   1 .
+SP= 0x17e9 [SP+1]= 9d 157 .  Limit= 0x1500
+0x081de  ? 20 00          jra    0x81e0[0K
+F 0x0081de
+Simulated 7 ticks [ELIDED]
+Host usage: [ELIDED]
+
+set hw cpu pipetrace pause
+step
+
+Stop at 0x0081e0: (109) stepped 1 ticks
+V-IHINZC  Flags= 0x2a  42 *  A= 0x01   1 .
+0-101010  X= 0x0008   8 .    Y= 0x0001   1 .
+SP= 0x17e9 [SP+1]= 9d 157 .  Limit= 0x1500
+0x081e0  ? ae 80 00       ldw    X,#0x8000[0K
+F 0x0081e0
+set hw cpu pipetrace resume
+step 3
+
+Stop at 0x0081e8: (109) stepped 8 ticks
+V-IHINZC  Flags= 0x2a  42 *  A= 0x01   1 .
+0-101010  X= 0x8000 32768 .    Y= 0x0000   0 .
+SP= 0x17e9 [SP+1]= 9d 157 .  Limit= 0x1500
+0x081e8  ? 20 02          jra    0x81ec[0K
+F 0x0081e8
+Simulated 8 ticks [ELIDED]
+Host usage: [ELIDED]
+
+set hw cpu pipetrace stop
+
+
+step 7
+
+Stop at 0x008201: (109) stepped 10 ticks
+V-IHINZC  Flags= 0x28  40 (  A= 0x0a  10 .
+0-101000  X= 0x00ff 255 .    Y= 0x0000   0 .
+SP= 0x17e9 [SP+1]= 9d 157 .  Limit= 0x1500
+0x08201  ? 62             div    X,A[0K
+F 0x008201
+Simulated 10 ticks [ELIDED]
+Host usage: [ELIDED]
+
+set hw cpu pipetrace title "Interrupted div"
+set hw cpu pipetrace start "out/test.int_div.html"
+set hw cpu pipetrace data "(Not currently implemented.)"
+# FIXME: once we have timer interrupts emulated correctly we need to add
+# the interrupt instructions to the following step count.
+#step 4
+step
+
+Stop at 0x008202: (109) stepped 4 ticks
+V-IHINZC  Flags= 0x2a  42 *  A= 0x05   5 .
+0-101010  X= 0x0019  25 .    Y= 0x0000   0 .
+SP= 0x17e9 [SP+1]= 9d 157 .  Limit= 0x1500
+0x08202  ? 20 00          jra    0x8204[0K
+F 0x008202
+set hw cpu pipetrace stop
+
+step
+
+Stop at 0x008204: (109) stepped 1 ticks
+V-IHINZC  Flags= 0x2a  42 *  A= 0x05   5 .
+0-101010  X= 0x0019  25 .    Y= 0x0000   0 .
+SP= 0x17e9 [SP+1]= 9d 157 .  Limit= 0x1500
+0x08204  ? a9 55          adc    A,#0x55[0K
+F 0x008204
+
+set hw cpu pipetrace title "All instructions and addressing modes"
+set hw cpu pipetrace start "out/test.instrs.html"
+set hw cpu pipetrace data "Note that timings given in PM0044 assume a 1 cycle overlap"
+set hw cpu pipetrace data "with the previous instruction and are specified as being"
+set hw cpu pipetrace data "one cycle less than they are in the no prefetch/stall case."
+set hw cpu pipetrace data "Instructions that flush the prefetch buffer such as jumps"
+set hw cpu pipetrace data "prevent the overlap with the following instruction. The cycle"
+set hw cpu pipetrace data "count for these instructions includes the extra cycles for"
+set hw cpu pipetrace data "the unavoidable fetches and stalls that follow them."
+cont
+Simulation started, PC=0x008204
+
+Stop at 0x008e53: (101) Halted
+F 0x008e53
+Simulated 2352 ticks [ELIDED]
+Host usage: [ELIDED]
+set hw cpu pipetrace stop
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/stm8-cycles/baseline/test.div.html sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/stm8-cycles/baseline/test.div.html
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/stm8-cycles/baseline/test.div.html	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/stm8-cycles/baseline/test.div.html	2022-01-18 09:48:32.000000000 +0000
@@ -0,0 +1,473 @@
+
+
+DIV tests - available ST docs simply say '2-17 cycles'
+
+
+
+
+
+
+
+DIV tests - available ST docs simply say '2-17 cycles'
+
+
+    
+    
+    
+    
+    
+    
+    
+    
+    
+Legend
Decode
Execute
Fetch
Flush
Fetch Stall - space in prefetch buffer but bus busy
Decode Stall - bus busy
Decode Stall - insufficient data in prefetch buffer
Decode Stall - read after write
+
+The stated cycle count would seem to imply binary long division and
+   this is how the STM8 emulator in ucsim currently treats div for.
+   cycle counting. However the cycles measured on actual hardware
+   suggest this is not correct.
+
+
+
+    
+        
+        
+        
+        
+    
+    
+        
+    
+ 
0x08100 ldw    X,#0x8000 
0x08103 ld     A,#0x80 
0x08105 div    X,A 
Address Instruction 1 2 3 4 5 6 7 8
+
+
+
+
+    
+        
+        
+        
+        
+    
+    
+        
+    
+ 
0x08108 ldw    X,#0x8000 
0x0810b ld     A,#0x40 
0x0810d div    X,A 
Address Instruction 1 2 3 4 5 6 7 8
+
+
+
+
+    
+        
+        
+        
+        
+    
+    
+        
+    
+ 
0x08110 ldw    X,#0x8000 
0x08113 ld     A,#0x20 
0x08115 div    X,A 
Address Instruction 1 2 3 4 5 6 7 8
+
+
+
+
+    
+        
+        
+        
+        
+    
+    
+        
+    
+ 
0x08118 ldw    X,#0x8000 
0x0811b ld     A,#0x10 
0x0811d div    X,A 
Address Instruction 1 2 3 4 5 6 7 8
+
+
+
+
+    
+        
+        
+        
+        
+    
+    
+        
+    
+ 
0x08120 ldw    X,#0x8000 
0x08123 ld     A,#0x08 
0x08125 div    X,A 
Address Instruction 1 2 3 4 5 6 7 8
+
+
+
+
+    
+        
+        
+        
+        
+    
+    
+        
+    
+ 
0x08128 ldw    X,#0x8000 
0x0812b ld     A,#0x04 
0x0812d div    X,A 
Address Instruction 1 2 3 4 5 6 7 8
+
+
+
+
+    
+        
+        
+        
+        
+    
+    
+        
+    
+ 
0x08130 ldw    X,#0x8000 
0x08133 ld     A,#0x02 
0x08135 div    X,A 
Address Instruction 1 2 3 4 5 6 7 8
+
+
+
+
+    
+        
+        
+        
+        
+    
+    
+        
+    
+ 
0x08138 ldw    X,#0x8000 
0x0813b ld     A,#0x01 
0x0813d div    X,A 
Address Instruction 1 2 3 4 5 6 7 8
+
+
+
+
+    
+        
+        
+        
+        
+    
+    
+        
+    
+ 
0x08140 ldw    X,#0x8000 
0x08143 ld     A,#0x80 
0x08145 div    X,A 
Address Instruction 1 2 3 4 5 6 7 8
+
+
+
+
+    
+        
+        
+        
+        
+    
+    
+        
+    
+ 
0x08148 ldw    X,#0x4000 
0x0814b ld     A,#0x80 
0x0814d div    X,A 
Address Instruction 1 2 3 4 5 6 7 8
+
+
+
+
+    
+        
+        
+        
+        
+    
+    
+        
+    
+ 
0x08150 ldw    X,#0x2000 
0x08153 ld     A,#0x80 
0x08155 div    X,A 
Address Instruction 1 2 3 4 5 6 7 8
+
+
+
+
+    
+        
+        
+        
+        
+    
+    
+        
+    
+ 
0x08158 ldw    X,#0x1000 
0x0815b ld     A,#0x80 
0x0815d div    X,A 
Address Instruction 1 2 3 4 5 6 7 8
+
+
+
+
+    
+        
+        
+        
+        
+    
+    
+        
+    
+ 
0x08160 ldw    X,#0x0800 
0x08163 ld     A,#0x80 
0x08165 div    X,A 
Address Instruction 1 2 3 4 5 6 7 8
+
+
+
+
+    
+        
+        
+        
+        
+    
+    
+        
+    
+ 
0x08168 ldw    X,#0x0400 
0x0816b ld     A,#0x80 
0x0816d div    X,A 
Address Instruction 1 2 3 4 5 6 7 8
+
+
+
+
+    
+        
+        
+        
+        
+    
+    
+        
+    
+ 
0x08170 ldw    X,#0x0200 
0x08173 ld     A,#0x80 
0x08175 div    X,A 
Address Instruction 1 2 3 4 5 6 7 8
+
+
+
+
+    
+        
+        
+        
+        
+    
+    
+        
+    
+ 
0x08178 ldw    X,#0x0100 
0x0817b ld     A,#0x80 
0x0817d div    X,A 
Address Instruction 1 2 3 4 5 6 7 8
+
+
+
+
+    
+        
+        
+        
+        
+    
+    
+        
+    
+ 
0x08180 ldw    X,#0x0080 
0x08183 ld     A,#0x80 
0x08185 div    X,A 
Address Instruction 1 2 3 4 5 6 7
+
+
+
+
+    
+        
+        
+        
+        
+    
+    
+        
+    
+ 
0x08188 ldw    X,#0x0040 
0x0818b ld     A,#0x80 
0x0818d div    X,A 
Address Instruction 1 2 3 4 5 6 7
+
+
+
+
+    
+        
+        
+        
+        
+    
+    
+        
+    
+ 
0x08190 ldw    X,#0x0020 
0x08193 ld     A,#0x80 
0x08195 div    X,A 
Address Instruction 1 2 3 4 5 6 7
+
+
+
+
+    
+        
+        
+        
+        
+    
+    
+        
+    
+ 
0x08198 ldw    X,#0x0010 
0x0819b ld     A,#0x80 
0x0819d div    X,A 
Address Instruction 1 2 3 4 5 6 7
+
+
+
+
+    
+        
+        
+        
+        
+    
+    
+        
+    
+ 
0x081a0 ldw    X,#0x0008 
0x081a3 ld     A,#0x80 
0x081a5 div    X,A 
Address Instruction 1 2 3 4 5 6 7
+
+
+
+
+    
+        
+        
+        
+        
+    
+    
+        
+    
+ 
0x081a8 ldw    X,#0x0004 
0x081ab ld     A,#0x80 
0x081ad div    X,A 
Address Instruction 1 2 3 4 5 6 7
+
+
+
+
+    
+        
+        
+        
+        
+    
+    
+        
+    
+ 
0x081b0 ldw    X,#0x0002 
0x081b3 ld     A,#0x80 
0x081b5 div    X,A 
Address Instruction 1 2 3 4 5 6 7
+
+
+
+
+    
+        
+        
+        
+        
+    
+    
+        
+    
+ 
0x081b8 ldw    X,#0x0001 
0x081bb ld     A,#0x80 
0x081bd div    X,A 
Address Instruction 1 2 3 4 5 6 7
+
+
+
+
+    
+        
+        
+        
+        
+    
+    
+        
+    
+ 
0x081c0 ldw    X,#0x0000 
0x081c3 ld     A,#0x80 
0x081c5 div    X,A 
Address Instruction 1 2 3 4 5 6 7
+
+
+
+
+    
+        
+        
+        
+        
+    
+    
+        
+    
+ 
0x081c8 ldw    X,#0x003f 
0x081cb ld     A,#0x08 
0x081cd div    X,A 
Address Instruction 1 2 3 4 5 6 7 8 9
+
+
+
+
+    
+        
+        
+        
+        
+    
+    
+        
+    
+ 
0x081d0 ldw    X,#0x0040 
0x081d3 ld     A,#0x08 
0x081d5 div    X,A 
Address Instruction 1 2 3 4 5 6 7 8
+
+
+
+
+    
+        
+        
+        
+        
+    
+    
+        
+    
+ 
0x081d8 ldw    X,#0x0041 
0x081db ld     A,#0x08 
0x081dd div    X,A 
Address Instruction 1 2 3 4 5 6 7 8
+
+
+
+
+    
+        
+        
+        
+        
+    
+    
+        
+    
+ 
0x081e0 ldw    X,#0x8000 
0x081e3 ldw    Y,#0x0001 
0x081e7 divw   X,Y 
Address Instruction 1 2 3 4 5 6 7 8 9
+
+
+
+
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/stm8-cycles/baseline/test.instrs.html sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/stm8-cycles/baseline/test.instrs.html
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/stm8-cycles/baseline/test.instrs.html	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/stm8-cycles/baseline/test.instrs.html	2022-02-03 14:06:06.000000000 +0000
@@ -0,0 +1,1627 @@
+
+
+All instructions and addressing modes
+
+
+
+
+
+
+
+All instructions and addressing modes
+
+
+    
+    
+    
+    
+    
+    
+    
+    
+    
+Legend
Decode
Execute
Fetch
Flush
Fetch Stall - space in prefetch buffer but bus busy
Decode Stall - bus busy
Decode Stall - insufficient data in prefetch buffer
Decode Stall - read after write
+
+Note that timings given in PM0044 assume a 1 cycle overlap
+with the previous instruction and are specified as being
+one cycle less than they are in the no prefetch/stall case.
+Instructions that flush the prefetch buffer such as jumps
+prevent the overlap with the following instruction. The cycle
+count for these instructions includes the extra cycles for
+the unavoidable fetches and stalls that follow them.
+
+
+    
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
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0x08290 add    A,(0x1000,Y) 
0x08294 jra    0x8298 
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0x082cc addw   X,0x1000 
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0x082dc addw   Y,#0x1000 
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0x082e4 addw   Y,0x1000 
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0x08358 bccm   0x10,#2 
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0x083d8 ccf 
0x083d9 jra    0x83dc 
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0x08466 jra    0x8468 
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0x08474 jra    0x8478 
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0x0847a jra    0x847c 
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0x08488 jra    0x848c 
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0x0848f jra    0x8494 
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0x08498 jra    0x849c 
0x0849c cp     A,([0x10.w],Y) 
0x0849f jra    0x84a4 
0x084a4 cpw    X,#0x0055 
0x084a7 jra    0x84ac 
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0x084ae jra    0x84b0 
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0x084b3 jra    0x84b8 
0x084b8 cpw    X,(Y) 
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0x084c8 jra    0x84cc 
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0x084ce jra    0x84d0 
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0x084d3 jra    0x84d8 
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0x084dc jra    0x84e0 
0x084e0 cpw    X,([0x10.w],Y) 
0x084e3 jra    0x84e8 
0x084e8 cpw    Y,([0x1000.w],X) 
0x084ec jra    0x84f0 
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0x084f1 jra    0x84f4 
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0x084f8 cpl    0xf5c2 
0x084fc jra    0x8500 
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0x08501 jra    0x8504 
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0x08506 jra    0x8508 
0x08508 cpl    (0xf5c2,X) 
0x0850c jra    0x8510 
0x08510 cpl    (Y) 
0x08512 jra    0x8514 
0x08514 cpl    (0xf5,Y) 
0x08517 jra    0x851c 
0x0851c cpl    (0xf5c2,Y) 
0x08520 jra    0x8524 
0x08524 cpl    (0xf5,SP) 
0x08526 jra    0x8528 
0x08528 cpl    [0xf5.w] 
0x0852b jra    0x8530 
0x08530 cpl    [0xf5c2.w] 
0x08534 jra    0x8538 
0x08538 cpl    ([0xf5.w],X) 
0x0853b jra    0x8540 
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0x08544 jra    0x8548 
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0x0854b jra    0x8550 
0x08550 cplw   X 
0x08551 jra    0x8554 
0x08554 cplw   Y 
0x08556 jra    0x8558 
0x08558 dec    A 
0x08559 jra    0x855c 
0x0855c dec    0xf5 
0x0855e jra    0x8560 
0x08560 dec    0xf5c2 
0x08564 jra    0x8568 
0x08568 dec    (X) 
0x08569 jra    0x856c 
0x0856c dec    (0xf5,X) 
0x0856e jra    0x8570 
0x08570 dec    (0xf5c2,X) 
0x08574 jra    0x8578 
0x08578 dec    (Y) 
0x0857a jra    0x857c 
0x0857c dec    (0xf5,Y) 
0x0857f jra    0x8584 
0x08584 dec    (0xf5c2,Y) 
0x08588 jra    0x858c 
0x0858c dec    (0xf5,SP) 
0x0858e jra    0x8590 
0x08590 dec    [0xf5.w] 
0x08593 jra    0x8598 
0x08598 dec    [0xf5c2.w] 
0x0859c jra    0x85a0 
0x085a0 dec    ([0xf5.w],X) 
0x085a3 jra    0x85a8 
0x085a8 dec    ([0xf5c2.w],X) 
0x085ac jra    0x85b0 
0x085b0 dec    ([0xf5.w],Y) 
0x085b3 jra    0x85b8 
0x085b8 decw   X 
0x085b9 jra    0x85bc 
0x085bc decw   Y 
0x085be jra    0x85c0 
0x085c0 exg    A,XL 
0x085c1 jra    0x85c4 
0x085c4 exg    A,YL 
0x085c5 jra    0x85c8 
0x085c8 exg    A,0x1000 
0x085cb jra    0x85d0 
0x085d0 exgw   X,Y 
0x085d1 jra    0x85d4 
0x085d4 inc    A 
0x085d5 jra    0x85d8 
0x085d8 inc    0xf5 
0x085da jra    0x85dc 
0x085dc inc    0xf5c2 
0x085e0 jra    0x85e4 
0x085e4 inc    (X) 
0x085e5 jra    0x85e8 
0x085e8 inc    (0xf5,X) 
0x085ea jra    0x85ec 
0x085ec inc    (0xf5c2,X) 
0x085f0 jra    0x85f4 
0x085f4 inc    (Y) 
0x085f6 jra    0x85f8 
0x085f8 inc    (0xf5,Y) 
0x085fb jra    0x8600 
0x08600 inc    (0xf5c2,Y) 
0x08604 jra    0x8608 
0x08608 inc    (0xf5,SP) 
0x0860a jra    0x860c 
0x0860c inc    [0xf5.w] 
0x0860f jra    0x8614 
0x08614 inc    [0xf5c2.w] 
0x08618 jra    0x861c 
0x0861c inc    ([0xf5.w],X) 
0x0861f jra    0x8624 
0x08624 inc    ([0xf5c2.w],X) 
0x08628 jra    0x862c 
0x0862c inc    ([0xf5.w],Y) 
0x0862f jra    0x8634 
0x08634 incw   X 
0x08635 jra    0x8638 
0x08638 incw   Y 
0x0863a jra    0x863c 
0x0863c ld     A,#0x55 
0x0863e jra    0x8640 
0x08640 ld     A,0x10 
0x08642 jra    0x8644 
0x08644 ld     A,0x1000 
0x08647 jra    0x864c 
0x0864c ld     A,(X) 
0x0864d jra    0x8650 
0x08650 ld     A,(0x10,X) 
0x08652 jra    0x8654 
0x08654 ld     A,(0x1000,X) 
0x08657 jra    0x865c 
0x0865c ld     A,(Y) 
0x0865e jra    0x8660 
0x08660 ld     A,(0x10,Y) 
0x08663 jra    0x8668 
0x08668 ld     A,(0x1000,Y) 
0x0866c jra    0x8670 
0x08670 ld     A,(0x10,SP) 
0x08672 jra    0x8674 
0x08674 ld     A,[0x10.w] 
0x08677 jra    0x867c 
0x0867c ld     A,[0x1000.w] 
0x08680 jra    0x8684 
0x08684 ld     A,([0x10.w],X) 
0x08687 jra    0x868c 
0x0868c ld     A,([0x1000.w],X) 
0x08690 jra    0x8694 
0x08694 ld     A,([0x10.w],Y) 
0x08697 jra    0x869c 
0x0869c ld     0x10,A 
0x0869e jra    0x86a0 
0x086a0 ld     0x1000,A 
0x086a3 jra    0x86a8 
0x086a8 ld     (X),A 
0x086a9 jra    0x86ac 
0x086ac ld     (0x10,X),A 
0x086ae jra    0x86b0 
0x086b0 ld     (0x1000,X),A 
0x086b3 jra    0x86b8 
0x086b8 ld     (Y),A 
0x086ba jra    0x86bc 
0x086bc ld     (0x10,Y),A 
0x086bf jra    0x86c4 
0x086c4 ld     (0x1000,Y),A 
0x086c8 jra    0x86cc 
0x086cc ld     (0x10,SP),A 
0x086ce jra    0x86d0 
0x086d0 ld     [0x10.w],A 
0x086d3 jra    0x86d8 
0x086d8 ld     [0x1000.w],A 
0x086dc jra    0x86e0 
0x086e0 ld     ([0x10.w],X),A 
0x086e3 jra    0x86e8 
0x086e8 ld     ([0x1000.w],X),A 
0x086ec jra    0x86f0 
0x086f0 ld     ([0x10.w],Y),A 
0x086f3 jra    0x86f8 
0x086f8 ldf    A,0x500000 
0x086fc jra    0x8700 
0x08700 ldf    A,(0x500000,X) 
0x08704 jra    0x8708 
0x08708 ldf    A,(0x500000,Y) 
0x0870d jra    0x8710 
0x08710 ldf    A,([0x5000 <PA_ODR>.e],X) 
0x08714 jra    0x8718 
0x08718 ldf    A,([0x5000 <PA_ODR>.e],Y) 
0x0871c jra    0x8720 
0x08720 ldf    A,[0x50.e] 
0x08724 jra    0x8728 
0x08728 ldw    X,#0x0055 
0x0872b jra    0x8730 
0x08730 ldw    X,0x10 
0x08732 jra    0x8734 
0x08734 ldw    X,0x1000 
0x08737 jra    0x873c 
0x0873c ldw    X,(X) 
0x0873d jra    0x8740 
0x08740 ldw    X,(0x10,X) 
0x08742 jra    0x8744 
0x08744 ldw    X,(0x1000,X) 
0x08747 jra    0x874c 
0x0874c ldw    X,(0x10,SP) 
0x0874e jra    0x8750 
0x08750 ldw    X,[0x10.w] 
0x08753 jra    0x8758 
0x08758 ldw    X,[0x1000.w] 
0x0875c jra    0x8760 
0x08760 ldw    X,([0x10.w],X) 
0x08763 jra    0x8768 
0x08768 ldw    X,([0x1000.w],X) 
0x0876c jra    0x8770 
0x08770 mov    0x8000,#0xaa 
0x08774 jra    0x8778 
0x08778 mov    0x80,0x10 
0x0877b jra    0x8780 
0x08780 mov    0x8000,0x1000 
0x08785 jra    0x8788 
0x08788 mul    X,A 
0x08789 jra    0x878c 
0x0878c neg    A 
0x0878d jra    0x8790 
0x08790 neg    0xf5 
0x08792 jra    0x8794 
0x08794 neg    0xf5c2 
0x08798 jra    0x879c 
0x0879c neg    (X) 
0x0879d jra    0x87a0 
0x087a0 neg    (0xf5,X) 
0x087a2 jra    0x87a4 
0x087a4 neg    (0xf5c2,X) 
0x087a8 jra    0x87ac 
0x087ac neg    (Y) 
0x087ae jra    0x87b0 
0x087b0 neg    (0xf5,Y) 
0x087b3 jra    0x87b8 
0x087b8 neg    (0xf5c2,Y) 
0x087bc jra    0x87c0 
0x087c0 neg    (0xf5,SP) 
0x087c2 jra    0x87c4 
0x087c4 neg    [0xf5.w] 
0x087c7 jra    0x87cc 
0x087cc neg    [0xf5c2.w] 
0x087d0 jra    0x87d4 
0x087d4 neg    ([0xf5.w],X) 
0x087d7 jra    0x87dc 
0x087dc neg    ([0xf5c2.w],X) 
0x087e0 jra    0x87e4 
0x087e4 neg    ([0xf5.w],Y) 
0x087e7 jra    0x87ec 
0x087ec negw   X 
0x087ed jra    0x87f0 
0x087f0 negw   Y 
0x087f2 jra    0x87f4 
0x087f4 nop 
0x087f5 jra    0x87f8 
0x087f8 or     A,#0x55 
0x087fa jra    0x87fc 
0x087fc or     A,0x10 
0x087fe jra    0x8800 
0x08800 or     A,0x1000 
0x08803 jra    0x8808 
0x08808 or     A,(X) 
0x08809 jra    0x880c 
0x0880c or     A,(0x10,X) 
0x0880e jra    0x8810 
0x08810 or     A,(0x1000,X) 
0x08813 jra    0x8818 
0x08818 or     A,(Y) 
0x0881a jra    0x881c 
0x0881c or     A,(0x10,Y) 
0x0881f jra    0x8824 
0x08824 or     A,(0x1000,Y) 
0x08828 jra    0x882c 
0x0882c or     A,(0x10,SP) 
0x0882e jra    0x8830 
0x08830 or     A,[0x10.w] 
0x08833 jra    0x8838 
0x08838 or     A,[0x1000.w] 
0x0883c jra    0x8840 
0x08840 or     A,([0x10.w],X) 
0x08843 jra    0x8848 
0x08848 or     A,([0x1000.w],X) 
0x0884c jra    0x8850 
0x08850 or     A,([0x10.w],Y) 
0x08853 jra    0x8858 
0x08858 rcf 
0x08859 jra    0x885c 
0x0885c rlc    A 
0x0885d jra    0x8860 
0x08860 rlc    0xf5 
0x08862 jra    0x8864 
0x08864 rlc    0xf5c2 
0x08868 jra    0x886c 
0x0886c rlc    (X) 
0x0886d jra    0x8870 
0x08870 rlc    (0xf5,X) 
0x08872 jra    0x8874 
0x08874 rlc    (0xf5c2,X) 
0x08878 jra    0x887c 
0x0887c rlc    (Y) 
0x0887e jra    0x8880 
0x08880 rlc    (0xf5,Y) 
0x08883 jra    0x8888 
0x08888 rlc    (0xf5c2,Y) 
0x0888c jra    0x8890 
0x08890 rlc    (0xf5,SP) 
0x08892 jra    0x8894 
0x08894 rlc    [0xf5.w] 
0x08897 jra    0x889c 
0x0889c rlc    [0xf5c2.w] 
0x088a0 jra    0x88a4 
0x088a4 rlc    ([0xf5.w],X) 
0x088a7 jra    0x88ac 
0x088ac rlc    ([0xf5c2.w],X) 
0x088b0 jra    0x88b4 
0x088b4 rlc    ([0xf5.w],Y) 
0x088b7 jra    0x88bc 
0x088bc rlcw   X 
0x088bd jra    0x88c0 
0x088c0 rlcw   Y 
0x088c2 jra    0x88c4 
0x088c4 rlwa   X 
0x088c5 jra    0x88c8 
0x088c8 rlwa   Y 
0x088ca jra    0x88cc 
0x088cc rrc    A 
0x088cd jra    0x88d0 
0x088d0 rrc    0xf5 
0x088d2 jra    0x88d4 
0x088d4 rrc    0xf5c2 
0x088d8 jra    0x88dc 
0x088dc rrc    (X) 
0x088dd jra    0x88e0 
0x088e0 rrc    (0xf5,X) 
0x088e2 jra    0x88e4 
0x088e4 rrc    (0xf5c2,X) 
0x088e8 jra    0x88ec 
0x088ec rrc    (Y) 
0x088ee jra    0x88f0 
0x088f0 rrc    (0xf5,Y) 
0x088f3 jra    0x88f8 
0x088f8 rrc    (0xf5c2,Y) 
0x088fc jra    0x8900 
0x08900 rrc    (0xf5,SP) 
0x08902 jra    0x8904 
0x08904 rrc    [0xf5.w] 
0x08907 jra    0x890c 
0x0890c rrc    [0xf5c2.w] 
0x08910 jra    0x8914 
0x08914 rrc    ([0xf5.w],X) 
0x08917 jra    0x891c 
0x0891c rrc    ([0xf5c2.w],X) 
0x08920 jra    0x8924 
0x08924 rrc    ([0xf5.w],Y) 
0x08927 jra    0x892c 
0x0892c rrcw   X 
0x0892d jra    0x8930 
0x08930 rrcw   Y 
0x08932 jra    0x8934 
0x08934 rrwa   X 
0x08935 jra    0x8938 
0x08938 rrwa   Y 
0x0893a jra    0x893c 
0x0893c rvf 
0x0893d jra    0x8940 
0x08940 sbc    A,#0x55 
0x08942 jra    0x8944 
0x08944 sbc    A,0x10 
0x08946 jra    0x8948 
0x08948 sbc    A,0x1000 
0x0894b jra    0x8950 
0x08950 sbc    A,(X) 
0x08951 jra    0x8954 
0x08954 sbc    A,(0x10,X) 
0x08956 jra    0x8958 
0x08958 sbc    A,(0x1000,X) 
0x0895b jra    0x8960 
0x08960 sbc    A,(Y) 
0x08962 jra    0x8964 
0x08964 sbc    A,(0x10,Y) 
0x08967 jra    0x896c 
0x0896c sbc    A,(0x1000,Y) 
0x08970 jra    0x8974 
0x08974 sbc    A,(0x10,SP) 
0x08976 jra    0x8978 
0x08978 sbc    A,[0x10.w] 
0x0897b jra    0x8980 
0x08980 sbc    A,[0x1000.w] 
0x08984 jra    0x8988 
0x08988 sbc    A,([0x10.w],X) 
0x0898b jra    0x8990 
0x08990 sbc    A,([0x1000.w],X) 
0x08994 jra    0x8998 
0x08998 sbc    A,([0x10.w],Y) 
0x0899b jra    0x89a0 
0x089a0 scf 
0x089a1 jra    0x89a4 
0x089a4 subw   X,#0x5500 
0x089a7 jra    0x89ac 
0x089ac subw   X,0x10 
0x089b0 jra    0x89b4 
0x089b4 subw   X,(0x10,SP) 
0x089b7 jra    0x89bc 
0x089bc ldw    Y,X 
0x089be jra    0x89c0 
0x089c0 ldw    0x10,X 
0x089c2 jra    0x89c4 
0x089c4 ldw    0x1000,X 
0x089c7 jra    0x89cc 
0x089cc ldw    (X),Y 
0x089cd jra    0x89d0 
0x089d0 ldw    (0x10,X),Y 
0x089d2 jra    0x89d4 
0x089d4 ldw    (0x1000,X),Y 
0x089d7 jra    0x89dc 
0x089dc ldw    (0x10,SP),X 
0x089de jra    0x89e0 
0x089e0 ldw    [0x10.w],X 
0x089e3 jra    0x89e8 
0x089e8 ldw    [0x1000.w],X 
0x089ec jra    0x89f0 
0x089f0 ldw    ([0x10.w],X),Y 
0x089f3 jra    0x89f8 
0x089f8 ldw    ([0x1000.w],X),Y 
0x089fc jra    0x8a00 
0x08a00 sla    A 
0x08a01 jra    0x8a04 
0x08a04 sla    0xf5 
0x08a06 jra    0x8a08 
0x08a08 sla    0xf5c2 
0x08a0c jra    0x8a10 
0x08a10 sla    (X) 
0x08a11 jra    0x8a14 
0x08a14 sla    (0xf5,X) 
0x08a16 jra    0x8a18 
0x08a18 sla    (0xf5c2,X) 
0x08a1c jra    0x8a20 
0x08a20 sla    (Y) 
0x08a22 jra    0x8a24 
0x08a24 sla    (0xf5,Y) 
0x08a27 jra    0x8a2c 
0x08a2c sla    (0xf5c2,Y) 
0x08a30 jra    0x8a34 
0x08a34 sla    (0xf5,SP) 
0x08a36 jra    0x8a38 
0x08a38 sla    [0xf5.w] 
0x08a3b jra    0x8a40 
0x08a40 sla    [0xf5c2.w] 
0x08a44 jra    0x8a48 
0x08a48 sla    ([0xf5.w],X) 
0x08a4b jra    0x8a50 
0x08a50 sla    ([0xf5c2.w],X) 
0x08a54 jra    0x8a58 
0x08a58 sla    ([0xf5.w],Y) 
0x08a5b jra    0x8a60 
0x08a60 slaw   X 
0x08a61 jra    0x8a64 
0x08a64 slaw   Y 
0x08a66 jra    0x8a68 
0x08a68 sla    A 
0x08a69 jra    0x8a6c 
0x08a6c sla    0xf5 
0x08a6e jra    0x8a70 
0x08a70 sla    0xf5c2 
0x08a74 jra    0x8a78 
0x08a78 sla    (X) 
0x08a79 jra    0x8a7c 
0x08a7c sla    (0xf5,X) 
0x08a7e jra    0x8a80 
0x08a80 sla    (0xf5c2,X) 
0x08a84 jra    0x8a88 
0x08a88 sla    (Y) 
0x08a8a jra    0x8a8c 
0x08a8c sla    (0xf5,Y) 
0x08a8f jra    0x8a94 
0x08a94 sla    (0xf5c2,Y) 
0x08a98 jra    0x8a9c 
0x08a9c sla    (0xf5,SP) 
0x08a9e jra    0x8aa0 
0x08aa0 sla    [0xf5.w] 
0x08aa3 jra    0x8aa8 
0x08aa8 sla    [0xf5c2.w] 
0x08aac jra    0x8ab0 
0x08ab0 sla    ([0xf5.w],X) 
0x08ab3 jra    0x8ab8 
0x08ab8 sla    ([0xf5c2.w],X) 
0x08abc jra    0x8ac0 
0x08ac0 sla    ([0xf5.w],Y) 
0x08ac3 jra    0x8ac8 
0x08ac8 slaw   X 
0x08ac9 jra    0x8acc 
0x08acc slaw   Y 
0x08ace jra    0x8ad0 
0x08ad0 sra    A 
0x08ad1 jra    0x8ad4 
0x08ad4 sra    0xf5 
0x08ad6 jra    0x8ad8 
0x08ad8 sra    0xf5c2 
0x08adc jra    0x8ae0 
0x08ae0 sra    (X) 
0x08ae1 jra    0x8ae4 
0x08ae4 sra    (0xf5,X) 
0x08ae6 jra    0x8ae8 
0x08ae8 sra    (0xf5c2,X) 
0x08aec jra    0x8af0 
0x08af0 sra    (Y) 
0x08af2 jra    0x8af4 
0x08af4 sra    (0xf5,Y) 
0x08af7 jra    0x8afc 
0x08afc sra    (0xf5c2,Y) 
0x08b00 jra    0x8b04 
0x08b04 sra    (0xf5,SP) 
0x08b06 jra    0x8b08 
0x08b08 sra    [0xf5.w] 
0x08b0b jra    0x8b10 
0x08b10 sra    [0xf5c2.w] 
0x08b14 jra    0x8b18 
0x08b18 sra    ([0xf5.w],X) 
0x08b1b jra    0x8b20 
0x08b20 sra    ([0xf5c2.w],X) 
0x08b24 jra    0x8b28 
0x08b28 sra    ([0xf5.w],Y) 
0x08b2b jra    0x8b30 
0x08b30 sraw   X 
0x08b31 jra    0x8b34 
0x08b34 sraw   Y 
0x08b36 jra    0x8b38 
0x08b38 srl    A 
0x08b39 jra    0x8b3c 
0x08b3c srl    0xf5 
0x08b3e jra    0x8b40 
0x08b40 srl    0xf5c2 
0x08b44 jra    0x8b48 
0x08b48 srl    (X) 
0x08b49 jra    0x8b4c 
0x08b4c srl    (0xf5,X) 
0x08b4e jra    0x8b50 
0x08b50 srl    (0xf5c2,X) 
0x08b54 jra    0x8b58 
0x08b58 srl    (Y) 
0x08b5a jra    0x8b5c 
0x08b5c srl    (0xf5,Y) 
0x08b5f jra    0x8b64 
0x08b64 srl    (0xf5c2,Y) 
0x08b68 jra    0x8b6c 
0x08b6c srl    (0xf5,SP) 
0x08b6e jra    0x8b70 
0x08b70 srl    [0xf5.w] 
0x08b73 jra    0x8b78 
0x08b78 srl    [0xf5c2.w] 
0x08b7c jra    0x8b80 
0x08b80 srl    ([0xf5.w],X) 
0x08b83 jra    0x8b88 
0x08b88 srl    ([0xf5c2.w],X) 
0x08b8c jra    0x8b90 
0x08b90 srl    ([0xf5.w],Y) 
0x08b93 jra    0x8b98 
0x08b98 srlw   X 
0x08b99 jra    0x8b9c 
0x08b9c srlw   Y 
0x08b9e jra    0x8ba0 
0x08ba0 sub    A,#0x55 
0x08ba2 jra    0x8ba4 
0x08ba4 sub    A,0x10 
0x08ba6 jra    0x8ba8 
0x08ba8 sub    A,0x1000 
0x08bab jra    0x8bb0 
0x08bb0 sub    A,(X) 
0x08bb1 jra    0x8bb4 
0x08bb4 sub    A,(0x10,X) 
0x08bb6 jra    0x8bb8 
0x08bb8 sub    A,(0x1000,X) 
0x08bbb jra    0x8bc0 
0x08bc0 sub    A,(Y) 
0x08bc2 jra    0x8bc4 
0x08bc4 sub    A,(0x10,Y) 
0x08bc7 jra    0x8bcc 
0x08bcc sub    A,(0x1000,Y) 
0x08bd0 jra    0x8bd4 
0x08bd4 sub    A,(0x10,SP) 
0x08bd6 jra    0x8bd8 
0x08bd8 sub    A,[0x10.w] 
0x08bdb jra    0x8be0 
0x08be0 sub    A,[0x1000.w] 
0x08be4 jra    0x8be8 
0x08be8 sub    A,([0x10.w],X) 
0x08beb jra    0x8bf0 
0x08bf0 sub    A,([0x1000.w],X) 
0x08bf4 jra    0x8bf8 
0x08bf8 sub    A,([0x10.w],Y) 
0x08bfb jra    0x8c00 
0x08c00 sub    SP,#0x55 
0x08c02 jra    0x8c04 
0x08c04 swap   A 
0x08c05 jra    0x8c08 
0x08c08 swap   0xf5 
0x08c0a jra    0x8c0c 
0x08c0c swap   0xf5c2 
0x08c10 jra    0x8c14 
0x08c14 swap   (X) 
0x08c15 jra    0x8c18 
0x08c18 swap   (0xf5,X) 
0x08c1a jra    0x8c1c 
0x08c1c swap   (0xf5c2,X) 
0x08c20 jra    0x8c24 
0x08c24 swap   (Y) 
0x08c26 jra    0x8c28 
0x08c28 swap   (0xf5,Y) 
0x08c2b jra    0x8c30 
0x08c30 swap   (0xf5c2,Y) 
0x08c34 jra    0x8c38 
0x08c38 swap   (0xf5,SP) 
0x08c3a jra    0x8c3c 
0x08c3c swap   [0xf5.w] 
0x08c3f jra    0x8c44 
0x08c44 swap   [0xf5c2.w] 
0x08c48 jra    0x8c4c 
0x08c4c swap   ([0xf5.w],X) 
0x08c4f jra    0x8c54 
0x08c54 swap   ([0xf5c2.w],X) 
0x08c58 jra    0x8c5c 
0x08c5c swap   ([0xf5.w],Y) 
0x08c5f jra    0x8c64 
0x08c64 swapw  X 
0x08c65 jra    0x8c68 
0x08c68 swapw  Y 
0x08c6a jra    0x8c6c 
0x08c6c tnz    A 
0x08c6d jra    0x8c70 
0x08c70 tnz    0xf5 
0x08c72 jra    0x8c74 
0x08c74 tnz    0xf5c2 
0x08c78 jra    0x8c7c 
0x08c7c tnz    (X) 
0x08c7d jra    0x8c80 
0x08c80 tnz    (0xf5,X) 
0x08c82 jra    0x8c84 
0x08c84 tnz    (0xf5c2,X) 
0x08c88 jra    0x8c8c 
0x08c8c tnz    (Y) 
0x08c8e jra    0x8c90 
0x08c90 tnz    (0xf5,Y) 
0x08c93 jra    0x8c98 
0x08c98 tnz    (0xf5c2,Y) 
0x08c9c jra    0x8ca0 
0x08ca0 tnz    (0xf5,SP) 
0x08ca2 jra    0x8ca4 
0x08ca4 tnz    [0xf5.w] 
0x08ca7 jra    0x8cac 
0x08cac tnz    [0xf5c2.w] 
0x08cb0 jra    0x8cb4 
0x08cb4 tnz    ([0xf5.w],X) 
0x08cb7 jra    0x8cbc 
0x08cbc tnz    ([0xf5c2.w],X) 
0x08cc0 jra    0x8cc4 
0x08cc4 tnz    ([0xf5.w],Y) 
0x08cc7 jra    0x8ccc 
0x08ccc tnzw   X 
0x08ccd jra    0x8cd0 
0x08cd0 tnzw   Y 
0x08cd2 jra    0x8cd4 
0x08cd4 xor    A,#0x55 
0x08cd6 jra    0x8cd8 
0x08cd8 xor    A,0x10 
0x08cda jra    0x8cdc 
0x08cdc xor    A,0x1000 
0x08cdf jra    0x8ce4 
0x08ce4 xor    A,(X) 
0x08ce5 jra    0x8ce8 
0x08ce8 xor    A,(0x10,X) 
0x08cea jra    0x8cec 
0x08cec xor    A,(0x1000,X) 
0x08cef jra    0x8cf4 
0x08cf4 xor    A,(Y) 
0x08cf6 jra    0x8cf8 
0x08cf8 xor    A,(0x10,Y) 
0x08cfb jra    0x8d00 
0x08d00 xor    A,(0x1000,Y) 
0x08d04 jra    0x8d08 
0x08d08 xor    A,(0x10,SP) 
0x08d0a jra    0x8d0c 
0x08d0c xor    A,[0x10.w] 
0x08d0f jra    0x8d14 
0x08d14 xor    A,[0x1000.w] 
0x08d18 jra    0x8d1c 
0x08d1c xor    A,([0x10.w],X) 
0x08d1f jra    0x8d24 
0x08d24 xor    A,([0x1000.w],X) 
0x08d28 jra    0x8d2c 
0x08d2c xor    A,([0x10.w],Y) 
0x08d2f jra    0x8d34 
0x08d34 ldw    X,#0x8000 
0x08d37 ld     A,#0x02 
0x08d39 div    X,A 
0x08d3a jra    0x8d3c 
0x08d3c ldw    X,#0x4000 
0x08d3f ld     A,#0x02 
0x08d41 div    X,A 
0x08d42 jra    0x8d44 
0x08d44 ldw    X,#0x2000 
0x08d47 ld     A,#0x02 
0x08d49 div    X,A 
0x08d4a jra    0x8d4c 
0x08d4c ldw    X,#0x1000 
0x08d4f ld     A,#0x02 
0x08d51 div    X,A 
0x08d52 jra    0x8d54 
0x08d54 ldw    X,#0x0800 
0x08d57 ld     A,#0x02 
0x08d59 div    X,A 
0x08d5a jra    0x8d5c 
0x08d5c ldw    X,#0x0400 
0x08d5f ld     A,#0x02 
0x08d61 div    X,A 
0x08d62 jra    0x8d64 
0x08d64 ldw    X,#0x0200 
0x08d67 ld     A,#0x02 
0x08d69 div    X,A 
0x08d6a jra    0x8d6c 
0x08d6c ldw    X,#0x0100 
0x08d6f ld     A,#0x02 
0x08d71 div    X,A 
0x08d72 jra    0x8d74 
0x08d74 ldw    X,#0x0080 
0x08d77 ld     A,#0x02 
0x08d79 div    X,A 
0x08d7a jra    0x8d7c 
0x08d7c ldw    X,#0x0040 
0x08d7f ld     A,#0x02 
0x08d81 div    X,A 
0x08d82 jra    0x8d84 
0x08d84 ldw    X,#0x0020 
0x08d87 ld     A,#0x02 
0x08d89 div    X,A 
0x08d8a jra    0x8d8c 
0x08d8c ldw    X,#0x0010 
0x08d8f ld     A,#0x02 
0x08d91 div    X,A 
0x08d92 jra    0x8d94 
0x08d94 ldw    X,#0x0008 
0x08d97 ld     A,#0x02 
0x08d99 div    X,A 
0x08d9a jra    0x8d9c 
0x08d9c ldw    X,#0x0004 
0x08d9f ld     A,#0x02 
0x08da1 div    X,A 
0x08da2 jra    0x8da4 
0x08da4 ldw    X,#0x0002 
0x08da7 ld     A,#0x02 
0x08da9 div    X,A 
0x08daa jra    0x8dac 
0x08dac ldw    X,#0xffff 
0x08daf ld     A,#0x02 
0x08db1 div    X,A 
0x08db2 jra    0x8db4 
0x08db4 ldw    X,#0x7fff 
0x08db7 ld     A,#0x02 
0x08db9 div    X,A 
0x08dba jra    0x8dbc 
0x08dbc ldw    X,#0x3fff 
0x08dbf ld     A,#0x02 
0x08dc1 div    X,A 
0x08dc2 jra    0x8dc4 
0x08dc4 ldw    X,#0x1fff 
0x08dc7 ld     A,#0x02 
0x08dc9 div    X,A 
0x08dca jra    0x8dcc 
0x08dcc ldw    X,#0x0fff 
0x08dcf ld     A,#0x02 
0x08dd1 div    X,A 
0x08dd2 jra    0x8dd4 
0x08dd4 ldw    X,#0x07ff 
0x08dd7 ld     A,#0x02 
0x08dd9 div    X,A 
0x08dda jra    0x8ddc 
0x08ddc ldw    X,#0x03ff 
0x08ddf ld     A,#0x02 
0x08de1 div    X,A 
0x08de2 jra    0x8de4 
0x08de4 ldw    X,#0x01ff 
0x08de7 ld     A,#0x02 
0x08de9 div    X,A 
0x08dea jra    0x8dec 
0x08dec ldw    X,#0x00ff 
0x08def ld     A,#0x02 
0x08df1 div    X,A 
0x08df2 jra    0x8df4 
0x08df4 ldw    X,#0x007f 
0x08df7 ld     A,#0x02 
0x08df9 div    X,A 
0x08dfa jra    0x8dfc 
0x08dfc ldw    X,#0x003f 
0x08dff ld     A,#0x02 
0x08e01 div    X,A 
0x08e02 jra    0x8e04 
0x08e04 ldw    X,#0x001f 
0x08e07 ld     A,#0x02 
0x08e09 div    X,A 
0x08e0a jra    0x8e0c 
0x08e0c ldw    X,#0x000f 
0x08e0f ld     A,#0x02 
0x08e11 div    X,A 
0x08e12 jra    0x8e14 
0x08e14 ldw    X,#0x0007 
0x08e17 ld     A,#0x02 
0x08e19 div    X,A 
0x08e1a jra    0x8e1c 
0x08e1c ldw    X,#0x0003 
0x08e1f ld     A,#0x02 
0x08e21 div    X,A 
0x08e22 jra    0x8e24 
0x08e24 ldw    X,#0x2000 
0x08e27 ld     A,#0x02 
0x08e29 div    X,A 
0x08e2a jra    0x8e2c 
0x08e2c ldw    X,#0x2040 
0x08e2f ld     A,#0x02 
0x08e31 div    X,A 
0x08e32 jra    0x8e34 
0x08e34 ldw    X,#0x2048 
0x08e37 ld     A,#0x02 
0x08e39 div    X,A 
0x08e3a jra    0x8e3c 
0x08e3c ldw    X,#0x2148 
0x08e3f ld     A,#0x02 
0x08e41 div    X,A 
0x08e42 jra    0x8e44 
0x08e44 ldw    X,#0x21c8 
0x08e47 ld     A,#0x02 
0x08e49 div    X,A 
0x08e4a jra    0x8e4c 
0x08e4c ldw    X,#0xb307 
0x08e4f ld     A,#0x5e 
0x08e51 div    X,A 
0x08e52 halt 
Address Instruction 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
+
+
+
+
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/stm8-cycles/baseline/test.int_div.html sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/stm8-cycles/baseline/test.int_div.html
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/stm8-cycles/baseline/test.int_div.html	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/stm8-cycles/baseline/test.int_div.html	2022-01-18 09:48:32.000000000 +0000
@@ -0,0 +1,74 @@
+
+
+Interrupted div
+
+
+
+
+
+
+
+Interrupted div
+
+
+    
+    
+    
+    
+    
+    
+    
+    
+    
+Legend
Decode
Execute
Fetch
Flush
Fetch Stall - space in prefetch buffer but bus busy
Decode Stall - bus busy
Decode Stall - insufficient data in prefetch buffer
Decode Stall - read after write
+
+(Not currently implemented.)
+
+
+    
+        
+    
+    
+        
+    
+0x08201 div    X,A 
Address Instruction 1 2 3 4 5
+
+
+
+
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/stm8-cycles/baseline/test.table10.html sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/stm8-cycles/baseline/test.table10.html
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/stm8-cycles/baseline/test.table10.html	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/stm8-cycles/baseline/test.table10.html	2022-01-18 09:48:32.000000000 +0000
@@ -0,0 +1,92 @@
+
+
+PM0044 5.4.3 Pipeline with Call/Jump, table 10
+
+
+
+
+
+
+
+PM0044 5.4.3 Pipeline with Call/Jump, table 10
+
+
+    
+    
+    
+    
+    
+    
+    
+    
+    
+Legend
Decode
Execute
Fetch
Flush
Fetch Stall - space in prefetch buffer but bus busy
Decode Stall - bus busy
Decode Stall - insufficient data in prefetch buffer
Decode Stall - read after write
+
+PM0044 table 10 shows a fetch stall in the first execution cycle
+of the call (cycle 7) however it should be possible for a fetch
+to take place since pushing the return address only busies the
+data bus (and STM8 is a Harvard architecture with unified address
+space so the data and program are separate buses).
+Also note that since the flush happens on the last execute cycle
+of the call (unlike the jp) there is no overlap and we mark
+the following cycle as a decode stall. Technically this is correct
+but table 10 does not and says the call takes 3 cycles which
+ignores the unavoidable stall cycle. The later instruction documentation
+for call says it takes 4 cycles which is presumed to include the
+stall cycle that follows it.
+
+
+    
+        
+        
+        
+        
+        
+        
+        
+        
+    
+    
+        
+    
+ 
0x080c4 inc    A 
0x080c5 jp     0x80cc 
0x080cc neg    A 
0x080cd call   0x80d8 
0x080d8 incw   X 
Address Instruction 1 2 3 4 5 6 7 8 9 10 11
+
+
+
+
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/stm8-cycles/baseline/test.table12.html sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/stm8-cycles/baseline/test.table12.html
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/stm8-cycles/baseline/test.table12.html	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/stm8-cycles/baseline/test.table12.html	2022-01-18 09:48:32.000000000 +0000
@@ -0,0 +1,94 @@
+
+
+PM0044 5.4.4 Pipeline stalled, table 12
+
+
+
+
+
+
+
+PM0044 5.4.4 Pipeline stalled, table 12
+
+
+    
+    
+    
+    
+    
+    
+    
+    
+    
+Legend
Decode
Execute
Fetch
Flush
Fetch Stall - space in prefetch buffer but bus busy
Decode Stall - bus busy
Decode Stall - insufficient data in prefetch buffer
Decode Stall - read after write
+
+Errata
+
+Table 12 shows the BTJT as taking 1 decode, 2 execute cycles but the
+    later documention for the instruction implies the second execution
+    cycle is only used if the branch is taken - and this isn't.
+    
+Table 12 has a jump in time (cycles) from 4 straight to 7.
+    
+The last instruction is shown one cycle early in table 12. The decode stall
+    should line up with the execution cycle of the previous instruction
+    as the description above the table says.
+    
+
+
+
+    
+        
+        
+        
+        
+        
+        
+        
+        
+        
+    
+    
+        
+    
+ 
0x080e0 sub    SP,#0x14 
0x080e2 ld     A,#0x14 
0x080e4 btjt   0x0010,#5,0x80f8 
0x080e9 inc    A 
0x080ea btjf   0x0020,#3,0x80f8 
0x080f8 incw   Y 
0x080fa ld     A,(X) 
Address Instruction 1 2 3 4 5 6 7 8 9 10 11 12
+
+
+
+
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/stm8-cycles/baseline/test.table3.html sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/stm8-cycles/baseline/test.table3.html
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/stm8-cycles/baseline/test.table3.html	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/stm8-cycles/baseline/test.table3.html	2022-01-18 09:48:32.000000000 +0000
@@ -0,0 +1,88 @@
+
+
+PM0044 5.4 Conventions, table 3
+
+
+
+
+
+
+
+PM0044 5.4 Conventions, table 3
+
+
+    
+    
+    
+    
+    
+    
+    
+    
+    
+Legend
Decode
Execute
Fetch
Flush
Fetch Stall - space in prefetch buffer but bus busy
Decode Stall - bus busy
Decode Stall - insufficient data in prefetch buffer
Decode Stall - read after write
+
+Errata
+
+The LDW shown in PM0044 table 3 is missing a decode cycle.
+    

+    (Confirmed on HW)
+    
+The ADDW shown in PM0044 table 3 has one too many decode cycles.
+    

+    (Confirmed on HW)
+    
+The LD shown in PM0044 table 3 is missing a decode cycle.
+
+
+
+    
+        
+        
+        
+        
+    
+    
+        
+    
+ 
0x0808c ldw    X,[0x50.w] 
0x0808f addw   X,#0x0014 
0x08092 ld     A,[0x30.w] 
Address Instruction 1 2 3 4 5 6 7 8 9 10 11 12 13
+
+
+
+
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/stm8-cycles/baseline/test.table6.html sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/stm8-cycles/baseline/test.table6.html
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/stm8-cycles/baseline/test.table6.html	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/stm8-cycles/baseline/test.table6.html	2022-01-18 09:48:32.000000000 +0000
@@ -0,0 +1,85 @@
+
+
+PM0044 5.4.1 Optimized pipeline example - execution from flash, table 6
+
+
+
+
+
+
+
+PM0044 5.4.1 Optimized pipeline example - execution from flash, table 6
+
+
+    
+    
+    
+    
+    
+    
+    
+    
+    
+Legend
Decode
Execute
Fetch
Flush
Fetch Stall - space in prefetch buffer but bus busy
Decode Stall - bus busy
Decode Stall - insufficient data in prefetch buffer
Decode Stall - read after write
+
+
+
+    
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+    
+    
+        
+    
+ 
0x08098 neg    A 
0x08099 xor    A,0x10 
0x0809b ld     A,#0x14 
0x0809d sub    A,0x1000 
0x080a0 inc    A 
0x080a1 ld     XL,A 
0x080a2 srl    A 
0x080a3 swap   A 
0x080a4 sla    0x15 
0x080a6 cp     A,#0xfe 
0x080a8 mov    0x0100,#0x0b 
0x080ac mov    0x0101,#0x16 
Address Instruction 1 2 3 4 5 6 7 8 9 10 11 12 13 14
+
+
+
+
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/stm8-cycles/baseline/test.table8.html sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/stm8-cycles/baseline/test.table8.html
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/stm8-cycles/baseline/test.table8.html	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/stm8-cycles/baseline/test.table8.html	2022-01-18 09:48:32.000000000 +0000
@@ -0,0 +1,83 @@
+
+
+PM0044 5.4.2 Optimize pipeline example - execution from RAM, table 8
+
+
+
+
+
+
+
+PM0044 5.4.2 Optimize pipeline example - execution from RAM, table 8
+
+
+    
+    
+    
+    
+    
+    
+    
+    
+    
+Legend
Decode
Execute
Fetch
Flush
Fetch Stall - space in prefetch buffer but bus busy
Decode Stall - bus busy
Decode Stall - insufficient data in prefetch buffer
Decode Stall - read after write
+
+
+
+    
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+    
+    
+        
+    
+ 
0x00104 neg    A 
0x00105 xor    A,0x10 
0x00107 ld     A,#0x14 
0x00109 sub    A,0x1000 
0x0010c inc    A 
0x0010d ld     XL,A 
0x0010e srl    A 
0x0010f swap   A 
0x00110 sla    0x15 
0x00112 cp     A,#0xfe 
Address Instruction 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
+
+
+
+
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/stm8-cycles/Makefile sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/stm8-cycles/Makefile
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/stm8-cycles/Makefile	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/stm8-cycles/Makefile	2022-01-18 09:48:32.000000000 +0000
@@ -0,0 +1,11 @@
+DIFF_OPTS += -b
+OUTPUTS = stdout
+
+#CPU = stm8
+TYPE = S003
+
+$(OUTPUTS):	test.cmd test.ihx
+	$(call run-sim)
+
+
+include test-lib.mk
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/stm8-cycles/test.asm sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/stm8-cycles/test.asm
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/stm8-cycles/test.asm	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/stm8-cycles/test.asm	2022-01-18 09:48:32.000000000 +0000
@@ -0,0 +1,484 @@
+	; For an STM8S003
+
+	TIM4_CR1              =: 0x5340
+	TIM4_IER              =: 0x5343
+	TIM4_EGR              =: 0x5345
+	TIM4_ARR              =: 0x5348
+
+
+	.macro codebndry
+		.$.end =: .
+		.bndry 4
+		.$.diff =: . - .$.end
+		. = . - .$.diff
+		.rept .$.diff
+			nop
+		.endm
+	.endm
+
+	.macro areabndry n
+		.$.end =: .
+		.bndry n
+		.ifne . - .$.end
+			. = . - 1
+			.byte 0
+		.endif
+	.endm
+
+	.area _CODE (REL,CON)
+	int reset
+	int no_action
+	int no_action
+	int no_action
+	int no_action
+	int no_action
+	int no_action
+	int no_action
+	int no_action
+	int no_action
+	int no_action
+	int no_action
+	int no_action
+	int no_action
+	int no_action
+	int no_action
+	int no_action
+	int no_action
+	int no_action
+	int no_action
+	int no_action
+	int no_action
+	int no_action
+	int no_action
+	int no_action
+	int no_action
+	int no_action
+no_action:
+	iret
+	codebndry
+	.area INITIALIZER (REL,CON)
+	.area CODE (REL,CON)
+	codebndry
+
+reset:
+	; PM0044 5.4 Conventions, table 3
+	; N.B. PM004 cannot be right. Table 3 disagrees with the section 7 documentation for ADDW.
+	; Table 4 has cycle counts for ADDW that disagree with the time graph on the right.
+	jra table3
+	codebndry
+table3:	ldw x,[0x50]
+	addw x,#20
+	ld a,[0x30]
+table3_end:
+
+	; PM0044 5.4.1 Optimized pipeline example, table 6
+	; N.B. Table 6 has the final F3 load one cycle too early surely?
+	jra table6
+	codebndry
+table6:	neg a
+	xor a, 0x10
+	ld a, #20
+	sub a, 0x1000
+	inc a
+	ld xl, a
+	srl a
+	swap a
+	sla 0x15
+	cp a, #0xfe
+	mov 0x100, #11
+	mov 0x101, #22
+table6_end:
+
+	; PM0044 5.4.2 Optimize pipeline example - execution from RAM, table 8 (requires copy to RAM)
+table8_copy:
+	ldw x, #table8_end - table8_start
+	jreq table8_copy_end
+table8_copy_loop:
+	ld a, (table8_start - 1, x)
+	ld (0x100 - 1, x), a
+	decw x
+	jrne table8_copy_loop
+table8_copy_end:
+	call 0x100
+
+	codebndry
+	.area INITIALIZER
+	codebndry
+table8_start:
+	jra table8
+	codebndry
+table8:	neg a
+	xor a, 0x10
+	ld a, #20
+	sub a, 0x1000
+	inc a
+	ld xl, a
+	srl a
+	swap a
+	sla 0x15
+	cp a, #0xfe
+	ret
+table8_end:
+	codebndry
+	.area CODE
+	codebndry
+
+	; PM0044 5.4.3 Pipeline with Call/Jump, table 10
+	jra table10
+	codebndry
+table10:
+	inc a
+	jp label
+	ldw x, [0x5432]
+label:	neg a
+	call label2
+	ldw x, [0x5432]
+	ldw x, [0x7895]
+label2:	incw x
+table10_end:
+
+	; PM0044 5.4.4 Pipeline stalled, table 12
+	clr a
+	ld 0x10, a
+	ld 0x20, a		; Table 12 doesn't include any setup...
+	jra table12
+	codebndry
+table12:
+	sub sp, #20
+	ld a, #20
+	btjt 0x10, #5, to	; Table 12 assumes not taken
+	inc a
+	btjf 0x20, #3, to	; Table 12 assumes taken
+	nop
+	ldw x, [0x5432]
+	ldw x, [0x1234]
+to:	incw y
+	ld a, (x)
+table12_end:
+
+	; DIV tests - available ST docs simply say "2-17 cycles"
+	.macro timed_div dividend divisor ?aligned
+		jra aligned
+		codebndry
+aligned:
+		ldw x, #dividend
+		ld a, #divisor
+		div x, a
+end_'aligned:
+	.endm
+
+	timed_div 0x8000,0x80
+	timed_div 0x8000,0x40
+	timed_div 0x8000,0x20
+	timed_div 0x8000,0x10
+	timed_div 0x8000,0x08
+	timed_div 0x8000,0x04
+	timed_div 0x8000,0x02
+	timed_div 0x8000,0x01
+
+	timed_div 0x8000,0x80
+	timed_div 0x4000,0x80
+	timed_div 0x2000,0x80
+	timed_div 0x1000,0x80
+	timed_div 0x0800,0x80
+	timed_div 0x0400,0x80
+	timed_div 0x0200,0x80
+	timed_div 0x0100,0x80
+	timed_div 0x0080,0x80
+	timed_div 0x0040,0x80
+	timed_div 0x0020,0x80
+	timed_div 0x0010,0x80
+	timed_div 0x0008,0x80
+	timed_div 0x0004,0x80
+	timed_div 0x0002,0x80
+	timed_div 0x0001,0x80
+	timed_div 0x0000,0x80
+
+	timed_div 63, 8
+	timed_div 64, 8
+	timed_div 65, 8
+
+	.macro timed_divw dividend divisor ?aligned
+		jra aligned
+		codebndry
+aligned:
+		ldw x, #dividend
+		ldw y, #divisor
+		divw x, y
+end_'aligned:
+	.endm
+
+	timed_divw 0x8000, 1
+
+	; Interrupted div
+	jra test_idiv
+	codebndry
+test_idiv:
+	bset TIM4_IER, #0
+	bset TIM4_EGR, #0
+	mov TIM4_ARR, #8
+	ldw x, #255
+	ld a, #10
+	mov TIM4_CR1, #0x0f
+	div x, a
+
+	; Exercising all code in stm8.cc + inst.cc
+	.macro timed_op op operand1 operand2a operand2b ?aligned
+		jra aligned
+		codebndry
+aligned:
+		.narg .narg
+		.ifeq .narg - 4
+				op operand1,operand2a,operand2b
+		.else
+			.ifeq .narg - 3
+				op operand1,operand2a
+			.else
+				.ifeq .narg - 2
+					op operand1
+				.else
+					op
+				.endif
+			.endif
+		.endif
+end_'aligned:
+	.endm
+
+	; a, shortmem, longmem,
+	; (X), (shortoff,X), (longoff,X)
+	; (Y), (shortoff,Y), (longoff,Y)
+	; (shortoff,SP)
+	; ([shortptr.w],X), ([longptr.w],X)
+	; ([shortptr.w],X), ([longptr.w],X)
+	; ([shortptr.w],Y)
+	.macro timed_class_1 op
+		timed_op op a
+		timed_op op 0xf5
+		timed_op op 0xf5c2
+		.irp reg,X,Y
+			timed_op op (reg)
+			timed_op op (0xf5,reg)
+			timed_op op (0xf5c2,reg)
+		.endm
+		timed_op op (0xf5,SP)
+		timed_op op [0xf5]
+		timed_op op [0xf5c2]
+		timed_op op ([0xf5],X)
+		timed_op op ([0xf5c2],X)
+		timed_op op ([0xf5],Y)
+	.endm
+
+	; a <- #byte, shortmem, longmem,
+	;      (X), (shortoff,X), (longoff,X)
+	;      (Y), (shortoff,Y), (longoff,Y)
+	;      (shortoff,SP)
+	;      ([shortptr.w],X), ([longptr.w],X)
+	;      ([shortptr.w],X), ([longptr.w],X)
+	;      ([shortptr.w],Y)
+	.macro timed_class_2 op
+		timed_op op a,#0x55
+		timed_op op a,0x10
+		timed_op op a,0x1000
+		.irp reg,X,Y
+			timed_op op a,(reg)
+			timed_op op a,(0x10,reg)
+			timed_op op a,(0x1000,reg)
+		.endm
+		timed_op op a,(0x10,SP)
+		timed_op op a,[0x10]
+		timed_op op a,[0x1000]
+		timed_op op a,([0x10],X)
+		timed_op op a,([0x1000],X)
+		timed_op op a,([0x10],Y)
+	.endm
+
+	; SP <- #byte
+	.macro timed_class_sp_imm op
+		timed_op op sp,#0x55
+	.endm
+
+	; X, Y
+	.macro timed_class_xy op
+		timed_op op X
+		timed_op op Y
+	.endm
+
+	; Bit addressed
+	.macro timed_class_bit op
+		timed_op op 0x1000,#2
+	.endm
+
+	; Inherent
+	.macro timed_class_inh op
+		timed_op op
+	.endm
+
+	timed_class_2 adc
+	timed_class_2 add
+	timed_op addw X,#0x1000
+	timed_op addw X,0x1000
+	timed_op addw X,(0x10,SP)
+	timed_op addw Y,#0x1000
+	timed_op addw Y,0x1000
+	timed_op addw Y,(0x10,SP)
+	timed_class_sp_imm addw
+	timed_class_2 and
+	timed_class_bit bccm
+	timed_class_2 bcp
+	timed_class_bit bcpl
+	;break
+	timed_class_bit bres
+	timed_class_bit bset
+	;btjf    - covered by table 12 above
+	;btjt    - covered by table 12 above
+	;call    - uses common fetchea code
+	;callf
+	;callr
+	timed_class_inh ccf
+	timed_class_1 clr
+	timed_class_xy clrw
+	timed_class_2 cp
+	timed_op cpw X,#0x55
+	timed_op cpw X,0x10
+	timed_op cpw X,0x1000
+	timed_op cpw X,(Y)
+	timed_op cpw X,(0x10,Y)
+	timed_op cpw X,(0x1000,Y)
+	timed_op cpw X,(0x10,SP)
+	timed_op cpw X,[0x10]
+	timed_op cpw X,[0x1000]
+	timed_op cpw X,([0x10],Y)
+	timed_op cpw Y,([0x1000],X)
+	timed_class_1 cpl
+	timed_class_xy cplw
+	timed_class_1 dec
+	timed_class_xy decw
+;	;div     - covered above
+;	;divw    - covered above
+	timed_op exg a,xl
+	timed_op exg a,yl
+	timed_op exg a,0x1000
+	timed_op exgw x,y
+	;halt
+	timed_class_1 inc
+	timed_class_xy incw
+	;int
+	;iret
+	;jp      -covered by table 10 above
+	;jpf
+	;jra
+	;jrxx
+	timed_class_2 ld
+	timed_op ld 0x10,a
+	timed_op ld 0x1000,a
+	timed_op ld (X),a
+	timed_op ld (0x10,X),a
+	timed_op ld (0x1000,X),a
+	timed_op ld (Y),a
+	timed_op ld (0x10,Y),a
+	timed_op ld (0x1000,Y),a
+	timed_op ld (0x10,SP),a
+	timed_op ld [0x10],a
+	timed_op ld [0x1000],a
+	timed_op ld ([0x10],X),a
+	timed_op ld ([0x1000],X),a
+	timed_op ld ([0x10],Y),a
+	timed_op ldf a,0x500000
+	timed_op ldf a,(0x500000,X)
+	timed_op ldf a,(0x500000,Y)
+	timed_op ldf a,([0x5000],X)
+	timed_op ldf a,([0x5000],Y)
+	timed_op ldf a,[0x5000]
+	timed_op ldw X,#0x55
+	timed_op ldw X,0x10
+	timed_op ldw X,0x1000
+	timed_op ldw X,(X)
+	timed_op ldw X,(0x10,X)
+	timed_op ldw X,(0x1000,X)
+	timed_op ldw X,(0x10,SP)
+	timed_op ldw X,[0x10]
+	timed_op ldw X,[0x1000]
+	timed_op ldw X,([0x10],X)
+	timed_op ldw X,([0x1000],X)
+	timed_op mov 0x8000,#0xAA
+	timed_op mov 0x80,0x10
+	timed_op mov 0x8000,0x1000
+	timed_op mul x,a
+	timed_class_1 neg
+	timed_class_xy negw
+	timed_op nop
+	timed_class_2 or
+	;pop
+	;popw
+	;push
+	;pushw
+	timed_class_inh rcf
+	;ret
+	;retf
+;	timed_class_inh rim
+	timed_class_1 rlc
+	timed_class_xy rlcw
+	timed_class_xy rlwa
+	timed_class_1 rrc
+	timed_class_xy rrcw
+	timed_class_xy rrwa
+	timed_class_inh rvf
+	timed_class_2 sbc
+	timed_class_inh scf
+;	timed_class_inh sim
+	timed_op subw X,#0x5500
+	timed_op subw X,0x1000
+	timed_op subw X,(0x10,SP)
+	timed_op ldw Y,X
+	timed_op ldw 0x10,X
+	timed_op ldw 0x1000,X
+	timed_op ldw (X),Y
+	timed_op ldw (0x10,X),Y
+	timed_op ldw (0x1000,X),Y
+	timed_op ldw (0x10,SP),X
+	timed_op ldw [0x10],X
+	timed_op ldw [0x1000],X
+	timed_op ldw ([0x10],X),Y
+	timed_op ldw ([0x1000],X),Y
+	timed_class_1 sla
+	timed_class_xy slaw
+	timed_class_1 sll
+	timed_class_xy sllw
+	timed_class_1 sra
+	timed_class_xy sraw
+	timed_class_1 srl
+	timed_class_xy srlw
+	timed_class_2 sub
+	timed_class_sp_imm sub
+	timed_class_1 swap
+	timed_class_xy swapw
+	timed_class_1 tnz
+	timed_class_xy tnzw
+	;trap
+	;wfe
+	;wfi
+	timed_class_2 xor
+
+	dividend = 0x8000
+	.rept 15
+		timed_div dividend,0x02
+		dividend = dividend >> 1
+	.endm
+
+	dividend = 0x10000
+	.rept 15
+		timed_div dividend-1,0x02
+		dividend = dividend >> 1
+	.endm
+
+	timed_div 0x2000 0x02
+	timed_div 0x2040 0x02
+	timed_div 0x2048 0x02
+	timed_div 0x2148 0x02
+	timed_div 0x21c8 0x02
+
+	timed_div 45831 94
+
+end:
+	halt
+	.area _DATA
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/stm8-cycles/test.cmd sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/stm8-cycles/test.cmd
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/stm8-cycles/test.cmd	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/stm8-cycles/test.cmd	2022-01-24 11:09:43.000000000 +0000
@@ -0,0 +1,241 @@
+# We don't want auto-generated labels in the output.
+set option analyzer false
+
+step
+
+# The pipelined examples from PM0044 5.4 are run with fold-on-flush off
+# so that they can be compared with the documentation easily.
+set hw cpu pipetrace fold off
+
+step
+set hw cpu pipetrace title "PM0044 5.4 Conventions, table 3"
+set hw cpu pipetrace start "out/test.table3.html"
+set hw cpu pipetrace data "Errata"
+set hw cpu pipetrace data ""
+set hw cpu pipetrace data "The LDW shown in PM0044 table 3 is missing a decode cycle."
+set hw cpu pipetrace data "    
"
+set hw cpu pipetrace data "    (Confirmed on HW)"
+set hw cpu pipetrace data "    "
+set hw cpu pipetrace data "The ADDW shown in PM0044 table 3 has one too many decode cycles."
+set hw cpu pipetrace data "    
"
+set hw cpu pipetrace data "    (Confirmed on HW)"
+set hw cpu pipetrace data "    "
+set hw cpu pipetrace data "The LD shown in PM0044 table 3 is missing a decode cycle."
+set hw cpu pipetrace data ""
+step 3
+set hw cpu pipetrace stop
+
+step
+set hw cpu pipetrace title "PM0044 5.4.1 Optimized pipeline example - execution from flash, table 6"
+set hw cpu pipetrace start "out/test.table6.html"
+step 12
+set hw cpu pipetrace stop
+
+break 0x0100
+cont
+
+step
+set hw cpu pipetrace title "PM0044 5.4.2 Optimize pipeline example - execution from RAM, table 8"
+set hw cpu pipetrace start "out/test.table8.html"
+step 10
+set hw cpu pipetrace stop
+step
+
+
+step
+set hw cpu pipetrace title "PM0044 5.4.3 Pipeline with Call/Jump, table 10"
+set hw cpu pipetrace start "out/test.table10.html"
+set hw cpu pipetrace data "PM0044 table 10 shows a fetch stall in the first execution cycle"
+set hw cpu pipetrace data "of the call (cycle 7) however it should be possible for a fetch"
+set hw cpu pipetrace data "to take place since pushing the return address only busies the"
+set hw cpu pipetrace data "data bus (and STM8 is a Harvard architecture with unified address"
+set hw cpu pipetrace data "space so the data and program are separate buses)."
+set hw cpu pipetrace data "Also note that since the flush happens on the last execute cycle"
+set hw cpu pipetrace data "of the call (unlike the jp) there is no overlap and we mark"
+set hw cpu pipetrace data "the following cycle as a decode stall. Technically this is correct"
+set hw cpu pipetrace data "but table 10 does not and says the call takes 3 cycles which"
+set hw cpu pipetrace data "ignores the unavoidable stall cycle. The later instruction documentation"
+set hw cpu pipetrace data "for call says it takes 4 cycles which is presumed to include the"
+set hw cpu pipetrace data "stall cycle that follows it."
+step 5
+set hw cpu pipetrace stop
+
+
+step 4
+set hw cpu pipetrace title "PM0044 5.4.4 Pipeline stalled, table 12"
+set hw cpu pipetrace start "out/test.table12.html"
+set hw cpu pipetrace data "Errata"
+set hw cpu pipetrace data ""
+set hw cpu pipetrace data "Table 12 shows the BTJT as taking 1 decode, 2 execute cycles but the"
+set hw cpu pipetrace data "    later documention for the instruction implies the second execution"
+set hw cpu pipetrace data "    cycle is only used if the branch is taken - and this isn't."
+set hw cpu pipetrace data "    "
+set hw cpu pipetrace data "Table 12 has a jump in time (cycles) from 4 straight to 7."
+set hw cpu pipetrace data "    "
+set hw cpu pipetrace data "The last instruction is shown one cycle early in table 12. The decode stall"
+set hw cpu pipetrace data "    should line up with the execution cycle of the previous instruction"
+set hw cpu pipetrace data "    as the description above the table says."
+set hw cpu pipetrace data "    "
+set hw cpu pipetrace data ""
+step 7
+set hw cpu pipetrace stop
+
+
+# Everything else needs to be folded on flush or it could go sideways very quickly.
+set hw cpu pipetrace fold on
+
+set hw cpu pipetrace title "DIV tests - available ST docs simply say '2-17 cycles'"
+set hw cpu pipetrace start "out/test.div.html"
+set hw cpu pipetrace data "The stated cycle count would seem to imply binary long division and"
+set hw cpu pipetrace data "   this is how the STM8 emulator in ucsim currently treats div for."
+set hw cpu pipetrace data "   cycle counting. However the cycles measured on actual hardware
+set hw cpu pipetrace data "   suggest this is not correct."
+set hw cpu pipetrace data ""
+
+set hw cpu pipetrace pause
+step
+set hw cpu pipetrace resume
+step 3
+set hw cpu pipetrace pause
+step
+set hw cpu pipetrace resume
+step 3
+set hw cpu pipetrace pause
+step
+set hw cpu pipetrace resume
+step 3
+set hw cpu pipetrace pause
+step
+set hw cpu pipetrace resume
+step 3
+set hw cpu pipetrace pause
+step
+set hw cpu pipetrace resume
+step 3
+set hw cpu pipetrace pause
+step
+set hw cpu pipetrace resume
+step 3
+set hw cpu pipetrace pause
+step
+set hw cpu pipetrace resume
+step 3
+set hw cpu pipetrace pause
+step
+set hw cpu pipetrace resume
+step 3
+
+set hw cpu pipetrace pause
+step
+set hw cpu pipetrace resume
+step 3
+set hw cpu pipetrace pause
+step
+set hw cpu pipetrace resume
+step 3
+set hw cpu pipetrace pause
+step
+set hw cpu pipetrace resume
+step 3
+set hw cpu pipetrace pause
+step
+set hw cpu pipetrace resume
+step 3
+set hw cpu pipetrace pause
+step
+set hw cpu pipetrace resume
+step 3
+set hw cpu pipetrace pause
+step
+set hw cpu pipetrace resume
+step 3
+set hw cpu pipetrace pause
+step
+set hw cpu pipetrace resume
+step 3
+set hw cpu pipetrace pause
+step
+set hw cpu pipetrace resume
+step 3
+set hw cpu pipetrace pause
+step
+set hw cpu pipetrace resume
+step 3
+set hw cpu pipetrace pause
+step
+set hw cpu pipetrace resume
+step 3
+set hw cpu pipetrace pause
+step
+set hw cpu pipetrace resume
+step 3
+set hw cpu pipetrace pause
+step
+set hw cpu pipetrace resume
+step 3
+set hw cpu pipetrace pause
+step
+set hw cpu pipetrace resume
+step 3
+set hw cpu pipetrace pause
+step
+set hw cpu pipetrace resume
+step 3
+set hw cpu pipetrace pause
+step
+set hw cpu pipetrace resume
+step 3
+set hw cpu pipetrace pause
+step
+set hw cpu pipetrace resume
+step 3
+set hw cpu pipetrace pause
+step
+set hw cpu pipetrace resume
+step 3
+
+set hw cpu pipetrace pause
+step
+set hw cpu pipetrace resume
+step 3
+set hw cpu pipetrace pause
+step
+set hw cpu pipetrace resume
+step 3
+set hw cpu pipetrace pause
+step
+set hw cpu pipetrace resume
+step 3
+
+set hw cpu pipetrace pause
+step
+set hw cpu pipetrace resume
+step 3
+
+set hw cpu pipetrace stop
+
+
+step 7
+
+set hw cpu pipetrace title "Interrupted div"
+set hw cpu pipetrace start "out/test.int_div.html"
+set hw cpu pipetrace data "(Not currently implemented.)"
+# FIXME: once we have timer interrupts emulated correctly we need to add
+# the interrupt instructions to the following step count.
+#step 4
+step
+set hw cpu pipetrace stop
+
+step
+
+set hw cpu pipetrace title "All instructions and addressing modes"
+set hw cpu pipetrace start "out/test.instrs.html"
+set hw cpu pipetrace data "Note that timings given in PM0044 assume a 1 cycle overlap"
+set hw cpu pipetrace data "with the previous instruction and are specified as being"
+set hw cpu pipetrace data "one cycle less than they are in the no prefetch/stall case."
+set hw cpu pipetrace data "Instructions that flush the prefetch buffer such as jumps"
+set hw cpu pipetrace data "prevent the overlap with the following instruction. The cycle"
+set hw cpu pipetrace data "count for these instructions includes the extra cycles for"
+set hw cpu pipetrace data "the unavoidable fetches and stalls that follow them."
+cont
+set hw cpu pipetrace stop
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/stm8-cycles/test.ihx sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/stm8-cycles/test.ihx
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/stm8-cycles/test.ihx	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/stm8-cycles/test.ihx	2022-01-18 09:48:32.000000000 +0000
@@ -0,0 +1,358 @@
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diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/stm8.h sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/stm8.h
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/stm8.h	2018-01-25 13:48:09.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/stm8.h	1970-01-01 00:00:00.000000000 +0000
@@ -1,798 +0,0 @@
-#ifndef STM8_HEADER
-#define STM8_HEADER
-
-#include "stdint.h"
-
-/* DEVICES 
- */
-
-#define DEV_STM8S903	0x00000001
-#define DEV_STM8S003	0x00000002
-#define DEV_STM8S005	0x00000004
-#define DEV_STM8S007	0x00000008
-#define DEV_STM8S103	0x00000010
-#define DEV_STM8S105	0x00000020
-#define DEV_STM8S207	0x00000040
-#define DEV_STM8S208	0x00000080
-#define DEV_STM8S	(DEV_STM8S903|\
-			 DEV_STM8S003|\
-			 DEV_STM8S005|\
-			 DEV_STM8S007|\
-			 DEV_STM8S103|\
-			 DEV_STM8S105|\
-			 DEV_STM8S207|\
-			 DEV_STM8S208)
-
-#define DEV_STM8AF52	0x00000100
-#define DEV_STM8AF62_12	0x00000200
-#define DEV_STM8AF62_46	0x00000400
-#define DEV_STM8AF	(DEV_STM8AF52|\
-			 DEV_STM8AF62_12|\
-			 DEV_STM8AF62_46)
-
-#define DEV_STM8SAF	(DEV_STM8S|DEV_STM8AF)
-
-#define DEV_STM8AL3xE	0x00010000
-#define DEV_STM8AL3x8	0x00020000
-#define DEV_STM8AL3x346	0x00040000
-#define DEV_STM8AL	(DEV_STM8AL3xE|\
-			 DEV_STM8AL3x8|\
-			 DEV_STM8AL3x346)
-
-#define DEV_STM8L051	0x01000000
-#define DEV_STM8L052C	0x02000000
-#define DEV_STM8L052R	0x04000000
-#define DEV_STM8L151x23	0x08000000
-#define DEV_STM8L15x46	0x10000000
-#define DEV_STM8L15x8	0x20000000
-#define DEV_STM8L162	0x40000000
-
-#define DEV_STM8L	(DEV_STM8L051|\
-			 DEV_STM8L052C|\
-			 DEV_STM8L052R|\
-			 DEV_STM8L151x23|\
-			 DEV_STM8L15x46|\
-			 DEV_STM8L15x8|\
-			 DEV_STM8L162)
-
-#define DEV_STM8ALL	(DEV_STM8AL|DEV_STM8L)
-
-#define DEV_STM8L101	0x00001000
-
-#define DEV_STM8LDISC	DEV_STM8L15x46
-#define DEV_LDISC	DEV_STM8L15x46
-#define DEV_STM8SDISC	DEV_STM8S105
-#define DEV_SDISC	DEV_STM8S105
-
-#ifndef DEVICE
-#define DEVICE DEV_STM8S208
-#endif
-
-//#define CLK_DIVR	(*(volatile uint8_t *)0x50c6)
-//#define CLK_PCKENR1	(*(volatile uint8_t *)0x50c7)
-
-
-//#define UART2_SR	(*(volatile uint8_t *)0x5240)
-//#define UART2_DR	(*(volatile uint8_t *)0x5241)
-//#define UART2_BRR1	(*(volatile uint8_t *)0x5242)
-//#define UART2_BRR2	(*(volatile uint8_t *)0x5243)
-//#define UART2_CR2	(*(volatile uint8_t *)0x5245)
-//#define UART2_CR3	(*(volatile uint8_t *)0x5246)
-
-//#define UART_CR2_TEN (1 << 3)
-//#define UART_CR2_REN (1 << 2)
-//#define UART_CR2_RIEN (1 << 5)
-//#define UART_CR3_STOP2 (1 << 5)
-//#define UART_CR3_STOP1 (1 << 4)
-//#define UART_SR_TXE (1 << 7)
-//#define UART_SR_RXNE (1 << 5)
-
-
-/* GPIO
- */
-
-struct GPIO_t {
-  volatile uint8_t odr;
-  volatile uint8_t idr;
-  volatile uint8_t ddr;
-  volatile uint8_t cr1;
-  volatile uint8_t cr2;
-};
-
-#define GPIOA ((struct GPIO_t *)0x5000)
-#define GPIOB ((struct GPIO_t *)0x5005)
-#define GPIOC ((struct GPIO_t *)0x500A)
-#define GPIOD ((struct GPIO_t *)0x500F)
-#if (DEVICE & DEV_STM8SAF) || \
-  (DEVICE & DEV_STM8AL) || \
-  (DEVICE & DEV_STM8L052C) || \
-  (DEVICE & DEV_STM8L052R) || \
-  (DEVICE & DEV_STM8L151x23) || \
-  (DEVICE & DEV_STM8L15x46) || \
-  (DEVICE & DEV_STM8L15x8) || \
-  (DEVICE & DEV_STM8L162)
-#define GPIOE ((struct GPIO_t *)0x5014)
-#define GPIOF ((struct GPIO_t *)0x5019)
-#endif
-#if (DEVICE & DEV_STM8S005) || \
-  (DEVICE & DEV_STM8S007) || \
-  (DEVICE & DEV_STM8S105) || \
-  (DEVICE & DEV_STM8S207) || \
-  (DEVICE & DEV_STM8S208) || \
-  (DEVICE & DEV_STM8AF52) || \
-  (DEVICE & DEV_STM8AF62_46) || \
-  (DEVICE & DEV_STM8AL3xE) || \
-  (DEVICE & DEV_STM8AL3x8) || \
-  (DEVICE & DEV_STM8L052R) || \
-  (DEVICE & DEV_STM8L15x8) || \
-  (DEVICE & DEV_STM8L162)
-#define GPIOG ((struct GPIO_t *)0x501E)
-#endif
-#if (DEVICE & DEV_STM8S005) || \
-  (DEVICE & DEV_STM8S007) || \
-  (DEVICE & DEV_STM8S105) || \
-  (DEVICE & DEV_STM8S207) || \
-  (DEVICE & DEV_STM8S208) || \
-  (DEVICE & DEV_STM8AF52) || \
-  (DEVICE & DEV_STM8AL3xE) || \
-  (DEVICE & DEV_STM8AL3x8) || \
-  (DEVICE & DEV_STM8L15x8) || \
-  (DEVICE & DEV_STM8L162)
-#define  GPIOH ((struct GPIO_t *)0x5023)
-#define  GPIOI ((struct GPIO_t *)0x5028)
-#endif
-
-
-/* Timers
- */
-
-/* bits of control 1 register */
-#define TIM_CR1_CEN	(1 << 0)
-
-/* Bits of interrupt enable register */
-#define TIM_IER_UIE	(1 << 0)
-
-/* Bits of interrupt flag register */
-#define TIM_SR1_UIF	(1 << 0)
-
-/* Bits of event generator register */
-#define TIM_EGR_UG	(1 << 0)
-
-/* TIM1
- */
-
-#if (DEVICE & DEV_STM8SAF)
-struct TIM1_t {
-  volatile uint8_t cr1;		//=  0;
-  volatile uint8_t cr2;		//=  1;
-  volatile uint8_t smcr;	//=  2;
-  volatile uint8_t etr;		//=  3;
-  volatile uint8_t ier;		//=  4;
-  volatile uint8_t sr1;		//=  5;
-  volatile uint8_t sr2;		//=  6;
-  volatile uint8_t egr;		//=  7;
-  volatile uint8_t ccmr1;	//=  8;
-  volatile uint8_t ccmr2;	//=  9;
-  volatile uint8_t ccmr3;	//= 10;
-  volatile uint8_t ccmr4;	//= 11;
-  volatile uint8_t ccer1;	//= 12;
-  volatile uint8_t ccer2;	//= 13;
-  volatile uint8_t cntrh;	//= 14;
-  volatile uint8_t cntrl;	//= 15;
-  volatile uint8_t pscrh;	//= 16;
-  volatile uint8_t pscrl;	//= 17;
-  volatile uint8_t arrh;	//= 18;
-  volatile uint8_t arrl;	//= 19;
-  volatile uint8_t rcr;		//= 20;
-  volatile uint8_t ccr1h;	//= 21;
-  volatile uint8_t ccr1l;	//= 22;
-  volatile uint8_t ccr2h;	//= 23;
-  volatile uint8_t ccr2l;	//= 24;
-  volatile uint8_t ccr3h;	//= 25;
-  volatile uint8_t ccr3l;	//= 26;
-  volatile uint8_t ccr4h;	//= 27;
-  volatile uint8_t ccr4l;	//= 28;
-  volatile uint8_t bkr;		//= 29;
-  volatile uint8_t dtr;		//= 30;
-  volatile uint8_t oisr;	//= 31;
-};
-#define TIM1_UP_IRQ	11
-#define TIM1_CC_IRQ	12
-#elif (DEVICE & DEV_STM8ALL)
-struct TIM1_t {
-  volatile uint8_t cr1;		//=  0;
-  volatile uint8_t cr2;		//=  1;
-  volatile uint8_t smcr;	//=  2;
-  volatile uint8_t etr;		//=  3;
-  volatile uint8_t der;         //=  4;
-  volatile uint8_t ier;		//=  5;
-  volatile uint8_t sr1;		//=  6;
-  volatile uint8_t sr2;		//=  7;
-  volatile uint8_t egr;		//=  8;
-  volatile uint8_t ccmr1;	//=  9;
-  volatile uint8_t ccmr2;	//= 10;
-  volatile uint8_t ccmr3;	//= 11;
-  volatile uint8_t ccmr4;	//= 12;
-  volatile uint8_t ccer1;	//= 13;
-  volatile uint8_t ccer2;	//= 14;
-  volatile uint8_t cntrh;	//= 15;
-  volatile uint8_t cntrl;	//= 16;
-  volatile uint8_t pscrh;	//= 17;
-  volatile uint8_t pscrl;	//= 18;
-  volatile uint8_t arrh;	//= 19;
-  volatile uint8_t arrl;	//= 20;
-  volatile uint8_t rcr;		//= 21;
-  volatile uint8_t ccr1h;	//= 22;
-  volatile uint8_t ccr1l;	//= 23;
-  volatile uint8_t ccr2h;	//= 24;
-  volatile uint8_t ccr2l;	//= 25;
-  volatile uint8_t ccr3h;	//= 26;
-  volatile uint8_t ccr3l;	//= 27;
-  volatile uint8_t ccr4h;	//= 28;
-  volatile uint8_t ccr4l;	//= 29;
-  volatile uint8_t bkr;		//= 30;
-  volatile uint8_t dtr;		//= 31;
-  volatile uint8_t oisr;	//= 32;
-};
-#define TIM1_UP_IRQ	23
-#define TIM1_CC_IRQ	24
-#endif
-
-#if (DEVICE & DEV_STM8S) || (DEVICE & DEV_STM8AF)
-#define TIM1 ((struct TIM1_t *)0x5250)
-#endif
-#if (DEVICE & DEV_STM8AL) || \
-  (DEVICE & DEV_STM8L052C) || \
-  (DEVICE & DEV_STM8L052R) || \
-  (DEVICE & DEV_STM8L15x46) || \
-  (DEVICE & DEV_STM8L15x8) || \
-  (DEVICE & DEV_STM8L162)
-#define TIM1 ((struct TIM1_t *)0x52B0)
-#endif
-
-/* TIM2
- */
-
-#if ((DEVICE & DEV_STM8S005) || \
-     (DEVICE & DEV_STM8S007) || \
-     (DEVICE & DEV_STM8S105) || \
-     (DEVICE & DEV_STM8S207) || \
-     (DEVICE & DEV_STM8S208) || \
-     (DEVICE & DEV_STM8AF52) ||	\
-     (DEVICE & DEV_STM8AF62_46))
-struct TIM2_t {
-  volatile uint8_t cr1;		//=  0;
-  volatile uint8_t ier;		//=  1;
-  volatile uint8_t sr1;		//=  2;
-  volatile uint8_t sr2;		//=  3;
-  volatile uint8_t egr;		//=  4;
-  volatile uint8_t ccmr1;	//=  5;
-  volatile uint8_t ccmr2;	//=  6;
-  volatile uint8_t ccmr3;	//=  7;
-  volatile uint8_t ccer1;	//=  8;
-  volatile uint8_t ccer2;	//=  9;
-  volatile uint8_t cntrh;	//= 10;
-  volatile uint8_t cntrl;	//= 11;
-  volatile uint8_t pscrl;	//= 12;
-  volatile uint8_t arrh;	//= 13;
-  volatile uint8_t arrl;	//= 14;
-  volatile uint8_t ccr1h;	//= 15;
-  volatile uint8_t ccr1l;	//= 0x10;
-  volatile uint8_t ccr2h;	//= 0x11;
-  volatile uint8_t ccr2l;	//= 0x12;
-  volatile uint8_t ccr3h;	//= 0x13;
-  volatile uint8_t ccr3l;	//= 0x14;
-};
-#define TIM2_UP_IRQ 13
-#define TIM2_CC_IRQ 14
-#define TIM2 ((struct TIM2_t *)0x5300)
-#elif ((DEVICE & DEV_STM8S003) || \
-       (DEVICE & DEV_STM8S103))
-struct TIM2_t {
-  volatile uint8_t cr1;		//=  0;
-  volatile uint8_t _dummy1;	//=  1;
-  volatile uint8_t _dummy2;	//=  2;
-  volatile uint8_t ier;		//=  3;
-  volatile uint8_t sr1;		//=  4;
-  volatile uint8_t sr2;		//=  5;
-  volatile uint8_t egr;		//=  6;
-  volatile uint8_t ccmr1;	//=  7;
-  volatile uint8_t ccmr2;	//=  8;
-  volatile uint8_t ccmr3;	//=  9;
-  volatile uint8_t ccer1;	//= 10;
-  volatile uint8_t ccer2;	//= 11;
-  volatile uint8_t cntrh;	//= 12;
-  volatile uint8_t cntrl;	//= 13;
-  volatile uint8_t pscrl;	//= 14;
-  volatile uint8_t arrh;	//= 15;
-  volatile uint8_t arrl;	//= 16;
-  volatile uint8_t ccr1h;	//= 0x11;
-  volatile uint8_t ccr1l;	//= 0x12;
-  volatile uint8_t ccr2h;	//= 0x13;
-  volatile uint8_t ccr2l;	//= 0x14;
-  volatile uint8_t ccr3h;	//= 0x15;
-  volatile uint8_t ccr3l;	//= 0x16;
-};
-#define TIM2_UP_IRQ 13
-#define TIM2_CC_IRQ 14
-#define TIM2 ((struct TIM2_t *)0x5300)
-#elif (DEVICE & DEV_STM8ALL)
-struct TIM2_t {
-  volatile uint8_t cr1;		//=  0;
-  volatile uint8_t cr2;		//=  1;
-  volatile uint8_t smcr;	//=  2;
-  volatile uint8_t etr;		//=  3;
-  volatile uint8_t der;		//=  4;
-  volatile uint8_t ier;		//=  5;
-  volatile uint8_t sr1;		//=  6;
-  volatile uint8_t sr2;		//=  7;
-  volatile uint8_t egr;		//=  8;
-  volatile uint8_t ccmr1;	//=  9;
-  volatile uint8_t ccmr2;	//= 0x0a;
-  volatile uint8_t ccer1;	//= 0x0b;
-  volatile uint8_t cntrh;	//= 0x0c;
-  volatile uint8_t cntrl;	//= 0x0d;
-  volatile uint8_t pscrl;	//= 0x0e;
-  volatile uint8_t arrh;	//= 0x0f;
-  volatile uint8_t arrl;	//= 0x10;
-  volatile uint8_t ccr1h;	//= 0x11;
-  volatile uint8_t ccr1l;	//= 0x12;
-  volatile uint8_t ccr2h;	//= 0x13;
-  volatile uint8_t ccr2l;	//= 0x14;
-  volatile uint8_t bkr;		//= 0x15;
-  volatile uint8_t oisr;	//= 0x16;
-};
-#define TIM2_UP_IRQ 19
-#define TIM2_CC_IRQ 20
-#define TIM2 ((struct TIM2_t *)0x5250)
-#elif (DEVICE & DEV_STM8L101)
-struct TIM2_t {
-  volatile uint8_t cr1;		//=  0;
-  volatile uint8_t cr2;		//=  1;
-  volatile uint8_t smcr;	//=  2;
-  volatile uint8_t etr;		//=  3;
-  volatile uint8_t ier;		//=  4;
-  volatile uint8_t sr1;		//=  5;
-  volatile uint8_t sr2;		//=  6;
-  volatile uint8_t egr;		//=  7;
-  volatile uint8_t ccmr1;	//=  8;
-  volatile uint8_t ccmr2;	//= 0x09;
-  volatile uint8_t ccer1;	//= 0x0a;
-  volatile uint8_t cntrh;	//= 0x0b;
-  volatile uint8_t cntrl;	//= 0x0c;
-  volatile uint8_t pscrl;	//= 0x0d;
-  volatile uint8_t arrh;	//= 0x0e;
-  volatile uint8_t arrl;	//= 0x0f;
-  volatile uint8_t ccr1h;	//= 0x10;
-  volatile uint8_t ccr1l;	//= 0x11;
-  volatile uint8_t ccr2h;	//= 0x12;
-  volatile uint8_t ccr2l;	//= 0x13;
-  volatile uint8_t bkr;		//= 0x14;
-  volatile uint8_t oisr;	//= 0x15;
-};
-#define TIM2_UP_IRQ 19
-#define TIM2_CC_IRQ 20
-#define TIM2 ((struct TIM2_t *)0x5250)
-#endif
-
-/* USART
- */
-
-#define USART_CR2_TEN (1 << 3)
-#define USART_CR2_REN (1 << 2)
-#define USART_CR2_RIEN (1 << 5)
-#define USART_CR3_STOP2 (1 << 5)
-#define USART_CR3_STOP1 (1 << 4)
-#define USART_SR_TXE (1 << 7)
-#define USART_SR_RXNE (1 << 5)
-
-/* USART1
- */
-
-struct USART1_saf_t {
-  volatile uint8_t sr;
-  volatile uint8_t dr;
-  volatile uint8_t brr1;
-  volatile uint8_t brr2;
-  volatile uint8_t cr1;
-  volatile uint8_t cr2;
-  volatile uint8_t cr3;
-  volatile uint8_t cr4;
-  volatile uint8_t cr5;
-  volatile uint8_t gtr;
-  volatile uint8_t pscr;
-};
-
-struct USART1_all_t {
-  volatile uint8_t sr;
-  volatile uint8_t dr;
-  volatile uint8_t brr1;
-  volatile uint8_t brr2;
-  volatile uint8_t cr1;
-  volatile uint8_t cr2;
-  volatile uint8_t cr3;
-  volatile uint8_t cr4;
-  volatile uint8_t cr5;
-  volatile uint8_t gtr;
-  volatile uint8_t pscr;
-};
-
-struct USART1_l101_t {
-  volatile uint8_t sr;
-  volatile uint8_t dr;
-  volatile uint8_t brr1;
-  volatile uint8_t brr2;
-  volatile uint8_t cr1;
-  volatile uint8_t cr2;
-  volatile uint8_t cr3;
-  volatile uint8_t cr4;
-};
-
-#if (DEVICE & DEV_STM8S003) || \
-  (DEVICE & DEV_STM8S007) || \
-  (DEVICE & DEV_STM8S103) || \
-  (DEVICE & DEV_STM8S207) || \
-  (DEVICE & DEV_STM8S208) || \
-  (DEVICE & DEV_STM8S903) || \
-  (DEVICE & DEV_STM8AF52)
-#define USART1_t USART1_saf_t
-#define USART1 ((struct USART1_t *)0x5230)
-#endif
-
-#if (DEVICE & DEV_STM8ALL)
-#define USART1_t USART1_all_t
-#define USART1 ((struct USART1_t *)0x5230)
-#endif
-
-#if (DEVICE & DEV_STM8L101)
-#define USART1_t USART1_l101_t
-#define USART1 ((struct USART1_t *)0x5230)
-#endif
-
-/* USART2
- */
-
-struct USART2_saf_t {
-  volatile uint8_t sr;
-  volatile uint8_t dr;
-  volatile uint8_t brr1;
-  volatile uint8_t brr2;
-  volatile uint8_t cr1;
-  volatile uint8_t cr2;
-  volatile uint8_t cr3;
-  volatile uint8_t cr4;
-  volatile uint8_t cr5;
-  volatile uint8_t cr6;
-  volatile uint8_t gtr;
-  volatile uint8_t pscr;
-};
-
-struct USART2_all_t {
-  volatile uint8_t sr;
-  volatile uint8_t dr;
-  volatile uint8_t brr1;
-  volatile uint8_t brr2;
-  volatile uint8_t cr1;
-  volatile uint8_t cr2;
-  volatile uint8_t cr3;
-  volatile uint8_t cr4;
-  volatile uint8_t cr5;
-  volatile uint8_t gtr;
-  volatile uint8_t pscr;
-};
-
-#if (DEVICE & DEV_STM8S005) || \
-  (DEVICE & DEV_STM8S105) || \
-  (DEVICE & DEV_STM8AF62_46)
-#define USART2_t USART2_saf_t
-#define USART2 ((struct USART2_t *)0x5240)
-#endif
-
-#if (DEVICE & DEV_STM8AL3xE) || \
-  (DEVICE & DEV_STM8AL3x8) || \
-  (DEVICE & DEV_STM8L052R) || \
-  (DEVICE & DEV_STM8L15x8) || \
-  (DEVICE & DEV_STM8L162)
-#define USART2_t USART2_all_t
-#define USART2 ((struct USART2_t *)0x53E0)
-#endif
-
-/* USART3
- */
-
-struct USART3_saf_t {
-  volatile uint8_t sr;
-  volatile uint8_t dr;
-  volatile uint8_t brr1;
-  volatile uint8_t brr2;
-  volatile uint8_t cr1;
-  volatile uint8_t cr2;
-  volatile uint8_t cr3;
-  volatile uint8_t cr4;
-  volatile uint8_t _dummy;
-  volatile uint8_t cr6;
-  volatile uint8_t gtr;
-  volatile uint8_t pscr;
-};
-
-struct USART3_all_t {
-  volatile uint8_t sr;
-  volatile uint8_t dr;
-  volatile uint8_t brr1;
-  volatile uint8_t brr2;
-  volatile uint8_t cr1;
-  volatile uint8_t cr2;
-  volatile uint8_t cr3;
-  volatile uint8_t cr4;
-  volatile uint8_t cr5;
-  volatile uint8_t gtr;
-  volatile uint8_t pscr;
-};
-
-#if (DEVICE & DEV_STM8S007) || \
-  (DEVICE & DEV_STM8S207) || \
-  (DEVICE & DEV_STM8S208) || \
-  (DEVICE & DEV_STM8AF52)
-#define USART3_t USART3_saf_t
-#define USART3 ((struct USART3_t *)0x5240)
-#endif
-
-#if (DEVICE & DEV_STM8AL3xE) || \
-  (DEVICE & DEV_STM8AL3x8) || \
-  (DEVICE & DEV_STM8L052R) || \
-  (DEVICE & DEV_STM8L15x8) || \
-  (DEVICE & DEV_STM8L162)
-#define USART3_t USART3_all_t
-#define USART3 ((struct USART3_t *)0x53F0)
-#endif
-
-/* USART4
- */
-
-struct USART4_saf_t {
-  volatile uint8_t sr;
-  volatile uint8_t dr;
-  volatile uint8_t brr1;
-  volatile uint8_t brr2;
-  volatile uint8_t cr1;
-  volatile uint8_t cr2;
-  volatile uint8_t cr3;
-  volatile uint8_t cr4;
-  volatile uint8_t cr5;
-  volatile uint8_t cr6;
-  volatile uint8_t gtr;
-  volatile uint8_t pscr;
-};
-
-#if (DEVICE & DEV_STM8AF62_12)
-#define USART4_t USART4_saf_t
-#define USART4 ((struct USART4_t *)0x5230)
-#endif
-
-/* USART interrupt numbers */
-
-#if (DEVICE & DEV_STM8SAF)
-#if defined USART1
-#define USART1_TX_IRQ 17
-#define USART1_RX_IRQ 18
-#endif
-#endif
-#if (DEVICE & DEV_STM8ALL) || \
-  (DEVICE & DEV_STM8_L101)
-#if defined USART1
-#define USART1_TX_IRQ 27
-#define USART1_RX_IRQ 28
-#endif
-#endif
-
-#if (DEVICE & DEV_STM8SAF)
-#if defined USART2
-#define USART2_TX_IRQ 20
-#define USART2_RX_IRQ 21
-#endif
-#endif
-#if (DEVICE & DEV_STM8ALL)
-#if defined USART2
-#define USART2_TX_IRQ 19
-#define USART2_RX_IRQ 20
-#endif
-#endif
-
-#if (DEVICE & DEV_STM8SAF)
-#if defined USART3
-#define USART3_TX_IRQ 20
-#define USART3_RX_IRQ 21
-#endif
-#endif
-#if (DEVICE & DEV_STM8ALL)
-#if defined USART3
-#define USART3_TX_IRQ 21
-#define USART3_RX_IRQ 22
-#endif
-#endif
-
-#if defined USART4
-#define USART3_TX_IRQ 17
-#define USART3_RX_IRQ 18
-#endif
-
-/* Select first USART as default */
-
-#ifndef USART
-#if (DEVICE & DEV_STM8S003) || \
-  (DEVICE & DEV_STM8S007) || \
-  (DEVICE & DEV_STM8S103) || \
-  (DEVICE & DEV_STM8S207) || \
-  (DEVICE & DEV_STM8S208) || \
-  (DEVICE & DEV_STM8S903) || \
-  (DEVICE & DEV_STM8AF52) || \
-  (DEVICE & DEV_STM8ALL) || \
-  (DEVICE & DEV_STM8L101)
-#define USART USART1
-#define USART_TX_IRQ USART1_TX_IRQ
-#define USART_RX_IRQ USART1_RX_IRQ
-#endif
-#if (DEVICE & DEV_STM8S005) || \
-  (DEVICE & DEV_STM8S105) || \
-  (DEVICE & DEV_STM8AF62_46)
-#define USART USART2
-#define USART_TX_IRQ USART2_TX_IRQ
-#define USART_RX_IRQ USART2_RX_IRQ
-#endif
-#if (DEVICE & DEV_STM8AF62_12)
-#define USART USART4
-#define USART_TX_IRQ USART4_TX_IRQ
-#define USART_RX_IRQ USART4_RX_IRQ
-#endif
-#endif
-#if ((DEVICE & DEV_STM8S003) || \
-     (DEVICE & DEV_STM8S005) || \
-     (DEVICE & DEV_STM8S103) || \
-     (DEVICE & DEV_STM8S105) || \
-     (DEVICE & DEV_STM8S903) || \
-     (DEVICE & DEV_STM8AF62_12) || \
-     (DEVICE & DEV_STM8AF62_46))
-#define USART_TX_GPIO GPIOD
-#define USART_RX_GPIO GPIOD
-#define USART_TX_PIN  5
-#define USART_RX_PIN  6
-#endif
-#if ((DEVICE & DEV_STM8S007) ||\
-     (DEVICE & DEV_STM8S207) ||\
-     (DEVICE & DEV_STM8S208) ||\
-     (DEVICE & DEV_STM8AF52))
-#define USART_TX_GPIO GPIOA
-#define USART_RX_GPIO GPIOA
-#define USART_TX_PIN  5
-#define USART_RX_PIN  4
-#endif
-#if (DEVICE & DEV_STM8AL) ||\
-  (DEVICE & DEV_STM8L052C) ||\
-  (DEVICE & DEV_STM8L052R) ||\
-  (DEVICE & DEV_STM8L151x23) ||\
-  (DEVICE & DEV_STM8L15x46) ||\
-  (DEVICE & DEV_STM8L15x8) ||\
-  (DEVICE & DEV_STM8L162) ||\
-  (DEVICE & DEV_STM8L101)
-#define USART_TX_GPIO GPIOC
-#define USART_RX_GPIO GPIOC
-#define USART_TX_PIN  3
-#define USART_RX_PIN  2
-#endif
-#if (DEVICE & DEV_STM8L051)
-/* non-default AF only because C2 and C3 are not available */
-#define USART_TX_GPIO
-#define USART_RX_GPIO
-#define USART_TX_PIN 
-#define USART_RX_PIN 
-#endif
-
-/* CLK
- */
-
-#if (DEVICE & DEV_STM8SAF)
-struct CLK_t {
-  uint8_t ickr;
-  uint8_t eckr;
-  uint8_t _dummy1;
-  uint8_t cmsr;
-  uint8_t swr;
-  uint8_t swcr;
-  uint8_t ckdivr;
-  uint8_t pckenr1;
-  uint8_t cssr;
-  uint8_t ccor;
-  uint8_t pckenr2;
-  uint8_t _dummy2;
-  uint8_t hsitrimr;
-  uint8_t swimccr;
-};
-#endif
-#if (DEVICE & DEV_STM8ALL)
-struct CLK_t {
-  uint8_t ckdivr;
-  uint8_t crtcr;
-  uint8_t ickcr;
-  uint8_t pckenr1;
-  uint8_t pckenr2;
-  uint8_t ccor;
-  uint8_t eckcr;
-  uint8_t scsr;
-  uint8_t swr;
-  uint8_t swcr;
-  uint8_t cssr;
-  uint8_t cbeepr;
-  uint8_t hsicalr;
-  uint8_t hsitrimr;
-  uint8_t hsiunclkr;
-  uint8_t regcsr;
-  uint8_t pckenr3;
-};
-#endif
-#if (DEVICE & DEV_STM8L101)
-struct CLK_t {
-  uint8_t ckdivr;
-  uint8_t _dummy1;
-  uint8_t _dummy2;
-  uint8_t pckenr;
-  uint8_t _dummy3;
-  uint8_t ccor;
-};
-#endif
-
-#define CLK ((struct CLK_t *)0x50C0)
-
-/* UID
- */
-
-#if (DEVICE & DEV_STM8S103) || \
-  (DEVICE & DEV_STM8S903) || \
-  (DEVICE & DEV_STM8AF62_12)
-#define UID ((uint8_t*)0x4865)
-#endif
-#if (DEVICE & DEV_STM8AL) || \
-  (DEVICE & DEV_STM8L151x23) || \
-  (DEVICE & DEV_STM8L15x46) ||	\
-  (DEVICE & DEV_STM8L15x8) || \
-  (DEVICE & DEV_STM8L162)
-#define UID ((uint8_t*)0x4926)
-#endif
-#if (DEVICE & DEV_STM8L101)
-#define UID ((uint8_t*)0x4925)
-#endif
-
-/* FLASH
- */
-
-#if (DEVICE & DEV_STM8SAF)
-struct FLASH_t {
-  volatile uint8_t cr1;
-  volatile uint8_t cr2;
-  volatile uint8_t ncr2;
-  volatile uint8_t fpr;
-  volatile uint8_t nfpr;
-  volatile uint8_t iapsr;
-  volatile uint16_t dummy1;
-  volatile uint8_t pukr;
-  volatile uint8_t dummy2;
-  volatile uint8_t dukr;
-};
-#define FLASH ((volatile struct FLASH_t * volatile)0x505a)
-#define FLASH_IRQ 24
-#elif (DEVICE & DEV_STM8ALL) ||			\
-  (DEVICE & DEV_STM8L101)
-struct FLASH_t {
-  volatile uint8_t cr1;
-  volatile uint8_t cr2;
-  volatile uint8_t pukr;
-  volatile uint8_t dukr;
-  volatile uint8_t iapsr;
-};
-#define FLASH ((struct FLASH_t *)0x5050)
-#define FLASH_IRQ 1
-#endif
-
-#define EI __asm__("rim")
-#define DI __asm__("sim")
-
-#endif
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/symdis/baseline/stdout sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/symdis/baseline/stdout
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/symdis/baseline/stdout	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/symdis/baseline/stdout	2022-02-08 21:21:05.000000000 +0000
@@ -0,0 +1,367 @@
+uCsim, Copyright (C)  Daniel Drotos.
+uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+This is free software, and you are welcome to redistribute it
+under certain conditions; type `show c' for details.
+var __interrupt_vect rom[0x8000]
+var _isr_unused rom[0x807c]
+var tx_bit_1 rom[0x8115]
+var tx_stop rom[0x811b]
+var tx_done rom[0x8121]
+var tx_idle rom[0x8145]
+var rx rom[0x8153]
+var rx_have_a rom[0x8156]
+var rx_active rom[0x8158]
+var rx_sample_1 rom[0x8165]
+var rx_next_bit rom[0x8169]
+var rx_done rom[0x817b]
+var rx_data rom[0x817c]
+var rx_idle rom[0x8189]
+var rx_stop rom[0x818e]
+var vuart_tx_put rom[0x81ba]
+var _boot rom[0x81db]
+var forever rom[0x82a1]
+var uart1_tx_buf rom[0x1]
+var vuart_tx_state rom[0x21]
+var vuart_tx rom[0x22]
+var vuart_rx_state rom[0x23]
+var vuart_rx rom[0x24]
+var vuart_rx_bit rom[0x25]
+var vuart_tx_buf rom[0x26]
+var uart1_tx_w rom[0x36]
+var uart1_tx_r rom[0x38]
+var vuart_tx_w rom[0x3a]
+var vuart_tx_r rom[0x3c]
+var IRQ_EXTI3 rom[0x80d3]
+var IRQ_TIM2 rom[0x80f5]
+var IRQ_UART1_TX rom[0x80a5]
+var IRQ_UART1_RX rom[0x807d]
+# Set some core vars
+var CLK_PCKENR1       rom[0x50c7][7:0]
+var CLK_PCKENR1_UART1 rom[0x50c7].3
+var CLK_PCKENR1_TIM2  rom[0x50c7].5
+var UART1_SR          rom[0x5230]
+var UART1_SR_TXE      rom[0x5230].7
+var UART1_SR_TC       rom[0x5230].6
+var UART1_SR_RXNE     rom[0x5230].5
+
+dump rom[0x00] 0x3d
+0x00000                       08                      .
+0x00001 uart1_tx_buf:         70 d4 b2 8a 29 54 48 9a p...)TH.
+0x00009                       0a bc d5 0e 18 a8 44 ac ......D.
+0x00011                       5b f3 8e 4c d7 2d 9b 09 [..L.-..
+0x00019                       42 e5 06 c4 33 af cd a3 B...3...
+0x00021 vuart_tx_state:       84                      .
+0x00022 vuart_tx:             7f                      .
+0x00023 vuart_rx_state:       2d                      -
+0x00024 vuart_rx:             ad                      .
+0x00025 vuart_rx_bit:         d4                      .
+0x00026 vuart_tx_buf:         76 47 de 32 1c ec 4a c4 vG.2..J.
+0x0002e                       30 f6 20 23 85 6c fb b2 0. #.l..
+0x00036 uart1_tx_w:           07 04                   ..
+0x00038 uart1_tx_r:           f4 ec                   ..
+0x0003a vuart_tx_w:           0b b9                   ..
+0x0003c vuart_tx_r:           20 ba                    .
+dc 0x8000 0x082a4 
+
+0x08000    <__interrupt_vect>:
+0x08000    82 00 81 db    int    #0x0081db <_boot>[0K
+0x08004    82 00 80 7c    int    #0x00807c <_isr_unused>[0K
+0x08008    82 00 80 7c    int    #0x00807c <_isr_unused>[0K
+0x0800c    82 00 80 7c    int    #0x00807c <_isr_unused>[0K
+0x08010    82 00 80 7c    int    #0x00807c <_isr_unused>[0K
+0x08014    82 00 80 7c    int    #0x00807c <_isr_unused>[0K
+0x08018    82 00 80 7c    int    #0x00807c <_isr_unused>[0K
+0x0801c    82 00 80 7c    int    #0x00807c <_isr_unused>[0K
+0x08020    82 00 80 d3    int    #0x0080d3 [0K
+0x08024    82 00 80 7c    int    #0x00807c <_isr_unused>[0K
+0x08028    82 00 80 7c    int    #0x00807c <_isr_unused>[0K
+0x0802c    82 00 80 7c    int    #0x00807c <_isr_unused>[0K
+0x08030    82 00 80 7c    int    #0x00807c <_isr_unused>[0K
+0x08034    82 00 80 7c    int    #0x00807c <_isr_unused>[0K
+0x08038    82 00 80 7c    int    #0x00807c <_isr_unused>[0K
+0x0803c    82 00 80 f5    int    #0x0080f5 [0K
+0x08040    82 00 80 7c    int    #0x00807c <_isr_unused>[0K
+0x08044    82 00 80 7c    int    #0x00807c <_isr_unused>[0K
+0x08048    82 00 80 7c    int    #0x00807c <_isr_unused>[0K
+0x0804c    82 00 80 a5    int    #0x0080a5 [0K
+0x08050    82 00 80 7d    int    #0x00807d [0K
+0x08054    82 00 80 7c    int    #0x00807c <_isr_unused>[0K
+0x08058    82 00 80 7c    int    #0x00807c <_isr_unused>[0K
+0x0805c    82 00 80 7c    int    #0x00807c <_isr_unused>[0K
+0x08060    82 00 80 7c    int    #0x00807c <_isr_unused>[0K
+0x08064    82 00 80 7c    int    #0x00807c <_isr_unused>[0K
+0x08068    82 00 80 7c    int    #0x00807c <_isr_unused>[0K
+0x0806c    82 00 80 7c    int    #0x00807c <_isr_unused>[0K
+0x08070    82 00 80 7c    int    #0x00807c <_isr_unused>[0K
+0x08074    82 00 80 7c    int    #0x00807c <_isr_unused>[0K
+0x08078    82 00 80 7c    int    #0x00807c <_isr_unused>[0K
+
+0x0807c    <_isr_unused>:
+0x0807c    80             iret[0K
+
+0x0807d    :
+0x0807d    4b 00          push   #0x00[0K
+0x0807f    86             pop    CC[0K
+0x08080    9b             sim[0K
+0x08081    c6 52 31       ld     A,0x5231[0K
+0x08084    ce 00 3a       ldw    X,0x003a [0K
+0x08087    d7 00 26       ld     (0x0026 ,X),A[0K
+0x0808a    5a             decw   X[0K
+0x0808b    2a 03          jrpl   0x8090 <.label$32>[0K
+0x0808d    ae 00 0f       ldw    X,#0x000f[0K
+
+0x08090    <.label$32>:
+0x08090    cf 00 3a       ldw    0x003a ,X[0K
+0x08093    72 00 53 00 0c btjt   0x5300,#0,0x80a4 <.bit0_isset$33>[0K
+0x08098    72 1a 50 c7    bset   0x50c7 ,#5 [0K
+0x0809c    72 10 53 00    bset   0x5300,#0[0K
+0x080a0    72 10 53 06    bset   0x5306,#0[0K
+
+0x080a4    <.bit0_isset$33>:
+0x080a4    80             iret[0K
+
+0x080a5    :
+0x080a5    4b 08          push   #0x08[0K
+0x080a7    86             pop    CC[0K
+0x080a8    9b             sim[0K
+0x080a9    72 0c 52 30 20 btjt   0x5230 ,#6 ,0x80ce <.bit6_isset$29>[0K
+0x080ae    ce 00 38       ldw    X,0x0038 [0K
+0x080b1    c3 00 36       cpw    X,0x0036 [0K
+0x080b4    27 13          jreq   0x80c9 <.label$30>[0K
+0x080b6    ce 00 38       ldw    X,0x0038 [0K
+0x080b9    d6 00 01       ld     A,(0x0001 ,X)[0K
+0x080bc    5a             decw   X[0K
+0x080bd    2a 03          jrpl   0x80c2 <.label$31>[0K
+0x080bf    ae 00 1f       ldw    X,#0x001f[0K
+
+0x080c2    <.label$31>:
+0x080c2    cf 00 38       ldw    0x0038 ,X[0K
+0x080c5    c7 52 31       ld     0x5231,A[0K
+0x080c8    80             iret[0K
+
+0x080c9    <.label$30>:
+0x080c9    72 1f 52 35    bres   0x5235,#7[0K
+0x080cd    80             iret[0K
+
+0x080ce    <.bit6_isset$29>:
+0x080ce    72 1d 52 30    bres   0x5230 ,#6 [0K
+0x080d2    80             iret[0K
+
+0x080d3    :
+0x080d3    4b 28          push   #0x28[0K
+0x080d5    86             pop    CC[0K
+0x080d6    9b             sim[0K
+0x080d7    72 17 50 13    bres   0x5013 ,#3[0K
+0x080db    35 0a 00 23    mov    0x0023 ,#0x0a[0K
+0x080df    35 ff 00 25    mov    0x0025 ,#0xff[0K
+0x080e3    72 00 53 00 0c btjt   0x5300,#0,0x80f4 <.bit0_isset$34>[0K
+0x080e8    72 1a 50 c7    bset   0x50c7 ,#5 [0K
+0x080ec    72 10 53 00    bset   0x5300,#0[0K
+0x080f0    72 10 53 06    bset   0x5306,#0[0K
+
+0x080f4    <.bit0_isset$34>:
+0x080f4    80             iret[0K
+
+0x080f5    :
+0x080f5    4b 28          push   #0x28[0K
+0x080f7    86             pop    CC[0K
+0x080f8    9b             sim[0K
+0x080f9    72 11 53 04    bres   0x5304,#0[0K
+0x080fd    c6 00 21       ld     A,0x0021 [0K
+0x08100    2b 1f          jrmi   0x8121 [0K
+0x08102    72 5a 00 21    dec    0x0021 [0K
+0x08106    2b 13          jrmi   0x811b [0K
+0x08108    72 56 00 22    rrc    0x0022 [0K
+0x0810c    25 07          jrult  0x8115 [0K
+0x0810e    9d             nop[0K
+0x0810f    72 15 50 0f    bres   0x500f ,#2[0K
+0x08113    20 3e          jra    0x8153 [0K
+
+0x08115    :
+0x08115    72 14 50 0f    bset   0x500f ,#2[0K
+0x08119    20 38          jra    0x8153 [0K
+
+0x0811b    :
+0x0811b    72 14 50 0f    bset   0x500f ,#2[0K
+0x0811f    20 32          jra    0x8153 [0K
+
+0x08121    :
+0x08121    ce 00 3c       ldw    X,0x003c [0K
+0x08124    c3 00 3a       cpw    X,0x003a [0K
+0x08127    27 1c          jreq   0x8145 [0K
+0x08129    72 15 50 0f    bres   0x500f ,#2[0K
+0x0812d    ce 00 3c       ldw    X,0x003c [0K
+0x08130    d6 00 26       ld     A,(0x0026 ,X)[0K
+0x08133    5a             decw   X[0K
+0x08134    2a 03          jrpl   0x8139 <.label$46>[0K
+0x08136    ae 00 0f       ldw    X,#0x000f[0K
+
+0x08139    <.label$46>:
+0x08139    cf 00 3c       ldw    0x003c ,X[0K
+0x0813c    c7 00 22       ld     0x0022 ,A[0K
+0x0813f    35 08 00 21    mov    0x0021 ,#0x08[0K
+0x08143    20 0e          jra    0x8153 [0K
+
+0x08145    :
+0x08145    c6 00 23       ld     A,0x0023 [0K
+0x08148    2a 0c          jrpl   0x8156 [0K
+0x0814a    72 11 53 00    bres   0x5300,#0[0K
+0x0814e    72 1b 50 c7    bres   0x50c7 ,#5 [0K
+0x08152    80             iret[0K
+
+0x08153    :
+0x08153    c6 00 23       ld     A,0x0023 [0K
+
+0x08156    :
+0x08156    2b 23          jrmi   0x817b [0K
+
+0x08158    :
+0x08158    72 07 50 10 08 btjf   0x5010 ,#3,0x8165 [0K
+0x0815d    72 5a 00 25    dec    0x0025 [0K
+0x08161    72 5a 00 25    dec    0x0025 [0K
+
+0x08165    :
+0x08165    72 5c 00 25    inc    0x0025 [0K
+
+0x08169    :
+0x08169    4a             dec    A[0K
+0x0816a    c7 00 23       ld     0x0023 ,A[0K
+0x0816d    2b 1a          jrmi   0x8189 [0K
+0x0816f    27 1d          jreq   0x818e [0K
+0x08171    a1 0a          cp     A,#0x0a[0K
+0x08173    26 07          jrne   0x817c [0K
+0x08175    72 59 00 25    rlc    0x0025 [0K
+0x08179    25 0e          jrult  0x8189 [0K
+
+0x0817b    :
+0x0817b    80             iret[0K
+
+0x0817c    :
+0x0817c    72 59 00 25    rlc    0x0025 [0K
+0x08180    72 56 00 24    rrc    0x0024 [0K
+0x08184    72 5f 00 25    clr    0x0025 [0K
+0x08188    80             iret[0K
+
+0x08189    :
+0x08189    72 16 50 13    bset   0x5013 ,#3[0K
+0x0818d    80             iret[0K
+
+0x0818e    :
+0x0818e    c6 00 24       ld     A,0x0024 [0K
+0x08191    8a             push   CC[0K
+0x08192    9b             sim[0K
+0x08193    ce 00 38       ldw    X,0x0038 [0K
+0x08196    c3 00 36       cpw    X,0x0036 [0K
+0x08199    26 0e          jrne   0x81a9 <.label$42>[0K
+0x0819b    72 0f 52 30 09 btjf   0x5230 ,#7 ,0x81a9 <.label$42>[0K
+0x081a0    c7 52 31       ld     0x5231,A[0K
+0x081a3    72 1e 52 35    bset   0x5235,#7[0K
+0x081a7    20 0f          jra    0x81b8 <.label$44>[0K
+
+0x081a9    <.label$42>:
+0x081a9    ce 00 36       ldw    X,0x0036 [0K
+0x081ac    d7 00 01       ld     (0x0001 ,X),A[0K
+0x081af    5a             decw   X[0K
+0x081b0    2a 03          jrpl   0x81b5 <.label$43>[0K
+0x081b2    ae 00 1f       ldw    X,#0x001f[0K
+
+0x081b5    <.label$43>:
+0x081b5    cf 00 36       ldw    0x0036 ,X[0K
+
+0x081b8    <.label$44>:
+0x081b8    86             pop    CC[0K
+0x081b9    80             iret[0K
+
+0x081ba    :
+0x081ba    ce 00 3a       ldw    X,0x003a [0K
+0x081bd    d7 00 26       ld     (0x0026 ,X),A[0K
+0x081c0    5a             decw   X[0K
+0x081c1    2a 03          jrpl   0x81c6 <.label$53>[0K
+0x081c3    ae 00 0f       ldw    X,#0x000f[0K
+
+0x081c6    <.label$53>:
+0x081c6    cf 00 3a       ldw    0x003a ,X[0K
+0x081c9    72 00 53 00 0c btjt   0x5300,#0,0x81da <.bit0_isset$54>[0K
+0x081ce    72 1a 50 c7    bset   0x50c7 ,#5 [0K
+0x081d2    72 10 53 00    bset   0x5300,#0[0K
+0x081d6    72 10 53 06    bset   0x5306,#0[0K
+
+0x081da    <.bit0_isset$54>:
+0x081da    81             ret[0K
+
+0x081db    <_boot>:
+0x081db    35 00 50 c6    mov    0x50c6 ,#0x00[0K
+0x081df    35 00 50 c7    mov    0x50c7 ,#0x00[0K
+0x081e3    35 00 50 ca    mov    0x50ca ,#0x00[0K
+0x081e7    ae 00 08       ldw    X,#0x0008[0K
+0x081ea    27 07          jreq   0x81f3 <.label$50>[0K
+
+0x081ec    <.loop$57>:
+0x081ec    72 4f 00 35    clr    (0x0035,X)[0K
+0x081f0    5a             decw   X[0K
+0x081f1    26 f9          jrne   0x81ec <.loop$57>[0K
+
+0x081f3    <.label$50>:
+0x081f3    ae 00 00       ldw    X,#0x0000[0K
+0x081f6    27 09          jreq   0x8201 <.label$51>[0K
+
+0x081f8    <.loop$56>:
+0x081f8    d6 81 da       ld     A,(0x81da <.bit0_isset$54>,X)[0K
+0x081fb    d7 00 3d       ld     (0x003d,X),A[0K
+0x081fe    5a             decw   X[0K
+0x081ff    26 f7          jrne   0x81f8 <.loop$56>[0K
+
+0x08201    <.label$51>:
+0x08201    c6 7f 74       ld     A,0x7f74 [0K
+0x08204    a4 f3          and    A,#0xf3[0K
+0x08206    aa 04          or     A,#0x04[0K
+0x08208    c7 7f 74       ld     0x7f74 ,A[0K
+0x0820b    c6 7f 74       ld     A,0x7f74 [0K
+0x0820e    a4 cf          and    A,#0xcf[0K
+0x08210    aa 00          or     A,#0x00[0K
+0x08212    c7 7f 74       ld     0x7f74 ,A[0K
+0x08215    c6 7f 73       ld     A,0x7f73 [0K
+0x08218    a4 f3          and    A,#0xf3[0K
+0x0821a    aa 0c          or     A,#0x0c[0K
+0x0821c    c7 7f 73       ld     0x7f73 ,A[0K
+0x0821f    35 20 52 34    mov    0x5234,#0x20[0K
+0x08223    35 2c 52 35    mov    0x5235,#0x2c[0K
+0x08227    35 00 52 36    mov    0x5236,#0x00[0K
+0x0822b    35 0b 52 33    mov    0x5233,#0x0b[0K
+0x0822f    35 08 52 32    mov    0x5232,#0x08[0K
+0x08233    72 16 50 c7    bset   0x50c7 ,#3 [0K
+0x08237    72 1b 52 34    bres   0x5234,#5[0K
+0x0823b    35 0f 00 3c    mov    0x003c ,#0x0f[0K
+0x0823f    35 0f 00 3a    mov    0x003a ,#0x0f[0K
+0x08243    35 ff 00 21    mov    0x0021 ,#0xff[0K
+0x08247    35 ff 00 23    mov    0x0023 ,#0xff[0K
+0x0824b    72 14 50 11    bset   0x5011 ,#2[0K
+0x0824f    72 14 50 12    bset   0x5012 ,#2[0K
+0x08253    72 15 50 13    bres   0x5013 ,#2[0K
+0x08257    72 14 50 0f    bset   0x500f ,#2[0K
+0x0825b    72 17 50 11    bres   0x5011 ,#3[0K
+0x0825f    72 17 50 12    bres   0x5012 ,#3[0K
+0x08263    72 16 50 13    bset   0x5013 ,#3[0K
+0x08267    c6 50 a1       ld     A,0x50a1 [0K
+0x0826a    a4 fc          and    A,#0xfc[0K
+0x0826c    aa 02          or     A,#0x02[0K
+0x0826e    c7 50 a1       ld     0x50a1 ,A[0K
+0x08271    35 00 53 0e    mov    0x530e,#0x00[0K
+0x08275    35 00 53 0f    mov    0x530f,#0x00[0K
+0x08279    35 8b 53 10    mov    0x5310,#0x8b[0K
+0x0827d    72 15 53 00    bres   0x5300,#2[0K
+0x08281    72 10 53 03    bset   0x5303,#0[0K
+0x08285    a6 48          ld     A,#0x48[0K
+0x08287    cd 81 ba       call   0x81ba [0K
+0x0828a    a6 69          ld     A,#0x69[0K
+0x0828c    cd 81 ba       call   0x81ba [0K
+0x0828f    a6 0d          ld     A,#0x0d[0K
+0x08291    cd 81 ba       call   0x81ba [0K
+0x08294    a6 0a          ld     A,#0x0a[0K
+0x08296    cd 81 ba       call   0x81ba [0K
+0x08299    72 12 7f 60    bset   0x7f60,#1[0K
+0x0829d    72 16 50 5a    bset   0x505a,#3[0K
+
+0x082a1    :
+0x082a1    8f             wfi[0K
+0x082a2    cc 82 a1       jp     0x82a1 [0K
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/symdis/Makefile sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/symdis/Makefile
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/symdis/Makefile	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/symdis/Makefile	2021-05-07 16:21:16.000000000 +0000
@@ -0,0 +1,15 @@
+OUTPUTS = stdout
+
+
+# Ignore changes in white space. The field widths for labels
+# depends on the length of the longest label. This will be
+# different for different simulators and should not be assumed
+# to be constant for any given simulator.
+DIFF_OPTS += -b
+
+
+stdout:	xconnect.ihx xconnect.vars test.cmd
+	@$(call run-sim, -t S003 '$(srcdir)/xconnect.ihx' -e 'exec "$(srcdir)/xconnect.vars"')
+
+
+include test-lib.mk
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/symdis/test.cmd sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/symdis/test.cmd
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/symdis/test.cmd	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/symdis/test.cmd	2021-05-07 16:21:16.000000000 +0000
@@ -0,0 +1,11 @@
+# Set some core vars
+var CLK_PCKENR1       rom[0x50c7][7:0]
+var CLK_PCKENR1_UART1 rom[0x50c7].3
+var CLK_PCKENR1_TIM2  rom[0x50c7].5
+var UART1_SR          rom[0x5230]
+var UART1_SR_TXE      rom[0x5230].7
+var UART1_SR_TC       rom[0x5230].6
+var UART1_SR_RXNE     rom[0x5230].5
+
+dump rom[0x00] 0x3d
+dc 0x8000 0x082a4 
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/symdis/xconnect.ihx sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/symdis/xconnect.ihx
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/symdis/xconnect.ihx	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/symdis/xconnect.ihx	2021-05-07 16:21:16.000000000 +0000
@@ -0,0 +1,32 @@
+:20800000820081DB8200807C8200807C8200807C8200807C8200807C8200807C8200807C10
+:208020008200807C8200807C8200807C8200807C8200807C8200807C8200807C8200807C50
+:208040008200807C8200807C8200807C8200807C8200807C8200807C8200807C8200807C30
+:1D8060008200807C8200807C8200807C8200807C8200807C8200807C8200807C8011
+:048050008200807DAD
+:20807D004B00869BC65231CE003AD700265A2A03AE000FCF003A720053000C721A50C772F6
+:08809D0010530072105306801D
+:04804C00820080A589
+:2080A5004B08869B720C523020CE0038C300362713CE0038D600015A2A03AE001FCF0038B6
+:0E80C500C7523180721F523580721D523080BA
+:04800000820081DB9E
+:2081DB00350050C6350050C7350050CAAE00082707724F00355A26F9AE00002709D681DA3C
+:2081FB00D7003D5A26F7C67F74A4F3AA04C77F74C67F74A4CFAA00C77F74C67F73A4F3AA98
+:20821B000CC77F7335205234352C523535005236350B523335085232721650C7721B5234C6
+:20823B00350F003C350F003A35FF002135FF00237214501172145012721550137214500FDB
+:20825B00721750117217501272165013C650A1A4FCAA02C750A13500530E3500530F358B9B
+:0A827B0053107215530072105303E4
+:04802000820080D387
+:2080D3004B28869B72175013350A002335FF0025720053000C721A50C77210530072105334
+:0280F300068005
+:04803C00820080F549
+:2080F5004B28869B72115304C600212B1F725A00212B137256002225079D7215500F203EAA
+:208115007214500F20387214500F2032CE003CC3003A271C7215500FCE003CD600265A2A1C
+:2081350003AE000FCF003CC7002235080021200EC600232A0C72115300721B50C780C6000B
+:20815500232B237207501008725A0025725A0025725C00254AC700232B1A271DA10A26074E
+:2081750072590025250E807259002572560024725F0025807216501380C600248A9BCE00AD
+:2081950038C30036260E720F523009C75231721E5235200FCE0036D700015A2A03AE001F99
+:0581B500CF00368680BA
+:20828500A648CD81BAA669CD81BAA60DCD81BAA60ACD81BA72127F607216505A8FCC82A146
+:2081BA00CE003AD700265A2A03AE000FCF003A720053000C721A50C772105300721053062F
+:0181DA008123
+:00000001FF
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/symdis/xconnect.vars sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/symdis/xconnect.vars
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/symdis/xconnect.vars	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/symdis/xconnect.vars	2021-05-07 16:21:16.000000000 +0000
@@ -0,0 +1,33 @@
+var __interrupt_vect rom[0x8000]
+var _isr_unused rom[0x807c]
+var tx_bit_1 rom[0x8115]
+var tx_stop rom[0x811b]
+var tx_done rom[0x8121]
+var tx_idle rom[0x8145]
+var rx rom[0x8153]
+var rx_have_a rom[0x8156]
+var rx_active rom[0x8158]
+var rx_sample_1 rom[0x8165]
+var rx_next_bit rom[0x8169]
+var rx_done rom[0x817b]
+var rx_data rom[0x817c]
+var rx_idle rom[0x8189]
+var rx_stop rom[0x818e]
+var vuart_tx_put rom[0x81ba]
+var _boot rom[0x81db]
+var forever rom[0x82a1]
+var uart1_tx_buf rom[0x1]
+var vuart_tx_state rom[0x21]
+var vuart_tx rom[0x22]
+var vuart_rx_state rom[0x23]
+var vuart_rx rom[0x24]
+var vuart_rx_bit rom[0x25]
+var vuart_tx_buf rom[0x26]
+var uart1_tx_w rom[0x36]
+var uart1_tx_r rom[0x38]
+var vuart_tx_w rom[0x3a]
+var vuart_tx_r rom[0x3c]
+var IRQ_EXTI3 rom[0x80d3]
+var IRQ_TIM2 rom[0x80f5]
+var IRQ_UART1_TX rom[0x80a5]
+var IRQ_UART1_RX rom[0x807d]
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/t1.c sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/t1.c
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/t1.c	2016-07-26 21:10:26.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/t1.c	1970-01-01 00:00:00.000000000 +0000
@@ -1,21 +0,0 @@
-volatile int x= 1;
-
-void isr_trap(void) __trap
-{
-  x= 2;
-}
-
-void trap()
-{
-  __asm
-    trap;
-  __endasm;
-}
-
-void
-main(void)
-{
-  trap();
-  for (;;)
-    ;
-}
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/t2.c sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/t2.c
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/t2.c	2016-07-26 21:10:26.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/t2.c	1970-01-01 00:00:00.000000000 +0000
@@ -1,17 +0,0 @@
-volatile unsigned char *sif= (unsigned char *)0x7fff;
-
-volatile char c;
-
-int f(int i)
-{
-  c= i;
-  return i;
-}
-
-void main(void)
-{
-  f('H'*256 + 'L');
-  *sif= 'p';
-  *sif= c;
-  *sif= 's';
-}
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/t3.c sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/t3.c
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/t3.c	2016-07-26 21:10:26.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/t3.c	1970-01-01 00:00:00.000000000 +0000
@@ -1,15 +0,0 @@
-#include 
-
-volatile unsigned char *sif= (unsigned char *)0x7fff;
-
-int putchar(int c)
-{
-  *sif= 'p';
-  *sif= c;
-  return c;
-}
-
-void main(void)
-{
-  printf("A");
-}
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/t4.c sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/t4.c
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/t4.c	2016-07-26 21:10:26.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/t4.c	1970-01-01 00:00:00.000000000 +0000
@@ -1,16 +0,0 @@
-#include 
-
-volatile unsigned char c;
-
-int putchar(int ch)
-{
-  c= ch;
-  return ch;
-}
-
-void main(void)
-{
-  printf("A");
-  putchar('B');
-  for (;;) ;
-}
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/test-conf.mk sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/test-conf.mk
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/test-conf.mk	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/test-conf.mk	2021-04-16 22:01:11.000000000 +0000
@@ -0,0 +1,4 @@
+CC = sdcc -mstm8
+AS = sdasstm8
+LD = sdldstm8
+LINKFLAGS = -b _CODE=0x8000 -b _DATA=0x0000
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/vcd-in/baseline/stdout sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/vcd-in/baseline/stdout
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/vcd-in/baseline/stdout	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/vcd-in/baseline/stdout	2022-02-08 21:21:05.000000000 +0000
@@ -0,0 +1,597 @@
+uCsim, Copyright (C)  Daniel Drotos.
+uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+This is free software, and you are welcome to redistribute it
+under certain conditions; type `show c' for details.
+# These are the test locations named in the input vcd.
+var loc1 rom[0x0000]
+var loc2 rom[0x0001]
+
+# Run the initialization code and stop when we reach the
+# first test loop.
+break 0x800c
+Breakpoint 1 at 0x00800c: 
+0x0800c    <.loop$0>:
+0x0800c F  cc 80 0c       jp     0x800c <.loop$0> (cond="")
+run
+Simulation started, PC=0x008000
+
+Stop at 0x00800c: (104) Breakpoint
+V-IHINZC  Flags= 0x2a  42 *  A= 0x00   0 .
+0-101010  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17ff [SP+1]= 00   0 .  Limit= 0x1500
+
+0x0800c    <.loop$0>:
+0x0800c F  cc 80 0c       jp     0x800c <.loop$0>[0K
+F 0x00800c
+Simulated 8 ticks [ELIDED]
+Host usage: [ELIDED]
+clear 0x800c
+
+# Start the vcd (we set the input file via the Makefile) and
+# have it stop execution each time an event occurs.
+set hw vcd start
+set hw vcd break
+Break on events enabled
+
+# The VCD data starts at time 0 which will, by default, align
+# with the current simulator time. We can adjust that by setting
+# starttime. This can be done before or after starting the vcd,
+# even part way through. Here we push the vcd 5 µs into the
+# future.
+set hw vcd starttime 5 us
+
+# Make sure what it is going to do is what we asked.
+conf
+Type of microcontroller: STM8 S,AF 208
+Controller has 24 hardware element(s).
+   on cpu[0]
+   on simif[0]
+   on vcd[0]
+   on dreg[0]
+   on dport[0]
+   on clk[0]
+   on uart[1]
+   on uart[3]
+   on itc[0]
+   on pa[0]
+   on pb[0]
+   on pc[0]
+   on pd[0]
+   on pe[0]
+   on pf[0]
+   on pg[0]
+   on ph[0]
+   on pi[0]
+   on rst[0]
+   on tim1[1]
+   on tim2[2]
+   on tim3[3]
+   on tim4[4]
+   on flash[0]
+info hw vcd
+vcd[0] value change dump
+  Modul:      ucsim_vcd_0
+  Started:    YES
+  Paused:     no
+  Mode:       input
+  Break:      enabled
+  Time scale: 1 ps
+  Start time: 0.000009000000000 s
+  Next event: 0.000011500000000 s
+  Pause time: 
+  Simul time: 0.000004000000000 s
+  Variables:
+    Address           Symbol
+    rom[0x00000].0    loc1.0
+    rom[0x00000].1    loc1.1
+    rom[0x00000].2    loc1.2
+    rom[0x00000].3    loc1.3
+    rom[0x00000].4    loc1.4
+    rom[0x00000].5    loc1.5
+    rom[0x00000].6    loc1.6
+    rom[0x00000].7    loc1.7
+    rom[0x00001]      loc2
+
+# Continue until an event stops us then dump the locations
+# that the vcd is driving according to the input file.
+# Repeat a sufficient number of times.
+cont
+Simulation started, PC=0x00800c
+
+Stop at 0x00800c: (104) Breakpoint
+V-IHINZC  Flags= 0x2a  42 *  A= 0x00   0 .
+0-101010  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17ff [SP+1]= 00   0 .  Limit= 0x1500
+
+0x0800c    <.loop$0>:
+0x0800c    cc 80 0c       jp     0x800c <.loop$0>[0K
+F 0x00800c
+Simulated 17 ticks [ELIDED]
+Host usage: [ELIDED]
+dump rom 0 1
+0x00000 loc1:                 01    .
+0x00001 loc2:                 00    .
+
+cont
+Simulation started, PC=0x00800c
+
+Stop at 0x00800c: (104) Breakpoint
+V-IHINZC  Flags= 0x2a  42 *  A= 0x00   0 .
+0-101010  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17ff [SP+1]= 00   0 .  Limit= 0x1500
+
+0x0800c    <.loop$0>:
+0x0800c    cc 80 0c       jp     0x800c <.loop$0>[0K
+F 0x00800c
+Simulated 2 ticks [ELIDED]
+Host usage: [ELIDED]
+dump rom 0 1
+0x00000 loc1:                 03    .
+0x00001 loc2:                 01    .
+
+cont
+Simulation started, PC=0x00800c
+
+Stop at 0x00800c: (104) Breakpoint
+V-IHINZC  Flags= 0x2a  42 *  A= 0x00   0 .
+0-101010  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17ff [SP+1]= 00   0 .  Limit= 0x1500
+
+0x0800c    <.loop$0>:
+0x0800c    cc 80 0c       jp     0x800c <.loop$0>[0K
+F 0x00800c
+Simulated 2 ticks [ELIDED]
+Host usage: [ELIDED]
+dump rom 0 1
+0x00000 loc1:                 02    .
+0x00001 loc2:                 02    .
+
+cont
+Simulation started, PC=0x00800c
+
+Stop at 0x00800c: (104) Breakpoint
+V-IHINZC  Flags= 0x2a  42 *  A= 0x00   0 .
+0-101010  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17ff [SP+1]= 00   0 .  Limit= 0x1500
+
+0x0800c    <.loop$0>:
+0x0800c    cc 80 0c       jp     0x800c <.loop$0>[0K
+F 0x00800c
+Simulated 2 ticks [ELIDED]
+Host usage: [ELIDED]
+dump rom 0 1
+0x00000 loc1:                 04    .
+0x00001 loc2:                 02    .
+
+cont
+Simulation started, PC=0x00800c
+
+Stop at 0x00800c: (104) Breakpoint
+V-IHINZC  Flags= 0x2a  42 *  A= 0x00   0 .
+0-101010  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17ff [SP+1]= 00   0 .  Limit= 0x1500
+
+0x0800c    <.loop$0>:
+0x0800c    cc 80 0c       jp     0x800c <.loop$0>[0K
+F 0x00800c
+Simulated 2 ticks [ELIDED]
+Host usage: [ELIDED]
+dump rom 0 1
+0x00000 loc1:                 0c    .
+0x00001 loc2:                 03    .
+
+cont
+Simulation started, PC=0x00800c
+
+Stop at 0x00800c: (104) Breakpoint
+V-IHINZC  Flags= 0x2a  42 *  A= 0x00   0 .
+0-101010  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17ff [SP+1]= 00   0 .  Limit= 0x1500
+
+0x0800c    <.loop$0>:
+0x0800c    cc 80 0c       jp     0x800c <.loop$0>[0K
+F 0x00800c
+Simulated 2 ticks [ELIDED]
+Host usage: [ELIDED]
+dump rom 0 1
+0x00000 loc1:                 08    .
+0x00001 loc2:                 04    .
+
+cont
+Simulation started, PC=0x00800c
+
+Stop at 0x00800c: (104) Breakpoint
+V-IHINZC  Flags= 0x2a  42 *  A= 0x00   0 .
+0-101010  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17ff [SP+1]= 00   0 .  Limit= 0x1500
+
+0x0800c    <.loop$0>:
+0x0800c    cc 80 0c       jp     0x800c <.loop$0>[0K
+F 0x00800c
+Simulated 2 ticks [ELIDED]
+Host usage: [ELIDED]
+dump rom 0 1
+0x00000 loc1:                 10    .
+0x00001 loc2:                 04    .
+
+cont
+Simulation started, PC=0x00800c
+
+Stop at 0x00800c: (104) Breakpoint
+V-IHINZC  Flags= 0x2a  42 *  A= 0x00   0 .
+0-101010  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17ff [SP+1]= 00   0 .  Limit= 0x1500
+
+0x0800c    <.loop$0>:
+0x0800c    cc 80 0c       jp     0x800c <.loop$0>[0K
+F 0x00800c
+Simulated 2 ticks [ELIDED]
+Host usage: [ELIDED]
+dump rom 0 1
+0x00000 loc1:                 30    0
+0x00001 loc2:                 05    .
+
+cont
+Simulation started, PC=0x00800c
+
+Stop at 0x00800c: (104) Breakpoint
+V-IHINZC  Flags= 0x2a  42 *  A= 0x00   0 .
+0-101010  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17ff [SP+1]= 00   0 .  Limit= 0x1500
+
+0x0800c    <.loop$0>:
+0x0800c    cc 80 0c       jp     0x800c <.loop$0>[0K
+F 0x00800c
+Simulated 2 ticks [ELIDED]
+Host usage: [ELIDED]
+timer get
+timer #1("time") ON 0.000020500000000 sec (41 clks)
+timer #2("isr") ON,ISR 0.000000000000000 sec (0 clks)
+timer #3("idle") ON,IDLE 0.000000000000000 sec (0 clks)
+timer #4("halt") ON,HALT 0.000000000000000 sec (0 clks)
+dump rom 0 1
+0x00000 loc1:                 20     
+0x00001 loc2:                 06    .
+
+set hw vcd pause
+Paused
+conf
+Type of microcontroller: STM8 S,AF 208
+Controller has 24 hardware element(s).
+   on cpu[0]
+   on simif[0]
+  off vcd[0]
+   on dreg[0]
+   on dport[0]
+   on clk[0]
+   on uart[1]
+   on uart[3]
+   on itc[0]
+   on pa[0]
+   on pb[0]
+   on pc[0]
+   on pd[0]
+   on pe[0]
+   on pf[0]
+   on pg[0]
+   on ph[0]
+   on pi[0]
+   on rst[0]
+   on tim1[1]
+   on tim2[2]
+   on tim3[3]
+   on tim4[4]
+   on flash[0]
+step
+
+Stop at 0x00800c: (109) stepped 2 ticks
+V-IHINZC  Flags= 0x2a  42 *  A= 0x00   0 .
+0-101010  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17ff [SP+1]= 00   0 .  Limit= 0x1500
+
+0x0800c    <.loop$0>:
+0x0800c    cc 80 0c       jp     0x800c <.loop$0>[0K
+F 0x00800c
+step
+
+Stop at 0x00800c: (109) stepped 2 ticks
+V-IHINZC  Flags= 0x2a  42 *  A= 0x00   0 .
+0-101010  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17ff [SP+1]= 00   0 .  Limit= 0x1500
+
+0x0800c    <.loop$0>:
+0x0800c    cc 80 0c       jp     0x800c <.loop$0>[0K
+F 0x00800c
+step
+
+Stop at 0x00800c: (109) stepped 2 ticks
+V-IHINZC  Flags= 0x2a  42 *  A= 0x00   0 .
+0-101010  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17ff [SP+1]= 00   0 .  Limit= 0x1500
+
+0x0800c    <.loop$0>:
+0x0800c    cc 80 0c       jp     0x800c <.loop$0>[0K
+F 0x00800c
+step
+
+Stop at 0x00800c: (109) stepped 2 ticks
+V-IHINZC  Flags= 0x2a  42 *  A= 0x00   0 .
+0-101010  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17ff [SP+1]= 00   0 .  Limit= 0x1500
+
+0x0800c    <.loop$0>:
+0x0800c    cc 80 0c       jp     0x800c <.loop$0>[0K
+F 0x00800c
+set hw vcd pause
+Unpaused
+conf
+Type of microcontroller: STM8 S,AF 208
+Controller has 24 hardware element(s).
+   on cpu[0]
+   on simif[0]
+   on vcd[0]
+   on dreg[0]
+   on dport[0]
+   on clk[0]
+   on uart[1]
+   on uart[3]
+   on itc[0]
+   on pa[0]
+   on pb[0]
+   on pc[0]
+   on pd[0]
+   on pe[0]
+   on pf[0]
+   on pg[0]
+   on ph[0]
+   on pi[0]
+   on rst[0]
+   on tim1[1]
+   on tim2[2]
+   on tim3[3]
+   on tim4[4]
+   on flash[0]
+timer get
+timer #1("time") ON 0.000024500000000 sec (49 clks)
+timer #2("isr") ON,ISR 0.000000000000000 sec (0 clks)
+timer #3("idle") ON,IDLE 0.000000000000000 sec (0 clks)
+timer #4("halt") ON,HALT 0.000000000000000 sec (0 clks)
+
+cont
+Simulation started, PC=0x00800c
+
+Stop at 0x00800c: (104) Breakpoint
+V-IHINZC  Flags= 0x2a  42 *  A= 0x00   0 .
+0-101010  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17ff [SP+1]= 00   0 .  Limit= 0x1500
+
+0x0800c    <.loop$0>:
+0x0800c    cc 80 0c       jp     0x800c <.loop$0>[0K
+F 0x00800c
+Simulated 2 ticks [ELIDED]
+Host usage: [ELIDED]
+dump rom 0 1
+0x00000 loc1:                 40    @
+0x00001 loc2:                 06    .
+
+cont
+Simulation started, PC=0x00800c
+
+Stop at 0x00800c: (104) Breakpoint
+V-IHINZC  Flags= 0x2a  42 *  A= 0x00   0 .
+0-101010  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17ff [SP+1]= 00   0 .  Limit= 0x1500
+
+0x0800c    <.loop$0>:
+0x0800c    cc 80 0c       jp     0x800c <.loop$0>[0K
+F 0x00800c
+Simulated 2 ticks [ELIDED]
+Host usage: [ELIDED]
+timer get
+timer #1("time") ON 0.000026500000000 sec (53 clks)
+timer #2("isr") ON,ISR 0.000000000000000 sec (0 clks)
+timer #3("idle") ON,IDLE 0.000000000000000 sec (0 clks)
+timer #4("halt") ON,HALT 0.000000000000000 sec (0 clks)
+dump rom 0 1
+0x00000 loc1:                 c0    .
+0x00001 loc2:                 07    .
+
+cont
+Simulation started, PC=0x00800c
+
+Stop at 0x00800c: (104) Breakpoint
+V-IHINZC  Flags= 0x2a  42 *  A= 0x00   0 .
+0-101010  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17ff [SP+1]= 00   0 .  Limit= 0x1500
+
+0x0800c    <.loop$0>:
+0x0800c    cc 80 0c       jp     0x800c <.loop$0>[0K
+F 0x00800c
+Simulated 2 ticks [ELIDED]
+Host usage: [ELIDED]
+dump rom 0 1
+0x00000 loc1:                 80    .
+0x00001 loc2:                 08    .
+
+cont
+Simulation started, PC=0x00800c
+
+Stop at 0x00800c: (104) Breakpoint
+V-IHINZC  Flags= 0x2a  42 *  A= 0x00   0 .
+0-101010  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17ff [SP+1]= 00   0 .  Limit= 0x1500
+
+0x0800c    <.loop$0>:
+0x0800c    cc 80 0c       jp     0x800c <.loop$0>[0K
+F 0x00800c
+Simulated 2 ticks [ELIDED]
+Host usage: [ELIDED]
+dump rom 0 1
+0x00000 loc1:                 81    .
+0x00001 loc2:                 08    .
+
+cont
+Simulation started, PC=0x00800c
+
+Stop at 0x00800c: (104) Breakpoint
+V-IHINZC  Flags= 0x2a  42 *  A= 0x00   0 .
+0-101010  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17ff [SP+1]= 00   0 .  Limit= 0x1500
+
+0x0800c    <.loop$0>:
+0x0800c    cc 80 0c       jp     0x800c <.loop$0>[0K
+F 0x00800c
+Simulated 2 ticks [ELIDED]
+Host usage: [ELIDED]
+dump rom 0 1
+0x00000 loc1:                 81    .
+0x00001 loc2:                 09    .
+
+cont
+Simulation started, PC=0x00800c
+
+Stop at 0x00800c: (104) Breakpoint
+V-IHINZC  Flags= 0x2a  42 *  A= 0x00   0 .
+0-101010  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17ff [SP+1]= 00   0 .  Limit= 0x1500
+
+0x0800c    <.loop$0>:
+0x0800c    cc 80 0c       jp     0x800c <.loop$0>[0K
+F 0x00800c
+Simulated 2 ticks [ELIDED]
+Host usage: [ELIDED]
+dump rom 0 1
+0x00000 loc1:                 80    .
+0x00001 loc2:                 09    .
+
+cont
+Simulation started, PC=0x00800c
+
+Stop at 0x00800c: (104) Breakpoint
+V-IHINZC  Flags= 0x2a  42 *  A= 0x00   0 .
+0-101010  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17ff [SP+1]= 00   0 .  Limit= 0x1500
+
+0x0800c    <.loop$0>:
+0x0800c    cc 80 0c       jp     0x800c <.loop$0>[0K
+F 0x00800c
+Simulated 2 ticks [ELIDED]
+Host usage: [ELIDED]
+dump rom 0 1
+0x00000 loc1:                 84    .
+0x00001 loc2:                 0a    .
+
+cont
+Simulation started, PC=0x00800c
+
+Stop at 0x00800c: (104) Breakpoint
+V-IHINZC  Flags= 0x2a  42 *  A= 0x00   0 .
+0-101010  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17ff [SP+1]= 00   0 .  Limit= 0x1500
+
+0x0800c    <.loop$0>:
+0x0800c    cc 80 0c       jp     0x800c <.loop$0>[0K
+F 0x00800c
+Simulated 2 ticks [ELIDED]
+Host usage: [ELIDED]
+dump rom 0 1
+0x00000 loc1:                 84    .
+0x00001 loc2:                 0b    .
+
+cont
+Simulation started, PC=0x00800c
+
+Stop at 0x00800c: (104) Breakpoint
+V-IHINZC  Flags= 0x2a  42 *  A= 0x00   0 .
+0-101010  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17ff [SP+1]= 00   0 .  Limit= 0x1500
+
+0x0800c    <.loop$0>:
+0x0800c    cc 80 0c       jp     0x800c <.loop$0>[0K
+F 0x00800c
+Simulated 2 ticks [ELIDED]
+Host usage: [ELIDED]
+dump rom 0 1
+0x00000 loc1:                 80    .
+0x00001 loc2:                 0b    .
+
+cont
+Simulation started, PC=0x00800c
+
+Stop at 0x00800c: (104) Breakpoint
+V-IHINZC  Flags= 0x2a  42 *  A= 0x00   0 .
+0-101010  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17ff [SP+1]= 00   0 .  Limit= 0x1500
+
+0x0800c    <.loop$0>:
+0x0800c    cc 80 0c       jp     0x800c <.loop$0>[0K
+F 0x00800c
+Simulated 2 ticks [ELIDED]
+Host usage: [ELIDED]
+dump rom 0 1
+0x00000 loc1:                 90    .
+0x00001 loc2:                 0c    .
+
+cont
+Simulation started, PC=0x00800c
+
+Stop at 0x00800c: (104) Breakpoint
+V-IHINZC  Flags= 0x2a  42 *  A= 0x00   0 .
+0-101010  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17ff [SP+1]= 00   0 .  Limit= 0x1500
+
+0x0800c    <.loop$0>:
+0x0800c    cc 80 0c       jp     0x800c <.loop$0>[0K
+F 0x00800c
+Simulated 2 ticks [ELIDED]
+Host usage: [ELIDED]
+dump rom 0 1
+0x00000 loc1:                 90    .
+0x00001 loc2:                 0d    .
+
+cont
+Simulation started, PC=0x00800c
+
+Stop at 0x00800c: (104) Breakpoint
+V-IHINZC  Flags= 0x2a  42 *  A= 0x00   0 .
+0-101010  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17ff [SP+1]= 00   0 .  Limit= 0x1500
+
+0x0800c    <.loop$0>:
+0x0800c    cc 80 0c       jp     0x800c <.loop$0>[0K
+F 0x00800c
+Simulated 2 ticks [ELIDED]
+Host usage: [ELIDED]
+dump rom 0 1
+0x00000 loc1:                 80    .
+0x00001 loc2:                 0d    .
+
+# Stop now
+set hw vcd stop
+conf
+Type of microcontroller: STM8 S,AF 208
+Controller has 24 hardware element(s).
+   on cpu[0]
+   on simif[0]
+  off vcd[0]
+   on dreg[0]
+   on dport[0]
+   on clk[0]
+   on uart[1]
+   on uart[3]
+   on itc[0]
+   on pa[0]
+   on pb[0]
+   on pc[0]
+   on pd[0]
+   on pe[0]
+   on pf[0]
+   on pg[0]
+   on ph[0]
+   on pi[0]
+   on rst[0]
+   on tim1[1]
+   on tim2[2]
+   on tim3[3]
+   on tim4[4]
+   on flash[0]
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/vcd-in/Makefile sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/vcd-in/Makefile
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/vcd-in/Makefile	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/vcd-in/Makefile	2021-04-16 22:01:11.000000000 +0000
@@ -0,0 +1,10 @@
+OUTPUTS = stdout
+
+
+# N.B. We name and open the input VCD file here because if this
+# is an out-of-tree build we want make to tell us the pathname.
+$(OUTPUTS):	test.cmd test.ihx test.vcd
+	$(call run-sim, -e 'set hw vcd input "$(filter %.vcd,$+)"')
+
+
+include test-lib.mk
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/vcd-in/test.asm sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/vcd-in/test.asm
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/vcd-in/test.asm	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/vcd-in/test.asm	2021-04-16 22:01:11.000000000 +0000
@@ -0,0 +1,14 @@
+	.area _DATA
+loc1:	.ds 1
+loc2:	.ds 1
+
+	.area _CODE
+	int reset
+
+reset:
+	ld a, #0
+	ld loc1, a
+	ld loc2, a
+
+loop:
+	jp loop
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/vcd-in/test.cmd sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/vcd-in/test.cmd
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/vcd-in/test.cmd	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/vcd-in/test.cmd	2022-01-20 15:57:08.000000000 +0000
@@ -0,0 +1,107 @@
+# These are the test locations named in the input vcd.
+var loc1 rom[0x0000]
+var loc2 rom[0x0001]
+
+# Run the initialization code and stop when we reach the
+# first test loop.
+break 0x800c
+run
+clear 0x800c
+
+# Start the vcd (we set the input file via the Makefile) and
+# have it stop execution each time an event occurs.
+set hw vcd start
+set hw vcd break
+
+# The VCD data starts at time 0 which will, by default, align
+# with the current simulator time. We can adjust that by setting
+# starttime. This can be done before or after starting the vcd,
+# even part way through. Here we push the vcd 5 µs into the
+# future.
+set hw vcd starttime 5 us
+
+# Make sure what it is going to do is what we asked.
+conf
+info hw vcd
+
+# Continue until an event stops us then dump the locations
+# that the vcd is driving according to the input file.
+# Repeat a sufficient number of times.
+cont
+dump rom 0 1
+
+cont
+dump rom 0 1
+
+cont
+dump rom 0 1
+
+cont
+dump rom 0 1
+
+cont
+dump rom 0 1
+
+cont
+dump rom 0 1
+
+cont
+dump rom 0 1
+
+cont
+dump rom 0 1
+
+cont
+timer get
+dump rom 0 1
+
+set hw vcd pause
+conf
+step
+step
+step
+step
+set hw vcd pause
+conf
+timer get
+
+cont
+dump rom 0 1
+
+cont
+timer get
+dump rom 0 1
+
+cont
+dump rom 0 1
+
+cont
+dump rom 0 1
+
+cont
+dump rom 0 1
+
+cont
+dump rom 0 1
+
+cont
+dump rom 0 1
+
+cont
+dump rom 0 1
+
+cont
+dump rom 0 1
+
+cont
+dump rom 0 1
+
+cont
+dump rom 0 1
+
+cont
+dump rom 0 1
+
+# Stop now
+set hw vcd stop
+conf
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/vcd-in/test.vcd sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/vcd-in/test.vcd
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/vcd-in/test.vcd	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/vcd-in/test.vcd	2022-01-20 15:57:08.000000000 +0000
@@ -0,0 +1,108 @@
+$date
+	Sat Aug 22 00:57:06 2020
+$end
+$version
+	ucsim
+$end
+$timescale 1ps $end
+$scope module ucsim_vcd_0 $end
+$var wire 1 ! loc1.0 $end
+$var wire 1 " loc1.1 $end
+$var wire 1 # loc1.2 $end
+$var wire 1 $ loc1.3 $end
+$var wire 1 % loc1.4 $end
+$var wire 1 & loc1.5 $end
+$var wire 1 ' loc1.6 $end
+$var wire 1 ( loc1.7 $end
+$var wire 8 ) loc2[7:0] $end
+$upscope $end
+$enddefinitions $end
+$dumpvars
+0!
+0"
+0#
+0$
+0%
+0&
+0'
+0(
+b00000000 )
+$end
+#2500000
+1!
+#3500000
+b00000001 )
+#4000000
+1"
+#4500000
+0!
+#5000000
+b00000010 )
+#5500000
+1#
+#6000000
+0"
+#6500000
+b00000011 )
+#7000000
+1$
+#7500000
+0#
+#8000000
+b00000100 )
+#8500000
+1%
+#9000000
+0$
+#9500000
+b00000101 )
+#10000000
+1&
+#10500000
+0%
+#11000000
+b00000110 )
+#11500000
+1'
+#12000000
+0&
+#12500000
+b00000111 )
+#13000000
+1(
+#13500000
+0'
+#14000000
+b00001000 )
+#15000000
+1!
+#16000000
+b00001001 )
+#17000000
+0!
+#17500000
+b00001010 )
+#18000000
+1#
+#19000000
+b00001011 )
+#20000000
+0#
+#20500000
+b00001100 )
+#21000000
+1%
+#22000000
+b00001101 )
+#23000000
+0%
+#23500000
+b00001110 )
+#24000000
+1'
+#25000000
+b00001111 )
+#26000000
+0'
+#26500000
+b00010000 )
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/vcd-op/baseline/stdout sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/vcd-op/baseline/stdout
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/vcd-op/baseline/stdout	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/vcd-op/baseline/stdout	2022-02-08 21:21:05.000000000 +0000
@@ -0,0 +1,409 @@
+uCsim, Copyright (C)  Daniel Drotos.
+uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+This is free software, and you are welcome to redistribute it
+under certain conditions; type `show c' for details.
+# Test vcd operations
+# Note that with the default clock settings on the STM8 we have
+# a tick of 125 ns.
+set hw vcd output "out/test.vcd"
+set hw vcd add rom[0x100]
+set hw vcd start
+info hw vcd
+vcd[0] value change dump
+  Modul:      ucsim_vcd_0
+  Started:    YES
+  Paused:     no
+  Mode:       output
+  Time scale: 1 ns
+  Start time: 0.000000000000000 s
+  Last event: 0.000000000000000 s
+  Pause time: 
+  Simul time: 0.000000000000000 s
+  Variables:
+    Address           Symbol
+    rom[0x00100]      
+
+# Four ticks (500 ns) of changing data
+set mem rom[0x100] 0
+0x00100                       00 .
+tick
+set mem rom[0x100] 1
+0x00100                       01 .
+tick
+set mem rom[0x100] 2
+0x00100                       02 .
+tick
+set mem rom[0x100] 3
+0x00100                       03 .
+tick
+
+# Now pause for 8 ticks (1000 ns).
+# Pause duration is not limited so all the following ticks are
+# recorded but not values.
+info hw vcd
+vcd[0] value change dump
+  Modul:      ucsim_vcd_0
+  Started:    YES
+  Paused:     no
+  Mode:       output
+  Time scale: 1 ns
+  Start time: 0.000000000000000 s
+  Last event: 0.000001500000000 s
+  Pause time: 
+  Simul time: 0.000002000000000 s
+  Variables:
+    Address           Symbol
+    rom[0x00100]      
+set hw vcd pause
+Paused
+info hw vcd
+vcd[0] value change dump
+  Modul:      ucsim_vcd_0
+  Started:    YES
+  Paused:     YES
+  Mode:       output
+  Time scale: 1 ns
+  Start time: 0.000000000000000 s
+  Last event: 0.000002000000000 s
+  Pause time: 
+  Simul time: 0.000002000000000 s
+  Variables:
+    Address           Symbol
+    rom[0x00100]      
+set mem rom[0x100] 4
+0x00100                       04 .
+tick
+set mem rom[0x100] 5
+0x00100                       05 .
+tick
+set mem rom[0x100] 6
+0x00100                       06 .
+tick
+set mem rom[0x100] 7
+0x00100                       07 .
+tick
+set mem rom[0x100] 8
+0x00100                       08 .
+tick
+set mem rom[0x100] 9
+0x00100                       09 .
+tick
+set mem rom[0x100] 10
+0x00100                       0a .
+tick
+set mem rom[0x100] 11
+0x00100                       0b .
+tick
+
+# Resume. States are updated to current values and recording resumes.
+info hw vcd
+vcd[0] value change dump
+  Modul:      ucsim_vcd_0
+  Started:    YES
+  Paused:     YES
+  Mode:       output
+  Time scale: 1 ns
+  Start time: 0.000000000000000 s
+  Last event: 0.000002000000000 s
+  Pause time: 
+  Simul time: 0.000006000000000 s
+  Variables:
+    Address           Symbol
+    rom[0x00100]      
+set hw vcd restart
+Unpaused
+info hw vcd
+vcd[0] value change dump
+  Modul:      ucsim_vcd_0
+  Started:    YES
+  Paused:     no
+  Mode:       output
+  Time scale: 1 ns
+  Start time: 0.000000000000000 s
+  Last event: 0.000006000000000 s
+  Pause time: 
+  Simul time: 0.000006000000000 s
+  Variables:
+    Address           Symbol
+    rom[0x00100]      
+set mem rom[0x100] 12
+0x00100                       0c .
+tick
+set mem rom[0x100] 13
+0x00100                       0d .
+tick
+set mem rom[0x100] 14
+0x00100                       0e .
+tick
+set mem rom[0x100] 15
+0x00100                       0f .
+tick
+
+# Pause again for 8 ticks (1000 ns) but this time limit the pause duration
+# to 300 ns. Note that since we are limited by tick granularity we will
+# record the first 3 ticks (375 ns) then ignore the rest.
+info hw vcd
+vcd[0] value change dump
+  Modul:      ucsim_vcd_0
+  Started:    YES
+  Paused:     no
+  Mode:       output
+  Time scale: 1 ns
+  Start time: 0.000000000000000 s
+  Last event: 0.000007500000000 s
+  Pause time: 
+  Simul time: 0.000008000000000 s
+  Variables:
+    Address           Symbol
+    rom[0x00100]      
+set hw vcd pausetime 300 ns
+set hw vcd pause
+Paused (pause limit 0.000000300000000 s)
+info hw vcd
+vcd[0] value change dump
+  Modul:      ucsim_vcd_0
+  Started:    YES
+  Paused:     YES
+  Mode:       output
+  Time scale: 1 ns
+  Start time: 0.000000000000000 s
+  Last event: 0.000008000000000 s
+  Pause time: 0.000000300000000 s
+  Simul time: 0.000008000000000 s
+  Variables:
+    Address           Symbol
+    rom[0x00100]      
+# vcd[0] should be clocked (on) until we have exceeded the pause limit.
+conf
+Type of microcontroller: STM8 S,AF 208
+Controller has 24 hardware element(s).
+   on cpu[0]
+   on simif[0]
+   on vcd[0]
+   on dreg[0]
+   on dport[0]
+   on clk[0]
+   on uart[1]
+   on uart[3]
+   on itc[0]
+   on pa[0]
+   on pb[0]
+   on pc[0]
+   on pd[0]
+   on pe[0]
+   on pf[0]
+   on pg[0]
+   on ph[0]
+   on pi[0]
+   on rst[0]
+   on tim1[1]
+   on tim2[2]
+   on tim3[3]
+   on tim4[4]
+   on flash[0]
+set mem rom[0x100] 16
+0x00100                       10 .
+tick
+conf
+Type of microcontroller: STM8 S,AF 208
+Controller has 24 hardware element(s).
+   on cpu[0]
+   on simif[0]
+  off vcd[0]
+   on dreg[0]
+   on dport[0]
+   on clk[0]
+   on uart[1]
+   on uart[3]
+   on itc[0]
+   on pa[0]
+   on pb[0]
+   on pc[0]
+   on pd[0]
+   on pe[0]
+   on pf[0]
+   on pg[0]
+   on ph[0]
+   on pi[0]
+   on rst[0]
+   on tim1[1]
+   on tim2[2]
+   on tim3[3]
+   on tim4[4]
+   on flash[0]
+set mem rom[0x100] 17
+0x00100                       11 .
+tick
+conf
+Type of microcontroller: STM8 S,AF 208
+Controller has 24 hardware element(s).
+   on cpu[0]
+   on simif[0]
+  off vcd[0]
+   on dreg[0]
+   on dport[0]
+   on clk[0]
+   on uart[1]
+   on uart[3]
+   on itc[0]
+   on pa[0]
+   on pb[0]
+   on pc[0]
+   on pd[0]
+   on pe[0]
+   on pf[0]
+   on pg[0]
+   on ph[0]
+   on pi[0]
+   on rst[0]
+   on tim1[1]
+   on tim2[2]
+   on tim3[3]
+   on tim4[4]
+   on flash[0]
+set mem rom[0x100] 18
+0x00100                       12 .
+tick
+conf
+Type of microcontroller: STM8 S,AF 208
+Controller has 24 hardware element(s).
+   on cpu[0]
+   on simif[0]
+  off vcd[0]
+   on dreg[0]
+   on dport[0]
+   on clk[0]
+   on uart[1]
+   on uart[3]
+   on itc[0]
+   on pa[0]
+   on pb[0]
+   on pc[0]
+   on pd[0]
+   on pe[0]
+   on pf[0]
+   on pg[0]
+   on ph[0]
+   on pi[0]
+   on rst[0]
+   on tim1[1]
+   on tim2[2]
+   on tim3[3]
+   on tim4[4]
+   on flash[0]
+set mem rom[0x100] 19
+0x00100                       13 .
+tick
+conf
+Type of microcontroller: STM8 S,AF 208
+Controller has 24 hardware element(s).
+   on cpu[0]
+   on simif[0]
+  off vcd[0]
+   on dreg[0]
+   on dport[0]
+   on clk[0]
+   on uart[1]
+   on uart[3]
+   on itc[0]
+   on pa[0]
+   on pb[0]
+   on pc[0]
+   on pd[0]
+   on pe[0]
+   on pf[0]
+   on pg[0]
+   on ph[0]
+   on pi[0]
+   on rst[0]
+   on tim1[1]
+   on tim2[2]
+   on tim3[3]
+   on tim4[4]
+   on flash[0]
+set mem rom[0x100] 20
+0x00100                       14 .
+tick
+set mem rom[0x100] 21
+0x00100                       15 .
+tick
+set mem rom[0x100] 22
+0x00100                       16 .
+tick
+set mem rom[0x100] 23
+0x00100                       17 .
+tick
+
+# Resume again. The recorded gap is limited by the pausetime. There are
+# comments placed in the VCD to indicate the real duration but it's up
+# to the viewer whether they are shown at all.
+info hw vcd
+vcd[0] value change dump
+  Modul:      ucsim_vcd_0
+  Started:    YES
+  Paused:     YES
+  Mode:       output
+  Time scale: 1 ns
+  Start time: 0.000000000000000 s
+  Last event: 0.000008000000000 s
+  Pause time: 0.000000300000000 s
+  Simul time: 0.000012000000000 s
+  Variables:
+    Address           Symbol
+    rom[0x00100]      
+set hw vcd restart
+Unpaused
+info hw vcd
+vcd[0] value change dump
+  Modul:      ucsim_vcd_0
+  Started:    YES
+  Paused:     no
+  Mode:       output
+  Time scale: 1 ns
+  Start time: 0.000003700000000 s
+  Last event: 0.000012000000000 s
+  Pause time: 0.000000300000000 s
+  Simul time: 0.000012000000000 s
+  Variables:
+    Address           Symbol
+    rom[0x00100]      
+set mem rom[0x100] 24
+0x00100                       18 .
+tick
+set mem rom[0x100] 25
+0x00100                       19 .
+tick
+set mem rom[0x100] 26
+0x00100                       1a .
+tick
+
+# That's all folks!
+info hw vcd
+vcd[0] value change dump
+  Modul:      ucsim_vcd_0
+  Started:    YES
+  Paused:     no
+  Mode:       output
+  Time scale: 1 ns
+  Start time: 0.000003700000000 s
+  Last event: 0.000013000000000 s
+  Pause time: 0.000000300000000 s
+  Simul time: 0.000013500000000 s
+  Variables:
+    Address           Symbol
+    rom[0x00100]      
+set hw vcd stop
+info hw vcd
+vcd[0] value change dump
+  Modul:      ucsim_vcd_0
+  Started:    no
+  Paused:     no
+  Mode:       output
+  Time scale: 1 ns
+  Start time: 0.000000000000000 s
+  Last event: 0.000000000000000 s
+  Pause time: 0.000000300000000 s
+  Simul time: 0.000013500000000 s
+  Variables:
+    Address           Symbol
+    rom[0x00100]      
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/vcd-op/baseline/test.vcd sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/vcd-op/baseline/test.vcd
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/vcd-op/baseline/test.vcd	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/vcd-op/baseline/test.vcd	2022-02-02 07:12:49.000000000 +0000
@@ -0,0 +1,55 @@
+$date
+	[ELIDED]
+$end
+$version
+	ucsim
+$end
+$timescale 1ns $end
+$scope module ucsim_vcd_0 $end
+$var wire 8 ! rom_0x00100 $end
+$upscope $end
+$enddefinitions $end
+#0
+$dumpvars
+b10010101 !
+$end
+b00000000 !
+#500
+b00000001 !
+#1000
+b00000010 !
+#1500
+b00000011 !
+#2000
+$comment Paused $end
+$dumpoff
+bxxxxxxxx !
+$end
+#6000
+$comment Unpaused $end
+$dumpon
+b00001011 !
+$end
+b00001100 !
+#6500
+b00001101 !
+#7000
+b00001110 !
+#7500
+b00001111 !
+#8000
+$comment Paused $end
+$dumpoff
+bxxxxxxxx !
+$end
+#8300
+$comment Unpaused. Real duration was 0.000004000000000 seconds $end
+$dumpon
+b00010111 !
+$end
+b00011000 !
+#8800
+b00011001 !
+#9300
+b00011010 !
+#9800
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/vcd-op/Makefile sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/vcd-op/Makefile
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/vcd-op/Makefile	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/vcd-op/Makefile	2022-01-09 14:14:40.000000000 +0000
@@ -0,0 +1,8 @@
+OUTPUTS = stdout
+
+
+$(OUTPUTS):	test.cmd
+	$(call run-sim)
+
+
+include test-lib.mk
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/vcd-op/test.cmd sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/vcd-op/test.cmd
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/vcd-op/test.cmd	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/vcd-op/test.cmd	2022-02-02 07:12:49.000000000 +0000
@@ -0,0 +1,101 @@
+# Test vcd operations
+# Note that with the default clock settings on the STM8 we have
+# a tick of 125 ns.
+set hw vcd output "out/test.vcd"
+set hw vcd add rom[0x100]
+set hw vcd start
+info hw vcd
+
+# Four ticks (500 ns) of changing data
+set mem rom[0x100] 0
+tick
+set mem rom[0x100] 1
+tick
+set mem rom[0x100] 2
+tick
+set mem rom[0x100] 3
+tick
+
+# Now pause for 8 ticks (1000 ns).
+# Pause duration is not limited so all the following ticks are
+# recorded but not values.
+info hw vcd
+set hw vcd pause
+info hw vcd
+set mem rom[0x100] 4
+tick
+set mem rom[0x100] 5
+tick
+set mem rom[0x100] 6
+tick
+set mem rom[0x100] 7
+tick
+set mem rom[0x100] 8
+tick
+set mem rom[0x100] 9
+tick
+set mem rom[0x100] 10
+tick
+set mem rom[0x100] 11
+tick
+
+# Resume. States are updated to current values and recording resumes.
+info hw vcd
+set hw vcd restart
+info hw vcd
+set mem rom[0x100] 12
+tick
+set mem rom[0x100] 13
+tick
+set mem rom[0x100] 14
+tick
+set mem rom[0x100] 15
+tick
+
+# Pause again for 8 ticks (1000 ns) but this time limit the pause duration
+# to 300 ns. Note that since we are limited by tick granularity we will
+# record the first 3 ticks (375 ns) then ignore the rest.
+info hw vcd
+set hw vcd pausetime 300 ns
+set hw vcd pause
+info hw vcd
+# vcd[0] should be clocked (on) until we have exceeded the pause limit.
+conf
+set mem rom[0x100] 16
+tick
+conf
+set mem rom[0x100] 17
+tick
+conf
+set mem rom[0x100] 18
+tick
+conf
+set mem rom[0x100] 19
+tick
+conf
+set mem rom[0x100] 20
+tick
+set mem rom[0x100] 21
+tick
+set mem rom[0x100] 22
+tick
+set mem rom[0x100] 23
+tick
+
+# Resume again. The recorded gap is limited by the pausetime. There are
+# comments placed in the VCD to indicate the real duration but it's up
+# to the viewer whether they are shown at all.
+info hw vcd
+set hw vcd restart
+info hw vcd
+set mem rom[0x100] 24
+tick
+set mem rom[0x100] 25
+tick
+set mem rom[0x100] 26
+tick
+
+# That's all folks!
+info hw vcd
+set hw vcd stop
+info hw vcd
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/vcd-out/baseline/stdout sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/vcd-out/baseline/stdout
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/vcd-out/baseline/stdout	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/vcd-out/baseline/stdout	2022-02-08 21:21:05.000000000 +0000
@@ -0,0 +1,124 @@
+uCsim, Copyright (C)  Daniel Drotos.
+uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+This is free software, and you are welcome to redistribute it
+under certain conditions; type `show c' for details.
+# These are our test locations to be probed.
+var loc1 rom[0x0000]
+var loc2 rom[0x0001]
+
+# Check the initial state of the default vcd.
+info hw vcd
+vcd[0] value change dump
+  Modul:      ucsim_vcd_0
+  Started:    no
+  Paused:     no
+  Mode:       output
+  Time scale: auto set on start
+  Start time: 0.000000000000000 s
+  Last event: 0.000000000000000 s
+  Pause time: 
+  Simul time: 0.000000000000000 s
+  Variables:
+    Address           Symbol
+
+# Run the initialization code and stop when we reach the
+# first test loop.
+break 0x800c
+Breakpoint 1 at 0x00800c: 
+0x0800c    <.loop$0>:
+0x0800c F  72 10 00 00    bset   0x0000 ,#0 (cond="")
+run
+Simulation started, PC=0x008000
+
+Stop at 0x00800c: (104) Breakpoint
+V-IHINZC  Flags= 0x2a  42 *  A= 0x00   0 .
+0-101010  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17ff [SP+1]= 00   0 .  Limit= 0x1500
+
+0x0800c    <.loop$0>:
+0x0800c F  72 10 00 00    bset   0x0000 ,#0[0K
+F 0x00800c
+Simulated 8 ticks [ELIDED]
+Host usage: [ELIDED]
+
+# Set up a vcd to monitor the bit changes in loc1 and the value of loc2.
+set hw vcd output "out/test.vcd"
+set hw vcd add loc1.0
+set hw vcd add loc1.1
+set hw vcd add loc1.2
+set hw vcd add loc1.3
+set hw vcd add loc1.4
+set hw vcd add loc1.5
+set hw vcd add loc1.6
+set hw vcd add loc1.7
+set hw vcd add loc2
+set hw vcd start
+
+# Make sure what it is going to do is what we asked.
+info hw vcd
+vcd[0] value change dump
+  Modul:      ucsim_vcd_0
+  Started:    YES
+  Paused:     no
+  Mode:       output
+  Time scale: 1 ns
+  Start time: 0.000004000000000 s
+  Last event: 0.000004000000000 s
+  Pause time: 
+  Simul time: 0.000004000000000 s
+  Variables:
+    Address           Symbol
+    rom[0x00000].0    loc1.0
+    rom[0x00000].1    loc1.1
+    rom[0x00000].2    loc1.2
+    rom[0x00000].3    loc1.3
+    rom[0x00000].4    loc1.4
+    rom[0x00000].5    loc1.5
+    rom[0x00000].6    loc1.6
+    rom[0x00000].7    loc1.7
+    rom[0x00001]      loc2
+
+# Run the first loop and stop when we hit the breakpoint again.
+cont
+Simulation started, PC=0x00800c
+
+Stop at 0x00800c: (104) Breakpoint
+V-IHINZC  Flags= 0x28  40 (  A= 0x00   0 .
+0-101000  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17ff [SP+1]= 00   0 .  Limit= 0x1500
+
+0x0800c    <.loop$0>:
+0x0800c F  72 10 00 00    bset   0x0000 ,#0[0K
+F 0x00800c
+Simulated 49 ticks [ELIDED]
+Host usage: [ELIDED]
+
+# Remove the probe from every second bit.
+# Removing probes while started is ok - we just stop logging changes.
+set hw vcd del loc1.1
+set hw vcd del loc1.3
+set hw vcd del loc1.5
+set hw vcd del loc1.7
+
+# We can't add anything though because that would require a change to the
+# header and it's far too late for that.
+set hw vcd add loc1.3
+Already started
+
+# Run the second loop and stop when we hit the breakpoint again.
+cont
+Simulation started, PC=0x00800c
+
+Stop at 0x00800c: (104) Breakpoint
+V-IHINZC  Flags= 0x28  40 (  A= 0x00   0 .
+0-101000  X= 0x0000   0 .    Y= 0x0000   0 .
+SP= 0x17ff [SP+1]= 00   0 .  Limit= 0x1500
+
+0x0800c    <.loop$0>:
+0x0800c F  72 10 00 00    bset   0x0000 ,#0[0K
+F 0x00800c
+Simulated 49 ticks [ELIDED]
+Host usage: [ELIDED]
+
+# Don't forget to close the vcd properly!
+set hw vcd stop
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/vcd-out/baseline/test.vcd sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/vcd-out/baseline/test.vcd
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/vcd-out/baseline/test.vcd	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/vcd-out/baseline/test.vcd	2022-01-20 15:57:08.000000000 +0000
@@ -0,0 +1,288 @@
+$date
+	[ELIDED]
+$end
+$version
+	ucsim
+$end
+$timescale 1ns $end
+$scope module ucsim_vcd_0 $end
+$var wire 1 ! loc1.0 $end
+$var wire 1 " loc1.1 $end
+$var wire 1 # loc1.2 $end
+$var wire 1 $ loc1.3 $end
+$var wire 1 % loc1.4 $end
+$var wire 1 & loc1.5 $end
+$var wire 1 ' loc1.6 $end
+$var wire 1 ( loc1.7 $end
+$var wire 8 ) loc2 $end
+$upscope $end
+$enddefinitions $end
+#0
+$dumpvars
+0!
+0"
+0#
+0$
+0%
+0&
+0'
+0(
+b00000000 )
+$end
+#1000
+1!
+0"
+0#
+0$
+0%
+0&
+0'
+0(
+#2000
+1!
+0"
+0#
+0$
+0%
+0&
+0'
+0(
+#3000
+b00000001 )
+#4000
+1!
+1"
+0#
+0$
+0%
+0&
+0'
+0(
+#5000
+0!
+1"
+0#
+0$
+0%
+0&
+0'
+0(
+#6000
+b00000010 )
+#7000
+0!
+1"
+1#
+0$
+0%
+0&
+0'
+0(
+#8000
+0!
+0"
+1#
+0$
+0%
+0&
+0'
+0(
+#9000
+b00000011 )
+#10000
+0!
+0"
+1#
+1$
+0%
+0&
+0'
+0(
+#11000
+0!
+0"
+0#
+1$
+0%
+0&
+0'
+0(
+#12000
+b00000100 )
+#13000
+0!
+0"
+0#
+1$
+1%
+0&
+0'
+0(
+#14000
+0!
+0"
+0#
+0$
+1%
+0&
+0'
+0(
+#15000
+b00000101 )
+#16000
+0!
+0"
+0#
+0$
+1%
+1&
+0'
+0(
+#17000
+0!
+0"
+0#
+0$
+0%
+1&
+0'
+0(
+#18000
+b00000110 )
+#19000
+0!
+0"
+0#
+0$
+0%
+1&
+1'
+0(
+#20000
+0!
+0"
+0#
+0$
+0%
+0&
+1'
+0(
+#21000
+b00000111 )
+#22000
+0!
+0"
+0#
+0$
+0%
+0&
+1'
+1(
+#23000
+0!
+0"
+0#
+0$
+0%
+0&
+0'
+1(
+#24000
+b00001000 )
+#25500
+1!
+0#
+0%
+0'
+#26500
+1!
+0#
+0%
+0'
+#27500
+b00001001 )
+#28500
+1!
+0#
+0%
+0'
+#29500
+0!
+0#
+0%
+0'
+#30500
+b00001010 )
+#31500
+0!
+1#
+0%
+0'
+#32500
+0!
+1#
+0%
+0'
+#33500
+b00001011 )
+#34500
+0!
+1#
+0%
+0'
+#35500
+0!
+0#
+0%
+0'
+#36500
+b00001100 )
+#37500
+0!
+0#
+1%
+0'
+#38500
+0!
+0#
+1%
+0'
+#39500
+b00001101 )
+#40500
+0!
+0#
+1%
+0'
+#41500
+0!
+0#
+0%
+0'
+#42500
+b00001110 )
+#43500
+0!
+0#
+0%
+1'
+#44500
+0!
+0#
+0%
+1'
+#45500
+b00001111 )
+#46500
+0!
+0#
+0%
+1'
+#47500
+0!
+0#
+0%
+0'
+#48500
+b00010000 )
+#49000
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/vcd-out/Makefile sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/vcd-out/Makefile
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/vcd-out/Makefile	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/vcd-out/Makefile	2021-04-16 22:01:11.000000000 +0000
@@ -0,0 +1,8 @@
+OUTPUTS = stdout
+
+
+$(OUTPUTS):	test.cmd test.ihx
+	$(call run-sim)
+
+
+include test-lib.mk
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/vcd-out/test.asm sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/vcd-out/test.asm
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/vcd-out/test.asm	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/vcd-out/test.asm	2021-04-16 22:01:11.000000000 +0000
@@ -0,0 +1,46 @@
+	.area _DATA
+loc1:	.ds 1
+loc2:	.ds 1
+
+	.area _CODE
+	int reset
+
+reset:
+	ld a, #0
+	ld loc1, a
+	ld loc2, a
+
+loop:
+	bset loc1, #0
+	bres loc1, #7
+	inc loc2
+
+	bset loc1, #1
+	bres loc1, #0
+	inc loc2
+
+	bset loc1, #2
+	bres loc1, #1
+	inc loc2
+
+	bset loc1, #3
+	bres loc1, #2
+	inc loc2
+
+	bset loc1, #4
+	bres loc1, #3
+	inc loc2
+
+	bset loc1, #5
+	bres loc1, #4
+	inc loc2
+
+	bset loc1, #6
+	bres loc1, #5
+	inc loc2
+
+	bset loc1, #7
+	bres loc1, #6
+	inc loc2
+
+	jp loop
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/vcd-out/test.cmd sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/vcd-out/test.cmd
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/vcd-out/test.cmd	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/vcd-out/test.cmd	2022-01-09 14:14:40.000000000 +0000
@@ -0,0 +1,47 @@
+# These are our test locations to be probed.
+var loc1 rom[0x0000]
+var loc2 rom[0x0001]
+
+# Check the initial state of the default vcd.
+info hw vcd
+
+# Run the initialization code and stop when we reach the
+# first test loop.
+break 0x800c
+run
+
+# Set up a vcd to monitor the bit changes in loc1 and the value of loc2.
+set hw vcd output "out/test.vcd"
+set hw vcd add loc1.0
+set hw vcd add loc1.1
+set hw vcd add loc1.2
+set hw vcd add loc1.3
+set hw vcd add loc1.4
+set hw vcd add loc1.5
+set hw vcd add loc1.6
+set hw vcd add loc1.7
+set hw vcd add loc2
+set hw vcd start
+
+# Make sure what it is going to do is what we asked.
+info hw vcd
+
+# Run the first loop and stop when we hit the breakpoint again.
+cont
+
+# Remove the probe from every second bit.
+# Removing probes while started is ok - we just stop logging changes.
+set hw vcd del loc1.1
+set hw vcd del loc1.3
+set hw vcd del loc1.5
+set hw vcd del loc1.7
+
+# We can't add anything though because that would require a change to the
+# header and it's far too late for that.
+set hw vcd add loc1.3
+
+# Run the second loop and stop when we hit the breakpoint again.
+cont
+
+# Don't forget to close the vcd properly!
+set hw vcd stop
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/xtest.c sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/xtest.c
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/xtest.c	2017-02-03 18:14:56.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/xtest.c	1970-01-01 00:00:00.000000000 +0000
@@ -1,10 +0,0 @@
-#include 
-
-char buf[10];
-
-void
-main(void)
-{
-  sprintf(buf, "%x", 0x1234);
-  for (;;);
-}
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/xtest.mk sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/xtest.mk
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/test/xtest.mk	2018-01-25 13:48:09.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/test/xtest.mk	1970-01-01 00:00:00.000000000 +0000
@@ -1 +0,0 @@
-DEVICES		= LDISC
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/timer.cc sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/timer.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/timer.cc	2019-04-02 10:46:33.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/timer.cc	2021-11-02 13:14:45.000000000 +0000
@@ -25,6 +25,8 @@
 02111-1307, USA. */
 /*@1@*/
 
+#include 
+
 #include "itsrccl.h"
 
 #include "clkcl.h"
@@ -72,7 +74,7 @@
 {
   int i;
   chars s("tim");
-  s.append("%d", id);
+  s.appendf("%d", id);
   set_name(s);
   id_string= strdup(s);
   cl_hw::init();
@@ -109,14 +111,14 @@
   return 0;
 }
 
-char *
+const char *
 cl_tim::cfg_help(t_addr addr)
 {
   switch (addr)
     {
-    case stm8_tim_on: return (char*)"Turn simulation of timer on/off (bool, RW)";
+    case stm8_tim_on: return "Turn simulation of timer on/off (bool, RW)";
     }
-  return (char*)"Not used";
+  return "Not used";
 }
 
 int
@@ -161,7 +163,7 @@
   regs[idx.arrl]->set(0xff);
 
   update_event();
-  regs[idx.sr1]->set_bit0(uif);
+  regs[idx.sr1]->set(regs[idx.sr1]->get() & ~uif);
 }
 
 void
@@ -195,7 +197,7 @@
   a-= base;
 
   if (a == idx.pscrl)
-    v= prescaler_preload && 0xff;
+    v= prescaler_preload & 0xff;
   else if (a == idx.pscrh)
     v= (prescaler_preload >> 8) & 0xff;
     
@@ -374,7 +376,7 @@
   u8_t c1= regs[idx.cr1]->get();
 
   if (c1 & opm)
-    regs[idx.cr1]->set_bit0(cen);
+    regs[idx.cr1]->set(regs[idx.cr1]->get() & ~cen);
   else
     {
       if (get_dir())
@@ -389,7 +391,7 @@
 	  set_counter(ar);
 	}
     }
-  regs[idx.sr1]->write_bit1(uif);
+  regs[idx.sr1]->write(regs[idx.sr1]->read() | uif);
 }
 
 // true: UP, false: down
@@ -443,7 +445,7 @@
 		 prescaler_cnt, prescaler_cnt,
 		 calc_prescaler(), calc_prescaler());
   con->dd_printf("arr= 0x%04x %d\n", get_arr(), get_arr());
-  print_cfg_info(con);
+  //print_cfg_info(con);
 }
 
 
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/timercl.h sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/timercl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/timercl.h	2019-04-02 10:46:33.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/timercl.h	2021-10-29 17:39:15.000000000 +0000
@@ -42,7 +42,7 @@
  protected:
   struct
   {
-    int
+    unsigned int
     // register indexes
     cr1, // control 1
       cr2, // control 2 (used in Master/Slave timers only, all except SAF 235)
@@ -102,8 +102,8 @@
  public:
   cl_tim(class cl_uc *auc, int aid, t_addr abase);
   virtual int init(void);
-  virtual int cfg_size(void) { return stm8_tim_nuof_cfg; }
-  virtual char *cfg_help(t_addr addr);
+  virtual unsigned int cfg_size(void) { return stm8_tim_nuof_cfg; }
+  virtual const char *cfg_help(t_addr addr);
  
   virtual int tick(int cycles);
   virtual void reset(void);
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/uid.cc sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/uid.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/stm8.src/uid.cc	2019-07-02 08:44:01.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stm8.src/uid.cc	2021-04-01 17:52:48.000000000 +0000
@@ -67,55 +67,28 @@
 cl_uid::read(class cl_memory_cell *cell)
 {
   t_mem v= cell->get();
-  //t_addr a;
   
   if (conf(cell, NULL))
     return v;
-  /*
-  if (!uc->rom->is_owned(cell, &a))
-    return v;
-  if ((a < base) ||
-      (a >= base+12))
-    return v;
-  a-= base;
 
-  cell->set(v= uid[a]);
-  */
   return v;
 }
 
 void
 cl_uid::write(class cl_memory_cell *cell, t_mem *val)
 {
-  //t_addr a;
-
   if (conf(cell, val))
     return;
-  /*
-  if (!uc->rom->is_owned(cell, &a))
-    return;  
-  if ((a < base) ||
-      (a >= base+12))
-    return;
-  a-= base;
-  *val= uid[a];
-  */
 }
 
 void
 cl_uid::print_info(class cl_console_base *con)
 {
-  /*
-  con->dd_printf("base= 0x%04x\n", base);
-  con->dd_printf("end = 0x%04x\n", base+12);
-  con->dd_printf("uid =");
-  int i;
-  for (i= 0; i < 12; i++)
-    con->dd_printf(" %02x", uc->rom->get(base+i));
+  for (t_addr i = 0; i < 12; i++)
+    con->dd_cprintf("dump_number", "%02x ", uc->rom->get(base+i));
   con->dd_printf("\n");
-  */
-  uc->rom->dump(base, base+12, 16, con/*->get_fout()*/);
-  print_cfg_info(con);
+
+  //print_cfg_info(con);
 }
 
 
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/stypes.h sdcc-4.2.0+dfsg/sim/ucsim/stypes.h
--- sdcc-4.0.0+dfsg/sim/ucsim/stypes.h	2019-04-16 10:04:43.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/stypes.h	2022-01-27 21:35:29.000000000 +0000
@@ -30,6 +30,13 @@
 
 #include "ddconfig.h"
 
+#ifdef HAVE_INTTYPES_H
+#include 
+#endif
+#ifdef HAVE_STDINT_H
+#include 
+#endif
+
 //typedef int8_t TYPE_BYTE;
 //typedef uint8_t TYPE_UBYTE;
 //typedef int16_t TYPE_WORD;
@@ -50,7 +57,7 @@
 typedef   signed TYPE_QWORD i64_t;
 typedef unsigned TYPE_QWORD u64_t;
 
-typedef i64_t		t_addr;		/* 64 bit max */
+typedef i64_t		t_addr;		/* 32 bit max */
 typedef u32_t		t_mem;		/* 32 bit max */
 typedef i32_t		t_smem;		/* signed 32 bit memory */
 
@@ -89,14 +96,15 @@
   err_warning  = 0x04
 };
 
-// table of dissassembled instructions
+// table of disassembled instructions
 struct dis_entry
 {
   /*uint64_t*/long long code, mask; // max 8 byte of code
   char  branch;
-  uchar length;
+  i8_t length;
   const char *mnemonic;
   bool is_call;
+  uchar ticks;
 };
 
 // table entry of SFR and BIT names
@@ -141,7 +149,14 @@
   CPU_R2K       = 0x0008,
   CPU_R3KA      = 0x0010,
   CPU_EZ80	= 0x0020,
-  CPU_ALL_Z80   = (CPU_Z80|CPU_Z180|CPU_R2K|CPU_LR35902|CPU_R3KA|CPU_EZ80),
+  CPU_Z80N      = 0x0040,
+  CPU_GB80      = 0x0080,
+  CPU_R3K	= 0x0100,
+  CPU_R4K	= 0x0200,
+  CPU_R5K	= 0x0400,
+  CPU_R6K	= 0x0800,
+  CPU_ALL_Z80   = (CPU_Z80|CPU_Z180|CPU_R2K|CPU_LR35902|CPU_R3KA|CPU_EZ80|
+		   CPU_Z80N|CPU_GB80),
 
   CPU_XA	= 0x0001,
   CPU_ALL_XA	= (CPU_XA),
@@ -150,6 +165,14 @@
   CPU_HCS08     = 0x0002,
   CPU_ALL_HC08  = (CPU_HC08|CPU_HCS08),
 
+  CPU_HC11      = 0x0004,
+  CPU_HC12      = 0x0008,
+  CPU_ALL_HC12  = (CPU_HC11|CPU_HC12),
+  
+  CPU_PBLAZE_3	= 0x0001,
+  CPU_PBLAZE_6	= 0x0002,
+  CPU_ALL_PBLAZE= (CPU_PBLAZE_3|CPU_PBLAZE_6),
+
   CPU_STM8S		= 0x0001,		// S and AF family
   CPU_STM8AF		= 0x0001,
   CPU_STM8SAF		= 0x0001,
@@ -217,6 +240,20 @@
   CPU_ST7       = 0x0001,
   CPU_ALL_ST7   = (CPU_ST7),
 
+  // MOS6502 and variants
+  CPU_6502	= 0x0001,	// NMOS
+  CPU_6502C	= 0x0002,	// 6502 + HALT pin
+  CPU_6510	= 0x0004,	// 6502 + integrated port
+  CPU_8500	= 0x0008,	// 6510 CMOS
+  CPU_8502	= 0x0010,	// 8500 2 MHz
+  CPU_7501	= 0x0020,	// 6502 HMOS-1
+  CPU_8501	= 0x0040,	// 6502 HMOS-2
+
+  // 6502 based, but not 100% compatible
+  CPU_65C02	= 0x0100,	// extended inst.set
+  CPU_65SC02	= 0x0200,      	// 65C02 variant, different inst.set
+  CPU_65CE02	= 0x0400,	// extension of 65C02
+  
   // technology
   CPU_CMOS	= 0x0001,
   CPU_HMOS	= 0x0002,
@@ -245,13 +282,16 @@
   MEM_SFR,
   MEM_DUMMY,
   MEM_IXRAM,
+  MEM_STACK,
   MEM_TYPES
 };
 
-#define MEM_SFR_ID	cchars("sfr")
-#define MEM_XRAM_ID	cchars("xram")
-#define MEM_IXRAM_ID	cchars("ixram")
-#define MEM_IRAM_ID	cchars("iram")
+#define MEM_SFR_ID	"sfr"
+#define MEM_XRAM_ID	"xram"
+#define MEM_IXRAM_ID	"ixram"
+#define MEM_IRAM_ID	"iram"
+#define MEM_STACK_ID	"stack"
+#define MEM_ROM_ID	"rom"
 
 // States of simulator
 enum sim_state {
@@ -272,19 +312,22 @@
   resGO		= 0,	/* OK, go on */
   resWDTRESET	= 1,	/* Reseted by WDT */
   resINTERRUPT	= 2,	/* Interrupt accepted */
-  resSTOP	= 100,	/* Stop if result greather then this */
+  resSTOP	= 100,	/* Stop if result greater then this */
   resHALT	= 101,	/* Serious error, halt CPU */
   resINV_ADDR	= 102,	/* Invalid indirect address */
   resSTACK_OV	= 103,	/* Stack overflow */
   resBREAKPOINT	= 104,	/* Fetch Breakpoint */
   resUSER	= 105,	/* Stopped by user */
   resINV_INST	= 106,	/* Invalid instruction */
+  resINST_INV	= 106,	/* Invalid instruction */
+  resINV	= 106,	/* Invalid instruction */
   resBITADDR	= 107,	/* Bit address is uninterpretable */
   resERROR	= 108,	/* Error happened during instruction exec */
   resSTEP	= 109,	/* Step command done, no more exex needed */
   resSIMIF	= 110,	/* Stopped by simulated prog itself through sim interface */
-  resNOT_DONE	= 111,	/* Intruction has not simulated */
+  resNOT_DONE	= 111,	/* Instruction has not simulated */
   resEVENTBREAK = 112,  /* Event breakpoint */
+  resSELFJUMP	= 113,  /* Jump to itself */
 };
   
 #define BIT_MASK(bitaddr) (1 << (bitaddr & 0x07))
@@ -320,7 +363,7 @@
 
 /* Interrupt levels */
 enum intr_levels {
-//IT_NO		= -1, /* not in interroupt service */
+//IT_NO		= -1, /* not in interrupt service */
   IT_LOW	= 1, /* low level interrupt service */
   IT_HIGH	= 2 /* service of high priority interrupt */
 };
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/test/Makefile sdcc-4.2.0+dfsg/sim/ucsim/test/Makefile
--- sdcc-4.0.0+dfsg/sim/ucsim/test/Makefile	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/test/Makefile	2020-03-27 20:18:53.000000000 +0000
@@ -0,0 +1,15 @@
+PROJECTS	= t1 stck_ovf
+
+.PHONY: projects $(PROJECTS)
+
+projects: $(PROJECTS)
+
+$(PROJECTS):
+	$(MAKE) MAIN=$@ -f sdcc.mk
+
+clean:
+	for p in $(PROJECTS); do \
+		$(MAKE) MAIN=$$p -f sdcc.mk clean ;\
+		rm -rf $$p*.hex ;\
+		rm -rf $$p*.cdb ;\
+	done
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/test/sdcc.mk sdcc-4.2.0+dfsg/sim/ucsim/test/sdcc.mk
--- sdcc-4.0.0+dfsg/sim/ucsim/test/sdcc.mk	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/test/sdcc.mk	2020-03-27 20:18:53.000000000 +0000
@@ -0,0 +1,67 @@
+VPATH		= ..
+
+vpath		%.mk $(VPATH)
+
+CPPFLAGS	=
+CFLAGS		= --debug
+LDFLAGS		=
+LIBS		=
+
+-include	$(MAIN).mk
+
+TARGETS		?= mcs51
+
+CC		= sdcc -m$(CPU) --std-c99 --out-fmt-ihx
+
+ALL		= $(MAIN) $(OTHERS)
+
+OBJECTS		= $(MAIN).rel $(OTHERS:=.rel)
+
+CPPFLAGS	= -I$(VPATH)
+
+.SUFFIXES: .rel .ihx .hex
+
+.PHONY: $(TARGETS)
+
+all: $(TARGETS)
+
+$(TARGETS):
+	test -d $@ || mkdir $@
+	echo "Compiling $@..."
+	$(MAKE) -C $@ CPU=$@ REAL=yes MAIN=$(MAIN) -I$(VPATH) -f$(VPATH)/sdcc.mk compile copy_result
+	echo "Done $@"
+
+copy_result: $(VPATH)/$(MAIN)_$(CPU).hex $(VPATH)/$(MAIN)_$(CPU).cdb
+
+$(VPATH)/$(MAIN)_$(CPU).hex: $(MAIN).hex
+	cp $< $@
+
+$(VPATH)/$(MAIN)_$(CPU).cdb: $(MAIN).cdb
+	cp $(MAIN).cdb $@
+
+compile: dep $(MAIN).hex
+
+.c.rel:
+	$(CC) $(CPPFLAGS) $(CFLAGS) -o $@ -c $<
+
+.ihx.hex:
+	packihx $< >$@
+
+$(MAIN).ihx: $(OBJECTS)
+	$(CC) $(CFLAGS) $(LDFLAAGS) $(OBJECTS) -o $@
+
+$(MAIN).cdb: $(MAIN).hex
+
+dep: $(MAIN).dep
+
+$(MAIN).dep: $(addprefix ../,$(OBJECTS:.rel=.c)) ../*.h
+	for c in $(addprefix ../,$(OBJECTS:.rel=.c)); do \
+		$(CC) -MM $(CPPFLAGS) $$c >>$@; \
+	done
+
+clean:
+	rm -rf $(TARGETS)
+
+ifeq ($(REAL),yes)
+include $(MAIN).dep
+endif
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/test/stck_ovf.c sdcc-4.2.0+dfsg/sim/ucsim/test/stck_ovf.c
--- sdcc-4.0.0+dfsg/sim/ucsim/test/stck_ovf.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/test/stck_ovf.c	2020-03-27 20:18:53.000000000 +0000
@@ -0,0 +1,12 @@
+int x;
+
+int f(int i)
+{
+  return f(i+1);
+}
+
+void main(void)
+{
+  x= 1;
+  f(x);
+}
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/test/stck_ovf.mk sdcc-4.2.0+dfsg/sim/ucsim/test/stck_ovf.mk
--- sdcc-4.0.0+dfsg/sim/ucsim/test/stck_ovf.mk	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/test/stck_ovf.mk	2020-03-27 20:18:53.000000000 +0000
@@ -0,0 +1 @@
+TARGETS		= mcs51 stm8 z80 hc08 tlcs90
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/test/t1.c sdcc-4.2.0+dfsg/sim/ucsim/test/t1.c
--- sdcc-4.0.0+dfsg/sim/ucsim/test/t1.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/test/t1.c	2020-03-27 20:18:53.000000000 +0000
@@ -0,0 +1,5 @@
+void
+main(void)
+{
+  for (;;) {}
+}
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/test/t1.mk sdcc-4.2.0+dfsg/sim/ucsim/test/t1.mk
--- sdcc-4.0.0+dfsg/sim/ucsim/test/t1.mk	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/test/t1.mk	2020-03-27 20:18:53.000000000 +0000
@@ -0,0 +1,5 @@
+TARGETS		= mcs51 \
+		hc08 s08 \
+		z80 z180 r2k r3ka tlcs90 ez80_z80 \
+		stm8 \
+		pdk14 pdk15
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/test-lib.mk sdcc-4.2.0+dfsg/sim/ucsim/test-lib.mk
--- sdcc-4.0.0+dfsg/sim/ucsim/test-lib.mk	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/test-lib.mk	2022-02-08 21:21:05.000000000 +0000
@@ -0,0 +1,131 @@
+# Work for individual tests is not parallelized although tests
+# themselves may be run in parallel.
+.NOTPARALLEL:
+
+VPATH := $(srcdir)
+
+# Include any target specifics.
+-include $(srcdir)/../test-conf.mk
+
+# Naming and target options are inconsistent so nearly all simulators
+# are going to have to define things in *.src/test-conf.mk some and
+# individual tests are likely to have to override on a per-target
+# basis using:
+#     target: CC=... SDAS=... SDLD=...
+#     target: prereqs
+#             recipe
+TARGET ?= $(patsubst s%,%,$(notdir $(SIM)))
+
+CC ?= sdcc -m$(TARGET)
+PACKIHX ?= packihx
+AS ?= sdas$(TARGET)
+ASFLAGS ?= -plosgffw
+LD ?= sdld$(TARGET)
+LDFLAGS ?=
+
+
+# When to colourize the diff output. Unless otherwise overridden we use
+# "auto" normally but "always" if output is being collected because make
+# is running parallel jobs.
+DIFF_COLOUR ?= $(if $(findstring --jobserver, $(MAKEFLAGS)),always,auto)
+
+# Things that are expected to change are elided in the output. We don't
+# care when comparing to baselines and we don't want to have to deal with
+# these changes when merging or rebasing.
+# N.B. These are sed arguments using extended regexps (sed -E)
+ELIDE += -e 's/^(uCsim )[^,]*(, Copyright \(C\) )[[:digit:]]+(-[[:digit:]]+)?/\1[ELIDED]\2[ELIDED]/'
+ELIDE += -e 's/^(ucsim version ).*/\1[ELIDED]/'
+ELIDE += -e 's/^(Loading from ).*/\1[ELIDED]/'
+ELIDE += -e 's/( words read from ).*/\1[ELIDED]/'
+ELIDE += -e 's/( File: ).*/\1[ELIDED]/'
+ELIDE += -e 's/^(Simulated [[:digit:]]+ ticks ).*/\1[ELIDED]/'
+ELIDE += -e 's/^(Host usage: ).*/\1[ELIDED]/'
+ELIDE += -e 's/([[:upper:]][[:alpha:]]{2} [[:upper:]][[:alpha:]]{2} .[[:digit:]] [[:digit:]]{2}:[[:digit:]]{2}:[[:digit:]]{2} [[:digit:]]{4})/[ELIDED]/'
+
+
+# $(call run-sim,)
+# Prerequisites of the form %.cmd are passed as command scripts
+# using -e immediately after any args specified.
+# Prerequisites of the form %.ihx are given as image files to load.
+# Other prerequisites are ignored.
+# If there are no %.cmd prequisites and -e does not appear anywhere
+# in the sim args "-e run" is passed to the simulator.
+define run-sim =
+	-$(SIM) -q -R 0 $(SIM_ARGS) $(1) \
+		$(if $(filter %.cmd, $+), \
+			$(foreach file, $(filter %.cmd, $+), -e 'exec "$(file)"'), \
+			$(if $(findstring -e, $(1)), , -g)) \
+		$(filter %.ihx, $+) \
+		2>&1 < /dev/null \
+		| sed -E $(ELIDE) \
+		> 'out/$@'; \
+	for file in out/*.vcd; do [ -r "$$file" ] && sed -E -i $(ELIDE) "$$file"; done
+endef
+
+
+.PHONY:	all clean _diff_to_baseline _log_test _silent
+
+# silent is used to suppress "nothing to do" messages.
+_silent:
+	@echo -n
+
+# A test produces one or more outputs which are then diff'd against
+# the baseline saved in the source tree.
+all:	_log_test out $(OUTPUTS) _diff_to_baseline
+
+_log_test:
+	@echo 'TEST $(srcdir)'
+
+out:
+	mkdir '$@'
+
+# Outputs must, at least, be up to date with respect to the baseline
+# output (if it exists), the main test's Makefile, test-lib.mk and the
+# simulator being tested. Other dependencies and the recipe used for
+# the test are in the main test's Makefile.
+.PHONY: $(patsubst %,baseline/%,$(OUTPUTS))
+$(OUTPUTS): %: baseline/% Makefile $(srcdir)/../../../test-lib.mk $(SIM)
+
+# Compare the complete output with the saved baseline. If there are
+# differences there is no need to report fail (the diff output is
+# sufficient) but hide the error to keep make quiet and allow other
+# tests to go ahead.
+_diff_to_baseline:
+	diff -urN --color='$(DIFF_COLOUR)' \
+		$(DIFF_OPTS) \
+		'$(srcdir)/baseline' 'out' \
+	|| true
+
+clean:	| _silent
+
+
+MAKEDEPEND = $(CC) -MM $(CPPFLAGS) $< > $*.d.tmp
+
+POSTCOMPILE = cp $*.d.tmp $*.d \
+	&& while read line; do \
+		for file in $${line\#*:}; do \
+			echo "$$file:"; \
+		done; \
+	done < $*.d.tmp >> $*.d \
+	&& rm -f $*.d.tmp
+
+
+%.hex:	%.ihx
+	$(PACKIHX) '$<' >'$@'
+
+# Build rules assuming an sdcc tool-chain. Override in per-target
+# test-conf.mk to use something else. Ideally pre-build tests and
+# ship the .ihx - we are NOT testing tool-chains!
+%.ihx:	%.c
+	$(MAKEDEPEND)
+	$(CC) $(CPPFLAGS) $(CFLAGS) $(LDFLAGS) --out-fmt-ihx -o '$@' '$<'
+	$(POSTCOMPILE)
+
+%.rel:	%.asm
+	$(AS) $(ASFLAGS) '$@' '$<'
+
+%.ihx:	%.rel
+	$(LD) $(LINKFLAGS) -i '$@' '$<'
+
+
+include $(wildcard *.d)
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/test-target.mk sdcc-4.2.0+dfsg/sim/ucsim/test-target.mk
--- sdcc-4.0.0+dfsg/sim/ucsim/test-target.mk	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/test-target.mk	2022-01-11 11:48:55.000000000 +0000
@@ -0,0 +1,74 @@
+SHELL := /bin/sh
+VPATH := $(srcdir)
+
+# Prefer built versions of the compiler, assemblers etc. but use installed versions if necessary.
+export PATH := $(abs_top_builddir)/bin:$(PATH)
+
+# We ONLY test the simulator version just built, never something installed.
+SIM := $(basename $(notdir $(patsubst %/,%,$(dir $(srcdir)))))
+ifeq ($(SIM), sim)
+	# If we are testing the core simulator itself rather than a specific
+	# version then any simulator will do. As long as it's been built.
+	SIM := $(firstword \
+			$(foreach p, $(basename $(notdir $(sort $(wildcard $(abs_top_builddir)/*.src)))), \
+				$(wildcard $(abs_top_builddir)/$(p).src/s$(p)) $(wildcard $(abs_top_builddir)/$(p).src/$(p)) \
+			) \
+		)
+else
+ifeq ($(SIM), s51)
+	SIM := $(abs_top_builddir)/$(SIM).src/ucsim_51
+else
+	SIM := $(abs_top_builddir)/$(SIM).src/ucsim_$(SIM)
+endif
+endif
+
+
+TESTS := $(patsubst $(srcdir)/%/Makefile,%,$(wildcard $(srcdir)/*/Makefile))
+BASELINES := $(patsubst %,%-baseline,$(TESTS))
+CLEAN_TESTS := $(addprefix Makefile/,$(TESTS))
+
+
+.PHONY:	all always clean $(CLEAN_TESTS)
+
+all::		$(SIM) $(TESTS)
+
+# It is not our place to build the simulator.
+$(SIM):
+	@echo 'FAIL $(SIM) does not exist. Build it before trying to test it!'
+	@exit 1
+
+baseline:	$(BASELINES) always
+
+%-baseline:	% always
+	@echo 'BASELINE $(srcdir)/$<'
+	@test -d '$(srcdir)/$read(addr);
   u8_t dh= nas->read(addr+1);
@@ -669,7 +669,7 @@
   int oldc= (reg.raf.f & FLAG_C)?1:0;
   vc.rd+= 2;
   
-  return op_add_hl((t_mem)d + oldc);
+  return op_add_hl_v(d + oldc);
 }
 
 
@@ -704,7 +704,7 @@
 
 // SUB HL,16-bit
 u16_t
-cl_tlcs::op_sub_hl(t_mem val)
+cl_tlcs::op_sub_hl_v(t_mem val)
 {
   return op_sub16(reg.hl, val);
 }
@@ -712,7 +712,7 @@
 
 // SUB HL,mem
 u16_t
-cl_tlcs::op_sub_hl(t_addr addr)
+cl_tlcs::op_sub_hl_a(t_addr addr)
 {
   u8_t dl= nas->read(addr);
   u8_t dh= nas->read(addr+1);
@@ -725,7 +725,7 @@
 
 // SBC HL,16-bit
 u16_t
-cl_tlcs::op_sbc_hl(t_mem val)
+cl_tlcs::op_sbc_hl_v(t_mem val)
 {
   u16_t r;
 
@@ -761,20 +761,20 @@
 
 // SBC HL,mem
 u16_t
-cl_tlcs::op_sbc_hl(t_addr addr)
+cl_tlcs::op_sbc_hl_a(t_addr addr)
 {
   u8_t dl= nas->read(addr);
   u8_t dh= nas->read(addr+1);
   u16_t d= dh*256 + dl;
   vc.rd+= 2;
   
-  return op_sbc_hl((t_mem)d);
+  return op_sbc_hl_v(d);
 }
 
 
 // AND HL,16-bit
 u16_t
-cl_tlcs::op_and_hl(t_mem val)
+cl_tlcs::op_and_hl_v(t_mem val)
 {
   u16_t d= val;
   u16_t r;
@@ -794,20 +794,20 @@
 
 // AND HL,mem
 u16_t
-cl_tlcs::op_and_hl(t_addr addr)
+cl_tlcs::op_and_hl_a(t_addr addr)
 {
   u8_t dl= nas->read(addr);
   u8_t dh= nas->read(addr+1);
   u16_t d= dh*256 + dl;
   vc.rd+= 2;
   
-  return op_and_hl((t_mem)d);
+  return op_and_hl_v(d);
 }
 
 
 // XOR HL,16-bit
 u16_t
-cl_tlcs::op_xor_hl(t_mem val)
+cl_tlcs::op_xor_hl_v(t_mem val)
 {
   u16_t d= val;
   u16_t r;
@@ -826,20 +826,20 @@
 
 // XOR HL,mem
 u16_t
-cl_tlcs::op_xor_hl(t_addr addr)
+cl_tlcs::op_xor_hl_a(t_addr addr)
 {
   u8_t dl= nas->read(addr);
   u8_t dh= nas->read(addr+1);
   u16_t d= dh*256 + dl;
   vc.rd+= 2;
   
-  return op_xor_hl((t_mem)d);
+  return op_xor_hl_v(d);
 }
 
 
 // OR HL,16-bit
 u16_t
-cl_tlcs::op_or_hl(t_mem val)
+cl_tlcs::op_or_hl_v(t_mem val)
 {
   u16_t d= val;
   u16_t r;
@@ -858,14 +858,14 @@
 
 // OR HL,mem
 u16_t
-cl_tlcs::op_or_hl(t_addr addr)
+cl_tlcs::op_or_hl_a(t_addr addr)
 {
   u8_t dl= nas->read(addr);
   u8_t dh= nas->read(addr+1);
   u16_t d= dh*256 + dl;
   vc.rd+= 2;
   
-  return op_or_hl((t_mem)d);
+  return op_or_hl_v(d);
 }
 
 
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/tlcs.src/Makefile.in sdcc-4.2.0+dfsg/sim/ucsim/tlcs.src/Makefile.in
--- sdcc-4.0.0+dfsg/sim/ucsim/tlcs.src/Makefile.in	2018-12-18 09:27:50.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/tlcs.src/Makefile.in	2022-01-09 14:02:03.000000000 +0000
@@ -5,6 +5,9 @@
 #
 #
 
+# tool name
+TN		= tlcs
+
 STARTYEAR	= 2016
 
 SHELL		= /bin/sh
@@ -25,8 +28,8 @@
 CPPFLAGS        = @CPPFLAGS@ -I$(srcdir) -I$(top_srcdir) -I$(top_builddir) \
 		  -I$(top_srcdir)/cmd.src -I$(top_srcdir)/sim.src \
 		  -I$(top_srcdir)/gui.src
-CFLAGS          = @CFLAGS@ @WALL_FLAG@
-CXXFLAGS        = @CXXFLAGS@ @WALL_FLAG@
+CFLAGS          = @WALL_FLAG@ @CFLAGS@
+CXXFLAGS        = @WALL_FLAG@ @CXXFLAGS@
 LDFLAGS         = @LDFLAGS@
 PICOPT		= @PICOPT@
 SHAREDLIB	= @SHAREDLIB@
@@ -51,40 +54,53 @@
 VPATH           = @srcdir@
 
 OBJECTS_SHARED	= glob.o \
-		  simtlcs.o tlcs.o \
+		  sim$(TN).o $(TN).o \
 		  inst_block.o inst_cpu_others.o inst_rot_sh.o \
 		  inst_jump.o inst_move.o inst_arith.o inst_bit.o
-OBJECTS_EXE	= stlcs.o
+OBJECTS_EXE	= s$(TN).o
 OBJECTS		= $(OBJECTS_SHARED) $(OBJECTS_EXE)
 
+# short/long exe and lib name
+SEN		= s$(TN)$(EXEEXT)
+LEN		= ucsim_$(TN)$(EXEEXT)
+SONAME		= libucsim_$(TN).so
+
 enable_dlso	= @enable_dlso@
 dlso_ok		= @dlso_ok@
 
 
 # Compiling entire program or any subproject
 # ------------------------------------------
-all: checkconf otherlibs tlcs.src
+all: checkconf otherlibs $(TN).src
 
 
 # Compiling and installing everything and runing test
 # ---------------------------------------------------
-install: all installdirs
-	$(INSTALL) stlcs$(EXEEXT) $(DESTDIR)$(bindir)/`echo stlcs|sed '$(transform)'`$(EXEEXT)
-	$(STRIP) $(DESTDIR)$(bindir)/`echo stlcs|sed '$(transform)'`$(EXEEXT)
+install: all installdirs install_shared_lib
+	$(INSTALL) $(SEN) $(DESTDIR)$(bindir)/$(SEN)
+	$(STRIP) $(DESTDIR)$(bindir)/$(SEN)
+	$(INSTALL) $(LEN) $(DESTDIR)$(bindir)/$(LEN)
+	$(STRIP) $(DESTDIR)$(bindir)/$(LEN)
 
 
 # Deleting all the installed files
 # --------------------------------
 uninstall:
-	rm -f $(DESTDIR)$(bindir)/stlcs
-	rm -f $(DESTDIR)$(bindir)/`echo stlcs|sed '$(transform)'`$(EXEEXT)
+	rm -f $(DESTDIR)$(bindir)/$(SEN)
+	rm -f $(DESTDIR)$(bindir)/$(LEN)
+	rm -f $(DESTDIR)$(libdir)/$(SONAME)
 
 
 # Performing self-test
 # --------------------
 check: $(TEST_OBJ)
 
+.PHONY:	test baseline
 test:
+	@$(MAKE) --no-print-directory -C test
+
+baseline:
+	@$(MAKE) --no-print-directory -C test baseline
 
 
 # Performing installation test
@@ -110,20 +126,27 @@
 
 # My rules
 # --------
-tlcs.src: stlcs$(EXEEXT) shared_lib
+$(TN).src: $(SEN) $(LEN) shared_lib
 
-stlcs$(EXEEXT): $(OBJECTS) $(top_builddir)/libcmd.a $(top_builddir)/libguiucsim.a $(top_builddir)/libsim.a $(top_builddir)/libucsimutil.a
+$(SEN): $(OBJECTS) $(top_builddir)/libcmd.a $(top_builddir)/libguiucsim.a $(top_builddir)/libsim.a $(top_builddir)/libucsimutil.a
 	$(CXX) $(CXXFLAGS) $(LDFLAGS) $(OBJECTS) $(LIBS) -o $@
 
+$(LEN): $(SEN)
+	cp $< $@
+
 ifeq ($(dlso_ok),yes)
-shared_lib: $(top_builddir)/stlcs.so
+shared_lib: $(top_builddir)/$(SONAME)
+install_shared_lib: shared_lib
+	test -d $(DESTDIR)$(libdir) || $(INSTALL) -d $(DESTDIR)$(libdir)
+	$(INSTALL) $(top_builddir)/$(SONAME) $(DESTDIR)$(libdir)/$(SONAME)
 else
 shared_lib:
-	@$(top_srcdir)/mkecho $(top_builddir) "No TLCS shared lib made."
+	@$(top_srcdir)/mkecho $(top_builddir) "No $(TN) shared lib made."
 	@$(top_srcdir)/mkecho $(top_builddir) "(SHAREDLIB="$(SHAREDLIB)",dl_ok="$(dl_ok)",enable_dlso="$(enable_dlso)")"
+install_shared_lib:
 endif
 
-$(top_builddir)/stlcs.so: $(OBJECTS_SHARED)
+$(top_builddir)/$(SONAME): $(OBJECTS_SHARED)
 	$(CXX) -shared $(LDFLAGS) $(OBJECTS_SHARED) -o $@
 
 otherlibs: $(top_builddir)/libcmd.a $(top_builddir)/libguiucsim.a $(top_builddir)/libsim.a $(top_builddir)/libucsimutil.a
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/tlcs.src/simtlcs.cc sdcc-4.2.0+dfsg/sim/ucsim/tlcs.src/simtlcs.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/tlcs.src/simtlcs.cc	2018-12-18 09:27:50.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/tlcs.src/simtlcs.cc	2020-03-27 20:18:53.000000000 +0000
@@ -26,7 +26,7 @@
 /*@1@*/
 
 // sim.src
-#include "appcl.h"
+//#include "appcl.h"
 
 // local
 #include "simtlcscl.h"
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/tlcs.src/stlcs.cc sdcc-4.2.0+dfsg/sim/ucsim/tlcs.src/stlcs.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/tlcs.src/stlcs.cc	2018-12-18 09:27:50.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/tlcs.src/stlcs.cc	2020-06-13 16:30:36.000000000 +0000
@@ -25,13 +25,13 @@
 02111-1307, USA. */
 /*@1@*/
 
-#include 
+//#include 
 
 // prj
 #include "globals.h"
 
 // sim.src
-#include "appcl.h"
+//#include "appcl.h"
 
 // local
 #include "simtlcscl.h"
@@ -43,6 +43,7 @@
   class cl_sim *sim;
   
   application= new cl_app();
+  application->set_name("stlcs");
   application->init(argc, argv);
   sim= new cl_simtlcs(application);
   if (sim->init())
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/tlcs.src/test/b2385.c sdcc-4.2.0+dfsg/sim/ucsim/tlcs.src/test/b2385.c
--- sdcc-4.0.0+dfsg/sim/ucsim/tlcs.src/test/b2385.c	2016-07-26 21:10:26.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/tlcs.src/test/b2385.c	1970-01-01 00:00:00.000000000 +0000
@@ -1,18 +0,0 @@
-struct ts { int a; };
-
-typedef struct ts *pts;
-
-pts s;
-
-int test(void)
-{
-  pts ps;
-  ps= s;
-  //return ps->a; // GOOD
-  return (ps= s)->a; // FAIL
-}
-
-void main(void)
-{
-  test();
-}
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/tlcs.src/test/b2385.mk sdcc-4.2.0+dfsg/sim/ucsim/tlcs.src/test/b2385.mk
--- sdcc-4.0.0+dfsg/sim/ucsim/tlcs.src/test/b2385.mk	2016-07-26 21:10:26.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/tlcs.src/test/b2385.mk	1970-01-01 00:00:00.000000000 +0000
@@ -1,3 +0,0 @@
-MAIN		= b2385
-
-include sdcc.mk
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/tlcs.src/test/clean.mk sdcc-4.2.0+dfsg/sim/ucsim/tlcs.src/test/clean.mk
--- sdcc-4.0.0+dfsg/sim/ucsim/tlcs.src/test/clean.mk	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/tlcs.src/test/clean.mk	2021-04-01 17:52:48.000000000 +0000
@@ -0,0 +1,5 @@
+clean:
+
+distclean:
+	rm -f Makefile
+	find . -type d -name out -exec rm -rf {} \;
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/tlcs.src/test/conf.cmd sdcc-4.2.0+dfsg/sim/ucsim/tlcs.src/test/conf.cmd
--- sdcc-4.0.0+dfsg/sim/ucsim/tlcs.src/test/conf.cmd	2016-07-26 21:10:26.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/tlcs.src/test/conf.cmd	1970-01-01 00:00:00.000000000 +0000
@@ -1 +0,0 @@
-set hw simif nas 0x7fff
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/tlcs.src/test/config/baseline/TLCS sdcc-4.2.0+dfsg/sim/ucsim/tlcs.src/test/config/baseline/TLCS
--- sdcc-4.0.0+dfsg/sim/ucsim/tlcs.src/test/config/baseline/TLCS	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/tlcs.src/test/config/baseline/TLCS	2022-02-08 21:21:05.000000000 +0000
@@ -0,0 +1,31 @@
+uCsim, Copyright (C)  Daniel Drotos.
+uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+This is free software, and you are welcome to redistribute it
+under certain conditions; type `show c' for details.
+Type of microcontroller: unspecified TLCS
+Controller has 4 hardware element(s).
+   on cpu[0]
+   on simif[0]
+  off vcd[0]
+   on dreg[0]
+SZIHXVNC  Flags= 0x00   0 .  A= 0x00   0 .
+00000000
+BC= 0x0000 [BC]= 08   8 .  DE= 0x0000 [DE]= 08   8 .  HL= 0x0000 [HL]= 08   8 .
+IX= 0x0000 [IX]= 08   8 .  IY= 0x0000 [IY]= 08   8 .  SP= 0x0000 [SP]= 08   8 .
+SP limit= 0xf000
+0x0000  ? 08                EX DE,HL[0K
+Memory chips:
+  0x000000-0x0000ff      256 variable_storage (32,%08x,0x%02lx)
+  0x000000-0x00ffff    65536 nas_chip (8,%02x,0x%04lx)
+Address spaces:
+  0x000000-0x00000f       16 regs8 (8,%02x,0x%01lx)
+  0x000000-0x00000a       11 regs16 (16,%04x,0x%01lx)
+  0x000000-0x0000ff      256 variables (32,%08x,0x%02lx)
+  0x000000-0x00ffff    65536 nas (8,%02x,0x%04lx)
+  0x000000-0x00ffff    65536 xas (8,%02x,0x%04lx)
+  0x000000-0x00ffff    65536 yas (8,%02x,0x%04lx)
+Address decoders:
+  variables 0x00 0xff -> variable_storage 0x00 activated
+  nas 0x0000 0xffff -> nas_chip 0x0000 activated
+  xas 0x0000 0xffff -> nas_chip 0x0000 activated
+  yas 0x0000 0xffff -> nas_chip 0x0000 activated
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/tlcs.src/test/config/Makefile sdcc-4.2.0+dfsg/sim/ucsim/tlcs.src/test/config/Makefile
--- sdcc-4.0.0+dfsg/sim/ucsim/tlcs.src/test/config/Makefile	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/tlcs.src/test/config/Makefile	2021-03-21 12:01:19.000000000 +0000
@@ -0,0 +1,8 @@
+OUTPUTS = TLCS
+
+
+$(OUTPUTS):
+	$(call run-sim, -e 'conf; info reg; info mem')
+
+
+include test-lib.mk
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/tlcs.src/test/Makefile sdcc-4.2.0+dfsg/sim/ucsim/tlcs.src/test/Makefile
--- sdcc-4.0.0+dfsg/sim/ucsim/tlcs.src/test/Makefile	2016-07-26 21:10:26.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/tlcs.src/test/Makefile	1970-01-01 00:00:00.000000000 +0000
@@ -1,11 +0,0 @@
-PRJ		= t0 t1 t2 t3 b2385
-
-all:
-	for p in $(PRJ); do \
-		$(MAKE) -f $$p.mk ;\
-	done
-
-clean:
-	for p in $(PRJ); do \
-		$(MAKE) -f $$p.mk clean ;\
-	done
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/tlcs.src/test/Makefile.in sdcc-4.2.0+dfsg/sim/ucsim/tlcs.src/test/Makefile.in
--- sdcc-4.0.0+dfsg/sim/ucsim/tlcs.src/test/Makefile.in	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/tlcs.src/test/Makefile.in	2021-03-28 10:28:14.000000000 +0000
@@ -0,0 +1,9 @@
+# @configure_input@
+
+srcdir           = @abs_srcdir@
+
+abs_top_builddir = @abs_top_builddir@
+abs_top_srcdir   = @abs_top_srcdir@
+
+
+include $(abs_top_srcdir)/test-target.mk
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/tlcs.src/test/run.cmd sdcc-4.2.0+dfsg/sim/ucsim/tlcs.src/test/run.cmd
--- sdcc-4.0.0+dfsg/sim/ucsim/tlcs.src/test/run.cmd	2016-07-26 21:10:26.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/tlcs.src/test/run.cmd	1970-01-01 00:00:00.000000000 +0000
@@ -1,2 +0,0 @@
-run
-state
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/tlcs.src/test/run.sh sdcc-4.2.0+dfsg/sim/ucsim/tlcs.src/test/run.sh
--- sdcc-4.0.0+dfsg/sim/ucsim/tlcs.src/test/run.sh	2016-12-12 13:18:23.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/tlcs.src/test/run.sh	1970-01-01 00:00:00.000000000 +0000
@@ -1,7 +0,0 @@
-PRJ=$1
-
-if [ -z "$PRJ" ]; then
-   PRJ=t1
-fi
-
-../stlcs -C conf.cmd ${PRJ}.ihx $(MAIN).dep
-	@for c in $(OBJECTS:.rel=.c); do \
-		$(CC) -MM $(CPPFALGS) $$c >>$(MAIN).dep ;\
-	done
-
-include $(MAIN).dep
-
-$(MAIN).ihx: $(OBJECTS)
-	$(CC) $(CFLAGS) $(LDFLAGS) $(OBJECTS) -o $@
-
-.SUFFIXES: .rel .ihx .hex
-
-.c.rel:
-	$(CC) -c $(CPPFLAGS) $(CFLAGS) $<
-
-.ihx.hex:
-	packihx $< >$@
-
-clean:
-	rm -f $(ALL:=.rel) $(ALL:=.asm) $(ALL:=.lst) $(ALL:=.rst) $(ALL:=.sym) $(ALL:=.adb)
-	rm -f $(MAIN).ihx $(MAIN).hex $(MAIN).lk $(MAIN).map $(MAIN).mem $(MAIN).cdb $(MAIN).omf $(MAIN).noi
-	rm -f *~
-	rm -f $(MAIN).dep
-
-
-# End of sdcc.mk
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/tlcs.src/test/symdis/baseline/stdout sdcc-4.2.0+dfsg/sim/ucsim/tlcs.src/test/symdis/baseline/stdout
--- sdcc-4.0.0+dfsg/sim/ucsim/tlcs.src/test/symdis/baseline/stdout	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/tlcs.src/test/symdis/baseline/stdout	2022-02-08 21:21:05.000000000 +0000
@@ -0,0 +1,26 @@
+uCsim, Copyright (C)  Daniel Drotos.
+uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+This is free software, and you are welcome to redistribute it
+under certain conditions; type `show c' for details.
+var _main nas[0x020b]
+dc 0x0100 0x0121
+0x0100  ? 3e a0 ff          LD SP,0xffa0[0K
+0x0103  ? 3a 00 80          LD HL,0x8000[0K
+0x0106  ? 36 00             LD A,00[0K
+0x0108  ? 1c 07 02          CALL 0x0207[0K
+0x010b  ? 7f c0 ff          CP HL,0xffc0[0K
+0x010e  ? c6 05             JR Z,0x0115[0K
+0x0110  ? ea 26             LD (HL),A[0K
+0x0112  ? 92                INC HL[0K
+0x0113  ? c8 f3             JR 0x0108[0K
+0x0115  ? 1c 07 02          CALL 0x0207[0K
+0x0118  ? 1c 07 02          CALL 0x0207[0K
+0x011b  ? 1c 0d 02          CALL 0x020d[0K
+0x011e  ? 1c 0b 02          CALL 0x020b <_main>[0K
+0x0121  ? 01                HALT[0K
+dc 0x0207 0x020c
+0x0207  ? 37 d3 4e          LD (0xffd3),4e[0K
+0x020a  ? 1e                RET[0K
+
+0x020b    <_main>:
+0x020b  ? c8 fe             JR 0x020b <_main>[0K
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/tlcs.src/test/symdis/Makefile sdcc-4.2.0+dfsg/sim/ucsim/tlcs.src/test/symdis/Makefile
--- sdcc-4.0.0+dfsg/sim/ucsim/tlcs.src/test/symdis/Makefile	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/tlcs.src/test/symdis/Makefile	2021-05-07 16:21:16.000000000 +0000
@@ -0,0 +1,15 @@
+OUTPUTS = stdout
+
+
+# Ignore changes in white space. The field widths for labels
+# depends on the length of the longest label. This will be
+# different for different simulators and should not be assumed
+# to be constant for any given simulator.
+DIFF_OPTS += -b
+
+
+stdout:	test.ihx test.cmd
+	$(call run-sim)
+
+
+include test-lib.mk
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/tlcs.src/test/symdis/test.c sdcc-4.2.0+dfsg/sim/ucsim/tlcs.src/test/symdis/test.c
--- sdcc-4.0.0+dfsg/sim/ucsim/tlcs.src/test/symdis/test.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/tlcs.src/test/symdis/test.c	2021-05-07 16:21:16.000000000 +0000
@@ -0,0 +1,4 @@
+int main(int argc, char *argv[])
+{
+	for (;;);
+}
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/tlcs.src/test/symdis/test.cmd sdcc-4.2.0+dfsg/sim/ucsim/tlcs.src/test/symdis/test.cmd
--- sdcc-4.0.0+dfsg/sim/ucsim/tlcs.src/test/symdis/test.cmd	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/tlcs.src/test/symdis/test.cmd	2021-05-18 07:55:03.000000000 +0000
@@ -0,0 +1,3 @@
+var _main nas[0x020b]
+dc 0x0100 0x0121
+dc 0x0207 0x020c
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/tlcs.src/test/symdis/test.ihx sdcc-4.2.0+dfsg/sim/ucsim/tlcs.src/test/symdis/test.ihx
--- sdcc-4.0.0+dfsg/sim/ucsim/tlcs.src/test/symdis/test.ihx	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/tlcs.src/test/symdis/test.ihx	2021-05-07 16:21:16.000000000 +0000
@@ -0,0 +1,11 @@
+:200000001A00010000000000000000000000000000000000000000000000000000000000C5
+:2000200000000000000000001F0000000000000000000000000000000000000000000000A1
+:200040001F0000000000000000000000000000000000000000000000000000000000000081
+:2000600000000000000000001F000000000000000000000000000000000000000000000061
+:01008000007F
+:200100003EA0FF3A008036001C07027FC0FFC605EA2692C8F31C07021C07021C0D021C0BEB
+:020120000201DA
+:0B02000037D20037D3B11E37D34E1E9B
+:11020D0038000020F966C6083900803A0D02FE591EE4
+:02020B00C8FE2B
+:00000001FF
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/tlcs.src/test/t0.c sdcc-4.2.0+dfsg/sim/ucsim/tlcs.src/test/t0.c
--- sdcc-4.0.0+dfsg/sim/ucsim/tlcs.src/test/t0.c	2016-07-26 21:10:26.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/tlcs.src/test/t0.c	1970-01-01 00:00:00.000000000 +0000
@@ -1,12 +0,0 @@
-static unsigned char * volatile sif= (unsigned char *)0xffff;
-
-void main(void)
-{
-  unsigned int i, j;
-
-  for (i=0; i<0x2233; i++)
-    j= i;
-  *sif= 's';
-  for (;;)
-    ;
-}
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/tlcs.src/test/t0.mk sdcc-4.2.0+dfsg/sim/ucsim/tlcs.src/test/t0.mk
--- sdcc-4.0.0+dfsg/sim/ucsim/tlcs.src/test/t0.mk	2016-07-26 21:10:26.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/tlcs.src/test/t0.mk	1970-01-01 00:00:00.000000000 +0000
@@ -1,3 +0,0 @@
-MAIN		= t0
-
-include sdcc.mk
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/tlcs.src/test/t1.c sdcc-4.2.0+dfsg/sim/ucsim/tlcs.src/test/t1.c
--- sdcc-4.0.0+dfsg/sim/ucsim/tlcs.src/test/t1.c	2016-07-26 21:10:26.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/tlcs.src/test/t1.c	1970-01-01 00:00:00.000000000 +0000
@@ -1,37 +0,0 @@
-static unsigned char * volatile sif= (unsigned char *)0x7fff;
-
-volatile unsigned char x;
-
-void
-putchar(unsigned char c)
-{
-  *sif= 'p';
-  *sif= c;
-}
-
-void
-prints(char *s)
-{
-  while (*s)
-    putchar(*s++);
-}
-
-void
-main(void)
-{
-  unsigned char i;
-  unsigned int j;
-
-  prints("Start.\n");
-  for (j= 0; j<41000; j++)
-    {
-      x= j;
-      i= j;
-      putchar('a');
-    }
-
-  prints("Done.\n");
-  *sif= 's';
-  for (;;)
-    ;
-}
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/tlcs.src/test/t1.mk sdcc-4.2.0+dfsg/sim/ucsim/tlcs.src/test/t1.mk
--- sdcc-4.0.0+dfsg/sim/ucsim/tlcs.src/test/t1.mk	2016-07-26 21:10:26.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/tlcs.src/test/t1.mk	1970-01-01 00:00:00.000000000 +0000
@@ -1,3 +0,0 @@
-MAIN		= t1
-
-include sdcc.mk
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/tlcs.src/test/t2.c sdcc-4.2.0+dfsg/sim/ucsim/tlcs.src/test/t2.c
--- sdcc-4.0.0+dfsg/sim/ucsim/tlcs.src/test/t2.c	2016-07-26 21:10:26.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/tlcs.src/test/t2.c	1970-01-01 00:00:00.000000000 +0000
@@ -1,36 +0,0 @@
-static unsigned char * volatile sif= (unsigned char *)0xffff;
-
-volatile unsigned char x;
-
-void
-putchar(unsigned char c)
-{
-  *sif= 'p';
-  *sif= c;
-}
-
-void
-prints(char *s)
-{
-  while (*s)
-    putchar(*s++);
-}
-
-void
-main(void)
-{
-  unsigned int i;
-  unsigned int j;
-
-  prints("Start.\n");
-  for (j= 0; j<200; j++)
-    {
-      for (i= 1000; i; i--)
-	putchar('a');
-    }
-
-  prints("Done.\n");
-  *sif= 's';
-  for (;;)
-    ;
-}
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/tlcs.src/test/t2.mk sdcc-4.2.0+dfsg/sim/ucsim/tlcs.src/test/t2.mk
--- sdcc-4.0.0+dfsg/sim/ucsim/tlcs.src/test/t2.mk	2016-07-26 21:10:26.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/tlcs.src/test/t2.mk	1970-01-01 00:00:00.000000000 +0000
@@ -1,3 +0,0 @@
-MAIN		= t2
-
-include sdcc.mk
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/tlcs.src/test/t3.c sdcc-4.2.0+dfsg/sim/ucsim/tlcs.src/test/t3.c
--- sdcc-4.0.0+dfsg/sim/ucsim/tlcs.src/test/t3.c	2016-07-26 21:10:26.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/tlcs.src/test/t3.c	1970-01-01 00:00:00.000000000 +0000
@@ -1,17 +0,0 @@
-const unsigned char a[2]= { 0x11, 0x22 };
-
-void __fail(char *s)
-{
-}
-
-#define ASSERT(_a)  ((_a) ? (void)0 : __fail ("Assertion failed", #_a, __FILE__, __LINE__))
-
-volatile unsigned char idx;
-
-void main(void)
-{
-  volatile unsigned char c;
-  idx= 1;
-  (a[idx]==0x22)?(void)0:__fail("s");
-  while (1) ;
-}
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/tlcs.src/test/t3.mk sdcc-4.2.0+dfsg/sim/ucsim/tlcs.src/test/t3.mk
--- sdcc-4.0.0+dfsg/sim/ucsim/tlcs.src/test/t3.mk	2016-07-26 21:10:26.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/tlcs.src/test/t3.mk	1970-01-01 00:00:00.000000000 +0000
@@ -1,3 +0,0 @@
-MAIN		= t3
-
-include sdcc.mk
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/tlcs.src/test/test-conf.mk sdcc-4.2.0+dfsg/sim/ucsim/tlcs.src/test/test-conf.mk
--- sdcc-4.0.0+dfsg/sim/ucsim/tlcs.src/test/test-conf.mk	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/tlcs.src/test/test-conf.mk	2021-03-21 12:01:19.000000000 +0000
@@ -0,0 +1,3 @@
+CC = sdcc -mtlcs90
+AS = sdastlcs90
+LD = sdldz80
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/tlcs.src/tlcs.cc sdcc-4.2.0+dfsg/sim/ucsim/tlcs.src/tlcs.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/tlcs.src/tlcs.cc	2019-05-06 09:55:43.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/tlcs.src/tlcs.cc	2021-10-29 17:39:15.000000000 +0000
@@ -25,20 +25,21 @@
 02111-1307, USA. */
 /*@1@*/
 
-#include "ddconfig.h"
+//#include "ddconfig.h"
 
 #include 
-#include 
+//#include 
 #include 
-#include "i_string.h"
+#include 
 
 // prj
-#include "pobjcl.h"
+//#include "pobjcl.h"
 
 // sim
-#include "simcl.h"
-#include "memcl.h"
-#include "stackcl.h"
+//#include "simcl.h"
+//#include "memcl.h"
+//#include "stackcl.h"
+#include "dregcl.h"
 
 // local
 #include "tlcscl.h"
@@ -96,91 +97,87 @@
 int
 cl_tlcs::init(void)
 {
-  class cl_var *v;
-
   cl_uc::init(); /* Memories now exist */
   //ram= address_space(MEM_IRAM_ID);
   //rom= address_space(MEM_ROM_ID);
-
+  sp_limit= 0xf000;
+  
   // zero out ram(this is assumed in regression tests)
   for (int i=0x8000; i<0x10000; i++) {
     nas->set((t_addr) i, 0);
   }
 
-  vars->add(v= new cl_var(cchars("A"), regs8, 0, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("F"), regs8, 1, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("B"), regs8, 2, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("C"), regs8, 3, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("D"), regs8, 4, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("E"), regs8, 5, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("H"), regs8, 6, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("L"), regs8, 7, ""));
-  v->init();
-
-  vars->add(v= new cl_var(cchars("ALT_A"), regs8, 8, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("ALT_F"), regs8, 9, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("ALT_B"), regs8, 10, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("ALT_C"), regs8, 11, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("ALT_D"), regs8, 12, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("ALT_E"), regs8, 13, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("ALT_H"), regs8, 14, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("ALT_L"), regs8, 15, ""));
-  v->init();
-
-  vars->add(v= new cl_var(cchars("AF"), regs16, 0, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("BC"), regs16, 1, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("DE"), regs16, 2, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("HL"), regs16, 3, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("IX"), regs16, 4, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("IY"), regs16, 5, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("SP"), regs16, 6, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("ALT_AF"), regs16, 7, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("ALT_BC"), regs16, 8, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("ALT_DE"), regs16, 9, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("ALT_HL"), regs16, 11, ""));
-  v->init();
+  vars->add("A", regs8, 0, 7, 0, "");
+  vars->add("F", regs8, 1, 7, 0, "");
+  vars->add("F_S", regs8, 1, 7, 7, "");
+  vars->add("F_Z", regs8, 1, 7, 7, "Zero");
+  vars->add("F_I", regs8, 1, 5, 5, "Interrupt Mask");
+  vars->add("F_H", regs8, 1, 4, 4, "Half Carry");
+  vars->add("F_X", regs8, 1, 3, 3, "");
+  vars->add("F_V", regs8, 1, 2, 2, "Overflow");
+  vars->add("F_N", regs8, 1, 1, 1, "Negative");
+  vars->add("F_C", regs8, 1, 0, 0, "Carry");
+  vars->add("B", regs8, 2, 7, 0, "");
+  vars->add("C", regs8, 3, 7, 0, "");
+  vars->add("D", regs8, 4, 7, 0, "");
+  vars->add("E", regs8, 5, 7, 0, "");
+  vars->add("H", regs8, 6, 7, 0, "");
+  vars->add("L", regs8, 7, 7, 0, "");
+
+  vars->add("ALT_A", regs8, 8, 7, 0, "");
+  vars->add("ALT_F", regs8, 9, 7, 0, "");
+  vars->add("ALT_F_S", regs8, 9, 7, 7, "");
+  vars->add("ALT_F_Z", regs8, 9, 7, 7, "Zero");
+  vars->add("ALT_F_I", regs8, 9, 5, 5, "Interrupt Mask");
+  vars->add("ALT_F_H", regs8, 9, 4, 4, "Half Carry");
+  vars->add("ALT_F_X", regs8, 9, 3, 3, "");
+  vars->add("ALT_F_V", regs8, 9, 2, 2, "Overflow");
+  vars->add("ALT_F_N", regs8, 9, 1, 1, "Negative");
+  vars->add("ALT_F_C", regs8, 9, 0, 0, "Carry");
+  vars->add("ALT_B", regs8, 10, 7, 0, "");
+  vars->add("ALT_C", regs8, 11, 7, 0, "");
+  vars->add("ALT_D", regs8, 12, 7, 0, "");
+  vars->add("ALT_E", regs8, 13, 7, 0, "");
+  vars->add("ALT_H", regs8, 14, 7, 0, "");
+  vars->add("ALT_L", regs8, 15, 7, 0, "");
+
+  vars->add("AF", regs16, 0, 15, 0, "");
+  vars->add("BC", regs16, 1, 15, 0, "");
+  vars->add("DE", regs16, 2, 15, 0, "");
+  vars->add("HL", regs16, 3, 15, 0, "");
+  vars->add("IX", regs16, 4, 15, 0, "");
+  vars->add("IY", regs16, 5, 15, 0, "");
+  vars->add("SP", regs16, 6, 15, 0, "");
+  vars->add("ALT_AF", regs16, 7, 15, 0, "");
+  vars->add("ALT_BC", regs16, 8, 15, 0, "");
+  vars->add("ALT_DE", regs16, 9, 15, 0, "");
+  vars->add("ALT_HL", regs16, 11, 15, 0, "");
 
   return(0);
 }
 
-char *
+const char *
 cl_tlcs::id_string(void)
 {
-  return((char*)"unspecified TLCS");
+  return("unspecified TLCS");
 }
 
 
 void
+cl_tlcs::make_cpu_hw(void)
+{
+  add_hw(cpu= new cl_tlcs_cpu(this));
+  cpu->init();
+}
+
+void
 cl_tlcs::mk_hw_elements(void)
 {
-  //class cl_base *o;
-  //hws->add(o= new cl_port(this));
-  //o->init();
+  class cl_hw *h;
   cl_uc::mk_hw_elements();
+
+  add_hw(h= new cl_dreg(this, 0, "dreg"));
+  h->init();
 }
 
 
@@ -189,20 +186,20 @@
 {
   class cl_address_space *as;
 
-  rom= nas= as= new cl_address_space(cchars("nas"), 0, 0x10000, 8);
+  rom= nas= as= new cl_address_space("nas", 0, 0x10000, 8);
   as->init();
   address_spaces->add(as);
-  xas= as= new cl_address_space(cchars("xas"), 0, 0x10000, 8);
+  xas= as= new cl_address_space("xas", 0, 0x10000, 8);
   as->init();
   address_spaces->add(as);
-  yas= as= new cl_address_space(cchars("yas"), 0, 0x10000, 8);
+  yas= as= new cl_address_space("yas", 0, 0x10000, 8);
   as->init();
   address_spaces->add(as);
 
   class cl_address_decoder *ad;
   class cl_memory_chip *chip;
 
-  chip= new cl_memory_chip("nas_chip", 0x10000, 8);
+  chip= new cl_chip8("nas_chip", 0x10000, 8);
   chip->init();
   memchips->add(chip);
   ad= new cl_address_decoder(as= nas,
@@ -363,14 +360,15 @@
 }
 
 char *
-cl_tlcs::disass(t_addr addr, const char *sep)
+cl_tlcs::disass(t_addr addr)
 {
   struct dis_entry *de;
+  t_addr operand;
   u64_t c;
   int i;
   chars s("");
-  char *buf, *t, l[20];
-  
+  const char *t;
+
   c= 0;
   for (i= 7; i>=0; i--)
     {
@@ -389,7 +387,7 @@
   if (de->mnemonic == NULL)
     return strdup("?");
 
-  for (t= (char*)de->mnemonic; *t; t++)
+  for (t= de->mnemonic; *t; t++)
     {
       if (*t == '%')
 	{
@@ -418,17 +416,43 @@
 	    case 'C': /* cc in 2nd byte */ s+= condname_C(c>>8); break; // without ,
 	    case 'f': /* cc in 4th byte */ s+= condname_cc(c>>24); break; // with ,
 	    case 'F': /* cc in 3rd byte */ s+= condname_cc(c>>16); break; // with ,
-	    case 'n': /*  n in 2nd byte */ snprintf(l,19,"%02x",(int)((c>>8)&0xff));s+= l; break;
-	    case 'N': /*  n in 3rd byte */ snprintf(l,19,"%02x",(int)((c>>16)&0xff));s+= l; break;
-	    case 'o': /*  n in 4th byte */ snprintf(l,19,"%02x",(int)((c>>24)&0xff));s+= l; break;
-	    case 'O': /*  n in 5th byte */ snprintf(l,19,"%02x",(int)((c>>32)&0xff));s+= l; break;
-	    case '1': /*  PC+2+d in 2nd byte */ snprintf(l,19,"0x%04x",(int)(addr+2+i8_t((c>>8)&0xff))); s+= l; break;
-	    case 'd': /*  d in 2nd byte */ snprintf(l,19,"%+d",(int)(i8_t((c>>8)&0xff))); s+= l; break;
-	    case 'D': /* cd in 2,3 byte */ snprintf(l,19,"0x%04x",(int)(addr+3+i16_t((c>>8)&0xffff))); s+= l; break;	      
-	    case 'M': /* mn in 2,3 byte */ snprintf(l,19,"0x%04x",(int)((c>>8)&0xffff)); s+= l; break;
-	    case 'm': /* mn in 3,4 byte */ snprintf(l,19,"0x%04x",(int)((c>>16)&0xffff)); s+= l; break;
-	    case 'X': /* mn in 4,5 byte */ snprintf(l,19,"0x%04x",(int)((c>>24)&0xffff)); s+= l; break;
-	    case 'x': /* mn in 5,6 byte */ snprintf(l,19,"0x%04x",(int)((c>>32)&0xffff)); s+= l; break;
+	    case 'n': /*  n in 2nd byte */ s.appendf("%02x",(int)((c>>8)&0xff)); break;
+	    case 'N': /*  n in 3rd byte */ s.appendf("%02x",(int)((c>>16)&0xff)); break;
+	    case 'o': /*  n in 4th byte */ s.appendf("%02x",(int)((c>>24)&0xff)); break;
+	    case 'O': /*  n in 5th byte */ s.appendf("%02x",(int)((c>>32)&0xff)); break;
+	    case 'd': /*  d in 2nd byte */ s.appendf("%+d",(int)(i8_t((c>>8)&0xff))); break;
+
+	    case '1': /*  PC+2+d in 2nd byte */
+	      operand= (u16_t)(addr+2 + (i8_t)((c>>8)&0xff));
+	      s.appendf("0x%04x", operand);
+	      addr_name(operand, rom, &s);
+	      break;
+	    case 'D': /* cd in 2,3 byte */
+	      operand= (u16_t)(addr+3 + (i16_t)((c>>8)&0xffff));
+	      s.appendf("0x%04x", operand);
+	      addr_name(operand, rom, &s);
+	      break;
+	    case 'M': /* mn in 2,3 byte */
+	      operand= (u16_t)((c>>8)&0xffff);
+	      s.appendf("0x%04x", operand);
+	      addr_name(operand, rom, &s);
+	      break;
+	    case 'm': /* mn in 3,4 byte */
+	      operand= (u16_t)((c>>16)&0xffff);
+	      s.appendf("0x%04x", operand);
+	      addr_name(operand, rom, &s);
+	      break;
+	    case 'X': /* mn in 4,5 byte */
+	      operand= (u16_t)((c>>24)&0xffff);
+	      s.appendf("0x%04x", operand);
+	      addr_name(operand, rom, &s);
+	      break;
+	    case 'x': /* mn in 5,6 byte */
+	      operand= (u16_t)((c>>32)&0xffff);
+	      s.appendf("0x%04x", operand);
+	      addr_name(operand, rom, &s);
+	      break;
+
 	    default: s+= '?'; break;
 	    }
 	}
@@ -436,8 +460,7 @@
 	s+= *t;
     }
   
-  buf= strdup(s);
-  return buf;
+  return strdup(s);
 }
 
 int
@@ -473,6 +496,7 @@
 void
 cl_tlcs::print_regs(class cl_console_base *con)
 {
+  con->dd_color("answer");
   con->dd_printf("SZIHXVNC  Flags= 0x%02x %3d %c  ",
                  reg.raf.f, reg.raf.f, isprint(reg.raf.f)?reg.raf.f:'.');
   con->dd_printf("A= 0x%02x %3d %c\n",
@@ -504,10 +528,32 @@
   con->dd_printf("SP= 0x%04x [SP]= %02x %3d %c\n",
                  reg.sp, nas->get(reg.sp), nas->get(reg.sp),
                  isprint(nas->get(reg.sp))?nas->get(reg.sp):'.');
+  con->dd_printf("SP limit= 0x%04x\n", AU(sp_limit));
 
   print_disass(PC, con);
 }
 
+
+void
+cl_tlcs::stack_check_overflow(class cl_stack_op *op)
+{
+  if (op)
+    {
+      if (op->get_op() & stack_write_operation)
+	{
+	  t_addr a= op->get_after();
+	  if (a < sp_limit)
+	    {
+	      class cl_error_stack_overflow *e=
+		new cl_error_stack_overflow(op);
+	      e->init();
+	      error(e);
+	    }
+	}
+    }
+}
+
+
 int
 cl_tlcs::exec_inst(void)
 {
@@ -692,14 +738,14 @@
     case 0x6D: inst_xor_a(c2); break; // XOR A,n
     case 0x6E: inst_or_a(c2); break; // OR A,n
     case 0x6F: op_cp_a(c2); break; // CP A,n
-    case 0x70: reg.hl= op_add_hl(t_addr(0xff00+c2)); break; // ADD HL,(0ffn)
-    case 0x71: reg.hl= op_adc_hl(t_addr(0xff00+c2)); break; // ADC HL,(0ffn)
-    case 0x72: reg.hl= op_sub_hl(t_addr(0xff00+c2)); break; // SUB HL,(0ffn)
-    case 0x73: reg.hl= op_sbc_hl(t_addr(0xff00+c2)); break; // SBC HL,(0ffn)
-    case 0x74: reg.hl= op_and_hl(t_addr(0xff00+c2)); break; // AND HL,(0ffn)
-    case 0x75: reg.hl= op_xor_hl(t_addr(0xff00+c2)); break; // XOR HL,(0ffn)
-    case 0x76: reg.hl= op_or_hl(t_addr(0xff00+c2)); break; // OR HL,(0ffn)
-    case 0x77: op_sub_hl(t_addr(0xff00+c2)); break; // CP HL,(0ffn)
+    case 0x70: reg.hl= op_add_hl_a(0xff00+c2); break; // ADD HL,(0ffn)
+    case 0x71: reg.hl= op_adc_hl_a(0xff00+c2); break; // ADC HL,(0ffn)
+    case 0x72: reg.hl= op_sub_hl_a(0xff00+c2); break; // SUB HL,(0ffn)
+    case 0x73: reg.hl= op_sbc_hl_a(0xff00+c2); break; // SBC HL,(0ffn)
+    case 0x74: reg.hl= op_and_hl_a(0xff00+c2); break; // AND HL,(0ffn)
+    case 0x75: reg.hl= op_xor_hl_a(0xff00+c2); break; // XOR HL,(0ffn)
+    case 0x76: reg.hl= op_or_hl_a(0xff00+c2); break; // OR HL,(0ffn)
+    case 0x77: op_sub_hl_a(0xff00+c2); break; // CP HL,(0ffn)
     case 0x87: inst_inc(n); break; // INC (0ffn)
     case 0x8F: inst_dec(n); break; // DEC (0ffn)
     default:
@@ -760,18 +806,18 @@
     case 0x65: res= inst_xor_a(cell_hl_a()); break; // XOR A,(HL+A)
     case 0x66: res= inst_or_a(cell_hl_a()); break; // OR A,(HL+A)
     case 0x67: res= op_cp_a(cell_hl_a()); break; // CP A,(HL+A)
-    case 0x70: reg.hl= op_add_hl((t_addr)(reg.hl+reg.raf.a)); break; // ADD HL,(HL+A)
-    case 0x71: reg.hl= op_adc_hl((t_addr)(reg.hl+reg.raf.a)); break; // ADC HL,(HL+A)
-    case 0x72: reg.hl= op_sub_hl((t_addr)(reg.hl+reg.raf.a)); break; // SUB HL,(HL+A)
-    case 0x73: reg.hl= op_sbc_hl((t_addr)(reg.hl+reg.raf.a)); break; // SBC HL,(HL+A)
-    case 0x74: reg.hl= op_and_hl((t_addr)(reg.hl+reg.raf.a)); break; // AND HL,(HL+A)
-    case 0x75: reg.hl= op_xor_hl((t_addr)(reg.hl+reg.raf.a)); break; // XOR HL,(HL+A)
-    case 0x76: reg.hl= op_or_hl((t_addr)(reg.hl+reg.raf.a)); break; // OR HL,(HL+A)
-    case 0x77: reg.hl= op_sub_hl((t_addr)(reg.hl+reg.raf.a)); break; // CP HL,(HL+A)
+    case 0x70: reg.hl= op_add_hl_a((reg.hl+reg.raf.a)); break; // ADD HL,(HL+A)
+    case 0x71: reg.hl= op_adc_hl_a((reg.hl+reg.raf.a)); break; // ADC HL,(HL+A)
+    case 0x72: reg.hl= op_sub_hl_a((reg.hl+reg.raf.a)); break; // SUB HL,(HL+A)
+    case 0x73: reg.hl= op_sbc_hl_a((reg.hl+reg.raf.a)); break; // SBC HL,(HL+A)
+    case 0x74: reg.hl= op_and_hl_a((reg.hl+reg.raf.a)); break; // AND HL,(HL+A)
+    case 0x75: reg.hl= op_xor_hl_a((reg.hl+reg.raf.a)); break; // XOR HL,(HL+A)
+    case 0x76: reg.hl= op_or_hl_a((reg.hl+reg.raf.a)); break; // OR HL,(HL+A)
+    case 0x77: reg.hl= op_sub_hl_a((reg.hl+reg.raf.a)); break; // CP HL,(HL+A)
     case 0x87: inst_inc(cell_hl_a()); break; // INC (HL+A)
     case 0x8f: inst_dec(cell_hl_a()); break; // DEC (HL+A)
-    case 0x97: inst_inc16((t_addr)(reg.hl+reg.raf.a)); break; // INCW (HL+A)
-    case 0x9f: inst_dec16((t_addr)(reg.hl+reg.raf.a)); break; // DECW (HL+A)
+    case 0x97: inst_inc16((reg.hl+reg.raf.a)); break; // INCW (HL+A)
+    case 0x9f: inst_dec16((reg.hl+reg.raf.a)); break; // DECW (HL+A)
     case 0xa0: inst_rlc(cell_hl_a()); break; // RLC (HL+A)
     case 0xa1: inst_rrc(cell_hl_a()); break; // RRC (HL+A)
     case 0xa2: inst_rl(cell_hl_a()); break; // RL (HL+A)
@@ -936,14 +982,14 @@
     case 0x65: inst_xor_a(gg); break; // XOR A(gg)
     case 0x66: inst_or_a(gg); break; // OR A,(gg)
     case 0x67: op_cp_a(gg); break; // CP A,(gg)
-    case 0x70: reg.hl= op_add_hl((t_addr)*aof_reg16_gg(c1)); break; // ADD HL,(gg)
-    case 0x71: reg.hl= op_adc_hl((t_addr)*aof_reg16_gg(c1)); break; // ADC HL,(gg)
-    case 0x72: reg.hl= op_sub_hl((t_addr)*aof_reg16_gg(c1)); break; // SUB HL,(gg)
-    case 0x73: reg.hl= op_sbc_hl((t_addr)*aof_reg16_gg(c1)); break; // SBC HL,(gg)
-    case 0x74: reg.hl= op_and_hl((t_addr)*aof_reg16_gg(c1)); break; // AND HL,(gg)
-    case 0x75: reg.hl= op_xor_hl((t_addr)*aof_reg16_gg(c1)); break; // XOR HL,(gg)
-    case 0x76: reg.hl= op_or_hl((t_addr)*aof_reg16_gg(c1)); break; // OR HL,(gg)
-    case 0x77: reg.hl= op_sub_hl((t_addr)*aof_reg16_gg(c1)); break; // CP HL,(gg)
+    case 0x70: reg.hl= op_add_hl_a(*aof_reg16_gg(c1)); break; // ADD HL,(gg)
+    case 0x71: reg.hl= op_adc_hl_a(*aof_reg16_gg(c1)); break; // ADC HL,(gg)
+    case 0x72: reg.hl= op_sub_hl_a(*aof_reg16_gg(c1)); break; // SUB HL,(gg)
+    case 0x73: reg.hl= op_sbc_hl_a(*aof_reg16_gg(c1)); break; // SBC HL,(gg)
+    case 0x74: reg.hl= op_and_hl_a(*aof_reg16_gg(c1)); break; // AND HL,(gg)
+    case 0x75: reg.hl= op_xor_hl_a(*aof_reg16_gg(c1)); break; // XOR HL,(gg)
+    case 0x76: reg.hl= op_or_hl_a(*aof_reg16_gg(c1)); break; // OR HL,(gg)
+    case 0x77: reg.hl= op_sub_hl_a(*aof_reg16_gg(c1)); break; // CP HL,(gg)
     case 0x87: inst_inc(gg); break; // INC (gg)
     case 0x8f: inst_dec(gg); break; // DEC (gg)
     case 0x97: inst_inc16gg(c1, *aof_reg16_gg(c1)); break; // INCW (gg)
@@ -1065,14 +1111,14 @@
 	case 0x65: inst_xor_a(*ga); break; // XOR A,g
 	case 0x66: inst_or_a(*ga); break; // OR A,g
 	case 0x67: op_cp_a(*ga); break; // CP A,g
-	case 0x70: reg.hl= op_add_hl((t_mem)*gga); break; // ADD HL,gg
-	case 0x71: reg.hl= op_adc_hl((t_mem)*gga); break; // ADC HL,gg
-	case 0x72: reg.hl= op_sub_hl((t_mem)*gga); break; // SUB HL,gg
-	case 0x73: reg.hl= op_sbc_hl((t_mem)*gga); break; // SBC HL,gg
-	case 0x74: reg.hl= op_and_hl((t_mem)*gga); break; // AND HL,gg
-	case 0x75: reg.hl= op_xor_hl((t_mem)*gga); break; // XOR HL,gg
-	case 0x76: reg.hl= op_or_hl((t_mem)*gga); break; // OR HL,gg
-	case 0x77: op_sub_hl((t_mem)*gga); break; // CP HL,gg
+	case 0x70: reg.hl= op_add_hl_v(*gga); break; // ADD HL,gg
+	case 0x71: reg.hl= op_adc_hl_v(*gga); break; // ADC HL,gg
+	case 0x72: reg.hl= op_sub_hl_v(*gga); break; // SUB HL,gg
+	case 0x73: reg.hl= op_sbc_hl_v(*gga); break; // SBC HL,gg
+	case 0x74: reg.hl= op_and_hl_v(*gga); break; // AND HL,gg
+	case 0x75: reg.hl= op_xor_hl_v(*gga); break; // XOR HL,gg
+	case 0x76: reg.hl= op_or_hl_v(*gga); break; // OR HL,gg
+	case 0x77: op_sub_hl_v(*gga); break; // CP HL,gg
 	case 0xA0: *ga= op_rlc(*ga, true); break; // RLC g
 	case 0xA1: *ga= op_rrc(*ga, true); break; // RRC g
 	case 0xA2: *ga= op_rl(*ga, true); break; // RL g
@@ -1129,14 +1175,14 @@
     case 0x1b: PC+= i16_t(c3*256 + c2); break; // JRL $+2+cd
     case 0x1c: inst_call(PC-3, c3*256 + c2); break; // CALL mn
     case 0x1d: inst_call(PC-3, PC + i16_t(c3*256 + c2)); break; // CALR $+2+cd
-    case 0x78: reg.hl= op_add_hl((t_mem)(c3*256+c2)); break; // ADD HL,mn
-    case 0x79: reg.hl= op_adc_hl((t_mem)(c3*256+c2)); break; // ADC HL,mn
-    case 0x7a: reg.hl= op_sub_hl((t_mem)(c3*256+c2)); break; // SUB HL,mn
-    case 0x7b: reg.hl= op_sbc_hl((t_mem)(c3*256+c2)); break; // SBC HL,mn
-    case 0x7c: reg.hl= op_and_hl((t_mem)(c3*256+c2)); break; // AND HL,mn
-    case 0x7d: reg.hl= op_xor_hl((t_mem)(c3*256+c2)); break; // XOR HL,mn
-    case 0x7e: reg.hl= op_or_hl((t_mem)(c3*256+c2)); break; // OR HL,mn
-    case 0x7f: op_sub_hl((t_mem)(c3*256+c2)); break; // CP HL,mn
+    case 0x78: reg.hl= op_add_hl_v((c3*256+c2)); break; // ADD HL,mn
+    case 0x79: reg.hl= op_adc_hl_v((c3*256+c2)); break; // ADC HL,mn
+    case 0x7a: reg.hl= op_sub_hl_v((c3*256+c2)); break; // SUB HL,mn
+    case 0x7b: reg.hl= op_sbc_hl_v((c3*256+c2)); break; // SBC HL,mn
+    case 0x7c: reg.hl= op_and_hl_v((c3*256+c2)); break; // AND HL,mn
+    case 0x7d: reg.hl= op_xor_hl_v((c3*256+c2)); break; // XOR HL,mn
+    case 0x7e: reg.hl= op_or_hl_v((c3*256+c2)); break; // OR HL,mn
+    case 0x7f: op_sub_hl_v((c3*256+c2)); break; // CP HL,mn
     default:
       switch (c1 & 0xf8)
 	{
@@ -1232,14 +1278,14 @@
     case 0x65: inst_xor_a(c); break; // XOR A,(ix+d)
     case 0x66: inst_or_a(c); break; // OR A,(ix+d)
     case 0x67: op_cp_a(c); break; // CP A,(ix+d)
-    case 0x70: reg.hl= op_add_hl((t_mem)mem16ixd(c1,d)); vc.rd+= 2; break; // ADD HL,(ix+d)
-    case 0x71: reg.hl= op_adc_hl((t_mem)mem16ixd(c1,d)); vc.rd+= 2; break; // ADC HL,(ix+d)
-    case 0x72: reg.hl= op_sub_hl((t_mem)mem16ixd(c1,d)); vc.rd+= 2; break; // SUB HL,(ix+d)
-    case 0x73: reg.hl= op_sbc_hl((t_mem)mem16ixd(c1,d)); vc.rd+= 2; break; // SBC HL,(ix+d)
-    case 0x74: reg.hl= op_and_hl((t_mem)mem16ixd(c1,d)); vc.rd+= 2; break; // AND HL,(ix+d)
-    case 0x75: reg.hl= op_xor_hl((t_mem)mem16ixd(c1,d)); vc.rd+= 2; break; // XOR HL,(ix+d)
-    case 0x76: reg.hl= op_or_hl((t_mem)mem16ixd(c1,d)); vc.rd+= 2; break; // OR HL,(ix+d)
-    case 0x77: op_sub_hl((t_mem)mem16ixd(c1,d)); vc.rd+= 2; break; // CP HL,(ix+d)
+    case 0x70: reg.hl= op_add_hl_v(mem16ixd(c1,d)); vc.rd+= 2; break; // ADD HL,(ix+d)
+    case 0x71: reg.hl= op_adc_hl_v(mem16ixd(c1,d)); vc.rd+= 2; break; // ADC HL,(ix+d)
+    case 0x72: reg.hl= op_sub_hl_v(mem16ixd(c1,d)); vc.rd+= 2; break; // SUB HL,(ix+d)
+    case 0x73: reg.hl= op_sbc_hl_v(mem16ixd(c1,d)); vc.rd+= 2; break; // SBC HL,(ix+d)
+    case 0x74: reg.hl= op_and_hl_v(mem16ixd(c1,d)); vc.rd+= 2; break; // AND HL,(ix+d)
+    case 0x75: reg.hl= op_xor_hl_v(mem16ixd(c1,d)); vc.rd+= 2; break; // XOR HL,(ix+d)
+    case 0x76: reg.hl= op_or_hl_v(mem16ixd(c1,d)); vc.rd+= 2; break; // OR HL,(ix+d)
+    case 0x77: op_sub_hl_v(mem16ixd(c1,d)); vc.rd+= 2; break; // CP HL,(ix+d)
     case 0x87: inst_inc(c); break; // INC (ix+d)
     case 0x8F: inst_dec(c); break; // DEC (ix+d)
     case 0x97: inst_inc16ix(c1, a); break; // INCW (ix+d)
@@ -1312,18 +1358,18 @@
     case 0x65: inst_xor_a(c); break; // XOR A,(mn)
     case 0x66: inst_or_a(c); break; // OR A,(mn)
     case 0x67: op_cp_a(c); break; // CP A,(mn)
-    case 0x70: reg.hl= op_add_hl((t_addr)mn); break; // ADD HL,(mn)
-    case 0x71: reg.hl= op_adc_hl((t_addr)mn); break; // ADC HL,(mn)
-    case 0x72: reg.hl= op_sub_hl((t_addr)mn); break; // SUB HL,(mn)
-    case 0x73: reg.hl= op_sbc_hl((t_addr)mn); break; // SBC HL,(mn)
-    case 0x74: reg.hl= op_and_hl((t_addr)mn); break; // AND HL,(mn)
-    case 0x75: reg.hl= op_xor_hl((t_addr)mn); break; // XOR HL,(mn)
-    case 0x76: reg.hl= op_or_hl((t_addr)mn); break; // OR HL,(mn)
-    case 0x77: op_sub_hl((t_addr)mn); break; // CP HL,(mn)
+    case 0x70: reg.hl= op_add_hl_a(mn); break; // ADD HL,(mn)
+    case 0x71: reg.hl= op_adc_hl_a(mn); break; // ADC HL,(mn)
+    case 0x72: reg.hl= op_sub_hl_a(mn); break; // SUB HL,(mn)
+    case 0x73: reg.hl= op_sbc_hl_a(mn); break; // SBC HL,(mn)
+    case 0x74: reg.hl= op_and_hl_a(mn); break; // AND HL,(mn)
+    case 0x75: reg.hl= op_xor_hl_a(mn); break; // XOR HL,(mn)
+    case 0x76: reg.hl= op_or_hl_a(mn); break; // OR HL,(mn)
+    case 0x77: op_sub_hl_a(mn); break; // CP HL,(mn)
     case 0x87: inst_inc(c); break; // INC (mn)
     case 0x8f: inst_dec(c); break; // DEC (mn)
-    case 0x97: inst_inc16((t_addr)mn); break; // INCW (mn)
-    case 0x9f: inst_dec16((t_addr)mn); break; // DECW (mn)
+    case 0x97: inst_inc16(mn); break; // INCW (mn)
+    case 0x9f: inst_dec16(mn); break; // DECW (mn)
     case 0xa0: inst_rlc(c); break; // RLC (mn)
     case 0xa1: inst_rrc(c); break; // RRC (mn)
     case 0xa2: inst_rl(c); break; // RL (mn)
@@ -1349,6 +1395,7 @@
 	      write16(mn, *ar);
 	      vc.wr+= 2;
 	      *ar= temp;
+	      break;
 	    }
 	  case 0xa8: inst_bit(c, c4); break; // BIT b,(mn)
 	  case 0xb0: inst_res(c, c4); break; // RES b,(mn)
@@ -1824,4 +1871,52 @@
 }
 
 
+cl_tlcs_cpu::cl_tlcs_cpu(class cl_uc *auc):
+  cl_hw(auc, HW_CPU, 0, "cpu")
+{
+}
+
+int
+cl_tlcs_cpu::init(void)
+{
+  cl_hw::init();
+
+  cl_var *v;
+  uc->vars->add(v= new cl_var("sp_limit", cfg, tlcscpu_sp_limit,
+			      cfg_help(tlcscpu_sp_limit)));
+  v->init();
+
+  return 0;
+}
+
+const char *
+cl_tlcs_cpu::cfg_help(t_addr addr)
+{
+  switch (addr)
+    {
+    case tlcscpu_sp_limit:
+      return "Stack overflows when SP is below this limit";
+    }
+  return "Not used";
+}
+
+t_mem
+cl_tlcs_cpu::conf_op(cl_memory_cell *cell, t_addr addr, t_mem *val)
+{
+  class cl_tlcs *u= (class cl_tlcs *)uc;
+  if (val)
+    cell->set(*val);
+  switch ((enum tlcscpu_confs)addr)
+    {
+    case tlcscpu_sp_limit:
+      if (val)
+	u->sp_limit= *val & 0xffff;
+      else
+	cell->set(u->sp_limit);
+      break;
+    case tlcscpu_nuof: break;
+    }
+  return cell->get();
+}
+
 /* End of tlcs.src/tlcs.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/tlcs.src/tlcscl.h sdcc-4.2.0+dfsg/sim/ucsim/tlcs.src/tlcscl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/tlcs.src/tlcscl.h	2018-12-18 09:27:50.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/tlcs.src/tlcscl.h	2021-10-29 17:39:15.000000000 +0000
@@ -161,13 +161,15 @@
   class cl_address_space *yas;
   class cl_address_space *regs8;
   class cl_address_space *regs16;
+  t_addr sp_limit;
  public:
   cl_tlcs(class cl_sim *asim);
   virtual int init(void);
-  virtual char *id_string(void);
+  virtual const char *id_string(void);
 
   //virtual t_addr get_mem_size(enum mem_class type);
   //virtual int get_mem_width(enum mem_class type);
+  virtual void make_cpu_hw(void);
   virtual void mk_hw_elements(void);
   virtual void make_memories(void);
 
@@ -181,10 +183,12 @@
   virtual const char *bitname(u8_t b);
   virtual const char *condname_cc(u8_t cc);
   virtual const char *condname_C(u8_t cc);
-  virtual char *disass(t_addr addr, const char *sep);
+  virtual char *disass(t_addr addr);
   virtual void print_regs(class cl_console_base *con);
   virtual int inst_length(t_addr addr);
 
+  virtual void stack_check_overflow(class cl_stack_op *op);
+  
   virtual int exec_inst(void);
   virtual int exec_inst2(u8_t c1);
   virtual int exec_inst2_f3(u8_t c1);
@@ -285,23 +289,23 @@
   virtual u16_t inst_inc16gg(u8_t gg,t_addr addr);// INCW mem
   virtual u16_t inst_inc16ix(u8_t ix,t_addr addr);// INCW mem
   virtual u16_t op_dec16(t_mem data);		// DEC 16 bit
-  virtual u16_t inst_dec16(t_addr addr);		// DECW mem
+  virtual u16_t inst_dec16(t_addr addr);	// DECW mem
   virtual u16_t inst_dec16gg(u8_t gg,t_addr addr);// DECW mem
   virtual u16_t inst_dec16ix(u8_t ix,t_addr addr);// DECW mem
-  virtual u16_t op_add_hl(t_mem val);		// ADD HL,16-bit
-  virtual u16_t op_add_hl(t_addr addr);		// ADD HL,mem
-  virtual u16_t op_adc_hl(t_mem val);		// ADC HL,16-bit
-  virtual u16_t op_adc_hl(t_addr addr);		// ADC HL,mem
-  virtual u16_t op_sub_hl(t_mem val);		// SUB HL,16-bit
-  virtual u16_t op_sub_hl(t_addr addr);		// SUB HL,mem
-  virtual u16_t op_sbc_hl(t_mem val);		// SBC HL,16-bit
-  virtual u16_t op_sbc_hl(t_addr addr);		// SBC HL,mem
-  virtual u16_t op_and_hl(t_mem val);		// AND HL,16-bit
-  virtual u16_t op_and_hl(t_addr addr);		// AND HL,mem
-  virtual u16_t op_xor_hl(t_mem val);		// XOR HL,16-bit
-  virtual u16_t op_xor_hl(t_addr addr);		// XOR HL,mem
-  virtual u16_t op_or_hl(t_mem val);			// OR HL,16-bit
-  virtual u16_t op_or_hl(t_addr addr);		// OR HL,mem
+  virtual u16_t op_add_hl_v(t_mem val);		// ADD HL,16-bit
+  virtual u16_t op_add_hl_a(t_addr addr);	// ADD HL,mem
+  virtual u16_t op_adc_hl_v(t_mem val);		// ADC HL,16-bit
+  virtual u16_t op_adc_hl_a(t_addr addr);	// ADC HL,mem
+  virtual u16_t op_sub_hl_v(t_mem val);		// SUB HL,16-bit
+  virtual u16_t op_sub_hl_a(t_addr addr);	// SUB HL,mem
+  virtual u16_t op_sbc_hl_v(t_mem val);		// SBC HL,16-bit
+  virtual u16_t op_sbc_hl_a(t_addr addr);	// SBC HL,mem
+  virtual u16_t op_and_hl_v(t_mem val);		// AND HL,16-bit
+  virtual u16_t op_and_hl_a(t_addr addr);	// AND HL,mem
+  virtual u16_t op_xor_hl_v(t_mem val);		// XOR HL,16-bit
+  virtual u16_t op_xor_hl_a(t_addr addr);	// XOR HL,mem
+  virtual u16_t op_or_hl_v(t_mem val);		// OR HL,16-bit
+  virtual u16_t op_or_hl_a(t_addr addr);	// OR HL,mem
   virtual u16_t op_add16(t_mem op1, t_mem op2);	// ADD 16-bit
   virtual u16_t op_sub16(t_mem op1, t_mem op2);	// SUB 16-bit
 
@@ -360,6 +364,23 @@
 };
 
 
+enum tlcscpu_confs
+  {
+   tlcscpu_sp_limit	= 0,
+   tlcscpu_nuof		= 1
+  };
+
+class cl_tlcs_cpu: public cl_hw
+{
+public:
+  cl_tlcs_cpu(class cl_uc *auc);
+  virtual int init(void);
+  virtual unsigned int cfg_size(void) { return tlcscpu_nuof; }
+  virtual const char *cfg_help(t_addr addr);
+
+  virtual t_mem conf_op(cl_memory_cell *cell, t_addr addr, t_mem *val);
+};
+
 #endif
 
 /* End of tlcs.src/tlcscl.h */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/utils.cc sdcc-4.2.0+dfsg/sim/ucsim/utils.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/utils.cc	2019-07-02 08:44:01.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/utils.cc	2022-01-18 21:40:45.000000000 +0000
@@ -35,13 +35,13 @@
 #include 
 #include 
 #include 
-#include 
+//#include 
 #include 
-#include "i_string.h"
+#include 
 
   // prj
-#include "stypes.h"
-#include "pobjcl.h"
+//#include "stypes.h"
+//#include "pobjcl.h"
 
 #include "utils.h"
 
@@ -74,7 +74,7 @@
 }
 
 
-char *
+const char *
 get_id_string(struct id_element *ids, int id)
 {
   int i= 0;
@@ -82,13 +82,13 @@
   while (ids[i].id_string &&
 	 id != ids[i].id)
     i++;
-  return(cchars(ids[i].id_string));
+  return(ids[i].id_string);
 }
 
-char *
-get_id_string(struct id_element *ids, int id, char *def)
+const char *
+get_id_string(struct id_element *ids, int id, const char *def)
 {
-  char *s= get_id_string(ids, id);
+  const char *s= get_id_string(ids, id);
 
   return(s?s:def);
 }
@@ -175,12 +175,12 @@
   if (name &&
       *name)
     return(name);
-  return(cchars("(unknown)"));
+  return("(unknown)");
 }
 
 
 char *
-case_string(enum letter_case lcase, char *str)
+case_string(enum letter_case lcase, const char *str)
 {
   char *p= strdup(str);
   char *s= p;
@@ -225,18 +225,6 @@
   return c;
 }
 
-/*char *
-case_string(enum letter_case lcase, const char *str)
-{
-  char *p= NIL;
-
-  if (!str ||
-      !*str)
-    return(NIL);
-  p= strdup(str);
-  return case_string(lcase, p);
-}*/
-
 double
 dnow(void)
 {
@@ -259,14 +247,14 @@
 /* Return true if "serach_in" string ends with string "what" */
 
 bool
-strend(char *search_in, char *what)
+strend(const char *search_in, const char *what)
 {
   if (!search_in ||
       !what ||
       !*search_in ||
       !*what)
     return false;
-  char *start= strstr(search_in, what);
+  const char *start= strstr(search_in, what);
   if (start == NULL)
     return false;
   if (start[strlen(what)] == '\0')
@@ -296,7 +284,7 @@
 bool
 is_hex_file(class cl_f *f)
 {
-  char *n;
+  const char *n;
   if (!f)
     return false;
   n= f->get_file_name();
@@ -304,9 +292,26 @@
       !*n)
     return false;
 
-  if (strend(n, cchars(".ihx")) ||
-      strend(n, cchars(".hex")) ||
-      strend(n, cchars(".ihex")))
+  if (strend(n, ".ihx") ||
+      strend(n, ".hex") ||
+      strend(n, ".ihex"))
+    return true;
+
+  return false;
+}
+
+bool
+is_asc_file(class cl_f *f)
+{
+  const char *n;
+  if (!f)
+    return false;
+  n= f->get_file_name();
+  if (!n ||
+      !*n)
+    return false;
+
+  if (strend(n, ".asc"))
     return true;
 
   return false;
@@ -315,7 +320,7 @@
 bool
 is_omf_file(class cl_f *f)
 {
-  char *n;
+  const char *n;
   if (!f)
     return false;
   n= f->get_file_name();
@@ -323,7 +328,7 @@
       !*n)
     return false;
 
-  if (strend(n, cchars(".omf")))
+  if (strend(n, ".omf"))
     return true;
 
   return false;
@@ -332,7 +337,7 @@
 bool
 is_cdb_file(class cl_f *f)
 {
-  char *n;
+  const char *n;
   if (!f)
     return false;
   n= f->get_file_name();
@@ -340,7 +345,7 @@
       !*n)
     return false;
 
-  if (strend(n, cchars(".cdb")))
+  if (strend(n, ".cdb"))
     return true;
 
   return false;
@@ -351,7 +356,7 @@
 
   option_name=
 	prompt prompt_console command answer
-  	dump_address dump_number dump_char
+	dump_address dump_label dump_number dump_char
 
   col_opt=
 	B bold
@@ -388,124 +393,124 @@
 {
   bool fg_rgb= false, bg_rgb= false;
   bool fg_bright= false, bg_bright= false;
-  chars r= "";
+  chars r= "", full= opt, tok= "";
   int fg= -1, bg= -1;
   int ctype= ct_none;
-  chars o;
-  
+
   if (!opt ||
       !*opt)
     return r;
-  o= opt;
-  char *s= strtok((char*)o, ":");
-  while (s)
+  tok.start_parse();
+  tok= full.token(":");
+  while (tok.nempty())
     {
-      if (strcmp(s, "black") == 0)
+      const char *s= tok.c_str();
+      if (tok=="black")
 	{
 	  if (fg<0)
 	    fg= 0;
 	  else
 	    bg= 0;
 	}
-      else if (strcmp(s, "bblack") == 0)
+      else if (tok=="bblack")
 	{
 	  if (fg<0)
 	    fg= 0, fg_bright= true;
 	  else
 	    bg= 0, bg_bright= true;
 	}
-      else if (strcmp(s, "red") == 0)
+      else if (tok=="red")
 	{
 	  if (fg<0)
 	    fg= 1;
 	  else
 	    bg= 1;
 	}
-      else if (strcmp(s, "bred") == 0)
+      else if (tok=="bred")
 	{
 	  if (fg<0)
 	    fg= 1, fg_bright= true;
 	  else
 	    bg= 1, bg_bright= true;
 	}
-      else if (strcmp(s, "green") == 0)
+      else if (tok=="green")
 	{
 	  if (fg<0)
 	    fg= 2;
 	  else
 	    bg= 2;
 	}
-      else if (strcmp(s, "bgreen") == 0)
+      else if (tok=="bgreen")
 	{
 	  if (fg<0)
 	    fg= 2, fg_bright= true;
 	  else
 	    bg= 2, bg_bright= true;
 	}
-      else if (strcmp(s, "yellow") == 0)
+      else if (tok=="yellow")
 	{
 	  if (fg<0)
 	    fg= 3;
 	  else
 	    bg= 3;
 	}
-      else if (strcmp(s, "byellow") == 0)
+      else if (tok=="byellow")
 	{
 	  if (fg<0)
 	    fg= 3, fg_bright= true;
 	  else
 	    bg= 3, bg_bright= true;
 	}
-      else if (strcmp(s, "blue") == 0)
+      else if (tok=="blue")
 	{
 	  if (fg<0)
 	    fg= 4;
 	  else
 	    bg= 4;
 	}
-      else if (strcmp(s, "bblue") == 0)
+      else if (tok=="bblue")
 	{
 	  if (fg<0)
 	    fg= 4, fg_bright= true;
 	  else
 	    bg= 4, bg_bright= true;
 	}
-      else if (strcmp(s, "magenta") == 0)
+      else if (tok=="magenta")
 	{
 	  if (fg<0)
 	    fg= 5;
 	  else
 	    bg= 5;
 	}
-      else if (strcmp(s, "bmagenta") == 0)
+      else if (tok=="bmagenta")
 	{
 	  if (fg<0)
 	    fg= 5, fg_bright= true;
 	  else
 	    bg= 5, bg_bright= true;
 	}
-      else if (strcmp(s, "cyan") == 0)
+      else if (tok=="cyan")
 	{
 	  if (fg<0)
 	    fg= 6;
 	  else
 	    bg= 6;
 	}
-      else if (strcmp(s, "bcyan") == 0)
+      else if (tok=="bcyan")
 	{
 	  if (fg<0)
 	    fg= 6, fg_bright= true;
 	  else
 	    bg= 6, bg_bright= true;
 	}
-      else if (strcmp(s, "white") == 0)
+      else if (tok=="white")
 	{
 	  if (fg<0)
 	    fg= 7;
 	  else
 	    bg= 7;
 	}
-      else if (strcmp(s, "bwhite") == 0)
+      else if (tok=="bwhite")
 	{
 	  if (fg<0)
 	    fg= 7, fg_bright= true;
@@ -520,28 +525,29 @@
 	  else
 	    bg= c, bg_rgb= true;
 	}
-      else if (strspn(s, "bBfFiIuUdDcCoOkKlL") > 0)
+      else
 	{
 	  int i;
-	  for (i=0; s[i]; i++)
-	    {
-	      switch (toupper(s[i]))
-		{
-		case 'B': ctype|= ct_bold; break;
-		case 'F': ctype|= ct_faint; break;
-		case 'I': ctype|= ct_italic; break;
-		case 'U': ctype|= ct_underl; break;
-		case 'D': ctype|= ct_dunderl; break;
-		case 'C': ctype|= ct_crossed; break;
-		case 'O': ctype|= ct_overl; break;
-		case 'K': ctype|= ct_blink; break;
-		case 'L': ctype|= ct_blink; break;
-		}
-	    }
+	  if (strcspn(s, "bBfFiIuUdDcCoOkKlL") == 0)
+	    for (i=0; s[i]; i++)
+	      {
+		switch (toupper(s[i]))
+		  {
+		  case 'B': ctype|= ct_bold; break;
+		  case 'F': ctype|= ct_faint; break;
+		  case 'I': ctype|= ct_italic; break;
+		  case 'U': ctype|= ct_underl; break;
+		  case 'D': ctype|= ct_dunderl; break;
+		  case 'C': ctype|= ct_crossed; break;
+		  case 'O': ctype|= ct_overl; break;
+		  case 'K': ctype|= ct_blink; break;
+		  case 'L': ctype|= ct_blink; break;
+		  }
+	      }
 	}
-      s= strtok(NULL, ":");
+      tok= full.token(":");
     }
-
+    
   /* set character rendering mode */
   if (ctype != ct_none)
     {
@@ -560,14 +566,14 @@
     {
       if (bg_rgb)
 	{
-	  r.append("\033[48;2;%d;%d;%dm", (bg>>16)&0xff, (bg>>8)&0xff, bg&0xff);
+	  r.appendf("\033[48;2;%d;%d;%dm", (bg>>16)&0xff, (bg>>8)&0xff, bg&0xff);
 	}
       else
 	{
 	  int i= 40+bg;
 	  if (bg_bright)
 	    i= 100+bg;
-	  r.append("\033[%dm", i);
+	  r.appendf("\033[%dm", i);
 	}
     }
   
@@ -576,19 +582,115 @@
     {
       if (fg_rgb)
 	{
-	  r.append("\033[38;2;%d;%d;%dm", (fg>>16)&0xff, (fg>>8)&0xff, fg&0xff);
+	  r.appendf("\033[38;2;%d;%d;%dm", (fg>>16)&0xff, (fg>>8)&0xff, fg&0xff);
 	}
       else
 	{
 	  int i= 30+fg;
 	  if (fg_bright)
 	    i= 90+fg;
-	  r.append("\033[%dm", i);
+	  r.appendf("\033[%dm", i);
 	}
     }
   
   return r;
 }
 
+double
+strtoscale(const char *scale, const char **units)
+{
+  double d = 1.0;
+  const char *u;
+
+  if (!units)
+    units = &u;
+
+  *units = &scale[0];
+
+  if (scale[0])
+    {
+      *units = &scale[1];
+      switch (scale[0])
+        {
+          case 'f':
+            d = 1 / 1000000000000000.0;
+            break;
+          case 'p':
+            d = 1 / 1000000000000.0;
+            break;
+          case 'n':
+            d = 1 / 1000000000.0;
+            break;
+          case 'u':
+            d = 1 / 1000000.0;
+            break;
+          case 'm':
+            d = 1 / 1000.0;
+            break;
+          default:
+            if (!strncmp(scale, "µ", sizeof("µ") - 1))
+              {
+                d = 1 / 1000000.0;
+                *units = &scale[sizeof("µ")];
+              }
+            else
+              {
+                if (scale[1] != 'i')
+                  {
+                    switch (scale[0])
+                      {
+                        case 'k':
+                          d = 1000.0;
+                          break;
+                        case 'M':
+                          d = 1000000.0;
+                          break;
+                        case 'G':
+                          d = 1000000000.0;
+                          break;
+                        case 'T':
+                          d = 1000000000000.0;
+                          break;
+                        case 'P':
+                          d = 1000000000000000.0;
+                          break;
+                        default:
+                          *units = &scale[0];
+                          break;
+                      }
+                  }
+                else
+                  {
+                    *units = &scale[2];
+                    switch (scale[0])
+                      {
+                        case 'k':
+                          d = 1024.0;
+                          break;
+                        case 'M':
+                          d = 1024.0 * 1024.0;
+                          break;
+                        case 'G':
+                          d = 1024.0 * 1024.0 * 1024.0;
+                          break;
+                        case 'T':
+                          d = 1024.0 * 1024.0 * 1024.0 * 1024.0;
+                          break;
+                        case 'P':
+                          d = 1024.0 * 1024.0 * 1024.0 * 1024.0 * 1024.0;
+                          break;
+                        default:
+                          *units = &scale[0];
+                          break;
+                      }
+                  }
+              }
+            break;
+        }
+    }
+
+  return d;
+}
+
 
 /* End of utils.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/utils.h sdcc-4.2.0+dfsg/sim/ucsim/utils.h
--- sdcc-4.0.0+dfsg/sim/ucsim/utils.h	2019-07-02 08:44:01.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/utils.h	2022-01-18 21:40:45.000000000 +0000
@@ -28,6 +28,7 @@
 #ifndef UTILS_HEADER
 #define UTILS_HEADER
 
+#include 
 #include 
 #include 
 
@@ -44,29 +45,31 @@
 extern int get_sub_opt(char **option,
 		       const char * const *tokens,
 		       char **valuep);
-extern char *get_id_string(struct id_element *ids, int id);
-extern char *get_id_string(struct id_element *ids, int id, char *def);
+extern const char *get_id_string(struct id_element *ids, int id);
+extern const char *get_id_string(struct id_element *ids, int id, const char *def);
 extern int get_string_id(struct id_element *ids, char *str);
 extern int get_string_id(struct id_element *ids, char *str, int def);
 extern char *vformat_string(const char *format, va_list ap);
 extern char *format_string(const char *format, ...);
 extern void print_char_octal(char c, FILE *f);
 extern const char *object_name(class cl_base *o);
-extern char *case_string(enum letter_case lcase, char *str);
+extern char *case_string(enum letter_case lcase, const char *str);
 extern chars cbin(long data, int bits);
 
 extern double dnow(void);
 
 extern int strispn(char *s, char c);
-extern bool strend(char *search_in, char *what);
+extern bool strend(const char *search_in, const char *what);
 extern bool valid_sym_name(char *s);
 
 extern bool is_hex_file(class cl_f *f);
+extern bool is_asc_file(class cl_f *f);
 extern bool is_omf_file(class cl_f *f);
 extern bool is_cdb_file(class cl_f *f);
 
 extern chars colopt2ansiseq(char *opt);
 
+extern double strtoscale(const char *s, const char **units = 0);
 
 #endif
 
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/.version sdcc-4.2.0+dfsg/sim/ucsim/.version
--- sdcc-4.0.0+dfsg/sim/ucsim/.version	2019-05-24 06:44:15.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/.version	2022-02-08 21:21:05.000000000 +0000
@@ -1 +1 @@
-0.6-pre56
+0.6.4
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/xa.src/clean.mk sdcc-4.2.0+dfsg/sim/ucsim/xa.src/clean.mk
--- sdcc-4.0.0+dfsg/sim/ucsim/xa.src/clean.mk	2003-04-24 21:06:59.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/xa.src/clean.mk	2021-09-19 19:38:05.000000000 +0000
@@ -3,7 +3,9 @@
 clean:
 	rm -f *core *[%~] *.[oa]
 	rm -f .[a-z]*~
-	rm -f sxa$(EXEEXT)
+	rm -f sxa sxa.exe
+	rm -f ucsim_xa ucsim_xa.exe
+	$(MAKE) -C test -f clean.mk clean
 
 
 # Deleting all files created by configuring or building the program
@@ -11,6 +13,7 @@
 distclean: clean
 	rm -f config.cache config.log config.status
 	rm -f Makefile *.dep
+	$(MAKE) -C test -f clean.mk distclean
 
 
 # Like clean but some files may still exist
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/xa.src/glob.cc sdcc-4.2.0+dfsg/sim/ucsim/xa.src/glob.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/xa.src/glob.cc	2017-03-29 15:20:04.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/xa.src/glob.cc	2020-03-27 20:18:53.000000000 +0000
@@ -29,7 +29,7 @@
 
 #include 
 
-#include "stypes.h"
+//#include "stypes.h"
 #include "glob.h"
 
 /* this needs to match enum definition in glob.h */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/xa.src/glob.h sdcc-4.2.0+dfsg/sim/ucsim/xa.src/glob.h
--- sdcc-4.0.0+dfsg/sim/ucsim/xa.src/glob.h	2017-03-29 15:20:04.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/xa.src/glob.h	2022-01-27 21:35:29.000000000 +0000
@@ -115,7 +115,7 @@
 
 extern const char *op_mnemonic_str[];
 
-/* this classifies the operands and is used in the dissassembly
+/* this classifies the operands and is used in the disassembly
    to print the operands.  Its also used in the simulation to characterize
    the op-code function.
  */   
@@ -190,7 +190,7 @@
   IIREG
 };
 
-// table of dissassembled instructions
+// table of disassembled instructions
 struct xa_dis_entry
 {
   uint is1byte; /* only grab 1 byte for table lookup(most are 2 bytes) */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/xa.src/inst.cc sdcc-4.2.0+dfsg/sim/ucsim/xa.src/inst.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/xa.src/inst.cc	2003-01-03 08:51:59.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/xa.src/inst.cc	2020-03-27 20:18:53.000000000 +0000
@@ -28,14 +28,15 @@
 02111-1307, USA. */
 /*@1@*/
 
-#include "ddconfig.h"
+//#include "ddconfig.h"
 
+#include 
 #include 
 
 // local
 #include "glob.h"
 #include "xacl.h"
-#include "regsxa.h"
+//#include "regsxa.h"
 
 #define NOTDONE_ASSERT { printf("**********Instr not done at %d!\n", __LINE__); }
 
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/xa.src/Makefile.in sdcc-4.2.0+dfsg/sim/ucsim/xa.src/Makefile.in
--- sdcc-4.0.0+dfsg/sim/ucsim/xa.src/Makefile.in	2017-03-12 13:28:55.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/xa.src/Makefile.in	2022-01-09 14:02:03.000000000 +0000
@@ -4,6 +4,9 @@
 # (c) Drotos Daniel, Talker Bt. 1997
 #
 
+# tool name
+TN		= xa
+
 STARTYEAR	= 1997
 
 SHELL		= /bin/sh
@@ -26,8 +29,8 @@
 CPPFLAGS        = @CPPFLAGS@ -I$(srcdir) -I$(top_srcdir) -I$(top_builddir) \
 		  -I$(top_srcdir)/cmd.src -I$(top_srcdir)/sim.src \
 		  -I$(top_srcdir)/gui.src
-CFLAGS          = @CFLAGS@ @WALL_FLAG@
-CXXFLAGS        = @CXXFLAGS@ @WALL_FLAG@
+CFLAGS          = @WALL_FLAG@ @CFLAGS@
+CXXFLAGS        = @WALL_FLAG@ @CXXFLAGS@
 LDFLAGS         = @LDFLAGS@
 PICOPT		= @PICOPT@
 
@@ -47,9 +50,19 @@
 srcdir          = @srcdir@
 VPATH           = @srcdir@
 
-OBJECTS         = sxa.o glob.o \
+OBJECTS_SHARED	= glob.o \
 		  inst.o \
-		  simxa.o xa.o
+		  sim$(TN).o $(TN).o
+OBJECTS_EXE	= s$(TN).o
+OBJECTS		= $(OBJECTS_SHARED) $(OBJECTS_EXE)
+
+# short/long exe and lib name
+SEN		= s$(TN)$(EXEEXT)
+LEN		= ucsim_$(TN)$(EXEEXT)
+SONAME		= libucsim_$(TN).so
+
+enable_dlso	= @enable_dlso@
+dlso_ok		= @dlso_ok@
 
 XAASM		= 
 #TEST_OBJ	= test_bit.hex test_dis.hex test_mov.hex test_jmp.hex \
@@ -58,27 +71,38 @@
 
 # Compiling entire program or any subproject
 # ------------------------------------------
-all: checkconf otherlibs xa.src tests
+all: checkconf otherlibs $(TN).src tests
 
 tests: $(TEST_OBJ)
 
 
 # Compiling and installing everything and runing test
 # ---------------------------------------------------
-install: all installdirs
-	$(INSTALL) sxa$(EXEEXT) $(DESTDIR)$(bindir)/`echo sxa|sed '$(transform)'`$(EXEEXT)
-	$(STRIP) $(DESTDIR)$(bindir)/`echo sxa|sed '$(transform)'`$(EXEEXT)
+install: all installdirs install_shared_lib
+	$(INSTALL) $(SEN) $(DESTDIR)$(bindir)/$(SEN)
+	$(STRIP) $(DESTDIR)$(bindir)/$(SEN)
+	$(INSTALL) $(LEN) $(DESTDIR)$(bindir)/$(LEN)
+	$(STRIP) $(DESTDIR)$(bindir)/$(LEN)
 
 
 # Deleting all the installed files
 # --------------------------------
 uninstall:
-	rm -f $(DESTDIR)$(bindir)/`echo sxa|sed '$(transform)'`$(EXEEXT)
+	rm -f $(DESTDIR)$(bindir)/$(SEN)
+	rm -f $(DESTDIR)$(bindir)/$(LEN)
+	rm -f $(DESTDIR)$(libdir)/$(SONAME)
 
 
 # Performing self-test
 # --------------------
-check:
+check: test
+
+.PHONY:	test baseline
+test:
+	@$(MAKE) --no-print-directory -C test
+
+baseline:
+	@$(MAKE) --no-print-directory -C test baseline
 
 
 # Performing installation test
@@ -106,11 +130,29 @@
 # --------
 .SUFFIXES: .asm .hex
 
-xa.src: sxa$(EXEEXT)
+$(TN).src: $(SEN) $(LEN) shared_lib
 
-sxa$(EXEEXT): $(OBJECTS) $(top_builddir)/libcmd.a $(top_builddir)/libguiucsim.a $(top_builddir)/libsim.a $(top_builddir)/libucsimutil.a
+$(SEN): $(OBJECTS) $(top_builddir)/libcmd.a $(top_builddir)/libguiucsim.a $(top_builddir)/libsim.a $(top_builddir)/libucsimutil.a
 	$(CXX) $(CXXFLAGS) $(LDFLAGS) $(OBJECTS) $(LIBS) -o $@
 
+$(LEN): s$(TN)$(EXEEXT)
+	cp $< $@
+
+ifeq ($(dlso_ok),yes)
+shared_lib: $(top_builddir)/$(SONAME)
+install_shared_lib: shared_lib
+	test -d $(DESTDIR)$(libdir) || $(INSTALL) -d $(DESTDIR)$(libdir)
+	$(INSTALL) $(top_builddir)/$(SONAME) $(DESTDIR)$(libdir)/$(SONAME)
+else
+shared_lib:
+	@$(top_srcdir)/mkecho $(top_builddir) "No $(TN) shared lib made."
+	@$(top_srcdir)/mkecho $(top_builddir) "(SHAREDLIB="$(SHAREDLIB)",dl_ok="$(dl_ok)",enable_dlso="$(enable_dlso)")"
+install_shared_lib:
+endif
+
+$(top_builddir)/$(SONAME): $(OBJECTS_SHARED)
+	$(CXX) -shared $(LDFLAGS) $(OBJECTS_SHARED) -o $@
+
 otherlibs: $(top_builddir)/libcmd.a $(top_builddir)/libguiucsim.a $(top_builddir)/libsim.a $(top_builddir)/libucsimutil.a
 
 $(top_builddir)/libcmd.a:
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/xa.src/sxa.cc sdcc-4.2.0+dfsg/sim/ucsim/xa.src/sxa.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/xa.src/sxa.cc	2017-01-06 07:36:33.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/xa.src/sxa.cc	2020-06-13 16:30:36.000000000 +0000
@@ -29,7 +29,7 @@
 #include "globals.h"
 
 // sim.src
-#include "appcl.h"
+//#include "appcl.h"
 
 // local
 #include "simxacl.h"
@@ -41,6 +41,7 @@
   class cl_sim *sim;
 
   application= new cl_app();
+  application->set_name("sxa");
   application->init(argc, argv);
   sim= new cl_simxa(application);
   if (sim->init())
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/xa.src/test/clean.mk sdcc-4.2.0+dfsg/sim/ucsim/xa.src/test/clean.mk
--- sdcc-4.0.0+dfsg/sim/ucsim/xa.src/test/clean.mk	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/xa.src/test/clean.mk	2021-04-01 17:52:48.000000000 +0000
@@ -0,0 +1,5 @@
+clean:
+
+distclean:
+	rm -f Makefile
+	find . -type d -name out -exec rm -rf {} \;
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/xa.src/test/config/baseline/XA sdcc-4.2.0+dfsg/sim/ucsim/xa.src/test/config/baseline/XA
--- sdcc-4.0.0+dfsg/sim/ucsim/xa.src/test/config/baseline/XA	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/xa.src/test/config/baseline/XA	2022-02-08 21:21:05.000000000 +0000
@@ -0,0 +1,31 @@
+uCsim, Copyright (C)  Daniel Drotos.
+uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+This is free software, and you are welcome to redistribute it
+under certain conditions; type `show c' for details.
+Type of microcontroller: unspecified XA
+Controller has 3 hardware element(s).
+   on simif[0]
+  off vcd[0]
+   on dreg[0]
+CA---VNZ | R0:eb90 R1:612a R2:fbc2 R3:9ce2
+00---000 | R4:7658 R5:39b5 R6:4a63 SP:0100 ES:0000  DS:0000
+0xb2d4  ? 44 3a 01          CMP   [R2+0x01],R1h[0K
+Memory chips:
+  0x000000-0x0000ff      256 variable_storage (32,%08x,0x%02lx)
+  0x000000-0x00ffff    65536 rom_chip (8,%02x,0x%04lx)
+  0x000000-0x001fff     8192 iram_chip (8,%02x,0x%04lx)
+  0x000000-0x00ffff    65536 xram_chip (8,%02x,0x%04lx)
+  0x000000-0x001fff     8192 sfr_chip (8,%02x,0x%04lx)
+Address spaces:
+  0x000000-0x0000ff      256 variables (32,%08x,0x%02lx)
+  0x000000-0x00ffff    65536 rom (8,%02x,0x%04lx)
+  0x000000-0x001fff     8192 iram (8,%02x,0x%04lx)
+  0x000000-0x001fff     8192 sfr (8,%02x,0x%04lx)
+  0x000000-0x00ffff    65536 xram (8,%02x,0x%04lx)
+Address decoders:
+  variables 0x00 0xff -> variable_storage 0x00 activated
+  rom 0x0000 0xffff -> rom_chip 0x0000 activated
+  iram 0x0000 0x1fff -> iram_chip 0x0000 activated
+  sfr 0x0000 0x1fff -> sfr_chip 0x0000 activated
+  xram 0x0000 0xffff -> xram_chip 0x0000 activated
+The XA Simulator is in development, UNSTABLE, DEVELOPERS ONLY!
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/xa.src/test/config/Makefile sdcc-4.2.0+dfsg/sim/ucsim/xa.src/test/config/Makefile
--- sdcc-4.0.0+dfsg/sim/ucsim/xa.src/test/config/Makefile	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/xa.src/test/config/Makefile	2021-03-21 12:01:19.000000000 +0000
@@ -0,0 +1,8 @@
+OUTPUTS = XA
+
+
+$(OUTPUTS):
+	$(call run-sim, -e 'conf; info reg; info mem')
+
+
+include test-lib.mk
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/xa.src/test/Makefile.in sdcc-4.2.0+dfsg/sim/ucsim/xa.src/test/Makefile.in
--- sdcc-4.0.0+dfsg/sim/ucsim/xa.src/test/Makefile.in	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/xa.src/test/Makefile.in	2021-03-28 10:28:14.000000000 +0000
@@ -0,0 +1,9 @@
+# @configure_input@
+
+srcdir           = @abs_srcdir@
+
+abs_top_builddir = @abs_top_builddir@
+abs_top_srcdir   = @abs_top_srcdir@
+
+
+include $(abs_top_srcdir)/test-target.mk
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/xa.src/test/symdis/baseline/stdout sdcc-4.2.0+dfsg/sim/ucsim/xa.src/test/symdis/baseline/stdout
--- sdcc-4.0.0+dfsg/sim/ucsim/xa.src/test/symdis/baseline/stdout	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/xa.src/test/symdis/baseline/stdout	2022-01-24 11:09:43.000000000 +0000
@@ -0,0 +1,23 @@
+uCsim [ELIDED], Copyright (C) [ELIDED] Daniel Drotos.
+uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+This is free software, and you are welcome to redistribute it
+under certain conditions; type `show c' for details.
+var init rom[0x0000]
+var main rom[0x0004]
+var forever rom[0x0008]
+dc 0x0000 0x0009
+
+0x0000    :
+0x0000    d5 00 01          JMP   0x0004 [0K
+0x0003  ? 00                NOP   [0K
+
+0x0004    :
+0x0004  ? 00                NOP   [0K
+0x0005  ? f3 01             BEQ   0x0008 [0K
+0x0007  ? 00                NOP   [0K
+
+0x0008    :
+0x0008  ? fe ff             BR    0x0008 [0K
+The XA Simulator is in development, UNSTABLE, DEVELOPERS ONLY!
+Loading from [ELIDED]
+10 words read from [ELIDED]
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/xa.src/test/symdis/Makefile sdcc-4.2.0+dfsg/sim/ucsim/xa.src/test/symdis/Makefile
--- sdcc-4.0.0+dfsg/sim/ucsim/xa.src/test/symdis/Makefile	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/xa.src/test/symdis/Makefile	2021-05-07 16:21:16.000000000 +0000
@@ -0,0 +1,15 @@
+OUTPUTS = stdout
+
+
+# Ignore changes in white space. The field widths for labels
+# depends on the length of the longest label. This will be
+# different for different simulators and should not be assumed
+# to be constant for any given simulator.
+DIFF_OPTS += -b
+
+
+stdout:	test.ihx test.cmd
+	$(call run-sim)
+
+
+include test-lib.mk
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/xa.src/test/symdis/test.asm sdcc-4.2.0+dfsg/sim/ucsim/xa.src/test/symdis/test.asm
--- sdcc-4.0.0+dfsg/sim/ucsim/xa.src/test/symdis/test.asm	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/xa.src/test/symdis/test.asm	2021-05-07 16:21:16.000000000 +0000
@@ -0,0 +1,11 @@
+	cpu XAG3
+
+init:	jmp main
+
+main:	;movs r0,#0
+	nop
+	beq forever
+	;movs r0,#1
+	nop
+forever:
+	br forever
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/xa.src/test/symdis/test.cmd sdcc-4.2.0+dfsg/sim/ucsim/xa.src/test/symdis/test.cmd
--- sdcc-4.0.0+dfsg/sim/ucsim/xa.src/test/symdis/test.cmd	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/xa.src/test/symdis/test.cmd	2021-05-07 16:21:16.000000000 +0000
@@ -0,0 +1,4 @@
+var init rom[0x0000]
+var main rom[0x0004]
+var forever rom[0x0008]
+dc 0x0000 0x0009
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/xa.src/test/symdis/test.ihx sdcc-4.2.0+dfsg/sim/ucsim/xa.src/test/symdis/test.ihx
--- sdcc-4.0.0+dfsg/sim/ucsim/xa.src/test/symdis/test.ihx	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/xa.src/test/symdis/test.ihx	2021-05-07 16:21:16.000000000 +0000
@@ -0,0 +1,2 @@
+:0A000000D500010000F30100FEFF2F
+:00000001FF
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/xa.src/test/test-conf.mk sdcc-4.2.0+dfsg/sim/ucsim/xa.src/test/test-conf.mk
--- sdcc-4.0.0+dfsg/sim/ucsim/xa.src/test/test-conf.mk	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/xa.src/test/test-conf.mk	2021-05-07 16:21:16.000000000 +0000
@@ -0,0 +1,10 @@
+# For asl see: http://john.ccac.rwth-aachen.de:8000/as/
+
+AS = asl
+ASFLAGS = -L -h -U
+
+%p:	%.asm
+	$(AS) $(ASFLAGS) -olist '$*.lst' -o '$@' '$<'
+
+%.ihx:	%.p
+	p2hex -F Intel '$<' '$@'
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/xa.src/xa.cc sdcc-4.2.0+dfsg/sim/ucsim/xa.src/xa.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/xa.src/xa.cc	2019-05-06 09:55:43.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/xa.src/xa.cc	2022-01-13 16:56:10.000000000 +0000
@@ -27,23 +27,24 @@
 02111-1307, USA. */
 /*@1@*/
 
-#include "ddconfig.h"
+//#include "ddconfig.h"
 
 #include 
 #include 
-#include 
-#include "i_string.h"
+//#include 
+#include 
 
 // prj
-#include "pobjcl.h"
+//#include "pobjcl.h"
 
 // sim
 #include "simcl.h"
+#include "dregcl.h"
 
 // local
 #include "xacl.h"
 #include "glob.h"
-#include "regsxa.h"
+//#include "regsxa.h"
 
 
 /*
@@ -254,19 +255,12 @@
   for (i= 0; sfr_tabXA51[i].name != NULL; i++)
     {
       if (type->type & sfr_tabXA51[i].cpu_type)
-	{
-	  class cl_var *v;
-	  vars->add(v= new cl_var(chars(sfr_tabXA51[i].name),
-				  sfr,
-				  sfr_tabXA51[i].addr, ""));
-	  v->init();
-	}
+        vars->add(chars(sfr_tabXA51[i].name), sfr, sfr_tabXA51[i].addr, 7, 0, "");
     }
   for (i= 0; bit_tabXA51[i].name != NULL; i++)
     {
       if (type->type & bit_tabXA51[i].cpu_type)
 	{
-	  class cl_var *v;
 	  t_addr a= bit_tabXA51[i].addr;
 	  int bitnr, offset= 0;
 	  if (a >= 0x200)
@@ -276,20 +270,17 @@
 	    }
 	  bitnr= a%8;
 	  a= offset + a/8;
-	  vars->add(v= new cl_var(chars(bit_tabXA51[i].name),
-				  sfr,
-				  a, "", bitnr));
-	  v->init();
+	  vars->add(chars(bit_tabXA51[i].name), sfr, a, bitnr, bitnr, "");
 	}
     }
   return(0);
 }
 
 
-char *
+const char *
 cl_xa::id_string(void)
 {
-  return((char*)"unspecified XA");
+  return("unspecified XA");
 }
 
 
@@ -301,7 +292,11 @@
 cl_xa::mk_hw_elements(void)
 {
   //class cl_base *o;
+  class cl_hw *h;
   cl_uc::mk_hw_elements();
+
+  add_hw(h= new cl_dreg(this, 0, "dreg"));
+  h->init();
 }
 
 void
@@ -325,7 +320,7 @@
   class cl_address_decoder *ad;
   class cl_memory_chip *chip;
 
-  chip= new cl_memory_chip("rom_chip", 0x10000, 8);
+  chip= new cl_chip8("rom_chip", 0x10000, 8);
   chip->init();
   memchips->add(chip);
   ad= new cl_address_decoder(as= address_space("rom"), chip, 0, 0xffff, 0);
@@ -333,7 +328,7 @@
   as->decoders->add(ad);
   ad->activate(0);
 
-  chip= new cl_memory_chip("iram_chip", 0x2000, 8);
+  chip= new cl_chip8("iram_chip", 0x2000, 8);
   chip->init();
   memchips->add(chip);
   ad= new cl_address_decoder(as= address_space("iram"), chip, 0, 0x1fff, 0);
@@ -341,7 +336,7 @@
   as->decoders->add(ad);
   ad->activate(0);
 
-  chip= new cl_memory_chip("xram_chip", 0x10000, 8);
+  chip= new cl_chip8("xram_chip", 0x10000, 8);
   chip->init();
   memchips->add(chip);
   ad= new cl_address_decoder(as= address_space("xram"), chip, 0, 0xffff, 0);
@@ -349,7 +344,7 @@
   as->decoders->add(ad);
   ad->activate(0);
 
-  chip= new cl_memory_chip("sfr_chip", 0x2000, 8);
+  chip= new cl_chip8("sfr_chip", 0x2000, 8);
   chip->init();
   memchips->add(chip);
   ad= new cl_address_decoder(as= address_space("sfr"), chip, 0x0, 0x1fff, 0);
@@ -408,23 +403,26 @@
   return 6;
 }
 
-static char dir_name[64];
-char *cl_xa::get_dir_name(short addr) {
-  if (!/*get*/addr_name(addr, sfr/*_tbl()*/, dir_name)) {
-    sprintf (dir_name, "0x%03x", addr);
-  }
-  return dir_name;
+chars
+cl_xa::get_dir_name(short addr)
+{
+  chars buf= "";
+  if (!addr_name(addr, sfr, &buf))
+    buf= chars("", "0x%03x", addr);
+  return buf;
 }
 
-static char bit_name[64];
-char *cl_xa::get_bit_name(short addr) {
+chars
+cl_xa::get_bit_name(short addr)
+{
   t_addr a= addr; int offset= 0, bitnr= addr%8;
   if (a >= 0x200) { a-= 0x200; offset= 0x400; }
   a= offset+a/8;
-  if (!/*get*/addr_name(a/*ddr*/, sfr/*bit_tbl()*/, bitnr, bit_name)) {
-    sprintf (bit_name, "0x%03x", addr);
-  }
-  return bit_name;
+
+  chars buf= "";
+  if (!addr_name(a, sfr, bitnr, &buf, NULL))
+    buf= chars("", "0x%03x", addr);
+  return buf;
 }
 
 /*--------------------------------------------------------------------
@@ -521,26 +519,26 @@
     sep - optionally points to string(tab) to use as separator.
 |--------------------------------------------------------------------*/
 char *
-cl_xa::disass(t_addr addr, const char *sep)
+cl_xa::disass(t_addr addr)
 {
-  char work[256], parm_str[40];
-  char *buf, *p, *b;
+  chars work;
+  chars parm_str = "";
   int code;
   int len = 0;
   int immed_offset = 0;
   int operands;
   int mnemonic;
   const char **reg_strs;
+  t_addr operand;
 
-  p= work;
+  work= "";
 
   code = get_disasm_info(addr, &len, NULL, &immed_offset, &operands, &mnemonic);
 
-  if (mnemonic == BAD_OPCODE) {
-    buf= (char*)malloc(30);
-    strcpy(buf, "UNKNOWN/INVALID");
-    return(buf);
-  }
+  if (mnemonic == BAD_OPCODE)
+    {
+      return strdup("UNKNOWN/INVALID");
+    }
 
   if (code & 0x0800)
     reg_strs = w_reg_strs;
@@ -550,408 +548,427 @@
   switch(operands) {
      // the repeating common parameter encoding for ADD, ADDC, SUB, AND...
     case REG_REG :
-      sprintf(parm_str, "%s,%s",
+      parm_str= chars("", "%s,%s",
               reg_strs[((code >> 4) & 0xf)],
               reg_strs[(code & 0xf)]);
     break;
     case REG_IREG :
-      sprintf(parm_str, "%s,[%s]",
+      parm_str= chars("", "%s,[%s]",
               reg_strs[((code >> 4) & 0xf)],
               w_reg_strs[(code & 0xf)]);
     break;
     case IREG_REG :
-      sprintf(parm_str, "[%s],%s",
+      parm_str= chars("", "[%s],%s",
               w_reg_strs[(code & 0x7)],
               reg_strs[((code >> 4) & 0xf)] );
     break;
     case REG_IREGOFF8 :
-      sprintf(parm_str, "%s,[%s+%02x]",
+      // Assumption: the index register points to a struct/record
+      // and the byte offset selects an entry.
+      parm_str= chars("", "%s,[%s+0x%02x]",
               reg_strs[((code >> 4) & 0xf)],
               w_reg_strs[(code & 0x7)],
               rom->get(addr+immed_offset));
       ++immed_offset;
     break;
     case IREGOFF8_REG :
-      sprintf(parm_str, "[%s+%02x],%s",
+      parm_str= chars("", "[%s+0x%02x],%s",
               w_reg_strs[(code & 0x7)],
               rom->get(addr+immed_offset),
               reg_strs[((code >> 4) & 0xf)] );
       ++immed_offset;
     break;
     case REG_IREGOFF16 :
-      sprintf(parm_str, "%s,[%s+%04x]",
+      // Assumption: the word offset address is the address of a
+      // fixed table and the index register selects an entry.
+      operand= (u16_t)((rom->get(addr+immed_offset+1)) |
+                       (rom->get(addr+immed_offset)<<8));
+      parm_str= chars("", "%s,[%s+0x%04x",
               reg_strs[((code >> 4) & 0xf)],
               w_reg_strs[(code & 0x7)],
-              (short)((rom->get(addr+immed_offset+1)) |
-                     (rom->get(addr+immed_offset)<<8)) );
+              operand);
+      addr_name(operand, rom, &parm_str);
+      parm_str+= ']';
       ++immed_offset;
       ++immed_offset;
     break;
     case IREGOFF16_REG :
-      sprintf(parm_str, "[%s+%04x],%s",
-              w_reg_strs[(code & 0x7)],
-              (short)((rom->get(addr+immed_offset+1)) |
-                     (rom->get(addr+immed_offset)<<8)),
-              reg_strs[((code >> 4) & 0xf)] );
+      operand= (u16_t)((rom->get(addr+immed_offset+1)) |
+                       (rom->get(addr+immed_offset)<<8));
+      parm_str= chars("", "[%s+%04x", w_reg_strs[(code & 0x7)], operand);
+      addr_name(operand, rom, &parm_str);
+      parm_str= chars("", "],%s", reg_strs[((code >> 4) & 0xf)] );
       ++immed_offset;
       ++immed_offset;
     break;
     case REG_IREGINC :
-      sprintf(parm_str, "%s,[%s+]",
+      parm_str= chars("", "%s,[%s+]",
               reg_strs[((code >> 4) & 0xf)],
               w_reg_strs[(code & 0xf)]);
     break;
     case IREGINC_REG :
-      sprintf(parm_str, "[%s+],%s",
+      parm_str= chars("", "[%s+],%s",
               w_reg_strs[(code & 0x7)],
               reg_strs[((code >> 4) & 0xf)] );
     break;
     case DIRECT_REG :
-      sprintf(parm_str, "%s,%s",
-              get_dir_name(((code & 0x7) << 8) |
-                           rom->get(addr+immed_offset)),
-              reg_strs[((code >> 4) & 0xf)] );
+      parm_str= chars("", "%s,%s",
+		      get_dir_name(((code & 0x7) << 8) |
+				   rom->get(addr+immed_offset)).c_str(),
+		      reg_strs[((code >> 4) & 0xf)] );
       ++immed_offset;
     break;
     case REG_DIRECT :
-      sprintf(parm_str, "%s,%s",
-              reg_strs[((code >> 4) & 0xf)],
-              get_dir_name(((code & 0x7) << 8) |
-                           rom->get(addr+immed_offset)));
+      parm_str= chars("", "%s,%s",
+		      reg_strs[((code >> 4) & 0xf)],
+		      get_dir_name(((code & 0x7) << 8) |
+				   rom->get(addr+immed_offset)).c_str());
       ++immed_offset;
     break;
     case REG_DATA8 :
-      sprintf(parm_str, "%s,#0x%02x",
+      parm_str= chars("", "%s,#0x%02x",
               b_reg_strs[((code >> 4) & 0xf)],
               rom->get(addr+immed_offset) );
       ++immed_offset;
     break;
     case REG_DATA16 :
-      sprintf(parm_str, "%s,#0x%04x",
+      operand= (u16_t)((rom->get(addr+immed_offset+1)) |
+                       (rom->get(addr+immed_offset)<<8));
+      parm_str= chars("", "%s,#0x%04x",
               reg_strs[((code >> 4) & 0xf)],
-              (short)((rom->get(addr+immed_offset+1)) |
-                     (rom->get(addr+immed_offset)<<8)) );
+              operand);
+      addr_name(operand, rom, &parm_str);
       ++immed_offset;
       ++immed_offset;
     break;
     case IREG_DATA8 :
-      sprintf(parm_str, "[%s], 0x%02x",
+      operand= rom->get(addr+immed_offset);
+      parm_str= chars("", "[%s], 0x%02x",
               w_reg_strs[((code >> 4) & 0x7)],
-              rom->get(addr+immed_offset) );
+              operand);
+      addr_name(operand, rom, &parm_str);
       ++immed_offset;
     break;
     case IREG_DATA16 :
-      sprintf(parm_str, "[%s], 0x%04x",
+      operand= (u16_t)((rom->get(addr+immed_offset+1)) |
+                       (rom->get(addr+immed_offset)<<8));
+      parm_str= chars("", "[%s], 0x%04x",
               w_reg_strs[((code >> 4) & 0x7)],
-              (short)((rom->get(addr+immed_offset+1)) |
-                     (rom->get(addr+immed_offset)<<8)) );
+              operand);
+      addr_name(operand, rom, &parm_str);
       ++immed_offset;
       ++immed_offset;
     break;
     case IREGINC_DATA8 :
-      sprintf(parm_str, "[%s+], 0x%02x",
+      operand= rom->get(addr+immed_offset);
+      parm_str= chars("", "[%s+], 0x%02x",
               w_reg_strs[((code >> 4) & 0x7)],
-              rom->get(addr+immed_offset) );
+              operand);
+      addr_name(operand, rom, &parm_str);
       ++immed_offset;
     break;
     case IREGINC_DATA16 :
-      sprintf(parm_str, "[%s+], 0x%04x",
+      operand= (u16_t)((rom->get(addr+immed_offset+1)) |
+                       (rom->get(addr+immed_offset)<<8));
+      parm_str= chars("", "[%s+], 0x%04x",
               w_reg_strs[((code >> 4) & 0x7)],
-              (short)((rom->get(addr+immed_offset+1)) |
-                     (rom->get(addr+immed_offset)<<8)) );
+              operand);
+      addr_name(operand, rom, &parm_str);
       ++immed_offset;
       ++immed_offset;
     break;
     case IREGOFF8_DATA8 :
-      sprintf(parm_str, "[%s+%02x], 0x%02x",
+      operand= rom->get(addr+immed_offset+1);
+      parm_str= chars("", "[%s+%02x], 0x%02x",
               w_reg_strs[((code >> 4) & 0x7)],
               rom->get(addr+immed_offset),
-              rom->get(addr+immed_offset+1) );
+              operand);
+      addr_name(operand, rom, &parm_str);
       immed_offset += 2;
     break;
     case IREGOFF8_DATA16 :
-      sprintf(parm_str, "[%s+%02x], 0x%04x",
+      operand= (u16_t)((rom->get(addr+immed_offset+2)) |
+                       (rom->get(addr+immed_offset+1)<<8));
+      parm_str= chars("", "[%s+%02x], 0x%04x",
               w_reg_strs[((code >> 4) & 0x7)],
               rom->get(addr+immed_offset),
-              (short)((rom->get(addr+immed_offset+2)) |
-                     (rom->get(addr+immed_offset+1)<<8)) );
+              operand);
+      addr_name(operand, rom, &parm_str);
       immed_offset += 3;
     break;
     case IREGOFF16_DATA8 :
-      sprintf(parm_str, "[%s+%04x], 0x%02x",
+      operand= (u16_t)((rom->get(addr+immed_offset+1)) |
+                       (rom->get(addr+immed_offset+0)<<8));
+      parm_str= chars("", "[%s+%04x",
               w_reg_strs[((code >> 4) & 0x7)],
-              (short)((rom->get(addr+immed_offset+1)) |
-                     (rom->get(addr+immed_offset+0)<<8)),
-              rom->get(addr+immed_offset+2) );
+              operand);
+      addr_name(operand, rom, &parm_str);
+      operand= rom->get(addr+immed_offset+2);
+      parm_str= chars("", "], 0x%02x", operand);
+      addr_name(operand, rom, &parm_str);
       immed_offset += 3;
     break;
     case IREGOFF16_DATA16 :
-      sprintf(parm_str, "[%s+%04x], 0x%04x",
+      operand= (u16_t)((rom->get(addr+immed_offset+1)) |
+                       (rom->get(addr+immed_offset+0)<<8));
+      parm_str= chars("", "[%s+%04x",
               w_reg_strs[((code >> 4) & 0x7)],
-              (short)((rom->get(addr+immed_offset+1)) |
-                     (rom->get(addr+immed_offset+0)<<8)),
-              (short)((rom->get(addr+immed_offset+3)) |
-                     (rom->get(addr+immed_offset+2)<<8)) );
+              operand);
+      addr_name(operand, rom, &parm_str);
+      operand= (u16_t)((rom->get(addr+immed_offset+3)) |
+                       (rom->get(addr+immed_offset+2)<<8));
+      parm_str= chars("", "], 0x%04x", operand);
+      addr_name(operand, rom, &parm_str);
       immed_offset += 4;
     break;
     case DIRECT_DATA8 :
-      sprintf(parm_str, "%s,#0x%02x",
-              get_dir_name(((code & 0x0070) << 4) |
-                           rom->get(addr+immed_offset)),
-              rom->get(addr+immed_offset+1));
+      parm_str= chars("", "%s,#0x%02x",
+		      get_dir_name(((code & 0x0070) << 4) |
+				   rom->get(addr+immed_offset)).c_str(),
+		      rom->get(addr+immed_offset+1));
       immed_offset += 3;
     break;
     case DIRECT_DATA16 :
-      sprintf(parm_str, "%s,#0x%04x",
-              get_dir_name(((code & 0x0070) << 4) |
-                           rom->get(addr+immed_offset)),
-              rom->get(addr+immed_offset+2) +
-              (rom->get(addr+immed_offset+1)<<8));
+      operand= rom->get(addr+immed_offset+2) +
+	(rom->get(addr+immed_offset+1)<<8);
+      parm_str= chars("", "%s,#0x%04x",
+		      get_dir_name(((code & 0x0070) << 4) |
+				   rom->get(addr+immed_offset)).c_str(),
+		      operand);
+      addr_name(operand, rom, &parm_str);
       immed_offset += 3;
     break;
 
 // odd-ball ones
     case NO_OPERANDS :  // for NOP
-      strcpy(parm_str, "");
+      parm_str= "";
     break;
     case CY_BIT :
-      sprintf(parm_str, "C,%s",
-             get_bit_name(((code&0x0003)<<8) + rom->get(addr+2)));
+      parm_str= chars("", "C,%s",
+		      get_bit_name(((code&0x0003)<<8) + rom->get(addr+2)).c_str());
     break;
     case BIT_CY :
-      sprintf(parm_str, "%s,C",
-              get_bit_name(((code&0x0003)<<8) + rom->get(addr+2)));
+      parm_str= chars("", "%s,C",
+		      get_bit_name(((code&0x0003)<<8) + rom->get(addr+2)).c_str());
     break;
     case REG_DATA4 :
-      strcpy(parm_str, "REG_DATA4");
+      parm_str= chars("", "REG_DATA4");
     break;
     case REG_DATA5 :
-      strcpy(parm_str, "REG_DATA5");
+      parm_str= chars("", "REG_DATA5");
     break;
     case IREG_DATA4 :
-      strcpy(parm_str, "IREG_DATA4");
+      parm_str= chars("", "IREG_DATA4");
     break;
     case IREGINC_DATA4 :
-      strcpy(parm_str, "IREGINC_DATA4");
+      parm_str= chars("", "IREGINC_DATA4");
     break;
     case IREGOFF8_DATA4 :
-      strcpy(parm_str, "IREGOFF8_DATA4");
+      parm_str= chars("", "IREGOFF8_DATA4");
     break;
     case IREGOFF16_DATA4 :
-      strcpy(parm_str, "IREGOFF16_DATA4");
+      parm_str= chars("", "IREGOFF16_DATA4");
     break;
     case DIRECT_DATA4 :
-      sprintf(parm_str, "%s,#0x%x",
-	      get_dir_name(((code & 0x70)<<4) |
-			   rom->get(addr+2)),
+      parm_str= chars("", "%s,#0x%x",
+		      get_dir_name(((code & 0x70)<<4) |
+				   rom->get(addr+2)).c_str(),
 	      code&0x0f);
     break;
     case DIRECT :
-      sprintf(parm_str, "%s",
-              get_dir_name(((code & 0x007) << 4) +
-                           rom->get(addr+2)));
+      parm_str= chars("", "%s",
+		      get_dir_name(((code & 0x007) << 4) +
+				   rom->get(addr+2)).c_str());
     break;
     case REG :
-      sprintf(parm_str, "%s",
-              reg_strs[((code >> 4) & 0xf)] );
-    break;
+      parm_str= chars("", "%s",
+		      reg_strs[((code >> 4) & 0xf)] );
+      break;
     case IREG :
-      sprintf(parm_str, "[%s]",
-              reg_strs[((code >> 4) & 0xf)] );
+      parm_str= chars("", "[%s]",
+		      reg_strs[((code >> 4) & 0xf)] );
     break;
     case BIT_ALONE :
-      sprintf(parm_str, "%s",
-	      get_bit_name(((code&0x0003)<<8) + rom->get(addr+2)));
+      parm_str= chars("", "%s",
+		      get_bit_name(((code&0x0003)<<8) + rom->get(addr+2)).c_str());
     break;
     case BIT_REL8 :
-      sprintf(parm_str, "%s,0x%04lx",
-	      get_bit_name((code&0x0003)<<8) + rom->get(addr+2),
-	      (long)(((signed char)rom->get(addr+3)*2+addr+len)&0xfffe));
+      operand= (u16_t)(((i8_t)rom->get(addr+3)*2+addr+len)&0xfffe);
+      parm_str= chars("", "%s,0x%04lx",
+		      get_bit_name(((code&0x0003)<<8) + rom->get(addr+2)).c_str(),
+		      operand);
+      addr_name(operand, rom, &parm_str);
     break;
     case DATA4:
-      sprintf(parm_str, "#0x%02x", code&0x0f);
+      parm_str= chars("", "#0x%02x", code&0x0f);
       break;
     case ADDR24 :
-      sprintf(parm_str, "0x%06x",
-             (rom->get(addr+3)<<16) +
-             (rom->get(addr+1)<<8) +
-             rom->get(addr+2));
+      operand= (u32_t)((rom->get(addr+3)<<16) +
+                       (rom->get(addr+1)<<8) +
+                       rom->get(addr+2));
+      parm_str= chars("", "0x%06x", operand);
+      addr_name(operand, rom, &parm_str);
       break;
     break;
     case REG_REL8 :
-      sprintf(parm_str, "%s,0x%04lx",
-	      reg_strs[(code>>4) & 0xf],
-	      (long)(((signed char)rom->get(addr+2)*2+addr+len)&0xfffe));
+      operand= (u16_t)(((i8_t)rom->get(addr+2)*2+addr+len)&0xfffe);
+      parm_str= chars("", "%s,0x%04lx",
+              reg_strs[(code>>4) & 0xf],
+              operand);
+      addr_name(operand, rom, &parm_str);
     break;
     case DIRECT_REL8 :
-      sprintf(parm_str, "%s,0x%04lx",
-	      get_dir_name(((code&0x07)<<8) +
-			   rom->get(addr+2)),
-	      (long)(((signed char)rom->get(addr+2)*2+addr+len)&0xfffe));
+      operand= (u16_t)(((i8_t)rom->get(addr+2)*2+addr+len)&0xfffe);
+      parm_str= chars("", "%s,0x%04lx",
+		      get_dir_name(((code&0x07)<<8) + rom->get(addr+2)).c_str(),
+		      operand);
+      addr_name(operand, rom, &parm_str);
     break;
     case REG_USP:
-      sprintf(parm_str, "REG_USP");
+      parm_str= chars("", "REG_USP");
     break;
     case USP_REG:
-      sprintf(parm_str, "USP_REG");
+      parm_str= chars("", "USP_REG");
     break;
     case REL8 :
-      sprintf(parm_str, "0x%04lx",
-	      (long)(((signed char)rom->get(addr+1)*2+addr+len)&0xfffe));
-    break;
-    case REL16 :
-      sprintf(parm_str, "0x%04lx",
-	      (long)(((signed short)((rom->get(addr+1)<<8) + rom->get(addr+2))*2+addr+len)&0xfffe));
+      operand= (u16_t)(((signed char)rom->get(addr+1)*2+addr+len)&0xfffe);
+      parm_str= chars("", "0x%04lx", operand);
+      addr_name(operand, rom, &parm_str);
+      break;
+  case REL16 :
+    operand= (u16_t)(((i8_t)((rom->get(addr+1)<<8) + rom->get(addr+2))*2+addr+len)&0xfffe);
+    parm_str= chars("", "0x%04lx", operand);
+    addr_name(operand, rom, &parm_str);
     break;
 
     case RLIST : {
-      /* TODO: the list should be comma reperated
+      /* TODO: the list should be comma separated
 	 and maybe for POP the list should be reversed */
       unsigned char rlist=code&0xff;
-      parm_str[0]='\0';
       if (code&0x0800) { // word list
 	if (code&0x4000) { // R8-R15
-	  if (rlist&0x80) strcat (parm_str, "R15 ");
-	  if (rlist&0x40) strcat (parm_str, "R14");
-	  if (rlist&0x20) strcat (parm_str, "R13 ");
-	  if (rlist&0x10) strcat (parm_str, "R12 ");
-	  if (rlist&0x08) strcat (parm_str, "R11 ");
-	  if (rlist&0x04) strcat (parm_str, "R10 ");
-	  if (rlist&0x02) strcat (parm_str, "R9 ");
-	  if (rlist&0x01) strcat (parm_str, "R8 ");
+	  if (rlist&0x80) parm_str+= "R15 ";
+	  if (rlist&0x40) parm_str+= "R14 ";
+	  if (rlist&0x20) parm_str+= "R13 ";
+	  if (rlist&0x10) parm_str+= "R12 ";
+	  if (rlist&0x08) parm_str+= "R11 ";
+	  if (rlist&0x04) parm_str+= "R10 ";
+	  if (rlist&0x02) parm_str+= "R9 ";
+	  if (rlist&0x01) parm_str+= "R8 ";
 	} else { // R7-R0
-	  if (rlist&0x80) strcat (parm_str, "R7 ");
-	  if (rlist&0x40) strcat (parm_str, "R6 ");
-	  if (rlist&0x20) strcat (parm_str, "R5 ");
-	  if (rlist&0x10) strcat (parm_str, "R4 ");
-	  if (rlist&0x08) strcat (parm_str, "R3 ");
-	  if (rlist&0x04) strcat (parm_str, "R2 ");
-	  if (rlist&0x02) strcat (parm_str, "R1 ");
-	  if (rlist&0x01) strcat (parm_str, "R0 ");
+	  if (rlist&0x80) parm_str+= "R7 ";
+	  if (rlist&0x40) parm_str+= "R6 ";
+	  if (rlist&0x20) parm_str+= "R5 ";
+	  if (rlist&0x10) parm_str+= "R4 ";
+	  if (rlist&0x08) parm_str+= "R3 ";
+	  if (rlist&0x04) parm_str+= "R2 ";
+	  if (rlist&0x02) parm_str+= "R1 ";
+	  if (rlist&0x01) parm_str+= "R0 ";
 	}
       } else { // byte list
 	if (code&0x4000) { //R7h-R4l
-	  if (rlist&0x80) strcat (parm_str, "R7h ");
-	  if (rlist&0x40) strcat (parm_str, "R7l ");
-	  if (rlist&0x20) strcat (parm_str, "R6h ");
-	  if (rlist&0x10) strcat (parm_str, "R6l ");
-	  if (rlist&0x08) strcat (parm_str, "R5h ");
-	  if (rlist&0x04) strcat (parm_str, "R5l ");
-	  if (rlist&0x02) strcat (parm_str, "R4h ");
-	  if (rlist&0x01) strcat (parm_str, "R4l ");
+	  if (rlist&0x80) parm_str+= "R7h ";
+	  if (rlist&0x40) parm_str+= "R7l ";
+	  if (rlist&0x20) parm_str+= "R6h ";
+	  if (rlist&0x10) parm_str+= "R6l ";
+	  if (rlist&0x08) parm_str+= "R5h ";
+	  if (rlist&0x04) parm_str+= "R5l ";
+	  if (rlist&0x02) parm_str+= "R4h ";
+	  if (rlist&0x01) parm_str+= "R4l ";
 	} else { // R3h-R0l
-	  if (rlist&0x80) strcat (parm_str, "R3h ");
-	  if (rlist&0x40) strcat (parm_str, "R3l ");
-	  if (rlist&0x20) strcat (parm_str, "R2h ");
-	  if (rlist&0x10) strcat (parm_str, "R2l ");
-	  if (rlist&0x08) strcat (parm_str, "R1h ");
-	  if (rlist&0x04) strcat (parm_str, "R1l ");
-	  if (rlist&0x02) strcat (parm_str, "R0h ");
-	  if (rlist&0x01) strcat (parm_str, "R0l ");
+	  if (rlist&0x80) parm_str+= "R3h ";
+	  if (rlist&0x40) parm_str+= "R3l ";
+	  if (rlist&0x20) parm_str+= "R2h ";
+	  if (rlist&0x10) parm_str+= "R2l ";
+	  if (rlist&0x08) parm_str+= "R1h ";
+	  if (rlist&0x04) parm_str+= "R1l ";
+	  if (rlist&0x02) parm_str+= "R0h ";
+	  if (rlist&0x01) parm_str+= "R0l ";
 	}
       }
     }
     break;
 
     case REG_DIRECT_REL8 :
-      sprintf(parm_str, "%s,%s,0x%02x",
-              reg_strs[((code >> 4) & 0xf)],
-              get_dir_name(((code & 0x7) << 8) +
-                           rom->get(addr+immed_offset)),
-              ((signed char) rom->get(addr+immed_offset+1) * 2) & 0xfffe );
+      parm_str= chars("", "%s,%s,0x%02x",
+		      reg_strs[((code >> 4) & 0xf)],
+		      get_dir_name(((code & 0x7) << 8) +
+				   rom->get(addr+immed_offset)).c_str(),
+		      ((signed char) rom->get(addr+immed_offset+1) * 2) & 0xfffe );
     break;
     case REG_DATA8_REL8 :
-      sprintf(parm_str, "%s,#0x%02x,0x%02x",
-              reg_strs[((code >> 4) & 0xf)],
-              rom->get(addr+immed_offset+1),
-              ((signed char)rom->get(addr+immed_offset) * 2) & 0xfffe );
+      parm_str= chars("", "%s,#0x%02x,0x%02x",
+		      reg_strs[((code >> 4) & 0xf)],
+		      rom->get(addr+immed_offset+1),
+		      ((signed char)rom->get(addr+immed_offset) * 2) & 0xfffe );
     break;
     case REG_DATA16_REL8 :
-      sprintf(parm_str, "%s,#0x%04x,0x%02x",
-              w_reg_strs[(code >> 4) & 0xf],
-              rom->get(addr+immed_offset+2) +
-                 (rom->get(addr+immed_offset+1)<<8),
-              ((signed char)rom->get(addr+immed_offset) * 2) & 0xfffe );
-    break;
-    case IREG_DATA8_REL8 :
-      sprintf(parm_str, "[%s],#0x%02x,0x%02x",
+      parm_str= chars("", "%s,#0x%04x,0x%02x",
+		      w_reg_strs[(code >> 4) & 0xf],
+		      rom->get(addr+immed_offset+2) +
+		      (rom->get(addr+immed_offset+1)<<8),
+		      ((signed char)rom->get(addr+immed_offset) * 2) & 0xfffe );
+      break;
+  case IREG_DATA8_REL8 :
+    parm_str= chars("", "[%s],#0x%02x,0x%02x",
               reg_strs[((code >> 4) & 0x7)],
-              rom->get(addr+immed_offset+1),
-              ((signed char)rom->get(addr+immed_offset) * 2) & 0xfffe );
-    break;
-    case IREG_DATA16_REL8 :
-      sprintf(parm_str, "[%s],#0x%04x,0x%02x",
-              w_reg_strs[(code >> 4) & 0x7],
-              rom->get(addr+immed_offset+2) +
-	        (rom->get(addr+immed_offset+1)<<8),
-              ((signed char)rom->get(addr+immed_offset) * 2) & 0xfffe );
-    break;
-
-    case A_APLUSDPTR :
-      strcpy(parm_str, "A, [A+DPTR]");
-    break;
-
-    case A_APLUSPC :
-      strcpy(parm_str, "A, [A+PC]");
+		    rom->get(addr+immed_offset+1),
+		    ((signed char)rom->get(addr+immed_offset) * 2) & 0xfffe );
     break;
-
-    case REG_REGOFF8 :
-      sprintf(parm_str, "%s,%s+0x%02x",
-              w_reg_strs[(code >> 4) & 0x7],
-              w_reg_strs[code & 0x7],
-              rom->get(addr+immed_offset));
-      break;
-
-    case REG_REGOFF16 :
-      sprintf(parm_str, "%s,%s+0x%02x",
-              w_reg_strs[(code >> 4) & 0x7],
-              w_reg_strs[code & 0x7],
-              rom->get(addr+immed_offset+1) +
-	        (rom->get(addr+immed_offset+0)<<8));
-      break;
-
-    case A_PLUSDPTR :
-      strcpy(parm_str, "[A+DPTR]");
-      break;
-
-    case IIREG :
-      sprintf(parm_str, "[[%s]]",
-              w_reg_strs[(code & 0x7)]);
-      break;
-
-    default:
-      strcpy(parm_str, "???");
+  case IREG_DATA16_REL8 :
+    parm_str= chars("", "[%s],#0x%04x,0x%02x",
+		    w_reg_strs[(code >> 4) & 0x7],
+		    rom->get(addr+immed_offset+2) +
+		    (rom->get(addr+immed_offset+1)<<8),
+		    ((signed char)rom->get(addr+immed_offset) * 2) & 0xfffe );
+    break;
+    
+  case A_APLUSDPTR :
+    parm_str= chars("", "A, [A+DPTR]");
+    break;
+    
+  case A_APLUSPC :
+    parm_str= chars("", "A, [A+PC]");
+    break;
+    
+  case REG_REGOFF8 :
+    operand= rom->get(addr+immed_offset);
+    parm_str= chars("", "%s,%s+0x%02x",
+		    w_reg_strs[(code >> 4) & 0x7],
+		    w_reg_strs[code & 0x7],
+		    operand);
+    addr_name(operand, rom, &parm_str);
+    break;
+    
+  case REG_REGOFF16 :
+    operand= rom->get(addr+immed_offset+1) +
+      (rom->get(addr+immed_offset+0)<<8);
+    parm_str= chars("", "%s,%s+0x%02x",
+		    w_reg_strs[(code >> 4) & 0x7],
+		    w_reg_strs[code & 0x7],
+		    operand);
+    addr_name(operand, rom, &parm_str);
+    break;
+    
+  case A_PLUSDPTR :
+    parm_str= chars("", "[A+DPTR]");
+    break;
+    
+  case IIREG :
+    parm_str= chars("", "[[%s]]",
+		    w_reg_strs[(code & 0x7)]);
+    break;
+    
+  default:
+    parm_str= chars("???");
     break;
   }
-
-  sprintf(work, "%s %s",
-          op_mnemonic_str[ mnemonic ],
-          parm_str);
-
-  p= strchr(work, ' ');
-  if (!p)
-    {
-      buf= strdup(work);
-      return(buf);
-    }
-  if (sep == NULL)
-    buf= (char *)malloc(6+strlen(p)+1);
-  else
-    buf= (char *)malloc((p-work)+strlen(sep)+strlen(p)+1);
-
-  for (p= work, b= buf; *p != ' '; p++, b++)
-    *b= *p;
-  p++;
-  *b= '\0';
-  if (sep == NULL)
-    {
-      while (strlen(buf) < 6)
-        strcat(buf, " ");
-    }
-  else
-    strcat(buf, sep);
-  strcat(buf, p);
-  return(buf);
+  
+  work= op_mnemonic_str[ mnemonic ];
+  while (work.len() < 6) work.append(' ');
+  work+= parm_str;
+  
+  return strdup(work.c_str());
 }
 
 /*--------------------------------------------------------------------
@@ -964,6 +981,7 @@
   unsigned char flags;
 
   flags = get_psw();
+  con->dd_color("answer");
   con->dd_printf("CA---VNZ | ", flags);
   con->dd_printf("R0:%04x R1:%04x R2:%04x R3:%04x\n",
                  reg2(0), reg2(1), reg2(2), reg2(3));
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/xa.src/xacl.h sdcc-4.2.0+dfsg/sim/ucsim/xa.src/xacl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/xa.src/xacl.h	2016-07-26 21:10:26.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/xa.src/xacl.h	2021-05-07 16:21:16.000000000 +0000
@@ -57,7 +57,7 @@
 public:
   cl_xa(class cl_sim *asim);
   virtual int init(void);
-  virtual char *id_string(void);
+  virtual const char *id_string(void);
 
   //virtual class cl_m *mk_mem(enum mem_class type, char *class_name);
   //virtual t_addr get_mem_size(enum mem_class type);
@@ -68,8 +68,8 @@
 
   virtual struct name_entry *sfr_tbl(void);
   virtual struct name_entry *bit_tbl(void);
-  virtual char *get_dir_name(short);
-  virtual char *get_bit_name(short);
+  virtual chars get_dir_name(short);
+  virtual chars get_bit_name(short);
 
   virtual int inst_length(t_addr addr);
   virtual int inst_branch(t_addr addr);
@@ -82,7 +82,7 @@
                        int *parms,
                        int *mnemonic);
 
-  virtual char *disass(t_addr addr, const char *sep);
+  virtual char *disass(t_addr addr);
   virtual void print_regs(class cl_console_base *con);
 
   virtual int exec_inst(void);
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/z80.src/clean.mk sdcc-4.2.0+dfsg/sim/ucsim/z80.src/clean.mk
--- sdcc-4.0.0+dfsg/sim/ucsim/z80.src/clean.mk	2003-04-24 21:06:59.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/z80.src/clean.mk	2021-09-19 19:38:05.000000000 +0000
@@ -3,7 +3,9 @@
 clean:
 	rm -f *core *[%~] *.[oa]
 	rm -f .[a-z]*~
-	rm -f sz80$(EXEEXT)
+	rm -f sz80 sz80.exe
+	rm -f ucsim_z80 ucsim_z80.exe
+	$(MAKE) -C test -f clean.mk clean
 
 
 # Deleting all files created by configuring or building the program
@@ -11,6 +13,7 @@
 distclean: clean
 	rm -f config.cache config.log config.status
 	rm -f Makefile *.dep
+	$(MAKE) -C test -f clean.mk distclean
 
 
 # Like clean but some files may still exist
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/z80.src/ez80.cc sdcc-4.2.0+dfsg/sim/ucsim/z80.src/ez80.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/z80.src/ez80.cc	2019-01-31 06:06:03.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/z80.src/ez80.cc	2020-08-25 12:30:39.000000000 +0000
@@ -25,8 +25,6 @@
 02111-1307, USA. */
 /*@1@*/
 
-#include 
-
 #include "z80mac.h"
 
 #include "ez80cl.h"
@@ -201,10 +199,10 @@
   return cl_z80::init();
 }
 
-char *
+const char *
 cl_ez80::id_string(void)
 {
-  return ((char*)"EZ80");
+  return ("EZ80");
 }
 
 
@@ -323,7 +321,7 @@
 int
 cl_ez80::inst_ed_ez80(t_mem code)
 {
-  int8_t d;
+  i8_t d;
   
   switch (code)
     {
@@ -430,7 +428,7 @@
 int
 cl_ez80::inst_dd_spec(t_mem code)
 {
-  int8_t d;
+  i8_t d;
   
   switch (code)
     {
@@ -646,7 +644,7 @@
 int
 cl_ez80::inst_fd_spec(t_mem code)
 {
-  int8_t d;
+  i8_t d;
   
   switch (code)
     {
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/z80.src/ez80cl.h sdcc-4.2.0+dfsg/sim/ucsim/z80.src/ez80cl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/z80.src/ez80cl.h	2019-01-07 14:30:39.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/z80.src/ez80cl.h	2020-08-22 10:25:08.000000000 +0000
@@ -36,7 +36,7 @@
  public:
   cl_ez80(struct cpu_entry *Itype, class cl_sim *asim);
   virtual int init(void);
-  virtual char *id_string(void);
+  virtual const char *id_string(void);
   virtual const char *get_disasm_info(t_addr addr,
 				      int *ret_len,
 				      int *ret_branch,
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/z80.src/gb80.cc sdcc-4.2.0+dfsg/sim/ucsim/z80.src/gb80.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/z80.src/gb80.cc	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/z80.src/gb80.cc	2021-05-06 08:57:13.000000000 +0000
@@ -0,0 +1,678 @@
+/*
+ * Simulator of microcontrollers (z80.src/gb80.cc)
+ *
+ * Copyright (C) 2021,21 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+//#include "ddconfig.h"
+
+#include 
+#include 
+#include 
+#include 
+
+// prj
+//#include "pobjcl.h"
+
+// sim
+#include "simcl.h"
+
+// local
+//#include "z80cl.h"
+#include "gb80cl.h"
+#include "glob.h"
+
+#define uint32 t_addr
+#define uint8 unsigned char
+
+/*******************************************************************/
+
+lr35902_memory::lr35902_memory( cl_uc &uc_parent_ref ):uc_r(uc_parent_ref) { }
+
+cl_gb80::cl_gb80(struct cpu_entry *Itype, class cl_sim *asim):
+  cl_z80(Itype, asim), mem(*this)
+{
+  type= Itype;
+  BIT_C= 0x10;
+  BIT_A= 0x20;
+  BIT_N= 0x40;
+  BIT_Z= 0x80;
+  BIT_ALL= (BIT_C |BIT_N |BIT_A |BIT_Z);
+  BIT_P= 0;
+  BIT_S= 0;
+  regs.raf.F= 0;
+  regs.ralt_af.aF= 0;
+}
+
+int
+cl_gb80::init(void)
+{
+  cl_uc::init(); /* Memories now exist */
+
+  //rom= address_space(MEM_ROM_ID);  // code goes here...
+  
+  //  ram= mem(MEM_XRAM);
+  //ram= address_space(MEM_XRAM_ID);  // data goes here...
+  
+  
+  // zero out ram(this is assumed in regression tests)
+  for (int i=0xA000; i<0xFF80; i++) {
+    ram->set((t_addr) i, 0);
+  }
+  
+  return(0);
+}
+
+const char *
+cl_gb80::id_string(void)
+{
+  return("GB80");
+}
+
+
+void
+cl_gb80::mk_hw_elements(void)
+{
+  //class cl_base *o;
+  cl_uc::mk_hw_elements();
+}
+
+void lr35902_memory::init(void) {
+  cl_address_space *as_rom;
+  cl_address_space *as_ram;
+  
+  as_rom = new cl_address_space("rom"/*MEM_ROM_ID*/,
+				lr35902_rom_start, lr35902_rom_size, 8);
+  as_rom->init();
+  uc_r.address_spaces->add(as_rom);
+  rom = as_rom;
+  
+  as_ram = new cl_address_space(MEM_XRAM_ID,
+				lr35902_ram_start, lr35902_ram_size, 8);
+  as_ram->init();
+  uc_r.address_spaces->add(as_ram);
+  ram = as_ram;
+}
+
+void
+cl_gb80::make_memories(void)
+{
+  mem.init( );
+  rom= mem.rom;
+  ram= mem.ram;
+  
+  regs8= new cl_address_space("regs8", 0, 16, 8);
+  regs8->init();
+  regs8->get_cell(0)->decode((t_mem*)®s.raf.A);
+  regs8->get_cell(1)->decode((t_mem*)®s.raf.F);
+  regs8->get_cell(2)->decode((t_mem*)®s.bc.h);
+  regs8->get_cell(3)->decode((t_mem*)®s.bc.l);
+  regs8->get_cell(4)->decode((t_mem*)®s.de.h);
+  regs8->get_cell(5)->decode((t_mem*)®s.de.l);
+  regs8->get_cell(6)->decode((t_mem*)®s.hl.h);
+  regs8->get_cell(7)->decode((t_mem*)®s.hl.l);
+
+  regs8->get_cell(8)->decode((t_mem*)®s.ralt_af.aA);
+  regs8->get_cell(9)->decode((t_mem*)®s.ralt_af.aF);
+  regs8->get_cell(10)->decode((t_mem*)®s.a_bc.h);
+  regs8->get_cell(11)->decode((t_mem*)®s.a_bc.l);
+  regs8->get_cell(12)->decode((t_mem*)®s.a_de.h);
+  regs8->get_cell(13)->decode((t_mem*)®s.a_de.l);
+  regs8->get_cell(14)->decode((t_mem*)®s.a_hl.h);
+  regs8->get_cell(15)->decode((t_mem*)®s.a_hl.l);
+
+  regs16= new cl_address_space("regs16", 0, 11, 16);
+  regs16->init();
+
+  regs16->get_cell(0)->decode((t_mem*)®s.AF);
+  regs16->get_cell(1)->decode((t_mem*)®s.BC);
+  regs16->get_cell(2)->decode((t_mem*)®s.DE);
+  regs16->get_cell(3)->decode((t_mem*)®s.HL);
+  regs16->get_cell(4)->decode((t_mem*)®s.IX);
+  regs16->get_cell(5)->decode((t_mem*)®s.IY);
+  regs16->get_cell(6)->decode((t_mem*)®s.SP);
+  regs16->get_cell(7)->decode((t_mem*)®s.aAF);
+  regs16->get_cell(8)->decode((t_mem*)®s.aBC);
+  regs16->get_cell(9)->decode((t_mem*)®s.aDE);
+  regs16->get_cell(10)->decode((t_mem*)®s.aHL);
+
+  address_spaces->add(regs8);
+  address_spaces->add(regs16);
+
+  class cl_var *v;
+  vars->add(v= new cl_var("A", regs8, 0, ""));
+  v->init();
+  vars->add(v= new cl_var("F", regs8, 1, ""));
+  v->init();
+  vars->add(v= new cl_var("B", regs8, 2, ""));
+  v->init();
+  vars->add(v= new cl_var("C", regs8, 3, ""));
+  v->init();
+  vars->add(v= new cl_var("D", regs8, 4, ""));
+  v->init();
+  vars->add(v= new cl_var("E", regs8, 5, ""));
+  v->init();
+  vars->add(v= new cl_var("H", regs8, 6, ""));
+  v->init();
+  vars->add(v= new cl_var("L", regs8, 7, ""));
+  v->init();
+
+  vars->add(v= new cl_var("ALT_A", regs8, 8, ""));
+  v->init();
+  vars->add(v= new cl_var("ALT_F", regs8, 9, ""));
+  v->init();
+  vars->add(v= new cl_var("ALT_B", regs8, 10, ""));
+  v->init();
+  vars->add(v= new cl_var("ALT_C", regs8, 11, ""));
+  v->init();
+  vars->add(v= new cl_var("ALT_D", regs8, 12, ""));
+  v->init();
+  vars->add(v= new cl_var("ALT_E", regs8, 13, ""));
+  v->init();
+  vars->add(v= new cl_var("ALT_H", regs8, 14, ""));
+  v->init();
+  vars->add(v= new cl_var("ALT_L", regs8, 15, ""));
+  v->init();
+
+  vars->add(v= new cl_var("AF", regs16, 0, ""));
+  v->init();
+  vars->add(v= new cl_var("BC", regs16, 1, ""));
+  v->init();
+  vars->add(v= new cl_var("DE", regs16, 2, ""));
+  v->init();
+  vars->add(v= new cl_var("HL", regs16, 3, ""));
+  v->init();
+  vars->add(v= new cl_var("IX", regs16, 4, ""));
+  v->init();
+  vars->add(v= new cl_var("IY", regs16, 5, ""));
+  v->init();
+  vars->add(v= new cl_var("SP", regs16, 6, ""));
+  v->init();
+  vars->add(v= new cl_var("ALT_AF", regs16, 7, ""));
+  v->init();
+  vars->add(v= new cl_var("ALT_BC", regs16, 8, ""));
+  v->init();
+  vars->add(v= new cl_var("ALT_DE", regs16, 9, ""));
+  v->init();
+  vars->add(v= new cl_var("ALT_HL", regs16, 10, ""));
+  v->init();
+}
+
+void cl_gb80::store1( u16_t addr, t_mem val ) {
+  mem.store1( addr, val );
+}
+
+void cl_gb80::store2( u16_t addr, u16_t val ) {
+  mem.store2( addr, val );
+}
+
+u8_t  cl_gb80::get1( u16_t addr ) {
+  return mem.get1( addr );
+}
+
+u16_t  cl_gb80::get2( u16_t addr ) {
+  return mem.get2( addr );
+}
+
+void lr35902_memory::store1( u16_t addr, t_mem val ) {
+  if (addr < lr35902_ram_start) {
+    /* flag illegal operation ? */
+    return;
+  }
+  
+  if ((addr- lr35902_ram_start) < lr35902_ram_size) {
+    ram->write(addr, val);
+  }
+}
+
+void lr35902_memory::store2( u16_t addr, u16_t val ) {
+  store1(addr,   val & 0xff);
+  store1(addr+1, (val >> 8) & 0xff);
+}
+
+u8_t  lr35902_memory::get1( u16_t addr ) {
+  if (addr < lr35902_rom_size) {
+    return rom->read(addr);    
+  }
+  
+  if (addr < lr35902_ram_start) {
+    /* flag illegal operation ? */
+    return (addr & 0xff);
+  }
+  
+  if ((addr-lr35902_ram_start) < lr35902_ram_size) {
+    return ram->read(addr);
+  }
+  
+  return (addr & 0xff);
+}
+
+u16_t  lr35902_memory::get2( u16_t addr ) {
+  u16_t  l, h;
+  
+  l = get1(addr  );
+  h = get1(addr+1);
+  
+  return (h << 8) | l;
+}
+
+/*
+ * Help command interpreter
+ */
+
+struct dis_entry *
+cl_gb80::dis_tbl(void)
+{
+  return(disass_gb80);
+}
+
+
+int
+cl_gb80::inst_length(t_addr addr)
+{
+  int len = 0;
+
+  get_disasm_info(addr, &len, NULL, NULL);
+
+  return len;
+}
+
+int
+cl_gb80::inst_branch(t_addr addr)
+{
+  int b;
+
+  get_disasm_info(addr, NULL, &b, NULL);
+
+  return b;
+}
+
+int
+cl_gb80::longest_inst(void)
+{
+  return 4;
+}
+
+
+const char *
+cl_gb80::get_disasm_info(t_addr addr,
+                        int *ret_len,
+                        int *ret_branch,
+                        int *immed_offset)
+{
+  const char *b = NULL;
+  uint code;
+  int len = 0;
+  int immed_n = 0;
+  int i;
+  int start_addr = addr;
+  struct dis_entry *dis_e;
+
+  code= rom->get(addr++);
+  dis_e = NULL;
+
+  switch(code) {
+    case 0xcb:  /* ESC code to lots of op-codes, all 2-byte */
+      code= rom->get(addr++);
+      i= 0;
+      while ((code & disass_gb80_cb[i].mask) != disass_gb80_cb[i].code &&
+        disass_gb80_cb[i].mnemonic)
+        i++;
+      dis_e = &disass_gb80_cb[i];
+      b= disass_gb80_cb[i].mnemonic;
+      if (b != NULL)
+        len += (disass_gb80_cb[i].length + 1);
+    break;
+
+    default:
+      i= 0;
+      while ((code & disass_gb80[i].mask) != disass_gb80[i].code &&
+             disass_gb80[i].mnemonic)
+        i++;
+      dis_e = &disass_gb80[i];
+      b= disass_gb80[i].mnemonic;
+      if (b != NULL)
+        len += (disass_gb80[i].length);
+    break;
+  }
+
+
+  if (ret_branch) {
+    *ret_branch = dis_e->branch;
+  }
+
+  if (immed_offset) {
+    if (immed_n > 0)
+         *immed_offset = immed_n;
+    else *immed_offset = (addr - start_addr);
+  }
+
+  if (len == 0)
+    len = 1;
+
+  if (ret_len)
+    *ret_len = len;
+
+  return b;
+}
+
+char *
+cl_gb80::disass(t_addr addr)
+{
+  chars work, temp;
+  const char *b;
+  int len = 0;
+  int immed_offset = 0;
+  bool first= true;
+  
+  work= "";
+  b = get_disasm_info(addr, &len, NULL, &immed_offset);
+  if (b == NULL)
+    {
+      return strdup("UNKNOWN/INVALID");
+    }
+
+  while (*b)
+    {
+      if ((*b == ' ') && first)
+	{
+	  first= false;
+	  while (work.len() < 6) work.append(' ');
+	}
+      if (*b == '%')
+        {
+	  temp= "";
+          b++;
+          switch (*(b++))
+            {
+            case 'd': // d    jump relative target, signed? byte immediate operand
+              temp.format("#%d", (char)rom->get(addr+immed_offset));
+              ++immed_offset;
+              break;
+            case 'w': // w    word immediate operand
+              temp.format("#0x%04x",
+                 (uint)((rom->get(addr+immed_offset)) |
+                        (rom->get(addr+immed_offset+1)<<8)) );
+              ++immed_offset;
+              ++immed_offset;
+              break;
+            case 'b': // b    byte immediate operand
+              temp.format("#0x%02x", (uint)rom->get(addr+immed_offset));
+              ++immed_offset;
+              break;
+            default:
+              temp= "?";
+              break;
+            }
+	  work+= temp;
+        }
+      else
+        work+= *(b++);
+    }
+  return strdup(work.c_str());
+}
+
+
+void
+cl_gb80::print_regs(class cl_console_base *con)
+{
+  con->dd_color("answer");
+  con->dd_printf("ZNHC---  Flags= 0x%02x %3d %c  ",
+                 regs.raf.F, regs.raf.F, isprint(regs.raf.F)?regs.raf.F:'.');
+  con->dd_printf("A= 0x%02x %3d %c\n",
+                 regs.raf.A, regs.raf.A, isprint(regs.raf.A)?regs.raf.A:'.');
+  con->dd_printf("%c%c%c%c%c%c%c%c\n",
+                 (regs.raf.F&BIT_Z)?'1':'0',
+                 (regs.raf.F&BIT_N)?'1':'0',
+                 (regs.raf.F&BIT_A)?'1':'0',
+                 (regs.raf.F&BIT_C)?'1':'0',
+                 (regs.raf.F& 0x08)?'1':'0',
+                 (regs.raf.F& 0x04)?'1':'0',
+                 (regs.raf.F& 0x03)?'1':'0',
+                 (regs.raf.F& 0x08)?'1':'0'
+		 );
+  con->dd_printf("BC= 0x%04x [BC]= %02x %3d %c  ",
+                 regs.BC, ram->get(regs.BC), ram->get(regs.BC),
+                 isprint(ram->get(regs.BC))?ram->get(regs.BC):'.');
+  con->dd_printf("DE= 0x%04x [DE]= %02x %3d %c  ",
+                 regs.DE, ram->get(regs.DE), ram->get(regs.DE),
+                 isprint(ram->get(regs.DE))?ram->get(regs.DE):'.');
+  con->dd_printf("HL= 0x%04x [HL]= %02x %3d %c\n",
+                 regs.HL, ram->get(regs.HL), ram->get(regs.HL),
+                 isprint(ram->get(regs.HL))?ram->get(regs.HL):'.');
+  con->dd_printf("SP= 0x%04x [SP]= %02x %3d %c\n",
+                 regs.SP, ram->get(regs.SP), ram->get(regs.SP),
+                 isprint(ram->get(regs.SP))?ram->get(regs.SP):'.');
+
+  print_disass(PC, con);
+}
+
+/*
+ * Execution
+ */
+
+int
+cl_gb80::exec_inst(void)
+{
+  t_mem code;
+
+  instPC= PC;
+
+  if (fetch(&code))
+    return(resBREAKPOINT);
+  tick(1);
+  switch (code)
+    {
+    case 0x00: return(inst_nop(code));
+    case 0x01: case 0x02: case 0x06: return(inst_ld(code));
+    case 0x03: case 0x04: return(inst_inc(code));
+    case 0x05: return(inst_dec(code));
+    case 0x07: {
+      int ret= (inst_rlca(code));
+      regs.raf.F&= ~(BIT_Z|BIT_A|BIT_N);
+      return ret;
+    }
+    case 0x08: return(inst_st_sp_abs(code));
+    case 0x09: return(inst_add(code));
+    case 0x0a: case 0x0e: return(inst_ld(code));
+    case 0x0b: case 0x0d: return(inst_dec(code));
+    case 0x0c: return(inst_inc(code));
+    case 0x0f: {
+      int ret= (inst_rrca(code));
+      regs.raf.F&= ~(BIT_Z|BIT_A|BIT_N);
+      return ret;
+    }
+
+    case 0x10: return(inst_stop0(code));
+    case 0x11: case 0x12: case 0x16: return(inst_ld(code));
+    case 0x13: case 0x14: return(inst_inc(code));
+    case 0x15: return(inst_dec(code));
+    case 0x17: {
+      int ret= (inst_rla(code));
+      regs.raf.F&= ~(BIT_Z|BIT_A|BIT_N);
+      return ret;
+    }
+    case 0x18: return(inst_jr(code));
+    case 0x19: return(inst_add(code));
+    case 0x1a: case 0x1e: return(inst_ld(code));
+    case 0x1b: case 0x1d: return(inst_dec(code));
+    case 0x1c: return(inst_inc(code));
+    case 0x1f: {
+      int ret= (inst_rra(code));
+      regs.raf.F&= ~(BIT_Z|BIT_A|BIT_N);
+      return ret;
+    }
+
+    case 0x20: return(inst_jr(code));
+    case 0x21: case 0x26: return(inst_ld(code));
+    case 0x22: return inst_ldi(code);
+    case 0x23: case 0x24: return(inst_inc(code));
+    case 0x25: return(inst_dec(code));
+    case 0x27: return(inst_daa(code));
+      
+    case 0x28: return(inst_jr(code));
+    case 0x29: return(inst_add(code));
+    case 0x2a: return(inst_ldi(code));
+    case 0x2b: case 0x2d: return(inst_dec(code));
+    case 0x2c: return(inst_inc(code));
+    case 0x2e: return(inst_ld(code));
+    case 0x2f: return(inst_cpl(code));
+
+    case 0x30: return(inst_jr(code));
+    case 0x31: case 0x36: return(inst_ld(code));
+    case 0x32: return(inst_ldd(code));
+    case 0x33: case 0x34: return(inst_inc(code));
+    case 0x35: return(inst_dec(code));
+    case 0x37: return(inst_scf(code));
+      
+    case 0x38: return(inst_jr(code));
+    case 0x39: return(inst_add(code));
+    case 0x3a: return inst_ldd(code);
+    case 0x3b: case 0x3d: return(inst_dec(code));
+    case 0x3c: return(inst_inc(code));
+    case 0x3e: return(inst_ld(code));
+    case 0x3f: return(inst_ccf(code));
+
+    case 0x40: case 0x41: case 0x42: case 0x43: case 0x44: case 0x45: case 0x46: case 0x47:
+    case 0x48: case 0x49: case 0x4a: case 0x4b: case 0x4c: case 0x4d: case 0x4e: case 0x4f:
+      return(inst_ld(code));
+
+    case 0x50: case 0x51: case 0x52: case 0x53: case 0x54: case 0x55: case 0x56: case 0x57:
+    case 0x58: case 0x59: case 0x5a: case 0x5b: case 0x5c: case 0x5d: case 0x5e: case 0x5f:
+      return(inst_ld(code));
+
+    case 0x60: case 0x61: case 0x62: case 0x63: case 0x64: case 0x65: case 0x66: case 0x67:
+    case 0x68: case 0x69: case 0x6a: case 0x6b: case 0x6c: case 0x6d: case 0x6e: case 0x6f:
+      return(inst_ld(code));
+
+    case 0x70: case 0x71: case 0x72: case 0x73: case 0x74: case 0x75: case 0x77:
+    case 0x78: case 0x79: case 0x7a: case 0x7b: case 0x7c: case 0x7d: case 0x7e: case 0x7f:
+      return(inst_ld(code));
+    case 0x76: return(inst_halt(code));
+
+    case 0x80: case 0x81: case 0x82: case 0x83: case 0x84: case 0x85: case 0x86: case 0x87:
+      return(inst_add(code));
+    case 0x88: case 0x89: case 0x8a: case 0x8b: case 0x8c: case 0x8d: case 0x8e: case 0x8f:
+      return(inst_adc(code));
+
+    case 0x90: case 0x91: case 0x92: case 0x93: case 0x94: case 0x95: case 0x96: case 0x97:
+      return(inst_sub(code));
+    case 0x98: case 0x99: case 0x9a: case 0x9b: case 0x9c: case 0x9d: case 0x9e: case 0x9f:
+      return(inst_sbc(code));
+
+    case 0xa0: case 0xa1: case 0xa2: case 0xa3: case 0xa4: case 0xa5: case 0xa6: case 0xa7:
+      return(inst_and(code));
+    case 0xa8: case 0xa9: case 0xaa: case 0xab: case 0xac: case 0xad: case 0xae: case 0xaf:
+      return(inst_xor(code));
+
+    case 0xb0: case 0xb1: case 0xb2: case 0xb3: case 0xb4: case 0xb5: case 0xb6: case 0xb7:
+      return(inst_or(code));
+    case 0xb8: case 0xb9: case 0xba: case 0xbb: case 0xbc: case 0xbd: case 0xbe: case 0xbf:
+      return(inst_cp(code));
+
+    case 0xc0: return(inst_ret(code));
+    case 0xc1: {
+      int ret= (inst_pop(code));
+      regs.raf.F&= 0xf0;
+      return ret;
+    }
+    case 0xc2: case 0xc3: return(inst_jp(code));
+    case 0xc4: return(inst_call(code));
+    case 0xc5: return(inst_push(code));
+    case 0xc6: return(inst_add(code));
+    case 0xc7: return(inst_rst(code));
+
+    case 0xc8: case 0xc9: return(inst_ret(code));
+    case 0xca: return(inst_jp(code));
+
+      /* CB escapes out to 2 byte opcodes(CB include), opcodes
+         to do register bit manipulations */
+    case 0xcb: return(inst_cb( ));
+    case 0xcc: case 0xcd: return(inst_call(code));
+    case 0xce: return(inst_adc(code));
+    case 0xcf: return(inst_rst(code));
+
+    case 0xd0: return(inst_ret(code));
+    case 0xd1: return(inst_pop(code));
+    case 0xd2: return(inst_jp(code));
+    case 0xd3: break;
+    case 0xd4: return(inst_call(code));
+    case 0xd5: return(inst_push(code));
+    case 0xd6: return(inst_sub(code));
+    case 0xd7: return(inst_rst(code));
+
+    case 0xd8: return(inst_ret(code));
+ case 0xd9: return(inst_reti(code));
+    case 0xda: return(inst_jp(code));
+    case 0xdb: break;
+    case 0xdc: return(inst_call(code));
+      
+ case 0xdd: break;  /* IX register doesn't exist on the GB80 */
+    case 0xde: return(inst_sbc(code));
+    case 0xdf: return(inst_rst(code));
+      
+      
+    case 0xe0: return(inst_ldh(code));
+    case 0xe1: return(inst_pop(code));
+    case 0xe2: return(inst_ldh(code));
+    case 0xe3:
+ case 0xe4: break;
+    case 0xe5: return(inst_push(code));
+    case 0xe6: return(inst_and(code));
+    case 0xe7: return(inst_rst(code));
+
+    case 0xe8: return(inst_add_sp_d(code));
+    case 0xe9: return(inst_jp(code));
+    case 0xea: return(inst_ld16(code));
+    case 0xeb:
+    case 0xec: case 0xed: break;
+    case 0xee: return(inst_xor(code));
+    case 0xef: return(inst_rst(code));
+      
+    case 0xf0: return(inst_ldh(code));
+    case 0xf1: return(inst_pop(code));
+ case 0xf2: return(inst_ldh(code));
+    case 0xf3: return(inst_di(code));
+    case 0xf4: break;
+    case 0xf5: return(inst_push(code));
+    case 0xf6: return(inst_or(code));
+    case 0xf7: return(inst_rst(code));
+
+    case 0xf8: return(inst_ldhl_sp(code));
+    case 0xf9: return(inst_ld(code));
+    case 0xfa: return(inst_ld16(code));
+    case 0xfb: return(inst_ei(code));
+    case 0xfc: 
+    case 0xfd: break;
+    case 0xfe: return(inst_cp(code));
+    case 0xff: return(inst_rst(code));
+    }
+
+  PC= rom->inc_address(PC, -1);
+
+  sim->stop(resINV_INST);
+  return(resINV_INST);
+}
+
+/* End of z80.src/gb80.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/z80.src/gb80cl.h sdcc-4.2.0+dfsg/sim/ucsim/z80.src/gb80cl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/z80.src/gb80cl.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/z80.src/gb80cl.h	2021-05-05 16:29:51.000000000 +0000
@@ -0,0 +1,123 @@
+/*
+ * Simulator of microcontrollers (z80.src/gb80cl.h)
+ *
+ * Copyright (C) 2021,21 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef GB80CL_HEADER
+#define GB80CL_HEADER
+
+
+#include "z80cl.h"
+
+class cl_gb80;
+
+const t_addr  lr35902_rom_start = 0x0000;
+const t_addr  lr35902_rom_size  = 0x6000;
+
+const t_addr  lr35902_ram_start = 0xA000;
+const t_addr  lr35902_ram_size  = 0x5F80;
+
+class lr35902_memory
+{
+ protected:
+  cl_uc  &uc_r;
+  
+ public:
+  cl_memory *rom;
+  cl_memory *ram;
+  
+  lr35902_memory( cl_uc &uc_p );
+  
+  virtual void init( void );
+  
+  
+  virtual void store1( u16_t addr, t_mem val );
+  virtual void store2( u16_t addr, u16_t val );
+  
+  virtual u8_t  get1( u16_t addr );
+  virtual u16_t  get2( u16_t addr );
+  
+  // fetch not included b/c it only uses the rom
+};
+
+
+class cl_gb80: public cl_z80
+{
+public:
+  lr35902_memory    mem;
+  
+public:
+  cl_gb80(struct cpu_entry *Itype, class cl_sim *asim);
+  virtual int init(void);
+  virtual const char *id_string(void);
+  
+  //virtual t_addr get_mem_size(enum mem_class type);
+  virtual void mk_hw_elements(void);
+  virtual void make_memories(void);
+  
+  virtual struct dis_entry *dis_tbl(void);
+  virtual int inst_length(t_addr addr);
+  virtual int inst_branch(t_addr addr);
+  virtual int longest_inst(void);
+  virtual char *disass(t_addr addr);
+  virtual void print_regs(class cl_console_base *con);
+
+  virtual int exec_inst(void);
+
+  virtual const char *get_disasm_info(t_addr addr,
+                        int *ret_len,
+                        int *ret_branch,
+                        int *immed_offset);
+  
+
+  // memory access altered to use the 'mem' object
+  virtual void store1( u16_t addr, t_mem val );
+  virtual void store2( u16_t addr, u16_t val );
+  
+  virtual u8_t  get1( u16_t addr );
+  virtual u16_t  get2( u16_t addr );
+  
+  
+  // see #include "instcl.h" for Z80 versions
+  /* instruction function that are add / modified from the Z80 versions */
+  virtual int inst_cb(void);
+  
+  virtual int inst_st_sp_abs(t_mem code);
+  virtual int inst_stop0    (t_mem code);
+  
+  virtual int inst_ldi   (t_mem code);
+  virtual int inst_ldd   (t_mem code);
+  virtual int inst_ldh   (t_mem code);
+  
+  virtual int inst_reti    (t_mem code);
+  virtual int inst_add_sp_d(t_mem code);
+  virtual int inst_ld16    (t_mem code);
+  virtual int inst_ldhl_sp (t_mem code);
+  
+};
+
+#endif /* GB80_CL */
+
+/* End of z80.src/gb80cl.h */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/z80.src/glob.cc sdcc-4.2.0+dfsg/sim/ucsim/z80.src/glob.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/z80.src/glob.cc	2016-11-13 20:24:15.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/z80.src/glob.cc	2021-03-18 13:53:28.000000000 +0000
@@ -402,6 +402,40 @@
 
 
 #ifndef R2K
+struct dis_entry disass_z80n_ed[]=
+  {
+   { 0x00a4, 0x00ff, ' ', 1, "LDIX" },
+   { 0x00a5, 0x00ff, ' ', 1, "LDWS" },
+   { 0x00b4, 0x00ff, ' ', 1, "LDIRX" },
+   { 0x00ac, 0x00ff, ' ', 1, "LDDX" },
+   { 0x00bc, 0x00ff, ' ', 1, "LDDRX" },
+   { 0x00b7, 0x00ff, ' ', 1, "LDPIRX" },
+   { 0x0090, 0x00ff, ' ', 1, "OUTINB" },
+   { 0x0030, 0x00ff, ' ', 1, "MUL" },
+   { 0x0031, 0x00ff, ' ', 1, "ADD HL,A" },
+   { 0x0032, 0x00ff, ' ', 1, "ADD DE,A" },
+   { 0x0033, 0x00ff, ' ', 1, "ADD BC,A" },
+   { 0x0034, 0x00ff, ' ', 3, "ADD HL,%w" },
+   { 0x0035, 0x00ff, ' ', 3, "ADD DE,%w" },
+   { 0x0036, 0x00ff, ' ', 3, "ADD BC,%w" },
+   { 0x0023, 0x00ff, ' ', 1, "SWAPNIB" },
+   { 0x0024, 0x00ff, ' ', 1, "MIRROR A" },
+   { 0x008a, 0x00ff, ' ', 3, "PUSH %W" },
+   { 0x0091, 0x00ff, ' ', 3, "NEXTREG %b,%b" },
+   { 0x0092, 0x00ff, ' ', 2, "NEXTREG %b,A" },
+   { 0x0093, 0x00ff, ' ', 1, "PIXELDN" },
+   { 0x0094, 0x00ff, ' ', 1, "PIXELAD" },
+   { 0x0095, 0x00ff, ' ', 1, "SETAE" },
+   { 0x0027, 0x00ff, ' ', 2, "TEST %b" },
+   { 0x0028, 0x00ff, ' ', 1, "BSLA DE,B" },
+   { 0x0029, 0x00ff, ' ', 1, "BSRA DE,B" },
+   { 0x002a, 0x00ff, ' ', 1, "BSRL DE,A" },
+   { 0x002b, 0x00ff, ' ', 1, "BSRF DE,A" },
+   { 0x002c, 0x00ff, ' ', 1, "BRLC DE,B" },
+   { 0x0098, 0x00ff, ' ', 1, "JP (C)" },
+   { 0, 0, 0, 0, NULL }
+};
+
 struct dis_entry disass_z80_ed[]= {
   { 0x0000, 0x00ff, ' ', 1, "RLC B" },
   { 0x0040, 0x00ff, ' ', 1, "IN B,(C)" },
@@ -441,7 +475,7 @@
   { 0x006B, 0x00ff, ' ', 1, "LD HL,(nnnn)" },
   { 0x006F, 0x00ff, ' ', 1, "RLD" },
   { 0x0070, 0x00ff, ' ', 1, "IN (C)" },
-  { 0x0071, 0x00ff, ' ', 1, " OUT (C),0" },
+  { 0x0071, 0x00ff, ' ', 1, "OUT (C),0" },
   { 0x0072, 0x00ff, ' ', 1, "SBC HL,SP" },
   { 0x0073, 0x00ff, ' ', 1, "LD (nnnn),SP" },
   { 0x0078, 0x00ff, ' ', 1, "IN A,(C)" },
@@ -511,11 +545,14 @@
   { 0x0061, 0x00ff, ' ', 1, "LD HL',DE" },
   { 0x0062, 0x00ff, ' ', 1, "SBC HL,HL" },
   { 0x0063, 0x00ff, ' ', 3, "LD (nnnn),HL" },
+  { 0x0064, 0x00ff, ' ', 1, "LDP (HL),HL" },
+  { 0x0065, 0x00ff, ' ', 3, "LDP (%w),HL" },
   { 0x0067, 0x00ff, ' ', 1, "LD XPC,A" },
   
   { 0x006A, 0x00ff, ' ', 1, "ADC HL,HL" },
   { 0x006B, 0x00ff, ' ', 3, "LD HL,(nnnn)" },
-  
+  { 0x006C, 0x00ff, ' ', 1, "LDP HL,(HL)" },
+  { 0x006D, 0x00ff, ' ', 3, "LDP HL,(%w)" },
   { 0x0072, 0x00ff, ' ', 1, "SBC HL,SP" },
   { 0x0073, 0x00ff, ' ', 3, "LD (nnnn),SP" },
   { 0x0076, 0x00ff, ' ', 1, "PUSH IP" },
@@ -830,15 +867,25 @@
   { 0x0061, 0x00ff, ' ', 1, "LD HX,C" },
   { 0x0062, 0x00ff, ' ', 1, "LD HX,D" },
   { 0x0063, 0x00ff, ' ', 1, "LD HX,E" },
+#ifndef R2K
   { 0x0064, 0x00ff, ' ', 1, "LD HX,HX" },
+#else
+  { 0x0064, 0x00ff, ' ', 1, "LDP (IX),HL" },
+#endif
+  { 0x0065, 0x00ff, ' ', 3, "LDP (%w),IX" },
   { 0x0066, 0x00ff, ' ', 2, "LD H,(IX+%d)" },
   { 0x0067, 0x00ff, ' ', 1, "LD HX,A" },
   { 0x0068, 0x00ff, ' ', 1, "LD LX,B" },
   { 0x0069, 0x00ff, ' ', 1, "LD LX,C" },
   { 0x006A, 0x00ff, ' ', 1, "LD LX,D" },
   { 0x006B, 0x00ff, ' ', 1, "LD LX,E" },
+#ifndef R2K
   { 0x006C, 0x00ff, ' ', 1, "LD LX,HX" },
   { 0x006D, 0x00ff, ' ', 1, "LD LX,LX" },
+#else
+  { 0x006C, 0x00ff, ' ', 1, "LDP HL,(IX)" },
+  { 0x006D, 0x00ff, ' ', 3, "LDP IX,(%w)" },
+#endif
   { 0x006E, 0x00ff, ' ', 2, "LD L,(IX+%d)" },
   { 0x006F, 0x00ff, ' ', 1, "LD LX,A" },
   { 0x0070, 0x00ff, ' ', 2, "LD (IX+%d),B" },
@@ -929,15 +976,25 @@
   { 0x0061, 0x00ff, ' ', 1, "LD HX,C" },
   { 0x0062, 0x00ff, ' ', 1, "LD HX,D" },
   { 0x0063, 0x00ff, ' ', 1, "LD HX,E" },
+#ifndef R2K
   { 0x0064, 0x00ff, ' ', 1, "LD HX,HX" },
+#else
+  { 0x0064, 0x00ff, ' ', 1, "LDP (IY),HL" },
+#endif
+  { 0x0065, 0x00ff, ' ', 3, "LDP (%w),IY" },
   { 0x0066, 0x00ff, ' ', 2, "LD H,(IY+%d)" },
   { 0x0067, 0x00ff, ' ', 1, "LD HX,A" },
   { 0x0068, 0x00ff, ' ', 1, "LD LX,B" },
   { 0x0069, 0x00ff, ' ', 1, "LD LX,C" },
   { 0x006A, 0x00ff, ' ', 1, "LD LX,D" },
   { 0x006B, 0x00ff, ' ', 1, "LD LX,E" },
+#ifndef R2K
   { 0x006C, 0x00ff, ' ', 1, "LD LX,HX" },
   { 0x006D, 0x00ff, ' ', 1, "LD LX,LX" },
+#else
+  { 0x006C, 0x00ff, ' ', 1, "LDP HL,(IY)" },
+  { 0x006D, 0x00ff, ' ', 3, "LDP IY,(%w)" },
+#endif
   { 0x006E, 0x00ff, ' ', 2, "LD L,(IY+%d)" },
   { 0x006F, 0x00ff, ' ', 1, "LD LX,A" },
   { 0x0070, 0x00ff, ' ', 2, "LD (IY+%d),B" },
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/z80.src/glob_gb80.cc sdcc-4.2.0+dfsg/sim/ucsim/z80.src/glob_gb80.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/z80.src/glob_gb80.cc	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/z80.src/glob_gb80.cc	2021-05-05 16:29:51.000000000 +0000
@@ -0,0 +1,614 @@
+/*
+ * Disassembly table for LR35902, a Z-80 derivative used
+ * by the Gameboy (glob_lr35902.cc)
+ *
+ */
+/* Derived from z80 glob.cc by Leland Morrison 2011 */
+
+/* This file is part of microcontroller simulator: ucsim.
+   
+   UCSIM is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2 of the License, or
+   (at your option) any later version.
+   
+   UCSIM is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+   
+   You should have received a copy of the GNU General Public License
+   along with UCSIM; see the file COPYING.  If not, write to the Free
+   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+   02111-1307, USA. 
+*/
+/*@1@*/
+#include 
+
+#include "stypes.h"
+
+#define  DISASS_NAME(X)  disass_gb80##X
+
+
+/* 
+%d - signed compl.,byte jump 
+%w - 2-byte jump or imm. value
+%b - byte imm. value
+  */
+/*  uint  code, mask;  char  branch;  uchar length;  char  *mnemonic; */
+
+struct dis_entry /*DISASS_NAME()*/disass_gb80 []= {
+  { 0x0000, 0x00ff, ' ', 1, "NOP" },
+  { 0x0001, 0x00ff, ' ', 3, "LD BC,%w" },
+  { 0x0002, 0x00ff, ' ', 1, "LD (BC),A" },
+  { 0x0003, 0x00ff, ' ', 1, "INC BC" },
+  { 0x0004, 0x00ff, ' ', 1, "INC B" },
+  { 0x0005, 0x00ff, ' ', 1, "DEC B" },
+  { 0x0006, 0x00ff, ' ', 2, "LD b,%b" },
+  { 0x0007, 0x00ff, ' ', 1, "RLCA" },
+
+  { 0x0008, 0x00ff, ' ', 3, "LD (%w),SP" },  // unique to GB80
+  { 0x0009, 0x00ff, ' ', 1, "ADD HL,BC" },
+  { 0x000a, 0x00ff, ' ', 1, "LD A,(BC)" },
+  { 0x000b, 0x00ff, ' ', 1, "DEC BC" },
+  { 0x000c, 0x00ff, ' ', 1, "INC C" },
+  { 0x000d, 0x00ff, ' ', 1, "DEC C" },
+  { 0x000e, 0x00ff, ' ', 2, "LD C,%b" },
+  { 0x000f, 0x00ff, ' ', 1, "RRCA" },
+
+#if 1
+  { 0x0010, 0x00ff, ' ', 2, "STOP 0" },  // unique to GB80
+#else
+  { 0x0010, 0x00ff, 'R', 2, "DJNZ %d" },
+#endif
+  { 0x0011, 0x00ff, ' ', 3, "LD DE,%w" },
+  { 0x0012, 0x00ff, ' ', 1, "LD (DE),A" },
+  { 0x0013, 0x00ff, ' ', 1, "INC DE" },
+  { 0x0014, 0x00ff, ' ', 1, "INC D" },
+  { 0x0015, 0x00ff, ' ', 1, "DEC D" },
+  { 0x0016, 0x00ff, ' ', 2, "LD D,%b" },
+  { 0x0017, 0x00ff, ' ', 1, "RLA" },
+
+  { 0x0018, 0x00ff, 'R', 2, "JR %d" },
+  { 0x0019, 0x00ff, ' ', 3, "ADD HL,DE" },
+  { 0x001a, 0x00ff, ' ', 1, "LD A,(DE)" },
+  { 0x001b, 0x00ff, ' ', 1, "DEC DE" },
+  { 0x001c, 0x00ff, ' ', 1, "INC E" },
+  { 0x001d, 0x00ff, ' ', 1, "DEC E" },
+  { 0x001e, 0x00ff, ' ', 2, "LD E,%b" },
+  { 0x001f, 0x00ff, ' ', 1, "RRA" },
+
+  { 0x0020, 0x00ff, 'R', 2, "JR NZ,%d" },
+  { 0x0021, 0x00ff, ' ', 3, "LD HL,%w" },
+#if 1
+  { 0x0022, 0x00ff, ' ', 1, "LD (HL+),A" },
+#else
+  { 0x0022, 0x00ff, ' ', 1, "LDI (HL),A" },// unique to GB80
+#endif
+  { 0x0023, 0x00ff, ' ', 1, "INC HL" },
+  { 0x0024, 0x00ff, ' ', 1, "INC H" },
+  { 0x0025, 0x00ff, ' ', 1, "DEC H" },
+  { 0x0026, 0x00ff, ' ', 2, "LD H,%b" },
+  { 0x0027, 0x00ff, ' ', 1, "DAA" },
+
+  { 0x0028, 0x00ff, 'R', 2, "JR Z,%d" },
+  { 0x0029, 0x00ff, ' ', 1, "ADD HL,HL" },
+#if 1
+  { 0x002a, 0x00ff, ' ', 1, "LD A,(HL+)" },
+#else
+  { 0x002a, 0x00ff, ' ', 1, "LDI A,(HL)" },// unique to GB80
+#endif
+  { 0x002b, 0x00ff, ' ', 1, "DEC HL" },
+  { 0x002c, 0x00ff, ' ', 1, "INC L" },
+  { 0x002d, 0x00ff, ' ', 1, "DEC L" },
+  { 0x002e, 0x00ff, ' ', 2, "LD L, %b" },
+  { 0x002f, 0x00ff, ' ', 1, "CPL" },
+
+  { 0x0030, 0x00ff, 'R', 2, "JR NC,%d" },
+  { 0x0031, 0x00ff, ' ', 3, "LD SP,%w" },
+#if 1
+  { 0x0032, 0x00ff, ' ', 1, "LD (HL-),A" },
+#else
+  { 0x0032, 0x00ff, ' ', 1, "LDD (HL),A" },  // unique to GB80
+#endif
+  { 0x0033, 0x00ff, ' ', 1, "INC SP" },
+  { 0x0034, 0x00ff, ' ', 1, "INC (HL)" },
+  { 0x0035, 0x00ff, ' ', 1, "DEC (HL)" },
+  { 0x0036, 0x00ff, ' ', 2, "LD (HL),%b" },
+  { 0x0037, 0x00ff, ' ', 1, "SCF" },
+
+  { 0x0038, 0x00ff, 'R', 2, "JR C,%d" },
+  { 0x0039, 0x00ff, ' ', 1, "ADD HL,SP" },
+#if 1
+  { 0x003a, 0x00ff, ' ', 1, "LD A,(HL-)" },
+#else
+  { 0x003a, 0x00ff, ' ', 1, "LDD A,(HL)" },  // unique to GB80
+#endif
+  { 0x003b, 0x00ff, ' ', 1, "DEC SP" },
+  { 0x003c, 0x00ff, ' ', 1, "INC A" },
+  { 0x003d, 0x00ff, ' ', 1, "DEC A" },
+  { 0x003e, 0x00ff, ' ', 2, "LD A,%b" },
+  { 0x003f, 0x00ff, ' ', 1, "CCF" },
+
+  { 0x0040, 0x00ff, ' ', 1, "LD B,B" },
+  { 0x0041, 0x00ff, ' ', 1, "LD B,C" },
+  { 0x0042, 0x00ff, ' ', 1, "LD B,D" },
+  { 0x0043, 0x00ff, ' ', 1, "LD B,E" },
+  { 0x0044, 0x00ff, ' ', 1, "LD B,H" },
+  { 0x0045, 0x00ff, ' ', 1, "LD B,L" },
+  { 0x0046, 0x00ff, ' ', 1, "LD B,(HL)" },
+  { 0x0047, 0x00ff, ' ', 1, "LD B,a" },
+
+  { 0x0048, 0x00ff, ' ', 1, "LD C,B" },
+  { 0x0049, 0x00ff, ' ', 1, "LD C,C" },
+  { 0x004a, 0x00ff, ' ', 1, "LD C,D" },
+  { 0x004b, 0x00ff, ' ', 1, "LD C,E" },
+  { 0x004c, 0x00ff, ' ', 1, "LD C,H" },
+  { 0x004d, 0x00ff, ' ', 1, "LD C,L" },
+  { 0x004e, 0x00ff, ' ', 1, "LD C,(HL)" },
+  { 0x004f, 0x00ff, ' ', 1, "LD C,A" },
+
+  { 0x0050, 0x00ff, ' ', 1, "LD D,B" },
+  { 0x0051, 0x00ff, ' ', 1, "LD D,C" },
+  { 0x0052, 0x00ff, ' ', 1, "LD D,D" },
+  { 0x0053, 0x00ff, ' ', 1, "LD D,E" },
+  { 0x0054, 0x00ff, ' ', 1, "LD D,H" },
+  { 0x0055, 0x00ff, ' ', 1, "LD D,L" },
+  { 0x0056, 0x00ff, ' ', 1, "LD D,(HL)" },
+  { 0x0057, 0x00ff, ' ', 1, "LD D,A" },
+
+  { 0x0058, 0x00ff, ' ', 1, "LD E,B" },
+  { 0x0059, 0x00ff, ' ', 1, "LD E,C" },
+  { 0x005a, 0x00ff, ' ', 1, "LD E,D" },
+  { 0x005b, 0x00ff, ' ', 1, "LD E,E" },
+  { 0x005c, 0x00ff, ' ', 1, "LD E,H" },
+  { 0x005d, 0x00ff, ' ', 1, "LD E,L" },
+  { 0x005e, 0x00ff, ' ', 1, "LD E,(HL)" },
+  { 0x005f, 0x00ff, ' ', 1, "LD E,A" },
+
+  { 0x0060, 0x00ff, ' ', 1, "LD H,B" },
+  { 0x0061, 0x00ff, ' ', 1, "LD H,C" },
+  { 0x0062, 0x00ff, ' ', 1, "LD H,D" },
+  { 0x0063, 0x00ff, ' ', 1, "LD H,E" },
+  { 0x0064, 0x00ff, ' ', 1, "LD H,H" },
+  { 0x0065, 0x00ff, ' ', 1, "LD H,L" },
+  { 0x0066, 0x00ff, ' ', 1, "LD H,(HL)" },
+  { 0x0067, 0x00ff, ' ', 1, "LD H,A" },
+
+  { 0x0068, 0x00ff, ' ', 1, "LD L,B" },
+  { 0x0069, 0x00ff, ' ', 1, "LD L,C" },
+  { 0x006a, 0x00ff, ' ', 1, "LD L,D" },
+  { 0x006b, 0x00ff, ' ', 1, "LD L,E" },
+  { 0x006c, 0x00ff, ' ', 1, "LD L,H" },
+  { 0x006d, 0x00ff, ' ', 1, "LD L,L" },
+  { 0x006e, 0x00ff, ' ', 1, "LD L,(HL)" },
+  { 0x006f, 0x00ff, ' ', 1, "LD L,A" },
+
+  { 0x0070, 0x00ff, ' ', 1, "LD (HL),B" },
+  { 0x0071, 0x00ff, ' ', 1, "LD (HL),C" },
+  { 0x0072, 0x00ff, ' ', 1, "LD (HL),D" },
+  { 0x0073, 0x00ff, ' ', 1, "LD (HL),E" },
+  { 0x0074, 0x00ff, ' ', 1, "LD (HL),H" },
+  { 0x0075, 0x00ff, ' ', 1, "LD (HL),L" },
+  { 0x0076, 0x00ff, ' ', 1, "HALT" },
+  { 0x0077, 0x00ff, ' ', 1, "LD (HL),A" },
+
+  { 0x0078, 0x00ff, ' ', 1, "LD A,B" },
+  { 0x0079, 0x00ff, ' ', 1, "LD A,C" },
+  { 0x007a, 0x00ff, ' ', 1, "LD A,D" },
+  { 0x007b, 0x00ff, ' ', 1, "LD A,E" },
+  { 0x007c, 0x00ff, ' ', 1, "LD A,H" },
+  { 0x007d, 0x00ff, ' ', 1, "LD A,L" },
+  { 0x007e, 0x00ff, ' ', 1, "LD A,(HL)" },
+  { 0x007f, 0x00ff, ' ', 1, "LD A,A" },
+
+  { 0x0080, 0x00ff, ' ', 1, "ADD A,B" },
+  { 0x0081, 0x00ff, ' ', 1, "ADD A,C" },
+  { 0x0082, 0x00ff, ' ', 1, "ADD A,D" },
+  { 0x0083, 0x00ff, ' ', 1, "ADD A,E" },
+  { 0x0084, 0x00ff, ' ', 1, "ADD A,H" },
+  { 0x0085, 0x00ff, ' ', 1, "ADD A,L" },
+  { 0x0086, 0x00ff, ' ', 1, "ADD A,(HL)" },
+  { 0x0087, 0x00ff, ' ', 1, "ADD A,A" },
+
+  { 0x0088, 0x00ff, ' ', 1, "ADC A,B" },
+  { 0x0089, 0x00ff, ' ', 1, "ADC A,C" },
+  { 0x008a, 0x00ff, ' ', 1, "ADC A,D" },
+  { 0x008b, 0x00ff, ' ', 1, "ADC A,E" },
+  { 0x008c, 0x00ff, ' ', 1, "ADC A,H" },
+  { 0x008d, 0x00ff, ' ', 1, "ADC A,L" },
+  { 0x008e, 0x00ff, ' ', 1, "ADC A,(HL)" },
+  { 0x008f, 0x00ff, ' ', 1, "ADC A,A" },
+
+  { 0x0090, 0x00ff, ' ', 1, "SUB A,B"},
+  { 0x0091, 0x00ff, ' ', 1, "SUB A,C"},
+  { 0x0092, 0x00ff, ' ', 1, "SUB A,D"},
+  { 0x0093, 0x00ff, ' ', 1, "SUB A,E"},
+  { 0x0094, 0x00ff, ' ', 1, "SUB A,H"},
+  { 0x0095, 0x00ff, ' ', 1, "SUB A,L"},
+  { 0x0096, 0x00ff, ' ', 1, "SUB A,(HL)"},
+  { 0x0097, 0x00ff, ' ', 1, "SUB A,A"},
+
+  { 0x0098, 0x00ff, ' ', 1, "SBC A,B" },
+  { 0x0099, 0x00ff, ' ', 1, "SBC A,C" },
+  { 0x009a, 0x00ff, ' ', 1, "SBC A,D" },
+  { 0x009b, 0x00ff, ' ', 1, "SBC A,E" },
+  { 0x009c, 0x00ff, ' ', 1, "SBC A,H" },
+  { 0x009d, 0x00ff, ' ', 1, "SBC A,L" },
+  { 0x009e, 0x00ff, ' ', 1, "SBC A,(HL)" },
+  { 0x009f, 0x00ff, ' ', 1, "SBC A,A" },
+
+  { 0x00a0, 0x00ff, ' ', 1, "AND B" },
+  { 0x00a1, 0x00ff, ' ', 1, "AND C" },
+  { 0x00a2, 0x00ff, ' ', 1, "AND D" },
+  { 0x00a3, 0x00ff, ' ', 1, "AND E" },
+  { 0x00a4, 0x00ff, ' ', 1, "AND H" },
+  { 0x00a5, 0x00ff, ' ', 1, "AND L" },
+  { 0x00a6, 0x00ff, ' ', 1, "AND (HL)" },
+  { 0x00a7, 0x00ff, ' ', 1, "AND A" },
+
+  { 0x00a8, 0x00ff, ' ', 1, "XOR B" },
+  { 0x00a9, 0x00ff, ' ', 1, "XOR C" },
+  { 0x00aa, 0x00ff, ' ', 1, "XOR D" },
+  { 0x00ab, 0x00ff, ' ', 1, "XOR E" },
+  { 0x00ac, 0x00ff, ' ', 1, "XOR H" },
+  { 0x00ad, 0x00ff, ' ', 1, "XOR L" },
+  { 0x00ae, 0x00ff, ' ', 1, "XOR (HL)" },
+  { 0x00af, 0x00ff, ' ', 1, "XOR A" },
+
+  { 0x00b0, 0x00ff, ' ', 1, "OR B" },
+  { 0x00b1, 0x00ff, ' ', 1, "OR C" },
+  { 0x00b2, 0x00ff, ' ', 1, "OR D" },
+  { 0x00b3, 0x00ff, ' ', 1, "OR E" },
+  { 0x00b4, 0x00ff, ' ', 1, "OR H" },
+  { 0x00b5, 0x00ff, ' ', 1, "OR L" },
+  { 0x00b6, 0x00ff, ' ', 1, "OR (HL)" },
+  { 0x00b7, 0x00ff, ' ', 1, "OR A" },
+
+  { 0x00b8, 0x00ff, ' ', 1, "CP B" },
+  { 0x00b9, 0x00ff, ' ', 1, "CP C" },
+  { 0x00ba, 0x00ff, ' ', 1, "CP D" },
+  { 0x00bb, 0x00ff, ' ', 1, "CP E" },
+  { 0x00bc, 0x00ff, ' ', 1, "CP H" },
+  { 0x00bd, 0x00ff, ' ', 1, "CP L" },
+  { 0x00be, 0x00ff, ' ', 1, "CP (HL)" },
+  { 0x00bf, 0x00ff, ' ', 1, "CP A" },
+
+  { 0x00c0, 0x00ff, ' ', 1, "RET NZ" },
+  { 0x00c1, 0x00ff, ' ', 1, "POP BC" },
+  { 0x00c2, 0x00ff, 'A', 3, "JP NZ, %w" },
+  { 0x00c3, 0x00ff, 'A', 3, "JP %w" },
+  { 0x00c4, 0x00ff, 'l', 3, "CALL NZ,%w" },
+  { 0x00c5, 0x00ff, ' ', 1, "PUSH BC" },
+  { 0x00c6, 0x00ff, ' ', 2, "ADD A,%b" },
+  { 0x00c7, 0x00ff, ' ', 1, "RST 0" },
+
+  { 0x00c8, 0x00ff, ' ', 1, "RET Z" },
+  { 0x00c9, 0x00ff, ' ', 1, "RET" },
+  { 0x00ca, 0x00ff, 'A', 3, "JP Z,%w" },
+  { 0x00cb, 0x00ff, ' ', 2, "?cb?" }, /* ESC code to lots of op-codes, all 2-byte */
+
+  { 0x00cc, 0x00ff, 'l', 3, "CALL Z,%w" },
+  { 0x00cd, 0x00ff, 'l', 3, "CALL %w" },
+  { 0x00ce, 0x00ff, ' ', 2, "ADC A,%b" },
+  { 0x00cf, 0x00ff, ' ', 1, "RST 8" },
+  
+  { 0x00d0, 0x00ff, ' ', 1, "RET NC" },
+  { 0x00d1, 0x00ff, ' ', 1, "POP DE" },
+  { 0x00d2, 0x00ff, 'A', 3, "JP NC,%w" },
+  { 0x00d3, 0x00ff, ' ', 2, "Illegal Op" },  // in/out do not exist on GB80
+  { 0x00d4, 0x00ff, 'l', 3, "CALL NC,%w" },
+  { 0x00d5, 0x00ff, ' ', 1, "PUSH DE" },
+  { 0x00d6, 0x00ff, ' ', 2, "SUB %b" },
+  { 0x00d7, 0x00ff, ' ', 1, "RST 10H" },
+
+  { 0x00d8, 0x00ff, ' ', 1, "RET C" },
+  { 0x00d9, 0x00ff, ' ', 1, "RETI" },  // unique to GB80
+  { 0x00da, 0x00ff, 'A', 3, "JP C,%w" },
+  { 0x00db, 0x00ff, ' ', 2, "Illegal Op" },  // in/out do not exist on GB80
+  { 0x00dc, 0x00ff, 'l', 3, "CALL C,%w" },
+  { 0x00dd, 0x00ff, ' ', 2, "Illegal Op" },  /* 0xdd - ESC codes,about 284, vary lengths, IX centric */
+  { 0x00de, 0x00ff, ' ', 2, "SBC A,%b" },
+  { 0x00df, 0x00ff, ' ', 1, "RST 18H" },
+
+  { 0x00e0, 0x00ff, ' ', 2, "LDH (0xFF00+%b),A" },  // unique to GB80
+  { 0x00e1, 0x00ff, ' ', 1, "POP HL" },
+  { 0x00e2, 0x00ff, 'A', 2, "LD (0xFF00+C),A" },  // unique to GB80
+  { 0x00e3, 0x00ff, ' ', 1, "Illegal Op" },
+  { 0x00e4, 0x00ff, 'l', 1, "Illegal Op" },
+  { 0x00e5, 0x00ff, ' ', 1, "PUSH HL" },
+  { 0x00e6, 0x00ff, ' ', 2, "AND %b" },
+  { 0x00e7, 0x00ff, ' ', 1, "RST 20H" },
+
+  { 0x00e8, 0x00ff, ' ', 2, "ADD SP,%d" },  // unique to GB80
+  { 0x00e9, 0x00ff, 'A', 1, "JP (HL)" },
+  { 0x00ea, 0x00ff, ' ', 3, "LD (%w),A" },  // unique to GB80
+  { 0x00eb, 0x00ff, ' ', 1, "Illegal Op" },
+  { 0x00ec, 0x00ff, 'l', 1, "Illegal Op" },
+  { 0x00ed, 0x00ff, ' ', 1, "Illegal Op" },
+  { 0x00ee, 0x00ff, ' ', 2, "XOR %b" },
+  { 0x00ef, 0x00ff, ' ', 1, "RST 28H" },
+
+  { 0x00f0, 0x00ff, ' ', 2, "LDH A,(0xFF00+%b)" },  // unique to GB80
+  { 0x00f1, 0x00ff, ' ', 1, "POP AF" },
+  { 0x00f2, 0x00ff, ' ', 2, "LD A,(0xFF00+C)" },  // unique to GB80
+  { 0x00f3, 0x00ff, ' ', 1, "DI" },
+  { 0x00f4, 0x00ff, 'l', 3, "Illegal Op" },
+  { 0x00f5, 0x00ff, ' ', 1, "PUSH AF" },
+  { 0x00f6, 0x00ff, ' ', 2, "OR %b" },
+  { 0x00f7, 0x00ff, ' ', 1, "RST 30H" },
+
+  { 0x00f8, 0x00ff, ' ', 2, "LD HL,SP+%d" },  // unique to GB80
+  { 0x00f9, 0x00ff, ' ', 1, "LD SP,HL" },
+  { 0x00fa, 0x00ff, ' ', 3, "LD A,(%w)" },  // unique to GB80
+  { 0x00fb, 0x00ff, ' ', 1, "EI" },
+  { 0x00fc, 0x00ff, 'l', 1, "Illegal Op" },
+  { 0x00fd, 0x00ff, ' ', 1, "Illegal Op" },
+  { 0x00fe, 0x00ff, ' ', 2, "CP %b" },
+  { 0x00ff, 0x00ff, ' ', 1, "RST 38H" },
+
+  { 0, 0, 0, 0, NULL }
+};
+
+
+struct dis_entry DISASS_NAME(_cb)[]= {
+  { 0x0000, 0x00ff, ' ', 1, "RLC B" },
+  { 0x0001, 0x00ff, ' ', 1, "RLC C" },
+  { 0x0002, 0x00ff, ' ', 1, "RLC D" },
+  { 0x0003, 0x00ff, ' ', 1, "RLC E" },
+  { 0x0004, 0x00ff, ' ', 1, "RLC H" },
+  { 0x0005, 0x00ff, ' ', 1, "RLC L" },
+  { 0x0006, 0x00ff, ' ', 1, "RLC (HL)" },
+  { 0x0007, 0x00ff, ' ', 1, "RLC A" },
+  { 0x0008, 0x00ff, ' ', 1, "RRC B" },
+  { 0x0009, 0x00ff, ' ', 1, "RRC C" },
+  { 0x000A, 0x00ff, ' ', 1, "RRC D" },
+  { 0x000B, 0x00ff, ' ', 1, "RRC E" },
+  { 0x000C, 0x00ff, ' ', 1, "RRC H" },
+  { 0x000D, 0x00ff, ' ', 1, "RRC L" },
+  { 0x000E, 0x00ff, ' ', 1, "RRC (HL)" },
+  { 0x000F, 0x00ff, ' ', 1, "RRC A" },
+  { 0x0010, 0x00ff, ' ', 1, "RL B" },
+  { 0x0011, 0x00ff, ' ', 1, "RL C" },
+  { 0x0012, 0x00ff, ' ', 1, "RL D" },
+  { 0x0013, 0x00ff, ' ', 1, "RL E" },
+  { 0x0014, 0x00ff, ' ', 1, "RL H" },
+  { 0x0015, 0x00ff, ' ', 1, "RL L" },
+  { 0x0016, 0x00ff, ' ', 1, "RL (HL)" },
+  { 0x0017, 0x00ff, ' ', 1, "RL A" },
+  { 0x0018, 0x00ff, ' ', 1, "RR B" },
+  { 0x0019, 0x00ff, ' ', 1, "RR C" },
+  { 0x001A, 0x00ff, ' ', 1, "RR D" },
+  { 0x001B, 0x00ff, ' ', 1, "RR E" },
+  { 0x001C, 0x00ff, ' ', 1, "RR H" },
+  { 0x001D, 0x00ff, ' ', 1, "RR L" },
+  { 0x001E, 0x00ff, ' ', 1, "RR (HL)" },
+  { 0x001F, 0x00ff, ' ', 1, "RR A" },
+  { 0x0020, 0x00ff, ' ', 1, "SLA B" },
+  { 0x0021, 0x00ff, ' ', 1, "SLA C" },
+  { 0x0022, 0x00ff, ' ', 1, "SLA D" },
+  { 0x0023, 0x00ff, ' ', 1, "SLA E" },
+  { 0x0024, 0x00ff, ' ', 1, "SLA H" },
+  { 0x0025, 0x00ff, ' ', 1, "SLA L" },
+  { 0x0026, 0x00ff, ' ', 1, "SLA (HL)" },
+  { 0x0027, 0x00ff, ' ', 1, "SLA A" },
+  { 0x0028, 0x00ff, ' ', 1, "SRA B" },
+  { 0x0029, 0x00ff, ' ', 1, "SRA C" },
+  { 0x002A, 0x00ff, ' ', 1, "SRA D" },
+  { 0x002B, 0x00ff, ' ', 1, "SRA E" },
+  { 0x002C, 0x00ff, ' ', 1, "SRA H" },
+  { 0x002D, 0x00ff, ' ', 1, "SRA L" },
+  { 0x002E, 0x00ff, ' ', 1, "SRA (HL)" },
+  { 0x002F, 0x00ff, ' ', 1, "SRA A" },
+  { 0x0030, 0x00ff, ' ', 1, "SWAP B" },
+  { 0x0031, 0x00ff, ' ', 1, "SWAP C" },
+  { 0x0032, 0x00ff, ' ', 1, "SWAP D" },
+  { 0x0033, 0x00ff, ' ', 1, "SWAP E" },
+  { 0x0034, 0x00ff, ' ', 1, "SWAP H" },
+  { 0x0035, 0x00ff, ' ', 1, "SWAP L" },
+  { 0x0036, 0x00ff, ' ', 1, "SWAP (HL)" },
+  { 0x0037, 0x00ff, ' ', 1, "SWAP A" },
+  { 0x0038, 0x00ff, ' ', 1, "SRL B" },
+  { 0x0039, 0x00ff, ' ', 1, "SRL C" },
+  { 0x003A, 0x00ff, ' ', 1, "SRL D" },
+  { 0x003B, 0x00ff, ' ', 1, "SRL E" },
+  { 0x003C, 0x00ff, ' ', 1, "SRL H" },
+  { 0x003D, 0x00ff, ' ', 1, "SRL L" },
+  { 0x003E, 0x00ff, ' ', 1, "SRL (HL)" },
+  { 0x003F, 0x00ff, ' ', 1, "SRL A" },
+  { 0x0040, 0x00ff, ' ', 1, "BIT 0,B" },
+  { 0x0041, 0x00ff, ' ', 1, "BIT 0,C" },
+  { 0x0042, 0x00ff, ' ', 1, "BIT 0,D" },
+  { 0x0043, 0x00ff, ' ', 1, "BIT 0,E" },
+  { 0x0044, 0x00ff, ' ', 1, "BIT 0,H" },
+  { 0x0045, 0x00ff, ' ', 1, "BIT 0,L" },
+  { 0x0046, 0x00ff, ' ', 1, "BIT 0,(HL)" },
+  { 0x0047, 0x00ff, ' ', 1, "BIT 0,A" },
+  { 0x0048, 0x00ff, ' ', 1, "BIT 1,B" },
+  { 0x0049, 0x00ff, ' ', 1, "BIT 1,C" },
+  { 0x004A, 0x00ff, ' ', 1, "BIT 1,D" },
+  { 0x004B, 0x00ff, ' ', 1, "BIT 1,E" },
+  { 0x004C, 0x00ff, ' ', 1, "BIT 1,H" },
+  { 0x004D, 0x00ff, ' ', 1, "BIT 1,L" },
+  { 0x004E, 0x00ff, ' ', 1, "BIT 1,(HL)" },
+  { 0x004F, 0x00ff, ' ', 1, "BIT 1,A" },
+  { 0x0050, 0x00ff, ' ', 1, "BIT 2,B" },
+  { 0x0051, 0x00ff, ' ', 1, "BIT 2,C" },
+  { 0x0052, 0x00ff, ' ', 1, "BIT 2,D" },
+  { 0x0053, 0x00ff, ' ', 1, "BIT 2,E" },
+  { 0x0054, 0x00ff, ' ', 1, "BIT 2,H" },
+  { 0x0055, 0x00ff, ' ', 1, "BIT 2,L" },
+  { 0x0056, 0x00ff, ' ', 1, "BIT 2,(HL)" },
+  { 0x0057, 0x00ff, ' ', 1, "BIT 2,A" },
+  { 0x0058, 0x00ff, ' ', 1, "BIT 3,B" },
+  { 0x0059, 0x00ff, ' ', 1, "BIT 3,C" },
+  { 0x005A, 0x00ff, ' ', 1, "BIT 3,D" },
+  { 0x005B, 0x00ff, ' ', 1, "BIT 3,E" },
+  { 0x005C, 0x00ff, ' ', 1, "BIT 3,H" },
+  { 0x005D, 0x00ff, ' ', 1, "BIT 3,L" },
+  { 0x005E, 0x00ff, ' ', 1, "BIT 3,(HL)" },
+  { 0x005F, 0x00ff, ' ', 1, "BIT 3,A" },
+  { 0x0060, 0x00ff, ' ', 1, "BIT 4,B" },
+  { 0x0061, 0x00ff, ' ', 1, "BIT 4,C" },
+  { 0x0062, 0x00ff, ' ', 1, "BIT 4,D" },
+  { 0x0063, 0x00ff, ' ', 1, "BIT 4,E" },
+  { 0x0064, 0x00ff, ' ', 1, "BIT 4,H" },
+  { 0x0065, 0x00ff, ' ', 1, "BIT 4,L" },
+  { 0x0066, 0x00ff, ' ', 1, "BIT 4,(HL)" },
+  { 0x0067, 0x00ff, ' ', 1, "BIT 4,A" },
+  { 0x0068, 0x00ff, ' ', 1, "BIT 5,B" },
+  { 0x0069, 0x00ff, ' ', 1, "BIT 5,C" },
+  { 0x006A, 0x00ff, ' ', 1, "BIT 5,D" },
+  { 0x006B, 0x00ff, ' ', 1, "BIT 5,E" },
+  { 0x006C, 0x00ff, ' ', 1, "BIT 5,H" },
+  { 0x006D, 0x00ff, ' ', 1, "BIT 5,L" },
+  { 0x006E, 0x00ff, ' ', 1, "BIT 5,(HL)" },
+  { 0x006F, 0x00ff, ' ', 1, "BIT 5,A" },
+  { 0x0070, 0x00ff, ' ', 1, "BIT 6,B" },
+  { 0x0071, 0x00ff, ' ', 1, "BIT 6,C" },
+  { 0x0072, 0x00ff, ' ', 1, "BIT 6,D" },
+  { 0x0073, 0x00ff, ' ', 1, "BIT 6,E" },
+  { 0x0074, 0x00ff, ' ', 1, "BIT 6,H" },
+  { 0x0075, 0x00ff, ' ', 1, "BIT 6,L" },
+  { 0x0076, 0x00ff, ' ', 1, "BIT 6,(HL)" },
+  { 0x0077, 0x00ff, ' ', 1, "BIT 6,A" },
+  { 0x0078, 0x00ff, ' ', 1, "BIT 7,B" },
+  { 0x0079, 0x00ff, ' ', 1, "BIT 7,C" },
+  { 0x007A, 0x00ff, ' ', 1, "BIT 7,D" },
+  { 0x007B, 0x00ff, ' ', 1, "BIT 7,E" },
+  { 0x007C, 0x00ff, ' ', 1, "BIT 7,H" },
+  { 0x007D, 0x00ff, ' ', 1, "BIT 7,L" },
+  { 0x007E, 0x00ff, ' ', 1, "BIT 7,(HL)" },
+  { 0x007F, 0x00ff, ' ', 1, "BIT 7,A" },
+  { 0x0080, 0x00ff, ' ', 1, "RES 0,B" },
+  { 0x0081, 0x00ff, ' ', 1, "RES 0,C" },
+  { 0x0082, 0x00ff, ' ', 1, "RES 0,D" },
+  { 0x0083, 0x00ff, ' ', 1, "RES 0,E" },
+  { 0x0084, 0x00ff, ' ', 1, "RES 0,H" },
+  { 0x0085, 0x00ff, ' ', 1, "RES 0,L" },
+  { 0x0086, 0x00ff, ' ', 1, "RES 0,(HL)" },
+  { 0x0087, 0x00ff, ' ', 1, "RES 0,A" },
+  { 0x0088, 0x00ff, ' ', 1, "RES 1,B" },
+  { 0x0089, 0x00ff, ' ', 1, "RES 1,C" },
+  { 0x008A, 0x00ff, ' ', 1, "RES 1,D" },
+  { 0x008B, 0x00ff, ' ', 1, "RES 1,E" },
+  { 0x008C, 0x00ff, ' ', 1, "RES 1,H" },
+  { 0x008D, 0x00ff, ' ', 1, "RES 1,L" },
+  { 0x008E, 0x00ff, ' ', 1, "RES 1,(HL)" },
+  { 0x008F, 0x00ff, ' ', 1, "RES 1,A" },
+  { 0x0090, 0x00ff, ' ', 1, "RES 2,B" },
+  { 0x0091, 0x00ff, ' ', 1, "RES 2,C" },
+  { 0x0092, 0x00ff, ' ', 1, "RES 2,D" },
+  { 0x0093, 0x00ff, ' ', 1, "RES 2,E" },
+  { 0x0094, 0x00ff, ' ', 1, "RES 2,H" },
+  { 0x0095, 0x00ff, ' ', 1, "RES 2,L" },
+  { 0x0096, 0x00ff, ' ', 1, "RES 2,(HL)" },
+  { 0x0097, 0x00ff, ' ', 1, "RES 2,A" },
+  { 0x0098, 0x00ff, ' ', 1, "RES 3,B" },
+  { 0x0099, 0x00ff, ' ', 1, "RES 3,C" },
+  { 0x009A, 0x00ff, ' ', 1, "RES 3,D" },
+  { 0x009B, 0x00ff, ' ', 1, "RES 3,E" },
+  { 0x009C, 0x00ff, ' ', 1, "RES 3,H" },
+  { 0x009D, 0x00ff, ' ', 1, "RES 3,L" },
+  { 0x009E, 0x00ff, ' ', 1, "RES 3,(HL)" },
+  { 0x009F, 0x00ff, ' ', 1, "RES 3,A" },
+  { 0x00A0, 0x00ff, ' ', 1, "RES 4,B" },
+  { 0x00A1, 0x00ff, ' ', 1, "RES 4,C" },
+  { 0x00A2, 0x00ff, ' ', 1, "RES 4,D" },
+  { 0x00A3, 0x00ff, ' ', 1, "RES 4,E" },
+  { 0x00A4, 0x00ff, ' ', 1, "RES 4,H" },
+  { 0x00A5, 0x00ff, ' ', 1, "RES 4,L" },
+  { 0x00A6, 0x00ff, ' ', 1, "RES 4,(HL)" },
+  { 0x00A7, 0x00ff, ' ', 1, "RES 4,A" },
+  { 0x00A8, 0x00ff, ' ', 1, "RES 5,B" },
+  { 0x00A9, 0x00ff, ' ', 1, "RES 5,C" },
+  { 0x00AA, 0x00ff, ' ', 1, "RES 5,D" },
+  { 0x00AB, 0x00ff, ' ', 1, "RES 5,E" },
+  { 0x00AC, 0x00ff, ' ', 1, "RES 5,H" },
+  { 0x00AD, 0x00ff, ' ', 1, "RES 5,L" },
+  { 0x00AE, 0x00ff, ' ', 1, "RES 5,(HL)" },
+  { 0x00AF, 0x00ff, ' ', 1, "RES 5,A" },
+  { 0x00B0, 0x00ff, ' ', 1, "RES 6,B" },
+  { 0x00B1, 0x00ff, ' ', 1, "RES 6,C" },
+  { 0x00B2, 0x00ff, ' ', 1, "RES 6,D" },
+  { 0x00B3, 0x00ff, ' ', 1, "RES 6,E" },
+  { 0x00B4, 0x00ff, ' ', 1, "RES 6,H" },
+  { 0x00B5, 0x00ff, ' ', 1, "RES 6,L" },
+  { 0x00B6, 0x00ff, ' ', 1, "RES 6,(HL)" },
+  { 0x00B7, 0x00ff, ' ', 1, "RES 6,A" },
+  { 0x00B8, 0x00ff, ' ', 1, "RES 7,B" },
+  { 0x00B9, 0x00ff, ' ', 1, "RES 7,C" },
+  { 0x00BA, 0x00ff, ' ', 1, "RES 7,D" },
+  { 0x00BB, 0x00ff, ' ', 1, "RES 7,E" },
+  { 0x00BC, 0x00ff, ' ', 1, "RES 7,H" },
+  { 0x00BD, 0x00ff, ' ', 1, "RES 7,L" },
+  { 0x00BE, 0x00ff, ' ', 1, "RES 7,(HL)" },
+  { 0x00BF, 0x00ff, ' ', 1, "RES 7,A" },
+  { 0x00C0, 0x00ff, ' ', 1, "SET 0,B" },
+  { 0x00C1, 0x00ff, ' ', 1, "SET 0,C" },
+  { 0x00C2, 0x00ff, ' ', 1, "SET 0,D" },
+  { 0x00C3, 0x00ff, ' ', 1, "SET 0,E" },
+  { 0x00C4, 0x00ff, ' ', 1, "SET 0,H" },
+  { 0x00C5, 0x00ff, ' ', 1, "SET 0,L" },
+  { 0x00C6, 0x00ff, ' ', 1, "SET 0,(HL)" },
+  { 0x00C7, 0x00ff, ' ', 1, "SET 0,A" },
+  { 0x00C8, 0x00ff, ' ', 1, "SET 1,B" },
+  { 0x00C9, 0x00ff, ' ', 1, "SET 1,C" },
+  { 0x00CA, 0x00ff, ' ', 1, "SET 1,D" },
+  { 0x00CB, 0x00ff, ' ', 1, "SET 1,E" },
+  { 0x00CC, 0x00ff, ' ', 1, "SET 1,H" },
+  { 0x00CD, 0x00ff, ' ', 1, "SET 1,L" },
+  { 0x00CE, 0x00ff, ' ', 1, "SET 1,(HL)" },
+  { 0x00CF, 0x00ff, ' ', 1, "SET 1,A" },
+  { 0x00D0, 0x00ff, ' ', 1, "SET 2,B" },
+  { 0x00D1, 0x00ff, ' ', 1, "SET 2,C" },
+  { 0x00D2, 0x00ff, ' ', 1, "SET 2,D" },
+  { 0x00D3, 0x00ff, ' ', 1, "SET 2,E" },
+  { 0x00D4, 0x00ff, ' ', 1, "SET 2,H" },
+  { 0x00D5, 0x00ff, ' ', 1, "SET 2,L" },
+  { 0x00D6, 0x00ff, ' ', 1, "SET 2,(HL)" },
+  { 0x00D7, 0x00ff, ' ', 1, "SET 2,A" },
+  { 0x00D8, 0x00ff, ' ', 1, "SET 3,B" },
+  { 0x00D9, 0x00ff, ' ', 1, "SET 3,C" },
+  { 0x00DA, 0x00ff, ' ', 1, "SET 3,D" },
+  { 0x00DB, 0x00ff, ' ', 1, "SET 3,E" },
+  { 0x00DC, 0x00ff, ' ', 1, "SET 3,H" },
+  { 0x00DD, 0x00ff, ' ', 1, "SET 3,L" },
+  { 0x00DE, 0x00ff, ' ', 1, "SET 3,(HL)" },
+  { 0x00DF, 0x00ff, ' ', 1, "SET 3,A" },
+  { 0x00E0, 0x00ff, ' ', 1, "SET 4,B" },
+  { 0x00E1, 0x00ff, ' ', 1, "SET 4,C" },
+  { 0x00E2, 0x00ff, ' ', 1, "SET 4,D" },
+  { 0x00E3, 0x00ff, ' ', 1, "SET 4,E" },
+  { 0x00E4, 0x00ff, ' ', 1, "SET 4,H" },
+  { 0x00E5, 0x00ff, ' ', 1, "SET 4,L" },
+  { 0x00E6, 0x00ff, ' ', 1, "SET 4,(HL)" },
+  { 0x00E7, 0x00ff, ' ', 1, "SET 4,A" },
+  { 0x00E8, 0x00ff, ' ', 1, "SET 5,B" },
+  { 0x00E9, 0x00ff, ' ', 1, "SET 5,C" },
+  { 0x00EA, 0x00ff, ' ', 1, "SET 5,D" },
+  { 0x00EB, 0x00ff, ' ', 1, "SET 5,E" },
+  { 0x00EC, 0x00ff, ' ', 1, "SET 5,H" },
+  { 0x00ED, 0x00ff, ' ', 1, "SET 5,L" },
+  { 0x00EE, 0x00ff, ' ', 1, "SET 5,(HL)" },
+  { 0x00EF, 0x00ff, ' ', 1, "SET 5,A" },
+  { 0x00F0, 0x00ff, ' ', 1, "SET 6,B" },
+  { 0x00F1, 0x00ff, ' ', 1, "SET 6,C" },
+  { 0x00F2, 0x00ff, ' ', 1, "SET 6,D" },
+  { 0x00F3, 0x00ff, ' ', 1, "SET 6,E" },
+  { 0x00F4, 0x00ff, ' ', 1, "SET 6,H" },
+  { 0x00F5, 0x00ff, ' ', 1, "SET 6,L" },
+  { 0x00F6, 0x00ff, ' ', 1, "SET 6,(HL)" },
+  { 0x00F7, 0x00ff, ' ', 1, "SET 6,A" },
+  { 0x00F8, 0x00ff, ' ', 1, "SET 7,B" },
+  { 0x00F9, 0x00ff, ' ', 1, "SET 7,C" },
+  { 0x00FA, 0x00ff, ' ', 1, "SET 7,D" },
+  { 0x00FB, 0x00ff, ' ', 1, "SET 7,E" },
+  { 0x00FC, 0x00ff, ' ', 1, "SET 7,H" },
+  { 0x00FD, 0x00ff, ' ', 1, "SET 7,L" },
+  { 0x00FE, 0x00ff, ' ', 1, "SET 7,(HL)" },
+  { 0x00FF, 0x00ff, ' ', 1, "SET 7,A" },
+  { 0, 0, 0, 0, NULL }
+};
+
+/* End of z80.src/glob_gb80.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/z80.src/glob.h sdcc-4.2.0+dfsg/sim/ucsim/z80.src/glob.h
--- sdcc-4.0.0+dfsg/sim/ucsim/z80.src/glob.h	2012-01-10 04:32:27.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/z80.src/glob.h	2021-03-20 16:44:50.000000000 +0000
@@ -32,6 +32,7 @@
 
 extern struct dis_entry disass_z80[];
 
+extern struct dis_entry disass_z80n_ed[];
 extern struct dis_entry disass_z80_ed[];
 extern struct dis_entry disass_z80_cb[];
 extern struct dis_entry disass_z80_dd[];
@@ -49,8 +50,8 @@
 extern struct dis_entry disass_r2k_ddcb[];
 extern struct dis_entry disass_r2k_fdcb[];
 
-extern struct dis_entry disass_lr35902[];
-extern struct dis_entry disass_lr35902_cb[];
+extern struct dis_entry disass_gb80[];
+extern struct dis_entry disass_gb80_cb[];
 
 #endif
 
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/z80.src/glob_lr35902.cc sdcc-4.2.0+dfsg/sim/ucsim/z80.src/glob_lr35902.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/z80.src/glob_lr35902.cc	2016-11-13 20:24:15.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/z80.src/glob_lr35902.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,596 +0,0 @@
-/*
- * Disassembly table for LR35902, a Z-80 derivative used
- * by the Gameboy (glob_lr35902.cc)
- *
- */
-/* Derived from z80 glob.cc by Leland Morrison 2011 */
-
-/* This file is part of microcontroller simulator: ucsim.
-   
-   UCSIM is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 2 of the License, or
-   (at your option) any later version.
-   
-   UCSIM is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-   GNU General Public License for more details.
-   
-   You should have received a copy of the GNU General Public License
-   along with UCSIM; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA. 
-*/
-/*@1@*/
-#include 
-
-#include "stypes.h"
-
-#define  DISASS_NAME(X)  disass_lr35902##X
-
-
-/* 
-%d - signed compl.,byte jump 
-%w - 2-byte jump or imm. value
-%b - byte imm. value
-  */
-/*  uint  code, mask;  char  branch;  uchar length;  char  *mnemonic; */
-
-struct dis_entry /*DISASS_NAME()*/disass_lr35902 []= {
-  { 0x0000, 0x00ff, ' ', 1, "NOP" },
-  { 0x0001, 0x00ff, ' ', 3, "LD BC,%w" },
-  { 0x0002, 0x00ff, ' ', 1, "LD (BC),A" },
-  { 0x0003, 0x00ff, ' ', 1, "INC BC" },
-  { 0x0004, 0x00ff, ' ', 1, "INC B" },
-  { 0x0005, 0x00ff, ' ', 1, "DEC B" },
-  { 0x0006, 0x00ff, ' ', 2, "LD b,%b" },
-  { 0x0007, 0x00ff, ' ', 1, "RLCA" },
-
-  { 0x0008, 0x00ff, ' ', 3, "LD (%w),SP" },  // unique to LR35902
-  { 0x0009, 0x00ff, ' ', 1, "ADD HL,BC" },
-  { 0x000a, 0x00ff, ' ', 1, "LD A,(BC)" },
-  { 0x000b, 0x00ff, ' ', 1, "DEC BC" },
-  { 0x000c, 0x00ff, ' ', 1, "INC C" },
-  { 0x000d, 0x00ff, ' ', 1, "DEC C" },
-  { 0x000e, 0x00ff, ' ', 2, "LD C,%b" },
-  { 0x000f, 0x00ff, ' ', 1, "RRCA" },
-
-#if 1
-  { 0x0010, 0x00ff, ' ', 2, "STOP 0" },  // unique to LR35902
-#else
-  { 0x0010, 0x00ff, 'R', 2, "DJNZ %d" },
-#endif
-  { 0x0011, 0x00ff, ' ', 3, "LD DE,%w" },
-  { 0x0012, 0x00ff, ' ', 1, "LD (DE),A" },
-  { 0x0013, 0x00ff, ' ', 1, "INC DE" },
-  { 0x0014, 0x00ff, ' ', 1, "INC D" },
-  { 0x0015, 0x00ff, ' ', 1, "DEC D" },
-  { 0x0016, 0x00ff, ' ', 2, "LD D,%b" },
-  { 0x0017, 0x00ff, ' ', 1, "RLA" },
-
-  { 0x0018, 0x00ff, 'R', 2, "JR %d" },
-  { 0x0019, 0x00ff, ' ', 3, "ADD HL,DE" },
-  { 0x001a, 0x00ff, ' ', 1, "LD A,(DE)" },
-  { 0x001b, 0x00ff, ' ', 1, "DEC DE" },
-  { 0x001c, 0x00ff, ' ', 1, "INC E" },
-  { 0x001d, 0x00ff, ' ', 1, "DEC E" },
-  { 0x001e, 0x00ff, ' ', 2, "LD E,%b" },
-  { 0x001f, 0x00ff, ' ', 1, "RRA" },
-
-  { 0x0020, 0x00ff, 'R', 2, "JR NZ,%d" },
-  { 0x0021, 0x00ff, ' ', 3, "LD HL,%w" },
-  { 0x0022, 0x00ff, ' ', 1, "LDI (HL),A" },// unique to LR35902
-  { 0x0023, 0x00ff, ' ', 1, "INC HL" },
-  { 0x0024, 0x00ff, ' ', 1, "INC H" },
-  { 0x0025, 0x00ff, ' ', 1, "DEC H" },
-  { 0x0026, 0x00ff, ' ', 2, "LD H,%b" },
-  { 0x0027, 0x00ff, ' ', 1, "DAA" },
-
-  { 0x0028, 0x00ff, 'R', 2, "JR Z,%d" },
-  { 0x0029, 0x00ff, ' ', 1, "ADD HL,HL" },
-  { 0x002a, 0x00ff, ' ', 1, "LDI A,(HL)" },// unique to LR35902
-  { 0x002b, 0x00ff, ' ', 1, "DEC HL" },
-  { 0x002c, 0x00ff, ' ', 1, "INC L" },
-  { 0x002d, 0x00ff, ' ', 1, "DEC L" },
-  { 0x002e, 0x00ff, ' ', 2, "LD L, %b" },
-  { 0x002f, 0x00ff, ' ', 1, "CPL" },
-
-  { 0x0030, 0x00ff, 'R', 2, "JR NC,%d" },
-  { 0x0031, 0x00ff, ' ', 3, "LD SP,%w" },
-  { 0x0032, 0x00ff, ' ', 1, "LDD (HL),A" },  // unique to LR35902
-  { 0x0033, 0x00ff, ' ', 1, "INC SP" },
-  { 0x0034, 0x00ff, ' ', 1, "INC (HL)" },
-  { 0x0035, 0x00ff, ' ', 1, "DEC (HL)" },
-  { 0x0036, 0x00ff, ' ', 2, "LD (HL),%b" },
-  { 0x0037, 0x00ff, ' ', 1, "SCF" },
-
-  { 0x0038, 0x00ff, 'R', 2, "JR C,%d" },
-  { 0x0039, 0x00ff, ' ', 1, "ADD HL,SP" },
-  { 0x003a, 0x00ff, ' ', 1, "LDD A,(HL)" },  // unique to LR35902
-  { 0x003b, 0x00ff, ' ', 1, "DEC SP" },
-  { 0x003c, 0x00ff, ' ', 1, "INC A" },
-  { 0x003d, 0x00ff, ' ', 1, "DEC A" },
-  { 0x003e, 0x00ff, ' ', 2, "LD A,%b" },
-  { 0x003f, 0x00ff, ' ', 1, "CCF" },
-
-  { 0x0040, 0x00ff, ' ', 1, "LD B,B" },
-  { 0x0041, 0x00ff, ' ', 1, "LD B,C" },
-  { 0x0042, 0x00ff, ' ', 1, "LD B,D" },
-  { 0x0043, 0x00ff, ' ', 1, "LD B,E" },
-  { 0x0044, 0x00ff, ' ', 1, "LD B,H" },
-  { 0x0045, 0x00ff, ' ', 1, "LD B,L" },
-  { 0x0046, 0x00ff, ' ', 1, "LD B,(HL)" },
-  { 0x0047, 0x00ff, ' ', 1, "LD B,a" },
-
-  { 0x0048, 0x00ff, ' ', 1, "LD C,B" },
-  { 0x0049, 0x00ff, ' ', 1, "LD C,C" },
-  { 0x004a, 0x00ff, ' ', 1, "LD C,D" },
-  { 0x004b, 0x00ff, ' ', 1, "LD C,E" },
-  { 0x004c, 0x00ff, ' ', 1, "LD C,H" },
-  { 0x004d, 0x00ff, ' ', 1, "LD C,L" },
-  { 0x004e, 0x00ff, ' ', 1, "LD C,(HL)" },
-  { 0x004f, 0x00ff, ' ', 1, "LD C,A" },
-
-  { 0x0050, 0x00ff, ' ', 1, "LD D,B" },
-  { 0x0051, 0x00ff, ' ', 1, "LD D,C" },
-  { 0x0052, 0x00ff, ' ', 1, "LD D,D" },
-  { 0x0053, 0x00ff, ' ', 1, "LD D,E" },
-  { 0x0054, 0x00ff, ' ', 1, "LD D,H" },
-  { 0x0055, 0x00ff, ' ', 1, "LD D,L" },
-  { 0x0056, 0x00ff, ' ', 1, "LD D,(HL)" },
-  { 0x0057, 0x00ff, ' ', 1, "LD D,A" },
-
-  { 0x0058, 0x00ff, ' ', 1, "LD E,B" },
-  { 0x0059, 0x00ff, ' ', 1, "LD E,C" },
-  { 0x005a, 0x00ff, ' ', 1, "LD E,D" },
-  { 0x005b, 0x00ff, ' ', 1, "LD E,E" },
-  { 0x005c, 0x00ff, ' ', 1, "LD E,H" },
-  { 0x005d, 0x00ff, ' ', 1, "LD E,L" },
-  { 0x005e, 0x00ff, ' ', 1, "LD E,(HL)" },
-  { 0x005f, 0x00ff, ' ', 1, "LD E,A" },
-
-  { 0x0060, 0x00ff, ' ', 1, "LD H,B" },
-  { 0x0061, 0x00ff, ' ', 1, "LD H,C" },
-  { 0x0062, 0x00ff, ' ', 1, "LD H,D" },
-  { 0x0063, 0x00ff, ' ', 1, "LD H,E" },
-  { 0x0064, 0x00ff, ' ', 1, "LD H,H" },
-  { 0x0065, 0x00ff, ' ', 1, "LD H,L" },
-  { 0x0066, 0x00ff, ' ', 1, "LD H,(HL)" },
-  { 0x0067, 0x00ff, ' ', 1, "LD H,A" },
-
-  { 0x0068, 0x00ff, ' ', 1, "LD L,B" },
-  { 0x0069, 0x00ff, ' ', 1, "LD L,C" },
-  { 0x006a, 0x00ff, ' ', 1, "LD L,D" },
-  { 0x006b, 0x00ff, ' ', 1, "LD L,E" },
-  { 0x006c, 0x00ff, ' ', 1, "LD L,H" },
-  { 0x006d, 0x00ff, ' ', 1, "LD L,L" },
-  { 0x006e, 0x00ff, ' ', 1, "LD L,(HL)" },
-  { 0x006f, 0x00ff, ' ', 1, "LD L,A" },
-
-  { 0x0070, 0x00ff, ' ', 1, "LD (HL),B" },
-  { 0x0071, 0x00ff, ' ', 1, "LD (HL),C" },
-  { 0x0072, 0x00ff, ' ', 1, "LD (HL),D" },
-  { 0x0073, 0x00ff, ' ', 1, "LD (HL),E" },
-  { 0x0074, 0x00ff, ' ', 1, "LD (HL),H" },
-  { 0x0075, 0x00ff, ' ', 1, "LD (HL),L" },
-  { 0x0076, 0x00ff, ' ', 1, "HALT" },
-  { 0x0077, 0x00ff, ' ', 1, "LD (HL),A" },
-
-  { 0x0078, 0x00ff, ' ', 1, "LD A,B" },
-  { 0x0079, 0x00ff, ' ', 1, "LD A,C" },
-  { 0x007a, 0x00ff, ' ', 1, "LD A,D" },
-  { 0x007b, 0x00ff, ' ', 1, "LD A,E" },
-  { 0x007c, 0x00ff, ' ', 1, "LD A,H" },
-  { 0x007d, 0x00ff, ' ', 1, "LD A,L" },
-  { 0x007e, 0x00ff, ' ', 1, "LD A,(HL)" },
-  { 0x007f, 0x00ff, ' ', 1, "LD A,A" },
-
-  { 0x0080, 0x00ff, ' ', 1, "ADD A,B" },
-  { 0x0081, 0x00ff, ' ', 1, "ADD A,C" },
-  { 0x0082, 0x00ff, ' ', 1, "ADD A,D" },
-  { 0x0083, 0x00ff, ' ', 1, "ADD A,E" },
-  { 0x0084, 0x00ff, ' ', 1, "ADD A,H" },
-  { 0x0085, 0x00ff, ' ', 1, "ADD A,L" },
-  { 0x0086, 0x00ff, ' ', 1, "ADD A,(HL)" },
-  { 0x0087, 0x00ff, ' ', 1, "ADD A,A" },
-
-  { 0x0088, 0x00ff, ' ', 1, "ADC A,B" },
-  { 0x0089, 0x00ff, ' ', 1, "ADC A,C" },
-  { 0x008a, 0x00ff, ' ', 1, "ADC A,D" },
-  { 0x008b, 0x00ff, ' ', 1, "ADC A,E" },
-  { 0x008c, 0x00ff, ' ', 1, "ADC A,H" },
-  { 0x008d, 0x00ff, ' ', 1, "ADC A,L" },
-  { 0x008e, 0x00ff, ' ', 1, "ADC A,(HL)" },
-  { 0x008f, 0x00ff, ' ', 1, "ADC A,A" },
-
-  { 0x0090, 0x00ff, ' ', 1, "SUB A,B"},
-  { 0x0091, 0x00ff, ' ', 1, "SUB A,C"},
-  { 0x0092, 0x00ff, ' ', 1, "SUB A,D"},
-  { 0x0093, 0x00ff, ' ', 1, "SUB A,E"},
-  { 0x0094, 0x00ff, ' ', 1, "SUB A,H"},
-  { 0x0095, 0x00ff, ' ', 1, "SUB A,L"},
-  { 0x0096, 0x00ff, ' ', 1, "SUB A,(HL)"},
-  { 0x0097, 0x00ff, ' ', 1, "SUB A,A"},
-
-  { 0x0098, 0x00ff, ' ', 1, "SBC A,B" },
-  { 0x0099, 0x00ff, ' ', 1, "SBC A,C" },
-  { 0x009a, 0x00ff, ' ', 1, "SBC A,D" },
-  { 0x009b, 0x00ff, ' ', 1, "SBC A,E" },
-  { 0x009c, 0x00ff, ' ', 1, "SBC A,H" },
-  { 0x009d, 0x00ff, ' ', 1, "SBC A,L" },
-  { 0x009e, 0x00ff, ' ', 1, "SBC A,(HL)" },
-  { 0x009f, 0x00ff, ' ', 1, "SBC A,A" },
-
-  { 0x00a0, 0x00ff, ' ', 1, "AND B" },
-  { 0x00a1, 0x00ff, ' ', 1, "AND C" },
-  { 0x00a2, 0x00ff, ' ', 1, "AND D" },
-  { 0x00a3, 0x00ff, ' ', 1, "AND E" },
-  { 0x00a4, 0x00ff, ' ', 1, "AND H" },
-  { 0x00a5, 0x00ff, ' ', 1, "AND L" },
-  { 0x00a6, 0x00ff, ' ', 1, "AND (HL)" },
-  { 0x00a7, 0x00ff, ' ', 1, "AND A" },
-
-  { 0x00a8, 0x00ff, ' ', 1, "XOR B" },
-  { 0x00a9, 0x00ff, ' ', 1, "XOR C" },
-  { 0x00aa, 0x00ff, ' ', 1, "XOR D" },
-  { 0x00ab, 0x00ff, ' ', 1, "XOR E" },
-  { 0x00ac, 0x00ff, ' ', 1, "XOR H" },
-  { 0x00ad, 0x00ff, ' ', 1, "XOR L" },
-  { 0x00ae, 0x00ff, ' ', 1, "XOR (HL)" },
-  { 0x00af, 0x00ff, ' ', 1, "XOR A" },
-
-  { 0x00b0, 0x00ff, ' ', 1, "OR B" },
-  { 0x00b1, 0x00ff, ' ', 1, "OR C" },
-  { 0x00b2, 0x00ff, ' ', 1, "OR D" },
-  { 0x00b3, 0x00ff, ' ', 1, "OR E" },
-  { 0x00b4, 0x00ff, ' ', 1, "OR H" },
-  { 0x00b5, 0x00ff, ' ', 1, "OR L" },
-  { 0x00b6, 0x00ff, ' ', 1, "OR (HL)" },
-  { 0x00b7, 0x00ff, ' ', 1, "OR A" },
-
-  { 0x00b8, 0x00ff, ' ', 1, "CP B" },
-  { 0x00b9, 0x00ff, ' ', 1, "CP C" },
-  { 0x00ba, 0x00ff, ' ', 1, "CP D" },
-  { 0x00bb, 0x00ff, ' ', 1, "CP E" },
-  { 0x00bc, 0x00ff, ' ', 1, "CP H" },
-  { 0x00bd, 0x00ff, ' ', 1, "CP L" },
-  { 0x00be, 0x00ff, ' ', 1, "CP (HL)" },
-  { 0x00bf, 0x00ff, ' ', 1, "CP A" },
-
-  { 0x00c0, 0x00ff, ' ', 1, "RET NZ" },
-  { 0x00c1, 0x00ff, ' ', 1, "POP BC" },
-  { 0x00c2, 0x00ff, 'A', 3, "JP NZ, %w" },
-  { 0x00c3, 0x00ff, 'A', 3, "JP %w" },
-  { 0x00c4, 0x00ff, 'l', 3, "CALL NZ,%w" },
-  { 0x00c5, 0x00ff, ' ', 1, "PUSH BC" },
-  { 0x00c6, 0x00ff, ' ', 2, "ADD A,%b" },
-  { 0x00c7, 0x00ff, ' ', 1, "RST 0" },
-
-  { 0x00c8, 0x00ff, ' ', 1, "RET Z" },
-  { 0x00c9, 0x00ff, ' ', 1, "RET" },
-  { 0x00ca, 0x00ff, 'A', 3, "JP Z,%w" },
-  { 0x00cb, 0x00ff, ' ', 2, "?cb?" }, /* ESC code to lots of op-codes, all 2-byte */
-
-  { 0x00cc, 0x00ff, 'l', 3, "CALL Z,%w" },
-  { 0x00cd, 0x00ff, 'l', 3, "CALL %w" },
-  { 0x00ce, 0x00ff, ' ', 2, "ADC A,%b" },
-  { 0x00cf, 0x00ff, ' ', 1, "RST 8" },
-  
-  { 0x00d0, 0x00ff, ' ', 1, "RET NC" },
-  { 0x00d1, 0x00ff, ' ', 1, "POP DE" },
-  { 0x00d2, 0x00ff, 'A', 3, "JP NC,%w" },
-  { 0x00d3, 0x00ff, ' ', 2, "Illegal Op" },  // in/out do not exist on LR35902
-  { 0x00d4, 0x00ff, 'l', 3, "CALL NC,%w" },
-  { 0x00d5, 0x00ff, ' ', 1, "PUSH DE" },
-  { 0x00d6, 0x00ff, ' ', 2, "sub %b" },
-  { 0x00d7, 0x00ff, ' ', 1, "RST 10H" },
-
-  { 0x00d8, 0x00ff, ' ', 1, "RET C" },
-  { 0x00d9, 0x00ff, ' ', 1, "RETI" },  // unique to LR35902
-  { 0x00da, 0x00ff, 'A', 3, "JP C,%w" },
-  { 0x00db, 0x00ff, ' ', 2, "Illegal Op" },  // in/out do not exist on LR35902
-  { 0x00dc, 0x00ff, 'l', 3, "CALL C,%w" },
-  { 0x00dd, 0x00ff, ' ', 2, "Illegal Op" },  /* 0xdd - ESC codes,about 284, vary lengths, IX centric */
-  { 0x00de, 0x00ff, ' ', 2, "SBC A,%b" },
-  { 0x00df, 0x00ff, ' ', 1, "RST 18H" },
-
-  { 0x00e0, 0x00ff, ' ', 2, "LDH (0xFF00+%b),A" },  // unique to LR35902
-  { 0x00e1, 0x00ff, ' ', 1, "POP HL" },
-  { 0x00e2, 0x00ff, 'A', 2, "LD (0xFF00+C),A" },  // unique to LR35902
-  { 0x00e3, 0x00ff, ' ', 1, "Illegal Op" },
-  { 0x00e4, 0x00ff, 'l', 1, "Illegal Op" },
-  { 0x00e5, 0x00ff, ' ', 1, "PUSH HL" },
-  { 0x00e6, 0x00ff, ' ', 2, "AND %b" },
-  { 0x00e7, 0x00ff, ' ', 1, "RST 20H" },
-
-  { 0x00e8, 0x00ff, ' ', 2, "ADD SP,%d" },  // unique to LR35902
-  { 0x00e9, 0x00ff, 'A', 1, "JP (HL)" },
-  { 0x00ea, 0x00ff, ' ', 3, "LD (%w),A" },  // unique to LR35902
-  { 0x00eb, 0x00ff, ' ', 1, "Illegal Op" },
-  { 0x00ec, 0x00ff, 'l', 1, "Illegal Op" },
-  { 0x00ed, 0x00ff, ' ', 1, "Illegal Op" },
-  { 0x00ee, 0x00ff, ' ', 2, "XOR %b" },
-  { 0x00ef, 0x00ff, ' ', 1, "RST 28H" },
-
-  { 0x00f0, 0x00ff, ' ', 2, "LDH A,(0xFF00+%b)" },  // unique to LR35902
-  { 0x00f1, 0x00ff, ' ', 1, "POP AF" },
-  { 0x00f2, 0x00ff, ' ', 2, "LD A,(0xFF00+C)" },  // unique to LR35902
-  { 0x00f3, 0x00ff, ' ', 1, "DI" },
-  { 0x00f4, 0x00ff, 'l', 3, "Illegal Op" },
-  { 0x00f5, 0x00ff, ' ', 1, "PUSH AF" },
-  { 0x00f6, 0x00ff, ' ', 2, "OR %b" },
-  { 0x00f7, 0x00ff, ' ', 1, "RST 30H" },
-
-  { 0x00f8, 0x00ff, ' ', 2, "LD HL,SP+%d" },  // unique to LR35902
-  { 0x00f9, 0x00ff, ' ', 1, "LD SP,HL" },
-  { 0x00fa, 0x00ff, ' ', 3, "LD A,(%w)" },  // unique to LR35902
-  { 0x00fb, 0x00ff, ' ', 1, "EI" },
-  { 0x00fc, 0x00ff, 'l', 1, "Illegal Op" },
-  { 0x00fd, 0x00ff, ' ', 1, "Illegal Op" },
-  { 0x00fe, 0x00ff, ' ', 2, "CP %b" },
-  { 0x00ff, 0x00ff, ' ', 1, "RST 38H" },
-
-  { 0, 0, 0, 0, NULL }
-};
-
-
-struct dis_entry DISASS_NAME(_cb)[]= {
-  { 0x0000, 0x00ff, ' ', 1, "RLC B" },
-  { 0x0001, 0x00ff, ' ', 1, "RLC C" },
-  { 0x0002, 0x00ff, ' ', 1, "RLC D" },
-  { 0x0003, 0x00ff, ' ', 1, "RLC E" },
-  { 0x0004, 0x00ff, ' ', 1, "RLC H" },
-  { 0x0005, 0x00ff, ' ', 1, "RLC L" },
-  { 0x0006, 0x00ff, ' ', 1, "RLC (HL)" },
-  { 0x0007, 0x00ff, ' ', 1, "RLC A" },
-  { 0x0008, 0x00ff, ' ', 1, "RRC B" },
-  { 0x0009, 0x00ff, ' ', 1, "RRC C" },
-  { 0x000A, 0x00ff, ' ', 1, "RRC D" },
-  { 0x000B, 0x00ff, ' ', 1, "RRC E" },
-  { 0x000C, 0x00ff, ' ', 1, "RRC H" },
-  { 0x000D, 0x00ff, ' ', 1, "RRC L" },
-  { 0x000E, 0x00ff, ' ', 1, "RRC (HL)" },
-  { 0x000F, 0x00ff, ' ', 1, "RRC A" },
-  { 0x0010, 0x00ff, ' ', 1, "RL B" },
-  { 0x0011, 0x00ff, ' ', 1, "RL C" },
-  { 0x0012, 0x00ff, ' ', 1, "RL D" },
-  { 0x0013, 0x00ff, ' ', 1, "RL E" },
-  { 0x0014, 0x00ff, ' ', 1, "RL H" },
-  { 0x0015, 0x00ff, ' ', 1, "RL L" },
-  { 0x0016, 0x00ff, ' ', 1, "RL (HL)" },
-  { 0x0017, 0x00ff, ' ', 1, "RL A" },
-  { 0x0018, 0x00ff, ' ', 1, "RR B" },
-  { 0x0019, 0x00ff, ' ', 1, "RR C" },
-  { 0x001A, 0x00ff, ' ', 1, "RR D" },
-  { 0x001B, 0x00ff, ' ', 1, "RR E" },
-  { 0x001C, 0x00ff, ' ', 1, "RR H" },
-  { 0x001D, 0x00ff, ' ', 1, "RR L" },
-  { 0x001E, 0x00ff, ' ', 1, "RR (HL)" },
-  { 0x001F, 0x00ff, ' ', 1, "RR A" },
-  { 0x0020, 0x00ff, ' ', 1, "SLA B" },
-  { 0x0021, 0x00ff, ' ', 1, "SLA C" },
-  { 0x0022, 0x00ff, ' ', 1, "SLA D" },
-  { 0x0023, 0x00ff, ' ', 1, "SLA E" },
-  { 0x0024, 0x00ff, ' ', 1, "SLA H" },
-  { 0x0025, 0x00ff, ' ', 1, "SLA L" },
-  { 0x0026, 0x00ff, ' ', 1, "SLA (HL)" },
-  { 0x0027, 0x00ff, ' ', 1, "SLA A" },
-  { 0x0028, 0x00ff, ' ', 1, "SRA B" },
-  { 0x0029, 0x00ff, ' ', 1, "SRA C" },
-  { 0x002A, 0x00ff, ' ', 1, "SRA D" },
-  { 0x002B, 0x00ff, ' ', 1, "SRA E" },
-  { 0x002C, 0x00ff, ' ', 1, "SRA H" },
-  { 0x002D, 0x00ff, ' ', 1, "SRA L" },
-  { 0x002E, 0x00ff, ' ', 1, "SRA (HL)" },
-  { 0x002F, 0x00ff, ' ', 1, "SRA A" },
-  { 0x0030, 0x00ff, ' ', 1, "SWAP B" },
-  { 0x0031, 0x00ff, ' ', 1, "SWAP C" },
-  { 0x0032, 0x00ff, ' ', 1, "SWAP D" },
-  { 0x0033, 0x00ff, ' ', 1, "SWAP E" },
-  { 0x0034, 0x00ff, ' ', 1, "SWAP H" },
-  { 0x0035, 0x00ff, ' ', 1, "SWAP L" },
-  { 0x0036, 0x00ff, ' ', 1, "SWAP (HL)" },
-  { 0x0037, 0x00ff, ' ', 1, "SWAP A" },
-  { 0x0038, 0x00ff, ' ', 1, "SRL B" },
-  { 0x0039, 0x00ff, ' ', 1, "SRL C" },
-  { 0x003A, 0x00ff, ' ', 1, "SRL D" },
-  { 0x003B, 0x00ff, ' ', 1, "SRL E" },
-  { 0x003C, 0x00ff, ' ', 1, "SRL H" },
-  { 0x003D, 0x00ff, ' ', 1, "SRL L" },
-  { 0x003E, 0x00ff, ' ', 1, "SRL (HL)" },
-  { 0x003F, 0x00ff, ' ', 1, "SRL A" },
-  { 0x0040, 0x00ff, ' ', 1, "BIT 0,B" },
-  { 0x0041, 0x00ff, ' ', 1, "BIT 0,C" },
-  { 0x0042, 0x00ff, ' ', 1, "BIT 0,D" },
-  { 0x0043, 0x00ff, ' ', 1, "BIT 0,E" },
-  { 0x0044, 0x00ff, ' ', 1, "BIT 0,H" },
-  { 0x0045, 0x00ff, ' ', 1, "BIT 0,L" },
-  { 0x0046, 0x00ff, ' ', 1, "BIT 0,(HL)" },
-  { 0x0047, 0x00ff, ' ', 1, "BIT 0,A" },
-  { 0x0048, 0x00ff, ' ', 1, "BIT 1,B" },
-  { 0x0049, 0x00ff, ' ', 1, "BIT 1,C" },
-  { 0x004A, 0x00ff, ' ', 1, "BIT 1,D" },
-  { 0x004B, 0x00ff, ' ', 1, "BIT 1,E" },
-  { 0x004C, 0x00ff, ' ', 1, "BIT 1,H" },
-  { 0x004D, 0x00ff, ' ', 1, "BIT 1,L" },
-  { 0x004E, 0x00ff, ' ', 1, "BIT 1,(HL)" },
-  { 0x004F, 0x00ff, ' ', 1, "BIT 1,A" },
-  { 0x0050, 0x00ff, ' ', 1, "BIT 2,B" },
-  { 0x0051, 0x00ff, ' ', 1, "BIT 2,C" },
-  { 0x0052, 0x00ff, ' ', 1, "BIT 2,D" },
-  { 0x0053, 0x00ff, ' ', 1, "BIT 2,E" },
-  { 0x0054, 0x00ff, ' ', 1, "BIT 2,H" },
-  { 0x0055, 0x00ff, ' ', 1, "BIT 2,L" },
-  { 0x0056, 0x00ff, ' ', 1, "BIT 2,(HL)" },
-  { 0x0057, 0x00ff, ' ', 1, "BIT 2,A" },
-  { 0x0058, 0x00ff, ' ', 1, "BIT 3,B" },
-  { 0x0059, 0x00ff, ' ', 1, "BIT 3,C" },
-  { 0x005A, 0x00ff, ' ', 1, "BIT 3,D" },
-  { 0x005B, 0x00ff, ' ', 1, "BIT 3,E" },
-  { 0x005C, 0x00ff, ' ', 1, "BIT 3,H" },
-  { 0x005D, 0x00ff, ' ', 1, "BIT 3,L" },
-  { 0x005E, 0x00ff, ' ', 1, "BIT 3,(HL)" },
-  { 0x005F, 0x00ff, ' ', 1, "BIT 3,A" },
-  { 0x0060, 0x00ff, ' ', 1, "BIT 4,B" },
-  { 0x0061, 0x00ff, ' ', 1, "BIT 4,C" },
-  { 0x0062, 0x00ff, ' ', 1, "BIT 4,D" },
-  { 0x0063, 0x00ff, ' ', 1, "BIT 4,E" },
-  { 0x0064, 0x00ff, ' ', 1, "BIT 4,H" },
-  { 0x0065, 0x00ff, ' ', 1, "BIT 4,L" },
-  { 0x0066, 0x00ff, ' ', 1, "BIT 4,(HL)" },
-  { 0x0067, 0x00ff, ' ', 1, "BIT 4,A" },
-  { 0x0068, 0x00ff, ' ', 1, "BIT 5,B" },
-  { 0x0069, 0x00ff, ' ', 1, "BIT 5,C" },
-  { 0x006A, 0x00ff, ' ', 1, "BIT 5,D" },
-  { 0x006B, 0x00ff, ' ', 1, "BIT 5,E" },
-  { 0x006C, 0x00ff, ' ', 1, "BIT 5,H" },
-  { 0x006D, 0x00ff, ' ', 1, "BIT 5,L" },
-  { 0x006E, 0x00ff, ' ', 1, "BIT 5,(HL)" },
-  { 0x006F, 0x00ff, ' ', 1, "BIT 5,A" },
-  { 0x0070, 0x00ff, ' ', 1, "BIT 6,B" },
-  { 0x0071, 0x00ff, ' ', 1, "BIT 6,C" },
-  { 0x0072, 0x00ff, ' ', 1, "BIT 6,D" },
-  { 0x0073, 0x00ff, ' ', 1, "BIT 6,E" },
-  { 0x0074, 0x00ff, ' ', 1, "BIT 6,H" },
-  { 0x0075, 0x00ff, ' ', 1, "BIT 6,L" },
-  { 0x0076, 0x00ff, ' ', 1, "BIT 6,(HL)" },
-  { 0x0077, 0x00ff, ' ', 1, "BIT 6,A" },
-  { 0x0078, 0x00ff, ' ', 1, "BIT 7,B" },
-  { 0x0079, 0x00ff, ' ', 1, "BIT 7,C" },
-  { 0x007A, 0x00ff, ' ', 1, "BIT 7,D" },
-  { 0x007B, 0x00ff, ' ', 1, "BIT 7,E" },
-  { 0x007C, 0x00ff, ' ', 1, "BIT 7,H" },
-  { 0x007D, 0x00ff, ' ', 1, "BIT 7,L" },
-  { 0x007E, 0x00ff, ' ', 1, "BIT 7,(HL)" },
-  { 0x007F, 0x00ff, ' ', 1, "BIT 7,A" },
-  { 0x0080, 0x00ff, ' ', 1, "RES 0,B" },
-  { 0x0081, 0x00ff, ' ', 1, "RES 0,C" },
-  { 0x0082, 0x00ff, ' ', 1, "RES 0,D" },
-  { 0x0083, 0x00ff, ' ', 1, "RES 0,E" },
-  { 0x0084, 0x00ff, ' ', 1, "RES 0,H" },
-  { 0x0085, 0x00ff, ' ', 1, "RES 0,L" },
-  { 0x0086, 0x00ff, ' ', 1, "RES 0,(HL)" },
-  { 0x0087, 0x00ff, ' ', 1, "RES 0,A" },
-  { 0x0088, 0x00ff, ' ', 1, "RES 1,B" },
-  { 0x0089, 0x00ff, ' ', 1, "RES 1,C" },
-  { 0x008A, 0x00ff, ' ', 1, "RES 1,D" },
-  { 0x008B, 0x00ff, ' ', 1, "RES 1,E" },
-  { 0x008C, 0x00ff, ' ', 1, "RES 1,H" },
-  { 0x008D, 0x00ff, ' ', 1, "RES 1,L" },
-  { 0x008E, 0x00ff, ' ', 1, "RES 1,(HL)" },
-  { 0x008F, 0x00ff, ' ', 1, "RES 1,A" },
-  { 0x0090, 0x00ff, ' ', 1, "RES 2,B" },
-  { 0x0091, 0x00ff, ' ', 1, "RES 2,C" },
-  { 0x0092, 0x00ff, ' ', 1, "RES 2,D" },
-  { 0x0093, 0x00ff, ' ', 1, "RES 2,E" },
-  { 0x0094, 0x00ff, ' ', 1, "RES 2,H" },
-  { 0x0095, 0x00ff, ' ', 1, "RES 2,L" },
-  { 0x0096, 0x00ff, ' ', 1, "RES 2,(HL)" },
-  { 0x0097, 0x00ff, ' ', 1, "RES 2,A" },
-  { 0x0098, 0x00ff, ' ', 1, "RES 3,B" },
-  { 0x0099, 0x00ff, ' ', 1, "RES 3,C" },
-  { 0x009A, 0x00ff, ' ', 1, "RES 3,D" },
-  { 0x009B, 0x00ff, ' ', 1, "RES 3,E" },
-  { 0x009C, 0x00ff, ' ', 1, "RES 3,H" },
-  { 0x009D, 0x00ff, ' ', 1, "RES 3,L" },
-  { 0x009E, 0x00ff, ' ', 1, "RES 3,(HL)" },
-  { 0x009F, 0x00ff, ' ', 1, "RES 3,A" },
-  { 0x00A0, 0x00ff, ' ', 1, "RES 4,B" },
-  { 0x00A1, 0x00ff, ' ', 1, "RES 4,C" },
-  { 0x00A2, 0x00ff, ' ', 1, "RES 4,D" },
-  { 0x00A3, 0x00ff, ' ', 1, "RES 4,E" },
-  { 0x00A4, 0x00ff, ' ', 1, "RES 4,H" },
-  { 0x00A5, 0x00ff, ' ', 1, "RES 4,L" },
-  { 0x00A6, 0x00ff, ' ', 1, "RES 4,(HL)" },
-  { 0x00A7, 0x00ff, ' ', 1, "RES 4,A" },
-  { 0x00A8, 0x00ff, ' ', 1, "RES 5,B" },
-  { 0x00A9, 0x00ff, ' ', 1, "RES 5,C" },
-  { 0x00AA, 0x00ff, ' ', 1, "RES 5,D" },
-  { 0x00AB, 0x00ff, ' ', 1, "RES 5,E" },
-  { 0x00AC, 0x00ff, ' ', 1, "RES 5,H" },
-  { 0x00AD, 0x00ff, ' ', 1, "RES 5,L" },
-  { 0x00AE, 0x00ff, ' ', 1, "RES 5,(HL)" },
-  { 0x00AF, 0x00ff, ' ', 1, "RES 5,A" },
-  { 0x00B0, 0x00ff, ' ', 1, "RES 6,B" },
-  { 0x00B1, 0x00ff, ' ', 1, "RES 6,C" },
-  { 0x00B2, 0x00ff, ' ', 1, "RES 6,D" },
-  { 0x00B3, 0x00ff, ' ', 1, "RES 6,E" },
-  { 0x00B4, 0x00ff, ' ', 1, "RES 6,H" },
-  { 0x00B5, 0x00ff, ' ', 1, "RES 6,L" },
-  { 0x00B6, 0x00ff, ' ', 1, "RES 6,(HL)" },
-  { 0x00B7, 0x00ff, ' ', 1, "RES 6,A" },
-  { 0x00B8, 0x00ff, ' ', 1, "RES 7,B" },
-  { 0x00B9, 0x00ff, ' ', 1, "RES 7,C" },
-  { 0x00BA, 0x00ff, ' ', 1, "RES 7,D" },
-  { 0x00BB, 0x00ff, ' ', 1, "RES 7,E" },
-  { 0x00BC, 0x00ff, ' ', 1, "RES 7,H" },
-  { 0x00BD, 0x00ff, ' ', 1, "RES 7,L" },
-  { 0x00BE, 0x00ff, ' ', 1, "RES 7,(HL)" },
-  { 0x00BF, 0x00ff, ' ', 1, "RES 7,A" },
-  { 0x00C0, 0x00ff, ' ', 1, "SET 0,B" },
-  { 0x00C1, 0x00ff, ' ', 1, "SET 0,C" },
-  { 0x00C2, 0x00ff, ' ', 1, "SET 0,D" },
-  { 0x00C3, 0x00ff, ' ', 1, "SET 0,E" },
-  { 0x00C4, 0x00ff, ' ', 1, "SET 0,H" },
-  { 0x00C5, 0x00ff, ' ', 1, "SET 0,L" },
-  { 0x00C6, 0x00ff, ' ', 1, "SET 0,(HL)" },
-  { 0x00C7, 0x00ff, ' ', 1, "SET 0,A" },
-  { 0x00C8, 0x00ff, ' ', 1, "SET 1,B" },
-  { 0x00C9, 0x00ff, ' ', 1, "SET 1,C" },
-  { 0x00CA, 0x00ff, ' ', 1, "SET 1,D" },
-  { 0x00CB, 0x00ff, ' ', 1, "SET 1,E" },
-  { 0x00CC, 0x00ff, ' ', 1, "SET 1,H" },
-  { 0x00CD, 0x00ff, ' ', 1, "SET 1,L" },
-  { 0x00CE, 0x00ff, ' ', 1, "SET 1,(HL)" },
-  { 0x00CF, 0x00ff, ' ', 1, "SET 1,A" },
-  { 0x00D0, 0x00ff, ' ', 1, "SET 2,B" },
-  { 0x00D1, 0x00ff, ' ', 1, "SET 2,C" },
-  { 0x00D2, 0x00ff, ' ', 1, "SET 2,D" },
-  { 0x00D3, 0x00ff, ' ', 1, "SET 2,E" },
-  { 0x00D4, 0x00ff, ' ', 1, "SET 2,H" },
-  { 0x00D5, 0x00ff, ' ', 1, "SET 2,L" },
-  { 0x00D6, 0x00ff, ' ', 1, "SET 2,(HL)" },
-  { 0x00D7, 0x00ff, ' ', 1, "SET 2,A" },
-  { 0x00D8, 0x00ff, ' ', 1, "SET 3,B" },
-  { 0x00D9, 0x00ff, ' ', 1, "SET 3,C" },
-  { 0x00DA, 0x00ff, ' ', 1, "SET 3,D" },
-  { 0x00DB, 0x00ff, ' ', 1, "SET 3,E" },
-  { 0x00DC, 0x00ff, ' ', 1, "SET 3,H" },
-  { 0x00DD, 0x00ff, ' ', 1, "SET 3,L" },
-  { 0x00DE, 0x00ff, ' ', 1, "SET 3,(HL)" },
-  { 0x00DF, 0x00ff, ' ', 1, "SET 3,A" },
-  { 0x00E0, 0x00ff, ' ', 1, "SET 4,B" },
-  { 0x00E1, 0x00ff, ' ', 1, "SET 4,C" },
-  { 0x00E2, 0x00ff, ' ', 1, "SET 4,D" },
-  { 0x00E3, 0x00ff, ' ', 1, "SET 4,E" },
-  { 0x00E4, 0x00ff, ' ', 1, "SET 4,H" },
-  { 0x00E5, 0x00ff, ' ', 1, "SET 4,L" },
-  { 0x00E6, 0x00ff, ' ', 1, "SET 4,(HL)" },
-  { 0x00E7, 0x00ff, ' ', 1, "SET 4,A" },
-  { 0x00E8, 0x00ff, ' ', 1, "SET 5,B" },
-  { 0x00E9, 0x00ff, ' ', 1, "SET 5,C" },
-  { 0x00EA, 0x00ff, ' ', 1, "SET 5,D" },
-  { 0x00EB, 0x00ff, ' ', 1, "SET 5,E" },
-  { 0x00EC, 0x00ff, ' ', 1, "SET 5,H" },
-  { 0x00ED, 0x00ff, ' ', 1, "SET 5,L" },
-  { 0x00EE, 0x00ff, ' ', 1, "SET 5,(HL)" },
-  { 0x00EF, 0x00ff, ' ', 1, "SET 5,A" },
-  { 0x00F0, 0x00ff, ' ', 1, "SET 6,B" },
-  { 0x00F1, 0x00ff, ' ', 1, "SET 6,C" },
-  { 0x00F2, 0x00ff, ' ', 1, "SET 6,D" },
-  { 0x00F3, 0x00ff, ' ', 1, "SET 6,E" },
-  { 0x00F4, 0x00ff, ' ', 1, "SET 6,H" },
-  { 0x00F5, 0x00ff, ' ', 1, "SET 6,L" },
-  { 0x00F6, 0x00ff, ' ', 1, "SET 6,(HL)" },
-  { 0x00F7, 0x00ff, ' ', 1, "SET 6,A" },
-  { 0x00F8, 0x00ff, ' ', 1, "SET 7,B" },
-  { 0x00F9, 0x00ff, ' ', 1, "SET 7,C" },
-  { 0x00FA, 0x00ff, ' ', 1, "SET 7,D" },
-  { 0x00FB, 0x00ff, ' ', 1, "SET 7,E" },
-  { 0x00FC, 0x00ff, ' ', 1, "SET 7,H" },
-  { 0x00FD, 0x00ff, ' ', 1, "SET 7,L" },
-  { 0x00FE, 0x00ff, ' ', 1, "SET 7,(HL)" },
-  { 0x00FF, 0x00ff, ' ', 1, "SET 7,A" },
-  { 0, 0, 0, 0, NULL }
-};
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/z80.src/glob_r2k.cc sdcc-4.2.0+dfsg/sim/ucsim/z80.src/glob_r2k.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/z80.src/glob_r2k.cc	2011-10-09 18:21:10.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/z80.src/glob_r2k.cc	2020-09-17 06:45:33.000000000 +0000
@@ -1,3 +1,3 @@
-#define R2K 1
-
-#include "glob.cc"
+#define R2K 1
+
+#include "glob.cc"
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/z80.src/inst_cb.cc sdcc-4.2.0+dfsg/sim/ucsim/z80.src/inst_cb.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/z80.src/inst_cb.cc	2017-03-02 10:01:56.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/z80.src/inst_cb.cc	2021-07-16 14:31:13.000000000 +0000
@@ -25,11 +25,11 @@
 02111-1307, USA. */
 /*@1@*/
 
-#include "ddconfig.h"
+//#include "ddconfig.h"
 
 // local
 #include "z80cl.h"
-#include "regsz80.h"
+//#include "regsz80.h"
 #include "z80mac.h"
 
 int
@@ -340,32 +340,40 @@
 int
 cl_z80::inst_cb_bit(t_mem code)
 {
-#define bit_bitnum ((code >> 3) & 7)
+  u8_t bit_bitnum= ((code >> 3) & 7);
 
   switch(code & 7) {
     case 0x0: // BIT x,B
-      bit_byte(regs.bc.h, bit_bitnum); break;
+      bit_byte(regs.bc.h, bit_bitnum);
+      break;
     case 0x1: // BIT x,C
-      bit_byte(regs.bc.l, bit_bitnum); break;
+      bit_byte(regs.bc.l, bit_bitnum);
+      break;
     case 0x2: // BIT x,D
-      bit_byte(regs.de.h, bit_bitnum); break;
+      bit_byte(regs.de.h, bit_bitnum);
+      break;
     case 0x3: // BIT x,E
-      bit_byte(regs.de.l, bit_bitnum); break;
+      bit_byte(regs.de.l, bit_bitnum);
+      break;
     case 0x4: // BIT x,H
-      bit_byte(regs.hl.h, bit_bitnum); break;
+      bit_byte(regs.hl.h, bit_bitnum);
+      break;
     case 0x5: // BIT x,L
-      bit_byte(regs.hl.l, bit_bitnum); break;
+      bit_byte(regs.hl.l, bit_bitnum);
+      break;
     case 0x6: // BIT x,(HL)
-      { unsigned char tmp;
+      {
+	unsigned char tmp;
         tmp = get1(regs.HL);
         bit_byte(tmp, bit_bitnum);
         store1(regs.HL, tmp);
 	vc.rd++;
 	vc.wr++;
+	break;
       }
-    break;
     case 0x7: // BIT x,A
-      bit_byte(regs.raf.A, bit_bitnum); break;
+      bit_byte(regs.raf.A, bit_bitnum);
+      break;
     break;
   }
   return(resGO);
@@ -445,7 +453,7 @@
 
   if (fetch(&code))
     return(resBREAKPOINT);
-  tick(1);
+  tick(7);
   switch (code)
     {
     case 0x00: // RLC B
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/z80.src/inst.cc sdcc-4.2.0+dfsg/sim/ucsim/z80.src/inst.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/z80.src/inst.cc	2018-12-19 08:15:29.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/z80.src/inst.cc	2020-08-01 16:50:18.000000000 +0000
@@ -27,13 +27,13 @@
 02111-1307, USA. */
 /*@1@*/
 
-#include "ddconfig.h"
+//#include "ddconfig.h"
 
-#include 
+#include 
 
 // local
 #include "z80cl.h"
-#include "regsz80.h"
+//#include "regsz80.h"
 #include "z80mac.h"
 
 
@@ -47,6 +47,7 @@
 int
 cl_z80::inst_nop(t_mem code)
 {
+  tick(3);
   return(resGO);
 }
 
@@ -64,40 +65,51 @@
     {
     case 1:  // LD BC,nnnn
       regs.BC = fetch2();
+      tick(9);
       break;
     case 2: // LD (BC),A
       store1(regs.BC, regs.raf.A);
       vc.wr++;
+      tick(6);
       break;
     case 6: // LD B,nn
       regs.bc.h = fetch();
+      tick(6);
       break;
     case 0xa: // LD A,(BC)
       regs.raf.A = get1(regs.BC);
       vc.rd++;
+      tick(6);
       break;
     case 0x0e: // LD C,nn
       regs.bc.l = fetch();
+      tick(6);
       break;
     case 0x11: // LD DE,nnnn
       regs.DE = fetch2();
+      tick(9);
       break;
     case 0x12: // LD (DE),A
       store1(regs.DE, regs.raf.A);
       vc.wr++;
+      tick(6);
       break;
     case 0x16: // LD D,nn
       regs.de.h = fetch();
+      tick(6);
       break;
     case 0x1A: // LD A,(DE)
       regs.raf.A = get1(regs.DE);
       vc.rd++;
+      tick(6);
       break;
     case 0x1E: // LD E,nn
       regs.de.l = fetch();
+      tick(6);
       break;
     case 0x21: // LD HL,nnnn
       regs.HL = fetch2();
+      tick(9);
       break;
     case 0x22: // LD (nnnn),HL
       {
@@ -105,10 +117,12 @@
 	tw = fetch2();
 	store2(tw, regs.HL);
 	vc.wr+= 2;
+	tick(15);
 	break;
       }
     case 0x26: // LD H,nn
       regs.hl.h = fetch();
+      tick(6);
       break;
     case 0x2A: // LD HL,(nnnn)
       {
@@ -116,13 +130,16 @@
 	tw = fetch2();
 	regs.HL = get2(tw);
 	vc.rd+= 2;
+	tick(15);
 	break;
       }
     case 0x2E: // LD L,nn
       regs.hl.l = fetch();
+      tick(6);
       break;
     case 0x31: // LD SP,nnnn
       regs.SP = fetch2();
+      tick(9);
       break;
     case 0x32: // LD (nnnn),A
       {
@@ -130,221 +147,290 @@
 	tw = fetch2();
 	store1(tw, regs.raf.A);
 	vc.wr++;
+	tick(12);
 	break;
       }
     case 0x36: // LD (HL),nn
       store1(regs.HL, fetch());
       vc.wr++;
+      tick(9);
       break;
     case 0x3A: // LD A,(nnnn)
       regs.raf.A = get1(fetch2());
       vc.rd++;
+      tick(12);
       break;
     case 0x3E: // LD A,nn
       regs.raf.A = fetch();
+      tick(6);
       break;
     case 0x40: // LD B,B
+      tick(3);
       break;
     case 0x41: // LD B,C
       regs.bc.h = regs.bc.l;
+      tick(3);
       break;
     case 0x42: // LD B,D
       regs.bc.h = regs.de.h;
+      tick(3);
       break;
     case 0x43: // LD B,E
       regs.bc.h = regs.de.l;
+      tick(3);
       break;
     case 0x44: // LD B,H
       regs.bc.h = regs.hl.h;
+      tick(3);
       break;
     case 0x45: // LD B,L
       regs.bc.h = regs.hl.l;
+      tick(3);
       break;
     case 0x46: // LD B,(HL)
       regs.bc.h = get1(regs.HL);
       vc.rd++;
+      tick(6);
       break;
     case 0x47: // LD B,A
       regs.bc.h = regs.raf.A;
+      tick(3);
       break;
     case 0x48: // LD C,B
       regs.bc.l = regs.bc.h;
+      tick(3);
       break;
     case 0x49: // LD C,C
+      tick(3);
       break;
     case 0x4A: // LD C,D
       regs.bc.l = regs.de.h;
+      tick(3);
       break;
     case 0x4B: // LD C,E
       regs.bc.l = regs.de.l;
+      tick(3);
       break;
     case 0x4C: // LD C,H
       regs.bc.l = regs.hl.h;
+      tick(3);
       break;
     case 0x4D: // LD C,L
       regs.bc.l = regs.hl.l;
+      tick(3);
       break;
     case 0x4E: // LD C,(HL)
       regs.bc.l = get1(regs.HL);
       vc.rd++;
+      tick(6);
       break;
     case 0x4F: // LD C,A
       regs.bc.l = regs.raf.A;
+      tick(3);
       break;
     case 0x50: // LD D,B
       regs.de.h = regs.bc.h;
+      tick(3);
       break;
     case 0x51: // LD D,C
       regs.de.h = regs.bc.l;
+      tick(3);
       break;
     case 0x52: // LD D,D
+      tick(3);
       break;
     case 0x53: // LD D,E
       regs.de.h = regs.de.l;
+      tick(3);
       break;
     case 0x54: // LD D,H
       regs.de.h = regs.hl.h;
+      tick(3);
       break;
     case 0x55: // LD D,L
       regs.de.h = regs.hl.l;
+      tick(3);
       break;
     case 0x56: // LD D,(HL)
       regs.de.h = get1(regs.HL);
       vc.rd++;
+      tick(6);
       break;
     case 0x57: // LD D,A
       regs.de.h = regs.raf.A;
+      tick(3);
       break;
     case 0x58: // LD E,B
       regs.de.l = regs.bc.h;
+      tick(3);
       break;
     case 0x59: // LD E,C
       regs.de.l = regs.bc.l;
+      tick(3);
       break;
     case 0x5A: // LD E,D
       regs.de.l = regs.de.h;
+      tick(3);
       break;
     case 0x5B: // LD E,E
+      tick(3);
       break;
     case 0x5C: // LD E,H
       regs.de.l = regs.hl.h;
+      tick(3);
       break;
     case 0x5D: // LD E,L
       regs.de.l = regs.hl.l;
+      tick(3);
       break;
     case 0x5E: // LD E,(HL)
       regs.de.l = get1(regs.HL);
       vc.rd++;
+      tick(6);
       break;
     case 0x5F: // LD E,A
       regs.de.l = regs.raf.A;
+      tick(3);
       break;
     case 0x60: // LD H,B
       regs.hl.h = regs.bc.h;
+      tick(3);
       break;
     case 0x61: // LD H,C
       regs.hl.h = regs.bc.l;
+      tick(3);
       break;
     case 0x62: // LD H,D
       regs.hl.h = regs.de.h;
+      tick(3);
       break;
     case 0x63: // LD H,E
       regs.hl.h = regs.de.l;
+      tick(3);
       break;
     case 0x64: // LD H,H
       regs.hl.h = regs.hl.h;
+      tick(3);
       break;
     case 0x65: // LD H,L
       regs.hl.h = regs.hl.l;
+      tick(3);
       break;
     case 0x66: // LD H,(HL)
       regs.hl.h = get1(regs.HL);
       vc.rd++;
+      tick(6);
       break;
     case 0x67: // LD H,A
       regs.hl.h = regs.raf.A;
+      tick(3);
       break;
     case 0x68: // LD L,B
       regs.hl.l = regs.bc.h;
+      tick(3);
       break;
     case 0x69: // LD L,C
       regs.hl.l = regs.bc.l;
+      tick(3);
       break;
     case 0x6A: // LD L,D
       regs.hl.l = regs.de.h;
+      tick(3);
       break;
     case 0x6B: // LD L,E
       regs.hl.l = regs.de.l;
+      tick(3);
       break;
     case 0x6C: // LD L,H
       regs.hl.l = regs.hl.h;
+      tick(3);
       break;
     case 0x6D: // LD L,L
+      tick(3);
       break;
     case 0x6E: // LD L,(HL)
       regs.hl.l = get1(regs.HL);
       vc.rd++;
+      tick(6);
       break;
     case 0x6F: // LD L,A
       regs.hl.l = regs.raf.A;
+      tick(3);
       break;
     case 0x70: // LD (HL),B
       store1(regs.HL, regs.bc.h);
       vc.wr++;
+      tick(6);
       break;
     case 0x71: // LD (HL),C
       store1(regs.HL, regs.bc.l);
       vc.wr++;
+      tick(6);
       break;
     case 0x72: // LD (HL),D
       store1(regs.HL, regs.de.h);
       vc.wr++;
+      tick(6);
       break;
     case 0x73: // LD (HL),E
       store1(regs.HL, regs.de.l);
       vc.wr++;
+      tick(6);
       break;
     case 0x74: // LD (HL),H
       store1(regs.HL, regs.hl.h);
       vc.wr++;
-      break;
+      tick(6);
+     break;
     case 0x75: // LD (HL),L
       store1(regs.HL, regs.hl.l);
       vc.wr++;
+      tick(6);
       break;
     case 0x76: // HALT
+      tick(3);
       return(resHALT);
 
     case 0x77: // LD (HL),A
       store1(regs.HL, regs.raf.A);
       vc.wr++;
+      tick(6);
       break;
     case 0x78: // LD A,B
       regs.raf.A = regs.bc.h;
+      tick(3);
       break;
     case 0x79: // LD A,C
       regs.raf.A = regs.bc.l;
+      tick(3);
       break;
     case 0x7A: // LD A,D
       regs.raf.A = regs.de.h;
+      tick(3);
       break;
     case 0x7B: // LD A,E
       regs.raf.A = regs.de.l;
+      tick(3);
       break;
     case 0x7C: // LD A,H
       regs.raf.A = regs.hl.h;
+      tick(3);
       break;
     case 0x7D: // LD A,L
       regs.raf.A = regs.hl.l;
+      tick(3);
       break;
     case 0x7E: // LD A,(HL)
       regs.raf.A = get1(regs.HL);
       vc.rd++;
+      tick(6);
       break;
     case 0x7F: // LD A,A
+      tick(3);
       break;
     case 0xF9: // LD SP,HL
       regs.SP = regs.HL;
+      tick(5);
       break;
     default:
       return(resINV_INST);
@@ -360,33 +446,43 @@
     {
     case 0x03: // INC BC
       ++regs.BC;
+      tick(5);
       break;
     case 0x04: // INC B
       inc(regs.bc.h);
+      tick(3);
       break;
     case 0x0C: // INC C
       inc(regs.bc.l);
+      tick(3);
       break;
     case 0x13: // INC DE
       ++regs.DE;
+      tick(5);
       break;
     case 0x14: // INC D
       inc(regs.de.h);
+      tick(3);
       break;
     case 0x1C: // INC E
       inc(regs.de.l);
+      tick(3);
       break;
     case 0x23: // INC HL
       ++regs.HL;
+      tick(5);
       break;
     case 0x24: // INC H
       inc(regs.hl.h);
+      tick(3);
       break;
     case 0x2C: // INC L
       inc(regs.hl.l);
+      tick(3);
       break;
     case 0x33: // INC SP
       ++regs.SP;
+      tick(5);
       break;
     case 0x34: // INC (HL)
       {
@@ -395,10 +491,12 @@
          store1(regs.HL, t);
 	 vc.rd++;
 	 vc.wr++;
+	 tick(6);
 	 break;
       }
     case 0x3C: // INC A
       inc(regs.raf.A);
+      tick(3);
       break;
     default:
       return(resINV_INST);
@@ -414,30 +512,39 @@
     {
     case 0x05: // DEC B
       dec(regs.bc.h);
+      tick(3);
       break;
     case 0x0B: // DEC BC
       --regs.BC;
+      tick(6);
       break;
     case 0x0D: // DEC C
       dec(regs.bc.l);
+      tick(3);
       break;
     case 0x15: // DEC D
       dec(regs.de.h);
+      tick(3);
       break;
     case 0x1B: // DEC DE
       --regs.DE;
+      tick(6);
       break;
     case 0x1D: // DEC E
       dec(regs.de.l);
+      tick(3);
       break;
     case 0x25: // DEC H
       dec(regs.hl.h);
+      tick(3);
       break;
     case 0x2B: // DEC HL
       --regs.HL;
+      tick(6);
       break;
     case 0x2D: // DEC L
       dec(regs.hl.l);
+      tick(3);
       break;
     case 0x35: // DEC (HL)
       {
@@ -446,13 +553,16 @@
 	store1(regs.HL, t);
 	vc.rd++;
 	vc.wr++;
+	tick(6);
 	break;
       }
     case 0x3B: // DEC SP
       --regs.SP;
+      tick(5);
       break;
     case 0x3D: // DEC A
       dec(regs.raf.A);
+      tick(3);
       break;
     default:
       return(resINV_INST);
@@ -470,7 +580,7 @@
      regs.raf.A = (regs.raf.A << 1) | 0x01;
    } else
      regs.raf.A = (regs.raf.A << 1);
-
+  tick(3);
   return(resGO);
 }
 
@@ -484,6 +594,7 @@
    }
    else
      regs.raf.A = (regs.raf.A >> 1);
+  tick(3);
   return(resGO);
 }
 
@@ -503,7 +614,8 @@
       tmp = regs.ralt_af.aF;
       regs.ralt_af.aF = regs.raf.F;
       regs.raf.F = tmp;
-    break;
+      tick(3);
+      break;
 
     case 0xE3: // EX (SP),HL
       tempw = regs.HL;
@@ -511,12 +623,14 @@
       store2(regs.SP, tempw);
       vc.rd+= 2;
       vc.wr+= 2;
+      tick(18);
     break;
 
     case 0xEB: // EX DE,HL
       tempw = regs.DE;
       regs.DE = regs.HL;
       regs.HL = tempw;
+      tick(3);
     break;
 
     default:
@@ -534,34 +648,44 @@
     {
     case 0x09: // ADD HL,BC
       add_HL_Word(regs.BC);
+      tick(10);
       break;
     case 0x19: // ADD HL,DE
       add_HL_Word(regs.DE);
+      tick(10);
       break;
     case 0x29: // ADD HL,HL
       add_HL_Word(regs.HL);
+      tick(10);
       break;
     case 0x39: // ADD HL,SP
       add_HL_Word(regs.SP);
+      tick(10);
       break;
       
     case 0x80: // ADD A,B
       add_A_bytereg(regs.bc.h);
+      tick(3);
       break;
     case 0x81: // ADD A,C
       add_A_bytereg(regs.bc.l);
+      tick(3);
       break;
     case 0x82: // ADD A,D
       add_A_bytereg(regs.de.h);
+      tick(3);
       break;
     case 0x83: // ADD A,E
       add_A_bytereg(regs.de.l);
+      tick(3);
       break;
     case 0x84: // ADD A,H
       add_A_bytereg(regs.hl.h);
+      tick(3);
       break;
     case 0x85: // ADD A,L
       add_A_bytereg(regs.hl.l);
+      tick(3);
       break;
       
     case 0x86: // ADD A,(HL)
@@ -570,11 +694,13 @@
         utmp = get1(regs.HL);
         add_A_bytereg(utmp);
 	vc.rd++;
+	tick(6);
 	break;
       }
       
     case 0x87: // ADD A,A
       add_A_bytereg(regs.raf.A);
+      tick(3);
       break;
       
     case 0xC6: // ADD A,nn
@@ -582,6 +708,7 @@
         unsigned char utmp1;
         utmp1 = fetch();
         add_A_bytereg(utmp1);
+	tick(6);
 	break;
       }
       
@@ -601,8 +728,10 @@
   // 0x10: DJNZ dd
 
   j = fetch1();
+  tick(7);
   if ((--regs.bc.h != 0)) {
     PC += j;
+    tick(5);
   } else {
   }
   return(resGO);
@@ -612,6 +741,7 @@
 cl_z80::inst_rra(t_mem code)
 {
   rr_byte(regs.raf.A);
+  tick(3);
   return(resGO);
 }
 
@@ -619,6 +749,7 @@
 cl_z80::inst_rla(t_mem code)
 {
   rl_byte(regs.raf.A);
+  tick(3);
   return(resGO);
 }
 
@@ -631,25 +762,34 @@
   switch(code) {
     case 0x18: // JR dd
       PC += j;
+      tick(11);
     break;
     case 0x20: // JR NZ,dd
+      tick(6);
       if (!(regs.raf.F & BIT_Z)) {
         PC += j;
+	tick(5);
       }
     break;
     case 0x28: // JR Z,dd
+      tick(6);
       if ((regs.raf.F & BIT_Z)) {
         PC += j;
+	tick(5);
       }
     break;
     case 0x30: // JR NC,dd
+      tick(6);
       if (!(regs.raf.F & BIT_C)) {
         PC += j;
+	tick(5);
       }
     break;
     case 0x38: // JR C,dd
+      tick(6);
       if ((regs.raf.F & BIT_C)) {
         PC += j;
+	tick(5);
       }
     break;
     default:
@@ -697,6 +837,7 @@
   regs.raf.F |= N; /* restore N */
   regs.raf.F |= C; /* or with original C */
 
+  tick(3);
   return(resGO);
 }
 
@@ -705,6 +846,7 @@
 {
   regs.raf.F |= (BIT_A | BIT_N);
   regs.raf.A = ~regs.raf.A;
+  tick(3);
   return(resGO);
 }
 
@@ -714,6 +856,7 @@
   /* Set Carry Flag */
   regs.raf.F &= ~(BIT_A | BIT_N);
   regs.raf.F |= BIT_C;
+  tick(3);
   return(resGO);
 }
 
@@ -725,12 +868,14 @@
   if (regs.raf.F & BIT_C)
     regs.raf.F |= BIT_A;
   regs.raf.F ^= BIT_C;
+  tick(3);
   return(resGO);
 }
 
 int
 cl_z80::inst_halt(t_mem code)
 {
+  tick(3);
   return(resHALT);
 }
 
@@ -741,21 +886,27 @@
     {
     case 0x88: // ADC A,B
       adc_A_bytereg(regs.bc.h);
+      tick(3);
       break;
     case 0x89: // ADC A,C
       adc_A_bytereg(regs.bc.l);
+      tick(3);
       break;
     case 0x8A: // ADC A,D
       adc_A_bytereg(regs.de.h);
+      tick(3);
       break;
     case 0x8B: // ADC A,E
       adc_A_bytereg(regs.de.l);
+      tick(3);
       break;
     case 0x8C: // ADC A,H
       adc_A_bytereg(regs.hl.h);
+      tick(3);
       break;
     case 0x8D: // ADC A,L
       adc_A_bytereg(regs.hl.l);
+      tick(3);
       break;
     case 0x8E: // ADC A,(HL)
       {
@@ -763,10 +914,12 @@
         utmp = get1(regs.HL);
         adc_A_bytereg(utmp);
 	vc.rd++;
+	tick(6);
 	break;
       }
     case 0x8F: // ADC A,A
       adc_A_bytereg(regs.raf.A);
+      tick(3);
       break;
       
     case 0xCE: // ADC A,nn
@@ -774,6 +927,7 @@
 	unsigned char utmp;
         utmp = fetch();
         adc_A_bytereg(utmp);
+	tick(6);
       }
       break;
       
@@ -791,21 +945,27 @@
     {
     case 0x98: // SBC A,B
       sbc_A_bytereg(regs.bc.h);
+      tick(3);
       break;
     case 0x99: // SBC A,C
       sbc_A_bytereg(regs.bc.l);
+      tick(3);
       break;
     case 0x9A: // SBC A,D
       sbc_A_bytereg(regs.de.h);
+      tick(3);
       break;
     case 0x9B: // SBC A,E
       sbc_A_bytereg(regs.de.l);
+      tick(3);
       break;
     case 0x9C: // SBC A,H
       sbc_A_bytereg(regs.hl.h);
+      tick(3);
       break;
     case 0x9D: // SBC A,L
       sbc_A_bytereg(regs.hl.l);
+      tick(3);
       break;
     case 0x9E: // SBC A,(HL)
       {
@@ -813,16 +973,19 @@
         utmp = get1(regs.HL);
         sbc_A_bytereg(utmp);
 	vc.rd++;
+	tick(6);
 	break;
       }
     case 0x9F: // SBC A,A
       sbc_A_bytereg(regs.raf.A);
+      tick(3);
       break;
     case 0xDE: // SBC A,nn
       {
 	unsigned char utmp;
         utmp = fetch();
         sbc_A_bytereg(utmp);
+	tick(6);
 	break;
       }
     default:
@@ -839,21 +1002,27 @@
     {
     case 0xA0: // AND B
       and_A_bytereg(regs.bc.h);
+      tick(3);
       break;
     case 0xA1: // AND C
       and_A_bytereg(regs.bc.l);
+      tick(3);
       break;
     case 0xA2: // AND D
       and_A_bytereg(regs.de.h);
+      tick(3);
       break;
     case 0xA3: // AND E
       and_A_bytereg(regs.de.l);
+      tick(3);
       break;
     case 0xA4: // AND H
       and_A_bytereg(regs.hl.h);
+      tick(3);
       break;
     case 0xA5: // AND L
       and_A_bytereg(regs.hl.l);
+      tick(3);
       break;
     case 0xA6: // AND (HL)
       {
@@ -861,13 +1030,16 @@
         utmp = get1(regs.HL);
         and_A_bytereg(utmp);
 	vc.rd++;
+	tick(6);
 	break;
       }
     case 0xA7: // AND A
       and_A_bytereg(regs.raf.A);
+      tick(3);
       break;
     case 0xE6: // AND nn
       and_A_bytereg(fetch());
+      tick(6);
       break;
       
     default:
@@ -884,21 +1056,27 @@
     {
     case 0xA8: // XOR B
       xor_A_bytereg(regs.bc.h);
+      tick(3);
       break;
     case 0xA9: // XOR C
       xor_A_bytereg(regs.bc.l);
+      tick(3);
       break;
     case 0xAA: // XOR D
       xor_A_bytereg(regs.de.h);
+      tick(3);
       break;
     case 0xAB: // XOR E
       xor_A_bytereg(regs.de.l);
+      tick(3);
       break;
     case 0xAC: // XOR H
       xor_A_bytereg(regs.hl.h);
+      tick(3);
       break;
     case 0xAD: // XOR L
       xor_A_bytereg(regs.hl.l);
+      tick(3);
       break;
     case 0xAE: // XOR (HL)
       {
@@ -906,13 +1084,16 @@
         utmp = get1(regs.HL);
         xor_A_bytereg(utmp);
 	vc.rd++;
+	tick(6);
 	break;
       }
     case 0xAF: // XOR A
       xor_A_bytereg(regs.raf.A);
+      tick(3);
       break;
     case 0xEE: // XOR nn
       xor_A_bytereg(fetch());
+      tick(6);
       break;
       
     default:
@@ -929,21 +1110,27 @@
     {
     case 0xB0: // OR B
       or_A_bytereg(regs.bc.h);
+      tick(3);
       break;
     case 0xB1: // OR C
       or_A_bytereg(regs.bc.l);
+      tick(3);
       break;
     case 0xB2: // OR D
       or_A_bytereg(regs.de.h);
+      tick(3);
       break;
     case 0xB3: // OR E
       or_A_bytereg(regs.de.l);
+      tick(3);
       break;
     case 0xB4: // OR H
       or_A_bytereg(regs.hl.h);
+      tick(3);
       break;
     case 0xB5: // OR L
       or_A_bytereg(regs.hl.l);
+      tick(3);
       break;
     case 0xB6: // OR (HL)
       {
@@ -951,13 +1138,16 @@
         utmp = get1(regs.HL);
         or_A_bytereg(utmp);
 	vc.rd++;
+	tick(6);
 	break;
       }
     case 0xB7: // OR A
       or_A_bytereg(regs.raf.A);
+      tick(3);
       break;
     case 0xF6: // OR nn
       or_A_bytereg(fetch());
+      tick(6);
       break;
     default:
       return(resINV_INST);
@@ -974,21 +1164,27 @@
     {
     case 0xB8: // CP B
       cp_bytereg(regs.bc.h);
+      tick(3);
       break;
     case 0xB9: // CP C
       cp_bytereg(regs.bc.l);
+      tick(3);
       break;
     case 0xBA: // CP D
       cp_bytereg(regs.de.h);
+      tick(3);
       break;
     case 0xBB: // CP E
       cp_bytereg(regs.de.l);
+      tick(3);
       break;
     case 0xBC: // CP H
       cp_bytereg(regs.hl.h);
+      tick(3);
       break;
     case 0xBD: // CP L
       cp_bytereg(regs.hl.l);
+      tick(3);
       break;
     case 0xBE: // CP (HL)
       {
@@ -996,16 +1192,19 @@
         utmp = get1(regs.HL);
         cp_bytereg(utmp);
 	vc.rd++;
+	tick(6);
 	break;
       }
     case 0xBF: // CP A
       cp_bytereg(regs.raf.A);
+      tick(3);
       break;
     case 0xFE: // CP nn
       {
 	unsigned char utmp;
         utmp = fetch();
         cp_bytereg(utmp);
+	tick(6);
 	break;
       }
     default:
@@ -1021,12 +1220,17 @@
   switch(code)
     {
     case 0xC7: // RST 0
-      push2(PC+2);
+      push2(PC);
       PC = 0x0;
       vc.wr+= 2;
+      tick(10);
       break;
     case 0xCF: // RST 8
-      //PC = 0x08;
+      push2(PC);
+      vc.wr+= 2;
+      PC = 0x08;
+      tick(10);
+      break;
       switch (regs.raf.A)
 	{
 	case 0:
@@ -1042,34 +1246,40 @@
 	}
       break;
     case 0xD7: // RST 10H
-      push2(PC+2);
+      push2(PC);
       PC = 0x10;
       vc.wr+= 2;
+      tick(10);
       break;
     case 0xDF: // RST 18H
-      push2(PC+2);
+      push2(PC);
       PC = 0x18;
       vc.wr+= 2;
+      tick(10);
       break;
     case 0xE7: // RST 20H
-      push2(PC+2);
+      push2(PC);
       PC = 0x20;
       vc.wr+= 2;
+      tick(10);
       break;
     case 0xEF: // RST 28H
-      push2(PC+2);
+      push2(PC);
       PC = 0x28;
       vc.wr+= 2;
+      tick(10);
       break;
     case 0xF7: // RST 30H
-      push2(PC+2);
+      push2(PC);
       PC = 0x30;
       vc.wr+= 2;
+      tick(10);
       break;
     case 0xFF: // RST 38H
-      push2(PC+2);
+      push2(PC);
       PC = 0x38;
       vc.wr+= 2;
+      tick(10);
       break;
     default:
       return(resINV_INST);
@@ -1084,55 +1294,72 @@
   switch(code)
     {
     case 0xC0: // RET NZ
+      tick(4);
       if (!(regs.raf.F & BIT_Z)) {
         pop2(PC);
 	vc.rd+= 2;
+	tick(6);
       }
       break;
     case 0xC8: // RET Z
+      tick(4);
       if ((regs.raf.F & BIT_Z)) {
         pop2(PC);
 	vc.rd+= 2;
+	tick(6);
       }
       break;
     case 0xC9: // RET
+      tick(9);
       pop2(PC);
       vc.rd+= 2;
       break;
     case 0xD0: // RET NC
+      tick(4);
       if (!(regs.raf.F & BIT_C)) {
         pop2(PC);
 	vc.rd+= 2;
+	tick(6);
       }
       break;
     case 0xD8: // RET C
+      tick(4);
       if ((regs.raf.F & BIT_C)) {
         pop2(PC);
 	vc.rd+= 2;
+	tick(6);
       }
       break;
     case 0xE0: // RET PO
+      tick(4);
       if (!(regs.raf.F & BIT_P)) {
         pop2(PC);
 	vc.rd+= 2;
+	tick(6);
       }
       break;
     case 0xE8: // RET PE
+      tick(4);
       if ((regs.raf.F & BIT_P)) {
         pop2(PC);
 	vc.rd+= 2;
+	tick(6);
       }
       break;
     case 0xF0: // RET P
+      tick(4);
       if (!(regs.raf.F & BIT_S)) {
         pop2(PC);
 	vc.rd+= 2;
+	tick(6);
       }
       break;
     case 0xF8: // RET M
+      tick(4);
       if ((regs.raf.F & BIT_S)) {
         pop2(PC);
 	vc.rd+= 2;
+	tick(6);
       }
       break;
     default:
@@ -1148,19 +1375,23 @@
   switch(code)
     {
     case 0xC4: // CALL NZ,nnnn
+      tick(9);
       if (!(regs.raf.F & BIT_Z)) {
         push2(PC+2);
         PC = fetch2();
 	vc.wr+= 2;
+	tick(7);
       } else {
         fetch2();
       }
       break;
     case 0xCC: // CALL Z,nnnn
+      tick(9);
       if (regs.raf.F & BIT_Z) {
         push2(PC+2);
         PC = fetch2();
 	vc.wr+= 2;
+	tick(7);
       } else {
         fetch2();
       }
@@ -1169,57 +1400,70 @@
       push2(PC+2);
       PC = fetch2();
       vc.wr+= 2;
+      tick(16);
       break;
     case 0xD4: // CALL NC,nnnn
+      tick(9);
       if (!(regs.raf.F & BIT_C)) {
         push2(PC+2);
         PC = fetch2();
 	vc.wr+= 2;
+	tick(7);
       } else {
         fetch2();
       }
       break;
     case 0xDC: // CALL C,nnnn
+      tick(9);
       if (regs.raf.F & BIT_C) {
         push2(PC+2);
         PC = fetch2();
 	vc.wr+= 2;
+	tick(7);
       } else {
         fetch2();
       }
       break;
     case 0xE4: // CALL PO,nnnn
+      tick(9);
       if (!(regs.raf.F & BIT_P)) {
         push2(PC+2);
         PC = fetch2();
 	vc.wr+= 2;
+	tick(7);
       } else {
         fetch2();
       }
       break;
     case 0xEC: // CALL PE,nnnn
+      tick(9);
       if (regs.raf.F & BIT_P) {
         push2(PC+2);
         PC = fetch2();
 	vc.wr+= 2;
+	tick(7);
       } else {
         fetch2();
       }
       break;
     case 0xF4: // CALL P,nnnn
+      tick(9);
       if (!(regs.raf.F & BIT_S)) {
         push2(PC+2);
         PC = fetch2();
 	vc.wr+= 2;
+	tick(7);
       } else {
         fetch2();
       }
       break;
     case 0xFC: // CALL M,nnnn
+      tick(9);
       if (regs.raf.F & BIT_S) {
         push2(PC+2);
         PC = fetch2();
 	vc.wr+= 2;
+	tick(7);
       } else {
         fetch2();
       }
@@ -1237,6 +1481,7 @@
 {
   t_addr a= fetch();
   outputs->write(a, regs.raf.A);
+  tick(10);
   return(resGO);
 }
 
@@ -1248,19 +1493,23 @@
     case 0xC5: // PUSH BC
       push2(regs.BC);
       vc.wr+= 2;
+      tick(10);
       break;
     case 0xD5: // PUSH DE
       push2(regs.DE);
       vc.wr+= 2;
+      tick(10);
       break;
     case 0xE5: // PUSH HL
       push2(regs.HL);
       vc.wr+= 2;
+      tick(10);
       break;
     case 0xF5: // PUSH AF
       push1(regs.raf.A);
       push1(regs.raf.F);
       vc.wr+= 2;
+      tick(10);
       break;
     default:
       return(resINV_INST);
@@ -1287,6 +1536,7 @@
   regs.aBC = regs.BC;
   regs.BC = tempw;
 
+  tick(3);
   return(resGO);
 }
 
@@ -1295,6 +1545,7 @@
 {
   t_addr a= fetch();
   regs.raf.A= inputs->read(a);
+  tick(10);
   return(resGO);
 }
 
@@ -1305,21 +1556,27 @@
     {
     case 0x90: // SUB B
       sub_A_bytereg(regs.bc.h);
+      tick(3);
       break;
     case 0x91: // SUB C
       sub_A_bytereg(regs.bc.l);
+      tick(3);
       break;
     case 0x92: // SUB D
       sub_A_bytereg(regs.de.h);
+      tick(3);
       break;
     case 0x93: // SUB E
       sub_A_bytereg(regs.de.l);
+      tick(3);
       break;
     case 0x94: // SUB H
       sub_A_bytereg(regs.hl.h);
+      tick(3);
       break;
     case 0x95: // SUB L
       sub_A_bytereg(regs.hl.l);
+      tick(3);
       break;
     case 0x96: // SUB (HL)
       {
@@ -1327,16 +1584,19 @@
         tmp1 = get1(regs.HL);
         sub_A_bytereg(tmp1);
 	vc.rd++;
+	tick(6);
       }
       break;
     case 0x97: // SUB A
       sub_A_bytereg(regs.raf.A);
+      tick(3);
       break;
     case 0xD6: // SUB nn
       {
 	unsigned char tmp1;
         tmp1 = fetch();
         sub_A_bytereg(tmp1);
+	tick(6);
       }
       break;
     default:
@@ -1355,21 +1615,25 @@
       regs.BC = get2(regs.SP);
       regs.SP+=2;
       vc.rd+= 2;
+      tick(9);
       break;
     case 0xD1: // POP DE
       regs.DE = get2(regs.SP);
       regs.SP+=2;
       vc.rd+= 2;
+      tick(9);
       break;
     case 0xE1: // POP HL
       regs.HL = get2(regs.SP);
       regs.SP+=2;
       vc.rd+= 2;
+      tick(9);
       break;
     case 0xF1: // POP AF
       regs.raf.F = get1(regs.SP++);
       regs.raf.A = get1(regs.SP++);
       vc.rd+= 2;
+      tick(9);
       break;
     default:
       return(resINV_INST);
@@ -1389,10 +1653,12 @@
       } else {
         fetch2();
       }
+      tick(9);
       break;
       
     case 0xC3: // JP nnnn
       PC = fetch2();
+      tick(9);
       break;
       
     case 0xCA: // JP Z,nnnn
@@ -1401,6 +1667,7 @@
       } else {
         fetch2();
       }
+      tick(9);
       break;
       
     case 0xD2: // JP NC,nnnn
@@ -1409,6 +1676,7 @@
       } else {
         fetch2();
       }
+      tick(9);
       break;
       
     case 0xDA: // JP C,nnnn
@@ -1417,6 +1685,7 @@
       } else {
         fetch2();
       }
+      tick(9);
       break;
       
     case 0xE2: // JP PO,nnnn
@@ -1425,10 +1694,12 @@
       } else {
         fetch2();
       }
+      tick(9);
       break;
       
     case 0xE9: // JP (HL)
       PC = regs.HL;
+      tick(3);
       break;
       
     case 0xEA: // JP PE,nnnn
@@ -1437,6 +1708,7 @@
       } else {
         fetch2();
       }
+      tick(9);
       break;
       
     case 0xF2: // JP P,nnnn (positive)
@@ -1445,6 +1717,7 @@
       } else {
         fetch2();
       }
+      tick(9);
       break;
       
     case 0xFA: // JP M,nnnn (sign negative)
@@ -1453,6 +1726,7 @@
       } else {
         fetch2();
       }
+      tick(9);
       break;
     default:
       return(resINV_INST);
@@ -1465,6 +1739,7 @@
 cl_z80::inst_di(t_mem code)
 {
   /* disable interrupts */
+  tick(3);
   return(resGO);
 }
 
@@ -1472,6 +1747,7 @@
 cl_z80::inst_ei(t_mem code)
 {
   /* enable interrupts */
+  tick(3);
   return(resGO);
 }
 
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/z80.src/inst_ddcb.cc sdcc-4.2.0+dfsg/sim/ucsim/z80.src/inst_ddcb.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/z80.src/inst_ddcb.cc	2002-01-28 10:19:59.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/z80.src/inst_ddcb.cc	2020-03-27 20:18:53.000000000 +0000
@@ -26,11 +26,11 @@
 02111-1307, USA. */
 /*@1@*/
 
-#include "ddconfig.h"
+//#include "ddconfig.h"
 
 // local
 #include "z80cl.h"
-#include "regsz80.h"
+//#include "regsz80.h"
 #include "z80mac.h"
 
 
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/z80.src/inst_dd.cc sdcc-4.2.0+dfsg/sim/ucsim/z80.src/inst_dd.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/z80.src/inst_dd.cc	2011-10-09 18:21:10.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/z80.src/inst_dd.cc	2020-03-27 20:18:53.000000000 +0000
@@ -28,7 +28,7 @@
 02111-1307, USA. */
 /*@1@*/
 
-#include "ddconfig.h"
+//#include "ddconfig.h"
 
 // local
 #include "z80cl.h"
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/z80.src/inst_ed.cc sdcc-4.2.0+dfsg/sim/ucsim/z80.src/inst_ed.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/z80.src/inst_ed.cc	2019-02-11 13:12:14.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/z80.src/inst_ed.cc	2020-08-01 16:50:18.000000000 +0000
@@ -26,15 +26,15 @@
 02111-1307, USA. */
 /*@1@*/
 
-#include "ddconfig.h"
+//#include "ddconfig.h"
 
 // local
 #include "z80cl.h"
-#include "regsz80.h"
+//#include "regsz80.h"
 #include "z80mac.h"
 
 
-#define tst_A_bytereg(br) {                                \
+#define tst_A_bytereg(br) {                                    \
    ubtmp = regs.raf.A & (br);                                  \
    regs.raf.F &= ~(BIT_ALL);  /* clear these */                \
    regs.raf.F |= BIT_A;                                        \
@@ -48,50 +48,68 @@
 {
   unsigned short tw;
   u8_t     ubtmp;
-  
+
+  if (type->type == CPU_Z80N)
+    {
+      int ret;
+      if (inst_z80n(code, &ret))
+        return ret;
+    }
+
   if (code < 0x40)
     {
       if (!(type->type & (CPU_Z180 | CPU_EZ80)))
         return resINV_INST;
-      
+
       switch ( code & 0x07 )
         {
         case 0:  //  IN0
           ubtmp = fetch1( );
           reg_g_store( (code >> 3) & 0x07, in_byte( ubtmp ) );
           return resGO;
-          
+
         case 1:  // OUT0
           ubtmp = fetch1( );
           out_byte( ubtmp, reg_g_read( (code >> 3) & 0x07 ) );
           return resGO;
-          
+
         case 4:  // TST
           tst_A_bytereg(reg_g_read( (code >> 3) & 0x07 ));
           return resGO;
-          
+
         default:
           return resINV_INST;
         }
     }
-  
+
   switch(code)
     {
-
-#if 0
     case 0x40: // IN B,(C)
+      regs.bc.h= inputs->read((type->type==CPU_Z80N)?regs.BC:regs.bc.l);
+      regs.raf.F &= ~(BIT_N | BIT_P);
+      if (parity(regs.bc.h)) regs.raf.F |= BIT_P;
+      vc.rd++;
+      tick(11);
       return(resGO);
+      
     case 0x41: // OUT (C),B
+      outputs->write((type->type==CPU_Z80N)?regs.BC:regs.bc.l, regs.bc.h);
+      vc.wr++;
+      tick(11);
       return(resGO);
-#endif
+
     case 0x42: // SBC HL,BC
       sbc_HL_wordreg(regs.BC);
+      tick(14);
       return(resGO);
+      
     case 0x43: // LD (nnnn),BC
       tw = fetch2();
       store2(tw, regs.BC);
       vc.wr+= 2;
+      tick(19);
       return(resGO);
+      
     case 0x44: // NEG
       regs.raf.F &= ~(BIT_ALL);  /* clear these */
       if (regs.raf.A != 0)    regs.raf.F |= BIT_C;
@@ -101,111 +119,178 @@
       regs.raf.F |= BIT_N; /* not addition */
       if (regs.raf.A == 0)    regs.raf.F |= BIT_Z;
       if (regs.raf.A & 0x80)  regs.raf.F |= BIT_S;
+      tick(7);
       return(resGO);
+      
     case 0x45: // RETN (return from non-maskable interrupt)
       pop2(PC);
       vc.rd+= 2;
+      tick(13);
       return(resGO);
-#if 0
+
     case 0x46: // IM 0
       /* interrupt device puts opcode on data bus */
+      tick(7);
       return(resGO);
-#endif
+
     case 0x47: // LD IV,A
       regs.iv = regs.raf.A;
+      tick(8);
       return(resGO);
-      
+
     case 0x48: // IN C,(C)
+      regs.bc.l= inputs->read((type->type==CPU_Z80N)?regs.BC:regs.bc.l);
+      regs.raf.F &= ~(BIT_N | BIT_P);
+      if (parity(regs.bc.l)) regs.raf.F |= BIT_P;
       vc.rd++;
+      tick(11);
       return(resGO);
+      
     case 0x49: // OUT (C),C
+      outputs->write((type->type==CPU_Z80N)?regs.BC:regs.bc.l, regs.bc.l);
       vc.wr++;
+      tick(11);
       return(resGO);
 
     case 0x4A: // ADC HL,BC
       adc_HL_wordreg(regs.BC);
+      tick(14);
       return(resGO);
+      
     case 0x4B: // LD BC,(nnnn)
       tw = fetch2();
       regs.BC = get2(tw);
       vc.rd+= 2;
+      tick(14);
       return(resGO);
+      
     case 0x4C: // MLT BC
       if (!(type->type & (CPU_Z180 | CPU_EZ80)))
         return(resINV_INST);
       regs.BC = (unsigned long)(regs.bc.h) * (unsigned long)(regs.bc.l);
       return(resGO);
+      
     case 0x4D: // RETI (return from interrupt)
       pop2(PC);
       vc.rd+= 2;
+      tick(13);
       return(resGO);
+      
     case 0x4F: // LD R,A
-      /* Load "refresh" register(whats that?) */
+      regs.R= regs.raf.A;
+      tick(8);
       return(resGO);
 
     case 0x50: // IN D,(C)
+      regs.de.h= inputs->read((type->type==CPU_Z80N)?regs.BC:regs.bc.l);
+      regs.raf.F &= ~(BIT_N | BIT_P);
+      if (parity(regs.de.h)) regs.raf.F |= BIT_P;
       vc.rd++;
+      tick(11);
       return(resGO);
+      
     case 0x51: // OUT (C),D
+      outputs->write((type->type==CPU_Z80N)?regs.BC:regs.bc.l, regs.de.h);
       vc.wr++;
+      tick(11);
       return(resGO);
 
     case 0x52: // SBC HL,DE
       sbc_HL_wordreg(regs.DE);
+      tick(14);
       return(resGO);
+      
     case 0x53: // LD (nnnn),DE
       tw = fetch2();
       store2(tw, regs.DE);
       vc.wr+= 2;
+      tick(19);
       return(resGO);
-#if 0
+
     case 0x56: // IM 1
+      tick(7);
       return(resGO);
-#endif
+
     case 0x57: // LD A,IV
       regs.raf.A = regs.iv;
+      SET_S(regs.iv);
+      SET_Z(regs.iv);
+      regs.raf.F &= ~(BIT_A | BIT_N | BIT_P);
+      if (IFF2) regs.raf.F |= BIT_P;
+      tick(8);
       return(resGO);
-      
+
     case 0x58: // IN E,(C)
+      regs.de.l= inputs->read((type->type==CPU_Z80N)?regs.BC:regs.bc.l);
+      regs.raf.F &= ~(BIT_N | BIT_P);
+      if (parity(regs.de.l)) regs.raf.F |= BIT_P;
       vc.rd++;
+      tick(11);
       return(resGO);
+      
     case 0x59: // OUT (C),E
+      outputs->write((type->type==CPU_Z80N)?regs.BC:regs.bc.l, regs.de.l);
       vc.wr++;
+      tick(11);
       return(resGO);
 
     case 0x5A: // ADC HL,DE
       adc_HL_wordreg(regs.DE);
+      tick(14);
       return(resGO);
+      
     case 0x5B: // LD DE,(nnnn)
       tw = fetch2();
       regs.DE = get2(tw);
       vc.rd+= 2;
+      tick(19);
       return(resGO);
+      
     case 0x5C: // MLT DE
       if (!(type->type & (CPU_Z180 | CPU_EZ80)))
         return(resINV_INST);
       regs.DE = (unsigned long)(regs.de.h) * (unsigned long)(regs.de.l);
       return(resGO);
-#if 0
+
     case 0x5E: // IM 2
+      tick(7);
       return(resGO);
+
     case 0x5F: // LD A,R
+      regs.raf.A= regs.R;
+      SET_S(regs.R);
+      SET_Z(regs.R);
+      regs.raf.F &= ~(BIT_A | BIT_N | BIT_P);
+      if (IFF2) regs.raf.F |= BIT_P;
+      tick(7);
       return(resGO);
+
     case 0x60: // IN H,(C)
+      regs.hl.h= inputs->read((type->type==CPU_Z80N)?regs.BC:regs.bc.l);
+      regs.raf.F &= ~(BIT_N | BIT_P);
+      if (parity(regs.hl.h)) regs.raf.F |= BIT_P;
       vc.rd++;
+      tick(11);
       return(resGO);
+      
     case 0x61: // OUT (C),H
+      outputs->write((type->type==CPU_Z80N)?regs.BC:regs.bc.l, regs.hl.h);
       vc.wr++;
+      tick(11);
       return(resGO);
-#endif
+
     case 0x62: // SBC HL,HL
       sbc_HL_wordreg(regs.HL);
+      tick(14);
       return(resGO);
+      
     case 0x63: // LD (nnnn),HL opcode 22 does the same faster
       tw = fetch2();
       store2(tw, regs.HL);
       vc.wr+= 2;
+      tick(19);
       return(resGO);
+      
     case 0x64:
       if (!(type->type & (CPU_Z180 | CPU_EZ80)))
         return(resINV_INST);
@@ -217,23 +302,35 @@
       ubtmp = get1(regs.HL);
       store1(regs.HL, (ubtmp >> 4) | (regs.raf.A << 4));
       regs.raf.A = (regs.raf.A & 0xf0) | (ubtmp & 0x0f);
+      tick(17);
       return(resGO);
 
     case 0x68: // IN L,(C)
+      regs.hl.l= inputs->read((type->type==CPU_Z80N)?regs.BC:regs.bc.l);
+      regs.raf.F &= ~(BIT_N | BIT_P);
+      if (parity(regs.hl.l)) regs.raf.F |= BIT_P;
       vc.rd++;
+      tick(11);
       return(resGO);
+      
     case 0x69: // OUT (C),L
+      outputs->write((type->type==CPU_Z80N)?regs.BC:regs.bc.l, regs.hl.l);
       vc.wr++;
+      tick(11);
       return(resGO);
 
     case 0x6A: // ADC HL,HL
       adc_HL_wordreg(regs.HL);
+      tick(14);
       return(resGO);
+      
     case 0x6B: // LD HL,(nnnn) opcode 2A does the same faster
       tw = fetch2();
       regs.HL = get2(tw);
       vc.rd+= 2;
+      tick(19);
       return(resGO);
+      
     case 0x6C: // MLT HL
       if (!(type->type & (CPU_Z180 | CPU_EZ80)))
         return(resINV_INST);
@@ -244,38 +341,61 @@
       ubtmp = get1(regs.HL);
       store1(regs.HL, (ubtmp << 4) | (regs.raf.A & 0x0f));
       regs.raf.A = (regs.raf.A & 0xf0) | (ubtmp >> 4);
+      tick(17);
       return(resGO);
 
     case 0x70: // IN (C)  set flags only (TSTI)
-      vc.rd++;
-      return(resGO);
+      {
+        u8_t x= inputs->read((type->type==CPU_Z80N)?regs.BC:regs.bc.l);
+        regs.raf.F &= ~(BIT_N | BIT_P);
+        if (parity(x)) regs.raf.F |= BIT_P;
+        vc.rd++;
+	tick(11);
+        return(resGO);
+      }
+      
     case 0x71: //  OUT (C),0
+      outputs->write((type->type==CPU_Z80N)?regs.BC:regs.bc.l, 0);
       vc.wr++;
+      tick(11);
       return(resGO);
 
     case 0x72: // SBC HL,SP
       sbc_HL_wordreg(regs.SP);
+      tick(14);
       return(resGO);
+      
     case 0x73: // LD (nnnn),SP
       tw = fetch2();
       store2(tw, regs.SP);
       vc.wr+= 2;
+      tick(19);
       return(resGO);
 
     case 0x78: // IN A,(C)
+      regs.raf.A= inputs->read((type->type==CPU_Z80N)?regs.BC:regs.bc.l);
+      regs.raf.F &= ~(BIT_N | BIT_P);
+      if (parity(regs.raf.A)) regs.raf.F |= BIT_P;
       vc.rd++;
+      tick(11);
       return(resGO);
+      
     case 0x79: // OUT (C),A
+      outputs->write((type->type==CPU_Z80N)?regs.BC:regs.bc.l, regs.raf.A);
       vc.wr++;
+      tick(11);
       return(resGO);
 
     case 0x7A: // ADC HL,SP
       adc_HL_wordreg(regs.SP);
+      tick(14);
       return(resGO);
+      
     case 0x7B: // LD SP,(nnnn)
       tw = fetch2();
       regs.SP = get2(tw);
       vc.rd+= 2;
+      tick(19);
       return(resGO);
 
     case 0x7C: // MLT SP
@@ -283,6 +403,7 @@
       return(resINV_INST);
       //regs.SP = (unsigned long)(regs.sp.h) * (unsigned long)(regs.sp.l);
       return(resGO);
+
     case 0xA0: // LDI
       // BC - count, sourc=HL, dest=DE.  *DE++ = *HL++, --BC until zero
       regs.raf.F &= ~(BIT_P | BIT_N | BIT_A);  /* clear these */
@@ -291,7 +412,9 @@
       ++regs.DE;
       --regs.BC;
       if (regs.BC != 0) regs.raf.F |= BIT_P;
+      tick(15);
       return(resGO);
+
     case 0xA1: // CPI
       // compare acc with mem(HL), if ACC=0 set Z flag.  Incr HL, decr BC.
       {
@@ -301,12 +424,36 @@
         ++regs.HL;
         --regs.BC;
         if (regs.BC != 0) regs.raf.F |= BIT_P;
+	tick(15);
       }
       return(resGO);
 
     case 0xA2: // INI
+      this->store1(regs.HL, inputs->read((type->type==CPU_Z80N)?regs.BC:regs.bc.l));
+      vc.rd++;
+      vc.wr++;
+      if (type->type==CPU_Z80N)
+        regs.raf.F |= BIT_N;
+      else
+        regs.raf.F &= ~(BIT_N);
+      regs.HL++;
+      regs.bc.h--;
+      SET_Z(regs.bc.h);
+      tick(16);
       return(resGO);
+
     case 0xA3: // OUTI
+      regs.bc.h--;
+      outputs->write((type->type==CPU_Z80N)?regs.BC:regs.bc.h, this->get1(regs.HL));
+      vc.wr++;
+      vc.rd++;
+      SET_Z(regs.bc.h);
+      if (type->type==CPU_Z80N)
+        regs.raf.F |= BIT_N;
+      else
+        regs.raf.F &= ~(BIT_N);
+      regs.HL++;
+      tick(16);
       return(resGO);
 
     case 0xA8: // LDD
@@ -319,7 +466,9 @@
       if (regs.BC != 0) regs.raf.F |= BIT_P;
       vc.rd++;
       vc.wr++;
+      tick(15);
       return(resGO);
+      
     case 0xA9: // CPD
 /* fixme: checkme, compare to other emul. */
 
@@ -331,12 +480,34 @@
       --regs.BC;
       if (regs.BC != 0) regs.raf.F |= BIT_P;
       vc.rd++;
-      
+      tick(15);
       return(resGO);
 
     case 0xAA: // IND
+      this->store1(regs.HL, inputs->read((type->type==CPU_Z80N)?regs.BC:regs.bc.l));
+      vc.rd++;
+      vc.wr++;
+      if (type->type==CPU_Z80N)
+        regs.raf.F |= BIT_N;
+      else
+        regs.raf.F &= ~(BIT_N);
+      regs.HL--;
+      regs.bc.h--;
+      SET_Z(regs.bc.h);
+      tick(15);
       return(resGO);
     case 0xAB: // OUTD
+      regs.bc.h--;
+      outputs->write((type->type==CPU_Z80N)?regs.BC:regs.bc.l, this->get1(regs.HL));
+      vc.rd++;
+      vc.wr++;
+      if (type->type==CPU_Z80N)
+        regs.raf.F |= BIT_N;
+      else
+        regs.raf.F &= ~(BIT_N);
+      regs.HL--;
+      SET_Z(regs.bc.h);
+      tick(15);
       return(resGO);
 
     case 0xB0: // LDIR
@@ -347,8 +518,10 @@
         ++regs.HL;
         ++regs.DE;
         --regs.BC;
-	vc.rd++;
-	vc.wr++;
+        vc.rd++;
+        vc.wr++;
+	tick(15);
+	if (regs.BC) tick(5);
       } while (regs.BC != 0);
       return(resGO);
 
@@ -360,26 +533,59 @@
         if((regs.raf.A - get1(regs.HL)) == 0)
           regs.raf.F |= BIT_Z;
         else
-          regs.raf.F &= ~BIT_Z;
+          regs.raf.F &= ~(BIT_Z);
         if((regs.raf.A - get1(regs.HL)) & 0x80)
           regs.raf.F |= BIT_S;
         else
-          regs.raf.F &= ~BIT_S;
+          regs.raf.F &= ~(BIT_S);
 /* fixme: set BIT_A correctly. */
         ++regs.HL;
         --regs.BC;
-	vc.rd++;
+        vc.rd++;
+	tick(15);
+	if (regs.BC) tick(5);
       } while (regs.BC != 0 && (regs.raf.F & BIT_Z) == 0);
       if(regs.BC != 0)
         regs.raf.F |= BIT_P;
 
       return(resGO);
-#if 0
+
     case 0xB2: // INIR
+      do {
+        this->store1(regs.HL, inputs->read((type->type==CPU_Z80N)?regs.BC:regs.bc.l));
+        vc.rd++;
+        vc.wr++;
+        if (type->type==CPU_Z80N)
+          regs.raf.F |= BIT_N;
+        else
+          regs.raf.F &= ~(BIT_N);
+        regs.HL++;
+        regs.bc.h--;
+        SET_Z(regs.bc.h);
+	tick(15);
+	if (regs.BC) tick(5);
+       }
+      while (regs.BC);
       return(resGO);
+      
     case 0xB3: // OTIR
+      do {
+        regs.bc.h--;
+        outputs->write((type->type==CPU_Z80N)?regs.BC:regs.bc.h, this->get1(regs.HL));
+        vc.wr++;
+        vc.rd++;
+        SET_Z(regs.bc.h);
+        if (type->type==CPU_Z80N)
+          regs.raf.F |= BIT_N;
+        else
+          regs.raf.F &= ~(BIT_N);
+        regs.HL++;
+	tick(15);
+	if (regs.BC) tick(5);
+      }
+      while (regs.BC);
       return(resGO);
-#endif
+
     case 0xB8: // LDDR
       // BC - count, source=HL, dest=DE.  *DE-- = *HL--, --BC until zero
       regs.raf.F &= ~(BIT_P | BIT_N | BIT_A);  /* clear these */
@@ -388,8 +594,10 @@
         --regs.HL;
         --regs.DE;
         --regs.BC;
-	vc.rd++;
-	vc.wr++;
+        vc.rd++;
+        vc.wr++;
+	tick(15);
+	if (regs.BC) tick(5);
       } while (regs.BC != 0);
       return(resGO);
     case 0xB9: // CPDR
@@ -402,20 +610,52 @@
         }
         --regs.HL;
         --regs.BC;
-	vc.rd++;
+        vc.rd++;
+	tick(15);
+	if (regs.BC) tick(5);
       } while (regs.BC != 0);
       return(resGO);
-#if 0
+
     case 0xBA: // INDR
+      do {
+        this->store1(regs.HL, inputs->read((type->type==CPU_Z80N)?regs.BC:regs.bc.l));
+        vc.rd++;
+        vc.wr++;
+        if (type->type==CPU_Z80N)
+          regs.raf.F |= BIT_N;
+        else
+          regs.raf.F &= ~(BIT_N);
+        regs.HL--;
+        regs.bc.h--;
+        SET_Z(regs.bc.h);
+	tick(15);
+	if (regs.BC) tick(5);
+      }
+      while (regs.BC);
       return(resGO);
+      
     case 0xBB: // OTDR
+      do {
+        regs.bc.h--;
+        outputs->write((type->type==CPU_Z80N)?regs.BC:regs.bc.l, this->get1(regs.HL));
+        vc.rd++;
+        vc.wr++;
+        if (type->type==CPU_Z80N)
+          regs.raf.F |= BIT_N;
+        else
+          regs.raf.F &= ~(BIT_N);
+        regs.HL--;
+        SET_Z(regs.bc.h);
+	tick(15);
+	if (regs.BC) tick(5);
+      }
+      while (regs.BC);
       return(resGO);
-#endif
 
     default:
       return(resINV_INST);
     }
-  
+
   return(resGO);
 }
 
@@ -426,7 +666,7 @@
 
   if (fetch(&code))
     return(resBREAKPOINT);
-  
+
   return inst_ed_(code);
 }
 
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/z80.src/inst_ed_r2k.cc sdcc-4.2.0+dfsg/sim/ucsim/z80.src/inst_ed_r2k.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/z80.src/inst_ed_r2k.cc	2018-01-25 13:48:09.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/z80.src/inst_ed_r2k.cc	2020-10-01 13:31:34.000000000 +0000
@@ -1,474 +1,520 @@
-/*
- * Simulator of microcontrollers (inst_ed.cc)
- *   ED escaped multi-byte opcodes for Z80.
- *
- * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
- *
- * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
- *
- */
-
-/* This file is part of microcontroller simulator: ucsim.
-
-UCSIM is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2 of the License, or
-(at your option) any later version.
-
-UCSIM is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with UCSIM; see the file COPYING.  If not, write to the Free
-Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-02111-1307, USA. */
-/*@1@*/
-
-#include "ddconfig.h"
-
-// local
-#include "r2kcl.h"
-#include "z80mac.h"
-
-
-int  cl_r2k::inst_ed_(t_mem code)
-{
-  unsigned short tw;
-  
-  switch(code)
-    {
-  case 0x41:
-    regs.aBC = regs.DE;
-    break;
-    
-  case 0x42: // SBC HL,BC
-    sbc_HL_wordreg(regs.BC);
-    break;
-    
-  case 0x43: // LD (nnnn),BC
-    tw = fetch2();
-    store2(tw, regs.BC);
-    vc.wr+= 2;
-    break;
-    
-  case 0x44: // NEG
-    regs.raf.F &= ~(BIT_ALL);  /* clear these */
-    if (regs.raf.A != 0)    regs.raf.F |= BIT_C;

-    if (regs.raf.A == 0x80) regs.raf.F |= BIT_P;

-    if ((regs.raf.A & 0x0F) != 0) regs.raf.F |= BIT_A;

-    regs.raf.A = 0 - regs.raf.A;

-    regs.raf.F |= BIT_N; /* not addition */

-    if (regs.raf.A == 0)    regs.raf.F |= BIT_Z;

-    if (regs.raf.A & 0x80)  regs.raf.F |= BIT_S;

-    break;
-    
-  case 0x46: // ipset0
-  case 0x56: // ipset1
-  case 0x4E: // ipset2
-  case 0x5E: // ipset3
-    ip = ((ip << 2) & 0xFC);
-    ip |= (code >> 3) & 0x03;
-    break;
-    
-  case 0x47: // LD EIR,A
-    eir = regs.raf.A;
-    break;
-  case 0x49:
-    regs.aBC = regs.BC;
-    break;
-    
-  case 0x4A: // ADC HL,BC
-    adc_HL_wordreg(regs.BC);
-    break;
-
-  case 0x4B: // LD BC,(nnnn)
-    tw = fetch2();
-    regs.BC = get2(tw);
-    vc.rd+= 2;
-    break;
-    
-  case 0x4D: // RETI
-    ip=get1(regs.SP); regs.SP+=1;
-    pop2(PC);
-    vc.rd+= 2;
-    // TODO: chained-atomic, so set some marker
-    break;
-
-    // 0x4E: see 0x46
-  case 0x4F:
-    iir = regs.raf.A;
-    break;
-    
-  case 0x51:
-    regs.aDE = regs.DE;
-    break;
-
-  case 0x52: // SBC HL,DE
-    sbc_HL_wordreg(regs.DE);
-    break;
-  case 0x53: // LD (nnnn),DE
-    tw = fetch2();
-    store2(tw, regs.DE);
-    vc.rd+= 2;
-    break;
-    
-  case 0x54: // EX (SP),HL
-    tw = get2(regs.SP);
-    store2( regs.SP, regs.HL );
-    regs.HL = tw;
-    vc.rd+= 2;
-    vc.wr+= 2;
-    break;
-    
-    // 0x56: see 0x46
-  case 0x57:
-    regs.raf.A = eir;
-    break;
-    
-  case 0x59: // LD DE', BC
-    regs.aDE = regs.BC;
-    break;
-    
-  case 0x5A: // ADC HL,DE
-    adc_HL_wordreg(regs.DE);
-    break;
-    
-  case 0x5B: // LD DE,(nnnn)
-    tw = fetch2();
-    regs.DE = get2(tw);
-    vc.rd+= 2;
-    break;
-    
-  case 0x5D: // ipres
-    ip = ((ip >> 2) & 0x3F) | ((ip & 0x03) << 6);
-    break;
-    
-    // 0x5E: see 0x46
-
-  case 0x5F: // LD A,IIR
-    regs.raf.A = iir;
-    break;
-    
-  case 0x61: // LD HL',DE
-    regs.aHL = regs.DE;
-    break;
-    
-  case 0x62: // SBC HL,HL
-    sbc_HL_wordreg(regs.HL);
-    break;
-    
-  case 0x63: // LD (nnnn),HL opcode 22 does the same faster
-    tw = fetch2();
-    store2(tw, regs.HL);
-    vc.wr+= 2;
-    break;
-    
-  case 0x67: // LD XPC,A
-    mmu.xpc = regs.raf.A;
-    break;
-    
-  case 0x69: // LD HL',BC
-    regs.aHL = regs.BC;
-    break;
-    
-  case 0x6A: // ADC HL,HL
-    adc_HL_wordreg(regs.HL);
-    break;
-    
-  case 0x6B: // LD HL,(nnnn) opcode 2A does the same faster
-    tw = fetch2();
-    regs.HL = get2(tw);
-    vc.rd+= 2;
-    break;
-    
-  case 0x72: // SBC HL,SP
-    sbc_HL_wordreg(regs.SP);
-    break;
-  case 0x73: // LD (nnnn),SP
-    tw = fetch2();
-    store2(tw, regs.SP);
-    vc.wr+= 2;
-    break;
-    
-  case 0x76: // PUSH IP
-    push1(ip);
-    vc.wr+= 2;
-    break;
-    
-  case 0x77: // LD A,XPC
-    regs.raf.A = mmu.xpc;
-    break;
-    
-  case 0x7A: // ADC HL,SP
-    adc_HL_wordreg(regs.SP);
-    break;
-  case 0x7B: // LD SP,(nnnn)
-    tw = fetch2();
-    regs.SP = get2(tw);
-    vc.rd+= 2;
-    break;
-    
-  case 0x7D: // LD IY, HL
-    regs.IY = regs.HL;
-    break;
-
-  case 0x7E:
-    ip=get1(regs.SP); regs.SP+=1;
-    vc.rd++;
-    break;
-    
-  case 0xA0: // LDI
-    // BC - count, sourc=HL, dest=DE.  *DE++ = *HL++, --BC until zero
-    regs.raf.F &= ~(BIT_P | BIT_N | BIT_A);  /* clear these */
-    store1(regs.DE, get1(regs.HL));
-    ++regs.HL;
-    ++regs.DE;
-    --regs.BC;
-    vc.rd++;
-    vc.wr++;
-    if (regs.BC != 0) regs.raf.F |= BIT_P;
-    return(resGO);
-    
-  case 0xA8: // LDD
-    // BC - count, source=HL, dest=DE.  *DE-- = *HL--, --BC until zero
-    regs.raf.F &= ~(BIT_P | BIT_N | BIT_A);  /* clear these */
-    store1(regs.DE, get1(regs.HL));
-    --regs.HL;
-    --regs.DE;
-    --regs.BC;
-    vc.rd++;
-    vc.wr++;
-    if (regs.BC != 0) regs.raf.F |= BIT_P;
-    return(resGO);
-    
-  case 0xB0: // LDIR
-    // BC - count, sourc=HL, dest=DE.  *DE++ = *HL++, --BC until zero
-    regs.raf.F &= ~(BIT_P | BIT_N | BIT_A);  /* clear these */
-    
-    tw = get1(regs.HL);
-    store1(regs.DE, tw);
-    ++regs.HL;
-    ++regs.DE;
-    --regs.BC;
-    vc.rd++;
-    vc.wr++;
-    if (regs.BC != 0)
-      PC = ins_start;
-    return(resGO);
-    
-  case 0xB8: // LDDR
-    // BC - count, source=HL, dest=DE.  *DE-- = *HL--, --BC until zero
-    regs.raf.F &= ~(BIT_P | BIT_N | BIT_A);  /* clear these */
-    
-    tw = get1(regs.HL);
-    store1(regs.DE, tw);
-    --regs.HL;
-    --regs.DE;
-    --regs.BC;
-    vc.rd++;
-    vc.wr++;
-    
-    if (regs.BC != 0)
-      PC = ins_start;
-    return(resGO);
-    
-  case 0xEA: // CALL (HL)
-    push2(PC);
-    PC = regs.HL;
-    vc.wr+= 2;
-    return(resGO);
-    
-  
-  default:
-    return(resINV_INST);
-    }
-  
-  return(resGO);
-}
-
-int  cl_r3ka::inst_ed_(t_mem code)
-{
-  u8_t  tb;
-  
-  switch(code)
-    {
-    case  0x66:  // PUSH SU
-      push1(SU);
-      vc.wr++;
-      return(resGO);
-      
-    case  0x6E:  // POP  SU
-      SU = get1(regs.SP);
-      regs.SP++;
-      vc.rd++;
-      return(resGO);
-      
-    case  0x6F:  // SETUSR
-      SU = ((SU << 2) & 0xFC) | 0x01;
-      return(resGO);
-      
-    case  0x7D:  // SURES
-      SU = ((SU >> 2) & 0x3F) | ((SU << 6) & 0xC0);
-      return(resGO);
-      
-    case  0x7F:  // RDMODE
-      regs.raf.F &= ~(BIT_C);
-      if (SU & 0x01)
-        regs.raf.F |= BIT_C;
-      return(resGO);
-      
-    case  0x90:  // LDISR
-      // repeat (cnt=BC) { (DE) <= (HL++) }  /* normally has io prefix */
-      /* TODO: fix IOI/IOE behavior */
-      tb = get1(regs.HL);
-      store1( regs.DE, tb );
-      regs.HL++;
-      regs.BC--;
-      vc.rd++;
-      vc.wr++;
-      if (regs.BC)
-        PC = ins_start;
-      return(resGO);
-      
-    case  0x98:  // LDDSR
-      /* TODO: fix IOI/IOE behavior */
-      // repeat (cnt=BC) { (DE) <= (HL--) }  /* normally has io prefix */
-      tb = get1(regs.HL);
-      store1( regs.DE, tb );
-      regs.HL--;
-      regs.BC--;
-      vc.rd++;
-      vc.wr++;
-      if (regs.BC)
-        PC = ins_start;
-      return(resGO);
-
-    case  0xC0:  // UMA
-      // repeat while BC != 0:
-      // {CF:DE':(HL)} <= (IX) + [(IY)*DE + DE' + CF];
-      // BC--; IX++; IY++; HL++;
-      {
-        u32_t  tmp;
-        
-        /* scale a sum for operand pointed to by IY */
-        tmp  = get1(regs.IY);
-        tmp *= regs.DE;
-        tmp += regs.aDE;
-        tmp += (regs.raf.F & BIT_C) ? 1 : 0;
-        
-        /* simple add for operand pointed to by IX */
-        tmp += get1(regs.IX);
-        
-        /* store the result(s) */
-        store1( regs.HL, tmp & 0xFF );
-        regs.aDE = ((tmp >> 8) & 0xFFFF);
-        regs.raf.F &= ~(BIT_C);
-        regs.raf.F |= (tmp >> 24) ? BIT_C : 0;
-	vc.rd+= 2;
-	vc.wr++;
-      }
-      
-      regs.IX++;
-      regs.IY++;
-      regs.HL++;
-      regs.BC--;
-      if (regs.BC)
-        PC = ins_start;
-      return(resGO);
-      
-    case  0xC8:  // UMS
-      // repeat while BC != 0:
-      // {CF:DE':(HL)} <= (IX) - [(IY)*DE + DE' + CF];
-      // BC--; IX++; IY++; HL++;
-      {
-        u32_t  tmp;
-        
-        /* scale a sum for operand pointed to by IY */
-        tmp  = get1(regs.IY);
-        tmp *= regs.DE;
-        tmp += regs.aDE;
-        tmp += (regs.raf.F & BIT_C) ? 1 : 0;
-        
-        /* subtract above from operand pointed to by IX */
-        tmp = get1(regs.IX) - tmp;
-        
-        /* store the result(s) */
-        store1( regs.HL, tmp & 0xFF );
-        regs.aDE = ((tmp >> 8) & 0xFFFF);
-        regs.raf.F &= ~(BIT_C);
-        regs.raf.F |= (tmp >> 24) ? BIT_C : 0;
-	vc.rd+= 2;
-	vc.wr++;
-      }
-      
-      regs.IX++;
-      regs.IY++;
-      regs.HL++;
-      regs.BC--;
-      if (regs.BC)
-        PC = ins_start;
-      return(resGO);
-
-    case  0xD0:  // LSIDR
-      /* TODO: fix IOI/IOE behavior */
-      // repeat (cnt=BC) { (DE++) <= (HL) }  /* normally has io prefix */
-      tb = get1( regs.HL );
-      store1( regs.DE, tb );
-      regs.DE++;
-      regs.BC--;
-      vc.rd++;
-      vc.wr++;
-      if (regs.BC)
-        PC = ins_start;
-      return(resGO);
-      
-    case 0xD8:   // LSDDR
-      /* TODO: fix IOI/IOE behavior */
-      // repeat (cnt=BC) { (DE--) <= (HL) }  /* normally has io prefix */
-      tb = get1( regs.HL );
-      store1( regs.DE, tb );
-      regs.DE--;
-      regs.BC--;
-      vc.rd++;
-      vc.wr++;
-      if (regs.BC)
-        PC = ins_start;
-      return(resGO);
-      
-    case  0xF0:  // LSIR
-      /* TODO: fix IOI/IOE behavior */
-      //  repeat (cnt=BC) { (DE++) <= (HL++) }
-      tb = get1( regs.HL );
-      store1( regs.DE, tb );
-      regs.DE++;
-      regs.HL++;
-      regs.BC--;
-      vc.rd++;
-      vc.wr++;
-      if (regs.BC)
-        PC = ins_start;
-      return(resGO);
-      
-    case  0xF8:  // LSDR
-      /* TODO: fix IOI/IOE behavior */
-      //  repeat (cnt=BC) { (DE--) <= (HL--) }
-      tb = get1( regs.HL );
-      store1( regs.DE, tb );
-      regs.DE--;
-      regs.HL--;
-      regs.BC--;
-      vc.rd++;
-      vc.wr++;
-      if (regs.BC)
-        PC = ins_start;
-      return(resGO);
-      
-    default:
-      return cl_r2k::inst_ed_(code);
-    }
-}
-
-//IDET        system mode violation interrupt if in user mode
-
+/*
+ * Simulator of microcontrollers (inst_ed.cc)
+ *   ED escaped multi-byte opcodes for Z80.
+ *
+ * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
+ *
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+//#include "ddconfig.h"
+
+// local
+#include "r2kcl.h"
+#include "z80mac.h"
+
+
+int  cl_r2k::inst_ed_(t_mem code)
+{
+  unsigned short tw;
+  
+  switch(code)
+    {
+  case 0x41:
+    regs.aBC = regs.DE;
+    break;
+    
+  case 0x42: // SBC HL,BC
+    sbc_HL_wordreg(regs.BC);
+    break;
+    
+  case 0x43: // LD (nnnn),BC
+    tw = fetch2();
+    store2(tw, regs.BC);
+    vc.wr+= 2;
+    break;
+    
+  case 0x44: // NEG
+    regs.raf.F &= ~(BIT_ALL);  /* clear these */
+    if (regs.raf.A != 0)    regs.raf.F |= BIT_C;
+    if (regs.raf.A == 0x80) regs.raf.F |= BIT_P;
+    if ((regs.raf.A & 0x0F) != 0) regs.raf.F |= BIT_A;
+    regs.raf.A = 0 - regs.raf.A;
+    regs.raf.F |= BIT_N; /* not addition */
+    if (regs.raf.A == 0)    regs.raf.F |= BIT_Z;
+    if (regs.raf.A & 0x80)  regs.raf.F |= BIT_S;
+    break;
+
+    case 0x45: return inst_lret(code);
+      
+  case 0x46: // ipset0
+  case 0x56: // ipset1
+  case 0x4E: // ipset2
+  case 0x5E: // ipset3
+    ip = ((ip << 2) & 0xFC);
+    ip |= (code >> 3) & 0x03;
+    break;
+    
+  case 0x47: // LD EIR,A
+    eir = regs.raf.A;
+    break;
+  case 0x49:
+    regs.aBC = regs.BC;
+    break;
+    
+  case 0x4A: // ADC HL,BC
+    adc_HL_wordreg(regs.BC);
+    break;
+
+  case 0x4B: // LD BC,(nnnn)
+    tw = fetch2();
+    regs.BC = get2(tw);
+    vc.rd+= 2;
+    break;
+    
+  case 0x4D: // RETI
+    ip=get1(regs.SP); regs.SP+=1;
+    pop2(PC);
+    vc.rd+= 2;
+    // TODO: chained-atomic, so set some marker
+    break;
+
+    // 0x4E: see 0x46
+  case 0x4F:
+    iir = regs.raf.A;
+    break;
+    
+  case 0x51:
+    regs.aDE = regs.DE;
+    break;
+
+  case 0x52: // SBC HL,DE
+    sbc_HL_wordreg(regs.DE);
+    break;
+  case 0x53: // LD (nnnn),DE
+    tw = fetch2();
+    store2(tw, regs.DE);
+    vc.rd+= 2;
+    break;
+    
+  case 0x54: // EX (SP),HL
+    tw = get2(regs.SP);
+    store2( regs.SP, regs.HL );
+    regs.HL = tw;
+    vc.rd+= 2;
+    vc.wr+= 2;
+    break;
+    
+    // 0x56: see 0x46
+  case 0x57:
+    regs.raf.A = eir;
+    break;
+    
+  case 0x59: // LD DE', BC
+    regs.aDE = regs.BC;
+    break;
+    
+  case 0x5A: // ADC HL,DE
+    adc_HL_wordreg(regs.DE);
+    break;
+    
+  case 0x5B: // LD DE,(nnnn)
+    tw = fetch2();
+    regs.DE = get2(tw);
+    vc.rd+= 2;
+    break;
+    
+  case 0x5D: // ipres
+    ip = ((ip >> 2) & 0x3F) | ((ip & 0x03) << 6);
+    break;
+    
+    // 0x5E: see 0x46
+
+  case 0x5F: // LD A,IIR
+    regs.raf.A = iir;
+    break;
+    
+  case 0x61: // LD HL',DE
+    regs.aHL = regs.DE;
+    break;
+    
+  case 0x62: // SBC HL,HL
+    sbc_HL_wordreg(regs.HL);
+    break;
+    
+  case 0x63: // LD (nnnn),HL opcode 22 does the same faster
+    tw = fetch2();
+    store2(tw, regs.HL);
+    vc.wr+= 2;
+    break;
+
+    case 0x64: // LDP (HL),HL
+      {
+	u16_t u16= regs.HL;
+	t_addr al= ((regs.raf.A & 0xf) << 16) | u16;
+	t_addr ah= ((regs.raf.A & 0xf) << 16) | ((u16+1)&0xffff);
+	rom->write(al, regs.hl.l);
+	rom->write(ah, regs.hl.h);
+	vc.wr+= 2;
+	break;
+      }
+      
+    case 0x65: // LDP (mn),HL
+      {
+	u16_t u16= fetch2();
+	t_addr al= ((regs.raf.A & 0xf) << 16) | u16;
+	t_addr ah= ((regs.raf.A & 0xf) << 16) | ((u16+1)&0xffff);
+	rom->write(al, regs.hl.l);
+	rom->write(ah, regs.hl.h);
+	vc.wr+= 2;
+	break;
+      }
+      
+  case 0x67: // LD XPC,A
+    mmu.xpc = regs.raf.A;
+    break;
+    
+  case 0x69: // LD HL',BC
+    regs.aHL = regs.BC;
+    break;
+    
+  case 0x6A: // ADC HL,HL
+    adc_HL_wordreg(regs.HL);
+    break;
+    
+  case 0x6B: // LD HL,(nnnn) opcode 2A does the same faster
+    tw = fetch2();
+    regs.HL = get2(tw);
+    vc.rd+= 2;
+    break;
+
+    case 0x6c: // LDP HL,(HL)
+      {
+	u16_t u16= regs.HL;
+	t_addr al= ((regs.raf.A & 0xf) << 16) | u16;
+	t_addr ah= ((regs.raf.A & 0xf) << 16) | ((u16+1)&0xffff);
+	regs.hl.l= rom->read(al);
+	regs.hl.h= rom->read(ah);
+	vc.rd+= 2;
+	break;
+      }
+      
+    case 0x6d: // LDP HL,(mn)
+      {
+	u16_t u16= fetch2();
+	t_addr al= ((regs.raf.A & 0xf) << 16) | u16;
+	t_addr ah= ((regs.raf.A & 0xf) << 16) | ((u16+1)&0xffff);
+	regs.hl.l= rom->read(al);
+	regs.hl.h= rom->read(ah);
+	vc.rd+= 2;
+	break;
+      }
+      
+  case 0x72: // SBC HL,SP
+    sbc_HL_wordreg(regs.SP);
+    break;
+  case 0x73: // LD (nnnn),SP
+    tw = fetch2();
+    store2(tw, regs.SP);
+    vc.wr+= 2;
+    break;
+    
+  case 0x76: // PUSH IP
+    push1(ip);
+    vc.wr+= 2;
+    break;
+    
+  case 0x77: // LD A,XPC
+    regs.raf.A = mmu.xpc;
+    break;
+    
+  case 0x7A: // ADC HL,SP
+    adc_HL_wordreg(regs.SP);
+    break;
+  case 0x7B: // LD SP,(nnnn)
+    tw = fetch2();
+    regs.SP = get2(tw);
+    vc.rd+= 2;
+    break;
+    
+  case 0x7D: // LD IY, HL
+    regs.IY = regs.HL;
+    break;
+
+  case 0x7E:
+    ip=get1(regs.SP); regs.SP+=1;
+    vc.rd++;
+    break;
+    
+  case 0xA0: // LDI
+    // BC - count, sourc=HL, dest=DE.  *DE++ = *HL++, --BC until zero
+    regs.raf.F &= ~(BIT_P | BIT_N | BIT_A);  /* clear these */
+    store1(regs.DE, get1(regs.HL));
+    ++regs.HL;
+    ++regs.DE;
+    --regs.BC;
+    vc.rd++;
+    vc.wr++;
+    if (regs.BC != 0) regs.raf.F |= BIT_P;
+    return(resGO);
+    
+  case 0xA8: // LDD
+    // BC - count, source=HL, dest=DE.  *DE-- = *HL--, --BC until zero
+    regs.raf.F &= ~(BIT_P | BIT_N | BIT_A);  /* clear these */
+    store1(regs.DE, get1(regs.HL));
+    --regs.HL;
+    --regs.DE;
+    --regs.BC;
+    vc.rd++;
+    vc.wr++;
+    if (regs.BC != 0) regs.raf.F |= BIT_P;
+    return(resGO);
+    
+  case 0xB0: // LDIR
+    // BC - count, sourc=HL, dest=DE.  *DE++ = *HL++, --BC until zero
+    regs.raf.F &= ~(BIT_P | BIT_N | BIT_A);  /* clear these */
+    
+    tw = get1(regs.HL);
+    store1(regs.DE, tw);
+    ++regs.HL;
+    ++regs.DE;
+    --regs.BC;
+    vc.rd++;
+    vc.wr++;
+    if (regs.BC != 0)
+      PC = ins_start;
+    return(resGO);
+    
+  case 0xB8: // LDDR
+    // BC - count, source=HL, dest=DE.  *DE-- = *HL--, --BC until zero
+    regs.raf.F &= ~(BIT_P | BIT_N | BIT_A);  /* clear these */
+    
+    tw = get1(regs.HL);
+    store1(regs.DE, tw);
+    --regs.HL;
+    --regs.DE;
+    --regs.BC;
+    vc.rd++;
+    vc.wr++;
+    
+    if (regs.BC != 0)
+      PC = ins_start;
+    return(resGO);
+    
+  case 0xEA: // CALL (HL)
+    push2(PC);
+    PC = regs.HL;
+    vc.wr+= 2;
+    return(resGO);
+    
+  
+  default:
+    return(resINV_INST);
+    }
+  
+  return(resGO);
+}
+
+int  cl_r3ka::inst_ed_(t_mem code)
+{
+  u8_t  tb;
+  
+  switch(code)
+    {
+    case  0x66:  // PUSH SU
+      push1(SU);
+      vc.wr++;
+      return(resGO);
+      
+    case  0x6E:  // POP  SU
+      SU = get1(regs.SP);
+      regs.SP++;
+      vc.rd++;
+      return(resGO);
+      
+    case  0x6F:  // SETUSR
+      SU = ((SU << 2) & 0xFC) | 0x01;
+      return(resGO);
+      
+    case  0x7D:  // SURES
+      SU = ((SU >> 2) & 0x3F) | ((SU << 6) & 0xC0);
+      return(resGO);
+      
+    case  0x7F:  // RDMODE
+      regs.raf.F &= ~(BIT_C);
+      if (SU & 0x01)
+        regs.raf.F |= BIT_C;
+      return(resGO);
+      
+    case  0x90:  // LDISR
+      // repeat (cnt=BC) { (DE) <= (HL++) }  /* normally has io prefix */
+      /* TODO: fix IOI/IOE behavior */
+      tb = get1(regs.HL);
+      store1( regs.DE, tb );
+      regs.HL++;
+      regs.BC--;
+      vc.rd++;
+      vc.wr++;
+      if (regs.BC)
+        PC = ins_start;
+      return(resGO);
+      
+    case  0x98:  // LDDSR
+      /* TODO: fix IOI/IOE behavior */
+      // repeat (cnt=BC) { (DE) <= (HL--) }  /* normally has io prefix */
+      tb = get1(regs.HL);
+      store1( regs.DE, tb );
+      regs.HL--;
+      regs.BC--;
+      vc.rd++;
+      vc.wr++;
+      if (regs.BC)
+        PC = ins_start;
+      return(resGO);
+
+    case  0xC0:  // UMA
+      // repeat while BC != 0:
+      // {CF:DE':(HL)} <= (IX) + [(IY)*DE + DE' + CF];
+      // BC--; IX++; IY++; HL++;
+      {
+        u32_t  tmp;
+        
+        /* scale a sum for operand pointed to by IY */
+        tmp  = get1(regs.IY);
+        tmp *= regs.DE;
+        tmp += regs.aDE;
+        tmp += (regs.raf.F & BIT_C) ? 1 : 0;
+        
+        /* simple add for operand pointed to by IX */
+        tmp += get1(regs.IX);
+        
+        /* store the result(s) */
+        store1( regs.HL, tmp & 0xFF );
+        regs.aDE = ((tmp >> 8) & 0xFFFF);
+        regs.raf.F &= ~(BIT_C);
+        regs.raf.F |= (tmp >> 24) ? BIT_C : 0;
+	vc.rd+= 2;
+	vc.wr++;
+      }
+      
+      regs.IX++;
+      regs.IY++;
+      regs.HL++;
+      regs.BC--;
+      if (regs.BC)
+        PC = ins_start;
+      return(resGO);
+      
+    case  0xC8:  // UMS
+      // repeat while BC != 0:
+      // {CF:DE':(HL)} <= (IX) - [(IY)*DE + DE' + CF];
+      // BC--; IX++; IY++; HL++;
+      {
+        u32_t  tmp;
+        
+        /* scale a sum for operand pointed to by IY */
+        tmp  = get1(regs.IY);
+        tmp *= regs.DE;
+        tmp += regs.aDE;
+        tmp += (regs.raf.F & BIT_C) ? 1 : 0;
+        
+        /* subtract above from operand pointed to by IX */
+        tmp = get1(regs.IX) - tmp;
+        
+        /* store the result(s) */
+        store1( regs.HL, tmp & 0xFF );
+        regs.aDE = ((tmp >> 8) & 0xFFFF);
+        regs.raf.F &= ~(BIT_C);
+        regs.raf.F |= (tmp >> 24) ? BIT_C : 0;
+	vc.rd+= 2;
+	vc.wr++;
+      }
+      
+      regs.IX++;
+      regs.IY++;
+      regs.HL++;
+      regs.BC--;
+      if (regs.BC)
+        PC = ins_start;
+      return(resGO);
+
+    case  0xD0:  // LSIDR
+      /* TODO: fix IOI/IOE behavior */
+      // repeat (cnt=BC) { (DE++) <= (HL) }  /* normally has io prefix */
+      tb = get1( regs.HL );
+      store1( regs.DE, tb );
+      regs.DE++;
+      regs.BC--;
+      vc.rd++;
+      vc.wr++;
+      if (regs.BC)
+        PC = ins_start;
+      return(resGO);
+      
+    case 0xD8:   // LSDDR
+      /* TODO: fix IOI/IOE behavior */
+      // repeat (cnt=BC) { (DE--) <= (HL) }  /* normally has io prefix */
+      tb = get1( regs.HL );
+      store1( regs.DE, tb );
+      regs.DE--;
+      regs.BC--;
+      vc.rd++;
+      vc.wr++;
+      if (regs.BC)
+        PC = ins_start;
+      return(resGO);
+      
+    case  0xF0:  // LSIR
+      /* TODO: fix IOI/IOE behavior */
+      //  repeat (cnt=BC) { (DE++) <= (HL++) }
+      tb = get1( regs.HL );
+      store1( regs.DE, tb );
+      regs.DE++;
+      regs.HL++;
+      regs.BC--;
+      vc.rd++;
+      vc.wr++;
+      if (regs.BC)
+        PC = ins_start;
+      return(resGO);
+      
+    case  0xF8:  // LSDR
+      /* TODO: fix IOI/IOE behavior */
+      //  repeat (cnt=BC) { (DE--) <= (HL--) }
+      tb = get1( regs.HL );
+      store1( regs.DE, tb );
+      regs.DE--;
+      regs.HL--;
+      regs.BC--;
+      vc.rd++;
+      vc.wr++;
+      if (regs.BC)
+        PC = ins_start;
+      return(resGO);
+      
+    default:
+      return cl_r2k::inst_ed_(code);
+    }
+}
+
+//IDET        system mode violation interrupt if in user mode
+
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/z80.src/inst_fdcb.cc sdcc-4.2.0+dfsg/sim/ucsim/z80.src/inst_fdcb.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/z80.src/inst_fdcb.cc	2004-11-06 19:56:53.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/z80.src/inst_fdcb.cc	2020-03-27 20:18:53.000000000 +0000
@@ -26,11 +26,11 @@
 02111-1307, USA. */
 /*@1@*/
 
-#include "ddconfig.h"
+//#include "ddconfig.h"
 
 // local
 #include "z80cl.h"
-#include "regsz80.h"
+//#include "regsz80.h"
 #include "z80mac.h"
 
 #define regs_IX_OR_IY regs.IY
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/z80.src/inst_fd.cc sdcc-4.2.0+dfsg/sim/ucsim/z80.src/inst_fd.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/z80.src/inst_fd.cc	2011-10-09 18:21:10.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/z80.src/inst_fd.cc	2020-03-27 20:18:53.000000000 +0000
@@ -28,11 +28,11 @@
 02111-1307, USA. */
 /*@1@*/
 
-#include "ddconfig.h"
+//#include "ddconfig.h"
 
 // local
 #include "z80cl.h"
-#include "regsz80.h"
+//#include "regsz80.h"
 #include "z80mac.h"
 
 #define regs_iX_h regs.iy.h
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/z80.src/inst_gb80.cc sdcc-4.2.0+dfsg/sim/ucsim/z80.src/inst_gb80.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/z80.src/inst_gb80.cc	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/z80.src/inst_gb80.cc	2021-03-20 16:44:50.000000000 +0000
@@ -0,0 +1,190 @@
+/*
+ * Simulated instructions specific to the GB80, the Z-80 derivative used
+ * in the gameboy.
+ *
+ * 2011-12-21  created by Leland Morrison
+ *
+ *
+
+This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+//#include "ddconfig.h"
+
+#include "gb80cl.h"
+
+static u8_t  swap_nibbles(u8_t  val) {
+  return ((val >> 4) & 0x0f) | ((val << 4) & 0xf0);
+}
+
+int cl_gb80::inst_cb(void) {
+  u8_t  result;
+  t_mem       code;
+  
+  if ( (peek1( ) & 0xf8) != 0x30 )
+    return cl_z80::inst_cb( );
+  
+  code = fetch1();
+  
+  /* perform SWAP instead of slia */
+  switch(code) {
+  case 0x30: result = regs.bc.h = swap_nibbles(regs.bc.h); break; /* b */
+  case 0x31: result = regs.bc.l = swap_nibbles(regs.bc.l); break; /* c */
+  case 0x32: result = regs.de.h = swap_nibbles(regs.de.h); break; /* d */
+  case 0x33: result = regs.de.l = swap_nibbles(regs.de.l); break; /* e */
+  case 0x34: result = regs.hl.h = swap_nibbles(regs.hl.h); break; /* h */
+  case 0x35: result = regs.hl.l = swap_nibbles(regs.hl.l); break; /* l */
+  case 0x36: /* SWAP (HL) */
+    {
+      result = swap_nibbles(get1(regs.HL));
+      store1(regs.HL, result);
+      vc.rd++;
+      vc.wr++;
+    }
+    break;
+    
+  case 0x37: result = regs.raf.A = swap_nibbles(regs.raf.A); break; /* swap a */
+  default: return resINV_INST;
+  }
+  regs.raf.F = (result)?0:BIT_Z;  // all except zero are simply cleared
+  return(resGO);
+}
+
+int cl_gb80::inst_st_sp_abs(t_mem code) {
+  if (code == 0x08) {
+    u16_t addr = fetch2( );
+    store2( addr, regs.SP );
+    vc.wr+= 2;
+    return(resGO);
+  }
+  
+  return resINV_INST;
+}
+
+int cl_gb80::inst_stop0    (t_mem code) {
+  // TODO: change to wait for a signal for simulated hardware
+  return resHALT;
+}
+
+int cl_gb80::inst_ldi   (t_mem code) {
+  if (code == 0x22) {
+    store1( regs.HL, regs.raf.A );
+    regs.HL ++;
+    vc.wr++;
+    return resGO;
+  } else if (code == 0x2A) {
+    regs.raf.A = get1( regs.HL );
+    regs.HL ++;
+    vc.rd++;
+    return resGO;
+  }
+  
+  return resINV_INST;
+}
+
+int cl_gb80::inst_ldd   (t_mem code) {
+  if (code == 0x32) {
+    store1( regs.HL, regs.raf.A );
+    regs.HL --;
+    vc.wr++;
+    return resGO;
+  } else if (code == 0x3A) {
+    regs.raf.A = get1( regs.HL );
+    regs.HL --;
+    vc.rd++;
+    return resGO;
+  }
+  
+  return resINV_INST;
+}
+
+int cl_gb80::inst_ldh   (t_mem code) {
+  u16_t addr = 0xFF00 + fetch1( );
+  
+  if (code == 0xE0) {
+    store1( addr, regs.raf.A );
+    vc.wr++;
+    return resGO;
+  } else if (code == 0xF0) {
+    regs.raf.A = get1( addr );
+    vc.rd++;
+    return resGO;
+  }
+  
+  return resINV_INST;
+}
+  
+int cl_gb80::inst_reti  (t_mem code) {
+  /* enable interrupts */
+  cl_z80::inst_ei(0xFB);
+  
+  /* pop2(PC); */
+  PC=get2(regs.SP);
+  regs.SP+=2;
+  vc.rd+= 2;
+  
+  return resGO;
+}
+
+int cl_gb80::inst_add_sp_d(t_mem code) {
+  u16_t  d = fetch( );
+  /* sign-extend d from 8-bits to 16-bits */
+  d |= (d>>7)*0xFF00;
+  
+  regs.raf.F &= ~(BIT_ALL);  /* clear these */
+  if ((regs.SP & 0x0FFF) + (d & 0x0FFF) > 0x0FFF)
+    regs.raf.F |= BIT_A;
+  if (regs.SP + (int)(d) > 0xffff)
+    regs.raf.F |= BIT_C;
+  
+  regs.SP = (regs.SP + d) & 0xffff;
+
+  return(resGO);
+}
+
+int cl_gb80::inst_ld16  (t_mem code) {
+  u16_t addr = fetch2( );
+  if (code == 0xEA) {
+    store1( addr, regs.raf.A );
+    vc.wr++;
+    return resGO;
+  } else if (code == 0xFA) {
+    regs.raf.A = get1( addr );
+    vc.rd++;
+    return resGO;
+  }
+  
+  return resINV_INST;
+}
+
+int cl_gb80::inst_ldhl_sp (t_mem code) {
+  u16_t  d = fetch( );
+  /* sign-extend d from 8-bits to 16-bits */
+  d |= (d>>7)*0xFF00;
+
+  regs.raf.F &= ~(BIT_ALL);  /* clear these */
+  if ((regs.SP & 0x0FFF) + (d & 0x0FFF) > 0x0FFF)
+    regs.raf.F |= BIT_A;
+  if (regs.SP + (int)(d) > 0xffff)
+    regs.raf.F |= BIT_C;
+  
+  regs.HL = (regs.SP + d) & 0xffff;
+  return resGO;
+}
+
+/* End of z80.src/inst_gb80.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/z80.src/inst_lr35902.cc sdcc-4.2.0+dfsg/sim/ucsim/z80.src/inst_lr35902.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/z80.src/inst_lr35902.cc	2017-03-02 10:01:56.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/z80.src/inst_lr35902.cc	1970-01-01 00:00:00.000000000 +0000
@@ -1,188 +0,0 @@
-/*
- * Simulated instructions specific to the LR35902, the Z-80 derivative used
- * in the gameboy.
- *
- * 2011-12-21  created by Leland Morrison
- *
- *
-
-This file is part of microcontroller simulator: ucsim.
-
-UCSIM is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2 of the License, or
-(at your option) any later version.
-
-UCSIM is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with UCSIM; see the file COPYING.  If not, write to the Free
-Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-02111-1307, USA. */
-/*@1@*/
-#include "ddconfig.h"
-
-#include "lr35902cl.h"
-
-static u8_t  swap_nibbles(u8_t  val) {
-  return ((val >> 4) & 0x0f) | ((val << 4) & 0xf0);
-}
-
-int cl_lr35902::inst_cb(void) {
-  u8_t  result;
-  t_mem       code;
-  
-  if ( (peek1( ) & 0xf8) != 0x30 )
-    return cl_z80::inst_cb( );
-  
-  code = fetch1();
-  
-  /* perform SWAP instead of slia */
-  switch(code) {
-  case 0x30: result = regs.bc.h = swap_nibbles(regs.bc.h); break; /* b */
-  case 0x31: result = regs.bc.l = swap_nibbles(regs.bc.l); break; /* c */
-  case 0x32: result = regs.de.h = swap_nibbles(regs.de.h); break; /* d */
-  case 0x33: result = regs.de.l = swap_nibbles(regs.de.l); break; /* e */
-  case 0x34: result = regs.hl.l = swap_nibbles(regs.hl.h); break; /* h */
-  case 0x35: result = regs.hl.h = swap_nibbles(regs.hl.l); break; /* l */
-  case 0x36: /* SWAP (HL) */
-    {
-      result = swap_nibbles(get1(regs.HL));
-      store1(regs.HL, result);
-      vc.rd++;
-      vc.wr++;
-    }
-    break;
-    
-  case 0x37: result = regs.raf.A = swap_nibbles(regs.raf.A); break; /* swap a */
-  default: return resINV_INST;
-  }
-  regs.raf.F = (result)?0:0x80;  // all except zero are simply cleared
-  return(resGO);
-}
-
-int cl_lr35902::inst_st_sp_abs(t_mem code) {
-  if (code == 0x08) {
-    u16_t addr = fetch2( );
-    store2( addr, regs.SP );
-    vc.wr+= 2;
-    return(resGO);
-  }
-  
-  return resINV_INST;
-}
-
-int cl_lr35902::inst_stop0    (t_mem code) {
-  // TODO: change to wait for a signal for simulated hardware
-  return resHALT;
-}
-
-int cl_lr35902::inst_ldi   (t_mem code) {
-  if (code == 0x22) {
-    store1( regs.HL, regs.raf.A );
-    regs.HL ++;
-    vc.wr++;
-    return resGO;
-  } else if (code == 0x2A) {
-    regs.raf.A = get1( regs.HL );
-    regs.HL ++;
-    vc.rd++;
-    return resGO;
-  }
-  
-  return resINV_INST;
-}
-
-int cl_lr35902::inst_ldd   (t_mem code) {
-  if (code == 0x32) {
-    store1( regs.HL, regs.raf.A );
-    regs.HL --;
-    vc.wr++;
-    return resGO;
-  } else if (code == 0x3A) {
-    regs.raf.A = get1( regs.HL );
-    regs.HL --;
-    vc.rd++;
-    return resGO;
-  }
-  
-  return resINV_INST;
-}
-
-int cl_lr35902::inst_ldh   (t_mem code) {
-  u16_t addr = 0xFF00 + fetch1( );
-  
-  if (code == 0xE0) {
-    store1( addr, regs.raf.A );
-    vc.wr++;
-    return resGO;
-  } else if (code == 0xF0) {
-    regs.raf.A = get1( addr );
-    vc.rd++;
-    return resGO;
-  }
-  
-  return resINV_INST;
-}
-  
-int cl_lr35902::inst_reti  (t_mem code) {
-  /* enable interrupts */
-  cl_z80::inst_ei(0xFB);
-  
-  /* pop2(PC); */
-  PC=get2(regs.SP);
-  regs.SP+=2;
-  vc.rd+= 2;
-  
-  return resGO;
-}
-
-int cl_lr35902::inst_add_sp_d(t_mem code) {
-  u16_t  d = fetch( );
-  /* sign-extend d from 8-bits to 16-bits */
-  d |= (d>>7)*0xFF00;
-  
-  regs.raf.F &= ~(BIT_ALL);  /* clear these */
-  if ((regs.SP & 0x0FFF) + (d & 0x0FFF) > 0x0FFF)
-    regs.raf.F |= BIT_A;
-  if (regs.SP + (int)(d) > 0xffff)
-    regs.raf.F |= BIT_C;
-  
-  regs.SP = (regs.SP + d) & 0xffff;
-
-  return(resGO);
-}
-
-int cl_lr35902::inst_ld16  (t_mem code) {
-  u16_t addr = fetch2( );
-  if (code == 0xEA) {
-    store1( addr, regs.raf.A );
-    vc.wr++;
-    return resGO;
-  } else if (code == 0xFA) {
-    regs.raf.A = get1( addr );
-    vc.rd++;
-    return resGO;
-  }
-  
-  return resINV_INST;
-}
-
-int cl_lr35902::inst_ldhl_sp (t_mem code) {
-  u16_t  d = fetch( );
-  /* sign-extend d from 8-bits to 16-bits */
-  d |= (d>>7)*0xFF00;
-
-  regs.raf.F &= ~(BIT_ALL);  /* clear these */
-  if ((regs.SP & 0x0FFF) + (d & 0x0FFF) > 0x0FFF)
-    regs.raf.F |= BIT_A;
-  if (regs.SP + (int)(d) > 0xffff)
-    regs.raf.F |= BIT_C;
-  
-  regs.HL = (regs.SP + d) & 0xffff;
-  return resGO;
-}
-
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/z80.src/inst_r2k.cc sdcc-4.2.0+dfsg/sim/ucsim/z80.src/inst_r2k.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/z80.src/inst_r2k.cc	2017-03-02 10:01:56.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/z80.src/inst_r2k.cc	2021-07-16 14:31:13.000000000 +0000
@@ -1,606 +1,671 @@
-/* This file is part of microcontroller simulator: ucsim.
-
-UCSIM is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2 of the License, or
-(at your option) any later version.
-
-UCSIM is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with UCSIM; see the file COPYING.  If not, write to the Free
-Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-02111-1307, USA. */
-/*@1@*/
-
-#include "ddconfig.h"
-
-// local
-#include "r2kcl.h"
-#include "z80mac.h"
-
-
-unsigned   word_parity( u16_t  x ) {
-  // bitcount(x) performed by shift-and-add
-  u16_t  tmp = (x & 0x5555) + ((x & 0xAAAA) >> 1);
-  tmp = (tmp & 0x3333) + ((tmp & 0xCCCC) >> 2);
-  tmp = (tmp & 0x0F0F) + ((tmp & 0xF0F0) >> 4);
-  tmp = (tmp & 0x000F) + ((tmp & 0x0F00) >> 8);
-  
-  // parity determined by count being odd or even
-  return  0x01 ^ (tmp & 1);
-}
-
-/******** rabbit 2000 memory access helper functions *****************/
-u32_t  rabbit_mmu::logical_addr_to_phys( u16_t logical_addr ) {
-  u32_t  phys_addr = logical_addr;
-  unsigned     segnib = logical_addr >> 12;
-  
-  if (segnib >= 0xE000)
-  {
-    phys_addr += ((u32_t)xpc) << 12;
-  }
-  else if (segnib >= ((segsize >> 4) & 0x0F))
-  {
-    phys_addr += ((u32_t)stackseg) << 12;    
-  }
-  else if (segnib >= (segsize & 0x0F))
-  {
-    phys_addr += ((u32_t)dataseg) << 12;    
-  }
-  
-  return phys_addr;
-}
-
-void cl_r2k::store1( u16_t addr, t_mem val ) {
-  u32_t  phys_addr;
-  
-  if (mmu.io_flag == IOI) {
-    if ((mmu.mmidr ^ 0x80) & 0x80)
-      /* bit 7 = 0 --> use only 8-bits for internal I/O addresses */
-      addr = addr & 0x0ff;
-    
-    if (addr == MMIDR) {
-      mmu.mmidr = val;
-      return;
-    }
-    
-    if (addr == SADR) {
-      /* serial A (console when using the rabbit programming cable) */
-      putchar(val);
-      fflush(stdout);
-    }
-    return;
-  }
-  if (mmu.io_flag == IOE) {
-    /* I/O operation for external device (such as an ethernet controller) */
-    return;
-  }
-  
-  phys_addr = mmu.logical_addr_to_phys( addr );
-  ram->write(phys_addr, val);
-}
-
-void cl_r2k::store2( u16_t addr, u16_t val ) {
-  u32_t  phys_addr;
-  
-  if (mmu.io_flag == IOI) {
-    /* I/O operation for on-chip device (serial ports, timers, etc) */
-    return;
-  }
-  
-  if (mmu.io_flag == IOE) {
-    /* I/O operation for external device (such as an ethernet controller) */
-    return;
-  }
-  
-  phys_addr = mmu.logical_addr_to_phys( addr );
-  
-  ram->write(phys_addr,   val & 0xff);
-  ram->write(phys_addr+1, (val >> 8) & 0xff);
-}
-
-u8_t  cl_r2k::get1( u16_t addr ) {
-  u32_t  phys_addr = mmu.logical_addr_to_phys( addr );
-  
-  if (mmu.io_flag == IOI) {
-    /* stub for on-chip device I/O */
-    return 0;
-  }
-  if (mmu.io_flag == IOE) {
-    /* stub for external device I/O */
-    return 0;
-  }
-  
-  return ram->read(phys_addr);
-}
-
-u16_t  cl_r2k::get2( u16_t addr ) {
-  u32_t phys_addr = mmu.logical_addr_to_phys( addr );
-  u16_t  l, h;
-  
-  if (mmu.io_flag == IOI) {
-    /* stub for on-chip device I/O */
-    return 0;
-  }
-  if (mmu.io_flag == IOE) {
-    /* stub for external device I/O */
-    return 0;
-  }
-  
-  l = ram->read(phys_addr  );
-  h = ram->read(phys_addr+1);
-  
-  return (h << 8) | l;
-}
-
-t_mem       cl_r2k::fetch1( void ) {
-  return fetch( );
-}
-
-u16_t  cl_r2k::fetch2( void ) {
-  u16_t  c1, c2;
-  
-  c1 = fetch( );
-  c2 = fetch( );
-  return (c2 << 8) | c1;
-}
-
-t_mem cl_r2k::fetch(void) {
-  /*
-   * Fetch without checking for breakpoint hit
-   *
-   * Used by bool cl_uc::fetch(t_mem *code) in sim.src/uc.cc
-   * which does check for a breakpoint hit
-   */
-  
-  u32_t phys_addr = mmu.logical_addr_to_phys( PC );
-  ulong code;
-  
-  if (!rom)
-    return(0);
-  
-  code= rom->read(phys_addr);
-  PC = (PC + 1) & 0xffffUL;
-  vc.fetch++;
-  return(code);
-}
-
-/******** start rabbit 2000 specific codes *****************/
-int cl_r2k::inst_add_sp_d(t_mem code) {
-  u16_t  d = fetch( );
-  /* sign-extend d from 8-bits to 16-bits */
-  d |= (d>>7)*0xFF00;
-  regs.SP = (regs.SP + d) & 0xffff;
-  return(resGO);
-}
-
-int cl_r2k::inst_altd(t_mem code) {
-  // stub
-  return(resGO);
-}
-
-int
-cl_r2k::inst_r2k_ld(t_mem code)
-{
-  /* 0xC4  ld hl,(sp+n)
-   * 0xD4  ld (sp+n),hl
-   * 0xE4  ld hl,(ix+d)
-   *   DD E4 = ld hl,(hl+d)   [note: (hl+d) breaks the normal prefix pattern]
-   *   FD E4 = ld hl,(iy+d)
-   * 0xF4  ld (ix+d),hl
-   *   DD F4 = ld (hl+d),hl
-   *   FD F4 = ld (iy+d),hl
-   */
-  switch(code) {
-  case 0xC4:  regs.HL = get2( add_u16_disp(regs.SP, fetch()) ); vc.rd+= 2; break;
-  case 0xD4:  store2( add_u16_disp(regs.SP, fetch()), regs.HL ); vc.wr+= 2; break;
-  case 0xE4:  regs.HL = get2( add_u16_disp(regs.IX, fetch()) ); vc.rd+= 2; break;
-  case 0xF4:  store2( add_u16_disp(regs.IX, fetch()), regs.HL ); vc.wr+= 2; break;
-  default:
-    return(resINV_INST);
-  }
-  
-  return(resGO);
-}
-
-int cl_r2k::inst_r2k_ex (t_mem code) {
-  u16_t tempw;
-  
-  switch(code) {
-  case 0xE3:
-    // EX DE', HL  on rabbit processors
-    tempw = regs.aDE;
-    regs.aDE = regs.HL;
-    regs.HL = tempw;
-    return(resGO);
-    
-  default:
-    return(resINV_INST);
-  }
-}
-
-int cl_r2k::inst_ljp(t_mem code) {
-  u16_t  mn;
-  
-  mn = fetch2();  /* don't clobber PC before the fetch for xmem page */
-  mmu.xpc = fetch1();
-  PC = mn;
-  
-  return(resGO);
-}
-
-int cl_r2k::inst_lcall(t_mem code) {
-  u16_t  mn;
-  
-  push1(mmu.xpc);
-  push2(PC+2);
-  vc.wr+= 2;
-  
-  mn = fetch2();  /* don't clobber PC before the fetch for xmem page */
-  mmu.xpc = fetch1();
-  PC = mn;
-  
-  return(resGO);
-}
-
-int cl_r2k::inst_bool(t_mem code) {
-  regs.raf.F &= ~BIT_ALL;
-  if (regs.HL)
-    regs.HL = 1;
-  else
-    regs.raf.F |= BIT_Z;
-  return(resGO);
-}
-
-int cl_r2k::inst_r2k_and(t_mem code) {  // AND HL,DE
-  regs.HL &= regs.DE;
-  
-  regs.raf.F &= ~BIT_ALL;
-  if (regs.DE & 0x8000)
-    regs.raf.F |= BIT_S;
-  if (regs.DE == 0)
-    regs.raf.F |= BIT_Z;
-  if (word_parity(regs.DE))
-    regs.raf.F |= BIT_P;
-  return(resGO);
-}
-
-int cl_r2k::inst_r2k_or (t_mem code) {  // OR  HL,DE
-  regs.HL |= regs.DE;
-  
-  regs.raf.F &= ~BIT_ALL;
-  if (regs.DE & 0x8000)
-    regs.raf.F |= BIT_S;
-  if (regs.DE == 0)
-    regs.raf.F |= BIT_Z;
-  if (word_parity(regs.DE))
-    regs.raf.F |= BIT_P;
-  return(resGO);
-}
-
-int cl_r2k::inst_mul(t_mem code) {
-  long m;
-  long m1 = (long)(regs.BC & 0x7fff);
-  long m2 = (long)(regs.DE & 0x7fff);
-  if (regs.BC & 0x8000)
-    m1 -= (1 << 15);
-  if (regs.DE & 0x8000)
-    m2 -= (1 << 15);
-  m = m1 * m2;
-  regs.BC = ((unsigned long)(m) & 0xffff);
-  regs.HL = ((unsigned long)(m) >> 16) & 0xffff;
-  return(resGO);
-}
-
-int cl_r2k::inst_rl_de(t_mem code) {
-  unsigned int oldcarry = (regs.raf.F & BIT_C);
-  
-  regs.raf.F &= ~BIT_ALL;
-  regs.raf.F |= (((regs.DE >> 15) & 1U) << BITPOS_C);
-  regs.DE = (regs.DE << 1) | (oldcarry >> BITPOS_C);
-  
-  if (regs.DE & 0x8000)
-    regs.raf.F |= BIT_S;
-  if (regs.DE == 0)
-    regs.raf.F |= BIT_Z;
-  if (word_parity(regs.DE))
-    regs.raf.F |= BIT_P;
-  return(resGO);
-}
-
-int cl_r2k::inst_rr_de(t_mem code) {
-  unsigned int oldcarry = (regs.raf.F & BIT_C);
-
-  regs.raf.F &= ~BIT_ALL;
-  regs.raf.F |= ((regs.DE & 1) << BITPOS_C);
-  regs.DE = (regs.DE >> 1) | (oldcarry << (15 - BITPOS_C));
-  
-  if (regs.DE & 0x8000)
-    regs.raf.F |= BIT_S;
-  if (regs.DE == 0)
-    regs.raf.F |= BIT_Z;
-  if (word_parity(regs.DE))
-    regs.raf.F |= BIT_P;
-  return(resGO);
-}
-
-int cl_r2k::inst_rr_hl(t_mem code)    // RR HL
-{
-  unsigned int oldcarry = (regs.raf.F & BIT_C);
-  
-  regs.raf.F &= ~BIT_ALL;
-  regs.raf.F |= ((regs.HL & 1) << BITPOS_C);
-  regs.HL = (regs.HL >> 1) | (oldcarry << (15 - BITPOS_C));
-  
-  if (regs.HL & 0x8000)
-    regs.raf.F |= BIT_S;
-  if (regs.HL == 0)
-    regs.raf.F |= BIT_Z;
-  if (word_parity(regs.HL))
-    regs.raf.F |= BIT_P;
-  return(resGO);
-}
-
-
-int
-cl_r2k::inst_rst(t_mem code)
-{
-  switch(code) {
-    case 0xC7: // RST 0
-      push2(PC+2);
-      PC = 0x0;
-      vc.wr+= 2;
-    break;
-    case 0xCF: // RST 8
-      return(resINV_INST);
-    
-    case 0xD7: // RST 10H
-      push2(PC+2);
-      PC = 0x10;
-      vc.wr+= 2;
-    break;
-    case 0xDF: // RST 18H
-      push2(PC+2);
-      PC = 0x18;
-      vc.wr+= 2;
-    break;
-    case 0xE7: // RST 20H
-      push2(PC+2);
-      PC = 0x20;
-      vc.wr+= 2;
-    break;
-    case 0xEF: // RST 28H
-      //PC = 0x28;
-      switch (regs.raf.A) {
-        case 0:
-          return(resBREAKPOINT);
-//          ::exit(0);
-        break;
-
-        case 1:
-          //printf("PUTCHAR-----> %xH\n", regs.hl.l);
-          putchar(regs.hl.l);
-          fflush(stdout);
-        break;
-      }
-    break;
-    case 0xF7: // RST 30H
-      return(resINV_INST);  // opcode is used for MUL on rabbit 2000+
-    break;
-    case 0xFF: // RST 38H
-      push2(PC+2);
-      PC = 0x38;
-      vc.wr+= 2;
-    break;
-    default:
-      return(resINV_INST);
-    break;
-  }
-  return(resGO);
-}
-
-int cl_r2k::inst_xd(t_mem prefix)
-{
-  u16_t  *regs_IX_OR_IY = (prefix==0xdd)?(®s.IX):(®s.IY);
-  t_mem code;
-  
-  if (fetch(&code))
-    return(resBREAKPOINT);
-
-  switch (code) {
-    
-    // 0x06 LD A,(IX+A) is r4k+ instruction
-  case 0x21: // LD IX,nnnn
-  case 0x22: // LD (nnnn),IX
-    
-  case 0x2A: // LD IX,(nnnn)
-  case 0x2E: // LD LX,nn
-  case 0x36: // LD (IX+dd),nn
-  case 0x46: // LD B,(IX+dd)
-  case 0x4E: // LD C,(IX+dd)
-  case 0x56: // LD D,(IX+dd)
-  case 0x5E: // LD E,(IX+dd)
-  case 0x66: // LD H,(IX+dd)
-  case 0x6E: // LD L,(IX+dd)
-    
-  case 0x70: // LD (IX+dd),B
-  case 0x71: // LD (IX+dd),C
-  case 0x72: // LD (IX+dd),D
-  case 0x73: // LD (IX+dd),E
-  case 0x74: // LD (IX+dd),H
-  case 0x75: // LD (IX+dd),L
-  case 0x77: // LD (IX+dd),A
-  case 0x7E: // LD A,(IX+dd)
-  case 0xF9: // LD SP,IX
-    if (prefix == 0xdd)
-      return(inst_dd_ld(code));
-    else
-      return(inst_fd_ld(code));
-    
-  case 0x7C: // LD HL,IX
-    regs.HL = *regs_IX_OR_IY;  // LD HL, IX|IY for rabbit processors
-    return(resGO);
-  case 0x7D: // LD IX,HL
-    *regs_IX_OR_IY = regs.HL;   // LD IX|IY,HL for rabbit processors
-    return(resGO);
-    
-  case 0x23: // INC IX
-  case 0x34: // INC (IX+dd)
-    if (prefix == 0xdd)
-      return(inst_dd_inc(code));
-    else
-      return(inst_fd_inc(code));
-    
-  case 0x09: // ADD IX,BC
-  case 0x19: // ADD IX,DE
-  case 0x29: // ADD IX,IX
-  case 0x39: // ADD IX,SP
-  case 0x86: // ADD A,(IX)
-    if (prefix == 0xdd)
-      return(inst_dd_add(code));
-    else
-      return(inst_fd_add(code));
-    
-  case 0x2B: // DEC IX
-  case 0x35: // DEC (IX+dd)
-    if (prefix == 0xdd)
-      return(inst_dd_dec(code));
-    else
-      return(inst_fd_dec(code));
-    
-    // 0x4C  TEST IX is r4k+
-
-  case 0x8E: // ADC A,(IX)
-  case 0x96: // SUB (IX+dd)
-  case 0x9E: // SBC A,(IX+dd)
-  case 0xA6: // AND (IX+dd)
-  case 0xAE: // XOR (IX+dd)
-  case 0xB6: // OR (IX+dd)
-  case 0xBE: // CP (IX+dd)
-    if (prefix == 0xdd)
-      return(inst_dd_misc(code));
-    else
-      return(inst_fd_misc(code));
-    
-  case 0xC4: // LD IX,(SP+n)
-    *regs_IX_OR_IY = get2( add_u16_disp(regs.SP, fetch()) );
-    vc.rd+= 2;
-    return(resGO);
-    
-  case 0xCB: // escape, IX prefix to CB commands
-    // fixme: limit the opcodes passed through to those officially
-    // documented as present on the rabbit processors
-    if (prefix == 0xdd)
-      return(inst_ddcb()); /* see inst_ddcb.cc */
-    else
-      return(inst_fdcb()); /* see inst_fdcb.cc */
-    
-  case 0xCC: // BOOL IX|IY
-    if (*regs_IX_OR_IY)
-      *regs_IX_OR_IY = 1;
-    
-    // update flags
-    regs.raf.F &= ~BIT_ALL;
-    // bit 15 will never be set, so S<=0
-    if (*regs_IX_OR_IY == 0)
-      regs.raf.F |= BIT_Z;
-    // L/V and C are always cleared
-    return(resGO);
-    
-  case 0xD4: // LD (SP+n),IX|IY
-    store2( add_u16_disp(regs.SP, fetch()), *regs_IX_OR_IY );
-    vc.wr+= 2;
-    return(resGO);
-    
-  case 0xE1: // POP IX
-    *regs_IX_OR_IY = get2(regs.SP);
-    regs.SP+=2;
-    vc.rd+= 2;
-    return(resGO);
-    
-  case 0xE3: // EX (SP),IX
-  {
-    u16_t tempw;
-    
-    tempw = *regs_IX_OR_IY;
-    *regs_IX_OR_IY = get2(regs.SP);
-    store2(regs.SP, tempw);
-    vc.rd+= 2;
-    vc.wr+= 2;
-  }
-  return(resGO);
-  
-  case 0xE4:
-    if (prefix == 0xDD)
-      regs.HL = get2( add_u16_disp(regs.HL, fetch()) );
-    else
-      regs.HL = get2( add_u16_disp(regs.IY, fetch()) );
-    vc.rd+= 2;
-    return(resGO);
-    
-  case 0xE5: // PUSH IX
-    push2(*regs_IX_OR_IY);
-    vc.wr+= 2;
-    return(resGO);
-    
-  case 0xE9: // JP (IX)
-    PC = *regs_IX_OR_IY;
-    return(resGO);
-    
-  case 0xEA:
-    push2(PC);
-    PC = *regs_IX_OR_IY;
-    vc.wr+= 2;
-    return(resGO);
-    
-  case 0xDC: // AND IX|IY,DE  for rabbit processors
-  case 0xEC: // OR  IX|IY,DE  for rabbit processors
-    if (code == 0xDC)
-      *regs_IX_OR_IY &= regs.DE;
-    else
-      *regs_IX_OR_IY |= regs.DE;
-    
-    // update flags
-    regs.raf.F &= ~BIT_ALL;
-    if (*regs_IX_OR_IY & 0x8000)
-      regs.raf.F |= BIT_S;
-    if (regs_IX_OR_IY == 0)
-      regs.raf.F |= BIT_Z;
-    if (word_parity(*regs_IX_OR_IY))
-      regs.raf.F |= BIT_P;
-    return(resGO);
-    
-  case 0xF4: // LD (HL|IY+d),HL
-    if (prefix == 0xDD)
-      store2( add_u16_disp(regs.HL, fetch()), regs.HL );
-    else
-      store2( add_u16_disp(regs.IY, fetch()), regs.HL );
-    vc.wr+= 2;
-    return(resGO);
-    
-  case 0xFC: // RR IX|IY
-  {
-    u16_t  tmp = (regs.raf.F & BIT_C) << (15 - BITPOS_C);
-    tmp |= (*regs_IX_OR_IY >> 1);
-    
-    regs.raf.F = (regs.raf.F & ~BIT_C) | ((*regs_IX_OR_IY & 1) << BITPOS_C);
-    
-    if (*regs_IX_OR_IY & 0x8000)
-      regs.raf.F |= BIT_S;
-    if (*regs_IX_OR_IY == 0)
-      regs.raf.F |= BIT_Z;
-    if (word_parity(*regs_IX_OR_IY))
-      regs.raf.F |= BIT_P;
-    return(resGO);
-  }
-  
-  default:
-    return(resINV_INST);
-  }
-  
-  return(resINV_INST);
-}
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+//#include "ddconfig.h"
+
+#include 
+
+// local
+#include "r2kcl.h"
+#include "z80mac.h"
+
+
+unsigned   word_parity( u16_t  x ) {
+  // bitcount(x) performed by shift-and-add
+  u16_t  tmp = (x & 0x5555) + ((x & 0xAAAA) >> 1);
+  tmp = (tmp & 0x3333) + ((tmp & 0xCCCC) >> 2);
+  tmp = (tmp & 0x0F0F) + ((tmp & 0xF0F0) >> 4);
+  tmp = (tmp & 0x000F) + ((tmp & 0x0F00) >> 8);
+  
+  // parity determined by count being odd or even
+  return  0x01 ^ (tmp & 1);
+}
+
+/******** rabbit 2000 memory access helper functions *****************/
+u32_t  rabbit_mmu::logical_addr_to_phys( u16_t logical_addr ) {
+  u32_t  phys_addr = logical_addr;
+  unsigned     segnib = logical_addr >> 12;
+  
+  if (segnib >= 0xe)
+  {
+    phys_addr += ((u32_t)xpc) << 12;
+  }
+  else if ((u8_t)segnib >= ((segsize >> 4) & 0xf))
+  {
+    phys_addr += ((u32_t)stackseg) << 12;    
+  }
+  else if ((u8_t)segnib >= (segsize & 0xf))
+  {
+    phys_addr += ((u32_t)dataseg) << 12;    
+  }
+  return phys_addr;
+}
+
+void cl_r2k::store1( u16_t addr, t_mem val ) {
+  u32_t  phys_addr;
+  
+  if (mmu.io_flag == IOI) {
+    if ((mmu.mmidr ^ 0x80) & 0x80)
+      /* bit 7 = 0 --> use only 8-bits for internal I/O addresses */
+      addr = addr & 0x0ff;
+    
+    if (addr == MMIDR) {
+      mmu.mmidr = val;
+      return;
+    }
+    
+    if (addr == SADR) {
+      /* serial A (console when using the rabbit programming cable) */
+      putchar(val);
+      fflush(stdout);
+    }
+    return;
+  }
+  if (mmu.io_flag == IOE) {
+    /* I/O operation for external device (such as an ethernet controller) */
+    return;
+  }
+  
+  phys_addr = mmu.logical_addr_to_phys( addr );
+  ram->write(phys_addr, val);
+}
+
+void cl_r2k::store2( u16_t addr, u16_t val ) {
+  u32_t  phys_addr;
+  
+  if (mmu.io_flag == IOI) {
+    /* I/O operation for on-chip device (serial ports, timers, etc) */
+    return;
+  }
+  
+  if (mmu.io_flag == IOE) {
+    /* I/O operation for external device (such as an ethernet controller) */
+    return;
+  }
+  
+  phys_addr = mmu.logical_addr_to_phys( addr );
+  
+  ram->write(phys_addr,   val & 0xff);
+  ram->write(phys_addr+1, (val >> 8) & 0xff);
+}
+
+u8_t  cl_r2k::get1( u16_t addr ) {
+  u32_t  phys_addr = mmu.logical_addr_to_phys( addr );
+  
+  if (mmu.io_flag == IOI) {
+    /* stub for on-chip device I/O */
+    return 0;
+  }
+  if (mmu.io_flag == IOE) {
+    /* stub for external device I/O */
+    return 0;
+  }
+  
+  return ram->read(phys_addr);
+}
+
+u16_t  cl_r2k::get2( u16_t addr ) {
+  u32_t phys_addr = mmu.logical_addr_to_phys( addr );
+  u16_t  l, h;
+  
+  if (mmu.io_flag == IOI) {
+    /* stub for on-chip device I/O */
+    return 0;
+  }
+  if (mmu.io_flag == IOE) {
+    /* stub for external device I/O */
+    return 0;
+  }
+  
+  l = ram->read(phys_addr  );
+  h = ram->read(phys_addr+1);
+  
+  return (h << 8) | l;
+}
+
+t_mem       cl_r2k::fetch1( void ) {
+  return fetch( );
+}
+
+u16_t  cl_r2k::fetch2( void ) {
+  u16_t  c1, c2;
+  
+  c1 = fetch( );
+  c2 = fetch( );
+  return (c2 << 8) | c1;
+}
+
+t_mem cl_r2k::fetch(void) {
+  /*
+   * Fetch without checking for breakpoint hit
+   *
+   * Used by bool cl_uc::fetch(t_mem *code) in sim.src/uc.cc
+   * which does check for a breakpoint hit
+   */
+  
+  u32_t phys_addr = mmu.logical_addr_to_phys( PC );
+  ulong code;
+  
+  if (!rom)
+    return(0);
+  
+  code= rom->read(phys_addr);
+  PC = (PC + 1) & 0xffffUL;
+  vc.fetch++;
+  return(code);
+}
+
+/******** start rabbit 2000 specific codes *****************/
+int cl_r2k::inst_add_sp_d(t_mem code) {
+  u16_t  d = fetch( );
+  /* sign-extend d from 8-bits to 16-bits */
+  d |= (d>>7)*0xFF00;
+  regs.SP = (regs.SP + d) & 0xffff;
+  return(resGO);
+}
+
+int cl_r2k::inst_altd(t_mem code) {
+  // stub
+  return(resGO);
+}
+
+int
+cl_r2k::inst_r2k_ld(t_mem code)
+{
+  /* 0xC4  ld hl,(sp+n)
+   * 0xD4  ld (sp+n),hl
+   * 0xE4  ld hl,(ix+d)
+   *   DD E4 = ld hl,(hl+d)   [note: (hl+d) breaks the normal prefix pattern]
+   *   FD E4 = ld hl,(iy+d)
+   * 0xF4  ld (ix+d),hl
+   *   DD F4 = ld (hl+d),hl
+   *   FD F4 = ld (iy+d),hl
+   */
+  switch(code) {
+  case 0xC4:  regs.HL = get2( add_u16_nisp(regs.SP, fetch()) ); vc.rd+= 2; break;
+  case 0xD4:  store2( add_u16_nisp(regs.SP, fetch()), regs.HL ); vc.wr+= 2; break;
+  case 0xE4:  regs.HL = get2( add_u16_disp(regs.IX, fetch()) ); vc.rd+= 2; break;
+  case 0xF4:  store2( add_u16_disp(regs.IX, fetch()), regs.HL ); vc.wr+= 2; break;
+  default:
+    return(resINV_INST);
+  }
+  
+  return(resGO);
+}
+
+int cl_r2k::inst_r2k_ex (t_mem code) {
+  u16_t tempw;
+  
+  switch(code) {
+  case 0xE3:
+    // EX DE', HL  on rabbit processors
+    tempw = regs.aDE;
+    regs.aDE = regs.HL;
+    regs.HL = tempw;
+    return(resGO);
+    
+  default:
+    return(resINV_INST);
+  }
+}
+
+int cl_r2k::inst_ljp(t_mem code) {
+  u16_t  mn;
+  
+  mn = fetch2();  /* don't clobber PC before the fetch for xmem page */
+  mmu.xpc = fetch1();
+  PC = mn;
+  
+  return(resGO);
+}
+
+int cl_r2k::inst_lcall(t_mem code) {
+  u16_t  mn;
+  
+  push1(mmu.xpc);
+  push2(PC+2);
+  vc.wr+= 2;
+  
+  mn = fetch2();  /* don't clobber PC before the fetch for xmem page */
+  mmu.xpc = fetch1();
+  PC = mn;
+  
+  return(resGO);
+}
+
+int cl_r2k::inst_lret(t_mem code)
+{
+  u16_t u16;
+  u8_t u8;
+
+  pop2(u16);
+  pop1(u8);
+  mmu.xpc= u8;
+  PC= u16;
+  
+  return resGO;
+}
+
+int cl_r2k::inst_bool(t_mem code) {
+  regs.raf.F &= ~BIT_ALL;
+  if (regs.HL)
+    regs.HL = 1;
+  else
+    regs.raf.F |= BIT_Z;
+  return(resGO);
+}
+
+int cl_r2k::inst_r2k_and(t_mem code) {  // AND HL,DE
+  regs.HL &= regs.DE;
+  
+  regs.raf.F &= ~BIT_ALL;
+  if (regs.DE & 0x8000)
+    regs.raf.F |= BIT_S;
+  if (regs.DE == 0)
+    regs.raf.F |= BIT_Z;
+  if (word_parity(regs.DE))
+    regs.raf.F |= BIT_P;
+  return(resGO);
+}
+
+int cl_r2k::inst_r2k_or (t_mem code) {  // OR  HL,DE
+  regs.HL |= regs.DE;
+  
+  regs.raf.F &= ~BIT_ALL;
+  if (regs.DE & 0x8000)
+    regs.raf.F |= BIT_S;
+  if (regs.DE == 0)
+    regs.raf.F |= BIT_Z;
+  if (word_parity(regs.DE))
+    regs.raf.F |= BIT_P;
+  return(resGO);
+}
+
+int cl_r2k::inst_mul(t_mem code) {
+  long m;
+  long m1 = (long)(regs.BC & 0x7fff);
+  long m2 = (long)(regs.DE & 0x7fff);
+  if (regs.BC & 0x8000)
+    m1 -= (1 << 15);
+  if (regs.DE & 0x8000)
+    m2 -= (1 << 15);
+  m = m1 * m2;
+  regs.BC = ((unsigned long)(m) & 0xffff);
+  regs.HL = ((unsigned long)(m) >> 16) & 0xffff;
+  return(resGO);
+}
+
+int cl_r2k::inst_rl_de(t_mem code) {
+  unsigned int oldcarry = (regs.raf.F & BIT_C);
+  
+  regs.raf.F &= ~BIT_ALL;
+  regs.raf.F |= (((regs.DE >> 15) & 1U) << BITPOS_C);
+  regs.DE = (regs.DE << 1) | (oldcarry >> BITPOS_C);
+  
+  if (regs.DE & 0x8000)
+    regs.raf.F |= BIT_S;
+  if (regs.DE == 0)
+    regs.raf.F |= BIT_Z;
+  if (word_parity(regs.DE))
+    regs.raf.F |= BIT_P;
+  return(resGO);
+}
+
+int cl_r2k::inst_rr_de(t_mem code) {
+  unsigned int oldcarry = (regs.raf.F & BIT_C);
+
+  regs.raf.F &= ~BIT_ALL;
+  regs.raf.F |= ((regs.DE & 1) << BITPOS_C);
+  regs.DE = (regs.DE >> 1) | (oldcarry << (15 - BITPOS_C));
+  
+  if (regs.DE & 0x8000)
+    regs.raf.F |= BIT_S;
+  if (regs.DE == 0)
+    regs.raf.F |= BIT_Z;
+  if (word_parity(regs.DE))
+    regs.raf.F |= BIT_P;
+  return(resGO);
+}
+
+int cl_r2k::inst_rr_hl(t_mem code)    // RR HL
+{
+  unsigned int oldcarry = (regs.raf.F & BIT_C);
+  
+  regs.raf.F &= ~BIT_ALL;
+  regs.raf.F |= ((regs.HL & 1) << BITPOS_C);
+  regs.HL = (regs.HL >> 1) | (oldcarry << (15 - BITPOS_C));
+  
+  if (regs.HL & 0x8000)
+    regs.raf.F |= BIT_S;
+  if (regs.HL == 0)
+    regs.raf.F |= BIT_Z;
+  if (word_parity(regs.HL))
+    regs.raf.F |= BIT_P;
+  return(resGO);
+}
+
+
+int
+cl_r2k::inst_rst(t_mem code)
+{
+  switch(code) {
+    case 0xC7: // RST 0
+      push2(PC+2);
+      PC = iir + 0x00 * 2;
+      vc.wr+= 2;
+    break;
+    case 0xCF: // RST 8
+      return(resINV_INST);
+    
+    case 0xD7: // RST 10H
+      push2(PC+2);
+      PC = iir + 0x10 * 2;
+      vc.wr+= 2;
+    break;
+    case 0xDF: // RST 18H
+      push2(PC+2);
+      PC = iir + 0x18 * 2;
+      vc.wr+= 2;
+    break;
+    case 0xE7: // RST 20H
+      push2(PC+2);
+      PC = iir + 0x20 * 2;
+      vc.wr+= 2;
+    break;
+    case 0xEF: // RST 28H
+      //PC = 0x28;
+      /*push2(PC+2);
+      PC = iir + 0x28 * 2;
+      vc.wr+= 2;
+      break;*/
+      switch (regs.raf.A) {
+        case 0:
+          return(resBREAKPOINT);
+//          ::exit(0);
+        break;
+
+        case 1:
+          //printf("PUTCHAR-----> %xH\n", regs.hl.l);
+          putchar(regs.hl.l);
+          fflush(stdout);
+        break;
+      }
+    break;
+    case 0xF7: // RST 30H
+      return(resINV_INST);  // opcode is used for MUL on rabbit 2000+
+    break;
+    case 0xFF: // RST 38H
+      push2(PC+2);
+      PC = iir + 0x38 * 2;
+      vc.wr+= 2;
+    break;
+    default:
+      return(resINV_INST);
+    break;
+  }
+  return(resGO);
+}
+
+int cl_r2k::inst_xd(t_mem prefix)
+{
+  u16_t  *regs_IX_OR_IY = (prefix==0xdd)?(®s.IX):(®s.IY);
+  t_mem code;
+  
+  if (fetch(&code))
+    return(resBREAKPOINT);
+
+  switch (code) {
+
+  case 0x64: // LDP (Ix),HL
+    {
+      u16_t u16= *regs_IX_OR_IY;
+      t_addr al= ((regs.raf.A & 0xf) << 16) | u16;
+      t_addr ah= ((regs.raf.A & 0xf) << 16) | ((u16+1)&0xffff);
+      rom->write(al, regs.hl.l);
+      rom->write(ah, regs.hl.h);
+      vc.wr+= 2;
+      break;
+    }
+    
+  case 0x65: // LDP (mn),IX
+    {
+      u16_t ix= *regs_IX_OR_IY;
+      u16_t u16= fetch2();
+      t_addr al= ((regs.raf.A & 0xf) << 16) | u16;
+      t_addr ah= ((regs.raf.A & 0xf) << 16) | ((u16+1)&0xffff);
+      rom->write(al, ix&0xff);
+      rom->write(ah, ix>>8);
+      vc.wr+= 2;
+      break;
+    }
+    
+  case 0x6c: // LDP HL,(Ix)
+    {
+      u16_t u16= *regs_IX_OR_IY;
+      t_addr al= ((regs.raf.A & 0xf) << 16) | u16;
+      t_addr ah= ((regs.raf.A & 0xf) << 16) | ((u16+1)&0xffff);
+      regs.hl.l= rom->read(al);
+      regs.hl.h= rom->read(ah);
+      vc.rd+= 2;
+      break;
+    }
+    
+  case 0x6d: // LDP IX,(mn)
+    {
+      u8_t l,h;
+      u16_t u16= fetch2();
+      t_addr al= ((regs.raf.A & 0xf) << 16) | u16;
+      t_addr ah= ((regs.raf.A & 0xf) << 16) | ((u16+1)&0xffff);
+      l= rom->read(al);
+      h= rom->read(ah);
+      *regs_IX_OR_IY= h*256+l;
+      vc.rd+= 2;
+      break;
+    }
+    
+    // 0x06 LD A,(IX+A) is r4k+ instruction
+  case 0x21: // LD IX,nnnn
+  case 0x22: // LD (nnnn),IX
+    
+  case 0x2A: // LD IX,(nnnn)
+  case 0x2E: // LD LX,nn
+  case 0x36: // LD (IX+dd),nn
+  case 0x46: // LD B,(IX+dd)
+  case 0x4E: // LD C,(IX+dd)
+  case 0x56: // LD D,(IX+dd)
+  case 0x5E: // LD E,(IX+dd)
+  case 0x66: // LD H,(IX+dd)
+  case 0x6E: // LD L,(IX+dd)
+    
+  case 0x70: // LD (IX+dd),B
+  case 0x71: // LD (IX+dd),C
+  case 0x72: // LD (IX+dd),D
+  case 0x73: // LD (IX+dd),E
+  case 0x74: // LD (IX+dd),H
+  case 0x75: // LD (IX+dd),L
+  case 0x77: // LD (IX+dd),A
+  case 0x7E: // LD A,(IX+dd)
+  case 0xF9: // LD SP,IX
+    if (prefix == 0xdd)
+      return(inst_dd_ld(code));
+    else
+      return(inst_fd_ld(code));
+    
+  case 0x7C: // LD HL,IX
+    regs.HL = *regs_IX_OR_IY;  // LD HL, IX|IY for rabbit processors
+    return(resGO);
+  case 0x7D: // LD IX,HL
+    *regs_IX_OR_IY = regs.HL;   // LD IX|IY,HL for rabbit processors
+    return(resGO);
+    
+  case 0x23: // INC IX
+  case 0x34: // INC (IX+dd)
+    if (prefix == 0xdd)
+      return(inst_dd_inc(code));
+    else
+      return(inst_fd_inc(code));
+    
+  case 0x09: // ADD IX,BC
+  case 0x19: // ADD IX,DE
+  case 0x29: // ADD IX,IX
+  case 0x39: // ADD IX,SP
+  case 0x86: // ADD A,(IX)
+    if (prefix == 0xdd)
+      return(inst_dd_add(code));
+    else
+      return(inst_fd_add(code));
+    
+  case 0x2B: // DEC IX
+  case 0x35: // DEC (IX+dd)
+    if (prefix == 0xdd)
+      return(inst_dd_dec(code));
+    else
+      return(inst_fd_dec(code));
+    
+    // 0x4C  TEST IX is r4k+
+
+  case 0x8E: // ADC A,(IX)
+  case 0x96: // SUB (IX+dd)
+  case 0x9E: // SBC A,(IX+dd)
+  case 0xA6: // AND (IX+dd)
+  case 0xAE: // XOR (IX+dd)
+  case 0xB6: // OR (IX+dd)
+  case 0xBE: // CP (IX+dd)
+    if (prefix == 0xdd)
+      return(inst_dd_misc(code));
+    else
+      return(inst_fd_misc(code));
+    
+  case 0xC4: // LD IX,(SP+n)
+    *regs_IX_OR_IY = get2( add_u16_nisp(regs.SP, fetch()) );
+    vc.rd+= 2;
+    return(resGO);
+    
+  case 0xCB: // escape, IX prefix to CB commands
+    // fixme: limit the opcodes passed through to those officially
+    // documented as present on the rabbit processors
+    if (prefix == 0xdd)
+      return(inst_ddcb()); /* see inst_ddcb.cc */
+    else
+      return(inst_fdcb()); /* see inst_fdcb.cc */
+    
+  case 0xCC: // BOOL IX|IY
+    if (*regs_IX_OR_IY)
+      *regs_IX_OR_IY = 1;
+    
+    // update flags
+    regs.raf.F &= ~BIT_ALL;
+    // bit 15 will never be set, so S<=0
+    if (*regs_IX_OR_IY == 0)
+      regs.raf.F |= BIT_Z;
+    // L/V and C are always cleared
+    return(resGO);
+    
+  case 0xD4: // LD (SP+n),IX|IY
+    store2( add_u16_nisp(regs.SP, fetch()), *regs_IX_OR_IY );
+    vc.wr+= 2;
+    return(resGO);
+    
+  case 0xE1: // POP IX
+    *regs_IX_OR_IY = get2(regs.SP);
+    regs.SP+=2;
+    vc.rd+= 2;
+    return(resGO);
+    
+  case 0xE3: // EX (SP),IX
+  {
+    u16_t tempw;
+    
+    tempw = *regs_IX_OR_IY;
+    *regs_IX_OR_IY = get2(regs.SP);
+    store2(regs.SP, tempw);
+    vc.rd+= 2;
+    vc.wr+= 2;
+  }
+  return(resGO);
+  
+  case 0xE4:
+    if (prefix == 0xDD)
+      regs.HL = get2( add_u16_disp(regs.HL, fetch()) );
+    else
+      regs.HL = get2( add_u16_disp(regs.IY, fetch()) );
+    vc.rd+= 2;
+    return(resGO);
+    
+  case 0xE5: // PUSH IX
+    push2(*regs_IX_OR_IY);
+    vc.wr+= 2;
+    return(resGO);
+    
+  case 0xE9: // JP (IX)
+    PC = *regs_IX_OR_IY;
+    return(resGO);
+    
+  case 0xEA:
+    push2(PC);
+    PC = *regs_IX_OR_IY;
+    vc.wr+= 2;
+    return(resGO);
+    
+  case 0xDC: // AND IX|IY,DE  for rabbit processors
+  case 0xEC: // OR  IX|IY,DE  for rabbit processors
+    if (code == 0xDC)
+      *regs_IX_OR_IY &= regs.DE;
+    else
+      *regs_IX_OR_IY |= regs.DE;
+    
+    // update flags
+    regs.raf.F &= ~BIT_ALL;
+    if (*regs_IX_OR_IY & 0x8000)
+      regs.raf.F |= BIT_S;
+    if (regs_IX_OR_IY == 0)
+      regs.raf.F |= BIT_Z;
+    if (word_parity(*regs_IX_OR_IY))
+      regs.raf.F |= BIT_P;
+    return(resGO);
+    
+  case 0xF4: // LD (HL|IY+d),HL
+    if (prefix == 0xDD)
+      store2( add_u16_disp(regs.HL, fetch()), regs.HL );
+    else
+      store2( add_u16_disp(regs.IY, fetch()), regs.HL );
+    vc.wr+= 2;
+    return(resGO);
+    
+  case 0xFC: // RR IX|IY
+  {
+    u16_t  tmp = (regs.raf.F & BIT_C) << (15 - BITPOS_C);
+    tmp |= (*regs_IX_OR_IY >> 1);
+    
+    regs.raf.F = (regs.raf.F & ~BIT_C) | ((*regs_IX_OR_IY & 1) << BITPOS_C);
+    
+    if (*regs_IX_OR_IY & 0x8000)
+      regs.raf.F |= BIT_S;
+    if (*regs_IX_OR_IY == 0)
+      regs.raf.F |= BIT_Z;
+    if (word_parity(*regs_IX_OR_IY))
+      regs.raf.F |= BIT_P;
+    return(resGO);
+  }
+  
+  default:
+    return(resINV_INST);
+  }
+  
+  return(resINV_INST);
+}
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/z80.src/inst_xd.cc sdcc-4.2.0+dfsg/sim/ucsim/z80.src/inst_xd.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/z80.src/inst_xd.cc	2019-01-07 14:30:39.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/z80.src/inst_xd.cc	2020-08-25 12:30:39.000000000 +0000
@@ -40,157 +40,199 @@
   switch (code) {
     case 0x21: // LD IX,nnnn
       regs_IX_OR_IY = fetch2();
-    return(resGO);
+      tick(13);
+      return(resGO);
     case 0x22: // LD (nnnn),IX
       tw = fetch2();
       store2(tw, regs_IX_OR_IY);
       vc.wr+= 2;
-    return(resGO);
+      tick(19);
+      return(resGO);
     case 0x26: // LD HX,nn
       regs_iX_h = fetch1();
-    return(resGO);
+      tick(10);
+      return(resGO);
     case 0x2A: // LD IX,(nnnn)
       tw = fetch2();
       regs_IX_OR_IY = get2(tw);
       vc.rd+= 2;
-    return(resGO);
+      tick(19);
+      return(resGO);
     case 0x2E: // LD LX,nn
       regs_iX_l = fetch1();
-    return(resGO);
+      tick(10);
+      return(resGO);
     case 0x36: // LD (IX+dd),nn
       tw = add_u16_disp(regs_IX_OR_IY, fetch());
       store1(tw, fetch());
       vc.wr++;
-    return(resGO);
+      tick(18);
+      return(resGO);
     case 0x44: // LD B,HX
       regs.bc.h = regs_iX_h;
-    return(resGO);
+      tick(7);
+      return(resGO);
     case 0x45: // LD B,LX
       regs.bc.h = regs_iX_l;
-    return(resGO);
+      tick(7);
+      return(resGO);
     case 0x46: // LD B,(IX+dd)
       regs.bc.h = get1(add_u16_disp(regs_IX_OR_IY,fetch()));
       vc.rd++;
-    return(resGO);
+      tick(18);
+      return(resGO);
     case 0x4C: // LD C,HX
       regs.bc.l = regs_iX_h;
-    return(resGO);
+      tick(7);
+      return(resGO);
     case 0x4D: // LD C,LX
       regs.bc.l = regs_iX_l;
-    return(resGO);
+      tick(7);
+      return(resGO);
     case 0x4E: // LD C,(IX+dd)
       regs.bc.l = get1(add_u16_disp(regs_IX_OR_IY,fetch()));
       vc.rd++;
-    return(resGO);
+      tick(18);
+      return(resGO);
     case 0x54: // LD D,HX
       regs.de.h = regs_iX_h;
-    return(resGO);
+      tick(7);
+      return(resGO);
     case 0x55: // LD D,LX
       regs.de.h = regs_iX_l;
-    return(resGO);
+      tick(7);
+      return(resGO);
     case 0x56: // LD D,(IX+dd)
       regs.de.h = get1(add_u16_disp(regs_IX_OR_IY,fetch()));
       vc.rd++;
-    return(resGO);
-    case 0x5C: // LD E,H
-      regs.de.l = regs.hl.h;
-    return(resGO);
-    case 0x5D: // LD E,L
-      regs.de.l = regs.hl.l;
-    return(resGO);
+      tick(18);
+      return(resGO);
+    case 0x5C: // LD E,H   E,HX?
+      regs.de.l = regs_iX_h;//regs.hl.h;
+      return(resGO);
+    case 0x5D: // LD E,L   E,LX?
+      regs.de.l = regs_iX_l;//regs.hl.l;
+      return(resGO);
     case 0x5E: // LD E,(IX+dd)
       regs.de.l = get1(add_u16_disp(regs_IX_OR_IY,fetch()));
       vc.rd++;
-    return(resGO);
+      tick(18);
+      return(resGO);
     case 0x60: // LD HX,B
       regs_iX_h = regs.bc.h;
-    return(resGO);
+      tick(7);
+      return(resGO);
     case 0x61: // LD HX,C
       regs_iX_h = regs.bc.l;
-    return(resGO);
+      tick(7);
+      return(resGO);
     case 0x62: // LD HX,D
       regs_iX_h = regs.de.h;
-    return(resGO);
+      tick(7);
+      return(resGO);
     case 0x63: // LD HX,E
       regs_iX_h = regs.de.l;
-    return(resGO);
+      tick(7);
+      return(resGO);
     case 0x64: // LD HX,HX
-    return(resGO);
+      tick(7);
+      return(resGO);
     case 0x65: // LD HX,LX
       regs_iX_h = regs_iX_l;
-    return(resGO);
+      tick(7);
+      return(resGO);
     case 0x66: // LD H,(IX+dd)
       regs.hl.h = get1(add_u16_disp(regs_IX_OR_IY,fetch()));
       vc.rd++;
-    return(resGO);
+      tick(18);
+      return(resGO);
     case 0x67: // LD HX,A
       regs_iX_h = regs.raf.A;
-    return(resGO);
+      tick(7);
+      return(resGO);
     case 0x68: // LD LX,B
       regs_iX_l = regs.bc.h;
-    return(resGO);
+      tick(7);
+      return(resGO);
     case 0x69: // LD LX,C
       regs_iX_l = regs.bc.l;
-    return(resGO);
+      tick(7);
+      return(resGO);
     case 0x6A: // LD LX,D
       regs_iX_l = regs.de.h;
-    return(resGO);
+      tick(7);
+      return(resGO);
     case 0x6B: // LD LX,E
       regs_iX_l = regs.de.l;
-    return(resGO);
-    case 0x6C: // LD LX,HX
-      regs_iX_l = regs.hl.h;
-    return(resGO);
+      tick(7);
+      return(resGO);
+    case 0x6C: // LD LX,HX ?
+      regs_iX_l = regs_iX_h;//regs.hl.h;
+      return(resGO);
     case 0x6D: // LD LX,LX
-    return(resGO);
+      tick(7);
+      return(resGO);
     case 0x6E: // LD L,(IX+dd)
       regs.hl.l = get1(add_u16_disp(regs_IX_OR_IY,fetch()));
       vc.rd++;
-    return(resGO);
+      tick(18);
+      return(resGO);
     case 0x6F: // LD LX,A
       regs_iX_l = regs.raf.A;
-    return(resGO);
+      tick(7);
+      return(resGO);
     case 0x70: // LD (IX+dd),B
       store1(add_u16_disp(regs_IX_OR_IY,fetch()), regs.bc.h);
       vc.wr++;
-    return(resGO);
+      tick(18);
+      return(resGO);
     case 0x71: // LD (IX+dd),C
       store1(add_u16_disp(regs_IX_OR_IY,fetch()), regs.bc.l);
       vc.wr++;
-    return(resGO);
+      tick(18);
+      return(resGO);
     case 0x72: // LD (IX+dd),D
       store1(add_u16_disp(regs_IX_OR_IY,fetch()), regs.de.h);
       vc.wr++;
-    return(resGO);
+      tick(18);
+      return(resGO);
     case 0x73: // LD (IX+dd),E
       store1(add_u16_disp(regs_IX_OR_IY,fetch()), regs.de.l);
       vc.wr++;
-    return(resGO);
+      tick(18);
+      return(resGO);
     case 0x74: // LD (IX+dd),H
       store1(add_u16_disp(regs_IX_OR_IY,fetch()), regs.hl.h);
       vc.wr++;
-    return(resGO);
+      tick(18);
+      return(resGO);
     case 0x75: // LD (IX+dd),L
       store1(add_u16_disp(regs_IX_OR_IY,fetch()), regs.hl.l);
       vc.wr++;
-    return(resGO);
+      tick(18);
+      return(resGO);
     case 0x77: // LD (IX+dd),A
       store1(add_u16_disp(regs_IX_OR_IY,fetch()), regs.raf.A);
       vc.wr++;
-    return(resGO);
+      tick(18);
+      return(resGO);
     case 0x7C: // LD A,HX
       regs.raf.A = regs_iX_h;
-    return(resGO);
+      tick(7);
+      return(resGO);
     case 0x7D: // LD A,LX
       regs.raf.A = regs_iX_l;
-    return(resGO);
+      tick(7);
+      return(resGO);
     case 0x7E: // LD A,(IX+dd)
       regs.raf.A = get1(add_u16_disp(regs_IX_OR_IY,fetch()));
       vc.rd++;
-    return(resGO);
+      tick(18);
+      return(resGO);
     case 0xF9: // LD SP,IX
       regs.SP = regs_IX_OR_IY;
-    return(resGO);
+      tick(9);
+      return(resGO);
   }
   return(resINV_INST);
 }
@@ -201,21 +243,27 @@
   switch (code) {
     case 0x09: // ADD IX,BC
       add_IX_Word(regs.BC);
+      tick(14);
       return(resGO);
     case 0x19: // ADD IX,DE
       add_IX_Word(regs.DE);
+      tick(14);
       return(resGO);
     case 0x29: // ADD IX,IX
       add_IX_Word(regs_IX_OR_IY);
+      tick(14);
       return(resGO);
     case 0x39: // ADD IX,SP
       add_IX_Word(regs.SP);
-    return(resGO);
+      tick(14);
+      return(resGO);
     case 0x84: // ADD A,HX
       add_A_bytereg(regs_iX_h);
+      tick(7);
       return(resGO);
     case 0x85: // ADD A,LX
       add_A_bytereg(regs_iX_l);
+      tick(7);
       return(resGO);
     case 0x86: // ADD A,(IX+dd)
       { unsigned char ourtmp;
@@ -224,6 +272,7 @@
         ourtmp = get1(addr);
         add_A_bytereg(ourtmp);
 	vc.rd++;
+	tick(18);
       }
       return(resGO);
   }
@@ -237,6 +286,7 @@
     case 0xe5: // PUSH IX
       push2(regs_IX_OR_IY);
       vc.wr+= 2;
+      tick(14);
     return(resGO);
   }
   return(resINV_INST);
@@ -248,13 +298,16 @@
   switch(code) {
     case 0x23: // INC IX
       ++regs_IX_OR_IY;
-    break;
+      tick(9);
+      break;
     case 0x24: // INC HX
       inc(regs_iX_h);
-    break;
+      tick(7);
+      break;
     case 0x2C: // INC LX
       inc(regs_iX_l);
-    break;
+      tick(7);
+      break;
     case 0x34: // INC (IX+dd)
       {
         t_addr addr;
@@ -265,8 +318,9 @@
         store1(addr, tmp);
 	vc.rd++;
 	vc.wr++;
+	tick(22);
       }
-    break;
+      break;
     default:
       return(resINV_INST);
     break;
@@ -280,13 +334,16 @@
   switch(code) {
     case 0x25: // DEC HX
       dec(regs_iX_h);
-    break;
+      tick(9);
+      break;
     case 0x2B: // DEC IX
       --regs_IX_OR_IY;
-    break;
+      tick(9);
+      break;
     case 0x2D: // DEC LX
       dec(regs_iX_l);
-    break;
+      tick(7);
+      break;
     case 0x35: // DEC (IX+dd)
       {
         t_addr addr;
@@ -297,8 +354,9 @@
         store1(addr, tmp);
 	vc.rd++;
 	vc.wr++;
+	tick(22);
       }
-    break;
+      break;
     default:
       return(resINV_INST);
     break;
@@ -314,10 +372,12 @@
   switch(code) {
     case 0x8C: // ADC A,HX
       adc_A_bytereg(regs_iX_h);
-    return(resGO);
+      tick(7);
+      return(resGO);
     case 0x8D: // ADC A,LX
       adc_A_bytereg(regs_iX_l);
-    return(resGO);
+      tick(7);
+      return(resGO);
     case 0x8E: // ADC A,(IX+dd)
       { unsigned char utmp;
         t_addr addr;
@@ -325,90 +385,109 @@
         utmp = get1(addr);
         adc_A_bytereg(utmp);
 	vc.rd++;
+	tick(18);
       }
-    return(resGO);
+      return(resGO);
 
     case 0x94: // SUB HX
       sub_A_bytereg(regs_iX_h);
-    return(resGO);
+      tick(7);
+      return(resGO);
     case 0x95: // SUB LX
       sub_A_bytereg(regs_iX_l);
-    return(resGO);
+      tick(7);
+      return(resGO);
     case 0x96: // SUB (IX+dd)
       { unsigned char tmp1;
         tmp1 = get1(add_u16_disp(regs_IX_OR_IY, fetch()));
         sub_A_bytereg(tmp1);
 	vc.rd++;
+	tick(18);
       }
-    return(resGO);
+      return(resGO);
 
     case 0x9C: // SBC A,HX
       sbc_A_bytereg(regs_iX_h);
-    return(resGO);
+      tick(7);
+      return(resGO);
     case 0x9D: // SBC A,LX
       sbc_A_bytereg(regs_iX_l);
-    return(resGO);
+      tick(7);
+      return(resGO);
     case 0x9E: // SBC A,(IX+dd)
       { unsigned char utmp;
         utmp = get1(add_u16_disp(regs_IX_OR_IY, fetch()));
         sbc_A_bytereg(utmp);
 	vc.rd++;
+	tick(18);
       }
-    return(resGO);
+      return(resGO);
 
     case 0xA4: // AND HX
       and_A_bytereg(regs_iX_h);
-    return(resGO);
+      tick(7);
+      return(resGO);
     case 0xA5: // AND LX
       and_A_bytereg(regs_iX_l);
-    return(resGO);
+      tick(7);
+      return(resGO);
     case 0xA6: // AND (IX+dd)
       { unsigned char utmp;
         utmp = get1(add_u16_disp(regs_IX_OR_IY, fetch()));
         and_A_bytereg(utmp);
 	vc.rd++;
+	tick(18);
       }
-    return(resGO);
+      return(resGO);
 
     case 0xAC: // XOR HX
       xor_A_bytereg(regs_iX_h);
-    return(resGO);
+      tick(7);
+      return(resGO);
     case 0xAD: // XOR LX
       xor_A_bytereg(regs_iX_l);
-    return(resGO);
+      tick(7);
+      return(resGO);
     case 0xAE: // XOR (IX+dd)
       { unsigned char utmp;
         utmp = get1(add_u16_disp(regs_IX_OR_IY, fetch()));
         xor_A_bytereg(utmp);
 	vc.rd++;
+	tick(18);
       }
-    return(resGO);
+      return(resGO);
 
     case 0xB4: // OR HX
       or_A_bytereg(regs_iX_h);
-    return(resGO);
+      tick(7);
+      return(resGO);
     case 0xB5: // OR LX
       or_A_bytereg(regs_iX_l);
-    return(resGO);
+      tick(7);
+      return(resGO);
     case 0xB6: // OR (IX+dd)
       { unsigned char utmp;
         utmp = get1(add_u16_disp(regs_IX_OR_IY, fetch()));
         or_A_bytereg(utmp);
 	vc.rd++;
+	tick(18);
       }
-    return(resGO);
+      return(resGO);
 
     case 0xBC: // CP HX
       cp_bytereg(regs_iX_h);
-    return(resGO);
+      tick(7);
+      return(resGO);
     case 0xBD: // CP LX
       cp_bytereg(regs_iX_l);
-    return(resGO);
+      tick(7);
+      return(resGO);
     case 0xBE: // CP (IX+dd)
       { unsigned char utmp;
         utmp = get1(add_u16_disp(regs_IX_OR_IY, fetch()));
         cp_bytereg(utmp);
 	vc.rd++;
+	tick(18);
       }
     return(resGO);
   }
@@ -535,7 +614,8 @@
         regs_IX_OR_IY = get2(regs.SP);
         regs.SP+=2;
 	vc.rd+= 2;
-      return(resGO);
+	tick(13);
+	return(resGO);
 
       case 0xE3: // EX (SP),IX
         {
@@ -546,20 +626,23 @@
           store2(regs.SP, tempw);
 	  vc.rd+= 2;
 	  vc.wr+= 2;
+	  tick(22);
         }
-      return(resGO);
+	return(resGO);
 
       case 0xE5: // PUSH IX
         push2(regs_IX_OR_IY);
 	vc.wr+= 2;
-      return(resGO);
+	tick(14);
+	return(resGO);
 
       case 0xE9: // JP (IX)
         PC = regs_IX_OR_IY;
-      return(resGO);
+	tick(7);
+	return(resGO);
 
       default:
-      return(resINV_INST);
+	return(resINV_INST);
     }
   return(resINV_INST);
 }
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/z80.src/inst_xxcb.cc sdcc-4.2.0+dfsg/sim/ucsim/z80.src/inst_xxcb.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/z80.src/inst_xxcb.cc	2017-03-02 10:01:56.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/z80.src/inst_xxcb.cc	2020-08-01 16:50:18.000000000 +0000
@@ -74,7 +74,8 @@
   }
   store1(addr, tmp);
   vc.wr++;
-  
+
+  tick(22);
   return(resGO);
 }
 
@@ -118,7 +119,8 @@
   }
   store1(addr, tmp);
   vc.wr++;
-  
+
+  tick(22);
   return(resGO);
 }
 
@@ -162,7 +164,8 @@
   }
   store1(addr, tmp);
   vc.wr++;
-  
+
+  tick(22);
   return(resGO);
 }
 
@@ -206,7 +209,8 @@
   }
   store1(addr, tmp);
   vc.wr++;
-  
+
+  tick(22);
   return(resGO);
 }
 
@@ -250,7 +254,8 @@
   }
   store1(addr, tmp);
   vc.wr++;
-  
+
+  tick(22);
   return(resGO);
 }
 
@@ -294,7 +299,8 @@
   }
   store1(addr, tmp);
   vc.wr++;
-  
+
+  tick(22);
   return(resGO);
 }
 
@@ -338,7 +344,8 @@
   }
   store1(addr, tmp);
   vc.wr++;
-  
+
+  tick(22);
   return(resGO);
 }
 
@@ -382,7 +389,8 @@
   }
   store1(addr, tmp);
   vc.wr++;
-  
+
+  tick(22);
   return(resGO);
 }
 
@@ -402,7 +410,8 @@
   
   store1(addr, tmp);
   vc.wr++;
-  
+
+  tick(19);
   return(resGO);
 }
 
@@ -441,7 +450,8 @@
   }
   store1(addr, tmp);
   vc.wr++;
-  
+
+  tick(22);
   return(resGO);
 }
 
@@ -480,7 +490,8 @@
   }
   store1(addr, tmp);
   vc.wr++;
-  
+
+  tick(22);
   return(resGO);
 }
 
@@ -496,7 +507,6 @@
 
   if (fetch(&code))
     return(resBREAKPOINT);
-  tick(1);
   switch (code)
     {
     case 0x00: // RLC B
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/z80.src/lr35902.cc sdcc-4.2.0+dfsg/sim/ucsim/z80.src/lr35902.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/z80.src/lr35902.cc	2019-05-06 09:55:43.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/z80.src/lr35902.cc	2021-03-20 16:44:50.000000000 +0000
@@ -1,670 +1,10 @@
-/*
- * Simulator for the LR35902 used in the gb console.
- * The processor is closely related to the Z-80, so the C++
- * emulator object inherits from it.
- *
- */
-
-/* This file is part of microcontroller simulator: ucsim.
-
- UCSIM is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
- 
- UCSIM is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- GNU General Public License for more details.
- 
- You should have received a copy of the GNU General Public License
- along with UCSIM; see the file COPYING.  If not, write to the Free
- Software Foundation, 59 Temple Place - Suite 330, Boston, MA
- 02111-1307, USA. */
-/*@1@*/
-
-#include "ddconfig.h"
-
-#include  /* for va_list */
-#include 
-#include 
-#include 
-#include "i_string.h"
-
-// prj
-#include "pobjcl.h"
-
-// sim
-#include "simcl.h"
-
-// local
-#include "z80cl.h"
-#include "lr35902cl.h"
-#include "glob.h"
-
-#define uint32 t_addr
-#define uint8 unsigned char
-
-/*******************************************************************/
-
-lr35902_memory::lr35902_memory( cl_uc &uc_parent_ref ):uc_r(uc_parent_ref) { }
-
-cl_lr35902::cl_lr35902(struct cpu_entry *Itype, class cl_sim *asim):
-  cl_z80(Itype, asim), mem(*this)
-{
-  type= Itype;
-}
-
-int
-cl_lr35902::init(void)
-{
-  cl_uc::init(); /* Memories now exist */
-
-  //rom= address_space(MEM_ROM_ID);  // code goes here...
-  
-  //  ram= mem(MEM_XRAM);
-  //ram= address_space(MEM_XRAM_ID);  // data goes here...
-  
-  
-  // zero out ram(this is assumed in regression tests)
-  for (int i=0xA000; i<0xFF80; i++) {
-    ram->set((t_addr) i, 0);
-  }
-
-  return(0);
-}
-
-char *
-cl_lr35902::id_string(void)
-{
-  return((char*)"LR35902");
-}
-
-
-void
-cl_lr35902::mk_hw_elements(void)
-{
-  //class cl_base *o;
-  cl_uc::mk_hw_elements();
-}
-
-void lr35902_memory::init(void) {
-  cl_address_space *as_rom;
-  cl_address_space *as_ram;
-  
-  as_rom = new cl_address_space("rom"/*MEM_ROM_ID*/,
-				lr35902_rom_start, lr35902_rom_size, 8);
-  as_rom->init();
-  uc_r.address_spaces->add(as_rom);
-  rom = as_rom;
-  
-  as_ram = new cl_address_space(MEM_XRAM_ID,
-				lr35902_ram_start, lr35902_ram_size, 8);
-  as_ram->init();
-  uc_r.address_spaces->add(as_ram);
-  ram = as_ram;
-}
-
-void
-cl_lr35902::make_memories(void)
-{
-  mem.init( );
-  rom= mem.rom;
-  ram= mem.ram;
-  
-  regs8= new cl_address_space("regs8", 0, 16, 8);
-  regs8->init();
-  regs8->get_cell(0)->decode((t_mem*)®s.raf.A);
-  regs8->get_cell(1)->decode((t_mem*)®s.raf.F);
-  regs8->get_cell(2)->decode((t_mem*)®s.bc.h);
-  regs8->get_cell(3)->decode((t_mem*)®s.bc.l);
-  regs8->get_cell(4)->decode((t_mem*)®s.de.h);
-  regs8->get_cell(5)->decode((t_mem*)®s.de.l);
-  regs8->get_cell(6)->decode((t_mem*)®s.hl.h);
-  regs8->get_cell(7)->decode((t_mem*)®s.hl.l);
-
-  regs8->get_cell(8)->decode((t_mem*)®s.ralt_af.aA);
-  regs8->get_cell(9)->decode((t_mem*)®s.ralt_af.aF);
-  regs8->get_cell(10)->decode((t_mem*)®s.a_bc.h);
-  regs8->get_cell(11)->decode((t_mem*)®s.a_bc.l);
-  regs8->get_cell(12)->decode((t_mem*)®s.a_de.h);
-  regs8->get_cell(13)->decode((t_mem*)®s.a_de.l);
-  regs8->get_cell(14)->decode((t_mem*)®s.a_hl.h);
-  regs8->get_cell(15)->decode((t_mem*)®s.a_hl.l);
-
-  regs16= new cl_address_space("regs16", 0, 11, 16);
-  regs16->init();
-
-  regs16->get_cell(0)->decode((t_mem*)®s.AF);
-  regs16->get_cell(1)->decode((t_mem*)®s.BC);
-  regs16->get_cell(2)->decode((t_mem*)®s.DE);
-  regs16->get_cell(3)->decode((t_mem*)®s.HL);
-  regs16->get_cell(4)->decode((t_mem*)®s.IX);
-  regs16->get_cell(5)->decode((t_mem*)®s.IY);
-  regs16->get_cell(6)->decode((t_mem*)®s.SP);
-  regs16->get_cell(7)->decode((t_mem*)®s.aAF);
-  regs16->get_cell(8)->decode((t_mem*)®s.aBC);
-  regs16->get_cell(9)->decode((t_mem*)®s.aDE);
-  regs16->get_cell(10)->decode((t_mem*)®s.aHL);
-
-  address_spaces->add(regs8);
-  address_spaces->add(regs16);
-
-  class cl_var *v;
-  vars->add(v= new cl_var(cchars("A"), regs8, 0, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("F"), regs8, 1, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("B"), regs8, 2, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("C"), regs8, 3, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("D"), regs8, 4, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("E"), regs8, 5, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("H"), regs8, 6, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("L"), regs8, 7, ""));
-  v->init();
-
-  vars->add(v= new cl_var(cchars("ALT_A"), regs8, 8, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("ALT_F"), regs8, 9, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("ALT_B"), regs8, 10, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("ALT_C"), regs8, 11, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("ALT_D"), regs8, 12, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("ALT_E"), regs8, 13, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("ALT_H"), regs8, 14, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("ALT_L"), regs8, 15, ""));
-  v->init();
-
-  vars->add(v= new cl_var(cchars("AF"), regs16, 0, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("BC"), regs16, 1, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("DE"), regs16, 2, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("HL"), regs16, 3, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("IX"), regs16, 4, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("IY"), regs16, 5, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("SP"), regs16, 6, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("ALT_AF"), regs16, 7, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("ALT_BC"), regs16, 8, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("ALT_DE"), regs16, 9, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("ALT_HL"), regs16, 10, ""));
-  v->init();
-}
-
-
-void cl_lr35902::store1( u16_t addr, t_mem val ) {
-  mem.store1( addr, val );
-}
-
-void cl_lr35902::store2( u16_t addr, u16_t val ) {
-  mem.store2( addr, val );
-}
-
-u8_t  cl_lr35902::get1( u16_t addr ) {
-  return mem.get1( addr );
-}
-
-u16_t  cl_lr35902::get2( u16_t addr ) {
-  return mem.get2( addr );
-}
-
-void lr35902_memory::store1( u16_t addr, t_mem val ) {
-  if (addr < lr35902_ram_start) {
-    /* flag illegal operation ? */
-    return;
-  }
-  
-  if ((addr- lr35902_ram_start) < lr35902_ram_size) {
-    ram->write(addr, val);
-  }
-}
-
-void lr35902_memory::store2( u16_t addr, u16_t val ) {
-  store1(addr,   val & 0xff);
-  store1(addr+1, (val >> 8) & 0xff);
-}
-
-u8_t  lr35902_memory::get1( u16_t addr ) {
-  if (addr < lr35902_rom_size) {
-    return rom->read(addr);    
-  }
-  
-  if (addr < lr35902_ram_start) {
-    /* flag illegal operation ? */
-    return (addr & 0xff);
-  }
-  
-  if ((addr-lr35902_ram_start) < lr35902_ram_size) {
-    return ram->read(addr);
-  }
-  
-  return (addr & 0xff);
-}
-
-u16_t  lr35902_memory::get2( u16_t addr ) {
-  u16_t  l, h;
-  
-  l = get1(addr  );
-  h = get1(addr+1);
-  
-  return (h << 8) | l;
-}
-
-/*
- * Help command interpreter
- */
-
-struct dis_entry *
-cl_lr35902::dis_tbl(void)
-{
-  return(disass_lr35902);
-}
-
-
-int
-cl_lr35902::inst_length(t_addr addr)
-{
-  int len = 0;
-
-  get_disasm_info(addr, &len, NULL, NULL);
-
-  return len;
-}
-
-int
-cl_lr35902::inst_branch(t_addr addr)
-{
-  int b;
-
-  get_disasm_info(addr, NULL, &b, NULL);
-
-  return b;
-}
-
-int
-cl_lr35902::longest_inst(void)
-{
-  return 4;
-}
-
-
-const char *
-cl_lr35902::get_disasm_info(t_addr addr,
-                        int *ret_len,
-                        int *ret_branch,
-                        int *immed_offset)
-{
-  const char *b = NULL;
-  uint code;
-  int len = 0;
-  int immed_n = 0;
-  int i;
-  int start_addr = addr;
-  struct dis_entry *dis_e;
-
-  code= rom->get(addr++);
-  dis_e = NULL;
-
-  switch(code) {
-    case 0xcb:  /* ESC code to lots of op-codes, all 2-byte */
-      code= rom->get(addr++);
-      i= 0;
-      while ((code & disass_lr35902_cb[i].mask) != disass_lr35902_cb[i].code &&
-        disass_lr35902_cb[i].mnemonic)
-        i++;
-      dis_e = &disass_lr35902_cb[i];
-      b= disass_lr35902_cb[i].mnemonic;
-      if (b != NULL)
-        len += (disass_lr35902_cb[i].length + 1);
-    break;
-
-    default:
-      i= 0;
-      while ((code & disass_lr35902[i].mask) != disass_lr35902[i].code &&
-             disass_lr35902[i].mnemonic)
-        i++;
-      dis_e = &disass_lr35902[i];
-      b= disass_lr35902[i].mnemonic;
-      if (b != NULL)
-        len += (disass_lr35902[i].length);
-    break;
-  }
-
-
-  if (ret_branch) {
-    *ret_branch = dis_e->branch;
-  }
-
-  if (immed_offset) {
-    if (immed_n > 0)
-         *immed_offset = immed_n;
-    else *immed_offset = (addr - start_addr);
-  }
-
-  if (len == 0)
-    len = 1;
-
-  if (ret_len)
-    *ret_len = len;
-
-  return b;
-}
-
-char *
-cl_lr35902::disass(t_addr addr, const char *sep)
-{
-  char work[256], temp[20];
-  const char *b;
-  char *buf, *p, *t;
-  int len = 0;
-  int immed_offset = 0;
-
-  p= work;
-
-  b = get_disasm_info(addr, &len, NULL, &immed_offset);
-
-  if (b == NULL) {
-    buf= (char*)malloc(30);
-    strcpy(buf, "UNKNOWN/INVALID");
-    return(buf);
-  }
-
-  while (*b)
-    {
-      if (*b == '%')
-        {
-          b++;
-          switch (*(b++))
-            {
-            case 'd': // d    jump relative target, signed? byte immediate operand
-              sprintf(temp, "#%d", (char)rom->get(addr+immed_offset));
-              ++immed_offset;
-              break;
-            case 'w': // w    word immediate operand
-              sprintf(temp, "#0x%04x",
-                 (uint)((rom->get(addr+immed_offset)) |
-                        (rom->get(addr+immed_offset+1)<<8)) );
-              ++immed_offset;
-              ++immed_offset;
-              break;
-            case 'b': // b    byte immediate operand
-              sprintf(temp, "#0x%02x", (uint)rom->get(addr+immed_offset));
-              ++immed_offset;
-              break;
-            default:
-              strcpy(temp, "?");
-              break;
-            }
-          t= temp;
-          while (*t)
-            *(p++)= *(t++);
-        }
-      else
-        *(p++)= *(b++);
-    }
-  *p= '\0';
-
-  p= strchr(work, ' ');
-  if (!p)
-    {
-      buf= strdup(work);
-      return(buf);
-    }
-  if (sep == NULL)
-    buf= (char *)malloc(6+strlen(p)+1);
-  else
-    buf= (char *)malloc((p-work)+strlen(sep)+strlen(p)+1);
-  for (p= work, t= buf; *p != ' '; p++, t++)
-    *t= *p;
-  p++;
-  *t= '\0';
-  if (sep == NULL)
-    {
-      while (strlen(buf) < 6)
-        strcat(buf, " ");
-    }
-  else
-    strcat(buf, sep);
-  strcat(buf, p);
-  return(buf);
-}
-
-
-void
-cl_lr35902::print_regs(class cl_console_base *con)
-{
-  con->dd_printf("SZ-A-PNC  Flags= 0x%02x %3d %c  ",
-                 regs.raf.F, regs.raf.F, isprint(regs.raf.F)?regs.raf.F:'.');
-  con->dd_printf("A= 0x%02x %3d %c\n",
-                 regs.raf.A, regs.raf.A, isprint(regs.raf.A)?regs.raf.A:'.');
-  con->dd_printf("%c%c-%c-%c%c%c\n",
-                 (regs.raf.F&BIT_S)?'1':'0',
-                 (regs.raf.F&BIT_Z)?'1':'0',
-                 (regs.raf.F&BIT_A)?'1':'0',
-                 (regs.raf.F&BIT_P)?'1':'0',
-                 (regs.raf.F&BIT_N)?'1':'0',
-                 (regs.raf.F&BIT_C)?'1':'0');
-  con->dd_printf("BC= 0x%04x [BC]= %02x %3d %c  ",
-                 regs.BC, ram->get(regs.BC), ram->get(regs.BC),
-                 isprint(ram->get(regs.BC))?ram->get(regs.BC):'.');
-  con->dd_printf("DE= 0x%04x [DE]= %02x %3d %c  ",
-                 regs.DE, ram->get(regs.DE), ram->get(regs.DE),
-                 isprint(ram->get(regs.DE))?ram->get(regs.DE):'.');
-  con->dd_printf("HL= 0x%04x [HL]= %02x %3d %c\n",
-                 regs.HL, ram->get(regs.HL), ram->get(regs.HL),
-                 isprint(ram->get(regs.HL))?ram->get(regs.HL):'.');
-  con->dd_printf("SP= 0x%04x [SP]= %02x %3d %c\n",
-                 regs.SP, ram->get(regs.SP), ram->get(regs.SP),
-                 isprint(ram->get(regs.SP))?ram->get(regs.SP):'.');
-
-  print_disass(PC, con);
-}
-
-/*
- * Execution
- */
-
-int
-cl_lr35902::exec_inst(void)
-{

-  t_mem code;

-

-  instPC= PC;

-

-  if (fetch(&code))

-    return(resBREAKPOINT);

-  tick(1);

-  switch (code)
-    {
-    case 0x00: return(inst_nop(code));
-    case 0x01: case 0x02: case 0x06: return(inst_ld(code));
-    case 0x03: case 0x04: return(inst_inc(code));
-    case 0x05: return(inst_dec(code));
-    case 0x07: return(inst_rlca(code));
-
-    case 0x08: return(inst_st_sp_abs(code));
-    case 0x09: return(inst_add(code));
-    case 0x0a: case 0x0e: return(inst_ld(code));
-    case 0x0b: case 0x0d: return(inst_dec(code));
-    case 0x0c: return(inst_inc(code));
-    case 0x0f: return(inst_rrca(code));
-
-
-    case 0x10: return(inst_stop0(code));
-    case 0x11: case 0x12: case 0x16: return(inst_ld(code));
-    case 0x13: case 0x14: return(inst_inc(code));
-    case 0x15: return(inst_dec(code));
-    case 0x17: return(inst_rla(code));
-
-    case 0x18: return(inst_jr(code));
-    case 0x19: return(inst_add(code));
-    case 0x1a: case 0x1e: return(inst_ld(code));
-    case 0x1b: case 0x1d: return(inst_dec(code));
-    case 0x1c: return(inst_inc(code));
-    case 0x1f: return(inst_rra(code));
-
-
-    case 0x20: return(inst_jr(code));
-    case 0x21: case 0x26: return(inst_ld(code));
-    case 0x22: return inst_ldi(code);
-    case 0x23: case 0x24: return(inst_inc(code));
-    case 0x25: return(inst_dec(code));
-    case 0x27: return(inst_daa(code));
-      
-    case 0x28: return(inst_jr(code));
-    case 0x29: return(inst_add(code));
-    case 0x2a: return(inst_ldi(code));
-    case 0x2b: case 0x2d: return(inst_dec(code));
-    case 0x2c: return(inst_inc(code));
-    case 0x2e: return(inst_ld(code));
-    case 0x2f: return(inst_cpl(code));
-
-    case 0x30: return(inst_jr(code));
-    case 0x31: case 0x36: return(inst_ld(code));
-    case 0x32: return(inst_ldd(code));
-    case 0x33: case 0x34: return(inst_inc(code));
-    case 0x35: return(inst_dec(code));
-    case 0x37: return(inst_scf(code));
-      
-    case 0x38: return(inst_jr(code));
-    case 0x39: return(inst_add(code));
-    case 0x3a: return inst_ldd(code);
-    case 0x3b: case 0x3d: return(inst_dec(code));
-    case 0x3c: return(inst_inc(code));
-    case 0x3e: return(inst_ld(code));
-    case 0x3f: return(inst_ccf(code));
-
-    case 0x40: case 0x41: case 0x42: case 0x43: case 0x44: case 0x45: case 0x46: case 0x47:
-    case 0x48: case 0x49: case 0x4a: case 0x4b: case 0x4c: case 0x4d: case 0x4e: case 0x4f:
-      return(inst_ld(code));
-
-    case 0x50: case 0x51: case 0x52: case 0x53: case 0x54: case 0x55: case 0x56: case 0x57:
-    case 0x58: case 0x59: case 0x5a: case 0x5b: case 0x5c: case 0x5d: case 0x5e: case 0x5f:
-      return(inst_ld(code));
-
-    case 0x60: case 0x61: case 0x62: case 0x63: case 0x64: case 0x65: case 0x66: case 0x67:
-    case 0x68: case 0x69: case 0x6a: case 0x6b: case 0x6c: case 0x6d: case 0x6e: case 0x6f:
-      return(inst_ld(code));
-
-    case 0x70: case 0x71: case 0x72: case 0x73: case 0x74: case 0x75: case 0x77:
-    case 0x78: case 0x79: case 0x7a: case 0x7b: case 0x7c: case 0x7d: case 0x7e: case 0x7f:
-      return(inst_ld(code));
-    case 0x76: return(inst_halt(code));
-
-    case 0x80: case 0x81: case 0x82: case 0x83: case 0x84: case 0x85: case 0x86: case 0x87:
-      return(inst_add(code));
-    case 0x88: case 0x89: case 0x8a: case 0x8b: case 0x8c: case 0x8d: case 0x8e: case 0x8f:
-      return(inst_adc(code));
-
-    case 0x90: case 0x91: case 0x92: case 0x93: case 0x94: case 0x95: case 0x96: case 0x97:
-      return(inst_sub(code));
-    case 0x98: case 0x99: case 0x9a: case 0x9b: case 0x9c: case 0x9d: case 0x9e: case 0x9f:
-      return(inst_sbc(code));
-
-    case 0xa0: case 0xa1: case 0xa2: case 0xa3: case 0xa4: case 0xa5: case 0xa6: case 0xa7:
-      return(inst_and(code));
-    case 0xa8: case 0xa9: case 0xaa: case 0xab: case 0xac: case 0xad: case 0xae: case 0xaf:
-      return(inst_xor(code));
-
-    case 0xb0: case 0xb1: case 0xb2: case 0xb3: case 0xb4: case 0xb5: case 0xb6: case 0xb7:
-      return(inst_or(code));
-    case 0xb8: case 0xb9: case 0xba: case 0xbb: case 0xbc: case 0xbd: case 0xbe: case 0xbf:
-      return(inst_cp(code));
-
-    case 0xc0: return(inst_ret(code));
-    case 0xc1: return(inst_pop(code));
-    case 0xc2: case 0xc3: return(inst_jp(code));
-    case 0xc4: return(inst_call(code));
-    case 0xc5: return(inst_push(code));
-    case 0xc6: return(inst_add(code));
-    case 0xc7: return(inst_rst(code));
-
-    case 0xc8: case 0xc9: return(inst_ret(code));
-    case 0xca: return(inst_jp(code));
-
-      /* CB escapes out to 2 byte opcodes(CB include), opcodes
-         to do register bit manipulations */
-    case 0xcb: return(inst_cb( ));
-    case 0xcc: case 0xcd: return(inst_call(code));
-    case 0xce: return(inst_adc(code));
-    case 0xcf: return(inst_rst(code));
-
-    case 0xd0: return(inst_ret(code));
-    case 0xd1: return(inst_pop(code));
-    case 0xd2: return(inst_jp(code));
-    case 0xd3: break;
-    case 0xd4: return(inst_call(code));
-    case 0xd5: return(inst_push(code));
-    case 0xd6: return(inst_sub(code));
-    case 0xd7: return(inst_rst(code));
-
-    case 0xd8: return(inst_ret(code));
- case 0xd9: return(inst_reti(code));
-    case 0xda: return(inst_jp(code));
-    case 0xdb: break;
-    case 0xdc: return(inst_call(code));
-      
- case 0xdd: break;  /* IX register doesn't exist on the LR35902 */
-    case 0xde: return(inst_sbc(code));
-    case 0xdf: return(inst_rst(code));
-      
-      
-    case 0xe0: return(inst_ldh(code));
-    case 0xe1: return(inst_pop(code));
-    case 0xe2: return(inst_ldh(code));
-    case 0xe3:
- case 0xe4: break;
-    case 0xe5: return(inst_push(code));
-    case 0xe6: return(inst_and(code));
-    case 0xe7: return(inst_rst(code));
-
-    case 0xe8: return(inst_add_sp_d(code));
-    case 0xe9: return(inst_jp(code));
-    case 0xea: return(inst_ld16(code));
-    case 0xeb:
-    case 0xec: case 0xed: break;
-    case 0xee: return(inst_xor(code));
-    case 0xef: return(inst_rst(code));
-      
-    case 0xf0: return(inst_ldh(code));
-    case 0xf1: return(inst_pop(code));
- case 0xf2: return(inst_ldh(code));
-    case 0xf3: return(inst_di(code));
-    case 0xf4: break;
-    case 0xf5: return(inst_push(code));
-    case 0xf6: return(inst_or(code));
-    case 0xf7: return(inst_rst(code));
-
-    case 0xf8: return(inst_ldhl_sp(code));
-    case 0xf9: return(inst_ld(code));
-    case 0xfa: return(inst_ld16(code));
-    case 0xfb: return(inst_ei(code));
-    case 0xfc: 
-    case 0xfd: break;
-    case 0xfe: return(inst_cp(code));
-    case 0xff: return(inst_rst(code));
-    }
-
-  PC= rom->inc_address(PC, -1);
-
-  sim->stop(resINV_INST);
-  return(resINV_INST);
-}
+/*@1@*/
+
+#include "lr35902cl.h"
+
+cl_lr35902::cl_lr35902(struct cpu_entry *Itype, class cl_sim *asim):
+  cl_gb80(Itype, asim)
+{
+}
+
+/* End of z80.src/lr35902.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/z80.src/lr35902cl.h sdcc-4.2.0+dfsg/sim/ucsim/z80.src/lr35902cl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/z80.src/lr35902cl.h	2017-01-24 13:53:15.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/z80.src/lr35902cl.h	2021-03-20 16:44:50.000000000 +0000
@@ -1,116 +1,18 @@
-/*
- * Simulator of microcontrollers (lr35902cl.h)
- *
- */
-
-/* This file is part of microcontroller simulator: ucsim.
-
-UCSIM is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2 of the License, or
-(at your option) any later version.
-
-UCSIM is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with UCSIM; see the file COPYING.  If not, write to the Free
-Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-02111-1307, USA. */
-/*@1@*/
-
-#ifndef LR35902_CL
-#define LR35902_CL
-
-#include "z80cl.h"
-
-class cl_lr35902;
-
-const t_addr  lr35902_rom_start = 0x0000;
-const t_addr  lr35902_rom_size  = 0x6000;
-
-const t_addr  lr35902_ram_start = 0xA000;
-const t_addr  lr35902_ram_size  = 0x5F80;
-
-class lr35902_memory
-{
- protected:
-  cl_uc  &uc_r;
-  
- public:
-  cl_memory *rom;
-  cl_memory *ram;
-  
-  lr35902_memory( cl_uc &uc_p );
-  
-  virtual void init( void );
-  
-  
-  virtual void store1( u16_t addr, t_mem val );
-  virtual void store2( u16_t addr, u16_t val );
-  
-  virtual u8_t  get1( u16_t addr );
-  virtual u16_t  get2( u16_t addr );
-  
-  // fetch not included b/c it only uses the rom
-};
-
-
-class cl_lr35902: public cl_z80
-{
-public:
-  lr35902_memory    mem;
-  
-public:
-  cl_lr35902(struct cpu_entry *Itype, class cl_sim *asim);
-  virtual int init(void);
-  virtual char *id_string(void);
-  
-  //virtual t_addr get_mem_size(enum mem_class type);
-  virtual void mk_hw_elements(void);
-  virtual void make_memories(void);
-  
-  virtual struct dis_entry *dis_tbl(void);
-  virtual int inst_length(t_addr addr);
-  virtual int inst_branch(t_addr addr);
-  virtual int longest_inst(void);
-  virtual char *disass(t_addr addr, const char *sep);
-  virtual void print_regs(class cl_console_base *con);
-
-  virtual int exec_inst(void);
-
-  virtual const char *get_disasm_info(t_addr addr,
-                        int *ret_len,
-                        int *ret_branch,
-                        int *immed_offset);
-  
-
-  // memory access altered to use the 'mem' object
-  virtual void store1( u16_t addr, t_mem val );
-  virtual void store2( u16_t addr, u16_t val );
-  
-  virtual u8_t  get1( u16_t addr );
-  virtual u16_t  get2( u16_t addr );
-  
-  
-  // see #include "instcl.h" for Z80 versions
-  /* instruction function that are add / modified from the Z80 versions */
-  virtual int inst_cb(void);
-  
-  virtual int inst_st_sp_abs(t_mem code);
-  virtual int inst_stop0    (t_mem code);
-  
-  virtual int inst_ldi   (t_mem code);
-  virtual int inst_ldd   (t_mem code);
-  virtual int inst_ldh   (t_mem code);
-  
-  virtual int inst_reti    (t_mem code);
-  virtual int inst_add_sp_d(t_mem code);
-  virtual int inst_ld16    (t_mem code);
-  virtual int inst_ldhl_sp (t_mem code);
-  
-};
-
-#endif /* LR35902_CL */
+/*@1@*/
+
+#ifndef LR35902_HEADER
+#define LR35902_HEADER
+
+#include "gb80cl.h"
+
+
+class cl_lr35902: public cl_gb80
+{
+public:
+  cl_lr35902(struct cpu_entry *Itype, class cl_sim *asim);
+};
+
+
+#endif
+
+/* End of z80.src/lr35902cl.h */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/z80.src/Makefile.in sdcc-4.2.0+dfsg/sim/ucsim/z80.src/Makefile.in
--- sdcc-4.0.0+dfsg/sim/ucsim/z80.src/Makefile.in	2018-12-05 13:58:20.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/z80.src/Makefile.in	2022-01-09 14:02:03.000000000 +0000
@@ -4,6 +4,9 @@
 # (c) Drotos Daniel, Talker Bt. 1997
 #
 
+# tool name
+TN		= z80
+
 STARTYEAR	= 1997
 
 SHELL		= /bin/sh
@@ -24,8 +27,8 @@
 CPPFLAGS        = @CPPFLAGS@ -I$(srcdir) -I$(top_srcdir) -I$(top_builddir) \
 		  -I$(top_srcdir)/cmd.src -I$(top_srcdir)/sim.src \
 		  -I$(top_srcdir)/gui.src
-CFLAGS          = @CFLAGS@ @WALL_FLAG@
-CXXFLAGS        = @CXXFLAGS@ @WALL_FLAG@
+CFLAGS          = @WALL_FLAG@ @CFLAGS@
+CXXFLAGS        = @WALL_FLAG@ @CXXFLAGS@
 LDFLAGS         = @LDFLAGS@
 PICOPT		= @PICOPT@
 SHAREDLIB	= @SHAREDLIB@
@@ -58,44 +61,57 @@
 		  inst_ddcb.o \
 		  inst_fdcb.o \
 		  glob_r2k.o inst_r2k.o inst_ed_r2k.o r2k.o \
-		  glob_lr35902.o inst_lr35902.o lr35902.o \
-		  simz80.o z80.o ez80.o
-OBJECTS_EXE	= sz80.o
+		  glob_gb80.o inst_gb80.o gb80.o lr35902.o \
+		  sim$(TN).o $(TN).o e$(TN).o
+OBJECTS_EXE	= s$(TN).o
 OBJECTS		= $(OBJECTS_SHARED) $(OBJECTS_EXE)
 
-Z80ASM		= 
+# short/long exe and lib name
+SEN		= s$(TN)$(EXEEXT)
+LEN		= ucsim_$(TN)$(EXEEXT)
+SONAME		= libucsim_$(TN).so
 
 enable_dlso	= @enable_dlso@
 dlso_ok		= @dlso_ok@
 
+Z80ASM		= 
 #TEST_OBJ	= test_bit.hex test_dis.hex test_mov.hex test_jmp.hex \
 #		  test_arith.hex
 
 # Compiling entire program or any subproject
 # ------------------------------------------
-all: checkconf otherlibs z80.src tests
+all: checkconf otherlibs $(TN).src tests
 
 tests: $(TEST_OBJ)
 
 
 # Compiling and installing everything and runing test
 # ---------------------------------------------------
-install: all installdirs
-	$(INSTALL) sz80$(EXEEXT) $(DESTDIR)$(bindir)/`echo sz80|sed '$(transform)'`$(EXEEXT)
-	$(STRIP) $(DESTDIR)$(bindir)/`echo sz80|sed '$(transform)'`$(EXEEXT)
+install: all installdirs install_shared_lib
+	$(INSTALL) $(SEN) $(DESTDIR)$(bindir)/$(SEN)
+	$(STRIP) $(DESTDIR)$(bindir)/$(SEN)
+	$(INSTALL) $(LEN) $(DESTDIR)$(bindir)/$(LEN)
+	$(STRIP) $(DESTDIR)$(bindir)/$(LEN)
 
 
 # Deleting all the installed files
 # --------------------------------
 uninstall:
-	rm -f $(DESTDIR)$(bindir)/`echo sz80|sed '$(transform)'`$(EXEEXT)
+	rm -f $(DESTDIR)$(bindir)/$(SEN)
+	rm -f $(DESTDIR)$(bindir)/$(LEN)
+	rm -f $(DESTDIR)$(libdir)/$(SONAME)
 
 
 # Performing self-test
 # --------------------
 check: test
 
+.PHONY:	test baseline
 test:
+	@$(MAKE) --no-print-directory -C test
+
+baseline:
+	@$(MAKE) --no-print-directory -C test baseline
 
 
 # Performing installation test
@@ -123,21 +139,28 @@
 # --------
 .SUFFIXES: .asm .hex
 
-z80.src: sz80$(EXEEXT) shared_lib
+$(TN).src: $(SEN) $(LEN) shared_lib
 
-sz80$(EXEEXT): $(OBJECTS) $(top_builddir)/libcmd.a $(top_builddir)/libguiucsim.a $(top_builddir)/libsim.a $(top_builddir)/libucsimutil.a
+$(SEN): $(OBJECTS) $(top_builddir)/libcmd.a $(top_builddir)/libguiucsim.a $(top_builddir)/libsim.a $(top_builddir)/libucsimutil.a
 	$(CXX) $(CXXFLAGS) $(LDFLAGS) $(OBJECTS) $(LIBS) -o $@
 
+$(LEN): $(SEN)
+	cp $< $@
+
 ifeq ($(dlso_ok),yes)
-shared_lib: $(top_builddir)/sz80.so
+shared_lib: $(top_builddir)/$(SONAME)
+install_shared_lib: shared_lib
+	test -d $(DESTDIR)$(libdir) || $(INSTALL) -d $(DESTDIR)$(libdir)
+	$(INSTALL) $(top_builddir)/$(SONAME) $(DESTDIR)$(libdir)/$(SONAME)
 else
 shared_lib:
-	@$(top_srcdir)/mkecho $(top_builddir) "No z80 shared lib made."
+	@$(top_srcdir)/mkecho $(top_builddir) "No $(TN) shared lib made."
 	@$(top_srcdir)/mkecho $(top_builddir) "(SHAREDLIB="$(SHAREDLIB)",dl_ok="$(dl_ok)",enable_dlso="$(enable_dlso)")"
+install_shared_lib:
 endif
 
-$(top_builddir)/sz80.so: $(OBJECTS_SHARED)
-	$(CXX) -shared $(LDFLAGS) $(OBJECTS_SHARED) -o $(top_builddir)/sz80.so
+$(top_builddir)/$(SONAME): $(OBJECTS_SHARED)
+	$(CXX) -shared $(LDFLAGS) $(OBJECTS_SHARED) -o $(top_builddir)/s$(TN).so
 
 otherlibs: $(top_builddir)/libcmd.a $(top_builddir)/libguiucsim.a $(top_builddir)/libsim.a $(top_builddir)/libucsimutil.a
 
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/z80.src/r2k.cc sdcc-4.2.0+dfsg/sim/ucsim/z80.src/r2k.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/z80.src/r2k.cc	2019-05-06 09:55:43.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/z80.src/r2k.cc	2021-07-31 09:28:22.000000000 +0000
@@ -30,22 +30,23 @@
 02111-1307, USA. */
 /*@1@*/
 
-#include "ddconfig.h"
+//#include "ddconfig.h"
 
-#include  /* for va_list */
+//#include  /* for va_list */
 #include 
 #include 
 #include 
-#include "i_string.h"
+#include 
 
 // prj
-#include "pobjcl.h"
+//#include "pobjcl.h"
+#include "globals.h"
 
 // sim
-#include "simcl.h"
+//#include "simcl.h"
 
 // local
-#include "z80cl.h"
+//#include "z80cl.h"
 #include "r2kcl.h"
 #include "glob.h"
 
@@ -85,20 +86,25 @@
   for (int i=0x8000; i<0x10000; i++) {
     ram->set((t_addr) i, 0);
   }
-
+  /*
+  sp_limit_opt= new cl_sp_limit_opt(this);
+  sp_limit_opt->set_value((char*)"0xf000");
+  application->options->add(sp_limit_opt);
+  */
+  
   return(0);
 }
 
-char *
+const char *
 cl_r2k::id_string(void)
 {
-  return((char*)"rabbit 2000");
+  return("rabbit 2000");
 }
 
-char *
+const char *
 cl_r3ka::id_string(void)
 {
-  return((char*)"rabbit 3000A");
+  return("rabbit 3000A");
 }
 
 /*
@@ -122,7 +128,11 @@
 cl_r2k::mk_hw_elements(void)
 {
   //class cl_base *o;
+  class cl_hw *h;
   cl_uc::mk_hw_elements();
+  
+  add_hw(h= new cl_z80_cpu(this));
+  h->init();
 }
 
 void
@@ -130,17 +140,17 @@
 {
   class cl_address_space *as;
 
-  rom= ram= as= new cl_address_space("rom", 0, 0x10000, 8);
+  rom= ram= as= new cl_address_space("rom", 0, 0x100000, 8);
   as->init();
   address_spaces->add(as);
 
   class cl_address_decoder *ad;
   class cl_memory_chip *chip;
 
-  chip= new cl_memory_chip("rom_chip", 0x10000, 8);
+  chip= new cl_chip8("rom_chip", 0x100000, 8);
   chip->init();
   memchips->add(chip);
-  ad= new cl_address_decoder(as= address_space("rom"), chip, 0, 0xffff, 0);
+  ad= new cl_address_decoder(as= address_space("rom"), chip, 0, 0xfffff, 0);
   ad->init();
   as->decoders->add(ad);
   ad->activate(0);
@@ -185,67 +195,49 @@
   address_spaces->add(regs8);
   address_spaces->add(regs16);
 
-  class cl_var *v;
-  vars->add(v= new cl_var(cchars("A"), regs8, 0, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("F"), regs8, 1, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("B"), regs8, 2, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("C"), regs8, 3, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("D"), regs8, 4, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("E"), regs8, 5, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("H"), regs8, 6, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("L"), regs8, 7, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("IIR"), regs8, 8, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("EIR"), regs8, 9, ""));
-  v->init();
-
-  vars->add(v= new cl_var(cchars("ALT_A"), regs8, 10, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("ALT_F"), regs8, 11, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("ALT_B"), regs8, 12, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("ALT_C"), regs8, 13, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("ALT_D"), regs8, 14, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("ALT_E"), regs8, 15, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("ALT_H"), regs8, 16, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("ALT_L"), regs8, 17, ""));
-  v->init();
-
-  vars->add(v= new cl_var(cchars("AF"), regs16, 0, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("BC"), regs16, 1, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("DE"), regs16, 2, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("HL"), regs16, 3, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("IX"), regs16, 4, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("IY"), regs16, 5, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("SP"), regs16, 6, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("ALT_AF"), regs16, 7, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("ALT_BC"), regs16, 8, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("ALT_DE"), regs16, 9, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("ALT_HL"), regs16, 10, ""));
-  v->init();
+  vars->add("A", regs8, 0, 7, 0, "Accumulator");
+  vars->add("F", regs8, 1, 7, 0, "Flags");
+  vars->add("F_C", regs8, 1, BITPOS_C, BITPOS_C, "Carry");
+  vars->add("F_SUB", regs8, 1, BITPOS_SUB, BITPOS_SUB, "");
+  vars->add("F_P", regs8, 1, BITPOS_P, BITPOS_P, "");
+  vars->add("F_A", regs8, 1, BITPOS_A, BITPOS_A, "");
+  vars->add("F_Z", regs8, 1, BITPOS_Z, BITPOS_Z, "Zero");
+  vars->add("F_S", regs8, 1, BITPOS_S, BITPOS_S, "");
+  vars->add("B", regs8, 2, 7, 0, "");
+  vars->add("C", regs8, 3, 7, 0, "");
+  vars->add("D", regs8, 4, 7, 0, "");
+  vars->add("E", regs8, 5, 7, 0, "");
+  vars->add("H", regs8, 6, 7, 0, "");
+  vars->add("L", regs8, 7, 7, 0, "");
+  vars->add("IIR", regs8, 8, 7, 0, "");
+  vars->add("EIR", regs8, 9, 7, 0, "");
+
+  vars->add("ALT_A", regs8, 10, 7, 0, "Alt Accumulator");
+  vars->add("ALT_F", regs8, 11, 7, 0, "Alt Flags");
+  vars->add("ALT_F_C", regs8, 11, BITPOS_C, BITPOS_C, "ALT_Carry");
+  vars->add("ALT_F_SUB", regs8, 11, BITPOS_SUB, BITPOS_SUB, "");
+  vars->add("ALT_F_P", regs8, 11, BITPOS_P, BITPOS_P, "");
+  vars->add("ALT_F_A", regs8, 11, BITPOS_A, BITPOS_A, "");
+  vars->add("ALT_F_Z", regs8, 11, BITPOS_Z, BITPOS_Z, "ALT_Zero");
+  vars->add("ALT_F_S", regs8, 11, BITPOS_S, BITPOS_S, "");
+  vars->add("ALT_B", regs8, 12, 7, 0, "");
+  vars->add("ALT_C", regs8, 13, 7, 0, "");
+  vars->add("ALT_D", regs8, 14, 7, 0, "");
+  vars->add("ALT_E", regs8, 15, 7, 0, "");
+  vars->add("ALT_H", regs8, 16, 7, 0, "");
+  vars->add("ALT_L", regs8, 17, 7, 0, "");
+
+  vars->add("AF", regs16, 0, 15, 0, "Accumulator/Flags");
+  vars->add("BC", regs16, 1, 15, 0, "");
+  vars->add("DE", regs16, 2, 15, 0, "");
+  vars->add("HL", regs16, 3, 15, 0, "");
+  vars->add("IX", regs16, 4, 15, 0, "");
+  vars->add("IY", regs16, 5, 15, 0, "");
+  vars->add("SP", regs16, 6, 15, 0, "Stack Pointer");
+  vars->add("ALT_AF", regs16, 7, 15, 0, "Alt Accumulator/Flags");
+  vars->add("ALT_BC", regs16, 8, 15, 0, "");
+  vars->add("ALT_DE", regs16, 9, 15, 0, "");
+  vars->add("ALT_HL", regs16, 10, 15, 0, "");
 }
 
 
@@ -426,88 +418,88 @@
 }
 
 char *
-cl_r2k::disass(t_addr addr, const char *sep)
+cl_r2k::disass(t_addr addr)
 {
-  char work[256], temp[20];
+  chars work, temp;
   const char *b;
-  char *buf, *p, *t;
   int len = 0;
   int immed_offset = 0;
-
-  p= work;
-
+  bool first= true;
+  
+  work= "";
   b = get_disasm_info(addr, &len, NULL, &immed_offset);
-
-  if (b == NULL) {
-    buf= (char*)malloc(30);
-    strcpy(buf, "UNKNOWN/INVALID");
-    return(buf);
-  }
+  if (b == NULL)
+    {
+      return strdup("UNKNOWN/INVALID");
+    }
 
   while (*b)
     {
+      if ((*b == ' ') && first)
+	{
+	  first= false;
+	  while (work.len() < 6) work.append(' ');
+	}
       if (*b == '%')
         {
+	  temp= "";
           b++;
           switch (*(b++))
             {
             case 'd': // d    jump relative target, signed? byte immediate operand
-              sprintf(temp, "#%d", (char)rom->get(addr+immed_offset));
+              temp.format("%d", (char)rom->get(addr+immed_offset));
               ++immed_offset;
               break;
             case 'w': // w    word immediate operand
-              sprintf(temp, "#0x%04x",
-                 (uint)((rom->get(addr+immed_offset)) |
-                        (rom->get(addr+immed_offset+1)<<8)) );
+              temp.format("0x%04x",
+			  (uint)((rom->get(addr+immed_offset)) |
+				 (rom->get(addr+immed_offset+1)<<8)) );
               ++immed_offset;
               ++immed_offset;
               break;
             case 'b': // b    byte immediate operand
-              sprintf(temp, "#0x%02x", (uint)rom->get(addr+immed_offset));
+              temp.format("0x%02x", (uint)rom->get(addr+immed_offset));
               ++immed_offset;
               break;
             default:
-              strcpy(temp, "?");
+              temp= "?";
               break;
             }
-          t= temp;
-          while (*t)
-            *(p++)= *(t++);
+	  work+= temp;
         }
       else
-        *(p++)= *(b++);
+	work+= *(b++);
     }
-  *p= '\0';
 
-  p= strchr(work, ' ');
-  if (!p)
-    {
-      buf= strdup(work);
-      return(buf);
-    }
-  if (sep == NULL)
-    buf= (char *)malloc(6+strlen(p)+1);
-  else
-    buf= (char *)malloc((p-work)+strlen(sep)+strlen(p)+1);
-  for (p= work, t= buf; *p != ' '; p++, t++)
-    *t= *p;
-  p++;
-  *t= '\0';
-  if (sep == NULL)
+  return strdup(work.c_str());
+}
+
+
+static FILE *log_file= NULL;
+static unsigned int cyc= 0;
+
+void
+cl_r2k::save_hist()
+{
+  cl_z80::save_hist();
+  if (juj&2)
     {
-      while (strlen(buf) < 6)
-        strcat(buf, " ");
+      if (log_file==NULL && PC==0x16) log_file= fopen("log.txt","w");
+      if (log_file!=NULL) {
+	fprintf(log_file, "%6u %06x ", cyc, AU(PC));
+	fprintf(log_file, "%02x %02x ", regs.raf.A, (regs.raf.F)&0xc1);
+	fprintf(log_file, "%04x %04x %04x ", regs.BC, regs.DE, regs.HL);
+	fprintf(log_file, "%04x %04x %04x ", regs.IX, regs.IY, regs.SP);
+	fprintf(log_file, "\n");
+	cyc++;
+      }
     }
-  else
-    strcat(buf, sep);
-  strcat(buf, p);
-  return(buf);
 }
 
-
 void
 cl_r2k::print_regs(class cl_console_base *con)
 {
+  con->dd_color("answer");
   con->dd_printf("SZ-A-PNC  Flags= 0x%02x %3d %c  ",
                  regs.raf.F, regs.raf.F, isprint(regs.raf.F)?regs.raf.F:'.');
   con->dd_printf("A= 0x%02x %3d %c\n",
@@ -515,9 +507,9 @@
   con->dd_printf("%c%c-%c-%c%c%c\n",
                  (regs.raf.F&BIT_S)?'1':'0',
                  (regs.raf.F&BIT_Z)?'1':'0',
-                 (regs.raf.F&BIT_A)?'1':'0',
+                 'x',//(regs.raf.F&BIT_A)?'1':'0',
                  (regs.raf.F&BIT_P)?'1':'0',
-                 (regs.raf.F&BIT_N)?'1':'0',
+                 'x',//(regs.raf.F&BIT_N)?'1':'0',
                  (regs.raf.F&BIT_C)?'1':'0');
   con->dd_printf("BC= 0x%04x [BC]= %02x %3d %c  ",
                  regs.BC, ram->get(regs.BC), ram->get(regs.BC),
@@ -537,6 +529,7 @@
   con->dd_printf("SP= 0x%04x [SP]= %02x %3d %c\n",
                  regs.SP, ram->get(regs.SP), ram->get(regs.SP),
                  isprint(ram->get(regs.SP))?ram->get(regs.SP):'.');
+  //con->dd_printf("SP limit= 0x%04x\n", AU(sp_limit));
 
   print_disass(PC, con);
 }
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/z80.src/r2kcl.h sdcc-4.2.0+dfsg/sim/ucsim/z80.src/r2kcl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/z80.src/r2kcl.h	2017-01-24 13:53:15.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/z80.src/r2kcl.h	2021-07-31 09:28:22.000000000 +0000
@@ -1,167 +1,170 @@
-/*
- * Simulator of microcontrollers (z80cl.h)
- *
- * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
- *
- * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
- *
- */
-
-/* This file is part of microcontroller simulator: ucsim.
-
-UCSIM is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2 of the License, or
-(at your option) any later version.
-
-UCSIM is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with UCSIM; see the file COPYING.  If not, write to the Free
-Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-02111-1307, USA. */
-/*@1@*/
-
-#ifndef R2KCL_HEADER
-#define R2KCL_HEADER
-
-#include "z80cl.h"
-
-  /* TODO: maybe this should become an enum */
-#define IOI  1  // next instruction uses internal I/O space
-#define IOE  2  // next instruction uses external I/O space
-
-#define MMIDR 0x10   /* MMU Instruction/Data Register */
-#define SADR  0xC0   /* Serial A Data Register in IOI (internal I/O space) */
-
-
-class cl_r2k;
-
-class rabbit_mmu {
-public:
-  cl_r2k     *parent_p;
-  
-  /* Note: DEF_REGPAIR is defined in regsz80.h */
-  
-  u8_t  xpc;
-  u8_t  dataseg;
-  u8_t  stackseg;
-  u8_t  segsize;
-  
-  u8_t  io_flag; /* pseudo register for ioi/ioe prefixes */
-  
-  u8_t  mmidr;  /* MMU Instruction/Data Register __at 0x10 */
-  
-  rabbit_mmu( cl_r2k *parent_ip ):parent_p(parent_ip),
-    xpc(0), dataseg(0), stackseg(0), segsize(0xFF)
-    { }
-  
-  u32_t/*TYPE_UDWORD*/  logical_addr_to_phys( u16_t logical_addr );
-};
-
-
-class cl_r2k: public cl_z80
-{
-public:
-  // from cl_z80:
-  //class cl_memory *ram;
-  //class cl_memory *rom;
-  //struct t_regs regs;  
-  
-  rabbit_mmu   mmu;
-
-  u16_t ins_start;  /* PC value for start of the current instruction */
-  u8_t ip;  /* interrupt priority register */
-  
-  /* iir, eir registers are not full supported */
-  u8_t iir;
-  u8_t eir;
-  
-  /* see Rabbit Family of Microprocessors: Instruction Reference Manual */
-  /*   019-0098 * 090409-L */
-  
-
-public:
-  cl_r2k(struct cpu_entry *Itype, class cl_sim *asim);
-  virtual int init(void);
-  virtual char *id_string(void);
-  
-  //virtual t_addr get_mem_size(enum mem_class type);
-  virtual void mk_hw_elements(void);
-  virtual void make_memories(void);
-  
-  virtual struct dis_entry *dis_tbl(void);
-  virtual int inst_length(t_addr addr);
-  virtual int inst_branch(t_addr addr);
-  virtual int longest_inst(void);
-  virtual char *disass(t_addr addr, const char *sep);
-  virtual void print_regs(class cl_console_base *con);
-
-  virtual int exec_inst(void);
-  virtual int exec_code(t_mem code);
-  
-  virtual const char *get_disasm_info(t_addr addr,
-                        int *ret_len,
-                        int *ret_branch,
-                        int *immed_offset);
-  
-  
-  virtual void store1( u16_t addr, t_mem val );
-  virtual void store2( u16_t addr, u16_t val );
-  
-  virtual u8_t  get1( u16_t addr );
-  virtual u16_t  get2( u16_t addr );
-  
-  virtual t_mem       fetch1( void );
-  virtual u16_t  fetch2( void );
-  
-  virtual t_mem fetch(void);
-  virtual bool fetch(t_mem *code) {
-    return cl_uc::fetch(code);
-  }
-  
-  // see #include "instcl.h" for Z80 versions
-  /* instruction function that are add / modified from the Z80 versions */
-  virtual int inst_rst(t_mem code);
-  
-  virtual int inst_add_sp_d(t_mem code);
-  virtual int inst_altd(t_mem code);
-  
-  virtual int inst_bool   (t_mem code);
-  virtual int inst_r2k_ld (t_mem code);
-  virtual int inst_r2k_and(t_mem code);
-  virtual int inst_r2k_or (t_mem code);
-  virtual int inst_r2k_ex (t_mem code);
-  
-  virtual int inst_ljp(t_mem code);
-  virtual int inst_lcall(t_mem code);
-  virtual int inst_mul(t_mem code);
-  
-  virtual int inst_rl_de(t_mem code);
-  virtual int inst_rr_de(t_mem code);
-  virtual int inst_rr_hl(t_mem code);
-
-  virtual int inst_xd(t_mem prefix);
-  
-  //virtual int inst_ed(void);
-  virtual int inst_ed_(t_mem code);
-  
-};
-
-class cl_r3ka: public cl_r2k {
- public:
-  
-  u8_t  SU;
-  
-  cl_r3ka(struct cpu_entry *Itype, class cl_sim *asim);
-  virtual char *id_string(void);
-  
-  virtual int exec_code(t_mem code);
-  
-  virtual int inst_ed_(t_mem code);
-};
-
-#endif /* R2KCL_HEADER */
+/*
+ * Simulator of microcontrollers (z80cl.h)
+ *
+ * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
+ *
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef R2KCL_HEADER
+#define R2KCL_HEADER
+
+#include "z80cl.h"
+
+  /* TODO: maybe this should become an enum */
+#define IOI  1  // next instruction uses internal I/O space
+#define IOE  2  // next instruction uses external I/O space
+
+#define MMIDR 0x10   /* MMU Instruction/Data Register */
+#define SADR  0xC0   /* Serial A Data Register in IOI (internal I/O space) */
+
+
+class cl_r2k;
+
+class rabbit_mmu {
+public:
+  cl_r2k     *parent_p;
+  
+  /* Note: DEF_REGPAIR is defined in regsz80.h */
+  
+  u8_t  xpc;
+  u8_t  dataseg;
+  u8_t  stackseg;
+  u8_t  segsize;
+  
+  u8_t  io_flag; /* pseudo register for ioi/ioe prefixes */
+  
+  u8_t  mmidr;  /* MMU Instruction/Data Register __at 0x10 */
+  
+  rabbit_mmu( cl_r2k *parent_ip ):parent_p(parent_ip),
+    xpc(0), dataseg(0), stackseg(0), segsize(0xFF)
+    { }
+  
+  u32_t/*TYPE_UDWORD*/  logical_addr_to_phys( u16_t logical_addr );
+};
+
+
+class cl_r2k: public cl_z80
+{
+public:
+  // from cl_z80:
+  //class cl_memory *ram;
+  //class cl_memory *rom;
+  //struct t_regs regs;  
+  
+  rabbit_mmu   mmu;
+
+  u16_t ins_start;  /* PC value for start of the current instruction */
+  u8_t ip;  /* interrupt priority register */
+  
+  /* iir, eir registers are not full supported */
+  u8_t iir;
+  u8_t eir;
+  
+  /* see Rabbit Family of Microprocessors: Instruction Reference Manual */
+  /*   019-0098 * 090409-L */
+  
+
+public:
+  cl_r2k(struct cpu_entry *Itype, class cl_sim *asim);
+  virtual int init(void);
+  virtual const char *id_string(void);
+  
+  //virtual t_addr get_mem_size(enum mem_class type);
+  virtual void mk_hw_elements(void);
+  virtual void make_memories(void);
+  
+  virtual struct dis_entry *dis_tbl(void);
+  virtual int inst_length(t_addr addr);
+  virtual int inst_branch(t_addr addr);
+  virtual int longest_inst(void);
+  virtual char *disass(t_addr addr);
+
+  virtual void save_hist();
+  virtual void print_regs(class cl_console_base *con);
+
+  virtual int exec_inst(void);
+  virtual int exec_code(t_mem code);
+  
+  virtual const char *get_disasm_info(t_addr addr,
+                        int *ret_len,
+                        int *ret_branch,
+                        int *immed_offset);
+  
+  
+  virtual void store1( u16_t addr, t_mem val );
+  virtual void store2( u16_t addr, u16_t val );
+  
+  virtual u8_t  get1( u16_t addr );
+  virtual u16_t  get2( u16_t addr );
+  
+  virtual t_mem       fetch1( void );
+  virtual u16_t  fetch2( void );
+  
+  virtual t_mem fetch(void);
+  virtual bool fetch(t_mem *code) {
+    return cl_uc::fetch(code);
+  }
+  
+  // see #include "instcl.h" for Z80 versions
+  /* instruction function that are add / modified from the Z80 versions */
+  virtual int inst_rst(t_mem code);
+  
+  virtual int inst_add_sp_d(t_mem code);
+  virtual int inst_altd(t_mem code);
+  
+  virtual int inst_bool   (t_mem code);
+  virtual int inst_r2k_ld (t_mem code);
+  virtual int inst_r2k_and(t_mem code);
+  virtual int inst_r2k_or (t_mem code);
+  virtual int inst_r2k_ex (t_mem code);
+  
+  virtual int inst_ljp(t_mem code);
+  virtual int inst_lcall(t_mem code);
+  virtual int inst_lret(t_mem code);
+  virtual int inst_mul(t_mem code);
+  
+  virtual int inst_rl_de(t_mem code);
+  virtual int inst_rr_de(t_mem code);
+  virtual int inst_rr_hl(t_mem code);
+
+  virtual int inst_xd(t_mem prefix);
+  
+  //virtual int inst_ed(void);
+  virtual int inst_ed_(t_mem code);
+  
+};
+
+class cl_r3ka: public cl_r2k {
+ public:
+  
+  u8_t  SU;
+  
+  cl_r3ka(struct cpu_entry *Itype, class cl_sim *asim);
+  virtual const char *id_string(void);
+  
+  virtual int exec_code(t_mem code);
+  
+  virtual int inst_ed_(t_mem code);
+};
+
+#endif /* R2KCL_HEADER */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/z80.src/regsz80.h sdcc-4.2.0+dfsg/sim/ucsim/z80.src/regsz80.h
--- sdcc-4.0.0+dfsg/sim/ucsim/z80.src/regsz80.h	2017-03-02 10:01:56.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/z80.src/regsz80.h	2021-03-20 16:44:50.000000000 +0000
@@ -76,6 +76,7 @@
      that swap one for the other */
   //TYPE_UBYTE aA;
   //TYPE_UBYTE aF;
+
   union {
     u16_t aAF;
     struct {
@@ -93,8 +94,10 @@
   DEF_REGPAIR(aHL, a_hl);
   
   u8_t/*TYPE_UBYTE*/ iv;  /* interrupt vector, see ed 47 ld A,IV.. */
+  u8_t R;
 };
 
+/*
 enum {
   BIT_C=	0x01,  // carry status(out of bit 7)
   BIT_N=	0x02,  // Not addition: subtract status(1 after subtract).
@@ -104,6 +107,7 @@
   BIT_S=	0x80,  // sign status(value of bit 7)
   BIT_ALL=	(BIT_C |BIT_N |BIT_P |BIT_A |BIT_Z |BIT_S)  // all bits
 };
+*/
 
 enum {
   BITPOS_C= 0,    // 1
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/z80.src/simz80.cc sdcc-4.2.0+dfsg/sim/ucsim/z80.src/simz80.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/z80.src/simz80.cc	2018-12-05 13:58:20.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/z80.src/simz80.cc	2021-10-29 17:39:15.000000000 +0000
@@ -25,12 +25,16 @@
 02111-1307, USA. */
 /*@1@*/
 
+#include 
+#include 
+
 #include "globals.h"
 
 // local
 #include "simz80cl.h"
-#include "z80cl.h"
+//#include "z80cl.h"
 #include "r2kcl.h"
+#include "gb80cl.h"
 #include "lr35902cl.h"
 #include "ez80cl.h"
 
@@ -42,13 +46,13 @@
 cl_simz80::mk_controller(void)
 {
   int i;
-  const char *typ= NIL;
+  const char *typ= NULL;
   class cl_optref type_option(this);
 
   type_option.init();
   type_option.use("cpu_type");
   i= 0;
-  if ((typ= type_option.get_value(typ)) == NIL)
+  if ((typ= type_option.get_value(typ)) == NULL)
     typ= "Z80";
 
   while ((cpus_z80[i].type_str != NULL) &&
@@ -65,6 +69,7 @@
     {
     case CPU_Z80:
     case CPU_Z180:
+    case CPU_Z80N:
       return(new cl_z80(&cpus_z80[i], this));
     // Add Rabbits, etc here.
 
@@ -76,6 +81,8 @@
       
     case CPU_LR35902:
       return(new cl_lr35902(&cpus_z80[i], this));
+    case CPU_GB80:
+      return(new cl_gb80(&cpus_z80[i], this));
 
     case CPU_EZ80:
       return(new cl_ez80(&cpus_z80[i], this));
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/z80.src/sz80.cc sdcc-4.2.0+dfsg/sim/ucsim/z80.src/sz80.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/z80.src/sz80.cc	2017-01-06 07:36:33.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/z80.src/sz80.cc	2020-06-13 16:30:36.000000000 +0000
@@ -29,7 +29,7 @@
 #include "globals.h"
 
 // sim.src
-#include "appcl.h"
+//#include "appcl.h"
 
 // local
 #include "simz80cl.h"
@@ -42,6 +42,7 @@
 
   cpus= cpus_z80;
   application= new cl_app();
+  application->set_name("sz80");
   application->init(argc, argv);
   sim= new cl_simz80(application);
   if (sim->init())
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/z80.src/test/clean.mk sdcc-4.2.0+dfsg/sim/ucsim/z80.src/test/clean.mk
--- sdcc-4.0.0+dfsg/sim/ucsim/z80.src/test/clean.mk	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/z80.src/test/clean.mk	2021-04-01 17:52:48.000000000 +0000
@@ -0,0 +1,5 @@
+clean:
+
+distclean:
+	rm -f Makefile
+	find . -type d -name out -exec rm -rf {} \;
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/z80.src/test/conf.cmd sdcc-4.2.0+dfsg/sim/ucsim/z80.src/test/conf.cmd
--- sdcc-4.0.0+dfsg/sim/ucsim/z80.src/test/conf.cmd	2016-07-26 21:10:26.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/z80.src/test/conf.cmd	1970-01-01 00:00:00.000000000 +0000
@@ -1 +0,0 @@
-set hw simif nas 0xffff
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/z80.src/test/config/baseline/EZ80 sdcc-4.2.0+dfsg/sim/ucsim/z80.src/test/config/baseline/EZ80
--- sdcc-4.0.0+dfsg/sim/ucsim/z80.src/test/config/baseline/EZ80	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/z80.src/test/config/baseline/EZ80	2022-02-08 21:21:05.000000000 +0000
@@ -0,0 +1,33 @@
+uCsim, Copyright (C)  Daniel Drotos.
+uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+This is free software, and you are welcome to redistribute it
+under certain conditions; type `show c' for details.
+Type of microcontroller: EZ80
+Controller has 4 hardware element(s).
+   on cpu[0]
+   on simif[0]
+  off vcd[0]
+   on dreg[0]
+SZ-A-PNC  Flags= 0x00   0 .  A= 0x00   0 .
+00-0-000
+BC= 0x0000 [BC]= 08   8 .  DE= 0x0000 [DE]= 08   8 .  HL= 0x0000 [HL]= 08   8 .
+IX= 0x0000 [IX]= 08   8 .  IY= 0x0000 [IY]= 08   8 .  SP= 0x0000 [SP]= 08   8 .
+SP limit= 0xf000
+0x0000  ? 08          EX     AF,AF'[0K
+Memory chips:
+  0x000000-0x0000ff      256 variable_storage (32,%08x,0x%02lx)
+  0x000000-0x00ffff    65536 rom_chip (8,%02x,0x%04lx)
+  0x000000-0x00ffff    65536 in_chip (8,%02x,0x%04lx)
+  0x000000-0x00ffff    65536 out_chip (8,%02x,0x%04lx)
+Address spaces:
+  0x000000-0x0000ff      256 variables (32,%08x,0x%02lx)
+  0x000000-0x00ffff    65536 rom (8,%02x,0x%04lx)
+  0x000000-0x00ffff    65536 inputs (8,%02x,0x%04lx)
+  0x000000-0x00ffff    65536 outputs (8,%02x,0x%04lx)
+  0x000000-0x00000f       16 regs8 (8,%02x,0x%01lx)
+  0x000000-0x00000a       11 regs16 (16,%04x,0x%01lx)
+Address decoders:
+  variables 0x00 0xff -> variable_storage 0x00 activated
+  rom 0x0000 0xffff -> rom_chip 0x0000 activated
+  inputs 0x0000 0xffff -> in_chip 0x0000 inactive
+  outputs 0x0000 0xffff -> out_chip 0x0000 inactive
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/z80.src/test/config/baseline/GB80 sdcc-4.2.0+dfsg/sim/ucsim/z80.src/test/config/baseline/GB80
--- sdcc-4.0.0+dfsg/sim/ucsim/z80.src/test/config/baseline/GB80	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/z80.src/test/config/baseline/GB80	2022-02-08 21:21:05.000000000 +0000
@@ -0,0 +1,24 @@
+uCsim, Copyright (C)  Daniel Drotos.
+uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+This is free software, and you are welcome to redistribute it
+under certain conditions; type `show c' for details.
+Type of microcontroller: GB80
+Controller has 3 hardware element(s).
+   on cpu[0]
+   on simif[0]
+  off vcd[0]
+ZNHC---  Flags= 0x00   0 .  A= 0x00   0 .
+00000000
+BC= 0x0000 [BC]= 00   0 .  DE= 0x0000 [DE]= 00   0 .  HL= 0x0000 [HL]= 00   0 .
+SP= 0x0000 [SP]= 00   0 .
+0x0000  ? 00          NOP[0K
+Memory chips:
+  0x000000-0x0000ff      256 variable_storage (32,%08x,0x%02lx)
+Address spaces:
+  0x000000-0x0000ff      256 variables (32,%08x,0x%02lx)
+  0x000000-0x005fff    24576 rom (8,%02x,0x%04lx)
+  0x00a000-0x00ff7f    24448 xram (8,%02x,0x%04lx)
+  0x000000-0x00000f       16 regs8 (8,%02x,0x%01lx)
+  0x000000-0x00000a       11 regs16 (16,%04x,0x%01lx)
+Address decoders:
+  variables 0x00 0xff -> variable_storage 0x00 activated
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/z80.src/test/config/baseline/LR35902 sdcc-4.2.0+dfsg/sim/ucsim/z80.src/test/config/baseline/LR35902
--- sdcc-4.0.0+dfsg/sim/ucsim/z80.src/test/config/baseline/LR35902	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/z80.src/test/config/baseline/LR35902	2022-02-08 21:21:05.000000000 +0000
@@ -0,0 +1,24 @@
+uCsim, Copyright (C)  Daniel Drotos.
+uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+This is free software, and you are welcome to redistribute it
+under certain conditions; type `show c' for details.
+Type of microcontroller: GB80
+Controller has 3 hardware element(s).
+   on cpu[0]
+   on simif[0]
+  off vcd[0]
+ZNHC---  Flags= 0x00   0 .  A= 0x00   0 .
+00000000
+BC= 0x0000 [BC]= 00   0 .  DE= 0x0000 [DE]= 00   0 .  HL= 0x0000 [HL]= 00   0 .
+SP= 0x0000 [SP]= 00   0 .
+0x0000  ? 00          NOP[0K
+Memory chips:
+  0x000000-0x0000ff      256 variable_storage (32,%08x,0x%02lx)
+Address spaces:
+  0x000000-0x0000ff      256 variables (32,%08x,0x%02lx)
+  0x000000-0x005fff    24576 rom (8,%02x,0x%04lx)
+  0x00a000-0x00ff7f    24448 xram (8,%02x,0x%04lx)
+  0x000000-0x00000f       16 regs8 (8,%02x,0x%01lx)
+  0x000000-0x00000a       11 regs16 (16,%04x,0x%01lx)
+Address decoders:
+  variables 0x00 0xff -> variable_storage 0x00 activated
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/z80.src/test/config/baseline/R2K sdcc-4.2.0+dfsg/sim/ucsim/z80.src/test/config/baseline/R2K
--- sdcc-4.0.0+dfsg/sim/ucsim/z80.src/test/config/baseline/R2K	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/z80.src/test/config/baseline/R2K	2022-02-08 21:21:05.000000000 +0000
@@ -0,0 +1,26 @@
+uCsim, Copyright (C)  Daniel Drotos.
+uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+This is free software, and you are welcome to redistribute it
+under certain conditions; type `show c' for details.
+Type of microcontroller: rabbit 2000
+Controller has 4 hardware element(s).
+   on cpu[0]
+   on simif[0]
+  off vcd[0]
+   on cpu[0]
+SZ-A-PNC  Flags= 0x00   0 .  A= 0x00   0 .
+00-x-0x0
+BC= 0x0000 [BC]= 08   8 .  DE= 0x0000 [DE]= 08   8 .  HL= 0x0000 [HL]= 08   8 .
+IX= 0x0000 [IX]= 08   8 .  IY= 0x0000 [IY]= 08   8 .  SP= 0x0000 [SP]= 08   8 .
+0x00000  ? 08          EX     AF,AF'[0K
+Memory chips:
+  0x000000-0x0000ff      256 variable_storage (32,%08x,0x%02lx)
+  0x000000-0x0fffff  1048576 rom_chip (8,%02x,0x%05lx)
+Address spaces:
+  0x000000-0x0000ff      256 variables (32,%08x,0x%02lx)
+  0x000000-0x0fffff  1048576 rom (8,%02x,0x%05lx)
+  0x000000-0x000011       18 regs8 (8,%02x,0x%02lx)
+  0x000000-0x00000a       11 regs16 (16,%04x,0x%01lx)
+Address decoders:
+  variables 0x00 0xff -> variable_storage 0x00 activated
+  rom 0x00000 0xfffff -> rom_chip 0x00000 activated
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/z80.src/test/config/baseline/R3KA sdcc-4.2.0+dfsg/sim/ucsim/z80.src/test/config/baseline/R3KA
--- sdcc-4.0.0+dfsg/sim/ucsim/z80.src/test/config/baseline/R3KA	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/z80.src/test/config/baseline/R3KA	2022-02-08 21:21:05.000000000 +0000
@@ -0,0 +1,26 @@
+uCsim, Copyright (C)  Daniel Drotos.
+uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+This is free software, and you are welcome to redistribute it
+under certain conditions; type `show c' for details.
+Type of microcontroller: rabbit 3000A
+Controller has 4 hardware element(s).
+   on cpu[0]
+   on simif[0]
+  off vcd[0]
+   on cpu[0]
+SZ-A-PNC  Flags= 0x00   0 .  A= 0x00   0 .
+00-x-0x0
+BC= 0x0000 [BC]= 08   8 .  DE= 0x0000 [DE]= 08   8 .  HL= 0x0000 [HL]= 08   8 .
+IX= 0x0000 [IX]= 08   8 .  IY= 0x0000 [IY]= 08   8 .  SP= 0x0000 [SP]= 08   8 .
+0x00000  ? 08          EX     AF,AF'[0K
+Memory chips:
+  0x000000-0x0000ff      256 variable_storage (32,%08x,0x%02lx)
+  0x000000-0x0fffff  1048576 rom_chip (8,%02x,0x%05lx)
+Address spaces:
+  0x000000-0x0000ff      256 variables (32,%08x,0x%02lx)
+  0x000000-0x0fffff  1048576 rom (8,%02x,0x%05lx)
+  0x000000-0x000011       18 regs8 (8,%02x,0x%02lx)
+  0x000000-0x00000a       11 regs16 (16,%04x,0x%01lx)
+Address decoders:
+  variables 0x00 0xff -> variable_storage 0x00 activated
+  rom 0x00000 0xfffff -> rom_chip 0x00000 activated
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/z80.src/test/config/baseline/Z180 sdcc-4.2.0+dfsg/sim/ucsim/z80.src/test/config/baseline/Z180
--- sdcc-4.0.0+dfsg/sim/ucsim/z80.src/test/config/baseline/Z180	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/z80.src/test/config/baseline/Z180	2022-02-08 21:21:05.000000000 +0000
@@ -0,0 +1,33 @@
+uCsim, Copyright (C)  Daniel Drotos.
+uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+This is free software, and you are welcome to redistribute it
+under certain conditions; type `show c' for details.
+Type of microcontroller: Z180
+Controller has 4 hardware element(s).
+   on cpu[0]
+   on simif[0]
+  off vcd[0]
+   on dreg[0]
+SZ-A-PNC  Flags= 0x00   0 .  A= 0x00   0 .
+00-0-000
+BC= 0x0000 [BC]= 08   8 .  DE= 0x0000 [DE]= 08   8 .  HL= 0x0000 [HL]= 08   8 .
+IX= 0x0000 [IX]= 08   8 .  IY= 0x0000 [IY]= 08   8 .  SP= 0x0000 [SP]= 08   8 .
+SP limit= 0xf000
+0x0000  ? 08          EX     AF,AF'[0K
+Memory chips:
+  0x000000-0x0000ff      256 variable_storage (32,%08x,0x%02lx)
+  0x000000-0x00ffff    65536 rom_chip (8,%02x,0x%04lx)
+  0x000000-0x00ffff    65536 in_chip (8,%02x,0x%04lx)
+  0x000000-0x00ffff    65536 out_chip (8,%02x,0x%04lx)
+Address spaces:
+  0x000000-0x0000ff      256 variables (32,%08x,0x%02lx)
+  0x000000-0x00ffff    65536 rom (8,%02x,0x%04lx)
+  0x000000-0x00ffff    65536 inputs (8,%02x,0x%04lx)
+  0x000000-0x00ffff    65536 outputs (8,%02x,0x%04lx)
+  0x000000-0x00000f       16 regs8 (8,%02x,0x%01lx)
+  0x000000-0x00000a       11 regs16 (16,%04x,0x%01lx)
+Address decoders:
+  variables 0x00 0xff -> variable_storage 0x00 activated
+  rom 0x0000 0xffff -> rom_chip 0x0000 activated
+  inputs 0x0000 0xffff -> in_chip 0x0000 inactive
+  outputs 0x0000 0xffff -> out_chip 0x0000 inactive
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/z80.src/test/config/baseline/Z80 sdcc-4.2.0+dfsg/sim/ucsim/z80.src/test/config/baseline/Z80
--- sdcc-4.0.0+dfsg/sim/ucsim/z80.src/test/config/baseline/Z80	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/z80.src/test/config/baseline/Z80	2022-02-08 21:21:05.000000000 +0000
@@ -0,0 +1,33 @@
+uCsim, Copyright (C)  Daniel Drotos.
+uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+This is free software, and you are welcome to redistribute it
+under certain conditions; type `show c' for details.
+Type of microcontroller: Z80
+Controller has 4 hardware element(s).
+   on cpu[0]
+   on simif[0]
+  off vcd[0]
+   on dreg[0]
+SZ-A-PNC  Flags= 0x00   0 .  A= 0x00   0 .
+00-0-000
+BC= 0x0000 [BC]= 08   8 .  DE= 0x0000 [DE]= 08   8 .  HL= 0x0000 [HL]= 08   8 .
+IX= 0x0000 [IX]= 08   8 .  IY= 0x0000 [IY]= 08   8 .  SP= 0x0000 [SP]= 08   8 .
+SP limit= 0xf000
+0x0000  ? 08          EX     AF,AF'[0K
+Memory chips:
+  0x000000-0x0000ff      256 variable_storage (32,%08x,0x%02lx)
+  0x000000-0x00ffff    65536 rom_chip (8,%02x,0x%04lx)
+  0x000000-0x00ffff    65536 in_chip (8,%02x,0x%04lx)
+  0x000000-0x00ffff    65536 out_chip (8,%02x,0x%04lx)
+Address spaces:
+  0x000000-0x0000ff      256 variables (32,%08x,0x%02lx)
+  0x000000-0x00ffff    65536 rom (8,%02x,0x%04lx)
+  0x000000-0x00ffff    65536 inputs (8,%02x,0x%04lx)
+  0x000000-0x00ffff    65536 outputs (8,%02x,0x%04lx)
+  0x000000-0x00000f       16 regs8 (8,%02x,0x%01lx)
+  0x000000-0x00000a       11 regs16 (16,%04x,0x%01lx)
+Address decoders:
+  variables 0x00 0xff -> variable_storage 0x00 activated
+  rom 0x0000 0xffff -> rom_chip 0x0000 activated
+  inputs 0x0000 0xffff -> in_chip 0x0000 inactive
+  outputs 0x0000 0xffff -> out_chip 0x0000 inactive
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/z80.src/test/config/baseline/Z80N sdcc-4.2.0+dfsg/sim/ucsim/z80.src/test/config/baseline/Z80N
--- sdcc-4.0.0+dfsg/sim/ucsim/z80.src/test/config/baseline/Z80N	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/z80.src/test/config/baseline/Z80N	2022-02-08 21:21:05.000000000 +0000
@@ -0,0 +1,33 @@
+uCsim, Copyright (C)  Daniel Drotos.
+uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+This is free software, and you are welcome to redistribute it
+under certain conditions; type `show c' for details.
+Type of microcontroller: Z80N
+Controller has 4 hardware element(s).
+   on cpu[0]
+   on simif[0]
+  off vcd[0]
+   on dreg[0]
+SZ-A-PNC  Flags= 0x00   0 .  A= 0x00   0 .
+00-0-000
+BC= 0x0000 [BC]= 08   8 .  DE= 0x0000 [DE]= 08   8 .  HL= 0x0000 [HL]= 08   8 .
+IX= 0x0000 [IX]= 08   8 .  IY= 0x0000 [IY]= 08   8 .  SP= 0x0000 [SP]= 08   8 .
+SP limit= 0xf000
+0x0000  ? 08          EX     AF,AF'[0K
+Memory chips:
+  0x000000-0x0000ff      256 variable_storage (32,%08x,0x%02lx)
+  0x000000-0x00ffff    65536 rom_chip (8,%02x,0x%04lx)
+  0x000000-0x00ffff    65536 in_chip (8,%02x,0x%04lx)
+  0x000000-0x00ffff    65536 out_chip (8,%02x,0x%04lx)
+Address spaces:
+  0x000000-0x0000ff      256 variables (32,%08x,0x%02lx)
+  0x000000-0x00ffff    65536 rom (8,%02x,0x%04lx)
+  0x000000-0x00ffff    65536 inputs (8,%02x,0x%04lx)
+  0x000000-0x00ffff    65536 outputs (8,%02x,0x%04lx)
+  0x000000-0x00000f       16 regs8 (8,%02x,0x%01lx)
+  0x000000-0x00000a       11 regs16 (16,%04x,0x%01lx)
+Address decoders:
+  variables 0x00 0xff -> variable_storage 0x00 activated
+  rom 0x0000 0xffff -> rom_chip 0x0000 activated
+  inputs 0x0000 0xffff -> in_chip 0x0000 inactive
+  outputs 0x0000 0xffff -> out_chip 0x0000 inactive
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/z80.src/test/config/Makefile sdcc-4.2.0+dfsg/sim/ucsim/z80.src/test/config/Makefile
--- sdcc-4.0.0+dfsg/sim/ucsim/z80.src/test/config/Makefile	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/z80.src/test/config/Makefile	2021-03-21 12:01:19.000000000 +0000
@@ -0,0 +1,8 @@
+OUTPUTS = $(filter-out Parameter, $(shell $(SIM) -H | cut -d' ' -f1))
+
+
+$(OUTPUTS):
+	$(call run-sim, -t $(@F) -e 'conf; info reg; info mem')
+
+
+include test-lib.mk
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/z80.src/test/Makefile sdcc-4.2.0+dfsg/sim/ucsim/z80.src/test/Makefile
--- sdcc-4.0.0+dfsg/sim/ucsim/z80.src/test/Makefile	2016-07-26 21:10:26.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/z80.src/test/Makefile	1970-01-01 00:00:00.000000000 +0000
@@ -1,11 +0,0 @@
-PRJ		= t0 t1 t2
-
-all:
-	for p in $(PRJ); do \
-		$(MAKE) -f $$p.mk ;\
-	done
-
-clean:
-	for p in $(PRJ); do \
-		$(MAKE) -f $$p.mk clean ;\
-	done
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/z80.src/test/Makefile.in sdcc-4.2.0+dfsg/sim/ucsim/z80.src/test/Makefile.in
--- sdcc-4.0.0+dfsg/sim/ucsim/z80.src/test/Makefile.in	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/z80.src/test/Makefile.in	2021-03-28 10:28:14.000000000 +0000
@@ -0,0 +1,9 @@
+# @configure_input@
+
+srcdir           = @abs_srcdir@
+
+abs_top_builddir = @abs_top_builddir@
+abs_top_srcdir   = @abs_top_srcdir@
+
+
+include $(abs_top_srcdir)/test-target.mk
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/z80.src/test/run.cmd sdcc-4.2.0+dfsg/sim/ucsim/z80.src/test/run.cmd
--- sdcc-4.0.0+dfsg/sim/ucsim/z80.src/test/run.cmd	2016-07-26 21:10:26.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/z80.src/test/run.cmd	1970-01-01 00:00:00.000000000 +0000
@@ -1,2 +0,0 @@
-run
-state
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/z80.src/test/run.sh sdcc-4.2.0+dfsg/sim/ucsim/z80.src/test/run.sh
--- sdcc-4.0.0+dfsg/sim/ucsim/z80.src/test/run.sh	2016-12-12 13:18:23.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/z80.src/test/run.sh	1970-01-01 00:00:00.000000000 +0000
@@ -1,7 +0,0 @@
-PRJ=$1
-
-if [ -z "$PRJ" ]; then
-   PRJ=t1
-fi
-
-../sz80 -C conf.cmd ${PRJ}.ihx $(MAIN).dep
-	@for c in $(OBJECTS:.rel=.c); do \
-		$(CC) -MM $(CPPFALGS) $$c >>$(MAIN).dep ;\
-	done
-
-include $(MAIN).dep
-
-$(MAIN).ihx: $(OBJECTS)
-	$(CC) $(CFLAGS) $(LDFLAGS) $(OBJECTS) -o $@
-
-.SUFFIXES: .rel .ihx .hex
-
-.c.rel:
-	$(CC) -c $(CPPFLAGS) $(CFLAGS) $<
-
-.ihx.hex:
-	packihx $< >$@
-
-clean:
-	rm -f $(ALL:=.rel) $(ALL:=.asm) $(ALL:=.lst) $(ALL:=.rst) $(ALL:=.sym) $(ALL:=.adb)
-	rm -f $(MAIN).ihx $(MAIN).hex $(MAIN).lk $(MAIN).map $(MAIN).mem $(MAIN).cdb $(MAIN).omf $(MAIN).noi
-	rm -f *~
-	rm -f $(MAIN).dep
-
-
-# End of sdcc.mk
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/z80.src/test/symdis/baseline/stdout sdcc-4.2.0+dfsg/sim/ucsim/z80.src/test/symdis/baseline/stdout
--- sdcc-4.0.0+dfsg/sim/ucsim/z80.src/test/symdis/baseline/stdout	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/z80.src/test/symdis/baseline/stdout	2022-02-08 21:21:05.000000000 +0000
@@ -0,0 +1,198 @@
+uCsim, Copyright (C)  Daniel Drotos.
+uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+This is free software, and you are welcome to redistribute it
+under certain conditions; type `show c' for details.
+var _main rom[0x020a]
+dc 0x0100 0x0210 
+0x0100  ? 31 00 00    LD     SP,0x0000[0K
+0x0103  ? cd 0c 02    CALL   0x020c[0K
+0x0106  ? cd 0a 02    CALL   0x020a[0K
+0x0109  ? c3 04 02    JP     0x0204[0K
+0x010c  ? ac          XOR    H[0K
+0x010d  ? 7a          LD     A,D[0K
+0x010e  ? a6          AND    (HL)[0K
+0x010f  ? f2 b4 a8    JP     P,0xa8b4[0K
+0x0112  ? ca 99 b2    JP     Z,0xb299[0K
+0x0115  ? c2 37 2a    JP     NZ, 0x2a37[0K
+0x0118  ? cb 08       RRC    B[0K
+0x011a  ? cf          RST    8[0K
+0x011b  ? 61          LD     H,C[0K
+0x011c  ? c9          RET[0K
+0x011d  ? c3 80 5e    JP     0x5e80[0K
+0x0120  ? 6e          LD     L,(HL)[0K
+0x0121  ? 03          INC    BC[0K
+0x0122  ? 28 da       JR     Z,-38[0K
+0x0124  ? 4c          LD     C,H[0K
+0x0125  ? d7          RST    10H[0K
+0x0126  ? 6a          LD     L,D[0K
+0x0127  ? 19 ed d2    ADD    HL,DE[0K
+0x012a  ? d3 99       OUT    (0x99),A[0K
+0x012c  ? 4c          LD     C,H[0K
+0x012d  ? 79          LD     A,C[0K
+0x012e  ? 8b          ADC    A,E[0K
+0x012f  ? 00          NOP[0K
+0x0130  ? 22 56 9a    LD     (0x9a56),HL[0K
+0x0133  ? d4 18 d1    CALL   NC,0xd118[0K
+0x0136  ? fe e4       CP     0xe4[0K
+0x0138  ? d9          EXX[0K
+0x0139  ? cd 45 a3    CALL   0xa345[0K
+0x013c  ? 91          SUB    A,C[0K
+0x013d  ? c6 01       ADD    A,0x01[0K
+0x013f  ? ff          RST    38H[0K
+0x0140  ? c9          RET[0K
+0x0141  ? 2a d9 15    LD     HL,(0x15d9)[0K
+0x0144  ? 01 43 2f    LD     BC,0x2f43[0K
+0x0147  ? ee 15       XOR    0x15[0K
+0x0149  ? 02          LD     (BC),A[0K
+0x014a  ? 87          ADD    A,A[0K
+0x014b  ? 61          LD     H,C[0K
+0x014c  ? 7c          LD     A,H[0K
+0x014d  ? 13          INC    DE[0K
+0x014e  ? 62          LD     H,D[0K
+0x014f  ? 9e          SBC    A,(HL)[0K
+0x0150  ? 69          LD     L,C[0K
+0x0151  ? fc 72 81    CALL   M,0x8172[0K
+0x0154  ? cd 71 65    CALL   0x6571[0K
+0x0157  ? a6          AND    (HL)[0K
+0x0158  ? 3e ab       LD     A,0xab[0K
+0x015a  ? 49          LD     C,C[0K
+0x015b  ? cf          RST    8[0K
+0x015c  ? 71          LD     (HL),C[0K
+0x015d  ? 4b          LD     C,E[0K
+0x015e  ? ce 3a       ADC    A,0x3a[0K
+0x0160  ? 75          LD     (HL),L[0K
+0x0161  ? a7          AND    A[0K
+0x0162  ? 4f          LD     C,A[0K
+0x0163  ? 76          HALT[0K
+0x0164  ? ea 7e 64    JP     PE,0x647e[0K
+0x0167  ? ff          RST    38H[0K
+0x0168  ? 81          ADD    A,C[0K
+0x0169  ? eb          EX     DE,HL[0K
+0x016a  ? 61          LD     H,C[0K
+0x016b  ? fd          UNKNOWN/INVALID[0K
+0x016c  ? fe c3       CP     0xc3[0K
+0x016e  ? 9b          SBC    A,E[0K
+0x016f  ? 67          LD     H,A[0K
+0x0170  ? bf          CP     A[0K
+0x0171  ? 0d          DEC    C[0K
+0x0172  ? e9          JP     (HL)[0K
+0x0173  ? 8c          ADC    A,H[0K
+0x0174  ? 7e          LD     A,(HL)[0K
+0x0175  ? 4e          LD     C,(HL)[0K
+0x0176  ? 32 bd f9    LD     (0xf9bd),A[0K
+0x0179  ? 7c          LD     A,H[0K
+0x017a  ? 8c          ADC    A,H[0K
+0x017b  ? 6a          LD     L,D[0K
+0x017c  ? c7          RST    0[0K
+0x017d  ? 5b          LD     E,E[0K
+0x017e  ? a4          AND    H[0K
+0x017f  ? 3c          INC    A[0K
+0x0180  ? 02          LD     (BC),A[0K
+0x0181  ? f4 b2 ed    CALL   P,0xedb2[0K
+0x0184  ? 72          LD     (HL),D[0K
+0x0185  ? 16 ec       LD     D,0xec[0K
+0x0187  ? f3          DI[0K
+0x0188  ? 01 4d f0    LD     BC,0xf04d[0K
+0x018b  ? 00          NOP[0K
+0x018c  ? 10 8b       DJNZ   -117[0K
+0x018e  ? 67          LD     H,A[0K
+0x018f  ? cf          RST    8[0K
+0x0190  ? 99          SBC    A,C[0K
+0x0191  ? 50          LD     D,B[0K
+0x0192  ? 5b          LD     E,E[0K
+0x0193  ? 17          RLA[0K
+0x0194  ? 9f          SBC    A,A[0K
+0x0195  ? 8e          ADC    A,(HL)[0K
+0x0196  ? d4 98 0a    CALL   NC,0x0a98[0K
+0x0199  ? 61          LD     H,C[0K
+0x019a  ? 03          INC    BC[0K
+0x019b  ? d1          POP    DE[0K
+0x019c  ? bc          CP     H[0K
+0x019d  ? a7          AND    A[0K
+0x019e  ? 0d          DEC    C[0K
+0x019f  ? be          CP     (HL)[0K
+0x01a0  ? 9b          SBC    A,E[0K
+0x01a1  ? bf          CP     A[0K
+0x01a2  ? ab          XOR    E[0K
+0x01a3  ? 0e d5       LD     C,0xd5[0K
+0x01a5  ? 98          SBC    A,B[0K
+0x01a6  ? 01 d6 e5    LD     BC,0xe5d6[0K
+0x01a9  ? f2 d6 f6    JP     P,0xf6d6[0K
+0x01ac  ? 7d          LD     A,L[0K
+0x01ad  ? 3e c5       LD     A,0xc5[0K
+0x01af  ? 16 8e       LD     D,0x8e[0K
+0x01b1  ? 21 2e 2d    LD     HL,0x2d2e[0K
+0x01b4  ? af          XOR    A[0K
+0x01b5  ? 02          LD     (BC),A[0K
+0x01b6  ? c6 b9       ADD    A,0xb9[0K
+0x01b8  ? 63          LD     H,E[0K
+0x01b9  ? c9          RET[0K
+0x01ba  ? 8a          ADC    A,D[0K
+0x01bb  ? 1f          RRA[0K
+0x01bc  ? 70          LD     (HL),B[0K
+0x01bd  ? 97          SUB    A,A[0K
+0x01be  ? de 0c       SBC    A,0x0c[0K
+0x01c0  ? 56          LD     D,(HL)[0K
+0x01c1  ? 89          ADC    A,C[0K
+0x01c2  ? 1a          LD     A,(DE)[0K
+0x01c3  ? 2b          DEC    HL[0K
+0x01c4  ? 21 1b 01    LD     HL,0x011b[0K
+0x01c7  ? 07          RLCA[0K
+0x01c8  ? 0d          DEC    C[0K
+0x01c9  ? d8          RET    C[0K
+0x01ca  ? fd          UNKNOWN/INVALID[0K
+0x01cb  ? 8b          ADC    A,E[0K
+0x01cc  ? 16 c2       LD     D,0xc2[0K
+0x01ce  ? a1          AND    C[0K
+0x01cf  ? a4          AND    H[0K
+0x01d0  ? e3          EX     (SP),HL[0K
+0x01d1  ? cf          RST    8[0K
+0x01d2  ? d2 92 d2    JP     NC,0xd292[0K
+0x01d5  ? 98          SBC    A,B[0K
+0x01d6  ? 4b          LD     C,E[0K
+0x01d7  ? 35          DEC    (HL)[0K
+0x01d8  ? 61          LD     H,C[0K
+0x01d9  ? d5          PUSH   DE[0K
+0x01da  ? 55          LD     D,L[0K
+0x01db  ? d1          POP    DE[0K
+0x01dc  ? 6c          LD     L,H[0K
+0x01dd  ? 33          INC    SP[0K
+0x01de  ? dd          UNKNOWN/INVALID[0K
+0x01df  ? c2 bc f7    JP     NZ, 0xf7bc[0K
+0x01e2  ? ed          UNKNOWN/INVALID[0K
+0x01e3  ? de 13       SBC    A,0x13[0K
+0x01e5  ? ef          RST    28H[0K
+0x01e6  ? e5          PUSH   HL[0K
+0x01e7  ? 20 c7       JR     NZ,-57[0K
+0x01e9  ? e2 ab dd    JP     PO,0xddab[0K
+0x01ec  ? a4          AND    H[0K
+0x01ed  ? 4d          LD     C,L[0K
+0x01ee  ? 81          ADD    A,C[0K
+0x01ef  ? 88          ADC    A,B[0K
+0x01f0  ? 1c          INC    E[0K
+0x01f1  ? 53          LD     D,E[0K
+0x01f2  ? 1a          LD     A,(DE)[0K
+0x01f3  ? ee eb       XOR    0xeb[0K
+0x01f5  ? 66          LD     H,(HL)[0K
+0x01f6  ? 24          INC    H[0K
+0x01f7  ? 4c          LD     C,H[0K
+0x01f8  ? 3b          DEC    SP[0K
+0x01f9  ? 79          LD     A,C[0K
+0x01fa  ? 1e a8       LD     E,0xa8[0K
+0x01fc  ? ac          XOR    H[0K
+0x01fd  ? fb          EI[0K
+0x01fe  ? 6a          LD     L,D[0K
+0x01ff  ? 68          LD     L,B[0K
+0x0200  ? 3e 02       LD     A,0x02[0K
+0x0202  ? cf          RST    8[0K
+0x0203  ? c9          RET[0K
+0x0204  ? 3e 00       LD     A,0x00[0K
+0x0206  ? cf          RST    8[0K
+0x0207  ? 76          HALT[0K
+0x0208  ? 18 fd       JR     -3[0K
+
+0x020a    <_main>:
+0x020a  ? 18 fe       JR     -2[0K
+0x020c  ? 01 00 00    LD     BC,0x0000[0K
+0x020f  ? 78          LD     A,B[0K
+0x0210  ? b1          OR     C[0K
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/z80.src/test/symdis/Makefile sdcc-4.2.0+dfsg/sim/ucsim/z80.src/test/symdis/Makefile
--- sdcc-4.0.0+dfsg/sim/ucsim/z80.src/test/symdis/Makefile	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/z80.src/test/symdis/Makefile	2021-05-07 16:21:16.000000000 +0000
@@ -0,0 +1,15 @@
+OUTPUTS = stdout
+
+
+# Ignore changes in white space. The field widths for labels
+# depends on the length of the longest label. This will be
+# different for different simulators and should not be assumed
+# to be constant for any given simulator.
+DIFF_OPTS += -b
+
+
+stdout:	test.ihx test.cmd
+	$(call run-sim, -t Z80)
+
+
+include test-lib.mk
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/z80.src/test/symdis/test.c sdcc-4.2.0+dfsg/sim/ucsim/z80.src/test/symdis/test.c
--- sdcc-4.0.0+dfsg/sim/ucsim/z80.src/test/symdis/test.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/z80.src/test/symdis/test.c	2021-05-07 16:21:16.000000000 +0000
@@ -0,0 +1,4 @@
+int main(int argc, char *argv[])
+{
+	for (;;);
+}
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/z80.src/test/symdis/test.cmd sdcc-4.2.0+dfsg/sim/ucsim/z80.src/test/symdis/test.cmd
--- sdcc-4.0.0+dfsg/sim/ucsim/z80.src/test/symdis/test.cmd	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/z80.src/test/symdis/test.cmd	2021-05-07 16:21:16.000000000 +0000
@@ -0,0 +1,2 @@
+var _main rom[0x020a]
+dc 0x0100 0x0210 
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/z80.src/test/symdis/test.ihx sdcc-4.2.0+dfsg/sim/ucsim/z80.src/test/symdis/test.ihx
--- sdcc-4.0.0+dfsg/sim/ucsim/z80.src/test/symdis/test.ihx	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/z80.src/test/symdis/test.ihx	2021-05-07 16:21:16.000000000 +0000
@@ -0,0 +1,13 @@
+:03000000C3000139
+:04000800FBED4DFBC4
+:03001000FBED4DB8
+:03001800FBED4DB0
+:03002000FBED4DA8
+:03002800FBED4DA0
+:03003000FBED4D98
+:03003800FBED4D90
+:0C010000310000CD0C02CD0A02C3040245
+:0A0200003E02CFC93E00CF7618FD84
+:10020C0001000078B12808110080210C02EDB0C962
+:02020A0018FEDC
+:00000001FF
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/z80.src/test/t0.c sdcc-4.2.0+dfsg/sim/ucsim/z80.src/test/t0.c
--- sdcc-4.0.0+dfsg/sim/ucsim/z80.src/test/t0.c	2016-07-26 21:10:26.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/z80.src/test/t0.c	1970-01-01 00:00:00.000000000 +0000
@@ -1,6 +0,0 @@
-void main(void)
-{
-  unsigned int i, j;
-  for (i=0; i<0x2233; i++)
-    j= i;
-}
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/z80.src/test/t0.mk sdcc-4.2.0+dfsg/sim/ucsim/z80.src/test/t0.mk
--- sdcc-4.0.0+dfsg/sim/ucsim/z80.src/test/t0.mk	2016-07-26 21:10:26.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/z80.src/test/t0.mk	1970-01-01 00:00:00.000000000 +0000
@@ -1,3 +0,0 @@
-MAIN		= t0
-
-include sdcc.mk
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/z80.src/test/t1.c sdcc-4.2.0+dfsg/sim/ucsim/z80.src/test/t1.c
--- sdcc-4.0.0+dfsg/sim/ucsim/z80.src/test/t1.c	2016-07-26 21:10:26.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/z80.src/test/t1.c	1970-01-01 00:00:00.000000000 +0000
@@ -1,37 +0,0 @@
-static unsigned char * volatile sif= (unsigned char *)0xffff;
-
-volatile unsigned char x;
-
-void
-putchar(unsigned char c)
-{
-  *sif= 'p';
-  *sif= c;
-}
-
-void
-prints(char *s)
-{
-  while (*s)
-    putchar(*s++);
-}
-
-void
-main(void)
-{
-  unsigned char i;
-  unsigned int j;
-
-  prints("Start.\n");
-  for (j= 0; j<41000; j++)
-    {
-      x= j;
-      i= j;
-      putchar('a');
-    }
-
-  prints("Done.\n");
-  *sif= 's';
-  for (;;)
-    ;
-}
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/z80.src/test/t1.mk sdcc-4.2.0+dfsg/sim/ucsim/z80.src/test/t1.mk
--- sdcc-4.0.0+dfsg/sim/ucsim/z80.src/test/t1.mk	2016-07-26 21:10:26.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/z80.src/test/t1.mk	1970-01-01 00:00:00.000000000 +0000
@@ -1,3 +0,0 @@
-MAIN		= t1
-
-include sdcc.mk
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/z80.src/test/t2.c sdcc-4.2.0+dfsg/sim/ucsim/z80.src/test/t2.c
--- sdcc-4.0.0+dfsg/sim/ucsim/z80.src/test/t2.c	2016-07-26 21:10:26.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/z80.src/test/t2.c	1970-01-01 00:00:00.000000000 +0000
@@ -1,36 +0,0 @@
-static unsigned char * volatile sif= (unsigned char *)0xffff;
-
-volatile unsigned char x;
-
-void
-putchar(unsigned char c)
-{
-  *sif= 'p';
-  *sif= c;
-}
-
-void
-prints(char *s)
-{
-  while (*s)
-    putchar(*s++);
-}
-
-void
-main(void)
-{
-  unsigned int i;
-  unsigned int j;
-
-  prints("Start.\n");
-  for (j= 0; j<200; j++)
-    {
-      for (i= 1000; i; i--)
-	putchar('a');
-    }
-
-  prints("Done.\n");
-  *sif= 's';
-  for (;;)
-    ;
-}
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/z80.src/test/t2.mk sdcc-4.2.0+dfsg/sim/ucsim/z80.src/test/t2.mk
--- sdcc-4.0.0+dfsg/sim/ucsim/z80.src/test/t2.mk	2016-07-26 21:10:26.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/z80.src/test/t2.mk	1970-01-01 00:00:00.000000000 +0000
@@ -1,3 +0,0 @@
-MAIN		= t2
-
-include sdcc.mk
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/z80.src/test/test-conf.mk sdcc-4.2.0+dfsg/sim/ucsim/z80.src/test/test-conf.mk
--- sdcc-4.0.0+dfsg/sim/ucsim/z80.src/test/test-conf.mk	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/z80.src/test/test-conf.mk	2021-03-21 12:01:19.000000000 +0000
@@ -0,0 +1,3 @@
+CC = sdcc -mz80
+AS = sdasz80
+LD = sdldz80
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/z80.src/z80.cc sdcc-4.2.0+dfsg/sim/ucsim/z80.src/z80.cc
--- sdcc-4.0.0+dfsg/sim/ucsim/z80.src/z80.cc	2019-05-06 09:55:43.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/z80.src/z80.cc	2021-07-16 14:31:13.000000000 +0000
@@ -27,24 +27,27 @@
 02111-1307, USA. */
 /*@1@*/
 
-#include "ddconfig.h"
+//#include "ddconfig.h"
 
-#include  /* for va_list */
+//#include  /* for va_list */
 #include 
 #include 
 #include 
-#include "i_string.h"
+#include 
 
 // prj
-#include "pobjcl.h"
+//#include "pobjcl.h"
+#include "globals.h"
 
 // sim
-#include "simcl.h"
+//#include "simcl.h"
+#include "dregcl.h"
 
 // local
 #include "z80cl.h"
 #include "glob.h"
-#include "regsz80.h"
+//#include "regsz80.h"
+#include "z80mac.h"
 
 #define uint32 t_addr
 #define uint8 unsigned char
@@ -60,6 +63,13 @@
   cl_uc(asim)
 {
   type= Itype;
+  BIT_C= 0x01;  // carry status(out of bit 7)
+  BIT_N= 0x02,  // Not addition: subtract status(1 after subtract).
+  BIT_P= 0x04,  // parity/overflow, 1=even, 0=odd parity.  arith:1=overflow
+  BIT_A= 0x10,  // aux carry status(out of bit 3)
+  BIT_Z= 0x40,  // zero status, 1=zero, 0=nonzero
+  BIT_S= 0x80,  // sign status(value of bit 7)
+  BIT_ALL= (BIT_C |BIT_N |BIT_P |BIT_A |BIT_Z |BIT_S);
 }
 
 int
@@ -76,14 +86,26 @@
   for (int i=0x8000; i<0x10000; i++) {
     ram->set((t_addr) i, 0);
   }
+  sp_limit= 0xf000;
+  
+  IFF1= false;
+  IFF2= false;
 
   return(0);
 }
 
-char *
+const char *
 cl_z80::id_string(void)
 {
-  return((char*)"unspecified Z80");
+  switch (type->type)
+    {
+    case CPU_Z80: return "Z80";
+    case CPU_Z180: return "Z180";
+    case CPU_Z80N: return "Z80N";
+    default:
+      return "unspecified Z80";
+    }
+  return "Z80";
 }
 
 
@@ -105,10 +127,21 @@
 */
 
 void
+cl_z80::make_cpu_hw(void)
+{
+  add_hw(cpu= new cl_z80_cpu(this));
+  cpu->init();
+}
+
+void
 cl_z80::mk_hw_elements(void)
 {
   //class cl_base *o;
+  class cl_hw *h;
   cl_uc::mk_hw_elements();
+
+  add_hw(h= new cl_dreg(this, 0, "dreg"));
+  h->init();
 }
 
 void
@@ -123,7 +156,7 @@
   class cl_address_decoder *ad;
   class cl_memory_chip *chip;
 
-  chip= new cl_memory_chip("rom_chip", 0x10000, 8);
+  chip= new cl_chip8("rom_chip", 0x10000, 8);
   chip->init();
   memchips->add(chip);
   ad= new cl_address_decoder(as= address_space("rom"), chip, 0, 0xffff, 0);
@@ -133,7 +166,7 @@
 
   inputs= new cl_address_space("inputs", 0, 0x10000, 8);
   inputs->init();
-  chip= new cl_memory_chip("in_chip", 0x10000, 8);
+  chip= new cl_chip8("in_chip", 0x10000, 8);
   chip->init();
   memchips->add(chip);
   ad= new cl_address_decoder(inputs, chip, 0, 0xffff, 0);
@@ -142,7 +175,7 @@
   address_spaces->add(inputs);
   outputs= new cl_address_space("outputs", 0, 0x10000, 8);
   outputs->init();
-  chip= new cl_memory_chip("out_chip", 0x10000, 8);
+  chip= new cl_chip8("out_chip", 0x10000, 8);
   chip->init();
   memchips->add(chip);
   ad= new cl_address_decoder(outputs, chip, 0, 0xffff, 0);
@@ -188,63 +221,47 @@
   address_spaces->add(regs8);
   address_spaces->add(regs16);
 
-  class cl_var *v;
-  vars->add(v= new cl_var(cchars("A"), regs8, 0, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("F"), regs8, 1, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("B"), regs8, 2, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("C"), regs8, 3, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("D"), regs8, 4, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("E"), regs8, 5, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("H"), regs8, 6, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("L"), regs8, 7, ""));
-  v->init();
-
-  vars->add(v= new cl_var(cchars("ALT_A"), regs8, 8, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("ALT_F"), regs8, 9, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("ALT_B"), regs8, 10, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("ALT_C"), regs8, 11, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("ALT_D"), regs8, 12, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("ALT_E"), regs8, 13, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("ALT_H"), regs8, 14, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("ALT_L"), regs8, 15, ""));
-  v->init();
-
-  vars->add(v= new cl_var(cchars("AF"), regs16, 0, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("BC"), regs16, 1, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("DE"), regs16, 2, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("HL"), regs16, 3, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("IX"), regs16, 4, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("IY"), regs16, 5, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("SP"), regs16, 6, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("ALT_AF"), regs16, 7, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("ALT_BC"), regs16, 8, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("ALT_DE"), regs16, 9, ""));
-  v->init();
-  vars->add(v= new cl_var(cchars("ALT_HL"), regs16, 10, ""));
-  v->init();
+  vars->add("A", regs8, 0, 7, 0, "Accumulator");
+  vars->add("F", regs8, 1, 7, 0, "Flags");
+  vars->add("F_C", regs8, 1, BITPOS_C, BITPOS_C, "Carry");
+  vars->add("F_SUB", regs8, 1, BITPOS_SUB, BITPOS_SUB, "");
+  vars->add("F_P", regs8, 1, BITPOS_P, BITPOS_P, "");
+  vars->add("F_A", regs8, 1, BITPOS_A, BITPOS_A, "");
+  vars->add("F_Z", regs8, 1, BITPOS_Z, BITPOS_Z, "Zero");
+  vars->add("F_S", regs8, 1, BITPOS_S, BITPOS_S, "");
+  vars->add("B", regs8, 2, 7, 0, "");
+  vars->add("C", regs8, 3, 7, 0, "");
+  vars->add("D", regs8, 4, 7, 0, "");
+  vars->add("E", regs8, 5, 7, 0, "");
+  vars->add("H", regs8, 6, 7, 0, "");
+  vars->add("L", regs8, 7, 7, 0, "");
+
+  vars->add("ALT_A", regs8, 8, 7, 0, "Alt Accumulator");
+  vars->add("ALT_F", regs8, 9, 7, 0, "Alt Flags");
+  vars->add("ALT_F_C", regs8, 9, BITPOS_C, BITPOS_C, "Carry");
+  vars->add("ALT_F_SUB", regs8, 9, BITPOS_SUB, BITPOS_SUB, "");
+  vars->add("ALT_F_P", regs8, 9, BITPOS_P, BITPOS_P, "");
+  vars->add("ALT_F_A", regs8, 9, BITPOS_A, BITPOS_A, "");
+  vars->add("ALT_F_Z", regs8, 9, BITPOS_Z, BITPOS_Z, "Zero");
+  vars->add("ALT_F_S", regs8, 9, BITPOS_S, BITPOS_S, "");
+  vars->add("ALT_B", regs8, 10, 7, 0, "");
+  vars->add("ALT_C", regs8, 11, 7, 0, "");
+  vars->add("ALT_D", regs8, 12, 7, 0, "");
+  vars->add("ALT_E", regs8, 13, 7, 0, "");
+  vars->add("ALT_H", regs8, 14, 7, 0, "");
+  vars->add("ALT_L", regs8, 15, 7, 0, "");
+
+  vars->add("AF", regs16, 0, 15, 0, "Accumulator/Flags");
+  vars->add("BC", regs16, 1, 15, 0, "");
+  vars->add("DE", regs16, 2, 15, 0, "");
+  vars->add("HL", regs16, 3, 15, 0, "");
+  vars->add("IX", regs16, 4, 15, 0, "");
+  vars->add("IY", regs16, 5, 15, 0, "");
+  vars->add("SP", regs16, 6, 15, 0, "");
+  vars->add("ALT_AF", regs16, 7, 15, 0, "Alt Accumulator/Flags");
+  vars->add("ALT_BC", regs16, 8, 15, 0, "");
+  vars->add("ALT_DE", regs16, 9, 15, 0, "");
+  vars->add("ALT_HL", regs16, 10, 15, 0, "");
 }
 
 
@@ -341,6 +358,19 @@
 
     case 0xed: /* ESC code to about 80 opcodes of various lengths */
       code= rom->get(addr++);
+      if (type->type == CPU_Z80N)
+	{
+	  i= 0;
+	  while ((code & disass_z80n_ed[i].mask) != disass_z80n_ed[i].code &&
+		 disass_z80n_ed[i].mnemonic)
+	    i++;
+	  b= disass_z80n_ed[i].mnemonic;
+	  if (b != NULL)
+	    {
+	      len += (disass_z80n_ed[i].length + 1);
+	      break;
+	    }
+	}
       i= 0;
       while ((code & disass_z80_ed[i].mask) != disass_z80_ed[i].code &&
         disass_z80_ed[i].mnemonic)
@@ -439,88 +469,76 @@
 }
 
 char *
-cl_z80::disass(t_addr addr, const char *sep)
+cl_z80::disass(t_addr addr)
 {
-  char work[256], temp[20];
+  chars work, temp;
   const char *b;
-  char *buf, *p, *t;
   int len = 0;
   int immed_offset = 0;
-
-  p= work;
+  bool first= true;
+  
+  work= "";
 
   b = get_disasm_info(addr, &len, NULL, &immed_offset, NULL);
 
-  if (b == NULL) {
-    buf= (char*)malloc(30);
-    strcpy(buf, "UNKNOWN/INVALID");
-    return(buf);
-  }
+  if (b == NULL)
+    {
+      return strdup("UNKNOWN/INVALID");
+    }
 
   while (*b)
     {
+      if ((*b == ' ') && first)
+	{
+	  first= false;
+	  while (work.len() < 6) work.append(' ');
+	}
       if (*b == '%')
         {
           b++;
+	  temp= "";
           switch (*(b++))
             {
-            case 'd': // d    jump relative target, signed? byte immediate operand
-              sprintf(temp, "#%d", (signed char)(rom->get(addr+immed_offset)));
+            case 'd': // jump relative target, signed? byte immediate operand
+              temp.format("%d", (signed char)(rom->get(addr+immed_offset)));
+              ++immed_offset;
+              break;
+            case 'w': // word immediate operand, little endian
+              temp.format("0x%04x",
+			  (uint)((rom->get(addr+immed_offset)) |
+				 (rom->get(addr+immed_offset+1)<<8)) );
+              ++immed_offset;
               ++immed_offset;
               break;
-            case 'w': // w    word immediate operand
-              sprintf(temp, "#0x%04x",
-                 (uint)((rom->get(addr+immed_offset)) |
-                        (rom->get(addr+immed_offset+1)<<8)) );
+            case 'W': // word immediate operand, big endian
+              temp.format("0x%04x",
+			  (uint)((rom->get(addr+immed_offset)<<8) |
+				 (rom->get(addr+immed_offset+1))) );
               ++immed_offset;
               ++immed_offset;
               break;
-            case 'b': // b    byte immediate operand
-              sprintf(temp, "#0x%02x", (uint)rom->get(addr+immed_offset));
+            case 'b': // byte immediate operand
+              temp.format("0x%02x", (uint)rom->get(addr+immed_offset));
               ++immed_offset;
               break;
             default:
-              strcpy(temp, "?");
+              temp= "?";
               break;
             }
-          t= temp;
-          while (*t)
-            *(p++)= *(t++);
+          work+= temp;
         }
       else
-        *(p++)= *(b++);
+        work+= *(b++);
     }
-  *p= '\0';
 
-  p= strchr(work, ' ');
-  if (!p)
-    {
-      buf= strdup(work);
-      return(buf);
-    }
-  if (sep == NULL)
-    buf= (char *)malloc(6+strlen(p)+1);
-  else
-    buf= (char *)malloc((p-work)+strlen(sep)+strlen(p)+1);
-  for (p= work, t= buf; *p != ' '; p++, t++)
-    *t= *p;
-  p++;
-  *t= '\0';
-  if (sep == NULL)
-    {
-      while (strlen(buf) < 6)
-        strcat(buf, " ");
-    }
-  else
-    strcat(buf, sep);
-  strcat(buf, p);
-  return(buf);
+  return strdup(work.c_str());
 }
 
 
 void
 cl_z80::print_regs(class cl_console_base *con)
 {
+  con->dd_color("answer");
   con->dd_printf("SZ-A-PNC  Flags= 0x%02x %3d %c  ",
                  regs.raf.F, regs.raf.F, isprint(regs.raf.F)?regs.raf.F:'.');
   con->dd_printf("A= 0x%02x %3d %c\n",
@@ -550,7 +568,8 @@
   con->dd_printf("SP= 0x%04x [SP]= %02x %3d %c\n",
                  regs.SP, ram->get(regs.SP), ram->get(regs.SP),
                  isprint(ram->get(regs.SP))?ram->get(regs.SP):'.');
-
+  con->dd_printf("SP limit= 0x%04x\n", AU(sp_limit));
+  
   print_disass(PC, con);
 }
 
@@ -562,12 +581,13 @@
 cl_z80::exec_inst(void)
 {
   t_mem code;
-
+  
   instPC= PC;
 
   if (fetch(&code))
     return(resBREAKPOINT);
   tick(1);
+
   switch (code)
     {
     case 0x00: return(inst_nop(code));
@@ -756,6 +776,206 @@
   return(resINV_INST);
 }
 
+bool cl_z80::inst_z80n(t_mem code, int *ret)
+{
+  int r= resGO;
+  switch (code)
+    {
+    case 0xa4: r= inst_ldix(code); break;
+    case 0xa5: // ldws
+      {
+	this->store1(regs.DE, this->get1(regs.HL));
+	vc.rd++;
+	vc.wr++;
+	inc(regs.hl.l);
+	inc(regs.de.h);
+	break;
+      }
+    case 0xb4: do r= inst_ldix(code); while (regs.BC); break;
+    case 0xac: r= inst_lddx(code); break;
+    case 0xbc: do r= inst_lddx(code); while (regs.BC); break;
+    case 0xb7:  // ldpirx
+      {
+	u8_t t;
+	do {
+	  t= this->get1((regs.HL & 0xfff8)+(regs.de.l & 7));
+	  vc.rd++;
+	  if (t != regs.raf.A)
+	    {
+	      this->store1(regs.DE, t);
+	      vc.wr++;
+	    }
+	  regs.DE++;
+	  regs.BC--;
+	}
+	while (regs.BC);
+	break;
+      }
+    case 0x90: // outinb
+      outputs->write(regs.BC, this->get1(regs.HL));
+      vc.wr++;
+      vc.rd++;
+      SET_Z(regs.bc.h);
+      regs.raf.F|= BIT_N;
+      regs.HL++;
+      break;
+    case 0x30: // mul
+      regs.DE= regs.de.h * regs.de.l;
+      break;
+    case 0x31: // add hl,a
+      regs.HL+= regs.raf.A;
+      break;
+    case 0x32: // add de,a
+      regs.DE+= regs.raf.A;
+      break;
+    case 0x33: // add bc,a
+      regs.BC+= regs.raf.A;
+      break;
+    case 0x34: // add hl,$nnnn
+      {
+	u16_t w= fetch2();
+	regs.HL+= w;
+	break;
+      }
+    case 0x35: // add de,$nnnn
+      {
+	u16_t w= fetch2();
+	regs.DE+= w;
+	break;
+      }
+
+    case 0x36: // add bc,$nnnn
+      {
+	u16_t w= fetch2();
+	regs.BC+= w;
+	break;
+      }
+    case 0x23: // swapnib
+      regs.raf.A= (regs.raf.A >> 4) | (regs.raf.A << 4);
+      break;
+    case 0x24: // mirror a
+      regs.raf.A=
+	((regs.raf.A&0x01)?0x80:0) |
+	((regs.raf.A&0x02)?0x40:0) |
+	((regs.raf.A&0x04)?0x20:0) |
+	((regs.raf.A&0x08)?0x10:0) |
+	((regs.raf.A&0x10)?0x08:0) |
+	((regs.raf.A&0x20)?0x04:0) |
+	((regs.raf.A&0x40)?0x02:0) |
+	((regs.raf.A&0x80)?0x01:0);
+      break;	
+    case 0x8a: // push $nnnn
+      {
+	u16_t w= fetch() * 256;
+	w+= fetch();
+	push2(w);
+	vc.wr+= 2;
+	break;
+      }
+    case 0x91: // nextreg $rr,$nn
+      outputs->write(0x243b, fetch());
+      outputs->write(0x253b, fetch());
+      vc.wr+= 2;
+      break;
+    case 0x92: // nextreg $rr,a
+      outputs->write(0x243b, fetch());
+      outputs->write(0x253b, regs.raf.A);
+      vc.wr+= 2;
+      break;
+    case 0x93: // pixeldn
+      if (regs.HL!=0x0700)
+	regs.HL+= 256;
+      else if ((regs.HL&0xe0)!=0xe0)
+	regs.HL= (regs.HL&0xf800)+0x20;
+      else
+	regs.HL= (regs.HL&0xf81f)+0x0800;
+      break;
+    case 0x94: // pixelad
+      regs.HL= 0x4000 + ((regs.de.h&0xc0)<<5) + ((regs.de.h&0x07)<<8) +
+	((regs.de.h&0x38)<<2) + (regs.de.l>>3);
+      break;
+    case 0x95: // setae
+      regs.raf.A= 0x80 >> (regs.de.l & 0x7);
+      break;
+    case 0x27: // test $nn
+      {
+	u8_t d= fetch();
+	d&= regs.raf.A;
+	regs.raf.F &= ~(BIT_ALL);
+	SET_Z(d);
+	SET_S(d);
+	if (parity(d))
+	  regs.raf.F|= BIT_P;
+	break;
+      }
+      // core version 2.00.22+
+    case 0x28: // bsla de,b
+      regs.DE= regs.DE << (regs.bc.h&31);
+      break;
+    case 0x29: // bsra de,b
+      {
+	i16_t w= regs.DE;
+	w= w >> (regs.bc.h&31);
+	regs.DE= w;
+	break;
+      }
+    case 0x2a: // bsrl de,b
+      regs.DE= regs.DE >> (regs.bc.h&31);
+      break;
+    case 0x2b: // bsrf de,b
+      regs.DE= ~(~regs.DE >> (regs.bc.h&31));
+      break;
+    case 0x2c: // brlc de,b
+      regs.DE= (regs.DE << (regs.bc.h&15)) | (regs.DE >> (16-(regs.bc.h&15)));
+      break;
+    case 0x98: // jp (c)
+      PC= (PC&0xc000) + (inputs->read(regs.BC)<<6);
+      break;
+    default: return false;
+    }
+  if (ret)
+    *ret= r;
+  return true;
+}
+
+// Z80N
+int
+cl_z80::inst_ldix(t_mem code)
+{
+  // ldix, -, {if HL*!=A DE*:=HL*;} DE++; HL++; BC--
+  u8_t at_hl;
+  at_hl= this->get1(regs.HL);
+  vc.rd++;
+  if (at_hl == regs.raf.A)
+    {
+      this->store1(regs.DE, at_hl);
+      vc.wr++;
+    }
+  regs.DE++;
+  regs.HL++;
+  regs.BC--;
+  return resGO;
+}
+
+// Z80N
+int
+cl_z80::inst_lddx(t_mem code)
+{
+  // lddx, -, {if HL*!=A DE*:=HL*;} DE++; HL--; BC--
+  u8_t at_hl;
+  at_hl= this->get1(regs.HL);
+  vc.rd++;
+  if (at_hl == regs.raf.A)
+    {
+      this->store1(regs.DE, at_hl);
+      vc.wr++;
+    }
+  regs.DE++;
+  regs.HL--;
+  regs.BC--;
+  return resGO;
+}
+
 void cl_z80::store1( u16_t addr, t_mem val ) {
   ram->write(addr, val);
 }
@@ -840,4 +1060,72 @@
     }
 }
 
+void
+cl_z80::stack_check_overflow(class cl_stack_op *op)
+{
+  if (op)
+    {
+      if (op->get_op() & stack_write_operation)
+	{
+	  t_addr a= op->get_after();
+	  if (a < sp_limit)
+	    {
+	      class cl_error_stack_overflow *e=
+		new cl_error_stack_overflow(op);
+	      e->init();
+	      error(e);
+	    }
+	}
+    }
+}
+
+
+cl_z80_cpu::cl_z80_cpu(class cl_uc *auc):
+  cl_hw(auc, HW_CPU, 0, "cpu")
+{
+}
+
+int
+cl_z80_cpu::init(void)
+{
+  cl_hw::init();
+
+  cl_var *v;
+  uc->vars->add(v= new cl_var("sp_limit", cfg, z80cpu_sp_limit,
+			      cfg_help(z80cpu_sp_limit)));
+  v->init();
+  return 0;
+}
+
+const char *
+cl_z80_cpu::cfg_help(t_addr addr)
+{
+  switch (addr)
+    {
+    case z80cpu_sp_limit:
+      return "Stack overflows when SP is below this limit";
+    }
+  return "Not used";
+}
+
+t_mem
+cl_z80_cpu::conf_op(cl_memory_cell *cell, t_addr addr, t_mem *val)
+{
+  class cl_z80 *u= (class cl_z80 *)uc;
+  if (val)
+    cell->set(*val);
+  switch ((enum z80cpu_confs)addr)
+    {
+    case z80cpu_sp_limit:
+      if (val)
+	u->sp_limit= *val & 0xffff;
+      else
+	cell->set(u->sp_limit);
+      break;
+    case z80cpu_nuof: break;
+    }
+  return cell->get();
+}
+
+
 /* End of z80.src/z80.cc */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/z80.src/z80cl.h sdcc-4.2.0+dfsg/sim/ucsim/z80.src/z80cl.h
--- sdcc-4.0.0+dfsg/sim/ucsim/z80.src/z80cl.h	2019-01-07 14:30:39.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/z80.src/z80cl.h	2021-10-29 17:39:15.000000000 +0000
@@ -32,6 +32,9 @@
 
 #include "regsz80.h"
 
+class cl_z80;
+class cl_sp_limit_opt;
+
 /*
  * Base type of Z80 microcontrollers
  */
@@ -46,12 +49,23 @@
   class cl_address_space *regs16;
   class cl_address_space *inputs;
   class cl_address_space *outputs;
+  class cl_sp_limit_opt *sp_limit_opt;
+  t_addr sp_limit;
+  bool IFF1, IFF2;
+  u8_t BIT_C;
+  u8_t BIT_N;
+  u8_t BIT_P;
+  u8_t BIT_A;
+  u8_t BIT_Z;
+  u8_t BIT_S;
+  u8_t BIT_ALL;
 public:
   cl_z80(struct cpu_entry *Itype, class cl_sim *asim);
   virtual int init(void);
-  virtual char *id_string(void);
+  virtual const char *id_string(void);
 
   //virtual t_addr get_mem_size(enum mem_class type);
+  virtual void make_cpu_hw(void);
   virtual void mk_hw_elements(void);
   virtual void make_memories(void);
 
@@ -59,7 +73,7 @@
   virtual int inst_length(t_addr addr);
   virtual int inst_branch(t_addr addr);
   virtual int longest_inst(void);
-  virtual char *disass(t_addr addr, const char *sep);
+  virtual char *disass(t_addr addr);
   virtual void print_regs(class cl_console_base *con);
 
   virtual int exec_inst(void);
@@ -70,7 +84,7 @@
                                       int *immed_offset,
                                       struct dis_entry **dentry);
   virtual bool is_call(t_addr addr);
-
+  
   virtual void store1( u16_t addr, t_mem val );
   virtual void store2( u16_t addr, u16_t val );
 
@@ -88,6 +102,8 @@
   virtual u8_t reg_g_read ( t_mem g );
   virtual void reg_g_store( t_mem g, u8_t new_val );
 
+  virtual void stack_check_overflow(class cl_stack_op *op);
+
   virtual int inst_nop(t_mem code);
   virtual int inst_ld(t_mem code);
   virtual int inst_inc(t_mem code);
@@ -184,12 +200,33 @@
 
   virtual int inst_dd_spec(t_mem code) { return -1; }
   virtual int inst_fd_spec(t_mem code) { return -1; }
+
+  virtual bool inst_z80n(t_mem code, int *ret);
+  virtual int inst_ldix(t_mem code);
+  virtual int inst_lddx(t_mem code);
 };
 
 
 unsigned   word_parity( u16_t  x );
 /* returns parity for a 16-bit value */
 
+enum z80cpu_confs
+  {
+   z80cpu_sp_limit	= 0,
+   z80cpu_nuof		= 1
+  };
+
+class cl_z80_cpu: public cl_hw
+{
+public:
+  cl_z80_cpu(class cl_uc *auc);
+  virtual int init(void);
+  virtual unsigned int cfg_size(void) { return z80cpu_nuof; }
+  virtual const char *cfg_help(t_addr addr);
+
+  virtual t_mem conf_op(cl_memory_cell *cell, t_addr addr, t_mem *val);
+};
+
 #endif
 
 /* End of z80.src/z80cl.h */
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/z80.src/z80mac.h sdcc-4.2.0+dfsg/sim/ucsim/z80.src/z80mac.h
--- sdcc-4.0.0+dfsg/sim/ucsim/z80.src/z80mac.h	2017-03-02 10:01:56.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/z80.src/z80mac.h	2021-07-31 09:28:22.000000000 +0000
@@ -24,12 +24,32 @@
 #define fetch1() fetch()
 #endif
 
-#define push2(val) {regs.SP-=2; store2(regs.SP,(val));}
-#define push1(val) {regs.SP-=1; store1(regs.SP,(val));}
+#define push2(val) {							\
+    t_addr sp_before= regs.SP;						\
+    regs.SP-=2;								\
+    store2(regs.SP,(val));						\
+    class cl_stack_op *so=						\
+      new cl_stack_push(instPC,val,sp_before,regs.SP);			\
+    so->init();								\
+    stack_write(so);							\
+  }
+#define push1(val) {					\
+    t_addr sp_before= regs.SP;				\
+    regs.SP-=1;						\
+    store1(regs.SP,(val));				\
+    class cl_stack_op *so=				\
+      new cl_stack_push(instPC,val,sp_before,regs.SP);	\
+    so->init();						\
+    stack_write(so);					\
+  }
 #define pop2(var) {var=get2(regs.SP),regs.SP+=2;}
+#define pop1(var) {var=get1(regs.SP),regs.SP++;}
 //#define pop1(var) {var=get1(regs.SP),regs.SP+=1;}
-#define add_u16_disp(_w, _d) (( (unsigned short)(_w) + (signed char)(_d) ) & 0xffff)
+#define add_u16_disp(_w, _d) (( (unsigned short)(_w) + (signed char)(_d) ) & 0xffff) // Signed displacement.
+#define add_u16_nisp(_w, _d) (( (unsigned short)(_w) + (unsigned char)(_d) ) & 0xffff) // Unsigned displacement.
 #define parity(val) ( ((val>>7)&1) ^ ((val>>6)&1) ^ ((val>>5)&1) ^ ((val>>4)&1) ^ ((val>>3)&1) ^ ((val>>2)&1) ^ ((val>>1)&1) ^ ((val>>0)&1) ^ 1 )
+#define SET_Z(val) (regs.raf.F= (regs.raf.F&(~BIT_Z)) | ((val==0)?BIT_Z:0))
+#define SET_S(val) (regs.raf.F= (regs.raf.F&(~BIT_S)) | ((((val)&0x80)==0)?0:BIT_S))
 
 #define add_A_bytereg(br) {                                         \
    unsigned int accu = (unsigned int)regs.raf.A;                        \
@@ -301,7 +321,7 @@
 }
 
 #define bit_byte(reg, _bitnum) {                                        \
-   regs.raf.F &= ~(BIT_N |BIT_P |BIT_A |BIT_Z |BIT_S);  /* clear these */   \
+    regs.raf.F &= ~(BIT_N |BIT_P |BIT_A |BIT_Z /*|BIT_S*/);  /* clear these */ \
    regs.raf.F |= BIT_A;                                                     \
    if (!(reg & (1 << (_bitnum))))                                       \
      regs.raf.F |= BIT_Z;                                                   \
diff -Nru sdcc-4.0.0+dfsg/sim/ucsim/z80.src/z80n.txt sdcc-4.2.0+dfsg/sim/ucsim/z80.src/z80n.txt
--- sdcc-4.0.0+dfsg/sim/ucsim/z80.src/z80n.txt	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/sim/ucsim/z80.src/z80n.txt	2020-06-08 07:35:50.000000000 +0000
@@ -0,0 +1,89 @@
+Example code:
+	.zxn			; accept ZX-Next opcodes
+	
+; T=4+	8T*	swapnib         ED 23           A bits 7-4 swap with A bits 3-0
+; T=4+  8T     mul d,e         ED 30           multiply DE = D*E (no flags set)
+; 4T    	add  hl,a       ED 31           Add A to HL (no flags set) not sign extended
+; 4T*    	add  de,a       ED 32           Add A to DE (no flags set) not sign extended
+; 4T*    	add  bc,a       ED 33           Add A to BC (no flags set) not sign extended
+; 12T    	add  hl,NNNN    ED 34 LO HI     Add NNNN to HL (no flags set)	add hl,#32767
+; 12T*   	add  de,NNNN    ED 35 LO HI     Add NNNN to DE (no flags set) add de,#32767
+; 12T*   	add  bc,NNNN    ED 36 LO HI     Add NNNN to BC (no flags set) add bc,#32767
+; 16T*      	outinb          ED 90           out (c),(hl), hl++
+; 16T    	ldix            ED A4           As LDI,  but if byte==A does not copy
+; 21T    	ldirx           ED B4           As LDIR, but if byte==A does not copy
+; 16T*   	lddx            ED AC           As LDD,  but if byte==A does not copy, and DE is incremented
+; 21T*   	lddrx           ED BC           As LDDR,  but if byte==A does not copy
+; 21T*   	ldirscale       ED B6           As LDIRX,  if(hl)!=A then (de)=(hl); HL_A'+=BC'; DE+=DE'; dec BC; Loop.
+; 12T*   	ldpirx          ED B7           (de) = ( (hl&$fff8)+(E&7) ) when != A
+; 8T     	mirror a        ED 24           mirror the bits in A     
+; 8T     	mirror de       ED 26           mirror the bits in DE     
+; 22T*   	push NNNN       ED 8A HI LO     push 16bit immediate value, big endian push #32767
+; 8T*    	pop x           ED 8B           pop value and discard
+	
+; ** reg,val are both 8-bit numbers
+; 16T*   	nextreg reg,val ED 91 reg,val   Set a NEXT register (like doing out($243b),reg then out($253b),val nextreg #31,#63
+; 12T*    	nextreg reg,a   ED 92 reg       Set a NEXT register using A (like doing out($243b),reg then out($253b),A ) nextreg #31,a
+; 8T   		pixeldn         ED 93           Move down a line on the ULA screen
+; 8T   		pixelad         ED 94           using D,E (as Y,X) calculate the ULA screen address and store in HL
+; 8T   		setae           ED 95           Using the lower 3 bits of E (X coordinate), set the correct bit value in A
+; 11T   	test NN         ED 27 NN        And A with NN and set all flags. A is not affected.
+	tst #31
+	test #31
+	tst a,#31
+	test a,#31
+	
+; Memory mapping - specify which 8k ram page is placed into
+; the corresponding 8k slot of the z80's 64k memory space.
+; 
+; 16T*  	mmu0 NN         ED 91 50 NN     macro: Ram page in slot 0-8k
+; 16T*  	mmu1 NN         ED 91 51 NN     macro: Ram page in slot 8k-16k
+; 16T*  	mmu2 NN         ED 91 52 NN     macro: Ram page in slot 16k-24k
+; 16T*  	mmu3 NN         ED 91 53 NN     macro: Ram page in slot 24k-32k
+; 16T*  	mmu4 NN         ED 91 54 NN     macro: Ram page in slot 32k-40k
+; 16T*  	mmu5 NN         ED 91 55 NN     macro: Ram page in slot 40k-48k
+; 16T*  	mmu6 NN         ED 91 56 NN     macro: Ram page in slot 48k-56k
+; 16T*  	mmu7 NN         ED 91 57 NN     macro: Ram page in slot 56k-64k
+
+; 12T*  	mmu0 a          ED 92 50        macro: Ram page in slot 0-8k
+; 12T*  	mmu1 a          ED 92 51        macro: Ram page in slot 8k-16k
+; 12T*  	mmu2 a          ED 92 52        macro: Ram page in slot 16k-24k
+; 12T*  	mmu3 a          ED 92 53        macro: Ram page in slot 24k-32k
+; 12T*  	mmu4 a          ED 92 54        macro: Ram page in slot 32k-40k
+; 12T*  	mmu5 a          ED 92 55        macro: Ram page in slot 40k-48k
+; 12T*  	mmu6 a          ED 92 56        macro: Ram page in slot 48k-56k
+; 12T*  	mmu7 a          ED 92 57        macro: Ram page in slot 56k-64k
+
+
+
+
+; cu.wait VER,HOR   ->  16-bit encoding 0x8000 + (HOR << 9) + VER
+; (0<=VER<=311, 0<=HOR<=55)  BIG ENDIAN!
+
+	cu.wait #0,#1		; 0x82, 0x00
+	cu.wait #0,#2		; 0x84, 0x00
+	cu.wait #0,#55		; 0xEE, 0x00
+	
+	cu.wait #1,#0		; 0x80, 0x01
+	cu.wait #2,#0		; 0x80, 0x02
+	cu.wait #311,#0		; 0x81, 0x37
+
+; cu.move REG,VAL  -> 16-bit encoding (REG << 8) + VAL
+; (0<= REG <= 127, 0 <= VAL <= 255)  BIG ENDIAN!
+
+	cu.move #0,#0		; 0x00, 0x00
+	cu.move #1,#0		; 0x01, 0x00
+	cu.move #127,#0		; 0x7F, 0x00
+	        
+	cu.move #0,#1		; 0x00, 0x01
+	cu.move #0,#2		; 0x00, 0x02
+	cu.move #0,#127		; 0x00, 0x7F
+	cu.move #0,#255		; 0x00, 0xFF
+
+; cu.stop   -> 16-bit encoding 0xffff (impossible cu.wait)
+
+	cu.stop			; 0xFF, 0xFF
+
+; cu.nop  -> 16-bit encoding 0x0000 (do nothing cu.move)
+
+	cu.nop 			; 0x00, 0x00
diff -Nru sdcc-4.0.0+dfsg/src/cdbFile.c sdcc-4.2.0+dfsg/src/cdbFile.c
--- sdcc-4.0.0+dfsg/src/cdbFile.c	2018-06-17 07:38:22.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/cdbFile.c	2021-01-03 09:47:54.000000000 +0000
@@ -294,6 +294,9 @@
   char debugSym[INITIAL_INLINEASM];
   
   if (!cdbFilePtr) return 0;
+  
+  if (ic->inlined)
+    return 0;
 
   sprintf (debugSym, "C$%s$%d$%ld_%ld$%d",
            FileBaseName (ic->filename), ic->lineno,
diff -Nru sdcc-4.0.0+dfsg/src/clean.mk sdcc-4.2.0+dfsg/src/clean.mk
--- sdcc-4.0.0+dfsg/src/clean.mk	2013-11-16 16:53:35.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/clean.mk	2022-01-09 00:54:25.000000000 +0000
@@ -1,4 +1,4 @@
-CLEANALLPORTS = avr ds390 ds400 hc08 mcs51 pic14 pic16 stm8 z80 xa51
+CLEANALLPORTS = avr ds390 ds400 hc08 mos6502 mcs51 pic14 pic16 stm8 z80 xa51 pdk
 
 # Deleting all files created by building the program
 # --------------------------------------------------
diff -Nru sdcc-4.0.0+dfsg/src/ds390/gen.c sdcc-4.2.0+dfsg/src/ds390/gen.c
--- sdcc-4.0.0+dfsg/src/ds390/gen.c	2019-05-31 04:35:49.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/ds390/gen.c	2021-07-13 08:19:08.000000000 +0000
@@ -862,20 +862,18 @@
     }
 
   dbuf_init (&dbuf, 128);
-  if (val)
+  if (IS_ASSIGN_ICODE (ic) && isOperandLiteral (IC_RIGHT (ic)))
+    {
+      val = (val + (int) operandLitValue (IC_RIGHT (ic))) & 0xffffff;
+      dbuf_printf (&dbuf, "0x%06x", val);
+    }
+  else if (val)
     {
       dbuf_printf (&dbuf, "(%s %c 0x%06x)", OP_SYMBOL (IC_LEFT (ic))->rname, val >= 0 ? '+' : '-', abs (val) & 0xffffff);
     }
   else
     {
-      if (IS_ASSIGN_ICODE (ic) && isOperandLiteral (IC_RIGHT (ic)))
-        {
-          dbuf_printf (&dbuf, "0x%06x", (int) operandLitValue (IC_RIGHT (ic)));
-        }
-      else
-        {
-          dbuf_append_str (&dbuf, OP_SYMBOL (IC_LEFT (ic))->rname);
-        }
+      dbuf_append_str (&dbuf, OP_SYMBOL (IC_LEFT (ic))->rname);
     }
 
   aop->aopu.aop_immd.aop_immd1 = dbuf_detach_c_str (&dbuf);
@@ -5097,6 +5095,7 @@
       int emitTlbl;
       int labelRange;
       const char *l;
+      unsigned int offset;
 
       /* If the next instruction is a goto and the goto target
        * is <= 5 instructions previous to this, we can generate
@@ -5129,7 +5128,8 @@
         }
       l = aopGet (IC_RESULT (ic), MSB16, FALSE, FALSE, NULL);
       emitcode ("dec", "%s", l);
-      if (size > 2)
+
+      for (offset=2; offsetkey));
             }
-          l = aopGet (IC_RESULT (ic), MSB24, FALSE, FALSE, NULL);
+          l = aopGet (IC_RESULT (ic), offset, FALSE, FALSE, NULL);
           emitcode ("dec", "%s", l);
         }
-      if (size > 3)
-        {
-          if (EQ (l, "acc"))
-            {
-              emitcode ("jnz", "!tlabel", labelKey2num (tlbl->key));
-            }
-          else if (AOP_TYPE (IC_RESULT (ic)) == AOP_REG ||
-                   AOP_TYPE (IC_RESULT (ic)) == AOP_DPTR || IS_AOP_PREG (IC_RESULT (ic)))
-            {
-              emitcode ("cjne", "%s,#!constbyte,!tlabel", l, 0xff, labelKey2num (tlbl->key));
-            }
-          else
-            {
-              emitcode ("cjne", "a,%s,!tlabel", l, labelKey2num (tlbl->key));
-            }
-          emitcode ("dec", "%s", aopGet (IC_RESULT (ic), MSB32, FALSE, FALSE, NULL));
-        }
+
       if (emitTlbl)
         {
           emitLabel (tlbl);
@@ -8659,36 +8643,74 @@
 }
 
 /*-----------------------------------------------------------------*/
-/* genGetHbit - generates code get highest order bit               */
+/* genGetAbit - generates code get highest order bit               */
 /*-----------------------------------------------------------------*/
 static void
-genGetHbit (iCode * ic)
+genGetAbit (iCode * ic)
 {
   operand *left, *result;
 
-  D (emitcode (";", "genGetHbit"));
+  D (emitcode (";", "genGetAbit"));
 
   left = IC_LEFT (ic);
   result = IC_RESULT (ic);
   aopOp (left, ic, FALSE, FALSE);
+  aopOp (IC_RIGHT (ic), ic, FALSE, FALSE);
   aopOp (result, ic, FALSE, AOP_USESDPTR (left));
 
-  /* get the highest order byte into a */
-  MOVA (aopGet (left, AOP_SIZE (left) - 1, FALSE, FALSE, NULL));
+  int shCount = (int) ulFromVal (IC_RIGHT (ic)->aop->aopu.aop_lit);
+
+  /* get byte into a */
+  MOVA (aopGet (left, shCount / 8, FALSE, FALSE, NULL));
+  shCount %= 8;
+
   if (AOP_TYPE (result) == AOP_CRY)
     {
-      emitcode ("rlc", "a");
+      if ((shCount) == 7)
+        emitcode ("rlc", "a");
+      else if ((shCount) == 0)
+        emitcode ("rrc", "a");
+      else
+        emitcode ("mov", "c,acc[%d]", shCount);
       outBitC (result);
     }
   else
     {
-      emitcode ("rl", "a");
-      emitcode ("anl", "a,#0x01");
+      switch (shCount)
+        {
+        case 2:
+          emitcode ("rr", "a");
+          //fallthrough
+        case 1:
+          emitcode ("rr", "a");
+          //fallthrough
+        case 0:
+          emitcode ("anl", "a,#0x01");
+          break;
+        case 3:
+        case 5:
+          emitcode ("mov", "c,acc[%d]", shCount);
+          emitcode ("clr", "a");
+          emitcode ("rlc", "a");
+          break;
+        case 4:
+          emitcode ("swap", "a");
+          emitcode ("anl", "a,#0x01");
+          break;
+        case 6:
+          emitcode ("rl", "a");
+          //fallthrough
+        case 7:
+          emitcode ("rl", "a");
+          emitcode ("anl", "a,#0x01");
+          break;
+        }
       outAcc (result);
     }
 
 
   freeAsmop (result, NULL, ic, TRUE);
+  freeAsmop (IC_RIGHT (ic), NULL, ic, TRUE);
   freeAsmop (left, NULL, ic, TRUE);
 }
 
@@ -9437,7 +9459,7 @@
     {
       shiftLLong (left, result, full_bytes);
     }
-  else if ((shCount == 2) && (full_bytes == 0))
+  else if ((shCount == 2) && (full_bytes == 0) && !isOperandVolatile (result, FALSE))
     {
       shiftLLong (left, result, full_bytes);
       shiftLLong (result, result, full_bytes);
@@ -14328,8 +14350,8 @@
           genRLC (ic);
           break;
 
-        case GETHBIT:
-          genGetHbit (ic);
+        case GETABIT:
+          genGetAbit (ic);
           break;
 
         case LEFT_OP:
diff -Nru sdcc-4.0.0+dfsg/src/ds390/main.c sdcc-4.2.0+dfsg/src/ds390/main.c
--- sdcc-4.0.0+dfsg/src/ds390/main.c	2019-01-02 15:30:21.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/ds390/main.c	2021-08-08 17:13:19.000000000 +0000
@@ -42,8 +42,6 @@
     { 0, OPTION_FLAT24_MODEL,   NULL, "use the flat24 model for the ds390 (default)" },
     { 0, OPTION_STACK_8BIT,     NULL, "use the 8bit stack for the ds390 (not supported yet)" },
     { 0, OPTION_STACK_SIZE,     &options.stack_size, "Tells the linker to allocate this space for stack", CLAT_INTEGER },
-    { 0, "--pack-iram",         NULL, "Tells the linker to pack variables in internal ram (default)"},
-    { 0, "--no-pack-iram",      &options.no_pack_iram, "Deprecated: Tells the linker not to pack variables in internal ram"},
     { 0, "--stack-10bit",       &options.stack10bit, "use the 10bit stack for ds390 (default)" },
     { 0, "--use-accelerator",   &options.useAccelerator, "generate code for ds390 arithmetic accelerator"},
     { 0, "--protect-sp-update", &options.protect_sp_update, "will disable interrupts during ESP:SP updates"},
@@ -99,6 +97,7 @@
 void ds390_assignRegisters (ebbIndex * ebbi);
 
 static int regParmFlg = 0;      /* determine if we can register a parameter */
+static struct sym_link *regParmFuncType;
 
 static void
 _ds390_init (void)
@@ -110,11 +109,15 @@
 _ds390_reset_regparm (struct sym_link *funcType)
 {
   regParmFlg = 0;
+  regParmFuncType = funcType;
 }
 
 static int
 _ds390_regparm (sym_link * l, bool reentrant)
 {
+  if (IFFUNC_HASVARARGS (regParmFuncType))
+    return 0;
+
     if (IS_SPEC(l) && (SPEC_NOUN(l) == V_BIT))
         return 0;
     if (options.parms_in_bank1 == 0) {
@@ -481,7 +484,7 @@
 {
   if (op == RRC
       || op == RLC
-      || op == GETHBIT
+      || op == GETABIT
       || (op == SWAP && size <= 2)
      )
     return TRUE;
@@ -1026,6 +1029,8 @@
     NULL,
     NULL,
     NULL,
+    NULL,
+    NULL,
   },
   /* Sizes: char, short, int, long, long long, near ptr, far ptr, gptr, bit, float */
   { 1, 2, 2, 4, 8, 1, 2, 3, 2, 3, 1, 4 },
@@ -1061,6 +1066,7 @@
     1                           // No fancy alignments supported.
   },
   { NULL, NULL },
+  0,                            // ABI revision
   { +1, 1, 4, 1, 1, 0, 0 },
   /* ds390 has an 16 bit mul & div */
   { -1, FALSE },
@@ -1126,8 +1132,6 @@
     { 0, OPTION_FLAT24_MODEL,   NULL, "use the flat24 model for the ds390 (default)" },
     { 0, OPTION_STACK_8BIT,     NULL, "use the 8bit stack for the ds390 (not supported yet)" },
     { 0, OPTION_STACK_SIZE,     &options.stack_size, "Tells the linker to allocate this space for stack", CLAT_INTEGER },
-    { 0, "--pack-iram",         NULL, "Tells the linker to pack variables in internal ram (default)"},
-    { 0, "--no-pack-iram",      &options.no_pack_iram, "Deprecated: Tells the linker not to pack variables in internal ram"},
     { 0, "--stack-10bit",       &options.stack10bit, "use the 10bit stack for ds390 (default)" },
     { 0, "--use-accelerator",   &options.useAccelerator, "generate code for ds390 arithmetic accelerator"},
     { 0, "--protect-sp-update", &options.protect_sp_update, "will disable interrupts during ESP:SP updates"},
@@ -1366,6 +1370,7 @@
     NULL,
     NULL,
     NULL,
+    NULL,
   },
   /* Sizes: char, short, int, long, long long, near ptr, far ptr, gptr, func ptr, banked func ptr, bit, float */
   { 1, 2, 2, 4, 8, 1, 3, 3, 3, 3, 1, 4 },
@@ -1400,6 +1405,7 @@
     1                           // No fancy alignments supported.
   },
   { NULL, NULL },
+  0,                            // ABI revision
   { +1, 1, 4, 1, 1, 0, 0 },
   /* ds390 has an 16 bit mul & div */
   { -1, FALSE },
@@ -1481,8 +1487,6 @@
     { 0, OPTION_FLAT24_MODEL,   NULL, "use the flat24 model for the ds400 (default)" },
     { 0, OPTION_STACK_8BIT,     NULL, "use the 8bit stack for the ds400 (not supported yet)" },
     { 0, OPTION_STACK_SIZE,     &options.stack_size, "Tells the linker to allocate this space for stack", CLAT_INTEGER },
-    { 0, "--pack-iram",         NULL, "Tells the linker to pack variables in internal ram (default)"},
-    { 0, "--no-pack-iram",      &options.no_pack_iram, "Deprecated: Tells the linker not to pack variables in internal ram"},
     { 0, "--stack-10bit",       &options.stack10bit, "use the 10bit stack for ds400 (default)" },
     { 0, "--use-accelerator",   &options.useAccelerator, "generate code for ds400 arithmetic accelerator"},
     { 0, "--protect-sp-update", &options.protect_sp_update, "will disable interrupts during ESP:SP updates"},
@@ -1622,6 +1626,7 @@
     NULL,
     NULL,
     NULL,
+    NULL,
   },
   /* Sizes: char, short, int, long, long long, near ptr, far ptr, gptr, func ptr, banked func ptr, bit, float */
   { 1, 2, 2, 4, 8, 1, 2, 3, 2, 3, 1, 4 },
@@ -1656,6 +1661,7 @@
     1
   },
   { _ds400_generateRomDataArea, _ds400_linkRomDataArea },
+  0,                            // ABI revision
   { +1, 1, 4, 1, 1, 0, 0 },
   { -1, FALSE },
   { ds390_emitDebuggerSymbol },
diff -Nru sdcc-4.0.0+dfsg/src/ds390/peeph.def sdcc-4.2.0+dfsg/src/ds390/peeph.def
--- sdcc-4.0.0+dfsg/src/ds390/peeph.def	2013-08-29 15:17:10.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/ds390/peeph.def	2020-07-31 11:03:31.000000000 +0000
@@ -1082,7 +1082,7 @@
 } by {
         ; Peephole 182a   used 24 bit load of dptr
         mov	dptr,#0x%3%2%1
-} if 24bitMode(), portIsDS390
+} if 24bitMode(), isPort('ds390' 'ds400')
 
 // saves 2 bytes, ?? cycles.
 replace {
@@ -1092,7 +1092,7 @@
 } by {
         ; Peephole 182b   used 24 bit load of dptr
         mov  dptr,#((%3 << 16) + (%2 << 8) + %1)
-} if 24bitMode(), portIsDS390
+} if 24bitMode(), isPort('ds390' 'ds400')
 
 // saving 3 byte, 2 cycles, return(float_constant) profits here
 replace {
@@ -1696,7 +1696,7 @@
 	; Peephole 213.a inserted fix
 	mov  %1,#(%2 >> 8)
 	xrl  %1,#0x80
-} if portIsDS390
+} if isPort('ds390' 'ds400')
 
 replace {
 	mov  %1,#(( %2 >> 16 ) ^ 0x80)
@@ -1704,7 +1704,7 @@
 	; Peephole 213.b inserted fix
 	mov  %1,#(%2 >> 16)
 	xrl  %1,#0x80
-} if portIsDS390
+} if isPort('ds390' 'ds400')
 
 replace {
 	mov  %1,#(( %2 + %3 >> 8 ) ^ 0x80)
@@ -1712,7 +1712,7 @@
 	; Peephole 213.c inserted fix
 	mov  %1,#((%2 + %3) >> 8)
 	xrl  %1,#0x80
-} if portIsDS390
+} if isPort('ds390' 'ds400')
 
 replace  {
 	mov  %1,a
diff -Nru sdcc-4.0.0+dfsg/src/ds390/ralloc.c sdcc-4.2.0+dfsg/src/ds390/ralloc.c
--- sdcc-4.0.0+dfsg/src/ds390/ralloc.c	2019-06-29 04:30:58.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/ds390/ralloc.c	2022-02-03 09:32:48.000000000 +0000
@@ -236,15 +236,12 @@
 static bool
 isOperandInFarSpace2 (operand * op)
 {
-  symbol * opsym;
-  
   if (isOperandInFarSpace (op))
     return TRUE;
 
   if (!IS_ITEMP (op))
     return FALSE;
-    
-  opsym = OP_SYMBOL (op);
+
   if (isOperandInReg (op))
     return FALSE;
 
@@ -2991,6 +2988,9 @@
 
   if (IS_OP_VOLATILE (IC_RIGHT (dic)))
     return;
+    
+  if (!IS_SYMOP (IC_RIGHT (dic)))
+    return;
 
   if ((IS_SYMOP (IC_RIGHT (dic)) && OP_SYMBOL (IC_RIGHT (dic))->addrtaken) || isOperandGlobal (IC_RIGHT (dic)))
     disallowHiddenAssignment = 1;
@@ -3347,7 +3347,7 @@
       /* pack registers for accumulator use, when the
          result of an arithmetic or bit wise operation
          has only one use, that use is immediately following
-         the defintion and the using iCode has only one
+         the definition and the using iCode has only one
          operand or has two operands but one is literal &
          the result of that operation is not on stack then
          we can leave the result of this operation in acc:b
diff -Nru sdcc-4.0.0+dfsg/src/hc08/gen.c sdcc-4.2.0+dfsg/src/hc08/gen.c
--- sdcc-4.0.0+dfsg/src/hc08/gen.c	2020-01-09 13:41:55.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/hc08/gen.c	2022-02-07 07:12:08.000000000 +0000
@@ -104,7 +104,7 @@
 #define AOP_OP(aop) aop->op
 
 static bool regalloc_dry_run;
-static unsigned char regalloc_dry_run_cost;
+static unsigned int regalloc_dry_run_cost;
 
 static void
 emitBranch (char *branchop, symbol * tlbl)
@@ -126,7 +126,6 @@
   genLine.lineElement.isDebug = 0;
 }
 
-
 /*--------------------------------------------------------------------------*/
 /* transferRegReg - Transfer from register(s) sreg to register(s) dreg. If  */
 /*                  freesrc is true, sreg is marked free and available for  */
@@ -143,7 +142,7 @@
   if (!dreg)
     return;
 
-  /* But it's definately an error if there's no source. */
+  /* But it's definitely an error if there's no source. */
   if (!sreg)
     {
       werror (E_INTERNAL_ERROR, __FILE__, __LINE__, "NULL sreg in transferRegReg");
@@ -167,7 +166,7 @@
       switch (srcidx)
         {
         case H_IDX:            /* H to A */
-          pushReg (hc08_reg_h, FALSE);
+          pushReg (hc08_reg_h, false);
           pullReg (hc08_reg_a);
           break;
         case X_IDX:            /* X to A */
@@ -182,11 +181,11 @@
       switch (srcidx)
         {
         case A_IDX:            /* A to H */
-          pushReg (hc08_reg_a, FALSE);
+          pushReg (hc08_reg_a, false);
           pullReg (hc08_reg_h);
           break;
         case X_IDX:            /* X to H */
-          pushReg (hc08_reg_x, FALSE);
+          pushReg (hc08_reg_x, false);
           pullReg (hc08_reg_h);
           break;
         default:
@@ -201,7 +200,7 @@
           regalloc_dry_run_cost++;
           break;
         case H_IDX:            /* H to X */
-          pushReg (hc08_reg_h, FALSE);
+          pushReg (hc08_reg_h, false);
           pullReg (hc08_reg_x);
           break;
         default:
@@ -212,7 +211,7 @@
       switch (srcidx)
         {
         case XA_IDX:           /* XA to HX */
-          pushReg (hc08_reg_x, FALSE);
+          pushReg (hc08_reg_x, false);
           pullReg (hc08_reg_h);
           emitcode ("tax", "");
           regalloc_dry_run_cost++;
@@ -227,7 +226,7 @@
         case HX_IDX:           /* HX to XA */
           emitcode ("txa", "");
           regalloc_dry_run_cost++;
-          pushReg (hc08_reg_h, FALSE);
+          pushReg (hc08_reg_h, false);
           pullReg (hc08_reg_x);
           break;
         default:
@@ -245,8 +244,8 @@
 
   dreg->aop = sreg->aop;
   dreg->aopofs = sreg->aopofs;
-  dreg->isFree = FALSE;
-  hc08_dirtyReg (dreg, FALSE);
+  dreg->isFree = false;
+  hc08_dirtyReg (dreg, false);
   hc08_useReg (dreg);
 }
 
@@ -374,7 +373,7 @@
       break;
     }
   hc08_useReg (reg);
-  hc08_dirtyReg (reg, FALSE);
+  hc08_dirtyReg (reg, false);
 }
 
 /*--------------------------------------------------------------------------*/
@@ -396,17 +395,17 @@
   if (hc08_reg_a->isFree)
     {
       loadRegFromConst (hc08_reg_a, c);
-      pushReg (hc08_reg_a, TRUE);
+      pushReg (hc08_reg_a, true);
     }
   else if (hc08_reg_x->isFree)
     {
       loadRegFromConst (hc08_reg_x, c);
-      pushReg (hc08_reg_x, TRUE);
+      pushReg (hc08_reg_x, true);
     }
   else if (hc08_reg_h->isFree && !c)
     {
       loadRegFromConst (hc08_reg_h, c);
-      pushReg (hc08_reg_h, TRUE);
+      pushReg (hc08_reg_h, true);
     }
   else if (!c)
     {
@@ -416,8 +415,8 @@
     }
   else
     {
-      pushReg (hc08_reg_a, FALSE);
-      pushReg (hc08_reg_a, FALSE);
+      pushReg (hc08_reg_a, false);
+      pushReg (hc08_reg_a, false);
       loadRegFromConst (hc08_reg_a, c);
       emitcode ("sta", "2,s");
       regalloc_dry_run_cost += 3;
@@ -434,11 +433,11 @@
 {
   if (!reg->isFree)
     {
-      pushReg (reg, TRUE);
-      return TRUE;
+      pushReg (reg, true);
+      return true;
     }
   else
-    return FALSE;
+    return false;
 }
 
 /*--------------------------------------------------------------------------*/
@@ -450,11 +449,11 @@
 {
   if (!reg->isDead)
     {
-      pushReg (reg, TRUE);
-      return TRUE;
+      pushReg (reg, true);
+      return true;
     }
   else
-    return FALSE;
+    return false;
 }
 
 /*--------------------------------------------------------------------------*/
@@ -585,7 +584,7 @@
 
 #if 0
   /* If operand is volatile, we cannot optimize. */
-  if (!aop->op || isOperandVolatile (aop->op, FALSE))
+  if (!aop->op || isOperandVolatile (aop->op, false))
     goto forceload;
 
 
@@ -604,7 +603,7 @@
       && operandsEqu (hc08_reg_h->aop->op, aop->op) && (hc08_reg_h->aopofs == loffset))
     {
       DD (emitcode ("", "; found correct value for %s in h", reg->name));
-      transferRegReg (hc08_reg_h, reg, FALSE);
+      transferRegReg (hc08_reg_h, reg, false);
       hc08_useReg (reg);
       return;
     }
@@ -614,7 +613,7 @@
       && operandsEqu (hc08_reg_x->aop->op, aop->op) && (hc08_reg_x->aopofs == loffset))
     {
       DD (emitcode ("", "; found correct value for %s in x", reg->name));
-      transferRegReg (hc08_reg_x, reg, FALSE);
+      transferRegReg (hc08_reg_x, reg, false);
       hc08_useReg (reg);
       return;
     }
@@ -623,7 +622,7 @@
       && operandsEqu (hc08_reg_a->aop->op, aop->op) && (hc08_reg_a->aopofs == loffset))
     {
       DD (emitcode ("", "; found correct value for %s in a", reg->name));
-      transferRegReg (hc08_reg_a, reg, FALSE);
+      transferRegReg (hc08_reg_a, reg, false);
       hc08_useReg (reg);
       return;
     }
@@ -637,7 +636,7 @@
       if (aop->type == AOP_REG)
         {
           if (loffset < aop->size)
-            transferRegReg (aop->aopu.aop_reg[loffset], reg, FALSE);
+            transferRegReg (aop->aopu.aop_reg[loffset], reg, false);
           else
             loadRegFromConst (reg, 0); /* TODO: handle sign extension */
         }
@@ -649,10 +648,10 @@
             }
           else
             {
-              const char *l = aopAdrStr (aop, loffset, FALSE);
+              const char *l = aopAdrStr (aop, loffset, false);
               emitcode ("lda", "%s", l);
               regalloc_dry_run_cost += ((aop->type == AOP_DIR || aop->type == AOP_IMMD || aop->type == AOP_LIT) ? 2 : 3);
-              hc08_dirtyReg (reg, FALSE);
+              hc08_dirtyReg (reg, false);
             }
         }
       break;
@@ -660,7 +659,7 @@
       if (aop->type == AOP_REG)
         {
           if (loffset < aop->size)
-            transferRegReg (aop->aopu.aop_reg[loffset], reg, FALSE);
+            transferRegReg (aop->aopu.aop_reg[loffset], reg, false);
           else
             loadRegFromConst (reg, 0); /* TODO: handle sign extension */
         }
@@ -672,10 +671,10 @@
             }
           else
             {
-              const char *l = aopAdrStr (aop, loffset, FALSE);
+              const char *l = aopAdrStr (aop, loffset, false);
               emitcode ("ldx", "%s", l);
               regalloc_dry_run_cost += ((aop->type == AOP_DIR || aop->type == AOP_IMMD || aop->type == AOP_LIT) ? 2 : 3);
-              hc08_dirtyReg (reg, FALSE);
+              hc08_dirtyReg (reg, false);
             }
         }
       break;
@@ -688,18 +687,18 @@
        if (aop->type == AOP_SOF && !(_G.stackOfs + _G.stackPushes + aop->aopu.aop_stk + aop->size - loffset - 1))
         {
           pullReg (hc08_reg_h);
-          pushReg (hc08_reg_h, FALSE);
+          pushReg (hc08_reg_h, false);
           break;
         }
       if (aop->type == AOP_REG && loffset < aop->size)
-        transferRegReg (aop->aopu.aop_reg[loffset], hc08_reg_h, TRUE);
-      else if (!(aop->op && isOperandVolatile (aop->op, FALSE)) &&  (loffset - 1 >= 0 || aop->type == AOP_LIT) && (aop->type == AOP_LIT || aop->type == AOP_IMMD || IS_S08 && aop->type == AOP_EXT)) /* TODO: Allow negative loffset - 1 */
+        transferRegReg (aop->aopu.aop_reg[loffset], hc08_reg_h, true);
+      else if (!(aop->op && isOperandVolatile (aop->op, false)) &&  (loffset - 1 >= 0 || aop->type == AOP_LIT) && (aop->type == AOP_LIT || aop->type == AOP_IMMD || IS_S08 && aop->type == AOP_EXT)) /* TODO: Allow negative loffset - 1 */
         {
-          bool pushedx = FALSE;
+          bool pushedx = false;
           if (!hc08_reg_x->isFree)
             {
-              pushReg (hc08_reg_x, TRUE);
-              pushedx = TRUE;
+              pushReg (hc08_reg_x, true);
+              pushedx = true;
             }
           loadRegFromAop (hc08_reg_hx, aop, loffset - 1);
           pullOrFreeReg (hc08_reg_x, pushedx);
@@ -707,18 +706,18 @@
       else if (hc08_reg_a->isFree)
         {
           loadRegFromAop (hc08_reg_a, aop, loffset);
-          transferRegReg (hc08_reg_a, hc08_reg_h, TRUE);
+          transferRegReg (hc08_reg_a, hc08_reg_h, true);
         }
       else if (hc08_reg_x->isFree)
         {
           loadRegFromAop (hc08_reg_x, aop, loffset);
-          transferRegReg (hc08_reg_x, hc08_reg_h, TRUE);
+          transferRegReg (hc08_reg_x, hc08_reg_h, true);
         }
       else
         {
-          pushReg (hc08_reg_a, TRUE);
+          pushReg (hc08_reg_a, true);
           loadRegFromAop (hc08_reg_a, aop, loffset);
-          transferRegReg (hc08_reg_a, hc08_reg_h, TRUE);
+          transferRegReg (hc08_reg_a, hc08_reg_h, true);
           pullReg (hc08_reg_a);
         }
       break;
@@ -734,31 +733,31 @@
           int offset = (_G.stackOfs + _G.stackPushes + aop->aopu.aop_stk + aop->size - loffset - 1);
           if (IS_S08 && offset >= 0 && offset <= 0xff)
             {
-              emitcode ("ldhx", "%s", aopAdrStr (aop, loffset, TRUE));
+              emitcode ("ldhx", "%s", aopAdrStr (aop, loffset, true));
               regalloc_dry_run_cost += 2;
-              hc08_dirtyReg (reg, FALSE);
+              hc08_dirtyReg (reg, false);
               break;
             }
           else if (offset == 1)
             {
               pullReg (hc08_reg_h);
               pullReg (hc08_reg_x);
-              pushReg (hc08_reg_x, FALSE);
-              pushReg (hc08_reg_h, FALSE);
+              pushReg (hc08_reg_x, false);
+              pushReg (hc08_reg_h, false);
               break;
             }
         }
       if (IS_AOP_HX (aop))
         break;
       else if (IS_AOP_XA (aop))
-        transferRegReg (hc08_reg_xa, hc08_reg_hx, FALSE);
+        transferRegReg (hc08_reg_xa, hc08_reg_hx, false);
       else if (aop->type == AOP_DIR || IS_S08 && aop->type == AOP_EXT)
         {
           if (aop->size >= (loffset + 2))
             {
-              emitcode ("ldhx", "%s", aopAdrStr (aop, loffset, TRUE));
+              emitcode ("ldhx", "%s", aopAdrStr (aop, loffset, true));
               regalloc_dry_run_cost += (aop->type == AOP_DIR ? 2 : 3);
-              hc08_dirtyReg (reg, FALSE);
+              hc08_dirtyReg (reg, false);
             }
           else 
             {
@@ -768,9 +767,9 @@
         }
       else if ((aop->type == AOP_LIT) || (aop->type == AOP_IMMD))
         {
-          emitcode ("ldhx", "%s", aopAdrStr (aop, loffset, TRUE));
+          emitcode ("ldhx", "%s", aopAdrStr (aop, loffset, true));
           regalloc_dry_run_cost += 3;
-          hc08_dirtyReg (reg, FALSE);
+          hc08_dirtyReg (reg, false);
         }
       else
         {
@@ -782,11 +781,11 @@
       if (IS_AOP_XA (aop))
         break;
       else if (IS_AOP_HX (aop))
-        transferRegReg (hc08_reg_hx, hc08_reg_xa, FALSE);
+        transferRegReg (hc08_reg_hx, hc08_reg_xa, false);
       else if (IS_AOP_AX (aop))
         {
-          pushReg (hc08_reg_a, FALSE);
-          transferRegReg (hc08_reg_x, hc08_reg_a, FALSE);
+          pushReg (hc08_reg_a, false);
+          transferRegReg (hc08_reg_x, hc08_reg_a, false);
           pullReg (hc08_reg_x);
         }
       else
@@ -814,30 +813,30 @@
   if (aopA && aopX && IS_AOPOFS_X (aopA, ofsA) && IS_AOPOFS_A (aopX, ofsX))
     {
       /* Swap A and X, load H */
-      pushReg (hc08_reg_a, TRUE);
+      pushReg (hc08_reg_a, true);
       if (aopH)
         loadRegFromAop (hc08_reg_h, aopH, ofsH);
-      transferRegReg (hc08_reg_x, hc08_reg_a, FALSE);
+      transferRegReg (hc08_reg_x, hc08_reg_a, false);
       pullReg (hc08_reg_x);
       return;
     }
   if (aopA && aopH && IS_AOPOFS_H (aopA, ofsA) && IS_AOPOFS_A (aopH, ofsH))
     {
       /* Swap A and H, load X */
-      pushReg (hc08_reg_a, TRUE);
+      pushReg (hc08_reg_a, true);
       if (aopX)
         loadRegFromAop (hc08_reg_x, aopX, ofsX);
-      transferRegReg (hc08_reg_h, hc08_reg_a, FALSE);
+      transferRegReg (hc08_reg_h, hc08_reg_a, false);
       pullReg (hc08_reg_h);
       return;
     }
   if (aopX && aopH && IS_AOPOFS_H (aopX, ofsX) && IS_AOPOFS_X (aopH, ofsH))
     {
       /* Swap X and H, load A */
-      pushReg (hc08_reg_x, TRUE);
+      pushReg (hc08_reg_x, true);
       if (aopA)
         loadRegFromAop (hc08_reg_a, aopA, ofsA);
-      transferRegReg (hc08_reg_h, hc08_reg_x, FALSE);
+      transferRegReg (hc08_reg_h, hc08_reg_x, false);
       pullReg (hc08_reg_h);
       return;
     }
@@ -846,18 +845,18 @@
   if (aopA && aopH && aopX && IS_AOPOFS_A (aopH, ofsH) && IS_AOPOFS_H (aopX, ofsX) && IS_AOPOFS_X (aopA, ofsA))
     {
       /* Rotate A->H->X->A */
-      pushReg (hc08_reg_a, FALSE);
-      transferRegReg (hc08_reg_x, hc08_reg_a, FALSE);
-      transferRegReg (hc08_reg_h, hc08_reg_x, FALSE);
+      pushReg (hc08_reg_a, false);
+      transferRegReg (hc08_reg_x, hc08_reg_a, false);
+      transferRegReg (hc08_reg_h, hc08_reg_x, false);
       pullReg (hc08_reg_h);
       return;
     }
   if (aopA && aopH && aopX && IS_AOPOFS_A (aopX, ofsX) && IS_AOPOFS_X (aopH, ofsH) && IS_AOPOFS_H (aopA, ofsA))
     {
       /* Rotate A->X->H->A */
-      pushReg (hc08_reg_a, FALSE);
-      transferRegReg (hc08_reg_h, hc08_reg_a, FALSE);
-      transferRegReg (hc08_reg_x, hc08_reg_h, FALSE);
+      pushReg (hc08_reg_a, false);
+      transferRegReg (hc08_reg_h, hc08_reg_a, false);
+      transferRegReg (hc08_reg_x, hc08_reg_h, false);
       pullReg (hc08_reg_x);
       return;
     }
@@ -933,11 +932,11 @@
       if (copyOrig && reg)
         {
           loadRegFromAop (reg, aop, loffset);
-          aopsof->aopu.aop_stk = pushReg (reg, FALSE);
+          aopsof->aopu.aop_stk = pushReg (reg, false);
         }
       else
         {
-          aopsof->aopu.aop_stk = pushReg (hc08_reg_a, FALSE);
+          aopsof->aopu.aop_stk = pushReg (hc08_reg_a, false);
         }
       aopsof->op = aop->op;
       newaop->stk_aop[loffset] = aopsof;
@@ -998,41 +997,41 @@
     {
     case A_IDX:
       if ((aop->type == AOP_REG) && (loffset < aop->size))
-        transferRegReg (reg, aop->aopu.aop_reg[loffset], FALSE);
+        transferRegReg (reg, aop->aopu.aop_reg[loffset], false);
       else
         {
-          emitcode ("sta", "%s", aopAdrStr (aop, loffset, FALSE));
+          emitcode ("sta", "%s", aopAdrStr (aop, loffset, false));
           regalloc_dry_run_cost += ((aop->type == AOP_DIR || aop->type == AOP_IMMD) ? 2 :3);
         }
       break;
     case X_IDX:
       if ((aop->type == AOP_REG) && (loffset < aop->size))
-        transferRegReg (reg, aop->aopu.aop_reg[loffset], FALSE);
+        transferRegReg (reg, aop->aopu.aop_reg[loffset], false);
       else
         {
-          emitcode ("stx", "%s", aopAdrStr (aop, loffset, FALSE));
+          emitcode ("stx", "%s", aopAdrStr (aop, loffset, false));
           regalloc_dry_run_cost += ((aop->type == AOP_DIR || aop->type == AOP_IMMD) ? 2 :3);
         }
       break;
     case H_IDX:
       if ((aop->type == AOP_REG) && (loffset < aop->size))
-        transferRegReg (reg, aop->aopu.aop_reg[loffset], FALSE);
+        transferRegReg (reg, aop->aopu.aop_reg[loffset], false);
       else if (hc08_reg_a->isFree)
         {
-          transferRegReg (hc08_reg_h, hc08_reg_a, FALSE);
+          transferRegReg (hc08_reg_h, hc08_reg_a, false);
           storeRegToAop (hc08_reg_a, aop, loffset);
           hc08_freeReg (hc08_reg_a);
         }
       else if (hc08_reg_x->isFree)
         {
-          transferRegReg (hc08_reg_h, hc08_reg_x, FALSE);
+          transferRegReg (hc08_reg_h, hc08_reg_x, false);
           storeRegToAop (hc08_reg_x, aop, loffset);
           hc08_freeReg (hc08_reg_x);
         }
       else
         {
-          pushReg (hc08_reg_a, TRUE);
-          transferRegReg (hc08_reg_h, hc08_reg_a, FALSE);
+          pushReg (hc08_reg_a, true);
+          transferRegReg (hc08_reg_h, hc08_reg_a, false);
           storeRegToAop (hc08_reg_a, aop, loffset);
           pullReg (hc08_reg_a);
         }
@@ -1043,25 +1042,25 @@
           int offset = (_G.stackOfs + _G.stackPushes + aop->aopu.aop_stk + aop->size - loffset - 1);
           if (IS_S08 && offset >= 0 && offset <= 0xff)
             {
-              emitcode ("sthx", "%s", aopAdrStr (aop, loffset, TRUE));
+              emitcode ("sthx", "%s", aopAdrStr (aop, loffset, true));
               regalloc_dry_run_cost += 2;
               break;
             }
         }
       if (aop->type == AOP_DIR || IS_S08 && aop->type == AOP_EXT)
         {
-          emitcode ("sthx", "%s", aopAdrStr (aop, loffset, TRUE));
+          emitcode ("sthx", "%s", aopAdrStr (aop, loffset, true));
           regalloc_dry_run_cost += (aop->type == AOP_DIR ? 2 : 3);;
         }
       else if (IS_AOP_XA (aop))
-        transferRegReg (reg, hc08_reg_xa, FALSE);
+        transferRegReg (reg, hc08_reg_xa, false);
       else if (IS_AOP_HX (aop))
         break;
       else if (hc08_reg_a->isFree)
         {
           bool needpula;
           needpula = pushRegIfUsed (hc08_reg_a);
-          transferRegReg (hc08_reg_h, hc08_reg_a, FALSE);
+          transferRegReg (hc08_reg_h, hc08_reg_a, false);
           storeRegToAop (hc08_reg_a, aop, loffset + 1);
           storeRegToAop (hc08_reg_x, aop, loffset);
           pullOrFreeReg (hc08_reg_a, needpula);
@@ -1071,20 +1070,20 @@
           bool needpulx;
           storeRegToAop (hc08_reg_x, aop, loffset);
           needpulx = pushRegIfUsed (hc08_reg_x);
-          transferRegReg (hc08_reg_h, hc08_reg_x, FALSE);
+          transferRegReg (hc08_reg_h, hc08_reg_x, false);
           storeRegToAop (hc08_reg_x, aop, loffset + 1);
           pullOrFreeReg (hc08_reg_x, needpulx);
         }
       break;
     case XA_IDX:
       if (IS_AOP_HX (aop))
-        transferRegReg (reg, hc08_reg_hx, FALSE);
+        transferRegReg (reg, hc08_reg_hx, false);
       else if (IS_AOP_XA (aop))
         break;
       else if (IS_AOP_AX (aop))
         {
-          pushReg (hc08_reg_a, FALSE);
-          transferRegReg (hc08_reg_x, hc08_reg_a, FALSE);
+          pushReg (hc08_reg_a, false);
+          transferRegReg (hc08_reg_x, hc08_reg_a, false);
           pullReg (hc08_reg_x);
         }
       else
@@ -1158,7 +1157,7 @@
         }
 
       if (hc08_reg_x->isLitConst && hc08_reg_x->litConst == c)
-        transferRegReg (hc08_reg_x, reg, FALSE);
+        transferRegReg (hc08_reg_x, reg, false);
       else if (!c)
         {
           emitcode ("clra", "");
@@ -1191,7 +1190,7 @@
         }
 
       if (hc08_reg_a->isLitConst && hc08_reg_a->litConst == c)
-        transferRegReg (hc08_reg_a, reg, FALSE);
+        transferRegReg (hc08_reg_a, reg, false);
       else if (!c)
         {
           emitcode ("clrx", "");
@@ -1214,13 +1213,13 @@
           regalloc_dry_run_cost++;
         }
       else if (hc08_reg_a->isLitConst && hc08_reg_a->litConst == c)
-        transferRegReg (hc08_reg_a, reg, FALSE);
+        transferRegReg (hc08_reg_a, reg, false);
       else if (hc08_reg_x->isLitConst && hc08_reg_x->litConst == c)
-        transferRegReg (hc08_reg_x, reg, FALSE);
+        transferRegReg (hc08_reg_x, reg, false);
       else if (hc08_reg_a->isFree)
         {
           loadRegFromConst (hc08_reg_a, c);
-          transferRegReg (hc08_reg_a, hc08_reg_h, TRUE);
+          transferRegReg (hc08_reg_a, hc08_reg_h, true);
         }
       else if (hc08_reg_x->isFree)
         {
@@ -1228,7 +1227,7 @@
         }
       else
         {
-          pushReg (hc08_reg_x, TRUE);
+          pushReg (hc08_reg_x, true);
           loadRegFromConst (hc08_reg_hx, c << 8);
           pullReg (hc08_reg_x);
         }
@@ -1280,7 +1279,7 @@
       return;
     }
 
-  hc08_dirtyReg (reg, FALSE);
+  hc08_dirtyReg (reg, false);
   reg->isLitConst = 1;
   reg->litConst = c;
   if (reg->rIdx == HX_IDX)
@@ -1315,18 +1314,18 @@
       if (hc08_reg_a->isFree)
         {
           loadRegFromImm (hc08_reg_a, c);
-          transferRegReg (hc08_reg_a, hc08_reg_h, TRUE);
+          transferRegReg (hc08_reg_a, hc08_reg_h, true);
         }
       else if (hc08_reg_x->isFree)
         {
           loadRegFromImm (hc08_reg_x, c);
-          transferRegReg (hc08_reg_x, hc08_reg_h, TRUE);
+          transferRegReg (hc08_reg_x, hc08_reg_h, true);
         }
       else
         {
-          pushReg (hc08_reg_a, TRUE);
+          pushReg (hc08_reg_a, true);
           loadRegFromImm (hc08_reg_a, c);
-          transferRegReg (hc08_reg_a, hc08_reg_h, TRUE);
+          transferRegReg (hc08_reg_a, hc08_reg_h, true);
           pullReg (hc08_reg_a);
         }
       break;
@@ -1343,7 +1342,7 @@
       werror (E_INTERNAL_ERROR, __FILE__, __LINE__, "Bad rIdx in loadRegFromConst");
       return;
     }
-  hc08_dirtyReg (reg, FALSE);
+  hc08_dirtyReg (reg, false);
   hc08_useReg (reg);
 }
 
@@ -1376,16 +1375,16 @@
     case AOP_DIR:
       /* clr operates with read-modify-write cycles, so don't use if the */
       /* destination is volatile to avoid the read side-effect. */
-      if (!c && !(aop->op && isOperandVolatile (aop->op, FALSE)) && optimize.codeSize)
+      if (!c && !(aop->op && isOperandVolatile (aop->op, false)) && optimize.codeSize)
         {
           /* clr dst : 2 bytes, 5 cycles */
-          emitcode ("clr", "%s", aopAdrStr (aop, loffset, FALSE));
+          emitcode ("clr", "%s", aopAdrStr (aop, loffset, false));
           regalloc_dry_run_cost += 2;
         }
       else
         {
           /* mov #0,dst : 3 bytes, 4 cycles */
-          emitcode ("mov", "!immedbyte,%s", c, aopAdrStr (aop, loffset, FALSE));
+          emitcode ("mov", "!immedbyte,%s", c, aopAdrStr (aop, loffset, false));
           regalloc_dry_run_cost += 3;
         }
       break;
@@ -1411,7 +1410,7 @@
         }
       else
         {
-          pushReg (hc08_reg_a, TRUE);
+          pushReg (hc08_reg_a, true);
           loadRegFromConst (hc08_reg_a, c);
           storeRegToAop (hc08_reg_a, aop, loffset);
           pullReg (hc08_reg_a);
@@ -1436,16 +1435,16 @@
     case AOP_DIR:
       /* clr operates with read-modify-write cycles, so don't use if the */
       /* destination is volatile to avoid the read side-effect. */
-      if (!strcmp (c, zero) && !(aop->op && isOperandVolatile (aop->op, FALSE)) && optimize.codeSize)
+      if (!strcmp (c, zero) && !(aop->op && isOperandVolatile (aop->op, false)) && optimize.codeSize)
         {
           /* clr dst : 2 bytes, 5 cycles */
-          emitcode ("clr", "%s", aopAdrStr (aop, loffset, FALSE));
+          emitcode ("clr", "%s", aopAdrStr (aop, loffset, false));
           regalloc_dry_run_cost += 2;
         }
       else
         {
           /* mov #0,dst : 3 bytes, 4 cycles */
-          emitcode ("mov", "%s,%s", c, aopAdrStr (aop, loffset, FALSE));
+          emitcode ("mov", "%s,%s", c, aopAdrStr (aop, loffset, false));
           regalloc_dry_run_cost += 3;
         }
       break;
@@ -1471,7 +1470,7 @@
         }
       else
         {
-          pushReg (hc08_reg_a, TRUE);
+          pushReg (hc08_reg_a, true);
           loadRegFromImm (hc08_reg_a, c);
           storeRegToAop (hc08_reg_a, aop, loffset);
           pullReg (hc08_reg_a);
@@ -1505,7 +1504,7 @@
   else
     {
       /* Signed case */
-      transferRegReg (reg, hc08_reg_a, FALSE);
+      transferRegReg (reg, hc08_reg_a, false);
       emitcode ("rola", "");
       emitcode ("clra", "");
       emitcode ("sbc", "#0");
@@ -1535,7 +1534,7 @@
     case H_IDX:
       storeRegToAop (reg, aop, 0);
       if (size > 1 && isSigned && aop->type == AOP_REG && aop->aopu.aop_reg[0]->rIdx == A_IDX)
-        pushReg (hc08_reg_a, TRUE);
+        pushReg (hc08_reg_a, true);
       storeRegSignToUpperAop (reg, aop, 1, isSigned);
       if (size > 1 && isSigned && aop->type == AOP_REG && aop->aopu.aop_reg[0]->rIdx == A_IDX)
         pullReg (hc08_reg_a);
@@ -1574,16 +1573,16 @@
 static void
 transferAopAop (asmop *srcaop, int srcofs, asmop *dstaop, int dstofs)
 {
-  bool needpula = FALSE;
+  bool needpula = false;
   reg_info *reg = NULL;
-  bool keepreg = FALSE;
+  bool keepreg = false;
   bool afree;
 
   wassert (srcaop && dstaop);
 
   /* ignore transfers at the same byte, unless its volatile */
-  if (srcaop->op && !isOperandVolatile (srcaop->op, FALSE)
-      && dstaop->op && !isOperandVolatile (dstaop->op, FALSE)
+  if (srcaop->op && !isOperandVolatile (srcaop->op, false)
+      && dstaop->op && !isOperandVolatile (dstaop->op, false)
       && operandsEqu (srcaop->op, dstaop->op) && srcofs == dstofs && dstaop->type == srcaop->type)
     return;
 
@@ -1615,9 +1614,9 @@
     
   if ((dstaop->type == AOP_DIR) && (srcaop->type == AOP_DIR))
     {
-      const char *src = aopAdrStr (srcaop, srcofs, FALSE);
+      const char *src = aopAdrStr (srcaop, srcofs, false);
       /* mov src,dst : 3 bytes, 5 cycles */
-      emitcode ("mov", "%s,%s", src, aopAdrStr (dstaop, dstofs, FALSE));
+      emitcode ("mov", "%s,%s", src, aopAdrStr (dstaop, dstofs, false));
       regalloc_dry_run_cost += 3;
       return;
     }
@@ -1625,12 +1624,12 @@
   if (dstaop->type == AOP_REG)
     {
       reg = dstaop->aopu.aop_reg[dstofs];
-      keepreg = TRUE;
+      keepreg = true;
     }
   else if ((srcaop->type == AOP_REG) && (srcaop->aopu.aop_reg[srcofs]))
     {
       reg = srcaop->aopu.aop_reg[srcofs];
-      keepreg = TRUE;
+      keepreg = true;
     }
 
   afree = hc08_reg_a->isFree;
@@ -1643,8 +1642,8 @@
         reg = hc08_reg_x;
       else
         {
-          pushReg (hc08_reg_a, TRUE);
-          needpula = TRUE;
+          pushReg (hc08_reg_a, true);
+          needpula = true;
           reg = hc08_reg_a;
         }
     }
@@ -1669,7 +1668,7 @@
   emitcode (accop, "%s", param);
   regalloc_dry_run_cost += ((!param[0] || !strcmp(param, ",x")) ? 1 : ((param[0]=='#' || param[0]=='*') ? 2 : 3));
   if (strcmp (accop, "bit") && strcmp (accop, "cmp") && strcmp (accop, "cpx"))
-    hc08_dirtyReg (hc08_reg_a, FALSE);
+    hc08_dirtyReg (hc08_reg_a, false);
 }
 
 /*--------------------------------------------------------------------------*/
@@ -1696,14 +1695,14 @@
     }
   else if (aop->type == AOP_REG)
     {
-      pushReg (aop->aopu.aop_reg[loffset], FALSE);
+      pushReg (aop->aopu.aop_reg[loffset], false);
       emitcode (accop, "1,s");
       regalloc_dry_run_cost += 3;
       pullNull (1);
     }
   else
     {
-      emitcode (accop, "%s", aopAdrStr (aop, loffset, FALSE));
+      emitcode (accop, "%s", aopAdrStr (aop, loffset, false));
       if (aop->type == AOP_DIR || aop->type == AOP_LIT)
         regalloc_dry_run_cost +=2;
       else
@@ -1711,7 +1710,7 @@
     }
 
   if (strcmp (accop, "bit") && strcmp (accop, "cmp") && strcmp (accop, "cpx"))
-    hc08_dirtyReg (hc08_reg_a, FALSE);
+    hc08_dirtyReg (hc08_reg_a, false);
 }
 
 
@@ -1732,22 +1731,22 @@
       sprintf (rmwaop, "%sa", rmwop);
       emitcode (rmwaop, "");
       regalloc_dry_run_cost++;
-      hc08_dirtyReg (hc08_reg_a, FALSE);
+      hc08_dirtyReg (hc08_reg_a, false);
     }
   else if (reg->rIdx == X_IDX)
     {
       sprintf (rmwaop, "%sx", rmwop);
       emitcode (rmwaop, "");
       regalloc_dry_run_cost++;
-      hc08_dirtyReg (hc08_reg_x, FALSE);
+      hc08_dirtyReg (hc08_reg_x, false);
     }
   else
     {
-      pushReg (reg, FALSE);
+      pushReg (reg, false);
       emitcode (rmwop, "1,s");
       regalloc_dry_run_cost += 3;
       pullReg (reg);
-      hc08_dirtyReg (reg, FALSE);
+      hc08_dirtyReg (reg, false);
     }
 }
 
@@ -1759,7 +1758,7 @@
 static void
 rmwWithAop (char *rmwop, asmop * aop, int loffset)
 {
-  bool needpull = FALSE;
+  bool needpull = false;
   reg_info * reg;
 
   if (aop->stacked && aop->stk_aop[loffset])
@@ -1811,7 +1810,7 @@
         /* If the offset is small enough, fall through to default case */
       }
     default:
-      emitcode (rmwop, "%s", aopAdrStr (aop, loffset, FALSE));
+      emitcode (rmwop, "%s", aopAdrStr (aop, loffset, false));
       regalloc_dry_run_cost += ((aop->type == AOP_DIR || aop->type == AOP_IMMD) ? 2 : 3);
     }
 
@@ -1824,7 +1823,7 @@
 static void
 loadRegIndexed (reg_info * reg, int offset, char * rematOfs)
 {
-  bool needpula = FALSE;
+  bool needpula = false;
 
   /* The rematerialized offset may have a "#" prefix; skip over it */
   if (rematOfs && rematOfs[0] == '#')
@@ -1861,7 +1860,7 @@
           emitcode ("lda", ",x");
           regalloc_dry_run_cost++;
         }
-      hc08_dirtyReg (reg, FALSE);
+      hc08_dirtyReg (reg, false);
       break;
     case X_IDX:
       if (rematOfs)
@@ -1885,12 +1884,12 @@
           emitcode ("ldx", ",x");
           regalloc_dry_run_cost++;
         }
-      hc08_dirtyReg (reg, FALSE);
+      hc08_dirtyReg (reg, false);
       break;
     case H_IDX:
       needpula = pushRegIfUsed (hc08_reg_a);
       loadRegIndexed (hc08_reg_a, offset, rematOfs);
-      transferRegReg (hc08_reg_a, hc08_reg_h, TRUE);
+      transferRegReg (hc08_reg_a, hc08_reg_h, true);
       pullOrFreeReg (hc08_reg_a, needpula);
       break;
     case HX_IDX:
@@ -1898,7 +1897,7 @@
         {
           needpula = pushRegIfUsed (hc08_reg_a);
           loadRegIndexed (hc08_reg_a, offset, rematOfs);
-          pushReg (hc08_reg_a, TRUE);
+          pushReg (hc08_reg_a, true);
           loadRegIndexed (hc08_reg_x, offset+1, rematOfs);
           pullReg (hc08_reg_h);
           pullOrFreeReg (hc08_reg_a, needpula);
@@ -1925,7 +1924,7 @@
           emitcode ("ldhx", ",x");
           regalloc_dry_run_cost += 2;
         }
-      hc08_dirtyReg (reg, FALSE);
+      hc08_dirtyReg (reg, false);
       break;
     case XA_IDX:
       loadRegIndexed (hc08_reg_a, offset+1, rematOfs);
@@ -1943,7 +1942,7 @@
 static void
 storeRegIndexed (reg_info * reg, int offset, char * rematOfs)
 {
-  bool needpula = FALSE;
+  bool needpula = false;
 
   /* The rematerialized offset may have a "#" prefix; skip over it */
   if (rematOfs && rematOfs[0] == '#')
@@ -2006,7 +2005,7 @@
       break;
     case H_IDX:
       needpula = pushRegIfUsed (hc08_reg_a);
-      transferRegReg (hc08_reg_h, hc08_reg_a, TRUE);
+      transferRegReg (hc08_reg_h, hc08_reg_a, true);
       storeRegIndexed (hc08_reg_a, offset, rematOfs);
       pullOrFreeReg (hc08_reg_a, needpula);
       break;
@@ -2056,11 +2055,11 @@
         {
           for(i = 0; i < sym->nRegs; i++)
             if (sym->regs[i] == hc08_reg_h || sym->regs[i] == hc08_reg_x)
-              return TRUE;
+              return true;
         }
     }
 
-  return FALSE;
+  return false;
 }
 
 /*-----------------------------------------------------------------*/
@@ -2072,17 +2071,17 @@
   symbol *sym;
 
   if (!op || !IS_SYMOP (op))
-    return FALSE;
+    return false;
   sym = OP_SYMBOL (op);
   if (!sym->isspilt && sym->onStack)
-    return TRUE;
+    return true;
   if (sym->isspilt)
     {
       sym = sym->usl.spillLoc;
       if (sym && sym->onStack)
-        return TRUE;
+        return true;
     }
-  return FALSE;
+  return false;
 }
 
 /*-----------------------------------------------------------------*/
@@ -2212,7 +2211,7 @@
           if (!tsxUseful (ic))
             return aop;
           emitcode ("tsx", "");
-          hc08_dirtyReg (hc08_reg_hx, FALSE);
+          hc08_dirtyReg (hc08_reg_hx, false);
           hc08_reg_hx->aop = &tsxaop;
           _G.tsxStackPushes = _G.stackPushes;
         }
@@ -2311,13 +2310,13 @@
 
   /* if they have registers in common */
   if (!IS_SYMOP (op1) || !IS_SYMOP (op2))
-    return FALSE;
+    return false;
 
   sym1 = OP_SYMBOL (op1);
   sym2 = OP_SYMBOL (op2);
 
   if (sym1->nRegs == 0 || sym2->nRegs == 0)
-    return FALSE;
+    return false;
 
   for (i = 0; i < sym1->nRegs; i++)
     {
@@ -2331,11 +2330,11 @@
             continue;
 
           if (sym2->regs[j] == sym1->regs[i])
-            return TRUE;
+            return true;
         }
     }
 
-  return FALSE;
+  return false;
 }
 
 /*-----------------------------------------------------------------*/
@@ -2348,7 +2347,7 @@
 
   /* if they not symbols */
   if (!IS_SYMOP (op1) || !IS_SYMOP (op2))
-    return FALSE;
+    return false;
 
   sym1 = OP_SYMBOL (op1);
   sym2 = OP_SYMBOL (op2);
@@ -2356,24 +2355,24 @@
   /* if both are itemps & one is spilt
      and the other is not then false */
   if (IS_ITEMP (op1) && IS_ITEMP (op2) && sym1->isspilt != sym2->isspilt)
-    return FALSE;
+    return false;
 
   /* if they are the same */
   if (sym1 == sym2)
-    return TRUE;
+    return true;
 
   /* if they have the same rname */
   if (sym1->rname[0] && sym2->rname[0] && strcmp (sym1->rname, sym2->rname) == 0)
-    return TRUE;
+    return true;
 
   /* if left is a tmp & right is not */
   if (IS_ITEMP (op1) && !IS_ITEMP (op2) && sym1->isspilt && (sym1->usl.spillLoc == sym2))
-    return TRUE;
+    return true;
 
   if (IS_ITEMP (op2) && !IS_ITEMP (op1) && sym2->isspilt && sym1->level > 0 && (sym2->usl.spillLoc == sym1))
-    return TRUE;
+    return true;
 
-  return FALSE;
+  return false;
 }
 
 /*-----------------------------------------------------------------*/
@@ -2385,10 +2384,10 @@
   int i;
 
   if (aop1 == aop2)
-    return TRUE;
+    return true;
 
 //  if (aop1->size != aop2->size)
-//    return FALSE;
+//    return false;
 
   if (aop1->type == aop2->type)
     {
@@ -2397,19 +2396,19 @@
         case AOP_REG:
           for (i = 0; i < aop1->size; i++)
             if (aop1->aopu.aop_reg[i] != aop2->aopu.aop_reg[i])
-              return FALSE;
-          return TRUE;
+              return false;
+          return true;
         case AOP_SOF:
           return (aop1->aopu.aop_stk == aop2->aopu.aop_stk);
         case AOP_DIR:
           if (regalloc_dry_run)
-            return FALSE;
+            return false;
         case AOP_EXT:
           return (!strcmp (aop1->aopu.aop_dir, aop2->aopu.aop_dir));
         }
     }
 
-  return FALSE;
+  return false;
 }
 
 /*-----------------------------------------------------------------*/
@@ -2907,8 +2906,8 @@
 
 /*-----------------------------------------------------------------*/
 /* asmopToBool - Emit code to convert an asmop to a boolean.       */
-/*               Result left in A (0=FALSE, 1=TRUE) if ResultInA,  */
-/*               otherwise result left in Z flag (1=FALSE, 0=TRUE) */
+/*               Result left in A (0=false, 1=true) if ResultInA,  */
+/*               otherwise result left in Z flag (1=false, 0=true) */
 /*-----------------------------------------------------------------*/
 static void
 asmopToBool (asmop *aop, bool resultInA)
@@ -2916,8 +2915,8 @@
   bool isFloat; 
   symbol *tlbl, *tlbl1;
   int size = aop->size;
-  bool needpula = FALSE;
-  bool flagsonly = TRUE;
+  bool needpula = false;
+  bool flagsonly = true;
   int offset = size - 1;
   sym_link *type;
 
@@ -2953,7 +2952,7 @@
         {
           emitcode ("tsta", "");
           regalloc_dry_run_cost++;
-          flagsonly = FALSE;
+          flagsonly = false;
         }
       else if (IS_AOP_X (aop))
         {
@@ -2964,15 +2963,15 @@
         {
           if (hc08_reg_a->isFree)
             {
-              transferRegReg (hc08_reg_h, hc08_reg_a, FALSE);
+              transferRegReg (hc08_reg_h, hc08_reg_a, false);
               emitcode ("tsta", "");
               regalloc_dry_run_cost++;
-              flagsonly = FALSE;
+              flagsonly = false;
               hc08_freeReg (hc08_reg_a);
             }
           else if (hc08_reg_x->isFree)
             {
-              transferRegReg (hc08_reg_h, hc08_reg_x, FALSE);
+              transferRegReg (hc08_reg_h, hc08_reg_x, false);
               emitcode ("tstx", "");
               regalloc_dry_run_cost++;
               hc08_freeReg (hc08_reg_x);
@@ -3024,7 +3023,7 @@
           break;
         }
       if (resultInA)
-        needpula = FALSE;
+        needpula = false;
       else
         needpula = pushRegIfUsed (hc08_reg_a);
       loadRegFromAop (hc08_reg_a, aop, offset--);
@@ -3040,7 +3039,7 @@
       else
         {
           hc08_freeReg (hc08_reg_a);
-          flagsonly = FALSE;
+          flagsonly = false;
         }
       break;
     case AOP_LIT:
@@ -3058,11 +3057,11 @@
             {
               loadRegFromAop (hc08_reg_a, aop, 0);
               hc08_freeReg (hc08_reg_a);
-              flagsonly = FALSE;
+              flagsonly = false;
             }
           else
             {
-              emitcode ("tst", "%s", aopAdrStr (aop, 0, FALSE));
+              emitcode ("tst", "%s", aopAdrStr (aop, 0, false));
               regalloc_dry_run_cost += ((aop->type == AOP_DIR || aop->type == AOP_IMMD) ? 2 : 3);
             }
           break;
@@ -3074,15 +3073,15 @@
               loadRegFromAop (hc08_reg_a, aop, 0);
               accopWithAop ("ora", aop, 1);
               hc08_freeReg (hc08_reg_a);
-              flagsonly = FALSE;
+              flagsonly = false;
             }
           else
             {
               tlbl = (regalloc_dry_run ? 0 : newiTempLabel (NULL));
-              emitcode ("tst", "%s", aopAdrStr (aop, 0, FALSE));
+              emitcode ("tst", "%s", aopAdrStr (aop, 0, false));
               if (!regalloc_dry_run)
                 emitcode ("bne", "%05d$", labelKey2num (tlbl->key));
-              emitcode ("tst", "%s", aopAdrStr (aop, 1, FALSE));
+              emitcode ("tst", "%s", aopAdrStr (aop, 1, false));
               regalloc_dry_run_cost += 4;
               if (!regalloc_dry_run)
                 emitLabel (tlbl);
@@ -3105,7 +3104,7 @@
           else
             {
               hc08_freeReg (hc08_reg_a);
-              flagsonly = FALSE;
+              flagsonly = false;
             }
         }
     }
@@ -3122,7 +3121,7 @@
           emitBranch ("bra", tlbl);
           if (!regalloc_dry_run)
             emitLabel (tlbl1);
-          hc08_dirtyReg (hc08_reg_a, FALSE);
+          hc08_dirtyReg (hc08_reg_a, false);
           loadRegFromConst (hc08_reg_a, 1);
         }
       else
@@ -3132,7 +3131,7 @@
         }
       if (!regalloc_dry_run)
         emitLabel (tlbl);
-      hc08_dirtyReg (hc08_reg_a, FALSE);
+      hc08_dirtyReg (hc08_reg_a, false);
       hc08_useReg (hc08_reg_a);
     }
 }
@@ -3149,8 +3148,8 @@
   int offset = 0;
 
   /* if they are the same and not volatile */
-  if (operandsEqu (result, source) && !isOperandVolatile (result, FALSE) &&
-      !isOperandVolatile (source, FALSE))
+  if (operandsEqu (result, source) && !isOperandVolatile (result, false) &&
+      !isOperandVolatile (source, false))
     return;
 
   /* The source and destinations may be different size due to optimizations. */
@@ -3198,7 +3197,7 @@
       if (AOP (result)->aopu.aop_reg[0] == AOP (source)->aopu.aop_reg[1] &&
           AOP (result)->aopu.aop_reg[1] == AOP (source)->aopu.aop_reg[0])
         {
-          pushReg (AOP (source)->aopu.aop_reg[1], TRUE);
+          pushReg (AOP (source)->aopu.aop_reg[1], true);
           transferAopAop (AOP (source), 0, AOP (result), 0);
           pullReg (AOP (result)->aopu.aop_reg[1]);
         }
@@ -3238,12 +3237,12 @@
         {
           if (AOP_TYPE (source) == AOP_IDX && AOP_TYPE (result) == AOP_DIR)
             {
-              emitcode ("mov", ",x+,%s", aopAdrStr (AOP (result), offset, FALSE));
+              emitcode ("mov", ",x+,%s", aopAdrStr (AOP (result), offset, false));
               regalloc_dry_run_cost += 2;
             }
           else if (AOP_TYPE (source) == AOP_DIR && AOP_TYPE (result) == AOP_IDX)
             {
-              emitcode ("mov", "%s,x+", aopAdrStr (AOP (source), offset, FALSE));
+              emitcode ("mov", "%s,x+", aopAdrStr (AOP (source), offset, false));
               regalloc_dry_run_cost += 2;
             }
           else
@@ -3265,18 +3264,18 @@
   D (emitcode (";     genNot", ""));
 
   /* assign asmOps to operand & result */
-  aopOp (IC_LEFT (ic), ic, FALSE);
-  aopOp (IC_RESULT (ic), ic, TRUE);
+  aopOp (IC_LEFT (ic), ic, false);
+  aopOp (IC_RESULT (ic), ic, true);
   needpulla = pushRegIfSurv (hc08_reg_a);
-  asmopToBool (AOP (IC_LEFT (ic)), TRUE);
+  asmopToBool (AOP (IC_LEFT (ic)), true);
 
   emitcode ("eor", one);
   regalloc_dry_run_cost += 2;
-  storeRegToFullAop (hc08_reg_a, AOP (IC_RESULT (ic)), FALSE);
+  storeRegToFullAop (hc08_reg_a, AOP (IC_RESULT (ic)), false);
   pullOrFreeReg (hc08_reg_a, needpulla);
 
-  freeAsmop (IC_RESULT (ic), NULL, ic, TRUE);
-  freeAsmop (IC_LEFT (ic), NULL, ic, TRUE);
+  freeAsmop (IC_RESULT (ic), NULL, ic, true);
+  freeAsmop (IC_LEFT (ic), NULL, ic, true);
 }
 
 
@@ -3294,8 +3293,8 @@
   D (emitcode (";     genCpl", ""));
 
   /* assign asmOps to operand & result */
-  aopOp (IC_LEFT (ic), ic, FALSE);
-  aopOp (IC_RESULT (ic), ic, TRUE);
+  aopOp (IC_LEFT (ic), ic, false);
+  aopOp (IC_RESULT (ic), ic, true);
   size = AOP_SIZE (IC_RESULT (ic));
 
   if(AOP_TYPE (IC_LEFT (ic)) == AOP_REG && AOP_TYPE (IC_RESULT (ic)) == AOP_REG &&
@@ -3339,7 +3338,7 @@
     {
       bool needpullreg2 = (!size && AOP_TYPE (IC_RESULT (ic)) == AOP_REG && AOP (IC_RESULT (ic))->aopu.aop_reg[0] == reg || size && AOP_TYPE (IC_RESULT (ic)) == AOP_REG && AOP (IC_RESULT (ic))->aopu.aop_reg[1] == reg);
       if (needpullreg2)
-        pushReg (reg, TRUE);
+        pushReg (reg, true);
       loadRegFromAop (reg, AOP (IC_LEFT (ic)), offset);
       rmwWithReg ("com", reg);
       hc08_useReg (reg);
@@ -3353,8 +3352,8 @@
 
   /* release the aops */
 release:
-  freeAsmop (IC_RESULT (ic), NULL, ic, TRUE);
-  freeAsmop (IC_LEFT (ic), NULL, ic, TRUE);
+  freeAsmop (IC_RESULT (ic), NULL, ic, true);
+  freeAsmop (IC_LEFT (ic), NULL, ic, true);
 }
 
 /*-----------------------------------------------------------------*/
@@ -3402,8 +3401,8 @@
   D (emitcode (";     genUminus", ""));
 
   /* assign asmops */
-  aopOp (IC_LEFT (ic), ic, FALSE);
-  aopOp (IC_RESULT (ic), ic, TRUE);
+  aopOp (IC_LEFT (ic), ic, false);
+  aopOp (IC_RESULT (ic), ic, true);
 
   optype = operandType (IC_LEFT (ic));
 
@@ -3449,7 +3448,7 @@
         }
       needpula = pushRegIfSurv (hc08_reg_a);
       if (left1 == hc08_reg_a)
-        pushReg (left1, TRUE);
+        pushReg (left1, true);
 
       if (left0 == hc08_reg_a)
         rmwWithReg ("neg", hc08_reg_a);
@@ -3459,7 +3458,7 @@
           accopWithAop ("sub", AOP (IC_LEFT (ic)), 0);
         }
       if (result0 == hc08_reg_a || (result0 && result0 == left1))
-        pushReg (hc08_reg_a, TRUE);
+        pushReg (hc08_reg_a, true);
       else
         storeRegToAop (hc08_reg_a, AOP (IC_RESULT (ic)), 0);
       loadRegFromConst (hc08_reg_a, 0);
@@ -3467,7 +3466,7 @@
         {
           emitcode ("sbc","%d,s", (result0 == hc08_reg_a || (result0 && result0 == left1)) ? 2 : 1);
           regalloc_dry_run_cost += 3;
-          hc08_dirtyReg (hc08_reg_a, FALSE);
+          hc08_dirtyReg (hc08_reg_a, false);
         }
       else
         {
@@ -3498,8 +3497,8 @@
 
 release:
   /* release the aops */
-  freeAsmop (IC_RESULT (ic), NULL, ic, TRUE);
-  freeAsmop (IC_LEFT (ic), NULL, ic, FALSE);
+  freeAsmop (IC_RESULT (ic), NULL, ic, true);
+  freeAsmop (IC_LEFT (ic), NULL, ic, false);
 }
 
 /*-----------------------------------------------------------------*/
@@ -3535,7 +3534,7 @@
   for (i = A_IDX; i <= H_IDX; i++)
     {
       if (bitVectBitValue (ic->rSurv, i))
-        pushReg (hc08_regWithIdx (i), FALSE);
+        pushReg (hc08_regWithIdx (i), false);
     }
 }
 
@@ -3566,14 +3565,14 @@
   bool xIsFree = hc08_reg_x->isFree;
 
   hc08_useReg (hc08_reg_x);
-  aopOp (oper, ic, FALSE);
+  aopOp (oper, ic, false);
 
   if (AOP_TYPE (oper) == AOP_REG)
     {
       /* The operand is in registers; we can push them directly */
       while (size--)
         {
-          pushReg (AOP (oper)->aopu.aop_reg[offset++], TRUE);
+          pushReg (AOP (oper)->aopu.aop_reg[offset++], true);
         }
     }
   else if (hc08_reg_a->isFree)
@@ -3582,7 +3581,7 @@
       while (size--)
         {
           loadRegFromAop (hc08_reg_a, AOP (oper), offset++);
-          pushReg (hc08_reg_a, TRUE);
+          pushReg (hc08_reg_a, true);
         }
     }
   else
@@ -3590,7 +3589,7 @@
       /* A is not free. Adjust stack, preserve A, copy operand */
       /* into position on stack (using A), and restore original A */
       adjustStack (-size);
-      pushReg (hc08_reg_a, TRUE);
+      pushReg (hc08_reg_a, true);
       while (size--)
         {
           loadRegFromAop (hc08_reg_a, AOP (oper), offset++);
@@ -3600,7 +3599,7 @@
       pullReg (hc08_reg_a);
     }
 
-  freeAsmop (oper, NULL, ic, TRUE);
+  freeAsmop (oper, NULL, ic, true);
   if (xIsFree)
     hc08_freeReg (hc08_reg_x);
 }
@@ -3613,13 +3612,13 @@
 {
   int size = AOP_SIZE (oper);
   int offset = 0;
-  bool delayed_x = FALSE;
+  bool delayed_x = false;
   while (size--)
     {
       if (!offset && AOP_TYPE (oper) == AOP_REG && AOP_SIZE (oper) > 1 && AOP (oper)->aopu.aop_reg[0]->rIdx == X_IDX)
         {
-          pushReg (hc08_reg_a, TRUE);
-          delayed_x = TRUE;
+          pushReg (hc08_reg_a, true);
+          delayed_x = true;
         }
       else
         transferAopAop (hc08_aop_pass[offset], 0, AOP (oper), offset);
@@ -3651,13 +3650,13 @@
       if (OP_SYMBOL (IC_LEFT (ic))->isspilt)
         return;
 
-      aopOp (IC_LEFT (ic), ic, FALSE);
+      aopOp (IC_LEFT (ic), ic, false);
       size = AOP_SIZE (IC_LEFT (ic));
       /* push it on the stack */
       while (size--)
         {
           loadRegFromAop (hc08_reg_a, AOP (IC_LEFT (ic)), offset++);
-          pushReg (hc08_reg_a, TRUE);
+          pushReg (hc08_reg_a, true);
         }
       return;
     }
@@ -3669,18 +3668,18 @@
     saveRegisters (ic);
 
   /* then do the push */
-  aopOp (IC_LEFT (ic), ic, FALSE);
+  aopOp (IC_LEFT (ic), ic, false);
 
   // pushSide(IC_LEFT(ic), AOP_SIZE(IC_LEFT(ic)));
   size = AOP_SIZE (IC_LEFT (ic));
 
-//  l = aopGet (AOP (IC_LEFT (ic)), 0, FALSE, TRUE);
+//  l = aopGet (AOP (IC_LEFT (ic)), 0, false, true);
   if (AOP_TYPE (IC_LEFT (ic)) == AOP_IMMD || AOP_TYPE (IC_LEFT (ic)) == AOP_LIT ||IS_AOP_HX (AOP (IC_LEFT (ic))))
     {
       if ((size == 2) && hc08_reg_hx->isDead || IS_AOP_HX (AOP (IC_LEFT (ic))))
         {
           loadRegFromAop (hc08_reg_hx, AOP (IC_LEFT (ic)), 0);
-          pushReg (hc08_reg_hx, TRUE);
+          pushReg (hc08_reg_hx, true);
           goto release;
         }
     }
@@ -3688,7 +3687,7 @@
   if (AOP_TYPE (IC_LEFT (ic)) == AOP_REG)
     {
       while (size--)
-        pushReg (AOP (IC_LEFT (ic))->aopu.aop_reg[offset++], TRUE);
+        pushReg (AOP (IC_LEFT (ic))->aopu.aop_reg[offset++], true);
       goto release;
     }
 
@@ -3697,11 +3696,11 @@
 //      printf("loading %d\n", offset);
       loadRegFromAop (hc08_reg_a, AOP (IC_LEFT (ic)), offset++);
 //      printf("pushing \n");
-      pushReg (hc08_reg_a, TRUE);
+      pushReg (hc08_reg_a, true);
     }
 
 release:
-  freeAsmop (IC_LEFT (ic), NULL, ic, TRUE);
+  freeAsmop (IC_LEFT (ic), NULL, ic, true);
 }
 
 /*-----------------------------------------------------------------*/
@@ -3718,7 +3717,7 @@
   if (OP_SYMBOL (IC_LEFT (ic))->isspilt)
     return;
 
-  aopOp (IC_LEFT (ic), ic, FALSE);
+  aopOp (IC_LEFT (ic), ic, false);
   size = AOP_SIZE (IC_LEFT (ic));
   offset = size - 1;
   while (size--)
@@ -3727,7 +3726,7 @@
       storeRegToAop (hc08_reg_a, AOP (IC_LEFT (ic)), offset--);
     }
 
-  freeAsmop (IC_LEFT (ic), NULL, ic, TRUE);
+  freeAsmop (IC_LEFT (ic), NULL, ic, true);
 }
 
 /*-----------------------------------------------------------------*/
@@ -3752,7 +3751,7 @@
     {
       int size;
       /* case 1 or 2, this is fairly easy */
-      aopOp (IC_LEFT (send1), send1, FALSE);
+      aopOp (IC_LEFT (send1), send1, false);
       size = AOP_SIZE (IC_LEFT (send1));
       wassert (size <= 2);
       if (size == 1)
@@ -3761,7 +3760,7 @@
         }
       else if (AOP (IC_LEFT (send1))->type == AOP_REG)
         loadRegFromAop (hc08_reg_xa, AOP (IC_LEFT (send1)), 0);
-      else if (isOperandVolatile (IC_LEFT (send1), FALSE))
+      else if (isOperandVolatile (IC_LEFT (send1), false))
         {
           /* use msb to lsb order for volatile operands */
           loadRegFromAop (hc08_reg_x, AOP (IC_LEFT (send1)), 1);
@@ -3773,7 +3772,7 @@
           loadRegFromAop (hc08_reg_a, AOP (IC_LEFT (send1)), 0);
           loadRegFromAop (hc08_reg_x, AOP (IC_LEFT (send1)), 1);
         }
-      freeAsmop (IC_LEFT (send1), NULL, send1, TRUE);
+      freeAsmop (IC_LEFT (send1), NULL, send1, true);
     }
   else
     {
@@ -3785,14 +3784,14 @@
           send1 = send2;
           send2 = sic;
         }
-      aopOp (IC_LEFT (send1), send1, FALSE);
-      aopOp (IC_LEFT (send2), send2, FALSE);
+      aopOp (IC_LEFT (send1), send1, false);
+      aopOp (IC_LEFT (send2), send2, false);
       if (IS_AOP_X (AOP (IC_LEFT (send1))) && IS_AOP_A (AOP (IC_LEFT (send2))))
         {
           /* If the parameters' register assignment is exactly backwards */
           /* from what is needed, then swap the registers. */
-          pushReg (hc08_reg_a, FALSE);
-          transferRegReg (hc08_reg_x, hc08_reg_a, FALSE);
+          pushReg (hc08_reg_a, false);
+          transferRegReg (hc08_reg_x, hc08_reg_a, false);
           pullReg (hc08_reg_x);
         }
       else if (IS_AOP_A (AOP (IC_LEFT (send2))))
@@ -3805,8 +3804,8 @@
           loadRegFromAop (hc08_reg_a, AOP (IC_LEFT (send1)), 0);
           loadRegFromAop (hc08_reg_x, AOP (IC_LEFT (send2)), 0);
         }
-      freeAsmop (IC_LEFT (send2), NULL, send2, TRUE);
-      freeAsmop (IC_LEFT (send1), NULL, send1, TRUE);
+      freeAsmop (IC_LEFT (send2), NULL, send2, true);
+      freeAsmop (IC_LEFT (send1), NULL, send1, true);
     }
 }
 
@@ -3818,8 +3817,8 @@
 {
   sym_link *dtype;
   sym_link *etype;
-//  bool restoreBank = FALSE;
-//  bool swapBanks = FALSE;
+//  bool restoreBank = false;
+//  bool swapBanks = false;
 
   D (emitcode (";", "genCall"));
 
@@ -3858,8 +3857,8 @@
       regalloc_dry_run_cost += 3;
     }
 
-  hc08_dirtyReg (hc08_reg_a, FALSE);
-  hc08_dirtyReg (hc08_reg_hx, FALSE);
+  hc08_dirtyReg (hc08_reg_a, false);
+  hc08_dirtyReg (hc08_reg_hx, false);
 
   /* if we need assign a result value */
   if ((IS_ITEMP (IC_RESULT (ic)) &&
@@ -3869,12 +3868,12 @@
       if (operandSize (IC_RESULT (ic)) > 1)
         hc08_useReg (hc08_reg_x);
       _G.accInUse++;
-      aopOp (IC_RESULT (ic), ic, FALSE);
+      aopOp (IC_RESULT (ic), ic, false);
       _G.accInUse--;
 
       assignResultValue (IC_RESULT (ic));
 
-      freeAsmop (IC_RESULT (ic), NULL, ic, TRUE);
+      freeAsmop (IC_RESULT (ic), NULL, ic, true);
     }
 
   /* adjust the stack for parameters if required */
@@ -3953,8 +3952,8 @@
       regalloc_dry_run_cost += 3;
     }
 
-  hc08_dirtyReg (hc08_reg_a, FALSE);
-  hc08_dirtyReg (hc08_reg_hx, FALSE);
+  hc08_dirtyReg (hc08_reg_a, false);
+  hc08_dirtyReg (hc08_reg_hx, false);
 
   /* if we need assign a result value */
   if ((IS_ITEMP (IC_RESULT (ic)) &&
@@ -3964,12 +3963,12 @@
       if (operandSize (IC_RESULT (ic)) > 1)
         hc08_useReg (hc08_reg_x);
       _G.accInUse++;
-      aopOp (IC_RESULT (ic), ic, FALSE);
+      aopOp (IC_RESULT (ic), ic, false);
       _G.accInUse--;
 
       assignResultValue (IC_RESULT (ic));
 
-      freeAsmop (IC_RESULT (ic), NULL, ic, TRUE);
+      freeAsmop (IC_RESULT (ic), NULL, ic, true);
     }
 
   /* adjust the stack for parameters if required */
@@ -4017,7 +4016,7 @@
   const char *p = setFirstItem (options.excludeRegsSet);
 
   if (p == NULL || STRCASECMP (p, "none") == 0)
-    return FALSE;
+    return false;
 
 
   return isinSetWith (options.excludeRegsSet, s, regsCmp);
@@ -4063,9 +4062,8 @@
      save h  */
   if (IFFUNC_ISISR (sym->type))
     {
-
       if (!inExcludeList ("h"))
-        pushReg (hc08_reg_h, FALSE);
+        pushReg (hc08_reg_h, false);
     }
 
   /* For some cases it is worthwhile to perform a RECEIVE iCode */
@@ -4098,7 +4096,7 @@
           for (ofs = 0; ofs < rsymSize; ofs++)
             {
               reg_info *reg = hc08_aop_pass[ofs + (ric->argreg - 1)]->aopu.aop_reg[0];
-              pushReg (reg, TRUE);
+              pushReg (reg, true);
               if (reg->rIdx == A_IDX)
                 accIsFree = 1;
               stackAdjust--;
@@ -4123,8 +4121,8 @@
       if (!accIsFree)
         {
           /* Function was passed parameters, so make sure A is preserved */
-          pushReg (hc08_reg_a, FALSE);
-          pushReg (hc08_reg_a, FALSE);
+          pushReg (hc08_reg_a, false);
+          pushReg (hc08_reg_a, false);
           emitcode ("tpa", "");
           emitcode ("sta", "2,s");
           emitcode ("sei", "");
@@ -4136,7 +4134,7 @@
           /* No passed parameters, so A can be freely modified */
           emitcode ("tpa", "");
           regalloc_dry_run_cost++;
-          pushReg (hc08_reg_a, TRUE);
+          pushReg (hc08_reg_a, true);
           emitcode ("sei", "");
           regalloc_dry_run_cost++;
         }
@@ -4164,7 +4162,7 @@
       if (!IS_VOID (sym->type->next))
         {
           /* Function has return value, so make sure A is preserved */
-          pushReg (hc08_reg_a, FALSE);
+          pushReg (hc08_reg_a, false);
           emitcode ("lda", "2,s");
           emitcode ("tap", "");
           regalloc_dry_run_cost += 4;
@@ -4248,7 +4246,7 @@
 {
   int size, offset = 0;
 //  int pushed = 0;
-  bool delayed_x = FALSE;
+  bool delayed_x = false;
 
   D (emitcode (";     genRet", ""));
 
@@ -4259,7 +4257,7 @@
 
   /* we have something to return then
      move the return value into place */
-  aopOp (IC_LEFT (ic), ic, FALSE);
+  aopOp (IC_LEFT (ic), ic, false);
   size = AOP_SIZE (IC_LEFT (ic));
 
   if (AOP_TYPE (IC_LEFT (ic)) == AOP_LIT)
@@ -4279,8 +4277,8 @@
       /* Take care when swapping a and x */
       if (AOP_TYPE (IC_LEFT (ic)) == AOP_REG && size > 1 && AOP (IC_LEFT (ic))->aopu.aop_reg[0]->rIdx == X_IDX)
         {
-          delayed_x = TRUE;
-          pushReg (hc08_reg_x, TRUE);
+          delayed_x = true;
+          pushReg (hc08_reg_x, true);
         }
 
       offset = size - 1;
@@ -4295,7 +4293,7 @@
         pullReg (hc08_reg_a);
     }
 
-  freeAsmop (IC_LEFT (ic), NULL, ic, TRUE);
+  freeAsmop (IC_LEFT (ic), NULL, ic, true);
 
 jumpret:
   /* generate a jump to the return label
@@ -4373,7 +4371,7 @@
   /* if the right side is not a literal
      we cannot */
   if (AOP_TYPE (IC_RIGHT (ic)) != AOP_LIT)
-    return FALSE;
+    return false;
 
   icount = (unsigned int) ulFromVal (AOP (IC_RIGHT (ic))->aopu.aop_lit);
 
@@ -4388,11 +4386,11 @@
       loadRegFromAop (hc08_reg_hx, AOP (left), 0);
       emitcode ("aix", "#%d", icount);
       regalloc_dry_run_cost += 2;
-      hc08_dirtyReg (hc08_reg_hx, FALSE);
+      hc08_dirtyReg (hc08_reg_hx, false);
       storeRegToAop (hc08_reg_hx, AOP (result), 0);
       pullOrFreeReg (hc08_reg_h, needpulh);
       pullOrFreeReg (hc08_reg_x, needpulx);
-      return TRUE;
+      return true;
     }
   if (size == 1 && (IS_AOP_X (AOP (result)) && (!IS_AOP_A (AOP (left)) || hc08_reg_h->isDead) || IS_AOP_X (AOP (left)) && !IS_AOP_A (AOP (result)) && hc08_reg_x->isDead && hc08_reg_h->isDead))
     {
@@ -4403,16 +4401,16 @@
       regalloc_dry_run_cost += 2;
       storeRegToAop (hc08_reg_x, AOP (result), 0);
       pullOrFreeReg (hc08_reg_h, needpulh);
-      return TRUE;
+      return true;
     }
 
   DD (emitcode ("", "; icount = %d, sameRegs=%d", icount, sameRegs (AOP (left), AOP (result))));
 
   if ((icount > 255) || (icount < 0))
-    return FALSE;
+    return false;
 
   if (!sameRegs (AOP (left), AOP (result)))
-    return FALSE;
+    return false;
 
   D (emitcode (";     genPlusIncr", ""));
 
@@ -4423,7 +4421,7 @@
 
   if (icount == 1)
     {
-      needpula = FALSE;
+      needpula = false;
       rmwWithAop ("inc", AOP (result), 0);
       if (1 < size)
         emitBranch ("bne", tlbl);
@@ -4433,7 +4431,7 @@
       if (!IS_AOP_A (AOP (result)) && !IS_AOP_XA (AOP (result)))
         needpula = pushRegIfUsed (hc08_reg_a);
       else
-        needpula = FALSE;
+        needpula = false;
       loadRegFromAop (hc08_reg_a, AOP (result), 0);
       accopWithAop ("add", AOP (IC_RIGHT (ic)), 0);
       hc08_useReg (hc08_reg_a);
@@ -4454,7 +4452,7 @@
 
   pullOrFreeReg (hc08_reg_a, needpula);
 
-  return TRUE;
+  return true;
 }
 
 
@@ -4469,18 +4467,18 @@
   char *add;
   asmop *leftOp, *rightOp;
   bool needpulla;
-  bool earlystore = FALSE;
-  bool delayedstore = FALSE;
-  bool mayskip = TRUE;
-  bool skip = FALSE;
+  bool earlystore = false;
+  bool delayedstore = false;
+  bool mayskip = true;
+  bool skip = false;
 
   /* special cases :- */
 
   D (emitcode (";     genPlus", ""));
 
-  aopOp (IC_LEFT (ic), ic, FALSE);
-  aopOp (IC_RIGHT (ic), ic, FALSE);
-  aopOp (IC_RESULT (ic), ic, TRUE);
+  aopOp (IC_LEFT (ic), ic, false);
+  aopOp (IC_RIGHT (ic), ic, false);
+  aopOp (IC_RESULT (ic), ic, true);
 
   /* we want registers on the left and literals on the right */
   if ((AOP_TYPE (IC_LEFT (ic)) == AOP_LIT) || (AOP_TYPE (IC_RIGHT (ic)) == AOP_REG && !IS_AOP_WITH_A (AOP (IC_LEFT (ic)))))
@@ -4494,7 +4492,7 @@
 
   /* if I can do an increment instead
      of add then GOOD for ME */
-  if (genPlusIncr (ic) == TRUE)
+  if (genPlusIncr (ic) == true)
     goto release;
 
   DD (emitcode ("", ";  left size = %d", getDataSize (IC_LEFT (ic))));
@@ -4514,8 +4512,8 @@
 
   if(size > 1 && IS_AOP_AX (AOP (IC_LEFT (ic))))
     {
-      earlystore = TRUE;
-      pushReg (hc08_reg_a, TRUE);
+      earlystore = true;
+      pushReg (hc08_reg_a, true);
     }
 
   while (size--)
@@ -4527,15 +4525,15 @@
       if (!mayskip || AOP_TYPE (IC_RIGHT (ic)) != AOP_LIT || (byteOfVal (AOP (IC_RIGHT (ic))->aopu.aop_lit, offset) != 0x00) )
         {
           accopWithAop (add, rightOp, offset);
-          mayskip = FALSE;
-          skip = FALSE;
+          mayskip = false;
+          skip = false;
         }
       else
-        skip = TRUE;
+        skip = true;
       if (size && AOP_TYPE (IC_RESULT (ic)) == AOP_REG && AOP (IC_RESULT (ic))->aopu.aop_reg[offset]->rIdx == A_IDX)
         {
-          pushReg (hc08_reg_a, TRUE);
-          delayedstore = TRUE;
+          pushReg (hc08_reg_a, true);
+          delayedstore = true;
         }
       else
         storeRegToAop (hc08_reg_a, AOP (IC_RESULT (ic)), offset);
@@ -4551,9 +4549,9 @@
  wassert (!earlystore || !delayedstore);
 
 release:
-  freeAsmop (IC_RESULT (ic), NULL, ic, TRUE);
-  freeAsmop (IC_RIGHT (ic), NULL, ic, TRUE);
-  freeAsmop (IC_LEFT (ic), NULL, ic, TRUE);
+  freeAsmop (IC_RESULT (ic), NULL, ic, true);
+  freeAsmop (IC_RIGHT (ic), NULL, ic, true);
+  freeAsmop (IC_LEFT (ic), NULL, ic, true);
 }
 
 /*-----------------------------------------------------------------*/
@@ -4578,7 +4576,7 @@
   /* if the right side is not a literal
      we cannot */
   if (AOP_TYPE (IC_RIGHT (ic)) != AOP_LIT)
-    return FALSE;
+    return false;
 
   icount = (unsigned int) ulFromVal (AOP (IC_RIGHT (ic))->aopu.aop_lit);
   if ((IS_AOP_HX (AOP (left)) || IS_AOP_HX (AOP (result)) ||
@@ -4591,21 +4589,21 @@
       loadRegFromAop (hc08_reg_hx, AOP (left), 0);
       emitcode ("aix", "#%d", -(int) icount);
       regalloc_dry_run_cost += 2;
-      hc08_dirtyReg (hc08_reg_hx, FALSE);
+      hc08_dirtyReg (hc08_reg_hx, false);
       storeRegToAop (hc08_reg_hx, AOP (result), 0);
       pullOrFreeReg (hc08_reg_h, needpulh);
       pullOrFreeReg (hc08_reg_x, needpulx);
-      return TRUE;
+      return true;
     }
 
   if ((icount > 1) || (icount < 0))
-    return FALSE;
+    return false;
 
   if (!sameRegs (AOP (left), AOP (result)))
-    return FALSE;
+    return false;
 
   if (size != 1)
-    return FALSE;
+    return false;
 
   D (emitcode (";     genMinusDec", ""));
 
@@ -4613,7 +4611,7 @@
 
   rmwWithAop ("dec", AOP (result), 0);
 
-  return TRUE;
+  return true;
 }
 
 /*-----------------------------------------------------------------*/
@@ -4630,7 +4628,7 @@
           emitcode ("rola", "");
           emitcode ("clra", "");
           emitcode ("sbc", zero);
-          hc08_dirtyReg (hc08_reg_a, FALSE);
+          hc08_dirtyReg (hc08_reg_a, false);
           regalloc_dry_run_cost += 4;
           while (size--)
             storeRegToAop (hc08_reg_a, AOP (result), offset++);
@@ -4651,21 +4649,21 @@
   char *sub;
   int size, offset = 0;
   bool needpulla;
-  bool earlystore = FALSE;
-  bool delayedstore = FALSE;
+  bool earlystore = false;
+  bool delayedstore = false;
 
   asmop *leftOp, *rightOp;
 
   D (emitcode (";     genMinus", ""));
 
-  aopOp (IC_LEFT (ic), ic, FALSE);
-  aopOp (IC_RIGHT (ic), ic, FALSE);
-  aopOp (IC_RESULT (ic), ic, TRUE);
+  aopOp (IC_LEFT (ic), ic, false);
+  aopOp (IC_RIGHT (ic), ic, false);
+  aopOp (IC_RESULT (ic), ic, true);
 
   /* special cases :- */
   /* if I can do an decrement instead
      of subtract then GOOD for ME */
-  if (genMinusDec (ic) == TRUE)
+  if (genMinusDec (ic) == true)
     goto release;
 
   aopOpExtToIdx (AOP (IC_RESULT (ic)), AOP (IC_LEFT (ic)), AOP (IC_RIGHT (ic)));
@@ -4685,15 +4683,15 @@
       loadRegFromAop (hc08_reg_a, rightOp, offset);
       accopWithAop (sub, leftOp, offset);
       accopWithMisc ("nega", "");
-      storeRegToAop (hc08_reg_a, AOP (IC_RESULT (ic)), offset++);
+      storeRegToAop (hc08_reg_a, AOP (IC_RESULT (ic)), offset);
       pullOrFreeReg (hc08_reg_a, needpulla);
       goto release;
     }
 
   if (size > 1 && (IS_AOP_AX (AOP (IC_LEFT (ic))) || IS_AOP_AX (AOP (IC_RIGHT (ic)))))
     {
-      earlystore = TRUE;
-      pushReg (hc08_reg_a, TRUE);
+      earlystore = true;
+      pushReg (hc08_reg_a, true);
     }
 
   while (size--)
@@ -4704,10 +4702,10 @@
         pullReg (hc08_reg_a);
       if (AOP_TYPE (IC_RIGHT (ic)) == AOP_REG && AOP (IC_RIGHT (ic))->aopu.aop_reg[offset]->rIdx == A_IDX)
         {
-          pushReg (hc08_reg_a, TRUE);
+          pushReg (hc08_reg_a, true);
           loadRegFromAop (hc08_reg_a, leftOp, offset);
           emitcode (sub, "1, s");
-          hc08_dirtyReg (hc08_reg_a, FALSE);
+          hc08_dirtyReg (hc08_reg_a, false);
           regalloc_dry_run_cost += 3;
           pullNull (1);
         }
@@ -4718,8 +4716,8 @@
         }
       if (size && AOP_TYPE (IC_RESULT (ic)) == AOP_REG && AOP (IC_RESULT (ic))->aopu.aop_reg[offset]->rIdx == A_IDX)
         {
-          pushReg (hc08_reg_a, TRUE);
-          delayedstore = TRUE;
+          pushReg (hc08_reg_a, true);
+          delayedstore = true;
         }
       else
         storeRegToAop (hc08_reg_a, AOP (IC_RESULT (ic)), offset);
@@ -4733,9 +4731,9 @@
   wassert (!earlystore || !delayedstore);
 
 release:
-  freeAsmop (IC_LEFT (ic), NULL, ic, (RESULTONSTACK (ic) ? FALSE : TRUE));
-  freeAsmop (IC_RIGHT (ic), NULL, ic, (RESULTONSTACK (ic) ? FALSE : TRUE));
-  freeAsmop (IC_RESULT (ic), NULL, ic, TRUE);
+  freeAsmop (IC_LEFT (ic), NULL, ic, (RESULTONSTACK (ic) ? false : true));
+  freeAsmop (IC_RIGHT (ic), NULL, ic, (RESULTONSTACK (ic) ? false : true));
+  freeAsmop (IC_RESULT (ic), NULL, ic, true);
 }
 
 
@@ -4749,7 +4747,7 @@
   /* sym_link *opetype = operandType (result); */
   symbol *tlbl1, *tlbl2, *tlbl3, *tlbl4;
   int size = AOP_SIZE (result);
-  bool negLiteral = FALSE;
+  bool negLiteral = false;
   bool lUnsigned, rUnsigned;
   bool needpulla, needpullx;
 
@@ -4804,8 +4802,8 @@
       loadRegFromAop (hc08_reg_x, AOP (right), 0);
       emitcode ("mul", "");
       regalloc_dry_run_cost++;
-      hc08_dirtyReg (hc08_reg_xa, FALSE);
-      storeRegToFullAop (hc08_reg_xa, AOP (result), TRUE);
+      hc08_dirtyReg (hc08_reg_xa, false);
+      storeRegToFullAop (hc08_reg_xa, AOP (result), true);
       hc08_freeReg (hc08_reg_xa);
       pullOrFreeReg (hc08_reg_x, needpullx);
       pullOrFreeReg (hc08_reg_a, needpulla);
@@ -4824,11 +4822,11 @@
       loadRegFromAop (hc08_reg_a, AOP (left), 0);
       emitcode ("ldx", "#0x%02x", val < 0 ? -val : val);
       regalloc_dry_run_cost += 2;
-      hc08_dirtyReg (hc08_reg_x, FALSE);
+      hc08_dirtyReg (hc08_reg_x, false);
 
       emitcode ("mul", "");
       regalloc_dry_run_cost++;
-      hc08_dirtyReg (hc08_reg_xa, FALSE);
+      hc08_dirtyReg (hc08_reg_xa, false);
 
       if (val < 0)
         {
@@ -4841,7 +4839,7 @@
           rmwWithReg ("neg", hc08_reg_x);
         }
 
-      storeRegToFullAop (hc08_reg_xa, AOP (result), TRUE);
+      storeRegToFullAop (hc08_reg_xa, AOP (result), true);
       hc08_freeReg (hc08_reg_xa);
       pullOrFreeReg (hc08_reg_x, needpullx);
       pullOrFreeReg (hc08_reg_a, needpulla);
@@ -4877,14 +4875,14 @@
         {
           emitcode ("ldx", "#0x%02x", -val);
           regalloc_dry_run_cost += 2;
-          negLiteral = TRUE;
+          negLiteral = true;
         }
       else
         {
           emitcode ("ldx", "#0x%02x", val);
           regalloc_dry_run_cost += 2;
         }
-      hc08_dirtyReg (hc08_reg_x, FALSE);
+      hc08_dirtyReg (hc08_reg_x, false);
       hc08_useReg (hc08_reg_x);
     }
   else
@@ -4907,7 +4905,7 @@
 
   emitcode ("mul", "");
   regalloc_dry_run_cost++;
-  hc08_dirtyReg (hc08_reg_xa, FALSE);
+  hc08_dirtyReg (hc08_reg_xa, false);
 
   tlbl3 = (regalloc_dry_run ? 0 : newiTempLabel (NULL));
   emitcode ("dec", "1,s");
@@ -4928,7 +4926,7 @@
   if (!regalloc_dry_run)
     emitLabel (tlbl3);
   adjustStack (1);
-  storeRegToFullAop (hc08_reg_xa, AOP (result), TRUE);
+  storeRegToFullAop (hc08_reg_xa, AOP (result), true);
   
   pullOrFreeReg (hc08_reg_x, needpullx);
   pullOrFreeReg (hc08_reg_a, needpulla);
@@ -4947,9 +4945,9 @@
   D (emitcode (";     genMult", ""));
 
   /* assign the amsops */
-  aopOp (left, ic, FALSE);
-  aopOp (right, ic, FALSE);
-  aopOp (result, ic, TRUE);
+  aopOp (left, ic, false);
+  aopOp (right, ic, false);
+  aopOp (result, ic, true);
 
   /* special cases first */
   /* if both are of size == 1 */
@@ -4967,9 +4965,9 @@
   assert (0);
 
 release:
-  freeAsmop (left, NULL, ic, (RESULTONSTACK (ic) ? FALSE : TRUE));
-  freeAsmop (right, NULL, ic, (RESULTONSTACK (ic) ? FALSE : TRUE));
-  freeAsmop (result, NULL, ic, TRUE);
+  freeAsmop (left, NULL, ic, (RESULTONSTACK (ic) ? false : true));
+  freeAsmop (right, NULL, ic, (RESULTONSTACK (ic) ? false : true));
+  freeAsmop (result, NULL, ic, true);
 }
 
 /*-----------------------------------------------------------------*/
@@ -4983,8 +4981,8 @@
   bool lUnsigned, rUnsigned;
   bool runtimeSign, compiletimeSign;
   bool needpulla, needpullh;
-  bool needpullx = FALSE;
-  bool preload_a = FALSE;
+  bool needpullx = false;
+  bool preload_a = false;
 
   lUnsigned = SPEC_USIGN (getSpec (operandType (left)));
   rUnsigned = SPEC_USIGN (getSpec (operandType (right)));
@@ -5003,8 +5001,8 @@
       t = left;
       left = right;
       right = t;
-      pushReg (hc08_reg_a, FALSE);
-      transferRegReg (hc08_reg_x, hc08_reg_a, FALSE);
+      pushReg (hc08_reg_a, false);
+      transferRegReg (hc08_reg_x, hc08_reg_a, false);
       pullReg (hc08_reg_x);
     }
 
@@ -5026,9 +5024,9 @@
       loadRegFromConst (hc08_reg_h, 0);
       emitcode ("div", "");
       regalloc_dry_run_cost++;
-      hc08_dirtyReg (hc08_reg_a, FALSE);
-      hc08_dirtyReg (hc08_reg_h, FALSE);
-      storeRegToFullAop (hc08_reg_a, AOP (result), FALSE);
+      hc08_dirtyReg (hc08_reg_a, false);
+      hc08_dirtyReg (hc08_reg_h, false);
+      storeRegToFullAop (hc08_reg_a, AOP (result), false);
       pullOrFreeReg (hc08_reg_x, needpullx);
       pullOrFreeReg (hc08_reg_h, needpullh);
       pullOrFreeReg (hc08_reg_a, needpulla);
@@ -5041,9 +5039,9 @@
 
   /* let's see what's needed: */
   /* apply negative sign during runtime */
-  runtimeSign = FALSE;
+  runtimeSign = false;
   /* negative sign from literals */
-  compiletimeSign = FALSE;
+  compiletimeSign = false;
 
   if (!lUnsigned)
     {
@@ -5052,11 +5050,11 @@
           /* signed literal */
           signed char val = (char) ulFromVal (AOP (left)->aopu.aop_lit);
           if (val < 0)
-            compiletimeSign = TRUE;
+            compiletimeSign = true;
         }
       else
         /* signed but not literal */
-        runtimeSign = TRUE;
+        runtimeSign = true;
     }
 
   if (!rUnsigned)
@@ -5066,11 +5064,11 @@
           /* signed literal */
           signed char val = (char) ulFromVal (AOP (right)->aopu.aop_lit);
           if (val < 0)
-            compiletimeSign ^= TRUE;
+            compiletimeSign ^= true;
         }
       else
         /* signed but not literal */
-        runtimeSign = TRUE;
+        runtimeSign = true;
     }
 
   /* initialize the runtime sign */
@@ -5085,7 +5083,7 @@
   if (IS_AOP_X (AOP (left)))
     {
       loadRegFromAop (hc08_reg_a, AOP (left), 0);
-      preload_a = TRUE;
+      preload_a = true;
     }
 
   /* save the signs of the operands */
@@ -5103,7 +5101,7 @@
           emitcode ("ldx", "#0x%02x", (unsigned char) val);
           regalloc_dry_run_cost += 2;
         }
-      hc08_dirtyReg (hc08_reg_x, FALSE);
+      hc08_dirtyReg (hc08_reg_x, false);
       hc08_useReg (hc08_reg_x);
     }
   else                          /* ! literal */
@@ -5137,7 +5135,7 @@
           emitcode ("lda", "#0x%02x", (unsigned char) val);
           regalloc_dry_run_cost += 2;
         }
-      hc08_dirtyReg (hc08_reg_a, FALSE);
+      hc08_dirtyReg (hc08_reg_a, false);
       hc08_useReg (hc08_reg_a);
     }
   else                          /* ! literal */
@@ -5161,9 +5159,9 @@
   loadRegFromConst (hc08_reg_h, 0);
   emitcode ("div", "");
   regalloc_dry_run_cost++;
-  hc08_dirtyReg (hc08_reg_x, FALSE);
-  hc08_dirtyReg (hc08_reg_a, FALSE);
-  hc08_dirtyReg (hc08_reg_h, FALSE);
+  hc08_dirtyReg (hc08_reg_x, false);
+  hc08_dirtyReg (hc08_reg_a, false);
+  hc08_dirtyReg (hc08_reg_h, false);
 
   if (runtimeSign || compiletimeSign)
     {
@@ -5197,7 +5195,7 @@
     }
   else
     {
-      storeRegToFullAop (hc08_reg_a, AOP (result), FALSE);
+      storeRegToFullAop (hc08_reg_a, AOP (result), false);
     }
 
   pullOrFreeReg (hc08_reg_x, needpullx);
@@ -5218,9 +5216,9 @@
   D (emitcode (";     genDiv", ""));
 
   /* assign the amsops */
-  aopOp (left, ic, FALSE);
-  aopOp (right, ic, FALSE);
-  aopOp (result, ic, TRUE);
+  aopOp (left, ic, false);
+  aopOp (right, ic, false);
+  aopOp (result, ic, true);
 
   /* special cases first */
   /* if both are of size == 1 */
@@ -5233,9 +5231,9 @@
   /* should have been converted to function call */
   assert (0);
 release:
-  freeAsmop (left, NULL, ic, (RESULTONSTACK (ic) ? FALSE : TRUE));
-  freeAsmop (right, NULL, ic, (RESULTONSTACK (ic) ? FALSE : TRUE));
-  freeAsmop (result, NULL, ic, TRUE);
+  freeAsmop (left, NULL, ic, (RESULTONSTACK (ic) ? false : true));
+  freeAsmop (right, NULL, ic, (RESULTONSTACK (ic) ? false : true));
+  freeAsmop (result, NULL, ic, true);
 }
 
 /*-----------------------------------------------------------------*/
@@ -5249,8 +5247,8 @@
   bool lUnsigned, rUnsigned;
   bool runtimeSign, compiletimeSign;
   bool needpulla, needpullh;
-  bool needpullx = FALSE;
-  bool preload_a = FALSE;
+  bool needpullx = false;
+  bool preload_a = false;
 
   lUnsigned = SPEC_USIGN (getSpec (operandType (left)));
   rUnsigned = SPEC_USIGN (getSpec (operandType (right)));
@@ -5271,8 +5269,8 @@
       t = left;
       left = right;
       right = t;
-      pushReg (hc08_reg_a, FALSE);
-      transferRegReg (hc08_reg_x, hc08_reg_a, FALSE);
+      pushReg (hc08_reg_a, false);
+      transferRegReg (hc08_reg_x, hc08_reg_a, false);
       pullReg (hc08_reg_x);
     }
 
@@ -5293,9 +5291,9 @@
       emitcode ("div", "");
       regalloc_dry_run_cost++;
       hc08_freeReg (hc08_reg_x);
-      hc08_dirtyReg (hc08_reg_a, TRUE);
-      hc08_dirtyReg (hc08_reg_h, FALSE);
-      storeRegToFullAop (hc08_reg_h, AOP (result), FALSE);
+      hc08_dirtyReg (hc08_reg_a, true);
+      hc08_dirtyReg (hc08_reg_h, false);
+      storeRegToFullAop (hc08_reg_h, AOP (result), false);
       pullOrFreeReg (hc08_reg_x, needpullx);
       pullOrFreeReg (hc08_reg_h, needpullh);
       pullOrFreeReg (hc08_reg_a, needpulla);
@@ -5306,7 +5304,7 @@
   if (IS_AOP_X (AOP (left)))
     {
       loadRegFromAop (hc08_reg_a, AOP (left), 0);
-      preload_a = TRUE;
+      preload_a = true;
     }
 
   if (AOP_TYPE (right) == AOP_LIT)
@@ -5323,7 +5321,7 @@
           emitcode ("ldx", "#0x%02x", (unsigned char) val);
           regalloc_dry_run_cost += 2;
         }
-      hc08_dirtyReg (hc08_reg_x, FALSE);
+      hc08_dirtyReg (hc08_reg_x, false);
       hc08_useReg (hc08_reg_x);
     }
   else                          /* ! literal */
@@ -5343,9 +5341,9 @@
 
   /* let's see what's needed: */
   /* apply negative sign during runtime */
-  runtimeSign = FALSE;
+  runtimeSign = false;
   /* negative sign from literals */
-  compiletimeSign = FALSE;
+  compiletimeSign = false;
 
   /* sign adjust left side */
   if (AOP_TYPE (left) == AOP_LIT)
@@ -5354,7 +5352,7 @@
 
       if (!lUnsigned && val < 0)
         {
-          compiletimeSign = TRUE;       /* set sign flag */
+          compiletimeSign = true;       /* set sign flag */
           emitcode ("lda", "#0x%02x", -val);
           regalloc_dry_run_cost += 2;
         }
@@ -5363,7 +5361,7 @@
           emitcode ("lda", "#0x%02x", (unsigned char) val);
           regalloc_dry_run_cost += 2;
         }
-      hc08_dirtyReg (hc08_reg_a, FALSE);
+      hc08_dirtyReg (hc08_reg_a, false);
       hc08_useReg (hc08_reg_a);
     }
   else                          /* ! literal */
@@ -5375,7 +5373,7 @@
         }
       else
         {
-          runtimeSign = TRUE;
+          runtimeSign = true;
           pushConst (0);
 
           if (!preload_a)
@@ -5396,12 +5394,12 @@
   emitcode ("div", "");
   regalloc_dry_run_cost++;
   hc08_freeReg (hc08_reg_x);
-  hc08_dirtyReg (hc08_reg_a, TRUE);
-  hc08_dirtyReg (hc08_reg_h, FALSE);
+  hc08_dirtyReg (hc08_reg_a, true);
+  hc08_dirtyReg (hc08_reg_h, false);
 
   if (runtimeSign || compiletimeSign)
     {
-      transferRegReg (hc08_reg_h, hc08_reg_a, TRUE);
+      transferRegReg (hc08_reg_h, hc08_reg_a, true);
       if (runtimeSign)
         {
           tlbl3 = (regalloc_dry_run ? 0 : newiTempLabel (NULL));
@@ -5432,7 +5430,7 @@
     }
   else
     {
-      storeRegToFullAop (hc08_reg_h, AOP (result), FALSE);
+      storeRegToFullAop (hc08_reg_h, AOP (result), false);
     }
 
   pullOrFreeReg (hc08_reg_x, needpullx);
@@ -5453,9 +5451,9 @@
   D (emitcode (";     genMod", ""));
 
   /* assign the amsops */
-  aopOp (left, ic, FALSE);
-  aopOp (right, ic, FALSE);
-  aopOp (result, ic, TRUE);
+  aopOp (left, ic, false);
+  aopOp (right, ic, false);
+  aopOp (result, ic, true);
 
   /* special cases first */
   /* if both are of size == 1 */
@@ -5469,9 +5467,9 @@
   assert (0);
 
 release:
-  freeAsmop (left, NULL, ic, (RESULTONSTACK (ic) ? FALSE : TRUE));
-  freeAsmop (right, NULL, ic, (RESULTONSTACK (ic) ? FALSE : TRUE));
-  freeAsmop (result, NULL, ic, TRUE);
+  freeAsmop (left, NULL, ic, (RESULTONSTACK (ic) ? false : true));
+  freeAsmop (right, NULL, ic, (RESULTONSTACK (ic) ? false : true));
+  freeAsmop (result, NULL, ic, true);
 }
 
 /*-----------------------------------------------------------------*/
@@ -5655,7 +5653,7 @@
   unsigned long long lit = 0ull;
   char *sub;
   symbol *jlbl = NULL;
-  bool needpulla = FALSE;
+  bool needpulla = false;
 
   opcode = ic->op;
 
@@ -5674,9 +5672,9 @@
     }
 
   /* assign the amsops */
-  aopOp (left, ic, FALSE);
-  aopOp (right, ic, FALSE);
-  aopOp (result, ic, TRUE);
+  aopOp (left, ic, false);
+  aopOp (right, ic, false);
+  aopOp (result, ic, true);
 
   /* need register operand on left, prefer literal operand on right */
   if ((AOP_TYPE (right) == AOP_REG) || AOP_TYPE (left) == AOP_LIT)
@@ -5716,7 +5714,7 @@
       && ((AOP_TYPE (right) == AOP_LIT) || ((AOP_TYPE (right) == AOP_DIR || IS_S08 && AOP_TYPE (right) == AOP_EXT) && (AOP_SIZE (right) == 2))) && (hc08_reg_h->isDead && hc08_reg_x->isDead || IS_AOP_HX (AOP (left))))
     {
       loadRegFromAop (hc08_reg_hx, AOP (left), 0);
-      emitcode ("cphx", "%s", aopAdrStr (AOP (right), 0, TRUE));
+      emitcode ("cphx", "%s", aopAdrStr (AOP (right), 0, true));
       regalloc_dry_run_cost += (AOP_TYPE (right) == AOP_DIR ? 2 : 3);
       hc08_freeReg (hc08_reg_hx);
     }
@@ -5743,7 +5741,7 @@
               opcode = exchangedCmp (opcode);
             }
 
-          if ((AOP_TYPE (right) == AOP_LIT) && !isOperandVolatile (left, FALSE))
+          if ((AOP_TYPE (right) == AOP_LIT) && !isOperandVolatile (left, false))
             {
               lit = ullFromVal (AOP (right)->aopu.aop_lit);
               while ((size > 1) && (((lit >> (8 * offset)) & 0xff) == 0))
@@ -5758,7 +5756,7 @@
         {
           if (AOP_TYPE (right) == AOP_REG && AOP(right)->aopu.aop_reg[offset]->rIdx == A_IDX)
             {
-              pushReg (hc08_reg_a, TRUE);
+              pushReg (hc08_reg_a, true);
               loadRegFromAop (hc08_reg_a, AOP (left), offset);
               emitcode (sub, "1, s");
               regalloc_dry_run_cost += 3;
@@ -5774,8 +5772,8 @@
           sub = "sbc";
         }
     }
-  freeAsmop (right, NULL, ic, FALSE);
-  freeAsmop (left, NULL, ic, FALSE);
+  freeAsmop (right, NULL, ic, false);
+  freeAsmop (left, NULL, ic, false);
 
   if (ifx)
     {
@@ -5784,7 +5782,7 @@
 
       pullOrFreeReg (hc08_reg_a, needpulla);
 
-      freeAsmop (result, NULL, ic, TRUE);
+      freeAsmop (result, NULL, ic, true);
 
       inst = branchInstCmp (opcode, sign);
       emitBranch (inst, tlbl);
@@ -5808,14 +5806,14 @@
       emitBranch ("bra", tlbl2);
       if (!regalloc_dry_run)
         emitLabel (tlbl1);
-      hc08_dirtyReg (hc08_reg_a, FALSE);
+      hc08_dirtyReg (hc08_reg_a, false);
       loadRegFromConst (hc08_reg_a, 1);
       if (!regalloc_dry_run)
         emitLabel (tlbl2);
-      hc08_dirtyReg (hc08_reg_a, FALSE);
-      storeRegToFullAop (hc08_reg_a, AOP (result), FALSE);
+      hc08_dirtyReg (hc08_reg_a, false);
+      storeRegToFullAop (hc08_reg_a, AOP (result), false);
       pullOrFreeReg (hc08_reg_a, needpulla);
-      freeAsmop (result, NULL, ic, TRUE);
+      freeAsmop (result, NULL, ic, true);
     }
 }
 
@@ -5831,7 +5829,7 @@
   symbol *jlbl = NULL;
   symbol *tlbl_NE = NULL;
   symbol *tlbl_EQ = NULL;
-  bool needpulla = FALSE;
+  bool needpulla = false;
 
   opcode = ic->op;
 
@@ -5842,9 +5840,9 @@
   right = IC_RIGHT (ic);
 
   /* assign the amsops */
-  aopOp (left, ic, FALSE);
-  aopOp (right, ic, FALSE);
-  aopOp (result, ic, TRUE);
+  aopOp (left, ic, false);
+  aopOp (right, ic, false);
+  aopOp (result, ic, true);
 
   /* need register operand on left, prefer literal operand on right */
   if ((AOP_TYPE (right) == AOP_REG) || AOP_TYPE (left) == AOP_LIT)
@@ -5876,7 +5874,7 @@
       && ((AOP_TYPE (right) == AOP_LIT) || ((AOP_TYPE (right) == AOP_DIR || IS_S08 && AOP_TYPE (right) == AOP_EXT) && (AOP_SIZE (right) == 2))) && hc08_reg_h->isDead && hc08_reg_x->isDead)
     {
       loadRegFromAop (hc08_reg_hx, AOP (left), 0);
-      emitcode ("cphx", "%s", aopAdrStr (AOP (right), 0, TRUE));
+      emitcode ("cphx", "%s", aopAdrStr (AOP (right), 0, true));
       regalloc_dry_run_cost += (AOP_TYPE (right) == AOP_DIR ? 2 : 3);
       hc08_freeReg (hc08_reg_hx);
     }
@@ -5897,7 +5895,7 @@
               accopWithAop ("cmp", AOP (right), offset);
               if (!(AOP_TYPE (left) == AOP_REG && AOP (left)->aopu.aop_reg[offset]->rIdx == A_IDX))
                 pullOrFreeReg (hc08_reg_a, needpulla);
-              needpulla = FALSE;
+              needpulla = false;
             }
           if (size)
             {
@@ -5907,17 +5905,17 @@
                 tlbl_NE = newiTempLabel (NULL);
               emitBranch ("bne", tlbl_NE);
               pullOrFreeReg (hc08_reg_a, needpulla);
-              needpulla = FALSE;
+              needpulla = false;
             }
           offset++;
           }
     }
-  freeAsmop (right, NULL, ic, FALSE);
-  freeAsmop (left, NULL, ic, FALSE);
+  freeAsmop (right, NULL, ic, false);
+  freeAsmop (left, NULL, ic, false);
 
   if (ifx)
     {
-      freeAsmop (result, NULL, ic, TRUE);
+      freeAsmop (result, NULL, ic, true);
 
       if (opcode == EQ_OP)
         {
@@ -5956,12 +5954,12 @@
           emitBranch ("beq", tlbl_EQ);
           if (tlbl_NE)
             emitLabel (tlbl_NE);
-          hc08_dirtyReg (hc08_reg_a, FALSE);
+          hc08_dirtyReg (hc08_reg_a, false);
           loadRegFromConst (hc08_reg_a, 0);
           emitBranch ("bra", tlbl);
           if (!regalloc_dry_run)
             emitLabel (tlbl_EQ);
-          hc08_dirtyReg (hc08_reg_a, FALSE);
+          hc08_dirtyReg (hc08_reg_a, false);
           loadRegFromConst (hc08_reg_a, 1);
         }
       else
@@ -5973,16 +5971,16 @@
           emitBranch ("bra", tlbl);
           if (!regalloc_dry_run)
             emitLabel (tlbl_NE);
-          hc08_dirtyReg (hc08_reg_a, FALSE);
+          hc08_dirtyReg (hc08_reg_a, false);
           loadRegFromConst (hc08_reg_a, 1);
         }
 
       if (!regalloc_dry_run)
         emitLabel (tlbl);
-      hc08_dirtyReg (hc08_reg_a, FALSE);
-      storeRegToFullAop (hc08_reg_a, AOP (result), FALSE);
+      hc08_dirtyReg (hc08_reg_a, false);
+      storeRegToFullAop (hc08_reg_a, AOP (result), false);
       pullOrFreeReg (hc08_reg_a, needpulla);
-      freeAsmop (result, NULL, ic, TRUE);
+      freeAsmop (result, NULL, ic, true);
     }
 }
 
@@ -6045,37 +6043,37 @@
   /* note here that && operations that are in an
      if statement are taken away by backPatchLabels
      only those used in arthmetic operations remain */
-  aopOp ((left = IC_LEFT (ic)), ic, FALSE);
-  aopOp ((right = IC_RIGHT (ic)), ic, FALSE);
-  aopOp ((result = IC_RESULT (ic)), ic, FALSE);
+  aopOp ((left = IC_LEFT (ic)), ic, false);
+  aopOp ((right = IC_RIGHT (ic)), ic, false);
+  aopOp ((result = IC_RESULT (ic)), ic, false);
 
   tlbl = (regalloc_dry_run ? 0 : newiTempLabel (NULL));
   tlbl0 = (regalloc_dry_run ? 0 : newiTempLabel (NULL));
 
   needpulla = pushRegIfSurv (hc08_reg_a);
-  asmopToBool (AOP (left), FALSE);
+  asmopToBool (AOP (left), false);
   emitBranch ("beq", tlbl0);
-  asmopToBool (AOP (right), FALSE);
+  asmopToBool (AOP (right), false);
   emitBranch ("beq", tlbl0);
   loadRegFromConst (hc08_reg_a, 1);
   emitBranch ("bra", tlbl);
   if (!regalloc_dry_run)
     emitLabel (tlbl0);
-  hc08_dirtyReg (hc08_reg_a, FALSE);
+  hc08_dirtyReg (hc08_reg_a, false);
   loadRegFromConst (hc08_reg_a, 0);
   if (!regalloc_dry_run)
     emitLabel (tlbl);
-  hc08_dirtyReg (hc08_reg_a, FALSE);
+  hc08_dirtyReg (hc08_reg_a, false);
 
   hc08_useReg (hc08_reg_a);
   hc08_freeReg (hc08_reg_a);
 
-  storeRegToFullAop (hc08_reg_a, AOP (result), FALSE);
+  storeRegToFullAop (hc08_reg_a, AOP (result), false);
   pullOrFreeReg(hc08_reg_a, needpulla);
 
-  freeAsmop (left, NULL, ic, (RESULTONSTACK (ic) ? FALSE : TRUE));
-  freeAsmop (right, NULL, ic, (RESULTONSTACK (ic) ? FALSE : TRUE));
-  freeAsmop (result, NULL, ic, TRUE);
+  freeAsmop (left, NULL, ic, (RESULTONSTACK (ic) ? false : true));
+  freeAsmop (right, NULL, ic, (RESULTONSTACK (ic) ? false : true));
+  freeAsmop (result, NULL, ic, true);
 }
 
 
@@ -6094,37 +6092,37 @@
   /* note here that || operations that are in an
      if statement are taken away by backPatchLabels
      only those used in arthmetic operations remain */
-  aopOp ((left = IC_LEFT (ic)), ic, FALSE);
-  aopOp ((right = IC_RIGHT (ic)), ic, FALSE);
-  aopOp ((result = IC_RESULT (ic)), ic, FALSE);
+  aopOp ((left = IC_LEFT (ic)), ic, false);
+  aopOp ((right = IC_RIGHT (ic)), ic, false);
+  aopOp ((result = IC_RESULT (ic)), ic, false);
 
   tlbl = (regalloc_dry_run ? 0 : newiTempLabel (NULL));
   tlbl0 = (regalloc_dry_run ? 0 : newiTempLabel (NULL));
 
   needpulla = pushRegIfSurv (hc08_reg_a);
-  asmopToBool (AOP (left), FALSE);
+  asmopToBool (AOP (left), false);
   emitBranch ("bne", tlbl0);
-  asmopToBool (AOP (right), FALSE);
+  asmopToBool (AOP (right), false);
   emitBranch ("bne", tlbl0);
   loadRegFromConst (hc08_reg_a, 0);
   emitBranch ("bra", tlbl);
   if (!regalloc_dry_run)
     emitLabel (tlbl0);
-  hc08_dirtyReg (hc08_reg_a, FALSE);
+  hc08_dirtyReg (hc08_reg_a, false);
   loadRegFromConst (hc08_reg_a, 1);
   if (!regalloc_dry_run)
     emitLabel (tlbl);
-  hc08_dirtyReg (hc08_reg_a, FALSE);
+  hc08_dirtyReg (hc08_reg_a, false);
 
   hc08_useReg (hc08_reg_a);
   hc08_freeReg (hc08_reg_a);
 
-  storeRegToFullAop (hc08_reg_a, AOP (result), FALSE);
+  storeRegToFullAop (hc08_reg_a, AOP (result), false);
   pullOrFreeReg(hc08_reg_a, needpulla);
 
-  freeAsmop (left, NULL, ic, (RESULTONSTACK (ic) ? FALSE : TRUE));
-  freeAsmop (right, NULL, ic, (RESULTONSTACK (ic) ? FALSE : TRUE));
-  freeAsmop (result, NULL, ic, TRUE);
+  freeAsmop (left, NULL, ic, (RESULTONSTACK (ic) ? false : true));
+  freeAsmop (right, NULL, ic, (RESULTONSTACK (ic) ? false : true));
+  freeAsmop (result, NULL, ic, true);
 }
 
 /*-----------------------------------------------------------------*/
@@ -6164,14 +6162,14 @@
   unsigned long long litinv;
   int bitpos = -1;
   unsigned char bytemask;
-  bool needpulla = FALSE;
-  bool earlystore = FALSE;
+  bool needpulla = false;
+  bool earlystore = false;
 
   D (emitcode (";     genAnd", ""));
 
-  aopOp ((left = IC_LEFT (ic)), ic, FALSE);
-  aopOp ((right = IC_RIGHT (ic)), ic, FALSE);
-  aopOp ((result = IC_RESULT (ic)), ic, TRUE);
+  aopOp ((left = IC_LEFT (ic)), ic, false);
+  aopOp ((right = IC_RIGHT (ic)), ic, false);
+  aopOp ((result = IC_RESULT (ic)), ic, true);
 
 #ifdef DEBUG_TYPE
   DD (emitcode ("", "; Type res[%d] = l[%d]&r[%d]", AOP_TYPE (result), AOP_TYPE (left), AOP_TYPE (right)));
@@ -6218,7 +6216,7 @@
       if (IC_TRUE (ifx))
         {
           if (!regalloc_dry_run)
-            emitcode ("brclr", "#%d,%s,%05d$", bitpos & 7, aopAdrStr (AOP (left), bitpos >> 3, FALSE), labelKey2num ((tlbl->key)));
+            emitcode ("brclr", "#%d,%s,%05d$", bitpos & 7, aopAdrStr (AOP (left), bitpos >> 3, false), labelKey2num ((tlbl->key)));
           regalloc_dry_run_cost += 3;
           emitBranch ("jmp", IC_TRUE (ifx));
           if (!regalloc_dry_run)
@@ -6229,23 +6227,23 @@
       else
         {
           if (!regalloc_dry_run)
-            emitcode ("brset", "#%d,%s,%05d$", bitpos & 7, aopAdrStr (AOP (left), bitpos >> 3, FALSE), labelKey2num ((tlbl->key)));
+            emitcode ("brset", "#%d,%s,%05d$", bitpos & 7, aopAdrStr (AOP (left), bitpos >> 3, false), labelKey2num ((tlbl->key)));
           regalloc_dry_run_cost += 3;
           emitBranch ("jmp", IC_FALSE (ifx));
           if (!regalloc_dry_run)
             emitLabel (tlbl);
         }
-      ifx->generated = TRUE;
+      ifx->generated = true;
       goto release;
     }
 
-  if (AOP_TYPE (result) == AOP_CRY && size > 1 && (isOperandVolatile (left, FALSE) || isOperandVolatile (right, FALSE)))
+  if (AOP_TYPE (result) == AOP_CRY && size > 1 && (isOperandVolatile (left, false) || isOperandVolatile (right, false)))
     {
       needpulla = pushRegIfSurv (hc08_reg_a);
 
       /* this generates ugly code, but meets volatility requirements */
       loadRegFromConst (hc08_reg_a, 0);
-      pushReg (hc08_reg_a, TRUE);
+      pushReg (hc08_reg_a, true);
 
       offset = 0;
       while (size--)
@@ -6346,7 +6344,7 @@
       if (sameRegs (AOP (IC_LEFT (ic)), AOP (IC_RESULT (ic))) && (AOP_TYPE (left) == AOP_DIR) && isLiteralBit (litinv))
         {
           bitpos = isLiteralBit (litinv) - 1;
-          emitcode ("bclr", "#%d,%s", bitpos & 7, aopAdrStr (AOP (left), bitpos >> 3, FALSE));
+          emitcode ("bclr", "#%d,%s", bitpos & 7, aopAdrStr (AOP (left), bitpos >> 3, false));
           regalloc_dry_run_cost += 2;
           goto release;
         }
@@ -6357,8 +6355,8 @@
   offset = 0;
   if (size >= 2 && IS_AOP_AX (AOP (left)))
     {
-      pushReg (hc08_reg_a, TRUE);
-      earlystore = TRUE;
+      pushReg (hc08_reg_a, true);
+      earlystore = true;
     }
   while (size--)
     {
@@ -6368,7 +6366,7 @@
         pullReg (hc08_reg_a);
       if (AOP_TYPE (right) == AOP_LIT && bytemask == 0)
         {
-          if (isOperandVolatile (left, FALSE))
+          if (isOperandVolatile (left, false))
             {
               loadRegFromAop (hc08_reg_a, AOP (left), offset);
               hc08_freeReg (hc08_reg_a);
@@ -6388,8 +6386,8 @@
         }
       if (AOP_TYPE (result) == AOP_REG && size && AOP (result)->aopu.aop_reg[offset]->rIdx == A_IDX)
         {
-          pushReg (hc08_reg_a, TRUE);
-          needpulla = TRUE;
+          pushReg (hc08_reg_a, true);
+          needpulla = true;
         }
       offset++;
     }
@@ -6397,9 +6395,9 @@
   pullOrFreeReg (hc08_reg_a, needpulla);
 
 release:
-  freeAsmop (left, NULL, ic, (RESULTONSTACK (ic) ? FALSE : TRUE));
-  freeAsmop (right, NULL, ic, (RESULTONSTACK (ic) ? FALSE : TRUE));
-  freeAsmop (result, NULL, ic, TRUE);
+  freeAsmop (left, NULL, ic, (RESULTONSTACK (ic) ? false : true));
+  freeAsmop (right, NULL, ic, (RESULTONSTACK (ic) ? false : true));
+  freeAsmop (result, NULL, ic, true);
 }
 
 /*-----------------------------------------------------------------*/
@@ -6412,14 +6410,14 @@
   int size, offset = 0;
   unsigned long long lit = 0ull;
   unsigned char bytemask;
-  bool needpulla = FALSE;
-  bool earlystore = FALSE;
+  bool needpulla = false;
+  bool earlystore = false;
 
   D (emitcode (";     genOr", ""));
 
-  aopOp ((left = IC_LEFT (ic)), ic, FALSE);
-  aopOp ((right = IC_RIGHT (ic)), ic, FALSE);
-  aopOp ((result = IC_RESULT (ic)), ic, TRUE);
+  aopOp ((left = IC_LEFT (ic)), ic, false);
+  aopOp ((right = IC_RIGHT (ic)), ic, false);
+  aopOp ((result = IC_RESULT (ic)), ic, true);
 
 #ifdef DEBUG_TYPE
   DD (emitcode ("", "; Type res[%d] = l[%d]&r[%d]", AOP_TYPE (result), AOP_TYPE (left), AOP_TYPE (right)));
@@ -6447,13 +6445,13 @@
 
   size = (AOP_SIZE (left) >= AOP_SIZE (right)) ? AOP_SIZE (left) : AOP_SIZE (right);
 
-  if (AOP_TYPE (result) == AOP_CRY && size > 1 && (isOperandVolatile (left, FALSE) || isOperandVolatile (right, FALSE)))
+  if (AOP_TYPE (result) == AOP_CRY && size > 1 && (isOperandVolatile (left, false) || isOperandVolatile (right, false)))
     {
       needpulla = pushRegIfSurv (hc08_reg_a);
 
       /* this generates ugly code, but meets volatility requirements */
       loadRegFromConst (hc08_reg_a, 0);
-      pushReg (hc08_reg_a, TRUE);
+      pushReg (hc08_reg_a, true);
 
       offset = 0;
       while (size--)
@@ -6532,7 +6530,7 @@
       (AOP_TYPE (right) == AOP_LIT) && isLiteralBit (lit) && (AOP_TYPE (left) == AOP_DIR))
     {
       int bitpos = isLiteralBit (lit) - 1;
-      emitcode ("bset", "#%d,%s", bitpos & 7, aopAdrStr (AOP (left), bitpos >> 3, FALSE));
+      emitcode ("bset", "#%d,%s", bitpos & 7, aopAdrStr (AOP (left), bitpos >> 3, false));
       regalloc_dry_run_cost += 2;
       goto release;
     }
@@ -6542,8 +6540,8 @@
   offset = 0;
   if (size >= 2 && IS_AOP_AX (AOP (left)))
     {
-      pushReg (hc08_reg_a, TRUE);
-      earlystore = TRUE;
+      pushReg (hc08_reg_a, true);
+      earlystore = true;
     }
   while (size--)
     {
@@ -6553,7 +6551,7 @@
         pullReg (hc08_reg_a);
       if (AOP_TYPE (right) == AOP_LIT && bytemask == 0xff)
         {
-          if (isOperandVolatile (left, FALSE))
+          if (isOperandVolatile (left, false))
             {
               loadRegFromAop (hc08_reg_a, AOP (left), offset);
               hc08_freeReg (hc08_reg_a);
@@ -6573,8 +6571,8 @@
         }
       if (AOP_TYPE (result) == AOP_REG && size && AOP (result)->aopu.aop_reg[offset]->rIdx == A_IDX)
         {
-          pushReg (hc08_reg_a, TRUE);
-          needpulla = TRUE;
+          pushReg (hc08_reg_a, true);
+          needpulla = true;
         }
       offset++;
     }
@@ -6582,9 +6580,9 @@
   pullOrFreeReg (hc08_reg_a, needpulla);
 
 release:
-  freeAsmop (left, NULL, ic, (RESULTONSTACK (ic) ? FALSE : TRUE));
-  freeAsmop (right, NULL, ic, (RESULTONSTACK (ic) ? FALSE : TRUE));
-  freeAsmop (result, NULL, ic, TRUE);
+  freeAsmop (left, NULL, ic, (RESULTONSTACK (ic) ? false : true));
+  freeAsmop (right, NULL, ic, (RESULTONSTACK (ic) ? false : true));
+  freeAsmop (result, NULL, ic, true);
 }
 
 /*-----------------------------------------------------------------*/
@@ -6595,14 +6593,14 @@
 {
   operand *left, *right, *result;
   int size, offset = 0;
-  bool needpulla = FALSE;
-  bool earlystore = FALSE;
+  bool needpulla = false;
+  bool earlystore = false;
 
   D (emitcode (";     genXor", ""));
 
-  aopOp ((left = IC_LEFT (ic)), ic, FALSE);
-  aopOp ((right = IC_RIGHT (ic)), ic, FALSE);
-  aopOp ((result = IC_RESULT (ic)), ic, TRUE);
+  aopOp ((left = IC_LEFT (ic)), ic, false);
+  aopOp ((right = IC_RIGHT (ic)), ic, false);
+  aopOp ((result = IC_RESULT (ic)), ic, true);
 
 #ifdef DEBUG_TYPE
   DD (emitcode ("", "; Type res[%d] = l[%d]&r[%d]", AOP_TYPE (result), AOP_TYPE (left), AOP_TYPE (right)));
@@ -6671,8 +6669,8 @@
   offset = 0;
   if (size >= 2 && IS_AOP_AX (AOP (left)))
     {
-      pushReg (hc08_reg_a, TRUE);
-      earlystore = TRUE;
+      pushReg (hc08_reg_a, true);
+      earlystore = true;
     }
   while (size--)
     {
@@ -6683,8 +6681,8 @@
       storeRegToAop (hc08_reg_a, AOP (result), offset);
       if (AOP_TYPE (result) == AOP_REG && size && AOP (result)->aopu.aop_reg[offset]->rIdx == A_IDX)
         {
-          pushReg (hc08_reg_a, TRUE);
-          needpulla = TRUE;
+          pushReg (hc08_reg_a, true);
+          needpulla = true;
         }
       hc08_freeReg (hc08_reg_a);
       offset++;
@@ -6694,16 +6692,16 @@
 
 release:
 
-  freeAsmop (left, NULL, ic, (RESULTONSTACK (ic) ? FALSE : TRUE));
-  freeAsmop (right, NULL, ic, (RESULTONSTACK (ic) ? FALSE : TRUE));
-  freeAsmop (result, NULL, ic, TRUE);
+  freeAsmop (left, NULL, ic, (RESULTONSTACK (ic) ? false : true));
+  freeAsmop (right, NULL, ic, (RESULTONSTACK (ic) ? false : true));
+  freeAsmop (result, NULL, ic, true);
 }
 
 static const char *
 expand_symbols (iCode * ic, const char *inlin)
 {
   const char *begin = NULL, *p = inlin;
-  bool inIdent = FALSE;
+  bool inIdent = false;
   struct dbuf_s dbuf;
 
   dbuf_init (&dbuf, 128);
@@ -6732,8 +6730,8 @@
                 }
               else
                 {
-                  asmop *aop = aopForSym (ic, sym, FALSE);
-                  const char *l = aopAdrStr (aop, aop->size - 1, TRUE);
+                  asmop *aop = aopForSym (ic, sym, false);
+                  const char *l = aopAdrStr (aop, aop->size - 1, true);
 
                   if ('#' == *l)
                     l++;
@@ -6754,7 +6752,7 @@
       else if ('_' == *p)
         {
           /* begin of identifier */
-          inIdent = TRUE;
+          inIdent = true;
           if (begin)
             dbuf_append (&dbuf, begin, p - begin);
           begin = p++;
@@ -6781,7 +6779,7 @@
 {
   char *buf, *bp, *begin;
   const char *expanded;
-  bool inComment = FALSE;
+  bool inComment = false;
 
   D (emitcode (";", "genInline"));
 
@@ -6795,13 +6793,13 @@
       switch (*bp)
         {
         case ';':
-          inComment = TRUE;
+          inComment = true;
           ++bp;
           break;
 
         case '\x87':
         case '\n':
-          inComment = FALSE;
+          inComment = false;
           *bp++ = '\0';
           expanded = expand_symbols (ic, begin);
           emitcode (expanded, NULL);
@@ -6847,8 +6845,8 @@
 {
   operand *left, *result;
   int size, offset = 0;
-  bool needpula = FALSE;
-  bool resultInA = FALSE;
+  bool needpula = false;
+  bool resultInA = false;
   char *shift;
 
   D (emitcode (";     genRRC", ""));
@@ -6856,11 +6854,11 @@
   /* rotate right with carry */
   left = IC_LEFT (ic);
   result = IC_RESULT (ic);
-  aopOp (left, ic, FALSE);
-  aopOp (result, ic, FALSE);
+  aopOp (left, ic, false);
+  aopOp (result, ic, false);
 
   if ((AOP_TYPE (result) == AOP_REG) && (AOP (result)->aopu.aop_reg[0]->rIdx == A_IDX))
-    resultInA = TRUE;
+    resultInA = true;
 
   size = AOP_SIZE (result);
   offset = size - 1;
@@ -6888,8 +6886,8 @@
 
   if ((!hc08_reg_a->isFree) || resultInA)
     {
-      pushReg (hc08_reg_a, TRUE);
-      needpula = TRUE;
+      pushReg (hc08_reg_a, true);
+      needpula = true;
     }
 
   /* now we need to put the carry into the
@@ -6898,14 +6896,14 @@
   emitcode ("clra", "");
   emitcode ("rora", "");
   regalloc_dry_run_cost += 2;
-  hc08_dirtyReg (hc08_reg_a, FALSE);
+  hc08_dirtyReg (hc08_reg_a, false);
   if (resultInA)
     {
       emitcode ("ora", "1,s");
       pullNull (1);
       regalloc_dry_run_cost += 3;
-      hc08_dirtyReg (hc08_reg_a, FALSE);
-      needpula = FALSE;
+      hc08_dirtyReg (hc08_reg_a, false);
+      needpula = false;
     }
   else
     accopWithAop ("ora", AOP (result), offset);
@@ -6913,8 +6911,8 @@
 
   pullOrFreeReg (hc08_reg_a, needpula);
 
-  freeAsmop (left, NULL, ic, TRUE);
-  freeAsmop (result, NULL, ic, TRUE);
+  freeAsmop (left, NULL, ic, true);
+  freeAsmop (result, NULL, ic, true);
 }
 
 /*-----------------------------------------------------------------*/
@@ -6926,19 +6924,19 @@
   operand *left, *result;
   int size, offset = 0;
   char *shift;
-  bool resultInA = FALSE;
-  bool needpula = FALSE;
+  bool resultInA = false;
+  bool needpula = false;
 
   D (emitcode (";     genRLC", ""));
 
   /* rotate right with carry */
   left = IC_LEFT (ic);
   result = IC_RESULT (ic);
-  aopOp (left, ic, FALSE);
-  aopOp (result, ic, FALSE);
+  aopOp (left, ic, false);
+  aopOp (result, ic, false);
 
   if ((AOP_TYPE (result) == AOP_REG) && (AOP (result)->aopu.aop_reg[0]->rIdx == A_IDX))
-    resultInA = TRUE;
+    resultInA = true;
 
   size = AOP_SIZE (result);
   offset = 0;
@@ -6966,8 +6964,8 @@
 
   if ((!hc08_reg_a->isFree) || resultInA)
     {
-      pushReg (hc08_reg_a, TRUE);
-      needpula = TRUE;
+      pushReg (hc08_reg_a, true);
+      needpula = true;
     }
 
   /* now we need to put the carry into the
@@ -6976,14 +6974,14 @@
   emitcode ("clra", "");
   emitcode ("rola", "");
   regalloc_dry_run_cost += 2;
-  hc08_dirtyReg (hc08_reg_a, FALSE);
+  hc08_dirtyReg (hc08_reg_a, false);
   if (resultInA)
     {
       emitcode ("ora", "1,s");
       pullNull (1);
       regalloc_dry_run_cost += 3;
-      hc08_dirtyReg (hc08_reg_a, FALSE);
-      needpula = FALSE;
+      hc08_dirtyReg (hc08_reg_a, false);
+      needpula = false;
     }
   else
     accopWithAop ("ora", AOP (result), offset);
@@ -6991,8 +6989,8 @@
 
   pullOrFreeReg (hc08_reg_a, needpula);
 
-  freeAsmop (left, NULL, ic, TRUE);
-  freeAsmop (result, NULL, ic, TRUE);
+  freeAsmop (left, NULL, ic, true);
+  freeAsmop (result, NULL, ic, true);
 }
 
 /*-----------------------------------------------------------------*/
@@ -7010,9 +7008,9 @@
   left = IC_LEFT (ic);
   right = IC_RIGHT (ic);
   result = IC_RESULT (ic);
-  aopOp (left, ic, FALSE);
-  aopOp (right, ic, FALSE);
-  aopOp (result, ic, FALSE);
+  aopOp (left, ic, false);
+  aopOp (right, ic, false);
+  aopOp (result, ic, false);
 
   shCount = (int) ulFromVal (AOP (IC_RIGHT (ic))->aopu.aop_lit);
 
@@ -7025,7 +7023,7 @@
     {
       emitcode ("and", "#0x%02x", 1 << shCount);
       regalloc_dry_run_cost += 2;
-      hc08_dirtyReg (hc08_reg_a, FALSE);
+      hc08_dirtyReg (hc08_reg_a, false);
     }
   else
     {
@@ -7067,14 +7065,14 @@
           regalloc_dry_run_cost += 3;
           break;
         }
-      hc08_dirtyReg (hc08_reg_a, FALSE);
-      storeRegToFullAop (hc08_reg_a, AOP (result), FALSE);
+      hc08_dirtyReg (hc08_reg_a, false);
+      storeRegToFullAop (hc08_reg_a, AOP (result), false);
     }
   pullOrFreeReg (hc08_reg_a, needpulla);
 
-  freeAsmop (result, NULL, ic, TRUE);
-  freeAsmop (right, NULL, ic, TRUE);
-  freeAsmop (left, NULL, ic, TRUE);
+  freeAsmop (result, NULL, ic, true);
+  freeAsmop (right, NULL, ic, true);
+  freeAsmop (left, NULL, ic, true);
 }
 
 /*-----------------------------------------------------------------*/
@@ -7091,16 +7089,16 @@
   left = IC_LEFT (ic);
   right = IC_RIGHT (ic);
   result = IC_RESULT (ic);
-  aopOp (left, ic, FALSE);
-  aopOp (right, ic, FALSE);
-  aopOp (result, ic, FALSE);
+  aopOp (left, ic, false);
+  aopOp (right, ic, false);
+  aopOp (result, ic, false);
 
   offset = (int) ulFromVal (AOP (right)->aopu.aop_lit) / 8;
   transferAopAop (AOP (left), offset, AOP (result), 0);
 
-  freeAsmop (result, NULL, ic, TRUE);
-  freeAsmop (right, NULL, ic, TRUE);
-  freeAsmop (left, NULL, ic, TRUE);
+  freeAsmop (result, NULL, ic, true);
+  freeAsmop (right, NULL, ic, true);
+  freeAsmop (left, NULL, ic, true);
 }
 
 /*-----------------------------------------------------------------*/
@@ -7117,17 +7115,17 @@
   left = IC_LEFT (ic);
   right = IC_RIGHT (ic);
   result = IC_RESULT (ic);
-  aopOp (left, ic, FALSE);
-  aopOp (right, ic, FALSE);
-  aopOp (result, ic, FALSE);
+  aopOp (left, ic, false);
+  aopOp (right, ic, false);
+  aopOp (result, ic, false);
 
   offset = (int) ulFromVal (AOP (right)->aopu.aop_lit) / 8;
   transferAopAop (AOP (left), offset + 1, AOP (result), 1);
   transferAopAop (AOP (left), offset, AOP (result), 0);
 
-  freeAsmop (result, NULL, ic, TRUE);
-  freeAsmop (right, NULL, ic, TRUE);
-  freeAsmop (left, NULL, ic, TRUE);
+  freeAsmop (result, NULL, ic, true);
+  freeAsmop (right, NULL, ic, true);
+  freeAsmop (left, NULL, ic, true);
 }
 
 /*-----------------------------------------------------------------*/
@@ -7143,8 +7141,8 @@
 
   left = IC_LEFT (ic);
   result = IC_RESULT (ic);
-  aopOp (left, ic, FALSE);
-  aopOp (result, ic, FALSE);
+  aopOp (left, ic, false);
+  aopOp (result, ic, false);
 
   switch (AOP_SIZE (left))
     {
@@ -7153,7 +7151,7 @@
       loadRegFromAop (hc08_reg_a, AOP (left), 0);
       emitcode ("nsa", "");
       regalloc_dry_run_cost++;
-      hc08_dirtyReg (hc08_reg_a, FALSE);
+      hc08_dirtyReg (hc08_reg_a, false);
       storeRegToAop (hc08_reg_a, AOP (result), 0);
       pullOrFreeReg (hc08_reg_a, needpulla);
       break;
@@ -7164,7 +7162,7 @@
       if (AOP_TYPE (result) == AOP_REG && AOP_TYPE (left) == AOP_REG)
         {
           if (AOP (result)->aopu.aop_reg[1] != AOP (left)->aopu.aop_reg[0])
-            pushReg (AOP (left)->aopu.aop_reg[0], TRUE);
+            pushReg (AOP (left)->aopu.aop_reg[0], true);
           storeRegToAop (AOP (left)->aopu.aop_reg[1], AOP (result), 0);
           if (AOP (result)->aopu.aop_reg[1] != AOP (left)->aopu.aop_reg[0])
             pullReg (AOP (result)->aopu.aop_reg[1]);
@@ -7185,11 +7183,11 @@
         }
       break;
     default:
-      wassertl (FALSE, "unsupported SWAP operand size");
+      wassertl (false, "unsupported SWAP operand size");
     }
 
-  freeAsmop (left, NULL, ic, TRUE);
-  freeAsmop (result, NULL, ic, TRUE);
+  freeAsmop (left, NULL, ic, true);
+  freeAsmop (result, NULL, ic, true);
 }
 
 #if 0
@@ -7385,7 +7383,7 @@
   if (shCount >= 8)
     {
       AccLsh (shCount - 8);
-      transferRegReg (hc08_reg_a, hc08_reg_x, FALSE);
+      transferRegReg (hc08_reg_a, hc08_reg_x, false);
       loadRegFromConst (hc08_reg_a, 0);
       return;
     }
@@ -7405,7 +7403,7 @@
        */
       rmwWithReg ("lsr", hc08_reg_x);
       rmwWithReg ("ror", hc08_reg_a);
-      transferRegReg (hc08_reg_a, hc08_reg_x, FALSE);
+      transferRegReg (hc08_reg_a, hc08_reg_x, false);
       loadRegFromConst (hc08_reg_a, 0);
       rmwWithReg ("ror", hc08_reg_a);
       return;
@@ -7450,7 +7448,7 @@
       loadRegFromConst (hc08_reg_a, 0);
       rmwWithReg ("rol", hc08_reg_a);
       rmwWithReg ("neg", hc08_reg_a);
-      transferRegReg (hc08_reg_a, hc08_reg_x, FALSE);
+      transferRegReg (hc08_reg_a, hc08_reg_x, false);
       return;
 
     case 14:
@@ -7471,7 +7469,7 @@
        **   rora       1  1        aaaa aaaa  LSBresult   0
        ** total: n-2 cycles, n-2 bytes (beats 2n cycles, 2n bytes (for n>=8))
        */
-      transferRegReg (hc08_reg_x, hc08_reg_a, FALSE);
+      transferRegReg (hc08_reg_x, hc08_reg_a, false);
       AccSRsh (shCount - 8);
       rmwWithReg ("lsl", hc08_reg_a);
       loadRegFromConst (hc08_reg_x, 0);
@@ -7552,8 +7550,8 @@
     case 10:
     case 9:
     case 8:
-      transferRegReg (hc08_reg_x, hc08_reg_a, FALSE);
-      AccRsh (shCount - 8, FALSE);
+      transferRegReg (hc08_reg_x, hc08_reg_a, false);
+      AccRsh (shCount - 8, false);
       loadRegFromConst (hc08_reg_x, 0);
       return;
 
@@ -7568,7 +7566,7 @@
        ** total: 5 cycles, 5 bytes (beats 14 cycles, 14 bytes)
        */
       rmwWithReg ("lsl", hc08_reg_a);
-      transferRegReg (hc08_reg_x, hc08_reg_a, FALSE);
+      transferRegReg (hc08_reg_x, hc08_reg_a, false);
       rmwWithReg ("rol", hc08_reg_a);
       loadRegFromConst (hc08_reg_x, 0);
       rmwWithReg ("rol", hc08_reg_x);
@@ -7689,7 +7687,7 @@
 
   loadRegFromAop (hc08_reg_a, AOP (left), offl);
   /* shift left accumulator */
-  AccRsh (shCount, FALSE);
+  AccRsh (shCount, false);
   /* or with result */
   accopWithAop ("ora", AOP (result), offr);
   /* back to result */
@@ -7762,8 +7760,8 @@
 //  char *l;
 //  int size = AOP_SIZE (result);
 
-  bool needpula = FALSE;
-  bool needpulx = FALSE;
+  bool needpula = false;
+  bool needpulx = false;
 
   needpula = pushRegIfUsed (hc08_reg_a);
   needpulx = pushRegIfUsed (hc08_reg_x);
@@ -7903,10 +7901,10 @@
 
   D (emitcode (";     genLeftShiftLiteral", ""));
 
-  freeAsmop (right, NULL, ic, TRUE);
+  freeAsmop (right, NULL, ic, true);
 
-  aopOp (left, ic, FALSE);
-  aopOp (result, ic, FALSE);
+  aopOp (left, ic, false);
+  aopOp (result, ic, false);
 
 //  size = getSize (operandType (result));
   size = AOP_SIZE (result);
@@ -7944,8 +7942,8 @@
           break;
         }
     }
-  freeAsmop (left, NULL, ic, TRUE);
-  freeAsmop (result, NULL, ic, TRUE);
+  freeAsmop (left, NULL, ic, true);
+  freeAsmop (result, NULL, ic, true);
 }
 
 /*-----------------------------------------------------------------*/
@@ -7968,7 +7966,7 @@
   left = IC_LEFT (ic);
   result = IC_RESULT (ic);
 
-  aopOp (right, ic, FALSE);
+  aopOp (right, ic, false);
 
   /* if the shift count is known then do it
      as efficiently as possible */
@@ -7984,11 +7982,11 @@
      more that 32 bits make no sense anyway, ( the
      largest size of an object can be only 32 bits ) */
 
-  aopOp (result, ic, FALSE);
-  aopOp (left, ic, FALSE);
+  aopOp (result, ic, false);
+  aopOp (left, ic, false);
   aopResult = AOP (result);
 
-  if (sameRegs (AOP (right), AOP (result)) || regsInCommon (right, result) || IS_AOP_XA (AOP (result)) || isOperandVolatile (result, FALSE))
+  if (sameRegs (AOP (right), AOP (result)) || regsInCommon (right, result) || IS_AOP_XA (AOP (result)) || isOperandVolatile (result, false))
     aopResult = forceStackedAop (AOP (result), sameRegs (AOP (left), AOP (result)));
 
   /* now move the left to the result if they are not the
@@ -7997,7 +7995,7 @@
     loadRegFromAop (hc08_reg_hx, AOP (left), 0);
   else if (IS_AOP_AX (AOP (result)) && IS_AOP_XA (AOP (left)) || IS_AOP_XA (AOP (result)) && IS_AOP_AX (AOP (left)))
     {
-      pushReg (hc08_reg_x, TRUE);
+      pushReg (hc08_reg_x, true);
       emitcode("tax", "");
       regalloc_dry_run_cost++;
       pullReg (hc08_reg_a);
@@ -8012,7 +8010,7 @@
           offset++;
         }
     }
-  freeAsmop (left, NULL, ic, TRUE);
+  freeAsmop (left, NULL, ic, true);
   AOP (result) = aopResult;
 
   tlbl = (regalloc_dry_run ? 0 : newiTempLabel (NULL));
@@ -8031,13 +8029,13 @@
   needpullcountreg = (countreg && pushRegIfSurv (countreg));
   if(countreg)
     {
-      countreg->isFree = FALSE;
+      countreg->isFree = false;
       loadRegFromAop (countreg, AOP (right), 0);
     }
   else
     {
-      pushReg (hc08_reg_a, FALSE);
-      pushReg (hc08_reg_a, TRUE);
+      pushReg (hc08_reg_a, false);
+      pushReg (hc08_reg_a, true);
       loadRegFromAop (hc08_reg_a, AOP (right), 0);
       emitcode ("sta", "2, s");
       regalloc_dry_run_cost += 3;
@@ -8068,8 +8066,8 @@
   else
     pullOrFreeReg (countreg, needpullcountreg);
 
-  freeAsmop (result, NULL, ic, TRUE);
-  freeAsmop (right, NULL, ic, TRUE);
+  freeAsmop (result, NULL, ic, true);
+  freeAsmop (right, NULL, ic, true);
 }
 
 /*-----------------------------------------------------------------*/
@@ -8187,8 +8185,8 @@
 static void
 genrshFour (operand * result, operand * left, int shCount, int sign)
 {
-  bool needpulla = FALSE;
-  bool needpullx = FALSE;
+  bool needpulla = false;
+  bool needpullx = false;
 
   /* TODO: handle cases where left == result */
 
@@ -8236,7 +8234,7 @@
           needpulla = pushRegIfSurv (hc08_reg_a);
           needpullx = pushRegIfSurv (hc08_reg_x);
           loadRegFromAop (hc08_reg_xa, AOP (left), 1);
-          XAccRsh (shCount - 8, FALSE);
+          XAccRsh (shCount - 8, false);
           storeRegToAop (hc08_reg_xa, AOP (result), 0);
           loadRegFromAop (hc08_reg_x, AOP (left), 3);
           loadRegFromConst (hc08_reg_a, 0);
@@ -8259,7 +8257,7 @@
           needpulla = pushRegIfSurv (hc08_reg_a);
           needpullx = pushRegIfSurv (hc08_reg_x);
           loadRegFromAop (hc08_reg_xa, AOP (left), 0);
-          XAccRsh (shCount, FALSE);
+          XAccRsh (shCount, false);
           storeRegToAop (hc08_reg_xa, AOP (result), 0);
           loadRegFromAop (hc08_reg_a, AOP (left), 2);
           AccLsh (8 - shCount);
@@ -8285,10 +8283,10 @@
 
   D (emitcode (";     genRightShiftLiteral", ""));
 
-  freeAsmop (right, NULL, ic, TRUE);
+  freeAsmop (right, NULL, ic, true);
 
-  aopOp (left, ic, FALSE);
-  aopOp (result, ic, FALSE);
+  aopOp (left, ic, false);
+  aopOp (result, ic, false);
 
 #if VIEW_SIZE
   DD (emitcode ("; shift right ", "result %d, left %d", AOP_SIZE (result), AOP_SIZE (left)));
@@ -8334,8 +8332,8 @@
           break;
         }
     }
-  freeAsmop (left, NULL, ic, TRUE);
-  freeAsmop (result, NULL, ic, TRUE);
+  freeAsmop (left, NULL, ic, true);
+  freeAsmop (result, NULL, ic, true);
 }
 
 
@@ -8373,7 +8371,7 @@
   left = IC_LEFT (ic);
   result = IC_RESULT (ic);
 
-  aopOp (right, ic, FALSE);
+  aopOp (right, ic, false);
 
   /* if the shift count is known then do it
      as efficiently as possible */
@@ -8389,11 +8387,11 @@
      more that 32 bits make no sense anyway, ( the
      largest size of an object can be only 32 bits ) */
 
-  aopOp (result, ic, FALSE);
-  aopOp (left, ic, FALSE);
+  aopOp (result, ic, false);
+  aopOp (left, ic, false);
   aopResult = AOP (result);
 
-  if (sameRegs (AOP (right), AOP (result)) || regsInCommon (right, result) || IS_AOP_XA (AOP (result)) || isOperandVolatile (result, FALSE))
+  if (sameRegs (AOP (right), AOP (result)) || regsInCommon (right, result) || IS_AOP_XA (AOP (result)) || isOperandVolatile (result, false))
     aopResult = forceStackedAop (AOP (result), sameRegs (AOP (left), AOP (result)));
 
   /* now move the left to the result if they are not the
@@ -8402,7 +8400,7 @@
     loadRegFromAop (hc08_reg_hx, AOP (left), 0);
   else if (IS_AOP_AX (AOP (result)) && IS_AOP_XA (AOP (left)) || IS_AOP_XA (AOP (result)) && IS_AOP_AX (AOP (left)))
     {
-      pushReg (hc08_reg_x, TRUE);
+      pushReg (hc08_reg_x, true);
       emitcode("tax", "");
       regalloc_dry_run_cost++;
       pullReg (hc08_reg_a);
@@ -8417,7 +8415,7 @@
           offset++;
         }
     }
-  freeAsmop (left, NULL, ic, TRUE);
+  freeAsmop (left, NULL, ic, true);
   AOP (result) = aopResult;
 
   tlbl = (regalloc_dry_run ? 0 : newiTempLabel (NULL));
@@ -8436,13 +8434,13 @@
   needpullcountreg = (countreg && pushRegIfSurv (countreg));
   if(countreg)
     {
-      countreg->isFree = FALSE;
+      countreg->isFree = false;
       loadRegFromAop (countreg, AOP (right), 0);
     }
   else
     {
-      pushReg (hc08_reg_a, FALSE);
-      pushReg (hc08_reg_a, TRUE);
+      pushReg (hc08_reg_a, false);
+      pushReg (hc08_reg_a, true);
       loadRegFromAop (hc08_reg_a, AOP (right), 0);
       emitcode ("sta", "2, s");
       regalloc_dry_run_cost += 3;
@@ -8474,8 +8472,8 @@
   else
     pullOrFreeReg (countreg, needpullcountreg);
 
-  freeAsmop (result, NULL, ic, TRUE);
-  freeAsmop (right, NULL, ic, TRUE);
+  freeAsmop (result, NULL, ic, true);
+  freeAsmop (right, NULL, ic, true);
 }
 
 /*-----------------------------------------------------------------*/
@@ -8521,9 +8519,9 @@
   sym_link *etype;              /* bitfield type information */
   unsigned blen;                /* bitfield length */
   unsigned bstr;                /* bitfield starting bit within byte */
-  bool needpulla = FALSE;
-  bool needpullh = FALSE;
-  bool needpullx = FALSE;
+  bool needpulla = false;
+  bool needpullh = false;
+  bool needpullx = false;
   int litOffset = 0;
   char * rematOffset = NULL;
 
@@ -8568,7 +8566,7 @@
   if (blen < 8)
     {
       loadRegIndexed (hc08_reg_a, litOffset, rematOffset);
-      AccRsh (bstr, FALSE);
+      AccRsh (bstr, false);
       emitcode ("and", "#0x%02x", ((unsigned char) - 1) >> (8 - blen));
       regalloc_dry_run_cost += 2;
       if (!SPEC_USIGN (etype))
@@ -8594,7 +8592,7 @@
     {
       loadRegIndexed (hc08_reg_a, litOffset, rematOffset);
       if (rlen > 8 && AOP_TYPE (result) == AOP_REG)
-        pushReg (hc08_reg_a, TRUE);
+        pushReg (hc08_reg_a, true);
       else
         storeRegToAop (hc08_reg_a, AOP (result), offset);
       offset++;
@@ -8673,20 +8671,20 @@
   unsigned blen;                /* bitfield length */
   unsigned bstr;                /* bitfield starting bit within byte */
   asmop *derefaop;
-  bool delayed_a = FALSE;
-  bool assigned_a = FALSE;
-  bool needpulla = FALSE;
+  bool delayed_a = false;
+  bool assigned_a = false;
+  bool needpulla = false;
 
   D (emitcode (";     genUnpackBitsImmed", ""));
 
   decodePointerOffset (right, &litOffset, &rematOffset);
   wassert (rematOffset==NULL);
 
-  aopOp (result, ic, TRUE);
+  aopOp (result, ic, true);
   size = AOP_SIZE (result);
 
   derefaop = aopDerefAop (AOP (left), litOffset);
-  freeAsmop (left, NULL, ic, TRUE);
+  freeAsmop (left, NULL, ic, true);
   derefaop->size = size;
 
   etype = getSpec (operandType (result));
@@ -8705,7 +8703,7 @@
 
           loadRegFromConst (hc08_reg_a, 0);
           if (!regalloc_dry_run)
-            emitcode ("brclr", "#%d,%s,%05d$", bstr, aopAdrStr (derefaop, 0, FALSE), labelKey2num ((tlbl->key)));
+            emitcode ("brclr", "#%d,%s,%05d$", bstr, aopAdrStr (derefaop, 0, false), labelKey2num ((tlbl->key)));
           regalloc_dry_run_cost += 3;
           if (SPEC_USIGN (etype))
             rmwWithReg ("inc", hc08_reg_a);
@@ -8715,7 +8713,7 @@
             emitLabel (tlbl);
           storeRegToAop (hc08_reg_a, AOP (result), offset);
           if (AOP_TYPE (result) == AOP_REG && AOP(result)->aopu.aop_reg[offset]->rIdx == A_IDX)
-            assigned_a = TRUE;
+            assigned_a = true;
           hc08_freeReg (hc08_reg_a);
           offset++;
           goto finish;
@@ -8737,7 +8735,7 @@
               inst = "brset";
             }
           if (!regalloc_dry_run)
-            emitcode (inst, "#%d,%s,%05d$", bstr, aopAdrStr (derefaop, 0, FALSE), labelKey2num ((tlbl->key)));
+            emitcode (inst, "#%d,%s,%05d$", bstr, aopAdrStr (derefaop, 0, false), labelKey2num ((tlbl->key)));
           regalloc_dry_run_cost += 3;
           emitBranch ("jmp", jlbl);
           if (!regalloc_dry_run)
@@ -8754,10 +8752,10 @@
       loadRegFromAop (hc08_reg_a, derefaop, 0);
       if (!ifx)
         {
-          AccRsh (bstr, FALSE);
+          AccRsh (bstr, false);
           emitcode ("and", "#0x%02x", ((unsigned char) - 1) >> (8 - blen));
           regalloc_dry_run_cost += 2;
-          hc08_dirtyReg (hc08_reg_a, FALSE);
+          hc08_dirtyReg (hc08_reg_a, false);
           if (!SPEC_USIGN (etype))
             {
               /* signed bitfield */
@@ -8773,13 +8771,13 @@
             }
           storeRegToAop (hc08_reg_a, AOP (result), offset);
           if (AOP_TYPE (result) == AOP_REG && AOP(result)->aopu.aop_reg[offset]->rIdx == A_IDX)
-            assigned_a = TRUE;
+            assigned_a = true;
         }
       else
         {
           emitcode ("and", "#0x%02x", (((unsigned char) - 1) >> (8 - blen)) << bstr);
           regalloc_dry_run_cost += 2;
-          hc08_dirtyReg (hc08_reg_a, FALSE);
+          hc08_dirtyReg (hc08_reg_a, false);
         }
       offset++;
       goto finish;
@@ -8791,15 +8789,15 @@
     {
       if (assigned_a && !delayed_a)
         {
-          pushReg (hc08_reg_a, TRUE);
-          delayed_a = TRUE;
+          pushReg (hc08_reg_a, true);
+          delayed_a = true;
         }
       loadRegFromAop (hc08_reg_a, derefaop, size - offset - 1);
       if (!ifx)
         {
           storeRegToAop (hc08_reg_a, AOP (result), offset);
           if (AOP_TYPE (result) == AOP_REG && AOP(result)->aopu.aop_reg[offset]->rIdx == A_IDX)
-            assigned_a = TRUE;
+            assigned_a = true;
         }
       else
         {
@@ -8814,8 +8812,8 @@
     {
       if (assigned_a && !delayed_a)
         {
-          pushReg (hc08_reg_a, TRUE);
-          delayed_a = TRUE;
+          pushReg (hc08_reg_a, true);
+          delayed_a = true;
         }
       loadRegFromAop (hc08_reg_a, derefaop, size - offset - 1);
       emitcode ("and", "#0x%02x", ((unsigned char) - 1) >> (8 - rlen));
@@ -8835,7 +8833,7 @@
         }
       storeRegToAop (hc08_reg_a, AOP (result), offset);
       if (AOP_TYPE (result) == AOP_REG && AOP(result)->aopu.aop_reg[offset]->rIdx == A_IDX)
-        assigned_a = TRUE;
+        assigned_a = true;
       offset++;
     }
 
@@ -8852,8 +8850,8 @@
         {
           if (assigned_a && !delayed_a)
             {
-              pushReg (hc08_reg_a, TRUE);
-              delayed_a = TRUE;
+              pushReg (hc08_reg_a, true);
+              delayed_a = true;
             }
 
           /* signed bitfield: sign extension with 0x00 or 0xff */
@@ -8867,8 +8865,8 @@
         }
     }
 
-  freeAsmop (NULL, derefaop, ic, TRUE);
-  freeAsmop (result, NULL, ic, TRUE);
+  freeAsmop (NULL, derefaop, ic, true);
+  freeAsmop (result, NULL, ic, true);
 
   if (ifx && !ifx->generated)
     {
@@ -8891,18 +8889,18 @@
   int litOffset = 0;
   char * rematOffset = NULL;
   asmop *derefaop;
-  bool needpulla = FALSE;
+  bool needpulla = false;
 
   D (emitcode (";     genDataPointerGet", ""));
 
   decodePointerOffset (right, &litOffset, &rematOffset);
   wassert (rematOffset==NULL);
 
-  aopOp (result, ic, TRUE);
+  aopOp (result, ic, true);
   size = AOP_SIZE (result);
 
   derefaop = aopDerefAop (AOP (left), litOffset);
-  freeAsmop (left, NULL, ic, TRUE);
+  freeAsmop (left, NULL, ic, true);
   derefaop->size = size;
   
   if (ifx)
@@ -8919,8 +8917,8 @@
           loadRegFromAop (hc08_reg_a, derefaop, size);
       }
 
-  freeAsmop (NULL, derefaop, ic, TRUE);
-  freeAsmop (result, NULL, ic, TRUE);
+  freeAsmop (NULL, derefaop, ic, true);
+  freeAsmop (result, NULL, ic, true);
 
   pullOrFreeReg (hc08_reg_a, needpulla);
   if (ifx && !ifx->generated)
@@ -8943,17 +8941,17 @@
   int litOffset = 0;
   char * rematOffset = NULL;
   sym_link *retype = getSpec (operandType (result));
-  bool needpulla = FALSE;
-  bool needpullh = FALSE;
-  bool needpullx = FALSE;
-  bool vol = FALSE;
+  bool needpulla = false;
+  bool needpullh = false;
+  bool needpullx = false;
+  bool vol = false;
 
   D (emitcode (";     genPointerGet", ""));
 
   if ((size = getSize (operandType (result))) > 1)
     ifx = NULL;
 
-  aopOp (left, ic, FALSE);
+  aopOp (left, ic, false);
 
   /* if left is rematerialisable */
   if (AOP_TYPE (left) == AOP_IMMD || AOP_TYPE (left) == AOP_LIT)
@@ -8971,7 +8969,7 @@
         }
     }
 
-  aopOp (result, ic, FALSE);
+  aopOp (result, ic, false);
 
   /* if bit then unpack */
   if (IS_BITVAR (retype))
@@ -8989,7 +8987,7 @@
     { 
       int i;
       for (i = 0; i < AOP_SIZE (left); i++)
-        AOP (left)->aopu.aop_reg[i]->isDead = TRUE;
+        AOP (left)->aopu.aop_reg[i]->isDead = true;
     }
 
   if (!IS_AOP_HX (AOP (left)))
@@ -9008,7 +9006,7 @@
   if (AOP_TYPE (result) == AOP_REG)
     {
       if (pi)
-        aopOp (IC_RESULT (pi), pi, FALSE);
+        aopOp (IC_RESULT (pi), pi, false);
 
       if (AOP_SIZE (result) == 1)
         {
@@ -9025,7 +9023,7 @@
               hc08_useReg (hc08_reg_a);
               emitcode ("aix", "#%d", size);
               regalloc_dry_run_cost += 2;
-              hc08_dirtyReg (hc08_reg_hx, FALSE);
+              hc08_dirtyReg (hc08_reg_hx, false);
               hc08_freeReg (hc08_reg_x);
               storeRegToAop (hc08_reg_hx, AOP (IC_RESULT (pi)), 0);
               pi->generated = 1;
@@ -9037,14 +9035,14 @@
           if (pi || (IS_AOP_XA (AOP (IC_RESULT (ic))) && vol))
             {
               loadRegIndexed (hc08_reg_a, litOffset, rematOffset);
-              pushReg (hc08_reg_a, FALSE);
+              pushReg (hc08_reg_a, false);
               loadRegIndexed (hc08_reg_a, litOffset+1, rematOffset);
               hc08_useReg (hc08_reg_a);
               if (pi)
                 {
                   emitcode ("aix", "#%d", size);
                   regalloc_dry_run_cost += 2;
-                  hc08_dirtyReg (hc08_reg_hx, FALSE);
+                  hc08_dirtyReg (hc08_reg_hx, false);
                   hc08_freeReg (hc08_reg_x);
                   storeRegToAop (hc08_reg_hx, AOP (IC_RESULT (pi)), 0);
                   pi->generated = 1;
@@ -9074,7 +9072,7 @@
 
       if (pi)
         {
-          freeAsmop (IC_RESULT (pi), NULL, pi, TRUE);
+          freeAsmop (IC_RESULT (pi), NULL, pi, true);
         }
     }
   else if (!pi && !ifx && size == 2 && IS_S08 && hc08_reg_x->isDead && hc08_reg_h->isDead && AOP_TYPE (result) == AOP_EXT) /* Todo: Use this for bigger sizes, too */
@@ -9104,15 +9102,15 @@
 
 release:
   size = AOP_SIZE (result);
-  freeAsmop (left, NULL, ic, TRUE);
-  freeAsmop (result, NULL, ic, TRUE);
+  freeAsmop (left, NULL, ic, true);
+  freeAsmop (result, NULL, ic, true);
 
   if (pi && !pi->generated)
     {
       emitcode ("aix", "#%d", size);
       regalloc_dry_run_cost += 2;
-      hc08_dirtyReg (hc08_reg_hx, FALSE);
-      aopOp (IC_RESULT (pi), pi, FALSE);
+      hc08_dirtyReg (hc08_reg_hx, false);
+      aopOp (IC_RESULT (pi), pi, false);
       storeRegToAop (hc08_reg_hx, AOP (IC_RESULT (pi)), 0);
       if (ifx && AOP_TYPE (IC_RESULT (pi)) != AOP_REG)
         {
@@ -9121,7 +9119,7 @@
           emitcode ("tsta", "");
           regalloc_dry_run_cost++;
         }
-      freeAsmop (IC_RESULT (pi), NULL, pi, TRUE);
+      freeAsmop (IC_RESULT (pi), NULL, pi, true);
       pi->generated = 1;
     }
 
@@ -9166,8 +9164,8 @@
       /* be to do some of the shifting/masking now and    */
       /* push the intermediate result. */
       if (blen > 8)
-        pushReg (AOP (right)->aopu.aop_reg[1], TRUE);
-      pushReg (AOP (right)->aopu.aop_reg[0], TRUE);
+        pushReg (AOP (right)->aopu.aop_reg[1], true);
+      pushReg (AOP (right)->aopu.aop_reg[0], true);
     }
   loadRegFromAop (hc08_reg_hx, AOP (result), 0);
 
@@ -9195,7 +9193,7 @@
               emitcode ("ora", "#0x%02x", litval);
               regalloc_dry_run_cost += 2;
             }
-          hc08_dirtyReg (hc08_reg_a, FALSE);
+          hc08_dirtyReg (hc08_reg_a, false);
           storeRegIndexed (hc08_reg_a, litOffset, rematOffset);
 
           pullOrFreeReg (hc08_reg_a, needpulla);
@@ -9212,8 +9210,8 @@
       AccLsh (bstr);
       emitcode ("and", "#0x%02x", (~mask) & 0xff);
       regalloc_dry_run_cost += 2;
-      hc08_dirtyReg (hc08_reg_a, FALSE);
-      pushReg (hc08_reg_a, TRUE);
+      hc08_dirtyReg (hc08_reg_a, false);
+      pushReg (hc08_reg_a, true);
 
       loadRegIndexed (hc08_reg_a, litOffset, rematOffset);
       emitcode ("and", "#0x%02x", mask);
@@ -9232,7 +9230,7 @@
     {
       if (!litOffset && !rematOffset && AOP (right)->type == AOP_DIR)
         {
-          emitcode ("mov", "%s,x+", aopAdrStr (AOP (right), offset, FALSE));
+          emitcode ("mov", "%s,x+", aopAdrStr (AOP (right), offset, false));
           regalloc_dry_run_cost += 2;
           litOffset--;
         }
@@ -9270,7 +9268,7 @@
               emitcode ("ora", "#0x%02x", litval);
               regalloc_dry_run_cost += 2;
             }
-          hc08_dirtyReg (hc08_reg_a, FALSE);
+          hc08_dirtyReg (hc08_reg_a, false);
           storeRegIndexed (hc08_reg_a, litOffset+offset, rematOffset);
           pullOrFreeReg (hc08_reg_a, needpulla);
           return;
@@ -9284,8 +9282,8 @@
         loadRegFromAop (hc08_reg_a, AOP (right), offset);
       emitcode ("and", "#0x%02x", (~mask) & 0xff);
       regalloc_dry_run_cost += 2;
-      hc08_dirtyReg (hc08_reg_a, FALSE);
-      pushReg (hc08_reg_a, TRUE);
+      hc08_dirtyReg (hc08_reg_a, false);
+      pushReg (hc08_reg_a, true);
 
       loadRegIndexed(hc08_reg_a, litOffset+offset, rematOffset);
       emitcode ("and", "#0x%02x", mask);
@@ -9321,13 +9319,13 @@
   blen = SPEC_BLEN (etype);
   bstr = SPEC_BSTR (etype);
 
-  aopOp (right, ic, FALSE);
+  aopOp (right, ic, false);
   size = AOP_SIZE (right);
   decodePointerOffset (left, &litOffset, &rematOffset);
   wassert (!rematOffset);
 
   derefaop = aopDerefAop (AOP (result), litOffset);
-  freeAsmop (result, NULL, ic, TRUE);
+  freeAsmop (result, NULL, ic, true);
   derefaop->size = size;
 
   /* if the bitfield is a single bit in the direct page */
@@ -9337,7 +9335,7 @@
         {
           litval = (int) ulFromVal (AOP (right)->aopu.aop_lit);
 
-          emitcode ((litval & 1) ? "bset" : "bclr", "#%d,%s", bstr, aopAdrStr (derefaop, 0, FALSE));
+          emitcode ((litval & 1) ? "bset" : "bclr", "#%d,%s", bstr, aopAdrStr (derefaop, 0, false));
           regalloc_dry_run_cost += 2;
         }
       else
@@ -9350,12 +9348,12 @@
           emitcode ("lsra", "");
           regalloc_dry_run_cost++;
           emitBranch ("bcs", tlbl1);
-          emitcode ("bclr", "#%d,%s", bstr, aopAdrStr (derefaop, 0, FALSE));
+          emitcode ("bclr", "#%d,%s", bstr, aopAdrStr (derefaop, 0, false));
           regalloc_dry_run_cost += 2;
           emitBranch ("bra", tlbl2);
           if (!regalloc_dry_run)
             emitLabel (tlbl1);
-          emitcode ("bset", "#%d,%s", bstr, aopAdrStr (derefaop, 0, FALSE));
+          emitcode ("bset", "#%d,%s", bstr, aopAdrStr (derefaop, 0, false));
           regalloc_dry_run_cost += 2;
           if (!regalloc_dry_run)
             emitLabel (tlbl2);
@@ -9389,7 +9387,7 @@
               emitcode ("ora", "#0x%02x", litval);
               regalloc_dry_run_cost += 2;
             }
-          hc08_dirtyReg (hc08_reg_a, FALSE);
+          hc08_dirtyReg (hc08_reg_a, false);
           storeRegToAop (hc08_reg_a, derefaop, 0);
 
           pullOrFreeReg (hc08_reg_a, needpulla);
@@ -9404,8 +9402,8 @@
       AccLsh (bstr);
       emitcode ("and", "#0x%02x", (~mask) & 0xff);
       regalloc_dry_run_cost += 2;
-      hc08_dirtyReg (hc08_reg_a, FALSE);
-      pushReg (hc08_reg_a, TRUE);
+      hc08_dirtyReg (hc08_reg_a, false);
+      pushReg (hc08_reg_a, true);
 
       loadRegFromAop (hc08_reg_a, derefaop, 0);
       emitcode ("and", "#0x%02x", mask);
@@ -9450,9 +9448,9 @@
               emitcode ("ora", "#0x%02x", litval);
               regalloc_dry_run_cost += 2;
             }
-          hc08_dirtyReg (hc08_reg_a, FALSE);
+          hc08_dirtyReg (hc08_reg_a, false);
           storeRegToAop (hc08_reg_a, derefaop, size - offset - 1);
-          hc08_dirtyReg (hc08_reg_a, FALSE);
+          hc08_dirtyReg (hc08_reg_a, false);
           pullOrFreeReg (hc08_reg_a, needpulla);
           goto release;
         }
@@ -9463,8 +9461,8 @@
       loadRegFromAop (hc08_reg_a, AOP (right), offset);
       emitcode ("and", "#0x%02x", (~mask) & 0xff);
       regalloc_dry_run_cost += 2;
-      hc08_dirtyReg (hc08_reg_a, FALSE);
-      pushReg (hc08_reg_a, TRUE);
+      hc08_dirtyReg (hc08_reg_a, false);
+      pushReg (hc08_reg_a, true);
 
       loadRegFromAop (hc08_reg_a, derefaop, size - offset - 1);
       emitcode ("and", "#0x%02x", mask);
@@ -9478,8 +9476,8 @@
   hc08_freeReg (hc08_reg_a);
 
 release:
-  freeAsmop (right, NULL, ic, TRUE);
-  freeAsmop (NULL, derefaop, ic, TRUE);
+  freeAsmop (right, NULL, ic, true);
+  freeAsmop (NULL, derefaop, ic, true);
 }
 
 /*-----------------------------------------------------------------*/
@@ -9495,13 +9493,13 @@
 
   D (emitcode (";     genDataPointerSet", ""));
 
-  aopOp (right, ic, FALSE);
+  aopOp (right, ic, false);
   size = AOP_SIZE (right);
   decodePointerOffset (left, &litOffset, &rematOffset);
   wassert (!rematOffset);
 
   derefaop = aopDerefAop (AOP (result), litOffset);
-  freeAsmop (result, NULL, ic, TRUE);
+  freeAsmop (result, NULL, ic, true);
   derefaop->size = size;
 
   if (IS_AOP_HX (AOP (right)))
@@ -9516,8 +9514,8 @@
         }
     }
 
-  freeAsmop (right, NULL, ic, TRUE);
-  freeAsmop (NULL, derefaop, ic, TRUE);
+  freeAsmop (right, NULL, ic, true);
+  freeAsmop (NULL, derefaop, ic, true);
 }
 
 
@@ -9533,16 +9531,16 @@
   int size, offset;
   sym_link *retype = getSpec (operandType (right));
   sym_link *letype = getSpec (operandType (result));
-  bool needpulla = FALSE;
-  bool needpullx = FALSE;
-  bool needpullh = FALSE;
-  bool vol = FALSE;
+  bool needpulla = false;
+  bool needpullx = false;
+  bool needpullh = false;
+  bool vol = false;
   int litOffset = 0;
   char *rematOffset = NULL;
 
   D (emitcode (";     genPointerSet", ""));
 
-  aopOp (result, ic, FALSE);
+  aopOp (result, ic, false);
 
   /* if the result is rematerializable */
   if (AOP_TYPE (result) == AOP_IMMD || AOP_TYPE (result) == AOP_LIT)
@@ -9562,13 +9560,13 @@
     { 
       int i;
       for (i = 0; i < AOP_SIZE (result); i++)
-        AOP (result)->aopu.aop_reg[i]->isDead = TRUE;
+        AOP (result)->aopu.aop_reg[i]->isDead = true;
     }
 
   needpullx = pushRegIfSurv (hc08_reg_x);
   needpullh = pushRegIfSurv (hc08_reg_h);
 
-  aopOp (right, ic, FALSE);
+  aopOp (right, ic, false);
   size = AOP_SIZE (right);
 
   /* if bit then pack */
@@ -9592,8 +9590,8 @@
             {
               if (AOP (right)->aopu.aop_reg[0]->rIdx != A_IDX)
                 needpulla = pushRegIfSurv (hc08_reg_a);
-              pushReg (AOP (right)->aopu.aop_reg[0], TRUE);
-              pushReg (AOP (right)->aopu.aop_reg[1], TRUE);
+              pushReg (AOP (right)->aopu.aop_reg[0], true);
+              pushReg (AOP (right)->aopu.aop_reg[1], true);
               loadRegFromAop (hc08_reg_hx, AOP (result), 0);
               pullReg (hc08_reg_a);
               storeRegIndexed (hc08_reg_a, litOffset, rematOffset);
@@ -9604,7 +9602,7 @@
             {
               needpulla = pushRegIfSurv (hc08_reg_a);
               loadRegFromAop (hc08_reg_a, AOP (right), 0);
-              pushReg (AOP (right)->aopu.aop_reg[1], TRUE);
+              pushReg (AOP (right)->aopu.aop_reg[1], true);
               loadRegFromAop (hc08_reg_hx, AOP (result), 0);
               storeRegIndexed (hc08_reg_a, litOffset+1, rematOffset);
               pullReg (hc08_reg_a);
@@ -9615,7 +9613,7 @@
       else if (IS_AOP_AX (AOP (right)))
         {
           needpulla = pushRegIfSurv (hc08_reg_a);
-          pushReg (hc08_reg_x, TRUE);
+          pushReg (hc08_reg_x, true);
           loadRegFromAop (hc08_reg_hx, AOP (result), 0);
           storeRegIndexed (hc08_reg_a, litOffset, rematOffset);
           pullReg (hc08_reg_a); /* original X value */
@@ -9642,17 +9640,17 @@
         }
     }
 
-  freeAsmop (result, NULL, ic, TRUE);
-  freeAsmop (right, NULL, ic, TRUE);
+  freeAsmop (result, NULL, ic, true);
+  freeAsmop (right, NULL, ic, true);
 
   if (pi)
     {
-      aopOp (IC_RESULT (pi), pi, FALSE);
+      aopOp (IC_RESULT (pi), pi, false);
       emitcode ("aix", "#%d", size);
       regalloc_dry_run_cost += 2;
-      hc08_dirtyReg (hc08_reg_hx, FALSE);
+      hc08_dirtyReg (hc08_reg_hx, false);
       storeRegToAop (hc08_reg_hx, AOP (IC_RESULT (pi)), 0);
-      freeAsmop (IC_RESULT (pi), NULL, pi, TRUE);
+      freeAsmop (IC_RESULT (pi), NULL, pi, true);
       pi->generated = 1;
     }
 
@@ -9671,14 +9669,14 @@
   
   D (emitcode (";     genIfx", ""));
 
-  aopOp (cond, ic, FALSE);
+  aopOp (cond, ic, false);
 
   /* If the condition is a literal, we can just do an unconditional */
   /* branch or no branch */
   if (AOP_TYPE (cond) == AOP_LIT)
     {
       unsigned long long lit = ullFromVal (AOP (cond)->aopu.aop_lit);
-      freeAsmop (cond, NULL, ic, TRUE);
+      freeAsmop (cond, NULL, ic, true);
 
       /* if there was something to be popped then do it */
       if (popIc)
@@ -9699,9 +9697,9 @@
 
   /* evaluate the operand */
   if (AOP_TYPE (cond) != AOP_CRY)
-    asmopToBool (AOP (cond), FALSE);
+    asmopToBool (AOP (cond), false);
   /* the result is now in the z flag bit */
-  freeAsmop (cond, NULL, ic, TRUE);
+  freeAsmop (cond, NULL, ic, true);
 
   /* if there was something to be popped then do it */
   if (popIc)
@@ -9719,12 +9717,15 @@
 genAddrOf (iCode * ic)
 {
   symbol *sym = OP_SYMBOL (IC_LEFT (ic));
+  asmop *aopr;
   int size, offset;
   bool needpullx, needpullh;
-
+  struct dbuf_s dbuf;
+  
   D (emitcode (";     genAddrOf", ""));
 
-  aopOp (IC_RESULT (ic), ic, FALSE);
+  aopOp (IC_RESULT (ic), ic, false);
+  aopr = AOP (IC_RESULT (ic));
 
   /* if the operand is on the stack then we
      need to get the stack offset of this
@@ -9737,7 +9738,7 @@
       offset = _G.stackOfs + _G.stackPushes + sym->stack;
       hc08_useReg (hc08_reg_hx);
       emitcode ("tsx", "");
-      hc08_dirtyReg (hc08_reg_hx, FALSE);
+      hc08_dirtyReg (hc08_reg_hx, false);
       regalloc_dry_run_cost++;
       while (offset > 127)
         {
@@ -9756,35 +9757,47 @@
           emitcode ("aix", "#%d", offset);
           regalloc_dry_run_cost += 2;
         }
-      storeRegToFullAop (hc08_reg_hx, AOP (IC_RESULT (ic)), FALSE);
+      storeRegToFullAop (hc08_reg_hx, AOP (IC_RESULT (ic)), false);
       pullOrFreeReg (hc08_reg_h, needpullh);
       pullOrFreeReg (hc08_reg_x, needpullx);
       goto release;
     }
 
+  if (IS_AOP_HX (aopr) || aopr->type == AOP_DIR ||
+      (IS_S08 && aopr->type != AOP_REG))
+    {
+      needpullx = pushRegIfSurv (hc08_reg_x);
+      needpullh = pushRegIfSurv (hc08_reg_h);
+      loadRegFromImm (hc08_reg_hx, sym->rname);
+      storeRegToFullAop (hc08_reg_hx, AOP (IC_RESULT (ic)), false);
+      pullOrFreeReg (hc08_reg_h, needpullh);
+      pullOrFreeReg (hc08_reg_x, needpullx);
+      goto release;
+    }
+  
   /* object not on stack then we need the name */
   size = AOP_SIZE (IC_RESULT (ic));
   offset = 0;
 
   while (size--)
     {
-      char s[SDCC_NAME_MAX + 10];
+      dbuf_init (&dbuf, 64);
       switch (offset)
         {
         case 0:
-          sprintf (s, "#%s", sym->rname);
+          dbuf_printf (&dbuf, "#%s", sym->rname);
           break;
         case 1:
-          sprintf (s, "#>%s", sym->rname);
+          dbuf_printf (&dbuf, "#>%s", sym->rname);
           break;
         default:
-          sprintf (s, "#(%s >> %d)", sym->rname, offset * 8);
+          dbuf_printf (&dbuf, "#0");
         }
-      storeImmToAop (s, AOP (IC_RESULT (ic)), offset++);
+      storeImmToAop (dbuf_detach_c_str (&dbuf), AOP (IC_RESULT (ic)), offset++);
     }
 
 release:
-  freeAsmop (IC_RESULT (ic), NULL, ic, TRUE);
+  freeAsmop (IC_RESULT (ic), NULL, ic, true);
 }
 
 /*-----------------------------------------------------------------*/
@@ -9800,27 +9813,27 @@
   int size;
   int offset,offset2;
   int dups,multiples;
-  bool needpula = FALSE;
-  bool canUseHX = TRUE;
+  bool needpula = false;
+  bool canUseHX = true;
   int remaining;
 
   /* Make sure this is a literal assignment */
   if (AOP_TYPE (right) != AOP_LIT)
-    return FALSE;
+    return false;
 
   /* The general case already handles register assignment well */
   if (AOP_TYPE (result) == AOP_REG)
-    return FALSE;
+    return false;
 
   /* Some hardware registers require MSB to LSB assignment order */
   /* so don't optimize the assignment order if volatile */
-  if (isOperandVolatile (result, FALSE))
-    return FALSE;
+  if (isOperandVolatile (result, false))
+    return false;
 
   /* Make sure the assignment is not larger than we can handle */
   size = AOP_SIZE (result);
   if (size > sizeof(assigned))
-    return FALSE;
+    return false;
 
   for (offset=0; offsetisDead && hc08_reg_x->isDead))
-    canUseHX = FALSE;
+    canUseHX = false;
 
   if (canUseHX && (size>=2))
     {
@@ -9863,14 +9876,14 @@
           assigned[offset] = 1;
           assigned[offset+1] = 1;
         }
-      return TRUE;
+      return true;
     }
 
   remaining = size;
   for (offset=0; offset 2)
     aopOpExtToIdx (AOP (result), NULL, NULL);
@@ -9938,7 +9951,7 @@
 
   if (needpula)
     pullReg (hc08_reg_a);
-  return TRUE;
+  return true;
 }
 
 
@@ -9955,14 +9968,14 @@
   result = IC_RESULT (ic);
   right = IC_RIGHT (ic);
   
-  aopOp (right, ic, FALSE);
-  aopOp (result, ic, TRUE);
+  aopOp (right, ic, false);
+  aopOp (result, ic, true);
 
   if (!genAssignLit (result, right))
     genCopy (result, right);
 
-  freeAsmop (right, NULL, ic, TRUE);
-  freeAsmop (result, NULL, ic, TRUE);
+  freeAsmop (right, NULL, ic, true);
+  freeAsmop (result, NULL, ic, true);
 }
 
 /*-----------------------------------------------------------------*/
@@ -9977,13 +9990,13 @@
 
   D (emitcode (";     genJumpTab", ""));
 
-  aopOp (IC_JTCOND (ic), ic, FALSE);
+  aopOp (IC_JTCOND (ic), ic, false);
 
   if (hc08_reg_x->isFree && hc08_reg_h->isFree)
     {
       /* get the condition into x */
       loadRegFromAop (hc08_reg_x, AOP (IC_JTCOND (ic)), 0);
-      freeAsmop (IC_JTCOND (ic), NULL, ic, TRUE);
+      freeAsmop (IC_JTCOND (ic), NULL, ic, true);
       loadRegFromConst (hc08_reg_h, 0);
 
       if (!regalloc_dry_run)
@@ -9992,21 +10005,21 @@
           emitcode ("ldx", "%05d$,x", labelKey2num (jtablo->key));
         }
       regalloc_dry_run_cost += 6;
-      transferRegReg (hc08_reg_a, hc08_reg_h, TRUE);
+      transferRegReg (hc08_reg_a, hc08_reg_h, true);
       emitcode ("jmp", ",x");
       regalloc_dry_run_cost++;
 
-      hc08_dirtyReg (hc08_reg_a, TRUE);
-      hc08_dirtyReg (hc08_reg_hx, TRUE);
+      hc08_dirtyReg (hc08_reg_a, true);
+      hc08_dirtyReg (hc08_reg_hx, true);
     }
   else
     {
       adjustStack (-2);
-      pushReg (hc08_reg_hx, TRUE);
+      pushReg (hc08_reg_hx, true);
 
       /* get the condition into x */
       loadRegFromAop (hc08_reg_x, AOP (IC_JTCOND (ic)), 0);
-      freeAsmop (IC_JTCOND (ic), NULL, ic, TRUE);
+      freeAsmop (IC_JTCOND (ic), NULL, ic, true);
       loadRegFromConst (hc08_reg_h, 0);
 
       if (!regalloc_dry_run)
@@ -10060,13 +10073,13 @@
   if (operandsEqu (IC_RESULT (ic), IC_RIGHT (ic)))
     return;
 
-  aopOp (right, ic, FALSE);
-  aopOp (result, ic, FALSE);
+  aopOp (right, ic, false);
+  aopOp (result, ic, false);
 
   if (IS_BOOL (operandType (result)))
     {
       bool needpulla = pushRegIfSurv (hc08_reg_a);
-      asmopToBool (AOP (right), TRUE);
+      asmopToBool (AOP (right), true);
       storeRegToAop (hc08_reg_a, AOP (result), 0);
       pullOrFreeReg (hc08_reg_a, needpulla);
       goto release;
@@ -10103,7 +10116,7 @@
 
               /* we need to extend the sign :{ */
               if (save_a)
-                pushReg(hc08_reg_a, FALSE);
+                pushReg(hc08_reg_a, false);
               if (AOP (result)->aopu.aop_reg[0] != hc08_reg_a)
                 loadRegFromAop (hc08_reg_a, AOP (right), 0);
               accopWithMisc ("rola", "");
@@ -10148,7 +10161,7 @@
   
   save_a = !hc08_reg_a->isDead && signExtend;
   if (save_a)
-    pushReg(hc08_reg_a, TRUE);
+    pushReg(hc08_reg_a, true);
 
   offset = 0;
   size = AOP_SIZE (right);
@@ -10201,8 +10214,8 @@
   /* we are done hurray !!!! */
 
 release:
-  freeAsmop (right, NULL, ic, TRUE);
-  freeAsmop (result, NULL, ic, TRUE);
+  freeAsmop (right, NULL, ic, true);
+  freeAsmop (result, NULL, ic, true);
 
 }
 
@@ -10227,10 +10240,10 @@
 
   /* if the size of this greater than one then no
      saving, unless it's already in HX  */
-  aopOp (IC_RESULT (ic), ic, FALSE);
+  aopOp (IC_RESULT (ic), ic, false);
   if (AOP_SIZE (IC_RESULT (ic)) > 1 && !IS_AOP_HX (AOP (IC_RESULT (ic))))
     {
-      freeAsmop (IC_RESULT (ic), NULL, ic, TRUE);
+      freeAsmop (IC_RESULT (ic), NULL, ic, true);
       return 0;
     }
 
@@ -10244,14 +10257,14 @@
   if (IS_AOP_HX (AOP (IC_RESULT (ic))))
     {
       emitcode ("aix", "#-1");
-      hc08_dirtyReg (hc08_reg_hx, FALSE);
+      hc08_dirtyReg (hc08_reg_hx, false);
       emitcode ("cphx", "#0");
       regalloc_dry_run_cost += 5;
     }
   else
     rmwWithAop ("dec", AOP (IC_RESULT (ic)), 0);
   genIfxJump (ifx, "a");
-  freeAsmop (IC_RESULT (ic), NULL, ic, TRUE);
+  freeAsmop (IC_RESULT (ic), NULL, ic, true);
   return 1;
 }
 
@@ -10263,17 +10276,17 @@
 {
   int size;
   int offset;
-  bool delayed_x = FALSE;
+  bool delayed_x = false;
 
   D (emitcode (";", "genReceive"));
 
-  aopOp (IC_RESULT (ic), ic, FALSE);
+  aopOp (IC_RESULT (ic), ic, false);
   size = AOP_SIZE (IC_RESULT (ic));
   offset = 0;
 
   if (ic->argreg && IS_AOP_HX (AOP (IC_RESULT (ic))) && (offset + (ic->argreg - 1)) == 0)
     {
-      pushReg (hc08_reg_x, TRUE);
+      pushReg (hc08_reg_x, true);
       emitcode ("tax", "");
       regalloc_dry_run_cost++;
       pullReg (hc08_reg_h);
@@ -10284,8 +10297,8 @@
         {
           if (AOP_TYPE (IC_RESULT (ic)) == AOP_REG && !(offset + (ic->argreg - 1)) && AOP (IC_RESULT (ic))->aopu.aop_reg[0]->rIdx == X_IDX && size)
             {
-              pushReg (hc08_reg_a, TRUE);
-              delayed_x = TRUE;
+              pushReg (hc08_reg_a, true);
+              delayed_x = true;
             }
           else
             transferAopAop (hc08_aop_pass[offset + (ic->argreg - 1)], 0, AOP (IC_RESULT (ic)), offset);
@@ -10298,7 +10311,7 @@
   if (delayed_x)
     pullReg (hc08_reg_x);
 
-  freeAsmop (IC_RESULT (ic), NULL, ic, TRUE);
+  freeAsmop (IC_RESULT (ic), NULL, ic, true);
 }
 
 /*-----------------------------------------------------------------*/
@@ -10319,7 +10332,7 @@
   if (op && IS_SYMOP (op))
     {
 
-      aopOp (op, ic, FALSE);
+      aopOp (op, ic, false);
 
       size = AOP_SIZE (op);
       offset = size - 1;
@@ -10331,13 +10344,13 @@
           offset--;
         }
 
-      freeAsmop (op, NULL, ic, TRUE);
+      freeAsmop (op, NULL, ic, true);
     }
   op = IC_LEFT (ic);
   if (op && IS_SYMOP (op))
     {
 
-      aopOp (op, ic, FALSE);
+      aopOp (op, ic, false);
 
       size = AOP_SIZE (op);
       offset = size - 1;
@@ -10349,7 +10362,7 @@
           offset--;
         }
 
-      freeAsmop (op, NULL, ic, TRUE);
+      freeAsmop (op, NULL, ic, true);
     }
   pullOrFreeReg (hc08_reg_a, needpulla);
 }
@@ -10363,22 +10376,22 @@
   D (emitcode (";     genCritical", ""));
 
   if (IC_RESULT (ic))
-    aopOp (IC_RESULT (ic), ic, TRUE);
+    aopOp (IC_RESULT (ic), ic, true);
 
   emitcode ("tpa", "");
   regalloc_dry_run_cost++;
-  hc08_dirtyReg (hc08_reg_a, FALSE);
+  hc08_dirtyReg (hc08_reg_a, false);
   emitcode ("sei", "");
   regalloc_dry_run_cost++;
 
   if (IC_RESULT (ic))
     storeRegToAop (hc08_reg_a, AOP (IC_RESULT (ic)), 0);
   else
-    pushReg (hc08_reg_a, FALSE);
+    pushReg (hc08_reg_a, false);
 
   hc08_freeReg (hc08_reg_a);
   if (IC_RESULT (ic))
-    freeAsmop (IC_RESULT (ic), NULL, ic, TRUE);
+    freeAsmop (IC_RESULT (ic), NULL, ic, true);
 }
 
 /*-----------------------------------------------------------------*/
@@ -10391,12 +10404,12 @@
 
   if (IC_RIGHT (ic))
     {
-      aopOp (IC_RIGHT (ic), ic, FALSE);
+      aopOp (IC_RIGHT (ic), ic, false);
       loadRegFromAop (hc08_reg_a, AOP (IC_RIGHT (ic)), 0);
       emitcode ("tap", "");
       regalloc_dry_run_cost++;
       hc08_freeReg (hc08_reg_a);
-      freeAsmop (IC_RIGHT (ic), NULL, ic, TRUE);
+      freeAsmop (IC_RIGHT (ic), NULL, ic, true);
     }
   else
     {
@@ -10450,7 +10463,7 @@
         reg = hc08_regWithIdx (i);
         //if (reg->aop)
         //  emitcode ("", "; %s = %s offset %d", reg->name, aopName (reg->aop), reg->aopofs);
-        reg->isFree = TRUE;
+        reg->isFree = true;
         if (regalloc_dry_run)
           reg->isLitConst = 0;
       }
@@ -10476,11 +10489,11 @@
       {
         if (bitVectBitValue (ic->rSurv, i))
           {
-            hc08_regWithIdx (i)->isDead = FALSE;
-            hc08_regWithIdx (i)->isFree = FALSE;
+            hc08_regWithIdx (i)->isDead = false;
+            hc08_regWithIdx (i)->isFree = false;
           }
         else
-          hc08_regWithIdx (i)->isDead = TRUE;
+          hc08_regWithIdx (i)->isDead = true;
       }
   }
 
@@ -10609,10 +10622,6 @@
       genRLC (ic);
       break;
 
-    case GETHBIT:
-      wassertl (0, "Unimplemented iCode");
-      break;
-
     case GETABIT:
       genGetAbit (ic);
       break;
@@ -10729,10 +10738,10 @@
   hc08_aop_pass[7]->aopu.aop_dir = "___SDCC_hc08_ret7";
 }
 
-unsigned char
+float
 dryhc08iCode (iCode *ic)
 {
-  regalloc_dry_run = TRUE;
+  regalloc_dry_run = true;
   regalloc_dry_run_cost = 0;
 
   init_aop_pass();
@@ -10756,11 +10765,11 @@
   int clevel = 0;
   int cblock = 0;
 
-  regalloc_dry_run = FALSE;
+  regalloc_dry_run = false;
 
-  hc08_dirtyReg (hc08_reg_a, FALSE);
-  hc08_dirtyReg (hc08_reg_h, FALSE);
-  hc08_dirtyReg (hc08_reg_x, FALSE);
+  hc08_dirtyReg (hc08_reg_a, false);
+  hc08_dirtyReg (hc08_reg_h, false);
+  hc08_dirtyReg (hc08_reg_x, false);
 
   /* print the allocation information */
   if (allocInfo && currFunc)
@@ -10777,7 +10786,7 @@
   init_aop_pass();
 
   for (ic = lic; ic; ic = ic->next)
-    ic->generated = FALSE;
+    ic->generated = false;
 
   for (ic = lic; ic; ic = ic->next)
     {
diff -Nru sdcc-4.0.0+dfsg/src/hc08/main.c sdcc-4.2.0+dfsg/src/hc08/main.c
--- sdcc-4.0.0+dfsg/src/hc08/main.c	2019-03-20 18:17:49.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/hc08/main.c	2022-01-06 05:46:17.000000000 +0000
@@ -77,7 +77,8 @@
 
 void hc08_assignRegisters (ebbIndex *);
 
-static int regParmFlg = 0;      /* determine if we can register a parameter */
+static int regParmFlg;      /* determine if we can register a parameter */
+static struct sym_link *regParmFuncType;
 
 static void
 _hc08_init (void)
@@ -97,11 +98,15 @@
 _hc08_reset_regparm (struct sym_link *funcType)
 {
   regParmFlg = 0;
+  regParmFuncType = funcType;
 }
 
 static int
 _hc08_regparm (sym_link * l, bool reentrant)
 {
+  if (IFFUNC_HASVARARGS (regParmFuncType))
+    return 0;
+
   int size = getSize(l);
 
   /* If they fit completely, the first two bytes of parameters can go */
@@ -134,16 +139,16 @@
     {
       options.out_fmt = 'E';
       debugFile = &dwarf2DebugFile;
-      return TRUE;
+      return true;
     }
 
   if (!strcmp (argv[*i], "--oldralloc"))
     {
-      options.oldralloc = TRUE;
-      return TRUE;
+      options.oldralloc = true;
+      return true;
     }
 
-  return FALSE;
+  return false;
 }
 
 #define OPTION_SMALL_MODEL          "--model-small"
@@ -315,7 +320,7 @@
     }
   dbuf_printf (oBuf, "\t.dw\t%s", "__sdcc_gs_init_startup\n");
 
-  return TRUE;
+  return true;
 }
 
 /* Generate code to copy XINIT to XISEG */
@@ -361,9 +366,9 @@
       || op == GETBYTE
       || op == GETWORD
      )
-    return TRUE;
+    return true;
   else
-    return FALSE;
+    return false;
 }
 
 /* Indicate the expense of an access to an output storage class */
@@ -774,7 +779,7 @@
   NULL,                         /* Processor name */
   {
     glue,
-    FALSE,                      /* Emit glue around main */
+    false,                      /* Emit glue around main */
     MODEL_SMALL | MODEL_LARGE,
     MODEL_LARGE,
     NULL,                       /* model == target */
@@ -836,6 +841,7 @@
   },
   { _hc08_genExtraAreas,
     NULL },
+  0,                      // ABI revision
   {
     -1,         /* direction (-1 = stack grows down) */
     0,          /* bank_overhead (switch between register banks) */
@@ -846,7 +852,7 @@
     1           /* sp is offset by 1 from last item pushed */
   },
   {
-    5, FALSE
+    5, false
   },
   {
     hc08_emitDebuggerSymbol,
@@ -893,15 +899,15 @@
   _hasNativeMulFor,             /* hasNativeMulFor */
   hasExtBitOp,                  /* hasExtBitOp */
   oclsExpense,                  /* oclsExpense */
-  TRUE,                         /* use_dw_for_init */
-  FALSE,                        /* little_endian */
+  true,                         /* use_dw_for_init */
+  false,                        /* little_endian */
   0,                            /* leave lt */
   0,                            /* leave gt */
   1,                            /* transform <= to ! > */
   1,                            /* transform >= to ! < */
   1,                            /* transform != to !(a == b) */
   0,                            /* leave == */
-  FALSE,                        /* No array initializer support. */
+  false,                        /* No array initializer support. */
   cseCostEstimation,
   NULL,                         /* no builtin functions */
   GPOINTER,                     /* treat unqualified pointers as "generic" pointers */
@@ -919,7 +925,7 @@
   NULL,                         /* Processor name */
   {
     glue,
-    FALSE,                      /* Emit glue around main */
+    false,                      /* Emit glue around main */
     MODEL_SMALL | MODEL_LARGE,
     MODEL_LARGE,
     NULL,                       /* model == target */
@@ -981,6 +987,7 @@
   },
   { _hc08_genExtraAreas,
     NULL },
+  0,
   {
     -1,         /* direction (-1 = stack grows down) */
     0,          /* bank_overhead (switch between register banks) */
@@ -991,7 +998,7 @@
     1           /* sp is offset by 1 from last item pushed */
   },
   {
-    5, FALSE
+    5, false
   },
   {
     hc08_emitDebuggerSymbol,
@@ -1038,15 +1045,15 @@
   _hasNativeMulFor,             /* hasNativeMulFor */
   hasExtBitOp,                  /* hasExtBitOp */
   oclsExpense,                  /* oclsExpense */
-  TRUE,                         /* use_dw_for_init */
-  FALSE,                        /* little_endian */
+  true,                         /* use_dw_for_init */
+  false,                        /* little_endian */
   0,                            /* leave lt */
   0,                            /* leave gt */
   1,                            /* transform <= to ! > */
   1,                            /* transform >= to ! < */
   1,                            /* transform != to !(a == b) */
   0,                            /* leave == */
-  FALSE,                        /* No array initializer support. */
+  false,                        /* No array initializer support. */
   cseCostEstimation,
   NULL,                         /* no builtin functions */
   GPOINTER,                     /* treat unqualified pointers as "generic" pointers */
diff -Nru sdcc-4.0.0+dfsg/src/hc08/ralloc2.cc sdcc-4.2.0+dfsg/src/hc08/ralloc2.cc
--- sdcc-4.0.0+dfsg/src/hc08/ralloc2.cc	2018-12-12 11:10:32.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/hc08/ralloc2.cc	2022-01-29 22:29:15.000000000 +0000
@@ -15,6 +15,8 @@
 // You should have received a copy of the GNU General Public License
 // along with this program; if not, write to the Free Software
 // Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+//
+// An optimal, polynomial-time register allocator.
 
 //#define DEBUG_RALLOC_DEC // Uncomment to get debug messages while doing register allocation on the tree decomposition.
 //#define DEBUG_RALLOC_DEC_ASS // Uncomment to get debug messages about assignments while doing register allocation on the tree decomposition (much more verbose than the one above).
@@ -28,7 +30,7 @@
 {
   #include "ralloc.h"
   #include "gen.h"
-  unsigned char dryhc08iCode (iCode *ic);
+  float dryhc08iCode (iCode *ic);
   bool hc08_assignment_optimal;
 }
 
@@ -87,6 +89,9 @@
   if(!o || !IS_SYMOP(o))
     return(false);
 
+  if(r >= port->num_regs)
+    return(false);
+
   operand_map_t::const_iterator oi, oi_end;
   for(boost::tie(oi, oi_end) = G[i].operands.equal_range(OP_SYMBOL_CONST(o)->key); oi != oi_end; ++oi)
     if(oi->second == ia.registers[r][1] || oi->second == ia.registers[r][0])
@@ -95,60 +100,6 @@
   return(false);
 }
 
-// Check that the operand is either fully in registers or fully in memory.
-template 
-static bool operand_sane(const operand *o, const assignment &a, unsigned short int i, const G_t &G, const I_t &I)
-{
-  if(!o || !IS_SYMOP(o))
-    return(true);
- 
-  operand_map_t::const_iterator oi, oi2, oi_end;
-  boost::tie(oi, oi_end) = G[i].operands.equal_range(OP_SYMBOL_CONST(o)->key);
-  
-  if(oi == oi_end)
-    return(true);
-
-  // Go to the second byte. If the operand is only a single byte, it cannot be
-  // an unsupported register combination or split between register and memory.
-  oi2 = oi;
-  oi2++;
-  if (oi2 == oi_end)
-    return(true);
-  
-  // Register combinations code generation cannot handle yet (AH, XH, HA).
-  if(std::binary_search(a.local.begin(), a.local.end(), oi->second) && std::binary_search(a.local.begin(), a.local.end(), oi2->second))
-    {
-      const reg_t l = a.global[oi->second];
-      const reg_t h = a.global[oi2->second];
-      if(l == REG_A && h == REG_H || l == REG_H)
-        return(false);
-    }
-  
-  // In registers.
-  if(std::binary_search(a.local.begin(), a.local.end(), oi->second))
-    {
-      while(++oi != oi_end)
-        if(!std::binary_search(a.local.begin(), a.local.end(), oi->second))
-          return(false);
-    }
-  else
-    {
-       while(++oi != oi_end)
-        if(std::binary_search(a.local.begin(), a.local.end(), oi->second))
-          return(false);
-    }
- 
-  return(true);
-}
-
-template 
-static bool inst_sane(const assignment &a, unsigned short int i, const G_t &G, const I_t &I)
-{
-  const iCode *ic = G[i].ic;
-
-  return(operand_sane(IC_RESULT(ic), a, i, G, I) && operand_sane(IC_LEFT(ic), a, i, G, I) && operand_sane(IC_RIGHT(ic), a, i, G, I));
-}
-
 template 
 static bool operand_is_ax(const operand *o, const assignment &a, unsigned short int i, const G_t &G, const I_t &I)
 {  
@@ -416,6 +367,60 @@
     }
 }
 
+// Check that the operand is either fully in registers or fully in memory.
+template 
+static bool operand_sane(const operand *o, const assignment &a, unsigned short int i, const G_t &G, const I_t &I)
+{
+  if(!o || !IS_SYMOP(o))
+    return(true);
+ 
+  operand_map_t::const_iterator oi, oi2, oi_end;
+  boost::tie(oi, oi_end) = G[i].operands.equal_range(OP_SYMBOL_CONST(o)->key);
+  
+  if(oi == oi_end)
+    return(true);
+
+  // Go to the second byte. If the operand is only a single byte, it cannot be
+  // an unsupported register combination or split between register and memory.
+  oi2 = oi;
+  oi2++;
+  if (oi2 == oi_end)
+    return(true);
+  
+  // Register combinations code generation cannot handle yet (AH, XH, HA).
+  if(std::binary_search(a.local.begin(), a.local.end(), oi->second) && std::binary_search(a.local.begin(), a.local.end(), oi2->second))
+    {
+      const reg_t l = a.global[oi->second];
+      const reg_t h = a.global[oi2->second];
+      if(l == REG_A && h == REG_H || l == REG_H)
+        return(false);
+    }
+  
+  // In registers.
+  if(std::binary_search(a.local.begin(), a.local.end(), oi->second))
+    {
+      while(++oi != oi_end)
+        if(!std::binary_search(a.local.begin(), a.local.end(), oi->second))
+          return(false);
+    }
+  else
+    {
+       while(++oi != oi_end)
+        if(std::binary_search(a.local.begin(), a.local.end(), oi->second))
+          return(false);
+    }
+ 
+  return(true);
+}
+
+template 
+static bool inst_sane(const assignment &a, unsigned short int i, const G_t &G, const I_t &I)
+{
+  const iCode *ic = G[i].ic;
+
+  return(operand_sane(IC_RESULT(ic), a, i, G, I) && operand_sane(IC_LEFT(ic), a, i, G, I) && operand_sane(IC_RIGHT(ic), a, i, G, I));
+}
+
 // Cost function.
 template 
 static float instruction_cost(const assignment &a, unsigned short int i, const G_t &G, const I_t &I)
@@ -428,12 +433,6 @@
   if(!inst_sane(a, i, G, I))
     return(std::numeric_limits::infinity());
 
-  if(!XAinst_ok(a, i, G, I))
-    return(std::numeric_limits::infinity());
-
-  if(!AXinst_ok(a, i, G, I))
-    return(std::numeric_limits::infinity());
-
 #if 0
   std::cout << "Calculating at cost at ic " << ic->key << " for: ";
   for(unsigned int i = 0; i < boost::num_vertices(I); i++)
@@ -447,6 +446,12 @@
   if(ic->generated)
     return(0.0f);
 
+  if(!XAinst_ok(a, i, G, I))
+    return(std::numeric_limits::infinity());
+
+  if(!AXinst_ok(a, i, G, I))
+    return(std::numeric_limits::infinity());
+
   switch(ic->op)
     {
     // Register assignment doesn't matter for these:
@@ -500,6 +505,7 @@
       assign_operands_for_cost(a, i, G, I);
       set_surviving_regs(a, i, G, I);
       c = dryhc08iCode(ic);
+      ic->generated = false;
       return(c);
     default:
       return(0.0f);
@@ -634,7 +640,6 @@
 
 iCode *hc08_ralloc2_cc(ebbIndex *ebbi)
 {
-  iCode *ic;
 
 #ifdef DEBUG_RALLOC_DEC
   std::cout << "Processing " << currFunc->name << " from " << dstFileName << "\n"; std::cout.flush();
@@ -644,7 +649,7 @@
 
   con_t conflict_graph;
 
-  ic = create_cfg(control_flow_graph, conflict_graph, ebbi);
+  iCode *ic = create_cfg(control_flow_graph, conflict_graph, ebbi);
 
   if(options.dump_graphs)
     dump_cfg(control_flow_graph);
diff -Nru sdcc-4.0.0+dfsg/src/hc08/ralloc.c sdcc-4.2.0+dfsg/src/hc08/ralloc.c
--- sdcc-4.0.0+dfsg/src/hc08/ralloc.c	2019-06-29 04:30:58.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/hc08/ralloc.c	2022-01-10 22:03:26.000000000 +0000
@@ -105,7 +105,7 @@
 }
 
 /*-----------------------------------------------------------------*/
-/* hc08_freeReg - frees a register                                      */
+/* hc08_freeReg - frees a register                                 */
 /*-----------------------------------------------------------------*/
 void
 hc08_freeReg (reg_info * reg)
@@ -795,13 +795,13 @@
           if (sym->ruonly || sym->accuse)
             {
               if (IS_AGGREGATE (sym->type) || sym->isptr)
-                sym->type = aggrToPtr (sym->type, FALSE);
+                sym->type = aggrToPtr (sym->type, false);
               continue;
             }
 
           /* if not then we require registers */
           sym->nRegs = ((IS_AGGREGATE (sym->type) || sym->isptr) ?
-                        getSize (sym->type = aggrToPtr (sym->type, FALSE)) :
+                        getSize (sym->type = aggrToPtr (sym->type, false)) :
                         getSize (sym->type));
 
           if (sym->nRegs > 8)
@@ -1100,11 +1100,11 @@
     return NULL;
 
   /* if the symbol is volatile then we should not */
-  if (isOperandVolatile (IC_RIGHT (dic), TRUE))
+  if (isOperandVolatile (IC_RIGHT (dic), true))
     return NULL;
-  /* XXX TODO --- should we be passing FALSE to isOperandVolatile()?
+  /* XXX TODO --- should we be passing false to isOperandVolatile()?
      What does it mean for an iTemp to be volatile, anyway? Passing
-     TRUE is more cautious but may prevent possible optimizations */
+     true is more cautious but may prevent possible optimizations */
 
   /* if the symbol is in far space then we should not */
   /* if (isOperandInFarSpace (IC_RIGHT (dic)))
@@ -1156,7 +1156,7 @@
 
   /* update the sym's liverange */
   if ( OP_LIVETO(op) < ic->seq )
-    setToRange(op, ic->seq, FALSE);
+    setToRange(op, ic->seq, false);
 
   /* remove the assignment iCode now that its result is unused */
   remiCodeFromeBBlock (ebp, assignment);
@@ -1208,162 +1208,6 @@
   return changes;
 }
 
-
-#if 0
-/*-----------------------------------------------------------------*/
-/* packRegsForOneuse : - will reduce some registers for single Use */
-/*-----------------------------------------------------------------*/
-static iCode *
-packRegsForOneuse (iCode * ic, operand * op, eBBlock * ebp)
-{
-  bitVect *uses;
-  iCode *dic, *sic;
-
-  /* if returning a literal then do nothing */
-  if (!IS_SYMOP (op))
-    return NULL;
-
-  /* only up to 2 bytes */
-  if (getSize (operandType (op)) > (fReturnSizeHC08 - 2))
-    return NULL;
-
-  return NULL;
-
-  if (ic->op != SEND && //RETURN
-      ic->op != SEND &&
-      !POINTER_SET (ic) &&
-      !POINTER_GET (ic))
-    return NULL;
-
-  if (ic->op == SEND && ic->argreg != 1)
-    return NULL;
-
-  /* this routine will mark the symbol as used in one
-     instruction use only && if the definition is local
-     (ie. within the basic block) && has only one definition &&
-     that definition is either a return value from a
-     function or does not contain any variables in
-     far space */
-  uses = bitVectCopy (OP_USES (op));
-  bitVectUnSetBit (uses, ic->key);      /* take away this iCode */
-  if (!bitVectIsZero (uses))    /* has other uses */
-    return NULL;
-
-  /* if it has only one definition */
-  if (bitVectnBitsOn (OP_DEFS (op)) > 1)
-    return NULL;                /* has more than one definition */
-
-  /* get that definition */
-  if (!(dic = hTabItemWithKey (iCodehTab, bitVectFirstBit (OP_DEFS (op)))))
-    return NULL;
-
-  /* if that only usage is a cast */
-  if (dic->op == CAST)
-    {
-      /* to a bigger type */
-      if (getSize(OP_SYM_TYPE(IC_RESULT(dic))) > getSize(OP_SYM_TYPE(IC_RIGHT(dic))))
-        {
-          /* then we can not, since we cannot predict the usage of b & acc */
-          return NULL;
-        }
-    }
-
-  /* found the definition now check if it is local */
-  if (dic->seq < ebp->fSeq || dic->seq > ebp->lSeq)
-    return NULL;                /* non-local */
-
-  /* now check if it is the return from a function call */
-  if (dic->op == CALL || dic->op == PCALL)
-    {
-      if (ic->op != SEND && ic->op != RETURN &&
-          !POINTER_SET(ic) && !POINTER_GET(ic))
-        {
-          OP_SYMBOL (op)->ruonly = 1;
-          return dic;
-        }
-      dic = dic->next;
-    }
-
-
-//  /* otherwise check that the definition does
-//     not contain any symbols in far space */
-//  if (isOperandInFarSpace (IC_LEFT (dic)) ||
-//      isOperandInFarSpace (IC_RIGHT (dic)) ||
-//      IS_OP_RUONLY (IC_LEFT (ic)) ||
-//      IS_OP_RUONLY (IC_RIGHT (ic)))
-//    {
-//      return NULL;
-//    }
-
-  /* if pointer set then make sure the pointer
-     is one byte */
-#if 0
-  if (POINTER_SET (dic) &&
-      !IS_DATA_PTR (aggrToPtr (operandType (IC_RESULT (dic)), FALSE)))
-    return NULL;
-
-  if (POINTER_GET (dic) &&
-      !IS_DATA_PTR (aggrToPtr (operandType (IC_LEFT (dic)), FALSE)))
-    return NULL;
-#endif
-
-  sic = dic;
-
-  /* make sure the intervening instructions
-     don't have anything in far space */
-  for (dic = dic->next; dic && dic != ic && sic != ic; dic = dic->next)
-    {
-      /* if there is an intervening function call then no */
-      if (dic->op == CALL || dic->op == PCALL)
-        return NULL;
-      /* if pointer set then make sure the pointer
-         is one byte */
-#if 0
-      if (POINTER_SET (dic) &&
-          !IS_DATA_PTR (aggrToPtr (operandType (IC_RESULT (dic)), FALSE)))
-        return NULL;
-
-      if (POINTER_GET (dic) &&
-          !IS_DATA_PTR (aggrToPtr (operandType (IC_LEFT (dic)), FALSE)))
-        return NULL;
-#endif
-      /* if address of & the result is remat then okay */
-      if (dic->op == ADDRESS_OF &&
-          OP_SYMBOL (IC_RESULT (dic))->remat)
-        continue;
-
-      /* if operand has size of three or more & this
-         operation is a '*','/' or '%' then 'b' may
-         cause a problem */
-#if 0
-      if ((dic->op == '%' || dic->op == '/' || dic->op == '*') &&
-          getSize (operandType (op)) >= 3)
-        return NULL;
-#endif
-
-      /* if left or right or result is in far space */
-//      if (isOperandInFarSpace (IC_LEFT (dic)) ||
-//        isOperandInFarSpace (IC_RIGHT (dic)) ||
-//        isOperandInFarSpace (IC_RESULT (dic)) ||
-//        IS_OP_RUONLY (IC_LEFT (dic)) ||
-//        IS_OP_RUONLY (IC_RIGHT (dic)) ||
-//        IS_OP_RUONLY (IC_RESULT (dic)))
-//      {
-//        return NULL;
-//      }
-//      /* if left or right or result is on stack */
-//     if (isOperandOnStack(IC_LEFT(dic)) ||
-//        isOperandOnStack(IC_RIGHT(dic)) ||
-//        isOperandOnStack(IC_RESULT(dic))) {
-//      return NULL;
-//     }
-    }
-
-  OP_SYMBOL (op)->ruonly = 1;
-  return sic;
-}
-#endif
-
 /*-----------------------------------------------------------------*/
 /* isBitwiseOptimizable - requirements of JEAN LOUIS VERN          */
 /*-----------------------------------------------------------------*/
@@ -1388,59 +1232,9 @@
   */
   if (IS_LITERAL(rtype) ||
       (IS_BITVAR (ltype) && IN_BITSPACE (SPEC_OCLS (ltype))))
-    return TRUE;
+    return true;
   else
-    return FALSE;
-}
-
-/*-----------------------------------------------------------------*/
-/* isCommutativeOp - tests whether this op cares what order its    */
-/*                   operands are in                               */
-/*-----------------------------------------------------------------*/
-bool isCommutativeOp2(unsigned int op)
-{
-  if (op == '+' || op == '*' || op == EQ_OP ||
-      op == '^' || op == '|' || op == BITWISEAND)
-    return TRUE;
-  else
-    return FALSE;
-}
-
-/*-----------------------------------------------------------------*/
-/* operandUsesAcc2 - determines whether the code generated for this */
-/*                  operand will have to use the accumulator       */
-/*-----------------------------------------------------------------*/
-bool operandUsesAcc2(operand *op)
-{
-  if (!op)
-    return FALSE;
-
-  if (IS_SYMOP(op)) {
-    symbol *sym = OP_SYMBOL(op);
-    memmap *symspace;
-
-    if (sym->accuse)
-      return TRUE;  /* duh! */
-
-    if (IS_ITEMP(op))
-      {
-        if (SPIL_LOC(op)) {
-          sym = SPIL_LOC(op);  /* if spilled, look at spill location */
-        } else {
-          return FALSE;  /* more checks? */
-        }
-      }
-
-    symspace = SPEC_OCLS(sym->etype);
-
-    if (IN_BITSPACE(symspace))
-      return TRUE;  /* fetching bit vars uses the accumulator */
-
-    if (IN_FARSPACE(symspace) || IN_CODESPACE(symspace))
-      return TRUE;  /* fetched via accumulator and dptr */
-  }
-
-  return FALSE;
+    return false;
 }
 
 /*-----------------------------------------------------------------*/
@@ -1604,12 +1398,12 @@
 /* packForPush - heuristics to reduce iCode for pushing            */
 /*-----------------------------------------------------------------*/
 static void
-packForPush (iCode * ic, eBBlock ** ebpp, int blockno)
+packForPush (iCode * ic, eBBlock ** ebpp, int count)
 {
   iCode *dic, *lic;
   bitVect *dbv;
-  struct eBBlock * ebp=ebpp[blockno];
   int disallowHiddenAssignment = 0;
+  eBBlock * ebp = ebpp[ic->eBBlockNum];
 
   if ((ic->op != IPUSH && ic->op != SEND) || !IS_ITEMP (IC_LEFT (ic)))
     return;
@@ -1627,10 +1421,10 @@
   if (dic->op != '=' || POINTER_SET (dic))
     return;
 
-  if (dic->seq < ebp->fSeq) // Evelyn did this
+  if (dic->seq < ebp->fSeq || dic->seq > ebp->lSeq) // Evelyn did this
     {
       int i;
-      for (i=0; iseq >= ebpp[i]->fSeq && dic->seq <= ebpp[i]->lSeq)
             {
@@ -1638,7 +1432,8 @@
               break;
             }
         }
-      wassert (i!=blockno); // no way to recover from here
+      if (i==count) // Abort if we can't find the definition's block
+        return;
     }
 
   if (IS_SYMOP(IC_RIGHT(dic)))
@@ -1850,144 +1645,149 @@
 /*                   pressure                                      */
 /*-----------------------------------------------------------------*/
 static void
-packRegisters (eBBlock ** ebpp, int blockno)
+packRegisters (eBBlock ** ebpp, int count)
 {
   iCode *ic;
   int change = 0;
-  eBBlock *ebp = ebpp[blockno];
+  int blockno;
 
-  do
+  for (blockno=0; blocknosch; ic; ic = ic->next)
+      do
         {
-          /* find assignment of the form TrueSym := iTempNN:1 */
-          if (ic->op == '=' && !POINTER_SET (ic))
-            change += packRegsForAssign (ic, ebp);
+          change = 0;
+
+          /* look for assignments of the form */
+          /* iTempNN = TrueSym (someoperation) SomeOperand */
+          /*       ....                       */
+          /* TrueSym := iTempNN:1             */
+          for (ic = ebp->sch; ic; ic = ic->next)
+            {
+              /* find assignment of the form TrueSym := iTempNN:1 */
+              if (ic->op == '=' && !POINTER_SET (ic))
+                change += packRegsForAssign (ic, ebp);
+            }
         }
-    }
-  while (change);
+      while (change);
 
-  for (ic = ebp->sch; ic; ic = ic->next)
-    {
-      //packRegsForLiteral (ic);
-      
-      /* move SEND to immediately precede its CALL/PCALL */
-      if (ic->op == SEND && ic->next &&
-          ic->next->op != CALL && ic->next->op != PCALL)
+      for (ic = ebp->sch; ic; ic = ic->next)
         {
-          ic = moveSendToCall (ic, ebp);
-        }
+          //packRegsForLiteral (ic);
+      
+          /* move SEND to immediately precede its CALL/PCALL */
+          if (ic->op == SEND && ic->next &&
+              ic->next->op != CALL && ic->next->op != PCALL)
+            {
+              ic = moveSendToCall (ic, ebp);
+            }
       
-      /* if this is an itemp & result of an address of a true sym
-         then mark this as rematerialisable   */
-      if (ic->op == ADDRESS_OF &&
-          IS_ITEMP (IC_RESULT (ic)) &&
-          IS_TRUE_SYMOP (IC_LEFT (ic)) &&
-          bitVectnBitsOn (OP_DEFS (IC_RESULT (ic))) == 1 &&
-          !OP_SYMBOL (IC_LEFT (ic))->onStack)
-        {
-          OP_SYMBOL (IC_RESULT (ic))->remat = 1;
-          OP_SYMBOL (IC_RESULT (ic))->rematiCode = ic;
-          OP_SYMBOL (IC_RESULT (ic))->usl.spillLoc = NULL;
-        }
-
-      /* if straight assignment then carry remat flag if
-         this is the only definition */
-      if (ic->op == '=' &&
-          !POINTER_SET (ic) &&
-          IS_SYMOP (IC_RIGHT (ic)) &&
-          OP_SYMBOL (IC_RIGHT (ic))->remat &&
-          bitVectnBitsOn (OP_SYMBOL (IC_RESULT (ic))->defs) <= 1 &&
-          !OP_SYMBOL (IC_RESULT (ic))->_isparm &&
-          !OP_SYMBOL (IC_RESULT (ic))->addrtaken &&
-          !isOperandGlobal (IC_RESULT (ic)))
-        {
-          OP_SYMBOL (IC_RESULT (ic))->remat = OP_SYMBOL (IC_RIGHT (ic))->remat;
-          OP_SYMBOL (IC_RESULT (ic))->rematiCode = OP_SYMBOL (IC_RIGHT (ic))->rematiCode;
-        }
-
-      /* if cast to a generic pointer & the pointer being
-         cast is remat, then we can remat this cast as well */
-      if (ic->op == CAST &&
-          IS_SYMOP(IC_RIGHT(ic)) &&
-          OP_SYMBOL(IC_RIGHT(ic))->remat &&
-          bitVectnBitsOn (OP_DEFS (IC_RESULT (ic))) == 1 &&
-          !OP_SYMBOL (IC_RESULT (ic))->_isparm &&
-          !OP_SYMBOL (IC_RESULT (ic))->addrtaken &&
-          !isOperandGlobal (IC_RESULT (ic)))
-        {
-          sym_link *to_type = operandType(IC_LEFT(ic));
-          sym_link *from_type = operandType(IC_RIGHT(ic));
-          if (IS_PTR(to_type) && IS_PTR(from_type))
+          /* if this is an itemp & result of an address of a true sym
+             then mark this as rematerialisable   */
+          if (ic->op == ADDRESS_OF &&
+              IS_ITEMP (IC_RESULT (ic)) &&
+              IS_TRUE_SYMOP (IC_LEFT (ic)) &&
+              bitVectnBitsOn (OP_DEFS (IC_RESULT (ic))) == 1 &&
+              !OP_SYMBOL (IC_LEFT (ic))->onStack)
             {
               OP_SYMBOL (IC_RESULT (ic))->remat = 1;
               OP_SYMBOL (IC_RESULT (ic))->rematiCode = ic;
               OP_SYMBOL (IC_RESULT (ic))->usl.spillLoc = NULL;
             }
-        }
 
-      /* if this is a +/- operation with a rematerizable
-         then mark this as rematerializable as well */
-      if ((ic->op == '+' || ic->op == '-') &&
-          (IS_SYMOP (IC_LEFT (ic)) &&
-           IS_ITEMP (IC_RESULT (ic)) &&
-           IS_OP_LITERAL (IC_RIGHT (ic))) &&
-           OP_SYMBOL (IC_LEFT (ic))->remat &&
-          (!IS_SYMOP (IC_RIGHT (ic)) || !IS_CAST_ICODE(OP_SYMBOL (IC_RIGHT (ic))->rematiCode)) &&
-           bitVectnBitsOn (OP_DEFS (IC_RESULT (ic))) == 1)
-        {
-          OP_SYMBOL (IC_RESULT (ic))->remat = 1;
-          OP_SYMBOL (IC_RESULT (ic))->rematiCode = ic;
-          OP_SYMBOL (IC_RESULT (ic))->usl.spillLoc = NULL;
-        }
-      /* mark the pointer usages */
-      if (POINTER_SET (ic) && IS_SYMOP (IC_RESULT (ic)))
-        OP_SYMBOL (IC_RESULT (ic))->uptr = 1;
-
-      if (POINTER_GET (ic) && IS_SYMOP (IC_LEFT (ic)))
-        OP_SYMBOL (IC_LEFT (ic))->uptr = 1;
-
-      /* reduce for support function calls */
-      if (ic->supportRtn || (ic->op != IFX && ic->op != JUMPTABLE))
-        packRegsForSupport (ic, ebp);
-
-      /* if the condition of an if instruction
-         is defined in the previous instruction and
-         this is the only usage then
-         mark the itemp as a conditional */
-      if ((IS_CONDITIONAL (ic) ||
-           (IS_BITWISE_OP(ic) && isBitwiseOptimizable (ic))) &&
-          ic->next && ic->next->op == IFX &&
-          bitVectnBitsOn (OP_USES(IC_RESULT(ic)))==1 &&
-          isOperandEqual (IC_RESULT (ic), IC_COND (ic->next)) &&
-          OP_SYMBOL (IC_RESULT (ic))->liveTo <= ic->next->seq)
-        {
-          OP_SYMBOL (IC_RESULT (ic))->regType = REG_CND;
-          continue;
-        }
+          /* if straight assignment then carry remat flag if
+             this is the only definition */
+          if (ic->op == '=' &&
+              !POINTER_SET (ic) &&
+              IS_SYMOP (IC_RIGHT (ic)) &&
+              OP_SYMBOL (IC_RIGHT (ic))->remat &&
+              bitVectnBitsOn (OP_SYMBOL (IC_RESULT (ic))->defs) <= 1 &&
+              !OP_SYMBOL (IC_RESULT (ic))->_isparm &&
+              !OP_SYMBOL (IC_RESULT (ic))->addrtaken &&
+              !isOperandGlobal (IC_RESULT (ic)))
+            {
+              OP_SYMBOL (IC_RESULT (ic))->remat = OP_SYMBOL (IC_RIGHT (ic))->remat;
+              OP_SYMBOL (IC_RESULT (ic))->rematiCode = OP_SYMBOL (IC_RIGHT (ic))->rematiCode;
+            }
+
+          /* if cast to a generic pointer & the pointer being
+             cast is remat, then we can remat this cast as well */
+          if (ic->op == CAST &&
+              IS_SYMOP(IC_RIGHT(ic)) &&
+              OP_SYMBOL(IC_RIGHT(ic))->remat &&
+              bitVectnBitsOn (OP_DEFS (IC_RESULT (ic))) == 1 &&
+              !OP_SYMBOL (IC_RESULT (ic))->_isparm &&
+              !OP_SYMBOL (IC_RESULT (ic))->addrtaken &&
+              !isOperandGlobal (IC_RESULT (ic)))
+            {
+              sym_link *to_type = operandType(IC_LEFT(ic));
+              sym_link *from_type = operandType(IC_RIGHT(ic));
+              if (IS_PTR(to_type) && IS_PTR(from_type))
+                {
+                  OP_SYMBOL (IC_RESULT (ic))->remat = 1;
+                  OP_SYMBOL (IC_RESULT (ic))->rematiCode = ic;
+                  OP_SYMBOL (IC_RESULT (ic))->usl.spillLoc = NULL;
+                }
+            }
 
-      /* pack for PUSH
-         iTempNN := (some variable in farspace) V1
-         push iTempNN ;
-         -------------
-         push V1
-       */
-      if (ic->op == IPUSH || ic->op == SEND)
-        {
-          packForPush (ic, ebpp, blockno);
-        }
+          /* if this is a +/- operation with a rematerizable
+             then mark this as rematerializable as well */
+          if ((ic->op == '+' || ic->op == '-') &&
+              (IS_SYMOP (IC_LEFT (ic)) &&
+               IS_ITEMP (IC_RESULT (ic)) &&
+               IS_OP_LITERAL (IC_RIGHT (ic))) &&
+               OP_SYMBOL (IC_LEFT (ic))->remat &&
+              (!IS_SYMOP (IC_RIGHT (ic)) || !IS_CAST_ICODE(OP_SYMBOL (IC_RIGHT (ic))->rematiCode)) &&
+               bitVectnBitsOn (OP_DEFS (IC_RESULT (ic))) == 1)
+            {
+              OP_SYMBOL (IC_RESULT (ic))->remat = 1;
+              OP_SYMBOL (IC_RESULT (ic))->rematiCode = ic;
+              OP_SYMBOL (IC_RESULT (ic))->usl.spillLoc = NULL;
+            }
+          /* mark the pointer usages */
+          if (POINTER_SET (ic) && IS_SYMOP (IC_RESULT (ic)))
+            OP_SYMBOL (IC_RESULT (ic))->uptr = 1;
+
+          if (POINTER_GET (ic) && IS_SYMOP (IC_LEFT (ic)))
+            OP_SYMBOL (IC_LEFT (ic))->uptr = 1;
+
+          /* reduce for support function calls */
+          if (ic->supportRtn || (ic->op != IFX && ic->op != JUMPTABLE))
+            packRegsForSupport (ic, ebp);
+
+          /* if the condition of an if instruction
+             is defined in the previous instruction and
+             this is the only usage then
+             mark the itemp as a conditional */
+          if ((IS_CONDITIONAL (ic) ||
+               (IS_BITWISE_OP(ic) && isBitwiseOptimizable (ic))) &&
+              ic->next && ic->next->op == IFX &&
+              bitVectnBitsOn (OP_USES(IC_RESULT(ic)))==1 &&
+              isOperandEqual (IC_RESULT (ic), IC_COND (ic->next)) &&
+              OP_SYMBOL (IC_RESULT (ic))->liveTo <= ic->next->seq)
+            {
+              OP_SYMBOL (IC_RESULT (ic))->regType = REG_CND;
+              continue;
+            }
 
-      if (POINTER_SET (ic) || POINTER_GET (ic))
-        packPointerOp (ic, ebpp);
+          /* pack for PUSH
+             iTempNN := (some variable in farspace) V1
+             push iTempNN ;
+             -------------
+             push V1
+           */
+          if (ic->op == IPUSH || ic->op == SEND)
+            {
+              packForPush (ic, ebpp, count);
+            }
 
-      if (options.oldralloc)
-        packRegsForAccUse (ic);
+          if (POINTER_SET (ic) || POINTER_GET (ic))
+            packPointerOp (ic, ebpp);
+
+          if (options.oldralloc)
+            packRegsForAccUse (ic);
+        }
     }
 }
 
@@ -2111,7 +1911,6 @@
   eBBlock ** ebbs = ebbi->bbOrder;
   int count = ebbi->count;
   iCode *ic;
-  int i;
 
   setToNull ((void *) &_G.funcrUsed);
   setToNull ((void *) &_G.regAssigned);
@@ -2129,12 +1928,11 @@
   /* change assignments this will remove some
      live ranges reducing some register pressure */
 
-  for (i = 0; i < count; i++)
-    packRegisters (ebbs, i);
+  packRegisters (ebbs, count);
 
   /* liveranges probably changed by register packing
      so we compute them again */
-  recomputeLiveRanges (ebbs, count, FALSE);
+  recomputeLiveRanges (ebbs, count, false);
 
   if (options.dump_i_code)
     dumpEbbsToFileExt (DUMP_PACK, ebbi);
@@ -2312,6 +2110,7 @@
         }
     }
 }
+
 /*-----------------------------------------------------------------*/
 /* New register allocator                                          */
 /*-----------------------------------------------------------------*/
@@ -2321,7 +2120,6 @@
   eBBlock ** ebbs = ebbi->bbOrder;
   int count = ebbi->count;
   iCode *ic;
-  int i;
 
   setToNull ((void *) &_G.funcrUsed);
   setToNull ((void *) &_G.regAssigned);
@@ -2339,12 +2137,11 @@
   /* change assignments this will remove some
      live ranges reducing some register pressure */
 
-  for (i = 0; i < count; i++)
-    packRegisters (ebbs, i);
+  packRegisters (ebbs, count);
 
   /* liveranges probably changed by register packing
      so we compute them again */
-  recomputeLiveRanges (ebbs, count, FALSE);
+  recomputeLiveRanges (ebbs, count, false);
 
   if (options.dump_i_code)
     dumpEbbsToFileExt (DUMP_PACK, ebbi);
diff -Nru sdcc-4.0.0+dfsg/src/Makefile.in sdcc-4.2.0+dfsg/src/Makefile.in
--- sdcc-4.0.0+dfsg/src/Makefile.in	2018-03-04 12:45:01.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/Makefile.in	2021-02-02 11:58:59.000000000 +0000
@@ -28,7 +28,7 @@
 
 SLIBOBJS        = NewAlloc.o dbuf.o dbuf_string.o findme.o
 
-OBJECTS         = SDCCy.o SDCChasht.o SDCCmain.o \
+OBJECTS         = SDCCy.o SDCChasht.o SDCCmain.o SDCCattr.o \
                   SDCCsymt.o SDCCopt.o SDCCast.o SDCCmem.o SDCCval.o \
                   SDCCicode.o SDCCbitv.o SDCCset.o SDCClabel.o \
                   SDCCBBlock.o SDCCloop.o SDCCcse.o SDCCcflow.o SDCCdflow.o \
@@ -111,7 +111,7 @@
 # My rules
 # --------
 $(TARGET): $(SLIBOBJS) $(OBJECTS) $(PORT_LIBS)
-	$(CXX) $(LDFLAGS) -o $@ $(SLIBOBJS) $(OBJECTS) $(PORT_LIBS) $(LIBDIRS) $(LIBS)
+	$(CXX) $(CXXFLAGS) $(LDFLAGS) -o $@ $(SLIBOBJS) $(OBJECTS) $(PORT_LIBS) $(LIBDIRS) $(LIBS)
 
 .c.o:
 	$(CC) $(CFLAGS) $(CPPFLAGS) -c $< -o $@
diff -Nru sdcc-4.0.0+dfsg/src/mcs51/gen.c sdcc-4.2.0+dfsg/src/mcs51/gen.c
--- sdcc-4.0.0+dfsg/src/mcs51/gen.c	2019-03-14 16:34:34.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/mcs51/gen.c	2021-07-13 08:19:08.000000000 +0000
@@ -1030,6 +1030,7 @@
   if (sym->regType == REG_CND)
     {
       sym->aop = op->aop = aop = newAsmop (AOP_CRY);
+      aop->aopu.aop_dir = "c";
       aop->size = sym->ruonly ? 1 : 0;
       return;
     }
@@ -1522,7 +1523,7 @@
           break;
 
         case AOP_CRY:
-          if (!IS_OP_RUONLY (oper))
+          if (!EQ (aop->aopu.aop_dir, "c"))
             emitcode ("mov", "c,%s", aop->aopu.aop_dir);
           emitcode ("clr", "a");
           emitcode ("rlc", "a");
@@ -1614,7 +1615,6 @@
   bool bvolatile = isOperandVolatile (result, FALSE);
   bool accuse = FALSE;
   asmop *aop = AOP (result);
-  const char *d = NULL;
   static struct dbuf_s dbuf = { 0 };
 
   if (dbuf_is_initialized (&dbuf))
@@ -1712,6 +1712,13 @@
 
     case AOP_R0:
     case AOP_R1:
+      /* Get source in A before inc/dec of r0/r1 */
+      /* in case source needed different offset  */
+      if (aop->paged || *s == '@')
+        {
+          MOVA (s);
+        }
+        
       while (offset > aop->coff)
         {
           aop->coff++;
@@ -1726,12 +1733,12 @@
 
       if (aop->paged)
         {
-          MOVA (s);
+          /* source already in A */
           emitcode ("movx", "@%s,a", aop->aopu.aop_ptr->name);
         }
       else if (*s == '@')
         {
-          MOVA (s);
+          /* source already in A */
           emitcode ("mov", "@%s,a", aop->aopu.aop_ptr->name);
         }
       else if (EQ (s, "r0") || EQ (s, "r1") || EQ (s, "r2") || EQ (s, "r3") ||
@@ -1751,9 +1758,6 @@
       break;
 
     case AOP_CRY:
-      // destination is carry for return-use-only
-      d = (IS_OP_RUONLY (result)) ? "c" : aop->aopu.aop_dir;
-
       // source is no literal and not in carry
       if (!EQ (s, zero) && !EQ (s, one) && !EQ (s, "c"))
         {
@@ -1765,7 +1769,7 @@
       // now source is zero, one or carry
 
       /* if result no bit variable */
-      if (!d)
+      if (!aop->aopu.aop_dir)
         {
           if (EQ (s, "c"))
             {
@@ -1781,11 +1785,11 @@
             }
         }
       else if (EQ (s, zero))
-        emitcode ("clr", "%s", d);
+        emitcode ("clr", "%s", aop->aopu.aop_dir);
       else if (EQ (s, one))
-        emitcode ("setb", "%s", d);
-      else if (!EQ (s, d))
-        emitcode ("mov", "%s,c", d);
+        emitcode ("setb", "%s", aop->aopu.aop_dir);
+      else if (!EQ (s, aop->aopu.aop_dir))
+        emitcode ("mov", "%s,c", aop->aopu.aop_dir);
       break;
 
     case AOP_STR:
@@ -1952,8 +1956,7 @@
   /* if the result is bit */
   if (AOP_TYPE (result) == AOP_CRY)
     {
-      if (!IS_OP_RUONLY (result) && !IS_OP_ACCUSE (result))
-        aopPut (result, "c", 0);
+      aopPut (result, "c", 0);
     }
   else if (AOP_TYPE (result) != AOP_DUMMY)
     {
@@ -2025,7 +2028,7 @@
 /*-----------------------------------------------------------------*/
 static void
 toCarry (operand *oper)
-{ 
+{
   /* if the operand is a literal then
      we know what the value is */
   if (AOP_TYPE (oper) == AOP_LIT)
@@ -3384,7 +3387,9 @@
 
   D (emitcode (";", "genPcall"));
 
-  dtype = operandType (IC_LEFT (ic))->next;
+  dtype = operandType (IC_LEFT (ic));
+  if (IS_FUNCPTR (dtype))
+    dtype = dtype->next;
   etype = getSpec (dtype);
   /* if caller saves & we have not saved then */
   if (!ic->regsSaved)
@@ -4968,6 +4973,7 @@
     {
       symbol *tlbl;
       const char *l;
+      unsigned int offset;
 
       tlbl = newiTempLabel (NULL);
       l = aopGet (IC_RESULT (ic), LSB, FALSE, FALSE);
@@ -4984,7 +4990,8 @@
         }
       l = aopGet (IC_RESULT (ic), MSB16, FALSE, FALSE);
       emitcode ("dec", "%s", l);
-      if (size > 2)
+
+      for (offset=2; offset < size; offset++)
         {
           if (EQ (l, "acc"))
             {
@@ -4998,25 +5005,10 @@
             {
               emitcode ("cjne", "a,%s,!tlabel", l, labelKey2num (tlbl->key));
             }
-          l = aopGet (IC_RESULT (ic), MSB24, FALSE, FALSE);
+          l = aopGet (IC_RESULT (ic), offset, FALSE, FALSE);
           emitcode ("dec", "%s", l);
         }
-      if (size > 3)
-        {
-          if (EQ (l, "acc"))
-            {
-              emitcode ("jnz", "!tlabel", labelKey2num (tlbl->key));
-            }
-          else if (AOP_TYPE (IC_RESULT (ic)) == AOP_REG || IS_AOP_PREG (IC_RESULT (ic)))
-            {
-              emitcode ("cjne", "%s,#!constbyte,!tlabel", l, 0xff, labelKey2num (tlbl->key));
-            }
-          else
-            {
-              emitcode ("cjne", "a,%s,!tlabel", l, labelKey2num (tlbl->key));
-            }
-          emitcode ("dec", "%s", aopGet (IC_RESULT (ic), MSB32, FALSE, FALSE));
-        }
+
       emitLabel (tlbl);
       return TRUE;
     }
@@ -6214,7 +6206,7 @@
                   if (!rightInB)
                     {
                       pushedB = pushB ();
-                      rightInB++;
+                      rightInB = TRUE;
                       MOVB (aopGet (right, offset, FALSE, FALSE));
                     }
                   emitcode ("xrl", "b,#0x80");
@@ -8399,10 +8391,12 @@
       else if (operandsEqu (left, result))
         {
           char *reg = "a";
+          const char *src;
           bool pushedB = FALSE, leftInB = FALSE;
 
-          MOVA (aopGet (left, 0, FALSE, FALSE));
-          if (aopGetUsesAcc (left, 1) || aopGetUsesAcc (result, 0))
+          src = aopGet (left, 0, FALSE, FALSE);
+          MOVA (src);
+          if (aopGetUsesAcc (left, 1) || aopGetUsesAcc (result, 0) || aopPutUsesAcc (result, src, 0))
             {
               pushedB = pushB ();
               emitcode ("mov", "b,a");
@@ -9041,7 +9035,7 @@
     {
       shiftLLong (left, result, full_bytes);
     }
-  else if ((shCount == 2) && (full_bytes == 0))
+  else if ((shCount == 2) && (full_bytes == 0) && !isOperandVolatile (result, FALSE))
     {
       shiftLLong (left, result, full_bytes);
       shiftLLong (result, result, full_bytes);
@@ -9060,7 +9054,7 @@
           shiftL1Left2Result (left, LSB, result, full_bytes, shCount);
         }
     }
-  for (b = LSB; b < full_bytes; b++)
+  for (b = LSB; b < full_bytes && b < size; b++)
     aopPut (result, zero, b);
   return;
 }
@@ -12276,10 +12270,6 @@
           genRLC (ic);
           break;
 
-        case GETHBIT:
-          assert (0);
-          break;
-
         case GETABIT:
           genGetAbit (ic);
           break;
diff -Nru sdcc-4.0.0+dfsg/src/mcs51/main.c sdcc-4.2.0+dfsg/src/mcs51/main.c
--- sdcc-4.0.0+dfsg/src/mcs51/main.c	2018-12-31 16:42:10.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/mcs51/main.c	2021-08-08 17:13:19.000000000 +0000
@@ -51,8 +51,6 @@
     { 0, OPTION_HUGE_MODEL, NULL, "functions are banked, data in external space"},
     { 0, OPTION_STACK_SIZE,  &options.stack_size, "Tells the linker to allocate this space for stack", CLAT_INTEGER },
     { 0, "--parms-in-bank1", &options.parms_in_bank1, "use Bank1 for parameter passing"},
-    { 0, "--pack-iram",      NULL, "Tells the linker to pack variables in internal ram (default)"},
-    { 0, "--no-pack-iram",   &options.no_pack_iram, "Deprecated: Tells the linker not to pack variables in internal ram"},
     { 0, "--acall-ajmp",     &options.acall_ajmp, "Use acall/ajmp instead of lcall/ljmp" },
     { 0, "--no-ret-without-call", &options.no_ret_without_call, "Do not use ret independent of acall/lcall" },
     { 0, NULL }
@@ -92,6 +90,7 @@
 
 static int regParmFlg = 0;      /* determine if we can register a parameter     */
 static int regBitParmFlg = 0;   /* determine if we can register a bit parameter */
+static struct sym_link *regParmFuncType;
 
 static void
 _mcs51_init (void)
@@ -104,11 +103,15 @@
 {
   regParmFlg = 0;
   regBitParmFlg = 0;
+  regParmFuncType = funcType;
 }
 
 static int
 _mcs51_regparm (sym_link * l, bool reentrant)
 {
+  if (IFFUNC_HASVARARGS (regParmFuncType))
+    return 0;
+
   if (IS_SPEC(l) && (SPEC_NOUN(l) == V_BIT))
     {
       /* bit parameters go to b0 thru b7 */
@@ -839,6 +842,8 @@
     NULL,
     NULL,
     NULL,
+    NULL,
+    NULL,
   },
   /* Sizes: char, short, int, long, long long, near ptr, far ptr, gptr, func ptr, banked func ptr, bit, float */
   { 1, 2, 2, 4, 8, 1, 2, 3, 2, 3, 1, 4 },
@@ -872,6 +877,7 @@
     1                           // No fancy alignments supported.
   },
   { _mcs51_genExtraAreas, NULL },
+  0,                            // ABI revision
   {
     +1,         /* direction (+1 = stack grows up) */
     0,          /* bank_overhead (switch between register banks) */
diff -Nru sdcc-4.0.0+dfsg/src/mcs51/peep.c sdcc-4.2.0+dfsg/src/mcs51/peep.c
--- sdcc-4.0.0+dfsg/src/mcs51/peep.c	2019-05-31 07:33:34.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/mcs51/peep.c	2021-06-21 14:47:22.000000000 +0000
@@ -551,13 +551,16 @@
 /* - recursion in case of conditional branches                     */
 /*-----------------------------------------------------------------*/
 static bool
-doPushScan (lineNode **pl, const char *pReg)
+doPushScan (lineNode **pl, const char *pReg, const char *instr)
 {
-  lineNode *plConditional, *pushPl = NULL;
+#if 0
+  lineNode *pushPl = NULL;
+#endif
+  lineNode *plConditional;
 
   for (;; *pl = (*pl)->next)
     {
-      switch (scan4op (pl, pReg, "push", &plConditional))
+      switch (scan4op (pl, pReg, instr, &plConditional))
         {
           case S4O_FOUNDOPCODE:
             /* this is what we're looking for */
@@ -589,7 +592,7 @@
 #else
             /* two possible destinations: give up */
             return FALSE;
-#endif   
+#endif
           default:
             return FALSE;
         }
@@ -653,7 +656,7 @@
       ; There must not be in area 1:
       ;    - read or write access of ar0
       ;    - "acall", "lcall", "pop", "ret", "reti" or "jmp @a+dptr" opcodes
-      ;    - "push" opcode, which doesn't push ar0 
+      ;    - "push" opcode, which doesn't push ar0
       ;    - inline assembly
       ;    - a jump in or out of area 1 (see checkLabelRef())
 
@@ -675,7 +678,7 @@
 
   /* area 1 */
   pushPl = currPl->next;
-  if (!doPushScan (&pushPl, pReg))
+  if (!doPushScan (&pushPl, pReg, "push"))
     return FALSE;
 
   if (!checkLabelRef())
@@ -698,11 +701,11 @@
   else
     {
       /* replace 'push ar0' by comment */
-      #define STR ";\tPeephole\tpush %s removed"
-      int size = sizeof(STR) + 2;
+      #define STR ";\tPeephole\t%s %s removed"
+      int size = sizeof(STR) + 6;
 
       pushPl->line = Safe_alloc (size);
-      SNPRINTF (pushPl->line, size, STR, pReg);
+      SNPRINTF (pushPl->line, size, STR, "push", pReg);
       pushPl->isComment = TRUE;
     }
 
@@ -711,6 +714,63 @@
 }
 
 /*-----------------------------------------------------------------*/
+/* removeDeadPushPop - remove push/pop pair if possible            */
+/*-----------------------------------------------------------------*/
+static bool
+removeDeadPushPop (const char *pReg, lineNode *currPl, lineNode *head)
+{
+  lineNode *popPl;
+
+  /* A push/pop pair can be removed, if these criteria are met
+     (ar0 is just an example here, ar0...ar7 are possible):
+
+     push ar0
+
+      ; There must not be in area 1:
+      ;    - write access of ar0
+      ;    - "acall", "lcall", "pop", "ret", "reti" or "jmp @a+dptr" opcodes
+      ;    - "push" opcode, which doesn't push ar0
+      ;    - inline assembly
+      ;    - a jump in or out of area 1 (see checkLabelRef())
+
+      ; area 1 must be terminated by a:
+     pop ar0
+
+      ; An "acall", "lcall" (not callee save), "ret" (not PCALL with
+      ; callee save), "reti" or write access of r0 terminate
+      ; the search, and the "pop/push ar0" can safely be removed.
+  */
+
+  popPl = currPl->next;
+  if (!doPushScan (&popPl, pReg, "pop"))
+    return FALSE;
+
+  if (!checkLabelRef())
+    return FALSE;
+
+  /* Success! */
+  if (options.noPeepComments)
+    {
+      /* remove popPl from list */
+      popPl->prev->next = popPl->next;
+      popPl->next->prev = popPl->prev;
+    }
+  else
+    {
+      /* replace 'push ar0' by comment */
+      #define STR ";\tPeephole\t%s %s removed"
+      int size = sizeof(STR) + 6;
+
+      popPl->line = Safe_alloc (size);
+      SNPRINTF (popPl->line, size, STR, "pop", pReg);
+      popPl->isComment = TRUE;
+    }
+
+  /* 'push ar0' will be removed by peephole framework after returning TRUE */
+  return TRUE;
+}
+
+/*-----------------------------------------------------------------*/
 /* removeDeadMove - remove superflous 'mov r%1,%2'                 */
 /*-----------------------------------------------------------------*/
 static bool
@@ -759,8 +819,10 @@
 
   if (strncmp (currPl->line, "pop", 3) == 0)
     return removeDeadPopPush (pReg, currPl, head);
-  else if (   strncmp (currPl->line, "mov", 3) == 0
-           && (currPl->line[3] == ' ' || currPl->line[3] == '\t'))
+  else if (strncmp (currPl->line, "push", 4) == 0)
+    return removeDeadPushPop (pReg, currPl, head);
+  else if (strncmp (currPl->line, "mov", 3) == 0 &&
+           (currPl->line[3] == ' ' || currPl->line[3] == '\t'))
     return removeDeadMove (pReg, currPl);
   else
     {
diff -Nru sdcc-4.0.0+dfsg/src/mcs51/peeph.def sdcc-4.2.0+dfsg/src/mcs51/peeph.def
--- sdcc-4.0.0+dfsg/src/mcs51/peeph.def	2018-10-26 19:26:48.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/mcs51/peeph.def	2021-06-21 14:47:22.000000000 +0000
@@ -5028,10 +5028,22 @@
 	;	Peephole 300	pop ar%1 removed
 } if deadMove(%1)
 
+replace restart {
+	push	ar%1
+} by {
+	;	Peephole 301	push ar%1 removed
+} if deadMove(%1)
+
 replace {
 	mov	r%1,%2
 } by {
-	;	Peephole 301	mov r%1,%2 removed
+	;	Peephole 302	mov r%1,%2 removed
+} if notVolatile(%2), deadMove(%1)
+
+replace {
+	mov	ar%1,%2
+} by {
+	;	Peephole 303	mov ar%1,%2 removed
 } if notVolatile(%2), deadMove(%1)
 
 
diff -Nru sdcc-4.0.0+dfsg/src/mcs51/ralloc.c sdcc-4.2.0+dfsg/src/mcs51/ralloc.c
--- sdcc-4.0.0+dfsg/src/mcs51/ralloc.c	2019-06-29 04:30:58.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/mcs51/ralloc.c	2020-05-30 13:56:07.000000000 +0000
@@ -83,7 +83,7 @@
   {REG_GPR, X10_IDX, REG_GPR, "x10", "x10", "xreg", 2, 1},
   {REG_GPR, X11_IDX, REG_GPR, "x11", "x11", "xreg", 3, 1},
   {REG_GPR, X12_IDX, REG_GPR, "x12", "x12", "xreg", 4, 1},
-  {REG_CND, CND_IDX, REG_CND, "C", "psw", "0xd0", 0, 1},
+  {REG_CND, CND_IDX, REG_CND, "C", "not_psw", "0xd0", 0, 1},
   {0, DPL_IDX, 0, "dpl", "dpl", "0x82", 0, 0},
   {0, DPH_IDX, 0, "dph", "dph", "0x83", 0, 0},
   {0, B_IDX, 0, "b", "b", "0xf0", 0, 0},
@@ -870,7 +870,7 @@
 /* getRegBit - will try for Bit if not spill this                  */
 /*-----------------------------------------------------------------*/
 static reg_info *
-getRegBitTry (symbol * sym)
+getRegBit (symbol * sym)
 {
   reg_info *reg;
 
@@ -878,6 +878,7 @@
   if ((reg = allocReg (REG_BIT)))
     return reg;
 
+  spillThis(sym);
   return 0;
 }
 
@@ -931,7 +932,7 @@
 {
   reg_info *reg;
 
-  /* try for a ptr type */
+  /* try for a bit type */
   if ((reg = allocReg (REG_BIT)))
     return reg;
 
@@ -1393,8 +1394,6 @@
                     sym->regs[j] = getRegPtr (ic, ebbs[i], sym);
                   else
                     {
-                      if (sym->regType == REG_BIT) /* Try to allocate to bit register if possible */
-                        sym->regs[j] = getRegBitTry (sym);
                       if (ic->op == CAST && IS_SYMOP (IC_RIGHT (ic)))
                         {
                           symbol *right = OP_SYMBOL (IC_RIGHT (ic));
@@ -1403,7 +1402,12 @@
                             sym->regs[j] = allocThisReg (right->regs[j]);
                         }
                       if (!sym->regs[j])
-                        sym->regs[j] = getRegGpr (ic, ebbs[i], sym);
+                        {
+                          if (sym->regType == REG_BIT) /* Prefer spilling over a GPR */
+                            sym->regs[j] = getRegBit (sym);
+                          else
+                            sym->regs[j] = getRegGpr (ic, ebbs[i], sym);
+                        }
                     }
 
                   /* if the allocation failed which means
@@ -1574,7 +1578,7 @@
                 {
                   symbol *right = OP_SYMBOL (IC_RIGHT (ic));
 
-                  if (right->regs[i])
+                  if (right->regs[i] && right->regs[i]->type != REG_BIT)
                     sym->regs[i] = allocThisReg (right->regs[i]);
                 }
               if (!sym->regs[i])
diff -Nru sdcc-4.0.0+dfsg/src/mos6502/gen.c sdcc-4.2.0+dfsg/src/mos6502/gen.c
--- sdcc-4.0.0+dfsg/src/mos6502/gen.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/mos6502/gen.c	2022-02-14 05:40:11.000000000 +0000
@@ -0,0 +1,10562 @@
+/*-------------------------------------------------------------------------
+  gen.c - source file for code generation for the MOS6502
+
+  Copyright (C) 1998, Sandeep Dutta . sandeep.dutta@usa.net
+  Copyright (C) 1999, Jean-Louis VERN.jlvern@writeme.com
+  Bug Fixes - Wojciech Stryjewski  wstryj1@tiger.lsu.edu (1999 v2.1.9a)
+  Hacked for the HC08:
+  Copyright (C) 2003, Erik Petrich
+  Hacked for the MOS6502:
+  Copyright (C) 2020, Steven Hugg  hugg@fasterlight.com
+  Copyright (C) 2021-2022, Gabriele Gorla
+
+  This program is free software; you can redistribute it and/or modify it
+  under the terms of the GNU General Public License as published by the
+  Free Software Foundation; either version 2, or (at your option) any
+  later version.
+
+  This program is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+  GNU General Public License for more details.
+
+  You should have received a copy of the GNU General Public License
+  along with this program; if not, write to the Free Software
+  Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+-------------------------------------------------------------------------*/
+
+#include "m6502.h"
+#include "ralloc.h"
+#include "gen.h"
+#include "dbuf_string.h"
+
+enum debug_messages {
+  ALWAYS=0x01, 
+  VASM=0x02,
+  TRACEGEN=0x04,
+  DEEPTRACE=0x08,
+  COST=0x10,
+  REGALLOC=0x20,
+  REGOPS=0x40,
+  TRACE_AOP=0x80,
+  TRACE_STACK=0x100,
+  VVDBG=0x80000000,
+  DEBUG_ALL=0x7fffffff
+};
+
+#define DBG_MSG (REGALLOC)
+//#define DBG_MSG (REGALLOC|TRACEGEN|COST)
+//#define DBG_MSG (DEBUG_ALL/*|VVDBG*/)
+//#define DBG_MSG ((DEBUG_ALL|VVDBG)&~COST)
+
+extern int allocInfo;
+unsigned fReturnSizeM6502 = 4;   /* shared with ralloc.c */
+
+static bool regalloc_dry_run;
+static unsigned int regalloc_dry_run_cost_bytes;
+static float regalloc_dry_run_cost_cycles;
+
+struct attr_t {
+  bool isLiteral;
+  unsigned char literalValue;
+};
+
+static struct
+{
+  int stackOfs;
+  int funcHasBasePtr;
+  int stackPushes;
+  int tsxStackPushes;
+//  int baseStackPushes;
+  set *sendSet;
+  int tempOfs;
+  struct attr_t tempAttr[NUM_TEMP_REGS];
+}
+_G;
+
+extern int m6502_ptrRegReq;
+extern int m6502_nRegs;
+extern struct dbuf_s *codeOutBuf;
+
+static void pushReg (reg_info * reg, bool freereg);
+static bool pushRegIfUsed (reg_info *reg);
+static bool pushRegIfSurv (reg_info *reg);
+static void pullReg (reg_info * reg);
+static void pullOrFreeReg (reg_info * reg, bool needpull);
+
+static void storeRegTemp (reg_info * reg, bool freereg);
+static bool storeRegTempIfUsed (reg_info *reg);
+static bool storeRegTempIfSurv (reg_info *reg);
+static void loadRegTemp (reg_info * reg);
+static void loadOrFreeRegTemp (reg_info * reg, bool needload);
+
+
+static void adjustStack (int n);
+static void loadRegFromConst (reg_info * reg, int c);
+
+static void transferAopAop (asmop * srcaop, int srcofs, asmop * dstaop, int dstofs);
+static bool operandsEqu (operand * op1, operand * op2);
+static asmop *newAsmop (short type);
+static void aopAdrPrepare (asmop * aop, int loffset);
+static const char *aopAdrStr (asmop * aop, int loffset, bool bit16);
+static void aopAdrUnprepare (asmop * aop, int loffset);
+static void updateiTempRegisterUse (operand * op);
+static void rmwWithReg (char *rmwop, reg_info * reg);
+
+static asmop *m6502_aop_pass[8];
+static asmop tsxaop;
+
+static char *IMMDFMT = "#0x%02x";
+static char *TEMPFMT = "*(__TEMP+%d)";
+static char *TEMPFMT_IND = "[__TEMP+%d]";
+static char *TEMPFMT_IY = "[__TEMP+%d],y";
+//static char *TEMPFMT_IX = "[(__TEMP+%d),x]";
+
+//static char *BASEPTR = "*(__BASEPTR)";
+
+const int STACK_TOP = 0x100;
+
+
+#define RESULTONSTACK(x) \
+                         (IC_RESULT(x) && IC_RESULT(x)->aop && \
+                         IC_RESULT(x)->aop->type == AOP_STK )
+#define IS_AOP_YX(x) ((x)->regmask == M6502MASK_YX)
+#define IS_AOP_XA(x) ((x)->regmask == M6502MASK_XA)
+#define IS_AOP_AX(x) ((x)->regmask == M6502MASK_AX)
+#define IS_AOP_A(x) ((x)->regmask == M6502MASK_A)
+#define IS_AOP_X(x) ((x)->regmask == M6502MASK_X)
+#define IS_AOP_Y(x) ((x)->regmask == M6502MASK_Y)
+#define IS_AOP_WITH_A(x) (((x)->regmask & M6502MASK_A) != 0)
+#define IS_AOP_WITH_X(x) (((x)->regmask & M6502MASK_X) != 0)
+#define IS_AOP_WITH_Y(x) (((x)->regmask & M6502MASK_Y) != 0)
+
+#define IS_AOPOFS_A(x,o) (((x)->type == AOP_REG) && ((x)->aopu.aop_reg[o]->mask == M6502MASK_A))
+#define IS_AOPOFS_X(x,o) (((x)->type == AOP_REG) && ((x)->aopu.aop_reg[o]->mask == M6502MASK_X))
+#define IS_AOPOFS_Y(x,o) (((x)->type == AOP_REG) && ((x)->aopu.aop_reg[o]->mask == M6502MASK_Y))
+
+#define safeLabelKey2num(a) ((regalloc_dry_run)?0:labelKey2num(a))
+#define safeNewiTempLabel(a) ((regalloc_dry_run)?0:newiTempLabel(a))
+#define safeEmitLabel(a) do { if(!regalloc_dry_run && a) emitLabel(a); } while(0)
+
+
+#define LSB     0
+#define MSB16   1
+#define MSB24   2
+#define MSB32   3
+
+#define AOP(op) op->aop
+#define AOP_TYPE(op) AOP(op)->type
+#define AOP_SIZE(op) AOP(op)->size
+#define AOP_OP(aop) aop->op
+
+/*------------------------------------------------------------------*/
+/* m6502_opcodeCycles - returns the cycle count for the instruction */
+/*------------------------------------------------------------------*/
+int
+m6502_opcodeCycles(const m6502opcodedata *opcode, const char *arg)
+{
+  int lastpos;
+
+  lastpos=(*arg)?strlen(arg)-1:0;
+
+  switch (opcode->type)
+    {
+      case M6502OP_INH: /* Inherent addressing mode */
+      case M6502OP_IDD:
+      case M6502OP_IDI:
+      case M6502OP_BR:  /* Branch (1 byte signed offset) */
+        if(opcode->name[0]=='r'&&opcode->name[1]=='t') // rti and rts
+          return 6;
+        return 2;
+      case M6502OP_SPH:
+        return 3;
+      case M6502OP_SPL:
+        return 4;
+      case M6502OP_BBR:  /* Branch on bit (1 byte signed offset) */
+        return 3;
+      case M6502OP_RMW: /* read/modify/write instructions */
+        if (!strcmp(arg, "a"))  /* accumulator */
+          return 2;
+     	if (arg[0] == '*') /* Zero page */
+    	  return 5;
+        if(lastpos>2 && arg[lastpos-1]!=',' && arg[lastpos]=='x' )
+          return 7;
+        return 6;  /* absolute */
+        
+      case M6502OP_REG: /* standard instruction */
+      case M6502OP_LD:
+        if (arg[0] == '#') /* Immediate addressing mode */
+	      return 2;
+        if (arg[0] == '*') { /* Zero page */
+          if(arg[lastpos]=='x' || arg[lastpos]=='y')
+            return 4;	
+          return 3;
+        }
+        if (arg[0] == '[') { /* indirect */
+          if(arg[lastpos]==']')
+            return 6;
+          return 5;
+        }
+	return 4; /* Otherwise, must be extended addressing mode */
+
+      case M6502OP_ST:
+        if (arg[0] == '*') { /* Zero page */
+          if(arg[lastpos]=='x' || arg[lastpos]=='y')
+            return 4;	
+          return 3;
+        }
+        if (arg[0] == '[')  /* indirect */
+            return 6;
+        if(arg[lastpos]=='x' || arg[lastpos]=='y')
+          return 5;	
+        return 4;
+
+      case M6502OP_JMP:
+        if(opcode->name[1]=='s') return 6;
+        if(arg[0]=='[') return 5;
+        return 3;
+      default:
+         werror (E_INTERNAL_ERROR, __FILE__, __LINE__, "unknown instruction type in m6502_opcodeSize");
+        return 3;
+    }
+}
+
+/*-----------------------------------------------------------------*/
+/* emitComment - emits comments and debug messages                 */
+/*-----------------------------------------------------------------*/
+void
+emitComment (unsigned int level, const char *fmt, ...)
+{
+  bool print=false;
+  va_list ap;
+
+  va_start (ap, fmt);
+
+  if ( level&DBG_MSG ) {
+     if(!(level&VVDBG)) print=true;
+     else if(DBG_MSG&VVDBG) print=true; 
+  }
+  if (level==VASM && options.verboseAsm) print=true;
+  if (level==ALWAYS) print=true;
+
+  if(print) va_emitcode (";", fmt, ap);
+  va_end (ap);
+}
+
+/*-----------------------------------------------------------------*/
+/* regInfoStr - returns register state as a string                 */
+/*-----------------------------------------------------------------*/
+const char *
+regInfoStr()
+{
+  static char outstr[30];
+  char regstring[3][10];
+
+  if(m6502_reg_a->isLitConst) snprintf(regstring[0],10,"A:%c%c:%02x",
+                (m6502_reg_a->isFree)?'-':'U',
+                (m6502_reg_a->isDead)?'-':'L',
+                m6502_reg_a->litConst );
+  else snprintf(regstring[0],10,"A:%c%c:??",
+                (m6502_reg_a->isFree)?'-':'U',
+                (m6502_reg_a->isDead)?'-':'L');
+
+  if(m6502_reg_x->isLitConst) snprintf(regstring[1],10,"X:%c%c:%02x",
+                (m6502_reg_x->isFree)?'-':'U',
+                (m6502_reg_x->isDead)?'-':'L',
+                m6502_reg_x->litConst );
+  else snprintf(regstring[1],10,"X:%c%c:??",
+                (m6502_reg_x->isFree)?'-':'U',
+                (m6502_reg_x->isDead)?'-':'L');
+
+  if(m6502_reg_y->isLitConst) snprintf(regstring[2],10,"Y:%c%c:%02x",
+                (m6502_reg_y->isFree)?'-':'U',
+                (m6502_reg_y->isDead)?'-':'L',
+                m6502_reg_y->litConst );
+  else snprintf(regstring[2],10,"Y:%c%c:??",
+                (m6502_reg_y->isFree)?'-':'U',
+                (m6502_reg_y->isDead)?'-':'L');
+
+  snprintf(outstr, 30, "%s %s %s",
+           regstring[0], regstring[1], regstring[2] );
+
+  return outstr;
+}
+
+/*-----------------------------------------------------------------*/
+/* emit6502op - emits opcopdes, updates cost and register state    */
+/*-----------------------------------------------------------------*/
+void
+emit6502op (const char *inst, const char *fmt, ...)
+{
+  static char verboseFmt[512];
+  va_list ap;
+  int isize = 0;
+  float cycles = 0;
+  float probability=1;
+
+  const m6502opcodedata *opcode = m6502_getOpcodeData(inst);
+
+  if(fmt==0) werror (E_INTERNAL_ERROR, __FILE__, __LINE__, "NULL fmt in emit6502op");
+
+
+  if(opcode)  {
+
+    isize = m6502_opcodeSize(opcode, fmt);
+    cycles = m6502_opcodeCycles(opcode, fmt);
+    reg_info *dst_reg = m6502_regWithIdx(opcode->dest);
+
+    // mark the destination register dirty as necessary
+    // load and transfer are handled in the instruction generator
+    switch (opcode->type) {
+      case M6502OP_REG: // target is accumulator
+#if 1
+        if(dst_reg && dst_reg->isLitConst && fmt[0]=='#' && isdigit(fmt[1]))
+          {
+            unsigned char b=strtol(&fmt[1],NULL,0);
+            if(!strcmp(inst,"and")) {
+              dst_reg->litConst&=b;
+              break;
+            }
+            if(!strcmp(inst,"ora")) {
+              dst_reg->litConst|=b;
+              break;
+            }
+            if(!strcmp(inst,"eor")) {
+              dst_reg->litConst^=b;
+              break;
+            }
+          }
+#endif
+        m6502_dirtyReg (m6502_regWithIdx(opcode->dest));
+        break;
+      case M6502OP_RMW: // target is accumulator
+        if (!strcmp(fmt, "a")) m6502_dirtyReg (m6502_reg_a);
+        break;
+      case M6502OP_SPL: // stack pull
+        _G.stackPushes--;
+        break;
+      case M6502OP_SPH: // stack push
+        _G.stackPushes++;
+        break;
+      case M6502OP_IDD: // index decrement
+        if(dst_reg->isLitConst)
+          dst_reg->litConst--;
+        break;
+      case M6502OP_IDI: // index increment
+        if(dst_reg->isLitConst)
+          dst_reg->litConst++;
+        break;
+      case M6502OP_BR: // add penalty for taken branches
+        // this assumes:
+        // 50% not taken (2 cycles)
+        // 30% taken with target in the same page (3 cycles)
+        // 20% taken with target in a different page (4 cycles)
+        cycles += (0.3 * 1) + (0.2 * 2);
+        break;
+    }
+  } else {
+    emitComment(ALWAYS,"unkwnon opcode %s",inst);
+    isize=10;
+    //werror (E_INTERNAL_ERROR, __FILE__, __LINE__, "NULL opcode in emit6502op");
+  }
+
+  regalloc_dry_run_cost_bytes += isize;
+  regalloc_dry_run_cost_cycles += cycles * probability;
+
+  va_start (ap, fmt);
+  if (options.verboseAsm) {
+    char dstring[3][64];
+    dstring[0][0]=0;
+    dstring[1][0]=0;
+    dstring[2][0]=0;
+    
+  if (DBG_MSG&COST) {
+      snprintf(dstring[0], 64, "sz=%d cl=%f p=%f",
+               isize, cycles, probability);
+   }
+
+  if (DBG_MSG®ALLOC) {
+      snprintf(dstring[1], 64, "%s",
+               regInfoStr() );
+    }
+  if (DBG_MSG&TRACE_STACK) {
+      snprintf(dstring[2], 64, "stkpush=%d",
+               _G.stackPushes );
+    }
+
+    snprintf(verboseFmt, 512, "%s \t; %s %s %s",
+             fmt, dstring[0], dstring[1], dstring[2]);
+    va_emitcode (inst, verboseFmt, ap);
+  } 
+  else
+  {
+    va_emitcode (inst, fmt, ap);
+  }
+  va_end (ap);
+}
+
+static void
+emitSignedBranch (bool gt, bool eq, symbol * tlbl)
+{
+  symbol *tlbl2 = safeNewiTempLabel (NULL);
+  symbol *tlbl3 = safeNewiTempLabel (NULL);
+  if (eq && !gt)
+    emit6502op ("beq", "%05d$", safeLabelKey2num (tlbl->key));
+  if (!eq && gt)
+    emit6502op ("beq", "%05d$", safeLabelKey2num (tlbl2->key));
+  emit6502op (gt ? "bvs" : "bvc", "%05d$", safeLabelKey2num (tlbl2->key));
+  emit6502op ("bpl", "%05d$", safeLabelKey2num (tlbl->key));
+  emit6502op ("bmi", "%05d$", safeLabelKey2num (tlbl3->key));
+  safeEmitLabel (tlbl2);
+  emit6502op ("bmi", "%05d$", safeLabelKey2num (tlbl->key));
+  safeEmitLabel (tlbl3);
+}
+
+static void
+emitUnsignedBranch (bool gt, bool eq, symbol * tlbl)
+{
+  symbol *tlbl2 = safeNewiTempLabel (NULL);
+  if (eq && !gt)
+    emit6502op ("beq", "%05d$", safeLabelKey2num (tlbl->key));
+  if (!eq && gt)
+    emit6502op ("beq", "%05d$", safeLabelKey2num (tlbl2->key));
+  emit6502op (gt ? "bcs" : "bcc", "%05d$", safeLabelKey2num (tlbl->key));
+  safeEmitLabel (tlbl2);
+}
+
+static void
+emitBranch (char *branchop, symbol * tlbl)
+{
+  if (!strcmp("bls", branchop)) {
+    emitUnsignedBranch(0, 1, tlbl);
+  } else if (!strcmp("bhi", branchop)) {
+    emitUnsignedBranch(1, 0, tlbl);
+  } else if (!strcmp("blt", branchop)) {
+    emitSignedBranch(0, 0, tlbl);
+  } else if (!strcmp("bgt", branchop)) {
+    emitSignedBranch(1, 0, tlbl);
+  } else if (!strcmp("ble", branchop)) {
+    emitSignedBranch(0, 1, tlbl);
+  } else if (!strcmp("bge", branchop)) {
+    emitSignedBranch(1, 1, tlbl);
+  } else {
+    if (!IS_MOS65C02 && !strcmp(branchop, "bra"))
+      branchop = "jmp";
+    emit6502op (branchop, "%05d$", safeLabelKey2num (tlbl->key));
+  }  
+}
+
+/*--------------------------------------------------------------------------*/
+/* smallAdjustReg - Adjust register by n bytes if possible.                              */
+/*--------------------------------------------------------------------------*/
+static int
+smallAdjustReg (reg_info *reg, int n)
+{
+  int regidx = reg->rIdx;
+
+  emitComment (REGOPS, __func__ );
+
+  if( (regidx!=X_IDX) && (regidx!=Y_IDX) )
+    return n;  
+  
+  if (n <= -4 || n >= 4) {
+    return n;
+  }
+
+  while (n < 0) {
+    rmwWithReg ("dec", reg); /* 1 byte,  2 cycles */
+    n++;
+  }
+  while (n > 0) {
+    rmwWithReg ("inc", reg); /* 1 byte,  2 cycles */
+    n--;
+  }
+  return 0;
+}
+
+/*-----------------------------------------------------------------*/
+/* m6502_emitDebuggerSymbol - associate the current code location   */
+/*   with a debugger symbol                                        */
+/*-----------------------------------------------------------------*/
+void
+m6502_emitDebuggerSymbol (const char *debugSym)
+{
+  genLine.lineElement.isDebug = 1;
+  emitcode ("", "%s ==.", debugSym);
+  genLine.lineElement.isDebug = 0;
+}
+
+/*--------------------------------------------------------------------------*/
+/* transferRegReg - Transfer from register(s) sreg to register(s) dreg. If  */
+/*                  freesrc is true, sreg is marked free and available for  */
+/*                  reuse. sreg and dreg must be of equal size              */
+/*--------------------------------------------------------------------------*/
+static void
+transferRegReg (reg_info *sreg, reg_info *dreg, bool freesrc)
+{
+  int srcidx;
+  int dstidx;
+  char error = 0;
+
+  /* Nothing to do if no destination. */
+  if (!dreg)
+    return;
+
+  /* But it's definitely an error if there's no source. */
+  if (!sreg)
+    {
+      werror (E_INTERNAL_ERROR, __FILE__, __LINE__, "NULL sreg in transferRegReg");
+      return;
+    }
+
+  emitComment (REGOPS, "  transferRegReg(%s,%s)", sreg->name, dreg->name);
+  emitComment (REGOPS, "  %s %s", __func__, regInfoStr() );
+
+  srcidx = sreg->rIdx;
+  dstidx = dreg->rIdx;
+
+  if (srcidx == dstidx)
+    {
+      m6502_useReg (dreg);
+      return;
+    }
+
+// TODO: make sure regs are killed if clobbered
+  switch (dstidx)
+    {
+    case A_IDX:
+      switch (srcidx)
+        {
+        case Y_IDX:            /* Y to A */
+          emit6502op ("tya", "");
+          break;
+        case X_IDX:            /* X to A */
+          emit6502op ("txa", "");
+          break;
+        default:
+          error = 1;
+        }
+      break;
+    case Y_IDX:
+      switch (srcidx)
+        {
+        case A_IDX:            /* A to Y */
+          emit6502op ("tay", "");
+          break;
+        case X_IDX:            /* X to Y */
+          if(m6502_reg_x->isLitConst) {
+            emit6502op ("ldy", IMMDFMT, m6502_reg_x->litConst);
+          } else if(m6502_reg_a->isFree) {
+          emit6502op ("txa", "");
+          emit6502op ("tay", "");
+          } else {
+            storeRegTemp (m6502_reg_x, false);
+            loadRegTemp (m6502_reg_y);
+          }
+          break;
+        default:
+          error = 1;
+        }
+      break;
+    case X_IDX:
+      switch (srcidx)
+        {
+        case A_IDX:            /* A to X */
+          emit6502op ("tax", "");
+          break;
+        case Y_IDX:            /* Y to X */
+          if(m6502_reg_y->isLitConst) {
+            emit6502op ("ldx", IMMDFMT, m6502_reg_y->litConst);
+          } else if(m6502_reg_a->isFree) {
+          emit6502op ("tya", "");
+          emit6502op ("tax", "");
+          } else {
+            storeRegTemp (m6502_reg_y, false);
+            loadRegTemp (m6502_reg_x);
+          }
+          break;
+        default:
+          error = 1;
+        }
+      break;
+    case YX_IDX:
+      switch (srcidx)
+        {
+        case XA_IDX:           /* XA to YX */
+          storeRegTemp (m6502_reg_x, false);
+          transferRegReg(m6502_reg_a, m6502_reg_x, true);
+          loadRegTemp (m6502_reg_y);
+          break;
+        default:
+          error = 1;
+        }
+      break;
+    case XA_IDX:
+      switch (srcidx)
+        {
+        case YX_IDX:           /* YX to XA */
+          transferRegReg(m6502_reg_x, m6502_reg_a, true);
+          storeRegTemp (m6502_reg_y, true);
+          loadRegTemp (m6502_reg_x);
+          break;
+        default:
+          error = 1;
+        }
+      break;
+    default:
+      error = 1;
+    }
+
+  wassertl (!error, "bad combo in transferRegReg");
+
+  m6502_useReg (dreg);
+
+  if(sreg->isLitConst) {
+    dreg->isLitConst = sreg->isLitConst;
+    dreg->litConst = sreg->litConst;
+  } else {
+    m6502_dirtyReg (dreg);
+  }
+//  dreg->aop = sreg->aop;
+//  dreg->aopofs = sreg->aopofs;
+
+  if (freesrc)
+    m6502_freeReg (sreg);
+}
+
+/*--------------------------------------------------------------------------*/
+/* updateCFA - update the debugger information to reflect the current       */
+/*             connonical frame address relative to the stack pointer       */
+/*--------------------------------------------------------------------------*/
+static void
+updateCFA (void)
+{
+  /* there is no frame unless there is a function */
+  if (!currFunc)
+    return;
+
+  if (options.debug && !regalloc_dry_run)
+    debugFile->writeFrameAddress (NULL, m6502_reg_sp, 1 + _G.stackOfs + _G.stackPushes);
+}
+
+/*--------------------------------------------------------------------------*/
+/* storeRegTemp - Store register onto the __TEMP stack. If freereg is true, */
+/*                reg is marked free and available for reuse.               */
+/*--------------------------------------------------------------------------*/
+static void
+storeRegTemp (reg_info * reg, bool freereg)
+{
+  emitComment (REGOPS, "  storeRegTemp(%s) %s", reg ? reg->name : "-", freereg?"free":"");
+
+  int regidx = reg->rIdx;
+
+  if(regidx<=Y_IDX) {
+    _G.tempAttr[_G.tempOfs].isLiteral=reg->isLitConst;
+    _G.tempAttr[_G.tempOfs].literalValue=reg->litConst;
+  }
+
+  switch (regidx) {
+    case A_IDX:
+      emit6502op ("sta", TEMPFMT, _G.tempOfs++);
+      break;
+    case X_IDX:
+      emit6502op ("stx", TEMPFMT, _G.tempOfs++);
+      break;
+    case Y_IDX:
+      emit6502op ("sty", TEMPFMT, _G.tempOfs++);
+      break;
+    case YX_IDX:
+      storeRegTemp (m6502_reg_x, freereg);
+      storeRegTemp (m6502_reg_y, freereg);
+      break;
+    case XA_IDX:
+      storeRegTemp (m6502_reg_a, freereg);
+      storeRegTemp (m6502_reg_x, freereg);
+      break;
+    default:
+      wassertl (0, "storeRegTemp()");
+      break;
+  }
+
+  if (freereg)
+    m6502_freeReg (reg);
+
+  //emitcode("", "storeRegTemp overflow");
+  wassertl (_G.tempOfs <= NUM_TEMP_REGS, "storeRegTemp(): overflow");
+}
+
+/*--------------------------------------------------------------------------*/
+/* loadRegTemp - Pull register reg off the stack.                               */
+/*--------------------------------------------------------------------------*/
+static void
+loadRegTemp (reg_info * reg)
+{
+  // pop off stack, unused
+  if (reg == NULL) {
+    _G.tempOfs--;
+    return;
+  }
+    
+  int regidx = reg->rIdx;
+  if(regidx<=Y_IDX) {
+    _G.tempOfs--;
+    if(_G.tempAttr[_G.tempOfs].isLiteral) {
+      loadRegFromConst(reg, _G.tempAttr[_G.tempOfs].literalValue);
+      return;
+    }
+  }
+   
+  switch (regidx) {
+    case A_IDX:
+      emit6502op ("lda", TEMPFMT, _G.tempOfs);
+      break;
+    case X_IDX:
+      emit6502op ("ldx", TEMPFMT, _G.tempOfs);
+      break;
+    case Y_IDX:
+      emit6502op ("ldy", TEMPFMT, _G.tempOfs);
+      break;
+    case YX_IDX:
+      loadRegTemp(m6502_reg_y);
+      loadRegTemp(m6502_reg_x);
+      break;
+    case XA_IDX:
+      loadRegTemp(m6502_reg_x);
+      loadRegTemp(m6502_reg_a);
+      break;
+    default:
+      wassertl (0, "loadRegTemp()");
+      break;
+  }
+
+// FIXME: figure out if register pairs are literals
+
+  m6502_useReg (reg);
+  m6502_dirtyReg (reg);
+}
+
+// TODO: note that needpull has diff. semantics than loadRegTemp()
+static void
+loadRegTempNoFlags (reg_info * reg, bool needpull)
+{
+  if (needpull) {
+    emit6502op("php", "");
+    loadRegTemp (reg);
+    emit6502op("plp", "");
+  } else {
+    m6502_freeReg (reg);
+  }
+}
+
+static bool
+storeRegTempIfSurv (reg_info *reg)
+{
+  if (!reg->isDead) {
+    storeRegTemp (reg, true);
+    return true;
+  }
+  return false;
+}
+
+static bool
+storeRegTempIfUsed (reg_info *reg)
+{
+  if (!reg->isFree)
+    {
+      storeRegTemp (reg, true);
+      return true;
+    }
+  return false;
+}
+
+static void
+loadOrFreeRegTemp (reg_info * reg, bool needpull)
+{
+  if (needpull)
+    loadRegTemp (reg);
+  else
+    m6502_freeReg (reg);
+}
+
+static void
+dirtyRegTemp (int temp_reg_idx)
+{
+  _G.tempAttr[temp_reg_idx].isLiteral=false;
+}
+
+/*--------------------------------------------------------------------------*/
+/* pushReg - Push register reg onto the stack. If freereg is true, reg is   */
+/*           marked free and available for reuse.                           */
+/*--------------------------------------------------------------------------*/
+static void
+pushReg (reg_info * reg, bool freereg)
+{
+  int regidx = reg->rIdx;
+
+  emitComment (REGOPS, "; pushReg(%s) %s %s", reg->name, reg->isFree?"free":"", reg->isDead?"dead":"");
+
+  switch (regidx)
+    {
+    case A_IDX:
+      emit6502op ("pha", "");
+      updateCFA ();
+      break;
+    case X_IDX:
+      if (IS_MOS65C02) {
+        emit6502op ("phx", "");
+      } else {
+        bool needloada = storeRegTempIfUsed (m6502_reg_a);
+        transferRegReg (m6502_reg_x, m6502_reg_a, false);
+        pushReg (m6502_reg_a, true);
+        loadOrFreeRegTemp (m6502_reg_a, needloada);
+      }
+      updateCFA ();
+      break;
+    case Y_IDX:
+      if (IS_MOS65C02) {
+        emit6502op ("phy", "");
+      } else {
+        bool needloada = storeRegTempIfUsed (m6502_reg_a);
+        transferRegReg (m6502_reg_y, m6502_reg_a, true);
+        pushReg (m6502_reg_a, true);
+        loadOrFreeRegTemp (m6502_reg_a, needloada);
+      }
+      updateCFA ();
+      break;
+    // little-endian order
+    case YX_IDX:
+      pushReg(m6502_reg_y, freereg);
+      pushReg(m6502_reg_x, freereg);
+      break;
+    case XA_IDX:
+      pushReg(m6502_reg_x, freereg);
+      pushReg(m6502_reg_a, freereg);
+      break;
+    default:
+      wassertl(0, "pushReg() error");
+      break;
+    }
+  if (freereg)
+    m6502_freeReg (reg);
+}
+
+/*--------------------------------------------------------------------------*/
+/* pullReg - Pull register reg off the stack.                               */
+/*--------------------------------------------------------------------------*/
+static void
+pullReg (reg_info * reg)
+{
+  int regidx = reg->rIdx;
+
+  emitComment (REGOPS, __func__ );
+
+  switch (regidx)
+    {
+    case A_IDX:
+      emit6502op ("pla", "");
+      updateCFA ();
+      break;
+    case X_IDX:
+      if (IS_MOS65C02) {
+        emit6502op ("plx", "");
+      } else {
+        // FIXME: saving A makes regression fail
+//	bool needloada = storeRegTempIfUsed (m6502_reg_a);
+        pullReg (m6502_reg_a);
+        transferRegReg (m6502_reg_a, m6502_reg_x, true);
+//	loadOrFreeRegTemp (m6502_reg_a, needloada);
+      }
+      updateCFA ();
+      break;
+    case Y_IDX:
+      if (IS_MOS65C02) {
+        emit6502op ("ply", "");
+      } else {
+        // FIXME: saving A makes regression fail
+//	bool needloada = storeRegTempIfUsed (m6502_reg_a);
+        pullReg (m6502_reg_a);
+        transferRegReg (m6502_reg_a, m6502_reg_y, true);
+//	loadOrFreeRegTemp (m6502_reg_a, needloada);
+      }
+      updateCFA ();
+      break;
+    // little-endian order
+    case YX_IDX:
+      pullReg(m6502_reg_x);
+      pullReg(m6502_reg_y);
+      break;
+    case XA_IDX:
+      pullReg(m6502_reg_a);
+      pullReg(m6502_reg_x);
+      break;
+    default:
+      break;
+    }
+  m6502_useReg (reg);
+  m6502_dirtyReg (reg);
+}
+
+/*--------------------------------------------------------------------------*/
+/* pullNull - Discard n bytes off the top of the stack                      */
+/*--------------------------------------------------------------------------*/
+static void
+pullNull (int n)
+{
+  emitComment (REGOPS, __func__ );
+  wassert (n >= 0);
+  adjustStack (n);
+}
+
+/*--------------------------------------------------------------------------*/
+/* pushRegIfUsed - Push register reg if marked in use. Returns true if the  */
+/*                 push was performed, false otherwise.                     */
+/*--------------------------------------------------------------------------*/
+static bool
+pushRegIfUsed (reg_info *reg)
+{
+  if (!reg->isFree)
+    {
+      pushReg (reg, true);
+      return true;
+    }
+  else
+    return false;
+}
+
+/*--------------------------------------------------------------------------*/
+/* pushRegIfSurv - Push register reg if marked surviving. Returns true if   */
+/*                 the push was performed, false otherwise.                 */
+/*--------------------------------------------------------------------------*/
+static bool
+pushRegIfSurv (reg_info *reg)
+{
+  if (!reg->isDead)
+    {
+      pushReg (reg, true);
+      return true;
+    }
+  else
+    return false;
+}
+
+/*--------------------------------------------------------------------------*/
+/* pullOrFreeReg - If needpull is true, register reg is pulled from the     */
+/*                 stack. Otherwise register reg is marked as free.         */
+/*--------------------------------------------------------------------------*/
+static void
+pullOrFreeReg (reg_info * reg, bool needpull)
+{
+  if (needpull)
+    pullReg (reg);
+  else
+    m6502_freeReg (reg);
+}
+
+/*--------------------------------------------------------------------------*/
+/* adjustStack - Adjust the stack pointer by n bytes.                       */
+/*--------------------------------------------------------------------------*/
+// TODO: optimize for 65C02
+static void
+adjustStack (int n)
+{
+  emitComment (REGOPS, __func__ );
+  emitComment (REGOPS, "  %s reg:  %s", __func__, regInfoStr());
+
+  if (n <= -8 || n >= 8) {
+    // TODO: too big, consider subroutine
+    storeRegTemp(m6502_reg_xa, true);
+    emit6502op ("tsx", "");
+    transferRegReg (m6502_reg_x, m6502_reg_a, true);
+    emit6502op ("clc", "");
+    emit6502op ("adc", IMMDFMT, n&0xff);
+    transferRegReg (m6502_reg_a, m6502_reg_x, true);
+    emit6502op ("txs", "");
+    _G.stackPushes -= n;
+    n = 0;
+    loadRegTemp(m6502_reg_xa);
+  }
+  while (n < 0) {
+    emit6502op ("pha", "");      /* 1 byte,  3 cycles */
+    n++;
+  }
+
+  if (n > 0) {
+    // FIXME: A is incorrectly marked free and makes many regression fail
+    //    bool needloada=storeRegTempIfUsed (m6502_reg_a);
+    bool needloada = true;
+    storeRegTemp(m6502_reg_a, true);
+    
+    while (n > 0) {
+      emit6502op ("pla", "");      /* 1 byte,  4 cycles */
+      n--;
+    }
+    loadOrFreeRegTemp(m6502_reg_a, needloada);
+  }
+  updateCFA ();
+}
+
+/*------------------------------------------------------------------*/
+/* swapXA - swap hi and low bytes ox XA                             */
+/*------------------------------------------------------------------*/
+static void
+swapXA ()
+{
+  emitComment (REGOPS, __func__ );
+
+  if(m6502_reg_a->isLitConst) {
+    unsigned char t=m6502_reg_a->litConst;
+    transferRegReg(m6502_reg_x, m6502_reg_a, true);
+    loadRegFromConst(m6502_reg_a,t);
+  } else if(m6502_reg_x->isLitConst) {
+    unsigned char t=m6502_reg_x->litConst;
+    transferRegReg(m6502_reg_a, m6502_reg_x, true);
+    loadRegFromConst(m6502_reg_a,t);
+  } else {
+    storeRegTemp (m6502_reg_a, false);
+    transferRegReg (m6502_reg_x, m6502_reg_a, false);
+    loadRegTemp (m6502_reg_x);
+  }
+
+  if(m6502_reg_a->isLitConst && m6502_reg_x->isLitConst) {
+     m6502_reg_xa->isLitConst=true;
+     m6502_reg_xa->litConst=(m6502_reg_x->litConst<<8)|m6502_reg_a->litConst;
+    }
+}
+
+/*--------------------------------------------------------------------------*/
+/* aopName - Return a string with debugging information about an asmop.     */
+/*--------------------------------------------------------------------------*/
+static char *
+aopName (asmop * aop)
+{
+  static char buffer[262];
+  char *buf = buffer;
+
+  if (!aop)
+    return "(asmop*)NULL";
+
+  switch (aop->type)
+    {
+    case AOP_IMMD:
+      sprintf (buf, "IMMD(%s)", aop->aopu.aop_immd.aop_immd1);
+      return buf;
+    case AOP_LIT:
+      sprintf (buf, "LIT(%s)", aopLiteral (aop->aopu.aop_lit, 0));
+      return buf;
+    case AOP_DIR:
+      sprintf (buf, "DIR(%s)", aop->aopu.aop_dir);
+      return buf;
+    case AOP_EXT:
+      sprintf (buf, "EXT(%s)", aop->aopu.aop_dir);
+      return buf;
+    case AOP_SOF:
+      sprintf (buf, "SOF(%s)", OP_SYMBOL (aop->op)->name);
+      return buf;
+    case AOP_REG:
+      sprintf (buf, "REG(%s,%s,%s,%s)",
+               aop->aopu.aop_reg[3] ? aop->aopu.aop_reg[3]->name : "-",
+               aop->aopu.aop_reg[2] ? aop->aopu.aop_reg[2]->name : "-",
+               aop->aopu.aop_reg[1] ? aop->aopu.aop_reg[1]->name : "-",
+               aop->aopu.aop_reg[0] ? aop->aopu.aop_reg[0]->name : "-");
+      return buf;
+    case AOP_STK:
+      return "STK";
+    default:
+      sprintf (buf, "?%d", aop->type);
+      return buf;
+    }
+
+  return "?";
+}
+
+// can we BIT aop ?
+static bool 
+canBitOp (const operand* aop)
+{
+  switch (AOP_TYPE(aop)) {
+    // bit aa, bit aaaa
+    case AOP_DIR:
+    case AOP_EXT:
+      return true;
+    // bit #aa
+    case AOP_LIT:
+      return IS_MOS65C02;
+    // TODO: ind,x for 65c02?
+  }
+  return false;
+}
+
+/*--------------------------------------------------------------------------*/
+/* loadRegFromAop - Load register reg from logical offset loffset of aop.   */
+/*                  For multi-byte registers, loffset is of the lsb reg.    */
+/*--------------------------------------------------------------------------*/
+static void
+loadRegFromAop (reg_info * reg, asmop * aop, int loffset)
+{
+  int regidx = reg->rIdx;
+
+  if (aop->stacked && aop->stk_aop[loffset])
+    {
+      loadRegFromAop (reg, aop->stk_aop[loffset], 0);
+      return;
+    }
+
+  emitComment (REGOPS, "      loadRegFromAop (%s, %s, %d)", reg->name, aopName (aop), loffset);
+
+#if 0
+  /* If operand is volatile, we cannot optimize. */
+  if (!aop->op || isOperandVolatile (aop->op, false))
+    goto forceload;
+
+
+  /* If this register already has this offset of the operand
+     then we need only mark it as in use. */
+  if (reg->aop && reg->aop->op && aop->op && operandsEqu (reg->aop->op, aop->op) && (reg->aopofs == loffset))
+    {
+      m6502_useReg (reg);
+      emitComment (REGOPS, "  already had correct value for %s", reg->name);
+      return;
+    }
+
+  /* TODO: check to see if we can transfer from another register */
+
+  if (m6502_reg_hy>aop && m6502_reg_y->aop->op && aop->op
+      && operandsEqu (m6502_reg_y->aop->op, aop->op) && (m6502_reg_y->aopofs == loffset))
+    {
+      emitComment (REGOPS, "  found correct value for %s in h", reg->name);
+      transferRegReg (m6502_reg_y, reg, false);
+      m6502_useReg (reg);
+      return;
+    }
+
+
+  if (m6502_reg_x->aop && m6502_reg_x->aop->op && aop->op
+      && operandsEqu (m6502_reg_x->aop->op, aop->op) && (m6502_reg_x->aopofs == loffset))
+    {
+      emitComment (REGOPS, "  found correct value for %s in x", reg->name);
+      transferRegReg (m6502_reg_x, reg, false);
+      m6502_useReg (reg);
+      return;
+    }
+
+  if (m6502_reg_a->aop && m6502_reg_a->aop->op && aop->op
+      && operandsEqu (m6502_reg_a->aop->op, aop->op) && (m6502_reg_a->aopofs == loffset))
+    {
+      emitComment (REGOPS, "  found correct value for %s in a", reg->name);
+      transferRegReg (m6502_reg_a, reg, false);
+      m6502_useReg (reg);
+      return;
+    }
+
+forceload:
+#endif
+
+  switch (regidx)
+    {
+    case X_IDX:
+    case A_IDX:
+    case Y_IDX:
+      if (aop->type == AOP_REG)
+        {
+          if (loffset < aop->size)
+            transferRegReg (aop->aopu.aop_reg[loffset], reg, false);
+          else
+            loadRegFromConst (reg, 0); /* TODO: handle sign extension */
+        }
+      else if (aop->type == AOP_LIT)
+        {
+          loadRegFromConst (reg, byteOfVal (aop->aopu.aop_lit, loffset));
+        }
+      // no such thing as stx aa,x
+      else if (aop->type == AOP_SOF && regidx != A_IDX)
+        {
+          bool needloada = storeRegTempIfUsed(m6502_reg_a);
+          loadRegFromAop(m6502_reg_a, aop, loffset);
+          transferRegReg(m6502_reg_a, reg, false);
+          loadOrFreeRegTemp(m6502_reg_a,needloada);
+          break;
+        }
+      else
+        {
+          aopAdrPrepare(aop, loffset);
+          const char *l = aopAdrStr (aop, loffset, false);
+          emit6502op (regidx == A_IDX ? "lda" : regidx == X_IDX ? "ldx" : "ldy", l);
+          aopAdrUnprepare(aop, loffset);
+          m6502_dirtyReg (reg);
+        }
+      break;
+
+    case YX_IDX:
+      if (IS_AOP_YX (aop))
+        break;
+      else if (IS_AOP_XA (aop))
+        transferRegReg (m6502_reg_xa, m6502_reg_yx, false);
+      else if (IS_AOP_AX (aop))
+        transferRegReg (m6502_reg_a, m6502_reg_y, false);
+      else
+        {
+          loadRegFromAop (m6502_reg_x, aop, loffset);
+          loadRegFromAop (m6502_reg_y, aop, loffset + 1);
+        }
+      break;
+
+    case XA_IDX:
+      if (IS_AOP_XA (aop))
+        break;
+      else if (IS_AOP_YX (aop))
+        transferRegReg (m6502_reg_yx, m6502_reg_xa, false);
+      else if (IS_AOP_AX (aop))
+        {
+          emitComment(REGOPS, "   * AX->XA");
+          swapXA();
+        }
+      else
+        {
+          emitComment (REGOPS, "XA");
+          loadRegFromAop (m6502_reg_a, aop, loffset);
+          loadRegFromAop (m6502_reg_x, aop, loffset + 1);
+        }
+      break;
+    }
+
+  m6502_useReg (reg);
+}
+
+// get any free 8-bit register
+static reg_info*
+getFreeByteReg()
+{
+  if (m6502_reg_a->isFree)
+    return m6502_reg_a;
+  else if (m6502_reg_x->isFree)
+    return m6502_reg_x;
+  else if (m6502_reg_y->isFree)
+    return m6502_reg_y;
+  else
+    return NULL;
+}
+
+// TODO: move more to this one?
+static reg_info*
+getDeadByteReg()
+{
+  if (m6502_reg_a->isDead)
+    return m6502_reg_a;
+  else if (m6502_reg_x->isDead)
+    return m6502_reg_x;
+  else if (m6502_reg_y->isDead)
+    return m6502_reg_y;
+  else
+    return NULL;
+}
+
+/*--------------------------------------------------------------------------*/
+/* storeRegToAop - Store register reg to logical offset loffset of aop.     */
+/*                 For multi-byte registers, loffset is of the lsb reg.     */
+/*--------------------------------------------------------------------------*/
+static void
+storeRegToAop (reg_info *reg, asmop * aop, int loffset)
+{
+  int regidx = reg->rIdx;
+
+  emitComment (TRACE_AOP, "      storeRegToAop (%s, %s, %d), stacked=%d",
+                reg->name, aopName (aop), loffset, aop->stacked);
+
+  if ((regidx == YX_IDX) && aop->stacked && (aop->stk_aop[loffset] || aop->stk_aop[loffset + 1]))
+    {
+      storeRegToAop (m6502_reg_y, aop, loffset + 1);
+      storeRegToAop (m6502_reg_x, aop, loffset);
+      return;
+    }
+
+  if ((regidx == XA_IDX) && aop->stacked && (aop->stk_aop[loffset] || aop->stk_aop[loffset + 1]))
+    {
+      storeRegToAop (m6502_reg_x, aop, loffset + 1);
+      storeRegToAop (m6502_reg_a, aop, loffset);
+      return;
+    }
+
+  if (aop->stacked && aop->stk_aop[loffset])
+    {
+      storeRegToAop (reg, aop->stk_aop[loffset], 0);
+      return;
+    }
+
+  if (aop->type == AOP_DUMMY)
+    return;
+
+  if (aop->type == AOP_CRY)     /* This can only happen if IFX was optimized */
+    return;                     /* away, so just toss the result */
+
+  switch (regidx)
+    {
+    case A_IDX:
+      if ((aop->type == AOP_REG) && (loffset < aop->size))
+        transferRegReg (reg, aop->aopu.aop_reg[loffset], false);
+      else
+        {
+          emitComment (TRACE_AOP|VVDBG, "      storeRegToAop: A");
+
+          // TODO: i think this does not assemble?
+          aopAdrPrepare(aop, loffset);
+          emit6502op ("sta", aopAdrStr (aop, loffset, false));
+          aopAdrUnprepare(aop, loffset);
+        }
+      break;
+    case X_IDX:
+    case Y_IDX:
+      if ((aop->type == AOP_REG) && (loffset < aop->size))
+        transferRegReg (reg, aop->aopu.aop_reg[loffset], false);
+      else if (aop->type == AOP_SOF)
+        {
+          // TODO: push if live
+          bool needpulla = pushRegIfUsed (m6502_reg_a);
+          transferRegReg (reg, m6502_reg_a, false);
+          storeRegToAop (m6502_reg_a, aop, loffset);
+          pullOrFreeReg (m6502_reg_a, needpulla);
+        }
+      else
+        {
+          aopAdrPrepare(aop, loffset);
+          emit6502op (regidx==X_IDX?"stx":"sty", aopAdrStr (aop, loffset, false));
+          aopAdrUnprepare(aop, loffset);
+        }
+      break;
+    case YX_IDX:
+      if (aop->type == AOP_SOF) // TODO: will fail assemble
+        {
+          //     werror (E_INTERNAL_ERROR, __FILE__, __LINE__, "storeRegToAop: aop->type == AOP_SOF");
+	  //     int offset = (_G.stackOfs + _G.stackPushes + aop->aopu.aop_stk + aop->size - loffset - 1);
+        }
+      if (aop->type == AOP_DIR || aop->type == AOP_EXT)
+        {
+          aopAdrPrepare(aop, loffset);
+          emit6502op ("stx", aopAdrStr (aop, loffset, true));
+          emit6502op ("sty", aopAdrStr (aop, loffset+1, true));
+          aopAdrUnprepare(aop, loffset);
+        }
+      else if (IS_AOP_XA (aop))
+        transferRegReg (reg, m6502_reg_xa, false);
+      else if (IS_AOP_YX (aop))
+        break;
+      else if (m6502_reg_a->isFree)
+        {
+          bool needpula;
+          needpula = pushRegIfUsed (m6502_reg_a);
+          transferRegReg (m6502_reg_y, m6502_reg_a, false);
+          storeRegToAop (m6502_reg_a, aop, loffset + 1);
+          storeRegToAop (m6502_reg_x, aop, loffset);
+          pullOrFreeReg (m6502_reg_a, needpula);
+        }
+      else
+        {
+          bool needloadx;
+          storeRegToAop (m6502_reg_x, aop, loffset);
+          needloadx = storeRegTempIfUsed (m6502_reg_x);
+          transferRegReg (m6502_reg_y, m6502_reg_x, false);
+          storeRegToAop (m6502_reg_x, aop, loffset + 1);
+          loadOrFreeRegTemp (m6502_reg_x, needloadx);
+        }
+      break;
+    case XA_IDX:
+      if (IS_AOP_YX (aop))
+        transferRegReg (reg, m6502_reg_yx, false);
+      else if (IS_AOP_XA (aop))
+        break;
+      else if (IS_AOP_AX (aop))
+        {
+          swapXA();
+        }
+      else
+        {
+          storeRegToAop (m6502_reg_a, aop, loffset);
+          storeRegToAop (m6502_reg_x, aop, loffset + 1);
+        }
+      break;
+    default:
+      wassert (0);
+    }
+
+  /* Disable the register tracking for now */
+#if 0
+  //if (!reg->aop || (reg->aop && (reg->aop != aop)))
+  {
+    //if (reg->aop!=aop)
+    for (otheridx = 0; otheridx < m6502_nRegs; otheridx++)
+      {
+        otherreg = m6502_regWithIdx (otheridx);
+        if (otherreg && otherreg->aop
+            && otherreg->aop->op && aop->op && operandsEqu (otherreg->aop->op, aop->op) && (otherreg->aopofs == loffset))
+          {
+            emitComment (TRACE_AOP|VVDBG, "  marking %s stale", otherreg->name);
+            otherreg->aop = NULL;
+          }
+      }
+    if ((!m6502_reg_x->aop || !m6502_reg_y->aop) && m6502_reg_yx->aop)
+      {
+        m6502_reg_yx->aop = NULL;
+        emitComment (TRACE_AOP|VVDBG, "  marking yx stale");
+      }
+    if ((!m6502_reg_x->aop || !m6502_reg_a->aop) && m6502_reg_xa->aop)
+      {
+        m6502_reg_xa->aop = NULL;
+        emitComment (TRACE_AOP|VVDBG, "  marking xa stale");
+      }
+
+    reg->aop = aop;
+    reg->aopofs = loffset;
+  }
+#endif
+}
+
+/*--------------------------------------------------------------------------*/
+/* loadRegFromConst - Load register reg from constant c.                    */
+/*--------------------------------------------------------------------------*/
+static void
+loadRegFromConst (reg_info * reg, int c)
+{
+  emitComment (REGOPS, __func__ );
+
+  switch (reg->rIdx)
+    {
+    case A_IDX:
+      c &= 0xff;
+      if (reg->isLitConst && reg->litConst == c)
+            break;
+
+      if (m6502_reg_y->isLitConst && m6502_reg_y->litConst == c)
+        transferRegReg (m6502_reg_y, reg, false);
+      else if (m6502_reg_x->isLitConst && m6502_reg_x->litConst == c)
+        transferRegReg (m6502_reg_x, reg, false);
+      else
+        {
+          emit6502op ("lda", IMMDFMT, c);
+        }
+      break;
+    case X_IDX:
+      c &= 0xff;
+      if (reg->isLitConst)
+        {
+          if (reg->litConst == c)
+            break;
+          if (((reg->litConst + 1) & 0xff) == c)
+            {
+              emit6502op ("inx", "");
+              break;
+            }
+          if (((reg->litConst - 1) & 0xff) == c)
+            {
+              emit6502op ("dex", "");
+              break;
+            }
+        }
+
+      if (m6502_reg_a->isLitConst && m6502_reg_a->litConst == c)
+        transferRegReg (m6502_reg_a, reg, false);
+        /*
+        TODO does not work for X<->Y
+      else if (m6502_reg_y->isLitConst && m6502_reg_y->litConst == c)
+        transferRegReg (m6502_reg_y, reg, false);
+        */
+      else
+        {
+          emit6502op ("ldx", IMMDFMT, c);
+        }
+      break;
+    case Y_IDX:
+      c &= 0xff;
+      if (reg->isLitConst)
+        {
+          if (reg->litConst == c)
+            break;
+          if (((reg->litConst + 1) & 0xff) == c)
+            {
+              emit6502op ("iny", "");
+              break;
+            }
+          if (((reg->litConst - 1) & 0xff) == c)
+            {
+              emit6502op ("dey", "");
+              break;
+            }
+        }
+
+      if (m6502_reg_a->isLitConst && m6502_reg_a->litConst == c)
+        transferRegReg (m6502_reg_a, reg, false);
+        /*
+        TODO does not work for X<->Y
+      else if (m6502_reg_x->isLitConst && m6502_reg_x->litConst == c)
+        transferRegReg (m6502_reg_x, reg, false);
+        */
+      else
+        {
+          emit6502op ("ldy", IMMDFMT, c);
+        }
+      break;
+    case YX_IDX:
+      c &= 0xffff;
+      if (reg->isLitConst && reg->litConst == c)
+	break;
+      loadRegFromConst (m6502_reg_x, c);
+      loadRegFromConst (m6502_reg_y, c >> 8);
+      break;
+    case XA_IDX:
+      c &= 0xffff;
+      if (reg->isLitConst && reg->litConst == c)
+	break;
+      loadRegFromConst (m6502_reg_a, c);
+      loadRegFromConst (m6502_reg_x, c >> 8);
+      break;
+    default:
+      werror (E_INTERNAL_ERROR, __FILE__, __LINE__, "Bad rIdx in loadRegFromConst");
+      return;
+    }
+
+  m6502_dirtyReg (reg);
+  reg->isLitConst = 1;
+  reg->litConst = c;
+  if (reg->rIdx == YX_IDX)
+    {
+      m6502_reg_x->isLitConst = 1;
+      m6502_reg_x->litConst = c & 0xff;
+      m6502_reg_y->isLitConst = 1;
+      m6502_reg_y->litConst = (c >> 8) & 0xff;
+    }
+  if (reg->rIdx == XA_IDX)
+    {
+      m6502_reg_a->isLitConst = 1;
+      m6502_reg_a->litConst = c & 0xff;
+      m6502_reg_x->isLitConst = 1;
+      m6502_reg_x->litConst = (c >> 8) & 0xff;
+    }
+  m6502_useReg (reg);
+}
+
+/*--------------------------------------------------------------------------*/
+/* loadRegFromImm - Load register reg from immediate value c.               */
+/*--------------------------------------------------------------------------*/
+static void
+loadRegFromImm (reg_info * reg, char * c)
+{
+  emitComment (REGOPS, __func__ );
+
+  if(!c) {
+     werror (E_INTERNAL_ERROR, __FILE__, __LINE__, "loadRegFromImm called with a null arg pointer");
+  }
+
+  if (*c == '#')
+    c++;
+  switch (reg->rIdx)
+    {
+    case A_IDX:
+      emit6502op ("lda", "#%s", c);
+      break;
+    case X_IDX:
+      emit6502op ("ldx", "#%s", c);
+      break;
+    case Y_IDX:
+      emit6502op ("ldy", "#%s", c);
+      break;
+    case YX_IDX:
+      emit6502op ("ldx", "#%s", c);
+      emit6502op ("ldy", "#%s >> 8", c);
+      break;
+    case XA_IDX:
+      emit6502op ("lda", "#%s", c);
+      emit6502op ("ldx", "#%s >> 8", c);
+      break;
+    default:
+      werror (E_INTERNAL_ERROR, __FILE__, __LINE__, "Bad rIdx in loadRegFromConst");
+      return;
+    }
+  m6502_dirtyReg (reg);
+  m6502_useReg (reg);
+}
+
+/*--------------------------------------------------------------------------*/
+/* storeConstToAop- Store constant c to logical offset loffset of asmop aop.*/
+/*--------------------------------------------------------------------------*/
+static void
+storeConstToAop (int c, asmop * aop, int loffset)
+{
+  emitComment (REGOPS, __func__ );
+
+  if (aop->stacked && aop->stk_aop[loffset])
+    {
+      storeConstToAop (c, aop->stk_aop[loffset], 0);
+      return;
+    }
+
+  /* If the value needed is already in A, X or Y just store it */
+  if (m6502_reg_a->isLitConst && m6502_reg_a->litConst == c)
+    {
+      storeRegToAop (m6502_reg_a, aop, loffset);
+      return;
+    }
+  if (m6502_reg_x->isLitConst && m6502_reg_x->litConst == c)
+    {
+      storeRegToAop (m6502_reg_x, aop, loffset);
+      return;
+    }
+  if (m6502_reg_y->isLitConst && m6502_reg_y->litConst == c)
+    {
+      storeRegToAop (m6502_reg_y, aop, loffset);
+      return;
+    }
+
+  switch (aop->type)
+    {
+    case AOP_REG:
+      if (loffset > (aop->size - 1))
+        break;
+      loadRegFromConst (aop->aopu.aop_reg[loffset], c);
+      break;
+    case AOP_DUMMY:
+      break;
+    case AOP_DIR:
+    case AOP_EXT:
+      /* clr operates with read-modify-write cycles, so don't use if the */
+      /* destination is volatile to avoid the read side-effect. */
+      // TODO: same for 6502?
+#if 0
+      if (!c && IS_MOS65C02 && !(aop->op && isOperandVolatile (aop->op, false)))
+        {
+	  // FIXME: unimplemented
+          aopAdrPrepare(aop, loffset);
+          emitcode ("stz", "%s", aopAdrStr (aop, loffset, false));
+          aopAdrUnprepare(aop, loffset);
+          break;
+        }
+#endif
+    default:
+      if (m6502_reg_x->isFree && aop->type != AOP_SOF)
+        {
+          loadRegFromConst (m6502_reg_x, c);
+          storeRegToAop (m6502_reg_x, aop, loffset);
+          m6502_freeReg (m6502_reg_x);
+        }
+      else if (m6502_reg_y->isFree && aop->type != AOP_SOF)
+        {
+          loadRegFromConst (m6502_reg_y, c);
+          storeRegToAop (m6502_reg_y, aop, loffset);
+          m6502_freeReg (m6502_reg_y);
+        }
+      else
+        {
+          bool needpulla = pushRegIfUsed (m6502_reg_a);
+ //         pushReg (m6502_reg_a, true);
+          loadRegFromConst (m6502_reg_a, c);
+          storeRegToAop (m6502_reg_a, aop, loffset);
+//          pullReg (m6502_reg_a);
+          pullOrFreeReg (m6502_reg_a, needpulla);
+        }
+    }
+}
+
+/*--------------------------------------------------------------------------*/
+/* storeImmToAop- Store immediate value c to logical offset loffset of asmop aop.*/
+/*--------------------------------------------------------------------------*/
+static void
+storeImmToAop (char *c, asmop * aop, int loffset)
+{
+  emitComment (TRACE_AOP, __func__ );
+
+  if (aop->stacked && aop->stk_aop[loffset])
+    {
+      storeImmToAop (c, aop->stk_aop[loffset], 0);
+      return;
+    }
+
+  switch (aop->type)
+    {
+    case AOP_REG:
+      if (loffset > (aop->size - 1))
+        break;
+      loadRegFromImm (aop->aopu.aop_reg[loffset], c);
+      break;
+    case AOP_DUMMY:
+      break;
+    case AOP_DIR:
+      /* clr operates with read-modify-write cycles, so don't use if the */
+      /* destination is volatile to avoid the read side-effect. */
+      if (!strcmp (c, "#0x00") && IS_MOS65C02 && !(aop->op && isOperandVolatile (aop->op, false)))
+        {
+	  // FIXME: unimplemented
+          aopAdrPrepare(aop, loffset);
+          emitcode ("stz", "%s", aopAdrStr (aop, loffset, false));
+          aopAdrUnprepare(aop, loffset);
+          break;
+        }
+    default:
+      if (m6502_reg_x->isFree)
+        {
+          loadRegFromImm (m6502_reg_x, c);
+          storeRegToAop (m6502_reg_x, aop, loffset);
+          m6502_freeReg (m6502_reg_x);
+        }
+      else if (m6502_reg_y->isFree)
+        {
+          loadRegFromImm (m6502_reg_y, c);
+          storeRegToAop (m6502_reg_y, aop, loffset);
+          m6502_freeReg (m6502_reg_y);
+        }
+      else
+        {
+          bool needpulla = pushRegIfUsed (m6502_reg_a);
+          loadRegFromImm (m6502_reg_a, c);
+          storeRegToAop (m6502_reg_a, aop, loffset);
+          pullOrFreeReg (m6502_reg_a, needpulla);
+        }
+    }
+}
+
+static void
+signExtendA()
+{
+      emit6502op ("asl", "a");
+      loadRegFromConst (m6502_reg_a, 0);
+      emit6502op ("adc", "#0xff");
+      emit6502op ("eor", "#0xff");
+}
+
+/*--------------------------------------------------------------------------*/
+/* storeRegSignToUpperAop - If isSigned is true, the sign bit of register   */
+/*                          reg is extended to fill logical offsets loffset */
+/*                          and above of asmop aop. Otherwise, logical      */
+/*                          offsets loffset and above of asmop aop are      */
+/*                          zeroed. reg must be an 8-bit register.          */
+/*--------------------------------------------------------------------------*/
+static void
+storeRegSignToUpperAop (reg_info * reg, asmop * aop, int loffset, bool isSigned)
+{
+  emitComment (TRACE_AOP, __func__ );
+
+//  int regidx = reg->rIdx;
+  int size = aop->size;
+
+  if (size <= loffset)
+    return;
+
+  if (!isSigned)
+    {
+      /* Unsigned case */
+      while (loffset < size)
+        storeConstToAop (0, aop, loffset++);
+    }
+  else
+    {
+      /* Signed case */
+      transferRegReg (reg, m6502_reg_a, false);
+      signExtendA();
+      m6502_useReg (m6502_reg_a);
+      while (loffset < size)
+        storeRegToAop (m6502_reg_a, aop, loffset++);
+      m6502_freeReg (m6502_reg_a);
+    }
+}
+
+/*--------------------------------------------------------------------------*/
+/* storeRegToFullAop - Store register reg to asmop aop with appropriate     */
+/*                     padding and/or truncation as needed. If isSigned is  */
+/*                     true, sign extension will take place in the padding. */
+/*--------------------------------------------------------------------------*/
+static void
+storeRegToFullAop (reg_info *reg, asmop *aop, bool isSigned)
+{
+  int regidx = reg->rIdx;
+  int size = aop->size;
+
+  emitComment (TRACE_AOP, __func__ );
+
+  switch (regidx)
+    {
+    case A_IDX:
+    case X_IDX:
+    case Y_IDX:
+      storeRegToAop (reg, aop, 0);
+      if (size > 1 && isSigned && aop->type == AOP_REG && aop->aopu.aop_reg[0]->rIdx == A_IDX)
+        pushReg (m6502_reg_a, true);
+      storeRegSignToUpperAop (reg, aop, 1, isSigned);
+      if (size > 1 && isSigned && aop->type == AOP_REG && aop->aopu.aop_reg[0]->rIdx == A_IDX)
+        pullReg (m6502_reg_a);
+      break;
+    case YX_IDX:
+      if (size == 1)
+        {
+          storeRegToAop (m6502_reg_x, aop, 0);
+        }
+      else
+        {
+          storeRegToAop (reg, aop, 0);
+          storeRegSignToUpperAop (m6502_reg_y, aop, 2, isSigned);
+        }
+      break;
+    case XA_IDX:
+      if (size == 1)
+        {
+          storeRegToAop (m6502_reg_a, aop, 0);
+        }
+      else
+        {
+          storeRegToAop (reg, aop, 0);
+          storeRegSignToUpperAop (m6502_reg_x, aop, 2, isSigned);
+        }
+      break;
+    default:
+      wassert (0);
+    }
+}
+
+/*--------------------------------------------------------------------------*/
+/* transferAopAop - Transfer the value at logical offset srcofs of asmop    */
+/*                  srcaop to logical offset dstofs of asmop dstaop.        */
+/*--------------------------------------------------------------------------*/
+static void
+transferAopAop (asmop *srcaop, int srcofs, asmop *dstaop, int dstofs)
+{
+  bool needpula = false;
+  reg_info *reg = NULL;
+  bool keepreg = false;
+
+  emitComment (TRACE_AOP, __func__ );
+
+  wassert (srcaop && dstaop);
+
+  /* ignore transfers at the same byte, unless its volatile */
+  if (srcaop->op && !isOperandVolatile (srcaop->op, false)
+      && dstaop->op && !isOperandVolatile (dstaop->op, false)
+      && operandsEqu (srcaop->op, dstaop->op) && srcofs == dstofs && dstaop->type == srcaop->type)
+    return;
+
+  if (srcaop->stacked && srcaop->stk_aop[srcofs])
+    {
+      transferAopAop (srcaop->stk_aop[srcofs], 0, dstaop, dstofs);
+      return;
+    }
+
+  if (dstaop->stacked && dstaop->stk_aop[srcofs])
+    {
+      transferAopAop (srcaop, srcofs, dstaop->stk_aop[dstofs], 0);
+      return;
+    }
+
+  emitComment (TRACE_AOP|VVDBG, "  transferAopAop from (%s, %d)", aopName (srcaop), srcofs);
+  emitComment (TRACE_AOP|VVDBG, "  transferAopAop to (%s, %d)", aopName (dstaop), dstofs);
+//  DD(emitcode ("", "; srcaop->type = %d, regmask = %x", srcaop->type, srcaop->regmask));
+//  DD(emitcode ("", "; dstaop->type = %d, regmask = %x", dstaop->type, dstaop->regmask));
+
+  if (dstofs >= dstaop->size)
+    return;
+
+  // same registers and offset, no transfer
+  if (srcaop->type == AOP_REG && dstaop->type == AOP_REG)
+    {
+      transferRegReg(srcaop->aopu.aop_reg[srcofs], dstaop->aopu.aop_reg[dstofs], false);
+      return;    
+    }
+
+  if (srcaop->type == AOP_LIT)
+    {
+      storeConstToAop (byteOfVal (srcaop->aopu.aop_lit, srcofs), dstaop, dstofs);
+      return;
+    }
+  if (dstaop->type == AOP_REG)
+    {
+      reg = dstaop->aopu.aop_reg[dstofs];
+      keepreg = true;
+    }
+  else if ((srcaop->type == AOP_REG) && (srcaop->aopu.aop_reg[srcofs]))
+    {
+      reg = srcaop->aopu.aop_reg[srcofs];
+      keepreg = true;
+    }
+
+  // TODO: pick reg based on if can load op?
+  if (!reg)
+    {
+      reg = getFreeByteReg();
+      if (reg == NULL)
+        {
+	  pushReg (m6502_reg_a, true);
+	  needpula = true;
+          reg = m6502_reg_a;
+        }
+    }
+
+  loadRegFromAop (reg, srcaop, srcofs);
+  storeRegToAop (reg, dstaop, dstofs);
+
+  if (!keepreg)
+    pullOrFreeReg (reg, needpula);
+}
+
+#if 0
+/*--------------------------------------------------------------------------*/
+/* forceStackedAop - Reserve space on the stack for asmop aop; when         */
+/*                   freeAsmop is called with aop, the stacked data will    */
+/*                   be copied to the original aop location.                */
+/*--------------------------------------------------------------------------*/
+// TODO????
+static asmop *
+forceStackedAop (asmop * aop, bool copyOrig)
+{
+  reg_info *reg = NULL;
+  int offset;
+  bool needpula = false;
+  asmop *newaop = newAsmop (AOP_DIR);
+  memcpy (newaop, aop, sizeof (*newaop));
+  newaop->aopu.aop_dir = "__TEMP";
+
+  emitComment (TRACE_AOP|VVDBG, "  forcedStackedAop %s", aopName (aop));
+
+  if (copyOrig) {
+    reg = getFreeByteReg();
+    if (reg == NULL) {
+      reg = m6502_reg_a;
+      storeRegTemp(reg, true);
+      needpula = true;
+    }
+  }
+  for (offset=0; offsetsize; offset++)
+  {
+    asmop *aopsof = newAsmop (AOP_SOF);
+    aopsof->size = 1;
+    if (copyOrig)
+      {
+        loadRegFromAop (reg, aop, offset);
+        pushReg (reg, false);
+      } else {
+        pushReg (m6502_reg_a, false);
+      }
+    aopsof->aopu.aop_stk = -_G.stackOfs - _G.stackPushes;
+    aopsof->op = aop->op;
+    newaop->stk_aop[offset] = aopsof;
+  }
+
+  if (!reg && copyOrig)
+    {
+      for (offset = 0; offset < newaop->size; offset++)
+        {
+          transferAopAop (aop, offset, newaop, offset);
+        }
+    }  
+  newaop->stacked = 1;
+  // FIXME: use loadOrFree
+  if (needpula) loadRegTemp(reg);
+  return newaop;
+}
+#endif
+
+// TODO: fix these
+/*--------------------------------------------------------------------------*/
+/* accopWithAop - Emit accumulator modifying instruction accop with the     */
+/*                byte at logical offset loffset of asmop aop.              */
+/*                Supports: adc, and, cmp, eor, ora, sbc                    */
+/*--------------------------------------------------------------------------*/
+static void
+accopWithAop (char *accop, asmop *aop, int loffset)
+{
+  emitComment (TRACE_AOP, __func__ );
+
+  if (aop->stacked && aop->stk_aop[loffset])
+    {
+      accopWithAop (accop, aop->stk_aop[loffset], 0);
+      return;
+    }
+
+  if (aop->type == AOP_DUMMY)
+    return;
+
+  if (loffset >= aop->size)
+    {
+      emit6502op (accop, "#0x00");
+    }
+  else if (aop->type == AOP_REG)
+    {
+      // TODO FIXME: this needs forcestore
+      storeRegTemp (aop->aopu.aop_reg[loffset], true);
+      emit6502op (accop, TEMPFMT, _G.tempOfs - 1);
+      loadRegTemp(NULL);
+    }
+  else
+    {
+      aopAdrPrepare(aop, loffset);
+      emit6502op (accop, aopAdrStr (aop, loffset, false));
+      aopAdrUnprepare(aop, loffset);
+    }
+}
+
+
+/*--------------------------------------------------------------------------*/
+/* rmwWithReg - Emit read/modify/write instruction rmwop with register reg. */
+/*              byte at logical offset loffset of asmop aop. Register reg   */
+/*              must be 8-bit.                                              */
+/*              Supports: com, dec, inc, lsl, lsr, neg, rol, ror            */
+/*--------------------------------------------------------------------------*/
+static void
+rmwWithReg (char *rmwop, reg_info * reg)
+{
+  if (reg->rIdx == A_IDX)
+    {
+      if (!strcmp(rmwop, "inc")) {
+        if (IS_MOS65C02) {
+          emit6502op (rmwop, "a");
+        } else {
+          emit6502op ("clc", "");
+          emit6502op ("adc", "#0x01");
+        }
+      } else if (!strcmp(rmwop, "dec")) {
+        if (IS_MOS65C02) {
+          emit6502op (rmwop, "a");
+        } else {
+          emit6502op ("sec", "");
+          emit6502op ("sbc", "#0x01");
+        }
+      } else if (!strcmp(rmwop, "com")) {
+        emit6502op ("eor", "#0xff");
+      } else if (!strcmp(rmwop, "neg")) {
+        emit6502op ("eor", "#0xff");
+        emit6502op ("clc", "");
+        emit6502op ("adc", "#0x01");
+      } else if (!strcmp(rmwop, "asr")) {
+        emit6502op ("cmp", "#0x80");
+        emit6502op ("ror", "a");
+      } else if (!strcmp(rmwop, "bit")) { // TODO???
+        // werror (E_INTERNAL_ERROR, __FILE__, __LINE__, "rmwWithReg: rmwop==\"bit\"");
+        emit6502op ("cmp", "#0x00");
+      } else {
+        emit6502op (rmwop, "a");
+      }
+    }
+  else if (reg->rIdx == X_IDX)
+    {
+      if (!strcmp(rmwop, "inc")) {
+        emit6502op ("inx", "");
+      } else if (!strcmp(rmwop, "dec")) {
+        emit6502op ("dex", "");
+      } else {
+        bool needpulla = pushRegIfUsed (m6502_reg_a);
+        transferRegReg (m6502_reg_x, m6502_reg_a, true);
+        rmwWithReg (rmwop, m6502_reg_a);
+        transferRegReg (m6502_reg_a, m6502_reg_x, true);
+        pullOrFreeReg (m6502_reg_a, needpulla);
+      }
+    }
+  else if (reg->rIdx == Y_IDX)
+    {
+      if (!strcmp(rmwop, "inc")) {
+        emit6502op ("iny", "");
+      } else if (!strcmp(rmwop, "dec")) {
+        emit6502op ("dey", "");
+      } else {
+        bool needpulla = pushRegIfUsed (m6502_reg_a);
+        transferRegReg (m6502_reg_y, m6502_reg_a, true);
+        rmwWithReg (rmwop, m6502_reg_a);
+        transferRegReg (m6502_reg_a, m6502_reg_y, true);
+        pullOrFreeReg (m6502_reg_a, needpulla);
+      }
+    }
+  else
+    {
+      wassertl(0, "rmwWithReg()");
+    }
+  // always dirty dest. register
+  //  m6502_dirtyReg (reg);
+}
+
+/*--------------------------------------------------------------------------*/
+/* rmwWithAop - Emit read/modify/write instruction rmwop with the byte at   */
+/*                logical offset loffset of asmop aop.                      */
+/*                Supports: bit, dec, inc, lsl, lsr, neg, rol, ror          */
+/*--------------------------------------------------------------------------*/
+static void
+rmwWithAop (char *rmwop, asmop * aop, int loffset)
+{
+  bool needpull = false;
+  emitComment (TRACE_AOP, __func__ );
+
+  if (aop->stacked && aop->stk_aop[loffset])
+    {
+      rmwWithAop (rmwop, aop->stk_aop[loffset], 0);
+      return;
+    }
+
+  switch (aop->type)
+    {
+    case AOP_REG:
+      rmwWithReg (rmwop, aop->aopu.aop_reg[loffset]);
+      break;
+    case AOP_DIR:
+    case AOP_EXT:
+      aopAdrPrepare(aop, loffset);
+      // TODO: this sucks
+      if (!strcmp("asr", rmwop)) {
+        emit6502op ("pha", "");
+        emit6502op ("lda", aopAdrStr(aop, loffset, false)); // load 
+        emit6502op ("cmp", "#0x80");
+        emit6502op ("pla", "");
+        rmwop = "ror";
+      }
+      emit6502op (rmwop, aopAdrStr(aop, loffset, false));
+      aopAdrUnprepare(aop, loffset);
+      break;
+    case AOP_DUMMY:
+      break;
+    case AOP_SOF:
+      {
+	 emitComment (TRACE_AOP, "  rmwWithAop AOP_SOF");
+        // TODO: does anything but A make sense here?
+        reg_info * reg = getFreeByteReg();
+        if (!reg) reg = m6502_reg_a;
+        int offset = loffset; // SEH: aop->size - 1 - loffset;
+        offset += _G.stackOfs + _G.stackPushes + aop->aopu.aop_stk + 1;
+	//    if ((offset > 0xff) || (offset < 0))
+          {
+	    emitComment (TRACE_AOP, "  rmwWithAop large offset");
+            /* Unfortunately, the rmw class of instructions only support a */
+            /* single byte stack pointer offset and we need two. */
+            needpull = pushRegIfUsed (reg);
+            loadRegFromAop (reg, aop, loffset);
+            rmwWithReg (rmwop, reg);
+            if (strcmp ("tst", rmwop)) //TODO: no tst
+              storeRegToAop (reg, aop, loffset);
+            pullOrFreeReg (reg, needpull);
+            break;
+          }
+        /* If the offset is small enough, fall through to default case */
+      }
+    default:
+      emitComment (TRACE_AOP, "  rmwWithAop small offset ");
+      // TODO: [aa],y dosn't work with inc/dec
+//      emitcode (rmwop, "%s ;type %d", aopAdrStr (aop, loffset, false), aop->type);
+      emit6502op (rmwop, aopAdrStr (aop, loffset, false));
+    }
+
+}
+
+/*--------------------------------------------------------------------------*/
+/* loadRegIndexed - Load a register using indexed addressing mode.          */
+/*                  NOTE: offset is physical (not logical)                  */
+/*--------------------------------------------------------------------------*/
+static void
+loadRegIndexed (reg_info * reg, int offset, char * rematOfs)
+{
+  bool needpula = false;
+
+  emitComment (REGOPS, "      loadRegIndexed (%s, %d, %s)", reg->name, offset, rematOfs);
+
+  /* The rematerialized offset may have a "#" prefix; skip over it */
+  if (rematOfs && rematOfs[0] == '#')
+    rematOfs++;
+  if (rematOfs && !rematOfs[0])
+    rematOfs = NULL;
+
+  /* force offset to signed 16-bit range */
+  offset &= 0xffff;
+  if (offset & 0x8000)
+    offset = 0x10000 - offset;
+
+// TODO: mostly awful
+  switch (reg->rIdx)
+    {
+    case A_IDX:
+      // TODO: have to remove dead Y loads
+      // addr is in (y,x) but y == 0, so 8-bit offset
+      if (!rematOfs && offset >= 0 && offset <= 0xff)
+        {
+          // FIXME: lots of failures if switch to isDead
+          bool restoreY = ! m6502_reg_y->isFree;
+//          bool restoreY = ! m6502_reg_y->isDead;
+          storeRegTemp (m6502_reg_x, false);
+          storeRegTemp (m6502_reg_y, false);
+          loadRegFromConst(m6502_reg_y, offset);
+          emit6502op ("lda", TEMPFMT_IY, _G.tempOfs - 2);
+          // TODO: isDead?
+// check here *****
+          loadRegTemp (restoreY ? m6502_reg_y: NULL );
+          loadRegTemp (NULL); // x not changed
+        }
+      else
+        {
+          // add remat + offset + YX
+          transferRegReg (m6502_reg_x, m6502_reg_a, true);
+          emit6502op ("clc", "");
+          emit6502op ("adc", "#<(%s+%d)", rematOfs, offset);
+          int tIdx=_G.tempOfs;
+          storeRegTemp(m6502_reg_a, true);
+          transferRegReg (m6502_reg_y, m6502_reg_a, true);
+          emit6502op ("adc", "#>(%s+%d)", rematOfs, offset);
+          storeRegTemp(m6502_reg_a, true);
+          bool py = storeRegTempIfSurv(m6502_reg_y);
+          loadRegFromConst(m6502_reg_y, 0);
+          emit6502op ("lda", TEMPFMT_IY, tIdx);
+          loadOrFreeRegTemp(m6502_reg_y,py);
+          loadRegTemp(NULL);
+          loadRegTemp(NULL);
+          }
+      break;
+    case X_IDX:
+    case Y_IDX:	
+//      pushReg (m6502_reg_a, false);
+//      needpula = true;
+      needpula = pushRegIfSurv(m6502_reg_a);
+      loadRegIndexed (m6502_reg_a, offset, rematOfs);
+      transferRegReg (m6502_reg_a, reg, true);
+      break;
+    case YX_IDX:
+      needpula = pushRegIfSurv(m6502_reg_a);
+      loadRegIndexed (m6502_reg_a, offset+1, rematOfs);
+      storeRegTemp (m6502_reg_a, true);
+      loadRegIndexed (m6502_reg_a, offset, rematOfs);
+      transferRegReg (m6502_reg_a, m6502_reg_x, true);
+      loadRegTemp (m6502_reg_y);
+      break;
+    case XA_IDX:
+      loadRegIndexed (m6502_reg_a, offset, rematOfs);
+      pushReg (m6502_reg_a, true);
+      needpula = true;
+//      needpula = pushRegIfSurv(m6502_reg_a);
+      loadRegIndexed (m6502_reg_x, offset+1, rematOfs);
+      break;
+    default:
+      wassert (0);
+    }
+  pullOrFreeReg (m6502_reg_a, needpula);
+}
+
+static int prepTempOfs = -1;
+static char* tempRematOfs = "???";
+static bool prepSwapAY;
+
+/*--------------------------------------------------------------------------*/
+/* storeRegIndexed - Store a register using indexed addressing mode.        */
+/*                   NOTE: offset is physical (not logical)                 */
+/*--------------------------------------------------------------------------*/
+static void
+storeRegIndexed (reg_info * reg, int offset, char * rematOfs)
+{
+  bool needpula = false;
+
+  emitComment (REGOPS, "      storeRegIndexed (%s, %d, %s)", reg->name, offset, rematOfs);
+
+  /* The rematerialized offset may have a "#" prefix; skip over it */
+  if (rematOfs && rematOfs[0] == '#')
+    rematOfs++;
+  if (rematOfs && !rematOfs[0])
+    rematOfs = NULL;
+
+  /* force offset to signed 16-bit range */
+  offset &= 0xffff;
+  if (offset & 0x8000)
+    offset = offset - 0x10000;
+
+  switch (reg->rIdx)
+    {
+    case A_IDX:
+      if (!rematOfs && offset >= 0 && offset <= 0xff)
+        {
+          bool restoreY = ! m6502_reg_y->isFree;
+          storeRegTemp (m6502_reg_x, false);
+          storeRegTemp (m6502_reg_y, false);
+          loadRegFromConst(m6502_reg_y, offset);
+          emit6502op ("sta", TEMPFMT_IY, _G.tempOfs - 2);
+          // FIXME: changing this to isDead makes regression fail
+// *****
+          loadRegTemp (restoreY ? m6502_reg_y : NULL);
+          loadRegTemp (NULL); // x is not clobbered
+        }
+      else
+        {
+          // add remat + offset + YX
+          int ptrOfs;
+          bool needloady;
+
+          if(!rematOfs) rematOfs="0";
+
+          pushReg(m6502_reg_a, false);
+          ptrOfs=_G.tempOfs;
+          transferRegReg (m6502_reg_x, m6502_reg_a, true);
+          emit6502op ("clc", "");
+          emit6502op ("adc", "#<(%s+%d)", rematOfs, offset);
+          storeRegTemp (m6502_reg_a, true);
+          transferRegReg (m6502_reg_y, m6502_reg_a, true);
+          emit6502op ("adc", "#>(%s+%d)", rematOfs, offset);
+          storeRegTemp (m6502_reg_a, true);
+          needloady = storeRegTempIfSurv (m6502_reg_y);
+          loadRegFromConst(m6502_reg_y, 0);
+          pullReg(m6502_reg_a);
+          emit6502op ("sta", TEMPFMT_IY, ptrOfs); // [aa],y
+          loadOrFreeRegTemp(m6502_reg_y, needloady);
+          loadRegTemp(NULL);
+          loadRegTemp(NULL);
+        }
+      break;
+    case X_IDX:
+      needpula = pushRegIfUsed (m6502_reg_a);
+      transferRegReg (m6502_reg_x, m6502_reg_a, true);
+      storeRegIndexed (m6502_reg_a, offset, rematOfs);
+      pullOrFreeReg (m6502_reg_a, needpula);
+      break;
+    case Y_IDX:
+      needpula = pushRegIfUsed (m6502_reg_a);
+      transferRegReg (m6502_reg_y, m6502_reg_a, true);
+      storeRegIndexed (m6502_reg_a, offset, rematOfs);
+      pullOrFreeReg (m6502_reg_a, needpula);
+      break;
+    case YX_IDX:
+      storeRegIndexed (m6502_reg_y, offset+1, rematOfs);
+      storeRegIndexed (m6502_reg_x, offset, rematOfs);
+      break;
+    case XA_IDX:
+      /* This case probably won't happen, but it's easy to implement */
+      /* SEH: it did happen in bug-1029883? */
+      storeRegIndexed (m6502_reg_x, offset+1, rematOfs);
+      storeRegIndexed (m6502_reg_a, offset, rematOfs);
+      break;
+    default:
+      wassert (0);
+    }
+}
+
+#if 0
+/*--------------------------------------------------------------------------*/
+/* storeRegIndexed2 - Store a register using indexed addressing mode.        */
+/*                   NOTE: offset is physical (not logical)                 */
+/* must call preparePointer() first */
+/*--------------------------------------------------------------------------*/
+static void
+storeRegIndexed2 (reg_info * reg, int offset)
+{
+  bool needpula = false;
+
+  emitComment (REGOPS, "      storeRegIndexed (%s, %d)", reg->name, offset);
+
+  /* force offset to signed 16-bit range */
+  offset &= 0xffff;
+  if (offset & 0x8000)
+    offset = offset - 0x10000;
+
+  switch (reg->rIdx)
+    {
+    case A_IDX:
+      if (prepTempOfs < 0)
+        {
+          emit6502op ("sta", "(%s+%d),y", tempRematOfs, offset);
+        }
+      else
+        {
+          loadRegFromConst(m6502_reg_y, offset);
+          emit6502op ("sta", TEMPFMT_IY, prepTempOfs);
+        }
+      break;
+    case X_IDX:
+      needpula = pushRegIfUsed (m6502_reg_a);
+      transferRegReg (m6502_reg_x, m6502_reg_a, true);
+      storeRegIndexed2 (m6502_reg_a, offset);
+      pullOrFreeReg (m6502_reg_a, needpula);
+      break;
+    case Y_IDX:
+      needpula = pushRegIfUsed (m6502_reg_a);
+      transferRegReg (m6502_reg_y, m6502_reg_a, true);
+      storeRegIndexed2 (m6502_reg_a, offset);
+      pullOrFreeReg (m6502_reg_a, needpula);
+      break;
+    case YX_IDX:
+      storeRegIndexed2 (m6502_reg_y, offset+1);
+      storeRegIndexed2 (m6502_reg_x, offset);
+      break;
+    case XA_IDX:
+      /* This case probably won't happen, but it's easy to implement */
+      /* SEH: it did happen in bug-1029883? */
+      storeRegIndexed2 (m6502_reg_x, offset+1);
+      storeRegIndexed2 (m6502_reg_a, offset);
+      break;
+    default:
+      wassert (0);
+    }
+}
+#endif
+
+/*-----------------------------------------------------------------*/
+/* newAsmop - creates a new asmOp                                  */
+/*-----------------------------------------------------------------*/
+static asmop *
+newAsmop (short type)
+{
+  asmop *aop;
+// TODO: are these ever freed?
+  aop = Safe_calloc (1, sizeof (asmop));
+  aop->type = type;
+  aop->op = NULL;
+  return aop;
+}
+
+
+/*-----------------------------------------------------------------*/
+/* operandConflictsWithYX - true if operand in h and/or x register */
+/*-----------------------------------------------------------------*/
+static bool
+operandConflictsWithYX (operand *op)
+{
+  symbol *sym;
+  int i;
+
+  if (IS_ITEMP (op))
+    {
+      sym = OP_SYMBOL (op);
+      if (!sym->isspilt)
+        {
+          for(i = 0; i < sym->nRegs; i++)
+            if (sym->regs[i] == m6502_reg_y || sym->regs[i] == m6502_reg_x)
+              return true;
+        }
+    }
+
+  return false;
+}
+
+/*-----------------------------------------------------------------*/
+/* operandConflictsWithX - true if operand in x register */
+/*-----------------------------------------------------------------*/
+static bool
+operandConflictsWithX (operand *op)
+{
+  symbol *sym;
+  int i;
+
+  if (IS_ITEMP (op))
+    {
+      sym = OP_SYMBOL (op);
+      if (!sym->isspilt)
+        {
+          for(i = 0; i < sym->nRegs; i++)
+            if (sym->regs[i] == m6502_reg_x)
+              return true;
+        }
+    }
+
+  return false;
+}
+
+/*-----------------------------------------------------------------*/
+/* operandOnStack - returns True if operand is on the stack        */
+/*-----------------------------------------------------------------*/
+static bool
+operandOnStack(operand *op)
+{
+  symbol *sym;
+
+  if (!op || !IS_SYMOP (op))
+    return false;
+  sym = OP_SYMBOL (op);
+  if (!sym->isspilt && sym->onStack)
+    return true;
+  if (sym->isspilt)
+    {
+      sym = sym->usl.spillLoc;
+      if (sym && sym->onStack)
+        return true;
+    }
+  return false;
+}
+
+/*-----------------------------------------------------------------*/
+/* tsxUseful - returns True if tsx could help at least one         */
+/*             anticipated stack reference                         */
+/*-----------------------------------------------------------------*/
+static bool
+tsxUseful(iCode *ic)
+{
+  int uses = 0;
+
+  if (ic->op == CALL)
+    {
+      if (IC_RESULT (ic) && operandSize (IC_RESULT (ic)) < 2 && operandOnStack (IC_RESULT (ic)))
+        {
+          uses++;
+          ic = ic->next;
+        }
+    }
+
+  while (ic && uses < 1)
+    {
+      if (ic->op == IFX)
+        {
+          if (operandOnStack (IC_COND (ic)))
+            uses += operandSize(IC_COND (ic));
+          break;
+        }
+      else if (ic->op == JUMPTABLE)
+        {
+          if (operandOnStack (IC_JTCOND (ic)))
+            uses++;
+          break;
+        }
+      else if (ic->op == ADDRESS_OF)
+        {
+          if (operandOnStack (IC_RIGHT (ic)))
+            break;
+        }
+      else if (ic->op == LABEL || ic->op == GOTO || ic->op == CALL || ic->op == PCALL)
+        break;
+      else if (POINTER_SET (ic) || POINTER_GET (ic))
+        break;
+      else
+        {
+          if (operandConflictsWithYX (IC_RESULT (ic)))
+            break;
+          if (operandOnStack (IC_LEFT (ic)))
+            uses += operandSize (IC_LEFT (ic));
+          if (operandOnStack (IC_RIGHT (ic)))
+            uses += operandSize (IC_RIGHT (ic));
+          if (operandOnStack (IC_RESULT (ic)))
+            uses += operandSize (IC_RESULT (ic));
+        }
+
+      ic = ic->next;
+    }
+
+  return uses >= 1;
+}
+
+static void doTSX()
+{
+  // already did TSX
+  if (m6502_reg_x->aop == &tsxaop)
+    return;
+  // put stack pointer in X
+  if(!m6502_reg_x->isFree)
+    emitcode("ERROR","doTSX called with X in use");
+  emit6502op ("tsx", "");
+  m6502_dirtyReg (m6502_reg_x);
+  m6502_reg_x->aop = &tsxaop;
+  _G.tsxStackPushes = _G.stackPushes;
+}
+
+// TODO: make these subroutines
+static void saveBasePtr()
+{
+#if 0
+  storeRegTemp (m6502_reg_x, true); // TODO: only when used?
+  // TODO: if X is free should we call doTSX() to mark X=S?
+  doTSX();
+  emit6502op ("stx", BASEPTR);
+  _G.baseStackPushes = _G.stackPushes;
+  loadRegTemp (m6502_reg_x);
+#endif
+}
+
+static void
+restoreBasePtr()
+{
+  // we recompute with saveBasePtr() after each jsr
+}
+
+/*-----------------------------------------------------------------*/
+/* aopForSym - for a true symbol                                   */
+/*-----------------------------------------------------------------*/
+static asmop *
+aopForSym (iCode * ic, symbol * sym, bool result)
+{
+  asmop *aop;
+  memmap *space;
+
+  wassertl (ic != NULL, "Got a null iCode");
+  wassertl (sym != NULL, "Got a null symbol");
+
+//  printf("in aopForSym for symbol %s\n", sym->name);
+
+  space = SPEC_OCLS (sym->etype);
+
+  /* if already has one */
+  if (sym->aop)
+    {
+      return sym->aop;
+    }
+
+  /* special case for a function */
+  if (IS_FUNC (sym->type))
+    {
+      sym->aop = aop = newAsmop (AOP_IMMD);
+      aop->aopu.aop_immd.aop_immd1 = Safe_calloc (1, strlen (sym->rname) + 1 + 6);
+      sprintf (aop->aopu.aop_immd.aop_immd1, "(%s)", sym->rname); // function pointer; take back one for RTS
+      aop->size = FARPTRSIZE;
+      return aop;
+    }
+
+  /* if it is on the stack */
+  if (sym->onStack)
+    {
+      sym->aop = aop = newAsmop (AOP_SOF);
+      aop->aopu.aop_dir = sym->rname;
+      aop->size = getSize (sym->type);
+      aop->aopu.aop_stk = sym->stack;
+
+      if (!regalloc_dry_run && m6502_reg_x->isFree && m6502_reg_x->aop != &tsxaop)
+        {
+          if (!m6502_reg_x->isDead)
+            return aop;
+          if (ic->op == IFX && operandConflictsWithX (IC_COND (ic)))
+            return aop;
+          else if (ic->op == JUMPTABLE && operandConflictsWithX (IC_JTCOND (ic)))
+            return aop;
+          else
+            {
+              // FIXME: this is likely incorrect at YX is not a adr register in the 6502
+              /* If this is a pointer gen/set, then hx is definitely in use */
+              if (POINTER_SET (ic) || POINTER_GET (ic))
+                return aop;
+              if (ic->op == ADDRESS_OF)
+                return aop;
+              if (operandConflictsWithX (IC_LEFT (ic)))
+                return aop;
+              if (operandConflictsWithX (IC_RIGHT (ic)))
+                return aop;
+            }
+          // TODO?
+          /* It's safe to use tsx here. */
+          if (!tsxUseful (ic))
+            return aop;
+          // transfer S to X
+          doTSX();
+        }
+      return aop;
+    }
+
+  /* if it is in direct space */
+  if (IN_DIRSPACE (space))
+    {
+      sym->aop = aop = newAsmop (AOP_DIR);
+      aop->aopu.aop_dir = sym->rname;
+      aop->size = getSize (sym->type);
+      return aop;
+    }
+
+  /* default to far space */
+  sym->aop = aop = newAsmop (AOP_EXT);
+  aop->aopu.aop_dir = sym->rname;
+  aop->size = getSize (sym->type);
+  return aop;
+}
+
+/*-----------------------------------------------------------------*/
+/* aopForRemat - rematerializes an object                          */
+/*-----------------------------------------------------------------*/
+static asmop *
+aopForRemat (symbol * sym)
+{
+  iCode *ic = sym->rematiCode;
+  asmop *aop = NULL;
+  int val = 0;
+
+  if (!ic)
+    {
+      fprintf (stderr, "Symbol %s to be rematerialized, but has no rematiCode.\n", sym->name);
+      wassert (0);
+    }
+
+  for (;;)
+    {
+      if (ic->op == '+')
+        val += (int) operandLitValue (IC_RIGHT (ic));
+      else if (ic->op == '-')
+        val -= (int) operandLitValue (IC_RIGHT (ic));
+      else if (IS_CAST_ICODE (ic))
+        {
+          ic = OP_SYMBOL (IC_RIGHT (ic))->rematiCode;
+          continue;
+        }
+      else
+        break;
+
+      ic = OP_SYMBOL (IC_LEFT (ic))->rematiCode;
+    }
+
+  if (ic->op == ADDRESS_OF)
+    {
+      if (val)
+        {
+          SNPRINTF (buffer, sizeof (buffer),
+                    "(%s %c 0x%04x)", OP_SYMBOL (IC_LEFT (ic))->rname, val >= 0 ? '+' : '-', abs (val) & 0xffff);
+        }
+      else
+        {
+          strncpyz (buffer, OP_SYMBOL (IC_LEFT (ic))->rname, sizeof (buffer));
+        }
+
+      aop = newAsmop (AOP_IMMD);
+      aop->aopu.aop_immd.aop_immd1 = Safe_strdup (buffer);
+      /* set immd2 field if required */
+    }
+  else if (ic->op == '=')
+    {
+      val += (int) operandLitValue (IC_RIGHT (ic));
+      val &= 0xffff;
+      SNPRINTF (buffer, sizeof (buffer), "0x%04x", val);
+      aop = newAsmop (AOP_LIT);
+      aop->aopu.aop_lit = constVal (buffer);
+    }
+  else
+    {
+      werror (E_INTERNAL_ERROR, __FILE__, __LINE__, "unexpected rematerialization");
+    }
+
+  return aop;
+}
+
+/*-----------------------------------------------------------------*/
+/* regsInCommon - two operands have some registers in common       */
+/*-----------------------------------------------------------------*/
+static bool
+regsInCommon (operand * op1, operand * op2)
+{
+  symbol *sym1, *sym2;
+  int i;
+
+  /* if they have registers in common */
+  if (!IS_SYMOP (op1) || !IS_SYMOP (op2))
+    return false;
+
+  sym1 = OP_SYMBOL (op1);
+  sym2 = OP_SYMBOL (op2);
+
+  if (sym1->nRegs == 0 || sym2->nRegs == 0)
+    return false;
+
+  for (i = 0; i < sym1->nRegs; i++)
+    {
+      int j;
+      if (!sym1->regs[i])
+        continue;
+
+      for (j = 0; j < sym2->nRegs; j++)
+        {
+          if (!sym2->regs[j])
+            continue;
+
+          if (sym2->regs[j] == sym1->regs[i])
+            return true;
+        }
+    }
+
+  return false;
+}
+
+/*-----------------------------------------------------------------*/
+/* operandsEqu - equivalent                                        */
+/*-----------------------------------------------------------------*/
+static bool
+operandsEqu (operand *op1, operand *op2)
+{
+  symbol *sym1, *sym2;
+
+  /* if they not symbols */
+  if (!IS_SYMOP (op1) || !IS_SYMOP (op2))
+    return false;
+
+  sym1 = OP_SYMBOL (op1);
+  sym2 = OP_SYMBOL (op2);
+
+  /* if both are itemps & one is spilt
+     and the other is not then false */
+  if (IS_ITEMP (op1) && IS_ITEMP (op2) && sym1->isspilt != sym2->isspilt)
+    return false;
+
+  /* if they are the same */
+  if (sym1 == sym2)
+    return true;
+
+  /* if they have the same rname */
+  if (sym1->rname[0] && sym2->rname[0] && strcmp (sym1->rname, sym2->rname) == 0)
+    return true;
+
+  /* if left is a tmp & right is not */
+  if (IS_ITEMP (op1) && !IS_ITEMP (op2) && sym1->isspilt && (sym1->usl.spillLoc == sym2))
+    return true;
+
+  if (IS_ITEMP (op2) && !IS_ITEMP (op1) && sym2->isspilt && sym1->level > 0 && (sym2->usl.spillLoc == sym1))
+    return true;
+
+  return false;
+}
+
+/*-----------------------------------------------------------------*/
+/* sameRegs - two asmops have the same registers                   */
+/*-----------------------------------------------------------------*/
+static bool
+sameRegs (asmop * aop1, asmop * aop2)
+{
+  int i;
+
+  if (aop1 == aop2)
+    return true;
+
+//  if (aop1->size != aop2->size)
+//    return false;
+
+  if (aop1->type == aop2->type)
+    {
+      switch (aop1->type)
+        {
+        case AOP_REG:
+          for (i = 0; i < aop1->size; i++)
+            if (aop1->aopu.aop_reg[i] != aop2->aopu.aop_reg[i])
+              return false;
+          return true;
+        case AOP_SOF:
+          return (aop1->aopu.aop_stk == aop2->aopu.aop_stk);
+        case AOP_DIR:
+//          if (regalloc_dry_run)
+//            return false; // TODO: why?
+        case AOP_EXT:
+          return (!strcmp (aop1->aopu.aop_dir, aop2->aopu.aop_dir));
+        }
+    }
+
+  return false;
+}
+
+/*-----------------------------------------------------------------*/
+/* aopCanIncDec - asmop is EXT or DIR or X/Y                            */
+/*-----------------------------------------------------------------*/
+static bool
+aopCanIncDec (asmop * aop)
+{
+  switch (aop->type) {
+    case AOP_REG:
+      if(aop->aopu.aop_reg[0]->rIdx == A_IDX) return false;
+    case AOP_DIR:
+    case AOP_EXT:
+      return true;
+  }
+  return false;
+}
+
+/*-----------------------------------------------------------------*/
+/* aopCanShift - asmop is EXT or DIR or A                          */
+/*-----------------------------------------------------------------*/
+static bool
+aopCanShift (asmop * aop)
+{
+  switch (aop->type) {
+    case AOP_REG:
+      return ((aop->size == 1) && (aop->aopu.aop_reg[0]->rIdx == A_IDX));
+    case AOP_DIR:
+    case AOP_EXT:
+      return true;
+  }
+  return false;
+}
+
+/*-----------------------------------------------------------------*/
+/* aopOp - allocates an asmop for an operand  :                    */
+/*-----------------------------------------------------------------*/
+static void
+aopOp (operand *op, iCode * ic, bool result)
+{
+  asmop *aop = NULL;
+  symbol *sym;
+  int i;
+
+  emitComment (TRACE_AOP, __func__);
+
+  if (!op)
+    return;
+
+  /* if already has an asmop */
+  if (op->aop)
+    return;
+
+  // Is this a pointer set result?
+  //
+  if ((op == IC_RESULT (ic)) && POINTER_SET (ic))
+    {
+    }
+
+//  printf("checking literal\n");
+  /* if this a literal */
+  if (IS_OP_LITERAL (op))
+    {
+      //op->aop = 
+      aop = newAsmop (AOP_LIT);
+      aop->aopu.aop_lit = OP_VALUE (op);
+      aop->size = getSize (operandType (op));
+      op->aop = aop;
+      return;
+    }
+
+
+//  printf("checking underlying sym\n");
+  /* if the underlying symbol has a aop */
+  if (IS_SYMOP (op) && OP_SYMBOL (op)->aop)
+    {
+      op->aop = aop = Safe_calloc (1, sizeof (*aop));
+      memcpy (aop, OP_SYMBOL (op)->aop, sizeof (*aop));
+      //op->aop = aop = OP_SYMBOL (op)->aop;
+      aop->size = getSize (operandType (op));
+      //printf ("reusing underlying symbol %s\n",OP_SYMBOL (op)->name);
+      //printf (" with size = %d\n", aop->size);
+
+      aop->op = op;
+      return;
+    }
+
+//  printf("checking true sym\n");
+  /* if this is a true symbol */
+  if (IS_TRUE_SYMOP (op))
+    {
+      op->aop = aop = aopForSym (ic, OP_SYMBOL (op), result);
+      aop->op = op;
+      //printf ("new symbol %s\n", OP_SYMBOL (op)->name);
+      //printf (" with size = %d\n", aop->size);
+      return;
+    }
+
+  /* this is a temporary : this has
+     only five choices :
+     a) register
+     b) spillocation
+     c) rematerialize
+     d) conditional
+     e) can be a return use only */
+
+  if (!IS_SYMOP (op))
+    piCode (ic, NULL);
+  sym = OP_SYMBOL (op);
+
+//  printf("checking conditional\n");
+  /* if the type is a conditional */
+  if (sym->regType == REG_CND)
+    {
+      sym->aop = op->aop = aop = newAsmop (AOP_CRY);
+      aop->size = 0;
+      aop->op = op;
+      return;
+    }
+
+//  printf("checking spilt\n");
+  /* if it is spilt then two situations
+     a) is rematerialize
+     b) has a spill location */
+  if (sym->isspilt || sym->nRegs == 0)
+    {
+//      printf("checking remat\n");
+      /* rematerialize it NOW */
+      if (sym->remat)
+        {
+          sym->aop = op->aop = aop = aopForRemat (sym);
+          aop->size = getSize (sym->type);
+          aop->op = op;
+          return;
+        }
+
+       wassertl (!sym->ruonly, "sym->ruonly not supported");
+
+       if (regalloc_dry_run)     // Todo: Handle dummy iTemp correctly
+        {
+          if (options.stackAuto || (currFunc && IFFUNC_ISREENT (currFunc->type)))
+            {
+              sym->aop = op->aop = aop = newAsmop (AOP_SOF);
+              aop->aopu.aop_stk = 8; /* bogus stack offset, high enough to prevent optimization */
+            }
+          else
+            {
+              sym->aop = op->aop = aop = newAsmop (AOP_DIR);
+              aop->aopu.aop_dir = sym->name; //TODO? avoids crashing in sameRegs()
+            }
+          aop->size = getSize (sym->type);
+          aop->op = op;
+          return;
+        }
+
+      /* else spill location  */
+      if (sym->isspilt && sym->usl.spillLoc || regalloc_dry_run)
+        {
+          asmop *oldAsmOp = NULL;
+
+          if (sym->usl.spillLoc->aop && sym->usl.spillLoc->aop->size != getSize (sym->type))
+            {
+              /* force a new aop if sizes differ */
+              oldAsmOp = sym->usl.spillLoc->aop;
+              sym->usl.spillLoc->aop = NULL;
+              //printf ("forcing new aop\n");
+            }
+          sym->aop = op->aop = aop = aopForSym (ic, sym->usl.spillLoc, result);
+          if (sym->usl.spillLoc->aop->size != getSize (sym->type))
+            {
+              /* Don't reuse the new aop, go with the last one */
+              sym->usl.spillLoc->aop = oldAsmOp;
+            }
+          aop->size = getSize (sym->type);
+          aop->op = op;
+          //printf ("spill symbol %s\n", OP_SYMBOL (op)->name);
+          //printf (" with size = %d\n", aop->size);
+          return;
+        }
+
+      /* else must be a dummy iTemp */
+      sym->aop = op->aop = aop = newAsmop (AOP_DUMMY);
+      aop->size = getSize (sym->type);
+      aop->op = op;
+      return;
+    }
+
+//  printf("assuming register\n");
+  /* must be in a register */
+  wassert (sym->nRegs);
+  sym->aop = op->aop = aop = newAsmop (AOP_REG);
+  aop->size = sym->nRegs;
+  for (i = 0; i < sym->nRegs; i++)
+    {
+       wassert (sym->regs[i] < regsm6502 + 3);
+       aop->aopu.aop_reg[i] = sym->regs[i];
+       aop->regmask |= sym->regs[i]->mask;
+    }
+  if ((sym->nRegs > 1) && (sym->regs[0]->mask > sym->regs[1]->mask))
+    aop->regmask |= M6502MASK_REV;
+  aop->op = op;
+}
+
+/*-----------------------------------------------------------------*/
+/* freeAsmop - free up the asmop given to an operand               */
+/*----------------------------------------------------------------*/
+static void
+freeAsmop (operand * op, asmop * aaop, iCode * ic, bool pop)
+{
+  asmop *aop;
+
+  if (!op)
+    aop = aaop;
+  else
+    aop = op->aop;
+
+  if (!aop)
+    return;
+
+  if (aop->freed)
+    goto dealloc;
+
+  aop->freed = 1;
+
+  if (aop->stacked)
+    {
+      int stackAdjust;
+      int loffset;
+
+      emitComment (TRACE_AOP, "  freeAsmop restoring stacked %s", aopName (aop));
+      aop->stacked = 0;
+      stackAdjust = 0;
+      for (loffset = 0; loffset < aop->size; loffset++)
+        if (aop->stk_aop[loffset])
+          {
+            transferAopAop (aop->stk_aop[loffset], 0, aop, loffset);
+            stackAdjust++;
+          }
+      pullNull (stackAdjust);
+    }
+
+dealloc:
+  /* all other cases just dealloc */
+  if (op)
+    {
+      op->aop = NULL;
+      if (IS_SYMOP (op))
+        {
+          OP_SYMBOL (op)->aop = NULL;
+          /* if the symbol has a spill */
+          if (SPIL_LOC (op))
+            SPIL_LOC (op)->aop = NULL;
+        }
+    }
+}
+
+
+/*-----------------------------------------------------------------*/
+/* aopDerefAop - treating the aop parameter as a pointer, return   */
+/*               an asmop for the object it references             */
+/*-----------------------------------------------------------------*/
+static asmop *
+aopDerefAop (asmop * aop, int offset)
+{
+  int adr;
+  asmop *newaop = NULL;
+  sym_link *type, *etype;
+  int p_type;
+  struct dbuf_s dbuf;
+
+  emitComment (TRACE_AOP, "      aopDerefAop(%s)", aopName (aop));
+  if (aop->op)
+    {
+
+      type = operandType (aop->op);
+      etype = getSpec (type);
+      /* if op is of type of pointer then it is simple */
+      if (IS_PTR (type) && !IS_FUNC (type->next))
+        p_type = DCL_TYPE (type);
+      else
+        {
+          /* we have to go by the storage class */
+          p_type = PTR_TYPE (SPEC_OCLS (etype));
+        }
+    }
+  else
+    p_type = UPOINTER;
+
+  switch (aop->type)
+    {
+    case AOP_IMMD:
+      if (p_type == POINTER)
+        newaop = newAsmop (AOP_DIR);
+      else
+        newaop = newAsmop (AOP_EXT);
+      if (!offset)
+        newaop->aopu.aop_dir = aop->aopu.aop_immd.aop_immd1;
+      else
+        {
+          dbuf_init (&dbuf, 64);
+          dbuf_printf (&dbuf, "(%s+%d)", aop->aopu.aop_immd.aop_immd1, offset);
+          newaop->aopu.aop_dir = dbuf_detach_c_str (&dbuf);
+        }
+      break;
+    case AOP_LIT:
+      adr = (int) ulFromVal (aop->aopu.aop_lit);
+      if (p_type == POINTER)
+        adr &= 0xff;
+      adr = (adr + offset) & 0xffff;
+      dbuf_init (&dbuf, 64);
+
+      if (adr < 0x100)
+        {
+          newaop = newAsmop (AOP_DIR);
+          dbuf_printf (&dbuf, "0x%02x", adr);
+        }
+      else
+        {
+          newaop = newAsmop (AOP_EXT);
+          dbuf_printf (&dbuf, "0x%04x", adr);
+        }
+      newaop->aopu.aop_dir = dbuf_detach_c_str (&dbuf);
+      break;
+    default:
+      werror (E_INTERNAL_ERROR, __FILE__, __LINE__, "unsupported asmop");
+      return NULL;
+    }
+
+
+  return newaop;
+}
+
+
+/*-----------------------------------------------------------------*/
+/* aopOpExtToIdx - attempt to convert AOP_EXT to AOP_IDX           */
+/*-----------------------------------------------------------------*/
+static void
+aopOpExtToIdx(asmop * result, asmop *left, asmop *right)
+{
+  int accesses=0;
+  int resultAccesses=0;
+  int leftAccesses=0;
+  int rightAccesses=0;
+  asmop * winner;
+  int winnerAccesses;
+  
+  return; //TODO: makes things worse often
+
+  if (!m6502_reg_x->isFree || !m6502_reg_y->isFree)
+    return;
+
+  /* Need to replace at least two extended mode accesses with indexed */
+  /* to break even with the extra cost of loading HX. Do a quick check */
+  /* to see if anything is using extended mode at all. */
+  if (result && result->type == AOP_EXT)
+    accesses += result->size;
+  if (left && left->type == AOP_EXT)
+    accesses += left->size;
+  if (right && right->type == AOP_EXT)
+    accesses += right->size;
+  if (accesses<2)
+    return;
+  
+  /* If an operand is already using or going to H or X then we cannot */
+  /* use indexed addressing mode at the same time. */
+  if (result && (IS_AOP_WITH_Y (result) || IS_AOP_WITH_X (result)))
+    return;
+  if (left && (IS_AOP_WITH_Y (left) || IS_AOP_WITH_X (left)))
+    return;
+  if (right && (IS_AOP_WITH_Y (right) || IS_AOP_WITH_X (right)))
+    return;
+
+  /* Decide which is the best asmop to make indexed. */
+  if (result && result->type == AOP_EXT)
+    {
+      resultAccesses = result->size;
+      if (result->op && left && left->op && result->op->key == left->op->key)
+        resultAccesses += result->size;
+      if (result->op && right && right->op && result->op->key == right->op->key)
+        resultAccesses += result->size;
+    }
+  if (left && left->type == AOP_EXT)
+    {
+      leftAccesses = left->size;
+      if (left->op && right && right->op && left->op->key == right->op->key)
+        leftAccesses += left->size;
+    }
+  if (right && right->type == AOP_EXT)
+    {
+      rightAccesses = right->size;
+    }
+
+  winner = result; winnerAccesses = resultAccesses;
+  if (leftAccesses > winnerAccesses)
+    {
+      winnerAccesses = leftAccesses;
+      winner = left;
+    }
+  if (rightAccesses > winnerAccesses)
+    {
+      winnerAccesses = rightAccesses;
+      winner = right;
+    }
+
+  /* Make sure there were enough accesses of a single variable to be worthwhile. */ 
+  if (winnerAccesses < 2)
+    return;
+
+  if (winner->op && result && result->op && winner->op->key == result->op->key)
+    result->type = AOP_IDX;
+  if (winner->op && left && left->op && winner->op->key == left->op->key)
+    left->type = AOP_IDX;
+  if (winner->op && right && right->op && winner->op->key == right->op->key)
+    right->type = AOP_IDX;
+  loadRegFromImm (m6502_reg_yx, winner->aopu.aop_dir);
+}
+
+// is it safe to aopAdrStr?
+static bool
+isAddrSafe(operand* op, reg_info* reg)
+{
+  switch (AOP(op)->type) 
+  {
+    case AOP_IMMD:	// #nn
+    case AOP_LIT:
+    case AOP_DIR:	// aa
+    case AOP_EXT:	// aaaa
+      return true;
+    case AOP_SOF:       // (BASEPTR),y
+      if (reg == m6502_reg_a && (m6502_reg_x->isFree || m6502_reg_y->isFree))
+        return true;
+  }
+  
+  return false;
+}
+
+static int aopPrepareStoreTemp = 0;
+static int aopPreparePreserveFlags = 0;
+
+// TODO: make sure this is called before/after aopAdrStr if indexing might be used
+static void
+aopAdrPrepare (asmop * aop, int loffset)
+{
+  aopPreparePreserveFlags = 0;
+  if (loffset > (aop->size - 1))
+    return;
+
+  switch (aop->type)
+    {
+    case AOP_SOF:
+        // can we get stack pointer?
+        if (m6502_reg_x->isFree) {
+          doTSX();
+          aopPrepareStoreTemp=0;
+        } else {
+#if 0
+          // code for lda [BASEPTR],y 
+          aopPrepareStoreTemp = storeRegTemp(m6502_reg_y, false);
+	  // FIXME: offset is wrong
+          emitComment (TRACE_AOP, "ofs=%d base=%d tsx=%d push=%d stk=%d loffset=%d", _G.stackOfs, _G.baseStackPushes, _G.tsxStackPushes, _G.stackPushes, aop->aopu.aop_stk, loffset);
+          loadRegFromConst(m6502_reg_y, _G.stackOfs + _G.baseStackPushes + aop->aopu.aop_stk + loffset + 1);
+	  // ORIG: loadRegFromConst(m6502_reg_y, _G.stackOfs - _G.baseStackPushes + aop->aopu.aop_stk + loffset + 1);
+          m6502_reg_y->aop = &tsxaop;
+#else
+          // FIXME: check if used/dead is ok
+//	  aopPrepareStoreTemp = storeRegTempIfSurv(m6502_reg_x);
+          storeRegTemp(m6502_reg_x, true);
+          aopPrepareStoreTemp = true;
+//          m6502_reg_x->isFree=true;
+          doTSX();
+#endif
+          aopPreparePreserveFlags = 1; // TODO: also need to make sure flags are needed by caller
+      }
+    }
+}
+
+static void
+aopAdrUnprepare (asmop * aop, int loffset)
+{
+  if (loffset > (aop->size - 1))
+    return;
+
+  switch (aop->type)
+    {
+    case AOP_SOF:
+        if (aopPrepareStoreTemp) {
+          if (aopPreparePreserveFlags) {
+            emit6502op("php", ""); // TODO: sucks
+          }
+#if 0
+          loadRegTemp(m6502_reg_y);
+          m6502_dirtyReg(m6502_reg_y, false);
+#else
+	  loadRegTemp(m6502_reg_x);
+#endif
+	  if (aopPreparePreserveFlags) {
+	    emit6502op("plp", ""); // TODO: sucks
+          }
+	  aopPreparePreserveFlags = 0;
+	  aopPrepareStoreTemp = 0;
+        }
+      }
+    }
+
+/*-----------------------------------------------------------------*/
+/* aopAdrStr - for referencing the address of the aop              */
+/*-----------------------------------------------------------------*/
+/* loffset seems to have a weird meaning here. It seems to be nonzero in some places where one would expect an offset to be zero */
+static const char *
+aopAdrStr (asmop * aop, int loffset, bool bit16)
+{
+  char *s = buffer;
+  char *rs;
+  int offset = loffset; // SEH: aop->size - 1 - loffset - (bit16 ? 1 : 0);
+  int xofs;
+
+  /* offset is greater than
+     size then zero */
+  if (loffset > (aop->size - 1) && aop->type != AOP_LIT)
+    return "#0x00";
+  
+  /* depending on type */
+  switch (aop->type)
+    {
+    case AOP_DUMMY:
+      return "#0x00";
+
+    case AOP_IMMD:
+      if (loffset)
+        {
+          if (loffset > 1)
+            sprintf (s, "#(%s >> %d)", aop->aopu.aop_immd.aop_immd1, loffset * 8);
+          else
+            sprintf (s, "#>%s", aop->aopu.aop_immd.aop_immd1);
+        }
+      else
+        sprintf (s, "#%s", aop->aopu.aop_immd.aop_immd1);
+      rs = Safe_calloc (1, strlen (s) + 1);
+      strcpy (rs, s);
+      return rs;
+
+    case AOP_DIR:
+      if (regalloc_dry_run)
+        return "*dry";
+      if (offset)
+        sprintf (s, "*(%s + %d)", aop->aopu.aop_dir, offset);
+      else
+        sprintf (s, "*%s", aop->aopu.aop_dir);
+      rs = Safe_calloc (1, strlen (s) + 1);
+      strcpy (rs, s);
+      return rs;
+
+    case AOP_EXT:
+      if (regalloc_dry_run)
+        return "dry";
+      if (offset)
+        sprintf (s, "(%s + %d)", aop->aopu.aop_dir, offset);
+      else
+        sprintf (s, "%s", aop->aopu.aop_dir);
+      rs = Safe_calloc (1, strlen (s) + 1);
+      strcpy (rs, s);
+      return rs;
+
+    case AOP_REG:
+      return aop->aopu.aop_reg[loffset]->name;
+
+    case AOP_LIT:
+      if (bit16)
+        return aopLiteralLong (aop->aopu.aop_lit, loffset, 2);
+      else
+        return aopLiteral (aop->aopu.aop_lit, loffset);
+
+    case AOP_SOF: // TODO?
+      if (regalloc_dry_run) {
+        return "1,x"; // fake result, not needed
+      } else {
+        // did we get stack pointer in X?
+        if (m6502_reg_x->aop == &tsxaop) {
+          // hc08's tsx returns +1, ours returns +0
+          //DD( emitcode( "", "; %d + %d + %d + %d + 1", _G.stackOfs, _G.tsxStackPushes, aop->aopu.aop_stk, offset ));
+          xofs = STACK_TOP + _G.stackOfs + _G.tsxStackPushes + aop->aopu.aop_stk + offset + 1;
+          sprintf (s, "0x%x,x", xofs);
+          rs = Safe_calloc (1, strlen (s) + 1);
+          strcpy (rs, s);
+          return rs;
+        // did we get base ptr in Y?
+        } else {
+          // FIXME: should X be saved?
+          doTSX();
+          xofs = STACK_TOP + _G.stackOfs + _G.tsxStackPushes + aop->aopu.aop_stk + offset + 1;
+          sprintf (s, "0x%x,x", xofs);
+          rs = Safe_calloc (1, strlen (s) + 1);
+          strcpy (rs, s);
+          return rs;
+
+        } 
+#if 0
+else if (m6502_reg_y->aop == &tsxaop) {
+          return "[__BASEPTR],y";
+        } else {
+	  // FIXME: unimplemented
+//          loadRegFromConst(m6502_reg_x, offset);
+          return "ERROR [__BASEPTR],y"; // TODO: is base ptr or Y loaded?
+        }
+#endif
+      }
+    case AOP_IDX:
+      xofs = offset; /* For now, assume yx points to the base address of operand */
+      // TODO: slow
+      storeRegTemp (m6502_reg_yx, true);
+      if (m6502_reg_y->aop == &tsxaop) {
+        loadRegFromConst(m6502_reg_y, offset);
+        return "ERROR [__TEMP],y"; // TODO: what if != 0 tempOfs?
+      } else
+        return "ERROR"; // TODO: error
+    }
+
+  werror (E_INTERNAL_ERROR, __FILE__, __LINE__, "aopAdrStr got unsupported aop->type");
+  exit (1);
+}
+
+
+/*-----------------------------------------------------------------*/
+/* getDataSize - get the operand data size                         */
+/*-----------------------------------------------------------------*/
+static int
+getDataSize (operand *op)
+{
+  int size;
+  size = AOP_SIZE (op);
+  return size;
+}
+
+/*-----------------------------------------------------------------*/
+/* asmopToBool - Emit code to convert an asmop to a boolean.       */
+/*               Result left in A (0=false, 1=true) if ResultInA,  */
+/*               otherwise result left in Z flag (1=false, 0=true) */
+/*-----------------------------------------------------------------*/
+static void
+asmopToBool (asmop *aop, bool resultInA)
+{
+  bool isFloat; 
+  symbol *tlbl, *tlbl1;
+  int size = aop->size;
+  bool needpula = false;
+  bool flagsonly = true;
+  int offset = size - 1;
+  sym_link *type;
+
+  emitComment (TRACE_AOP, "asmopToBool resultinA %s", resultInA?"yes":"no");
+
+  wassert (aop);
+  type = operandType (AOP_OP (aop));
+  isFloat = IS_FLOAT (type);
+
+  if (resultInA)
+    m6502_freeReg (m6502_reg_a);
+
+  if (IS_BOOL (type))
+    {
+      // result -> A
+      if (resultInA)
+        {
+          loadRegFromAop (m6502_reg_a, aop, 0);
+        }
+      // result -> flags
+      else if (IS_AOP_A(aop))
+        {
+          emit6502op ("cmp", "#0x00");
+        }
+      else if (IS_AOP_X(aop))
+        {
+          emit6502op ("cpx", "#0x00");
+        }
+      else if (IS_AOP_Y(aop))
+        {
+          emit6502op ("cpy", "#0x00");
+        }
+      else  // TODO: more cases? use transfer reg?
+      {
+        // ldx or ldy? or lda?
+        reg_info* freereg = getDeadByteReg();
+        if (freereg) {
+          loadRegFromAop (freereg, aop, 0);
+        } else {
+          // no choice, all regs are full
+          storeRegTemp (m6502_reg_a, true);
+          loadRegFromAop (m6502_reg_a, aop, 0);
+          loadRegTempNoFlags (m6502_reg_a, true); // TODO?
+        }
+      }
+      return;
+    }
+
+  if (resultInA && size == 1)
+    {
+      loadRegFromAop (m6502_reg_a, aop, 0);
+      emit6502op ("cmp", "#0x01");
+      loadRegFromConst (m6502_reg_a, 0);
+      rmwWithReg ("rol", m6502_reg_a);
+      return;
+    }
+
+  switch (aop->type)
+    {
+    case AOP_REG:
+      if (IS_AOP_A (aop))
+        {
+          emit6502op ("cmp", "#0x00");
+          flagsonly = false; // because it's in A
+        }
+      else if (IS_AOP_X (aop))
+        {
+          emit6502op ("cpx", "#0x00");
+        }
+      else if (IS_AOP_Y (aop))
+        {
+          emit6502op ("cpy", "#0x00");
+        }
+      else if (IS_AOP_YX (aop))
+        {
+          symbol *tlbl = safeNewiTempLabel (NULL);
+          emit6502op ("cpy", "#0x00");
+          emit6502op ("bne", "%05d$", safeLabelKey2num (tlbl->key));
+          emit6502op ("cpx", "#0x00");
+          safeEmitLabel (tlbl);
+        }
+      else if (IS_AOP_XA (aop) || IS_AOP_AX (aop))
+        {
+          symbol *tlbl = safeNewiTempLabel (NULL);
+          emit6502op ("cmp", "#0x00");
+          emit6502op ("bne", "%05d$", safeLabelKey2num (tlbl->key));
+          emit6502op ("cpx", "#0x00");
+          safeEmitLabel (tlbl);
+        }
+      else
+        {
+          werror (E_INTERNAL_ERROR, __FILE__, __LINE__, "Bad rIdx in asmopToBool");
+          return;
+        }
+      break;
+    case AOP_DIR:
+    case AOP_EXT:
+        emitComment (TRACE_AOP|VVDBG, "asmopToBool - AOP_DIR || AOP_EXT");
+
+      if (!resultInA && (size == 1) && !IS_AOP_A (aop) && !m6502_reg_a->isFree && m6502_reg_x->isFree)
+        {
+          loadRegFromAop (m6502_reg_x, aop, 0);
+          break;
+        }
+      if (resultInA)
+        needpula = false;
+      else
+        needpula = storeRegTempIfSurv (m6502_reg_a);
+      loadRegFromAop (m6502_reg_a, aop, offset--);
+      if (isFloat)
+        {
+          emit6502op ("and", "#0x7F");      //clear sign bit
+        }
+      while (--size)
+        accopWithAop ("ora", aop, offset--);
+      if (needpula)
+        {
+          loadRegTempNoFlags (m6502_reg_a, true);
+        }
+      else
+        {
+          m6502_freeReg (m6502_reg_a);
+          flagsonly = false;
+        }
+      break;
+    case AOP_LIT:
+      /* Higher levels should optimize this case away but let's be safe */
+      if (ulFromVal (aop->aopu.aop_lit))
+        loadRegFromConst (m6502_reg_a, 1);
+      else
+        loadRegFromConst (m6502_reg_a, 0);
+      m6502_freeReg (m6502_reg_a);
+      break;
+    default:
+      if (size == 1)
+        {
+          if (resultInA)
+            {
+              loadRegFromAop (m6502_reg_a, aop, 0);
+              m6502_freeReg (m6502_reg_a);
+              flagsonly = false;
+            }
+          else
+            {
+              bool needloada;
+              emitComment (TRACE_AOP|VVDBG, "asmopToBool - loadreg");
+              needloada = storeRegTempIfUsed (m6502_reg_a);
+              loadRegFromAop (m6502_reg_a, aop, 0);
+              loadRegTempNoFlags(m6502_reg_a,needloada);
+            }
+          break;
+        }
+      else if (size == 2)
+        {
+          if (m6502_reg_a->isFree)
+            {
+              loadRegFromAop (m6502_reg_a, aop, 0);
+              accopWithAop ("ora", aop, 1);
+              m6502_freeReg (m6502_reg_a);
+              flagsonly = false;
+            }
+          else
+            {
+#if 0
+              // FIXME: unimplemented
+              tlbl = safeNewiTempLabel (NULL);
+              emitcode ("bit3", "%s", aopAdrStr (aop, 0, false));
+              emitcode ("bne", "%05d$", safeLabelKey2num (tlbl->key));
+              emitcode ("bit4", "%s", aopAdrStr (aop, 1, false));
+              safeEmitLabel (tlbl);
+#endif
+              emitComment(TRACE_AOP|VVDBG, "  asmopToBool default case");
+              bool needloada = storeRegTempIfUsed (m6502_reg_a);
+              bool needloadx = storeRegTempIfUsed (m6502_reg_x);
+              m6502_freeReg(m6502_reg_x);
+              emit6502op ("lda", aopAdrStr (aop, 0, false));
+              emit6502op ("ora", aopAdrStr (aop, 1, false));
+              emit6502op ("php", "" );
+              loadOrFreeRegTemp (m6502_reg_x, needloadx);
+              loadOrFreeRegTemp (m6502_reg_a, needloada);
+              emit6502op ("plp", "" );
+
+              break;
+            }
+        }
+      else
+        {
+          needpula = storeRegTempIfSurv (m6502_reg_a);
+          loadRegFromAop (m6502_reg_a, aop, offset--);
+          if (isFloat)
+            {
+              emit6502op ("and", "#0x7F");
+            }
+          while (--size)
+            accopWithAop ("ora", aop, offset--);
+          if (needpula)
+            loadRegTempNoFlags (m6502_reg_a, true);
+          else
+            {
+              m6502_freeReg (m6502_reg_a);
+              flagsonly = false;
+            }
+          // TODO: can we assume a=0?
+        }
+    }
+
+  if (resultInA)
+    {
+      tlbl = safeNewiTempLabel (NULL);
+
+      if (flagsonly)
+        {
+          tlbl1 = safeNewiTempLabel (NULL);
+          emitBranch ("bne", tlbl1);
+          loadRegFromConst (m6502_reg_a, 0);
+          emitBranch ("bra", tlbl);
+          safeEmitLabel (tlbl1);
+          m6502_dirtyReg (m6502_reg_a);
+          loadRegFromConst (m6502_reg_a, 1);
+        }
+      else
+        {
+          emitBranch ("beq", tlbl);
+          loadRegFromConst (m6502_reg_a, 1);
+        }
+      safeEmitLabel (tlbl);
+      m6502_dirtyReg (m6502_reg_a);
+      m6502_useReg (m6502_reg_a);
+    }
+}
+
+/*-----------------------------------------------------------------*/
+/* genCopy - Copy the value from one operand to another            */
+/*           The caller is responsible for aopOp and freeAsmop     */
+/*-----------------------------------------------------------------*/
+static void
+genCopy (operand * result, operand * source)
+{
+  int size = AOP_SIZE (result);
+  int srcsize = AOP_SIZE (source);
+  int offset = 0;
+
+  emitComment (TRACEGEN, __func__);
+  emitComment (TRACEGEN|VVDBG, "      genCopy - size %d -> %d", srcsize, size);
+  emitComment (TRACEGEN|VVDBG, "      genCopy - regmask %02x -> %02x", 
+               AOP(source)->regmask, AOP(result)->regmask );
+
+  /* if they are the same and not volatile */
+  if (operandsEqu (result, source) && !isOperandVolatile (result, false) &&
+      !isOperandVolatile (source, false))
+    return;
+
+  /* The source and destinations may be different size due to optimizations. */
+  /* This is not a cast, so there is no need to worry about sign extension. */
+  /* When this happens, it is usually just 1 byte source to 2 byte dest, so */
+  /* nothing significant to optimize. */
+  if (srcsize < size)
+    {
+      size -= srcsize;
+      while (srcsize)
+        {
+          transferAopAop (AOP (source), offset, AOP (result), offset);
+          offset++;
+          srcsize--;
+        }
+      while (size)
+        {
+          storeConstToAop (0, AOP (result), offset);
+          offset++;
+          size--;
+        }
+
+      return;
+    }
+
+  /* if they are the same registers */
+  if (sameRegs (AOP (source), AOP (result)))
+    return;
+
+  /* either source or result is two-byte register pair */
+  if (IS_AOP_YX (AOP (result)) && srcsize == 2)
+    {
+      loadRegFromAop (m6502_reg_yx, AOP (source), 0);
+      return;
+    }
+  if (IS_AOP_YX (AOP (source)) && size == 2)
+    {
+      storeRegToAop (m6502_reg_yx, AOP (result), 0);
+      return;
+    }
+  if (IS_AOP_XA (AOP (result)) && srcsize == 2)
+    {
+      loadRegFromAop (m6502_reg_xa, AOP (source), 0);
+      return;
+    }
+  if (IS_AOP_XA (AOP (source)) && size == 2)
+    {
+      storeRegToAop (m6502_reg_xa, AOP (result), 0);
+      return;
+    }
+
+  // TODO?
+  //  if (IS_MOS6502 && (size > 2))
+  //    aopOpExtToIdx (AOP (result), NULL, AOP (source));
+
+  /* general case */
+  // TODO: sucks for copying registers
+  emitComment (TRACEGEN|VVDBG, "      genCopy (general case)", "");
+  for (offset=0; offsetaopu.aop_reg[0] == AOP (IC_LEFT (ic))->aopu.aop_reg[0] &&
+    (size < 2 || AOP (IC_RESULT (ic))->aopu.aop_reg[1] == AOP (IC_LEFT (ic))->aopu.aop_reg[1]))
+    {
+      while (size--)
+        rmwWithReg ("com", AOP (IC_RESULT (ic))->aopu.aop_reg[offset++]);
+      goto release;
+    }
+
+  if (AOP_TYPE (IC_RESULT (ic)) == AOP_REG && AOP_TYPE (IC_LEFT (ic)) == AOP_REG)
+    {
+      while (size--)
+        {
+          if ((reg = AOP (IC_RESULT (ic))->aopu.aop_reg[offset]) != m6502_reg_y)
+            {
+              transferAopAop (AOP (IC_LEFT (ic)), offset, AOP (IC_RESULT (ic)), offset);
+              rmwWithReg ("com", reg);
+            }
+          else
+            {
+              if ((reg = AOP (IC_LEFT (ic))->aopu.aop_reg[offset]) == m6502_reg_y)
+                reg = m6502_reg_a->isDead ? m6502_reg_a : m6502_reg_x;
+              needpullreg = pushRegIfSurv (reg);
+              loadRegFromAop (reg, AOP (IC_LEFT (ic)), offset);
+              rmwWithReg ("com", reg);
+              storeRegToAop (reg, AOP (IC_RESULT (ic)), offset);
+              if (needpullreg)
+                pullReg (reg);
+            }
+          offset++;
+        }
+      goto release;
+    }
+
+  reg = (m6502_reg_a->isDead && !(AOP_TYPE (IC_RESULT (ic)) == AOP_REG && AOP (IC_RESULT (ic))->aopu.aop_reg[0] == m6502_reg_a) ? m6502_reg_a : m6502_reg_x);
+
+  needpullreg = pushRegIfSurv (reg);
+  while (size--)
+    {
+      bool needpullreg2 = (!size && AOP_TYPE (IC_RESULT (ic)) == AOP_REG && AOP (IC_RESULT (ic))->aopu.aop_reg[0] == reg || size && AOP_TYPE (IC_RESULT (ic)) == AOP_REG && AOP (IC_RESULT (ic))->aopu.aop_reg[1] == reg);
+      if (needpullreg2)
+        pushReg (reg, true);
+      loadRegFromAop (reg, AOP (IC_LEFT (ic)), offset);
+      rmwWithReg ("com", reg);
+      m6502_useReg (reg);
+      storeRegToAop (reg, AOP (IC_RESULT (ic)), offset);
+      m6502_freeReg (reg);
+      if (needpullreg2)
+        pullReg (reg);
+      offset++;
+    }
+  pullOrFreeReg (reg, needpullreg);
+
+  /* release the aops */
+release:
+  freeAsmop (IC_RESULT (ic), NULL, ic, true);
+  freeAsmop (IC_LEFT (ic), NULL, ic, true);
+}
+
+/*-----------------------------------------------------------------*/
+/* genUminusFloat - unary minus for floating points                */
+/*-----------------------------------------------------------------*/
+static void
+genUminusFloat (operand * op, operand * result)
+{
+  int size, offset = 0;
+  bool needpula;
+
+  emitComment (TRACEGEN, __func__);
+
+  /* for this we just copy and then flip the bit */
+
+  size = AOP_SIZE (op) - 1;
+
+  while (size--)
+    {
+      transferAopAop (AOP (op), offset, AOP (result), offset);
+      offset++;
+    }
+
+  needpula = pushRegIfSurv (m6502_reg_a);
+  loadRegFromAop (m6502_reg_a, AOP (op), offset);
+  emit6502op ("eor", "#0x80");
+  m6502_useReg (m6502_reg_a);
+  storeRegToAop (m6502_reg_a, AOP (result), offset);
+  pullOrFreeReg (m6502_reg_a, needpula);
+}
+
+/*-----------------------------------------------------------------*/
+/* genUminus - unary minus code generation                         */
+/*-----------------------------------------------------------------*/
+static void
+genUminus (iCode * ic)
+{
+  int offset, size;
+  sym_link *optype;
+  bool carry = true;
+  bool needpula;
+  asmop *result;
+
+  emitComment (TRACEGEN, __func__);
+
+  /* assign asmops */
+  aopOp (IC_LEFT (ic), ic, false);
+  aopOp (IC_RESULT (ic), ic, true);
+
+  optype = operandType (IC_LEFT (ic));
+
+  /* if float then do float stuff */
+  if (IS_FLOAT (optype))
+    {
+      genUminusFloat (IC_LEFT (ic), IC_RESULT (ic));
+      goto release;
+    }
+
+  /* otherwise subtract from zero */
+  size = AOP_SIZE (IC_LEFT (ic));
+  offset = 0;
+
+  if (size == 1)
+    {
+      needpula = pushRegIfSurv (m6502_reg_a);
+      loadRegFromAop (m6502_reg_a, AOP (IC_LEFT (ic)), 0);
+      rmwWithReg ("neg", m6502_reg_a);
+      m6502_freeReg (m6502_reg_a);
+      storeRegToFullAop (m6502_reg_a, AOP (IC_RESULT (ic)), SPEC_USIGN (operandType (IC_LEFT (ic))));
+      pullOrFreeReg (m6502_reg_a, needpula);
+      goto release;
+    }
+
+  /* If either left or result are in registers, handle this carefully to     */
+  /* avoid prematurely overwriting register values. The 1 byte case was      */
+  /* handled above and there aren't enough registers to handle 4 byte values */
+  /* so this case only needs to deal with 2 byte values. */
+  if (AOP_TYPE (IC_RESULT (ic)) == AOP_REG || AOP_TYPE (IC_LEFT (ic)) == AOP_REG)
+    {
+      reg_info *result0 = NULL;
+      reg_info *left0 = NULL;
+      reg_info *left1 = NULL;
+      if (AOP_TYPE (IC_LEFT (ic)) == AOP_REG)
+        {
+          left0 = AOP (IC_LEFT (ic))->aopu.aop_reg[0];
+          left1 = AOP (IC_LEFT (ic))->aopu.aop_reg[1];
+        }
+      if (AOP_TYPE (IC_RESULT (ic)) == AOP_REG)
+        {
+          result0 = AOP (IC_RESULT (ic))->aopu.aop_reg[0];
+        }
+      needpula = pushRegIfSurv (m6502_reg_a);
+      if (left1 == m6502_reg_a)
+        pushReg (left1, true);
+
+      if (left0 == m6502_reg_a) // TODO?
+        rmwWithReg ("neg", m6502_reg_a);
+      else
+        {
+          loadRegFromConst (m6502_reg_a, 0);
+          emit6502op("sec", "");
+          accopWithAop ("sbc", AOP (IC_LEFT (ic)), 0);
+        }
+      if (result0 == m6502_reg_a || (result0 && result0 == left1))
+        pushReg (m6502_reg_a, true);
+      else
+        storeRegToAop (m6502_reg_a, AOP (IC_RESULT (ic)), 0);
+      loadRegFromConst (m6502_reg_a, 0);
+      if (left1 == m6502_reg_a)
+        {
+	  // FIXME: unimplemented
+          emitcode ("sbc1","%d,s", (result0 == m6502_reg_a || (result0 && result0 == left1)) ? 2 : 1);
+          m6502_dirtyReg (m6502_reg_a);
+        }
+      else
+        {
+          accopWithAop ("sbc", AOP (IC_LEFT (ic)), 1);
+        }
+      storeRegToAop (m6502_reg_a, AOP (IC_RESULT (ic)), 1);
+      if (result0 == m6502_reg_a || (result0 && result0 == left1))
+        pullReg (result0);
+      if (left1 == m6502_reg_a)
+        pullNull (1);
+      pullOrFreeReg (m6502_reg_a, needpula);
+      goto release;
+    }
+
+  result = AOP (IC_RESULT (ic));
+
+  needpula = pushRegIfSurv (m6502_reg_a);
+  while (size--)
+    {
+      loadRegFromConst (m6502_reg_a, 0);
+      if (carry) {
+        emit6502op("sec", "");
+      }
+      accopWithAop ("sbc", AOP (IC_LEFT (ic)), offset);
+      storeRegToAop (m6502_reg_a, result, offset++);
+      carry = false;
+    }
+  storeRegSignToUpperAop (m6502_reg_a, result, offset, SPEC_USIGN (operandType (IC_LEFT (ic))));
+  pullOrFreeReg (m6502_reg_a, needpula);
+
+release:
+  /* release the aops */
+  freeAsmop (IC_RESULT (ic), NULL, ic, true);
+  freeAsmop (IC_LEFT (ic), NULL, ic, false);
+}
+
+/*-----------------------------------------------------------------*/
+/* saveRegisters - will look for a call and save the registers     */
+/*-----------------------------------------------------------------*/
+static void
+saveRegisters (iCode *lic)
+{
+  int i;
+  iCode *ic;
+
+  /* look for call */
+  for (ic = lic; ic; ic = ic->next)
+    if (ic->op == CALL || ic->op == PCALL)
+      break;
+
+  if (!ic)
+    {
+      fprintf (stderr, "found parameter push with no function call\n");
+      return;
+    }
+
+  /* if the registers have been saved already or don't need to be then
+     do nothing */
+  if (ic->regsSaved)
+    return;
+  if (IS_SYMOP (IC_LEFT (ic)) &&
+      (IFFUNC_CALLEESAVES (OP_SYMBOL (IC_LEFT (ic))->type) || IFFUNC_ISNAKED (OP_SYM_TYPE (IC_LEFT (ic)))))
+    return;
+
+  if (!regalloc_dry_run)
+    ic->regsSaved = 1;
+
+  emitComment (REGOPS, "  saveRegisters");
+  
+  // make sure not to clobber A
+  // TODO: why does isUsed not set?
+  // TODO: only clobbered if m6502_reg_a->isFree
+  // TODO: 65C02
+  bool clobbers_a = !IS_MOS65C02 
+    && (bitVectBitValue(ic->rSurv, X_IDX) || bitVectBitValue(ic->rSurv, Y_IDX))
+    && !bitVectBitValue(ic->rSurv, A_IDX);
+  if (clobbers_a)
+    storeRegTemp (m6502_reg_a, true);
+  for (i = A_IDX; i <= Y_IDX; i++)
+    {
+      if (bitVectBitValue (ic->rSurv, i))
+        pushReg (m6502_regWithIdx (i), false);
+    }
+  if (clobbers_a)
+    loadRegTemp (m6502_reg_a);
+}
+
+/*-----------------------------------------------------------------*/
+/* unsaveRegisters - pop the pushed registers                      */
+/*-----------------------------------------------------------------*/
+static void
+unsaveRegisters (iCode *ic)
+{
+  int i;
+
+  emitComment (REGOPS, "; unsaveRegisters");
+
+  // TODO: only clobbered if m6502_reg_a->isFree
+  // TODO: 65C02
+  bool clobbers_a = !IS_MOS65C02 
+    && (bitVectBitValue(ic->rSurv, X_IDX) || bitVectBitValue(ic->rSurv, Y_IDX))
+    && !bitVectBitValue(ic->rSurv, A_IDX);
+  if (clobbers_a)
+    storeRegTemp (m6502_reg_a, true);
+  for (i = Y_IDX; i >= A_IDX; i--)
+    {
+      if (bitVectBitValue (ic->rSurv, i))
+        pullReg (m6502_regWithIdx (i));
+    }
+  if (clobbers_a)
+    loadRegTemp (m6502_reg_a);
+}
+
+/*-----------------------------------------------------------------*/
+/* pushSide -                                                      */
+/*-----------------------------------------------------------------*/
+static void
+pushSide (operand *oper, int size, iCode *ic)
+{
+  int offset = 0;
+//  bool xIsFree = m6502_reg_x->isFree;
+
+  aopOp (oper, ic, false);
+
+  if (AOP_TYPE (oper) == AOP_REG)
+    {
+      /* The operand is in registers; we can push them directly */
+      storeRegTemp(AOP (oper)->aopu.aop_reg[0], true);      
+      storeRegTemp(AOP (oper)->aopu.aop_reg[1], true); 
+    }
+  else
+    {
+      // push A if not free
+      // TODO: consider other regs for 65C02
+      bool needloada = pushRegIfUsed(m6502_reg_a);
+      bool needloadx = false;
+      if(AOP_TYPE(oper)==AOP_SOF) needloadx=pushRegIfUsed(m6502_reg_x);
+      /* A is free, so piecewise load operand into a and push A */
+      for (offset=0; offset 1 && AOP (oper)->aopu.aop_reg[0]->rIdx == X_IDX)
+        {
+          storeRegTemp (m6502_reg_a, true);
+          delayed_x = true;
+        }
+      else
+        transferAopAop (m6502_aop_pass[offset], 0, AOP (oper), offset);
+      if (m6502_aop_pass[offset]->type == AOP_REG)
+        m6502_freeReg (m6502_aop_pass[offset]->aopu.aop_reg[0]);
+      offset++;
+    }
+  if (delayed_x)
+    loadRegTemp (m6502_reg_x);
+}
+
+
+
+/*-----------------------------------------------------------------*/
+/* genIpush - generate code for pushing this gets a little complex */
+/*-----------------------------------------------------------------*/
+static void
+genIpush (iCode * ic)
+{
+  int size, offset = 0;
+
+  emitComment (TRACEGEN, __func__);
+
+  /* if this is not a parm push : ie. it is spill push
+     and spill push is always done on the local stack */
+  if (!ic->parmPush)
+    {
+      /* and the item is spilt then do nothing */
+      if (OP_SYMBOL (IC_LEFT (ic))->isspilt)
+        return;
+
+      aopOp (IC_LEFT (ic), ic, false);
+      size = AOP_SIZE (IC_LEFT (ic));
+      /* push it on the stack */
+      for (offset=size-1; offset>=0; offset--)
+        {
+          loadRegFromAop (m6502_reg_a, AOP (IC_LEFT (ic)), offset);
+          pushReg (m6502_reg_a, true);
+        }
+      return;
+    }
+
+  /* this is a parameter push: in this case we call
+     the routine to find the call and save those
+     registers that need to be saved */
+  if (!regalloc_dry_run) /* Cost for saving registers is counted at CALL or PCALL */
+    saveRegisters (ic);
+
+  /* then do the push */
+  aopOp (IC_LEFT (ic), ic, false);
+
+  // pushSide(IC_LEFT(ic), AOP_SIZE(IC_LEFT(ic)));
+  size = AOP_SIZE (IC_LEFT (ic));
+
+//  l = aopGet (AOP (IC_LEFT (ic)), 0, false, true);
+  if (AOP_TYPE (IC_LEFT (ic)) == AOP_IMMD || AOP_TYPE (IC_LEFT (ic)) == AOP_LIT ||IS_AOP_YX (AOP (IC_LEFT (ic))))
+    {
+      if ((size == 2) && m6502_reg_yx->isDead || IS_AOP_YX (AOP (IC_LEFT (ic))))
+        {
+          loadRegFromAop (m6502_reg_yx, AOP (IC_LEFT (ic)), 0);
+          pushReg (m6502_reg_yx, true);
+          goto release;
+        }
+    }
+
+  if (AOP_TYPE (IC_LEFT (ic)) == AOP_REG)
+    {
+      for (offset=size-1; offset>=0; offset--)
+        pushReg (AOP (IC_LEFT (ic))->aopu.aop_reg[offset], true);
+      goto release;
+    }
+
+  for (offset=size-1; offset>=0; offset--)
+    {
+//      printf("loading %d\n", offset);
+      loadRegFromAop (m6502_reg_a, AOP (IC_LEFT (ic)), offset);
+//      printf("pushing \n");
+      pushReg (m6502_reg_a, true);
+    }
+
+release:
+  freeAsmop (IC_LEFT (ic), NULL, ic, true);
+}
+
+/*-----------------------------------------------------------------*/
+/* genIpop - recover the registers: can happen only for spilling   */
+/*-----------------------------------------------------------------*/
+static void
+genIpop (iCode * ic)
+{
+  int size, offset;
+
+  emitComment (TRACEGEN, __func__);
+
+  /* if the temp was not pushed then */
+  if (OP_SYMBOL (IC_LEFT (ic))->isspilt)
+    return;
+
+  aopOp (IC_LEFT (ic), ic, false);
+  size = AOP_SIZE (IC_LEFT (ic));
+  offset = size - 1;
+  while (size--)
+    {
+      pullReg (m6502_reg_a);
+      storeRegToAop (m6502_reg_a, AOP (IC_LEFT (ic)), offset--);
+    }
+
+  freeAsmop (IC_LEFT (ic), NULL, ic, true);
+}
+
+/*-----------------------------------------------------------------*/
+/* genSend - gen code for SEND                                     */
+/*-----------------------------------------------------------------*/
+static void
+genSend (set *sendSet)
+{
+  iCode *send1;
+  iCode *send2;
+
+  emitComment (TRACEGEN, __func__);
+
+  /* case 1: single parameter in A
+   * case 2: single parameter in XA
+   * case 3: first parameter in A, second parameter in X
+   */
+  send1 = setFirstItem (sendSet);
+  send2 = setNextItem (sendSet);
+
+  if (!send2)
+    {
+      int size;
+      /* case 1 or 2, this is fairly easy */
+      aopOp (IC_LEFT (send1), send1, false);
+      size = AOP_SIZE (IC_LEFT (send1));
+      wassert (size <= 2);
+      if (size == 1)
+        {
+          loadRegFromAop (send1->argreg == 2 ? m6502_reg_x : m6502_reg_a, AOP (IC_LEFT (send1)), 0);
+        }
+      else if (AOP (IC_LEFT (send1))->type == AOP_REG)
+        loadRegFromAop (m6502_reg_xa, AOP (IC_LEFT (send1)), 0);
+      else if (isOperandVolatile (IC_LEFT (send1), false))
+        {
+          /* use lsb to msb order for volatile operands */
+          loadRegFromAop (m6502_reg_a, AOP (IC_LEFT (send1)), 0);
+          loadRegFromAop (m6502_reg_x, AOP (IC_LEFT (send1)), 1);
+        }
+      else
+        {
+          /* otherwise perfer to load a last */
+          loadRegFromAop (m6502_reg_x, AOP (IC_LEFT (send1)), 1);
+          loadRegFromAop (m6502_reg_a, AOP (IC_LEFT (send1)), 0);
+
+        }
+      freeAsmop (IC_LEFT (send1), NULL, send1, true);
+    }
+  else
+    {
+      /* case 3 */
+      /* make sure send1 is the first argument and swap with send2 if not */
+      if (send1->argreg > send2->argreg)
+        {
+          iCode * sic = send1;
+          send1 = send2;
+          send2 = sic;
+        }
+      aopOp (IC_LEFT (send1), send1, false);
+      aopOp (IC_LEFT (send2), send2, false);
+      if (IS_AOP_X (AOP (IC_LEFT (send1))) && IS_AOP_A (AOP (IC_LEFT (send2))))
+        {
+          /* If the parameters' register assignment is exactly backwards */
+          /* from what is needed, then swap the registers. */
+          swapXA();
+        }
+      else if (IS_AOP_A (AOP (IC_LEFT (send2))))
+        {
+          loadRegFromAop (m6502_reg_x, AOP (IC_LEFT (send2)), 0);
+          loadRegFromAop (m6502_reg_a, AOP (IC_LEFT (send1)), 0);
+        }
+      else
+        {
+          loadRegFromAop (m6502_reg_a, AOP (IC_LEFT (send1)), 0);
+          loadRegFromAop (m6502_reg_x, AOP (IC_LEFT (send2)), 0);
+        }
+      freeAsmop (IC_LEFT (send2), NULL, send2, true);
+      freeAsmop (IC_LEFT (send1), NULL, send1, true);
+    }
+}
+
+/*-----------------------------------------------------------------*/
+/* genCall - generates a call statement                            */
+/*-----------------------------------------------------------------*/
+static void
+genCall (iCode * ic)
+{
+  sym_link *dtype;
+  sym_link *etype;
+//  bool restoreBank = false;
+//  bool swapBanks = false;
+
+  emitComment (TRACEGEN, __func__);
+
+  /* if caller saves & we have not saved then */
+  if (!ic->regsSaved)
+    saveRegisters (ic);
+
+  dtype = operandType (IC_LEFT (ic));
+  etype = getSpec (dtype);
+  /* if send set is not empty then assign */
+  if (_G.sendSet && !regalloc_dry_run)
+    {
+      if (IFFUNC_ISREENT (dtype))       /* need to reverse the send set */
+        {
+	  //genSend (_G.sendSet);
+          genSend (reverseSet (_G.sendSet));
+        }
+      else
+        {
+          genSend (_G.sendSet);
+        }
+      _G.sendSet = NULL;
+    }
+
+  /* make the call */
+  if (IS_LITERAL (etype))
+    {
+      emit6502op ("jsr", "0x%04X", ulFromVal (OP_VALUE (IC_LEFT (ic))));
+    }
+  else
+    {
+      bool jump = (!ic->parmBytes && IFFUNC_ISNORETURN (OP_SYMBOL (IC_LEFT (ic))->type));
+
+      emit6502op (jump ? "jmp" : "jsr", "%s", (OP_SYMBOL (IC_LEFT (ic))->rname[0] ?
+                              OP_SYMBOL (IC_LEFT (ic))->rname : OP_SYMBOL (IC_LEFT (ic))->name));
+    }
+
+  m6502_dirtyReg (m6502_reg_a);
+  m6502_dirtyReg (m6502_reg_x);
+  m6502_dirtyReg (m6502_reg_y);
+
+  /* do we need to recompute the base ptr? */
+  if (_G.funcHasBasePtr) {
+    saveBasePtr();
+  }
+  
+  /* if we need assign a result value */
+  if ((IS_ITEMP (IC_RESULT (ic)) &&
+       (OP_SYMBOL (IC_RESULT (ic))->nRegs || OP_SYMBOL (IC_RESULT (ic))->spildir)) || IS_TRUE_SYMOP (IC_RESULT (ic)))
+    {
+      m6502_useReg (m6502_reg_a);
+      if (operandSize (IC_RESULT (ic)) > 1)
+        m6502_useReg (m6502_reg_x);
+      aopOp (IC_RESULT (ic), ic, false);
+
+      assignResultValue (IC_RESULT (ic));
+
+      freeAsmop (IC_RESULT (ic), NULL, ic, true);
+    }
+
+  /* adjust the stack for parameters if required */
+  if (ic->parmBytes)
+    {
+      pullNull (ic->parmBytes);
+    }
+
+  /* if we had saved some registers then unsave them */
+  if (ic->regsSaved && !IFFUNC_CALLEESAVES (dtype))
+    unsaveRegisters (ic);
+}
+
+/*-----------------------------------------------------------------*/
+/* genPcall - generates a call by pointer statement                */
+/*-----------------------------------------------------------------*/
+static void
+genPcall (iCode * ic)
+{
+  sym_link *dtype;
+  sym_link *etype;
+  iCode * sendic;
+
+  emitComment (TRACEGEN, __func__);
+
+  dtype = operandType (IC_LEFT (ic))->next;
+  etype = getSpec (dtype);
+  /* if caller saves & we have not saved then */
+  if (!ic->regsSaved)
+    saveRegisters (ic);
+
+  /* Go through the send set and mark any registers used by iTemps as */
+  /* in use so we don't clobber them while setting up the return address */
+  for (sendic = setFirstItem (_G.sendSet); sendic; sendic = setNextItem (_G.sendSet))
+    {
+      updateiTempRegisterUse (IC_LEFT (sendic));
+    }
+
+  // TODO: handle DIR/EXT with jmp [aa] or jmp [aaaa]
+  
+  if (!IS_LITERAL (etype))
+    {
+      updateCFA ();
+      /* compute the function address */
+      pushSide (IC_LEFT (ic), FARPTRSIZE, ic); // -1 is baked into initialization
+    }
+
+  /* if send set is not empty then assign */
+  if (_G.sendSet && !regalloc_dry_run)
+    {
+      genSend (reverseSet (_G.sendSet));
+      _G.sendSet = NULL;
+    }
+
+  /* make the call */
+  if (!IS_LITERAL (etype))
+    {
+#if 0
+      emit6502op("jsr","__sdcc_indirect_jsr");
+#else
+      symbol *rlbl = safeNewiTempLabel (NULL);
+      symbol *tlbl = safeNewiTempLabel (NULL);
+
+      emitBranch ("jsr", tlbl);
+      emitBranch ("bra", rlbl);
+      safeEmitLabel (tlbl);
+      emit6502op("jmp", "[__TEMP]");
+      safeEmitLabel (rlbl);
+#endif
+      _G.tempOfs -= 2;
+      updateCFA ();
+    }
+  else
+    {
+      emit6502op ("jsr", "0x%04X", ulFromVal (OP_VALUE (IC_LEFT (ic))));
+    }
+
+  m6502_dirtyReg (m6502_reg_a);
+  m6502_dirtyReg (m6502_reg_x);
+  m6502_dirtyReg (m6502_reg_y);
+
+  /* do we need to recompute the base ptr? */
+  if (_G.funcHasBasePtr) {
+    saveBasePtr();
+  }
+
+  /* if we need assign a result value */
+  if ((IS_ITEMP (IC_RESULT (ic)) &&
+       (OP_SYMBOL (IC_RESULT (ic))->nRegs || OP_SYMBOL (IC_RESULT (ic))->spildir)) || IS_TRUE_SYMOP (IC_RESULT (ic)))
+    {
+      m6502_useReg (m6502_reg_a);
+      if (operandSize (IC_RESULT (ic)) > 1)
+        m6502_useReg (m6502_reg_x);
+      aopOp (IC_RESULT (ic), ic, false);
+
+      assignResultValue (IC_RESULT (ic));
+
+      freeAsmop (IC_RESULT (ic), NULL, ic, true);
+    }
+
+  /* adjust the stack for parameters if required */
+  if (ic->parmBytes)
+    {
+      pullNull (ic->parmBytes);
+    }
+
+  /* if we had saved some registers then unsave them */
+  if (ic->regsSaved && !IFFUNC_CALLEESAVES (dtype))
+    unsaveRegisters (ic);
+}
+
+/*-----------------------------------------------------------------*/
+/* resultRemat - result  is rematerializable                       */
+/*-----------------------------------------------------------------*/
+static int
+resultRemat (iCode * ic)
+{
+  if (SKIP_IC (ic) || ic->op == IFX)
+    return 0;
+
+  if (IC_RESULT (ic) && IS_ITEMP (IC_RESULT (ic)))
+    {
+      symbol *sym = OP_SYMBOL (IC_RESULT (ic));
+      if (sym->remat && !POINTER_SET (ic))
+        return 1;
+    }
+
+  return 0;
+}
+
+/*-----------------------------------------------------------------*/
+/* inExcludeList - return 1 if the string is in exclude Reg list   */
+/*-----------------------------------------------------------------*/
+static int
+regsCmp (void *p1, void *p2)
+{
+  return (STRCASECMP ((char *) p1, (char *) (p2)) == 0);
+}
+
+static bool
+inExcludeList (char *s)
+{
+  const char *p = setFirstItem (options.excludeRegsSet);
+
+  if (p == NULL || STRCASECMP (p, "none") == 0)
+    return false;
+
+
+  return isinSetWith (options.excludeRegsSet, s, regsCmp);
+}
+
+/*-----------------------------------------------------------------*/
+/* genFunction - generated code for function entry                 */
+/*-----------------------------------------------------------------*/
+static void
+genFunction (iCode * ic)
+{
+  symbol *sym = OP_SYMBOL (IC_LEFT (ic));
+  sym_link *ftype;
+  iCode *ric = (ic->next && ic->next->op == RECEIVE) ? ic->next : NULL;
+  int stackAdjust = sym->stack;
+  //  int accIsFree = sym->recvSize == 0;
+
+  /* create the function header */
+  emitComment (ALWAYS, "-----------------------------------------");
+  emitComment (ALWAYS, " function %s", sym->name);
+  emitComment (ALWAYS, "-----------------------------------------");
+  emitComment (ALWAYS, m6502_assignment_optimal ? "Register assignment is optimal." : "Register assignment might be sub-optimal.");
+  emitComment (ALWAYS, "Stack space usage: %d bytes.", sym->stack);
+
+  emitcode ("", "%s:", sym->rname);
+  genLine.lineCurr->isLabel = 1;
+  ftype = operandType (IC_LEFT (ic));
+
+  _G.stackOfs = 0;
+  _G.stackPushes = 0;
+  if (options.debug && !regalloc_dry_run)
+    debugFile->writeFrameAddress (NULL, m6502_reg_sp, 0);
+
+  if (IFFUNC_ISNAKED (ftype))
+    {
+      emitComment (ALWAYS, "naked function: no prologue.");
+      return;
+    }
+
+  /* if this is an interrupt service routine then
+     save h  */
+  if (IFFUNC_ISISR (sym->type))
+    {
+      if (!inExcludeList ("y"))
+        pushReg (m6502_reg_y, false);
+    }
+
+  /* For some cases it is worthwhile to perform a RECEIVE iCode */
+  /* before setting up the stack frame completely. */
+  int numStackParams = 0;
+  while (ric && ric->next && ric->next->op == RECEIVE)
+    ric = ric->next;
+  while (ric && IC_RESULT (ric))
+    {
+      symbol *rsym = OP_SYMBOL (IC_RESULT (ric));
+      int rsymSize = rsym ? getSize (rsym->type) : 0;
+
+      if (rsym->isitmp)
+        {
+          if (rsym && rsym->regType == REG_CND)
+            rsym = NULL;
+          if (rsym && (/*rsym->accuse ||*/ rsym->ruonly))
+            rsym = NULL;
+          if (rsym && (rsym->isspilt || rsym->nRegs == 0) && rsym->usl.spillLoc)
+            rsym = rsym->usl.spillLoc;
+        }
+
+      /* If the RECEIVE operand immediately spills to the first entry on the  */
+      /* stack, we can push it directly rather than use an sp relative store. */
+      if (rsym && rsym->onStack && rsym->stack == -_G.stackPushes - rsymSize)
+        {
+          int ofs;
+
+          genLine.lineElement.ic = ric;
+          emitComment (TRACEGEN, "genReceive", "size=%d", rsymSize);
+	  //          for (ofs = 0; ofs < rsymSize; ofs++)
+          m6502_reg_a->isFree=false;
+	  for (ofs = rsymSize-1; ofs >=0; ofs--)
+            {
+              reg_info *reg = m6502_aop_pass[ofs + (ric->argreg - 1)]->aopu.aop_reg[0];
+	      emitComment (TRACEGEN, "pushreg", "ofs=%d", ofs);
+              pushReg (reg, true);
+	      //              if (reg->rIdx == A_IDX)
+	      //                accIsFree = 1;
+              stackAdjust--;
+            }
+          genLine.lineElement.ic = ic;
+          ric->generated = 1;
+        }
+      ric = (ric->prev && ric->prev->op == RECEIVE) ? ric->prev : NULL;
+    }
+
+  /* adjust the stack for the function */
+  if (stackAdjust)
+    {
+      adjustStack (-stackAdjust);
+    }
+  _G.stackOfs = sym->stack;
+  _G.stackPushes = 0;
+  _G.funcHasBasePtr = 0;
+  // TODO: how to see if needed? how to count params?
+  if ( stackAdjust || sym->stack || numStackParams || IFFUNC_ISREENT(sym->type) )
+    {
+      saveBasePtr();
+      _G.funcHasBasePtr = 1;
+    }
+
+  /* if critical function then turn interrupts off */
+  if (IFFUNC_ISCRITICAL (ftype))
+    {
+      emit6502op ("php", "");
+      emit6502op ("sei", "");
+    }
+}
+
+/*-----------------------------------------------------------------*/
+/* genEndFunction - generates epilogue for functions               */
+/*-----------------------------------------------------------------*/
+static void
+genEndFunction (iCode * ic)
+{
+  symbol *sym = OP_SYMBOL (IC_LEFT (ic));
+
+  emitComment (TRACEGEN, __func__);
+  emitComment (REGOPS, "  %s %s", __func__, regInfoStr() );
+
+
+  if (IFFUNC_ISNAKED (sym->type))
+    {
+      emitComment (ALWAYS, "naked function: no epilogue.");
+      if (options.debug && currFunc && !regalloc_dry_run)
+        debugFile->writeEndFunction (currFunc, ic, 0);
+      return;
+    }
+
+  if (IFFUNC_ISCRITICAL (sym->type))
+    {
+      emit6502op ("plp", "");
+    }
+
+  if (IFFUNC_ISREENT (sym->type) || options.stackAuto)
+    {
+    }
+    
+  if (_G.funcHasBasePtr)
+    restoreBasePtr();
+
+  if(_G.stackPushes)
+    emitcode("ERROR","_G.stackPushes=%d in genEndFunction");
+
+  if (sym->stack)
+    {
+      _G.stackPushes += sym->stack;
+      adjustStack (sym->stack);
+    }
+
+
+  if ((IFFUNC_ISREENT (sym->type) || options.stackAuto))
+    {
+    }
+
+  if (IFFUNC_ISISR (sym->type))
+    {
+
+      if (!inExcludeList ("y"))
+        pullReg (m6502_reg_y); // TODO?
+
+
+      /* if debug then send end of function */
+      if (options.debug && currFunc && !regalloc_dry_run)
+        {
+          debugFile->writeEndFunction (currFunc, ic, 1);
+        }
+
+      emit6502op ("rti", "");
+    }
+  else
+    {
+      if (IFFUNC_CALLEESAVES (sym->type))
+        {
+          int i;
+
+          /* if any registers used */
+          if (sym->regsUsed)
+            {
+              /* save the registers used */
+              for (i = sym->regsUsed->size; i >= 0; i--)
+                {
+                  if (bitVectBitValue (sym->regsUsed, i) || (m6502_ptrRegReq && (i == YX_IDX || i == YX_IDX)))
+		    // FIXME
+                    emitcode ("pop", "%s", m6502_regWithIdx (i)->name); /* Todo: Cost. Can't find this instruction in manual! */
+                }
+            }
+        }
+
+      /* if debug then send end of function */
+      if (options.debug && currFunc && !regalloc_dry_run)
+        {
+          debugFile->writeEndFunction (currFunc, ic, 1);
+        }
+
+      emit6502op ("rts", "");
+    }
+}
+
+/*-----------------------------------------------------------------*/
+/* genRet - generate code for return statement                     */
+/*-----------------------------------------------------------------*/
+static void
+genRet (iCode * ic)
+{
+  int size, offset = 0;
+//  int pushed = 0;
+  bool delayed_x = false;
+
+  emitComment (TRACEGEN, __func__);
+  emitComment (REGOPS, "  %s %s", __func__, regInfoStr() );
+
+
+  /* if we have no return value then
+     just generate the "ret" */
+  if (!IC_LEFT (ic))
+    goto jumpret;
+
+  /* we have something to return then
+     move the return value into place */
+  aopOp (IC_LEFT (ic), ic, false);
+  size = AOP_SIZE (IC_LEFT (ic));
+
+  if (AOP_TYPE (IC_LEFT (ic)) == AOP_LIT)
+    {
+      /* If returning a literal, we can load the bytes of the return value */
+      /* in any order. By loading A and X first, any other bytes that match */
+      /* can use the shorter sta and stx instructions. */
+      offset = 0;
+      while (size--)
+        {
+          transferAopAop (AOP (IC_LEFT (ic)), offset, m6502_aop_pass[offset], 0);
+          offset++;
+        }
+    }
+  else
+    {
+      /* Take care when swapping a and x */
+      if (AOP_TYPE (IC_LEFT (ic)) == AOP_REG && size > 1 && AOP (IC_LEFT (ic))->aopu.aop_reg[0]->rIdx == X_IDX)
+        {
+          delayed_x = true;
+          pushReg (m6502_reg_x, true);
+        }
+
+      offset = size - 1;
+      while (size--)
+        {
+          if (!(delayed_x && !offset))
+            transferAopAop (AOP (IC_LEFT (ic)), offset, m6502_aop_pass[offset], 0);
+          offset--;
+        }
+
+      if (delayed_x)
+        pullReg (m6502_reg_a);
+    }
+
+  freeAsmop (IC_LEFT (ic), NULL, ic, true);
+
+jumpret:
+  /* generate a jump to the return label
+     if the next is not the return statement */
+  if (!(ic->next && ic->next->op == LABEL && IC_LABEL (ic->next) == returnLabel))
+    {
+      emit6502op ("jmp", "%05d$", safeLabelKey2num (returnLabel->key));
+    }
+}
+
+/*-----------------------------------------------------------------*/
+/* genLabel - generates a label                                    */
+/*-----------------------------------------------------------------*/
+static void
+genLabel (iCode * ic)
+{
+  int i;
+
+  emitComment (TRACEGEN, __func__);
+  emitComment (REGOPS, "  %s %s", __func__, regInfoStr() );
+
+
+  /* For the high level labels we cannot depend on any */
+  /* register's contents. Amnesia time.                */
+  for (i = A_IDX; i <= XA_IDX; i++) {
+      m6502_dirtyReg (m6502_regWithIdx (i));
+      m6502_useReg (m6502_regWithIdx (i));
+        }
+  /* special case never generate */
+  if (IC_LABEL (ic) == entryLabel)
+    return;
+
+  if (options.debug && !regalloc_dry_run)
+    debugFile->writeLabel (IC_LABEL (ic), ic);
+
+  emitLabel (IC_LABEL (ic));
+}
+
+/*-----------------------------------------------------------------*/
+/* genGoto - generates a jmp                                      */
+/*-----------------------------------------------------------------*/
+static void
+genGoto (iCode * ic)
+{
+  emitComment (TRACEGEN, __func__);
+  emit6502op ("jmp", "%05d$", safeLabelKey2num (IC_LABEL (ic)->key));
+}
+
+
+/*-----------------------------------------------------------------*/
+/* genPlusIncr :- does addition with increment if possible         */
+/*-----------------------------------------------------------------*/
+static bool
+genPlusIncr (iCode * ic)
+{
+  int icount;
+  operand *left;
+  operand *result;
+  bool needpula;
+  unsigned int size = getDataSize (IC_RESULT (ic));
+  unsigned int offset;
+  symbol *tlbl = NULL;
+
+  emitComment (TRACEGEN, __func__);
+
+  left = IC_LEFT (ic);
+  result = IC_RESULT (ic);
+
+  /* will try to generate an increment */
+  /* if the right side is not a literal
+     we cannot */
+  if (AOP_TYPE (IC_RIGHT (ic)) != AOP_LIT)
+    return false;
+
+  icount = (unsigned int) ulFromVal (AOP (IC_RIGHT (ic))->aopu.aop_lit);
+
+  emitComment (TRACEGEN|VVDBG, "  icount = %d, sameRegs=%d", icount, sameRegs (AOP (left), AOP (result)));
+
+  if (icount > 255)
+    return false;
+
+  if (!sameRegs (AOP (left), AOP (result)))
+    return false;
+
+  // TODO: can inc blah,x
+  if (!aopCanIncDec (AOP (result)))
+    return false;
+
+  emitComment (TRACEGEN|VVDBG, "   genPlusIncr");
+
+  if (size==1 && AOP(result)->type==AOP_REG) {
+    // if it's in a 8-bit register try to do small adjust
+    if(smallAdjustReg(AOP(result)->aopu.aop_reg[0], icount)==0) return true;   
+  }
+
+  if(icount < 0 )
+    return false;
+
+  aopOpExtToIdx (AOP (result), AOP (left), NULL);
+
+  if (size > 1)
+    tlbl = safeNewiTempLabel (NULL);
+
+  if (icount == 1)
+    {
+      needpula = false;
+      rmwWithAop ("inc", AOP (result), 0);
+      if (size > 1)
+        emitBranch ("bne", tlbl);
+    }
+  else
+    {
+     if (!IS_AOP_A (AOP (result)) && !IS_AOP_XA (AOP (result)))
+        needpula = pushRegIfUsed (m6502_reg_a);
+      else
+        needpula = false;
+      loadRegFromAop (m6502_reg_a, AOP (result), 0);
+      emit6502op("clc", "");
+      accopWithAop ("adc", AOP (IC_RIGHT (ic)), 0);
+      storeRegToAop (m6502_reg_a, AOP (result), 0);
+      if (size > 1)
+        emitBranch ("bcc", tlbl);
+    }
+  for (offset = 1; offset < size; offset++)
+    {
+      rmwWithAop ("inc", AOP (result), offset);
+      if(AOP(result)->type==AOP_REG) m6502_dirtyReg(AOP(result)->aopu.aop_reg[offset]);
+      if ((offset + 1) < size)
+        emitBranch ("bne", tlbl);
+    }
+
+  if (size > 1)
+    safeEmitLabel (tlbl);
+
+  pullOrFreeReg (m6502_reg_a, needpula);
+
+  return true;
+}
+
+
+
+/*-----------------------------------------------------------------*/
+/* genPlus - generates code for addition                           */
+/*-----------------------------------------------------------------*/
+static void
+genPlus (iCode * ic)
+{
+  int size, offset = 0;
+  bool clc = true;
+  asmop *leftOp, *rightOp;
+  bool needpulla;
+  bool earlystore = false;
+  bool delayedstore = false;
+  bool mayskip = true;
+  bool skip = false;
+
+  /* special cases :- */
+
+  emitComment (TRACEGEN, __func__);
+
+  aopOp (IC_LEFT (ic), ic, false);
+  aopOp (IC_RIGHT (ic), ic, false);
+  aopOp (IC_RESULT (ic), ic, true);
+
+  /* we want registers on the left and literals on the right */
+  if ((AOP_TYPE (IC_LEFT (ic)) == AOP_LIT) || (AOP_TYPE (IC_RIGHT (ic)) == AOP_REG && !IS_AOP_WITH_A (AOP (IC_LEFT (ic)))))
+    {
+      operand *t = IC_RIGHT (ic);
+      IC_RIGHT (ic) = IC_LEFT (ic);
+      IC_LEFT (ic) = t;
+    }
+
+  /* if I can do an increment instead
+     of add then GOOD for ME */
+  if (genPlusIncr (ic) == true)
+    goto release;
+
+  emitComment (TRACEGEN|VVDBG, "   left size = %d", getDataSize (IC_LEFT (ic)));
+  emitComment (TRACEGEN|VVDBG, "   right size = %d", getDataSize (IC_RIGHT (ic)));
+  emitComment (TRACEGEN|VVDBG, "   result size = %d", getDataSize (IC_RESULT (ic)));
+
+  aopOpExtToIdx (AOP (IC_RESULT (ic)), AOP (IC_LEFT (ic)), AOP (IC_RIGHT (ic)));
+
+  size = getDataSize (IC_RESULT (ic));
+
+  leftOp = AOP (IC_LEFT (ic));
+  rightOp = AOP (IC_RIGHT (ic));
+
+  offset = 0;
+  needpulla = pushRegIfSurv (m6502_reg_a);
+
+  if(size > 1 && IS_AOP_AX (AOP (IC_LEFT (ic))))
+    {
+      earlystore = true;
+      pushReg (m6502_reg_a, true);
+    }
+
+  while (size--)
+    {
+      if (earlystore && offset == 1)
+        pullReg (m6502_reg_a);
+      else
+        loadRegFromAop (m6502_reg_a, leftOp, offset);
+      if (clc)
+        emit6502op ("clc", "");
+      if (!mayskip || AOP_TYPE (IC_RIGHT (ic)) != AOP_LIT || (byteOfVal (AOP (IC_RIGHT (ic))->aopu.aop_lit, offset) != 0x00) )
+        {
+          accopWithAop ("adc", rightOp, offset);
+          mayskip = false;
+          skip = false;
+        }
+      else
+        skip = true;
+      if (size && AOP_TYPE (IC_RESULT (ic)) == AOP_REG && AOP (IC_RESULT (ic))->aopu.aop_reg[offset]->rIdx == A_IDX)
+        {
+          pushReg (m6502_reg_a, true);
+          delayedstore = true;
+        }
+      else
+        storeRegToAop (m6502_reg_a, AOP (IC_RESULT (ic)), offset);
+      offset++;
+      m6502_freeReg (m6502_reg_a);
+      if (!skip)
+        clc = false;              /* further adds must propagate carry */
+    }
+ if (delayedstore)
+   pullReg (m6502_reg_a);
+ pullOrFreeReg (m6502_reg_a, needpulla);
+
+ wassert (!earlystore || !delayedstore);
+
+release:
+  freeAsmop (IC_RESULT (ic), NULL, ic, true);
+  freeAsmop (IC_RIGHT (ic), NULL, ic, true);
+  freeAsmop (IC_LEFT (ic), NULL, ic, true);
+}
+
+/*-----------------------------------------------------------------*/
+/* genMinusDec :- does subtraction with decrement if possible      */
+/*-----------------------------------------------------------------*/
+static bool
+genMinusDec (iCode * ic)
+{
+  int icount;
+  operand *left;
+  operand *result;
+  unsigned int size = getDataSize (IC_RESULT (ic));
+//  int offset;
+//  symbol *tlbl;
+
+  emitComment (TRACEGEN, __func__);
+
+  left = IC_LEFT (ic);
+  result = IC_RESULT (ic);
+
+  /* will try to generate an increment */
+  /* if the right side is not a literal
+     we cannot */
+  if (AOP_TYPE (IC_RIGHT (ic)) != AOP_LIT)
+    return false;
+    
+  icount = (unsigned int) ulFromVal (AOP (IC_RIGHT (ic))->aopu.aop_lit);
+  // TODO: genPlusIncr has a lot more, can merge?
+
+  if (!sameRegs (AOP (left), AOP (result)))
+    return false;
+
+  if (size != 1)
+    return false;
+
+  // TODO: can inc blah,x
+  if (!aopCanIncDec (AOP (result)))
+    return false;
+
+  // do dex/dey and inx/iny if icount is negative
+  if(!smallAdjustReg(AOP(result)->aopu.aop_reg[0],-icount))
+      return true;
+
+  if ((icount > 1) || (icount < 0))
+    return false;
+
+  emitComment (TRACEGEN|VVDBG, "     genMinusDec");
+
+  aopOpExtToIdx (AOP (result), AOP (left), NULL);
+
+  rmwWithAop ("dec", AOP (result), 0);
+
+  return true;
+}
+
+/*-----------------------------------------------------------------*/
+/* addSign - complete with sign                                    */
+/*-----------------------------------------------------------------*/
+static void
+addSign (operand * result, int offset, int sign)
+{
+  int size = (getDataSize (result) - offset);
+  if (size > 0)
+    {
+      if (sign)
+        {
+          signExtendA();
+          while (size--)
+            storeRegToAop (m6502_reg_a, AOP (result), offset++);
+        }
+      else
+        while (size--)
+          storeConstToAop (0, AOP (result), offset++);
+    }
+}
+
+
+/*-----------------------------------------------------------------*/
+/* genMinus - generates code for subtraction                       */
+/*-----------------------------------------------------------------*/
+static void
+genMinus (iCode * ic)
+{
+  bool carry = true;
+  int size, offset = 0;
+  bool needpulla;
+  bool earlystore = false;
+  bool delayedstore = false;
+
+  asmop *leftOp, *rightOp;
+
+  emitComment (TRACEGEN, __func__);
+
+  aopOp (IC_LEFT (ic), ic, false);
+  aopOp (IC_RIGHT (ic), ic, false);
+  aopOp (IC_RESULT (ic), ic, true);
+
+  /* special cases :- */
+  /* if I can do an decrement instead
+     of subtract then GOOD for ME */
+  if (genMinusDec (ic) == true)
+    goto release;
+
+  emitComment (TRACEGEN|VVDBG, "    genMinus - Can't Dec");
+  aopOpExtToIdx (AOP (IC_RESULT (ic)), AOP (IC_LEFT (ic)), AOP (IC_RIGHT (ic)));
+
+  size = getDataSize (IC_RESULT (ic));
+
+
+  leftOp = AOP (IC_LEFT (ic));
+  rightOp = AOP (IC_RIGHT (ic));
+  offset = 0;
+
+  if (IS_AOP_A (rightOp))
+    {
+      // op - a = neg(a - op) = not(a - op) + 1 = not(a - op - 1)
+      needpulla = pushRegIfSurv (m6502_reg_a);
+      emit6502op("clc", "");
+      accopWithAop ("sbc", leftOp, offset);
+      emit6502op("eor", "#0xff");
+      storeRegToAop (m6502_reg_a, AOP (IC_RESULT (ic)), offset);
+      pullOrFreeReg (m6502_reg_a, needpulla);
+      goto release;
+    }
+
+  needpulla = pushRegIfSurv (m6502_reg_a);
+
+  if (size > 1 && (IS_AOP_AX (AOP (IC_LEFT (ic))) || IS_AOP_AX (AOP (IC_RIGHT (ic)))))
+    {
+      earlystore = true;
+      pushReg (m6502_reg_a, true);
+    }
+
+  while (size--)
+    {
+      if (earlystore &&
+        (AOP_TYPE (IC_LEFT (ic)) == AOP_REG && AOP (IC_LEFT (ic))->aopu.aop_reg[offset]->rIdx == A_IDX ||
+        AOP_TYPE (IC_RIGHT (ic)) == AOP_REG && AOP (IC_RIGHT (ic))->aopu.aop_reg[offset]->rIdx == A_IDX))
+        pullReg (m6502_reg_a);
+      if (AOP_TYPE (IC_RIGHT (ic)) == AOP_REG && AOP (IC_RIGHT (ic))->aopu.aop_reg[offset]->rIdx == A_IDX)
+        {
+          storeRegTemp (m6502_reg_a, true);
+          loadRegFromAop (m6502_reg_a, leftOp, offset);
+          if (carry) {
+            emit6502op("sec", "");
+            }
+          emit6502op ("sbc", TEMPFMT, _G.tempOfs - 1);
+          loadRegTemp (NULL);
+        }
+      else
+        {
+          emitComment (TRACEGEN|VVDBG, "    - default path");
+
+          loadRegFromAop (m6502_reg_a, leftOp, offset);
+          if (carry) {
+            emit6502op("sec", "");
+            }
+          accopWithAop ("sbc", rightOp, offset);
+        }
+      if (size && AOP_TYPE (IC_RESULT (ic)) == AOP_REG && AOP (IC_RESULT (ic))->aopu.aop_reg[offset]->rIdx == A_IDX)
+        {
+          emitComment (TRACEGEN|VVDBG, "    - push");
+          pushReg (m6502_reg_a, true);
+          delayedstore = true;
+        }
+      else
+        {
+          emitComment (TRACEGEN|VVDBG, "    - store");
+        storeRegToAop (m6502_reg_a, AOP (IC_RESULT (ic)), offset);
+        }
+      offset++;
+      carry = false;
+    }
+  if(delayedstore)
+    pullReg (m6502_reg_a);
+  pullOrFreeReg (m6502_reg_a, needpulla);
+
+  wassert (!earlystore || !delayedstore);
+
+release:
+  freeAsmop (IC_LEFT (ic), NULL, ic, (RESULTONSTACK (ic) ? false : true));
+  freeAsmop (IC_RIGHT (ic), NULL, ic, (RESULTONSTACK (ic) ? false : true));
+  freeAsmop (IC_RESULT (ic), NULL, ic, true);
+}
+
+
+/*-----------------------------------------------------------------*/
+/* genMult - generates code for multiplication                     */
+/*-----------------------------------------------------------------*/
+static void
+genMult (iCode * ic)
+{
+  /* Shouldn't occur - all done through function calls */
+  wassertl (0, "Multiplication is handled through support function calls");
+}
+
+/*-----------------------------------------------------------------*/
+/* genDiv - generates code for division                            */
+/*-----------------------------------------------------------------*/
+static void
+genDiv (iCode * ic)
+{
+  /* Shouldn't occur - all done through function calls */
+  wassertl (0, "Division is handled through support function calls");
+}
+
+/*-----------------------------------------------------------------*/
+/* genMod - generates code for division                            */
+/*-----------------------------------------------------------------*/
+static void
+genMod (iCode * ic)
+{
+  /* Shouldn't occur - all done through function calls */
+  wassertl (0, "Division is handled through support function calls");
+}
+
+/*-----------------------------------------------------------------*/
+/* genIfxJump :- will create a jump depending on the ifx           */
+/*-----------------------------------------------------------------*/
+static void
+genIfxJump (iCode * ic, char *jval)
+{
+  symbol *jlbl;
+  symbol *tlbl = safeNewiTempLabel (NULL);
+  char *inst;
+
+  emitComment (TRACEGEN, __func__);
+
+  /* if true label then we jump if condition
+     supplied is true */
+  if (IC_TRUE (ic))
+    {
+      jlbl = IC_TRUE (ic);
+      if (!strcmp (jval, "a"))
+        inst = "beq";
+      else if (!strcmp (jval, "c"))
+        inst = "bcc";
+      else if (!strcmp (jval, "n"))
+        inst = "bpl";
+      else if (!strcmp (jval, "v"))
+        inst = "bvc";
+      else
+        inst = "bge";
+    }
+  else
+    {
+      /* false label is present */
+      jlbl = IC_FALSE (ic);
+      if (!strcmp (jval, "a"))
+        inst = "bne";
+      else if (!strcmp (jval, "c"))
+        inst = "bcs";
+      else if (!strcmp (jval, "n"))
+        inst = "bmi";
+      else if (!strcmp (jval, "v"))
+        inst = "bvs";
+      else
+        inst = "blt";
+    }
+  emitBranch (inst, tlbl);
+  emitBranch ("jmp", jlbl);
+  safeEmitLabel (tlbl);
+
+  /* mark the icode as generated */
+  ic->generated = 1;
+}
+
+
+/*-----------------------------------------------------------------*/
+/* exchangedCmp : returns the opcode need if the two operands are  */
+/*                exchanged in a comparison                        */
+/*-----------------------------------------------------------------*/
+static int
+exchangedCmp (int opcode)
+{
+  switch (opcode)
+    {
+    case '<':
+      return '>';
+    case '>':
+      return '<';
+    case LE_OP:
+      return GE_OP;
+    case GE_OP:
+      return LE_OP;
+    case NE_OP:
+      return NE_OP;
+    case EQ_OP:
+      return EQ_OP;
+    default:
+      werror (E_INTERNAL_ERROR, __FILE__, __LINE__, "opcode not a comparison");
+    }
+  return EQ_OP;                 /* shouldn't happen, but need to return something */
+}
+
+/*------------------------------------------------------------------*/
+/* negatedCmp : returns the equivalent opcode for when a comparison */
+/*              if not true                                         */
+/*------------------------------------------------------------------*/
+static int
+negatedCmp (int opcode)
+{
+  switch (opcode)
+    {
+    case '<':
+      return GE_OP;
+    case '>':
+      return LE_OP;
+    case LE_OP:
+      return '>';
+    case GE_OP:
+      return '<';
+    case NE_OP:
+      return EQ_OP;
+    case EQ_OP:
+      return NE_OP;
+    default:
+      werror (E_INTERNAL_ERROR, __FILE__, __LINE__, "opcode not a comparison");
+    }
+  return EQ_OP;                 /* shouldn't happen, but need to return something */
+}
+
+/*------------------------------------------------------------------*/
+/* nameCmp : helper function for human readable debug output        */
+/*------------------------------------------------------------------*/
+static char *
+nameCmp (int opcode)
+{
+  switch (opcode)
+    {
+    case '<':
+      return "<";
+    case '>':
+      return ">";
+    case LE_OP:
+      return "<=";
+    case GE_OP:
+      return ">=";
+    case NE_OP:
+      return "!=";
+    case EQ_OP:
+      return "==";
+    default:
+      return "invalid";
+    }
+}
+
+/*------------------------------------------------------------------*/
+/* branchInstCmp : returns the conditional branch instruction that  */
+/*                 will branch if the comparison is true            */
+/*------------------------------------------------------------------*/
+static char *
+branchInstCmp (int opcode, int sign)
+{
+  switch (opcode)
+    {
+    case '<':
+      if (sign)
+        return "blt";
+      else
+        return "bcc";
+    case '>':
+      if (sign)
+        return "bgt";
+      else
+        return "bhi";
+    case LE_OP:
+      if (sign)
+        return "ble";
+      else
+        return "bls";
+    case GE_OP:
+      if (sign)
+        return "bge";
+      else
+        return "bcs";
+    case NE_OP:
+      return "bne";
+    case EQ_OP:
+      return "beq";
+    default:
+      werror (E_INTERNAL_ERROR, __FILE__, __LINE__, "opcode not a comparison");
+    }
+  return "brn";
+}
+
+/*------------------------------------------------------------------*/
+/* genCmp :- greater or less than (and maybe with equal) comparison */
+/*------------------------------------------------------------------*/
+static void
+genCmp (iCode * ic, iCode * ifx)
+{
+  operand *left, *right, *result;
+  sym_link *letype, *retype;
+  int sign, opcode;
+  int size, offset = 0;
+  unsigned long long lit = 0ull;
+  char *sub;
+  symbol *jlbl = NULL;
+  bool needloada = false;
+
+  emitComment (TRACEGEN, __func__);
+
+  opcode = ic->op;
+
+  // TODO: optimize for cmp regs with 0 or constant
+
+  result = IC_RESULT (ic);
+  left = IC_LEFT (ic);
+  right = IC_RIGHT (ic);
+
+  sign = 0;
+  // TODO: don't use signed when unsigned will do
+  if (IS_SPEC (operandType (left)) && IS_SPEC (operandType (right)))
+    {
+      letype = getSpec (operandType (left));
+      retype = getSpec (operandType (right));
+      sign = !(SPEC_USIGN (letype) | SPEC_USIGN (retype));
+    }
+
+  /* assign the amsops */
+  aopOp (left, ic, false);
+  aopOp (right, ic, false);
+  aopOp (result, ic, true);
+
+  /* need register operand on left, prefer literal operand on right */
+  if ((AOP_TYPE (right) == AOP_REG) || AOP_TYPE (left) == AOP_LIT)
+    {
+      operand *temp = left;
+      left = right;
+      right = temp;
+      opcode = exchangedCmp (opcode);
+    }
+  // TODO: special case for compare with 0
+
+  if (ifx)
+    {
+      if (IC_TRUE (ifx))
+        {
+          jlbl = IC_TRUE (ifx);
+          opcode = negatedCmp (opcode);
+        }
+      else
+        {
+          /* false label is present */
+          jlbl = IC_FALSE (ifx);
+        }
+    }
+
+  size = max (AOP_SIZE (left), AOP_SIZE (right));
+
+  emitComment (TRACEGEN|VVDBG, "      genCmp", "(%s, size %d, sign %d)", nameCmp (opcode), size, sign);
+  
+  if (!sign && size == 1 && IS_AOP_X (AOP (left)) && isAddrSafe(right, m6502_reg_x) )
+    {
+      accopWithAop ("cpx", AOP (right), offset);
+    }
+  else if (!sign && size == 1 && IS_AOP_Y (AOP (left)) && isAddrSafe(right, m6502_reg_y) )
+    {
+      accopWithAop ("cpy", AOP (right), offset);
+    }
+  else if (!sign && size == 1 && IS_AOP_A (AOP (left)) && isAddrSafe(right, m6502_reg_a))
+    {
+      accopWithAop ("cmp", AOP (right), offset);
+    }
+  else
+    {
+      offset = 0;
+      // need V flag for signed compare
+      // FIXME: is this covered above?
+      if (size == 1 && sign == 0)
+        sub = "cmp";
+      else
+        {
+          sub = "sub";
+
+          /* These conditions depend on the Z flag bit, but Z is */
+          /* only valid for the last byte of the comparison, not */
+          /* the whole value. So exchange the operands to get a  */
+          /* comparison that doesn't depend on Z. (This is safe  */
+          /* to do here since ralloc won't assign multi-byte     */
+          /* operands to registers for comparisons)              */
+          if ((opcode == '>') || (opcode == LE_OP))
+            {
+              operand *temp = left;
+              left = right;
+              right = temp;
+              opcode = exchangedCmp (opcode);
+            }
+
+          if ((AOP_TYPE (right) == AOP_LIT) && !isOperandVolatile (left, false))
+            {
+              lit = ullFromVal (AOP (right)->aopu.aop_lit);
+              while ((size > 1) && (((lit >> (8 * offset)) & 0xff) == 0))
+                {
+                  offset++;
+                  size--;
+                }
+            }
+        }
+      needloada = storeRegTempIfSurv (m6502_reg_a);
+      while (size--)
+        {
+          emitComment (TRACEGEN|VVDBG, "   GenCmp - size counter = %d", size);
+
+          if (AOP_TYPE (right) == AOP_REG && AOP(right)->aopu.aop_reg[offset]->rIdx == A_IDX)
+            {
+              storeRegTemp(m6502_reg_a, true);
+              loadRegFromAop (m6502_reg_a, AOP (left), offset);
+              if (!strcmp(sub, "sub")) {
+                emit6502op ("sec", "");
+                emit6502op ("sbc", TEMPFMT, _G.tempOfs - 1);
+              } else {         
+                emit6502op (sub, TEMPFMT, _G.tempOfs - 1);
+              }
+              loadRegTemp(NULL);
+            }
+          else
+            {
+              loadRegFromAop (m6502_reg_a, AOP (left), offset);
+              if (!strcmp(sub, "sub")) {
+                emit6502op ("sec", "");
+                accopWithAop ("sbc", AOP (right), offset);
+              } else {
+                accopWithAop (sub, AOP (right), offset);
+              }
+            }
+          m6502_freeReg (m6502_reg_a);
+          offset++;
+          sub = "sbc";
+        }
+    }
+  freeAsmop (right, NULL, ic, false);
+  freeAsmop (left, NULL, ic, false);
+
+  if (ifx)
+    {
+      symbol *tlbl = safeNewiTempLabel (NULL);
+      char *inst;
+
+      if(needloada) 
+          loadRegTempNoFlags(m6502_reg_a, needloada);
+      else
+          m6502_freeReg(m6502_reg_a);
+
+      freeAsmop (result, NULL, ic, true);
+
+      inst = branchInstCmp (opcode, sign);
+      emitBranch (inst, tlbl);
+      emitBranch ("jmp", jlbl);
+      safeEmitLabel (tlbl);
+
+      /* mark the icode as generated */
+      ifx->generated = 1;
+    }
+  else
+    {
+      symbol *tlbl1 = safeNewiTempLabel (NULL);
+      symbol *tlbl2 = safeNewiTempLabel (NULL);
+
+      if (!needloada)
+        needloada = storeRegTempIfSurv (m6502_reg_a);
+
+      emitBranch (branchInstCmp (opcode, sign), tlbl1);
+      loadRegFromConst (m6502_reg_a, 0);
+      emitBranch ("bra", tlbl2);
+      safeEmitLabel (tlbl1);
+      loadRegFromConst (m6502_reg_a, 1);
+      safeEmitLabel (tlbl2);
+      m6502_dirtyReg (m6502_reg_a);
+      storeRegToFullAop (m6502_reg_a, AOP (result), false);
+      loadOrFreeRegTemp (m6502_reg_a, needloada);
+      freeAsmop (result, NULL, ic, true);
+    }
+}
+
+/*-----------------------------------------------------------------*/
+/* genCmpEQorNE - equal or not equal comparison                    */
+/*-----------------------------------------------------------------*/
+static void
+genCmpEQorNE (iCode * ic, iCode * ifx)
+{
+  operand *result = IC_RESULT (ic);
+  operand *left = IC_LEFT (ic);
+  operand *right = IC_RIGHT (ic);
+  int opcode;
+  int size;
+  symbol *jlbl = NULL;
+  symbol *tlbl_NE = NULL;
+  symbol *tlbl_EQ = NULL;
+  bool needloada = false;
+  int offset = 0;
+
+  emitComment (TRACEGEN, __func__);
+
+  opcode = ic->op;
+
+  emitComment (TRACEGEN|VVDBG, "      genCmpEQorNE (%s)", nameCmp (opcode));
+
+  /* assign the amsops */
+  aopOp (left, ic, false);
+  aopOp (right, ic, false);
+  aopOp (result, ic, true);
+
+  /* need register operand on left, prefer literal operand on right */
+  if ((AOP_TYPE (right) == AOP_REG) || AOP_TYPE (left) == AOP_LIT)
+    {
+      operand *temp = left;
+      left = right;
+      right = temp;
+      opcode = exchangedCmp (opcode);
+    }
+
+  size = max (AOP_SIZE (left), AOP_SIZE (right));
+
+  if (ifx)
+    {
+      if (IC_TRUE (ifx))
+        {
+          jlbl = IC_TRUE (ifx);
+          opcode = negatedCmp (opcode);
+        }
+      else
+        {
+          /* false label is present */
+          jlbl = IC_FALSE (ifx);
+        }
+    }
+
+  if(AOP_TYPE (left) == AOP_REG)
+  emitComment (TRACEGEN|VVDBG, "   genCmpEQorNE left is reg: %s",AOP (left)->aopu.aop_reg[offset]->name);
+  else
+  emitComment (TRACEGEN|VVDBG, "   genCmpEQorNE left is not not a reg");
+
+// TODO: could clobber A if reg = XA?
+    {
+      offset = 0;
+      while (size--)
+        {
+          if (AOP_TYPE (left) == AOP_REG && AOP (left)->aopu.aop_reg[offset]->rIdx == X_IDX && isAddrSafe(right, m6502_reg_x))
+            accopWithAop ("cpx", AOP (right), offset);
+          else if (AOP_TYPE (left) == AOP_REG && AOP (left)->aopu.aop_reg[offset]->rIdx == Y_IDX && isAddrSafe(right, m6502_reg_y))
+            accopWithAop ("cpy", AOP (right), offset);
+          else
+            {
+              emitComment (TRACEGEN|VVDBG, "      genCmpEQorNE can't cpx or cpy");
+
+            // TODO? why do we push when we could cpx?
+              if (!(AOP_TYPE (left) == AOP_REG && AOP (left)->aopu.aop_reg[offset]->rIdx == A_IDX))
+                {
+                  // FIXME: always?
+                  storeRegTemp (m6502_reg_a, true);
+                  needloada = true;
+//                  needloada = storeRegTempIfUsed (m6502_reg_a);
+                  loadRegFromAop (m6502_reg_a, AOP (left), offset);
+                }
+              accopWithAop ("cmp", AOP (right), offset);
+              loadRegTempNoFlags (m6502_reg_a, needloada);
+              needloada = false;
+            }
+          if (size)
+            {
+              symbol *tmp_label = safeNewiTempLabel (NULL);;
+              if (!tlbl_NE)
+                tlbl_NE = safeNewiTempLabel (NULL);
+              if (!needloada && !ifx)
+                needloada = storeRegTempIfSurv (m6502_reg_a);
+
+              emitBranch ("beq", tmp_label);
+              emitBranch ("jmp", tlbl_NE);
+              safeEmitLabel (tmp_label);
+
+              loadOrFreeRegTemp (m6502_reg_a, needloada);
+              needloada = false;
+            }
+          offset++;
+          }
+    }
+  freeAsmop (right, NULL, ic, false);
+  freeAsmop (left, NULL, ic, false);
+
+  if (ifx)
+    {
+      freeAsmop (result, NULL, ic, true);
+
+      if (opcode == EQ_OP)
+        {
+          if (!tlbl_EQ)
+            tlbl_EQ = safeNewiTempLabel (NULL);
+          emitBranch ("beq", tlbl_EQ);
+          if (tlbl_NE)
+            safeEmitLabel (tlbl_NE);
+          emitBranch ("jmp", jlbl);
+          safeEmitLabel (tlbl_EQ);
+        }
+      else
+        {
+          if (!tlbl_NE)
+            tlbl_NE = safeNewiTempLabel (NULL);
+          emitBranch ("bne", tlbl_NE);
+          emitBranch ("jmp", jlbl);
+          safeEmitLabel (tlbl_NE);
+        }
+
+      /* mark the icode as generated */
+      ifx->generated = 1;
+    }
+  else
+    {
+      symbol *tlbl = safeNewiTempLabel (NULL);
+
+      if (!needloada)
+        needloada = storeRegTempIfSurv (m6502_reg_a);
+      if (opcode == EQ_OP)
+        {
+          if (!tlbl_EQ)
+            tlbl_EQ = safeNewiTempLabel (NULL);
+          emitBranch ("beq", tlbl_EQ);
+          if (tlbl_NE)
+            emitLabel (tlbl_NE);
+          loadRegFromConst (m6502_reg_a, 0);
+          emitBranch ("bra", tlbl);
+          safeEmitLabel (tlbl_EQ);
+          loadRegFromConst (m6502_reg_a, 1);
+        }
+      else
+        {
+          if (!tlbl_NE)
+            tlbl_NE = safeNewiTempLabel (NULL);
+          emitBranch ("bne", tlbl_NE);
+          loadRegFromConst (m6502_reg_a, 0);
+          emitBranch ("bra", tlbl);
+          safeEmitLabel (tlbl_NE);
+          loadRegFromConst (m6502_reg_a, 1);
+        }
+
+      safeEmitLabel (tlbl);
+      m6502_dirtyReg (m6502_reg_a);
+      storeRegToFullAop (m6502_reg_a, AOP (result), false);
+      loadOrFreeRegTemp (m6502_reg_a, needloada);
+      freeAsmop (result, NULL, ic, true);
+    }
+}
+
+/*-----------------------------------------------------------------*/
+/* genAndOp - for && operation                                     */
+/*-----------------------------------------------------------------*/
+static void
+genAndOp (iCode * ic)
+{
+  operand *left, *right, *result;
+  symbol *tlbl, *tlbl0;
+  bool needpulla;
+
+  emitComment (TRACEGEN, __func__);
+  
+  // TODO: optimize & 0xff as cast when signed
+
+  /* note here that && operations that are in an
+     if statement are taken away by backPatchLabels
+     only those used in arthmetic operations remain */
+  aopOp ((left = IC_LEFT (ic)), ic, false);
+  aopOp ((right = IC_RIGHT (ic)), ic, false);
+  aopOp ((result = IC_RESULT (ic)), ic, false);
+
+  tlbl = safeNewiTempLabel (NULL);
+  tlbl0 = safeNewiTempLabel (NULL);
+
+  needpulla = pushRegIfSurv (m6502_reg_a);
+  asmopToBool (AOP (left), false);
+  emitBranch ("beq", tlbl0);
+  asmopToBool (AOP (right), false);
+  emitBranch ("beq", tlbl0);
+  loadRegFromConst (m6502_reg_a, 1);
+  emitBranch ("bra", tlbl);
+  safeEmitLabel (tlbl0);
+//  m6502_dirtyReg (m6502_reg_a);
+  loadRegFromConst (m6502_reg_a, 0);
+  safeEmitLabel (tlbl);
+  m6502_dirtyReg (m6502_reg_a);
+
+//  m6502_useReg (m6502_reg_a);
+//  m6502_freeReg (m6502_reg_a);
+
+  storeRegToFullAop (m6502_reg_a, AOP (result), false);
+  pullOrFreeReg(m6502_reg_a, needpulla);
+
+  freeAsmop (left, NULL, ic, (RESULTONSTACK (ic) ? false : true));
+  freeAsmop (right, NULL, ic, (RESULTONSTACK (ic) ? false : true));
+  freeAsmop (result, NULL, ic, true);
+}
+
+
+/*-----------------------------------------------------------------*/
+/* genOrOp - for || operation                                      */
+/*-----------------------------------------------------------------*/
+static void
+genOrOp (iCode * ic)
+{
+  operand *left, *right, *result;
+  symbol *tlbl, *tlbl0;
+  bool needpulla;
+
+  emitComment (TRACEGEN, __func__);
+
+  /* note here that || operations that are in an
+     if statement are taken away by backPatchLabels
+     only those used in arthmetic operations remain */
+  aopOp ((left = IC_LEFT (ic)), ic, false);
+  aopOp ((right = IC_RIGHT (ic)), ic, false);
+  aopOp ((result = IC_RESULT (ic)), ic, false);
+
+  tlbl = safeNewiTempLabel (NULL);
+  tlbl0 = safeNewiTempLabel (NULL);
+
+  needpulla = pushRegIfSurv (m6502_reg_a);
+  asmopToBool (AOP (left), false);
+  emitBranch ("bne", tlbl0);
+  asmopToBool (AOP (right), false);
+  emitBranch ("bne", tlbl0);
+  loadRegFromConst (m6502_reg_a, 0);
+  emitBranch ("bra", tlbl);
+  safeEmitLabel (tlbl0);
+//  m6502_dirtyReg (m6502_reg_a);
+  loadRegFromConst (m6502_reg_a, 1);
+  safeEmitLabel (tlbl);
+  m6502_dirtyReg (m6502_reg_a);
+
+//  m6502_useReg (m6502_reg_a);
+//  m6502_freeReg (m6502_reg_a);
+
+  storeRegToFullAop (m6502_reg_a, AOP (result), false);
+  pullOrFreeReg(m6502_reg_a, needpulla);
+
+  freeAsmop (left, NULL, ic, (RESULTONSTACK (ic) ? false : true));
+  freeAsmop (right, NULL, ic, (RESULTONSTACK (ic) ? false : true));
+  freeAsmop (result, NULL, ic, true);
+}
+
+/*-----------------------------------------------------------------*/
+/* isLiteralBit - test if lit == 2^n                               */
+/*-----------------------------------------------------------------*/
+static int
+isLiteralBit (unsigned long lit)
+{
+  unsigned long pw[32] =
+  {
+    1L, 2L, 4L, 8L, 16L, 32L, 64L, 128L,
+    0x100L, 0x200L, 0x400L, 0x800L,
+    0x1000L, 0x2000L, 0x4000L, 0x8000L,
+    0x10000L, 0x20000L, 0x40000L, 0x80000L,
+    0x100000L, 0x200000L, 0x400000L, 0x800000L,
+    0x1000000L, 0x2000000L, 0x4000000L, 0x8000000L,
+    0x10000000L, 0x20000000L, 0x40000000L, 0x80000000L
+  };
+  int idx;
+
+  for (idx = 0; idx < 32; idx++)
+    if (lit == pw[idx])
+      return idx + 1;
+  return 0;
+}
+
+
+/*-----------------------------------------------------------------*/
+/* genAnd  - code for and                                          */
+/*-----------------------------------------------------------------*/
+static void
+genAnd (iCode * ic, iCode * ifx)
+{
+  operand *left, *right, *result;
+  int size, offset = 0;
+  unsigned long long lit = 0ll;
+  unsigned long long litinv;
+  int bitpos = -1;
+  unsigned char bytemask;
+  bool needpulla = false;
+  bool earlystore = false;
+
+  emitComment (TRACEGEN, __func__);
+
+  aopOp ((left = IC_LEFT (ic)), ic, false);
+  aopOp ((right = IC_RIGHT (ic)), ic, false);
+  aopOp ((result = IC_RESULT (ic)), ic, true);
+
+  emitComment (TRACEGEN|VVDBG, "  Type res[%d] = l[%d]&r[%d]", AOP_TYPE (result), AOP_TYPE (left), AOP_TYPE (right));
+  emitComment (TRACEGEN|VVDBG, "  Size res[%d] = l[%d]&r[%d]", AOP_SIZE (result), AOP_SIZE (left), AOP_SIZE (right));
+
+  /* if left is a literal & right is not then exchange them */
+  if (AOP_TYPE (left) == AOP_LIT && AOP_TYPE (right) != AOP_LIT)
+    {
+      operand *tmp = right;
+      right = left;
+      left = tmp;
+    }
+
+  /* if right is accumulator & left is not then exchange them */
+  if (AOP_TYPE (right) == AOP_REG && ! IS_AOP_WITH_A (AOP (left)))
+    {
+      operand *tmp = right;
+      right = left;
+      left = tmp;
+    }
+
+  size = (AOP_SIZE (left) >= AOP_SIZE (right)) ? AOP_SIZE (left) : AOP_SIZE (right);
+
+  if (AOP_TYPE (right) == AOP_LIT)
+    {
+      lit = ullFromVal (AOP (right)->aopu.aop_lit);
+      if (size == 1)
+        lit &= 0xff;
+      else if (size == 2)
+        lit &= 0xffff;
+      else if (size == 4)
+        lit &= 0xffffffff;
+      else if (size == 8)
+        lit &= 0xffffffffffffffff;
+      bitpos = isLiteralBit (lit) - 1;
+    }
+
+  emitComment (TRACEGEN|VVDBG, "  lit=%04x bitpos=%d", lit, bitpos );
+  
+#if 0
+  if (IS_MOS65C02 && ifx && AOP_TYPE (result) == AOP_CRY && AOP_TYPE (right) == AOP_LIT && AOP_TYPE (left) == AOP_DIR && bitpos >= 0)
+    {
+      symbol *tlbl = NULL;
+      tlbl = safeNewiTempLabel (NULL);
+      if (IC_TRUE (ifx))
+        {
+	  // FIXME: unimplemented
+          emitcode ("brclr", "#%d,%s,%05d$", bitpos & 7, aopAdrStr (AOP (left), bitpos >> 3, false), safeLabelKey2num ((tlbl->key)));
+          emitBranch ("jmp", IC_TRUE (ifx));
+          safeEmitLabel (tlbl);
+          if (IC_FALSE (ifx))
+            emitBranch ("jmp", IC_FALSE (ifx));
+        }
+      else
+        {
+	  // FIXME: unimplemented
+          if (!regalloc_dry_run)
+            emitcode ("brset", "#%d,%s,%05d$", bitpos & 7, aopAdrStr (AOP (left), bitpos >> 3, false), safeLabelKey2num ((tlbl->key)));
+          emitBranch ("jmp", IC_FALSE (ifx));
+          safeEmitLabel (tlbl);
+        }
+      ifx->generated = true;
+      goto release;
+    }
+#endif
+
+/* TODO
+  if (AOP_TYPE (result) == AOP_CRY && size > 1 && (isOperandVolatile (left, false) || isOperandVolatile (right, false)))
+    {
+      needpulla = pushRegIfSurv (m6502_reg_a);
+
+      // this generates ugly code, but meets volatility requirements
+      loadRegFromConst (m6502_reg_a, 0);
+      pushReg (m6502_reg_a, true);
+
+      offset = 0;
+      while (size--)
+        {
+	  // FIXME: unimplemented
+          loadRegFromAop (m6502_reg_a, AOP (left), offset);
+          accopWithAop ("and", AOP (right), offset);
+          emitcode ("ora", "1,s");
+          emitcode ("sta", "1,s");
+          offset++;
+        }
+
+      pullReg (m6502_reg_a);
+      emit6502op ("cmp", "#0x00");
+
+      pullOrFreeReg (m6502_reg_a, needpulla);
+
+      genIfxJump (ifx, "a");
+
+      goto release;
+    }
+  */
+
+  #if 0
+  // special case for bit 7 and 6
+  if (AOP_TYPE (result) == AOP_CRY && AOP_TYPE (right) == AOP_LIT)
+    {
+      if (bitpos >= 0 && (bitpos & 7) == 7)
+        {
+          rmwWithAop ("bit", AOP (left), bitpos >> 3);
+          genIfxJump (ifx, "n");
+          goto release;
+        }
+      if (bitpos >= 0 && (bitpos & 7) == 6)
+        {
+          rmwWithAop ("bit", AOP (left), bitpos >> 3);
+          genIfxJump (ifx, "v");
+          goto release;
+        }
+    }
+  #endif
+
+  // test A for flags only
+  if (AOP_TYPE (result) == AOP_CRY && size == 1 && (IS_AOP_A (AOP (left)) || IS_AOP_A (AOP (right))))
+    {
+      if (IS_AOP_A (AOP (left)) && m6502_reg_a->isDead)
+        accopWithAop ("and", AOP (right), 0);
+      else if (IS_AOP_A (AOP (right)) && m6502_reg_a->isDead)
+        accopWithAop ("and", AOP (left), 0);
+      else if (IS_AOP_A (AOP (left)) && canBitOp(right))
+        accopWithAop ("bit", AOP (right), 0);
+      else if (IS_AOP_A (AOP (right)) && canBitOp(left))
+        accopWithAop ("bit", AOP (left), 0);
+      else {
+        storeRegTemp(m6502_reg_a, true);
+        loadRegFromAop (m6502_reg_a, IS_AOP_A(AOP(left)) ? AOP(right) : AOP(left), offset);
+        emit6502op ("bit", TEMPFMT, _G.tempOfs - 1);
+        loadRegTempNoFlags(m6502_reg_a, true); // preserve flags
+      }
+      genIfxJump (ifx, "a");
+      goto release;
+    }
+
+  // test for flags only (general case)
+  if (AOP_TYPE (result) == AOP_CRY)
+    {
+      symbol *tlbl = NULL;
+
+      needpulla = storeRegTempIfSurv (m6502_reg_a);
+
+      offset = 0;
+      while (size--)
+        {
+          bytemask = (lit >> (offset * 8)) & 0xff;
+
+          if (AOP_TYPE (right) == AOP_LIT && bytemask == 0)
+            {
+              /* do nothing */
+            }
+          else if (AOP_TYPE (right) == AOP_LIT && bytemask == 0xff)
+            {
+              // TODO: what if A? are flags set?
+              loadRegFromAop (m6502_reg_a, AOP(left), offset);
+              if (size)
+                {
+                  if (!tlbl)
+                    tlbl = safeNewiTempLabel (NULL);
+                  emitBranch ("bne", tlbl);
+                }
+            }
+          // don't clobber A (TODO: other ops?)
+          else if (IS_AOPOFS_A(AOP(right), offset))
+            {
+              accopWithAop ("and", AOP(left), offset);
+              m6502_freeReg (m6502_reg_a);
+              if (size)
+                {
+                  if (!tlbl)
+                    tlbl = safeNewiTempLabel (NULL);
+                  emitBranch ("bne", tlbl);
+                }
+            }
+          else if (IS_AOPOFS_A(AOP(left), offset))
+            {
+              accopWithAop ("and", AOP(right), offset);
+              m6502_freeReg (m6502_reg_a);
+              if (size)
+                {
+                  if (!tlbl)
+                    tlbl = safeNewiTempLabel (NULL);
+                  emitBranch ("bne", tlbl);
+                }
+            }
+          else
+            {
+              // TODO: fix other ops like this?
+              loadRegFromAop (m6502_reg_a, AOP(right), offset);
+              accopWithAop ("and", AOP(left), offset);
+              m6502_freeReg (m6502_reg_a);
+              if (size)
+                {
+                  if (!tlbl)
+                    tlbl = safeNewiTempLabel (NULL);
+                  emitBranch ("bne", tlbl);
+                }
+            }
+          offset++;
+        }
+      if (tlbl)
+        emitLabel (tlbl);
+
+      // TODO: better way to preserve flags?
+      if (ifx) {
+        loadRegTempNoFlags (m6502_reg_a, needpulla);
+        genIfxJump (ifx, "a");
+      } else {
+        if (needpulla) loadRegTemp (NULL);
+      }
+      goto release;
+    }
+
+  size = AOP_SIZE (result);
+
+  if (AOP_TYPE (right) == AOP_LIT && IS_MOS65C02)
+    {
+      litinv = (~lit) & (((unsigned int) 0xffffffff) >> (8 * (4 - size)));
+      if (sameRegs (AOP (IC_LEFT (ic)), AOP (IC_RESULT (ic))) && (AOP_TYPE (left) == AOP_DIR) && isLiteralBit (litinv))
+        {
+	  // FIXME: unimplemented
+          bitpos = isLiteralBit (litinv) - 1;
+          emitcode ("bclr", "#%d,%s", bitpos & 7, aopAdrStr (AOP (left), bitpos >> 3, false));
+          goto release;
+        }
+    }
+
+  needpulla = pushRegIfSurv (m6502_reg_a);
+
+  offset = 0;
+  if (size >= 2 && IS_AOP_AX (AOP (left)))
+    {
+      pushReg (m6502_reg_a, true);
+      earlystore = true;
+    }
+  while (size--)
+    {
+      bytemask = (lit >> (offset * 8)) & 0xff;
+
+      if (earlystore && offset == 1)
+        pullReg (m6502_reg_a);
+      if (AOP_TYPE (right) == AOP_LIT && bytemask == 0)
+        {
+          if (isOperandVolatile (left, false))
+            {
+              loadRegFromAop (m6502_reg_a, AOP (left), offset);
+              m6502_freeReg (m6502_reg_a);
+            }
+          storeConstToAop (0, AOP (result), offset);
+        }
+      else if (AOP_TYPE (right) == AOP_LIT && bytemask == 0xff)
+        {
+          transferAopAop (AOP (left), offset, AOP (result), offset);
+        }
+      else
+        {
+          loadRegFromAop (m6502_reg_a, AOP (left), offset);
+          accopWithAop ("and", AOP (right), offset);
+          storeRegToAop (m6502_reg_a, AOP (result), offset);
+          m6502_freeReg (m6502_reg_a);
+        }
+      if (AOP_TYPE (result) == AOP_REG && size && AOP (result)->aopu.aop_reg[offset]->rIdx == A_IDX)
+        {
+          pushReg (m6502_reg_a, true);
+          needpulla = true;
+        }
+      offset++;
+    }
+
+  pullOrFreeReg (m6502_reg_a, needpulla);
+
+release:
+  freeAsmop (left, NULL, ic, (RESULTONSTACK (ic) ? false : true));
+  freeAsmop (right, NULL, ic, (RESULTONSTACK (ic) ? false : true));
+  freeAsmop (result, NULL, ic, true);
+}
+
+/*-----------------------------------------------------------------*/
+/* genOr  - code for or                                            */
+/*-----------------------------------------------------------------*/
+static void
+genOr (iCode * ic, iCode * ifx)
+{
+  operand *left, *right, *result;
+  int size, offset = 0;
+  unsigned long long lit = 0ull;
+  unsigned char bytemask;
+  bool needpulla = false;
+  bool earlystore = false;
+
+  emitComment (TRACEGEN, __func__);
+
+  aopOp ((left = IC_LEFT (ic)), ic, false);
+  aopOp ((right = IC_RIGHT (ic)), ic, false);
+  aopOp ((result = IC_RESULT (ic)), ic, true);
+
+  emitComment (TRACEGEN|VVDBG, "  Type res[%d] = l[%d]&r[%d]", AOP_TYPE (result), AOP_TYPE (left), AOP_TYPE (right));
+  emitComment (TRACEGEN|VVDBG, "  Size res[%d] = l[%d]&r[%d]", AOP_SIZE (result), AOP_SIZE (left), AOP_SIZE (right));
+
+  /* if left is a literal & right is not then exchange them */
+  if (AOP_TYPE (left) == AOP_LIT && AOP_TYPE (right) != AOP_LIT)
+    {
+      operand *tmp = right;
+      right = left;
+      left = tmp;
+    }
+
+  /* if left is accumulator & right is not then exchange them */
+  if (AOP_TYPE (right) == AOP_REG && !IS_AOP_WITH_A (AOP (left)))
+    {
+      operand *tmp = right;
+      right = left;
+      left = tmp;
+    }
+
+  if (AOP_TYPE (right) == AOP_LIT)
+    lit = ullFromVal (AOP (right)->aopu.aop_lit);
+
+  size = (AOP_SIZE (left) >= AOP_SIZE (right)) ? AOP_SIZE (left) : AOP_SIZE (right);
+
+/* TODO
+  if (AOP_TYPE (result) == AOP_CRY && size > 1 && (isOperandVolatile (left, false) || isOperandVolatile (right, false)))
+    {
+      needpulla = pushRegIfSurv (m6502_reg_a);
+
+      // this generates ugly code, but meets volatility requirements 
+      loadRegFromConst (m6502_reg_a, 0);
+      storeRegTemp (m6502_reg_a, true);
+
+      offset = 0;
+      while (size--)
+        {
+	  // FIXME: unimplemented
+          loadRegFromAop (m6502_reg_a, AOP (left), offset);
+          accopWithAop ("ora", AOP (right), offset);
+          emitcode ("ora", "1,s"); // TODO :P
+          emitcode ("sta", "1,s");
+          offset++;
+        }
+
+      loadRegTemp (m6502_reg_a);
+      emit6502op ("cmp", "#0x00");
+
+      pullOrFreeRegNoFlags (m6502_reg_a, needpulla);
+
+      genIfxJump (ifx, "a");
+
+      goto release;
+    }
+*/    
+  // TODO: (x | const) should always be known result
+
+  if (AOP_TYPE (result) == AOP_CRY)
+    {
+      symbol *tlbl = NULL;
+
+      needpulla = storeRegTempIfSurv (m6502_reg_a);
+
+      offset = 0;
+      while (size--)
+        {
+          bytemask = (lit >> (offset * 8)) & 0xff;
+
+          if (AOP_TYPE (right) == AOP_LIT && bytemask == 0x00)
+            {
+              loadRegFromAop (m6502_reg_a, AOP (left), offset);
+              if (size)
+                {
+                  if (!tlbl)
+                    tlbl = safeNewiTempLabel (NULL);
+                  emitBranch ("bne", tlbl);
+                }
+            }
+          else
+            {
+              loadRegFromAop (m6502_reg_a, AOP (left), offset);
+              accopWithAop ("ora", AOP (right), offset);
+              m6502_freeReg (m6502_reg_a);
+              if (size)
+                {
+                  if (!tlbl)
+                    tlbl = safeNewiTempLabel (NULL);
+                  emitBranch ("bne", tlbl);
+                }
+            }
+          offset++;
+        }
+      if (tlbl)
+        emitLabel (tlbl);
+
+
+      if (ifx) {
+        loadRegTempNoFlags (m6502_reg_a, needpulla);
+        genIfxJump (ifx, "a");
+      } else {
+        if (needpulla) loadRegTemp (NULL);
+      }
+
+      goto release;
+    }
+
+  if (AOP_TYPE (right) == AOP_LIT)
+    lit = ullFromVal (AOP (right)->aopu.aop_lit);
+
+  size = AOP_SIZE (result);
+
+  if (IS_MOS65C02 && sameRegs (AOP (IC_LEFT (ic)), AOP (IC_RESULT (ic))) &&
+      (AOP_TYPE (right) == AOP_LIT) && isLiteralBit (lit) && (AOP_TYPE (left) == AOP_DIR))
+    {
+      // FIXME: unimplemented
+      int bitpos = isLiteralBit (lit) - 1;
+      emitcode ("bset", "#%d,%s", bitpos & 7, aopAdrStr (AOP (left), bitpos >> 3, false));
+      goto release;
+    }
+
+  needpulla = pushRegIfSurv (m6502_reg_a);
+
+  offset = 0;
+  if (size >= 2 && IS_AOP_AX (AOP (left)))
+    {
+      pushReg (m6502_reg_a, true);
+      earlystore = true;
+    }
+  while (size--)
+    {
+      bytemask = (lit >> (offset * 8)) & 0xff;
+
+      if (earlystore && offset == 1)
+        pullReg (m6502_reg_a);
+      if (AOP_TYPE (right) == AOP_LIT && bytemask == 0xff)
+        {
+          if (isOperandVolatile (left, false))
+            {
+              loadRegFromAop (m6502_reg_a, AOP (left), offset);
+              m6502_freeReg (m6502_reg_a);
+            }
+          transferAopAop (AOP (right), offset, AOP (result), offset);
+        }
+      else if (AOP_TYPE (right) == AOP_LIT && bytemask == 0)
+        {
+          transferAopAop (AOP (left), offset, AOP (result), offset);
+        }
+      else
+        {
+          loadRegFromAop (m6502_reg_a, AOP (left), offset);
+          accopWithAop ("ora", AOP (right), offset);
+          storeRegToAop (m6502_reg_a, AOP (result), offset);
+          m6502_freeReg (m6502_reg_a);
+        }
+      if (AOP_TYPE (result) == AOP_REG && size && AOP (result)->aopu.aop_reg[offset]->rIdx == A_IDX)
+        {
+          pushReg (m6502_reg_a, true);
+          needpulla = true;
+        }
+      offset++;
+    }
+
+  pullOrFreeReg (m6502_reg_a, needpulla);
+
+release:
+  freeAsmop (left, NULL, ic, (RESULTONSTACK (ic) ? false : true));
+  freeAsmop (right, NULL, ic, (RESULTONSTACK (ic) ? false : true));
+  freeAsmop (result, NULL, ic, true);
+}
+
+/*-----------------------------------------------------------------*/
+/* genXor - code for Exclusive or                                  */
+/*-----------------------------------------------------------------*/
+static void
+genXor (iCode * ic, iCode * ifx)
+{
+  operand *left, *right, *result;
+  int size, offset = 0;
+  bool needpulla = false;
+  bool earlystore = false;
+
+  emitComment (TRACEGEN, __func__);
+
+  aopOp ((left = IC_LEFT (ic)), ic, false);
+  aopOp ((right = IC_RIGHT (ic)), ic, false);
+  aopOp ((result = IC_RESULT (ic)), ic, true);
+
+  emitComment (TRACEGEN|VVDBG, " Type res[%d] = l[%d]&r[%d]", AOP_TYPE (result), AOP_TYPE (left), AOP_TYPE (right));
+  emitComment (TRACEGEN|VVDBG, " Size res[%d] = l[%d]&r[%d]", AOP_SIZE (result), AOP_SIZE (left), AOP_SIZE (right));
+
+  /* if left is a literal & right is not ||
+     if left needs acc & right does not */
+  if (AOP_TYPE (left) == AOP_LIT && AOP_TYPE (right) != AOP_LIT)
+    {
+      operand *tmp = right;
+      right = left;
+      left = tmp;
+    }
+
+  /* if left is accumulator & right is not then exchange them */
+  if (AOP_TYPE (right) == AOP_REG && !IS_AOP_WITH_A (AOP (left)))
+    {
+      operand *tmp = right;
+      right = left;
+      left = tmp;
+    }
+
+  needpulla = storeRegTempIfSurv (m6502_reg_a);
+
+  if (AOP_TYPE (result) == AOP_CRY)
+    {
+      symbol *tlbl;
+
+      tlbl = safeNewiTempLabel (NULL);
+      size = (AOP_SIZE (left) >= AOP_SIZE (right)) ? AOP_SIZE (left) : AOP_SIZE (right);
+      offset = 0;
+      while (size--)
+        {
+          loadRegFromAop (m6502_reg_a, AOP (left), offset);
+          if (AOP_TYPE (right) == AOP_LIT && ((ullFromVal (AOP (right)->aopu.aop_lit) >> (offset * 8)) & 0xff) == 0)
+            {
+              emit6502op ("cmp", "#0x00");
+            }
+          else
+            accopWithAop ("eor", AOP (right), offset);
+
+          m6502_freeReg (m6502_reg_a);
+          if (size)
+            emitBranch ("bne", tlbl);
+          else
+            {
+              /*
+               * I think this is all broken here, (see simulation mismatch in bug1875933.c)
+               *   multiple calls to emitLabel() ?!
+               * and we can't genIfxJump, if there is none
+               */
+              safeEmitLabel (tlbl);
+              if (ifx) {
+                loadRegTempNoFlags (m6502_reg_a, needpulla);
+                genIfxJump (ifx, "a");
+              } else {
+                if (needpulla) loadRegTemp (NULL);
+              }
+            }
+          offset++;
+        }
+      goto release;
+    }
+
+  size = AOP_SIZE (result);
+  offset = 0;
+  // TODO?
+  if (size >= 2 && IS_AOP_AX (AOP (left)))
+    {
+      pushReg (m6502_reg_a, true);
+      earlystore = true;
+    }
+  while (size--)
+    {
+      if (earlystore && offset == 1)
+        pullReg (m6502_reg_a);
+      loadRegFromAop (m6502_reg_a, AOP (left), offset);
+      accopWithAop ("eor", AOP (right), offset);
+      storeRegToAop (m6502_reg_a, AOP (result), offset);
+      if (AOP_TYPE (result) == AOP_REG && size && AOP (result)->aopu.aop_reg[offset]->rIdx == A_IDX)
+        {
+          storeRegTemp (m6502_reg_a, true);
+          needpulla = true;
+        }
+      m6502_freeReg (m6502_reg_a);
+      offset++;
+    }
+// FIXME: check for loadOrFree
+  loadOrFreeRegTemp (m6502_reg_a, needpulla);
+
+release:
+
+  freeAsmop (left, NULL, ic, (RESULTONSTACK (ic) ? false : true));
+  freeAsmop (right, NULL, ic, (RESULTONSTACK (ic) ? false : true));
+  freeAsmop (result, NULL, ic, true);
+}
+
+static const char *
+expand_symbols (iCode * ic, const char *inlin)
+{
+  const char *begin = NULL, *p = inlin;
+  bool inIdent = false;
+  struct dbuf_s dbuf;
+
+  dbuf_init (&dbuf, 128);
+
+  while (*p)
+    {
+      if (inIdent)
+        {
+          if ('_' == *p || isalnum (*p))
+            /* in the middle of identifier */
+            ++p;
+          else
+            {
+              /* end of identifier */
+              symbol *sym, *tempsym;
+              char *symname = Safe_strndup (p + 1, p - begin - 1);
+
+              inIdent = 0;
+
+              tempsym = newSymbol (symname, ic->level);
+              tempsym->block = ic->block;
+              sym = (symbol *) findSymWithLevel (SymbolTab, tempsym);
+              if (!sym)
+                {
+                  dbuf_append (&dbuf, begin, p - begin);
+                }
+              else
+                {
+                  asmop *aop = aopForSym (ic, sym, false);
+                  const char *l = aopAdrStr (aop, aop->size - 1, true);
+
+                  if ('#' == *l)
+                    l++;
+                  sym->isref = 1;
+                  if (sym->level && !sym->allocreq && !sym->ismyparm)
+                    {
+                      werror (E_ID_UNDEF, sym->name);
+                      werror (W_CONTINUE,
+                              "  Add 'volatile' to the variable declaration so that it\n"
+                              "  can be referenced within inline assembly");
+                    }
+                  dbuf_append_str (&dbuf, l);
+                }
+              Safe_free (symname);
+              begin = p++;
+            }
+        }
+      else if ('_' == *p)
+        {
+          /* begin of identifier */
+          inIdent = true;
+          if (begin)
+            dbuf_append (&dbuf, begin, p - begin);
+          begin = p++;
+        }
+      else
+        {
+          if (!begin)
+            begin = p;
+          p++;
+        }
+    }
+
+  if (begin)
+    dbuf_append (&dbuf, begin, p - begin);
+
+  return dbuf_detach_c_str (&dbuf);
+}
+
+/*-----------------------------------------------------------------*/
+/* genInline - write the inline code out                           */
+/*-----------------------------------------------------------------*/
+static void
+m6502_genInline (iCode * ic)
+{
+  char *buf, *bp, *begin;
+  const char *expanded;
+  bool inComment = false;
+
+  emitComment (TRACEGEN, __func__);
+
+  genLine.lineElement.isInline += (!options.asmpeep);
+
+  buf = bp = begin = Safe_strdup (IC_INLINE (ic));
+
+  /* emit each line as a code */
+  while (*bp)
+    {
+      switch (*bp)
+        {
+        case ';':
+          inComment = true;
+          ++bp;
+          break;
+
+        case '\x87':
+        case '\n':
+          inComment = false;
+          *bp++ = '\0';
+          expanded = expand_symbols (ic, begin);
+          emitcode (expanded, NULL);
+          dbuf_free (expanded);
+          begin = bp;
+          break;
+
+        default:
+          /* Add \n for labels, not dirs such as c:\mydir */
+          if (!inComment && (*bp == ':') && (isspace ((unsigned char) bp[1])))
+            {
+              ++bp;
+              *bp = '\0';
+              ++bp;
+              emitcode (begin, NULL);
+              begin = bp;
+            }
+          else
+            ++bp;
+          break;
+        }
+    }
+  if (begin != bp)
+    {
+      expanded = expand_symbols (ic, begin);
+      emitcode (expanded, NULL);
+      dbuf_free (expanded);
+    }
+
+  Safe_free (buf);
+
+  /* consumed; we can free it here */
+  dbuf_free (IC_INLINE (ic));
+
+  genLine.lineElement.isInline -= (!options.asmpeep);
+}
+
+// TODO: are these called?
+/*-----------------------------------------------------------------*/
+/* genRRC - rotate right with carry                                */
+/*-----------------------------------------------------------------*/
+static void
+genRRC (iCode * ic)
+{
+  operand *left, *result;
+  int size, offset = 0;
+  bool needpula = false;
+  bool resultInA = false;
+  char *shift;
+
+  emitComment (TRACEGEN, __func__);
+
+  /* rotate right with carry */
+  left = IC_LEFT (ic);
+  result = IC_RESULT (ic);
+  aopOp (left, ic, false);
+  aopOp (result, ic, false);
+
+  if ((AOP_TYPE (result) == AOP_REG) && (AOP (result)->aopu.aop_reg[0]->rIdx == A_IDX))
+    resultInA = true;
+
+  size = AOP_SIZE (result);
+  offset = size - 1;
+
+  shift = "lsr";
+  if (sameRegs (AOP (IC_LEFT (ic)), AOP (IC_RESULT (ic))))
+    {
+      while (size--)
+        {
+          rmwWithAop (shift, AOP (result), offset--);
+          shift = "ror";
+        }
+    }
+  else
+    {
+      while (size--)
+        {
+          loadRegFromAop (m6502_reg_a, AOP (left), offset);
+          rmwWithReg (shift, m6502_reg_a);
+          storeRegToAop (m6502_reg_a, AOP (result), offset--);
+          m6502_freeReg (m6502_reg_a);
+          shift = "ror";
+        }
+    }
+
+  if ((!m6502_reg_a->isFree) || resultInA)
+    {
+      pushReg (m6502_reg_a, true);
+      needpula = true;
+    }
+
+  /* now we need to put the carry into the
+     highest order byte of the result */
+  offset = AOP_SIZE (result) - 1;
+  loadRegFromConst(m6502_reg_a, 0);
+  emit6502op ("ror", "a");
+  if (resultInA)
+    {
+      // FIXME: unimplemented
+      emitcode ("ora10", "1,s");
+      pullNull (1);
+      m6502_dirtyReg (m6502_reg_a);
+      needpula = false;
+    }
+  else
+    accopWithAop ("ora", AOP (result), offset);
+  storeRegToAop (m6502_reg_a, AOP (result), offset);
+
+  pullOrFreeReg (m6502_reg_a, needpula);
+
+  freeAsmop (left, NULL, ic, true);
+  freeAsmop (result, NULL, ic, true);
+}
+
+/*-----------------------------------------------------------------*/
+/* genRLC - generate code for rotate left with carry               */
+/*-----------------------------------------------------------------*/
+static void
+genRLC (iCode * ic)
+{
+  operand *left, *result;
+  int size, offset = 0;
+  char *shift;
+  bool resultInA = false;
+  bool needpula = false;
+
+  emitComment (TRACEGEN, __func__);
+
+  /* rotate right with carry */
+  left = IC_LEFT (ic);
+  result = IC_RESULT (ic);
+  aopOp (left, ic, false);
+  aopOp (result, ic, false);
+
+  if ((AOP_TYPE (result) == AOP_REG) && (AOP (result)->aopu.aop_reg[0]->rIdx == A_IDX))
+    resultInA = true;
+
+  size = AOP_SIZE (result);
+  offset = 0;
+
+  shift = "asl";
+  if (sameRegs (AOP (IC_LEFT (ic)), AOP (IC_RESULT (ic))))
+    {
+      while (size--)
+        {
+          rmwWithAop (shift, AOP (result), offset++);
+          shift = "rol";
+        }
+    }
+  else
+    {
+      while (size--)
+        {
+          loadRegFromAop (m6502_reg_a, AOP (left), offset);
+          rmwWithReg (shift, m6502_reg_a);
+          storeRegToAop (m6502_reg_a, AOP (result), offset++);
+          m6502_freeReg (m6502_reg_a);
+          shift = "rol";
+        }
+    }
+
+  if ((!m6502_reg_a->isFree) || resultInA)
+    {
+      pushReg (m6502_reg_a, true);
+      needpula = true;
+    }
+
+  /* now we need to put the carry into the
+     lowest order byte of the result */
+  offset = 0;
+  loadRegFromConst(m6502_reg_a, 0);
+  emit6502op ("rol", "a");
+  if (resultInA)
+    {
+      // FIXME: unimplemented
+      emitcode ("ora11", "1,s");
+      pullNull (1);
+      m6502_dirtyReg (m6502_reg_a);
+      needpula = false;
+    }
+  else
+    accopWithAop ("ora", AOP (result), offset);
+  storeRegToAop (m6502_reg_a, AOP (result), offset);
+
+  pullOrFreeReg (m6502_reg_a, needpula);
+
+  freeAsmop (left, NULL, ic, true);
+  freeAsmop (result, NULL, ic, true);
+}
+
+/*-----------------------------------------------------------------*/
+/* AccLsh - left shift accumulator by known count                  */
+/*-----------------------------------------------------------------*/
+static void
+AccLsh (int shCount)
+{
+  int i;
+
+  shCount &= 0x0007;            // shCount : 0..7
+
+  /* For shift counts of 6 and 7, the unrolled loop is never optimal.      */
+  switch (shCount)
+    {
+    case 6:
+      emit6502op ("ror", "a");
+      emit6502op ("ror", "a");
+      emit6502op ("ror", "a");
+      emit6502op ("and", "#0xc0");
+      /* total: 8 cycles, 5 bytes */
+      return;
+    case 7:
+      emit6502op ("ror", "a");
+      loadRegFromConst(m6502_reg_a, 0);
+      emit6502op ("ror", "a");
+      /* total: 6 cycles, 4 bytes */
+      return;
+    }
+
+  /* asl a is 2 cycles and 1 byte, so an unrolled loop is the   */
+  /* fastest and shortest (shCount<6).                            */
+  for (i = 0; i < shCount; i++)
+    emit6502op ("asl", "a");
+}
+
+
+/*-----------------------------------------------------------------*/
+/* AccSRsh - signed right shift accumulator by known count         */
+/*-----------------------------------------------------------------*/
+static void
+AccSRsh (int shCount)
+{
+  int i;
+
+  shCount &= 0x0007;            // shCount : 0..7
+
+  if (shCount == 7)
+    {
+      emit6502op ("rol", "a");
+      loadRegFromConst(m6502_reg_a, 0);
+      emit6502op ("adc", "#0xff");
+      emit6502op ("eor", "#0xff");
+      return;
+    }
+  if (shCount == 6) {
+      symbol *tlbl = safeNewiTempLabel (NULL);
+      emit6502op ("ora", "#0x3f");
+      emit6502op ("sec", "");
+      emit6502op ("bmi", "%05d$", safeLabelKey2num (tlbl->key));
+      emit6502op ("and", "#0xc0");
+      emit6502op ("clc", "");
+      safeEmitLabel(tlbl);
+      emit6502op ("rol", "a");
+      emit6502op ("rol", "a");
+      emit6502op ("rol", "a");
+      return;
+  }
+  // TODO: optimize? (asr?)
+  for (i = 0; i < shCount; i++) {
+    emit6502op ("cmp", "#0x80");
+    emit6502op ("ror", "a");
+  }
+}
+
+/*-----------------------------------------------------------------*/
+/* AccRsh - right shift accumulator by known count                 */
+/*-----------------------------------------------------------------*/
+static void
+AccRsh (int shCount, bool sign)
+{
+  int i;
+
+  if (sign)
+    {
+      AccSRsh (shCount);
+      return;
+    }
+
+  shCount &= 0x0007;            // shCount : 0..7
+
+  /* For shift counts of 6 and 7, the unrolled loop is never optimal.      */
+  switch (shCount)
+    {
+    case 6:
+      emit6502op ("rol", "a");
+      emit6502op ("rol", "a");
+      emit6502op ("rol", "a");
+      emit6502op ("and", "#0x03");
+      /* total: 8 cycles, 5 bytes */
+      return;
+    case 7:
+      emit6502op ("rol", "a");
+      loadRegFromConst(m6502_reg_a, 0);
+      emit6502op ("rol", "a");
+      /* total: 6 cycles, 4 bytes */
+      return;
+    }
+
+  /* lsra is 2 cycles and 1 byte, so an unrolled loop is the      */
+  /* the fastest and shortest (shCount<6).            */
+  for (i = 0; i < shCount; i++)
+    emit6502op ("lsr", "a");
+}
+
+
+/*-----------------------------------------------------------------*/
+/* XAccLsh - left shift register pair XA by known count            */
+/*-----------------------------------------------------------------*/
+static void
+XAccLsh (int shCount)
+{
+  int i;
+
+  shCount &= 0x000f;            // shCount : 0..15
+
+  if (shCount >= 8)
+    {
+      AccLsh (shCount - 8);
+      transferRegReg (m6502_reg_a, m6502_reg_x, false);
+      loadRegFromConst (m6502_reg_a, 0);
+      return;
+    }
+
+  /* if we can beat 2n cycles or bytes for some special case, do it here */
+  switch (shCount)
+    {
+    case 7:
+      storeRegTemp(m6502_reg_x, true);
+      emit6502op ("lsr", TEMPFMT, _G.tempOfs - 1);
+      dirtyRegTemp(_G.tempOfs - 1);
+      rmwWithReg ("ror", m6502_reg_a);
+      transferRegReg (m6502_reg_a, m6502_reg_x, false);
+      loadRegFromConst (m6502_reg_a, 0);
+      rmwWithReg ("ror", m6502_reg_a);
+      loadRegTemp(NULL);
+      return;
+    case 0:
+      return;
+    default:
+  /* lsla/rolx is only 2 cycles and bytes, so an unrolled loop is often  */
+  /* the fastest and shortest.                                           */
+      storeRegTemp(m6502_reg_x, true);
+
+  for (i = 0; i < shCount; i++)
+    {
+      rmwWithReg ("asl", m6502_reg_a);
+      emit6502op ("rol", TEMPFMT, _G.tempOfs - 1);
+      dirtyRegTemp(_G.tempOfs - 1);
+    }
+  loadRegTemp(m6502_reg_x);
+
+    }
+}
+
+/*-----------------------------------------------------------------*/
+/* XAccSRsh - signed right shift register pair XA by known count   */
+/*-----------------------------------------------------------------*/
+static void
+XAccSRsh (int shCount)
+{
+  symbol *tlbl;
+  int i;
+
+  shCount &= 0x000f;            // shCount : 0..7
+
+  /* if we can beat 2n cycles or bytes for some special case, do it here */
+  switch (shCount) // TODO
+    {
+    case 15:
+    case 14:
+    case 13:
+    case 12:
+    case 11:
+    case 10:
+    case 9:
+      transferRegReg (m6502_reg_x, m6502_reg_a, false);
+      loadRegFromConst (m6502_reg_x, 0);
+      AccSRsh (shCount - 8);
+      tlbl = safeNewiTempLabel (NULL);
+      emit6502op ("bpl", "%05d$", safeLabelKey2num (tlbl->key));
+      loadRegFromConst (m6502_reg_x, 0xff);
+      safeEmitLabel(tlbl);
+      break;
+    case 8:
+      transferRegReg (m6502_reg_x, m6502_reg_a, false);
+      loadRegFromConst (m6502_reg_x, 0);
+      emit6502op("cmp","#0x00");
+      tlbl = safeNewiTempLabel (NULL);
+      emit6502op ("bpl", "%05d$", safeLabelKey2num (tlbl->key));
+      loadRegFromConst (m6502_reg_x, 0xff);
+      safeEmitLabel(tlbl);
+      break;
+
+    default:
+      /* asrx/rora is only 2 cycles and bytes, so an unrolled loop is often  */
+      /* the fastest and shortest.                                           */
+      storeRegTemp(m6502_reg_x, true);
+      for (i = 0; i < shCount; i++)
+        {
+          // TODO: this is so bad
+          emit6502op ("cpx", "#0x80");
+          emit6502op ("ror", TEMPFMT, _G.tempOfs - 1);
+          dirtyRegTemp(_G.tempOfs - 1);
+          rmwWithReg ("ror", m6502_reg_a);
+        }
+      loadRegTemp(m6502_reg_x);
+    }
+}
+
+/*-----------------------------------------------------------------*/
+/* XAccRsh - right shift register pair XA by known count           */
+/*-----------------------------------------------------------------*/
+static void
+XAccRsh (int shCount, bool sign)
+{
+  int i;
+
+  if (sign)
+    {
+      XAccSRsh (shCount);
+      return;
+    }
+
+  shCount &= 0x000f;            // shCount : 0..f
+
+  /* if we can beat 2n cycles or bytes for some special case, do it here */
+ switch (shCount)
+   {
+    case 15:
+    case 14:
+    case 13:
+    case 12:
+    case 11:
+    case 10:
+    case 9:
+    case 8:
+      transferRegReg(m6502_reg_x, m6502_reg_a, true);
+      AccRsh (shCount - 8, false);
+      loadRegFromConst (m6502_reg_x, 0);
+      break;
+    case 7:
+      storeRegTemp(m6502_reg_x, true);
+      rmwWithReg ("rol", m6502_reg_a);
+      emit6502op ("rol", TEMPFMT, _G.tempOfs - 1);
+      dirtyRegTemp(_G.tempOfs - 1);
+      loadRegFromConst (m6502_reg_a, 0);
+      rmwWithReg ("rol", m6502_reg_a);
+      transferRegReg(m6502_reg_a, m6502_reg_x, true);
+      loadRegTemp(m6502_reg_a);
+      break;
+    case 0:
+      break;
+    default:
+      /* lsrx/rora is only 2 cycles and bytes, so an unrolled loop is often  */
+      /* the fastest and shortest.                                           */
+      storeRegTemp(m6502_reg_x, true);
+      for (i = 0; i < shCount; i++)
+        {
+          emit6502op ("lsr", TEMPFMT, _G.tempOfs - 1);
+          dirtyRegTemp(_G.tempOfs - 1);
+          rmwWithReg ("ror", m6502_reg_a);
+        }
+      loadRegTemp(m6502_reg_x);
+  }
+}
+
+
+/*-----------------------------------------------------------------*/
+/* shiftL1Left2Result - shift left one byte from left to result    */
+/*-----------------------------------------------------------------*/
+static void
+shiftL1Left2Result (operand * left, int offl, operand * result, int offr, int shCount)
+{
+  // TODO: shift > 2?
+  if (sameRegs (AOP (left), AOP (result)) && aopCanShift(AOP(left)) && offr == offl)
+    {
+      while (shCount--)
+        rmwWithAop ("asl", AOP (result), 0);
+    }
+  else
+    {
+      bool needpulla = pushRegIfSurv (m6502_reg_a);
+      loadRegFromAop (m6502_reg_a, AOP (left), offl);
+      /* shift left accumulator */
+      AccLsh (shCount);
+      storeRegToAop (m6502_reg_a, AOP (result), offr);
+      pullOrFreeReg (m6502_reg_a, needpulla);
+    }
+}
+
+/*-----------------------------------------------------------------*/
+/* movLeft2Result - move byte from left to result                  */
+/*-----------------------------------------------------------------*/
+static void
+movLeft2Result (operand * left, int offl, operand * result, int offr, int sign)
+{
+  if (!sameRegs (AOP (left), AOP (result)) || (offl != offr))
+    {
+      transferAopAop (AOP (left), offl, AOP (result), offr);
+    }
+}
+
+
+/*-----------------------------------------------------------------*/
+/* shiftL2Left2Result - shift left two bytes from left to result   */
+/*-----------------------------------------------------------------*/
+static void
+shiftL2Left2Result (operand * left, int offl, operand * result, int offr, int shCount)
+{
+  int i;
+  bool needpula = false;
+  bool needpulx = false;
+
+  if (!IS_AOP_XA (AOP (left)) && !IS_AOP_A (AOP (left)))
+    needpula = pushRegIfUsed (m6502_reg_a);
+  else
+    needpula = false;
+  if (!IS_AOP_XA (AOP (left)))
+    needpulx = pushRegIfUsed (m6502_reg_x);
+  else
+    needpulx = false;
+
+  loadRegFromAop (m6502_reg_xa, AOP (left), offl);
+
+  switch (shCount)
+    {
+    case 7:
+      rmwWithReg ("lsr", m6502_reg_x);
+      rmwWithReg ("ror", m6502_reg_a);
+      transferRegReg (m6502_reg_a, m6502_reg_x, false);
+      loadRegFromConst (m6502_reg_a, 0);
+      rmwWithReg ("ror", m6502_reg_a);
+      break;
+    default:
+      for (i = 0; i < shCount; i++)
+        {
+          rmwWithReg ("asl", m6502_reg_a);
+          rmwWithReg ("rol", m6502_reg_x);
+        }
+    }
+  storeRegToAop (m6502_reg_xa, AOP (result), offr);
+
+  pullOrFreeReg (m6502_reg_x, needpulx);
+  pullOrFreeReg (m6502_reg_a, needpula);
+
+}
+
+
+
+/*-----------------------------------------------------------------*/
+/* shiftRLeftOrResult - shift right one byte from left,or to result */
+/*-----------------------------------------------------------------*/
+static void
+shiftRLeftOrResult (operand * left, int offl, operand * result, int offr, int shCount)
+{
+  loadRegFromAop (m6502_reg_a, AOP (left), offl);
+  /* shift left accumulator */
+  AccRsh (shCount, false);
+  /* or with result */
+  accopWithAop ("ora", AOP (result), offr);
+  /* back to result */
+  storeRegToAop (m6502_reg_a, AOP (result), offr);
+  m6502_freeReg (m6502_reg_a);
+}
+
+/*-----------------------------------------------------------------*/
+/* genlshOne - left shift a one byte quantity by known count       */
+/*-----------------------------------------------------------------*/
+static void
+genlshOne (operand * result, operand * left, int shCount)
+{
+  emitComment (TRACEGEN, __func__);
+
+  shiftL1Left2Result (left, LSB, result, LSB, shCount);
+}
+
+/*-----------------------------------------------------------------*/
+/* genlshTwo - left shift two bytes by known amount != 0           */
+/*-----------------------------------------------------------------*/
+static void
+genlshTwo (operand * result, operand * left, int shCount)
+{
+  bool needpulla, needpullx;
+
+  emitComment (TRACEGEN, __func__);
+
+  /* if shCount >= 8 */
+  if (shCount >= 8)
+    {
+      shCount -= 8;
+      // TODO
+      needpulla = pushRegIfSurv (m6502_reg_a);
+          loadRegFromAop (m6502_reg_a, AOP (left), 0);
+          AccLsh (shCount);
+          storeRegToAop (m6502_reg_a, AOP (result), 1);
+      storeConstToAop (0, AOP (result), LSB);
+      pullOrFreeReg (m6502_reg_a, needpulla);
+    }
+  /*  1 <= shCount <= 7 */
+  // TODO: count > 2 efficient?
+  else if (sameRegs (AOP (left), AOP (result)) && aopCanShift(AOP(result)) && shCount <= 4)
+    {
+      while (shCount--) {
+        rmwWithAop ("asl", AOP (result), 0);
+        rmwWithAop ("rol", AOP (result), 1);
+      }
+    }
+  else
+    {
+      needpulla = storeRegTempIfSurv (m6502_reg_a);
+      needpullx = storeRegTempIfSurv (m6502_reg_x);
+      loadRegFromAop (m6502_reg_xa, AOP (left), 0);
+      XAccLsh (shCount);
+      storeRegToFullAop (m6502_reg_xa, AOP (result), 0);
+// FIXME: check for loadOrFree
+      loadOrFreeRegTemp (m6502_reg_x, needpullx);
+      loadOrFreeRegTemp (m6502_reg_a, needpulla);
+    }
+}
+
+/*-----------------------------------------------------------------*/
+/* shiftLLong - shift left one long from left to result            */
+/* offr = LSB or MSB16                                             */
+/*-----------------------------------------------------------------*/
+static void
+shiftLLong (operand * left, operand * result, int offr)
+{
+  bool needpulla = false;
+  bool needloadx = false;
+
+  needpulla = pushRegIfUsed (m6502_reg_a);
+
+  switch(offr) {
+  case LSB:
+    loadRegFromAop (m6502_reg_a, AOP (left), 0);
+    rmwWithReg ("asl", m6502_reg_a);
+    storeRegToAop (m6502_reg_a, AOP (result), 0);
+    loadRegFromAop (m6502_reg_a, AOP (left), 1);
+    rmwWithReg ("rol", m6502_reg_a);
+    storeRegToAop (m6502_reg_a, AOP (result), 1);
+    loadRegFromAop (m6502_reg_a, AOP (left), 2);
+    rmwWithReg ("rol", m6502_reg_a);
+    storeRegToAop (m6502_reg_a, AOP (result), 2);
+    loadRegFromAop (m6502_reg_a, AOP (left), 3);
+    rmwWithReg ("rol", m6502_reg_a);
+    storeRegToAop (m6502_reg_a, AOP (result), 3);
+    break;
+  case MSB16:
+    needloadx = storeRegTempIfUsed (m6502_reg_x);
+    loadRegFromAop (m6502_reg_a, AOP (left), 0);
+    rmwWithReg ("asl", m6502_reg_a);
+    loadRegFromAop (m6502_reg_x, AOP (left), 1);
+    storeRegToAop (m6502_reg_a, AOP (result), 1);
+    transferRegReg (m6502_reg_x, m6502_reg_a, true);
+    rmwWithReg ("rol", m6502_reg_a);
+    loadRegFromAop (m6502_reg_x, AOP (left), 2);
+    storeRegToAop (m6502_reg_a, AOP (result), 2);
+    transferRegReg (m6502_reg_x, m6502_reg_a, true);
+    rmwWithReg ("rol", m6502_reg_a);
+    storeRegToAop (m6502_reg_a, AOP (result), 3);
+    storeConstToAop (0, AOP (result), 0);    
+    break;
+  }
+    
+  loadOrFreeRegTemp (m6502_reg_x, needloadx);
+  pullOrFreeReg (m6502_reg_a, needpulla);
+}
+
+/*-----------------------------------------------------------------*/
+/* genlshFour - shift four byte by a known amount != 0             */
+/*-----------------------------------------------------------------*/
+static void
+genlshFour (operand * result, operand * left, int shCount)
+{
+  emitComment (TRACEGEN, __func__);
+  emitComment (TRACEGEN, "  %s - shift=%d", __func__, shCount);
+
+  if(AOP_SIZE (result)!=4) abort();
+
+  /* TODO: deal with the &result == &left case */
+
+  /* if shifting more that 3 bytes */
+  if (shCount >= 24)
+    {
+      shCount -= 24;
+      if (shCount)
+        /* lowest order of left goes to the highest
+           order of the destination */
+        shiftL1Left2Result (left, LSB, result, MSB32, shCount);
+      else
+        movLeft2Result (left, LSB, result, MSB32, 0);
+      storeConstToAop (0, AOP (result), LSB);
+      storeConstToAop (0, AOP (result), MSB16);
+      storeConstToAop (0, AOP (result), MSB24);
+      return;
+    }
+
+  /* more than two bytes */
+  else if (shCount >= 16)
+    {
+      /* lower order two bytes goes to higher order two bytes */
+      shCount -= 16;
+      /* if some more remaining */
+      if (shCount)
+        shiftL2Left2Result (left, LSB, result, MSB24, shCount);
+      else
+        {
+          movLeft2Result (left, MSB16, result, MSB32, 0);
+          movLeft2Result (left, LSB, result, MSB24, 0);
+        }
+      storeConstToAop (0, AOP (result), LSB);
+      storeConstToAop (0, AOP (result), MSB16);
+      return;
+    }
+
+  /* if more than 1 byte */
+  else if (shCount >= 8)
+    {
+      /* lower order three bytes goes to higher order  three bytes */
+      shCount -= 8;
+      if (shCount == 0)
+        {
+          movLeft2Result (left, MSB24, result, MSB32, 0);
+          movLeft2Result (left, MSB16, result, MSB24, 0);
+          movLeft2Result (left, LSB, result, MSB16, 0);
+          storeConstToAop (0, AOP (result), LSB);
+       }
+      else if (shCount == 1)
+        shiftLLong (left, result, MSB16);
+      else
+        {
+          shiftL2Left2Result (left, MSB16, result, MSB24, shCount);
+          shiftL1Left2Result (left, LSB, result, MSB16, shCount);
+          shiftRLeftOrResult (left, LSB, result, MSB24, 8 - shCount);
+          storeConstToAop (0, AOP (result), LSB);
+        }
+    }
+
+  /* 1 <= shCount <= 2 */
+    else if (shCount <= 2)
+    {
+      shiftLLong (left, result, LSB);
+      if (shCount == 2)
+        shiftLLong (result, result, LSB);
+	} 
+  else
+    {
+  /* 3 <= shCount <= 7, optimize */
+#if 1
+      shiftLLong (left, result, LSB);	
+      while(--shCount)
+        shiftLLong (result , result, LSB);	
+#else
+      // FIXME: bug 2825
+      shiftL2Left2Result (left, MSB24, result, MSB24, shCount);
+      shiftRLeftOrResult (left, MSB16, result, MSB24, 8 - shCount);
+      shiftL2Left2Result (left, LSB, result, LSB, shCount);
+#endif
+    }
+}
+
+/*-----------------------------------------------------------------*/
+/* genLeftShiftLiteral - left shifting by known count              */
+/*-----------------------------------------------------------------*/
+static void
+genLeftShiftLiteral (operand * left, operand * right, operand * result, iCode * ic)
+{
+  int shCount = (int) ulFromVal (AOP (right)->aopu.aop_lit);
+  int size;
+
+  emitComment (TRACEGEN, __func__);
+
+  freeAsmop (right, NULL, ic, true);
+
+  aopOp (left, ic, false);
+  aopOp (result, ic, false);
+
+  size = AOP_SIZE (result);
+
+#if VIEW_SIZE
+  emitComment (TRACEGEN|VVDBG, "  shift left ", "result %d, left %d", size, AOP_SIZE (left));
+#endif
+
+  if (shCount == 0)
+    {
+      genCopy (result, left);
+    }
+  else if (shCount >= (size * 8))
+    {
+      while (size--)
+        storeConstToAop (0, AOP (result), size);
+    }
+  else
+    {
+      switch (size)
+        {
+        case 1:
+          genlshOne (result, left, shCount);
+          break;
+
+        case 2:
+          genlshTwo (result, left, shCount);
+          break;
+
+        case 4:
+          genlshFour (result, left, shCount);
+          break;
+        default:
+          werror (E_INTERNAL_ERROR, __FILE__, __LINE__, "*** ack! mystery literal shift!\n");
+          break;
+        }
+    }
+  freeAsmop (left, NULL, ic, true);
+  freeAsmop (result, NULL, ic, true);
+}
+
+/*-----------------------------------------------------------------*/
+/* genLeftShift - generates code for left shifting                 */
+/*-----------------------------------------------------------------*/
+static void
+genLeftShift (iCode * ic)
+{
+  operand *left, *right, *result;
+  int size, offset;
+  symbol *tlbl, *tlbl1;
+  char *shift;
+  asmop *aopResult;
+  reg_info *countreg = NULL;
+  int count_offset = 0;
+
+  emitComment (TRACEGEN, __func__);
+
+  right = IC_RIGHT (ic);
+  left = IC_LEFT (ic);
+  result = IC_RESULT (ic);
+
+  aopOp (right, ic, false);
+
+  /* if the shift count is known then do it
+     as efficiently as possible */
+  if (AOP_TYPE (right) == AOP_LIT)
+    {
+      genLeftShiftLiteral (left, right, result, ic);
+      return;
+    }
+
+  /* shift count is unknown then we have to form
+     a loop get the loop count in X : Note: we take
+     only the lower order byte since shifting
+     more that 32 bits make no sense anyway, ( the
+     largest size of an object can be only 32 bits ) */
+
+  aopOp (result, ic, false);
+  aopOp (left, ic, false);
+  aopResult = AOP (result);
+
+// TODO
+#if 0
+  if (sameRegs (AOP (right), AOP (result)) || regsInCommon (right, result) || IS_AOP_XA (AOP (result)) || isOperandVolatile (result, false))
+    aopResult = forceZeropageAop (AOP (result), sameRegs (AOP (left), AOP (result)));
+#endif
+
+  /* load the count register */
+  if (m6502_reg_y->isDead && !IS_AOP_WITH_Y (AOP (result)) && !IS_AOP_WITH_Y (AOP (left)))
+    countreg = m6502_reg_y;
+  else if (m6502_reg_x->isDead && !IS_AOP_WITH_X (AOP (result)) && !IS_AOP_WITH_X (AOP (left)))
+    countreg = m6502_reg_x;
+  else if (m6502_reg_a->isDead && !IS_AOP_WITH_A (AOP (result)) && !IS_AOP_WITH_A (AOP (left)))
+    countreg = m6502_reg_a;
+    
+  if(countreg)
+    {
+      countreg->isFree = false;
+      emitComment (TRACEGEN|VVDBG, "  load countreg");
+      loadRegFromAop (countreg, AOP (right), 0);
+    } else {
+      // FIXME FIXME : something odd with load/store/pull reg
+      emitComment (TRACEGEN|VVDBG, "  count is not a register");
+      bool needpully = pushRegIfUsed (m6502_reg_y);
+      loadRegFromAop (m6502_reg_y, AOP (right), 0);
+      count_offset=_G.tempOfs;
+      storeRegTemp (m6502_reg_y, true);
+      pullOrFreeReg(m6502_reg_y, needpully);
+    }
+
+  /* now move the left to the result if they are not the
+     same */
+  if (IS_AOP_YX (AOP (result)))
+    loadRegFromAop (m6502_reg_yx, AOP (left), 0);
+  else if (IS_AOP_AX (AOP (result)) && IS_AOP_XA (AOP (left)) || IS_AOP_XA (AOP (result)) && IS_AOP_AX (AOP (left)))
+    {
+      swapXA();
+    }
+  else if (!sameRegs (AOP (left), aopResult))
+    {
+      size = AOP_SIZE (result);
+      offset = 0;
+      while (size--)
+        {
+          transferAopAop (AOP (left), offset, aopResult, offset);
+          offset++;
+        }
+    }
+  freeAsmop (left, NULL, ic, true);
+  AOP (result) = aopResult;
+
+  tlbl = safeNewiTempLabel (NULL);
+  size = AOP_SIZE (result);
+  offset = 0;
+  tlbl1 = safeNewiTempLabel (NULL);
+
+  if (countreg)
+    {
+      // TODO: can combine these with load of count reg?
+      if (countreg == m6502_reg_a)
+        emit6502op("cmp", "#0x00");
+      if (countreg == m6502_reg_x)
+        emit6502op("cpx", "#0x00");
+      if (countreg == m6502_reg_y)
+        emit6502op("cpy", "#0x00");
+      emitBranch ("beq", tlbl1);
+    }
+  else
+    {
+      emit6502op ("dec", TEMPFMT, count_offset);
+      // FIXME: could keep it literal
+      dirtyRegTemp(_G.tempOfs - 1);
+      emitBranch ("bmi", tlbl1);
+    }
+
+  safeEmitLabel (tlbl);
+
+  shift = "asl";
+  for (offset = 0; offset < size; offset++)
+    {
+      rmwWithAop (shift, AOP (result), offset);
+      shift = "rol";
+    }
+
+  if (countreg) {
+      rmwWithReg("dec", countreg);
+      emit6502op("bne", "%05d$", safeLabelKey2num (tlbl->key));
+  } else {
+      emit6502op("dec", TEMPFMT, count_offset );
+      // FIXME: could keep it literal
+      dirtyRegTemp(_G.tempOfs - 1);
+      emit6502op("bpl", "%05d$", safeLabelKey2num (tlbl->key));
+    }
+
+  safeEmitLabel (tlbl1);
+
+  if (!countreg) {
+    emitComment (TRACEGEN|VVDBG, "  pull null (1) ");
+    loadRegTemp(NULL);
+  }
+
+  freeAsmop (result, NULL, ic, true);
+  freeAsmop (right, NULL, ic, true);
+}
+
+/*-----------------------------------------------------------------*/
+/* genrshOne - right shift a one byte quantity by known count      */
+/*-----------------------------------------------------------------*/
+static void
+genrshOne (operand * result, operand * left, int shCount, int sign)
+{
+  bool needpulla;
+  emitComment (TRACEGEN, __func__);
+  if (shCount==0) return;
+  needpulla = pushRegIfSurv (m6502_reg_a);
+  loadRegFromAop (m6502_reg_a, AOP (left), 0);
+  AccRsh (shCount, sign);
+  storeRegToFullAop (m6502_reg_a, AOP (result), sign);
+  pullOrFreeReg (m6502_reg_a, needpulla);
+}
+
+/*-----------------------------------------------------------------*/
+/* genrshTwo - right shift two bytes by known amount != 0          */
+/*-----------------------------------------------------------------*/
+static void
+genrshTwo (operand * result, operand * left, int shCount, int sign)
+{
+  bool needpulla, needpullx;
+  emitComment (TRACEGEN, __func__);
+
+  /* if shCount >= 8 */
+  if (shCount >= 8)
+    {
+      if (shCount != 8 || sign)
+        {
+          needpulla = pushRegIfSurv (m6502_reg_a);
+          loadRegFromAop (m6502_reg_a, AOP (left), 1);
+          AccRsh (shCount - 8, sign);
+          storeRegToFullAop (m6502_reg_a, AOP (result), sign);
+          pullOrFreeReg (m6502_reg_a, needpulla);
+        }
+      else
+        {
+          transferAopAop (AOP (left), 1, AOP (result), 0);
+          storeConstToAop (0, AOP (result), 1);
+        }
+    }
+  /*  1 <= shCount <= 7 */
+  else
+    {
+      needpulla = storeRegTempIfSurv (m6502_reg_a);
+      needpullx = storeRegTempIfSurv (m6502_reg_x);
+      loadRegFromAop (m6502_reg_xa, AOP (left), 0);
+      XAccRsh (shCount, sign);
+      storeRegToAop (m6502_reg_xa, AOP (result), 0);
+      loadOrFreeRegTemp (m6502_reg_x, needpullx);
+      loadOrFreeRegTemp (m6502_reg_a, needpulla);
+    }
+}
+
+/*-----------------------------------------------------------------*/
+/* shiftRLong - shift right one long from left to result           */
+/* offl = LSB or MSB16                                             */
+/*-----------------------------------------------------------------*/
+static void
+shiftRLong (operand * left, int offl, operand * result, int sign)
+{
+  bool needpulla = pushRegIfSurv (m6502_reg_a);
+  bool needloadx = false;
+
+  switch(offl)
+    {
+    case LSB:
+      loadRegFromAop (m6502_reg_a, AOP (left), 3);
+      if(sign)
+        {
+          emit6502op("cmp","#0x80");
+          rmwWithReg ("ror", m6502_reg_a);
+        }
+      else 
+        rmwWithReg ("lsr", m6502_reg_a);
+
+      storeRegToAop (m6502_reg_a, AOP (result), 3);
+      loadRegFromAop (m6502_reg_a, AOP (left), 2);
+      rmwWithReg ("ror", m6502_reg_a);
+      storeRegToAop (m6502_reg_a, AOP (result), 2);
+      loadRegFromAop (m6502_reg_a, AOP (left), 1);
+      rmwWithReg ("ror", m6502_reg_a);
+      storeRegToAop (m6502_reg_a, AOP (result), 1);
+      loadRegFromAop (m6502_reg_a, AOP (left), 0);
+      rmwWithReg ("ror", m6502_reg_a);
+      storeRegToAop (m6502_reg_a, AOP (result), 0);
+      break;
+    case MSB16:
+      needloadx = storeRegTempIfSurv (m6502_reg_x);
+
+      loadRegFromConst(m6502_reg_x,0);
+      loadRegFromAop (m6502_reg_a, AOP (left), 3);
+      if(sign) {
+          symbol *tlbl = safeNewiTempLabel (NULL);
+          emit6502op("clc","");
+          emit6502op("bpl","%05d$", safeLabelKey2num (tlbl->key));
+          emit6502op("sec","");
+          loadRegFromConst(m6502_reg_x,0xff);
+          safeEmitLabel(tlbl);
+          rmwWithReg ("ror", m6502_reg_a);
+      } else {
+          rmwWithReg ("lsr", m6502_reg_a);
+      }
+      storeRegToAop (m6502_reg_x, AOP (result), 3);    
+
+      loadRegFromAop (m6502_reg_x, AOP (left), 2);
+      storeRegToAop (m6502_reg_a, AOP (result), 2);
+      transferRegReg(m6502_reg_x, m6502_reg_a, true);
+      rmwWithReg ("ror", m6502_reg_a);
+
+      loadRegFromAop (m6502_reg_x, AOP (left), 1);
+      storeRegToAop (m6502_reg_a, AOP (result), 1);
+      transferRegReg(m6502_reg_x, m6502_reg_a, true);
+      rmwWithReg ("ror", m6502_reg_a);
+      storeRegToAop (m6502_reg_a, AOP (result), 0);
+      break;
+ //   default:
+      // error
+    }
+  loadOrFreeRegTemp (m6502_reg_x, needloadx);
+  pullOrFreeReg (m6502_reg_a, needpulla);
+}
+
+/*-----------------------------------------------------------------*/
+/* genrshFour - shift four byte by a known amount != 0             */
+/*-----------------------------------------------------------------*/
+static void
+genrshFour (operand * result, operand * left, int shCount, int sign)
+{
+  bool needpulla = false;
+  bool needpullx = false;
+
+  /* TODO: handle cases where left == result */
+
+  emitComment (TRACEGEN, __func__);
+  emitComment (TRACEGEN, "  %s - shift=%d", __func__, shCount);
+
+  /* if shifting more that 3 bytes */
+  if (shCount >= 24)
+    {
+      needpulla = storeRegTempIfSurv (m6502_reg_a);
+      loadRegFromAop (m6502_reg_a, AOP (left), 3);
+      AccRsh (shCount - 24, sign);
+      storeRegToFullAop (m6502_reg_a, AOP (result), sign);
+    }
+  else if (shCount >= 16)
+    {
+      needpulla = storeRegTempIfSurv (m6502_reg_a);
+      needpullx = storeRegTempIfSurv (m6502_reg_x);
+      loadRegFromAop (m6502_reg_xa, AOP (left), 2);
+      XAccRsh (shCount - 16, sign);
+      storeRegToFullAop (m6502_reg_xa, AOP (result), sign);
+    }
+  else if (shCount >= 8)
+    {
+      if (shCount == 8)
+        {
+          needpulla = storeRegTempIfSurv (m6502_reg_a);
+          transferAopAop (AOP (left), 1, AOP (result), 0);
+          transferAopAop (AOP (left), 2, AOP (result), 1);
+          loadRegFromAop (m6502_reg_a, AOP (left), 3);
+          storeRegToAop (m6502_reg_a, AOP (result), 2);
+          storeRegSignToUpperAop (m6502_reg_a, AOP (result), 3, sign);
+        }
+      else if (shCount == 9)
+        {
+          shiftRLong (left, MSB16, result, sign);
+          return;
+        }
+      else
+        {
+          needpulla = storeRegTempIfSurv (m6502_reg_a);
+          needpullx = storeRegTempIfSurv (m6502_reg_x);
+          loadRegFromAop (m6502_reg_xa, AOP (left), 1);
+          XAccRsh (shCount - 8, false);
+          storeRegToAop (m6502_reg_xa, AOP (result), 0);
+          loadRegFromAop (m6502_reg_x, AOP (left), 3);
+          loadRegFromConst (m6502_reg_a, 0);
+          XAccRsh (shCount - 8, sign);
+          accopWithAop ("ora", AOP (result), 1);
+          storeRegToAop (m6502_reg_xa, AOP (result), 1);
+          storeRegSignToUpperAop (m6502_reg_x, AOP (result), 3, sign);
+        }
+    }
+  else
+    {
+      /* 1 <= shCount <= 7 */
+      if (shCount == 1)
+        {
+          shiftRLong (left, LSB, result, sign);
+          return;
+        }
+      else
+        {
+          needpulla = storeRegTempIfSurv (m6502_reg_a);
+          needpullx = storeRegTempIfSurv (m6502_reg_x);
+          loadRegFromAop (m6502_reg_xa, AOP (left), 0);
+          XAccRsh (shCount, false);
+          storeRegToAop (m6502_reg_xa, AOP (result), 0);
+          loadRegFromAop (m6502_reg_a, AOP (left), 2);
+          AccLsh (8 - shCount);
+          accopWithAop ("ora", AOP (result), 1);
+          storeRegToAop (m6502_reg_a, AOP (result), 1);
+          loadRegFromAop (m6502_reg_xa, AOP (left), 2);
+          XAccRsh (shCount, sign);
+          storeRegToAop (m6502_reg_xa, AOP (result), 2);
+        }
+    }
+  loadOrFreeRegTemp (m6502_reg_x, needpullx);
+  loadOrFreeRegTemp (m6502_reg_a, needpulla);
+}
+
+/*-----------------------------------------------------------------*/
+/* genRightShiftLiteral - right shifting by known count            */
+/*-----------------------------------------------------------------*/
+static void
+genRightShiftLiteral (operand * left, operand * right, operand * result, iCode * ic, int sign)
+{
+  int shCount = (int) ulFromVal (AOP (right)->aopu.aop_lit);
+  int size;
+
+  emitComment (TRACEGEN, __func__);
+
+  freeAsmop (right, NULL, ic, true);
+
+  aopOp (left, ic, false);
+  aopOp (result, ic, false);
+
+#if VIEW_SIZE
+  emitComment (TRACEGEN|VVDBG, "  shift right ", "result %d, left %d", AOP_SIZE (result), AOP_SIZE (left));
+#endif
+
+  size = getDataSize (left);
+  /* test the LEFT size !!! */
+
+  /* I suppose that the left size >= result size */
+  if (shCount == 0)
+    {
+      genCopy (result, left);
+    }
+  else if (shCount >= (size * 8))
+    {
+      bool needpulla = pushRegIfSurv (m6502_reg_a);
+      if (sign)
+        {
+          
+          /* get sign in acc.7 */
+          loadRegFromAop (m6502_reg_a, AOP (left), size - 1);
+        }
+      addSign (result, LSB, sign);
+      pullOrFreeReg (m6502_reg_a, needpulla);
+    }
+  else
+    {
+      switch (size)
+        {
+        case 1:
+          genrshOne (result, left, shCount, sign);
+          break;
+
+        case 2:
+          genrshTwo (result, left, shCount, sign);
+          break;
+
+        case 4:
+          genrshFour (result, left, shCount, sign);
+          break;
+        default:
+          wassertl (0, "Invalid operand size in right shift.");
+          break;
+        }
+    }
+  freeAsmop (left, NULL, ic, true);
+  freeAsmop (result, NULL, ic, true);
+}
+
+// TODO: can refactor lots of left shift with right shift
+
+/*-----------------------------------------------------------------*/
+/* genRightShift - generate code for right shifting                */
+/*-----------------------------------------------------------------*/
+static void
+genRightShift (iCode * ic)
+{
+  operand *right, *left, *result;
+  sym_link *retype;
+  int size, offset;
+  symbol *tlbl, *tlbl1;
+  char *shift;
+  bool sign;
+  asmop *aopResult;
+  reg_info *countreg = NULL;
+  int count_offset=0;
+
+  emitComment (TRACEGEN, __func__);
+
+  /* if signed then we do it the hard way preserve the
+     sign bit moving it inwards */
+  retype = getSpec (operandType (IC_RESULT (ic)));
+  sign = !SPEC_USIGN (retype);
+
+  /* signed & unsigned types are treated the same : i.e. the
+     signed is NOT propagated inwards : quoting from the
+     ANSI - standard : "for E1 >> E2, is equivalent to division
+     by 2**E2 if unsigned or if it has a non-negative value,
+     otherwise the result is implementation defined ", MY definition
+     is that the sign does not get propagated */
+
+  right = IC_RIGHT (ic);
+  left = IC_LEFT (ic);
+  result = IC_RESULT (ic);
+
+  aopOp (right, ic, false);
+
+  /* if the shift count is known then do it
+     as efficiently as possible */
+  if (AOP_TYPE (right) == AOP_LIT)
+    {
+      genRightShiftLiteral (left, right, result, ic, sign);
+      return;
+    }
+
+  /* shift count is unknown then we have to form
+     a loop get the loop count in X : Note: we take
+     only the lower order byte since shifting
+     more that 32 bits make no sense anyway, ( the
+     largest size of an object can be only 32 bits ) */
+
+  aopOp (result, ic, false);
+  aopOp (left, ic, false);
+  aopResult = AOP (result);
+
+// TODO
+#if 0
+  if (sameRegs (AOP (right), AOP (result)) || regsInCommon (right, result) || IS_AOP_XA (AOP (result)) || isOperandVolatile (result, false))
+    aopResult = forceZeropageAop (AOP (result), sameRegs (AOP (left), AOP (result)));
+#endif
+
+  /* load the count register */
+  if (m6502_reg_y->isDead && !IS_AOP_WITH_Y (AOP (result)) && !IS_AOP_WITH_Y (AOP (left)))
+    countreg = m6502_reg_y;
+  else if (m6502_reg_x->isDead && !IS_AOP_WITH_X (AOP (result)) && !IS_AOP_WITH_X (AOP (left)))
+    countreg = m6502_reg_x;
+  else if (m6502_reg_a->isDead && !IS_AOP_WITH_A (AOP (result)) && !IS_AOP_WITH_A (AOP (left)))
+    countreg = m6502_reg_a;
+    
+  if(countreg)
+    {
+      countreg->isFree = false;
+      loadRegFromAop (countreg, AOP (right), 0);
+    } else {
+      // FIXME FIXME
+      emitComment (TRACEGEN|VVDBG, "  count is not a register");
+      bool needpully = pushRegIfUsed (m6502_reg_y);
+      loadRegFromAop (m6502_reg_y, AOP (right), 0);
+      count_offset=_G.tempOfs;
+      storeRegTemp (m6502_reg_y, true);
+      pullOrFreeReg(m6502_reg_y, needpully);
+    }
+
+  /* now move the left to the result if they are not the
+     same */
+  // TODO: can we keep it in A?
+  if (IS_AOP_YX (AOP (result)))
+    {
+      loadRegFromAop (m6502_reg_yx, AOP (left), 0);
+    }
+  else if (IS_AOP_AX (AOP (result)) && IS_AOP_XA (AOP (left)) || IS_AOP_XA (AOP (result)) && IS_AOP_AX (AOP (left)))
+    {
+      swapXA();
+    }
+  else if (!sameRegs (AOP (left), aopResult))
+    {
+      size = AOP_SIZE (result);
+      offset = 0;
+      while (size--)
+        {
+          transferAopAop (AOP (left), offset, aopResult, offset);
+          offset++;
+        }
+    }
+  freeAsmop (left, NULL, ic, true);
+  AOP (result) = aopResult;
+
+  tlbl = safeNewiTempLabel (NULL);
+  size = AOP_SIZE (result);
+  offset = 0;
+  tlbl1 = safeNewiTempLabel (NULL);
+
+  if (countreg) // TODO
+    {
+      // TODO: combine with load index?
+      if (countreg == m6502_reg_a)
+        emit6502op("cmp", "#0x00");
+      if (countreg == m6502_reg_x)
+        emit6502op("cpx", "#0x00");
+      if (countreg == m6502_reg_y)
+        emit6502op("cpy", "#0x00");
+      emitBranch ("beq", tlbl1);
+    }
+  else
+    {
+      emit6502op ("dec", TEMPFMT, count_offset);
+      // could keep it literal
+      dirtyRegTemp(_G.tempOfs - 1);
+      emitBranch ("bmi", tlbl1);
+    }
+
+  safeEmitLabel (tlbl);
+
+  shift = sign ? "asr" : "lsr";
+  for (offset = size - 1; offset >= 0; offset--)
+    {
+      rmwWithAop (shift, AOP (result), offset);
+      shift = "ror";
+    }
+
+  if (countreg) {
+      rmwWithReg("dec", countreg);
+        emit6502op("bne", "%05d$", safeLabelKey2num (tlbl->key));
+  } else {
+      emit6502op("dec", TEMPFMT, count_offset );
+      // FIXME: could keep it literal
+      dirtyRegTemp(_G.tempOfs - 1);
+      emit6502op("bpl", "%05d$", safeLabelKey2num (tlbl->key));
+    }
+
+  safeEmitLabel (tlbl1);
+
+  if (!countreg) 
+    loadRegTemp(NULL);
+
+  freeAsmop (result, NULL, ic, true);
+  freeAsmop (right, NULL, ic, true);
+}
+
+/*-----------------------------------------------------------------*/
+/* decodePointerOffset - decode a pointer offset operand into a    */
+/*                    literal offset and a rematerializable offset */
+/*-----------------------------------------------------------------*/
+static void
+decodePointerOffset (operand * opOffset, int * litOffset, char ** rematOffset)
+{
+  *litOffset = 0;
+  *rematOffset = NULL;
+
+  if (!opOffset)
+    return;
+
+  if (IS_OP_LITERAL (opOffset))
+    {
+      *litOffset = (int)operandLitValue (opOffset);
+    }
+  else if (IS_ITEMP (opOffset) && OP_SYMBOL (opOffset)->remat)
+    {
+      asmop * aop = aopForRemat (OP_SYMBOL (opOffset));
+
+      if (aop->type == AOP_LIT)
+        *litOffset = (int) floatFromVal (aop->aopu.aop_lit);
+      else if (aop->type == AOP_IMMD)
+        *rematOffset = aop->aopu.aop_immd.aop_immd1;
+    }
+  else
+    wassertl (0, "Pointer get/set with non-constant offset");
+}
+
+// does a BIT A with a constant, even for non-65C02
+// TODO: lookup table for each new const?
+void bitAConst(int val)
+{
+  wassertl (val >= 0 && val <= 0xff, "bitAConst()");
+  if (IS_MOS65C02) {
+    emit6502op ("bit", IMMDFMT, val);
+  } else {
+    storeRegTemp (m6502_reg_a, true);
+    emit6502op ("and", IMMDFMT, val);
+    loadRegTempNoFlags (m6502_reg_a, true);
+  }
+}
+
+/*-----------------------------------------------------------------*/
+/* genUnpackBits - generates code for unpacking bits               */
+/*-----------------------------------------------------------------*/
+static void
+genUnpackBits (operand * result, operand * left, operand * right, iCode * ifx)
+{
+  int offset = 0;               /* result byte offset */
+  int rsize;                    /* result size */
+  int rlen = 0;                 /* remaining bitfield length */
+  sym_link *etype;              /* bitfield type information */
+  unsigned blen;                /* bitfield length */
+  unsigned bstr;                /* bitfield starting bit within byte */
+  bool needpulla = false;
+  bool needpully = false;
+  bool needpullx = false;
+  int litOffset = 0;
+  char * rematOffset = NULL;
+
+  emitComment (TRACEGEN, __func__);
+
+  decodePointerOffset (right, &litOffset, &rematOffset);
+  etype = getSpec (operandType (result));
+  rsize = getSize (operandType (result));
+  blen = SPEC_BLEN (etype);
+  bstr = SPEC_BSTR (etype);
+
+  needpulla = pushRegIfSurv (m6502_reg_a);
+
+  if (!IS_AOP_YX (AOP (left)))
+    {
+      needpullx = pushRegIfSurv (m6502_reg_x);
+      needpully = pushRegIfSurv (m6502_reg_y);
+    }
+
+  /* if the operand is already in yx
+     then we do nothing else we move the value to yx */
+  loadRegFromAop (m6502_reg_yx, AOP (left), 0);
+  /* so yx now contains the address */
+
+  if (ifx && blen <= 8)
+    {
+      loadRegIndexed (m6502_reg_a, litOffset, rematOffset);
+      if (blen < 8)
+        {
+          emit6502op ("and", IMMDFMT, (((unsigned char) - 1) >> (8 - blen)) << bstr);
+        }
+//      emit6502op("php", "");//TODO
+      pullOrFreeReg (m6502_reg_y, needpully);
+      pullOrFreeReg (m6502_reg_x, needpullx);
+      pullOrFreeReg (m6502_reg_a, needpulla);
+//      emit6502op("plp", "");
+      genIfxJump (ifx, "a");
+      return;
+    }
+  wassert (!ifx);
+
+  /* If the bitfield length is less than a byte */
+  if (blen < 8)
+    {
+      loadRegIndexed (m6502_reg_a, litOffset, rematOffset);
+      AccRsh (bstr, false);
+      emit6502op ("and", IMMDFMT, ((unsigned char) - 1) >> (8 - blen));
+      if (!SPEC_USIGN (etype))
+        {
+          /* signed bitfield */
+          symbol *tlbl = safeNewiTempLabel (NULL);
+
+	  // FIXME
+          // emitcode ("bit11", IMMDFMT, 1 << (blen - 1));
+          bitAConst(1 << (blen - 1));
+          emitcode ("beq", "%05d$", safeLabelKey2num (tlbl->key));
+          emitcode ("ora", IMMDFMT, (unsigned char) (0xff << blen));
+          safeEmitLabel (tlbl);
+        }
+      storeRegToAop (m6502_reg_a, AOP (result), offset++);
+      goto finish;
+    }
+
+  /* Bit field did not fit in a byte. Copy all
+     but the partial byte at the end.  */
+  for (rlen = blen; rlen >= 8; rlen -= 8)
+    {
+      loadRegIndexed (m6502_reg_a, litOffset, rematOffset);
+      if (rlen > 8 && AOP_TYPE (result) == AOP_REG)
+        pushReg (m6502_reg_a, true);
+      else
+        storeRegToAop (m6502_reg_a, AOP (result), offset);
+      offset++;
+      if (rlen > 8)
+        {
+          litOffset++;
+        }
+    }
+
+  /* Handle the partial byte at the end */
+  if (rlen)
+    {
+      loadRegIndexed (m6502_reg_a, litOffset, rematOffset);
+      emit6502op ("and", IMMDFMT, ((unsigned char) - 1) >> (8 - rlen));
+      if (!SPEC_USIGN (etype))
+        {
+          /* signed bitfield */
+          symbol *tlbl = safeNewiTempLabel (NULL);
+
+	  // FIXME: unimplemented
+          // emitcode ("bit12", IMMDFMT, 1 << (rlen - 1));
+          bitAConst(1 << (rlen - 1));
+          emitcode ("beq", "%05d$", safeLabelKey2num (tlbl->key));
+          emitcode ("ora", IMMDFMT, (unsigned char) (0xff << rlen));
+          safeEmitLabel (tlbl);
+        }
+      storeRegToAop (m6502_reg_a, AOP (result), offset++);
+    }
+  if (blen > 8 && AOP_TYPE (result) == AOP_REG)
+    {
+      pullReg (AOP (result)->aopu.aop_reg[0]);
+    }
+
+finish:
+  if (offset < rsize)
+    {
+      rsize -= offset;
+      if (SPEC_USIGN (etype))
+        {
+          while (rsize--)
+            storeConstToAop (0, AOP (result), offset++);
+        }
+      else
+        {
+          /* signed bitfield: sign extension with 0x00 or 0xff */
+          signExtendA();
+          while (rsize--)
+            storeRegToAop (m6502_reg_a, AOP (result), offset++);
+        }
+    }
+  pullOrFreeReg (m6502_reg_y, needpully);
+  pullOrFreeReg (m6502_reg_x, needpullx);
+  pullOrFreeReg (m6502_reg_a, needpulla);
+}
+
+/*-----------------------------------------------------------------*/
+/* genUnpackBitsImmed - generates code for unpacking bits          */
+/*-----------------------------------------------------------------*/
+static void
+genUnpackBitsImmed (operand * left, operand *right, operand * result, iCode * ic, iCode * ifx)
+{
+  int size;
+  int offset = 0;               /* result byte offset */
+  int litOffset = 0;
+  char * rematOffset = NULL;
+  int rsize;                    /* result size */
+  int rlen = 0;                 /* remaining bitfield length */
+  sym_link *etype;              /* bitfield type information */
+  unsigned blen;                /* bitfield length */
+  unsigned bstr;                /* bitfield starting bit within byte */
+  asmop *derefaop;
+  bool delayed_a = false;
+  bool assigned_a = false;
+  bool needpulla = false;
+
+  emitComment (TRACEGEN, __func__);
+
+  decodePointerOffset (right, &litOffset, &rematOffset);
+  wassert (rematOffset==NULL);
+
+  aopOp (result, ic, true);
+  size = AOP_SIZE (result);
+
+  derefaop = aopDerefAop (AOP (left), litOffset);
+  freeAsmop (left, NULL, ic, true);
+  derefaop->size = size;
+
+  etype = getSpec (operandType (result));
+  rsize = getSize (operandType (result));
+  blen = SPEC_BLEN (etype);
+  bstr = SPEC_BSTR (etype);
+
+  needpulla = pushRegIfSurv (m6502_reg_a);
+
+  /* if the bitfield is a single bit in the direct page */
+  if (blen == 1 && derefaop->type == AOP_DIR)
+    {
+      if (!ifx && bstr)
+        {
+          symbol *tlbl = safeNewiTempLabel (NULL);
+
+	  // FIXME: unimplemented
+          loadRegFromConst (m6502_reg_a, 0);
+          emitcode ("brclr", "#%d,%s,%05d$", bstr, aopAdrStr (derefaop, 0, false), safeLabelKey2num ((tlbl->key)));
+          if (SPEC_USIGN (etype))
+            rmwWithReg ("inc", m6502_reg_a);
+          else
+            rmwWithReg ("dec", m6502_reg_a);
+          safeEmitLabel (tlbl);
+          storeRegToAop (m6502_reg_a, AOP (result), offset);
+          if (AOP_TYPE (result) == AOP_REG && AOP(result)->aopu.aop_reg[offset]->rIdx == A_IDX)
+            assigned_a = true;
+          m6502_freeReg (m6502_reg_a);
+          offset++;
+          goto finish;
+        }
+      else if (ifx)
+        {
+          symbol *tlbl = safeNewiTempLabel (NULL);
+          symbol *jlbl;
+          char *inst;
+
+	  // FIXME
+          if (IC_TRUE (ifx))
+            {
+              jlbl = IC_TRUE (ifx);
+              inst = "brclr";
+            }
+          else
+            {
+              jlbl = IC_FALSE (ifx);
+              inst = "brset";
+            }
+          emitcode (inst, "#%d,%s,%05d$", bstr, aopAdrStr (derefaop, 0, false), safeLabelKey2num ((tlbl->key)));
+          emitBranch ("jmp", jlbl);
+          safeEmitLabel (tlbl);
+          ifx->generated = 1;
+          offset++;
+          goto finish;
+        }
+    }
+
+  /* If the bitfield length is less than a byte */
+  if (blen < 8)
+    {
+      loadRegFromAop (m6502_reg_a, derefaop, 0);
+      if (!ifx)
+        {
+          // TODO: inefficient if just getting flags
+          AccRsh (bstr, false);
+          emit6502op ("and", IMMDFMT, ((unsigned char) - 1) >> (8 - blen));
+          if (!SPEC_USIGN (etype))
+            {
+              /* signed bitfield */
+              symbol *tlbl = safeNewiTempLabel (NULL);
+              bitAConst(1 << (blen - 1));
+              emit6502op ("beq", "%05d$", safeLabelKey2num (tlbl->key));
+              emit6502op ("ora", IMMDFMT, (unsigned char) (0xff << blen));
+              safeEmitLabel (tlbl);
+            }
+          storeRegToAop (m6502_reg_a, AOP (result), offset);
+          if (AOP_TYPE (result) == AOP_REG && AOP(result)->aopu.aop_reg[offset]->rIdx == A_IDX)
+            assigned_a = true;
+        }
+      else
+        {
+          emit6502op ("and", IMMDFMT, (((unsigned char) - 1) >> (8 - blen)) << bstr);
+        }
+      offset++;
+      goto finish;
+    }
+
+  /* Bit field did not fit in a byte. Copy all
+     but the partial byte at the end.  */
+  for (rlen = blen; rlen >= 8; rlen -= 8)
+    {
+      if (assigned_a && !delayed_a)
+        {
+          pushReg (m6502_reg_a, true);
+          delayed_a = true;
+        }
+      loadRegFromAop (m6502_reg_a, derefaop, offset);
+      if (!ifx)
+        {
+          storeRegToAop (m6502_reg_a, AOP (result), offset);
+          if (AOP_TYPE (result) == AOP_REG && AOP(result)->aopu.aop_reg[offset]->rIdx == A_IDX)
+            assigned_a = true;
+        }
+      else
+        {
+          emit6502op ("cmp", "#0x00");
+        }
+      offset++;
+    }
+
+  /* Handle the partial byte at the end */
+  if (rlen)
+    {
+      if (assigned_a && !delayed_a)
+        {
+          pushReg (m6502_reg_a, true);
+          delayed_a = true;
+        }
+      loadRegFromAop (m6502_reg_a, derefaop, offset);
+      emit6502op ("and", IMMDFMT, ((unsigned char) - 1) >> (8 - rlen));
+      if (!SPEC_USIGN (etype))
+        {
+          /* signed bitfield */
+          symbol *tlbl = safeNewiTempLabel (NULL);
+
+          bitAConst (1 << (rlen - 1));
+          emit6502op ("beq", "%05d$", safeLabelKey2num (tlbl->key));
+          emit6502op ("ora", IMMDFMT, (unsigned char) (0xff << rlen));
+          safeEmitLabel (tlbl);
+        }
+      storeRegToAop (m6502_reg_a, AOP (result), offset);
+      if (AOP_TYPE (result) == AOP_REG && AOP(result)->aopu.aop_reg[offset]->rIdx == A_IDX)
+        assigned_a = true;
+      offset++;
+    }
+
+finish:
+  if (offset < rsize)
+    {
+      rsize -= offset;
+      if (SPEC_USIGN (etype))
+        {
+          while (rsize--)
+            storeConstToAop (0, AOP (result), offset++);
+        }
+      else
+        {
+          if (assigned_a && !delayed_a)
+            {
+              pushReg (m6502_reg_a, true);
+              delayed_a = true;
+            }
+
+          /* signed bitfield: sign extension with 0x00 or 0xff */
+          signExtendA();
+          while (rsize--)
+            storeRegToAop (m6502_reg_a, AOP (result), offset++);
+        }
+    }
+
+  freeAsmop (NULL, derefaop, ic, true);
+  freeAsmop (result, NULL, ic, true);
+
+  if (ifx && !ifx->generated)
+    {
+      genIfxJump (ifx, "a");
+    }
+  if (delayed_a)
+    pullReg (m6502_reg_a);
+
+    // TODO? wrong plac?
+  pullOrFreeReg (m6502_reg_a, needpulla);
+}
+
+
+/*-----------------------------------------------------------------*/
+/* genDataPointerGet - generates code when ptr offset is known     */
+/*-----------------------------------------------------------------*/
+static void
+genDataPointerGet (operand * left, operand * right, operand * result, iCode * ic, iCode * ifx)
+{
+  int size;
+  int litOffset = 0;
+  char * rematOffset = NULL;
+  asmop *derefaop;
+  bool needpulla = false;
+
+  emitComment (TRACEGEN, __func__);
+
+  decodePointerOffset (right, &litOffset, &rematOffset);
+  wassert (rematOffset==NULL);
+
+  aopOp (result, ic, true);
+  size = AOP_SIZE (result);
+
+  // TODO: aopDerefAop(IMMD(_ftest_a_65536_8)), why?
+  derefaop = aopDerefAop (AOP (left), litOffset);
+  freeAsmop (left, NULL, ic, true);
+  derefaop->size = size;
+  
+  if (ifx)
+    needpulla = storeRegTempIfSurv (m6502_reg_a);
+
+  if (IS_AOP_YX (AOP (result)))
+    loadRegFromAop (m6502_reg_yx, derefaop, 0);
+  else
+    while (size--)
+      {
+        if (!ifx)
+          transferAopAop (derefaop, size, AOP (result), size);
+        else
+          loadRegFromAop (m6502_reg_a, derefaop, size);
+      }
+
+  freeAsmop (NULL, derefaop, ic, true);
+  freeAsmop (result, NULL, ic, true);
+
+  if (ifx && !ifx->generated)
+    {
+      loadRegTempNoFlags (m6502_reg_a, needpulla);
+      genIfxJump (ifx, "a");
+    }
+    else
+    {
+      if (needpulla) loadRegTemp (NULL);
+    }
+}
+
+/* copy pointer into TEMP+i zero-page location, and load Y if needed */
+/* return -1 if can be absolute indexed */
+/* left is address, right is value to write or NULL */
+static int
+preparePointer (operand* left, int offset, char* rematOfs, operand* right)
+{
+  // TODO: really do we need this?
+  asmop *newaop = newAsmop (AOP_DIR);
+  newaop->aopu.aop_dir = Safe_calloc (1, 10+4);
+  snprintf(newaop->aopu.aop_dir, 14, "(__TEMP+%d)", _G.tempOfs);
+
+  emitComment (TRACEGEN|VVDBG, "      preparePointer: %s", newaop->aopu.aop_dir);
+  newaop->size = 2;
+  
+  /* The rematerialized offset may have a "#" prefix; skip over it */
+  if (rematOfs && rematOfs[0] == '#')
+    rematOfs++;
+  if (rematOfs && !rematOfs[0])
+    rematOfs = NULL;
+
+  /* force offset to signed 16-bit range */
+  offset &= 0xffff;
+  if (offset & 0x8000)
+    offset = 0x10000 - offset;
+
+  emitComment (TRACEGEN|VVDBG, "      preparePointer (%s, off=%d, remat=%s) tempOfs %d", aopName(AOP(left)), offset, rematOfs, _G.tempOfs);
+
+  tempRematOfs = rematOfs;
+  prepSwapAY = false;
+
+  if(right) {
+  emitComment (TRACEGEN|VVDBG, "      preparePointer AOP_TYPE(right)==AOP_REG: %s", (AOP_TYPE(right) == AOP_REG)?"yes":"no");
+  emitComment (TRACEGEN|VVDBG, "      preparePointer AOP_SIZE(right)=%d", AOP_SIZE(right));
+}
+  if(left) {
+  emitComment (TRACEGEN|VVDBG, "      preparePointer AOP_TYPE(left)==AOP_REG: %s", (AOP_TYPE(left) == AOP_REG)?"yes":"no");
+  emitComment (TRACEGEN|VVDBG, "      preparePointer AOP_SIZE(left)=%d", AOP_SIZE(left));
+//  emitComment (TRACEGEN|VVDBG, "      preparePointer (%s, off=%d, remat=%s) tempOfs %d", aopName(AOP(left)), offset, rematOfs, _G.tempOfs);
+}
+  
+#if 1
+  // FIXME: this code sometimes improperly detects 8-bit offsets
+  // triggers failure on bug-477927 when using zero weight for cycles cost
+  // FIXME FIXME: this is a great optimization opportunity
+  // 8-bit absolute offset? (remat+offset,y)
+  // TODO: better way than checking register?
+  if (rematOfs && AOP_TYPE(left) == AOP_REG 
+      && (AOP_SIZE(left) == 1 || AOP(left)->aopu.aop_reg[1]->isLitConst && AOP(left)->aopu.aop_reg[1]->litConst == 0))
+    {
+      emitComment (TRACEGEN|VVDBG, "        preparePointer: 8-bit offset");
+      // TODO: what if Y is right and AX is pointer?
+      prepSwapAY = right && AOP(left)->aopu.aop_reg[0] == m6502_reg_a && AOP_TYPE(right) == AOP_REG && IS_AOP_WITH_Y(AOP(right));
+      if (prepSwapAY) {
+        // swap A and Y
+        emitComment (TRACEGEN|VVDBG, "        preparePointer: swap A and Y");
+        storeRegTemp(m6502_reg_a, true);
+        transferRegReg(m6502_reg_y, m6502_reg_a, true);
+        loadRegTemp(m6502_reg_y);
+      } else {
+        // transfer lower byte of offset to Y
+        // FIXME: should allow offset in X as well
+        transferRegReg(AOP(left)->aopu.aop_reg[0], m6502_reg_y, true);
+      }
+      return (prepTempOfs = -1);
+    }
+#endif
+
+  // need to do pointer math?
+  if (!rematOfs && offset >= 0 && offset <= 255-4)
+    {
+      prepTempOfs = _G.tempOfs;
+      _G.tempOfs += 2;
+
+      // just copy, we can add the remaining offset to Y later
+      transferAopAop(AOP(left), 0, newaop, 0);
+      transferAopAop(AOP(left), 1, newaop, 1);
+    }
+  else
+    {
+      bool needpulla = pushRegIfUsed(m6502_reg_a);
+
+      emit6502op ("clc", "");
+      prepTempOfs = _G.tempOfs;
+
+      if (IS_AOP_AX(AOP(left))) {
+        pushReg(m6502_reg_a, true);
+        loadRegFromAop(m6502_reg_a, AOP(left), 0);
+        emit6502op ("adc", "#<(%s+%d)", rematOfs, offset);
+        storeRegTemp(m6502_reg_a, true);
+        pullReg(m6502_reg_a);
+        emit6502op ("adc", "#>(%s+%d)", rematOfs, offset);
+        storeRegTemp(m6502_reg_a, true);
+      } else {
+        loadRegFromAop(m6502_reg_a, AOP(left), 0);
+      emit6502op ("adc", "#<(%s+%d)", rematOfs, offset);
+      storeRegTemp(m6502_reg_a, true);
+      loadRegFromAop(m6502_reg_a, AOP(left), 1);
+      emit6502op ("adc", "#>(%s+%d)", rematOfs, offset);
+      storeRegTemp(m6502_reg_a, true);
+      }
+      pullOrFreeReg (m6502_reg_a, needpulla);
+    }
+    
+  Safe_free (newaop->aopu.aop_dir);
+  Safe_free (newaop);
+
+  emitComment (TRACEGEN|VVDBG, "      preparePointer: prepoff=%d  G.off=%d", prepTempOfs, _G.tempOfs);
+
+  wassertl (_G.tempOfs <= NUM_TEMP_REGS, "preparePointer(): overflow");
+  return prepTempOfs;
+}
+
+static void unpreparePointer()
+{
+  emitComment (TRACEGEN|VVDBG, "      unpreparePointer: prepoff=%d  G.off=%d", prepTempOfs, _G.tempOfs);
+
+  if (prepTempOfs >= 0)
+    {
+      loadRegTemp(NULL);
+      loadRegTemp(NULL);
+      prepTempOfs = -2;
+    }
+}
+
+/*-----------------------------------------------------------------*/
+/* genPointerGet - generate code for pointer get                   */
+/*-----------------------------------------------------------------*/
+static void
+genPointerGet (iCode * ic, iCode * ifx)
+{
+  operand *left = IC_LEFT (ic);
+  operand *right = IC_RIGHT (ic);
+  operand *result = IC_RESULT (ic);
+  int size, offset;
+  int litOffset = 0;
+  char * rematOffset = NULL;
+  sym_link *retype = getSpec (operandType (result));
+  bool needpulla = false;
+  // TODO? bool vol = false;
+  int tIdx;
+
+  emitComment (TRACEGEN, __func__);
+ 
+  // result = right (remat+literal_offset) + left (register offset)
+ 
+  size = getSize (operandType (result));
+
+  if (size > 1)
+    ifx = NULL;
+
+  aopOp (left, ic, false);
+
+  /* if left is rematerialisable */
+  if (AOP_TYPE (left) == AOP_IMMD || AOP_TYPE (left) == AOP_LIT)
+    {
+      /* if result is not bit variable type */
+      if (!IS_BITVAR (retype))
+          genDataPointerGet (left, right, result, ic, ifx);
+      else
+          genUnpackBitsImmed (left, right, result, ic, ifx);
+          return;
+    }
+
+  aopOp (result, ic, false);
+
+  /* if bit then unpack */
+  if (IS_BITVAR (retype))
+    {
+      genUnpackBits (result, left, right, ifx);
+      goto release;
+    }
+
+  // TODO? 
+  aopOp (right, ic, false);
+
+  decodePointerOffset (right, &litOffset, &rematOffset);
+
+  emitComment (TRACEGEN|VVDBG,"   %s -   res: %s ", __func__, aopName(AOP(result)));
+  emitComment (TRACEGEN|VVDBG,"   %s -  left: %s ", __func__, aopName(AOP(left)));
+  emitComment (TRACEGEN|VVDBG,"   %s - right: %s ", __func__, aopName(AOP(right)));
+
+  /* force offset to signed 16-bit range */
+  litOffset &= 0xffff;
+  if (litOffset & 0x8000)
+    litOffset = 0x10000 - litOffset;
+  
+  emitComment (TRACEGEN|VVDBG, "      genPointerGet (%s) size=%d loff=%d rmoff=%s", 
+               aopName(AOP(left)), size, litOffset, rematOffset );  
+  
+  
+  if (AOP_TYPE (left) == AOP_DIR && !rematOffset && litOffset >= 0 && litOffset <= 256-size) 
+  {
+    // pointer is already in zero page & 8-bit offset
+    emitComment (TRACEGEN|VVDBG, "      genPointerGet - pointer already in zp");
+    bool needloady = storeRegTempIfSurv(m6502_reg_y);
+
+#if 0
+    // seem to make perf worse
+    if (size == 1 && litOffset == 0 
+          && ( /*m6502_reg_x->isDead || */ (m6502_reg_x->isLitConst && m6502_reg_x->litConst == 0) ) ) 
+      {
+      // [aa,x] x == 0
+      loadRegFromConst(m6502_reg_x,0);
+      emit6502op ("lda", "[%s,x]", aopAdrStr ( AOP(left), 0, true ) );
+      storeRegToAop (m6502_reg_a, AOP (result), 0);
+      goto release;
+    }
+#endif
+
+    if (sameRegs(AOP(left), AOP(result)) ) {
+      // pointer and destination is the same - need avoid overwriting
+      emitComment (TRACEGEN|VVDBG, "        genPointerGet - sameregs");
+      needpulla = storeRegTempIfSurv (m6502_reg_a);
+      for (int i=size-1; i>=0; i--) {
+        loadRegFromConst(m6502_reg_y, litOffset + i);
+        emit6502op ("lda", "[*%s],y", AOP(left)->aopu.aop_dir);
+        if(i>1) {
+        storeRegToAop (m6502_reg_a, AOP (result), i);
+        } else if(i==1) {
+          pushReg(m6502_reg_a, false);
+        } else if(i==0) {
+      storeRegToAop (m6502_reg_a, AOP (result), 0);
+          if(size>1) {
+            pullReg(m6502_reg_a);
+            storeRegToAop (m6502_reg_a, AOP (result), 1);
+          }
+        }
+      }
+    } else {
+      // otherwise use [aa],y
+      if (IS_AOP_XA(AOP(result))) {
+        // reverse order so A is last
+        for (int i=size-1; i>=0; i--) {
+          loadRegFromConst(m6502_reg_y, litOffset + i);
+          emit6502op ("lda", "[%s],y", aopAdrStr ( AOP(left), 0, true ) );
+          storeRegToAop (m6502_reg_a, AOP (result), i);
+        }
+      } else {
+        // forward order
+        if (!IS_AOP_WITH_A(AOP(result))) needpulla = storeRegTempIfSurv (m6502_reg_a);
+        for (int i=0; iaopu.aop_reg[1]->isLitConst ) ) )
+#else
+  // index can only be a register
+  if (rematOffset && AOP_TYPE(left) == AOP_REG && 
+      (AOP_SIZE(left) == 1|| AOP(left)->aopu.aop_reg[1]->isLitConst ))
+#endif
+{
+      emitComment (TRACEGEN|VVDBG,"   %s - absolute with 8-bit index", __func__);
+         unsigned int hi_offset=0;
+         char *dst_reg;
+         char idx_reg;
+
+         if(AOP_SIZE(left)==2)
+             hi_offset=(AOP(left)->aopu.aop_reg[1]->litConst)<<8;
+
+         if(AOP_TYPE(left)==AOP_REG) {
+           switch(AOP(left)->aopu.aop_reg[0]->rIdx) {
+             case X_IDX: idx_reg='x'; break;
+             case Y_IDX: idx_reg='y'; break;
+             case A_IDX: idx_reg='A'; break;
+             default: idx_reg='E'; break;
+           }
+         } else {
+           idx_reg='M';
+         }
+ 
+         if(AOP_TYPE(result)==AOP_REG) {
+           switch(AOP(result)->aopu.aop_reg[0]->rIdx) {
+             case A_IDX: dst_reg="lda"; break;
+             case X_IDX: dst_reg="ldx"; break;
+             case Y_IDX: dst_reg="ldy"; break;
+             default: dst_reg="ERROR"; break;
+           }
+         } else {
+           dst_reg="MEM";
+         }
+
+         bool px = false;
+         bool py = false;
+         bool pa = false;
+
+         if(idx_reg=='A' || idx_reg=='M') {
+           if(dst_reg[2]=='y') {
+             px = storeRegTempIfSurv(m6502_reg_x);
+             loadRegFromAop(m6502_reg_x, AOP(left), 0 );
+             idx_reg='x';
+           } else if(dst_reg[2]=='x') {
+             py = storeRegTempIfSurv(m6502_reg_y);
+             loadRegFromAop(m6502_reg_y, AOP(left), 0 );
+             idx_reg='y';
+           } else {
+             // FIXME: should check for a free reg to avoid saving if possible
+             py = storeRegTempIfSurv(m6502_reg_y);
+             loadRegFromAop(m6502_reg_y, AOP(left), 0 );
+             idx_reg='y';
+           }
+           
+         }
+
+         if(dst_reg[2] == idx_reg || dst_reg[0]=='M') {
+//             loadRegFromAop (m6502_reg_a, AOP (right), 0);
+//             dst_reg="lda";
+             pa = storeRegTempIfSurv(m6502_reg_a);
+             emit6502op("lda", "(%s+%d+0x%04x),%c",
+                         rematOffset, litOffset, hi_offset, idx_reg );
+
+            storeRegToAop (m6502_reg_a, AOP (result), 0);
+            loadOrFreeRegTemp(m6502_reg_a,pa);
+         } else {
+           emit6502op(dst_reg, "(%s+%d+0x%04x),%c",
+                     rematOffset, litOffset, hi_offset, idx_reg );
+         }
+
+       loadOrFreeRegTemp(m6502_reg_x,px);
+       loadOrFreeRegTemp(m6502_reg_y,py);
+      loadOrFreeRegTemp (m6502_reg_a, needpulla);
+      goto release;
+  }
+ 
+  // indirect with a 8-bit offset
+  if ( !rematOffset && litOffset>=0 && litOffset<=256-size) {
+      emitComment (TRACEGEN|VVDBG,"   %s - indirect with 8-bit offset", __func__);
+      needpulla = storeRegTempIfSurv (m6502_reg_a);
+      bool needloady = storeRegTempIfSurv(m6502_reg_y);
+      tIdx = _G.tempOfs;
+      if(AOP_TYPE(left) == AOP_REG) {
+        storeRegTemp(AOP(left)->aopu.aop_reg[0] ,true);
+        storeRegTemp(AOP(left)->aopu.aop_reg[1] ,true);
+      } else if(AOP_TYPE(left) == AOP_EXT || AOP_TYPE(left) == AOP_SOF) {
+        loadRegFromAop(m6502_reg_a, AOP(left), 0);
+        storeRegTemp(m6502_reg_a ,true);
+        loadRegFromAop(m6502_reg_a, AOP(left), 1);
+        storeRegTemp(m6502_reg_a ,true);        
+      } else if(AOP_TYPE(left) == AOP_DIR) {
+      
+      } else {
+        emitcode("ERROR","AOP_TYPE=%02x",AOP_TYPE(left));
+      }
+      if(AOP_TYPE(result) == AOP_REG && IS_AOP_XA(AOP(result) )) {
+        // reverse order to prevent overwriting A
+        for (offset=size-1; offset>=0; offset--) {
+          loadRegFromConst(m6502_reg_y, litOffset+offset);
+          emit6502op("lda",TEMPFMT_IY,tIdx);
+          storeRegToAop (m6502_reg_a, AOP (result), offset);      
+        }
+      } else {
+        // normal order
+        for (offset=0; offset(%s+%d)", rematOffset, litOffset);
+  storeRegTemp(m6502_reg_a, true);
+
+
+  if(AOP_TYPE (result) == AOP_REG && size>1) {
+    // special case the 2 bytes registers to avoid overwriting
+          if(size>2) emitcode("ERROR"," size=%d", size);
+            if (IS_AOP_YX (AOP (IC_RESULT (ic))))
+            {
+              loadRegFromConst(m6502_reg_y, 0);
+          emit6502op("lda", TEMPFMT_IY, tIdx);
+          transferRegReg(m6502_reg_a, m6502_reg_x, true);
+              loadRegFromConst(m6502_reg_y, 1);
+          emit6502op("lda", TEMPFMT_IY, tIdx);
+          transferRegReg(m6502_reg_a, m6502_reg_y, true);
+            }
+          else if (IS_AOP_XA (AOP (IC_RESULT (ic))))
+            {
+          loadRegFromConst(m6502_reg_y, 1);
+          emit6502op("lda", TEMPFMT_IY, tIdx);
+          transferRegReg(m6502_reg_a, m6502_reg_x, true);
+          loadRegFromConst(m6502_reg_y, 0);
+          emit6502op("lda", TEMPFMT_IY, tIdx);
+            }
+          else if (IS_AOP_AX (AOP (IC_RESULT (ic)))) // TODO?
+            {
+          loadRegFromConst(m6502_reg_y, 0);
+          emit6502op("lda", TEMPFMT_IY, tIdx);
+          transferRegReg(m6502_reg_a, m6502_reg_x, true);
+          loadRegFromConst(m6502_reg_y, 1);
+          emit6502op("lda", TEMPFMT_IY, tIdx);
+            }
+  } else {
+        for (offset=0; offsetgenerated)
+    {
+      genIfxJump (ifx, "a");
+    }
+}
+
+/*-----------------------------------------------------------------*/
+/* genPackBits - generates code for packed bit storage             */
+/*-----------------------------------------------------------------*/
+static void
+genPackBits (operand * result, operand * left, sym_link * etype, operand * right)
+{
+  int offset = 0;               /* source byte offset */
+  int rlen = 0;                 /* remaining bitfield length */
+  unsigned blen;                /* bitfield length */
+  unsigned bstr;                /* bitfield starting bit within byte */
+  int litval;                   /* source literal value (if AOP_LIT) */
+  unsigned char mask;           /* bitmask within current byte */
+  int litOffset = 0;
+  char *rematOffset = NULL;
+  bool needpulla;
+
+  emitComment (TRACEGEN, __func__);
+
+  decodePointerOffset (left, &litOffset, &rematOffset);
+  blen = SPEC_BLEN (etype);
+  bstr = SPEC_BSTR (etype);
+
+  needpulla = pushRegIfSurv (m6502_reg_a);
+  if (AOP_TYPE (right) == AOP_REG)
+    {
+      /* Not optimal, but works for any register sources. */
+      /* Just push the source values onto the stack and   */
+      /* pull them off any needed. Better optimzed would  */
+      /* be to do some of the shifting/masking now and    */
+      /* push the intermediate result. */
+      if (blen > 8)
+        pushReg (AOP (right)->aopu.aop_reg[1], true);
+      pushReg (AOP (right)->aopu.aop_reg[0], true);
+    }
+  loadRegFromAop (m6502_reg_yx, AOP (result), 0);
+
+  /* If the bitfield length is less than a byte */
+  if (blen < 8)
+    {
+      mask = ((unsigned char) (0xFF << (blen + bstr)) | (unsigned char) (0xFF >> (8 - bstr)));
+
+      if (AOP_TYPE (right) == AOP_LIT)
+        {
+          /* Case with a bitfield length <8 and literal source
+           */
+          litval = (int) ulFromVal (AOP (right)->aopu.aop_lit);
+          litval <<= bstr;
+          litval &= (~mask) & 0xff;
+
+          loadRegIndexed (m6502_reg_a, litOffset, rematOffset);
+          if ((mask | litval) != 0xff)
+            {
+              emit6502op ("and", IMMDFMT, mask);
+            }
+          if (litval)
+            {
+              emit6502op ("ora", IMMDFMT, litval);
+            }
+          m6502_dirtyReg (m6502_reg_a);
+          storeRegIndexed (m6502_reg_a, litOffset, rematOffset);
+
+          pullOrFreeReg (m6502_reg_a, needpulla);
+          return;
+        }
+
+      /* Case with a bitfield length < 8 and arbitrary source
+       */
+      if (AOP_TYPE (right) == AOP_REG)
+        pullReg (m6502_reg_a);
+      else
+        loadRegFromAop (m6502_reg_a, AOP (right), 0);
+      /* shift and mask source value */
+      AccLsh (bstr);
+      emit6502op ("and", IMMDFMT, (~mask) & 0xff);
+      storeRegTemp (m6502_reg_a, true);
+
+      loadRegIndexed (m6502_reg_a, litOffset, rematOffset);
+      emit6502op ("and", IMMDFMT, mask);
+      emit6502op ("ora", TEMPFMT, _G.tempOfs-1);
+      storeRegIndexed (m6502_reg_a, litOffset, rematOffset);
+//      loadRegTemp (m6502_reg_a);
+      loadRegTemp (NULL);
+      // TODO? redundant?
+      pullOrFreeReg (m6502_reg_a, needpulla);
+      return;
+    }
+
+  /* Bit length is greater than 7 bits. In this case, copy  */
+  /* all except the partial byte at the end                 */
+  for (rlen = blen; rlen >= 8; rlen -= 8)
+    {
+      if (!litOffset && !rematOffset && AOP (right)->type == AOP_DIR)
+        {
+	  // FIXME: unimplemented
+          emitcode ("mov", "%s,x+", aopAdrStr (AOP (right), offset, false));
+          litOffset--;
+        }
+      else
+        {
+          if (AOP_TYPE (right) == AOP_REG)
+            pullReg (m6502_reg_a);
+          else
+            loadRegFromAop (m6502_reg_a, AOP (right), offset);
+          storeRegIndexed (m6502_reg_a, litOffset+offset, rematOffset);
+        }
+      offset++;
+    }
+
+  /* If there was a partial byte at the end */
+  if (rlen)
+    {
+      mask = (((unsigned char) - 1 << rlen) & 0xff);
+
+      if (AOP_TYPE (right) == AOP_LIT)
+        {
+          /* Case with partial byte and literal source
+           */
+          litval = (int) ulFromVal (AOP (right)->aopu.aop_lit);
+          litval >>= (blen - rlen);
+          litval &= (~mask) & 0xff;
+          loadRegIndexed (m6502_reg_a, litOffset+offset, rematOffset);
+          if ((mask | litval) != 0xff)
+            {
+              emit6502op ("and", IMMDFMT, mask);
+            }
+          if (litval)
+            {
+              emit6502op ("ora", IMMDFMT, litval);
+            }
+          m6502_dirtyReg (m6502_reg_a);
+          storeRegIndexed (m6502_reg_a, litOffset+offset, rematOffset);
+          pullOrFreeReg (m6502_reg_a, needpulla);
+          return;
+        }
+
+      /* Case with partial byte and arbitrary source
+       */
+      if (AOP_TYPE (right) == AOP_REG)
+        pullReg (m6502_reg_a);
+      else
+        loadRegFromAop (m6502_reg_a, AOP (right), offset);
+      emit6502op ("and", IMMDFMT, (~mask) & 0xff);
+      pushReg (m6502_reg_a, true);
+
+      // FIXME: unimplemented
+      loadRegIndexed(m6502_reg_a, litOffset+offset, rematOffset);
+      emitcode ("and", IMMDFMT, mask);
+//      emitcode ("ora19", "1,s");
+      storeRegTemp(m6502_reg_a, true);
+      emit6502op("pla","");
+      emit6502op("pha","");
+      emit6502op("ora", TEMPFMT, _G.tempOfs-1);
+      loadRegTemp(NULL);
+      storeRegIndexed (m6502_reg_a, litOffset+offset, rematOffset);
+      pullReg (m6502_reg_a);
+    }
+
+  pullOrFreeReg (m6502_reg_a, needpulla);
+}
+
+/*-----------------------------------------------------------------*/
+/* genPackBitsImmed - generates code for packed bit storage        */
+/*-----------------------------------------------------------------*/
+static void
+genPackBitsImmed (operand * result, operand * left, sym_link * etype, operand * right, iCode * ic)
+{
+  asmop *derefaop;
+  int size;
+  int offset = 0;               /* source byte offset */
+  int rlen = 0;                 /* remaining bitfield length */
+  unsigned blen;                /* bitfield length */
+  unsigned bstr;                /* bitfield starting bit within byte */
+  int litval;                   /* source literal value (if AOP_LIT) */
+  unsigned char mask;           /* bitmask within current byte */
+  bool needpulla;
+  int litOffset = 0;
+  char *rematOffset = NULL;
+
+  emitComment (TRACEGEN, __func__);
+
+  blen = SPEC_BLEN (etype);
+  bstr = SPEC_BSTR (etype);
+
+  aopOp (right, ic, false);
+  size = AOP_SIZE (right);
+  decodePointerOffset (left, &litOffset, &rematOffset);
+  wassert (!rematOffset);
+
+  derefaop = aopDerefAop (AOP (result), litOffset);
+  freeAsmop (result, NULL, ic, true);
+  derefaop->size = size;
+
+  /* if the bitfield is a single bit in the direct page */
+  if (blen == 1 && derefaop->type == AOP_DIR)
+    {
+      if (AOP_TYPE (right) == AOP_LIT)
+        {
+          litval = (int) ulFromVal (AOP (right)->aopu.aop_lit);
+	  // FIXME: unimplemented
+          emitcode ((litval & 1) ? "bset" : "bclr", "#%d,%s", bstr, aopAdrStr (derefaop, 0, false));
+        }
+      else
+        {
+          symbol *tlbl1 = safeNewiTempLabel (NULL);
+          symbol *tlbl2 = safeNewiTempLabel (NULL);
+
+	  // FIXME: unimplemented
+          needpulla = pushRegIfSurv (m6502_reg_a);
+          loadRegFromAop (m6502_reg_a, AOP (right), 0);
+          emit6502op ("lsr", "a");
+          emitBranch ("bcs", tlbl1);
+          emitcode ("bclr", "#%d,%s", bstr, aopAdrStr (derefaop, 0, false));
+          emitBranch ("bra", tlbl2);
+          safeEmitLabel (tlbl1);
+          emitcode ("bset", "#%d,%s", bstr, aopAdrStr (derefaop, 0, false));
+          safeEmitLabel (tlbl2);
+          pullOrFreeReg (m6502_reg_a, needpulla);
+        }
+      goto release;
+    }
+
+  /* If the bitfield length is less than a byte */
+  if (blen < 8)
+    {
+      mask = ((unsigned char) (0xFF << (blen + bstr)) | (unsigned char) (0xFF >> (8 - bstr)));
+
+      if (AOP_TYPE (right) == AOP_LIT)
+        {
+          /* Case with a bitfield length <8 and literal source
+           */
+          litval = (int) ulFromVal (AOP (right)->aopu.aop_lit);
+          litval <<= bstr;
+          litval &= (~mask) & 0xff;
+
+          needpulla = pushRegIfSurv (m6502_reg_a);
+          loadRegFromAop (m6502_reg_a, derefaop, 0);
+          if ((mask | litval) != 0xff)
+            {
+              emit6502op ("and", IMMDFMT, mask);
+            }
+          if (litval)
+            {
+              emit6502op ("ora", IMMDFMT, litval);
+            }
+          m6502_dirtyReg (m6502_reg_a);
+          storeRegToAop (m6502_reg_a, derefaop, 0);
+
+          pullOrFreeReg (m6502_reg_a, needpulla);
+          goto release;
+        }
+
+      /* Case with a bitfield length < 8 and arbitrary source
+       */
+      needpulla = pushRegIfSurv (m6502_reg_a);
+      loadRegFromAop (m6502_reg_a, AOP (right), 0);
+      /* shift and mask source value */
+      AccLsh (bstr);
+      emit6502op ("and", IMMDFMT, (~mask) & 0xff);
+      storeRegTemp(m6502_reg_a, true);
+
+      loadRegFromAop (m6502_reg_a, derefaop, 0);
+      emit6502op ("and", IMMDFMT, mask);
+      emit6502op ("ora", TEMPFMT, _G.tempOfs - 1);
+      storeRegToAop (m6502_reg_a, derefaop, 0);
+
+      pullOrFreeReg (m6502_reg_a, needpulla);
+      loadRegTemp(NULL);
+      goto release;
+    }
+
+  /* Bit length is greater than 7 bits. In this case, copy  */
+  /* all except the partial byte at the end                 */
+  for (rlen = blen; rlen >= 8; rlen -= 8)
+    {
+      transferAopAop (AOP (right), offset, derefaop, offset);
+      offset++;
+    }
+
+  /* If there was a partial byte at the end */
+  if (rlen)
+    {
+      mask = (((unsigned char) - 1 << rlen) & 0xff);
+
+      if (AOP_TYPE (right) == AOP_LIT)
+        {
+          /* Case with partial byte and literal source
+           */
+          litval = (int) ulFromVal (AOP (right)->aopu.aop_lit);
+          litval >>= (blen - rlen);
+          litval &= (~mask) & 0xff;
+          needpulla = pushRegIfSurv (m6502_reg_a);
+          loadRegFromAop (m6502_reg_a, derefaop, offset);
+          if ((mask | litval) != 0xff)
+            {
+              emit6502op ("and", IMMDFMT, mask);
+            }
+          if (litval)
+            {
+              emit6502op ("ora", IMMDFMT, litval);
+            }
+          m6502_dirtyReg (m6502_reg_a);
+          storeRegToAop (m6502_reg_a, derefaop, offset);
+          m6502_dirtyReg (m6502_reg_a);
+          pullOrFreeReg (m6502_reg_a, needpulla);
+          goto release;
+        }
+
+      /* Case with partial byte and arbitrary source
+       */
+      needpulla = pushRegIfSurv (m6502_reg_a);
+      loadRegFromAop (m6502_reg_a, AOP (right), offset);
+      emit6502op ("and", IMMDFMT, (~mask) & 0xff);
+      storeRegTemp (m6502_reg_a, true);
+
+      loadRegFromAop (m6502_reg_a, derefaop, offset);
+      emit6502op ("and", IMMDFMT, mask);
+      emit6502op ("ora", TEMPFMT, _G.tempOfs - 1);
+      storeRegToAop (m6502_reg_a, derefaop, offset);
+      pullOrFreeReg (m6502_reg_a, needpulla);
+      loadRegTemp (NULL);
+    }
+
+  m6502_freeReg (m6502_reg_a);
+
+release:
+  freeAsmop (right, NULL, ic, true);
+  freeAsmop (NULL, derefaop, ic, true);
+}
+
+/*-----------------------------------------------------------------*/
+/* genDataPointerSet - remat pointer to data space                 */
+/*-----------------------------------------------------------------*/
+static void
+genDataPointerSet (operand * left, operand * right, operand * result, iCode * ic)
+{
+  int size;
+  asmop *derefaop;
+  int litOffset = 0;
+  char *rematOffset = NULL;
+
+  emitComment (TRACEGEN, __func__);
+
+  aopOp (right, ic, false);
+  size = AOP_SIZE (right);
+  decodePointerOffset (left, &litOffset, &rematOffset);
+  wassert (!rematOffset);
+
+  derefaop = aopDerefAop (AOP (result), litOffset);
+  freeAsmop (result, NULL, ic, true);
+  derefaop->size = size;
+
+      while (size--)
+        {
+          transferAopAop (AOP (right), size, derefaop, size);
+    }
+
+  freeAsmop (right, NULL, ic, true);
+  freeAsmop (NULL, derefaop, ic, true);
+}
+
+
+/*-----------------------------------------------------------------*/
+/* genPointerSet - stores the value into a pointer location        */
+/*-----------------------------------------------------------------*/
+static void
+genPointerSet (iCode * ic)
+{
+  operand *left = IC_LEFT (ic);
+  operand *right = IC_RIGHT (ic);
+  operand *result = IC_RESULT (ic);
+  int size, offset;
+  sym_link *retype = getSpec (operandType (right));
+  sym_link *letype = getSpec (operandType (result));
+  bool needpulla = false;
+  bool needpullx = false;
+  bool needpully = false;
+//  bool vol = false;
+  int litOffset = 0;
+  char *rematOffset = NULL;
+
+  emitComment (TRACEGEN, __func__);
+  
+  // *(result (reg) + left (rematoffset+litoffset) = right
+
+  
+  aopOp (result, ic, false);
+
+  /* if the result is rematerializable */
+  if (AOP_TYPE (result) == AOP_IMMD || AOP_TYPE (result) == AOP_LIT)
+    {
+      if (!IS_BITVAR (retype) && !IS_BITVAR (letype))
+          genDataPointerSet (left, right, result, ic);
+      else
+          genPackBitsImmed (result, left, (IS_BITVAR (retype) ? retype : letype), right, ic);
+          return;
+    }
+
+  aopOp (right, ic, false);
+  //aopOp (left, ic, false);
+
+  size = AOP_SIZE (right);
+
+  decodePointerOffset (left, &litOffset, &rematOffset);
+
+  emitComment (TRACEGEN|VVDBG,"   %s -   res: %s ", __func__, aopName(AOP(result)));
+//  emitComment (TRACEGEN|VVDBG,"   %s -  left: %s ", __func__, aopName(AOP(left)));
+  emitComment (TRACEGEN|VVDBG,"   %s - right: %s ", __func__, aopName(AOP(right)));
+
+  emitComment (TRACEGEN|VVDBG, "      genPointerSet (%s), size=%d, litoffset=%d, rematoffset=%s", 
+               aopName(AOP(right)), size, litOffset, rematOffset );
+
+  // shortcut for [aa],y (or [aa,x]) if already in zero-page
+  // and we're not storing to the same pointer location
+
+  if (!(IS_BITVAR (retype) || IS_BITVAR (letype))
+      && AOP_TYPE (result) == AOP_DIR && !rematOffset && litOffset >= 0 && litOffset <= 256-size
+      && !sameRegs(AOP(right), AOP(result)) ) {
+  
+#if 0
+    if (size == 1 && litOffset == 0 && m6502_reg_x->isLitConst && m6502_reg_x->litConst == 0) {
+      // use [aa,x] if only 1 byte and offset is 0
+      loadRegFromAop (m6502_reg_a, AOP (right), 0);
+      emit6502op ("sta", "[%s,x]", aopAdrStr ( AOP(result), 0, true ) );
+    } 
+    else
+#endif
+    {
+      needpulla = storeRegTempIfSurv (m6502_reg_a);
+      needpully = storeRegTempIfUsed (m6502_reg_y);
+
+      if (IS_AOP_AX(AOP(right))) {
+        // reverse order so A is first
+        for (int i=size-1; i>=0; i--) {
+          loadRegFromAop (m6502_reg_a, AOP (right), i);
+          loadRegFromConst(m6502_reg_y, litOffset + i);
+          emit6502op ("sta", "[%s],y", aopAdrStr ( AOP(result), 0, true ) );
+        }
+      } else {
+        // forward order
+        for (int i=0; iaopu.aop_reg[1]->isLitConst ) ) )
+#else
+    // abs,x or abs,y with index in register
+  if (rematOffset && AOP_TYPE(result)== AOP_REG
+           && ( AOP_SIZE(result) == 1 || AOP(result)->aopu.aop_reg[1]->isLitConst ) )
+#endif
+      {
+      emitComment (TRACEGEN|VVDBG,"   %s - absolute with 8-bit index", __func__);
+      emitComment(TRACEGEN|VVDBG," reg : %d  size:%d", AOP(result)->aopu.aop_reg[0]->rIdx,  AOP_SIZE(result) );
+
+      emitComment (TRACEGEN|VVDBG,"AOP TYPE(result)=%d",AOP_TYPE (result));
+      emitComment (TRACEGEN|VVDBG,"AOP(result) reg=%d",AOP(result)->aopu.aop_reg[0]->rIdx);
+         unsigned int hi_offset=0;
+         bool src_reg_is_y = false;
+         char idx_reg;
+         bool px = false;
+         bool py = false;
+         bool pa = false;
+
+         pa=pushRegIfSurv(m6502_reg_a);
+
+
+         if(AOP_SIZE(result)==2)
+             hi_offset=(AOP(result)->aopu.aop_reg[1]->litConst)<<8;
+
+//  if ( ( AOP_TYPE(result) == AOP_REG && AOP(result)->aopu.aop_reg[0]->isLitConst ) )
+//	emitcode("ERROR","");
+
+
+         if(AOP_TYPE(result)==AOP_REG) {
+           switch(AOP(result)->aopu.aop_reg[0]->rIdx) {
+             case X_IDX: idx_reg='x'; break;
+             case Y_IDX: idx_reg='y'; break;
+             case A_IDX: idx_reg='A'; break;
+             default: idx_reg='E'; break;
+           }
+         } else {
+           idx_reg='M';
+         }
+
+         if(AOP_TYPE(right)==AOP_REG 
+            && AOP(right)->aopu.aop_reg[0]->rIdx == Y_IDX ) 
+               src_reg_is_y = true;
+
+         if(idx_reg=='A' || idx_reg=='M') {
+           if(src_reg_is_y) {
+             px = storeRegTempIfSurv(m6502_reg_x);
+             loadRegFromAop(m6502_reg_x, AOP(result), 0 );
+             idx_reg='x';
+           } else {
+             py = storeRegTempIfSurv(m6502_reg_y);
+             loadRegFromAop(m6502_reg_y, AOP(result), 0 );
+             idx_reg='y';
+           }
+         }
+
+             loadRegFromAop (m6502_reg_a, AOP (right), 0);
+
+         emit6502op("sta", "(%s+%d+0x%04x),%c",
+                     rematOffset, litOffset, hi_offset, idx_reg );
+
+       pullOrFreeReg(m6502_reg_a, pa);
+       loadOrFreeRegTemp(m6502_reg_x,px);
+       loadOrFreeRegTemp(m6502_reg_y,py);
+
+       goto release;
+     } 
+
+
+  // general case
+  needpulla = storeRegTempIfSurv (m6502_reg_a);
+  needpullx = storeRegTempIfSurv (m6502_reg_x);
+  needpully = storeRegTempIfSurv (m6502_reg_y);
+  int tIdx;
+
+  if(needpulla) m6502_reg_a->isFree=false;
+
+  // general case
+
+  /* if bit then pack */
+  if (IS_BITVAR (retype) || IS_BITVAR (letype))
+    {
+      //int ptrofs =
+      preparePointer (result, litOffset, rematOffset, right);
+      genPackBits (result, left, (IS_BITVAR (retype) ? retype : letype), right);
+      unpreparePointer();
+      goto release;
+    }
+
+#if 0
+  bool savea = false;
+  if(!m6502_reg_a->isFree) {
+      savea = true;
+      transferRegReg(m6502_reg_a, m6502_reg_y, true);
+  }
+#endif
+
+    tIdx = _G.tempOfs;
+    bool pa=pushRegIfUsed(m6502_reg_a);
+  if(!rematOffset && !litOffset) {
+     // just register content, no remat and no offset
+     if(AOP_TYPE(result)==AOP_REG) {
+       // already in registers just save to TEMP
+       storeRegTemp(AOP(result)->aopu.aop_reg[0], true);
+       storeRegTemp(AOP(result)->aopu.aop_reg[1], true);
+     } else {
+       loadRegFromAop(m6502_reg_a, AOP(result), 0);
+       storeRegTemp(m6502_reg_a, true);
+       loadRegFromAop(m6502_reg_a, AOP(result), 1);
+       storeRegTemp(m6502_reg_a, true);
+     }
+  } else {
+    if(!rematOffset || rematOffset[0]==0)
+       rematOffset="0";
+
+    emit6502op ("clc", "");
+    loadRegFromAop(m6502_reg_a, AOP(result), 0);
+    emit6502op ("adc", "#<(%s+%d)", rematOffset, litOffset);
+    storeRegTemp(m6502_reg_a, true);
+    loadRegFromAop(m6502_reg_a, AOP(result), 1);
+    emit6502op ("adc", "#>(%s+%d)", rematOffset, litOffset);
+    storeRegTemp(m6502_reg_a, true);
+  }
+
+    pullOrFreeReg(m6502_reg_a,pa);
+//  if(savea) transferRegReg(m6502_reg_y, m6502_reg_a, true);
+
+
+    if (IS_AOP_YX (AOP(right)) || IS_AOP_AX (AOP(right)))
+          {
+            // reverse order to avoid overwriting A or Y
+            loadRegFromAop (m6502_reg_a, AOP (right), 1);
+            loadRegFromConst(m6502_reg_y, 1);
+            emit6502op("sta",TEMPFMT_IY,tIdx);
+            loadRegFromAop (m6502_reg_a, AOP (right), 0);
+            loadRegFromConst(m6502_reg_y, 0);
+            emit6502op("sta",TEMPFMT_IY,tIdx);
+          }
+ else
+ {
+    for (offset=0; offsetaopu.aop_lit);
+      freeAsmop (cond, NULL, ic, true);
+
+      /* if there was something to be popped then do it */
+      if (popIc)
+        genIpop (popIc);
+      if (lit)
+        {
+          if (IC_TRUE (ic))
+            emitBranch ("jmp", IC_TRUE (ic));
+        }
+      else
+        {
+          if (IC_FALSE (ic))
+            emitBranch ("jmp", IC_FALSE (ic));
+        }
+      ic->generated = 1;
+      return;
+    }
+
+  /* evaluate the operand */
+  if (AOP_TYPE (cond) != AOP_CRY) {
+    emitComment (TRACEGEN|VVDBG, "     genIfx - !AOP_CRY");
+    asmopToBool (AOP (cond), false);
+  }
+  /* the result is now in the z flag bit */
+  freeAsmop (cond, NULL, ic, true);
+
+  /* if there was something to be popped then do it */
+  if (popIc)
+      genIpop (popIc);
+
+// TODO: redundant bne/beq 
+  emitComment (TRACEGEN|VVDBG, "      genIfx - call jump");
+  genIfxJump (ic, "a");
+
+  ic->generated = 1;
+}
+
+/*-----------------------------------------------------------------*/
+/* genAddrOf - generates code for address of                       */
+/*-----------------------------------------------------------------*/
+static void
+genAddrOf (iCode * ic)
+{
+  symbol *sym = OP_SYMBOL (IC_LEFT (ic));
+  //  asmop *aopr;
+  int size, offset;
+  bool needpulla, needpullx;
+  struct dbuf_s dbuf;
+
+  emitComment (TRACEGEN, __func__);
+
+  aopOp (IC_RESULT (ic), ic, false);
+  //  aopr = AOP (IC_RESULT (ic));
+
+  /* if the operand is on the stack then we
+     need to get the stack offset of this
+     variable */
+  if (sym->onStack)
+    {
+      needpulla = pushRegIfSurv (m6502_reg_a);
+      needpullx = pushRegIfSurv (m6502_reg_x);
+      /* if it has an offset then we need to compute it */
+      offset = _G.stackOfs + _G.stackPushes + sym->stack + 1;
+      m6502_useReg (m6502_reg_xa);
+      emit6502op ("tsx", "");
+      m6502_dirtyReg (m6502_reg_x);
+      offset=smallAdjustReg(m6502_reg_x, offset);
+      transferRegReg (m6502_reg_x, m6502_reg_a, true);
+      if (offset) {
+          emit6502op ("clc", "");
+          emit6502op ("adc", IMMDFMT, offset&0xff);
+      }
+      loadRegFromConst(m6502_reg_x, 0x01); // stack top = 0x100
+      storeRegToFullAop (m6502_reg_xa, AOP (IC_RESULT (ic)), false);
+      pullOrFreeReg (m6502_reg_x, needpullx);
+      pullOrFreeReg (m6502_reg_a, needpulla);
+      goto release;
+    }
+
+  /* object not on stack then we need the name */
+  size = AOP_SIZE (IC_RESULT (ic));
+  offset = 0;
+
+  while (size--)
+    {
+      dbuf_init (&dbuf, 64);
+      switch (offset)
+        {
+        case 0:
+          dbuf_printf (&dbuf, "#%s", sym->rname);
+          break;
+        case 1:
+          dbuf_printf (&dbuf, "#>%s", sym->rname);
+          break;
+        default:
+          dbuf_printf (&dbuf, "#0");
+        }
+      storeImmToAop (dbuf_detach_c_str (&dbuf), AOP (IC_RESULT (ic)), offset++);
+    }
+
+release:
+  freeAsmop (IC_RESULT (ic), NULL, ic, true);
+}
+
+/*-----------------------------------------------------------------*/
+/* genAssignLit - Try to generate code for literal assignment.     */
+/*                result and right should already be asmOped       */
+/*-----------------------------------------------------------------*/
+static bool
+genAssignLit (operand * result, operand * right)
+{
+  char assigned[8];
+  unsigned char value[sizeof(assigned)];
+  int size;
+  int offset,offset2;
+
+  emitComment (TRACEGEN, __func__);
+
+  /* Make sure this is a literal assignment */
+  if (AOP_TYPE (right) != AOP_LIT)
+    return false;
+
+  /* The general case already handles register assignment well */
+  if (AOP_TYPE (result) == AOP_REG)
+    return false;
+
+  /* Some hardware registers require MSB to LSB assignment order */
+  /* so don't optimize the assignment order if volatile */
+  if (isOperandVolatile (result, false))
+    return false;
+
+  /* Make sure the assignment is not larger than we can handle */
+  size = AOP_SIZE (result);
+  if (size > sizeof(assigned))
+    return false;
+
+  for (offset=0; offsetaopu.aop_lit, offset);
+    }
+
+  for (offset=0; offsetisFree ? m6502_reg_x : m6502_reg_y;
+        needpullind = pushRegIfSurv (indreg);
+        /* get the condition into indreg */
+        loadRegFromAop (indreg, AOP (IC_JTCOND (ic)), 0);
+      }
+      freeAsmop (IC_JTCOND (ic), NULL, ic, true);
+
+          if (indreg == m6502_reg_x) {
+            emit6502op ("lda", "%05d$,x", safeLabelKey2num (jtablo->key));
+            storeRegTemp (m6502_reg_a, true);
+            emit6502op ("lda", "%05d$,x", safeLabelKey2num (jtabhi->key));
+            storeRegTemp (m6502_reg_a, true);
+          } else {
+            emit6502op ("lda", "%05d$,y", safeLabelKey2num (jtablo->key));
+            storeRegTemp (m6502_reg_a, true);
+            emit6502op ("lda", "%05d$,y", safeLabelKey2num (jtabhi->key));
+            storeRegTemp (m6502_reg_a, true);
+          }
+      loadRegTemp(NULL);
+      loadRegTemp(NULL);
+      if (needpullind) pullReg(indreg);
+      if (needpulla) pullReg(m6502_reg_a);
+      emit6502op ("jmp", TEMPFMT_IND, _G.tempOfs);
+
+      m6502_dirtyReg (m6502_reg_a);
+      m6502_dirtyReg (m6502_reg_x);
+      m6502_dirtyReg (m6502_reg_y);
+      m6502_freeReg (m6502_reg_a);
+      m6502_freeReg (m6502_reg_x);
+      m6502_freeReg (m6502_reg_y);
+    }
+
+  /* now generate the jump labels */
+  safeEmitLabel (jtablo);
+  // FIXME: add this to gen6502op
+  for (jtab = setFirstItem (IC_JTLABELS (ic)); jtab; jtab = setNextItem (IC_JTLABELS (ic)))
+    {
+      emitcode (".db", "%05d$", labelKey2num (jtab->key));
+      regalloc_dry_run_cost_bytes++;
+    }
+  safeEmitLabel (jtabhi);
+  for (jtab = setFirstItem (IC_JTLABELS (ic)); jtab; jtab = setNextItem (IC_JTLABELS (ic)))
+    {
+      emitcode (".db", ">%05d$", labelKey2num (jtab->key));
+      regalloc_dry_run_cost_bytes++;
+    }
+}
+
+/*-----------------------------------------------------------------*/
+/* genCast - generate code for cast                                */
+/*-----------------------------------------------------------------*/
+static void
+genCast (iCode * ic)
+{
+  operand *result = IC_RESULT (ic);
+  sym_link *rtype = operandType (IC_RIGHT (ic));
+  operand *right = IC_RIGHT (ic);
+  int size, offset;
+  bool signExtend;
+  bool save_a;
+
+  emitComment (TRACEGEN, __func__);
+
+  /* if they are equivalent then do nothing */
+  if (operandsEqu (IC_RESULT (ic), IC_RIGHT (ic)))
+    return;
+
+  aopOp (right, ic, false);
+  aopOp (result, ic, false);
+
+  emitComment (TRACEGEN|VVDBG, "      genCast - size %d -> %d", right?AOP_SIZE(right):0, result?AOP_SIZE(result):0);
+
+  if (IS_BOOL (operandType (result)))
+    {
+      bool needpulla = pushRegIfSurv (m6502_reg_a);
+      asmopToBool (AOP (right), true);
+      storeRegToAop (m6502_reg_a, AOP (result), 0);
+      pullOrFreeReg (m6502_reg_a, needpulla);
+      goto release;
+    }
+
+  /* If the result is 1 byte, then just copy the one byte; there is */
+  /* nothing special required. */
+  if (AOP_SIZE (result) == 1)
+    {
+      transferAopAop (AOP (right), 0, AOP (result), 0);
+      goto release;
+    }
+
+  signExtend = AOP_SIZE (result) > AOP_SIZE (right) && !IS_BOOL (rtype) && IS_SPEC (rtype) && !SPEC_USIGN (rtype);
+
+  /* If the result is 2 bytes and in registers, we have to be careful */
+  /* to make sure the registers are not overwritten prematurely. */
+  if (AOP_SIZE (result) == 2 && AOP (result)->type == AOP_REG)
+    {
+      if (IS_AOP_YX (AOP (result)) && (AOP_SIZE (right) == 2))
+        {
+          loadRegFromAop (m6502_reg_yx, AOP (right), 0);
+          goto release;
+        }
+
+      if (AOP_SIZE (right) == 1)
+        {
+          transferAopAop (AOP (right), 0, AOP (result), 0);
+          if (!signExtend)
+            {
+              storeConstToAop (0, AOP (result), 1);
+            }
+          else
+            {
+              save_a = (AOP (result)->aopu.aop_reg[0] == m6502_reg_a || !m6502_reg_a->isDead);
+
+              /* we need to extend the sign :{ */
+              // TODO: try to avoid doing this
+              if (save_a)
+                pushReg(m6502_reg_a, false);
+              if (AOP (result)->aopu.aop_reg[0] != m6502_reg_a)
+                loadRegFromAop (m6502_reg_a, AOP (right), 0);
+              signExtendA();
+              storeRegToAop (m6502_reg_a, AOP (result), 1);
+              if (save_a)
+                pullReg(m6502_reg_a);
+            }
+          goto release;
+        }
+
+      if (AOP (right)->type == AOP_REG)
+        {
+          wassert (AOP_SIZE (right) == 2);
+          /* Source and destination are the same size; no need for sign */
+          /* extension or zero padding. Just copy in the order that */
+          /* won't prematurely overwrite the source. */
+          if (AOP (result)->aopu.aop_reg[0] == AOP (right)->aopu.aop_reg[1])
+            {
+              transferAopAop (AOP (right), 1, AOP (result), 1);
+              transferAopAop (AOP (right), 0, AOP (result), 0);
+            }
+          else
+            {
+              transferAopAop (AOP (right), 0, AOP (result), 0);
+              transferAopAop (AOP (right), 1, AOP (result), 1);
+            }
+          goto release;
+        }
+      else
+        {
+          /* Source is at least 2 bytes and not in registers; no need */
+          /* for sign extension or zero padding. Just copy. */
+          transferAopAop (AOP (right), 0, AOP (result), 0);
+          transferAopAop (AOP (right), 1, AOP (result), 1);
+          goto release;
+        }
+    }
+
+  wassert (AOP (result)->type != AOP_REG);
+  
+  save_a = !m6502_reg_a->isDead && signExtend;
+  if (save_a)
+    pushReg(m6502_reg_a, true);
+
+  offset = 0;
+  size = AOP_SIZE (right);
+  if (AOP_SIZE (result) < size)
+    size = AOP_SIZE (result);
+  while (size)
+    {
+      if (size == 1 && signExtend)
+        {
+          loadRegFromAop (m6502_reg_a, AOP (right), offset);
+          storeRegToAop (m6502_reg_a, AOP (result), offset);
+          offset++;
+          size--;
+        }
+      else if ((size > 2 || size >= 2 && !signExtend) && m6502_reg_y->isDead && m6502_reg_x->isDead && 
+        (AOP_TYPE (right) == AOP_IMMD || IS_MOS65C02 && AOP_TYPE (right) == AOP_EXT) &&
+        (AOP_TYPE (result) == AOP_DIR || IS_MOS65C02 && AOP_TYPE (result) == AOP_EXT))
+        {
+          // FIXME: the above exception for 65C02 is likely incorrect
+          loadRegFromAop (m6502_reg_yx, AOP (right), offset);
+          storeRegToAop (m6502_reg_yx, AOP (result), offset);
+          offset += 2;
+          size -= 2;
+        }
+      else
+        {
+          transferAopAop (AOP (right), offset, AOP (result), offset);
+          offset++;
+          size--;
+        }
+    }
+
+  size = AOP_SIZE (result) - offset;
+  if (size && !signExtend)
+    {
+      while (size--)
+        storeConstToAop (0, AOP (result), offset++);
+    }
+  else if (size)
+    {
+      signExtendA();
+      while (size--)
+        storeRegToAop (m6502_reg_a, AOP (result), offset++);
+    }
+
+  if (save_a)
+    pullReg(m6502_reg_a);
+
+  /* we are done hurray !!!! */
+
+release:
+  freeAsmop (right, NULL, ic, true);
+  freeAsmop (result, NULL, ic, true);
+
+}
+
+/*-----------------------------------------------------------------*/
+/* genReceive - generate code for a receive iCode                  */
+/*-----------------------------------------------------------------*/
+static void
+genReceive (iCode * ic)
+{
+  int size;
+  int offset;
+  bool delayed_x = false;
+
+  emitComment (TRACEGEN, __func__);
+
+  aopOp (IC_RESULT (ic), ic, false);
+  size = AOP_SIZE (IC_RESULT (ic));
+  offset = 0;
+
+  if (ic->argreg && IS_AOP_YX (AOP (IC_RESULT (ic))) && (offset + (ic->argreg - 1)) == 0)
+    {
+      storeRegTemp (m6502_reg_x, true);
+      transferRegReg (m6502_reg_a, m6502_reg_x, true);
+      loadRegTemp (m6502_reg_y);
+    }
+  else if (ic->argreg)
+    {
+      while (size--)
+        {
+          if (AOP_TYPE (IC_RESULT (ic)) == AOP_REG && !(offset + (ic->argreg - 1)) && AOP (IC_RESULT (ic))->aopu.aop_reg[0]->rIdx == X_IDX && size)
+            {
+              storeRegTemp (m6502_reg_a, true);
+              delayed_x = true;
+            }
+          else
+            transferAopAop (m6502_aop_pass[offset + (ic->argreg - 1)], 0, AOP (IC_RESULT (ic)), offset);
+          if (m6502_aop_pass[offset]->type == AOP_REG)
+            m6502_freeReg (m6502_aop_pass[offset]->aopu.aop_reg[0]);
+          offset++;
+        }
+    }
+
+  if (delayed_x)
+    loadRegTemp (m6502_reg_x);
+
+  freeAsmop (IC_RESULT (ic), NULL, ic, true);
+}
+
+// support routine for genDummyRead
+static void
+dummyRead (iCode* ic, operand* op, reg_info* reg)
+{
+  if (op && IS_SYMOP (op))
+    {
+      aopOp (op, ic, false);
+      int size = AOP_SIZE (op);
+      for (int offset=0; offsetisspilt)
+        {
+	  /* If only used by IFX, there might not be any register assigned */
+          int i;
+          for(i = 0; i < sym->nRegs; i++)
+            if (sym->regs[i])
+              m6502_useReg (sym->regs[i]);
+        }
+    }
+}
+
+/*---------------------------------------------------------------------*/
+/* genm6502iCode - generate code for M6502 based controllers for a single iCode instruction */
+/*---------------------------------------------------------------------*/
+static void
+genm6502iCode (iCode *ic)
+  {
+    int i;
+    reg_info *reg;
+
+    initGenLineElement ();
+    genLine.lineElement.ic = ic;
+
+#if 0
+  if (!regalloc_dry_run)
+    printf ("ic %d op %d stack pushed %d\n", ic->key, ic->op, G.stack.pushed);
+#endif
+
+  if (resultRemat (ic))
+    {
+      if (!regalloc_dry_run)
+        emitComment(TRACEGEN, "skipping iCode since result will be rematerialized");
+      return;
+    }
+
+  if (ic->generated)
+    {
+      if (!regalloc_dry_run)
+        emitComment(TRACEGEN, "skipping generated iCode");
+      return;
+    }
+
+    for (i = A_IDX; i <= XA_IDX; i++)
+      {
+        reg = m6502_regWithIdx (i);
+        //if (reg->aop)
+        //  emitcode ("", "; %s = %s offset %d", reg->name, aopName (reg->aop), reg->aopofs);
+        reg->isFree = true;
+        if (regalloc_dry_run)
+          reg->isLitConst = 0;
+      }
+
+    if (ic->op == IFX)
+      updateiTempRegisterUse (IC_COND (ic));
+    else if (ic->op == JUMPTABLE)
+      updateiTempRegisterUse (IC_JTCOND (ic));
+    else if (ic->op == RECEIVE)
+      {
+        m6502_useReg (m6502_reg_a);
+        m6502_useReg (m6502_reg_x); // TODO: x really is free if function only receives 1 byte
+      }
+    else
+      {
+        if (POINTER_SET (ic))
+          updateiTempRegisterUse (IC_RESULT (ic));
+        updateiTempRegisterUse (IC_LEFT (ic));
+        updateiTempRegisterUse (IC_RIGHT (ic));
+      }
+
+    for (i = A_IDX; i <= Y_IDX; i++)
+      {
+        if (bitVectBitValue (ic->rSurv, i))
+          {
+            m6502_regWithIdx (i)->isDead = false;
+            m6502_regWithIdx (i)->isFree = false;
+          }
+        else
+          m6502_regWithIdx (i)->isDead = true;
+      }
+
+  /* depending on the operation */
+  switch (ic->op)
+    {
+    case '!':
+      genNot (ic);
+      break;
+
+    case '~':
+      genCpl (ic);
+      break;
+
+    case UNARYMINUS:
+          genUminus (ic);
+          break;
+
+    case IPUSH:
+          genIpush (ic);
+          break;
+
+    case IPOP:
+      /* IPOP happens only when trying to restore a
+         spilt live range, if there is an ifx statement
+         following this pop then the if statement might
+         be using some of the registers being popped which
+         would destory the contents of the register so
+         we need to check for this condition and handle it */
+      if (ic->next && ic->next->op == IFX && regsInCommon (IC_LEFT (ic), IC_COND (ic->next)))
+        genIfx (ic->next, ic);
+      else
+        genIpop (ic);
+      break;
+
+    case CALL:
+      genCall (ic);
+      break;
+
+    case PCALL:
+      genPcall (ic);
+      break;
+
+    case FUNCTION:
+      genFunction (ic);
+      break;
+
+    case ENDFUNCTION:
+      genEndFunction (ic);
+      break;
+
+    case RETURN:
+      genRet (ic);
+      break;
+
+    case LABEL:
+      genLabel (ic);
+      break;
+
+    case GOTO:
+      genGoto (ic);
+      break;
+
+    case '+':
+      genPlus (ic);
+      break;
+
+    case '-':
+      genMinus (ic);
+      break;
+
+    case '*':
+      genMult (ic);
+      break;
+
+    case '/':
+      genDiv (ic);
+      break;
+
+    case '%':
+      genMod (ic);
+      break;
+
+    case '>':
+    case '<':
+    case LE_OP:
+    case GE_OP:
+      genCmp (ic, ifxForOp (IC_RESULT (ic), ic));
+      break;
+
+    case NE_OP:
+    case EQ_OP:
+      genCmpEQorNE (ic, ifxForOp (IC_RESULT (ic), ic));
+      break;
+
+    case AND_OP:
+      genAndOp (ic);
+      break;
+
+    case OR_OP:
+      genOrOp (ic);
+      break;
+
+    case '^':
+      genXor (ic, ifxForOp (IC_RESULT (ic), ic));
+      break;
+
+    case '|':
+      genOr (ic, ifxForOp (IC_RESULT (ic), ic));
+      break;
+
+    case BITWISEAND:
+      genAnd (ic, ifxForOp (IC_RESULT (ic), ic));
+      break;
+
+    case INLINEASM:
+      m6502_genInline (ic);
+      break;
+
+    case RRC:
+      genRRC (ic);
+      break;
+
+    case RLC:
+      genRLC (ic);
+      break;
+
+    case SWAP:
+    case GETABIT:
+    case GETBYTE:
+    case GETWORD:
+      wassertl (0, "Unimplemented iCode");
+      break;
+
+    case LEFT_OP:
+      genLeftShift (ic);
+      break;
+
+    case RIGHT_OP:
+      genRightShift (ic);
+      break;
+
+    case GET_VALUE_AT_ADDRESS:
+      genPointerGet (ic, NULL); // TODO? ifxForOp (IC_RESULT (ic), ic));
+      break;
+
+   case SET_VALUE_AT_ADDRESS:
+      genPointerSet (ic);
+      break;
+
+    case '=':
+      if (POINTER_SET (ic))
+        genPointerSet (ic);
+      else
+        genAssign (ic);
+      break;
+
+    case IFX:
+      genIfx (ic, NULL);
+      break;
+
+    case ADDRESS_OF:
+      genAddrOf (ic);
+      break;
+
+    case JUMPTABLE:
+      genJumpTab (ic);
+      break;
+
+    case CAST:
+      genCast (ic);
+      break;
+
+    case RECEIVE:
+      genReceive (ic);
+      break;
+
+    case SEND:
+      if (!regalloc_dry_run)
+        addSet (&_G.sendSet, ic);
+      else
+        {
+          set * sendSet = NULL;
+          addSet (&sendSet, ic);
+          genSend (sendSet);
+          deleteSet (&sendSet);
+        }
+      break;
+
+    case DUMMY_READ_VOLATILE:
+      genDummyRead (ic);
+      break;
+
+    case CRITICAL:
+      genCritical (ic);
+      break;
+
+    case ENDCRITICAL:
+      genEndCritical (ic);
+      break;
+
+    default:
+      wassertl (0, "Unknown iCode");
+    }
+}
+
+static void
+init_aop_pass(void)
+{
+  if (m6502_aop_pass[0])
+    return;
+
+  m6502_aop_pass[0] = newAsmop (AOP_REG);
+  m6502_aop_pass[0]->size = 1;
+  m6502_aop_pass[0]->aopu.aop_reg[0] = m6502_reg_a;
+  m6502_aop_pass[1] = newAsmop (AOP_REG);
+  m6502_aop_pass[1]->size = 1;
+  m6502_aop_pass[1]->aopu.aop_reg[0] = m6502_reg_x;
+  m6502_aop_pass[2] = newAsmop (AOP_DIR);
+  m6502_aop_pass[2]->size = 1;
+  m6502_aop_pass[2]->aopu.aop_dir = "___SDCC_m6502_ret2";
+  m6502_aop_pass[3] = newAsmop (AOP_DIR);
+  m6502_aop_pass[3]->size = 1;
+  m6502_aop_pass[3]->aopu.aop_dir = "___SDCC_m6502_ret3";
+  m6502_aop_pass[4] = newAsmop (AOP_DIR);
+  m6502_aop_pass[4]->size = 1;
+  m6502_aop_pass[4]->aopu.aop_dir = "___SDCC_m6502_ret4";
+  m6502_aop_pass[5] = newAsmop (AOP_DIR);
+  m6502_aop_pass[5]->size = 1;
+  m6502_aop_pass[5]->aopu.aop_dir = "___SDCC_m6502_ret5";
+  m6502_aop_pass[6] = newAsmop (AOP_DIR);
+  m6502_aop_pass[6]->size = 1;
+  m6502_aop_pass[6]->aopu.aop_dir = "___SDCC_m6502_ret6";
+  m6502_aop_pass[7] = newAsmop (AOP_DIR);
+  m6502_aop_pass[7]->size = 1;
+  m6502_aop_pass[7]->aopu.aop_dir = "___SDCC_m6502_ret7";
+}
+
+float
+drym6502iCode (iCode *ic)
+{
+  regalloc_dry_run = true;
+  regalloc_dry_run_cost_bytes = 0;
+  regalloc_dry_run_cost_cycles = 0;
+
+  init_aop_pass();
+  
+  genm6502iCode (ic);
+
+  destroy_line_list ();
+  /*freeTrace (&_G.trace.aops);*/
+
+  wassert (regalloc_dry_run);
+
+  int byte_cost_weight = 1;
+  if(optimize.codeSize) byte_cost_weight*=2;
+  if(!optimize.codeSpeed) byte_cost_weight*=4;
+
+//   return (2* (float)regalloc_dry_run_cost_bytes + (float)regalloc_dry_run_cost_cycles* ic->count);
+
+  return ((float)regalloc_dry_run_cost_bytes * byte_cost_weight + regalloc_dry_run_cost_cycles * ic->count);
+}
+
+/*---------------------------------------------------------------------*/
+/* genm6502Code - generate code for M6502 based controllers            */
+/*---------------------------------------------------------------------*/
+void
+genm6502Code (iCode *lic)
+{
+  iCode *ic;
+  int clevel = 0;
+  int cblock = 0;
+  int cln = 0;
+  regalloc_dry_run = false;
+
+  m6502_dirtyReg (m6502_reg_a);
+  m6502_dirtyReg (m6502_reg_y);
+  m6502_dirtyReg (m6502_reg_x);
+  _G.tempOfs = 0;
+
+  /* print the allocation information */
+  if (allocInfo && currFunc)
+    printAllocInfo (currFunc, codeOutBuf);
+  /* if debug information required */
+  if (options.debug && currFunc && !regalloc_dry_run)
+      debugFile->writeFunction (currFunc, lic);
+
+  if (options.debug && !regalloc_dry_run)
+    debugFile->writeFrameAddress (NULL, NULL, 0); /* have no idea where frame is now */
+
+  init_aop_pass();
+
+  for (ic = lic; ic; ic = ic->next)
+    ic->generated = false;
+
+  for (ic = lic; ic; ic = ic->next)
+    {
+      initGenLineElement ();
+
+      genLine.lineElement.ic = ic;
+
+      if (ic->level != clevel || ic->block != cblock)
+        {
+          if (options.debug)
+              debugFile->writeScope (ic);
+          clevel = ic->level;
+          cblock = ic->block;
+        }
+
+      if (ic->lineno && cln != ic->lineno)
+        {
+          if (options.debug)
+              debugFile->writeCLine (ic);
+
+          if (!options.noCcodeInAsm)
+            emitComment (ALWAYS, "%s: %d: %s", ic->filename, ic->lineno, printCLine (ic->filename, ic->lineno));
+          cln = ic->lineno;
+        }
+
+      regalloc_dry_run_cost_bytes = 0;
+      regalloc_dry_run_cost_cycles = 0;
+
+      if (options.iCodeInAsm)
+        {
+          char regsSurv[4];
+          const char *iLine;
+
+          regsSurv[0] = (bitVectBitValue (ic->rSurv, A_IDX)) ? 'a' : '-';
+          regsSurv[1] = (bitVectBitValue (ic->rSurv, Y_IDX)) ? 'y' : '-';
+          regsSurv[2] = (bitVectBitValue (ic->rSurv, X_IDX)) ? 'x' : '-';
+          regsSurv[3] = 0;
+          iLine = printILine (ic);
+          emitComment (ALWAYS, " [%s] ic:%d: %s", regsSurv, ic->key, iLine);
+          dbuf_free (iLine);
+        }
+
+      genm6502iCode(ic);
+      emitComment (TRACEGEN, "Raw cost for generated ic %d : (%d, %f) count=%f", ic->key, regalloc_dry_run_cost_bytes, regalloc_dry_run_cost_cycles, ic->count);
+
+      // TODO: should be asserts?
+/*
+      if (!m6502_reg_a->isFree)
+        emitComment (REGOPS|VVDBG, "  forgot to free a");
+      if (!m6502_reg_x->isFree)
+        emitComment (REGOPS|VVDBG, "  forgot to free x");
+      if (!m6502_reg_y->isFree)
+        emitComment (REGOPS|VVDBG, "  forgot to free y");
+      if (!m6502_reg_yx->isFree)
+        emitComment (REGOPS|VVDBG, "  forgot to free yx");
+      if (!m6502_reg_xa->isFree)
+        emitComment (REGOPS|VVDBG, "  forgot to free xa");
+*/
+
+      if (_G.tempOfs != 0)
+        emitcode("ERROR", "; forgot to free temp stack (%d)", _G.tempOfs);
+    }
+
+  if (options.debug)
+    debugFile->writeFrameAddress (NULL, NULL, 0); /* have no idea where frame is now */
+
+  /* now we are ready to call the
+     peep hole optimizer */
+  if (!options.nopeep)
+    peepHole (&genLine.lineHead);
+
+  /* now do the actual printing */
+  printLine (genLine.lineHead, codeOutBuf);
+
+  /* destroy the line list */
+  destroy_line_list ();
+}
+
diff -Nru sdcc-4.0.0+dfsg/src/mos6502/gen.h sdcc-4.2.0+dfsg/src/mos6502/gen.h
--- sdcc-4.0.0+dfsg/src/mos6502/gen.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/mos6502/gen.h	2022-02-03 07:49:29.000000000 +0000
@@ -0,0 +1,96 @@
+/*-------------------------------------------------------------------------
+  gen.h - header file for code generation for mos6502
+
+             Written By -  Sandeep Dutta . sandeep.dutta@usa.net (1998)
+
+   This program is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published by the
+   Free Software Foundation; either version 2, or (at your option) any
+   later version.
+   
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+   
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+   
+   In other words, you are welcome to use, share and improve this program.
+   You are forbidden to forbid anyone else to use, share and improve
+   what you give them.   Help stamp out software-hoarding!  
+-------------------------------------------------------------------------*/
+
+#ifndef SDCCGENM6502_H
+#define SDCCGENM6502_H
+
+enum
+  {
+    AOP_LIT = 1,
+    AOP_REG, AOP_DIR,
+    AOP_STK, AOP_IMMD, AOP_STR,
+    AOP_CRY, 
+    AOP_EXT, AOP_SOF, AOP_DUMMY, AOP_IDX
+  };
+
+enum
+  {
+    ACCUSE_XA = 1,
+    ACCUSE_YX
+  };
+
+/* type asmop : a homogenised type for 
+   all the different spaces an operand can be
+   in */
+typedef struct asmop
+  {
+
+    short type;			
+    /* can have values
+       AOP_LIT    -  operand is a literal value
+       AOP_REG    -  is in registers
+       AOP_DIR    -  operand using direct addressing mode
+       AOP_STK    -  should be pushed on stack this
+       can happen only for the result
+       AOP_IMMD   -  immediate value for eg. remateriazable 
+       AOP_CRY    -  carry contains the value of this
+       AOP_STR    -  array of strings
+       AOP_SOF    -  operand at an offset on the stack
+       AOP_EXT    -  operand using extended addressing mode
+       AOP_IDX    -  operand using indexed addressing mode
+    */
+    short regmask;              /* register mask if AOP_REG */
+    short coff;			/* current offset */
+    short size;			/* total size */
+    operand *op;		/* originating operand */
+    unsigned code:1;		/* is in Code space */
+    unsigned freed:1;		/* already freed    */
+    unsigned stacked:1;		/* partial results stored on stack */
+    struct asmop *stk_aop[4];	/* asmops for the results on the stack */
+    union
+      {
+	value *aop_lit;		/* if literal */
+	reg_info *aop_reg[4];	/* array of registers */
+	char *aop_dir;		/* if direct  */
+	struct {
+		char *aop_immd1;	/* if immediate others are implied */
+		char *aop_immd2;	/* cast remat will generate this   */
+	} aop_immd;
+	int aop_stk;		/* stack offset when AOP_STK */
+      }
+    aopu;
+  }
+asmop;
+
+void genm6502Code (iCode *);
+void m6502_emitDebuggerSymbol (const char *);
+
+extern unsigned fReturnSizeM6502;
+
+extern bool m6502_assignment_optimal;
+
+#define NUM_TEMP_REGS 8
+
+#endif
+
diff -Nru sdcc-4.0.0+dfsg/src/mos6502/m6502.h sdcc-4.2.0+dfsg/src/mos6502/m6502.h
--- sdcc-4.0.0+dfsg/src/mos6502/m6502.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/mos6502/m6502.h	2022-01-08 21:48:36.000000000 +0000
@@ -0,0 +1,18 @@
+typedef enum
+  {
+    SUB_MOS6502,
+    SUB_MOS65C02
+  }
+MOS6502_SUB_PORT;
+
+typedef struct
+  {
+    MOS6502_SUB_PORT sub;
+  }
+MOS6502_OPTS;
+
+extern MOS6502_OPTS mos6502_opts;
+
+#define IS_MOS6502 (mos6502_opts.sub == SUB_MOS6502)
+#define IS_MOS65C02 (mos6502_opts.sub == SUB_MOS65C02)
+
diff -Nru sdcc-4.0.0+dfsg/src/mos6502/main.c sdcc-4.2.0+dfsg/src/mos6502/main.c
--- sdcc-4.0.0+dfsg/src/mos6502/main.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/mos6502/main.c	2022-02-24 20:52:17.000000000 +0000
@@ -0,0 +1,915 @@
+/*-------------------------------------------------------------------------
+  main.c - m6502 specific general function
+
+  Copyright (C) 2003, Erik Petrich
+
+  Hacked for the MOS6502:
+  Copyright (C) 2020, Steven Hugg  hugg@fasterlight.com
+  Copyright (C) 2021, Gabriele Gorla
+
+
+  This program is free software; you can redistribute it and/or modify it
+  under the terms of the GNU General Public License as published by the
+  Free Software Foundation; either version 2, or (at your option) any
+  later version.
+
+  This program is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+  GNU General Public License for more details.
+
+  You should have received a copy of the GNU General Public License
+  along with this program; if not, write to the Free Software
+  Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+-------------------------------------------------------------------------*/
+/*
+    Note that mlh prepended _m6502_ on the static functions.  Makes
+    it easier to set a breakpoint using the debugger.
+*/
+#include "common.h"
+#include "m6502.h"
+#include "main.h"
+#include "ralloc.h"
+#include "gen.h"
+#include "dbuf_string.h"
+
+#define OPTION_SMALL_MODEL          "--model-small"
+#define OPTION_LARGE_MODEL          "--model-large"
+//#define OPTION_CODE_SEG        "--codeseg"
+//#define OPTION_CONST_SEG       "--constseg"
+//#define OPTION_DATA_SEG        "--dataseg"
+#define OPTION_NO_STD_CRT0     "--no-std-crt0"
+
+extern char * iComments2;
+extern DEBUGFILE dwarf2DebugFile;
+extern int dwarf2FinalizeFile(FILE *);
+
+static OPTION _mos6502_options[] =
+  {
+    {0, OPTION_SMALL_MODEL, NULL, "8-bit address space for data"},
+    {0, OPTION_LARGE_MODEL, NULL, "16-bit address space for data (default)"},
+    //    {0, OPTION_CODE_SEG,        &options.code_seg, " use this name for the code segment", CLAT_STRING},
+    //    {0, OPTION_CONST_SEG,       &options.const_seg, " use this name for the const segment", CLAT_STRING},
+    //    {0, OPTION_DATA_SEG,        &options.data_seg, " use this name for the data segment", CLAT_STRING},
+    {0, OPTION_NO_STD_CRT0,     &options.no_std_crt0, "Do not link default crt0.rel"},
+    {0, NULL }
+  };
+
+static char _m6502_defaultRules[] =
+{
+#include "peeph.rul"
+};
+
+static char _m65c02_defaultRules[] =
+{
+#include "peeph.rul"
+};
+
+MOS6502_OPTS mos6502_opts;
+
+/* list of key words used by m6502 */
+static char *_keywords[] = {
+  "at",
+  "code",
+  "critical",
+  "data",
+  "far",
+  //"idata",
+  "interrupt",
+  "near",
+  //"pdata",
+  "reentrant",
+  //"using",
+  "xdata",
+  "_data",
+  "_code",
+  "_generic",
+  "_near",
+  "_xdata",
+  //"_pdata",
+  //"_idata",
+  "_naked",
+  "_overlay",
+  NULL
+};
+
+
+void m6502_assignRegisters (ebbIndex *);
+
+static int regParmFlg;      /* determine if we can register a parameter */
+static struct sym_link *regParmFuncType;
+
+static void
+_m6502_init (void)
+{
+  mos6502_opts.sub = SUB_MOS6502;
+  asm_addTree (&asm_asxxxx_mapping);
+}
+
+static void
+_m65c02_init (void)
+{
+  mos6502_opts.sub = SUB_MOS65C02;
+  asm_addTree (&asm_asxxxx_mapping);
+}
+
+static void
+_m6502_reset_regparm (struct sym_link *funcType)
+{
+  regParmFlg = 0;
+  regParmFuncType = funcType;
+}
+
+static int
+_m6502_regparm (sym_link * l, bool reentrant)
+{
+  if (IFFUNC_HASVARARGS (regParmFuncType))
+    return 0;
+
+  int size = getSize(l);
+
+  /* If they fit completely, the first two bytes of parameters can go */
+  /* into A and X, otherwise, they go on the stack. Examples:         */
+  /*   foo(char p1)                    A <- p1                        */
+  /*   foo(char p1, char p2)           A <- p1, X <- p2               */
+  /*   foo(char p1, char p2, char p3)  A <- p1, X <- p2, stack <- p3  */
+  /*   foo(int p1)                     XA <- p1                       */
+  /*   foo(long p1)                    stack <- p1                    */
+  /*   foo(char p1, int p2)            A <- p1, stack <- p2           */
+  /*   foo(int p1, char p2)            XA <- p1, stack <- p2          */
+
+  if (regParmFlg>=2)
+    return 0;
+
+  if ((regParmFlg+size)>2)
+    {
+      regParmFlg = 2;
+      return 0;
+    }
+
+  regParmFlg += size;
+  return 1+regParmFlg-size;
+}
+
+static bool
+_m6502_parseOptions (int *pargc, char **argv, int *i)
+{
+  return false;
+}
+
+static void
+_m6502_finaliseOptions (void)
+{
+  if (options.noXinitOpt)
+    port->genXINIT = 0;
+
+  if (options.model == MODEL_LARGE) {
+      port->mem.default_local_map = xdata;
+      port->mem.default_globl_map = xdata;
+    }
+  else
+    {
+      port->mem.default_local_map = data;
+      port->mem.default_globl_map = data;
+    }
+
+  istack->ptrType = FPOINTER;
+}
+
+static void
+_m6502_setDefaultOptions (void)
+{
+  options.code_loc = 0x200;
+  options.data_loc = 0x20;	/* zero page */
+  options.xdata_loc = 0x8000;   /* 0 means immediately following data */
+  options.stack_loc = 0x1ff;
+
+  options.omitFramePtr = 1;     /* no frame pointer (we use SP */
+                                /* offsets instead)            */
+
+  options.out_fmt = 'i';        /* Default output format is ihx */
+}
+
+static const char *
+_m6502_getRegName (const struct reg_info *reg)
+{
+  if (reg)
+    return reg->name;
+  return "err";
+}
+
+static void
+_m6502_genAssemblerPreamble (FILE * of)
+{
+  symbol *mainExists=newSymbol("main", 0);
+  mainExists->block=0;
+
+  if ((mainExists=findSymWithLevel(SymbolTab, mainExists)))
+    {
+      // global variables in zero page
+      fprintf (of, "\t.globl __TEMP\n");
+      fprintf (of, "\t.globl __BASEPTR\n");
+      
+      fprintf (of, "\t.area %s\n",port->mem.data_name);
+      fprintf (of, "__TEMP:\t.ds %d\n", NUM_TEMP_REGS);
+      fprintf (of, "__BASEPTR:\t.ds 2\n");
+    }
+}
+
+static void
+_m6502_genAssemblerEnd (FILE * of)
+{
+  if (options.out_fmt == 'E' && options.debug)
+    {
+      dwarf2FinalizeFile (of);
+    }
+}
+
+static void
+_m6502_genExtraAreas (FILE * asmFile, bool mainExists)
+{
+    fprintf (asmFile, "%s", iComments2);
+    fprintf (asmFile, "; extended address mode data\n");
+    fprintf (asmFile, "%s", iComments2);
+    dbuf_write_and_destroy (&xdata->oBuf, asmFile);
+}
+
+
+//#if 0
+/* Generate interrupt vector table. */
+static int
+_m6502_genIVT (struct dbuf_s * oBuf, symbol ** interrupts, int maxInterrupts)
+{
+  int i;
+
+  dbuf_printf (oBuf, "\t.area\tCODEIVT (ABS)\n");
+  dbuf_printf (oBuf, "\t.org\t0x%04x\n",
+    (0xfffe - 2 - (maxInterrupts * 2)));
+
+  for (i=maxInterrupts;i>1;i--)
+    {
+      if (interrupts[i])
+        dbuf_printf (oBuf, "\t.dw\t%s\n", interrupts[i]->rname);
+      else
+        dbuf_printf (oBuf, "\t.dw\t0xffff\n");
+    }
+  dbuf_printf (oBuf, "\t.dw\t%s", "__sdcc_gs_init_startup\n");
+  if (maxInterrupts > 0)
+    {
+      if (interrupts[0])
+        dbuf_printf (oBuf, "\t.dw\t%s\n", interrupts[0]->rname);
+      else
+        dbuf_printf (oBuf, "\t.dw\t0xffff\n");
+    }
+
+  return true;
+}
+
+/* Generate code to copy XINIT to XISEG */
+static void _m6502_genXINIT (FILE * of) {
+  fprintf (of, ";       _m6502_genXINIT() start\n");
+  fprintf (of, ";       _m6502_genXINIT() end\n");
+}
+
+//#endif
+
+/* Do CSE estimation */
+static bool cseCostEstimation (iCode *ic, iCode *pdic)
+{
+    operand *result = IC_RESULT(ic);
+    sym_link *result_type = operandType(result);
+
+    /* if it is a pointer then return ok for now */
+    if (IC_RESULT(ic) && IS_PTR(result_type)) return 1;
+
+    if (ic->op == ADDRESS_OF)
+      return 0;
+
+    /* if bitwise | add & subtract then no since m6502 is pretty good at it
+       so we will cse only if they are local (i.e. both ic & pdic belong to
+       the same basic block */
+    if (IS_BITWISE_OP(ic) || ic->op == '+' || ic->op == '-') {
+        /* then if they are the same Basic block then ok */
+        if (ic->eBBlockNum == pdic->eBBlockNum) return 1;
+        else return 0;
+    }
+
+    /* for others it is cheaper to do the cse */
+    return 1;
+}
+
+/* Indicate which extended bit operations this port supports */
+static bool
+hasExtBitOp (int op, int size)
+{
+  // TODO: doesn't seem to use RLC/RRC
+  if (op == RRC
+      || op == RLC
+      //|| (op == SWAP && size <= 2)
+      // TODO?
+      //|| op == GETABIT
+      //|| op == GETBYTE
+      //|| op == GETWORD
+     )
+    return true;
+  else
+    return false;
+}
+
+/* Indicate the expense of an access to an output storage class */
+static int
+oclsExpense (struct memmap *oclass)
+{
+  if (IN_DIRSPACE (oclass))     /* direct addressing mode is fastest */
+    return -2;
+  if (IN_FARSPACE (oclass))     /* extended addressing mode is almost at fast */
+    return -1;
+  if (oclass == istack)         /* stack is the slowest */
+    return 2;
+
+  return 0; /* anything we missed */
+}
+
+/*----------------------------------------------------------------------*/
+/* m6502_dwarfRegNum - return the DWARF register number for a register.  */
+/*   These are defined for the M6502 in "Motorola 8- and 16-bit Embedded */
+/*   Application Binary Interface (M8/16EABI)"                          */
+/*----------------------------------------------------------------------*/
+static int
+m6502_dwarfRegNum (const struct reg_info *reg)
+{
+  switch (reg->rIdx)
+    {
+    case A_IDX: return 0;
+    case Y_IDX: return 1;
+    case X_IDX: return 2;
+    case CND_IDX: return 17;
+    case SP_IDX: return 15;
+    }
+  return -1;
+}
+
+static bool
+_hasNativeMulFor (iCode *ic, sym_link *left, sym_link *right)
+{
+  return false;
+}
+
+typedef struct asmLineNode
+  {
+    int size;
+  }
+asmLineNode;
+
+static asmLineNode *
+newAsmLineNode (void)
+{
+  asmLineNode *aln;
+
+  aln = Safe_alloc ( sizeof (asmLineNode));
+  aln->size = 0;
+
+  return aln;
+}
+
+/* These must be kept sorted by opcode name */
+static m6502opcodedata m6502opcodeDataTable[] =
+  {
+    {".db",   M6502OP_INH, 0,     0 }, /* used by the code generator only in the jump table */
+    {"adc",   M6502OP_REG, A_IDX, 0xc3 },
+    {"and",   M6502OP_REG, A_IDX, 0x82 },
+    {"asl",   M6502OP_RMW, 0,     0x83 },
+    {"bbr",   M6502OP_BBR, 0,     0 }, // Rockwell and WDC only
+    {"bbs",   M6502OP_BBR, 0,     0 }, // Rockwell and WDC only
+    {"bcc",   M6502OP_BR,  0,     0 },
+    {"bcs",   M6502OP_BR,  0,     0 },
+    {"beq",   M6502OP_BR,  0,     0 },
+    {"bit",   M6502OP_REG, 0,     0xc2 },
+    {"bmi",   M6502OP_BR,  0,     0 },
+    {"bne",   M6502OP_BR,  0,     0 },
+    {"bpl",   M6502OP_BR,  0,     0 },
+    {"brk",   M6502OP_INH, 0,     0 },
+    {"bvc",   M6502OP_BR,  0,     0 },
+    {"bvs",   M6502OP_BR,  0,     0 },
+    {"bra",   M6502OP_BR,  0,     0 }, // 65C02 only
+    {"clc",   M6502OP_INH, 0,     0x01 },
+    {"cld",   M6502OP_INH, 0,     0x80 },
+    {"cli",   M6502OP_INH, 0,     0x04 },
+    {"clv",   M6502OP_INH, 0,     0x40 },
+    {"cmp",   M6502OP_REG, 0,     0xc3 },
+    {"cpx",   M6502OP_REG, 0,     0xc3 },
+    {"cpy",   M6502OP_REG, 0,     0xc3 },
+    {"dec",   M6502OP_RMW, 0,     0x82 },
+    {"dex",   M6502OP_IDD, X_IDX, 0x82 },
+    {"dey",   M6502OP_IDD, Y_IDX, 0x82 },
+    {"eor",   M6502OP_REG, A_IDX, 0x82 },
+    {"inc",   M6502OP_RMW, 0,     0x82 },
+    {"inx",   M6502OP_IDI, X_IDX, 0x82 },
+    {"iny",   M6502OP_IDI, Y_IDX, 0x82 },
+    {"jmp",   M6502OP_JMP, 0,     0 },
+    {"jsr",   M6502OP_JMP, 0,     0 },
+    {"lda",   M6502OP_LD , A_IDX, 0x82 },
+    {"ldx",   M6502OP_LD , X_IDX, 0x82 },
+    {"ldy",   M6502OP_LD , Y_IDX, 0x82 },
+    {"lsr",   M6502OP_RMW, 0,     0x83 },
+    {"nop",   M6502OP_INH, 0,     0 },
+    {"ora",   M6502OP_REG, A_IDX, 0x82 },
+    {"pha",   M6502OP_SPH, 0,     0 },
+    {"php",   M6502OP_SPH, 0,     0 },
+    {"phy",   M6502OP_SPH, 0,     0 }, // 65C02 only
+    {"phx",   M6502OP_SPH, 0,     0 }, // 65C02 only
+    {"pla",   M6502OP_SPL, A_IDX, 0x82 },
+    {"plp",   M6502OP_SPL, 0,     0xdf },
+    {"ply",   M6502OP_SPL, Y_IDX, 0x82 }, // 65C02 only
+    {"plx",   M6502OP_SPL, X_IDX, 0x82 }, // 65C02 only
+    {"rmb",   M6502OP_REG, 0,     0 }, // Rockwell and WDC only
+    {"rol",   M6502OP_RMW, 0,     0x83 },
+    {"ror",   M6502OP_RMW, 0,     0x83 },
+    {"rti",   M6502OP_INH, 0,     0xdf },
+    {"rts",   M6502OP_INH, 0,     0 },
+    {"sbc",   M6502OP_REG, A_IDX, 0xc3 },
+    {"sec",   M6502OP_INH, 0,     0x01 },
+    {"sed",   M6502OP_INH, 0,     0x08 },
+    {"sei",   M6502OP_INH, 0,     0x04 },
+    {"smb",   M6502OP_REG, 0,     0 }, // Rockwell and WDC only
+    {"sta",   M6502OP_ST , 0,     0 },
+    {"stp",   M6502OP_INH, 0,     0 }, // WDC only
+    {"stx",   M6502OP_ST , 0,     0 },
+    {"sty",   M6502OP_ST , 0,     0 },
+    {"stz",   M6502OP_ST , 0,     0 }, // 65C02 only
+    {"tax",   M6502OP_INH, X_IDX, 0x82 },
+    {"tay",   M6502OP_INH, Y_IDX, 0x82 },
+    {"trb",   M6502OP_REG, 0,     0 }, // 65C02 only
+    {"tsb",   M6502OP_REG, 0,     0 }, // 65C02 only
+    {"tsx",   M6502OP_INH, X_IDX, 0x82 },
+    {"txa",   M6502OP_INH, A_IDX, 0x82 },
+    {"txs",   M6502OP_INH, 0,     0 },
+    {"tya",   M6502OP_INH, A_IDX, 0x82 },
+    {"wai",   M6502OP_INH, 0,     0 }  // WDC only
+  };
+
+static int
+m6502_opcodeCompare (const void *key, const void *member)
+{
+  return strcmp((const char *)key, ((m6502opcodedata *)member)->name);
+}
+
+
+const m6502opcodedata *m6502_getOpcodeData(const char *inst)
+{
+  
+  return   bsearch (inst, m6502opcodeDataTable,
+                    sizeof(m6502opcodeDataTable)/sizeof(m6502opcodedata),
+                    sizeof(m6502opcodedata), m6502_opcodeCompare);
+}
+
+int
+m6502_opcodeSize(const m6502opcodedata *opcode, const char *arg)
+{
+  switch (opcode->type)
+    {
+      case M6502OP_INH: /* Inherent addressing mode */
+      case M6502OP_SPH:
+      case M6502OP_SPL:
+      case M6502OP_IDD:
+      case M6502OP_IDI:
+        return 1;
+        
+      case M6502OP_BR:  /* Branch (1 byte signed offset) */
+        return 2;
+        
+      case M6502OP_BBR:  /* Branch on bit (1 byte signed offset) */
+        return 3;
+
+      case M6502OP_RMW: /* read/modify/write instructions */
+        if (!strcmp(arg, "a"))  /* accumulator */
+          return 1;
+     	if (arg[0] == '*') /* Zero page */
+    	  return 2;
+        return 3;  /* absolute */
+        
+      case M6502OP_REG: /* standard instruction */
+      case M6502OP_LD:
+      case M6502OP_ST:
+        if (arg[0] == '#') /* Immediate addressing mode */
+	      return 2;
+        if (arg[0] == '*') /* Zero page */
+	      return 2;
+        if (arg[0] == '[') /* indirect */
+          return 2;
+	return 3; /* Otherwise, must be extended addressing mode */
+	    
+      case M6502OP_JMP:
+        return 3;
+
+      default:
+         werror (E_INTERNAL_ERROR, __FILE__, __LINE__, "unknown instruction type in m6502_opcodeSize");
+         return 3;
+    }
+}
+
+/*--------------------------------------------------------------------*/
+/* Given an instruction and its first two operands, compute the       */
+/* instruction size. There are a few cases where it's too complicated */
+/* to distinguish between an 8-bit offset and 16-bit offset; in these */
+/* cases we conservatively assume the 16-bit offset size.             */
+/*--------------------------------------------------------------------*/
+static int
+m6502_instructionSize(const char *inst, const char *op1, const char *op2)
+{
+  const m6502opcodedata *opcode = m6502_getOpcodeData(inst);
+
+  if (!opcode)
+    return 999;
+
+  //  printf("op: %s - %s - %s\n",inst,op1, op2);
+
+  return m6502_opcodeSize(opcode, op1);
+}
+
+
+static asmLineNode *
+m6502_asmLineNodeFromLineNode (lineNode *ln)
+{
+  asmLineNode *aln = newAsmLineNode();
+  char *op, op1[256], op2[256];
+  int opsize;
+  const char *p;
+  char inst[8];
+
+  p = ln->line;
+
+  while (*p && isspace(*p)) p++;
+  for (op = inst, opsize=1; *p; p++)
+    {
+      if (isspace(*p) || *p == ';' || *p == ':' || *p == '=')
+        break;
+      else
+        if (opsize < sizeof(inst))
+          *op++ = tolower(*p), opsize++;
+    }
+  *op = '\0';
+
+  if (*p == ':' || *p == '=')
+    return aln;
+
+  while (*p && isspace(*p)) p++;
+  if (*p == '=')
+    return aln;
+
+  if(*p==';') {
+    op1[0]=0;
+    op2[0]=0;
+    aln->size = m6502_instructionSize(inst, op1, op2);
+    return aln;
+  }
+
+  for (op = op1, opsize=1; *p && *p != ',' && *p != ';'; p++)
+    {
+      if (!isspace(*p) && opsize < sizeof(op1))
+        *op++ = tolower(*p), opsize++;
+    }
+  *op = '\0';
+
+  if (*p == ',') p++;
+  if (*p == ';') {
+    op2[0]=0;
+    aln->size = m6502_instructionSize(inst, op1, op2);
+    return aln;
+  }
+
+  
+  for (op = op2, opsize=1; *p && *p != ',' && *p != ';' ; p++)
+    {
+      if (!isspace(*p) && opsize < sizeof(op2))
+        *op++ = tolower(*p), opsize++;
+    }
+  *op = '\0';
+
+  aln->size = m6502_instructionSize(inst, op1, op2);
+
+  return aln;
+}
+
+static int
+m6502_getInstructionSize (lineNode *line)
+{
+  if (!line->aln)
+    line->aln = (asmLineNodeBase *) m6502_asmLineNodeFromLineNode (line);
+
+  return line->aln->size;
+}
+
+/** $1 is always the basename.
+    $2 is always the output file.
+    $3 varies
+    $l is the list of extra options that should be there somewhere...
+    MUST be terminated with a NULL.
+*/
+static const char *_linkCmd[] =
+{
+  "sdld6808", "-nf", "$1", NULL
+};
+
+/* $3 is replaced by assembler.debug_opts resp. port->assembler.plain_opts */
+static const char *_asmCmd[] =
+{
+  "sdas6500", "$l", "$3", "$2", "$1.asm", NULL
+};
+
+static const char *const _crt[] = { "crt0.rel", NULL, };
+static const char * const _libs_m6502[] = { "mos6502", NULL, };
+static const char * const _libs_m65c02[] = { "mos65c02", NULL, };
+
+/* Globals */
+PORT mos6502_port =
+{
+  TARGET_ID_MOS6502,
+  "mos6502",
+  "MOS 6502",                       /* Target name */
+  NULL,                         /* Processor name */
+  {
+    glue,
+    false,                      /* Emit glue around main */
+    MODEL_SMALL | MODEL_LARGE,
+    MODEL_LARGE,
+    NULL,                       /* model == target */
+  },
+  {
+    _asmCmd,
+    NULL,
+    "-plosgffwy",               /* Options with debug */
+    "-plosgffw",                /* Options without debug */
+    0,
+    ".asm",
+    NULL                        /* no do_assemble function */
+  },
+  {                             /* Linker */
+    _linkCmd,
+    NULL,
+    NULL,
+    ".rel",                     /* object file extension */
+    1,                          /* need linker script */
+    _crt,                       /* crt */
+    _libs_m6502,                 /* libs */
+  },
+  {                             /* Peephole optimizer */
+    _m6502_defaultRules,
+    m6502_getInstructionSize,
+  },
+  // TODO: banked func ptr?
+  {
+    /* Sizes: char, short, int, long, long long, near ptr, far ptr, gptr, func ptr, banked func ptr, bit, float */
+    1, 2, 2, 4, 8, 2, 2, 2, 2, 0, 1, 4
+  },
+  /* tags for generic pointers */
+  { 0x00, 0x00, 0x00, 0x00 },           /* far, near, xstack, code */
+  {
+    "XSEG",               // xstack_name
+    "STACK",              // istack_name
+    "CODE",               // code
+    "ZP      (PAG)",      // data
+    NULL,                 // idata
+    NULL,                 // pdata
+    "BSS",                // xdata
+    NULL,                 // bit
+    "RSEG    (ABS)",      // reg
+    "GSINIT",             // static initialization
+    "OSEG    (PAG, OVR)", // overlay
+    "GSFINAL",            // gsfinal
+    "_CODE",              // home
+    "DATA",               // initialized xdata
+    "XINIT",              // a code copy of xiseg
+    "RODATA",             // const_name - const data (code or not)
+    "CABS    (ABS)",      // cabs_name - const absolute data (code or not)
+    "DABS    (ABS)",      // xabs_name - absolute xdata
+    NULL,                 // iabs_name - absolute data
+    NULL,                 // name of segment for initialized variables
+    NULL,                 // name of segment for copies of initialized variables in code space
+    NULL,
+    NULL,
+    1,
+    1                     // No fancy alignments supported.
+  },
+  { _m6502_genExtraAreas,
+    NULL },
+  0,                      // ABI revision
+  {
+    -1,         /* direction (-1 = stack grows down) */
+    0,          /* bank_overhead (switch between register banks) */
+    4,          /* isr_overhead */
+    2,          /* call_overhead */
+    0,          /* reent_overhead */
+    0,          /* banked_overhead (switch between code banks) */
+    1           /* sp is offset by 1 from last item pushed */
+  },
+  {
+    5, false // TODO: 5 max shift?
+  },
+  {
+    m6502_emitDebuggerSymbol,
+    {
+      m6502_dwarfRegNum,
+      NULL,
+      NULL,
+      4,                        /* addressSize */
+      14,                       /* regNumRet */
+      15,                       /* regNumSP */
+      -1,                       /* regNumBP */
+      1,                        /* offsetSP */
+    },
+  },
+  {
+    256,        /* maxCount */
+    2,          /* sizeofElement */
+    {8,16,32},  /* sizeofMatchJump[] */
+    {8,16,32},  /* sizeofRangeCompare[] */
+    5,          /* sizeofSubtract */
+    10,         /* sizeofDispatch */
+  },
+  "_",
+  _m6502_init,
+  _m6502_parseOptions,
+  _mos6502_options,
+  NULL,
+  _m6502_finaliseOptions,
+  _m6502_setDefaultOptions,
+  m6502_assignRegisters,
+  _m6502_getRegName,
+  0,
+  NULL,
+  _keywords,
+  _m6502_genAssemblerPreamble,
+  _m6502_genAssemblerEnd,        /* no genAssemblerEnd */
+  _m6502_genIVT,
+  _m6502_genXINIT,
+  NULL,                         /* genInitStartup */
+  _m6502_reset_regparm,
+  _m6502_regparm,
+  NULL,                         /* process_pragma */
+  NULL,                         /* getMangledFunctionName */
+  _hasNativeMulFor,             /* hasNativeMulFor */
+  hasExtBitOp,                  /* hasExtBitOp */
+  oclsExpense,                  /* oclsExpense */
+  true,                         /* use_dw_for_init */
+  true,                         /* little_endian */
+  0,                            /* leave lt */
+  0,                            /* leave gt */
+  1,                            /* transform <= to ! > */
+  1,                            /* transform >= to ! < */
+  1,                            /* transform != to !(a == b) */
+  0,                            /* leave == */
+  false,                        /* No array initializer support. */
+  cseCostEstimation,
+  NULL,                         /* no builtin functions */
+  GPOINTER,                     /* treat unqualified pointers as "generic" pointers */
+  1,                            /* reset labelKey to 1 */
+  1,                            /* globals & local statics allowed */
+  3,                            /* Number of registers handled in the tree-decomposition-based register allocator in SDCCralloc.hpp */
+  PORT_MAGIC
+};
+
+PORT mos65c02_port =
+{
+  TARGET_ID_MOS65C02,
+  "mos65c02",
+  "WDC 65C02",                        /* Target name */
+  NULL,                         /* Processor name */
+  {
+    glue,
+    false,                      /* Emit glue around main */
+    MODEL_SMALL | MODEL_LARGE,
+    MODEL_LARGE,
+    NULL,                       /* model == target */
+  },
+  {
+    _asmCmd,
+    NULL,
+    "-plosgffwy",               /* Options with debug */
+    "-plosgffw",                /* Options without debug */
+    0,
+    ".asm",
+    NULL                        /* no do_assemble function */
+  },
+  {                             /* Linker */
+    _linkCmd,
+    NULL,
+    NULL,
+    ".rel",
+    1,
+    NULL,                       /* crt */
+    _libs_m65c02,                  /* libs */
+  },
+  {                             /* Peephole optimizer */
+    _m65c02_defaultRules,
+    m6502_getInstructionSize,
+  },
+  {
+    /* Sizes: char, short, int, long, long long, near ptr, far ptr, gptr, func ptr, banked func ptr, bit, float */
+    1, 2, 2, 4, 8, 2, 2, 2, 2, 0, 1, 4
+  },
+  /* tags for generic pointers */
+  { 0x00, 0x00, 0x00, 0x00 },           /* far, near, xstack, code */
+  {
+    "XSEG",               // xstack_name
+    "STACK",              // istack_name
+    "CODE",               // code
+    "ZP      (PAG)",      // data
+    NULL,                 // idata
+    NULL,                 // pdata
+    "BSS",                // xdata
+    NULL,                 // bit
+    "RSEG    (ABS)",      // reg
+    "GSINIT",             // static initialization
+    "OSEG    (PAG, OVR)", // overlay
+    "GSFINAL",            // gsfinal
+    "_CODE",              // home
+    "DATA",               // initialized xdata
+    "XINIT",              // a code copy of xiseg
+    "RODATA",             // const_name - const data (code or not)
+    "CABS    (ABS)",      // cabs_name - const absolute data (code or not)
+    "DABS    (ABS)",      // xabs_name - absolute xdata
+    NULL,                 // iabs_name - absolute data
+    NULL,                 // name of segment for initialized variables
+    NULL,                 // name of segment for copies of initialized variables in code space
+    NULL,
+    NULL,
+    1,                    /* CODE  is read-only */
+    1                     // No fancy alignments supported.
+  },
+  { _m6502_genExtraAreas, NULL },
+  0,                      // ABI revision
+  {
+    -1,         /* direction (-1 = stack grows down) */
+    0,          /* bank_overhead (switch between register banks) */
+    4,          /* isr_overhead */
+    2,          /* call_overhead */
+    0,          /* reent_overhead */
+    0,          /* banked_overhead (switch between code banks) */
+    1           /* sp is offset by 1 from last item pushed */
+  },
+  {
+    5, false
+  },
+  {
+    m6502_emitDebuggerSymbol,
+    {
+      m6502_dwarfRegNum,
+      NULL,
+      NULL,
+      4,                        /* addressSize */
+      14,                       /* regNumRet */
+      15,                       /* regNumSP */
+      -1,                       /* regNumBP */
+      1,                        /* offsetSP */
+    },
+  },
+  {
+    256,        /* maxCount */
+    2,          /* sizeofElement */
+    {8,16,32},  /* sizeofMatchJump[] */
+    {8,16,32},  /* sizeofRangeCompare[] */
+    5,          /* sizeofSubtract */
+    10,         /* sizeofDispatch */
+  },
+  "_",
+  _m65c02_init,
+  _m6502_parseOptions,
+  _mos6502_options,
+  NULL,
+  _m6502_finaliseOptions,
+  _m6502_setDefaultOptions,
+  m6502_assignRegisters,
+  _m6502_getRegName,
+  0,
+  NULL,
+  _keywords,
+  _m6502_genAssemblerPreamble,
+  _m6502_genAssemblerEnd,        /* no genAssemblerEnd */
+  _m6502_genIVT,
+  _m6502_genXINIT,
+  NULL,                         /* genInitStartup */
+  _m6502_reset_regparm,
+  _m6502_regparm,
+  NULL,                         /* process_pragma */
+  NULL,                         /* getMangledFunctionName */
+  _hasNativeMulFor,             /* hasNativeMulFor */
+  hasExtBitOp,                  /* hasExtBitOp */
+  oclsExpense,                  /* oclsExpense */
+  true,                         /* use_dw_for_init */
+  true,                         /* little_endian */
+  0,                            /* leave lt */
+  0,                            /* leave gt */
+  1,                            /* transform <= to ! > */
+  1,                            /* transform >= to ! < */
+  1,                            /* transform != to !(a == b) */
+  0,                            /* leave == */
+  false,                        /* No array initializer support. */
+  cseCostEstimation,
+  NULL,                         /* no builtin functions */
+  GPOINTER,                     /* treat unqualified pointers as "generic" pointers */
+  1,                            /* reset labelKey to 1 */
+  1,                            /* globals & local statics allowed */
+  3,                            /* Number of registers handled in the tree-decomposition-based register allocator in SDCCralloc.hpp */
+  PORT_MAGIC
+};
diff -Nru sdcc-4.0.0+dfsg/src/mos6502/main.h sdcc-4.2.0+dfsg/src/mos6502/main.h
--- sdcc-4.0.0+dfsg/src/mos6502/main.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/mos6502/main.h	2022-01-08 21:48:36.000000000 +0000
@@ -0,0 +1,8 @@
+#ifndef MAIN_INCLUDE
+#define MAIN_INCLUDE
+
+bool x_parseOptions (char **argv, int *pargc);
+void x_setDefaultOptions (void);
+void x_finaliseOptions (void);
+
+#endif
diff -Nru sdcc-4.0.0+dfsg/src/mos6502/Makefile.in sdcc-4.2.0+dfsg/src/mos6502/Makefile.in
--- sdcc-4.0.0+dfsg/src/mos6502/Makefile.in	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/mos6502/Makefile.in	2022-01-08 21:48:36.000000000 +0000
@@ -0,0 +1,7 @@
+VPATH        = @srcdir@
+srcdir       = @srcdir@
+top_builddir = @top_builddir@
+top_srcdir   = @top_srcdir@
+
+# Make all in this directory
+include $(srcdir)/../port.mk
diff -Nru sdcc-4.0.0+dfsg/src/mos6502/peeph.def sdcc-4.2.0+dfsg/src/mos6502/peeph.def
--- sdcc-4.0.0+dfsg/src/mos6502/peeph.def	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/mos6502/peeph.def	2022-02-09 00:14:17.000000000 +0000
@@ -0,0 +1,417 @@
+replace restart {
+        sta	%1
+        stx	%2
+	lda     %1
+	ldx     %2
+} by {
+    ; Peephole 1sta-lda   - eliminated redundant lda/ldx
+        sta	%1
+        stx	%2
+} if notVolatile(%1), notVolatile(%2)
+
+
+replace restart {
+        %1	%2
+        %1	%3
+} by {
+    ; Peephole 1ldld   - eliminated unused load
+	%1	%3
+} if same(%1 'lda' 'ldx' 'ldy'), notVolatile(%2)
+
+replace restart {
+	pla
+	pha
+	lda	%1
+} by {
+	; Peephole 1ldst - removed redundant pla/pha followed by lda
+	lda	%1
+}
+
+replace restart {
+	pla
+	pha
+	%1
+} by {
+	; Peephole 1txst - removed redundant pla/pha followed by txa/tya
+	%1
+}  if same(%1 'txa' 'tya')
+
+
+replace restart {
+	php
+	%1 %2
+	plp
+} by {
+	; Peephole stack 3 - removed redundant php/plp around a store
+	%1 %2
+}  if same(%1 'sta' 'stx' 'sty' )
+
+
+replace restart {
+	php
+	plp
+} by {
+	; Peephole stack 4 - removed redundant php/plp
+}
+
+replace restart {
+	%1
+	lda	%2
+} by {
+	; Peephole 2txld - removed unused txa/tya folowed by lda
+	lda	%2
+} if same(%1 'txa' 'tya')
+
+replace restart {
+	%1
+	ldx	%2
+} by {
+	; Peephole 2b - removed unused tax/inx/tsx followed by ldx
+	ldx	%2
+} if same(%1 'tax' 'inx' 'tsx')
+
+replace restart {
+	tax
+	tsx
+} by {
+	; Peephole 2c - removed unused tax followed by tsx
+	tsx
+}
+
+replace restart {
+	tsx
+	tax
+} by {
+	; Peephole 2d - removed unused tsx followed by tax
+	tax
+}
+
+replace restart {
+	%1
+	ldy	%2
+} by {
+	; Peephole 2e - removed unused tay/iny followed by ldy
+	ldy	%2
+} if same(%1 'tay' 'iny')
+
+replace restart {
+	tax
+	txa
+} by {
+	; Peephole 2f - removed unused txa preceded by tax
+	tax
+}
+
+replace restart {
+	tay
+	tya
+} by {
+	; Peephole 2g - removed unused tya preceded by tay
+	tay
+}
+
+replace restart {
+	ldx %1
+	tax
+} by {
+	; Peephole 2f - removed unused ldx followed by tax
+	tax
+}
+
+replace restart {
+	ldy %1
+	tay
+} by {
+	; Peephole 2g - removed unused ldy followed by tay
+	tay
+}
+
+////////////////////////////////////////////////////////
+// Remove unnecessary cmp/cpx/cpy #00
+////////////////////////////////////////////////////////
+
+replace restart {
+	lda	%1
+	cmp	#0x00
+} by {
+	; Peephole 3a	- eliminated redundant cmp #0x00
+	lda	%1
+}
+
+replace restart {
+	pla
+	cmp	#0x00
+} by {
+	; Peephole 3b	- eliminated redundant cmp #0x00
+	pla
+}
+
+replace restart {
+	ldx	%1
+	cpx	#0x00
+} by {
+	; Peephole 3c	- eliminated redundant cpx #0x00
+	ldx	%1
+}
+
+replace restart {
+	ldy	%1
+	cpy	#0x00
+} by {
+	; Peephole 3d	- eliminated redundant cpy #0x00
+	ldy	%1
+}
+
+replace restart {
+	%1
+	cpx	#0x00
+} by {
+	; Peephole 3e	- eliminated redundant cpx #0x00
+	%1
+} if same(%1 'inx' 'dex' )
+
+replace restart {
+	%1
+	cpy	#0x00
+} by {
+	; Peephole 3f	- eliminated redundant cpy #0x00
+	%1
+} if same(%1 'iny' 'dey' )
+
+////////////////////////////////////////////////////////
+// 
+////////////////////////////////////////////////////////
+
+replace restart {
+	lda	%2
+	sta	%2
+} by {
+	; Peephole 4sta - removed redundant sta
+	lda	%2
+}
+
+replace restart {
+	lda	%1
+	pla
+} by {
+	; Peephole 4lda - removed dead lda
+	pla
+}
+
+replace restart {
+	ldx	%2
+	stx	%2
+} by {
+	; Peephole 4stx - removed redundant stx
+	ldx	%2
+}
+
+replace restart {
+	ldy	%2
+	sty	%2
+} by {
+	; Peephole 4sty - removed redundant sty
+	ldy	%2
+}
+
+
+
+replace restart {
+	lda	%2
+	%1 	a
+	sta	%2
+} by {
+	; Peephole 4st - removed redundant sta
+	%1	%2
+	lda	%2
+} if same(%1 'asl' 'rol' 'ror')
+
+replace restart {
+	lda	%4
+	%1	%2
+	lda	%3
+} by {
+	; Peephole 4a - removed redundant lda not followed by sta or branch
+	%1	%2
+	lda	%3
+} if notSame(%1 'sta' 'adc' 'sbc' 'cmp' 'bne' 'beq' 'bpl' 'bmi' 'jsr' 'jmp'), notSame(%2 'a')
+
+//same(%1 'ldx' 'ldy' 'stx' 'sty' 'cpx' 'cpy')
+
+replace restart {
+	ldx	%4
+	%1	%2
+	ldx	%3
+} by {
+	; Peephole 4x - removed redundant lda not followed by sta or branch
+	%1	%2
+	ldx	%3
+} if notSame(%1 'stx' 'cpx' 'bne' 'beq' 'bpl' 'bmi' 'jsr' 'jmp')
+
+replace restart {
+	ldy	%4
+	%1 	%2
+	ldy	%3
+} by {
+	; Peephole 4y - removed redundant lda not followed by sta or branch
+	%1	%2
+	ldy	%3
+} if notSame(%1 'sty' 'cpy' 'bne' 'beq' 'bpl' 'bmi' 'jsr' 'jmp')
+
+replace restart {
+	lda	%3
+	%1
+	lda	%2
+} by {
+	; Peephole 4a1 - removed redundant lda (followed by inx/iny/dex/dey)
+	%1 
+	lda	%2
+} if notSame(%1 'pha' 'php' 'tax' 'tay')
+
+replace restart {
+	ldx	%3
+	%1
+	ldx	%2
+} by {
+	; Peephole 4x1 - removed redundant ldx (followed by inx/iny/dex/dey)
+	%1 
+	ldx	%2
+} if notSame(%1 'txa' 'txs')
+
+
+////////////////////////////////////////////////////////
+// Replace jmp with branch
+////////////////////////////////////////////////////////
+
+replace restart {
+	bne	%1
+	jmp	%5
+%1:
+} by {
+	; Peephole 5a	- eliminated jmp
+	beq	%5
+%1:
+} if labelInRange(%5), labelRefCountChange(%1 -1)
+
+replace restart {
+	beq	%1
+	jmp	%5
+%1:
+} by {
+	; Peephole 5b	- eliminated jmp
+	bne	%5
+%1:
+} if labelInRange(%5), labelRefCountChange(%1 -1)
+
+replace restart {
+	bcc	%1
+	jmp	%5
+%1:
+} by {
+	; Peephole 5c	- eliminated jmp
+	bcs	%5
+%1:
+} if labelInRange(%5), labelRefCountChange(%1 -1)
+
+replace restart {
+	bcs	%1
+	jmp	%5
+%1:
+} by {
+	; Peephole 5d	- eliminated jmp
+	bcc	%5
+%1:
+} if labelInRange(%5), labelRefCountChange(%1 -1)
+
+replace restart {
+	bpl	%1
+	jmp	%5
+%1:
+} by {
+	; Peephole 5e	- eliminated jmp
+	bmi	%5
+%1:
+} if labelInRange(%5), labelRefCountChange(%1 -1)
+
+replace restart {
+	bmi	%1
+	jmp	%5
+%1:
+} by {
+	; Peephole 5f	- eliminated jmp
+	bpl	%5
+%1:
+} if labelInRange(%5), labelRefCountChange(%1 -1)
+
+replace restart {
+	bvc	%1
+	jmp	%5
+%1:
+} by {
+	; Peephole 5g	- eliminated jmp
+	bvs	%5
+%1:
+} if labelInRange(%5), labelRefCountChange(%1 -1)
+
+replace restart {
+	bvs	%1
+	jmp	%5
+%1:
+} by {
+	; Peephole 5h	- eliminated jmp
+	bvc	%5
+%1:
+} if labelInRange(%5), labelRefCountChange(%1 -1)
+
+////////////////////////////////////////////////////////
+// Replace branch to jmp with branch
+////////////////////////////////////////////////////////
+
+replace restart {
+	%1	%5
+} by {
+	; Peephole 6b  - replaced branch to jmp with branch
+	%1	%6
+} if same(%1 'bne' 'beq' 'bcc' 'bcs' 'bvc' 'bvs' 'bpl' 'bmi'), labelIsUncondJump(%5), notSame(%5 %6), labelInRange(%6), labelRefCountChange(%5 -1), labelRefCountChange(%6 +1)
+
+replace restart {
+	jmp	%5
+} by {
+	; Peephole 6c  - replaced jmp to jmp with jmp
+	jmp	%6
+} if labelIsUncondJump(%5), notSame(%5 %6), labelRefCountChange(%5 -1), labelRefCountChange(%6 +1)
+
+replace restart {
+	jmp	%5
+} by {
+	; Peephole 6a  - replaced jmp to rts with rts
+	rts
+} if optimizeReturn(), labelIsReturnOnly(%5), labelRefCountChange(%5 -1)
+
+////////////////////////////////////////////////////////
+// Remove branch/jump to following label
+////////////////////////////////////////////////////////
+
+replace restart {
+        %1	%2
+%2:
+} by {
+        ; Peephole 7   - eliminated branch
+%2:
+} if same(%1 'bne' 'beq' 'bcc' 'bcs' 'bvc' 'bvs' 'bpl' 'bmi' 'jmp' 'bra'), labelRefCountChange(%2 -1)
+
+
+// should be one of the last peepholes
+replace restart {
+%1:
+} by {
+	; Peephole 500    removed redundant label %1
+} if labelRefCount(%1 0)
+
+replace restart {
+	jsr	%1
+	rts
+} by {
+	; Peephole 501 did tail call optimization.
+	jmp	%1
+} if optimizeReturn()
diff -Nru sdcc-4.0.0+dfsg/src/mos6502/ralloc2.cc sdcc-4.2.0+dfsg/src/mos6502/ralloc2.cc
--- sdcc-4.0.0+dfsg/src/mos6502/ralloc2.cc	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/mos6502/ralloc2.cc	2022-02-06 00:37:14.000000000 +0000
@@ -0,0 +1,691 @@
+// Philipp Klaus Krause, philipp@informatik.uni-frankfurt.de, pkk@spth.de, 2010 - 2011
+//
+// (c) 2012 Goethe-Universität Frankfurt
+//
+// This program is free software; you can redistribute it and/or modify it
+// under the terms of the GNU General Public License as published by the
+// Free Software Foundation; either version 2, or (at your option) any
+// later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+//
+// An optimal, polynomial-time register allocator.
+
+//#define DEBUG_RALLOC_DEC // Uncomment to get debug messages while doing register allocation on the tree decomposition.
+//#define DEBUG_RALLOC_DEC_ASS // Uncomment to get debug messages about assignments while doing register allocation on the tree decomposition (much more verbose than the one above).
+
+#define TD_SALLOC
+#define CH_SALLOC
+
+#include "SDCCralloc.hpp"
+
+extern "C"
+{
+  #include "ralloc.h"
+  #include "gen.h"
+  float drym6502iCode (iCode *ic);
+  bool m6502_assignment_optimal;
+}
+
+#define REG_A 0
+#define REG_X 1
+#define REG_Y 2
+
+template 
+static void add_operand_conflicts_in_node(const cfg_node &n, I_t &I)
+{
+  const iCode *ic = n.ic;
+  
+  const operand *result = IC_RESULT(ic);
+  const operand *left = IC_LEFT(ic);
+  const operand *right = IC_RIGHT(ic);
+	
+  if(!result || !IS_SYMOP(result))
+    return;
+    
+  // Todo: Identify more operations that code generation can always handle and exclude them (as done for the z80-like ports).
+  if (ic->op == '=')
+    return;
+
+  operand_map_t::const_iterator oir, oir_end, oirs; 
+  boost::tie(oir, oir_end) = n.operands.equal_range(OP_SYMBOL_CONST(result)->key);
+  if(oir == oir_end)
+    return;
+    
+  operand_map_t::const_iterator oio, oio_end;
+  
+  if(left && IS_SYMOP(left))
+    for(boost::tie(oio, oio_end) = n.operands.equal_range(OP_SYMBOL_CONST(left)->key); oio != oio_end; ++oio)
+      for(oirs = oir; oirs != oir_end; ++oirs)
+        {
+          var_t rvar = oirs->second;
+          var_t ovar = oio->second;
+          if(I[rvar].byte < I[ovar].byte)
+            boost::add_edge(rvar, ovar, I);
+        }
+        
+  if(right && IS_SYMOP(right))
+    for(boost::tie(oio, oio_end) = n.operands.equal_range(OP_SYMBOL_CONST(right)->key); oio != oio_end; ++oio)
+      for(oirs = oir; oirs != oir_end; ++oirs)
+        {
+          var_t rvar = oirs->second;
+          var_t ovar = oio->second;
+          if(I[rvar].byte < I[ovar].byte)
+            boost::add_edge(rvar, ovar, I);
+        }
+}
+
+// Return true, iff the operand is placed (partially) in r.
+template 
+static bool operand_in_reg(const operand *o, reg_t r, const i_assignment_t &ia, unsigned short int i, const G_t &G)
+{
+  if(!o || !IS_SYMOP(o))
+    return(false);
+
+  if(r >= port->num_regs)
+    return(false);
+
+  operand_map_t::const_iterator oi, oi_end;
+  for(boost::tie(oi, oi_end) = G[i].operands.equal_range(OP_SYMBOL_CONST(o)->key); oi != oi_end; ++oi)
+    if(oi->second == ia.registers[r][1] || oi->second == ia.registers[r][0])
+      return(true);
+
+  return(false);
+}
+
+template 
+static bool operand_is_ax(const operand *o, const assignment &a, unsigned short int i, const G_t &G, const I_t &I)
+{  
+  if(!o || !IS_SYMOP(o))
+    return(false);
+ 
+  operand_map_t::const_iterator oi, oi2, oi_end;
+  boost::tie(oi, oi_end) = G[i].operands.equal_range(OP_SYMBOL_CONST(o)->key);
+  
+  if(oi == oi_end)
+    return(false);
+
+  oi2 = oi;
+  oi2++;
+  if (oi2 == oi_end)
+    return(false);
+  
+  // Register combinations code generation cannot handle yet (AX, AY, XY, YA).
+  if(std::binary_search(a.local.begin(), a.local.end(), oi->second) && std::binary_search(a.local.begin(), a.local.end(), oi2->second))
+    {
+      const reg_t l = a.global[oi->second];
+      const reg_t h = a.global[oi2->second];
+      if(l == REG_X && h == REG_A)
+        return(true);
+    }
+
+  return(false);
+}
+
+template 
+static bool XAinst_ok(const assignment &a, unsigned short int i, const G_t &G, const I_t &I)
+{
+  const iCode *ic = G[i].ic;
+
+  // Instructions that can handle anything.
+  if(ic->op == '!' ||
+    ic->op == '~' ||
+    ic->op == UNARYMINUS ||
+    ic->op == CALL ||
+    ic->op == PCALL ||
+    ic->op == FUNCTION ||
+    ic->op == ENDFUNCTION ||
+    ic->op == RETURN ||
+    ic->op == LABEL ||
+    ic->op == GOTO ||
+    ic->op == IFX ||
+    ic->op == '+' ||
+    ic->op == '-' ||
+    ic->op == '*' ||
+    ic->op == '/' ||
+    ic->op == '%' ||
+    ic->op == '<' || ic->op == '>' || ic->op == LE_OP || ic->op == GE_OP ||
+    ic->op == NE_OP || ic->op == EQ_OP ||
+    ic->op == AND_OP ||
+    ic->op == OR_OP ||
+    ic->op == '^' ||
+    ic->op == '|' ||
+    ic->op == BITWISEAND ||
+    ic->op == GETABIT ||
+    ic->op == GETBYTE ||
+    ic->op == GETWORD ||
+    ic->op == LEFT_OP ||
+    ic->op == RIGHT_OP ||
+    //ic->op == '=' ||  /* both regular assignment and POINTER_SET safe */
+    //ic->op == GET_VALUE_AT_ADDRESS ||
+    ic->op == ADDRESS_OF ||
+    ic->op == CAST ||
+    ic->op == DUMMY_READ_VOLATILE ||
+    ic->op == SWAP)
+    return(true);
+
+  if(ic->op == IFX && ic->generated)
+    return(true);
+
+  const i_assignment_t &ia = a.i_assignment;
+
+  bool unused_A = (ia.registers[REG_A][1] < 0);
+  bool unused_Y = (ia.registers[REG_Y][1] < 0);
+  bool unused_X = (ia.registers[REG_X][1] < 0);
+
+  if(unused_X && unused_A && unused_Y)
+    return(true);
+
+#if 0
+  std::cout << "XAinst_ok: at (" << i << ", " << ic->key << ")\nX = (" << ia.registers[REG_X][0] << ", " << ia.registers[REG_X][1] << "), A = (" << ia.registers[REG_A][0] << ", " << ia.registers[REG_A][1] << ")inst " << i << ", " << ic->key << "\n";
+#endif
+
+  const operand *left = IC_LEFT(ic);
+  const operand *right = IC_RIGHT(ic);
+  const operand *result = IC_RESULT(ic);
+
+  bool result_in_A = operand_in_reg(result, REG_A, ia, i, G) && !(ic->op == '=' && POINTER_SET(ic));
+  bool result_in_Y = operand_in_reg(result, REG_Y, ia, i, G) && !(ic->op == '=' && POINTER_SET(ic));
+  bool result_in_X = operand_in_reg(result, REG_X, ia, i, G) && !(ic->op == '=' && POINTER_SET(ic));
+  bool left_in_A = operand_in_reg(result, REG_A, ia, i, G);
+  bool left_in_X = operand_in_reg(result, REG_X, ia, i, G);
+
+  const cfg_dying_t &dying = G[i].dying;
+
+  bool dying_A = result_in_A || dying.find(ia.registers[REG_A][1]) != dying.end() || dying.find(ia.registers[REG_A][0]) != dying.end();
+  bool dying_Y = result_in_Y || dying.find(ia.registers[REG_Y][1]) != dying.end() || dying.find(ia.registers[REG_Y][0]) != dying.end();
+  bool dying_X = result_in_X || dying.find(ia.registers[REG_X][1]) != dying.end() || dying.find(ia.registers[REG_X][0]) != dying.end();
+
+  bool result_only_XA = (result_in_X || unused_X || dying_X) && (result_in_A || unused_A || dying_A);
+
+  if(ic->op == JUMPTABLE && (unused_A || dying_A))
+    return(true);
+
+  if(ic->op == IPUSH && (unused_A || dying_A || left_in_A || operand_in_reg(left, REG_Y, ia, i, G) || left_in_X))
+    return(true);
+
+  if(ic->op == RECEIVE && (!ic->next || !(ic->next->op == RECEIVE) || !result_in_X || getSize(operandType(result)) >= 2))
+    return(true);
+
+  if(ic->op == SEND && ic->next && ic->next->op == SEND && ic->next->next && ic->next->next->op == SEND)
+    return(true);
+
+  if(ic->op == SEND && ic->next && ic->next->op == SEND && (unused_X || dying_X))
+    return(true);
+
+  if(ic->op == SEND && (unused_X || dying_X) && (unused_A || dying_A))
+    return(true);
+
+  if(ic->op == SEND && ic->next && (ic->next->op == CALL || ic->next->op == PCALL)) // Might mess up A and X, but these would have been saved before if surviving, and will not be needed again before the call.
+    return(true);
+
+  if((ic->op == CRITICAL || ic->op == ENDCRITICAL) && (unused_A || dying_A))
+    return(true);
+    
+  // Y must be free
+  if ((ic->op == GET_VALUE_AT_ADDRESS) && (unused_Y || dying_Y))
+    return true;
+  if (POINTER_SET(ic) && (unused_Y || dying_Y))
+    return true;
+  if (ic->op == '=')
+    return true;
+
+  return(false);
+}
+
+template 
+static bool AXinst_ok(const assignment &a, unsigned short int i, const G_t &G, const I_t &I)
+{
+  const iCode *ic = G[i].ic;
+
+  const i_assignment_t &ia = a.i_assignment;
+
+  if(ic->op == '!' ||
+    ic->op == '~' ||
+    ic->op == IPUSH ||
+    ic->op == CALL ||
+    ic->op == FUNCTION ||
+    ic->op == ENDFUNCTION ||
+    ic->op == RETURN ||
+    ic->op == LABEL ||
+    ic->op == GOTO ||
+    ic->op == '+' ||
+    ic->op == '-' ||
+    ic->op == NE_OP || ic->op == EQ_OP ||
+    ic->op == '^' ||
+    ic->op == '|' ||
+    ic->op == BITWISEAND ||
+    ic->op == GETABIT ||
+    ic->op == GETBYTE ||
+    ic->op == GETWORD ||
+    /*ic->op == LEFT_OP ||
+    ic->op == RIGHT_OP ||*/
+    ic->op == GET_VALUE_AT_ADDRESS ||
+    ic->op == '=' ||
+    ic->op == ADDRESS_OF ||
+    ic->op == RECEIVE ||
+    ic->op == SEND ||
+    ic->op == DUMMY_READ_VOLATILE ||
+    ic->op == CRITICAL ||
+    ic->op == ENDCRITICAL ||
+    ic->op == SWAP)
+    return(true);
+
+  bool unused_A = (ia.registers[REG_A][1] < 0);
+  bool unused_X = (ia.registers[REG_X][1] < 0);
+
+  if (unused_A || unused_X)
+    return(true);
+
+  const operand *left = IC_LEFT(ic);
+  const operand *right = IC_RIGHT(ic);
+  const operand *result = IC_RESULT(ic);
+
+  bool result_in_A = operand_in_reg(result, REG_A, ia, i, G) && !(ic->op == '=' && POINTER_SET(ic));
+  bool result_in_X = operand_in_reg(result, REG_X, ia, i, G) && !(ic->op == '=' && POINTER_SET(ic));
+  bool left_in_A = operand_in_reg(result, REG_A, ia, i, G);
+  bool left_in_X = operand_in_reg(result, REG_X, ia, i, G);
+  bool right_in_A = operand_in_reg(result, REG_A, ia, i, G);
+  bool right_in_X = operand_in_reg(result, REG_X, ia, i, G);
+
+  bool result_is_ax = operand_is_ax (result, a, i, G, I);
+  bool left_is_ax = operand_is_ax (left, a, i, G, I);
+  bool right_is_ax = operand_is_ax (right, a, i, G, I);
+
+  if (!result_is_ax && !left_is_ax && !right_is_ax)
+    return(true);
+
+  return(false);
+}
+
+template 
+static void set_surviving_regs(const assignment &a, unsigned short int i, const G_t &G, const I_t &I)
+{
+  iCode *ic = G[i].ic;
+  
+  bitVectClear(ic->rMask);
+  bitVectClear(ic->rSurv);
+  
+  cfg_alive_t::const_iterator v, v_end;
+  for (v = G[i].alive.begin(), v_end = G[i].alive.end(); v != v_end; ++v)
+    {
+      if(a.global[*v] < 0)
+        continue;
+      ic->rMask = bitVectSetBit(ic->rMask, a.global[*v]);
+      if(G[i].dying.find(*v) == G[i].dying.end())
+        if(!((IC_RESULT(ic) && !POINTER_SET(ic)) && IS_SYMOP(IC_RESULT(ic)) && OP_SYMBOL_CONST(IC_RESULT(ic))->key == I[*v].v))
+          ic->rSurv = bitVectSetBit(ic->rSurv, a.global[*v]);
+    }
+}
+
+template 
+static void assign_operand_for_cost(operand *o, const assignment &a, unsigned short int i, const G_t &G, const I_t &I)
+{
+  if(!o || !IS_SYMOP(o))
+    return;
+  symbol *sym = OP_SYMBOL(o);
+  operand_map_t::const_iterator oi, oi_end;
+  for(boost::tie(oi, oi_end) = G[i].operands.equal_range(OP_SYMBOL_CONST(o)->key); oi != oi_end; ++oi)
+    {
+      var_t v = oi->second;
+      if(a.global[v] >= 0)
+        { 
+          sym->regs[I[v].byte] = regsm6502 + a.global[v];   
+          sym->isspilt = false;
+          sym->nRegs = I[v].size;
+          sym->accuse = 0;
+        }
+      else
+        {
+          for(int i = 0; i < I[v].size; i++)
+            sym->regs[i] = 0;
+          sym->accuse = 0;
+          sym->nRegs = I[v].size;
+          sym->isspilt = true;
+        }
+    }
+}
+
+template 
+static void assign_operands_for_cost(const assignment &a, unsigned short int i, const G_t &G, const I_t &I)
+{
+  const iCode *ic = G[i].ic;
+  
+  if(ic->op == IFX)
+    assign_operand_for_cost(IC_COND(ic), a, i, G, I);
+  else if(ic->op == JUMPTABLE)
+    assign_operand_for_cost(IC_JTCOND(ic), a, i, G, I);
+  else
+    {
+      assign_operand_for_cost(IC_LEFT(ic), a, i, G, I);
+      assign_operand_for_cost(IC_RIGHT(ic), a, i, G, I);
+      assign_operand_for_cost(IC_RESULT(ic), a, i, G, I);
+    }
+    
+  if(ic->op == SEND && ic->builtinSEND)
+    assign_operands_for_cost(a, (unsigned short)*(adjacent_vertices(i, G).first), G, I);
+}
+
+// Check that the operand is either fully in registers or fully in memory.
+template 
+static bool operand_sane(const operand *o, const assignment &a, unsigned short int i, const G_t &G, const I_t &I)
+{
+  if(!o || !IS_SYMOP(o))
+    return(true);
+ 
+  operand_map_t::const_iterator oi, oi2, oi_end;
+  boost::tie(oi, oi_end) = G[i].operands.equal_range(OP_SYMBOL_CONST(o)->key);
+  
+  if(oi == oi_end)
+    return(true);
+
+  // Go to the second byte. If the operand is only a single byte, it cannot be
+  // an unsupported register combination or split between register and memory.
+  oi2 = oi;
+  oi2++;
+  if (oi2 == oi_end)
+    return(true);
+  
+  // Register combinations code generation cannot handle yet (AY, XY, YA).
+  if(std::binary_search(a.local.begin(), a.local.end(), oi->second) && std::binary_search(a.local.begin(), a.local.end(), oi2->second))
+    {
+      const reg_t l = a.global[oi->second];
+      const reg_t h = a.global[oi2->second];
+      if(l == REG_A && h == REG_Y || l == REG_Y)
+        return(false);
+    }
+  
+  // In registers.
+  if(std::binary_search(a.local.begin(), a.local.end(), oi->second))
+    {
+      while(++oi != oi_end)
+        if(!std::binary_search(a.local.begin(), a.local.end(), oi->second))
+          return(false);
+    }
+  else
+    {
+       while(++oi != oi_end)
+        if(std::binary_search(a.local.begin(), a.local.end(), oi->second))
+          return(false);
+    }
+ 
+  return(true);
+}
+
+template 
+static bool inst_sane(const assignment &a, unsigned short int i, const G_t &G, const I_t &I)
+{
+  const iCode *ic = G[i].ic;
+
+  return(operand_sane(IC_RESULT(ic), a, i, G, I) && operand_sane(IC_LEFT(ic), a, i, G, I) && operand_sane(IC_RIGHT(ic), a, i, G, I));
+}
+
+// Cost function.
+template 
+static float instruction_cost(const assignment &a, unsigned short int i, const G_t &G, const I_t &I)
+{
+  iCode *ic = G[i].ic;
+  float c;
+
+  wassert (TARGET_IS_MOS6502 || TARGET_IS_MOS65C02);
+  wassert(ic);
+
+  if(!inst_sane(a, i, G, I))
+    return(std::numeric_limits::infinity());
+
+#if 0
+  std::cout << "Calculating at cost at ic " << ic->key << " for: ";
+  for(unsigned int i = 0; i < boost::num_vertices(I); i++)
+  {
+  	std::cout << "(" << i << ", " << int(a.global[i]) << ") ";
+  }
+  std::cout << "\n";
+  std::cout.flush();
+#endif
+
+  if(ic->generated)
+    return(0.0f);
+
+  if(!XAinst_ok(a, i, G, I))
+    return(std::numeric_limits::infinity());
+
+  if(!AXinst_ok(a, i, G, I))
+    return(std::numeric_limits::infinity());
+
+  switch(ic->op)
+    {
+    // Register assignment doesn't matter for these:
+    case FUNCTION:
+    case ENDFUNCTION:
+    case LABEL:
+    case GOTO:
+    case INLINEASM:
+      return(0.0f);
+    case '!':
+    case '~':
+    case UNARYMINUS:
+    case '+':
+    case '-':
+    case '^':
+    case '|':
+    case BITWISEAND:
+    case IPUSH:
+    //case IPOP:
+    case CALL:
+    case PCALL:
+    case RETURN:
+    case '*':
+    case '/':
+    case '%':
+    case '>':
+    case '<':
+    case LE_OP:
+    case GE_OP:
+    case EQ_OP:
+    case NE_OP:
+    case AND_OP:
+    case OR_OP:
+    case RLC:
+    case RRC:
+    case GETABIT:
+    case GETBYTE:
+    case GETWORD:
+    case SWAP:
+    case LEFT_OP:
+    case RIGHT_OP:
+    case GET_VALUE_AT_ADDRESS:
+//    case SET_VALUE_AT_ADDRESS:
+    case '=':
+    case IFX:
+    case ADDRESS_OF:
+    case JUMPTABLE:
+    case CAST:
+    case RECEIVE:
+    case SEND:
+    case DUMMY_READ_VOLATILE:
+    case CRITICAL:
+    case ENDCRITICAL:
+      assign_operands_for_cost(a, i, G, I);
+      set_surviving_regs(a, i, G, I);
+      c = drym6502iCode(ic);
+      ic->generated = false;
+      return(c);
+    default:
+      return(0.0f);
+    }
+}
+
+// For early removal of assignments that cannot be extended to valid assignments. This is just a dummy for now, it probably isn't really needed for m6502 due to the low number of registers.
+template 
+static bool assignment_hopeless(const assignment &a, unsigned short int i, const G_t &G, const I_t &I, const var_t lastvar)
+{
+  return(false);
+}
+
+// Increase chance of finding good compatible assignments at join nodes. This is just a dummy for now, it probably isn't really needed for m6502 due to the low number of registers.
+template 
+static void get_best_local_assignment_biased(assignment &a, typename boost::graph_traits::vertex_descriptor t, const T_t &T)
+{
+  a = *T[t].assignments.begin();
+
+  std::set::const_iterator vi, vi_end;
+  varset_t newlocal;
+  std::set_union(T[t].alive.begin(), T[t].alive.end(), a.local.begin(), a.local.end(), std::inserter(newlocal, newlocal.end()));
+  a.local = newlocal;
+}
+
+// This is just a dummy for now, it probably isn't really needed for m6502 due to the low number of registers.
+template 
+static float rough_cost_estimate(const assignment &a, unsigned short int i, const G_t &G, const I_t &I)
+{
+  return(0.0f);
+}
+
+// Code for another ic is generated when generating this one. Mark the other as generated.
+static void extra_ic_generated(iCode *ic)
+{
+  if(ic->op == '>' || ic->op == '<' || ic->op == LE_OP || ic->op == GE_OP || ic->op == EQ_OP || ic->op == NE_OP || ic->op == '^' || ic->op == '|' || ic->op == BITWISEAND)
+    {
+      iCode *ifx;
+      if (ifx = ifxForOp (IC_RESULT (ic), ic))
+        {
+          OP_SYMBOL (IC_RESULT (ic))->for_newralloc = false;
+          OP_SYMBOL (IC_RESULT (ic))->regType = REG_CND;
+          ifx->generated = true;
+        }
+    }
+  if(ic->op == '-' && IS_VALOP (IC_RIGHT (ic)) && operandLitValue (IC_RIGHT (ic)) == 1 && getSize(operandType(IC_RESULT (ic))) == 1 && !isOperandInFarSpace (IC_RESULT (ic)) && isOperandEqual (IC_RESULT (ic), IC_LEFT (ic)))
+    {
+      iCode *ifx;
+      if (ifx = ifxForOp (IC_RESULT (ic), ic))
+        {
+          OP_SYMBOL (IC_RESULT (ic))->for_newralloc = false;
+          OP_SYMBOL (IC_RESULT (ic))->regType = REG_CND;
+          ifx->generated = true;
+        }
+    }
+}
+
+template 
+static bool tree_dec_ralloc(T_t &T, G_t &G, const I_t &I)
+{
+  bool assignment_optimal;
+
+  con2_t I2(boost::num_vertices(I));
+  for(unsigned int i = 0; i < boost::num_vertices(I); i++)
+    {
+      I2[i].v = I[i].v;
+      I2[i].byte = I[i].byte;
+      I2[i].size = I[i].size;
+      I2[i].name = I[i].name;
+    }
+  typename boost::graph_traits::edge_iterator e, e_end;
+  for(boost::tie(e, e_end) = boost::edges(I); e != e_end; ++e)
+    add_edge(boost::source(*e, I), boost::target(*e, I), I2);
+
+  assignment ac;
+  assignment_optimal = true;
+  tree_dec_ralloc_nodes(T, find_root(T), G, I2, ac, &assignment_optimal);
+
+  const assignment &winner = *(T[find_root(T)].assignments.begin());
+
+#ifdef DEBUG_RALLOC_DEC
+  std::cout << "Winner: ";
+  for(unsigned int i = 0; i < boost::num_vertices(I); i++)
+  {
+  	std::cout << "(" << i << ", " << int(winner.global[i]) << ") ";
+  }
+  std::cout << "\n";
+  std::cout << "Cost: " << winner.s << "\n";
+  std::cout.flush();
+#endif
+
+  // Todo: Make this an assertion
+  if(winner.global.size() != boost::num_vertices(I))
+    {
+      std::cerr << "ERROR: No Assignments at root\n";
+      exit(-1);
+    }
+
+  for(unsigned int v = 0; v < boost::num_vertices(I); v++)
+    {
+      symbol *sym = (symbol *)(hTabItemWithKey(liveRanges, I[v].v));
+      if(winner.global[v] >= 0)
+        { 
+          sym->regs[I[v].byte] = regsm6502 + winner.global[v];   
+          sym->isspilt = false;
+          sym->nRegs = I[v].size;
+          sym->accuse = 0;
+        }
+      else
+        {
+          for(int i = 0; i < I[v].size; i++)
+            sym->regs[i] = 0;
+          sym->accuse = 0;
+          sym->nRegs = I[v].size;
+          wassert (sym->nRegs);
+          //spillThis(sym); Leave it to regFix, which can do some spillocation compaction. Todo: Use Thorup instead.
+          sym->isspilt = false;
+        }
+    }
+
+  for(unsigned int i = 0; i < boost::num_vertices(G); i++)
+    set_surviving_regs(winner, i, G, I);
+
+  return(!assignment_optimal);
+}
+
+iCode *m6502_ralloc2_cc(ebbIndex *ebbi)
+{
+  eBBlock **const ebbs = ebbi->bbOrder;
+  const int count = ebbi->count;
+  iCode *ic;
+
+#ifdef DEBUG_RALLOC_DEC
+  std::cout << "Processing " << currFunc->name << " from " << dstFileName << "\n"; std::cout.flush();
+#endif
+
+  cfg_t control_flow_graph;
+
+  con_t conflict_graph;
+
+  ic = create_cfg(control_flow_graph, conflict_graph, ebbi);
+
+  if(options.dump_graphs)
+    dump_cfg(control_flow_graph);
+
+  if(options.dump_graphs)
+    dump_con(conflict_graph);
+
+  tree_dec_t tree_decomposition;
+
+  get_nice_tree_decomposition(tree_decomposition, control_flow_graph);
+
+  alive_tree_dec(tree_decomposition, control_flow_graph);
+
+  good_re_root(tree_decomposition);
+  nicify(tree_decomposition);
+  alive_tree_dec(tree_decomposition, control_flow_graph);
+
+  if(options.dump_graphs)
+    dump_tree_decomposition(tree_decomposition);
+
+  guessCounts (ic, ebbi);
+
+  m6502_assignment_optimal = !tree_dec_ralloc(tree_decomposition, control_flow_graph, conflict_graph);
+
+  m6502RegFix (ebbs, count);
+
+  /* do the overlaysegment stuff SDCCmem.c */
+  doOverlays (ebbs, count);
+
+  return(ic);
+}
+
diff -Nru sdcc-4.0.0+dfsg/src/mos6502/ralloc.c sdcc-4.2.0+dfsg/src/mos6502/ralloc.c
--- sdcc-4.0.0+dfsg/src/mos6502/ralloc.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/mos6502/ralloc.c	2022-02-11 06:17:03.000000000 +0000
@@ -0,0 +1,1636 @@
+/*------------------------------------------------------------------------
+
+  SDCCralloc.c - source file for register allocation. M6502 specific
+
+                Written By -  Sandeep Dutta . sandeep.dutta@usa.net (1998)
+
+   This program is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published by the
+   Free Software Foundation; either version 2, or (at your option) any
+   later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+   In other words, you are welcome to use, share and improve this program.
+   You are forbidden to forbid anyone else to use, share and improve
+   what you give them.   Help stamp out software-hoarding!
+-------------------------------------------------------------------------*/
+
+#include "ralloc.h"
+#include "gen.h"
+
+#include "dbuf_string.h"
+
+/* 6502 registers */
+reg_info regsm6502[] =
+{
+  {REG_GPR, A_IDX,   "a",  M6502MASK_A,  NULL, 0, 1},
+  {REG_GPR, X_IDX,   "x",  M6502MASK_X,  NULL, 0, 1},
+  {REG_GPR, Y_IDX,   "y",  M6502MASK_Y,  NULL, 0, 1},
+  {REG_GPR, YX_IDX,  "yx", M6502MASK_YX, NULL, 0, 1},
+  {REG_GPR, XA_IDX,  "xa", M6502MASK_XA, NULL, 0, 1},
+
+  {REG_CND, CND_IDX, "C",  0, NULL, 0, 1},
+  {0,       SP_IDX,  "sp", 0, NULL, 0, 1},
+};
+
+/* Flags to turn on debugging code.
+ */
+enum
+{
+  D_ALLOC = 0,
+};
+
+/** Local static variables */
+static struct
+  {
+    bitVect *spiltSet;
+    set *stackSpil;
+    bitVect *regAssigned;
+    bitVect *totRegAssigned;    /* final set of LRs that got into registers */
+    short blockSpil;
+    int slocNum;
+    bitVect *funcrUsed;         /* registers used in a function */
+    int stackExtend;
+    int dataExtend;
+  }
+_G;
+
+#if 1
+#define D(_a, _s)       if (_a)  { printf _s; fflush(stdout); }
+#else
+#define D(_a, _s)
+#endif
+extern void genm6502Code (iCode *);
+
+/* Shared with gen.c */
+int m6502_ptrRegReq;             /* one byte pointer register required */
+
+
+
+int m6502_nRegs = 7;
+
+reg_info *m6502_reg_a;
+reg_info *m6502_reg_x;
+reg_info *m6502_reg_y;
+reg_info *m6502_reg_yx;
+reg_info *m6502_reg_xa;
+reg_info *m6502_reg_sp;
+
+static void spillThis (symbol *);
+static void freeAllRegs ();
+
+/*-----------------------------------------------------------------*/
+/* m6502_regWithIdx - returns pointer to register with index number */
+/*-----------------------------------------------------------------*/
+reg_info *
+m6502_regWithIdx (int idx)
+{
+  int i;
+
+  for (i = 0; i < m6502_nRegs; i++)
+    if (regsm6502[i].rIdx == idx)
+      return ®sm6502[i];
+
+  werror (E_INTERNAL_ERROR, __FILE__, __LINE__,
+          "regWithIdx not found");
+  exit (1);
+}
+
+/*-----------------------------------------------------------------*/
+/* m6502_freeReg - frees a register                                */
+/*-----------------------------------------------------------------*/
+void
+m6502_freeReg (reg_info * reg)
+{
+  if (!reg)
+    {
+      werror (E_INTERNAL_ERROR, __FILE__, __LINE__,
+              "m6502_freeReg - Freeing NULL register");
+      exit (1);
+    }
+
+  reg->isFree = 1;
+
+  switch (reg->rIdx)
+    {
+      case A_IDX:
+        if (m6502_reg_x->isFree)
+          m6502_reg_xa->isFree = 1;
+        break;
+      case X_IDX:
+        if (m6502_reg_a->isFree)
+          m6502_reg_xa->isFree = 1;
+        if (m6502_reg_y->isFree)
+          m6502_reg_yx->isFree = 1;
+        break;
+      case Y_IDX:
+        if (m6502_reg_x->isFree)
+          m6502_reg_yx->isFree = 1;
+        break;
+      case YX_IDX:
+        m6502_reg_y->isFree = 1;
+        m6502_reg_x->isFree = 1;
+        if (m6502_reg_a->isFree)
+          m6502_reg_xa->isFree = 1;
+        break;
+      case XA_IDX:
+        m6502_reg_x->isFree = 1;
+        m6502_reg_a->isFree = 1;
+        if (m6502_reg_y->isFree)
+          m6502_reg_yx->isFree = 1;
+        break;
+      default:
+        break;
+    }
+}
+
+
+/*-----------------------------------------------------------------*/
+/* m6502_useReg - marks a register  as used                        */
+/*-----------------------------------------------------------------*/
+void
+m6502_useReg (reg_info * reg)
+{
+  reg->isFree = 0;
+
+  switch (reg->rIdx)
+    {
+      case A_IDX:
+        m6502_reg_xa->aop = NULL;
+        m6502_reg_xa->isFree = 0;
+        break;
+      case X_IDX:
+        m6502_reg_xa->aop = NULL;
+        m6502_reg_xa->isFree = 0;
+        m6502_reg_yx->aop = NULL;
+        m6502_reg_yx->isFree = 0;
+        break;
+      case Y_IDX:
+        m6502_reg_yx->aop = NULL;
+        m6502_reg_yx->isFree = 0;
+        break;
+      case YX_IDX:
+        m6502_reg_y->aop = NULL;
+        m6502_reg_y->isFree = 0;
+        m6502_reg_x->aop = NULL;
+        m6502_reg_x->isFree = 0;
+        break;
+      case XA_IDX:
+        m6502_reg_x->aop = NULL;
+        m6502_reg_x->isFree = 0;
+        m6502_reg_a->aop = NULL;
+        m6502_reg_a->isFree = 0;
+        break;
+      default:
+        break;
+    }
+}
+
+/*-----------------------------------------------------------------*/
+/* m6502_dirtyReg - marks a register as dirty                      */
+/*-----------------------------------------------------------------*/
+void
+m6502_dirtyReg (reg_info * reg)
+{
+  reg->aop = NULL;
+
+  switch (reg->rIdx)
+    {
+      case A_IDX:
+        m6502_reg_xa->aop = NULL;
+	m6502_reg_xa->isLitConst = 0;
+	m6502_reg_a->aop = NULL;
+	m6502_reg_a->isLitConst = 0;
+        break;
+      case X_IDX:
+        m6502_reg_xa->aop = NULL;
+	m6502_reg_xa->isLitConst = 0;
+        m6502_reg_yx->aop = NULL;
+	m6502_reg_yx->isLitConst = 0;
+	m6502_reg_x->aop = NULL;
+	m6502_reg_x->isLitConst = 0;
+        break;
+      case Y_IDX:
+        m6502_reg_yx->aop = NULL;
+	m6502_reg_yx->isLitConst = 0;
+	m6502_reg_y->aop = NULL;
+	m6502_reg_y->isLitConst = 0;
+        break;
+      case YX_IDX:
+        m6502_reg_yx->aop = NULL;
+	m6502_reg_yx->isLitConst = 0;
+        m6502_reg_y->aop = NULL;
+	m6502_reg_y->isLitConst = 0;
+        m6502_reg_x->aop = NULL;
+	m6502_reg_x->isLitConst = 0;
+        break;
+      case XA_IDX:
+        m6502_reg_xa->aop = NULL;
+	m6502_reg_xa->isLitConst = 0;
+        m6502_reg_x->aop = NULL;
+	m6502_reg_x->isLitConst = 0;
+        m6502_reg_a->aop = NULL;
+	m6502_reg_a->isLitConst = 0;
+        break;
+      default:
+        break;
+    }
+//  if (freereg)
+//    m6502_freeReg(reg);
+}
+
+/*-----------------------------------------------------------------*/
+/* noOverLap - will iterate through the list looking for over lap  */
+/*-----------------------------------------------------------------*/
+static int
+noOverLap (set * itmpStack, symbol * fsym)
+{
+  symbol *sym;
+
+  for (sym = setFirstItem (itmpStack); sym; sym = setNextItem (itmpStack))
+    {
+        if (bitVectBitValue(sym->clashes,fsym->key)) 
+          return 0;
+    }
+  return 1;
+}
+
+/*-----------------------------------------------------------------*/
+/* isFree - will return 1 if the a free spil location is found     */
+/*-----------------------------------------------------------------*/
+static
+DEFSETFUNC (isFree)
+{
+  symbol *sym = item;
+  V_ARG (symbol **, sloc);
+  V_ARG (symbol *, fsym);
+
+  /* if already found */
+  if (*sloc)
+    return 0;
+
+  /* if it is free && and the itmp assigned to
+     this does not have any overlapping live ranges
+     with the one currently being assigned and
+     the size can be accomodated  */
+  if (sym->isFree
+      && noOverLap (sym->usl.itmpStack, fsym)
+      && getSize (sym->type) >= getSize (fsym->type))
+    {
+      *sloc = sym;
+      return 1;
+    }
+
+  return 0;
+}
+
+/*-----------------------------------------------------------------*/
+/* createStackSpil - create a location somewhere to spill          */
+/*-----------------------------------------------------------------*/
+static symbol *
+createStackSpil (symbol * sym)
+{
+  symbol *sloc = NULL;
+  struct dbuf_s dbuf;
+  int useXstack, model;
+
+  /* first go try and find a free one that is already
+     existing on the stack */
+  if (applyToSet (_G.stackSpil, isFree, &sloc, sym))
+    {
+      /* found a free one : just update & return */
+      sym->usl.spillLoc = sloc;
+      sym->stackSpil = 1;
+      sloc->isFree = 0;
+      addSetHead (&sloc->usl.itmpStack, sym);
+      return sym;
+    }
+
+  /* could not then have to create one , this is the hard part
+     we need to allocate this on the stack : this is really a
+     hack!! but cannot think of anything better at this time */
+
+  D (D_ALLOC, ("createStackSpil: for sym %p %s (old currFunc->stack %ld)\n", sym, sym->name, (long)(currFunc->stack)));
+
+  dbuf_init (&dbuf, 128);
+  dbuf_printf (&dbuf, "sloc%d", _G.slocNum++);
+  sloc = newiTemp (dbuf_c_str (&dbuf));
+  dbuf_destroy (&dbuf);
+
+  /* set the type to the spilling symbol */
+  sloc->type = copyLinkChain (sym->type);
+  sloc->etype = getSpec (sloc->type);
+  SPEC_SCLS (sloc->etype) = S_DATA;
+  SPEC_EXTR (sloc->etype) = 0;
+  SPEC_STAT (sloc->etype) = 0;
+  SPEC_VOLATILE(sloc->etype) = 0;
+  SPEC_ABSA(sloc->etype) = 0;
+
+  /* we don't allow it to be allocated
+     onto the external stack since : so we
+     temporarily turn it off ; we also
+     turn off memory model to prevent
+     the spil from going to the external storage
+   */
+
+  useXstack = options.useXstack;
+  model = options.model;
+/*     noOverlay = options.noOverlay; */
+/*     options.noOverlay = 1; */
+  options.model = options.useXstack = 0;
+
+  allocLocal (sloc);
+
+  options.useXstack = useXstack;
+  options.model = model;
+/*     options.noOverlay = noOverlay; */
+  sloc->isref = 1;              /* to prevent compiler warning */
+
+  /* if it is on the stack then update the stack */
+  if (IN_STACK (sloc->etype))
+    {
+      currFunc->stack += getSize (sloc->type);
+      _G.stackExtend += getSize (sloc->type);
+    }
+  else
+    _G.dataExtend += getSize (sloc->type);
+
+  /* add it to the stackSpil set */
+  addSetHead (&_G.stackSpil, sloc);
+  sym->usl.spillLoc = sloc;
+  sym->stackSpil = 1;
+
+  /* add it to the set of itempStack set
+     of the spill location */
+  addSetHead (&sloc->usl.itmpStack, sym);
+
+  D (D_ALLOC, ("createStackSpil: created new %s\n", sloc->name));
+  return sym;
+}
+
+/*-----------------------------------------------------------------*/
+/* spillThis - spils a specific operand                            */
+/*-----------------------------------------------------------------*/
+void
+spillThis (symbol * sym)
+{
+  int i;
+  /* if this is rematerializable or has a spillLocation
+     we are okay, else we need to create a spillLocation
+     for it */
+  if (!(sym->remat || sym->usl.spillLoc))
+    createStackSpil (sym);
+
+  /* mark it as spilt & put it in the spilt set */
+  sym->isspilt = sym->spillA = 1;
+  _G.spiltSet = bitVectSetBit (_G.spiltSet, sym->key);
+
+  bitVectUnSetBit (_G.regAssigned, sym->key);
+  bitVectUnSetBit (_G.totRegAssigned, sym->key);
+
+  for (i = 0; i < sym->nRegs; i++)
+    {
+      if (sym->regs[i])
+        {
+          m6502_freeReg (sym->regs[i]);
+          sym->regs[i] = NULL;
+        }
+    }
+
+  if (sym->usl.spillLoc && !sym->remat)
+    sym->usl.spillLoc->allocreq++;
+  return;
+}
+
+/*-----------------------------------------------------------------*/
+/* updateRegUsage -  update the registers in use at the start of   */
+/*                   this icode                                    */
+/*-----------------------------------------------------------------*/
+static void
+updateRegUsage (iCode * ic)
+{
+  int reg;
+
+  // update the registers in use at the start of this icode
+  for (reg=0; regriu &= ~(regsm6502[reg].mask);
+        }
+      else
+        {
+          ic->riu |= (regsm6502[reg].mask);
+        }
+    }
+}
+
+/*-----------------------------------------------------------------*/
+/* deassignLRs - check the live to and if they have registers &    */
+/*               are not spilt then free up the registers          */
+/*-----------------------------------------------------------------*/
+static void
+deassignLRs (iCode * ic, eBBlock * ebp)
+{
+  symbol *sym;
+  int k;
+
+  for (sym = hTabFirstItem (liveRanges, &k); sym;
+       sym = hTabNextItem (liveRanges, &k))
+    {
+      /* if it does not end here */
+      if (sym->liveTo > ic->seq)
+        continue;
+
+      /* if it was spilt on stack then we can
+         mark the stack spil location as free */
+      if (sym->isspilt)
+        {
+          if (sym->stackSpil)
+            {
+              sym->usl.spillLoc->isFree = 1;
+              sym->stackSpil = 0;
+            }
+          continue;
+        }
+    }
+}
+
+
+/*-----------------------------------------------------------------*/
+/* reassignLR - reassign this to registers                         */
+/*-----------------------------------------------------------------*/
+static void
+reassignLR (operand * op)
+{
+  symbol *sym = OP_SYMBOL (op);
+  int i;
+
+  /* not spilt any more */
+  sym->isspilt = sym->spillA = sym->blockSpil = sym->remainSpil = 0;
+  bitVectUnSetBit (_G.spiltSet, sym->key);
+
+  _G.regAssigned = bitVectSetBit (_G.regAssigned, sym->key);
+  _G.totRegAssigned = bitVectSetBit (_G.totRegAssigned, sym->key);
+
+  _G.blockSpil--;
+
+  for (i = 0; i < sym->nRegs; i++)
+    sym->regs[i]->isFree = 0;
+}
+
+/*------------------------------------------------------------------*/
+/* verifyRegsAssigned - make sure an iTemp is properly initialized; */
+/* it should either have registers or have beed spilled. Otherwise, */
+/* there was an uninitialized variable, so just spill this to get   */
+/* the operand in a valid state.                                    */
+/*------------------------------------------------------------------*/
+static void
+verifyRegsAssigned (operand *op, iCode * ic)
+{
+  symbol * sym;
+
+  if (!op) return;
+  if (!IS_ITEMP (op)) return;
+
+  sym = OP_SYMBOL (op);
+  if (sym->isspilt) return;
+  if (!sym->nRegs) return;
+  if (sym->regs[0]) return;
+
+  spillThis (sym);
+}
+
+/*-----------------------------------------------------------------*/
+/* rUmaskForOp :- returns register mask for an operand             */
+/*-----------------------------------------------------------------*/
+bitVect *
+m6502_rUmaskForOp (operand * op)
+{
+  bitVect *rumask;
+  symbol *sym;
+  int j;
+
+  /* only temporaries are assigned registers */
+  if (!IS_ITEMP (op))
+    return NULL;
+
+  sym = OP_SYMBOL (op);
+
+  /* if spilt or no registers assigned to it
+     then nothing */
+  if (sym->isspilt || !sym->nRegs)
+    return NULL;
+
+  rumask = newBitVect (m6502_nRegs);
+
+  for (j = 0; j < sym->nRegs; j++)
+    {
+      rumask = bitVectSetBit (rumask, sym->regs[j]->rIdx);
+    }
+
+  return rumask;
+}
+
+/*-----------------------------------------------------------------*/
+/* regTypeNum - computes the type & number of registers required   */
+/*-----------------------------------------------------------------*/
+static void
+regTypeNum (void)
+{
+  symbol *sym;
+  int k;
+
+  /* for each live range do */
+  for (sym = hTabFirstItem (liveRanges, &k); sym; sym = hTabNextItem (liveRanges, &k))
+    {
+      /* if used zero times then no registers needed */
+      if ((sym->liveTo - sym->liveFrom) == 0)
+        continue;
+
+      D (D_ALLOC, ("regTypeNum: loop on sym %p\n", sym));
+
+      /* if the live range is a temporary */
+      if (sym->isitmp)
+        {
+          /* if the type is marked as a conditional */
+          if (sym->regType == REG_CND)
+            continue;
+
+          /* if used in return only then we don't
+             need registers */
+          if (sym->ruonly || sym->accuse)
+            {
+              if (IS_AGGREGATE (sym->type) || sym->isptr)
+                sym->type = aggrToPtr (sym->type, false);
+              continue;
+            }
+
+          /* if not then we require registers */
+          D (D_ALLOC,
+             ("regTypeNum: isagg %u nRegs %u type %p\n", IS_AGGREGATE (sym->type) || sym->isptr, sym->nRegs, sym->type));
+          sym->nRegs = ((IS_AGGREGATE (sym->type)
+                         || sym->isptr) ? getSize (sym->type = aggrToPtr (sym->type, false)) : getSize (sym->type));
+          D (D_ALLOC, ("regTypeNum: setting nRegs of %s (%p) to %u\n", sym->name, sym, sym->nRegs));
+
+          D (D_ALLOC, ("regTypeNum: setup to assign regs sym %p\n", sym));
+
+          if (sym->nRegs > 8)
+            {
+              fprintf (stderr, "allocated more than 8 registers for type ");
+              printTypeChain (sym->type, stderr);
+              fprintf (stderr, "\n");
+            }
+
+          /* determine the type of register required */
+          if (sym->nRegs == 1 && IS_PTR (sym->type) && sym->uptr)
+            sym->regType = REG_PTR;
+          else
+            sym->regType = REG_GPR;
+        }
+      else
+        {
+          /* for the first run we don't provide */
+          /* registers for true symbols we will */
+          /* see how things go                  */
+          D (D_ALLOC, ("regTypeNum: #2 setting num of %p to 0\n", sym));
+          sym->nRegs = 0;
+        }
+    }
+}
+
+/*-----------------------------------------------------------------*/
+/* freeAllRegs - mark all registers as free                        */
+/*-----------------------------------------------------------------*/
+static void
+freeAllRegs ()
+{
+  int i;
+
+  for (i = 0; i < m6502_nRegs; i++)
+    {
+      regsm6502[i].isFree = 1;
+      regsm6502[i].aop = NULL;
+    }
+}
+
+/*-----------------------------------------------------------------*/
+/* deallocStackSpil - this will set the stack pointer back         */
+/*-----------------------------------------------------------------*/
+static
+DEFSETFUNC (deallocStackSpil)
+{
+  symbol *sym = item;
+
+  deallocLocal (sym);
+  return 0;
+}
+
+#if 0
+/** Transform weird SDCC handling of writes via pointers
+    into something more sensible. */
+static void
+transformPointerSet (eBBlock **ebbs, int count)
+{
+  /* for all blocks */
+  for (int i = 0; i < count; i++)
+    {
+      iCode *ic;
+
+      /* for all instructions do */
+      for (ic = ebbs[i]->sch; ic; ic = ic->next)
+        if (POINTER_SET (ic))
+          {
+            IC_LEFT (ic) = IC_RESULT (ic);
+            IC_RESULT (ic) = 0;
+            ic->op = SET_VALUE_AT_ADDRESS;
+          }
+    }
+}
+#endif
+
+/*-----------------------------------------------------------------*/
+/* packRegsForAssign - register reduction for assignment           */
+/*-----------------------------------------------------------------*/
+static int
+packRegsForAssign (iCode * ic, eBBlock * ebp)
+{
+  iCode *dic, *sic;
+
+  if (!IS_ITEMP (IC_RIGHT (ic))
+      || OP_SYMBOL (IC_RIGHT (ic))->isind
+      || OP_LIVETO (IC_RIGHT (ic)) > ic->seq)
+    {
+      return 0;
+    }
+
+  /* if the true symbol is defined in far space or on stack
+     then we should not since this will increase register pressure */
+#if 0
+  if (isOperandInFarSpace(IC_RESULT(ic)) && !farSpacePackable(ic))
+    {
+      return 0;
+    }
+#endif
+
+  /* find the definition of iTempNN scanning backwards if we find
+     a use of the true symbol before we find the definition then
+     we cannot */
+  for (dic = ic->prev; dic; dic = dic->prev)
+    {
+      int crossedCall = 0;
+
+      /* We can pack across a function call only if it's a local */
+      /* variable or our parameter. Never pack global variables */
+      /* or parameters to a function we call. */
+      if ((dic->op == CALL || dic->op == PCALL))
+        {
+          if (!OP_SYMBOL (IC_RESULT (ic))->ismyparm
+              && !OP_SYMBOL (IC_RESULT (ic))->islocal)
+            {
+              crossedCall = 1;
+            }
+        }
+
+      /* Don't move an assignment out of a critical block */
+      if (dic->op == CRITICAL)
+        {
+          dic = NULL;
+          break;
+        }
+
+      if (SKIP_IC2 (dic))
+        continue;
+
+      if (dic->op == IFX)
+        {
+          if (IS_SYMOP (IC_COND (dic))
+              && (IC_COND (dic)->key == IC_RESULT (ic)->key
+                  || IC_COND (dic)->key == IC_RIGHT (ic)->key))
+            {
+              dic = NULL;
+              break;
+            }
+        }
+      else
+        {
+          if (IS_TRUE_SYMOP (IC_RESULT (dic))
+              && IS_OP_VOLATILE (IC_RESULT (dic)))
+            {
+              dic = NULL;
+              break;
+            }
+
+          if (IS_SYMOP (IC_RESULT (dic))
+              && IC_RESULT (dic)->key == IC_RIGHT (ic)->key)
+            {
+              if (POINTER_SET (dic))
+                dic = NULL;
+              break;
+            }
+
+          if (IS_SYMOP (IC_RIGHT (dic))
+              && (IC_RIGHT (dic)->key == IC_RESULT (ic)->key
+                  || IC_RIGHT (dic)->key == IC_RIGHT (ic)->key))
+            {
+              dic = NULL;
+              break;
+            }
+
+          if (IS_SYMOP (IC_LEFT (dic))
+              && (IC_LEFT (dic)->key == IC_RESULT (ic)->key
+                  || IC_LEFT (dic)->key == IC_RIGHT (ic)->key))
+            {
+              dic = NULL;
+              break;
+            }
+
+          if (POINTER_SET (dic) &&
+              IC_RESULT (dic)->key == IC_RESULT (ic)->key)
+            {
+              dic = NULL;
+              break;
+            }
+
+          if (crossedCall)
+            {
+              dic = NULL;
+              break;
+            }
+        }
+    }
+
+  if (!dic)
+    return 0;                   /* did not find */
+
+  /* if assignment then check that right is not a bit */
+  if (ASSIGNMENT (ic) && !POINTER_SET (ic))
+    {
+      sym_link *etype = operandType (IC_RESULT (dic));
+      if (IS_BITFIELD (etype))
+        {
+          /* if result is a bit too then it's ok */
+          etype = operandType (IC_RESULT (ic));
+          if (!IS_BITFIELD (etype))
+            {
+              return 0;
+            }
+        }
+    }
+
+  /* found the definition */
+
+  /* delete from liverange table also
+     delete from all the points inbetween and the new
+     one */
+  for (sic = dic; sic != ic; sic = sic->next)
+    {
+      bitVectUnSetBit (sic->rlive, IC_RESULT (ic)->key);
+      if (IS_ITEMP (IC_RESULT (dic)))
+        bitVectSetBit (sic->rlive, IC_RESULT (dic)->key);
+    }
+
+  /* replace the result with the result of */
+  /* this assignment and remove this assignment */
+  bitVectUnSetBit (OP_SYMBOL (IC_RESULT (dic))->defs, dic->key);
+  ReplaceOpWithCheaperOp (&IC_RESULT (dic), IC_RESULT (ic));
+
+  if (IS_ITEMP (IC_RESULT (dic)) && OP_SYMBOL (IC_RESULT (dic))->liveFrom > dic->seq)
+    {
+      OP_SYMBOL (IC_RESULT (dic))->liveFrom = dic->seq;
+    }
+  // TODO: and the otherway around?
+
+  remiCodeFromeBBlock (ebp, ic);
+  bitVectUnSetBit (OP_DEFS (IC_RESULT (ic)), ic->key);
+  hTabDeleteItem (&iCodehTab, ic->key, ic, DELETE_ITEM, NULL);
+  OP_DEFS (IC_RESULT (dic)) = bitVectSetBit (OP_DEFS (IC_RESULT (dic)), dic->key);
+  return 1;
+}
+
+/*------------------------------------------------------------------*/
+/* findAssignToSym : scanning backwards looks for first assig found */
+/*------------------------------------------------------------------*/
+static iCode *
+findAssignToSym (operand * op, iCode * ic)
+{
+  iCode *dic;
+
+  /* This routine is used to find sequences like
+     iTempAA = FOO;
+     ...;  (intervening ops don't use iTempAA or modify FOO)
+     blah = blah + iTempAA;
+
+     and eliminate the use of iTempAA, freeing up its register for
+     other uses.
+  */
+  for (dic = ic->prev; dic; dic = dic->prev)
+    {
+      if (dic->op == '=' &&
+          !POINTER_SET (dic) &&
+          IC_RESULT (dic)->key == op->key
+          &&  IS_TRUE_SYMOP(IC_RIGHT(dic))
+        )
+        break;  /* found where this temp was defined */
+
+      /* if we find an usage then we cannot delete it */
+      if (IC_LEFT (dic) && IC_LEFT (dic)->key == op->key)
+        return NULL;
+
+      if (IC_RIGHT (dic) && IC_RIGHT (dic)->key == op->key)
+        return NULL;
+
+      if (POINTER_SET (dic) && IC_RESULT (dic)->key == op->key)
+        return NULL;
+    }
+
+  if (!dic)
+    return NULL;   /* didn't find any assignment to op */
+  /* we are interested only if defined in far space */
+  /* or in stack space in case of + & - */
+
+  /* if assigned to a non-symbol then don't repack regs */
+  if (!IS_SYMOP (IC_RIGHT (dic)))
+    return NULL;
+
+  /* if the symbol's address has been taken, there might be a */
+  /* non-obvious assignment to it, and so we should not */
+  if (OP_SYMBOL (IC_RIGHT (dic))->addrtaken)
+    return NULL;
+
+  /* if the symbol is volatile then we should not */
+  if (isOperandVolatile (IC_RIGHT (dic), true))
+    return NULL;
+  /* XXX TODO --- should we be passing false to isOperandVolatile()?
+     What does it mean for an iTemp to be volatile, anyway? Passing
+     true is more cautious but may prevent possible optimizations */
+
+  /* if the symbol is in far space then we should not */
+  /* if (isOperandInFarSpace (IC_RIGHT (dic)))
+    return NULL; */
+
+
+  /* now make sure that the right side of dic
+     is not defined between ic & dic */
+  if (dic)
+    {
+      iCode *sic = dic->next;
+
+      for (; sic != ic; sic = sic->next)
+        if (IC_RESULT (sic) &&
+            IC_RESULT (sic)->key == IC_RIGHT (dic)->key)
+          return NULL;
+    }
+
+  return dic;
+}
+
+/*-----------------------------------------------------------------*/
+/* reassignAliasedSym - used by packRegsForSupport to replace      */
+/*                      redundant iTemp with equivalent symbol     */
+/*-----------------------------------------------------------------*/
+static void
+reassignAliasedSym (eBBlock *ebp, iCode *assignment, iCode *use, operand *op)
+{
+  iCode *ic;
+  unsigned oldSymKey, newSymKey;
+
+  oldSymKey = op->key;
+  newSymKey = IC_RIGHT(assignment)->key;
+
+  /* only track live ranges of compiler-generated temporaries */
+  if (!IS_ITEMP(IC_RIGHT(assignment)))
+    newSymKey = 0;
+
+  /* update the live-value bitmaps */
+  for (ic = assignment; ic != use; ic = ic->next) {
+    bitVectUnSetBit (ic->rlive, oldSymKey);
+    if (newSymKey != 0)
+      ic->rlive = bitVectSetBit (ic->rlive, newSymKey);
+  }
+
+  /* update the sym of the used operand */
+  OP_SYMBOL(op) = OP_SYMBOL(IC_RIGHT(assignment));
+  op->key = OP_SYMBOL(op)->key;
+
+  /* update the sym's liverange */
+  if ( OP_LIVETO(op) < ic->seq )
+    setToRange(op, ic->seq, false);
+
+  /* remove the assignment iCode now that its result is unused */
+  remiCodeFromeBBlock (ebp, assignment);
+  bitVectUnSetBit(OP_SYMBOL(IC_RESULT(assignment))->defs, assignment->key);
+  hTabDeleteItem (&iCodehTab, assignment->key, assignment, DELETE_ITEM, NULL);
+}
+
+
+/*-----------------------------------------------------------------*/
+/* packRegsForSupport :- reduce some registers for support calls   */
+/*-----------------------------------------------------------------*/
+static int
+packRegsForSupport (iCode * ic, eBBlock * ebp)
+{
+  iCode *dic;
+  int changes = 0;
+
+  /* for the left & right operand :- look to see if the
+     left was assigned a true symbol in far space in that
+     case replace them */
+
+  if (IS_ITEMP (IC_LEFT (ic)) &&
+      OP_SYMBOL (IC_LEFT (ic))->liveTo <= ic->seq)
+    {
+      dic = findAssignToSym (IC_LEFT (ic), ic);
+
+      if (dic)
+        {
+          /* found it we need to remove it from the block */
+          reassignAliasedSym (ebp, dic, ic, IC_LEFT(ic));
+          changes++;
+        }
+    }
+
+  /* do the same for the right operand */
+  if (IS_ITEMP (IC_RIGHT (ic)) &&
+      OP_SYMBOL (IC_RIGHT (ic))->liveTo <= ic->seq)
+    {
+      iCode *dic = findAssignToSym (IC_RIGHT (ic), ic);
+
+      if (dic)
+        {
+          /* found it we need to remove it from the block */
+          reassignAliasedSym (ebp, dic, ic, IC_RIGHT(ic));
+          changes++;
+        }
+    }
+
+  return changes;
+}
+
+/*-----------------------------------------------------------------*/
+/* isBitwiseOptimizable - requirements of JEAN LOUIS VERN          */
+/*-----------------------------------------------------------------*/
+static bool
+isBitwiseOptimizable (iCode * ic)
+{
+  sym_link *ltype = getSpec (operandType (IC_LEFT (ic)));
+  sym_link *rtype = getSpec (operandType (IC_RIGHT (ic)));
+
+  /* bitwise operations are considered optimizable
+     under the following conditions (Jean-Louis VERN)
+
+     x & lit
+     bit & bit
+     bit & x
+     bit ^ bit
+     bit ^ x
+     x   ^ lit
+     x   | lit
+     bit | bit
+     bit | x
+  */
+  if (IS_LITERAL(rtype) ||
+      (IS_BITVAR (ltype) && IN_BITSPACE (SPEC_OCLS (ltype))))
+    return true;
+  else
+    return false;
+}
+
+
+/*-----------------------------------------------------------------*/
+/* packForPush - heuristics to reduce iCode for pushing            */
+/*-----------------------------------------------------------------*/
+static void
+packForPush (iCode * ic, eBBlock ** ebpp, int count)
+{
+  iCode *dic, *lic;
+  bitVect *dbv;
+  int disallowHiddenAssignment = 0;
+  eBBlock * ebp = ebpp[ic->eBBlockNum];
+
+  if ((ic->op != IPUSH && ic->op != SEND) || !IS_ITEMP (IC_LEFT (ic)))
+    return;
+
+  /* must have only definition & one usage */
+  if (bitVectnBitsOn (OP_DEFS (IC_LEFT (ic))) != 1 ||
+      bitVectnBitsOn (OP_USES (IC_LEFT (ic))) != 1)
+    return;
+
+  /* find the definition */
+  if (!(dic = hTabItemWithKey (iCodehTab,
+                               bitVectFirstBit (OP_DEFS (IC_LEFT (ic))))))
+    return;
+
+  if (dic->op != '=' || POINTER_SET (dic))
+    return;
+
+  if (dic->seq < ebp->fSeq || dic->seq > ebp->lSeq) // Evelyn did this
+    {
+      int i;
+      for (i=0; iseq >= ebpp[i]->fSeq && dic->seq <= ebpp[i]->lSeq)
+            {
+              ebp=ebpp[i];
+              break;
+            }
+        }
+      if (i==count) // Abort if we can't find the definition's block
+        return;
+    }
+
+  if (IS_SYMOP(IC_RIGHT(dic)))
+    {
+      if (IC_RIGHT (dic)->isvolatile)
+        return;
+
+      if (OP_SYMBOL (IC_RIGHT (dic))->addrtaken || isOperandGlobal (IC_RIGHT (dic)))
+        disallowHiddenAssignment = 1;
+
+      /* make sure the right side does not have any definitions
+         inbetween */
+      dbv = OP_DEFS(IC_RIGHT(dic));
+      for (lic = ic; lic && lic != dic ; lic = lic->prev)
+        {
+          if (bitVectBitValue(dbv,lic->key))
+            return ;
+          if (disallowHiddenAssignment && (lic->op == CALL || lic->op == PCALL || POINTER_SET (lic)))
+            return;
+        }
+      /* make sure they have the same type */
+      if (IS_SPEC(operandType(IC_LEFT(ic))))
+        {
+          sym_link *itype=operandType(IC_LEFT(ic));
+          sym_link *ditype=operandType(IC_RIGHT(dic));
+
+          if (SPEC_USIGN(itype)!=SPEC_USIGN(ditype) ||
+              SPEC_LONG(itype)!=SPEC_LONG(ditype))
+            return;
+        }
+      /* extend the live range of replaced operand if needed */
+      if (OP_SYMBOL(IC_RIGHT(dic))->liveTo < ic->seq)
+        {
+          OP_SYMBOL(IC_RIGHT(dic))->liveTo = ic->seq;
+        }
+      bitVectUnSetBit(OP_SYMBOL(IC_RESULT(dic))->defs,dic->key);
+    }
+  if (IS_ITEMP (IC_RIGHT (dic)))
+    OP_USES (IC_RIGHT (dic)) = bitVectSetBit (OP_USES (IC_RIGHT (dic)), ic->key);
+
+  /* we now we know that it has one & only one def & use
+     and the that the definition is an assignment */
+  ReplaceOpWithCheaperOp(&IC_LEFT (ic), IC_RIGHT (dic));
+  remiCodeFromeBBlock (ebp, dic);
+  hTabDeleteItem (&iCodehTab, dic->key, dic, DELETE_ITEM, NULL);
+}
+
+/*------------------------------------------------------------------*/
+/* moveSendToCall - move SEND to immediately precede its CALL/PCALL */
+/*------------------------------------------------------------------*/
+static iCode *
+moveSendToCall (iCode *sic, eBBlock *ebp)
+{
+  iCode * prev = sic->prev;
+  iCode * sic2 = NULL;
+  iCode * cic;
+  
+  /* Go find the CALL/PCALL */
+  cic = sic;
+  while (cic && cic->op != CALL && cic->op != PCALL)
+    cic = cic->next;
+  if (!cic)
+    return sic;
+
+  /* Is there a second SEND? If so, we'll need to move it too. */
+  if (sic->next->op == SEND)
+    sic2 = sic->next;
+  
+  /* relocate the SEND(s) */
+  remiCodeFromeBBlock (ebp, sic);
+  addiCodeToeBBlock (ebp, sic, cic);
+  if (sic2)
+    {
+      remiCodeFromeBBlock (ebp, sic2);
+      addiCodeToeBBlock (ebp, sic2, cic);
+    }
+
+  /* Return the iCode to continue processing at. */
+  if (prev)
+    return prev->next;
+  else
+    return ebp->sch;
+}
+
+
+/*---------------------------------------------------------------------*/
+/* packPointerOp - see if we can move an offset from addition iCode    */
+/*                 to the pointer iCode to used indexed addr mode      */
+/* The z80-related ports do a similar thing in SDCCopt.c, offsetFold() */
+/*---------------------------------------------------------------------*/
+static void
+packPointerOp (iCode * ic, eBBlock ** ebpp)
+{
+  operand * pointer;
+  operand * offsetOp;
+  operand * nonOffsetOp;
+  iCode * dic;
+  iCode * uic;
+  int key;
+
+  if (POINTER_SET (ic))
+    {
+      pointer = IC_RESULT (ic);
+      offsetOp = IC_LEFT (ic);
+    }
+  else if (POINTER_GET (ic))
+    {
+      pointer = IC_LEFT (ic);
+      offsetOp = IC_RIGHT (ic);
+    }
+  else
+    return;
+
+  if (!IS_ITEMP (pointer))
+    return;
+
+  /* If the pointer is rematerializable, it's already fully optimized */
+  if (OP_SYMBOL (pointer)->remat)
+    return;
+
+  if (offsetOp && IS_OP_LITERAL (offsetOp) && operandLitValue (offsetOp) != 0)
+    return;
+  if (offsetOp && IS_SYMOP (offsetOp))
+    return;
+
+  /* There must be only one definition */
+  if (bitVectnBitsOn (OP_DEFS (pointer)) != 1)
+    return;
+  /* find the definition */
+  if (!(dic = hTabItemWithKey (iCodehTab, bitVectFirstBit (OP_DEFS (pointer)))))
+    return;
+
+  if (dic->op == '+' && (IS_OP_LITERAL (IC_RIGHT (dic)) ||
+                        (IS_ITEMP (IC_RIGHT (dic)) && OP_SYMBOL (IC_RIGHT (dic))->remat)))
+    {
+      nonOffsetOp = IC_LEFT (dic);
+      offsetOp = IC_RIGHT (dic);
+    }
+  else if (dic->op == '+' && IS_ITEMP (IC_LEFT (dic)) && OP_SYMBOL (IC_LEFT (dic))->remat)
+    {
+      nonOffsetOp = IC_RIGHT (dic);
+      offsetOp = IC_LEFT (dic);
+    }
+  else
+    return;
+
+
+  /* Now check all of the uses to make sure they are all get/set pointer */
+  /* and don't already have a non-zero offset operand */
+  for (key=0; keysize; key++)
+    {
+      if (bitVectBitValue (OP_USES (pointer), key))
+        {
+          uic = hTabItemWithKey (iCodehTab, key);
+          if (POINTER_GET (uic))
+            {
+              if (IC_RIGHT (uic) && IS_OP_LITERAL (IC_RIGHT (uic)) && operandLitValue (IC_RIGHT (uic)) != 0)
+                return;
+              if (IC_RIGHT (uic) && IS_SYMOP (IC_RIGHT (uic)))
+                return;
+            }
+          else if (POINTER_SET (uic))
+            {
+              if (IC_LEFT (uic) && IS_OP_LITERAL (IC_LEFT (uic)) && operandLitValue (IC_LEFT (uic)) != 0)
+                return;
+              if (IC_LEFT (uic) && IS_SYMOP (IC_LEFT (uic)))
+                return;
+            }
+          else
+            return;
+        }
+    }
+
+  /* Everything checks out. Move the literal or rematerializable offset */
+  /* to the pointer get/set iCodes */
+  for (key=0; keysize; key++)
+    {
+      if (bitVectBitValue (OP_USES (pointer), key))
+        {
+          uic = hTabItemWithKey (iCodehTab, key);
+          if (POINTER_GET (uic))
+            {
+              IC_RIGHT (uic) = offsetOp;
+              if (IS_SYMOP (offsetOp))
+                OP_USES (offsetOp) = bitVectSetBit (OP_USES (offsetOp), key);
+            }
+          else if (POINTER_SET (uic))
+            {
+              IC_LEFT (uic) = offsetOp;
+              if (IS_SYMOP (offsetOp))
+                OP_USES (offsetOp) = bitVectSetBit (OP_USES (offsetOp), key);
+            }
+          else
+            return;
+        }
+    }
+
+  /* Put the remaining operand on the right and convert to assignment     */
+  if (IS_SYMOP (offsetOp))
+    bitVectUnSetBit (OP_USES (offsetOp), dic->key);
+  IC_RIGHT (dic) = nonOffsetOp;
+  IC_LEFT (dic) = NULL;
+  SET_ISADDR (IC_RESULT (dic), 0);
+  dic->op = '=';
+}
+
+/*-----------------------------------------------------------------*/
+/* packRegisters - does some transformations to reduce register    */
+/*                 pressure                                        */
+/*-----------------------------------------------------------------*/
+static void
+packRegisters (eBBlock ** ebpp, int count)
+{
+  iCode *ic;
+  int change = 0;
+  int blockno;
+
+  for (blockno=0; blocknosch; ic; ic = ic->next)
+        {
+          /* find assignment of the form TrueSym := iTempNN:1 */
+          if (ic->op == '=' && !POINTER_SET (ic))
+            change += packRegsForAssign (ic, ebp);
+        }
+    }
+  while (change);
+
+  for (ic = ebp->sch; ic; ic = ic->next)
+    {
+      //packRegsForLiteral (ic);
+      
+      /* move SEND to immediately precede its CALL/PCALL */
+      if (ic->op == SEND && ic->next &&
+          ic->next->op != CALL && ic->next->op != PCALL)
+        {
+          ic = moveSendToCall (ic, ebp);
+        }
+      
+      /* if this is an itemp & result of an address of a true sym
+         then mark this as rematerialisable   */
+      if (ic->op == ADDRESS_OF &&
+          IS_ITEMP (IC_RESULT (ic)) &&
+          IS_TRUE_SYMOP (IC_LEFT (ic)) &&
+          bitVectnBitsOn (OP_DEFS (IC_RESULT (ic))) == 1 &&
+          !OP_SYMBOL (IC_LEFT (ic))->onStack)
+        {
+          OP_SYMBOL (IC_RESULT (ic))->remat = 1;
+          OP_SYMBOL (IC_RESULT (ic))->rematiCode = ic;
+          OP_SYMBOL (IC_RESULT (ic))->usl.spillLoc = NULL;
+        }
+
+      /* Safe: just propagates the remat flag */
+      /* if straight assignment then carry remat flag if this is the
+         only definition */
+      if (ic->op == '=' &&
+          !POINTER_SET (ic) &&
+          IS_SYMOP (IC_RIGHT (ic)) &&
+          OP_SYMBOL (IC_RIGHT (ic))->remat &&
+          bitVectnBitsOn (OP_SYMBOL (IC_RESULT (ic))->defs) <= 1 &&
+          !OP_SYMBOL (IC_RESULT (ic))->_isparm &&
+          !OP_SYMBOL (IC_RESULT (ic))->addrtaken &&
+          !isOperandGlobal (IC_RESULT (ic)))
+        {
+          OP_SYMBOL (IC_RESULT (ic))->remat = OP_SYMBOL (IC_RIGHT (ic))->remat;
+          OP_SYMBOL (IC_RESULT (ic))->rematiCode = OP_SYMBOL (IC_RIGHT (ic))->rematiCode;
+        }
+
+      /* if cast to a pointer & the pointer being
+         cast is remat, then we can remat this cast as well */
+      if (ic->op == CAST &&
+          IS_SYMOP(IC_RIGHT(ic)) &&
+          OP_SYMBOL(IC_RIGHT(ic))->remat &&
+          bitVectnBitsOn (OP_DEFS (IC_RESULT (ic))) == 1 &&
+          !OP_SYMBOL (IC_RESULT (ic))->_isparm &&
+          !OP_SYMBOL (IC_RESULT (ic))->addrtaken &&
+          !isOperandGlobal (IC_RESULT (ic)))
+        {
+          sym_link *to_type = operandType(IC_LEFT(ic));
+          sym_link *from_type = operandType(IC_RIGHT(ic));
+          if (IS_PTR(to_type) && IS_PTR(from_type))
+            {
+              OP_SYMBOL (IC_RESULT (ic))->remat = 1;
+              OP_SYMBOL (IC_RESULT (ic))->rematiCode = ic;
+              OP_SYMBOL (IC_RESULT (ic))->usl.spillLoc = NULL;
+            }
+        }
+
+      /* if this is a +/- operation with a rematerializable
+         then mark this as rematerializable as well */
+      if ((ic->op == '+' || ic->op == '-') &&
+          (IS_SYMOP (IC_LEFT (ic)) &&
+           IS_ITEMP (IC_RESULT (ic)) &&
+           IS_OP_LITERAL (IC_RIGHT (ic))) &&
+           OP_SYMBOL (IC_LEFT (ic))->remat &&
+          (!IS_SYMOP (IC_RIGHT (ic)) || !IS_CAST_ICODE(OP_SYMBOL (IC_RIGHT (ic))->rematiCode)) &&
+           bitVectnBitsOn (OP_DEFS (IC_RESULT (ic))) == 1)
+        {
+          OP_SYMBOL (IC_RESULT (ic))->remat = 1;
+          OP_SYMBOL (IC_RESULT (ic))->rematiCode = ic;
+          OP_SYMBOL (IC_RESULT (ic))->usl.spillLoc = NULL;
+        }
+      /* mark the pointer usages */
+      if (POINTER_SET (ic) && IS_SYMOP (IC_RESULT (ic)))
+        OP_SYMBOL (IC_RESULT (ic))->uptr = 1;
+
+      if (POINTER_GET (ic) && IS_SYMOP (IC_LEFT (ic)))
+        OP_SYMBOL (IC_LEFT (ic))->uptr = 1;
+
+      /* reduce for support function calls */
+      if (ic->supportRtn || (ic->op != IFX && ic->op != JUMPTABLE))
+        packRegsForSupport (ic, ebp);
+
+      /* if the condition of an if instruction
+         is defined in the previous instruction and
+         this is the only usage then
+         mark the itemp as a conditional */
+      if ((IS_CONDITIONAL (ic) ||
+           (IS_BITWISE_OP(ic) && isBitwiseOptimizable (ic))) &&
+          ic->next && ic->next->op == IFX &&
+          bitVectnBitsOn (OP_USES(IC_RESULT(ic)))==1 &&
+          isOperandEqual (IC_RESULT (ic), IC_COND (ic->next)) &&
+          OP_SYMBOL (IC_RESULT (ic))->liveTo <= ic->next->seq)
+        {
+          OP_SYMBOL (IC_RESULT (ic))->regType = REG_CND;
+          continue;
+        }
+
+      /* pack for PUSH
+         iTempNN := (some variable in farspace) V1
+         push iTempNN ;
+         -------------
+         push V1
+       */
+      if (ic->op == IPUSH || ic->op == SEND)
+        {
+              packForPush (ic, ebpp, count);
+        }
+
+      if (POINTER_SET (ic) || POINTER_GET (ic))
+        packPointerOp (ic, ebpp);
+
+        }
+    }
+}
+
+void
+m6502RegFix (eBBlock ** ebbs, int count)
+{
+  int i;
+
+  /* Check for and fix any problems with uninitialized operands */
+  for (i = 0; i < count; i++)
+    {
+      iCode *ic;
+
+      if (ebbs[i]->noPath && (ebbs[i]->entryLabel != entryLabel && ebbs[i]->entryLabel != returnLabel))
+        continue;
+
+      for (ic = ebbs[i]->sch; ic; ic = ic->next)
+        {
+          deassignLRs (ic, ebbs[i]);
+
+          if (SKIP_IC2 (ic))
+            continue;
+
+          if (ic->op == IFX)
+            {
+              verifyRegsAssigned (IC_COND (ic), ic);
+              continue;
+            }
+
+          if (ic->op == JUMPTABLE)
+            {
+              verifyRegsAssigned (IC_JTCOND (ic), ic);
+              continue;
+            }
+
+          verifyRegsAssigned (IC_RESULT (ic), ic);
+          verifyRegsAssigned (IC_LEFT (ic), ic);
+          verifyRegsAssigned (IC_RIGHT (ic), ic);
+        }
+    }
+}
+
+/**
+  Mark variables for assignment by the register allocator.
+ */
+static void
+serialRegMark (eBBlock ** ebbs, int count)
+{
+  int i;
+  short int max_alloc_bytes = SHRT_MAX; // Byte limit. Set this to a low value to pass only few variables to the register allocator. This can be useful for debugging.
+
+  D (D_ALLOC, ("serialRegMark for %s, currFunc->stack %d\n", currFunc->name, currFunc->stack));
+
+  /* for all blocks */
+  for (i = 0; i < count; i++)
+    {
+      iCode *ic;
+
+      if (ebbs[i]->noPath
+          && (ebbs[i]->entryLabel != entryLabel
+              && ebbs[i]->entryLabel != returnLabel))
+        continue;
+
+      /* for all instructions do */
+      for (ic = ebbs[i]->sch; ic; ic = ic->next)
+        {
+          updateRegUsage(ic);
+
+          /* if this is an ipop that means some live
+             range will have to be assigned again */
+          if (ic->op == IPOP)
+              reassignLR (IC_LEFT (ic));
+
+          /* if result is present && is a true symbol */
+          if (IC_RESULT (ic) && ic->op != IFX &&
+              IS_TRUE_SYMOP (IC_RESULT (ic)))
+            {
+              OP_SYMBOL (IC_RESULT (ic))->allocreq++;
+            }
+
+          /* take away registers from live
+             ranges that end at this instruction */
+          deassignLRs (ic, ebbs[i]);
+
+          /* some don't need registers */
+          if (SKIP_IC2 (ic) ||
+              ic->op == JUMPTABLE ||
+              ic->op == IFX ||
+              ic->op == IPUSH ||
+              ic->op == IPOP ||
+              (IC_RESULT (ic) && POINTER_SET (ic)))
+              continue;
+
+          /* now we need to allocate registers only for the result */
+          if (IC_RESULT (ic))
+            {
+              symbol *sym = OP_SYMBOL (IC_RESULT (ic));
+
+              /* Make sure any spill location is definitely allocated */
+              if (sym->isspilt && !sym->remat && sym->usl.spillLoc &&
+                  !sym->usl.spillLoc->allocreq)
+                {
+                  sym->usl.spillLoc->allocreq++;
+                }
+
+              /* if it does not need or is spilt
+                 or is already assigned to registers
+                 or will not live beyond this instructions */
+              if (!sym->nRegs ||
+                  sym->isspilt ||
+                  bitVectBitValue (_G.regAssigned, sym->key) ||
+                  sym->liveTo <= ic->seq)
+                {
+                  D (D_ALLOC, ("serialRegMark: won't live long enough.\n"));
+                  continue;
+                }
+
+              /* if some liverange has been spilt at the block level
+                 and this one live beyond this block then spil this
+                 to be safe */
+              if (_G.blockSpil && sym->liveTo > ebbs[i]->lSeq)
+                {
+                  spillThis (sym);
+                  continue;
+                }
+
+              if (sym->remat)
+                {
+                  spillThis (sym);
+                  continue;
+                }
+
+              if (max_alloc_bytes >= sym->nRegs)
+                {
+                  sym->for_newralloc = 1;
+                  max_alloc_bytes -= sym->nRegs;
+                }
+              else if (!sym->for_newralloc)
+                {
+                  spillThis (sym);
+                  printf ("Spilt %s due to byte limit.\n", sym->name);
+                }
+            }
+        }
+    }
+}
+
+/*-----------------------------------------------------------------*/
+/* assignRegisters - assigns registers to each live range as need  */
+/*-----------------------------------------------------------------*/
+void
+m6502_assignRegisters (ebbIndex *ebbi)
+{
+  eBBlock ** ebbs = ebbi->bbOrder;
+  int count = ebbi->count;
+  iCode *ic;
+
+  setToNull ((void *) &_G.funcrUsed);
+  setToNull ((void *) &_G.regAssigned);
+  setToNull ((void *) &_G.totRegAssigned);
+  m6502_ptrRegReq = _G.stackExtend = _G.dataExtend = 0;
+  m6502_nRegs = 7;
+  m6502_reg_a = m6502_regWithIdx(A_IDX);
+  m6502_reg_x = m6502_regWithIdx(X_IDX);
+  m6502_reg_y = m6502_regWithIdx(Y_IDX);
+  m6502_reg_yx = m6502_regWithIdx(YX_IDX);
+  m6502_reg_xa = m6502_regWithIdx(XA_IDX);
+  m6502_reg_sp = m6502_regWithIdx(SP_IDX);
+  m6502_nRegs = 5;
+
+//  transformPointerSet (ebbs, count);
+
+  /* change assignments this will remove some
+     live ranges reducing some register pressure */
+
+  packRegisters (ebbs, count);
+
+  /* liveranges probably changed by register packing
+     so we compute them again */
+  recomputeLiveRanges (ebbs, count, false);
+
+  if (options.dump_i_code)
+    dumpEbbsToFileExt (DUMP_PACK, ebbi);
+
+  /* first determine for each live range the number of
+     registers & the type of registers required for each */
+  regTypeNum ();
+
+  /* Mark variables for assignment by the new allocator */
+  serialRegMark (ebbs, count);
+
+  /* Invoke optimal register allocator */
+  ic = m6502_ralloc2_cc (ebbi);
+
+  /* if stack was extended then tell the user */
+  if (_G.stackExtend)
+    {
+/*      werror(W_TOOMANY_SPILS,"stack", */
+/*             _G.stackExtend,currFunc->name,""); */
+      _G.stackExtend = 0;
+    }
+
+  if (_G.dataExtend)
+    {
+/*      werror(W_TOOMANY_SPILS,"data space", */
+/*             _G.dataExtend,currFunc->name,""); */
+      _G.dataExtend = 0;
+    }
+
+  /* redo that offsets for stacked automatic variables */
+  if (currFunc)
+    {
+      redoStackOffsets ();
+    }
+
+  if (options.dump_i_code)
+    {
+      dumpEbbsToFileExt (DUMP_RASSGN, ebbi);
+      dumpLiveRanges (DUMP_LRANGE, liveRanges);
+    }
+
+  /* now get back the chain */
+  ic = iCodeLabelOptimize (iCodeFromeBBlock (ebbs, count));
+
+  genm6502Code (ic);
+
+  /* free up any _G.stackSpil locations allocated */
+  applyToSet (_G.stackSpil, deallocStackSpil);
+  _G.slocNum = 0;
+  setToNull ((void *) &_G.stackSpil);
+  setToNull ((void *) &_G.spiltSet);
+  /* mark all registers as free */
+  freeAllRegs ();
+
+  return;
+}
+
diff -Nru sdcc-4.0.0+dfsg/src/mos6502/ralloc.h sdcc-4.2.0+dfsg/src/mos6502/ralloc.h
--- sdcc-4.0.0+dfsg/src/mos6502/ralloc.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/mos6502/ralloc.h	2022-02-06 00:37:14.000000000 +0000
@@ -0,0 +1,123 @@
+/*-------------------------------------------------------------------------
+
+  SDCCralloc.h - header file register allocation
+
+                Written By -  Sandeep Dutta . sandeep.dutta@usa.net (1998)
+
+   This program is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published by the
+   Free Software Foundation; either version 2, or (at your option) any
+   later version.
+   
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+   
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+   
+   In other words, you are welcome to use, share and improve this program.
+   You are forbidden to forbid anyone else to use, share and improve
+   what you give them.   Help stamp out software-hoarding!  
+-------------------------------------------------------------------------*/
+
+#ifndef SDCCRALLOC_H
+#define SDCCRALLOC_H 1
+
+#include "common.h"
+
+enum
+  {
+    A_IDX,
+    X_IDX,
+    Y_IDX,
+    YX_IDX,
+    XA_IDX,
+    CND_IDX,
+    SP_IDX
+  };
+
+enum
+{
+  REG_PTR = 1,
+  REG_GPR = 2,
+  REG_CND = 4,
+};
+
+/* Must preserve the relation M6502MASK_Y > M6502MASK_X > M6502MASK_A  */
+/* so that M6502MASK_REV can be automatically applied when reversing */
+/* the usual register pair ordering. */
+#define M6502MASK_A 0x01
+#define M6502MASK_X 0x02
+#define M6502MASK_Y 0x04
+#define M6502MASK_REV 0x80
+#define M6502MASK_XA (M6502MASK_X | M6502MASK_A)
+#define M6502MASK_YX (M6502MASK_Y | M6502MASK_X)
+#define M6502MASK_AX (M6502MASK_REV | M6502MASK_X | M6502MASK_A)
+    
+/* definition for the registers */
+typedef struct reg_info
+  {
+    short type;			/* can have value 
+				   REG_GPR, REG_PTR or REG_CND */
+    short rIdx;			/* index into register table */
+    char *name;			/* name */
+    short mask;			/* bitmask for pair allocation */
+    struct asmop *aop;		/* last operand */
+    int aopofs;			/* last operand offset */
+    unsigned isFree:1;		/* is currently unassigned */
+    unsigned isDead:1;      /* does not need to survive current instruction */
+    unsigned isLitConst:1;      /* has an literal constant loaded */
+    int litConst;		/* last literal constant */
+  }
+reg_info;
+
+#define M6502OP_REG 1
+#define M6502OP_LD  2
+#define M6502OP_ST  3
+#define M6502OP_RMW 4
+#define M6502OP_INH 5
+#define M6502OP_SPH 6
+#define M6502OP_SPL 7
+#define M6502OP_JMP 8
+#define M6502OP_BR  9
+#define M6502OP_BBR 10
+#define M6502OP_IDD 11
+#define M6502OP_IDI 12
+
+/* opcode table */
+typedef struct m6502opcodedata
+  {
+    char name[6];
+    char type;
+    int  dest;
+    unsigned char flags;
+    /* info for registers used and/or modified by an instruction will be added here */
+  }
+m6502opcodedata;
+
+extern reg_info regsm6502[];
+extern reg_info *m6502_reg_a;
+extern reg_info *m6502_reg_x;
+extern reg_info *m6502_reg_y;
+extern reg_info *m6502_reg_yx;
+extern reg_info *m6502_reg_xa;
+extern reg_info *m6502_reg_sp;
+
+reg_info *m6502_regWithIdx (int);
+void m6502_useReg (reg_info * reg);
+void m6502_freeReg (reg_info * reg);
+void m6502_dirtyReg (reg_info * reg);
+bitVect *m6502_rUmaskForOp (operand * op);
+
+const m6502opcodedata *m6502_getOpcodeData(const char *inst);
+int m6502_opcodeSize(const m6502opcodedata *opcode, const char *arg);
+
+iCode *m6502_ralloc2_cc(ebbIndex *ebbi);
+
+void m6502RegFix (eBBlock **ebbs, int count);
+
+#endif
+
diff -Nru sdcc-4.0.0+dfsg/src/pdk/gen.c sdcc-4.2.0+dfsg/src/pdk/gen.c
--- sdcc-4.0.0+dfsg/src/pdk/gen.c	2019-12-09 15:40:45.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/pdk/gen.c	2022-02-03 09:32:48.000000000 +0000
@@ -1,7 +1,7 @@
 /*-------------------------------------------------------------------------
   gen.c - code generator for Padauk.
 
-  Copyright (C) 2018, Philipp Klaus Krause pkk@spth.de
+  Copyright (C) 2018-2021, Philipp Klaus Krause pkk@spth.de
 
   This program is free software; you can redistribute it and/or modify it
   under the terms of the GNU General Public License as published by the
@@ -50,13 +50,14 @@
 }
 G;
 
-static struct asmop asmop_a, asmop_p, asmop_pa, asmop_ap, asmop_zero, asmop_one, asmop_sp;
+static struct asmop asmop_a, asmop_p, asmop_pa, asmop_ap, asmop_zero, asmop_one, asmop_mone, asmop_sp;
 static struct asmop *const ASMOP_A = &asmop_a;
 static struct asmop *const ASMOP_P = &asmop_p;
 static struct asmop *const ASMOP_PA = &asmop_pa;
 static struct asmop *const ASMOP_AP = &asmop_ap;
 static struct asmop *const ASMOP_ZERO = &asmop_zero;
 static struct asmop *const ASMOP_ONE = &asmop_one;
+static struct asmop *const ASMOP_MONE = &asmop_mone;
 static struct asmop *const ASMOP_SP = &asmop_sp;
 
 void
@@ -93,6 +94,10 @@
   asmop_one.type = AOP_LIT;
   asmop_one.size = 1;
   asmop_one.aopu.aop_lit = constVal ("1");
+  
+  asmop_mone.type = AOP_LIT;
+  asmop_mone.size = 8; // Maximum size for asmop.
+  asmop_mone.aopu.aop_lit = constVal ("-1");
 
   asmop_sp.type = AOP_SFR;
   asmop_sp.aopu.aop_dir = "sp";
@@ -135,6 +140,18 @@
   return (!bitVectBitValue (ic->rSurv, idx));
 }
 
+/*---------------------------------------------------------------------*/
+/* pdk_emitDebuggerSymbol - associate the current code location        */
+/*   with a debugger symbol                                            */
+/*---------------------------------------------------------------------*/
+void
+pdk_emitDebuggerSymbol (const char *debugSym)
+{
+  G.debugLine = 1;
+  emit2 ("", "%s ==.", debugSym);
+  G.debugLine = 0;
+}
+
 /*-----------------------------------------------------------------*/
 /* aopInReg - asmop from offset in the register                    */
 /*-----------------------------------------------------------------*/
@@ -195,7 +212,7 @@
       val >>= 8;
 
       // Leading zeroes
-      if (aop->size <= offset && !b)
+      if ((aop->size <= offset || aop->type == AOP_STL && offset) && !b)
         continue;
 
       if (aop->type == AOP_IMMD && offset > (aop->aopu.code ? 1 : 0) && !b)
@@ -470,7 +487,7 @@
     }
 
   /* None of the above, which only leaves temporaries. */
-  if ((sym->isspilt || sym->nRegs == 0) && !(regalloc_dry_run && (options.stackAuto || reentrant)))
+  if ((sym->isspilt || sym->nRegs == 0) && sym->usl.spillLoc && !(regalloc_dry_run && (options.stackAuto || reentrant)))
     {
       sym->aop = op->aop = aopForSym (ic, sym->usl.spillLoc);
       op->aop->size = getSize (sym->type);
@@ -674,7 +691,7 @@
     {
       int soffset = s - G.stack.pushed;
       emit2 ("xch", "a, p");
-      emit2 ("mov", "a, sp");
+      emit2 ("mov.io", "a, sp");
       emit2 ("add", "a, #0x%02x", soffset & 0xff);
       emit2 ("xch", "a, p");
       cost (4, 4);
@@ -763,7 +780,7 @@
         }
       else
         {
-          emit2 ("mov", "a, sp");
+          emit2 ("mov.io", "a, sp");
           emit2 ("add", "a, #0x%02x", (source->aopu.stk_off - G.stack.pushed) & 0xff);
           cost (2, 2);
         }
@@ -804,18 +821,24 @@
     }
   else if (aopInReg (result, roffset, A_IDX))
     {
-      emit2 ("mov", "a, %s", aopGet (source, soffset));
-      cost (1, 1);
+      if (!dummy)
+        {
+          emit2 (source->type == AOP_SFR ? "mov.io" : "mov", "a, %s", aopGet (source, soffset));
+          cost (1, 1);
+        }
     }
   else if (aopInReg (source, soffset, A_IDX))
     {
-      emit2 ("mov", "%s, a", aopGet (result, roffset));
-      cost (1, 1);
+      if (!dummy)
+        {
+          emit2 (result->type == AOP_SFR ? "mov.io" : "mov", "%s, a", aopGet (result, roffset));
+          cost (1, 1);
+        }
     }
   else if (result->type == AOP_STK && (source->type == AOP_DIR || source->type == AOP_IMMD || source->type == AOP_LIT || source->type == AOP_SFR) && a_dead && p_dead)
     {
       pointPStack(result->aopu.bytes[roffset].byteu.stk, true, f_dead);
-      emit2 ("mov", "a, %s", aopGet (source, soffset));
+      emit2 (source->type == AOP_SFR ? "mov.io" : "mov", "a, %s", aopGet (source, soffset));
       emit2 ("idxm", "p, a");
       cost (2, 3);
     }
@@ -861,9 +884,9 @@
   else if (!a_free && p_free)
     {
       emit2 ("xch", "a, p");
-      emit2 ("mov", "a, sp");
+      emit2 ("mov.io", "a, sp");
       emit2 ("add", "a, #%d", n);
-      emit2 ("mov", "sp, a");
+      emit2 ("mov.io", "sp, a");
       emit2 ("xch", "a, p");
       cost (5, 5);
     }
@@ -879,9 +902,9 @@
       emit2 ("mov", "p, a");
       cost (2, 3);
 
-      emit2 ("mov", "a, sp");
+      emit2 ("mov.io", "a, sp");
       emit2 ("add", "a, #%d", n - 2);
-      emit2 ("mov", "sp, a");
+      emit2 ("mov.io", "sp, a");
       cost (3, 3);
       G.stack.pushed -= 2;
 
@@ -890,9 +913,9 @@
   else // Can't use pop af, since it might affect reserved flag bits.
     {
       wassert (a_free);
-      emit2 ("mov", "a, sp");
+      emit2 ("mov.io", "a, sp");
       emit2 ("add", "a, #%d", n);
-      emit2 ("mov", "sp, a");
+      emit2 ("mov.io", "sp, a");
       cost (3, 3);
     }
 
@@ -980,9 +1003,22 @@
 genMove_o (asmop *result, int roffset, asmop *source, int soffset, int size, bool a_dead_global, bool p_dead_global)
 {
   // Handle I/O first.
-  wassert_bt ((result->type == AOP_SFR) + (source->type == AOP_SFR) <= 1);
+  if (result->type == AOP_SFR && source->type == AOP_SFR)
+    {
+      wassert (result->size == 1 && source->size == 1);
+      if (!a_dead_global)
+        pushAF ();
+
+      // Explicitly go through a (cheapMove might otherwise optimize out assignment of volatiles).
+      cheapMove (ASMOP_A, 0, source, soffset, true, p_dead_global, true);
+      cheapMove (result, roffset, ASMOP_A, 0, true, p_dead_global, true);
 
-  if (source->type == AOP_SFR)
+      if (!a_dead_global)
+        popAF ();
+        
+      return;
+    }
+  else if (source->type == AOP_SFR)
     {
       wassert (source->size == 1 || source->size == 2);
       wassert (size >= source->size);
@@ -1045,7 +1081,7 @@
       cheapMove (result, roffset + 0, source, soffset + 0, false, p_dead_global, true);
       return;
     }
-  else if (size == 2 && result->type == AOP_STK && aopInReg (source, soffset, A_IDX) && aopInReg (source, soffset + 1, P_IDX))
+  else if (size >= 2 && result->type == AOP_STK && aopInReg (source, soffset, A_IDX) && aopInReg (source, soffset + 1, P_IDX))
     {
       if (!p_dead_global)
         pushPF (false);
@@ -1055,11 +1091,12 @@
       cheapMove (result, roffset + 1, ASMOP_A, 0, false, true, true);
       popAF ();
       cheapMove (result, roffset + 0, ASMOP_A, 0, a_dead_global, true, true);
+      genMove_o (result, 2, ASMOP_ZERO, 0, size - 2, a_dead_global, true);
       if (!p_dead_global)
         popPF (a_dead_global);
       return;
     }
-  else if (size == 2 && result->type == AOP_STK && aopInReg (source, soffset, P_IDX) && aopInReg (source, soffset + 1, A_IDX))
+  else if (size >= 2 && result->type == AOP_STK && aopInReg (source, soffset, P_IDX) && aopInReg (source, soffset + 1, A_IDX))
     {
       if (!p_dead_global)
         pushPF (false);
@@ -1069,6 +1106,7 @@
       cheapMove (result, roffset + 0, ASMOP_A, 0, false, true, true);
       popAF ();
       cheapMove (result, roffset + 1, ASMOP_A, 0, a_dead_global, true, true);
+      genMove_o (result, 2, ASMOP_ZERO, 0, size - 2, a_dead_global, true);
       if (!p_dead_global)
         popPF (a_dead_global);
       return;
@@ -1117,10 +1155,10 @@
         pushAF ();
       if (soffset + 1 == roffset) // Use xch via a.
         {
-          emit2 ("mov", "a, %s", aopGet (source, soffset));
+          emit2 (source->type == AOP_SFR ? "mov.io" : "mov", "a, %s", aopGet (source, soffset));
           for (int i = 0; i < size - 1; i++)
             emit2 ("xch", "a, %s", aopGet (result, roffset + i));
-          emit2 ("mov", "%s, a", aopGet (result, roffset + size - 1));
+          emit2 (result->type == AOP_SFR ? "mov.io" : "mov", "%s, a", aopGet (result, roffset + size - 1));
           cost (size + 1, size + 1);
         }
       else // Copy high-to-low to avoid overwriting of still-needed bytes.
@@ -1265,6 +1303,7 @@
                 pushPF (true);
               cheapMove (ASMOP_P, 0, left->aop, i, false, true, true);
               emit2 ("or", "a, p");
+              cost (1, 1);
               if (!regDead (P_IDX, ic))
                 popPF (true);
             }
@@ -1275,6 +1314,7 @@
       emit2 ("sub", "a, #0x01");
       emit2 ("mov", "a, #0x00");
       emit2 ("slc", "a");
+      cost (3, 3);
 
       cheapMove (result->aop, 0, ASMOP_A, 0, true, true, true);
     }
@@ -1285,6 +1325,119 @@
   freeAsmop (result);
 }
 
+static void
+genXorByte (const asmop *result_aop, const asmop *left_aop, const asmop *right_aop, int i, bool *pushed_a, bool a_dead, bool p_dead)
+{
+  if ((aopInReg (left_aop, i, A_IDX) || aopInReg (left_aop, i, P_IDX) || left_aop->type == AOP_DIR) &&
+    aopIsLitVal (right_aop, i, 1, 0xff) && aopSame (result_aop, i, left_aop, i, 1))
+    {
+      emit2 ("not", "%s", aopGet (left_aop, i));
+      cost (1, 1);
+    }
+  else if (aopIsLitVal (right_aop, i, 1, 0x00))
+    {
+      cheapMove (result_aop, i, left_aop, i, a_dead, p_dead, true);
+    }
+  else if (aopInReg (left_aop, i, P_IDX) && aopInReg (result_aop, i, P_IDX) && right_aop->type != AOP_STK && !a_dead)
+    {
+      emit2 ("xch", "a, p");
+      emit2 ("xor", "a, %s", aopGet (right_aop, i));
+      emit2 ("xch", "a, p");
+      cost (3, 3);
+    }
+  else
+    {
+      if (!a_dead && !*pushed_a)
+        {
+          pushAF();
+          *pushed_a = true;
+        }
+
+      if ((left_aop->type == AOP_DIR || aopInReg (left_aop, i, P_IDX) || TARGET_IS_PDK15 && left_aop->type == AOP_SFR) && aopSame (left_aop, i, result_aop, i, 1))
+        {
+          cheapMove (ASMOP_A, 0, right_aop, i, true, p_dead, true);
+          emit2 (left_aop->type == AOP_SFR ? "xor.io" : "xor", "%s, a", aopGet (left_aop, i));
+          cost (1, 1);
+        }
+      else if ((right_aop->type == AOP_DIR || aopInReg (right_aop, i, P_IDX) || TARGET_IS_PDK15 && right_aop->type == AOP_SFR) && aopSame (right_aop, i, result_aop, i, 1))
+        {
+          cheapMove (ASMOP_A, 0, left_aop, i, true, true, true);
+          emit2 (right_aop->type == AOP_SFR ? "xor.io" : "xor", "%s, a", aopGet (right_aop, i));
+          cost (1, 1);
+        }
+      else if (right_aop->type == AOP_STK || right_aop->type == AOP_STL)
+        {
+          if (!p_dead || aopInReg (left_aop, i, P_IDX))
+            {
+              cost (100, 100);
+              wassert (regalloc_dry_run);
+            }
+          cheapMove (ASMOP_A, 0, left_aop, i, true, true, true);
+          cheapMove (ASMOP_P, 0, right_aop, i, false, true, true);
+          emit2 ("xor", "a, p");
+          cost (1, 1);
+          cheapMove (result_aop, i, ASMOP_A, 0, true, true, true);
+        }
+      else
+        {
+          cheapMove (ASMOP_A, 0, left_aop, i, true, p_dead, true);
+          emit2 ("xor", "a, %s", aopGet (right_aop, i));
+          cost (1, 1);
+          cheapMove (result_aop, i, ASMOP_A, 0, true, p_dead, true);
+        }
+    }
+}
+
+/*-----------------------------------------------------------------*/
+/* genXorImpl - code for xor asmops                                */
+/*-----------------------------------------------------------------*/
+static void
+genXorImpl (const iCode *ic, asmop *result_aop, asmop *left_aop, asmop *right_aop)
+{
+  int size = result_aop->size;
+  int skip_byte = -1;
+
+  /* Swap if left is literal or right is in A. */
+  if (left_aop->type == AOP_LIT || aopInReg (right_aop, 0, A_IDX) || aopInReg (right_aop, 1, A_IDX) || right_aop->type == AOP_STK && !aopInReg (left_aop, 0, A_IDX))
+    {
+      asmop *t = right_aop;
+      right_aop = left_aop;
+      left_aop = t;
+    }
+
+  bool a_free = regDead (A_IDX, ic);
+  bool p_free = regDead (P_IDX, ic);
+  bool pushed_a = false;
+
+  for (int i = 0; i < size; i++)
+    if (aopInReg (left_aop, i, A_IDX))
+      {
+        genXorByte (result_aop, left_aop, right_aop, i, &pushed_a, a_free, p_free && !aopInReg (left_aop, !i, P_IDX));
+        skip_byte = i;
+
+        if (aopInReg (result_aop, i, A_IDX))
+          a_free = false;
+        if (aopInReg (result_aop, i, P_IDX))
+          p_free = false;
+      }
+
+  for (int i = 0; i < size; i++)
+    {
+      if (i == skip_byte)
+        continue;
+
+      genXorByte (result_aop, left_aop, right_aop, i, &pushed_a, a_free, p_free);
+
+      if (aopInReg (result_aop, i, A_IDX))
+        a_free = false;
+      if (aopInReg (result_aop, i, P_IDX))
+        p_free = false;
+    }
+
+  if (pushed_a)
+    popAF();
+}
+
 /*-----------------------------------------------------------------*/
 /* genCpl - generate code for complement                           */
 /*-----------------------------------------------------------------*/
@@ -1298,40 +1451,8 @@
 
   aopOp (left, ic);
   aopOp (result, ic);
-
-  int size = result->aop->size;
-
-  if (result->aop->type == AOP_STK)
-    {
-      bool pushed_p = false;
-      for (int i = 0; i < size; i++)
-        {
-          if (aopInReg (left->aop, P_IDX, i) && pushed_p)
-            {
-              popAF ();
-              pushed_p = false;
-            }
-          else
-            cheapMove (ASMOP_A, 0, left->aop, i, true, true, true);
-          emit2 ("not", "a");
-          if (aopInReg (left->aop, P_IDX, i + 1))
-            {
-              pushPF (false);
-              pushed_p = true;
-            }
-          cheapMove (result->aop, i, ASMOP_A, 0, true, true, true);
-        }
-     }
-  else
-    {
-      genMove (result->aop, left->aop, true, true);
-
-      for (int i = 0; i < size; i++)
-        {
-          emit2 ("not", "%s", aopGet (result->aop, i));
-          cost (1, 1);
-        }
-    }
+  
+  genXorImpl (ic, result->aop, left->aop, ASMOP_MONE);
 
   freeAsmop (left);
   freeAsmop (result);
@@ -1452,7 +1573,7 @@
             }
           started = true;
         }
-      else if (right_aop->type == AOP_STK || right_aop->type == AOP_STL && !i)
+      else if (right_aop->type == AOP_STK || right_aop->type == AOP_STL && !i || right_aop->type == AOP_CODE || right_aop->type == AOP_SFR)
         {
           if (i + 1 < size && aopInReg (left_aop, i + 1, P_IDX))
             pushPF (!aopInReg (left_aop, i, A_IDX));
@@ -1674,7 +1795,7 @@
 
       if (rsym->onStack || rsym->isspilt && regalloc_dry_run && (options.stackAuto || reentrant))
         {
-          emit2 ("mov", "a, sp");
+          emit2 ("mov.io", "a, sp");
           emit2 ("add", "a, #0x%02x", (rsym->stack + (rsym->stack < 0 ? G.stack.param_offset : 0) - G.stack.pushed) & 0xff);
         }
       else
@@ -1752,7 +1873,7 @@
             {
               emit2 ("mov", "a, #<(!tlabel)", labelKey2num (tlbl->key));
               emit2 ("push", "af");
-              emit2 ("mov", "a, sp");
+              emit2 ("mov.io", "a, sp");
               emit2 ("mov", "p, a");
               emit2 ("dec", "p");
               emit2 ("mov", "a, #>(!tlabel)", labelKey2num (tlbl->key));
@@ -2121,7 +2242,7 @@
           started = true;
           continue;
         }
-      else if (right->aop->type == AOP_STK || right->aop->type == AOP_STL && !i)
+      else if (right->aop->type == AOP_STK || right->aop->type == AOP_STL && !i || right->aop->type == AOP_CODE)
         {
           if (!regDead (P_IDX, ic) && !pushed_p)
             {
@@ -2238,6 +2359,9 @@
   freeAsmop (result);
 }
 
+static void
+genIfx (const iCode *ic);
+
 /*-----------------------------------------------------------------*/
 /* genMinus - generates code for minus                             */
 /*-----------------------------------------------------------------*/
@@ -2256,20 +2380,52 @@
 
   if (ifx && ifx->generated)
     {
-      wassert (IC_TRUE (ifx));
       wassert (left->aop->type == AOP_REG || left->aop->type == AOP_DIR);
-      wassert (aopIsLitVal (right->aop, 0, 2, 1));
+      wassert (aopIsLitVal (right->aop, 0, left->aop->size, 1));
 
-      emit2 ("dzsn", aopGet (left->aop, 0));
-      cost (1, 1.8f);
-      emitJP (IC_TRUE (ifx), 0.2f);
-
-      for(int i = 1; i < left->aop->size; i++)
+      if (left->aop->size == 1 && IC_TRUE (ifx))
+        {
+          emit2 ("dzsn", aopGet (left->aop, 0));
+          cost (1, 1.8f);
+          emitJP (IC_TRUE (ifx), 0.2f);
+        }
+      else if (aopInReg (left->aop, 0, A_IDX) || aopInReg (left->aop, 1, A_IDX) && IC_TRUE (ifx))
         {
-          emit2 ("subc", aopGet (left->aop, i));
-          emit2 ("t1sn", "f, z");
-          cost (2, 2.8f);
+          if (aopInReg (left->aop, 0, A_IDX))
+            emit2 ("sub", "a, #0x01");
+          else
+            emit2 ("dec", aopGet (left->aop, 0));
+          for (int i = 1; i < left->aop->size; i++)
+            emit2 ("subc", aopGet (left->aop, i));
+            
+          emit2 ("ceqsn", "a, #0x00");
+          cost (1 + left->aop->size, left->aop->size + 1.8f);
           emitJP (IC_TRUE (ifx), 0.2f);
+          
+          for (int i = 0; i < left->aop->size; i++)
+            {
+              if (aopInReg (left->aop, i, A_IDX))
+                continue;
+              emit2 ("ceqsn", "a, %s", aopGet (left->aop, i));
+              cost (1, 1.8f);
+              emitJP (IC_TRUE (ifx), 0.2f);
+            }
+        }
+      else if (left->aop->size == 1 && IC_FALSE (ifx))
+        {
+          if (aopInReg (left->aop, 0, A_IDX))
+            emit2 ("sub", "a, #0x01");
+          else
+            emit2 ("dec", aopGet (left->aop, 0));
+            
+          emit2 ("t0sn.io", "f, z");
+          cost (2, 2.5f);
+          emitJP (IC_FALSE (ifx), 0.5f);
+        }
+      else
+        {
+          genSub (ic, result->aop, left->aop, right->aop);
+          genIfx (ifx);
         }
     }
   else
@@ -2314,9 +2470,7 @@
   unsigned long long add, sub;
   int topbit, nonzero;
 
-  value *bval = valueFromLit (ulFromVal (right->aop->aopu.aop_lit) & 0xff);
-  wassert (!csdOfVal (&topbit, &nonzero, &add, &sub, bval));
-  Safe_free (bval);
+  wassert (!csdOfVal (&topbit, &nonzero, &add, &sub, right->aop->aopu.aop_lit, 0xff));
 
   // If the leading digits of the cse are 1 0 -1 we can use 0 1 1 instead to reduce the number of shifts.
   if (topbit >= 2 && (add & (1ull << topbit)) && (sub & (1ull << (topbit - 2))))
@@ -2414,14 +2568,14 @@
           if (IC_TRUE (ifx))
             {
               emit2 ("ceqsn", "a, #0x%02x", byteOfVal (right->aop->aopu.aop_lit, 0) + 1);
-              emit2 ("t1sn", "f, c");
+              emit2 ("t1sn.io", "f, c");
               cost (2, 2.5);
             }
           else
             {
               emit2 ("ceqsn", "a, #0x%02x", byteOfVal (right->aop->aopu.aop_lit, 0) + 1);
               emit2 ("nop", "");
-              emit2 ("t0sn", "f, c");
+              emit2 ("t0sn.io", "f, c");
               cost (3, 3.5);
             }
           emitJP (IC_FALSE (ifx) ? IC_FALSE (ifx) : IC_TRUE (ifx), 0.5f);
@@ -2432,20 +2586,20 @@
           if (IC_FALSE (ifx))
             {
               emit2 ("ceqsn", "a, %s", aopGet (right->aop, 0));
-              emit2 ("t1sn", "f, c");
+              emit2 ("t1sn.io", "f, c");
               cost (2, 2.5);
             }
           else if ((TARGET_IS_PDK15 || TARGET_IS_PDK16) && (right->aop->type == AOP_DIR || aopInReg (right->aop, 0, P_IDX)))
             {
               emit2 ("comp", "a, %s", aopGet (right->aop, 0));
-              emit2 ("t0sn", "f, c");
+              emit2 ("t0sn.io", "f, c");
               cost (2, 2.5);
             }
           else
             {
               emit2 ("ceqsn", "a, %s", aopGet (right->aop, 0));
               emit2 ("nop", "");
-              emit2 ("t0sn", "f, c");
+              emit2 ("t0sn.io", "f, c");
               cost (3, 3.5);
             }
           emitJP (IC_FALSE (ifx) ? IC_FALSE (ifx) : IC_TRUE (ifx), 0.5f);
@@ -2481,13 +2635,13 @@
                        emit2 ("sub", "a, #0x80");
                        cost (1, 1);
                      }
-                   emit2 ("t0sn", "f, c");
+                   emit2 ("t0sn.io", "f, c");
                    cost (1, 1.5);
                  }
                else
                  {
                    emit2 ("ceqsn", "a, #0x80");
-                   emit2 ("t1sn", "f, c");
+                   emit2 ("t1sn.io", "f, c");
                    cost (2, 2.5);
                  }
 
@@ -2513,7 +2667,13 @@
         }
       else if (started && (right->aop->type == AOP_LIT && !aopIsLitVal (right->aop, i, 1, 0x00) || right->aop->type == AOP_IMMD)) // Work around lack of subc a, #nn.
         {
-          if (left->aop->type == AOP_STK)
+          if (aopInReg (left->aop, i, P_IDX))
+            {
+              cheapMove (ASMOP_A, 0, right->aop, i, true, false, !i);
+              emit2 ("xch", "a, p");
+              cost (1, 1);
+            }
+          else if (left->aop->type == AOP_STK)
             {
               cheapMove (ASMOP_A, 0, left->aop, i, true, true, !i);
               cheapMove (ASMOP_P, 0, right->aop, i, false, true, !i);
@@ -2566,7 +2726,7 @@
 
   if (sign)
     {
-      emit2 ("t0sn", "f, ov");
+      emit2 ("t0sn.io", "f, ov");
       emit2 ("xor", "a, #0x80");
       emit2 ("sl", "a");
       cost (3, 3);
@@ -2574,7 +2734,7 @@
 
   if (ifx)
     {
-      emit2 (IC_FALSE(ifx) ? "t1sn" : "t0sn", "f, c");
+      emit2 (IC_FALSE(ifx) ? "t1sn.io" : "t0sn.io", "f, c");
       cost (1, 1.5);
       emitJP (IC_FALSE (ifx) ? IC_FALSE (ifx) : IC_TRUE (ifx), 0.5f);
     }
@@ -2638,34 +2798,42 @@
 
   if (aopInReg (left->aop, 1, A_IDX) && (right->aop->type == AOP_LIT || right->aop->type == AOP_DIR || right->aop->type == AOP_IMMD))
     {
-      wassert (regDead (A_IDX, ic));
-
       emit2 ("ceqsn", "a, %s", aopGet (right->aop, 1));
-      cost (1, 1);
-      emitJP (lbl_ne, 0.0f);
-      cheapMove (ASMOP_A, 0, left->aop, 0, true, true, true);
+      cost (1, 1.0f);
+      emitJP (lbl_ne, 1.0f);
+      
       if (ifx && ((ic->op == EQ_OP) ^ (bool)(IC_FALSE(ifx))))
         {
+          wassert (regDead (A_IDX, ic));
+          cheapMove (ASMOP_A, 0, left->aop, 0, true, true, true);
           if (TARGET_IS_PDK13) // pdk13 does not have cneqsn
             {
               symbol *tlbl = (regalloc_dry_run ? 0 : newiTempLabel (NULL));
               emit2 ("ceqsn", "a, %s", aopGet (right->aop, 0));
               emitJP (tlbl, 0.0f);
-              cost (2, 3);
+              cost (2, 0);
               emitJP (IC_FALSE (ifx) ? IC_FALSE (ifx) : IC_TRUE (ifx), 0.0f);
               emitLabel (tlbl);
             }
           else
             {
               emit2 ("cneqsn", "a, %s", aopGet (right->aop, 0));
-              cost (1, 1);
+              cost (1, 0);
               emitJP (IC_FALSE (ifx) ? IC_FALSE (ifx) : IC_TRUE (ifx), 0.0f);
             }
         }
+      else if (aopInReg (left->aop, 0, P_IDX) && regDead (P_IDX, ic) && aopIsLitVal (right->aop, 0, 1, 0xff))
+        {
+          emit2 ("izsn", "p");
+          cost (1, 0);
+          emitJP (lbl_ne, 0.0f);
+        }
       else
         {
+          wassert (regDead (A_IDX, ic));
+          cheapMove (ASMOP_A, 0, left->aop, 0, true, true, true);
           emit2 ("ceqsn", "a, %s", aopGet (right->aop, 0));
-          cost (1, 1);
+          cost (1, 0);
           emitJP (lbl_ne, 0.0f);
         }
     }
@@ -2765,62 +2933,6 @@
   freeAsmop (result);
 }
 
-static void
-genXorByte (const asmop *result_aop, const asmop *left_aop, const asmop *right_aop, int i, bool *pushed_a, bool a_dead, bool p_dead)
-{
-  if ((aopInReg (left_aop, i, A_IDX) || aopInReg (left_aop, i, P_IDX) || left_aop->type == AOP_DIR) &&
-    aopIsLitVal (right_aop, i, 1, 0xff) && aopSame (result_aop, i, left_aop, i, 1))
-    {
-      emit2 ("not", "%s", aopGet (left_aop, i));
-      cost (1, 1);
-    }
-  else if (aopIsLitVal (right_aop, i, 1, 0x00))
-    {
-      cheapMove (result_aop, i, left_aop, i, a_dead, p_dead, true);
-    }
-  else
-    {
-      if (!a_dead && !*pushed_a)
-        {
-          pushAF();
-          *pushed_a = true;
-        }
-
-      if ((left_aop->type == AOP_DIR || aopInReg (left_aop, i, P_IDX)) && aopSame (left_aop, i, result_aop, i, 1))
-        {
-          cheapMove (ASMOP_A, 0, right_aop, i, true, p_dead, true);
-          emit2 ("xor", "%s, a", aopGet (left_aop, i));
-          cost (1, 1);
-        }
-      else if ((right_aop->type == AOP_DIR || aopInReg (right_aop, i, P_IDX)) && aopSame (right_aop, i, result_aop, i, 1))
-        {
-          cheapMove (ASMOP_A, 0, left_aop, i, true, true, true);
-          emit2 ("xor", "%s, a", aopGet (right_aop, i));
-          cost (1, 1);
-        }
-      else if (right_aop->type == AOP_STK)
-        {
-          if (!p_dead || aopInReg (left_aop, i, P_IDX))
-            {
-              cost (100, 100);
-              wassert (regalloc_dry_run);
-            }
-          cheapMove (ASMOP_A, 0, left_aop, i, true, true, true);
-          cheapMove (ASMOP_P, 0, right_aop, i, false, true, true);
-          emit2 ("xor", "a, p");
-          cost (1, 1);
-          cheapMove (result_aop, i, ASMOP_A, 0, true, true, true);
-        }
-      else
-        {
-          cheapMove (ASMOP_A, 0, left_aop, i, true, p_dead, true);
-          emit2 ("xor", "a, %s", aopGet (right_aop, i));
-          cost (1, 1);
-          cheapMove (result_aop, i, ASMOP_A, 0, true, p_dead, true);
-        }
-    }
-}
-
 /*-----------------------------------------------------------------*/
 /* genXor - code for xor                                           */
 /*-----------------------------------------------------------------*/
@@ -2836,50 +2948,9 @@
   aopOp (left, ic);
   aopOp (right, ic);
   aopOp (result, ic);
-
-  int size = result->aop->size;
-  int skip_byte = -1;
-
-  /* Swap if left is literal or right is in A. */
-  if (left->aop->type == AOP_LIT || aopInReg (right->aop, 0, A_IDX) || aopInReg (right->aop, 1, A_IDX) || right->aop->type == AOP_STK && !aopInReg (left->aop, 0, A_IDX))
-    {
-      operand *t = right;
-      right = left;
-      left = t;
-    }
-
-  bool a_free = regDead (A_IDX, ic);
-  bool p_free = regDead (P_IDX, ic);
-  bool pushed_a = false;
-
-  for (int i = 0; i < size; i++)
-    if (aopInReg (left->aop, i, A_IDX))
-      {
-        genXorByte (result->aop, left->aop, right->aop, i, &pushed_a, a_free, p_free);
-        skip_byte = i;
-
-        if (aopInReg (result->aop, i, A_IDX))
-          a_free = false;
-        if (aopInReg (result->aop, i, P_IDX))
-          p_free = false;
-      }
-
-  for (int i = 0; i < size; i++)
-    {
-      if (i == skip_byte)
-        continue;
-
-      genXorByte (result->aop, left->aop, right->aop, i, &pushed_a, a_free, p_free);
-
-      if (aopInReg (result->aop, i, A_IDX))
-        a_free = false;
-      if (aopInReg (result->aop, i, P_IDX))
-        p_free = false;
-    }
-
-  if (pushed_a)
-    popAF();
-
+  
+  genXorImpl (ic, result->aop, left->aop, right->aop);  
+  
   freeAsmop (right);
   freeAsmop (left);
   freeAsmop (result);
@@ -2903,46 +2974,51 @@
 
   int size = result->aop->size;
 
-  /* Swap if left is literal or right is in A. */
-  if (left->aop->type == AOP_LIT || aopInReg (right->aop, 0, A_IDX)  || right->aop->type == AOP_STK && !aopInReg (left->aop, 0, A_IDX))
-    {
-      operand *t = right;
-      right = left;
-      left = t;
-    }
-
   bool p_free = regDead (P_IDX, ic) && !aopInReg (left->aop, 0, P_IDX) && !aopInReg (left->aop, 1, P_IDX) && !aopInReg (right->aop, 0, P_IDX) && !aopInReg (right->aop, 1, P_IDX);
+  bool a_free = regDead (A_IDX, ic) && !aopInReg (left->aop, 0, A_IDX) && !aopInReg (left->aop, 1, A_IDX) && !aopInReg (right->aop, 0, A_IDX) && !aopInReg (right->aop, 1, A_IDX);
 
   for (int i = 0; i < size; i++)
     {
-      if (regDead (P_IDX, ic) && (aopInReg (left->aop, i, P_IDX) || aopInReg (right->aop, i, P_IDX)))
+      /* Swap if left is literal or right is in A. */
+      if (left->aop->type == AOP_LIT || aopInReg (right->aop, 0, A_IDX)  || (right->aop->type == AOP_STK || right->aop->type == AOP_SFR) && !aopInReg (left->aop, i, A_IDX))
+        {
+          operand *t = right;
+          right = left;
+          left = t;
+        }
+    
+      if (regDead (P_IDX, ic) && aopInReg (left->aop, i, P_IDX))
         p_free = true;
+      if (regDead (A_IDX, ic) && aopInReg (left->aop, i, A_IDX))
+        a_free = true;
 
       int bit = right->aop->type == AOP_LIT ? isLiteralBit (byteOfVal (right->aop->aopu.aop_lit, i)) : -1;
 
       if (aopIsLitVal (right->aop, i, 1, 0x00))
         {
-          cheapMove (result->aop, i, left->aop, i, true, p_free, true);
+          cheapMove (result->aop, i, left->aop, i, a_free, p_free, true);
         }
       else if ((left->aop->type == AOP_SFR || aopInReg (left->aop, i, P_IDX)) && aopSame (left->aop, i, result->aop, i, 1) && bit >= 0)
         {
-          emit2 ("set1", "%s, #%d", aopGet (left->aop, i), bit);
+          emit2 (left->aop->type == AOP_SFR ? "set1.io" : "set1", "%s, #%d", aopGet (left->aop, i), bit);
           cost (1, 1);
         }
-      else if ((left->aop->type == AOP_DIR || aopInReg (left->aop, i, P_IDX) && right->aop->type != AOP_STK) && aopSame (left->aop, i, result->aop, i, 1))
+      else if ((left->aop->type == AOP_DIR || aopInReg (left->aop, i, P_IDX) && right->aop->type != AOP_STK) && aopSame (left->aop, i, result->aop, i, 1) && a_free)
         {
           cheapMove (ASMOP_A, 0, right->aop, i, true, p_free && !aopInReg (left->aop, i, P_IDX), true);
           emit2 ("or", "%s, a", aopGet (left->aop, i));
           cost (1, 1);
         }
-      else if ((right->aop->type == AOP_DIR || aopInReg (right->aop, i, P_IDX) && left->aop->type != AOP_STK) && aopSame (right->aop, i, result->aop, i, 1))
+      else if ((right->aop->type == AOP_DIR || aopInReg (right->aop, i, P_IDX) && left->aop->type != AOP_STK) && aopSame (right->aop, i, result->aop, i, 1) && a_free)
         {
           cheapMove (ASMOP_A, 0, left->aop, i, true, p_free && !aopInReg (right->aop, i, P_IDX), true);
           emit2 ("or", "%s, a", aopGet (right->aop, i));
           cost (1, 1);
         }
-      else if (right->aop->type == AOP_STK)
+      else if (right->aop->type == AOP_STK || right->aop->type == AOP_SFR)
         {
+          if (!a_free)
+            pushAF();
           if (!p_free)
             pushPF (!aopInReg (right->aop, i, A_IDX));
           cheapMove (ASMOP_A, 0, left->aop, i, true, p_free && !aopInReg (right->aop, i, P_IDX), true);
@@ -2952,17 +3028,39 @@
           cheapMove (result->aop, i, ASMOP_A, 0, true, true, true);
           if (!p_free)
             popPF (!aopInReg (result->aop, i, A_IDX));
+          if (!a_free)
+            popAF();
+        }
+      else if (aopInReg (left->aop, i, P_IDX) && aopInReg (result->aop, i, P_IDX) && !a_free)
+        {
+          emit2 ("xch", "a, p");
+          emit2 ("or", "a, %s", aopGet (right->aop, i));
+          emit2 ("xch", "a, p");
+          cost (3, 3);
+        }
+      else if (aopInReg (right->aop, i, P_IDX) && aopInReg (result->aop, i, P_IDX) && !a_free)
+        {
+          emit2 ("xch", "a, p");
+          emit2 ("or", "a, %s", aopGet (left->aop, i));
+          emit2 ("xch", "a, p");
+          cost (3, 3);
         }
       else
         {
+          if (!a_free)
+            pushAF();
           cheapMove (ASMOP_A, 0, left->aop, i, true, p_free && !aopInReg (right->aop, i, P_IDX), true);
           emit2 ("or", "a, %s", aopGet (right->aop, i));
           cost (1, 1);
           cheapMove (result->aop, i, ASMOP_A, 0, true, p_free, true);
+          if (!a_free)
+            popAF();
         }
 
       if (aopInReg (result->aop, i, P_IDX))
         p_free = false;
+      if (aopInReg (result->aop, i, A_IDX))
+        a_free = false;
     }
 
   freeAsmop (right);
@@ -3028,7 +3126,7 @@
         (byteOfVal (right->aop->aopu.aop_lit, i) == 0x7f || byteOfVal (right->aop->aopu.aop_lit, i) == 0xfe))
         {
           emit2 (byteOfVal (right->aop->aopu.aop_lit, 0) == 0x7f ? "sl" : "sr", "p");
-          emit2 (IC_FALSE  (ifx) ? "t0sn" : "t1sn", "f, z");
+          emit2 (IC_FALSE  (ifx) ? "t0sn.io" : "t1sn.io", "f, z");
           cost (2, 2.5);
         }
       else
@@ -3077,13 +3175,15 @@
             (byteOfVal (right->aop->aopu.aop_lit, i) == 0x7f || byteOfVal (right->aop->aopu.aop_lit, i) == 0xfe))
             {
               emit2 (byteOfVal (right->aop->aopu.aop_lit, 0) == 0x7f ? "sl" : "sr", "p");
-              emit2 ("t1sn", "f, z");
+              emit2 ("t1sn.io", "f, z");
               cost (2, 2.5);
             }
           else if (left->aop->type == AOP_DIR && right->aop->type == AOP_LIT) // Try to combine multiple bytes with 0xff mask by or.
             {
               int j, k;
-              for(j = i; j + 1 < right->aop->size && (aopIsLitVal (right->aop, j, 1, 0xff) || aopIsLitVal (right->aop, j, 1, 0x00)); j++);
+              for(j = i; j + 1 < right->aop->size && (aopIsLitVal (right->aop, j, 1, 0xff) || aopIsLitVal (right->aop, j, 1, 0x00)); j++); // Find a byte that does need an and-mask, and handle it first.
+              while(j > 0 && aopIsLitVal (right->aop, j, 1, 0x00)) // Avoid wrongly loading the last byte, if that one is to be ignored.
+                j--;
               cheapMove (ASMOP_A, 0, left->aop, j, true, true, true);
               if (!(aopIsLitVal (right->aop, j, 1, 0xff) || aopIsLitVal (right->aop, j, 1, 0x00)))
                 {
@@ -3121,13 +3221,16 @@
       goto release;
     }
 
-  bool p_dead = regDead (P_IDX, ic) && !aopInReg (left->aop, 0, P_IDX) && !aopInReg (left->aop, 1, P_IDX) && !aopInReg (right->aop, 0, P_IDX) && !aopInReg (right->aop, 1, P_IDX);
+  bool p_free = regDead (P_IDX, ic) && !aopInReg (left->aop, 0, P_IDX) && !aopInReg (left->aop, 1, P_IDX) && !aopInReg (right->aop, 0, P_IDX) && !aopInReg (right->aop, 1, P_IDX);
+  bool a_free = regDead (A_IDX, ic) && !aopInReg (left->aop, 0, A_IDX) && !aopInReg (left->aop, 1, A_IDX) && !aopInReg (right->aop, 0, A_IDX) && !aopInReg (right->aop, 1, A_IDX);
 
   for (int i = 0; i < size; i++)
     {
       if (regDead (P_IDX, ic) && (aopInReg (left->aop, i, P_IDX) || aopInReg (right->aop, i, P_IDX)))
-        p_dead = true;
-
+        p_free = true;
+      if (regDead (A_IDX, ic) && (aopInReg (left->aop, i, A_IDX) || aopInReg (right->aop, i, A_IDX)))
+        a_free = true;
+        
       if (aopInReg (right->aop, i, A_IDX))
         {
           operand *t = right;
@@ -3138,53 +3241,82 @@
       int bit = right->aop->type == AOP_LIT ? isLiteralBit (~byteOfVal (right->aop->aopu.aop_lit, i) & 0xff) : -1;
 
       if (aopIsLitVal (right->aop, i, 1, 0xff))
-        cheapMove (result->aop, i, left->aop, i, true, p_dead, true);
+        cheapMove (result->aop, i, left->aop, i, a_free, p_free, true);
       else if (aopIsLitVal (right->aop, i, 1, 0x00))
         {
           int zend;
           for (zend = i; zend + 1 < size && aopIsLitVal (right->aop, zend + 1, 1, 0x00); zend++);
-          genMove_o (result->aop, i, ASMOP_ZERO, 0, zend + 1 - i, true, p_dead);
+          genMove_o (result->aop, i, ASMOP_ZERO, 0, zend + 1 - i, a_free, p_free);
           i = zend;
         }
       else if ((left->aop->type == AOP_SFR || aopInReg (left->aop, i, P_IDX)) && aopSame (left->aop, i, result->aop, i, 1) && bit >= 0)
         {
-          emit2 ("set0", "%s, #%d", aopGet (left->aop, i), bit);
+          emit2 (left->aop->type == AOP_SFR ? "set0.io" : "set0", "%s, #%d", aopGet (left->aop, i), bit);
           cost (1, 1);
         }
-      else if ((left->aop->type == AOP_DIR || aopInReg (left->aop, i, P_IDX) && right->aop->type != AOP_STK) && aopSame (left->aop, i, result->aop, i, 1))
+      else if ((left->aop->type == AOP_DIR || aopInReg (left->aop, i, P_IDX) && right->aop->type != AOP_STK) && aopSame (left->aop, i, result->aop, i, 1) && a_free)
         {
-          cheapMove (ASMOP_A, 0, right->aop, i, true, p_dead && !aopInReg (left->aop, i, P_IDX), true);
+          cheapMove (ASMOP_A, 0, right->aop, i, true, p_free && !aopInReg (left->aop, i, P_IDX), true);
           emit2 ("and", "%s, a", aopGet (left->aop, i));
           cost (1, 1);
         }
-      else if ((right->aop->type == AOP_DIR || aopInReg (right->aop, i, P_IDX) && left->aop->type != AOP_STK) && aopSame (right->aop, i, result->aop, i, 1))
+      else if ((right->aop->type == AOP_DIR || aopInReg (right->aop, i, P_IDX) && left->aop->type != AOP_STK) && aopSame (right->aop, i, result->aop, i, 1) && a_free)
         {
-          cheapMove (ASMOP_A, 0, left->aop, i, true, p_dead && !aopInReg (right->aop, i, P_IDX), true);
+          cheapMove (ASMOP_A, 0, left->aop, i, true, p_free && !aopInReg (right->aop, i, P_IDX), true);
           emit2 ("and", "%s, a", aopGet (right->aop, i));
           cost (1, 1);
         }
       else if (right->aop->type == AOP_STK)
         {
-          if (!p_dead)
+          if (!a_free)
+            pushAF();
+          if (!p_free)
             pushPF (!aopInReg (left->aop, i, A_IDX));
           cheapMove (ASMOP_A, 0, left->aop, i, true, !aopInReg (right->aop, i, P_IDX), true);
           cheapMove (ASMOP_P, 0, right->aop, i, false, true, true);
           emit2 ("and", "a, p");
           cost (1, 1);
           cheapMove (result->aop, i, ASMOP_A, 0, true, true, true);
-          if (!p_dead)
+          if (!p_free)
             popPF (!aopInReg (result->aop, i, A_IDX));
+           if (!a_free)
+            popAF();
+        }
+      else if (aopInReg (left->aop, i, P_IDX) && aopInReg (result->aop, i, P_IDX) && !a_free)
+        {
+          emit2 ("xch", "a, p");
+          emit2 ("and", "a, %s", aopGet (right->aop, i));
+          emit2 ("xch", "a, p");
+          cost (3, 3);
+        }
+      else if (aopInReg (right->aop, i, P_IDX) && aopInReg (result->aop, i, P_IDX) && !a_free && left->aop->type != AOP_STK)
+        {
+          emit2 ("xch", "a, p");
+          emit2 ("and", "a, %s", aopGet (left->aop, i));
+          emit2 ("xch", "a, p");
+          cost (3, 3);
+        }
+      else if (right->aop->type == AOP_SFR)
+        {
+          wassert (regalloc_dry_run);
+          cost (100, 100);
         }
       else
         {
-          cheapMove (ASMOP_A, 0, left->aop, i, true, p_dead && !aopInReg (right->aop, i, P_IDX), true);
+          if (!a_free)
+            pushAF();
+          cheapMove (ASMOP_A, 0, left->aop, i, true, p_free && !aopInReg (right->aop, i, P_IDX), true);
           emit2 ("and", "a, %s", aopGet (right->aop, i));
           cost (1, 1);
-          cheapMove (result->aop, i, ASMOP_A, 0, true, p_dead, true);
+          cheapMove (result->aop, i, ASMOP_A, 0, true, p_free, true);
+          if (!a_free)
+            popAF();
         }
 
       if (aopInReg (result->aop, i, P_IDX))
-        p_dead = false;
+        p_free = false;
+      if (aopInReg (result->aop, i, A_IDX))
+        a_free = false;
     }
 
 release:
@@ -3194,7 +3326,72 @@
 }
 
 /*-----------------------------------------------------------------*/
-/* genLeftShift - generates code for right shifting               */
+/* genGetByte - generates code to get a single byte                */
+/*-----------------------------------------------------------------*/
+static void
+genGetByte (const iCode *ic)
+{
+  operand *left = IC_LEFT (ic);
+  operand *right = IC_RIGHT (ic);
+  operand *result = IC_RESULT (ic);
+  
+  aopOp (left, ic);
+  aopOp (right, ic);
+  aopOp (result, ic);
+
+  int offset = (int) ulFromVal (right->aop->aopu.aop_lit) / 8;  
+  genMove_o (result->aop, 0, left->aop, offset, 1, regDead (A_IDX, ic), regDead (P_IDX, ic));
+
+  freeAsmop (result);
+  freeAsmop (right);
+  freeAsmop (left);
+}
+
+/*-----------------------------------------------------------------*/
+/* genSwap - generates code for nibble swapping                    */
+/*-----------------------------------------------------------------*/
+static void
+genSwap (const iCode *ic)
+{
+  operand *result = IC_RESULT (ic);
+  operand *left = IC_LEFT (ic);
+
+  D (emit2 ("; genSwap", ""));
+
+  aopOp (result, ic);
+  aopOp (left, ic);
+
+  wassert (result->aop->size == 1);
+
+  if (TARGET_IS_PDK16 && // swap m is supported in pdk16, but not pdk13 and pdk14. Some pdk15 devices support it officially, some support it as undocumented feature. It is unclear if there are pdk15 that do not support it.
+    (result->aop->type == AOP_DIR || aopInReg (result->aop, 0, P_IDX)) &&
+    aopSame (left->aop, 0, result->aop, 0, 1))
+    {
+      emit2 ("swap", "%s", aopGet (result->aop, 0));
+      cost (1, 1);
+    }
+  else
+    {
+      if (!regDead (A_IDX, ic))
+        pushAF ();
+    
+      cheapMove (ASMOP_A, 0, left->aop, 0, true, regDead (P_IDX, ic), true);
+  
+      emit2 ("swap", "a");
+      cost (1, 1);
+  
+      cheapMove (result->aop, 0, ASMOP_A, 0, true, regDead (P_IDX, ic), true);
+    
+      if (!regDead (A_IDX, ic))
+        popAF ();
+    }
+
+  freeAsmop (left);
+  freeAsmop (result);
+}
+
+/*-----------------------------------------------------------------*/
+/* genLeftShift - generates code for right shifting                */
 /*-----------------------------------------------------------------*/
 static void
 genLeftShift (const iCode *ic)
@@ -3255,7 +3452,7 @@
           if (shCount == 7 && (size - offset) == 1 && (result->aop->type == AOP_REG || result->aop->type == AOP_DIR))
             {
               emit2 ("sr", "%s", aopGet (result->aop, offset));
-              if (aopInReg (result->aop, 0, A_IDX))
+              if (aopInReg (result->aop, offset, A_IDX))
                 emit2("mov", "a, #0x00");
               else
                 emit2 ("clear", "%s", aopGet (result->aop, offset));
@@ -3344,7 +3541,7 @@
       emitLabel (tlbl1);
       G.p.type = AOP_INVALID;
       emit2 ("sub", "a, #1");
-      emit2 ("t0sn", "f, c");
+      emit2 ("t0sn.io", "f, c");
       if (!regalloc_dry_run)
         emit2 ("goto", "!tlabel", labelKey2num (tlbl2->key));
       cost (3, 3);
@@ -3425,6 +3622,8 @@
   if (right->aop->type == AOP_LIT)
     {
       int shCount = ulFromVal (right->aop->aopu.aop_lit);
+      
+      wassert (shCount >= 0);
 
       if (SPEC_USIGN (getSpec (operandType (left))))
         {
@@ -3515,7 +3714,7 @@
               else if (aopInReg (result->aop, size - 1, A_IDX))
                 {
                    emit2 ("sl", "a");
-                   emit2 ("t0sn", "f, c");
+                   emit2 ("t0sn.io", "f, c");
                    emit2 ("or", "a, #0x01", aopGet (result->aop, size - 1));
                    emit2 ("src", "a");
                    emit2 ("src", "a");
@@ -3621,7 +3820,7 @@
       G.p.type = AOP_INVALID;
 
       emit2 ("sub", "a, #1");
-      emit2 ("t0sn", "f, c");
+      emit2 ("t0sn.io", "f, c");
       if (!regalloc_dry_run)
         emit2 ("goto", "!tlabel", labelKey2num (tlbl2->key));
       cost (3, 3);
@@ -3641,7 +3840,7 @@
               cheapMove (ASMOP_P, 0, result->aop, size - 1, true, true, true);
               emit2 ("mov", "a, #0x01");
               emit2 ("sl", "p");
-              emit2 ("t0sn", "f, c");
+              emit2 ("t0sn.io", "f, c");
               emit2 ("or", "p, a");
               emit2 ("src", "p");
               emit2 ("src", "p");
@@ -3651,7 +3850,7 @@
             {
               emit2 ("mov", "a, #0x01");
               emit2 ("sl", aopGet (result->aop, size - 1));
-              emit2 ("t0sn", "f, c");
+              emit2 ("t0sn.io", "f, c");
               emit2 ("or", "%s, a", aopGet (result->aop, size - 1));
               emit2 ("src", aopGet (result->aop, size - 1));
               emit2 ("src", aopGet (result->aop, size - 1));
@@ -3759,7 +3958,7 @@
       symbol *const tlbl = regalloc_dry_run ? 0 : newiTempLabel (0);
       emit2 ("ceqsn", "a, #0x%02x", 0x80 >> (8 - len));
       emit2 ("nop", "");
-      emit2 ("t0sn", "f, c");
+      emit2 ("t0sn.io", "f, c");
       if (tlbl)
         emit2 ("goto", "!tlabel", labelKey2num (tlbl->key));
       emit2 ("or", "a, #0x%02x", (0xff00 >> (8 - len)) & 0xff);
@@ -3801,10 +4000,12 @@
 
   if (left->aop->type == AOP_IMMD && ptype == GPOINTER && IS_SYMOP (left) && OP_SYMBOL (left)->remat)
     ptype = left->aop->aopu.code ? CPOINTER : POINTER;
+  else if (left->aop->type == AOP_STL)
+    ptype = POINTER;
 
   wassertl (aopIsLitVal (right->aop, 0, 2, 0x0000), "Unimplemented nonzero right operand in pointer read");
 
-  if (left->aop->type == AOP_IMMD && (ptype == POINTER || ptype == CPOINTER))
+  if (left->aop->type == AOP_IMMD && (ptype == POINTER || ptype == CPOINTER) || left->aop->type == AOP_LIT && operandLitValueUll(left) & 0x8000)
     {
       for (int i = 0; !bit_field ? i < size : blen > 0; i++, blen -= 8)
         {
@@ -3814,7 +4015,13 @@
               pushed_a = true;
             }
 
-          if (ptype == POINTER)
+          if (left->aop->type == AOP_LIT)
+            {
+              unsigned int litval = operandLitValueUll(left);
+              emit2 ("call", "#0x%04x", litval & (TARGET_IS_PDK13 ? 0x03ff : TARGET_IS_PDK14 ? 0x07ff : 0x0fff));
+              cost (1, 4);
+            }
+          else if (ptype == POINTER)
             {
               emit2 ("mov", "a, %s+%d", left->aop->aopu.immd, left->aop->aopu.immd_off + i);
               cost (1, 1);
@@ -3851,6 +4058,10 @@
       goto release;
     }
 #endif
+  else if (!bit_field && left->aop->type == AOP_STL && result->aop->type == AOP_STK) // Just a stack-to-stack copy
+    {
+      moveStackStack (result->aop->aopu.bytes[0].byteu.stk, left->aop->aopu.stk_off, size, regDead (A_IDX, ic));
+    }
   else if (ptype == POINTER) // Try to use efficient idxm when we know the source is in RAM.
     {
       const asmop *ptr_aop = (left->aop->type == AOP_DIR && TARGET_IS_PDK16) ? left->aop : ASMOP_P;
@@ -4061,7 +4272,11 @@
             }
         }
     }
-  if (right->aop->type == AOP_STK && !bit_field && left->aop->type != AOP_IMMD)
+  if (right->aop->type == AOP_STK && !bit_field && left->aop->type == AOP_STL)
+    {
+      moveStackStack (left->aop->aopu.stk_off, right->aop->aopu.bytes[0].byteu.stk, size, regDead (A_IDX, ic));
+    }
+  else if (right->aop->type == AOP_STK && !bit_field && left->aop->type != AOP_IMMD)
     {
       if (!regDead (A_IDX, ic))
         {
@@ -4087,6 +4302,10 @@
                   emit2 ("add", "a, #%d", i);
                   emit2 ("xch", "a, p");
                   cost (3, 3);
+                  if (G.p.type == AOP_STL)
+                    G.p.offset += i;
+                  else
+                    G.p.type = AOP_INVALID;
                 }
               else
                 for (int j = 0; j < i; j++)
@@ -4247,7 +4466,8 @@
                 }
               else if (bit_field && blen == 1)
                 {
-                  cheapMove (ASMOP_A, 0, right->aop, i, true, !ptr_aop || !aopInReg (ptr_aop, 0, P_IDX), true);
+                  if (!swapped)
+                    cheapMove (ASMOP_A, 0, right->aop, i, true, !ptr_aop || !aopInReg (ptr_aop, 0, P_IDX), true);
                   emit2 ("sr", "a");
                   cost (1, 1);
                   if (!ptr_aop)
@@ -4261,13 +4481,13 @@
                       cost (1, 2);
                     }
                   emit2 ("and", "a, #0x%02x", ~((0xff >> (8 - blen)) << bstr) & 0xff);
-                  emit2 ("t0sn", "f, c");
+                  emit2 ("t0sn.io", "f, c");
                   emit2 ("or", "a, #0x%02x", 1 << bstr);
                   cost (3, 3);
                 }
               else
                 {
-                  if (aopInReg (right->aop, i, A_IDX))
+                  if (aopInReg (right->aop, i, A_IDX) || aopInReg (right->aop, i, P_IDX) && swapped)
                     {
                       cost (100, 100);
                       wassert (regalloc_dry_run);
@@ -4295,7 +4515,11 @@
                   if (ptr_aop && aopInReg (ptr_aop, 0, P_IDX))
                     pushAF ();
                   if (!aopInReg (right->aop, i, P_IDX)) // xch above would already have brought it into a.
-                    cheapMove (ASMOP_A, 0, right->aop, i, true, false, true);
+                    {
+                      if (right->aop->type == AOP_STK)
+                        G.p.type = AOP_INVALID;
+                      cheapMove (ASMOP_A, 0, right->aop, i, true, false, true);
+                    }
                   if (bstr >= 4)
                     {
                       emit2 ("swap", "a");
@@ -4797,9 +5021,9 @@
   return (false);
 }
 
-/*---------------------------------------------------------------------*/
-/* genSTM8Code - generate code for STM8 for a single iCode instruction */
-/*---------------------------------------------------------------------*/
+/*-----------------------------------------------------------------------*/
+/* genPdkiCode - generate code for PADAUK for a single iCode instruction */
+/*-----------------------------------------------------------------------*/
 static void
 genPdkiCode (iCode *ic)
 {
@@ -4927,6 +5151,18 @@
     case GETABIT:
       wassertl (0, "Unimplemented iCode");
       break;
+      
+    case GETBYTE:
+      genGetByte (ic);
+      break;
+      
+    case GETWORD:
+      wassertl (0, "Unimplemented iCode");
+      break;
+      
+    case SWAP:
+      genSwap (ic);
+      break;
 
     case LEFT_OP:
       genLeftShift (ic);
@@ -5011,7 +5247,7 @@
 }
 
 /*---------------------------------------------------------------------*/
-/* genPdkCode - generate code for Padauk for a block of intructions    */
+/* genPdkCode - generate code for Padauk for a block of instructions   */
 /*---------------------------------------------------------------------*/
 void
 genPdkCode (iCode *lic)
@@ -5021,6 +5257,13 @@
   int cln = 0;
   regalloc_dry_run = false;
 
+  /* if debug information required */
+  if (options.debug && currFunc && !regalloc_dry_run)
+    debugFile->writeFunction (currFunc, lic);
+  
+  if (options.debug && !regalloc_dry_run)
+    debugFile->writeFrameAddress (NULL, NULL, 0); /* have no idea where frame is now */
+
   for (iCode *ic = lic; ic; ic = ic->next)
     {
       initGenLineElement ();
diff -Nru sdcc-4.0.0+dfsg/src/pdk/gen.h sdcc-4.2.0+dfsg/src/pdk/gen.h
--- sdcc-4.0.0+dfsg/src/pdk/gen.h	2019-09-26 20:31:10.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/pdk/gen.h	2020-07-29 09:45:51.000000000 +0000
@@ -85,6 +85,7 @@
 asmop;
 
 void genPdkCode (iCode *);
+void pdk_emitDebuggerSymbol (const char *);
 
 extern bool pdk_assignment_optimal;
 void pdk_init_asmops (void);
diff -Nru sdcc-4.0.0+dfsg/src/pdk/main.c sdcc-4.2.0+dfsg/src/pdk/main.c
--- sdcc-4.0.0+dfsg/src/pdk/main.c	2019-09-30 09:10:08.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/pdk/main.c	2021-08-08 17:13:19.000000000 +0000
@@ -26,6 +26,7 @@
 #include "dbuf_string.h"
 
 #include "ralloc.h"
+#include "gen.h"
 #include "peep.h"
 
 extern DEBUGFILE dwarf2DebugFile;
@@ -98,21 +99,20 @@
   if (options.stack_loc >= 0)
     {
       fprintf (of, "\tmov\ta, #0x%02x\n", options.stack_loc);
-      fprintf (of, "\tmov\tsp, a\n");
+      fprintf (of, "\tmov.io\tsp, a\n");
     }
   else
     {
       fprintf (of, "\tmov\ta, #s_OSEG\n");
       fprintf (of, "\tadd\ta, #l_OSEG + 1\n");
       fprintf (of, "\tand\ta, #0xfe\n");
-      fprintf (of, "\tmov\tsp, a\n");
+      fprintf (of, "\tmov.io\tsp, a\n");
     }
 
   fprintf (of, "\tcall\t__sdcc_external_startup\n");
-  fprintf (of, "\tgoto\t__sdcc_gs_init_startup\n");
+  fprintf (of, "\tgoto\ts_GSINIT\n");
 
   tfprintf (of, "\t!area\n", STATIC_NAME);
-  fprintf (of, "__sdcc_gs_init_startup:\n");
 
   /* Init static & global variables */
   fprintf (of, "__sdcc_init_data:\n");
@@ -136,6 +136,8 @@
 pdk_init (void)
 {
   asm_addTree (&asm_asxxxx_smallpdk_mapping);
+
+  pdk_init_asmops();
 }
 
 static void
@@ -200,7 +202,7 @@
 static bool
 hasExtBitOp (int op, int size)
 {
-  return (false);
+  return (op == GETBYTE || op == SWAP && size == 1);
 }
 
 static const char *
@@ -268,6 +270,8 @@
     0,
     pdknotUsedFrom,
     0,
+    0,
+    0,
   },
   /* Sizes: char, short, int, long, long long, ptr, fptr, gptr, bit, float, max */
   {
@@ -314,6 +318,7 @@
     1                           /* No fancy alignments supported. */
   },
   { 0, 0 },
+  0,                            /* ABI revision */
   {                             /* stack information */
      +1,                        /* direction: stack grows up */
      0,
@@ -324,7 +329,7 @@
      1,                         /* sp points to next free stack location */
   },     
   { -1, false },                /* no int x int -> long multiplication support routine. */
-  { 0,
+  { pdk_emitDebuggerSymbol,
     {
       0,
       0,                        /* cfiSame */
@@ -480,6 +485,7 @@
     1                           /* No fancy alignments supported. */
   },
   { 0, 0 },
+  0,                            /* ABI revision */
   {                             /* stack information */
      +1,                        /* direction: stack grows up */
      0,
@@ -490,7 +496,7 @@
      1,                         /* sp points to next free stack location */
   },     
   { -1, false },                /* no int x int -> long multiplication support routine. */
-  { 0,
+  { pdk_emitDebuggerSymbol,
     {
       0,
       0,                        /* cfiSame */
@@ -646,6 +652,7 @@
     1                           /* No fancy alignments supported. */
   },
   { 0, 0 },
+  0,                            /* ABI revision */
   {                             /* stack information */
      +1,                        /* direction: stack grows up */
      0,
@@ -656,7 +663,7 @@
      1,                         /* sp points to next free stack location */
   },     
   { -1, false },                /* no int x int -> long multiplication support routine. */
-  { 0,
+  { pdk_emitDebuggerSymbol,
     {
       0,
       0,                        /* cfiSame */
diff -Nru sdcc-4.0.0+dfsg/src/pdk/peep.c sdcc-4.2.0+dfsg/src/pdk/peep.c
--- sdcc-4.0.0+dfsg/src/pdk/peep.c	2019-06-10 18:09:35.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/pdk/peep.c	2021-07-25 22:35:23.000000000 +0000
@@ -140,13 +140,11 @@
 
   /* 3. search lineNode with label definition and return it */
   for (cpl = _G.head; cpl; cpl = cpl->next)
-    {
-      if (   cpl->isLabel
-          && strncmp (p, cpl->line, strlen(p)) == 0)
-        {
-          return cpl;
-        }
-    }
+    if (cpl->isLabel &&
+      strncmp (p, cpl->line, strlen(p)) == 0 &&
+      cpl->line[strlen(p)] == ':')
+        return cpl;
+
   return NULL;
 }
 
@@ -175,7 +173,7 @@
   if (ISINST (pl->line, "push") && argIs (pl->line + 4, "af") || ISINST (pl->line, "pushaf"))
     return true;
 
-  if (ISINST (pl->line, "t0sn") || ISINST (pl->line, "t1sn"))
+  if (ISINST (pl->line, "t0sn.io") || ISINST (pl->line, "t1sn.io"))
     return argIs(strchr (pl->line, ','), what);
 
   if(ISINST (pl->line, "addc") ||
@@ -208,7 +206,8 @@
   if (ISINST(pl->line, "ret"))
     return isReturned(what);
 
-  if (ISINST(pl->line, "mov"))
+  if (ISINST(pl->line, "mov") ||
+    ISINST(pl->line, "mov.io"))
     return argIs (strchr (pl->line, ','), what);
 
   if (ISINST (pl->line, "push") && argIs (pl->line + 4, "af") || ISINST (pl->line, "pushaf"))
@@ -224,7 +223,8 @@
   if (ISINST(pl->line, "idxm"))
     return argIs (pl->line + 4, what) || argIs (strchr (pl->line, ','), what);
   if (ISINST (pl->line, "ceqsn") ||
-    ISINST (pl->line, "cneqsn"))
+    ISINST (pl->line, "cneqsn") ||
+    ISINST (pl->line, "xor.io"))
     return argIs (pl->line + 6, what) || argIs (strchr (pl->line, ','), what);
 
   // One-operand instructions
@@ -277,12 +277,17 @@
     ISINST (pl->line, "neg") ||
     ISINST (pl->line, "not") ||
     ISINST (pl->line, "or") ||
-    ISINST (pl->line, "xor"))
+    ISINST (pl->line, "xor") ||
+    ISINST (pl->line, "xor.io"))
       return !strcmp(what, "z");
 
   // mov writes z when the destination is a and hte source not an immediate only.
-  if (ISINST (pl->line, "mov") && !strcmp(what, "z") && pl->line[4] == 'a' && pl->line[5] == ',' && !strchr(pl->line, '#'))
-    return true;
+  if (!strcmp(what, "z") && !strchr(pl->line, '#'))
+    {
+      if ( (ISINST (pl->line, "mov") && pl->line[4] == 'a' && pl->line[5] == ',') ||
+         (ISINST (pl->line, "mov.io") && pl->line[7] == 'a' && pl->line[8] == ','))
+        return true;
+    }
 
   return false;
 }
@@ -295,6 +300,8 @@
 
   if (ISINST(pl->line, "mov") || ISINST(pl->line, "idxm"))
     return argIs (pl->line + 4, what);
+  if (ISINST(pl->line, "mov.io"))
+    return argIs (pl->line + 7, what);
 
   if (ISINST (pl->line, "pop") && argIs (pl->line + 4, "af") || ISINST (pl->line, "popaf"))
     return !strcmp(what, "a");
@@ -329,6 +336,7 @@
 {
   return (ISINST(pl->line, "ceqsn") || ISINST(pl->line, "cneqsn") ||
     ISINST(pl->line, "t0sn") || ISINST(pl->line, "t1sn") ||
+    ISINST(pl->line, "t0sn.io") || ISINST(pl->line, "t1sn.io") ||
     ISINST(pl->line, "izsn") || ISINST(pl->line, "dzsn"));
 }
 
diff -Nru sdcc-4.0.0+dfsg/src/pdk/peeph.def sdcc-4.2.0+dfsg/src/pdk/peeph.def
--- sdcc-4.0.0+dfsg/src/pdk/peeph.def	2019-09-21 10:44:41.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/pdk/peeph.def	2021-07-25 22:35:23.000000000 +0000
@@ -1,7 +1,7 @@
 // peeph.def - PDK peephole rules
 
 replace restart {
-	mov	%1, %2
+	mo%3	%1, %2
 } by {
 	; peephole 0 removed dead load into %1 from %2.
 } if notUsed(%1), notVolatile(%1), notVolatile(%2)
@@ -13,10 +13,10 @@
 } if notUsed(%1)
 
 replace restart {
-	mov	%1, a
-	mov	a, %1
+	mo%3	%1, a
+	mo%3	a, %1
 } by {
-	mov	%1, a
+	mo%3	%1, a
 	; peephole 2 removed redundant load from %1 into a.
 } if notVolatile(%1)
 
@@ -29,7 +29,7 @@
 
 
 replace restart {
-	mov	a, #%1
+	mo%3	a, #%1
 	ret
 } by {
 	; peephole 4 moved load to ret.
@@ -44,11 +44,11 @@
 } if notVolatile(%1)
 
 replace restart {
-	mov	a, #0x00
+	mo%3	a, #0x00
 	slc	a
 	and	a, #0x01
 } by {
-	mov	a, #0x00
+	mo%3	a, #0x00
 	slc	a
 	; peephole 6 removed redundant and.
 }
diff -Nru sdcc-4.0.0+dfsg/src/pdk/ralloc2.cc sdcc-4.2.0+dfsg/src/pdk/ralloc2.cc
--- sdcc-4.0.0+dfsg/src/pdk/ralloc2.cc	2019-09-27 13:20:27.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/pdk/ralloc2.cc	2021-03-18 19:32:59.000000000 +0000
@@ -139,7 +139,8 @@
   bool left_dir = IS_TRUE_SYMOP (left) || IS_ITEMP (left) && !(options.stackAuto || reentrant) && !left_in_A;
   bool right_dir = IS_TRUE_SYMOP (right) || IS_ITEMP (right) && !(options.stackAuto || reentrant) && !right_in_A;
 
-  if (ic->op == '=' || ic->op == DUMMY_READ_VOLATILE || ic->op == CAST || ic->op == GET_VALUE_AT_ADDRESS || ic->op == SET_VALUE_AT_ADDRESS)
+  // For some iCodes, code generation can handle anything.
+  if (ic->op == GETBYTE || ic->op == '=' || ic->op == DUMMY_READ_VOLATILE || ic->op == CAST || ic->op == GET_VALUE_AT_ADDRESS || ic->op == SET_VALUE_AT_ADDRESS || ic->op == '~' || ic->op == '|' || ic->op == '^' || ic->op == BITWISEAND && !ifxForOp (result, ic))
     return(true);
 
   if(result && IS_ITEMP(result) && OP_SYMBOL_CONST(result)->remat && !operand_in_reg(result, REG_A, ia, i, G) && !operand_in_reg(result, REG_P, ia, i, G))
@@ -522,7 +523,7 @@
   iCode *ifx;
 
   // - can only jump on nonzero result for decrement of register / direct variable.
-  if(ic->op == '-' && ic->next && ic->next->op == IFX && IC_TRUE(ic->next) && IC_COND (ic->next)->key == IC_RESULT(ic)->key)
+  if(ic->op == '-' && ic->next && ic->next->op == IFX && IC_COND (ic->next)->key == IC_RESULT(ic)->key)
     {
       ifx = ic->next;
 
@@ -538,9 +539,6 @@
       if (!isOperandEqual (IC_RESULT(ic), IC_LEFT(ic)))
         return;
 
-      if (getSize(operandType(IC_RESULT(ic))) > 2)
-        return;
-
       ifx->generated = true;
       return;
     }
diff -Nru sdcc-4.0.0+dfsg/src/pdk/ralloc.c sdcc-4.2.0+dfsg/src/pdk/ralloc.c
--- sdcc-4.0.0+dfsg/src/pdk/ralloc.c	2019-09-27 17:15:57.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/pdk/ralloc.c	2021-06-29 16:13:13.000000000 +0000
@@ -349,8 +349,25 @@
     || !isOperandGlobal (IC_RIGHT (dic)))
     return 0;
 
-  if (IS_OP_VOLATILE (IC_RESULT (ic)) && IS_OP_VOLATILE (IC_RIGHT (dic)))
-    return 0;
+  if (IS_OP_VOLATILE (IC_RESULT (ic)) && IS_OP_VOLATILE (IC_RIGHT (dic))) // Only case with two volatiles that we can optimize: Some bitwise operation on __sfr.
+    {
+      if (ic->op != BITWISEAND && ic->op != '|' && ic->op != '^' || operandSize (IC_LEFT (ic)) != 1 || !IS_OP_LITERAL (IC_RIGHT (ic)))
+        return 0;
+
+      if (!OP_SYMBOL (IC_RESULT (ic)) || !IN_REGSP (SPEC_OCLS (OP_SYMBOL (IC_RESULT (ic))->etype)))
+        return 0;
+  
+      if (OP_SYMBOL (IC_RIGHT (dic))->key != OP_SYMBOL (IC_RESULT (ic))->key)
+        return 0;
+
+      unsigned int val = operandLitValueUll (IC_RIGHT (ic));
+      if (ic->op == BITWISEAND)
+        val = ~val;
+      val &= 0xff;
+
+      if(ic->op != '^' && val != 0x01 && val != 0x02 && val != 0x04 && val != 0x08 && val != 0x10 && val != 0x20 && val != 0x40 && val != 0x80)
+        return 0;
+    }
 
   /* also make sure the intervenening instructions
      don't have any thing in far space */
@@ -706,8 +723,6 @@
   int count = ebbi->count;
   iCode *ic;
 
-  pdk_init_asmops();
-
   transformPointerSet (ebbs, count);
 
   /* change assignments this will remove some
diff -Nru sdcc-4.0.0+dfsg/src/pic14/gen.c sdcc-4.2.0+dfsg/src/pic14/gen.c
--- sdcc-4.0.0+dfsg/src/pic14/gen.c	2019-10-14 11:33:28.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/pic14/gen.c	2021-06-08 11:45:18.000000000 +0000
@@ -5077,39 +5077,6 @@
 }
 
 /*-----------------------------------------------------------------*/
-/* genGetHbit - generates code get highest order bit               */
-/*-----------------------------------------------------------------*/
-static void
-genGetHbit (iCode * ic)
-{
-  operand *left, *result;
-  left = IC_LEFT (ic);
-  result = IC_RESULT (ic);
-  aopOp (left, ic, FALSE);
-  aopOp (result, ic, FALSE);
-
-  FENTRY;
-  DEBUGpic14_emitcode ("; ***", "%s  %d", __FUNCTION__, __LINE__);
-  /* get the highest order byte into a */
-  MOVA (aopGet (AOP (left), AOP_SIZE (left) - 1, FALSE, FALSE));
-  if (AOP_TYPE (result) == AOP_CRY)
-    {
-      pic14_emitcode ("rlc", "a");
-      pic14_outBitC (result);
-    }
-  else
-    {
-      pic14_emitcode ("rl", "a");
-      pic14_emitcode ("anl", "a,#0x01");
-      pic14_outAcc (result);
-    }
-
-
-  freeAsmop (left, NULL, ic, TRUE);
-  freeAsmop (result, NULL, ic, TRUE);
-}
-
-/*-----------------------------------------------------------------*/
 /* AccLsh - shift left accumulator by known count                  */
 /* MARK: pic14 always rotates through CARRY!                       */
 /*-----------------------------------------------------------------*/
@@ -7893,10 +7860,6 @@
           genGetABit (ic);
           break;
 
-        case GETHBIT:
-          genGetHbit (ic);
-          break;
-
         case LEFT_OP:
           genLeftShift (ic);
           break;
diff -Nru sdcc-4.0.0+dfsg/src/pic14/glue.c sdcc-4.2.0+dfsg/src/pic14/glue.c
--- sdcc-4.0.0+dfsg/src/pic14/glue.c	2019-10-14 11:33:28.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/pic14/glue.c	2021-07-05 00:58:42.000000000 +0000
@@ -437,7 +437,7 @@
   dbuf_printf (vBuf, "; reset vector \n");
   dbuf_printf (vBuf, "%s", iComments2);
   // Lkr file should place section STARTUP at address 0x0, but does not ...
-  dbuf_printf (vBuf, "STARTUP\t%s 0x0000\n", CODE_NAME);
+  dbuf_printf (vBuf, "STARTUP\t%s 0x%04X\n", CODE_NAME, options.code_loc);
   dbuf_printf (vBuf, "\tnop\n");        /* first location for used by incircuit debugger */
   dbuf_printf (vBuf, "\tpagesel __sdcc_gsinit_startup\n");
   dbuf_printf (vBuf, "\tgoto\t__sdcc_gsinit_startup\n");
@@ -655,7 +655,7 @@
       // Note - for mplink may have to enlarge section vectors in .lnk file
       // Note: Do NOT name this code_interrupt to avoid nameclashes with
       //       source files's code segment (interrupt.c -> code_interrupt)
-      fprintf (asmFile, "c_interrupt\t%s\t0x0004\n", CODE_NAME);
+      fprintf (asmFile, "c_interrupt\t%s\t0x%04X\n", CODE_NAME, options.code_loc+4);
 
       /* interrupt service routine */
       fprintf (asmFile, "__sdcc_interrupt:\n");
@@ -743,7 +743,7 @@
 
   if (!(asmFile = fopen (buffer, "w")))
     {
-      werror (E_FILE_OPEN_ERR, buffer);
+      werror (E_OUTPUT_FILE_OPEN_ERR, buffer, strerror (errno));
       exit (1);
     }
 
@@ -1987,7 +1987,7 @@
       else
         {
           ast *ast = newAst_VALUE (constVal ("0"));
-          ast = decorateType (ast, RESULT_TYPE_NONE);
+          ast = decorateType (ast, RESULT_TYPE_NONE, true);
           ilist = newiList (INIT_NODE, ast);
         }
       DBG_ILIST ("ilist substituted", ilist);
diff -Nru sdcc-4.0.0+dfsg/src/pic14/main.c sdcc-4.2.0+dfsg/src/pic14/main.c
--- sdcc-4.0.0+dfsg/src/pic14/main.c	2019-06-06 09:43:54.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/pic14/main.c	2021-08-08 17:13:19.000000000 +0000
@@ -69,7 +69,7 @@
 };
 
 static int regParmFlg = 0;  /* determine if we can register a parameter */
-
+static struct sym_link *regParmFuncType;
 
 /** $1 is always the basename.
     $2 is always the output file.
@@ -100,11 +100,15 @@
 _pic14_reset_regparm (struct sym_link *funcType)
 {
   regParmFlg = 0;
+  regParmFuncType = funcType;
 }
 
 static int
 _pic14_regparm (sym_link * l, bool reentrant)
 {
+  if (IFFUNC_HASVARARGS (regParmFuncType))
+    return 0;
+
 /* for this processor it is simple
   can pass only the first parameter in a register */
   //if (regParmFlg)
@@ -250,7 +254,6 @@
   if (op == RRC
     || op == RLC
     || op == GETABIT
-    /* || op == GETHBIT */ /* GETHBIT doesn't look complete for PIC */
     )
     return TRUE;
   else
@@ -420,6 +423,7 @@
     1                       // No fancy alignments supported.
   },
   { NULL, NULL },
+  0,                        // ABI revision
   {
     +1, 1, 4, 1, 1, 0, 0
   },
diff -Nru sdcc-4.0.0+dfsg/src/pic14/pcode.c sdcc-4.2.0+dfsg/src/pic14/pcode.c
--- sdcc-4.0.0+dfsg/src/pic14/pcode.c	2019-10-14 11:33:28.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/pic14/pcode.c	2020-05-18 08:57:45.000000000 +0000
@@ -2158,10 +2158,10 @@
 		char buffer[200];
 
 		/* create the file name */
-                SNPRINTF(buffer, sizeof(buffer), "%s.p", dstFileName);
+		SNPRINTF(buffer, sizeof(buffer), "%s.p", dstFileName);
 
 		if( !(pFile = fopen(buffer, "w" ))) {
-			werror(E_FILE_OPEN_ERR,buffer);
+			werror(E_OUTPUT_FILE_OPEN_ERR, buffer, strerror(errno));
 			exit(1);
 		}
 
@@ -5275,7 +5275,7 @@
 	pBlock  *pb;
 
 	if(!picIsInitialized()) {
-		werror(E_FILE_OPEN_ERR, "no memory size is known for this processor");
+		werror(E_UNKNOWN_TARGET, "no memory size is known for this processor");
 		exit(1);
 	}
 	
diff -Nru sdcc-4.0.0+dfsg/src/pic14/ralloc.c sdcc-4.2.0+dfsg/src/pic14/ralloc.c
--- sdcc-4.0.0+dfsg/src/pic14/ralloc.c	2019-10-14 11:33:28.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/pic14/ralloc.c	2021-06-08 11:45:18.000000000 +0000
@@ -105,7 +105,7 @@
 
                 if (!(debugF = fopen (buffer, (append ? "a+" : "w"))))
                 {
-                        werror (E_FILE_OPEN_ERR, buffer);
+                        werror (E_OUTPUT_FILE_OPEN_ERR, buffer, strerror (errno));
                         exit (1);
                 }
 
@@ -247,7 +247,6 @@
         case GET_VALUE_AT_ADDRESS:      return "GET_VALUE_AT_ADDRESS";
         case SPIL:                      return "SPIL";
         case UNSPIL:                    return "UNSPIL";
-        case GETHBIT:                   return "GETHBIT";
         case BITWISEAND:                return "BITWISEAND";
         case UNARYMINUS:                return "UNARYMINUS";
         case IPUSH:                     return "IPUSH";
diff -Nru sdcc-4.0.0+dfsg/src/pic16/gen.c sdcc-4.2.0+dfsg/src/pic16/gen.c
--- sdcc-4.0.0+dfsg/src/pic16/gen.c	2018-03-25 18:13:56.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/pic16/gen.c	2021-06-08 11:45:18.000000000 +0000
@@ -1486,7 +1486,7 @@
   cfunc = currFunc;
   currFunc = NULL;
 
-  i = bitVectFirstBit (f);
+  i = bitVectFirstBit (f) + 1;
   while (i < 128)
     {
 
@@ -7228,42 +7228,6 @@
   pic16_freeAsmop (result, NULL, ic, TRUE);
 }
 
-
-/* gpasm can get the highest order bit with HIGH/UPPER
- * so the following probably is not needed -- VR */
-
-/*-----------------------------------------------------------------*/
-/* genGetHbit - generates code get highest order bit               */
-/*-----------------------------------------------------------------*/
-static void
-genGetHbit (iCode * ic)
-{
-  operand *left, *result;
-  left = IC_LEFT (ic);
-  result = IC_RESULT (ic);
-  pic16_aopOp (left, ic, FALSE);
-  pic16_aopOp (result, ic, FALSE);
-
-  DEBUGpic16_emitcode ("; ***", "%s  %d", __FUNCTION__, __LINE__);
-  /* get the highest order byte into a */
-  MOVA (pic16_aopGet (AOP (left), AOP_SIZE (left) - 1, FALSE, FALSE));
-  if (AOP_TYPE (result) == AOP_CRY)
-    {
-      pic16_emitcode ("rlc", "a");
-      pic16_outBitC (result);
-    }
-  else
-    {
-      pic16_emitcode ("rl", "a");
-      pic16_emitcode ("anl", "a,#0x01");
-      pic16_outAcc (result);
-    }
-
-
-  pic16_freeAsmop (left, NULL, ic, TRUE);
-  pic16_freeAsmop (result, NULL, ic, TRUE);
-}
-
 static void
 genGetABit (iCode * ic)
 {
@@ -11498,10 +11462,6 @@
           genGetABit (ic);
           break;
 
-        case GETHBIT:
-          genGetHbit (ic);
-          break;
-
         case LEFT_OP:
           genLeftShift (ic);
           break;
diff -Nru sdcc-4.0.0+dfsg/src/pic16/glue.c sdcc-4.2.0+dfsg/src/pic16/glue.c
--- sdcc-4.0.0+dfsg/src/pic16/glue.c	2016-04-10 09:42:37.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/pic16/glue.c	2021-07-05 00:58:42.000000000 +0000
@@ -382,7 +382,7 @@
       return valCastLiteral(toType, 0.0, 0);
   }
 
-  expr = decorateType(resolveSymbols( list2expr (ilist) ), FALSE);
+  expr = decorateType(resolveSymbols( list2expr (ilist) ), FALSE, true);
 //  expr = list2expr( ilist );
 
   if (!expr)
@@ -1179,7 +1179,7 @@
       else
         {
           ast *ast = newAst_VALUE (constVal("0"));
-          ast = decorateType (ast, RESULT_TYPE_NONE);
+          ast = decorateType (ast, RESULT_TYPE_NONE, true);
           ilist = newiList(INIT_NODE, ast);
         }
     }
@@ -1846,7 +1846,7 @@
     }
 
     if(!(asmFile = fopen (buffer, "w"))) {
-      werror (E_FILE_OPEN_ERR, buffer);
+      werror (E_OUTPUT_FILE_OPEN_ERR, buffer, strerror (errno));
       exit (1);
     }
 
diff -Nru sdcc-4.0.0+dfsg/src/pic16/main.c sdcc-4.2.0+dfsg/src/pic16/main.c
--- sdcc-4.0.0+dfsg/src/pic16/main.c	2018-03-24 16:33:15.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/pic16/main.c	2021-08-08 17:13:19.000000000 +0000
@@ -84,6 +84,7 @@
 int has_xinst_config = 0;
 
 static int regParmFlg = 0;  /* determine if we can register a parameter */
+static struct sym_link *regParmFuncType;
 
 pic16_options_t pic16_options;
 pic16_config_options_t *pic16_config_options;
@@ -113,11 +114,15 @@
 _pic16_reset_regparm (struct sym_link *funcType)
 {
   regParmFlg = 0;
+  regParmFuncType = funcType;
 }
 
 static int
 _pic16_regparm (sym_link * l, bool reentrant)
 {
+  if (IFFUNC_HASVARARGS (regParmFuncType))
+    return 0;
+
   /* force all parameters via SEND/RECEIVE */
   if(0 /*pic16_options.ip_stack*/) {
     /* for this processor it is simple
@@ -1229,7 +1234,6 @@
   if (op == RRC
       || op == RLC
       || op == GETABIT
-      /* || op == GETHBIT */ /* GETHBIT doesn't look complete for PIC */
      )
     return TRUE;
   else
@@ -1314,7 +1318,7 @@
     2,      /* near ptr */
     3,      /* far ptr, far pointers (see Microchip) */
     3,      /* gptr */
-    2,      /* func ptr */
+    3,      /* func ptr */
     3,      /* banked func ptr */
     1,      /* bit */
     4,      /* float */
@@ -1359,6 +1363,7 @@
     NULL,       /* genExtraAreaDeclaration */
     NULL        /* genExatrAreaLinkOptions */
   },
+  0,            /* ABI revision */
   {
     /* stack related information */
     -1,         /* -1 stack grows downwards, +1 upwards */
diff -Nru sdcc-4.0.0+dfsg/src/pic16/pcode.c sdcc-4.2.0+dfsg/src/pic16/pcode.c
--- sdcc-4.0.0+dfsg/src/pic16/pcode.c	2016-04-10 09:42:37.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/pic16/pcode.c	2020-05-18 08:57:45.000000000 +0000
@@ -3561,7 +3561,7 @@
     SNPRINTF(buffer, sizeof(buffer), "%s.p", dstFileName);
 
     if(!(pFile = fopen(buffer, "w" ))) {
-      werror(E_FILE_OPEN_ERR,buffer);
+      werror(E_OUTPUT_FILE_OPEN_ERR, buffer, strerror(errno));
       exit(1);
     }
 
diff -Nru sdcc-4.0.0+dfsg/src/pic16/ralloc.c sdcc-4.2.0+dfsg/src/pic16/ralloc.c
--- sdcc-4.0.0+dfsg/src/pic16/ralloc.c	2019-06-29 04:30:58.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/pic16/ralloc.c	2021-06-08 11:45:18.000000000 +0000
@@ -134,7 +134,7 @@
 
       if (!(debugF = fopen (buffer, (append ? "a+" : "w"))))
         {
-          werror (E_FILE_OPEN_ERR, buffer);
+          werror (E_OUTPUT_FILE_OPEN_ERR, buffer, strerror (errno));
           exit (1);
         }
       append = 1;               // Next time debubLog is called, we'll append the debug info
@@ -288,7 +288,6 @@
                 case GET_VALUE_AT_ADDRESS:      return "GET_VALUE_AT_ADDRESS";
                 case SPIL:              return "SPIL";
                 case UNSPIL:            return "UNSPIL";
-                case GETHBIT:           return "GETHBIT";
                 case BITWISEAND:        return "BITWISEAND";
                 case UNARYMINUS:        return "UNARYMINUS";
                 case IPUSH:             return "IPUSH";
diff -Nru sdcc-4.0.0+dfsg/src/port.h sdcc-4.2.0+dfsg/src/port.h
--- sdcc-4.0.0+dfsg/src/port.h	2019-03-14 16:34:34.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/port.h	2022-01-09 00:54:25.000000000 +0000
@@ -11,7 +11,7 @@
 #include "dbuf.h"
 
 #define TARGET_ID_MCS51    1
-#define TARGET_ID_GBZ80    2
+#define TARGET_ID_SM83     2
 #define TARGET_ID_Z80      3
 #define TARGET_ID_AVR      4
 #define TARGET_ID_DS390    5
@@ -30,6 +30,10 @@
 #define TARGET_ID_PDK14    20
 #define TARGET_ID_PDK15    21
 #define TARGET_ID_PDK16    22
+#define TARGET_ID_Z80N     23
+#define TARGET_ID_R2KA     24
+#define TARGET_ID_MOS6502  25
+#define TARGET_ID_MOS65C02 26
 
 /* Macro to test the target we are compiling for.
    Can only be used after SDCCmain has defined the port
@@ -43,10 +47,12 @@
 #define TARGET_IS_Z80      (port->id == TARGET_ID_Z80)
 #define TARGET_IS_Z180     (port->id == TARGET_ID_Z180)
 #define TARGET_IS_R2K      (port->id == TARGET_ID_R2K)
+#define TARGET_IS_R2KA     (port->id == TARGET_ID_R2KA)
 #define TARGET_IS_R3KA     (port->id == TARGET_ID_R3KA)
-#define TARGET_IS_GBZ80    (port->id == TARGET_ID_GBZ80)
+#define TARGET_IS_SM83     (port->id == TARGET_ID_SM83)
 #define TARGET_IS_TLCS90   (port->id == TARGET_ID_TLCS90)
 #define TARGET_IS_EZ80_Z80 (port->id == TARGET_ID_EZ80_Z80)
+#define TARGET_IS_Z80N     (port->id == TARGET_ID_Z80N)
 #define TARGET_IS_HC08     (port->id == TARGET_ID_HC08)
 #define TARGET_IS_S08      (port->id == TARGET_ID_S08)
 #define TARGET_IS_STM8     (port->id == TARGET_ID_STM8)
@@ -54,13 +60,16 @@
 #define TARGET_IS_PDK14    (port->id == TARGET_ID_PDK14)
 #define TARGET_IS_PDK15    (port->id == TARGET_ID_PDK15)
 #define TARGET_IS_PDK16    (port->id == TARGET_ID_PDK16)
+#define TARGET_IS_MOS6502  (port->id == TARGET_ID_MOS6502)
+#define TARGET_IS_MOS65C02 (port->id == TARGET_ID_MOS65C02)
 
 #define TARGET_MCS51_LIKE  (TARGET_IS_MCS51 || TARGET_IS_DS390 || TARGET_IS_DS400)
-#define TARGET_Z80_LIKE    (TARGET_IS_Z80 || TARGET_IS_Z180 || TARGET_IS_GBZ80 || TARGET_IS_R2K || TARGET_IS_R3KA || TARGET_IS_TLCS90 || TARGET_IS_EZ80_Z80)
-#define TARGET_IS_RABBIT   (TARGET_IS_R2K || TARGET_IS_R3KA)
+#define TARGET_Z80_LIKE    (TARGET_IS_Z80 || TARGET_IS_Z180 || TARGET_IS_SM83 || TARGET_IS_R2K || TARGET_IS_R2KA || TARGET_IS_R3KA || TARGET_IS_TLCS90 || TARGET_IS_EZ80_Z80 || TARGET_IS_Z80N)
+#define TARGET_IS_RABBIT   (TARGET_IS_R2K || TARGET_IS_R2KA || TARGET_IS_R3KA)
 #define TARGET_HC08_LIKE   (TARGET_IS_HC08 || TARGET_IS_S08)
 #define TARGET_PIC_LIKE    (TARGET_IS_PIC14 || TARGET_IS_PIC16)
 #define TARGET_PDK_LIKE    (TARGET_IS_PDK13 || TARGET_IS_PDK14 || TARGET_IS_PDK15 || TARGET_IS_PDK16)
+#define TARGET_MOS6502_LIKE  (TARGET_IS_MOS6502 || TARGET_IS_MOS65C02)
 
 /* is using sdas / sdld assembler / linker */
 #define IS_SDASLD          (TARGET_Z80_LIKE || TARGET_MCS51_LIKE || TARGET_HC08_LIKE)
@@ -171,7 +180,9 @@
     bool (*notUsed) (const char *reg, lineNode * currPl, lineNode * head);
     bool (*canAssign) (const char *op1, const char *op2, const char *op3);
     bool (*notUsedFrom) (const char *reg, const char *label, lineNode *head);
-    bool (*symmParmStack) (void);
+    bool (*symmParmStack) (const char *name);
+    bool (*canJoinRegs) (const char **regs, char dst[20]);
+    bool (*canSplitReg) (const char *reg, char dst[][16], int nDst);
   }
   peep;
 
@@ -208,13 +219,8 @@
   {
     const char *const xstack_name;
     const char *const istack_name;
-    /*
-     * The following 2 items can't be const pointers
-     * due to ugly implementation in gbz80 target;
-     * this should be fixed in src/z80/main.c (borutr)
-     */
-    const char *code_name;
-    const char *data_name;
+    const char *const code_name;
+    const char *const data_name;
     const char *const idata_name;
     const char *const pdata_name;
     const char *const xdata_name;
@@ -246,6 +252,9 @@
   }
   extraAreas;
 
+  /* Default ABI version */
+  unsigned sdcccall;
+
   /* stack related information */
   struct
   {
@@ -377,7 +386,7 @@
   bool (*hasNativeMulFor) (iCode *ic, sym_link *left, sym_link *right);
 
   /** Returns true if the port has implemented certain bit
-      manipulation iCodes (RRC, RLC, SWAP, GETHBIT, GETABIT, GETBYTE, GETWORD)
+      manipulation iCodes (RRC, RLC, SWAP, GETABIT, GETBYTE, GETWORD)
    */
   bool (*hasExtBitOp) (int op, int size);
 
@@ -430,13 +439,16 @@
 extern PORT z180_port;
 #endif
 #if !OPT_DISABLE_R2K
-extern PORT r2k_port;  /* Rabbit 2000/3000 */
+extern PORT r2k_port;  // Rabbit 2000
+#endif
+#if !OPT_DISABLE_R2KA
+extern PORT r2ka_port; // Rabbit 2000A, 2000C, 2000C, 3000
 #endif
 #if !OPT_DISABLE_R3KA
-extern PORT r3ka_port; /* Rabbit 3000A */
+extern PORT r3ka_port; // Rabbit 3000A
 #endif
-#if !OPT_DISABLE_GBZ80
-extern PORT gbz80_port;
+#if !OPT_DISABLE_SM83
+extern PORT sm83_port;
 #endif
 #if !OPT_DISABLE_TLCS90
 extern PORT tlcs90_port;
@@ -444,6 +456,9 @@
 #if !OPT_DISABLE_EZ80_Z80
 extern PORT ez80_z80_port;
 #endif
+#if !OPT_DISABLE_Z80N
+extern PORT z80n_port;
+#endif
 #if !OPT_DISABLE_AVR
 extern PORT avr_port;
 #endif
@@ -480,5 +495,11 @@
 #if !OPT_DISABLE_PDK15
 extern PORT pdk15_port;
 #endif
+#if !OPT_DISABLE_MOS6502
+extern PORT mos6502_port;
+#endif
+#if !OPT_DISABLE_MOS65C02
+extern PORT mos65c02_port;
+#endif
 
 #endif /* PORT_INCLUDE */
diff -Nru sdcc-4.0.0+dfsg/src/SDCCasm.c sdcc-4.2.0+dfsg/src/SDCCasm.c
--- sdcc-4.0.0+dfsg/src/SDCCasm.c	2019-03-14 16:34:34.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/SDCCasm.c	2020-07-31 18:57:58.000000000 +0000
@@ -434,7 +434,8 @@
    "; ---------------------------------"},
   {"functionlabeldef", "%s:"},
   {"globalfunctionlabeldef", "%s::"},
-  {"bankimmeds", "0     ; PENDING: bank support"},
+  {"bankimmeds", "b%s"},
+  {"hashedbankimmeds", "#b%s"},
   {"los", "(%s & 0xFF)"},
   {"his", "(%s >> 8)"},
   {"hihis", "(%s >> 16)"},
@@ -448,6 +449,7 @@
   {"hihil", "(%05d$ >> 16)"},
   {"hihihil", "(%05d$ >> 24)"},
   {"equ", "="},
+  {"bequ", "b%s = %i"},
   {"org", ".org 0x%04X"},
   {NULL, NULL}
 };
@@ -486,7 +488,8 @@
    "; ---------------------------------"},
   {"functionlabeldef", "%s:"},
   {"globalfunctionlabeldef", "%s::"},
-  {"bankimmeds", "0     ; PENDING: bank support"},
+  {"bankimmeds", "b%s"},
+  {"hashedbankimmeds", "#b%s"},
   {"los", "(%s & 0xFF)"},
   {"his", "(%s >> 8)"},
   {"hihis", "(%s >> 16)"},
@@ -504,10 +507,8 @@
   {NULL, NULL}
 };
 
-#if 0
-/* not used */
 static const ASM_MAPPING _gas_mapping[] = {
-  {"labeldef", "%s::"},
+  {"labeldef", "%s:"},
   {"slabeldef", "%s:"},
   {"tlabeldef", "%05d$:"},
   {"tlabel", "%05d$"},
@@ -515,15 +516,15 @@
   {"zero", "#0x00"},
   {"one", "#0x01"},
   {"area", ".section %s"},
-  {"areacode", ".section %s"},
-  {"areadata", ".section %s"},
-  {"areahome", ".section %s"},
-  {"ascii", ".ascii \"%s\""},
-  {"ds", ".ds %d"},
+  {"areacode", ".section %s,\"ax\""},
+  {"areadata", ".section %s,\"rw\""},
+  {"areahome", ".section %s,\"ax\""},
+  {"ascii", ".ascii\t\"%s\""},
+  {"ds", ".ds\t%d"},
   {"db", ".db"},
-  {"dbs", ".db %s"},
+  {"dbs", ".db\t%s"},
   {"dw", ".dw"},
-  {"dws", ".dw %s"},
+  {"dws", ".dw\t%s"},
   {"constbyte", "0x%02X"},
   {"constword", "0x%04X"},
   {"immedword", "#0x%04X"},
@@ -531,20 +532,32 @@
   {"hashedstr", "#%s"},
   {"lsbimmeds", "#<%s"},
   {"msbimmeds", "#>%s"},
-  {"module", ".file \"%s.c\""},
-  {"global", ".globl %s"},
-  {"extern", ".globl %s"},
+  {"module", ".file\t\"%s.c\""},
+  {"global", ".globl\t%s"},
+  {"extern", ".extern\t%s"},
   {"fileprelude", ""},
   {"functionheader",
    "; ---------------------------------\n"
    "; Function %s\n"
    "; ---------------------------------"},
   {"functionlabeldef", "%s:"},
-  {"globalfunctionlabeldef", "%s::"},
-  {"bankimmeds", "0     ; PENDING: bank support"},
+  {"globalfunctionlabeldef", "%s:"},
+  {"bankimmeds", "b%s"},
+  {"hashedbankimmeds", "#b%s"},
+  {"los", "%s & 0xFF"},
+  {"his", "%s >> 8"},
+  {"hihis", "%s >> 16"},
+  {"hihihis", "%s >> 24"},
+  {"lod", "%d & 0xFF"},
+  {"hid", "%d >> 8"},
+  {"hihid", "%d >> 16"},
+  {"hihihid", "%d >> 24"},
+  {"lol", "%05d$ & 0xFF"},
+  {"hil", "%05d$ >> 8"},
+  {"hihil", "%05d$ >> 16"},
+  {"hihihil", "%05d$ >> 24"},
   {NULL, NULL}
 };
-#endif
 
 static const ASM_MAPPING _a390_mapping[] = {
   {"labeldef", "%s:"},
@@ -580,7 +593,8 @@
    "; ---------------------------------"},
   {"functionlabeldef", "%s:"},
   {"globalfunctionlabeldef", "%s::"},
-  {"bankimmeds", "0     ; PENDING: bank support"},
+  {"bankimmeds", "b%s"},
+  {"hashedbankimmeds", "#b%s"},
   {"los", "(%s & 0FFh)"},
   {"his", "((%s / 256) & 0FFh)"},
   {"hihis", "((%s / 65536) & 0FFh)"},
@@ -608,13 +622,10 @@
   _asxxxx_smallpdk_mapping
 };
 
-#if 0
-/* not used */
 const ASM_MAPPINGS asm_gas_mapping = {
   NULL,
   _gas_mapping
 };
-#endif
 
 const ASM_MAPPINGS asm_a390_mapping = {
   NULL,
diff -Nru sdcc-4.0.0+dfsg/src/SDCCasm.h sdcc-4.2.0+dfsg/src/SDCCasm.h
--- sdcc-4.0.0+dfsg/src/SDCCasm.h	2019-03-14 16:34:34.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/SDCCasm.h	2020-07-31 18:57:58.000000000 +0000
@@ -51,10 +51,7 @@
 /* The default mapping for small (<16 bit word) Padauk architectures.
  */
 extern const ASM_MAPPINGS asm_asxxxx_smallpdk_mapping;
-#if 0
-/* not used */
 extern const ASM_MAPPINGS asm_gas_mapping;
-#endif
 extern const ASM_MAPPINGS asm_a390_mapping;
 
 /** Last entry has szKey = NULL.
diff -Nru sdcc-4.0.0+dfsg/src/SDCCast.c sdcc-4.2.0+dfsg/src/SDCCast.c
--- sdcc-4.0.0+dfsg/src/SDCCast.c	2020-01-13 19:22:15.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/SDCCast.c	2022-02-19 20:33:04.000000000 +0000
@@ -74,7 +74,6 @@
 static ast *optimizeCompare (ast *);
 ast *optimizeRRCRLC (ast *);
 ast *optimizeSWAP (ast *);
-ast *optimizeGetHbit (ast *, RESULT_TYPE);
 ast *optimizeGetAbit (ast *, RESULT_TYPE);
 ast *optimizeGetByte (ast *, RESULT_TYPE);
 ast *optimizeGetWord (ast *, RESULT_TYPE);
@@ -254,6 +253,8 @@
   dest->level = src->level;
   dest->funcName = src->funcName;
   dest->reversed = src->reversed;
+  dest->inlined = src->inlined;
+  dest->initMode = src->initMode;
 
   if (src->ftype)
     dest->etype = getSpec (dest->ftype = copyLinkChain (src->ftype));
@@ -911,7 +912,7 @@
 
   /* decorate parameter */
   resultType = defParm ? getResultTypeFromType (defParm->type) : RESULT_TYPE_NONE;
-  *actParm = decorateType (*actParm, resultType);
+  *actParm = decorateType (*actParm, resultType, true);
 
   if (IS_VOID ((*actParm)->ftype))
     {
@@ -975,7 +976,7 @@
           (*actParm)->lineno = (*actParm)->right->lineno;
           AST_VALUES (*actParm, cast.implicitCast) = 1;
 
-          *actParm = decorateType (*actParm, resultType);
+          *actParm = decorateType (*actParm, resultType, true);
         }
       return 0;
     }                           /* vararg */
@@ -991,18 +992,8 @@
   /* the parameter type must be at least castable */
   if (compareType (defParm->type, (*actParm)->ftype) == 0)
     {
-      if (IS_STRUCT ((*actParm)->ftype))
-        {
-          if (IS_AST_VALUE (*actParm))
-            werrorfl ((*actParm)->filename, (*actParm)->lineno, E_STRUCT_AS_ARG, (*actParm)->opval.val->name);
-          else
-            werrorfl ((*actParm)->filename, (*actParm)->lineno, E_STRUCT_AS_ARG, "");
-        }
-      else
-        {
-          werror (E_INCOMPAT_TYPES);
-          printFromToType ((*actParm)->ftype, defParm->type);
-        }
+      werror (E_INCOMPAT_TYPES);
+      printFromToType ((*actParm)->ftype, defParm->type);
       return 1;
     }
 
@@ -1020,7 +1011,7 @@
       (*actParm)->filename = (*actParm)->right->filename;
       (*actParm)->lineno = (*actParm)->right->lineno;
       AST_VALUES (*actParm, cast.implicitCast) = 1;
-      *actParm = decorateType (*actParm, IS_GENPTR (defParm->type) ? RESULT_TYPE_GPTR : resultType);
+      *actParm = decorateType (*actParm, IS_GENPTR (defParm->type) ? RESULT_TYPE_GPTR : resultType, true);
     }
 
   /* make a copy and change the regparm type to the defined parm */
@@ -1055,10 +1046,10 @@
     ilist = ilist->init.deep;
 
   if (ilist)
-    iExpr = decorateType (resolveSymbols (list2expr (ilist)), RESULT_TYPE_NONE);
+    iExpr = decorateType (resolveSymbols (list2expr (ilist)), RESULT_TYPE_NONE, true);
   else
     iExpr = newAst_VALUE (valueFromLit (0));
-  return decorateType (newNode ('=', sym, iExpr), RESULT_TYPE_NONE);
+  return decorateType (newNode ('=', sym, iExpr), RESULT_TYPE_NONE, true);
 }
 
 /*------------------------------------------------------------------*/
@@ -1175,15 +1166,15 @@
           {
             ps->implicit = 1;
             lAst = newNode (PTR_OP, newNode ('&', sym, NULL), newAst_VALUE (symbolVal (ps)));
-            lAst = decorateType (resolveSymbols (lAst), RESULT_TYPE_NONE);
-            rast = decorateType (resolveSymbols (createIval (lAst, ps->type, NULL, rast, rootValue, 1)), RESULT_TYPE_NONE);          
+            lAst = decorateType (resolveSymbols (lAst), RESULT_TYPE_NONE, true);
+            rast = decorateType (resolveSymbols (createIval (lAst, ps->type, NULL, rast, rootValue, 1)), RESULT_TYPE_NONE, true);          
           }
 
       /* initialize this field */
       sflds->implicit = 1;
       lAst = newNode (PTR_OP, newNode ('&', sym, NULL), newAst_VALUE (symbolVal (sflds)));
-      lAst = decorateType (resolveSymbols (lAst), RESULT_TYPE_NONE);
-      rast = decorateType (resolveSymbols (createIval (lAst, sflds->type, iloop, rast, rootValue, 1)), RESULT_TYPE_NONE);
+      lAst = decorateType (resolveSymbols (lAst), RESULT_TYPE_NONE, true);
+      rast = decorateType (resolveSymbols (createIval (lAst, sflds->type, iloop, rast, rootValue, 1)), RESULT_TYPE_NONE, true);
       iloop = iloop ? iloop->next : NULL;
 
       /* Unions can only initialize a single field */
@@ -1223,17 +1214,17 @@
       ilist && ilist->type == INIT_NODE)
     if ((rast = createIvalCharPtr (sym,
                                    type,
-                                   decorateType (resolveSymbols (list2expr (ilist)), RESULT_TYPE_NONE),
+                                   decorateType (resolveSymbols (list2expr (ilist)), RESULT_TYPE_NONE, true),
                                    rootValue)))
-      return decorateType (resolveSymbols (rast), RESULT_TYPE_NONE);
+      return decorateType (resolveSymbols (rast), RESULT_TYPE_NONE, true);
   /* char *p = {"abc"}; */
   if ((IS_CHAR (type->next) || IS_INT (type->next) && IS_UNSIGNED (type->next)) &&
       ilist && ilist->type == INIT_DEEP && ilist->init.deep && ilist->init.deep->type == INIT_NODE)
     if ((rast = createIvalCharPtr (sym,
                                    type,
-                                   decorateType (resolveSymbols (list2expr (ilist->init.deep)), RESULT_TYPE_NONE),
+                                   decorateType (resolveSymbols (list2expr (ilist->init.deep)), RESULT_TYPE_NONE, true),
                                    rootValue)))
-      return decorateType (resolveSymbols (rast), RESULT_TYPE_NONE);
+      return decorateType (resolveSymbols (rast), RESULT_TYPE_NONE, true);
 
   /* not the special case */
   if (ilist && ilist->type != INIT_DEEP)
@@ -1254,7 +1245,7 @@
     {
       ast *aSym;
 
-      aSym = decorateType (resolveSymbols (sym), RESULT_TYPE_NONE);
+      aSym = decorateType (resolveSymbols (sym), RESULT_TYPE_NONE, true);
 
       rast = newNode (ARRAYINIT, aSym, NULL);
       rast->values.constlist = literalL;
@@ -1310,7 +1301,7 @@
             }
 
           aSym = newNode ('[', sym, newAst_VALUE (valueFromLit ((float) (idx))));
-          aSym = decorateType (resolveSymbols (aSym), RESULT_TYPE_NONE);
+          aSym = decorateType (resolveSymbols (aSym), RESULT_TYPE_NONE, true);
           rast = createIval (aSym, type->next, iloop, rast, rootValue, 0);
           idx++;
           iloop = (iloop ? iloop->next : NULL);
@@ -1327,7 +1318,7 @@
         DCL_ELEM (type) = size;
     }
 
-  return decorateType (resolveSymbols (rast), RESULT_TYPE_NONE);
+  return decorateType (resolveSymbols (rast), RESULT_TYPE_NONE, true);
 }
 
 /*-----------------------------------------------------------------*/
@@ -1364,7 +1355,7 @@
                                             newAst_VALUE (valueFromLit ((float) i))), newAst_VALUE (valueFromLit (0))));
         }
 
-      return decorateType (resolveSymbols (rast), RESULT_TYPE_NONE);
+      return decorateType (resolveSymbols (rast), RESULT_TYPE_NONE, true);
     }
 
   if ((IS_LITERAL (iexpr->etype) || (IS_SPEC (iexpr->etype) && SPEC_SCLS (iexpr->etype) == S_CODE)) && IS_ARRAY (iexpr->ftype))
@@ -1438,7 +1429,7 @@
             DCL_ELEM (type) = size;
         }
 
-      return decorateType (resolveSymbols (rast), RESULT_TYPE_NONE);
+      return decorateType (resolveSymbols (rast), RESULT_TYPE_NONE, true);
     }
 
   return NULL;
@@ -1458,7 +1449,7 @@
     ilist = ilist->init.deep;
 
   if (ilist)
-    iexpr = decorateType (resolveSymbols (list2expr (ilist)), RESULT_TYPE_NONE);
+    iexpr = decorateType (resolveSymbols (list2expr (ilist)), RESULT_TYPE_NONE, true);
   else
     iexpr = newAst_VALUE (valueFromLit (0));
 
@@ -1498,13 +1489,13 @@
     rast = createIvalType (sym, type, ilist);
 
   if (wid)
-    return decorateType (resolveSymbols (newNode (NULLOP, wid, rast)), RESULT_TYPE_NONE);
+    return decorateType (resolveSymbols (newNode (NULLOP, wid, rast)), RESULT_TYPE_NONE, true);
   else
-    return decorateType (resolveSymbols (rast), RESULT_TYPE_NONE);
+    return decorateType (resolveSymbols (rast), RESULT_TYPE_NONE, true);
 }
 
 /*-----------------------------------------------------------------*/
-/* initAggregates - initialises aggregate variables with initv     */
+/* initAggregates - initializes aggregate variables with initv     */
 /*-----------------------------------------------------------------*/
 ast *
 initAggregates (symbol *sym, initList *ival, ast *wid)
@@ -1548,7 +1539,7 @@
       /* if this is a static variable & has an */
       /* initial value the code needs to be lifted */
       /* here to the main portion since they can be */
-      /* initialised only once at the start    */
+      /* initialized only once at the start    */
       if (IS_STATIC (sym->etype) && sym->ival && SPEC_SCLS (sym->etype) != S_CODE)
         {
           symbol *newSym;
@@ -1779,7 +1770,7 @@
       return TRUE;
     }
 
-  cexpr = decorateType (resolveSymbols (cexpr), RESULT_TYPE_NONE);
+  cexpr = decorateType (resolveSymbols (cexpr), RESULT_TYPE_NONE, true);
 
   switch (cexpr->type)
     {
@@ -1858,7 +1849,7 @@
 value *
 constExprValue (ast * cexpr, int check)
 {
-  cexpr = decorateType (resolveSymbols (cexpr), RESULT_TYPE_NONE);
+  cexpr = decorateType (resolveSymbols (cexpr), RESULT_TYPE_NONE, true);
 
   /* if this is not a constant then */
   if (!IS_LITERAL (cexpr->ftype))
@@ -2206,7 +2197,6 @@
     case '!':
     case RRC:
     case RLC:
-    case GETHBIT:
     case SWAP:
       if (IS_AST_SYM_VALUE (pbody->left) && isSymbolEqual (AST_SYMBOL (pbody->left), sym))
         return FALSE;
@@ -2224,7 +2214,7 @@
     case NE_OP:
     case '?':
     case ':':
-    case SIZEOF:               /* evaluate wihout code generation */
+    case SIZEOF:               /* evaluate without code generation */
 
       if (IS_AST_SYM_VALUE (pbody->left) && isSymbolEqual (AST_SYMBOL (pbody->left), sym))
         return FALSE;
@@ -2411,7 +2401,7 @@
                                                            newAst_VALUE (constVal ("1"))), rloop))));
 
   rloop->lineno = init->lineno;
-  return decorateType (rloop, RESULT_TYPE_NONE);
+  return decorateType (rloop, RESULT_TYPE_NONE, true);
 }
 
 /*-----------------------------------------------------------------*/
@@ -2489,7 +2479,7 @@
   initExpr->opval.op = CAST;
   initExpr->left = newAst_LINK (LTYPE (initExpr));
   initExpr->decorated = 0;
-  decorateType (initExpr, RESULT_TYPE_NONE);
+  decorateType (initExpr, RESULT_TYPE_NONE, true);
   if (!IS_AST_LIT_VALUE (initExpr))
     return FALSE;
 
@@ -2505,7 +2495,7 @@
       /* trigger a warning that may not apply to the original */
       /* source code. */
       original = setWarningDisabledState (W_COMP_RANGE, TRUE);
-      condExpr = decorateType (condExpr, RESULT_TYPE_NONE);
+      condExpr = decorateType (condExpr, RESULT_TYPE_NONE, true);
       setWarningDisabledState (W_COMP_RANGE, original);
     }
   if (!IS_AST_LIT_VALUE (condExpr))
@@ -2731,7 +2721,7 @@
      but not when promoting from char to int */
   if (!upCasted)
     SPEC_USIGN (tree->left->opval.lnk) = IS_UNSIGNED (tree->right->etype) ? 1 : 0;
-  return decorateType (tree, resultType);
+  return decorateType (tree, resultType, true);
 }
 
 /*-----------------------------------------------------------------*/
@@ -2740,6 +2730,11 @@
 static RESULT_TYPE
 resultTypePropagate (ast *tree, RESULT_TYPE resultType)
 {
+  /* In general, we don't want to propagate BOOL or IFX result types */
+  if (((resultType == RESULT_TYPE_BOOL) || (resultType == RESULT_TYPE_IFX))
+      && (tree->opval.op != '='))
+    resultType = RESULT_TYPE_NONE;
+
   switch (tree->opval.op)
     {
     case AND_OP:
@@ -2755,7 +2750,6 @@
     case '~':
     case LEFT_OP:
     case LABEL:
-    case GETHBIT:
     case GETABIT:
     case GETBYTE:
     case GETWORD:
@@ -2837,7 +2831,7 @@
          compute type of RHS, and set the symbol's type to match */
       if (assignee->type == NULL && assignee->infertype)
         {
-          ast *dtr = decorateType (resolveSymbols (tree->right), RESULT_TYPE_NONE);
+          ast *dtr = decorateType (resolveSymbols (tree->right), RESULT_TYPE_NONE, true);
 
           if (dtr != tree->right)
             tree->right = dtr;
@@ -2877,8 +2871,31 @@
       tree->opval.val->etype = tree->opval.val->sym->etype;
     }
 
-  gatherImplicitVariables (tree->left, block);
-  gatherImplicitVariables (tree->right, block);
+  /* If entering a block with symbols defined, mark the symbols in-scope */
+  /* before continuing down the tree, and mark them out-of-scope again   */
+  /* on the way back up */ 
+  if (tree->type == EX_OP && tree->opval.op == BLOCK && tree->values.sym)
+    {
+      symbol * sym = tree->values.sym;
+      while (sym)
+        {
+          sym->isinscope = 1;
+          sym = sym->next;
+        }
+      gatherImplicitVariables (tree->left, block);
+      gatherImplicitVariables (tree->right, block);
+      sym = tree->values.sym;
+      while (sym)
+        {
+          sym->isinscope = 0;
+          sym = sym->next;
+        }
+    }
+  else
+    {
+      gatherImplicitVariables (tree->left, block);
+      gatherImplicitVariables (tree->right, block);
+    }
 }
 
 /*-----------------------------------------------------------------*/
@@ -2977,7 +2994,7 @@
               if (IS_FUNCPTR (newType) && !orgIsNullPtrConstant) // cast to pointer to function is only allowed for null pointer constants
                 errors += werror (W_INCOMPAT_PTYPES);
             }
-          else if (GPTRSIZE > FARPTRSIZE /*!TARGET_IS_Z80 && !TARGET_IS_GBZ80 */ )
+          else if (GPTRSIZE > FARPTRSIZE /*!TARGET_IS_Z80 && !TARGET_IS_SM83 */ )
             {
               // if not a pointer to a function
               if (!(IS_CODEPTR (newType) && IS_FUNC (newType->next) && IS_FUNC (orgType)))
@@ -3233,6 +3250,8 @@
         ((char *)(dbuf_get_buf (&dbuf)))[strlength - 2] = 0;
 
         parm->opval.val = stringToSymbol (rawStrVal (dbuf_get_buf (&dbuf), strlength - 1));
+        SPEC_REGPARM (parms->etype) = SPEC_REGPARM (FUNC_ARGS (puts_sym->type)->etype);
+        SPEC_ARGREG (parms->etype) = SPEC_ARGREG (FUNC_ARGS (puts_sym->type)->etype);
 	dbuf_destroy (&dbuf);
 
         freeStringSymbol (strsym);
@@ -3241,7 +3260,7 @@
       func->opval.val->sym = puts_sym;
     }
   // Optimize strcpy() to memcpy().
-  else if (!strcmp(funcname, "strcpy") && nparms == 2)
+  else if ((!strcmp(funcname, "strcpy") || !strcmp(funcname, "__builtin_strcpy")) && nparms == 2)
     {
       ast *parm = parms->right;
 
@@ -3268,25 +3287,42 @@
       size_t minlength; // Minimum string length for replacement.
       if (TARGET_IS_STM8)
         minlength = optimize.codeSize ? SIZE_MAX : 12;
+      else if (TARGET_IS_RABBIT)
+        minlength = optimize.codeSize ? SIZE_MAX : (optimize.codeSpeed ? 8 : 24);
       else // TODO:Check for other targets when memcpy() is a better choice than strcpy;
         minlength = SIZE_MAX;
 
       if (strlength < minlength)
         return;
 
-      symbol *memcpy_sym = findSym (SymbolTab, NULL, "memcpy");
+      symbol *memcpy_sym = findSym (SymbolTab, NULL, !strcmp(funcname, "__builtin_strcpy") ? "__builtin_memcpy" : "__memcpy");
 
       if(!memcpy_sym)
         return;
 
       ast *lengthparm = newAst_VALUE (valCastLiteral (newIntLink(), strlength, strlength));
-      decorateType (lengthparm, RESULT_TYPE_NONE);
+      lengthparm->lineno = parm->lineno;
+      decorateType (lengthparm, RESULT_TYPE_NONE, true);
       ast *node = newAst_OP (PARAM);
-      node->left = parm;
+      node->lineno = parm->lineno;
+
+      node->left = newNode (CAST, newAst_LINK (copyLinkChain (FUNC_ARGS(memcpy_sym->type)->type)), parm);
+      node->left->values.cast.implicitCast = 1;
+      node->left->lineno = parm->lineno;
+      node->left->filename = node->left->left->filename = parm->filename;
+      node->left = decorateType (node->left, RESULT_TYPE_GPTR, true);
+      
       node->right = lengthparm;
       node->decorated = 1;
       parms->right = node;
+
       func->opval.val->sym = memcpy_sym;
+      SPEC_REGPARM (parms->left->etype) = SPEC_REGPARM (FUNC_ARGS (memcpy_sym->type)->etype);
+      SPEC_ARGREG (parms->left->etype) = SPEC_ARGREG (FUNC_ARGS (memcpy_sym->type)->etype);
+      SPEC_REGPARM (parms->right->left->etype) = SPEC_REGPARM (FUNC_ARGS (memcpy_sym->type)->next->etype);
+      SPEC_ARGREG (parms->right->left->etype) = SPEC_ARGREG (FUNC_ARGS (memcpy_sym->type)->next->etype);
+      SPEC_REGPARM (parms->right->right->etype) = SPEC_REGPARM (FUNC_ARGS (memcpy_sym->type)->next->next->etype);
+      SPEC_ARGREG (parms->right->right->etype) = SPEC_ARGREG (FUNC_ARGS (memcpy_sym->type)->next->next->etype);
     }
 }
 
@@ -3352,9 +3388,9 @@
   copyAstLoc (params, tree);
 
   /* create call to the appropriate memcpy function */
-  ast *memcpy_ast = newAst_VALUE (symbolVal (memcpy_builtin));
-  copyAstLoc (memcpy_ast, tree);
-  ast *call = newNode (CALL, memcpy_ast, params);
+  ast *ast_memcpy = newAst_VALUE (symbolVal (builtin_memcpy));
+  copyAstLoc (ast_memcpy, tree);
+  ast *call = newNode (CALL, ast_memcpy, params);
   copyAstLoc (call, tree);
 
   /* assemble the result expression depending on side effects */
@@ -3374,7 +3410,7 @@
 
   /* copy source location and return decorated result */
   copyAstLoc (newTree, tree);
-  return decorateType (newTree, RESULT_TYPE_OTHER);
+  return decorateType (newTree, RESULT_TYPE_OTHER, true);
 }
 
 /*--------------------------------------------------------------------*/
@@ -3385,11 +3421,12 @@
 /* It also does constant folding, and parameter checking.             */
 /*--------------------------------------------------------------------*/
 ast *
-decorateType (ast *tree, RESULT_TYPE resultType)
+decorateType (ast *tree, RESULT_TYPE resultType, bool reduceTypeAllowed)
 {
   int parmNumber;
   sym_link *p;
   RESULT_TYPE resultTypeProp;
+  static int findingAddressOf=0;
 
   if (!tree)
     return tree;
@@ -3499,12 +3536,21 @@
 
     /* Before decorating the left branch we've to decide in dependence
        upon tree->opval.op, if resultType can be propagated */
-    resultTypeProp = resultTypePropagate (tree, resultType);
+    if (reduceTypeAllowed)
+      resultTypeProp = resultTypePropagate (tree, resultType);
+    else
+      resultTypeProp = RESULT_TYPE_OTHER;
 
-    if ((tree->opval.op == '?') && (resultTypeProp != RESULT_TYPE_BOOL))
-      dtl = decorateType (tree->left, RESULT_TYPE_IFX);
+    if ((tree->opval.op == '?') && (resultTypeProp != RESULT_TYPE_BOOL) && reduceTypeAllowed)
+      dtl = decorateType (tree->left, RESULT_TYPE_IFX, reduceTypeAllowed);
+    else if ((tree->opval.op == '&') && (!tree->right))
+      {
+        findingAddressOf = 1;
+        dtl = decorateType (tree->left, resultTypeProp, reduceTypeAllowed);
+        findingAddressOf = 0;
+      }
     else
-      dtl = decorateType (tree->left, resultTypeProp);
+      dtl = decorateType (tree->left, resultTypeProp, reduceTypeAllowed);
 
     /* if an array node, we may need to swap branches */
     if (tree->opval.op == '[')
@@ -3521,8 +3567,11 @@
     /* After decorating the left branch there's type information available
        in tree->left->?type. If the op is e.g. '=' we extract the type
        information from there and propagate it to the right branch. */
-    resultTypeProp = getLeftResultType (tree, resultTypeProp);
-
+    if (reduceTypeAllowed)
+      resultTypeProp = getLeftResultType (tree, resultTypeProp);
+    else
+      resultTypeProp = RESULT_TYPE_OTHER;
+      
     switch (tree->opval.op)
       {
       case '?':
@@ -3538,14 +3587,19 @@
       case SIZEOF:
         /* don't allocate string if it is a sizeof argument */
         ++noAlloc;
-        dtr = decorateType (tree->right, resultTypeProp);
+        resultTypeProp = RESULT_TYPE_OTHER;
+        reduceTypeAllowed = false;
+        dtr = decorateType (tree->right, resultTypeProp, reduceTypeAllowed);
         --noAlloc;
         break;
       default:
-        dtr = decorateType (tree->right, resultTypeProp);
+        dtr = decorateType (tree->right, resultTypeProp, reduceTypeAllowed);
         break;
       }
 
+    if (!reduceTypeAllowed)
+      resultType = RESULT_TYPE_OTHER;
+
     /* this is to take care of situations
        when the tree gets rewritten */
     if (dtl != tree->left)
@@ -3598,7 +3652,9 @@
         {
           int arrayIndex = (int) ulFromVal (valFromType (RETYPE (tree)));
           int arraySize = DCL_ELEM (LTYPE (tree));
-          if (arraySize && arrayIndex >= arraySize)
+          int arrayLimit = findingAddressOf ? arraySize+1 : arraySize;
+          
+          if (arraySize && arrayIndex >= arrayLimit)
             {
               werrorfl (tree->filename, tree->lineno, W_IDX_OUT_OF_BOUNDS, arrayIndex, arraySize);
             }
@@ -3741,7 +3797,7 @@
           if (IS_LITERAL (RTYPE (tree)) && IS_LITERAL (LTYPE (tree)))
             {
               tree->type = EX_VALUE;
-              tree->opval.val = valBitwise (valFromType (LETYPE (tree)), valFromType (RETYPE (tree)), '&');
+              tree->opval.val = valBitwise (valFromType (LETYPE (tree)), valFromType (RETYPE (tree)), '&', reduceTypeAllowed);
 
               tree->right = tree->left = NULL;
               TETYPE (tree) = tree->opval.val->etype;
@@ -3770,40 +3826,34 @@
                   litTree->left = tree->right;
                   tree->right = tTree;
                   /* both operands in litTree are literal now */
-                  decorateType (parent, resultType);
+                  decorateType (parent, resultType, reduceTypeAllowed);
                 }
             }
 
           /* if ANDing boolean with literal then reduce literal LSB to boolean */
-          if (IS_LITERAL (RTYPE (tree)) && IS_BOOLEAN (LTYPE (tree)))
+          if (reduceTypeAllowed && IS_LITERAL (RTYPE (tree)) && IS_BOOLEAN (LTYPE (tree)))
             {
               unsigned long litval = AST_ULONG_VALUE (tree->right);
-              tree->right = decorateType (newAst_VALUE (constBoolVal (litval & 1)), resultType);
+              tree->right = decorateType (newAst_VALUE (constBoolVal (litval & 1, reduceTypeAllowed)), resultType, reduceTypeAllowed);
             }
 
-          /* see if this is a GETHBIT operation if yes
-             then return that */
-          otree = optimizeGetHbit (tree, resultType);
-          if (otree != tree)
-            return decorateType (otree, RESULT_TYPE_NONE);
-
           /* see if this is a GETABIT operation if yes
              then return that */
           otree = optimizeGetAbit (tree, resultType);
           if (otree != tree)
-            return decorateType (otree, RESULT_TYPE_NONE);
+            return decorateType (otree, RESULT_TYPE_NONE, reduceTypeAllowed);
 
           /* see if this is a GETBYTE operation if yes
              then return that */
           otree = optimizeGetByte (tree, resultType);
           if (otree != tree)
-            return decorateType (otree, RESULT_TYPE_NONE);
+            return decorateType (otree, RESULT_TYPE_NONE, reduceTypeAllowed);
 
           /* see if this is a GETWORD operation if yes
              then return that */
           otree = optimizeGetWord (tree, resultType);
           if (otree != tree)
-            return decorateType (otree, RESULT_TYPE_NONE);
+            return decorateType (otree, RESULT_TYPE_NONE, reduceTypeAllowed);
 
           /* if right is a literal and has the same size with left, 
              then also sync their signess to avoid unecessary cast */
@@ -3834,6 +3884,11 @@
           werrorfl (tree->filename, tree->lineno, E_ILLEGAL_ADDR, "address of bit variable");
           goto errorTreeReturn;
         }
+        
+      if ((TARGET_Z80_LIKE || TARGET_PDK_LIKE) && SPEC_SCLS (LETYPE (tree)) == S_SFR)
+        {
+          werror (W_SFR_ADDRESS);
+        }
 
       if (LETYPE (tree) && SPEC_SCLS (tree->left->etype) == S_REGISTER)
         {
@@ -3908,11 +3963,11 @@
       {
         ast *wtree = optimizeRRCRLC (tree);
         if (wtree != tree)
-          return decorateType (wtree, RESULT_TYPE_NONE);
+          return decorateType (wtree, RESULT_TYPE_NONE, reduceTypeAllowed);
 
         wtree = optimizeSWAP (tree);
         if (wtree != tree)
-          return decorateType (wtree, RESULT_TYPE_NONE);
+          return decorateType (wtree, RESULT_TYPE_NONE, reduceTypeAllowed);
       }
 
       /* if left is a literal exchange left & right */
@@ -3936,18 +3991,19 @@
               litTree->left = tree->right;
               tree->right = tTree;
               /* both operands in tTree are literal now */
-              decorateType (parent, resultType);
+              decorateType (parent, resultType, reduceTypeAllowed);
             }
         }
 
       /* if ORing boolean with literal then reduce literal to boolean */
-      if (IS_LITERAL (RTYPE (tree)) &&
+      if (reduceTypeAllowed &&
+          IS_LITERAL (RTYPE (tree)) &&
           IS_BOOLEAN (LTYPE (tree)) &&
           IS_INTEGRAL (RTYPE (tree)) &&
           resultType == RESULT_TYPE_BOOL)
         {
           unsigned long litval = AST_ULONG_VALUE (tree->right);
-          tree->right = decorateType (newAst_VALUE (constBoolVal (litval != 0)), resultType);
+          tree->right = decorateType (newAst_VALUE (constBoolVal (litval != 0, reduceTypeAllowed)), resultType, reduceTypeAllowed);
         }
 
       /* fall through */
@@ -3971,8 +4027,8 @@
       /* if they are both literal then rewrite the tree */
       if (IS_LITERAL (RTYPE (tree)) && IS_LITERAL (LTYPE (tree)))
         {
-          rewriteAstNodeVal (tree, valBitwise (valFromType (LETYPE (tree)), valFromType (RETYPE (tree)), tree->opval.op));
-          return decorateType (tree, resultType);
+          rewriteAstNodeVal (tree, valBitwise (valFromType (LETYPE (tree)), valFromType (RETYPE (tree)), tree->opval.op, reduceTypeAllowed));
+          return decorateType (tree, resultType, reduceTypeAllowed);
         }
 
       /* if left is a literal exchange left & right */
@@ -3996,12 +4052,13 @@
               litTree->left = tree->right;
               tree->right = tTree;
               /* both operands in litTree are literal now */
-              decorateType (parent, resultType);
+              decorateType (parent, resultType, reduceTypeAllowed);
             }
         }
 
       /* if XORing boolean with literal then reduce literal to boolean */
-      if (IS_LITERAL (RTYPE (tree)) &&
+      if (reduceTypeAllowed &&
+          IS_LITERAL (RTYPE (tree)) &&
           IS_BOOLEAN (LTYPE (tree)) &&
           IS_INTEGRAL (RTYPE (tree)) &&
           resultType == RESULT_TYPE_BOOL &&
@@ -4010,14 +4067,32 @@
           unsigned long litval = AST_ULONG_VALUE (tree->right);
           if (litval == 0 || litval == 1)
             {
-              tree->right = decorateType (newAst_VALUE (constBoolVal (litval != 0)), resultType);
+              tree->right = decorateType (newAst_VALUE (constBoolVal (litval != 0, reduceTypeAllowed)), resultType, reduceTypeAllowed);
             }
           else
             {
               tree->opval.op = '|';
-              tree->right = newAst_VALUE (constBoolVal (1));
+              tree->right = newAst_VALUE (constBoolVal (1, reduceTypeAllowed));
               tree->decorated = 0;
-              return decorateType (tree, resultType);
+              return decorateType (tree, resultType, reduceTypeAllowed);
+            }
+        }
+        
+      /* OR / XOR char with literal integral, try to reduce integral to CHAR if it fits in a CHAR */
+      if (reduceTypeAllowed && 
+          !TARGET_PDK_LIKE && // Temporary fix to avoid bug #3259 - Wrong opcodes
+          IS_LITERAL (RTYPE (tree)) &&
+          IS_INTEGRAL (RTYPE (tree)) &&
+          !IS_CHAR (RTYPE (tree)) &&
+          IS_CHAR(LTYPE(tree)))
+        {
+          unsigned long litval = AST_ULONG_VALUE (tree->right); 
+          if ((litval >= 0) && (litval <= 255) && reduceTypeAllowed)
+            {
+              ast *newAst = newAst_VALUE (valueFromLit (litval));
+              copyAstLoc (newAst, tree->right);
+              tree->right = decorateType (newAst, resultType, reduceTypeAllowed);
+              //SPEC_USIGN (RTYPE (tree)) = 1;
             }
         }
 
@@ -4050,8 +4125,8 @@
       /* rewrite the tree */
       if (IS_LITERAL (RTYPE (tree)) && IS_LITERAL (LTYPE (tree)))
         {
-          rewriteAstNodeVal (tree, valDiv (valFromType (LETYPE (tree)), valFromType (RETYPE (tree))));
-          return decorateType (tree, resultType);
+          rewriteAstNodeVal (tree, valDiv (valFromType (LETYPE (tree)), valFromType (RETYPE (tree)), reduceTypeAllowed));
+          return decorateType (tree, resultType, reduceTypeAllowed);
         }
 
       LRVAL (tree) = RRVAL (tree) = 1;
@@ -4084,7 +4159,7 @@
                   litTree->right->lineno = tree->lineno;
 
                   tree->right->opval.val = constCharVal (1);
-                  decorateType (parent, resultType);
+                  decorateType (parent, resultType, reduceTypeAllowed);
                 }
               else
                 {
@@ -4092,7 +4167,7 @@
                      We can't call decorateType(parent, RESULT_TYPE_NONE), because
                      this would cause an infinit loop. */
                   parent->decorated = 1;
-                  decorateType (litTree, resultType);
+                  decorateType (litTree, resultType, reduceTypeAllowed);
                 }
             }
         }
@@ -4122,8 +4197,8 @@
       /* rewrite the tree */
       if (IS_LITERAL (RTYPE (tree)) && IS_LITERAL (LTYPE (tree)))
         {
-          rewriteAstNodeVal (tree, valMod (valFromType (LETYPE (tree)), valFromType (RETYPE (tree))));
-          return decorateType (tree, resultType);
+          rewriteAstNodeVal (tree, valMod (valFromType (LETYPE (tree)), valFromType (RETYPE (tree)), reduceTypeAllowed));
+          return decorateType (tree, resultType, reduceTypeAllowed);
         }
       LRVAL (tree) = RRVAL (tree) = 1;
       TETYPE (tree) = getSpec (TTYPE (tree) = computeType (LTYPE (tree), RTYPE (tree), resultType, tree->opval.op));
@@ -4175,8 +4250,8 @@
       /* rewrite the tree */
       if (IS_LITERAL (RTYPE (tree)) && IS_LITERAL (LTYPE (tree)))
         {
-          rewriteAstNodeVal (tree, valMult (valFromType (LETYPE (tree)), valFromType (RETYPE (tree))));
-          return decorateType (tree, resultType);
+          rewriteAstNodeVal (tree, valMult (valFromType (LETYPE (tree)), valFromType (RETYPE (tree)), reduceTypeAllowed));
+          return decorateType (tree, resultType, reduceTypeAllowed);
         }
 
       /* if left is a literal exchange left & right */
@@ -4200,7 +4275,7 @@
               litTree->left = tree->right;
               tree->right = tTree;
               /* both operands in litTree are literal now */
-              decorateType (parent, resultType);
+              decorateType (parent, resultType, reduceTypeAllowed);
             }
         }
 
@@ -4242,8 +4317,15 @@
               TETYPE (tree) = TTYPE (tree) = tree->opval.val->type;
               return tree;
             }
+          
           LRVAL (tree) = 1;
-          COPYTYPE (TTYPE (tree), TETYPE (tree), LTYPE (tree));
+          if (reduceTypeAllowed)
+              COPYTYPE (TTYPE (tree), TETYPE (tree), LTYPE (tree));
+          else
+            {
+              tree->left = addCast (tree->left, resultTypeProp, true);
+              TETYPE (tree) = getSpec (TTYPE (tree) = computeType (LTYPE (tree), NULL, resultType, tree->opval.op));
+            }
           return tree;
         }
 
@@ -4277,8 +4359,8 @@
         {
           tree->left = addCast (tree->left, resultTypeProp, TRUE);
           tree->right = addCast (tree->right, resultTypeProp, TRUE);
-          rewriteAstNodeVal (tree, valPlus (valFromType (LETYPE (tree)), valFromType (RETYPE (tree))));
-          return decorateType (tree, resultType);
+          rewriteAstNodeVal (tree, valPlus (valFromType (LETYPE (tree)), valFromType (RETYPE (tree)), reduceTypeAllowed));
+          return decorateType (tree, resultType, reduceTypeAllowed);
         }
 
       /* if the right is a pointer or left is a literal
@@ -4328,7 +4410,7 @@
                       tree->opval.op = '-';
                     }
                 }
-              decorateType (parent, resultType);
+              decorateType (parent, resultType, reduceTypeAllowed);
             }
         }
 
@@ -4370,7 +4452,7 @@
           if (IS_LITERAL (LTYPE (tree)))
             {
               tree->type = EX_VALUE;
-              tree->opval.val = valUnaryPM (valFromType (LETYPE (tree)));
+              tree->opval.val = valUnaryPM (valFromType (LETYPE (tree)), reduceTypeAllowed);
               tree->left = NULL;
               TETYPE (tree) = TTYPE (tree) = tree->opval.val->type;
               return tree;
@@ -4411,8 +4493,8 @@
         {
           tree->left = addCast (tree->left, resultTypeProp, TRUE);
           tree->right = addCast (tree->right, resultTypeProp, TRUE);
-          rewriteAstNodeVal (tree, valMinus (valFromType (LETYPE (tree)), valFromType (RETYPE (tree))));
-          return decorateType (tree, resultType);
+          rewriteAstNodeVal (tree, valMinus (valFromType (LETYPE (tree)), valFromType (RETYPE (tree)), reduceTypeAllowed));
+          return decorateType (tree, resultType, reduceTypeAllowed);
        }
 
       /* if the left & right are equal then zero */
@@ -4420,16 +4502,16 @@
         isAstEqual (tree->left, tree->right))
         {
           tree->type = EX_VALUE;
+          tree->opval.val = valZeroResultFromOp(LTYPE (tree), RTYPE (tree), tree->opval.op, reduceTypeAllowed);
           tree->left = tree->right = NULL;
-          tree->opval.val = constVal ("0");
           TETYPE (tree) = TTYPE (tree) = tree->opval.val->type;
           return tree;
         }
 
       /* if both of them are pointers or arrays then */
-      /* the result is going to be an integer        */
+      /* the result is a ptrdiff */
       if ((IS_ARRAY (LTYPE (tree)) || IS_PTR (LTYPE (tree))) && (IS_ARRAY (RTYPE (tree)) || IS_PTR (RTYPE (tree))))
-        TETYPE (tree) = TTYPE (tree) = newIntLink ();
+        TETYPE (tree) = TTYPE (tree) = newPtrDiffLink();
       else
         /* if only the left is a pointer */
         /* then result is a pointer      */
@@ -4484,7 +4566,7 @@
                       litTree->opval.op = '+';
 
                       tree->decorated = 0;
-                      decorateType (tree, resultType);
+                      decorateType (tree, resultType, reduceTypeAllowed);
                     }
                   else
                     {
@@ -4494,7 +4576,7 @@
                       tree->right = tTree;
                     }
                 }
-              decorateType (litParent, resultType);
+              decorateType (litParent, resultType, reduceTypeAllowed);
             }
         }
       return tree;
@@ -4515,7 +4597,7 @@
       if (IS_LITERAL (LTYPE (tree)))
         {
           tree->type = EX_VALUE;
-          tree->opval.val = valComplement (valFromType (LETYPE (tree)));
+          tree->opval.val = valComplement (valFromType (LETYPE (tree)), reduceTypeAllowed);
           tree->left = NULL;
           TETYPE (tree) = TTYPE (tree) = tree->opval.val->type;
           return addCast (tree, resultTypeProp, TRUE);
@@ -4531,7 +4613,7 @@
 
           /* optimize bit-result, even if we optimize a buggy source */
           tree->type = EX_VALUE;
-          tree->opval.val = constBoolVal (1);
+          tree->opval.val = constBoolVal (1, reduceTypeAllowed);
         }
       else
         tree->left = addCast (tree->left, resultTypeProp, TRUE);
@@ -4564,24 +4646,32 @@
           /* remove double '!!X' by 'X ? 1 : 0' */ /* TODO: Casts to _Bools tend to result in far more efficient code than '?' */
           tree->opval.op = '?';
           tree->left = tree->left->left;
-          tree->right = newNode (':', newAst_VALUE (constBoolVal (1)), newAst_VALUE (constBoolVal (0)));
+          tree->right = newNode (':', newAst_VALUE (constBoolVal (1, reduceTypeAllowed)), newAst_VALUE (constBoolVal (0, reduceTypeAllowed)));
           tree->right->filename = tree->filename;
           tree->right->lineno = tree->lineno;
           tree->decorated = 0;
-          return decorateType (tree, resultType);
+          return decorateType (tree, resultType, reduceTypeAllowed);
         }
 #endif
 
       /* if left is a literal then do it */
       if (IS_LITERAL (LTYPE (tree)))
         {
-          rewriteAstNodeVal (tree, valNot (valFromType (LETYPE (tree))));
-          return decorateType (tree, resultType);
+          rewriteAstNodeVal (tree, valNot (valFromType (LETYPE (tree)), reduceTypeAllowed));
+          return decorateType (tree, resultType, reduceTypeAllowed);
         }
       LRVAL (tree) = 1;
-      TTYPE (tree) = TETYPE (tree) = (resultTypeProp == RESULT_TYPE_BOOL) ? newBoolLink () : newCharLink ();
-      if (IS_BOOLEAN (LTYPE (tree)))
-        SPEC_USIGN (TTYPE (tree)) = SPEC_USIGN (LTYPE (tree));
+      if (reduceTypeAllowed)
+        {
+          TTYPE (tree) = TETYPE (tree) = (resultTypeProp == RESULT_TYPE_BOOL) ? newBoolLink () : newCharLink ();
+          if (IS_BOOLEAN (LTYPE (tree)))
+            SPEC_USIGN (TTYPE (tree)) = SPEC_USIGN (LTYPE (tree));
+        }
+      else
+        {
+          TTYPE (tree) = TETYPE (tree) = newIntLink ();
+          SPEC_USIGN (TTYPE (tree)) = 0;
+        }
       return tree;
 
       /*------------------------------------------------------------------*/
@@ -4595,7 +4685,6 @@
       TETYPE (tree) = LETYPE (tree);
       return tree;
 
-    case GETHBIT:
     case GETABIT:
       TTYPE (tree) = TETYPE (tree) = (resultTypeProp == RESULT_TYPE_BOOL) ? newBoolLink () : newCharLink ();
       return tree;
@@ -4629,8 +4718,8 @@
       /* rewrite the tree */
       if (IS_LITERAL (RTYPE (tree)) && IS_LITERAL (LTYPE (tree)))
         {
-          rewriteAstNodeVal (tree, valShift (valFromType (LETYPE (tree)), valFromType (RETYPE (tree)), (tree->opval.op == LEFT_OP ? 1 : 0)));
-          return decorateType (tree, resultType);
+          rewriteAstNodeVal (tree, valShift (valFromType (LETYPE (tree)), valFromType (RETYPE (tree)), (tree->opval.op == LEFT_OP ? 1 : 0), reduceTypeAllowed));
+          return decorateType (tree, resultType, reduceTypeAllowed);
         }
 
       /* see if this is a GETBYTE operation if yes
@@ -4639,7 +4728,7 @@
         ast *otree = optimizeGetByte (tree, resultType);
 
         if (otree != tree)
-          return decorateType (otree, RESULT_TYPE_NONE);
+          return decorateType (otree, RESULT_TYPE_NONE, reduceTypeAllowed);
       }
 
       /* see if this is a GETWORD operation if yes
@@ -4648,11 +4737,21 @@
         ast *otree = optimizeGetWord (tree, resultType);
 
         if (otree != tree)
-          return decorateType (otree, RESULT_TYPE_NONE);
+          return decorateType (otree, RESULT_TYPE_NONE, reduceTypeAllowed);
       }
 
       LRVAL (tree) = RRVAL (tree) = 1;
-      if (tree->opval.op == LEFT_OP)
+      if(!reduceTypeAllowed)
+        {
+          TETYPE (tree) = getSpec (TTYPE (tree) = computeType (LTYPE (tree), NULL, resultType, tree->opval.op));
+          if(IS_INTEGRAL (TETYPE (tree)) && bitsForType (TETYPE (tree)) < INTSIZE * 8)
+            {
+              // Promote to int for smaller types
+              SPEC_NOUN (TETYPE (tree)) = V_INT;
+              SPEC_USIGN (TETYPE (tree)) = 0;
+            }
+        }
+      else if ((tree->opval.op == LEFT_OP))
         {
           TETYPE (tree) = getSpec (TTYPE (tree) = computeType (LTYPE (tree), NULL, resultType, tree->opval.op));
         }
@@ -4664,9 +4763,19 @@
             SPEC_SCLS (TTYPE (tree)) &= ~S_LITERAL;
         }
 
+      if (IS_LITERAL (RTYPE (tree)) && floatFromVal (valFromType (RETYPE (tree))) < 0)
+        {
+          werrorfl (tree->filename, tree->lineno, W_SHIFT_NEGATIVE, (tree->opval.op == LEFT_OP ? "left" : "right"));
+          /* Change shift op to comma op and replace the right operand with 0. */
+          /* This preserves the left operand in case there were side-effects. */
+          tree->opval.op = ',';
+          tree->right->opval.val = valZeroResultFromOp(LTYPE (tree), RTYPE (tree), tree->opval.op, reduceTypeAllowed);
+          TETYPE (tree) = TTYPE (tree) = tree->right->opval.val->type;
+          return tree;
+        }
       /* if only the right side is a literal & we are
          shifting more than size of the left operand then zero */
-      if (IS_LITERAL (RTYPE (tree)) &&
+      else if (IS_LITERAL (RTYPE (tree)) &&
           ((TYPE_TARGET_ULONG) ulFromVal (valFromType (RETYPE (tree)))) >= (getSize (TETYPE (tree)) * 8))
         {
           if (tree->opval.op == LEFT_OP || (tree->opval.op == RIGHT_OP && SPEC_USIGN (LETYPE (tree))))
@@ -4675,7 +4784,7 @@
               /* Change shift op to comma op and replace the right operand with 0. */
               /* This preserves the left operand in case there were side-effects. */
               tree->opval.op = ',';
-              tree->right->opval.val = constVal ("0");
+              tree->right->opval.val = valZeroResultFromOp(LTYPE (tree), RTYPE (tree), tree->opval.op, reduceTypeAllowed);
               TETYPE (tree) = TTYPE (tree) = tree->right->opval.val->type;
               return tree;
             }
@@ -4931,11 +5040,11 @@
       /* rewrite the tree */
       if (IS_LITERAL (RTYPE (tree)) && IS_LITERAL (LTYPE (tree)))
         {
-          rewriteAstNodeVal (tree, valLogicAndOr (valFromType (LETYPE (tree)), valFromType (RETYPE (tree)), tree->opval.op));
-          return decorateType (tree, resultType);
+          rewriteAstNodeVal (tree, valLogicAndOr (valFromType (LETYPE (tree)), valFromType (RETYPE (tree)), tree->opval.op, reduceTypeAllowed));
+          return decorateType (tree, resultType, reduceTypeAllowed);
         }
       LRVAL (tree) = RRVAL (tree) = 1;
-      TTYPE (tree) = TETYPE (tree) = (resultTypeProp == RESULT_TYPE_BOOL) ? newBoolLink () : newCharLink ();
+      TTYPE (tree) = TETYPE (tree) = reduceTypeAllowed ? ((resultTypeProp == RESULT_TYPE_BOOL) ? newBoolLink () : newCharLink ()) : newIntLink();
       return tree;
 
       /*------------------------------------------------------------------*/
@@ -5036,7 +5145,8 @@
           case CCR_ALWAYS_TRUE:
           case CCR_ALWAYS_FALSE:
             werrorfl (tree->filename, tree->lineno, W_COMP_RANGE, ccr_result == CCR_ALWAYS_TRUE ? "true" : "false");
-            newResult = newAst_VALUE (constBoolVal ((unsigned char) (ccr_result == CCR_ALWAYS_TRUE)));
+            newResult = newAst_VALUE (constBoolVal ((unsigned char) (ccr_result == CCR_ALWAYS_TRUE), reduceTypeAllowed));
+
             /* If there are side effects, join the non-literal side */
             /* to the boolean result with a comma operator */
             if (hasSEFcalls (tree))
@@ -5046,7 +5156,7 @@
                 else
                   newResult = newNode (',', tree->right, newResult);
               }
-            return decorateType (newResult, resultType);
+            return decorateType (newResult, resultType, reduceTypeAllowed);
           case CCR_OK:
           default:
             break;
@@ -5066,13 +5176,13 @@
 
           /* (unsigned value) ? 1 : 0 */ /* TODO: Casts to _Bools tend to result in far more efficient code than '?' */
           tree->opval.op = '?';
-          tree->right = newNode (':', newAst_VALUE (constBoolVal (1)), tree->right);    /* val 0 */
+          tree->right = newNode (':', newAst_VALUE (constBoolVal (1, reduceTypeAllowed)), tree->right);    /* val 0 */
           tree->right->filename = tree->filename;
           tree->right->lineno = tree->lineno;
           tree->right->left->filename = tree->filename;
           tree->right->left->lineno = tree->lineno;
           tree->decorated = 0;
-          return decorateType (tree, resultType);
+          return decorateType (tree, resultType, reduceTypeAllowed);
         }
 
       /* 'ifx (0 == op)' -> 'ifx (!(op))' */
@@ -5081,7 +5191,7 @@
           tree->opval.op == EQ_OP && (resultType == RESULT_TYPE_IFX || resultType == RESULT_TYPE_BOOL))
         {
           rewriteAstNodeOp (tree, '!', tree->right, NULL);
-          return decorateType (tree, resultType);
+          return decorateType (tree, resultType, reduceTypeAllowed);
         }
 
       /* 'ifx (op == 0)' -> 'ifx (!(op))' */
@@ -5090,7 +5200,7 @@
           tree->opval.op == EQ_OP && (resultType == RESULT_TYPE_IFX || resultType == RESULT_TYPE_BOOL))
         {
           rewriteAstNodeOp (tree, '!', tree->left, NULL);
-          return decorateType (tree, resultType);
+          return decorateType (tree, resultType, reduceTypeAllowed);
         }
 
       /* 'ifx (op == 1)' -> 'ifx (op)' for bool */
@@ -5099,15 +5209,15 @@
           tree->opval.op == EQ_OP && (resultType == RESULT_TYPE_IFX || resultType == RESULT_TYPE_BOOL))
         {
           tree = tree->left;
-          return decorateType (tree, resultType);
+          return decorateType (tree, resultType, reduceTypeAllowed);
         }
 
       /* if they are both literal then */
       /* rewrite the tree */
       if (IS_LITERAL (RETYPE (tree)) && IS_LITERAL (LETYPE (tree)))
         {
-          rewriteAstNodeVal (tree, valCompare (valFromType (LETYPE (tree)), valFromType (RETYPE (tree)), tree->opval.op));
-          return decorateType (tree, resultType);
+          rewriteAstNodeVal (tree, valCompare (valFromType (LETYPE (tree)), valFromType (RETYPE (tree)), tree->opval.op, reduceTypeAllowed));
+          return decorateType (tree, resultType, reduceTypeAllowed);
         }
 
       /* if one is 'signed char ' and the other one is 'unsigned char' */
@@ -5147,7 +5257,13 @@
         }
 
       LRVAL (tree) = RRVAL (tree) = 1;
-      TTYPE (tree) = TETYPE (tree) = (resultType == RESULT_TYPE_BOOL) ? newBoolLink () : newCharLink ();
+      if (reduceTypeAllowed)
+          TTYPE (tree) = TETYPE (tree) = (resultType == RESULT_TYPE_BOOL) ? newBoolLink () : newCharLink ();
+      else
+        {
+          TTYPE (tree) = TETYPE (tree) = newIntLink ();
+          SPEC_USIGN (TTYPE (tree)) = 0;
+        }
 
       /* condition transformations */
       {
@@ -5189,7 +5305,7 @@
             tree = newNode ('!', tree, NULL);
             tree->filename = tree->left->filename;
             tree->lineno = tree->left->lineno;
-            return decorateType (tree, resultType);
+            return decorateType (tree, resultType, reduceTypeAllowed);
           }
       }
 
@@ -5326,7 +5442,7 @@
           ast * heir;
           
           ++noAlloc;
-          tree->right = decorateType (tree->right, resultTypeProp);
+          tree->right = decorateType (tree->right, resultTypeProp, reduceTypeAllowed);
           --noAlloc;
 
           if (((int) ulFromVal (valFromType (LETYPE (tree)))) != 0)
@@ -5334,7 +5450,7 @@
           else
             heir = tree->right->right;
             
-          heir = decorateType (heir, resultTypeProp);
+          heir = decorateType (heir, resultTypeProp, reduceTypeAllowed);
           if (IS_LITERAL (TETYPE (heir)))
             TTYPE (heir) = valRecastLitVal (TTYPE (tree->right), valFromType (TETYPE (heir)))->type;
           else
@@ -5343,7 +5459,7 @@
           return heir;
         }
 
-      tree->right = decorateType (tree->right, resultTypeProp);
+      tree->right = decorateType (tree->right, resultTypeProp, reduceTypeAllowed);
 
       if (IS_AST_LIT_VALUE (tree->right->left) && IS_AST_LIT_VALUE (tree->right->right) &&
           ((resultType == RESULT_TYPE_IFX) || (resultType == RESULT_TYPE_BOOL)))
@@ -5355,7 +5471,7 @@
             {
               /* assign cond to result */
               tree->left->decorated = 0;
-              return decorateType (tree->left, resultTypeProp);
+              return decorateType (tree->left, resultTypeProp, reduceTypeAllowed);
             }
           else if ((valTrue == 0) && (valFalse != 0))
             {
@@ -5363,7 +5479,7 @@
               tree->opval.op = '!';
               tree->decorated = 0;
               tree->right = NULL;
-              return decorateType (tree, resultTypeProp);
+              return decorateType (tree, resultTypeProp, reduceTypeAllowed);
             }
           else
             {
@@ -5425,6 +5541,8 @@
         if (!found_expr)
           {
             werror (E_NO_MATCH_IN_GENERIC);
+            printTypeChain (type, stderr);
+            fprintf (stderr, "\n");
             goto errorTreeReturn;
           }
         
@@ -5582,7 +5700,7 @@
           goto errorTreeReturn;
         }
 
-      tree->right = decorateType (newNode ('+', copyAst (tree->left), tree->right), RESULT_TYPE_NONE);
+      tree->right = decorateType (newNode ('+', copyAst (tree->left), tree->right), RESULT_TYPE_NONE, reduceTypeAllowed);
       tree->opval.op = '=';
 
       return tree;
@@ -5739,7 +5857,7 @@
               tree->right->values.cast.implicitCast = 1;
               tree->right->lineno = tree->right->left->lineno = tree->lineno;
               tree->right->filename = tree->right->left->filename = tree->filename;
-              tree->right = decorateType (tree->right, IS_GENPTR (currFunc->type->next) ? RESULT_TYPE_GPTR : RESULT_TYPE_NONE);
+              tree->right = decorateType (tree->right, IS_GENPTR (currFunc->type->next) ? RESULT_TYPE_GPTR : RESULT_TYPE_NONE, reduceTypeAllowed);
             }
           else if (!typecompat)
             {
@@ -5791,9 +5909,9 @@
       /*----------------------------*/
     case FOR:
 
-      AST_FOR (tree, initExpr) = decorateType (resolveSymbols (AST_FOR (tree, initExpr)), RESULT_TYPE_NONE);
-      AST_FOR (tree, condExpr) = decorateType (resolveSymbols (AST_FOR (tree, condExpr)), RESULT_TYPE_NONE);
-      AST_FOR (tree, loopExpr) = decorateType (resolveSymbols (AST_FOR (tree, loopExpr)), RESULT_TYPE_NONE);
+      AST_FOR (tree, initExpr) = decorateType (resolveSymbols (AST_FOR (tree, initExpr)), RESULT_TYPE_NONE, reduceTypeAllowed);
+      AST_FOR (tree, condExpr) = decorateType (resolveSymbols (AST_FOR (tree, condExpr)), RESULT_TYPE_NONE, reduceTypeAllowed);
+      AST_FOR (tree, loopExpr) = decorateType (resolveSymbols (AST_FOR (tree, loopExpr)), RESULT_TYPE_NONE, reduceTypeAllowed);
 
       /* if the for loop is reversible then
          reverse it otherwise do what we normally
@@ -5817,7 +5935,7 @@
                                 AST_FOR (tree, loopExpr),
                                 tree->left,
                                 tree->right);
-            return decorateType (tree, RESULT_TYPE_NONE);
+            return decorateType (tree, RESULT_TYPE_NONE, reduceTypeAllowed);
           }
         else
           {
@@ -5830,7 +5948,7 @@
                               AST_FOR (tree, loopExpr),
                               tree->left,
                               tree->right);
-            return decorateType (tree, RESULT_TYPE_NONE);
+            return decorateType (tree, RESULT_TYPE_NONE, reduceTypeAllowed);
           }
       }
     case PARAM:
@@ -6073,7 +6191,7 @@
       return NULL;
     }
 
-  caseVal = decorateType (resolveSymbols (caseVal), RESULT_TYPE_NONE);
+  caseVal = decorateType (resolveSymbols (caseVal), RESULT_TYPE_NONE, true);
   /* if not a constant then error  */
   if (!IS_LITERAL (caseVal->ftype))
     {
@@ -6436,40 +6554,6 @@
 }
 
 /*-----------------------------------------------------------------*/
-/* optimizeGetHbit - get highest order bit of the expression       */
-/*-----------------------------------------------------------------*/
-ast *
-optimizeGetHbit (ast * tree, RESULT_TYPE resultType)
-{
-  unsigned int bit, msb;
-  ast *expr;
-
-  expr = isShiftRightLitVal_BitAndLitVal (tree);
-  if (expr)
-    {
-      if ((AST_ULONG_VALUE (tree->right) != 1) ||
-          ((bit = AST_ULONG_VALUE (tree->left->right)) != (msb = (bitsForType (TTYPE (expr)) - 1))))
-        expr = NULL;
-    }
-  if (!expr && (resultType == RESULT_TYPE_BOOL))
-    {
-      int bit = isBitAndPow2 (tree);
-      expr = tree->left;
-      msb = bitsForType (TTYPE (expr)) - 1;
-      if ((bit < 0) || (bit != (int) msb))
-        expr = NULL;
-    }
-  if (!expr || IS_BOOLEAN (TTYPE (expr)))
-    return tree;
-
-  /* make sure the port supports GETHBIT */
-  if (port->hasExtBitOp && !port->hasExtBitOp (GETHBIT, getSize (TTYPE (expr))))
-    return tree;
-
-  return decorateType (newNode (GETHBIT, expr, NULL), resultType);
-}
-
-/*-----------------------------------------------------------------*/
 /* optimizeGetAbit - get a single bit of the expression            */
 /*-----------------------------------------------------------------*/
 ast *
@@ -6501,7 +6585,7 @@
   if (port->hasExtBitOp && !port->hasExtBitOp (GETABIT, getSize (TTYPE (expr))))
     return tree;
 
-  return decorateType (newNode (GETABIT, expr, count), resultType);
+  return decorateType (newNode (GETABIT, expr, count), resultType, true);
 }
 
 /*-----------------------------------------------------------------*/
@@ -6543,7 +6627,7 @@
   if (port->hasExtBitOp && !port->hasExtBitOp (GETBYTE, size))
     return tree;
 
-  return decorateType (newNode (GETBYTE, expr, count), RESULT_TYPE_NONE);
+  return decorateType (newNode (GETBYTE, expr, count), RESULT_TYPE_NONE, true);
 }
 
 /*-----------------------------------------------------------------*/
@@ -6586,7 +6670,7 @@
   if (port->hasExtBitOp && !port->hasExtBitOp (GETWORD, size))
     return tree;
 
-  return decorateType (newNode (GETWORD, expr, count), RESULT_TYPE_NONE);
+  return decorateType (newNode (GETWORD, expr, count), RESULT_TYPE_NONE, true);
 }
 
 /*-----------------------------------------------------------------*/
@@ -6632,6 +6716,10 @@
       if (AST_ULONG_VALUE (root->right->right) != (getSize (TTYPE (root->left->left)) * 8 - 1))
         goto tryNext0;
 
+      /* cannot have side effects or volatility */
+      if (hasSEFcalls (root))
+        return root;
+
       /* make sure the port supports RLC */
       if (port->hasExtBitOp && !port->hasExtBitOp (RLC, getSize (TTYPE (root->left->left))))
         return root;
@@ -6662,6 +6750,10 @@
       if (AST_ULONG_VALUE (root->left->right) != (getSize (TTYPE (root->left->left)) * 8 - 1))
         goto tryNext1;
 
+      /* cannot have side effects or volatility */
+      if (hasSEFcalls (root))
+        return root;
+
       /* make sure the port supports RLC */
       if (port->hasExtBitOp && !port->hasExtBitOp (RLC, getSize (TTYPE (root->left->left))))
         return root;
@@ -6693,6 +6785,10 @@
       if (AST_ULONG_VALUE (root->right->right) != (getSize (TTYPE (root->left->left)) * 8 - 1))
         goto tryNext2;
 
+      /* cannot have side effects or volatility */
+      if (hasSEFcalls (root))
+        return root;
+
       /* make sure the port supports RRC */
       if (port->hasExtBitOp && !port->hasExtBitOp (RRC, getSize (TTYPE (root->left->left))))
         return root;
@@ -6722,6 +6818,10 @@
       if (AST_ULONG_VALUE (root->left->right) != (getSize (TTYPE (root->left->left)) * 8 - 1))
         return root;
 
+      /* cannot have side effects or volatility */
+      if (hasSEFcalls (root))
+        return root;
+
       /* make sure the port supports RRC */
       if (port->hasExtBitOp && !port->hasExtBitOp (RRC, getSize (TTYPE (root->left->left))))
         return root;
@@ -6769,6 +6869,10 @@
 
       if (AST_ULONG_VALUE (root->right->right) != (getSize (TTYPE (root->left->left)) * 4))
         return root;
+      
+      /* cannot have side effects or volatility */
+      if (hasSEFcalls (root))
+        return root;
 
       /* make sure the port supports SWAP */
       if (port->hasExtBitOp && !port->hasExtBitOp (SWAP, getSize (TTYPE (root->left->left))))
@@ -6814,16 +6918,16 @@
         case '>':
         case '<':
         case NE_OP:
-          optExpr = newAst_VALUE (constBoolVal (0));
+          optExpr = newAst_VALUE (constBoolVal (0, true));
           break;
         case GE_OP:
         case LE_OP:
         case EQ_OP:
-          optExpr = newAst_VALUE (constBoolVal (1));
+          optExpr = newAst_VALUE (constBoolVal (1, true));
           break;
         }
 
-      return decorateType (optExpr, RESULT_TYPE_NONE);
+      return decorateType (optExpr, RESULT_TYPE_NONE, true);
     }
 
   vleft = (root->left->type == EX_VALUE ? root->left->opval.val : NULL);
@@ -6891,7 +6995,7 @@
               break;
             }
         }
-      return decorateType (resolveSymbols (optExpr), RESULT_TYPE_NONE);
+      return decorateType (resolveSymbols (optExpr), RESULT_TYPE_NONE, true);
     }                           /* end-of-if of BITVAR */
 
 noOptimize:
@@ -6928,12 +7032,9 @@
 static void
 processRegParms (value * args, ast * body)
 {
-  while (args)
-    {
-      if (IS_REGPARM (args->etype))
-        addSymToBlock (args->sym, body);
-      args = args->next;
-    }
+  for (; args; args = args->next)
+    if (IS_REGPARM (args->etype) && args->sym)
+      addSymToBlock (args->sym, body);
 }
 
 /*-----------------------------------------------------------------*/
@@ -6960,9 +7061,9 @@
 {
   struct dbuf_s dbuf;
 
-  dbuf_init (&dbuf, 128);
+  dbuf_init (&dbuf, SDCC_SYMNAME_MAX+1);
   dbuf_printf (&dbuf, "%s_%d", sym->name, inlineState.count);
-  strncpyz (sym->name, dbuf_c_str (&dbuf), SDCC_NAME_MAX);
+  strncpyz (sym->name, dbuf_c_str (&dbuf), SDCC_SYMNAME_MAX);
   dbuf_destroy (&dbuf);
 }
 
@@ -7040,6 +7141,7 @@
 
   tree->level = level;
   tree->block = currBlockno;
+  tree->inlined = 1;
 
   /* Update symbols */
   if (IS_AST_VALUE (tree) && tree->opval.val->sym)
@@ -7357,7 +7459,7 @@
           args = FUNC_ARGS (func->type);
           argIndex = 0;
 
-          while (args)
+          for (; args; args = args->next, argIndex++)
             {
               symbol *temparg;
               ast *assigntree;
@@ -7370,6 +7472,9 @@
                   break;
                 }
 
+              if (!args->sym) /* skip arg if it's missing a name */
+                continue;
+
               temparg = inlineTempVar (args->sym->type, tree->level + LEVEL_UNIT);
               inlineAddDecl (copySymbol (temparg), inlinetree, FALSE, FALSE);
 
@@ -7385,34 +7490,27 @@
               assigntree->initMode = 1; // tell that assignment is initializer
               inlinetree2->right = newNode (NULLOP, assigntree, inlinetree2->right);
               parm->onStack = 0; // stack usage will be recomputed later
-
-              args = args->next;
-              argIndex++;
             }
 
           if (inlineFindParm (tree->right, argIndex) && !IFFUNC_HASVARARGS (func->type))
             werror (E_TOO_MANY_PARMS);
 
           /* Handle the return type */
-          if (!IS_VOID (func->type->next))
-            {
-              /* Generate return symbol coma statement;                   */
-              /* ...                                                      */
-              /* {{inline_function_code}}, retsym                         */
-
-              tree->opval.op = ',';
-              if (IFFUNC_ISCRITICAL (func->type))
-                inlinetree = newNode (CRITICAL, inlinetree, NULL);
-              tree->left = inlinetree;
+          /* Generate return symbol coma statement;                   */
+          /* ...                                                      */
+          /* {{inline_function_code}}, retsym                         */
+          tree->opval.op = ',';
+          if (IFFUNC_ISCRITICAL (func->type))
+            inlinetree = newNode (CRITICAL, inlinetree, NULL);
+          tree->left = inlinetree;
+          if (retsym)
               tree->right = newAst_VALUE (symbolVal (retsym));
-            }
           else
             {
-              tree->opval.op = NULLOP;
-              if (IFFUNC_ISCRITICAL (func->type))
-                inlinetree = newNode (CRITICAL, inlinetree, NULL);
-              tree->left = NULL;
-              tree->right = inlinetree;
+              /* create a literal void if the return type is void */
+              value * voidval = valFromType (newVoidLink ());
+              SPEC_SCLS (voidval->type) = S_LITERAL;
+              tree->right = newAst_VALUE (voidval);
             }
           inlineState.retsym = retsym;
 
@@ -7601,7 +7699,7 @@
   SNPRINTF (name->rname, sizeof (name->rname), "%s%s", port->fun_prefix, name->name);
 
   body = resolveSymbols (body); /* resolve the symbols */
-  body = decorateType (body, RESULT_TYPE_NONE); /* propagateType & do semantic checks */
+  body = decorateType (body, RESULT_TYPE_NONE, true); /* propagateType & do semantic checks */
 
   /* save the stack information */
   if (options.useXstack)
@@ -7646,7 +7744,7 @@
     {
       GcurMemmap = statsg;
       codeOutBuf = &statsg->oBuf;
-      eBBlockFromiCode (iCodeFromAst (decorateType (resolveSymbols (staticAutos), RESULT_TYPE_NONE)));
+      eBBlockFromiCode (iCodeFromAst (decorateType (resolveSymbols (staticAutos), RESULT_TYPE_NONE, true)));
       staticAutos = NULL;
     }
 
@@ -8115,13 +8213,6 @@
       ast_print (tree->left, outfile, indent + 2);
       return;
 
-    case GETHBIT:
-      fprintf (outfile, "GETHBIT (%p) type (", tree);
-      printTypeChain (tree->ftype, outfile);
-      fprintf (outfile, ")\n");
-      ast_print (tree->left, outfile, indent + 2);
-      return;
-
     case GETABIT:
       fprintf (outfile, "GETABIT (%p) type (", tree);
       printTypeChain (tree->ftype, outfile);
@@ -8565,17 +8656,17 @@
  */
 
 static ast *
-offsetofOp_rec (sym_link * type, ast * snd, sym_link ** result_type)
+offsetofOp_rec (sym_link *type, ast *snd, sym_link **result_type)
 {
   /* make sure the type is complete and sane */
   checkTypeSanity (type, "(offsetofOp)");
 
   /* offsetof can only be applied to structs/unions */
-  if (!IS_STRUCT (type))
+  if (!IS_STRUCT (type) || !getSize (type))
     {
       werrorfl (snd->filename, snd->lineno, E_OFFSETOF_TYPE);
-      *result_type = NULL;
-      return NULL;
+      *result_type = 0;
+      return newAst_VALUE (valueFromLit (0));
     }
 
   /* offsetof(struct_type, symbol); */
@@ -8609,8 +8700,10 @@
 }
 
 ast *
-offsetofOp (sym_link * type, ast * snd)
+offsetofOp (sym_link *type, ast *snd)
 {
   sym_link *result_type;
+
   return offsetofOp_rec (type, snd, &result_type);
 }
+
diff -Nru sdcc-4.0.0+dfsg/src/SDCCast.h sdcc-4.2.0+dfsg/src/SDCCast.h
--- sdcc-4.0.0+dfsg/src/SDCCast.h	2018-06-17 07:38:22.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/SDCCast.h	2021-07-05 00:58:42.000000000 +0000
@@ -50,6 +50,7 @@
   unsigned lvalue:1;
   unsigned initMode:1;
   unsigned reversed:1;
+  unsigned inlined:1;
   long level;                   /* level for expr */
   int block;                    /* block number   */
   int seqPoint;                 /* sequence point */
@@ -212,7 +213,7 @@
 ast *resolveSymbols (ast *);
 void CodePtrPointsToConst (sym_link * t);
 void checkPtrCast (sym_link * newType, sym_link * orgType, bool implicit, bool orgIsNullPtrConstant);
-ast *decorateType (ast *, RESULT_TYPE);
+ast *decorateType (ast *, RESULT_TYPE, bool reduceTypeAllowed);
 ast *createWhile (symbol *, symbol *, symbol *, ast *, ast *);
 ast *createIf (ast *, ast *, ast *);
 ast *createDo (symbol *, symbol *, symbol *, ast *, ast *);
diff -Nru sdcc-4.0.0+dfsg/src/SDCCattr.c sdcc-4.2.0+dfsg/src/SDCCattr.c
--- sdcc-4.0.0+dfsg/src/SDCCattr.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/SDCCattr.c	2021-02-05 05:36:42.000000000 +0000
@@ -0,0 +1,72 @@
+/*-------------------------------------------------------------------------
+  SDCCattr.h - Code file for attributes.
+
+  Copyright (c) 2021 Philipp Klaus Krause pkk@spth.de
+
+  This program is free software; you can redistribute it and/or modify it
+  under the terms of the GNU General Public License as published by the
+  Free Software Foundation; either version 2, or (at your option) any
+  later version.
+
+  This program is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+  GNU General Public License for more details.
+
+  You should have received a copy of the GNU General Public License
+  along with this program; if not, write to the Free Software
+  Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+-------------------------------------------------------------------------*/
+
+#include "SDCCattr.h"
+#include "SDCCsymt.h"
+#include "SDCCutil.h"
+#include "newalloc.h"
+
+attribute *newAttribute(const symbol *token_sym, const char *argument_clause)
+{
+  const char *token_string, *token_string_prefix;
+
+  attribute *attr = Safe_alloc (sizeof (attribute));
+  
+  attr->next = 0;
+
+  wassert (token_sym);
+  
+  if(token_sym->next)
+    {
+      token_string = token_sym->next->name;
+      token_string_prefix = token_sym->name;
+    }
+  else
+    {
+      token_string = token_sym->name;
+      token_string_prefix = 0;
+    }
+
+  wassert(token_string);
+  strncpyz (attr->token_string, token_string, sizeof (attr->token_string));
+
+  if (!token_string_prefix)
+    {
+      if(!strcmp(token_string, "nodiscard") || !strcmp(token_string, "__nodiscard__"))
+        attr->token = ATTRIBUTE_NODISCARD;
+      else if(!strcmp(token_string, "maybe_unused") || !strcmp(token_string, "__maybe_unused__"))
+        attr->token = ATTRIBUTE_MAYBE_UNUSED;
+      else if(!strcmp(token_string, "deprecated") || !strcmp(token_string, "__deprecated__"))
+        attr->token = ATTRIBUTE_DEPRECATED;
+      else if(!strcmp(token_string, "fallthrough") || !strcmp(token_string, "__fallthrough__"))
+        attr->token = ATTRIBUTE_FALLTHROUGH;
+      else // Unknown standard attribute
+        attr->token = ATTRIBUTE_OTHER;
+    }
+  else if(!strcmp(token_string_prefix, "sdcc")) // SDCC implementation-specific attribute
+    {
+      attr->token = ATTRIBUTE_OTHER;
+    }
+  else // Unknown-implementation implementation-specific unknown attribute.
+    attr->token = ATTRIBUTE_OTHER;
+    
+  return attr;
+}
+
diff -Nru sdcc-4.0.0+dfsg/src/SDCCattr.h sdcc-4.2.0+dfsg/src/SDCCattr.h
--- sdcc-4.0.0+dfsg/src/SDCCattr.h	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/SDCCattr.h	2021-02-02 11:58:59.000000000 +0000
@@ -0,0 +1,49 @@
+/*-------------------------------------------------------------------------
+  SDCCattr.h - Header file for attributes.
+
+  Copyright (c) 2021 Philipp Klaus Krause pkk@spth.de
+
+  This program is free software; you can redistribute it and/or modify it
+  under the terms of the GNU General Public License as published by the
+  Free Software Foundation; either version 2, or (at your option) any
+  later version.
+
+  This program is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+  GNU General Public License for more details.
+
+  You should have received a copy of the GNU General Public License
+  along with this program; if not, write to the Free Software
+  Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+-------------------------------------------------------------------------*/
+
+#ifndef SDCCATTR_H
+#define SDCCATTR_H 1
+
+struct symbol;
+typedef struct symbol symbol;
+
+typedef enum
+{
+  ATTRIBUTE_NODISCARD = 1,
+  ATTRIBUTE_MAYBE_UNUSED,
+  ATTRIBUTE_DEPRECATED,
+  ATTRIBUTE_FALLTHROUGH,
+  ATTRIBUTE_OTHER
+} ATTRIBUTE_TOKEN;
+
+typedef struct attribute
+{
+  ATTRIBUTE_TOKEN token;
+  char token_string[32];
+  char argument_clause[32];
+  
+  struct attribute *next;	// Next attribute in attribute list.
+}
+attribute;
+
+attribute *newAttribute(const symbol *token_sym, const char *argument_clause);
+
+#endif
+
diff -Nru sdcc-4.0.0+dfsg/src/SDCCBBlock.c sdcc-4.2.0+dfsg/src/SDCCBBlock.c
--- sdcc-4.0.0+dfsg/src/SDCCBBlock.c	2018-10-08 10:10:30.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/SDCCBBlock.c	2020-05-18 08:57:45.000000000 +0000
@@ -125,7 +125,7 @@
       dbuf_append_str (&dumpFileName, dumpFilesPtr->ext);
       if (!(dumpFilesPtr->filePtr = fopen (dbuf_c_str (&dumpFileName), "w")))
         {
-          werror (E_FILE_OPEN_ERR, dbuf_c_str (&dumpFileName));
+          werror (E_OUTPUT_FILE_OPEN_ERR, dbuf_c_str (&dumpFileName), strerror (errno));
           dbuf_destroy (&dumpFileName);
           exit (1);
         }
diff -Nru sdcc-4.0.0+dfsg/src/SDCCBBlock.h sdcc-4.2.0+dfsg/src/SDCCBBlock.h
--- sdcc-4.0.0+dfsg/src/SDCCBBlock.h	2018-10-08 10:10:30.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/SDCCBBlock.h	2022-02-03 09:32:48.000000000 +0000
@@ -57,8 +57,8 @@
   set *inExprs;                 /* in coming common expressions    */
   set *outExprs;                /* out going common expressions    */
   set *killedExprs;             /* killed common expressions       */
-  bitVect *inDefs;              /* in coming defintions            */
-  bitVect *outDefs;             /* out going defintions            */
+  bitVect *inDefs;              /* in coming definitions           */
+  bitVect *outDefs;             /* out going definitions           */
   bitVect *defSet;              /* symbols defined in block        */
   bitVect *ldefs;               /* local definitions only          */
   bitVect *usesDefs;            /* which definitions are used in this block */
diff -Nru sdcc-4.0.0+dfsg/src/SDCCbtree.cc sdcc-4.2.0+dfsg/src/SDCCbtree.cc
--- sdcc-4.0.0+dfsg/src/SDCCbtree.cc	2019-03-14 16:34:34.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/SDCCbtree.cc	2021-04-13 08:09:42.000000000 +0000
@@ -57,7 +57,7 @@
   btree_clear_subtree(0);
 }
 
-void btree_add_child(short parent, short child)
+void btree_add_child(int parent, int child)
 {
 #ifdef BTREE_DEBUG
   std::cout << "Adding child " << child << " at parent " << parent << "\n"; std::cout.flush();
@@ -94,7 +94,7 @@
   return(btree_lowest_common_ancestor(a, b));
 }
 
-short btree_lowest_common_ancestor(short a, short b)
+int btree_lowest_common_ancestor(int a, int b)
 {
   return(bmaprev[btree_lowest_common_ancestor_impl(bmap[a], bmap[b])]);
 }
diff -Nru sdcc-4.0.0+dfsg/src/SDCCbtree.h sdcc-4.2.0+dfsg/src/SDCCbtree.h
--- sdcc-4.0.0+dfsg/src/SDCCbtree.h	2012-12-27 12:01:01.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/SDCCbtree.h	2021-04-13 08:09:42.000000000 +0000
@@ -24,10 +24,10 @@
 void btree_clear(void);
 
 // Add child as a sub-block of parent.
-void btree_add_child(short parent, short child);
+void btree_add_child(int parent, int child);
 
 // Gives the lowest common ancestor for blocks a and b.
-short btree_lowest_common_ancestor(short a, short b);
+int btree_lowest_common_ancestor(int a, int b);
 
 // Add symbol to block tree for allocation.
 void btree_add_symbol(struct symbol *s);
diff -Nru sdcc-4.0.0+dfsg/src/SDCCcse.c sdcc-4.2.0+dfsg/src/SDCCcse.c
--- sdcc-4.0.0+dfsg/src/SDCCcse.c	2019-05-29 08:11:58.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/SDCCcse.c	2021-06-08 11:57:11.000000000 +0000
@@ -1029,7 +1029,7 @@
       /* if subtracting the same thing then zero     */
       if (IC_LEFT (ic)->key == IC_RIGHT (ic)->key &&
         !IS_OP_VOLATILE (IC_LEFT (ic)))
-        {printf("Sub. at %d\n", ic->key);
+        {
           ic->op = '=';
           IC_RIGHT (ic) = operandFromLit (0);
           IC_LEFT (ic) = NULL;
@@ -1691,44 +1691,50 @@
           ReplaceOpWithCheaperOp(&IC_COND (ic), pdop);
           (*change)++;
         }
-      else if(ic->prev &&  /* Remove unnecessary casts */
-        (ic->prev->op == '=' || ic->prev->op == CAST || ic->prev->op == '!') && IS_ITEMP (IC_RESULT (ic->prev)) &&
-        IC_RESULT (ic->prev)->key == IC_COND (ic)->key && bitVectnBitsOn (OP_USES (IC_RESULT (ic->prev))) <= 1)
-        {
-          sym_link *type = operandType (IC_RESULT (ic->prev));
-          if (ic->prev->op != CAST || IS_BOOL (type) || bitsForType (operandType (IC_RIGHT (ic->prev))) < bitsForType (type))
-          {
-            if (!isOperandVolatile (ic->prev->op == '!' ? IC_LEFT (ic->prev) : IC_RIGHT (ic->prev), FALSE))
-              {
-                if (ic->prev->op =='!') /* Invert jump logic */
-                  {
-                    symbol *tmp = IC_TRUE (ic);
-                    IC_TRUE (ic) = IC_FALSE (ic);
-                    IC_FALSE (ic) = tmp;
-                  }
-                bitVectUnSetBit (OP_USES (IC_COND (ic)), ic->key);
-                ReplaceOpWithCheaperOp(&IC_COND (ic), ic->prev->op == '!' ? IC_LEFT (ic->prev) : IC_RIGHT (ic->prev));
-                (*change)++;
-              }
+      else if (ic->prev &&  /* Remove unnecessary casts */
+               (ic->prev->op == '=' || ic->prev->op == CAST || ic->prev->op == '!') &&
+               IS_ITEMP (IC_RESULT (ic->prev)) &&
+               IC_RESULT (ic->prev)->key == IC_COND (ic)->key &&
+               bitVectnBitsOn (OP_USES (IC_RESULT (ic->prev))) <= 1)
+        {
+          /* Don't do this for "if (--c)", it inhibits DJNZ generation */
+          if (!ic->prev->prev || ic->prev->prev->op != '-' || !IS_OP_LITERAL(IC_RIGHT(ic->prev->prev)))
+            {
+              sym_link *type = operandType (IC_RESULT (ic->prev));
+              if (ic->prev->op != CAST || IS_BOOL (type) || bitsForType (operandType (IC_RIGHT (ic->prev))) < bitsForType (type))
+                {
+                  if (!isOperandVolatile (ic->prev->op == '!' ? IC_LEFT (ic->prev) : IC_RIGHT (ic->prev), FALSE))
+                    {
+                      if (ic->prev->op == '!') /* Invert jump logic */
+                        {
+                          symbol *tmp = IC_TRUE (ic);
+                          IC_TRUE (ic) = IC_FALSE (ic);
+                          IC_FALSE (ic) = tmp;
+                        }
+                      bitVectUnSetBit (OP_USES (IC_COND (ic)), ic->key);
+                      ReplaceOpWithCheaperOp(&IC_COND (ic), ic->prev->op == '!' ? IC_LEFT (ic->prev) : IC_RIGHT (ic->prev));
+                      (*change)++;
+                    }
 /* There's an optimization opportunity here, but OP_USES doesn't seem to be */
 /* initialized properly at this point. - EEP 2016-08-04 */
 #if 0
-            else if (bitVectnBitsOn (OP_USES(IC_COND (ic))) == 1)
-              {
-                /* We can replace the iTemp with the original volatile symbol */
-                /* but we must make sure the volatile symbol is still accessed */
-                /* only once. */
-                bitVectUnSetBit (OP_USES (IC_COND (ic)), ic->key);
-                ReplaceOpWithCheaperOp(&IC_COND (ic), IC_RIGHT (ic->prev));
-                (*change)++;
-                /* Make previous assignment an assignment to self. */
-                /* killDeadCode() will eliminiate it. */
-                IC_RIGHT (ic->prev) = IC_RESULT (ic->prev);
-                IC_LEFT (ic->prev) = NULL;
-                ic->prev->op = '=';
-              }
+                  else if (bitVectnBitsOn (OP_USES(IC_COND (ic))) == 1)
+                    {
+                      /* We can replace the iTemp with the original volatile symbol */
+                      /* but we must make sure the volatile symbol is still accessed */
+                      /* only once. */
+                      bitVectUnSetBit (OP_USES (IC_COND (ic)), ic->key);
+                      ReplaceOpWithCheaperOp(&IC_COND (ic), IC_RIGHT (ic->prev));
+                      (*change)++;
+                      /* Make previous assignment an assignment to self. */
+                      /* killDeadCode() will eliminiate it. */
+                      IC_RIGHT (ic->prev) = IC_RESULT (ic->prev);
+                      IC_LEFT (ic->prev) = NULL;
+                      ic->prev->op = '=';
+                    }
 #endif
-          }
+                }
+            }
         }
     }
 
@@ -1933,7 +1939,6 @@
     case NE_OP:
     case AND_OP:
     case OR_OP:
-    case GETHBIT:
     case GETABIT:
       break;
     case BITWISEAND:
@@ -2099,7 +2104,6 @@
     case NE_OP:
     case RRC:
     case RLC:
-    case GETHBIT:
     case GETABIT:
     case GETBYTE:
     case GETWORD:
diff -Nru sdcc-4.0.0+dfsg/src/SDCCdwarf2.c sdcc-4.2.0+dfsg/src/SDCCdwarf2.c
--- sdcc-4.0.0+dfsg/src/SDCCdwarf2.c	2019-02-09 04:57:49.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/SDCCdwarf2.c	2022-02-03 09:32:48.000000000 +0000
@@ -331,9 +331,9 @@
 static void
 dwWriteString (const char * string, const char * comment)
 {
-  /* FIXME: need to safely handle nonalphanumeric data in string */
-  
-  tfprintf (dwarf2FilePtr, "\t!ascii\n", string);
+  char * escaped = string_escape (string);
+  tfprintf (dwarf2FilePtr, "\t!ascii\n", escaped);
+  Safe_free (escaped);
   dwWriteByte (NULL, 0, comment);
 }
 
@@ -1335,18 +1335,30 @@
 /* dwWriteAbbrevs - write the abbreviations to the .debug_abbrev section */
 /*-----------------------------------------------------------------------*/
 static void
-dwWriteAbbrevs (void)
+dwWriteAbbrevs (int abbrevNum)
 {
   dwtag * tp;
   dwattr * ap;
   int key;
+  dwtag ** tptable = NULL;
+  int abbrev;
   
   tfprintf (dwarf2FilePtr, "\n\t!area\n", ".debug_abbrev (NOLOAD)");
   tfprintf (dwarf2FilePtr, "!slabeldef\n", "Ldebug_abbrev");
 
+  /* Sort the abbreviations by their abbreviation number so that   */
+  /* we can output them in this order. I don't see any requirement */
+  /* in the standard for this, but some things seem to assume it.  */
+  tptable = Safe_calloc (1+abbrevNum, sizeof(dwtag *));
   tp = hTabFirstItem (dwAbbrevTable, &key);
   for (; tp; tp = hTabNextItem (dwAbbrevTable, &key))
+    tptable[tp->abbrev] = tp;
+
+  for (abbrev=1; abbrev<=abbrevNum; abbrev++)
     {
+      tp = tptable[abbrev];
+      if (!tp) continue;
+
       dwWriteULEB128 (NULL, tp->abbrev, NULL);
       dwWriteULEB128 (NULL, tp->tag, NULL);
       dwWriteByte (NULL, tp->firstChild ? DW_CHILDREN_yes : DW_CHILDREN_no,
@@ -1364,6 +1376,7 @@
     }
   dwWriteULEB128 (NULL, 0, NULL);
   
+  Safe_free (tptable);
   hTabDeleteAll (dwAbbrevTable);
 }
 
@@ -1407,6 +1420,9 @@
 static void
 dwWriteTags (void)
 {  
+  if (!dwRootTag)
+    return;
+
   tfprintf (dwarf2FilePtr, "\n\t!area\n", ".debug_info (NOLOAD)");
   
   dwWriteWordDelta ("Ldebug_info_end", "Ldebug_info_start");
@@ -1418,11 +1434,14 @@
   dwWriteWord ("Ldebug_abbrev", 0, NULL);
     
   dwWriteByte (NULL, port->debugger.dwarf.addressSize, NULL);
-    
-  dwTraverseTag (dwRootTag, dwWriteTag, NULL);
-  
-  dwWriteULEB128 (NULL, 0, NULL);
-  
+
+  // The root tag has no siblings and must not have an end-of-sibling-
+  // chain marker, so handle it separately and start the traversal with
+  // its children.
+  dwWriteTag (dwRootTag, NULL);
+  if (dwRootTag->firstChild)
+    dwTraverseTag (dwRootTag->firstChild, dwWriteTag, NULL);
+
   tfprintf (dwarf2FilePtr, "!slabeldef\n", "Ldebug_info_end");
 
 }
@@ -1702,7 +1721,7 @@
               /* ok, we can use a "special" opcode */
               
               /* If the deltaAddr value was symbolic, it can't be part */
-              /* of the "special" opcode, so encode it seperately      */
+              /* of the "special" opcode, so encode it separately      */
               if (!deltaAddrValid)
                 {
                   dwWriteByte (NULL, DW_LNS_advance_pc, NULL);
@@ -1969,6 +1988,7 @@
   dwcfop * op;
   int i;
   char s[32];
+  int padding;
   
   tfprintf (dwarf2FilePtr, "\n\t!area\n", ".debug_frame (NOLOAD)");
 
@@ -2031,6 +2051,14 @@
       }
 
   dwWriteCFAinstructions (ip);
+
+  //pad with NOPs if needed to maintain 32-bit alignment
+  padding = (4 - ((5 + dwSizeofCFAinstructions (ip)) & 3)) & 3;
+  while (padding)
+    {
+      dwWriteByte (NULL, DW_CFA_nop, NULL);
+      padding--;
+    }
   
   op = ip->first;
   while (op)
@@ -2050,9 +2078,12 @@
 static void
 dwWriteFDE (dwfde * fp, int id)
 {
+  int length = dwSizeofCFAinstructions(fp->ins) + 4
+               + port->debugger.dwarf.addressSize * 2;
+  int padding = (4 - (length & 3)) & 3;
+
   //length
-  dwWriteWord (NULL, dwSizeofCFAinstructions(fp->ins) + 4
-                + port->debugger.dwarf.addressSize * 2 , NULL);
+  dwWriteWord (NULL, length + padding , NULL);
 
   //CIE ptr
   char s[32];
@@ -2067,6 +2098,13 @@
 
   //instructions
   dwWriteCFAinstructions (fp->ins);
+
+  //pad with NOPs if needed to maintain 32-bit alignment
+  while (padding)
+    {
+      dwWriteByte (NULL, DW_CFA_nop, NULL);
+      padding--;
+    }
 }
 
 static void
@@ -2078,9 +2116,11 @@
   dwlocregion * lrp;
 
   int id = 0;
-  cfip = dwCFIRoot;
-  while (cfip)
+  for (cfip = dwCFIRoot; cfip; cfip = cfip->next)
     {
+      if (!cfip->startLabel || !cfip->endLabel)
+        continue;
+        
       fp.startLabel=cfip->startLabel;
       fp.endLabel=cfip->endLabel;
 
@@ -2116,8 +2156,6 @@
         Safe_free(op);
         op = next;
       }
-
-      cfip = cfip->next;
     }
 }
 
@@ -3048,7 +3086,10 @@
 {
   dwline * lp;
   char * debugSym;
-  
+
+  if (ic->inlined)
+    return 0;
+
   lp = Safe_alloc (sizeof (dwline));
 
   lp->line = ic->lineno;
@@ -3230,7 +3271,7 @@
   dwTraverseTag (dwRootTag, dwAssignTagAddress, &tagAddress);
   
   /* Write the .debug_abbrev section */
-  dwWriteAbbrevs ();  
+  dwWriteAbbrevs (abbrevNum);  
   
   /* Write the .debug_info section */
   dwWriteTags ();
diff -Nru sdcc-4.0.0+dfsg/src/SDCCdwarf2.h sdcc-4.2.0+dfsg/src/SDCCdwarf2.h
--- sdcc-4.0.0+dfsg/src/SDCCdwarf2.h	2017-10-17 07:24:51.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/SDCCdwarf2.h	2021-07-09 08:40:23.000000000 +0000
@@ -284,6 +284,7 @@
 #define DW_CFA_advance_loc (1 << 6)
 #define DW_CFA_offset (2 << 6)
 #define DW_CFA_restore (3 << 6)
+#define DW_CFA_nop 0x00
 #define DW_CFA_set_loc 0x01
 #define DW_CFA_advance_loc1 0x02
 #define DW_CFA_advance_loc2 0x03
@@ -298,7 +299,6 @@
 #define DW_CFA_def_cfa 0x0c
 #define DW_CFA_def_cfa_register 0x0d
 #define DW_CFA_def_cfa_offset 0x0e
-#define DW_CFA_nop 0x0f
 #define DW_CFA_lo_user 0x1c
 #define DW_CFA_hi_user 0x3f
 
diff -Nru sdcc-4.0.0+dfsg/src/SDCCerr.c sdcc-4.2.0+dfsg/src/SDCCerr.c
--- sdcc-4.0.0+dfsg/src/SDCCerr.c	2020-01-13 11:56:57.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/SDCCerr.c	2021-06-03 15:45:12.000000000 +0000
@@ -18,8 +18,10 @@
 
 #include 
 #include 
+#include 
 
 #include "SDCCglobl.h"
+#include "dbuf_string.h"
 #ifdef HAVE_BACKTRACE_SYMBOLS_FD
 #include 
 #include 
@@ -571,6 +573,40 @@
     "attribute requires C2X or later", 0},
   { E_COMPOUND_LITERALS_C99, ERROR_LEVEL_ERROR,
     "compound literals require ISO C99 or later and are not implemented", 0},
+  { E_THREAD_LOCAL, ERROR_LEVEL_ERROR,
+    "thread-local storage is not implemented", 0},
+  { E_ENUM_COMMA_C99,  ERROR_LEVEL_ERROR,
+    "trailing comma after enumerator list requires ISO C99 or later", 0},
+  { E_OUTPUT_FILE_OPEN_ERR, ERROR_LEVEL_ERROR,
+     "Failed to open output file '%s' (%s)", 0 },
+  { E_INPUT_FILE_OPEN_ERR, ERROR_LEVEL_ERROR,
+     "Failed to open input file '%s' (%s)", 0 },
+  { W_SHIFT_NEGATIVE, ERROR_LEVEL_WARNING,
+     "%s shift by negative amount", 0 },
+  { W_INVALID_STACK_LOCATION, ERROR_LEVEL_WARNING,
+     "access to invalid stack location", 0 },
+  { W_BINARY_INTEGER_CONSTANT_C23, ERROR_LEVEL_WARNING,
+     "binary integer constant requires C23 or later", 0 },
+  { E_U8CHAR_STRING_C11, ERROR_LEVEL_ERROR,
+     "unicode string literal requires ISO C 11 or later", 0 },
+  { W_PREFIXED_STRINGS, ERROR_LEVEL_WARNING,
+     "sequence of differently prefixed string literals", 0 },
+  { W_DIGIT_SEPARATOR_C23, ERROR_LEVEL_WARNING,
+     "digit separators require ISO C23 or later", 0 },
+  { E_INVALID_LANG_OVERRIDE, ERROR_LEVEL_ERROR,
+     "argument to option -x is not a valid file type override", 0},
+  { E_RAISONANCE_LARGE_RETURN, ERROR_LEVEL_ERROR,
+     "return values larger than 16 bits are not supported for Raisonance calling convention", 0},
+  { E_IAR_LARGE_RETURN, ERROR_LEVEL_ERROR,
+     "return values larger than 16 bits are not supported for IAR calling convention", 0},
+  { E_IAR_PSEUDOPARM, ERROR_LEVEL_ERROR,
+     "IAR function call with parameter in pseudoregister", 0},
+  { E_COSMIC_LARGE_RETURN, ERROR_LEVEL_ERROR,
+     "return values larger than 16 bits are not supported for Cosmic calling convention", 0},
+  { E_MULTIPLE_CALLINGCONVENTIONS, ERROR_LEVEL_ERROR,
+     "multiple incompatible calling conventions for '%s'", 0},
+  { W_SFR_ADDRESS, ERROR_LEVEL_WARNING,
+     "unsupported address of __sfr taken", 0},
 };
 
 /* -------------------------------------------------------------------------------
@@ -602,6 +638,10 @@
 int
 vwerror (int errNum, va_list marker)
 {
+  struct dbuf_s dbuf;
+  char *errmsg;
+  char *oldmsg;
+
   if (_SDCCERRG.out == NULL)
     {
       _SDCCERRG.out = DEFAULT_ERROR_OUT;
@@ -620,6 +660,8 @@
       return 0;
     }
 
+  dbuf_init(&dbuf, 200);
+  
   if ((ErrTab[errNum].errType >= _SDCCERRG.logLevel) && (!ErrTab[errNum].disabled))
     {
       if (ErrTab[errNum].errType >= ERROR_LEVEL_ERROR || _SDCCERRG.werror)
@@ -628,47 +670,55 @@
       if (filename && lineno)
         {
           if (_SDCCERRG.style)
-            fprintf (_SDCCERRG.out, "%s(%d) : ", filename, lineno);
+            dbuf_printf (&dbuf, "%s(%d) : ", filename, lineno);
           else
-            fprintf (_SDCCERRG.out, "%s:%d: ", filename, lineno);
+            dbuf_printf (&dbuf, "%s:%d: ", filename, lineno);
         }
       else if (lineno)
         {
-          fprintf (_SDCCERRG.out, "at %d: ", lineno);
+          dbuf_printf (&dbuf, "at %d: ", lineno);
         }
       else
         {
-          fprintf (_SDCCERRG.out, "-:0: ");
+          dbuf_printf (&dbuf, "-:0: ");
         }
 
       switch (ErrTab[errNum].errType)
         {
         case ERROR_LEVEL_SYNTAX_ERROR:
-          fprintf (_SDCCERRG.out, "syntax error: ");
+          dbuf_printf (&dbuf, "syntax error: ");
           break;
 
         case ERROR_LEVEL_ERROR:
-          fprintf (_SDCCERRG.out, "error %d: ", errNum);
+          dbuf_printf (&dbuf, "error %d: ", errNum);
           break;
 
         case ERROR_LEVEL_WARNING:
         case ERROR_LEVEL_PEDANTIC:
           if (_SDCCERRG.werror)
-            fprintf (_SDCCERRG.out, "error %d: ", errNum);
+            dbuf_printf (&dbuf, "error %d: ", errNum);
           else
-            fprintf (_SDCCERRG.out, "warning %d: ", errNum);
+            dbuf_printf (&dbuf, "warning %d: ", errNum);
           break;
 
         case ERROR_LEVEL_INFO:
-          fprintf (_SDCCERRG.out, "info %d: ", errNum);
+          dbuf_printf (&dbuf, "info %d: ", errNum);
           break;
 
         default:
           break;
         }
 
-      vfprintf (_SDCCERRG.out, ErrTab[errNum].errText, marker);
-      fprintf (_SDCCERRG.out, "\n");
+      dbuf_vprintf (&dbuf, ErrTab[errNum].errText, marker);
+      errmsg = dbuf_detach_c_str (&dbuf);
+      for (oldmsg = setFirstItem (_SDCCERRG.log); oldmsg; oldmsg = setNextItem (_SDCCERRG.log))
+        if (strcmp (errmsg, oldmsg) == 0)
+          {
+            free(errmsg);
+            return 0;
+          }
+      addSetHead (&_SDCCERRG.log, errmsg);
+      fprintf (_SDCCERRG.out, "%s\n", errmsg);
       return 1;
     }
   else
diff -Nru sdcc-4.0.0+dfsg/src/SDCCerr.h sdcc-4.2.0+dfsg/src/SDCCerr.h
--- sdcc-4.0.0+dfsg/src/SDCCerr.h	2020-01-13 11:56:57.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/SDCCerr.h	2021-06-03 15:45:12.000000000 +0000
@@ -22,6 +22,7 @@
 
 #include 
 #include 
+#include "SDCCset.h"
 
 /* ERROR Message Definition */
 
@@ -281,6 +282,23 @@
   E_U8_CHAR_INVALID             = 252, /* invalid u8 character constant */
   E_ATTRIBUTE_C2X               = 253, /* attribute requires ISO C2X or later */
   E_COMPOUND_LITERALS_C99       = 254, /* compound literals require ISO C99 or later */
+  E_THREAD_LOCAL                = 255, /* thread-local storage is not implemented */
+  E_ENUM_COMMA_C99              = 256, /* trailing comma after enumerator list requires ISO C99 or later */
+  E_OUTPUT_FILE_OPEN_ERR        = 257, /* Failed to open output file for writing (with error message) */
+  E_INPUT_FILE_OPEN_ERR         = 258, /* Failed to open input file for readin (with error message) */
+  W_SHIFT_NEGATIVE              = 259, /* shift by negative amount */
+  W_INVALID_STACK_LOCATION      = 260, /* access to invalid stack location */
+  W_BINARY_INTEGER_CONSTANT_C23 = 261, /* binary integer constant requires ISO C23 or later */
+  E_U8CHAR_STRING_C11           = 262, /* unicode string literal requires ISO C 11 or later */
+  W_PREFIXED_STRINGS            = 263, /* sequence of differently prefixed string literals */
+  W_DIGIT_SEPARATOR_C23         = 264, /* digit separators require ISO C23 or later */
+  E_INVALID_LANG_OVERRIDE       = 265, /* argument to option -x is not a valid file type override */
+  E_RAISONANCE_LARGE_RETURN     = 266, /* large return value not supported for Raisonance calling convention */
+  E_IAR_LARGE_RETURN            = 267, /* large return value not supported for IAR calling convention */
+  E_IAR_PSEUDOPARM              = 268, /* IAR function call with parameter in pseudoregister */
+  E_COSMIC_LARGE_RETURN         = 269, /* large return value not supported for Cosmic calling convention */
+  E_MULTIPLE_CALLINGCONVENTIONS = 270, /* multiple incompatible calling conventions */
+  W_SFR_ADDRESS                 = 271, /* unsupported address of __sfr taken */
 
   /* don't touch this! */
   NUMBER_OF_ERROR_MESSAGES             /* Number of error messages */
@@ -329,6 +347,7 @@
   FILE *out;
   int style;                        /* 1=MSVC */
   int werror;                       /* treat the warnings as errors */
+  set *log;
 };
 
 extern struct SDCCERRG _SDCCERRG;
diff -Nru sdcc-4.0.0+dfsg/src/SDCCgen.c sdcc-4.2.0+dfsg/src/SDCCgen.c
--- sdcc-4.0.0+dfsg/src/SDCCgen.c	2019-06-16 13:34:14.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/SDCCgen.c	2020-09-25 17:30:08.000000000 +0000
@@ -181,7 +181,7 @@
 }
 
 void
-emitLabel (symbol *tlbl)
+emitLabel (const symbol *tlbl)
 {
   if (!tlbl)
     return;
diff -Nru sdcc-4.0.0+dfsg/src/SDCCgen.h sdcc-4.2.0+dfsg/src/SDCCgen.h
--- sdcc-4.0.0+dfsg/src/SDCCgen.h	2019-06-16 13:34:14.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/SDCCgen.h	2020-09-25 17:30:08.000000000 +0000
@@ -93,7 +93,7 @@
 void emit_raw (const char *line);
 void va_emitcode (const char *inst, const char *fmt, va_list ap);
 void emitcode (const char *inst, const char *fmt, ...);
-void emitLabel (symbol * tlbl);
+void emitLabel (const symbol * tlbl);
 void genInline (iCode * ic);
 void printLine (lineNode *, struct dbuf_s *);
 iCode *ifxForOp (const operand *op, const iCode *ic);
diff -Nru sdcc-4.0.0+dfsg/src/SDCCglobl.h sdcc-4.2.0+dfsg/src/SDCCglobl.h
--- sdcc-4.0.0+dfsg/src/SDCCglobl.h	2018-06-17 07:38:22.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/SDCCglobl.h	2021-12-10 14:48:15.000000000 +0000
@@ -25,6 +25,7 @@
 #include 
 #include 
 #include 
+#include 
 
 # ifndef __cplusplus
 #  include 
@@ -275,7 +276,6 @@
     int noRegParams;            /* Disable passing some parameters in registers */
     int verbose;                /* Show what the compiler is doing */
     int lessPedantic;           /* disable some warnings */
-    int profile;                /* Turn on extra profiling information */
     int omitFramePtr;           /* Turn off the frame pointer. */
     int useAccelerator;         /* use ds390 Arithmetic Accelerator */
     int noiv;                   /* do not generate irq vector table entries */
@@ -285,7 +285,6 @@
     int protect_sp_update;      /* DS390 - will disable interrupts during ESP:SP updates */
     int parms_in_bank1;         /* DS390 - use reg bank1 to pass parameters */
     int stack_size;             /* MCS51/DS390 - Tells the linker to allocate this space for stack */
-    int no_pack_iram;           /* MCS51/DS390 - Deprecated: Tells the linker not to pack variables in internal ram */
     int acall_ajmp;             /* MCS51 - Use acall/ajmp instead of lcall/ljmp */
     int no_ret_without_call;    /* MCS51 - Do not use ret independent of acall/lcall */
     int use_non_free;           /* Search / include non-free licensed libraries and header files */
@@ -309,7 +308,7 @@
     int printSearchDirs;        /* display the directories in the compiler's search path */
     int vc_err_style;           /* errors and warnings are compatible with Micro$oft visual studio */
     int use_stdout;             /* send errors to stdout instead of stderr */
-    int no_std_crt0;            /* for the z80/gbz80 do not link default crt0.o*/
+    int no_std_crt0;            /* for the z80/sm83 do not link default crt0.o*/
     int std_c95;                /* enable C95 keywords/constructs */
     int std_c99;                /* enable C99 keywords/constructs */
     int std_c11;                /* enable C11 keywords/constructs */
@@ -328,6 +327,7 @@
     int max_allocs_per_node;    /* Maximum number of allocations / combinations considered at each node in the tree-decomposition based algorithms */
     bool noOptsdccInAsm;        /* Do not emit .optsdcc in asm */
     bool oldralloc;             /* Use old register allocator */
+    int sdcccall;               /* ABI version */
   };
 
 /* forward definition for variables accessed globally */
diff -Nru sdcc-4.0.0+dfsg/src/SDCCglue.c sdcc-4.2.0+dfsg/src/SDCCglue.c
--- sdcc-4.0.0+dfsg/src/SDCCglue.c	2020-01-14 11:38:33.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/SDCCglue.c	2022-02-14 05:30:03.000000000 +0000
@@ -150,12 +150,18 @@
     {
       /* PENDING: special case here - should remove */
       if (!strcmp (map->sname, CODE_NAME))
-        dbuf_tprintf (&map->oBuf, "\t!areacode\n", map->sname);
+        {
+          if (options.code_seg && strcmp (CODE_NAME, options.code_seg))
+            dbuf_tprintf (&map->oBuf, "\t!areacode\n", options.code_seg);
+          else
+            dbuf_tprintf (&map->oBuf, "\t!areacode\n", map->sname);
+        }
       else if (!strcmp (map->sname, DATA_NAME))
         {
-          dbuf_tprintf (&map->oBuf, "\t!areadata\n", map->sname);
           if (options.data_seg && strcmp (DATA_NAME, options.data_seg))
-            dbuf_tprintf (&map->oBuf, "\t!area\n", options.data_seg);
+            dbuf_tprintf (&map->oBuf, "\t!areadata\n", options.data_seg);
+          else
+            dbuf_tprintf (&map->oBuf, "\t!areadata\n", map->sname);
         }
       else if (!strcmp (map->sname, HOME_NAME))
         dbuf_tprintf (&map->oBuf, "\t!areahome\n", map->sname);
@@ -229,7 +235,7 @@
                       werrorfl (tsym->fileDef, tsym->lineDef, W_EXCESS_INITIALIZERS, "scalar", tsym->name);
                     }
                   ival = newNode ('=', newAst_VALUE (symbolVal (tsym)),
-                                  decorateType (resolveSymbols (list2expr (tsym->ival)), RESULT_TYPE_NONE));
+                                  decorateType (resolveSymbols (list2expr (tsym->ival)), RESULT_TYPE_NONE, true));
                 }
               if (ival)
                 {
@@ -311,7 +317,7 @@
                       werrorfl (sym->fileDef, sym->lineDef, W_EXCESS_INITIALIZERS, "scalar", sym->name);
                     }
                   ival = newNode ('=', newAst_VALUE (symbolVal (sym)),
-                                  decorateType (resolveSymbols (list2expr (sym->ival)), RESULT_TYPE_NONE));
+                                  decorateType (resolveSymbols (list2expr (sym->ival)), RESULT_TYPE_NONE, true));
                 }
               codeOutBuf = &statsg->oBuf;
 
@@ -518,7 +524,7 @@
       while (t->left != NULL && t->opval.op != '[')
         t = t->left;
 
-      return valForStructElem (t, expr->right); 
+      return valForStructElem (t, expr->right);
     }
 
   /* case 7. function name */
@@ -860,7 +866,7 @@
     {
       if (!!(val = initPointer (ilist, type, 0)))
         {
-          int i, size = getSize (type), le = port->little_endian, top = (options.model == MODEL_FLAT24) ? 3 : 2;;         
+          int i, size = getSize (type), le = port->little_endian, top = (options.model == MODEL_FLAT24) ? 3 : 2;;
           dbuf_printf (oBuf, "\t.byte ");
           for (i = (le ? 0 : size - 1); le ? (i < size) : (i > -1); i += (le ? 1 : -1))
             {
@@ -873,7 +879,7 @@
 			    if (val->name && strlen (val->name) > 0)
                   dbuf_printf (oBuf, "(%s >> %d)", val->name, i * 8);
 				else
-                  dbuf_printf (oBuf, "#0x00");				
+                  dbuf_printf (oBuf, "#0x00");
               else
                 dbuf_printf (oBuf, "#0x00");
               if (i == (le ? (size - 1) : 0))
@@ -1797,7 +1803,7 @@
       else
         {
           ast *ast = newAst_VALUE (constVal("0"));
-          ast = decorateType (ast, RESULT_TYPE_NONE);
+          ast = decorateType (ast, RESULT_TYPE_NONE, true);
           ilist = newiList(INIT_NODE, ast);
         }
     }
@@ -2148,7 +2154,15 @@
   fprintf (afile, "%s", iComments2);
 
   for (sym = setFirstItem (publics); sym; sym = setNextItem (publics))
-    tfprintf (afile, "\t!global\n", sym->rname);
+    {
+      if (TARGET_Z80_LIKE && IFFUNC_BANKED(sym->type))
+        {
+          /* TODO: use template for bank symbol generation */
+          sprintf (buffer, "b%s", sym->rname);
+          tfprintf (afile, "\t!global\n", buffer);
+        }
+      tfprintf (afile, "\t!global\n", sym->rname);
+    }
 }
 
 /*-----------------------------------------------------------------*/
@@ -2299,7 +2313,7 @@
 
   if (!(asmFile = fopen (dbuf_c_str (&asmFileName), "w")))
     {
-      werror (E_FILE_OPEN_ERR, dbuf_c_str (&asmFileName));
+      werror (E_OUTPUT_FILE_OPEN_ERR, dbuf_c_str (&asmFileName), strerror (errno));
       dbuf_destroy (&asmFileName);
       exit (EXIT_FAILURE);
     }
@@ -2316,6 +2330,8 @@
     fprintf (asmFile, "\t.r3k\n");
   else if (TARGET_IS_EZ80_Z80)
     fprintf (asmFile, "\t.ez80\n");
+  else if (TARGET_IS_Z80N)
+    fprintf (asmFile, "\t.zxn\n");
 
   /* print module name */
   tfprintf (asmFile, "\t!module\n", moduleName);
@@ -2378,7 +2394,7 @@
   if (port->assembler.externGlobal)
     printExterns (asmFile);
 
-  if ((mcs51_like) || (TARGET_IS_Z80 || TARGET_IS_GBZ80 || TARGET_IS_Z180 || TARGET_IS_RABBIT || TARGET_IS_EZ80_Z80) || TARGET_PDK_LIKE)  /*.p.t.20030924 need to output SFR table for Z80 as well */
+  if ((mcs51_like) || (TARGET_Z80_LIKE && !TARGET_IS_TLCS90) || TARGET_PDK_LIKE)  /*.p.t.20030924 need to output SFR table for Z80 as well */
     {
       /* copy the sfr segment */
       fprintf (asmFile, "%s", iComments2);
@@ -2456,7 +2472,7 @@
   if (overlay)
     {
       fprintf (asmFile, "%s", iComments2);
-      fprintf (asmFile, "; overlayable items in%s ram \n", mcs51_like ? " internal" : "");
+      fprintf (asmFile, "; overlayable items in%s ram\n", mcs51_like ? " internal" : "");
       fprintf (asmFile, "%s", iComments2);
       dbuf_write_and_destroy (&ovrBuf, asmFile);
     }
@@ -2465,7 +2481,7 @@
   if (mainf && IFFUNC_HASBODY (mainf->type))
     {
       fprintf (asmFile, "%s", iComments2);
-      fprintf (asmFile, "; Stack segment in internal ram \n");
+      fprintf (asmFile, "; Stack segment in internal ram\n");
       fprintf (asmFile, "%s", iComments2);
       fprintf (asmFile, "\t.area\tSSEG\n" "__start__stack:\n\t.ds\t1\n\n");
     }
@@ -2513,7 +2529,7 @@
   if (mainf && IFFUNC_HASBODY (mainf->type) && options.useXstack)
     {
       fprintf (asmFile, "%s", iComments2);
-      fprintf (asmFile, "; external stack \n");
+      fprintf (asmFile, "; external stack\n");
       fprintf (asmFile, "%s", iComments2);
       fprintf (asmFile, "\t.area XSTK (PAG,XDATA)\n" "__start__xstack:\n\t.ds\t1\n\n");
     }
@@ -2555,7 +2571,7 @@
   if (mainf && IFFUNC_HASBODY (mainf->type))
     {
       fprintf (asmFile, "%s", iComments2);
-      fprintf (asmFile, "; interrupt vector \n");
+      fprintf (asmFile, "; interrupt vector\n");
       fprintf (asmFile, "%s", iComments2);
       dbuf_write_and_destroy (&vBuf, asmFile);
     }
@@ -2613,7 +2629,7 @@
   if (mainf && IFFUNC_HASBODY (mainf->type))
     {
       /* STM8 note: there is no need to call main().
-         Instead of that, it's address is specified in the 
+         Instead of that, it's address is specified in the
          interrupts table and always equals to 0x8080.
        */
 
diff -Nru sdcc-4.0.0+dfsg/src/SDCCicode.c sdcc-4.2.0+dfsg/src/SDCCicode.c
--- sdcc-4.0.0+dfsg/src/SDCCicode.c	2019-12-09 14:41:31.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/SDCCicode.c	2022-02-03 09:32:48.000000000 +0000
@@ -41,6 +41,7 @@
 long scopeLevel;
 int seqPoint;
 int inCriticalPair = 0;
+int inlinedActive = 0;
 
 symbol *returnLabel;            /* function return label */
 symbol *entryLabel;             /* function entry  label */
@@ -79,7 +80,6 @@
   {'~', "~", picGenericOne, NULL},
   {RRC, "rrc", picGenericOne, NULL},
   {RLC, "rlc", picGenericOne, NULL},
-  {GETHBIT, "ghbit", picGenericOne, NULL},
   {GETABIT, "gabit", picGenericOne, NULL},
   {GETBYTE, "gbyte", picGenericOne, NULL},
   {GETWORD, "gword", picGenericOne, NULL},
@@ -554,7 +554,7 @@
 }
 
 /*-----------------------------------------------------------------*/
-/* newiCode - create and return a new iCode entry initialised      */
+/* newiCode - create and return a new iCode entry initialized      */
 /*-----------------------------------------------------------------*/
 iCode *
 newiCode (int op, operand *left, operand *right)
@@ -572,9 +572,11 @@
   ic->key = iCodeKey++;
   IC_LEFT (ic) = left;
   IC_RIGHT (ic) = right;
+  ic->inlined = inlinedActive;
 
-  // Err on the save side for now, settign this to false later is up to later analysis.
+  // Err on the save side for now, setting this to false later is up to later analysis.
   ic->localEscapeAlive = true;
+  ic->parmEscapeAlive = true;
 
   return ic;
 }
@@ -695,7 +697,7 @@
 
 
 /*-----------------------------------------------------------------*/
-/* initiCode - initialises some iCode related stuff                */
+/* initiCode - initializes some iCode related stuff                */
 /*-----------------------------------------------------------------*/
 void
 initiCode ()
@@ -1085,6 +1087,76 @@
   return FALSE;
 }
 
+
+/*-------------------------------------------------------------------*/
+/* detachiCodeOperand - remove a specific operand position (left,    */
+/*                      right, result, etc) from an iCode and update */
+/*                      the uses & defs as appropriate.              */
+/*-------------------------------------------------------------------*/
+operand *
+detachiCodeOperand (operand **opp, iCode *ic)
+{
+  operand * op = *opp;
+  
+  if (IS_SYMOP (op))
+    {
+      if ((ic->op == IFX) || (ic->op == JUMPTABLE))
+        {
+          *opp = NULL;
+          bitVectUnSetBit (OP_USES (op), ic->key);
+        }
+      else
+        {
+          int uses = 0;
+          bool ispointerset = POINTER_SET (ic);
+
+          if (!ispointerset && (opp == &IC_RESULT (ic)))
+            bitVectUnSetBit (OP_DEFS (op), ic->key);
+          *opp = NULL;
+          if (ispointerset && (op == IC_RESULT (ic)))
+            uses++;
+          if (op == IC_LEFT (ic))
+            uses++;
+          if (op == IC_RIGHT (ic))
+            uses++;
+          if (uses == 0)
+            bitVectUnSetBit (OP_USES (op), ic->key);
+        }
+    }
+  else
+    *opp = NULL;
+  return op;
+}
+
+/*-------------------------------------------------------------------*/
+/* attachiCodeOperand - insert an operand to a specific operand      */
+/*                      position (left, right, result, etc) in an    */
+/*                      iCode and update the uses & defs as          */
+/*                      appropriate. Any previously existing operand */
+/*                      in that position will be detached first.     */
+/*-------------------------------------------------------------------*/
+void
+attachiCodeOperand (operand *newop, operand **opp, iCode *ic)
+{
+  /* If there is already an operand here, detach it first */
+  if (*opp)
+    detachiCodeOperand (opp, ic);
+
+  /* Insert new operand */
+  *opp = newop;
+  
+  /* Update defs/uses for new operand */
+  if (IS_SYMOP (newop))
+    {
+      if (opp == &IC_RESULT (ic) && !POINTER_SET (ic))
+        OP_DEFS (newop) = bitVectSetBit (OP_DEFS (newop), ic->key);
+      else
+        OP_USES (newop) = bitVectSetBit (OP_USES (newop), ic->key);
+    }
+}
+
+
+
 /*-----------------------------------------------------------------*/
 /* isOclsExpensive - will return true if accesses to an output     */
 /*                   storage class are expensive                   */
@@ -1340,7 +1412,7 @@
     case RIGHT_OP:
       /* The number of right shifts is always unsigned. Signed doesn't make
          sense here. Shifting by a negative number is impossible. */
-      retval = operandFromValue (valRecastLitVal (type, valShift (OP_VALUE (left), OP_VALUE (right), 0)));
+      retval = operandFromValue (valRecastLitVal (type, valShift (OP_VALUE (left), OP_VALUE (right), 0, true)));
       break;
     case EQ_OP:
       if (IS_FLOAT (let) || IS_FLOAT (ret))
@@ -1363,9 +1435,9 @@
           l = (TYPE_TARGET_ULONG) double2ul (operandLitValue (left));
           r = (TYPE_TARGET_ULONG) double2ul (operandLitValue (right));
           /* In order to correctly compare 'signed int' and 'unsigned int' it's
-             neccessary to strip them to 16 bit.
+             necessary to strip them to 16 bit.
              Literals are reduced to their cheapest type, therefore left and
-             right might have different types. It's neccessary to find a
+             right might have different types. It's necessary to find a
              common type: int (used for char too) or long */
           if (!IS_LONG (let) && !IS_LONG (ret))
             {
@@ -1431,6 +1503,13 @@
         retval = operandFromLit ((i << (getSize (operandType (left)) * 8 - 1)) | (i >> 1));
       }
       break;
+    case SWAP:
+      {
+        TYPE_TARGET_ULONG i = (TYPE_TARGET_ULONG) double2ul (operandLitValue (left));
+        unsigned sz = getSize (operandType (left)) * 4;
+        retval = operandFromLit ((i >> sz) | (i << sz));
+      }
+      break;
     case GETABIT:
       retval = operandFromLit (((TYPE_TARGET_ULONG) double2ul (operandLitValue (left)) >>
                                 (TYPE_TARGET_ULONG) double2ul (operandLitValue (right))) & 1);
@@ -1444,10 +1523,6 @@
                                 (TYPE_TARGET_ULONG) double2ul (operandLitValue (right)) & 0xFFFF));
       break;
 
-    case GETHBIT:
-      retval = operandFromLit (((TYPE_TARGET_ULONG) double2ul (operandLitValue (left)) >> ((getSize (let) * 8) - 1)) & 1);
-      break;
-
     case UNARYMINUS:
       retval = operandFromValue (valCastLiteral (type, -1 * operandLitValue (left), (-1ll) * operandLitValueUll (left)));
       break;
@@ -1661,7 +1736,7 @@
   /* under the following conditions create a
      register equivalent for a local symbol */
   if (sym->level && sym->etype && SPEC_OCLS (sym->etype) &&
-      (IN_FARSPACE (SPEC_OCLS (sym->etype)) && !TARGET_HC08_LIKE && (!(options.model == MODEL_FLAT24))) && options.stackAuto == 0)
+      (IN_FARSPACE (SPEC_OCLS (sym->etype)) && !TARGET_HC08_LIKE && !TARGET_MOS6502_LIKE && (!(options.model == MODEL_FLAT24))) && options.stackAuto == 0)
     {
       ok = 0;
     }
@@ -1672,9 +1747,9 @@
       IS_AUTO (sym) &&                  /* is a local auto variable */
       !sym->addrtaken &&                /* whose address has not been taken */
       !sym->reqv &&                     /* does not already have a reg equivalence */
-      !IS_VOLATILE (sym->etype) &&      /* not declared as volatile */
+      !IS_VOLATILE (sym->type) &&       /* not declared as volatile */
       !sym->islbl &&                    /* not a label */
-      !(TARGET_HC08_LIKE && (getSize (sym->type) > 2)) && /* will fit in regs */
+      !((TARGET_HC08_LIKE || TARGET_MOS6502_LIKE) && (getSize (sym->type) > 2)) && /* will fit in regs */
       ok                                /* farspace check */
     )
     {
@@ -1959,7 +2034,7 @@
     return op;
 
   /* if this is not a temp symbol then */
-  if (!IS_ITEMP (op) && !force && !(IN_FARSPACE (SPEC_OCLS (etype)) && !TARGET_HC08_LIKE))
+  if (!IS_ITEMP (op) && !force && !(IN_FARSPACE (SPEC_OCLS (etype)) && !TARGET_HC08_LIKE && !TARGET_MOS6502_LIKE))
     {
       op = operandFromOperand (op);
       op->isaddr = 0;
@@ -1967,7 +2042,7 @@
     }
 
   if (IS_SPEC (type) &&
-      IS_TRUE_SYMOP (op) && (!(IN_FARSPACE (SPEC_OCLS (etype)) && !TARGET_HC08_LIKE) || (options.model == MODEL_FLAT24)))
+      IS_TRUE_SYMOP (op) && (!(IN_FARSPACE (SPEC_OCLS (etype)) && !TARGET_HC08_LIKE && !TARGET_MOS6502_LIKE) || (options.model == MODEL_FLAT24)))
     {
       op = operandFromOperand (op);
       op->isaddr = 0;
@@ -1991,7 +2066,7 @@
 }
 
 /*-----------------------------------------------------------------*/
-/* checkPtrQualifiers - check for lost pointer qualifers           */
+/* checkPtrQualifiers - check for lost pointer qualifiers          */
 /*-----------------------------------------------------------------*/
 static void
 checkPtrQualifiers (sym_link * ltype, sym_link * rtype, int warn_const)
@@ -2099,7 +2174,7 @@
 
   /* if they are both literal then we know the result */
   if (IS_LITERAL (letype) && IS_LITERAL (retype))
-    return operandFromValue (valMult (OP_VALUE (left), OP_VALUE (right)));
+    return operandFromValue (valMult (OP_VALUE (left), OP_VALUE (right), true));
 
   if (IS_LITERAL (retype))
     {
@@ -2118,7 +2193,7 @@
      efficient in most cases than 2 bytes result = 2 bytes << literal
      if port has 1 byte muldiv */
   if ((p2 > 0) && !IS_FLOAT (letype) && !IS_FIXED (letype) &&
-      !((resultType == RESULT_TYPE_INT) && (getSize (resType) != getSize (ltype)) && !(TARGET_Z80_LIKE || TARGET_IS_STM8 && p2 == 1) /* Mimic old behaviour that tested port->muldiv, which was zero for stm8 and z80-like only. Someone should look into what really makes sense here. */) &&
+      !((resultType == RESULT_TYPE_INT) && (getSize (resType) != getSize (ltype)) && !(TARGET_Z80_LIKE || TARGET_MOS6502_LIKE || TARGET_IS_STM8 && p2 == 1) /* Mimic old behaviour that tested port->muldiv, which was zero for stm8 and z80-like only. Someone should look into what really makes sense here. */) &&
       !TARGET_PIC_LIKE)      /* don't shift for pic */
     {
       if ((resultType == RESULT_TYPE_INT) && (getSize (resType) != getSize (ltype)))
@@ -2190,7 +2265,7 @@
       !IS_FLOAT (letype) &&
       !IS_FIXED (letype) && !IS_UNSIGNED (letype) &&
       ((p2 = powof2 ((TYPE_TARGET_ULONG) ulFromVal (OP_VALUE (right)))) > 0) &&
-      (TARGET_Z80_LIKE || TARGET_HC08_LIKE))
+      (TARGET_Z80_LIKE || TARGET_HC08_LIKE || TARGET_MOS6502_LIKE))
     {
       operand *tmp;
       symbol *label = newiTempLabel (NULL);
@@ -2231,7 +2306,7 @@
 
   /* if they are both literal then we know the result */
   if (IS_LITERAL (letype) && IS_LITERAL (retype))
-    return operandFromValue (valMod (OP_VALUE (left), OP_VALUE (right)));
+    return operandFromValue (valMod (OP_VALUE (left), OP_VALUE (right), true));
 
   resType = usualBinaryConversions (&left, &right, resultType, '%');
 
@@ -2260,7 +2335,7 @@
   /* if they are both literals then */
   if (IS_LITERAL (letype) && IS_LITERAL (retype))
     {
-      result = operandFromValue (valMinus (OP_VALUE (left), OP_VALUE (right)));
+      result = operandFromValue (valMinus (OP_VALUE (left), OP_VALUE (right), true));
       goto subtractExit;
     }
 
@@ -2295,7 +2370,7 @@
 
   /* if they are both literal then we know the result */
   if (IS_LITERAL (letype) && IS_LITERAL (retype) && left->isLiteral && right->isLiteral)
-    return operandFromValue (valMinus (OP_VALUE (left), OP_VALUE (right)));
+    return operandFromValue (valMinus (OP_VALUE (left), OP_VALUE (right), true));
 
   /* if left is an array or pointer */
   if (IS_PTR (ltype) || IS_ARRAY (ltype))
@@ -2407,8 +2482,8 @@
     {
       value *scaledRight = valFromType (rtype);
       if (IS_PTR (ltype))
-        scaledRight = valMult (scaledRight, valueFromLit (getSize (ltype->next)));
-      return operandFromValue (valPlus (valFromType (ltype), scaledRight));
+        scaledRight = valMult (scaledRight, valueFromLit (getSize (ltype->next)), true);
+      return operandFromValue (valPlus (valFromType (ltype), scaledRight, true));
     }
 
   ic = newiCode ('+', left, right);
@@ -2795,8 +2870,12 @@
 {
   iCode *ic;
 
-  left = geniCodeCast (resType, left, TRUE);
-  right = geniCodeCast (resType, right, TRUE);
+  /* Signedness doesn't matter for bit ops, so omit */
+  /* possible cast if that is the only difference */
+  if (compareType (resType, operandType (left)) != -2)
+    left = geniCodeCast (resType, left, TRUE);
+  if (compareType (resType, operandType (right)) != -2)
+    right = geniCodeCast (resType, right, TRUE);
 
   ic = newiCode (oper, left, right);
   IC_RESULT (ic) = newiTempOperand (resType, 0);
@@ -3257,7 +3336,7 @@
      done with the type & not the pointer */
   /* then cast rights type to left */
 
-  /* first check the type for pointer assignement */
+  /* first check the type for pointer assignment */
   if (left->isaddr && IS_PTR (ltype) && IS_ITEMP (left) && compareType (ltype, rtype) <= 0)
     {
       if (left->aggr2ptr)
@@ -3365,7 +3444,7 @@
 /* geniCodeSEParms - generate code for side effecting fcalls       */
 /*-----------------------------------------------------------------*/
 static void
-geniCodeSEParms (ast * parms, int lvl)
+geniCodeSEParms (ast *parms, int lvl)
 {
   if (!parms)
     return;
@@ -3460,7 +3539,7 @@
           ic = newiCode (IPUSH, pval, NULL);
           ic->parmPush = 1;
           /* update the stack adjustment */
-          *stack += getSize (IS_AGGREGATE (p) ? aggrToPtr (p, FALSE) : p);
+          *stack += getSize (IS_ARRAY (p) ? aggrToPtr (p, FALSE) : p);
           if ((IFFUNC_ISSMALLC (ftype) || TARGET_PDK_LIKE) && !IS_AGGREGATE (p) && getSize (p) == 1) /* SmallC calling convention passes 8-bit parameters as 16-bit values. So does pdk due to stack alignment requirements */
             (*stack)++;
           ADDTOCHAIN (ic);
@@ -3599,7 +3678,7 @@
           if (!sym->addrtaken && !IS_VOLATILE (sym->etype))
             {
 
-              if ((IN_FARSPACE (SPEC_OCLS (sym->etype)) && !TARGET_HC08_LIKE) &&
+              if ((IN_FARSPACE (SPEC_OCLS (sym->etype)) && !TARGET_HC08_LIKE && !TARGET_MOS6502_LIKE) &&
                   options.stackAuto == 0 && (!(options.model == MODEL_FLAT24)))
                 {
                 }
@@ -3815,6 +3894,8 @@
   max = (int) ulFromVal (vch);
   maxVal = vch;
 
+  if (max-min < 0)
+    return 0;
   /* Exit if the range is too large to handle with a jump table. */
   if (1 + max - min > port->jumptableCost.maxCount)
     return 0;
@@ -4103,7 +4184,7 @@
   operand *op = NULL;
   sym_link *type;
 
-  if (!options.stackAuto && !TARGET_HC08_LIKE)
+  if (!options.stackAuto && !TARGET_HC08_LIKE && !TARGET_MOS6502_LIKE)
     {
       type = newLink (SPECIFIER);
       SPEC_VOLATILE (type) = 1;
@@ -4238,6 +4319,9 @@
   /* if we find a nullop */
   if (tree->type == EX_OP && (tree->opval.op == NULLOP || tree->opval.op == BLOCK))
     {
+      int oldInlinedActive = inlinedActive;
+      if (tree->inlined)
+        inlinedActive = 1;
       if (tree->left && tree->left->type == EX_VALUE)
         geniCodeDummyRead (ast2iCode (tree->left, lvl + 1));
       else
@@ -4246,6 +4330,7 @@
         geniCodeDummyRead (ast2iCode (tree->right, lvl + 1));
       else
         ast2iCode (tree->right, lvl + 1);
+      inlinedActive = oldInlinedActive;
       return NULL;
     }
 
@@ -4409,7 +4494,6 @@
       return geniCodeUnary (geniCodeRValue (left, FALSE), tree->opval.op, tree->ftype);
 
     case '!':
-    case GETHBIT:
       {
         operand *op = geniCodeUnary (geniCodeRValue (left, FALSE), tree->opval.op, tree->ftype);
         return op;
diff -Nru sdcc-4.0.0+dfsg/src/SDCCicode.h sdcc-4.2.0+dfsg/src/SDCCicode.h
--- sdcc-4.0.0+dfsg/src/SDCCicode.h	2019-10-13 14:48:53.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/SDCCicode.h	2021-05-17 13:45:17.000000000 +0000
@@ -148,6 +148,8 @@
   unsigned bankSaved:1;         /* register bank has been saved */
   unsigned builtinSEND:1;       /* SEND for parameter of builtin function */
   bool localEscapeAlive:1;      /* At this iCode, a local variable, a pointer to which has escaped (e.g. by having been stored in a global variable, cast to integer, passed to function) might be alive. */
+  bool parmEscapeAlive:1;       /* At this iCode, a stack parameter, a pointer to which has escaped (e.g. by having been stored in a global variable, cast to integer, passed to function) might be alive. */
+  unsigned inlined:1;           /* from an inlined function */
 
   struct iCode *next;           /* next in chain */
   struct iCode *prev;           /* previous in chain */
@@ -355,6 +357,9 @@
 operand *newiTempFromOp (operand *);
 iCode *getBuiltinParms (iCode *, int *, operand **);
 int isiCodeInFunctionCall (iCode *);
+operand *detachiCodeOperand (operand **, iCode *);
+void attachiCodeOperand (operand *, operand **, iCode *);
+
 /*-----------------------------------------------------------------*/
 /* declaration of exported variables                               */
 /*-----------------------------------------------------------------*/
diff -Nru sdcc-4.0.0+dfsg/src/SDCClabel.c sdcc-4.2.0+dfsg/src/SDCClabel.c
--- sdcc-4.0.0+dfsg/src/SDCClabel.c	2016-10-21 13:12:06.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/SDCClabel.c	2022-02-03 09:32:48.000000000 +0000
@@ -199,7 +199,7 @@
             continue;
 
           /* now make sure that this is the only */
-          /* referenece to the _trueLabel        */
+          /* reference to the _trueLabel        */
           if (IC_TRUE (loop) && hTabItemWithKey (labelRef, (IC_TRUE (loop))->key))
             {
               /* we just change the falseLabel */
@@ -415,7 +415,7 @@
           if (hTabItemWithKey (labelRef, (IC_LABEL (loop))->key))
             continue;
 
-          /* else eliminitate this one */
+          /* else eliminate this one */
           loop->prev->next = loop->next;        /* get this out of the chain */
           loop->next->prev = loop->prev;
           change++;
diff -Nru sdcc-4.0.0+dfsg/src/SDCC.lex sdcc-4.2.0+dfsg/src/SDCC.lex
--- sdcc-4.0.0+dfsg/src/SDCC.lex	2020-01-12 07:53:06.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/SDCC.lex	2021-08-08 17:13:19.000000000 +0000
@@ -173,10 +173,14 @@
 "alignof"               { count (); TKEYWORD2X (ALIGNOF); }
 "_Alignof"              { count (); return ALIGNOF; }
 "__builtin_offsetof"    { count (); return OFFSETOF; }
+"__builtin_rlc"         { count (); return RLC; }
+"__builtin_rrc"         { count (); return RRC; }
+"__builtin_swap"        { count (); return SWAP; }
 "__sram"                { count (); TKEYWORD (XDATA); }
 "static"                { count (); return STATIC; }
 "struct"                { count (); return STRUCT; }
 "switch"                { count (); return SWITCH; }
+"_Thread_local"         { count (); return THREAD_LOCAL; }
 "typedef"               { count (); return TYPEDEF; }
 "union"                 { count (); return UNION; }
 "unsigned"              { count (); return UNSIGNED; }
@@ -194,6 +198,10 @@
 "_Noreturn"             { count (); return NORETURN;}
 "restrict"              { count (); TKEYWORD99 (RESTRICT); }
 "__smallc"              { count (); TKEYWORD (SMALLC); }
+"__raisonance"          { count (); TKEYWORD (RAISONANCE); }
+"__iar"                 { count (); TKEYWORD (IAR); }
+"__cosmic"              { count (); TKEYWORD (COSMIC); }
+"__sdcccall"            { count (); return SDCCCALL; }
 "__preserves_regs"      { count (); return PRESERVES_REGS; }
 "__z88dk_fastcall"      { count (); TKEYWORD (Z88DK_FASTCALL); }
 "__z88dk_callee"        { count (); TKEYWORD (Z88DK_CALLEE); }
@@ -224,18 +232,16 @@
   count ();
   return check_type();
 }
-0[bB]{B}+{IS}?          {
-  if (!options.std_sdcc)
-    {
-      yyerror ("binary (0b) constants are not allowed in ISO C");
-    }
+0[bB]('?{B})+{IS}?          {
+  if (!options.std_sdcc && !options.std_c2x)
+    werror (W_BINARY_INTEGER_CONSTANT_C23);
   count ();
   yylval.val = constIntVal (yytext);
   return CONSTANT;
 }
-0[xX]{H}+{IS}?               { count (); yylval.val = constIntVal (yytext); return CONSTANT; }
-0[0-7]*{IS}?                 { count (); yylval.val = constIntVal (yytext); return CONSTANT; }
-[1-9]{D}*{IS}?               { count (); yylval.val = constIntVal (yytext); return CONSTANT; }
+0[xX]('?{H})+{IS}?           { count (); yylval.val = constIntVal (yytext); return CONSTANT; }
+0('?[0-7])*{IS}?             { count (); yylval.val = constIntVal (yytext); return CONSTANT; }
+[1-9]('?{D})*{IS}?           { count (); yylval.val = constIntVal (yytext); return CONSTANT; }
 {CP}?'(\\.|[^\\'])+'         { count (); yylval.val = charVal (yytext); return CONSTANT; /* ' make syntax highlighter happy */ }
 {D}+{E}{FS}?                 { count (); yylval.val = constFloatVal (yytext); return CONSTANT; }
 {D}*"."{D}+({E})?{FS}?       { count (); yylval.val = constFloatVal (yytext); return CONSTANT; }
@@ -245,7 +251,7 @@
 0[xX]{H}+"."{H}*({BE})?{FS}? { count (); if (!options.std_c99) werror(E_HEXFLOAT_C99); yylval.val = constFloatVal (yytext); return CONSTANT; }
 \"                           { count (); yylval.yystr = stringLiteral (0); return STRING_LITERAL; }
 "L\""                        { count (); if (!options.std_c95) werror(E_WCHAR_STRING_C95); yylval.yystr = stringLiteral ('L'); return STRING_LITERAL; }
-"u8\""                       { count (); if (!options.std_c11) werror(E_WCHAR_STRING_C11); yylval.yystr = stringLiteral (0); return STRING_LITERAL; }
+"u8\""                       { count (); if (!options.std_c11) werror(E_U8CHAR_STRING_C11); yylval.yystr = stringLiteral ('8'); return STRING_LITERAL; }
 "u\""                        { count (); if (!options.std_c11) werror(E_WCHAR_STRING_C11); yylval.yystr = stringLiteral ('u'); return STRING_LITERAL; }
 "U\""                        { count (); if (!options.std_c11) werror(E_WCHAR_STRING_C11); yylval.yystr = stringLiteral ('U'); return STRING_LITERAL; }
 ">>="                   { count (); yylval.yyint = RIGHT_ASSIGN; return RIGHT_ASSIGN; }
@@ -560,11 +566,17 @@
     case 'u': // UTF-16
       dbuf_append_str(&dbuf, "u\"");
       break;
-    case 'L':
+    case 'L': // UTF-32
+      enc = 'L';
+      dbuf_append_str(&dbuf, "L\"");
+      break;
     case 'U': // UTF-32
       enc = 'U';
       dbuf_append_str(&dbuf, "U\"");
       break;
+    case '8': // UTF-8
+      enc = '8';
+      dbuf_append_str(&dbuf, "u8\"");
     default: // UTF-8 or whatever else the source character set is encoded in
       dbuf_append_char(&dbuf, '"');
     }
@@ -677,7 +689,7 @@
           if (ch == EOF)
             goto out;
 
-          if (ch == 'u' || ch == 'U' || ch == 'L') /* Could be an utf-16 or utf-32 wide string literal prefix */
+          if (ch == 'u' || ch == 'U' || ch == 'L') /* Could be an utf-16 or utf-32 wide string literal prefix or an utf-8 prefix */
             {
               int ch2;
 
@@ -698,6 +710,8 @@
                       dbuf_prepend_char(&dbuf, ch == 'L' ? 'U' : ch);
                       enc = ch;
                     }
+                  else if (enc != ch)
+                    werror (W_PREFIXED_STRINGS);
                   count_char(ch);
                   count_char(ch2);
                   break;
@@ -721,6 +735,10 @@
                   unput('u');
                   goto out;
                 }
+              if (!enc)
+                enc = '8';
+              else if (enc != '8')
+                werror (W_PREFIXED_STRINGS);
             }
           if (ch != '"')
             {
diff -Nru sdcc-4.0.0+dfsg/src/SDCCloop.c sdcc-4.2.0+dfsg/src/SDCCloop.c
--- sdcc-4.0.0+dfsg/src/SDCCloop.c	2018-08-08 08:08:15.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/SDCCloop.c	2022-02-03 09:32:48.000000000 +0000
@@ -349,7 +349,7 @@
   int opin = 0;
   /* operand is an invariant if it is a                */
   /*       a. constants .                              */
-  /*       b. that have defintions reaching loop entry */
+  /*       b. that have definitions reaching loop entry */
   /*       c. that are already defined as invariant    */
   /*       d. has no assignments in the loop           */
   if (op)
@@ -550,7 +550,7 @@
               set *lSet = setFromSet (theLoop->regBlocks);
 
               /* if this block does not dominate all exits */
-              /* make sure this defintion is not used anywhere else */
+              /* make sure this definition is not used anywhere else */
               if (!domsAllExits)
                 {
                   if (isOperandGlobal (IC_RESULT (ic)))
@@ -781,7 +781,7 @@
 
   /* if the number of exits is greater than one then
      we use another trick: we will create an intersection
-     of succesors of the exits, then take those that are not
+     of successors of the exits, then take those that are not
      part of the loop and have dfNumber greater loop entry (eblock),
      insert a new predecessor postLoopBlk before them and add
      a copy of ic in the new block. The postLoopBlk in between
@@ -1009,7 +1009,7 @@
           /* Only consider variables with integral type. */
           /* (2004/12/06 - EEP - ds390 fails regression tests unless */
           /* pointers are also considered for induction (due to some */
-          /* register alloctaion bugs). Remove !IS_PTR clause when */
+          /* register allocation bugs). Remove !IS_PTR clause when */
           /* that gets fixed) */
           optype = operandType (IC_RIGHT (ic));
           if (!IS_INTEGRAL (optype) && !IS_PTR (optype))
@@ -1096,6 +1096,7 @@
                  but it's a nice to see a clean dumploop now. */
               remiCodeFromeBBlock (lBlock, ic);
               /* clear the definition */
+              bitVectUnSetBit (OP_DEFS (IC_RESULT (ic)), ic->key);
               bitVectUnSetBit (lBlock->defSet, ic->key);
               ic = saveic;
             }
@@ -1215,6 +1216,7 @@
           ic->op = '=';
           IC_LEFT (ic) = NULL;
           IC_RIGHT (ic) = IC_RESULT (ic);
+          bitVectUnSetBit (OP_USES (aSym), ic->key);
 
           /* Insert an update of the induction variable just before */
           /* the update of the basic induction variable. */
diff -Nru sdcc-4.0.0+dfsg/src/SDCClospre.cc sdcc-4.2.0+dfsg/src/SDCClospre.cc
--- sdcc-4.0.0+dfsg/src/SDCClospre.cc	2019-12-09 13:03:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/SDCClospre.cc	2021-06-08 11:57:11.000000000 +0000
@@ -90,7 +90,6 @@
     ic->op != RRC &&
     ic->op != RLC &&
     ic->op != GETABIT &&
-    ic->op != GETHBIT &&
     ic->op != LEFT_OP &&
     ic->op != RIGHT_OP &&
     !(ic->op == '=' && !POINTER_SET(ic) && !(IS_ITEMP(IC_RIGHT(ic)) /*&& IC_RIGHT(ic)->key > lkey*/)) &&
@@ -223,9 +222,9 @@
   if (eic->op == GET_VALUE_AT_ADDRESS && !optimize.allow_unsafe_read)
     safety_required = true;
 
-  // The division routines for z80-like ports and the hc08/s08's and stm8's hardware division just give an undefined result
+  // The division routines for z80-like ports, the hc08/s08's, the pdk ports and stm8's hardware division just give an undefined result
   // for division by zero, but there are no harmful side effects. I don't know about the other ports.
-  if ((eic->op == '/' || eic->op == '%') && !TARGET_Z80_LIKE && !TARGET_HC08_LIKE && !TARGET_IS_STM8)
+  if ((eic->op == '/' || eic->op == '%') && !TARGET_Z80_LIKE && !TARGET_HC08_LIKE && !TARGET_PDK_LIKE && !TARGET_IS_STM8)
     safety_required = true;
 
   // TODO: Relax this! There are cases where allowing unsafe optimizations will improve speed.
@@ -281,7 +280,8 @@
 // Dump tree decomposition.
 static void dump_dec_lospre(const tree_dec_t &tree_dec)
 {
-  wassert (currFunc);
+  if (!currFunc)
+    return;
 
   std::ofstream dump_file((std::string(dstFileName) + ".dumplospredec" + currFunc->rname + ".dot").c_str());
 
diff -Nru sdcc-4.0.0+dfsg/src/SDCClospre.hpp sdcc-4.2.0+dfsg/src/SDCClospre.hpp
--- sdcc-4.0.0+dfsg/src/SDCClospre.hpp	2018-12-31 19:37:10.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/SDCClospre.hpp	2021-07-04 08:59:36.000000000 +0000
@@ -729,6 +729,8 @@
           IC_RESULT(ic) = operandFromOperand (IC_RESULT (ic));
           IC_RESULT(ic)->isaddr = 0;
         }
+      else
+        continue; // pointer set is not an assignment, so no need to forward
       if(IS_OP_VOLATILE(IC_RESULT (ic)))
         continue;
 
@@ -748,7 +750,10 @@
     }
 
   if(substituted < split) // Todo: Remove this warning when optimization for speed instead of code size is implemented!
-    std::cout << "Introduced " << OP_SYMBOL_CONST(tmpop)->name << ", but did substitute only " << substituted << " calculations, while introducing "<< split << ".\n"; std::cout.flush();
+    {
+      std::cout << "Introduced " << OP_SYMBOL_CONST(tmpop)->name << ", but did substitute only " << substituted << " calculations, while introducing "<< split << ".\n";
+      std::cout.flush();
+    }
 
   return(1);
 }
diff -Nru sdcc-4.0.0+dfsg/src/SDCClrange.c sdcc-4.2.0+dfsg/src/SDCClrange.c
--- sdcc-4.0.0+dfsg/src/SDCClrange.c	2019-11-28 21:10:51.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/SDCClrange.c	2021-05-13 09:35:46.000000000 +0000
@@ -442,11 +442,13 @@
 /*                  - fix the life range, if the symbol is used in  */
 /*                    a loop                                        */
 /*------------------------------------------------------------------*/
-static void
+static int
 findPrevUse (eBBlock *ebp, iCode *ic, operand *op,
              eBBlock ** ebbs, int count,
              bool emitWarnings)
 {
+  int change=0;
+
   unvisitBlocks (ebbs, count);
 
   if (op->isaddr)
@@ -463,16 +465,85 @@
             {
               if (OP_SYMBOL (op)->prereqv)
                 {
+                  iCode *newic, *ip;
+                  value *val;
+                  bitVect * dom = NULL;
+                  bitVect * used;
+                  int i, blocknum;
                   werrorfl (ic->filename, ic->lineno, W_LOCAL_NOINIT,
                             OP_SYMBOL (op)->prereqv->name);
-                  OP_SYMBOL (op)->prereqv->reqv = NULL;
-                  OP_SYMBOL (op)->prereqv->allocreq = 1;
+
+                  /* iTemps must have a valid initial value, otherwise */
+                  /* downstream algorithms will have problems. If      */
+                  /* there's a problem with the user program such that */
+                  /* something was left undefined, add an initializer  */
+                  /* to the last common dominator before defs/uses.    */
+                  /* First, find the common dominators of all defs/uses */
+                  unvisitBlocks (ebbs, count);
+                  used = newBitVect (count);
+                  for (i=0; ieBBlockNum]->visited)
+                            continue;
+                          ebbs[usedic->eBBlockNum]->visited = 1;
+                          if (bitVectBitValue (OP_USES (op), i))
+                            used = bitVectSetBit (used, usedic->eBBlockNum);
+                          blockdomVect = ebbs[usedic->eBBlockNum]->domVect;
+                          if (dom)
+                            dom = bitVectInplaceIntersect (dom, blockdomVect);
+                          else
+                            dom = bitVectCopy (blockdomVect);
+                        }
+                    }
+                  /* Find the common dominator with highest block num */
+                  blocknum = 0;
+                  for (i=0; isize; i++)
+                    if (bitVectBitValue (dom, i) && !ebbs[i]->partOfLoop)
+                      blocknum = i;
+                  /* If there was a use in this block, set the insertion */
+                  /* point near the beginning of the block, otherwise */
+                  /* near the end */
+                  if (bitVectBitValue (used, blocknum))
+                    {
+                      ip = ebbs[blocknum]->sch;
+                      while (ip && (ip->op == LABEL || ip->op == FUNCTION || ip->op == RECEIVE))
+                        ip = ip->next;
+                    }
+                  else
+                    ip = NULL;
+                  /* Finally, create initializer and insert it*/
+                  val = valCastLiteral (operandType (op), 0.0, 0);
+                  newic = newiCode ('=', NULL, operandFromValue (val));
+                  IC_RESULT (newic) = operandFromOperand (op);
+                  IC_RESULT (newic)->isaddr = 0;
+                  OP_DEFS (IC_RESULT (newic)) = OP_DEFS (op) = bitVectSetBit (OP_DEFS (op), newic->key);
+                  addiCodeToeBBlock (ebbs[blocknum], newic, ip);
+                  newic->eBBlockNum = blocknum;
+                  if (!ip && newic->prev)
+                    {
+                      newic->filename = newic->prev->filename;
+                      newic->lineno = newic->prev->lineno;
+                    }
+                  ebbs[blocknum]->defSet = bitVectSetBit (ebbs[blocknum]->defSet, newic->key);
+                  freeBitVect (used);
+                  freeBitVect (dom);
+                  change++;
                 }
             }
           else
             {
               werrorfl (ic->filename, ic->lineno, W_LOCAL_NOINIT,
                         OP_SYMBOL (op)->name);
+              OP_SYMBOL (op)->allocreq=1;
+              OP_SYMBOL (op)->addrtaken=1; /* just to force allocation */
             }
         }
       /* is this block part of a loop? */
@@ -483,6 +554,7 @@
           markWholeLoop (ebp, op->key);
         }
     }
+  return change;
 }
 
 /*-----------------------------------------------------------------*/
@@ -525,12 +597,13 @@
 /* to find use of unitialized AUTOSYMs (an ITEMP is an AUTOSYM).   */
 /* also, update funcUsesVolatile flag for current function         */
 /*-----------------------------------------------------------------*/
-static void
+static int
 rlivePoint (eBBlock ** ebbs, int count, bool emitWarnings)
 {
   int i, key;
   eBBlock *succ;
   bitVect *alive;
+  int change = 0;
 
   bool uses_volatile = false;
 
@@ -550,7 +623,7 @@
 
 	  if (SKIP_IC2(ic))
 	    continue;
-
+      if (ebbs[i]->noPath) continue;
 	  if (ic->op == JUMPTABLE && IS_SYMOP(IC_JTCOND(ic)))
 	    {
 	      incUsed (ic, IC_JTCOND(ic));
@@ -558,7 +631,7 @@
 	      if (!IS_AUTOSYM(IC_JTCOND(ic)))
 	        continue;
 
-	      findPrevUse (ebbs[i], ic, IC_JTCOND(ic), ebbs, count, emitWarnings);
+	      change += findPrevUse (ebbs[i], ic, IC_JTCOND(ic), ebbs, count, emitWarnings);
               if (IS_ITEMP(IC_JTCOND(ic)))
                 {
                   unvisitBlocks(ebbs, count);
@@ -576,7 +649,7 @@
 	      if (!IS_AUTOSYM(IC_COND(ic)))
 	        continue;
 
-	      findPrevUse (ebbs[i], ic, IC_COND(ic), ebbs, count, emitWarnings);
+	      change += findPrevUse (ebbs[i], ic, IC_COND(ic), ebbs, count, emitWarnings);
               if (IS_ITEMP(IC_COND(ic)))
                 {
                   unvisitBlocks (ebbs, count);
@@ -593,15 +666,15 @@
 	      if (IS_AUTOSYM(IC_LEFT(ic)) &&
 	          ic->op != ADDRESS_OF)
 	        {
-	          findPrevUse (ebbs[i], ic, IC_LEFT(ic), ebbs, count, emitWarnings);
+	          change += findPrevUse (ebbs[i], ic, IC_LEFT(ic), ebbs, count, emitWarnings);
                   if (IS_ITEMP(IC_LEFT(ic)))
                     {
                       unvisitBlocks(ebbs, count);
                       ic->rlive = bitVectSetBit (ic->rlive, IC_LEFT(ic)->key);
                       findNextUse (ebbs[i], ic->next, IC_LEFT(ic));
 
-                      /* if this is a send extend the LR to the call */
-                      if (ic->op == SEND)
+                      // If this is a send extend the LR to the call. For new register allocator we want this for builtin send only.
+                      if (ic->op == SEND && !((TARGET_Z80_LIKE || TARGET_PDK_LIKE || TARGET_IS_STM8) && !ic->builtinSEND))
                         {
                           iCode *lic;
                           for (lic = ic; lic; lic = lic->next)
@@ -622,7 +695,7 @@
 	      incUsed (ic, IC_RIGHT(ic));
               if (IS_AUTOSYM(IC_RIGHT(ic)))
 	        {
-	          findPrevUse (ebbs[i], ic, IC_RIGHT(ic), ebbs, count, emitWarnings);
+	          change += findPrevUse (ebbs[i], ic, IC_RIGHT(ic), ebbs, count, emitWarnings);
                   if (IS_ITEMP(IC_RIGHT(ic)))
                     {
                       unvisitBlocks(ebbs, count);
@@ -639,7 +712,7 @@
 	    {
 	      if (POINTER_SET(ic))
 	        {
-	          findPrevUse (ebbs[i], ic, IC_RESULT(ic), ebbs, count, emitWarnings);
+	          change += findPrevUse (ebbs[i], ic, IC_RESULT(ic), ebbs, count, emitWarnings);
 		}
               if (IS_ITEMP(IC_RESULT(ic)))
                 {
@@ -689,6 +762,7 @@
 
   if(currFunc)
     currFunc->funcUsesVolatile = uses_volatile;
+  return change;
 }
 
 /*-----------------------------------------------------------------*/
@@ -856,6 +930,7 @@
 void
 computeLiveRanges (eBBlock **ebbs, int count, bool emitWarnings)
 {
+  int change;
   /* first look through all blocks and adjust the
      sch and ech pointers */
   adjustIChain (ebbs, count);
@@ -863,17 +938,22 @@
   /* sequence the code the live ranges are computed
      in terms of this sequence additionally the
      routine will also create a hashtable of instructions */
-  iCodeSeq = 0;
-  setToNull ((void *) &iCodehTab);
-  iCodehTab = newHashTable (iCodeKey);
-  hashiCodeKeys (ebbs, count);
-  setToNull ((void *) &iCodeSeqhTab);
-  iCodeSeqhTab = newHashTable (iCodeKey);
-  sequenceiCode (ebbs, count);
-
-  /* mark the ranges live for each point */
-  setToNull ((void *) &liveRanges);
-  rlivePoint (ebbs, count, emitWarnings);
+  do
+    {
+      iCodeSeq = 0;
+      setToNull ((void *) &iCodehTab);
+      iCodehTab = newHashTable (iCodeKey);
+      hashiCodeKeys (ebbs, count);
+      setToNull ((void *) &iCodeSeqhTab);
+      iCodeSeqhTab = newHashTable (iCodeKey);
+      sequenceiCode (ebbs, count);
+
+      /* mark the ranges live for each point */
+      setToNull ((void *) &liveRanges);
+      change = rlivePoint (ebbs, count, emitWarnings);
+      emitWarnings = FALSE;
+    }
+  while (change);
 
   /* mark the from & to live ranges for variables used */
   markLiveRanges (ebbs, count);
diff -Nru sdcc-4.0.0+dfsg/src/SDCCmacro.c sdcc-4.2.0+dfsg/src/SDCCmacro.c
--- sdcc-4.0.0+dfsg/src/SDCCmacro.c	2011-03-22 20:33:32.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/SDCCmacro.c	2022-02-03 09:32:48.000000000 +0000
@@ -122,7 +122,7 @@
     }
 
 
-  /* If we did something then recursivly expand any expanded macros */
+  /* If we did something then recursively expand any expanded macros */
   if (fdidsomething)
     {
       char *ret = eval_macros (pvals, dbuf_c_str (&dbuf));
@@ -141,14 +141,14 @@
 
   dbuf_init (&dbuf, 256);
 
-  /* Recursivly evaluate all the macros in the string */
+  /* Recursively evaluate all the macros in the string */
   p = eval_macros (pvals, pformat);
 
   /* Evaluate all the arguments */
   dbuf_vprintf (&dbuf, p, ap);
   Safe_free (p);
 
-  /* Recursivly evaluate any macros that were used as arguments */
+  /* Recursively evaluate any macros that were used as arguments */
   p = eval_macros (pvals, dbuf_c_str (&dbuf));
   dbuf_destroy (&dbuf);
   return p;
diff -Nru sdcc-4.0.0+dfsg/src/SDCCmain.c sdcc-4.2.0+dfsg/src/SDCCmain.c
--- sdcc-4.0.0+dfsg/src/SDCCmain.c	2019-03-14 16:34:34.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/SDCCmain.c	2022-02-24 20:52:17.000000000 +0000
@@ -76,6 +76,15 @@
 set *libDirsSet = NULL;         /* list of lib search directories */
 bool regalloc_dry_run = FALSE;
 
+/* language override constants and variable for handling -x during command line parsing */
+enum
+{
+  LANG_OVERRIDE_NONE,
+  LANG_OVERRIDE_C,
+  LANG_OVERRIDE_C_HEADER
+};
+int langOverride = LANG_OVERRIDE_NONE;
+
 static const char *dstPath = "";          /* path for the output files; */
                                           /* "" is equivalent with cwd */
 static const char *moduleNameBase = NULL; /* module name base is source file without path and extension */
@@ -152,6 +161,7 @@
 #define OPTION_DUMP_AST             "--dump-ast"
 #define OPTION_DUMP_I_CODE          "--dump-i-code"
 #define OPTION_DUMP_GRAPHS          "--dump-graphs"
+#define OPTION_INCLUDE              "--include"
 
 #define OPTION_SMALL_MODEL          "--model-small"
 #define OPTION_MEDIUM_MODEL         "--model-medium"
@@ -164,18 +174,20 @@
   {'v', OPTION_VERSION, NULL, "Display sdcc's version"},
   {0,   "--verbose", &options.verbose, "Trace calls to the preprocessor, assembler, and linker"},
   {'V', NULL, &options.verboseExec, "Execute verbosely. Show sub commands as they are run"},
-  {'d', NULL, NULL, "Output list of mcaro definitions in effect. Use with -E"},
+  {'d', NULL, NULL, "Output list of macro definitions in effect. Use with -E"},
   {'D', NULL, NULL, "Define macro as in -Dmacro"},
   {'I', NULL, NULL, "Add to the include (*.h) path, as in -Ipath"},
   {'A', NULL, NULL, NULL},
   {'U', NULL, NULL, "Undefine macro as in -Umacro"},
   {'M', NULL, NULL, "Preprocessor option"},
   {'W', NULL, NULL, "Pass through options to the pre-processor (p), assembler (a) or linker (l)"},
+  {0,   OPTION_INCLUDE, NULL, "Pre-include a file during pre-processing"},
   {'S', NULL, &noAssemble, "Compile only; do not assemble or link"},
   {'c', "--compile-only", &options.cc_only, "Compile and assemble, but do not link"},
   {'E', "--preprocessonly", &preProcOnly, "Preprocess only, do not compile"},
   {0,   "--c1mode", &options.c1mode, "Act in c1 mode.  The standard input is preprocessed code, the output is assembly code."},
   {'o', NULL, NULL, "Place the output into the given path resp. file"},
+  {'x', NULL, NULL, "Optional file type override (c, c-header or none), valid until the next -x"},
   {0,   OPTION_PRINT_SEARCH_DIRS, &options.printSearchDirs, "display the directories in the compiler's search path"},
   {0,   OPTION_MSVC_ERROR_STYLE, &options.vc_err_style, "messages are compatible with Micro$oft visual studio"},
   {0,   OPTION_USE_STDOUT, NULL, "send errors to stdout instead of stderr"},
@@ -208,7 +220,6 @@
   {0,   "--float-reent", &options.float_rent, "Use reentrant calls on the float support functions"},
   {0,   "--xram-movc", &options.xram_movc, "Use movc instead of movx to read xram (xdata)"},
   {0,   OPTION_CALLEE_SAVES, &options.calleeSavesSet, " Cause the called function to save registers instead of the caller", CLAT_SET},
-  {0,   "--profile", &options.profile, "On supported ports, generate extra profiling information"},
   {0,   "--fomit-frame-pointer", &options.omitFramePtr, "Leave out the frame pointer."},
   {0,   "--all-callee-saves", &options.all_callee_saves, "callee will always save registers used"},
   {0,   "--stack-probe", &options.stack_probe, "insert call to function __stack_probe at each function prologue"},
@@ -283,7 +294,6 @@
 
 static const UNSUPPORTEDOPT unsupportedOptTable[] = {
   {'X', NULL, "use --xstack-loc instead"},
-  {'x', NULL, "use --xstack instead"},
   {'i', NULL, "use --idata-loc instead"},
   {'r', NULL, "use --xdata-loc instead"},
   {'s', NULL, "use --code-loc instead"},
@@ -318,11 +328,14 @@
 #if !OPT_DISABLE_R2K
   &r2k_port,
 #endif
+#if !OPT_DISABLE_R2KA
+  &r2ka_port,
+#endif
 #if !OPT_DISABLE_R3KA
   &r3ka_port,
 #endif
-#if !OPT_DISABLE_GBZ80
-  &gbz80_port,
+#if !OPT_DISABLE_SM83
+  &sm83_port,
 #endif
 #if !OPT_DISABLE_TLCS90
   &tlcs90_port,
@@ -330,6 +343,9 @@
 #if !OPT_DISABLE_EZ80_Z80
   &ez80_z80_port,
 #endif
+#if !OPT_DISABLE_Z80N
+  &z80n_port,
+#endif
 #if !OPT_DISABLE_AVR
   &avr_port,
 #endif
@@ -366,6 +382,12 @@
 #if !OPT_DISABLE_PDK15
   &pdk15_port,
 #endif
+#if !OPT_DISABLE_MOS6502
+  &mos6502_port,
+#endif
+#if !OPT_DISABLE_MOS65C02
+  &mos65c02_port,
+#endif
 };
 
 #define NUM_PORTS (sizeof(_ports)/sizeof(_ports[0]))
@@ -633,6 +655,7 @@
   options.out_fmt = 0;
   options.dump_graphs = 0;
   options.dependencyFileOpt = 0;
+  options.sdcccall = port->sdcccall;
 
   /* now for the optimizations */
   /* turn on the everything */
@@ -667,7 +690,7 @@
   /* get the file extension.
      If no '.' then we don't know what the file type is
      so give an error and return */
-  if (!dbuf_splitFile (s, &path, &ext))
+  if (!dbuf_splitFile (s, &path, &ext) && langOverride == LANG_OVERRIDE_NONE)
     {
       werror (E_UNKNOWN_FEXT, s);
 
@@ -679,7 +702,8 @@
 
   /* otherwise depending on the file type */
   extp = dbuf_c_str (&ext);
-  if (STRCASECMP (extp, ".c") == 0 || STRCASECMP (extp, ".h") == 0)
+  if (STRCASECMP (extp, ".c") == 0 || langOverride == LANG_OVERRIDE_C
+      || STRCASECMP (extp, ".h") == 0 || langOverride == LANG_OVERRIDE_C_HEADER)
     {
       char *p, *m;
 
@@ -700,7 +724,7 @@
       fullSrcFileName = s;
       if (!(srcFile = fopen (fullSrcFileName, "r")))
         {
-          werror (E_FILE_OPEN_ERR, s);
+          werror (E_INPUT_FILE_OPEN_ERR, fullSrcFileName, strerror (errno));
 
           dbuf_destroy (&path);
 
@@ -1295,6 +1319,13 @@
               continue;
             }
 
+          if (strcmp (argv[i], OPTION_INCLUDE) == 0)
+            {
+              addSet (&preArgvSet, Safe_strdup ("-include"));
+              addSet (&preArgvSet, getStringArg (OPTION_INCLUDE, argv, &i, argc));
+              continue;
+            }
+
           werror (W_UNKNOWN_OPTION, argv[i]);
           continue;
         }
@@ -1368,6 +1399,21 @@
                 break;
               }
 
+            case 'x':
+              {
+                char *langName = getStringArg ("-x", argv, &i, argc);
+
+                if (strcmp (langName, "none") == 0)
+                  langOverride = LANG_OVERRIDE_NONE;
+                else if (strcmp (langName, "c") == 0)
+                  langOverride = LANG_OVERRIDE_C;
+                else if (strcmp (langName, "c-header") == 0)
+                  langOverride = LANG_OVERRIDE_C_HEADER;
+                else
+                  werror (E_INVALID_LANG_OVERRIDE);
+                break;
+              }
+
             case 'W':
               /* pre-processer options */
               if (argv[i][2] == 'p')
@@ -1600,7 +1646,7 @@
       if (debugFile->openFile (dbuf_c_str (&adbFile)))
         debugFile->writeModule (moduleName);
       else
-        werror (E_FILE_OPEN_ERR, dbuf_c_str (&adbFile));
+        werror (E_OUTPUT_FILE_OPEN_ERR, dbuf_c_str (&adbFile), strerror (errno));
 
       dbuf_destroy (&adbFile);
     }
@@ -1671,11 +1717,11 @@
       dbuf_printf (&linkerScriptFileName, "%s.lk", dstFileName);
       if (!(lnkfile = fopen (dbuf_c_str (&linkerScriptFileName), "w")))
         {
-          werror (E_FILE_OPEN_ERR, dbuf_c_str (&linkerScriptFileName));
+          werror (E_OUTPUT_FILE_OPEN_ERR, dbuf_c_str (&linkerScriptFileName), strerror (errno));
           exit (EXIT_FAILURE);
         }
 
-      if (TARGET_Z80_LIKE)
+      if (TARGET_Z80_LIKE||TARGET_MOS6502_LIKE)
         {
           fprintf (lnkfile, "-mjwx\n-%c %s\n", out_fmt, dbuf_c_str (&binFileName));
         }
@@ -1684,13 +1730,9 @@
           fprintf (lnkfile, "-muwx\n-%c %s\n", out_fmt, dbuf_c_str (&binFileName));
           if (TARGET_MCS51_LIKE)
             fprintf (lnkfile, "-M\n");
-          if (!options.no_pack_iram)
-            fprintf (lnkfile, "-Y\n");
-          else
-            werror (W_DEPRECATED_OPTION, "--no-pack-iram");
         }
 
-      if (!TARGET_Z80_LIKE)   /* Not for the z80, gbz80 */
+      if (!TARGET_Z80_LIKE)   /* Not for the z80 and related */
         {
           /* if iram size specified */
           if (options.iram_size)
@@ -1722,7 +1764,7 @@
     if (segName) { Safe_free (segName); } \
   }
 
-      if (!TARGET_Z80_LIKE)   /* Not for the z80, z180, gbz80 */
+      if (!TARGET_Z80_LIKE)   /* Not for the z80 and related */
         {
 
           /* code segment start */
@@ -1739,7 +1781,11 @@
              the best place for xdata */
           if (options.xdata_loc)
             {
-              WRITE_SEG_LOC (XDATA_NAME, options.xdata_loc);
+	      if(!TARGET_MOS6502_LIKE) {
+		WRITE_SEG_LOC (XDATA_NAME, options.xdata_loc);
+	      } else {
+		WRITE_SEG_LOC ("_DATA", options.xdata_loc);
+	      }
             }
 
           /* pdata/xstack segment start. If zero, the linker
@@ -1759,12 +1805,14 @@
           WRITE_SEG_LOC (BIT_NAME, 0);
 
           /* stack start */
-          if ((options.stack_loc) && (options.stack_loc < 0x100) && !TARGET_HC08_LIKE)
+          if ((options.stack_loc) && (options.stack_loc < 0x100) && TARGET_MCS51_LIKE && !TARGET_MOS6502_LIKE)
             {
               WRITE_SEG_LOC ("SSEG", options.stack_loc);
+              /* with the disappearance of --no-pack-iram I don't think this is ever valid anymore */
+              werror (W_DEPRECATED_OPTION, "--stack-loc");
             }
         }
-      else                      /* For the z80, z180, gbz80 */
+      else                      /* For the z80 and related */
         {
           WRITE_SEG_LOC ("_CODE", options.code_loc);
           WRITE_SEG_LOC ("_DATA", options.data_loc);
@@ -2123,6 +2171,12 @@
           break;
         }
 
+      /* set macro for optimization level */
+      if (optimize.codeSpeed)
+        addSet (&preArgvSet, Safe_strdup ("-D__SDCC_OPTIMIZE_SPEED"));
+      if (optimize.codeSize)
+        addSet (&preArgvSet, Safe_strdup ("-D__SDCC_OPTIMIZE_SIZE"));
+
       /* set macro corresponding to compiler option */
       if (options.intlong_rent)
         addSet (&preArgvSet, Safe_strdup ("-D__SDCC_INT_LONG_REENT"));
@@ -2134,6 +2188,16 @@
       if (options.all_callee_saves)
         addSet(&preArgvSet, Safe_strdup("-D__SDCC_ALL_CALLEE_SAVES"));
 
+
+      /* set macro for ABI (calling convention) version */
+      {
+        struct dbuf_s dbuf;
+
+        dbuf_init (&dbuf, 32);
+        dbuf_printf (&dbuf, "-D__SDCCCALL=%d", options.sdcccall);
+        addSet (&preArgvSet, dbuf_detach_c_str (&dbuf));
+      }
+
       /* add SDCC version number */
       {
         struct dbuf_s dbuf;
@@ -2182,7 +2246,7 @@
       {
         struct dbuf_s dbuf;
 
-        dbuf_init (&dbuf, 20);        
+        dbuf_init (&dbuf, 20);
         dbuf_printf (&dbuf, "-D__SDCC_REVISION=%s", getBuildNumber ());
         addSet (&preArgvSet, dbuf_detach_c_str (&dbuf));
       }
@@ -2316,7 +2380,10 @@
 
       tempSet = processStrSet (dataDirsSet, NULL, INCLUDE_DIR_SUFFIX, NULL);
       includeDirsSet = processStrSet (tempSet, NULL, DIR_SEPARATOR_STRING, NULL);
-      includeDirsSet = processStrSet (includeDirsSet, NULL, port->target, NULL);
+      if (TARGET_IS_RABBIT) // Rabbits have a shared include directory.
+        includeDirsSet = processStrSet (includeDirsSet, NULL, "rab", NULL);
+      else
+        includeDirsSet = processStrSet (includeDirsSet, NULL, port->target, NULL);
       mergeSets (&includeDirsSet, tempSet);
 
       if (options.use_non_free)
diff -Nru sdcc-4.0.0+dfsg/src/SDCCmem.c sdcc-4.2.0+dfsg/src/SDCCmem.c
--- sdcc-4.0.0+dfsg/src/SDCCmem.c	2019-03-14 16:34:34.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/SDCCmem.c	2021-07-19 09:49:35.000000000 +0000
@@ -358,22 +358,24 @@
 {
   memmap *segment;
 
-  if (SPEC_ADDRSPACE (sym->etype))
+  const symbol *symbolspace = getAddrspace (sym->type);
+
+  if (symbolspace)
     {
       namedspacemap *nm;
       for (nm = namedspacemaps; nm; nm = nm->next)
-        if (!strcmp (nm->name, SPEC_ADDRSPACE (sym->etype)->name))
+        if (!strcmp (nm->name, symbolspace->name))
           break;
 
       if (!nm)
         {
           nm = Safe_alloc (sizeof (namedspacemap));
-          nm->name = Safe_alloc (strlen(SPEC_ADDRSPACE (sym->etype)->name) + 1);
-          strcpy (nm->name, SPEC_ADDRSPACE (sym->etype)->name);
-          nm->is_const = (SPEC_ADDRSPACE (sym->etype)->type && SPEC_CONST (SPEC_ADDRSPACE (sym->etype)->type));
+          nm->name = Safe_alloc (strlen(symbolspace->name) + 1);
+          strcpy (nm->name, symbolspace->name);
+          nm->is_const = (symbolspace->type && SPEC_CONST (symbolspace->type));
           nm->map = nm->is_const ?
-            allocMap (0, 1, 0, 0, 0, 1, options.code_loc, SPEC_ADDRSPACE (sym->etype)->name, 'C', CPOINTER) :
-            allocMap (0, 0, 0, 1, 0, 0, options.data_loc, SPEC_ADDRSPACE (sym->etype)->name, 'E', POINTER);
+            allocMap (0, 1, 0, 0, 0, 1, options.code_loc, symbolspace->name, 'C', CPOINTER) :
+            allocMap (0, 0, 0, 1, 0, 0, options.data_loc, symbolspace->name, 'E', POINTER);
           nm->next = namedspacemaps;
           namedspacemaps = nm;
         }
@@ -631,6 +633,12 @@
 
   for (lval = val; lval; lval = lval->next, pNum++)
     {
+      if (!lval->sym) // Can only happen if there was a syntax error in the declaration.
+        {
+          fatalError++;
+          return;
+        }
+        
       /* check the declaration */
       checkDecl (lval->sym, 0);
 
@@ -747,6 +755,9 @@
 
   for (lval = val; lval; lval = lval->next)
     {
+      if (!lval->sym) /* Syntax error in declaration */
+        continue;
+
       /* unmark is myparm */
       lval->sym->ismyparm = 0;
 
@@ -815,7 +826,7 @@
     }
 
   /* if volatile then */
-  if (IS_VOLATILE (sym->etype))
+  if (IS_VOLATILE (sym->type))
     sym->allocreq = 1;
 
   /* this is automatic           */
@@ -852,7 +863,7 @@
   /* else depending on the storage class specified */
 
   /* if this is a function then assign code space    */
-  if (IS_FUNC (sym->type))
+  if (IS_FUNC (sym->type) && !sym->isitmp)
     {
       SPEC_OCLS (sym->etype) = code;
       return;
@@ -1005,7 +1016,7 @@
       /* function then do args processing        */
       if (funcInChain (csym->type))
         {
-          processFuncArgs (csym);
+          processFuncArgs (csym, NULL);
         }
 
       /* if this is an extern variable then change */
diff -Nru sdcc-4.0.0+dfsg/src/SDCCopt.c sdcc-4.2.0+dfsg/src/SDCCopt.c
--- sdcc-4.0.0+dfsg/src/SDCCopt.c	2019-12-14 10:34:43.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/SDCCopt.c	2021-12-10 14:48:15.000000000 +0000
@@ -752,19 +752,13 @@
   SPEC_SHORT (leftType) = 0;
   SPEC_SHORT (rightType) = 0;
 
-  remiCodeFromeBBlock (ebp, ic);
-
   left = IC_LEFT (ic);
   right = IC_RIGHT (ic);
 
-  if (IS_SYMOP (left))
-      bitVectUnSetBit (OP_USES (left), ic->key);
-  if (IS_SYMOP (right))
-      bitVectUnSetBit (OP_USES (right), ic->key);
-
-  if (op == '*' && (muls16tos32[0] || muls16tos32[1]) &&
-    (IS_SYMOP (left) && bitVectnBitsOn (OP_DEFS (left)) == 1 && bitVectnBitsOn (OP_USES (left)) == 0 || IS_OP_LITERAL (left) && operandLitValue (left) < 32768 && operandLitValue (left) >= -32768) &&
-    (IS_SYMOP (right) && bitVectnBitsOn (OP_DEFS (right)) == 1 && bitVectnBitsOn (OP_USES (right)) == 0 || IS_OP_LITERAL (right) && operandLitValue (right) < 32768 && operandLitValue (right) >= -32768) &&
+  // Special case: 16x16->32 multiplication.
+  if (op == '*' && (muls16tos32[0] || muls16tos32[1] || port->hasNativeMulFor) &&
+    (IS_SYMOP (left) && bitVectnBitsOn (OP_DEFS (left)) == 1 && bitVectnBitsOn (OP_USES (left)) == 1 || IS_OP_LITERAL (left) && operandLitValue (left) < 32768 && operandLitValue (left) >= -32768) &&
+    (IS_SYMOP (right) && bitVectnBitsOn (OP_DEFS (right)) == 1 && bitVectnBitsOn (OP_USES (right)) == 1 || IS_OP_LITERAL (right) && operandLitValue (right) < 32768 && operandLitValue (right) >= -32768) &&
     getSize (leftType) == 4 && getSize (rightType) == 4)
     {
       iCode *lic = IS_SYMOP (left) ? hTabItemWithKey (iCodehTab, bitVectFirstBit (OP_DEFS (left))) : 0;
@@ -775,24 +769,29 @@
         {
           func = muls16tos32[SPEC_USIGN (operandType (left))];
 
-          if (lic)
+          if (func || port->hasNativeMulFor && lic && ric && port->hasNativeMulFor (ic, operandType (IC_RIGHT (lic)),operandType (IC_RIGHT (ric))))
             {
-              lic->op = '=';
-              OP_SYMBOL (left)->type = newIntLink();
-            }
-          else
-            IC_LEFT (ic) = operandFromValue (valCastLiteral (newIntLink(), operandLitValue (left), operandLitValue (left)));
+              if (lic)
+                {
+                  lic->op = '=';
+                  OP_SYMBOL (left)->type = newIntLink();
+                }
+              else
+                IC_LEFT (ic) = operandFromValue (valCastLiteral (newIntLink(), operandLitValue (left), operandLitValue (left)));
 
-          if (ric)
-            {
-              ric->op = '=';
-              OP_SYMBOL (right)->type = newIntLink();
-            }
-          else
-            IC_RIGHT (ic) = operandFromValue (valCastLiteral (newIntLink(), operandLitValue (right), operandLitValue (right)));
+              if (ric)
+                {
+                  ric->op = '=';
+                  OP_SYMBOL (right)->type = newIntLink();
+                }
+              else
+                IC_RIGHT (ic) = operandFromValue (valCastLiteral (newIntLink(), operandLitValue (right), operandLitValue (right)));
 
-          if (func)
-            goto found;
+              if (func) // Use 16x16->32 support function
+                goto found;
+              else // Native
+                return;
+            }
         }
     }
 
@@ -858,6 +857,13 @@
   werrorfl (filename, lineno, E_INVALID_OP, "");
   return;
 found:
+  remiCodeFromeBBlock (ebp, ic);
+
+  if (IS_SYMOP (left))
+      bitVectUnSetBit (OP_USES (left), ic->key);
+  if (IS_SYMOP (right))
+      bitVectUnSetBit (OP_USES (right), ic->key);
+
   /* if int & long support routines NOT compiled as reentrant */
   if (!options.intlong_rent)
     {
@@ -1014,27 +1020,36 @@
       goto convert;
     }
 
-  if ((TARGET_IS_Z80 || TARGET_IS_Z180 || TARGET_IS_RABBIT || TARGET_IS_EZ80_Z80) && (!strcmp (bif->name, "__builtin_memcpy") || !strcmp (bif->name, "__builtin_strncpy") || !strcmp (bif->name, "__builtin_memset")))
+  if ((TARGET_IS_Z80 || TARGET_IS_Z180 || TARGET_IS_RABBIT || TARGET_IS_EZ80_Z80 || TARGET_IS_Z80N) && (!strcmp (bif->name, "__builtin_memcpy") || !strcmp (bif->name, "__builtin_strncpy") || !strcmp (bif->name, "__builtin_memset")))
     {
-      /* Replace iff return value is used or last parameter is not an integer constant. */
-      if (bitVectIsZero (OP_USES (IC_RESULT (icc))) && IS_OP_LITERAL (IC_LEFT (lastparam)))
+      /* Replace iff return value is used or last parameter is not an integer constant (except for memcpy, where non-integers can be handled). */
+      if (bitVectIsZero (OP_USES (IC_RESULT (icc))) && (IS_OP_LITERAL (IC_LEFT (lastparam)) || !strcmp (bif->name, "__builtin_memcpy")))
         return;
-      
+
       strcpy(OP_SYMBOL (IC_LEFT (icc))->rname, !strcmp (bif->name, "__builtin_memcpy") ? "___memcpy" : (!strcmp (bif->name, "__builtin_strncpy") ? "_strncpy" : "_memset"));
       goto convert;
     }
-  
+
   return;
 
 convert:
   /* Convert parameter passings from SEND to PUSH. */
   stack = 0;
-  for (icc = ic; icc->op != CALL; icc = icc->next)
+  struct value *args;
+  for (icc = ic, args = FUNC_ARGS (nonbuiltin_memcpy->type); icc->op != CALL; icc = icc->next, args = args->next)
     {
+      wassert (args);
       icc->builtinSEND = 0;
-      icc->op = IPUSH;
-      icc->parmPush = 1;
-      stack += getSize (operandType (IC_LEFT (icc)));
+      if (IS_REGPARM (args->etype))
+        {
+          icc->argreg = SPEC_ARGREG (args->etype);
+        }
+      else
+        {
+          icc->op = IPUSH;
+          icc->parmPush = 1;
+          stack += getSize (operandType (IC_LEFT (icc)));
+        }
     }
   icc->parmBytes = stack;
 
@@ -1059,37 +1074,56 @@
     }
 }
 
+/*-----------------------------------------------------------------*/
+/* convconvention - handle calling convention                      */
+/*-----------------------------------------------------------------*/
 static void
-convsmallc (iCode *ic, eBBlock *ebp)
+convconvention (iCode *ic, eBBlock *ebp)
 {
   iCode *icc, *icp, *ico = NULL;
 
   assert (ic->op == CALL || ic->op == PCALL);
 
-  for (icc = ic->prev; icc && icc->op == IPUSH; icc = icc->prev)
-    ic = icc;
-  icp = icc;
+  sym_link *ftype = operandType (IC_LEFT (ic));
+  if (ic->op == PCALL)
+    ftype =ftype->next;
+
+  // Small-C passed stack parameters left-to-right.
+  if (FUNC_ISSMALLC (ftype))
+    {
+      for (icc = ic->prev; icc && icc->op == IPUSH; icc = icc->prev)
+        ic = icc;
+      icp = icc;
 
-  /* Reverse parameters. */
-  for (icc = ic; icc->op != CALL && icc->op != PCALL; icc = icc->next)
-    {
-      if (icc->next->op != CALL && icc->next->op != PCALL)
-        icc->prev = icc->next;
-      else
-        icc->prev = icp;
-    }
-  if (icc != ic)
-    {
-      if (icp)
-        icp->next = icc->prev;
-      else
-        ebp->sch = icc->prev;
-      icc->prev = ic;
+      /* Reverse parameters. */
+      for (icc = ic; icc->op != CALL && icc->op != PCALL; icc = icc->next)
+        {
+          if (icc->next->op != CALL && icc->next->op != PCALL)
+            icc->prev = icc->next;
+          else
+            icc->prev = icp;
+        }
+      if (icc != ic)
+        {
+          if (icp)
+            icp->next = icc->prev;
+          else
+            ebp->sch = icc->prev;
+          icc->prev = ic;
+        }
+      for (; icc != icp; ico = icc, icc = icc->prev)
+        {
+          if (icc->op != CALL && icc->op != PCALL)
+            icc->next = ico;
+        }
     }
-  for (; icc != icp; ico = icc, icc = icc->prev)
+  else if (FUNC_ISRAISONANCE (ftype) || FUNC_ISIAR (ftype) || FUNC_ISCOSMIC (ftype) || FUNC_ISZ88DK_FASTCALL (ftype))
+    ;
+  else // SDCC calling convention
     {
-      if (icc->op != CALL && icc->op != PCALL)
-        icc->next = ico;
+      // Use default ABI version if no ABI version is explicitly requested.
+      if (FUNC_SDCCCALL (ftype) < 0)
+        FUNC_SDCCCALL (ftype) = options.sdcccall;
     }
 }
 
@@ -1135,25 +1169,29 @@
           if (ic->op == '%' && isOperandLiteral (IC_RIGHT(ic)))
             {
               bool us = IS_UNSIGNED (operandType (IC_LEFT(ic)));
+              bool upcast = FALSE;
+              iCode *dic = NULL;
 
               // Chek if left really is just an upcasted unsigned value.
               if (!us && IS_SYMOP (IC_LEFT(ic)) && bitVectnBitsOn (OP_DEFS (IC_LEFT (ic))) == 1)
                 {
-                  iCode *dic = hTabItemWithKey (iCodehTab, bitVectFirstBit (OP_DEFS (IC_LEFT (ic))));
+                  dic = hTabItemWithKey (iCodehTab, bitVectFirstBit (OP_DEFS (IC_LEFT (ic))));
 
                   if (dic && dic->op == CAST && IS_UNSIGNED (operandType (IC_RIGHT (dic))) && getSize (operandType (IC_RIGHT (dic))) < getSize (operandType (IC_RESULT (dic))))
-                    us = true;
+                    us = upcast = true;
                 }
 
               if (us)
                 {
                   unsigned long litVal = double2ul (operandLitValue (IC_RIGHT (ic)));
-    
+
                   /* modulo by 1: no remainder */
                   if (litVal == 1)
                     {
                       ic->op = '=';
                       IC_RIGHT (ic) = operandFromLit (0);
+                      if (IS_SYMOP (IC_LEFT (ic)))
+                        bitVectUnSetBit (OP_USES (IC_LEFT (ic)), ic->key);
                       IC_LEFT (ic) = NULL;
                       continue;
                     }
@@ -1167,12 +1205,38 @@
                       // discard lowest set bit.
                       litVal >>= 1;
                     }
-    
+
                   if (!litVal)
                     {
                       ic->op = BITWISEAND;
                       IC_RIGHT(ic) = operandFromLit (operandLitValue (IC_RIGHT (ic)) - 1);
+                      if (upcast && IS_CHAR (operandType (IC_RIGHT (dic)))
+                          && bitVectnBitsOn (OP_USES (IC_LEFT (ic))) == 1)
+                        {
+                          // Use precasted value
+                          attachiCodeOperand (IC_RIGHT (dic), &IC_LEFT (ic), ic);
+                          // Change cast to assignmnent to self to avoid
+                          // reading IC_RIGHT (dic) twice in case it
+                          // was volatile
+                          attachiCodeOperand (IC_RESULT (dic), &IC_RIGHT (dic), dic);
+                          dic->op = '=';
+                          // If upcast from char, maybe there's a
+                          // corresponding downcast to char that could
+                          // be eliminated too
+                          if (bitVectnBitsOn (OP_USES (IC_RESULT (ic))) == 1)
+                            {
+                              iCode *uic;
+                              uic = hTabItemWithKey (iCodehTab, bitVectFirstBit (OP_USES (IC_RESULT (ic))));
+                              if (uic->op == CAST && IS_CHAR (operandType (IC_RESULT (uic))))\
+                                {
+                                  attachiCodeOperand (IC_RESULT (uic), &IC_RESULT (ic), ic);
+                                  attachiCodeOperand (IC_RESULT (uic), &IC_RIGHT (uic), uic);
+                                  uic->op = '=';
+                                }
+                            }
+                        }
                       continue;
+
                     }
                 }
             }
@@ -1211,10 +1275,9 @@
             {
               convbuiltin (ic, ebbs[i]);
             }
-          if ((ic->op == CALL  && IFFUNC_ISSMALLC (operandType (IC_LEFT (ic)))) ||
-              (ic->op == PCALL && IFFUNC_ISSMALLC (operandType (IC_LEFT (ic))->next)))
+          if (ic->op == CALL || ic->op == PCALL)
             {
-              convsmallc (ic, ebbs[i]);
+              convconvention (ic, ebbs[i]);
             }
         }
     }
@@ -1366,10 +1429,10 @@
           left = IC_LEFT (ic);
           right = IC_RIGHT (ic);
           result = IC_RESULT (ic);
-          
+
           /*printf ("Looking at ic %d, op %d\n", ic->key, (int)(ic->op));*/
-          
-          if (left && IS_SYMOP (left))
+
+          if (left && ic->op != ADDRESS_OF && IS_SYMOP (left))
             {
               if (POINTER_GET (ic))
                 {
@@ -1391,8 +1454,8 @@
               else
                 resultaddrspace = getAddrspace (OP_SYMBOL (result)->type);
             }
-            
-#if 0           
+
+#if 0
           if (leftaddrspace)
             printf("ic %d (dcl? %d) leftaddrspace %s\n", ic->key, (int)(IS_DECL  (OP_SYMBOL (left)->type)), leftaddrspace->name);
           if (rightaddrspace)
@@ -1400,14 +1463,14 @@
           if (resultaddrspace)
             printf("ic %d (dcl? %d) resultaddrspace %s\n", ic->key, (int)(IS_DECL  (OP_SYMBOL (result)->type)), resultaddrspace->name);
 #endif
-            
+
           if (ic->op == IPUSH && leftaddrspace)
             {
               operand *newop;
-              
-              source = OP_SYMBOL (left); 
+
+              source = OP_SYMBOL (left);
               newic = newiCode ('=', 0, left);
-              IC_RESULT (newic) = newop = newiTempOperand (source->type, 0);          
+              IC_RESULT (newic) = newop = newiTempOperand (source->type, 0);
               IC_LEFT (ic) = newop;
               leftaddrspace = 0;
               for (iic = ic; iic->prev && iic->prev->op == IPUSH; iic = iic->prev);
@@ -1417,7 +1480,7 @@
             resultaddrspace && leftaddrspace && resultaddrspace != leftaddrspace)
             {
               operand *newop;
-              
+
               if (rightaddrspace == resultaddrspace)
                 source = OP_SYMBOL (left);
               else
@@ -1436,15 +1499,15 @@
                 }
               iic = ic;
             }
-            
+
           if (newic)
             {
               newic->filename = ic->filename;
               newic->lineno = ic->lineno;
               hTabAddItem (&iCodehTab, newic->key, newic);
               addiCodeToeBBlock (ebbs[i], newic, iic);
-            } 
-            
+            }
+
           assert (!leftaddrspace || !resultaddrspace || leftaddrspace == resultaddrspace);
           assert (!rightaddrspace || !resultaddrspace || rightaddrspace == resultaddrspace);
         }
@@ -1479,8 +1542,8 @@
 
   /* Previous transformations in separateAddressSpaces() should
      ensure that at most one addressspace occours in each iCode. */
-  if (left && IS_SYMOP (left))
-    { 
+  if (left && ic->op != ADDRESS_OF && IS_SYMOP (left))
+    {
       if (POINTER_GET (ic))
         {
           assert (!(IS_DECL (OP_SYMBOL (left)->type) && DCL_PTR_ADDRSPACE (OP_SYMBOL (left)->type)));
@@ -1492,7 +1555,7 @@
   if (right && IS_SYMOP (right))
     rightaddrspace = getAddrspace (OP_SYMBOL (right)->type);
   if (result && IS_SYMOP (result))
-    { 
+    {
       if (POINTER_SET (ic))
         {
           assert (!(IS_DECL (OP_SYMBOL (result)->type) && DCL_PTR_ADDRSPACE (OP_SYMBOL (result)->type)));
@@ -1501,7 +1564,7 @@
       else
         resultaddrspace = getAddrspace (OP_SYMBOL (result)->type);
     }
-           
+
   addrspace = leftaddrspace;
   if (rightaddrspace)
     {
@@ -1553,14 +1616,14 @@
   for (; ic; ic = ic->next)
     {
       const symbol *const addrspace = getAddrspaceiCode (ic);
- 
+
       if (addrspace && addrspace != oldaddrspace)
-        { 
+        {
           switchAddressSpaceAt (ic, addrspace);
-          
+
           oldaddrspace = addrspace;
         }
-        
+
       /* Address space might not be preserved over these. */
       if (ic->op == LABEL || ic->op == CALL || ic->op == PCALL)
         oldaddrspace = 0;
@@ -1597,7 +1660,7 @@
 {
   operand * op = *opp;
   symbol * sym = OP_SYMBOL (op);
-  
+
   if (isLocalWithoutDef (sym))
     {
       werrorfl (ic->filename, ic->lineno, W_LOCAL_NOINIT, sym->name);
@@ -1639,7 +1702,7 @@
   for (i = 0; i < count; i++)
     {
       iCode *ic;
-      
+
       if (ebbs[i]->noPath)
         continue;
 
@@ -1667,7 +1730,7 @@
                 }
               continue;
             }
-          
+
           if (IS_TRUE_SYMOP (IC_RESULT (ic)))
             {
               OP_DEFS (IC_RESULT (ic)) = NULL;
@@ -1697,7 +1760,7 @@
   for (i = 0; i < count; i++)
     {
       iCode *ic;
-      
+
       if (ebbs[i]->noPath)
         continue;
 
@@ -2133,7 +2196,8 @@
             continue;
 
           // Only try to narrow wide counters.
-          if (!IS_INTEGRAL(oldcountertype) || bitsForType (oldcountertype) <= 8 || TARGET_IS_DS390 || TARGET_IS_DS400 || (!SPEC_USIGN (oldcountertype))) // TODO: Handle signed types as well, maybe even transform int to unsigned int?
+          // TODO: Handle signed types as well, maybe even transform int to unsigned int?
+          if (!IS_INTEGRAL(oldcountertype) || bitsForType (oldcountertype) <= 8 || TARGET_IS_DS390 || TARGET_IS_DS400 || (!SPEC_USIGN (oldcountertype)))
             continue;
 
           ifx = ifxForOp (IC_RESULT (ic), ic);
@@ -2143,14 +2207,14 @@
 
           /* For now we handle only loops that have no complex control flow inside them and where
              the loop is entered and left through ifx only */
-          for(uic = ebbs[i + 1]->sch; uic; uic = uic->next)
+          for (uic = ebbs[i + 1]->sch; uic; uic = uic->next)
             {
-              if(uic->op == GOTO && IC_LABEL (uic) == label)
+              if (uic->op == GOTO && IC_LABEL (uic) == label)
                 break;
 
-              if(!obstacle &&
-                (uic->op == CALL || uic->op == PCALL || uic->op == IFX || uic->op == LABEL ||
-                uic->op == GOTO && IC_LABEL (uic) != label || uic->op == INLINEASM))
+              if (!obstacle &&
+                  (uic->op == CALL || uic->op == PCALL || uic->op == IFX || uic->op == LABEL ||
+                   uic->op == GOTO && IC_LABEL (uic) != label || uic->op == INLINEASM))
                 {
                   obstacle = uic;
                   break;
@@ -2158,7 +2222,7 @@
             }
 
           // TODO: Proceed despite obstacle, but only consider array accesses before obstacle.
-          if(obstacle || !uic || uic->op != GOTO || IC_LABEL (uic) != label)
+          if (obstacle || !uic || uic->op != GOTO || IC_LABEL (uic) != label)
             continue;
 
           const bitVect *uses;
@@ -2172,7 +2236,17 @@
               iCode *mul_candidate = 0;
               uic = hTabItemWithKey (iCodehTab, bit);
 
-              if(uic->op == '+' && IS_OP_LITERAL (IC_RIGHT (uic)) && operandLitValue (IC_RIGHT (uic)) == 1 && isOperandEqual (IC_LEFT (uic), IC_LEFT (ic)))
+              if (!uic)
+                {
+                  /* This iCode has been deleted but is still        */
+                  /* referenced. This shouldn't happen if everything */
+                  /* else is managing OP_USES properly, but better   */
+                  /* to ignore the problem than crash. */
+                  //printf ("%s used in iCode %d, but iCode missing\n",  OP_SYMBOL (IC_LEFT (ic))->name, bit);
+                  continue;
+                }
+
+              if (uic->op == '+' && IS_OP_LITERAL (IC_RIGHT (uic)) && operandLitValue (IC_RIGHT (uic)) == 1 && isOperandEqual (IC_LEFT (uic), IC_LEFT (ic)))
                 {
                   inc = uic;
                   continue;
@@ -2194,19 +2268,21 @@
                     }
                 }
 
-              for (int i = 0; i < 8 && uic &&
-                (uic->op == CAST && bitsForType (operandType (IC_RESULT (uic))) >= 16 ||
-                uic->op == '=' || uic->op == '+' || uic->op == LEFT_OP ||
-                uic->op == '*' && IS_OP_LITERAL (IC_RIGHT (uic)) && operandLitValue (IC_RIGHT (uic)) >= 1); i++)
+              for (int i = 0;
+                   i < 8 && uic &&
+                   (uic->op == CAST && bitsForType (operandType (IC_RESULT (uic))) >= 16 ||
+                    uic->op == '=' || uic->op == '+' || uic->op == LEFT_OP ||
+                    uic->op == '*' && IS_OP_LITERAL (IC_RIGHT (uic)) && operandLitValue (IC_RIGHT (uic)) >= 1);
+                   i++)
                 {
                   prevresult = IC_RESULT (uic);
                   uic = hTabItemWithKey (iCodehTab, bitVectFirstBit (OP_USES (IC_RESULT (uic))));
                 }
- 
-              if(!uic)
+
+              if (!uic)
                 continue;
 
-              // Use as array index?    
+              // Use as array index?
               if (uic->op == GET_VALUE_AT_ADDRESS || POINTER_SET(uic) && isOperandEqual (IC_RESULT (uic), prevresult))
                 {
                   found = true;
@@ -2278,13 +2354,17 @@
           sym_link *resulttype = operandType (IC_RESULT (ic));
 
           if (!IS_INTEGRAL (resulttype) || bitsForType (resulttype) <= 16 ||
-            !(IS_ITEMP (left) || IS_OP_LITERAL (left)) ||
-            !(IS_ITEMP (right) || IS_OP_LITERAL (right)))
-            continue;
+              !(IS_ITEMP (left) || IS_OP_LITERAL (left)) ||
+              !(IS_ITEMP (right) || IS_OP_LITERAL (right)))
+            {
+              continue;
+            }
 
           if (IS_ITEMP (left) && bitVectnBitsOn (OP_DEFS (left)) != 1 ||
-            IS_ITEMP (right) && bitVectnBitsOn (OP_DEFS (right)) != 1)
-            continue;
+              IS_ITEMP (right) && bitVectnBitsOn (OP_DEFS (right)) != 1)
+            {
+              continue;
+            }
 
           iCode *lic = IS_ITEMP (left) ? hTabItemWithKey (iCodehTab, bitVectFirstBit (OP_DEFS (left))) : 0;
           iCode *ric = IS_ITEMP (right) ? hTabItemWithKey (iCodehTab, bitVectFirstBit (OP_DEFS (right))) : 0;
@@ -2298,7 +2378,7 @@
 
               if (litval > 0x7f)
                 continue;
-            }     
+            }
           else if (operandLitValue (left) > 0x7f)
             continue;
 
@@ -2313,7 +2393,9 @@
                 continue;
             }
           else if (operandLitValue (right) > 0x7f)
-            continue;
+            {
+              continue;
+            }
 
           // Now replace the wide multiplication by 8x8->16 multiplication and insert casts.
 
@@ -2332,7 +2414,9 @@
               addiCodeToeBBlock (ebbs[i], newic, ic);
             }
           else
-            IC_LEFT (ic) = operandFromValue (valCastLiteral (newCharLink(), operandLitValue (IC_LEFT (ic)), operandLitValue (IC_LEFT (ic))));
+            {
+              IC_LEFT (ic) = operandFromValue (valCastLiteral (newCharLink(), operandLitValue (IC_LEFT (ic)), operandLitValue (IC_LEFT (ic))));
+            }
 
           if (ric)
             {
@@ -2349,7 +2433,9 @@
               addiCodeToeBBlock (ebbs[i], newic, ic);
             }
           else
-            IC_LEFT (ic) = operandFromValue (valCastLiteral (newCharLink(), operandLitValue (IC_LEFT (ic)), operandLitValue (IC_LEFT (ic))));
+            {
+              IC_LEFT (ic) = operandFromValue (valCastLiteral (newCharLink(), operandLitValue (IC_LEFT (ic)), operandLitValue (IC_LEFT (ic))));
+            }
 
           // Insert cast on result
           nextresulttype = newIntLink();
@@ -2362,15 +2448,19 @@
     {
       for (ic = ebbs[i]->sch; ic; ic = ic->next)
         {
-          if ((ic->op == '+' || ic->op == '-' || ic->op == UNARYMINUS || ic->op == '*' || ic->op == LEFT_OP || ic->op == RIGHT_OP || ic->op == BITWISEAND || ic->op == '|' || ic->op == CAST) &&
-            IC_RESULT (ic) && IS_ITEMP (IC_RESULT (ic)))
+          if ( (ic->op == CAST || ic->op == '+' || ic->op == '-' || ic->op == UNARYMINUS || ic->op == '*' ||
+                ic->op == LEFT_OP || ic->op == RIGHT_OP || ic->op == BITWISEAND || ic->op == '|' || ic->op == '^') &&
+               IC_RESULT (ic) && IS_ITEMP (IC_RESULT (ic)) )
             {
               sym_link *resulttype = operandType (IC_RESULT (ic));
 
               if (!IS_INTEGRAL (resulttype) ||
-                ic->op != CAST && !(IS_SYMOP (IC_LEFT (ic)) || IS_OP_LITERAL (IC_LEFT (ic))) ||
-                !(IS_SYMOP (IC_RIGHT (ic)) || IS_OP_LITERAL (IC_RIGHT (ic)) || ic->op == UNARYMINUS))
-                continue;
+                  ic->op != CAST && !(IS_SYMOP (IC_LEFT (ic)) ||
+                  IS_OP_LITERAL (IC_LEFT (ic))) ||
+                  !(IS_SYMOP (IC_RIGHT (ic)) || IS_OP_LITERAL (IC_RIGHT (ic)) || ic->op == UNARYMINUS))
+                {
+                  continue;
+                }
 
               resultsize = bitsForType (resulttype);
 
@@ -2380,23 +2470,23 @@
 
               uic = hTabItemWithKey (iCodehTab, bitVectFirstBit (OP_USES (IC_RESULT (ic))));
 
-              if(!uic)
+              if (!uic)
                 continue;
 
               /* Skip over assignment */
               skipuic = NULL;
-              if(uic->op == '=' && IS_ITEMP (IC_RESULT (uic)) &&
-                bitVectnBitsOn (OP_DEFS (IC_RESULT (uic))) == 1 && bitVectnBitsOn (OP_USES (IC_RESULT (ic))) == 1 && bitVectnBitsOn (OP_USES (IC_RESULT (uic))) == 1 &&
-                compareType (operandType (IC_RESULT (ic)), operandType (IC_RESULT (uic))) == 1)
+              if (uic->op == '=' && IS_ITEMP (IC_RESULT (uic)) &&
+                  bitVectnBitsOn (OP_DEFS (IC_RESULT (uic))) == 1 && bitVectnBitsOn (OP_USES (IC_RESULT (ic))) == 1 && bitVectnBitsOn (OP_USES (IC_RESULT (uic))) == 1 &&
+                  compareType (operandType (IC_RESULT (ic)), operandType (IC_RESULT (uic))) == 1)
                 {
                   skipuic = uic;
                   uic = hTabItemWithKey (iCodehTab, bitVectFirstBit (OP_USES (IC_RESULT (uic))));
                 }
 
               /* Try to handle a few cases where the result has multiple uses */
-              else if(ic->op == '*' && bitsForType (operandType (IC_RESULT (ic))) > 16 && uic->op == '=' &&
-                bitVectnBitsOn (OP_DEFS (IC_RESULT (uic))) == 1 && bitVectnBitsOn (OP_USES (IC_RESULT (ic))) == 1 && bitVectnBitsOn (OP_USES (IC_RESULT (uic))) > 1 &&
-                compareType (operandType (IC_RESULT (ic)), operandType (IC_RESULT (uic))) == 1)
+              else if (ic->op == '*' && bitsForType (operandType (IC_RESULT (ic))) > 16 && uic->op == '=' &&
+                       bitVectnBitsOn (OP_DEFS (IC_RESULT (uic))) == 1 && bitVectnBitsOn (OP_USES (IC_RESULT (ic))) == 1 && bitVectnBitsOn (OP_USES (IC_RESULT (uic))) > 1 &&
+                       compareType (operandType (IC_RESULT (ic)), operandType (IC_RESULT (uic))) == 1)
                 {
                   bool ok = true;
                   const bitVect *uses;
@@ -2454,7 +2544,7 @@
                 {
                    /* Since shifting by the width of an operand or more is undefined behaviour, and no type is wider than 256 bits,
                       we can optimize when the result is used as right operand to a shift. */
-                   if(!isOperandEqual (IC_RESULT (ic), IC_RIGHT (uic)) || isOperandEqual (IC_RESULT (ic), IC_LEFT (uic)))
+                   if (!isOperandEqual (IC_RESULT (ic), IC_RIGHT (uic)) || isOperandEqual (IC_RESULT (ic), IC_LEFT (uic)))
                      continue;
 
                    nextresulttype = newCharLink ();
@@ -2471,7 +2561,9 @@
                       SPEC_USIGN (nextresulttype) = 1;
                     }
                   else
-                    nextresulttype = copyLinkChain (nextresulttype);
+                    {
+                      nextresulttype = copyLinkChain (nextresulttype);
+                    }
                 }
 
               nextresultsize = bitsForType (nextresulttype);
@@ -2489,12 +2581,17 @@
               /* Insert casts on operands */
               if (ic->op != CAST)
                 {
+                  sym_link *clefttype = copyLinkChain (nextresulttype);
+                  SPEC_VOLATILE (clefttype) = IS_OP_VOLATILE (IC_LEFT (ic));
+                  sym_link *crighttype = copyLinkChain (nextresulttype);
+                  SPEC_VOLATILE (crighttype) = IS_OP_VOLATILE (IC_RIGHT (ic));
+
                   if (IS_SYMOP (IC_LEFT (ic)))
                     {
-                      newic = newiCode (CAST, operandFromLink (nextresulttype), IC_LEFT (ic));
+                      newic = newiCode (CAST, operandFromLink (clefttype), IC_LEFT (ic));
                       hTabAddItem (&iCodehTab, newic->key, newic);
                       bitVectSetBit (OP_USES (IC_LEFT (ic)), newic->key);
-                      IC_RESULT (newic) = newiTempOperand (nextresulttype, 0);
+                      IC_RESULT (newic) = newiTempOperand (clefttype, 0);
                       OP_DEFS (IC_RESULT (newic)) = bitVectSetBit (OP_DEFS (IC_RESULT (newic)), newic->key);
                       bitVectUnSetBit (OP_USES (IC_LEFT (ic)), ic->key);
                       IC_LEFT (ic) = operandFromOperand (IC_RESULT (newic));
@@ -2506,14 +2603,14 @@
                   else
                     {
                       wassert (IS_OP_LITERAL (IC_LEFT (ic)));
-                      IC_LEFT (ic) = operandFromValue (valCastLiteral (nextresulttype, operandLitValue (IC_LEFT (ic)), operandLitValue (IC_LEFT (ic))));
+                      IC_LEFT (ic) = operandFromValue (valCastLiteral (clefttype, operandLitValue (IC_LEFT (ic)), operandLitValue (IC_LEFT (ic))));
                     }
                   if (ic->op != LEFT_OP && IS_SYMOP (IC_RIGHT (ic)))
                     {
-                      newic = newiCode (CAST, operandFromLink (nextresulttype), IC_RIGHT (ic));
+                      newic = newiCode (CAST, operandFromLink (crighttype), IC_RIGHT (ic));
                       hTabAddItem (&iCodehTab, newic->key, newic);
                       bitVectSetBit (OP_USES (IC_RIGHT (ic)), newic->key);
-                      IC_RESULT (newic) = newiTempOperand (nextresulttype, 0);
+                      IC_RESULT (newic) = newiTempOperand (crighttype, 0);
                       OP_DEFS (IC_RESULT (newic)) = bitVectSetBit (OP_DEFS (IC_RESULT (newic)), newic->key);
                       bitVectUnSetBit (OP_USES (IC_RIGHT (ic)), ic->key);
                       IC_RIGHT (ic) = operandFromOperand (IC_RESULT (newic));
@@ -2525,7 +2622,7 @@
                   else if (ic->op != LEFT_OP && ic->op != UNARYMINUS)
                     {
                       wassert (IS_OP_LITERAL (IC_RIGHT (ic)));
-                      IC_RIGHT (ic) = operandFromValue (valCastLiteral (nextresulttype, operandLitValue (IC_RIGHT (ic)), operandLitValue (IC_RIGHT (ic))));
+                      IC_RIGHT (ic) = operandFromValue (valCastLiteral (crighttype, operandLitValue (IC_RIGHT (ic)), operandLitValue (IC_RIGHT (ic))));
                     }
                 }
               if (uic->op == CAST && ic->op != RIGHT_OP)
@@ -2538,6 +2635,16 @@
                       OP_USES (IC_RIGHT (uic)) = bitVectSetBit (OP_USES (IC_RIGHT (uic)), uic->key);
                     }
                 }
+              if (skipuic && skipuic->op == '=' &&
+                  compareType (operandType (IC_RESULT (skipuic)), operandType (IC_RIGHT (skipuic))) != 1)
+                {
+                  /* Because of the type change, this assignment  */
+                  /* is now really a cast, so make it official.   */
+                  /* Later optimizeCastCast() will decide if this */
+                  /* is safe to remove completely. */
+                  skipuic->op = CAST;
+                  IC_LEFT (skipuic) = operandFromLink (copyLinkChain (operandType (IC_RESULT (skipuic))));
+                }
               change++;
             }
         }
@@ -2635,7 +2742,7 @@
           if (IC_RESULT (nic) && (!IS_ITEMP (IC_RESULT (nic)) || bitVectnBitsOn (OP_USES (IC_RESULT (nic)))))
             continue;
 
-          // Chek that their parameters are string literals
+          // Check that their parameters are string literals
           strsym = findStrLitDef (IC_LEFT (ic->prev), 0);
           nstrsym = findStrLitDef (IC_LEFT (nic->prev), &ndic);
           if (!strsym || !nstrsym)
@@ -2665,7 +2772,7 @@
           dbuf_destroy (&dbuf);
 
           // Make second call print the combined string (which allows further optimization with subsequent calls)
-          IC_LEFT (ndic)->key = cstrsym->key;
+          IC_LEFT (ndic)->key = cstrsym->key = ++operandKey;
           IC_LEFT (ndic)->svt.symOperand = cstrsym;
 
           // Change unused call to assignments to self to mark it for dead-code elimination.
@@ -2844,7 +2951,7 @@
 
   if (!TARGET_Z80_LIKE && !TARGET_IS_STM8)
     return;
-  
+
   for (i = 0; i < count; i++)
     {
       for (ic = ebbs[i]->sch; ic; ic = ic->next)
@@ -2894,9 +3001,9 @@
   iCode *ic;
   iCode *uic;
 
-  if (!TARGET_IS_Z80 && !TARGET_IS_Z180 && !TARGET_IS_RABBIT && !TARGET_IS_STM8)
+  if (!(TARGET_Z80_LIKE && !TARGET_IS_SM83) && !TARGET_IS_STM8) // All z80-related targets except sm83 support non-zero right operand. stm8 also supports it.
     return;
-  
+
   for (i = 0; i < count; i++)
     {
       for (ic = ebbs[i]->sch; ic; ic = ic->next)
@@ -3100,7 +3207,7 @@
 
   /* compute the control flow */
   computeControlFlow (ebbi);
- 
+
   /* dumpraw if asked for */
   if (options.dump_i_code)
     dumpEbbsToFileExt (DUMP_RAW0, ebbi);
@@ -3199,7 +3306,7 @@
   computeControlFlow (ebbi);
   loops = createLoopRegions (ebbi);
   computeDataFlow (ebbi);
-  computeLiveRanges (ebbi->bbOrder, ebbi->count, FALSE);
+  computeLiveRanges (ebbi->bbOrder, ebbi->count, TRUE);
   while (optimizeOpWidth (ebbi->bbOrder, ebbi->count))
     optimizeCastCast (ebbi->bbOrder, ebbi->count);
   adjustIChain (ebbi->bbOrder, ebbi->count);
@@ -3212,7 +3319,7 @@
       if (options.dump_i_code)
         dumpEbbsToFileExt (DUMP_LOSPRE, ebbi);
 
-      /* GCSE, lospre and maybe other optimizations sometimes create temporaries that have non-connected live ranges, which is bad. Split them. */
+      /* GCSE, lospre and maybe other optimizations sometimes create temporaries that have non-connected live ranges, which is bad (e.g. for offsetFoldUse and register allocation). Split them. */
       freeeBBlockData (ebbi);
       ebbi = iCodeBreakDown (ic);
       computeControlFlow (ebbi);
diff -Nru sdcc-4.0.0+dfsg/src/SDCCpeeph.c sdcc-4.2.0+dfsg/src/SDCCpeeph.c
--- sdcc-4.0.0+dfsg/src/SDCCpeeph.c	2019-06-10 18:09:35.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/SDCCpeeph.c	2022-02-10 06:43:16.000000000 +0000
@@ -132,15 +132,6 @@
 }
 
 /*-----------------------------------------------------------------*/
-/* portIsDS390 - return true if port is DS390                      */
-/*-----------------------------------------------------------------*/
-FBYNAME (portIsDS390)
-{
-    return ((strcmp(port->target,"ds390") == 0) ||
-            (strcmp(port->target,"ds400") == 0));
-}
-
-/*-----------------------------------------------------------------*/
 /* flat24bitMode - will check to see if we are in flat24 mode      */
 /*-----------------------------------------------------------------*/
 FBYNAME (flat24bitMode)
@@ -322,10 +313,19 @@
     ;
 
   retInst = "ret";
-  if (TARGET_HC08_LIKE)
+  if (TARGET_HC08_LIKE || TARGET_MOS6502_LIKE)
     retInst = "rts";
-  if (strcmp(p, retInst) == 0)
+
+  if (strncmp(p, retInst,strlen(retInst)) != 0)
+    return FALSE;
+
+  p+=strlen(retInst);
+  while(*p && ISCHARSPACE(*p))
+    p++;
+
+  if(*p==0 || *p==';')
     return TRUE;
+
   return FALSE;
 }
 
@@ -353,9 +353,9 @@
     {
       if (pl->line && !pl->isDebug && !pl->isComment && pl->isLabel)
         {
-          if (strncmp(pl->line, label, len) == 0)
+          if (strncmp(pl->line, label, len) == 0 && pl->line[len] == ':')
             {
-              found = TRUE;
+              found = true;
               break; /* Found Label */
             }
           if (strlen(pl->line) != 7       || !ISCHARDIGIT(*(pl->line))   ||
@@ -374,9 +374,9 @@
         {
           if (pl->line && !pl->isDebug && !pl->isComment && pl->isLabel)
             {
-              if (strncmp(pl->line, label, len) == 0)
+              if (strncmp(pl->line, label, len) == 0 && pl->line[len] == ':')
                 {
-                  found = TRUE;
+                  found = true;
                   break; /* Found Label */
                 }
               if (strlen(pl->line) != 7       || !ISCHARDIGIT(*(pl->line))   ||
@@ -406,7 +406,7 @@
       jpInst = "ljmp";
       jpInst2 = "sjmp";
     }
-  else if (TARGET_HC08_LIKE)
+  else if (TARGET_HC08_LIKE || TARGET_MOS6502_LIKE)
     {
       jpInst = "jmp";
       jpInst2 = "bra";
@@ -666,6 +666,70 @@
   return rc;
 }
 
+/* newLabel creates new dollar-label and returns it in the specified container.
+ * Optional second operand may specify initial reference count, by default 1.
+ * return TRUE if no errors detected
+ */
+FBYNAME (newLabel)
+{
+  int varNumber;
+  unsigned refCount;
+  switch (sscanf (cmdLine, " %%%d %u", &varNumber, &refCount))
+    {
+    case 1:
+      refCount = 1;
+      break;
+    case 2:
+      break;
+    default:
+      fprintf (stderr,
+               "*** internal error: newLabel peephole restriction"
+               " malformed: %s\n", cmdLine);
+      return FALSE;
+    }
+
+  if (varNumber <= 0)
+    {
+      fprintf (stderr, "*** internal error: invalid container %%%d"
+               " in peephole %s rule.\n",
+               varNumber, __func__);
+      return FALSE;
+    }
+
+  if (labelHash == NULL)
+    buildLabelRefCountHash (head);
+
+  labelHashEntry *entry;
+  int key;
+  unsigned maxLabel = 100; // do not use labels below than 00100$
+  for (entry = hTabFirstItem (labelHash, &key); entry;
+       entry = hTabNextItem (labelHash, &key))
+    {
+      const char *name = entry->name;
+      wassert (name);
+      if (!ISCHARDIGIT (name[0]))
+        continue;
+      if (name[strlen (name)-1] != '$')
+        continue;
+      unsigned n;
+      if (sscanf (name, "%u$", &n) != 1)
+        continue;
+      if (maxLabel < n)
+        maxLabel = n;
+    }
+  ++maxLabel;
+  entry = traceAlloc (&_G.labels, Safe_alloc (sizeof (*entry)));
+  int len = snprintf (entry->name, SDCC_NAME_MAX, "%05u$", maxLabel);
+  entry->name[len] = 0;
+  entry->refCount = refCount;
+  hTabAddItem (&labelHash, hashSymbolName (entry->name), entry);
+
+  char *value = traceAlloc (&_G.values, Safe_strdup(entry->name));
+  hTabAddItem (&vars, varNumber, value);
+
+  return TRUE;
+}
+
 /* Within the context of the lines currPl through endPl, determine
 ** if the variable var contains a symbol that is volatile. Returns
 ** TRUE only if it is certain that this was not volatile (the symbol
@@ -703,12 +767,16 @@
         return global_not_volatile;
       if (strstr (var, "(de)"))
         return global_not_volatile;
-      if (strstr (var, "(hl)"))
+      if (strstr (var, "(hl"))
         return global_not_volatile;
       if (strstr (var, "(ix"))
         return global_not_volatile;
       if (strstr (var, "(iy"))
         return global_not_volatile;
+      // sm83-specific ldh can be volatile
+      // but HRAM doesn't have to be volatile
+      if (TARGET_ID_SM83 && strstr (var, "(c)"))
+        return global_not_volatile;
     }
 
   if (TARGET_IS_STM8)
@@ -1013,25 +1081,92 @@
   return op;
 }
 
-/*-----------------------------------------------------------------*/
-/* notUsed - Check, if value in register is not read again         */
-/*-----------------------------------------------------------------*/
-FBYNAME (notUsed)
+/*------------------------------------------------------------------*/
+/* optimizeFor - check optimization conditions                      */
+/* valid parameters:                                                */
+/*  code-size  -> checks for optimize.codeSize > 0                  */
+/*  code-speed -> checks for optimize.codeSpeed > 0                 */
+/*  add the ! symbol before each parameter to negate the condition  */
+/* combinations with multiple parameters                            */
+/*  '!code-speed' '!code-size': apply for balanced opt.             */
+/*  '!code-size': apply for balanced and when optimizing for speed  */
+/*  '!code-speed': apply unless optimizing for code speed           */
+/*------------------------------------------------------------------*/
+FBYNAME (optimizeFor)
 {
-  const char *what;
-  bool ret;
+  const char *cond;
+  int speed = 0, size = 0; // 0: nothing requested, >0 optimization requested, <0 negated optimization requested
+  
+  bool ret = false, error = false;
 
   set *operands = setFromConditionArgs (cmdLine, vars);
 
-  if (!operands || elementsInSet(operands) != 1)
+  if (!operands)
   {
     fprintf (stderr,
-             "*** internal error: notUsed peephole restriction"
-             " malformed: %s\n", cmdLine);
-    return FALSE;
+             "*** internal error: optimizeFor peephole restriction"
+             " requires operand(s): %s\n", cmdLine);
+    return false;
   }
 
-  what = setFirstItem (operands);
+  // Loop through all conditions to check requested optimizations
+  for (cond = setFirstItem (operands); !error && cond != NULL; cond = setNextItem (operands))
+    {
+      const char *condTextSpeed = strstr (cond, "code-speed");
+      const char *condTextSize  = strstr (cond, "code-size");
+      const char *condNegated = strstr (cond, "!");
+      const char *condText = condTextSpeed ? condTextSpeed : condTextSize;
+      
+      // Check for invalid conditions or invalid combinations in the same string
+      if (!condText || condTextSpeed && condTextSize || condNegated && (condNegated + 1 != condText))
+        {
+          error = true;
+          break;
+        }
+      if (condTextSize)
+        {
+          if (size == 0)
+            size = condNegated ? -1 : 1;
+          else
+            error = true;
+        }
+      else
+        {
+          if (speed == 0)
+            speed = condNegated ? -1 : 1;
+          else
+            error = true;
+        }
+    }
+  // check error, invalid combination of both speed and size or nothing
+  if (error || (speed != -1) && (speed == size) )
+    {
+      fprintf (stderr,
+             "*** internal error: optimizeFor peephole restriction"
+             " malformed: %s\n", cmdLine);
+      error = true;
+    }
+  else
+    { // Check conditions and generate return value
+      ret = true;
+      if (speed != 0)
+        ret &= (speed < 0) ^ (optimize.codeSpeed > 0);
+        
+      if (size != 0)
+        ret &= (size < 0) ^ (optimize.codeSize > 0);
+    }
+    
+  deleteSet(&operands);
+  return (ret);
+}
+
+/*-----------------------------------------------------------------*/
+/* notUsed - Check, if values in all registers are not read again  */
+/*-----------------------------------------------------------------*/
+FBYNAME (notUsed)
+{
+  const char *what;
+  bool ret;
 
   if (!port->peep.notUsed)
     {
@@ -1039,7 +1174,19 @@
       return FALSE;
     }
 
-  ret = port->peep.notUsed (what, endPl, head);
+  set *operands = setFromConditionArgs (cmdLine, vars);
+
+  if (!operands)
+    {
+      fprintf (stderr,
+             "*** internal error: notUsed peephole restriction"
+             " requires operand(s): %s\n", cmdLine);
+      return FALSE;
+    }
+
+  what = setFirstItem (operands);
+  for (ret = TRUE; ret && what != NULL; what = setNextItem (operands))
+    ret = port->peep.notUsed (what, endPl, head);
 
   deleteSet(&operands);
 
@@ -1047,30 +1194,93 @@
 }
 
 /*-----------------------------------------------------------------*/
-/* notUsed - Check, if value in register is not read again         */
+/* notUsedFrom - Check, if values in registers are not read again  */
 /*           starting from label                                   */
+/*           Registers are checked from left to right              */
 /*-----------------------------------------------------------------*/
 FBYNAME (notUsedFrom)
 {
   const char *what, *label;
+  bool ret;
+  
+  if (!port->peep.notUsedFrom)
+    {
+      fprintf (stderr, "Function notUsedFrom not initialized in port structure\n");
+      return false;
+    }
+  
   set *operands = setFromConditionArgs (cmdLine, vars);
 
-  if (!operands || elementsInSet(operands) != 2)
+  if (!operands)
+  {
+    fprintf (stderr,
+             "*** internal error: notUsedFrom peephole restriction"
+             " requires operand(s): %s\n", cmdLine);
+    return false;
+  }
+  if (elementsInSet(operands) < 2)
   {
     fprintf (stderr,
              "*** internal error: notUsedFrom peephole restriction"
              " malformed: %s\n", cmdLine);
-    return FALSE;
+    deleteSet(&operands);
+    return false;
   }
 
-  what = setFirstItem (operands);
-  label = setNextItem (operands); 
+  operands = reverseSet(operands);
 
-  if (port->peep.notUsedFrom)
-    return port->peep.notUsedFrom (what, label, head);
+  label = setFirstItem (operands);
+  what = setNextItem (operands);
 
-  fprintf (stderr, "Function notUsed not initialized in port structure\n");
-  return FALSE;
+  for (ret = true; ret && what; what = setNextItem (operands))
+      ret = port->peep.notUsedFrom (what, label, head);
+  
+  deleteSet(&operands);
+
+  return (ret);
+}
+
+/*-----------------------------------------------------------------*/
+/* unusedReg - find first unused register from specified list and  */
+/* assign to container specified as first argument. Fails if all   */
+/* of specified registers are accessed for reading.                */
+/*-----------------------------------------------------------------*/
+FBYNAME (unusedReg)
+{
+  int dst;
+  int n;
+  if (sscanf (cmdLine, " %%%d%n", &dst, &n) != 1 || dst <= 0)
+    {
+      fprintf (stderr,
+               "*** internal error: unusedReg peephole restriction"
+               " malformed: %s\n", cmdLine);
+      return FALSE;
+    }
+
+  set *operands = setFromConditionArgs (&cmdLine[n], vars);
+  if (!operands || elementsInSet (operands) < 2 || elementsInSet (operands) > 3)
+    {
+      fprintf (stderr,
+               "*** internal error: unusedReg peephole restriction"
+               " malformed: %s\n", cmdLine);
+      return FALSE;
+    }
+
+  char *what = setFirstItem (operands);
+  for (; what != NULL; what = setNextItem (operands))
+    if (port->peep.notUsed (what, endPl, head))
+      break;
+
+  bool ret = (what != NULL);
+  if (ret)
+    {
+      char *s[] = {what, NULL};
+      bindVar (dst, s, &vars);
+    }
+
+  deleteSet (&operands);
+
+  return ret;
 }
 
 /*-----------------------------------------------------------------*/
@@ -1105,7 +1315,7 @@
     }
 
   if (port->peep.canAssign)
-    {  
+    {
       bool ret = port->peep.canAssign (dst, src, exotic);
       deleteSet (&operands);
       return (ret);
@@ -1118,6 +1328,209 @@
 }
 
 /*-----------------------------------------------------------------*/
+/* canJoinRegs - joins set of registers to combined one, returns   */
+/* true, if result register is valid. First operand can be         */
+/* 'unordered' if order of registers is not sufficient. Last       */
+/* operand should be wildcard. If result is not required, then     */
+/* wildcard should be %0. If some of source registers is not       */
+/* sufficient then empty string can be passed.                     */
+/*-----------------------------------------------------------------*/
+FBYNAME (canJoinRegs)
+{
+  // Must be specified at least 3 parameters: reg_hi reg_lo and dst
+  // If destination is not required, then %0 should be specified
+  if (!port->peep.canJoinRegs)
+    {
+      fprintf (stderr, "Function canJoinRegs not supported by the port\n");
+      return FALSE;
+    }
+
+  int dstKey;
+  int i;
+  for (i = strlen (cmdLine)-1; i >= 0 && ISCHARSPACE (cmdLine[i]); --i)
+    ;
+  for (; i >= 0 && !ISCHARSPACE (cmdLine[i]); --i)
+    ;
+  if (i < 0 || cmdLine[i+1] != '%' || (cmdLine[i+1] && (sscanf (&cmdLine[i+2], "%d", &dstKey) != 1 || dstKey < 0)))
+    {
+      fprintf (stderr,
+           "*** internal error: canJoinRegs peephole restriction"
+           " has bad result container: %s\n", &cmdLine[i+1]);
+      return FALSE;
+    }
+  //parse cmd line without last operand
+  cmdLine[i] = '\0';
+  set *operands = setFromConditionArgs (cmdLine, vars);
+  cmdLine[i] = ' ';
+
+  if (operands == NULL)
+    {
+      fprintf (stderr,
+               "*** internal error: canJoinRegs peephole restriction"
+               " malformed: %s\n", cmdLine);
+      return FALSE;
+    }
+
+  bool unordered = false;
+  const char *first = setFirstItem (operands);
+  if (first && !strcmp (first, "unordered"))
+    {
+      unordered = true;
+      deleteSetItem (&operands, (void*)first);
+    }
+
+  int size = elementsInSet (operands);
+  if (size < 2)
+    {
+      fprintf (stderr,
+               "*** internal error: canJoinRegs peephole restriction"
+               " requires at least 3 operands: %s\n", cmdLine);
+      return FALSE;
+    }
+
+  const char **regs = (const char**) Safe_alloc ( (size + 1) * sizeof (*regs));
+  i = size;
+  regs[size] = NULL; /* end of registers */
+  //fill regs reversing order (operands have reversed order)
+  for (set *it = operands; it; it = it->next)
+    regs[--i] = (const char*)it->item;
+
+  //if unordered specified, then sort elements by ascending order
+  if (unordered)
+    qsort (regs, size, sizeof (*regs), (int (*)(const void*,const void*))&strcmp);
+
+  char dst[20];
+  bool result;
+  for (;;)
+    {
+      result = port->peep.canJoinRegs (regs, dst);
+      if (result || !unordered)
+        break;
+
+      //do next registers permutation
+      int i;
+      //find last regs[i] < regs[i+1]
+      for (i = size-2; i >= 0; --i)
+        if (strcmp (regs[i+1], regs[i]) > 0)
+          break;
+      if (i < 0)
+        break; /* was last permutation */
+
+      int j;
+      //find last regs[j] > regs[i], where j > i
+      for (j = size-1; j > i; --j)
+        if (strcmp (regs[j], regs[i]) > 0)
+          break;
+
+      //swap regs[j] and regs[i]
+      const char *t = regs[i];
+      regs[i] = regs[j];
+      regs[j] = t;
+      //reverse order from j+1 to end
+      for (j = j+1, i = size - 1; j < i; ++j, --i)
+        {
+          t = regs[j];
+          regs[j] = regs[i];
+          regs[i] = t;
+        }
+    }
+
+  Safe_free (regs);
+
+  if (result && dstKey > 0)
+    {
+      char *s[] = { dst, NULL };
+      bindVar (dstKey, s, &vars);
+    }
+
+  deleteSet (&operands);
+  return result;
+}
+
+/*-----------------------------------------------------------------*/
+/* canSplitReg - returns true, if register can be splitted. First  */
+/* operand contains complex register name and is required. Other   */
+/* operands should be wildcards. If result is not sufficient then  */
+/* they can be omited.                                             */
+/*-----------------------------------------------------------------*/
+FBYNAME (canSplitReg)
+{
+  if (!port->peep.canSplitReg)
+    {
+      fprintf (stderr, "Function canSplitReg not supported by the port\n");
+      return FALSE;
+    }
+
+  int i;
+  //find start of first operand
+  for (i = 0; cmdLine[i] && ISCHARSPACE (cmdLine[i]); ++i)
+    ;
+  if (cmdLine[i] == '\0')
+    {
+      fprintf (stderr,
+               "*** internal error: canSplitReg peephole restriction"
+               " malformed: %s\n", cmdLine);
+      return FALSE;
+    }
+
+  //find end of first operand
+  for (; cmdLine[i] && !ISCHARSPACE (cmdLine[i]); ++i)
+    ;
+
+  //parse first operand
+  char t = cmdLine[i];
+  cmdLine[i] = '\0';
+  set *operands = setFromConditionArgs (cmdLine, vars);
+  cmdLine[i] = t;
+  if (cmdLine[i] == '\0')
+    {
+      fprintf (stderr,
+               "*** internal error: canSplitReg peephole restriction"
+               " malformed: %s\n", cmdLine);
+      return FALSE;
+    }
+
+  //scan remaining operands
+  int size = 2;
+  int *varIds = (int*)Safe_alloc (size * sizeof(*varIds));
+  const char *cl = &cmdLine[i+1];
+  for (i = 0;; ++i)
+    {
+      if (i >= size)
+        {
+          size *= 2;
+          varIds = (int*)Safe_realloc (varIds, size * sizeof(*varIds));
+        }
+      int len;
+      if (sscanf (cl, " %%%d%n", &varIds[i], &len) != 1)
+        break;
+      if (varIds[i] < 0)
+        {
+          fprintf (stderr,
+                   "*** internal error: canSplitReg peephole restriction"
+                   " has invalid destination container: %s\n", cmdLine);
+          return FALSE;
+        }
+      cl += len;
+    }
+  size = i;
+  char (*dst)[16];
+  dst = Safe_alloc (size * sizeof (*dst));
+  bool ret = port->peep.canSplitReg ((char*)setFirstItem (operands), dst, size);
+  for (i = 0; ret && i < size; ++i)
+    {
+      if (varIds[i] <= 0)
+        continue;
+      char *s[] = { dst[i], NULL };
+      bindVar (varIds[i], s, &vars);
+    }
+  Safe_free (dst);
+  Safe_free (varIds);
+  deleteSet (&operands);
+  return ret;
+}
+
+/*-----------------------------------------------------------------*/
 /* operandsNotRelated - returns true if the condition's operands   */
 /* are not related (taking into account register name aliases).    */
 /* N-way comparison performed between all operands.                */
@@ -1181,7 +1594,7 @@
 
       for (op2 = setFirstItem (operands); op2; op2 = setNextItem (operands))
         {
-          if ((strstr (op1, op2) || strstr (op2, op1)) && strcmp (op1, op2) == 0)
+          if (strstr (op1, op2) || strstr (op2, op1))
             {
               deleteSet (&operands);
               return FALSE;
@@ -1199,9 +1612,25 @@
 /*-----------------------------------------------------------------*/
 FBYNAME (symmParmStack)
 {
+  set *operands = setFromConditionArgs (cmdLine, vars);
+
+  if (!operands)
+  {
+    fprintf (stderr,
+             "*** internal error: symmParmStack peephole restriction"
+             " requires operand: %s\n", cmdLine);
+    return FALSE;
+  }
+
+  const char *name = setFirstItem (operands);
+
+  bool ret = false;
+
   if (port->peep.symmParmStack)
-    return port->peep.symmParmStack();
-  return FALSE;
+    return port->peep.symmParmStack (name);
+  deleteSet(&operands);
+
+  return ret;
 }
 
 /*-----------------------------------------------------------------*/
@@ -1275,11 +1704,126 @@
 }
 
 /*-----------------------------------------------------------------*/
+/* strIsSymbol - returns true if the parameter is a symbol         */
+/* That is: an underscore followed by one or more chars            */
+/*-----------------------------------------------------------------*/
+static bool
+strIsSymbol(const char *str)
+{
+  return *str == '_' && str[1] != '\0';
+}
+
+/*-----------------------------------------------------------------*/
+/* strIsLiteral - returns true if the parameter is a literal       */
+/* Checks these formats: binary, octal, decimal, hexadecimal       */
+/* Skips preceding signs.                                          */
+/*-----------------------------------------------------------------*/
+static bool
+strIsLiteral(const char *str)
+{
+  const char digits[] = {'0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'a', 'b', 'c', 'd', 'e', 'f'}; 
+  unsigned char base = 10;
+  unsigned char validDigits = 0;
+  
+  // has to start with a number or a sign
+  if(!isdigit( (unsigned char)(*str) ) && (*str) != '-' && (*str) != '+')
+    return false;
+  // skip sign
+  if ((*str) == '-' || (*str) == '+')
+    str++;
+
+  // handle 0b 0o 0d 0x
+  if((*str) == '0')
+    {
+      const char nextChar = tolower((unsigned char)(str[1]));
+      validDigits = 0;
+      if (nextChar == 'b')
+        {
+          base = 2;
+          ++str;
+        }
+      else if(nextChar == 'o')
+        {
+          base = 8;
+          ++str;
+        }
+      else if(nextChar == 'd')
+        {
+          base = 10;
+          ++str;
+        }
+      else if(nextChar == 'x')
+        {
+          base = 16;
+          ++str;
+        }
+      else
+        validDigits = 1; // the first '0' is a valid digit
+      
+      ++str;
+    }
+  
+  while((unsigned char)(*str) != '\0'){
+    unsigned char i;
+    for(i = 0; i < base; ++i){
+      if(tolower((unsigned char)(*str)) == digits[i])
+        break;
+    }
+    // number was too big or not valid
+    if(i >= base)
+      return false;
+    ++validDigits;
+    ++str;
+  }
+  return validDigits > 0;
+}
+
+/*-----------------------------------------------------------------*/
 /* operandsLiteral - returns true if the condition's operands are  */
 /* literals.                                                       */
 /*-----------------------------------------------------------------*/
 FBYNAME (operandsLiteral)
 {
+  set *operands = setFromConditionArgs (cmdLine, vars);
+  const char *op;
+
+  if (!operands)
+    {
+      fprintf (stderr,
+               "*** internal error: operandsLiteral peephole restriction"
+               " malformed: %s\n", cmdLine);
+      return FALSE;
+    }
+
+  for (op = setFirstItem (operands); op; op = setNextItem (operands))
+    {
+      if (!strIsLiteral(op))
+        {
+          deleteSet (&operands);
+          return false;
+        }
+    }
+
+  deleteSet (&operands);
+  return true;
+}
+
+/*-----------------------------------------------------------------*/
+/* strIsLiteralOrSymbol - returns true if the parameter is a       */
+/* literal or compiler symbol                                      */
+/*-----------------------------------------------------------------*/
+static bool
+strIsLiteralOrSymbol(const char *str)
+{
+  return strIsSymbol(str) || strIsLiteral(str);
+}
+
+/*-----------------------------------------------------------------*/
+/* operandsLitOrSym - returns true if the condition's operands are */
+/* literals or compiler symbols.                                   */
+/*-----------------------------------------------------------------*/
+FBYNAME (operandsLitOrSym)
+{
   set *operands;
   const char *op;
 
@@ -1288,22 +1832,113 @@
   if (!operands)
     {
       fprintf (stderr,
-               "*** internal error: operandsLiteral peephole restriction"
+               "*** internal error: operandsLitOrSym peephole restriction"
                " malformed: %s\n", cmdLine);
-      return FALSE;
+      return false;
     }
 
   for (op = setFirstItem (operands); op; op = setNextItem (operands))
     {
-      if (!isdigit( (unsigned char)(*op) ))
+      if (!strIsLiteralOrSymbol(op))
         {
           deleteSet (&operands);
-          return FALSE;
+          return false;
         }
     }
 
   deleteSet (&operands);
-  return TRUE;
+  return true;
+}
+
+/*-----------------------------------------------------------------*/
+/* removeParentheses                                               */
+/* First operand: parameter to be parsed                           */
+/* Second operand: result of conversion                            */
+/* The function removes the input parameter parentheses if present,*/
+/* else it copies the input directly to the output.                */
+/* returns true if the input has not parentheses.                  */
+/* returns true if it has parametheses at first and last chars     */
+/*              and there was no other error                       */
+/*-----------------------------------------------------------------*/
+FBYNAME (removeParentheses)
+{
+  int dstKey;
+  int i;
+  
+  // Find space previous to last operand
+  for (i = strlen (cmdLine)-1; i >= 0 && ISCHARSPACE (cmdLine[i]); --i)
+    ;
+  for (; i >= 0 && !ISCHARSPACE (cmdLine[i]); --i)
+    ;
+  if (i < 0 || cmdLine[i+1] != '%' || (cmdLine[i+1] && (sscanf (&cmdLine[i+2], "%d", &dstKey) != 1 || dstKey < 0)))
+    {
+      fprintf (stderr,
+           "*** internal error: removeParentheses peephole restriction"
+           " has bad result container: %s\n", &cmdLine[i+1]);
+      return false;
+    }
+  //Parse cmd line without last operand
+  cmdLine[i] = '\0';
+  set *operands = setFromConditionArgs (cmdLine, vars);
+  cmdLine[i] = ' '; // Restore space
+    
+  if (!operands || elementsInSet(operands) > 1)
+    {
+      fprintf (stderr,
+               "*** internal error: removeParentheses peephole restriction"
+               " malformed: %s\n", cmdLine);
+      return false;
+    }
+  
+  // Parse the operand and remove the parenthesis
+  char r[128];  
+  const char *op = setFirstItem (operands);
+  
+  if (*op == '(')
+  {
+    if(op[strlen(op)-1] == ')')
+      op++; // Skip start parenthesis
+    else
+      {
+        // Abort if no matching closing parenthesis
+        deleteSet (&operands);
+        return false;
+      }
+  }
+  if (strlen(op) > 127) // Abort if string does not fit in buffer
+    {
+      deleteSet (&operands);
+      return false;
+    }
+  
+  // Do the copy and skip ending parenthesis
+  i = 0;
+  while (*op)
+  {
+    if (*op != ')')
+      {
+        r[i++] = *op++;
+      }
+    else
+      {
+        op++;
+        break;
+      }
+  }
+  r[i] = '\0';
+  
+  // Abort if remaining chars in source or no chars copied into result string
+  if ((*op) || (i == 0))
+    {
+      deleteSet (&operands);
+      return false;
+    }
+     
+  char *p[] = {r, NULL};  
+  bindVar (dstKey, p, &vars);
+
+  deleteSet (&operands);
+  return true;
 }
 
 static long *
@@ -1349,16 +1984,114 @@
 }
 
 /*-----------------------------------------------------------------*/
-/* immdInRange - returns true if the sum or difference of two      */
-/* immediates is in a give range.                                  */
+/* isPowerOfTwo - true if n is a power of 2                        */
+/*-----------------------------------------------------------------*/
+static bool
+isPowerOfTwo(unsigned long n)
+{  
+  return (n != 0) && ((n & (n - 1)) == 0);
+}  
+
+/*-----------------------------------------------------------------*/
+/* findBitPosition - Returns the bit position set or cleared in n  */
+/* Parameters:                                                     */
+/*  n: value to be tested.                                         */
+/*  bits: number of positions to test.                             */
+/*  complement: when true, the number must be bitwise complemented */
+/* Returns:                                                        */
+/*  -2 if bits is out of valid range (1..32)                       */
+/*  -1 if n has more than one bit set or cleared                   */
+/*  -1 if n has bits in positions over the bits param              */
+/*  bit position (starting at 0) when only 1 bit set or clear      */
+/* Examples:                                                       */
+/*  n=0x02, bits=8, complemented=false -> 1                        */
+/*  n=0x7F, bits=8, complemented=true  -> 7                        */
+/*-----------------------------------------------------------------*/
+static int
+findBitPosition(unsigned long n, unsigned long bits, bool complement)
+{
+  unsigned long mask;
+  int bitPos;
+  
+  if ((bits < 1) || (bits > 32)) //bits out of range?
+    return -2;
+  mask = (1ULL << bits) -1;
+  if (n != (n & mask)) // bits outside mask?
+    return -1;
+  
+  if (complement)
+    n = (~n) & mask;
+  if (!isPowerOfTwo (n)) // Not valid if more than one bit is set
+    return -1;
+  
+  bitPos = -1;
+  // One by one move the only set bit to right till it reaches end  
+  while (n)
+    {  
+      n >>= 1;
+      bitPos++; //count number of shifts
+    }
+  
+  return bitPos;
+}
+
+/*-----------------------------------------------------------------*/
+/* swapOperation - Calculates a swap operation with given params   */
+/* Parameters:                                                     */
+/*  n: value to be swapped.                                        */
+/*  bits: length of value to be swapped, in bits.                  */
+/* Returns 0 if no error:                                          */
+/*  -2 if bits is out of valid range: even numbers (2..32)         */
+/*  -1 if n has bits in positions over the bits param              */
+/*-----------------------------------------------------------------*/
+static int
+swapOperation (unsigned long n, unsigned long bits, unsigned long * result)
+{
+  unsigned long mask = (1ULL << bits) -1;
+  unsigned int shift = bits / 2;
+  
+  if ((bits < 1) || (bits > 32) || (bits & 0x01)) // bits out of range or odd
+    return -2;
+  if (n != (n & mask)) // bits outside mask?
+    return -1;
+  
+  *result = (((n << shift) | (n >> shift)) & mask);
+  return 0; // no error.
+}
+
+/*-----------------------------------------------------------------*/ 
+/* stringMatchesOperator - returns true if 'str' matches 'op'      */
+/* 'str' matches 'op' if they contain the same string              */
+/* 'str' also matches if surrounded by quotes or double quotes     */
+/*-----------------------------------------------------------------*/
+static bool 
+stringMatchesOperator (const char * str, const char *op)
+{
+  if (str && op)
+    {
+      if (strcmp(str, op) == 0)
+        {
+          return true;
+        }
+      else
+        {
+          size_t length = strlen(str);
+          // Check if quotes are present and they are the same at start and end.
+          if ((length >= 2) && ((str[0] == '\'') || (str[0] == '\"')) && (str[0] == str[length-1]))
+            return strncmp(&str[1], op, length-2) == 0;
+        }
+    }
+  return false;
+}
+/*-----------------------------------------------------------------*/ 
+/* immdInRange - returns true if the result of a given operation   */
+/* of two immediates is in a give range.                           */
 /*-----------------------------------------------------------------*/
 FBYNAME (immdInRange)
 {
-  char r[64], operator[8];
+  char r[64], operator[24];
   const char *op;
   long i, j, k, h, low, high, left_l, right_l, order;
-  const char *padd[] = {"+", "'+'", "\"+\"", "add", "'add'", "\"add\""};
-  const char *psub[] = {"-", "'-'", "\"-\"", "sub", "'sub'", "\"sub\""};
 
   for (i = order = 0; order < 6;)
     {
@@ -1367,6 +2100,8 @@
       for (j = i; !ISCHARSPACE (cmdLine[j]) && cmdLine[j]; j++);
       if (!cmdLine[i]) // unexpected end
         return immdError ("no enough input", "", cmdLine);
+      else if(j >= 64)
+        return immdError ("buffer overflow", "", cmdLine);
       else
         {
           for (k = i; k < j; k++)
@@ -1385,7 +2120,7 @@
               return immdError ("bad upper bound", r, cmdLine);
             break;
           case 2: // operator
-            if (sscanf (r, "%s", operator) != 1)
+            if (sscanf (r, "%23s", operator) != 1)
               return immdError ("bad operator", r, cmdLine);
             break;
           case 3: // left operand
@@ -1397,7 +2132,7 @@
                 if (!immdGet (r + 1, &k) || !(op = hTabItemWithKey (vars, (int) k)))
                   return immdError ("bad left operand", r, cmdLine);
                 else if (!immdGet (op, &left_l))
-                  return immdError ("bad left operand", op, r);
+                  return FALSE;
               }
             else
               return immdError ("bad left operand", r, cmdLine);
@@ -1417,7 +2152,7 @@
               return immdError ("bad right operand", r, cmdLine);
             break;
           case 5: // result
-            if (r[0] != '%' || !immdGet (r + 1, &h))
+            if (r[0] != '%' || !(immdGet (r + 1, &h) || (r[1] == 'x' && immdGet (r + 2, &h))))
               return immdError ("bad result container", r, cmdLine);
             break;
           default: // should not reach
@@ -1429,29 +2164,71 @@
     }
 
   // calculate
-  for (j = k = 0; k < sizeof (padd) / sizeof (padd[0]); k++) // add
-    if (strcmp (operator, padd[k]) == 0)
-      {
-        i = left_l + right_l;
-        j = 1;
-        break;
-      }
-  if (!j)
-    for (k = 0; k < sizeof (psub) / sizeof (psub[0]); k++) // sub
-      if (strcmp (operator, psub[k]) == 0)
-        {
-          i = left_l - right_l;
-          j = 1;
-          break;
-        }
-  if (!j)
+  if (stringMatchesOperator (operator, "+")) // add
+    {
+      i = left_l + right_l;
+    }
+  else if (stringMatchesOperator (operator, "-")) // sub
+    {
+      i = left_l - right_l;
+    }
+  else if (stringMatchesOperator (operator, "*")) // mul
+    {
+      i = left_l * right_l;
+    }
+  else if (stringMatchesOperator (operator, "/")) // div
+    {
+      if (right_l == 0)
+        return immdError ("division by zero", "", cmdLine);
+      i = left_l / right_l;
+    }
+  else if (stringMatchesOperator (operator, "%")) // mod
+    {
+      if (right_l == 0)
+        return immdError ("division by zero", "", cmdLine);
+      i = left_l % right_l;
+    }
+  else if (stringMatchesOperator (operator, "&")) // and
+    {
+      i = left_l & right_l;
+    }
+  else if (stringMatchesOperator (operator, "^")) // xor
+    {
+      i = left_l ^ right_l;
+    }
+  else if (stringMatchesOperator (operator, "|")) // or
+    {
+      i = left_l | right_l;
+    }
+  else if (stringMatchesOperator (operator, "singleSetBit") || stringMatchesOperator (operator, "singleResetBit")) // singleSetBit - singleResetBit
+    {
+      i = findBitPosition(left_l, right_l, stringMatchesOperator (operator, "singleResetBit"));
+      if(i < -1 )
+        return immdError ("bad right operand", operator, cmdLine);
+      if(i < 0)
+        return false;
+    }
+  else if (stringMatchesOperator (operator, "swap")) // swap
+    {
+      if (swapOperation(left_l, right_l, (unsigned long *)&i) != 0)
+        return immdError ("bad right operand", operator, cmdLine);
+    }
+  else
     return immdError ("bad operator", operator, cmdLine);
 
   // bind the result
   if ((low <= i && i <= high) || (high <= i && i <= low))
     {
+      bool hex = false;
+      if(r[1] == 'x'){
+        hex = true;
+        r[1] = '0';
+      }
       char *p[] = {r, NULL};
-      sprintf (r, "%ld", i);
+      if(!hex)
+        sprintf (r, "%ld", i);
+      else
+        sprintf (r, "0x%lx", i);
       bindVar ((int) h, p, &vars);
       return TRUE;
     }
@@ -1503,6 +2280,40 @@
   return TRUE;
 }
 
+/*-----------------------------------------------------------------*/
+/* isPort - return true if port name matches one of args           */
+/*-----------------------------------------------------------------*/
+FBYNAME (isPort)
+{
+  const char *name;
+  bool ret = false;
+
+  set *operands = setFromConditionArgs(cmdLine, vars);
+
+  if (!operands)
+    {
+      fprintf(stderr,
+        "*** internal error: isPort peephole restriction"
+        " malformed: %s\n", cmdLine);
+      return false;
+    }
+
+  while (name = setFirstItem(operands))
+    {
+      deleteSetItem(&operands, (void *)name);
+
+      if (strcmp(port->target, name) == 0)
+        {
+          ret = true;
+          break;
+        }
+    }
+
+  deleteSet(&operands);
+
+  return ret;
+}
+
 static const struct ftab
 {
   char *fname;
@@ -1547,6 +2358,9 @@
     "inSequence", inSequence                        // z88dk z80
   },
   {
+    "optimizeFor", optimizeFor
+  },
+  {
     "optimizeReturn", optimizeReturn                // ? just a guess
   },
   {
@@ -1559,7 +2373,10 @@
     "operandsLiteral", operandsLiteral              // 6
   },
   {
-    "portIsDS390", portIsDS390                      // 5
+    "operandsLitOrSym", operandsLitOrSym
+  },
+  {
+    "removeParentheses", removeParentheses
   },
   {
     "labelIsUncondJump", labelIsUncondJump          // 4
@@ -1585,6 +2402,21 @@
   {
     "symmParmStack", symmParmStack
   },
+  {
+    "isPort", isPort
+  },
+  {
+    "canJoinRegs", canJoinRegs
+  },
+  {
+    "canSplitReg", canSplitReg
+  },
+  {
+    "unusedReg", unusedReg
+  },
+  {
+    "newLabel", newLabel
+  },
 };
 
 /*-----------------------------------------------------------------*/
@@ -1832,8 +2664,7 @@
     return;
 
   /* then look for either "restart" or '{' */
-  while (strncmp (bp, "restart", 7) &&
-         *bp != '{' && bp)
+  while (strncmp (bp, "restart", 7) && *bp != '{' && bp)
     bp++;
 
   /* not found */
@@ -1976,6 +2807,7 @@
          !ISCHARSPACE (*vvx) &&
          *vvx != '\n' &&
          *vvx != ':' &&
+         *vvx != ';' &&
          *vvx != ')')
     {
       char ubb = 0;
@@ -2025,6 +2857,8 @@
       /* skip white space in both */
       while (ISCHARSPACE(*s))
           s++;
+      if(*s==';') break;
+      
       while (ISCHARSPACE(*d))
           d++;
 
@@ -2049,20 +2883,9 @@
           while (ISCHARDIGIT (*d))
             d++;
         }
-      else if (ISCHARSPACE (*s) && ISCHARSPACE (*d)) /* whitespace sequences match any whitespace sequences */
-        {
-          while (ISCHARSPACE (*s))
-            s++;
-          while (ISCHARSPACE (*d))
-            d++;
-        }
-      else if (*s == ',' && *d == ',') /* Allow comman to match comma followed by whitespace */
+      else if (*s == ',' && *d == ',') /* Allow comma to match comma */
         {
           s++, d++;
-          while (ISCHARSPACE (*s))
-            s++;
-          while (ISCHARSPACE (*d))
-            d++;
         }
       else if (*s && *d) /* they should be an exact match otherwise */
         {
@@ -2076,6 +2899,11 @@
     while (ISCHARSPACE (*s))
       s++;
 
+  /* skip trailing comments as well*/
+  if(*s==';')
+   while (*s)
+     s++;
+
   if (*d)
     while (ISCHARSPACE (*d))
       d++;
@@ -2133,6 +2961,11 @@
       /* if this rule has additional conditions */
       if (pr->cond)
         {
+          /* constraints which uses variables as destination container
+             requires to vars table to be defined */
+          if (!pr->vars)
+            pr->vars = newHashTable (128);
+
           if (callFuncByName (pr->cond, pr->vars, pl, spl, head))
             {
               *mtail = spl;
@@ -2502,22 +3335,22 @@
   s = line;
   while (ISCHARSPACE (*s))
     ++s;
-  	
+
   if(strncmp(s, "call", 4))
     return FALSE;
   s += 4;
 
   while (ISCHARSPACE (*s))
     ++s;
-  
+
   /* Skip condition in conditional call */
   if (strchr(s, ',')) 
     s = strchr(s, ',') + 1;
-    
+
   e = s, *len = 0;
   while(*e && !ISCHARSPACE (*e) && *e != ';')
     ++e, ++(*len);
-    
+
   *start = s;
 
   return TRUE;
@@ -2571,13 +3404,13 @@
           labelHashEntry *entry, *e;
 
           assert (labelLen <= SDCC_NAME_MAX);
-              
+
           entry = traceAlloc (&_G.labels, Safe_alloc(sizeof (labelHashEntry)));
 
           memcpy (entry->name, label, labelLen);
           entry->name[labelLen] = 0;
           entry->refCount = -1;
-     
+
           for (e = hTabFirstItemWK (labelHash, hashSymbolName (entry->name)); e; e = hTabNextItemWK (labelHash))
             if (!strcmp (entry->name, e->name))
               goto c;
@@ -2620,8 +3453,8 @@
                 e->refCount++;
             }
         }
-        
-        
+
+
       for (i = 0; i < HTAB_SIZE; i++)
         {
           labelHashEntry *thisEntry;
@@ -2868,26 +3701,26 @@
 /*-----------------------------------------------------------------*/
 const char * StrStr (const char * str1, const char * str2)
 {
-	const char * cp = str1;
-	const char * s1;
-	const char * s2;
+  const char * cp = str1;
+  const char * s1;
+  const char * s2;
 
-	if ( !*str2 )
-	    return str1;
+  if ( !*str2 )
+    return str1;
 
-	while (*cp)
-	{
-		s1 = cp;
-		s2 = str2;
+  while (*cp)
+    {
+      s1 = cp;
+      s2 = str2;
 
-		while ( *s1 && *s2 && !(tolower(*s1)-tolower(*s2)) )
-			s1++, s2++;
+      while ( *s1 && *s2 && !(tolower(*s1)-tolower(*s2)) )
+        s1++, s2++;
 
-		if (!*s2)
-			return( cp );
+      if (!*s2)
+        return( cp );
 
-		cp++;
-	}
+      cp++;
+    }
 
-	return (NULL) ;
+  return (NULL) ;
 }
diff -Nru sdcc-4.0.0+dfsg/src/SDCCralloc.hpp sdcc-4.2.0+dfsg/src/SDCCralloc.hpp
--- sdcc-4.0.0+dfsg/src/SDCCralloc.hpp	2018-11-12 14:53:56.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/SDCCralloc.hpp	2021-05-12 12:33:07.000000000 +0000
@@ -364,7 +364,7 @@
         if (currFunc)
           currFunc->funcDivFlagSafe &= !(ic->op == INLINEASM || ic->op == '/' || ic->op == '%' || ic->op == PCALL ||
             ic->op == CALL && (IS_OP_LITERAL (IC_LEFT (ic)) || !OP_SYMBOL(IC_LEFT (ic))->funcDivFlagSafe) ||
-            ic->op == RIGHT_OP && IS_OP_LITERAL (IC_RIGHT (ic))); // Right shift might be implemented using division.
+            ic->op == RIGHT_OP && IS_OP_LITERAL (IC_RIGHT (ic)) && ulFromVal (OP_VALUE_CONST (IC_RIGHT (ic))) > 2); // Right shift might be implemented using division when shifting by more than 2.
 
 #ifdef DEBUG_SEGV
         default_constructor_of_cfg_node_called = false;
@@ -672,7 +672,6 @@
         }
       inserter_t& operator++(int i)
         {
-          i;
           return(*this);
         }
       private:
diff -Nru sdcc-4.0.0+dfsg/src/SDCCsalloc.hpp sdcc-4.2.0+dfsg/src/SDCCsalloc.hpp
--- sdcc-4.0.0+dfsg/src/SDCCsalloc.hpp	2019-10-13 14:48:53.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/SDCCsalloc.hpp	2021-11-22 14:39:14.000000000 +0000
@@ -144,6 +144,7 @@
   for(unsigned int i = 0; i < boost::num_vertices(G); i++)
     {
       G[i].ic->localEscapeAlive = false;
+      G[i].ic->parmEscapeAlive = false;
 
       for(unsigned int j = 0; j < boost::num_vertices(scon); j++)
         {
@@ -151,7 +152,7 @@
           if(p == G[i].ic->block || p == scon[j].sym->block)
             {
               G[i].stack_alive.insert(j);
-              if (scon[j].sym->addrtaken || IS_AGGREGATE(scon[j].sym->type) ) // TODO: More accurate analysis.
+              if (scon[j].sym->addrtaken || IS_AGGREGATE(scon[j].sym->type)) // TODO: More accurate analysis.
                 G[i].ic->localEscapeAlive = true;
             }
         }
@@ -217,6 +218,10 @@
   // Ugly hack: Regparms.
   for(sym = static_cast(setFirstItem(istack->syms)), j = boost::num_vertices(scon); sym; sym = static_cast(setNextItem(istack->syms)))
     {
+      if (sym->_isparm && !IS_REGPARM(sym->etype) && sym->addrtaken)
+        for(unsigned int i = 0; i < boost::num_vertices(G); i++)
+          G[i].ic->parmEscapeAlive = true;
+      
       if(!sym->_isparm || !IS_REGPARM(sym->etype) || !sym->onStack || !sym->allocreq)
         continue;
       
@@ -226,7 +231,11 @@
 
       // Extend liverange to cover everything.
       for(unsigned int i = 0; i < boost::num_vertices(G); i++)
-        G[i].stack_alive.insert(j);
+        {
+          G[i].stack_alive.insert(j);
+          if (sym->addrtaken)
+            G[i].ic->localEscapeAlive = true;
+        }
 
       // Conflict with everything.
       for(unsigned int i = 0; i < j; i++)
@@ -250,8 +259,13 @@
       const var_t right = var_from_operand (symbol_to_sindex, IC_RIGHT(G[i].ic));
 
       if(left >= 0 && !boost::edge (result, left, scon).second)
-        scon[(boost::add_edge(result, left, scon)).first].alignment_conflict_only =
-          !(TARGET_PDK_LIKE && G[i].ic->op == GET_VALUE_AT_ADDRESS && getSize(scon[result].sym->type) > 2); // Padauk still needs pointer read operand, since pointer read of more than 2 bytes is broken into multiple support routine calls.
+        {
+          scon[(boost::add_edge(result, left, scon)).first].alignment_conflict_only = true;
+          if (TARGET_PDK_LIKE && G[i].ic->op == GET_VALUE_AT_ADDRESS && getSize(scon[result].sym->type) > 2) // Padauk still needs pointer read operand, since pointer read of more than 2 bytes is broken into multiple support routine calls.
+            scon[(boost::add_edge(result, left, scon)).first].alignment_conflict_only = false;
+          if (TARGET_IS_STM8 && (G[i].ic->op == RIGHT_OP || G[i].ic->op == LEFT_OP) && IS_OP_LITERAL(IC_RIGHT(G[i].ic)) && ulFromVal (OP_VALUE_CONST (IC_RIGHT(G[i].ic))) >= 6) // Byte shifting in shift by constant might fail for partially spilt variables. Currently only the stm8 register allocator might partially spill variables.
+            scon[(boost::add_edge(result, left, scon)).first].alignment_conflict_only = false;
+        }
       if(right >= 0 && !boost::edge (result, right, scon).second)
         scon[(boost::add_edge(result, right, scon)).first].alignment_conflict_only = true;
     }
@@ -265,7 +279,7 @@
   
   SI[v].color = start;
 
-  const int sloc = (port->stack.direction > 0) ? start : -start - size ;
+  const int sloc = (port->stack.direction > 0) ? start : -start - size;
   symbol *const ssym = (sym->isspilt && sym->usl.spillLoc) ? sym->usl.spillLoc : sym;
 
   SPEC_STAK(ssym->etype) = ssym->stack = sloc;
diff -Nru sdcc-4.0.0+dfsg/src/SDCCset.c sdcc-4.2.0+dfsg/src/SDCCset.c
--- sdcc-4.0.0+dfsg/src/SDCCset.c	2018-06-12 23:40:05.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/SDCCset.c	2022-02-03 09:32:48.000000000 +0000
@@ -192,7 +192,7 @@
     {
       /*
        * On the x86 va_list is just a pointer, so due to pass by value
-       * ap is not mofified by the called function.  On the PPC va_list
+       * ap is not modified by the called function.  On the PPC va_list
        * is a pointer to a structure, so ap is modified.  Re-init each time.
        */
       va_start (ap, cond);
@@ -223,7 +223,7 @@
     {
       /*
        * On the x86 va_list is just a pointer, so due to pass by value
-       * ap is not mofified by the called function.  On the PPC va_list
+       * ap is not modified by the called function.  On the PPC va_list
        * is a pointer to a structure, so ap is modified.  Re-init each time.
        */
       va_start (ap, cond);
diff -Nru sdcc-4.0.0+dfsg/src/SDCCsymt.c sdcc-4.2.0+dfsg/src/SDCCsymt.c
--- sdcc-4.0.0+dfsg/src/SDCCsymt.c	2019-12-29 11:00:56.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/SDCCsymt.c	2022-02-26 13:53:38.000000000 +0000
@@ -353,6 +353,7 @@
   p = Safe_alloc (sizeof (sym_link));
   p->xclass = select;
   p->funcAttrs.z88dk_params_offset = 0;
+  FUNC_SDCCCALL (p) = -1;
 
   return p;
 }
@@ -491,7 +492,6 @@
 void
 addDecl (symbol * sym, int type, sym_link * p)
 {
-  static sym_link *empty = NULL;
   sym_link *head;
   sym_link *tail;
   sym_link *t;
@@ -499,9 +499,6 @@
   if (getenv ("SDCC_DEBUG_FUNCTION_POINTERS"))
     fprintf (stderr, "SDCCsymt.c:addDecl(%s,%d,%p)\n", sym->name, type, (void *)p);
 
-  if (empty == NULL)
-    empty = newLink (SPECIFIER);
-
   /* if we are passed a link then set head & tail */
   if (p)
     {
@@ -515,16 +512,18 @@
       DCL_TYPE (head) = type;
     }
 
-  /* if this is the first entry   */
+  // no type yet: make p the type
   if (!sym->type)
     {
       sym->type = head;
       sym->etype = tail;
     }
+  // type ends in spec, p is single spec element: merge specs
   else if (IS_SPEC (sym->etype) && IS_SPEC (head) && head == tail)
     {
       sym->etype = mergeSpec (sym->etype, head, sym->name);
     }
+  // type ends in spec, p is single decl element: p goes before spec
   else if (IS_SPEC (sym->etype) && !IS_SPEC (head) && head == tail)
     {
       t = sym->type;
@@ -533,11 +532,25 @@
       t->next = head;
       tail->next = sym->etype;
     }
-  else if (IS_FUNC (sym->type) && IS_SPEC (sym->type->next) && !memcmp (sym->type->next, empty, sizeof (sym_link)))
+  // type ends in spec, p ends in spec: merge specs, p's decls go before spec
+  else if (IS_SPEC (sym->etype) && IS_SPEC (tail))
     {
-      sym->type->next = head;
-      sym->etype = tail;
+      sym->etype = mergeSpec (sym->etype, tail, sym->name);
+
+      // cut off p's spec
+      t = head;
+      while (t->next != tail)
+          t = t->next;
+      tail = t;
+
+      // splice p's decls
+      t = sym->type;
+      while (t->next != sym->etype)
+          t = t->next;
+      t->next = head;
+      tail->next = sym->etype;
     }
+  // append p to the type
   else
     {
       sym->etype->next = head;
@@ -545,7 +558,7 @@
     }
 
   /* if the type is an unknown pointer and has
-     a tspec then take the storage class const & volatile
+     a tspec then take the storage class and address
      attribute from the tspec & make it those of this
      symbol */
   if (p && !IS_SPEC (p) &&
@@ -565,7 +578,7 @@
   // if there is a function in this type chain
   if (p && funcInChain (sym->type))
     {
-      processFuncArgs (sym);
+      processFuncArgs (sym, NULL);
     }
 
   return;
@@ -823,7 +836,18 @@
   FUNC_REGBANK (dest) |= FUNC_REGBANK (src);
   FUNC_ISINLINE (dest) |= FUNC_ISINLINE (src);
   FUNC_ISNORETURN (dest) |= FUNC_ISNORETURN (src);
+  if (FUNC_ISRAISONANCE (dest) && (FUNC_ISIAR (src) || FUNC_ISCOSMIC (src) || FUNC_SDCCCALL (src) >= 0 || FUNC_ISZ88DK_CALLEE (src)) ||
+    FUNC_ISIAR (dest) && (FUNC_ISRAISONANCE (src) || FUNC_ISCOSMIC (src) || FUNC_SDCCCALL (src) >= 0 || FUNC_ISZ88DK_CALLEE (src)) ||
+    FUNC_ISCOSMIC (dest) && (FUNC_ISRAISONANCE (src) || FUNC_ISIAR (src) || FUNC_SDCCCALL (src) >= 0 || FUNC_ISZ88DK_CALLEE (src)) ||
+    FUNC_SDCCCALL (dest) >= 0 && (FUNC_ISRAISONANCE (src) || FUNC_ISIAR (src) || FUNC_ISCOSMIC (src) || FUNC_SDCCCALL (src) >= 0 && FUNC_SDCCCALL (dest) != FUNC_SDCCCALL (src)) || // __sdcccall can be combined with __z88dk_callee.
+    FUNC_ISZ88DK_CALLEE (src) && (FUNC_ISRAISONANCE (src) || FUNC_ISIAR (dest) || FUNC_ISCOSMIC (dest)))
+    werror (E_MULTIPLE_CALLINGCONVENTIONS, name);
+  if (FUNC_SDCCCALL (dest) == -1)
+    FUNC_SDCCCALL (dest) = FUNC_SDCCCALL (src);
   FUNC_ISSMALLC (dest) |= FUNC_ISSMALLC (src);
+  FUNC_ISRAISONANCE (dest) |= FUNC_ISRAISONANCE (src);
+  FUNC_ISIAR (dest) |= FUNC_ISIAR (src);
+  FUNC_ISCOSMIC (dest) |= FUNC_ISCOSMIC (src);
   FUNC_ISZ88DK_FASTCALL (dest) |= FUNC_ISZ88DK_FASTCALL (src);
   FUNC_ISZ88DK_CALLEE (dest) |= FUNC_ISZ88DK_CALLEE (src);
   for (i = 0; i < 9; i++)
@@ -877,14 +901,23 @@
         }
     }
 
-  DCL_PTR_CONST (decl) |= SPEC_CONST (spec);
-  DCL_PTR_VOLATILE (decl) |= SPEC_VOLATILE (spec);
-  DCL_PTR_RESTRICT (decl) |= SPEC_RESTRICT (spec);
-  if (DCL_PTR_ADDRSPACE (decl) && SPEC_ADDRSPACE (spec) &&
-    strcmp (DCL_PTR_ADDRSPACE (decl)->name, SPEC_ADDRSPACE (spec)->name))
-    werror (E_SYNTAX_ERROR, yytext);
-  if (SPEC_ADDRSPACE (spec))
-    DCL_PTR_ADDRSPACE (decl) = SPEC_ADDRSPACE (spec);
+  // for pointers, type qualifiers go in the declarator
+  if (DCL_TYPE (decl) != ARRAY && DCL_TYPE (decl) != FUNCTION)
+    {
+      DCL_PTR_CONST (decl) |= SPEC_CONST (spec);
+      DCL_PTR_VOLATILE (decl) |= SPEC_VOLATILE (spec);
+      DCL_PTR_RESTRICT (decl) |= SPEC_RESTRICT (spec);
+      if (DCL_PTR_ADDRSPACE (decl) && SPEC_ADDRSPACE (spec) &&
+        strcmp (DCL_PTR_ADDRSPACE (decl)->name, SPEC_ADDRSPACE (spec)->name))
+        werror (E_SYNTAX_ERROR, yytext);
+      if (SPEC_ADDRSPACE (spec))
+        DCL_PTR_ADDRSPACE (decl) = SPEC_ADDRSPACE (spec);
+
+      SPEC_CONST (spec) = 0;
+      SPEC_VOLATILE (spec) = 0;
+      SPEC_RESTRICT (spec) = 0;
+      SPEC_ADDRSPACE (spec) = 0;
+    }
 
   lnk = decl;
   while (lnk && !IS_SPEC (lnk->next))
@@ -1023,6 +1056,25 @@
 }
 
 /*------------------------------------------------------------------*/
+/* newPtrDiffLink() - creates a ptrdiff type                        */
+/*------------------------------------------------------------------*/
+sym_link *
+newPtrDiffLink ()
+{
+  if (GPTRSIZE <= INTSIZE)
+    return newIntLink ();
+  else if (GPTRSIZE <= LONGSIZE)
+    return newLongLink ();
+  else if (GPTRSIZE <= LONGLONGSIZE)
+    return newLongLongLink();
+  else
+    {
+      assert (0);
+      return NULL;
+    }
+}
+
+/*------------------------------------------------------------------*/
 /* newVoidLink() - creates an void type                             */
 /*------------------------------------------------------------------*/
 sym_link *
@@ -1097,10 +1149,13 @@
     case CPOINTER:
       if (!IS_FUNCPTR(p))
         return (FARPTRSIZE);
-    case FUNCTION:
-      return (IFFUNC_ISBANKEDCALL (p) ? BFUNCPTRSIZE : FUNCPTRSIZE);
     case GPOINTER:
-      return (GPTRSIZE);
+      if (!IS_FUNCPTR(p))
+        return (GPTRSIZE);
+    case FUNCTION:
+      if (IS_FUNCPTR(p))
+        return ((IFFUNC_ISBANKEDCALL (p->next) || TARGET_IS_STM8 && IFFUNC_ISCOSMIC (p->next)) ? BFUNCPTRSIZE : FUNCPTRSIZE);
+      return ((IFFUNC_ISBANKEDCALL (p) || TARGET_IS_STM8 && IFFUNC_ISCOSMIC (p)) ? BFUNCPTRSIZE : FUNCPTRSIZE);
 
     default:
       return 0;
@@ -1732,8 +1787,7 @@
   int base;
 
   tofield = &sdef->fields;
-  field = sdef->fields;
-  while (field)
+  for (field = sdef->fields; field; field = nextfield)
     {
       nextfield = field->next;
       if (!*field->name && IS_STRUCT (field->type))
@@ -1778,7 +1832,6 @@
         }
       else
         tofield = &field->next;
-      field = nextfield;
     }
 }
 
@@ -2130,9 +2183,43 @@
     }
 }
 
+/*------------------------------------------------------------------*/
+/* leaveBlockScope - mark items in SymbolTab from a particular      */
+/*                   block as out-of-scope                          */
+/*------------------------------------------------------------------*/
+void
+leaveBlockScope (int block)
+{
+  int i;
+  bucket *chain;
+
+  /* go thru the entire  table  */
+  for (i = 0; i < 256; i++)
+    {
+      for (chain = SymbolTab[i]; chain; chain = chain->next)
+        {
+          if (chain->block == block)
+            {
+              symbol *sym = (symbol *)chain->sym;
+              
+              /* Temporary fix for bug #3289 - leave enums in scope. */
+              /* This is also buggy but compatible with 4.1.0 and    */
+              /* earlier behavior and less likely to trigger errors. */
+              if (sym->etype && SPEC_ENUM(sym->etype))
+                continue;
+              /* Everything else, mark as out of scope. */
+              sym->isinscope = 0;
+            }
+        }
+    }
+}
+
 symbol *
 getAddrspace (sym_link *type)
 {
+  while(IS_ARRAY (type))
+    type = type->next;
+
   if (IS_DECL (type))
     return (DCL_PTR_ADDRSPACE (type));
   return (SPEC_ADDRSPACE (type));
@@ -2218,6 +2305,23 @@
   /* Conditional operator has some special type conversion rules */
   if (op == ':')
     {
+      /* Function types are really pointers to functions */
+      if (IS_FUNC (type1))
+        {
+          sym_link *fptr;
+          fptr = newLink (DECLARATOR);
+          DCL_TYPE (fptr) = CPOINTER;
+          fptr->next = type1;
+          type1 = fptr;
+        }
+      if (IS_FUNC (type2))
+        {
+          sym_link *fptr;
+          fptr = newLink (DECLARATOR);
+          DCL_TYPE (fptr) = CPOINTER;
+          fptr->next = type2;
+          type2 = fptr;
+        }
       /* If either type is an array, convert to pointer */
       if (IS_ARRAY(type1))
         {
@@ -2259,7 +2363,9 @@
   /* shift operators have the important type in the left operand */
   if (op == LEFT_OP || op == RIGHT_OP)
     rType = copyLinkChain(type1);
-
+  /* If difference between pointers or arrays then the result is a ptrdiff */
+  else if ((op == '-') && (IS_PTR (type1) || IS_ARRAY (type1)) && (IS_PTR (type2) || IS_ARRAY (type2)))
+    rType = newPtrDiffLink();
   /* if one of them is a pointer or array then that prevails */
   else if (IS_PTR (type1) || IS_ARRAY (type1))
     rType = copyLinkChain (type1);
@@ -2336,7 +2442,7 @@
     case RESULT_TYPE_BOOL:
       if (op == ':')
         {
-          SPEC_NOUN (reType) = V_BIT;
+          SPEC_NOUN (reType) = TARGET_MCS51_LIKE ? V_BIT : V_BOOL;
           return rType;
         }
       break;
@@ -2506,6 +2612,15 @@
     IFFUNC_ISZ88DK_CALLEE (dest) != IFFUNC_ISZ88DK_CALLEE (src))
     return 0;
 
+  if (IFFUNC_ISRAISONANCE (dest) != IFFUNC_ISRAISONANCE (src) ||
+    IFFUNC_ISCOSMIC (dest) != IFFUNC_ISCOSMIC (src) ||
+    IFFUNC_ISIAR (dest) != IFFUNC_ISIAR (src))
+    return 0;
+
+  if (FUNC_SDCCCALL (dest) >= 0 && FUNC_SDCCCALL (src) >= 0 &&
+    FUNC_SDCCCALL (dest) != FUNC_SDCCCALL (src))
+    return 0;
+
   for (i = 0; i < 9; i++)
     if (dest->funcAttrs.preserved_regs[i] > src->funcAttrs.preserved_regs[i])
       return 0;
@@ -2760,6 +2875,19 @@
                     return 0;
                   if (IFFUNC_ISNAKED (dest) != IFFUNC_ISNAKED (src))
                     return 0;
+
+                  if (IFFUNC_ISZ88DK_FASTCALL (dest) != IFFUNC_ISZ88DK_FASTCALL (src))
+                    return 0;
+                  if (IFFUNC_ISRAISONANCE (dest) != IFFUNC_ISRAISONANCE (src))
+                    return 0;
+                  if (IFFUNC_ISCOSMIC (dest) != IFFUNC_ISCOSMIC (src))
+                    return 0;
+                  if (IFFUNC_ISIAR (dest) != IFFUNC_ISIAR (src))
+                    return 0;
+                  if (FUNC_SDCCCALL (dest) >= 0 && FUNC_SDCCCALL (src) >= 0 &&
+                    FUNC_SDCCCALL (dest) != FUNC_SDCCCALL (src))
+                    return 0;
+
 #if 0
                   if (IFFUNC_ISREENT (dest) != IFFUNC_ISREENT (src) && argCnt > 1)
                     return 0;
@@ -3040,6 +3168,10 @@
       FUNC_ISNORETURN (sym->type) = 1;
     }
 
+  /* If no ABI version specified, use port default */
+  if (FUNC_SDCCCALL (sym->type) < 0)
+    FUNC_SDCCCALL (sym->type) = options.sdcccall;
+
   /* make sure the type is complete and sane */
   checkTypeSanity (sym->etype, sym->name);
 
@@ -3264,41 +3396,58 @@
 void
 processFuncPtrArgs (sym_link * funcType)
 {
-  value *val = FUNC_ARGS (funcType);
-
-  /* if it is void then remove parameters */
-  if (val && IS_VOID (val->type))
-    {
-      FUNC_ARGS (funcType) = NULL;
-      return;
-    }
+  processFuncArgs (NULL, funcType);
 }
 
 /*-----------------------------------------------------------------*/
 /* processFuncArgs - does some processing with function args       */
+/*                                                                 */
+/*   Leave func NULL if processing a type rather than a symbol     */
 /*-----------------------------------------------------------------*/
 void
-processFuncArgs (symbol *func)
+processFuncArgs (symbol *func, sym_link *funcType)
 {
   value *val;
   int pNum = 1;
-  sym_link *funcType = func->type;
+  char *funcName = NULL;
+  int funcCdef = 0;
+
+  if (func && !funcType)
+    funcType = func->type;
+  if (func)
+    {
+      funcCdef = func->cdef;
+      funcName = func->name;
+    }
+  else
+    {
+      funcCdef = 0;
+      funcName = "unnamed function type";
+    }
 
   if (getenv ("SDCC_DEBUG_FUNCTION_POINTERS"))
-    fprintf (stderr, "SDCCsymt.c:processFuncArgs(%s)\n", func->name);
+    fprintf (stderr, "SDCCsymt.c:processFuncArgs(%s)\n", funcName);
 
   /* find the function declaration within the type */
   while (funcType && !IS_FUNC (funcType))
     funcType = funcType->next;
 
+  /* Nothing to do if no function type found */
+  if (!funcType)
+    return;
+
   /* if this function has variable argument list */
   /* then make the function a reentrant one    */
-  if (IFFUNC_HASVARARGS (funcType) || (options.stackAuto && !func->cdef))
+  if (IFFUNC_HASVARARGS (funcType) || (options.stackAuto && !funcCdef))
     FUNC_ISREENT (funcType) = 1;
 
   /* check if this function is defined as calleeSaves
      then mark it as such */
-  FUNC_CALLEESAVES (funcType) = inCalleeSaveList (func->name);
+  FUNC_CALLEESAVES (funcType) = inCalleeSaveList (funcName);
+
+  /* If no ABI version specified, use port default */
+  if (FUNC_SDCCCALL (funcType) < 0)
+    FUNC_SDCCCALL (funcType) = options.sdcccall;
 
   /* loop thru all the arguments   */
   val = FUNC_ARGS (funcType);
@@ -3323,10 +3472,10 @@
       if (val->sym && val->sym->name)
         for (value *val2 = val->next; val2; val2 = val2->next)
           if (val2->sym && val2->sym->name && !strcmp (val->sym->name, val2->sym->name))
-            werror (E_DUPLICATE_PARAMTER_NAME, val->sym->name, func->name);
+            werror (E_DUPLICATE_PARAMTER_NAME, val->sym->name, funcName);
 
       dbuf_init (&dbuf, 128);
-      dbuf_printf (&dbuf, "%s parameter %d", func->name, pNum);
+      dbuf_printf (&dbuf, "%s parameter %d", funcName, pNum);
       checkTypeSanity (val->etype, dbuf_c_str (&dbuf));
       dbuf_destroy (&dbuf);
 
@@ -3338,7 +3487,7 @@
       /* mark it as a register parameter if
          the function does not have VA_ARG
          and as port dictates */
-      if (!IFFUNC_HASVARARGS (funcType) && (argreg = (*port->reg_parm) (val->type, FUNC_ISREENT (funcType))))
+      if (argreg = (*port->reg_parm) (val->type, FUNC_ISREENT (funcType)))
         {
           SPEC_REGPARM (val->etype) = 1;
           SPEC_ARGREG (val->etype) = argreg;
@@ -3361,7 +3510,7 @@
     }
 
   /* if this is an internal generated function call */
-  if (func->cdef)
+  if (funcCdef)
     {
       /* ignore --stack-auto for this one, we don't know how it is compiled */
       /* simply trust on --int-long-reent or --float-reent */
@@ -3378,6 +3527,10 @@
         return;
     }
 
+  /* Don't create parameter symbols without a function symbol */
+  if (!func)
+    return;
+
   val = FUNC_ARGS (funcType);
   pNum = 1;
   while (val)
@@ -3507,9 +3660,11 @@
               for (args = FUNC_ARGS (type); args; args = args->next)
                 {
                   dbuf_printTypeChain (args->type, dbuf);
-                  if (args->next)
+                  if (args->next || FUNC_HASVARARGS(type))
                     dbuf_append_str (dbuf, ", ");
                 }
+              if (FUNC_HASVARARGS(type))
+                dbuf_append_str (dbuf, "...");
               dbuf_append_str (dbuf, ")");
               if (IFFUNC_ISREENT (type) && isTargetKeyword("__reentrant"))
                 dbuf_append_str (dbuf, " __reentrant");
@@ -3521,10 +3676,20 @@
                 }
               if (IFFUNC_ISBANKEDCALL (type))
                 dbuf_append_str (dbuf, " __banked");
+              if (IFFUNC_ISSMALLC (type))
+                dbuf_append_str (dbuf, " __smallc");
+              if (IFFUNC_ISRAISONANCE (type))
+                dbuf_append_str (dbuf, " __raisonance");
+              if (IFFUNC_ISIAR (type))
+                dbuf_append_str (dbuf, " __iar");
+              if (IFFUNC_ISCOSMIC (type))
+                dbuf_append_str (dbuf, " __cosmic");
               if (IFFUNC_ISZ88DK_CALLEE (type))
                 dbuf_append_str (dbuf, " __z88dk_callee");
               if (IFFUNC_ISZ88DK_FASTCALL (type))
                 dbuf_append_str (dbuf, " __z88dk_fastcall");
+              if (FUNC_SDCCCALL (type) >= 0 && FUNC_SDCCCALL (type) != options.sdcccall)
+                dbuf_printf (dbuf, " __sdcccall(%d)", FUNC_SDCCCALL (type));
               for (unsigned char i = 0; i < 9; i++)
                   if (type->funcAttrs.preserved_regs[i])
                   {
@@ -4002,11 +4167,11 @@
 /* Dims: shift left/shift right, BYTE/WORD/DWORD/QWORD, SIGNED/UNSIGNED */
 symbol *rlrr[2][4][2];
 
-sym_link *charType;
 sym_link *floatType;
 sym_link *fixed16x16Type;
 
-symbol *memcpy_builtin;
+symbol *builtin_memcpy;
+symbol *nonbuiltin_memcpy;
 
 static const char *
 _mangleFunctionName (const char *in)
@@ -4234,15 +4399,16 @@
 
   floatType = newFloatLink ();
   fixed16x16Type = newFixed16x16Link ();
-  charType = (options.signed_char) ? SCHARTYPE : UCHARTYPE;
+  sym_link *boolType = newLink (SPECIFIER); SPEC_NOUN (boolType) = V_BOOL; // Can't use newBoolLink, as it might give us a __bit.
+  sym_link *charType = (options.signed_char) ? SCHARTYPE : UCHARTYPE;
 
   fsadd = funcOfType ("__fsadd", floatType, floatType, 2, options.float_rent);
   fssub = funcOfType ("__fssub", floatType, floatType, 2, options.float_rent);
   fsmul = funcOfType ("__fsmul", floatType, floatType, 2, options.float_rent);
   fsdiv = funcOfType ("__fsdiv", floatType, floatType, 2, options.float_rent);
-  fseq = funcOfType ("__fseq", charType, floatType, 2, options.float_rent);
-  fsneq = funcOfType ("__fsneq", charType, floatType, 2, options.float_rent);
-  fslt = funcOfType ("__fslt", charType, floatType, 2, options.float_rent);
+  fseq = funcOfType ("__fseq", boolType, floatType, 2, options.float_rent);
+  fsneq = funcOfType ("__fsneq", boolType, floatType, 2, options.float_rent);
+  fslt = funcOfType ("__fslt", boolType, floatType, 2, options.float_rent);
 
   fps16x16_add = funcOfType ("__fps16x16_add", fixed16x16Type, fixed16x16Type, 2, options.float_rent);
   fps16x16_sub = funcOfType ("__fps16x16_sub", fixed16x16Type, fixed16x16Type, 2, options.float_rent);
@@ -4355,7 +4521,7 @@
           dbuf_init (&dbuf, 128);
           dbuf_printf (&dbuf, "_%s%s%s", smuldivmod[muldivmod], ssu[su], sbwd[bwd]);
           muldiv[muldivmod][bwd][su] =
-            funcOfType (_mangleFunctionName (dbuf_c_str (&dbuf)), multypes[(TARGET_IS_PIC16 && muldivmod == 1 && bwd == 0 && su == 0 || (TARGET_IS_PIC14 || TARGET_IS_STM8 || TARGET_Z80_LIKE || TARGET_PDK_LIKE) && bwd == 0) ? 1 : bwd][su % 2], multypes[bwd][su / 2], 2,
+            funcOfType (_mangleFunctionName (dbuf_c_str (&dbuf)), multypes[(TARGET_IS_PIC16 && muldivmod == 1 && bwd == 0 && su == 0 || (TARGET_IS_PIC14 || TARGET_IS_STM8 || TARGET_Z80_LIKE || TARGET_PDK_LIKE || TARGET_MOS6502_LIKE ) && bwd == 0) ? 1 : bwd][su % 2], multypes[bwd][su / 2], 2,
                         options.intlong_rent);
           dbuf_destroy (&dbuf);
         }
@@ -4452,15 +4618,19 @@
     }
 
   /* initialize memcpy symbol for struct assignment */
-  memcpy_builtin = findSym (SymbolTab, NULL, "__builtin_memcpy");
-  /* if there is no __builtin_memcpy, use __memcpy instead of an actual builtin */
-  if (!memcpy_builtin)
+  builtin_memcpy = findSym (SymbolTab, NULL, "__builtin_memcpy");
+  nonbuiltin_memcpy = findSym (SymbolTab, NULL, "__memcpy");
+
+  if (!nonbuiltin_memcpy)
     {
       const char *argTypeStrs[] = {"vg*", "Cvg*", "Ui"};
-      memcpy_builtin = funcOfTypeVarg ("__memcpy", "vg*", 3, argTypeStrs);
-      FUNC_ISBUILTIN (memcpy_builtin->type) = 0;
-      FUNC_ISREENT (memcpy_builtin->type) = options.stackAuto;
+      nonbuiltin_memcpy = funcOfTypeVarg ("__memcpy", "vg*", 3, argTypeStrs);
+      FUNC_ISBUILTIN (nonbuiltin_memcpy->type) = 0;
+      FUNC_ISREENT (nonbuiltin_memcpy->type) = options.stackAuto;
     }
+  /* if there is no __builtin_memcpy, use __memcpy instead of an actual builtin */
+  if (!builtin_memcpy)
+    builtin_memcpy = nonbuiltin_memcpy;
 }
 
 sym_link *
diff -Nru sdcc-4.0.0+dfsg/src/SDCCsymt.h sdcc-4.2.0+dfsg/src/SDCCsymt.h
--- sdcc-4.0.0+dfsg/src/SDCCsymt.h	2019-10-11 17:13:50.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/SDCCsymt.h	2021-08-08 17:13:19.000000000 +0000
@@ -22,10 +22,11 @@
 #define  SDCCSYMT_H
 
 #define MAX_NEST_LEVEL  256
-#define SDCC_SYMNAME_MAX 64
+#define SDCC_SYMNAME_MAX 256
 #define SDCC_NAME_MAX  3*SDCC_SYMNAME_MAX       // big enough for ___etc
 #include "SDCChasht.h"
 #include "SDCCglobl.h"
+#include "SDCCattr.h"
 #include "dbuf.h"
 
 #define INTNO_MAX 255           /* maximum allowed interrupt number */
@@ -272,7 +273,11 @@
     unsigned rbank:1;               /* seperate register bank               */
     unsigned inlinereq:1;           /* inlining requested                   */
     unsigned noreturn:1;            /* promised not to return               */
-    unsigned smallc:1;              /* Parameters on stack are passed in reverse order */
+    signed sdcccall;                /* ABI version used                     */
+    unsigned smallc:1;              /* Small-C calling convention: Parameters on stack are passed left-to-right */
+    unsigned raisonance:1;          /* Raisonance calling convention for STM8 */
+    unsigned iar:1;                 /* IAR calling convention               */
+    unsigned cosmic:1;              /* Cosmic calling convention            */
     unsigned z88dk_fastcall:1;      /* For the z80-related ports: Function has a single paramter of at most 32 bits that is passed in dehl */
     unsigned z88dk_callee:1;        /* Stack pointer adjustment for parameters passed on the stack is done by the callee */
     unsigned z88dk_shortcall:1;     /* Short call available via rst (see values later) (Z80 only) */
@@ -299,7 +304,7 @@
   char rname[SDCC_NAME_MAX + 1];    /* internal name           */
 
   long level;                       /* declaration lev,fld offset */
-  short block;                      /* sequential block # of definition */
+  int block;                        /* sequential block # of definition */
   int seqPoint;                     /* sequence point defined or, if unbound, used */
   int key;
   unsigned flexArrayLength;         /* if the symbol specifies a struct
@@ -429,6 +434,7 @@
 #define FUNC_ISISR(x) (x->funcAttrs.intrtn)
 #define IFFUNC_ISISR(x) (IS_FUNC(x) && FUNC_ISISR(x))
 #define FUNC_INTNO(x) (x->funcAttrs.intno)
+#define FUNC_SDCCCALL(x) (x->funcAttrs.sdcccall)
 #define FUNC_REGBANK(x) (x->funcAttrs.regbank)
 #define FUNC_HASSTACKPARM(x) (x->funcAttrs.hasStackParms)
 #define FUNC_ISINLINE(x) (x->funcAttrs.inlinereq)
@@ -458,6 +464,12 @@
 #define IFFUNC_ISOVERLAY(x) (IS_FUNC(x) && FUNC_ISOVERLAY(x))
 #define FUNC_ISSMALLC(x) (x->funcAttrs.smallc)
 #define IFFUNC_ISSMALLC(x) (IS_FUNC(x) && FUNC_ISSMALLC(x))
+#define FUNC_ISRAISONANCE(x) (x->funcAttrs.raisonance)
+#define IFFUNC_ISRAISONANCE(x) (IS_FUNC(x) && FUNC_ISRAISONANCE(x))
+#define FUNC_ISIAR(x) (x->funcAttrs.iar)
+#define IFFUNC_ISIAR(x) (IS_FUNC(x) && FUNC_ISIAR(x))
+#define FUNC_ISCOSMIC(x) (x->funcAttrs.cosmic)
+#define IFFUNC_ISCOSMIC(x) (IS_FUNC(x) && FUNC_ISCOSMIC(x))
 #define FUNC_ISZ88DK_FASTCALL(x) (x->funcAttrs.z88dk_fastcall)
 #define IFFUNC_ISZ88DK_FASTCALL(x) (IS_FUNC(x) && FUNC_ISZ88DK_FASTCALL(x))
 #define FUNC_ISZ88DK_CALLEE(x) (x->funcAttrs.z88dk_callee)
@@ -626,7 +638,8 @@
 /* Dims: shift left/shift right, BYTE/WORD/DWORD/QWORD, SIGNED/UNSIGNED */
 extern symbol *rlrr[2][4][2];
 
-extern symbol *memcpy_builtin;
+extern symbol *builtin_memcpy;
+extern symbol *nonbuiltin_memcpy;
 
 #define SCHARTYPE       multypes[0][0]
 #define UCHARTYPE       multypes[0][1]
@@ -667,8 +680,6 @@
 sym_link *reverseLink (sym_link *);
 symbol *copySymbol (const symbol *);
 symbol *copySymbolChain (const symbol *);
-void printSymChain (symbol *, int);
-void printStruct (structdef *, int);
 char *genSymName (long);
 sym_link *getSpec (sym_link *);
 int compStructSize (int, structdef *);
@@ -685,6 +696,7 @@
 sym_link *newCharLink ();
 sym_link *newLongLink ();
 sym_link *newBoolLink ();
+sym_link *newPtrDiffLink ();
 sym_link *newVoidLink ();
 int compareType (sym_link *, sym_link *);
 int compareTypeExact (sym_link *, sym_link *, long);
@@ -699,7 +711,7 @@
 symbol *getStructElement (structdef *, symbol *);
 sym_link *computeType (sym_link *, sym_link *, RESULT_TYPE, int);
 void processFuncPtrArgs (sym_link *);
-void processFuncArgs (symbol *);
+void processFuncArgs (symbol *, sym_link *);
 int isSymbolEqual (const symbol *, const symbol *);
 int powof2 (TYPE_TARGET_ULONG);
 void dbuf_printTypeChain (sym_link *, struct dbuf_s *);
@@ -726,6 +738,7 @@
 int isVolatile (sym_link * type);
 int isRestrict (sym_link * type);
 value *aggregateToPointer (value *);
+void leaveBlockScope (int block);
 
 
 extern char *nounName (sym_link *);     /* noun strings */
diff -Nru sdcc-4.0.0+dfsg/src/SDCCutil.c sdcc-4.2.0+dfsg/src/SDCCutil.c
--- sdcc-4.0.0+dfsg/src/SDCCutil.c	2020-01-10 21:45:20.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/SDCCutil.c	2022-02-03 09:32:48.000000000 +0000
@@ -96,7 +96,7 @@
               if (str > begin)
                 dbuf_append (&dbuf, begin, str - begin);
 
-              /* append additional beckslash */
+              /* append additional backslash */
               ++backshl;
 
               /* special handling if last chars before double quote are backslashes */
@@ -117,7 +117,7 @@
             }
           else if ('%' == *str)
             {
-              /* diseble env. variable expansion */
+              /* disable env. variable expansion */
               /* append the remaining characters */
               if (begin && str > begin)
                 dbuf_append (&dbuf, begin, str - begin);
@@ -233,6 +233,42 @@
 #endif
 }
 
+
+/** Escape string for string constants.
+    Returns dynamically allocated string, which should be free-ed.
+    TODO: Maybe handle other non-printable characters.
+*/
+char *
+string_escape (const char *str)
+{
+  struct dbuf_s dbuf;
+
+  dbuf_init (&dbuf, 128);
+
+  while (*str)
+    {
+      switch (*str)
+        {
+        case '\\': case '"':
+          dbuf_append_char (&dbuf, '\\');
+          dbuf_append_char (&dbuf, *str);
+          break;
+
+        case '\n':
+          dbuf_append_str (&dbuf, "\\n");
+          break;
+
+        default:
+          dbuf_append_char (&dbuf, *str);
+          break;
+        }
+      ++str;
+    }
+
+  return dbuf_detach_c_str (&dbuf);
+}
+
+
 /** Prints elements of the set to the file, each element on new line
 */
 void
@@ -283,7 +319,7 @@
   return new_list;
 }
 
-/** Given a set returns a string containing all of the strings seperated
+/** Given a set returns a string containing all of the strings separated
     by spaces. The returned string is on the heap.
 */
 const char *
@@ -536,7 +572,7 @@
                         if (*tmp != '\0')
                           {
                             if (sep)
-                              dbuf_append_char (&dbuf, ' ');    /* seperate it */
+                              dbuf_append_char (&dbuf, ' ');    /* separate it */
                             dbuf_append_str (&dbuf, tmp);
                             tmp++;
                             sep = 1;
@@ -555,7 +591,7 @@
           if (par && *par != '\0')
             {
               if (!first && sep)
-                dbuf_append_char (&dbuf, ' ');  /* seperate it */
+                dbuf_append_char (&dbuf, ' ');  /* separate it */
               dbuf_append_str (&dbuf, par);
               sep = 0;
             }
@@ -565,7 +601,7 @@
       if (*from != '\0')
         {
           if (!first && sep)
-            dbuf_append_char (&dbuf, ' ');      /* seperate it */
+            dbuf_append_char (&dbuf, ' ');      /* separate it */
           dbuf_append_str (&dbuf, from);
           sep = 0;
         }
@@ -839,8 +875,8 @@
 
 /*------------------------------------------------------------------*/
 /* universalEscape - process an hex constant of exactly four digits */
-/* return the hex value, throw a warning for illegal octal          */
-/* adjust src to point at the last proccesed char                   */
+/* return the hex value, throw an error warning for invalid hex     */
+/* adjust src to point at the last processed char                   */
 /*------------------------------------------------------------------*/
 
 unsigned long int
@@ -859,14 +895,14 @@
 
   for (digits = 0; digits < n; ++digits)
     {
-      if (**str >= '0' && **str <= '7')
+      if (**str >= '0' && **str <= '9')
         {
           value = (value << 4) + (**str - '0');
           ++*str;
         }
-      else if ((**str | 0x20) >= 'a' && (**str | 0x20) <= 'f')
+      else if (tolower((unsigned char)(**str)) >= 'a' && (tolower((unsigned char)(**str)) <= 'f'))
         {
-          value = (value << 4) + ((**str | 0x20) - 'a' + 10);
+          value = (value << 4) + (tolower((unsigned char)(**str)) - 'a' + 10);
           ++*str;
         }
       else
@@ -883,7 +919,7 @@
 /*------------------------------------------------------------------*/
 /* octalEscape - process an octal constant of max three digits      */
 /* return the octal value, throw a warning for illegal octal        */
-/* adjust src to point at the last proccesed char                   */
+/* adjust src to point at the last processed char                   */
 /*------------------------------------------------------------------*/
 
 unsigned long int
@@ -914,8 +950,8 @@
   Copies source string to a dynamically allocated buffer interpreting
   escape sequences and special characters
 
-  /param src  Buffer containing the source string with escape sequecnes
-  /param size Pointer to loction where the resulting buffer length is written
+  /param src  Buffer containing the source string with escape sequences
+  /param size Pointer to location where the resulting buffer length is written
   /return Dynamically allocated resulting buffer
 */
 
diff -Nru sdcc-4.0.0+dfsg/src/SDCCutil.h sdcc-4.2.0+dfsg/src/SDCCutil.h
--- sdcc-4.0.0+dfsg/src/SDCCutil.h	2017-10-27 11:53:14.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/SDCCutil.h	2022-02-02 20:45:33.000000000 +0000
@@ -39,6 +39,11 @@
  */
 char *shell_escape (const char *str);
 
+/** Escape string for string constants.
+ *  Returns dynamically allocated string, which should be free-ed.
+ */
+char *string_escape (const char *str);
+
 /** Prints elements of the set to the file, each element on new line
  */
 void fputStrSet (FILE * fp, set * list);
diff -Nru sdcc-4.0.0+dfsg/src/SDCCval.c sdcc-4.2.0+dfsg/src/SDCCval.c
--- sdcc-4.0.0+dfsg/src/SDCCval.c	2019-11-11 19:27:05.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/SDCCval.c	2022-02-03 09:32:48.000000000 +0000
@@ -129,7 +129,7 @@
           return FALSE;
         }
 
-      if (!IS_AST_LIT_VALUE (decorateType (resolveSymbols (iLoop->init.node), RESULT_TYPE_NONE)))
+      if (!IS_AST_LIT_VALUE (decorateType (resolveSymbols (iLoop->init.node), RESULT_TYPE_NONE, true)))
         {
           return FALSE;
         }
@@ -146,16 +146,26 @@
   iLoop = src ? src->init.deep : NULL;
   while (size--)
     {
-      double val = iLoop ? AST_FLOAT_VALUE (iLoop->init.node) : 0;
+      literalList ll = {0};
+      value *val = iLoop ? AST_VALUE (iLoop->init.node) : NULL;
+      if (val)
+        {
+          ll.isFloat = IS_FLOAT(val->type);
+          if (ll.isFloat)
+            ll.value.f64 = floatFromVal(val);
+          else
+            ll.value.ull = ullFromVal(val);
+        }
 
-      if (last && last->literalValue == val)
+      if (last && ((!last->isFloat && last->value.ull == ll.value.ull) ||
+                   (last->isFloat && last->value.f64 == ll.value.f64)))
         {
           last->count++;
         }
       else
         {
           newL = Safe_alloc (sizeof (literalList));
-          newL->literalValue = val;
+          *newL = ll;
           newL->count = 1;
           newL->next = NULL;
 
@@ -192,7 +202,7 @@
     {
       newL = Safe_alloc (sizeof (literalList));
 
-      newL->literalValue = src->literalValue;
+      *newL = *src;
       newL->count = src->count;
       newL->next = NULL;
 
@@ -308,7 +318,7 @@
     {
       if (ilist->type == INIT_NODE)
         {
-          ilist->init.node = decorateType (resolveSymbols (ilist->init.node), is_ptr ? RESULT_TYPE_INT : resultType);
+          ilist->init.node = decorateType (resolveSymbols (ilist->init.node), is_ptr ? RESULT_TYPE_INT : resultType, true);
         }
       else if (ilist->type == INIT_DEEP)
         {
@@ -500,7 +510,11 @@
 
   /* okay, allocate enough space */
   if (IS_ARRAY (type))
-    size = getNelements(type, ilist);
+    {
+      size = getNelements(type, ilist);
+      if (size == 0)
+        return NULL;
+    }
   else if (IS_STRUCT (type))
     {
       /* compute size from struct type. */
@@ -1158,6 +1172,54 @@
 }
 
 /*-----------------------------------------------------------------*/
+/* sepStrToUll - like stroull, but also handles digit separators   */
+/*-----------------------------------------------------------------*/
+static unsigned long long 
+sepStrToUll (const char *nptr, char **endptr, int base)
+{
+  wassert (base >= 2 && base <= 16);
+
+  unsigned long long ret = 0ull;
+  bool separated = false;
+
+  for(;;nptr++)
+    {
+      int next = nptr[0];
+
+      // Skip digit separators
+      if (next == '\'')
+        {
+          separated = true;
+          continue;
+        }
+      
+      // Assumes 0-9, a-f and A-F are consecutive in character set.
+      if (next >= 'a' && next <= 'f')
+        next = next - 'a' + 10;
+      else if (next >= 'A' && next <= 'F')
+        next = next - 'A' + 10;
+      else if (next >= '0' && next <= '9')
+        next = next - '0';
+      else
+        break;
+
+      if (!(next >= 0 && next < base))
+        break;
+        
+      ret *= base;
+      ret += next;
+    }
+
+  if(separated && !options.std_c2x)
+    werror (W_DIGIT_SEPARATOR_C23);
+
+  if (endptr) 
+    *endptr = (char *)nptr;
+
+  return(ret);
+}
+
+/*-----------------------------------------------------------------*/
 /* constIntVal - converts an integer constant into correct type    */
 /* See ISO C11, section 6.4.4.1 for the rules.                     */
 /*-----------------------------------------------------------------*/
@@ -1180,9 +1242,11 @@
   if (s[0] == '0')
     {
       if (s[1] == 'b' || s[1] == 'B')
-        llval = strtoull (s + 2, &p, 2);
+        llval = sepStrToUll (s + 2, &p, 2);
+      else if (s[1] == 'x' || s[1] == 'X')
+        llval = sepStrToUll (s + 2, &p, 16);
       else
-        llval = strtoull (s, &p, 0);
+        llval = sepStrToUll (s, &p, 8);
       dval = (double)(unsigned long long int) llval;
       decimal = FALSE;
     }
@@ -1190,10 +1254,17 @@
     {
       dval = strtod (s, &p);
       if (dval >= 0.0)
-        llval = strtoull (s, &p, 0);
+        {
+          llval = sepStrToUll (s, &p, 10);
+          dval = (double)(unsigned long long int) llval;
+        }
       else
-        llval = strtoll (s, &p, 0);
-      decimal = TRUE;
+        {
+          llval = sepStrToUll (s + 1, &p, 10);
+          llval = -llval;
+          dval = (double) llval;
+        }
+      decimal = true;
     }
 
   if (errno)
@@ -1408,19 +1479,24 @@
 /* constBoolVal - converts a BOOL constant to value                */
 /*-----------------------------------------------------------------*/
 value *
-constBoolVal (bool v)
+constBoolVal (bool v, bool reduceType)
 {
-  value *val = newValue ();     /* alloc space for value   */
-
-  val->type = val->etype = newLink (SPECIFIER); /* create the specifier */
-  SPEC_SCLS (val->type) = S_LITERAL;
-  SPEC_CONST (val->type) = 1;
-
-  SPEC_NOUN (val->type) = (bit) ? V_BIT : V_BOOL;
-
-  SPEC_CVAL (val->type).v_uint = (unsigned int) v;
-
-  return val;
+  if (reduceType)
+    {
+      value *val = newValue ();     /* alloc space for value   */
+      val->type = val->etype = newLink (SPECIFIER); /* create the specifier */
+      SPEC_SCLS (val->type) = S_LITERAL;
+      SPEC_CONST (val->type) = 1;
+    
+      SPEC_NOUN (val->type) = (bit) ? V_BIT : V_BOOL;
+    
+      SPEC_CVAL (val->type).v_uint = (unsigned int) v;
+      return val;
+    }
+  else
+    {
+      return constIntVal (v ? "1" : "0");
+    }
 }
 
 // TODO: Move this function to SDCCutil?
@@ -1523,11 +1599,11 @@
   SPEC_SCLS (val->etype) = S_LITERAL;
   SPEC_CONST (val->etype) = 1;
 
-  // Convert input string (mixed UTF-8 and UTF-32) to UTF-8 first (handling all escape sequences, etc).
-  utf_8 = copyStr (s[0] == '"' ? s : s + 1, &utf_8_size);
-
-  if (s[0] == '"') // UTF-8 string literal (any prefix u8 or L in the source would already have been stripped by earlier stages)
+  if (s[0] == '"' || s[0] == 'u' && s[1] == '8' && s[2] == '"') // UTF-8 string literal
     {
+      // Convert input string (mixed UTF-8 and UTF-32) to UTF-8 (handling all escape sequences, etc).
+      utf_8 = copyStr (s[0] == '"' ? s : s + 2, &utf_8_size);
+
       SPEC_NOUN (val->etype) = V_CHAR;
       SPEC_USIGN (val->etype) = !options.signed_char;
       val->etype->select.s.b_implicit_sign = true;
@@ -1536,6 +1612,9 @@
     }
   else
     {
+      // Convert input string (mixed UTF-8 and UTF-32) to UTF-8 first (handling all escape sequences, etc).
+      utf_8 = copyStr (s + 1, &utf_8_size);
+      
       size_t utf_32_size;
       // Convert to UTF-32 next, since converting UTF-32 to UTF-16 is easier than UTF-8 to UTF-16.
       const TYPE_UDWORD *utf_32 = utf_32_from_utf_8 (&utf_32_size, utf_8, utf_8_size);
@@ -1854,7 +1933,7 @@
 /* ulFromVal - value to unsigned long conversion                    */
 /*------------------------------------------------------------------*/
 unsigned long
-ulFromVal (value *val)
+ulFromVal (const value *val)
 {
   if (!val)
     return 0;
@@ -2105,15 +2184,17 @@
 }
 
 /*------------------------------------------------------------------*/
-/* csdOfVal - return 0 if the value can be represented as csd       */
+/* csdOfVal - return 0 if the value can be represented as           */
+/* canonical signed digit. Useful for generating                    */
+/* shift / add / sub code sequences for multiplication by literals. */
 /* topbit  - highest nonzero bit in csd                             */
 /* nonzero - number of nonzero bits in csd                          */
 /* csd_add - positive bits in csd                                   */
 /* csd_sub - negative bits in csd                                   */
 /*------------------------------------------------------------------*/
-int csdOfVal (int *topbit, int *nonzero, unsigned long long *csd_add, unsigned long long *csd_sub, value *val)
+int csdOfVal (int *topbit, int *nonzero, unsigned long long *csd_add, unsigned long long *csd_sub, value *val, unsigned long long mask)
 {
-  unsigned long long binary = ullFromVal (val);
+  unsigned long long binary = ullFromVal (val) & mask;
   bool gamma, theta, a;
   int bit, next;
 
@@ -2217,7 +2298,7 @@
 /* valUnaryPM - does the unary +/- operation on a constant          */
 /*------------------------------------------------------------------*/
 value *
-valUnaryPM (value * val)
+valUnaryPM (value * val, bool reduceType)
 {
   /* depending on type */
   if (SPEC_NOUN (val->etype) == V_FLOAT)
@@ -2251,7 +2332,8 @@
           SPEC_USIGN (val->etype) = 0;
           SPEC_NOUN (val->etype) = V_INT;
         }
-      return cheapestVal (val);
+      if (reduceType)
+        return cheapestVal (val);
     }
   return val;
 }
@@ -2260,7 +2342,7 @@
 /* valueComplement - complements a constant                         */
 /*------------------------------------------------------------------*/
 value *
-valComplement (value * val)
+valComplement (value * val, bool reduceType)
 {
   /* depending on type */
   if (SPEC_LONGLONG (val->etype))
@@ -2290,7 +2372,8 @@
           SPEC_USIGN (val->etype) = 0;
           SPEC_NOUN (val->etype) = V_INT;
         }
-      return cheapestVal (val);
+      if (reduceType)
+        return cheapestVal (val);
     }
   return val;
 }
@@ -2299,7 +2382,7 @@
 /* valueNot - complements a constant                                */
 /*------------------------------------------------------------------*/
 value *
-valNot (value * val)
+valNot (value * val, bool reduceType)
 {
   /* depending on type */
   if (SPEC_LONGLONG (val->etype))
@@ -2324,12 +2407,22 @@
         SPEC_CVAL (val->etype).v_int = !SPEC_CVAL (val->etype).v_int;
 
     }
+    
   /* ANSI: result type is int, value is 0 or 1 */
-  /* sdcc will hold this in an 'unsigned char' */
-  SPEC_USIGN (val->etype) = 1;
+  /* If reduction is allowed SDCC will hold this in an 'unsigned char' */
+  if (reduceType)
+    {
+      SPEC_USIGN (val->etype) = 1;
+      SPEC_NOUN (val->etype) = V_CHAR;
+    }
+  else
+    {
+      SPEC_USIGN (val->etype) = 0;
+      SPEC_NOUN (val->etype) = V_INT;
+    }
   SPEC_LONG (val->etype) = 0;
   SPEC_LONGLONG (val->type) = 0;
-  SPEC_NOUN (val->etype) = V_CHAR;
+
   return val;
 }
 
@@ -2337,7 +2430,7 @@
 /* valMult - multiply constants                                     */
 /*------------------------------------------------------------------*/
 value *
-valMult (value * lval, value * rval)
+valMult (value * lval, value * rval, bool reduceType)
 {
   value *val;
 
@@ -2372,14 +2465,15 @@
       if (l != (TYPE_TARGET_INT) l)
         werror (W_INT_OVL);
     }
-  return cheapestVal (val);
+
+  return reduceType ? cheapestVal (val) : val;
 }
 
 /*------------------------------------------------------------------*/
 /* valDiv  - Divide   constants                                     */
 /*------------------------------------------------------------------*/
 value *
-valDiv (value * lval, value * rval)
+valDiv (value * lval, value * rval, bool reduceType)
 {
   value *val;
 
@@ -2419,14 +2513,14 @@
       else
         SPEC_CVAL (val->type).v_int = (TYPE_TARGET_INT) ulFromVal (lval) / (TYPE_TARGET_INT) ulFromVal (rval);
     }
-  return cheapestVal (val);
+  return reduceType ? cheapestVal (val) : val;
 }
 
 /*------------------------------------------------------------------*/
 /* valMod  - Modulus  constants                                     */
 /*------------------------------------------------------------------*/
 value *
-valMod (value * lval, value * rval)
+valMod (value * lval, value * rval, bool reduceType)
 {
   value *val;
 
@@ -2462,14 +2556,64 @@
       else
         SPEC_CVAL (val->type).v_int = (TYPE_TARGET_INT) ulFromVal (lval) % (TYPE_TARGET_INT) ulFromVal (rval);
     }
-  return cheapestVal (val);
+  return reduceType ? cheapestVal (val) : val;
+}
+
+/*------------------------------------------------------------------*/
+/* valZeroResult - constant zero with type from two values          */
+/*------------------------------------------------------------------*/
+value *
+valZeroResultFromOp (sym_link * type1, sym_link * type2, int op, bool reduceType)
+{
+  value *val;
+
+  /* create a new value */
+  val = newValue ();
+  val->type = computeType (type1, type2, RESULT_TYPE_INT, op);
+  val->etype = getSpec (val->type);
+  // If type reduction is not allowed, make sure we get integer promotion for smaller types
+  if(!reduceType && IS_INTEGRAL (val->etype) && bitsForType (val->etype) < INTSIZE * 8)
+    {
+      SPEC_NOUN (val->etype) = V_INT;
+      SPEC_USIGN (val->etype) = 0;
+    }
+  SPEC_SCLS (val->etype) = S_LITERAL;
+
+  if (!IS_SPEC (val->type))
+    SPEC_CVAL (val->etype).v_ulong = 0;
+  else if (IS_FLOAT (val->type))
+    SPEC_CVAL (val->type).v_float = 0;
+  else if (IS_FIXED16X16 (val->type))
+    SPEC_CVAL (val->type).v_fixed16x16 = 0;
+  else if (SPEC_LONGLONG (val->type))
+    {
+      if (SPEC_USIGN (val->type))
+        SPEC_CVAL (val->type).v_ulonglong = 0;
+      else
+        SPEC_CVAL (val->type).v_longlong = 0;
+    }
+  else if (SPEC_LONG (val->type))
+    {
+      if (SPEC_USIGN (val->type))
+        SPEC_CVAL (val->type).v_ulong = 0;
+      else
+        SPEC_CVAL (val->type).v_long = 0;
+    }
+  else
+    {
+      if (SPEC_USIGN (val->type))
+        SPEC_CVAL (val->type).v_uint = 0;
+      else
+        SPEC_CVAL (val->type).v_int = 0;
+    }
+  return reduceType ? cheapestVal (val) : val;
 }
 
 /*------------------------------------------------------------------*/
 /* valPlus - Addition constants                                     */
 /*------------------------------------------------------------------*/
 value *
-valPlus (value * lval, value * rval)
+valPlus (value * lval, value * rval, bool reduceType)
 {
   value *val;
 
@@ -2506,14 +2650,14 @@
       else
         SPEC_CVAL (val->type).v_int = (TYPE_TARGET_INT) ulFromVal (lval) + (TYPE_TARGET_INT) ulFromVal (rval);
     }
-  return cheapestVal (val);
+  return reduceType ? cheapestVal (val) : val;
 }
 
 /*------------------------------------------------------------------*/
 /* valMinus - Addition constants                                    */
 /*------------------------------------------------------------------*/
 value *
-valMinus (value * lval, value * rval)
+valMinus (value * lval, value * rval, bool reduceType)
 {
   value *val;
 
@@ -2550,14 +2694,14 @@
       else
         SPEC_CVAL (val->type).v_int = (TYPE_TARGET_INT) ulFromVal (lval) - (TYPE_TARGET_INT) ulFromVal (rval);
     }
-  return cheapestVal (val);
+  return reduceType ? cheapestVal (val) : val;
 }
 
 /*------------------------------------------------------------------*/
 /* valShift - Shift left or right                                   */
 /*------------------------------------------------------------------*/
 value *
-valShift (value * lval, value * rval, int lr)
+valShift (value * lval, value * rval, int lr, bool reduceType)
 {
   value *val;
 
@@ -2621,14 +2765,14 @@
             (TYPE_TARGET_INT) ulFromVal (lval) >> (TYPE_TARGET_ULONG) ulFromVal (rval);
         }
     }
-  return cheapestVal (val);
+  return reduceType ? cheapestVal (val) : val;
 }
 
 /*------------------------------------------------------------------*/
 /* valCompare - Compares two literal                                */
 /*------------------------------------------------------------------*/
 value *
-valCompare (value * lval, value * rval, int ctype)
+valCompare (value * lval, value * rval, int ctype, bool reduceType)
 {
   value *val;
 
@@ -2636,9 +2780,18 @@
   val = newValue ();
   val->type = val->etype = newCharLink ();
   val->type->xclass = SPECIFIER;
-  SPEC_NOUN (val->type) = V_CHAR;       /* type is char */
-  SPEC_USIGN (val->type) = 1;
   SPEC_SCLS (val->type) = S_LITERAL;    /* will remain literal */
+  
+  if (reduceType)
+    {
+      SPEC_NOUN (val->type) = V_CHAR;       /* type is char */
+      SPEC_USIGN (val->type) = 1;
+    }
+  else
+    {
+      SPEC_NOUN (val->type) = V_INT;
+      SPEC_USIGN (val->type) = 0;
+    }
 
   switch (ctype)
     {
@@ -2676,9 +2829,9 @@
           l = (TYPE_TARGET_ULONGLONG) ullFromVal (lval);
           r = (TYPE_TARGET_ULONGLONG) ullFromVal (rval);
           /* In order to correctly compare 'signed int' and 'unsigned int' it's
-             neccessary to strip them to 16 bit.
+             necessary to strip them to 16 bit.
              Literals are reduced to their cheapest type, therefore left and
-             right might have different types. It's neccessary to find a
+             right might have different types. It's necessary to find a
              common type: int (used for char too) or long */
           if (!IS_LONGLONG (lval->etype) && !IS_LONGLONG (rval->etype))
             {
@@ -2710,9 +2863,9 @@
           l = (TYPE_TARGET_ULONGLONG) ullFromVal (lval);
           r = (TYPE_TARGET_ULONGLONG) ullFromVal (rval);
           /* In order to correctly compare 'signed int' and 'unsigned int' it's
-             neccessary to strip them to 16 bit.
+             necessary to strip them to 16 bit.
              Literals are reduced to their cheapest type, therefore left and
-             right might have different types. It's neccessary to find a
+             right might have different types. It's necessary to find a
              common type: int (used for char too) or long */
           if (!IS_LONGLONG (lval->etype) && !IS_LONGLONG (rval->etype))
             {
@@ -2737,7 +2890,7 @@
 /* valBitwise - Bitwise operation                                   */
 /*------------------------------------------------------------------*/
 value *
-valBitwise (value * lval, value * rval, int op)
+valBitwise (value * lval, value * rval, int op, bool reduceType)
 {
   value *val;
 
@@ -2823,14 +2976,14 @@
       break;
     }
 
-  return cheapestVal (val);
+  return reduceType ? cheapestVal (val) : val;
 }
 
 /*------------------------------------------------------------------*/
 /* valAndOr   - Generates code for and / or operation               */
 /*------------------------------------------------------------------*/
 value *
-valLogicAndOr (value * lval, value * rval, int op)
+valLogicAndOr (value * lval, value * rval, int op, bool reduceType)
 {
   value *val;
 
@@ -2839,7 +2992,14 @@
   val->type = val->etype = newCharLink ();
   val->type->xclass = SPECIFIER;
   SPEC_SCLS (val->type) = S_LITERAL;    /* will remain literal */
-  SPEC_USIGN (val->type) = 1;
+  
+  if (reduceType)
+      SPEC_USIGN (val->type) = 1;
+  else
+    {
+      SPEC_NOUN (val->type) = V_INT;
+      SPEC_USIGN (val->type) = 0;
+    }
 
   switch (op)
     {
@@ -2866,6 +3026,8 @@
 
   if (!dtype)
     return NULL;
+  if ((fval > 0x7ffffffful) || (-fval > 0x7ffffffful))
+    l = (unsigned long)llval;
 
   val = newValue ();
   if (dtype)
diff -Nru sdcc-4.0.0+dfsg/src/SDCCval.h sdcc-4.2.0+dfsg/src/SDCCval.h
--- sdcc-4.0.0+dfsg/src/SDCCval.h	2018-03-29 09:38:43.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/SDCCval.h	2022-02-03 09:32:48.000000000 +0000
@@ -40,7 +40,12 @@
 
 typedef struct literalList
 {
-  double literalValue;
+  bool isFloat;
+  union {
+    unsigned long long ull;
+    double f64;
+  }
+  value;
   unsigned count;
   struct literalList *next;
 } literalList;
@@ -111,7 +116,7 @@
 value *constIntVal (const char *);
 value *constCharacterVal (unsigned long v, char type);
 value *constCharVal (unsigned char v);
-value *constBoolVal (bool v);
+value *constBoolVal (bool v, bool reduceType);
 value *reverseVal (value *);
 value *reverseValWithType (value *);
 value *copyValue (value *);
@@ -122,7 +127,7 @@
 value *symbolVal (symbol *);
 void printVal (value *);
 double floatFromVal (value *);
-unsigned long ulFromVal (value *);
+unsigned long ulFromVal (const value *);
 unsigned long long ullFromVal (value *);
 
 /* convert a fixed16x16 type to double */
@@ -133,18 +138,19 @@
 
 CCR_RESULT checkConstantRange (sym_link * var, sym_link * lit, int op, bool exchangeOps);
 value *array2Ptr (value *);
-value *valUnaryPM (value *);
-value *valComplement (value *);
-value *valNot (value *);
-value *valMult (value *, value *);
-value *valDiv (value *, value *);
-value *valMod (value *, value *);
-value *valPlus (value *, value *);
-value *valMinus (value *, value *);
-value *valShift (value *, value *, int);
-value *valCompare (value *, value *, int);
-value *valBitwise (value *, value *, int);
-value *valLogicAndOr (value *, value *, int);
+value *valUnaryPM (value *, bool reduceType);
+value *valComplement (value *, bool reduceType);
+value *valNot (value *, bool reduceType);
+value *valMult (value *, value *, bool reduceType);
+value *valDiv (value *, value *, bool reduceType);
+value *valMod (value *, value *, bool reduceType);
+value *valZeroResultFromOp (sym_link * type1, sym_link * type2, int op, bool reduceType);
+value *valPlus (value *, value *, bool reduceType);
+value *valMinus (value *, value *, bool reduceType);
+value *valShift (value *, value *, int, bool reduceType);
+value *valCompare (value *, value *, int, bool reduceType);
+value *valBitwise (value *, value *, int, bool reduceType);
+value *valLogicAndOr (value *, value *, int, bool reduceType);
 value *valCastLiteral (sym_link *, double, TYPE_TARGET_ULONGLONG);
 value *valueFromLit (double);
 initList *newiList (int, void *);
@@ -170,7 +176,7 @@
 literalList *copyLiteralList (literalList * src);
 unsigned long double2ul (double val);
 unsigned char byteOfVal (value *, int);
-int csdOfVal (int *topbit, int *nonzero, unsigned long long *csd_add, unsigned long long *csd_sub, value *val);
+int csdOfVal (int *topbit, int *nonzero, unsigned long long *csd_add, unsigned long long *csd_sub, value *val, unsigned long long mask);
 int isEqualVal (value *, int);
 TYPE_TARGET_ULONGLONG ullFromLit (sym_link * lit);
 value * valRecastLitVal (sym_link * dtype, value * val);
diff -Nru sdcc-4.0.0+dfsg/src/SDCC.y sdcc-4.2.0+dfsg/src/SDCC.y
--- sdcc-4.0.0+dfsg/src/SDCC.y	2020-01-13 11:56:57.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/SDCC.y	2021-08-08 17:13:19.000000000 +0000
@@ -26,6 +26,7 @@
 #include 
 #include 
 #include "SDCCglobl.h"
+#include "SDCCattr.h"
 #include "SDCCsymt.h"
 #include "SDCChasht.h"
 #include "SDCCval.h"
@@ -72,6 +73,7 @@
 %expect 11
 
 %union {
+    attribute  *attr;       /* attribute                              */
     symbol     *sym;        /* symbol table pointer                   */
     structdef  *sdef;       /* structure definition                   */
     char       yychar[SDCC_NAME_MAX+1];
@@ -93,7 +95,7 @@
 %token  MUL_ASSIGN DIV_ASSIGN MOD_ASSIGN ADD_ASSIGN
 %token  SUB_ASSIGN LEFT_ASSIGN RIGHT_ASSIGN AND_ASSIGN
 %token  XOR_ASSIGN OR_ASSIGN
-%token TYPEDEF EXTERN STATIC AUTO REGISTER CODE EEPROM INTERRUPT SFR SFR16 SFR32 ADDRESSMOD STATIC_ASSERT
+%token TYPEDEF EXTERN STATIC THREAD_LOCAL AUTO REGISTER CODE EEPROM INTERRUPT SFR SFR16 SFR32 ADDRESSMOD STATIC_ASSERT
 %token AT SBIT REENTRANT USING  XDATA DATA IDATA PDATA VAR_ARGS CRITICAL
 %token NONBANKED BANKED SHADOWREGS SD_WPARAM
 %token SD_BOOL SD_CHAR SD_SHORT SD_INT SD_LONG SIGNED UNSIGNED SD_FLOAT DOUBLE FIXED16X16 SD_CONST VOLATILE SD_VOID BIT
@@ -101,16 +103,17 @@
 %token CASE DEFAULT IF ELSE SWITCH WHILE DO FOR GOTO CONTINUE BREAK RETURN
 %token NAKED JAVANATIVE OVERLAY TRAP
 %token  STRING_LITERAL INLINEASM
-%token IFX ADDRESS_OF GET_VALUE_AT_ADDRESS SET_VALUE_AT_ADDRESS SPIL UNSPIL GETHBIT GETABIT GETBYTE GETWORD
+%token IFX ADDRESS_OF GET_VALUE_AT_ADDRESS SET_VALUE_AT_ADDRESS SPIL UNSPIL GETABIT GETBYTE GETWORD
 %token BITWISEAND UNARYMINUS IPUSH IPOP PCALL  ENDFUNCTION JUMPTABLE
 %token RRC RLC
 %token CAST CALL PARAM NULLOP BLOCK LABEL RECEIVE SEND ARRAYINIT
-%token DUMMY_READ_VOLATILE ENDCRITICAL SWAP INLINE NORETURN RESTRICT SMALLC PRESERVES_REGS Z88DK_FASTCALL Z88DK_CALLEE ALIGNAS Z88DK_SHORTCALL Z88DK_PARAMS_OFFSET
+%token DUMMY_READ_VOLATILE ENDCRITICAL SWAP INLINE NORETURN RESTRICT SMALLC RAISONANCE IAR COSMIC SDCCCALL PRESERVES_REGS Z88DK_FASTCALL Z88DK_CALLEE ALIGNAS Z88DK_SHORTCALL Z88DK_PARAMS_OFFSET
 %token GENERIC GENERIC_ASSOC_LIST GENERIC_ASSOCIATION
 %token ASM
 
 %type  Interrupt_storage
-%type  identifier declarator declarator2 direct_declarator array_declarator enumerator_list enumerator
+%type  attribute_specifier_sequence attribute_specifier_sequence_opt attribute_specifier attribute_list attribute
+%type  identifier attribute_token declarator declarator2 direct_declarator array_declarator enumerator_list enumerator
 %type  member_declarator function_declarator
 %type  member_declarator_list member_declaration member_declaration_list
 %type  declaration init_declarator_list init_declarator
@@ -118,11 +121,11 @@
 %type  declaration_after_statement
 %type  declarator2_function_attributes while do for critical
 %type  addressmod
-%type  pointer type_specifier_list type_specifier_list_ type_specifier type_qualifier_list type_qualifier type_name
+%type  pointer specifier_qualifier_list type_specifier_list_ type_specifier_qualifier type_specifier type_qualifier_list type_qualifier type_name
 %type  storage_class_specifier struct_or_union_specifier function_specifier alignment_specifier
 %type  declaration_specifiers declaration_specifiers_ sfr_reg_bit sfr_attributes
 %type  function_attribute function_attributes enum_specifier
-%type  abstract_declarator direct_abstract_declarator array_abstract_declarator function_abstract_declarator
+%type  abstract_declarator direct_abstract_declarator direct_abstract_declarator_opt array_abstract_declarator function_abstract_declarator
 %type  unqualified_pointer
 %type  parameter_type_list parameter_list parameter_declaration opt_assign_expr
 %type  stag opt_stag
@@ -204,6 +207,7 @@
                           werror(E_COMPOUND_LITERALS_C99);
 
                         /* TODO: implement compound literals (C99) */
+                        $$ = newAst_VALUE (valueFromLit (0));
                       }
    | '(' type_name ')' '{' initializer_list ',' '}'
                       {
@@ -211,6 +215,7 @@
                           werror(E_COMPOUND_LITERALS_C99);
 
                         /* TODO: implement compound literals (C99) */
+                        $$ = newAst_VALUE (valueFromLit (0));
                       }
    ;
 
@@ -237,6 +242,9 @@
    | ALIGNOF '(' type_name ')'{ $$ = newAst_VALUE (alignofOp ($3)); }
    | TYPEOF unary_expr        { $$ = newNode (TYPEOF, NULL, $2); }
    | OFFSETOF '(' type_name ',' offsetof_member_designator ')' { $$ = offsetofOp($3, $5); }
+   | RLC unary_expr           { $$ = newNode (RLC, $2, NULL); }
+   | RRC unary_expr           { $$ = newNode (RRC, $2, NULL); }
+   | SWAP unary_expr          { $$ = newNode (SWAP, $2, NULL); }
    ;
 
 unary_operator
@@ -324,7 +332,7 @@
 
 assignment_expr
    : conditional_expr
-   | cast_expr assignment_operator assignment_expr
+   | unary_expr assignment_operator assignment_expr
                      {
 
                              switch ($2) {
@@ -477,11 +485,11 @@
      /* find the spec and replace it      */
      $$ = mergeDeclSpec($1, $2, "storage_class_specifier declaration_specifiers - skipped");
    }
-   | type_specifier                                 { $$ = $1; }
-   | type_specifier declaration_specifiers_         {
+   | type_specifier_qualifier                       { $$ = $1; }
+   | type_specifier_qualifier declaration_specifiers_ {
      /* if the decl $2 is not a specifier */
      /* find the spec and replace it      */
-     $$ = mergeDeclSpec($1, $2, "type_specifier declaration_specifiers - skipped");
+     $$ = mergeDeclSpec($1, $2, "type_specifier_qualifier declaration_specifiers - skipped");
    }
    | function_specifier                             { $$ = $1; }
    | function_specifier declaration_specifiers_     {
@@ -489,12 +497,6 @@
      /* find the spec and replace it      */
      $$ = mergeDeclSpec($1, $2, "function_specifier declaration_specifiers - skipped");
    }
-   | alignment_specifier                            { $$ = $1; }
-   | alignment_specifier declaration_specifiers_    {
-     /* if the decl $2 is not a specifier */
-     /* find the spec and replace it      */
-     $$ = mergeDeclSpec($1, $2, "alignment_specifier declaration_specifiers - skipped");
-   }
    ;
 
 init_declarator_list
@@ -524,6 +526,11 @@
                   $$ = newLink (SPECIFIER);
                   SPEC_STAT($$) = 1;
                }
+   | THREAD_LOCAL
+               {
+                  $$ = 0;
+                  werror(E_THREAD_LOCAL);
+               }
    | AUTO      {
                   $$ = newLink (SPECIFIER);
                   SPEC_SCLS($$) = S_AUTO;
@@ -535,10 +542,9 @@
    ;
 
 type_specifier
-   : type_qualifier { $$ = $1; }
-   | SD_BOOL   {
+   : SD_VOID   {
                   $$=newLink(SPECIFIER);
-                  SPEC_NOUN($$) = V_BOOL;
+                  SPEC_NOUN($$) = V_VOID;
                   ignoreTypedefType = 1;
                }
    | SD_CHAR   {
@@ -555,12 +561,17 @@
                   $$=newLink(SPECIFIER);
                   SPEC_NOUN($$) = V_INT;
                   ignoreTypedefType = 1;
-               }
+               }              
    | SD_LONG   {
                   $$=newLink(SPECIFIER);
                   SPEC_LONG($$) = 1;
                   ignoreTypedefType = 1;
                }
+   | SD_FLOAT  {
+                  $$=newLink(SPECIFIER);
+                  SPEC_NOUN($$) = V_FLOAT;
+                  ignoreTypedefType = 1;
+               }
    | SIGNED    {
                   $$=newLink(SPECIFIER);
                   $$->select.s.b_signed = 1;
@@ -571,16 +582,31 @@
                   SPEC_USIGN($$) = 1;
                   ignoreTypedefType = 1;
                }
-   | SD_VOID   {
-                  $$=newLink(SPECIFIER);
-                  SPEC_NOUN($$) = V_VOID;
-                  ignoreTypedefType = 1;
-               }
-   | SD_FLOAT  {
+   | SD_BOOL   {
                   $$=newLink(SPECIFIER);
-                  SPEC_NOUN($$) = V_FLOAT;
+                  SPEC_NOUN($$) = V_BOOL;
                   ignoreTypedefType = 1;
                }
+   | struct_or_union_specifier  {
+                                   uselessDecl = FALSE;
+                                   $$ = $1;
+                                   ignoreTypedefType = 1;
+                                }
+   | enum_specifier     {
+                           cenum = NULL;
+                           uselessDecl = FALSE;
+                           ignoreTypedefType = 1;
+                           $$ = $1;
+                        }       
+   | TYPE_NAME
+         {
+            symbol *sym;
+            sym_link *p;
+            sym = findSym(TypedefTab,NULL,$1);
+            $$ = p = copyLinkChain(sym ? sym->type : NULL);
+            SPEC_TYPEDEF(getSpec(p)) = 0;
+            ignoreTypedefType = 1;
+         }            
    | FIXED16X16 {
                   $$=newLink(SPECIFIER);
                   SPEC_NOUN($$) = V_FIXED16X16;
@@ -601,42 +627,23 @@
                   /* now get the abs addr from value */
                   SPEC_ADDR($$) = (unsigned int) ulFromVal(constExprValue($2,TRUE));
                }
-   | struct_or_union_specifier  {
-                                   uselessDecl = FALSE;
-                                   $$ = $1;
-                                   ignoreTypedefType = 1;
-                                }
-   | enum_specifier     {
-                           cenum = NULL;
-                           uselessDecl = FALSE;
-                           ignoreTypedefType = 1;
-                           $$ = $1;
-                        }
-   | TYPE_NAME
-         {
-            symbol *sym;
-            sym_link *p;
-            sym = findSym(TypedefTab,NULL,$1);
-            $$ = p = copyLinkChain(sym ? sym->type : NULL);
-            SPEC_TYPEDEF(getSpec(p)) = 0;
-            ignoreTypedefType = 1;
-         }
-   | sfr_reg_bit
-   ;
+
+
+   | sfr_reg_bit;
 
 struct_or_union_specifier
-   : struct_or_union opt_stag
+   : struct_or_union attribute_specifier_sequence_opt opt_stag
         {
           structdef *sdef;
 
-          if (! $2->tagsym)
+          if (! $3->tagsym)
             {
               /* no tag given, so new struct def for current scope */
-              addSym (StructTab, $2, $2->tag, $2->level, currBlockno, 0);
+              addSym (StructTab, $3, $3->tag, $3->level, currBlockno, 0);
             }
           else
             {
-              sdef = findSymWithBlock (StructTab, $2->tagsym, currBlockno, NestLevel);
+              sdef = findSymWithBlock (StructTab, $3->tagsym, currBlockno, NestLevel);
               if (sdef)
                 {
                   /* Error if a complete type already defined in this scope */
@@ -644,37 +651,37 @@
                     {
                       if (sdef->fields)
                         {
-                          werror(E_STRUCT_REDEF, $2->tag);
+                          werror(E_STRUCT_REDEF, $3->tag);
                           werrorfl(sdef->tagsym->fileDef, sdef->tagsym->lineDef, E_PREVIOUS_DEF);
                         }
                       else
                         {
-                          $2 = sdef; /* We are completing an incomplete type */
+                          $3 = sdef; /* We are completing an incomplete type */
                         }
                     }
                   else
                     {
                       /* There is an existing struct def in an outer scope. */
                       /* Create new struct def for current scope */
-                      addSym (StructTab, $2, $2->tag, $2->level, currBlockno, 0);
+                      addSym (StructTab, $3, $3->tag, $3->level, currBlockno, 0);
                     }
                 }
               else
                {
                  /* There is no existing struct def at all. */
                  /* Create new struct def for current scope */
-                 addSym (StructTab, $2, $2->tag, $2->level, currBlockno, 0);
+                 addSym (StructTab, $3, $3->tag, $3->level, currBlockno, 0);
                }
             }
 
-          if (!$2->type)
+          if (!$3->type)
             {
-              $2->type = $1;
+              $3->type = $1;
             }
           else
             {
-              if ($2->type != $1)
-                  werror(E_BAD_TAG, $2->tag, $1==STRUCT ? "struct" : "union");
+              if ($3->type != $1)
+                  werror(E_BAD_TAG, $3->tag, $1==STRUCT ? "struct" : "union");
             }
         }
    '{' member_declaration_list '}'
@@ -683,7 +690,7 @@
           symbol *sym, *dsym;
 
           // check for errors in structure members
-          for (sym=$5; sym; sym=sym->next)
+          for (sym=$6; sym; sym=sym->next)
             {
               if (IS_ABSOLUTE(sym->etype))
                 {
@@ -708,8 +715,8 @@
             }
 
           /* Create a structdef   */
-          sdef = $2;
-          sdef->fields = reverseSyms($5);        /* link the fields */
+          sdef = $3;
+          sdef->fields = reverseSyms($6);        /* link the fields */
           sdef->size = compStructSize($1, sdef); /* update size of  */
           promoteAnonStructs ($1, sdef);
 
@@ -718,31 +725,31 @@
           SPEC_NOUN($$) = V_STRUCT;
           SPEC_STRUCT($$)= sdef;
         }
-   | struct_or_union stag
+   | struct_or_union attribute_specifier_sequence_opt stag
         {
           structdef *sdef;
 
-          sdef = findSymWithBlock (StructTab, $2->tagsym, currBlockno, NestLevel);
+          sdef = findSymWithBlock (StructTab, $3->tagsym, currBlockno, NestLevel);
 
           if (sdef)
-            $2 = sdef;
+            $3 = sdef;
           else
             {
               /* new struct def for current scope */
-              addSym (StructTab, $2, $2->tag, $2->level, currBlockno, 0);
+              addSym (StructTab, $3, $3->tag, $3->level, currBlockno, 0);
             }
           $$ = newLink(SPECIFIER);
           SPEC_NOUN($$) = V_STRUCT;
-          SPEC_STRUCT($$) = $2;
+          SPEC_STRUCT($$) = $3;
 
-          if (!$2->type)
+          if (!$3->type)
             {
-              $2->type = $1;
+              $3->type = $1;
             }
           else
             {
-              if ($2->type != $1)
-                  werror(E_BAD_TAG, $2->tag, $1==STRUCT ? "struct" : "union");
+              if ($3->type != $1)
+                  werror(E_BAD_TAG, $3->tag, $1==STRUCT ? "struct" : "union");
             }
         }
    ;
@@ -767,13 +774,13 @@
    ;
 
 member_declaration
-   : type_specifier_list member_declarator_list ';'
+   : attribute_specifier_sequence_opt specifier_qualifier_list member_declarator_list ';'
         {
           /* add this type to all the symbols */
           symbol *sym;
-          for ( sym = $2; sym != NULL; sym = sym->next )
+          for ( sym = $3; sym != NULL; sym = sym->next )
             {
-              sym_link *btype = copyLinkChain($1);
+              sym_link *btype = copyLinkChain($2);
 
               pointerTypes(sym->type, btype);
               if (!sym->type)
@@ -787,10 +794,16 @@
               checkTypeSanity(sym->etype, sym->name);
             }
           ignoreTypedefType = 0;
-          $$ = $2;
+          $$ = $3;
         }
    ;
 
+type_specifier_qualifier
+   : type_specifier      { $$ = $1; }
+   | type_qualifier      { $$ = $1; }
+   | alignment_specifier { $$ = $1; }
+   ;
+
 member_declarator_list
    : member_declarator
    | member_declarator_list ',' member_declarator
@@ -835,8 +848,38 @@
           $$ = newEnumType ($3);
           SPEC_SCLS(getSpec($$)) = 0;
         }
-   | ENUM identifier '{' enumerator_list '}'
+    | ENUM '{' enumerator_list ',' '}'
+        {
+          if (!options.std_c99)
+            werror (E_ENUM_COMMA_C99);
+          $$ = newEnumType ($3);
+          SPEC_SCLS(getSpec($$)) = 0;
+        }
+    | ENUM identifier '{' enumerator_list '}'
+        {
+          symbol *csym;
+          sym_link *enumtype;
+
+          csym = findSymWithLevel(enumTab, $2);
+          if ((csym && csym->level == $2->level))
+            {
+              werrorfl($2->fileDef, $2->lineDef, E_DUPLICATE_TYPEDEF, csym->name);
+              werrorfl(csym->fileDef, csym->lineDef, E_PREVIOUS_DEF);
+            }
+
+          enumtype = newEnumType ($4);
+          SPEC_SCLS(getSpec(enumtype)) = 0;
+          $2->type = enumtype;
+
+          /* add this to the enumerator table */
+          if (!csym)
+              addSym (enumTab, $2, $2->name, $2->level, $2->block, 0);
+          $$ = copyLinkChain(enumtype);
+        }
+     | ENUM identifier '{' enumerator_list ',' '}'
         {
+          if (!options.std_c99)
+            werror (E_ENUM_COMMA_C99);
           symbol *csym;
           sym_link *enumtype;
 
@@ -873,7 +916,6 @@
 
 enumerator_list
    : enumerator
-   | enumerator_list ','
    | enumerator_list ',' enumerator
         {
           $3->next = $1;
@@ -882,7 +924,7 @@
    ;
 
 enumerator
-   : identifier opt_assign_expr
+   : identifier attribute_specifier_sequence_opt opt_assign_expr
         {
           symbol *sym;
 
@@ -892,7 +934,7 @@
               werrorfl ($1->fileDef, $1->lineDef, E_DUPLICATE_MEMBER, "enum", $1->name);
               werrorfl (sym->fileDef, sym->lineDef, E_PREVIOUS_DEF);
             }
-          $1->type = copyLinkChain ($2->type);
+          $1->type = copyLinkChain ($3->type);
           $1->etype = getSpec ($1->type);
           SPEC_ENUM ($1->etype) = 1;
           $$ = $1;
@@ -1277,7 +1319,10 @@
           FUNC_HASVARARGS(funcType) = IS_VARG($4);
           FUNC_ARGS(funcType) = reverseVal($4);
 
+          FUNC_SDCCCALL(funcType) = -1;
+
           /* nest level was incremented to take care of the parms  */
+          leaveBlockScope (currBlockno);
           NestLevel -= LEVEL_UNIT;
           currBlockno = STACK_POP(blockNum);
           seqPointNo++; /* not a true sequence point, but helps resolve scope */
@@ -1291,8 +1336,9 @@
    | declarator2 '(' identifier_list ')'
         {
           werror(E_OLD_STYLE,$1->name);
-          /* assume it returns an int */
-          $1->type = $1->etype = newIntLink();
+          
+          addDecl ($1, FUNCTION, NULL);
+          
           $$ = $1;
         }
    ;
@@ -1458,38 +1504,33 @@
    | array_abstract_declarator
    | function_abstract_declarator
    ;
+   
+direct_abstract_declarator_opt
+   :                             { $$ = NULL; }
+   | direct_abstract_declarator
+   ;
 
 array_abstract_declarator
-   : '[' ']'                        {
-                                       $$ = newLink (DECLARATOR);
-                                       DCL_TYPE($$) = ARRAY;
-                                       DCL_ELEM($$) = 0;
-                                    }
-   | '[' constant_expr ']'          {
-                                       value *val;
-                                       $$ = newLink (DECLARATOR);
-                                       DCL_TYPE($$) = ARRAY;
-                                       DCL_ELEM($$) = (int) ulFromVal(val = constExprValue($2,TRUE));
-                                    }
-   | direct_abstract_declarator '[' ']'   {
+   : direct_abstract_declarator_opt '[' ']'   {
                                        $$ = newLink (DECLARATOR);
                                        DCL_TYPE($$) = ARRAY;
                                        DCL_ELEM($$) = 0;
-                                       $$->next = $1;
+                                       if($1)
+                                         $$->next = $1;
                                     }
-   | direct_abstract_declarator '[' constant_expr ']'
+   | direct_abstract_declarator_opt '[' constant_expr ']'
                                     {
                                        value *val;
                                        $$ = newLink (DECLARATOR);
                                        DCL_TYPE($$) = ARRAY;
                                        DCL_ELEM($$) = (int) ulFromVal(val = constExprValue($3,TRUE));
-                                       $$->next = $1;
+                                       if($1)
+                                         $$->next = $1;
                                     }
    ;
 
 function_abstract_declarator
    : '(' ')'                        { $$ = NULL;}
-   | '(' parameter_type_list ')'    { $$ = NULL;}
    | direct_abstract_declarator '(' ')' {
      // $1 must be a pointer to a function
      sym_link *p=newLink(DECLARATOR);
@@ -1502,6 +1543,7 @@
      }
      $1->next=p;
    }
+   | '(' parameter_type_list ')'    { $$ = NULL;}
    | direct_abstract_declarator '('
         {
           NestLevel += LEVEL_UNIT;
@@ -1611,12 +1653,27 @@
 
 attribute_specifier_sequence
    : attribute_specifier_sequence attribute_specifier
+     {
+       $$ = $1;
+       attribute *a;
+       for (a = $$; a->next; a = a->next);
+       a->next = $2;
+     }
    | attribute_specifier
+     {
+       $$ = $1;
+     }
    ;
 
 attribute_specifier_sequence_opt
    : /* empty */
+     {
+       $$ = 0;
+     }
    | attribute_specifier_sequence
+     {
+       $$ = $1;
+     }
    ;
 
 attribute_specifier
@@ -1624,24 +1681,54 @@
      {
        if (!options.std_c2x)
          werror(E_ATTRIBUTE_C2X);
+       $$ = $3;
      }
    ;
 
 attribute_list
    : /* empty */
+     {
+       $$ = 0;
+     }
    | attribute
+     {
+       $$ = $1;
+     }
    | attribute_list ','
+     {
+       $$ = $1;
+     }
    | attribute_list ',' attribute
+     {
+       $$ = $1;
+       attribute *a;
+       for (a = $$; a->next; a = a->next);
+       a->next = $3;
+     }
    ;
 
 attribute
    : attribute_token
+   {
+     $$ = newAttribute ($1, 0);
+   }
    | attribute_token attribute_argument_clause
+   {
+     $$ = newAttribute ($1, 0);
+   }
    ;
 
 attribute_token
    : identifier
+     {
+       $$ = $1;
+       $$->next = 0;
+     }
    | identifier ATTRIBCOLON identifier
+     {
+       $$ = $1;
+       $$->next = $3;
+     }
    ;
 
 attribute_argument_clause
@@ -1732,6 +1819,7 @@
 end_block
    : '}'
         {
+          leaveBlockScope (currBlockno);
           NestLevel -= LEVEL_UNIT;
           currBlockno = STACK_POP(blockNum);
         }
@@ -1871,6 +1959,7 @@
                           cleanUpLevel(StructTab, NestLevel + LEVEL_UNIT);
                           noLineno--;
 
+                          leaveBlockScope (currBlockno);
                           NestLevel -= LEVEL_UNIT;
                           currBlockno = STACK_POP(blockNum);
                         }
@@ -2097,6 +2186,19 @@
    |  SMALLC         {  $$ = newLink (SPECIFIER);
                         FUNC_ISSMALLC($$) = 1;
                      }
+   |  RAISONANCE     {  $$ = newLink (SPECIFIER);
+                        FUNC_ISRAISONANCE($$) = 1;
+                     }
+   |  IAR            {  $$ = newLink (SPECIFIER);
+                        FUNC_ISIAR($$) = 1;
+                     }
+   |  COSMIC         {  $$ = newLink (SPECIFIER);
+                        FUNC_ISCOSMIC($$) = 1;
+                     }
+   |  SDCCCALL '('constant_expr ')'
+                     {  $$ = newLink (SPECIFIER);
+                        FUNC_SDCCCALL($$) = ulFromVal(constExprValue ($3, true));
+                     }
    |  Z88DK_FASTCALL {  $$ = newLink (SPECIFIER);
                         FUNC_ISZ88DK_FASTCALL($$) = 1;
                      }
@@ -2105,7 +2207,7 @@
                      }
    |  Z88DK_PARAMS_OFFSET '(' constant_expr ')' 
                      {
-                        value *offset_v = constExprValue ($3, TRUE);
+                        value *offset_v = constExprValue ($3, true);
                         int    offset = 0;
                         $$ = newLink(SPECIFIER);
                         if  ( offset_v ) 
@@ -2302,7 +2404,12 @@
           value *val;
 
           val = constExprValue($2, TRUE);
-          if (!IS_INT(val->type) && !IS_CHAR(val->type) && !IS_BOOL(val->type))
+          if (!val) // Not a constant expression
+            {
+              werror (E_CONST_EXPECTED);
+              val = constIntVal("0");
+            }
+          else if (!IS_INT(val->type) && !IS_CHAR(val->type) && !IS_BOOL(val->type))
             {
               werror(E_ENUM_NON_INTEGER);
               SNPRINTF(lbuff, sizeof(lbuff), "%d", (int) ulFromVal(val));
@@ -2323,12 +2430,12 @@
         }
    ;
 
-type_specifier_list : type_specifier_list_ { $$ = finalizeSpec($1); };
+specifier_qualifier_list : type_specifier_list_ { $$ = finalizeSpec($1); };
 
 type_specifier_list_
-   : type_specifier
+   : type_specifier_qualifier
    //| type_specifier_list_ type_specifier         {  $$ = mergeSpec ($1,$2, "type_specifier_list"); }
-   | type_specifier_list_ type_specifier {
+   | type_specifier_list_ type_specifier_qualifier {
      /* if the decl $2 is not a specifier */
      /* find the spec and replace it      */
      $$ = mergeDeclSpec($1, $2, "type_specifier_list type_specifier skipped");
@@ -2422,6 +2529,7 @@
 implicit_block
    : declaration_after_statement statements_and_implicit
      {
+       leaveBlockScope (currBlockno);
        NestLevel -= SUBLEVEL_UNIT;
        currBlockno = STACK_POP(blockNum);
        $$ = createBlock($1, $2);
@@ -2429,6 +2537,7 @@
      }
    | declaration_after_statement
      {
+       leaveBlockScope (currBlockno);
        NestLevel -= SUBLEVEL_UNIT;
        currBlockno = STACK_POP(blockNum);
        $$ = createBlock($1, NULL);
diff -Nru sdcc-4.0.0+dfsg/src/stm8/gen.c sdcc-4.2.0+dfsg/src/stm8/gen.c
--- sdcc-4.0.0+dfsg/src/stm8/gen.c	2020-01-08 21:42:28.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/stm8/gen.c	2022-02-03 09:32:48.000000000 +0000
@@ -1,7 +1,7 @@
 /*-------------------------------------------------------------------------
   gen.c - code generator for STM8.
 
-  Copyright (C) 2012 - 2013, Philipp Klaus Krause pkk@spth.de, philipp@informatik.uni-frankfurt.de)
+  Copyright (C) 2012 - 2021, Philipp Klaus Krause pkk@spth.de, philipp@informatik.uni-frankfurt.de, krauseph@informatik.uni-freiburg.de)
 
   This program is free software; you can redistribute it and/or modify it
   under the terms of the GNU General Public License as published by the
@@ -24,6 +24,8 @@
 /* Use the D macro for basic (unobtrusive) debugging messages */
 #define D(x) do if (options.verboseAsm) { x; } while (0)
 
+#define UNIMPLEMENTED do {wassertl (regalloc_dry_run, "Unimplemented"); cost (500, 500);} while(0)
+
 static bool regalloc_dry_run;
 static unsigned int regalloc_dry_run_cost_bytes;
 static unsigned int regalloc_dry_run_cost_cycles;
@@ -55,9 +57,12 @@
   A_CPLW,
   A_DEC,
   A_DECW,
+  A_EXG,
+  A_EXGW,
   A_INC,
   A_INCW,
   A_LD,
+  A_LDW,
   A_MOV,
   A_NEG,
   A_NEGW,
@@ -77,6 +82,7 @@
   A_SRLW,
   A_SUB,
   A_SWAP,
+  A_SWAPW,
   A_TNZ,
   A_TNZW,
   A_XOR
@@ -95,9 +101,12 @@
   "cplw",
   "dec",
   "decw",
+  "exg",
+  "exgw",
   "inc",
   "incw",
   "ld",
+  "ldw",
   "mov",
   "neg",
   "negw",
@@ -117,91 +126,52 @@
   "srlw",
   "sub",
   "swap",
+  "swapw",
   "tnz",
   "tnzw",
   "xor"
 };
 
-static struct asmop asmop_a, asmop_x, asmop_y, asmop_xy, asmop_xyl, asmop_zero, asmop_one;
+bool stm8_regs_used_as_parms_in_calls_from_current_function[YH_IDX + 1];
+bool stm8_regs_used_as_parms_in_pcalls_from_current_function[YH_IDX + 1];
+
+static struct asmop asmop_a, asmop_x, asmop_y, asmop_xy, asmop_xyl, asmop_yx, asmop_zero, asmop_one, asmop_mone;
 static struct asmop *const ASMOP_A = &asmop_a;
 static struct asmop *const ASMOP_X = &asmop_x;
 static struct asmop *const ASMOP_Y = &asmop_y;
 static struct asmop *const ASMOP_XY = &asmop_xy;
 static struct asmop *const ASMOP_XYL = &asmop_xyl;
+static struct asmop *const ASMOP_YX = &asmop_yx;
 static struct asmop *const ASMOP_ZERO = &asmop_zero;
 static struct asmop *const ASMOP_ONE = &asmop_one;
+static struct asmop *const ASMOP_MONE = &asmop_mone;
+
+// Init aop as a an asmop for data in registers, as given by the -1-terminated array regidx.
+static void
+stm8_init_reg_asmop(asmop *aop, const signed char *regidx)
+{
+  aop->type = AOP_REG;
+  aop->size = 0;
+  memset (aop->regs, -1, sizeof(aop->regs));
+  
+  for(int i = 0; regidx[i] >= 0; i++)
+    {
+      aop->aopu.bytes[i].byteu.reg = stm8_regs + regidx[i];
+      aop->regs[regidx[i]] = i;
+      aop->aopu.bytes[i].in_reg = true;
+      aop->size++;
+    }
+}
 
 void
 stm8_init_asmops (void)
 {
-  asmop_a.type = AOP_REG;
-  asmop_a.size = 1;
-  asmop_a.aopu.bytes[0].in_reg = TRUE;
-  asmop_a.aopu.bytes[0].byteu.reg = stm8_regs + A_IDX;
-  asmop_a.regs[A_IDX] = 0;
-  asmop_a.regs[XL_IDX] = -1;
-  asmop_a.regs[XH_IDX] = -1;
-  asmop_a.regs[YL_IDX] = -1;
-  asmop_a.regs[YH_IDX] = -1;
-  asmop_a.regs[C_IDX] = -1;
-
-  asmop_x.type = AOP_REG;
-  asmop_x.size = 2;
-  asmop_x.aopu.bytes[0].in_reg = TRUE;
-  asmop_x.aopu.bytes[0].byteu.reg = stm8_regs + XL_IDX;
-  asmop_x.aopu.bytes[1].in_reg = TRUE;
-  asmop_x.aopu.bytes[1].byteu.reg = stm8_regs + XH_IDX;
-  asmop_x.regs[A_IDX] = -1;
-  asmop_x.regs[XL_IDX] = 0;
-  asmop_x.regs[XH_IDX] = 1;
-  asmop_x.regs[YL_IDX] = -1;
-  asmop_x.regs[YH_IDX] = -1;
-  asmop_x.regs[C_IDX] = -1;
-
-  asmop_y.type = AOP_REG;
-  asmop_y.size = 2;
-  asmop_y.aopu.bytes[0].in_reg = TRUE;
-  asmop_y.aopu.bytes[0].byteu.reg = stm8_regs + YL_IDX;
-  asmop_y.aopu.bytes[1].in_reg = TRUE;
-  asmop_y.aopu.bytes[1].byteu.reg = stm8_regs + YH_IDX;
-  asmop_y.regs[A_IDX] = -1;
-  asmop_y.regs[XL_IDX] = -1;
-  asmop_y.regs[XH_IDX] = -1;
-  asmop_y.regs[YL_IDX] = 0;
-  asmop_y.regs[YH_IDX] = 1;
-  asmop_y.regs[C_IDX] = -1;
-
-  asmop_xy.type = AOP_REG;
-  asmop_xy.size = 4;
-  asmop_xy.aopu.bytes[0].in_reg = TRUE;
-  asmop_xy.aopu.bytes[0].byteu.reg = stm8_regs + XL_IDX;
-  asmop_xy.aopu.bytes[1].in_reg = TRUE;
-  asmop_xy.aopu.bytes[1].byteu.reg = stm8_regs + XH_IDX;
-  asmop_xy.aopu.bytes[2].in_reg = TRUE;
-  asmop_xy.aopu.bytes[2].byteu.reg = stm8_regs + YL_IDX;
-  asmop_xy.aopu.bytes[3].in_reg = TRUE;
-  asmop_xy.aopu.bytes[3].byteu.reg = stm8_regs + YH_IDX;
-  asmop_xy.regs[A_IDX] = -1;
-  asmop_xy.regs[XL_IDX] = 0;
-  asmop_xy.regs[XH_IDX] = 1;
-  asmop_xy.regs[YL_IDX] = 2;
-  asmop_xy.regs[YH_IDX] = 3;
-  asmop_xy.regs[C_IDX] = -1;
-
-  asmop_xyl.type = AOP_REG;
-  asmop_xyl.size = 3;
-  asmop_xyl.aopu.bytes[0].in_reg = TRUE;
-  asmop_xyl.aopu.bytes[0].byteu.reg = stm8_regs + XL_IDX;
-  asmop_xyl.aopu.bytes[1].in_reg = TRUE;
-  asmop_xyl.aopu.bytes[1].byteu.reg = stm8_regs + XH_IDX;
-  asmop_xyl.aopu.bytes[2].in_reg = TRUE;
-  asmop_xyl.aopu.bytes[2].byteu.reg = stm8_regs + YL_IDX;
-  asmop_xy.regs[A_IDX] = -1;
-  asmop_xy.regs[XL_IDX] = 0;
-  asmop_xy.regs[XH_IDX] = 1;
-  asmop_xy.regs[YL_IDX] = 2;
-  asmop_xy.regs[YH_IDX] = -1;
-  asmop_xy.regs[C_IDX] = -1;
+  stm8_init_reg_asmop(&asmop_a, (const signed char[]){A_IDX, -1});
+  stm8_init_reg_asmop(&asmop_x, (const signed char[]){XL_IDX, XH_IDX, -1});
+  stm8_init_reg_asmop(&asmop_y, (const signed char[]){YL_IDX, YH_IDX, -1});
+  stm8_init_reg_asmop(&asmop_xy, (const signed char[]){XL_IDX, XH_IDX, YL_IDX, YH_IDX, -1});
+  stm8_init_reg_asmop(&asmop_xyl, (const signed char[]){XL_IDX, XH_IDX, YL_IDX, -1});
+  stm8_init_reg_asmop(&asmop_yx, (const signed char[]){YL_IDX, YH_IDX, XL_IDX, XH_IDX, -1});
 
   asmop_zero.type = AOP_LIT;
   asmop_zero.size = 1;
@@ -222,9 +192,20 @@
   asmop_one.regs[YL_IDX] = -1;
   asmop_one.regs[YH_IDX] = -1;
   asmop_one.regs[C_IDX] = -1;
+  
+  asmop_mone.type = AOP_LIT;
+  asmop_mone.size = 8; // Maximum size for asmop.
+  asmop_mone.aopu.aop_lit = constVal ("-1");
+  asmop_mone.regs[A_IDX] = -1;
+  asmop_mone.regs[XL_IDX] = -1;
+  asmop_mone.regs[XH_IDX] = -1;
+  asmop_mone.regs[YL_IDX] = -1;
+  asmop_mone.regs[YH_IDX] = -1;
+  asmop_mone.regs[C_IDX] = -1;
 }
 
-void emit2 (const char *inst, const char *fmt, ...)
+static void 
+emit2 (const char *inst, const char *fmt, ...)
 {
   if (!regalloc_dry_run)
     {
@@ -317,7 +298,7 @@
 static bool
 aopOnStackNotExt (const asmop *aop, int offset, int size)
 {
-  return (aopOnStack (aop, offset, size) && (aop->aopu.bytes[offset].byteu.stk + G.stack.pushed <= 255 || regalloc_dry_run));// Todo: Stack offsets might be unavailable during dry run (messes with addition costs, so we should have a mechanism to do it better).
+  return (aopOnStack (aop, offset, size) && (aop->aopu.bytes[offset].byteu.stk + G.stack.pushed <= 255 || regalloc_dry_run)); // Todo: Stack offsets might be unavailable during dry run (messes with addition costs, so we should have a mechanism to do it better).
 }
 
 /*-----------------------------------------------------------------*/
@@ -328,6 +309,9 @@
 {
   for(; size; size--, offset1++, offset2++)
     {
+      if (offset1 >= aop1->size || offset2 >= aop2->size)
+        return (false);
+
       if (aopRS (aop1) && aopRS (aop2) && // Same register
         aop1->aopu.bytes[offset1].in_reg && aop2->aopu.bytes[offset2].in_reg &&
         aop1->aopu.bytes[offset1].byteu.reg == aop2->aopu.bytes[offset2].byteu.reg)
@@ -385,13 +369,15 @@
   regalloc_dry_run_cost_cycles += cycles * regalloc_dry_run_cycle_scale;
 }
 
-void emitJP(const symbol *target, float probability)
+static void 
+emitJP(const symbol *target, float probability)
 {
   if (!regalloc_dry_run)
      emit2 (options.model == MODEL_LARGE ? "jpf" : "jp", "%05d$", labelKey2num (target->key));
   cost (3 + (options.model == MODEL_LARGE), (1 + (options.model == MODEL_LARGE)) * probability);
 }
 
+// Get aop at offset as 8-bit operand.
 static const char *
 aopGet(const asmop *aop, int offset)
 {
@@ -401,21 +387,23 @@
   if (regalloc_dry_run)
     return ("");
 
-  if (offset >= aop->size)
-    return ("#0x00");
-
   if (aop->type == AOP_LIT)
     {
       SNPRINTF (buffer, sizeof(buffer), "#0x%02x", byteOfVal (aop->aopu.aop_lit, offset));
       return (buffer);
     }
 
+  if (offset >= aop->size)
+    return ("#0x00");
+
   if (aopRS (aop) && aop->aopu.bytes[offset].in_reg)
     return (aop->aopu.bytes[offset].byteu.reg->name);
 
   if (aopRS (aop) && !aop->aopu.bytes[offset].in_reg)
     {
-      int soffset = aop->aopu.bytes[offset].byteu.stk + G.stack.pushed;
+      long int soffset = aop->aopu.bytes[offset].byteu.stk + G.stack.pushed;
+      
+      wassert (soffset < (1 << 16) && soffset >= 0);
 
       if (soffset > 255)
         {
@@ -433,11 +421,10 @@
 
   if (aop->type == AOP_IMMD)
     {
-      wassertl_bt (offset < (2 + (options.model == MODEL_LARGE)), "Immediate operand out of range");
       if (offset == 0)
-        SNPRINTF (buffer, sizeof(buffer), "#<(%s + %d)", aop->aopu.immd, aop->aopu.immd_off);
+        SNPRINTF (buffer, sizeof(buffer), "#<(%s+%d)", aop->aopu.immd, aop->aopu.immd_off);
       else
-        SNPRINTF (buffer, sizeof(buffer), "#((%s + %d) >> %d)", aop->aopu.immd, aop->aopu.immd_off, offset * 8);
+        SNPRINTF (buffer, sizeof(buffer), "#((%s+%d) >> %d)", aop->aopu.immd, aop->aopu.immd_off, offset * 8);
       return (buffer);
     }
 
@@ -451,6 +438,7 @@
   return ("dummy");
 }
 
+// Get aop at offset as 16-bit operand.
 static const char *
 aopGet2(const asmop *aop, int offset)
 {
@@ -480,9 +468,9 @@
   else if (aop->type == AOP_IMMD)
     {
       if (offset)
-        SNPRINTF (buffer, sizeof(buffer), "#((%s + %d) >> %d)", aop->aopu.immd, aop->aopu.immd_off, offset * 8);
+        SNPRINTF (buffer, sizeof(buffer), "#((%s+%d) >> %d)", aop->aopu.immd, aop->aopu.immd_off, offset * 8);
       else
-        SNPRINTF (buffer, sizeof(buffer), "#(%s + %d)", aop->aopu.immd, aop->aopu.immd_off);
+        SNPRINTF (buffer, sizeof(buffer), "#(%s+%d)", aop->aopu.immd, aop->aopu.immd_off);
       return (buffer);
     }
 
@@ -583,7 +571,7 @@
   cost (8, 4 * 8);
 }
 
-/* For 16-bit operations that have only one operand, i.e. tnzw */
+/* For other 16-bit operations that have only one operand, i.e. tnzw */
 static void
 opw_cost2 (const asmop *op1, int offset1)
 {
@@ -605,6 +593,15 @@
 }
 
 static void
+exg_cost (const asmop *op2)
+{
+  if (op2->type == AOP_DIR)
+    cost (3, 3);
+  else
+    cost (1, 1);
+}
+
+static void
 ld_cost (const asmop *op1, int offset1, const asmop *op2, int offset2)
 {
   int r1Idx, r2Idx;
@@ -734,6 +731,9 @@
   case A_DEC:
     op_cost (op1, offset1);
     break;
+  case A_EXG:
+    exg_cost (op2);
+    break;
   case A_LD:
     ld_cost (op1, offset1, op2, offset2);
     break;
@@ -788,6 +788,18 @@
   case A_INCW:
     opw_cost (op1, offset1);
     break;
+  case A_EXGW:
+    if (offset1 != 0 || offset2 != 0 || !aopSame (op1, 0, ASMOP_X, 0, 2) || !aopSame (op2, 0, ASMOP_Y, 0, 2))
+      wassertl_bt (0, "Tried to get cost for EXGW with invalid arguments");
+    cost (1, 1);
+    break;
+  case A_LDW:
+    if (aopSame (op1, offset1, ASMOP_X, 0, 2) && aopSame (op2, offset2, ASMOP_Y, 0, 2) || aopSame (op1, offset1, ASMOP_Y, 0, 2) && aopSame (op2, offset2, ASMOP_X, 0, 2))
+      {
+        opw_cost (op1, offset1);
+        break;
+      }
+    wassert (0);
   case A_NEGW:
   case A_RLCW:
     opw_cost2 (op1, offset1);
@@ -807,6 +819,9 @@
   case A_TNZW:
     opw_cost2 (op1, offset1);
     break;
+  case A_SWAPW:
+    opw_cost (op1, offset1);
+    break;
   default:
     wassertl_bt (0, "Tried to get cost for unknown 16-bit instruction");
   }
@@ -954,13 +969,20 @@
   else if (sym->onStack || sym->iaccess)
     {
       int offset;
-      int base;
+      long int base;
 
       aop = newAsmop (AOP_STK);
       aop->size = getSize (sym->type);
 
       base = sym->stack + (sym->stack > 0 ? G.stack.param_offset : 0);
 
+      if (labs(base) > (1 << 15))
+      {
+        if (!regalloc_dry_run)
+          werror (W_INVALID_STACK_LOCATION);
+        base = 0;
+      }
+
       for(offset = 0; offset < aop->size; offset++)
         aop->aopu.bytes[offset].byteu.stk = base + aop->size - offset;
     }
@@ -982,7 +1004,7 @@
 {
   iCode *ic = sym->rematiCode;
   asmop *aop;
-  int val = 0;
+  long val = 0;
 
   wassert_bt (ic);
 
@@ -992,18 +1014,18 @@
         {
           if (isOperandLiteral (IC_RIGHT (ic)))
             {
-              val += (int) operandLitValue (IC_RIGHT (ic));
+              val += (long) operandLitValue (IC_RIGHT (ic));
               ic = OP_SYMBOL (IC_LEFT (ic))->rematiCode;
             }
           else
             {
-              val += (int) operandLitValue (IC_LEFT (ic));
+              val += (long) operandLitValue (IC_LEFT (ic));
               ic = OP_SYMBOL (IC_RIGHT (ic))->rematiCode;
             }
         }
       else if (ic->op == '-')
         {
-          val -= (int) operandLitValue (IC_RIGHT (ic));
+          val -= (long) operandLitValue (IC_RIGHT (ic));
           ic = OP_SYMBOL (IC_LEFT (ic))->rematiCode;
         }
       else if (IS_CAST_ICODE (ic))
@@ -1012,7 +1034,7 @@
         }
       else if (ic->op == ADDRESS_OF)
         {
-          val += (int) operandLitValue (IC_RIGHT (ic));
+          val += (long) operandLitValue (IC_RIGHT (ic));
           break;
         }
       else
@@ -1163,6 +1185,185 @@
   }
 }
 
+// Get asmop for registers containing the return type of function
+// Returns 0 if the function does not have a return value or it is not returned in registers.
+static asmop *
+aopRet (sym_link *ftype)
+{
+  wassert (IS_FUNC (ftype));
+
+  int size = getSize (ftype->next);
+
+  // Raisonance passes return values larger than 16 bits in pseudoregisters.
+  if (FUNC_ISRAISONANCE (ftype) && size > 2)
+    werror (E_RAISONANCE_LARGE_RETURN);
+
+  // IAR passes return values larger than 16 bits in pseudoregisters.
+  if (FUNC_ISIAR (ftype) && size > 2)
+    werror (E_IAR_LARGE_RETURN);
+
+  // Cosmic passes return values larger than 16 bits in pseudoregisters.
+  if (FUNC_ISCOSMIC (ftype) && size > 2)
+    werror (E_COSMIC_LARGE_RETURN);
+
+  switch (size)
+    {
+    case 1:
+      return (ASMOP_A);
+    case 2:
+      return (ASMOP_X);
+    case 3:
+      return (ASMOP_XYL);
+    case 4:
+      return (ASMOP_XY);   
+    default:
+      return 0;
+    }
+}
+
+// Get asmop for registers containing a parameter
+// Returns 0 if the parameter is passed on the stack
+static asmop *
+aopArg (sym_link *ftype, int i)
+{
+  wassert (IS_FUNC (ftype));
+
+  // Calling convention for variable arguments not documented in Raisonance C compiler manual. Needs reverse-engineering.
+  wassertl (!FUNC_ISRAISONANCE (ftype) || !FUNC_HASVARARGS (ftype), "Unimplemented support for variable arguments in Raisonance calling convention.");
+  // Calling convention for variable arguments not documented in IAR C/C++ development guide. Needs reverse-engineering.
+  wassertl (!FUNC_ISIAR (ftype) || !FUNC_HASVARARGS (ftype), "Unimplemented support for variable arguments in IAR calling convention.");
+
+  value *args = FUNC_ARGS(ftype);
+  wassert (args);
+
+  if (FUNC_HASVARARGS (ftype))
+    return 0;
+
+  // Old SDCC calling convention.
+  if (FUNC_SDCCCALL (ftype) == 0)
+    return 0;
+    
+  // IAR calling convention.
+  if (FUNC_ISIAR (ftype))
+    {
+      int j, num_1_byte_args, num_2_byte_args;
+      value *arg;
+
+      num_1_byte_args = 0;
+      num_2_byte_args = 0;
+      bool stackarg = false;
+      for (j = 1, arg = args; j < i; j++, arg = arg->next)
+        {
+          wassert (arg);
+          num_1_byte_args += (getSize (arg->type) == 1);
+          num_2_byte_args += (getSize (arg->type) == 2);
+          stackarg |= (getSize (arg->type) > 4 || num_1_byte_args > 1 || num_2_byte_args > 2);
+        }
+
+      // IAR passes the first two 24-bit / 32-bit arguments in pseudoregisters.
+      if ((getSize (arg->type) == 3 || getSize (arg->type) == 4))
+        werror (E_IAR_PSEUDOPARM);
+
+      if (getSize (arg->type) == 1)
+        {
+          if (num_1_byte_args > 0)
+            werror (E_IAR_PSEUDOPARM);
+          else if (stackarg)
+            wassertl (0, "Unimplemented stack argument before register argument for IAR calling convention.");
+          else
+            return ASMOP_A;
+        }
+
+      if (getSize (arg->type) == 2)
+        {
+          if (num_2_byte_args > 1)
+            werror (E_IAR_PSEUDOPARM);
+          else if (stackarg)
+            wassertl (0, "Unimplemented stack argument before register argument for IAR calling convention.");
+          else if (num_2_byte_args)
+            return ASMOP_Y;
+          else
+            return ASMOP_X;
+        }
+
+      return 0;
+    }
+    
+  // Cosmic calling convention.
+  if (FUNC_ISCOSMIC (ftype))
+    {
+      if (i == 1 && getSize (args->type) == 1)
+        return ASMOP_A;
+
+      if (i == 1 && getSize (args->type) == 2)
+        return ASMOP_X;
+
+      return 0;
+    }
+
+  // Raisonance calling convention, same as current SDCC.
+  if (FUNC_ISRAISONANCE (ftype) || !FUNC_HASVARARGS (ftype))
+    {
+      int j;
+      value *arg;
+
+      for (j = 1, arg = args; j < i; j++, arg = arg->next)
+        wassert (arg);
+
+      if (i == 1 && getSize (arg->type) == 2)
+        return ASMOP_X;
+
+      if (i == 1 && getSize (arg->type) == 1)
+        return ASMOP_A;
+
+      if (i == 2 && aopArg (ftype, 1) == ASMOP_X && getSize (arg->type) == 1)
+        return ASMOP_A;
+
+      if (i == 2 && aopArg (ftype, 1) == ASMOP_A && getSize (arg->type) == 2)
+        return ASMOP_X;
+
+      return 0;
+    }
+    
+  return 0;
+}
+
+// Return true, iff ftype cleans up stack parameters.
+static bool
+isFuncCalleeStackCleanup (sym_link *ftype)
+{
+  wassert (IS_FUNC (ftype));
+
+  const bool bigreturn = (getSize (ftype->next) > 4) || IS_STRUCT (ftype->next);
+  int stackparmbytes = bigreturn * 2;
+
+  for (value *arg = FUNC_ARGS(ftype); arg && !FUNC_HASVARARGS(ftype); arg = arg->next)
+    {
+      int argsize = getSize (arg->type);
+      if (!SPEC_REGPARM (arg->etype))
+        stackparmbytes += argsize;
+    }
+  if (!stackparmbytes)
+    return false;
+
+  if (IFFUNC_ISZ88DK_CALLEE (ftype))
+    return true;
+
+  if (FUNC_SDCCCALL (ftype) != 1 || FUNC_ISRAISONANCE (ftype) || FUNC_ISCOSMIC(ftype) || FUNC_ISIAR (ftype))
+    return false;
+
+  if (!IFFUNC_HASVARARGS (ftype) && options.model != MODEL_LARGE)
+    {
+      if (!ftype->next || getSize (ftype->next) <= 2)
+        return true;
+      else if (IS_FLOAT (ftype->next) && FUNC_ARGS(ftype) && IS_FLOAT(FUNC_ARGS(ftype)->etype))
+        return true;
+      return false;
+    }
+  
+  return false;
+}
+
 static void
 push (const asmop *op, int offset, int size)
 {
@@ -1244,15 +1445,13 @@
 	case A_IDX:
       break;
     case XL_IDX:
-      emit2 ("exg", "a, xl");
-      cost (1, 1);
+      emit3 (A_EXG, ASMOP_A, ASMOP_X);
       break;
     case XH_IDX:
       emit3w (A_RLWA, ASMOP_X, 0);
       break;
     case YL_IDX:
-      emit2 ("exg", "a, yl");
-      cost (1, 1);
+      emit3 (A_EXG, ASMOP_A, ASMOP_Y);
       break;
     case YH_IDX:
       emit3w (A_RLWA, ASMOP_Y, 0);
@@ -1269,15 +1468,13 @@
     case A_IDX:
       break;
     case XL_IDX:
-      emit2 ("exg", "a, xl");
-      cost (1, 1);
+      emit3 (A_EXG, ASMOP_A, ASMOP_X);
       break;
     case XH_IDX:
       emit3w (A_RRWA, ASMOP_X, 0);
       break;
     case YL_IDX:
-      emit2 ("exg", "a, yl");
-      cost (1, 1);
+      emit3 (A_EXG, ASMOP_A, ASMOP_Y);
       break;
     case YH_IDX:
       emit3w (A_RRWA, ASMOP_Y, 0);
@@ -1288,7 +1485,7 @@
 }
 
 /*-----------------------------------------------------------------*/
-/* stackAop - put xl, xh, yl, yh aop on stack                      */
+/* stack_aop - put xl, xh, yl, yh aop on stack                     */
 /*-----------------------------------------------------------------*/
 static
 const asmop *stack_aop (const asmop *aop, int i, int *offset)
@@ -1337,7 +1534,7 @@
       // seems addw sp, byte has a signed operand, while sub sp, #byte has an unsigned operand, also, in contrast to what the
       // manual states, addw sp, #byte only takes 1 cycle.
 
-      // todo: For big n, use addition in X or Y when free.
+      // For big n, use addition in X or Y when free.
       if (abs (n) > 255 * 2 + (n > 0 || a_free) + (optimize.codeSize ? x_free : 255) && x_free)
         {
           emit2 ("ldw", "x, sp");
@@ -1552,6 +1749,9 @@
   wassertl_bt (*size >= 0, "genCopyStack() copied more than there is to be copied.");
 }
 
+static void
+genMove_o (asmop *result, int roffset, asmop *source, int soffset, int size, bool a_dead_global, bool x_dead_global, bool y_dead_global);
+
 /*-----------------------------------------------------------------*/
 /* genCopy - Copy the value from one reg/stk asmop to another      */
 /*-----------------------------------------------------------------*/
@@ -1640,8 +1840,24 @@
 
           emit2 ("ldw", aopInReg (source, soffset + i, X_IDX) ? "%s, x" : "%s, y", aopGet2 (result, roffset + i));
           cost (2, 2);
-          assigned[i] = TRUE;
-          assigned[i + 1] = TRUE;
+          assigned[i] = true;
+          assigned[i + 1] = true;
+          regsize -= 2;
+          size -= 2;
+          i += 2;
+        }
+      else if (i < n - 1 && !assigned[i] && !assigned[i + 1] &&
+        (aopInReg (source, soffset + i, XH_IDX) && aopInReg (source, soffset + i + 1, XL_IDX) && x_dead || aopInReg (source, soffset + i, YH_IDX) && aopInReg (source, soffset + i + 1, YL_IDX) && y_dead) &&
+        aopOnStack (result, roffset + i, 2))
+        {
+          wassert_bt (size >= 2);
+
+          bool y = aopInReg (source, soffset + i, YH_IDX);
+          emit3w (A_SWAPW, y ? ASMOP_Y : ASMOP_X, 0);
+          emit2 ("ldw", y ? "%s, y" : "%s, x", aopGet2 (result, roffset + i));
+          cost (2, 2);
+          assigned[i] = true;
+          assigned[i + 1] = true;
           regsize -= 2;
           size -= 2;
           i += 2;
@@ -1655,7 +1871,7 @@
           emit3_o (A_LD, result, roffset + i, ASMOP_A, 0);
           if (!aopInReg (source, soffset + i, A_IDX))
             swap_from_a (source->aopu.bytes[soffset + i].byteu.reg->rIdx);
-          assigned[i] = TRUE;
+          assigned[i] = true;
           regsize--;
           size--;
           i++;
@@ -1717,8 +1933,7 @@
 
       if (exsum == 4)
         {
-          emit2 ("exgw", "x, y");
-          cost (1, 1);
+          emit3w (A_EXGW, ASMOP_X, ASMOP_Y);
           if(ex[0] >= 0)
             assigned[ex[0]] = TRUE;
           if(ex[1] >= 0)
@@ -1847,10 +2062,9 @@
 
       if (ex[0] >= 0 && ex[1] >= 0)
         {
-          emit2 ("exg", "a, xl");
-          cost (1, 1);
-          assigned[ex[0]] = TRUE;
-          assigned[ex[1]] = TRUE;
+          emit3 (A_EXG, ASMOP_A, ASMOP_X);
+          assigned[ex[0]] = true;
+          assigned[ex[1]] = true;
           regsize -= 2;
           size -= 2;
         }
@@ -1870,10 +2084,9 @@
 
       if (ex[0] >= 0 && ex[1] >= 0)
         {
-          emit2 ("exg", "a, yl");
-          cost (1, 1);
-          assigned[ex[0]] = TRUE;
-          assigned[ex[1]] = TRUE;
+          emit3 (A_EXG, ASMOP_A, ASMOP_Y);
+          assigned[ex[0]] = true;
+          assigned[ex[1]] = true;
           regsize -= 2;
           size -= 2;
         }
@@ -1893,8 +2106,7 @@
 
       if (ex[0] >= 0 && ex[1] >= 0)
         {
-          emit2 ("swapw", "x");
-          cost (1, 1);
+          emit3w (A_SWAPW, ASMOP_X, 0);
           assigned[ex[0]] = TRUE;
           assigned[ex[1]] = TRUE;
           regsize -= 2;
@@ -1916,8 +2128,7 @@
 
       if (ex[0] >= 0 && ex[1] >= 0)
         {
-          emit2 ("swapw", "y");
-          cost (2, 1);
+          emit3w (A_SWAPW, ASMOP_Y, 0);
           assigned[ex[0]] = TRUE;
           assigned[ex[1]] = TRUE;
           regsize -= 2;
@@ -1931,11 +2142,10 @@
     const int ih = result->regs[XH_IDX] - roffset;
     const bool assign_l = (il >= 0 && il < n && !assigned[il] && aopInReg (source, soffset + il, YL_IDX));
     const bool assign_h = (ih >= 0 && ih < n && !assigned[ih] && aopInReg (source, soffset + ih, YH_IDX));
-    if (source->regs[XL_IDX] < 0 && source->regs[XH_IDX] < 0 &&
+    if (source->regs[XL_IDX] < soffset && source->regs[XH_IDX] < soffset &&
       (assign_l && assign_h || assign_l && xh_dead && ih < 0 || assign_h && xl_dead && il < 0))
     {
-      emit2 ("ldw", "x, y");
-      cost (1, 1);
+      emit3w (A_LDW, ASMOP_X, ASMOP_Y);
       if (assign_l)
         {
           assigned[il] = TRUE;
@@ -1957,19 +2167,14 @@
     const int ih = result->regs[YH_IDX] - roffset;
     const bool assign_l = (il >= 0 && il < n && !assigned[il] && aopInReg (source, soffset + il, XL_IDX));
     const bool assign_h = (ih >= 0 && ih < n && !assigned[ih] && aopInReg (source, soffset + ih, XH_IDX));
-    if (source->regs[YL_IDX] < 0 && source->regs[YH_IDX] < 0 &&
+    if (source->regs[YL_IDX] < soffset && source->regs[YH_IDX] < soffset &&
       (assign_l && assign_h || assign_l && yh_dead && ih < 0 || assign_h && yl_dead && il < 0))
     {
       if(x_dead && assign_l && assign_h)
-        {
-          emit2 ("exgw", "x, y");
-          cost (1, 1);
-        }
+        emit3w (A_EXGW, ASMOP_X, ASMOP_Y);
       else
-        {
-          emit2 ("ldw", "y, x");
-          cost (2, 1);
-        }
+        emit3w (A_LDW, ASMOP_Y, ASMOP_X);
+
       if (assign_l)
         {
           assigned[il] = TRUE;
@@ -2033,7 +2238,7 @@
           cheapMove (result, roffset + i, source, soffset + i, TRUE);       // We can safely assign a byte.
           regsize--;
           size--;
-          assigned[i] = TRUE;
+          assigned[i] = true;
           continue;
         }
 
@@ -2042,7 +2247,7 @@
         wassertl_bt (0, "Unimplemented.");
       cost (180, 180);
       return;
-    }  
+    }
 
   // Copy (stack-to-stack) what we can with whatever free regs we have now.
   a_free = a_dead;
@@ -2069,15 +2274,35 @@
           i++;
           continue;
         }
-      else if (i < n - 1 && (aopInReg (result, roffset + i, X_IDX) || aopInReg (result, roffset + i, Y_IDX)) && aopOnStackNotExt (source, soffset + i, 2))
+      else if (i < n - 1 && (aopInReg (result, roffset + i, X_IDX) && aopOnStackNotExt (source, soffset + i, 2) || aopInReg (result, roffset + i, Y_IDX) && aopOnStack (source, soffset + i, 2)))
         {
           wassert_bt (size >= 2);
           emit2 ("ldw", aopInReg (result, roffset + i, X_IDX) ? "x, %s" : "y, %s", aopGet2 (source, soffset + i));
           cost (2, 2);
-          assigned[i] = TRUE;
-          assigned[i + 1] = TRUE;
+          assigned[i] = true;
+          assigned[i + 1] = true;
           if (aopInReg (result, roffset + i, X_IDX))
-            x_free = FALSE;
+            x_free = false;
+          else
+            y_free = false;
+          size -= 2;
+          i += 2;
+        }
+      else if (i < n - 1 &&
+        (aopInReg (result, roffset + i, XH_IDX) && aopInReg (result, roffset + i + 1, XL_IDX) || aopInReg (result, roffset + i, YH_IDX) && aopInReg (result, roffset + i + 1, YL_IDX)) &&
+        aopOnStackNotExt (source, soffset + i, 2))
+        {
+          bool y = aopInReg (result, roffset + i, YH_IDX);
+          wassert_bt (size >= 2);
+          emit2 ("ldw", y ? "y, %s" : "x, %s", aopGet2 (source, soffset + i));
+          cost (2, 2);
+          emit3w (A_SWAPW, y ? ASMOP_Y : ASMOP_X, 0);
+          assigned[i] = true;
+          assigned[i + 1] = true;
+          if (y)
+            y_free = false;
+          else
+            x_free = false;
           size -= 2;
           i += 2;
         }
@@ -2087,11 +2312,10 @@
           wassertl_bt (regalloc_dry_run || stm8_extend_stack, "Extended stack access, but y not prepared for extended stack access.");
           wassertl_bt (regalloc_dry_run || eoffset >= 0l && eoffset <= 0xffffl, "Stack access out of extended stack range."); // Stack > 64K.
 
-          emit2 ("ldw", "x, y");
-          cost (1, 1);
+          emit3w (A_LDW, ASMOP_X, ASMOP_Y);
           emit2 ("ldw", "x, (0x%x, x)", (unsigned)eoffset);
           cost (2 + (eoffset > 255), 2);
-          x_free = FALSE;
+          x_free = false;
           size -= 2;
           i += 2;
         }
@@ -2102,9 +2326,11 @@
           cheapMove (result, roffset + i, source, soffset + i, !a_free);
           assigned[i] = TRUE;
           if (aopInReg (result, roffset + i, A_IDX))
-            a_free = FALSE;
+            a_free = false;
           if (aopInReg (result, roffset + i, XL_IDX) || aopInReg (result, roffset + i, XH_IDX))
-            x_free = FALSE;
+            x_free = false;
+          if (aopInReg (result, roffset + i, YL_IDX) || aopInReg (result, roffset + i, YH_IDX))
+            y_free = false;
           size--;
           i++;
         }
@@ -2135,33 +2361,12 @@
           i++;
           continue;
         }
-      else if (i + 1 < sizex && !assigned[i + 1] && (aopInReg (result, roffset + i, X_IDX) || aopInReg (result, roffset + i, Y_IDX)))
-        {
-          if (aopInReg (result, roffset + i, X_IDX))
-            emit3w (A_CLRW, ASMOP_X, 0);
-          else if (aopInReg (result, roffset + i, Y_IDX))
-            emit3w (A_CLRW, ASMOP_Y, 0);
-          i += 2;
-        }
-      else if(x_free && (aopInReg (result, roffset + i, XL_IDX) || aopInReg (result, roffset + i, XH_IDX)))
-        {
-          emit3w (A_CLRW, ASMOP_X, 0);
-          i++;
-        }
-      else if (y_dead && aopIsLitVal (source, soffset + i + 1, 1, 0x00) &&
-        (aopInReg (result, roffset + i, YL_IDX) && result->regs[YH_IDX] < 0 || aopInReg (result, roffset + i, YH_IDX) && result->regs[YL_IDX] < 0))
-        {
-          emit3w (A_CLRW, ASMOP_Y, 0);
-          i++;
-        }
-      else
-        { 
-          cheapMove (result, roffset + i, ASMOP_ZERO, 0, !a_free);
-          assigned[i] = TRUE;
-          if (aopInReg (result, roffset + i, A_IDX))
-            a_free = FALSE;
-          i++;
-        }
+        
+      int s = 1;
+      for (int j = i + 1; j < sizex && !assigned[j]; j++, s++);
+
+      genMove_o (result, roffset + i, ASMOP_ZERO, 0, s, a_free, x_free, y_free);
+      i += s;
     }
 
   if (size)
@@ -2179,6 +2384,79 @@
 }
 
 /*-----------------------------------------------------------------*/
+/* adjustRegW - Set register x or y at result to source,           */
+/* assuming previous value is oldval (-1 for unknown)              */
+/*-----------------------------------------------------------------*/
+void
+adjustRegW (const asmop *result, int roffset, const asmop *source, int soffset, long *val_x, long *val_y)
+{
+  wassert_bt (result && source);
+  wassert_bt (
+    aopInReg (result, roffset, X_IDX) || aopInReg (result, roffset, Y_IDX) ||
+    aopInReg (result, roffset, XH_IDX) && aopInReg (result, roffset + 1, XL_IDX) ||
+    aopInReg (result, roffset, YH_IDX) && aopInReg (result, roffset + 1, YL_IDX));
+  wassert_bt (source->type == AOP_LIT || aopIsLitVal (source, soffset, 2, 0x0000));
+
+  bool swapped = aopInReg (result, roffset, XH_IDX) || aopInReg (result, roffset, YH_IDX);
+  long newval = (source->type == AOP_LIT) ? (byteOfVal (source->aopu.aop_lit, soffset) << (swapped * 8)) + (byteOfVal (source->aopu.aop_lit, soffset + 1) << (8 - swapped * 8)) : 0;
+  bool y = aopInReg (result, roffset, YL_IDX) || aopInReg (result, roffset, YH_IDX);
+  long oldval = y ? *val_y : *val_x;
+  asmop *resreg = y ? ASMOP_Y : ASMOP_X;
+
+  // Value matches, Nothing to be done.
+  if (newval == oldval)
+    ;
+    
+  // Try to use a 1-cycle instruction (1 B for x, 2 B for y)
+  else if (!newval)
+    emit3w (A_CLRW, resreg, 0);
+  else if (oldval != -1 && newval == ((oldval - 1) & 0xffff))
+    emit3w (A_DECW, resreg, 0);
+  else if (oldval != -1 && newval == ((oldval + 1) & 0xffff))
+    emit3w (A_INCW, resreg, 0);
+  else if (oldval != -1 && newval == (((oldval << 8) | (oldval >> 8)) & 0xffff))
+    emit3w (A_SWAPW, resreg, 0);
+  else if (newval == (y ? *val_x : *val_y))
+    emit3w (A_LDW, resreg, y ? ASMOP_X : ASMOP_Y);
+
+  // Try to use a 2-cycle instruction (1 B for x, 2 B for y)
+  else if (oldval != -1 && newval == ((oldval >> 1) & 0xffff))
+    emit3w (A_SRLW, resreg, 0);
+  else if (oldval != -1 && newval == ((oldval << 1) & 0xffff))
+    emit3w (A_SLLW, resreg, 0);
+  else if (oldval != -1 && newval == ((-oldval) & 0xffff))
+    emit3w (A_NEGW, resreg, 0);
+  else if (oldval != -1 && newval == ((~oldval) & 0xffff))
+    emit3w (A_CPLW, resreg, 0);
+  else if (oldval != -1 && newval == (((oldval >> 1) | (oldval & 0x8000)) & 0xffff))
+    emit3w (A_SRAW, resreg, 0);
+
+  // Try to use 2-cycle sequence (2 B for x)
+  else if (!y && newval == 0x0001)
+    {
+      emit3w (A_CLRW, resreg, 0);
+      emit3w (A_INCW, resreg, 0);
+    }
+  else if (!y && newval == 0xffff)
+    {
+      emit3w (A_CLRW, resreg, 0);
+      emit3w (A_DECW, resreg, 0);
+    }
+
+  // Fallback to 2-cycle ldw (3B for x, 4B for y)
+  else
+    {
+      emit2 ("ldw", y ? "y, #0x%04x" : "x, #0x%04x", newval);
+      cost (3 + y, 2);
+    }
+  
+  if (y)
+    *val_y = newval;
+  else
+    *val_x = newval;
+}
+
+/*-----------------------------------------------------------------*/
 /* genMove_o - Copy part of one asmop to another                   */
 /*-----------------------------------------------------------------*/
 static void
@@ -2186,7 +2464,8 @@
 {
   int i;
 
-  bool clr_x = FALSE, clr_y = FALSE;
+  long val_x = -1;
+  long val_y = -1;
 
   wassertl_bt (result->type != AOP_LIT, "Trying to write to literal.");
   wassertl_bt (result->type != AOP_IMMD, "Trying to write to immediate.");
@@ -2244,60 +2523,46 @@
         (!aopRS (result) || (result->regs[A_IDX] >= (roffset + i) || result->regs[A_IDX] < 0)) &&
         (!aopRS (source) || source->regs[A_IDX] <= i);
 
-      if (i + 1 < size && (aopInReg (result, roffset + i, X_IDX) || aopInReg (result, roffset + i, Y_IDX)) && aopIsLitVal (source, soffset + i, 2, 0x0000))
+      if (i + 1 < size && (source->type == AOP_LIT || aopIsLitVal (source, soffset + i, 2, 0x0000)) &&
+        (aopInReg (result, roffset + i, X_IDX) || aopInReg (result, roffset + i, Y_IDX) ||
+        aopInReg (result, roffset + i, XH_IDX) && aopInReg (result, roffset + i + 1, XL_IDX) ||
+        aopInReg (result, roffset + i, YH_IDX) && aopInReg (result, roffset + i + 1, YL_IDX)))
         {
-          if (aopInReg (result, roffset + i, X_IDX) && !clr_x)
-            {
-              emit3w (A_CLRW, ASMOP_X, 0);
-              clr_x = TRUE;
-            }
-          else if (aopInReg (result, roffset + i, Y_IDX) && !clr_y)
-            {
-              emit3w (A_CLRW, ASMOP_Y, 0);
-              clr_y = TRUE;
-            }
+          adjustRegW (result, roffset + i, source, soffset + i, &val_x, &val_y);
           i += 2;
         }
       else if (x_dead && aopIsLitVal (source, soffset + i, 1, 0x00) && (aopInReg (result, roffset + i, XL_IDX) || aopInReg (result, roffset + i, XH_IDX)))
         {
           emit3w (A_CLRW, ASMOP_X, 0);
-          clr_x = true;
+          val_x = 0;
           i++;
         }
       else if (y_dead && aopIsLitVal (source, soffset + i, 1, 0x00) && (aopInReg (result, roffset + i, YL_IDX) || aopInReg (result, roffset + i, YH_IDX)))
         {
           emit3w (A_CLRW, ASMOP_Y, 0);
-          clr_y = true;
+          val_y = 0;
           i++;
         }
-      else if (i + 1 < size && i >= 2 && source->type == AOP_LIT && aopIsLitVal (source, soffset + i, 2, byteOfVal (source->aopu.aop_lit, soffset + i - 2) + byteOfVal (source->aopu.aop_lit, soffset + i - 1) * 256) &&
-        (aopInReg (result, roffset + i, X_IDX) && aopInReg (result, roffset + i - 2, Y_IDX) || aopInReg (result, roffset + i, Y_IDX) && aopInReg (result, roffset + i - 2, X_IDX)))
-        {
-          emit2 ("ldw", "%s, %s", aopGet2 (result, roffset + i), aopGet2 (result, roffset + i - 2));
-          cost (1 + aopInReg (result, roffset + i, Y_IDX), 1);
-          i += 2;
-        }
-      else if (i + 1 < size && aopInReg (result, roffset + i, X_IDX) && (aopIsLitVal (source, soffset + i, 2, 0x0001) || aopIsLitVal (source, soffset + i, 2, 0xffff)))
+      else if (i + 1 < size && aopInReg (result, roffset + i, X_IDX) && (source->type == AOP_DIR && soffset + i + 1 < source->size || source->type == AOP_IMMD))
         {
-          bool dec = aopIsLitVal (source, soffset + i, 2, 0xffff);
-          emit3w (A_CLRW, ASMOP_X, 0);
-          emit3w (dec ? A_DECW : A_INCW, ASMOP_X, 0);
+          emit2 ("ldw", "x, %s", aopGet2 (source, soffset + i));
+          cost (3, 2);
+          val_x = -1;
           i += 2;
         }
-      else if (i + 1 < size && aopInReg (result, roffset + i, X_IDX) &&
-        (source->type == AOP_LIT || source->type == AOP_DIR && soffset + i + 1 < source->size || source->type == AOP_IMMD))
+      else if (i + 1 < size && aopInReg (result, roffset + i, XH_IDX) && aopInReg (result, roffset + i + 1, XL_IDX) && source->type == AOP_DIR && soffset + i + 1 < source->size)
         {
           emit2 ("ldw", "x, %s", aopGet2 (source, soffset + i));
           cost (3, 2);
-          clr_x = FALSE;
+          emit3w (A_SWAPW, ASMOP_X, 0);
+          val_x = -1;
           i += 2;
         }
-      else if (i + 1 < size && aopInReg (result, roffset + i, Y_IDX) &&
-        (source->type == AOP_LIT || source->type == AOP_DIR && soffset + i + 1 < source->size || source->type == AOP_IMMD))
+      else if (i + 1 < size && aopInReg (result, roffset + i, Y_IDX) && (source->type == AOP_DIR && soffset + i + 1 < source->size || source->type == AOP_IMMD))
         {
           emit2 ("ldw", "y, %s", aopGet2 (source, soffset + i));
           cost (4, 2);
-          clr_y = FALSE;
+          val_y = -1;
           i += 2;
         }
       else if (i + 1 < size && result->type == AOP_DIR && aopInReg (source, soffset + i, X_IDX))
@@ -2316,17 +2581,13 @@
         (aopOnStack (result, roffset + i, 2) || result->type == AOP_DIR) &&
         (aopOnStackNotExt (source, soffset + i, 2) || source->type == AOP_LIT || source->type == AOP_DIR && soffset + i + 1 < source->size || source->type == AOP_IMMD))
         {
-          if (aopIsLitVal (source, soffset + i, 2, 0x0000))
-            {
-              if (!clr_x)
-                emit3w (A_CLRW, ASMOP_X, 0);
-              clr_x = TRUE;
-            }
+          if (source->type == AOP_LIT || aopIsLitVal (source, soffset + i, 2, 0x0000))
+            adjustRegW (ASMOP_X, 0, source, soffset + i, &val_x, &val_y);
           else
             {
               emit2 ("ldw", "x, %s", aopGet2 (source, soffset + i));
               cost (3, 2);
-              clr_x = FALSE;
+              val_x = -1;
             }
           emit2 ("ldw", "%s, x", aopGet2 (result, roffset + i));
           cost (2, 2);
@@ -2336,6 +2597,22 @@
         {
           emit3w_o (A_CLRW, result, roffset + i, 0, 0);
           cheapMove (result, roffset + i, source, soffset + i, !a_dead);
+          if (aopInReg (result, roffset + i, X_IDX))
+            val_x = -1;
+          else
+            val_y = -1;
+          i += 2;
+        }
+      else if (i + 1 < size && (aopOnStack(result, roffset + i, 2) || result->type == AOP_DIR) && val_x >= 0 && aopIsLitVal (source, soffset + i, 2, val_x))
+        {
+          emit2 ("ldw", "%s, x", aopGet2 (result, roffset + i));
+          cost (2, 2);
+          i += 2;
+        }
+      else if (i + 1 < size && (aopOnStack(result, roffset + i, 2) || result->type == AOP_DIR) && val_y >= 0 && aopIsLitVal (source, soffset + i, 2, val_y))
+        {
+          emit2 ("ldw", "%s, y", aopGet2 (result, roffset + i));
+          cost (2 + (result->type == AOP_DIR), 2);
           i += 2;
         }
       else if ((!aopRS (result) || aopOnStack(result, roffset + i, 1) || aopInReg (result, roffset + i, A_IDX)) && aopIsLitVal (source, soffset + i, 1, 0x00))
@@ -2346,17 +2623,13 @@
       else if (y_dead && aopOnStack (result, roffset + i, 2) &&
         (source->type == AOP_LIT || source->type == AOP_DIR && soffset + i + 1 < source->size || source->type == AOP_IMMD))
         {
-          if (aopIsLitVal (source, soffset + i, 2, 0x0000))
-            {
-              if (!clr_y)
-                emit3w (A_CLRW, ASMOP_Y, 0);
-              clr_y = TRUE;
-            }
+          if (source->type == AOP_LIT || aopIsLitVal (source, soffset + i, 2, 0x0000))
+            adjustRegW (ASMOP_Y, 0, source, soffset + i, &val_x,&val_y);
           else
             {
               emit2 ("ldw", "y, %s", aopGet2 (source, soffset + i));
               cost (4, 2);
-              clr_y = FALSE;
+              val_y = -1;
             }
           emit2 ("ldw", "%s, y", aopGet2 (result, roffset + i));
           cost (2, 2);
@@ -2367,7 +2640,7 @@
           emit2 ("ldw", "y, %s", aopGet2 (source, soffset + i));
           emit2 ("ldw", "%s, y", aopGet2 (result, roffset + i));
           cost (6, 4);
-          clr_y = FALSE;
+          val_y = -1;
           i += 2;
         }
       else
@@ -2553,101 +2826,196 @@
 }
 
 /*-----------------------------------------------------------------*/
-/* genCpl - generate code for complement                           */
+/* genEor - generates code for bitwise exlusive or                 */
 /*-----------------------------------------------------------------*/
 static void
-genCpl (const iCode *ic)
+genEor (const iCode *ic, asmop *result_aop, asmop *left_aop, asmop *right_aop)
 {
-  operand *result = IC_RESULT (ic);
-  operand *left = IC_LEFT (ic);
-  int left_in_a = 0;
-  bool result_in_a = FALSE;
-  bool destroyed_a = FALSE;
-  bool pushed_a = FALSE;
-  bool result_pushed = FALSE;
-  int i, size;
-
-  D (emit2 ("; genCpl", ""));
-
-  aopOp (left, ic);
-  aopOp (result, ic);
+  int omitbyte = -1;
+  int size = getSize (operandType (IC_RESULT(ic)));
+  bool result_in_a = false;
+  bool pushed_a = false;
+  
+  /* Prefer literal operand on right */
+  if (left_aop->type == AOP_LIT ||
+    right_aop->type != AOP_LIT && left_aop->type == AOP_DIR ||
+    (aopInReg (right_aop, 0, A_IDX) || aopInReg (right_aop, 0, X_IDX) || aopInReg (right_aop, 0, Y_IDX)) && left_aop->type == AOP_STK)
+    {
+      asmop *taop = left_aop;
+      left_aop = right_aop;
+      right_aop = taop;
+    }
 
-  size = result->aop->size;
+  // todo: Use bit complement instructions where it is faster.
+  if (!regDead (A_IDX, ic))
+    {
+      push (ASMOP_A, 0, 1);
+      pushed_a = true;
+    }
 
-  for (i = 1; i < left->aop->size; i++)
-    if (aopInReg (left->aop, i, A_IDX))
+  // Byte in a needs to be handled first.
+  for (int i = 0; i < size; i++)
+    if (aopInReg (left_aop, i, A_IDX) || aopInReg (right_aop, i, A_IDX))
       {
-        left_in_a = i;
-        break;
-      }
+        const asmop *other_stacked = 0;
+        int other_offset;
+        asmop *other = (aopInReg (left_aop, i, A_IDX) ? right_aop : left_aop);
 
-  for (i = 0; i < size;)
-    {
-      // todo: Complement in source where dead and more efficient.
-      if (aopInReg (result->aop, i, X_IDX) || aopInReg (result->aop, i, Y_IDX))
-        {
-          const bool x_free = regDead (X_IDX, ic) &&
-            left->aop->regs[XL_IDX] < i && left->aop->regs[XH_IDX] < i &&
-            (result->aop->regs[XL_IDX] < 0 || result->aop->regs[XL_IDX] >= i) && (result->aop->regs[XH_IDX] < 0 || result->aop->regs[XH_IDX] >= i);
-          const bool y_free = regDead (Y_IDX, ic) &&
-            left->aop->regs[YL_IDX] < i && left->aop->regs[YH_IDX] < i &&
-            (result->aop->regs[YL_IDX] < 0 || result->aop->regs[YL_IDX] >= i) && (result->aop->regs[YH_IDX] < 0 || result->aop->regs[YH_IDX] >= i);
-          genMove_o (result->aop, i, left->aop, i, 2, (regDead (A_IDX, ic) || pushed_a) && !result_in_a && !(left_in_a > i), x_free, y_free);
+        other_stacked = stack_aop (other, i, &other_offset);
+
+        if (aopIsLitVal (right_aop, i, 1, 0))
+          ;
+        else if (aopIsLitVal (right_aop, i, 1, 0xff))
+          emit3 (A_CPL, ASMOP_A, 0);
+        else if (!other_stacked)
+          emit3_o (A_XOR, ASMOP_A, 0, other, i);
+        else
+          {
+            emit2 ("xor", "a, (%d, sp)", other_offset);
+            cost (2, 1);
+          }
+        omitbyte = i;
 
-          emit3w_o (A_CPLW, result->aop, i, 0, 0);
+        if (other_stacked)
+          pop (other_stacked, 0, 2);
 
-          i += 2;
+        if (aopInReg (result_aop, i, A_IDX) && size > 1)
+          result_in_a = true;
+        else
+          {
+            // Avoid overwriting operand.
+            if (aopRS (result_aop) && !aopOnStack (result_aop, i, 1))
+              for (int j = 0; j < size; j++)
+                {
+                  if (i == j)
+                    continue;
+                  if (j < left_aop->size && aopRS (left_aop) && !aopOnStack (left_aop, j, 1) &&
+                    left_aop->aopu.bytes[j].byteu.reg->rIdx == result_aop->aopu.bytes[i].byteu.reg->rIdx ||
+                    j < right_aop->size && aopRS (right_aop) && !aopOnStack (right_aop, j, 1) &&
+                    right_aop->aopu.bytes[j].byteu.reg->rIdx == result_aop->aopu.bytes[i].byteu.reg->rIdx)
+                    {
+                      if (!regalloc_dry_run)
+                        wassertl (0, "Unimplemented xor operand.");
+                      cost (180, 180);
+                    }
+                }
+
+            cheapMove (result_aop, i, ASMOP_A, 0, false);
+          }
+        break;
+      }
+
+  for (int i = 0; i < size; i++)
+    {
+      const asmop *right_stacked = 0;
+      int right_offset;
+
+      if (omitbyte == i)
+        continue;
+
+      if (aopIsLitVal (right_aop, i, 1, 0))
+        {
+          cheapMove (result_aop, i, left_aop, i, result_in_a);
+          if (aopInReg (result_aop, i, A_IDX))
+            result_in_a = true;
+          continue;
+        }
+      else if ((aopOnStack (result_aop, i, 1) || result_aop->type == AOP_DIR) && aopSame (result_aop, i, left_aop, i, 1) &&
+        aopIsLitVal (right_aop, i, 1, 0xff))
+        {
+          emit3_o (A_CPL, result_aop, i, 0, 0);
+          continue;
         }
-      else if ((aopOnStack (result->aop, i, 1) || result->aop->type == AOP_DIR) && aopSame (result->aop, i, left->aop, i, 1))
+      else if ((aopInReg (result_aop, i, X_IDX) || aopInReg (result_aop, i, Y_IDX)) &&
+        aopIsLitVal (right_aop, i, 2, 0xffff))
         {
-          emit3_o (A_CPL, result->aop, i, 0, 0);
+          const bool x_free = regDead (X_IDX, ic) &&
+            left_aop->regs[XL_IDX] <= i + 1 && left_aop->regs[XH_IDX] <= i + 1 &&
+            (result_aop->regs[XL_IDX] < 0 || result_aop->regs[XL_IDX] >= i) && (result_aop->regs[XH_IDX] < 0 || result_aop->regs[XH_IDX] >= i);
+          const bool y_free = regDead (Y_IDX, ic) &&
+            left_aop->regs[YL_IDX] <= i + 1 && left_aop->regs[YH_IDX] <= i + 1 &&
+            (result_aop->regs[YL_IDX] < 0 || result_aop->regs[YL_IDX] >= i) && (result_aop->regs[YH_IDX] < 0 || result_aop->regs[YH_IDX] >= i);
+
+          genMove_o (result_aop, i, left_aop, i, 2, (regDead (A_IDX, ic) || pushed_a) && !result_in_a, x_free, y_free);
+          emit3w_o (A_CPLW, result_aop, i, 0, 0);
+          
           i++;
+          continue;
         }
-      else
+      else if ((aopInReg (left_aop, i, X_IDX) && regDead (X_IDX, ic) || aopInReg (left_aop, i, Y_IDX) && regDead (Y_IDX, ic)) &&
+        aopIsLitVal (right_aop, i, 2, 0xffff))
         {
-          bool pushed_left = destroyed_a && aopInReg (left->aop, i, A_IDX);
+          const bool x_free = regDead (X_IDX, ic) &&
+            left_aop->regs[XL_IDX] <= i + 1 && left_aop->regs[XH_IDX] <= i + 1 &&
+            (result_aop->regs[XL_IDX] < 0 || result_aop->regs[XL_IDX] >= i) && (result_aop->regs[XH_IDX] < 0 || result_aop->regs[XH_IDX] >= i);
+          const bool y_free = regDead (Y_IDX, ic) &&
+            left_aop->regs[YL_IDX] <= i + 1 && left_aop->regs[YH_IDX] <= i + 1 &&
+            (result_aop->regs[YL_IDX] < 0 || result_aop->regs[YL_IDX] >= i) && (result_aop->regs[YH_IDX] < 0 || result_aop->regs[YH_IDX] >= i);
+          
+          emit3w_o (A_CPLW, left_aop, i, 0, 0);
+          genMove_o (result_aop, i, left_aop, i, 2, (regDead (A_IDX, ic) || pushed_a) && !result_in_a, x_free, y_free);
+          
+          i++;
+          continue;
+        }   
 
-          if ((left_in_a > i || !regDead (A_IDX, ic) || result_in_a) && !pushed_a)
-            {
-              push (ASMOP_A, 0, 1);
-              pushed_a = TRUE;
-              if (result_in_a)
-                {
-                  result_in_a = FALSE;
-                  result_pushed = TRUE;
-                }
-            }
+      if (left_aop->type == AOP_DIR && aopSame (left_aop, i, result_aop, i, 1) &&
+        right_aop->type == AOP_LIT && isLiteralBit (byteOfVal (right_aop->aopu.aop_lit, i)) >= 0)
+        {
+          emit2 ("bcpl", "%s, #%d", aopGet (left_aop, i), isLiteralBit (byteOfVal (right_aop->aopu.aop_lit, i)));
+          cost (4, 1);
+          continue;
+        }
 
-          if (pushed_left && !regDead (A_IDX, ic))
-            {
-              pop (ASMOP_A, 0, 1);
-              pushed_a = FALSE;
-            }
-          else if (pushed_left)
-            {
-              emit2 ("ld", "a, (1, sp)");
-              cost (2, 1);
-            }
-          else
-            cheapMove (ASMOP_A, 0, left->aop, i, FALSE);
+      right_stacked = stack_aop (right_aop, i, &right_offset);
 
-          destroyed_a = TRUE;
+      if (result_in_a)
+        {
+          push (ASMOP_A, 0, 1);
+          pushed_a = true;
+          result_in_a = false;
+        }
 
-          emit3 (A_CPL, ASMOP_A, 0);
+      cheapMove (ASMOP_A, 0, left_aop, i, false);
 
-          cheapMove (result->aop, i, ASMOP_A, 0, FALSE);
+      if (aopIsLitVal (right_aop, i, 1, 0xff))
+        emit3 (A_CPL, ASMOP_A, 0);
+      else if (!right_stacked && !(i && aopInReg (right_aop, i, A_IDX)))
+        emit3_o (A_XOR, ASMOP_A, 0, right_aop, i);
+      else
+        {
+          emit2 ("xor", "a, (%d, sp)", right_offset);
+          cost (2, 1);
+        }
 
-          if (aopInReg (result->aop, i, A_IDX))
-            result_in_a = TRUE;
+      if (right_stacked)
+        pop (right_stacked, 0, 2);
 
-          i++;
-        }
+      if (!aopInReg (result_aop, i, A_IDX))
+        cheapMove (result_aop, i, ASMOP_A, 0, false);
+      else
+        result_in_a = true;
     }
 
-  if (pushed_a && !regDead (A_IDX, ic) || result_pushed)
+  if (pushed_a)
     pop (ASMOP_A, 0, 1);
-  else if (pushed_a)
-    adjustStack (1, FALSE, FALSE, FALSE);
+}
+
+/*-----------------------------------------------------------------*/
+/* genCpl - generate code for complement                           */
+/*-----------------------------------------------------------------*/
+static void
+genCpl (const iCode *ic)
+{
+  operand *result = IC_RESULT (ic);
+  operand *left = IC_LEFT (ic);
+
+  D (emit2 ("; genCpl", ""));
+
+  aopOp (left, ic);
+  aopOp (result, ic);
+
+  genEor (ic, result->aop, left->aop, ASMOP_MONE);
 
   freeAsmop (left);
   freeAsmop (result);
@@ -2690,8 +3058,18 @@
           if (!y && !x_free)
             push (ASMOP_X, 0, 2);
           emit2 ("ldw", y ? "y, sp" : "x, sp");
-          emit2 ("addw", y ? "y, #%ld" : "x, #%ld", (long)(left_aop->aopu.stk_off) + G.stack.pushed - offset);
-          cost (4 + 2 * y, 3);
+          cost (1 + y, 1);
+          switch ((long)(left_aop->aopu.stk_off) + G.stack.pushed - offset)
+            {
+            case 2:
+              emit3w (A_INCW, y ? ASMOP_Y : ASMOP_X, 0);
+            case 1:
+              emit3w (A_INCW, y ? ASMOP_Y : ASMOP_X, 0);
+              break;
+            default:
+              emit2 ("addw", y ? "y, #%ld" : "x, #%ld", (long)(left_aop->aopu.stk_off) + G.stack.pushed - offset);
+              cost (3 + y, 2);
+            }
           if (!lit)
             {
               emit2 ("subw", y ? "y, %s" : "x, %s", aopGet2 (right_aop, i));
@@ -3241,41 +3619,86 @@
           cost (180, 180);
         }
 
-      emit2 ("ldw", "x, sp");
-      emit2 ("addw", "x, #%d", IC_RESULT (ic)->aop->aopu.bytes[getSize (ftype->next) - 1].byteu.stk + G.stack.pushed);
-      cost (2 + 4, 1 + 2);
-      push (ASMOP_X, 0, 2);
+      if (stm8_extend_stack && !stm8IsParmInCall(ftype, "y") && ic->op != PCALL && optimize.codeSpeed) // 6 bytes, 4 cycles.
+        {
+          emit2 ("addw", "y, #%d", IC_RESULT (ic)->aop->aopu.bytes[getSize (ftype->next) - 1].byteu.stk + G.stack.size - 256 + G.stack.pushed);
+          cost (4, 2);
+          push (ASMOP_Y, 0, 2);
+        }
+      else if (!stm8IsParmInCall(ftype, "x")) // 5 bytes, 5 cycles.
+        {
+          emit2 ("ldw", "x, sp");
+          emit2 ("addw", "x, #%d", IC_RESULT (ic)->aop->aopu.bytes[getSize (ftype->next) - 1].byteu.stk + G.stack.pushed);
+          cost (1 + 3, 1 + 2);
+          push (ASMOP_X, 0, 2);
+        }
+      else if (!stm8IsParmInCall(ftype, "y")) // 8 bytes, 6 cycles.
+        {
+          emit2 ("ldw", "y, sp");
+          emit2 ("addw", "y, #%d", IC_RESULT (ic)->aop->aopu.bytes[getSize (ftype->next) - 1].byteu.stk + G.stack.pushed);
+          cost (2 + 4, 1 + 2);
+          push (ASMOP_Y, 0, 2);
+        }
+      else
+        wassertl (0, "Big return value requires free x or y, but both are used for register parameters.");
 
       freeAsmop (IC_RESULT (ic));
     }
   // Check if we can do tail call optimization.
   else if (!(currFunc && IFFUNC_ISISR (currFunc->type)) &&
-    (!SomethingReturned || IC_RESULT (ic)->aop->size == 1 && aopInReg (IC_RESULT (ic)->aop, 0, A_IDX) || IC_RESULT (ic)->aop->size == 2 && aopInReg (IC_RESULT (ic)->aop, 0, X_IDX)) &&
-    !ic->parmBytes && !ic->localEscapeAlive)
+    (!SomethingReturned || aopInReg (IC_RESULT (ic)->aop, 0, aopRet (ftype)->aopu.bytes[0].byteu.reg->rIdx) &&
+      (IC_RESULT (ic)->aop->size <= 1 || aopInReg (IC_RESULT (ic)->aop, 1, aopRet (ftype)->aopu.bytes[1].byteu.reg->rIdx)) &&
+      (IC_RESULT (ic)->aop->size <= 2 || aopInReg (IC_RESULT (ic)->aop, 2, aopRet (ftype)->aopu.bytes[2].byteu.reg->rIdx)) &&
+      (IC_RESULT (ic)->aop->size <= 3 || aopInReg (IC_RESULT (ic)->aop, 3, aopRet (ftype)->aopu.bytes[3].byteu.reg->rIdx)) &&
+      IC_RESULT (ic)->aop->size <= 4) &&
+    !ic->parmBytes && !bigreturn &&
+    (!isFuncCalleeStackCleanup (currFunc->type) || !ic->parmEscapeAlive && options.model != MODEL_LARGE && !IFFUNC_ISCOSMIC (ftype) && !optimize.codeSize && ic->op == CALL) &&
+    !ic->localEscapeAlive &&
+    !(ic->op == PCALL && (left->aop->type == AOP_STK || left->aop->type == AOP_REGSTK)) && // Avoid destroying the pointer that we need to call
+    !(options.model != MODEL_LARGE && !IFFUNC_ISCOSMIC (currFunc->type) && IFFUNC_ISCOSMIC (ftype))) // __cosmic uses 24 bits for return address on stack frame. Can only optimize tail call to __cosmic callee, if caller also uses 24 bits.
     {
       int limit = 16; // Avoid endless loops in the code putting us into an endless loop here.
 
+      if (isFuncCalleeStackCleanup (currFunc->type))
+        {
+           const bool caller_bigreturn = currFunc->type->next && (getSize (currFunc->type->next) > 4) || IS_STRUCT (currFunc->type->next);
+           int caller_stackparmbytes = caller_bigreturn * 2;
+           for (value *caller_arg = FUNC_ARGS(currFunc->type); caller_arg; caller_arg = caller_arg->next)
+             {
+               wassert (caller_arg->sym);
+               if (!SPEC_REGPARM (caller_arg->etype))
+                 caller_stackparmbytes += getSize (caller_arg->sym->type);
+             }
+           prestackadjust += caller_stackparmbytes;
+        }
+
       for (const iCode *nic = ic->next; nic && --limit;)
         {
           const symbol *targetlabel = 0;
 
           if (nic->op == LABEL)
             ;
-          else if (nic->op == GOTO) // We dont have ebbi here, so we cant jsut use eBBWithEntryLabel (ebbi, ic->label). Search manually.
+          else if (nic->op == GOTO) // We dont have ebbi here, so we can't just use eBBWithEntryLabel (ebbi, ic->label). Search manually.
             targetlabel = IC_LABEL (nic);
           else if (nic->op == RETURN && (!IC_LEFT (nic) || SomethingReturned && IC_RESULT (ic)->key == IC_LEFT (nic)->key))
             targetlabel = returnLabel;
           else if (nic->op == ENDFUNCTION)
             {
               if (OP_SYMBOL (IC_LEFT (nic))->stack <= (optimize.codeSize ? 250 : 510))
-                {
-                  prestackadjust = OP_SYMBOL (IC_LEFT (nic))->stack;
-                  tailjump = true;
-                }
+                if (!isFuncCalleeStackCleanup (currFunc->type) || prestackadjust <= 250)
+                  {
+                    prestackadjust += OP_SYMBOL (IC_LEFT (nic))->stack;
+                    tailjump = true;
+                    break;
+                  }
+              prestackadjust = 0;
               break;
             }
           else
-            break;
+            {
+              prestackadjust = 0;
+              break;
+            }
 
           if (targetlabel)
             {
@@ -3288,7 +3711,11 @@
                   if (nnic->op == LABEL && IC_LABEL (nnic)->key == targetlabel->key)
                     break;
               if (!nnic)
-                break;
+                {
+                  prestackadjust = 0;
+                  tailjump = false;
+                  break;
+                }
 
               nic = nnic;
             }
@@ -3301,7 +3728,7 @@
 
   if (ic->op == PCALL)
     {
-      if (options.model == MODEL_LARGE && left->aop->type == AOP_DIR)
+      if ((options.model == MODEL_LARGE || IFFUNC_ISCOSMIC (ftype)) && left->aop->type == AOP_DIR)
         {
           wassertl (left->aop->size == 3, "Functions pointers should be 24 bits in large memory model.");
 
@@ -3310,7 +3737,7 @@
           emit2 (jump ? "jpf" : "callf", "[%s]", left->aop->aopu.aop_dir);
           cost (4, jump ? 6 : 8);
         }
-      else if (options.model == MODEL_LARGE)
+      else if (options.model == MODEL_LARGE || IFFUNC_ISCOSMIC (ftype))
         {
           wassertl (left->aop->size == 3, "Functions pointers should be 24 bits in large memory model.");
 
@@ -3332,21 +3759,49 @@
 
           if (aopInReg (left->aop, 0, X_IDX) || aopInReg (left->aop, 0, Y_IDX))
             push (left->aop, 0, 2);
-          else if (aopOnStackNotExt (left->aop, 0, 2) && !(aopInReg (left->aop, 2, XL_IDX) || aopInReg (left->aop, 2, XH_IDX)) ||
-            aopInReg (left->aop, 2, A_IDX))
+          else if ((aopOnStackNotExt (left->aop, 0, 2) || !stm8IsParmInCall(ftype, "y")) &&
+            !aopInReg (left->aop, 2, XL_IDX) && !aopInReg (left->aop, 2, XH_IDX) &&
+            !stm8IsParmInCall(ftype, "x"))
             {
-              genMove (ASMOP_X, left->aop, !aopInReg (left->aop, 2, A_IDX), true, false);
+              genMove (ASMOP_X, left->aop, !aopInReg (left->aop, 2, A_IDX), true, !stm8IsParmInCall(ftype, "y"));
               push (ASMOP_X, 0, 2);
             }
-          else
+          else if (!stm8IsParmInCall(ftype, "a") && left->aop->regs[A_IDX] < 1)
             {
               cheapMove (ASMOP_A, 0, left->aop, 0, false);
               push (ASMOP_A, 0, 1);
               cheapMove (ASMOP_A, 0, left->aop, 1, false);
               push (ASMOP_A, 0, 1);
             }
-          cheapMove (ASMOP_A, 0, left->aop, 2, false);
-          push (ASMOP_A, 0, 1);
+          else if (aopOnStackNotExt (left->aop, 1, 1) && !stm8IsParmInCall(ftype, "y"))
+            {
+              genMove (ASMOP_Y, left->aop, false, false, true);
+              push (ASMOP_Y, 0, 2);
+            }
+          else
+            {
+              cost (500, 500);
+              wassert (regalloc_dry_run);
+            }
+          if (!stm8IsParmInCall(ftype, "a"))
+            {
+              cheapMove (ASMOP_A, 0, left->aop, 2, false);
+              push (ASMOP_A, 0, 1);
+            }
+          else if (!stm8IsParmInCall(ftype, "xl"))
+            {
+              cheapMove (ASMOP_X, 0, left->aop, 2, true);
+              push (ASMOP_X, 0, 2);
+              adjustStack (1, false, false, false);
+            }
+          else if (!stm8IsParmInCall(ftype, "yl"))
+            {
+              cheapMove (ASMOP_Y, 0, left->aop, 2, true);
+              push (ASMOP_Y, 0, 2);
+              adjustStack (1, false, false, false);
+            }
+          else
+            wassert (0);
           emit2("retf", "");
           cost (1, 5);
 
@@ -3363,32 +3818,82 @@
             {
               adjustStack (prestackadjust, true, true, true);
 
-              emit2 (jump ? "jp" : "call", "%s", aopGet2 (left->aop, 0));
+              if (left->aop->type == AOP_LIT)
+                emit2 (jump ? "jp" : "call", "0x%02x%02x", byteOfVal (left->aop->aopu.aop_lit, 1), byteOfVal (left->aop->aopu.aop_lit, 0));
+              else
+                emit2 (jump ? "jp" : "call", "%s", left->aop->aopu.immd);
               cost (3, jump ? 1 : 4);
             }
-          else if (aopInReg (left->aop, 0, Y_IDX)) // Faster than going through x.
+          else if ((aopInReg (left->aop, 0, Y_IDX) || stm8IsParmInCall(ftype, "x")) && !stm8IsParmInCall(ftype, "y")) // Faster than going through x.
             {
+              genMove (ASMOP_Y, left->aop, !stm8IsParmInCall(ftype, "a"), !stm8IsParmInCall(ftype, "x"), true);
+
               adjustStack (prestackadjust, true, true, false);
 
               emit2 (jump ? "jp" : "call", "(y)");
               cost (2,jump ? 1 : 4);
             }
-          else
+          else if (!stm8IsParmInCall(ftype, "x"))
             {
-              genMove (ASMOP_X, left->aop, true, true, true);
+              genMove (ASMOP_X, left->aop, !stm8IsParmInCall(ftype, "a"), true, !stm8IsParmInCall(ftype, "y"));
 
               adjustStack (prestackadjust, true, false, true);
           
               emit2 (jump ? "jp" : "call", "(x)");
               cost (1, jump ? 1 : 4);
             }
+          else
+            {
+              if (stm8IsParmInCall(ftype, "a"))
+                {
+                  cost (500, 500);
+                  wassert (regalloc_dry_run);
+                }
+
+              adjustStack (prestackadjust, left->aop->regs[A_IDX] < 0, left->aop->regs[XL_IDX] < 0 && left->aop->regs[XH_IDX] < 0, left->aop->regs[YL_IDX] < 0 && left->aop->regs[YH_IDX] < 0);
+                
+              symbol *tlbl = (regalloc_dry_run ? 0 : newiTempLabel (NULL));
+
+              if (!jump)
+                {
+                  if (!regalloc_dry_run)
+                    {
+                      emit2("push", "#(!tlabel)", labelKey2num (tlbl->key));
+                      emit2("push", "#(!tlabel >> 8)", labelKey2num (tlbl->key));
+                    }
+                  G.stack.pushed += 2;
+                  cost (4, 2);
+                }
+
+              cheapMove (ASMOP_A, 0, left->aop, 0, false);
+              push (ASMOP_A, 0, 1);
+              cheapMove (ASMOP_A, 0, left->aop, 1, false);
+              push (ASMOP_A, 0, 1);
+              emit2 ("ret", "");
+              cost (1, 4);
+
+              G.stack.pushed -= 2 * (2 - jump);
+
+              if (!jump)
+                emitLabel (tlbl);
+            }
         }
     }
   else
     {
+      if (isFuncCalleeStackCleanup (currFunc->type) && prestackadjust && !IFFUNC_ISNORETURN (ftype)) // Copy return value into correct location on stack for tail call optimization.
+        {
+          wassert (options.model != MODEL_LARGE && !IFFUNC_ISCOSMIC (ftype));
+          bool use_y = stm8IsParmInCall(ftype, "x");
+          wassert (G.stack.pushed + 1 <= 255 && prestackadjust + 1 <= 255);
+          emit2 ("ldw", use_y ? "y, (%d, sp)" : "x, (%d, sp)", G.stack.pushed + 1);
+          emit2 ("ldw", use_y ? "(%d, sp), y" : "(%d, sp), x", prestackadjust + 1);
+          cost (4, 4);
+        }
+
       adjustStack (prestackadjust, true, true, true);
 
-      if (options.model == MODEL_LARGE)
+      if (options.model == MODEL_LARGE || IFFUNC_ISCOSMIC (ftype))
         {
           if (IS_LITERAL (etype))
             emit2 (jump ? "jpf" : "callf", "0x%06X", ulFromVal (OP_VALUE (left)));
@@ -3411,76 +3916,109 @@
   freeAsmop (left);
   G.stack.pushed += prestackadjust;
 
+  // Adjust the stack for parameters if required.
   if (ic->parmBytes || bigreturn)
-    adjustStack (ic->parmBytes + bigreturn * 2, !(SomethingReturned && getSize (ftype->next) == 1), !(SomethingReturned && (getSize (ftype->next) == 2 || getSize (ftype->next) == 4)), !(SomethingReturned && getSize (ftype->next) == 4));
+    {
+      const bool a_free = !aopRet (ftype) || aopRet (ftype)->regs[A_IDX] < 0;
+      const bool x_free = !aopRet (ftype) || (aopRet (ftype)->regs[XL_IDX] < 0 && aopRet (ftype)->regs[XH_IDX] < 0);
+      const bool y_free = !aopRet (ftype) || (aopRet (ftype)->regs[YL_IDX] < 0 && aopRet (ftype)->regs[YH_IDX] < 0);
+      if (IFFUNC_ISNORETURN (ftype) || isFuncCalleeStackCleanup (ftype))
+        {
+          G.stack.pushed -= ic->parmBytes + bigreturn * 2;
+          updateCFA ();
+        }
+      else
+        adjustStack (ic->parmBytes + bigreturn * 2, a_free, x_free, y_free);
+    }
 
-  const bool half = stm8_extend_stack && SomethingReturned && getSize (ftype->next) == 4;
 
-  /* Todo: More efficient handling of long return value for function with extendeds stack when the result value does not use the extended stack. */
+  const bool result_in_frameptr = stm8_extend_stack && SomethingReturned && !bigreturn && (aopRet (ftype)->regs[YL_IDX] >= 0 || aopRet (ftype)->regs[YH_IDX] >= 0);
 
-  /* Special handling of assignment of long result value when using extended stack. */
-  if (half)
+  asmop *result = IC_RESULT (ic)->aop;
+
+  if (result_in_frameptr)
     {
-      asmop *result;
-      int save_a = 0;
+      bool result_in_extstk = (result->type == AOP_STK || result->type == AOP_REGSTK) && !(!regalloc_dry_run && aopOnStackNotExt (result, 0, result->size));
 
-      result = IC_RESULT (ic)->aop;
+      if (result->size == 1 && aopInReg (result, 0, XL_IDX) && aopInReg (aopRet (ftype), 0, YL_IDX) ||
+        result->size == 2 && aopInReg (aopRet (ftype), 0, Y_IDX) && result_in_extstk)
+        {
+          pop (ASMOP_X, 0, 2);
+          emit2 ("exgw", "x, y");
+          cost (1, 1);
+          genMove (result, ASMOP_X, true, true, !stm8_extend_stack);
+        }
+      else if (!result_in_extstk)
+        {
+          genMove (result, aopRet (ftype), true, true, true);
+          pop (ASMOP_Y, 0, 2);
+        }
+      else if (result->size == 1)
+        {
+          genMove (ASMOP_A, aopRet (ftype), true, true, true);
+          pop (ASMOP_Y, 0, 2);
+          genMove (result, ASMOP_A, true, true, !stm8_extend_stack);
+        }
+      else if (result->size == 2)
+        {
+          genMove (ASMOP_X, aopRet (ftype), true, true, true);
+          pop (ASMOP_Y, 0, 2);
+          genMove (result, ASMOP_X, true, true, !stm8_extend_stack);
+        }
+      else
+        {
+          push (ASMOP_Y, 0, 2);
 
-      push (ASMOP_Y, 0, 2);
-      emit2 ("ldw", "y, (3, sp)");
-      cost (2, 2);
+          // Restore frame pointer
+          emit2 ("ldw", "y, (3, sp)");
+          cost (2, 2);
 
-      emit2 ("ld", "a, (2, sp)");
-      cost (2, 1);
-      if (IC_RESULT (ic)->aop->size > 2)
-        cheapMove (IC_RESULT (ic)->aop, 2, ASMOP_A, 0, TRUE);
-      if (result->size > 2)
-        if (aopRS (result) && aopRS (ASMOP_A) &&
-          result->aopu.bytes[2].in_reg && ASMOP_A->aopu.bytes[0].in_reg &&
-          result->aopu.bytes[2].byteu.reg == ASMOP_A->aopu.bytes[0].byteu.reg)
+          for(int i = 0; i < result->size; i++)
             {
-              push (ASMOP_A, 0, 1);
-              save_a = 1;
-            }
+              bool a_dead = (result->regs[A_IDX] < 0 || result->regs[A_IDX] >= i);
 
-      if (save_a)
-        emit2 ("ld", "a, (2, sp)");
-      else
-        emit2 ("ld", "a, (1, sp)");
-      cost (2, 1);
-      if (IC_RESULT (ic)->aop->size > 3)
-        cheapMove (IC_RESULT (ic)->aop, 3, ASMOP_A, 0, TRUE);
-      if (save_a)
-        {
-          pop (ASMOP_A, 0, 1);
-          save_a = 0;
-        }
+              if (result->aopu.bytes[i].in_reg &&
+                !aopInReg (result, i, YL_IDX) && !aopInReg (result, i, YH_IDX) &&
+                aopRet (ftype)->regs[result->aopu.bytes[i].byteu.reg->rIdx] > i && aopRet (ftype)->regs[result->aopu.bytes[i].byteu.reg->rIdx] < result->size)
+                {
+                  cost (300, 300);
+                  wassert (regalloc_dry_run);
+                }
 
-      adjustStack (4, FALSE, FALSE, FALSE);
+              if (aopInReg (aopRet (ftype), i, YL_IDX) || aopInReg (aopRet (ftype), i, YH_IDX))
+                {
+                  if (!a_dead)
+                    push (ASMOP_A, 0, 1);
+                  emit2 ("ld", "a, (%d, sp)", 1 + !a_dead + aopInReg (aopRet (ftype), i, YL_IDX));
+                  cost (2, 1);
+                  cheapMove (result, i, ASMOP_A, 0, true);
+                  if (!a_dead)
+                    pop (ASMOP_A, 0, 1);
+                }
+              else
+                cheapMove (result, i, aopRet (ftype), i, !a_dead);
+            }
 
-      if (IC_RESULT (ic)->aop->regs[XL_IDX] >= 2 || IC_RESULT (ic)->aop->regs[XH_IDX] >= 2)
-        {
-          wassert (regalloc_dry_run);
-          cost (180, 180);
+          adjustStack (4, aopRet (ftype)->regs[A_IDX] < 0, aopRet (ftype)->regs[XL_IDX] < 0 && aopRet (ftype)->regs[XH_IDX] < 0, false);
         }
+
+      goto restore;
     }
-  else if (stm8_extend_stack)
+
+  if (stm8_extend_stack)
     pop (ASMOP_Y, 0, 2);
 
   /* if we need assign a result value */
   if (SomethingReturned && !bigreturn)
     {
-      int size;
-
-      size = !half ? IC_RESULT (ic)->aop->size : (IC_RESULT (ic)->aop->size > 2 ? 2 : IC_RESULT (ic)->aop->size);   
-
       wassert (getSize (ftype->next) >= 1 && getSize (ftype->next) <= 4);
-
-      genMove_o (IC_RESULT (ic)->aop, 0, getSize (ftype->next) == 1 ? ASMOP_A : ASMOP_XY, 0, size, TRUE, TRUE, !stm8_extend_stack);
-
-      freeAsmop (IC_RESULT (ic));
+      genMove (result, aopRet (ftype), true, true, !stm8_extend_stack);
     }
 
+restore:
+  if (SomethingReturned && !bigreturn)
+    freeAsmop (IC_RESULT (ic));
+
   // Restore regs.
   if (!regDead (Y_IDX, ic) && !stm8_extend_stack)
     if (regDead (YH_IDX, ic))
@@ -3573,6 +4111,7 @@
 
   if (IFFUNC_ISNAKED(ftype))
   {
+      updateCFA(); //ensure function has at least 1 CFA record
       emit2(";", "naked function: no prologue.");
       return;
   }
@@ -3615,12 +4154,26 @@
   bigreturn = (getSize (ftype->next) > 4);
   G.stack.param_offset += bigreturn * 2;
 
+  // Cosmic stack frame always uses 24-bit return address.
+  if (IFFUNC_ISCOSMIC (ftype) && options.model != MODEL_LARGE)
+    G.stack.param_offset++;
+
   if (options.debug && !regalloc_dry_run)
     debugFile->writeFrameAddress (NULL, &stm8_regs[SP_IDX], 1);
 
   /* adjust the stack for the function */
-  if (sym->stack)
-    adjustStack (-sym->stack, TRUE, TRUE, !stm8_extend_stack);
+  {
+    int fadjust = -sym->stack;
+    if (stm8_extend_stack && G.stack.size - 256 >= 255 && // Using frame pointer speeds up stack adjustment (unless we add in x anyway).
+      fadjust < -255 && fadjust >= -255 - (G.stack.size - 256))
+      {
+        emit2 ("ldw", "sp, y");
+        G.stack.pushed += (G.stack.size - 256);
+        fadjust += G.stack.size - 256;
+        updateCFA ();
+      }
+    adjustStack (fadjust, true, true, !stm8_extend_stack);
+  }
 }
 
 /*-----------------------------------------------------------------*/
@@ -3630,7 +4183,6 @@
 genEndFunction (iCode *ic)
 {
   symbol *sym = OP_SYMBOL (IC_LEFT (ic));
-  int retsize = getSize (sym->type->next);
 
   D (emit2 ("; genEndFunction", ""));
 
@@ -3644,12 +4196,93 @@
       return;
   }
 
-  /* adjust the stack for the function */
-  if (sym->stack)
-    adjustStack (sym->stack, retsize != 1, retsize != 2 && retsize != 4, retsize != 4);
+  const bool bigreturn = (getSize (sym->type->next) > 4) || IS_STRUCT (sym->type->next);
+  int stackparmbytes = bigreturn * 2;
+  for (value *arg = FUNC_ARGS(sym->type); arg; arg = arg->next)
+    {
+      wassert (arg->sym);
+      if (!SPEC_REGPARM (arg->etype))
+        stackparmbytes += getSize (arg->sym->type);
+    }
+
+  int poststackadjust = isFuncCalleeStackCleanup (sym->type) ? stackparmbytes : 0;
+
+  bool a_free = !aopRet (sym->type) || aopRet (sym->type)->regs[A_IDX] < 0;
+  bool x_free = !aopRet (sym->type) || (aopRet (sym->type)->regs[XL_IDX] < 0 && aopRet (sym->type)->regs[XH_IDX] < 0);
+  bool y_free = !aopRet (sym->type) || (aopRet (sym->type)->regs[YL_IDX] < 0 && aopRet (sym->type)->regs[YH_IDX] < 0);
+
+  // Adjust the stack for the function.
+  if ((poststackadjust > 1 && x_free || poststackadjust > 2 && y_free) && // Try to do both stack adjustments at once.
+    options.model != MODEL_LARGE && !IFFUNC_ISCOSMIC (sym->type) &&
+    sym->stack < 255 - 1 &&
+    !IFFUNC_ISISR (sym->type) && !IFFUNC_ISCRITICAL (sym->type))
+    {
+      emit2 ("ldw", x_free ? "x, (%d, sp)" : "y, (%d, sp)", sym->stack+ 1);
+      cost (2, 2);
+      adjustStack (sym->stack + 2 + poststackadjust, a_free, false, x_free ? y_free : false);
+      emit2 ("jp", x_free ? "(x)" : "(y)");
+      cost (1 + !x_free, 1);
+      return;
+    }
+  else if (sym->stack) // Only do the first one for now.
+    adjustStack (sym->stack, a_free, x_free, y_free);
 
   wassertl (!G.stack.pushed, "Unbalanced stack.");
 
+  if (poststackadjust)
+    {
+      if (x_free && options.model != MODEL_LARGE && !IFFUNC_ISISR (sym->type) && !IFFUNC_ISCOSMIC (sym->type))
+        {
+          pop (ASMOP_X, 0, 2);
+          adjustStack (poststackadjust, a_free, false, y_free);
+          if (IFFUNC_ISCRITICAL (sym->type))
+            genEndCritical (NULL);
+          emit2 ("jp", "(x)");
+          cost (1, 1);
+          return;
+        }
+      else if (y_free && options.model != MODEL_LARGE && !IFFUNC_ISISR (sym->type) && !IFFUNC_ISCOSMIC (sym->type))
+        {
+          pop (ASMOP_Y, 0, 2);
+          adjustStack (poststackadjust, a_free, x_free, false);
+          if (IFFUNC_ISCRITICAL (sym->type))
+            genEndCritical (NULL);
+          emit2 ("jp", "(y)");
+          cost (2, 1);
+          return;
+        }
+      else if (3 + poststackadjust <= 255 && options.model != MODEL_LARGE && !IFFUNC_ISCOSMIC (sym->type))
+        {
+          push (ASMOP_X, 0, 2);
+          emit2 ("ldw", "x, (3, sp)");
+          emit2 ("ldw", "(%d, sp), x", 3 + poststackadjust);
+          pop (ASMOP_X, 0, 2);
+          adjustStack (poststackadjust, a_free, x_free, y_free);
+        }
+      else if (4 + poststackadjust <= 255 && (options.model == MODEL_LARGE || IFFUNC_ISCOSMIC (sym->type) ))
+        {
+          bool pushed_a = false;
+          if (!a_free)
+            {
+              push (ASMOP_A, 0, 1);
+              pushed_a = true;
+            }
+          emit2 ("ld", "a, (%d, sp)", 3 + pushed_a);
+          emit2 ("ld", "(%d, sp), a", 3 + pushed_a + poststackadjust);
+          emit2 ("ld", "a, (%d, sp)", 2 + pushed_a);
+          emit2 ("ld", "(%d, sp), a", 2 + pushed_a + poststackadjust);
+          emit2 ("ld", "a, (%d, sp)", 1 + pushed_a);
+          emit2 ("ld", "(%d, sp), a", 1 + pushed_a + poststackadjust);
+          if (pushed_a)
+            pop (ASMOP_A, 0, 1);
+          adjustStack (poststackadjust, a_free, x_free, y_free);
+        }
+      else
+        {
+          wassertl (regalloc_dry_run, "Unimplemented return from __z88dk_fastcall function with no free 16-bit reg and more than 252 B of stack parameters.");
+        }
+    }
+
   if (IFFUNC_ISCRITICAL (sym->type))
       genEndCritical (NULL);
 
@@ -3668,7 +4301,7 @@
       if (options.debug && currFunc && !regalloc_dry_run)
         debugFile->writeEndFunction (currFunc, ic, 1);
 
-      if (options.model == MODEL_LARGE)
+      if (options.model == MODEL_LARGE || IFFUNC_ISCOSMIC (currFunc->type))
         {
           emit2 ("retf", "");
           cost (1, 5);
@@ -3688,7 +4321,7 @@
 genReturn (const iCode *ic)
 {
   operand *left = IC_LEFT (ic);
-  int size, i;
+  int size;
   bool stacked = FALSE;
 
   D (emit2 ("; genReturn", ""));
@@ -3707,24 +4340,17 @@
     {
     case 0:
       break;
-    case 1:
-      cheapMove (ASMOP_A, 0, left->aop, 0, FALSE);
-      break;
-    case 2:
-      genMove (ASMOP_X, left->aop, TRUE, TRUE, TRUE);
-      break;
     case 3:
-      wassertl (regalloc_dry_run || !stm8_extend_stack, "Unimplemented 24-bit return in function with extended stack access.");
-      genMove (ASMOP_XYL, left->aop, TRUE, TRUE, TRUE);
-      break;
     case 4:
-      wassertl (regalloc_dry_run || !stm8_extend_stack, "Unimplemented long return in function with extended stack access.");
-      genMove (ASMOP_XY, left->aop, TRUE, TRUE, TRUE);
+      wassertl (regalloc_dry_run || !stm8_extend_stack, "Unimplemented 24-Bit/32-Bit return in function with extended stack access.");
+    case 1:
+    case 2:
+      genMove (aopRet (currFunc->type), left->aop, true, true, true);
       break;
     default:
       wassertl (size > 4, "Return not implemented for return value of this size.");
 
-      for(i = 0; i < size; i++)
+      for(int i = 0; i < size; i++)
         if (aopInReg (left->aop, i, XL_IDX) || aopInReg (left->aop, i, XH_IDX))
           {
             push (ASMOP_X, 0, 2);
@@ -3750,7 +4376,7 @@
         }
 
       // Clear a first.
-      for(i = 0; i < size; i++)
+      for(int i = 0; i < size; i++)
         if (aopInReg (left->aop, i, A_IDX))
           {
             emit2 ("ld", "(#%d, x), a", size - 1 - i);
@@ -3758,7 +4384,7 @@
             break;
           }
 
-      for(i = 0; i < size;)
+      for(int i = 0; i < size;)
         {
           if (aopInReg (left->aop, i, Y_IDX) || size > 2 && left->aop->regs[YL_IDX] < i && left->aop->regs[YH_IDX] < i && (aopOnStackNotExt (left->aop, i, 2) || left->aop->type == AOP_LIT))
             {
@@ -3797,7 +4423,7 @@
                 }
               i++;
             }
-          else
+          else // a, already stored early.
             i++;
         }
 
@@ -3987,7 +4613,7 @@
           i += 2;
         }
       // Special case for rematerializing sums
-      else if (!started && i == size - 2 &&
+      else if (!started && !i &&
         (leftop->type == AOP_STL && (rightop->type == AOP_LIT || rightop->type == AOP_DIR || aopOnStackNotExt (rightop, i, 2)) || rightop->type == AOP_STL && (leftop->type == AOP_LIT || leftop->type == AOP_DIR || aopOnStackNotExt (leftop, i, 2))) &&
         (aopInReg (result->aop, i, X_IDX) || aopInReg (result->aop, i, Y_IDX) || x_free || y_free || result->aop->regs[XL_IDX] < 0 && result->aop->regs[XH_IDX] < 0))
         {
@@ -3999,8 +4625,18 @@
           if (!y && !x_free)
             push (ASMOP_X, 0, 2);
           emit2 ("ldw", y ? "y, sp" : "x, sp");
-          emit2 ("addw", y ? "y, #%ld" : "x, #%ld", (long)((leftop->type == AOP_STL ? left : right)->aop->aopu.stk_off) + G.stack.pushed + offset);
-          cost (4 + 2 * y, 3);
+          cost (1 + y, 1);
+          switch ((long)((leftop->type == AOP_STL ? left : right)->aop->aopu.stk_off) + G.stack.pushed + offset)
+            {
+            case 2:
+              emit3w (A_INCW, y ? ASMOP_Y : ASMOP_X, 0);
+            case 1:
+              emit3w (A_INCW, y ? ASMOP_Y : ASMOP_X, 0);
+              break;
+            default:
+              emit2 ("addw", y ? "y, #%ld" : "x, #%ld", (long)((leftop->type == AOP_STL ? left : right)->aop->aopu.stk_off) + G.stack.pushed + offset);
+              cost (3 + y, 2);
+            }
           if (!lit)
             {
               emit2 ("addw", y ? "y, %s" : "x, %s", aopGet2 (leftop->type == AOP_STL ? rightop : leftop, i));
@@ -4190,30 +4826,33 @@
           i += 2;
         }
       // Fallback for rematerialization
-      else if (!started && (leftop->type == AOP_STL || rightop->type == AOP_STL) && x_free && leftop->regs[XL_IDX] < 0 && leftop->regs[XH_IDX] < 0)
+      else if (!started && (leftop->type == AOP_STL || rightop->type == AOP_STL) &&
+        (x_free || result->aop->regs[XL_IDX] < 0 && result->aop->regs[XH_IDX] < 0) &&
+        leftop->regs[XL_IDX] < 0 && leftop->regs[XH_IDX] < 0)
         {
+          if (!x_free)
+            push (ASMOP_X, 0, 2);
           genMove_o (ASMOP_X, 0, rightop, i, 2, a_free, true, y_free);
           push (ASMOP_X, 0, 2);
           genMove_o (ASMOP_X, 0, leftop, i, 2, a_free, true, y_free);
           emit2 ("addw", "x, (1, sp)");
           cost (3, 2);
-          genMove_o (result->aop, 0, ASMOP_X, 0, 2, a_free, true, y_free);
-          adjustStack (2, false, false, false);
+          genMove_o (result->aop, i, ASMOP_X, 0, 2, a_free, true, y_free);
+          adjustStack (2, a_free && result->aop->regs[A_IDX] < 0, result->aop->regs[XL_IDX] < 0 && result->aop->regs[XH_IDX] < 0, false);
+          if (!x_free)
+            pop (ASMOP_X, 0, 2);
           started = true;
           i += 2;
         }
       else if (leftop->type == AOP_STL || rightop->type == AOP_STL)
         {
-          cost (1000, 1000);
-          wassert (regalloc_dry_run);
+          UNIMPLEMENTED;
           break;
         }
       else if (aopInReg (rightop, i, A_IDX)) //todo: Implement handling of right operands that can't be directly added to a.
         {
-          if (!regalloc_dry_run)
-            wassertl (0, "Unimplemented addition operand.");
-          cost (180, 180);
-          i++;
+          UNIMPLEMENTED;
+          break;
         }
       else
         {
@@ -4318,7 +4957,7 @@
     unsigned long long add, sub;
     int topbit, nonzero;
 
-    wassert(!csdOfVal (&topbit, &nonzero, &add, &sub, right->aop->aopu.aop_lit));
+    wassert(!csdOfVal (&topbit, &nonzero, &add, &sub, right->aop->aopu.aop_lit, 0xffff));
 
     // If the leading digits of the cse are 1 0 -1 we can use 0 1 1 instead to reduce the number of shifts.
     if (topbit >= 2 && (add & (1ull << topbit)) && (sub & (1ull << (topbit - 2))))
@@ -4440,6 +5079,92 @@
 }
 
 /*-----------------------------------------------------------------*/
+/* genDivSign - generates code for signed division by power of 2   */
+/* any operands and results of up to 2 bytes                       */
+/*-----------------------------------------------------------------*/
+static void
+genDivSign (const iCode *ic)
+{
+  operand *result = IC_RESULT (ic);
+  operand *left = IC_LEFT (ic);
+  operand *right = IC_RIGHT (ic);
+  
+  wassert (right->aop->type == AOP_LIT && !SPEC_USIGN (operandType (left)) && isLiteralBit (ulFromVal (right->aop->aopu.aop_lit)) >= 0);
+  
+  symbol *tlbl = regalloc_dry_run ? 0 : newiTempLabel (0);
+
+  if (result->aop->size == 1)
+    {
+      if (!regDead (A_IDX, ic))
+        push (ASMOP_A, 0, 1);
+        
+      cheapMove (ASMOP_A, 0, left->aop, 0, false);
+      
+      emit3w (A_TNZ, ASMOP_X, 0);
+      if (!regalloc_dry_run)
+        emit2 ("jrpl", "!tlabel", labelKey2num (tlbl->key));
+      if (ulFromVal (right->aop->aopu.aop_lit) == 2)
+        emit3w (A_INC, ASMOP_A, 0);
+      else
+        {
+          emit2 ("add", "a, #0x%02x", ulFromVal (right->aop->aopu.aop_lit) - 1);
+          cost (3, 2);
+        }
+      emitLabel (tlbl);
+      for (unsigned int i = 0; i < isLiteralBit (ulFromVal (right->aop->aopu.aop_lit)); i++)
+        emit3w (A_SRA, ASMOP_A, 0);
+        
+      cheapMove (result->aop, 0, ASMOP_A, 0, false);
+        
+      if (!regDead (A_IDX, ic))
+        pop (ASMOP_A, 0, 1);
+    }
+  else
+    {
+      if (!regDead (X_IDX, ic))
+        push (ASMOP_X, 0, 2);
+    
+      genMove (ASMOP_X, left->aop, regDead (A_IDX, ic), true, regDead (Y_IDX, ic));
+
+      emit3w (A_TNZW, ASMOP_X, 0);
+      if (!regalloc_dry_run)
+        emit2 ("jrpl", "!tlabel", labelKey2num (tlbl->key));
+      if (ulFromVal (right->aop->aopu.aop_lit) == 2)
+        emit3w (A_INCW, ASMOP_X, 0);
+      else
+        {
+          emit2 ("addw", "x, #0x%04x", ulFromVal (right->aop->aopu.aop_lit) - 1);
+          cost (3, 2);
+        }
+      emitLabel (tlbl);
+      for (unsigned int i = 0; i < isLiteralBit (ulFromVal (right->aop->aopu.aop_lit)); i++)
+        emit3w (A_SRAW, ASMOP_X, 0);
+          
+      genMove (result->aop, ASMOP_X, regDead (A_IDX, ic), true, regDead (Y_IDX, ic));
+      
+      if (!regDead (X_IDX, ic))
+        {
+          if (result->aop->regs[XH_IDX] >= 0)
+            {
+              adjustStack (1, FALSE, FALSE, FALSE);
+              swap_to_a (XL_IDX);
+              pop (ASMOP_A, 0, 1);
+              swap_from_a(XL_IDX);
+            }
+          else if (result->aop->regs[XL_IDX] >= 0)
+            {
+              swap_to_a (XH_IDX);
+              pop (ASMOP_A, 0, 1);
+              swap_from_a(XH_IDX);
+              adjustStack (1, FALSE, FALSE, FALSE);
+            }
+          else
+            pop (ASMOP_X, 0, 2);
+        }
+    }
+}
+
+/*-----------------------------------------------------------------*/
 /* genDivMod2 - generates code for unsigned division               */
 /* any operands and results of up to 2 bytes                       */
 /*-----------------------------------------------------------------*/
@@ -4528,8 +5253,7 @@
 
   if (ic->op == '%' && stm8_extend_stack)
     {
-      emit2 ("exgw", "x, y");
-      cost (1, 1);
+      emit3w (A_EXGW, ASMOP_X, ASMOP_Y);
     }
 
   if (!regDead (Y_IDX, ic))
@@ -4601,8 +5325,7 @@
     {
       cheapMove (ASMOP_X, 1, ASMOP_ZERO, 0, false);
       cheapMove (ASMOP_A, 0, left->aop, 0, false);
-      emit2 ("exg", "a, xl");
-      cost (1, 1);
+      emit3 (A_EXG, ASMOP_A, ASMOP_X);
     }
   else if (aopInReg (right->aop, 0, use_y ? YL_IDX : XL_IDX) || aopInReg (right->aop, 0, use_y ? YH_IDX : XH_IDX))
     {
@@ -4659,7 +5382,9 @@
   aopOp (IC_RIGHT (ic), ic);
   aopOp (IC_RESULT (ic), ic);
 
-  if (result->aop->size <= (ic->op == '/' ? 2 : 1) && left->aop->size <= 2 && right->aop->size <= 1)
+  if (ic->op == '/' && right->aop->type == AOP_LIT && !SPEC_USIGN (operandType (left)))
+    genDivSign(ic);
+  else if (result->aop->size <= (ic->op == '/' ? 2 : 1) && left->aop->size <= 2 && right->aop->size <= 1)
     genDivMod1(ic);
   else
     genDivMod2(ic);
@@ -4783,19 +5508,19 @@
   return "brn";
 }
 
-/*------------------------------------------------------------------*/
-/* genCmp :- greater or less than (and maybe with equal) comparison */
-/* Handles cases where the decision can be made based on top bytes. */
-/*------------------------------------------------------------------*/
+/*---------------------------------------------------------------------*/
+/* genCmpTnz :- greater or less than (and maybe with equal) comparison */
+/* Handles cases where the decision can be made using tnz(w).          */
+/*---------------------------------------------------------------------*/
 static int
-genCmpTop (operand *left, operand *right, operand *result, const iCode *ic)
+genCmpTnz (operand *left, operand *right, operand *result, const iCode *ic)
 {
   sym_link *letype, *retype;
   int sign, opcode;
   int size;
   int ret = 0;
 
-  D (emit2 ("; genCmpTop", ""));
+  D (emit2 ("; genCmpTnz", ""));
 
   if (left->aop->type != AOP_LIT && right->aop->type != AOP_LIT)
     return 0;
@@ -4955,7 +5680,7 @@
     exchange = TRUE;
 
   /* Right operand is a special literal */
-  if ((special = genCmpTop(left, right, result, ic)) > 0)
+  if ((special = genCmpTnz(left, right, result, ic)) > 0)
     goto _genCmp_1;
 
   /* Cannot do multibyte signed comparison, except for 2-byte using cpw */
@@ -4979,22 +5704,23 @@
     (right->aop->type == AOP_LIT || right->aop->type == AOP_DIR || right->aop->type == AOP_STK) &&
     aopInReg (left->aop, 0, A_IDX))
     emit3 (A_CP, ASMOP_A, right->aop);
-  else if (size == 2 && (right->aop->type == AOP_LIT || right->aop->type == AOP_DIR || right->aop->type == AOP_STK))
+  else if (size == 2 && (right->aop->type == AOP_LIT || right->aop->type == AOP_DIR || right->aop->type == AOP_STK) &&
+    !(aopIsLitVal (right->aop, 0, 1, 0) && opcode != '<' && opcode != LE_OP && (aopInReg (left->aop, 1, A_IDX) || regDead (A_IDX, ic) && (aopOnStack(left->aop, 1, 1) || left->aop->type == AOP_DIR)))) // Do not use cpw here if cp in generic codegen is cheaper.
     {
       if (aopInReg (left->aop, 0, Y_IDX) && right->aop->type == AOP_STK)
         {
           if (regDead (X_IDX, ic) && regDead (Y_IDX, ic))
             {
-              emit2 ("ldw", "x, y");
+              emit3w (A_LDW, ASMOP_X, ASMOP_Y);
               emit2 ("cpw", "x, %s", aopGet2 (right->aop, 0));
-              cost (3, 3);
+              cost (2, 2);
             }
           else
             {
-              emit2 ("exgw", "x, y");
+              emit3w (A_EXGW, ASMOP_X, ASMOP_Y);
               emit2 ("cpw", "x, %s", aopGet2 (right->aop, 0));
-              emit2 ("exgw", "x, y");
-              cost (4, 4);
+              cost (2, 2);
+              emit3w (A_EXGW, ASMOP_X, ASMOP_Y);
             }
         }
       else
@@ -5031,11 +5757,14 @@
           const asmop *right_stacked = NULL;
           int right_offset;
 
-          if (!started && aopIsLitVal (right->aop, i, 2, 0) && (i + 1 < size)) // Skip over trailing 0x0000.
+          if (!started && opcode != '<' && opcode != LE_OP && aopIsLitVal (right->aop, i, 2, 0) && (i + 2 < size)) // Skip over trailing 0x0000.
             {
               i++;
               continue;
             }
+          else if (!started && opcode != '<' && opcode != LE_OP && aopIsLitVal (right->aop, i, 2, 0) && (i + 2 < size) && // Skip over trailing 0x00.
+            (aopInReg (left->aop, 1, A_IDX) || regDead (A_IDX, ic) && (aopOnStack(left->aop, 1, 1) || left->aop->type == AOP_DIR)))
+            continue;
 
           if (!started && (aopInReg (left->aop, i, X_IDX) || aopInReg (left->aop, i, Y_IDX) && !aopOnStack(right->aop, i, 2)) &&
             (right->aop->type == AOP_LIT || right->aop->type == AOP_DIR || aopOnStack(right->aop, i, 2)))
@@ -5220,16 +5949,16 @@
             {
               if (x_dead)
                 {
-                  emit2 ("ldw", "x, y");
+                  emit3w (A_LDW, ASMOP_X, ASMOP_Y);
                   emit2 ("cpw", "x, %s", aopGet2 (right->aop, i));
-                  cost (3, 3);
+                  cost (2, 2);
                 }
               else
                 {
-                  emit2 ("exgw", "x, y");
+                  emit3w (A_EXGW, ASMOP_X, ASMOP_Y);
                   emit2 ("cpw", "x, %s", aopGet2 (right->aop, i));
-                  emit2 ("exgw", "x, y");
-                  cost (4, 4);
+                  cost (2, 2);
+                  emit3w (A_EXGW, ASMOP_X, ASMOP_Y);
                 }
             }
           else
@@ -5280,6 +6009,16 @@
 
           i++;
         }
+      else if (aopInReg (left->aop, i, X_IDX) && right->aop->type == AOP_STL || left->aop->type == AOP_STL && aopInReg (right->aop, i, X_IDX))
+        {
+          push (ASMOP_X, 0, 2);
+          genMove_o (ASMOP_X, 0, right->aop->type == AOP_STL ? right->aop : left->aop, i, 2, regDead (A_IDX, ic) || pushed_a, true, regDead (Y_IDX, ic));
+          emit2 ("cpw", "x, (1, sp)");
+          cost (2, 2);
+          pop (ASMOP_X, 0, 2);
+          
+          i += 2;
+        }
       else
         {
           if (!regalloc_dry_run)
@@ -5369,143 +6108,14 @@
 genXor (const iCode *ic)
 {
   operand *left, *right, *result;
-  int size, i, j, omitbyte = -1;
-  bool result_in_a = false;
-  bool pushed_a = false;
 
   D (emit2 ("; genXor", ""));
 
   aopOp ((left = IC_LEFT (ic)), ic);
   aopOp ((right = IC_RIGHT (ic)), ic);
   aopOp ((result = IC_RESULT (ic)), ic);
-
-  size = getSize (operandType (result));
-
-  /* Prefer literal operand on right */
-  if (left->aop->type == AOP_LIT ||
-    right->aop->type != AOP_LIT && left->aop->type == AOP_DIR ||
-    (aopInReg (right->aop, 0, A_IDX) || aopInReg (right->aop, 0, X_IDX) || aopInReg (right->aop, 0, Y_IDX)) && left->aop->type == AOP_STK)
-    {
-      operand *temp = left;
-      left = right;
-      right = temp;
-    }
-
-  // todo: Use bit complement instructions where it is faster.
-  if (!regDead (A_IDX, ic))
-    {
-      push (ASMOP_A, 0, 1);
-      pushed_a = true;
-    }
-
-  // Byte in a needs to be handled first.
-  for (i = 0; i < size; i++)
-    if (aopInReg (left->aop, i, A_IDX) || aopInReg (right->aop, i, A_IDX))
-      {
-        const asmop *other_stacked = 0;
-        int other_offset;
-        asmop *other = (aopInReg (left->aop, i, A_IDX) ? right : left)->aop;
-
-        other_stacked = stack_aop (other, i, &other_offset);
-
-        if (aopIsLitVal (right->aop, i, 1, 0))
-          ;
-        else if (aopIsLitVal (right->aop, i, 1, 0xff))
-          emit3 (A_CPL, ASMOP_A, 0);
-        else if (!other_stacked)
-          emit3_o (A_XOR, ASMOP_A, 0, other, i);
-        else
-          {
-            emit2 ("xor", "a, (%d, sp)", other_offset);
-            cost (2, 1);
-          }
-        omitbyte = i;
-
-        if (other_stacked)
-          pop (other_stacked, 0, 2);
-
-        if (aopInReg (result->aop, i, A_IDX) && size > 1)
-          result_in_a = true;
-        else
-          {
-            // Avoid overwriting operand.
-            if (aopRS (result->aop) && !aopOnStack (result->aop, i, 1))
-              for (j = 0; j < size; j++)
-                {
-                  if (i == j)
-                    continue;
-                  if (j < left->aop->size && aopRS (left->aop) && !aopOnStack (left->aop, j, 1) &&
-                    left->aop->aopu.bytes[j].byteu.reg->rIdx == result->aop->aopu.bytes[i].byteu.reg->rIdx ||
-                    j < right->aop->size && aopRS (right->aop) && !aopOnStack (right->aop, j, 1) &&
-                    right->aop->aopu.bytes[j].byteu.reg->rIdx == result->aop->aopu.bytes[i].byteu.reg->rIdx)
-                    {
-                      if (!regalloc_dry_run)
-                        wassertl (0, "Unimplemented xor operand.");
-                      cost (180, 180);
-                    }
-                }
-
-            cheapMove (result->aop, i, ASMOP_A, 0, false);
-          }
-        break;
-      }
-
-  for (i = 0; i < size; i++)
-    {
-      const asmop *right_stacked = 0;
-      int right_offset;
-
-      if (omitbyte == i)
-        continue;
-
-      if (aopIsLitVal (right->aop, i, 1, 0))
-        {
-          cheapMove (result->aop, i, left->aop, i, result_in_a);
-          if (aopInReg (result->aop, i, A_IDX))
-            result_in_a = true;
-          continue;
-        }
-
-      if (left->aop->type == AOP_DIR && aopSame (left->aop, i, result->aop, i, 1) &&
-        right->aop->type == AOP_LIT && isLiteralBit (byteOfVal (right->aop->aopu.aop_lit, i)) >= 0)
-        {
-          emit2 ("bcpl", "%s, #%d", aopGet (left->aop, i), isLiteralBit (byteOfVal (right->aop->aopu.aop_lit, i)));
-          cost (4, 1);
-          continue;
-        }
-
-      right_stacked = stack_aop (right->aop, i, &right_offset);
-
-      if (result_in_a)
-        {
-          push (ASMOP_A, 0, 1);
-          pushed_a = true;
-          result_in_a = false;
-        }
-
-      cheapMove (ASMOP_A, 0, left->aop, i, false);
-
-      if (aopIsLitVal (right->aop, i, 1, 0xff))
-        emit3 (A_CPL, ASMOP_A, 0);
-      else if (!right_stacked && !(i && aopInReg (right->aop, i, A_IDX)))
-        emit3_o (A_XOR, ASMOP_A, 0, right->aop, i);
-      else
-        {
-          emit2 ("xor", "a, (%d, sp)", right_offset);
-          cost (2, 1);
-        }
-
-      if (right_stacked)
-        pop (right_stacked, 0, 2);
-
-      if (!aopInReg (result->aop, i, A_IDX))
-        cheapMove (result->aop, i, ASMOP_A, 0, false);
-      else
-        result_in_a = true;
-    }
-
-  if (pushed_a)
-    pop (ASMOP_A, 0, 1);
+  
+  genEor (ic, result->aop, left->aop, right->aop);
 
   freeAsmop (left);
   freeAsmop (right);
@@ -5991,86 +6601,361 @@
           continue;
         }
 
-      // Cases that want a free a.
-      if (!pushed_a && !(regDead (A_IDX, ic) && !result_in_a))
-        {
-          push (ASMOP_A, 0, 1);
-          pushed_a = TRUE;
-        }
+      // Cases that want a free a.
+      if (!pushed_a && !(regDead (A_IDX, ic) && !result_in_a))
+        {
+          push (ASMOP_A, 0, 1);
+          pushed_a = TRUE;
+        }
+
+      if (aopIsLitVal (right->aop, i, 1, 0x00))
+        {
+          bool new_in_a = FALSE;
+          for(j = i; j < size && j != omitbyte && aopIsLitVal (right->aop, j, 1, 0x00); j++)
+            if (aopInReg (result->aop, j, A_IDX))
+              new_in_a = TRUE;
+          genMove_o (result->aop, i, ASMOP_ZERO, 0, j - i, TRUE, regFree (X_IDX, ic), regFree (Y_IDX, ic));
+          result_in_a |= new_in_a;
+          i = j;
+        }
+      else if (aopIsLitVal (right->aop, i, 1, 0xff)) 
+        {
+          bool new_in_a = FALSE;
+          for(j = i; j < size && j != omitbyte && aopIsLitVal (right->aop, j, 1, 0xff); j++)
+            if (aopInReg (result->aop, j, A_IDX))
+              new_in_a = TRUE;
+          genMove_o (result->aop, i, left->aop, i, j - i, TRUE, regFree (X_IDX, ic), regFree (Y_IDX, ic));
+          result_in_a |= new_in_a;
+          i = j;
+        }
+      else if ((aopInReg (result->aop, i, X_IDX) && !aopInReg (left->aop, i, XL_IDX) && !aopInReg (left->aop, i, XH_IDX) || aopInReg (result->aop, i, Y_IDX) && !aopInReg (left->aop, i, YL_IDX) && !aopInReg (left->aop, i, YH_IDX)) &&
+        right->aop->type == AOP_LIT && aopIsLitVal (right->aop, i + 1, 1, 0x00)) // Use clrw to efficiently clear upper byte before writing lower byte.
+        {
+          emit3w_o (A_CLRW, result->aop, i, 0, 0);
+          cheapMove (ASMOP_A, 0, left->aop, i, false);
+          emit3_o (A_AND, ASMOP_A, 0, right->aop, i);
+          cheapMove (result->aop, i, ASMOP_A, 0, false);
+          i += 2;
+        }
+      else
+        {
+          const asmop *right_stacked = NULL;
+          int right_offset;
+
+          wassert (pushed_a || regDead (A_IDX, ic) && !result_in_a);
+
+          right_stacked = stack_aop (right->aop, i, &right_offset);
+
+          cheapMove (ASMOP_A, 0, left->aop, i, FALSE);
+
+          if (!right_stacked && !(i && aopInReg (right->aop, i, A_IDX)))
+            emit3_o (A_AND, ASMOP_A, 0, right->aop, i);
+          else
+            {
+              emit2 ("and", "a, (%d, sp)", right_offset);
+              cost (2, 1);
+            }
+
+          if (right_stacked)
+            pop (right_stacked, 0, 2);
+
+          cheapMove (result->aop, i, ASMOP_A, 0, FALSE);
+
+          if (aopInReg (result->aop, i, A_IDX))
+            result_in_a = TRUE;
+
+          i++;
+        }
+    }
+
+  if (pushed_a)
+    pop (ASMOP_A, 0, 1);
+
+release:
+  freeAsmop (left);
+  freeAsmop (right);
+  freeAsmop (result);
+}
+
+/*------------------------------------------------------------------*/
+/* genRoate - rotate                                                */
+/*------------------------------------------------------------------*/
+static void
+genRotate (const iCode *ic)
+{
+  operand *left, *result;
+
+  D (emit2 ("; genRotate", ""));
+
+  aopOp (left = IC_LEFT (ic), ic);
+  aopOp (result = IC_RESULT (ic), ic);
+  
+  const bool rlc = (ic->op == RLC);
+  
+  wassert (left->aop->size == result->aop->size);
+  
+  switch (left->aop->size)
+    {
+    case 1:
+      if (aopSame (result->aop, 0, left->aop, 0, 1) && left->aop->type == AOP_DIR) // Use bccm
+        {
+          emit3 (rlc ? A_SLL : A_SRL, left->aop, 0);
+          emit2 ("bccm", rlc ? "%s, #0" : "%s, #7", aopGet (left->aop, 0));
+          cost (4, 1);
+        }
+      else if (rlc && aopSame (result->aop, 0, left->aop, 0, 1) && aopOnStack (left->aop, 0, 1))
+        {
+          emit3 (A_SLL, left->aop, 0);
+          symbol *tlbl = (regalloc_dry_run ? 0 : newiTempLabel (0));
+          if (!regalloc_dry_run)
+              emit2 ("jrnc", "!tlabel", labelKey2num (tlbl->key));
+          emit2 ("inc", aopGet (left->aop, 0));
+          cost (2, 2);
+          emitLabel (tlbl);
+        }
+      else
+        {
+          if (!regDead (A_IDX, ic))
+            push (ASMOP_A, 0, 1);
+          cheapMove (ASMOP_A, 0, left->aop, 0, false);
+          if (rlc) // 3 bytes, 2 cycles.
+            {
+              emit3 (A_SLL, ASMOP_A, 0);
+              emit3 (A_ADC, ASMOP_A, ASMOP_ZERO);
+            }
+          else if (aopOnStack (left->aop, 0, 1) || (!aopInReg (left->aop, 0, A_IDX) && left->aop->type == AOP_REG)) // 3 or 4 bytes, 3 cycles.
+            {
+              emit3 (A_SRL, ASMOP_A, 0); // Get lowest bit into carry
+              cheapMove (ASMOP_A, 0, left->aop, 0, false);
+              emit3 (A_RRC, ASMOP_A, 0); // Rotate
+            }
+          else if (optimize.codeSpeed) // 5 bytes, 3 cycles
+            {
+              emit3 (A_SRL, ASMOP_A, 0);
+              symbol *tlbl = (regalloc_dry_run ? 0 : newiTempLabel (0));
+              if (!regalloc_dry_run)
+                emit2 ("jrnc", "!tlabel", labelKey2num (tlbl->key));
+              emit2 ("or", "#0x80");
+              cost (4, 2);
+              emitLabel (tlbl);
+            }
+          else // 4 bytes, 4 cycles.
+            {
+              push (ASMOP_A, 0, 1);
+              emit3 (A_SRL, ASMOP_A, 0); // Get lowest bit into carry
+              pop (ASMOP_A, 0, 1);
+              emit3 (A_RRC, ASMOP_A, 0); // Rotate
+            }
+          cheapMove (result->aop, 0, ASMOP_A, 0, false);
+          if (!regDead (A_IDX, ic))
+            pop (ASMOP_A, 0, 1);
+        }
+      break;
+    case 2:
+      if (rlc && aopSame (result->aop, 0, left->aop, 0, 2) && left->aop->type == AOP_DIR)  // Use bccm
+        {
+          emit3_o (A_SLL, left->aop, 0, 0, 0);
+          emit3_o (A_RLC, left->aop, 1, 0, 0);
+          emit2 ("bccm", "%s, #0", aopGet (left->aop, 0));
+          cost (4, 1);
+        }
+      else if (!rlc && aopSame (result->aop, 0, left->aop, 0, 2) && left->aop->type == AOP_DIR)  // Use bccm
+        {
+          emit3_o (A_SLL, left->aop, 1, 0, 0);
+          emit3_o (A_RLC, left->aop, 0, 0, 0);
+          emit2 ("bccm", "%s, #7", aopGet (left->aop, 1));
+          cost (4, 1);
+        }
+      else
+        {
+          bool use_y = (aopSame (result->aop, 0, left->aop, 0, 2) && aopInReg (left->aop, Y_IDX, 0) ||
+            aopInReg (result->aop, Y_IDX, 0) && !regDead (X_IDX, ic) ||
+            aopInReg (result->aop, Y_IDX, 0) && aopInReg (left->aop, X_IDX, 0));
+          if (!use_y && !regDead (X_IDX, ic))
+            push (ASMOP_X, 0, 2);
+          asmop *rotaop = use_y ? ASMOP_Y : ASMOP_X;
+          genMove (rotaop, left->aop, regDead (A_IDX, ic), !use_y || regDead (X_IDX, ic), use_y || regDead (Y_IDX, ic));
+          if (regDead (A_IDX, ic))
+            {
+              if (!(aopInReg (left->aop, rlc, A_IDX) && aopInReg (left->aop, !rlc, rlc ? (use_y ? YL_IDX : XL_IDX) : (use_y ? YH_IDX : XH_IDX))))
+                cheapMove (ASMOP_A, 0, rotaop, rlc, false);
+              emit3 (rlc ? A_SLL : A_SRL, ASMOP_A, 0);
+              emit3w (rlc ? A_RLCW : A_RRCW, rotaop, 0);
+            }
+          else if (regDead (use_y ? X_IDX : Y_IDX, ic))
+            {
+              if (!aopInReg (left->aop, 0, use_y ? X_IDX : Y_IDX))
+                {
+                  emit2 ("ldw", use_y ? "x, y" : "y, x");
+                  cost (1 + !use_y, 1);
+                }
+              emit3w (rlc ? A_SLLW : A_SRLW, use_y ? ASMOP_X : ASMOP_Y, 0);
+              emit3w (rlc ? A_RLCW : A_RRCW, rotaop, 0);
+            }
+          else
+            {
+              emit3w (rlc ? A_SLLW : A_SRLW, rotaop, 0);
+              symbol *tlbl = (regalloc_dry_run ? 0 : newiTempLabel (0));
+              if (!regalloc_dry_run)
+                emit2 ("jrnc", "!tlabel", labelKey2num (tlbl->key));
+              if (rlc)
+                emit2 ("incw", aopGet2 (rotaop, 0));
+              else
+                emit2 ("addw", "%s, #0x8000", aopGet2 (rotaop, 0));
+              cost (3 + !rlc * 2 + use_y * 2, 2 + !rlc);
+              emitLabel (tlbl);
+            }
+          if ((result->aop->regs[use_y ? YL_IDX : XL_IDX] >= 0 || result->aop->regs[use_y ? YH_IDX : XH_IDX] >= 0) && !regDead (use_y ? Y_IDX : X_IDX, ic))
+            {
+              cost (300, 300);
+              wassertl (regalloc_dry_run, "Unimplemented roatate with result partially in non-dead x.");
+            }
+          genMove (result->aop, rotaop, regDead (A_IDX, ic), !use_y || regDead (X_IDX, ic), use_y || regDead (Y_IDX, ic));
+          if (!use_y && !regDead (X_IDX, ic))
+            pop (ASMOP_X, 0, 2);
+        }
+      break;
+    default:
+      wassertl (0, "Unsupported rotate size.");
+    }
+
+  freeAsmop (left);
+  freeAsmop (result);
+}
+ 
+/*------------------------------------------------------------------*/
+/* genSwap - swap nibbles or bytes                                  */
+/*------------------------------------------------------------------*/
+static void
+genSwap (const iCode *ic)
+{
+  operand *left, *result;
+
+  D (emit2 ("; genSwap", ""));
 
-      if (aopIsLitVal (right->aop, i, 1, 0x00))
+  aopOp (left = IC_LEFT (ic), ic);
+  aopOp (result = IC_RESULT (ic), ic);
+
+  asmop swapped_aop;
+
+  wassert (left->aop->size == result->aop->size);
+
+  switch (left->aop->size)
+    {
+    case 1:
+      if (aopSame (result->aop, 0, left->aop, 0, 1) &&
+        (aopOnStack (result->aop, 0, 1) || result->aop->type == AOP_DIR))
+        emit3 (A_SWAP, result->aop, 0);
+      else
         {
-          bool new_in_a = FALSE;
-          for(j = i; j < size && j != omitbyte && aopIsLitVal (right->aop, j, 1, 0x00); j++)
-            if (aopInReg (result->aop, j, A_IDX))
-              new_in_a = TRUE;
-          genMove_o (result->aop, i, ASMOP_ZERO, 0, j - i, TRUE, regFree (X_IDX, ic), regFree (Y_IDX, ic));
-          result_in_a |= new_in_a;
-          i = j;
+          if (!regDead (A_IDX, ic))
+            push (ASMOP_A, 0, 1);
+
+          cheapMove (ASMOP_A, 0, left->aop, 0, false);
+          emit3 (A_SWAP, ASMOP_A, 0);
+          cheapMove (result->aop, 0, ASMOP_A, 0, false);
+  
+          if (!regDead (A_IDX, ic))
+            pop (ASMOP_A, 0, 1);
         }
-      else if (aopIsLitVal (right->aop, i, 1, 0xff)) 
+      break;
+    case 2:
+      if (result->aop->type == AOP_REG) // Let genMove handle all the coalescing, swapw, exg, rlwa, etc).
         {
-          bool new_in_a = FALSE;
-          for(j = i; j < size && j != omitbyte && aopIsLitVal (right->aop, j, 1, 0xff); j++)
-            if (aopInReg (result->aop, j, A_IDX))
-              new_in_a = TRUE;
-          genMove_o (result->aop, i, left->aop, i, j - i, TRUE, regFree (X_IDX, ic), regFree (Y_IDX, ic));
-          result_in_a |= new_in_a;
-          i = j;
+          signed char idxarray[3];
+          idxarray[0] = result->aop->aopu.bytes[1].byteu.reg->rIdx;
+          idxarray[1] = result->aop->aopu.bytes[0].byteu.reg->rIdx;
+          idxarray[2] = -1;
+          stm8_init_reg_asmop (&swapped_aop, idxarray);
+          genMove (&swapped_aop, left->aop, regDead (A_IDX, ic), regDead (X_IDX, ic), regDead (Y_IDX, ic));
         }
-      else if ((aopInReg (result->aop, i, X_IDX) && !aopInReg (left->aop, i, XL_IDX) && !aopInReg (left->aop, i, XH_IDX) || aopInReg (result->aop, i, Y_IDX) && !aopInReg (left->aop, i, YL_IDX) && !aopInReg (left->aop, i, YH_IDX)) &&
-        right->aop->type == AOP_LIT && aopIsLitVal (right->aop, i + 1, 1, 0x00)) // Use clrw to efficiently clear upper byte before writing lower byte.
+      else if (left->aop->type == AOP_REG)
         {
-          emit3w_o (A_CLRW, result->aop, i, 0, 0);
-          cheapMove (ASMOP_A, 0, left->aop, i, false);
-          emit3_o (A_AND, ASMOP_A, 0, right->aop, i);
-          cheapMove (result->aop, i, ASMOP_A, 0, false);
-          i += 2;
+          signed char idxarray[3];
+          idxarray[0] = left->aop->aopu.bytes[1].byteu.reg->rIdx;
+          idxarray[1] = left->aop->aopu.bytes[0].byteu.reg->rIdx;
+          idxarray[2] = -1;
+          stm8_init_reg_asmop (&swapped_aop, idxarray);
+          genMove (result->aop, &swapped_aop, regDead (A_IDX, ic), regDead (X_IDX, ic), regDead (Y_IDX, ic));
         }
       else
         {
-          const asmop *right_stacked = NULL;
-          int right_offset;
-
-          wassert (pushed_a || regDead (A_IDX, ic) && !result_in_a);
-
-          right_stacked = stack_aop (right->aop, i, &right_offset);
+          if (!regDead (X_IDX, ic))
+            push (ASMOP_X, 0, 2);
 
-          cheapMove (ASMOP_A, 0, left->aop, i, FALSE);
+          genMove (ASMOP_X, left->aop, regDead (A_IDX, ic), true, regDead (Y_IDX, ic));
+          emit3w (A_SWAPW, ASMOP_X, 0);
+          genMove (result->aop, ASMOP_X, regDead (A_IDX, ic), true, regDead (Y_IDX, ic));
 
-          if (!right_stacked && !(i && aopInReg (right->aop, i, A_IDX)))
-            emit3_o (A_AND, ASMOP_A, 0, right->aop, i);
-          else
+          if (!regDead (X_IDX, ic) && (result->aop->regs[XL_IDX] >= 0 || result->aop->regs[XH_IDX] >= 0))
             {
-              emit2 ("and", "a, (%d, sp)", right_offset);
-              cost (2, 1);
+              cost (300, 300);
+              wassertl (regalloc_dry_run, "Swap result partially in non-dead x not implemented.");
             }
 
-          if (right_stacked)
-            pop (right_stacked, 0, 2);
-
-          cheapMove (result->aop, i, ASMOP_A, 0, FALSE);
+          if (!regDead (X_IDX, ic))
+            pop (ASMOP_X, 0, 2);
+        }
+      break;
+    case 4:
+      if (result->aop->type == AOP_REG) // Let genMove handle all the coalescing, swapw, exg, rlwa, etc).
+        {
+          signed char idxarray[5];
+          idxarray[0] = result->aop->aopu.bytes[2].byteu.reg->rIdx;
+          idxarray[1] = result->aop->aopu.bytes[3].byteu.reg->rIdx;
+          idxarray[2] = result->aop->aopu.bytes[0].byteu.reg->rIdx;
+          idxarray[3] = result->aop->aopu.bytes[1].byteu.reg->rIdx;
+          idxarray[4] = -1;
+          stm8_init_reg_asmop (&swapped_aop, idxarray);
+          genMove (&swapped_aop, left->aop, regDead (A_IDX, ic), regDead (X_IDX, ic), regDead (Y_IDX, ic));
+        }
+      else if (left->aop->type == AOP_REG)
+        {
+          signed char idxarray[5];
+          idxarray[0] = left->aop->aopu.bytes[2].byteu.reg->rIdx;
+          idxarray[1] = left->aop->aopu.bytes[3].byteu.reg->rIdx;
+          idxarray[2] = left->aop->aopu.bytes[0].byteu.reg->rIdx;
+          idxarray[3] = left->aop->aopu.bytes[1].byteu.reg->rIdx;
+          idxarray[4] = -1;
+          stm8_init_reg_asmop (&swapped_aop, idxarray);
+          genMove (result->aop, &swapped_aop, regDead (A_IDX, ic), regDead (X_IDX, ic), regDead (Y_IDX, ic));
+        }
+      else
+        {
+          if (!regDead (X_IDX, ic))
+            push (ASMOP_X, 0, 2);
+          if (!regDead (Y_IDX, ic))
+            push (ASMOP_Y, 0, 2);
 
-          if (aopInReg (result->aop, i, A_IDX))
-            result_in_a = TRUE;
+          genMove (ASMOP_XY, left->aop, regDead (A_IDX, ic), true, true);
+          genMove (result->aop, ASMOP_YX, regDead (A_IDX, ic), true, true);
+ 
+          if (!regDead (X_IDX, ic) && (result->aop->regs[XL_IDX] >= 0 || result->aop->regs[XH_IDX] >= 0) ||
+            !regDead (Y_IDX, ic) && (result->aop->regs[YL_IDX] >= 0 || result->aop->regs[YH_IDX] >= 0))
+            {
+              cost (300, 300);
+              wassertl (regalloc_dry_run, "Swap result partially in non-dead x/y not implemented.");
+            }
 
-          i++;
+          if (!regDead (Y_IDX, ic))
+            pop (ASMOP_Y, 0, 2);
+          if (!regDead (X_IDX, ic))
+            pop (ASMOP_X, 0, 2);
         }
+      break;
+    default:
+      wassertl (0, "Unsupported swap size.");
     }
 
-  if (pushed_a)
-    pop (ASMOP_A, 0, 1);
-
-release:
   freeAsmop (left);
-  freeAsmop (right);
   freeAsmop (result);
 }
 
 /*------------------------------------------------------------------*/
 /* init_shiftop - find a good place to shift in                     */
 /*------------------------------------------------------------------*/
-static void init_shiftop(asmop *shiftop, const asmop *result, const asmop *left, const asmop *right, const iCode *ic, bool a_needed_for_count)
+static void 
+init_shiftop(asmop *shiftop, const asmop *result, const asmop *left, const asmop *right, const iCode *ic, bool a_needed_for_count)
 {
   int i;
   const int size = result->size;
@@ -6078,11 +6963,7 @@
   bool all_in_reg = TRUE;
 
   shiftop->size = size;
-  shiftop->regs[A_IDX] = -1;
-  shiftop->regs[XL_IDX] = -1;
-  shiftop->regs[XH_IDX] = -1;
-  shiftop->regs[YL_IDX] = -1;
-  shiftop->regs[YH_IDX] = -1;
+  memset (shiftop->regs, -1, sizeof(shiftop->regs));
 
   for (i = 0; i < size;)
     {
@@ -6176,6 +7057,19 @@
   if (shCount > (size * 8))
     shCount = size * 8;
 
+  if (size == 2 && shCount < 16 && shCount >= 13 && regDead (A_IDX, ic) && regDead (X_IDX, ic))
+    {
+      cheapMove (ASMOP_A, 0, left->aop, 0, false);
+      emit3w (A_CLRW, ASMOP_X, 0);
+      for (int i = shCount; i < 16; i++)
+        {
+          emit3 (A_SRL, ASMOP_A, 0);
+          emit3w (A_RRCW, ASMOP_X, 0);
+        }
+      genMove(result->aop, ASMOP_X, regDead (A_IDX, ic), regDead (X_IDX, ic), regDead (Y_IDX, ic));
+      goto release;
+    }
+
   if (shCount >= (size * 8))
     {
       genMove(result->aop, ASMOP_ZERO, regDead (A_IDX, ic), regDead (X_IDX, ic), regDead (Y_IDX, ic));
@@ -6415,6 +7309,32 @@
 
   size = result->aop->size;
 
+  if (skip_bytes + 2 == size && right->aop->type == AOP_LIT &&
+    (iterations <= 3 || iterations == 7) &&
+    (aopInReg (shiftop, skip_bytes, X_IDX) || aopInReg (shiftop, skip_bytes, Y_IDX)))
+    {
+      bool a_free = regDead (A_IDX, ic) && shiftop->regs[A_IDX] < 0;
+      if (iterations <= 3)
+        {
+          for(int i = 0; i < iterations; i++)
+            emit3w_o (A_SLLW, shiftop, skip_bytes, 0, 0);
+          goto postshift;
+        }
+      wassert (iterations == 7);
+      if (!a_free)
+        {
+          push (ASMOP_A, 0, 1);
+          pushed_a = true;
+        }
+      bool y = aopInReg (shiftop, skip_bytes, Y_IDX);
+      emit2 ("clr", "a");
+      emit2 ("rlwa", y ? "y" : "x");
+      emit2 ("srl", "a");
+      emit2 ("rrcw", y ? "y" : "x");
+      cost (4 + y * 2, 5);
+      goto postshift;
+    }
+
   for (i = 0; i < size; i++)
     {
       if (aopRS (shiftop) && (!aopInReg (shiftop, i, A_IDX) || aopInReg (right->aop, 0, A_IDX)) && shiftop->aopu.bytes[i].in_reg &&
@@ -6632,6 +7552,58 @@
   freeAsmop (result);
 }
 
+/*-----------------------------------------------------------------*/
+/* genGetByte - generates code to get a single byte                */
+/*-----------------------------------------------------------------*/
+static void
+genGetByte (const iCode *ic)
+{
+  operand *left, *right, *result;
+  int offset;
+
+  D (emit2 ("; genGetByte", ""));
+
+  left = IC_LEFT (ic);
+  right = IC_RIGHT (ic);
+  result = IC_RESULT (ic);
+  aopOp (left, ic);
+  aopOp (right, ic);
+  aopOp (result, ic);
+
+  offset = (int) ulFromVal (right->aop->aopu.aop_lit) / 8;
+  genMove_o (result->aop, 0, left->aop, offset, 1, regDead (A_IDX, ic), regDead (X_IDX, ic), regDead (Y_IDX, ic));
+
+  freeAsmop (result);
+  freeAsmop (right);
+  freeAsmop (left);
+}
+
+/*-----------------------------------------------------------------*/
+/* genGetWord - generates code to get a 16-bit word                */
+/*-----------------------------------------------------------------*/
+static void
+genGetWord (const iCode *ic)
+{
+  operand *left, *right, *result;
+  int offset;
+
+  D (emit2 ("; genGetWord", ""));
+
+  left = IC_LEFT (ic);
+  right = IC_RIGHT (ic);
+  result = IC_RESULT (ic);
+  aopOp (left, ic);
+  aopOp (right, ic);
+  aopOp (result, ic);
+
+  offset = (int) ulFromVal (right->aop->aopu.aop_lit) / 8;
+  genMove_o (result->aop, 0, left->aop, offset, 2, regDead (A_IDX, ic), regDead (X_IDX, ic), regDead (Y_IDX, ic));
+
+  freeAsmop (result);
+  freeAsmop (right);
+  freeAsmop (left);
+}
+
 /*------------------------------------------------------------------*/
 /* genRightShiftLiteral - right shifting by known count             */
 /*------------------------------------------------------------------*/
@@ -6641,7 +7613,7 @@
   int shCount = (int) ulFromVal (right->aop->aopu.aop_lit);
   int size, i;
   bool sign;
-  bool xh_zero, yh_zero, xl_free, yl_free;
+  bool xh_zero, yh_zero, xl_free, yl_free, a_free;
 
   struct asmop shiftop_impl;
   struct asmop *shiftop;
@@ -6657,6 +7629,8 @@
 
   aopOp (left, ic);
   aopOp (result, ic);
+  
+  wassert (shCount >= 0);
 
   if (shCount > (size * 8))
     shCount = size * 8;
@@ -6699,6 +7673,7 @@
   yh_zero = shiftop->regs[YH_IDX] >= size;
   xl_free = regDead (XL_IDX, ic) && shiftop->regs[XL_IDX] < 0;
   yl_free = regDead (YL_IDX, ic) && shiftop->regs[YL_IDX] < 0;
+  a_free = regDead (A_IDX, ic) && shiftop->regs[A_IDX] < 0;
 
   // Use swap a where beneficial.
   if (!sign && size == 1 && aopRS (shiftop) && !aopOnStack (shiftop, 0, 1) &&
@@ -6719,24 +7694,24 @@
       goto release;
     }
 
-  // div can be cheaper than a sequence of shifts.
+  // div can be cheaper than a sequence of shifts. Keep the decision here consistent with handling of funcDivFlagSafe in SDCCralloc.hpp!
   if (!sign && shCount < 8 &&
-    (shCount > 3 + !regDead (A_IDX, ic) * 2 && (size == 2 && aopInReg (shiftop, 0, X_IDX) || size == 1 && aopInReg (shiftop, 0, XL_IDX) && xh_zero) ||
-    shCount * 2 > 4 + !regDead (A_IDX, ic) * 2 && (size == 2 && aopInReg (shiftop, 0, Y_IDX) || size == 1 && aopInReg (shiftop, 0, YL_IDX) && yh_zero)))
+    (shCount > 3 + !a_free * 2 && (size == 2 && aopInReg (shiftop, 0, X_IDX) || size == 1 && aopInReg (shiftop, 0, XL_IDX) && xh_zero) ||
+    shCount * 2 > 4 + !a_free * 2 && (size == 2 && aopInReg (shiftop, 0, Y_IDX) || size == 1 && aopInReg (shiftop, 0, YL_IDX) && yh_zero)))
     {
       const bool in_y = aopInReg (shiftop, 0, Y_IDX);
-      if (!regDead (A_IDX, ic))
+      if (!a_free)
         push (ASMOP_A, 0, 1);
       emit2 ("ld", "a, #0x%02x", 1 << shCount);
       cost (2, 1);
       emit2 ("div", in_y ? "y, a" : "x, a");
       cost (1 + in_y, 17); // TODO: Find out exact value, replace 17 by exact value, and accordingly choose this optimization depending on optimization goal.
-      if (!regDead (A_IDX, ic))
+      if (!a_free)
         pop (ASMOP_A, 0, 1);
       goto release;
     }
 
-  // divw can be cheaper than a sequence of shifts.
+  // divw can be cheaper than a sequence of shifts. Keep the decision here consistent with handling of funcDivFlagSafe in SDCCralloc.hpp!
   if (!sign && size == 2 && shCount > 5 && regDead (Y_IDX, ic) && aopInReg (shiftop, 0, X_IDX))
     {
       emit2 ("ldw", "y, #0x%04x", 1 << shCount);
@@ -6804,7 +7779,7 @@
     (aopInReg (shiftop, 0, X_IDX) || aopInReg (shiftop, 0, Y_IDX)) &&
     (aopInReg (shiftop, 2, X_IDX) || aopInReg (shiftop, 2, Y_IDX)))
     {
-      if (!regDead (A_IDX, ic))
+      if (!a_free)
         push (ASMOP_A, 0, 1);
       emit3 (A_CLR, ASMOP_A, 0);
       emit3w_o (A_RRWA, shiftop, 2, 0, 0);
@@ -6816,7 +7791,7 @@
           emit3w_o (A_RLCW, shiftop, 0, 0, 0);
           emit3w_o (A_RLCW, shiftop, 2, 0, 0);
         }
-      if (!regDead (A_IDX, ic))
+      if (!a_free)
         pop (ASMOP_A, 0, 1);
     }
 
@@ -7039,7 +8014,8 @@
 /*------------------------------------------------------------------*/
 /* init_stackop - initalize asmop for stack location                */
 /*------------------------------------------------------------------*/
-static void init_stackop (asmop *stackop, int size, long int stk_off)
+static void 
+init_stackop (asmop *stackop, int size, long int stk_off)
 {
   stackop->size = size;
   stackop->regs[A_IDX] = -1;
@@ -7048,6 +8024,13 @@
   stackop->regs[YL_IDX] = -1;
   stackop->regs[YH_IDX] = -1;
 
+  if (labs(stk_off) > (1 << 15))
+  {
+    if (!regalloc_dry_run)
+      werror (W_INVALID_STACK_LOCATION);
+    stk_off = 0;
+  }
+
   for (int i = 0; i < size; i++)
     {
       stackop->aopu.bytes[i].in_reg = false;
@@ -7067,7 +8050,7 @@
   operand *left = IC_LEFT (ic);
   operand *right = IC_RIGHT (ic);
   int size, i;
-  unsigned offset;
+  long offset;
   bool use_y;
   bool pushed_x = false;
   bool pushed_a = false;
@@ -7092,8 +8075,7 @@
 
   size = result->aop->size;
 
-  // todo: What if right operand is negative?
-  offset = byteOfVal (right->aop->aopu.aop_lit, 1) * 256 + byteOfVal (right->aop->aopu.aop_lit, 0);
+  offset = operandLitValue (IC_RIGHT(ic));
 
   // Long pointer indirect long addressing mode is useful only in one very specific case:
   if (!bit_field && size == 1 && !offset && left->aop->type == AOP_DIR && !regDead (X_IDX, ic) && regDead (A_IDX, ic))
@@ -7111,9 +8093,18 @@
       genMove(result->aop, &stackop_impl, regDead (A_IDX, ic), regDead (X_IDX, ic), regDead (Y_IDX, ic));
       goto release;
     }
+  // Special case for efficient handling of 8-bit I/O and rematerialized pointers when assigning to direct memory.
+  else if (!bit_field && size == 1 && (left->aop->type == AOP_LIT || left->aop->type == AOP_IMMD) && result->aop->type == AOP_DIR)
+    {
+      if (left->aop->type == AOP_LIT)
+        emit2("mov", offset ? "%s, 0x%02x%02x+%d" : "%s, 0x%02x%02x", aopGet (result->aop, 0), byteOfVal (left->aop->aopu.aop_lit, 1), byteOfVal (left->aop->aopu.aop_lit, 0), offset);
+      else
+        emit2("mov", offset ? "%s, %s+%d" : "%s, %s+%d", aopGet (result->aop, 0), left->aop->aopu.immd, left->aop->aopu.immd_off + offset);
+      cost (5, 1);
+      goto release;
+    }
   // Special case for efficient handling of 8-bit I/O and rematerialized pointers
-  else if (!bit_field && size == 1 && (left->aop->type == AOP_LIT || left->aop->type == AOP_IMMD)
-    && regDead (A_IDX, ic))
+  else if (!bit_field && size == 1 && (left->aop->type == AOP_LIT || left->aop->type == AOP_IMMD) && regDead (A_IDX, ic))
     {
       if (left->aop->type == AOP_LIT)
         emit2("ld", offset ? "a, 0x%02x%02x+%d" : "a, 0x%02x%02x",  byteOfVal (left->aop->aopu.aop_lit, 1), byteOfVal (left->aop->aopu.aop_lit, 0), offset);
@@ -7202,12 +8193,12 @@
         {
           o--;
 
-          emit2 ("ldw", "y, x");
+          emit3w (A_LDW, ASMOP_Y, ASMOP_X);
           if (!o)
             emit2 ("ldw", "y, (y)");
           else
             emit2 ("ldw", "y, (0x%x, y)", o);
-          cost (4 + (o > 0) + (o > 256), 3);
+          cost (2 + (o > 0) + (o > 256), 2);
           genMove_o (result->aop, i, ASMOP_Y, 0, 2, pushed_a, false, true);
 
           i++, blen -= 8;
@@ -7579,18 +8570,18 @@
             }
           else
             {
-              emit2 ("ld", "a, #0x%02x", ~((0xff >> (8 - blen)) << bstr) & 0xff);
-              cost (2, 1);
               if (!i)
                 {
-                  emit2 ("and", use_y ? "a, (y)" : "a, (x)");
+                  emit2 ("ld", use_y ? "a, (y)" : "a, (x)");
                   cost (1 + use_y, 1);
                 }
               else
                 {
-                  emit2 ("and", use_y ? "a, (0x%x, y)" : "a, (0x%x, x)", i);
+                  emit2 ("ld", use_y ? "a, (0x%x, y)" : "a, (0x%x, x)", i);
                   cost ((size - 1 - i < 256 ? 2 : 3) + use_y, 1);
                 }
+              emit2 ("and", "a, #0x%02x", ~((0xff >> (8 - blen)) << bstr) & 0xff);
+              cost (2, 1);
             }
           if (bval)
             {
@@ -7618,18 +8609,19 @@
           cost (2, 1);
           push (ASMOP_A, 0, 1);
           pushed_a++;
-          emit2 ("ld", "a, #0x%02x", ~((0xff >> (8 - blen)) << bstr) & 0xff);
-          cost (2, 1);
           if (!i)
             {
-              emit2 ("and", use_y ? "a, (y)" : "a, (x)", i);
+              emit2 ("ld", use_y ? "a, (y)" : "a, (x)");
               cost (1 + use_y, 1);
             }
           else
             {
-              emit2 ("and", use_y ? "a, (0x%x, y)" : "a, (0x%x, x)", i);
+              emit2 ("ld", use_y ? "a, (0x%x, y)" : "a, (0x%x, x)", i);
               cost ((size - 1 - i < 256 ? 2 : 3) + use_y, 1);
             }
+          emit2 ("and", "a, #0x%02x", ~((0xff >> (8 - blen)) << bstr) & 0xff);
+          cost (2, 1);
+          
           emit2 ("or", "a, (1, sp)");
           cost (2, 1);
         }
@@ -7727,20 +8719,16 @@
           // We can't just use swap_to_a() to improve the following four cases because it might use rrwa and rlwa which destroy the Z flag.
           else if (aopInReg (cond->aop, i, XL_IDX) && (!floattopbyte || regDead (XL_IDX, ic)))
             {
-              emit2 ("exg", "a, xl");
-              cost (1, 1);
-              emit3(floattopbyte ? A_SLL : A_TNZ, ASMOP_A, 0);
-              emit2 ("exg", "a, xl");
-              cost (1, 1);
+              emit3 (A_EXG, ASMOP_A, ASMOP_X);
+              emit3 (floattopbyte ? A_SLL : A_TNZ, ASMOP_A, 0);
+              emit3 (A_EXG, ASMOP_A, ASMOP_X);
               i++;
             }
           else if (aopInReg (cond->aop, i, YL_IDX) && (!floattopbyte || regDead (YL_IDX, ic)))
             {
-              emit2 ("exg", "a, yl");
-              cost (1, 1);
-              emit3(floattopbyte ? A_SLL : A_TNZ, ASMOP_A, 0);
-              emit2 ("exg", "a, yl");
-              cost (1, 1);
+              emit3 (A_EXG, ASMOP_A, ASMOP_Y);
+              emit3 (floattopbyte ? A_SLL : A_TNZ, ASMOP_A, 0);
+              emit3 (A_EXG, ASMOP_A, ASMOP_Y);
               i++;
             }
           else if (!floattopbyte && !aopInReg (cond->aop, i, XH_IDX) && !aopInReg (cond->aop, i, YH_IDX))
@@ -7774,9 +8762,11 @@
           cost (2, 0);
         }
     }
-  else if (cond->aop->type == AOP_IMMD)
+  else if (cond->aop->type == AOP_IMMD || cond->aop->type == AOP_STL) // An AOP_IMMD or AOP_STL points to something valid, so it is not a null pointer.
     {
-      // An AOP_IMMD points to something valid, so it is not a null pointer. Just fall through to the unconditional jump generated below.
+      if (IC_TRUE (ic))
+        emitJP (IC_TRUE (ic), 1.0f);
+      goto release;
     }
   else
     {
@@ -7800,6 +8790,7 @@
       emitLabel (tlbl);
     }
 
+release:
   freeAsmop (cond);
 }
 
@@ -8145,7 +9136,115 @@
 }
 
 /*-----------------------------------------------------------------*/
-/* genDummyRead - generate code for dummy read of volatiles        */
+/* genReceive - generate code for receiving a register parameter.  */
+/*-----------------------------------------------------------------*/
+static void
+genReceive (const iCode *ic)
+{
+  operand *result = IC_RESULT (ic);
+  aopOp (result, ic);
+
+  D (emit2 ("; genReceive", ""));
+
+  wassert (currFunc);
+  wassert (ic->argreg);
+  wassert (aopArg (currFunc->type, ic->argreg));
+
+  bool dead_regs[YH_IDX + 1];
+  
+  for (int i = 0; i <= YH_IDX; i++)
+    dead_regs[i] = regDead (i, ic);
+
+  for(iCode *nic = ic->next; nic && nic->op == RECEIVE; nic = nic->next)
+    {
+      asmop *narg = aopArg (currFunc->type, nic->argreg);
+      wassert (narg);
+      for (int i = 0; i < narg->size; i++)
+        dead_regs[narg->aopu.bytes[i].byteu.reg->rIdx] = false;
+    }
+    
+  if (result->aop->type == AOP_REG || result->aop->type == AOP_REGSTK)
+    for (int i = 0; i < result->aop->size; i++)
+      if (result->aop->aopu.bytes[i].in_reg && !dead_regs[result->aop->aopu.bytes[i].byteu.reg->rIdx])
+        {
+          cost (500, 500);
+          wassert (regalloc_dry_run);
+        }
+
+  genMove (result->aop, aopArg (currFunc->type, ic->argreg), dead_regs[A_IDX], dead_regs[XL_IDX] && dead_regs[XH_IDX], dead_regs[YL_IDX] && dead_regs[YH_IDX]);
+
+  freeAsmop (result);
+}
+
+/*-----------------------------------------------------------------*/
+/* genSend - generate code for sending a register parameter.       */
+/*-----------------------------------------------------------------*/
+static void
+genSend (const iCode *ic)
+{
+  D (emit2 ("; genSend", ""));
+
+  aopOp (IC_LEFT (ic), ic);
+
+  /* Caller saves, and this is the first iPush. */
+  /* Scan ahead until we find the function that we are pushing parameters to.
+     Count the number of addSets on the way to figure out what registers
+     are used in the send set.
+   */
+  const iCode *walk;
+  for (walk = ic->next; walk; walk = walk->next)
+    {
+      if (walk->op == CALL || walk->op == PCALL)
+        break;
+    }
+
+  if (!G.saved && !regalloc_dry_run) // Cost is counted at CALL or PCALL instead
+    saveRegsForCall (walk);
+
+  sym_link *ftype = IS_FUNCPTR (operandType (IC_LEFT (walk))) ? operandType (IC_LEFT (walk))->next : operandType (IC_LEFT (walk));
+  asmop *argreg = aopArg (ftype, ic->argreg);
+
+  wassert (argreg);
+
+  // The register argument shall not overwrite a still-needed (i.e. as further parameter or function for the call) value.
+  for (int i = 0; i < argreg->size; i++)
+    if (!regDead (argreg->aopu.bytes[i].byteu.reg->rIdx, ic))
+      for (iCode *walk2 = ic->next; walk2; walk2 = walk2->next)
+        {
+          if (walk2->op != CALL && IC_LEFT (walk2) && !IS_OP_LITERAL (IC_LEFT (walk2)))
+            {
+              cost (500, 500);
+              wassert (regalloc_dry_run);
+            }
+
+          if (walk2->op == CALL || walk2->op == PCALL)
+            break;
+        }
+
+  bool a_dead = regDead (A_IDX, ic);
+  bool x_dead = regDead (X_IDX, ic);
+  bool y_dead = regDead (Y_IDX, ic);
+  
+  for (iCode *walk2 = ic->prev; walk2 && walk2->op == SEND; walk2 = walk2->prev)
+    {
+      asmop *warg = aopArg (ftype, walk2->argreg);
+      wassert (warg);
+      a_dead &= (warg->regs[A_IDX] < 0);
+      x_dead &= (warg->regs[XL_IDX] < 0 && warg->regs[XH_IDX] < 0);
+      y_dead &= (warg->regs[YL_IDX] < 0 && warg->regs[YH_IDX] < 0);
+    }
+    
+  genMove (argreg, IC_LEFT (ic)->aop, a_dead, x_dead, y_dead);
+
+  for (int i = 0; i < argreg->size; i++)
+    if (!regalloc_dry_run)
+       ((walk->op == PCALL) ? stm8_regs_used_as_parms_in_pcalls_from_current_function : stm8_regs_used_as_parms_in_calls_from_current_function)[argreg->aopu.bytes[i].byteu.reg->rIdx] = true;
+
+  freeAsmop (IC_LEFT (ic));
+}
+
+/*-----------------------------------------------------------------*/
+/* genDummyRead - generate code for dummy read of volatiles.       */
 /*-----------------------------------------------------------------*/
 static void
 genDummyRead (const iCode *ic)
@@ -8352,13 +9451,25 @@
 
     case RRC:
     case RLC:
-      wassertl (0, "Unimplemented iCode");
+      genRotate (ic);
       break;
 
     case GETABIT:
       genGetABit (ic, ifxForOp (IC_RESULT (ic), ic));
       break;
 
+    case GETBYTE:
+      genGetByte (ic);
+      break;
+
+    case GETWORD:
+      genGetWord (ic);
+      break;
+
+    case SWAP:
+      genSwap (ic);
+      break;
+
     case LEFT_OP:
       genLeftShift (ic);
       break;
@@ -8397,8 +9508,11 @@
       break;
 
     case RECEIVE:
+      genReceive (ic);
+      break;
+      
     case SEND:
-      wassertl (0, "Unimplemented iCode");
+      genSend (ic);
       break;
 
     case DUMMY_READ_VOLATILE:
@@ -8439,7 +9553,7 @@
 }
 
 /*---------------------------------------------------------------------*/
-/* genSTM8Code - generate code for STM8 for a block of intructions     */
+/* genSTM8Code - generate code for STM8 for a block of instructions    */
 /*---------------------------------------------------------------------*/
 void
 genSTM8Code (iCode *lic)
@@ -8457,6 +9571,9 @@
   if (options.debug && !regalloc_dry_run)
     debugFile->writeFrameAddress (NULL, NULL, 0); /* have no idea where frame is now */
 
+  memset(stm8_regs_used_as_parms_in_calls_from_current_function, 0, sizeof(bool) * (YH_IDX + 1));
+  memset(stm8_regs_used_as_parms_in_pcalls_from_current_function, 0, sizeof(bool) * (YH_IDX + 1));
+
   for (ic = lic; ic; ic = ic->next)
     {
       initGenLineElement ();
@@ -8515,3 +9632,58 @@
   destroy_line_list ();
 }
 
+bool
+stm8IsReturned(const char *what)
+{
+  if (!strcmp(what, "x"))
+    return (stm8IsReturned ("xl") || stm8IsReturned ("xh"));
+  else if (!strcmp(what, "y"))
+    return (stm8IsReturned ("yl") || stm8IsReturned ("yh"));
+
+  const asmop *retaop = aopRet (currFunc->type);
+
+  if (!retaop)
+    return false;
+  for (int i = 0; i < retaop->size; i++)
+    if (!strcmp(retaop->aopu.bytes[i].byteu.reg->name, what))
+      return true;
+  return false;
+}
+
+// Check if what is part of the ith argument (counting from 1) to a function of type ftype.
+// If what is 0, just check if hte ith argument is in registers.
+bool
+stm8IsRegArg(struct sym_link *ftype, int i, const char *what)
+{
+  if (what && !strcmp(what, "x"))
+    return (stm8IsRegArg (ftype, i, "xl") || stm8IsRegArg (ftype, i, "xh"));
+  else if (what && !strcmp(what, "y"))
+    return (stm8IsRegArg (ftype, i, "yl") || stm8IsRegArg (ftype, i, "yh"));
+ 
+  const asmop *argaop = aopArg (ftype, i);
+
+  if (!argaop)
+    return false;
+    
+  if (!what)
+    return true;
+    
+  for (int i = 0; i < argaop->size; i++)
+    if (!strcmp(argaop->aopu.bytes[i].byteu.reg->name, what))
+      return true;
+
+  return false; 
+}
+
+bool
+stm8IsParmInCall(sym_link *ftype, const char *what)
+{
+  const value *args;
+  int i;
+
+  for (i = 1, args = FUNC_ARGS (ftype); args; args = args->next, i++)
+    if (stm8IsRegArg(ftype, i, what))
+      return true;
+  return false;
+}
+
diff -Nru sdcc-4.0.0+dfsg/src/stm8/gen.h sdcc-4.2.0+dfsg/src/stm8/gen.h
--- sdcc-4.0.0+dfsg/src/stm8/gen.h	2018-10-29 07:36:38.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/stm8/gen.h	2021-05-12 14:21:30.000000000 +0000
@@ -21,6 +21,8 @@
 #ifndef STM8GEN_H
 #define STM8GEN_H 1
 
+#include "ralloc.h"
+
 typedef enum
 {
   AOP_INVALID,
@@ -82,6 +84,15 @@
 void genSTM8Code (iCode *);
 void stm8_emitDebuggerSymbol (const char *);
 
+bool stm8IsReturned(const char *what);
+
+// Check if what is part of the ith argument (counting from 1) to a function of type ftype.
+// If what is 0, just check if hte ith argument is in registers.
+bool stm8IsRegArg(struct sym_link *ftype, int i, const char *what);
+
+// Check if what is part of the any argument (counting from 1) to a function of type ftype.
+bool stm8IsParmInCall(sym_link *ftype, const char *what);
+
 extern bool stm8_assignment_optimal;
 extern long int stm8_call_stack_size;
 extern bool stm8_extend_stack;
diff -Nru sdcc-4.0.0+dfsg/src/stm8/main.c sdcc-4.2.0+dfsg/src/stm8/main.c
--- sdcc-4.0.0+dfsg/src/stm8/main.c	2019-09-03 09:59:09.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/stm8/main.c	2022-02-03 09:32:48.000000000 +0000
@@ -35,6 +35,7 @@
 #define OPTION_CODE_SEG        "--codeseg"
 #define OPTION_CONST_SEG       "--constseg"
 #define OPTION_ELF             "--out-fmt-elf"
+#define OPTION_SDCCCALL        "--sdcccall"
 
 extern DEBUGFILE dwarf2DebugFile;
 extern int dwarf2FinalizeFile(FILE *);
@@ -45,6 +46,7 @@
   {0, OPTION_CODE_SEG,        &options.code_seg, " use this name for the code segment", CLAT_STRING},
   {0, OPTION_CONST_SEG,       &options.const_seg, " use this name for the const segment", CLAT_STRING},
   {0, OPTION_ELF,             NULL, "Output executable in ELF format"},
+  {0, OPTION_SDCCCALL,         &options.sdcccall, "Set ABI version for default calling convention", CLAT_INTEGER},
   {0, NULL}
 };
 
@@ -54,6 +56,17 @@
   P_CONSTSEG,
 };
 
+static struct
+{
+  // Determine if we can put parameters in registers
+  struct
+  {
+    int n;
+    struct sym_link *ftype;
+  } regparam;
+}
+_G;
+
 static int
 stm8_do_pragma (int id, const char *name, const char *cp)
 {
@@ -138,6 +151,10 @@
   "interrupt",
   "trap",
   "naked",
+  "raisonance",
+  "iar",
+  "cosmic",
+  "z88dk_callee",
   NULL
 };
 
@@ -150,34 +167,41 @@
     }
 }
 
+extern void stm8_init_asmops (void);
+
 static void
 stm8_init (void)
 {
   asm_addTree (&asm_asxxxx_mapping);
-}
 
+  stm8_init_asmops ();
+}
 
 static void
-stm8_reset_regparm (struct sym_link *funcType)
+stm8_reset_regparm (struct sym_link *ftype)
 {
+  _G.regparam.n = 0;
+  _G.regparam.ftype = ftype;
 }
 
 static int
-stm8_reg_parm (sym_link * l, bool reentrant)
+stm8_reg_parm (sym_link *l, bool reentrant)
 {
-  return FALSE;
+  bool is_regarg = stm8IsRegArg(_G.regparam.ftype, ++_G.regparam.n, 0);
+
+  return (is_regarg ? _G.regparam.n : 0);
 }
 
 static bool
 stm8_parseOptions (int *pargc, char **argv, int *i)
 {
-  if (!strcmp (argv[*i], "--out-fmt-elf"))
+  if (!strncmp (argv[*i], OPTION_ELF, sizeof (OPTION_ELF) - 1))
   {
     options.out_fmt = 'E';
     debugFile = &dwarf2DebugFile;
-    return TRUE;
+    return true;
   }
-  return FALSE;
+  return false;
 }
 
 static void
@@ -234,8 +258,6 @@
 static void
 stm8_genInitStartup (FILE *of)
 {
-  fprintf (of, "__sdcc_gs_init_startup:\n");
-
   if (options.stack_loc >= 0)
     {
       fprintf (of, "\tldw\tx, #0x%04x\n", options.stack_loc);
@@ -313,6 +335,8 @@
   switch (ic->op)
     {
     case '/':
+      if (getSize (left) <= 2 && getSize (right) <= 2 && IS_LITERAL (right) && isPowerOf2 (ulFromVal (valFromType (right))) && ulFromVal (valFromType (right)) <= 32) // Using arithmetic right-shift is worth it for small divisors only.
+        return true;
     case '%':
       return (getSize (left) <= 2 && IS_UNSIGNED (left) && getSize (right) <= 2 && IS_UNSIGNED (right));
     case '*':
@@ -327,8 +351,8 @@
         int topbit, nonzero;
         
 
-        if (floatFromVal (valFromType (test)) < 0 || csdOfVal (&topbit, &nonzero, &add, &sub, valFromType (test)))
-          return FALSE;
+        if (floatFromVal (valFromType (test)) < 0 || csdOfVal (&topbit, &nonzero, &add, &sub, valFromType (test), 0xffff))
+          return false;
 
         int shifts = topbit;
 
@@ -353,7 +377,10 @@
 static bool
 hasExtBitOp (int op, int size)
 {
-  return (op == GETABIT);
+  return (op == GETABIT || op == GETBYTE || op == GETWORD ||
+    op == SWAP && (size <= 2 || size == 4) ||
+    op == RLC && size <= 2 ||
+    op == RRC && size <= 2);
 }
 
 static const char *
@@ -432,6 +459,8 @@
     stm8canAssign,
     stm8notUsedFrom,
     NULL,
+    NULL,
+    NULL,
   },
   /* Sizes: char, short, int, long, long long, ptr, fptr, gptr, bit, float, max */
   {
@@ -444,7 +473,7 @@
     2,                          /* far ptr */
     2,                          /* generic ptr */
     2,                          /* func ptr */
-    0,                          /* banked func ptr */
+    3,                          /* banked func ptr */
     1,                          /* bit */
     4,                          /* float */
   },
@@ -478,6 +507,7 @@
     1                           /* No fancy alignments supported. */
   },
   { stm8_genExtraArea, NULL },
+  1,                            /* default ABI revision */
   {                             /* stack information */
     -1,                         /* stack grows down */
      0,
@@ -487,7 +517,10 @@
      2,
      1,                         /* sp points to next free stack location */
   },     
-  { -1, TRUE },
+  { 
+    -1,                         /* shifts never use support routines */
+    true,                       /* use support routine for int x int -> long multiplication */
+  },
   { stm8_emitDebuggerSymbol,
     {
       stm8_dwarfRegNum,
diff -Nru sdcc-4.0.0+dfsg/src/stm8/peep.c sdcc-4.2.0+dfsg/src/stm8/peep.c
--- sdcc-4.0.0+dfsg/src/stm8/peep.c	2019-08-14 12:49:17.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/stm8/peep.c	2021-09-23 21:28:06.000000000 +0000
@@ -4,6 +4,7 @@
 #include "SDCCgen.h"
 
 #include "peep.h"
+#include "gen.h"
 
 #define NOTUSEDERROR() do {werror(E_INTERNAL_ERROR, __FILE__, __LINE__, "error in notUsed()");} while(0)
 
@@ -30,6 +31,9 @@
   lineNode *head;
 } _G;
 
+extern bool stm8_regs_used_as_parms_in_calls_from_current_function[YH_IDX + 1];
+extern bool stm8_regs_used_as_parms_in_pcalls_from_current_function[YH_IDX + 1];
+
 /*----------------------------------------------------------------------------*/
 /* strNextCharBlock - Returns the next block of chars (after spaces, comma)   */
 /* Leading spaces and Current block are skipped and search stops at next block*/
@@ -600,13 +604,11 @@
 
   /* 3. search lineNode with label definition and return it */
   for (cpl = _G.head; cpl; cpl = cpl->next)
-    {
-      if (   cpl->isLabel
-          && strncmp (p, cpl->line, strlen(p)) == 0)
-        {
-          return cpl;
-        }
-    }
+    if (cpl->isLabel &&
+      strncmp (p, cpl->line, strlen(p)) == 0 &&
+      cpl->line[strlen(p)] == ':')
+        return cpl;
+
   return NULL;
 }
 
@@ -628,8 +630,10 @@
   if (arg[0] == '#')
     return FALSE;
 
-  if (arg[0] == '(' && arg[1] == '0' && (tolower(arg[2])) == 'x') 
-    arg += 3; // Skip hex prefix to avoid false x positive.
+  if (arg[0] == '(') 
+    arg++;
+  if (arg[0] == '0' && (tolower(arg[1])) == 'x') 
+    arg += 2; // Skip hex prefix to avoid false x positive.
 
   if (strlen(arg) == 0)
     return FALSE;
@@ -641,64 +645,6 @@
 }
 
 static bool
-isReturned(const char *what)
-{
-  symbol *sym;
-  sym_link *sym_lnk;
-  int size;
-  lineNode *l;
-
-  l = _G.head;
-  do
-  {
-    l = l->next;
-  } while(l->isComment || l->ic == NULL || l->ic->op != FUNCTION);
-
-  sym = OP_SYMBOL(IC_LEFT(l->ic));
-
-  if(sym && IS_DECL(sym->type))
-    {
-      // Find size of return value.
-      specifier *spec;
-      if(sym->type->select.d.dcl_type != FUNCTION)
-        NOTUSEDERROR();
-      spec = &(sym->etype->select.s);
-      if(spec->noun == V_VOID)
-        size = 0;
-      else if(spec->noun == V_CHAR || spec->noun == V_BOOL)
-        size = 1;
-      else if(spec->noun == V_INT && !(spec->b_long))
-        size = 2;
-      else
-        size = 4;
-
-      // Check for returned pointer.
-      sym_lnk = sym->type;
-      while (sym_lnk && !IS_PTR (sym_lnk))
-        sym_lnk = sym_lnk->next;
-      if(IS_PTR(sym_lnk))
-        size = 2;
-    }
-  else
-    {
-      NOTUSEDERROR();
-      return TRUE;
-    }
-
-  switch(*what)
-    {
-    case 'a':
-      return(size == 1);
-    case 'x':
-      return(size > 1);
-    case 'y':
-      return(size > 2);
-    default:
-      return FALSE;
-    }
-}
-
-static bool
 stm8MightReadFlag(const lineNode *pl, const char *what)
 {
   if (strcmp (what, "c") && strcmp (what, "n") && strcmp (what, "z"))
@@ -707,11 +653,14 @@
   if (ISINST (pl->line, "push"))
      return (pl->line[5] == 'c');
 
+  if (!strcmp (what, "v"))
+    return (ISINST (pl->line, "jrnv") || ISINST (pl->line, "jrsge") || ISINST (pl->line, "jrsgt") || ISINST (pl->line, "jrsle") || ISINST (pl->line, "jrslt") || ISINST (pl->line, "jrv"));
+
   if (!strcmp (what, "n"))
-    return (ISINST (pl->line, "jrmi") || ISINST (pl->line, "jrpl") || ISINST (pl->line, "jrsge") || ISINST (pl->line, "jrsgte") || ISINST (pl->line, "jrsle") || ISINST (pl->line, "jrslt"));
+    return (ISINST (pl->line, "jrmi") || ISINST (pl->line, "jrpl") || ISINST (pl->line, "jrsge") || ISINST (pl->line, "jrsgt") || ISINST (pl->line, "jrsle") || ISINST (pl->line, "jrslt"));
 
   if (!strcmp (what, "z"))
-    return (ISINST (pl->line, "jreq") || ISINST (pl->line, "jrne") || ISINST (pl->line, "jrsgte") || ISINST (pl->line, "jrsle"));
+    return (ISINST (pl->line, "jreq") || ISINST (pl->line, "jrne") || ISINST (pl->line, "jrsgt") || ISINST (pl->line, "jrsle"));
 
   if (!strcmp (what, "c"))
     return (ISINST (pl->line, "jrc") || ISINST (pl->line, "jrnc") || ISINST (pl->line, "jruge") || ISINST (pl->line, "jrugt") || ISINST (pl->line, "jrule") || ISINST (pl->line, "jrult") ||
@@ -722,6 +671,44 @@
 }
 
 static bool
+stm8MightBeParmInCallFromCurrentFunction(const char *what)
+{
+  if (!strcmp(what, "a"))
+    return stm8_regs_used_as_parms_in_calls_from_current_function[A_IDX];
+    
+  if ((!strcmp(what, "x") || !strcmp(what, "xl")) && stm8_regs_used_as_parms_in_calls_from_current_function[XL_IDX])
+    return true;
+  if ((!strcmp(what, "x") || !strcmp(what, "xh")) && stm8_regs_used_as_parms_in_calls_from_current_function[XH_IDX])
+    return true;
+
+  if ((!strcmp(what, "y") || !strcmp(what, "yl")) && stm8_regs_used_as_parms_in_calls_from_current_function[YL_IDX])
+    return true;
+  if ((!strcmp(what, "yx") || !strcmp(what, "yh")) && stm8_regs_used_as_parms_in_calls_from_current_function[YH_IDX])
+    return true;
+
+  return false;
+}
+
+static bool
+stm8MightBeParmInPCallFromCurrentFunction(const char *what)
+{
+  if (!strcmp(what, "a"))
+    return stm8_regs_used_as_parms_in_pcalls_from_current_function[A_IDX];
+
+  if ((!strcmp(what, "x") || !strcmp(what, "xl")) && stm8_regs_used_as_parms_in_pcalls_from_current_function[XL_IDX])
+    return true;
+  if ((!strcmp(what, "x") || !strcmp(what, "xh")) && stm8_regs_used_as_parms_in_pcalls_from_current_function[XH_IDX])
+    return true;
+
+  if ((!strcmp(what, "y") || !strcmp(what, "yl")) && stm8_regs_used_as_parms_in_pcalls_from_current_function[YL_IDX])
+    return true;
+  if ((!strcmp(what, "yx") || !strcmp(what, "yh")) && stm8_regs_used_as_parms_in_pcalls_from_current_function[YH_IDX])
+    return true;
+
+  return false;
+}
+
+static bool
 stm8MightRead(const lineNode *pl, const char *what)
 {
   char extra = 0;
@@ -843,7 +830,9 @@
 
       if (ISINST (pl->line, "ld") || ISINST (pl->line, "ldw"))
         {
-          char buf[64], *p;
+          char buf[128], *p;
+          if (strlen (pl->line) >= 128) // Avoid buffer overflow, err on safe side.
+            return TRUE;
           strcpy (buf, pl->line);
           if (!!(p = strstr (buf, "0x")) || !!(p = strstr (buf, "0X")))
             p[0] = p[1] = ' ';
@@ -852,8 +841,20 @@
         }
     }
 
-  if(ISINST(pl->line, "ret") || ISINST(pl->line, "retf"))
-    return(isReturned(what));
+  if (ISINST (pl->line, "call") || ISINST (pl->line, "callr") || ISINST (pl->line, "callf"))
+    {
+      const symbol *f = findSym (SymbolTab, 0, pl->line + (ISINST (pl->line, "call") ? 6 : 7));
+      if (f)
+        return stm8IsParmInCall(f->type, what);
+      else // Fallback needed for calls through function pointers and for calls to literal addresses.
+        return (stm8MightBeParmInCallFromCurrentFunction(what) || stm8MightBeParmInPCallFromCurrentFunction(what));
+    }
+
+  if(ISINST(pl->line, "ret")) // IAR calling convention uses ret for some calls via pointers
+    return(stm8IsReturned(what) || stm8MightBeParmInPCallFromCurrentFunction(what));
+
+  if(ISINST(pl->line, "retf")) // Large model uses retf for calls via function pointers
+    return(stm8IsReturned(what) || stm8MightBeParmInPCallFromCurrentFunction(what));
 
   return FALSE;
 }
@@ -874,6 +875,23 @@
 static bool
 stm8SurelyWritesFlag(const lineNode *pl, const char *what)
 {
+  if (!strcmp (what, "v") || !strcmp (what, "c"))
+    {        
+      if (ISINST (pl->line, "addw") && !strcmp (pl->line + 5, "sp"))
+        return false;
+      if (ISINST (pl->line, "sub") && !strcmp (pl->line + 4, "sp"))
+        return false;
+
+      if (ISINST (pl->line, "adc") ||
+        STARTSINST (pl->line, "add") || // add, addw
+        STARTSINST (pl->line, "cp") || // cp, cpw, cpl, cplw
+        STARTSINST (pl->line, "div") || // div, divw
+        STARTSINST (pl->line, "neg") || // neg, negw
+        ISINST (pl->line, "sbc") ||
+        STARTSINST (pl->line, "sub")) // sub, subw
+        return true;
+    }
+
   if (!strcmp (what, "n") || !strcmp (what, "z"))
     {
       if (ISINST (pl->line, "addw") && !strcmp (pl->line + 5, "sp"))
@@ -906,20 +924,11 @@
         return false;
       return true;
     }
-  else if (!strcmp (what, "c"))
-    {        
-      if (ISINST (pl->line, "addw") && !strcmp (pl->line + 5, "sp"))
-        return false;
-      if (ISINST (pl->line, "sub") && !strcmp (pl->line + 4, "sp"))
-        return false;
-        
-      if (ISINST (pl->line, "adc") ||
-        STARTSINST (pl->line, "add") || // add, addw
-        STARTSINST (pl->line, "btj") || // btjt, btjf
+
+  if (!strcmp (what, "c"))
+    {
+      if (STARTSINST (pl->line, "btj") || // btjt, btjf
         ISINST (pl->line, "ccf") ||
-        STARTSINST (pl->line, "cp") || // cp, cpw, cpl, cplw
-        STARTSINST (pl->line, "div") || // div, divw
-        STARTSINST (pl->line, "neg") || // neg, negw
         ISINST (pl->line, "rcf") ||
         STARTSINST (pl->line, "rlc") || // rlc, rlcw
         STARTSINST (pl->line, "rrc") || // rrc, rrcw
diff -Nru sdcc-4.0.0+dfsg/src/stm8/peeph.def sdcc-4.2.0+dfsg/src/stm8/peeph.def
--- sdcc-4.0.0+dfsg/src/stm8/peeph.def	2019-10-24 09:50:53.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/stm8/peeph.def	2021-10-18 11:25:35.000000000 +0000
@@ -7,10 +7,10 @@
 } if notVolatile(%1), notVolatile(%2), notUsed(%1), notUsed('n'), notUsed('z')
 
 replace restart {
-	ldw	a, (%2, sp)
+	ld	a, (%2, sp)
 } by {
-	; peephole 0a removed dead load into a from %2.
-} if notUsed('n'), notUsed('z')
+	; peephole 0a removed dead load into a from (%2, sp).
+} if notUsed('a'), notUsed('n'), notUsed('z')
 
 replace restart {
 	ldw	%1, %2
@@ -21,7 +21,7 @@
 replace restart {
 	ldw	%1, (%2, sp)
 } by {
-	; peephole 0wa removed dead load into %1 from %2.
+	; peephole 0wa removed dead load into %1 from (%2, sp).
 } if notUsed(%1), notUsed('n'), notUsed('z')
 
 replace restart {
@@ -143,7 +143,7 @@
 } by {
 	; peephole 8 moved addition of offset into storage instruction
 	ldw	(%2, %1), %3
-} if notUsed(%1)
+} if notUsed(%1), notUsed('c')
 
 replace restart {
 	addw	%1, #%2
@@ -153,7 +153,7 @@
 	; peephole 9 moved addition of offset into storage instruction
 	ld	a, %4
 	ld	(%2, %1), a
-} if notUsed(%1)
+} if notUsed(%1), notUsed('c')
 
 replace restart {
 	addw	%1, #%2
@@ -161,7 +161,7 @@
 } by {
 	; peephole 9a moved addition of offset into clear instruction
 	clr	(%2, %1)
-} if notUsed(%1)
+} if notUsed(%1), notUsed('c')
 
 replace restart {
 	addw	%1, #%2
@@ -171,7 +171,7 @@
 	; peephole 10 moved addition of offset into storage instruction
 	ldw	%3, %4
 	ldw	(%2, %1), %3
-} if notUsed(%1)
+} if notUsed(%1), notUsed('c')
 
 replace restart {
 	incw	%1
@@ -185,6 +185,66 @@
 } if notUsed(%1)
 
 replace restart {
+	addw	%1, #(_%2)
+	ld	a, (%1)
+} by {
+	; peephole 10b moved addition of offset into storage instruction
+	ld	a, (_%2, %1)
+} if notUsed(%1), notUsed('c')
+
+replace restart {
+	addw	%1, #(_%2)
+	inc	(%1)
+} by {
+	; peephole 10c moved addition of offset into increment instruction
+	inc	(_%2, %1)
+} if notUsed(%1), notUsed('c')
+
+replace restart {
+	addw	%1, #(_%2)
+	ldw	%1, (%1)
+} by {
+	; peephole 10d moved addition of offset into storage instruction
+	ldw	%1, (_%2, %1)
+}if notUsed('c')
+
+replace restart {
+	addw	%1, #(_%2)
+	ld	(%1), a
+} by {
+	; peephole 10e moved addition of offset into storage instruction
+	ld	(_%2, %1), a
+} if notUsed(%1), notUsed('c')
+
+replace restart {
+	ldw %1, sp
+	addw    %1, #%2
+	ld	a, (%1)
+} by {
+	ld	a, (%2, sp)
+	; peephole 10f moved addition to sp to storage instruction.
+} if notUsed(%1), notUsed('c'), operandsLiteral(%2), immdInRange(0 255 '+' 0 %2 %9)
+
+replace restart {
+	ldw	%1, sp
+	incw	x
+	ld	a, (%1)
+} by {
+	ld	a, (1, sp)
+	; peephole 10g moved increment to sp into storage instruction.
+} if notUsed(%1)
+
+replace restart {
+	ldw	%1, sp
+	incw	x
+	incw	x
+	ld	a, (%1)
+} by {
+	ld	a, (2, sp)
+	; peephole 10h moved increments to sp into storage instruction.
+} if notUsed(%1)
+
+replace restart {
 	ldw	(%1, sp), x
 	ldw	x, (%2, sp)
 	addw	x, (%1, sp)
@@ -269,312 +329,489 @@
 	; peephole 16 applied %2 on %1 instead of a.
 } if notUsed('a'), notSame(%2 'push' 'pop'), notSame(%1 'xl' 'xh' 'yl' 'yh')
 
+// Remove use of extra index register
 replace restart {
-	ld	a, %1
-	or	a, #0x80
-	ld	%1, a
+	ldw	%2, #%1
+	ldw	%3, #%1
+	ld	a, (%3)
 } by {
-	rlc	%1
-	scf
-	rrc	%1
-	; peephole 17 set msb in carry instead of a.
-} if notUsed('a'), notSame(%1 'xl' 'xh' 'yl' 'yh'), notUsed('c'), notVolatile(%1)
+	ldw	%2, #%1
+	ld	a, (%2)
+	; peephole 101 removed use of extra index register (%3).
+} if notUsed(%3)
 
+// XOR-AND with same operand to CPL-AND saving 1 byte
 replace restart {
-	ld	a, %1
-	or	a, #0x01
-	ld	%1, a
+	xor	a, #%1
+	and	a, #%2
 } by {
-	bset	%2, #0
-	; peephole 18-0 replaced or by bset.
-} if notUsed('a'), operandsLiteral(%1), immdInRange(0 65535 '+' 0 %1 %2)
+	cpl	a
+	and	a, #%1
+	; peephole 110 replaced 'xor-and' by 'cpl-and'.
+} if operandsLiteral(%1 %2), immdInRange(0 0 '^' %1 %2 %3), notUsed('c')
+	
+// AND-CP with same operand (and only z is used) to CPL-BCP saving 1 byte
+replace restart {
+	and	a, #%1
+	cp	a, #%2
+} by {
+	cpl	a
+	bcp	a, #%1
+	; peephole 111 replaced 'and-cp' by 'cpl-bcp'.
+} if operandsLiteral(%1 %2), immdInRange(0 0 '^' %1 %2 %3), notUsed('a' 'n' 'c')
 
+// Combine double AND in one AND
 replace restart {
-	ld	a, %1
-	or	a, #0x02
-	ld	%1, a
+	and	a, #%1
+	and	a, #%2
 } by {
-	bset	%2, #1
-	; peephole 18-1 replaced or by bset.
-} if notUsed('a'), operandsLiteral(%1), immdInRange(0 65535 '+' 0 %1 %2)
+	and	a, #%3
+	; peephole 130 combined 'and-and' (%1, %2) into 'and' (%3).
+} if operandsLiteral(%1 %2), immdInRange(0 255 '&' %1 %2 %3)
 
+// Remove unneeded AND before CPL-AND with same operand or when the second AND operand is a subset of the first AND bits
 replace restart {
-	ld	a, %1
-	or	a, #0x04
-	ld	%1, a
+	and	a, #%1
+	cpl	a
+	and	a, #%2
 } by {
-	bset	%2, #2
-	; peephole 18-2 replaced or by bset.
-} if notUsed('a'), operandsLiteral(%1), immdInRange(0 65535 '+' 0 %1 %2)
+	; peephole 131 removed unneeded 'and' before 'cpl-and'.
+	cpl a
+	and a, #%2
+} if operandsLiteral(%1 %2), immdInRange(0 255 '&' %1 %2 %3), immdInRange(0 0 '^' %2 %3 %4)
 
+// Combine AND in AND-OR / XOR-AND
 replace restart {
-	ld	a, %1
-	or	a, #0x08
-	ld	%1, a
+	and	a, #%1
+	%4	a, #%2
+	and	a, #%3
 } by {
-	bset	%2, #3
-	; peephole 18-3 replaced or by bset.
-} if notUsed('a'), operandsLiteral(%1), immdInRange(0 65535 '+' 0 %1 %2)
+	and	a, #%5
+	%4	a, #%6
+	; peephole 132 removed unneded and in 'and-%4-and' (%1 %2 %3) -> (%5 %6).
+} if operandsLiteral(%1 %2 %3), same(%4 'or' 'xor') immdInRange(0 255 '&' %1 %3 %5), immdInRange(0 255 '&' %2 %3 %6)
 
+// This is generated by some other peephole rules, not by normal code generator
+// It happens after simplifiying expressions like Nibbles.low ^= 0xF0;
 replace restart {
-	ld	a, %1
-	or	a, #0x10
-	ld	%1, a
+	xor	a, #0
 } by {
-	bset	%2, #4
-	; peephole 18-4 replaced or by bset.
-} if notUsed('a'), operandsLiteral(%1), immdInRange(0 65535 '+' 0 %1, %2)
+	; peephole 133 removed xor with 0 
+} if notUsed('n' 'z')
 
 replace restart {
-	ld	a, %1
-	or	a, #0x20
-	ld	%1, a
+	and	a, #255
 } by {
-	bset	%2, #5
-	; peephole 18-5 replaced or by bset.
-} if notUsed('a'), operandsLiteral(%1), immdInRange(0 65535 '+' 0 %1 %2)
+	; peephole 134 removed and with 255
+} if notUsed('n' 'z')
 
+// Reverse A0 bit and move it to carry, shift it left or right
 replace restart {
-	ld	a, %1
-	or	a, #0x40
-	ld	%1, a
+	and	a, #%1
+	sub	a, #%2
+	clr	a
+	rlc	a
+	s%3	a
 } by {
-	bset	%2, #6
-	; peephole 18-6 replaced or by bset.
-} if notUsed('a'), operandsLiteral(%1), immdInRange(0 65535 '+' 0 %1 %2)
+	and	a, #%1
+	xor	a, #%1
+	s%3	a
+	; peephole 140 replaced 'and-sub-clr-rlc-s%3' to reverse A0 bit by 'xor-and-s%3'.
+} if same(%3 'rl' 'll'), operandsLiteral(%1 %2), immdInRange(0 0 '^' %1 %2 %4), immdInRange(0 0 '^' %1 1 %5)
 
+// Reverse A0 bit
 replace restart {
-	ld	a, %1
-	or	a, #0x80
-	ld	%1, a
+	and	a, #%1
+	sub	a, #%2
+	clr	a
+	rlc	a
 } by {
-	bset	%2, #7
-	; peephole 18-7 replaced or by bset.
-} if notUsed('a'), operandsLiteral(%1), immdInRange(0 65535 '+' 0 %1 %2)
+	and	a, #%1
+	xor	a, #%1
+	; peephole 141 replaced 'and-sub-clr-rlc' to reverse A0 bit by 'xor-and'.
+} if operandsLiteral(%1 %2), immdInRange(0 0 '^' %1 %2 %4), immdInRange(0 0 '^' %1 1 %5), notUsed('c')
+  
+// Reverse bit A3-A2-A1 and post swap
+replace restart {
+	srl	a
+	cpl	a
+	and	a, #%1
+	swap	a
+	sll	a
+} by {
+	cpl	a
+	and	a, #%2
+	swap	a
+	; peephole 143 replaced 'srl-cpl-and-swap-sll' (%1) to reverse bits by 'cpl-and-swap' (%2).
+} if operandsLiteral(%1), immdInRange(0 0 '&' %1 0xF8 %4), immdInRange(2 0x0E '*' %1 2 %2), notUsed('c')
+
+// Reverse bits with pre-post swap
+replace restart {
+	swap	a
+	cpl	a
+	and	a, #%1
+	swap	a
+} by {
+	cpl a
+	and a, #%2
+	; peephole 144 replaced 'swap-cpl-and-swap' (%1) to reverse bits by 'cpl-and' with swapped and literal (%2).
+} if operandsLiteral(%1), immdInRange(0 255 'swap' %1 8 %2)
+
+replace restart {
+	swap	a
+	and	a, #%1
+	cpl	a
+	swap	a
+} by {
+	and	a, #%2
+	cpl	a
+	; peephole 145 replaced 'swap-and-cpl-swap' (%1) to reverse bits by 'and-cpl' with swapped and literal (%2).
+} if operandsLiteral(%1), immdInRange(0 255 'swap' %1 8 %2)
 
+// copy reversed bit to carry (xor-and)
 replace restart {
-	ld	a, %1
-	and	a, #0xfe
-	ld	%1, a
+	and	a, #%1
+	xor	a, #%1
+	srl	a
 } by {
-	bres	%2, #0
-	; peephole 19-0 replaced and by bres.
-} if notUsed('a'), operandsLiteral(%1), immdInRange(0 65535 '+' 0 %1 %2)
+	and	a, #%1
+	sub	a, #%1
+	; peephole 150 replaced 'xor-and-srl' by 'and-sub'.
+} if operandsLiteral(%1), immdInRange(1 1 '+' 0 %1 %2), notUsed('a' 'n' 'z')
 
+// copy reversed bit to carry with previous shift right
 replace restart {
-	ld	a, %1
-	and	a, #0xfd
-	ld	%1, a
+	srl	a
+	and	a, #%1
+	sub	a, #%1
 } by {
-	bres	%2, #1
-	; peephole 19-1 replaced and by bres.
-} if notUsed('a'), operandsLiteral(%1), immdInRange(0 65535 '+' 0 %1 %2)
+	and	a, #%3
+	sub	a, #%3
+	; peephole 153 replaced 'srl-and-sub' (%1) by 'and-sub' (%3).
+} if operandsLiteral(%1), immdInRange(0 7 'singleSetBit' %1 8 %2), immdInRange(2 255 '*' %1 2 %3), notUsed('a' 'n' 'z')
+
+// copy reversed bit to carry with previous swap
+replace restart {
+	swap	a
+	and	a, #%1
+	sub	a, #%1
+} by {
+	and	a, #%3
+	sub	a, #%3
+	; peephole 154 replaced 'swap-and-sub' (%1) by 'and-sub' (%3).
+} if operandsLiteral(%1), immdInRange(0 7 'singleSetBit' %1 8 %2), immdInRange(0 255 'swap' %1 8 %3), notUsed('a' 'n' 'z')
 
+// SRL - XOR - AND - SLL, not using carry later
 replace restart {
-	ld	a, %1
-	and	a, #0xfb
-	ld	%1, a
+	srl	a
+	and	a, #%2
+	xor	a, #%1
+	sll	a
+} by {
+	and	a, #%5
+	xor	a, #%3
+	; peephole 160 replaced 'srl-xor-and-sll' (%1, %2) by 'xor-and' (%3, %5).
+} if operandsLiteral(%1 %2), immdInRange(2 255 '*' %1 2 %3), immdInRange(2 255 '*' %2 2 %4), immdInRange(0 255 '|' %4 1 %5), notUsed('c')
+
+// SRL - CPL - AND - SLL, not using carry later
+replace restart {
+	srl	a
+	cpl	a
+	and	a, #%2
+	sll	a
 } by {
-	bres	%2, #2
-	; peephole 19-2 replaced and by bres.
-} if notUsed('a'), operandsLiteral(%1), immdInRange(0 65535 '+' 0 %1 %2)
+	and a, #%5
+	xor a, #%4
+	; peephole 161 replaced 'srl-cpl-and-sll' (%2) by 'xor-and' (%4, %5).
+} if operandsLiteral(%2), immdInRange(2 255 '*' %2 2 %4), immdInRange(0 255 '|' %4 1 %5), notUsed('c')
 
+// Replace swaps by swapping literal values instead
 replace restart {
-	ld	a, %1
-	and	a, #0xf7
-	ld	%1, a
+	swap	a
+	%1	a, #%4
+	%2	a, #%5
+	swap	a
+} by {
+	%1	a, #%8
+	%2	a, #%9
+	; peephole 170 replaced swaps by swapping literal values of '%1-%2' (%4, %5) -> (%8, %9).
+}if same(%1 'and' 'or' 'xor'), same(%2 'and' 'or' 'xor'), operandsLiteral(%4 %5), immdInRange(0 255 'swap' %4 8 %8), immdInRange(0 255 'swap' %5 8 %9)
+
+replace restart {
+	swap	a
+	%1	a, #%4
+	swap	a
 } by {
-	bres	%2, #3
-	; peephole 19-3 replaced and by bres.
-} if notUsed('a'), operandsLiteral(%1), immdInRange(0 65535 '+' 0 %1 %2)
+	%1	a, #%8
+	; peephole 171 replaced swaps by swapping literal values of '%1' (%4) -> (%8).
+}if same(%1 'and' 'or' 'xor'), operandsLiteral(%4), immdInRange(0 255 'swap' %4 8 %8)
 
+// Optimize comparisons of 8 bits using 16 bits reg by using only 'a'
+replace restart {
+	clrw	%6
+	ld	a, (%1, sp)
+	and	a, #%2
+	ld	%6l, a
+	cpw	%6, #%3
+} by {
+	ld	a, (%1, sp)
+	and	a, #%2
+	cp	a, #%4
+	; peephole 180 replaced comparison operation using '%6' with comparison operation using 'a'
+} if operandsLiteral(%2 %3), immdInRange(0 127 '+' 0 %3 %4), immdInRange(0 127 '+' 0 %2 %5), notUsed(%6)
+
+// Value |= (1 << X)
 replace restart {
 	ld	a, %1
-	and	a, #0xef
+	or	a, #%3
 	ld	%1, a
 } by {
-	bres	%2, #4
-	; peephole 19-4 replaced and by bres.
-} if notUsed('a'), operandsLiteral(%1), immdInRange(0 65535 '+' 0 %1 %2)
+	bset	%1, #%4
+	; peephole 202x replaced 'or' by 'bset' ('%1').
+} if operandsLitOrSym(%1), operandsLiteral(%3), immdInRange(0 7 'singleSetBit' %3 8 %4), notUsed('a' 'n' 'z')
+
+// Value |= (1 << X)
+replace restart {
+	ldw	%2, #%1
+	ld	a, (%2)
+	or	a, #%3
+	ld	(%2), a
+} by {
+	ldw	%2, #%1
+	bset	%10, #%4
+	; peephole 203x replaced 'or' by 'bset' (index register) ('%1' -> '%10').
+} if operandsLiteral(%3), immdInRange(0 7 'singleSetBit' %3 8 %4), notUsed('a' 'n' 'z'), removeParentheses(%1 %10)
 
+// Value &= ~(1 << X)
 replace restart {
 	ld	a, %1
-	and	a, #0xdf
+	and	a, #%3
 	ld	%1, a
 } by {
-	bres	%2, #5
-	; peephole 19-5 replaced and by bres.
-} if notUsed('a'), operandsLiteral(%1), immdInRange(0 65535 '+' 0 %1 %2)
+	bres	%1, #%4
+	; peephole 204x replaced 'and' by 'bres' ('%1').
+} if operandsLitOrSym(%1), operandsLiteral(%3), immdInRange(0 7 'singleResetBit' %3 8 %4), notUsed('a' 'n' 'z')
 
+// Value &= ~(1 << X)
+replace restart {
+	ldw	%2, #%1
+	ld	a, (%2)
+	and	a, #%3
+	ld	(%2), a
+} by {
+	ldw	%2, #%1
+	bres	%10, #%4
+	; peephole 205x replaced 'and' by 'bres' (index register) ('%1' -> '%10').
+} if operandsLiteral(%3), immdInRange(0 7 'singleResetBit' %3 8 %4), notUsed('a' 'n' 'z'), removeParentheses(%1 %10)
+
+// Value ^= (1 << X)
 replace restart {
 	ld	a, %1
-	and	a, #0xbf
+	xor	a, #%3
 	ld	%1, a
 } by {
-	bres	%2, #6
-	; peephole 19-6 replaced and by bres.
-} if notUsed('a'), operandsLiteral(%1), immdInRange(0 65535 '+' 0 %1 %2)
+	bcpl	%1, #%4
+	; peephole 210x replaced 'xor' by 'bcpl' ('%1').
+} if operandsLitOrSym(%1), operandsLiteral(%3), immdInRange(0 7 'singleSetBit' %3 8 %4), notUsed('a' 'n' 'z')
+  
+//*** XOR special cases
+// bccm to bcpl
+replace restart {
+	ld	a, %1
+	and	a, #%3
+	sub	a, #%3
+	bccm	%1, #%4
+} by {
+	bcpl	%1, #%4
+	; peephole 220x replaced 'and-sub-bccm' by 'bcpl' ('%1').
+} if operandsLitOrSym(%1), operandsLiteral(%3), immdInRange(0 7 'singleSetBit' %3 8 %5), immdInRange(0 0 '-' %4 %5 %6), notUsed('a' 'n' 'z')
 
 replace restart {
 	ld	a, %1
-	and	a, #0x7f
+	or	a, #0x80
 	ld	%1, a
 } by {
-	bres	%2, #7
-	; peephole 19-7 replaced and by bres.
-} if notUsed('a'), operandsLiteral(%1), immdInRange(0 65535 '+' 0 %1 %2)
+	rlc	%1
+	scf
+	rrc	%1
+	; peephole 17 set msb in carry instead of a.
+} if notUsed('a'), notSame(%1 'xl' 'xh' 'yl' 'yh'), notUsed('c'), notVolatile(%1)
 
 replace restart {
 	ldw	%1, #%2
 	ld	a, (%1)
-	xor	a, #0x01
+	cpl	a
+	and	a, #%3
+	push	a
+	ld	a, (%1)
+	and	a, #%4
+	or	a, (1, sp)
 	ld	(%1), a
+	pop	a
 } by {
-	bcpl	%2, #0
-	; peephole 20-0 replaced or by bcpl.
-} if notUsed(%1), notUsed('a')
-
-replace restart {
 	ldw	%1, #%2
 	ld	a, (%1)
-	xor	a, #0x02
+	xor	a, #%3
 	ld	(%1), a
+	; peephole 300a replaced 'cpl-and-and-or' by 'xor' v1.
+} if operandsLiteral(%3 %4), immdInRange(0xFF 0xFF '^' %3 %4 %5)
+  
+replace restart {
+	ld	a, (%2, sp)
+	ldw	%1, sp
+	addw	%1, #%5
+	cpl	a
+	and	a, #%3
+	push	a
+	ld	a, (%1)
+	and	a, #%4
+	or	a, (1, sp)
+	ld	(%1), a
+	pop	a
 } by {
-	bcpl	%2, #1
-	; peephole 20-1 replaced or by bcpl.
-} if notUsed(%1), notUsed('a')
+	ldw	%1, sp
+	addw	%1, #%5
+	ld	a, (%2, sp)
+	xor	a, #%3
+	ld	(%2, sp), a
+	; peephole 300b replaced 'cpl-and-and-or' by 'xor' v2, with addw.
+} if operandsLiteral(%3 %4 %2 %5), immdInRange(0 0 '^' %2 %5 %8), immdInRange(0xFF 0xFF '^' %3 %4 %9)
 
 replace restart {
-	ldw	%1, #%2
+	ld	a, (%2, sp)
+	ldw	%1, sp
+	incw	%1
+	cpl	a
+	and	a, #%3
+	push	a
 	ld	a, (%1)
-	xor	a, #0x04
+	and	a, #%4
+	or	a, (1, sp)
 	ld	(%1), a
+	pop	a
 } by {
-	bcpl	%2, #2
-	; peephole 20-2 replaced or by bcpl.
-} if notUsed(%1), notUsed('a')
+	ldw	%1, sp
+	incw	%1
+	ld	a, (%2, sp)
+	xor	a, #%3
+	ld	(%2, sp), a
+	; peephole 300c replaced 'cpl-and-and-or' by 'xor' v3, with incw.
+} if operandsLiteral(%3 %4 %2), immdInRange(0 0 '^' %2 1 %8), immdInRange(0xFF 0xFF '^' %3 %4 %9)
 
 replace restart {
-	ldw	%1, #%2
+	ld	a, (%2, sp)
+	ldw	%1, sp
+	incw	%1
+	incw	%1
+	cpl	a
+	and	a, #%3
+	push	a
 	ld	a, (%1)
-	xor	a, #0x08
+	and	a, #%4
+	or	a, (1, sp)
 	ld	(%1), a
+	pop	a
 } by {
-	bcpl	%2, #3
-	; peephole 20-3 replaced or by bcpl.
-} if notUsed(%1), notUsed('a')
+	ldw	%1, sp
+	incw	%1
+	incw	%1
+	ld	a, (%2, sp)
+	xor	a, #%3
+	ld	(%2, sp), a
+	; peephole 300d replaced 'cpl-and-and-or' by 'xor' v4, with 2 incw.
+} if operandsLiteral(%3 %4 %2), immdInRange(0 0 '^' %2 2 %8), immdInRange(0xFF 0xFF '^' %3 %4 %9)
 
+// OR, XOR
 replace restart {
 	ldw	%1, #%2
 	ld	a, (%1)
-	xor	a, #0x10
+	and	a, #%3
+	%10	a, #%5
+	push	a
+	ld	a, (%1)
+	and	a, #%4
+	or	a, (1, sp)
 	ld	(%1), a
+	pop	a
 } by {
-	bcpl	%2, #4
-	; peephole 20-4 replaced or by bcpl.
-} if notUsed(%1), notUsed('a')
-
-replace restart {
 	ldw	%1, #%2
 	ld	a, (%1)
-	xor	a, #0x20
+	%10	a, #%5
 	ld	(%1), a
-} by {
-	bcpl	%2, #5
-	; peephole 20-5 replaced or by bcpl.
-} if notUsed(%1), notUsed('a')
+	; peephole 310 replaced 'and-%10-and-or' by '%10'.
+} if same(%10 'or' 'xor'), operandsLiteral(%3 %4 %5), immdInRange(0xFF 0xFF '^' %3 %4 %6), immdInRange(0 255 '&' %3 %5 %7), immdInRange(0 0 '^' %5 %7 %8)
+
 
+// COMBINED ANDS
 replace restart {
 	ldw	%1, #%2
 	ld	a, (%1)
-	xor	a, #0x40
+	and	a, #%3
+	push	a
+	ld	a, (%1)
+	and	a, #%4
+	or	a, (1, sp)
 	ld	(%1), a
+	pop	a
 } by {
-	bcpl	%2, #6
-	; peephole 20-6 replaced or by bcpl.
-} if notUsed(%1), notUsed('a')
-
-replace restart {
 	ldw	%1, #%2
 	ld	a, (%1)
-	xor	a, #0x80
+	and	a, #%6
 	ld	(%1), a
-} by {
-	bcpl	%2, #7
-	; peephole 20-7 replaced or by bcpl.
-} if notUsed(%1), notUsed('a')
+	; peephole 320 replaced 'and-and-or' by 'combined and'.
+} if operandsLiteral(%3 %4), immdInRange(0 255 '|' %3 %4 %6)
 
-replace restart {
-	ld	a, %1
-	xor	a, #0x01
-	ld	%1, a
-} by {
-	bcpl	%2, #0
-	; peephole 21-0 replaced or by bcpl.
-} if notUsed('a'), operandsLiteral(%1), immdInRange(0 65535 '+' 0 %1 %2)
-
-replace restart {
-	ld	a, %1
-	xor	a, #0x02
-	ld	%1, a
-} by {
-	bcpl	%2, #1
-	; peephole 21-1 replaced or by bcpl.
-} if notUsed('a'), operandsLiteral(%1), immdInRange(0 65535 '+' 0 %1 %2)
 
+// XOR, OR, AND convert to direct load
 replace restart {
-	ld	a, %1
-	xor	a, #0x04
-	ld	%1, a
-} by {
-	bcpl	%2, #2
-	; peephole 21-2 replaced or by bcpl.
-} if notUsed('a'), operandsLiteral(%1), immdInRange(0 65535 '+' 0 %1 %2)
-
-replace restart {
-	ld	a, %1
-	xor	a, #0x08
-	ld	%1, a
-} by {
-	bcpl	%2, #3
-	; peephole 21-3 replaced or by bcpl.
-} if notUsed('a'), operandsLiteral(%1), immdInRange(0 65535 '+' 0 %1 %2)
-
-replace restart {
-	ld	a, %1
-	xor	a, #0x10
-	ld	%1, a
+	ldw	%1, #%2
+	ld	a, (%1)
+	%4	a, #%3
+	ld	(%1), a
 } by {
-	bcpl	%2, #4
-	; peephole 21-4 replaced or by bcpl.
-} if notUsed('a'), operandsLiteral(%1), immdInRange(0 65535 '+' 0 %1, %2)
+	ld	a, %10
+	%4	a, #%3
+	ld	%10, a
+	; peephole 330x replaced 'ldw-ld-%4-ld' by 'ld-%4-ld direct' ('%2' -> '%10').
+} if same(%4 'xor' 'or' 'and'), notUsed(%1), removeParentheses(%2 %10)
 
+// XOR, OR, AND - stack version
 replace restart {
-	ld	a, %1
-	xor	a, #0x20
-	ld	%1, a
+	ldw	%1, sp
+	addw	%1, #%2
+	ld	a, (%1)
+	%4	a, #%3
+	ld	(%1), a
 } by {
-	bcpl	%2, #5
-	; peephole 21-5 replaced or by bcpl.
-} if notUsed('a'), operandsLiteral(%1), immdInRange(0 65535 '+' 0 %1 %2)
+	ld	a, (%2, sp)
+	%4	a, #%3
+	ld	(%2, sp), a
+	; peephole 330c replaced 'ldw-addw-ld-%4-ld' by 'ld-%4-ld sp indexed'.
+} if same(%4 'xor' 'or' 'and'), operandsLiteral(%2), immdInRange(0 0xFF '+' %2 0 %6), notUsed(%1)
 
+// Used when assigning a bitfield with more than 1 bit
 replace restart {
-	ld	a, %1
-	xor	a, #0x40
-	ld	%1, a
+	ldw	%1, #%2
+	ld	a, (%1)
+	%8	a, #%3
+	%9	a, #%4
+	ld	(%1), a
 } by {
-	bcpl	%2, #6
-	; peephole 21-6 replaced or by bcpl.
-} if notUsed('a'), operandsLiteral(%1), immdInRange(0 65535 '+' 0 %1 %2)
+	ld	a, %10
+	%8	a, #%3
+	%9	a, #%4
+	ld	%10, a
+	; peephole 340x exchanged 'ldw-ld-%8-%9-ld' by 'ld-%8-%9-ld direct' ('%2' -> '%10').
+} if same(%1 'x' 'y'), same(%8 'or' 'and'), same(%9 'or' 'and'), notUsed(%1), removeParentheses(%2 %10)
 
 replace restart {
-	ld	a, %1
-	xor	a, #0x80
-	ld	%1, a
+	rlc	a
+	xor	a, #0x01
 } by {
-	bcpl	%2, #7
-	; peephole 21-7 replaced or by bcpl.
-} if notUsed('a'), operandsLiteral(%1), immdInRange(0 65535 '+' 0 %1 %2)
+	ccf
+	; peephole 20a replaced xor by ccf-
+	rlc	a
+} if notUsed('c')
 
 replace restart {
 	clr	a
@@ -586,9 +823,9 @@
 
 replace restart {
 	clr	a
-	; peephole 22a removed redundant clr a.
 	or	a, %1
 } by {
+	; peephole 22a removed redundant clr a.
 	ld	a, %1
 }
 
@@ -621,60 +858,20 @@
 }
 
 replace restart {
-	and	a, %1
+	%3	a, %1
 	tnz	a
 } by {
-	and	a, %1
+	%3	a, %1
 	; peephole 23 removed redundant tnz.
-}
+} if same(%3 'and' 'or' 'xor' 'add' 'adc' 'sub' 'sbc')
 
 replace restart {
-	or	a, %1
-	tnz	a
+	%3	(%1, %2)
+	tnz	(%1, %2)
 } by {
-	or	a, %1
+	%3	(%1, %2)
 	; peephole 24 removed redundant tnz.
-}
-
-replace restart {
-	xor	a, %1
-	tnz	a
-} by {
-	xor	a, %1
-	; peephole 25 removed redundant tnz.
-}
-
-replace restart {
-	add	a, %1
-	tnz	a
-} by {
-	add	a, %1
-	; peephole 26 removed redundant tnz.
-}
-
-replace restart {
-	adc	a, %1
-	tnz	a
-} by {
-	adc	a, %1
-	; peephole 27 removed redundant tnz.
-}
-
-replace restart {
-	sub	a, %1
-	tnz	a
-} by {
-	sub	a, %1
-	; peephole 28 removed redundant tnz.
-}
-
-replace restart {
-	sbc	a, %1
-	tnz	a
-} by {
-	sbc	a, %1
-	; peephole 29 removed redundant tnz.
-}
+} if same(%3 'neg' 'cpl' 'inc' 'dec' 'sll' 'srl' 'sra' 'rlc' 'rrc')
 
 replace restart {
 	ld	a, %1
@@ -726,10 +923,10 @@
 
 replace restart {
 	ldw	(%1, sp), x
-	tnz	(%1, sp)
+	tnzw	(%1, sp)
 } by {
 	ldw	(%1, sp), x
-	; peephole 31c removed redundant tnz.
+	; peephole 31c removed redundant tnzw.
 }
 
 replace restart {
@@ -951,21 +1148,377 @@
 	; peephole 51 used inc to get #1 into a.
 } if notUsedFrom(%2 'a')
 
+// Unneeded sub-cp
+replace restart {
+	ld	a, %1
+	%2	a, #%3
+} by {
+	ld	a, %1
+	; peephole 600a removed unneeded %2 a, #%3
+} if same(%2 'cp' 'sub'), operandsLiteral(%3), immdInRange(0 0 '+' 0 %3 %4), notUsed('v' 'c')
+
+replace restart {
+	ld	%1, a
+	%2	a, #%3
+} by {
+	ld	%1, a
+	; peephole 600b removed unneeded %2 a, #%3
+} if same(%2 'cp' 'sub'), operandsLiteral(%3), immdInRange(0 0 '+' 0 %3 %4), notUsed('v' 'c')
+
+// Do operations directly on stack, leave 'a' as it was, load into 'a' may be removed by dead load optimizations
+replace restart {
+	ld	a, (%1, sp)
+	%5	a
+	ld	(%2, sp), a
+} by {
+	%5	(%1, sp)
+	ld	a, (%1, sp)
+	; peephole 610 optimized direct operation in stack (%5).
+}if same(%5 'swap' 'clr' 'dec' 'inc' 'neg' 'cpl'), immdInRange(0 0 '-' %1 %2 %7), notVolatile(%1)
+
+// Leave constant in 'a' before loop
+replace restart {
+%3:
+	ld	a,	%1
+	%4	a,	#%2
+	jr%5	%3
+} by {
+%3:
+	ld	a,	#%2
+%6:
+	%4	a,	%1
+	jr%5	%6
+	; peephole 620x moved 'ld' outside of loop: '%4-jr%5' ('%1').
+} if same(%4 'cp' 'bcp'), same(%5 'ne' 'eq'), operandsLitOrSym(%1), notUsed('a'), notUsedFrom(%3 'a'), newLabel(%6), labelRefCountChange(%3 -1)
+
+// Save 1 byte if 'a' is not used.
+// Same rule with literal value case is not needed because:
+//  ld followed by tnz is generated
+//  redundant tnz is removed by another rule
+replace restart {
+	tnz	_%1
+} by {
+	ld	a, _%1
+	; peephole 625a changed tnz by ld
+} if notUsed('a')
+
+// Change AND to BCP to enable other rules using bcp
+replace restart {
+	and	a, #%1
+} by {
+	bcp	a, #%1
+	; peephole 500 replaced 'and' by 'bcp'.
+} if operandsLiteral(%1), immdInRange(0 255 '+' 0 %1 %2), notUsed('a')
+
+// SRL - BCP, only using Z
+replace restart {
+	srl	a
+	bcp	a, #%1
+} by {
+	bcp	a, #%2
+	; peephole 510 replaced 'srl-bcp' (%1) by 'bcp' (%2).
+} if operandsLiteral(%1), immdInRange(2 255 '*' %1 2 %2), notUsed('a' 'n' 'c')
+
+// SWAP - BCP, only using Z
+replace restart {
+	swap	a
+	bcp	a, #%1
+} by {
+	bcp	a, #%2
+	; peephole 511 replaced 'swap-bcp' (%1) by 'bcp' (%2).
+} if operandsLiteral(%1), immdInRange(0 255 'swap' %1 8 %2), notUsed('a' 'n' 'c')
+
+// SRL - AND - CP to AND - CP
+replace restart {
+	srl	a
+	and	a, #%1
+	cp	a, #%2
+} by {
+	and	a, #%3
+	cp	a, #%4
+	; peephole 512 replaced 'srl-and-cp' (%1 %2) by 'and-cp' (%3 %4).
+} if operandsLiteral(%1 %2), immdInRange(2 255 '*' %1 2 %3), immdInRange(2 255 '*' %2 2 %4), notUsed('a')
+  
+// SWAP - AND - CP to AND - CP
+replace restart {
+	swap	a
+	and	a, #%1
+	cp	a, #%2
+} by {
+	and	a, #%3
+	cp	a, #%4
+	; peephole 513 replaced 'swap-and-cp' (%1 %2) by 'and-cp' (%3 %4).
+} if operandsLiteral(%1 %2), immdInRange(0 255 'swap' %1 8 %3), immdInRange(0 255 'swap' %2 8 %4), notUsed('a')
+
+// Direct load into a - should be one of the last ones
+replace restart {
+	ldw	%1, #%2
+	ld	a, (%1)
+} by {
+	ld	a, %10
+	; peephole 630x replaced 'ldw-ld' by 'ld direct' ('%2' -> '%10').
+} if same(%1 'x' 'y'), notUsed(%1), removeParentheses(%2 %10)
+
+// Use index register if already loaded with same address
+replace restart {
+	ldw	%1, #(%2)
+	ld	a, %2
+} by {
+	ldw	%1, #(%2)
+	ld	a, (%1)
+	; peephole 631 replaced 'ldw-ld' by 'ldw-ld' with index register (%1).
+}
+
+// Dead addw / incw
+replace restart {
+	addw	%1, %2
+} by {
+	; peephole 640 removed dead addw into %1 from %2.
+} if same(%1 'x' 'y'), notVolatile(%2), notUsed(%1), notUsed('n' 'z' 'c')
+
+replace restart {
+	addw	%1, (%2, sp)
+} by {
+	; peephole 641 removed dead addw into %1 from (%2, sp).
+} if notUsed(%1), notUsed('n' 'z' 'c')
+
+replace restart {
+	incw	%1
+} by {
+	; peephole 642 removed dead incw %1.
+} if notUsed(%1), notUsed('n' 'z')
+
+// Redundant jr
+replace restart {
+	jr%1	%2
+%2:
+} by {
+%2:
+	; peephole 650 removed redundant relative jump 'jr%1'.
+} if labelRefCountChange(%2 -1)
+
+// Swap optimizations x>>4 + x<<4
+replace restart {
+	ld	a, (%1, sp)
+	swap	a
+	and	a, #%3	
+	ld	xl, a
+	ld	a, (%1, sp)
+	swap	a
+	and	a, #%4
+	pushw	x
+	%5	a, (%2, sp)
+	popw	x
+} by {
+	ld	a, (%1, sp)
+	swap	a
+	; peephole 660c optimized swap (v3).
+} if same(%5 'or' 'add'), operandsLiteral(%3 %4), immdInRange(0xFF 0xFF '^' %3 %4 %6), immdInRange(2 2 '+' %2 0 %7), notUsed('x')
+
+// Optimizations of stack restore, less size but more cycles
+// No CC flags need to be checked because neither of these instructions modify them
+replace restart {
+	addw	sp, #%1
+} by {
+	pop	a
+	; peephole 670 replaced 'addw sp, #1' by 'pop a'
+} if optimizeFor('code-size'), operandsLiteral(%1), immdInRange(1 1 '+' 0 %1 %2), notUsed('a')
+
+replace restart {
+	addw	sp, #%1
+} by {
+	popw	x
+	; peephole 671 replaced 'addw sp, #2' by 'popw x'
+} if optimizeFor('code-size'), operandsLiteral(%1), immdInRange(2 2 '+' 0 %1 %2), notUsed('x')
+
+//----- Very seldom found optimizations
+
+// Remove operations in stack that will be immediately out of scope
+// 'ld(w)' followed by 'addw sp' and 'ret(tf)'
+// No need to check src operand of 'ld(w)', It must be 'a', 'x' or 'y' when loading into stack.
+// No need to check 're%3' for 'ret' and 'retf', those are the only instructions starting with 're'
+replace restart {
+	l%1	(%4, sp), %2
+	addw	sp, #%5
+	re%3
+} by {
+	; peephole 680 removed dead l%1 into stack variable %4 (%6).
+	addw	sp, #%5
+	re%3
+} if same(%1 'd' 'dw'), operandsLiteral(%5), immdInRange(-100000 0 '-' %4 %5 %6)
+
+// struct.bit == 1 AND-DEC-JRNE to BCP-JREQ
+replace restart {
+	and	a, #%1
+	dec	a
+	jrne	%2
+} by {
+	bcp	a, #%1
+	jreq	%2
+	; peephole j520 replaced 'and-dec-jrne' by 'bcp-jreq'.
+} if operandsLiteral(%1), immdInRange(1 1 '+' 0 %1 %2), notUsed('a' 'n' 'z' 'c'), notUsedFrom(%2 'a' 'n' 'z' 'c')
+
+// !(struct.bit == 1) AND-DEC-JREQ to BCP-JRNE
+replace restart {
+	and	a, #%1
+	dec	a
+	jreq	%2
+} by {
+	bcp	a, #%1
+	jrne	%2
+	; peephole j521 replaced 'and-dec-jreq' by 'bcp-jrne'.
+} if operandsLiteral(%1), immdInRange(1 1 '+' 0 %1 %2), notUsed('a' 'n' 'z' 'c'), notUsedFrom(%2 'a' 'n' 'z' 'c')
+
+// jreq to btjf
+replace restart {
+	ld	a, %1
+	bcp	a, #%2
+	jreq	%3
+} by {
+	btjf	%1, #%4, %3
+	; peephole j530x replaced 'ld-bcp-jreq' by 'btjf' ('%1').
+} if operandsLitOrSym(%1), operandsLiteral(%2), immdInRange(0 7 'singleSetBit' %2 8 %4), notUsed('a' 'n' 'z' 'c'), notUsedFrom(%3 'a' 'n' 'z' 'c')
+
+// jrne to btjt
+replace restart {
+	ld	a,	%1
+	bcp	a,	#%2
+	jrne	%3
+} by {
+	btjt	%1, #%4, %3
+	; peephole j531x replaced 'ld-bcp-jrne' by 'btjt' ('%1').
+} if operandsLitOrSym(%1), operandsLiteral(%2), immdInRange(0 7 'singleSetBit' %2 8 %4), notUsed('a' 'n' 'z' 'c'), notUsedFrom(%3 'a' 'n' 'z' 'c')
+
+
+// REPLACE LD + SRL + JRC WITH BTJT
+// 3/4 cycles, 6 bytes versus 2/3 cycles, 5 bytes
+replace restart {
+	ld	a, %1
+	srl	a
+	jrc	%2
+} by {
+	btjt	%1, #0, %2
+	; peephole j540x replaced 'ld-srl-jrc' by 'btjt' ('%1').
+} if operandsLitOrSym(%1), notUsed('a' 'n' 'z' 'c'), notUsedFrom(%2 'a' 'n' 'z' 'c')
+
+// REPLACE LD + SRL + JRNC WITH BTJF
+// 3/4 cycles, 6 bytes versus 2/3 cycles, 5 bytes  
+replace restart {
+	ld	a, %1
+	srl	a
+	jrnc	%2
+} by {
+	btjf	%1, #0, %2
+	; peephole j541x replaced 'ld-srl-jrnc' by 'btjf' ('%1').
+} if operandsLitOrSym(%1), notUsed('a' 'n' 'z' 'c'), notUsedFrom(%2 'a' 'n' 'z' 'c')
+
+// To check bit 7, jrpl and jrmi are as efficient as btxx (same size and cycles), and less conditions need to be checked.
+// jreq to jrpl
+replace restart {
+	ld	a, %1
+	bcp	a, #%2
+	jreq	%3
+} by {
+	ld	a, %1
+	jrpl	%3
+	; peephole j550 replaced 'ld-bcp-jreq' by 'ld-jrpl'.
+} if operandsLiteral(%2), immdInRange(0x80 0x80 '+' %2 0 %4), notUsed('n' 'z'), notUsedFrom(%3 'n' 'z')
+
+// jrne to jrmi
+replace restart {
+	ld	a, %1
+	bcp	a, #%2
+	jrne	%3
+} by {
+	ld	a, %1
+	jrmi	%3
+	; peephole j551 replaced 'ld-bcp-jrne' by 'ld-jrmi'.
+} if operandsLiteral(%2), immdInRange(0x80 0x80 '+' %2 0 %4), notUsed('n' 'z'), notUsedFrom(%3 'n' 'z')
+
+// SRL - AND - DEC to AND - CP
+replace restart {
+	srl	a
+	and	a, #%1
+	dec	a
+} by {
+	and	a, #%3
+	cp	a, #2
+	; peephole 515 replaced 'srl-and-dec' (%1) by 'and-cp' (%3 2).
+} if operandsLiteral(%1), immdInRange(2 255 '*' %1 2 %3), notUsed('a' 'c')
+  
+// SWAP - AND - DEC to AND - CP
+replace restart {
+	swap	a
+	and	a, #%1
+	dec	a
+} by {
+	and	a, #%3
+	cp	a, #16
+	; peephole 516 replaced 'swap-and-dec' (%1) by 'and-cp' (%3 16).
+} if operandsLiteral(%1), immdInRange(0 255 'swap' %1 8 %3), notUsed('a' 'c')
+
 replace {
 	jp	%5
 	ret
 } by {
 	jp	%5
-	; peephole 52 removed unused ret.
+	; peephole 52 removed unreachable ret.
 }
 
 replace {
+	jpf	%5
+	retf
+} by {
+	jpf	%5
+	; peephole 52a removed unreachable retf.
+}
+
+replace restart {
 	jp	%5
 	addw	sp, %1
-	ret
 } by {
 	jp	%5
-	; peephole 53 removed unused ret.
+	; peephole 53 removed unreachable addw.
+}
+
+replace restart {
+	jpf	%5
+	addw	sp, %1
+} by {
+	jpf	%5
+	; peephole 53a removed unreachable addw.
+}
+
+replace restart {
+	jp	%5
+	popw	%1
+} by {
+	jp	%5
+	; peephole 53b removed unreachable popw.
+}
+
+replace restart {
+	jpf	%5
+	popw	%1
+} by {
+	jpf	%5
+	; peephole 53c removed unreachable popw.
+}
+
+replace restart {
+	jp	%5
+	ldw	%1, (%2, sp)
+} by {
+	jp	%5
+	; peephole 54 removed unreachable ldw.
+}
+
+replace restart {
+	jp	%5
+	jp	(%1)
+} by {
+	jp	%5
+	; peephole 55 removed unreachable jp (%1).
 }
 
 replace restart {
@@ -1152,8 +1705,8 @@
 	jrne	%2
 %1:
 } by {
-    jrne	%2
-    ; peephole j7-eq-ne replaced jreq-jrne by jrne
+	jrne	%2
+	; peephole j7-eq-ne replaced jreq-jrne by jrne
 %1:	
 } if labelRefCountChange(%1 -1)
 
@@ -1162,8 +1715,8 @@
 	jreq	%2
 %1:
 } by {
-    jreq	%2
-    ; peephole j7-ne-eq replaced jrne-jreq by jreq
+	jreq	%2
+	; peephole j7-ne-eq replaced jrne-jreq by jreq
 %1:	
 } if labelRefCountChange(%1 -1)
 
@@ -1390,24 +1943,28 @@
 	; peephole j32 removed load by inverting jump condition.
 } if notUsedFrom(%3 'x')
 
-// Barrier, since notUsed() is better at dealing with ret than with jp to unknown location.
-barrier
-
 replace restart {
-	call	%1
-	ret
-} by {
-	jp	%1
-	; peephole j31 replaced call at end of function by jump (tail call optimization).
-}
+	btjt	%1, %2, %3
+	jra	%4
+%3:
+} by {
+	btjf	%1, %2, %4
+	; peephole j33 removed jra by using inverse bit-test-jump logic
+%3:
+} if labelRefCountChange(%3 -1)
+
+replace restart {
+	btjf	%1, %2, %3
+	jra	%4
+%3:
+} by {
+	btjt	%1, %2, %4
+	; peephole j34 removed jra by using inverse bit-test-jump logic
+%3:
+} if labelRefCountChange(%3 -1)
 
-replace restart {
-	callf	%1
-	retf
-} by {
-	jpf	%1
-	; peephole j31a replaced call at end of function by jump (tail call optimization).
-}
+// Barrier, since notUsed() is better at dealing with ret than with jp to unknown location.
+barrier
 
 replace restart {
 	ld	xl, a
@@ -1514,7 +2071,7 @@
 	%5:
 } if labelRefCountChange(%5 -1)
 
-// We don't have an explicit instruction to jump over 2 bytes. But when flags are not used, we can use cp a, longmen instead.
+// We don't have an explicit instruction to jump over 2 bytes. But when flags are not used, we can use cp/bcp a, longmen instead.
 
 // Jumping over ld a, #0xmm bcp does a read from a memory location at 0xa6mm - which for all current STM8 is in Flash or unused. If a future STM8 places memory-mapped I/O there, we're in trouble.
 replace {
@@ -1599,7 +2156,7 @@
 %5:
 } by {
 	.byte 0xbc
-	; peephole jrf11 used ldf opcode to jump over 3-byte instruction.
+	; peephole jrf11 used ldf opcode to jump over 3-byte instructions.
 %1:
 	clrw	x
 	ldw	(%2, sp), x
diff -Nru sdcc-4.0.0+dfsg/src/stm8/ralloc2.cc sdcc-4.2.0+dfsg/src/stm8/ralloc2.cc
--- sdcc-4.0.0+dfsg/src/stm8/ralloc2.cc	2019-12-29 10:16:46.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/stm8/ralloc2.cc	2021-09-20 12:21:15.000000000 +0000
@@ -242,56 +242,31 @@
 template 
 static bool operand_sane(const operand *o, const assignment &a, unsigned short int i, const G_t &G, const I_t &I)
 {
-#if 0
-  int v, byteregs[8];   // Todo: Change this when sdcc supports variables larger than 8 bytes.
-  unsigned short int size;
-
-  if(!o || !IS_SYMOP(o))
+  // stm8 code generation is very flexible, and can handle nearly anything (including variables where some bytes are spilt, while others are not).
+  // The only thing it can't handle is variables where some bytes are rematerialized, while others are not.
+  if(!o || !IS_SYMOP(o) || !OP_SYMBOL_CONST(o)->remat)
     return(true);
- 
+
   operand_map_t::const_iterator oi, oi_end;
   boost::tie(oi, oi_end) = G[i].operands.equal_range(OP_SYMBOL_CONST(o)->key);
   
   if(oi == oi_end)
     return(true);
   
-  // Ensure: Fully in registers or fully in mem.
-  if(a.local.find(oi->second) != a.local.end())
+  // In registers.
+  if(std::binary_search(a.local.begin(), a.local.end(), oi->second))
     {
       while(++oi != oi_end)
-        if(a.local.find(oi->second) == a.local.end())
+        if(!std::binary_search(a.local.begin(), a.local.end(), oi->second))
           return(false);
     }
   else
     {
        while(++oi != oi_end)
-        if(a.local.find(oi->second) != a.local.end())
+        if(std::binary_search(a.local.begin(), a.local.end(), oi->second))
           return(false);
     }
 
-  boost::tie(oi, oi_end) = G[i].operands.equal_range(OP_SYMBOL_CONST(o)->key);
-  v = oi->second;
-  byteregs[I[v].byte] = a.global[v];
-  size = 1;
-  while(++oi != oi_end)
-    {
-      v = oi->second;
-      byteregs[I[v].byte] = a.global[v];
-      size++;
-    }
-
-  if (byteregs[0] == -1)
-    return(true);
-
-  // Ensure: 8 bit only in A, 16 bit only in X or Y.
-  if (size == 1)
-    return(byteregs[0] == A_IDX);
-  if (size == 2)
-    return(byteregs[0] == XL_IDX && byteregs[1] == XH_IDX || byteregs[0] == YL_IDX && byteregs[1] == YH_IDX);
-  if (size > 2)
-    return(false);
-#endif
-
   return(true);
 }
 
@@ -373,9 +348,12 @@
     case NE_OP:
     case AND_OP:
     case OR_OP:
+    case RLC:
+    case RRC:
     case GETABIT:
     case GETBYTE:
     case GETWORD:
+    case SWAP:
     case LEFT_OP:
     case RIGHT_OP:
     case GET_VALUE_AT_ADDRESS:
@@ -385,12 +363,11 @@
     case ADDRESS_OF:
     case JUMPTABLE:
     case CAST:
-    /*case RECEIVE:
-    case SEND:*/
+    case RECEIVE:
+    case SEND:
     case DUMMY_READ_VOLATILE:
-    /*case CRITICAL:
-    case ENDCRITICAL:*/
-    case SWAP:
+    case CRITICAL:
+    case ENDCRITICAL:
       assign_operands_for_cost(a, i, G, I);
       set_surviving_regs(a, i, G, I);
       c = drySTM8iCode(ic);
diff -Nru sdcc-4.0.0+dfsg/src/stm8/ralloc.c sdcc-4.2.0+dfsg/src/stm8/ralloc.c
--- sdcc-4.0.0+dfsg/src/stm8/ralloc.c	2019-10-24 09:50:53.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/stm8/ralloc.c	2021-11-10 13:01:59.000000000 +0000
@@ -3,8 +3,6 @@
 
 #include "dbuf_string.h"
 
-extern void genSTM08Code (iCode *);
-
 reg_info stm8_regs[] =
 {
   {REG_GPR, A_IDX,   "a"},
@@ -281,7 +279,7 @@
 
   if (!IS_ITEMP (IC_RIGHT (ic)) || OP_SYMBOL (IC_RIGHT (ic))->isind || OP_LIVETO (IC_RIGHT (ic)) > ic->seq)
     return 0;
-  
+
   /* Avoid having multiple named address spaces in one iCode. */
   if (IS_SYMOP (IC_RESULT (ic)) && SPEC_ADDRSPACE (OP_SYMBOL (IC_RESULT (ic))->etype))
     return 0;
@@ -363,14 +361,24 @@
         }
     }
 
-  /* For now eliminate 8-bit temporary variables only.
+  // Can do wide shift by 1 in place.
+  if ((dic->op == LEFT_OP || dic->op == RIGHT_OP) && IS_OP_LITERAL (IC_RIGHT (dic)) && operandLitValue (IC_RIGHT (dic))  == 1 &&
+    IS_SYMOP (IC_LEFT (dic)) && IS_SYMOP (IC_RESULT (ic)) && OP_SYMBOL (IC_LEFT (dic)) == OP_SYMBOL (IC_RESULT (ic)))
+    ;
+  // Optimize out short-lived extra temporary.
+  else if ((dic->op == CAST ||
+    dic->op == UNARYMINUS || dic->op == '+' || dic->op == '-' || dic->op == '*' || dic->op == '%' ||
+    dic->op == '~' || dic->op == '^' || dic->op == '|' || dic->op == BITWISEAND ||
+    dic->op == LEFT_OP || dic->op == RIGHT_OP ||
+    dic->op == RRC || dic->op == RLC || dic->op == SWAP || dic->op == GETABIT) &&
+    dic->next == ic && IS_ITEMP (IC_RESULT (ic)))
+    ;
+  /* Otherwise, for now eliminate 8-bit temporary variables only.
      The STM8 instructions operating directly on memory
      operands are 8-bit, so the most benefit is in 8-bit
      operations. On the other hand, supporting wider
-     operations well in codegen is also more effort. */
-  if (bitsForType (operandType (IC_RESULT (dic))) > 8 &&
-    !((dic->op == LEFT_OP || dic->op == RIGHT_OP) && IS_OP_LITERAL (IC_RIGHT (dic)) && operandLitValue (IC_RIGHT (dic))  == 1 && // Can do wide shift by 1 in place.
-      IS_SYMOP (IC_LEFT (dic)) && IS_SYMOP (IC_RESULT (ic)) && OP_SYMBOL (IC_LEFT (dic)) == OP_SYMBOL (IC_RESULT (ic))))
+     operations well in codegen is also more effort. */ 
+  else if (bitsForType (operandType (IC_RESULT (dic))) > 8)
     return 0;
 
   /* if the result is on stack or iaccess then it must be
@@ -566,6 +574,21 @@
             }
         }
 
+      /* if this is a +/- operation with a rematerializable
+         then mark this as rematerializable as well */
+      if ((ic->op == '+' || ic->op == '-') &&
+          IS_SYMOP (IC_LEFT (ic)) &&
+          IS_ITEMP (IC_RESULT (ic)) &&
+          IS_OP_LITERAL (IC_RIGHT (ic)) &&
+          OP_SYMBOL (IC_LEFT (ic))->remat &&
+          (!IS_SYMOP (IC_RIGHT (ic)) || !IS_CAST_ICODE (OP_SYMBOL (IC_RIGHT (ic))->rematiCode)) &&
+          bitVectnBitsOn (OP_DEFS (IC_RESULT (ic))) == 1)
+        {
+          OP_SYMBOL (IC_RESULT (ic))->remat = 1;
+          OP_SYMBOL (IC_RESULT (ic))->rematiCode = ic;
+          OP_SYMBOL (IC_RESULT (ic))->usl.spillLoc = NULL;
+        }
+
       /* In some cases redundant moves can be eliminated */
       if (ic->op == GET_VALUE_AT_ADDRESS || ic->op == SET_VALUE_AT_ADDRESS ||
         ic->op == IFX && operandSize (IC_COND (ic)) == 1 ||
@@ -748,8 +771,6 @@
     }
 }
 
-void stm8_init_asmops (void);
-
 /*-----------------------------------------------------------------*/
 /* assignRegisters - assigns registers to each live range as need  */
 /*-----------------------------------------------------------------*/
@@ -760,8 +781,6 @@
   int count = ebbi->count;
   iCode *ic;
 
-  stm8_init_asmops();
-
   transformPointerSet (ebbs, count);
 
   /* change assignments this will remove some
diff -Nru sdcc-4.0.0+dfsg/src/z80/gen.c sdcc-4.2.0+dfsg/src/z80/gen.c
--- sdcc-4.0.0+dfsg/src/z80/gen.c	2020-01-22 11:31:27.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/z80/gen.c	2022-02-21 07:19:35.000000000 +0000
@@ -1,10 +1,10 @@
 /*-------------------------------------------------------------------------
-  gen.c - code generator for Z80 / Z180 / GBZ80.
+  gen.c - code generator for Z80 and related.
 
   Copyright (C) 1998, Sandeep Dutta . sandeep.dutta@usa.net
   Copyright (C) 1999, Jean-Louis VERN.jlvern@writeme.com
   Copyright (C) 2000, Michael Hope 
-  Copyright (C) 2011-2018, Philipp Klaus Krause pkk@spth.de, philipp@informatik.uni-frankfurt.de)
+  Copyright (C) 2011-2021, Philipp Klaus Krause pkk@spth.de, philipp@informatik.uni-frankfurt.de, krauseph@informatik.uni-freiburg.de)
 
   This program is free software; you can redistribute it and/or modify it
   under the terms of the GNU General Public License as published by the
@@ -55,6 +55,8 @@
   DISABLE_DEBUG = 0
 };
 
+#define UNIMPLEMENTED do {wassertl (regalloc_dry_run, "Unimplemented"); cost (500, 500);} while(0)
+
 // #define DEBUG_DRY_COST
 
 extern struct dbuf_s *codeOutBuf;
@@ -135,10 +137,12 @@
   A_RLA,
   A_RLC,
   A_RLCA,
+  A_RLD,
   A_RR,
   A_RRA,
   A_RRC,
   A_RRCA,
+  A_RRD,
   A_SBC,
   A_SLA,
   A_SRA,
@@ -164,10 +168,12 @@
   "rla",
   "rlc",
   "rlca",
+  "rld",
   "rr",
   "rra",
   "rrc",
   "rrca",
+  "rrd",
   "sbc",
   "sla",
   "sra",
@@ -187,7 +193,8 @@
   struct
   {
     AOP_TYPE last_type;
-    const char *base;
+    const char *base;   // For addresses
+    unsigned int value; // For AOP_LIT
     int offset;
   } pairs[NUM_PAIRS];
   struct
@@ -242,7 +249,7 @@
 
 static const char *aopGet (asmop *aop, int offset, bool bit16);
 
-static struct asmop asmop_a, asmop_b, asmop_c, asmop_d, asmop_e, asmop_h, asmop_l, asmop_iyh, asmop_iyl, asmop_zero, asmop_one, asmop_return;
+static struct asmop asmop_a, asmop_b, asmop_c, asmop_d, asmop_e, asmop_h, asmop_l, asmop_iyh, asmop_iyl, asmop_hl, asmop_de, asmop_bc, asmop_iy, asmop_dehl, asmop_hlde, asmop_hlbc, asmop_debc, asmop_zero, asmop_one, asmop_mone;
 static struct asmop *const ASMOP_A = &asmop_a;
 static struct asmop *const ASMOP_B = &asmop_b;
 static struct asmop *const ASMOP_C = &asmop_c;
@@ -252,69 +259,57 @@
 static struct asmop *const ASMOP_L = &asmop_l;
 static struct asmop *const ASMOP_IYH = &asmop_iyh;
 static struct asmop *const ASMOP_IYL = &asmop_iyl;
+static struct asmop *const ASMOP_HL = &asmop_hl;
+static struct asmop *const ASMOP_DE = &asmop_de;
+static struct asmop *const ASMOP_BC = &asmop_bc;
+static struct asmop *const ASMOP_IY = &asmop_iy;
+static struct asmop *const ASMOP_DEHL = &asmop_dehl;
+static struct asmop *const ASMOP_HLDE = &asmop_hlde;
+static struct asmop *const ASMOP_HLBC = &asmop_hlbc;
+static struct asmop *const ASMOP_DEBC = &asmop_debc;
 static struct asmop *const ASMOP_ZERO = &asmop_zero;
 static struct asmop *const ASMOP_ONE = &asmop_one;
-static struct asmop *const ASMOP_RETURN = &asmop_return;
+static struct asmop *const ASMOP_MONE = &asmop_mone;
 
 static asmop *asmopregs[] = { &asmop_a, &asmop_c, &asmop_b, &asmop_e, &asmop_d, &asmop_l, &asmop_h, &asmop_iyl, &asmop_iyh };
 
+// Init aop as a an asmop for data in registers, as given by the -1-terminated array regidx.
+static void
+z80_init_reg_asmop(asmop *aop, const signed char *regidx)
+{
+  aop->type = AOP_REG;
+  aop->size = 0;
+  memset (aop->regs, -1, sizeof(aop->regs));
+  
+  for(int i = 0; regidx[i] >= 0; i++)
+    {
+      aop->aopu.aop_reg[i] = regsZ80 + regidx[i];
+      aop->regs[regidx[i]] = i;
+      aop->size++;
+    }
+}
+
 void
 z80_init_asmops (void)
 {
-  asmop_a.type = AOP_REG;
-  asmop_a.size = 1;
-  asmop_a.aopu.aop_reg[0] = regsZ80 + A_IDX;
-  memset (asmop_a.regs, -1, 9);
-  asmop_a.regs[A_IDX] = 0;
-  asmop_b.type = AOP_REG;
-  asmop_b.size = 1;
-  asmop_b.aopu.aop_reg[0] = regsZ80 + B_IDX;
-  memset (asmop_b.regs, -1, 9);
-  asmop_b.regs[B_IDX] = 0;
-  asmop_c.type = AOP_REG;
-  asmop_c.size = 1;
-  asmop_c.aopu.aop_reg[0] = regsZ80 + C_IDX;
-  memset (asmop_c.regs, -1, 9);
-  asmop_c.regs[C_IDX] = 0;
-  asmop_d.type = AOP_REG;
-  asmop_d.size = 1;
-  asmop_d.aopu.aop_reg[0] = regsZ80 + D_IDX;
-  memset (asmop_d.regs, -1, 9);
-  asmop_d.regs[D_IDX] = 0;
-  asmop_e.type = AOP_REG;
-  asmop_e.size = 1;
-  asmop_e.aopu.aop_reg[0] = regsZ80 + E_IDX;
-  memset (asmop_e.regs, -1, 9);
-  asmop_e.regs[E_IDX] = 0;
-  asmop_h.type = AOP_REG;
-  asmop_h.size = 1;
-  asmop_h.aopu.aop_reg[0] = regsZ80 + H_IDX;
-  memset (asmop_h.regs, -1, 9);
-  asmop_h.regs[H_IDX] = 0;
-  asmop_l.type = AOP_REG;
-  asmop_l.size = 1;
-  asmop_l.aopu.aop_reg[0] = regsZ80 + L_IDX;
-  memset (asmop_l.regs, -1, 9);
-  asmop_l.regs[L_IDX] = 0;
-  asmop_iyh.type = AOP_REG;
-  asmop_iyh.size = 1;
-  asmop_iyh.aopu.aop_reg[0] = regsZ80 + IYH_IDX;
-  memset (asmop_iyh.regs, -1, 9);
-  asmop_iyh.regs[IYH_IDX] = 0;
-  asmop_iyl.type = AOP_REG;
-  asmop_iyl.size = 1;
-  asmop_iyl.aopu.aop_reg[0] = regsZ80 + IYL_IDX;
-  memset (asmop_iyl.regs, -1, 9);
-  asmop_iyl.regs[IYL_IDX] = 0;
-
-  /*asmop_hl.type = AOP_REG;
-  asmop_hl.size = 2;
-  asmop_hl.aopu.aop_reg[0] = regsZ80 + L_IDX;
-  asmop_hl.aopu.aop_reg[1] = regsZ80 + H_IDX;
-  memset (asmop_hl.regs, -1, 9);
-  asmop_hl.regs[L_IDX] = 0;
-  asmop_hl.regs[H_IDX] = 1;*/
-
+  z80_init_reg_asmop(&asmop_a, (const signed char[]){A_IDX, -1});
+  z80_init_reg_asmop(&asmop_b, (const signed char[]){B_IDX, -1});
+  z80_init_reg_asmop(&asmop_c, (const signed char[]){C_IDX, -1});
+  z80_init_reg_asmop(&asmop_d, (const signed char[]){D_IDX, -1});
+  z80_init_reg_asmop(&asmop_e, (const signed char[]){E_IDX, -1});
+  z80_init_reg_asmop(&asmop_h, (const signed char[]){H_IDX, -1});
+  z80_init_reg_asmop(&asmop_l, (const signed char[]){L_IDX, -1});
+  z80_init_reg_asmop(&asmop_iyh, (const signed char[]){IYH_IDX, -1});
+  z80_init_reg_asmop(&asmop_iyl, (const signed char[]){IYL_IDX, -1});
+  z80_init_reg_asmop(&asmop_bc, (const signed char[]){C_IDX, B_IDX, -1});
+  z80_init_reg_asmop(&asmop_de, (const signed char[]){E_IDX, D_IDX, -1});
+  z80_init_reg_asmop(&asmop_hl, (const signed char[]){L_IDX, H_IDX, -1});
+  z80_init_reg_asmop(&asmop_dehl, (const signed char[]){L_IDX, H_IDX, E_IDX, D_IDX, -1});
+  z80_init_reg_asmop(&asmop_hlde, (const signed char[]){E_IDX, D_IDX, L_IDX, H_IDX, -1});
+  z80_init_reg_asmop(&asmop_iy, (const signed char[]){IYL_IDX, IYH_IDX, -1});
+  z80_init_reg_asmop(&asmop_hlbc, (const signed char[]){C_IDX, B_IDX, L_IDX, H_IDX, -1});
+  z80_init_reg_asmop(&asmop_debc, (const signed char[]){C_IDX, B_IDX, E_IDX, D_IDX, -1});
+  
   asmop_zero.type = AOP_LIT;
   asmop_zero.aopu.aop_lit = constVal ("0");
   asmop_zero.size = 1;
@@ -325,46 +320,116 @@
   asmop_one.size = 1;
   memset (asmop_one.regs, -1, 9);
 
-  asmop_return.type = AOP_REG;
-  asmop_return.size = 4;
-  memset (asmop_return.regs, -1, 9);
-  if (IS_GB)
-    {
-      asmop_return.aopu.aop_reg[0] = regsZ80 + E_IDX;
-      asmop_return.regs[E_IDX] = 0;
-      asmop_return.aopu.aop_reg[1] = regsZ80 + D_IDX;
-      asmop_return.regs[D_IDX] = 1;
-      asmop_return.aopu.aop_reg[2] = regsZ80 + L_IDX;
-      asmop_return.regs[L_IDX] = 2;
-      asmop_return.aopu.aop_reg[3] = regsZ80 + H_IDX;
-      asmop_return.regs[H_IDX] = 2;
-    }
-  else
-    {
-      asmop_return.aopu.aop_reg[0] = regsZ80 + L_IDX;
-      asmop_return.regs[L_IDX] = 0;
-      asmop_return.aopu.aop_reg[1] = regsZ80 + H_IDX;
-      asmop_return.regs[H_IDX] = 1;
-      asmop_return.aopu.aop_reg[2] = regsZ80 + E_IDX;
-      asmop_return.regs[E_IDX] = 2;
-      asmop_return.aopu.aop_reg[3] = regsZ80 + D_IDX;
-      asmop_return.regs[D_IDX] = 3;
-    }
+  asmop_mone.type = AOP_LIT;
+  asmop_mone.aopu.aop_lit = constVal ("-1");
+  asmop_mone.size = 1;
+  memset (asmop_mone.regs, -1, 9);
 }
 
 static bool regalloc_dry_run;
-static unsigned int regalloc_dry_run_cost;
+static unsigned int regalloc_dry_run_cost; // Legacy: cost counted in bytes only (i.e. states have been ignored for corresponding instructions).
+static unsigned int regalloc_dry_run_cost_bytes;
+static unsigned int regalloc_dry_run_cost_states;
 
 static void
-cost(unsigned int bytes, unsigned int cycles)
+cost(unsigned int bytes, unsigned int states)
 {
-  regalloc_dry_run_cost += bytes;
+  regalloc_dry_run_cost_bytes += bytes;
+  regalloc_dry_run_cost_states += states;
 }
 
 static void
-cost2(unsigned int bytes, unsigned int cycles_z80, unsigned int cycles_z180, unsigned int cycles_r2k, unsigned int cycles_gbz80, unsigned int cycles_tlcs90, unsigned int cycles_ez80_z80)
+cost2(unsigned int bytes, unsigned int z80_states /* also z80n */, unsigned int z180_states, unsigned int r2k_clocks, unsigned int sm83_cycles, unsigned int tlcs90_states, unsigned int ez80_z80_cycles)
+{
+  regalloc_dry_run_cost_bytes += bytes;
+  if (IS_Z80 || IS_Z80N)
+    regalloc_dry_run_cost_states += z80_states;
+  else if (IS_Z180)
+    regalloc_dry_run_cost_states += z180_states;
+  else if (IS_R2K || IS_R2KA || IS_R3KA)
+    regalloc_dry_run_cost_states += r2k_clocks;
+  else if (IS_SM83)
+    regalloc_dry_run_cost_states += sm83_cycles;
+  else if(IS_TLCS90)
+    regalloc_dry_run_cost_states += tlcs90_states;
+  else if(IS_EZ80_Z80)
+    regalloc_dry_run_cost_states += ez80_z80_cycles;
+  else
+    wassert (0);
+}
+
+/*-----------------------------------------------------------------*/
+/* isRegIdxPair - true, if specified index is register pair,       */
+/*                rIdx changed to index of lower register          */
+/*-----------------------------------------------------------------*/
+static bool
+isRegIdxPair (short *rIdx)
+{
+  switch (*rIdx)
+    {
+    case BC_IDX:
+      *rIdx = C_IDX;
+      break;
+    case DE_IDX:
+      *rIdx = E_IDX;
+      break;
+    case HL_IDX:
+      *rIdx = L_IDX;
+      break;
+    case IY_IDX:
+      *rIdx = IYL_IDX;
+      break;
+    default:
+      return false;
+    }
+  return true;
+}
+
+/*-----------------------------------------------------------------*/
+/* aopRegOffset - return register offset in the asmop              */
+/*-----------------------------------------------------------------*/
+static int
+aopRegOffset (const asmop *aop, short rIdx)
+{
+  if (rIdx < 0 || aop->type != AOP_REG)
+    return -1;
+
+  if (!isRegIdxPair (&rIdx))
+    return aop->regs[rIdx];
+
+  int offset = aop->regs[rIdx];
+  return (offset != -1 && aop->regs[rIdx+1] == offset+1) ? offset : -1;
+}
+
+/*-----------------------------------------------------------------*/
+/* aopUseReg - return true if register is in the asmop             */
+/*-----------------------------------------------------------------*/
+static inline bool
+aopRegUsed (const asmop *aop, short rIdx)
+{
+  if (aop->type != AOP_REG)
+    return false;
+
+  if (!isRegIdxPair (&rIdx))
+    return aop->regs[rIdx];
+
+  return aop->regs[rIdx] != -1 || aop->regs[rIdx+1] != -1;
+}
+
+/*-----------------------------------------------------------------*/
+/* aopRegUsedRange - true if register is in specified position range [minPos;maxPos) */
+/*-----------------------------------------------------------------*/
+static inline bool
+aopRegUsedRange (const asmop *aop, short rIdx, int minPos, int maxPos)
 {
-  regalloc_dry_run_cost += bytes;
+  if (aop->type != AOP_REG)
+    return false;
+
+  if (!isRegIdxPair (&rIdx))
+    return aop->regs[rIdx] >= minPos && aop->regs[rIdx] < maxPos;
+
+  return (aop->regs[rIdx] >= minPos && aop->regs[rIdx] < maxPos) ||
+         (aop->regs[rIdx+1] >= minPos && aop->regs[rIdx+1] < maxPos);
 }
 
 /*-----------------------------------------------------------------*/
@@ -390,17 +455,17 @@
       val >>= 8;
 
       // Leading zeroes
-      if (aop->size <= offset && !b)
+      if (aop->size <= offset && !b && aop->type != AOP_LIT)
         continue;
 
       if (aop->type != AOP_LIT)
-        return (FALSE);
+        return (false);
 
       if (byteOfVal (aop->aopu.aop_lit, offset) != b)
-        return (FALSE);
+        return (false);
     }
 
-  return (TRUE);
+  return (true);
 }
 
 /*-----------------------------------------------------------------*/
@@ -409,22 +474,10 @@
 static inline bool
 aopInReg (const asmop *aop, int offset, short rIdx)
 {
-  if (!(aop->type == AOP_REG))
-    return (false);
-
   if (offset >= aop->size || offset < 0)
     return (false);
 
-  if (rIdx == IY_IDX)
-    return (aopInReg (aop, offset, IYL_IDX) && aopInReg (aop, offset + 1, IYH_IDX));
-  if (rIdx == BC_IDX)
-    return (aopInReg (aop, offset, C_IDX) && aopInReg (aop, offset + 1, B_IDX));
-  if (rIdx == DE_IDX)
-    return (aopInReg (aop, offset, E_IDX) && aopInReg (aop, offset + 1, D_IDX));
-  if (rIdx == HL_IDX)
-    return (aopInReg (aop, offset, L_IDX) && aopInReg (aop, offset + 1, H_IDX));
-
-  return (aop->aopu.aop_reg[offset]->rIdx == rIdx);
+  return aopRegOffset (aop, rIdx) == offset;
 }
 
 /*-----------------------------------------------------------------*/
@@ -442,6 +495,18 @@
   return (true);
 }
 
+static inline int
+fpOffset (int aop_stk)
+{
+  return aop_stk + (aop_stk > 0 ? _G.stack.param_offset : 0);
+}
+
+static int
+spOffset (int aop_stk)
+{
+  return fpOffset (aop_stk) + _G.stack.pushed + _G.stack.offset;
+}
+
 /* WARNING: This function is dangerous to use. It works literally:
    It will return true if ic the the last use of op, even if ic might
    be executed again, e.g. due to a loop. Most of the time you will want
@@ -470,10 +535,18 @@
   return FALSE;
 }
 
+static bool
+isRegDead (short rIdx, const iCode * ic)
+{
+  if (!isRegIdxPair (&rIdx))
+    return !bitVectBitValue (ic->rSurv, rIdx);
+  return !bitVectBitValue (ic->rSurv, rIdx) && !bitVectBitValue (ic->rSurv, rIdx+1);
+}
+
 static PAIR_ID
 _getTempPairId (void)
 {
-  if (IS_GB)
+  if (IS_SM83)
     {
       return PAIR_DE;
     }
@@ -510,22 +583,19 @@
 static bool
 isPairDead (PAIR_ID id, const iCode * ic)
 {
-  const bitVect *r = (!options.oldralloc ? ic->rSurv :
-                      (POINTER_SET (ic) ? ic->rMask :
-                       (bitVectCplAnd (bitVectCopy (ic->rMask), z80_rUmaskForOp (IC_RESULT (ic))))));
-
-  if (id == PAIR_DE)
-    return !(bitVectBitValue (r, D_IDX) || bitVectBitValue (r, E_IDX));
-  else if (id == PAIR_BC)
-    return !(bitVectBitValue (r, B_IDX) || bitVectBitValue (r, C_IDX));
-  else if (id == PAIR_HL)
-    return !(bitVectBitValue (r, H_IDX) || bitVectBitValue (r, L_IDX));
-  else if (id == PAIR_IY)
-    return !(bitVectBitValue (r, IYH_IDX) || bitVectBitValue (r, IYL_IDX));
-  else
+  switch (id)
     {
+    case PAIR_DE:
+      return isRegDead (D_IDX, ic) && isRegDead (E_IDX, ic);
+    case PAIR_BC:
+      return isRegDead (B_IDX, ic) && isRegDead (C_IDX, ic);
+    case PAIR_HL:
+      return isRegDead (H_IDX, ic) && isRegDead (L_IDX, ic);
+    case PAIR_IY:
+      return isRegDead (IYH_IDX, ic) && isRegDead (IYL_IDX, ic);
+    default:
       wassertl (0, "Only implemented for DE, BC, HL and IY");
-      return TRUE;
+      return FALSE;
     }
 }
 
@@ -536,7 +606,7 @@
     {
       return PAIR_BC;
     }
-  else if (!IS_GB && isPairDead (PAIR_DE, ic))
+  else if (!IS_SM83 && isPairDead (PAIR_DE, ic))
     {
       return PAIR_DE;
     }
@@ -553,7 +623,7 @@
     {
       return PAIR_BC;
     }
-  else if (!IS_GB && !isPairInUse (PAIR_DE, ic))
+  else if (!IS_SM83 && !isPairInUse (PAIR_DE, ic))
     {
       return PAIR_DE;
     }
@@ -664,7 +734,7 @@
 static PAIR_ID
 getPairId_o (const asmop *aop, int offset)
 {
-  if (offset + 2 <= aop->size)
+  if (offset >= 0 && offset + 2 <= aop->size)
     {
       if (aop->type == AOP_REG)
         {
@@ -717,20 +787,23 @@
 z80_emitDebuggerSymbol (const char *debugSym)
 {
   genLine.lineElement.isDebug = 1;
-  emit2 ("%s !equ .", debugSym);
+  emit2 ("%s !equ !here", debugSym);
   emit2 ("!global", debugSym);
   genLine.lineElement.isDebug = 0;
 }
 
 // Todo: Handle IY correctly.
 static unsigned char
-ld_cost (const asmop *op1, const asmop *op2)
+ld_cost (const asmop *op1, int offset1, const asmop *op2, int offset2)
 {
   AOP_TYPE op1type = op1->type;
   AOP_TYPE op2type = op2->type;
 
+  if (offset2 >= op2->size)
+    return(ld_cost(op1, offset1, ASMOP_ZERO, 0));
+
   /* Costs are symmetric */
-  if (op2type == AOP_REG || op2type == AOP_DUMMY)
+  if (op1type != AOP_REG && (op2type == AOP_REG || op2type == AOP_DUMMY))
     {
       const asmop *tmp = op1;
       op1 = op2;
@@ -746,6 +819,10 @@
       switch (op2type)
         {
         case AOP_REG:
+          // eZ80 ld r, ir / ld ir, r / ld ir, ir
+          if (op1->aopu.aop_reg[offset1]->rIdx == IYL_IDX || op1->aopu.aop_reg[offset1]->rIdx == IYH_IDX ||
+            op2->aopu.aop_reg[offset2]->rIdx == IYL_IDX || op2->aopu.aop_reg[offset2]->rIdx == IYH_IDX)
+            return (2);
         case AOP_DUMMY:
           return (1);
         case AOP_IMMD:
@@ -868,59 +945,125 @@
   return (8);                   // Fallback
 }
 
-static unsigned char
-op8_cost (const asmop * op2)
+static void
+op8_cost (const asmop *op, int offset)
 {
-  switch (op2->type)
+  switch (op->type)
     {
     case AOP_REG:
+      if (op->aopu.aop_reg[offset]->rIdx == IYL_IDX || op->aopu.aop_reg[offset]->rIdx == IYH_IDX) // eZ80
+        {
+          cost (2, 2);
+          return;
+        }
     case AOP_DUMMY:
-      return (1);
+      cost2 (1, 4, 4, 2, 4, 4, 1);
+      return;
     case AOP_IMMD:
     case AOP_LIT:
-      return (2);
+      cost2 (2, 7, 6, 4, 8, 4, 2);
+      return;
     case AOP_STK:
-      return (3);
+      if (!IS_SM83)
+        {
+          cost2 (3, 19, 15, 9, 0, 10, 4);
+          return;
+        }
+      cost (1, 8); // add hl, sp
     case AOP_HL:
-      return (4);
+      cost2 (3 + 1, 10 + 7, 9 + 6, 6 + 5, 12 + 8, 6 + 6, 3 + 2);
+      return;
     case AOP_IY:               /* 4 from ld iy, #... */
     case AOP_EXSTK:            /* 4 from ld iy, #... */
-      return (7);
+      cost2 (4 + 3, 12 + 19, 12 + 15, 8 + 9, 0 + 0, 6 + 10, 4 + 4);
+      return;
     case AOP_PAIRPTR:
-      if (op2->aopu.aop_pairId == PAIR_HL)
-        return (1);
-      if (op2->aopu.aop_pairId == PAIR_IY || op2->aopu.aop_pairId == PAIR_IX)
-        return (3);
+      if (op->aopu.aop_pairId == PAIR_HL)
+        cost2 (1, 7, 6, 5, 8, 6, 2);
+      if (op->aopu.aop_pairId == PAIR_IY || op->aopu.aop_pairId == PAIR_IX)
+        cost2 (3, 19, 15, 9, 0, 10, 4);
+      return;
     default:
-      printf ("op8_cost op2: %d\n", (int) (op2->type));
+      printf ("op8_cost op: %d\n", (int) (op->type));
       wassert (0);
     }
-  return (8);                   // Fallback
 }
 
-static unsigned char
-bit8_cost (const asmop * op1)
+static void
+incdec_cost (const asmop *op, int offset)
 {
-  switch (op1->type)
+  switch (op->type)
     {
     case AOP_REG:
+      if (op->aopu.aop_reg[offset]->rIdx == IYL_IDX || op->aopu.aop_reg[offset]->rIdx == IYH_IDX) // eZ80
+        {
+          cost (2, 2);
+          return;
+        }
     case AOP_DUMMY:
-      return (2);
+      cost2 (1, 4, 4, 2, 4, 2, 2);
+      return;
     case AOP_STK:
-      return (4);
+      if (!IS_SM83)
+        {
+          cost2 (3, 23, 18, 12, 0, 12, 6);
+          return;
+        }
+      cost (1, 8); // add hl, sp
     case AOP_HL:
-      return (5);
+      cost2 (3 + 1, 10 + 11, 9 + 10, 6 + 8, 12 + 12, 6 + 8, 3 + 5);
+      return;
     case AOP_IY:               /* 4 from ld iy, #... */
     case AOP_EXSTK:            /* 4 from ld iy, #... */
-      return (8);
+      cost2 (4 + 3, 14 + 23, 12 + 18, 8 + 12, 0 + 0, 6 + 12, 4 + 6);
+      return;
+    case AOP_PAIRPTR:
+      if (op->aopu.aop_pairId == PAIR_HL)
+        {
+          cost2 (1, 11, 10, 8, 12, 8, 5);
+          return;
+        }
+      if (op->aopu.aop_pairId == PAIR_IY || op->aopu.aop_pairId == PAIR_IX)
+        {
+          cost2 (3, 23, 18, 12, 0, 12, 6);
+          return;
+        }
     default:
-      printf ("bit8_cost op1: %d\n", (int) (op1->type));
+      printf ("op8_cost op: %d\n", (int) (op->type));
       wassert (0);
     }
-  return (8);                   //Fallback
 }
 
-static unsigned char
+static void
+bit8_cost (const asmop *op)
+{
+  switch (op->type)
+    {
+    case AOP_REG:
+    case AOP_DUMMY:
+      cost2 (2, 8, 7, 4, 8, 4, 2);
+      return;
+    case AOP_STK:
+      if (!IS_SM83)
+        {
+          cost2 (4, 23, 19, 13, 0, 12, 7);
+          return;
+        }
+      cost (1, 8); // add hl, sp
+    case AOP_HL:               /* 3 from ld hl, #... */
+      cost2 (3 + 2, 10 + 15, 9 + 13, 6 + 10, 12 + 16, 6 + 8, 3 + 5);
+      return;
+    case AOP_IY:               /* 4 from ld iy, #... */
+    case AOP_EXSTK:            /* 4 from ld iy, #... */
+      cost2 (4 + 4, 14 + 23, 12 + 19, 8 + 13, 0 + 0, 6 + 12, 4 + 7);
+      return;
+    default:
+      printf ("bit8_cost op: %d\n", (int) (op->type));
+      wassert (0);
+    }
+}
+
+static void
 emit3Cost (enum asminst inst, const asmop *op1, int offset1, const asmop *op2, int offset2)
 {
   if (op2 && offset2 >= op2->size)
@@ -933,11 +1076,18 @@
     case A_RLCA:
     case A_RRA:
     case A_RRCA:
-      return (1);
+      cost2 (1, 4, 3, 2, 4, 2, 1);
+      return;
     case A_NEG:
-      return(2);
+      cost2 (2, 8, 6, 4, 0, 2, 2);
+      return;
+    case A_RLD:
+    case A_RRD:
+      cost2 (2, 18, 16, 0, 0, 12, 5);
+      return;
     case A_LD:
-      return (ld_cost (op1, op2));
+      regalloc_dry_run_cost += ld_cost (op1, offset1, op2, offset2);
+      return;
     case A_ADD:
     case A_ADC:
     case A_AND:
@@ -946,10 +1096,12 @@
     case A_SBC:
     case A_SUB:
     case A_XOR:
-      return (op8_cost (op2));
+      op8_cost (op2, offset2);
+      return;
     case A_DEC:
     case A_INC:
-      return (op8_cost (op1));
+      incdec_cost (op1, offset1);
+      return;
     case A_RL:
     case A_RLC:
     case A_RR:
@@ -958,23 +1110,26 @@
     case A_SRA:
     case A_SRL:
     case A_SWAP:
-      return (bit8_cost (op1));
+      bit8_cost (op1);
+      return;
     default:
       wassertl (0, "Tried get cost for unknown instruction");
     }
-  return (0);
 }
 
 static void
 emit3_o (enum asminst inst, asmop *op1, int offset1, asmop *op2, int offset2)
 {
-  unsigned char cost;
+  unsigned int cost, bytecost, statecost;
+
+  emit3Cost (inst, op1, offset1, op2, offset2);
 
-  regalloc_dry_run_cost += emit3Cost (inst, op1, offset1, op2, offset2);
   if (regalloc_dry_run)
     return;
 
   cost = regalloc_dry_run_cost;
+  bytecost = regalloc_dry_run_cost_bytes;
+  statecost = regalloc_dry_run_cost_states;
   if (!op1)
     emit2 ("%s", asminstnames[inst]);
   else if (!op2)
@@ -988,6 +1143,8 @@
     }
 
   regalloc_dry_run_cost = cost;
+  regalloc_dry_run_cost_bytes = bytecost;
+  regalloc_dry_run_cost_states = statecost;
   //emitDebug(";emit3_o cost: %d total so far: %d", (int)emit3Cost(inst, op1, offset1, op2, offset2), (int)cost);
 }
 
@@ -1143,21 +1300,6 @@
   return FALSE;
 }
 
-static bool
-isPtrPair (const asmop * aop)
-{
-  PAIR_ID pairId = getPairId (aop);
-  switch (pairId)
-    {
-    case PAIR_HL:
-    case PAIR_IY:
-    case PAIR_IX:
-      return TRUE;
-    default:
-      return FALSE;
-    }
-}
-
 static void
 spillPair (PAIR_ID pairId)
 {
@@ -1174,7 +1316,7 @@
       switch (*regname)
         {
         case 'h':
-        case 'l':
+        case 'l':emit2("; spillPairReg hl");
           spillPair (PAIR_HL);
           break;
         case 'd':
@@ -1189,6 +1331,25 @@
     }
 }
 
+/* swap pairs fiels type/base */
+static void
+swapPairs (PAIR_ID pair1Id, PAIR_ID pair2Id)
+{
+  /*AOP_TYPE tt = _G.pairs[pair1Id].last_type;
+  _G.pairs[pair1Id].last_type = _G.pairs[pair2Id].last_type;
+  _G.pairs[pair2Id].last_type = tt;
+  const char *tb = _G.pairs[pair1Id].base;
+  unsigned int tv = _G.pairs[pair1Id].value;
+  _G.pairs[pair1Id].base = _G.pairs[pair2Id].base;
+  _G.pairs[pair2Id].base = tb;
+  _G.pairs[pair1Id].value = _G.pairs[pair2Id].value;
+  _G.pairs[pair2Id].value = tv;*/
+  
+  // For now just spill both: Makign this work would require proper tracking of de (i.e. adding spillPair (PAIR_DE) as consistently as has been done for spillPair (PAIR_HL)
+  spillPair (pair1Id);
+  spillPair (pair2Id);
+}
+
 static void
 _push (PAIR_ID pairId)
 {
@@ -1240,6 +1401,7 @@
     }
   _G.pairs[dstPair].last_type = _G.pairs[srcPair].last_type;
   _G.pairs[dstPair].base = _G.pairs[srcPair].base;
+  _G.pairs[dstPair].value = _G.pairs[srcPair].value;
   _G.pairs[dstPair].offset = _G.pairs[srcPair].offset;
 }
 
@@ -1286,7 +1448,7 @@
          Normally everything is AOP_STK, but for offsets of < -128 or
          > 127 on the Z80 an extended stack pointer is used.
        */
-      if (!IS_GB && (_G.omitFramePtr || sym->stack < INT8MIN || sym->stack > (int) (INT8MAX - getSize (sym->type))))
+      if (!IS_SM83 && (_G.omitFramePtr || sym->stack < INT8MIN || sym->stack > (int) (INT8MAX - getSize (sym->type))))
         {
           emitDebug ("; AOP_EXSTK for %s, _G.omitFramePtr %d, sym->stack %d, size %d", sym->rname, (int) (_G.omitFramePtr),
                      sym->stack, getSize (sym->type));
@@ -1315,7 +1477,7 @@
   if (IN_REGSP (space))
     {
       /*.p.t.20030716 minor restructure to add SFR support to the Z80 */
-      if (IS_GB)
+      if (IS_SM83)
         {
           /* if it is in direct space */
           if (!requires_a)
@@ -1344,7 +1506,7 @@
 
   /* only remaining is far space */
   /* in which case DPTR gets the address */
-  if (IS_GB || IY_RESERVED)
+  if (IS_SM83 || IY_RESERVED)
     {
       /* emitDebug ("; AOP_HL for %s", sym->rname); */
       sym->aop = aop = newAsmop (AOP_HL);
@@ -1369,8 +1531,8 @@
 aopForRemat (symbol *sym)
 {
   iCode *ic = sym->rematiCode;
-  asmop *aop = newAsmop (AOP_IMMD);
   int val = 0;
+  asmop *aop;
   struct dbuf_s dbuf;
 
   wassert(ic);
@@ -1408,17 +1570,27 @@
         break;
     }
 
-  dbuf_init (&dbuf, 128);
-  if (val)
+  if (OP_SYMBOL (IC_LEFT (ic))->onStack)
     {
-      dbuf_printf (&dbuf, "(%s %c 0x%04x)", OP_SYMBOL (IC_LEFT (ic))->rname, val >= 0 ? '+' : '-', abs (val) & 0xffff);
+      aop = newAsmop (AOP_STL);
+      aop->aopu.aop_stk = (long)(OP_SYMBOL (IC_LEFT (ic))->stack) + val;
     }
   else
     {
-      dbuf_append_str (&dbuf, OP_SYMBOL (IC_LEFT (ic))->rname);
+      aop = newAsmop (AOP_IMMD);
+      
+      dbuf_init (&dbuf, 128);
+      if (val)
+        {
+          dbuf_tprintf (&dbuf, "(%s %c %d)", OP_SYMBOL (IC_LEFT (ic))->rname, val >= 0 ? '+' : '-', abs (val) & 0xffff);
+        }
+      else
+        {
+          dbuf_append_str (&dbuf, OP_SYMBOL (IC_LEFT (ic))->rname);
+        }
+      aop->aopu.aop_immd = traceAlloc (&_G.trace.aops, dbuf_detach_c_str (&dbuf));
     }
 
-  aop->aopu.aop_immd = traceAlloc (&_G.trace.aops, dbuf_detach_c_str (&dbuf));
   return aop;
 }
 
@@ -1530,6 +1702,44 @@
 }
 
 /*-----------------------------------------------------------------*/
+/* aopSame - two asmops refer to the same storage                  */
+/*-----------------------------------------------------------------*/
+static bool
+aopSame (const asmop *aop1, int offset1, const asmop *aop2, int offset2, int size)
+{
+  if (aop1 == aop2 && offset1 == offset2)
+    return (true);
+
+  for(; size; size--, offset1++, offset2++)
+    {
+      if (offset1 >= aop1->size || offset2 >= aop2->size)
+        return (false);
+
+      if (aop1->type == AOP_REG && aop2->type == AOP_REG && // Same register
+        aop1->aopu.aop_reg[offset1]->rIdx == aop2->aopu.aop_reg[offset2]->rIdx)
+        continue;
+
+      if (aopOnStack (aop1, offset1, 1) && aopOnStack (aop2, offset2, 1) && !regalloc_dry_run && // Same stack location - stack locations might change after register allocation, so make no assumption during dry run.
+        aop1->aopu.aop_stk + offset1 == aop2->aopu.aop_stk + offset2)
+        continue;
+
+      if (aop1->type == AOP_LIT && aop2->type == AOP_LIT && // Same literal
+        byteOfVal (aop1->aopu.aop_lit, offset1) == byteOfVal (aop2->aopu.aop_lit, offset2))
+        continue;
+
+      // Same file-scope variable.
+      if ((aop1->type == AOP_DIR || aop1->type == AOP_HL || aop1->type == AOP_IY) &&
+        (aop2->type == AOP_DIR || aop2->type == AOP_HL || aop2->type == AOP_IY) &&
+        offset1 == offset2 && !strcmp(aop1->aopu.aop_dir, aop2->aopu.aop_dir))
+        return (true);
+  
+      return (false);
+    }
+
+  return (true);
+}
+
+/*-----------------------------------------------------------------*/
 /* aopOp - allocates an asmop for an operand  :                    */
 /*-----------------------------------------------------------------*/
 static void
@@ -1602,39 +1812,9 @@
      b) has a spill location */
   if (sym->isspilt || sym->nRegs == 0)
     {
-      if (sym->ruonly)
-        {
-          int i;
-          aop = op->aop = sym->aop = newAsmop (AOP_STR);
-          aop->size = getSize (sym->type);
-          for (i = 0; i < 4; i++)
-            aop->aopu.aop_str[i] = ASMOP_RETURN->aopu.aop_reg[i]->name;
-          return;
-        }
+      wassert (!sym->ruonly); // iTemp optimized out via ifxForOp shouldn'T reach here.
 
-      if (sym->accuse)
-        {
-          if (sym->accuse == ACCUSE_A) /* For compability with old register allocator only */
-            {
-              sym->aop = op->aop = aop = newAsmop (AOP_REG);
-              aop->size = getSize (sym->type);
-              wassertl (aop->size == 1, "Internal error: Caching in A, but too big to fit in A");
-              aop->aopu.aop_reg[0] = regsZ80 + A_IDX;
-            }
-          else if (sym->accuse == ACCUSE_IY) /* For compability with old register allocator only */
-            {
-              sym->aop = op->aop = aop = newAsmop (AOP_REG);
-              aop->size = getSize (sym->type);
-              wassertl (aop->size <= 2, "Internal error: Caching in IY, but too big to fit in IY");
-              aop->aopu.aop_reg[0] = regsZ80 + IYL_IDX;
-              aop->aopu.aop_reg[0] = regsZ80 + IYH_IDX;
-            }
-          else
-            {
-              wassertl (0, "Marked as being allocated into A or IY but is actually in neither");
-            }
-          return;
-        }
+      wassert (!sym->accuse); // Should not happen anymore with curetn register allocator.
 
       /* rematerialize it NOW */
       if (sym->remat)
@@ -1647,7 +1827,7 @@
       /* On-stack for dry run. */
       if (sym->nRegs && regalloc_dry_run)
         {
-          sym->aop = op->aop = aop = newAsmop (AOP_STK);
+          sym->aop = op->aop = aop = newAsmop (_G.omitFramePtr ? AOP_EXSTK : AOP_STK);
           aop->size = getSize (sym->type);
           return;
         }
@@ -1692,48 +1872,221 @@
     }
 }
 
-/*-----------------------------------------------------------------*/
-/* freeAsmop - free up the asmop given to an operand               */
-/*----------------------------------------------------------------*/
-static void
-freeAsmop (operand * op, asmop *aaop)
+// Get asmop for registers containing the return type of function
+// Returns 0 if the function does not have a return value or it is not returned in registers.
+static asmop *
+aopRet (sym_link *ftype)
 {
-  asmop *aop;
+  wassert (IS_FUNC (ftype));
 
-  if (!op)
-    aop = aaop;
-  else
-    aop = op->aop;
+  // Adjust returnregs in isReturned in peep.c accordingly when changing asmop_return here.
 
-  if (!aop)
-    return;
+  int size = getSize (ftype->next);
 
-  if (aop->freed)
-    goto dealloc;
+  if (FUNC_SDCCCALL (ftype) == 0 || FUNC_ISSMALLC (ftype) || FUNC_ISZ88DK_FASTCALL (ftype))
+    switch (size)
+      {
+      case 1:
+        return (IS_SM83 ? ASMOP_E : ASMOP_L);
+      case 2:
+        return (IS_SM83 ? ASMOP_DE : ASMOP_HL);
+      case 4:
+        return (IS_SM83 ? ASMOP_HLDE : ASMOP_DEHL);   
+      default:
+        return 0;
+      }
 
-  aop->freed = 1;
+  wassert (FUNC_SDCCCALL (ftype) == 1);
 
-  if (aop->type == AOP_PAIRPTR && !IS_GB && aop->aopu.aop_pairId == PAIR_DE)
+  switch (size)
     {
-      _pop (aop->aopu.aop_pairId);
+    case 1:
+      return (ASMOP_A);
+    case 2:
+      if (IS_RAB || IS_TLCS90 || IS_EZ80_Z80)
+        return ASMOP_HL;
+      else if (IS_SM83)
+        return ASMOP_BC;
+      else
+        return ASMOP_DE;
+    case 4:
+      return (IS_SM83 ? ASMOP_DEBC : ASMOP_HLDE);   
+    default:
+      return 0;
     }
+}
 
-  if (getPairId (aop) == PAIR_HL)
-    {
-      spillPair (PAIR_HL);
-    }
+// Get asmop for registers containing a parameter
+// Returns 0 if the parameter is passed on the stack
+static asmop *
+aopArg (sym_link *ftype, int i)
+{
+  wassert (IS_FUNC (ftype));
 
-dealloc:
-  /* all other cases just dealloc */
-  if (op)
+  if (IFFUNC_HASVARARGS (ftype))
+    return 0;
+
+  value *args = FUNC_ARGS(ftype);
+  wassert (args);
+
+  if (FUNC_ISZ88DK_FASTCALL (ftype))
     {
-      op->aop = NULL;
-      if (IS_SYMOP (op))
+      if (i != 1)
+        return false;
+
+      switch (getSize (args->type))
         {
-          OP_SYMBOL (op)->aop = NULL;
-          /* if the symbol has a spill */
-          if (SPIL_LOC (op))
-            SPIL_LOC (op)->aop = NULL;
+        case 1:
+          return ASMOP_L;
+        case 2:
+          return ASMOP_HL;
+        case 4:
+          return ASMOP_DEHL;
+        default:
+          return 0;
+        }
+    }
+    
+  // Old SDCC calling convention.
+  if (FUNC_SDCCCALL (ftype) == 0 || FUNC_ISSMALLC (ftype) || IFFUNC_ISBANKEDCALL (ftype))
+    return 0;
+
+  wassert (FUNC_SDCCCALL (ftype) == 1);
+
+  if (!FUNC_HASVARARGS (ftype))
+    {
+      int j;
+      value *arg;
+
+      for (j = 1, arg = args; j < i; j++, arg = arg->next)
+        wassert (arg);
+
+      if (i == 1 && getSize (arg->type) == 1)
+        return ASMOP_A;
+      if (i == 1 && getSize (arg->type) == 2)
+        return (IS_SM83 ? ASMOP_DE : ASMOP_HL);
+      if (i == 1 && getSize (arg->type) == 4)
+        return (IS_SM83 ? ASMOP_DEBC : ASMOP_HLDE);
+
+      if (IS_SM83 && i == 2 && aopArg (ftype, 1) == ASMOP_A && getSize (arg->type) == 1)
+        return ASMOP_E;
+      if (IS_SM83 && i == 2 && aopArg (ftype, 1) == ASMOP_A && getSize (arg->type) == 2)
+        return ASMOP_DE;
+  
+      if (IS_SM83 && i == 2 && aopArg (ftype, 1) == ASMOP_DE && getSize (arg->type) == 1)
+        return ASMOP_A;
+      if (IS_SM83 && i == 2 && aopArg (ftype, 1) == ASMOP_DE && getSize (arg->type) == 2)
+        return ASMOP_BC;
+
+      if (!IS_SM83 && i == 2 && aopArg (ftype, 1) == ASMOP_A && getSize (arg->type) == 1)
+        return ASMOP_L;
+
+      if ((IS_Z80 || IS_Z180 || IS_Z80N) && i == 2 && aopArg (ftype, 1) == ASMOP_A && getSize (arg->type) == 2)
+        return ASMOP_DE;
+      if ((IS_Z80 || IS_Z180 || IS_Z80N) && i == 2 && aopArg (ftype, 1) == ASMOP_HL && getSize (arg->type) == 2)
+        return ASMOP_DE;
+
+      if ((IS_RAB || IS_TLCS90 || IS_EZ80_Z80) && i == 2 && aopArg (ftype, 1) == ASMOP_A && getSize (arg->type) == 2)
+        return ASMOP_HL;
+      if ((IS_RAB || IS_TLCS90 || IS_EZ80_Z80) && i == 2 && aopArg (ftype, 1) == ASMOP_HL && getSize (arg->type) == 1)
+        return ASMOP_A;
+      if ((IS_RAB || IS_TLCS90 || IS_EZ80_Z80) && i == 2 && aopArg (ftype, 1) == ASMOP_HLDE && getSize (arg->type) == 1)
+        return ASMOP_A;
+
+      return 0;
+    }
+
+  return 0;
+}
+
+// Return true, iff ftype cleans up stack parameters.
+static bool
+isFuncCalleeStackCleanup (sym_link *ftype)
+{
+  wassert (IS_FUNC (ftype));
+
+  const bool farg = !FUNC_HASVARARGS (ftype) && FUNC_ARGS (ftype) && IS_FLOAT (FUNC_ARGS (ftype)->type); 
+  const bool bigreturn = (getSize (ftype->next) > 4) || IS_STRUCT (ftype->next);
+  int stackparmbytes = bigreturn * 2;
+  for (value *arg = FUNC_ARGS(ftype); arg && !FUNC_HASVARARGS(ftype); arg = arg->next)
+    {
+      int argsize = getSize (arg->type);
+      if (argsize == 1 && FUNC_ISSMALLC (ftype)) // SmallC calling convention passes 8-bit stack arguments as 16 bit.
+        argsize++;
+      if (!SPEC_REGPARM (arg->etype))
+        stackparmbytes += argsize;
+    }
+  if (!stackparmbytes)
+    return false;
+
+  if (IFFUNC_ISZ88DK_CALLEE (ftype))
+    return true;
+
+  if (FUNC_SDCCCALL (ftype) == 0 || FUNC_ISSMALLC (ftype) || FUNC_ISZ88DK_FASTCALL (ftype))
+    return false;
+
+  if (IFFUNC_ISBANKEDCALL (ftype))
+    return false;
+
+  if (FUNC_HASVARARGS (ftype))
+    return false;
+
+  wassert (FUNC_SDCCCALL (ftype) == 1);
+
+  // Callee cleans up stack for all non-vararg functions on sm83.
+  if (IS_SM83)
+    return true;
+
+  // Callee cleans up stack if return value has at most 16 bits or the return value is float and there is a first argument of type float.
+  if (!ftype->next || getSize (ftype->next) <= 2)
+    return true;
+  else if (IS_FLOAT (ftype->next) && farg)
+    return true;
+  return false;
+}
+
+/*-----------------------------------------------------------------*/
+/* freeAsmop - free up the asmop given to an operand               */
+/*----------------------------------------------------------------*/
+static void
+freeAsmop (operand * op, asmop *aaop)
+{
+  asmop *aop;
+
+  if (!op)
+    aop = aaop;
+  else
+    aop = op->aop;
+
+  if (!aop)
+    return;
+
+  if (aop->freed)
+    goto dealloc;
+
+  aop->freed = 1;
+
+  if (aop->type == AOP_PAIRPTR && !IS_SM83 && aop->aopu.aop_pairId == PAIR_DE)
+    {
+      _pop (aop->aopu.aop_pairId);
+    }
+
+  if (getPairId (aop) == PAIR_HL)
+    {
+      spillPair (PAIR_HL);
+    }
+
+dealloc:
+  /* all other cases just dealloc */
+  if (op)
+    {
+      op->aop = NULL;
+      if (IS_SYMOP (op))
+        {
+          OP_SYMBOL (op)->aop = NULL;
+          /* if the symbol has a spill */
+          if (SPIL_LOC (op))
+            SPIL_LOC (op)->aop = NULL;
         }
     }
 
@@ -1829,6 +2182,7 @@
     case AOP_STK:
     case AOP_DIR:
     case AOP_SFR:
+    case AOP_STL:
     case AOP_STR:
     case AOP_CRY:
     case AOP_EXSTK:
@@ -1890,9 +2244,10 @@
       return FALSE;
     case AOP_HL:
     case AOP_EXSTK:
-      return TRUE;
+    case AOP_STL:
+      return true;
     case AOP_STK:
-      return (IS_GB || _G.omitFramePtr);
+      return (IS_SM83 || _G.omitFramePtr);
     case AOP_REG:
     {
       int i;
@@ -1910,50 +2265,19 @@
     }
 }
 
-/*----------------------------------------------------------*/
-/* strtoul_z80: a wrapper to strtoul, which can also handle */
-/* hex numbers with a $ prefix.                             */
-/*----------------------------------------------------------*/
-static unsigned long int 
-strtoul_z80asm (const char *nptr, char **endptr, int base)
-{
-  char *p = NULL;
-  int i, flag = 0, len;
-  unsigned long ret;
-
-  if (nptr != NULL && (p = malloc ((len = strlen (nptr)) + 1 + 1)) != NULL)
-    {
-      memset (p, 0, len + 2);
-      for (i = 0; i < len; i++)
-        {
-          if (!flag)
-            if (isspace (nptr[i]))
-              p[i] = nptr[i];
-            else if (nptr[i] == '$')
-              {
-                p[i] = '0';
-                p[i + 1] = 'x';
-                flag = 1;
-              }
-            else
-              break;
-          else
-            p[i + 1] = nptr[i];
-        }
-    }
-
-  if (flag)
-    ret = strtoul (p, endptr, base);
-  else
-    ret = strtoul (nptr, endptr, base);
-
-  if (p)
-    free (p);
-  return ret;
+// Updated the internally cached value for a pair.
+static void
+updatePair (PAIR_ID pairId, int diff)
+{
+  if (_G.pairs[pairId].last_type == AOP_LIT)
+    _G.pairs[pairId].value = (_G.pairs[pairId].value + (unsigned int)diff) & 0xffff;
+  else if (_G.pairs[pairId].last_type == AOP_IMMD || _G.pairs[pairId].last_type == AOP_IY || _G.pairs[pairId].last_type == AOP_HL ||
+    _G.pairs[pairId].last_type == AOP_STK || _G.pairs[pairId].last_type == AOP_EXSTK)
+    _G.pairs[pairId].offset += diff;
 }
 
 static void
-fetchLitPair (PAIR_ID pairId, asmop *left, int offset)
+fetchLitPair (PAIR_ID pairId, asmop *left, int offset, bool f_dead)
 {
   const char *pair = _pairs[pairId].name;
   char *l = Safe_strdup (aopGetLitWordLong (left, offset, FALSE));
@@ -1962,7 +2286,7 @@
 
   wassert (pair);
 
-  emitDebug (";fetchLitPair");
+  emitDebug (";fetchLitPair %s",  pair);
 
   if (isPtr (pair))
     {
@@ -1995,46 +2319,66 @@
             }
         }
 
-      if (pairId == PAIR_HL && left->type == AOP_LIT && _G.pairs[pairId].last_type == AOP_LIT &&
-          !IS_FLOAT (left->aopu.aop_lit->type) && offset == 0 && _G.pairs[pairId].offset == 0)
+      if (pairId == PAIR_HL && left->type == AOP_LIT && _G.pairs[pairId].last_type == AOP_LIT)
         {
           unsigned new_low, new_high, old_low, old_high;
-          unsigned long v_new = ulFromVal (left->aopu.aop_lit);
-          unsigned long v_old = strtoul_z80asm (_G.pairs[pairId].base, NULL, 0);
-          new_low = (v_new >> 0) & 0xff;
-          new_high = (v_new >> 8) & 0xff;
-          old_low = (v_old >> 0) & 0xff;
-          old_high = (v_old >> 8) & 0xff;
-
+          new_low = byteOfVal (left->aopu.aop_lit, offset);
+          new_high = byteOfVal (left->aopu.aop_lit, offset + 1);
+          old_low = (_G.pairs[pairId].value >> 0) & 0xff;
+          old_high = (_G.pairs[pairId].value >> 8) & 0xff;
+
+          if (new_low == old_low && new_high == old_high)
+            goto adjusted;
+          else if (IS_RAB && !new_high && (new_low == 1 && (old_high || old_low)) && f_dead)
+            {
+              emit2 ("bool hl");
+              regalloc_dry_run_cost++;
+              goto adjusted;
+            }
+          else if (new_high == old_high && new_low == old_high)
+            {
+              emit3_o (A_LD, ASMOP_L, 0, ASMOP_H, 0);
+              goto adjusted;
+            }
+          else if (new_low == old_low && new_high == old_low)
+            {
+              emit3_o (A_LD, ASMOP_H, 0, ASMOP_L, 0);
+              goto adjusted;
+            }
           /* Change lower byte only. */
-          if (new_high == old_high)
+          else if (new_high == old_high)
             {
-              emit3_o (A_LD, ASMOP_L, 0, left, 0);
+              emit3_o (A_LD, ASMOP_L, 0, left, offset);
               goto adjusted;
             }
           /* Change upper byte only. */
           else if (new_low == old_low)
             {
-              emit3_o (A_LD, ASMOP_H, 0, left, 1);
+              emit3_o (A_LD, ASMOP_H, 0, left, offset + 1);
               goto adjusted;
             }
         }
-
-
-      _G.pairs[pairId].last_type = left->type;
-      _G.pairs[pairId].base = traceAlloc (&_G.trace.aops, Safe_strdup (base));
-      _G.pairs[pairId].offset = offset;
     }
+  
   /* Both a lit on the right and a true symbol on the left */
-  emit2 ("ld %s, !hashedstr", pair, l);
-  regalloc_dry_run_cost += (pairId == PAIR_IX || pairId == PAIR_IY) ? 4 : 3;
-  Safe_free (base_str);
-  Safe_free (l);
-  return;
+  if (IS_RAB && pairId == PAIR_HL && left->type == AOP_LIT && !byteOfVal (left->aopu.aop_lit, offset + 1) && !byteOfVal (left->aopu.aop_lit, offset) && f_dead)
+  {
+    emit2 ("bool hl");
+    emit2 ("ld l, h");
+    regalloc_dry_run_cost += 2;
+  }
+  else
+  {
+    emit2 ("ld %s, !hashedstr", pair, l);
+    regalloc_dry_run_cost += (pairId == PAIR_IX || pairId == PAIR_IY) ? 4 : 3;
+  }
 
 adjusted:
   _G.pairs[pairId].last_type = left->type;
-  _G.pairs[pairId].base = traceAlloc (&_G.trace.aops, Safe_strdup (base));
+  if (left->type == AOP_LIT)
+    _G.pairs[pairId].value = byteOfVal (left->aopu.aop_lit, offset) + (byteOfVal (left->aopu.aop_lit, offset + 1) << 8);
+  else
+    _G.pairs[pairId].base = traceAlloc (&_G.trace.aops, Safe_strdup (base));
   _G.pairs[pairId].offset = offset;
   Safe_free (base_str);
   Safe_free (l);
@@ -2051,7 +2395,7 @@
         {
           return PAIR_BC;
         }
-      else if (!IS_GB && !bitVectBitValue (ic->rMask, D_IDX) && !bitVectBitValue (ic->rMask, E_IDX))
+      else if (!IS_SM83 && !bitVectBitValue (ic->rMask, D_IDX) && !bitVectBitValue (ic->rMask, E_IDX))
         {
           return PAIR_DE;
         }
@@ -2069,17 +2413,60 @@
 }
 
 /* If ic != 0, we can safely use isPairDead(). */
+/* By now, genMove / genMove_o is as good or better than this for nearly all uses. */
 static void
 fetchPairLong (PAIR_ID pairId, asmop *aop, const iCode *ic, int offset)
 {
   emitDebug (";fetchPairLong");
 
+  if (aop->type == AOP_STL && !offset)
+    {
+      if (IS_SM83 && pairId == PAIR_DE || pairId == PAIR_BC)
+        {
+          _push (PAIR_HL);
+          emit2 ("ld hl, !immed%d", spOffset(aop->aopu.aop_stk));
+          emit2 ("add hl, sp");
+          emit2 ("ld %s, l", _pairs[pairId].l);
+          emit2 ("ld %s, h", _pairs[pairId].h);
+          regalloc_dry_run_cost += 6;
+          _pop (PAIR_HL);
+          return;
+        }
+      else if (pairId == PAIR_IY)
+        {
+          emit2 ("ld iy, !immed%d", spOffset(aop->aopu.aop_stk));
+          emit2 ("add iy, sp");
+          regalloc_dry_run_cost += 6;
+          return;
+        }
+
+      if (pairId == PAIR_DE)
+        emit2 ("ex de, hl");
+      emit2 ("ld hl, !immed%d", spOffset(aop->aopu.aop_stk));
+      emit2 ("add hl, sp");
+      if (pairId == PAIR_DE)
+        emit2 ("ex de, hl");
+      regalloc_dry_run_cost += 4 + 2 * (pairId != PAIR_HL);
+      spillPair (pairId);
+      return;
+    }
+  else if (aop->type == AOP_STL && offset >= 2)
+    {
+      fetchLitPair (pairId, ASMOP_ZERO, 0, true);
+      return;
+    }
+  else if (aop->type == AOP_STL)
+    {
+      UNIMPLEMENTED;
+      return;
+    }
+
   /* if this is rematerializable */
   if (isLitWord (aop))
-    fetchLitPair (pairId, aop, offset);
+    fetchLitPair (pairId, aop, offset, true);
   else
     {
-      if (getPairId (aop) == pairId)
+      if (getPairId_o (aop, offset) == pairId)
         {
           /* Do nothing */
         }
@@ -2090,8 +2477,9 @@
           regalloc_dry_run_cost += 3;
         }
       /* Getting the parameter by a pop / push sequence is cheaper when we have a free pair (except for the Rabbit, which has an even cheaper sp-relative load).
+         SM83 is nearly twice as fast doing it byte by byte, but that's a byte bigger.
          Stack allocation can change after register allocation, so assume this optimization is not possible for the allocator's cost function (unless the stack location is for a parameter). */
-      else if (!IS_RAB && aop->size - offset >= 2 &&
+      else if (!IS_RAB && (!IS_SM83 || optimize.codeSize) && aop->size - offset >= 2 &&
                (aop->type == AOP_STK || aop->type == AOP_EXSTK) && (!regalloc_dry_run || aop->aopu.aop_stk > 0)
                && (aop->aopu.aop_stk + offset + _G.stack.offset + (aop->aopu.aop_stk > 0 ? _G.stack.param_offset : 0) +
                    _G.stack.pushed) == 2 && ic && getFreePairId (ic) != PAIR_INVALID && getFreePairId (ic) != pairId)
@@ -2111,11 +2499,11 @@
           _pop (pairId);
           _push (pairId);
         }
-      else if (!IS_GB && (aop->type == AOP_IY || aop->type == AOP_HL) && !(pairId == PAIR_IY && aop->size < 2))
+      else if (!IS_SM83 && (aop->type == AOP_IY || aop->type == AOP_HL) && !(pairId == PAIR_IY && aop->size < 2))
         {
           /* Instead of fetching relative to IY, just grab directly
              from the address IY refers to */
-          emit2 ("ld %s, (%s)", _pairs[pairId].name, aopGetLitWordLong (aop, offset, FALSE));
+          emit2 ("ld %s, !mems", _pairs[pairId].name, aopGetLitWordLong (aop, offset, FALSE));
           regalloc_dry_run_cost += (pairId == PAIR_HL ? 3 : 4);
 
           if (aop->size < 2)
@@ -2125,7 +2513,7 @@
             }
         }
       /* we need to get it byte by byte */
-      else if (pairId == PAIR_HL && (IS_GB || (IY_RESERVED && (aop->type == AOP_HL || aop->type == AOP_EXSTK))) && requiresHL (aop))
+      else if (pairId == PAIR_HL && (IS_SM83 || IY_RESERVED) && (aop->type == AOP_HL || aop->type == AOP_EXSTK || IS_SM83 && aop->type == AOP_STK) && requiresHL (aop))
         {
           if (!regalloc_dry_run)        // TODO: Fix this to get correct cost!
             aopGet (aop, offset, FALSE);
@@ -2145,7 +2533,7 @@
                 }
               else if (IS_EZ80_Z80)
                 {
-                  emit2 ("ld hl, (hl)");
+                  emit2 ("ld hl, !*hl");
                   regalloc_dry_run_cost += 2;
                 }
               else
@@ -2153,8 +2541,7 @@
                   if (ic && bitVectBitValue (ic->rMask, A_IDX))
                     _push (PAIR_AF);
 
-                  emit2 ("ld a, !*hl");
-                  emit2 ("inc hl");
+                  emit2 ("!ldahli");
                   emit2 ("ld h, !*hl");
                   emit2 ("ld l, a");
                   regalloc_dry_run_cost += 4;
@@ -2198,7 +2585,7 @@
                   emit2 ("ld %s, %s", _pairs[id].l, aopGet (aop, offset, FALSE));
                   emit2 ("ld %s, %s", _pairs[id].h, aopGet (aop, offset + 1, FALSE));
                 }
-              regalloc_dry_run_cost += ld_cost (ASMOP_L, aop) + ld_cost (ASMOP_H, aop);
+              regalloc_dry_run_cost += ld_cost (ASMOP_L, 0, aop, offset) + ld_cost (ASMOP_H, 0, aop, offset + 1);
 
               if ((IS_RAB || IS_TLCS90) && id == PAIR_HL)
                 {
@@ -2231,7 +2618,7 @@
                   && aop->type == AOP_STK
                   || abs (sp_offset) <= 127))
             {
-              if (pairId == PAIR_DE)
+              if (pairId == PAIR_DE && !(ic && isPairDead (PAIR_HL, ic)))
                 {
                   emit2 ("ex de, hl");
                   regalloc_dry_run_cost += 1;
@@ -2253,7 +2640,7 @@
               _moveA3 (aop, offset);
               if (!regalloc_dry_run)
                 emit2 ("ld %s, %s", _pairs[pairId].h, aopGet (aop, offset + 1, FALSE));
-              regalloc_dry_run_cost += ld_cost (ASMOP_A, aop);
+              regalloc_dry_run_cost += ld_cost (ASMOP_H, 0, aop, offset + 1);
               emit2 ("ld %s, a", _pairs[pairId].l);
               regalloc_dry_run_cost += 1;
             }
@@ -2264,21 +2651,25 @@
               regalloc_dry_run_cost++;
               if (!regalloc_dry_run)
                 emit2 ("ld %s, %s", _pairs[pairId].l, aopGet (aop, offset, FALSE));
-              regalloc_dry_run_cost += ld_cost (ASMOP_L, aop);
+              regalloc_dry_run_cost += ld_cost (ASMOP_L, 0, aop, offset);
             }
           else
             {
+              if (pairId == PAIR_HL && (aopInReg (aop, offset, IYL_IDX) || aopInReg (aop, offset, IYH_IDX)))
+                UNIMPLEMENTED;
               if (!aopInReg (aop, offset, _pairs[pairId].l_idx))
                 {
                    if (!regalloc_dry_run)
                      emit2 ("ld %s, %s", _pairs[pairId].l, aopGet (aop, offset, FALSE));
-                   regalloc_dry_run_cost += ld_cost (ASMOP_L, aop);
+                   regalloc_dry_run_cost += ld_cost (ASMOP_L, 0, aop, offset);
                 }
+              if (pairId == PAIR_HL && (aopInReg (aop, offset + 1, IYL_IDX) || aopInReg (aop, offset + 1, IYH_IDX)))
+                UNIMPLEMENTED;
               if (!aopInReg (aop, offset + 1, _pairs[pairId].h_idx))
                 {
                    if (!regalloc_dry_run)
                      emit2 ("ld %s, %s", _pairs[pairId].h, aopGet (aop, offset + 1, FALSE));
-                   regalloc_dry_run_cost += ld_cost (ASMOP_H, aop);
+                   regalloc_dry_run_cost += ld_cost (ASMOP_H, 0, aop, offset);
                 }
             }
         }
@@ -2305,7 +2696,7 @@
       offset += 2;
     }
 
-  if (id == PAIR_DE && !IS_GB) // TODO: Could hl be in use for gbz80, so it needs to be saved and restored?
+  if (id == PAIR_DE && !IS_SM83) // TODO: Could hl be in use for sm83, so it needs to be saved and restored?
     {
       emit2 ("ex de, hl");
       regalloc_dry_run_cost++;
@@ -2326,10 +2717,10 @@
     {
       wassert (id == PAIR_DE || id == PAIR_HL);
       emit2 ("!ldahlsp", offset);
-      regalloc_dry_run_cost += 4 - IS_GB * 2;
+      regalloc_dry_run_cost += 4 - IS_SM83 * 2;
     }
 
-  if (id == PAIR_DE && !IS_GB)
+  if (id == PAIR_DE && !IS_SM83)
     {
       emit2 ("ex de, hl");
       regalloc_dry_run_cost++;
@@ -2346,6 +2737,8 @@
       regalloc_dry_run_cost++;
       offset -= 2;
     }
+    
+  spillPair (id);
 }
 
 static void
@@ -2359,12 +2752,12 @@
   switch (aop->type)
     {
     case AOP_EXSTK:
-      wassertl (!IS_GB, "The GBZ80 doesn't have an extended stack");
+      wassertl (!IS_SM83, "The SM83 doesn't have an extended stack");
 
     case AOP_STK:
       ; int abso = aop->aopu.aop_stk + offset + _G.stack.offset + (aop->aopu.aop_stk > 0 ? _G.stack.param_offset : 0);
 
-      if ((_G.pairs[pairId].last_type == AOP_STK || _G.pairs[pairId].last_type == AOP_EXSTK) && abs (_G.pairs[pairId].offset - abso) < 3)
+      if ((_G.pairs[pairId].last_type == AOP_STK || _G.pairs[pairId].last_type == AOP_EXSTK) && abs (_G.pairs[pairId].offset - abso) < (_G.preserveCarry ? 5 : 3))
         adjustPair (_pairs[pairId].name, &_G.pairs[pairId].offset, abso);
       else
         setupPairFromSP (pairId, abso + _G.stack.pushed);
@@ -2373,14 +2766,16 @@
 
       break;
 
-    case AOP_HL: // Legacy.
-      fetchLitPair (pairId, (asmop *) aop, offset);
+    // Legacy.
+    case AOP_HL:
+    case AOP_IY:
+      fetchLitPair (pairId, (asmop *) aop, offset, true);
       _G.pairs[pairId].offset = offset;
       break;
 
     case AOP_PAIRPTR:
       wassert (!offset);
-      
+
       shiftIntoPair (pairId, (asmop *) aop); // Legacy. Todo eliminate uses of shiftIntoPair() ?
 
       break;
@@ -2402,18 +2797,18 @@
     {
     case AOP_IY:
       wassertl (pairId == PAIR_IY || pairId == PAIR_HL, "AOP_IY must be in IY or HL");
-      fetchLitPair (pairId, aop, 0);
+      fetchLitPair (pairId, aop, 0, true);
       break;
 
     case AOP_HL:
       wassertl (pairId == PAIR_HL, "AOP_HL must be in HL");
 
-      fetchLitPair (pairId, aop, offset);
+      fetchLitPair (pairId, aop, offset, true);
       _G.pairs[pairId].offset = offset;
       break;
 
     case AOP_EXSTK:
-      wassertl (!IS_GB, "The GBZ80 doesn't have an extended stack");
+      wassertl (!IS_SM83, "The SM83 doesn't have an extended stack");
       wassertl (pairId == PAIR_IY || pairId == PAIR_HL, "The Z80 extended stack must be in IY or HL");
 
       {
@@ -2528,7 +2923,7 @@
                 {
                 case 2:
                   // dbuf_tprintf (&dbuf, "!bankimmeds", aop->aopu.aop_immd); Bank support not fully implemented yet.
-                  dbuf_tprintf (&dbuf, "#0x00");
+                  dbuf_tprintf (&dbuf, "!zero");
                   break;
 
                 case 1:
@@ -2540,13 +2935,13 @@
                   break;
 
                 default:
-                  dbuf_tprintf (&dbuf, "#0x00");
+                  dbuf_tprintf (&dbuf, "!zero");
                 }
             }
           break;
 
         case AOP_DIR:
-          wassert (IS_GB);
+          wassert (IS_SM83);
           emit2 ("ld a, (%s+%d)", aop->aopu.aop_dir, offset);
           regalloc_dry_run_cost += 3;
           dbuf_append_char (&dbuf, 'a');
@@ -2554,16 +2949,16 @@
 
         case AOP_SFR:
           wassertl (!IS_TLCS90, "TLCS-90 does not have a separate I/O space");
-          if (IS_GB)
+          if (IS_SM83)
             {
-              emit2 ("ldh a, (%s+%d)", aop->aopu.aop_dir, offset);
+              emit2 ("!rldh", aop->aopu.aop_dir, offset);
               regalloc_dry_run_cost += 2;
               dbuf_append_char (&dbuf, 'a');
             }
           else if (IS_RAB)
             {
               emit2 ("ioi");
-              emit2 ("ld a, (%s)", aop->aopu.aop_dir);
+              emit2 ("ld a, !mems", aop->aopu.aop_dir);
               emit2 ("nop");    /* Workaround for Rabbit 2000 hardware bug. see TN302 for details. */
               dbuf_append_char (&dbuf, 'a');
             }
@@ -2580,12 +2975,12 @@
               else if (z80_opts.port_mode == 180)
                 {
                   /* z180 in0/out0 mode */
-                  emit2 ("in0 a, (%s)", aop->aopu.aop_dir);
+                  emit2 ("in0 a, !mems", aop->aopu.aop_dir);
                 }
               else
                 {
                   /* 8 bit mode */
-                  emit2 ("in a, (%s)", aop->aopu.aop_dir);
+                  emit2 ("in a, !mems", aop->aopu.aop_dir);
                 }
 
               dbuf_append_char (&dbuf, 'a');
@@ -2602,7 +2997,7 @@
           break;
 
         case AOP_IY:
-          wassert (!IS_GB);
+          wassert (!IS_SM83);
           setupPair (PAIR_IY, aop, offset);
           dbuf_tprintf (&dbuf, "!*iyx", offset);
           break;
@@ -2610,14 +3005,25 @@
         case AOP_EXSTK:
           if (!IY_RESERVED)
             {
-              wassert (!IS_GB);
+              wassert (!IS_SM83);
               setupPair (PAIR_IY, aop, offset);
               dbuf_tprintf (&dbuf, "!*iyx", offset);
               break;
             }
 
         case AOP_STK:
-          if (IS_GB || aop->type == AOP_EXSTK)
+          if (IS_TLCS90) // Try to use (sp) addressing mode.
+            {
+              int sp_offset = aop->aopu.aop_stk + offset + (aop->aopu.aop_stk > 0 ? _G.stack.param_offset : 0) + _G.stack.pushed + _G.stack.offset;
+
+              if (!sp_offset)
+                {
+                  dbuf_tprintf (&dbuf, "(sp)");
+                  break;
+                }
+            }
+
+          if (IS_SM83 || aop->type == AOP_EXSTK)
             {
               pointPairToAop (PAIR_HL, aop, offset);
               dbuf_tprintf (&dbuf, "!*hl");
@@ -2657,7 +3063,7 @@
           else if (aop->aopu.aop_pairId == PAIR_IY)
             dbuf_tprintf (&dbuf, "!*iyx", offset);
           else
-            dbuf_printf (&dbuf, "(%s)", _pairs[aop->aopu.aop_pairId].name);
+            dbuf_tprintf (&dbuf, "!mems", _pairs[aop->aopu.aop_pairId].name);
           break;
 
         default:
@@ -2686,11 +3092,8 @@
   return (*s == '#' || *s == '$');
 }
 
-#define AOP(op) op->aop
-#define AOP_TYPE(op) AOP(op)->type
-#define AOP_SIZE(op) AOP(op)->size
-#define AOP_NEEDSACC(x) (AOP(x) && ((AOP_TYPE(x) == AOP_CRY) || (AOP_TYPE(x) == AOP_SFR)))
-#define AOP_IS_PAIRPTR(x, p) (AOP_TYPE (x) == AOP_PAIRPTR && AOP (x)->aopu.aop_pairId == p)
+#define AOP_NEEDSACC(x) ((x)->aop && (((x)->aop->type == AOP_CRY) || ((x)->aop->type == AOP_SFR)))
+#define AOP_IS_PAIRPTR(x, p) ((x)->aop->type == AOP_PAIRPTR && (x)->aop->aopu.aop_pairId == (p))
 
 static bool
 canAssignToPtr (const char *s)
@@ -2743,7 +3146,7 @@
 
     case AOP_DIR:
       /* Direct.  Hmmm. */
-      wassert (IS_GB);
+      wassert (IS_SM83);
       if (strcmp (s, "a"))
         emit2 ("ld a, %s", s);
       emit2 ("ld (%s+%d),a", aop->aopu.aop_dir, offset);
@@ -2751,12 +3154,12 @@
 
     case AOP_SFR:
       wassertl (!IS_TLCS90, "TLCS-90 does not have a separate I/O space");
-      if (IS_GB)
+      if (IS_SM83)
         {
-          //  wassert (IS_GB);
+          //  wassert (IS_SM83);
           if (strcmp (s, "a"))
             emit2 ("ld a, %s", s);
-          emit2 ("ldh (%s+%d),a", aop->aopu.aop_dir, offset);
+          emit2 ("!lldh", aop->aopu.aop_dir, offset);
         }
       else if (IS_RAB)
         {
@@ -2767,7 +3170,7 @@
            * (for internal vs. external I/O space
            */
           emit2 ("ioi");
-          emit2 ("ld (%s),a", aop->aopu.aop_dir);
+          emit2 ("ld !mems,a", aop->aopu.aop_dir);
           emit2 ("nop");        /* Workaround for Rabbit 2000 hardware bug. see TN302 for details. */
         }
       else
@@ -2785,7 +3188,7 @@
                   s = "a";
                 }
 
-              emit2 ("ld bc,#%s", aop->aopu.aop_dir);
+              emit2 ("ld bc, !hashedstr", aop->aopu.aop_dir);
               emit2 ("out (c),%s", s);
 
               if (aop->bcInUse)
@@ -2820,7 +3223,7 @@
       break;
 
     case AOP_IY:
-      wassert (!IS_GB);
+      wassert (!IS_SM83);
       if (!canAssignToPtr (s))
         {
           emit2 ("ld a, %s", s);
@@ -2835,7 +3238,7 @@
       break;
 
     case AOP_HL:
-      //wassert (IS_GB);
+      //wassert (IS_SM83);
       /* PENDING: for re-target */
       if (!strcmp (s, "!*hl") || !strcmp (s, "(hl)") || !strcmp (s, "[hl]"))
         {
@@ -2855,7 +3258,7 @@
     case AOP_EXSTK:
       if(!IY_RESERVED)
         {
-          wassert (!IS_GB);
+          wassert (!IS_SM83);
           if (!canAssignToPtr (s))
             {
               emit2 ("ld a, %s", s);
@@ -2871,7 +3274,7 @@
        }
 
     case AOP_STK:
-      if (IS_GB || aop->type == AOP_EXSTK)
+      if (IS_SM83 || aop->type == AOP_EXSTK)
         {
           /* PENDING: re-target */
           if (!strcmp (s, "!*hl") || !strcmp (s, "(hl)") || !strcmp (s, "[hl]"))
@@ -2956,7 +3359,7 @@
       else if (aop->aopu.aop_pairId == PAIR_IY)
         emit2 ("ld !*iyx, %s", 0, s);
       else
-        emit2 ("ld (%s), %s", _pairs[aop->aopu.aop_pairId].name, s);
+        emit2 ("ld !mems, %s", _pairs[aop->aopu.aop_pairId].name, s);
       break;
 
     default:
@@ -2968,48 +3371,152 @@
   dbuf_destroy (&dbuf);
 }
 
-// Move, but try not to. Cannot use xor to zero, since xor resets the carry flag.
+// Move, but try not to. Preserves flags. Cannot use xor to zero, since xor resets the carry flag.
 static void
 cheapMove (asmop *to, int to_offset, asmop *from, int from_offset, bool a_dead)
 {
+  // emitDebug ("; cheapMove");
+
   if (aopInReg (to, to_offset, A_IDX))
     a_dead = true;
 
+  if (from->type == AOP_STL)
+    {
+      if (from_offset > 2)
+        {
+          cheapMove (to, to_offset, ASMOP_ZERO, 0, a_dead);
+          return;
+        }
+      if (aopInReg (to, to_offset, L_IDX) || aopInReg (to, to_offset, H_IDX))
+        {
+          UNIMPLEMENTED;
+          return;
+        }
+
+      _push (PAIR_HL);
+      _push (PAIR_AF); // Preserve f
+      emit2 ("ld hl, !immed%d", spOffset(from->aopu.aop_stk));
+      emit2 ("add hl, sp");
+      _pop (PAIR_AF);
+      regalloc_dry_run_cost += 4;
+      spillPair (PAIR_HL);
+      cheapMove (to, to_offset, ASMOP_HL, from_offset, a_dead);
+      _pop (PAIR_HL);
+
+      return;
+    }
+
+  const bool from_index = aopInReg (from, from_offset, IYL_IDX) || aopInReg (from, from_offset, IYH_IDX);
+  const bool to_index = aopInReg (to, to_offset, IYL_IDX) || aopInReg (to, to_offset, IYH_IDX);
+  const bool index = to_index || from_index;
+
   if (to->type == AOP_REG && from->type == AOP_REG)
     {
       if (to->aopu.aop_reg[to_offset] == from->aopu.aop_reg[from_offset])
         return;
-      bool from_index = aopInReg (from, from_offset, IYL_IDX) || aopInReg (from, from_offset, IYH_IDX);
-      bool to_index = aopInReg (to, to_offset, IYL_IDX)  || aopInReg (to, to_offset, IYH_IDX);
-      bool index = to_index || from_index;
-      if (!index || IS_EZ80_Z80)
+
+      if (!index ||
+        // eZ80 can assign between any byte of an index register and any non-hl register.
+        (IS_EZ80_Z80 || IS_Z80N) && !aopInReg (to, to_offset, L_IDX) && !aopInReg (to, to_offset, H_IDX) && !aopInReg (from, from_offset, L_IDX) && !aopInReg (from, from_offset, H_IDX))
         {
           bool a = aopInReg (to, to_offset, A_IDX) || aopInReg (from, from_offset, A_IDX);
           if (!regalloc_dry_run)
             aopPut (to, aopGet (from, from_offset, false), to_offset);
-          regalloc_dry_run_cost += 1 + (IS_TLCS90 + !a) + index;
+          regalloc_dry_run_cost += 1 + (IS_TLCS90 && !a) + index;
+          spillPairReg (to->aopu.aop_reg[to_offset]->name);
           return;
         }
-      if (aopInReg (from, from_offset, IYL_IDX) && !to_index && a_dead)
+#if 0 // Might destroy carry. Would also mess up interrupts on TLCS-90.
+      if (aopInReg (from, from_offset, IYH_IDX) && !to_index && a_dead)
         {
           _push(PAIR_IY);
           _pop (PAIR_AF);
           cheapMove (to, to_offset, ASMOP_A, 0, true);
           return;
         }
-      if (from_index && !to_index && _G.stack.pushed + _G.stack.offset + 2 <= 127 && !_G.omitFramePtr)
-        {
-          _push(PAIR_IY);
-          if (!regalloc_dry_run)
-            emit2 ("ld %s, %d (ix)", aopGet (to, to_offset, false), _G.stack.pushed + _G.stack.offset);
-          regalloc_dry_run_cost += 3;
-          _pop(PAIR_IY);
-          return;
-        }
+#endif
+    }
 
-      // Can't do it (todo: implement something there - will be expensive though, probably at least 7B of code).
-      regalloc_dry_run_cost += 100;
-      wassert (regalloc_dry_run);
+  if (to->type == AOP_REG && from_index && !to_index && - _G.stack.pushed - _G.stack.offset >= -128 && !_G.omitFramePtr)
+    {
+      _push(PAIR_IY);
+      if (!regalloc_dry_run)
+        emit2 ("ld %s, %d (ix)", aopGet (to, to_offset, false), - _G.stack.pushed - _G.stack.offset + aopInReg (from, from_offset, IYH_IDX));
+      regalloc_dry_run_cost += 3;
+      spillPairReg (to->aopu.aop_reg[to_offset]->name);
+      _pop(PAIR_IY);
+      return;
+    }
+   else if (to_index && !from_index && from->type == AOP_REG && - _G.stack.pushed - _G.stack.offset >= -128 && !_G.omitFramePtr)
+    {
+      _push(PAIR_IY);
+      if (!regalloc_dry_run)
+        emit2 ("ld %d (ix), %s", - _G.stack.pushed - _G.stack.offset + aopInReg (to, to_offset, IYH_IDX), aopGet (from, from_offset, false));
+      regalloc_dry_run_cost += 3;
+      _pop(PAIR_IY);
+      return;
+    }
+  
+  if (from_index && !to_index && !aopInReg (to, to_offset, L_IDX) && !aopInReg (to, to_offset, H_IDX))
+    {
+      _push (PAIR_IY);
+      emit2 ("ex (sp), hl");
+      regalloc_dry_run_cost += 1;
+      cheapMove (to, to_offset, aopInReg (from, from_offset, IYL_IDX) ? ASMOP_L : ASMOP_H, 0, a_dead);
+      emit2 ("ex (sp), hl");
+      regalloc_dry_run_cost += 1;
+      _pop (PAIR_IY);
+      return;
+    }
+  else if (to_index && !from_index && !aopInReg (from, from_offset, L_IDX) && !aopInReg (from, from_offset, H_IDX))
+    {
+      _push (PAIR_IY);
+      emit2 ("ex (sp), hl");
+      regalloc_dry_run_cost += 1;
+      cheapMove (aopInReg (to, to_offset, IYL_IDX) ? ASMOP_L : ASMOP_H, 0, from, from_offset, a_dead);
+      emit2 ("ex (sp), hl");
+      regalloc_dry_run_cost += 1;
+      _pop (PAIR_IY);
+      return;
+    }
+  else if (from_index && !to_index)
+    {
+      wassert (aopInReg (to, to_offset, L_IDX) || aopInReg (to, to_offset, H_IDX));
+      _push (PAIR_IY);
+      emit2 ("ex de, hl");
+      emit2 ("ex (sp), hl");
+      regalloc_dry_run_cost += 1;
+      cheapMove (aopInReg (to, to_offset, L_IDX) ? ASMOP_E : ASMOP_D, 0, aopInReg (from, from_offset, IYL_IDX) ? ASMOP_L : ASMOP_H, 0, a_dead);
+      emit2 ("ex (sp), hl");
+      emit2 ("ex de, hl");
+      regalloc_dry_run_cost += 1;
+      _pop (PAIR_IY);
+      return;
+    }
+  else if (to_index && !from_index)
+    {
+      wassert (aopInReg (from, from_offset, L_IDX) || aopInReg (from, from_offset, H_IDX));
+      _push (PAIR_IY);
+      emit2 ("ex de, hl");
+      emit2 ("ex (sp), hl");
+      regalloc_dry_run_cost += 2;
+      cheapMove (aopInReg (to, to_offset, IYL_IDX) ? ASMOP_L : ASMOP_H, 0, aopInReg (from, from_offset, L_IDX) ? ASMOP_E : ASMOP_D, 0, a_dead);
+      emit2 ("ex (sp), hl");
+      emit2 ("ex de, hl");
+      regalloc_dry_run_cost += 2;
+      _pop (PAIR_IY);
+      return;
+    }
+  else if (to_index && from_index)
+    {
+      _push (PAIR_IY);
+      emit2 ("ex (sp), hl");
+      regalloc_dry_run_cost += 1;
+      cheapMove (aopInReg (to, to_offset, IYL_IDX) ? ASMOP_L : ASMOP_H, 0, aopInReg (to, to_offset, IYL_IDX) ? ASMOP_L : ASMOP_H, 0, a_dead);
+      emit2 ("ex (sp), hl");
+      regalloc_dry_run_cost += 1;
+      _pop (PAIR_IY);
+      return;
     }
 
   // Try to push to avoid setting up temporary stack pointer in hl or iy.
@@ -3029,12 +3536,22 @@
         }
     }
 
-  if (aopInReg (from, from_offset, A_IDX) && to->type == AOP_IY)
+  if (from->type == AOP_IY && aopInReg (to, to_offset, A_IDX) && from_offset < from->size)
+    {
+      emit2 ("ld a, (%s+%d)", from->aopu.aop_dir, from_offset);
+      regalloc_dry_run_cost += 3;
+    }
+  else if (aopInReg (from, from_offset, A_IDX) && to->type == AOP_IY)
     {
+      wassert (to_offset < to->size);
       emit2 ("ld (%s+%d), a", to->aopu.aop_dir, to_offset);
       regalloc_dry_run_cost += 3;
     }
-  else if (!aopInReg (to, to_offset, A_IDX) && !aopInReg (from, from_offset, A_IDX) && (from->type == AOP_DIR || from->type == AOP_SFR || to->type == AOP_IY && from->type == AOP_EXSTK)) // Go through a.
+  else if (!aopInReg (to, to_offset, A_IDX) && !aopInReg (from, from_offset, A_IDX) && // Go through a.
+    (from->type == AOP_DIR ||
+    from->type == AOP_SFR || to->type == AOP_SFR ||
+    (to->type == AOP_HL || to->type == AOP_IY || to->type == AOP_EXSTK || to->type == AOP_STK) && (from->type == AOP_HL || from->type == AOP_IY || from->type == AOP_EXSTK || from->type == AOP_STK) ||
+    (to->type == AOP_HL || IS_SM83 && to->type == AOP_STK || to->type == AOP_EXSTK) && (aopInReg(from, from_offset, L_IDX) || aopInReg(from, from_offset, H_IDX))))
     {
       if (!a_dead)
         _push (PAIR_AF);
@@ -3049,13 +3566,15 @@
     {
       if (!regalloc_dry_run)
         aopPut (to, aopGet (from, from_offset, false), to_offset);
+      if (to->type == AOP_REG)
+        spillPairReg (to->aopu.aop_reg[to_offset]->name);
 
-      regalloc_dry_run_cost += ld_cost (to, from_offset < from->size ? from : ASMOP_ZERO);
+      regalloc_dry_run_cost += ld_cost (to, 0, from_offset < from->size ? from : ASMOP_ZERO, from_offset);
     }
 }
 
 static void
-commitPair (asmop *aop, PAIR_ID id, const iCode *ic, bool dont_destroy)
+commitPair (asmop *aop, PAIR_ID id, const iCode *ic, bool dont_destroy) // Obsolete. Replace uses by genMove or genMove_o.
 {
   int fp_offset = aop->aopu.aop_stk + (aop->aopu.aop_stk > 0 ? _G.stack.param_offset : 0);
   int sp_offset = fp_offset + _G.stack.pushed + _G.stack.offset;
@@ -3064,7 +3583,7 @@
     return;
 
   /* Stack positions will change, so do not assume this is possible in the cost function. */
-  if (!regalloc_dry_run && !IS_GB && (aop->type == AOP_STK || aop->type == AOP_EXSTK) && !sp_offset
+  if (!regalloc_dry_run && !IS_SM83 && (aop->type == AOP_STK || aop->type == AOP_EXSTK) && !sp_offset
       && ((!IS_RAB && id == PAIR_HL) || id == PAIR_IY) && !dont_destroy)
     {
       emit2 ("ex (sp), %s", _pairs[id].name);
@@ -3094,9 +3613,9 @@
     }
 
   /* PENDING: Verify this. */
-  else if (id == PAIR_HL && requiresHL (aop) && (IS_GB || IY_RESERVED && aop->type != AOP_HL && aop->type != AOP_IY))
+  else if (id == PAIR_HL && requiresHL (aop) && (IS_SM83 || IY_RESERVED && aop->type != AOP_HL && aop->type != AOP_IY))
     {
-      if (bitVectBitValue (ic->rSurv, D_IDX))
+      if (!isRegDead (D_IDX, ic))
         _push (PAIR_DE);
       if (!regalloc_dry_run)
         {
@@ -3105,18 +3624,18 @@
           aopPut (aop, "a", 0);
           aopPut (aop, "d", 1);
         }
-      regalloc_dry_run_cost += (2 + ld_cost (aop, ASMOP_A) + ld_cost (aop, ASMOP_D));
-      if (bitVectBitValue (ic->rSurv, D_IDX))
+      regalloc_dry_run_cost += (2 + ld_cost (aop, 0, ASMOP_A, 0) + ld_cost (aop, 0, ASMOP_D, 0));
+      if (!isRegDead (D_IDX, ic))
         _pop (PAIR_DE);
     }
   else
     {
       /* Special cases */
-      if ((aop->type == AOP_IY || aop->type == AOP_HL) && !IS_GB && aop->size == 2)
+      if ((aop->type == AOP_IY || aop->type == AOP_HL) && !IS_SM83 && aop->size == 2)
         {
           if (!regalloc_dry_run)
             {
-              emit2 ("ld (%s), %s", aopGetLitWordLong (aop, 0, FALSE), _pairs[id].name);
+              emit2 ("ld !mems, %s", aopGetLitWordLong (aop, 0, FALSE), _pairs[id].name);
             }
           regalloc_dry_run_cost += (id == PAIR_HL ? 3 : 4);
         }
@@ -3129,9 +3648,10 @@
               cheapMove (aop, 1, ASMOP_B, 0, true);
               break;
             case PAIR_DE:
-              if (!IS_GB && aop->type == AOP_REG && aop->aopu.aop_reg[0]->rIdx == L_IDX && aop->aopu.aop_reg[1]->rIdx == H_IDX && !dont_destroy)
+              if (!IS_SM83 && aop->type == AOP_REG && aop->aopu.aop_reg[0]->rIdx == L_IDX && aop->aopu.aop_reg[1]->rIdx == H_IDX && !dont_destroy)
                 {
                   emit2 ("ex de, hl");
+                  swapPairs (PAIR_DE, PAIR_HL);
                   regalloc_dry_run_cost++;
                 }
               else
@@ -3152,9 +3672,10 @@
                   cheapMove (aop, 1, ASMOP_H, 0, true);
                   cheapMove (aop, 0, ASMOP_L, 0, true);
                 }
-              else if (!IS_GB && aop->type == AOP_REG && aop->aopu.aop_reg[0]->rIdx == E_IDX && aop->aopu.aop_reg[1]->rIdx == D_IDX && !dont_destroy)
+              else if (!IS_SM83 && aop->type == AOP_REG && aop->aopu.aop_reg[0]->rIdx == E_IDX && aop->aopu.aop_reg[1]->rIdx == D_IDX && !dont_destroy)
                 {
                   emit2 ("ex de, hl");
+                  swapPairs (PAIR_DE, PAIR_HL);
                   regalloc_dry_run_cost++;
                 }
               else
@@ -3194,13 +3715,35 @@
           i++;
           continue;
         }
+  
+      int source_fp_offset = source->aopu.aop_stk + soffset + i + (source->aopu.aop_stk > 0 ? _G.stack.param_offset : 0);
+      int source_sp_offset = source_fp_offset + _G.stack.pushed + _G.stack.offset;
+      int result_fp_offset = result->aopu.aop_stk + roffset + i + (result->aopu.aop_stk > 0 ? _G.stack.param_offset : 0);
+      int result_sp_offset = result_fp_offset + _G.stack.pushed + _G.stack.offset;
+        
+      if (result_fp_offset == source_fp_offset && !regalloc_dry_run) // Stack locations can change, so in dry run do not assume stack coalescing will happen.
+        {
+          assigned[i] = true;
+          i++;
+          continue;
+        }
 
-      if (i + 1 < n && !assigned[i + 1] && hl_free && (IS_RAB || IS_EZ80_Z80 || IS_TLCS90))
+      bool source_sp = IS_RAB && source_sp_offset <= 255 || IS_TLCS90 && source_sp_offset <= 127;
+      bool result_sp = IS_RAB && result_sp_offset <= 255 || IS_TLCS90 && result_sp_offset <= 127;
+      if (i + 1 < n && !assigned[i + 1] && hl_free && (IS_RAB || IS_EZ80_Z80 || IS_TLCS90) && // Todo: For Rabbit, use ld hl n (sp) and ld n(sp), hl when sp_offset is <= 255.
+        (result->type == AOP_STK && result_fp_offset >= -128 && result_fp_offset <= 127 || result_sp) &&
+        (source->type == AOP_STK && source_fp_offset >= -128 && source_fp_offset <= 127 || source_sp))
         {
           if (!regalloc_dry_run)
             {
-              emit2 ("ld hl, %s", aopGet (source, soffset + i, false));
-              emit2 ("ld %s, hl", aopGet (result, roffset + i, false));
+              if (source_sp)
+                emit2 ("ld hl, %d (sp)", source_sp_offset);
+              else
+                emit2 ("ld hl, %s", aopGet (source, soffset + i, false));
+              if (result_sp)
+                emit2 ("ld %d (sp), hl", result_sp_offset);
+              else
+                emit2 ("ld %s, hl", aopGet (result, roffset + i, false));
             }
           cost2 (6 - 2 * IS_RAB, 0, 0, 22, 0, 21, 10);
 
@@ -3215,7 +3758,11 @@
 
       if (a_free || really_do_it_now)
         {
+          if ((requiresHL (result)  || requiresHL (source)) && !hl_free)
+            _push (PAIR_HL);
           cheapMove (result, roffset + i, source, soffset + i, a_free);
+          if ((requiresHL (result)  || requiresHL (source)) && !hl_free)
+            _pop (PAIR_HL);
           assigned[i] = true;
           (*size)--;
           i++;
@@ -3232,7 +3779,7 @@
 /* genCopy - Copy the value from one reg/stk asmop to another      */
 /*-----------------------------------------------------------------*/
 static void
-genCopy (asmop *result, int roffset, asmop *source, int soffset, int sizex, bool a_dead, bool hl_dead)
+genCopy (asmop *result, int roffset, asmop *source, int soffset, int sizex, bool a_dead, bool hl_dead, bool de_dead)
 {
   int regsize, size, n = (sizex < source->size - soffset) ? sizex : (source->size - soffset);
   bool assigned[8] = {false, false, false, false, false, false, false, false};
@@ -3243,6 +3790,10 @@
   wassertl_bt (n <= 8, "Invalid size for genCopy().");
   wassertl_bt (aopRS (source), "Invalid source type.");
   wassertl_bt (aopRS (result), "Invalid result type.");
+  
+  a_dead |= (result->regs[A_IDX] >= roffset && result->regs[A_IDX] < roffset + sizex);
+  hl_dead |= (result->regs[L_IDX] >= roffset && result->regs[L_IDX] < roffset + sizex && result->regs[H_IDX] >= roffset && result->regs[H_IDX] < roffset + sizex);
+  de_dead |= (result->regs[E_IDX] >= roffset && result->regs[E_IDX] < roffset + sizex && result->regs[D_IDX] >= roffset && result->regs[D_IDX] < roffset + sizex);
 
   size = n;
   regsize = 0;
@@ -3257,16 +3808,37 @@
         regsize--;
         size--;
       }
-
+  
   // Move everything from registers to the stack.
   for (int i = 0; i < n;)
     {
-      if (i + 1 < n && result->type == AOP_STK &&
-        (aopInReg (source, soffset + i, HL_IDX) && IS_RAB ||
-        (aopInReg (source, soffset + i, BC_IDX) || aopInReg (source, soffset + i, DE_IDX) || aopInReg (source, soffset + i, HL_IDX) || aopInReg (source, soffset + i, IY_IDX)) && (IS_EZ80_Z80 || IS_TLCS90)))
+      bool a_free = a_dead && (source->regs[A_IDX] < 0 || assigned[source->regs[A_IDX] - soffset] || i == source->regs[A_IDX] - soffset);
+      bool hl_free = hl_dead && (source->regs[L_IDX] < 0 || assigned[source->regs[L_IDX] - soffset] || i == source->regs[L_IDX] - soffset) && (source->regs[H_IDX] < 0 || assigned[source->regs[H_IDX] - soffset] || i == source->regs[H_IDX] - soffset);
+      bool de_free = de_dead && (source->regs[E_IDX] < 0 || assigned[source->regs[E_IDX] - soffset] || i == source->regs[E_IDX] - soffset) && (source->regs[D_IDX] < 0 || assigned[source->regs[D_IDX] - soffset] || i == source->regs[D_IDX] - soffset);
+
+      int fp_offset = result->aopu.aop_stk + (result->aopu.aop_stk > 0 ? _G.stack.param_offset : 0) + roffset + i;
+      int sp_offset = fp_offset + _G.stack.pushed + _G.stack.offset;
+
+      if (!IS_SM83 && !IS_RAB && !(IS_TLCS90 && optimize.codeSpeed) && // The sm83 doesn't have ex (sp), hl. The Rabbits and tlcs90 have it, but ld 0 (sp), hl is faster. For the Rabbits, they are also the same size.
+        i + 1 < n && aopOnStack (result, roffset + i, 2) && !sp_offset &&
+        aopInReg (source, soffset + i, HL_IDX) && hl_dead && // If we knew that iy was dead, we could also use ex (sp), iy here.
+        !regalloc_dry_run) // Stack positions will change, so do not assume this is possible in the cost function.
+        {
+          emit2 ("ex (sp), hl");
+          cost2 (1 + IS_RAB, 19, 16, 15, 0, 14, 5);
+          spillPair (PAIR_HL);
+          assigned[i] = true;
+          assigned[i + 1] = true;
+          regsize -= 2;
+          size -= 2;
+          i += 2;        
+        }
+      else if (i + 1 < n && aopOnStack (result, roffset + i, 2) && (abs(fp_offset) <= 127 && !_G.omitFramePtr || IS_RAB && sp_offset <= 255 || IS_TLCS90 && sp_offset <= 127) &&
+        ((aopInReg (source, soffset + i, HL_IDX) || aopInReg (source, soffset + i, IY_IDX)) && IS_RAB || (getPairId_o (source, soffset + i) != PAIR_INVALID && (IS_EZ80_Z80 || IS_TLCS90))))
         {
+          bool use_sp = IS_RAB && sp_offset <= 255 || IS_TLCS90 && sp_offset <= 127;
           if (!regalloc_dry_run)
-            emit2 ("ld %s, %s", aopGet (result, roffset + i, false), _pairs[getPairId_o (source, soffset + i)].name);
+            emit2 ("ld %d %s, %s", use_sp ? sp_offset : fp_offset, use_sp ? "(sp)" : "(ix)", _pairs[getPairId_o (source, soffset + i)].name);
           cost2 (3 - IS_RAB, 0, 0, 11, 0, 12, 5);
           assigned[i] = true;
           assigned[i + 1] = true;
@@ -3274,9 +3846,80 @@
           size -= 2;
           i += 2;
         }
+      else if (IS_RAB && i + 1 < n && aopOnStack (result, roffset + i, 2) && aopInReg (source, soffset + i, IY_IDX) &&
+        sp_offset <= 255)
+        {
+          emit2 ("ld %d (sp), iy", sp_offset);
+          cost2 (3, 0, 0, 13, 0, 0, 0);
+          assigned[i] = true;
+          assigned[i + 1] = true;
+          regsize -= 2;
+          size -= 2;
+          i += 2;         
+        }
+      else if (i + 1 < n && aopOnStack (result, roffset + i, 2) && getPairId_o (source, soffset + i) != PAIR_INVALID && !sp_offset && !regalloc_dry_run) // Stack positions will change, so do not assume this is possible in the cost function.
+        {
+          bool iy = aopInReg (source, soffset + i, IY_IDX);
+          emit2 ("inc sp");
+          emit2 ("inc sp");
+          emit2 ("push %s", _pairs[getPairId_o (source, soffset + i)].name);
+          cost2 (3 + iy, 23 + 4 * iy, 19 + 3 * iy, 14 + 2 * iy, 32, 16, 5 + iy);
+          assigned[i] = true;
+          assigned[i + 1] = true;
+          regsize -= 2;
+          size -= 2;
+          i += 2;  
+        }
+      else if (IS_RAB && i + 1 < n && aopOnStack (result, roffset + i, 2) && aopInReg (source, soffset + i, DE_IDX) &&
+        (sp_offset <= 255 || abs(fp_offset) <= 127 && !_G.omitFramePtr))
+        {
+          bool use_sp = (sp_offset <= 255);
+          emit2 ("ex de, hl");
+          if (!regalloc_dry_run)
+            emit2 ("ld %d %s, hl", use_sp ? sp_offset : fp_offset, use_sp ? "(sp)" : "(ix)");
+          cost2 (3, 0, 0, 13, 0, 0, 0);
+          if (!de_dead || !hl_dead || source->regs[L_IDX] >= 0 && !assigned[source->regs[L_IDX]] || source->regs[H_IDX] >= 0 && !assigned[source->regs[H_IDX]])
+            {
+              emit2 ("ex de, hl");
+              cost2 (1, 0, 0, 2, 0, 0, 0);
+            }
+          spillPair (PAIR_HL);
+          assigned[i] = true;
+          assigned[i + 1] = true;
+          regsize -= 2;
+          size -= 2;
+          i += 2;
+        }
+      else if (!IS_SM83 && i + 1 < n && aopOnStack (result, roffset + i, 2) && requiresHL (result) &&
+        aopInReg (source, soffset + i, HL_IDX) && hl_free)
+        {
+          if (!de_free)
+            _push (PAIR_DE);
+          emit2 ("ex de, hl");
+          cost2 (1, 4, 3, 2, 0, 2, 1);
+          spillPair (PAIR_HL);
+          genCopy (result, roffset + i, ASMOP_DE, 0, 2, a_free, true, true);
+          if (!de_free)
+            _pop (PAIR_DE);
+          assigned[i] = true;
+          assigned[i + 1] = true;
+          regsize -= 2;
+          size -= 2;
+          i += 2;
+        }
+      else if (aopOnStack (result, roffset + i, 1) && requiresHL (result) && !hl_free)
+        {
+          _push(PAIR_HL);
+          cheapMove (result, roffset + i, source, soffset + i, a_free);
+          _pop(PAIR_HL);
+          assigned[i] = true;
+          regsize--;
+          size--;
+          i++;
+        }
       else if (aopRS (source) && !aopOnStack (source, soffset + i, 1) && aopOnStack (result, roffset + i, 1))
         {
-          cheapMove (result, roffset + i, source, soffset + i, true);
+          cheapMove (result, roffset + i, source, soffset + i, a_free);
           assigned[i] = true;
           regsize--;
           size--;
@@ -3308,13 +3951,14 @@
       if (aopInReg (operand, offset, A_IDX))
         a_free = false;
       else if (aopInReg (operand, offset, L_IDX) || aopInReg (operand, offset, H_IDX))
-        hl_free = FALSE;
+        hl_free = false;
     }
   genCopyStack (result, roffset, source, soffset, n, assigned, &size, a_free, hl_free, false);
 
   // Now do the register shuffling.
 
   // Try to use:
+  // Rabbits: ld hl, iy; ld iy, hl
   // TLCS-90 ld rr, rr
   // eZ80 lea rr, iy.
   // All: push rr / pop iy
@@ -3331,15 +3975,20 @@
             goto skip_byte_push_iy; // We can't write this one without overwriting the source.
         }
 
-      if (IS_TLCS90 && getPairId_o (result, roffset + i) != PAIR_INVALID && getPairId_o (source, soffset + i) != PAIR_INVALID)
+      if (IS_RAB && (getPairId_o (result, roffset + i) == PAIR_HL || getPairId_o (result, roffset + i) == PAIR_IY) && (getPairId_o (source, soffset + i) == PAIR_HL || getPairId_o (source, soffset + i) == PAIR_IY))
+        {
+          emit2 ("ld %s, %s", _pairs[getPairId_o (result, roffset + i)].name, _pairs[getPairId_o (source, soffset + i)].name);
+          cost (2, 4);
+        }
+      else if (IS_TLCS90 && getPairId_o (result, roffset + i) != PAIR_INVALID && getPairId_o (source, soffset + i) != PAIR_INVALID)
         {
           emit2 ("ld %s, %s", _pairs[getPairId_o (result, roffset + i)].name, _pairs[getPairId_o (source, soffset + i)].name);
           regalloc_dry_run_cost += 1 + (!aopInReg (result, roffset + i, HL_IDX) && !aopInReg (source, soffset + i, HL_IDX));
         }
       else if (IS_EZ80_Z80 && getPairId_o (result, roffset + i) != PAIR_INVALID && aopInReg (source, soffset + i, IY_IDX))
         {
-          emit2 ("lea %s, iy, #0", _pairs[getPairId_o (result, roffset + i)].name);
-          regalloc_dry_run_cost += 3;
+          emit2 ("lea %s, iy, !zero", _pairs[getPairId_o (result, roffset + i)].name);
+          cost (3, 3);
         }
       else if (aopInReg (result, roffset + i, IY_IDX) && getPairId_o (source, soffset + i) != PAIR_INVALID ||
         getPairId_o (result, roffset + i) != PAIR_INVALID && aopInReg (source, soffset + i, IY_IDX))
@@ -3360,30 +4009,47 @@
         ;
     }
 
-  // Try to use ex de, hl. TODO: Also do so when only some bytes are used, while others are dead (useful e.g. for emulating ld de, hl or ld hl, de).
-  if (regsize >= 4)
+  if (!IS_SM83)
     {
-      int ex[4] = {-2, -2, -2, -2};
+      int ex[4] = {-2, -2, -2, -2}; // Swapped bytes
+      bool no = false; // Still needed byte would be overwritten
 
       // Find L and check that it is exchanged with E, find H and check that it is exchanged with D.
       for (int i = 0; i < n; i++)
         {
-          if (!assigned[i] && aopInReg (result, roffset + i, L_IDX) && aopInReg (source, soffset + i, E_IDX))
-            ex[0] = i;
-          if (!assigned[i] && aopInReg (result, roffset + i, E_IDX) && aopInReg (source, soffset + i, L_IDX))
-            ex[1] = i;
-          if (!assigned[i] && aopInReg (result, roffset + i, H_IDX) && aopInReg (source, soffset + i, D_IDX))
-            ex[2] = i;
-          if (!assigned[i] && aopInReg (result, roffset + i, D_IDX) && aopInReg (source, soffset + i, H_IDX))
-            ex[3] = i;
+          if (assigned[i] &&
+            (aopInReg (result, roffset + i, E_IDX) || aopInReg (result, roffset + i, L_IDX) || aopInReg (result, roffset + i, D_IDX) || aopInReg (result, roffset + i, H_IDX)))
+            no = true;
+       
+          if (!assigned[i] && aopInReg (source, soffset + i, E_IDX))
+            if (aopInReg (result, roffset + i, L_IDX))
+              ex[0] = i;
+            else
+              no = true;
+          if (!assigned[i] && aopInReg (source, soffset + i, L_IDX))
+            if (aopInReg (result, roffset + i, E_IDX))
+              ex[1] = i;
+            else
+              no = true;
+          if (!assigned[i] && aopInReg (source, soffset + i, D_IDX))
+            if (aopInReg (result, roffset + i, H_IDX))
+              ex[2] = i;
+            else
+              no = true;
+          if (!assigned[i] && aopInReg (source, soffset + i, H_IDX))
+            if (aopInReg (result, roffset + i, D_IDX))
+              ex[3] = i;
+            else
+              no = true; 
         }
 
       int exsum = (ex[0] >= 0) + (ex[1] >= 0) + (ex[2] >= 0) + (ex[3] >= 0);
 
-      if (exsum == 4)
+      if (!no && exsum >= 2 && hl_dead && de_dead)
         {
           emit2 ("ex de, hl");
-          regalloc_dry_run_cost += 1; // TODO: Use cost() to enable better optimization for speed.
+          swapPairs (PAIR_DE, PAIR_HL);
+          cost2 (1, 4, 3, 2, 0, 2, 1);
           if(ex[0] >= 0)
             assigned[ex[0]] = TRUE;
           if(ex[1] >= 0)
@@ -3443,7 +4109,7 @@
           break;
 
       wassertl_bt (i != n, "genCopy error: Trying to cache non-existant byte in accumulator.");
-      if (a_free && !pushed_a)
+      if (!a_free && !pushed_a)
         {
           _push (PAIR_AF);
           pushed_a = TRUE;
@@ -3469,16 +4135,154 @@
     }
   genCopyStack (result, roffset, source, soffset, n, assigned, &size, a_free, hl_free, false);
 
-  // Last, move everything from stack to registers.
+  // Take de from stack first on Rabbit, while hl is still free, so we can do with just one ex de, hl.
+  if (IS_RAB && hl_free &&
+    result->regs[E_IDX] > roffset && result->regs[E_IDX] < roffset + n && !assigned[result->regs[E_IDX] - roffset] &&
+    result->regs[D_IDX] > roffset && result->regs[D_IDX] < roffset + n && !assigned[result->regs[D_IDX] - roffset] &&
+    result->regs[E_IDX] + 1 == result->regs[D_IDX])
+    {
+      int i = result->regs[E_IDX] - roffset;
+      const int fp_offset = source->aopu.aop_stk + soffset + i + (source->aopu.aop_stk > 0 ? _G.stack.param_offset : 0);
+      const int sp_offset = fp_offset + _G.stack.pushed + _G.stack.offset;     
+      if (sp_offset <= 255 || fp_offset <= 127)
+        {
+          if (!regalloc_dry_run)
+            if (sp_offset <= 255)
+              emit2 ("ld hl, %d (sp)", sp_offset);
+            else
+              emit2 ("ld hl, %s", aopGet (source, soffset + i, false));
+          emit2 ("ex de, hl");
+          regalloc_dry_run_cost += 3;
+          spillPair (PAIR_HL);
+          spillPair (PAIR_DE);
+          assigned[i] = true;
+          assigned[i + 1] = true;
+          size -= 2;
+          i += 2;
+        }
+    }
+  
+  // Last, move everything else from stack to registers.
   for (int i = 0; i < n;)
     {
-      if (i + 1 < n && source->type == AOP_STK &&
+      const int fp_offset = source->aopu.aop_stk + soffset + i + (source->aopu.aop_stk > 0 ? _G.stack.param_offset : 0);
+      const int sp_offset = fp_offset + _G.stack.pushed + _G.stack.offset;
+
+      bool a_free = a_dead && (result->regs[A_IDX] < 0 || !assigned[result->regs[A_IDX] - roffset]);
+      const bool hl_free = hl_dead && (result->regs[L_IDX] < 0 || !assigned[result->regs[L_IDX] - roffset]) && (result->regs[H_IDX] < 0 || !assigned[result->regs[H_IDX] - roffset]);
+      const bool e_free = de_dead && (result->regs[E_IDX] < 0 || !assigned[result->regs[E_IDX] - roffset]);
+      const bool d_free = de_dead && (result->regs[D_IDX] < 0 || !assigned[result->regs[D_IDX] - roffset]);
+      const bool de_free = e_free && d_free;
+ 
+      if (assigned[i])
+        {
+          i++;
+          continue;
+        }
+      else if (i + 1 < n && !assigned[i + 1] && (source->type == AOP_STK || source->type == AOP_EXSTK) &&
+        (IS_RAB && sp_offset <= 255 || IS_TLCS90 && sp_offset <= 127) &&
+        (aopInReg (result, roffset + i, HL_IDX) || aopInReg (result, roffset + i, IY_IDX)))
+        {
+          if (!regalloc_dry_run)
+            emit2 ("ld %s, %d (sp)", _pairs[getPairId_o (result, roffset + i)].name, sp_offset);
+          spillPair (getPairId_o (result, roffset + i));
+          cost2 (3 - IS_RAB, 0, 0, 11, 0, 12, 0);
+          assigned[i] = true;
+          assigned[i + 1] = true;
+          size -= 2;
+          i += 2;
+        }
+      else if (i + 1 < n && !assigned[i + 1] && source->type == AOP_STK &&
         (aopInReg (result, roffset + i, HL_IDX) && IS_RAB ||
         (aopInReg (result, roffset + i, BC_IDX) || aopInReg (result, roffset + i, DE_IDX) || aopInReg (result, roffset + i, HL_IDX) || aopInReg (result, roffset + i, IY_IDX)) && (IS_EZ80_Z80 || IS_TLCS90)))
         {
           if (!regalloc_dry_run)
             emit2 ("ld %s, %s", _pairs[getPairId_o (result, roffset + i)].name, aopGet (source, soffset + i, false));
-          cost2 (3 - IS_RAB, 0, 0, 11, 0, 9, 5);
+          spillPair (getPairId_o (result, roffset + i));
+          cost2 (3 - IS_RAB, 0, 0, 11, 0, 12, 5);
+          assigned[i] = true;
+          assigned[i + 1] = true;
+          size -= 2;
+          i += 2;
+        }
+      else if (i + 1 < n && !assigned[i + 1] && (source->type == AOP_STK || source->type == AOP_EXSTK) &&
+        !sp_offset && getPairId_o (result, roffset + i) != PAIR_INVALID &&
+        !regalloc_dry_run) // Stack locations might change.
+        {
+          PAIR_ID pair = getPairId_o (result, roffset + i);
+          _pop (pair);
+          _push (pair);
+          assigned[i] = true;
+          assigned[i + 1] = true;
+          size -= 2;
+          i += 2;
+        }
+      else if (i + 1 < n && !assigned[i + 1] && (source->type == AOP_STK || source->type == AOP_EXSTK) &&
+        sp_offset == 2 && getPairId_o (result, roffset + i) != PAIR_INVALID &&
+        (getPairId_o (result, roffset + i) != PAIR_HL && hl_free || getPairId_o (result, roffset + i) != PAIR_DE && de_free) &&
+        (!regalloc_dry_run || source->aopu.aop_stk > 0) &&  // Stack locations might change, unless its a parameter.
+        !(IS_RAB && aopInReg (result, roffset + i, DE_IDX)) && // For de, Rabbit can do it faster at same code size using ex twice
+        (!IS_SM83 || optimize.codeSize) // SM83 can do it faster (worst case 2B bigger, but 1B smaller if lucky -> hl reuse)
+        && !optimize.codeSpeed) // A bit slower (42 vs 38 cycles on Z80 and Z80N), so don't do it when optimizing for speed.
+        {
+          PAIR_ID pair = getPairId_o (result, roffset + i);
+          PAIR_ID extrapair = (getPairId_o (result, roffset + i) != PAIR_HL && hl_free) ? PAIR_HL : PAIR_DE; // If we knew it is dead, we could use bc as extrapair here, too.
+          _pop (extrapair);
+          _pop (pair);
+          _push (pair);
+          _push (extrapair);
+          spillPair (extrapair);
+          assigned[i] = true;
+          assigned[i + 1] = true;
+          size -= 2;
+          i += 2;
+        }
+      else if (i + 1 < n && !assigned[i + 1] &&
+        (source->type == AOP_STK && fp_offset <= 127 || sp_offset <= 255) &&
+        (aopInReg (result, roffset + i, DE_IDX) || result->type == AOP_REG && result->regs[L_IDX] < i && result->regs[IYL_IDX] < i && result->regs[H_IDX] < i && result->regs[IYH_IDX] < i && hl_free) &&
+        IS_RAB)
+        {
+          if (!hl_free)
+            emit2 ("ex de, hl");
+          if (!regalloc_dry_run)
+            if (sp_offset <= 255)
+              emit2 ("ld hl, %d (sp)", sp_offset);
+            else
+              emit2 ("ld hl, %s", aopGet (source, soffset + i, false));
+          cost2 (2 + !hl_free, 0, 0, 11 + !hl_free * 2, 0, 0, 0);
+          spillPair (PAIR_HL);
+          if (aopInReg (result, roffset + i, DE_IDX))
+            {
+              emit2 ("ex de, hl");
+              cost2 (1, 0, 0, 2, 0, 0, 0);
+            }
+          else
+            {
+              wassert (hl_free);
+              emit3_o (A_LD, result, roffset + i, ASMOP_L, 0);
+              emit3_o (A_LD, result, roffset + i + 1, ASMOP_H, 0);
+            }
+          assigned[i] = true;
+          assigned[i + 1] = true;
+          size -= 2;
+          i += 2;      
+        }
+      else if (i + 1 < n && !assigned[i + 1] && (source->type == AOP_STK || source->type == AOP_EXSTK) && requiresHL (source) &&
+        (aopInReg (result, roffset + i, HL_IDX) || aopInReg (result, roffset + i, H_IDX) && aopInReg (result, roffset + i + 1, L_IDX))) // Stack access might go through hl.
+        {
+          bool a_pushed = false;
+          if (!a_free && !e_free && !d_free)
+            {
+              _push (PAIR_AF);
+              a_pushed = true;
+              a_free = true;
+            }
+          asmop *tmpaop = a_free ? ASMOP_A : e_free ? ASMOP_E : ASMOP_D;
+          cheapMove (tmpaop, 0, source, soffset + i, true);
+          cheapMove (result, roffset + i + 1, source, soffset + i + 1, false);
+          cheapMove (result, roffset + i, tmpaop, 0, true);
+          if (a_pushed)
+            _pop (PAIR_AF);
           assigned[i] = true;
           assigned[i + 1] = true;
           size -= 2;
@@ -3486,7 +4290,25 @@
         }
       else if (aopRS (result) && aopOnStack (source, soffset + i, 1) && !aopOnStack (result, roffset + i, 1))
         {
-          cheapMove (result, roffset + i, source, soffset + i, true);
+          if (requiresHL (source) && !hl_free && (aopInReg (result, roffset + i, L_IDX) || aopInReg (result, roffset + i, H_IDX)))
+            {
+              if (!a_free)
+                _push (PAIR_AF);
+              _push (PAIR_HL);
+              cheapMove (ASMOP_A, 0, source, soffset + i, true);
+              _pop (PAIR_HL);
+              cheapMove (result, roffset + i, ASMOP_A, 0, true);
+              if (!a_free)
+                _pop (PAIR_AF);
+            }
+          else
+            {
+              if (requiresHL (source) && !hl_free)
+                _push (PAIR_HL);
+              cheapMove (result, roffset + i, source, soffset + i, a_free);
+              if (requiresHL (source) && source->type != AOP_REG && !hl_free)
+                _pop (PAIR_HL);
+              }
           assigned[i] = true;
           size--;
           i++;
@@ -3499,7 +4321,7 @@
   if (size)
     {
       a_free = a_dead && (result->regs[A_IDX] < 0 || result->regs[A_IDX] >= roffset + source->size);
-      hl_free = a_dead && (result->regs[L_IDX] < 0 || result->regs[L_IDX] >= roffset + source->size) && (result->regs[H_IDX] < 0 || result->regs[H_IDX] >= roffset + source->size);
+      hl_free = hl_dead && (result->regs[L_IDX] < 0 || result->regs[L_IDX] >= roffset + source->size) && (result->regs[H_IDX] < 0 || result->regs[H_IDX] >= roffset + source->size);
       if (!a_free)
         _push (PAIR_AF);
       genCopyStack (result, roffset, source, soffset, n, assigned, &size, true, hl_free, true);
@@ -3526,31 +4348,107 @@
 /* genMove_o - Copy part of one asmop to another                   */
 /*-----------------------------------------------------------------*/
 static void
-genMove_o (asmop *result, int roffset, asmop *source, int soffset, int size, bool a_dead_global, bool hl_dead_global)
+genMove_o (asmop *result, int roffset, asmop *source, int soffset, int size, bool a_dead_global, bool hl_dead_global, bool de_dead_global, bool iy_dead_global, bool f_dead)
 {
   emitDebug ("; genMove_o");
+  wassert (result->size >= roffset + size);
 
-  if ((result->type == AOP_REG || !IS_GB && result->type == AOP_STK) && (source->type == AOP_REG || !IS_GB && source->type == AOP_STK))
+  if (aopSame (result, roffset, source, soffset, size))
+    return;
+
+  if ((result->type == AOP_REG || result->type == AOP_STK || result->type == AOP_EXSTK) && (source->type == AOP_REG || source->type == AOP_STK || source->type == AOP_EXSTK))
     {
       int csize = size > source->size - soffset ? source->size - soffset : size;
-      genCopy (result, roffset, source, soffset, csize, a_dead_global, hl_dead_global);
+      genCopy (result, roffset, source, soffset, csize, a_dead_global, hl_dead_global, de_dead_global);
       roffset += csize;
       size -= csize;
-      genMove_o (result, roffset, ASMOP_ZERO, 0, size, a_dead_global && result->regs[A_IDX] < roffset, hl_dead_global && result->regs[H_IDX] < roffset && result->regs[L_IDX] < roffset);
+      bool a_dead = a_dead_global && result->regs[A_IDX] < roffset;
+      bool hl_dead = hl_dead_global && result->regs[H_IDX] < roffset && result->regs[L_IDX] < roffset;
+      bool de_dead = de_dead_global && result->regs[D_IDX] < roffset && result->regs[E_IDX] < roffset;
+      bool iy_dead = iy_dead_global && result->regs[IYH_IDX] < roffset && result->regs[IYL_IDX] < roffset;
+      genMove_o (result, roffset, ASMOP_ZERO, 0, size, a_dead, hl_dead, de_dead, iy_dead, f_dead);
       return;
     }
 
   bool zeroed_a = false;
   long value_hl = -1;
-  bool a_dead = a_dead_global;
-  bool hl_dead = hl_dead_global;
-  for (unsigned int i = 0; i < size;)
+
+  for (int i = 0; i < size;)
     {
+      bool a_dead = a_dead_global && source->regs[A_IDX] <= i && (result->regs[A_IDX] < 0 || result->regs[A_IDX] >= i);
+      bool hl_dead = hl_dead_global && source->regs[L_IDX] <= i && source->regs[H_IDX] <= i && (result->regs[L_IDX] < 0 || result->regs[L_IDX] >= i) && (result->regs[H_IDX] < 0 || result->regs[H_IDX] >= i);
+      bool iy_dead = iy_dead_global && source->regs[IYL_IDX] <= i && source->regs[IYH_IDX] <= i && (result->regs[IYL_IDX] < 0 || result->regs[IYL_IDX] >= i) && (result->regs[IYH_IDX] < 0 || result->regs[IYH_IDX] >= i);
+
+      if (source->type == AOP_STL && (soffset + i) >= 2)
+        {
+          genMove_o (result, roffset + i, ASMOP_ZERO, 0, size - i, a_dead, hl_dead, false, iy_dead, f_dead);
+          return;
+        }
+      else if (IS_EZ80_Z80 && source->type == AOP_STL && !(soffset + i) && getPairId_o(result, roffset) != PAIR_INVALID &&
+        !_G.omitFramePtr && abs(fpOffset (source->aopu.aop_stk)) <= 127)
+        {
+          emit2 ("lea %s, ix, !immed%d", _pairs[getPairId_o(result, roffset)].name, fpOffset (source->aopu.aop_stk));
+          spillPair (getPairId_o(result, roffset));
+          regalloc_dry_run_cost += 3;
+          i += 2;
+          continue;
+        }
+      else if (source->type == AOP_STL && !(soffset + i) && getPairId_o(result, roffset) == PAIR_IY)
+        {
+          if (!f_dead)
+            _push (PAIR_AF);
+          emit2 ("ld iy, !immed%d", spOffset (source->aopu.aop_stk));
+          emit2 ("add iy, sp");
+          if (!f_dead)
+            _pop (PAIR_AF);
+          spillPair (PAIR_IY);
+          regalloc_dry_run_cost += 6 + 2 * !f_dead;
+          i += 2;
+          continue;
+        }
+      else if (!IS_SM83 && source->type == AOP_STL && !(soffset + i) && size == 2 && getPairId_o(result, roffset) == PAIR_DE) // For result in de, we don't need hl dead.
+        {
+          if (!hl_dead)
+            {
+              emit2 ("ex de, hl");
+              regalloc_dry_run_cost++;
+            }
+          else
+            spillPair (PAIR_HL);
+          if (!f_dead)
+            _push (PAIR_AF);
+          emit2 ("ld hl, !immed%d", spOffset (source->aopu.aop_stk));
+          emit2 ("add hl, sp");
+          if (!f_dead)
+            _pop (PAIR_AF);
+          emit2 ("ex de, hl");
+          regalloc_dry_run_cost += 5 + 2 * !f_dead;;
+          spillPair (PAIR_DE);
+          i += 2;
+          continue;
+        }
+      else if (source->type == AOP_STL)
+        {
+          if (i || soffset || !hl_dead)
+            UNIMPLEMENTED;
+          if (!f_dead)
+            _push (PAIR_AF);
+          emit2 ("ld hl, !immed%d", spOffset (source->aopu.aop_stk));
+          emit2 ("add hl, sp");
+          if (!f_dead)
+            _pop (PAIR_AF);
+          regalloc_dry_run_cost += 4 + 2 * !f_dead;;
+          spillPair (PAIR_HL);
+          genMove_o (result, roffset, ASMOP_HL, 0, size, a_dead, true, de_dead_global, iy_dead, f_dead);
+          i += 2;
+          continue;
+        }
+
       if ((IS_EZ80_Z80 || IS_RAB || IS_TLCS90) && i + 1 < size && result->type == AOP_STK &&
         source->type == AOP_LIT && (value_hl >= 0 && aopIsLitVal (source, soffset + i, 2, value_hl) || hl_dead))
         {
           if (value_hl < 0 || !aopIsLitVal (source, soffset + i, 2, value_hl))
-            fetchLitPair (PAIR_HL, source, soffset + i);
+            fetchLitPair (PAIR_HL, source, soffset + i, f_dead);
           if (!regalloc_dry_run)
             emit2 ("ld %s, hl", aopGet (result, roffset + i, false));
           cost2 (3 - IS_RAB, 0, 0, 11, 0, 12, 5);
@@ -3559,28 +4457,68 @@
           i += 2;
           continue;
         }
+      else if (i + 1 < size && IS_SM83 && result->type != AOP_REG && requiresHL (result) && source->type == AOP_REG && requiresHL (source) && // word through de is cheaper than direct byte-by-byte, since it requires fewer updates of hl.
+        de_dead_global && source->regs[E_IDX] <= i + 1 && source->regs[D_IDX] <= i + 1 &&
+        hl_dead_global && source->regs[L_IDX] <= i + 1 && source->regs[H_IDX] <= i + 1)
+        {
+          cheapMove (ASMOP_E, 0, source, i, a_dead);
+          cheapMove (ASMOP_D, 0, source, i + 1, a_dead);
+          cheapMove (result, i, ASMOP_E, 0, a_dead);
+          cheapMove (result, i + 1, ASMOP_D, 0, a_dead);
+          i += 2;
+          continue;
+        }
+      else if (!IS_SM83 && i + 1 < size && getPairId_o(source, soffset + i) != PAIR_INVALID &&
+        (result->type == AOP_IY || result->type == AOP_DIR || result->type == AOP_HL && (getPairId_o(source, soffset + i) == PAIR_HL || !hl_dead)))
+        {
+          emit2 ("ld !mems, %s", aopGetLitWordLong (result, roffset + i, false), _pairs[getPairId_o(source, soffset + i)].name);
+          regalloc_dry_run_cost += 3 + (getPairId_o(source, soffset + i) != PAIR_HL);
+          i += 2;
+          continue;
+        }
+      else if (!IS_SM83 && i + 1 < size && soffset + i + 1 < source->size && getPairId_o(result, roffset + i) != PAIR_INVALID &&
+        (source->type == AOP_IY || source->type == AOP_DIR || source->type == AOP_HL && (getPairId_o(result, roffset + i) == PAIR_HL || !hl_dead)))
+        {
+          emit2 ("ld %s, !mems", _pairs[getPairId_o(result, roffset + i)].name, aopGetLitWordLong (source, soffset + i, false));
+          regalloc_dry_run_cost += 3 + (getPairId_o(result, roffset + i) != PAIR_HL);
+          spillPair (getPairId_o(result, roffset + i));
+          i += 2;
+          continue;      
+        }
+      else if (i + 1 < size && getPairId_o(result, roffset + i) != PAIR_INVALID &&
+        (source->type == AOP_LIT && !(aopIsLitVal (source, soffset + i, 2, 0x0000) && zeroed_a) || source->type == AOP_IMMD))
+        {
+          fetchLitPair (getPairId_o(result, roffset + i), source, soffset + i, f_dead);
+          i += 2;
+          continue;
+        }
 
       // Cache a copy of zero in a.
-      if (result->type != AOP_REG && aopIsLitVal (source, soffset + i, 2, 0x0000) && !zeroed_a && a_dead)
+      if (size > 1 && result->type != AOP_REG && aopIsLitVal (source, soffset + i, 2, 0x0000) && !zeroed_a && a_dead && source->regs[A_IDX] <= i && f_dead)
         {
           emit3 (A_XOR, ASMOP_A, ASMOP_A);
           regalloc_dry_run_cost += 1;
           zeroed_a = true;
         }
 
-      if (result->type == AOP_HL && a_dead_global && (!hl_dead_global || source->regs[L_IDX] != -1 || source->regs[H_IDX] != -1))
+      if (result->type == AOP_HL && a_dead_global && (!hl_dead_global || source->regs[L_IDX] >= i || source->regs[H_IDX] >= i) && source->regs[A_IDX] <= i)
         {
-          if (!aopIsLitVal (source, soffset + i, 1, 0x00) || !zeroed_a)
+          if (source->type == AOP_HL)
+            {
+              emit2 ("ld a, !mems", aopGetLitWordLong (source, soffset + i, FALSE));
+              regalloc_dry_run_cost += 3;
+            }
+          else if (!aopIsLitVal (source, soffset + i, 1, 0x00) || !zeroed_a)
             {
               cheapMove (ASMOP_A, 0, source, soffset + i, true);
               zeroed_a = aopIsLitVal (source, soffset + i, 1, 0x00);
             }
-          emit2 ("ld (%s), a", aopGetLitWordLong (result, roffset + i, FALSE));
+          emit2 ("ld !mems, a", aopGetLitWordLong (result, roffset + i, FALSE));
           regalloc_dry_run_cost += 3;
         }
       else if (aopIsLitVal (source, soffset + i, 1, 0x00) && zeroed_a)
         cheapMove (result, roffset + i, ASMOP_A, 0, false);
-      else if (aopIsLitVal (source, soffset + i, 1, 0x00) && aopInReg (result, roffset + i, A_IDX))
+      else if (aopIsLitVal (source, soffset + i, 1, 0x00) && aopInReg (result, roffset + i, A_IDX) && f_dead)
         {
           emit3 (A_XOR, ASMOP_A, ASMOP_A);
           regalloc_dry_run_cost += 1;
@@ -3588,15 +4526,69 @@
         }
       else
         {
-          cheapMove (result, roffset + i, source, soffset + i, a_dead_global);
+          bool pushed_hl = false;
+          bool via_a = false;
+          bool premoved_a = false;
+          if ((requiresHL (result) && result->type != AOP_REG || requiresHL (source) && source->type != AOP_REG) && !hl_dead)
+            {
+              via_a = aopInReg (result, roffset + i, L_IDX) || aopInReg (result, roffset + i, H_IDX);
+              if (via_a && !a_dead)
+                _push (PAIR_AF);
+              if (via_a && source->type == AOP_HL)
+                {
+                  emit2 ("ld a, !mems", aopGetLitWordLong (source, soffset + i, FALSE));
+                  regalloc_dry_run_cost += 3;
+                  premoved_a = true;
+                }
+              else
+                {
+                  _push (PAIR_HL);
+                  pushed_hl = true;
+                }
+            }
+          else if (result->type == AOP_IY && !iy_dead && !aopInReg (source, soffset + i, A_IDX))
+            {
+              via_a = true;
+              if (!a_dead)
+                _push (PAIR_AF);
+            }
+          else if (!premoved_a && source->type == AOP_IY && result->type == AOP_REG && a_dead && i == 0 && i + 1 == size) // Using free a is cheaper than using iy.
+            via_a = true;
+          if (!premoved_a)
+            {
+              bool save_iy = !iy_dead && source->type == AOP_IY && (result->type == AOP_REG && !via_a && !aopInReg (result, roffset + i, A_IDX));
+              if (save_iy)
+                _push (PAIR_IY);
+              cheapMove (via_a ? ASMOP_A : result, via_a ? 0 : (roffset + i), source, soffset + i, via_a || a_dead);
+              if (save_iy)
+                _pop (PAIR_IY);
+            }
+          if (pushed_hl)
+            _pop (PAIR_HL);
+          if (via_a)
+            {
+              if (requiresHL (result) && result->type != AOP_REG && !hl_dead)
+                {
+                  if (result->type == AOP_HL)
+                    {
+                      emit2 ("ld !mems, a", aopGetLitWordLong (result, roffset + i, FALSE));
+                      regalloc_dry_run_cost += 3;
+                    }
+                  else
+                    {
+                      _push (PAIR_HL);
+                      cheapMove (result, roffset + i, ASMOP_A, 0, true);
+                      _pop (PAIR_HL);
+                    }
+                }
+              else
+                cheapMove (result, roffset + i, ASMOP_A, 0, true);
+              if (!a_dead)
+                _pop (PAIR_AF);
+            }
           zeroed_a = false;
         }
 
-      if (aopInReg (result, roffset + i, A_IDX))
-        a_dead = false;
-      if (aopInReg (result, roffset + i, H_IDX) || aopInReg (result, roffset + i, L_IDX))
-        hl_dead = false;
-
       i++;
     }
 }
@@ -3605,9 +4597,9 @@
 /* genMove - Copy the value from one asmop to another              */
 /*-----------------------------------------------------------------*/
 static void
-genMove (asmop *result, asmop *source, bool a_dead, bool hl_dead)
+genMove (asmop *result, asmop *source, bool a_dead, bool hl_dead, bool de_dead, bool iy_dead)
 {
-  genMove_o (result, 0, source, 0, result->size, a_dead, hl_dead);
+  genMove_o (result, 0, source, 0, result->size, a_dead, hl_dead, de_dead, iy_dead, true);
 }
 
 /*-----------------------------------------------------------------*/
@@ -3617,7 +4609,7 @@
 getDataSize (operand * op)
 {
   int size;
-  size = AOP_SIZE (op);
+  size = op->aop->size;
   if (size == 3)
     {
       /* pointer */
@@ -3630,40 +4622,94 @@
 /* adjustStack - Adjust the stack pointer by n bytes.                       */
 /*--------------------------------------------------------------------------*/
 static void
-adjustStack (int n, bool af_free, bool bc_free, bool hl_free, bool iy_free)
+adjustStack (int n, bool af_free, bool bc_free, bool de_free, bool hl_free, bool iy_free)
 {
+  if(n != 0)
+    emitDebug("; adjustStack by %d", n);
   _G.stack.pushed -= n;
+  
+  iy_free &= !IS_SM83;
+
+  int loop_bytes, loop_cycles;
+  if (abs(n) > 0 && (IS_RAB || IS_SM83)) // Assume sequence of add sp, #d
+    {
+      loop_bytes = (abs(n) / 127 + 1) * 2;
+      loop_cycles = (abs(n) / 127 + 1) * (IS_RAB ? 4 : 16);
+    }
+  else if (n > 0 && (IS_Z80 || IS_Z80N || optimize.codeSize) && // Assume sequence of pop rr
+    (!IS_TLCS90 && af_free || bc_free || de_free || hl_free || IS_TLCS90 && iy_free)) 
+    {
+      loop_bytes = n / 2 + n % 2;
+      if (IS_RAB)
+        loop_cycles = n / 2 * 7 + n % 2 * 2;
+      else if (IS_SM83)
+        loop_cycles = n / 2 * 12 + n % 2 * 8;
+      else // Z80
+        loop_cycles = n / 2 * 10 + n % 2 * 6;
+    }
+  else // Assume sequence of inc / dec sp
+    {
+      loop_bytes = abs(n);
+      if (IS_RAB)
+        loop_cycles = abs(n) * 2;
+      else if (IS_SM83)
+        loop_cycles = abs(n) * 8;
+      else // Z80
+        loop_cycles = abs(n) * 6;
+    }
 
-  if (IS_TLCS90 && abs(n) > (optimize.codeSize ? 2 + (af_free || bc_free || hl_free || iy_free || n < 0) * 2: 1))
+  if (IS_TLCS90 && abs(n) > (optimize.codeSize ? 2 + (bc_free || de_free || hl_free || iy_free || n < 0) * 2 : 1))
     {
-      emit2 ("add sp, #%d", n);
+      emit2 ("add sp, !immed%d", n);
       cost (3, 6);
       n -= n;
     }
-  else if (abs(n) > ((IS_RAB || IS_GB) ? 127 * 4 - 1 : (optimize.codeSize ? 8 : 5)) && hl_free)
+  else if ((optimize.codeSpeed ?
+    (loop_cycles >= (IS_RAB ? 10 : IS_SM83 ? 28 : 27)) :
+    (loop_bytes >= 5)) &&
+    hl_free)
     {
-      spillCached ();
-      emit2 ("ld hl, #%d", n);
+      emit2 ("ld hl, !immed%d", n);
       emit2 ("add hl, sp");
       emit2 ("ld sp, hl");
+      spillPair (PAIR_HL);
       cost2 (5, 27, 20, 10, 28, 18, 4);
       regalloc_dry_run_cost += 5;
       n -= n;
     }
-  else if (!IS_GB && abs(n) > ((IS_RAB || IS_GB) ? 127 * 4 - 1 : 8) && iy_free)
+  else if ((optimize.codeSpeed ?
+    (loop_cycles >= (IS_RAB ? 14 : 35)) :
+    (loop_bytes >= 7)) &&
+    hl_free)
+    {
+      emit2 ("ex de, hl");
+      emit2 ("ld hl, !immed%d", n);
+      emit2 ("add hl, sp");
+      emit2 ("ld sp, hl");
+      emit2 ("ex de, hl");
+      spillPair (PAIR_DE);
+      cost2 (7, 35, 26, 14, 0, 22, 6);
+      regalloc_dry_run_cost += 5;
+      n -= n;
+    }
+  else if ((optimize.codeSpeed ?
+    (loop_cycles >= (IS_RAB ? 16 : 39)) :
+    (loop_bytes >= (IS_TLCS90 ? 7 : 8))) &&
+    iy_free)
     {
-      spillCached ();
-      emit2 ("ld iy, #%d", n);
+      emit2 ("ld iy, !immed%d", n);
       emit2 ("add iy, sp");
       emit2 ("ld sp, iy");
+      spillPair (PAIR_IY);
+      cost2 (IS_TLCS90 ? 7 : 8, 39, 26, 16, 0, 20, 8);
       regalloc_dry_run_cost += 8;
       n -= n;
     }
-  else if (abs(n) > ((IS_RAB || IS_GB) ? 127 * 4 - 1 : 8) && bc_free)
+  else if (loop_bytes >= 9 && bc_free)
     {
       emit2 ("ld c, l");
       emit2 ("ld b, h");
-      emit2 ("ld hl, #%d", n);
+      emit2 ("ld hl, !immed%d", n);
       emit2 ("add hl, sp");
       emit2 ("ld sp, hl");
       emit2 ("ld l, c");
@@ -3674,8 +4720,8 @@
 
   while (abs(n))
     {
-      if ((IS_RAB || IS_GB) && abs(n) > (optimize.codeSize ? 2 : 1))
-        {
+      if ((IS_RAB && abs(n) > (optimize.codeSize ? 2 : 1) ) || (IS_SM83 && abs(n) > 2))
+        { // on sm83 inc/dec is nicer for 2B because it touches no flags
           int d;
           if (n > 127)
             d = 127;
@@ -3683,29 +4729,37 @@
             d = -128;
           else
             d = n;
-          emit2 ("add sp, #%d", d);
-          cost (2, IS_GB ? 16 : 4);
+          emit2 ("add sp, !immed%d", d);
+          cost (2, IS_SM83 ? 16 : 4);
           n -= d;
         }
-      else if (n >= 2 && af_free && (IS_Z80 || optimize.codeSize))
+      // on sm83 pop is smaller and faster, but that makes detection of unitialized memory harder
+      // On TLCS-90 pop af messes up interrupts (unless we have a valid value for f on the stack from previous push af).
+      else if (!IS_SM83 && !IS_TLCS90 && n >= 2 && af_free && ((IS_Z80 || IS_Z80N) || optimize.codeSize))
         {
           emit2 ("pop af");
           cost2 (1, 10, 9, 7, 12, 10, 3);
           n -= 2;
         }
-      else if (n <= -2 && (IS_Z80 || optimize.codeSize))
+      else if (!IS_SM83 && n <= -2 && ((IS_Z80 || IS_Z80N) || optimize.codeSize))
         {
           emit2 ("push af");
           cost2 (1, 10, 11, 7, 12, 10, 3);
           n += 2;
         }
-      else if (n >= 2 && bc_free && (IS_Z80 || optimize.codeSize))
+      else if (!IS_SM83 && n >= 2 && bc_free && ((IS_Z80 || IS_Z80N) || optimize.codeSize))
         {
           emit2 ("pop bc");
           cost2 (1, 10, 9, 7, 12, 10, 3);
           n -= 2;
         }
-      else if (n >= 2 && hl_free && (IS_Z80 || optimize.codeSize))
+      else if (!IS_SM83 && n >= 2 && de_free && ((IS_Z80 || IS_Z80N) || optimize.codeSize))
+        {
+          emit2 ("pop de");
+          cost2 (1, 10, 9, 7, 12, 10, 3);
+          n -= 2;
+        }
+      else if (!IS_SM83 && n >= 2 && hl_free && ((IS_Z80 || IS_Z80N) || optimize.codeSize))
         {
           emit2 ("pop hl");
           cost2 (1, 10, 9, 7, 12, 10, 3);
@@ -3734,38 +4788,17 @@
   wassert(!n);
 }
 
-/*-----------------------------------------------------------------*/
-/* movLeft2Result - move byte from left to result                  */
-/*-----------------------------------------------------------------*/
+/** Put Acc into a register set
+ */
 static void
-movLeft2Result (operand *left, int offl, operand *result, int offr, int sign)
+outAcc (operand * result)
 {
-  if (!sameRegs (AOP (left), AOP (result)) || (offl != offr))
+  int size = getDataSize (result);
+  if (size)
     {
-      if (!sign)
-        cheapMove (AOP (result), offr, AOP (left), offl, true);
-      else
-        {
-          if (getDataSize (left) == offl + 1)
-            {
-              cheapMove (ASMOP_A, 0, AOP (left), offl, true);
-              cheapMove (AOP (result), offr, ASMOP_A, 0, true);
-            }
-        }
-    }
-}
-
-/** Put Acc into a register set
- */
-static void
-outAcc (operand * result)
-{
-  int size = getDataSize (result);
-  if (size)
-    {
-      cheapMove (AOP (result), 0, ASMOP_A, 0, true);
+      cheapMove (result->aop, 0, ASMOP_A, 0, true);
       size--;
-      genMove_o (result->aop, 1, ASMOP_ZERO, 0, size, true, false);
+      genMove_o (result->aop, 1, ASMOP_ZERO, 0, size, true, false, false, true, true);
     }
 }
 
@@ -3775,10 +4808,10 @@
 outBitC (operand * result)
 {
   /* if the result is bit */
-  if (AOP_TYPE (result) == AOP_CRY)
+  if (result->aop->type == AOP_CRY)
     {
       if (!IS_OP_RUONLY (result) && !regalloc_dry_run)
-        aopPut (AOP (result), "c", 0);  // Todo: Cost.
+        aopPut (result->aop, "c", 0);  // Todo: Cost.
     }
   else
     {
@@ -3795,7 +4828,7 @@
 static void
 _toBoolean (const operand *oper, bool needflag)
 {
-  int size = AOP_SIZE (oper);
+  int size = oper->aop->size;
   sym_link *type = operandType (oper);
   int skipbyte;
 
@@ -3806,6 +4839,16 @@
       return;
     }
 
+  if (size == 2 && oper->aop->type == AOP_STL)
+    {
+      _push(PAIR_HL);
+      genMove (ASMOP_HL, oper->aop, true, false, false, false);
+      emit2 ("ld a, l");
+      emit2 ("or a, h");
+      _pop (PAIR_HL);
+      return;
+    }
+
   // Special handling to not overwrite a.
   if (oper->aop->regs[A_IDX] >= 0)
     skipbyte = oper->aop->regs[A_IDX];
@@ -3818,10 +4861,7 @@
   if (IS_FLOAT (type))
     {
       if (skipbyte != size - 1)
-        {
-          wassert (regalloc_dry_run);
-          regalloc_dry_run_cost += 120;
-        }
+        UNIMPLEMENTED;
       emit2 ("res 7, a");   //clear sign bit
       regalloc_dry_run_cost += 2;
       skipbyte = size - 1;
@@ -3830,10 +4870,7 @@
     if (size != skipbyte)
       {
         if (aopInReg (oper->aop, size, IYL_IDX) || aopInReg (oper->aop, size, IYH_IDX))
-          {
-            regalloc_dry_run_cost += 100;
-            wassert (regalloc_dry_run);
-          }
+          UNIMPLEMENTED;
         emit3_o (A_OR, ASMOP_A, 0, oper->aop, size);
       }
 }
@@ -3847,10 +4884,10 @@
   emitDebug ("; Casting to bool");
 
   /* Can do without OR-ing for small arguments */
-  if (AOP_SIZE (right) == 1 && !aopInReg (right->aop, 0, A_IDX))
+  if (right->aop->size == 1 && !aopInReg (right->aop, 0, A_IDX))
     {
       emit3 (A_XOR, ASMOP_A, ASMOP_A);
-      emit3 (A_CP, ASMOP_A, AOP (right));
+      emit3 (A_CP, ASMOP_A, right->aop);
     }
   else
     {
@@ -3865,7 +4902,7 @@
 
 /* Shuffle src reg array into dst reg array. */
 static void
-regMove (const short *dst, const short *src, size_t n, bool preserve_a)
+regMove (const short *dst, const short *src, size_t n, bool preserve_a) // Todo: replace uses of this one by uses of genMove_o?
 {
   bool assigned[9] = { FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE };
   int cached_byte = -1;
@@ -3874,7 +4911,7 @@
   size_t i;
   bool pushed_a = FALSE;
 
-  wassert (n < 6);
+  wassert (n <= 9);
 
   // Try to use ex de, hl
   if (size >= 4)
@@ -3896,6 +4933,7 @@
       if (ex[0] >= 0 && ex[1] >= 0 && ex[2] >= 0 && ex[3] >= 0)
         {
           emit2 ("ex de, hl");
+          swapPairs (PAIR_DE, PAIR_HL);
           regalloc_dry_run_cost++;
           assigned[ex[0]] = TRUE;
           assigned[ex[1]] = TRUE;
@@ -3983,16 +5021,36 @@
   aopOp (result, ic, TRUE, FALSE);
 
   /* if in bit space then a special case */
-  if (AOP_TYPE (left) == AOP_CRY)
+  if (left->aop->type == AOP_CRY)
     {
       wassertl (0, "Tried to negate a bit");
     }
   else if (IS_BOOL (operandType (left)))
     {
-      cheapMove (ASMOP_A, 0, AOP (left), 0, true);
+      cheapMove (ASMOP_A, 0, left->aop, 0, true);
       emit2 ("xor a, !immedbyte", 0x01);
       regalloc_dry_run_cost += 2;
-      cheapMove (AOP (result), 0, ASMOP_A, 0, true);
+      cheapMove (result->aop, 0, ASMOP_A, 0, true);
+      goto release;
+    }
+  else if (IS_RAB && left->aop->size == 2 && aopInReg (left->aop, 0, HL_IDX) && isPairDead (PAIR_HL, ic) && aopInReg (result->aop, 0, L_IDX))
+    {
+      emit2 ("bool hl");
+      emit2 ("rr hl");
+      emit2 ("ccf");
+      emit2 ("adc hl, hl");
+      cost (5, 10);
+      goto release;
+    }
+  else if (IS_RAB && left->aop->size == 2 && aopInReg (left->aop, 0, HL_IDX) && isPairDead (PAIR_HL, ic))
+    {
+      emit2 ("bool hl");
+      emit2 ("xor a, a");
+      emit2 ("rr hl");
+      emit2 ("ccf");
+      emit2 ("rla");
+      cost (5, 10);
+      cheapMove (result->aop, 0, ASMOP_A, 0, true);
       goto release;
     }
 
@@ -4012,88 +5070,6 @@
   freeAsmop (result, NULL);
 }
 
-/*-----------------------------------------------------------------*/
-/* genCpl - generate code for complement                           */
-/*-----------------------------------------------------------------*/
-static void
-genCpl (const iCode *ic)
-{
-  int skip_byte = -1;
-
-  bool a_dead = !bitVectBitValue (ic->rSurv, A_IDX);
-  bool pushed_a = false;
-
-  /* assign asmOps to operand & result */
-  aopOp (IC_LEFT (ic), ic, false, false);
-  aopOp (IC_RESULT (ic), ic, true, false);
-
-  /* if both are in bit space then
-     a special case */
-  if (AOP_TYPE (IC_RESULT (ic)) == AOP_CRY && AOP_TYPE (IC_LEFT (ic)) == AOP_CRY)
-    wassertl (0, "Left and the result are in bit space");
-
-  int size = IC_RESULT (ic)->aop->size;
-
-  if (IC_LEFT (ic)->aop->regs[A_IDX] >= 0 && IC_LEFT (ic)->aop->regs[A_IDX] < size)
-    {
-      int i = IC_LEFT (ic)->aop->regs[A_IDX];
-      emit3 (A_CPL, 0, 0);
-      cheapMove (IC_RESULT (ic)->aop, i, ASMOP_A, 0, true);
-      skip_byte = i;
-
-      if (aopInReg (IC_RESULT (ic)->aop, i, A_IDX))
-        a_dead = false;
-
-      // Do not overwrite still-needed value
-      if (IC_RESULT (ic)->aop->type == AOP_REG && !aopInReg (IC_RESULT (ic)->aop, i, A_IDX))
-        {
-          int j = IC_LEFT (ic)->aop->regs[IC_RESULT (ic)->aop->aopu.aop_reg[i]->rIdx];
-          if (j >= 0 && j != skip_byte && j < size)
-            {
-              regalloc_dry_run_cost += 150;
-              wassert (regalloc_dry_run);
-            } 
-        }
-    }
-
-  for (int i = 0; i < size; i++)
-    {
-      if (i == skip_byte)
-        continue;
-
-      if (!a_dead && !pushed_a)
-        {
-          _push (PAIR_AF);
-          pushed_a = true;
-        }
-
-      cheapMove (ASMOP_A, 0, IC_LEFT (ic)->aop, i, true);
-      emit3 (A_CPL, 0, 0);
-      cheapMove (IC_RESULT (ic)->aop, i, ASMOP_A, 0, true);
-
-      if (aopInReg (IC_RESULT (ic)->aop, i, A_IDX))
-        a_dead = false;
-
-      // Do not overwrite still-needed value
-      if (IC_RESULT (ic)->aop->type == AOP_REG && !aopInReg (IC_RESULT (ic)->aop, i, A_IDX))
-        {
-          int j = IC_LEFT (ic)->aop->regs[IC_RESULT (ic)->aop->aopu.aop_reg[i]->rIdx];
-          if (j > i && j < size && j != skip_byte)
-            {
-              regalloc_dry_run_cost += 150;
-              wassert (regalloc_dry_run);
-            } 
-        }
-    }
-
-  if (pushed_a)
-    _pop (PAIR_AF);
-
-  /* release the aops */
-  freeAsmop (IC_LEFT (ic), 0);
-  freeAsmop (IC_RESULT (ic), 0);
-}
-
 static void
 _gbz80_emitAddSubLongLong (const iCode * ic, asmop * left, asmop * right, bool isAdd)
 {
@@ -4114,8 +5090,8 @@
      store de into result
    */
 
-  wassertl (IS_GB, "Code is only relevant to the gbz80");
-  wassertl (AOP (IC_RESULT (ic))->size == 4, "Only works for four bytes");
+  wassertl (IS_SM83, "Code is only relevant to the gbz80");
+  wassertl (IC_RESULT (ic)->aop->size == 4, "Only works for four bytes");
 
   fetchPair (PAIR_DE, left);
 
@@ -4129,8 +5105,8 @@
 
   _push (PAIR_AF);
 
-  cheapMove (AOP (IC_RESULT (ic)), MSB16, ASMOP_A, 0, true);
-  cheapMove (AOP (IC_RESULT (ic)), LSB, ASMOP_E, 0, true);
+  cheapMove (IC_RESULT (ic)->aop, MSB16, ASMOP_A, 0, true);
+  cheapMove (IC_RESULT (ic)->aop, LSB, ASMOP_E, 0, true);
 
   fetchPairLong (PAIR_DE, left, NULL, MSB24);
 
@@ -4145,38 +5121,14 @@
   regalloc_dry_run_cost += 2;
   emit3_o (later, ASMOP_A, 0, right, MSB32);
 
-  cheapMove (AOP (IC_RESULT (ic)), MSB32, ASMOP_A, 0, true);
-  cheapMove (AOP (IC_RESULT (ic)), MSB24, ASMOP_E, 0, true);
+  cheapMove (IC_RESULT (ic)->aop, MSB32, ASMOP_A, 0, true);
+  cheapMove (IC_RESULT (ic)->aop, MSB24, ASMOP_E, 0, true);
 }
 
 static void
 _gbz80_emitAddSubLong (const iCode * ic, bool isAdd)
 {
-  _gbz80_emitAddSubLongLong (ic, AOP (IC_LEFT (ic)), AOP (IC_RIGHT (ic)), isAdd);
-}
-
-/*-----------------------------------------------------------------*/
-/* assignResultValue -               */
-/*-----------------------------------------------------------------*/
-static void
-assignResultValue (operand * oper)
-{
-  int size = oper->aop->size;
-
-  wassertl (size <= 4, "Got a result that is bigger than four bytes");
-
-  if (IS_GB && size == 4 && requiresHL (AOP (oper)))
-    {
-      /* We do it the hard way here. */
-      _push (PAIR_HL);
-      cheapMove (oper->aop, 0, ASMOP_RETURN, 0, true);
-      cheapMove (oper->aop, 1, ASMOP_RETURN, 1, true);
-      _pop (PAIR_DE);
-      cheapMove (oper->aop, 2, ASMOP_E, 0, true);
-      cheapMove (oper->aop, 3, ASMOP_D, 0, true);
-    }
-  else
-    genMove (oper->aop, ASMOP_RETURN, true, true);
+  _gbz80_emitAddSubLongLong (ic, IC_LEFT (ic)->aop, IC_RIGHT (ic)->aop, isAdd);
 }
 
 /* Pop saved regs from stack, taking care not to destroy result */
@@ -4186,10 +5138,8 @@
   bool bInRet, cInRet, dInRet, eInRet, hInRet, lInRet;
   bool SomethingReturned;
 
-  SomethingReturned = (result && IS_ITEMP (result) &&
-                      (OP_SYMBOL_CONST (result)->nRegs ||
-                      OP_SYMBOL_CONST (result)->spildir ||
-                      OP_SYMBOL_CONST (result)->accuse == ACCUSE_A)) || IS_TRUE_SYMOP (result);
+  SomethingReturned = result && IS_ITEMP (result) && (OP_SYMBOL_CONST (result)->nRegs || OP_SYMBOL_CONST (result)->spildir)
+                      || IS_TRUE_SYMOP (result);
 
   if (SomethingReturned)
     {
@@ -4228,13 +5178,22 @@
           emit2 ("ld d, a");
           regalloc_dry_run_cost += 1;
         }
-      else if (eInRet)
+      else if (eInRet && !IS_TLCS90) // TLCS-90 has interrupt settings in f, so we can't pop af unless we did push af before.
         {
           /* Only restore D */
           _pop (PAIR_AF);
           emit2 ("ld d, a");
           regalloc_dry_run_cost += 1;
         }
+      else if (eInRet)
+        {
+          /* Only restore D */
+          emit2 ("ld a, e");
+          regalloc_dry_run_cost += 1;
+          _pop (PAIR_DE);
+          emit2 ("ld e, a");
+          regalloc_dry_run_cost += 1;
+        }
       else
         _pop (PAIR_DE);
     }
@@ -4252,13 +5211,22 @@
           emit2 ("ld b, a");
           regalloc_dry_run_cost += 1;
         }
-      else if (cInRet)
+      else if (cInRet && !IS_TLCS90)
         {
           /* Only restore B */
           _pop (PAIR_AF);
           emit2 ("ld b, a");
           regalloc_dry_run_cost += 1;
         }
+      else if (cInRet)
+        {
+          /* Only restore B */
+          emit2 ("ld a, c");
+          regalloc_dry_run_cost += 1;
+          _pop (PAIR_BC);
+          emit2 ("ld c, a");
+          regalloc_dry_run_cost += 1;
+        }
       else
         _pop (PAIR_BC);
     }
@@ -4276,13 +5244,22 @@
           emit2 ("ld h, a");
           regalloc_dry_run_cost += 1;
         }
-      else if (lInRet)
+      else if (lInRet && !IS_TLCS90)
         {
           /* Only restore D */
           _pop (PAIR_AF);
           emit2 ("ld h, a");
           regalloc_dry_run_cost += 1;
         }
+      else if (lInRet)
+        {
+          /* Only restore E */
+          emit2 ("ld a, l");
+          regalloc_dry_run_cost += 1;
+          _pop (PAIR_HL);
+          emit2 ("ld l, a");
+          regalloc_dry_run_cost += 1;
+        }
       else
         _pop (PAIR_HL);
     }
@@ -4318,33 +5295,10 @@
 
   if (_G.saves.saved == FALSE)
     {
-      bool push_bc, push_de, push_hl, push_iy;
-
-      if (options.oldralloc)
-        {
-          bool deInUse, bcInUse;
-          bool bcInRet = FALSE, deInRet = FALSE;
-          bitVect *rInUse;
-
-          rInUse = bitVectCplAnd (bitVectCopy (ic->rMask), z80_rUmaskForOp (IC_RESULT (ic)));
-
-          deInUse = bitVectBitValue (rInUse, D_IDX) || bitVectBitValue (rInUse, E_IDX);
-          bcInUse = bitVectBitValue (rInUse, B_IDX) || bitVectBitValue (rInUse, C_IDX);
-
-          emitDebug ("; _saveRegsForCall: deInUse: %u bcInUse: %u", deInUse, bcInUse);
-
-          push_bc = bcInUse && !bcInRet;
-          push_de = deInUse && !deInRet;
-          push_hl = FALSE;
-          push_iy = FALSE;
-        }
-      else
-        {
-          push_bc = bitVectBitValue (ic->rSurv, B_IDX) && !ftype->funcAttrs.preserved_regs[B_IDX] || bitVectBitValue (ic->rSurv, C_IDX) && !ftype->funcAttrs.preserved_regs[C_IDX];
-          push_de = bitVectBitValue (ic->rSurv, D_IDX) && !ftype->funcAttrs.preserved_regs[D_IDX] || bitVectBitValue (ic->rSurv, E_IDX) && !ftype->funcAttrs.preserved_regs[E_IDX];
-          push_hl = bitVectBitValue (ic->rSurv, H_IDX) || bitVectBitValue (ic->rSurv, L_IDX);
-          push_iy = !dontsaveIY && (bitVectBitValue (ic->rSurv, IYH_IDX) || bitVectBitValue (ic->rSurv, IYL_IDX));
-        }
+      const bool push_bc = !isRegDead (B_IDX, ic) && !ftype->funcAttrs.preserved_regs[B_IDX] || !isRegDead (C_IDX, ic) && !ftype->funcAttrs.preserved_regs[C_IDX];
+      const bool push_de = !isRegDead (D_IDX, ic) && !ftype->funcAttrs.preserved_regs[D_IDX] || !isRegDead (E_IDX, ic) && !ftype->funcAttrs.preserved_regs[E_IDX];
+      const bool push_hl = !isRegDead (H_IDX, ic) || !isRegDead (L_IDX, ic);
+      const bool push_iy = !dontsaveIY && (!isRegDead (IYH_IDX, ic) || !isRegDead (IYL_IDX, ic));
 
       if (push_hl)
         {
@@ -4382,8 +5336,6 @@
 static void
 genIpush (const iCode *ic)
 {
-  int size, offset = 0;
-
   /* if this is not a parm push : ie. it is spill push
      and spill push is always done on the local stack */
   if (!ic->parmPush)
@@ -4391,7 +5343,7 @@
       wassertl (0, "Encountered an unsupported spill push.");
       return;
     }
-      
+
   /* Scan ahead until we find the function that we are pushing parameters to.
      Count the number of addSets on the way to figure out what registers
      are used in the send set.
@@ -4411,195 +5363,303 @@
   if (!regalloc_dry_run && !_G.saves.saved && !regalloc_dry_run) /* Cost is counted at CALL or PCALL instead */
     _saveRegsForCall (walk, false); /* Caller saves, and this is the first iPush. */
 
-  const bool smallc = IFFUNC_ISSMALLC (operandType (IC_LEFT (walk)));
+  sym_link *ftype = operandType (IC_LEFT (walk));
+  if (walk->op == PCALL)
+    ftype = ftype->next;
+  const bool smallc = IFFUNC_ISSMALLC (ftype);
 
   /* then do the push */
   aopOp (IC_LEFT (ic), ic, FALSE, FALSE);
 
-  size = AOP_SIZE (IC_LEFT (ic));
+  int size = IC_LEFT (ic)->aop->size;
 
-  if (isPair (AOP (IC_LEFT (ic))) && size == 2)
+  if (size == 1 && smallc) /* The SmallC calling convention pushes 8-bit parameters as 16-bit values. */
     {
-      if (!regalloc_dry_run)
+      if (IC_LEFT (ic)->aop->type == AOP_REG && IC_LEFT (ic)->aop->aopu.aop_reg[0]->rIdx == C_IDX)
         {
-          _G.stack.pushed += 2;
-          emit2 ("push %s", getPairName (AOP (IC_LEFT (ic))));
+          emit2 ("push bc");
+          regalloc_dry_run_cost++;
         }
-      regalloc_dry_run_cost += (getPairId (AOP (IC_LEFT (ic))) == PAIR_IY ? 2 : 1);
-    }
-  else
-    {
-      if (size == 1 && smallc) /* The SmallC calling convention pushes 8-bit parameters as 16-bit values. */
+      else if (IC_LEFT (ic)->aop->type == AOP_REG && IC_LEFT (ic)->aop->aopu.aop_reg[0]->rIdx == E_IDX)
         {
-          if (AOP_TYPE (IC_LEFT (ic)) == AOP_REG && AOP (IC_LEFT (ic))->aopu.aop_reg[2]->rIdx == C_IDX)
-            {
-              emit2 ("push bc");
-              regalloc_dry_run_cost += 1;
-            }
-          else if (AOP_TYPE (IC_LEFT (ic)) == AOP_REG && AOP (IC_LEFT (ic))->aopu.aop_reg[2]->rIdx == E_IDX)
-            {
-              emit2 ("push de");
-              regalloc_dry_run_cost += 1;
-            }
-          else if (AOP_TYPE (IC_LEFT (ic)) == AOP_REG && AOP (IC_LEFT (ic))->aopu.aop_reg[2]->rIdx == L_IDX)
-            {
-              emit2 ("push hl");
-              regalloc_dry_run_cost += 1;
-            }
-          else
-            {
-              emit2 ("dec sp");
-              cheapMove (ASMOP_A, 0, AOP (IC_LEFT (ic)), 0, true);
-              emit2 ("push af");
-              emit2 ("inc sp");
-              regalloc_dry_run_cost += 3;
-            }
-          if (!regalloc_dry_run)
-            _G.stack.pushed += 2;
-          goto release;
+          emit2 ("push de");
+          regalloc_dry_run_cost++;
         }
-      else if (size == 2)
+      else if (IC_LEFT (ic)->aop->type == AOP_REG && IC_LEFT (ic)->aop->aopu.aop_reg[0]->rIdx == L_IDX)
         {
-          PAIR_ID pair = getDeadPairId (ic);
-          if (pair == PAIR_INVALID || isPairDead (PAIR_HL, ic))
-            pair = PAIR_HL;     /* hl sometimes is cheaper to load than other pairs. */
-
-          fetchPairLong (pair, AOP (IC_LEFT (ic)), ic, 0);
-          if (!regalloc_dry_run)
-            {
-              emit2 ("push %s", _pairs[pair].name);
-              _G.stack.pushed += 2;
-            }
-          regalloc_dry_run_cost += 1;
-          goto release;
+          emit2 ("push hl");
+          regalloc_dry_run_cost++;
         }
-      if (size == 4)
+      else if (isRegDead (HL_IDX, ic))
         {
-          if (getPairId_o (IC_LEFT (ic)->aop, 2) != PAIR_INVALID)
-            {
-              emit2 ("push %s", _pairs[getPairId_o (IC_LEFT (ic)->aop, 2)].name);
-              regalloc_dry_run_cost += 1 + (getPairId_o (IC_LEFT (ic)->aop, 2) == PAIR_IY);
-            }
-          else
-            {
-              fetchPairLong (PAIR_HL, AOP (IC_LEFT (ic)), 0, 2);
-              emit2 ("push hl");
-              regalloc_dry_run_cost += 1;
-            }
-          if (!regalloc_dry_run)
-            _G.stack.pushed += 2;
-
-          if (getPairId_o (IC_LEFT (ic)->aop, 0) != PAIR_INVALID)
-            {
-              emit2 ("push %s", _pairs[getPairId_o (IC_LEFT (ic)->aop, 0)].name);
-              regalloc_dry_run_cost += 1 + (getPairId_o (IC_LEFT (ic)->aop, 2) == PAIR_IY);
-            }
-          else
-            {
-              fetchPairLong (PAIR_HL, AOP (IC_LEFT (ic)), 0, 0);
-              emit2 ("push hl");
-              regalloc_dry_run_cost += 1;
-            }
-          if (!regalloc_dry_run)
-            _G.stack.pushed += 2;
-
-          goto release;
+          cheapMove (ASMOP_L, 0, IC_LEFT (ic)->aop, 0, true);
+          emit2 ("push hl");
+          regalloc_dry_run_cost++;
         }
-      offset = size;
-      while (size--)
+      else if (isRegDead (A_IDX, ic))
         {
-          if (size && getFreePairId (ic) != PAIR_INVALID)
-            {
-              offset -= 2;
-
-              PAIR_ID pair = getFreePairId (ic);
-              fetchPairLong (pair, AOP (IC_LEFT (ic)), 0, offset);
-              emit2 ("push %s", _pairs[pair].name);
-              regalloc_dry_run_cost += 1;
-              size--;
-
-              if (!regalloc_dry_run)
-                _G.stack.pushed += 2;
-
-              continue;
-            }
-          else if (AOP (IC_LEFT (ic))->type == AOP_IY)
-            {
-              wassertl (!bitVectBitValue (ic->rSurv, A_IDX), "Loading from address destroys A, which must survive.");
-              emit2 ("ld a, (%s)", aopGetLitWordLong (AOP (IC_LEFT (ic)), --offset, FALSE));
-              emit2 ("push af");
-              regalloc_dry_run_cost += 4;
-            }
-          else
-            {
-              offset--;
-              if (AOP (IC_LEFT (ic))->type == AOP_REG && AOP (IC_LEFT (ic))->aopu.aop_reg[offset]->rIdx == B_IDX)
-                {
-                  emit2 ("push bc");
-                  regalloc_dry_run_cost += 1;
-                }
-              else if (AOP (IC_LEFT (ic))->type == AOP_REG && AOP (IC_LEFT (ic))->aopu.aop_reg[offset]->rIdx == D_IDX)
-                {
-                  emit2 ("push de");
-                  regalloc_dry_run_cost += 1;
-                }
-              else if (AOP (IC_LEFT (ic))->type == AOP_REG && AOP (IC_LEFT (ic))->aopu.aop_reg[offset]->rIdx == H_IDX)
-                {
-                  emit2 ("push hl");
-                  regalloc_dry_run_cost += 1;
-                }
-              else
-                {
-                  if (AOP_TYPE (IC_LEFT (ic)) != AOP_SFR && !regalloc_dry_run && !strcmp (aopGet (AOP (IC_LEFT (ic)), offset, FALSE), "h"))   // todo: More exact cost!
-                    emit2 ("push hl");
-                  else
-                    {
-                      wassertl (aopInReg (IC_LEFT (ic)->aop, 0, A_IDX) || !bitVectBitValue (ic->rSurv, A_IDX), "Push operand destroys A, which must survive.");
-                      if (AOP_TYPE (IC_LEFT (ic)) == AOP_LIT && byteOfVal (AOP (IC_LEFT (ic))->aopu.aop_lit, offset) == 0x00)
-                        emit3 (A_XOR, ASMOP_A, ASMOP_A);
-                      else
-                        {
-                          cheapMove (ASMOP_A, 0, AOP (IC_LEFT (ic)), offset, true);
-                          if (!aopInReg (IC_LEFT (ic)->aop, 0, A_IDX))
-                            regalloc_dry_run_cost += ld_cost (ASMOP_A, AOP (IC_LEFT (ic)));
-                        }
-                      emit2 ("push af");
-                      regalloc_dry_run_cost += 1;
-                    }
-                }
-            }
-          if (!regalloc_dry_run)
-            {
-              emit2 ("inc sp");
-              _G.stack.pushed++;
-            }
-          regalloc_dry_run_cost += 1;
+          emit2 ("dec sp");
+          cheapMove (ASMOP_A, 0, IC_LEFT (ic)->aop, 0, true);
+          emit2 ("push af");
+          emit2 ("inc sp");
+          regalloc_dry_run_cost += 3;
         }
+      else if (!IS_SM83)
+        {
+          emit2 ("push hl");
+          cheapMove (ASMOP_L, 0, IC_LEFT (ic)->aop, 0, false);
+          emit2 ("ex (sp), hl");
+          spillPair (PAIR_HL);
+          regalloc_dry_run_cost += 2;
+        }
+      else
+        wassert (0);
+
+      if (!regalloc_dry_run)
+        _G.stack.pushed += 2;
+      goto release;
     }
-release:
-  freeAsmop (IC_LEFT (ic), NULL);
-}
 
-/*-----------------------------------------------------------------*/
-/* genIpop - recover the registers: can happen only for spilling   */
-/*-----------------------------------------------------------------*/
-static void
-genIpop (const iCode * ic)
-{
-  int size, offset;
+    while (size)
+      {
+        int d = 0;
 
-  wassert (!regalloc_dry_run);
+        bool a_free = isRegDead (A_IDX, ic) && (IC_LEFT (ic)->aop->regs[A_IDX] < 0 || IC_LEFT (ic)->aop->regs[A_IDX] >= size - 1);
+        bool b_free = isRegDead (B_IDX, ic) && (IC_LEFT (ic)->aop->regs[B_IDX] < 0 || IC_LEFT (ic)->aop->regs[B_IDX] >= size - 1);
+        bool c_free = isRegDead (C_IDX, ic) && (IC_LEFT (ic)->aop->regs[C_IDX] < 0 || IC_LEFT (ic)->aop->regs[C_IDX] >= size - 1);
+        bool d_free = isRegDead (D_IDX, ic) && (IC_LEFT (ic)->aop->regs[D_IDX] < 0 || IC_LEFT (ic)->aop->regs[D_IDX] >= size - 1);
+        bool e_free = isRegDead (E_IDX, ic) && (IC_LEFT (ic)->aop->regs[E_IDX] < 0 || IC_LEFT (ic)->aop->regs[E_IDX] >= size - 1);
+        bool h_free = isRegDead (H_IDX, ic) && (IC_LEFT (ic)->aop->regs[H_IDX] < 0 || IC_LEFT (ic)->aop->regs[H_IDX] >= size - 1);
+        bool l_free = isRegDead (L_IDX, ic) && (IC_LEFT (ic)->aop->regs[L_IDX] < 0 || IC_LEFT (ic)->aop->regs[L_IDX] >= size - 1);
+        bool hl_free = isPairDead (PAIR_HL, ic) && (h_free || IC_LEFT (ic)->aop->regs[H_IDX] >= size - 2) && (l_free || IC_LEFT (ic)->aop->regs[L_IDX] >= size - 2);
+        bool de_free = isPairDead (PAIR_DE, ic) && (d_free || IC_LEFT (ic)->aop->regs[D_IDX] >= size - 2) && (e_free || IC_LEFT (ic)->aop->regs[E_IDX] >= size - 2);
+        bool bc_free = isPairDead (PAIR_BC, ic) && (b_free || IC_LEFT (ic)->aop->regs[B_IDX] >= size - 2) && (c_free || IC_LEFT (ic)->aop->regs[C_IDX] >= size - 2);
 
-  /* if the temp was not pushed then */
-  if (OP_SYMBOL (IC_LEFT (ic))->isspilt)
-    return;
+        if (getPairId_o (IC_LEFT (ic)->aop, size - 2) != PAIR_INVALID)
+          {
+            emit2 ("push %s", _pairs[getPairId_o (IC_LEFT (ic)->aop, size - 2)].name);
+            regalloc_dry_run_cost += 1 + (getPairId_o (IC_LEFT (ic)->aop, size - 2) == PAIR_IY);
+            d = 2;
+          }
+#if 0 // Fails regression tests. Simulator issue regarding flags?
+        // gbz80 flag handling differs from other z80 variants, allowing this hack to push a 16-bit zero.
+        else if (size >= 2 && IS_SM83 && a_free &&
+          IC_LEFT (ic)->aop->type == AOP_LIT && !byteOfVal (IC_LEFT(ic)->aop->aopu.aop_lit, size - 2) && !byteOfVal (IC_LEFT(ic)->aop->aopu.aop_lit, size - 1))
+          {
+            emit2 ("xor a, a"); // Resets all flags except for z
+            emit2 ("rra");      // Resets z (and since a is already 0, c stays reset)
+            emit2 ("push af");  // Pushes 0 in a, 0 for the unused upper 4 flag bits, 4 flag bits that are all reset, giving us a 16-bit 0 push.
+            regalloc_dry_run_cost += 3;
+            d = 2;
+          }
+#endif
+        else if (size >= 2 &&
+          (hl_free || de_free || bc_free ||
+          aopInReg (IC_LEFT (ic)->aop, size - 1, B_IDX) && c_free || b_free && aopInReg (IC_LEFT (ic)->aop, size - 2, C_IDX) ||
+          aopInReg (IC_LEFT (ic)->aop, size - 1, D_IDX) && e_free || d_free && aopInReg (IC_LEFT (ic)->aop, size - 2, E_IDX) ||
+          aopInReg (IC_LEFT (ic)->aop, size - 1, H_IDX) && l_free || h_free && aopInReg (IC_LEFT (ic)->aop, size - 2, L_IDX)))
+          {
+            asmop *pair = 0;
+            
+            /* hl has lower priority on GB, because it's needed for stack access */
+            if (!IS_SM83 && hl_free)
+              pair = ASMOP_HL;
+            else if (de_free)
+              pair = ASMOP_DE;
+            else if (bc_free)
+              pair = ASMOP_BC;
+            else if (hl_free)
+              pair = ASMOP_HL;
+              
+            if (IS_SM83 && requiresHL (IC_LEFT (ic)->aop) && IC_LEFT (ic)->aop->type != AOP_REG && de_free)
+              pair = ASMOP_DE;
+            else if (IS_SM83 && requiresHL (IC_LEFT (ic)->aop) && IC_LEFT (ic)->aop->type != AOP_REG && bc_free)
+              pair = ASMOP_BC;
+
+            if (aopInReg (IC_LEFT (ic)->aop, size - 1, H_IDX) && l_free || h_free && aopInReg (IC_LEFT (ic)->aop, size - 2, L_IDX))
+              pair = ASMOP_HL;
+            else if (aopInReg (IC_LEFT (ic)->aop, size - 1, D_IDX) && e_free || d_free && aopInReg (IC_LEFT (ic)->aop, size - 2, E_IDX))
+              pair = ASMOP_DE;
+            else if (aopInReg (IC_LEFT (ic)->aop, size - 1, B_IDX) && c_free || b_free && aopInReg (IC_LEFT (ic)->aop, size - 2, C_IDX))
+              pair = ASMOP_BC;
+            
+            genMove_o (pair, 0, IC_LEFT (ic)->aop, size - 2, 2, a_free, hl_free, de_free, true, true);
+            emit2 ("push %s", _pairs[getPairId (pair)].name);
+            regalloc_dry_run_cost++;
+            d = 2;
 
-  aopOp (IC_LEFT (ic), ic, FALSE, FALSE);
-  size = AOP_SIZE (IC_LEFT (ic));
+            // For hl and iy, genMove_o can do better caching of literal values than what we do here. TODO: Remove this, and make genMove_o handle cahing well for bc and de, too (will require quite some spillPair() calls througout codegen).
+            while (getPairId (pair) != PAIR_HL && IC_LEFT (ic)->aop->type == AOP_LIT && !IS_FLOAT (IC_LEFT (ic)->aop->aopu.aop_lit->type) && size - (d+2) >= 0)
+              {
+                unsigned long current = (ullFromVal(IC_LEFT (ic)->aop->aopu.aop_lit)>>((size - d    )*8)) & 0xFFFF;
+                unsigned long next = (ullFromVal(IC_LEFT (ic)->aop->aopu.aop_lit)>>((size - (d+2))*8)) & 0xFFFF;
+                if (current == next)
+                  {
+                    emitDebug ("; genIpush identical value again");
+                    emit2 ("push %s", _pairs[getPairId (pair)].name);
+                    regalloc_dry_run_cost++;
+                    d+=2;
+                  }
+                else if ((current & 0xFF) == (next & 0xFF))
+                  {
+                    emitDebug ("; genIpush similar value again");
+                    emit2 ("ld %s, !immedbyte", _pairs[getPairId (pair)].h, next>>8);
+                    emit2 ("push %s", _pairs[getPairId (pair)].name);
+                    regalloc_dry_run_cost++;
+                    d+=2;
+                  }
+                else if ((current & 0xFF00) == (next & 0xFF00))
+                  {
+                    emitDebug ("; genIpush similar value again");
+                    emit2 ("ld %s, !immedbyte", _pairs[getPairId (pair)].l, next & 0xFF);
+                    emit2 ("push %s", _pairs[getPairId (pair)].name);
+                    regalloc_dry_run_cost++;
+                    d+=2;
+                  }
+                else
+                  break;
+              }
+         }
+       else if (size >= 2 && IS_Z80N && (IC_LEFT (ic)->aop->type == AOP_LIT || IC_LEFT (ic)->aop->type == AOP_IMMD)) // Same size, but slower (21 vs 23 cycles) than going through a register pair other than iy. Only worth it under high register pressure.
+         {
+           emit2 ("push !hashedstr", aopGetLitWordLong (IC_LEFT (ic)->aop, size - 2, false));
+           regalloc_dry_run_cost += 4;
+           d = 2;
+         }
+       else if (size >= 2 && !IS_SM83 && !IY_RESERVED && isPairDead (PAIR_IY, ic) && (IC_LEFT (ic)->aop->type == AOP_LIT || IC_LEFT (ic)->aop->type == AOP_IMMD))
+         {
+           genMove_o (ASMOP_IY, 0, IC_LEFT (ic)->aop, size - 2, 2, a_free, hl_free, de_free, true, true);
+           emit2 ("push iy");
+           regalloc_dry_run_cost += 2;
+           d = 2;
+         }
+       else if (size >= 2 && !IS_SM83)
+         {
+           emit2 ("push hl");
+           _G.stack.pushed += 2;
+           genMove_o (ASMOP_HL, 0, IC_LEFT (ic)->aop, size - 2, 2, a_free, hl_free, de_free, true, true);
+           _G.stack.pushed -= 2;
+           emit2 ("ex (sp), hl");
+           spillPair (PAIR_HL);
+           regalloc_dry_run_cost += 3;
+           d = 2;
+         }
+       else if (aopInReg (IC_LEFT (ic)->aop, size - 1, A_IDX))
+         {
+           emit2 ("push af");
+           emit2 ("inc sp");
+           regalloc_dry_run_cost += 2;
+           d = 1;
+         }
+       else if (aopInReg (IC_LEFT (ic)->aop, size - 1, B_IDX))
+         {
+           emit2 ("push bc");
+           emit2 ("inc sp");
+           regalloc_dry_run_cost += 2;
+           d = 1;
+         }
+       else if (aopInReg (IC_LEFT (ic)->aop, size - 1, D_IDX))
+         {
+           emit2 ("push de");
+           emit2 ("inc sp");
+           regalloc_dry_run_cost += 2;
+           d = 1;
+         }
+       else if (aopInReg (IC_LEFT (ic)->aop, size - 1, H_IDX))
+         {
+           emit2 ("push hl");
+           emit2 ("inc sp");
+           regalloc_dry_run_cost += 2;
+           d = 1;
+         }
+       else if (aopInReg (IC_LEFT (ic)->aop, size - 1, IYH_IDX))
+         {
+           emit2 ("push iy");
+           emit2 ("inc sp");
+           regalloc_dry_run_cost += 2;
+           d = 1;
+         }
+       else if (a_free)
+         {
+           genMove_o (ASMOP_A, 0, IC_LEFT (ic)->aop, size - 1, 1, true, h_free && l_free, d_free && e_free, true, true);
+           emit2 ("push af");
+           emit2 ("inc sp");
+           regalloc_dry_run_cost += 2;
+           d = 1;
+         }
+       else if (h_free)
+         {
+           cheapMove (ASMOP_H, 0, IC_LEFT (ic)->aop, size - 1, false);
+           emit2 ("push hl");
+           emit2 ("inc sp");
+           regalloc_dry_run_cost += 2;
+           d = 1;
+         }
+       else if (d_free)
+         {
+           cheapMove (ASMOP_D, 0, IC_LEFT (ic)->aop, size - 1, false);
+           emit2 ("push de");
+           emit2 ("inc sp");
+           regalloc_dry_run_cost += 2;
+           d = 1;
+         }
+       else if (b_free)
+         {
+           cheapMove (ASMOP_B, 0, IC_LEFT (ic)->aop, size - 1, false);
+           emit2 ("push bc");
+           emit2 ("inc sp");
+           regalloc_dry_run_cost += 2;
+           d = 1;
+         }
+      else if (IS_Z80N && IC_LEFT (ic)->aop->type == AOP_LIT)
+         {
+           emit2 ("push !immedword", byteOfVal (IC_LEFT (ic)->aop->aopu.aop_lit, size - 1) << 8);
+           emit2 ("inc sp");
+           regalloc_dry_run_cost += 5;
+           d = 1;
+         }
+       else if (!IS_SM83)
+         {
+           emit2 ("push hl");
+           cheapMove (ASMOP_H, 0, IC_LEFT (ic)->aop, size - 1, false);
+           emit2 ("ex (sp), hl");
+           spillPair (PAIR_HL);
+           emit2 ("inc sp");
+           regalloc_dry_run_cost += 3;
+           d = 1;
+         }
+       else
+         wassert (0);
+
+       if (!regalloc_dry_run)
+          _G.stack.pushed += d;
+       size -= d;
+     }
+
+release:
+  freeAsmop (IC_LEFT (ic), NULL);
+}
+
+/*-----------------------------------------------------------------*/
+/* genIpop - recover the registers: can happen only for spilling   */
+/*-----------------------------------------------------------------*/
+static void
+genIpop (const iCode * ic)
+{
+  int size, offset;
+
+  wassert (!regalloc_dry_run);
+
+  /* if the temp was not pushed then */
+  if (OP_SYMBOL (IC_LEFT (ic))->isspilt)
+    return;
+
+  aopOp (IC_LEFT (ic), ic, FALSE, FALSE);
+  size = IC_LEFT (ic)->aop->size;
   offset = (size - 1);
-  if (isPair (AOP (IC_LEFT (ic))))
+  if (isPair (IC_LEFT (ic)->aop))
     {
-      emit2 ("pop %s", getPairName (AOP (IC_LEFT (ic))));
+      emit2 ("pop %s", getPairName (IC_LEFT (ic)->aop));
     }
   else
     {
@@ -4608,7 +5668,7 @@
           emit2 ("dec sp");
           emit2 ("pop hl");
           spillPair (PAIR_HL);
-          aopPut (AOP (IC_LEFT (ic)), "l", offset--);
+          aopPut (IC_LEFT (ic)->aop, "l", offset--);
         }
     }
 
@@ -4645,81 +5705,59 @@
  */
 static void genSend (const iCode *ic)
 {
-  int size;
-
   aopOp (IC_LEFT (ic), ic, FALSE, FALSE);
-  size = AOP_SIZE (IC_LEFT (ic));
+  
+  /* Caller saves, and this is the first iPush. */
+  // Scan ahead until we find the function that we are pushing parameters to.
+  const iCode *walk;
+  for (walk = ic->next; walk; walk = walk->next)
+    {
+      if (walk->op == CALL || walk->op == PCALL)
+        break;
+    }
 
-  wassertl (ic->next->op == CALL || ic->next->op == PCALL, "Sending register parameter for missing call");
-  wassertl (!IS_GB, "Register parameters are not supported in gbz80 port");
+  if (!_G.saves.saved && !regalloc_dry_run) // Cost is counted at CALL or PCALL instead
+    _saveRegsForCall (walk, false);
 
-  if (_G.saves.saved == FALSE && !regalloc_dry_run /* Cost is counted at CALL or PCALL instead */ )
-    {
-      /* Caller saves, and this is the first iPush. */
-      /* Scan ahead until we find the function that we are pushing parameters to.
-         Count the number of addSets on the way to figure out what registers
-         are used in the send set.
-       */
-      int nAddSets = 0;
-      iCode *walk = ic->next;
+  sym_link *ftype = IS_FUNCPTR (operandType (IC_LEFT (walk))) ? operandType (IC_LEFT (walk))->next : operandType (IC_LEFT (walk));
+  asmop *argreg = aopArg (ftype, ic->argreg);
+  
+  wassert (argreg);
 
-      while (walk)
-        {
-          if (walk->op == SEND)
-            {
-              nAddSets++;
-            }
-          else if (walk->op == CALL || walk->op == PCALL)
-            {
-              /* Found it. */
+  // The register argument shall not overwrite a still-needed (i.e. as further parameter or function for the call) value.
+  for (int i = 0; i < argreg->size; i++)
+    if (!isRegDead (argreg->aopu.aop_reg[i]->rIdx, ic))
+      for (iCode *walk2 = ic->next; walk2; walk2 = walk2->next)
+          {
+            if (walk2->op != CALL && IC_LEFT (walk2) && !IS_OP_LITERAL (IC_LEFT (walk2)))
+              UNIMPLEMENTED;
+
+            if (walk2->op == CALL || walk2->op == PCALL)
               break;
-            }
-          else
-            {
-              /* Keep looking. */
-            }
-          walk = walk->next;
-        }
-      _saveRegsForCall (walk, FALSE);
-    }
-  if (size == 2)
+          }
+
+  bool a_dead = isRegDead (A_IDX, ic);
+  bool hl_dead = isPairDead (PAIR_HL, ic);
+  bool de_dead = isPairDead (PAIR_DE, ic);
+  
+  for (iCode *walk2 = ic->prev; walk2 && walk2->op == SEND; walk2 = walk2->prev)
     {
-      fetchPairLong (PAIR_HL, AOP (IC_LEFT (ic)), ic, 0);
-      z80_regs_used_as_parms_in_calls_from_current_function[L_IDX] = true;
-      z80_regs_used_as_parms_in_calls_from_current_function[H_IDX] = true;
+      asmop *warg = aopArg (ftype, walk2->argreg);
+      wassert (warg);
+      a_dead &= (warg->regs[A_IDX] < 0);
+      hl_dead &= (warg->regs[L_IDX] < 0 && warg->regs[H_IDX] < 0);
+      de_dead &= (warg->regs[E_IDX] < 0 && warg->regs[D_IDX] < 0);
     }
-  else if (size <= 4)
-    {
-      if (size == 4 && ASMOP_RETURN->aopu.aop_reg[0]->rIdx == L_IDX && ASMOP_RETURN->aopu.aop_reg[1]->rIdx == H_IDX &&
-        ASMOP_RETURN->aopu.aop_reg[2]->rIdx == E_IDX && ASMOP_RETURN->aopu.aop_reg[3]->rIdx == D_IDX)
-        {
-          if (!isPairDead (PAIR_DE, ic) && getPairId_o (AOP (IC_LEFT (ic)), 2) != PAIR_DE)
-            {
-              regalloc_dry_run_cost += 100;
-              wassertl (regalloc_dry_run, "Register parameter overwrites value that is still needed");
-            }
-          fetchPairLong (PAIR_DE, AOP (IC_LEFT (ic)), ic, 2);
-          z80_regs_used_as_parms_in_calls_from_current_function[E_IDX] = true;
-          z80_regs_used_as_parms_in_calls_from_current_function[D_IDX] = true;
-          fetchPairLong (PAIR_HL, AOP (IC_LEFT (ic)), ic, 0);
-          z80_regs_used_as_parms_in_calls_from_current_function[L_IDX] = true;
-          z80_regs_used_as_parms_in_calls_from_current_function[H_IDX] = true;
-        }
-      else
-        {
-          for (int i = 0; i < AOP_SIZE (IC_LEFT (ic)); i++)
-            if (!regalloc_dry_run)
-              z80_regs_used_as_parms_in_calls_from_current_function[ASMOP_RETURN->aopu.aop_reg[i]->rIdx] = true;
 
-          genMove_o (ASMOP_RETURN, 0, IC_LEFT (ic)->aop, 0, IC_LEFT (ic)->aop->size, true, true);
-        }
-    }
+  genMove (argreg, IC_LEFT (ic)->aop, a_dead, hl_dead, de_dead, true);
+  
+  for (int i = 0; i < IC_LEFT (ic)->aop->size; i++)
+    if (!regalloc_dry_run)
+      z80_regs_used_as_parms_in_calls_from_current_function[argreg->aopu.aop_reg[i]->rIdx] = true;
 
   freeAsmop (IC_LEFT (ic), NULL);
 }
 
-/** Emit the code for a call statement
- */
 static void
 genCall (const iCode *ic)
 {
@@ -4730,18 +5768,19 @@
   int prestackadjust = 0;
   bool tailjump = false;
 
-  const bool z88dk_callee = IFFUNC_ISZ88DK_CALLEE (ftype);
-
   for (i = 0; i < IYH_IDX + 1; i++)
     z80_regs_preserved_in_calls_from_current_function[i] |= ftype->funcAttrs.preserved_regs[i];
 
   _saveRegsForCall (ic, FALSE);
 
   const bool bigreturn = (getSize (ftype->next) > 4); // Return value of big type or returning struct or union.
-  const bool SomethingReturned = (IS_ITEMP (IC_RESULT (ic)) &&
-                       (OP_SYMBOL (IC_RESULT (ic))->nRegs ||
-                        OP_SYMBOL (IC_RESULT (ic))->spildir ||
-                        OP_SYMBOL (IC_RESULT (ic))->accuse == ACCUSE_A)) || IS_TRUE_SYMOP (IC_RESULT (ic));
+  const bool SomethingReturned = IS_ITEMP (IC_RESULT (ic)) && (OP_SYMBOL (IC_RESULT (ic))->nRegs || OP_SYMBOL (IC_RESULT (ic))->spildir) ||
+                       IS_TRUE_SYMOP (IC_RESULT (ic));
+
+  bool a_free_pre_call = !z80IsParmInCall(ftype, "a");
+  bool hl_free_pre_call = !z80IsParmInCall(ftype, "l") && !z80IsParmInCall(ftype, "h");
+  bool de_free_pre_call = !z80IsParmInCall(ftype, "e") && !z80IsParmInCall(ftype, "d");
+  bool bc_free_pre_call = !z80IsParmInCall(ftype, "c") && !z80IsParmInCall(ftype, "b");
 
   aopOp (IC_LEFT (ic), ic, false, false);
   if (SomethingReturned && !bigreturn)
@@ -4752,47 +5791,89 @@
       PAIR_ID pair;
       int fp_offset, sp_offset;
 
-      if (ic->op == PCALL && IS_GB)
+      if (ic->op == PCALL && IS_SM83 || !hl_free_pre_call)
         _push (PAIR_HL);
-      aopOp (IC_RESULT (ic), ic, FALSE, FALSE);
-      wassert (AOP_TYPE (IC_RESULT (ic)) == AOP_STK || AOP_TYPE (IC_RESULT (ic)) == AOP_EXSTK);
+      aopOp (IC_RESULT (ic), ic, false, false);
+      wassert (IC_RESULT (ic)->aop->type == AOP_STK || IC_RESULT (ic)->aop->type == AOP_EXSTK);
       fp_offset =
-        AOP (IC_RESULT (ic))->aopu.aop_stk + (AOP (IC_RESULT (ic))->aopu.aop_stk >
+        IC_RESULT (ic)->aop->aopu.aop_stk + (IC_RESULT (ic)->aop->aopu.aop_stk >
             0 ? _G.stack.param_offset : 0);
       sp_offset = fp_offset + _G.stack.pushed + _G.stack.offset;
-      pair = (ic->op == PCALL && !IS_GB && !IY_RESERVED) ? PAIR_IY : PAIR_HL;
-      emit2 ("ld %s, !immedword", _pairs[pair].name, sp_offset);
-      emit2 ("add %s, sp", _pairs[pair].name);
-      regalloc_dry_run_cost += (pair == PAIR_IY ? 6 : 4);
-      if (ic->op == PCALL && IS_GB)
+      pair = (ic->op == PCALL && !IS_SM83 && !IY_RESERVED) ? PAIR_IY : PAIR_HL;
+      if (IS_SM83 && sp_offset <= 127 && sp_offset >= -128)
         {
-          emit2 ("ld e, l");
-          emit2 ("ld d, h");
+          emit2 ("!ldahlsp", sp_offset);
           regalloc_dry_run_cost += 2;
-          _pop (PAIR_HL);
-          pair = PAIR_DE;
+        }
+      else
+        {
+          emit2 ("ld %s, !immedword", _pairs[pair].name, sp_offset);
+          emit2 ("add %s, sp", _pairs[pair].name);
+          regalloc_dry_run_cost += (pair == PAIR_IY ? 6 : 4);
+        }
+      if (ic->op == PCALL && IS_SM83 || !hl_free_pre_call)
+        {
+          if (de_free_pre_call)
+            {
+              emit2 ("ld e, l");
+              emit2 ("ld d, h");
+              regalloc_dry_run_cost += 2;
+              _pop (PAIR_HL);
+              pair = PAIR_DE;
+            }
+          else
+            {
+              wassert (bc_free_pre_call);
+              emit2 ("ld c, l");
+              emit2 ("ld b, h");
+              regalloc_dry_run_cost += 2;
+              _pop (PAIR_HL);
+              pair = PAIR_BC;             
+            }
         }
       emit2 ("push %s", _pairs[pair].name);
       regalloc_dry_run_cost += (pair == PAIR_IY ? 2 : 1);
       if (!regalloc_dry_run)
         _G.stack.pushed += 2;
-      freeAsmop (IC_RESULT (ic), NULL);
+      freeAsmop (IC_RESULT (ic), 0);
+      hl_free_pre_call = false;
     }
+
   // Check if we can do tail call optimization.
   else if (!(currFunc && IFFUNC_ISISR (currFunc->type)) &&
-    (!SomethingReturned || IC_RESULT (ic)->aop->size == 1 && aopInReg (IC_RESULT (ic)->aop, 0, IS_GB ? E_IDX : L_IDX) || IC_RESULT (ic)->aop->size == 2 && aopInReg (IC_RESULT (ic)->aop, 0, IS_GB ? DE_IDX : HL_IDX)) &&
-    !ic->parmBytes && !ic->localEscapeAlive && !IFFUNC_ISBANKEDCALL (dtype) && !IFFUNC_ISZ88DK_SHORTCALL (ftype) && _G.omitFramePtr &&
-    (ic->op != PCALL || !IFFUNC_ISZ88DK_FASTCALL (ftype)))
+    (!SomethingReturned || aopInReg (IC_RESULT (ic)->aop, 0, aopRet (ftype)->aopu.aop_reg[0]->rIdx) &&
+      (IC_RESULT (ic)->aop->size <= 1 || aopInReg (IC_RESULT (ic)->aop, 1, aopRet (ftype)->aopu.aop_reg[1]->rIdx)) &&
+      (IC_RESULT (ic)->aop->size <= 2 || aopInReg (IC_RESULT (ic)->aop, 2, aopRet (ftype)->aopu.aop_reg[2]->rIdx)) &&
+      (IC_RESULT (ic)->aop->size <= 3 || aopInReg (IC_RESULT (ic)->aop, 3, aopRet (ftype)->aopu.aop_reg[3]->rIdx)) &&
+      IC_RESULT (ic)->aop->size <= 4) &&
+    !ic->parmBytes &&
+    (!isFuncCalleeStackCleanup (currFunc->type) || !ic->parmEscapeAlive && ic->op == CALL && 0 /* todo: test and enable depending on optimization goal - as done for stm8 - for z80 and r3ka this will be slower and bigger than without tail call optimization, but it saves RAM */) &&
+    !ic->localEscapeAlive &&
+    !IFFUNC_ISBANKEDCALL (dtype) && !IFFUNC_ISZ88DK_SHORTCALL (ftype) &&
+    (_G.omitFramePtr || IS_SM83))
     {
       int limit = 16; // Avoid endless loops in the code putting us into an endless loop here.
 
+      if (isFuncCalleeStackCleanup (currFunc->type))
+        {
+           const bool caller_bigreturn = currFunc->type->next && (getSize (currFunc->type->next) > 4) || IS_STRUCT (currFunc->type->next);
+           int caller_stackparmbytes = caller_bigreturn * 2;
+           for (value *caller_arg = FUNC_ARGS(currFunc->type); caller_arg; caller_arg = caller_arg->next)
+             {
+               wassert (caller_arg->sym);
+               if (!SPEC_REGPARM (caller_arg->etype))
+                 caller_stackparmbytes += getSize (caller_arg->sym->type);
+             }
+           prestackadjust += caller_stackparmbytes;
+        }
+
       for (const iCode *nic = ic->next; nic && --limit;)
         {
           const symbol *targetlabel = 0;
 
           if (nic->op == LABEL)
             ;
-          else if (nic->op == GOTO) // We dont have ebbi here, so we cant jsut use eBBWithEntryLabel (ebbi, ic->label). Search manually.
+          else if (nic->op == GOTO) // We dont have ebbi here, so we cant just use eBBWithEntryLabel (ebbi, ic->label). Search manually.
             targetlabel = IC_LABEL (nic);
           else if (nic->op == RETURN && (!IC_LEFT (nic) || SomethingReturned && IC_RESULT (ic)->key == IC_LEFT (nic)->key))
             targetlabel = returnLabel;
@@ -4802,11 +5883,16 @@
                 {
                   prestackadjust = OP_SYMBOL (IC_LEFT (nic))->stack;
                   tailjump = true;
+                  break;
                 }
+              prestackadjust = 0;
               break;
             }
           else
-            break;
+            {
+              prestackadjust = 0;
+              break;
+            }
 
           if (targetlabel)
             {
@@ -4819,7 +5905,11 @@
                   if (nnic->op == LABEL && IC_LABEL (nnic)->key == targetlabel->key)
                     break;
               if (!nnic)
-                break;
+                {
+                  prestackadjust = 0;
+                  tailjump = false;
+                  break;
+                }
 
               nic = nnic;
             }
@@ -4836,56 +5926,106 @@
         {
           werror (W_INDIR_BANKED);
         }
-      else if (IFFUNC_ISZ88DK_SHORTCALL (ftype)) 
+      else if (IFFUNC_ISZ88DK_SHORTCALL (ftype))
        {
           wassertl(0, "__z88dk_short_call via function pointer not implemented");
        }
 
-      if (isLitWord (AOP (IC_LEFT (ic))))
+      if (isLitWord (IC_LEFT (ic)->aop))
         {
-          adjustStack (prestackadjust, false, false, false, false);
-          emit2 (jump ? "jp %s" : "call %s", aopGetLitWordLong (AOP (IC_LEFT (ic)), 0, FALSE));
+          adjustStack (prestackadjust, a_free_pre_call, bc_free_pre_call, de_free_pre_call, hl_free_pre_call, false);
+          emit2 (jump ? "jp %s" : "call %s", aopGetLitWordLong (IC_LEFT (ic)->aop, 0, FALSE));
           regalloc_dry_run_cost += 3;
         }
-      else if (getPairId (AOP (IC_LEFT (ic))) != PAIR_IY && !IFFUNC_ISZ88DK_FASTCALL (ftype))
+      else if (getPairId (IC_LEFT (ic)->aop) != PAIR_IY && hl_free_pre_call)
         {
           spillPair (PAIR_HL);
-          fetchPairLong (PAIR_HL, AOP (IC_LEFT (ic)), ic, 0);
-          adjustStack (prestackadjust, false, false, false, false);
-          emit2 (jump ? "jp (hl)" : "call ___sdcc_call_hl");
+          genMove (ASMOP_HL, IC_LEFT (ic)->aop, a_free_pre_call, hl_free_pre_call, de_free_pre_call, true);
+          adjustStack (prestackadjust, a_free_pre_call, bc_free_pre_call, de_free_pre_call, false, false);
+          emit2 (jump ? "!jphl" : "call ___sdcc_call_hl");
           regalloc_dry_run_cost += 3;
         }
-      else if (!IS_GB && !IY_RESERVED)
+      else if (!IS_SM83 && !IY_RESERVED && !z80IsParmInCall (ftype, "iy"))
         {
           spillPair (PAIR_IY);
-          fetchPairLong (PAIR_IY, IC_LEFT (ic)->aop, ic, 0);
-          adjustStack (prestackadjust, false, false, false, false);
+          genMove (ASMOP_IY, IC_LEFT (ic)->aop, a_free_pre_call, hl_free_pre_call, de_free_pre_call, true);
+          adjustStack (prestackadjust, a_free_pre_call, bc_free_pre_call, de_free_pre_call, hl_free_pre_call, false);
           emit2 (jump ? "jp (iy)" : "call ___sdcc_call_iy");
           regalloc_dry_run_cost += 3;
         }
-      else // Use bc, since it is the only 16-bit register guarateed to be free even for __z88dk_fastcall with --reserve-regs-iy
+      else if (bc_free_pre_call) // Try bc, since it is the only 16-bit register guarateed to be free even for __z88dk_fastcall with --reserve-regs-iy
         {
           wassert (!prestackadjust);
-          wassert (IY_RESERVED); // The peephole optimizer handles ret for purposes other than returning only for --reserve-regs-iy
+          wassert (IY_RESERVED || IS_SM83); // The peephole optimizer handles ret for purposes other than returning only for --reserve-regs-iy
+          symbol *tlbl = 0;
           if (aopInReg (IC_LEFT (ic)->aop, 0, B_IDX) || aopInReg (IC_LEFT (ic)->aop, 0, C_IDX) || aopInReg (IC_LEFT (ic)->aop, 1, B_IDX) || aopInReg (IC_LEFT (ic)->aop, 1, C_IDX))
             {
-              regalloc_dry_run_cost += 100;
-              wassertl (regalloc_dry_run, "Unimplemented function pointer in bc");
+              if (!de_free_pre_call)
+                UNIMPLEMENTED;
+              if (!regalloc_dry_run)
+                {
+                  tlbl = newiTempLabel (NULL);
+                  emit2 ("ld de, !immed!tlabel", labelKey2num (tlbl->key));
+                  _push (PAIR_DE);
+                }
             }
-          symbol *tlbl = 0;
-          if (!regalloc_dry_run)
+          else if (!regalloc_dry_run)
             {
-              tlbl = newiTempLabel (NULL);
-              emit2 ("ld bc, #!tlabel", labelKey2num (tlbl->key));
-              emit2 ("push bc");
-              regalloc_dry_run_cost += 4;
+              if (!regalloc_dry_run)
+                {
+                  tlbl = newiTempLabel (NULL);
+                  emit2 ("ld bc, !immed!tlabel", labelKey2num (tlbl->key));
+                  _push (PAIR_BC);
+                }
             }
-          fetchPairLong (PAIR_BC, IC_LEFT (ic)->aop, 0, 0);
+          regalloc_dry_run_cost += 3;
+          genMove (ASMOP_BC, IC_LEFT (ic)->aop, z80IsParmInCall(ftype, "a"), hl_free_pre_call, de_free_pre_call, true);
           emit2 ("push bc");
           emit2 ("ret");
+          if (!regalloc_dry_run)
+            _G.stack.pushed -= 2;
           regalloc_dry_run_cost += 2;
           if (tlbl)
-            emit2 ("!tlabeldef", labelKey2num (tlbl->key));
+            emitLabel (tlbl);
+        }
+      else if (de_free_pre_call) // Try de.
+        {
+          wassert (!prestackadjust);
+          wassert (IY_RESERVED || IS_SM83); // The peephole optimizer handles ret for purposes other than returning only for --reserve-regs-iy
+          symbol *tlbl = 0;
+          if (aopInReg (IC_LEFT (ic)->aop, 0, D_IDX) || aopInReg (IC_LEFT (ic)->aop, 0, E_IDX) || aopInReg (IC_LEFT (ic)->aop, 1, D_IDX) || aopInReg (IC_LEFT (ic)->aop, 1, E_IDX))
+            {
+              if (!bc_free_pre_call)
+                UNIMPLEMENTED;
+              if (!regalloc_dry_run)
+                {
+                  tlbl = newiTempLabel (NULL);
+                  emit2 ("ld bc, !immed!tlabel", labelKey2num (tlbl->key));
+                  _push (PAIR_BC);
+                }
+            }
+          else if (!regalloc_dry_run)
+            {
+              if (!regalloc_dry_run)
+                {
+                  tlbl = newiTempLabel (NULL);
+                  emit2 ("ld de, !immed!tlabel", labelKey2num (tlbl->key));
+                  _push (PAIR_DE);
+                }
+            }
+          regalloc_dry_run_cost += 3;
+          genMove (ASMOP_DE, IC_LEFT (ic)->aop, z80IsParmInCall(ftype, "a"), hl_free_pre_call, true, true);
+          emit2 ("push de");
+          emit2 ("ret");
+          if (!regalloc_dry_run)
+            _G.stack.pushed -= 2;
+          regalloc_dry_run_cost += 2;
+          if (tlbl)
+            emitLabel (tlbl);
+        }
+      else
+        {
+          wassert (0);
         }
     }
   else
@@ -4896,29 +6036,59 @@
           wassert (!prestackadjust);
 
           char *name = OP_SYMBOL (IC_LEFT (ic))->rname[0] ? OP_SYMBOL (IC_LEFT (ic))->rname : OP_SYMBOL (IC_LEFT (ic))->name;
-          emit2 ("call banked_call");
-          emit2 ("!dws", name);
-          emit2 ("!dw !bankimmeds", name);
-          regalloc_dry_run_cost += 6;
+          /* there 3 types of banked call:
+               legacy - only if --legacy-banking is specified
+               a:bc - only for __z88dk_fastcall __banked functions
+               e:hl - default (may have optimal bank switch routine) */
+          if (z80_opts.legacyBanking)
+            {
+              emit2 ("call ___sdcc_bcall");
+              emit2 ("!dws", name);
+              emit2 ("!dw !bankimmeds", name);
+              regalloc_dry_run_cost += 7;
+            }
+          else if (IFFUNC_ISZ88DK_FASTCALL (ftype))
+            {
+              spillPair (PAIR_BC);
+              emit2 ("ld a, !hashedbankimmeds", name);
+              emit2 ("ld bc, !hashedstr", name);
+              emit2 ("call ___sdcc_bcall_abc");
+              regalloc_dry_run_cost += 8;
+            }
+          else
+            {
+              spillPair (PAIR_DE);
+              spillPair (PAIR_HL);
+              emit2 ("ld e, !hashedbankimmeds", name);
+              emit2 ("ld hl, !hashedstr", name);
+              emit2 ("call ___sdcc_bcall_ehl");
+              regalloc_dry_run_cost += 8;
+            }
         }
       else
         {
-          adjustStack (prestackadjust, false, false, false, false);
+          if (isFuncCalleeStackCleanup (currFunc->type) && prestackadjust && !IFFUNC_ISNORETURN (ftype)) // Copy return value into correct location on stack for tail call optimization.
+            {
+              wassert (0);
+              /* todo: implement */
+            }
+
+          adjustStack (prestackadjust, false, bc_free_pre_call, de_free_pre_call, hl_free_pre_call, false);
 
           if (IS_LITERAL (etype))
             {
-              emit2 (jump ? "jp 0x%04X" : "call 0x%04X", ulFromVal (OP_VALUE (IC_LEFT (ic))));
+              emit2 (jump ? "jp !constword" : "call !constword", ulFromVal (OP_VALUE (IC_LEFT (ic))));
               regalloc_dry_run_cost += 3;
             }
-          else if (IFFUNC_ISZ88DK_SHORTCALL(ftype)) 
+          else if (IFFUNC_ISZ88DK_SHORTCALL(ftype))
             {
               int rst = ftype->funcAttrs.z88dk_shortcall_rst;
               int value = ftype->funcAttrs.z88dk_shortcall_val;
-              emit2 ("rst 0x%02x", rst);
-              if ( value < 256 ) 
-                emit2 ("defb 0x%02x\n",value);
+              emit2 ("rst !constbyte", rst);
+              if ( value < 256 )
+                emit2 ("defb !constbyte\n",value);
               else
-                emit2 ("defw 0x%04x\n",value);
+                emit2 ("defw !constword\n",value);
               regalloc_dry_run_cost += 3;
             }
           else
@@ -4936,20 +6106,26 @@
   _G.stack.pushed += prestackadjust;
 
   /* Mark the registers as restored. */
-  _G.saves.saved = FALSE;
+  _G.saves.saved = false;
 
   /* adjust the stack for parameters if required */
-  if ((ic->parmBytes || bigreturn) && (IFFUNC_ISNORETURN (ftype) || z88dk_callee))
+  if ((ic->parmBytes || bigreturn) && (IFFUNC_ISNORETURN (ftype) || isFuncCalleeStackCleanup (ftype)))
     {
       if (!regalloc_dry_run)
         {
           _G.stack.pushed -= (ic->parmBytes + bigreturn * 2);
-          z80_symmParm_in_calls_from_current_function = FALSE;
+          z80_symmParm_in_calls_from_current_function = false;
         }
     }
   else if ((ic->parmBytes || bigreturn))
     {
-      adjustStack (ic->parmBytes + bigreturn * 2, !IS_TLCS90, TRUE, !SomethingReturned || bigreturn, !IY_RESERVED);
+      bool return_in_reg = SomethingReturned && !bigreturn;
+      adjustStack (ic->parmBytes + bigreturn * 2,
+        !return_in_reg || !aopRet (ftype) || aopRet (ftype)->regs[A_IDX] < 0 || aopRet (ftype)->regs[A_IDX] > IC_RESULT (ic)->aop->size,
+        !return_in_reg || !aopRet (ftype) || (aopRet (ftype)->regs[C_IDX] < 0 || aopRet (ftype)->regs[C_IDX] > IC_RESULT (ic)->aop->size) && (aopRet (ftype)->regs[B_IDX] < 0 || aopRet (ftype)->regs[B_IDX] > IC_RESULT (ic)->aop->size),
+        !return_in_reg || !aopRet (ftype) || (aopRet (ftype)->regs[E_IDX] < 0 || aopRet (ftype)->regs[E_IDX] > IC_RESULT (ic)->aop->size) && (aopRet (ftype)->regs[D_IDX] < 0 || aopRet (ftype)->regs[D_IDX] > IC_RESULT (ic)->aop->size),
+        !return_in_reg || !aopRet (ftype) || (aopRet (ftype)->regs[L_IDX] < 0 || aopRet (ftype)->regs[L_IDX] > IC_RESULT (ic)->aop->size) && (aopRet (ftype)->regs[H_IDX] < 0 || aopRet (ftype)->regs[H_IDX] > IC_RESULT (ic)->aop->size),
+        !IY_RESERVED);
 
       if (regalloc_dry_run)
         _G.stack.pushed += ic->parmBytes + bigreturn * 2;
@@ -4958,9 +6134,9 @@
   /* if we need assign a result value */
   if (SomethingReturned && !bigreturn)
     {
-      assignResultValue (IC_RESULT (ic));
+      genMove (IC_RESULT (ic)->aop, aopRet (ftype), true, true, true, true);
 
-      freeAsmop (IC_RESULT (ic), NULL);
+      freeAsmop (IC_RESULT (ic), 0);
     }
 
   spillCached ();
@@ -5024,11 +6200,25 @@
   emitDebug (z80_assignment_optimal ? "; Register assignment is optimal." : "; Register assignment might be sub-optimal.");
   emitDebug ("; Stack space usage: %d bytes.", sym->stack);
 
+  if (IFFUNC_BANKED (sym->type))
+    {
+      int bank_number = 0;
+      for (int i  = strlen (options.code_seg)-1; i >= 0; i--)
+        {
+          if (!isdigit (options.code_seg[i]) && options.code_seg[i+1] != '\0')
+            {
+              bank_number = atoi (&options.code_seg[i+1]);
+              break;
+            }
+        }
+      emit2("!bequ", sym->rname, bank_number);
+    }
+
   if (IS_STATIC (sym->etype))
     emit2 ("!functionlabeldef", sym->rname);
   else
     emit2 ("!globalfunctionlabeldef", sym->rname);
- 
+
   if (!regalloc_dry_run)
     genLine.lineCurr->isLabel = 1;
 
@@ -5057,15 +6247,21 @@
          If critical function then turn interrupts off */
       if (IFFUNC_ISCRITICAL (sym->type))
         {
-          if (IS_GB || IS_RAB || IS_TLCS90)
+          if (IS_SM83 || IS_RAB || IS_TLCS90)
             {
               emit2 ("!di");
             }
           else
             {
-              //get interrupt enable flag IFF2 into P/O
-              emit2 ("ld a,i");
-              emit2 ("!di");
+              if (z80_opts.nmosZ80)
+                emit2 ("call ___sdcc_critical_enter");
+              else
+                {
+                  //get interrupt enable flag IFF2 into P/O
+                  emit2 ("ld a,i");
+                  //disable interrupts
+                  emit2 ("!di");
+                }
               //save P/O flag
               emit2 ("push af");
               _G.stack.param_offset += 2;
@@ -5073,11 +6269,6 @@
         }
     }
 
-  if (options.profile)
-    {
-      emit2 ("!profileenter");
-    }
-
   if (z80_opts.calleeSavesBC)
     {
       bcInUse = TRUE;
@@ -5099,9 +6290,9 @@
                   break;
                 case D_IDX:
                 case E_IDX:
-                  if (!IS_GB)
+                  if (!IS_SM83)
                     {
-                      deInUse = TRUE;
+                      deInUse = true;
                     }
                   else
                     {
@@ -5146,48 +6337,66 @@
     }
   sym = OP_SYMBOL (IC_LEFT (ic));
 
-  _G.omitFramePtr = options.oldralloc ? (!IS_GB && options.omitFramePtr) : should_omit_frame_ptr;
+  _G.omitFramePtr = should_omit_frame_ptr;
 
-  if (!IS_GB && !z80_opts.noOmitFramePtr && !stackParm && !sym->stack)
+  if (!IS_SM83 && !z80_opts.noOmitFramePtr && !stackParm && !sym->stack)
     {
       if (!regalloc_dry_run)
-        _G.omitFramePtr = TRUE;
+        _G.omitFramePtr = true;
     }
   else if (sym->stack)
     {
-      if (!_G.omitFramePtr)
-        emit2 ((optimize.codeSize && !IFFUNC_ISZ88DK_FASTCALL (ftype)) ? "!enters" : "!enter");
-      if (IS_EZ80_Z80 && !_G.omitFramePtr && -sym->stack > -128 && -sym->stack <= -3 && !IFFUNC_ISZ88DK_FASTCALL (ftype))
+      if (IS_EZ80_Z80 && !_G.omitFramePtr && -sym->stack > -128 && -sym->stack <= -3 && (z80IsParmInCall (sym->type, "l") || z80IsParmInCall (sym->type, "h")))
         {
-          emit2 ("lea hl, ix, #%d", -sym->stack);
-          emit2 ("ld sp, hl");
-          regalloc_dry_run_cost += 4;
+          emit2 ("push ix");
+          emit2 ("ld ix, !immed%d", -sym->stack);
+          emit2 ("add ix, sp");
+          emit2 ("ld sp, ix");
+          emit2 ("lea ix, ix, !immed%d", sym->stack);
+          regalloc_dry_run_cost += 3;
         }
       else
-        adjustStack (-sym->stack, !IS_TLCS90, TRUE, !IFFUNC_ISZ88DK_FASTCALL (ftype), !IY_RESERVED);
+        {
+          if (!_G.omitFramePtr)
+            emit2 ((optimize.codeSize && !z80IsParmInCall (sym->type, "l") && !z80IsParmInCall (sym->type, "h")) ? "!enters" : "!enter");
+          if (IS_EZ80_Z80 && !_G.omitFramePtr && -sym->stack > -128 && -sym->stack <= -3 && !z80IsParmInCall (sym->type, "l") && !z80IsParmInCall (sym->type, "h"))
+            {
+              emit2 ("lea hl, ix, !immed%d", -sym->stack);
+              emit2 ("ld sp, hl");
+              regalloc_dry_run_cost += 4;
+            }
+          else
+            adjustStack (-sym->stack, !z80IsParmInCall (sym->type, "a"), !z80IsParmInCall (sym->type, "c") && !z80IsParmInCall (sym->type, "v"), !z80IsParmInCall (sym->type, "e") && !z80IsParmInCall (sym->type, "d"), !z80IsParmInCall (sym->type, "l") && !z80IsParmInCall (sym->type, "h"), !IY_RESERVED);
+        }
       _G.stack.pushed = 0;
     }
   else if (!_G.omitFramePtr)
     {
-      emit2 ((optimize.codeSize && !IFFUNC_ISZ88DK_FASTCALL (ftype)) ? "!enters" : "!enter");
+      emit2 ((optimize.codeSize && !z80IsParmInCall (sym->type, "l") && !z80IsParmInCall (sym->type, "h")) ? "!enters" : "!enter"); // !enters might result in a function call to a helper function.
     }
 
   _G.stack.offset = sym->stack;
+  
+  for (PAIR_ID pairId = 0; pairId < NUM_PAIRS; pairId++)
+    spillPair (pairId);
 }
 
 /*-----------------------------------------------------------------*/
 /* genEndFunction - generates epilogue for functions               */
 /*-----------------------------------------------------------------*/
 static void
-genEndFunction (iCode * ic)
+genEndFunction (iCode *ic)
 {
   symbol *sym = OP_SYMBOL (IC_LEFT (ic));
-  int retsize = getSize (sym->type->next);
   /* __critical __interrupt without an interrupt number is the non-maskable interrupt */
-  bool is_nmi = (IS_Z80 || IS_Z180 || IS_EZ80_Z80) && IFFUNC_ISCRITICAL (sym->type) && FUNC_INTNO (sym->type) == INTNO_UNSPEC; 
+  bool is_nmi = (IS_Z80 || IS_Z180 || IS_EZ80_Z80 || IS_Z80N) && IFFUNC_ISCRITICAL (sym->type) && FUNC_INTNO (sym->type) == INTNO_UNSPEC;
+  bool bc_free = !aopRet (sym->type) || aopRet (sym->type)->regs[C_IDX] < 0 && aopRet (sym->type)->regs[B_IDX] < 0;
+  bool de_free = !aopRet (sym->type) || aopRet (sym->type)->regs[E_IDX] < 0 && aopRet (sym->type)->regs[D_IDX] < 0;
+  bool hl_free = !aopRet (sym->type) || aopRet (sym->type)->regs[L_IDX] < 0 && aopRet (sym->type)->regs[H_IDX] < 0;
+  bool iy_free = !IY_RESERVED && (!aopRet (sym->type) || aopRet (sym->type)->regs[IYL_IDX] < 0 && aopRet (sym->type)->regs[IYH_IDX] < 0);
 
   wassert (!regalloc_dry_run);
-  wassertl (!_G.stack.pushed, "Unbalanced stack.");
+  //wassertl (!_G.stack.pushed, "Unbalanced stack.");
 
   if (IFFUNC_ISNAKED (sym->type) || IFFUNC_ISNORETURN (sym->type))
     {
@@ -5195,47 +6404,87 @@
       return;
     }
 
-  wassertl(regalloc_dry_run || !IFFUNC_ISZ88DK_CALLEE(sym->type), "Unimplemented __z88dk_callee support on callee side");
-
-  if (!IS_GB && !_G.omitFramePtr && sym->stack > (optimize.codeSize ? 2 : 1))
+  const bool bigreturn = (getSize (sym->type->next) > 4) || IS_STRUCT (sym->type->next);
+  int stackparmbytes = bigreturn * 2;
+  for (value *arg = FUNC_ARGS(sym->type); arg; arg = arg->next)
+    {
+      wassert (arg->sym);
+      int argsize = getSize (arg->sym->type);
+      if (argsize == 1 && FUNC_ISSMALLC (sym->type)) // SmallC calling convention passes 8-bit stack arguments as 16 bit.
+        argsize++;
+      if (!SPEC_REGPARM (arg->etype))
+        stackparmbytes += argsize;
+    }
+
+  int poststackadjust = isFuncCalleeStackCleanup (sym->type) ? stackparmbytes : 0;
+
+  if (poststackadjust && // Try to merge both stack adjustments.
+    _G.omitFramePtr &&
+    (IS_RAB && _G.stack.offset <= 255 || IS_TLCS90 && _G.stack.offset <= 127) &&
+    (hl_free || iy_free) && 
+    !_G.calleeSaves.pushedDE && !_G.calleeSaves.pushedBC &&
+    !IFFUNC_ISISR (sym->type) && !IFFUNC_ISCRITICAL (sym->type))
+    {
+      emit2 (hl_free ? "ld hl, %d (sp)" : "ld iy, %d (sp)", _G.stack.offset);
+      regalloc_dry_run_cost += 2 + !hl_free;
+      adjustStack (_G.stack.offset + 2 + poststackadjust,
+      !aopRet (sym->type)  || aopRet (sym->type)->regs[A_IDX] < 0,
+      bc_free,
+      de_free,
+      false,
+      iy_free && hl_free);
+      emit2 (hl_free ? "jp (hl)" : "jp (iy)");
+      regalloc_dry_run_cost += 2;
+      goto done;
+    }
+  else if (!IS_SM83 && !_G.omitFramePtr && sym->stack > (optimize.codeSize ? 2 : 1))
     {
       emit2 ("ld sp, ix");
       cost2 (2, 10, 7, 4, 0, 6, 2);
     }
   else
-    adjustStack (_G.stack.offset, !IS_TLCS90, TRUE, retsize == 0 || retsize > 4, !IY_RESERVED);
+    adjustStack (_G.stack.offset,
+      !aopRet (sym->type)  || aopRet (sym->type)->regs[A_IDX] < 0,
+      bc_free,
+      de_free,
+      hl_free,
+      iy_free);
 
-  if(!IS_GB && !_G.omitFramePtr)
-    emit2 ("pop ix");
+  if(!IS_SM83 && !_G.omitFramePtr)
+    {
+      emit2 ("pop ix");
+      regalloc_dry_run_cost += 2;
+    }
 
+  wassertl(regalloc_dry_run || !(isFuncCalleeStackCleanup (sym->type) && (_G.calleeSaves.pushedDE || _G.calleeSaves.pushedBC)), "Unimplemented __z88dk_callee support for calle-saved bc/de on callee side");
   if (_G.calleeSaves.pushedDE)
     {
       emit2 ("pop de");
+      regalloc_dry_run_cost++;
       _G.calleeSaves.pushedDE = FALSE;
     }
 
   if (_G.calleeSaves.pushedBC)
     {
       emit2 ("pop bc");
+      regalloc_dry_run_cost++;
       _G.calleeSaves.pushedBC = FALSE;
     }
 
-  if (options.profile)
-    {
-      emit2 ("!profileexit");
-    }
-
   /* if this is an interrupt service routine
-     then save all potentially used registers. */
+     then restore all potentially used registers. */
   if (IFFUNC_ISISR (sym->type))
-    emit2 ("!popa");
+    {
+      emit2 ("!popa");
+      regalloc_dry_run_cost++;
+    }
   else
     {
       /* This is a non-ISR function.
          If critical function then turn interrupts back on */
       if (IFFUNC_ISCRITICAL (sym->type))
         {
-          if (IS_GB || IS_TLCS90)
+          if (IS_SM83 || IS_TLCS90)
             emit2 ("!ei");
           else if (IS_RAB)
             emit2 ("ipres");
@@ -5243,6 +6492,13 @@
             {
               symbol *tlbl = newiTempLabel (NULL);
               //restore P/O flag
+              if (aopRet (sym->type) && aopRet (sym->type)->regs[A_IDX] >= 0) // Preserve return value in a.
+                {
+                  wassert (!IS_SM83);
+                  emit2 ("ex (sp), hl");
+                  emit2 ("ld h, a");
+                  emit2 ("ex (sp), hl");
+                }
               emit2 ("pop af");
               //parity odd <==> P/O=0 <==> interrupt enable flag IFF2 was 0 <==>
               //don't enable interrupts as they were off before
@@ -5254,43 +6510,134 @@
         }
     }
 
-  if (options.debug && currFunc)
+  if (poststackadjust)
     {
-      debugFile->writeEndFunction (currFunc, ic, 1);
-    }
+      wassertl(regalloc_dry_run || !IFFUNC_ISBANKEDCALL (sym->type), "Unimplemented __banked __z88dk_callee support on callee side");
+      wassertl(regalloc_dry_run || !IFFUNC_HASVARARGS (sym->type), "__z88dk_callee function may to have variable arguments");
 
-  if (IFFUNC_ISISR (sym->type))
-    {
-      if (is_nmi)
-        emit2 ("retn");
-      else if (IS_RAB && IFFUNC_ISCRITICAL (sym->type) && FUNC_INTNO (sym->type) == INTNO_UNSPEC)
+      if (hl_free && !IFFUNC_ISISR (sym->type))
         {
-          emit2 ("ipres");
-          emit2 ("ret");
+          _pop (PAIR_HL);
+          adjustStack (poststackadjust,
+          !aopRet (sym->type) || aopRet (sym->type)->regs[A_IDX] < 0, bc_free, de_free, false, iy_free);
+          emit2 ("jp (hl)");
+          regalloc_dry_run_cost++;
+          goto done;
         }
-      else if (IS_GB)
-        emit2 (IFFUNC_ISCRITICAL (sym->type) ? "reti" : "ret");
-      else
+      else if (!IS_SM83 && iy_free && !!IFFUNC_ISISR (sym->type))
         {
-          if (IFFUNC_ISCRITICAL (sym->type) && !is_nmi)
-            emit2 ("!ei");
-          emit2 ("reti");
+          _pop (PAIR_IY);
+          adjustStack (poststackadjust, !aopRet (sym->type) || aopRet (sym->type)->regs[A_IDX] < 0, bc_free, de_free, hl_free, false);
+          emit2 ("jp (iy)");
+          regalloc_dry_run_cost += 2;
+          goto done;
         }
-    }
-  else
-    {
-      /* Both banked and non-banked just ret */
-      emit2 ("ret");
-    }
-
-  _G.flushStatics = 1;
-  _G.stack.pushed = 0;
-  _G.stack.offset = 0;
-}
-
-/*-----------------------------------------------------------------*/
-/* genRet - generate code for return statement                     */
-/*-----------------------------------------------------------------*/
+      else if (bc_free || de_free)
+       {
+         _pop (bc_free ? PAIR_BC : PAIR_DE);
+         adjustStack (poststackadjust, !aopRet (sym->type) || aopRet (sym->type)->regs[A_IDX] < 0, false, bc_free && de_free, false, false);
+         _push (bc_free ? PAIR_BC : PAIR_DE);
+       }
+      else // Do it the hard way: Copy return address on stack before stack pointer adjustment.
+        {
+          if (poststackadjust == 1)
+            {
+              emit2 ("push hl");
+              emit2 ("push de");
+              emit2 ("ld hl, !immedword", 4);
+              emit2 ("add hl, sp");
+              emit2 ("ld e, (hl)");
+              emit2 ("inc hl");
+              emit2 ("ld d, (hl)");
+              emit2 ("ld (hl), e");
+              emit2 ("inc hl");
+              emit2 ("ld (hl), d");
+              emit2 ("pop de");
+              emit2 ("pop hl");
+              regalloc_dry_run_cost += 14;
+            }
+          else if (IS_SM83)
+            {
+              emit2 ("push hl");
+              emit2 ("push de");
+              emit2 ("!ldahlsp", 4);
+              emit2 ("ld e, (hl)");
+              emit2 ("inc hl");
+              emit2 ("ld d, (hl)");
+              emit2 ("ld hl, !immedword", 4 +  poststackadjust);
+              emit2 ("add hl, sp");
+              emit2 ("ld (hl), e");
+              emit2 ("inc hl");
+              emit2 ("ld (hl), d");
+              emit2 ("pop de");
+              emit2 ("pop hl");
+              regalloc_dry_run_cost += 16;
+            }
+          else
+            {
+              wassert (!IS_SM83);
+              wassert (stackparmbytes != 1); // Avoid overwriting return address and hl.
+              emit2 ("ex (sp), hl");
+              emit2 ("push de");
+              emit2 ("ex de, hl");
+              emit2 ("ld hl, !immedword", 2 +  poststackadjust);
+              emit2 ("add hl, sp");
+              emit2 ("ld (hl), e");
+              emit2 ("inc hl");
+              emit2 ("ld (hl), d");
+              emit2 ("pop de");
+              emit2 ("ex (sp), hl");
+              regalloc_dry_run_cost += 12;
+            }
+
+          adjustStack (poststackadjust,
+          !aopRet (sym->type) || aopRet (sym->type)->regs[A_IDX] < 0,
+          bc_free,
+          de_free,
+          false,
+          iy_free);
+        }
+    }
+
+  if (options.debug && currFunc)
+    {
+      debugFile->writeEndFunction (currFunc, ic, 1);
+    }
+
+  if (IFFUNC_ISISR (sym->type))
+    {
+      if (is_nmi)
+        emit2 ("retn");
+      else if (IS_RAB && IFFUNC_ISCRITICAL (sym->type) && FUNC_INTNO (sym->type) == INTNO_UNSPEC)
+        {
+          emit2 ("ipres");
+          emit2 ("ret");
+        }
+      else if (IS_SM83)
+        emit2 (IFFUNC_ISCRITICAL (sym->type) ? "reti" : "ret");
+      else
+        {
+          if (IFFUNC_ISCRITICAL (sym->type) && !is_nmi)
+            emit2 ("!ei");
+          emit2 ("reti");
+        }
+    }
+  else
+    {
+      /* Both banked and non-banked just ret */
+      emit2 ("ret");
+      regalloc_dry_run_cost++;
+    }
+
+done:
+  _G.flushStatics = 1;
+  _G.stack.pushed = 0;
+  _G.stack.offset = 0;
+}
+
+/*-----------------------------------------------------------------*/
+/* genRet - generate code for return statement                     */
+/*-----------------------------------------------------------------*/
 static void
 genRet (const iCode *ic)
 {
@@ -5306,57 +6653,103 @@
   /* we have something to return then
      move the return value into place */
   aopOp (IC_LEFT (ic), ic, FALSE, FALSE);
-  size = AOP_SIZE (IC_LEFT (ic));
+  size = IC_LEFT (ic)->aop->size;
 
-  if (size == 2)
-    {
-      fetchPairLong (IS_GB ? PAIR_DE : PAIR_HL, AOP (IC_LEFT (ic)), ic, 0);
-    }
-  else if (size <= 4)
+  if (size <= 4)
     {
-      if (IS_GB && size == 4 && requiresHL (AOP (IC_LEFT (ic))))
-        {
-          fetchPairLong (PAIR_DE, AOP (IC_LEFT (ic)), 0, 0);
-          fetchPairLong (PAIR_HL, AOP (IC_LEFT (ic)), 0, 2);
-        }
-      else if (AOP_TYPE (IC_LEFT (ic)) == AOP_REG)
-        genMove_o (ASMOP_RETURN, 0, IC_LEFT (ic)->aop, 0, IC_LEFT (ic)->aop->size, true, true);
-      else
-        {
-          bool skipbytes[4] = {false, false, false, false}; // Take care to not overwrite hl.
-          for (offset = 0; offset < size; offset++)
+      /* TODO: get this working with floats */
+      if (IC_LEFT (ic)->aop->type == AOP_LIT && size == 4 && !IS_FLOAT (IC_LEFT (ic)->aop->aopu.aop_lit->type) &&
+        (aopRet (currFunc->type) == ASMOP_DEHL || aopRet (currFunc->type) == ASMOP_HLDE))
+        {
+          /* if we have to use two register pairs
+             we can reuse values, this is also a prototype
+             for the later literal on stack case */
+          /* double load is slower, if one is immd, than 2B immd load,
+             so we have to make sure both can be reused */
+          bool first = false;
+          unsigned char value[4];
+          PAIR_ID regpairs[2];
+          unsigned char offset[2] = {0, 2};
+          unsigned long lit = ulFromVal (IC_LEFT (ic)->aop->aopu.aop_lit);
+          value[0] = lit&0xff;
+          lit>>=8;
+          value[1] = lit&0xff;
+          lit>>=8;
+          value[2] = lit&0xff;
+          lit>>=8;
+          value[3] = lit&0xff;
+
+          if(aopRet (currFunc->type) == ASMOP_HLDE)
+            {
+              regpairs[0] = PAIR_DE;
+              regpairs[1] = PAIR_HL;
+            }
+          else
             {
-              if (requiresHL (AOP (IC_LEFT (ic))) && (ASMOP_RETURN->aopu.aop_reg[offset]->rIdx == H_IDX || ASMOP_RETURN->aopu.aop_reg[offset]->rIdx == L_IDX))
-                {
-                  skipbytes[offset] = true;
-                  continue;
-                }
-              cheapMove (ASMOP_RETURN, offset, IC_LEFT (ic)->aop, offset, true);
+              regpairs[0] = PAIR_HL;
+              regpairs[1] = PAIR_DE;
+            }
+
+          /* swap if first pair can't hold the immd */
+          if(value[0] == value[1] && value[2] != value[3])
+            {
+              PAIR_ID tmpair = regpairs[0];
+              regpairs[0] = regpairs[1];
+              regpairs[1] = tmpair;
+
+              unsigned char tmp = value[0];
+              value[0] = value[2];
+              value[2] = tmp;
+              tmp = value[1];
+              value[1] = value[3];
+              value[3] = tmp;
+
+              tmp = offset[0];
+              offset[0] = offset[1];
+              offset[1] = tmp;
+            }
+          
+          fetchPairLong (regpairs[0], IC_LEFT (ic)->aop, 0, offset[0]);
+          if(value[2] == value[0])
+            {
+              emit2 ("ld %s, %s", _pairs[regpairs[1]].l, _pairs[regpairs[0]].l);
+              first = true;
+            }
+          else if(value[2] == value[1])
+            {
+              emit2 ("ld %s, %s", _pairs[regpairs[1]].l, _pairs[regpairs[0]].h);
+              first = true;
+            }
+          
+          if(value[3] == value[0] && first == true)
+            {
+              emit2 ("ld %s, %s", _pairs[regpairs[1]].h, _pairs[regpairs[0]].l);
+            }
+          else if(value[3] == value[1] && first == true)
+            {
+              emit2 ("ld %s, %s", _pairs[regpairs[1]].h, _pairs[regpairs[0]].h);
+            }
+          else
+            {
+              /* Makes previous loads redundant, which
+                 will be optimized by peep hole rules */
+              fetchPairLong (regpairs[1], IC_LEFT (ic)->aop, 0, offset[1]);
             }
-          for (offset = 0; offset < size; offset++)
-            if (skipbytes[offset] && offset + 1 < size && ASMOP_RETURN->aopu.aop_reg[offset]->rIdx == L_IDX && ASMOP_RETURN->aopu.aop_reg[offset + 1]->rIdx == H_IDX)
-              {
-                fetchPairLong (PAIR_HL, IC_LEFT (ic)->aop, 0, offset);
-                break;
-              }
-            else if (skipbytes[offset])
-              {
-                cheapMove (ASMOP_RETURN, offset, IC_LEFT (ic)->aop, offset, true);
-              }
         }
+      else if (size > 0) // SDCC supports GCC extension of returning void
+        genMove (aopRet (currFunc->type), IC_LEFT (ic)->aop, true, true, true, true);
     }
-  else if (AOP_TYPE (IC_LEFT (ic)) == AOP_LIT)
+  else if (IC_LEFT (ic)->aop->type == AOP_LIT)
     {
-      unsigned long long lit = ullFromVal (AOP (IC_LEFT (ic))->aopu.aop_lit);
-      setupPairFromSP (PAIR_HL, _G.stack.offset + _G.stack.param_offset + _G.stack.pushed + (_G.omitFramePtr || IS_GB ? 0 : 2));
-      emit2 ("ld a, (hl)");
-      emit2 ("inc hl");
-      emit2 ("ld h, (hl)");
+      unsigned long long lit = ullFromVal (IC_LEFT (ic)->aop->aopu.aop_lit);
+      setupPairFromSP (PAIR_HL, _G.stack.offset + _G.stack.param_offset + _G.stack.pushed + (_G.omitFramePtr || IS_SM83 ? 0 : 2));
+      emit2 ("!ldahli");
+      emit2 ("ld h, !*hl");
       emit2 ("ld l, a");
       regalloc_dry_run_cost += 8;
       do
         {
-          emit2 ("ld (hl), !immedbyte", (unsigned long) (lit & 0xff));
+          emit2 ("ld !*hl, !immedbyte", (unsigned long) (lit & 0xff));
           regalloc_dry_run_cost += 2;
           lit >>= 8;
           if (size > 1)
@@ -5367,46 +6760,46 @@
         }
       while (--size);
     }
-  else if (!IS_GB && AOP_TYPE (IC_LEFT (ic)) == AOP_STK || AOP_TYPE (IC_LEFT (ic)) == AOP_EXSTK
-           || AOP_TYPE (IC_LEFT (ic)) == AOP_DIR || AOP_TYPE (IC_LEFT (ic)) == AOP_IY)
+  // gbz80 doesn't have have ldir. r2k and r2ka have an ldir wait state bug that affects copies between different types of memory.
+  else if (!IS_SM83 && IC_LEFT (ic)->aop->type == AOP_STK || IC_LEFT (ic)->aop->type == AOP_EXSTK
+           || (IC_LEFT (ic)->aop->type == AOP_DIR || IC_LEFT (ic)->aop->type == AOP_IY) && !(IS_R2K || IS_R2KA))
     {
-      setupPairFromSP (PAIR_HL, _G.stack.offset + _G.stack.param_offset + _G.stack.pushed + (_G.omitFramePtr || IS_GB ? 0 : 2));
-      emit2 ("ld e, (hl)");
+      setupPairFromSP (PAIR_HL, _G.stack.offset + _G.stack.param_offset + _G.stack.pushed + (_G.omitFramePtr || IS_SM83 ? 0 : 2));
+      emit2 ("ld e, !*hl");
       emit2 ("inc hl");
-      emit2 ("ld d, (hl)");
+      emit2 ("ld d, !*hl");
       regalloc_dry_run_cost += 7;
-      if (AOP_TYPE (IC_LEFT (ic)) == AOP_STK || AOP_TYPE (IC_LEFT (ic)) == AOP_EXSTK)
+      if (IC_LEFT (ic)->aop->type == AOP_STK || IC_LEFT (ic)->aop->type == AOP_EXSTK)
         {
           int sp_offset, fp_offset;
           fp_offset =
-            AOP (IC_LEFT (ic))->aopu.aop_stk + (AOP (IC_LEFT (ic))->aopu.aop_stk >
+            IC_LEFT (ic)->aop->aopu.aop_stk + (IC_LEFT (ic)->aop->aopu.aop_stk >
                 0 ? _G.stack.param_offset : 0);
           sp_offset = fp_offset + _G.stack.pushed + _G.stack.offset;
-          emit2 ("ld hl, #%d", sp_offset);
-          emit2 ("add hl, sp");
+          // TODO: find out if offset is okay
+          emit2 ("!ldahlsp", sp_offset);
+          spillPair (PAIR_HL);
           regalloc_dry_run_cost += 4;
         }
       else
-        {
-          emit2 ("ld hl, #%s", AOP (IC_LEFT (ic))->aopu.aop_dir);
-          regalloc_dry_run_cost += 3;
-        }
-      emit2 ("ld bc, #%d", size);
+        fetchLitPair (PAIR_HL, IC_LEFT (ic)->aop, 0, true);
+      emit2 ("ld bc, !immed%d", size);
       emit2 ("ldir");
+      updatePair (PAIR_HL, size);
       regalloc_dry_run_cost += 5;
     }
   else
     {
-      setupPairFromSP (PAIR_HL, _G.stack.offset + _G.stack.param_offset + _G.stack.pushed + (_G.omitFramePtr || IS_GB ? 0 : 2));
-      emit2 ("ld c, (hl)");
+      setupPairFromSP (PAIR_HL, _G.stack.offset + _G.stack.param_offset + _G.stack.pushed + (_G.omitFramePtr || IS_SM83 ? 0 : 2));
+      emit2 ("ld c, !*hl");
       emit2 ("inc hl");
-      emit2 ("ld b, (hl)");
+      emit2 ("ld b, !*hl");
       regalloc_dry_run_cost += 7;
-      spillPair (PAIR_HL);
+      updatePair (PAIR_HL, 1);
       do
         {
-          cheapMove (ASMOP_A, 0, AOP (IC_LEFT (ic)), offset++, true);
-          emit2 ("ld (bc), a");
+          cheapMove (ASMOP_A, 0, IC_LEFT (ic)->aop, offset++, true);
+          emit2 ("ld !mems, a", "bc");
           regalloc_dry_run_cost++;
           if (size > 1)
             {
@@ -5455,37 +6848,52 @@
 /* genPlusIncr :- does addition with increment if possible         */
 /*-----------------------------------------------------------------*/
 static bool
-genPlusIncr (const iCode * ic)
+genPlusIncr (const iCode *ic)
 {
   unsigned int icount;
   unsigned int size = getDataSize (IC_RESULT (ic));
-  PAIR_ID resultId = getPairId (AOP (IC_RESULT (ic)));
+  PAIR_ID resultId = getPairId (IC_RESULT (ic)->aop);
 
   /* will try to generate an increment */
   /* if the right side is not a literal
      we cannot */
-  if (AOP_TYPE (IC_RIGHT (ic)) != AOP_LIT)
+  if (IC_RIGHT (ic)->aop->type != AOP_LIT)
     return FALSE;
 
-  icount = (unsigned int) ulFromVal (AOP (IC_RIGHT (ic))->aopu.aop_lit);
+  icount = (unsigned int) ulFromVal (IC_RIGHT (ic)->aop->aopu.aop_lit);
 
   /* If result is a pair */
   if (resultId != PAIR_INVALID)
     {
       bool delayed_move;
-      if (isLitWord (AOP (IC_LEFT (ic))))
+      if (isLitWord (IC_LEFT (ic)->aop))
         {
-          fetchLitPair (getPairId (AOP (IC_RESULT (ic))), AOP (IC_LEFT (ic)), icount);
+          fetchLitPair (getPairId (IC_RESULT (ic)->aop), IC_LEFT (ic)->aop, icount, true);
           return TRUE;
         }
-      if (isPair (AOP (IC_LEFT (ic))) && resultId == PAIR_HL && icount > 3)
+
+      if (IS_Z80N && resultId == getPairId (IC_LEFT (ic)->aop) && resultId != PAIR_IY && icount > 3 && icount < 256 && isRegDead (A_IDX, ic)) // Saves once cycle vs. add dd, nn below.
+        {
+          cheapMove (ASMOP_A, 0, IC_RIGHT (ic)->aop, 0, true);
+          emit2 ("add %s, a", getPairName (IC_RESULT (ic)->aop));
+          regalloc_dry_run_cost += 2;
+          return true;
+        }
+      else if (IS_Z80N && resultId == getPairId (IC_LEFT (ic)->aop) && resultId != PAIR_IY && icount > 3)
         {
-          if (getPairId (AOP (IC_LEFT (ic))) == PAIR_HL)
+          emit2 ("add %s, !immed%s", getPairName (IC_RESULT (ic)->aop), aopGetLitWordLong (IC_RIGHT (ic)->aop, 0, false));
+          regalloc_dry_run_cost += 4;
+          return true;
+        }
+
+      if (isPair (IC_LEFT (ic)->aop) && getPairId (IC_LEFT (ic)->aop) != PAIR_IY && resultId == PAIR_HL && icount > 3)
+        {
+          if (getPairId (IC_LEFT (ic)->aop) == PAIR_HL)
             {
               PAIR_ID freep = getDeadPairId (ic);
               if (freep != PAIR_INVALID)
                 {
-                  fetchPair (freep, AOP (IC_RIGHT (ic)));
+                  fetchPair (freep, IC_RIGHT (ic)->aop);
                   emit2 ("add hl, %s", _pairs[freep].name);
                   regalloc_dry_run_cost += 1;
                   return TRUE;
@@ -5493,8 +6901,8 @@
             }
           else
             {
-              fetchPair (PAIR_HL, AOP (IC_RIGHT (ic)));
-              emit2 ("add hl, %s", getPairName (AOP (IC_LEFT (ic))));
+              fetchPair (PAIR_HL, IC_RIGHT (ic)->aop);
+              emit2 ("add hl, %s", getPairName (IC_LEFT (ic)->aop));
               regalloc_dry_run_cost += 1;
               return TRUE;
             }
@@ -5502,31 +6910,31 @@
       if (icount > 5)
         return FALSE;
       /* Inc a pair */
-      delayed_move = (getPairId (AOP (IC_RESULT (ic))) == PAIR_IY && getPairId (AOP (IC_LEFT (ic))) != PAIR_INVALID
-                      && isPairDead (getPairId (AOP (IC_LEFT (ic))), ic));
-      if (!sameRegs (AOP (IC_LEFT (ic)), AOP (IC_RESULT (ic))))
+      delayed_move = (getPairId (IC_RESULT (ic)->aop) == PAIR_IY && getPairId (IC_LEFT (ic)->aop) != PAIR_INVALID
+                      && isPairDead (getPairId (IC_LEFT (ic)->aop), ic));
+      if (!sameRegs (IC_LEFT (ic)->aop, IC_RESULT (ic)->aop))
         {
           if (icount > 3)
             return FALSE;
           if (!delayed_move)
-            fetchPair (getPairId (AOP (IC_RESULT (ic))), AOP (IC_LEFT (ic)));
+            genMove (IC_RESULT (ic)->aop, IC_LEFT (ic)->aop, isRegDead (A_IDX, ic), isPairDead (PAIR_HL, ic), isPairDead (PAIR_DE, ic), true);
         }
       while (icount--)
         {
-          PAIR_ID pair = delayed_move ? getPairId (AOP (IC_LEFT (ic))) : getPairId (AOP (IC_RESULT (ic)));
+          PAIR_ID pair = delayed_move ? getPairId (IC_LEFT (ic)->aop) : getPairId (IC_RESULT (ic)->aop);
           emit2 ("inc %s", _pairs[pair].name);
           regalloc_dry_run_cost += (pair == PAIR_IY ? 2 : 1);
         }
       if (delayed_move)
-        fetchPair (getPairId (AOP (IC_RESULT (ic))), AOP (IC_LEFT (ic)));
-      return TRUE;
+        fetchPair (getPairId (IC_RESULT (ic)->aop), IC_LEFT (ic)->aop);
+      return true;
     }
 
-  if (!IS_GB && isLitWord (AOP (IC_LEFT (ic))) && size == 2 && isPairDead (PAIR_HL, ic))
+  if (!IS_SM83 && isLitWord (IC_LEFT (ic)->aop) && size == 2 && isPairDead (PAIR_HL, ic))
     {
-      fetchLitPair (PAIR_HL, AOP (IC_LEFT (ic)), icount);
-      commitPair (AOP (IC_RESULT (ic)), PAIR_HL, ic, FALSE);
-      return TRUE;
+      fetchLitPair (PAIR_HL, IC_LEFT (ic)->aop, icount, true);
+      genMove (IC_RESULT (ic)->aop, ASMOP_HL, isRegDead (A_IDX, ic), true, isPairDead (PAIR_DE, ic), true);
+      return true;
     }
 
   if (icount > 4) // Not worth it if the sequence of inc gets too long.
@@ -5535,77 +6943,82 @@
   if (icount > 1 && size == 1 && aopInReg (IC_LEFT (ic)->aop, 0, A_IDX)) // add a, #n is cheaper than sequence of inc a.
     return false;
 
-  if (size == 2 && getPairId (AOP (IC_LEFT (ic))) != PAIR_INVALID && icount <= 3 && isPairDead (getPairId (AOP (IC_LEFT (ic))), ic))
+  if (size == 2 && getPairId (IC_LEFT (ic)->aop) != PAIR_INVALID && icount <= 3 && isPairDead (getPairId (IC_LEFT (ic)->aop), ic))
     {
-      PAIR_ID pair = getPairId (AOP (IC_LEFT (ic)));
+      PAIR_ID pair = getPairId (IC_LEFT (ic)->aop);
       while (icount--)
-        emit2 ("inc %s", _pairs[pair].name);
-      commitPair (AOP (IC_RESULT (ic)), pair, ic, FALSE);
+        {
+          emit2 ("inc %s", _pairs[pair].name);
+          regalloc_dry_run_cost += (pair == PAIR_IY ? 2 : 1);
+        }
+      genMove (IC_RESULT (ic)->aop, IC_LEFT (ic)->aop, isRegDead (A_IDX, ic), isPairDead(PAIR_HL, ic), isPairDead(PAIR_DE, ic), true);
       return true;
     }
 
-  if (size == 2 && icount <= 2 && isPairDead (PAIR_HL, ic) && !IS_GB &&
+  if (size == 2 && icount <= 2 && isPairDead (PAIR_HL, ic) && !IS_SM83 &&
     (IC_LEFT (ic)->aop->type == AOP_HL || IC_LEFT (ic)->aop->type == AOP_IY))
     {
-      fetchPair (PAIR_HL, AOP (IC_LEFT (ic)));
+      genMove (ASMOP_HL, IC_LEFT (ic)->aop, isRegDead (A_IDX, ic), true, isPairDead (PAIR_DE, ic), true);
       while (icount--)
         emit2 ("inc hl");
       regalloc_dry_run_cost++;
-      commitPair (AOP (IC_RESULT (ic)), PAIR_HL, ic, FALSE);
+      genMove (IC_RESULT (ic)->aop, ASMOP_HL, isRegDead (A_IDX, ic), true, isPairDead (PAIR_DE, ic), true);
       return true;
     }
 
   /* if increment 16 bits in register */
-  if (sameRegs (AOP (IC_LEFT (ic)), AOP (IC_RESULT (ic))) && size > 1 && icount == 1)
+  if (sameRegs (IC_LEFT (ic)->aop, IC_RESULT (ic)->aop) && size > 1 && icount == 1
+    && ((IS_EZ80_Z80 || IS_Z80N) || size == 2 && getPairId (IC_RESULT (ic)->aop) != PAIR_INVALID || size >= 2 && !aopInReg (IC_RESULT (ic)->aop, 0, IYL_IDX) && !aopInReg (IC_RESULT (ic)->aop, 0, IYH_IDX) && !aopInReg (IC_RESULT (ic)->aop, 1, IYL_IDX) && !aopInReg (IC_RESULT (ic)->aop, 1, IYH_IDX)))
     {
       int offset = 0;
       symbol *tlbl = regalloc_dry_run ? 0 : newiTempLabel (0);
       while (size--)
         {
-          if (size == 1 && getPairId_o (AOP (IC_RESULT (ic)), offset) != PAIR_INVALID)
+          if (size == 1 && getPairId_o (IC_RESULT (ic)->aop, offset) != PAIR_INVALID)
             {
-              emit2 ("inc %s", _pairs[getPairId_o (AOP (IC_RESULT (ic)), offset)].name);
+              emit2 ("inc %s", _pairs[getPairId_o (IC_RESULT (ic)->aop, offset)].name);
+              regalloc_dry_run_cost += (getPairId_o (IC_RESULT (ic)->aop, offset) == PAIR_IY ? 2 : 1);
               size--;
               offset += 2;
               break;
             }
-          emit3_o (A_INC, AOP (IC_RESULT (ic)), offset++, 0, 0);
+          emit3_o (A_INC, IC_RESULT (ic)->aop, offset++, 0, 0);
           if (size)
             {
               if (!regalloc_dry_run)
                 emit2 ("jp NZ, !tlabel", labelKey2num (tlbl->key));
-              regalloc_dry_run_cost += 3;
+              regalloc_dry_run_cost += 2;
             }
         }
       if (!regalloc_dry_run)
-        (AOP_TYPE (IC_LEFT (ic)) == AOP_HL || IS_GB
-         && AOP_TYPE (IC_LEFT (ic)) == AOP_STK) ? emitLabelSpill (tlbl) : emitLabel (tlbl);
-      else if (AOP_TYPE (IC_LEFT (ic)) == AOP_HL)
+        (IC_LEFT (ic)->aop->type == AOP_HL || IS_SM83
+         && IC_LEFT (ic)->aop->type == AOP_STK) ? emitLabelSpill (tlbl) : emitLabel (tlbl);
+      else if (IC_LEFT (ic)->aop->type == AOP_HL)
         spillCached ();
       return TRUE;
     }
 
   /* if the sizes are greater than 1 then we cannot */
-  if (AOP_SIZE (IC_RESULT (ic)) > 1 || AOP_SIZE (IC_LEFT (ic)) > 1)
+  if (IC_RESULT (ic)->aop->size > 1 || IC_LEFT (ic)->aop->size > 1)
     return FALSE;
 
   /* If the result is in a register then we can load then increment.
    */
-  if (AOP_TYPE (IC_RESULT (ic)) == AOP_REG)
+  if (IC_RESULT (ic)->aop->type == AOP_REG)
     {
-      cheapMove (AOP (IC_RESULT (ic)), LSB, AOP (IC_LEFT (ic)), LSB, true);
+      cheapMove (IC_RESULT (ic)->aop, LSB, IC_LEFT (ic)->aop, LSB, true);
       while (icount--)
-        emit3_o (A_INC, AOP (IC_RESULT (ic)), LSB, 0, 0);
+        emit3_o (A_INC, IC_RESULT (ic)->aop, LSB, 0, 0);
       return TRUE;
     }
 
   /* we can if the aops of the left & result match or
      if they are in registers and the registers are the
      same */
-  if (sameRegs (AOP (IC_LEFT (ic)), AOP (IC_RESULT (ic))))
+  if (sameRegs (IC_LEFT (ic)->aop, IC_RESULT (ic)->aop))
     {
       while (icount--)
-        emit3 (A_INC, AOP (IC_LEFT (ic)), 0);
+        emit3 (A_INC, IC_LEFT (ic)->aop, 0);
       return TRUE;
     }
 
@@ -5620,7 +7033,7 @@
 {
   symbol *tlbl = regalloc_dry_run ? 0 : newiTempLabel (0);
   /* if the result is a bit */
-  if (AOP_TYPE (result) == AOP_CRY)
+  if (result->aop->type == AOP_CRY)
     {
       wassertl (0, "Tried to write A into a bit");
     }
@@ -5653,7 +7066,7 @@
 static void
 shiftIntoPair (PAIR_ID id, asmop *aop)
 {
-  wassertl (!IS_GB, "Not implemented for the GBZ80");
+  wassertl (!IS_SM83, "Not implemented for the SM83");
 
   emitDebug ("; Shift into pair");
 
@@ -5686,7 +7099,7 @@
 {
   wassert (left && right);
 
-  if (!IS_GB)
+  if (!IS_SM83)
     {
       if (couldDestroyCarry (right) && couldDestroyCarry (result))
         {
@@ -5738,7 +7151,8 @@
      if literal, literal on the right or
      if left requires ACC or right is already
      in ACC */
-  if ((AOP_TYPE (IC_LEFT (ic)) == AOP_LIT) || (AOP_NEEDSACC (IC_RIGHT (ic))) || aopInReg (IC_RIGHT (ic)->aop, 0, A_IDX))
+  if ((IC_LEFT (ic)->aop->type == AOP_LIT) || (AOP_NEEDSACC (IC_RIGHT (ic))) || aopInReg (IC_RIGHT (ic)->aop, 0, A_IDX) ||
+    IC_LEFT (ic)->aop->regs[A_IDX] < 0 && IC_RIGHT (ic)->aop->type == AOP_STL)
     {
       operand *t = IC_RIGHT (ic);
       IC_RIGHT (ic) = IC_LEFT (ic);
@@ -5750,14 +7164,14 @@
 
   /* if both left & right are in bit
      space */
-  if (AOP_TYPE (IC_LEFT (ic)) == AOP_CRY && AOP_TYPE (IC_RIGHT (ic)) == AOP_CRY)
+  if (IC_LEFT (ic)->aop->type == AOP_CRY && IC_RIGHT (ic)->aop->type == AOP_CRY)
     {
       /* Cant happen */
       wassertl (0, "Tried to add two bits");
     }
 
   /* if left in bit space & right literal */
-  if (AOP_TYPE (IC_LEFT (ic)) == AOP_CRY && AOP_TYPE (IC_RIGHT (ic)) == AOP_LIT)
+  if (IC_LEFT (ic)->aop->type == AOP_CRY && IC_RIGHT (ic)->aop->type == AOP_LIT)
     {
       /* Can happen I guess */
       wassertl (0, "Tried to add a bit to a literal");
@@ -5771,23 +7185,23 @@
   size = getDataSize (IC_RESULT (ic));
 
   /* Special case when left and right are constant */
-  if (isPair (AOP (IC_RESULT (ic))))
+  if (isPair (IC_RESULT (ic)->aop))
     {
-      char *left = Safe_strdup (aopGetLitWordLong (AOP (IC_LEFT (ic)), 0, FALSE));
-      const char *right = aopGetLitWordLong (AOP (IC_RIGHT (ic)), 0, FALSE);
+      char *left = Safe_strdup (aopGetLitWordLong (IC_LEFT (ic)->aop, 0, FALSE));
+      const char *right = aopGetLitWordLong (IC_RIGHT (ic)->aop, 0, FALSE);
 
-      if (AOP_TYPE (IC_LEFT (ic)) == AOP_LIT && AOP_TYPE (IC_RIGHT (ic)) == AOP_LIT && left && right)
+      if (IC_LEFT (ic)->aop->type == AOP_LIT && IC_RIGHT (ic)->aop->type == AOP_LIT && left && right)
         {
           struct dbuf_s dbuf;
 
           /* It's a pair */
           /* PENDING: fix */
           dbuf_init (&dbuf, 128);
-          dbuf_printf (&dbuf, "#(%s + %s)", left, right);
+          dbuf_printf (&dbuf, "!immed(%s + %s)", left, right);
           Safe_free (left);
-          emit2 ("ld %s, %s", getPairName (AOP (IC_RESULT (ic))), dbuf_c_str (&dbuf));
+          emit2 ("ld %s, %s", getPairName (IC_RESULT (ic)->aop), dbuf_c_str (&dbuf));
           dbuf_destroy (&dbuf);
-          regalloc_dry_run_cost += (getPairId (AOP (IC_RESULT (ic))) == PAIR_IY ? 4 : 3);
+          regalloc_dry_run_cost += (getPairId (IC_RESULT (ic)->aop) == PAIR_IY ? 4 : 3);
           goto release;
         }
       Safe_free (left);
@@ -5796,54 +7210,54 @@
   // eZ80 has lea.
   if (IS_EZ80_Z80 && isPair (IC_RESULT (ic)->aop) && getPairId (IC_LEFT (ic)->aop) == PAIR_IY && IC_RIGHT (ic)->aop->type == AOP_LIT)
     {
-       int lit = (int) ulFromVal (AOP (IC_RIGHT (ic))->aopu.aop_lit);
+       int lit = (int) ulFromVal (IC_RIGHT (ic)->aop->aopu.aop_lit);
        if (lit >= -128 && lit < 128)
          {
-           emit2 ("lea %s, iy, #%d", _pairs[getPairId (IC_RESULT (ic)->aop)].name, lit);
+           emit2 ("lea %s, iy, !immed%d", _pairs[getPairId (IC_RESULT (ic)->aop)].name, lit);
            regalloc_dry_run_cost += 3;
            spillPair (getPairId (IC_RESULT (ic)->aop));
            goto release;
          }
     }
 
-  if ((isPair (AOP (IC_RIGHT (ic))) || isPair (AOP (IC_LEFT (ic)))) && getPairId (AOP (IC_RESULT (ic))) == PAIR_HL)
+  if ((isPair (IC_RIGHT (ic)->aop) || isPair (IC_LEFT (ic)->aop)) && getPairId (IC_RESULT (ic)->aop) == PAIR_HL)
     {
       /* Fetch into HL then do the add */
-      PAIR_ID left = getPairId (AOP (IC_LEFT (ic)));
-      PAIR_ID right = getPairId (AOP (IC_RIGHT (ic)));
+      PAIR_ID left = getPairId (IC_LEFT (ic)->aop);
+      PAIR_ID right = getPairId (IC_RIGHT (ic)->aop);
 
       spillPair (PAIR_HL);
 
-      if (left == PAIR_HL && right != PAIR_INVALID)
+      if (left == PAIR_HL && right != PAIR_INVALID && (IS_TLCS90 || right != PAIR_IY))
         {
           emit2 ("add hl, %s", _pairs[right].name);
           regalloc_dry_run_cost += 1;
           goto release;
         }
-      else if (right == PAIR_HL && left != PAIR_INVALID)
+      else if (right == PAIR_HL && left != PAIR_INVALID && (IS_TLCS90 || left != PAIR_IY))
         {
           emit2 ("add hl, %s", _pairs[left].name);
           regalloc_dry_run_cost += 1;
           goto release;
         }
-      else if (right != PAIR_INVALID && right != PAIR_HL)
+      else if (right != PAIR_INVALID && right != PAIR_HL && (IS_TLCS90 || right != PAIR_IY))
         {
-          fetchPair (PAIR_HL, AOP (IC_LEFT (ic)));
-          emit2 ("add hl, %s", getPairName (AOP (IC_RIGHT (ic))));
+          fetchPair (PAIR_HL, leftop);
+          emit2 ("add hl, %s", getPairName (IC_RIGHT (ic)->aop));
           regalloc_dry_run_cost += 1;
           goto release;
         }
-      else if (left != PAIR_INVALID && left != PAIR_HL)
+      else if (left != PAIR_INVALID && left != PAIR_HL && (IS_TLCS90 || left != PAIR_IY))
         {
-          fetchPair (PAIR_HL, AOP (IC_RIGHT (ic)));
-          emit2 ("add hl, %s", getPairName (AOP (IC_LEFT (ic))));
+          fetchPair (PAIR_HL, rightop);
+          emit2 ("add hl, %s", getPairName (IC_LEFT (ic)->aop));
           regalloc_dry_run_cost += 1;
           goto release;
         }
       else if (left == PAIR_HL && (isPairDead (PAIR_DE, ic) || isPairDead (PAIR_BC, ic)))
         {
           PAIR_ID pair = (isPairDead (PAIR_DE, ic) ? PAIR_DE : PAIR_BC);
-          fetchPair (pair, AOP (IC_RIGHT (ic)));
+          fetchPair (pair, IC_RIGHT (ic)->aop);
           emit2 ("add hl, %s", _pairs[pair].name);
           regalloc_dry_run_cost += 1;
           goto release;
@@ -5851,7 +7265,7 @@
       else if (right == PAIR_HL && (isPairDead (PAIR_DE, ic) || isPairDead (PAIR_BC, ic)))
         {
           PAIR_ID pair = (isPairDead (PAIR_DE, ic) ? PAIR_DE : PAIR_BC);
-          fetchPair (pair, AOP (IC_LEFT (ic)));
+          fetchPair (pair, leftop);
           emit2 ("add hl, %s", _pairs[pair].name);
           regalloc_dry_run_cost += 1;
           goto release;
@@ -5861,9 +7275,18 @@
           /* Can't do it */
         }
     }
+  else if (getPairId (IC_RESULT (ic)->aop) == PAIR_HL && (isPairDead (PAIR_DE, ic) || isPairDead (PAIR_BC, ic)) && IC_RIGHT (ic)->aop->type == AOP_LIT)
+    {
+      PAIR_ID extrapair = isPairDead (PAIR_DE, ic) ? PAIR_DE : PAIR_BC;
+      fetchPair (PAIR_HL, IC_LEFT (ic)->aop);
+      fetchPair (extrapair, IC_RIGHT (ic)->aop);
+      emit2 ("add hl, %s", _pairs[extrapair].name);
+      regalloc_dry_run_cost += 1;
+      goto release;
+    }
 
   // Handle AOP_EXSTK conflict with hl here, since setupToPreserveCarry() would cause problems otherwise.
-  if (IC_RESULT (ic)->aop->type == AOP_EXSTK && (getPairId (IC_LEFT (ic)->aop) == PAIR_HL || getPairId (IC_RIGHT (ic)->aop) == PAIR_HL) &&
+  if (IC_RESULT (ic)->aop->type == AOP_EXSTK && size <= 2 && (getPairId (IC_LEFT (ic)->aop) == PAIR_HL || getPairId (IC_RIGHT (ic)->aop) == PAIR_HL) &&
     (isPairDead (PAIR_DE, ic) || isPairDead (PAIR_BC, ic)) && isPairDead (PAIR_HL, ic))
     {
       PAIR_ID extrapair = isPairDead (PAIR_DE, ic) ? PAIR_DE : PAIR_BC;
@@ -5871,50 +7294,53 @@
       emit2 ("add hl, %s", _pairs[extrapair].name);
       regalloc_dry_run_cost += 1;
       spillPair (PAIR_HL);
-      commitPair (IC_RESULT (ic)->aop, PAIR_HL, ic, FALSE);
+      genMove (IC_RESULT (ic)->aop, ASMOP_HL, isRegDead (A_IDX, ic), true, isPairDead (PAIR_DE, ic), true);
       goto release;
     }
-  else if (getPairId (AOP (IC_RESULT (ic))) == PAIR_IY &&
-    (getPairId (AOP (IC_LEFT (ic))) == PAIR_HL && isPair (AOP (IC_RIGHT (ic))) && getPairId (AOP (IC_RIGHT (ic))) != PAIR_IY || getPairId (AOP (IC_RIGHT (ic))) == PAIR_HL && isPair (AOP (IC_LEFT (ic))) && getPairId (AOP (IC_LEFT (ic))) != PAIR_IY) &&
+  else if (getPairId (IC_RESULT (ic)->aop) == PAIR_IY &&
+    (getPairId (IC_LEFT (ic)->aop) == PAIR_HL && isPair (IC_RIGHT (ic)->aop) && getPairId (IC_RIGHT (ic)->aop) != PAIR_IY || getPairId (IC_RIGHT (ic)->aop) == PAIR_HL && isPair (IC_LEFT (ic)->aop) && getPairId (IC_LEFT (ic)->aop) != PAIR_IY) &&
     isPairDead (PAIR_HL, ic))
     {
-      PAIR_ID pair = (getPairId (AOP (IC_LEFT (ic))) == PAIR_HL ? getPairId (AOP (IC_RIGHT (ic))) : getPairId (AOP (IC_LEFT (ic))));
+      PAIR_ID pair = (getPairId (IC_LEFT (ic)->aop) == PAIR_HL ? getPairId (IC_RIGHT (ic)->aop) : getPairId (IC_LEFT (ic)->aop));
       emit2 ("add hl, %s", _pairs[pair].name);
+      regalloc_dry_run_cost++;
       _push (PAIR_HL);
       _pop (PAIR_IY);
       goto release;
     }
-  else if (getPairId (AOP (IC_RESULT (ic))) == PAIR_IY)
+  else if (getPairId (IC_RESULT (ic)->aop) == PAIR_IY)
     {
       bool save_pair = FALSE;
       PAIR_ID pair;
 
-      if (getPairId (AOP (IC_RIGHT (ic))) == PAIR_IY || getPairId (AOP (IC_LEFT (ic))) == PAIR_BC
-          || getPairId (AOP (IC_LEFT (ic))) == PAIR_DE || getPairId (AOP (IC_LEFT (ic))) != PAIR_IY
-          && (AOP_TYPE (IC_RIGHT (ic)) == AOP_IMMD || AOP_TYPE (IC_RIGHT (ic)) == AOP_LIT))
+      if (getPairId (IC_RIGHT (ic)->aop) == PAIR_IY || getPairId (IC_LEFT (ic)->aop) == PAIR_BC
+          || getPairId (IC_LEFT (ic)->aop) == PAIR_DE || getPairId (IC_LEFT (ic)->aop) != PAIR_IY
+          && (IC_RIGHT (ic)->aop->type == AOP_IMMD || IC_RIGHT (ic)->aop->type == AOP_LIT))
         {
           operand *t = IC_RIGHT (ic);
           IC_RIGHT (ic) = IC_LEFT (ic);
           IC_LEFT (ic) = t;
+          leftop = IC_LEFT (ic)->aop;
+          rightop = IC_RIGHT (ic)->aop;
         }
-      pair = getPairId (AOP (IC_RIGHT (ic)));
+      pair = getPairId (IC_RIGHT (ic)->aop);
       if (pair != PAIR_BC && pair != PAIR_DE)
         {
-          if (AOP_TYPE (IC_RIGHT (ic)) == AOP_REG && AOP (IC_RIGHT (ic))->aopu.aop_reg[0]->rIdx == C_IDX
-              && (!bitVectBitValue (ic->rSurv, B_IDX) || !isPairDead (PAIR_DE, ic)))
+          if (IC_RIGHT (ic)->aop->type == AOP_REG && IC_RIGHT (ic)->aop->aopu.aop_reg[0]->rIdx == C_IDX
+              && (isRegDead (B_IDX, ic) || !isPairDead (PAIR_DE, ic)))
             pair = PAIR_BC;
-          else if (AOP_TYPE (IC_RIGHT (ic)) == AOP_REG && AOP (IC_RIGHT (ic))->aopu.aop_reg[0]->rIdx == E_IDX
-                   && (!bitVectBitValue (ic->rSurv, D_IDX) || !isPairDead (PAIR_BC, ic)))
+          else if (IC_RIGHT (ic)->aop->type == AOP_REG && IC_RIGHT (ic)->aop->aopu.aop_reg[0]->rIdx == E_IDX
+                   && (isRegDead (D_IDX, ic) || !isPairDead (PAIR_BC, ic)))
             pair = PAIR_DE;
           else
             pair = isPairDead (PAIR_DE, ic) ? PAIR_DE : PAIR_BC;
           if (!isPairDead (pair, ic))
             save_pair = TRUE;
         }
-      fetchPair (PAIR_IY, AOP (IC_LEFT (ic)));
+      genMove (ASMOP_IY, IC_LEFT (ic)->aop, isRegDead (A_IDX, ic), isPairDead (PAIR_HL, ic), isPairDead (PAIR_DE, ic), true);
       if (save_pair)
         _push (pair);
-      fetchPair (pair, AOP (IC_RIGHT (ic)));
+      fetchPair (pair, IC_RIGHT (ic)->aop);
       emit2 ("add iy, %s", _pairs[pair].name);
       spillPair (PAIR_IY);
       regalloc_dry_run_cost += 2;
@@ -5923,7 +7349,7 @@
       goto release;
     }
 
-  /* gbz80 special case:
+  /* sm83 special case:
      ld hl,sp+n trashes C so we can't afford to do it during an
      add with stack based variables.  Worst case is:
      ld  hl,sp+left
@@ -5951,68 +7377,76 @@
      * If left or right are in bc then the loss is small - trap later
      * If the result is in bc then the loss is also small
    */
-  if (IS_GB)
+  if (IS_SM83)
     {
-      if (AOP_TYPE (IC_LEFT (ic)) == AOP_STK || AOP_TYPE (IC_RIGHT (ic)) == AOP_STK || AOP_TYPE (IC_RESULT (ic)) == AOP_STK)
+      if (IC_LEFT (ic)->aop->type == AOP_STK || IC_RIGHT (ic)->aop->type == AOP_STK || IC_RESULT (ic)->aop->type == AOP_STK)
         {
-          if ((AOP_SIZE (IC_LEFT (ic)) == 2 ||
-               AOP_SIZE (IC_RIGHT (ic)) == 2) && (AOP_SIZE (IC_LEFT (ic)) <= 2 && AOP_SIZE (IC_RIGHT (ic)) <= 2 || size == 2))
+          if ((IC_LEFT (ic)->aop->size == 2 ||
+               IC_RIGHT (ic)->aop->size == 2) && (IC_LEFT (ic)->aop->size <= 2 && IC_RIGHT (ic)->aop->size <= 2 || size == 2))
             {
-              if (getPairId (AOP (IC_RIGHT (ic))) == PAIR_BC || getPairId (AOP (IC_RIGHT (ic))) == PAIR_DE)
+              if (getPairId (IC_RIGHT (ic)->aop) == PAIR_BC || getPairId (IC_RIGHT (ic)->aop) == PAIR_DE && getPairId (IC_LEFT (ic)->aop) != PAIR_BC)
                 {
                   /* Swap left and right */
                   operand *t = IC_RIGHT (ic);
                   IC_RIGHT (ic) = IC_LEFT (ic);
                   IC_LEFT (ic) = t;
+                  leftop = IC_LEFT (ic)->aop;
+                  rightop = IC_RIGHT (ic)->aop;
                 }
-              if (getPairId (AOP (IC_LEFT (ic))) == PAIR_BC)
+              if (getPairId (IC_LEFT (ic)->aop) == PAIR_BC)
                 {
-                  fetchPair (PAIR_HL, AOP (IC_RIGHT (ic)));
+                  fetchPair (PAIR_HL, IC_RIGHT (ic)->aop);
                   emit2 ("add hl, bc");
                   regalloc_dry_run_cost += 1;
                 }
               else
                 {
-                  if (AOP_TYPE (IC_RIGHT (ic)) == AOP_REG && AOP_SIZE (IC_RIGHT (ic)) == 2 && AOP_TYPE (IC_LEFT (ic)) == AOP_REG && AOP_SIZE (IC_LEFT (ic)) == 2)
+                  if (!isPairDead (PAIR_DE, ic))
+                    _push (PAIR_DE);
+
+                  if (IC_RIGHT (ic)->aop->type == AOP_REG && IC_RIGHT (ic)->aop->size == 2 && IC_LEFT (ic)->aop->type == AOP_REG && IC_LEFT (ic)->aop->size == 2)
                     {
                       const short dst[4] = { E_IDX, L_IDX, D_IDX, H_IDX };
                       short src[4];
-                      if (AOP (IC_RIGHT (ic))->aopu.aop_reg[0]->rIdx == E_IDX
-                          || AOP (IC_LEFT (ic))->aopu.aop_reg[0]->rIdx == L_IDX)
+                      if (IC_RIGHT (ic)->aop->aopu.aop_reg[0]->rIdx == E_IDX
+                          || IC_LEFT (ic)->aop->aopu.aop_reg[0]->rIdx == L_IDX)
                         {
-                          src[0] = AOP (IC_RIGHT (ic))->aopu.aop_reg[0]->rIdx;
-                          src[1] = AOP (IC_LEFT (ic))->aopu.aop_reg[0]->rIdx;
-                          src[2] = AOP (IC_RIGHT (ic))->aopu.aop_reg[1]->rIdx;
-                          src[3] = AOP (IC_LEFT (ic))->aopu.aop_reg[1]->rIdx;
+                          src[0] = IC_RIGHT (ic)->aop->aopu.aop_reg[0]->rIdx;
+                          src[1] = IC_LEFT (ic)->aop->aopu.aop_reg[0]->rIdx;
+                          src[2] = IC_RIGHT (ic)->aop->aopu.aop_reg[1]->rIdx;
+                          src[3] = IC_LEFT (ic)->aop->aopu.aop_reg[1]->rIdx;
                         }
                       else
                         {
-                          src[1] = AOP (IC_RIGHT (ic))->aopu.aop_reg[0]->rIdx;
-                          src[0] = AOP (IC_LEFT (ic))->aopu.aop_reg[0]->rIdx;
-                          src[3] = AOP (IC_RIGHT (ic))->aopu.aop_reg[1]->rIdx;
-                          src[2] = AOP (IC_LEFT (ic))->aopu.aop_reg[1]->rIdx;
+                          src[1] = IC_RIGHT (ic)->aop->aopu.aop_reg[0]->rIdx;
+                          src[0] = IC_LEFT (ic)->aop->aopu.aop_reg[0]->rIdx;
+                          src[3] = IC_RIGHT (ic)->aop->aopu.aop_reg[1]->rIdx;
+                          src[2] = IC_LEFT (ic)->aop->aopu.aop_reg[1]->rIdx;
                         }
-                      regMove (dst, src, size, FALSE);
+                      regMove (dst, src, 4, FALSE);
                     }
-                  else if (AOP_TYPE (IC_RIGHT (ic)) == AOP_REG &&
-                           (AOP (IC_RIGHT (ic))->aopu.aop_reg[0]->rIdx == E_IDX
-                            || AOP (IC_RIGHT (ic))->aopu.aop_reg[0]->rIdx == D_IDX || AOP_SIZE (IC_RIGHT (ic)) == 2
-                            && (AOP (IC_RIGHT (ic))->aopu.aop_reg[1]->rIdx == E_IDX
-                                || AOP (IC_RIGHT (ic))->aopu.aop_reg[1]->rIdx == D_IDX)))
+                  else if (IC_RIGHT (ic)->aop->type == AOP_REG &&
+                           (IC_RIGHT (ic)->aop->aopu.aop_reg[0]->rIdx == E_IDX
+                            || IC_RIGHT (ic)->aop->aopu.aop_reg[0]->rIdx == D_IDX || IC_RIGHT (ic)->aop->size == 2
+                            && (IC_RIGHT (ic)->aop->aopu.aop_reg[1]->rIdx == E_IDX
+                                || IC_RIGHT (ic)->aop->aopu.aop_reg[1]->rIdx == D_IDX)))
                     {
-                      fetchPair (PAIR_DE, AOP (IC_RIGHT (ic)));
-                      fetchPair (PAIR_HL, AOP (IC_LEFT (ic)));
+                      fetchPair (PAIR_DE, IC_RIGHT (ic)->aop);
+                      fetchPair (PAIR_HL, IC_LEFT (ic)->aop);
                     }
                   else
                     {
-                      fetchPair (PAIR_DE, AOP (IC_LEFT (ic)));
-                      fetchPair (PAIR_HL, AOP (IC_RIGHT (ic)));
+                      fetchPair (PAIR_DE, IC_LEFT (ic)->aop);
+                      fetchPair (PAIR_HL, IC_RIGHT (ic)->aop);
                     }
                   emit2 ("add hl, de");
                   regalloc_dry_run_cost += 1;
+
+                  if (!isPairDead (PAIR_DE, ic))
+                    _pop (PAIR_DE);
                 }
               spillPair (PAIR_HL);
-              commitPair (AOP (IC_RESULT (ic)), PAIR_HL, ic, FALSE);
+              genMove (IC_RESULT (ic)->aop, ASMOP_HL, isRegDead (A_IDX, ic), true, isPairDead (PAIR_DE, ic), true);
               goto release;
             }
         }
@@ -6028,22 +7462,26 @@
 
   // Avoid overwriting operand in h or l when setupToPreserveCarry () loads hl - only necessary if carry is actually used during addition.
   premoved = FALSE;
-  if (size > 1 && !(size == 2 && (isPair (leftop) && rightop->type == AOP_LIT)))
+  if (size > 1 &&
+    !(size == 2 && isPair (leftop) && (rightop->type == AOP_LIT || rightop->type == AOP_IY)) && !(size == 2 && leftop->type == AOP_STL && isPairDead (PAIR_HL, ic))) // No need to setup if a single 16 bit addition is sufficient below.
     {
-      if (!couldDestroyCarry (leftop) && (couldDestroyCarry (rightop) || couldDestroyCarry (AOP (IC_RESULT (ic)))))
+      if (!couldDestroyCarry (leftop) && (couldDestroyCarry (rightop) || couldDestroyCarry (IC_RESULT (ic)->aop)))
         {
           cheapMove (ASMOP_A, 0, leftop, offset, true);
           premoved = TRUE;
         }
 
-      setupToPreserveCarry (AOP (IC_RESULT (ic)), leftop, rightop);
+      if ((requiresHL (IC_RESULT (ic)->aop) && IC_RESULT (ic)->aop->type != AOP_REG || requiresHL (leftop) && leftop->type != AOP_REG || requiresHL (rightop) && rightop->type != AOP_REG) &&
+        (leftop->regs[L_IDX] > 0 || leftop->regs[H_IDX] > 0 || rightop->regs[L_IDX] > 0 || rightop->regs[H_IDX] > 0))
+        UNIMPLEMENTED;
+      setupToPreserveCarry (IC_RESULT (ic)->aop, leftop, rightop);
     }
   // But if we don't actually want to use hl for the addition, it can make sense to setup an op to use cheaper hl instead of iy.
-  if (size == 1 && !aopInReg(leftop, 0, H_IDX) && !aopInReg(leftop, 0, L_IDX) && isPairDead (PAIR_HL, ic))
+  if (size == 1 && !aopInReg(leftop, 0, H_IDX) && !aopInReg(leftop, 0, L_IDX) && !aopInReg(rightop, 0, H_IDX) && !aopInReg(rightop, 0, L_IDX) && isPairDead (PAIR_HL, ic))
     {
-      if (couldDestroyCarry (AOP (IC_RESULT (ic))) &&
-        (AOP (IC_RESULT (ic)) == leftop || AOP (IC_RESULT (ic)) == rightop))
-        shiftIntoPair (PAIR_HL, AOP (IC_RESULT (ic)));
+      if (couldDestroyCarry (IC_RESULT (ic)->aop) &&
+        (IC_RESULT (ic)->aop == leftop || IC_RESULT (ic)->aop == rightop))
+        shiftIntoPair (PAIR_HL, IC_RESULT (ic)->aop);
       else if (couldDestroyCarry (rightop))
         shiftIntoPair (PAIR_HL, rightop);
     }
@@ -6051,21 +7489,63 @@
   cached[0] = -1;
   cached[1] = -1;
 
-  for (i = 0, started = FALSE; i < size;)
+  for (i = 0, started = false; i < size;)
     {
+      const bool de_dead = isPairDead (PAIR_DE, ic) &&
+        leftop->regs[E_IDX] <= i && leftop->regs[D_IDX] <= i &&
+        rightop->regs[E_IDX] <= i && rightop->regs[D_IDX] <= i &&
+        (IC_RESULT (ic)->aop->regs[E_IDX] < 0 || IC_RESULT (ic)->aop->regs[E_IDX] >= i) && (IC_RESULT (ic)->aop->regs[D_IDX] < 0 || IC_RESULT (ic)->aop->regs[D_IDX] >= i);
+      const bool hl_dead = isPairDead (PAIR_HL, ic) &&
+        leftop->regs[L_IDX] <= i && leftop->regs[H_IDX] <= i &&
+        rightop->regs[L_IDX] <= i && rightop->regs[H_IDX] <= i &&
+        (IC_RESULT (ic)->aop->regs[L_IDX] < 0 || IC_RESULT (ic)->aop->regs[L_IDX] >= i) && (IC_RESULT (ic)->aop->regs[H_IDX] < 0 || IC_RESULT (ic)->aop->regs[H_IDX] >= i);
+
+      // Rematerialization of addresses on the stack.
+      if (leftop->type == AOP_STL && !i && i + 1 < size && rightop->type == AOP_LIT && hl_dead)
+        {
+          emit2 ("ld hl, !immed%d", spOffset (leftop->aopu.aop_stk) + (ulFromVal (rightop->aopu.aop_lit) & 0xffff));
+          emit2 ("add hl, sp");
+          spillPair (PAIR_HL);
+          regalloc_dry_run_cost += 4;
+          started = true;
+          genMove_o (IC_RESULT (ic)->aop, 0, ASMOP_HL, 0, 2, true, true, de_dead, false, i + 2 == size);
+          i += 2;
+          continue;
+        }
+      else if (leftop->type == AOP_STL && !i && i + 1 < size && hl_dead && (size <= 2 || leftop->type != AOP_EXSTK /* (hl) would be pointed to result, overwritten by addition here */))
+        {
+          PAIR_ID pair = getPairId (rightop);
+          if (pair != PAIR_BC)
+            pair = PAIR_DE;
+          if (pair == PAIR_DE && !de_dead)
+            _push (PAIR_DE);
+          genMove (pair == PAIR_BC ? ASMOP_BC : ASMOP_DE, rightop, true, true, de_dead, false);
+          genMove (ASMOP_HL, leftop, true, true, de_dead && pair != PAIR_DE, false);
+          emit2 ("add hl, %s", _pairs[pair].name);
+          spillPair (pair);
+          regalloc_dry_run_cost++;
+          started = true;
+          if (pair == PAIR_DE && !de_dead)
+            _pop (PAIR_DE);
+          genMove_o (IC_RESULT (ic)->aop, 0, ASMOP_HL, 0, 2, true, true, de_dead, false, i + 2 == size);
+          i += 2;
+          continue;
+        }
       // Addition of interleaved pairs.
-      if ((!premoved || i) && aopInReg (AOP (IC_RESULT (ic)), i, HL_IDX) && leftop->size - i >= 2 && rightop->size - i >= 2)
+      else if ((!premoved || i) && leftop->size - i >= 2 && rightop->size - i >= 2 &&
+        (aopInReg (IC_RESULT (ic)->aop, i, HL_IDX) || aopInReg (IC_RESULT (ic)->aop, i, IY_IDX) && !started))
         {
+          const bool iy = aopInReg (IC_RESULT (ic)->aop, i, IY_IDX);
           PAIR_ID pair = PAIR_INVALID;
 
-          if (aopInReg (leftop, i, L_IDX) && aopInReg (rightop, i + 1, H_IDX))
+          if (aopInReg (leftop, i, iy ? IYL_IDX : L_IDX) && aopInReg (rightop, i + 1, iy ? IYH_IDX : H_IDX))
             {
               if (aopInReg (leftop, i + 1, D_IDX) && aopInReg (rightop, i, E_IDX))
                 pair = PAIR_DE;
               else if (aopInReg (leftop, i + 1, B_IDX) && aopInReg (rightop, i, C_IDX))
                 pair = PAIR_BC;
             }
-          else if (aopInReg (leftop, i + 1, H_IDX) && aopInReg (rightop, i, L_IDX))
+          else if (aopInReg (leftop, i + 1, iy ? IYH_IDX : H_IDX) && aopInReg (rightop, i, iy ? IYL_IDX : L_IDX))
             {
               if (aopInReg (leftop, i, E_IDX) && aopInReg (rightop, i + 1, D_IDX))
                 pair = PAIR_DE;
@@ -6077,124 +7557,141 @@
             {
               if (started)
                 {
+                  wassert (!iy);
                   emit2 ("adc hl, %s", _pairs[pair].name);
                   regalloc_dry_run_cost += 2;
                 }
               else
                 {
-                  emit2 ("add hl, %s", _pairs[pair].name);
-                  started = TRUE;
-                  regalloc_dry_run_cost += 1;
+                  emit2 (iy ? "add iy, %s" : "add hl, %s", _pairs[pair].name);
+                  started = true;
+                  regalloc_dry_run_cost += 1 + iy;
                 }
               i += 2;
               continue;
             }
         }
 
-      if ((!premoved || i) && !started && i == size - 2 && !i && isPair (AOP (IC_RIGHT (ic))) && AOP_TYPE (IC_LEFT (ic)) == AOP_IMMD && getPairId (AOP (IC_RIGHT (ic))) != PAIR_HL
-          && isPairDead (PAIR_HL, ic))
+      if ((!premoved || i) && !started && leftop->size - i >= 2 && rightop->size - i >= 2 &&
+        aopInReg (IC_RESULT (ic)->aop, i, IY_IDX) &&
+        (aopInReg (leftop, i, IY_IDX) && (aopInReg (rightop, i, BC_IDX) || aopInReg (rightop, i, DE_IDX)) || aopInReg (rightop, i, IY_IDX) && (aopInReg (leftop, i, BC_IDX) || aopInReg (leftop, i, DE_IDX))))
         {
-          fetchPair (PAIR_HL, AOP (IC_LEFT (ic)));
-          emit2 ("add hl, %s", getPairName (AOP (IC_RIGHT (ic))));
-          started = TRUE;
+          PAIR_ID pair = aopInReg(aopInReg (leftop, i, IY_IDX) ? rightop : leftop, i, BC_IDX) ? PAIR_BC : PAIR_DE;
+          emit2 ("add iy, %s", _pairs[pair].name);
+          started = true;
+          regalloc_dry_run_cost += 2;
+          i += 2;
+        }
+      else if ((!premoved || i) && !started && i == size - 2 && !i && isPair (rightop) && leftop->type == AOP_IMMD &&
+        getPairId (rightop) != PAIR_HL && (IS_TLCS90 || getPairId (rightop) != PAIR_IY) &&
+        isPairDead (PAIR_HL, ic))
+        {
+          genMove_o (ASMOP_HL, 0, IC_LEFT (ic)->aop, i, 2, true, true, de_dead, true, true);
+          emit2 ("add hl, %s", getPairName (IC_RIGHT (ic)->aop));
+          started = true;
           regalloc_dry_run_cost += 1;
           spillPair (PAIR_HL);
-          commitPair (AOP (IC_RESULT (ic)), PAIR_HL, ic, FALSE);
+          genMove_o (IC_RESULT (ic)->aop, i, ASMOP_HL, 0, 2, true, true, de_dead, true, true);
           i += 2;
         }
-     else  if ((!premoved || i) && !started && i == size - 2 && !i && isPair (AOP (IC_LEFT (ic))) && (rightop->type == AOP_LIT  || rightop->type == AOP_IMMD) && getPairId (AOP (IC_LEFT (ic))) != PAIR_HL
-          && isPairDead (PAIR_HL, ic))
+     else  if ((!premoved || i) && !started && i == size - 2 && !i && isPair (leftop) && (rightop->type == AOP_LIT  || rightop->type == AOP_IMMD) &&
+       getPairId (leftop) != PAIR_HL && (IS_TLCS90 || getPairId (leftop) != PAIR_IY) &&
+       isPairDead (PAIR_HL, ic))
         {
-          fetchPair (PAIR_HL, AOP (IC_RIGHT (ic)));
-          emit2 ("add hl, %s", getPairName (AOP (IC_LEFT (ic))));
-          started = TRUE;
+          genMove_o (ASMOP_HL, 0, IC_RIGHT (ic)->aop, i, 2, true, true, de_dead, true, true);
+          emit2 ("add hl, %s", getPairName (IC_LEFT (ic)->aop));
+          started = true;
           regalloc_dry_run_cost += 1;
           spillPair (PAIR_HL);
-          commitPair (AOP (IC_RESULT (ic)), PAIR_HL, ic, FALSE);
+          genMove_o (IC_RESULT (ic)->aop, i, ASMOP_HL, 0, 2, true, true, de_dead, true, true);
           i += 2;
         }
-      else if ((!premoved || i) && !started && i == size - 2 && !i && aopInReg (leftop, i, HL_IDX) && isPair (AOP (IC_RIGHT (ic))) && isPairDead (PAIR_HL, ic))
+      else if ((!premoved || i) && !started && i == size - 2 && !i && aopInReg (leftop, i, HL_IDX) &&
+        isPair (rightop) && getPairId (rightop) != PAIR_HL && (IS_TLCS90 || getPairId (rightop) != PAIR_IY) &&
+        isPairDead (PAIR_HL, ic))
         {
-          emit2 ("add hl, %s", getPairName (AOP (IC_RIGHT (ic))));
-          started = TRUE;
+          emit2 ("add hl, %s", getPairName (IC_RIGHT (ic)->aop));
+          started = true;
           regalloc_dry_run_cost += 1;
-          commitPair (AOP (IC_RESULT (ic)), PAIR_HL, ic, FALSE);
+          genMove_o (IC_RESULT (ic)->aop, i, ASMOP_HL, 0, 2, true, true, de_dead, true, true);
           i += 2;
         }
-      else if ((!premoved || i) && !started && i == size - 2 && !i && isPair (AOP (IC_LEFT (ic))) && aopInReg (rightop, i, HL_IDX) && isPairDead (PAIR_HL, ic))
+      else if ((!premoved || i) && !started && i == size - 2 && !i &&
+        isPair (leftop) && getPairId (leftop) != PAIR_HL && (IS_TLCS90 || getPairId (leftop) != PAIR_IY) &&
+        aopInReg (rightop, i, HL_IDX) && isPairDead (PAIR_HL, ic))
         {
-          emit2 ("add hl, %s", getPairName (AOP (IC_LEFT (ic))));
-          started = TRUE;
+          emit2 ("add hl, %s", getPairName (leftop));
+          started = true;
           regalloc_dry_run_cost += 1;
-          commitPair (AOP (IC_RESULT (ic)), PAIR_HL, ic, FALSE);
+          genMove_o (IC_RESULT (ic)->aop, i, ASMOP_HL, 0, 2, true, true, de_dead, true, true);
           i += 2;
         }
-      else if ((!premoved || i) && !started && i == size - 2 && aopInReg (AOP (IC_RESULT (ic)), i, HL_IDX) &&
-          aopInReg (rightop, i, C_IDX) && !bitVectBitValue (ic->rSurv, B_IDX))
+      else if ((!premoved || i) && !started && i == size - 2 && aopInReg (IC_RESULT (ic)->aop, i, HL_IDX) &&
+          aopInReg (rightop, i, C_IDX) && isRegDead (B_IDX, ic))
         {
           if (aopInReg (rightop, i + 1, H_IDX) || aopInReg (rightop, i + 1, L_IDX))
             {
-              cheapMove (ASMOP_B, 0, AOP (IC_RIGHT (ic)), i + 1, true);
-              fetchPairLong (PAIR_HL, AOP (IC_LEFT (ic)), 0, i);
+              cheapMove (ASMOP_B, 0, IC_RIGHT (ic)->aop, i + 1, true);
+              fetchPairLong (PAIR_HL, IC_LEFT (ic)->aop, 0, i);
             }
           else
             {
-              fetchPairLong (PAIR_HL, AOP (IC_LEFT (ic)), 0, i);
-              cheapMove (ASMOP_B, 0, AOP (IC_RIGHT (ic)), i + 1, true);
+              fetchPairLong (PAIR_HL, IC_LEFT (ic)->aop, 0, i);
+              cheapMove (ASMOP_B, 0, IC_RIGHT (ic)->aop, i + 1, true);
             }
           emit2 ("add hl, bc");
           started = TRUE;
           regalloc_dry_run_cost += 1;
           i += 2;
         }
-      else if (!options.oldralloc && (!premoved || i) && !started && i == size - 2 && aopInReg (AOP (IC_RESULT (ic)), i, HL_IDX) &&
-          aopInReg (leftop, i, C_IDX) && !bitVectBitValue (ic->rSurv, B_IDX))
+      else if ((!premoved || i) && !started && i == size - 2 && aopInReg (IC_RESULT (ic)->aop, i, HL_IDX) &&
+          aopInReg (leftop, i, C_IDX) && isRegDead (B_IDX, ic))
         {
           if (aopInReg (leftop, i + 1, H_IDX) || aopInReg (leftop, i + 1, L_IDX))
             {
-              cheapMove (ASMOP_B, 0, AOP (IC_LEFT (ic)), i + 1, true);
-              fetchPairLong (PAIR_HL, AOP (IC_RIGHT (ic)), 0, i);
+              cheapMove (ASMOP_B, 0, IC_LEFT (ic)->aop, i + 1, true);
+              fetchPairLong (PAIR_HL, IC_RIGHT (ic)->aop, 0, i);
             }
           else
             {
-              fetchPairLong (PAIR_HL, AOP (IC_RIGHT (ic)), 0, i);
-              cheapMove (ASMOP_B, 0, AOP (IC_LEFT (ic)), i + 1, true);
+              fetchPairLong (PAIR_HL, IC_RIGHT (ic)->aop, 0, i);
+              cheapMove (ASMOP_B, 0, IC_LEFT (ic)->aop, i + 1, true);
             }
           emit2 ("add hl, bc");
           started = TRUE;
           regalloc_dry_run_cost += 1;
           i += 2;
         }
-       else if (!options.oldralloc && (!premoved || i) && !started && i == size - 2 && aopInReg (AOP (IC_RESULT (ic)), i, HL_IDX) &&
-          aopInReg (rightop, i, E_IDX) && !bitVectBitValue (ic->rSurv, D_IDX))
+       else if ((!premoved || i) && !started && i == size - 2 && aopInReg (IC_RESULT (ic)->aop, i, HL_IDX) &&
+          aopInReg (rightop, i, E_IDX) && isRegDead (D_IDX, ic))
         {
           if (aopInReg (rightop, i + 1, H_IDX) || aopInReg (rightop, i + 1, L_IDX))
             {
-              cheapMove (ASMOP_D, 0, AOP (IC_RIGHT (ic)), i + 1, true);
-              fetchPairLong (PAIR_HL, AOP (IC_LEFT (ic)), 0, i);
+              cheapMove (ASMOP_D, 0, IC_RIGHT (ic)->aop, i + 1, true);
+              fetchPairLong (PAIR_HL, IC_LEFT (ic)->aop, 0, i);
             }
           else
             {
-              fetchPairLong (PAIR_HL, AOP (IC_LEFT (ic)), 0, i);
-              cheapMove (ASMOP_D, 0, AOP (IC_RIGHT (ic)), i + 1, true);
+              fetchPairLong (PAIR_HL, IC_LEFT (ic)->aop, 0, i);
+              cheapMove (ASMOP_D, 0, IC_RIGHT (ic)->aop, i + 1, true);
             }
           emit2 ("add hl, de");
           started = TRUE;
           regalloc_dry_run_cost += 1;
           i += 2;
         }
-       else if (!options.oldralloc && (!premoved || i) && !started && i == size - 2 && aopInReg (AOP (IC_RESULT (ic)), i, HL_IDX) && 
-          aopInReg (leftop, i, E_IDX) && !bitVectBitValue (ic->rSurv, D_IDX))
+       else if ((!premoved || i) && !started && i == size - 2 && aopInReg (IC_RESULT (ic)->aop, i, HL_IDX) &&
+          aopInReg (leftop, i, E_IDX) && isRegDead (D_IDX, ic))
         {
           if (aopInReg (leftop, i + 1, H_IDX) || aopInReg (leftop, i + 1, L_IDX))
             {
-              cheapMove (ASMOP_D, 0, AOP (IC_LEFT (ic)), i + 1, true);
-              fetchPairLong (PAIR_HL, AOP (IC_RIGHT (ic)), 0, i);
+              cheapMove (ASMOP_D, 0, IC_LEFT (ic)->aop, i + 1, true);
+              fetchPairLong (PAIR_HL, IC_RIGHT (ic)->aop, 0, i);
             }
           else
             {
-              fetchPairLong (PAIR_HL, AOP (IC_RIGHT (ic)), 0, i);
-              cheapMove (ASMOP_D, 0, AOP (IC_LEFT (ic)), i + 1, true);
+              fetchPairLong (PAIR_HL, IC_RIGHT (ic)->aop, 0, i);
+              cheapMove (ASMOP_D, 0, IC_LEFT (ic)->aop, i + 1, true);
             }
           emit2 ("add hl, de");
           started = TRUE;
@@ -6202,15 +7699,18 @@
           i += 2;
         }
       // When adding a literal, the 16 bit addition results in smaller, faster code than two 8-bit additions.
-      else if ((!premoved || i) && aopInReg (AOP (IC_RESULT (ic)), i, HL_IDX) && aopInReg (leftop, i, HL_IDX) && (rightop->type == AOP_LIT && !aopIsLitVal (rightop, i, 1, 0) || rightop->type == AOP_IMMD))
+      else if ((!premoved || i) && aopInReg (IC_RESULT (ic)->aop, i, HL_IDX) && aopInReg (leftop, i, HL_IDX) && (rightop->type == AOP_LIT && !aopIsLitVal (rightop, i, 1, 0) || rightop->type == AOP_IMMD))
         {
           PAIR_ID pair = getFreePairId (ic);
           bool pair_alive;
           if (pair == PAIR_INVALID)
             pair = PAIR_DE;
-          if (pair_alive = !isPairDead (pair, ic))
+          pair_alive = !isPairDead (pair, ic) ||
+            IC_RESULT (ic)->aop->regs[_pairs[pair].l_idx] < i || IC_RESULT (ic)->aop->regs[_pairs[pair].h_idx] < i ||
+            IC_LEFT (ic)->aop->regs[_pairs[pair].l_idx] >= i + 2 || IC_LEFT (ic)->aop->regs[_pairs[pair].h_idx] >= i + 2;
+          if (pair_alive)
             _push (pair);
-          fetchPairLong (pair, AOP (IC_RIGHT (ic)), 0, i);
+          fetchPairLong (pair, IC_RIGHT (ic)->aop, 0, i);
           if (started)
             {
               emit2 ("adc hl, %s", _pairs[pair].name);
@@ -6228,7 +7728,7 @@
           i += 2;
         }
       // When adding registers the 16 bit addition results in smaller, faster code than an 8-bit addition.
-      else if ((!premoved || i) && i == size - 1 && isPairDead (PAIR_HL, ic) && aopInReg (AOP (IC_RESULT (ic)), i, L_IDX)
+      else if ((!premoved || i) && i == size - 1 && isPairDead (PAIR_HL, ic) && aopInReg (IC_RESULT (ic)->aop, i, L_IDX)
         && (aopInReg (leftop, i, L_IDX) || aopInReg (rightop, i, L_IDX))
         && (aopInReg (leftop, i, C_IDX) || aopInReg (rightop, i, C_IDX) || aopInReg (leftop, i, E_IDX) || aopInReg (rightop, i, E_IDX)))
         {
@@ -6249,28 +7749,28 @@
         }
       // When adding a literal, the 16 bit addition results in smaller, slower code than an 8-bit addition.
       else if ((!premoved || i) && optimize.codeSize && !started && i == size - 1 && isPairDead (PAIR_HL, ic)
-        && rightop->type == AOP_LIT && aopInReg (AOP (IC_RESULT (ic)), i, L_IDX) && aopInReg (leftop, i, L_IDX)
-        && (!bitVectBitValue (ic->rSurv, C_IDX) || !bitVectBitValue (ic->rSurv, E_IDX)))
+        && rightop->type == AOP_LIT && aopInReg (IC_RESULT (ic)->aop, i, L_IDX) && aopInReg (leftop, i, L_IDX)
+        && (isRegDead (C_IDX, ic) || isRegDead (E_IDX, ic)))
         {
-          PAIR_ID pair = bitVectBitValue (ic->rSurv, C_IDX) ? PAIR_DE : PAIR_BC;
-          emit2 ("ld %s, !immedbyte", _pairs[pair].l, ((unsigned int) ulFromVal (AOP (IC_RIGHT (ic))->aopu.aop_lit)) & 0xff);
+          PAIR_ID pair = !isRegDead (C_IDX, ic) ? PAIR_DE : PAIR_BC;
+          emit2 ("ld %s, !immedbyte", _pairs[pair].l, ((unsigned int) ulFromVal (IC_RIGHT (ic)->aop->aopu.aop_lit)) & 0xff);
           emit2 ("add hl, %s", _pairs[pair].name);
           started = TRUE;
           regalloc_dry_run_cost += 3;
           i++;
         }
       // Skip over this byte.
-      else if (!premoved && !started && (leftop->type == AOP_REG || AOP (IC_RESULT (ic))->type == AOP_REG) && aopIsLitVal (rightop, i, 1, 0))
+      else if (!premoved && !started && (leftop->type == AOP_REG || IC_RESULT (ic)->aop->type == AOP_REG) && aopIsLitVal (rightop, i, 1, 0))
         {
-          cheapMove (AOP (IC_RESULT (ic)), i, leftop, i, true);
+          cheapMove (IC_RESULT (ic)->aop, i, leftop, i, true);
           i++;
         }
       // Conditional 16-bit inc.
       else if (i == size - 2 && started && aopIsLitVal (rightop, i, 2, 0) && (
-        aopInReg (AOP (IC_RESULT (ic)), i, BC_IDX) && aopInReg (leftop, i, BC_IDX) ||
-        aopInReg (AOP (IC_RESULT (ic)), i, DE_IDX) && aopInReg (leftop, i, DE_IDX) ||
-        aopInReg (AOP (IC_RESULT (ic)), i, HL_IDX) && aopInReg (leftop, i, HL_IDX) ||
-        aopInReg (AOP (IC_RESULT (ic)), i, IY_IDX) && aopInReg (leftop, i, IY_IDX)))
+        aopInReg (IC_RESULT (ic)->aop, i, BC_IDX) && aopInReg (leftop, i, BC_IDX) ||
+        aopInReg (IC_RESULT (ic)->aop, i, DE_IDX) && aopInReg (leftop, i, DE_IDX) ||
+        aopInReg (IC_RESULT (ic)->aop, i, HL_IDX) && aopInReg (leftop, i, HL_IDX) ||
+        aopInReg (IC_RESULT (ic)->aop, i, IY_IDX) && aopInReg (leftop, i, IY_IDX)))
         {
           PAIR_ID pair = getPairId_o (leftop, i);
 
@@ -6288,15 +7788,14 @@
       else if (i == size - 1 && started && aopIsLitVal (rightop, i, 1, 0) &&
         !aopInReg (leftop, i, A_IDX) && // adc a, #0 is cheaper than conditional inc.
         (i < leftop->size &&
-        leftop->type == AOP_REG && AOP (IC_RESULT (ic))->type == AOP_REG &&
-        leftop->aopu.aop_reg[i]->rIdx == AOP (IC_RESULT (ic))->aopu.aop_reg[i]->rIdx &&
-        leftop->aopu.aop_reg[i]->rIdx != IYL_IDX && leftop->aopu.aop_reg[i]->rIdx != IYH_IDX ||
-        leftop->type == AOP_STK && leftop == AOP (IC_RESULT (ic)) ||
+        leftop->type == AOP_REG && IC_RESULT (ic)->aop->type == AOP_REG &&
+        leftop->aopu.aop_reg[i]->rIdx == IC_RESULT (ic)->aop->aopu.aop_reg[i]->rIdx &&
+        ((IS_EZ80_Z80 || IS_Z80N) || leftop->aopu.aop_reg[i]->rIdx != IYL_IDX && leftop->aopu.aop_reg[i]->rIdx != IYH_IDX) ||
+        leftop->type == AOP_STK && leftop == IC_RESULT (ic)->aop ||
         leftop->type == AOP_PAIRPTR && leftop->aopu.aop_pairId == PAIR_HL))
         {
           if (!tlbl && !regalloc_dry_run)
             tlbl = newiTempLabel (0);
-
           if (!regalloc_dry_run)
             emit2 ("jp NC, !tlabel", labelKey2num (tlbl->key));
           regalloc_dry_run_cost += 2; // Use cost of jr as the peephole optimizer can typically optimize this jp into jr. Do not emit jr directly to still allow jump-to-jump optimization.
@@ -6305,19 +7804,33 @@
         }
       else
         {
-          if (!premoved)
+          if (!IS_EZ80_Z80 && !IS_Z80N && (aopInReg (rightop, i, IYL_IDX) || aopInReg (rightop, i, IYH_IDX)))
+            if (!premoved && !aopInReg (leftop, i, IYL_IDX) && !aopInReg (leftop, i, IYL_IDX))
+              {
+                operand *t = IC_RIGHT (ic);
+                IC_RIGHT (ic) = IC_LEFT (ic);
+                IC_LEFT (ic) = t;
+                leftop = IC_LEFT (ic)->aop;
+                rightop = IC_RIGHT (ic)->aop;
+              }
+            else // Can't handle both sides in iy.
+              UNIMPLEMENTED;
+          else if (rightop->type == AOP_STL && i < 2) // can't handle rematerialized stack location on the right.
+            {
+              operand *t = IC_RIGHT (ic);
+              IC_RIGHT (ic) = IC_LEFT (ic);
+              IC_LEFT (ic) = t;
+              leftop = IC_LEFT (ic)->aop;
+              rightop = IC_RIGHT (ic)->aop;
+            }
+
+          if (aopInReg (rightop, i, A_IDX) && !aopInReg (leftop, i, A_IDX)) // Make sure we don't overwrite the other operand.
+            UNIMPLEMENTED;
+          else if (!premoved)
             cheapMove (ASMOP_A, 0, leftop, i, true);
           else
             premoved = FALSE;
 
-          // Can't handle overwritten operand in hl.
-          if (started && (IC_RESULT (ic)->aop->type == AOP_EXSTK ||  IC_RESULT (ic)->aop->type == AOP_PAIRPTR) && requiresHL (IC_RESULT (ic)->aop) &&
-            (aopInReg (leftop, i, L_IDX) || aopInReg (leftop, i, H_IDX) || aopInReg (rightop, i, L_IDX) || aopInReg (rightop, i, H_IDX)))
-            {
-              wassert (regalloc_dry_run);
-              regalloc_dry_run_cost += 1000;
-            }
-
           if (!started && aopIsLitVal (rightop, i, 1, 0))
             ; // Skip over this byte.
           // We can use inc / dec only for the only, top non-zero byte, since it neither takes into account an existing carry nor does it update the carry.
@@ -6326,6 +7839,8 @@
               emit3 (aopIsLitVal (rightop, i, 1, 1) ? A_INC : A_DEC, ASMOP_A, 0);
               started = TRUE;
             }
+          else if (rightop->type == AOP_STL && i < 2)
+            UNIMPLEMENTED;
           else
             {
               emit3_o (started ? A_ADC : A_ADD, ASMOP_A, 0, rightop, i);
@@ -6334,17 +7849,25 @@
 
           _G.preserveCarry = (i != size - 1);
           if (size &&
-            (requiresHL (rightop) && rightop->type != AOP_REG || requiresHL (leftop)
-            && leftop->type != AOP_REG) && AOP_TYPE (IC_RESULT (ic)) == AOP_REG
-            && (AOP (IC_RESULT (ic))->aopu.aop_reg[i]->rIdx == L_IDX
-              || AOP (IC_RESULT (ic))->aopu.aop_reg[i]->rIdx == H_IDX))
+            (requiresHL (rightop) && rightop->size > i + 1 && rightop->type != AOP_REG || (requiresHL (leftop) && leftop->size > i + 1)
+            && leftop->type != AOP_REG) && IC_RESULT (ic)->aop->type == AOP_REG
+            && (IC_RESULT (ic)->aop->aopu.aop_reg[i]->rIdx == L_IDX
+              || IC_RESULT (ic)->aop->aopu.aop_reg[i]->rIdx == H_IDX))
             {
               wassert (cached[0] == -1 || cached[1] == -1);
               cached[cached[0] == -1 ? 0 : 1] = offset++;
               _push (PAIR_AF);
             }
+          // Avoid overwriting still-needed operand in h or l.
+          else if (requiresHL (IC_RESULT (ic)->aop) && IC_RESULT (ic)->aop->type != AOP_REG && (IC_RESULT (ic)->aop->type == AOP_EXSTK || IS_SM83 || IC_RESULT (ic)->aop->type == AOP_PAIRPTR) &&
+            (!isPairDead(PAIR_HL, ic) || i + 1 < size && IC_LEFT(ic)->aop->regs[L_IDX] > i || i + 1 < size && IC_LEFT(ic)->aop->regs[H_IDX] > i || i + 1 < size && IC_RIGHT(ic)->aop->regs[L_IDX] > i || i + 1 < size && IC_RIGHT(ic)->aop->regs[H_IDX] > i))
+            {
+              _push (PAIR_HL);
+              cheapMove (IC_RESULT (ic)->aop, i, ASMOP_A, 0, true);
+              _pop (PAIR_HL);
+            }
           else
-            cheapMove (AOP (IC_RESULT (ic)), i, ASMOP_A, 0, true);
+            cheapMove (IC_RESULT (ic)->aop, i, ASMOP_A, 0, true);
           i++;
         }
     }
@@ -6357,8 +7880,10 @@
   for (size = 1; size >= 0; size--)
     if (cached[size] != -1)
       {
+        if (IC_RESULT (ic)->aop->regs[A_IDX] >= 0 && IC_RESULT (ic)->aop->regs[A_IDX] != size) // Don't overwrite still-needed a below.
+          UNIMPLEMENTED;
         _pop (PAIR_AF);
-        cheapMove (AOP (IC_RESULT (ic)), cached[size], ASMOP_A, 0, true);
+        cheapMove (IC_RESULT (ic)->aop, cached[size], ASMOP_A, 0, true);
       }
 
 release:
@@ -6380,32 +7905,33 @@
   /* will try to generate a decrement */
   /* if the right side is not a literal we cannot */
   if (right->type != AOP_LIT)
-    return FALSE;
+    return false;
 
   /* if the literal value of the right hand side
      is greater than 4 then it is not worth it */
   if ((icount = (unsigned int) ulFromVal (right->aopu.aop_lit)) > 2)
-    return FALSE;
+    return false;
 
   size = getDataSize (IC_RESULT (ic));
 
   /* if decrement 16 bits in register */
   if (sameRegs (left, result) && (size > 1) && isPair (result))
     {
+      regalloc_dry_run_cost += icount * (1 + (getPairId (result) == PAIR_IY));
       while (icount--)
         emit2 ("dec %s", getPairName (result));
-      return TRUE;
+      return true;
     }
 
   /* If result is a pair */
-  if (isPair (AOP (IC_RESULT (ic))))
+  if (isPair (IC_RESULT (ic)->aop))
     {
       fetchPair (getPairId (result), left);
+      regalloc_dry_run_cost += icount * (1 + (getPairId (result) == PAIR_IY));
       while (icount--)
         if (!regalloc_dry_run)
           emit2 ("dec %s", getPairName (result));
-      regalloc_dry_run_cost += 1;
-      return TRUE;
+      return true;
     }
 
   /* if decrement 16 bits in register */
@@ -6413,20 +7939,20 @@
     {
       fetchPair (_getTempPairId (), left);
 
+      regalloc_dry_run_cost += icount * (1 + (_getTempPairId () == PAIR_IY));
       while (icount--)
         if (!regalloc_dry_run)
           emit2 ("dec %s", _getTempPairName ());
-      regalloc_dry_run_cost += 1;
 
-      commitPair (result, _getTempPairId (), ic, FALSE);
+      commitPair (result, _getTempPairId (), ic, false);
 
-      return TRUE;
+      return true;
     }
 
 
   /* if the sizes are greater than 1 then we cannot */
   if (result->size > 1 || left->size > 1)
-    return FALSE;
+    return false;
 
   /* we can if the aops of the left & result match or if they are in
      registers and the registers are the same */
@@ -6434,7 +7960,7 @@
     {
       while (icount--)
         emit3 (A_DEC, result, 0);
-      return TRUE;
+      return true;
     }
 
   if (result->type == AOP_REG)
@@ -6442,10 +7968,10 @@
       cheapMove (result, 0, left, 0, true);
       while (icount--)
         emit3 (A_DEC, result, 0);
-      return TRUE;
+      return true;
     }
 
-  return FALSE;
+  return false;
 }
 
 /*-----------------------------------------------------------------*/
@@ -6478,9 +8004,9 @@
     }
 
   /* Same logic as genPlus */
-  if (IS_GB)
+  if (IS_SM83)
     {
-      if (left->type == AOP_STK || right->type == AOP_STK || AOP_TYPE (IC_RESULT (ic)) == AOP_STK)
+      if (left->type == AOP_STK || right->type == AOP_STK || result->type == AOP_STK)
         {
           if ((left->size == 2 ||
                right->size == 2) && (left->size <= 2 && right->size <= 2))
@@ -6512,9 +8038,9 @@
                 }
               regalloc_dry_run_cost += 5;
 
-              if (AOP_SIZE (IC_RESULT (ic)) > 1)
-                cheapMove (AOP (IC_RESULT (ic)), 1, ASMOP_A, 0, true);
-              cheapMove (AOP (IC_RESULT (ic)), 0, ASMOP_E, 0, true);
+              if (IC_RESULT (ic)->aop->size > 1)
+                cheapMove (IC_RESULT (ic)->aop, 1, ASMOP_A, 0, true);
+              cheapMove (IC_RESULT (ic)->aop, 0, ASMOP_E, 0, true);
               return;
             }
         }
@@ -6528,61 +8054,135 @@
         }
     }
 
+  if ((requiresHL (result) && result->type != AOP_REG || requiresHL (left) && left->type != AOP_REG || requiresHL (right) && right->type != AOP_REG) &&
+    (left->regs[L_IDX] > 0 || left->regs[H_IDX] > 0 || right->regs[L_IDX] > 0 || right->regs[H_IDX] > 0))
+    UNIMPLEMENTED;
   setupToPreserveCarry (result, left, right);
 
   /* if literal right, add a, #-lit, else normal subb */
   while (size)
     {
-      if (!IS_GB &&
-        aopInReg (result, offset, HL_IDX) &&
-        (aopInReg (left, offset, HL_IDX) || left->type == AOP_LIT || left->type == AOP_IY) &&
-        (aopInReg (right, offset, BC_IDX) || aopInReg (right, offset, DE_IDX) || ((right->type == AOP_IY || right->type == AOP_HL) && getFreePairId (ic) != PAIR_INVALID)))
+      if (!IS_SM83 && size >= 2 &&
+        isPairDead (PAIR_HL, ic) &&
+        (aopInReg (result, offset, HL_IDX) || aopInReg (result, offset, DE_IDX) || IS_RAB && result->type == AOP_STK) &&
+        (result->regs[L_IDX] < 0 || result->regs[L_IDX] >= offset) && (result->regs[H_IDX] < 0 || result->regs[H_IDX] >= offset) &&
+        (aopInReg (left, offset, HL_IDX) || (left->type == AOP_LIT || left->type == AOP_IY) && right->regs[L_IDX] < offset && right->regs[H_IDX] < offset) &&
+        (aopInReg (right, offset, BC_IDX) || aopInReg (right, offset, DE_IDX) || ((right->type == AOP_IY || right->type == AOP_HL || IS_RAB && right->type == AOP_STK) && (getFreePairId (ic) == PAIR_DE || getFreePairId (ic) == PAIR_BC))))
         {
           PAIR_ID rightpair;
 
-          if (left->type == AOP_LIT || left->type == AOP_IY)
-            fetchPairLong (PAIR_HL, left, ic, offset);
-          if (right->type == AOP_IY || right->type == AOP_HL)
+          bool a_dead = isRegDead (A_IDX, ic) && (result->regs[A_IDX] < 0 || result->regs[A_IDX] >= offset);
+
+          if (getPartPairId (right, offset) == PAIR_INVALID)
             {
               rightpair = getFreePairId (ic);
-              fetchPairLong (rightpair, right, ic, offset);
+              genMove_o (rightpair == PAIR_DE ? ASMOP_DE : ASMOP_BC, 0, right, offset, 2, a_dead, !aopInReg (left, offset, HL_IDX), false, true, !offset);
             }
           else
             rightpair = getPartPairId (right, offset);
+          if (!aopInReg (left, offset, HL_IDX))
+            genMove_o (ASMOP_HL, 0, left, offset, 2, a_dead, true, false, true, !offset);
 
           if (!offset)
             emit3 (A_CP, ASMOP_A, ASMOP_A);
           emit2 ("sbc hl, %s", _pairs[rightpair].name);
           regalloc_dry_run_cost += 2;
+          spillPair (PAIR_HL);
+          genMove_o (result, offset, ASMOP_HL, 0, 2, a_dead, true, false, true, size <= 2);
           offset += 2;
           size -= 2;
           _G.preserveCarry = !!size;
           continue;
         }
-      
-      if (right->type != AOP_LIT)
-        {    
+        
+      bool l_dead = !(!isRegDead (L_IDX, ic) || left->regs[L_IDX] > offset || right->regs[L_IDX] > offset || result->regs[L_IDX] >= 0 && result->regs[L_IDX] < offset);
+      bool h_dead = !(!isRegDead (H_IDX, ic) || left->regs[H_IDX] > offset || right->regs[H_IDX] > offset || result->regs[H_IDX] >= 0 && result->regs[H_IDX] < offset);
+      bool hl_dead = l_dead && h_dead;
+      bool pushed_hl = false;
+
+      if (right->type == AOP_SFR) // Right operand needs to go through a
+        {
+          asmop *tmpaop;
+
+          if (aopInReg (left, offset, H_IDX))
+            tmpaop = ASMOP_L;
+          else if (aopInReg (left, offset, L_IDX))
+            tmpaop = ASMOP_H;
+          else if (!l_dead && h_dead)
+            tmpaop = ASMOP_H;
+          else
+            tmpaop = ASMOP_L;
+
+          bool tmpaop_dead = aopInReg (tmpaop, 0, L_IDX) ? l_dead : h_dead;
+          if (!tmpaop_dead)
+            {
+              _push (PAIR_HL);
+              pushed_hl = true;
+            }
+
+          if (aopInReg (left, offset, A_IDX))
+            cheapMove (tmpaop, 0, right, offset, false);
+          else
+            {
+              cheapMove (tmpaop, 0, right, offset, true);
+              cheapMove (ASMOP_A, 0, left, offset, true);
+            }
+          emit3_o (offset ? A_SBC : A_SUB, ASMOP_A, 0, tmpaop, 0);
+        }
+      else if (right->type != AOP_LIT)
+        {
+          if ((requiresHL (left) && left->type != AOP_REG || requiresHL (right) && right->type != AOP_REG) && !hl_dead)
+            {
+              _push (PAIR_HL);
+              pushed_hl = true;
+            }
+
           if (!offset)
             {
               if (left->type == AOP_LIT && byteOfVal (left->aopu.aop_lit, offset) == 0x00 && aopInReg (right, offset, A_IDX))
                 emit3 (A_NEG, 0, 0);
+              else if (right->type == AOP_STL)
+                UNIMPLEMENTED;
               else
                 {
                   if (left->type == AOP_LIT && byteOfVal (left->aopu.aop_lit, offset) == 0x00)
                     emit3 (A_XOR, ASMOP_A, ASMOP_A);
                   else
                     cheapMove (ASMOP_A, 0, left, offset, true);
+                  if ((aopInReg (right, offset, L_IDX) || aopInReg (right, offset, H_IDX)) && pushed_hl)
+                    {
+                      _pop (PAIR_HL);
+                      pushed_hl = false;
+                    }
                   emit3_o (A_SUB, ASMOP_A, 0, right, offset);
                 }
             }
+          else if (left->type == AOP_LIT && byteOfVal (left->aopu.aop_lit, offset) == 0x00 && size == 1) // For the last byte, we can do an optimization that results in the same value in a, but different carry.
+            {
+              emit3 (A_SBC, ASMOP_A, ASMOP_A);
+              emit3_o (A_SUB, ASMOP_A, 0, right, offset);
+            }
+          else if (right->type == AOP_STL)
+            UNIMPLEMENTED;
           else
             {
               cheapMove (ASMOP_A, 0, left, offset, true);
+              if ((aopInReg (right, offset, L_IDX) || aopInReg (right, offset, H_IDX)) && pushed_hl)
+                {
+                  _pop (PAIR_HL);
+                  pushed_hl = false;
+                }
               emit3_o (A_SBC, ASMOP_A, 0, right, offset);
             }
         }
       else
         {
+          if (requiresHL (left) && left->type != AOP_REG && !hl_dead)
+            {
+              _push (PAIR_HL);
+              pushed_hl = true;
+            }
+
           cheapMove (ASMOP_A, 0, left, offset, true);
 
           /* first add without previous c */
@@ -6600,12 +8200,19 @@
           else
             emit2 ("adc a, !immedbyte", (unsigned int) ((lit >> (offset * 8)) & 0x0FFL));
         }
+      if (pushed_hl)
+        _pop (PAIR_HL);
       size--;
       _G.preserveCarry = !!size;
       cheapMove (result, offset++, ASMOP_A, 0, true);
+
+      if ((left->type == AOP_PAIRPTR && left->aopu.aop_pairId == PAIR_HL || right->type == AOP_PAIRPTR && right->aopu.aop_pairId == PAIR_HL) &&
+        size &&
+        (aopInReg (result, offset, L_IDX) || aopInReg (result, offset, H_IDX)))
+        UNIMPLEMENTED;
     }
 
-  if (AOP_SIZE (IC_RESULT (ic)) == 3 && left->size == 3 && !sameRegs (result, left))
+  if (IC_RESULT (ic)->aop->size == 3 && left->size == 3 && !sameRegs (result, left))
     {
       wassertl (0, "Tried to subtract on a long pointer");
     }
@@ -6621,7 +8228,7 @@
   aopOp (IC_RIGHT (ic), ic, FALSE, FALSE);
   aopOp (IC_RESULT (ic), ic, TRUE, FALSE);
 
-  genSub (ic, AOP (IC_RESULT (ic)), AOP (IC_LEFT (ic)), AOP (IC_RIGHT (ic)));
+  genSub (ic, IC_RESULT (ic)->aop, IC_LEFT (ic)->aop, IC_RIGHT (ic)->aop);
 
   _G.preserveCarry = FALSE;
   freeAsmop (IC_LEFT (ic), NULL);
@@ -6633,23 +8240,26 @@
 /* genUminusFloat - unary minus for floating points                */
 /*-----------------------------------------------------------------*/
 static void
-genUminusFloat (operand *op, operand *result)
+genUminusFloat (const iCode *ic, operand *result, operand *op)
 {
   emitDebug ("; genUminusFloat");
 
   /* for this we just need to flip the
      first bit then copy the rest in place */
+     
+  if (!isRegDead (A_IDX, ic))
+    _push (PAIR_AF);
 
-  cheapMove (ASMOP_A, 0, AOP (op), MSB32, true);
+  cheapMove (ASMOP_A, 0, op->aop, MSB32, true);
 
   emit2 ("xor a,!immedbyte", 0x80);
   regalloc_dry_run_cost += 2;
-  cheapMove (AOP (result), MSB32, ASMOP_A, 0, true);
+  cheapMove (result->aop, MSB32, ASMOP_A, 0, true);
 
-  if (operandsEqu (result, op))
-    return;
-
-  genMove_o (result->aop, 0, op->aop, 0, AOP_SIZE (op) - 1, !aopInReg(result->aop, MSB32, A_IDX), false);
+  genMove_o (result->aop, 0, op->aop, 0, op->aop->size - 1, !aopInReg (result->aop, MSB32, A_IDX), false, false, true, true);
+  
+  if (!isRegDead (A_IDX, ic))
+    _pop (PAIR_AF);
 }
 
 /*-----------------------------------------------------------------*/
@@ -6664,16 +8274,16 @@
 
   /* if both in bit space then special
      case */
-  if (AOP_TYPE (IC_RESULT (ic)) == AOP_CRY && AOP_TYPE (IC_LEFT (ic)) == AOP_CRY)
+  if (IC_RESULT (ic)->aop->type == AOP_CRY && IC_LEFT (ic)->aop->type == AOP_CRY)
     {
       wassertl (0, "Left and right are in bit space");
       goto release;
     }
 
   if (IS_FLOAT (operandType (IC_LEFT (ic))))
-    genUminusFloat (IC_LEFT (ic), IC_RESULT (ic));
+    genUminusFloat (ic, IC_RESULT (ic), IC_LEFT (ic));
   else
-    genSub (ic, AOP (IC_RESULT (ic)), ASMOP_ZERO, AOP (IC_LEFT (ic)));
+    genSub (ic, IC_RESULT (ic)->aop, ASMOP_ZERO, IC_LEFT (ic)->aop);
 
 release:
   _G.preserveCarry = FALSE;
@@ -6688,86 +8298,90 @@
 genMultOneChar (const iCode * ic)
 {
   symbol *tlbl1, *tlbl2;
-  bool savedB = FALSE;
+  bool savedB = false;
 
-  asmop *result = AOP (IC_RESULT (ic));
-  int resultsize = AOP_SIZE (IC_RESULT (ic));
+  asmop *result = IC_RESULT (ic)->aop;
+  int resultsize = result->size;
 
-  if (IS_GB)
+  if (IC_LEFT (ic)->aop->size > 1 || IC_RIGHT (ic)->aop->size > 2)
+    wassertl (0, "Large multiplication is handled through support function calls.");
+    
+  if (IS_SM83)
     {
-      wassertl (0, "Multiplication is handled through support function calls on gbz80");
+      wassertl (0, "Multiplication is handled through support function calls on sm83");
       return;
     }
 
-  if ((IS_Z180 || IS_EZ80_Z80) && AOP_TYPE (IC_RESULT (ic)) == AOP_REG)
+  if ((IS_Z180 || IS_EZ80_Z80 || IS_Z80N) && IC_RESULT (ic)->aop->type == AOP_REG)
     {
-      if ((resultsize > 1 ? result->aopu.aop_reg[1]->rIdx == B_IDX : !bitVectBitValue (ic->rSurv, B_IDX))
+      if (!IS_Z80N && (resultsize > 1 ? result->aopu.aop_reg[1]->rIdx == B_IDX : isRegDead (B_IDX, ic))
           && result->aopu.aop_reg[0]->rIdx == C_IDX)
         {
-          if (AOP_TYPE (IC_LEFT (ic)) == AOP_REG && AOP (IC_LEFT (ic))->aopu.aop_reg[0]->rIdx == C_IDX ||
-              AOP_TYPE (IC_RIGHT (ic)) == AOP_REG && AOP (IC_RIGHT (ic))->aopu.aop_reg[0]->rIdx == B_IDX)
+          if (IC_LEFT (ic)->aop->type == AOP_REG && IC_LEFT (ic)->aop->aopu.aop_reg[0]->rIdx == C_IDX ||
+              IC_RIGHT (ic)->aop->type == AOP_REG && IC_RIGHT (ic)->aop->aopu.aop_reg[0]->rIdx == B_IDX)
             {
-              cheapMove (ASMOP_C, 0, AOP (IC_LEFT (ic)), LSB, true);
-              cheapMove (ASMOP_B, 0, AOP (IC_RIGHT (ic)), LSB, true);
+              cheapMove (ASMOP_C, 0, IC_LEFT (ic)->aop, LSB, true);
+              cheapMove (ASMOP_B, 0, IC_RIGHT (ic)->aop, LSB, true);
             }
           else
             {
-              cheapMove (ASMOP_B, 0, AOP (IC_LEFT (ic)), LSB, true);
-              cheapMove (ASMOP_C, 0, AOP (IC_RIGHT (ic)), LSB, true);
+              cheapMove (ASMOP_B, 0, IC_LEFT (ic)->aop, LSB, true);
+              cheapMove (ASMOP_C, 0, IC_RIGHT (ic)->aop, LSB, true);
             }
           emit2 ("mlt bc");
           regalloc_dry_run_cost += 2;
           return;
         }
-      if ((resultsize > 1 ? result->aopu.aop_reg[1]->rIdx == D_IDX : !bitVectBitValue (ic->rSurv, D_IDX))
+      if ((resultsize > 1 ? result->aopu.aop_reg[1]->rIdx == D_IDX : isRegDead (D_IDX, ic))
           && result->aopu.aop_reg[0]->rIdx == E_IDX)
         {
-          if (AOP_TYPE (IC_LEFT (ic)) == AOP_REG && AOP (IC_LEFT (ic))->aopu.aop_reg[0]->rIdx == E_IDX ||
-              AOP_TYPE (IC_RIGHT (ic)) == AOP_REG && AOP (IC_RIGHT (ic))->aopu.aop_reg[0]->rIdx == D_IDX)
+          if (IC_LEFT (ic)->aop->type == AOP_REG && IC_LEFT (ic)->aop->aopu.aop_reg[0]->rIdx == E_IDX ||
+              IC_RIGHT (ic)->aop->type == AOP_REG && IC_RIGHT (ic)->aop->aopu.aop_reg[0]->rIdx == D_IDX)
             {
-              cheapMove (ASMOP_E, 0, AOP (IC_LEFT (ic)), LSB, true);
-              cheapMove (ASMOP_D, 0, AOP (IC_RIGHT (ic)), LSB, true);
+              cheapMove (ASMOP_E, 0, IC_LEFT (ic)->aop, LSB, true);
+              cheapMove (ASMOP_D, 0, IC_RIGHT (ic)->aop, LSB, true);
             }
           else
             {
-              cheapMove (ASMOP_D, 0, AOP (IC_LEFT (ic)), LSB, true);
-              cheapMove (ASMOP_E, 0, AOP (IC_RIGHT (ic)), LSB, true);
+              cheapMove (ASMOP_D, 0, IC_LEFT (ic)->aop, LSB, true);
+              cheapMove (ASMOP_E, 0, IC_RIGHT (ic)->aop, LSB, true);
             }
           emit2 ("mlt de");
           regalloc_dry_run_cost += 2;
           return;
         }
-      if (AOP_TYPE (IC_LEFT (ic)) == AOP_REG && AOP_TYPE (IC_RIGHT (ic)) == AOP_REG &&
-          ((AOP (IC_LEFT (ic))->aopu.aop_reg[0]->rIdx == H_IDX && AOP (IC_RIGHT (ic))->aopu.aop_reg[0]->rIdx == L_IDX ||
-            AOP (IC_LEFT (ic))->aopu.aop_reg[0]->rIdx == L_IDX && AOP (IC_RIGHT (ic))->aopu.aop_reg[0]->rIdx == H_IDX) &&
-           (resultsize > 1 ? result->aopu.aop_reg[1]->rIdx == H_IDX : !bitVectBitValue (ic->rSurv, H_IDX))
+      if (!IS_Z80N && IC_LEFT (ic)->aop->type == AOP_REG && IC_RIGHT (ic)->aop->type == AOP_REG &&
+          ((IC_LEFT (ic)->aop->aopu.aop_reg[0]->rIdx == H_IDX && IC_RIGHT (ic)->aop->aopu.aop_reg[0]->rIdx == L_IDX ||
+            IC_LEFT (ic)->aop->aopu.aop_reg[0]->rIdx == L_IDX && IC_RIGHT (ic)->aop->aopu.aop_reg[0]->rIdx == H_IDX) &&
+           (resultsize > 1 ? result->aopu.aop_reg[1]->rIdx == H_IDX : isRegDead (H_IDX, ic))
            && result->aopu.aop_reg[0]->rIdx == L_IDX))
         {
           emit2 ("mlt hl");
+          spillPair (PAIR_HL);
           regalloc_dry_run_cost += 2;
           return;
         }
     }
 
-  if (IS_RAB && isPairDead (PAIR_HL, ic) && isPairDead (PAIR_BC, ic))
+  if (IS_RAB && !IS_R2K && isPairDead (PAIR_HL, ic) && isPairDead (PAIR_BC, ic)) // A wait state bug makes mul unuseable in most scenarios on the original Rabbit 2000.
     {
-      const bool save_de = (resultsize > 1 && bitVectBitValue (ic->rSurv, D_IDX) ||
-        bitVectBitValue (ic->rSurv, E_IDX) && !(AOP_TYPE (IC_LEFT (ic)) == AOP_REG && AOP (IC_LEFT (ic))->aopu.aop_reg[0]->rIdx == E_IDX) && !(AOP_TYPE (IC_RIGHT (ic)) == AOP_REG && AOP (IC_RIGHT (ic))->aopu.aop_reg[0]->rIdx == E_IDX));
+      const bool save_de = (resultsize > 1 && !isRegDead (D_IDX, ic) ||
+        !isRegDead (E_IDX, ic) && !(IC_LEFT (ic)->aop->type == AOP_REG && IC_LEFT (ic)->aop->aopu.aop_reg[0]->rIdx == E_IDX) && !(IC_RIGHT (ic)->aop->type == AOP_REG && IC_RIGHT (ic)->aop->aopu.aop_reg[0]->rIdx == E_IDX));
       if (save_de)
         _push (PAIR_DE);
 
-      if (AOP_TYPE (IC_RIGHT (ic)) == AOP_REG && AOP (IC_RIGHT (ic))->aopu.aop_reg[0]->rIdx == E_IDX)
-         cheapMove (ASMOP_C, 0, AOP (IC_LEFT (ic)), 0, true);
-      else if (AOP_TYPE (IC_LEFT (ic)) == AOP_REG && AOP (IC_LEFT (ic))->aopu.aop_reg[0]->rIdx == E_IDX)
-         cheapMove (ASMOP_C, 0, AOP (IC_RIGHT (ic)), 0, true);
-      else if (AOP_TYPE (IC_RIGHT (ic)) == AOP_REG && AOP (IC_RIGHT (ic))->aopu.aop_reg[0]->rIdx == C_IDX)
-         cheapMove (ASMOP_E, 0, AOP (IC_LEFT (ic)), 0, true);
-      else if (AOP_TYPE (IC_LEFT (ic)) == AOP_REG && AOP (IC_LEFT (ic))->aopu.aop_reg[0]->rIdx == C_IDX)
-         cheapMove (ASMOP_E, 0, AOP (IC_RIGHT (ic)), 0, true);
-      else 
+      if (IC_RIGHT (ic)->aop->type == AOP_REG && IC_RIGHT (ic)->aop->aopu.aop_reg[0]->rIdx == E_IDX)
+         cheapMove (ASMOP_C, 0, IC_LEFT (ic)->aop, 0, true);
+      else if (IC_LEFT (ic)->aop->type == AOP_REG && IC_LEFT (ic)->aop->aopu.aop_reg[0]->rIdx == E_IDX)
+         cheapMove (ASMOP_C, 0, IC_RIGHT (ic)->aop, 0, true);
+      else if (IC_RIGHT (ic)->aop->type == AOP_REG && IC_RIGHT (ic)->aop->aopu.aop_reg[0]->rIdx == C_IDX)
+         cheapMove (ASMOP_E, 0, IC_LEFT (ic)->aop, 0, true);
+      else if (IC_LEFT (ic)->aop->type == AOP_REG && IC_LEFT (ic)->aop->aopu.aop_reg[0]->rIdx == C_IDX)
+         cheapMove (ASMOP_E, 0, IC_RIGHT (ic)->aop, 0, true);
+      else
         {
-          cheapMove (ASMOP_C, 0, AOP (IC_LEFT (ic)), 0, true);
-          cheapMove (ASMOP_E, 0, AOP (IC_RIGHT (ic)), 0, true);
+          cheapMove (ASMOP_C, 0, IC_LEFT (ic)->aop, 0, true);
+          cheapMove (ASMOP_E, 0, IC_RIGHT (ic)->aop, 0, true);
         }
 
       if (resultsize > 1)
@@ -6778,11 +8392,9 @@
 
       emit2 ("mul");
       regalloc_dry_run_cost++;
+      spillPair (PAIR_HL);
 
-      if (resultsize > 1)
-        commitPair (result, PAIR_BC, ic, FALSE);
-      else
-        cheapMove (result, 0, ASMOP_C, 0, true);
+      genMove (result, resultsize > 1 ? ASMOP_BC : ASMOP_C, !isRegDead (A_IDX, ic), true, false, true);
 
       if (save_de)
         _pop (PAIR_DE);
@@ -6795,34 +8407,33 @@
       _G.stack.pushedDE = TRUE;
     }
   if (IS_RAB && !isPairDead (PAIR_BC, ic) ||
-      !(IS_Z180 || IS_EZ80_Z80) && (!options.oldralloc && bitVectBitValue (ic->rSurv, B_IDX) ||
-                   options.oldralloc && bitVectBitValue (ic->rMask, B_IDX) && !(getPairId (AOP (IC_RESULT (ic))) == PAIR_BC)))
+  !(IS_Z180 || IS_EZ80_Z80) && !isRegDead (B_IDX, ic))
     {
       _push (PAIR_BC);
       savedB = TRUE;
     }
 
   // genMult() already swapped operands if necessary.
-  if (AOP_TYPE (IC_LEFT (ic)) == AOP_REG && AOP (IC_LEFT (ic))->aopu.aop_reg[0]->rIdx == E_IDX ||
-      AOP_TYPE (IC_RIGHT (ic)) == AOP_REG && AOP (IC_RIGHT (ic))->aopu.aop_reg[0]->rIdx == H_IDX
-      && !requiresHL (AOP (IC_LEFT (ic))))
+  if (IC_LEFT (ic)->aop->type == AOP_REG && IC_LEFT (ic)->aop->aopu.aop_reg[0]->rIdx == E_IDX ||
+      IC_RIGHT (ic)->aop->type == AOP_REG && IC_RIGHT (ic)->aop->aopu.aop_reg[0]->rIdx == H_IDX
+      && !requiresHL (IC_LEFT (ic)->aop))
     {
-      cheapMove (ASMOP_E, 0, AOP (IC_LEFT (ic)), 0, true);
-      cheapMove (ASMOP_H, 0, AOP (IC_RIGHT (ic)), 0, true);
+      cheapMove (ASMOP_E, 0, IC_LEFT (ic)->aop, 0, true);
+      cheapMove (ASMOP_H, 0, IC_RIGHT (ic)->aop, 0, true);
     }
   else
     {
-      cheapMove (ASMOP_E, 0, AOP (IC_RIGHT (ic)), 0, true);
-      cheapMove (ASMOP_H, 0, AOP (IC_LEFT (ic)), 0, true);
+      cheapMove (ASMOP_E, 0, IC_RIGHT (ic)->aop, 0, true);
+      cheapMove (ASMOP_H, 0, IC_LEFT (ic)->aop, 0, true);
     }
 
   if (IS_Z180 || IS_EZ80_Z80)
     {
       emit2 ("ld l, e");
       emit2 ("mlt hl");
-      regalloc_dry_run_cost += 3;
+      regalloc_dry_run_cost += 3;  
     }
-  else if (IS_RAB)
+  else if (IS_RAB && !IS_R2K) // A wait state bug makes mul unuseable in most scenarios on the original Rabbit 2000.
     {
       emit2 ("ld c, h");
       emit2 ("ld d, !immedbyte", 0x00);
@@ -6850,7 +8461,6 @@
   else
     regalloc_dry_run_cost += 12;
 
-
   spillPair (PAIR_HL);
 
   if (savedB)
@@ -6863,53 +8473,64 @@
       _G.stack.pushedDE = FALSE;
     }
 
-  if (result->type != AOP_HL)
+  genMove (result, ASMOP_HL, isRegDead (A_IDX, ic), true, isPairDead (PAIR_DE, ic), true);
+}
+
+/*----------------------------------------------------------------------*/
+/* genMultTwoChar - generates code for 16x16->(16 to 32) multiplication */
+/*----------------------------------------------------------------------*/
+static void
+genMultTwoChar (const iCode *ic)
+{
+  operand *left = IC_LEFT (ic);
+  operand *right = IC_RIGHT (ic);
+  wassert (IS_RAB && !IS_R2K); // mul instruction is broken on Rabbit 2000.
+  
+  bool save_bc = !isPairDead(PAIR_BC, ic);
+  bool save_de = !isPairDead(PAIR_DE, ic) && getPairId (left->aop) != PAIR_DE && getPairId (right->aop) != PAIR_DE;
+
+  if (save_bc)
+    _push (PAIR_BC);
+  if (save_de)
+    _push (PAIR_DE);
+    
+  if (getPairId (left->aop) == PAIR_BC || getPairId (right->aop) == PAIR_DE)
     {
-      if (resultsize == 1)
-        cheapMove (result, 0, ASMOP_L, 0, true);
-      else
-        commitPair (result, PAIR_HL, ic, FALSE);
+      if (right->aop->regs[C_IDX] >= 0 || right->aop->regs[B_IDX] >= 0)
+        UNIMPLEMENTED;
+      genMove (ASMOP_BC, left->aop, isRegDead (A_IDX, ic), right->aop->regs[L_IDX] < 0 && right->aop->regs[H_IDX] < 0, right->aop->regs[E_IDX] < 0 && right->aop->regs[D_IDX] < 0, true);
+      genMove (ASMOP_DE, right->aop, isRegDead (A_IDX, ic), true, true, true);
     }
   else
     {
-      if (resultsize == 1)
-        {
-          emit2 ("ld a, l");
-          regalloc_dry_run_cost += 1;
-          cheapMove (result, 0, ASMOP_A, 0, true);
-        }
-      else
-        {
-          if (!isPairDead (PAIR_DE, ic))
-            {
-              _push (PAIR_DE);
-              _G.stack.pushedDE = TRUE;
-            }
-          emit2 ("ld e, l");
-          emit2 ("ld d, h");
-          regalloc_dry_run_cost += 2;
-          commitPair (result, PAIR_DE, ic, FALSE);
-          if (!isPairDead (PAIR_DE, ic))
-            {
-              _pop (PAIR_DE);
-              _G.stack.pushedDE = FALSE;
-            }
-        }
+      if (left->aop->regs[C_IDX] >= 0 || left->aop->regs[B_IDX] >= 0)
+        UNIMPLEMENTED;
+      genMove (ASMOP_BC, right->aop, isRegDead (A_IDX, ic), left->aop->regs[L_IDX] < 0 && left->aop->regs[H_IDX] < 0, left->aop->regs[E_IDX] < 0 && left->aop->regs[D_IDX] < 0, true);
+      genMove (ASMOP_DE, left->aop, isRegDead (A_IDX, ic), true, true, true);
     }
+
+  emit2 ("mul");
+  regalloc_dry_run_cost++;
+  
+  genMove (IC_RESULT (ic)->aop, ASMOP_HLBC, isRegDead (A_IDX, ic), isPairDead (PAIR_HL, ic), true, true);
+  
+  if (save_de)
+    _pop (PAIR_DE);
+  if (save_bc)
+    _pop (PAIR_BC);
 }
 
 /*-----------------------------------------------------------------*/
 /* genMult - generates code for multiplication                     */
 /*-----------------------------------------------------------------*/
 static void
-genMult (iCode * ic)
+genMult (iCode *ic)
 {
-  int val;
-  int count, i;
+  int val, i;
   /* If true then the final operation should be a subtract */
-  bool active = FALSE;
+  bool active = false;
   bool byteResult;
-  bool add_in_hl = FALSE;
+  bool add_in_hl = false;
   int a_cost = 0, l_cost = 0;
   PAIR_ID pair;
 
@@ -6918,42 +8539,47 @@
   aopOp (IC_RIGHT (ic), ic, FALSE, FALSE);
   aopOp (IC_RESULT (ic), ic, TRUE, FALSE);
 
-  byteResult = (AOP_SIZE (IC_RESULT (ic)) == 1);
+  byteResult = (IC_RESULT (ic)->aop->size == 1);
 
-  if (AOP_SIZE (IC_LEFT (ic)) > 2 || AOP_SIZE (IC_RIGHT (ic)) > 2 || AOP_SIZE (IC_RESULT (ic)) > 2)
+  if (IC_LEFT (ic)->aop->size > 2 || IC_RIGHT (ic)->aop->size > 2)
     wassertl (0, "Large multiplication is handled through support function calls.");
 
   /* Swap left and right such that right is a literal */
-  if (AOP_TYPE (IC_LEFT (ic)) == AOP_LIT)
+  if (IC_LEFT (ic)->aop->type == AOP_LIT)
     {
       operand *t = IC_RIGHT (ic);
       IC_RIGHT (ic) = IC_LEFT (ic);
       IC_LEFT (ic) = t;
     }
 
-  if (AOP_TYPE (IC_RIGHT (ic)) != AOP_LIT)
+  if (IS_RAB && !IS_R2K && IC_RIGHT (ic)->aop->type != AOP_LIT && !byteResult && IC_LEFT (ic)->aop->size == 2 && IC_RIGHT (ic)->aop->size == 2)
+    {
+      genMultTwoChar (ic);
+      goto release;
+    }  
+  else if (IC_RIGHT (ic)->aop->type != AOP_LIT)
     {
       genMultOneChar (ic);
       goto release;
     }
 
-  wassertl (AOP_TYPE (IC_RIGHT (ic)) == AOP_LIT, "Right must be a literal.");
+  wassertl (IC_RIGHT (ic)->aop->type == AOP_LIT, "Right must be a literal.");
 
-  val = (int) ulFromVal (AOP (IC_RIGHT (ic))->aopu.aop_lit);
+  val = (int) ulFromVal (IC_RIGHT (ic)->aop->aopu.aop_lit);
   wassertl (val != 1, "Can't multiply by 1");
 
   // Try to use mlt.
-  if ((IS_Z180 || IS_EZ80_Z80) && AOP_SIZE (IC_LEFT (ic)) == 1 && AOP_SIZE (IC_RIGHT (ic)) == 1 &&
+  if ((IS_Z180 || IS_EZ80_Z80 || IS_Z80N) && IC_LEFT (ic)->aop->size == 1 && IC_RIGHT (ic)->aop->size == 1 &&
     (byteResult || SPEC_USIGN (getSpec (operandType (IC_LEFT (ic)))) && SPEC_USIGN (getSpec (operandType (IC_RIGHT (ic))))))
     {
-      pair = getPairId (AOP (IC_RESULT (ic)));
-      if (pair == PAIR_INVALID && AOP_TYPE (IC_RESULT (ic)) == AOP_REG)
+      pair = getPairId (IC_RESULT (ic)->aop);
+      if (pair == PAIR_INVALID && IC_RESULT (ic)->aop->type == AOP_REG)
         {
-          if (!bitVectBitValue (ic->rSurv, H_IDX) && AOP (IC_RESULT (ic))->aopu.aop_reg[0]->rIdx == L_IDX)
+          if (isRegDead (H_IDX, ic) && IC_RESULT (ic)->aop->aopu.aop_reg[0]->rIdx == L_IDX)
             pair = PAIR_HL;
-          else if (!bitVectBitValue (ic->rSurv, D_IDX) && AOP (IC_RESULT (ic))->aopu.aop_reg[0]->rIdx == E_IDX)
+          else if (isRegDead (D_IDX, ic) && IC_RESULT (ic)->aop->aopu.aop_reg[0]->rIdx == E_IDX)
             pair = PAIR_HL;
-          else if (!bitVectBitValue (ic->rSurv, B_IDX) && AOP (IC_RESULT (ic))->aopu.aop_reg[0]->rIdx == C_IDX)
+          else if (isRegDead (B_IDX, ic) && IC_RESULT (ic)->aop->aopu.aop_reg[0]->rIdx == C_IDX)
             pair = PAIR_HL;
         }
       else if (pair == PAIR_INVALID)
@@ -6961,13 +8587,13 @@
 
       if (pair == PAIR_INVALID)
         {
-          if (!(AOP_TYPE (IC_RESULT (ic)) == AOP_REG &&
-            (AOP (IC_RESULT (ic))->aopu.aop_reg[0]->rIdx == L_IDX || AOP (IC_RESULT (ic))->aopu.aop_reg[0]->rIdx == H_IDX ||
-            !byteResult && (AOP (IC_RESULT (ic))->aopu.aop_reg[1]->rIdx == L_IDX || AOP (IC_RESULT (ic))->aopu.aop_reg[1]->rIdx == H_IDX))))
+          if (!(IC_RESULT (ic)->aop->type == AOP_REG &&
+            (IC_RESULT (ic)->aop->aopu.aop_reg[0]->rIdx == L_IDX || IC_RESULT (ic)->aop->aopu.aop_reg[0]->rIdx == H_IDX ||
+            !byteResult && (IC_RESULT (ic)->aop->aopu.aop_reg[1]->rIdx == L_IDX || IC_RESULT (ic)->aop->aopu.aop_reg[1]->rIdx == H_IDX))))
             pair = PAIR_HL;
-          else if (!(AOP_TYPE (IC_RESULT (ic)) == AOP_REG &&
-            (AOP (IC_RESULT (ic))->aopu.aop_reg[0]->rIdx == E_IDX || AOP (IC_RESULT (ic))->aopu.aop_reg[0]->rIdx == D_IDX ||
-            !byteResult && (AOP (IC_RESULT (ic))->aopu.aop_reg[1]->rIdx == E_IDX || AOP (IC_RESULT (ic))->aopu.aop_reg[1]->rIdx == D_IDX))))
+          else if (!(IC_RESULT (ic)->aop->type == AOP_REG &&
+            (IC_RESULT (ic)->aop->aopu.aop_reg[0]->rIdx == E_IDX || IC_RESULT (ic)->aop->aopu.aop_reg[0]->rIdx == D_IDX ||
+            !byteResult && (IC_RESULT (ic)->aop->aopu.aop_reg[1]->rIdx == E_IDX || IC_RESULT (ic)->aop->aopu.aop_reg[1]->rIdx == D_IDX))))
             pair = PAIR_DE;
           else
             pair = PAIR_BC;
@@ -6975,40 +8601,45 @@
 
       // For small operands under low register pressure, the standard approach is better than the mlt one.
       if (byteResult && val <= 6 && isPairDead (PAIR_HL, ic) && (isPairDead (PAIR_DE, ic) || isPairDead (PAIR_BC, ic)) &&
-        !(AOP_TYPE (IC_RESULT (ic)) == AOP_REG && (AOP (IC_RESULT (ic))->aopu.aop_reg[0]->rIdx == E_IDX || AOP (IC_RESULT (ic))->aopu.aop_reg[0]->rIdx == C_IDX)))
+        !(IC_RESULT (ic)->aop->type == AOP_REG && (IC_RESULT (ic)->aop->aopu.aop_reg[0]->rIdx == E_IDX || IC_RESULT (ic)->aop->aopu.aop_reg[0]->rIdx == C_IDX)))
         goto no_mlt;
 
+      if (IS_Z80N && pair != PAIR_DE)
+        goto no_mlt;
+
+      asmop *pairop = pair == PAIR_HL ? ASMOP_HL : (pair == PAIR_DE ? ASMOP_DE : ASMOP_BC);
+
       if (!isPairDead (pair, ic))
         _push (pair);
 
       switch (pair)
         {
         case PAIR_HL:
-          if (AOP_TYPE (IC_LEFT (ic)) == AOP_REG && AOP (IC_LEFT (ic))->aopu.aop_reg[0]->rIdx == H_IDX)
-            cheapMove (ASMOP_L, 0, AOP (IC_RIGHT (ic)), 0, true);
+          if (IC_LEFT (ic)->aop->type == AOP_REG && IC_LEFT (ic)->aop->aopu.aop_reg[0]->rIdx == H_IDX)
+            cheapMove (ASMOP_L, 0, IC_RIGHT (ic)->aop, 0, true);
           else
             {
-              cheapMove (ASMOP_L, 0, AOP (IC_LEFT (ic)), 0, true);
-              cheapMove (ASMOP_H, 0, AOP (IC_RIGHT (ic)), 0, true);
+              cheapMove (ASMOP_L, 0, IC_LEFT (ic)->aop, 0, true);
+              cheapMove (ASMOP_H, 0, IC_RIGHT (ic)->aop, 0, true);
             }
           break;
         case PAIR_DE:
-          if (AOP_TYPE (IC_LEFT (ic)) == AOP_REG && AOP (IC_LEFT (ic))->aopu.aop_reg[0]->rIdx == D_IDX)
-            cheapMove (ASMOP_E, 0, AOP (IC_RIGHT (ic)), 0, true);
+          if (IC_LEFT (ic)->aop->type == AOP_REG && IC_LEFT (ic)->aop->aopu.aop_reg[0]->rIdx == D_IDX)
+            cheapMove (ASMOP_E, 0, IC_RIGHT (ic)->aop, 0, true);
           else
             {
-              cheapMove (ASMOP_E, 0, AOP (IC_LEFT (ic)), 0, true);
-              cheapMove (ASMOP_D, 0, AOP (IC_RIGHT (ic)), 0, true);
+              cheapMove (ASMOP_E, 0, IC_LEFT (ic)->aop, 0, true);
+              cheapMove (ASMOP_D, 0, IC_RIGHT (ic)->aop, 0, true);
             }
           break;
         default:
           wassert (pair == PAIR_BC);
-          if (AOP_TYPE (IC_LEFT (ic)) == AOP_REG && AOP (IC_LEFT (ic))->aopu.aop_reg[0]->rIdx == B_IDX)
-            cheapMove (ASMOP_C, 0, AOP (IC_RIGHT (ic)), 0, true);
+          if (IC_LEFT (ic)->aop->type == AOP_REG && IC_LEFT (ic)->aop->aopu.aop_reg[0]->rIdx == B_IDX)
+            cheapMove (ASMOP_C, 0, IC_RIGHT (ic)->aop, 0, true);
           else
             {
-              cheapMove (ASMOP_C, 0, AOP (IC_LEFT (ic)), 0, true);
-              cheapMove (ASMOP_B, 0, AOP (IC_RIGHT (ic)), 0, true);
+              cheapMove (ASMOP_C, 0, IC_LEFT (ic)->aop, 0, true);
+              cheapMove (ASMOP_B, 0, IC_RIGHT (ic)->aop, 0, true);
             }
           break;
         }
@@ -7016,10 +8647,7 @@
       emit2 ("mlt %s", _pairs[pair].name);
       regalloc_dry_run_cost += 2;
 
-      if (byteResult)
-        cheapMove (AOP (IC_RESULT (ic)), 0, pair == PAIR_HL ? ASMOP_L : (pair == PAIR_DE ? ASMOP_E : ASMOP_C), 0, true);
-      else
-        commitPair (AOP (IC_RESULT (ic)), pair, ic, FALSE);
+      genMove_o (IC_RESULT (ic)->aop, 0, pairop, 0, 2 - byteResult, true, pair == PAIR_HL || isPairDead (PAIR_HL, ic), pair == PAIR_DE || isPairDead (PAIR_DE, ic), true, true);
 
       if (!isPairDead (pair, ic))
         _pop (pair);
@@ -7028,14 +8656,49 @@
     }
 no_mlt:
 
+  if (IS_RAB && !IS_R2K && isPairDead(PAIR_DE, ic) && isPairDead(PAIR_BC, ic) && // mul might be cheaper than a series of additions. mul is broken on the original Rabbit 2000.
+    !byteResult && (IC_LEFT (ic)->aop->size > 1 || SPEC_USIGN (getSpec (operandType (IC_LEFT (ic))))))
+    {
+      int num_add = 0;
+      bool active = false;
+      i = val;
+      for (int count = 0; count < 16; count++)
+        {
+          if (count != 0 && active)
+            num_add++;
+          if (i & 0x8000u)
+            {
+              active = true;
+              num_add += active;
+            }
+          i <<= 1;
+        }
+
+      if(num_add > (optimize.codeSize ? 4 : 6))
+        {
+          if (getPairId (IC_LEFT (ic)->aop) == PAIR_BC)
+            fetchPair (PAIR_DE, IC_RIGHT (ic)->aop);
+          else
+            {
+              fetchPairLong (PAIR_DE, IC_LEFT(ic)->aop, ic, 0);
+              fetchPair (PAIR_BC, IC_RIGHT (ic)->aop);
+            }
+          emit2 ("mul");
+          regalloc_dry_run_cost++;
+          spillPair (PAIR_HL);
+          genMove (IC_RESULT (ic)->aop, ASMOP_BC, isRegDead (A_IDX, ic), isPairDead (PAIR_HL, ic), isPairDead (PAIR_DE, ic), true);
+          goto release;
+        }
+    }
+
   pair = PAIR_DE;
-  if (getPairId (AOP (IC_LEFT (ic))) == PAIR_BC ||
-    (byteResult || !bitVectBitValue (ic->rSurv, B_IDX)) && AOP_TYPE (IC_LEFT (ic)) == AOP_REG && AOP (IC_LEFT (ic))->aopu.aop_reg[0]->rIdx == C_IDX)
+  if (getPairId (IC_LEFT (ic)->aop) == PAIR_BC ||
+    (byteResult || isRegDead (B_IDX, ic)) && IC_LEFT (ic)->aop->type == AOP_REG && IC_LEFT (ic)->aop->aopu.aop_reg[0]->rIdx == C_IDX)
     pair = PAIR_BC;
-  if (isPairDead (PAIR_BC, ic) && !(AOP_TYPE (IC_LEFT (ic)) == AOP_REG && AOP (IC_LEFT (ic))->aopu.aop_reg[0]->rIdx == E_IDX))
+  if (isPairDead (PAIR_BC, ic) && !(IC_LEFT (ic)->aop->type == AOP_REG && IC_LEFT (ic)->aop->aopu.aop_reg[0]->rIdx == E_IDX))
     pair = PAIR_BC;
 
-  if (pair == PAIR_DE && (byteResult ? bitVectBitValue (ic->rSurv, E_IDX) : !isPairDead (PAIR_DE, ic)))
+  if (pair == PAIR_DE && (byteResult ? !isRegDead (E_IDX, ic) : !isPairDead (PAIR_DE, ic)))
     {
       _push (PAIR_DE);
       _G.stack.pushedDE = TRUE;
@@ -7045,38 +8708,38 @@
   if (byteResult)
     {
       if (!aopInReg (IC_LEFT (ic)->aop, 0, A_IDX))
-        a_cost += ld_cost (ASMOP_A, AOP (IC_LEFT (ic)));
+        a_cost += ld_cost (ASMOP_A, 0, IC_LEFT (ic)->aop, 0);
       if (!aopInReg (IC_RESULT (ic)->aop, 0, A_IDX))
-        a_cost += ld_cost (AOP (IC_RESULT (ic)), ASMOP_A);
-      if (AOP_TYPE (IC_LEFT (ic)) != AOP_REG || AOP (IC_LEFT (ic))->aopu.aop_reg[0]->rIdx != L_IDX)
-        l_cost += ld_cost (ASMOP_L, AOP (IC_LEFT (ic)));
-      if (AOP_TYPE (IC_RESULT (ic)) != AOP_REG || AOP (IC_RESULT (ic))->aopu.aop_reg[0]->rIdx != L_IDX)
-        l_cost += ld_cost (AOP (IC_RESULT (ic)), ASMOP_L);
+        a_cost += ld_cost (IC_RESULT (ic)->aop, 0, ASMOP_A, 0);
+      if (IC_LEFT (ic)->aop->type != AOP_REG || IC_LEFT (ic)->aop->aopu.aop_reg[0]->rIdx != L_IDX)
+        l_cost += ld_cost (ASMOP_L, 0, IC_LEFT (ic)->aop, 0);
+      if (IC_RESULT (ic)->aop->type != AOP_REG || IC_RESULT (ic)->aop->aopu.aop_reg[0]->rIdx != L_IDX)
+        l_cost += ld_cost (IC_RESULT (ic)->aop, 0, ASMOP_L, 0);
     }
   add_in_hl = (!byteResult || isPairDead (PAIR_HL, ic) && l_cost < a_cost);
 
   if (byteResult)
     {
-      cheapMove (add_in_hl ? ASMOP_L : ASMOP_A, 0, AOP (IC_LEFT (ic)), 0, true);
-      if (AOP_TYPE (IC_LEFT (ic)) != AOP_REG || AOP (IC_LEFT (ic))->aopu.aop_reg[0]->rIdx != (pair == PAIR_BC ? C_IDX : E_IDX))
+      cheapMove (add_in_hl ? ASMOP_L : ASMOP_A, 0, IC_LEFT (ic)->aop, 0, true);
+      if (IC_LEFT (ic)->aop->type != AOP_REG || IC_LEFT (ic)->aop->aopu.aop_reg[0]->rIdx != (pair == PAIR_BC ? C_IDX : E_IDX))
         cheapMove (pair == PAIR_BC ? ASMOP_C : ASMOP_E, 0, add_in_hl ? ASMOP_L : ASMOP_A, 0, true);
     }
-  else if (AOP_SIZE (IC_LEFT (ic)) == 1 && !SPEC_USIGN (getSpec (operandType (IC_LEFT (ic)))))
+  else if (IC_LEFT (ic)->aop->size == 1 && !SPEC_USIGN (getSpec (operandType (IC_LEFT (ic)))))
     {
-      cheapMove (pair == PAIR_BC ? ASMOP_C : ASMOP_E, 0, AOP (IC_LEFT (ic)), 0, true);
+      cheapMove (pair == PAIR_BC ? ASMOP_C : ASMOP_E, 0, IC_LEFT (ic)->aop, 0, true);
       emit2 ("ld a, %s", _pairs[pair].l);
-      emit2 ("rlc a");
+      emit2 ("rlca");
       emit2 ("sbc a, a");
       emit2 ("ld %s, a", _pairs[pair].h);
-      regalloc_dry_run_cost += 5;
+      regalloc_dry_run_cost += 4;
       emit2 ("ld l, %s", _pairs[pair].l);
       emit2 ("ld h, %s", _pairs[pair].h);
       regalloc_dry_run_cost += 2;
     }
   else
     {
-      fetchPair (pair, AOP (IC_LEFT (ic)));
-      if (getPairId (AOP (IC_LEFT (ic))) != PAIR_HL)
+      fetchPair (pair, IC_LEFT (ic)->aop);
+      if (getPairId (IC_LEFT (ic)->aop) != PAIR_HL)
         {
           emit2 ("ld l, %s", _pairs[pair].l);
           emit2 ("ld h, %s", _pairs[pair].h);
@@ -7084,45 +8747,62 @@
         }
     }
 
-  i = val;
-
-  for (count = 0; count < 16; count++)
+  if (!add_in_hl) 
     {
-      if (count != 0 && active)
+      unsigned long long add, sub;
+      int topbit, nonzero;
+
+      wassert(!csdOfVal (&topbit, &nonzero, &add, &sub, IC_RIGHT (ic)->aop->aopu.aop_lit, 0xff));
+      
+      // If the leading digits of the cse are 1 0 -1 we can use 0 1 1 instead to reduce the number of shifts.
+      if (topbit >= 2 && (add & (1ull << topbit)) && (sub & (1ull << (topbit - 2))))
         {
-          if (!add_in_hl)
-            emit2 ("add a, a");
-          else
-            emit2 ("add hl, hl");
-          regalloc_dry_run_cost += 1;
+          add = (add & ~(1u << topbit)) | (3u << (topbit - 2));
+          sub &= ~(1u << (topbit - 1));
+          topbit--;
         }
-      if (i & 0x8000U)
+
+      for (int bit = topbit - 1; bit >= 0; bit--)
         {
-          if (active)
+          emit3 (A_ADD, ASMOP_A, ASMOP_A);
+          if ((add | sub) & (1ull << bit))
             {
-              if (!add_in_hl)
-                emit2 ("add a, %s", _pairs[pair].l);
-              else
-                emit2 ("add hl, %s", _pairs[pair].name);
-              regalloc_dry_run_cost += 1;
+              emit2 (add & (1ull << bit) ? "add a, %s" : "sub a, %s", _pairs[pair].l);
+              regalloc_dry_run_cost++;
             }
-          active = TRUE;
         }
-      i <<= 1;
     }
-
-  spillPair (PAIR_HL);
+  else // Don't try to use CSD for hl, since subtraction there is more expensive than addition.
+    {
+      i = val;
+      for (int count = 0; count < 16; count++)
+        {
+          if (count != 0 && active)
+            {
+              emit2 ("add hl, hl");
+              regalloc_dry_run_cost++;
+            }
+          if (i & 0x8000u)
+            {
+              if (active)
+                {
+                  emit2 ("add hl, %s", _pairs[pair].name);
+                  regalloc_dry_run_cost++;
+                }
+              active = true;
+            }
+          i <<= 1;
+        }
+      spillPair (PAIR_HL);
+    }
 
   if (_G.stack.pushedDE)
     {
       _pop (PAIR_DE);
-      _G.stack.pushedDE = FALSE;
+      _G.stack.pushedDE = false;
     }
 
-  if (byteResult)
-    cheapMove (AOP (IC_RESULT (ic)), 0, add_in_hl ? ASMOP_L : ASMOP_A, 0, true);
-  else
-    commitPair (AOP (IC_RESULT (ic)), PAIR_HL, ic, FALSE);
+  genMove (IC_RESULT (ic)->aop, add_in_hl ? ASMOP_HL : ASMOP_A, true, add_in_hl || isPairDead (PAIR_HL, ic), isPairDead (PAIR_DE, ic), true);
 
 release:
   freeAsmop (IC_LEFT (ic), NULL);
@@ -7167,6 +8847,7 @@
       if (!strcmp (jval, "a"))
         {
           emit3 (A_OR, ASMOP_A, ASMOP_A);
+          regalloc_dry_run_cost++;
           inst = "NZ";
         }
       else if (!strcmp (jval, "z"))
@@ -7216,6 +8897,7 @@
       if (!strcmp (jval, "a"))
         {
           emit3 (A_OR, ASMOP_A, ASMOP_A);
+          regalloc_dry_run_cost++;
           inst = "Z";
         }
       else if (!strcmp (jval, "z"))
@@ -7285,9 +8967,10 @@
   unsigned long long lit = 0ull;
   bool result_in_carry = FALSE;
   int a_always_byte = -1;
+  bool started = false;
 
   /* if left & right are bit variables */
-  if (AOP_TYPE (left) == AOP_CRY && AOP_TYPE (right) == AOP_CRY)
+  if (left->aop->type == AOP_CRY && right->aop->type == AOP_CRY)
     {
       /* Can't happen on the Z80 */
       wassertl (0, "Tried to compare two bits");
@@ -7295,15 +8978,15 @@
   else
     {
       /* Do a long subtract of right from left. */
-      size = max (AOP_SIZE (left), AOP_SIZE (right));
+      size = max (left->aop->size, right->aop->size);
 
-      if (AOP_TYPE (right) == AOP_SFR)  /* Avoid overwriting A */
+      if (right->aop->type == AOP_SFR)  /* Avoid overwriting A */
         {
           bool save_a, save_b, save_bc;
           wassertl (size == 1, "Right side sfr in comparison with more than 8 bits.");
 
-          save_b = bitVectBitValue (ic->rSurv, B_IDX);
-          save_bc = (save_b && bitVectBitValue (ic->rSurv, C_IDX));
+          save_b = !isRegDead (B_IDX, ic);
+          save_bc = (save_b && !isRegDead (C_IDX, ic));
           save_a = (aopInReg (left->aop, 0, A_IDX) ||
                     aopInReg (left->aop, 0, B_IDX) && save_b ||
                     aopInReg (left->aop, 0, C_IDX) && !save_b && save_bc);
@@ -7312,16 +8995,16 @@
             _push (PAIR_BC);
           if (save_a)
             {
-              cheapMove (ASMOP_A, 0, AOP (right), 0, true);
+              cheapMove (ASMOP_A, 0, right->aop, 0, true);
               _push (PAIR_AF);
             }
           else
-            cheapMove (ASMOP_A, 0, AOP (right), 0, true);
+            cheapMove (ASMOP_A, 0, right->aop, 0, true);
           cheapMove (save_b ? ASMOP_C : ASMOP_B, 0, ASMOP_A, 0, true);
           if (save_a)
             _pop (PAIR_AF);
           else
-            cheapMove (ASMOP_A, 0, AOP (left), 0, true);
+            cheapMove (ASMOP_A, 0, left->aop, 0, true);
           emit3_o (A_SUB, ASMOP_A, 0, save_b ? ASMOP_C : ASMOP_B, offset);
           if (save_bc)
             _pop (PAIR_BC);
@@ -7330,16 +9013,55 @@
         }
 
       // Preserve A if necessary
-      if (ifx && size == 1 && !sign && aopInReg (left->aop, 0, A_IDX) && bitVectBitValue (ic->rSurv, A_IDX) &&
-        (AOP_TYPE (right) == AOP_LIT || AOP_TYPE (right) == AOP_REG && AOP (right)->aopu.aop_reg[offset]->rIdx != IYL_IDX && AOP (right)->aopu.aop_reg[offset]->rIdx != IYH_IDX || AOP_TYPE (right) == AOP_STK))
+      if (ifx && size == 1 && !sign && aopInReg (left->aop, 0, A_IDX) && !isRegDead (A_IDX, ic) &&
+        (right->aop->type == AOP_LIT || right->aop->type == AOP_REG && right->aop->aopu.aop_reg[offset]->rIdx != IYL_IDX && right->aop->aopu.aop_reg[offset]->rIdx != IYH_IDX || right->aop->type == AOP_STK))
         {
-          emit3 (A_CP, ASMOP_A, AOP (right));
+          emit3 (A_CP, ASMOP_A, right->aop);
           result_in_carry = TRUE;
           goto release;
         }
+        
+      if (right->aop->type == AOP_LIT && !ullFromVal (right->aop->aopu.aop_lit)) // special case: comparison to 0. Do it here early, so we don't run into sm83 workarounds below.
+        {
+          if (!sign)
+            {
+              /* No sign so it's always false */
+              emit3 (A_CP, ASMOP_A, ASMOP_A);
+              result_in_carry = TRUE;
+            }
+          else
+            {
+              if (!(result->aop->type == AOP_CRY && result->aop->size) && ifx &&
+                (left->aop->type == AOP_REG || left->aop->type == AOP_STK && !IS_SM83))
+                {
+                  if (!regalloc_dry_run)
+                    emit2 ("bit 7, %s", aopGet (left->aop, left->aop->size - 1, FALSE));
+                  regalloc_dry_run_cost += ((left->aop->type == AOP_REG) ? 2 : 4);
+                  genIfxJump (ifx, "nz");
+                  return;
+                }
+             /* Just load in the top most bit */
+             cheapMove (ASMOP_A, 0, left->aop, left->aop->size - 1, true);
+             if (!(result->aop->type == AOP_CRY && result->aop->size) && ifx)
+               {
+                 genIfxJump (ifx, "7");
+                 return;
+               }
+             else
+               {
+                  if (ifx)
+                    {
+                      genIfxJump (ifx, "nc");
+                      return;
+                    }
+                  result_in_carry = FALSE;
+                }
+            }
+          goto release;
+        }
 
-      // On the Gameboy we can't afford to adjust HL as it may trash the carry.
-      if (size > 1 && (IS_GB || IY_RESERVED) && left->aop->type != AOP_REG && right->aop->type != AOP_REG && (requiresHL (AOP (right)) && requiresHL (AOP (left))))
+      // On the SM83 we can't afford to adjust HL as it may trash the carry.
+      if (size > 1 && (IS_SM83 || IY_RESERVED) && left->aop->type != AOP_REG && right->aop->type != AOP_REG && (requiresHL (right->aop) && requiresHL (left->aop)))
         {
           if (!isPairDead (PAIR_DE, ic))
             _push (PAIR_DE);
@@ -7349,24 +9071,28 @@
 
           while (size--)
             {
-              emit2 ("ld a, (de)");
-              emit2 ("%s a, (hl)", offset == 0 ? "sub" : "sbc");
-              regalloc_dry_run_cost += 2;
-
+              emit2 ("ld a, !mems", "de");
+              regalloc_dry_run_cost += 1;
               if (size != 0)
                 {
-                  emit2 ("inc hl");
                   emit2 ("inc de");
-                  regalloc_dry_run_cost += 2;
+                  regalloc_dry_run_cost += 1;
+                }
+              emit2 ("%s a, !*hl", offset == 0 ? "sub" : "sbc");
+              regalloc_dry_run_cost += 1;
+              if (size != 0)
+                {
+                  emit2 ("inc hl");
+                  regalloc_dry_run_cost += 1;
                 }
               offset++;
             }
-          if (sign && IS_GB)
+          if (sign && IS_SM83)
             {
               wassert(isPairDead (PAIR_DE, ic));
-              emit2 ("ld a, (de)");
+              emit2 ("ld a, !mems", "de");
               emit2 ("ld d, a");
-              emit2 ("ld e, (hl)");
+              emit2 ("ld e, !*hl");
               regalloc_dry_run_cost += 3;
             }
 
@@ -7378,15 +9104,15 @@
           result_in_carry = TRUE;
           goto fix;
         }
-      else if (size > 1 && IS_GB && (requiresHL (AOP (right)) && !requiresHL (AOP (left))))
+      else if (size > 1 && IS_SM83 && (requiresHL (right->aop) && right->aop->type != AOP_REG && !requiresHL (left->aop)))
         {
           if (!regalloc_dry_run)
-            aopGet (AOP (right), LSB, FALSE);
+            aopGet (right->aop, LSB, FALSE);
 
           while (size--)
             {
-              cheapMove (ASMOP_A, 0, AOP (left), offset, true);
-              emit2 ("%s a, (hl)", offset == 0 ? "sub" : "sbc");
+              cheapMove (ASMOP_A, 0, left->aop, offset, true);
+              emit2 ("%s a, !*hl", offset == 0 ? "sub" : "sbc");
               regalloc_dry_run_cost += 1;
 
               if (size != 0)
@@ -7398,97 +9124,57 @@
             }
           if (sign)
             {
-              cheapMove (ASMOP_A, 0, AOP (left), offset - 1, true);
+              cheapMove (ASMOP_A, 0, left->aop, offset - 1, true);
               emit2 ("ld d, a");
-              emit2 ("ld e, (hl)");
+              emit2 ("ld e, !*hl");
               regalloc_dry_run_cost += 2;
             }
           spillPair (PAIR_HL);
           result_in_carry = TRUE;
           goto fix;
         }
-      else if (size > 1 && IS_GB && (!requiresHL (AOP (right)) && requiresHL (AOP (left))))
+      else if (size > 1 && IS_SM83 && (!requiresHL (right->aop) && requiresHL (left->aop) && left->aop->type != AOP_REG))
         {
           if (!regalloc_dry_run)
-            aopGet (AOP (left), LSB, FALSE);
+            aopGet (left->aop, LSB, FALSE);
 
           while (size--)
             {
-              emit2 ("ld a, (hl)");
+              emit2 ("ld a, !*hl");
               regalloc_dry_run_cost += 1;
-              emit3_o (offset == 0 ? A_SUB : A_SBC, ASMOP_A, 0, AOP (right), offset);
+              emit3_o (offset == 0 ? A_SUB : A_SBC, ASMOP_A, 0, right->aop, offset);
 
               if (size != 0)
                 {
                   emit2 ("inc hl");
+                  updatePair (PAIR_HL, 1);
                   regalloc_dry_run_cost += 1;
                 }
               offset++;
             }
           if (sign)
             {
-              emit2 ("ld d, (hl)");
+              emit2 ("ld d, !*hl");
               regalloc_dry_run_cost += 1;
-              cheapMove (ASMOP_A, 0, AOP (right), offset - 1, true);
+              cheapMove (ASMOP_A, 0, right->aop, offset - 1, true);
               emit2 ("ld e, a");
               regalloc_dry_run_cost += 1;
             }
-          spillPair (PAIR_HL);
           result_in_carry = TRUE;
           goto fix;
         }
 
-      if (IS_GB && sign && AOP_TYPE (right) != AOP_LIT)
+      if (IS_SM83 && sign && right->aop->type != AOP_LIT)
         {
-          cheapMove (ASMOP_A, 0, AOP (right), size - 1, true);
+          cheapMove (ASMOP_A, 0, right->aop, size - 1, true);
           cheapMove (ASMOP_E, 0, ASMOP_A, 0, true);
-          cheapMove (ASMOP_A, 0, AOP (left), size - 1, true);
+          cheapMove (ASMOP_A, 0, left->aop, size - 1, true);
           cheapMove (ASMOP_D, 0, ASMOP_A, 0, true);
         }
 
-      if (AOP_TYPE (right) == AOP_LIT)
+      if (right->aop->type == AOP_LIT)
         {
-          lit = ullFromVal (AOP (right)->aopu.aop_lit);
-
-          /* optimize if(x < 0) or if(x >= 0) */
-          if (lit == 0ull)
-            {
-              if (!sign)
-                {
-                  /* No sign so it's always false */
-                  emit3 (A_CP, ASMOP_A, ASMOP_A);
-                  result_in_carry = TRUE;
-                }
-              else
-                {
-                  if (!(AOP_TYPE (result) == AOP_CRY && AOP_SIZE (result)) && ifx &&
-                    (AOP_TYPE (left) == AOP_REG || AOP_TYPE (left) == AOP_STK && !IS_GB))
-                    {
-                      if (!regalloc_dry_run)
-                        emit2 ("bit 7, %s", aopGet (AOP (left), AOP_SIZE (left) - 1, FALSE));
-                      regalloc_dry_run_cost += ((AOP_TYPE (left) == AOP_REG) ? 2 : 4);
-                      genIfxJump (ifx, "nz");
-                      return;
-                    }
-                  /* Just load in the top most bit */
-                  cheapMove (ASMOP_A, 0, AOP (left), AOP_SIZE (left) - 1, true);
-                  if (!(AOP_TYPE (result) == AOP_CRY && AOP_SIZE (result)) && ifx)
-                    {
-                      genIfxJump (ifx, "7");
-                      return;
-                    }
-                  else
-                    {
-                      if (ifx)
-                        {
-                          genIfxJump (ifx, "nc");
-                          return;
-                        }
-                      result_in_carry = FALSE;
-                    }
-                }
-              goto release;
-            }
+          lit = ullFromVal (right->aop->aopu.aop_lit);
 
           while (!((lit >> (offset * 8)) & 0xffull))
             {
@@ -7498,10 +9184,10 @@
 
           if (sign)             /* Map signed operands to unsigned ones. This pre-subtraction workaround to lack of signed comparison is cheaper than the post-subtraction one at fix. */
             {
-              if (size == 2 && !(IS_GB || !ifx && requiresHL(AOP(result)) && AOP_TYPE (result) != AOP_REG) && isPairDead (PAIR_HL, ic) && (isPairDead (PAIR_DE, ic) || isPairDead (PAIR_BC, ic)) && (getPairId (AOP (left)) == PAIR_HL || IS_RAB && (AOP_TYPE (left) == AOP_STK || AOP_TYPE (left) == AOP_EXSTK)))
+              if (size == 2 && !(IS_SM83 || !ifx && requiresHL(result->aop) && result->aop->type != AOP_REG) && isPairDead (PAIR_HL, ic) && (isPairDead (PAIR_DE, ic) || isPairDead (PAIR_BC, ic)) && (getPairId (left->aop) == PAIR_HL || IS_RAB && (left->aop->type == AOP_STK || left->aop->type == AOP_EXSTK)))
                 {
                   PAIR_ID litpair = (isPairDead (PAIR_DE, ic) ? PAIR_DE : PAIR_BC);
-                  fetchPair (PAIR_HL, AOP (left));
+                  fetchPair (PAIR_HL, left->aop);
                   emit2 ("ld %s, !immedbyte", _pairs[litpair].name, (unsigned long) ((lit ^ 0x8000u) & 0xffffu));
                   regalloc_dry_run_cost += 3;
                   emit2 ("add hl, hl");
@@ -7520,11 +9206,12 @@
                     }
                   emit2 ("sbc hl, %s", _pairs[litpair].name);
                   regalloc_dry_run_cost += 2;
-                  result_in_carry = TRUE;
+                  spillPair (PAIR_HL);
+                  result_in_carry = true;
                   goto release;
                 }
 
-              cheapMove (ASMOP_A, 0, AOP (left), offset, true);
+              cheapMove (ASMOP_A, 0, left->aop, offset, true);
               if (size == 1)
                 {
                   emit2 ("xor a, !immedbyte", 0x80);
@@ -7537,7 +9224,7 @@
 
               while (size--)
                 {
-                  cheapMove (ASMOP_A, 0, AOP (left), offset, true);
+                  cheapMove (ASMOP_A, 0, left->aop, offset, true);
                   if (!size)
                     {
                       emit2 ("rla");
@@ -7549,34 +9236,37 @@
                   emit2 ("sbc a, !immedbyte", (unsigned long) (((lit >> (offset++ * 8)) & 0xff) ^ (size ? 0x00 : 0x80)));
                   regalloc_dry_run_cost += 2;
                 }
-              result_in_carry = TRUE;
+              result_in_carry = true;
               goto release;
             }
         }
-      if (!IS_GB && (!sign || size > 2) && (getPartPairId (left->aop, offset) == PAIR_HL || size == 2 && left->aop->type == AOP_IY) && isPairDead (PAIR_HL, ic) &&
+      if (!IS_SM83 && (!sign || size > 2) && (getPartPairId (left->aop, offset) == PAIR_HL || size == 2 && left->aop->type == AOP_IY) && isPairDead (PAIR_HL, ic) &&
         (getPartPairId (right->aop, offset) == PAIR_DE || getPartPairId (right->aop, offset) == PAIR_BC))
         {
           if (left->aop->type == AOP_DIR || left->aop->type == AOP_IY)
             fetchPair (PAIR_HL, left->aop);
           emit3 (A_XOR, ASMOP_A, ASMOP_A); // Clear carry.
-          emit2 ("sbc hl, %s", _pairs[getPartPairId (AOP (right), offset)].name);
+          emit2 ("sbc hl, %s", _pairs[getPartPairId (right->aop, offset)].name);
           regalloc_dry_run_cost += 2;
+          spillPair (PAIR_HL);
+          started = true;
           size -= 2;
           offset += 2;
         }
-      else
+      else if (left->aop->type == AOP_LIT)
         {
-          if (AOP_TYPE (left) == AOP_LIT && byteOfVal (AOP (left)->aopu.aop_lit, offset) == 0x00)
+          if (byteOfVal (left->aop->aopu.aop_lit, offset) == 0x00)
             emit3 (A_XOR, ASMOP_A, ASMOP_A);
           else
-            cheapMove (ASMOP_A, 0, AOP (left), offset, true);
-          if (size > 1 && AOP_TYPE (left) == AOP_LIT)
+            cheapMove (ASMOP_A, 0, left->aop, offset, true);
+          if (size > 1)
             {
-              emit3_o (A_CP, ASMOP_A, 0, AOP (right), offset);
-              a_always_byte = byteOfVal (AOP (left)->aopu.aop_lit, offset);
+              emit3_o (A_CP, ASMOP_A, 0, right->aop, offset);
+              started = true;
+              a_always_byte = byteOfVal (left->aop->aopu.aop_lit, offset);
             }
           else
-            emit3_o (A_SUB, ASMOP_A, 0, AOP (right), offset);
+            emit3_o (A_SUB, ASMOP_A, 0, right->aop, offset);
           size--;
           offset++;
         }
@@ -7584,23 +9274,52 @@
       /* Subtract through, propagating the carry */
       while (size)
         {
-          if (!IS_GB && (!sign || size > 2) &&
+          bool left_already_in_a = (left->aop->type == AOP_LIT && byteOfVal (left->aop->aopu.aop_lit, offset) == a_always_byte);
+
+          if (!IS_SM83 && size >= 2 && (!sign || size > 2) && !left_already_in_a &&
             isPairDead (PAIR_HL, ic) &&
-            (getPartPairId (left->aop, offset) == PAIR_HL || left->aop->type == AOP_LIT && right->aop->regs[L_IDX] < offset && right->aop->regs[H_IDX] < offset) &&
+            (getPartPairId (left->aop, offset) == PAIR_HL || (left->aop->type == AOP_LIT || left->aop->type == AOP_IMMD || left->aop->type == AOP_HL || left->aop->type == AOP_IY || IS_RAB && left->aop->type == AOP_STK) && right->aop->regs[L_IDX] < offset && right->aop->regs[H_IDX] < offset) &&
             (getPartPairId (right->aop, offset) == PAIR_DE || getPartPairId (right->aop, offset) == PAIR_BC))
             {
-              fetchPairLong (PAIR_HL, left->aop, 0, offset);
-              emit2 ("sbc hl, %s", _pairs[getPartPairId (AOP (right), offset)].name);
+              genMove_o (ASMOP_HL, 0, left->aop, offset, 2, isRegDead (A_IDX, ic), true, false, true, !offset);
+              if (!started)
+                {
+                  emit2 ("cp a, a");
+                  regalloc_dry_run_cost++;
+                }
+              emit2 ("sbc hl, %s", _pairs[getPartPairId (right->aop, offset)].name);
+              regalloc_dry_run_cost += 2;
+              spillPair (PAIR_HL);
+              started = true;
+              size -= 2;
+              offset += 2;
+            }
+          else if (!IS_SM83 && size >= 2 && (!sign || size > 2) && !left_already_in_a &&
+            isPairDead (PAIR_HL, ic) && isPairDead (PAIR_DE, ic) && left->aop->regs[E_IDX] < offset + 1 && left->aop->regs[D_IDX] < offset + 1 &&
+            (getPartPairId (left->aop, offset) == PAIR_HL || left->aop->type == AOP_LIT || left->aop->type == AOP_IMMD || left->aop->type == AOP_HL || left->aop->type == AOP_IY || IS_RAB && left->aop->type == AOP_STK) &&
+            (right->aop->type == AOP_LIT || right->aop->type == AOP_IMMD || right->aop->type == AOP_HL || right->aop->type == AOP_IY || IS_RAB && right->aop->type == AOP_STK))
+            {
+              genMove_o (ASMOP_DE, 0, right->aop, offset, 2, isRegDead (A_IDX, ic), getPartPairId (left->aop, offset) != PAIR_HL, true, true, !offset);
+              genMove_o (ASMOP_HL, 0, left->aop, offset, 2, isRegDead (A_IDX, ic), true, false, true, !offset);
+              if (!started)
+                {
+                  emit2 ("cp a, a");
+                  regalloc_dry_run_cost++;
+                }
+              emit2 ("sbc hl, de");
               regalloc_dry_run_cost += 2;
+              spillPair (PAIR_HL);
+              started = true;
               size -= 2;
               offset += 2;
             }
           else
             {
-              if (!(left->aop->type == AOP_LIT && byteOfVal (left->aop->aopu.aop_lit, offset) == a_always_byte))
+              if (!left_already_in_a)
                 cheapMove (ASMOP_A, 0, left->aop, offset, true);
               a_always_byte = -1;
-              emit3_o (A_SBC, ASMOP_A, 0, right->aop, offset);
+              emit3_o (started ? A_SBC : A_SUB, ASMOP_A, 0, right->aop, offset);
+              started = true;
               size--;
               offset++;
             }
@@ -7610,7 +9329,7 @@
       /* There is no good signed compare in the Z80, so we need workarounds */
       if (sign)
         {
-          if (!IS_GB)           /* Directly check for overflow, can't be done on GBZ80 */
+          if (!IS_SM83)           /* Directly check for overflow, can't be done on SM83 */
             {
               if (!regalloc_dry_run)
                 {
@@ -7653,7 +9372,7 @@
     }
 
 release:
-  if (AOP_TYPE (result) == AOP_CRY && AOP_SIZE (result))
+  if (result->aop->type == AOP_CRY && result->aop->size)
     {
       if (!result_in_carry)
         {
@@ -7672,7 +9391,7 @@
         {
           if (!result_in_carry)
             {
-              if (!IS_GB)
+              if (!IS_SM83)
                 genIfxJump (ifx, "m");
               else
                 {
@@ -7725,7 +9444,7 @@
   aopOp (right, ic, FALSE, FALSE);
   aopOp (result, ic, TRUE, FALSE);
 
-  setupToPreserveCarry (AOP (result), AOP (left), AOP (right));
+  setupToPreserveCarry (result->aop, left->aop, right->aop);
 
   genCmp (right, left, result, ifx, sign, ic);
 
@@ -7762,7 +9481,7 @@
   aopOp (right, ic, FALSE, FALSE);
   aopOp (result, ic, TRUE, FALSE);
 
-  setupToPreserveCarry (AOP (result), AOP (left), AOP (right));
+  setupToPreserveCarry (result->aop, left->aop, right->aop);
 
   genCmp (left, right, result, ifx, sign, ic);
 
@@ -7779,13 +9498,12 @@
 static PAIR_ID
 gencjneshort (operand *left, operand *right, symbol *lbl, const iCode *ic)
 {
-  int size = max (AOP_SIZE (left), AOP_SIZE (right));
+  int size = max (left->aop->size, right->aop->size);
   int offset = 0;
-  bool a_result = FALSE;
-  bool next_zero;
+  bool a_result = false;
 
   /* Swap the left and right if it makes the computation easier */
-  if (AOP_TYPE (left) == AOP_LIT || aopInReg (right->aop, 0, A_IDX))
+  if (left->aop->type == AOP_LIT || aopInReg (right->aop, 0, A_IDX))
     {
       operand *t = right;
       right = left;
@@ -7793,47 +9511,67 @@
     }
 
   /* Non-destructive compare */
-  if (aopInReg (left->aop, 0, A_IDX) && bitVectBitValue (ic->rSurv, A_IDX) &&
-    (AOP_TYPE (right) == AOP_LIT || AOP_TYPE (right) == AOP_REG && AOP (right)->aopu.aop_reg[offset]->rIdx != IYL_IDX && AOP (right)->aopu.aop_reg[offset]->rIdx != IYH_IDX || AOP_TYPE (right) == AOP_STK))
+  if (aopInReg (left->aop, 0, A_IDX) && !isRegDead (A_IDX, ic) &&
+    (right->aop->type == AOP_LIT ||
+    right->aop->type == AOP_REG && (IS_EZ80_Z80 || IS_Z80N || right->aop->aopu.aop_reg[offset]->rIdx != IYL_IDX && right->aop->aopu.aop_reg[offset]->rIdx != IYH_IDX) ||
+    right->aop->type == AOP_STK))
     {
-      if (AOP_TYPE (right) == AOP_LIT && !byteOfVal (AOP (right)->aopu.aop_lit, 0))
+      bool pushed_hl = false;
+      if(requiresHL (right->aop) && right->aop->type != AOP_REG && !isPairDead(PAIR_HL, ic))
+        {
+          _push (PAIR_HL);
+          pushed_hl = true;
+        }
+        
+      if (right->aop->type == AOP_LIT && !byteOfVal (right->aop->aopu.aop_lit, 0))
         emit3 (A_OR, ASMOP_A, ASMOP_A);
       else
-        emit3 (A_CP, ASMOP_A, AOP (right));
+        emit3 (A_CP, ASMOP_A, right->aop);
+        
+      if (pushed_hl)
+        _pop (PAIR_HL);
+
       if (!regalloc_dry_run)
         emit2 ("jp NZ,!tlabel", labelKey2num (lbl->key));
       regalloc_dry_run_cost += 3;
     }
   /* if the right side is a literal then anything goes */
-  else if (AOP_TYPE (right) == AOP_LIT)
+  else if (right->aop->type == AOP_LIT)
     {
       while (size--)
         {
-          next_zero = size && !byteOfVal (AOP (right)->aopu.aop_lit, offset + 1);
+          bool pushed_hl = false;
+          bool next_zero = size && !byteOfVal (right->aop->aopu.aop_lit, offset + 1);
+
+          if(requiresHL (left->aop) && left->aop->type != AOP_REG && !isPairDead(PAIR_HL, ic))
+            {
+              _push (PAIR_HL);
+              pushed_hl = true;
+            }
 
           // Test for 0 can be done more efficiently using or
-          if (!byteOfVal (AOP (right)->aopu.aop_lit, offset))
+          if (!byteOfVal (right->aop->aopu.aop_lit, offset))
             {
               if (!a_result)
                 {
-                  cheapMove (ASMOP_A, 0, AOP (left), offset, true);
+                  cheapMove (ASMOP_A, 0, left->aop, offset, true);
                   emit3 (A_OR, ASMOP_A, ASMOP_A);
                 }
               else
-                emit3_o (A_OR, ASMOP_A, 0, AOP (left), offset);
+                emit3_o (A_OR, ASMOP_A, 0, left->aop, offset);
 
               a_result = TRUE;
             }
-          else if ((aopInReg (left->aop, 0, A_IDX) && !bitVectBitValue (ic->rSurv, A_IDX) ||
-            AOP_TYPE (left) == AOP_REG && AOP (left)->aopu.aop_reg[offset]->rIdx != IYL_IDX && AOP (left)->aopu.aop_reg[offset]->rIdx != IYH_IDX && !bitVectBitValue (ic->rSurv, AOP (left)->aopu.aop_reg[offset]->rIdx)) &&
-            byteOfVal (AOP (right)->aopu.aop_lit, offset) == 0x01 && !next_zero)
+          else if ((aopInReg (left->aop, 0, A_IDX) && isRegDead (A_IDX, ic) ||
+            left->aop->type == AOP_REG && left->aop->aopu.aop_reg[offset]->rIdx != IYL_IDX && left->aop->aopu.aop_reg[offset]->rIdx != IYH_IDX && !bitVectBitValue (ic->rSurv, left->aop->aopu.aop_reg[offset]->rIdx)) &&
+            byteOfVal (right->aop->aopu.aop_lit, offset) == 0x01 && !next_zero)
             {
               if(!regalloc_dry_run)
-                emit2 ("dec %s", aopGet (AOP (left), offset, FALSE));
+                emit2 ("dec %s", aopGet (left->aop, offset, FALSE));
               regalloc_dry_run_cost++;
               a_result = aopInReg (left->aop, 0, A_IDX);
             }
-          else if (!bitVectBitValue (ic->rSurv, A_IDX) && left->aop->regs[A_IDX] < offset && size && byteOfVal (right->aop->aopu.aop_lit, offset) == 0xff &&
+          else if (isRegDead (A_IDX, ic) && left->aop->regs[A_IDX] < offset && size && byteOfVal (right->aop->aopu.aop_lit, offset) == 0xff &&
             (left->aop->type == AOP_REG || left->aop->type == AOP_STK) &&
             byteOfVal (right->aop->aopu.aop_lit, offset) == byteOfVal (right->aop->aopu.aop_lit, offset + 1))
             {
@@ -7844,15 +9582,15 @@
                   size--;
                 }
               emit3 (A_INC, ASMOP_A, 0);
-              next_zero = size && !byteOfVal (AOP (right)->aopu.aop_lit, offset + 1);
+              next_zero = size && !byteOfVal (right->aop->aopu.aop_lit, offset + 1);
               a_result = true;
             }
-          else if ((aopInReg (left->aop, 0, A_IDX) && !bitVectBitValue (ic->rSurv, A_IDX) ||
-            AOP_TYPE (left) == AOP_REG && AOP (left)->aopu.aop_reg[offset]->rIdx != IYL_IDX && AOP (left)->aopu.aop_reg[offset]->rIdx != IYH_IDX && !bitVectBitValue (ic->rSurv, AOP (left)->aopu.aop_reg[offset]->rIdx)) &&
-            byteOfVal (AOP (right)->aopu.aop_lit, offset) == 0xff && !next_zero)
+          else if ((aopInReg (left->aop, 0, A_IDX) && isRegDead (A_IDX, ic) ||
+            left->aop->type == AOP_REG && left->aop->aopu.aop_reg[offset]->rIdx != IYL_IDX && left->aop->aopu.aop_reg[offset]->rIdx != IYH_IDX && !bitVectBitValue (ic->rSurv, left->aop->aopu.aop_reg[offset]->rIdx)) &&
+            byteOfVal (right->aop->aopu.aop_lit, offset) == 0xff && !next_zero)
             {
               if(!regalloc_dry_run)
-                emit2 ("inc %s", aopGet (AOP (left), offset, FALSE));
+                emit2 ("inc %s", aopGet (left->aop, offset, FALSE));
               regalloc_dry_run_cost++;
               a_result = aopInReg (left->aop, 0, A_IDX);
             }
@@ -7870,6 +9608,9 @@
               a_result = true;
             }
 
+          if (pushed_hl)
+            _pop (PAIR_HL);
+
           // Only emit jump now if there is no following test for 0 (which would just or to a current result in a)
           if (!(next_zero && a_result))
             {
@@ -7882,12 +9623,12 @@
     }
   /* if the right side is in a register or
      pointed to by HL, IX or IY */
-  else if (AOP_TYPE (right) == AOP_REG ||
-           AOP_TYPE (right) == AOP_HL ||
-           AOP_TYPE (right) == AOP_IY ||
-           AOP_TYPE (right) == AOP_STK ||
-           AOP_TYPE (right) == AOP_EXSTK ||
-           AOP_TYPE (right) == AOP_IMMD ||
+  else if (right->aop->type == AOP_REG ||
+           right->aop->type == AOP_HL ||
+           right->aop->type == AOP_IY ||
+           right->aop->type == AOP_STK ||
+           right->aop->type == AOP_EXSTK ||
+           right->aop->type == AOP_IMMD ||
            AOP_IS_PAIRPTR (right, PAIR_HL) || AOP_IS_PAIRPTR (right, PAIR_IX) || AOP_IS_PAIRPTR (right, PAIR_IY))
     {
       while (size--)
@@ -7899,7 +9640,7 @@
               left = t;
             }
 
-          if (!IS_GB && isPairDead (PAIR_HL, ic) &&
+          if (!IS_SM83 && isPairDead (PAIR_HL, ic) &&
             (aopInReg (left->aop, offset, HL_IDX) && (aopInReg (right->aop, offset, BC_IDX) || aopInReg (right->aop, offset, DE_IDX) || getFreePairId (ic) != PAIR_INVALID) ||
             size == 1 && (aopInReg (right->aop, offset, BC_IDX) || aopInReg (right->aop, offset, DE_IDX))))
             {
@@ -7914,23 +9655,27 @@
               if (!regalloc_dry_run)
                 emit2 ("jp NZ,!tlabel", labelKey2num (lbl->key));
               regalloc_dry_run_cost += 5;
-
+              spillPair (PAIR_HL);
               offset += 2;
               size--;
               continue;
             }
 
-          cheapMove (ASMOP_A, 0, AOP (left), offset, true);
-          if (AOP_TYPE (right) == AOP_LIT && byteOfVal (AOP (right)->aopu.aop_lit, offset) == 0)
+          cheapMove (ASMOP_A, 0, left->aop, offset, true);
+          if (right->aop->type == AOP_LIT && byteOfVal (right->aop->aopu.aop_lit, offset) == 0)
             {
               emit3 (A_OR, ASMOP_A, ASMOP_A);
               if (!regalloc_dry_run)
                 emit2 ("jp NZ,!tlabel", labelKey2num (lbl->key));
               regalloc_dry_run_cost += 3;
             }
+          else if (right->aop->type == AOP_STL)
+            {
+              UNIMPLEMENTED;
+            }
           else
             {
-              emit3_o (A_SUB, ASMOP_A, 0, AOP (right), offset);
+              emit3_o (A_SUB, ASMOP_A, 0, right->aop, offset);
               if (!regalloc_dry_run)
                 emit2 ("jp NZ,!tlabel", labelKey2num (lbl->key));
               regalloc_dry_run_cost += 3;
@@ -7944,8 +9689,8 @@
       PAIR_ID pair;
       for (pair = PAIR_BC; pair <= PAIR_HL; pair++)
         {
-          if (((AOP_TYPE (left) != AOP_PAIRPTR) || (AOP (left)->aopu.aop_pairId != pair)) &&
-              ((AOP_TYPE (right) != AOP_PAIRPTR) || (AOP (right)->aopu.aop_pairId != pair)))
+          if (((left->aop->type != AOP_PAIRPTR) || (left->aop->aopu.aop_pairId != pair)) &&
+              ((right->aop->type != AOP_PAIRPTR) || (right->aop->aopu.aop_pairId != pair)))
             {
               break;
             }
@@ -7953,11 +9698,8 @@
       _push (pair);
       while (size--)
         {
-          if (!regalloc_dry_run)
-            _emitMove (_pairs[pair].l, aopGet (AOP (left), offset, FALSE));
-          else
-            regalloc_dry_run_cost += ld_cost (ASMOP_E, AOP (left));
-          cheapMove (ASMOP_A, 0, AOP (right), offset, true);
+          cheapMove (pair == PAIR_BC ? ASMOP_BC : (pair == PAIR_DE ? ASMOP_DE : ASMOP_HL), 0, left->aop, offset, true);
+          cheapMove (ASMOP_A, 0, right->aop, offset, true);
           emit2 ("sub a,%s", _pairs[pair].l);
           regalloc_dry_run_cost += 1;
           if (!regalloc_dry_run)
@@ -8007,24 +9749,24 @@
   aopOp ((right = IC_RIGHT (ic)), ic, FALSE, FALSE);
   aopOp ((result = IC_RESULT (ic)), ic, TRUE, FALSE);
 
-  hl_touched = (AOP_TYPE (IC_LEFT (ic)) == AOP_HL || AOP_TYPE (IC_RIGHT (ic)) == AOP_HL || IS_GB
-                && AOP_TYPE (IC_LEFT (ic)) == AOP_STK || IS_GB && AOP_TYPE (IC_RIGHT (ic)) == AOP_STK);
+  hl_touched = (IC_LEFT (ic)->aop->type == AOP_HL || IC_RIGHT (ic)->aop->type == AOP_HL || IS_SM83
+                && IC_LEFT (ic)->aop->type == AOP_STK || IS_SM83 && IC_RIGHT (ic)->aop->type == AOP_STK);
 
   /* Swap operands if it makes the operation easier. ie if:
      1.  Left is a literal.
    */
-  if (AOP_TYPE (IC_LEFT (ic)) == AOP_LIT || AOP_TYPE (IC_RIGHT (ic)) != AOP_LIT && AOP_TYPE (IC_RIGHT (ic)) != AOP_REG
-      && AOP_TYPE (IC_LEFT (ic)) == AOP_REG)
+  if (IC_LEFT (ic)->aop->type == AOP_LIT || IC_RIGHT (ic)->aop->type != AOP_LIT && IC_RIGHT (ic)->aop->type != AOP_REG
+      && IC_LEFT (ic)->aop->type == AOP_REG)
     {
       operand *t = IC_RIGHT (ic);
       IC_RIGHT (ic) = IC_LEFT (ic);
       IC_LEFT (ic) = t;
     }
 
-  if (ifx && !AOP_SIZE (result))
+  if (ifx && !result->aop->size)
     {
       /* if they are both bit variables */
-      if (AOP_TYPE (left) == AOP_CRY && ((AOP_TYPE (right) == AOP_CRY) || (AOP_TYPE (right) == AOP_LIT)))
+      if (left->aop->type == AOP_CRY && ((right->aop->type == AOP_CRY) || (right->aop->type == AOP_LIT)))
         {
           wassertl (0, "Tried to compare two bits");
         }
@@ -8080,14 +9822,14 @@
     }
 
   /* if they are both bit variables */
-  if (AOP_TYPE (left) == AOP_CRY && ((AOP_TYPE (right) == AOP_CRY) || (AOP_TYPE (right) == AOP_LIT)))
+  if (left->aop->type == AOP_CRY && ((right->aop->type == AOP_CRY) || (right->aop->type == AOP_LIT)))
     {
       wassertl (0, "Tried to compare a bit to either a literal or another bit");
     }
   else
     {
       gencjne (left, right, regalloc_dry_run ? 0 : newiTempLabel (NULL), ic);
-      if (AOP_TYPE (result) == AOP_CRY && AOP_SIZE (result))
+      if (result->aop->type == AOP_CRY && result->aop->size)
         {
           wassert (0);
         }
@@ -8098,9 +9840,8 @@
         }
       /* if the result is used in an arithmetic operation
          then put the result in place */
-      if (AOP_TYPE (result) != AOP_CRY)
-        outAcc (result);
-      /* leave the result in acc */
+      if (result->aop->type != AOP_CRY)
+        genMove (result->aop, ASMOP_A, true, isPairDead (PAIR_HL, ic), isPairDead (PAIR_DE, ic), true);
     }
 
 release:
@@ -8125,7 +9866,7 @@
   aopOp ((result = IC_RESULT (ic)), ic, FALSE, FALSE);
 
   /* if both are bit variables */
-  if (AOP_TYPE (left) == AOP_CRY && AOP_TYPE (right) == AOP_CRY)
+  if (left->aop->type == AOP_CRY && right->aop->type == AOP_CRY)
     {
       wassertl (0, "Tried to and two bits");
     }
@@ -8163,7 +9904,7 @@
   aopOp ((result = IC_RESULT (ic)), ic, FALSE, FALSE);
 
   /* if both are bit variables */
-  if (AOP_TYPE (left) == AOP_CRY && AOP_TYPE (right) == AOP_CRY)
+  if (left->aop->type == AOP_CRY && right->aop->type == AOP_CRY)
     {
       wassertl (0, "Tried to OR two bits");
     }
@@ -8216,7 +9957,7 @@
 jmpTrueOrFalse (iCode * ic, symbol * tlbl)
 {
   // ugly but optimized by peephole
-  // Using emitLabelSpill instead of emitLabel (esp. on gbz80)
+  // Using emitLabelSpill instead of emitLabel (esp. on sm83)
   // We could jump there from locations with different values in hl.
   // This should be changed to a more efficient solution that spills
   // only what and when necessary.
@@ -8261,10 +10002,10 @@
   aopOp ((result = IC_RESULT (ic)), ic, TRUE, FALSE);
 
   bool pushed_a = false;
-  bool a_free = !bitVectBitValue (ic->rSurv, A_IDX) && left->aop->regs[A_IDX] <= 0 && right->aop->regs[A_IDX] <= 0;
+  bool a_free = isRegDead (A_IDX, ic) && left->aop->regs[A_IDX] <= 0 && right->aop->regs[A_IDX] <= 0;
 
   /* if left is a literal & right is not then exchange them */
-  if ((AOP_TYPE (left) == AOP_LIT && AOP_TYPE (right) != AOP_LIT) || (AOP_NEEDSACC (right) && !AOP_NEEDSACC (left)))
+  if ((left->aop->type == AOP_LIT && right->aop->type != AOP_LIT) || (AOP_NEEDSACC (right) && !AOP_NEEDSACC (left)))
     {
       operand *tmp = right;
       right = left;
@@ -8272,19 +10013,19 @@
     }
 
   /* if result = right then exchange them */
-  if (sameRegs (AOP (result), AOP (right)) && !AOP_NEEDSACC (left))
+  if (sameRegs (result->aop, right->aop) && !AOP_NEEDSACC (left))
     {
       operand *tmp = right;
       right = left;
       left = tmp;
     }
 
-  if (AOP_TYPE (right) == AOP_LIT)
-    lit = ullFromVal (AOP (right)->aopu.aop_lit);
+  if (right->aop->type == AOP_LIT)
+    lit = ullFromVal (right->aop->aopu.aop_lit);
 
-  size = AOP_SIZE (result);
+  size = result->aop->size;
 
-  if (AOP_TYPE (left) == AOP_CRY)
+  if (left->aop->type == AOP_CRY)
     {
       wassertl (0, "Tried to perform an AND with a bit as an operand");
       goto release;
@@ -8292,7 +10033,7 @@
 
   /* Make sure A is on the left to not overwrite it. */
   if (aopInReg (right->aop, 0, A_IDX) ||
-    !aopInReg (left->aop, 0, A_IDX) && isPair (AOP (right)) && (getPairId (AOP (right)) == PAIR_HL || getPairId (AOP (right)) == PAIR_IY))
+    !aopInReg (left->aop, 0, A_IDX) && isPair (right->aop) && (getPairId (right->aop) == PAIR_HL || getPairId (right->aop) == PAIR_IY))
     {
       operand *tmp = right;
       right = left;
@@ -8301,12 +10042,12 @@
 
   // if(val & 0xZZ)       - size = 0, ifx != FALSE  -
   // bit = val & 0xZZ     - size = 1, ifx = FALSE -
-  if ((AOP_TYPE (right) == AOP_LIT) && (AOP_TYPE (result) == AOP_CRY) && (AOP_TYPE (left) != AOP_CRY))
+  if ((right->aop->type == AOP_LIT) && (result->aop->type == AOP_CRY) && (left->aop->type != AOP_CRY))
     {
       symbol *tlbl = regalloc_dry_run ? 0 : newiTempLabel (0);
       int sizel;
 
-      sizel = AOP_SIZE (left);
+      sizel = left->aop->size;
       if (size)
         {
           /* PENDING: Test case for this. */
@@ -8325,7 +10066,7 @@
             }
 
           /* Testing for the border bits of the accumulator destructively is cheap. */
-          if ((isLiteralBit (bytelit) == 0 || isLiteralBit (bytelit) == 7) && aopInReg (left->aop, 0, A_IDX) && !bitVectBitValue (ic->rSurv, A_IDX))
+          if ((isLiteralBit (bytelit) == 0 || isLiteralBit (bytelit) == 7) && aopInReg (left->aop, offset, A_IDX) && isRegDead (A_IDX, ic))
             {
               emit3 (isLiteralBit (bytelit) == 0 ? A_RRCA : A_RLCA, 0 , 0);
               jumpcond = "C";
@@ -8334,9 +10075,9 @@
             }
           /* Testing for the inverse of the border bits of some 32-bit registers destructively is cheap. */
           /* More combinations would be possible, but this one is the one that is common in the floating-point library. */
-          else if (AOP_TYPE (left) == AOP_REG && sizel >= 4 && ((lit >> (offset * 8)) & 0xffffffffull) == 0x7fffffffull &&
-            !IS_GB && getPartPairId (AOP (left), offset) == PAIR_HL && isPairDead (PAIR_HL, ic) &&
-            IS_RAB && getPartPairId (AOP (left), offset + 2) == PAIR_DE && isPairDead (PAIR_HL, ic))
+          else if (left->aop->type == AOP_REG && sizel >= 4 && ((lit >> (offset * 8)) & 0xffffffffull) == 0x7fffffffull &&
+            !IS_SM83 && getPartPairId (left->aop, offset) == PAIR_HL && isPairDead (PAIR_HL, ic) &&
+            IS_RAB && getPartPairId (left->aop, offset + 2) == PAIR_DE && isPairDead (PAIR_HL, ic))
             {
               emit3 (A_CP, ASMOP_A, ASMOP_A); // Clear carry.
               emit2 ("adc hl, hl"); // Cannot use "add hl, hl instead, since it does not affect zero flag.
@@ -8349,12 +10090,12 @@
             }
           /* Testing for the inverse of the border bits of some 16-bit registers destructively is cheap. */
           /* More combinations would be possible, but these are the common ones. */
-          else if (AOP_TYPE (left) == AOP_REG && sizel >= 2 && ((lit >> (offset * 8)) & 0xffffull) == 0x7fffull &&
-            (!IS_GB && getPartPairId (AOP (left), offset) == PAIR_HL && isPairDead (PAIR_HL, ic) ||
-            IS_RAB && getPartPairId (AOP (left), offset) == PAIR_DE  && isPairDead (PAIR_DE, ic)))
+          else if (left->aop->type == AOP_REG && sizel >= 2 && ((lit >> (offset * 8)) & 0xffffull) == 0x7fffull &&
+            (!IS_SM83 && getPartPairId (left->aop, offset) == PAIR_HL && isPairDead (PAIR_HL, ic) ||
+            IS_RAB && getPartPairId (left->aop, offset) == PAIR_DE  && isPairDead (PAIR_DE, ic)))
             {
               PAIR_ID pair;
-              switch (AOP (left)->aopu.aop_reg[offset]->rIdx)
+              switch (left->aop->aopu.aop_reg[offset]->rIdx)
                 {
                 case L_IDX:
                 case H_IDX:
@@ -8378,20 +10119,20 @@
               offset += 2;
             }
           /* Testing for the border bits of some 16-bit registers destructively is cheap. */
-          else if (AOP_TYPE (left) == AOP_REG && sizel == 1 &&
+          else if (left->aop->type == AOP_REG && sizel == 1 &&
             (isLiteralBit (bytelit) == 7 && (
-              AOP (left)->aopu.aop_reg[offset]->rIdx == H_IDX && isPairDead (PAIR_HL, ic) ||
-              IS_RAB && AOP (left)->aopu.aop_reg[offset]->rIdx == D_IDX && isPairDead (PAIR_DE, ic) ||
-              AOP (left)->aopu.aop_reg[offset]->rIdx == IYH_IDX && isPairDead (PAIR_IY, ic)
+              left->aop->aopu.aop_reg[offset]->rIdx == H_IDX && isPairDead (PAIR_HL, ic) ||
+              IS_RAB && left->aop->aopu.aop_reg[offset]->rIdx == D_IDX && isPairDead (PAIR_DE, ic) ||
+              left->aop->aopu.aop_reg[offset]->rIdx == IYH_IDX && isPairDead (PAIR_IY, ic)
             ) ||
             isLiteralBit (bytelit) == 0 && IS_RAB && (
-              AOP (left)->aopu.aop_reg[offset]->rIdx == L_IDX && isPairDead (PAIR_HL, ic) ||
-              AOP (left)->aopu.aop_reg[offset]->rIdx == E_IDX && isPairDead (PAIR_DE, ic) ||
-              AOP (left)->aopu.aop_reg[offset]->rIdx == IYL_IDX && isPairDead (PAIR_IY, ic)
+              left->aop->aopu.aop_reg[offset]->rIdx == L_IDX && isPairDead (PAIR_HL, ic) ||
+              left->aop->aopu.aop_reg[offset]->rIdx == E_IDX && isPairDead (PAIR_DE, ic) ||
+              left->aop->aopu.aop_reg[offset]->rIdx == IYL_IDX && isPairDead (PAIR_IY, ic)
               )))
             {
               PAIR_ID pair;
-              switch (AOP (left)->aopu.aop_reg[offset]->rIdx)
+              switch (left->aop->aopu.aop_reg[offset]->rIdx)
                 {
                 case L_IDX:
                 case H_IDX:
@@ -8422,31 +10163,32 @@
             }
           /* Non-destructive and when exactly one bit per byte is set. */
           else if (isLiteralBit (bytelit) >= 0 &&
-            (AOP_TYPE (left) == AOP_STK || aopInReg (left->aop, 0, A_IDX) || AOP_TYPE (left) == AOP_HL || AOP_TYPE (left) == AOP_IY || AOP_TYPE (left) == AOP_REG && AOP (left)->aopu.aop_reg[0]->rIdx != IYL_IDX))
+            (left->aop->type == AOP_STK || aopInReg (left->aop, 0, A_IDX) || left->aop->type == AOP_HL || left->aop->type == AOP_IY || left->aop->type == AOP_REG && left->aop->aopu.aop_reg[0]->rIdx != IYL_IDX))
             {
+              if (requiresHL (left->aop) && left->aop->type != AOP_REG)
+                _push (PAIR_HL);
               if (!regalloc_dry_run)
-                emit2 ("bit %d, %s", isLiteralBit (bytelit), aopGet (AOP (left), offset, FALSE));
-              regalloc_dry_run_cost += (AOP_TYPE (left) == AOP_STK || AOP_TYPE (left) == AOP_IY) ? 4 : 2;
+                emit2 ("bit %d, %s", isLiteralBit (bytelit), aopGet (left->aop, offset, FALSE));
+              regalloc_dry_run_cost += (left->aop->type == AOP_STK || left->aop->type == AOP_IY) ? 4 : 2;
+              if (requiresHL (left->aop) && left->aop->type != AOP_REG)
+                _pop (PAIR_HL);
               sizel--;
               offset++;
             }
           /* Z180 has non-destructive and. */
-          else if ((IS_Z180 || IS_EZ80_Z80) && aopInReg (left->aop, 0, A_IDX) && bitVectBitValue (ic->rSurv, A_IDX) && bytelit != 0x0ff)
+          else if ((IS_Z180 || IS_EZ80_Z80 || IS_Z80N) && aopInReg (left->aop, 0, A_IDX) && !isRegDead (A_IDX, ic) && bytelit != 0x0ff)
             {
               if (!regalloc_dry_run)
-                emit2 ("tst a, %s", aopGet (AOP (right), 0, FALSE));
-              regalloc_dry_run_cost += (AOP_TYPE (right) == AOP_LIT ? 3 : 2);
+                emit2 ("tst a, %s", aopGet (right->aop, 0, FALSE));
+              regalloc_dry_run_cost += (right->aop->type == AOP_LIT ? 3 : 2);
               sizel--;
               offset++;
             }
           /* Generic case, loading into accumulator and testing there. */
           else
             {
-              if (bitVectBitValue (ic->rSurv, A_IDX) || left->aop->regs[A_IDX] > offset || right->aop->regs[A_IDX] > offset)
-                {
-                  regalloc_dry_run_cost += 100;
-                  wassert (regalloc_dry_run);
-                }
+              if (!isRegDead (A_IDX, ic) || left->aop->regs[A_IDX] > offset || right->aop->regs[A_IDX] > offset)
+                UNIMPLEMENTED;
 
               cheapMove (ASMOP_A, 0, left->aop, offset, true);
               if (isLiteralBit (bytelit) == 0 || isLiteralBit (bytelit) == 7)
@@ -8455,7 +10197,7 @@
                   jumpcond = "C";
                 }
               else if (bytelit != 0xffu)
-                emit3_o (A_AND, ASMOP_A, 0, AOP (right), offset);
+                emit3_o (A_AND, ASMOP_A, 0, right->aop, offset);
               else
                 emit3 (A_OR, ASMOP_A, ASMOP_A);     /* For the flags */
               sizel--;
@@ -8488,59 +10230,57 @@
       goto release;
     }
 
-  if (IS_RAB && isPair (AOP (result)) &&
-      (getPairId (AOP (result)) == PAIR_HL && isPair (AOP (right)) && getPairId (AOP (right)) == PAIR_DE ||
-       getPairId (AOP (result)) == PAIR_HL && isPair (AOP (left)) && getPairId (AOP (left)) == PAIR_DE ||
-       isPair (AOP (left)) && getPairId (AOP (left)) == PAIR_IY && getPairId (AOP (result)) == PAIR_IY && isPair (AOP (right))
-       && getPairId (AOP (right)) == PAIR_DE))
+  if (IS_RAB && isPair (result->aop) &&
+      (getPairId (result->aop) == PAIR_HL && isPair (right->aop) && getPairId (right->aop) == PAIR_DE ||
+       getPairId (result->aop) == PAIR_HL && isPair (left->aop) && getPairId (left->aop) == PAIR_DE ||
+       isPair (left->aop) && getPairId (left->aop) == PAIR_IY && getPairId (result->aop) == PAIR_IY && isPair (right->aop)
+       && getPairId (right->aop) == PAIR_DE))
     {
-      if (isPair (AOP (left)) && getPairId (AOP (left)) == PAIR_DE)
-        fetchPair (PAIR_HL, AOP (right));
+      if (isPair (left->aop) && getPairId (left->aop) == PAIR_DE)
+        fetchPair (PAIR_HL, right->aop);
       else                      /* right operand in DE */
-        fetchPair (getPairId (AOP (result)), AOP (left));
+        fetchPair (getPairId (result->aop), left->aop);
       emit2 ("and hl, de");
-      regalloc_dry_run_cost += (getPairId (AOP (result)) == PAIR_HL ? 1 : 2);
+      regalloc_dry_run_cost += (getPairId (result->aop) == PAIR_HL ? 1 : 2);
       goto release;
     }
 
-  wassertl (AOP_TYPE (result) != AOP_CRY, "Result of and is in a bit");
+  wassertl (result->aop->type != AOP_CRY, "Result of and is in a bit");
 
   for (int i = 0; i < size;)
     {
-      if (!bitVectBitValue (ic->rSurv, A_IDX) && left->aop->regs[A_IDX] <= i && right->aop->regs[A_IDX] <= i && (result->aop->regs[A_IDX] < 0 || result->aop->regs[A_IDX] >= i))
+      bool hl_free = isPairDead (PAIR_HL, ic) &&
+        (left->aop->regs[L_IDX] < i && left->aop->regs[H_IDX] < i && right->aop->regs[L_IDX] < i && right->aop->regs[H_IDX] < i) &&
+        (result->aop->regs[L_IDX] < 0 || result->aop->regs[L_IDX] >= i) && (result->aop->regs[H_IDX] < 0 || result->aop->regs[H_IDX] >= i);
+
+      if (isRegDead (A_IDX, ic) && left->aop->regs[A_IDX] <= i && right->aop->regs[A_IDX] <= i && (result->aop->regs[A_IDX] < 0 || result->aop->regs[A_IDX] >= i))
         a_free = true;
 
       if (pushed_a && (aopInReg (left->aop, i, A_IDX) || aopInReg (right->aop, i, A_IDX)))
         {
           _pop (PAIR_AF);
-          if (bitVectBitValue (ic->rSurv, A_IDX))
+          if (!isRegDead (A_IDX, ic))
             _push (PAIR_AF);
           else
             pushed_a = false;
         }
 
-      if (AOP_TYPE (right) == AOP_LIT)
+      if (right->aop->type == AOP_LIT)
         {
           bytelit = byteOfVal (right->aop->aopu.aop_lit, i);
 
-          if (bytelit == 0x00)
-            {
-              cheapMove (result->aop, i, ASMOP_ZERO, 0, a_free);
-              if (aopInReg (result->aop, i, A_IDX))
-                a_free = false;
-              i++;
-              continue;
-            }
-          else if (bytelit == 0xff)
+          if (bytelit == 0x00 || bytelit == 0xff)
             {
-              cheapMove (result->aop, i, AOP (left), i, a_free);
-              if (aopInReg (result->aop, i, A_IDX))
+              int end;
+              for(end = i; end < size && byteOfVal (right->aop->aopu.aop_lit, end) == bytelit; end++);
+              genMove_o (result->aop, i, bytelit == 0x00 ? ASMOP_ZERO : left->aop, i, end - i, a_free, hl_free, !isPairInUse (PAIR_DE, ic), true, true);
+              if (result->aop->regs[A_IDX] >= i && result->aop->regs[A_IDX] < end)
                 a_free = false;
-              i++;
+              i = end;
               continue;
             }
           else if (isLiteralBit (~bytelit & 0xffu) >= 0 &&
-            (AOP_TYPE (result) == AOP_REG || left == right && (AOP_TYPE (result) == AOP_STK || AOP_TYPE (result) == AOP_DIR)))
+            (result->aop->type == AOP_REG || left == right && (result->aop->type == AOP_STK || result->aop->type == AOP_DIR)))
             {
               cheapMove (result->aop, i, left->aop, i, a_free);
               if (!regalloc_dry_run)
@@ -8563,23 +10303,35 @@
               i += 2;
               continue;
             }
+          else if (IS_TLCS90 &&
+            (aopInReg (left->aop, i, HL_IDX) && aopInReg (result->aop, i, HL_IDX) || aopInReg (left->aop, i, H_IDX) && aopInReg (left->aop, i + 1, L_IDX) && aopInReg (result->aop, i, H_IDX) && aopInReg (result->aop, i + 1, L_IDX)))
+            {
+              unsigned short mask = aopInReg (result->aop, i, L_IDX) ? (bytelit + (byteOfVal (right->aop->aopu.aop_lit, i + 1) << 8)) : (byteOfVal (right->aop->aopu.aop_lit, i + 1) + (bytelit << 8));
+              emit2 ("and hl, !immedword", mask);
+              regalloc_dry_run_cost += 3;
+              i += 2;
+              continue;
+            }
         }
 
       if (IS_RAB)
         {
           const bool this_byte_l = aopInReg (result->aop, i, L_IDX) &&
-            (aopInReg (left->aop, i, L_IDX) && aopInReg (left->aop, i, E_IDX) || aopInReg (left->aop, i, E_IDX) && aopInReg (left->aop, i, L_IDX));
+            (aopInReg (left->aop, i, L_IDX) && aopInReg (right->aop, i, E_IDX) || aopInReg (left->aop, i, E_IDX) && aopInReg (right->aop, i, L_IDX));
           const bool this_byte_h = aopInReg (result->aop, i, H_IDX) &&
-            (aopInReg (left->aop, i, H_IDX) && aopInReg (left->aop, i, D_IDX) || aopInReg (left->aop, i, D_IDX) && aopInReg (left->aop, i, H_IDX));
+            (aopInReg (left->aop, i, H_IDX) && aopInReg (right->aop, i, D_IDX) || aopInReg (left->aop, i, D_IDX) && aopInReg (right->aop, i, H_IDX));
           const bool next_byte_l = aopInReg (result->aop, i + 1, L_IDX) &&
-            (aopInReg (left->aop, i + 1, L_IDX) && aopInReg (left->aop, i + 1, E_IDX) || aopInReg (left->aop, i + 1, E_IDX) && aopInReg (left->aop, i + 1, L_IDX));
+            (aopInReg (left->aop, i + 1, L_IDX) && aopInReg (right->aop, i + 1, E_IDX) || aopInReg (left->aop, i + 1, E_IDX) && aopInReg (right->aop, i + 1, L_IDX));
           const bool next_byte_h = aopInReg (result->aop, i + 1, H_IDX) &&
-            (aopInReg (left->aop, i + 1, H_IDX) && aopInReg (left->aop, i + 1, D_IDX) || aopInReg (left->aop, i + 1, D_IDX) && aopInReg (left->aop, i + 1, H_IDX));
+            (aopInReg (left->aop, i + 1, H_IDX) && aopInReg (right->aop, i + 1, D_IDX) || aopInReg (left->aop, i + 1, D_IDX) && aopInReg (right->aop, i + 1, H_IDX));
 
           const bool this_byte = this_byte_l || this_byte_h;
           const bool next_byte = next_byte_l || next_byte_h;
 
-          const bool next_byte_unused = !bitVectBitValue (ic->rMask, this_byte_l ? H_IDX : L_IDX);
+          const int next_byte_idx = this_byte_l ? H_IDX : L_IDX;
+          const bool next_byte_unused = isRegDead (next_byte_idx, ic) &&
+            left->aop->regs[next_byte_idx] <= i && right->aop->regs[next_byte_idx] <= i &&
+            (result->aop->regs[next_byte_idx] < 0 || result->aop->regs[next_byte_idx] >= i);
 
           if (this_byte && (next_byte || next_byte_unused))
             {
@@ -8592,21 +10344,43 @@
 
       if (!a_free)
         {
-          wassert (!pushed_a);
-          _push (PAIR_AF);
+          if (pushed_a)
+            UNIMPLEMENTED;
+          else
+            _push (PAIR_AF);
           pushed_a = true;
           a_free = true;
         }
 
       // Use plain and in a.
       if (aopInReg (right->aop, i, A_IDX))
-        emit3_o (A_AND, ASMOP_A, 0, left->aop, i);
+        {
+          if (requiresHL (left->aop) && left->aop->type != AOP_REG && !hl_free)
+            _push (PAIR_HL);
+          emit3_o (A_AND, ASMOP_A, 0, left->aop, i);
+          if (requiresHL (left->aop) && left->aop->type != AOP_REG && !hl_free)
+            _pop (PAIR_HL);
+        }
       else
         {
+          if (requiresHL (left->aop) && left->aop->type != AOP_REG && !hl_free)
+            _push (PAIR_HL);
           cheapMove (ASMOP_A, 0, left->aop, i, true);
+          if (requiresHL (left->aop) && left->aop->type != AOP_REG && !hl_free)
+            _pop (PAIR_HL);
+
+          if (requiresHL (right->aop) && right->aop->type != AOP_REG && !hl_free)
+            _push (PAIR_HL);
           emit3_o (A_AND, ASMOP_A, 0, right->aop, i);
+          if (requiresHL (right->aop) && right->aop->type != AOP_REG && !hl_free)
+            _pop (PAIR_HL);
         }
-      cheapMove (result->aop, i, ASMOP_A, 0, true);
+
+      hl_free = isPairDead (PAIR_HL, ic) &&
+        (left->aop->regs[L_IDX] <= i && left->aop->regs[H_IDX] <= i && right->aop->regs[L_IDX] <= i && right->aop->regs[H_IDX] <= i) &&
+        (result->aop->regs[L_IDX] < 0 || result->aop->regs[L_IDX] >= i) && (result->aop->regs[H_IDX] < 0 || result->aop->regs[H_IDX] >= i);
+
+      genMove_o (result->aop, i, ASMOP_A, 0, 1, true, hl_free, !isPairInUse (PAIR_DE, ic), true, true);
 
       if (aopInReg (result->aop, i, A_IDX))
         a_free = false;
@@ -8633,15 +10407,33 @@
   unsigned long long lit = 0;
   int bytelit = 0;
 
-  aopOp ((left = IC_LEFT (ic)), ic, FALSE, FALSE);
-  aopOp ((right = IC_RIGHT (ic)), ic, FALSE, FALSE);
-  aopOp ((result = IC_RESULT (ic)), ic, TRUE, FALSE);
+  aopOp (IC_LEFT (ic), ic, FALSE, FALSE);
+  aopOp (IC_RIGHT (ic), ic, FALSE, FALSE);
+  aopOp (IC_RESULT (ic), ic, TRUE, FALSE);
+  
+  left = IC_LEFT (ic);
+  right = IC_RIGHT (ic);
+  result = IC_RESULT (ic);
+
+  if (result->aop->type == AOP_REG && left->aop->type != AOP_REG && right->aop->type != AOP_REG)
+    {
+      if (!requiresHL (right->aop) || (result->aop->regs[L_IDX] < 0 && result->aop->regs[H_IDX] < 0))
+        { /* only if not (right requires HL and result use HL) */
+          genMove (result->aop, left->aop,
+                   isRegDead (A_IDX, ic),
+                   isPairDead (PAIR_HL, ic),
+                   isPairDead (PAIR_DE, ic) && right->aop->regs[D_IDX] < 0 && right->aop->regs[E_IDX] < 0,
+                   true);
+          left = result;
+        }
+    }
+
 
   bool pushed_a = false;
-  bool a_free = !bitVectBitValue (ic->rSurv, A_IDX) && left->aop->regs[A_IDX] <= 0 && right->aop->regs[A_IDX] <= 0;
+  bool a_free = isRegDead (A_IDX, ic) && left->aop->regs[A_IDX] <= 0 && right->aop->regs[A_IDX] <= 0;
 
   /* if left is a literal & right is not then exchange them */
-  if ((AOP_TYPE (left) == AOP_LIT && AOP_TYPE (right) != AOP_LIT) || (AOP_NEEDSACC (right) && !AOP_NEEDSACC (left)))
+  if ((left->aop->type == AOP_LIT && right->aop->type != AOP_LIT) || (AOP_NEEDSACC (right) && !AOP_NEEDSACC (left)))
     {
       operand *tmp = right;
       right = left;
@@ -8649,19 +10441,19 @@
     }
 
   /* if result = right then exchange them */
-  if (sameRegs (AOP (result), AOP (right)) && !AOP_NEEDSACC (left))
+  if (sameRegs (result->aop, right->aop) && !AOP_NEEDSACC (left))
     {
       operand *tmp = right;
       right = left;
       left = tmp;
     }
 
-  if (AOP_TYPE (right) == AOP_LIT)
-    lit = ullFromVal (AOP (right)->aopu.aop_lit);
+  if (right->aop->type == AOP_LIT)
+    lit = ullFromVal (right->aop->aopu.aop_lit);
 
-  size = AOP_SIZE (result);
+  size = result->aop->size;
 
-  if (AOP_TYPE (left) == AOP_CRY)
+  if (left->aop->type == AOP_CRY)
     {
       wassertl (0, "Tried to OR where left is a bit");
       goto release;
@@ -8677,12 +10469,12 @@
 
   // if(val | 0xZZ)       - size = 0, ifx != FALSE  -
   // bit = val | 0xZZ     - size = 1, ifx = FALSE -
-  if ((AOP_TYPE (right) == AOP_LIT) && (AOP_TYPE (result) == AOP_CRY) && (AOP_TYPE (left) != AOP_CRY))
+  if ((right->aop->type == AOP_LIT) && (result->aop->type == AOP_CRY) && (left->aop->type != AOP_CRY))
     {
       symbol *tlbl = regalloc_dry_run ? 0 : newiTempLabel (0);
       int sizel;
 
-      sizel = AOP_SIZE (left);
+      sizel = left->aop->size;
 
       if (size)
         {
@@ -8691,21 +10483,18 @@
       /* PENDING: Modeled after the AND code which is inefficient. */
       while (sizel--)
         {
-          if (!bitVectBitValue (ic->rSurv, A_IDX) && left->aop->regs[A_IDX] <= offset && right->aop->regs[A_IDX] <= offset && (result->aop->regs[A_IDX] < 0 || result->aop->regs[A_IDX] >= offset))
+          if (isRegDead (A_IDX, ic) && left->aop->regs[A_IDX] <= offset && right->aop->regs[A_IDX] <= offset && (result->aop->regs[A_IDX] < 0 || result->aop->regs[A_IDX] >= offset))
             a_free = true;
 
           if (!a_free) // Hard to handle pop with ifx
-            {
-               regalloc_dry_run_cost += 100;
-               wassert (regalloc_dry_run);
-            }
+            UNIMPLEMENTED;
 
           bytelit = (lit >> (offset * 8)) & 0x0FFull;
 
-          cheapMove (ASMOP_A, 0, left->aop, offset, true);  
+          cheapMove (ASMOP_A, 0, left->aop, offset, true);
 
           if (bytelit != 0)
-            emit3_o (A_OR, ASMOP_A, 0, AOP (right), offset);
+            emit3_o (A_OR, ASMOP_A, 0, right->aop, offset);
           else if (ifx)
             {
               /* For the flags */
@@ -8728,40 +10517,42 @@
       goto release;
     }
 
-  wassertl (AOP_TYPE (result) != AOP_CRY, "Result of or is in a bit");
+  wassertl (result->aop->type != AOP_CRY, "Result of or is in a bit");
 
   for (int i = 0; i < size;)
     {
-      if (!bitVectBitValue (ic->rSurv, A_IDX) && left->aop->regs[A_IDX] <= i && right->aop->regs[A_IDX] <= i && (result->aop->regs[A_IDX] < 0 || result->aop->regs[A_IDX] >= i))
+      bool hl_free = isPairDead (PAIR_HL, ic) &&
+        (left->aop->regs[L_IDX] < i && left->aop->regs[H_IDX] < i && right->aop->regs[L_IDX] < i && right->aop->regs[H_IDX] < i) &&
+        (result->aop->regs[L_IDX] < 0 || result->aop->regs[L_IDX] >= i) && (result->aop->regs[H_IDX] < 0 || result->aop->regs[H_IDX] >= i);
+        
+      if (isRegDead (A_IDX, ic) && left->aop->regs[A_IDX] <= i && right->aop->regs[A_IDX] <= i && (result->aop->regs[A_IDX] < 0 || result->aop->regs[A_IDX] >= i))
         a_free = true;
 
       if (pushed_a && (aopInReg (left->aop, i, A_IDX) || aopInReg (right->aop, i, A_IDX)))
         {
           _pop (PAIR_AF);
-          if (bitVectBitValue (ic->rSurv, A_IDX))
+          if (!isRegDead (A_IDX, ic))
             _push (PAIR_AF);
           else
             pushed_a = false;
         }
 
-      if (AOP_TYPE (right) == AOP_LIT)
+      if (right->aop->type == AOP_LIT)
         {
           bytelit = byteOfVal (right->aop->aopu.aop_lit, i);
 
-          if (bytelit == 0xff)
-            {
-              // TODO
-            }
-          else if (bytelit == 0x00)
+          if (bytelit == 0x00 || bytelit == 0xff)
             {
-              cheapMove (result->aop, i, left->aop, i, a_free);
-              if (aopInReg (result->aop, i, A_IDX))
+              int end;
+              for(end = i; end < size && byteOfVal (right->aop->aopu.aop_lit, end) == bytelit; end++);
+              genMove_o (result->aop, i, bytelit == 0x00 ? left->aop : ASMOP_MONE, i, end - i, a_free, hl_free, !isPairInUse (PAIR_DE, ic), true, true);
+              if (result->aop->regs[A_IDX] >= i && result->aop->regs[A_IDX] < end)
                 a_free = false;
-              i++;
+              i = end;
               continue;
             }
           else if (isLiteralBit (bytelit) >= 0 &&
-            (AOP_TYPE (result) == AOP_REG || left == right && (AOP_TYPE (result) == AOP_STK || AOP_TYPE (result) == AOP_DIR)))
+            (result->aop->type == AOP_REG || left == right && (result->aop->type == AOP_STK || result->aop->type == AOP_DIR)))
             {
               cheapMove (result->aop, i, left->aop, i, a_free);
               if (!regalloc_dry_run)
@@ -8784,29 +10575,73 @@
               i += 2;
               continue;
             }
+          else if (IS_RAB &&
+            (aopInReg (result->aop, i, IY_IDX) && (aopInReg (left->aop, i, IY_IDX) && !isPairInUse (PAIR_DE, ic) || aopInReg (left->aop, i, DE_IDX)) ||
+            aopInReg (result->aop, i, IYH_IDX) && aopInReg (result->aop, i + 1, IYL_IDX) && (aopInReg (left->aop, i, IYH_IDX) && aopInReg (left->aop, i + 1, IYL_IDX) && !isPairInUse (PAIR_DE, ic) || aopInReg (left->aop, i, D_IDX) && aopInReg (left->aop, i + 1, E_IDX))))
+            {
+              unsigned short mask = aopInReg (result->aop, i, IYL_IDX) ? (bytelit + (byteOfVal (right->aop->aopu.aop_lit, i + 1) << 8)) : (byteOfVal (right->aop->aopu.aop_lit, i + 1) + (bytelit << 8));
+              bool mask_in_de = (aopInReg (left->aop, i, IYL_IDX) | aopInReg (left->aop, i, IYH_IDX));
+              emit2 (mask_in_de ? "ld de, !immedword" : "ld iy, !immedword", mask);
+              emit2 ("or iy, de");
+              regalloc_dry_run_cost += 5 + !mask_in_de;
+              i += 2;
+              continue;
+            }
+          else if (IS_TLCS90 &&
+            (aopInReg (left->aop, i, HL_IDX) && aopInReg (result->aop, i, HL_IDX) || aopInReg (left->aop, i, H_IDX) && aopInReg (left->aop, i + 1, L_IDX) && aopInReg (result->aop, i, H_IDX) && aopInReg (result->aop, i + 1, L_IDX)))
+            {
+              unsigned short mask = aopInReg (result->aop, i, L_IDX) ? (bytelit + (byteOfVal (right->aop->aopu.aop_lit, i + 1) << 8)) : (byteOfVal (right->aop->aopu.aop_lit, i + 1) + (bytelit << 8));
+              emit2 ("or hl, !immedword", mask);
+              regalloc_dry_run_cost += 3;
+              i += 2;
+              continue;
+            }
         }
 
       if (IS_RAB)
         {
           const bool this_byte_l = aopInReg (result->aop, i, L_IDX) &&
-            (aopInReg (left->aop, i, L_IDX) && aopInReg (left->aop, i, E_IDX) || aopInReg (left->aop, i, E_IDX) && aopInReg (left->aop, i, L_IDX));
+            (aopInReg (left->aop, i, L_IDX) && aopInReg (right->aop, i, E_IDX) || aopInReg (left->aop, i, E_IDX) && aopInReg (right->aop, i, L_IDX));
           const bool this_byte_h = aopInReg (result->aop, i, H_IDX) &&
-            (aopInReg (left->aop, i, H_IDX) && aopInReg (left->aop, i, D_IDX) || aopInReg (left->aop, i, D_IDX) && aopInReg (left->aop, i, H_IDX));
+            (aopInReg (left->aop, i, H_IDX) && aopInReg (right->aop, i, D_IDX) || aopInReg (left->aop, i, D_IDX) && aopInReg (right->aop, i, H_IDX));
           const bool next_byte_l = aopInReg (result->aop, i + 1, L_IDX) &&
-            (aopInReg (left->aop, i + 1, L_IDX) && aopInReg (left->aop, i + 1, E_IDX) || aopInReg (left->aop, i + 1, E_IDX) && aopInReg (left->aop, i + 1, L_IDX));
+            (aopInReg (left->aop, i + 1, L_IDX) && aopInReg (right->aop, i + 1, E_IDX) || aopInReg (left->aop, i + 1, E_IDX) && aopInReg (right->aop, i + 1, L_IDX));
           const bool next_byte_h = aopInReg (result->aop, i + 1, H_IDX) &&
-            (aopInReg (left->aop, i + 1, H_IDX) && aopInReg (left->aop, i + 1, D_IDX) || aopInReg (left->aop, i + 1, D_IDX) && aopInReg (left->aop, i + 1, H_IDX));
+            (aopInReg (left->aop, i + 1, H_IDX) && aopInReg (right->aop, i + 1, D_IDX) || aopInReg (left->aop, i + 1, D_IDX) && aopInReg (right->aop, i + 1, H_IDX));
 
-          const bool this_byte = this_byte_l || this_byte_h;
-          const bool next_byte = next_byte_l || next_byte_h;
+          const bool this_byte_hl = this_byte_l || this_byte_h;
+          const bool next_byte_hl = next_byte_l || next_byte_h;
 
-          const bool next_byte_unused = !bitVectBitValue (ic->rMask, this_byte_l ? H_IDX : L_IDX);
+          const int next_byte_hl_idx = this_byte_l ? H_IDX : L_IDX;
+          const bool next_byte_hl_unused = isRegDead (next_byte_hl_idx, ic) &&
+            left->aop->regs[next_byte_hl_idx] <= i && right->aop->regs[next_byte_hl_idx] <= i &&
+            (result->aop->regs[next_byte_hl_idx] < 0 || result->aop->regs[next_byte_hl_idx] >= i);
 
-          if (this_byte && (next_byte || next_byte_unused))
+          if (this_byte_hl && (next_byte_hl || next_byte_hl_unused))
             {
               emit2 ("or hl, de");
               regalloc_dry_run_cost++;
-              i += (1 + next_byte);
+              i += (1 + next_byte_hl);
+              continue;
+            }
+            
+          if (aopInReg (result->aop, i, IY_IDX) &&
+           (aopInReg (left->aop, i, IY_IDX) && aopInReg (right->aop, i, DE_IDX) || aopInReg (left->aop, i, DE_IDX) && aopInReg (right->aop, i, IY_IDX)))
+            {
+              emit2 ("or iy, de");
+              regalloc_dry_run_cost += 2;
+              i += 2;
+              continue;
+            }
+          else if (aopInReg (right->aop, i, DE_IDX) &&
+            (left->aop->type == AOP_STK || left->aop->type == AOP_DIR || left->aop->type == AOP_IY) &&
+            (aopInReg (result->aop, i, HL_IDX) || isPairDead(PAIR_HL, ic) && right->aop->regs[L_IDX] < i + 2 && right->aop->regs[H_IDX] < i + 2 && (result->aop->type == AOP_DIR || result->aop->type == AOP_IY || result->aop->type == AOP_STK)))
+            {
+              fetchPairLong (PAIR_HL, left->aop, ic, i);
+              emit2 ("or hl, de");
+              regalloc_dry_run_cost++;
+              genMove_o (result->aop, i, ASMOP_HL, 0, 2, a_free, true, false, true, true);
+              i += 2;
               continue;
             }
         }
@@ -8820,14 +10655,41 @@
           a_free = true;
         }
 
-      if (aopInReg (right->aop, i, A_IDX))
-        emit3_o (A_OR, ASMOP_A, 0, left->aop, i);
+      if (aopInReg (right->aop, i, A_IDX) || right->aop->type == AOP_SFR ||
+        !IS_EZ80_Z80 && !IS_Z80N && (aopInReg (right->aop, i, IYL_IDX) || aopInReg (right->aop, i, IYH_IDX)))
+        {
+          cheapMove (ASMOP_A, 0, right->aop, i, true);
+
+          if (requiresHL (left->aop) && left->aop->type != AOP_REG && !hl_free)
+            _push (PAIR_HL);
+          if (left->aop->type == AOP_SFR || aopInReg (right->aop, i, A_IDX) || aopInReg (right->aop, i, IYL_IDX) || aopInReg (right->aop, i, IYH_IDX))
+            UNIMPLEMENTED;
+          else
+            emit3_o (A_OR, ASMOP_A, 0, left->aop, i);
+          if (requiresHL (left->aop) && left->aop->type != AOP_REG && !hl_free)
+            _pop (PAIR_HL);
+        }
       else
         {
+          if (requiresHL (left->aop) && left->aop->type != AOP_REG && !hl_free)
+            _push (PAIR_HL);
           cheapMove (ASMOP_A, 0, left->aop, i, true);
-          emit3_o (A_OR, ASMOP_A, 0, right->aop, i);
-        }
-      cheapMove (result->aop, i, ASMOP_A, 0, true);
+          if (requiresHL (left->aop) && left->aop->type != AOP_REG && !hl_free)
+            _pop (PAIR_HL);
+
+          if (requiresHL (right->aop) && right->aop->type != AOP_REG && !hl_free)
+            _push (PAIR_HL);
+          emit3_o (A_OR, ASMOP_A, 0, right->aop, i);
+          if (requiresHL (right->aop) && right->aop->type != AOP_REG && !hl_free)
+            _pop (PAIR_HL);
+        }
+
+      hl_free = isPairDead (PAIR_HL, ic) &&
+        (left->aop->regs[L_IDX] <= i && left->aop->regs[H_IDX] <= i && right->aop->regs[L_IDX] <= i && right->aop->regs[H_IDX] <= i) &&
+        (result->aop->regs[L_IDX] < 0 || result->aop->regs[L_IDX] >= i) && (result->aop->regs[H_IDX] < 0 || result->aop->regs[H_IDX] >= i);
+
+      genMove_o (result->aop, i, ASMOP_A, 0, 1, true, hl_free, !isPairInUse (PAIR_DE, ic), true, true);
+        
       if (aopInReg (result->aop, i, A_IDX))
         a_free = false;
       i++;
@@ -8837,72 +10699,62 @@
     _pop (PAIR_AF);
 
 release:
-  freeAsmop (left, NULL);
-  freeAsmop (right, NULL);
-  freeAsmop (result, NULL);
+  freeAsmop (IC_LEFT (ic), NULL);
+  freeAsmop (IC_RIGHT (ic), NULL);
+  freeAsmop (IC_RESULT (ic), NULL);
 }
 
 /*-----------------------------------------------------------------*/
-/* genXor - code for xclusive or                                   */
+/* genEor - code for xclusive or                                   */
 /*-----------------------------------------------------------------*/
 static void
-genXor (const iCode *ic, iCode *ifx)
+genEor (const iCode *ic, iCode *ifx, asmop *result_aop, asmop *left_aop, asmop *right_aop)
 {
-  operand *left, *right, *result;
-  int size, offset = 0;
-  unsigned long long lit = 0;
+  int size;
   bool pushed_a = false;
 
-  aopOp ((left = IC_LEFT (ic)), ic, FALSE, FALSE);
-  aopOp ((right = IC_RIGHT (ic)), ic, FALSE, FALSE);
-  aopOp ((result = IC_RESULT (ic)), ic, TRUE, FALSE);
-
-  bool a_free = !bitVectBitValue (ic->rSurv, A_IDX) && left->aop->regs[A_IDX] <= 0 && right->aop->regs[A_IDX] <= 0;
+  bool a_free = isRegDead (A_IDX, ic) && left_aop->regs[A_IDX] <= 0 && right_aop->regs[A_IDX] <= 0;
 
   /* if left is a literal & right is not then exchange them */
-  if ((AOP_TYPE (left) == AOP_LIT && AOP_TYPE (right) != AOP_LIT) || (AOP_NEEDSACC (right) && !AOP_NEEDSACC (left)))
+  if ((left_aop->type == AOP_LIT && right_aop->type != AOP_LIT) || ((right_aop->type == AOP_SFR || right_aop->type == AOP_CRY) && !(left_aop->type == AOP_SFR || left_aop->type == AOP_CRY)))
     {
-      operand *tmp = right;
-      right = left;
-      left = tmp;
+      asmop *taop = right_aop;
+      right_aop = left_aop;
+      left_aop = taop;
     }
 
   /* if result = right then exchange them */
-  if (sameRegs (result->aop, AOP (right)) && !AOP_NEEDSACC (left))
+  if (sameRegs (result_aop, right_aop) && !(left_aop->type == AOP_SFR || left_aop->type == AOP_CRY))
     {
-      operand *tmp = right;
-      right = left;
-      left = tmp;
+      asmop *taop = right_aop;
+      right_aop = left_aop;
+      left_aop = taop;
     }
 
-  if (AOP_TYPE (right) == AOP_LIT)
-    lit = ullFromVal (AOP (right)->aopu.aop_lit);
-
-  size = AOP_SIZE (result);
+  size = result_aop->size;
 
-  if (AOP_TYPE (left) == AOP_CRY)
+  if (left_aop->type == AOP_CRY)
     {
       wassertl (0, "Tried to XOR a bit");
-      goto release;
+      return;
     }
 
   /* Make sure A is on the left to not overwrite it. */
-  if (aopInReg (right->aop, 0, A_IDX))
+  if (aopInReg (right_aop, 0, A_IDX))
     {
-      wassert (!AOP_NEEDSACC (left));
-      operand *tmp = right;
-      right = left;
-      left = tmp;
+      wassert (!(left_aop->type == AOP_SFR || left_aop->type == AOP_CRY));
+      asmop *taop = right_aop;
+      right_aop = left_aop;
+      left_aop = taop;
     }
 
   // if(val & 0xZZ)       - size = 0, ifx != FALSE  -
   // bit = val & 0xZZ     - size = 1, ifx = FALSE -
-  if ((AOP_TYPE (right) == AOP_LIT) && (AOP_TYPE (result) == AOP_CRY) && (AOP_TYPE (left) != AOP_CRY))
+  if ((right_aop->type == AOP_LIT) && (result_aop->type == AOP_CRY) && (left_aop->type != AOP_CRY))
     {
       symbol *tlbl = regalloc_dry_run ? 0 : newiTempLabel (0);
-      int sizel;
-
-      sizel = AOP_SIZE (left);
+      int offset = 0;
+      int sizel = left_aop->size;
 
       if (size)
         {
@@ -8911,7 +10763,7 @@
         }
       while (sizel--)
         {
-          if (!bitVectBitValue (ic->rSurv, A_IDX) && left->aop->regs[A_IDX] <= offset && right->aop->regs[A_IDX] <= offset && (result->aop->regs[A_IDX] < 0 || result->aop->regs[A_IDX] >= offset))
+          if (isRegDead (A_IDX, ic) && left_aop->regs[A_IDX] <= offset && right_aop->regs[A_IDX] <= offset && (result_aop->regs[A_IDX] < 0 || result_aop->regs[A_IDX] >= offset))
             a_free = true;
 
           if (!a_free)
@@ -8920,27 +10772,24 @@
               _push (PAIR_AF);
               a_free = true;
               pushed_a = true;
-              if (ifx) // The pop at the end is hard to eal with in case of ifx.
-                {
-                  regalloc_dry_run_cost += 100;
-                  wassert (regalloc_dry_run);
-                }
+              if (ifx) // The pop at the end is hard to deal with in case of ifx.
+                UNIMPLEMENTED;
             }
-          else if (pushed_a && (aopInReg (left->aop, offset, A_IDX) || aopInReg (right->aop, offset, A_IDX)))
+          else if (pushed_a && (aopInReg (left_aop, offset, A_IDX) || aopInReg (right_aop, offset, A_IDX)))
             {
               _pop (PAIR_AF);
-              if (bitVectBitValue (ic->rSurv, A_IDX))
+              if (!isRegDead (A_IDX, ic))
                 _push (PAIR_AF);
               else
                 pushed_a = false;
             }
 
-          if (aopInReg (right->aop, offset, A_IDX))
-            emit3_o (A_XOR, ASMOP_A, 0, left->aop, offset);
+          if (aopInReg (right_aop, offset, A_IDX))
+            emit3_o (A_XOR, ASMOP_A, 0, left_aop, offset);
           else
             {
-              cheapMove (ASMOP_A, 0, left->aop, offset, true);
-              emit3_o (A_XOR, ASMOP_A, 0, right->aop, offset);
+              cheapMove (ASMOP_A, 0, left_aop, offset, true);
+              emit3_o (A_XOR, ASMOP_A, 0, right_aop, offset);
             }
           if (ifx)              /* emit jmp only, if it is actually used * */
             if (!regalloc_dry_run)
@@ -8949,7 +10798,10 @@
           offset++;
         }
       if (pushed_a)
-        _pop (PAIR_AF);
+        {
+          _pop (PAIR_AF);
+          pushed_a = false;
+        }
       if (ifx)
         {
           jmpTrueOrFalse (ifx, tlbl);
@@ -8958,124 +10810,426 @@
         {
           wassertl (0, "Result of XOR was destined for a bit");
         }
-      goto release;
+      return;
     }
 
     // left & result in different registers
-    if (AOP_TYPE (result) == AOP_CRY)
+    if (result_aop->type == AOP_CRY)
       {
         wassertl (0, "Result of XOR is in a bit");
+        return;
       }
-    else
-      for (; (size--); offset++)
-        {
-          if (!bitVectBitValue (ic->rSurv, A_IDX) && left->aop->regs[A_IDX] <= offset && right->aop->regs[A_IDX] <= offset && (result->aop->regs[A_IDX] < 0 || result->aop->regs[A_IDX] >= offset))
-            a_free = true;
 
-          if (pushed_a && (aopInReg (left->aop, offset, A_IDX) || aopInReg (right->aop, offset, A_IDX)))
-            {
-              _pop (PAIR_AF);
-              if (bitVectBitValue (ic->rSurv, A_IDX))
-                _push (PAIR_AF);
-              else
-                pushed_a = false;
-            }
+    for (int i = 0; i < size;)
+      {
+        bool hl_free = isPairDead (PAIR_HL, ic) &&
+          (left_aop->regs[L_IDX] < i && left_aop->regs[H_IDX] < i && right_aop->regs[L_IDX] < i && right_aop->regs[H_IDX] < i) &&
+          (result_aop->regs[L_IDX] < 0 || result_aop->regs[L_IDX] >= i) && (result_aop->regs[H_IDX] < 0 || result_aop->regs[H_IDX] >= i);
 
-          // normal case
-          // result = left & right
-          if (right->aop->type == AOP_LIT)
-            {
-              if (((lit >> (offset * 8)) & 0x0FFL) == 0x00L)
-                {
-                  cheapMove (result->aop, offset, left->aop, offset, a_free);
-                  if (aopInReg (result->aop, offset, A_IDX))
-                    a_free = false;
-                  continue;
-                }
-            }
-          // faster than result <- left, anl result,right
-          // and better if result is SFR
-          if (!a_free)
-            {
-              wassert (!pushed_a);
+        if (isRegDead (A_IDX, ic) && left_aop->regs[A_IDX] <= i && right_aop->regs[A_IDX] <= i && (result_aop->regs[A_IDX] < 0 || result_aop->regs[A_IDX] >= i))
+          a_free = true;
+
+        if (pushed_a && (aopInReg (left_aop, i, A_IDX) || aopInReg (right_aop, i, A_IDX)))
+          {
+            if (result_aop->regs[A_IDX] >= 0 && result_aop->regs[A_IDX] < i)
+              UNIMPLEMENTED;
+            _pop (PAIR_AF);
+            if (!isRegDead (A_IDX, ic))
               _push (PAIR_AF);
-              a_free = true;
-              pushed_a = true;
-            }
+            else
+              pushed_a = false;
+          }
+            
+        // normal case
+        // result = left ^ right
+        if (right_aop->type == AOP_LIT)
+          {
+            unsigned int bytelit = byteOfVal (right_aop->aopu.aop_lit, i);
+
+            if (bytelit == 0x00)
+              {
+                int end;
+                for(end = i; end < size && byteOfVal (right_aop->aopu.aop_lit, end) == bytelit; end++);
+                genMove_o (result_aop, i, left_aop, i, end - i, a_free, hl_free, !isPairInUse (PAIR_DE, ic), true, true);
+                if(result_aop->type == AOP_REG &&
+                  (left_aop->regs[result_aop->aopu.aop_reg[i]->rIdx] >= end || right_aop->regs[result_aop->aopu.aop_reg[i]->rIdx] >= end))
+                  {
+                    wassert(regalloc_dry_run);
+                    regalloc_dry_run_cost += 500;
+                  }
+                if (result_aop->regs[A_IDX] >= i && result_aop->regs[A_IDX] < end)
+                  a_free = false;
+                i = end;
+                continue;
+              }
+            else if (IS_TLCS90 &&
+              (aopInReg (left_aop, i, HL_IDX) && aopInReg (result_aop, i, HL_IDX) || aopInReg (left_aop, i, H_IDX) && aopInReg (left_aop, i + 1, L_IDX) && aopInReg (result_aop, i, H_IDX) && aopInReg (result_aop, i + 1, L_IDX)))
+              {
+                unsigned short mask = aopInReg (result_aop, i, L_IDX) ? (bytelit + (byteOfVal (right_aop->aopu.aop_lit, i + 1) << 8)) : (byteOfVal (right_aop->aopu.aop_lit, i + 1) + (bytelit << 8));
+                emit2 ("xor hl, !immedword", mask);
+                regalloc_dry_run_cost += 3;
+                i += 2;
+                continue;
+              }
+            else if (IS_RAB && bytelit == 0x01 &&
+              (aopInReg (left_aop, i, L_IDX) && aopInReg (result_aop, i, L_IDX) || aopInReg (left_aop, i, E_IDX) && aopInReg (result_aop, i, E_IDX)))
+              {
+                bool de = aopInReg (result_aop, i, E_IDX);
+                emit2 (de ? "rr de" : "rr hl");
+                emit2 ("ccf");
+                emit2 (de ? "rl de" : "adc hl, hl");
+                regalloc_dry_run_cost += 4 - de;
+                i++;
+                continue;
+              }
+            else if (IS_RAB && bytelit == 0x80 &&
+              (aopInReg (left_aop, i, H_IDX) && aopInReg (result_aop, i, H_IDX) || aopInReg (left_aop, i, D_IDX) && aopInReg (result_aop, i, D_IDX)))
+              {
+                bool de = aopInReg (result_aop, i, D_IDX);
+                emit2 (de ? "rl de" : "add hl, hl");
+                emit2 ("ccf");
+                emit2 (de ? "rr de" : "rr hl");
+                regalloc_dry_run_cost += 3;
+                i++;
+                continue;
+              }
+          }
+        // faster than result <- left, anl result,right
+        // and better if result is SFR
+        if (!a_free)
+          {
+            if (pushed_a)
+              {
+                wassert(regalloc_dry_run);
+                regalloc_dry_run_cost += 500;
+              }
+            else
+              _push (PAIR_AF);
+            a_free = true;
+            pushed_a = true;
+          }
+
+        if (aopInReg (right_aop, i, A_IDX) && left_aop->type != AOP_STL)
+          {
+            if (requiresHL (left_aop) && left_aop->type != AOP_REG && !hl_free)
+              _push (PAIR_HL);
+            emit3_o (A_XOR, ASMOP_A, 0, left_aop, i);
+            if (requiresHL (left_aop) && left_aop->type != AOP_REG && !hl_free)
+              _pop (PAIR_HL);
+          }
+        else if (right_aop->type == AOP_STL)
+          UNIMPLEMENTED;
+        else
+          {
+            if (requiresHL (left_aop) && left_aop->type != AOP_REG && !hl_free)
+               _push (PAIR_HL);
+            cheapMove (ASMOP_A, 0, left_aop, i, true);
+            if (requiresHL (left_aop) && left_aop->type != AOP_REG && !hl_free)
+               _pop (PAIR_HL);
+            if (right_aop->type == AOP_LIT && byteOfVal (right_aop->aopu.aop_lit, i) == 0xff)
+              emit3 (A_CPL, 0, 0);
+            else
+              {
+                if (requiresHL (right_aop) && right_aop->type != AOP_REG && !hl_free)
+                  _push (PAIR_HL);
+                emit3_o (A_XOR, ASMOP_A, 0, right_aop, i);
+                if (requiresHL (right_aop) && right_aop->type != AOP_REG && !hl_free)
+                  _pop (PAIR_HL);
+              }
+          }
+          
+        hl_free = isPairDead (PAIR_HL, ic) &&
+          (left_aop->regs[L_IDX] <= i && left_aop->regs[H_IDX] <= i && right_aop->regs[L_IDX] <= i && right_aop->regs[H_IDX] <= i) &&
+          (result_aop->regs[L_IDX] < 0 || result_aop->regs[L_IDX] >= i) && (result_aop->regs[H_IDX] < 0 || result_aop->regs[H_IDX] >= i);
+
+        genMove_o (result_aop, i, ASMOP_A, 0, 1, true, hl_free, !isPairInUse (PAIR_DE, ic), true, true);
+
+        if(result_aop->type == AOP_REG &&
+          (left_aop->regs[result_aop->aopu.aop_reg[i]->rIdx] > i || right_aop->regs[result_aop->aopu.aop_reg[i]->rIdx] > i))
+          {
+            wassert(regalloc_dry_run);
+            regalloc_dry_run_cost += 500;
+          }
+        if (aopInReg (result_aop, i, A_IDX))
+          a_free = false;
+
+        i++;
+     }
 
-          if (aopInReg (right->aop, offset, A_IDX))
-            emit3_o (A_XOR, ASMOP_A, 0, left->aop, offset);
-          else
-            {
-              cheapMove (ASMOP_A, 0, left->aop, offset, true);
-              if (right->aop->type == AOP_LIT && ((lit >> (offset * 8)) & 0xff) == 0xff)
-                emit3 (A_CPL, 0, 0);
-              else
-                emit3_o (A_XOR, ASMOP_A, 0, right->aop, offset);
-            }
-          cheapMove (result->aop, offset, ASMOP_A, 0, true);
-          if (aopInReg (result->aop, offset, A_IDX))
-            a_free = false;
-        }
   if (pushed_a)
      _pop (PAIR_AF);
+}
 
-release:
-  freeAsmop (left, NULL);
-  freeAsmop (right, NULL);
-  freeAsmop (result, NULL);
+/*-----------------------------------------------------------------*/
+/* genXor - code for exclusive or                                   */
+/*-----------------------------------------------------------------*/
+static void
+genXor (const iCode *ic, iCode *ifx)
+{
+  aopOp (IC_LEFT (ic), ic, false, false);
+  aopOp (IC_RIGHT (ic), ic, false, false);
+  aopOp (IC_RESULT (ic), ic, true, false);
+  
+  genEor (ic, ifx, IC_RESULT (ic)->aop, IC_LEFT (ic)->aop, IC_RIGHT (ic)->aop);
+  
+  freeAsmop (IC_LEFT (ic), NULL);
+  freeAsmop (IC_RIGHT (ic), NULL);
+  freeAsmop (IC_RESULT (ic), NULL);
 }
 
 /*-----------------------------------------------------------------*/
-/* genRRC - rotate right with carry                                */
+/* genCpl - generate code for complement                           */
 /*-----------------------------------------------------------------*/
 static void
-genRRC (const iCode * ic)
+genCpl (const iCode *ic)
 {
-  wassert (0);
+  /* assign asmOps to operand & result */
+  aopOp (IC_LEFT (ic), ic, false, false);
+  aopOp (IC_RESULT (ic), ic, true, false);
+
+  genEor (ic, 0, IC_RESULT (ic)->aop, IC_LEFT (ic)->aop, ASMOP_MONE);
+
+  /* release the aops */
+  freeAsmop (IC_LEFT (ic), 0);
+  freeAsmop (IC_RESULT (ic), 0);
 }
 
 /*-----------------------------------------------------------------*/
-/* genRLC - generate code for rotate left with carry               */
+/* genRRC - rotate right with carry                                */
 /*-----------------------------------------------------------------*/
 static void
-genRLC (const iCode * ic)
+genRRC (const iCode * ic)
 {
-  wassert (0);
+  operand *left, *result;
+  bool pushed_a = false;
+  /* rotate right with carry */
+  aopOp (IC_LEFT (ic), ic, FALSE, FALSE);
+  aopOp (IC_RESULT (ic), ic, TRUE, FALSE);
+  
+  left = IC_LEFT (ic);
+  result = IC_RESULT (ic);
+
+  if (pushed_a)
+    _push (PAIR_AF);
+
+  int size = result->aop->size;
+  int offset = size - 1;
+
+  if (size == 1)
+    {
+      asmop *rotaop = ASMOP_A;
+      if (result->aop->type == AOP_REG && !aopInReg (result->aop, 0, IYL_IDX) && !aopInReg (result->aop, 0, IYH_IDX) && !aopInReg (left->aop, 0, A_IDX) ||
+        result->aop->type == AOP_STK && aopSame (result->aop, 0, left->aop, 0, 1))
+        rotaop = result->aop;
+
+      if (aopInReg (rotaop, 0, A_IDX) && !isRegDead (A_IDX, ic))
+      {
+        _push (PAIR_AF);
+        pushed_a = true;
+      }
+ 
+      cheapMove (rotaop, 0, left->aop, 0, isRegDead (A_IDX, ic) || pushed_a);
+      emit3 (aopInReg (rotaop, 0, A_IDX) ? A_RRCA : A_RRC, aopInReg (rotaop, 0, A_IDX) ? 0 : rotaop, 0);
+      cheapMove (result->aop, 0, rotaop, 0, isRegDead (A_IDX, ic) || pushed_a);
+    }
+  else if (left->aop->type == AOP_REG || result->aop->type == AOP_STK ||
+           result->aop->type == AOP_HL || result->aop->type == AOP_IY ||
+           result->aop->type == AOP_EXSTK || result->aop->type == AOP_REG)
+    {
+      if (!isRegDead (A_IDX, ic))
+      {
+        _push (PAIR_AF);
+        pushed_a = true;
+      }
+      if (left->aop->type != AOP_REG && !operandsEqu (result, left))
+        {
+          /* always prefer register operations */
+          genMove_o (result->aop, 0, left->aop, 0, size, true, isPairDead (PAIR_HL, ic), isPairDead (PAIR_DE, ic), true, true);
+          left = result;
+        }
+      _moveA (aopGet (left->aop, offset, false));
+      emit3_o (A_RRA, 0, 0, 0, 0);
+      while (--offset >= 0)
+        emit3_o (A_RR, left->aop, offset, 0, 0);
+      if (IS_SM83 && requiresHL (left->aop))
+        { /* ldhl sp,N changes CARRY */
+          emit3_o (A_RRA, 0, 0, 0, 0);
+          aopGet (left->aop, size - 1, false);
+          emit3_o (A_RLA, 0, 0, 0, 0);
+        }
+      emit3_o (A_RR, left->aop, size - 1, 0, 0);
+      if (!operandsEqu (result, left))
+        genMove_o (result->aop, 0, left->aop, 0, size, true, isPairDead (PAIR_HL, ic), isPairDead (PAIR_DE, ic), true, true);
+    }
+  else
+    {
+      if (!isRegDead (A_IDX, ic))
+      {
+        _push (PAIR_AF);
+        pushed_a = true;
+      }
+      while (offset >= 0)
+        {
+          _moveA (aopGet (left->aop, offset, false));
+          emit3_o (A_RRA, 0, 0, 0, 0);
+          if (offset != size - 1)
+            aopPut (result->aop, "a", offset);
+          --offset;
+        }
+      _moveA (aopGet (left->aop, size - 1, false));
+      emit3_o (A_RRA, 0, 0, 0, 0);
+      aopPut (result->aop, "a", size - 1);
+    }
+  if (pushed_a)
+    _pop (PAIR_AF);
+
+  freeAsmop (IC_LEFT (ic), 0);
+  freeAsmop (IC_RESULT (ic), 0);
 }
 
 /*-----------------------------------------------------------------*/
-/* genGetHbit - generates code get highest order bit               */
+/* genRLC - generate code for rotate left with carry               */
 /*-----------------------------------------------------------------*/
 static void
-genGetHbit (const iCode * ic)
+genRLC (const iCode * ic)
 {
   operand *left, *result;
+  bool pushed_a = false;
+  /* rotate left with carry */
+  aopOp (IC_LEFT (ic), ic, FALSE, FALSE);
+  aopOp (IC_RESULT (ic), ic, TRUE, FALSE);
+  
   left = IC_LEFT (ic);
   result = IC_RESULT (ic);
 
-  aopOp (left, ic, FALSE, FALSE);
-  aopOp (result, ic, FALSE, FALSE);
+  int size = result->aop->size;
 
-  /* get the highest order byte into a */
-  cheapMove (ASMOP_A, 0, left->aop, AOP_SIZE (left) - 1, true);
+  if (size == 1)
+    {
+      asmop *rotaop = ASMOP_A;
+      if (result->aop->type == AOP_REG && !aopInReg (result->aop, 0, IYL_IDX) && !aopInReg (result->aop, 0, IYH_IDX) && !aopInReg (left->aop, 0, A_IDX) ||
+        result->aop->type == AOP_STK && aopSame (result->aop, 0, left->aop, 0, 1))
+        rotaop = result->aop;
 
-  if (AOP_TYPE (result) == AOP_CRY)
+      if (aopInReg (rotaop, 0, A_IDX) && !isRegDead (A_IDX, ic))
+      {
+        _push (PAIR_AF);
+        pushed_a = true;
+      }
+ 
+      cheapMove (rotaop, 0, left->aop, 0, isRegDead (A_IDX, ic) || pushed_a);
+      emit3 (aopInReg (rotaop, 0, A_IDX) ? A_RLCA : A_RLC, aopInReg (rotaop, 0, A_IDX) ? 0 : rotaop, 0);
+      cheapMove (result->aop, 0, rotaop, 0, isRegDead (A_IDX, ic) || pushed_a);
+    }
+  else if (IS_Z80N && size == 2 && aopInReg (result->aop, 0, DE_IDX) && isRegDead (B_IDX, ic))
+    {
+      genMove (ASMOP_DE, left->aop, isRegDead (A_IDX, ic), isRegDead (HL_IDX, ic), true, true);
+      emit2 ("ld b, !immedbyte", 1);
+      emit2 ("brlc de, b");
+      regalloc_dry_run_cost += 4;
+    }
+  else if (left->aop->type == AOP_REG || result->aop->type == AOP_STK ||
+           result->aop->type == AOP_HL || result->aop->type == AOP_IY ||
+           result->aop->type == AOP_EXSTK || result->aop->type == AOP_REG)
     {
-      emit3 (A_RL, ASMOP_A, 0);
-      outBitC (result);
+      if (!isRegDead (A_IDX, ic))
+      {
+        _push (PAIR_AF);
+        pushed_a = true;
+      }
+      if (left->aop->type != AOP_REG && !operandsEqu (result, left))
+        {
+          /* always prefer register operations */
+          genMove_o (result->aop, 0, left->aop, 0, size, true, isPairDead (PAIR_HL, ic), isPairDead (PAIR_DE, ic), true, true);
+          left = result;
+        }
+      _moveA (aopGet (left->aop, 0, false));
+      emit3_o (A_RLA, 0, 0, 0, 0);
+      for (int offset = 1; offset < size; ++offset)
+        emit3_o (A_RL, left->aop, offset, 0, 0);
+      if (IS_SM83 && requiresHL (left->aop))
+        { /* ldhl sp,N changes CARRY */
+          emit3_o (A_RRA, 0, 0, 0, 0);
+          aopGet (left->aop, 0, false);
+          emit3_o (A_RLA, 0, 0, 0, 0);
+        }
+      emit3_o (A_RL, left->aop, 0, 0, 0);
+      if (!operandsEqu (result, left))
+        genMove_o (result->aop, 0, left->aop, 0, size, true, isPairDead (PAIR_HL, ic), isPairDead (PAIR_DE, ic), true, true);
     }
   else
     {
-      emit3 (A_RLC, ASMOP_A, 0);
-      emit2 ("and a, !one");
-      regalloc_dry_run_cost += 2;
-      outAcc (result);
+      if (!isRegDead (A_IDX, ic))
+      {
+        _push (PAIR_AF);
+        pushed_a = true;
+      }
+
+      for (int offset = 0; offset < size; ++offset)
+        {
+          _moveA (aopGet (left->aop, offset, false));
+          emit3_o (A_RLA, 0, 0, 0, 0);
+          if (offset != 0)
+            aopPut (result->aop, "a", offset);
+        }
+      _moveA (aopGet (left->aop, 0, false));
+      emit3_o (A_RLA, 0, 0, 0, 0);
+      aopPut (result->aop, "a", 0);
     }
 
+  if (pushed_a)
+    _pop (PAIR_AF);
 
+  freeAsmop (IC_LEFT (ic), 0);
+  freeAsmop (IC_RESULT (ic), 0);
+}
+
+/*-----------------------------------------------------------------*/
+/* genGetByte - generates code to get a single byte                */
+/*-----------------------------------------------------------------*/
+static void
+genGetByte (const iCode *ic)
+{
+  operand *left, *right, *result;
+  int offset;
+
+  left = IC_LEFT (ic);
+  right = IC_RIGHT (ic);
+  result = IC_RESULT (ic);
+  aopOp (left, ic, FALSE, FALSE);
+  aopOp (right, ic, FALSE, FALSE);
+  aopOp (result, ic, TRUE, FALSE);
+
+  offset = (int) ulFromVal (right->aop->aopu.aop_lit) / 8;
+  genMove_o (result->aop, 0, left->aop, offset, 1, isRegDead (A_IDX, ic), isPairDead (PAIR_HL, ic), isPairDead (PAIR_DE, ic), true, true);
+
+  freeAsmop (result, NULL);
+  freeAsmop (right, NULL);
   freeAsmop (left, NULL);
+}
+
+/*-----------------------------------------------------------------*/
+/* genGetWord - generates code to get a 16-bit word                */
+/*-----------------------------------------------------------------*/
+static void
+genGetWord (const iCode *ic)
+{
+  operand *left, *right, *result;
+  int offset;
+
+  left = IC_LEFT (ic);
+  right = IC_RIGHT (ic);
+  result = IC_RESULT (ic);
+  aopOp (left, ic, FALSE, FALSE);
+  aopOp (right, ic, FALSE, FALSE);
+  aopOp (result, ic, TRUE, FALSE);
+
+  offset = (int) ulFromVal (right->aop->aopu.aop_lit) / 8;
+  genMove_o (result->aop, 0, left->aop, offset, 2, isRegDead (A_IDX, ic), isPairDead (PAIR_HL, ic), isPairDead (PAIR_DE, ic), true, true);
+
   freeAsmop (result, NULL);
+  freeAsmop (right, NULL);
+  freeAsmop (left, NULL);
 }
 
 /*-----------------------------------------------------------------*/
@@ -9084,7 +11238,53 @@
 static void
 genGetAbit (const iCode * ic)
 {
-  wassert (0);
+  operand *left, *right, *result;
+  int shCount;
+
+  left = IC_LEFT (ic);
+  right = IC_RIGHT (ic);
+  result = IC_RESULT (ic);
+  aopOp (left, ic, FALSE, FALSE);
+  aopOp (right, ic, FALSE, FALSE);
+  aopOp (result, ic, TRUE, FALSE);
+
+  shCount = (int) ulFromVal (right->aop->aopu.aop_lit);
+
+  /* get the needed byte into a */
+  cheapMove (ASMOP_A, 0, left->aop, shCount / 8, true);
+  shCount %= 8;
+  if (shCount == 4 && (IS_SM83 || IS_Z80N))
+    {
+      emit3_o (A_SWAP, ASMOP_A, 0, 0, 0);
+      shCount -= 4;
+    }
+  if (result->aop->type == AOP_CRY)
+    {
+      
+      if (shCount < 4)
+        while (shCount-- >= 0)
+          emit3_o (A_RRCA, 0, 0, 0, 0);
+      else
+        while (shCount++ < 8)
+          emit3_o (A_RLCA, 0, 0, 0, 0);
+      outBitC (result);
+    }
+  else
+    {
+      if (shCount < 5)
+        while (shCount-- > 0)
+          emit3_o (A_RRCA, 0, 0, 0, 0);
+      else
+        while (shCount++ < 8)
+          emit3_o (A_RLCA, 0, 0, 0, 0);
+      emit2 ("and a, !immedbyte", 0x01);
+      regalloc_dry_run_cost++;
+      outAcc (result);
+    }
+
+  freeAsmop (result, NULL);
+  freeAsmop (right, NULL);
+  freeAsmop (left, NULL);
 }
 
 static void
@@ -9112,10 +11312,10 @@
   symbol *tlbl;
 
   if (IS_RAB && !is_signed && shCount < 4 &&
-    (getPairId (AOP (result)) == PAIR_HL || getPairId (AOP (result)) == PAIR_DE))
+    (getPairId (result->aop) == PAIR_HL || getPairId (result->aop) == PAIR_DE))
     {
-      bool op_de = (getPairId (AOP (result)) == PAIR_DE);
-      fetchPairLong (getPairId (AOP (result)), AOP(left), ic, offl);
+      bool op_de = (getPairId (result->aop) == PAIR_DE);
+      fetchPairLong (getPairId (result->aop), left->aop, ic, offl);
       while (shCount--)
         {
           emit3 (A_CP, ASMOP_A, ASMOP_A);
@@ -9124,17 +11324,40 @@
         }
       return;
     }
+  else if (!IS_SM83 && !IS_RAB && !is_signed && aopSame (result->aop, offr, left->aop, offl, 2) && isPairDead (PAIR_HL, ic) && isRegDead (A_IDX, ic) &&
+    (shCount == 4 || shCount == 5) &&
+    (result->aop->type == AOP_DIR || result->aop->type == AOP_HL || result->aop->type == AOP_IY))
+    {
+      emit2 ("xor a, a");
+      emit2 ("ld hl, !hashedstr+1", result->aop->aopu.aop_dir);
+      regalloc_dry_run_cost += 4;
+      emit3 (A_RRD, 0, 0);
+      if (shCount == 5)
+        {
+          emit2 ("srl (hl)");
+          regalloc_dry_run_cost++;
+        }
+      emit2 ("dec hl");
+      regalloc_dry_run_cost++;
+      emit3 (A_RRD, 0, 0);
+      if (shCount == 5)
+        {
+          emit2 ("rr (hl)");
+          regalloc_dry_run_cost++;
+        }
+      return;
+    }
   else if (IS_RAB && !is_signed && shCount >= 2 && isPairDead (PAIR_HL, ic) &&
-      ((isPair (AOP (left)) && getPairId (AOP (left)) == PAIR_HL || isPair (AOP (result))
-        && getPairId (AOP (result)) == PAIR_HL) && isPairDead (PAIR_DE, ic) || isPair (AOP (left))
-       && getPairId (AOP (left)) == PAIR_DE))
+      ((isPair (left->aop) && getPairId (left->aop) == PAIR_HL || isPair (result->aop)
+        && getPairId (result->aop) == PAIR_HL) && isPairDead (PAIR_DE, ic) || isPair (left->aop)
+       && getPairId (left->aop) == PAIR_DE))
     {
-      bool op_de = (getPairId (AOP (left)) == PAIR_DE);
+      bool op_de = (getPairId (left->aop) == PAIR_DE);
       if (op_de)
         emit2 ("ld hl, !immedword", 0xffff >> shCount);
       else
         {
-          fetchPair (PAIR_HL, AOP (left));
+          fetchPair (PAIR_HL, left->aop);
           emit2 ("ld de, !immedword", 0xffff >> shCount);
         }
       regalloc_dry_run_cost += 3;
@@ -9145,19 +11368,19 @@
         }
       emit2 ("and hl, de");
       regalloc_dry_run_cost += 1;
-      commitPair (AOP (IC_RESULT (ic)), PAIR_HL, ic, TRUE);
+      genMove (IC_RESULT (ic)->aop, ASMOP_HL, true, true, isPairDead (PAIR_DE, ic), true);
       return;
     }
 
-  if (isPair (AOP (result)) && !offr)
-    fetchPairLong (getPairId (AOP (result)), AOP(left), ic, offl);
+  if (isPair (result->aop) && !offr)
+    fetchPairLong (getPairId (result->aop), left->aop, ic, offl);
   else
-    genMove_o (result->aop, offr, left->aop, offl, 2, true, isPairDead (PAIR_HL, ic));
+    genMove_o (result->aop, offr, left->aop, offl, 2, true, isPairDead (PAIR_HL, ic), isPairDead (PAIR_DE, ic), true, true);
 
   if (shCount == 0)
     return;
 
-  /*  if (AOP(result)->type == AOP_REG) { */
+  /*  if (result->aop->type == AOP_REG) { */
 
   /* Left is already in result - so now do the shift */
   /* Optimizing for speed by default. */
@@ -9165,16 +11388,19 @@
     {
       while (shCount--)
         {
-          emitRsh2 (AOP (result), size, is_signed);
+          emitRsh2 (result->aop, size, is_signed);
         }
     }
   else
     {
-      bool use_b = (!IS_GB && !bitVectBitValue (ic->rSurv, B_IDX)
-                    && !(AOP_TYPE (result) == AOP_REG
-                         && (AOP (result)->aopu.aop_reg[0]->rIdx == B_IDX || AOP (result)->aopu.aop_reg[1]->rIdx == B_IDX)));
+      bool use_b = (!IS_SM83 && isRegDead (B_IDX, ic)
+                    && !(result->aop->type == AOP_REG
+                         && (result->aop->aopu.aop_reg[0]->rIdx == B_IDX || result->aop->aopu.aop_reg[1]->rIdx == B_IDX)));
 
       tlbl = regalloc_dry_run ? 0 : newiTempLabel (NULL);
+      
+      if (requiresHL (result->aop))
+        spillPair (PAIR_HL);
 
       if (!regalloc_dry_run)
         {
@@ -9183,7 +11409,7 @@
         }
       regalloc_dry_run_cost += 2;
 
-      emitRsh2 (AOP (result), size, is_signed);
+      emitRsh2 (result->aop, size, is_signed);
 
       if (!regalloc_dry_run)
         {
@@ -9203,32 +11429,27 @@
 /* shiftL2Left2Result - shift left two bytes from left to result   */
 /*-----------------------------------------------------------------*/
 static void
-shiftL2Left2Result (operand *left, int offl, operand *result, int offr, int shCount, const iCode *ic)
+shiftL2Left2Result (operand *left, operand *result, int shCount, const iCode *ic)
 {
-  operand *shiftoperand = result;
-
-  if (sameRegs (AOP (result), AOP (left)) && ((offl + MSB16) == offr))
-    {
-      wassert (0);
-    }
+  asmop *shiftaop = result->aop;
 
   /* For a shift of 7 we can use cheaper right shifts */
-  else if (shCount == 7 && AOP_TYPE (left) == AOP_REG && !bitVectBitValue (ic->rSurv, AOP (left)->aopu.aop_reg[0]->rIdx) && AOP_TYPE (result) == AOP_REG &&
-    AOP (left)->aopu.aop_reg[0]->rIdx != IYL_IDX && AOP (left)->aopu.aop_reg[1]->rIdx != IYL_IDX && AOP (left)->aopu.aop_reg[0]->rIdx != IYH_IDX && AOP (left)->aopu.aop_reg[1]->rIdx != IYH_IDX &&
-    AOP (result)->aopu.aop_reg[0]->rIdx != IYL_IDX && AOP (result)->aopu.aop_reg[1]->rIdx != IYL_IDX && AOP (result)->aopu.aop_reg[0]->rIdx != IYH_IDX && AOP (result)->aopu.aop_reg[1]->rIdx != IYH_IDX &&
-    (optimize.codeSpeed || getPairId (AOP (result)) != PAIR_HL || getPairId (AOP (left)) != PAIR_HL)) /* but a sequence of add hl, hl might still be cheaper code-size wise */
+  if (shCount == 7 && left->aop->type == AOP_REG && !bitVectBitValue (ic->rSurv, left->aop->aopu.aop_reg[0]->rIdx) && result->aop->type == AOP_REG &&
+    left->aop->aopu.aop_reg[0]->rIdx != IYL_IDX && left->aop->aopu.aop_reg[1]->rIdx != IYL_IDX && left->aop->aopu.aop_reg[0]->rIdx != IYH_IDX && left->aop->aopu.aop_reg[1]->rIdx != IYH_IDX &&
+    result->aop->aopu.aop_reg[0]->rIdx != IYL_IDX && result->aop->aopu.aop_reg[1]->rIdx != IYL_IDX && result->aop->aopu.aop_reg[0]->rIdx != IYH_IDX && result->aop->aopu.aop_reg[1]->rIdx != IYH_IDX &&
+    (optimize.codeSpeed || getPairId (result->aop) != PAIR_HL || getPairId (left->aop) != PAIR_HL)) /* but a sequence of add hl, hl might still be cheaper code-size wise */
     {
       // Handling the low byte in A with xor clearing is cheaper.
-      bool special_a = (!bitVectBitValue (ic->rSurv, A_IDX) && !aopInReg (AOP (left), 0, A_IDX) && !aopInReg (AOP (left), 0, A_IDX));
-      asmop *lowbyte = special_a ? ASMOP_A : AOP (result);
+      bool special_a = (isRegDead (A_IDX, ic) && !aopInReg (left->aop, 0, A_IDX) && !aopInReg (left->aop, 0, A_IDX));
+      asmop *lowbyte = special_a ? ASMOP_A : result->aop;
 
       if (special_a)
         emit3 (A_XOR, ASMOP_A, ASMOP_A);
-      emit3_o (A_RR, AOP (left), 1, 0, 0);
-      emit3_o (A_LD, AOP (result), 1, AOP (left), 0);
-      emit3_o (A_RR, AOP (result), 1, 0, 0);
+      emit3_o (A_RR, left->aop, 1, 0, 0);
+      emit3_o (A_LD, result->aop, 1, left->aop, 0);
+      emit3_o (A_RR, result->aop, 1, 0, 0);
       if (!special_a)
-        emit3_o (A_LD, AOP (result), 0, ASMOP_ZERO, 0);
+        emit3_o (A_LD, result->aop, 0, ASMOP_ZERO, 0);
       if (aopInReg (lowbyte, 0, A_IDX))
         emit3 (A_RRA, 0, 0);
       else
@@ -9237,18 +11458,26 @@
         cheapMove (result->aop, 0, lowbyte, 0, true);
       return;
     }
-
-  if (AOP_TYPE (result) != AOP_REG && AOP_TYPE (left) == AOP_REG && AOP_SIZE (left) >= 2 && !bitVectBitValue (ic->rSurv, AOP (left)->aopu.aop_reg[0]->rIdx) && !bitVectBitValue (ic->rSurv, AOP (left)->aopu.aop_reg[1]->rIdx) ||
-    getPairId (AOP (left)) == PAIR_HL && isPairDead (PAIR_HL, ic))
-    shiftoperand = left;
-  else if (isPair (AOP (result)) && !offr)
-    fetchPairLong (getPairId (AOP (result)), AOP(left), ic, offl);
+  if ((result->aop->type == AOP_HL || result->aop->type == AOP_IY || IS_RAB && result->aop->type == AOP_STK) && // Being able to use cheap add hl, hl is worth it in most cases.
+    (left->aop->type == AOP_HL || left->aop->type == AOP_IY || IS_RAB && left->aop->type == AOP_STK) &&
+    !IS_SM83 && isPairDead (PAIR_HL, ic) &&
+    (shCount > 1 || !sameRegs (result->aop, left->aop)) ||
+    isPairDead (PAIR_HL, ic) && !IS_SM83 && getPairId (result->aop) == PAIR_DE && getPairId (left->aop) != PAIR_DE) // Shift in hl if we can cheaply move to de via ex later.
+    {
+      shiftaop = ASMOP_HL;
+      genMove (ASMOP_HL, left->aop, isRegDead (A_IDX, ic), true, isPairDead (PAIR_DE, ic), true);
+    }
+  else if (result->aop->type != AOP_REG && left->aop->type == AOP_REG && left->aop->size >= 2 && !bitVectBitValue (ic->rSurv, left->aop->aopu.aop_reg[0]->rIdx) && !bitVectBitValue (ic->rSurv, left->aop->aopu.aop_reg[1]->rIdx) ||
+    getPairId (left->aop) == PAIR_HL && isPairDead (PAIR_HL, ic))
+    shiftaop = left->aop;
+  else if (isPair (result->aop))
+    fetchPairLong (getPairId (result->aop), left->aop, ic, 0);
   else
-    genMove_o (result->aop, offr, left->aop, offl, 2, true, isPairDead (PAIR_HL, ic));
+    genMove_o (result->aop, 0, left->aop, 0, 2, isRegDead (A_IDX, ic), isPairDead (PAIR_HL, ic), isPairDead (PAIR_DE, ic), true, true);
 
   if (shCount == 0)
     ;
-  else if (getPairId (AOP (shiftoperand)) == PAIR_HL)
+  else if (getPairId (shiftaop) == PAIR_HL)
     {
       while (shCount--)
         {
@@ -9256,7 +11485,7 @@
           regalloc_dry_run_cost += 1;
         }
     }
-  else if (getPairId (AOP (shiftoperand)) == PAIR_IY)
+  else if (getPairId (shiftaop) == PAIR_IY)
     {
       while (shCount--)
         {
@@ -9264,76 +11493,313 @@
           regalloc_dry_run_cost += 2;
         }
     }
-  else if (IS_RAB && getPairId (AOP (shiftoperand)) == PAIR_DE)
+  else if (IS_RAB && getPairId (shiftaop) == PAIR_DE && shCount <= 2 + optimize.codeSpeed)
     {
       while (shCount--)
         {
-          emit3 (A_CP, ASMOP_A, ASMOP_A);
-          emit2 ("rl de");
-          regalloc_dry_run_cost++;
+          emit3 (A_CP, ASMOP_A, ASMOP_A);
+          emit2 ("rl de");
+          regalloc_dry_run_cost++;
+        }
+    }
+  else if (!IS_SM83 && getPairId (shiftaop) == PAIR_DE)
+    {
+      emit2 ("ex de, hl");
+      regalloc_dry_run_cost++;
+      while (shCount--)
+        {
+          emit2 ("add hl, hl");
+          regalloc_dry_run_cost++;
+        }
+      emit2 ("ex de, hl");
+      regalloc_dry_run_cost++;
+    }
+  else
+    {
+      int size = 2;
+      int offset = 0;
+      
+      bool use_b = (!IS_SM83 && isRegDead (B_IDX, ic)
+        && (shiftaop->type != AOP_REG || shiftaop->aopu.aop_reg[0]->rIdx != B_IDX && shiftaop->aopu.aop_reg[1]->rIdx != B_IDX));
+                         
+      symbol *tlbl = regalloc_dry_run ? 0 : newiTempLabel (0);
+
+      if (shiftaop->type == AOP_REG)
+        {
+          while (shCount--)
+            {
+              for (offset = 0; offset < size; offset++)
+                if (aopInReg (shiftaop, offset, A_IDX))
+                  emit3 (offset ? A_ADC : A_ADD, ASMOP_A, ASMOP_A);
+                else
+                  emit3_o (offset ? A_RL : A_SLA, shiftaop, offset, 0, 0);
+            }
+        }
+      else
+        {
+          /* Left is already in result - so now do the shift */
+          if (shCount > 1)
+            {
+              if (!regalloc_dry_run)
+                {
+                  emit2 ("ld %s, !immedbyte", use_b ? "b" : "a", shCount);
+                  emitLabel (tlbl);
+                }
+              regalloc_dry_run_cost += 2;
+              
+              if (requiresHL (shiftaop))
+                spillPair (PAIR_HL);
+            }
+
+          if (!use_b && !isRegDead (A_IDX, ic))
+            _push (PAIR_AF);
+
+          while (size--)
+            {
+              emit3_o (offset ? A_RL : A_SLA, shiftaop, offset, 0, 0);
+
+              offset++;
+            }
+          if (shCount > 1)
+            {
+              if (!regalloc_dry_run)
+                {
+                  if (use_b)
+                    emit2 ("djnz !tlabel", labelKey2num (tlbl->key));
+                  else
+                    {
+                      emit2 ("dec a");
+                      emit2 ("jp NZ, !tlabel", labelKey2num (tlbl->key));
+                    }
+                }
+                regalloc_dry_run_cost += use_b ? 2 : 3;
+            }
+          if (!use_b && !isRegDead (A_IDX, ic))
+            _pop (PAIR_AF);
+        }
+    }
+
+  if (shiftaop != result->aop)
+    {
+      if (isPair (result->aop))
+        fetchPairLong (getPairId (result->aop), shiftaop, ic, 0);
+      else
+        genMove_o (result->aop, 0, shiftaop, 0, 2, isRegDead (A_IDX, ic), isPairDead (PAIR_HL, ic), isPairDead (PAIR_DE, ic), true, true);
+    }
+}
+
+/*-----------------------------------------------------------------*/
+/* genSwap - generates code to swap nibbles or bytes               */
+/*-----------------------------------------------------------------*/
+static void
+genSwap (iCode * ic)
+{
+  operand *left, *result;
+  asmop swapped_result_aop;
+  
+  left = IC_LEFT (ic);
+  result = IC_RESULT (ic);
+  aopOp (left, ic, FALSE, FALSE);
+  aopOp (result, ic, FALSE, FALSE);
+  bool pushed_a = false;
+  switch (left->aop->size)
+    {
+    case 1: // swap nibbles in byte
+      ;
+      bool needLastMove = true;
+      // For sm83, options other than a can make sense for swapping in.
+      asmop *shiftop = ASMOP_A;
+      if (IS_SM83)
+        {
+          if (result->aop->type == AOP_REG || result->aop->type == AOP_STK || result->aop->type == AOP_HL) 
+            shiftop = result->aop;
+          else if (left->aop->type == AOP_REG && !bitVectBitValue (ic->rSurv, left->aop->aopu.aop_reg[0]->rIdx))
+            shiftop = left->aop;
+        }
+
+      if (!isRegDead (A_IDX, ic) && aopInReg (shiftop, 0, A_IDX))
+        {
+          _push (PAIR_AF);
+          pushed_a = true;
+        }
+
+      genMove (shiftop, left->aop, isRegDead (A_IDX, ic) || pushed_a, isPairDead (PAIR_HL, ic), isPairDead (PAIR_DE, ic), true);
+
+      if (IS_SM83 || IS_Z80N)
+        emit3 (A_SWAP, shiftop, 0);
+      else if (!IS_SM83 && !IS_RAB && aopInReg (shiftop, 0, A_IDX) &&
+        (result->aop->type == AOP_DIR || result->aop->type == AOP_HL || result->aop->type == AOP_IY) && isPairDead (PAIR_HL, ic))
+        {
+          if (!aopSame (result->aop, 0, left->aop, 0, 1))
+            cheapMove (result->aop, 0, ASMOP_A, 0, true);
+          pointPairToAop (PAIR_HL, result->aop, 0);
+          emit3 (A_RRD, 0, 0);
+          needLastMove = false;
+        }
+      else
+        {
+          emit3 (A_RLCA, 0, 0);
+          emit3 (A_RLCA, 0, 0);
+          emit3 (A_RLCA, 0, 0);
+          emit3 (A_RLCA, 0, 0);
+        }
+
+      if (needLastMove)
+        genMove (result->aop, shiftop, isRegDead (A_IDX, ic) || pushed_a, isPairDead (PAIR_HL, ic), isPairDead (PAIR_DE, ic), true);
+
+      if (pushed_a)
+        _pop (PAIR_AF);  
+
+      break;
+    case 2: // swap bytes in word
+      if (result->aop->type == AOP_REG) // Create result asmop with swapped bytes, let genMove handle the details.
+        {
+          signed char idxarray[3];
+          idxarray[0] = result->aop->aopu.aop_reg[1]->rIdx;
+          idxarray[1] = result->aop->aopu.aop_reg[0]->rIdx;
+          idxarray[2] = -1;
+          z80_init_reg_asmop (&swapped_result_aop, idxarray);
+          genMove (&swapped_result_aop, left->aop, isRegDead (A_IDX, ic), isPairDead (PAIR_HL, ic), isPairDead (PAIR_DE, ic), true);
+          break;
         }
-    }
-  else
-    {
-      int size = 2;
-      int offset = 0;
-      symbol *tlbl = regalloc_dry_run ? 0 : newiTempLabel (0);
-      symbol *tlbl1 = regalloc_dry_run ? 0 : newiTempLabel (0);
 
-      if (AOP (shiftoperand)->type == AOP_REG)
+      if (sameRegs (result->aop, left->aop) || operandsEqu (result, left))
         {
-          while (shCount--)
+          // avoid push/pop by finding free register
+          asmop *free_reg = ASMOP_A;
+          if (isRegDead (B_IDX, ic))
+            free_reg = ASMOP_B;
+          if (isRegDead (C_IDX, ic))
+            free_reg = ASMOP_C;
+          if (isRegDead (D_IDX, ic))
+            free_reg = ASMOP_D;
+          if (isRegDead (E_IDX, ic))
+            free_reg = ASMOP_E;
+          _moveA (aopGet (left->aop, 0, FALSE));
+          if (free_reg == ASMOP_A)
             {
-              for (offset = 0; offset < size; offset++)
-                emit3_o (offset ? A_RL : A_SLA, AOP (shiftoperand), offset, 0, 0);
+              _push (PAIR_AF);
+              pushed_a = true;
             }
+          // if left and result are registers, this should get optimized away
+          cheapMove (free_reg, 0, left->aop, 1, FALSE);
+          cheapMove (result->aop, (free_reg == ASMOP_A ? 0 : 1), ASMOP_A, 0, FALSE);
+          if(pushed_a){
+            _pop (PAIR_AF);
+          }
+          cheapMove (result->aop, (free_reg == ASMOP_A ? 1 : 0), free_reg, 0, TRUE);
         }
       else
         {
-          /* Left is already in result - so now do the shift */
-          if (shCount > 1)
-            {
-              if (!regalloc_dry_run)
+          aopPut (result->aop, aopGet (left->aop, 1, FALSE), 0);
+          aopPut (result->aop, aopGet (left->aop, 0, FALSE), 1);
+        }
+      break;
+
+    case 4: // swap words in double word
+        if (result->aop->type == AOP_REG) // Create result asmop with swapped words, let genMove handle the details.
+        {
+          signed char idxarray[5];
+          idxarray[0] = result->aop->aopu.aop_reg[2]->rIdx;
+          idxarray[1] = result->aop->aopu.aop_reg[3]->rIdx;
+          idxarray[2] = result->aop->aopu.aop_reg[0]->rIdx;
+          idxarray[3] = result->aop->aopu.aop_reg[1]->rIdx;
+          idxarray[4] = -1;
+          z80_init_reg_asmop(&swapped_result_aop, idxarray);
+          genMove (&swapped_result_aop, left->aop, isRegDead (A_IDX, ic), isPairDead (PAIR_HL, ic), isPairDead (PAIR_DE, ic), true);
+          break;
+        }
+      if (operandsEqu (result, left) && left->aop->type == AOP_STK &&
+          spOffset (left->aop->aopu.aop_stk) == 0 && isPairDead (PAIR_HL, ic) &&
+          (!IS_SM83 || isPairDead(PAIR_DE, ic) || isPairDead(PAIR_BC, ic)))
+        { /* result & left are top of stack and there are free register pairs */
+          if (IS_SM83)
+            {
+              if (isPairDead(PAIR_DE, ic))
+                {
+                  _pop (PAIR_DE);
+                  _pop (PAIR_HL);
+                  _push (PAIR_DE);
+                  _push (PAIR_HL);
+                }
+              else
                 {
-                  emit2 ("ld a, !immedbyte+1", shCount);
-                  emit2 ("jp !tlabel", labelKey2num (tlbl1->key));
-                  emitLabel (tlbl);
+                  _pop (PAIR_BC);
+                  _pop (PAIR_HL);
+                  _push (PAIR_BC);
+                  _push (PAIR_HL);
                 }
-              regalloc_dry_run_cost += 4;
-            }
-
-          while (size--)
-            {
-              emit3_o (offset ? A_RL : A_SLA, AOP (shiftoperand), offset, 0, 0);
-
-              offset++;
             }
-          if (shCount > 1)
+          else
             {
-              if (!regalloc_dry_run)
-                {
-                  emitLabel (tlbl1);
-                  emit2 ("dec a");
-                  emit2 ("jp NZ, !tlabel", labelKey2num (tlbl->key));
-                }
-              regalloc_dry_run_cost += 4;
+              _pop (PAIR_HL);
+              emit2 ("ex (sp), hl");
+              regalloc_dry_run_cost++;
+              _push (PAIR_HL);
             }
+          break;
         }
-    }
 
-  if (shiftoperand != result)
-    {
-      if (isPair (AOP (result)) && !offr)
-        fetchPairLong (getPairId (AOP (result)), AOP(shiftoperand), ic, offl);
-      else if (isPair (AOP (shiftoperand)))
-        commitPair (AOP (result), getPairId (AOP (shiftoperand)), ic, FALSE);
+      /* --== generic implementations ==-- */
+      if (!operandsEqu (result, left))
+        { /* result is registers or left differs than result */
+          bool pushed = !isRegDead (A_IDX, ic);
+          if (pushed)
+            _push (PAIR_AF);
+          cheapMove (ASMOP_A, 0, left->aop, 0, TRUE);
+          cheapMove (result->aop, 0, left->aop, 2, FALSE);
+          cheapMove (result->aop, 2, ASMOP_A, 0, FALSE);
+          cheapMove (ASMOP_A, 0, left->aop, 1, TRUE);
+          cheapMove (result->aop, 1, left->aop, 3, FALSE);
+          cheapMove (result->aop, 3, ASMOP_A, 0, FALSE);
+          if (pushed)
+            _pop (PAIR_AF);
+        }
       else
         {
-          /* Copy left into result */
-          movLeft2Result (shiftoperand, offl, result, offr, 0);
-          movLeft2Result (shiftoperand, offl + 1, result, offr + 1, 0);
+          asmop *tmp = NULL;
+          bool pushed = false;
+          bool dead_a = isRegDead (A_IDX, ic);
+          bool dead_de = isPairDead (PAIR_DE, ic);
+          bool dead_hl = isPairDead (PAIR_HL, ic);
+          if (isPairDead (PAIR_BC, ic) &&
+              (left->aop->type != AOP_REG || !aopInReg (left->aop, 0, BC_IDX)))
+            tmp = ASMOP_BC;
+          else if (dead_hl &&
+              (left->aop->type != AOP_REG || !aopInReg (left->aop, 0, HL_IDX)))
+            tmp = ASMOP_HL;
+          else if (dead_de &&
+                   (left->aop->type != AOP_REG || !aopInReg (left->aop, 0, DE_IDX)))
+            tmp = ASMOP_DE;
+          else if (!IS_SM83 && !IY_RESERVED && isPairDead (PAIR_IY, ic) &&
+                   (left->aop->type != AOP_REG || !aopInReg (left->aop, 0, IY_IDX)))
+            tmp = ASMOP_IY;
+          else 
+            {
+              pushed = true;
+              if ((left->aop->type != AOP_REG || !aopInReg (left->aop, 0, HL_IDX)))
+                tmp = ASMOP_HL;
+              else if ((left->aop->type != AOP_REG || !aopInReg (left->aop, 0, BC_IDX)))
+                tmp = ASMOP_BC;
+              else if ((left->aop->type != AOP_REG || !aopInReg (left->aop, 0, DE_IDX)))
+                tmp = ASMOP_DE;
+              else
+                wassertl (FALSE, "impossible case");
+              _push (tmp->aopu.aop_pairId);
+            }
+          genMove_o (tmp, 0, left->aop, 0, 2, dead_a, dead_hl && !aopInReg (left->aop, 2, HL_IDX), dead_de && !aopInReg (left->aop, 2, DE_IDX), true, true);
+          genMove_o (result->aop, 0, left->aop, 2, 2, dead_a, dead_hl && (tmp != ASMOP_HL), dead_de && (tmp != ASMOP_DE), true, true);
+          genMove_o (result->aop, 2, tmp, 0, 2, dead_a, dead_hl && !aopInReg (result->aop, 0, HL_IDX), dead_de && !aopInReg (result->aop, 0, DE_IDX), true, true);
+          if (pushed)
+            _pop (tmp->aopu.aop_pairId);
         }
+      break;
+    default:
+      wassertl (FALSE, "unsupported SWAP operand size");
     }
+
+  freeAsmop (result, NULL);
+  freeAsmop (left, NULL);
 }
 
 /*-----------------------------------------------------------------*/
@@ -9347,14 +11813,14 @@
   switch (shCount)
     {
     case 4:
-      if (IS_GB)
+      if (IS_SM83 || IS_Z80N)
         {
           emit3 (A_SWAP, ASMOP_A, 0);
           break;
         }
       emit3 (A_RLCA, 0, 0);
     case 3:
-      if (IS_GB)
+      if (IS_SM83 || IS_Z80N)
         {
           emit3 (A_SWAP, ASMOP_A, 0);
           emit3 (A_RRCA, 0, 0);
@@ -9368,7 +11834,7 @@
     case 0:
       break;
     case 5:
-      if (IS_GB)
+      if (IS_SM83 || IS_Z80N)
         {
           emit3 (A_SWAP, ASMOP_A, 0);
           emit3 (A_RLCA, 0, 0);
@@ -9394,7 +11860,7 @@
     0xFF, 0xFE, 0xFC, 0xF8, 0xF0, 0xE0, 0xC0, 0x80, 0x00
   };
 
-  if (shCount <= 3 + !IS_GB)
+  if (shCount <= 3 + !IS_SM83)
     while (shCount--)
       emit3 (A_ADD, ASMOP_A, ASMOP_A);
   else
@@ -9413,37 +11879,55 @@
 static void
 shiftL1Left2Result (operand *left, int offl, operand *result, int offr, unsigned int shCount, const iCode *ic)
 {
+  // add hl, hl is cheap in code size. On Rabbits it is also fastest.
+  if (sameRegs (result->aop, left->aop) && aopInReg (result->aop, offr, L_IDX) && isPairDead(PAIR_HL, ic) && offr == offl && (!optimize.codeSpeed && IS_RAB))
+    {
+      while (shCount--)
+        {
+          emit2 ("add hl, hl");
+          regalloc_dry_run_cost++;
+        }
+    }
+  else if (!IS_SM83 && !IS_RAB && aopSame (result->aop, offr, left->aop, offr, 1) && !offr && shCount == 4 && isPairDead (PAIR_HL, ic) && isRegDead (A_IDX, ic) &&
+    (result->aop->type == AOP_DIR || result->aop->type == AOP_HL || result->aop->type == AOP_IY))
+    {
+      emit2 ("xor a, a");
+      regalloc_dry_run_cost++;
+      pointPairToAop (PAIR_HL, result->aop, 0);
+      emit2 ("rld");
+      regalloc_dry_run_cost += 2;
+    }
   /* If operand and result are the same we can shift in place.
      However shifting in acc using add is cheaper than shifting
      in place using sla; when shifting by more than 2 shifting in
      acc it is worth the additional effort for loading from / to acc. */
-  if (!aopInReg(result->aop, 0, A_IDX) && sameRegs (AOP (left), AOP (result)) && shCount <= 2 && offr == offl)
+  else if (!aopInReg(result->aop, 0, A_IDX) && sameRegs (left->aop, result->aop) && shCount <= 2 && offr == offl)
     {
       while (shCount--)
-        emit3 (A_SLA, AOP (result), 0);
+        emit3 (A_SLA, result->aop, 0);
     }
-  else if ((IS_Z180 && !optimize.codeSpeed || IS_EZ80_Z80) && // Try to use mlt
-    (aopInReg (result->aop, offr, C_IDX) && isPairDead(PAIR_BC, ic) || aopInReg (result->aop, offr, E_IDX) && isPairDead(PAIR_DE, ic) || aopInReg (result->aop, offr, L_IDX) && isPairDead(PAIR_HL, ic)))
+  else if ((IS_Z180 && !optimize.codeSpeed || IS_EZ80_Z80 || IS_Z80N) && // Try to use mlt
+    (!IS_Z80N && aopInReg (result->aop, offr, C_IDX) && isPairDead(PAIR_BC, ic) || aopInReg (result->aop, offr, E_IDX) && isPairDead(PAIR_DE, ic) || !IS_Z80N && aopInReg (result->aop, offr, L_IDX) && isPairDead(PAIR_HL, ic)))
     {
       PAIR_ID pair = aopInReg (result->aop, offr, C_IDX) ? PAIR_BC : (aopInReg (result->aop, offr, E_IDX) ? PAIR_DE : PAIR_HL);
 
       bool top = aopInReg (left->aop, offl, _pairs[pair].h_idx);
       if (!top)
-        cheapMove (pair == PAIR_BC ? ASMOP_C : (pair == PAIR_DE ? ASMOP_E : ASMOP_L), 0, left->aop, offl, !bitVectBitValue (ic->rSurv, A_IDX));
+        cheapMove (pair == PAIR_BC ? ASMOP_C : (pair == PAIR_DE ? ASMOP_E : ASMOP_L), 0, left->aop, offl, isRegDead (A_IDX, ic));
 
-      emit2 ("ld %s, #%d", top ? _pairs[pair].l : _pairs[pair].h, 1 << shCount);
+      emit2 ("ld %s, !immed%d", top ? _pairs[pair].l : _pairs[pair].h, 1 << shCount);
       emit2 ("mlt %s", _pairs[pair].name);
       regalloc_dry_run_cost += 4;
     }
   else
     {
-      if (bitVectBitValue (ic->rSurv, A_IDX))
+      if (!isRegDead (A_IDX, ic))
         _push (PAIR_AF);
       cheapMove (ASMOP_A, 0, left->aop, offl, true);
       /* shift left accumulator */
       AccLsh (shCount);
-      cheapMove (AOP (result), offr, ASMOP_A, 0, true);
-      if (bitVectBitValue (ic->rSurv, A_IDX))
+      cheapMove (result->aop, offr, ASMOP_A, 0, true);
+      if (!isRegDead (A_IDX, ic))
         _pop (PAIR_AF);
     }
 }
@@ -9454,12 +11938,20 @@
 static void
 genlshTwo (operand *result, operand *left, unsigned int shCount, const iCode *ic)
 {
-  int size = AOP_SIZE (result);
+  int size = result->aop->size;
 
   wassert (size == 2);
 
-  /* if shCount >= 8 */
-  if (shCount >= 8)
+  if (IS_Z80N &&
+    aopInReg (result->aop, 0, DE_IDX) && isRegDead (B_IDX, ic) &&
+    shCount > 2 && shCount != 8) // Only worth it when shifting by more than 2 (we can get a cheap path using add hl, hl in shiftL2Left2Result (left, result, shCount, ic)).
+    {
+      genMove (ASMOP_DE, left->aop, isRegDead (A_IDX, ic), isRegDead (HL_IDX, ic), true, true);
+      emit2 ("ld b, !immedbyte", shCount);
+      emit2 ("bsla de, b");
+      regalloc_dry_run_cost += 4;
+    }
+  else if (shCount >= 8)
     {
       shCount -= 8;
       if (size > 1)
@@ -9467,22 +11959,12 @@
           if (shCount)
             shiftL1Left2Result (left, 0, result, 1, shCount, ic);
           else
-            movLeft2Result (left, LSB, result, MSB16, 0);
+            cheapMove (result->aop, 1, left->aop, 0, isRegDead (A_IDX, ic));
         }
-      cheapMove (result->aop, 0, ASMOP_ZERO, 0, true);
+      cheapMove (result->aop, 0, ASMOP_ZERO, 0, isRegDead (A_IDX, ic));
     }
-  /*  0 <= shCount <= 7 */
   else
-    {
-      if (size == 1)
-        {
-          wassert (0);
-        }
-      else
-        {
-          shiftL2Left2Result (left, LSB, result, LSB, shCount, ic);
-        }
-    }
+    shiftL2Left2Result (left, result, shCount, ic);
 }
 
 /*------------------------------------------------------------------*/
@@ -9491,7 +11973,7 @@
 static void
 genLeftShiftLiteral (operand *left, operand *right, operand *result, const iCode *ic)
 {
-  unsigned int shCount = ulFromVal (AOP (right)->aopu.aop_lit);
+  unsigned int shCount = ulFromVal (right->aop->aopu.aop_lit);
   unsigned int size;
 
   freeAsmop (right, NULL);
@@ -9505,7 +11987,7 @@
   wassert (getSize (operandType (left)) >= size);
 
   if (shCount >= (size * 8))
-    genMove (result->aop, ASMOP_ZERO, !bitVectBitValue (ic->rSurv, A_IDX), isPairDead (PAIR_HL, ic) && left->aop->regs[H_IDX] < 0 && left->aop->regs[L_IDX] < 0);
+    genMove (result->aop, ASMOP_ZERO, isRegDead (A_IDX, ic), isPairDead (PAIR_HL, ic) && left->aop->regs[H_IDX] < 0 && left->aop->regs[L_IDX] < 0, isPairDead (PAIR_DE, ic) && left->aop->regs[D_IDX] < 0 && left->aop->regs[E_IDX] < 0, true);
   else
     {
       switch (size)
@@ -9536,12 +12018,13 @@
   int size, offset;
   symbol *tlbl = 0, *tlbl1 = 0;
   operand *left, *right, *result;
+  asmop *shiftop;
   int countreg;
   bool shift_by_lit;
   int shiftcount = 0;
   int byteshift = 0;
   bool started;
-  bool save_a;
+  bool save_a_outer = false;
 
   right = IC_RIGHT (ic);
   left = IC_LEFT (ic);
@@ -9551,7 +12034,7 @@
 
   /* if the shift count is known then do it
      as efficiently as possible */
-  if (AOP_TYPE (right) == AOP_LIT && getSize (operandType (result)) <= 2)
+  if (right->aop->type == AOP_LIT && getSize (operandType (result)) <= 2)
     {
       genLeftShiftLiteral (left, right, result, ic);
       freeAsmop (right, NULL);
@@ -9559,36 +12042,75 @@
     }
 
   /* Useful for the case of shifting a size > 2 value by a literal */
-  shift_by_lit = AOP_TYPE (right) == AOP_LIT;
+  shift_by_lit = right->aop->type == AOP_LIT;
   if (shift_by_lit)
-    shiftcount = ulFromVal (AOP (right)->aopu.aop_lit);
+    shiftcount = ulFromVal (right->aop->aopu.aop_lit);
 
   aopOp (result, ic, FALSE, FALSE);
   aopOp (left, ic, FALSE, FALSE);
 
-  if (AOP_TYPE (right) == AOP_REG && !bitVectBitValue (ic->rSurv, AOP (right)->aopu.aop_reg[0]->rIdx) && AOP (right)->aopu.aop_reg[0]->rIdx != IYL_IDX && (sameRegs (AOP (left), AOP (result)) || AOP_TYPE (left) != AOP_REG) &&
-    (AOP_TYPE (result) != AOP_REG ||
-    AOP (result)->aopu.aop_reg[0]->rIdx != AOP (right)->aopu.aop_reg[0]->rIdx &&
-    !aopInReg (AOP (result), 0, AOP (right)->aopu.aop_reg[0]->rIdx) && !aopInReg (AOP (result), 1, AOP (right)->aopu.aop_reg[0]->rIdx) && !aopInReg (AOP (result), 2, AOP (right)->aopu.aop_reg[0]->rIdx) && !aopInReg (AOP (result), 3, AOP (right)->aopu.aop_reg[0]->rIdx)))
-    countreg = AOP (right)->aopu.aop_reg[0]->rIdx;
-  else if (!IS_GB && !bitVectBitValue (ic->rSurv, B_IDX) && (sameRegs (AOP (left), AOP (result)) || AOP_TYPE (left) != AOP_REG || shift_by_lit) &&
-    !aopInReg (AOP (result), 0, B_IDX) && !aopInReg (AOP (result), 1, B_IDX) && !aopInReg (AOP (result), 2, B_IDX) && !aopInReg (AOP (result), 3, B_IDX))
+  bool z80n_de = ((result->aop->size == 2 && (aopInReg (result->aop, 0, DE_IDX) || aopInReg (left->aop, 0, DE_IDX)) ||
+      result->aop->size == 1 && (aopInReg (result->aop, 0, D_IDX) || aopInReg (left->aop, 0, D_IDX)))) && isRegDead (PAIR_DE, ic);
+
+  if (right->aop->type == AOP_REG && !bitVectBitValue (ic->rSurv, right->aop->aopu.aop_reg[0]->rIdx) && right->aop->aopu.aop_reg[0]->rIdx != IYL_IDX && (sameRegs (left->aop, result->aop) || left->aop->type != AOP_REG) &&
+    (result->aop->type != AOP_REG ||
+    result->aop->aopu.aop_reg[0]->rIdx != right->aop->aopu.aop_reg[0]->rIdx &&
+    !aopInReg (result->aop, 0, right->aop->aopu.aop_reg[0]->rIdx) && !aopInReg (result->aop, 1, right->aop->aopu.aop_reg[0]->rIdx) && !aopInReg (result->aop, 2, right->aop->aopu.aop_reg[0]->rIdx) && !aopInReg (result->aop, 3, right->aop->aopu.aop_reg[0]->rIdx)))
+    countreg = right->aop->aopu.aop_reg[0]->rIdx;
+  else if (!IS_SM83 && isRegDead (B_IDX, ic) && (sameRegs (left->aop, result->aop) || left->aop->type != AOP_REG || shift_by_lit) &&
+    !aopInReg (result->aop, 0, B_IDX) && !aopInReg (result->aop, 1, B_IDX) && !aopInReg (result->aop, 2, B_IDX) && !aopInReg (result->aop, 3, B_IDX))
     countreg = B_IDX;
-  else
+  else if (isRegDead (A_IDX, ic) && result->aop->regs[A_IDX] < 0 && left->aop->regs[A_IDX] < 0)
     countreg = A_IDX;
+  else if (isRegDead (B_IDX, ic) && result->aop->regs[B_IDX] < 0 && left->aop->regs[B_IDX] < 0)
+    countreg = B_IDX;
+  else if (isRegDead (C_IDX, ic) && result->aop->regs[C_IDX] < 0 && left->aop->regs[C_IDX] < 0)
+    countreg = C_IDX;
+  else if (IS_Z80N && z80n_de && aopInReg (right->aop, 0, B_IDX))
+    countreg = B_IDX;
+  else
+    {
+      UNIMPLEMENTED;
+      countreg = A_IDX;
+    }
+
+  if (IS_Z80N && z80n_de && (aopInReg (right->aop, 0, B_IDX) || countreg == B_IDX))
+    {
+      shiftop = result->aop->size == 2 ? ASMOP_DE : ASMOP_E;
+      cheapMove (ASMOP_B, 0, right->aop, 0, isRegDead (A_IDX, ic));
+      genMove (shiftop, left->aop, isRegDead (A_IDX, ic), isRegDead (HL_IDX, ic), true, true);
+      emit2 ("bsla de, b");
+      regalloc_dry_run_cost += 2;
+      goto end;
+    }
 
+  save_a_outer = (!isRegDead (A_IDX, ic) && countreg == A_IDX && !(shift_by_lit && shiftcount == 1));
+  
+  if(save_a_outer)
+      _push (PAIR_AF);
+    
   if (!shift_by_lit)
     cheapMove (asmopregs[countreg], 0, right->aop, 0, true);
 
-  save_a = (countreg == A_IDX && !shift_by_lit) &&
-    !(AOP_TYPE (left) == AOP_REG && AOP_TYPE (result) != AOP_REG ||
-    !IS_GB && (AOP_TYPE (left) == AOP_STK && canAssignToPtr3 (result->aop) || AOP_TYPE (result) == AOP_STK && canAssignToPtr3 (left->aop)));
+  bool save_a_inner = (countreg == A_IDX && !shift_by_lit) &&
+    !(left->aop->type == AOP_REG && result->aop->type != AOP_REG ||
+    !IS_SM83 && (left->aop->type == AOP_STK && canAssignToPtr3 (result->aop) || result->aop->type == AOP_STK && canAssignToPtr3 (left->aop)));
+
+  shiftop = result->aop;
+  if (result->aop->type != AOP_REG && left->aop->type == AOP_REG && result->aop->size == left->aop->size && left->aop->regs[countreg] < 0)
+    {
+      bool left_dead = true;
+      for (int i = 0; i < left->aop->size; i++)
+        left_dead &= isRegDead (left->aop->aopu.aop_reg[i]->rIdx, ic);
+      if (left_dead)
+        shiftop = left->aop;
+    }
 
   /* now move the left to the result if they are not the
      same */
-  if (!sameRegs (AOP (left), AOP (result)))
+  if (!sameRegs (shiftop, left->aop) || shiftop->type == AOP_REG)
     {
-      if (save_a)
+      if (save_a_inner)
         _push (PAIR_AF);
 
       if (shift_by_lit)
@@ -9596,14 +12118,17 @@
         byteshift = shiftcount / 8;
         shiftcount %= 8;
       }
-      size = AOP_SIZE (result) - byteshift;
-      int lsize = AOP_SIZE (left) - byteshift;
-
-      genMove_o (result->aop, byteshift, left->aop, 0, size <= lsize ? size : lsize, save_a || countreg != A_IDX, false);
+      size = shiftop->size - byteshift;
+      int lsize = left->aop->size - byteshift;
 
-      genMove_o (result->aop, 0, ASMOP_ZERO, 0, byteshift, save_a || countreg != A_IDX, false);
+      bool hl_dead = isPairDead (PAIR_HL, ic) && (countreg != L_IDX && countreg != H_IDX || shift_by_lit);
+      bool de_dead = isPairDead (PAIR_DE, ic) && (countreg != E_IDX && countreg != D_IDX || shift_by_lit);
+      genMove_o (shiftop, byteshift, left->aop, 0, size <= lsize ? size : lsize, (save_a_inner || countreg != A_IDX) && (isRegDead (A_IDX, ic) || save_a_outer), hl_dead, de_dead, true, true);
+      hl_dead &= shiftop->regs[L_IDX] < byteshift && shiftop->regs[L_IDX] < byteshift;
+      de_dead &= shiftop->regs[E_IDX] < byteshift && shiftop->regs[D_IDX] < byteshift;
+      genMove_o (shiftop, 0, ASMOP_ZERO, 0, byteshift, (save_a_inner || countreg != A_IDX) && (isRegDead (A_IDX, ic) || save_a_outer), hl_dead, de_dead, true, true);
 
-      if (save_a)
+      if (save_a_inner)
         _pop (PAIR_AF);
     }
 
@@ -9612,8 +12137,8 @@
       tlbl = newiTempLabel (NULL);
       tlbl1 = newiTempLabel (NULL);
     }
-  size = AOP_SIZE (result);
-  offset = 0;
+  size = shiftop->size - byteshift;
+  offset = byteshift;
 
   if (shift_by_lit && !shiftcount)
     goto end;
@@ -9631,32 +12156,48 @@
       regalloc_dry_run_cost += 3;
     }
   if (!(shift_by_lit && shiftcount == 1) && !regalloc_dry_run)
-    emitLabel (tlbl);
-
-  if (requiresHL (AOP (result)))
-    spillPair (PAIR_HL);
+    {
+      emitLabel (tlbl);
+      if (requiresHL (shiftop))
+        spillPair (PAIR_HL);
+    }
 
   started = false;
   while (size)
     {
       if (size >= 2 && offset + 1 >= byteshift &&
-         AOP_TYPE (result) == AOP_REG &&
-        (getPartPairId (AOP (result), offset) == PAIR_HL ||
-         IS_RAB && getPartPairId (AOP (result), offset) == PAIR_DE))
+        shiftop->type == AOP_REG &&
+        (!started || !IS_SM83) && // sm83 doesn't have wide adc
+        (getPartPairId (shiftop, offset) == PAIR_HL ||
+        !started && getPartPairId (shiftop, offset) == PAIR_IY ||
+        (IS_RAB || optimize.codeSize && !started && !IS_SM83) && getPartPairId (shiftop, offset) == PAIR_DE))
         {
-          if (AOP (result)->aopu.aop_reg[offset]->rIdx == L_IDX)
-          {
-            emit2 (started ? "adc hl, hl" : "add hl, hl");
-            regalloc_dry_run_cost += 1 + started;
-          }
+          if (shiftop->aopu.aop_reg[offset]->rIdx == L_IDX)
+            {
+              emit2 (started ? "adc hl, hl" : "add hl, hl");
+              regalloc_dry_run_cost += 1 + started;
+            }
+          else if (shiftop->aopu.aop_reg[offset]->rIdx == IYL_IDX)
+            {
+              emit2 ("add iy, iy");
+              regalloc_dry_run_cost += 2;
+            }
+          else if (IS_RAB)
+            {
+              if (!started)
+                emit3 (A_CP, ASMOP_A, ASMOP_A);
+              emit2 ("rl de");
+              regalloc_dry_run_cost++;
+            }
           else
-          {
-            if (!started)
-              emit3 (A_CP, ASMOP_A, ASMOP_A);
-            emit2 ("rl de");
-            regalloc_dry_run_cost++;
-          }
-          
+            {
+              wassert (!IS_SM83);
+              emit2 ("ex de, hl");
+              emit2 (started ? "adc hl, hl" : "add hl, hl");
+              emit2 ("ex de, hl");
+              regalloc_dry_run_cost += 3 + started;
+            }
+
           started = true;
           size -= 2, offset += 2;
         }
@@ -9664,10 +12205,10 @@
         {
           if (offset >= byteshift)
             {
-              if (aopInReg (AOP (result) , offset, A_IDX))
+              if (aopInReg (shiftop, offset, A_IDX))
                 emit3 (started ? A_ADC : A_ADD, ASMOP_A, ASMOP_A);
               else
-                emit3_o (started ? A_RL : A_SLA, AOP (result), offset, 0, 0);
+                emit3_o (started ? A_RL : A_SLA, shiftop, offset, 0, 0);
               started = true;
             }
           size--, offset++;
@@ -9678,7 +12219,7 @@
     {
       if (!regalloc_dry_run)
         emitLabel (tlbl1);
-      if (!IS_GB && countreg == B_IDX)
+      if (!IS_SM83 && countreg == B_IDX)
         {
           if (!regalloc_dry_run)
             emit2 ("djnz !tlabel", labelKey2num (tlbl->key));
@@ -9686,7 +12227,7 @@
         }
       else
         {
-          emit2 ("dec %s", countreg == A_IDX ? "a" : regsZ80[countreg].name);
+          emit2 ("dec %s", regsZ80[countreg].name);
           if (!regalloc_dry_run)
             emit2 ("jr NZ,!tlabel", labelKey2num (tlbl->key));
           regalloc_dry_run_cost += 3;
@@ -9694,9 +12235,14 @@
     }
 
 end:
-  if (!shift_by_lit && requiresHL (AOP (result))) // Shift by 0 skips over hl adjustments.
+  if (!shift_by_lit && requiresHL (shiftop)) // Shift by 0 skips over hl adjustments.
     spillPair (PAIR_HL);
 
+  genMove_o (result->aop, 0, shiftop, 0, result->aop->size, isRegDead (A_IDX, ic), isPairDead (PAIR_HL, ic), isPairDead (PAIR_DE, ic), true, true);
+
+  if (save_a_outer)
+    _pop (PAIR_AF);
+
   freeAsmop (left, NULL);
   freeAsmop (right, NULL);
   freeAsmop (result, NULL);
@@ -9728,24 +12274,33 @@
 genrshOne (operand *result, operand *left, int shCount, int is_signed, const iCode *ic)
 {
   /* Errk */
-  int size = AOP_SIZE (result);
+  int size = result->aop->size;
 
   wassert (size == 1);
 
-  bool a_dead = !bitVectBitValue (ic->rSurv, A_IDX);
-  
-  if ((IS_Z180 || IS_EZ80_Z80) && !is_signed && shCount >= 3 && shCount <= 6 + a_dead && // Try to use mlt.
-    (aopInReg (result->aop, 0, B_IDX) && isPairDead(PAIR_BC, ic) || aopInReg (result->aop, 0, D_IDX) && isPairDead(PAIR_DE, ic) || aopInReg (result->aop, 0, H_IDX) && isPairDead(PAIR_HL, ic)))
+  bool a_dead = isRegDead (A_IDX, ic);
+
+  if ((IS_Z180 || IS_EZ80_Z80 || IS_Z80N) && !is_signed && shCount >= 3 && shCount <= 6 + a_dead && // Try to use mlt.
+    (!IS_Z80N && aopInReg (result->aop, 0, B_IDX) && isPairDead(PAIR_BC, ic) || aopInReg (result->aop, 0, D_IDX) && isPairDead(PAIR_DE, ic) || !IS_Z80N && aopInReg (result->aop, 0, H_IDX) && isPairDead(PAIR_HL, ic)))
     {
       PAIR_ID pair = aopInReg (result->aop, 0, B_IDX) ? PAIR_BC : (aopInReg (result->aop, 0, D_IDX) ? PAIR_DE : PAIR_HL);
       bool top = aopInReg (left->aop, 0, _pairs[pair].h_idx);
       if (!top)
         cheapMove (pair == PAIR_BC ? ASMOP_C : (pair == PAIR_DE ? ASMOP_E : ASMOP_L), 0, left->aop, 0, a_dead);
 
-      emit2 ("ld %s, #%d", top ? _pairs[pair].l : _pairs[pair].h, 1 << (8 - shCount));
+      emit2 ("ld %s, !immed%d", top ? _pairs[pair].l : _pairs[pair].h, 1 << (8 - shCount));
       emit2 ("mlt %s", _pairs[pair].name);
       regalloc_dry_run_cost += 4;
     }
+  else if (!IS_SM83 && !IS_RAB && !is_signed && aopSame (result->aop, 0, left->aop, 0, 1) && shCount == 4 && isPairDead (PAIR_HL, ic) && isRegDead (A_IDX, ic) &&
+    (result->aop->type == AOP_DIR || result->aop->type == AOP_HL || result->aop->type == AOP_IY))
+    {
+      emit2 ("xor a, a");
+      regalloc_dry_run_cost++;
+      pointPairToAop (PAIR_HL, result->aop, 0);
+      emit2 ("rrd");
+      regalloc_dry_run_cost += 2;
+    }
   else if (!is_signed && // Shifting in the accumulator is cheap for unsigned operands.
     (aopInReg (result->aop, 0, A_IDX) ||
     result->aop->type != AOP_REG ||
@@ -9759,9 +12314,9 @@
       if (!a_dead)
         _pop (PAIR_AF);
     }
-  else if (AOP (result)->type == AOP_REG) // Can shift in destination for register result.
+  else if (result->aop->type == AOP_REG) // Can shift in destination for register result.
     {
-      cheapMove (AOP (result), 0, AOP (left), 0, a_dead);
+      cheapMove (result->aop, 0, left->aop, 0, a_dead);
 
       while (shCount--)
         emit3 (is_signed ? A_SRA : A_SRL, result->aop, 0);
@@ -9800,32 +12355,35 @@
 /* genrshTwo - right shift two bytes by known amount               */
 /*-----------------------------------------------------------------*/
 static void
-genrshTwo (const iCode * ic, operand * result, operand * left, int shCount, int sign)
+genrshTwo (const iCode *ic, operand *result, operand *left, int shCount, int sign)
 {
-  /* if shCount >= 8 */
-  if (shCount >= 8)
+  if (IS_Z80N &&
+    aopInReg (result->aop, 0, DE_IDX) && isRegDead (B_IDX, ic) &&
+    shCount != 8)
+    {
+      genMove (ASMOP_DE, left->aop, isRegDead (A_IDX, ic), isRegDead (HL_IDX, ic), true, true);
+      emit2 ("ld b, !immedbyte", shCount);
+      emit2 (sign ? "bsra de, b" : "bsrl de, b");
+      regalloc_dry_run_cost += 4;
+    }
+  else if (shCount >= 8)
     {
       shCount -= 8;
       if (shCount)
-        {
-          shiftR1Left2Result (left, MSB16, result, LSB, shCount, sign);
-        }
+        shiftR1Left2Result (left, MSB16, result, LSB, shCount, sign);
       else
-        {
-          movLeft2Result (left, MSB16, result, LSB, sign);
-        }
+        cheapMove (result->aop, 0, left->aop, 1, isRegDead (A_IDX, ic));
       if (sign)
         {
           /* Sign extend the result */
           cheapMove (ASMOP_A, 0, result->aop, 0, true);
-          emit3 (A_RLC, ASMOP_A, 0);
+          emit3 (A_RLCA, 0, 0);
           emit3 (A_SBC, ASMOP_A, ASMOP_A);
           cheapMove (result->aop, 1, ASMOP_A, 0, true);
         }
       else
         cheapMove (result->aop, 1, ASMOP_ZERO, 0, true);
     }
-  /*  0 <= shCount <= 7 */
   else
     shiftR2Left2Result (ic, left, LSB, result, LSB, shCount, sign);
 }
@@ -9836,7 +12394,7 @@
 static void
 genRightShiftLiteral (operand * left, operand * right, operand * result, const iCode *ic, int sign)
 {
-  unsigned int shCount = (unsigned int) ulFromVal (AOP (right)->aopu.aop_lit);
+  unsigned int shCount = (unsigned int) ulFromVal (right->aop->aopu.aop_lit);
   unsigned int size;
 
   freeAsmop (right, NULL);
@@ -9854,13 +12412,13 @@
       if (!SPEC_USIGN (getSpec (operandType (left))))
         {
           cheapMove (ASMOP_A, 0, left->aop, 0, true);
-          emit3 (A_RLC, ASMOP_A, 0);
+          emit3 (A_RLCA, 0, 0);
           emit3 (A_SBC, ASMOP_A, ASMOP_A);
           while (size--)
             cheapMove (result->aop, size, ASMOP_A, 0, true);
         }
       else
-        genMove (result->aop, ASMOP_ZERO, !bitVectBitValue (ic->rSurv, A_IDX), isPairDead (PAIR_HL, ic));
+        genMove (result->aop, ASMOP_ZERO, isRegDead (A_IDX, ic), isPairDead (PAIR_HL, ic), false, true);
     }
   else
     {
@@ -9890,6 +12448,7 @@
 genRightShift (const iCode * ic)
 {
   operand *right, *left, *result;
+  asmop *shiftop;
   sym_link *retype;
   int size, offset, first = 1;
   bool is_signed;
@@ -9915,7 +12474,7 @@
 
   /* if the shift count is known then do it
      as efficiently as possible */
-  if (AOP_TYPE (right) == AOP_LIT && getSize (operandType (result)) <= 2)
+  if (right->aop->type == AOP_LIT && getSize (operandType (result)) <= 2)
     {
       genRightShiftLiteral (left, right, result, ic, is_signed);
       freeAsmop (right, NULL);
@@ -9923,43 +12482,66 @@
     }
 
   /* Useful for the case of shifting a size > 2 value by a literal */
-  shift_by_lit = AOP_TYPE (right) == AOP_LIT;
+  shift_by_lit = right->aop->type == AOP_LIT;
   if (shift_by_lit)
-    shiftcount = ulFromVal (AOP (right)->aopu.aop_lit);
+    shiftcount = ulFromVal (right->aop->aopu.aop_lit);
 
   aopOp (result, ic, FALSE, FALSE);
   aopOp (left, ic, FALSE, FALSE);
-
-  if (AOP_TYPE (right) == AOP_REG && !bitVectBitValue (ic->rSurv, AOP (right)->aopu.aop_reg[0]->rIdx) && AOP (right)->aopu.aop_reg[0]->rIdx != IYL_IDX && (sameRegs (AOP (left), AOP (result)) || AOP_TYPE (left) != AOP_REG) &&
-    (AOP_TYPE (result) != AOP_REG ||
-    AOP (result)->aopu.aop_reg[0]->rIdx != AOP (right)->aopu.aop_reg[0]->rIdx &&
-    (AOP_SIZE (result) < 2 || AOP (result)->aopu.aop_reg[1]->rIdx != AOP (right)->aopu.aop_reg[0]->rIdx &&
-    (AOP_SIZE (result) < 3 || AOP (result)->aopu.aop_reg[2]->rIdx != AOP (right)->aopu.aop_reg[0]->rIdx &&
-    (AOP_SIZE (result) < 4 || AOP (result)->aopu.aop_reg[3]->rIdx != AOP (right)->aopu.aop_reg[0]->rIdx)))))
-    countreg = AOP (right)->aopu.aop_reg[0]->rIdx;
-  else if (!IS_GB && !bitVectBitValue (ic->rSurv, B_IDX) && (sameRegs (AOP (left), AOP (result)) || AOP_TYPE (left) != AOP_REG || shift_by_lit) &&
-    (AOP_TYPE (result) != AOP_REG ||
-    AOP (result)->aopu.aop_reg[0]->rIdx != B_IDX &&
-    (AOP_SIZE (result) < 2 || AOP (result)->aopu.aop_reg[1]->rIdx != B_IDX &&
-    (AOP_SIZE (result) < 3 || AOP (result)->aopu.aop_reg[2]->rIdx != B_IDX &&
-    (AOP_SIZE (result) < 4 || AOP (result)->aopu.aop_reg[3]->rIdx != B_IDX)))))
+    
+  if (right->aop->type == AOP_REG && !bitVectBitValue (ic->rSurv, right->aop->aopu.aop_reg[0]->rIdx) && right->aop->aopu.aop_reg[0]->rIdx != IYL_IDX && (sameRegs (left->aop, result->aop) || left->aop->type != AOP_REG) &&
+    (result->aop->type != AOP_REG ||
+    result->aop->aopu.aop_reg[0]->rIdx != right->aop->aopu.aop_reg[0]->rIdx &&
+    (result->aop->size < 2 || result->aop->aopu.aop_reg[1]->rIdx != right->aop->aopu.aop_reg[0]->rIdx &&
+    (result->aop->size < 3 || result->aop->aopu.aop_reg[2]->rIdx != right->aop->aopu.aop_reg[0]->rIdx &&
+    (result->aop->size < 4 || result->aop->aopu.aop_reg[3]->rIdx != right->aop->aopu.aop_reg[0]->rIdx)))))
+    countreg = right->aop->aopu.aop_reg[0]->rIdx;
+  else if (!IS_SM83 && isRegDead (B_IDX, ic) && (sameRegs (left->aop, result->aop) || left->aop->type != AOP_REG || shift_by_lit) &&
+    (result->aop->type != AOP_REG ||
+    result->aop->aopu.aop_reg[0]->rIdx != B_IDX &&
+    (result->aop->size < 2 || result->aop->aopu.aop_reg[1]->rIdx != B_IDX &&
+    (result->aop->size < 3 || result->aop->aopu.aop_reg[2]->rIdx != B_IDX &&
+    (result->aop->size < 4 || result->aop->aopu.aop_reg[3]->rIdx != B_IDX)))))
     countreg = B_IDX;
   else
     countreg = A_IDX;
 
+  if (IS_Z80N && isRegDead (PAIR_DE, ic) &&
+    (result->aop->size == 2 && (aopInReg (result->aop, 0, DE_IDX) || aopInReg (left->aop, 0, DE_IDX)) ||
+      result->aop->size == 1 && (aopInReg (result->aop, 0, D_IDX) || aopInReg (left->aop, 0, D_IDX))) &&
+    (aopInReg (right->aop, 0, B_IDX) || countreg == B_IDX))
+    {
+      shiftop = result->aop->size == 2 ? ASMOP_DE : ASMOP_D;
+      cheapMove (ASMOP_B, 0, right->aop, 0, isRegDead (A_IDX, ic));
+      genMove (shiftop, left->aop, isRegDead (A_IDX, ic), isRegDead (HL_IDX, ic), true, true);
+      emit2 (is_signed ? "bsra de, b" : "bsrl de, b");
+      regalloc_dry_run_cost += 2;
+      goto end;
+    }
+
   if (!shift_by_lit)
     cheapMove (countreg == A_IDX ? ASMOP_A : asmopregs[countreg], 0, right->aop, 0, true);
 
   save_a = (countreg == A_IDX && !shift_by_lit) &&
-    !(AOP_TYPE (left) == AOP_REG && AOP_TYPE (result) != AOP_REG ||
-    !IS_GB && (AOP_TYPE (left) == AOP_STK && canAssignToPtr3 (result->aop) || AOP_TYPE (result) == AOP_STK && canAssignToPtr3 (left->aop)));
+    !(left->aop->type == AOP_REG && result->aop->type != AOP_REG ||
+    !IS_SM83 && (left->aop->type == AOP_STK && canAssignToPtr3 (result->aop) || result->aop->type == AOP_STK && canAssignToPtr3 (left->aop)));
 
-  /* now move the left to the result if they are not the
+  shiftop = result->aop;
+  if (result->aop->type != AOP_REG && left->aop->type == AOP_REG && result->aop->size == left->aop->size && left->aop->regs[countreg] < 0)
+    {
+      bool left_dead = true;
+      for (int i = 0; i < left->aop->size; i++)
+        left_dead &= isRegDead (left->aop->aopu.aop_reg[i]->rIdx, ic);
+      if (left_dead)
+        shiftop = left->aop;
+    }
+
+  /* now move the left to the shiftop if they are not the
      same */
-  if (!sameRegs (AOP (left), AOP (result)))
+  if (!sameRegs (shiftop, left->aop) || shiftop->type == AOP_REG)
     {
       int soffset = 0;
-      size = AOP_SIZE (result);
+      size = shiftop->size;
 
       if (!is_signed && shift_by_lit)
       {
@@ -9972,9 +12554,10 @@
       if (save_a)
         _push (PAIR_AF);
 
-      genMove_o (result->aop, 0, left->aop, soffset, size, true, isPairDead (PAIR_HL, ic));
-
-      genMove_o (result->aop, result->aop->size - byteoffset, ASMOP_ZERO, 0, byteoffset, true, false);
+      bool hl_dead = isPairDead (PAIR_HL, ic) && (countreg != L_IDX && countreg != H_IDX || shift_by_lit);
+      genMove_o (shiftop, 0, left->aop, soffset, size, true, hl_dead, false, true, true);
+      hl_dead &= (shiftop->regs[L_IDX] < 0 || shiftop->regs[L_IDX] >= size) && (shiftop->regs[H_IDX] < 0 || shiftop->regs[H_IDX] >= size);
+      genMove_o (shiftop, shiftop->size - byteoffset, ASMOP_ZERO, 0, byteoffset, true, hl_dead, false, true, true);
 
       if (save_a)
         _pop (PAIR_AF);
@@ -9988,7 +12571,7 @@
       tlbl = newiTempLabel (NULL);
       tlbl1 = newiTempLabel (NULL);
     }
-  size = AOP_SIZE (result);
+  size = result->aop->size;
   offset = size - 1;
 
   if (shift_by_zero)
@@ -10007,22 +12590,22 @@
       regalloc_dry_run_cost += 3;
     }
   if (!shift_by_one && !regalloc_dry_run)
-    IS_GB ? emitLabelSpill (tlbl) : emitLabel (tlbl);
+    IS_SM83 ? emitLabelSpill (tlbl) : emitLabel (tlbl);
 
-  if (requiresHL (AOP (result)))
+  if (!shift_by_one && requiresHL (shiftop))
     spillPair (PAIR_HL);
 
   while (size)
-    { 
-      if (IS_RAB && !(is_signed && first) && size >= 2 && byteoffset < 2 && AOP_TYPE (result) == AOP_REG &&
-        (getPartPairId (AOP (result), offset - 1) == PAIR_HL || getPartPairId (AOP (result), offset - 1) == PAIR_DE))
+    {
+      if (IS_RAB && !(is_signed && first) && size >= 2 && byteoffset < 2 && shiftop->type == AOP_REG &&
+        (getPartPairId (shiftop, offset - 1) == PAIR_HL || getPartPairId (shiftop, offset - 1) == PAIR_DE))
         {
           if (first)
             {
               emit3 (A_CP, ASMOP_A, ASMOP_A);
               first = 0;
             }
-          emit2 (AOP (result)->aopu.aop_reg[offset - 1]->rIdx == L_IDX ? "rr hl" : "rr de");
+          emit2 (shiftop->aopu.aop_reg[offset - 1]->rIdx == L_IDX ? "rr hl" : "rr de");
           regalloc_dry_run_cost++;
           size -= 2, offset -= 2;
         }
@@ -10030,13 +12613,13 @@
         size--, offset--;
       else if (first)
         {
-          emit3_o (is_signed ? A_SRA : A_SRL, AOP (result), offset, 0, 0);
+          emit3_o (is_signed ? A_SRA : A_SRL, shiftop, offset, 0, 0);
           first = 0;
           size--, offset--;
         }
       else
         {
-          emit3_o (A_RR, AOP (result), offset, 0, 0);
+          emit3_o (A_RR, shiftop, offset, 0, 0);
           size--, offset--;
         }
     }
@@ -10045,7 +12628,7 @@
     {
       if (!regalloc_dry_run)
         emitLabel (tlbl1);
-      if (!IS_GB && countreg == B_IDX)
+      if (!IS_SM83 && countreg == B_IDX)
         {
           if (!regalloc_dry_run)
             emit2 ("djnz !tlabel", labelKey2num (tlbl->key));
@@ -10061,9 +12644,11 @@
     }
 
 end:
-  if (!shift_by_lit && requiresHL (AOP (result))) // Shift by 0 skips over hl adjustments.
+  if (!shift_by_lit && requiresHL (shiftop)) // Shift by 0 skips over hl adjustments.
     spillPair (PAIR_HL);
 
+  genMove_o (result->aop, 0, shiftop, 0, result->aop->size, isRegDead (A_IDX, ic), isPairDead (PAIR_HL, ic), isPairDead (PAIR_DE, ic), true, true);
+
   freeAsmop (left, NULL);
   freeAsmop (right, NULL);
   freeAsmop (result, NULL);
@@ -10071,7 +12656,7 @@
 
 /*-----------------------------------------------------------------*/
 /* unpackMaskA - generate masking code for unpacking last byte     */
-/* of bitfiled. And mask for unsigned, sign extension for signed.  */
+/* of bitfield. And mask for unsigned, sign extension for signed.  */
 /*-----------------------------------------------------------------*/
 static void
 unpackMaskA(sym_link *type, int len)
@@ -10127,37 +12712,36 @@
   /* If the bit-field length is less than a byte */
   if (blen < 8)
     {
-      emit2 ("ld a, !*pair", _pairs[pair].name);
+      emit2 ("ld a, !mems", _pairs[pair].name);
       regalloc_dry_run_cost += (pair == PAIR_IX || pair == PAIR_IY) ? 3 : 1;
       AccRol (8 - bstr);
       unpackMaskA (etype, blen);
-      cheapMove (AOP (result), offset++, ASMOP_A, 0, true);
+      cheapMove (result->aop, offset++, ASMOP_A, 0, true);
       goto finish;
     }
 
   /* TODO: what if pair == PAIR_DE ? */
-  if (getPairId (AOP (result)) == PAIR_HL ||
-      AOP_TYPE (result) == AOP_REG && rsize >= 2 && (AOP (result)->aopu.aop_reg[0]->rIdx == L_IDX
-          || AOP (result)->aopu.aop_reg[0]->rIdx == H_IDX))
+  if (getPairId (result->aop) == PAIR_HL ||
+      result->aop->type == AOP_REG && rsize >= 2 && (result->aop->aopu.aop_reg[0]->rIdx == L_IDX
+          || result->aop->aopu.aop_reg[0]->rIdx == H_IDX))
     {
       wassertl (rsize == 2, "HL must be of size 2");
-      emit2 ("ld a, !*hl");
-      emit2 ("inc hl");
-      if (AOP_TYPE (result) != AOP_REG || AOP (result)->aopu.aop_reg[0]->rIdx != H_IDX)
+      emit2 ("!ldahli");
+      if (result->aop->type != AOP_REG || result->aop->aopu.aop_reg[0]->rIdx != H_IDX)
         {
           emit2 ("ld h, !*hl");
-          cheapMove (AOP (result), offset++, ASMOP_A, 0, true);
+          cheapMove (result->aop, offset++, ASMOP_A, 0, true);
           emit2 ("ld a, h");
         }
       else
         {
           emit2 ("ld l, !*hl");
-          cheapMove (AOP (result), offset++, ASMOP_A, 0, true);
+          cheapMove (result->aop, offset++, ASMOP_A, 0, true);
           emit2 ("ld a, l");
         }
       regalloc_dry_run_cost += 5;
       unpackMaskA (etype, blen - 8);
-      cheapMove (AOP (result), offset++, ASMOP_A, 0, true);
+      cheapMove (result->aop, offset++, ASMOP_A, 0, true);
       regalloc_dry_run_cost += 1;
       spillPair (PAIR_HL);
       return;
@@ -10167,9 +12751,9 @@
      but the partial byte at the end.  */
   for (rlen = blen; rlen >= 8; rlen -= 8)
     {
-      emit2 ("ld a, !*pair", _pairs[pair].name);
+      emit2 ("ld a, !mems", _pairs[pair].name);
       regalloc_dry_run_cost += 1;
-      cheapMove (AOP (result), offset++, ASMOP_A, 0, true);
+      cheapMove (result->aop, offset++, ASMOP_A, 0, true);
       if (rlen > 8)
         {
           emit2 ("inc %s", _pairs[pair].name);
@@ -10182,10 +12766,10 @@
   /* Handle the partial byte at the end */
   if (rlen)
     {
-      emit2 ("ld a, !*pair", _pairs[pair].name);
+      emit2 ("ld a, !mems", _pairs[pair].name);
       regalloc_dry_run_cost++;
       unpackMaskA (etype, rlen);
-      cheapMove (AOP (result), offset++, ASMOP_A, 0, true);
+      cheapMove (result->aop, offset++, ASMOP_A, 0, true);
     }
 
 finish:
@@ -10213,7 +12797,7 @@
         }
       rsize -= offset;
       while (rsize--)
-        cheapMove (AOP (result), offset++, source, 0, true);
+        cheapMove (result->aop, offset++, source, 0, true);
     }
 }
 
@@ -10225,11 +12809,11 @@
     {
       if (!regalloc_dry_run)
         aopPut (aop, "!*hl", offset);
-      regalloc_dry_run_cost += ld_cost (aop, ASMOP_A);
+      regalloc_dry_run_cost += ld_cost (aop, 0, ASMOP_A, 0);
     }
   else
     {
-      emit2 ("ld a, !*pair", _pairs[pair].name);
+      emit2 ("ld a, !mems", _pairs[pair].name);
       regalloc_dry_run_cost += 1;
       cheapMove (aop, offset, ASMOP_A, 0, true);
     }
@@ -10261,6 +12845,22 @@
     }
 }
 
+/*------------------------------------------------------------------*/
+/* init_stackop - initalize asmop for stack location                */
+/*------------------------------------------------------------------*/
+static void 
+init_stackop (asmop *stackop, int size, long int stk_off)
+{
+  stackop->size = size;
+  memset (stackop->regs, -1, 9);
+  stackop->aopu.aop_stk = stk_off;
+
+  if (!IS_SM83 && (_G.omitFramePtr || stk_off < INT8MIN || stk_off > (int) (INT8MAX - size)))
+    stackop->type = AOP_EXSTK;
+  else
+    stackop->type = AOP_STK;
+}
+
 /*-----------------------------------------------------------------*/
 /* genPointerGet - generate code for pointer get                   */
 /*-----------------------------------------------------------------*/
@@ -10273,7 +12873,7 @@
   sym_link *retype;
   bool pushed_pair = FALSE;
   bool pushed_a = FALSE;
-  bool surviving_a = !options.oldralloc && bitVectBitValue (ic->rSurv, A_IDX);
+  bool surviving_a = !isRegDead (A_IDX, ic);
   bool rightval_in_range;
 
   left = IC_LEFT (ic);
@@ -10283,88 +12883,103 @@
 
   aopOp (left, ic, FALSE, FALSE);
   aopOp (result, ic, FALSE, FALSE);
-  size = AOP_SIZE (result);
+  size = result->aop->size;
 
   /* Historically GET_VALUE_AT_ADDRESS didn't have a right operand */
   wassertl (right, "GET_VALUE_AT_ADDRESS without right operand");
   wassertl (IS_OP_LITERAL (IC_RIGHT (ic)), "GET_VALUE_AT_ADDRESS with non-literal right operand");
   rightval = (int)operandLitValue (right);
   rightval_in_range = (rightval >= -128 && rightval + size - 1 < 127);
-  if (IS_GB)
-    wassert (!rightval);
 
-  if (IS_GB && left->aop->type == AOP_STK) // Try to avoid (hl) to hl copy, which requires 3 instructions and free a.
+  if (IS_SM83 && left->aop->type == AOP_STK) // Try to avoid (hl) to hl copy, which requires 3 instructions and free a.
     pair = PAIR_DE;
-  if ((IS_GB || IY_RESERVED) && requiresHL (AOP (result)) && size > 1 && AOP_TYPE (result) != AOP_REG)
+  if ((IS_SM83 || IY_RESERVED) && requiresHL (result->aop) && size > 1 && result->aop->type != AOP_REG)
     pair = PAIR_DE;
 
-  if (AOP_TYPE (left) == AOP_IMMD && size == 1 && aopInReg (result->aop, 0, A_IDX) && !IS_BITVAR (retype))
+  if (IS_SM83 && size == 1 && left->aop->type == AOP_LIT && (((unsigned long)(operandLitValue (left) + rightval) & 0xff00) == 0xff00) && isRegDead (A_IDX, ic) && !IS_BITVAR (retype)) // SM83 has special instructions for address range 0xff00 - 0xffff.
+    {
+      emit2 ("ldh a, !mems", aopGetLitWordLong (left->aop, rightval, true));
+      cost (2, 12);
+      cheapMove (result->aop, 0, ASMOP_A, 0, true);
+      goto release;
+    }
+  if ((left->aop->type == AOP_IMMD || left->aop->type == AOP_LIT && !rightval) && size == 1 && aopInReg (result->aop, 0, A_IDX) && !IS_BITVAR (retype))
     {
-      emit2 ("ld a, (%s)", aopGetLitWordLong (AOP (left), rightval, TRUE));
+      emit2 ("ld a, !mems", aopGetLitWordLong (left->aop, rightval, true));
       regalloc_dry_run_cost += 3;
       goto release;
     }
-  else if (!IS_GB && AOP_TYPE (left) == AOP_IMMD && isPair (AOP (result)) && !IS_BITVAR (retype))
+  else if (!IS_SM83 && (left->aop->type == AOP_IMMD || left->aop->type == AOP_LIT && !rightval) && isPair (result->aop) && !IS_BITVAR (retype))
     {
-      PAIR_ID pair = getPairId (AOP (result));
-      emit2 ("ld %s, (%s)", _pairs[pair].name, aopGetLitWordLong (AOP (left), rightval, TRUE));
+      PAIR_ID pair = getPairId (result->aop);
+      emit2 ("ld %s, !mems", _pairs[pair].name, aopGetLitWordLong (left->aop, rightval, TRUE));
       regalloc_dry_run_cost += (pair == PAIR_HL ? 3 : 4);
       goto release;
     }
-  else if (!IS_GB && AOP_TYPE (left) == AOP_IMMD && getPartPairId (AOP (result), 0) != PAIR_INVALID && getPartPairId (AOP (result), 2) != PAIR_INVALID)
-   {
+  else if (!IS_SM83 && (left->aop->type == AOP_IMMD) && getPartPairId (result->aop, 0) != PAIR_INVALID && getPartPairId (result->aop, 2) != PAIR_INVALID)
+    {
       PAIR_ID pair;
-      pair = getPartPairId (AOP (result), 0);
-      emit2 ("ld %s, (%s)", _pairs[pair].name, aopGetLitWordLong (AOP (left), rightval, TRUE));
+      pair = getPartPairId (result->aop, 0);
+      emit2 ("ld %s, !mems", _pairs[pair].name, aopGetLitWordLong (left->aop, rightval, TRUE));
       regalloc_dry_run_cost += (pair == PAIR_HL ? 3 : 4);
-      pair = getPartPairId (AOP (result), 2);
-      emit2 ("ld %s, (%s)", _pairs[pair].name, aopGetLitWordLong (AOP (left), rightval + 2, TRUE));
+      pair = getPartPairId (result->aop, 2);
+      emit2 ("ld %s, !mems", _pairs[pair].name, aopGetLitWordLong (left->aop, rightval + 2, TRUE));
       regalloc_dry_run_cost += (pair == PAIR_HL ? 3 : 4);
       goto release;
-   }
+    }
+  else if (left->aop->type == AOP_STL && !IS_BITVAR (retype) && size <= 4)
+    {
+      struct asmop saop;
+      init_stackop (&saop, size, left->aop->aopu.aop_stk + rightval);
+      genMove (result->aop, &saop, !surviving_a, isPairDead(PAIR_HL, ic), isPairDead(PAIR_DE, ic), isPairDead(PAIR_IY, ic));
+      goto release;
+    }
+
+  if (IS_SM83)
+    wassert (!rightval);
 
-  if (isPair (AOP (left)) && size == 1 && !IS_BITVAR (retype) && !rightval)
+  if (isPair (left->aop) && size == 1 && !IS_BITVAR (retype) && !rightval)
     {
       /* Just do it */
-      if (isPtrPair (AOP (left)))
+      if ((getPairId (left->aop) == PAIR_HL || getPairId (left->aop) == PAIR_IY) && result->aop->type == AOP_REG)
         {
           if (!regalloc_dry_run)        // Todo: More exact cost.
             {
               struct dbuf_s dbuf;
 
               dbuf_init (&dbuf, 128);
-              dbuf_tprintf (&dbuf, "!*pair", getPairName (AOP (left)));
-              aopPut (AOP (result), dbuf_c_str (&dbuf), 0);
+              dbuf_tprintf (&dbuf, "!mems", getPairName (left->aop));
+              aopPut (result->aop, dbuf_c_str (&dbuf), 0);
               dbuf_destroy (&dbuf);
             }
-          regalloc_dry_run_cost += ld_cost (AOP (result), ASMOP_A);
+          regalloc_dry_run_cost += ld_cost (result->aop, 0, ASMOP_A, 0);
         }
       else
         {
           if (surviving_a && !pushed_a)
             _push (PAIR_AF), pushed_a = TRUE;
-          emit2 ("ld a, !*pair", getPairName (AOP (left)));
-          regalloc_dry_run_cost += (getPairId (AOP (left)) == PAIR_IY ? 3 : 1);
-          cheapMove (AOP (result), 0, ASMOP_A, 0, true);
+          emit2 ("ld a, !mems", getPairName (left->aop));
+          regalloc_dry_run_cost += (getPairId (left->aop) == PAIR_IY ? 3 : 1);
+          genMove(result->aop, ASMOP_A, true, isPairDead(PAIR_HL, ic), isPairDead(PAIR_DE, ic), true);
         }
 
       goto release;
     }
 
-  if (getPairId (AOP (left)) == PAIR_IY && !IS_BITVAR (retype) && rightval_in_range)
+  if (getPairId (left->aop) == PAIR_IY && !IS_BITVAR (retype) && rightval_in_range)
     {
       offset = 0;
 
-      if ((IS_RAB || IS_TLCS90) && getPartPairId (AOP (result), 0) == PAIR_HL)
+      if ((IS_RAB || IS_TLCS90) && getPartPairId (result->aop, 0) == PAIR_HL)
         {
           emit2 ("ld hl, %d (iy)", rightval);
           regalloc_dry_run_cost += 3;
           offset = 2;
           size -= 2;
         }
-      else if (IS_EZ80_Z80 && getPartPairId (AOP (result), 0) != PAIR_INVALID)
+      else if (IS_EZ80_Z80 && getPartPairId (result->aop, 0) != PAIR_INVALID)
         {
-          emit2 ("ld %s, %d (iy)", _pairs[getPartPairId (AOP (result), 0)].name, rightval);
+          emit2 ("ld %s, %d (iy)", _pairs[getPartPairId (result->aop, 0)].name, rightval);
           regalloc_dry_run_cost += 3;
           offset = 2;
           size -= 2;
@@ -10385,10 +13000,10 @@
 
               dbuf_init (&dbuf, 128);
               dbuf_tprintf (&dbuf, "!*iyx", rightval + offset);
-              aopPut (AOP (result), dbuf_c_str (&dbuf), offset);
+              aopPut (result->aop, dbuf_c_str (&dbuf), offset);
               dbuf_destroy (&dbuf);
             }
-          regalloc_dry_run_cost += ld_cost (AOP (result), ASMOP_A) + 2; // Todo: More exact cost.
+          regalloc_dry_run_cost += ld_cost (result->aop, offset, ASMOP_A, 0) + 2; // Todo: More exact cost.
           offset++;
         }
 
@@ -10396,7 +13011,7 @@
     }
 
   /* Using ldir is cheapest for large memory-to-memory transfers. */
-  if (!IS_GB && (AOP_TYPE (result) == AOP_STK || AOP_TYPE (result) == AOP_EXSTK) && size > 2 && (!rightval || AOP_TYPE (left) == AOP_IMMD))
+  if (!IS_SM83 && !IS_R2K && !IS_R2KA && (result->aop->type == AOP_STK || result->aop->type == AOP_EXSTK) && size > 2)
     {
       int fp_offset, sp_offset;
 
@@ -10407,22 +13022,60 @@
       if(!isPairDead (PAIR_BC, ic))
         _push (PAIR_BC);
 
-      if (!rightval)
-        fetchPair (PAIR_DE, AOP (left));
-      else
+      fp_offset = result->aop->aopu.aop_stk + (result->aop->aopu.aop_stk > 0 ? _G.stack.param_offset : 0);
+      sp_offset = fp_offset + _G.stack.pushed + _G.stack.offset;
+
+      if (IS_EZ80_Z80 && !_G.omitFramePtr && fp_offset >= -128 && fp_offset < 128)
         {
-          emit2 ("ld de, %s", aopGetLitWordLong (AOP (left), rightval, TRUE));
+          if (left->aop->type == AOP_IMMD)
+            {
+              emit2 ("ld hl, %s", aopGetLitWordLong (left->aop, rightval, TRUE));
+              regalloc_dry_run_cost += 3;
+            }
+          else
+            fetchPair (PAIR_HL, left->aop);
+          emit2 ("lea de, ix, !immed%d", fp_offset);
           regalloc_dry_run_cost += 3;
         }
+      else
+        {
+          if (left->aop->type == AOP_IMMD)
+            {
+              emit2 ("ld de, %s", aopGetLitWordLong (left->aop, rightval, TRUE));
+              regalloc_dry_run_cost += 3;
+            }
+          else
+            genMove (ASMOP_DE, left->aop, isRegDead (A_IDX, ic), true, true, true);
+          emit2 ("!ldahlsp", sp_offset);
+          emit2 ("ex de, hl");
+          regalloc_dry_run_cost += 5;
+        }
+
+      if (rightval && left->aop->type != AOP_IMMD)
+          if (abs(rightval) < 4)
+            {
+              for(;rightval > 0; rightval--)
+                {
+                  emit2 ("inc hl");
+                  regalloc_dry_run_cost++;
+                }
+              for(;rightval < 0; rightval++)
+                {
+                  emit2 ("inc hl");
+                  regalloc_dry_run_cost++;
+                }
+             }
+          else
+            {
+              emit2 ("ld bc, !immedword", rightval);
+              emit2 ("add hl, bc");
+              rightval = 0;
+              regalloc_dry_run_cost += 4;
+            }
 
-      fp_offset = AOP (result)->aopu.aop_stk + (AOP (result)->aopu.aop_stk > 0 ? _G.stack.param_offset : 0);
-      sp_offset = fp_offset + _G.stack.pushed + _G.stack.offset;
-      emit2 ("ld hl, !immedword", sp_offset);
-      emit2 ("add hl, sp");
-      emit2 ("ex de, hl");
       emit2 ("ld bc, !immedword", size);
       emit2 ("ldir");
-      regalloc_dry_run_cost += 10;
+      regalloc_dry_run_cost += 5;
       spillPair (PAIR_HL);
       spillPair (PAIR_DE);
       spillPair (PAIR_BC);
@@ -10439,24 +13092,43 @@
 
   extrapair = isPairDead (PAIR_DE, ic) ? PAIR_DE : PAIR_BC;
 
+  if (!surviving_a && (getPairId (left->aop) == PAIR_BC || getPairId (left->aop) == PAIR_DE) && isPairDead (getPairId (left->aop), ic) && abs(rightval) <= 2 && !IS_BITVAR (retype) && size < 2) // Use inc ss (size < 2 condition to avoid overwriting pair with result)
+    pair = getPairId (left->aop);
+
   /* For now we always load into temp pair */
   /* if this is rematerializable */
-  if (!IS_GB && (getPairId (AOP (left)) == PAIR_BC || getPairId (AOP (left)) == PAIR_DE) && AOP_TYPE (result) == AOP_STK && !rightval
-      || getPairId (AOP (left)) == PAIR_IY && SPEC_BLEN (getSpec (operandType (result))) < 8 && rightval_in_range)
-    pair = getPairId (AOP (left));
+  if (!IS_SM83 && (getPairId (left->aop) == PAIR_BC || getPairId (left->aop) == PAIR_DE) && result->aop->type == AOP_STK && !rightval
+      || getPairId (left->aop) == PAIR_IY && SPEC_BLEN (getSpec (operandType (result))) < 8 && rightval_in_range)
+    pair = getPairId (left->aop);
   else
     {
-      if (!isPairDead (pair, ic) && size > 1 && (getPairId (AOP (left)) != pair || rightval || IS_BITVAR (retype) || size > 2)) // For simple cases, restoring via dec is cheaper than push / pop.
+      if (!isPairDead (pair, ic) && size > 1 && (getPairId (left->aop) != pair || rightval || IS_BITVAR (retype) || size > 2)) // For simple cases, restoring via dec is cheaper than push / pop.
         _push (pair), pushed_pair = TRUE;
-      if (AOP_TYPE(left) == AOP_IMMD)
+      if (left->aop->type == AOP_IMMD)
         {
-          emit2 ("ld %s, %s", _pairs[pair].name, aopGetLitWordLong (AOP (left), rightval, TRUE));
-          spillPair (pair);
+          emit2 ("ld %s, %s", _pairs[pair].name, aopGetLitWordLong (left->aop, rightval, TRUE));
           regalloc_dry_run_cost += 3;
+          spillPair (pair);
+          rightval = 0;
+        }
+      else if (pair == PAIR_HL && rightval > 2 && (getPairId (left->aop) == PAIR_BC || getPairId (left->aop) == PAIR_DE)) // Cheaper than moving to hl followed by offset adjustment.
+        {
+          emit2 ("ld hl, !immed%d", rightval);
+          emit2 ("add hl, %s", _pairs[getPairId (left->aop)].name);
+          regalloc_dry_run_cost += 4;
+          spillPair (pair);
+          rightval = 0;
+        }
+      else if (pair == PAIR_HL && left->aop->type == AOP_STL)
+        {
+          emit2 ("ld hl, !immed%d", spOffset (left->aop->aopu.aop_stk) + rightval);
+          emit2 ("add hl, sp");
+          regalloc_dry_run_cost += 4;
+          spillPair (pair);
           rightval = 0;
         }
       else
-        fetchPair (pair, AOP (left));
+        fetchPair (pair, left->aop);
     }
 
   /* if bit then unpack */
@@ -10470,32 +13142,31 @@
       goto release;
     }
 
- if (isPair (AOP (result)) && IS_EZ80_Z80 && getPairId (AOP (left)) == PAIR_HL && !IS_BITVAR (retype) && !rightval)
+ if (isPair (result->aop) && IS_EZ80_Z80 && getPairId (left->aop) == PAIR_HL && !IS_BITVAR (retype) && !rightval)
    {
-     emit2 ("ld %s, (hl)", _pairs[getPairId (AOP (result))].name);
+     emit2 ("ld %s, !*hl", _pairs[getPairId (result->aop)].name);
      regalloc_dry_run_cost += 2;
      goto release;
    }
- else if (getPairId (AOP (result)) == PAIR_HL || size == 2 && (aopInReg (result->aop, 0, L_IDX) || aopInReg (result->aop, 0, H_IDX)))
+ else if (pair == PAIR_HL && (getPairId (result->aop) == PAIR_HL || size == 2 && (aopInReg (result->aop, 0, L_IDX) || aopInReg (result->aop, 0, H_IDX))))
     {
       wassertl (size == 2, "HL must be of size 2");
-      if (IS_RAB && getPairId (AOP (result)) == PAIR_HL && rightval_in_range)
+      if (IS_RAB && getPairId (result->aop) == PAIR_HL && rightval_in_range)
         {
-          emit2 ("ld hl, %d (hl)", rightval);
+          emit2 ("ld hl, %d !*hl", rightval);
           regalloc_dry_run_cost += 3;
         }
-      else if (IS_EZ80_Z80 && getPairId (AOP (result)) == PAIR_HL && !rightval)
+      else if (IS_EZ80_Z80 && getPairId (result->aop) == PAIR_HL && !rightval)
         {
-          emit2 ("ld hl, (hl)");
+          emit2 ("ld hl, !*hl");
           regalloc_dry_run_cost += 2;
         }
       else if (aopInReg (result->aop, 1, A_IDX))
         {
           offsetPair (pair, extrapair, !isPairDead (extrapair, ic), rightval + 1);
-          emit2 ("ld a, !*hl");
-          emit2 ("dec hl");
+          emit2 ("!ldahld");
           if (!regalloc_dry_run)
-            aopPut (AOP (result), "!*hl", 0);
+            aopPut (result->aop, "!*hl", 0);
           regalloc_dry_run_cost += 3;
         }
       else
@@ -10503,10 +13174,9 @@
           if (surviving_a && !pushed_a)
             _push (PAIR_AF), pushed_a = TRUE;
           offsetPair (pair, extrapair, !isPairDead (extrapair, ic), rightval);
-          emit2 ("ld a, !*hl");
-          emit2 ("inc hl");
+          emit2 ("!ldahli");
           if (!regalloc_dry_run)
-            aopPut (AOP (result), "!*hl", 1);
+            aopPut (result->aop, "!*hl", 1);
           regalloc_dry_run_cost += 3;
           cheapMove (result->aop, 0, ASMOP_A, 0, true);
         }
@@ -10517,25 +13187,25 @@
   offsetPair (pair, extrapair, !isPairDead (extrapair, ic), rightval);
 
   if (pair == PAIR_HL
-           || (!IS_GB && (getPairId (AOP (left)) == PAIR_BC || getPairId (AOP (left)) == PAIR_DE)
-               && AOP_TYPE (result) == AOP_STK))
+           || (!IS_SM83 && (getPairId (left->aop) == PAIR_BC || getPairId (left->aop) == PAIR_DE)
+               && result->aop->type == AOP_STK))
     {
-      size = AOP_SIZE (result);
+      size = result->aop->size;
       offset = 0;
       int last_offset = 0;
 
       /* might use ld a,(hl) followed by ld d (iy),a */
-      if ((AOP_TYPE (result) == AOP_EXSTK || AOP_TYPE (result) == AOP_STK) && surviving_a && !pushed_a)
+      if ((result->aop->type == AOP_EXSTK || result->aop->type == AOP_STK) && surviving_a && !pushed_a)
         _push (PAIR_AF), pushed_a = TRUE;
 
-      if (size >= 2 && pair == PAIR_HL && AOP_TYPE (result) == AOP_REG)
+      if (size >= 2 && pair == PAIR_HL && result->aop->type == AOP_REG)
         {
           int i, l = -10, h = -10, r;
           for (i = 0; i < size; i++)
             {
-              if (AOP (result)->aopu.aop_reg[i]->rIdx == L_IDX)
+              if (result->aop->aopu.aop_reg[i]->rIdx == L_IDX)
                 l = i;
-              else if (AOP (result)->aopu.aop_reg[i]->rIdx == H_IDX)
+              else if (result->aop->aopu.aop_reg[i]->rIdx == H_IDX)
                 h = i;
             }
 
@@ -10546,7 +13216,7 @@
               while (offset < size)
                 {
                   if (offset != r)
-                    _moveFrom_tpair_ (AOP (result), offset, pair);
+                    _moveFrom_tpair_ (result->aop, offset, pair);
 
                   if (offset < size)
                     {
@@ -10563,7 +13233,7 @@
                   regalloc_dry_run_cost += 1;
                 }
 
-              _moveFrom_tpair_ (AOP (result), r, pair);
+              _moveFrom_tpair_ (result->aop, r, pair);
 
               // No fixup since result uses HL.
               spillPair (pair);
@@ -10591,7 +13261,7 @@
                     }
 
                   if (offset != l && offset != h)
-                    _moveFrom_tpair_ (AOP (result), offset, pair);
+                    _moveFrom_tpair_ (result->aop, offset, pair);
                   offset++;
 
                   if (offset < size)
@@ -10618,7 +13288,7 @@
                   emit2 ("dec %s", _pairs[pair].name);
                   regalloc_dry_run_cost += 1;
                 }
-              _moveFrom_tpair_ (AOP (result), r, pair);
+              _moveFrom_tpair_ (result->aop, r, pair);
 
               r = (l > h ? l : h);
               cheapMove (result->aop, r, ASMOP_A, 0, true);
@@ -10648,7 +13318,7 @@
               continue;
             }
 
-          _moveFrom_tpair_ (AOP (result), offset++, pair);
+          _moveFrom_tpair_ (result->aop, offset++, pair);
 
           if (offset < size)
             {
@@ -10658,19 +13328,19 @@
             }
         }
       /* Fixup HL back down */
-      if (getPairId (AOP (left)) == pair && !isPairDead (pair, ic) && !pushed_pair)
+      if (getPairId (left->aop) == pair && !isPairDead (pair, ic) && !pushed_pair)
         while (last_offset --> 0)
           {
             emit2 ("dec %s", _pairs[pair].name);
             regalloc_dry_run_cost += 1;
             _G.pairs[pair].offset--;
           }
-       else if (rightval || AOP_SIZE (result))
+       else if (rightval || result->aop->size)
          spillPair (pair);
     }
   else
     {
-      size = AOP_SIZE (result);
+      size = result->aop->size;
       offset = 0;
 
       for (offset = 0; offset < size;)
@@ -10679,15 +13349,15 @@
             _push (PAIR_AF), pushed_a = TRUE;
 
           /* PENDING: make this better */
-          if ((pair == PAIR_HL) && AOP_TYPE (result) == AOP_REG)
+          if ((pair == PAIR_HL) && result->aop->type == AOP_REG)
             {
               if (!regalloc_dry_run)
-                aopPut (AOP (result), "!*hl", offset++);
-              regalloc_dry_run_cost += ld_cost (AOP (result), ASMOP_A);
+                aopPut (result->aop, "!*hl", offset++);
+              regalloc_dry_run_cost += ld_cost (result->aop, 0, ASMOP_A, 0);
             }
           else
             {
-              emit2 ("ld a,!*pair", _pairs[pair].name);
+              emit2 ("ld a, !mems", _pairs[pair].name);
               regalloc_dry_run_cost += 1;
               cheapMove (result->aop, offset++, ASMOP_A, 0, true);
             }
@@ -10698,7 +13368,14 @@
               _G.pairs[pair].offset++;
             }
         }
-      if (rightval || AOP_SIZE (result))
+      if (!isPairDead (pair, ic))
+        while (offset --> 1)
+          {
+            emit2 ("dec %s", _pairs[pair].name);
+            regalloc_dry_run_cost += 1;
+            _G.pairs[pair].offset--;
+          }
+      else if (rightval || result->aop->size)
          spillPair (pair);
     }
 
@@ -10748,20 +13425,20 @@
     {
       mask = ((unsigned char) (0xFF << (blen + bstr)) | (unsigned char) (0xFF >> (8 - bstr)));
 
-      if (AOP_TYPE (right) == AOP_LIT && blen == 1 && (pair == PAIR_HL || pair == PAIR_IX || pair == PAIR_IY))
+      if (right->aop->type == AOP_LIT && blen == 1 && (pair == PAIR_HL || pair == PAIR_IX || pair == PAIR_IY))
         {
-          litval = (int) ulFromVal (AOP (right)->aopu.aop_lit);
-          emit2 (litval & 1 ? "set %d, !*pair" : "res %d, !*pair", bstr, _pairs[pair].name);
-          regalloc_dry_run_cost = (pair == PAIR_IX || pair == PAIR_IY) ? 4 : 2;
+          litval = (int) ulFromVal (right->aop->aopu.aop_lit);
+          emit2 (litval & 1 ? "set %d, !mems" : "res %d, !mems", bstr, _pairs[pair].name);
+          regalloc_dry_run_cost += (pair == PAIR_IX || pair == PAIR_IY) ? 4 : 2;
           return;
         }
-      else if (AOP_TYPE (right) == AOP_LIT)
+      else if (right->aop->type == AOP_LIT)
         {
           /* Case with a bit-field length <8 and literal source */
-          litval = (int) ulFromVal (AOP (right)->aopu.aop_lit);
+          litval = (int) ulFromVal (right->aop->aopu.aop_lit);
           litval <<= bstr;
           litval &= (~mask) & 0xff;
-          emit2 ("ld a, !*pair", _pairs[pair].name);
+          emit2 ("ld a, !mems", _pairs[pair].name);
           regalloc_dry_run_cost += (pair == PAIR_IX || pair == PAIR_IY) ? 3 : 1;
           if ((mask | litval) != 0xff)
             {
@@ -10773,23 +13450,21 @@
               emit2 ("or a, !immedbyte", litval);
               regalloc_dry_run_cost += 1;
             }
-          emit2 ("ld !*pair,a", _pairs[pair].name);
+          emit2 ("ld !mems, a", _pairs[pair].name);
           regalloc_dry_run_cost += (pair == PAIR_IX || pair == PAIR_IY) ? 3 : 1;
           return;
         }
-      else if (blen == 4 && bstr % 4 == 0 && pair == PAIR_HL && !aopInReg (right->aop, 0, A_IDX) && !requiresHL (right->aop) && (IS_Z80 || IS_Z180 || IS_EZ80_Z80))
+      else if (blen == 4 && bstr % 4 == 0 && pair == PAIR_HL && !aopInReg (right->aop, 0, A_IDX) && !requiresHL (right->aop) && (IS_Z80 || IS_Z180 || IS_EZ80_Z80 || IS_Z80N))
         {
-          emit2 (bstr ? "rld" : "rrd");
-          regalloc_dry_run_cost += 2;
-          cheapMove (ASMOP_A, 0, AOP (right), 0, true);
-          emit2 (bstr ? "rrd" : "rld");
-          regalloc_dry_run_cost += 2;
+          emit3 ((bstr ? A_RLD : A_RRD), 0, 0);
+          cheapMove (ASMOP_A, 0, right->aop, 0, true);
+          emit3 ((bstr ? A_RRD : A_RLD), 0, 0);
           return;
         }
       else
         {
           /* Case with a bit-field length <8 and arbitrary source */
-          cheapMove (ASMOP_A, 0, AOP (right), 0, true);
+          cheapMove (ASMOP_A, 0, right->aop, 0, true);
           /* shift and mask source value */
           if (blen + bstr == 8)
             AccLsh (bstr);
@@ -10808,7 +13483,7 @@
               else
                 {
                   extraPair = PAIR_BC;
-                  if (getPairId (AOP (right)) != PAIR_BC || !isLastUse (ic, right))
+                  if (getPairId (right->aop) != PAIR_BC || !isLastUse (ic, right))
                     {
                       _push (extraPair);
                       needPopExtra = 1;
@@ -10818,14 +13493,14 @@
           emit2 ("ld %s, a", _pairs[extraPair].l);
           spillPair (extraPair);
           regalloc_dry_run_cost += 1;
-          emit2 ("ld a, !*pair", _pairs[pair].name);
+          emit2 ("ld a, !mems", _pairs[pair].name);
           regalloc_dry_run_cost += (pair == PAIR_IX || pair == PAIR_IY) ? 3 : 1;
 
           emit2 ("and a, !immedbyte", mask);
           regalloc_dry_run_cost += 2;
           emit2 ("or a, %s", _pairs[extraPair].l);
           regalloc_dry_run_cost += 1;
-          emit2 ("ld !*pair, a", _pairs[pair].name);
+          emit2 ("ld !mems, a", _pairs[pair].name);
           regalloc_dry_run_cost += (pair == PAIR_IX || pair == PAIR_IY) ? 3 : 1;
           if (needPopExtra)
             _pop (extraPair);
@@ -10837,15 +13512,15 @@
   /* all except the partial byte at the end                 */
   for (rlen = blen; rlen >= 8; rlen -= 8)
     {
-      cheapMove (ASMOP_A, 0, AOP (right), offset++, true);
+      cheapMove (ASMOP_A, 0, right->aop, offset++, true);
       if (pair == PAIR_IX || pair == PAIR_IY)
         {
-          emit2 ("ld %d !*pair,a", pair_offset, _pairs[pair].name);
+          emit2 ("ld %d !mems, a", pair_offset, _pairs[pair].name);
           regalloc_dry_run_cost += 3;
         }
       else
         {
-          emit2 ("ld !*pair,a", _pairs[pair].name);
+          emit2 ("ld !mems, a", _pairs[pair].name);
           regalloc_dry_run_cost += 1;
         }
       if (rlen > 8 && pair != PAIR_IX && pair != PAIR_IY)
@@ -10864,21 +13539,21 @@
     {
       mask = (((unsigned char) - 1 << rlen) & 0xff);
 
-      if (AOP_TYPE (right) == AOP_LIT)
+      if (right->aop->type == AOP_LIT)
         {
           /* Case with partial byte and literal source */
-          litval = (int) ulFromVal (AOP (right)->aopu.aop_lit);
+          litval = (int) ulFromVal (right->aop->aopu.aop_lit);
           litval >>= (blen - rlen);
           litval &= (~mask) & 0xff;
 
           if (pair == PAIR_IX || pair == PAIR_IY)
             {
-              emit2 ("ld a, %d !*pair", pair_offset, _pairs[pair].name);
+              emit2 ("ld a, %d !mems", pair_offset, _pairs[pair].name);
               regalloc_dry_run_cost += 3;
             }
           else
             {
-              emit2 ("ld a, !*pair", _pairs[pair].name);
+              emit2 ("ld a, !mems", _pairs[pair].name);
               regalloc_dry_run_cost += 1;
             }
 
@@ -10890,7 +13565,7 @@
       else
         {
           /* Case with partial byte and arbitrary source */
-          cheapMove (ASMOP_A, 0, AOP (right), offset++, true);
+          cheapMove (ASMOP_A, 0, right->aop, offset++, true);
           emit2 ("and a, !immedbyte", (~mask) & 0xff);
           regalloc_dry_run_cost += 2;
 
@@ -10902,7 +13577,7 @@
               else
                 {
                   extraPair = PAIR_BC;
-                  if (getPairId (AOP (right)) != PAIR_BC || !isLastUse (ic, right))
+                  if (getPairId (right->aop) != PAIR_BC || !isLastUse (ic, right))
                     {
                       _push (extraPair);
                       needPopExtra = 1;
@@ -10916,12 +13591,12 @@
 
           if (pair == PAIR_IX || pair == PAIR_IY)
             {
-              emit2 ("ld a, %d !*pair", pair_offset, _pairs[pair].name);
+              emit2 ("ld a, %d !mems", pair_offset, _pairs[pair].name);
               regalloc_dry_run_cost += 3;
             }
           else
             {
-              emit2 ("ld a, !*pair", _pairs[pair].name);
+              emit2 ("ld a, !mems", _pairs[pair].name);
               regalloc_dry_run_cost += 1;
             }
 
@@ -10935,12 +13610,12 @@
         }
       if (pair == PAIR_IX || pair == PAIR_IY)
         {
-          emit2 ("ld %d !*pair, a", pair_offset, _pairs[pair].name);
+          emit2 ("ld %d !mems, a", pair_offset, _pairs[pair].name);
           regalloc_dry_run_cost += 3;
         }
       else
         {
-          emit2 ("ld !*pair, a", _pairs[pair].name);
+          emit2 ("ld !mems, a", _pairs[pair].name);
           regalloc_dry_run_cost += 1;
         }
     }
@@ -10967,8 +13642,9 @@
   bool isBitvar;
   sym_link *retype;
   sym_link *letype;
-  bool pushed_a = FALSE;
-  bool surviving_a = !options.oldralloc && bitVectBitValue (ic->rSurv, A_IDX);
+  bool pushed_a = false;
+  bool pushed_pair = false;
+  bool surviving_a = !isRegDead (A_IDX, ic);
 
   right = IC_RIGHT (ic);
   result = IC_RESULT (ic);
@@ -10978,45 +13654,62 @@
   aopOp (result, ic, FALSE, FALSE);
   aopOp (right, ic, FALSE, FALSE);
 
-  if (IS_GB)
-    pairId = isRegOrLit (AOP (right)) ? PAIR_HL : PAIR_DE;
+  if (IS_SM83)
+    pairId = isRegOrLit (right->aop) ? PAIR_HL : PAIR_DE;
   else if (IY_RESERVED)
-    pairId = (isRegOrLit (AOP (right)) || AOP_TYPE (right) == AOP_STK) ? PAIR_HL : PAIR_DE;
-  if (isPair (AOP (result)) && isPairDead (getPairId (AOP (result)), ic))
-    pairId = getPairId (AOP (result));
+    pairId = (isRegOrLit (right->aop) || right->aop->type == AOP_STK) ? PAIR_HL : PAIR_DE;
+  if (isPair (result->aop) && isPairDead (getPairId (result->aop), ic))
+    pairId = getPairId (result->aop);
 
-  size = AOP_SIZE (right);
+  size = right->aop->size;
 
   isBitvar = IS_BITVAR (retype) || IS_BITVAR (letype);
   emitDebug ("; isBitvar = %d", isBitvar);
 
+  if (IS_SM83 && size == 1 && result->aop->type == AOP_LIT && (((unsigned long)operandLitValue (result) & 0xff00) == 0xff00) && (isRegDead (A_IDX, ic) || aopInReg (right->aop, 0, A_IDX)) && !isBitvar) // SM83 has special instructions for address range 0xff00 - 0xffff.
+    {
+      cheapMove (ASMOP_A, 0, right->aop, 0, isRegDead (A_IDX, ic));
+      emit2 ("ldh !mems, a", aopGetLitWordLong (result->aop, 0, true));
+      cost (2, 12);
+      goto release;
+    }
+
   /* Handle the exceptions first */
-  if (isPair (AOP (result)) && size == 1 && !isBitvar)
+  if (isPair (result->aop) && size == 1 && !isBitvar)
     {
       /* Just do it */
-      const char *pair = getPairName (AOP (result));
-      if (canAssignToPtr3 (AOP (right)) && isPtr (pair))        // Todo: correct cost for pair iy.
+      const char *pair = getPairName (result->aop);
+      if (canAssignToPtr3 (right->aop) && isPtr (pair))        // Todo: correct cost for pair iy.
         {
           if (!regalloc_dry_run)
-            emit2 ("ld !*pair, %s", pair, aopGet (AOP (right), 0, FALSE));
-          regalloc_dry_run_cost += ld_cost (ASMOP_A, AOP (right)) + (getPairId (AOP (result)) != PAIR_IY ? 0 : 2);
+            emit2 ("ld !mems, %s", pair, aopGet (right->aop, 0, FALSE));
+          regalloc_dry_run_cost += ld_cost (ASMOP_A, 0, right->aop, 0) + (getPairId (result->aop) != PAIR_IY ? 0 : 2);
         }
       else
         {
           if (surviving_a && !pushed_a && !aopInReg (right->aop, 0, A_IDX))
             _push (PAIR_AF), pushed_a = TRUE;
-          if (AOP_TYPE (right) == AOP_LIT && byteOfVal (AOP (right)->aopu.aop_lit, offset) == 0x00)
+          if (right->aop->type == AOP_LIT && byteOfVal (right->aop->aopu.aop_lit, offset) == 0x00)
             emit3 (A_XOR, ASMOP_A, ASMOP_A);
           else
-            cheapMove (ASMOP_A, 0, AOP (right), 0, true);
-          emit2 ("ld !*pair, a", pair);
-          regalloc_dry_run_cost += (getPairId (AOP (result)) != PAIR_IY ? 1 : 3);
+            cheapMove (ASMOP_A, 0, right->aop, 0, true);
+          emit2 ("ld !mems, a", pair);
+          regalloc_dry_run_cost += (getPairId (result->aop) != PAIR_IY ? 1 : 3);
         }
       goto release;
     }
 
+  /* Rematerialized stack location */
+  if (result->aop->type == AOP_STL && !isBitvar && size <= 4)
+    {
+      struct asmop saop;
+      init_stackop (&saop, size, result->aop->aopu.aop_stk);
+      genMove (&saop, right->aop, isRegDead (A_IDX, ic), isPairDead(PAIR_HL, ic), isPairDead(PAIR_DE, ic), isPairDead(PAIR_IY, ic));
+      goto release;
+    }
+
   /* Using ldir is cheapest for large memory-to-memory transfers. */
-  if (!IS_GB && (AOP_TYPE (right) == AOP_STK || AOP_TYPE (right) == AOP_EXSTK) && size > 2)
+  if (!IS_SM83 && !IS_R2K && !IS_R2KA && (right->aop->type == AOP_STK || right->aop->type == AOP_EXSTK) && size > 2)
     {
       int fp_offset, sp_offset;
 
@@ -11027,14 +13720,14 @@
       if(!isPairDead (PAIR_HL, ic))
         _push (PAIR_HL);
 
-      fetchPair (PAIR_DE, AOP (result));
+      fetchPair (PAIR_DE, result->aop);
 
-      fp_offset = AOP (right)->aopu.aop_stk + (AOP (right)->aopu.aop_stk > 0 ? _G.stack.param_offset : 0);
+      fp_offset = right->aop->aopu.aop_stk + (right->aop->aopu.aop_stk > 0 ? _G.stack.param_offset : 0);
       sp_offset = fp_offset + _G.stack.pushed + _G.stack.offset;
-      emit2 ("ld hl, !immedword", sp_offset);
-      emit2 ("add hl, sp");
+      emit2 ("!ldahlsp", sp_offset);
       emit2 ("ld bc, !immedword", size);
       emit2 ("ldir");
+      spillPair (PAIR_HL);
       regalloc_dry_run_cost += 9;
 
       if(!isPairDead (PAIR_HL, ic))
@@ -11046,20 +13739,20 @@
       goto release;
     }
 
-  if (getPairId (AOP (result)) == PAIR_IY && !isBitvar)
+  if (getPairId (result->aop) == PAIR_IY && !isBitvar)
     {
       /* Just do it */
       while (size--)
         {
-          if (canAssignToPtr3 (AOP (right)))
+          if (canAssignToPtr3 (right->aop))
             {
               if (!regalloc_dry_run)
-                emit2 ("ld !*iyx, %s", offset, aopGet (AOP (right), offset, FALSE));
+                emit2 ("ld !*iyx, %s", offset, aopGet (right->aop, offset, FALSE));
               regalloc_dry_run_cost += 3;       // Todo: More exact cost here!
             }
           else
             {
-              cheapMove (ASMOP_A, 0, AOP (right), offset, true);
+              cheapMove (ASMOP_A, 0, right->aop, offset, true);
               emit2 ("ld !*iyx, a", offset);
               regalloc_dry_run_cost += 3;
             }
@@ -11075,7 +13768,7 @@
 
           if (IS_EZ80_Z80 && offset + 1 < size && getPairId_o (right->aop, offset) != PAIR_INVALID)
             {
-              emit2 ("ld !*pair, %s", _pairs[PAIR_HL].name, _pairs[getPairId_o (right->aop, offset)].name);
+              emit2 ("ld !mems, %s", _pairs[PAIR_HL].name, _pairs[getPairId_o (right->aop, offset)].name);
               regalloc_dry_run_cost += 2;
               offset += 2;
 
@@ -11089,11 +13782,11 @@
 
               continue;
             }
-          else if (isRegOrLit (AOP (right)) && !IS_GB)
+          else if (isRegOrLit (right->aop) && !IS_SM83)
             {
               if (!regalloc_dry_run)
-                emit2 ("ld !*pair, %s", _pairs[PAIR_HL].name, aopGet (right->aop, offset, FALSE));
-              regalloc_dry_run_cost += ld_cost (ASMOP_A, right->aop);
+                emit2 ("ld !mems, %s", _pairs[PAIR_HL].name, aopGet (right->aop, offset, FALSE));
+              regalloc_dry_run_cost += ld_cost (ASMOP_A, 0, right->aop, offset);
               offset++;
             }
           else
@@ -11101,7 +13794,7 @@
               if (surviving_a && !pushed_a && (!aopInReg (right->aop, 0, A_IDX) || offset))
                 _push (PAIR_AF), pushed_a = TRUE;
               cheapMove (ASMOP_A, 0, right->aop, offset, true);
-              emit2 ("ld !*pair, a", _pairs[PAIR_HL].name);
+              emit2 ("ld !mems, a", _pairs[PAIR_HL].name);
               regalloc_dry_run_cost += 1;
               offset++;
             }
@@ -11123,52 +13816,59 @@
       goto release;
     }
 
-  if (!IS_GB && !isBitvar && isLitWord (AOP (result)) && size == 2 && offset == 0 &&
-      (AOP_TYPE (right) == AOP_REG && getPairId (AOP (right)) != PAIR_INVALID || isLitWord (AOP (right))))
+  if (!IS_SM83 && !isBitvar && isLitWord (result->aop) && size == 2 && offset == 0 &&
+      (right->aop->type == AOP_REG && getPairId (right->aop) != PAIR_INVALID || isLitWord (right->aop)))
     {
-      if (isLitWord (AOP (right)))
+      if (isLitWord (right->aop))
         {
           pairId = PAIR_HL;
-          fetchPairLong (pairId, AOP (right), ic, 0);
+          fetchPairLong (pairId, right->aop, ic, 0);
         }
       else
-        pairId = getPairId (AOP (right));
-      emit2 ("ld (%s), %s", aopGetLitWordLong (AOP (result), offset, FALSE), _pairs[pairId].name);
+        pairId = getPairId (right->aop);
+      emit2 ("ld !mems, %s", aopGetLitWordLong (result->aop, offset, FALSE), _pairs[pairId].name);
       regalloc_dry_run_cost += (pairId == PAIR_HL) ? 3 : 4;
       goto release;
     }
-  if (!IS_GB && !isBitvar && isLitWord (AOP (result)) && size == 4 && offset == 0 &&
-    (getPartPairId (AOP (right), 0) != PAIR_INVALID && getPartPairId (AOP (right), 2) != PAIR_INVALID || isLitWord (AOP (right))))
+  if (!IS_SM83 && !isBitvar && isLitWord (result->aop) && size == 4 && offset == 0 &&
+    (getPartPairId (right->aop, 0) != PAIR_INVALID && getPartPairId (right->aop, 2) != PAIR_INVALID || isLitWord (right->aop)))
     {
-      if (isLitWord (AOP (right)))
+      if (isLitWord (right->aop))
         {
           pairId = PAIR_HL;
-          fetchPairLong (pairId, AOP (right), ic, 0);
+          fetchPairLong (pairId, right->aop, ic, 0);
         }
       else
-        pairId = getPartPairId (AOP (right), 0);
-      emit2 ("ld (%s), %s", aopGetLitWordLong (AOP (result), offset, FALSE), _pairs[pairId].name);
+        pairId = getPartPairId (right->aop, 0);
+      emit2 ("ld !mems, %s", aopGetLitWordLong (result->aop, offset, FALSE), _pairs[pairId].name);
       regalloc_dry_run_cost += (pairId == PAIR_HL) ? 3 : 4;
-      if (isLitWord (AOP (right)))
+      if (isLitWord (right->aop))
         {
           pairId = PAIR_HL;
-          fetchPairLong (pairId, AOP (right), ic, 2);
+          fetchPairLong (pairId, right->aop, ic, 2);
         }
       else
-        pairId = getPartPairId (AOP (right), 2);
-      emit2 ("ld (%s+%d), %s", aopGetLitWordLong (AOP (result), offset, FALSE),2,  _pairs[pairId].name); // Handling of literal addresses is somewhat broken, use explicit offset as workaround.
+        pairId = getPartPairId (right->aop, 2);
+      emit2 ("ld (%s+%d), %s", aopGetLitWordLong (result->aop, offset, FALSE),2,  _pairs[pairId].name); // Handling of literal addresses is somewhat broken, use explicit offset as workaround.
       regalloc_dry_run_cost += (pairId == PAIR_HL) ? 3 : 4;
       goto release;
     }
 
   /* if the operand is already in dptr
      then we do nothing else we move the value to dptr */
-  if (AOP_TYPE (result) != AOP_STR)
+  if (result->aop->type != AOP_STR)
     {
-      if (isBitvar && getPairId (AOP (result)) != PAIR_INVALID && (getPairId (AOP (result)) != PAIR_IY || SPEC_BLEN (IS_BITVAR (retype) ? retype : letype) < 8 || isPairDead (getPairId (AOP (result)), ic)))   /* Avoid destroying result by increments */
-        pairId = getPairId (AOP (result));
+      if (isBitvar && getPairId (result->aop) != PAIR_INVALID && (getPairId (result->aop) != PAIR_IY || SPEC_BLEN (IS_BITVAR (retype) ? retype : letype) < 8 || isPairDead (getPairId (result->aop), ic)))   /* Avoid destroying result by increments */
+        pairId = getPairId (result->aop);
       else
-        fetchPairLong (pairId, AOP (result), ic, 0);
+        {
+          if (!isPairDead (pairId, ic) && getPairId (result->aop) != pairId)
+            {
+              _push (pairId);
+              pushed_pair = true;
+            }
+          fetchPairLong (pairId, result->aop, ic, 0);
+        }
     }
   /* so hl now contains the address */
   /*freeAsmop (result, NULL, ic);*/
@@ -11189,7 +13889,7 @@
 
           if (IS_EZ80_Z80 && offset + 1 < size && pairId == PAIR_HL && getPairId_o (right->aop, offset) != PAIR_INVALID)
             {
-              emit2 ("ld !*pair, %s", _pairs[pairId].name, _pairs[getPairId_o (right->aop, offset)].name);
+              emit2 ("ld !mems, %s", _pairs[pairId].name, _pairs[getPairId_o (right->aop, offset)].name);
               regalloc_dry_run_cost += 2;
               offset += 2;
 
@@ -11210,25 +13910,25 @@
               regalloc_dry_run_cost++;
               zero_a = true;
             }
- 
+
           if (aopIsLitVal (right->aop, offset, 1, 0x00) && zero_a)
             {
-              emit2 ("ld !*pair, a", _pairs[pairId].name);
+              emit2 ("ld !mems, a", _pairs[pairId].name);
               regalloc_dry_run_cost++;
             }
           else if (isRegOrLit (right->aop) && pairId == PAIR_HL)
             {
               if (!regalloc_dry_run)
-                emit2 ("ld !*pair, %s", _pairs[pairId].name, aopGet (AOP (right), offset, FALSE));
-              regalloc_dry_run_cost += ld_cost (ASMOP_A, AOP (right));
+                emit2 ("ld !mems, %s", _pairs[pairId].name, aopGet (right->aop, offset, FALSE));
+              regalloc_dry_run_cost += ld_cost (ASMOP_A, 0, right->aop, offset);
             }
           else
             {
               if (surviving_a && !pushed_a && (!aopInReg (right->aop, 0, A_IDX) || offset))
-                _push (PAIR_AF), pushed_a = TRUE;
-              cheapMove (ASMOP_A, 0, AOP (right), offset, true);
+                _push (PAIR_AF), pushed_a = true;
+              cheapMove (ASMOP_A, 0, right->aop, offset, true);
               zero_a = false;
-              emit2 ("ld !*pair, a", _pairs[pairId].name);
+              emit2 ("ld !mems, a", _pairs[pairId].name);
               regalloc_dry_run_cost += 1;
             }
           offset++;
@@ -11240,19 +13940,18 @@
               _G.pairs[pairId].offset++;
             }
         }
-      /* Restore operand partially in HL. */
-      if (!isPairDead (pairId, ic) && AOP (result)->type == AOP_REG)
-        {
-          while(last_offset --> 0)
-            {
-              emit2 ("dec %s", _pairs[pairId].name);
-              regalloc_dry_run_cost += 1;
-              _G.pairs[pairId].offset--;
-            }
-          commitPair (AOP (result), pairId, ic, FALSE);
-        }
+      /* Restore operand in pair. */
+      if (!isPairDead (pairId, ic) && getPairId (result->aop) == pairId)
+        while(last_offset --> 0)
+          {
+            emit2 ("dec %s", _pairs[pairId].name);
+            regalloc_dry_run_cost += 1;
+            _G.pairs[pairId].offset--;
+          }
     }
 release:
+  if (pushed_pair)
+    _pop (pairId);
   if (pushed_a)
     _pop (PAIR_AF);
 
@@ -11271,24 +13970,39 @@
 
   aopOp (cond, ic, FALSE, TRUE);
 
-  /* get the value into acc */
-  if (AOP_TYPE (cond) != AOP_CRY && !IS_BOOL (operandType (cond)))
-    _toBoolean (cond, !popIc);
   /* Special case: Condition is bool */
-  else if (IS_BOOL (operandType (cond)))
+  if (IS_BOOL (operandType (cond)) && !aopInReg (cond->aop, 0, A_IDX))
     {
       if (!regalloc_dry_run)
         {
-          emit2 ("bit 0, %s", aopGet (AOP (cond), 0, FALSE));
-          emit2 ("jp %s, !tlabel", IC_TRUE (ic) ? "NZ" : "Z", labelKey2num ((IC_TRUE (ic) ? IC_TRUE (ic) : IC_FALSE (ic))->key));
+          emit2 ("bit 0, %s", aopGet (cond->aop, 0, FALSE));
+          genIfxJump (ic, "nz");
         }
-      regalloc_dry_run_cost += (bit8_cost (AOP (cond)) + 3);
+      bit8_cost (cond->aop); // todo: fix, bit has different cost!
 
-      freeAsmop (cond, NULL);
-      if (!regalloc_dry_run)
-        ic->generated = 1;
-      return;
+      goto release;
+    }
+  else if (cond->aop->size == 1 && !isRegDead (A_IDX, ic) &&
+    (aopInReg (cond->aop, 0, B_IDX) || aopInReg (cond->aop, 0, C_IDX) || aopInReg (cond->aop, 0, D_IDX) || aopInReg (cond->aop, 0, E_IDX) || aopInReg (cond->aop, 0, H_IDX) || aopInReg (cond->aop, 0, L_IDX)))
+    {
+      emit3 (A_INC, cond->aop, 0);
+      emit3 (A_DEC, cond->aop, 0);
+      regalloc_dry_run_cost += 2;
+      genIfxJump (ic, "nz");
+
+      goto release;
+    }
+  else if (IS_RAB && (getPairId (cond->aop) == PAIR_HL || getPairId (cond->aop) == PAIR_IY) && isPairDead (getPairId (cond->aop), ic))
+    {
+      emit2 ("bool %s", _pairs[getPairId (cond->aop)].name);
+      regalloc_dry_run_cost += 1 + (getPairId (cond->aop) == PAIR_IY);
+      genIfxJump (ic, "nz");
+      
+      goto release;
     }
+  /* get the value into acc */
+  else if (cond->aop->type != AOP_CRY)
+    _toBoolean (cond, !popIc);
   else
     isbit = 1;
   /* the result is now in the accumulator */
@@ -11308,6 +14022,16 @@
 
   if (!regalloc_dry_run)
     ic->generated = 1;
+
+  return;
+
+release:
+
+  freeAsmop (cond, NULL);
+  if (!regalloc_dry_run)
+    ic->generated = 1;
+
+  return;
 }
 
 /*-----------------------------------------------------------------*/
@@ -11337,18 +14061,18 @@
       spillPair (pair);
       if (IS_EZ80_Z80 && in_fp_range)
         {
-          emit2 ("lea %s, ix, #%d", _pairs[pair].name, fp_offset);
+          emit2 ("lea %s, ix, !immed%d", _pairs[pair].name, fp_offset);
           regalloc_dry_run_cost += 3;
         }
       else
         setupPairFromSP (pair, sp_offset);
     }
-  else 
+  else
     {
       pair = getPairId (IC_RESULT (ic)->aop);
       if (pair == PAIR_INVALID)
         {
-          pair = IS_GB ? PAIR_DE : PAIR_HL;
+          pair = IS_SM83 ? PAIR_DE : PAIR_HL;
           spillPair (pair);
         }
       emit2 ("ld %s, !hashedstr+%ld", _pairs[pair].name, sym->rname, (long)(operandLitValue (right)));
@@ -11371,6 +14095,8 @@
 
   result = IC_RESULT (ic);
   right = IC_RIGHT (ic);
+  
+  const bool hl_dead = isPairDead (PAIR_HL, ic);
 
   /* Dont bother assigning if they are the same */
   if (operandsEqu (IC_RESULT (ic), IC_RIGHT (ic)))
@@ -11380,46 +14106,59 @@
   aopOp (result, ic, TRUE, FALSE);
 
   /* if they are the same registers */
-  if (sameRegs (AOP (right), AOP (result)))
+  if (sameRegs (right->aop, result->aop))
     {
       emitDebug ("; (locations are the same)");
       goto release;
     }
 
   /* if the result is a bit */
-  if (AOP_TYPE (result) == AOP_CRY)
+  if (result->aop->type == AOP_CRY)
     {
       wassertl (0, "Tried to assign to a bit");
     }
 
   /* general case */
-  size = AOP_SIZE (result);
+  size = result->aop->size;
   offset = 0;
 
-  if (isPair (AOP (result)))
-    fetchPairLong (getPairId (AOP (result)), AOP (right), ic, LSB);
-  else if (isPair (AOP (right)) && AOP_TYPE (result) == AOP_IY && size == 2)
-    commitPair (AOP (result), getPairId (AOP (right)), ic, FALSE);
-  else if (size == 2 && isPairDead (PAIR_HL, ic) &&
-    (!IS_GB && (AOP_TYPE (right) == AOP_STK && !_G.omitFramePtr || AOP_TYPE (right) == AOP_IY || AOP_TYPE (right) == AOP_LIT) && AOP_TYPE (result) == AOP_IY || // Use ld (nn), hl
-    !IS_GB && AOP_TYPE (right) == AOP_IY && (AOP_TYPE (result) == AOP_STK && !_G.omitFramePtr || AOP_TYPE (result) == AOP_IY) || // Use ld hl, (nn)
-    !IS_GB && AOP_TYPE (right) == AOP_LIT && (AOP_TYPE(result) == AOP_STK || AOP_TYPE(result) == AOP_EXSTK) && (AOP(result)->aopu.aop_stk + offset + _G.stack.offset + (AOP(result)->aopu.aop_stk > 0 ? _G.stack.param_offset : 0) + _G.stack.pushed) == 0 || // Use ex (sp), hl
-    (IS_RAB || IS_TLCS90) && (AOP_TYPE(result) == AOP_STK || AOP_TYPE(result) == AOP_EXSTK) && (AOP_TYPE(right) == AOP_LIT || AOP_TYPE (right) == AOP_IMMD))) // Use ld d(sp), hl
+  // SM83 has special instruction for access to addresses 0xff00 to 0xffff, so use them here, when possible
+  if (IS_SM83 && size == 1 && aopInReg (result->aop, 0, A_IDX) && right->aop->type == AOP_HL && SPEC_ABSA (OP_SYM_ETYPE (right)) && (SPEC_ADDR (OP_SYM_ETYPE (right)) & 0xff00) == 0xff00)
     {
-      fetchPair (PAIR_HL, AOP (right));
-      commitPair (AOP (result), PAIR_HL, ic, FALSE);
+      emit2 ("ldh a, !mems", right->aop->aopu.aop_dir);
+      cost (2, 12);
+      goto release;
     }
-  else if (size == 2 && getPairId (AOP (right)) != PAIR_INVALID && getPairId (AOP (right)) != PAIR_IY && AOP_TYPE (result) != AOP_REG)
+  else if (IS_SM83 && size == 1 && aopInReg (right->aop, 0, A_IDX) && result->aop->type == AOP_HL && SPEC_ABSA (OP_SYM_ETYPE (result)) && (SPEC_ADDR (OP_SYM_ETYPE (result)) & 0xff00) == 0xff00)
     {
-      commitPair (AOP (result), getPairId (AOP (right)), ic, TRUE);
+      emit2 ("ldh (#%x), a", result->aop->aopu.aop_dir);
+      cost (2, 12);
+      goto release;
     }
-  else if (getPairId (AOP (right)) == PAIR_IY)
+
+  if (isPair (result->aop) && getPairId (result->aop) != PAIR_IY ||
+    isPair (right->aop) && result->aop->type == AOP_IY && size == 2)
+    genMove (result->aop, right->aop, isRegDead (A_IDX, ic), isPairDead (PAIR_HL, ic), isPairDead (PAIR_DE, ic), true);
+  else if (size == 2 && isPairDead (PAIR_HL, ic) &&
+    (!IS_SM83 && (right->aop->type == AOP_STK && !_G.omitFramePtr || right->aop->type == AOP_IY || right->aop->type == AOP_LIT) && result->aop->type == AOP_IY || // Use ld (nn), hl
+    !IS_SM83 && right->aop->type == AOP_IY && (result->aop->type == AOP_STK && !_G.omitFramePtr || result->aop->type == AOP_IY) || // Use ld hl, (nn)
+    !IS_SM83 && right->aop->type == AOP_LIT && (result->aop->type == AOP_STK || result->aop->type == AOP_EXSTK) && (result->aop->aopu.aop_stk + offset + _G.stack.offset + (result->aop->aopu.aop_stk > 0 ? _G.stack.param_offset : 0) + _G.stack.pushed) == 0 || // Use ex (sp), hl
+    (IS_RAB || IS_TLCS90) && (result->aop->type == AOP_STK || result->aop->type == AOP_EXSTK) && (right->aop->type == AOP_LIT || right->aop->type == AOP_IMMD))) // Use ld d(sp), hl
+    {
+      fetchPair (PAIR_HL, right->aop);
+      genMove (result->aop, ASMOP_HL, isRegDead (A_IDX, ic), true, isPairDead (PAIR_DE, ic), isPairDead (PAIR_IY, ic));
+    }
+  else if (size == 2 && getPairId (right->aop) != PAIR_INVALID)
+    genMove (result->aop, right->aop, isRegDead (A_IDX, ic), isPairDead (PAIR_HL, ic), isPairDead (PAIR_DE, ic), isPairDead (PAIR_IY, ic));
+  else if (size <= 2 && requiresHL (right->aop) && requiresHL (result->aop) && IS_SM83)
+    genMove (result->aop, right->aop, isRegDead (A_IDX, ic), isPairDead (PAIR_HL, ic), isPairDead (PAIR_DE, ic), isPairDead (PAIR_IY, ic));
+  else if (getPairId (right->aop) == PAIR_IY && result->aop->type != AOP_REG)
     {
       while (size--)
         {
           if (size == 0)
             {
-              if (IS_TLCS90)
+              if (IS_TLCS90) // f needs to be preserved for tlcs90.
                 {
                   emit2 ("push iy");
                   emit2 ("ld a, 0(sp)");
@@ -11435,23 +14174,23 @@
                   emit2 ("inc sp");
                   regalloc_dry_run_cost += 5;
                 }
-              if (AOP_TYPE (result) == AOP_IY) /* Take care not to overwrite iy */
+              if (result->aop->type == AOP_IY) /* Take care not to overwrite iy */
                 {
-                  emit2 ("ld (%s+%d), a", AOP (result)->aopu.aop_dir, size);
+                  emit2 ("ld (%s+%d), a", result->aop->aopu.aop_dir, size);
                   regalloc_dry_run_cost += 3;
                 }
               else
-                cheapMove (AOP (result), size, ASMOP_A, 0, true);
+                cheapMove (result->aop, size, ASMOP_A, 0, true);
             }
           else if (size == 1)
             {
-              if (AOP_TYPE (result) == AOP_IY) /* Take care not to overwrite iy */
+              if (result->aop->type == AOP_IY) /* Take care not to overwrite iy */
                 {
-                  emit2 ("ld (%s), iy", AOP (result)->aopu.aop_dir);
+                  emit2 ("ld !mems, iy", result->aop->aopu.aop_dir);
                   regalloc_dry_run_cost += 4;
                   size--;
                 }
-              else if (AOP_TYPE (result) == AOP_EXSTK || IS_TLCS90) /* Take care not to overwrite iy */
+              else if (result->aop->type == AOP_EXSTK || IS_TLCS90) /* Take care not to overwrite iy or f */
                 {
                   bool pushed_pair = FALSE;
                   PAIR_ID pair = getDeadPairId (ic);
@@ -11461,8 +14200,8 @@
                     _push(pair);
                     pushed_pair= TRUE;
                   }
-                  fetchPair (pair, AOP (right));
-                  commitPair (AOP (result), pair, ic, FALSE);
+                  fetchPair (pair, right->aop);
+                  commitPair (result->aop, pair, ic, FALSE);
                   if (pushed_pair)
                     _pop (pair);
                   size--;
@@ -11472,99 +14211,110 @@
                   emit2 ("push iy");
                   emit2 ("pop af");
                   regalloc_dry_run_cost += 3;
-                  cheapMove (AOP (result), size, ASMOP_A, 0, true);
+                  cheapMove (result->aop, size, ASMOP_A, 0, true);
                 }
             }
           else
             {
-              if (AOP_TYPE (result) == AOP_IY) /* Take care not to overwrite iy */
+              if (result->aop->type == AOP_IY) /* Take care not to overwrite iy */
                 {
                   cheapMove (ASMOP_A, 0, ASMOP_ZERO, 0, true);
-                  emit2 ("ld (%s+%d), a", AOP (result)->aopu.aop_dir, size);
+                  emit2 ("ld (%s+%d), a", result->aop->aopu.aop_dir, size);
                   regalloc_dry_run_cost += 3;
                 }
               else
-                cheapMove (AOP (result), size, ASMOP_ZERO, 0, true);
+                cheapMove (result->aop, size, ASMOP_ZERO, 0, true);
             }
         }
     }
-  else if (size == 2 && requiresHL (AOP (right)) && requiresHL (AOP (result)) && isPairDead (PAIR_DE, ic) && (IS_GB /*|| IY_RESERVED */ ))
-    {
-      /* Special case.  Load into a and d, then load out. */
-      cheapMove (ASMOP_A, 0, AOP (right), 0, true);
-      emit3_o (A_LD, ASMOP_E, 0, AOP (right), 1);
-      cheapMove (AOP (result), 0, ASMOP_A, 0, true);
-      cheapMove (AOP (result), 1, ASMOP_E, 0, true);
-    }
-  else if (size == 4 && requiresHL (AOP (right)) && requiresHL (AOP (result)) && isPairDead (PAIR_DE, ic) && (IS_GB /*|| IY_RESERVED */ ))
+  else if (size == 4 && (requiresHL (right->aop) && right->aop->type != AOP_REG) && (requiresHL (result->aop) && result->aop->type != AOP_REG ) && isPairDead (PAIR_DE, ic) && (IS_SM83 || IY_RESERVED))
     {
       /* Special case - simple memcpy */
       if (!regalloc_dry_run)
         {
-          aopGet (AOP (right), LSB, FALSE);
+          aopGet (right->aop, LSB, FALSE);
           emit2 ("ld d, h");
           emit2 ("ld e, l");
-          aopGet (AOP (result), LSB, FALSE);
+          aopGet (result->aop, LSB, FALSE);
         }
       regalloc_dry_run_cost += 8;       // Todo: More exact cost here!
 
       while (size--)
         {
-          emit2 ("ld a, (de)");
-          /* Peephole will optimise this. */
-          emit2 ("ld (hl), a");
-          regalloc_dry_run_cost += 2;
+          emit2 ("ld a, !mems", "de");
+          regalloc_dry_run_cost += 1;
           if (size != 0)
             {
-              emit2 ("inc hl");
+              emit2 ("!lldahli");
               emit2 ("inc de");
-              regalloc_dry_run_cost += 2;
+              regalloc_dry_run_cost += 3;
+            }
+          else
+            {
+              emit2 ("ld !*hl, a");
+              regalloc_dry_run_cost += 1;
             }
         }
       spillPair (PAIR_HL);
     }
   else
     {
-      if (!IS_GB &&             /* gbz80 doesn't have ldir */
-          (AOP_TYPE (result) == AOP_STK || AOP_TYPE (result) == AOP_EXSTK || AOP_TYPE (result) == AOP_DIR
-           || AOP_TYPE (result) == AOP_IY) && (AOP_TYPE (right) == AOP_STK || AOP_TYPE (right) == AOP_EXSTK
-               || AOP_TYPE (right) == AOP_DIR || AOP_TYPE (right) == AOP_IY) && size >= 2)
+      if (!IS_SM83 && // sm83 doesn't have ldir, r2k and r2ka ldir is affected by a wait state bug when copying between different types of memory.
+          (result->aop->type == AOP_STK || result->aop->type == AOP_EXSTK || result->aop->type == AOP_DIR
+           || result->aop->type == AOP_IY) && (right->aop->type == AOP_STK || right->aop->type == AOP_EXSTK
+               || right->aop->type == AOP_DIR || right->aop->type == AOP_IY) && size >= 2)
         {
-          /* This estimation is only accurate, if neither operand is AOP_EXSTK, and we are optimizing for code size or targeting the z80 or z180. */
+          // This estimation is only accurate, if neither operand is AOP_EXSTK, and we are optimizing for code size or targeting the Z80, Z180, eZ80, Z80N or Rabbit 3000A.
           int sizecost_n, sizecost_l, cyclecost_n, cyclecost_l;
           const bool hl_alive = !isPairDead (PAIR_HL, ic);
           const bool de_alive = !isPairDead (PAIR_DE, ic);
           const bool bc_alive = !isPairDead (PAIR_BC, ic);
           bool l_better;
-          sizecost_n = 6 * size;
-          sizecost_l = 13 + hl_alive * 2 + de_alive * 2 + bc_alive * 2 - (AOP_TYPE (right) == AOP_DIR
-                       || AOP_TYPE (right) == AOP_IY) - (AOP_TYPE (result) ==
-                           AOP_DIR
-                           || AOP_TYPE (result)
-                           == AOP_IY) * 2;
-          if (IS_Z180 || IS_EZ80_Z80)
+
+          if (IS_EZ80_Z80 && result->aop->type == AOP_STK && right->aop->type == AOP_STK) // eZ80: Use 16-Bit loads, except for odd trailing byte.
+            sizecost_n = (size / 2 * 6) + (size % 2 * 6);
+          else if (IS_RAB && result->aop->type == AOP_STK && right->aop->type == AOP_STK) // Rabbit: Use 16-Bit loads, except for odd trailing byte.
+            sizecost_n = (size / 2 * 4) + (size % 2 * 6);
+          else // Use 8-Bit loads: Z80, Z180, Z80N.
+            sizecost_n = 6 * size;
+
+          sizecost_l = 13 + hl_alive * 2 + de_alive * 2 + bc_alive * 2 -
+            (right->aop->type == AOP_DIR || right->aop->type == AOP_IY) -
+            (result->aop->type == AOP_DIR || result->aop->type == AOP_IY) * 2;
+
+          if (IS_EZ80_Z80 && result->aop->type == AOP_STK && right->aop->type == AOP_STK)
+            cyclecost_n = (size / 2 * 10) + (size % 2 * 8);
+          else if (IS_RAB && result->aop->type == AOP_STK && right->aop->type == AOP_STK)
+            cyclecost_n = (size / 2 * 18) + (size % 2 * 18);
+          else if (IS_EZ80_Z80)
+            cyclecost_n = 8 * size;
+          else if (IS_Z180)
             cyclecost_n = 30 * size;
-          else                  /* Z80 */
+          else if (IS_RAB)
+            cyclecost_n = 18 * size;
+          else // Z80, Z80N
             cyclecost_n = 38 * size;
-          if (IS_Z180 || IS_EZ80_Z80)
-            cyclecost_l = 14 * size + 42 + hl_alive * 22 + de_alive * 22 + bc_alive * 22 - (AOP_TYPE (right) == AOP_DIR
-                          || AOP_TYPE (right) ==
-                          AOP_IY) * 7 - (AOP_TYPE (result) ==
-                                         AOP_DIR
-                                         || AOP_TYPE (result)
-                                         == AOP_IY) * 10;
-          else                  /* Z80 */
-            cyclecost_l = 21 * size + 51 + hl_alive * 20 + de_alive * 20 + bc_alive * 20 - (AOP_TYPE (right) == AOP_DIR
-                          || AOP_TYPE (right) ==
-                          AOP_IY) * 11 - (AOP_TYPE (result) ==
-                                          AOP_DIR
-                                          || AOP_TYPE (result)
-                                          == AOP_IY) * 15;
+
+          if (IS_EZ80_Z80)
+            cyclecost_l = 2 * size + 9 + hl_alive * 6 + de_alive * 6 + bc_alive * 6; // lea is as fast as ld rr, nn. So it does not matter if the operands are on stack.
+          else if (IS_Z180)
+            cyclecost_l = 14 * size + 42 + hl_alive * 22 + de_alive * 22 + bc_alive * 22 -
+              (right->aop->type == AOP_DIR || right->aop->type == AOP_IY) * 7 -
+              (result->aop->type == AOP_DIR || result->aop->type == AOP_IY) * 10;
+          else if (IS_RAB)
+            cyclecost_l = 7 * size + 34 + hl_alive * 17 + de_alive * 17 + bc_alive * 17 -
+              (right->aop->type == AOP_DIR || right->aop->type == AOP_IY) * 4 -
+              (result->aop->type == AOP_DIR || result->aop->type == AOP_IY) * 6;    
+          else // Z80
+            cyclecost_l = 21 * size + 51 + hl_alive * 21 + de_alive * 21 + bc_alive * 21 -
+              (right->aop->type == AOP_DIR || right->aop->type == AOP_IY) * 11 -
+              (result->aop->type == AOP_DIR || result->aop->type == AOP_IY) * 15;
 
           if (optimize.codeSize)
             l_better = (sizecost_l < sizecost_n || sizecost_l == sizecost_n && cyclecost_l < cyclecost_n);
           else
             l_better = (cyclecost_l < cyclecost_n || cyclecost_l == cyclecost_n && sizecost_l < sizecost_n);
+
           if (l_better)
             {
               if (hl_alive)
@@ -11574,41 +14324,35 @@
               if (bc_alive)
                 _push (PAIR_BC);
 
-              if (AOP_TYPE (result) == AOP_STK || AOP_TYPE (result) == AOP_EXSTK)
+              if (result->aop->type == AOP_STK || result->aop->type == AOP_EXSTK)
                 {
                   int fp_offset =
-                    AOP (result)->aopu.aop_stk + offset + (AOP (result)->aopu.aop_stk >
+                    result->aop->aopu.aop_stk + offset + (result->aop->aopu.aop_stk >
                         0 ? _G.stack.param_offset : 0);
                   int sp_offset = fp_offset + _G.stack.pushed + _G.stack.offset;
-                  emit2 ("ld hl, #%d", sp_offset);
-                  emit2 ("add hl, sp");
+                  emit2 ("!ldahlsp", sp_offset);
                   emit2 ("ex de, hl");
                   regalloc_dry_run_cost += 5;
                 }
               else
-                {
-                  emit2 ("ld de, #%s", AOP (IC_RESULT (ic))->aopu.aop_dir);
-                  regalloc_dry_run_cost += 3;
-                }
+                pointPairToAop (PAIR_DE, result->aop, 0);
 
-              if (AOP_TYPE (right) == AOP_STK || AOP_TYPE (right) == AOP_EXSTK)
+              if (right->aop->type == AOP_STK || right->aop->type == AOP_EXSTK)
                 {
                   int fp_offset =
-                    AOP (right)->aopu.aop_stk + offset + (AOP (right)->aopu.aop_stk >
+                    right->aop->aopu.aop_stk + offset + (right->aop->aopu.aop_stk >
                         0 ? _G.stack.param_offset : 0);
                   int sp_offset = fp_offset + _G.stack.pushed + _G.stack.offset;
-                  emit2 ("ld hl, #%d", sp_offset);
-                  emit2 ("add hl, sp");
+                  emit2 ("!ldahlsp", sp_offset);
+                  spillPair (PAIR_HL);
                   regalloc_dry_run_cost += 4;
                 }
               else
-                {
-                  emit2 ("ld hl, #%s", AOP (IC_RIGHT (ic))->aopu.aop_dir);
-                  regalloc_dry_run_cost += 3;
-                }
-              spillPair (PAIR_HL);
+                pointPairToAop (PAIR_HL, right->aop, 0);
 
-              if (size <= 2 + optimize.codeSpeed)
+              if (size <= 2 + (!IS_RAB && optimize.codeSpeed) ||
+                // Early Rabbits have a wait state bug when ldir copies between different types of memory.
+                (IS_R2K || IS_R2KA) && !((right->aop->type == AOP_STK || right->aop->type == AOP_EXSTK) && (result->aop->type == AOP_STK || result->aop->type == AOP_EXSTK)))
                 for(int i = 0; i < size; i++)
                   {
                     emit2 ("ldi");
@@ -11616,10 +14360,13 @@
                   }
               else
                 {
-                  emit2 ("ld bc, #%d", size);
+                  emit2 ("ld bc, !immed%d", size);
                   emit2 ("ldir");
                   regalloc_dry_run_cost += 5;
                 }
+              spillPair (PAIR_HL);
+              spillPair (PAIR_DE);
+              spillPair (PAIR_BC);
 
               if (bc_alive)
                 _pop (PAIR_BC);
@@ -11631,22 +14378,24 @@
               goto release;
             }
         }
-      if ((result->aop->type == AOP_REG || result->aop->type == AOP_STK || result->aop->type == AOP_EXSTK) && (right->aop->type == AOP_REG || right->aop->type == AOP_STK || right->aop->type == AOP_LIT))
-        genMove (result->aop, right->aop, !bitVectBitValue (ic->rSurv, A_IDX), isPairDead (PAIR_HL, ic));
+      if ((result->aop->type == AOP_REG || result->aop->type == AOP_STK || result->aop->type == AOP_EXSTK || result->aop->type == AOP_IY || result->aop->type == AOP_HL) && (right->aop->type == AOP_REG || right->aop->type == AOP_STK || right->aop->type == AOP_EXSTK || right->aop->type == AOP_LIT || right->aop->type == AOP_IMMD || right->aop->type == AOP_DIR || right->aop->type == AOP_IY || right->aop->type == AOP_HL))
+        genMove (result->aop, right->aop, isRegDead (A_IDX, ic), isPairDead (PAIR_HL, ic), isPairDead (PAIR_DE, ic), isPairDead (PAIR_IY, ic));
       else
         while (size--)
           {
-            /* PENDING: do this check better */
-            if ((IS_GB || IY_RESERVED) && requiresHL (AOP (right)) && requiresHL (AOP (result)))
+            const bool hl_free = hl_dead &&
+              (right->aop->regs[L_IDX] <= offset) && (right->aop->regs[H_IDX] <= offset) &&
+              (result->aop->regs[L_IDX] < 0 || result->aop->regs[L_IDX] >= offset) && (result->aop->regs[H_IDX] < 0 || result->aop->regs[H_IDX] >= offset);
+            const bool save_hl = !hl_free && ((IS_SM83 || IY_RESERVED) && (requiresHL (right->aop) || requiresHL (result->aop)));
+
+            if (save_hl)
+              _push (PAIR_HL);
+            cheapMove (result->aop, offset, right->aop, offset, isRegDead (A_IDX, ic));
+            if (save_hl)
               {
-                _push (PAIR_HL);
-                cheapMove (ASMOP_A, 0, AOP (right), offset, true);
-                cheapMove (AOP (result), offset, ASMOP_A, 0, true);
                 _pop (PAIR_HL);
                 spillPair (PAIR_HL);
               }
-            else
-              cheapMove (AOP (result), offset, AOP (right), offset, true);
             offset++;
           }
     }
@@ -11670,9 +14419,9 @@
   aopOp (jtcond, ic, FALSE, FALSE);
 
   // Choose extra pair DE or BC for addition
-  if (AOP_TYPE (jtcond) == AOP_REG && AOP (jtcond)->aopu.aop_reg[0]->rIdx == E_IDX && isPairDead (PAIR_DE, ic))
+  if (jtcond->aop->type == AOP_REG && jtcond->aop->aopu.aop_reg[0]->rIdx == E_IDX && isPairDead (PAIR_DE, ic))
     pair = PAIR_DE;
-  else if (AOP_TYPE (jtcond) == AOP_REG && AOP (jtcond)->aopu.aop_reg[0]->rIdx == C_IDX && isPairDead (PAIR_BC, ic))
+  else if (jtcond->aop->type == AOP_REG && jtcond->aop->aopu.aop_reg[0]->rIdx == C_IDX && isPairDead (PAIR_BC, ic))
     pair = PAIR_BC;
   else if ((pair = getDeadPairId (ic)) == PAIR_INVALID)
     pair = PAIR_DE;
@@ -11683,7 +14432,7 @@
       pushed_pair = TRUE;
     }
 
-  cheapMove (pair == PAIR_DE ? ASMOP_E : ASMOP_C, 0, AOP (jtcond), 0, true);
+  cheapMove (pair == PAIR_DE ? ASMOP_E : ASMOP_C, 0, jtcond->aop, 0, true);
   if (!regalloc_dry_run)
     {
       emit2 ("ld %s, !zero", _pairs[pair].h);
@@ -11706,7 +14455,7 @@
 
   if (!regalloc_dry_run)
     {
-      emit2 ("jp !*hl");
+      emit2 ("!jphl");
       emitLabelSpill (jtab);
     }
   regalloc_dry_run_cost += 1;
@@ -11726,8 +14475,8 @@
   operand *result = IC_RESULT (ic);
   sym_link *rtype = operandType (IC_RIGHT (ic));
   operand *right = IC_RIGHT (ic);
-  int size, offset;
-  bool surviving_a = !options.oldralloc && bitVectBitValue (ic->rSurv, A_IDX);
+  int size;
+  bool surviving_a = !isRegDead (A_IDX, ic);
   bool pushed_a = FALSE;
 
   /* if they are equivalent then do nothing */
@@ -11738,18 +14487,18 @@
   aopOp (result, ic, FALSE, FALSE);
 
   /* if the result is a bit */
-  if (AOP_TYPE (result) == AOP_CRY)
+  if (result->aop->type == AOP_CRY)
     {
       wassertl (0, "Tried to cast to a bit");
     }
 
   /* casting to bool */
-  if (IS_BOOL (operandType (result)) && IS_RAB && right->aop->size == 2 && 
+  if (IS_BOOL (operandType (result)) && IS_RAB && right->aop->size == 2 &&
     (aopInReg (right->aop, 0, HL_IDX) && isPairDead (PAIR_HL, ic)|| aopInReg (right->aop, 0, IY_IDX) && isPairDead (PAIR_IY, ic)))
     {
       bool iy = aopInReg (right->aop, 0, IY_IDX);
       emit2 ("bool %s", _pairs[getPairId (right->aop)].name);
-      cheapMove (result->aop, 0, iy ? ASMOP_IYL : ASMOP_L, 0, !bitVectBitValue (ic->rSurv, A_IDX));
+      cheapMove (result->aop, 0, iy ? ASMOP_IYL : ASMOP_L, 0, isRegDead (A_IDX, ic));
       goto release;
     }
   if (IS_BOOL (operandType (result)))
@@ -11760,41 +14509,64 @@
     }
 
   /* if they are the same size or less */
-  if (AOP_SIZE (result) <= AOP_SIZE (right))
+  if (result->aop->size <= right->aop->size)
     {
       genAssign (ic);
       goto release;
     }
 
-  /* So we now know that the size of destination is greater
-     than the size of the source */
-  genMove_o (result->aop, 0, right->aop, 0, right->aop->size - 1, true, isPairDead (PAIR_HL, ic));
+  // Now we know that the size of destination is greater than the size of the source
 
   /* now depending on the sign of the destination */
   size = result->aop->size - right->aop->size;
-  offset = right->aop->size - 1;
+  
   /* Unsigned or not an integral type - fill with zeros */
-  if (IS_BOOL (rtype) || !IS_SPEC (rtype) || SPEC_USIGN (rtype) || AOP_TYPE (right) == AOP_CRY)
+  if (IS_BOOL (rtype) || !IS_SPEC (rtype) || SPEC_USIGN (rtype) || right->aop->type == AOP_CRY)
     {
-      cheapMove (result->aop, offset, right->aop, offset, true);
-      offset++;
-      genMove_o (result->aop, offset, ASMOP_ZERO, 0, size, true, false);
+      genMove_o (result->aop, 0, right->aop, 0, right->aop->size, !surviving_a, isPairDead (PAIR_HL, ic), isPairDead (PAIR_DE, ic), isPairDead (PAIR_IY, ic), true);
+      surviving_a |= (result->aop->regs[A_IDX] >= 0 && result->aop->regs[A_IDX] < right->aop->size);
+      bool hl_dead = isPairDead (PAIR_HL, ic) && (result->aop->regs[L_IDX] < 0 || result->aop->regs[L_IDX] >= right->aop->size) && (result->aop->regs[H_IDX] < 0 || result->aop->regs[H_IDX] >= right->aop->size);
+      bool de_dead = isPairDead (PAIR_DE, ic) && (result->aop->regs[E_IDX] < 0 || result->aop->regs[E_IDX] >= right->aop->size) && (result->aop->regs[D_IDX] < 0 || result->aop->regs[D_IDX] >= right->aop->size);
+      bool iy_dead = isPairDead (PAIR_DE, ic) && (result->aop->regs[IYL_IDX] < 0 || result->aop->regs[IYL_IDX] >= right->aop->size) && (result->aop->regs[IYH_IDX] < 0 || result->aop->regs[IYH_IDX] >= right->aop->size);
+      genMove_o (result->aop, right->aop->size, ASMOP_ZERO, 0, size, !surviving_a, hl_dead, de_dead, iy_dead, true);
     }
   else
     {
+      genMove_o (result->aop, 0, right->aop, 0, right->aop->size - 1, !surviving_a, isPairDead (PAIR_HL, ic), isPairDead (PAIR_DE, ic), isPairDead (PAIR_IY, ic), true);
+      if (result->aop->type == AOP_REG && right->aop->type == AOP_REG && // Overwritten last byte of right operand
+        result->aop->regs[right->aop->aopu.aop_reg[right->aop->size - 1]->rIdx] >= 0 && result->aop->regs[right->aop->aopu.aop_reg[right->aop->size - 1]->rIdx] < right->aop->size - 1)
+        UNIMPLEMENTED;
+      int offset = right->aop->size - 1;
+      surviving_a |= (result->aop->regs[A_IDX] >= 0 && result->aop->regs[A_IDX] < offset);
       if (surviving_a && !pushed_a)
-        _push (PAIR_AF), pushed_a = TRUE;
+        _push (PAIR_AF), pushed_a = true;
 
-      cheapMove (ASMOP_A, 0, AOP (right), offset, true);
-      if (AOP (right)->type != AOP_REG || AOP (result)->type != AOP_REG || AOP (right)->aopu.aop_reg[offset] != AOP (result)->aopu.aop_reg[offset])
-        cheapMove (AOP (result), offset, ASMOP_A, 0, true);
+      cheapMove (ASMOP_A, 0, right->aop, offset, true);
+      if (right->aop->type != AOP_REG || result->aop->type != AOP_REG || right->aop->aopu.aop_reg[offset] != result->aop->aopu.aop_reg[offset])
+        cheapMove (result->aop, offset, ASMOP_A, 0, true);
       offset++;
+      
+      surviving_a |= (result->aop->regs[A_IDX] >= 0 && result->aop->regs[A_IDX] < offset);
+      if (surviving_a && !pushed_a)
+        _push (PAIR_AF), pushed_a = true;
 
       /* we need to extend the sign */
-      emit3 (A_RLA, 0, 0);
-      emit3 (A_SBC, ASMOP_A, ASMOP_A);
-      while (size--)
-        cheapMove (AOP (result), offset++, ASMOP_A, 0, true);
+      emit3 (A_RLCA, 0, 0);
+
+      if (!IS_SM83 && isPairDead (PAIR_HL, ic) && size == 2 && /* writing AOP_HL is so cheap, it is not worth the 2-byte sbc hl, hl here */
+        (aopInReg (result->aop, offset, HL_IDX) || result->aop->type == AOP_IY || (IS_RAB || IS_TLCS90 || IS_EZ80_Z80) && result->aop->type == AOP_STK))
+        {
+          emit2 ("sbc hl, hl");
+          regalloc_dry_run_cost += 2;
+          spillPair (PAIR_HL);
+          genMove_o (result->aop, offset, ASMOP_HL, 0, 2, true, true, isPairDead (PAIR_DE, ic), true, false);
+        }
+      else
+        {
+          emit3 (A_SBC, ASMOP_A, ASMOP_A);
+          while (size--)
+            cheapMove (result->aop, offset++, ASMOP_A, 0, true);
+        }
     }
 
 release:
@@ -11813,7 +14585,27 @@
   operand *result = IC_RESULT (ic);
   aopOp (result, ic, FALSE, FALSE);
   
-  genMove (result->aop, ASMOP_RETURN, true, isPairDead (PAIR_HL, ic));
+  wassert (currFunc && ic->argreg);
+
+  bool dead_regs[IYH_IDX + 1];
+  
+  for (int i = 0; i <= IYH_IDX; i++)
+    dead_regs[i] = isRegDead (i, ic);
+
+  for(iCode *nic = ic->next; nic && nic->op == RECEIVE; nic = nic->next)
+    {
+      asmop *narg = aopArg (currFunc->type, nic->argreg);
+      wassert (narg);
+      for (int i = 0; i < narg->size; i++)
+        dead_regs[narg->aopu.aop_reg[i]->rIdx] = false;
+    }
+    
+  if (result->aop->type == AOP_REG)
+    for (int i = 0; i < result->aop->size; i++)
+      if (!dead_regs[result->aop->aopu.aop_reg[i]->rIdx])
+        UNIMPLEMENTED;
+
+  genMove (result->aop, aopArg (currFunc->type, ic->argreg), dead_regs[A_IDX], dead_regs[L_IDX] && dead_regs[H_IDX], dead_regs[E_IDX] && dead_regs[D_IDX], true);
 
   freeAsmop (IC_RESULT (ic), NULL);
 }
@@ -11833,12 +14625,12 @@
       aopOp (op, ic, FALSE, FALSE);
 
       /* general case */
-      size = AOP_SIZE (op);
+      size = op->aop->size;
       offset = 0;
 
       while (size--)
         {
-          _moveA3 (AOP (op), offset);
+          _moveA3 (op->aop, offset);
           offset++;
         }
 
@@ -11851,12 +14643,12 @@
       aopOp (op, ic, FALSE, FALSE);
 
       /* general case */
-      size = AOP_SIZE (op);
+      size = op->aop->size;
       offset = 0;
 
       while (size--)
         {
-          _moveA3 (AOP (op), offset);
+          _moveA3 (op->aop, offset);
           offset++;
         }
 
@@ -11872,7 +14664,7 @@
 {
   symbol *tlbl = regalloc_dry_run ? 0 : newiTempLabel (0);
 
-  if (IS_GB || IS_RAB || IS_TLCS90)
+  if (IS_SM83 || IS_RAB || IS_TLCS90)
     {
       emit2 ("!di");
       regalloc_dry_run_cost += 1;
@@ -11883,11 +14675,17 @@
       cheapMove (IC_RESULT (ic)->aop, 0, ASMOP_ZERO, 0, true);
       if (!regalloc_dry_run)
         {
-          //get interrupt enable flag IFF2 into P/O
-          emit2 ("ld a,i");
-
-          //disable interrupt
-          emit2 ("!di");
+          if (z80_opts.nmosZ80)
+            {
+              emit2 ("call ___sdcc_critical_enter");
+            }
+          else
+            {
+              //get interrupt enable flag IFF2 into P/O
+              emit2 ("ld a,i");
+              //disable interrupt
+              emit2 ("!di");
+            }
           //parity odd <==> P/O=0 <==> interrupt enable flag IFF2=0
           emit2 ("jp PO, !tlabel", labelKey2num (tlbl->key));
         }
@@ -11902,12 +14700,16 @@
     }
   else
     {
-      //get interrupt enable flag IFF2 into P/O
-      emit2 ("ld a,i");
-
-      //disable interrupt
-      emit2 ("!di");
-      regalloc_dry_run_cost += 2;
+      if (z80_opts.nmosZ80)
+        emit2 ("call ___sdcc_critical_enter");
+      else
+        {
+          //get interrupt enable flag IFF2 into P/O
+          emit2 ("ld a,i");
+          //disable interrupt
+          emit2 ("!di");
+        }
+      regalloc_dry_run_cost += 3;
       //save P/O flag
       if (!regalloc_dry_run)    // _push unbalances _G.stack.pushed.
         _push (PAIR_AF);
@@ -11924,7 +14726,7 @@
 {
   symbol *tlbl = regalloc_dry_run ? 0 : newiTempLabel (0);
 
-  if (IS_GB || IS_TLCS90)
+  if (IS_SM83 || IS_TLCS90)
     {
       emit2 ("!ei");
       regalloc_dry_run_cost += 1;
@@ -11969,7 +14771,6 @@
     }
 }
 
-#if 0                           //Disabled since it doesn't work for arrays of float.
 enum
 {
   /** Maximum number of bytes to emit per line. */
@@ -11995,11 +14796,11 @@
   if (self->pos > 0)
     {
       int i;
-      sprintf (line, ".db 0x%02X", self->buffer[0]);
+      sprintf (line, ".db !immed%d", self->buffer[0]);
 
       for (i = 1; i < self->pos; i++)
         {
-          sprintf (line + strlen (line), ", 0x%02X", self->buffer[i]);
+          sprintf (line + strlen (line), ", !immed%d", self->buffer[i]);
         }
       emit2 (line);
     }
@@ -12047,7 +14848,7 @@
       DBEMITCTX db;
       memset (&db, 0, sizeof (db));
 
-      emit2 (".db %u", self->pos);
+      emit2 (".db !immed%u", self->pos);
 
       for (i = 0; i < self->pos; i++)
         {
@@ -12095,7 +14896,7 @@
           /* Yes, worthwhile. */
           /* Commit whatever was in the buffer. */
           _rleCommit (self);
-          emit2 ("!db !immed-%u,!immedbyte", self->runLen, self->last);
+          emit2 ("!db !immed-%u, !immedbyte", self->runLen, self->last);
         }
       else
         {
@@ -12120,7 +14921,7 @@
           /* Commit whatever was in the buffer. */
           _rleCommit (self);
 
-          emit2 ("!db !immed-%u,!immedbyte", self->runLen, self->last);
+          emit2 ("!db !immed-%u, !immedbyte", self->runLen, self->last);
           self->runLen = 0;
         }
       self->runLen++;
@@ -12147,17 +14948,35 @@
   literalList *iLoop;
   int ix;
   int elementSize = 0, eIndex, i;
-  unsigned val, lastVal;
   sym_link *type;
   RLECTX rle;
+  bool isBool = FALSE;
+  bool isFloat = FALSE;
+  bool saved_BC = FALSE;
+  bool saved_DE = FALSE;
+  bool saved_HL = FALSE;
 
   memset (&rle, 0, sizeof (rle));
 
   aopOp (IC_LEFT (ic), ic, FALSE, FALSE);
 
-  _saveRegsForCall (ic, 0);
+  if (!isPairDead (PAIR_HL, ic))
+    {
+      _push (PAIR_HL);
+      saved_HL = TRUE;
+    }
+  if (!isPairDead (PAIR_DE, ic))
+    {
+      _push (PAIR_DE);
+      saved_DE = TRUE;
+    }
+  if (!isPairDead (PAIR_BC, ic))
+    {
+      _push (PAIR_BC);
+      saved_BC = TRUE;
+    }
 
-  fetchPair (PAIR_HL, AOP (IC_LEFT (ic)));
+  fetchPair (PAIR_DE, IC_LEFT (ic)->aop);
   emit2 ("call __initrleblock");
 
   type = operandType (IC_LEFT (ic));
@@ -12167,10 +14986,14 @@
       if (IS_SPEC (type->next) || IS_PTR (type->next))
         {
           elementSize = getSize (type->next);
+          isBool = IS_BOOL (type->next);
+          isFloat = IS_FLOAT (type->next);
         }
       else if (IS_ARRAY (type->next) && type->next->next)
         {
           elementSize = getSize (type->next->next);
+          isBool = IS_BOOL (type->next->next);
+          isFloat = IS_FLOAT (type->next->next);
         }
       else
         {
@@ -12183,10 +15006,9 @@
       wassertl (0, "Can't determine element size in genArrayInit.");
     }
 
-  wassertl ((elementSize > 0) && (elementSize <= 4), "Illegal element size in genArrayInit.");
+  wassertl ((elementSize > 0) && (elementSize <= 8), "Illegal element size in genArrayInit.");
 
   iLoop = IC_ARRAYILIST (ic);
-  lastVal = (unsigned) - 1;
 
   /* Feed all the bytes into the run length encoder which will handle
      the actual output.
@@ -12199,11 +15021,34 @@
 
       for (i = 0; i < ix; i++)
         {
-          for (eIndex = 0; eIndex < elementSize; eIndex++)
+          union
             {
-              val = (((int) iLoop->literalValue) >> (eIndex * 8)) & 0xff;
-              _rleAppend (&rle, val);
+              unsigned char c[sizeof(unsigned long long)];
+              float f;
+              unsigned long long ull;
             }
+            buf;
+            if (isFloat)
+              {
+                if (iLoop->isFloat)
+                  buf.f = iLoop->value.f64;
+                else
+                  buf.f = iLoop->value.ull;
+              }
+            else
+              {
+                if (iLoop->isFloat)
+                  buf.ull = (isBool) ? !!iLoop->value.f64 : (unsigned long long)iLoop->value.f64;
+                else
+                  buf.ull = (isBool) ? !!iLoop->value.ull : iLoop->value.ull;
+              }
+            
+#ifdef WORDS_BIGENDIAN
+          for (eIndex = elementSize-1; eIndex >= 0; eIndex--)
+#else
+          for (eIndex = 0; eIndex < elementSize; eIndex++)
+#endif
+            _rleAppend (&rle, buf.c[eIndex]);
         }
 
       iLoop = iLoop->next;
@@ -12211,59 +15056,102 @@
 
   _rleFlush (&rle);
   /* Mark the end of the run. */
-  emit2 (".db 0");
-
-  _restoreRegsAfterCall ();
+  emit2 (".db !zero");
 
   spillCached ();
 
-  freeAsmop (IC_LEFT (ic), NULL, ic);
+  if (saved_BC)
+    _pop (PAIR_BC);
+
+  if (saved_DE)
+    _pop (PAIR_DE);
+
+  if (saved_HL)
+    _pop (PAIR_HL);
+
+  freeAsmop (IC_LEFT (ic), NULL);
 }
-#endif
 
 static void
-setupForMemcpy (const iCode *ic, const operand *to, const operand *from)
+setupForMemcpy (const iCode *ic, const operand *to, const operand *from, const operand *count)
 {
   /* Both are in regs. Let regMove() do the shuffling. */
-  if (AOP_TYPE (to) == AOP_REG && AOP_TYPE (from) == AOP_REG)
+  if (to->aop->type == AOP_REG && from->aop->type == AOP_REG)
+    {
+      const short larray[6] = {E_IDX, D_IDX, L_IDX, H_IDX, C_IDX, B_IDX};
+      short oparray[6];
+      oparray[0] = to->aop->aopu.aop_reg[0]->rIdx;
+      oparray[1] = to->aop->aopu.aop_reg[1]->rIdx;
+      oparray[2] = from->aop->aopu.aop_reg[0]->rIdx;
+      oparray[3] = from->aop->aopu.aop_reg[1]->rIdx;
+      if (count && count->aop->type == AOP_REG)
+        {
+          oparray[4] = count->aop->aopu.aop_reg[0]->rIdx;
+          oparray[5] = count->aop->aopu.aop_reg[1]->rIdx;
+        }
+
+      regMove (larray, oparray, 4 + (count && count->aop->type == AOP_REG) * 2, false);
+    }
+  else if (to->aop->type == AOP_REG && count && count->aop->type == AOP_REG)
     {
-      const short larray[4] = {E_IDX, D_IDX, L_IDX, H_IDX};
+      const short larray[4] = {E_IDX, D_IDX, C_IDX, B_IDX};
       short oparray[4];
-      oparray[0] = AOP (to)->aopu.aop_reg[0]->rIdx;
-      oparray[1] = AOP (to)->aopu.aop_reg[1]->rIdx;
-      oparray[2] = AOP (from)->aopu.aop_reg[0]->rIdx;
-      oparray[3] = AOP (from)->aopu.aop_reg[1]->rIdx;
+      oparray[0] = to->aop->aopu.aop_reg[0]->rIdx;
+      oparray[1] = to->aop->aopu.aop_reg[1]->rIdx;
+      oparray[2] = count->aop->aopu.aop_reg[0]->rIdx;
+      oparray[3] = count->aop->aopu.aop_reg[1]->rIdx;
 
-      regMove (larray, oparray, 4, FALSE);
+      regMove (larray, oparray, 4 , false);
+
+      fetchPair (PAIR_HL, from->aop);
+    }
+  else if (from->aop->type == AOP_REG && count && count->aop->type == AOP_REG)
+    {
+      const short larray[4] = {L_IDX, H_IDX, C_IDX, B_IDX};
+      short oparray[4];
+      oparray[0] = from->aop->aopu.aop_reg[0]->rIdx;
+      oparray[1] = from->aop->aopu.aop_reg[1]->rIdx;
+      oparray[2] = count->aop->aopu.aop_reg[0]->rIdx;
+      oparray[3] = count->aop->aopu.aop_reg[1]->rIdx;
+
+      regMove (larray, oparray, 4 , false);
+
+      fetchPair (PAIR_DE, to->aop);
+    }
+  else if (count && count->aop->type == AOP_REG)
+    {
+      fetchPair (PAIR_BC, count->aop);
+      fetchPair (PAIR_DE, to->aop);
+      fetchPair (PAIR_HL, from->aop);
     }
   else
     {
       /* DE is free. Write it first. */
-      if (AOP_TYPE (from) != AOP_REG || AOP (from)->aopu.aop_reg[0]->rIdx != E_IDX && AOP (from)->aopu.aop_reg[0]->rIdx != D_IDX && AOP (from)->aopu.aop_reg[1]->rIdx != E_IDX && AOP (from)->aopu.aop_reg[1]->rIdx != D_IDX)
+      if (from->aop->type != AOP_REG || from->aop->aopu.aop_reg[0]->rIdx != E_IDX && from->aop->aopu.aop_reg[0]->rIdx != D_IDX && from->aop->aopu.aop_reg[1]->rIdx != E_IDX && from->aop->aopu.aop_reg[1]->rIdx != D_IDX)
         {
-          fetchPair (PAIR_DE, AOP (to));
-          fetchPair (PAIR_HL, AOP (from));
+          fetchPair (PAIR_DE, to->aop);
+          fetchPair (PAIR_HL, from->aop);
         }
       /* HL is free. Write it first. */
-      else if (AOP_TYPE (to) != AOP_REG || AOP (to)->aopu.aop_reg[0]->rIdx != L_IDX && AOP (to)->aopu.aop_reg[0]->rIdx != H_IDX && AOP (to)->aopu.aop_reg[1]->rIdx != L_IDX && AOP (to)->aopu.aop_reg[1]->rIdx != H_IDX)
+      else if (to->aop->type != AOP_REG || to->aop->aopu.aop_reg[0]->rIdx != L_IDX && to->aop->aopu.aop_reg[0]->rIdx != H_IDX && to->aop->aopu.aop_reg[1]->rIdx != L_IDX && to->aop->aopu.aop_reg[1]->rIdx != H_IDX)
         {
-          fetchPair (PAIR_HL, AOP (from));
-          fetchPair (PAIR_DE, AOP (to));
+          fetchPair (PAIR_HL, from->aop);
+          fetchPair (PAIR_DE, to->aop);
         }
       /* L is free, but H is not. */
-      else if ((AOP_TYPE (to) != AOP_REG || AOP (to)->aopu.aop_reg[0]->rIdx != L_IDX && AOP (to)->aopu.aop_reg[1]->rIdx != L_IDX) &&
-        (AOP_TYPE (from) != AOP_REG || AOP (from)->aopu.aop_reg[0]->rIdx != L_IDX && AOP (from)->aopu.aop_reg[1]->rIdx != L_IDX))
+      else if ((to->aop->type != AOP_REG || to->aop->aopu.aop_reg[0]->rIdx != L_IDX && to->aop->aopu.aop_reg[1]->rIdx != L_IDX) &&
+        (from->aop->type != AOP_REG || from->aop->aopu.aop_reg[0]->rIdx != L_IDX && from->aop->aopu.aop_reg[1]->rIdx != L_IDX))
         {
-          cheapMove (ASMOP_L, 0, AOP (from), 0, true);
-          fetchPair (PAIR_DE, AOP (to));
-          cheapMove (ASMOP_H, 0, AOP (from), 1, true);
+          cheapMove (ASMOP_L, 0, from->aop, 0, true);
+          fetchPair (PAIR_DE, to->aop);
+          cheapMove (ASMOP_H, 0, from->aop, 1, true);
         }
       /* H is free, but L is not. */
       else
         {
-          cheapMove (ASMOP_H, 0, AOP (from), 1, true);
-          fetchPair (PAIR_DE, AOP (to));
-          cheapMove (ASMOP_L, 0, AOP (from), 0, true);
+          cheapMove (ASMOP_H, 0, from->aop, 1, true);
+          fetchPair (PAIR_DE, to->aop);
+          cheapMove (ASMOP_L, 0, from->aop, 0, true);
         }
     }
 }
@@ -12279,16 +15167,16 @@
   for (i = 0; i < nparams; i++)
     aopOp (pparams[i], ic, FALSE, FALSE);
 
-  wassertl (!IS_GB, "Built-in memcpy() not available on gbz80.");
+  wassertl (!IS_SM83, "Built-in memcpy() not available on sm83.");
   wassertl (nparams == 3, "Built-in memcpy() must have three parameters.");
-  /* Check for zero length copy. */
-  wassertl (AOP_TYPE (pparams[2]) == AOP_LIT, "Last parameter to builtin memcpy() must be literal.");
 
   count = pparams[2];
   from = pparams[1];
   to = pparams[0];
 
-  if (!(n = (unsigned int) ulFromVal (AOP (pparams[2])->aopu.aop_lit)))
+  if (pparams[2]->aop->type != AOP_LIT)
+    n = UINT_MAX;
+  else if (!(n = (unsigned int) ulFromVal (pparams[2]->aop->aopu.aop_lit))) /* Check for zero length copy. */
     goto done;
 
   if (!isPairDead (PAIR_HL, ic))
@@ -12307,19 +15195,19 @@
       saved_BC = TRUE;
     }
 
- setupForMemcpy (ic, to, from);
+ setupForMemcpy (ic, to, from, count);
 
   if (n == 1)
     {
-      emit2 ("ld a, (hl)");
-      emit2 ("ld (de), a");
+      emit2 ("ld a, !*hl");
+      emit2 ("ld !mems, a", "de");
       regalloc_dry_run_cost += 2;
     }
   else if (n == 2)
     {
       emit2 ("ldi");
-      emit2 ("ld a, (hl)");
-      emit2 ("ld (de), a");
+      emit2 ("ld a, !*hl");
+      emit2 ("ld !mems, a", "de");
       regalloc_dry_run_cost += 4;
       if (!isPairDead (PAIR_BC, ic)) /* Restore bc. */
         {
@@ -12327,11 +15215,63 @@
           regalloc_dry_run_cost++;
         }
     }
+  else if (n <= 4 && IS_Z80 && optimize.codeSpeed || (IS_R2K || IS_R2KA) && n <= 5)
+    {
+      for(unsigned int i = 0; i < n; i++)
+        emit2 ("ldi");
+      regalloc_dry_run_cost += n * 2;
+    }
   else
     {
-      fetchPair (PAIR_BC, AOP (count));
-      emit2 ("ldir");
-      regalloc_dry_run_cost += 2;
+      symbol *tlbl = 0;
+      if (count->aop->type != AOP_REG) // If in reg: Has been fetched early by setupForMemcpy() above.
+        fetchPair (PAIR_BC, count->aop);
+      if (count->aop->type != AOP_LIT)
+        {
+          if (!regalloc_dry_run)
+            {
+              tlbl = newiTempLabel (0);
+              emit2 ("ld a, b");
+              emit2 ("or a, c");
+              emit2 ("jp Z, !tlabel", labelKey2num (tlbl->key));
+            }
+          regalloc_dry_run_cost += 5;
+        }
+      if ((IS_R2K || IS_R2KA) && optimize.codeSpeed && n != UINT_MAX) // Work around ldir wait state bug, but care for speed
+        {
+          wassert (n > 3);
+          if (n % 2)
+            {
+              emit2 ("ldi");
+              regalloc_dry_run_cost += 2;
+            }
+          if (!regalloc_dry_run)
+            {
+              const symbol *tlbl2 = newiTempLabel (0);
+              emitLabel (tlbl2);
+              emit2("ldi");
+              emit2("ldi");
+              emit2 ("jp LO, !tlabel", labelKey2num (tlbl2->key));
+            }
+          regalloc_dry_run_cost += 7;         
+        }
+      else if (IS_R2K || IS_R2KA) // Work around ldir wait state bug.
+        {
+          if (!regalloc_dry_run)
+            {
+              const symbol *tlbl2 = newiTempLabel (0);
+              emitLabel (tlbl2);
+              emit2("ldi");
+              emit2 ("jp LO, !tlabel", labelKey2num (tlbl2->key));
+            }
+          regalloc_dry_run_cost += 5;
+        }
+      else
+        {
+          emit2 ("ldir");
+          regalloc_dry_run_cost += 2;
+        }
+      emitLabel (tlbl);
     }
 
   spillPair (PAIR_HL);
@@ -12355,41 +15295,41 @@
 setupForMemset (const iCode *ic, const operand *dst, const operand *c, bool direct_c)
 {
   /* Both are in regs. Let regMove() do the shuffling. */
-  if (AOP_TYPE (dst) == AOP_REG && !direct_c && AOP_TYPE (c) == AOP_REG)
+  if (dst->aop->type == AOP_REG && !direct_c && c->aop->type == AOP_REG)
     {
       const short larray[2] = {L_IDX, H_IDX};
       short oparray[2];
-      bool early_a = AOP_TYPE (c) == AOP_REG && (AOP (c)->aopu.aop_reg[0]->rIdx == L_IDX || AOP (c)->aopu.aop_reg[0]->rIdx == H_IDX);
+      bool early_a = c->aop->type == AOP_REG && (c->aop->aopu.aop_reg[0]->rIdx == L_IDX || c->aop->aopu.aop_reg[0]->rIdx == H_IDX);
 
       if (early_a)
-        cheapMove (ASMOP_A, 0, AOP (c), 0, true);
+        cheapMove (ASMOP_A, 0, c->aop, 0, true);
 
-      oparray[0] = AOP (dst)->aopu.aop_reg[0]->rIdx;
-      oparray[1] = AOP (dst)->aopu.aop_reg[1]->rIdx;
+      oparray[0] = dst->aop->aopu.aop_reg[0]->rIdx;
+      oparray[1] = dst->aop->aopu.aop_reg[1]->rIdx;
 
       regMove (larray, oparray, 2, early_a);
 
       if (!early_a)
-        cheapMove (ASMOP_A, 0, AOP (c), 0, true);
+        cheapMove (ASMOP_A, 0, c->aop, 0, true);
     }
-  else if (AOP_TYPE (c) == AOP_REG && requiresHL (AOP (c)))
+  else if (c->aop->type == AOP_REG && requiresHL (c->aop))
     {
-      cheapMove (ASMOP_A, 0, AOP (c), 0, true);
-      if (AOP_TYPE (dst) == AOP_EXSTK)
+      cheapMove (ASMOP_A, 0, c->aop, 0, true);
+      if (dst->aop->type == AOP_EXSTK)
         _push (PAIR_AF);
-      fetchPair (PAIR_HL, AOP (dst));
-      if (AOP_TYPE (dst) == AOP_EXSTK)
+      fetchPair (PAIR_HL, dst->aop);
+      if (dst->aop->type == AOP_EXSTK)
         _pop (PAIR_AF);
     }
   else
     {
-      fetchPair (PAIR_HL, AOP (dst));
+      fetchPair (PAIR_HL, dst->aop);
       if (!direct_c)
         {
-          if (requiresHL (AOP (c)))
+          if (requiresHL (c->aop))
             _push (PAIR_HL);
-          cheapMove (ASMOP_A, 0, AOP (c), 0, true);
-          if (requiresHL (AOP (c)))
+          cheapMove (ASMOP_A, 0, c->aop, 0, true);
+          if (requiresHL (c->aop))
             _pop (PAIR_HL);
         }
     }
@@ -12405,7 +15345,7 @@
   unsigned long sizecost_ldir, sizecost_direct, sizecost_loop;
   bool double_loop;
   unsigned size;
-  bool live_BC = !isPairDead (PAIR_BC, ic), live_DE = !isPairDead (PAIR_DE, ic), live_HL = !isPairDead (PAIR_HL, ic), live_B = bitVectBitValue (ic->rSurv, B_IDX);
+  bool live_BC = !isPairDead (PAIR_BC, ic), live_DE = !isPairDead (PAIR_DE, ic), live_HL = !isPairDead (PAIR_HL, ic), live_B = !isRegDead (B_IDX, ic);
   bool saved_BC = FALSE, saved_DE = FALSE, saved_HL = FALSE;
 
   wassertl (nParams == 3, "Built-in memset() must have three parameters");
@@ -12418,23 +15358,27 @@
   aopOp (dst, ic, FALSE, FALSE);
   aopOp (n, ic, FALSE, FALSE);
 
-  wassertl (AOP_TYPE (n) == AOP_LIT, "Last parameter to builtin memset() must be literal.");
-  if(!(size = ulFromVal (AOP (n)->aopu.aop_lit)))
+  wassertl (n->aop->type == AOP_LIT, "Last parameter to builtin memset() must be literal.");
+
+  if(n->aop->type != AOP_LIT || !(size = ulFromVal (n->aop->aopu.aop_lit)))
     goto done;
 
-  direct_c = (AOP_TYPE (c) == AOP_LIT || AOP_TYPE (c) == AOP_REG && AOP (c)->aopu.aop_reg[0]->rIdx != H_IDX
-              && AOP (c)->aopu.aop_reg[0]->rIdx != L_IDX);
-  direct_cl = (AOP_TYPE (c) == AOP_LIT || AOP_TYPE (c) == AOP_REG && AOP (c)->aopu.aop_reg[0]->rIdx != H_IDX
-              && AOP (c)->aopu.aop_reg[0]->rIdx != L_IDX && AOP (c)->aopu.aop_reg[0]->rIdx != B_IDX);
-  indirect_c = IS_R3KA && ulFromVal (AOP (n)->aopu.aop_lit) > 1 && AOP_TYPE (c) == AOP_IY;
+  direct_c = (c->aop->type == AOP_LIT || c->aop->type == AOP_REG &&
+              c->aop->aopu.aop_reg[0]->rIdx != H_IDX && c->aop->aopu.aop_reg[0]->rIdx != L_IDX &&
+              c->aop->aopu.aop_reg[0]->rIdx != IYH_IDX && c->aop->aopu.aop_reg[0]->rIdx != IYL_IDX);
+  direct_cl = (c->aop->type == AOP_LIT || c->aop->type == AOP_REG &&
+              c->aop->aopu.aop_reg[0]->rIdx != H_IDX && c->aop->aopu.aop_reg[0]->rIdx != L_IDX &&
+              c->aop->aopu.aop_reg[0]->rIdx != IYH_IDX && c->aop->aopu.aop_reg[0]->rIdx != IYL_IDX &&
+              c->aop->aopu.aop_reg[0]->rIdx != B_IDX);
+  indirect_c = IS_R3KA && ulFromVal (n->aop->aopu.aop_lit) > 1 && c->aop->type == AOP_IY;
 
   double_loop = (size > 255 || optimize.codeSpeed);
 
-  sizecost_direct = 3 + 2 * size - 1 + !direct_c * ld_cost (ASMOP_A, AOP (c));
+  sizecost_direct = 3 + 2 * size - 1 + !direct_c * ld_cost (ASMOP_A, 0, c->aop, 0);
   sizecost_direct += (live_HL) * 2;
-  sizecost_loop = 9 + double_loop * 2 + ((size % 2) && double_loop) * 2 + !direct_cl * ld_cost (ASMOP_A, AOP (c));
+  sizecost_loop = 9 + double_loop * 2 + ((size % 2) && double_loop) * 2 + !direct_cl * ld_cost (ASMOP_A, 0, c->aop, 0);
   sizecost_loop += (live_HL + live_B) * 2;
-  sizecost_ldir = indirect_c ? 11 : (12 + !direct_c * ld_cost (ASMOP_A, AOP (c)) - (IS_R3KA && !optimize.codeSpeed));
+  sizecost_ldir = indirect_c ? 11 : (12 + !direct_c * ld_cost (ASMOP_A, 0, c->aop, 0) - (IS_R3KA && !optimize.codeSpeed));
   sizecost_ldir += (live_HL + live_DE + live_BC) * 2;
 
   if (sizecost_direct <= sizecost_loop && sizecost_direct < sizecost_ldir) // straight-line code.
@@ -12451,7 +15395,7 @@
       if (!regalloc_dry_run)
         while (size--)
 		  {
-            emit2 ("ld (hl), %s", aopGet (direct_c ? AOP (c) : ASMOP_A, 0, FALSE));
+            emit2 ("ld !*hl, %s", aopGet (direct_c ? c->aop : ASMOP_A, 0, FALSE));
             if (size)
               emit2 ("inc hl");
           }
@@ -12466,7 +15410,7 @@
           _push (PAIR_HL);
           saved_HL = TRUE;
         }
-      if (bitVectBitValue (ic->rSurv, B_IDX))
+      if (!isRegDead (B_IDX, ic))
         {
           _push (PAIR_BC);
           saved_BC = TRUE;
@@ -12487,13 +15431,13 @@
       if (!regalloc_dry_run)
         {
           emitLabel (tlbl1);
-          emit2 ("ld (hl), %s", aopGet (direct_cl ? AOP (c) : ASMOP_A, 0, FALSE));
+          emit2 ("ld !*hl, %s", aopGet (direct_cl ? c->aop : ASMOP_A, 0, FALSE));
           emit2 ("inc hl");
           if (double_loop)
             {
               if (size % 2)
                 emitLabel (tlbl2);
-              emit2 ("ld (hl), %s", aopGet (direct_cl ? AOP (c) : ASMOP_A, 0, FALSE));
+              emit2 ("ld !*hl, %s", aopGet (direct_cl ? c->aop : ASMOP_A, 0, FALSE));
               emit2 ("inc hl");
             }
           emit2 ("djnz !tlabel", labelKey2num (tlbl1->key));
@@ -12517,20 +15461,19 @@
           _push (PAIR_BC);
           saved_BC = TRUE;
         }
-	  if (indirect_c)
-		{
-		  fetchPair (PAIR_DE, AOP (dst));
-		  emit2 ("ld hl, #%s", AOP (c)->aopu.aop_dir);
-		  regalloc_dry_run_cost += 3;
-		}
-	  else
-		{
+      if (indirect_c)
+        {
+          fetchPair (PAIR_DE, dst->aop);
+          pointPairToAop (PAIR_HL, c->aop, 0);
+        }
+      else
+        {
 		  setupForMemset (ic, dst, c, direct_c);
 
 		  if (!regalloc_dry_run)
-		    emit2 ("ld (hl), %s", aopGet (direct_c ? AOP (c) : ASMOP_A, 0, FALSE));
-		  regalloc_dry_run_cost += (direct_c && AOP_TYPE (c) == AOP_LIT) ? 2 : 1;
-		  if (ulFromVal (AOP (n)->aopu.aop_lit) <= 1)
+		    emit2 ("ld !*hl, %s", aopGet (direct_c ? c->aop : ASMOP_A, 0, FALSE));
+		  regalloc_dry_run_cost += (direct_c && c->aop->type == AOP_LIT) ? 2 : 1;
+		  if (ulFromVal (n->aop->aopu.aop_lit) <= 1)
 		    goto done;
 
 		  emit2 ("ld e, l");
@@ -12542,10 +15485,25 @@
 		      regalloc_dry_run_cost++;
 		      preinc = TRUE;
 		    }
-		}
-	  emit2 ("ld bc, !immedword", size - preinc);
-	  emit2 (IS_R3KA ? "lsidr" : "ldir");
-	  regalloc_dry_run_cost += 5;
+        }
+      emit2 ("ld bc, !immedword", size - preinc);
+      regalloc_dry_run_cost += 3;
+      if (IS_R2K || IS_R2KA) // Work around ldir wait state bug that affects copies between different types of memory.
+        {
+          if (!regalloc_dry_run)
+            {
+              const symbol *tlbl2 = newiTempLabel (0);
+              emitLabel (tlbl2);
+              emit2("ldi");
+              emit2 ("jp LO, !tlabel", labelKey2num (tlbl2->key));
+            }
+          regalloc_dry_run_cost += 5;
+        }
+      else
+        {
+          emit2 (IS_R3KA ? "lsidr" : "ldir");
+          regalloc_dry_run_cost += 2;
+        }
     }
 
 done:
@@ -12555,7 +15513,7 @@
   freeAsmop (c, NULL);
   freeAsmop (dst, NULL);
 
-  
+
   if (saved_BC)
     _pop (PAIR_BC);
   if (saved_DE)
@@ -12573,14 +15531,12 @@
   bool saved_BC = FALSE, saved_DE = FALSE, saved_HL = FALSE;
   int i;
   bool SomethingReturned;
-  
-  SomethingReturned = (IS_ITEMP (IC_RESULT (ic)) &&
-                      (OP_SYMBOL (IC_RESULT (ic))->nRegs ||
-                      OP_SYMBOL (IC_RESULT (ic))->spildir ||
-                      OP_SYMBOL (IC_RESULT (ic))->accuse == ACCUSE_A)) || IS_TRUE_SYMOP (IC_RESULT (ic));
+
+  SomethingReturned = IS_ITEMP (IC_RESULT (ic)) && (OP_SYMBOL (IC_RESULT (ic))->nRegs || OP_SYMBOL (IC_RESULT (ic))->spildir) ||
+                      IS_TRUE_SYMOP (IC_RESULT (ic));
 
   wassertl (nParams == 2, "Built-in strcpy() must have two parameters.");
-  wassertl (!IS_GB, "Built-in strcpy() not available for gbz80.");
+  wassertl (!IS_SM83, "Built-in strcpy() not available for sm83.");
 
   dst = pparams[0];
   src = pparams[1];
@@ -12604,7 +15560,7 @@
       saved_DE = TRUE;
     }
 
-  setupForMemcpy (ic, dst, src);
+  setupForMemcpy (ic, dst, src, 0);
 
   emit3 (A_XOR, ASMOP_A, ASMOP_A);
   if (SomethingReturned)
@@ -12613,7 +15569,7 @@
     {
       symbol *tlbl = newiTempLabel (NULL);
       emitLabel (tlbl);
-      emit2 ("cp a, (hl)");
+      emit2 ("cp a, !*hl");
       emit2 ("ldi");
       emit2 ("jr NZ, !tlabel", labelKey2num (tlbl->key));
     }
@@ -12624,10 +15580,10 @@
   if (SomethingReturned)
     aopOp (IC_RESULT (ic), ic, FALSE, FALSE);
 
-  if (!SomethingReturned || SomethingReturned && getPairId (AOP (IC_RESULT (ic))) != PAIR_INVALID)
+  if (!SomethingReturned || SomethingReturned && getPairId (IC_RESULT (ic)->aop) != PAIR_INVALID)
     {
       if (SomethingReturned)
-        _pop (getPairId (AOP (IC_RESULT (ic))));
+        _pop (getPairId (IC_RESULT (ic)->aop));
       if (saved_DE)
         _pop (PAIR_DE);
       if (saved_BC)
@@ -12638,7 +15594,7 @@
   else
     {
       _pop (PAIR_HL);
-      assignResultValue (IC_RESULT (ic));
+      genMove (IC_RESULT (ic)->aop, ASMOP_HL, true, true, true, true);
 
       restoreRegs (0, saved_DE, saved_BC, saved_HL, IC_RESULT (ic));
     }
@@ -12659,15 +15615,15 @@
   for (i = 0; i < nparams; i++)
     aopOp (pparams[i], ic, FALSE, FALSE);
 
-  wassertl (!IS_GB, "Built-in strncpy() not available on gbz80.");
+  wassertl (!IS_SM83, "Built-in strncpy() not available on sm83.");
   wassertl (nparams == 3, "Built-in strncpy() must have three parameters.");
-  wassertl (AOP_TYPE (pparams[2]) == AOP_LIT, "Last parameter to builtin strncpy() must be literal.");
+  wassertl (pparams[2]->aop->type == AOP_LIT, "Last parameter to builtin strncpy() must be literal.");
 
   s1 = pparams[0];
   s2 = pparams[1];
   n = pparams[2];
 
-  if (!ulFromVal (AOP (n)->aopu.aop_lit))
+  if (!ulFromVal (n->aop->aopu.aop_lit))
     goto done;
 
   if (!isPairDead (PAIR_HL, ic))
@@ -12686,9 +15642,9 @@
       saved_DE = TRUE;
     }
 
-  setupForMemcpy (ic, s1, s2);
+  setupForMemcpy (ic, s1, s2, 0);
 
-  fetchPair (PAIR_BC, AOP (n));
+  fetchPair (PAIR_BC, n->aop);
 
   emit3 (A_XOR, ASMOP_A, ASMOP_A);
   if (!regalloc_dry_run)
@@ -12697,7 +15653,7 @@
       symbol *tlbl2 = newiTempLabel (0);
       symbol *tlbl3 = newiTempLabel (0);
       emitLabel (tlbl2);
-      emit2 ("cp a, (hl)");
+      emit2 ("cp a,!*hl");
       emit2 ("ldi");
       emit2 (IS_RAB ? "jp LZ, !tlabel" : "jp PO, !tlabel", labelKey2num (tlbl1->key));
       emit2 ("jr NZ, !tlabel", labelKey2num (tlbl2->key));
@@ -12732,10 +15688,8 @@
   symbol *tlbl1 = regalloc_dry_run ? 0 : newiTempLabel(0);
   symbol *tlbl2 = regalloc_dry_run ? 0 : newiTempLabel(0);
 
-  SomethingReturned = (IS_ITEMP (IC_RESULT (ic)) &&
-                      (OP_SYMBOL (IC_RESULT (ic))->nRegs ||
-                      OP_SYMBOL (IC_RESULT (ic))->spildir ||
-                      OP_SYMBOL (IC_RESULT (ic))->accuse == ACCUSE_A)) || IS_TRUE_SYMOP (IC_RESULT (ic));
+  SomethingReturned = IS_ITEMP (IC_RESULT (ic)) && (OP_SYMBOL (IC_RESULT (ic))->nRegs || OP_SYMBOL (IC_RESULT (ic))->spildir) ||
+                      IS_TRUE_SYMOP (IC_RESULT (ic));
 
   wassertl (nParams == 2, "Built-in strchr() must have two parameters.");
 
@@ -12748,24 +15702,24 @@
   if (SomethingReturned)
     aopOp (IC_RESULT (ic), ic, FALSE, FALSE);
 
-  if (getPairId (AOP (s)) != PAIR_INVALID && getPairId (AOP (s)) != PAIR_IY)
-    pair = getPairId (AOP (s));
-  else if (SomethingReturned && getPairId (AOP (IC_RESULT (ic))) != PAIR_INVALID && getPairId (AOP (IC_RESULT (ic))) != PAIR_IY)
-    pair = getPairId (AOP (IC_RESULT (ic)));
+  if (getPairId (s->aop) != PAIR_INVALID && getPairId (s->aop) != PAIR_IY)
+    pair = getPairId (s->aop);
+  else if (SomethingReturned && getPairId (IC_RESULT (ic)->aop) != PAIR_INVALID && getPairId (IC_RESULT (ic)->aop) != PAIR_IY)
+    pair = getPairId (IC_RESULT (ic)->aop);
   else
     pair = PAIR_HL;
 
-  if (AOP_TYPE (c) == AOP_REG && AOP (c)->aopu.aop_reg[0]->rIdx != IYL_IDX && AOP (c)->aopu.aop_reg[0]->rIdx != IYH_IDX &&
-    !(pair == PAIR_HL && (AOP (c)->aopu.aop_reg[0]->rIdx == L_IDX || AOP (c)->aopu.aop_reg[0]->rIdx == H_IDX)) &&
-    !(pair == PAIR_DE && (AOP (c)->aopu.aop_reg[0]->rIdx == E_IDX || AOP (c)->aopu.aop_reg[0]->rIdx == D_IDX)) &&
-    !(pair == PAIR_BC && (AOP (c)->aopu.aop_reg[0]->rIdx == B_IDX || AOP (c)->aopu.aop_reg[0]->rIdx == C_IDX)))
+  if (c->aop->type == AOP_REG && c->aop->aopu.aop_reg[0]->rIdx != IYL_IDX && c->aop->aopu.aop_reg[0]->rIdx != IYH_IDX &&
+    !(pair == PAIR_HL && (c->aop->aopu.aop_reg[0]->rIdx == L_IDX || c->aop->aopu.aop_reg[0]->rIdx == H_IDX)) &&
+    !(pair == PAIR_DE && (c->aop->aopu.aop_reg[0]->rIdx == E_IDX || c->aop->aopu.aop_reg[0]->rIdx == D_IDX)) &&
+    !(pair == PAIR_BC && (c->aop->aopu.aop_reg[0]->rIdx == B_IDX || c->aop->aopu.aop_reg[0]->rIdx == C_IDX)))
     direct_c = TRUE;
-  else if (AOP_TYPE (c) == AOP_LIT && optimize.codeSize)
+  else if (c->aop->type == AOP_LIT && optimize.codeSize)
     direct_c = TRUE;
   else
     direct_c = FALSE;
 
-  aop_c = direct_c ? AOP (c) : (pair == PAIR_DE ? ASMOP_H : ASMOP_D);
+  aop_c = direct_c ? c->aop : (pair == PAIR_DE ? ASMOP_H : ASMOP_D);
 
   if ((pair == PAIR_HL || pair == PAIR_DE && !direct_c) && !isPairDead (PAIR_HL, ic))
     {
@@ -12784,12 +15738,12 @@
     }
 
   if (!direct_c)
-    cheapMove (aop_c, 0, AOP (c), 0, true);
-  fetchPair (pair, AOP (s));
+    cheapMove (aop_c, 0, c->aop, 0, true);
+  fetchPair (pair, s->aop);
 
   if (!regalloc_dry_run)
     emitLabel (tlbl2);
-  emit2 ("ld a, (%s)", _pairs[pair].name);
+  emit2 ("ld a, !mems", _pairs[pair].name);
   regalloc_dry_run_cost++;
   emit3 (A_CP, ASMOP_A, aop_c);
   if (!regalloc_dry_run)
@@ -12804,7 +15758,7 @@
   if (!regalloc_dry_run)
     emitLabel (tlbl1);
   if (SomethingReturned)
-    commitPair (AOP (IC_RESULT (ic)), pair, ic, FALSE);
+    commitPair (IC_RESULT (ic)->aop, pair, ic, FALSE);
 
   restoreRegs (0, saved_DE, saved_BC, saved_HL, SomethingReturned ? IC_RESULT (ic) : 0);
 
@@ -12873,7 +15827,10 @@
      this has already been generated then
      do nothing */
   if (resultRemat (ic) || ic->generated)
-    return;
+    {
+      emitDebug ("; skipping iCode since result will be rematerialized");
+      return;
+    }
 
   /* depending on the operation */
   switch (ic->op)
@@ -13037,16 +15994,26 @@
       genRLC (ic);
       break;
 
-    case GETHBIT:
-      emitDebug ("; genGetHbit");
-      genGetHbit (ic);
-      break;
-
     case GETABIT:
       emitDebug ("; genGetAbit");
       genGetAbit (ic);
       break;
 
+    case GETBYTE:
+      emitDebug ("; genGetByte");
+      genGetByte (ic);
+      break;
+
+    case GETWORD:
+      emitDebug ("; genGetWord");
+      genGetWord (ic);
+      break;
+
+    case SWAP:
+      emitDebug ("; genSwap");
+      genSwap (ic);
+      break;
+
     case LEFT_OP:
       emitDebug ("; genLeftShift");
       genLeftShift (ic);
@@ -13114,12 +16081,10 @@
         }
       break;
 
-#if 0
     case ARRAYINIT:
       emitDebug ("; genArrayInit");
       genArrayInit (ic);
       break;
-#endif
 
     case DUMMY_READ_VOLATILE:
       emitDebug ("; genDummyRead");
@@ -13141,11 +16106,13 @@
     }
 }
 
-unsigned char
+float
 dryZ80iCode (iCode * ic)
 {
-  regalloc_dry_run = TRUE;
+  regalloc_dry_run = true;
   regalloc_dry_run_cost = 0;
+  regalloc_dry_run_cost_bytes = 0;
+  regalloc_dry_run_cost_states = 0;
 
   initGenLineElement ();
   _G.omitFramePtr = should_omit_frame_ptr;
@@ -13161,7 +16128,7 @@
       spillPair (pairId);
   }
 
-  return (regalloc_dry_run_cost);
+  return (regalloc_dry_run_cost + regalloc_dry_run_cost_bytes);
 }
 
 #ifdef DEBUG_DRY_COST
@@ -13177,7 +16144,7 @@
 #endif
 
 /*-------------------------------------------------------------------------------------*/
-/* genZ80Code - generate code for Z80 based controllers for a block of intructions     */
+/* genZ80Code - generate code for Z80 based controllers for a block of instructions    */
 /*-------------------------------------------------------------------------------------*/
 void
 genZ80Code (iCode * lic)
@@ -13188,7 +16155,7 @@
 
   iCode *ic;
   int cln = 0;
-  regalloc_dry_run = FALSE;
+  regalloc_dry_run = false;
 
   initGenLineElement ();
 
@@ -13203,7 +16170,7 @@
     }
 
   for (ic = lic; ic; ic = ic->next)
-    ic->generated = FALSE;
+    ic->generated = false;
 
   /* Generate Code for all instructions */
   for (ic = lic; ic; ic = ic->next)
@@ -13223,10 +16190,12 @@
           dbuf_free (iLine);
         }
       regalloc_dry_run_cost = 0;
+      regalloc_dry_run_cost_bytes = 0;
+      regalloc_dry_run_cost_states = 0;
       genZ80iCode (ic);
 
 #ifdef DEBUG_DRY_COST
-      emit2 ("; iCode %d total cost: %d\n", ic->key, regalloc_dry_run_cost);
+      emit2 ("; iCode %d total cost: %d %d %d\n", ic->key, regalloc_dry_run_cost, regalloc_dry_run_cost_bytes, regalloc_dry_run_cost_states);
 #endif
     }
 
@@ -13260,3 +16229,55 @@
   freeTrace (&_G.trace.aops);
 }
 
+// Check if what is returned by the curent function.
+bool
+z80IsReturned(const char *what)
+{
+  if (!strcmp(what, "iy"))
+    return (z80IsReturned ("iyl") || z80IsReturned ("iyh"));
+
+  const asmop *retaop = aopRet (currFunc->type);
+
+  if (!retaop)
+    return false;
+  for (int i = 0; i < retaop->size; i++)
+    if (!strcmp(retaop->aopu.aop_reg[i]->name, what))
+      return true;
+  return false;
+}
+
+// Check if what is part of the ith argument (counting from 1) to a function of type ftype.
+// If what is 0, just check if the ith argument is in registers.
+bool
+z80IsRegArg(struct sym_link *ftype, int i, const char *what)
+{
+  if (what && !strcmp(what, "iy"))
+    return (z80IsRegArg (ftype, i, "iyl") || z80IsRegArg (ftype, i, "iyh"));
+
+  const asmop *argaop = aopArg (ftype, i);
+
+  if (!argaop)
+    return false;
+    
+  if (!what)
+    return true;
+    
+  for (int i = 0; i < argaop->size; i++)
+    if (!strcmp(argaop->aopu.aop_reg[i]->name, what))
+      return true;
+
+  return false; 
+}
+
+bool
+z80IsParmInCall(sym_link *ftype, const char *what)
+{
+  const value *args;
+  int i;
+
+  for (i = 1, args = FUNC_ARGS (ftype); args; args = args->next, i++)
+    if (z80IsRegArg(ftype, i, what))
+      return true;
+  return false;
+}
+
diff -Nru sdcc-4.0.0+dfsg/src/z80/gen.h sdcc-4.2.0+dfsg/src/z80/gen.h
--- sdcc-4.0.0+dfsg/src/z80/gen.h	2019-06-15 17:59:11.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/z80/gen.h	2021-11-15 14:29:13.000000000 +0000
@@ -36,6 +36,8 @@
   AOP_STK,
   /* Is an immediate value */
   AOP_IMMD,
+  /* Is an address on the stack */
+  AOP_STL,
   /* Is a string (?) */
   AOP_STR,
   /* Is in the carry register */
@@ -44,7 +46,7 @@
   AOP_IY,
   /* Is pointed to by HL */
   AOP_HL,
-  /* Is in the extended stack pointer (IY on the Z80) */
+  /* Is on the extended stack (addressed via IY or HL) */
   AOP_EXSTK,
   /* Is referenced by a pointer in a register pair. */
   AOP_PAIRPTR,
@@ -71,7 +73,7 @@
     reg_info *aop_reg[4];       /* array of registers */
     char *aop_dir;              /* if direct  */
     char *aop_immd;             /* if immediate others are implied */
-    int aop_stk;                /* stack offset when AOP_STK */
+    int aop_stk;                /* stack offset when AOP_STK or AOP_STL*/
     const char *aop_str[4];     /* just a string array containing the location */
     int aop_pairId;             /* The pair ID */
   }
@@ -83,6 +85,16 @@
 void genZ80Code (iCode *);
 void z80_emitDebuggerSymbol (const char *);
 
+
+bool z80IsReturned(const char *what);
+
+// Check if what is part of the ith argument (counting from 1) to a function of type ftype.
+// If what is 0, just check if hte ith argument is in registers.
+bool z80IsRegArg(struct sym_link *ftype, int i, const char *what);
+
+// Check if what is part of the any argument (counting from 1) to a function of type ftype.
+bool z80IsParmInCall(sym_link *ftype, const char *what);
+
 extern bool z80_assignment_optimal;
 extern bool should_omit_frame_ptr;
 
diff -Nru sdcc-4.0.0+dfsg/src/z80/main.c sdcc-4.2.0+dfsg/src/z80/main.c
--- sdcc-4.0.0+dfsg/src/z80/main.c	2019-12-12 09:59:51.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/z80/main.c	2021-12-10 14:48:15.000000000 +0000
@@ -42,6 +42,9 @@
 #define OPTION_OLDRALLOC       "--oldralloc"
 #define OPTION_FRAMEPOINTER    "--fno-omit-frame-pointer"
 #define OPTION_EMIT_EXTERNS    "--emit-externs"
+#define OPTION_LEGACY_BANKING  "--legacy-banking"
+#define OPTION_NMOS_Z80        "--nmos-z80"
+#define OPTION_SDCCCALL        "--sdcccall"
 
 static char _z80_defaultRules[] = {
 #include "peeph.rul"
@@ -58,11 +61,22 @@
 #include "peeph-tlcs90.rul"
 };
 
-static char _gbz80_defaultRules[] = {
+static char _sm83_defaultRules[] = {
+#include "peeph-sm83.rul"
 #include "peeph.rul"
-#include "peeph-gbz80.rul"
 };
 
+static char _ez80_z80_defaultRules[] = {
+#include "peeph.rul"
+#include "peeph-z80.rul"
+#include "peeph-ez80_z80.rul"
+};
+
+static char _z80n_defaultRules[] = {
+#include "peeph.rul"
+#include "peeph-z80.rul"
+#include "peeph-z80n.rul"
+};
 
 
 Z80_OPTS z80_opts;
@@ -70,26 +84,32 @@
 static OPTION _z80_options[] = {
   {0, OPTION_CALLEE_SAVES_BC, &z80_opts.calleeSavesBC, "Force a called function to always save BC"},
   {0, OPTION_PORTMODE,        NULL, "Determine PORT I/O mode (z80/z180)"},
-  {0, OPTION_ASM,             NULL, "Define assembler name (rgbds/asxxxx/isas/z80asm)"},
+  {0, OPTION_ASM,             NULL, "Define assembler name (rgbds/asxxxx/isas/z80asm/gas)"},
   {0, OPTION_CODE_SEG,        &options.code_seg, " use this name for the code segment", CLAT_STRING},
   {0, OPTION_CONST_SEG,       &options.const_seg, " use this name for the const segment", CLAT_STRING},
   {0, OPTION_DATA_SEG,        &options.data_seg, " use this name for the data segment", CLAT_STRING},
-  {0, OPTION_NO_STD_CRT0,     &options.no_std_crt0, "For the z80/gbz80 do not link default crt0.rel"},
+  {0, OPTION_NO_STD_CRT0,     &options.no_std_crt0, "Do not link default crt0.rel"},
   {0, OPTION_RESERVE_IY,      &z80_opts.reserveIY, "Do not use IY (incompatible with --fomit-frame-pointer)"},
-  {0, OPTION_OLDRALLOC,       &options.oldralloc, "Use old register allocator"},
+  {0, OPTION_OLDRALLOC,       &options.oldralloc, "Use old register allocator (deprecated)"},
   {0, OPTION_FRAMEPOINTER,    &z80_opts.noOmitFramePtr, "Do not omit frame pointer"},
   {0, OPTION_EMIT_EXTERNS,    NULL, "Emit externs list in generated asm"},
+  {0, OPTION_LEGACY_BANKING,  &z80_opts.legacyBanking, "Use legacy method to call banked functions"},
+  {0, OPTION_NMOS_Z80,        &z80_opts.nmosZ80, "Generate workaround for NMOS Z80 when saving IFF2"},
+  {0, OPTION_SDCCCALL,         &options.sdcccall, "Set ABI version for default calling convention", CLAT_INTEGER},
   {0, NULL}
 };
 
-static OPTION _gbz80_options[] = {
+static OPTION _sm83_options[] = {
   {0, OPTION_BO,              NULL, " use code bank "},
   {0, OPTION_BA,              NULL, " use data bank "},
+  {0, OPTION_ASM,             NULL, "Define assembler name (rgbds/asxxxx/isas/z80asm/gas)"},
   {0, OPTION_CALLEE_SAVES_BC, &z80_opts.calleeSavesBC, "Force a called function to always save BC"},
   {0, OPTION_CODE_SEG,        &options.code_seg, " use this name for the code segment", CLAT_STRING},
   {0, OPTION_CONST_SEG,       &options.const_seg, " use this name for the const segment", CLAT_STRING},
   {0, OPTION_DATA_SEG,        &options.data_seg, " use this name for the data segment", CLAT_STRING},
-  {0, OPTION_NO_STD_CRT0,     &options.no_std_crt0, "For the z80/gbz80 do not link default crt0.rel"},
+  {0, OPTION_NO_STD_CRT0,     &options.no_std_crt0, "Do not link default crt0.rel"},
+  {0, OPTION_LEGACY_BANKING,  &z80_opts.legacyBanking, "Use legacy method to call banked functions"},
+  {0, OPTION_SDCCCALL,         &options.sdcccall, "Set ABI version for default calling convention", CLAT_INTEGER},
   {0, NULL}
 };
 
@@ -99,16 +119,20 @@
   ASM_TYPE_ASXXXX,
   ASM_TYPE_RGBDS,
   ASM_TYPE_ISAS,
-  ASM_TYPE_Z80ASM
+  ASM_TYPE_Z80ASM,
+  ASM_TYPE_GAS
 }
 ASM_TYPE;
 
 static struct
 {
   ASM_TYPE asmType;
-  /* determine if we can register a parameter */
-  int regParams;
-  bool z88dk_fastcall;
+  // Determine if we can put parameters in registers
+  struct
+  {
+    int n;
+    struct sym_link *ftype;
+  } regparam;
 }
 _G;
 
@@ -156,7 +180,7 @@
 
 extern PORT z80_port;
 extern PORT r2k_port;
-extern PORT gbz80_port;
+extern PORT sm83_port;
 
 #include "mappings.i"
 
@@ -169,18 +193,45 @@
   {NULL, NULL, 0, {NULL}}
 };
 
+extern reg_info sm83_regs[];
+extern reg_info z80_regs[];
+extern void z80_init_asmops (void);
+extern reg_info *regsZ80;
+
 static void
 _z80_init (void)
 {
   z80_opts.sub = SUB_Z80;
-  asm_addTree (&_asxxxx_z80);
+  switch (_G.asmType)
+    {
+    case ASM_TYPE_GAS:
+      asm_addTree (&_gas_z80);
+      break;
+    default:
+      asm_addTree (&_asxxxx_z80);
+      break;
+    }
+
+  regsZ80 = z80_regs;
+  z80_init_asmops ();
 }
 
 static void
 _z180_init (void)
 {
   z80_opts.sub = SUB_Z180;
-  asm_addTree (&_asxxxx_z80);
+  switch (_G.asmType)
+    {
+    case ASM_TYPE_GAS:
+      asm_addTree (&_gas_z80);
+      break;
+    default:
+      asm_addTree (&_asxxxx_z80);
+      break;
+    }
+
+  regsZ80 = z80_regs;
+  z80_init_asmops ();
 }
 
 static void
@@ -188,6 +239,19 @@
 {
   z80_opts.sub = SUB_R2K;
   asm_addTree (&_asxxxx_r2k);
+
+  regsZ80 = z80_regs;
+  z80_init_asmops ();
+}
+
+static void
+_r2ka_init (void)
+{
+  z80_opts.sub = SUB_R2KA;
+  asm_addTree (&_asxxxx_r2k);
+
+  regsZ80 = z80_regs;
+  z80_init_asmops ();
 }
 
 static void
@@ -195,12 +259,18 @@
 {
   z80_opts.sub = SUB_R3KA;
   asm_addTree (&_asxxxx_r2k);
+
+  regsZ80 = z80_regs;
+  z80_init_asmops ();
 }
 
 static void
-_gbz80_init (void)
+_sm83_init (void)
 {
-  z80_opts.sub = SUB_GBZ80;
+  z80_opts.sub = SUB_SM83;
+
+  regsZ80 = sm83_regs;
+  z80_init_asmops ();
 }
 
 static void
@@ -208,37 +278,62 @@
 {
   z80_opts.sub = SUB_TLCS90;
   asm_addTree (&_asxxxx_z80);
+
+  regsZ80 = z80_regs;
+  z80_init_asmops ();
 }
 
 static void
 _ez80_z80_init (void)
 {
   z80_opts.sub = SUB_EZ80_Z80;
+  switch (_G.asmType)
+    {
+    case ASM_TYPE_GAS:
+      asm_addTree (&_gas_z80);
+      break;
+    default:
+      asm_addTree (&_asxxxx_z80);
+      break;
+    }
+
+  regsZ80 = z80_regs;
+  z80_init_asmops ();
+}
+
+static void
+_z80n_init (void)
+{
+  z80_opts.sub = SUB_Z80N;
   asm_addTree (&_asxxxx_z80);
+
+  regsZ80 = z80_regs;
+  z80_init_asmops ();
 }
 
 static void
-_reset_regparm (struct sym_link *funcType)
+_reset_regparm (struct sym_link *ftype)
 {
-  _G.regParams = 0;
-  _G.z88dk_fastcall = IFFUNC_ISZ88DK_FASTCALL (funcType);
-  if (_G.z88dk_fastcall && IFFUNC_HASVARARGS (funcType))
+  _G.regparam.n = 0;
+  _G.regparam.ftype = ftype;
+  if (IFFUNC_ISZ88DK_FASTCALL (ftype) && IFFUNC_HASVARARGS (ftype))
     werror (E_Z88DK_FASTCALL_PARAMETERS);
 }
 
 static int
 _reg_parm (sym_link *l, bool reentrant)
 {
-  if (_G.z88dk_fastcall)
+  if (IFFUNC_ISZ88DK_FASTCALL (_G.regparam.ftype))
     {
-      if (_G.regParams)
+      if (_G.regparam.n)
         werror (E_Z88DK_FASTCALL_PARAMETERS);
       if (getSize (l) > 4)
         werror (E_Z88DK_FASTCALL_PARAMETER);
-      _G.regParams++;
-      return TRUE;
     }
- return FALSE;
+
+  bool is_regarg = z80IsRegArg(_G.regparam.ftype, ++_G.regparam.n, 0);
+
+  return (is_regarg ? _G.regparam.n : 0);
 }
 
 enum
@@ -282,7 +377,7 @@
                 break;
 
               case ASM_TYPE_RGBDS:
-                dbuf_printf (&buffer, "CODE,BANK[%d]", token.val.int_val);
+                dbuf_printf (&buffer, "ROMX,BANK[%d]", token.val.int_val);
                 break;
 
               case ASM_TYPE_ISAS:
@@ -290,6 +385,10 @@
                 dbuf_printf (&buffer, "CODE,BANK(%d)", token.val.int_val);
                 break;
 
+              case ASM_TYPE_GAS:
+                dbuf_printf (&buffer, ".ovly%04x", token.val.int_val);
+                break;
+
               default:
                 wassert (0);
               }
@@ -312,10 +411,7 @@
           }
 
         dbuf_c_str (&buffer);
-        /* ugly, see comment in src/port.h (borutr) */
-        gbz80_port.mem.code_name = dbuf_detach (&buffer);
-        code->sname = gbz80_port.mem.code_name;
-        options.code_seg = (char *) gbz80_port.mem.code_name;
+        options.code_seg = (char *) dbuf_detach (&buffer);
       }
       break;
 
@@ -426,16 +522,16 @@
   return process_pragma_tbl (pragma_tbl, s);
 }
 
-static const char *_gbz80_rgbasmCmd[] = {
+static const char *_sm83_rgbasmCmd[] = {
   "rgbasm", "-o$1.rel", "$1.asm", NULL
 };
 
-static const char *_gbz80_rgblinkCmd[] = {
+static const char *_sm83_rgblinkCmd[] = {
   "xlink", "-tg", "-n$1.sym", "-m$1.map", "-zFF", "$1.lnk", NULL
 };
 
 static void
-_gbz80_rgblink (void)
+_sm83_rgblink (void)
 {
   FILE *lnkfile;
   struct dbuf_s lnkFileName;
@@ -448,7 +544,7 @@
   dbuf_append_str (&lnkFileName, ".lk");
   if (!(lnkfile = fopen (dbuf_c_str (&lnkFileName), "w")))
     {
-      werror (E_FILE_OPEN_ERR, dbuf_c_str (&lnkFileName));
+      werror (E_OUTPUT_FILE_OPEN_ERR, dbuf_c_str (&lnkFileName), strerror (errno));
       dbuf_destroy (&lnkFileName);
       exit (1);
     }
@@ -484,7 +580,7 @@
 {
   if (argv[*i][0] == '-')
     {
-      if (IS_GB)
+      if (IS_SM83)
         {
           if (!strncmp (argv[*i], OPTION_BO, sizeof (OPTION_BO) - 1))
             {
@@ -493,11 +589,16 @@
               struct dbuf_s buffer;
 
               dbuf_init (&buffer, 16);
-              dbuf_printf (&buffer, "CODE_%u", bank);
+              if (_G.asmType == ASM_TYPE_RGBDS)
+                {
+                  dbuf_printf (&buffer, "ROMX,BANK[%u]", bank);
+                }
+              else
+                {
+                  dbuf_printf (&buffer, "CODE_%u", bank);
+                }
               dbuf_c_str (&buffer);
-              /* ugly, see comment in src/port.h (borutr) */
-              gbz80_port.mem.code_name = dbuf_detach (&buffer);
-              options.code_seg = (char *) gbz80_port.mem.code_name;
+              options.code_seg = (char *) dbuf_detach (&buffer);
               return TRUE;
             }
           else if (!strncmp (argv[*i], OPTION_BA, sizeof (OPTION_BA) - 1))
@@ -507,10 +608,16 @@
               struct dbuf_s buffer;
 
               dbuf_init (&buffer, 16);
-              dbuf_printf (&buffer, "DATA_%u", bank);
+              if (_G.asmType == ASM_TYPE_RGBDS)
+                {
+                  dbuf_printf (&buffer, "SRAM,BANK[%u]", bank);
+                }
+              else
+                {
+                  dbuf_printf (&buffer, "DATA_%u", bank);
+                }
               dbuf_c_str (&buffer);
-              /* ugly, see comment in src/port.h (borutr) */
-              gbz80_port.mem.data_name = dbuf_detach (&buffer);
+              options.data_seg = (char *) dbuf_detach (&buffer);
               return TRUE;
             }
         }
@@ -522,9 +629,26 @@
           if (!strcmp (asmblr, "rgbds"))
             {
               asm_addTree (&_rgbds_gb);
-              gbz80_port.assembler.cmd = _gbz80_rgbasmCmd;
-              gbz80_port.linker.cmd = _gbz80_rgblinkCmd;
-              gbz80_port.linker.do_link = _gbz80_rgblink;
+              // rgbds doesn't understand that
+              options.noOptsdccInAsm = true;
+
+              sm83_port.assembler.cmd = _sm83_rgbasmCmd;
+              sm83_port.linker.cmd = _sm83_rgblinkCmd;
+              sm83_port.linker.do_link = _sm83_rgblink;
+
+              if(!(options.code_seg && strcmp(options.code_seg, CODE_NAME)))
+                {
+                  if (options.code_seg)
+                    Safe_free (options.code_seg);
+                  options.code_seg = Safe_strdup ("ROMX");
+                }
+              if(!(options.data_seg && strcmp(options.data_seg, DATA_NAME)))
+                {
+                  if (options.data_seg)
+                    Safe_free (options.data_seg);
+                  options.data_seg = Safe_strdup ("WRAMX");
+                }
+
               _G.asmType = ASM_TYPE_RGBDS;
               return TRUE;
             }
@@ -537,7 +661,7 @@
             {
               asm_addTree (&_isas_gb);
               /* Munge the function prefix */
-              gbz80_port.fun_prefix = "";
+              sm83_port.fun_prefix = "";
               _G.asmType = ASM_TYPE_ISAS;
               return TRUE;
             }
@@ -548,6 +672,13 @@
               _G.asmType = ASM_TYPE_ISAS;
               return TRUE;
             }
+          else if (!strcmp (asmblr, "gas"))
+            {
+              port->assembler.externGlobal = TRUE;
+              asm_addTree (&_gas_z80);
+              _G.asmType = ASM_TYPE_GAS;
+              return TRUE;
+            }
         }
       else if (!strncmp (argv[*i], OPTION_PORTMODE, sizeof (OPTION_PORTMODE) - 1))
         {
@@ -567,7 +698,12 @@
       else if (!strncmp (argv[*i], OPTION_EMIT_EXTERNS, sizeof (OPTION_EMIT_EXTERNS) - 1))
         {
           port->assembler.externGlobal = 1;
-          return TRUE;
+          return true;
+        }
+      else if (!strncmp (argv[*i], OPTION_OLDRALLOC, sizeof (OPTION_OLDRALLOC) - 1))
+        {
+          werror (W_DEPRECATED_OPTION, "--oldralloc");
+          return true;
         }
     }
   return FALSE;
@@ -637,7 +773,7 @@
   setMainValue ("z80extralibpaths", (s = joinStrSet (libPathsSet)));
   Safe_free ((void *) s);
 
-  if (IS_GB)
+  if (IS_SM83)
     {
       setMainValue ("z80outputtypeflag", "-Z");
       setMainValue ("z80outext", ".gb");
@@ -660,7 +796,7 @@
   dbuf_destroy (&dbuf);
 
   /* For the old register allocator (with the new one we decide to omit the frame pointer for each function individually) */
-  if (!IS_GB && options.omitFramePtr)
+  if (!IS_SM83 && options.omitFramePtr)
     port->stack.call_overhead = 2;
 }
 
@@ -669,8 +805,20 @@
 {
   port->mem.default_local_map = data;
   port->mem.default_globl_map = data;
-  if (_G.asmType == ASM_TYPE_ASXXXX && IS_GB)
-    asm_addTree (&_asxxxx_gb);
+  if (IS_SM83)
+    switch (_G.asmType)
+      {
+      case ASM_TYPE_ASXXXX:
+        asm_addTree (&_asxxxx_gb);
+        break;
+      case ASM_TYPE_GAS:
+        asm_addTree (&_gas_gb);
+        break;
+      case ASM_TYPE_ISAS:
+      case ASM_TYPE_RGBDS:
+      case ASM_TYPE_Z80ASM:
+        break;
+      }
 
   if (IY_RESERVED)
     port->num_regs -= 2;
@@ -690,7 +838,13 @@
   /* Default code and data locations. */
   options.code_loc = 0x200;
 
-  options.data_loc = IS_GB ? 0xC000 : 0x8000;
+  if (IS_SM83)
+    options.data_loc = 0xc000;
+  else if (IS_RAB) // Match default crt0
+    options.data_loc = 0xa000;
+  else
+    options.data_loc = 0x8000;
+
   options.out_fmt = 'i';        /* Default output format is ihx */
 }
 
@@ -773,9 +927,7 @@
   int result_size = IS_SYMOP (IC_RESULT(ic)) ? getSize (OP_SYM_TYPE (IC_RESULT(ic))) : 4;
 
   if (ic->op != '*')
-    {
-      return FALSE;
-    }
+    return(false);
 
   if (IS_LITERAL (left))
     test = left;
@@ -783,36 +935,40 @@
     test = right;
   /* 8x8 unsigned multiplication code is shorter than
      call overhead for the multiplication routine. */
-  else if (IS_CHAR (right) && IS_UNSIGNED (right) && IS_CHAR (left) && IS_UNSIGNED (left) && !IS_GB)
-    {
-      return TRUE;
-    }
+  else if (IS_CHAR (right) && IS_UNSIGNED (right) && IS_CHAR (left) && IS_UNSIGNED (left) && !IS_SM83)
+    return(true);
   /* Same for any multiplication with 8 bit result. */
-  else if (result_size == 1 && !IS_GB)
-    {
-      return TRUE;
-    }
+  else if (result_size == 1 && !IS_SM83)
+    return(true);
+  // Rabbits have signed 16x16->32 multiplication, which is broken on original Rabbit 2000.
+  else if (IS_RAB && !IS_R2K && getSize (left) == 2 && getSize(right) == 2 &&
+    (result_size == 2 || result_size <= 4 && !IS_UNSIGNED (left) && !IS_UNSIGNED (right)))
+    return(true);
   else
-    {
-      return FALSE;
-    }
+    return(false);
 
   if (getSize (test) <= 2)
-    {
-      return TRUE;
-    }
+    return(true);
 
-  return FALSE;
+  return(false);
 }
 
 /* Indicate which extended bit operations this port supports */
 static bool
 hasExtBitOp (int op, int size)
 {
-  if (op == GETHBIT)
-    return TRUE;
-  else
-    return FALSE;
+  switch (op)
+    {
+    case GETABIT:
+    case GETBYTE:
+    case GETWORD:
+    case RLC:
+    case RRC:
+      return true;
+    case SWAP:
+      return size <= 4;
+    }
+  return false;
 }
 
 /* Indicate the expense of an access to an output storage class */
@@ -845,7 +1001,11 @@
 static const char *_gbLinkCmd[] = {
   "sdldgb", "-nf", "$1", NULL
 };
-
+/*
+static const char *_gnuLdCmd[] = {
+  "z80-elf-ld", "", "$1", NULL
+};
+*/
 /* $3 is replaced by assembler.debug_opts resp. port->assembler.plain_opts */
 static const char *_z80AsmCmd[] = {
   "sdasz80", "$l", "$3", "$2", "$1.asm", NULL
@@ -862,15 +1022,21 @@
 static const char *_tlcs90AsmCmd[] = {
   "sdastlcs90", "$l", "$3", "$2", "$1.asm", NULL
 };
-
+/*
+static const char *_GnuAsmCmd[] = {
+  "z80-elf-as", "$l", "$3", "$2", "$1.asm", NULL
+};
+*/
 static const char *const _crt[] = { "crt0.rel", NULL, };
 static const char *const _libs_z80[] = { "z80", NULL, };
 static const char *const _libs_z180[] = { "z180", NULL, };
 static const char *const _libs_r2k[] = { "r2k", NULL, };
+static const char *const _libs_r2ka[] = { "r2ka", NULL, };
 static const char *const _libs_r3ka[] = { "r3ka", NULL, };
 static const char *const _libs_tlcs90[] = { "tlcs90", NULL, };
-static const char *const _libs_gb[] = { "gbz80", NULL, };
+static const char *const _libs_sm83[] = { "sm83", NULL, };
 static const char *const _libs_ez80_z80[] = { "ez80_z80", NULL, };
+static const char *const _libs_z80n[] = { "z80n", NULL, };
 
 /* Globals */
 PORT z80_port =
@@ -913,6 +1079,8 @@
     z80canAssign,
     z80notUsedFrom,
     z80symmParmStack,
+    z80canJoinRegs,
+    z80canSplitReg,
   },
   /* Sizes: char, short, int, long, long long, near ptr, far ptr, gptr, func ptr, banked func ptr, bit, float */
   { 1, 2, 2, 4, 8, 2, 2, 2, 2, 2, 1, 4 },
@@ -946,8 +1114,12 @@
     1                           /* No fancy alignments supported. */
   },
   { NULL, NULL },
-  { -1, 0, 0, 4, 0, 2, 0 },
-  { -1, FALSE },
+  1,                            /* ABI revision */
+  { -1, 0, 0, 4, 0, 3, 0 },
+  { 
+    -1,                         /* shifts never use support routines */
+    true,                       /* use support routine for int x int -> long multiplication */
+  },
   { z80_emitDebuggerSymbol },
   {
     256,                        /* maxCount */
@@ -1039,6 +1211,8 @@
     z80canAssign,
     z80notUsedFrom,
     z80symmParmStack,
+    z80canJoinRegs,
+    z80canSplitReg,
   },
   /* Sizes: char, short, int, long, long long, near ptr, far ptr, gptr, func ptr, banked func ptr, bit, float */
   { 1, 2, 2, 4, 8, 2, 2, 2, 2, 2, 1, 4 },
@@ -1072,7 +1246,8 @@
     1                           /* No fancy alignments supported. */
   },
   { NULL, NULL },
-  { -1, 0, 0, 4, 0, 2, 0 },
+  1,                            /* ABI revision */
+  { -1, 0, 0, 4, 0, 3, 0 },
   { -1, FALSE },
   { z80_emitDebuggerSymbol },
   {
@@ -1164,6 +1339,8 @@
     z80canAssign,
     z80notUsedFrom,
     z80symmParmStack,
+    z80canJoinRegs,
+    z80canSplitReg,
   },
   /* Sizes: char, short, int, long, long long, near ptr, far ptr, gptr, func ptr, banked func ptr, bit, float */
   { 1, 2, 2, 4, 8, 2, 2, 2, 2, 2, 1, 4 },
@@ -1197,6 +1374,7 @@
     1                           /* No fancy alignments supported. */
   },
   { NULL, NULL },
+  0,                            /* ABI revision */
   { -1, 0, 0, 4, 0, 2, 0 },
   { -1, FALSE },
   { z80_emitDebuggerSymbol },
@@ -1250,6 +1428,135 @@
   PORT_MAGIC
 };
 
+PORT r2ka_port =
+{
+  TARGET_ID_R2KA,
+  "r2ka",
+  "Rabbit 2000A",               /* Target name */
+  NULL,                         /* Processor name */
+  {
+    glue,
+    FALSE,
+    NO_MODEL,
+    NO_MODEL,
+    NULL,                       /* model == target */
+  },
+  {                             /* Assembler */
+    _r2kAsmCmd,
+    NULL,
+    "-plosgffwy",               /* Options with debug */
+    "-plosgffw",                /* Options without debug */
+    0,
+    ".asm"
+  },
+  {                             /* Linker */
+    _z80LinkCmd,                //NULL,
+    NULL,                       //LINKCMD,
+    NULL,
+    ".rel",
+    1,
+    _crt,                       /* crt */
+    _libs_r2ka,                 /* libs */
+  },
+  {                             /* Peephole optimizer */
+    _r2k_defaultRules,
+    z80instructionSize,
+    0,
+    0,
+    0,
+    z80notUsed,
+    z80canAssign,
+    z80notUsedFrom,
+    z80symmParmStack,
+    z80canJoinRegs,
+    z80canSplitReg,
+  },
+  /* Sizes: char, short, int, long, long long, near ptr, far ptr, gptr, func ptr, banked func ptr, bit, float */
+  { 1, 2, 2, 4, 8, 2, 2, 2, 2, 2, 1, 4 },
+  /* tags for generic pointers */
+  { 0x00, 0x40, 0x60, 0x80 },   /* far, near, xstack, code */
+  {
+    "XSEG",
+    "STACK",
+    "CODE",
+    "DATA",
+    NULL,                       /* idata */
+    NULL,                       /* pdata */
+    NULL,                       /* xdata */
+    NULL,                       /* bit */
+    "RSEG (ABS)",
+    "GSINIT",
+    NULL,                       /* overlay */
+    "GSFINAL",
+    "HOME",
+    NULL,                       /* xidata */
+    NULL,                       /* xinit */
+    NULL,                       /* const_name */
+    "CABS (ABS)",               /* cabs_name */
+    "DABS (ABS)",               /* xabs_name */
+    NULL,                       /* iabs_name */
+    "INITIALIZED",              /* name of segment for initialized variables */
+    "INITIALIZER",              /* name of segment for copies of initialized variables in code space */
+    NULL,
+    NULL,
+    1,                          /* CODE  is read-only */
+    1                           /* No fancy alignments supported. */
+  },
+  { NULL, NULL },
+  0,                            /* ABI revision */
+  { -1, 0, 0, 4, 0, 2, 0 },
+  { -1, FALSE },
+  { z80_emitDebuggerSymbol },
+  {
+    256,                        /* maxCount */
+    3,                          /* sizeofElement */
+    {6, 7, 8},                  /* sizeofMatchJump[] - Assumes operand allocated to registers */
+    {6, 9, 15},                 /* sizeofRangeCompare[] - Assumes operand allocated to registers*/
+    1,                          /* sizeofSubtract - Assumes use of a singel inc or dec */
+    9,                          /* sizeofDispatch - Assumes operand allocated to register e or c*/
+  },
+  "_",
+  _r2ka_init,
+  _parseOptions,
+  _z80_options,
+  NULL,
+  _finaliseOptions,
+  _setDefaultOptions,
+  z80_assignRegisters,
+  _getRegName,
+  _getRegByName,
+  NULL,
+  _keywords,
+  0,                            /* no assembler preamble */
+  NULL,                         /* no genAssemblerEnd */
+  0,                            /* no local IVT generation code */
+  0,                            /* no genXINIT code */
+  NULL,                         /* genInitStartup */
+  _reset_regparm,
+  _reg_parm,
+  _process_pragma,
+  NULL,
+  _hasNativeMulFor,
+  hasExtBitOp,                  /* hasExtBitOp */
+  oclsExpense,                  /* oclsExpense */
+  TRUE,
+  TRUE,                         /* little endian */
+  0,                            /* leave lt */
+  0,                            /* leave gt */
+  1,                            /* transform <= to ! > */
+  1,                            /* transform >= to ! < */
+  1,                            /* transform != to !(a == b) */
+  0,                            /* leave == */
+  FALSE,                        /* Array initializer support. */
+  0,                            /* no CSE cost estimation yet */
+  _z80_builtins,                /* builtin functions */
+  GPOINTER,                     /* treat unqualified pointers as "generic" pointers */
+  1,                            /* reset labelKey to 1 */
+  1,                            /* globals & local statics allowed */
+  9,                            /* Number of registers handled in the tree-decomposition-based register allocator in SDCCralloc.hpp */
+  PORT_MAGIC
+};
+
 PORT r3ka_port =
 {
   TARGET_ID_R3KA,
@@ -1290,6 +1597,8 @@
     z80canAssign,
     z80notUsedFrom,
     z80symmParmStack,
+    z80canJoinRegs,
+    z80canSplitReg,
   },
   /* Sizes: char, short, int, long, long long, near ptr, far ptr, gptr, func ptr, banked func ptr, bit, float */
   { 1, 2, 2, 4, 8, 2, 2, 2, 2, 2, 1, 4 },
@@ -1323,6 +1632,7 @@
     1                           /* No fancy alignments supported. */
   },
   { NULL, NULL },
+  0,                            /* ABI revision */
   { -1, 0, 0, 4, 0, 2, 0 },
   { -1, FALSE },
   { z80_emitDebuggerSymbol },
@@ -1377,11 +1687,11 @@
 };
 
 /* Globals */
-PORT gbz80_port =
+PORT sm83_port =
 {
-  TARGET_ID_GBZ80,
-  "gbz80",
-  "Gameboy Z80-like",           /* Target name */
+  TARGET_ID_SM83,
+  "sm83",
+  "Sharp SM83",           /* Target name */
   NULL,
   {
     glue,
@@ -1406,18 +1716,20 @@
     ".rel",
     1,
     _crt,                       /* crt */
-    _libs_gb,                   /* libs */
+    _libs_sm83,                 /* libs */
   },
   {                             /* Peephole optimizer */
-    _gbz80_defaultRules,
-    NULL,
-    NULL,
+    _sm83_defaultRules,
+    z80instructionSize,
     NULL,
     NULL,
     NULL,
+    z80notUsed,
     z80canAssign,
-    NULL,
+    z80notUsedFrom,
     z80symmParmStack,
+    z80canJoinRegs,
+    z80canSplitReg,
   },
   /* Sizes: char, short, int, long, long long, near ptr, far ptr, gptr, func ptr, banked func ptr, bit, float */
   { 1, 2, 2, 4, 8, 2, 2, 2, 2, 2, 1, 4 },
@@ -1443,14 +1755,15 @@
     "CABS (ABS)",               /* cabs_name */
     "DABS (ABS)",               /* xabs_name */
     NULL,                       /* iabs_name */
-    NULL,                       /* name of segment for initialized variables */
-    NULL,                       /* name of segment for copies of initialized variables in code space */
+    "INITIALIZED",              /* name of segment for initialized variables */
+    "INITIALIZER",              /* name of segment for copies of initialized variables in code space */
     NULL,
     NULL,
     1,                          /* CODE is read-only */
     1                           /* No fancy alignments supported. */
   },
   { NULL, NULL },
+  1,                            /* default ABI revision */
   { -1, 0, 0, 2, 0, 4, 0 },
   { -1, FALSE },
   { z80_emitDebuggerSymbol },
@@ -1463,9 +1776,9 @@
     9,                          /* sizeofDispatch - Assumes operand allocated to register e or c*/
   },
   "_",
-  _gbz80_init,
+  _sm83_init,
   _parseOptions,
-  _gbz80_options,
+  _sm83_options,
   NULL,
   _finaliseOptions,
   _setDefaultOptions,
@@ -1494,13 +1807,13 @@
   1,                            /* transform >= to ! < */
   1,                            /* transform != to !(a == b) */
   0,                            /* leave == */
-  FALSE,                        /* Array initializer support. */
+  false,                        /* Array initializer support. */
   0,                            /* no CSE cost estimation yet */
   NULL,                         /* no builtin functions */
   GPOINTER,                     /* treat unqualified pointers as "generic" pointers */
   1,                            /* reset labelKey to 1 */
   1,                            /* globals & local statics allowed */
-  5,                            /* Number of registers handled in the tree-decomposition-based register allocator in SDCCralloc.hpp */
+  7,                            /* Number of registers handled in the tree-decomposition-based register allocator in SDCCralloc.hpp */
   PORT_MAGIC
 };
 
@@ -1544,6 +1857,8 @@
     z80canAssign,
     z80notUsedFrom,
     z80symmParmStack,
+    z80canJoinRegs,
+    z80canSplitReg,
   },
   /* Sizes: char, short, int, long, long long, near ptr, far ptr, gptr, func ptr, banked func ptr, bit, float */
   { 1, 2, 2, 4, 8, 2, 2, 2, 2, 2, 1, 4 },
@@ -1577,6 +1892,7 @@
     1                           /* No fancy alignments supported. */
    },
   { NULL, NULL },
+  0,                            /* ABI revision */
   { -1, 0, 0, 4, 0, 2, 0 },
   { -1, FALSE },
   { z80_emitDebuggerSymbol },
@@ -1622,7 +1938,7 @@
   0,                            /* leave == */
   FALSE,                        /* Array initializer support. */
   0,                            /* no CSE cost estimation yet */
-  _z80_builtins,                /* builtin functions */
+  0,                            /* no builtin functions */
   GPOINTER,                     /* treat unqualified pointers as "generic" pointers */
   1,                            /* reset labelKey to 1 */
   1,                            /* globals & local statics allowed */
@@ -1634,7 +1950,7 @@
 {
   TARGET_ID_EZ80_Z80,
   "ez80_z80",
-  "eZ80-Z80",                  /* Target name */
+  "eZ80-Z80",                   /* Target name */
   NULL,                         /* Processor name */
   {
     glue,
@@ -1658,10 +1974,10 @@
     ".rel",
     1,
     _crt,                       /* crt */
-    _libs_ez80_z80,                 /* libs */
+    _libs_ez80_z80,             /* libs */
   },
   {                             /* Peephole optimizer */
-    _z80_defaultRules,
+    _ez80_z80_defaultRules,
     z80instructionSize,
     NULL,
     NULL,
@@ -1670,6 +1986,8 @@
     z80canAssign,
     z80notUsedFrom,
     z80symmParmStack,
+    z80canJoinRegs,
+    z80canSplitReg,
   },
   /* Sizes: char, short, int, long, long long, near ptr, far ptr, gptr, func ptr, banked func ptr, bit, float */
   { 1, 2, 2, 4, 8, 2, 2, 2, 2, 2, 1, 4 },
@@ -1703,7 +2021,8 @@
     1                           /* No fancy alignments supported. */
   },
   { NULL, NULL },
-  { -1, 0, 0, 4, 0, 2, 0 },
+  0,                            /* ABI revision */
+  { -1, 0, 0, 4, 0, 3, 0 },
   { -1, FALSE },
   { z80_emitDebuggerSymbol },
   {
@@ -1719,6 +2038,135 @@
   _parseOptions,
   _z80_options,
   NULL,
+  _finaliseOptions,
+  _setDefaultOptions,
+  z80_assignRegisters,
+  _getRegName,
+  _getRegByName,
+  NULL,
+  _keywords,
+  0,                            /* no assembler preamble */
+  NULL,                         /* no genAssemblerEnd */
+  0,                            /* no local IVT generation code */
+  0,                            /* no genXINIT code */
+  NULL,                         /* genInitStartup */
+  _reset_regparm,
+  _reg_parm,
+  _process_pragma,
+  NULL,
+  _hasNativeMulFor,
+  hasExtBitOp,                  /* hasExtBitOp */
+  oclsExpense,                  /* oclsExpense */
+  TRUE,
+  TRUE,                         /* little endian */
+  0,                            /* leave lt */
+  0,                            /* leave gt */
+  1,                            /* transform <= to ! > */
+  1,                            /* transform >= to ! < */
+  1,                            /* transform != to !(a == b) */
+  0,                            /* leave == */
+  FALSE,                        /* Array initializer support. */
+  0,                            /* no CSE cost estimation yet */
+  _z80_builtins,                /* builtin functions */
+  GPOINTER,                     /* treat unqualified pointers as "generic" pointers */
+  1,                            /* reset labelKey to 1 */
+  1,                            /* globals & local statics allowed */
+  9,                            /* Number of registers handled in the tree-decomposition-based register allocator in SDCCralloc.hpp */
+  PORT_MAGIC
+};
+
+PORT z80n_port =
+{
+  TARGET_ID_Z80N,
+  "z80n",
+  "z80n",                       /* Target name */
+  NULL,                         /* Processor name */
+  {
+    glue,
+    FALSE,
+    NO_MODEL,
+    NO_MODEL,
+    NULL,                       /* model == target */
+  },
+  {                             /* Assembler */
+    _z80AsmCmd,
+    NULL,
+    "-plosgffwy",               /* Options with debug */
+    "-plosgffw",                /* Options without debug */
+    0,
+    ".asm"
+  },
+  {                             /* Linker */
+    _z80LinkCmd,                //NULL,
+    NULL,                       //LINKCMD,
+    NULL,
+    ".rel",
+    1,
+    _crt,                       /* crt */
+    _libs_z80n,                 /* libs */
+  },
+  {                             /* Peephole optimizer */
+    _z80n_defaultRules,
+    z80instructionSize,
+    NULL,
+    NULL,
+    NULL,
+    z80notUsed,
+    z80canAssign,
+    z80notUsedFrom,
+    z80symmParmStack,
+    z80canJoinRegs,
+    z80canSplitReg,
+  },
+  /* Sizes: char, short, int, long, long long, near ptr, far ptr, gptr, func ptr, banked func ptr, bit, float */
+  { 1, 2, 2, 4, 8, 2, 2, 2, 2, 2, 1, 4 },
+  /* tags for generic pointers */
+  { 0x00, 0x40, 0x60, 0x80 },   /* far, near, xstack, code */
+  {
+    "XSEG",
+    "STACK",
+    "CODE",
+    "DATA",
+    NULL,                       /* idata */
+    NULL,                       /* pdata */
+    NULL,                       /* xdata */
+    NULL,                       /* bit */
+    "RSEG (ABS)",
+    "GSINIT",
+    NULL,                       /* overlay */
+    "GSFINAL",
+    "HOME",
+    NULL,                       /* xidata */
+    NULL,                       /* xinit */
+    NULL,                       /* const_name */
+    "CABS (ABS)",               /* cabs_name */
+    "DABS (ABS)",               /* xabs_name */
+    NULL,                       /* iabs_name */
+    "INITIALIZED",              /* name of segment for initialized variables */
+    "INITIALIZER",              /* name of segment for copies of initialized variables in code space */
+    NULL,
+    NULL,
+    1,                          /* CODE  is read-only */
+    1                           /* No fancy alignments supported. */
+  },
+  { NULL, NULL },
+  1,                            /* ABI revision */
+  { -1, 0, 0, 4, 0, 3, 0 },
+  { -1, FALSE },
+  { z80_emitDebuggerSymbol },
+  {
+    256,                        /* maxCount */
+    3,                          /* sizeofElement */
+    {6, 7, 8},                  /* sizeofMatchJump[] - Assumes operand allocated to registers */
+    {6, 9, 15},                 /* sizeofRangeCompare[] - Assumes operand allocated to registers*/
+    1,                          /* sizeofSubtract - Assumes use of a singel inc or dec */
+    9,                          /* sizeofDispatch - Assumes operand allocated to register e or c*/
+  },
+  "_",
+  _z80n_init,
+  _parseOptions,
+  _z80_options,
+  NULL,
   _finaliseOptions,
   _setDefaultOptions,
   z80_assignRegisters,
diff -Nru sdcc-4.0.0+dfsg/src/z80/mappings.i sdcc-4.2.0+dfsg/src/z80/mappings.i
--- sdcc-4.0.0+dfsg/src/z80/mappings.i	2018-11-14 12:55:26.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/z80/mappings.i	2021-11-16 15:46:09.000000000 +0000
@@ -7,39 +7,37 @@
     { "functionlabeldef", "%s:" },
     { "globalfunctionlabeldef", "%s::" },
     { "*hl", "(hl)" },
+    { "jphl", "jp (hl)" },
     { "di", "di" },
     { "ei", "ei" },
-    /*{ "ldahli", "ldi\ta, (hl)" }, use when assembler update is complete*/
-    {"ldahli", "ld\ta, (hl)\ninc\thl"},
+    { "ldahli", "ld\ta, (hl+)"},
+    { "ldahld", "ld\ta, (hl-)"},
+    { "lldahli", "ld\t(hl+), a"},
+    { "lldahld", "ld\t(hl-), a"},
+    { "rldh", "ldh a, (%s + %d)"},
+    { "lldh", "ldh (%s + %d), a"},
     { "ldahlsp", "ldhl\tsp, #%d" },
     { "ldaspsp", "add sp, #%d" },
-    { "*pair", "(%s)" },
+    { "mems", "(%s)" },
     { "enter", "" },
     { "enters", "" },
-    { "enterx", 
+    { "enterx",
       "add sp, #-%d" },
-    { "pusha", 
+    { "pusha",
       "push af\n"
       "push bc\n"
       "push de\n"
       "push hl"
     },
-    { "popa", 
+    { "popa",
       "pop hl\n"
       "pop de\n"
       "pop bc\n"
       "pop af"
     },
-    { "adjustsp", "lda sp, -%d(sp)" },
+    { "adjustsp", "add sp, #-%d" },
     { "fileprelude", "" },
-    { "profileenter",
-                "ld a, #3\n"
-                "rst\t0x08"
-    },
-    { "profileexit",
-                "ld a, #4\n"
-                "rst\t0x08"
-    },
+    { "here", "." },
     { NULL, NULL }
 };
 
@@ -52,48 +50,51 @@
     { "*ixx", "%d (ix)" },
     { "*iyx", "%d (iy)" },
     { "*hl", "(hl)" },
+    { "jphl", "jp (hl)" },
     { "di", "di" },
     { "ei", "ei" },
-    { "ldahli", 
-		"ld a, (hl)\n"
-		"inc\thl" },
-    { "ldahlsp", 
-		"ld hl, #%d\n"
-		"add\thl, sp" },
-    { "ldaspsp", 
-		"ld iy,#%d\n"
-		"add\tiy,sp\n"
-		"ld\tsp,iy" },
-    { "*pair", "(%s)" },
-    { "enter", 
-		"push\tix\n"
-		"ld\tix,#0\n"
-		"add\tix,sp" },
-    { "enters", 
-		"call\t___sdcc_enter_ix\n" },
-    { "pusha", 
-      		"push af\n"
-      		"push\tbc\n"
-      		"push\tde\n"
-      		"push\thl\n"
-		"push\tiy"
+    { "ldahli",
+      "ld a, (hl)\n"
+      "inc\thl" },
+    { "ldahld",
+      "ld a, (hl)\n"
+      "dec\thl" },
+    { "lldahli",
+      "ld (hl), a\n"
+      "inc\thl" },
+    { "lldahld",
+      "ld (hl), a\n"
+      "dec\thl" },
+    { "ldahlsp",
+      "ld hl, #%d\n"
+      "add\thl, sp" },
+    { "ldaspsp",
+      "ld iy,#%d\n"
+      "add\tiy,sp\n"
+      "ld\tsp,iy" },
+    { "mems", "(%s)" },
+    { "enter",
+      "push\tix\n"
+      "ld\tix,#0\n"
+      "add\tix,sp" },
+    { "enters",
+      "call\t___sdcc_enter_ix\n" },
+    { "pusha",
+      "push af\n"
+      "push\tbc\n"
+      "push\tde\n"
+      "push\thl\n"
+      "push\tiy"
     },
     { "popa",
-		"pop iy\n"
-		"pop\thl\n"
-		"pop\tde\n"
-		"pop\tbc\n"
-		"pop\taf"
+      "pop iy\n"
+      "pop\thl\n"
+      "pop\tde\n"
+      "pop\tbc\n"
+      "pop\taf"
     },
     { "adjustsp", "lda sp,-%d(sp)" },
-    { "profileenter",
-                "ld a,#3\n"
-                "rst\t0x08"
-    },
-    { "profileexit",
-                "ld a,#4\n"
-                "rst\t0x08"
-    },
+    { "here", "." },
     { NULL, NULL }
 };
 
@@ -106,79 +107,64 @@
     { "*ixx", "%d (ix)" },
     { "*iyx", "%d (iy)" },
     { "*hl", "(hl)" },
+    { "jphl", "jp (hl)" },
     { "di", "ipset3" },
     { "ei", "ipres" },
-    { "ldahli", 
-		"ld a, (hl)\n"
-		"inc\thl" },
-    { "ldahlsp", 
-		"ld hl, #%d\n"
-		"add\thl, sp" },
-    { "ldaspsp", 
-		"ld iy,#%d\n"
-		"add\tiy,sp\n"
-		"ld\tsp,iy" },
-    { "*pair", "(%s)" },
-    { "enter", 
-		"push\tix\n"
-		"ld\tix,#0\n"
-		"add\tix,sp" },
-    { "enters", 
-		"call\t___sdcc_enter_ix\n" },
-    { "pusha", 
-      		"push af\n"
-      		"push\tbc\n"
-      		"push\tde\n"
-      		"push\thl\n"
-		"push\tiy"
+    { "ldahli",
+      "ld a, (hl)\n"
+      "inc\thl" },
+    { "ldahld",
+      "ld a, (hl)\n"
+      "dec\thl" },
+    { "lldahli",
+      "ld (hl), a\n"
+      "inc\thl" },
+    { "lldahld",
+      "ld (hl), a\n"
+      "dec\thl" },
+    { "ldahlsp",
+      "ld hl, #%d\n"
+      "add\thl, sp" },
+    { "ldaspsp",
+      "ld iy,#%d\n"
+      "add\tiy,sp\n"
+      "ld\tsp,iy" },
+    { "mems", "(%s)" },
+    { "enter",
+      "push\tix\n"
+      "ld\tix,#0\n"
+      "add\tix,sp" },
+    { "enters",
+      "call\t___sdcc_enter_ix\n" },
+    { "pusha",
+      "push af\n"
+      "push\tbc\n"
+      "push\tde\n"
+      "push\thl\n"
+      "push\tiy"
     },
     { "popa",
-		"pop iy\n"
-		"pop\thl\n"
-		"pop\tde\n"
-		"pop\tbc\n"
-		"pop\taf"
+      "pop iy\n"
+      "pop\thl\n"
+      "pop\tde\n"
+      "pop\tbc\n"
+      "pop\taf"
     },
     { "adjustsp", "lda sp,-%d(sp)" },
-    { "profileenter",
-                "ld a,#3\n"
-                "rst\t0x28"
-    },
-    { "profileexit",
-                "ld a,#4\n"
-                "rst\t0x28"
-    },
     { NULL, NULL }
 };
 
 static const ASM_MAPPING _rgbds_mapping[] = {
-    { "global", "GLOBAL %s" },
-    { "extern", "GLOBAL %s" },
+    { "global", "EXPORT %s" },
+    { "extern", "" },
     { "slabeldef", "%s:" },
     { "labeldef", "%s:" },
     { "tlabeldef", ".l%05d:" },
     { "tlabel", ".l%05d" },
-    { "fileprelude", 
+    { "fileprelude",
       "; Generated using the rgbds tokens.\n"
-      "\t; We have to define these here as sdcc doesn't make them global by default\n"
-      "\tGLOBAL __mulschar\n"
-      "\tGLOBAL __muluchar\n"
-      "\tGLOBAL __mulint\n"
-      "\tGLOBAL __divschar\n"
-      "\tGLOBAL __divuchar\n"
-      "\tGLOBAL __divsint\n"
-      "\tGLOBAL __divuint\n"
-      "\tGLOBAL __modschar\n"
-      "\tGLOBAL __moduchar\n"
-      "\tGLOBAL __modsint\n"
-      "\tGLOBAL __moduint\n"
-      "\tGLOBAL __mullong\n"  
-      "\tGLOBAL __modslong\n"  
-      "\tGLOBAL __divslong\n"  
-      "\tGLOBAL banked_call\n"
-      "\tGLOBAL banked_ret\n"
     },
-    { "functionheader", 
+    { "functionheader",
       "; ---------------------------------\n"
       "; Function %s\n"
       "; ---------------------------------"
@@ -187,10 +173,10 @@
     { "globalfunctionlabeldef", "%s::" },
     { "zero", "$00" },
     { "one", "$01" },
-    { "area", "SECTION \"%s\",CODE" },
-    { "areadata", "SECTION \"%F_%s\",BSS" },
-    { "areacode", "SECTION \"%F_CODE\",%s" }, 
-    { "areahome", "SECTION \"%F_HOME\",HOME" },
+    { "area", "SECTION FRAGMENT \"_%s\",ROM0" },
+    { "areadata", "SECTION FRAGMENT \"%F_DATA\",%s" },
+    { "areacode", "SECTION FRAGMENT \"%F_CODE\",%s" },
+    { "areahome", "SECTION FRAGMENT \"%F_HOME\",ROM0" },
     { "ascii", "DB \"%s\"" },
     { "ds", "DS %d" },
     { "db", "DB" },
@@ -203,21 +189,25 @@
     { "immedword", "$%04X" },
     { "immedbyte", "$%02X" },
     { "hashedstr", "%s" },
-    { "lsbimmeds", "%s & $FF" },
-    { "msbimmeds", "%s >> 8" },
+    { "lsbimmeds", "LOW(%s)" },
+    { "msbimmeds", "HIGH(%s)" },
     { "bankimmeds", "BANK(%s)" },
+    { "hashedbankimmeds", "BANK(%s)" },
     { "module", "; MODULE %s" },
+    { "equ", "EQU" },
+    { "bequ", "\rb%s EQU %i" },
+    { "here", "@" },
     { NULL, NULL }
 };
 
 static const ASM_MAPPING _rgbds_gb_mapping[] = {
-    { "pusha", 
+    { "pusha",
       "push af\n"
       "\tpush bc\n"
       "\tpush de\n"
       "\tpush hl"
     },
-    { "popa", 
+    { "popa",
       "pop hl\n"
       "\tpop de\n"
       "\tpop bc\n"
@@ -228,11 +218,19 @@
     { "adjustsp", "add sp, -%d" },
     { "enter", "" },
     { "enters", "" },
+    { "enterx",
+      "add sp, -%d" },
+    { "rldh", "ldh a, [%s + %d]"},
+    { "lldh", "ldh [%s + %d], a"},
     { "ldahli", "ld a, [hl+]" },
+    { "ldahld", "ld a, [hl-]" },
+    { "lldahli", "ld [hl+], a" },
+    { "lldahld", "ld [hl-], a" },
     { "*hl", "[hl]" },
-    { "ldahlsp", "ld hl, [sp+%d]" },
+    { "jphl", "jp hl" },
+    { "ldahlsp", "ld hl, sp+%d" },
     { "ldaspsp", "add sp, %d" },
-    { "*pair", "[%s]" },
+    { "mems", "[%s]" },
     { NULL, NULL }
 };
 
@@ -243,7 +241,7 @@
     { "labeldef", "%s:" },
     { "tlabeldef", "?l%05d:" },
     { "tlabel", "?l%05d" },
-    { "fileprelude", 
+    { "fileprelude",
       ";Generated using the isas tokens.\n"
       "\tLPREFIX '?'  ; Treat labels starting with ? as local.\n"
       "\tONCNUM       ; Numbers are hex\n"
@@ -265,7 +263,7 @@
       "\tGLOBAL banked_call\n"
       "\tGLOBAL banked_ret\n"
     },
-    { "functionheader", 
+    { "functionheader",
       "; ---------------------------------\n"
       "; Function %s\n"
       "; ---------------------------------"
@@ -293,18 +291,19 @@
     { "lsbimmeds", "%s & 0xFF" },
     { "msbimmeds", "%s >> 8" },
     { "bankimmeds", "!%s" },
+    { "hashedbankimmeds", "!%s" },
     { "module", "; MODULE %s" },
     { NULL, NULL }
 };
 
 static const ASM_MAPPING _isas_gb_mapping[] = {
-    { "pusha", 
+    { "pusha",
       "push af\n"
       "push bc\n"
       "push de\n"
       "push hl"
     },
-    { "popa", 
+    { "popa",
       "pop hl\n"
       "pop de\n"
       "pop bc\n"
@@ -316,10 +315,14 @@
     { "enter", "" },
     { "enters", "" },
     { "ldahli", "ld a, (hli)" },
+    { "ldahld", "ld a, (hld)" },
+    { "lldahli", "ld (hli), a" },
+    { "lldahld", "ld (hld), a" },
     { "*hl", "(hl)" },
+    { "jphl", "jp (hl)" },
     { "ldahlsp", "ldhl sp, %d" },
     { "ldaspsp", "add sp, %d" },
-    { "*pair", "(%s)" },
+    { "mems", "(%s)" },
     { NULL, NULL }
 };
 
@@ -330,24 +333,24 @@
     { "labeldef", "\n.%s" },
     { "tlabeldef", "\n.l%N%05d" },
     { "tlabel", "l%N%05d" },
-    { "fileprelude", 
-        "; Generated using the z80asm/z88 tokens.\n"
-        "\tXREF __muluchar_rrx_s\n"
-        "\tXREF __mulschar_rrx_s\n"
-        "\tXREF __mulint_rrx_s\n"
-        "\tXREF __mullong_rrx_s\n"
-        "\tXREF __divuchar_rrx_s\n"
-        "\tXREF __divschar_rrx_s\n"
-        "\tXREF __divsint_rrx_s\n"
-        "\tXREF __divuint_rrx_s\n"
-        "\tXREF __divulong_rrx_s\n"
-        "\tXREF __divslong_rrx_s\n"
-        "\tXREF __rrulong_rrx_s\n"
-        "\tXREF __rrslong_rrx_s\n"
-        "\tXREF __rlulong_rrx_s\n"
-        "\tXREF __rlslong_rrx_s\n"
+    { "fileprelude",
+      "; Generated using the z80asm/z88 tokens.\n"
+      "\tXREF __muluchar_rrx_s\n"
+      "\tXREF __mulschar_rrx_s\n"
+      "\tXREF __mulint_rrx_s\n"
+      "\tXREF __mullong_rrx_s\n"
+      "\tXREF __divuchar_rrx_s\n"
+      "\tXREF __divschar_rrx_s\n"
+      "\tXREF __divsint_rrx_s\n"
+      "\tXREF __divuint_rrx_s\n"
+      "\tXREF __divulong_rrx_s\n"
+      "\tXREF __divslong_rrx_s\n"
+      "\tXREF __rrulong_rrx_s\n"
+      "\tXREF __rrslong_rrx_s\n"
+      "\tXREF __rlulong_rrx_s\n"
+      "\tXREF __rlslong_rrx_s\n"
     },
-    { "functionheader", 
+    { "functionheader",
       "; ---------------------------------\n"
       "; Function %s\n"
       "; ---------------------------------"
@@ -372,10 +375,11 @@
     { "msbimmeds", "%s / 256" },
 
     { "bankimmeds", "BANK(%s)" },
+    { "hashedbankimmeds", "BANK(%s)" },
     { "module", "MODULE %s" },
     { "area", "; Area  %s" },
     { "areadata", "; Aread BSS" },
-    { "areacode", "; Area CODE" }, 
+    { "areacode", "; Area CODE" },
     { "areahome", "; Area HOME" },
     { NULL, NULL }
 };
@@ -384,48 +388,151 @@
     { "*ixx", "(ix%+d)" },
     { "*iyx", "(iy%+d)" },
     { "*hl", "(hl)" },
+    { "jphl", "jp (hl)" },
+    { "di", "di" },
+    { "ei", "ei" },
+    { "ldahli",
+      "ld a, (hl)\n"
+      "inc\thl" },
+    { "ldahld",
+      "ld a, (hl)\n"
+      "dec\thl" },
+    { "ldahli",
+      "ld (hl), a\n"
+      "inc\thl" },
+    { "ldahld",
+      "ld (hl), a\n"
+      "dec\thl" },
+    { "ldahlsp",
+      "ld hl, %d\n"
+      "add\thl, sp" },
+    { "ldaspsp",
+      "ld iy, %d\n"
+      "add\tiy, sp\n"
+      "ld\tsp, iy" },
+    { "mems", "(%s)" },
+    { "enter",
+      "push\tix\n"
+      "ld\tix,0\n"
+      "add\tix,sp" },
+    { "enters",
+      "call\t___sdcc_enter_ix\n" },
+    { "pusha",
+      "push af\n"
+      "push\tbc\n"
+      "push\tde\n"
+      "push\thl\n"
+      "push\tiy"
+    },
+    { "popa",
+      "pop\tiy\n"
+      "pop\thl\n"
+      "pop\tde\n"
+      "pop\tbc\n"
+      "pop\taf"
+    },
+    { "adjustsp", "lda sp, (sp%+d)" },
+    { NULL, NULL }
+};
+static const ASM_MAPPING _gas_gb_mapping[] = {
+    { "immed", "#"},
+    { "zero", "#0x00"},
+    { "one", "#0x01"},
+    { "area", ".area\t%s" },
+    { "areacode", ".area\t%s"},
+    { "areadata", ".area\t%s"},
+    { "areahome", ".area\t%s"},
+    { "functionlabeldef", "%s:" },
+    { "globalfunctionlabeldef", "%s:" },
+    { "*hl", "(hl)" },
+    { "di", "di" },
+    { "ei", "ei" },
+    { "ldahli", "ldi\ta, (hl)" },
+    { "ldahld", "ldd\ta, (hl)" },
+    { "lldahli", "ldi\t(hl), a" },
+    { "lldahld", "ldd\t(hl), a" },
+    { "ldahlsp", "ldhl\tsp, #%d" },
+    { "ldaspsp", "add\tsp, #%d" },
+    { "mems", "(%s)" },
+    { "enter", "" },
+    { "enters", "" },
+    { "enterx", "add\tsp, #-%d" },
+    { "pusha", 
+      "push\taf\n"
+      "push\tbc\n"
+      "push\tde\n"
+      "push\thl"
+    },
+    { "popa", 
+      "pop\thl\n"
+      "pop\tde\n"
+      "pop\tbc\n"
+      "pop\taf"
+    },
+    { "adjustsp", "lda\tsp, -%d (sp)" },
+    { "fileprelude", "" },
+    { NULL, NULL }
+};
+
+static const ASM_MAPPING _gas_z80_mapping[] = {
+    {"immed", "#"},
+    {"zero", "#0x00"},
+    {"one", "#0x01"},
+    {"area", ".area\t%s"},
+    {"areacode", ".area\t%s"},
+    {"areadata", ".area\t%s"},
+    {"areahome", ".area\t%s"},
+    {"constbyte", "0x%02x"},
+    {"constword", "0x%04x"},
+    {"immedword", "#0x%04x"},
+    {"immedbyte", "#0x%02x"},
+    {"hashedstr", "#%s"},
+    {"bankimmeds", "%s >> 16"},
+    { "*ixx", "%d (ix)" },
+    { "*iyx", "%d (iy)" },
+    { "*hl", "(hl)" },
     { "di", "di" },
     { "ei", "ei" },
     { "ldahli", 
-		"ld a, (hl)\n"
+		"ld\ta,(hl)\n"
+		"inc\thl" },
+    { "ldahld", 
+		"ld\ta,(hl)\n"
+		"dec\thl" },
+    { "lldahli", 
+		"ld\t(hl),a\n"
 		"inc\thl" },
+    { "lldahld", 
+		"ld\t(hl),a\n"
+		"dec\thl" },
     { "ldahlsp", 
-		"ld hl, %d\n"
+		"ld\thl, #%d\n"
 		"add\thl, sp" },
     { "ldaspsp", 
-		"ld iy, %d\n"
-		"add\tiy, sp\n"
-		"ld\tsp, iy" },
-    { "*pair", "(%s)" },
+		"ld\tiy,#%d\n"
+		"add\tiy,sp\n"
+		"ld\tsp,iy" },
+    { "mems", "(%s)" },
     { "enter", 
 		"push\tix\n"
-		"ld\tix,0\n"
+		"ld\tix,#0\n"
 		"add\tix,sp" },
-    { "enters", 
-		"call\t___sdcc_enter_ix\n" },
+    { "enters", "call\t___sdcc_enter_ix\n" },
     { "pusha", 
-      		"push af\n"
+      		"push\taf\n"
       		"push\tbc\n"
       		"push\tde\n"
       		"push\thl\n"
 		"push\tiy"
     },
-    { "popa", 
+    { "popa",
 		"pop\tiy\n"
 		"pop\thl\n"
 		"pop\tde\n"
 		"pop\tbc\n"
 		"pop\taf"
     },
-    { "adjustsp", "lda sp, (sp%+d)" },
-    { "profileenter",
-                "ld a,3\n"
-                "rst\t$08"
-    },
-    { "profileexit",
-                "ld a,4\n"
-                "rst\t$08"
-    },
+    { "adjustsp", "lda\tsp,-%d (sp)" },
     { NULL, NULL }
 };
 
@@ -473,3 +580,13 @@
     &asm_asxxxx_mapping,
     _asxxxx_r2k_mapping
 };
+
+const ASM_MAPPINGS _gas_gb = {
+    &asm_gas_mapping,
+    _gas_gb_mapping
+};
+
+const ASM_MAPPINGS _gas_z80 = {
+    &asm_gas_mapping,
+    _gas_z80_mapping
+};
diff -Nru sdcc-4.0.0+dfsg/src/z80/peep.c sdcc-4.2.0+dfsg/src/z80/peep.c
--- sdcc-4.0.0+dfsg/src/z80/peep.c	2020-01-14 17:49:16.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/z80/peep.c	2021-12-10 14:48:15.000000000 +0000
@@ -72,71 +72,6 @@
 #define AOP(op) op->aop
 #define AOP_SIZE(op) AOP(op)->size
 
-static bool
-isReturned(const char *what)
-{
-  symbol *sym;
-  sym_link *sym_lnk;
-  int size;
-  lineNode *l;
-
-  if(strncmp(what, "iy", 2) == 0)
-    return FALSE;
-  if(strlen(what) != 1)
-    return TRUE;
-
-  l = _G.head;
-  do
-  {
-    l = l->next;
-  } while(l->isComment || l->ic == NULL || l->ic->op != FUNCTION);
-
-  sym = OP_SYMBOL(IC_LEFT(l->ic));
-
-  if(sym && IS_DECL(sym->type))
-    {
-      // Find size of return value.
-      specifier *spec;
-      if(sym->type->select.d.dcl_type != FUNCTION)
-        NOTUSEDERROR();
-      spec = &(sym->etype->select.s);
-      if(spec->noun == V_VOID || spec->noun == V_INT && spec->b_longlong) // long long is not returned via registers for the Z80-related ports
-        size = 0;
-      else if(spec->noun == V_CHAR || spec->noun == V_BOOL)
-        size = 1;
-      else if(spec->noun == V_INT && !(spec->b_long))
-        size = 2;
-      else
-        size = 4;
-
-      // Check for returned pointer.
-      sym_lnk = sym->type;
-      while (sym_lnk && !IS_PTR (sym_lnk))
-        sym_lnk = sym_lnk->next;
-      if(IS_PTR(sym_lnk))
-        size = 2;
-    }
-  else
-    {
-      NOTUSEDERROR();
-      size = 4;
-    }
-
-  switch(*what)
-    {
-    case 'd':
-      return(size >= 4);
-    case 'e':
-      return(size >= 3);
-    case 'h':
-      return(size >= 2);
-    case 'l':
-      return(size >= 1);
-    default:
-      return FALSE;
-    }
-}
-
 /*-----------------------------------------------------------------*/
 /* incLabelJmpToCount - increment counter "jmpToCount" in entry    */
 /* of the list labelHash                                           */
@@ -191,13 +126,11 @@
 
   /* 3. search lineNode with label definition and return it */
   for (cpl = _G.head; cpl; cpl = cpl->next)
-    {
-      if (cpl->isLabel
-          && strncmp (p, cpl->line, strlen(p)) == 0)
-        {
-          return cpl;
-        }
-    }
+    if (cpl->isLabel &&
+      strncmp (p, cpl->line, strlen(p)) == 0 &&
+      cpl->line[strlen(p)] == ':')
+        return cpl;
+
   return NULL;
 }
 
@@ -209,15 +142,19 @@
   while(isspace (*arg) || *arg == ',')
     arg++;
 
-  if (arg[0] == '#')
+  if (arg[0] == '#' || arg[0] == '_')
     return false;
 
-  if(arg[0] == '(' && arg[1] && arg[2] && (arg[2] != ')' && arg[3] != ')'))
-    return FALSE;
+  if(arg[0] == '(' && arg[1] && arg[2] && (arg[2] != ')' && arg[3] != ')')
+     && !(IS_SM83 && (arg[3] == '-' || arg[3] == '+') && arg[4] == ')'))
+    return false;
 
   if(*arg == '(')
     arg++;
 
+  if (arg[0] == '#' || arg[0] == '_')
+    return false;
+    
   // Get suitable end to avoid reading into further arguments.
   const char *end = strchr(arg, ',');
   if (!end)
@@ -243,10 +180,153 @@
     return TRUE;
   if (strchr(what, 'b') && z80_regs_used_as_parms_in_calls_from_current_function[B_IDX])
     return TRUE;
+  if (strchr(what, 'a') && z80_regs_used_as_parms_in_calls_from_current_function[A_IDX])
+    return true;
   if (strstr(what, "iy") && (z80_regs_used_as_parms_in_calls_from_current_function[IYL_IDX] || z80_regs_used_as_parms_in_calls_from_current_function[IYH_IDX]))
-    return TRUE;
+    return true;
 
-  return FALSE;
+  return false;
+}
+
+/* Check if the flag implies reading what. */
+static bool
+z80MightReadFlagCondition(const char *cond, const char *what)
+{
+  while(isspace (*cond))
+    cond++;
+
+  if(!STRNCASECMP(cond, "po", 2) || !STRNCASECMP(cond, "pe", 2))
+    return !strcmp(what, "pf");
+  if(tolower(cond[0]) == 'm' || tolower(cond[0]) == 'p')
+    return !strcmp(what, "sf");
+
+  // skip inverted conditions
+  if(tolower(cond[0]) == 'n')
+    cond++;
+
+  if(tolower(cond[0]) == 'c')
+    return !strcmp(what, "cf");
+  if(tolower(cond[0]) == 'z')
+    return !strcmp(what, "zf");
+  return true;
+}
+
+static bool
+z80MightReadFlag(const lineNode *pl, const char *what)
+{
+  if(ISINST(pl->line, "ld") ||
+     ISINST(pl->line, "or") ||
+     ISINST(pl->line, "cp") ||
+     ISINST(pl->line, "di") ||
+     ISINST(pl->line, "ei") ||
+     ISINST(pl->line, "im") ||
+     ISINST(pl->line, "in"))
+    return false;
+  if(ISINST(pl->line, "nop") ||
+     ISINST(pl->line, "add") ||
+     ISINST(pl->line, "sub") ||
+     ISINST(pl->line, "and") ||
+     ISINST(pl->line, "xor") ||
+     ISINST(pl->line, "dec") ||
+     ISINST(pl->line, "inc") ||
+     ISINST(pl->line, "cpl") ||
+     ISINST(pl->line, "bit") ||
+     ISINST(pl->line, "res") ||
+     ISINST(pl->line, "set") ||
+     ISINST(pl->line, "pop") ||
+     ISINST(pl->line, "rlc") ||
+     ISINST(pl->line, "rrc") ||
+     ISINST(pl->line, "sla") ||
+     ISINST(pl->line, "sra") ||
+     ISINST(pl->line, "srl") ||
+     ISINST(pl->line, "scf") ||
+     ISINST(pl->line, "cpd") ||
+     ISINST(pl->line, "cpi") ||
+     ISINST(pl->line, "ind") ||
+     ISINST(pl->line, "ini") ||
+     ISINST(pl->line, "ldd") ||
+     ISINST(pl->line, "ldi") ||
+     ISINST(pl->line, "neg") ||
+     ISINST(pl->line, "rld") ||
+     ISINST(pl->line, "rrd"))
+    return false;
+  if(ISINST(pl->line, "halt") ||
+     ISINST(pl->line, "rlca") ||
+     ISINST(pl->line, "rrca") ||
+     ISINST(pl->line, "cpdr") ||
+     ISINST(pl->line, "cpir") ||
+     ISINST(pl->line, "indr") ||
+     ISINST(pl->line, "inir") ||
+     ISINST(pl->line, "lddr") ||
+     ISINST(pl->line, "ldir") ||
+     ISINST(pl->line, "outd") ||
+     ISINST(pl->line, "outi") ||
+     ISINST(pl->line, "jdnz"))
+    return false;
+
+  if(IS_SM83 &&
+     (ISINST(pl->line, "stop") ||
+      ISINST(pl->line, "ldh")))
+    return false;
+
+  if((IS_SM83 || IS_Z80N) &&
+      ISINST(pl->line, "swap"))
+    return false;
+
+  if(ISINST(pl->line, "rl") ||
+     ISINST(pl->line, "rr") ||
+     ISINST(pl->line, "rla") ||
+     ISINST(pl->line, "rra") ||
+     ISINST(pl->line, "sbc") ||
+     ISINST(pl->line, "adc") ||
+     ISINST(pl->line, "ccf"))
+    return (!strcmp(what, "cf"));
+
+  if(ISINST(pl->line, "daa"))
+    return (!strcmp(what, "cf") || !strcmp(what, "nf") ||
+            !strcmp(what, "hf"));
+
+  if(ISINST(pl->line, "push"))
+    return (argCont(pl->line + 4, "af"));
+
+  if(ISINST(pl->line, "ex"))
+    return (argCont(pl->line + 2, "af"));
+
+  // catch c, nc, z, nz, po, pe, p and m
+  if(ISINST(pl->line, "jp") ||
+     ISINST(pl->line, "jr"))
+    return (strchr(pl->line, ',') && z80MightReadFlagCondition(pl->line + 2, what));
+
+  // flags don't matter according to calling convention
+  if(ISINST(pl->line, "reti") ||
+     ISINST(pl->line, "retn"))
+    return false;
+
+  if(ISINST(pl->line, "call"))
+    return (strchr(pl->line, ',') && z80MightReadFlagCondition(pl->line + 4, what));
+
+  if(ISINST(pl->line, "ret"))
+    return (pl->line[3] == '\t' && z80MightReadFlagCondition(pl->line + 3, what));
+
+  // we don't know anything about this
+  if(ISINST(pl->line, "rst"))
+    return true;
+
+  if (IS_SM83 && ISINST(pl->line, "ldhl"))
+    return false;
+    
+  if(IS_RAB && (ISINST(pl->line, "ioi") || ISINST(pl->line, "ioe")))
+    return(false);
+
+  if(IS_Z80N &&
+    (ISINST(pl->line, "bsla") ||
+    ISINST(pl->line, "bsra") ||
+    ISINST(pl->line, "bsrl") ||
+    ISINST(pl->line, "bsrf") ||
+    ISINST(pl->line, "brlc")))
+    return(false);
+
+  return true;
 }
 
 static bool
@@ -257,7 +337,10 @@
   if(strcmp(what, "ixl") == 0 || strcmp(what, "ixh") == 0)
     what = "ix";
 
-  if(strcmp(pl->line, "call\t__initrleblock") == 0)
+  if(ISINST(pl->line, "call") && strcmp(what, "sp") == 0)
+    return TRUE;
+
+  if(strcmp(pl->line, "call\t__initrleblock") == 0 && (strchr(what, 'd') != 0 || strchr(what, 'e') != 0))
     return TRUE;
 
   if(strcmp(pl->line, "call\t___sdcc_call_hl") == 0 && (strchr(what, 'h') != 0 || strchr(what, 'l') != 0))
@@ -266,44 +349,31 @@
   if(strcmp(pl->line, "call\t___sdcc_call_iy") == 0 && strstr(what, "iy") != 0)
     return TRUE;
 
-  if(strncmp(pl->line, "call\t", 5) == 0 && strchr(pl->line, ',') == 0)
+  if(strncmp(pl->line, "call\t___sdcc_bcall_", 19) == 0)
+    if (strchr (what, pl->line[19]) != 0 || strchr (what, pl->line[20]) != 0 || strchr (what, pl->line[21]) != 0)
+      return TRUE;
+
+  if(ISINST(pl->line, "call") && strchr(pl->line, ',') == 0)
     {
       const symbol *f = findSym (SymbolTab, 0, pl->line + 6);
       if (f)
-      {
-        const value *args = FUNC_ARGS (f->type);
-
-        if (IFFUNC_ISZ88DK_FASTCALL (f->type) && args) // Has one register argument of size up to 32 bit.
-          {
-            const unsigned int size = getSize (args->type);
-            wassert (!args->next); // Only one argment allowed in __z88dk_fastcall functions.
-            if (strchr(what, 'l') && size >= 1)
-              return TRUE;
-            if (strchr(what, 'h') && size >= 2)
-              return TRUE;
-            if (strchr(what, 'e') && size >= 3)
-              return TRUE;
-            if (strchr(what, 'd') && size >= 4)
-              return TRUE;
-          }
-        return FALSE;
-      }
+        return z80IsParmInCall(f->type, what);
       else // Fallback needed for calls through function pointers and for calls to literal addresses.
         return z80MightBeParmInCallFromCurrentFunction(what);
     }
 
   if(ISINST(pl->line, "reti") || ISINST(pl->line, "retn"))
-    return(false);
+    return(strcmp(what, "sp") == 0);
 
-  if(ISINST(pl->line, "ret")) // --reserve-regs-iy uses ret in code gen for calls through function pointers
-    return(IY_RESERVED ? isReturned(what) || z80MightBeParmInCallFromCurrentFunction(what) : isReturned(what));
+  if(ISINST(pl->line, "ret")) // --reserve-regs-iy and the sm83 port use ret in code gen for calls through function pointers
+    return((IY_RESERVED || IS_SM83) ? z80IsReturned(what) || z80MightBeParmInCallFromCurrentFunction(what) : z80IsReturned(what)) || strcmp(what, "sp") == 0;
 
   if(!strcmp(pl->line, "ex\t(sp), hl") || !strcmp(pl->line, "ex\t(sp),hl"))
-    return(!strcmp(what, "h") || !strcmp(what, "l"));
+    return(!strcmp(what, "h") || !strcmp(what, "l") || strcmp(what, "sp") == 0);
   if(!strcmp(pl->line, "ex\t(sp), ix") || !strcmp(pl->line, "ex\t(sp),ix"))
-    return(!!strstr(what, "ix"));
+    return(!!strstr(what, "ix") || strcmp(what, "sp") == 0);
   if(!strcmp(pl->line, "ex\t(sp), iy") || !strcmp(pl->line, "ex\t(sp),iy"))
-    return(!!strstr(what, "iy"));
+    return(!!strstr(what, "iy") || strcmp(what, "sp") == 0);
   if(!strcmp(pl->line, "ex\tde, hl") || !strcmp(pl->line, "ex\tde,hl"))
     return(!strcmp(what, "h") || !strcmp(what, "l") || !strcmp(what, "d") || !strcmp(what, "e"));
   if(ISINST(pl->line, "ld"))
@@ -312,10 +382,22 @@
         return(true);
       if(*(strchr(pl->line, ',') - 1) == ')' && strstr(pl->line + 3, what) && (strchr(pl->line, '#') == 0 || strchr(pl->line, '#') > strchr(pl->line, ',')))
         return(true);
+      if (!strcmp(what, "sp") && strchr(pl->line, '(')) // Assume any indirect memory access to be a stack access. This avoids optimizing out stackframe setups for local variables (bug #3173).
+        return(true);
       return(false);
     }
 
-  if(!strcmp(pl->line, "xor\ta, a") || !strcmp(pl->line, "xor\ta,a"))
+  //ld a, #0x00
+  if((ISINST(pl->line, "xor") || ISINST(pl->line, "sub")) &&
+     (!strcmp(pl->line+4, "a, a") || !strcmp(pl->line+4, "a,a") || (!strchr(pl->line, ',') && !strcmp(pl->line+4, "a"))))
+    return(false);
+
+  //ld a, #0x00
+  if(!strcmp(pl->line, "and\ta, #0x00") || !strcmp(pl->line, "and\ta,#0x00") || !strcmp(pl->line, "and\t#0x00"))
+    return(false);
+
+  //ld a, #0xff
+  if(!strcmp(pl->line, "or\ta, #0xff") || !strcmp(pl->line, "or\ta,#0xff") || !strcmp(pl->line, "or\t#0xff"))
     return(false);
 
   if(ISINST(pl->line, "adc") ||
@@ -328,18 +410,42 @@
       const char *arg = pl->line + 4;
       while(isspace(*arg))
         arg++;
-      if(*arg == 'a' && *(arg + 1) == ',')
+      if(arg[0] == 'a' && arg[1] == ',')
         {
           if(!strcmp(what, "a"))
             return(true);
           arg += 2;
         }
-      else if(!strncmp(arg, "hl", 2) && *(arg + 2) == ',')
+      else if(IS_Z80N && !strncmp(arg, "bc", 2) && *(arg + 2) == ',')
+        {
+          if(!strcmp(what, "b") || !strcmp(what, "c"))
+            return(true);
+          arg += 3;
+        }
+      else if(IS_Z80N && !strncmp(arg, "de", 2) && *(arg + 2) == ',')
+        {
+          if(!strcmp(what, "d") || !strcmp(what, "e"))
+            return(true);
+          arg += 3;
+        }
+      else if(!strncmp(arg, "hl", 2) && arg[2] == ',') // add hl, rr
         {
           if(!strcmp(what, "h") || !strcmp(what, "l"))
             return(true);
           arg += 3;
         }
+      else if(!strncmp(arg, "sp", 2) && arg[2] == ',') // add sp, rr
+        {
+          if(!strcmp(what, "sp"))
+            return(true);
+          arg += 3;
+        }
+      else if(arg[0] == 'i') // add ix/y, rr
+        {
+          if(!strncmp(arg, what, 2))
+            return(true);
+          arg += 3;
+        }
       return(argCont(arg, what));
     }
 
@@ -360,6 +466,12 @@
             return(true);
           arg += 3;
         }
+      else if(!strncmp(arg, "iy", 2) && *(arg + 2) == ',')
+        {
+          if(!strcmp(what, "iy"))
+            return(true);
+          arg += 3;
+        }
       return(argCont(arg, what));
     }
 
@@ -367,10 +479,10 @@
     return(strcmp(what, "a") == 0);
 
   if(ISINST(pl->line, "pop"))
-    return(false);
+    return(strcmp(what, "sp") == 0);
 
   if(ISINST(pl->line, "push"))
-    return(strstr(pl->line + 5, what) != 0);
+    return(strstr(pl->line + 5, what) != 0 || strcmp(what, "sp") == 0);
 
   if(ISINST(pl->line, "dec") ||
      ISINST(pl->line, "inc"))
@@ -388,7 +500,8 @@
   if(ISINST(pl->line, "rlca") ||
      ISINST(pl->line, "rla")  ||
      ISINST(pl->line, "rrca") ||
-     ISINST(pl->line, "rra"))
+     ISINST(pl->line, "rra")  ||
+     ISINST(pl->line, "daa"))
     {
       return(strcmp(what, "a") == 0);
     }
@@ -399,12 +512,17 @@
     }
   if(ISINST(pl->line, "rlc") ||
      ISINST(pl->line, "sla") ||
+     ISINST(pl->line, "rrc") ||
      ISINST(pl->line, "sra") ||
      ISINST(pl->line, "srl"))
     {
       return(argCont(pl->line + 4, what));
     }
-  if(!IS_GB && !IS_RAB &&
+  if((IS_SM83 || IS_Z80N) && ISINST(pl->line, "swap"))
+    {
+      return(argCont(pl->line + 5, what));
+    }
+  if(!IS_SM83 && !IS_RAB &&
     (ISINST(pl->line, "rld") ||
      ISINST(pl->line, "rrd")))
     return(!!strstr("ahl", what));
@@ -417,8 +535,11 @@
       return(argCont(strchr(pl->line + 4, ','), what));
     }
 
- if(ISINST(pl->line, "ccf") ||
-    ISINST(pl->line, "nop"))
+  if(ISINST(pl->line, "ccf") ||
+    ISINST(pl->line, "scf")  ||
+    ISINST(pl->line, "nop")  ||
+    ISINST(pl->line, "halt") ||
+    (IS_SM83 && ISINST(pl->line, "stop")))
     return(false);
 
   if(ISINST(pl->line, "jp") || ISINST(pl->line, "jr"))
@@ -427,18 +548,23 @@
   if(ISINST(pl->line, "djnz"))
     return(strchr(what, 'b') != 0);
 
-  if(!IS_GB && (ISINST(pl->line, "ldd") || ISINST(pl->line, "lddr") || ISINST(pl->line, "ldi") || ISINST(pl->line, "ldir")))
+  if(!IS_SM83 && (ISINST(pl->line, "ldd") || ISINST(pl->line, "lddr") || ISINST(pl->line, "ldi") || ISINST(pl->line, "ldir")))
     return(strchr("bcdehl", *what));
+  if(IS_SM83 && (ISINST(pl->line, "ldd") || ISINST(pl->line, "ldi")))
+    return(strchr("hl", *what) || strstr(strchr(pl->line + 4, ','), what) != 0);
 
-  if(!IS_GB && !IS_RAB && (ISINST(pl->line, "cpd") || ISINST(pl->line, "cpdr") || ISINST(pl->line, "cpi") || ISINST(pl->line, "cpir")))
+  if(!IS_SM83 && !IS_RAB && (ISINST(pl->line, "cpd") || ISINST(pl->line, "cpdr") || ISINST(pl->line, "cpi") || ISINST(pl->line, "cpir")))
     return(strchr("abchl", *what));
 
-  if(!IS_GB && !IS_RAB && ISINST(pl->line, "out"))
+  if(!IS_SM83 && !IS_RAB && ISINST(pl->line, "out"))
     return(strstr(strchr(pl->line + 4, ','), what) != 0 || strstr(pl->line + 4, "(c)") && (!strcmp(what, "b") || !strcmp(what, "c")));
-  if(!IS_GB && !IS_RAB && ISINST(pl->line, "in"))
+  if(!IS_SM83 && !IS_RAB && ISINST(pl->line, "in"))
     return(!strstr(strchr(pl->line + 4, ','), "(c)") && !strcmp(what, "a") || strstr(strchr(pl->line + 4, ','), "(c)") && (!strcmp(what, "b") || !strcmp(what, "c")));
 
-  if(!IS_GB && !IS_RAB &&
+  if(IS_SM83 && (ISINST(pl->line, "out") || ISINST(pl->line, "ldh") || ISINST(pl->line, "in")))
+    return(strstr(strchr(pl->line + 3, ','), what) != 0 || (!strcmp(what, "c") && strstr(pl->line + 3, "(c)")));
+
+  if(!IS_SM83 && !IS_RAB &&
     (ISINST(pl->line, "ini") || ISINST(pl->line, "ind") || ISINST(pl->line, "inir") || ISINST(pl->line, "indr") ||
     ISINST(pl->line, "outi") || ISINST(pl->line, "outd") || ISINST(pl->line, "otir") || ISINST(pl->line, "otdr")))
     return(strchr("bchl", *what));
@@ -446,7 +572,7 @@
   if((IS_Z180 || IS_EZ80_Z80) && ISINST(pl->line, "in0"))
     return(false);
 
-  if((IS_Z180 || IS_EZ80_Z80) && ISINST(pl->line, "mlt"))
+  if((IS_Z180 || IS_EZ80_Z80 || IS_Z80N) && ISINST(pl->line, "mlt"))
     return(argCont(pl->line + 4, what));
 
   if((IS_Z180 || IS_EZ80_Z80) &&
@@ -456,22 +582,45 @@
   if((IS_Z180 || IS_EZ80_Z80) && ISINST(pl->line, "slp"))
     return(false);
 
-  if((IS_Z180 || IS_EZ80_Z80) && ISINST(pl->line, "tst"))
+  if((IS_Z180 || IS_EZ80_Z80 || IS_Z80N) && ISINST(pl->line, "tst"))
     return(argCont(pl->line + 4, what));
 
   if((IS_Z180 || IS_EZ80_Z80) && ISINST(pl->line, "tstio"))
     return(!strcmp(what, "c"));
 
+  if(IS_RAB && (ISINST(pl->line, "ioi") || ISINST(pl->line, "ioe")))
+    return(false);
+    
   if(IS_RAB && ISINST(pl->line, "mul"))
     return(!strcmp(what, "b") || !strcmp(what, "c") || !strcmp(what, "d") || !strcmp(what, "e"));
 
   if(IS_RAB && ISINST(pl->line, "bool"))
     return(argCont(pl->line + 5, what));
+    
+  if(IS_R3KA && ISINST(pl->line, "lsdr") || ISINST(pl->line, "lidr") || ISINST(pl->line, "lsddr") || ISINST(pl->line, "lsidr"))
+    return(strchr("bcdehl", *what));
+
+  if(IS_EZ80_Z80 && ISINST(pl->line, "lea"))
+    return(argCont(strchr(pl->line + 4, ','), what));
+
+  if(IS_EZ80_Z80 && ISINST(pl->line, "pea"))
+    return(argCont(pl->line + 4, what) || !strcmp(what, "sp"));
+
+  if (IS_SM83 && (ISINST(pl->line, "lda") || ISINST(pl->line, "ldhl")))
+    return(!strcmp(what, "sp"));
+
+  if(IS_Z80N &&
+    (ISINST(pl->line, "bsla") ||
+    ISINST(pl->line, "bsra") ||
+    ISINST(pl->line, "bsrl") ||
+    ISINST(pl->line, "bsrf") ||
+    ISINST(pl->line, "brlc")))
+    return(strchr("bde", *what));
 
   /* TODO: Can we know anything about rst? */
   if(ISINST(pl->line, "rst"))
     return(true);
-
+    
   return(true);
 }
 
@@ -494,6 +643,110 @@
   return FALSE;
 }
 
+// TODO: z80 flags only partly implemented
+static bool
+z80SurelyWritesFlag(const lineNode *pl, const char *what)
+{
+  /* LD instruction is never change flags except LD A,I and LD A,R.
+    But it is most popular instruction so place it first */
+  if(ISINST(pl->line, "ld"))
+    {
+      if(IS_SM83 || IS_RAB || !!strcmp(what, "pf") ||
+          !argCont(pl->line+3, "a"))
+        return false;
+      const char *p = strchr(pl->line+4, ',');
+      if (p == NULL)
+        return false; /* unknown instruction */
+      ++p;
+      return argCont(p, "i") || argCont(p, "r");
+    }
+
+  if(ISINST(pl->line, "rlca") ||
+     ISINST(pl->line, "rrca") ||
+     ISINST(pl->line, "rra")  ||
+     ISINST(pl->line, "rla"))
+    return (IS_SM83 || !!strcmp(what, "zf") && !!strcmp(what, "sf") && !!strcmp(what, "pf"));
+
+  if(ISINST(pl->line, "adc") ||
+     ISINST(pl->line, "and") ||
+     ISINST(pl->line, "sbc") ||
+     ISINST(pl->line, "sub") ||
+     ISINST(pl->line, "xor") ||
+     ISINST(pl->line, "and") ||
+     ISINST(pl->line, "rlc") ||
+     ISINST(pl->line, "rrc") ||
+     ISINST(pl->line, "sla") ||
+     ISINST(pl->line, "sra") ||
+     ISINST(pl->line, "srl") ||
+     ISINST(pl->line, "neg"))
+    return true;
+
+  if(ISINST(pl->line, "or") ||
+     ISINST(pl->line, "cp") ||
+     ISINST(pl->line, "rl") ||
+     ISINST(pl->line, "rr"))
+    return true;
+
+  if(ISINST(pl->line, "bit") ||
+     ISINST(pl->line, "cpd") ||
+     ISINST(pl->line, "cpi") ||
+     ISINST(pl->line, "ind") ||
+     ISINST(pl->line, "ini") ||
+     ISINST(pl->line, "rrd"))
+    return (!!strcmp(what, "cf"));
+
+  if(ISINST(pl->line, "cpdr") ||
+     ISINST(pl->line, "cpir") ||
+     ISINST(pl->line, "indr") ||
+     ISINST(pl->line, "inir") ||
+     ISINST(pl->line, "otdr") ||
+     ISINST(pl->line, "otir") ||
+     ISINST(pl->line, "outd") ||
+     ISINST(pl->line, "outi"))
+    return (!!strcmp(what, "cf"));
+
+  if(ISINST(pl->line, "daa"))
+    return (!!strcmp(what, "nf"));
+
+  if(ISINST(pl->line, "scf") ||
+     ISINST(pl->line, "ccf"))
+    return (!!strcmp(what, "zf") && !!strcmp(what, "sf") && !!strcmp(what, "pf"));
+
+  if(ISINST(pl->line, "cpl"))
+    return (!!strcmp(what, "zf") && !!strcmp(what, "cf"));
+
+  // only for simple registers
+  if((ISINST(pl->line, "inc") ||
+      ISINST(pl->line, "dec")) && (strlen(pl->line+4) == 1))
+    return (!!strcmp(what, "cf"));
+
+  if(ISINST(pl->line, "add"))
+    return (argCont(pl->line + 4, "a") ||
+           (!!strcmp(what, "zf") && !!strcmp(what, "sf") && !!strcmp(what, "pf")));
+
+  // pop af writes
+  if(ISINST(pl->line, "pop"))
+    return (argCont(pl->line + 4, "af"));
+
+  // according to calling convention caller has to save flags
+  if(ISINST(pl->line, "ret") ||
+     ISINST(pl->line, "call"))
+    return true;
+
+  if(IS_SM83 &&
+     (ISINST(pl->line, "swap") ||
+      ISINST(pl->line, "ldhl") ||
+      ISINST(pl->line, "lda")))
+    return true;
+
+  /* handle IN0 r,(n) and IN r,(c) instructions */
+  if(ISINST(pl->line, "in0") || (!strncmp(pl->line, "in\t", 3) &&
+     (!strcmp(pl->line+5, "(c)") || !strcmp(pl->line+5, "(bc)"))))
+    return (!!strcmp(what, "cf"));
+
+  return false;
+}
+
 static bool
 z80SurelyWrites(const lineNode *pl, const char *what)
 {
@@ -502,8 +755,19 @@
   if(strcmp(what, "ixl") == 0 || strcmp(what, "ixh") == 0)
     what = "ix";
 
-  if(ISINST(pl->line, "xor") && strcmp(what, "a") == 0)
+  //ld a, #0x00
+  if((ISINST(pl->line, "xor") || ISINST(pl->line, "sub")) && !strcmp(what, "a") &&
+     (!strcmp(pl->line+4, "a, a") || !strcmp(pl->line+4, "a,a") || (!strchr(pl->line, ',') && !strcmp(pl->line+4, "a"))))
+    return(true);
+
+  //ld a, #0x00
+  if(!strcmp(what, "a") && (!strcmp(pl->line, "and\ta, #0x00") || !strcmp(pl->line, "and\ta,#0x00") || !strcmp(pl->line, "and\t#0x00")))
+    return(true);
+
+  //ld a, #0xff
+  if(!strcmp(what, "a") && (!strcmp(pl->line, "or\ta, #0xff") || !strcmp(pl->line, "or\ta,#0xff") || !strcmp(pl->line, "or\t#0xff")))
     return(true);
+
   if(ISINST(pl->line, "ld") && strncmp(pl->line + 3, "hl", 2) == 0 && (what[0] == 'h' || what[0] == 'l'))
     return(true);
   if(ISINST(pl->line, "ld") && strncmp(pl->line + 3, "de", 2) == 0 && (what[0] == 'd' || what[0] == 'e'))
@@ -513,6 +777,10 @@
   if((ISINST(pl->line, "ld") || ISINST(pl->line, "in"))
     && strncmp(pl->line + 3, what, strlen(what)) == 0 && pl->line[3 + strlen(what)] == ',')
     return(true);
+
+  if(IS_SM83 && (ISINST(pl->line, "ldd") || ISINST(pl->line, "ldi") || ISINST(pl->line, "ldh")))
+    return(strncmp(pl->line + 4, what, strlen(what)) == 0);
+
   if(ISINST(pl->line, "pop") && strstr(pl->line + 4, what))
     return(true);
   if(ISINST(pl->line, "call") && strchr(pl->line, ',') == 0)
@@ -545,14 +813,13 @@
     }
   if(strcmp(pl->line, "ret") == 0)
     return true;
-  if(strcmp(pl->line, "ld\tiy")  == 0 && strncmp(what, "iy", 2) == 0)
-    return true;
+
+  if (IS_Z180 || IS_EZ80_Z80 || IS_Z80N)
+    if (ISINST(pl->line, "mlt"))
+      return(strchr(pl->line + 4, *what) != 0);
 
   if (IS_Z180 || IS_EZ80_Z80)
     {
-      if (ISINST(pl->line, "mlt"))
-        return(strchr(pl->line + 4, *what) != 0);
-
       if (ISINST(pl->line, "otim") ||
         ISINST(pl->line, "otimr") ||
         ISINST(pl->line, "otdm") ||
@@ -563,13 +830,22 @@
         return(!strncmp(pl->line + 4, what, strlen(what)));
     }
 
+  if (IS_EZ80_Z80 && ISINST(pl->line, "lea"))
+    return (strstr(pl->line + 4, what));
+
+  if (IS_SM83 && ISINST(pl->line, "lda") && strncmp(pl->line + 4, "hl", 2) == 0 && (what[0] == 'h' || what[0] == 'l'))
+    return(true);
+
+  if (IS_SM83 && ISINST(pl->line, "ldhl") && (what[0] == 'h' || what[0] == 'l'))
+    return(true);
+
   return(false);
 }
 
 static bool
 z80SurelyReturns(const lineNode *pl)
 {
-  if(strcmp(pl->line, "\tret") == 0)
+  if(strcmp(pl->line, "ret") == 0)
     return TRUE;
   return FALSE;
 }
@@ -614,6 +890,7 @@
 scan4op (lineNode **pl, const char *what, const char *untilOp,
          lineNode **plCond)
 {
+  bool isFlag = (strlen(what) == 2 && what[1] == 'f');
   for (; *pl; *pl = (*pl)->next)
     {
       if (!(*pl)->line || (*pl)->isDebug || (*pl)->isComment || (*pl)->isLabel)
@@ -635,10 +912,21 @@
 
       (*pl)->visited = TRUE;
 
-      if(z80MightRead(*pl, what))
+      if(isFlag)
         {
-          D(("S4O_RD_OP\n"));
-          return S4O_RD_OP;
+        if(z80MightReadFlag(*pl, what))
+          {
+            D(("S4O_RD_OP (flag)\n"));
+            return S4O_RD_OP;
+          }
+        }
+      else
+        {
+        if(z80MightRead(*pl, what))
+          {
+            D(("S4O_RD_OP\n"));
+            return S4O_RD_OP;
+          }
         }
 
       if(z80UncondJump(*pl))
@@ -662,10 +950,21 @@
           return S4O_CONDJMP;
         }
 
-      if(z80SurelyWrites(*pl, what))
+      if(isFlag)
         {
-          D(("S4O_WR_OP\n"));
-          return S4O_WR_OP;
+        if(z80SurelyWritesFlag(*pl, what))
+          {
+            D(("S4O_WR_OP (flag)\n"));
+            return S4O_WR_OP;
+          }
+        }
+      else
+        {
+        if(z80SurelyWrites(*pl, what))
+          {
+            D(("S4O_WR_OP\n"));
+            return S4O_WR_OP;
+          }
         }
 
       /* Don't need to check for de, hl since z80MightRead() does that */
@@ -758,8 +1057,6 @@
     return TRUE;
   if(strcmp(what, "hl") == 0)
     return TRUE;
-  if(strcmp(what, "sp") == 0)
-    return TRUE;
   if(strcmp(what, "ix") == 0)
     return TRUE;
   if(strcmp(what, "iy") == 0)
@@ -774,6 +1071,29 @@
 {
   lineNode *pl;
   D(("Checking for %s\n", what));
+
+  if(strcmp(what, "af") == 0)
+    {
+      if(!z80notUsed("a", endPl, head))
+        return FALSE;
+      what++;
+    }
+
+  if(strcmp(what, "f") == 0)
+    return z80notUsed("zf", endPl, head) && z80notUsed("cf", endPl, head) &&
+           z80notUsed("sf", endPl, head) && z80notUsed("pf", endPl, head) &&
+           z80notUsed("nf", endPl, head) && z80notUsed("hf", endPl, head);
+
+  if(strcmp(what, "iy") == 0)
+    {
+      if(IY_RESERVED)
+        return FALSE;
+      return(z80notUsed("iyl", endPl, head) && z80notUsed("iyh", endPl, head));
+    }
+
+  if(strcmp(what, "ix") == 0)
+    return(z80notUsed("ixl", endPl, head) && z80notUsed("ixh", endPl, head));
+
   if(isRegPair(what))
     {
       char low[2], high[2];
@@ -781,22 +1101,24 @@
       high[0] = what[0];
       low[1] = 0;
       high[1] = 0;
-      if(strcmp(what, "iy") == 0)
-        {
-          if(IY_RESERVED)
-            return FALSE;
-          return(z80notUsed("iyl", endPl, head) && z80notUsed("iyh", endPl, head));
-        }
-      if(strcmp(what, "ix") == 0)
-        {
-          if(IY_RESERVED)
-            return FALSE;
-          return(z80notUsed("ixl", endPl, head) && z80notUsed("ixh", endPl, head));
-        }
       return(z80notUsed(low, endPl, head) && z80notUsed(high, endPl, head));
     }
 
-  if(!isReg(what) && !isUReg(what))
+  // P/V and L/V (rarbbits) are the same flag
+  if(!strcmp(what, "vf") || !strcmp(what, "lf"))
+    what = "pf";
+
+  // SM83 does not use what it does not have
+  // but this allows to write rules for all Z80ies
+  if(IS_SM83 && (!strcmp(what, "sf") || !strcmp(what, "pf")))
+    {
+      D(("Flag %s does not exist\n", what));
+      return true;
+    }
+
+  // enable sp and flags
+  if(!isReg(what) && !isUReg(what) &&
+     strcmp(what, "sp") && strcmp(what+1, "f"))
     return FALSE;
 
   _G.head = head;
@@ -836,12 +1158,12 @@
   {
     if(!strcmp(exotic, "ix") || !strcmp(exotic, "iy"))
     {
-      if(isReg(op1))
+      if(isReg(op1) || (IS_EZ80_Z80 && isRegPair(op1)))
         return TRUE;
     }
     else if(!strcmp(op2, "ix") || !strcmp(op2, "iy"))
     {
-      if(isReg(exotic) || exotic[0] == '#')
+      if(isReg(exotic) || exotic[0] == '#' || (IS_EZ80_Z80 && isRegPair(exotic)))
         return TRUE;
     }
 
@@ -857,31 +1179,121 @@
     return TRUE;
 
   // Same if at most one of them is (hl).
-  if(isReg(dst) && !strcmp(src, "(hl)"))
+  if((isReg(dst) || (IS_EZ80_Z80 && isRegPair(dst))) && !strcmp(src, "(hl)"))
     return TRUE;
-  if(!strcmp(dst, "(hl)") && isReg(src))
+  if(!strcmp(dst, "(hl)") && (isReg(src) || (IS_EZ80_Z80 && isRegPair(src))))
     return TRUE;
 
-  // Can assign between a and (bc), (de)
-  if(!strcmp(dst, "a") && (!strcmp(src, "(bc)") || ! strcmp(src, "(de)")))
+  // Can assign between a and (bc), (de), (hl+), (hl-)
+  if(!strcmp(dst, "a") &&
+     (!strcmp(src, "(bc)") || !strcmp(src, "(de)") || !strcmp(src, "(hl+)") || !strcmp(src, "(hl-)")))
     return TRUE;
-  if((!strcmp(dst, "(bc)") || ! strcmp(dst, "(de)")) && !strcmp(src, "a"))
+  if((!strcmp(dst, "(bc)") || !strcmp(dst, "(de)") || !strcmp(src, "(hl+)") || !strcmp(src, "(hl-)"))
+     && !strcmp(src, "a"))
     return TRUE;
 
   // Can load immediate values directly into registers and register pairs.
-  if((isReg(dst) || isRegPair(dst)) && src[0] == '#')
+  if((isReg(dst) || isRegPair(dst) || !strcmp(src, "sp")) && src[0] == '#')
     return TRUE;
 
-  if((!strcmp(dst, "a") || isRegPair(dst)) && !strncmp(src, "(#", 2))
+  if((!strcmp(dst, "a") || (!IS_SM83 && (isRegPair(dst) || !strcmp(src, "sp")))) && !strncmp(src, "(#", 2))
     return TRUE;
-  if(!strncmp(dst, "(#", 2) && (!strcmp(src, "a") || isRegPair(src)))
+  if(!strncmp(dst, "(#", 2) && (!strcmp(src, "a") || (!IS_SM83 && isRegPair(src)) || !strcmp(src, "sp")))
     return TRUE;
 
   // Can load immediate values directly into (hl).
   if(!strcmp(dst, "(hl)") && src[0] == '#')
-    return TRUE;
+    return true;
 
-  return FALSE;
+  // Can load between hl / ix / iy and sp.
+  if(!strcmp(dst, "sp") && (!strcmp(src, "hl") || !strcmp(src, "ix") || !strcmp(src, "iy")) ||
+    (!strcmp(dst, "hl") || !strcmp(dst, "ix") || !strcmp(dst, "iy")) && !strcmp(src, "sp"))
+    return true;
+
+  // Rabbit can load between iy and hl.
+  if (IS_RAB &&
+    (!strcmp(dst, "hl") && (!strcmp(src, "ix") || !strcmp(src, "iy")) ||
+    (!strcmp(dst, "ix") || !strcmp(dst, "iy")) && !strcmp(src, "hl")))
+    return true;
+
+  return false;
+}
+
+static const char *
+registerBaseName (const char *op)
+{
+  if (!strcmp (op, "d") || !strcmp (op, "e") || !strcmp (op, "(de)"))
+    return "de";
+  if (!strcmp (op, "b") || !strcmp (op, "c") || !strcmp (op, "(bc)"))
+    return "bc";
+  if (!strcmp (op, "h") || !strcmp (op, "l") || !strcmp (op, "(hl)") || !strcmp (op, "(hl+)")  || !strcmp (op, "(hl-)"))
+    return "hl";
+  if (!strcmp (op, "iyh") || !strcmp (op, "iyl") || strstr (op, "iy"))
+    return "iy";
+  if (!strcmp (op, "ixh") || !strcmp (op, "ixl") || strstr (op, "ix"))
+    return "ix";
+  if (!strcmp (op, "a"))
+    return "af";
+  return op;
+}
+
+// canJoinRegs(reg_hi reg_lo [dst]) returns TRUE,
+bool z80canJoinRegs (const char **regs, char dst[20])
+{
+  //check for only 2 source registers
+  if (!regs[0] || !regs[1] || regs[2])
+    return FALSE;
+  size_t l1 = strlen (regs[0]);
+  size_t l2 = strlen (regs[1]);
+  if (l1 + l2 >= 20)
+    return FALSE;
+  if (l1 == 0 || l2 == 0)
+    {
+      if (l1 == 0 && l2 == 0)
+        return FALSE;
+      strcpy (dst, registerBaseName (regs[l1 ? 0 : 1]));
+    }
+  else
+    {
+      memcpy (&dst[0], regs[0], l1);
+      memcpy (&dst[l1], regs[1], l2 + 1); //copy including \0
+    }
+  if (!strcmp (dst, "ixhixl") || !strcmp (dst, "iyhiyl"))
+    {
+      if (IS_SM83)
+        return FALSE;
+      dst[2] = '\0';
+    }
+  return isRegPair (dst);
+}
+
+bool z80canSplitReg (const char *reg, char dst[][16], int nDst)
+{
+  int i;
+  if (nDst < 0 || nDst > 2)
+    return FALSE;
+  if (!strcmp (reg, "bc") || !strcmp (reg, "de") || !strcmp (reg, "hl"))
+    {
+      for (i = 0; i < nDst; ++i)
+        {
+          dst[i][0] = reg[i];
+          dst[i][1] = '\0';
+        }
+    }
+  else if (!IS_SM83 && (!strcmp (reg, "ix") || !strcmp (reg, "iy")))
+    {
+      for (i = 0; i < nDst; ++i)
+        {
+          dst[i][0] = reg[0];
+          dst[i][1] = reg[1];
+          dst[i][2] = "hl"[i];
+          dst[i][3] = '\0';
+        }
+    }
+  else
+    return FALSE;
+
+  return TRUE;
 }
 
 int z80instructionSize(lineNode *pl)
@@ -889,7 +1301,7 @@
   const char *op1start, *op2start;
 
   /* move to the first operand:
-   * leading spaces are already removed, skip the mnenonic */
+   * leading spaces are already removed, skip the mnemonic */
   for (op1start = pl->line; *op1start && !isspace (*op1start); ++op1start);
 
   /* skip the spaces between mnemonic and the operand */
@@ -929,10 +1341,11 @@
         return(4);
 
       if(op1start[0] == '('               && STRNCASECMP(op1start, "(bc)", 4) &&
-         STRNCASECMP(op1start, "(de)", 4) && STRNCASECMP(op1start, "(hl)", 4) &&
-         STRNCASECMP(op2start, "hl", 2)   && STRNCASECMP(op2start, "a", 1) ||
+         STRNCASECMP(op1start, "(de)", 4) && STRNCASECMP(op1start, "(hl" , 3) &&
+         STRNCASECMP(op2start, "hl", 2)   && STRNCASECMP(op2start, "a", 1)   &&
+         (!IS_SM83 || STRNCASECMP(op2start, "sp", 2)) ||
          op2start[0] == '('               && STRNCASECMP(op2start, "(bc)", 4) &&
-         STRNCASECMP(op1start, "(de)", 4) && STRNCASECMP(op2start, "(hl)", 4) &&
+         STRNCASECMP(op1start, "(de)", 4) && STRNCASECMP(op2start, "(hl" , 3) &&
          STRNCASECMP(op1start, "hl", 2)   && STRNCASECMP(op1start, "a", 1))
         return(4);
 
@@ -942,7 +1355,8 @@
       if(IS_RAB && !STRNCASECMP(op1start, "hl", 2) && (argCont(op2start, "(sp)") || argCont(op2start, "(ix)")))
         return(3);
 
-      if(IS_EZ80_Z80 && /* eZ80 16-bit pointer load */
+      /* eZ80 16-bit pointer load */
+      if(IS_EZ80_Z80 &&
         (!STRNCASECMP(op1start, "bc", 2) || !STRNCASECMP(op1start, "de", 2) || !STRNCASECMP(op1start, "hl", 2) || !STRNCASECMP(op1start, "ix", 2) || !STRNCASECMP(op1start, "iy", 2)))
         {
           if (!STRNCASECMP(op2start, "(hl)", 4))
@@ -950,14 +1364,22 @@
           if (argCont(op2start, "(ix)") || argCont(op2start, "(iy)"))
             return(3);
         }
+      if(IS_EZ80_Z80 &&
+        (!STRNCASECMP(op2start, "bc", 2) || !STRNCASECMP(op2start, "de", 2) || !STRNCASECMP(op2start, "hl", 2) || !STRNCASECMP(op2start, "ix", 2) || !STRNCASECMP(op2start, "iy", 2)))
+        {
+          if (!STRNCASECMP(op1start, "(hl)", 4))
+            return(2);
+          if (argCont(op1start, "(ix)") || argCont(op1start, "(iy)"))
+            return(3);
+        }
 
       /* These 4 are the only remaining cases of 3 byte long ld instructions. */
       if(argCont(op2start, "(ix)") || argCont(op2start, "(iy)"))
         return(3);
       if(argCont(op1start, "(ix)") || argCont(op1start, "(iy)"))
         return(3);
-      if((op1start[0] == '(' && STRNCASECMP(op1start, "(bc)", 4) && STRNCASECMP(op1start, "(de)", 4) && STRNCASECMP(op1start, "(hl)", 4)) ||
-         (op2start[0] == '(' && STRNCASECMP(op2start, "(bc)", 4) && STRNCASECMP(op2start, "(de)", 4) && STRNCASECMP(op2start, "(hl)", 4)))
+      if((op1start[0] == '(' && STRNCASECMP(op1start, "(bc)", 4) && STRNCASECMP(op1start, "(de)", 4) && STRNCASECMP(op1start, "(hl", 3)) ||
+         (op2start[0] == '(' && STRNCASECMP(op2start, "(bc)", 4) && STRNCASECMP(op2start, "(de)", 4) && STRNCASECMP(op2start, "(hl", 3)))
         return(3);
       if(op2start[0] == '#' &&
          (!STRNCASECMP(op1start, "bc", 2) || !STRNCASECMP(op1start, "de", 2) || !STRNCASECMP(op1start, "hl", 2) || !STRNCASECMP(op1start, "sp", 2)))
@@ -976,6 +1398,19 @@
       return(1);
     }
 
+  // load from sp with offset
+  if(IS_SM83 && (ISINST(pl->line, "lda") || ISINST(pl->line, "ldhl")))
+    {
+      return(2);
+    }
+  // load from/to 0xffXX addresses
+  if(IS_SM83 && (ISINST(pl->line, "ldh")))
+    {
+      if(!STRNCASECMP(pl->line, "(c)", 3))
+        return(1);
+      return(2);
+    }
+
   /* Exchange */
   if(ISINST(pl->line, "exx"))
     return(1);
@@ -992,6 +1427,8 @@
     }
 
   /* Push / pop */
+  if(ISINST(pl->line, "push")  && IS_Z80N && op1start[0] == '#')
+    return(4);
   if(ISINST(pl->line, "push") || ISINST(pl->line, "pop"))
     {
       if(!STRNCASECMP(op1start, "ix", 2) || !STRNCASECMP(op1start, "iy", 2))
@@ -999,27 +1436,29 @@
       return(1);
     }
 
-  /* 16 bit add / subtract / and */
-  if((ISINST(pl->line, "add") || ISINST(pl->line, "adc") || ISINST(pl->line, "sbc") || IS_RAB && ISINST(pl->line, "and")) &&
+  /* 16 bit add / subtract / and / or */
+  if(IS_Z80N && ISINST(pl->line, "add") && (!STRNCASECMP(op1start, "bc", 2) || !STRNCASECMP(op1start, "de", 2) || !STRNCASECMP(op1start, "hl", 2)))
+    return(4);
+  if((ISINST(pl->line, "add") || ISINST(pl->line, "adc") || ISINST(pl->line, "sbc") || IS_RAB && (ISINST(pl->line, "and") || ISINST(pl->line, "or"))) &&
      !STRNCASECMP(op1start, "hl", 2))
     {
-      if(ISINST(pl->line, "add") || ISINST(pl->line, "and"))
+      if(ISINST(pl->line, "add") || ISINST(pl->line, "and") || ISINST(pl->line, "or"))
         return(1);
       return(2);
     }
-  if(ISINST(pl->line, "add") && (!STRNCASECMP(op1start, "ix", 2) || !STRNCASECMP(op1start, "iy", 2)))
+  if((ISINST(pl->line, "add") || IS_RAB && (ISINST(pl->line, "and") || ISINST(pl->line, "or")))&& (!STRNCASECMP(op1start, "ix", 2) || !STRNCASECMP(op1start, "iy", 2)))
     return(2);
 
   /* signed 8 bit adjustment to stack pointer */
-  if((IS_RAB || IS_GB) && ISINST(pl->line, "add") && !STRNCASECMP(op1start, "sp", 2))
+  if((IS_RAB || IS_SM83) && ISINST(pl->line, "add") && !STRNCASECMP(op1start, "sp", 2))
     return(2);
 
   /* 16 bit adjustment to stack pointer */
   if(IS_TLCS90 && ISINST(pl->line, "add") && !STRNCASECMP(op1start, "sp", 2))
     return(3);
-  
+
   /* 8 bit arithmetic, two operands */
-  if(op2start &&  op1start[0] == 'a' &&
+  if(op2start && op1start[0] == 'a' &&
      (ISINST(pl->line, "add") || ISINST(pl->line, "adc") || ISINST(pl->line, "sub") || ISINST(pl->line, "sbc") ||
       ISINST(pl->line, "cp")  || ISINST(pl->line, "and") || ISINST(pl->line, "or")  || ISINST(pl->line, "xor")))
     {
@@ -1079,11 +1518,11 @@
        ISINST(pl->line, "ipset1") || ISINST(pl->line, "ipset0") ||
        ISINST(pl->line, "ipres")))
     return(2);
-  
-  if(ISINST(pl->line, "reti") || ISINST(pl->line, "retn"))
+
+  if(!IS_SM83 && (ISINST(pl->line, "reti") || ISINST(pl->line, "retn")))
     return(2);
 
-  if(ISINST(pl->line, "ret") || ISINST(pl->line, "rst"))
+  if(ISINST(pl->line, "ret") || ISINST(pl->line, "reti") || ISINST(pl->line, "rst"))
     return(1);
 
   if(ISINST(pl->line, "call"))
@@ -1096,7 +1535,8 @@
     return(2);
 
   if(ISINST(pl->line, "daa") || ISINST(pl->line, "cpl")  || ISINST(pl->line, "ccf") || ISINST(pl->line, "scf") ||
-     ISINST(pl->line, "nop") || ISINST(pl->line, "halt") || ISINST(pl->line,  "ei") || ISINST(pl->line, "di"))
+     ISINST(pl->line, "nop") || ISINST(pl->line, "halt") || ISINST(pl->line,  "ei") || ISINST(pl->line, "di")  ||
+     (IS_SM83 && ISINST(pl->line, "stop")))
     return(1);
 
   if(ISINST(pl->line, "im"))
@@ -1108,15 +1548,15 @@
   if((IS_Z180 || IS_EZ80_Z80) && (ISINST(pl->line, "in0") || ISINST(pl->line, "out0")))
     return(3);
 
-  if(ISINST(pl->line, "di") || ISINST(pl->line, "ei"))
-    return(1);
-
-  if((IS_Z180 || IS_EZ80_Z80) && ISINST(pl->line, "mlt"))
+  if((IS_Z180 || IS_EZ80_Z80 || IS_Z80N) && ISINST(pl->line, "mlt"))
     return(2);
 
-  if((IS_Z180 || IS_EZ80_Z80) && ISINST(pl->line, "tst"))
+  if((IS_Z180 || IS_EZ80_Z80 || IS_Z80N) && ISINST(pl->line, "tst"))
     return((op1start[0] == '#' || op2start && op1start[0] == '#') ? 3 : 2);
-  
+
+  if(IS_RAB && (ISINST(pl->line, "ioi") || ISINST(pl->line, "ioe")))
+    return(1);
+    
   if(IS_RAB && ISINST(pl->line, "mul"))
     return(1);
 
@@ -1128,7 +1568,7 @@
      ISINST(pl->line, "lsdr")  || ISINST(pl->line, "lsir")  ||
      ISINST(pl->line, "lsddr") || ISINST(pl->line, "lsidr")))
     return(2);
-  
+
   if(IS_R3KA && (ISINST(pl->line, "uma") || ISINST(pl->line, "ums")))
     return(2);
 
@@ -1138,6 +1578,17 @@
   if(IS_EZ80_Z80 && (ISINST(pl->line, "lea") || ISINST(pl->line, "pea")))
     return(3);
 
+  if((IS_SM83 || IS_Z80N) && ISINST(pl->line, "swap"))
+    return(2);
+
+  if(IS_Z80N &&
+    (ISINST(pl->line, "bsla") ||
+    ISINST(pl->line, "bsra") ||
+    ISINST(pl->line, "bsrl") ||
+    ISINST(pl->line, "bsrf") ||
+    ISINST(pl->line, "brlc")))
+    return(2);
+
   if(ISINST(pl->line, ".db") || ISINST(pl->line, ".byte"))
     {
       int i, j;
@@ -1162,8 +1613,10 @@
   return(999);
 }
 
-bool z80symmParmStack (void)
+bool z80symmParmStack (const char *name)
 {
+  if (!strcmp (name, "___sdcc_enter_ix"))
+   return false;
   return z80_symmParm_in_calls_from_current_function;
 }
 
diff -Nru sdcc-4.0.0+dfsg/src/z80/peep.h sdcc-4.2.0+dfsg/src/z80/peep.h
--- sdcc-4.0.0+dfsg/src/z80/peep.h	2015-04-21 08:26:32.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/z80/peep.h	2021-02-09 21:58:36.000000000 +0000
@@ -25,6 +25,8 @@
 bool z80notUsed(const char *what, lineNode *endPl, lineNode *head);
 bool z80notUsedFrom(const char *what, const char *label, lineNode *head);
 bool z80canAssign (const char *dst, const char *src, const char *exotic);
-bool z80symmParmStack (void);
+bool z80symmParmStack (const char *name);
+bool z80canJoinRegs (const char **regs, char dst[20]);
+bool z80canSplitReg (const char *reg, char dst[][16], int nDst);
 int z80instructionSize(lineNode *node);
 
diff -Nru sdcc-4.0.0+dfsg/src/z80/peeph.def sdcc-4.2.0+dfsg/src/z80/peeph.def
--- sdcc-4.0.0+dfsg/src/z80/peeph.def	2008-07-12 11:01:54.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/z80/peeph.def	2022-01-05 19:18:52.000000000 +0000
@@ -1,7 +1,2985 @@
 // peeph.def - Common Z80 and gbz80 peephole rules
+//
+// (c) Philipp Klaus Krause (pkk@spth.de, philipp@colecovision.eu) 2006 - 2021
+// (c) Sebastian 'basxto' Riedel (sdcc@basxto.de) 2020 - 2021
+//
+// This program is free software; you can redistribute it and/or modify it
+// under the terms of the GNU General Public License as published by the
+// Free Software Foundation; either version 2, or (at your option) any
+// later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
 
-// This file should contain common Z80/GBZ80 peepholes.
-// However the GBZ80 port is currently unmaintained;
-// a GBZ80 expert could extract peepholes that are useful for both Z80 and GBZ80
-// from peeph-z80.def and peeph-gbz80.def and move them here.
+replace restart {
+	ld	%1, %1
+} by {
+	; common peephole 0 removed redundant load from %1 into %1.
+} if notVolatile(%1)
 
+replace restart {
+	ld	%1, %2
+} by {
+	; common peephole 1 removed dead load from %2 into %1.
+} if notVolatile(%1), notUsed(%1), notVolatile(%2), notSame(%1 '(hl+)' '(hl-)'), notSame(%2 '(hl+)' '(hl-)')
+
+replace restart {
+	%1	hl, %2
+} by {
+	; common peephole 2a removed %1 hl, %2 due to unused result.
+} if same(%1 'adc' 'sbc'), notUsed('hl' 'f')
+
+replace restart {
+	add	hl, %2
+} by {
+	; common peephole 2b removed add hl, %2 due to unused result.
+} if notUsed('hl' 'cf' 'nf')
+
+replace restart {
+	%1	%2
+} by {
+	; common peephole 2c removed %1 %2 due to unused result.
+} if same(%1 'dec' 'inc'), same(%2 'bc' 'de' 'hl' 'sp' 'ix' 'iy'), notUsed(%2)
+
+replace restart {
+	ld	%1, %2 + %3
+} by {
+	; common peephole 3 removed dead load from %2 + %3 into %1.
+} if notVolatile(%1), notUsed(%1), notSame(%1 '(hl+)' '(hl-)')
+// Should probably check for notVolatile(%2), too, but gives many false positives and no regression tests fail.
+
+replace restart {
+	ld	%1, (%2)
+} by {
+	ld	%1, 0 (%2)
+	; common peephole 4a made 0 offset explicit.
+} if same(%2 'ix' 'iy')
+
+replace restart {
+	ld	(%1), %2
+} by {
+	ld	0 (%1), %2
+	; common peephole 4b made 0 offset explicit.
+} if same(%1 'ix' 'iy')
+
+//remove dead INC/DEC instructions on 16-bit registers
+replace restart {
+	%1	%2
+} by {
+	; common peephole 5 removed dead %1 %2.
+} if same(%1 'inc' 'dec'), same(%2 'bc' 'de' 'hl' 'sp' 'ix' 'iy'), notUsed(%2)
+
+//remove dead INC/DEC instructions on 8-bit registers
+replace restart {
+	%1	%2
+} by {
+	; common peephole 6a removed dead %1 %2
+} if same(%1 'inc' 'dec'), same(%2 'a' 'b' 'c' 'd' 'e' 'h' 'l' 'ixh' 'ixl' 'iyh' 'iyl'), notUsed(%2 'f')
+
+//remove dead ALU instructions on 8-bit register
+replace restart {
+	%1	a, %2
+} by {
+	; common peephole 6b removed dead %1 a, %2
+} if same(%1 'sub' 'sbc' 'add' 'adc' 'and' 'or' 'xor'), notUsed('af')
+
+//remove dead CP instructions
+replace restart {
+	cp	a, %1
+} by {
+	; common peephole 6c removed dead cp a, %1
+} if notUsed('f')
+
+replace restart {
+	%1	%2
+} by {
+	; common peephole 6d removed dead %1 %2
+} if same(%1 'rlc' 'rl' 'rrc' 'rr' 'sla' 'sra' 'srl' 'sll' 'sli'), notVolatile(%2), notUsed(%2 'f')
+
+replace restart {
+	ld	%1, %2 (%3)
+} by {
+	; common peephole 7 removed dead load from %2 (%3) into %1.
+} if notUsed(%1), same(%3 'ix' 'iy')
+// Should probably check for notVolatile(), but gives many false positives and no regression tests fail.
+
+replace {
+	ex	de, hl
+	ex	de, hl
+} by {
+	; common peephole 8 removed double de/hl swap.
+}
+
+replace restart {
+	ld	%1, %2
+	ld	%3, %1
+} by {
+	; common peephole 9 loaded %3 from %2 directly instead of going through %1.
+	ld	%3, %2
+} if canAssign(%3 %2), notVolatile(%1), notUsed(%1), notSame(%3 '(hl)' '(de)' '(bc)' '(hl+)' '(hl-)'), notSame(%1 '(hl+)' '(hl-)')
+
+replace restart {
+	ld	%1, %2
+	ld	%3, %1
+} by {
+	; common peephole 9a loaded %3 from %2 directly instead of going through %1.
+	ld	%3, %2
+} if canAssign(%3 %2), notVolatile(%1), notUsed(%1), canAssign('a' %1), notSame(%1 '(hl+)' '(hl-)')
+
+replace restart {
+	ld	%1, hl
+	ld	hl, %1
+} by {
+	; common peephole 9b reused value still in hl.
+	ld	%1, hl
+} if notVolatile(%1), notSame(%1 '(hl+)' '(hl-)')
+
+replace restart {
+	ld	%1, %2
+	ld	%3, %4
+	ld	%5, %1
+} by {
+	ld	%5, %2
+	; common peephole 10 loaded %5 from %2 directly instead of going through %1.
+	ld	%3, %4
+} if canAssign(%5 %2), notVolatile(%1), operandsNotRelated(%1 %4), operandsNotRelated(%1 %3), operandsNotRelated(%3 %5), operandsNotRelated(%4 %5), notUsed(%1), notSame(%3 %4 '(hl)' '(de)' '(bc)' '(hl+)' '(hl-)'),
+   notVolatile(%5), notSame(%1 '(hl+)' '(hl-)'), notSame(%5 '(hl+)' '(hl-)')
+// Rule OK unless both %5 and %4 are volatile, but we can't express that directly.
+
+replace restart {
+	ld	%3 (ix), %1
+	ld	%4 (ix), %2
+	ld	%5, %3 (ix)
+	ld	%6, %4 (ix)
+} by {
+	ld	%3 (ix), %1
+	ld	%4 (ix), %2
+	; common peephole 11 loaded %5%6 from %1%2 directly instead of going through %3 (ix) %4 (ix).
+	ld	%5, %1
+	ld	%6, %2
+} if canAssign(%5 %1), canAssign(%6 %2), notSame(%5 %2)
+
+replace restart {
+	ld	%1, %2 (%3)
+	ld	%4, %1
+} by {
+	; common peephole 12 loaded %2 (%3) into %4 directly instead of going through %1.
+	ld	%4, %2 (%3)
+} if canAssign(%4 %2 %3), notVolatile(%1), notUsed(%1)
+
+replace restart {
+	ld	%1, %2
+	ld	%3 (%4), %1
+} by {
+	; common peephole 13 loaded %2 into %3 (%4) directly instead of going through %1.
+	ld	%3 (%4), %2
+} if canAssign(%3 %4 %2), notVolatile(%1), notUsed(%1), canAssign('a' %1)
+// canAssign ('a' %1) checks that %1 is an 8-bit value
+
+replace restart {
+	ld	%1, %2 (%3)
+	ld	%4, %5 (%6)
+	ld	%7, %1
+} by {
+	ld	%7, %2 (%3)
+	; common peephole 14 loaded %2 (%3) into %7 directly instead of going through %1.
+	ld	%4, %5 (%6)
+} if canAssign(%7 %2 %3), notVolatile(%1), notUsed(%1), notSame(%1 %4), notSame(%7 %4)
+
+replace restart {
+	ld	%1, %2 (%3)
+	ld	%4, %5
+	ld	%7, %1
+} by {
+	ld	%7, %2 (%3)
+	; common peephole 15 loaded %2 (%3) into %7 directly instead of going through %1.
+	ld	%4, %5
+} if canAssign(%7 %2 %3), notVolatile(%1), notUsed(%1), operandsNotRelated(%1 %5), operandsNotRelated(%7 %4), operandsNotRelated(%7 %5), notSame(%4 '(hl)' '(de)' '(bc)' '(hl+)' '(hl-)'), notSame(%5 '(hl)' '(de)' '(bc)' '(hl+)' '(hl-)' '(iy)')
+
+replace restart {
+	ld	%1,#%2
+	ld	a,%3 (%1)
+} by {
+	; common peephole 16 loaded %2 into a directly instead of going through %1.
+	ld	a,(#%2 + %3)
+} if notUsed(%1)
+
+replace restart {
+	ld	hl, #%1
+	ld	a, (hl)
+} by {
+	ld	a, (#%1)
+	; common peephole 17 loaded a from (#%1) directly instead of using hl.
+} if notUsed('hl')
+
+replace restart {
+	ld	hl,#%1 + %2
+	ld	a,(hl)
+} by {
+	; common peephole 18 loaded %2 into a directly instead of using hl.
+	ld	a, (#%1 + %2)
+} if notUsed('hl')
+
+replace restart {
+	ld	hl,#%1
+	ld	(hl),a
+} by {
+	ld	(#%1),a
+	; common peephole 19 loaded (#%1) from a directly instead of using hl.
+} if notUsed('hl')
+
+replace restart {
+	ld	hl,#%1 + %2
+	ld	(hl),a
+} by {
+	ld	(#%1 + %2),a
+	; common peephole 20 loaded (#%1) from a directly instead of using hl.
+} if notUsed('hl')
+
+replace restart {
+	ld	a, %1 (%2)
+	%3	a
+	ld	%1 (%2), a
+} by {
+	%3	%1 (%2)
+	ld	a, %1 (%2)
+	; common peephole 21 shifted in (%2) instead of a.
+} if same(%3 'srl' 'sla' 'rl' 'rr' 'rlc' 'rrc' 'sll')
+
+replace restart {
+	ld	%1,(hl)
+	ld	a,%2 (%3)
+	%4	a,%1
+} by {
+	ld	a,%2 (%3)
+	; common peephole 22 used (hl) in %4 directly instead of going through %1.
+	%4	a,(hl)
+} if notVolatile(%1), notUsed(%1), same(%4 'add' 'adc' 'sub' 'sbc' 'and' 'or' 'xor')
+
+replace restart {
+	ld	l, %1
+	ld	h, %2
+	ld	a, (hl)
+	inc	hl
+	ld	h, (hl)
+	ld	l, a
+} by {
+	ld	a, (%3)
+	ld	l, a
+	inc	%3
+	ld	a, (%3)
+	ld	h, a
+	; common peephole 23 optimize 16-bit load from %3.
+} if canJoinRegs(%2 %1 %3), notUsed(%3 'a')
+
+replace restart {
+	inc	%1
+	ld	l, %2
+	ld	h, %3
+} by {
+	ld	l, %2
+	ld	h, %3
+	; common peephole 24 incremented in hl instead of %1.
+	inc	hl
+} if canJoinRegs(%3 %2 %4), same(%1 %4), notUsed(%1)
+
+replace restart {
+	ld	%1, l
+	ld	%2, h
+	ld	a, #%3
+	ld	(%4), a
+} by {
+	ld	%1, l
+	ld	%2, h
+	ld	(hl), #%3
+	; common peephole 25 loaded #%1 into (hl) instead of (%4).
+} if canJoinRegs(%2 %1 %5), same(%4 %5), notUsed('a')
+
+replace restart {
+	push	de
+	ex	de, hl
+} by {
+	; common peephole 26a moved push after de/hl swap.
+	ex	de, hl
+	push	hl
+}
+
+replace restart {
+	push	hl
+	ex	de, hl
+} by {
+	; common peephole 26b moved push after de/hl swap.
+	ex	de, hl
+	push	de
+}
+
+replace restart {
+	ex	de, hl
+	push	%1
+} by {
+	; common peephole 26c moved push %1 before de/hl swap.
+	push	%1
+	ex	de, hl
+} if notSame(%1 'hl' 'de')
+
+replace restart {
+	ex	de, hl
+	push	de
+} by {
+	; common peephole 26d pushed hl directly instead of going through de.
+	push	hl
+} if notUsed('de' 'hl')
+
+replace restart {
+	ld	l,%1
+	ld	h,d
+	push	hl
+} by {
+	; common peephole 27 pushed de instead of hl removing a load.
+	ld	e,%1
+	push	de
+} if notUsed('hl' 'e')
+
+//TODO: remove if unused
+replace restart {
+	ex	de, hl
+	push	%1
+	push	de
+} by {
+	; common peephole 28 pushed hl directly instead of going through de.
+	push	%1
+	push	hl
+} if notSame(%1 'hl' 'de'), notUsed('de' 'hl')
+
+replace restart {
+	ld	%4,%1
+	ld	%5,%2
+	push	%6
+} by {
+	; common peephole 29 pushed %3 directly instead of going through %6.
+	push	%3
+} if canJoinRegs(%2 %1 %3), canJoinRegs(%5 %4 %7), same(%7 %6), notUsed(%6)
+
+replace restart {
+	ld	%2,%5
+	ld	%3,%6
+	push	%1
+	push	%4
+} by {
+	; common peephole 30 pushed %7 directly instead of going through %4.
+	push	%1
+	push	%7
+} if canJoinRegs(%3 %2 %5), same(%5 %4), canJoinRegs(%6 %5 %7), notSame(%1 %4), notUsed(%4)
+
+replace restart {
+	pop	%1
+	ld	%2, %3
+	ld	%4, %5
+} by {
+	; common peephole 31 popped %6 directly instead of going through %1.
+	pop	%6
+} if canJoinRegs(%4 %2 %6), canJoinRegs(%5 %3 %7), same(%7 %1), notUsed(%1)
+
+replace restart {
+	ex	de, hl
+	ld	e, l
+	ld	d, h
+} by {
+	; common peephole 32a removed de/hl swap.
+	ld	l, e
+	ld	h, d
+}
+
+replace restart {
+	ex	de, hl
+	ld	l, e
+	ld	h, d
+} by {
+	; common peephole 32b removed de/hl swap.
+	ld	e, l
+	ld	d, h
+}
+
+replace restart {
+	ld	%1 (%4), %2
+	ld	%3, %1 (%4)
+} by {
+	; common peephole 33 loaded %3 from %2 instead of going through %1 (%4).
+	ld	%1 (%4), %2
+	ld	%3, %2
+} if same(%4 'ix' 'iy'), canAssign(%3 %2), notSame(%3 'bc' 'de' 'hl' 'ix' 'iy')
+// Don't need to check for volatile, since ix is used for the stack.
+
+replace restart {
+	ld	%1 (%3), a
+	push	%4
+	ld	%2, %1 (%3)
+} by {
+	ld	%1 (%3), a
+	push	%4
+	; common peephole 34 loaded %2 from a instead of %1 (%3)
+	ld	%2, a
+} if same(%3 'ix' 'iy'), canAssign(%2 'a')
+
+replace restart {
+	push	af
+	inc	sp
+	ld	a,e
+	push	af
+	inc	sp
+} by {
+	; common peephole 35 pushed de instead of pushing a twice.
+	ld	d,a
+	push	de
+} if notUsed('d'), notUsed('a')
+
+replace restart {
+	pop	%1
+	pop	%2
+	push	%2
+	push	%1
+	ld	a, #%3
+	ld	(%2), a
+} by {
+	; common peephole 36 used hl instead of %2.
+	pop	%1
+	pop	hl
+	push	hl
+	push	%1
+	ld	(hl), #%3
+} if notUsed('hl' %2)
+
+replace restart {
+	push	af
+	inc	sp
+	ld	a, #%1
+	push	af
+	inc	sp
+} by {
+	; common peephole 37a pushed %4 instead of pushing a twice.
+	ld	%2, a
+	ld	%3, #%1
+	push	%4
+} if unusedReg(%4 'bc' 'de' 'hl'), canSplitReg(%4 %2 %3), notUsed('a')
+
+replace restart {
+	push	af
+	inc	sp
+	xor	a, a
+	push	af
+	inc	sp
+} by {
+	; common peephole 37b pushed %4 instead of pushing a twice.
+	ld	%2, a
+	ld	%3, #0x00
+	push	%4
+} if unusedReg(%4 'bc' 'de' 'hl'), canSplitReg(%4 %2 %3), notUsed('af')
+
+replace restart {
+	push	%1
+	inc	sp
+	push	%2
+	inc	sp
+} by {
+	ld	%4, %5
+	; common peephole 38 combined pushing of %3 and %5.
+	push	%1
+} if canSplitReg(%1 %3 %4), canSplitReg(%2 %5), notUsed(%4)
+
+replace restart {
+	ld	hl, #%1
+	add	hl, %2
+} by {
+	; common peephole 39 replaced 16-bit addition by 8-bit loads and 16-bit increment.
+	ld	l, %4
+	ld	h, %3
+	inc	hl
+} if canSplitReg(%2 %3 %4), immdInRange(1 1 '+' %1 0 %9)
+
+replace restart {
+	and	a, #%1
+	and	a, #%2
+} by {
+	; common peephole 40a combined redundant ANDs #%1 and #%2.
+	and	a, #%3
+} if operandsLiteral(%1 %2), immdInRange(0x00 0xFF '&' %1 %2 %x3)
+
+replace restart {
+	or	a, #%1
+	or	a, #%2
+} by {
+	; common peephole 40b combined redundant ORs #%1 and #%2.
+	or	a, #%3
+} if operandsLiteral(%1 %2), immdInRange(0x00 0xFF '|' %1 %2 %x3)
+
+replace restart {
+	ld	%1, %2
+	ld	%1, %3
+} by {
+	; common peephole 41a remove double load to %1.
+	ld	%1, %3
+} if notVolatile(%1), notVolatile(%2), notSame(%1 '(hl+)' '(hl-)'), notSame(%2 '(hl+)' '(hl-)'), operandsNotRelated(%1 %3)
+
+replace restart {
+	ld	%1 (%4), %2
+	ld	%1 (%4), %3
+} by {
+	; common peephole 41b remove double load to %1 (%4).
+	ld	%1 (%4), %3
+}
+
+replace restart {
+	push	af
+	inc	sp
+	ld	a, c
+	push	af
+	inc	sp
+} by {
+	ld	b, a
+	; common peephole 42 combined pushing of a and c.
+	push	bc
+} if notUsed('b'), notUsed('a')
+
+replace restart {
+	push	%1
+	inc	sp
+	ld	a, %2
+	push	af
+	inc	sp
+} by {
+	ld	%4, %2
+	; common peephole 43 combined pushing of %3 and %2.
+	push	%1
+} if notSame(%1 'iy'), canSplitReg(%1 %3 %4), canAssign(%4 %2), notUsed(%4 'a')
+
+replace restart {
+	ld	a, %1
+	push	af
+	inc	sp
+	ld	a, %2 (%3)
+	push	af
+	inc	sp
+} by {
+	ld	%4, %1
+	ld	%5, %2 (%3)
+	; common peephole 44a combined pushing of %1 and %2 (%3).
+	push	%6
+} if unusedReg(%6 'bc' 'de' 'hl'), canSplitReg(%6 %4 %5), canAssign(%4 %1), notUsed('a')
+
+replace restart {
+	ld	a, (%1)
+	push	af
+	inc	sp
+	ld	a, (%2)
+	push	af
+	inc	sp
+} by {
+	ld	a, (%1)
+	ld	%4, a
+	ld	a, (%2)
+	ld	%5, a
+	; common peephole 44b combined pushing of (%1) and (%2).
+	push	%6
+} if unusedReg(%6 'bc' 'de' 'hl'), notSame(%6 %1 %2), canSplitReg(%6 %4 %5)
+
+replace restart {
+	ld	%1, #%2
+} by {
+	; common peephole 45 replace 16-bit immediate load by 8-bit one.
+	ld	%3, #%4
+} if canSplitReg(%1 %5 %3), immdInRange(0x00 0xff '&' %2 0xff %4), canAssign(%3 %4), notUsed(%5)
+
+replace restart {
+	ld	%1, #%2
+} by {
+	; common peephole 46 replace 16-bit immediate load by 8-bit one.
+	ld	%3, #%4
+} if canSplitReg(%1 %3 %5), immdInRange(0x00 0xff '/' %2 256 %4), canAssign(%3 %4), notUsed(%5)
+
+replace restart {
+	ld	a, %1 (%3)
+	push	af
+	inc	sp
+	ld	a, %2 (%3)
+	push	af
+	inc	sp
+} by {
+	; common peephole 47a pushed %1 (%3), %2 (%3) through %6 instead of af.
+	ld	%4, %1 (%3)
+	ld	%5, %2 (%3)
+	push	%6
+} if unusedReg(%6 'bc' 'de' 'hl'), canSplitReg(%6 %4 %5), notUsed('a')
+
+replace restart {
+	ld	a, (hl)
+	push	af
+	inc	sp
+	%1	hl
+	ld	a, (hl)
+	push	af
+	inc	sp
+} by {
+	; common peephole 47b pushed (hl), %1, (hl) through %4 instead of af.
+	ld	a, (hl)
+	%1	hl
+	ld	%2, a
+	ld	a, (hl)
+	ld	%3, a
+	push	%4
+} if same(%1 'inc' 'dec'), unusedReg(%4 'bc' 'de'), canSplitReg(%4 %2 %3), notUsed('a')
+
+replace restart {
+	ld	a, (%5)
+	push	af
+	inc	sp
+	ld	a, (%6)
+	push	af
+	inc	sp
+} by {
+	; common peephole 47c pushed (%5), (%6) through %4 instead of af.
+	ld	a, (%5)
+	ld	%2, a
+	ld	a, (%6)
+	ld	%3, a
+	push	%4
+} if same(%5 'hl' 'hl+' 'hl-'), same(%6 'hl' 'hl+' 'hl-'), unusedReg(%4 'bc' 'de'), canSplitReg(%4 %2 %3)
+
+replace restart {
+	ld	%1, %4
+	ld	%2, %5
+	push	%3
+} by {
+	; common peephole 48 pushed %6 instead of %3.
+	push	%6
+} if canJoinRegs(%2 %1 %7), same(%3 %7), canJoinRegs(%5 %4 %6), notUsed(%3)
+
+replace restart {
+	ld	a, (hl)
+	%4	hl
+	ld	h, (hl)
+	ld	l, a
+	push	hl
+} by {
+	; common peephole 49 pushed %3 instead of hl.
+	ld	%1, (hl)
+	%4	hl
+	ld	%2, (hl)
+	push	%3
+} if same(%4 'inc' 'dec'), unusedReg(%3 'de' 'bc'), canSplitReg(%3 %2 %1), notUsed('hl')
+
+replace restart {
+	ld	%3, %1
+	push	%3
+} by {
+	; common peephole 49a pushed %2 instead of %3.
+	ld	%2, %1
+	push	%2
+} if same(%3 'ix' 'iy'), notUsed(%3), unusedReg(%2 'bc' 'de' 'hl'), canAssign(%2 %1)
+
+replace restart {
+	pop	%1
+	push	%1
+} by {
+	; common peephole 50a eleminated dead pop/push %1 pair.
+} if notUsed(%1)
+
+replace restart {
+	push	%1
+	pop	%1
+} by {
+	; common peephole 50b eleminated dead push/pop pair.
+}
+
+replace restart {
+	pop	%1
+	ld	%2 (ix), %3
+	push	%1
+} by {
+	; common peephole 51 eleminated dead pop/push pair.
+	ld	%2 (ix), %3
+} if notUsed(%1), operandsNotRelated(%1 %3)
+
+replace restart {
+	push	%1
+	pop	%2
+} by {
+	ld	%6, %4
+	ld	%5, %3
+	; common peephole 52 replaced push/pop pair by loads.
+} if canSplitReg(%1 %3 %4), canSplitReg(%2 %5 %6), notSame(%1 %2 'ix' 'iy'), notUsed(%1)
+
+replace restart {
+	ld	%3, #%1
+	ld	%4, %2 (%3)
+} by {
+	; common peephole 53 used direct memory loading instead of indirect.
+	ld	a, (#%1 + %2)
+	ld	%4, a
+} if notUsed(%3 'a')
+
+replace restart {
+	ld	%4, #%1
+	%3	%5, %2 (%4)
+} by {
+	; common peephole 54 used hl instead of %4.
+	ld	hl, #%1 + %2
+	%3	%5, (hl)
+} if notUsed(%4 'hl'), same(%5 'a' 'b' 'c' 'd' 'e' 'h' 'l'), same(%3 'add' 'adc' 'and' 'ld' 'or' 'sbc' 'sub' 'xor')
+
+replace restart {
+	ld	%4, #%1
+	ld	l, %3 (%4)
+} by {
+	; common peephole 55l used hl instead of %4.
+	ld	hl, #%1 + %3
+	ld	l, (hl)
+} if notUsed(%4 'h')
+
+replace restart {
+	ld	%4, #%1
+	ld	h, %3 (%4)
+} by {
+	; common peephole 55 used hl instead of %4.
+	ld	hl, #%1 + %3
+	ld	h, (hl)
+} if notUsed(%4 'l')
+
+replace restart {
+	ld	%4, #%1
+	ld	%2 (%4), %3
+} by {
+	; common peephole 56 used hl instead of %4.
+	ld	hl, #%1 + %2
+	ld	(hl), %3
+} if notUsed(%4 'hl'), notSame(%3 'h' 'l')
+
+replace restart {
+	ld	%4, #%1
+	ld	%2 (%4), %3
+} by {
+	; common peephole 57 used direct memory storing instead of indirect.
+	ld	a, %3
+	ld	(#%1 + %2), a
+} if notUsed('a' %4)
+
+replace restart {
+	ld	%4, #%1
+	ld	%2, %5 (%4)
+	ld	%3, %6 (%4)
+} by {
+	; common peephole 58 used hl instead of %4.
+	ld	hl, #%1 + %5
+	ld	%2, (hl)
+	inc	hl
+	ld	%3, (hl)
+} if operandsNotRelated(%2 'hl'), operandsNotRelated(%3 'hl'), immdInRange(-128 127 '+' %5 1 %7), same(%6 %7), notUsed(%4 'hl')
+
+replace restart {
+	ld	%4, #%1
+	ld	%2 (%4), %3
+	ld	l, %2 (%4)
+} by {
+	; common peephole 59 used hl instead of %4.
+	ld	hl, #%1 + %2
+	ld	(hl), %3
+	ld	l, (hl)
+} if notUsed(%4 'h')
+
+replace restart {
+	ld	%3, #%1
+	ld	%2 (%3), %4
+} by {
+	; common peephole 60 used hl instead of %3.
+	ld	hl, #%1 + %2
+	ld	(hl), %4
+} if notUsed(%3 'hl'), operandsNotRelated(%4 'hl')
+
+replace restart {
+	ld	%4, #%1
+	%5	%2, %3 (%4)
+} by {
+	; common peephole 61 used hl instead of %4.
+	ld	hl, #%1 + %3
+	%5	%2, (hl)
+} if same(%5 'bit' 'res' 'set'), notUsed(%4 'hl')
+
+replace restart {
+	ld	%4, #%1
+	add	%4, sp
+	ld	%2, %5 (%4)
+	ld	%3, %6 (%4)
+} by {
+	; common peephole 62 used hl instead of %4.
+	ld	hl, #%1 + %5
+	add	hl, sp
+	ld	%2, (hl)
+	inc	hl
+	ld	%3, (hl)
+} if operandsNotRelated(%2 'hl'), immdInRange(-128 127 '+' %5 1 %7), same(%7 %6), notUsed(%4 'hl')
+
+replace restart {
+	ld	%4, #%1
+	add	%4, sp
+	ld	%2, %3 (%4)
+} by {
+	; common peephole 63 used hl instead of %4.
+	ld	hl, #%1 + %3
+	add	hl, sp
+	ld	%2, (hl)
+} if notUsed(%4 'hl')
+
+replace restart {
+	ld	%4, #%1
+	add	%4, sp
+	ld	l, %2 (%4)
+	ld	h, %3 (%4)
+} by {
+	; common peephole 64 used hl instead of %4.
+	ld	hl, #%1 + %2
+	add	hl, sp
+	ld	a, (hl)
+	inc	hl
+	ld	h, (hl)
+	ld	l, a
+} if immdInRange(-128 127 '+' %2 1 %5), same(%5 %3), notUsed(%4 'a')
+
+replace restart {
+	ld	%4, #%1
+	add	%4, sp
+	ld	%5 (iy), #%2
+	ld	%6 (iy), #%3
+} by {
+	; common peephole 65 used hl instead of %4.
+	ld	hl, #%1 + %5
+	add	hl, sp
+	ld	(hl), #%2
+	inc	hl
+	ld	(hl), #%3
+} if immdInRange(-128 127 '+' %5 1 %7), same(%7 %6), notUsed(%4 'hl')
+
+replace restart {
+	ld	%4, #%1
+	add	%4, sp
+	ld	a, %2 (%4)
+	or	a, %3 (%4)
+} by {
+	ld	hl, #%1 + %2
+	add	hl, sp
+	ld	a, (hl)
+	inc	hl
+	or	a, (hl)
+	; common peephole 66a used hl instead of %4.
+} if immdInRange(-128 127 '+' %2 1 %5), same(%5 %3), notUsed(%4 'hl')
+
+replace restart {
+	ld	%4, #%1
+	add	%4, sp
+	ld	a, %2 (%4)
+	or	a, %3 (%4)
+} by {
+	ld	hl, #%1 + %3
+	add	hl, sp
+	ld	a, (hl)
+	inc	hl
+	or	a, (hl)
+	; common peephole 66b used hl instead of %4.
+} if immdInRange(-128 127 '-' %2 1 %5), same(%5 %3), notUsed(%4 'hl')
+
+replace restart {
+	ld	%4, #%1
+	add	%4, sp
+	%5	%2, %3 (%4)
+} by {
+	ld	hl, #%1 + %3
+	add	hl, sp
+	%5	%2, (hl)
+	; common peephole 67 used hl instead of %4.
+} if same(%5 'bit' 'res' 'set'), notUsed(%4 'hl')
+
+replace restart {
+	ld	%4, #%1
+	add	%4, sp
+	%5	%3, %2 (%4)
+} by {
+	ld	hl, #%1 + %2
+	add	hl, sp
+	%5	%3, (hl)
+	; common peephole 68 used hl instead of %4.
+} if same(%5 'adc' 'add' 'and' 'ld' 'or' 'sbc' 'sub' 'xor'), notUsed(%4 'hl')
+
+// can be further optimized to (hl+) on gbz80
+replace restart {
+	ld	%1, l
+	ld	%2, h
+	inc	%3
+} by {
+	; common peephole 69 incremented in hl instead of %3.
+	inc	hl
+	ld	%1, l
+	ld	%2, h
+} if canJoinRegs(%2 %1 %4), same(%4 %3), notUsed('hl')
+
+replace restart {
+	ld	%4, #%1
+	%3	%2 (%4)
+} by {
+	; common peephole 70 %3 (hl) instead of %2 (%4).
+	ld	hl, #%1 + %2
+	%3	(hl)
+} if same(%3 'inc' 'dec'), notUsed(%4 'hl')
+
+replace restart {
+	ld	%1, %2
+	push	%3
+	inc	sp
+} by {
+	; common peephole 71 eliminate unnecessary initialization of %1 register.
+	push	%3
+	inc	sp
+} if same(%1 'c' 'e' 'l' 'ixl' 'iyl'), canJoinRegs('' %1 %4), same(%3 %4), notUsed(%1)
+
+replace restart {
+	ld	a, %1 (%2)
+	bit	%3, a
+} by {
+	; common peephole 72 tested bit %3 of %1 (%2) directly instead of going through a.
+	bit	%3, %1 (%2)
+} if notUsed('a')
+
+replace restart {
+	ld	%1, (hl)
+	bit	%2, %1
+} by {
+	; common peephole 73 tested bit %2 of (hl) directly instead of going through %1.
+	bit	%2, (hl)
+} if notUsed(%1)
+
+replace restart {
+	ld	a, %1
+	bit	%2, a
+} by {
+	; common peephole 74 tested bit %2 of %1 directly instead of going through a.
+	bit	%2, %1
+} if notUsed('a'), canAssign(%1 'b')
+
+replace restart {
+	ld	a, %1
+	%3	%2, a
+	ld	%1, a
+} by {
+	; common peephole 75 %3 bit %2 of %1 directly instead of going through a.
+	%3	%2, %1
+	ld	a, %1
+} if same(%3 'set' 'res'), canAssign(%1 'b'), notSame(%1 '(hl+)' '(hl-)')
+// canAssign(%1 'b') is true, iff set b, %1 is possible.
+
+replace restart {
+	ld	a, %1 (%2)
+	%4	%3, a
+	ld	%1 (%2), a
+} by {
+	; common peephole 76 %4 bit %3 of %1 (%2) directly instead of going through a.
+	%4	%3, %1 (%2)
+	ld	a, %1 (%2)
+} if same(%4 'set' 'res')
+
+replace restart {
+	ld	%1, #%2 + %3
+	inc	%1
+} by {
+	ld	%1, #%2 + %4
+	; common peephole 77a incremented immediate.
+} if operandsLiteral(%3), immdInRange(0 256 '+' %3 1 %4), notUsed('f')
+
+replace restart {
+	ld	%1, #%2 - %3
+	inc	%1
+} by {
+	ld	%1, #%2 - %4
+	; common peephole 77b incremented immediate.
+} if operandsLiteral(%3), immdInRange(0 256 '-' %3 1 %4), notUsed('f')
+
+replace restart {
+	ld	%1, #%2 + %3
+	dec	%1
+} by {
+	ld	%1, #%2 + %4
+	; common peephole 77c decremented immediate.
+} if operandsLiteral(%3), immdInRange(0 256 '-' %3 1 %4), notUsed('f')
+
+replace restart {
+	ld	%1, #%2 - %3
+	dec	%1
+} by {
+	ld	%1, #%2 - %4
+	; common peephole 77d decremented immediate.
+} if operandsLiteral(%3), immdInRange(0 256 '+' %3 1 %4), notUsed('f')
+
+replace {
+	ld	%1, #%2 - 0
+} by {
+	ld	%1, #%2 + 0
+	; common peephole 77e changed -0 to +0.
+}
+
+replace {
+	ld	%1, #%2 + 0
+	dec	%1
+} by {
+	ld	%1, #%2 - 1
+	; common peephole 77f decremented immediate.
+} if notUsed('f')
+
+// should improve flag based optimizations
+replace restart {
+	jp	%1,%2
+	jp	%2
+} by {
+	; common peephole 78 removed redundant jp
+	jp	%2
+} if labelRefCountChange(%2 -1)
+
+replace restart {
+	jp	NC,%1
+	jp	%2
+%1:
+} by {
+	jp	C,%2
+	; common peephole 79 removed jp by using inverse jump logic
+%1:
+} if labelRefCountChange(%1 -1)
+
+replace restart {
+	jp	C,%1
+	jp	%2
+%1:
+} by {
+	jp	NC,%2
+	; common peephole 80 removed jp by using inverse jump logic
+%1:
+} if labelRefCountChange(%1 -1)
+
+replace restart {
+	jp	NZ,%1
+	jp	%2
+%1:
+} by {
+	jp	Z,%2
+	; common peephole 81 removed jp by using inverse jump logic
+%1:
+} if labelRefCountChange(%1 -1)
+
+replace restart {
+	jp	Z,%1
+	jp	%2
+%1:
+} by {
+	jp	NZ,%2
+	; common peephole 82 removed jp by using inverse jump logic
+%1:
+} if labelRefCountChange(%1 -1)
+
+replace restart {
+	jp	%5
+} by {
+	jp	%6
+	; common peephole 83 jumped to %6 directly instead of via %5.
+} if labelIsUncondJump(), notSame(%5 %6), labelRefCountChange(%5 -1), labelRefCountChange(%6 +1)
+
+replace restart {
+	jp	%1,%5
+} by {
+	jp	%1,%6
+	; common peephole 84 jumped to %6 directly instead of via %5.
+} if labelIsUncondJump(), notSame(%5 %6), labelRefCountChange(%5 -1), labelRefCountChange(%6 +1)
+
+replace restart {
+	jp	%1
+%2:
+%1:
+} by {
+   ; common peephole 85 eliminated jump.
+%2:
+%1:
+} if labelRefCountChange(%1 -1)
+
+// A peephole that makes the code longer. Let's hope it's worth it in speed gain and further optimization potential.
+replace restart {
+	ld	a,#0x00
+%1:
+	bit	%2,a
+	jp	Z,%3
+} by {
+	ld	a,#0x00
+	jp	%3
+	; common peephole 86 jumped directly to %3 instead of testing a first.
+%1:
+	bit	%2,a
+	jp	Z,%3
+} if labelRefCountChange(%3 +1)
+
+replace restart {
+	ld	%1, %2
+	jp	%3
+	jp	%4
+} by {
+	ld	%1, %2
+	jp	%3
+	; common peephole 87a removed unreachable jump to %4
+} if labelRefCountChange(%4 -1)
+
+replace restart {
+	jp	%1
+%2:
+	jp	%3
+} by {
+	; common peephole 87b removed unreachable jump to %3
+	jp	%1
+} if labelRefCount(%2 0), labelRefCountChange(%3 -1)
+
+replace restart {
+	ld	%1, %2
+	jp	%3
+%3:
+} by {
+	ld	%1, %2
+%3:
+	; common peephole 88 removed redundant jump to %3.
+} if labelRefCountChange(%3 -1)
+
+replace restart {
+	ld	%1, #0x01
+	bit	0, %1
+	jp	Z, %2
+} by {
+	ld	%1, #0x01
+	; common peephole 89 removed impossible jump to %2.
+} if labelRefCountChange(%2 -1)
+
+replace restart {
+	rlca
+	and	a, #0x01
+	jp	Z, %1
+} by {
+	rlca
+	; common peephole 90 removed and by changing jump condition.
+	jp	NC, %1
+} if notUsed('a'), notUsedFrom(%1 'a')
+
+replace restart {
+	rlca
+	and	a, #0x01
+	jp	NZ, %1
+} by {
+	; common peephole 91 removed and by changing jump condition.
+	rlca
+	jp	C, %1
+} if notUsed('a'), notUsedFrom(%1 'a')
+
+replace {
+	ld	%5, #%1
+	ld	%6, #%2
+} by {
+	; common peephole 92a combined constant loads into register pair.
+	ld	%7, #%4
+} if canJoinRegs(%6 %5 %7), operandsLiteral(%1 %2), immdInRange(0x00 0xffff '*' %2 0x100 %3), immdInRange(0x00 0xffff '|' %3 %1 %x4)
+
+replace {
+	xor	a, a
+	ld	%5, a
+	ld	%6, #%2
+} by {
+	; common peephole 92b combined constant loads into register pair.
+	ld	%7, #%4
+} if canJoinRegs(%6 %5 %7), operandsLiteral(%2), immdInRange(0x00 0xffff '*' %2 0x100 %x4), notUsed('a' 'cf' 'zf')
+
+replace {
+	xor	a, a
+	ld	%5, #%1
+	ld	%6, a
+} by {
+	; common peephole 92c combined constant loads into register pair.
+	ld	%7, #%1
+} if canJoinRegs(%6 %5 %7), operandsLiteral(%1), notUsed('a' 'cf' 'zf')
+
+replace {
+	ld	%5, #%1
+	ld	%6, #%2
+} by {
+	; common peephole 93a combined constant loads into register pair.
+	ld	%7, #%4
+} if canJoinRegs(%5 %6 %7), operandsLiteral(%1 %2), immdInRange(0x00 0xffff '*' %1 0x100 %3), immdInRange(0x00 0xffff '|' %3 %2 %x4)
+
+replace {
+	xor	a, a
+	ld	%5, a
+	ld	%6, #%2
+} by {
+	; common peephole 93b combined constant loads into register pair.
+	ld	%7, #%2
+} if canJoinRegs(%5 %6 %7), operandsLiteral(%2), notUsed('a' 'cf' 'zf')
+
+replace {
+	xor	a, a
+	ld	%5, #%1
+	ld	%6, a
+} by {
+	; common peephole 93c combined constant loads into register pair.
+	ld	%7, #%4
+} if canJoinRegs(%5 %6 %7), operandsLiteral(%1), immdInRange(0x00 0xffff '*' %1 0x100 %x4), notUsed('a' 'cf' 'zf')
+
+replace {
+	ld	%8, #%1
+	ld	%5, %8
+	ld	%6, #%2
+} by {
+	ld	%8, #%1
+	ld	%7, #%4
+	; common peephole 93d combined constant loads into register pair.
+} if canJoinRegs(%5 %6 %7), operandsLiteral(%1 %2), immdInRange(0x00 0xffff '*' %1 0x100 %3), immdInRange(0x00 0xffff '|' %3 %2 %x4)
+
+replace {
+	ld	%1, #%2
+	xor	a, a
+} by {
+	; common peephole 94a reused constant #0 loaded into register.
+	xor	a, a
+	ld	%1, a
+} if same(%1 'a' 'b' 'c' 'd' 'e' 'h' 'l'), operandsLiteral(%2), immdInRange(0 0 '+' %2 0 %3)
+
+replace {
+	xor	a, a
+	ld	(%1), a
+	ld	(hl), #%2
+} by {
+	; common peephole 94b reused constant #0 loaded into register.
+	xor	a, a
+	ld	(%1), a
+	ld	(hl), a
+} if same(%1 'hl' 'hl+' 'hl-'), operandsLiteral(%2), immdInRange(0 0 '+' %2 0 %3)
+
+replace {
+	xor	a, a
+	ld	(hl), a
+	%1	hl
+	ld	(hl), #%2
+} by {
+	; common peephole 94c reused constant #0 loaded into register.
+	xor	a, a
+	ld	(hl), a
+	%1	hl
+	ld	(hl), a
+} if same(%1 'inc' 'dec'), operandsLiteral(%2), immdInRange(0 0 '+' %2 0 %3)
+
+replace {
+	ld	%1, %2
+	push	%1
+	ld	%1, %2
+} by {
+	ld	%1, %2
+	push	%1
+	; common peephole 94d pushed register pair twice.
+}
+
+// optimizes genRet
+replace restart {
+	ld	(%1), %2
+	inc	%1
+	ld	(%1), %3
+	dec	%1
+	ld	%4, (%1)
+	inc	%1
+	ld	%5, (%1)
+} by {
+	; common peephole 95a switched loads to %4 and %5.
+	ld	(%1), %2
+	inc	%1
+	ld	(%1), %3
+	ld	%5, (%1)
+	dec	%1
+	ld	%4, (%1)
+	inc	%1
+} if operandsNotRelated(%4 %5 %1), operandsNotRelated(%5 %1)
+
+replace restart {
+	ld	(%1), %2
+	dec	%1
+	ld	%4, (%1)
+	inc	%1
+	ld	%5, (%1)
+} by {
+	; common peephole 95b switched loads to %4 and %5.
+	ld	(%1), %2
+	ld	%5, (%1)
+	dec	%1
+	ld	%4, (%1)
+	inc	%1
+} if operandsNotRelated(%4 %5 %1), operandsNotRelated(%5 %1)
+
+// improves genRet after (hl) access
+replace restart {
+	%2	(%1)
+	dec	%1
+	ld	%4, (%1)
+	inc	%1
+	ld	%5, (%1)
+} by {
+	; common peephole 95c switched loads to %4 and %5.
+	%2	(%1)
+	ld	%5, (%1)
+	dec	%1
+	ld	%4, (%1)
+	inc	%1
+}if operandsNotRelated(%4 %5 %1), operandsNotRelated(%5 %1)
+
+replace restart {
+	%1
+	%2	%3
+} by {
+	; common peephole 96a move %2 %3 before %1
+	%2	%3
+	%1
+} if same(%2 'inc' 'dec'), same(%3 'hl'), same(%1 'rlca' 'rrca' 'rra' 'rla' 'cpl' 'scf' 'daa' 'ccf' 'sra' 'swap' 'nop')
+
+replace restart {
+	%4	%1, %2
+	%3	%5
+} by {
+	; common peephole 96b move %3 %5 before %4 %1, %2
+	%3	%5
+	%4	%1, %2
+} if same(%3 'inc' 'dec'), same(%5 'hl'), same(%4 'ld' 'ldh' 'cp' 'add' 'adc' 'and' 'or' 'xor' 'sub' 'sbc' 'set' 'res' 'bit' 'in' 'out' 'in0' 'out0'), operandsNotRelated(%1 %5), operandsNotRelated(%2 %5)
+
+replace restart {
+	%2	%1
+	%3	%4
+} by {
+	; common peephole 96c move %3 %4 before %2 %1
+	%3	%4
+	%2	%1
+} if same(%3 'inc' 'dec'), same(%4 'hl'), same(%2 'inc' 'dec' 'rl' 'rlc' 'rr' 'rrc' 'srl' 'sla' 'sra' 'swap'), operandsNotRelated(%1 %4), operandsNotRelated(%2 %4)
+
+replace restart {
+	%2	%1
+	%3	%4
+} by {
+	; common peephole 96d move %3 %4 before %2 (%1)
+	%3	%4
+	%2	%1
+} if same(%3 'inc' 'dec'), same(%4 'hl'), same(%2 'push' 'pop'), notSame(%1 %4)
+
+// check if constant loaded into (hl) is the same that's loaded into the second register
+replace {
+	ld	(hl), #%2
+	ld	%1, #%3
+} by {
+	; common peephole 97a reused constant loaded into register pair. %2 %3
+	ld	%1, #%3
+	ld	(hl), %5
+} if same(%1 'bc' 'de'), operandsLiteral(%2 %3), canSplitReg(%1 %4 %5), immdInRange(0x00 0xff '&' %3 0xff %7), immdInRange(0 0 '-' %7 %2 %8)
+// ., ., ., ., get second byte, compare second byte with %2
+
+// check if constant loaded into (hl) is the same that's loaded into the first register
+replace {
+	ld	(hl), #%2
+	ld	%1, #%3
+} by {
+	; common peephole 97b reused constant loaded into register pair.
+	ld	%1, #%3
+	ld	(hl), %4
+} if same(%1 'bc' 'de'), operandsLiteral(%2 %3), canSplitReg(%1 %4 %5), immdInRange(0x00 0xff '/' %3 0xff %6), immdInRange(0x00 0xff '&' %6 0xff %7), immdInRange(0 0 '-' %7 %2 %8)
+// ., ., ., ., bit shift, get second byte, compare second byte with %2
+
+replace restart {
+	ld	%1, a
+	ld	a, %1
+} by {
+	ld	%1, a
+	; common peephole 98 removed redundant load from %1 into a.
+} if notVolatile(%1), notSame(%1 '(hl+)' '(hl-)')
+// This gives many false negatives and without the test no problems are encountered in the regression tests
+// Maybe we can try this after 2.7.0 release
+
+replace restart {
+	ld	%2 (ix), %1
+	ld	%1, %2 (ix)
+} by {
+	ld	%2 (ix), %1
+	; common peephole 98a removed redundant load of %1 from %2 (ix)
+}
+
+replace restart {
+	ld	%1,a
+	ld	a,%2
+	or	a,%1
+} by {
+	ld	%1,a
+	or	a,%2
+	; common peephole 99 removed load by reordering or arguments.
+} if notVolatile(%1), canAssign('b' %2), notSame(%1 '(hl+)' '(hl-)')
+// canAssign('b' %2) is true, iff or a,%2 is possible.
+
+replace restart {
+	ld	%1, (hl)
+	inc	hl
+	ld	a, (hl)
+	or	a, %1
+} by {
+	ld	a, (hl)
+	inc	hl
+	; common peephole 99a removed load by reordering or arguments.
+	or	a, (hl)
+} if notUsed(%1)
+
+replace restart {
+	and	a,%1
+	or	a,a
+} by {
+	and	a,%1
+	; common peephole 100 removed redundant or after and.
+}
+
+replace restart {
+	%2	%1
+	ld	a, %1
+	or	a, a
+} by {
+	%2	%1
+	ld	a, %1
+	; common peephole 100b removed redundant or after %2
+
+} if same(%2 'inc' 'dec'), notUsed('cf' 'hf' 'nf' 'sf' 'pf')
+
+replace restart {
+	xor	a,%1
+	or	a,a
+} by {
+	xor	a,%1
+	; common peephole 101 removed redundant or after xor.
+}
+
+replace restart {
+	xor	a,%1 (%2)
+	or	a,a
+} by {
+	xor	a,%1 (%2)
+	; common peephole 102 removed redundant or after xor.
+}
+
+replace restart {
+	dec	a
+	or	a, a
+} by {
+	; common peephole 102a removed redundant or after dec.
+	dec	a
+} if notUsed('cf')
+
+replace restart {
+	dec	%1
+	ld	a, %1
+	or	a, a
+} by {
+	; common peephole 102b removed redundant or after dec.
+	dec	%1
+	ld	a, %1
+} if notUsed('cf')
+
+replace restart {
+	sbc	hl, %1
+	ld	a, h
+	or	a, l
+	jp	NZ, %2
+} by {
+	sbc	hl, %1
+	jp	NZ, %2
+	; common peephole 102c removed redundant or after sbc.
+}
+
+replace restart {
+	sbc	hl, %1
+	ld	a, h
+	or	a, l
+	jp	Z, %2
+} by {
+	sbc	hl, %1
+	jp	Z, %2
+	; common peephole 102d removed redundant or after sbc.
+}
+
+replace {
+	ld	%1,%2
+	ld	a,%2
+} by {
+	ld	a,%2
+	ld	%1,a
+	; common peephole 103 loaded value in a first and used it next
+} if notVolatile(%1 %2), canAssign(%1 'a'), operandsNotRelated(%1 %2), notSame(%1 '(hl+)' '(hl-)'), notSame(%2 '(hl+)' '(hl-)')
+
+replace restart {
+	ld	%2, #%1
+	ld	%3, #%1
+} by {
+	; common peephole 103b loaded constant in %2 first and used it next
+	ld	%2, #%1
+	ld	%3, %2
+} if notVolatile(%2), canAssign(%3 %2)
+
+replace restart {
+	ld	%1,%2
+	ld	%3,%4
+	ld	%2,%1
+	ld	%4,%3
+} by {
+	ld	%1,%2
+	ld	%3,%4
+	; common peephole 104 removed redundant load from %3%1 into %4%2
+} if notVolatile(%1 %2 %3 %4), notSame(%1 '(hl+)' '(hl-)'), notSame(%2 '(hl+)' '(hl-)'), notSame(%3 '(hl+)' '(hl-)'), notSame(%4 '(hl+)' '(hl-)')
+
+replace restart {
+	ld	%2, %1
+	%3	%2
+	ld	%1, %2
+} by {
+	%3	%1
+	ld	%2, %1
+	; common peephole 104b %3 %1 directly to remove redundant load from %2 into %1
+} if same(%1 'a' 'b' 'c' 'd' 'e' 'h' 'l' '(hl)'), same(%3 'inc' 'dec')
+
+replace restart {
+	push	de
+	inc	sp
+	ld	a,e
+	push	af
+	inc	sp
+} by {
+	push	de
+	; common peephole 105 pushed de
+} if notUsed('a')
+
+replace restart {
+	ld	iy,%1
+	add	iy,sp
+	ld	sp,iy
+} by {
+	ld	hl,%1
+	add	hl,sp
+	ld	sp,hl
+	; common peephole 106 fixed stack using hl instead of iy.
+} if notUsed('hl'), notUsed('iy')
+
+replace restart {
+	ld	a,%1
+	sub	a,%2
+	jp	%3,%4
+	ld	a,%1
+} by {
+	ld	a,%1
+	cp	a,%2
+	jp	%3,%4
+	; common peephole 107 removed load from %1 into a by replacing sub with cp
+	assert	a=%1
+} if notVolatile(%1), notUsedFrom(%4 'a'), notSame(%1 '(hl+)' '(hl-)')
+
+replace restart {
+	assert	a=%1
+	sub	a,%2
+	jp	%3,%4
+	ld	a,%1
+} by {
+	cp	a,%2
+	jp	%3,%4
+	; common peephole 108 removed load from %1 into a by replacing sub with cp
+	assert	a=%1
+} if notUsedFrom(%4 'a')
+
+replace restart {
+	assert	a=%1
+} by {
+}
+
+replace restart {
+	rlca
+	ld	a,#0x00
+	rla
+} by {
+	rlca
+	and	a,#0x01
+	; common peephole 109 replaced zero load, rla by and since rlca writes the same value to carry bit and least significant bit.
+}
+
+replace restart {
+	ld	%1,%2
+	push	%1
+	pop	%4
+	ld	%1,%3
+} by {
+	ld	%4,%2
+	; common peephole 110 moved %2 directly into de instead of going through %1.
+	ld	%1,%3
+}
+
+replace restart {
+	add	a,#0x00
+	ld	%2,a
+	ld	a,%3
+	adc	a,%4
+} by {
+	; common peephole 111 removed lower part of multibyte addition.
+	ld	%2,a
+	ld	a,%3
+	add	a,%4
+}
+
+replace restart {
+	ld	a, l
+	add	a, #%1
+	ld	e, a
+	ld	a, h
+	adc	a, #%2
+	ld	d, a
+} by {
+	ld	de, #%4
+	add	hl, de
+	; common peephole 112 used 16-bit addition.
+	ld	e, l
+	ld	d, h
+	ld	a, h
+} if operandsLiteral(%1 %2), immdInRange(0x00 0xffff '*' %2 0x100 %3), immdInRange(0x00 0xffff '|' %3 %1 %x4), notUsed('hl')
+
+replace restart {
+	ld	a, l
+	add	a, #%1
+	ld	c, a
+	ld	a, h
+	adc	a, #%2
+	ld	b, a
+} by {
+	ld	bc, #%4
+	add	hl,bc
+	; common peephole 113 used 16-bit addition.
+	ld	c, l
+	ld	b, h
+	ld	a, h
+} if operandsLiteral(%1 %2), immdInRange(0x00 0xffff '*' %2 0x100 %3), immdInRange(0x00 0xffff '|' %3 %1 %x4), notUsed('hl')
+
+replace restart {
+	ld	l,%1 (ix)
+	ld	h,%2 (ix)
+	ld	a,(hl)
+	inc	a
+	ld	l,%1 (ix)
+	ld	h,%2 (ix)
+	ld	(hl),a
+} by {
+	ld	l,%1 (ix)
+	ld	h,%2 (ix)
+	inc	(hl)
+	; common peephole 114 incremented in (hl) instead of going through a.
+} if notUsed('a')
+
+replace restart {
+	ld	a,(hl)
+	inc	a
+	ld	(hl),a
+} by {
+	inc	(hl)
+	; common peephole 115 incremented in (hl) instead of going through a.
+} if notUsed('a')
+
+// TODO: Check for volatile?
+replace restart {
+	ld	%1, %2 (%3)
+	inc	%1
+	ld	%2 (%3), %1
+} by {
+	inc	%2 (%3)
+	ld	%1, %2 (%3)
+	; common peephole 116 incremented in %2 (%3) instead of going through %1.
+} if canAssign('a' %1)
+
+// TODO: Check for volatile?
+replace restart {
+	ld	%1, %2 (%3)
+	dec	%1
+	ld	%2 (%3), %1
+} by {
+	dec	%2 (%3)
+	ld	%1, %2 (%3)
+	; common peephole 117 decremented in %2 (%3) instead of going through %1.
+} if canAssign('a' %1)
+
+replace restart {
+	ld	%1,a
+	ld	a,%2
+	add	a,%1
+} by {
+	ld	%1, a
+	; common peephole 118 removed load by exploiting commutativity of addition.
+	add	a,%2
+} if notSame(%2 '(bc)' '(de)'), canAssign('b' %2)
+// canAssign('b' %2) is true, iff add a,%2 is possible.
+
+replace restart {
+	ld	c,l
+	ld	b,h
+	ld	hl,#%1
+	add	hl,bc
+} by {
+	; common peephole 119 removed loads by exploiting commutativity of addition.
+	ld	bc,#%1
+	add	hl,bc
+} if notUsed('bc')
+
+replace restart {
+	ld	hl,#%1
+	add	hl,%2
+	ld	bc,#%4
+	add	hl,bc
+} by {
+	; common peephole 120 removed loads by exploiting commutativity of addition.
+	ld	hl,#%1 + %4
+	add	hl,%2
+} if notUsed('bc')
+
+replace restart {
+	or	a,%1
+	jp	NZ,%2
+	ld	%3,#0x00
+} by {
+	or	a,%1
+	jp	NZ,%2
+	ld	%3,a
+	; common peephole 121a replaced constant #0x00 by a (which has just been tested to be #0x00).
+}
+
+replace restart {
+	and	a,%1
+	jp	NZ,%2
+	ld	%3,#0x00
+} by {
+	and	a,%1
+	jp	NZ,%2
+	ld	%3,a
+	; common peephole 121b replaced constant #0x00 by a (which has just been tested to be #0x00).
+}
+
+replace {
+	ld	a, #%1
+	sbc	a, %3
+} by {
+	; common peephole 122a optimized carry substraction by 0.
+	sbc	a, a
+	sub	a, %3
+} if operandsLiteral(%1), immdInRange(0 0 '+' %1 0 %2), notVolatile(%3), notUsed('f')
+
+replace {
+	ld	a, #%1
+	sub	a, %3
+} by {
+	; common peephole 122b optimized carry substraction by 0.
+	xor	a, a
+	sub	a, %3
+} if operandsLiteral(%1), immdInRange(0 0 '+' %1 0 %2), notVolatile(%3), notUsed('f')
+
+replace {
+	ld	a, #%1
+	sbc	a, %2 (ix)
+} by {
+	; common peephole 122c optimized carry substraction by 0.
+	sbc	a, a
+	sub	a, %2 (ix)
+} if operandsLiteral(%1), immdInRange(0 0 '+' %1 0 %3), notUsed('f')
+
+replace {
+	ld	a, #%1
+	sbc	a, %2
+} by {
+	; common peephole 122d optimized carry substraction by 0.
+	sbc	a, a
+	sub	a, %2
+} if operandsLiteral(%1), immdInRange(0 0 '+' %1 0 %3), notUsed('f')
+
+replace restart {
+	ld	a, #%1
+} by {
+	; common peephole 123 optimize ld a, %1
+	xor	a, a
+} if operandsLiteral(%1), immdInRange(0 0 '+' %1 0 %2), notUsed('f')
+
+replace restart {
+	sub	a,%1
+	jp	NZ,%2
+	ld	%3,#0x00
+} by {
+	sub	a,%1
+	jp	NZ,%2
+	ld	%3,a
+	; common peephole 124 replaced constant #0x00 by a (which has just been tested to be #0x00).
+}
+
+replace restart {
+	inc	a
+	jp	NZ,%1
+	ld	%2,#0x00
+} by {
+	inc	a
+	jp	NZ,%1
+	ld	%2,a
+	; common peephole 125a replaced constant #0x00 by a (which has just been tested to be #0x00).
+}
+
+replace restart {
+	dec	a
+	jp	NZ,%1
+	ld	%2,#0x00
+} by {
+	dec	a
+	jp	NZ,%1
+	ld	%2,a
+	; common peephole 125b replaced constant #0x00 by a (which has just been tested to be #0x00).
+}
+
+replace restart {
+	or	a,%1
+	jp	NZ,%2
+	ld	a,%3
+	or	a,a
+} by {
+	or	a,%1
+	jp	NZ,%2
+	or	a,%3
+	; common peephole 126 shortened or using a (which has just been tested to be #0x00).
+} if canAssign('b' %3)
+// canAssign('b' %2) is true, iff or a,%2 is possible.
+
+replace restart {
+	sub	a,%1
+	jp	NZ,%2
+	ld	a,%3
+	or	a,a
+} by {
+	sub	a,%1
+	jp	NZ,%2
+	or	a,%3
+	; common peephole 127 shortened or using a (which has just been tested to be #0x00).
+} if canAssign('b' %3)
+// canAssign('b' %2) is true, iff or a,%2 is possible.
+
+replace restart {
+	ld	hl,#%1
+	add	hl,%2
+	inc	hl
+} by {
+	ld	hl,#%3
+	add	hl,%2
+	; common peephole 129a moved increment of hl to constant.
+} if operandsLiteral(%1), immdInRange(0 0xFFFF '+' %1 1 %x3)
+
+// breaks 130 otherwise
+replace restart {
+	ld	hl,#%1
+	add	hl,%2
+	dec hl
+} by {
+	ld	hl,#%3
+	add	hl,%2
+	; common peephole 129b moved decrement of hl to constant.
+} if operandsLiteral(%1), immdInRange(0 0xFFFF '-' %1 1 %x3)
+
+replace restart {
+	ld	hl,#%1
+	add	hl,%2
+	inc	hl
+} by {
+	ld	hl,#%1 + 1
+	add	hl,%2
+	; common peephole 129c moved increment of hl to constant.
+}
+
+replace restart {
+	ld	hl,#%1
+	add	hl,%2
+	dec hl
+} by {
+	ld	hl,#%1 - 1
+	add	hl,%2
+	; common peephole 129d moved decrement of hl to constant.
+}
+
+replace {
+	ld	%1, #%2 + 0
+} by {
+	; common peephole 130a removed unnecessary +0 from constant
+	ld	%1, #%2
+}
+
+//TODO: %2 matches 4+1+1
+replace {
+	ld	%1, #%2 + %3
+} by {
+	; common peephole 130b added +%3 to immediate %2
+	ld	%1, #%4
+} if operandsLiteral(%2 %3), immdInRange(0 0xFF '+' %2 %3 %x4)
+
+replace {
+	ld	%1, #%2 + %3
+} by {
+	; common peephole 130c added +%3 to immediate %2
+	ld	%1, #%4
+} if operandsLiteral(%2 %3), immdInRange(0 0xFFFF '+' %2 %3 %x4), canSplitReg(%1 %0 %0)
+
+replace {
+	ld	%1, #%2 - 0
+} by {
+	; common peephole 130d removed unnecessary -0 from constant
+	ld	%1, #%2
+}
+
+replace {
+	ld	%1, #%2 - %3
+} by {
+	; common peephole 130e substracted -%3 from immediate %2
+	ld	%1, #%4
+} if operandsLiteral(%2 %3), immdInRange(0 0xFF '-' %2 %3 %x4)
+
+replace {
+	ld	%1, #%2 - %3
+} by {
+	; common peephole 130f substracted -%3 from to immediate %2
+	ld	%1, #%4
+} if operandsLiteral(%2 %3), immdInRange(0 0xFFFF '-' %2 %3 %x4), canSplitReg(%1 %0 %0)
+
+
+// Bug #3102
+//replace {
+//	ld	%1, (#%2 + 0)
+//} by {
+//	; common peephole 130g removed unnecessary +0 to immediate
+//	ld	%1, (#%2)
+//}
+
+replace {
+	ld	(#%2 + 0), %1
+} by {
+	; common peephole 130h removed unnecessary +0 to immediate
+	ld	(#%2), %1
+}
+
+replace restart {
+	push	hl
+	pop	iy
+	pop	hl
+	inc	iy
+} by {
+	inc	hl
+	push	hl
+	pop	iy
+	pop	hl
+	; common peephole 131a incremented in hl instead of iy.
+}
+
+replace restart {
+	push	bc
+	pop	iy
+	inc	iy
+} by {
+	inc	bc
+	push	bc
+	pop	iy
+	; common peephole 131b incremented in bc instead of iy.
+} if notUsed('bc')
+
+replace restart {
+	ld	hl,%1
+	add	hl,%2
+	push	hl
+	pop	iy
+} by {
+	ld	iy,%1
+	add	iy,%2
+	; common peephole 132 added in iy instead of hl.
+} if notUsed('hl'), notSame(%2 'hl')
+
+replace restart {
+	pop	af
+	ld	sp,%1
+} by {
+	; common peephole 133 removed redundant pop af.
+	ld	sp,%1
+} if notUsed('a')
+
+replace restart {
+	inc	sp
+	ld	sp,%1
+} by {
+	; common peephole 134 removed redundant inc sp.
+	ld	sp,%1
+}
+
+replace restart {
+	call    %1
+	ret
+} by {
+	jp  %1
+	; common peephole 135 replaced call at end of function by jump (tail call optimization).
+} if symmParmStack(%1)
+
+// Callee saves ix.
+replace restart {
+	call	%1
+	pop	ix
+	ret
+} by {
+	pop	ix
+	jp	%1
+	; common peephole 136 replaced call at end of function by jump moving call beyond pop ix (tail call optimization).
+} if symmParmStack(%1)
+
+replace restart {
+	ld	%1,#%2
+	ld	%3,%4
+	ld	%1,#%2
+} by {
+	ld	%1,#%2
+	ld	%3,%4
+	; common peephole 137 removed load of #%2 into %1 since it's still there.
+} if notVolatile(%1), operandsNotRelated(%3 %1), notSame(%1 '(hl+)' '(hl-)')
+
+replace restart {
+	ld	hl,#%1
+	ld	de,#%1
+} by {
+	; common peephole 138 used #%1 from hl for load into de.
+	ld	hl,#%1
+	ld	e,l
+	ld	d,h
+}
+
+replace restart {
+	ld	sp,hl
+	ld	hl,#0x0002
+	add	hl,sp
+} by {
+	ld	sp, hl
+	inc	hl
+	inc	hl
+	; common peephole 139 replaced addition by increment.
+}
+
+replace restart {
+	ex	de, hl
+	ld	hl, #%1
+	add	hl, de
+} by {
+	; common peephole 140 removed ex exploiting commutativity of addition.
+	ld	de, #%1
+	add	hl, de
+} if notUsed('de')
+
+replace restart {
+	ld	hl, #%1
+	add	hl, %2
+	ex	de, hl
+	inc	de
+} by {
+	ld	hl, #%1+1
+	; common peephole 141 moved increment to constant.
+	add	hl, %2
+	ex	de, hl
+} if notUsed('hl')
+
+
+// those might work for tlcs90 too
+replace restart {
+	pop	af
+	push	hl
+} by {
+	; common peephole 142 used ex to move hl onto the stack.
+	ex	(sp),hl
+} if isPort('z80' 'ez80_z80' 'z180' 'z80n'), notUsed('a'), notUsed('hl')
+
+replace restart {
+	pop	af
+	ld	hl, #%1
+	push	hl
+} by {
+	ld	hl, #%1
+	; common peephole 143 used ex to move hl onto the stack.
+	ex	(sp),hl
+} if isPort('z80' 'ez80_z80' 'z180' 'z80n'), notUsed('a'), notUsed('hl')
+
+replace restart {
+	pop	af
+	inc	sp
+	ld	hl,#%1
+	push	hl
+} by {
+	inc	sp
+	ld	hl,#%1
+	; common peephole 144 used ex to move #%1 onto the stack.
+	ex	(sp),hl
+} if isPort('z80' 'ez80_z80' 'z180' 'z80n'), notUsed('a'), notUsed('hl')
+
+replace restart {
+	pop	af
+	inc	sp
+	ld	h, %1 (ix)
+	ld	l, %2 (ix)
+	push	hl
+} by {
+	inc	sp
+	ld	h, %1 (ix)
+	ld	l, %2 (ix)
+	; common peephole 145 used ex to move %1 (ix) %2 (ix) onto the stack.
+	ex	(sp),hl
+} if isPort('z80' 'ez80_z80' 'z180' 'z80n'), notUsed('a'), notUsed('hl')
+
+replace restart {
+	pop	af
+	ld	a,#%1
+	push	af
+	inc	sp
+} by {
+	ld	h,#%1
+	ex	(sp),hl
+	; common peephole 146 used ex to move #%1 onto the stack.
+	inc	sp
+} if isPort('z80' 'ez80_z80' 'z180' 'z80n'), notUsed('a'), notUsed('hl')
+
+replace restart {
+	ld	%1,#%2
+	ld	%3 (%1),a
+%4:
+	ld	%1,%5
+} by {
+	ld	(#%2 + %3),a
+	; common peephole 147 directly used #%2 instead of going through %1 using indirect addressing.
+%4:
+	ld	%1,%5
+}
+
+replace restart {
+	pop	af
+	ld	%1,#%2
+	ld	%3 (%1),%4
+	ld	%1,#%5
+} by {
+	ld	a,%4
+	ld	(#%2 + %3),a
+	; common peephole 148 used #%2 directly instead of going through %1 using indirect addressing.
+	pop	af
+	ld	%1,#%5
+} if notSame(%3 'a')
+
+replace restart {
+	ld	%1,a
+	bit	%2,%1
+} by {
+	bit	%2,a
+	; common peephole 149 tested bit %2 of a directly instead of going through %1.
+} if notUsed(%1)
+
+replace restart {
+	sbc	a,%1
+	bit	7,a
+	jp	NZ,%2
+} by {
+	sbc	a,%1
+	jp	M,%2
+	; common peephole 150 used sign flag instead of testing bit 7.
+} if isPort('z80' 'ez80_z80' 'z180' 'z80n' 'tlcs90')
+
+replace restart {
+	ld	%1,a
+	or	a,a
+	jp	%3,%4
+	ld	a,%1
+} by {
+	ld	%1,a
+	or	a,a
+	jp	%3,%4
+	; common peephole 151 used value still in a instead of reloading from %1.
+}
+
+replace {
+	jp	%5
+	ret
+} by {
+	jp	%5
+	; common peephole 152 removed unused ret.
+}
+
+replace {
+	jp	%5
+	ld	sp,ix
+	pop	ix
+	ret
+} by {
+	jp	%5
+	; common peephole 153 removed unused ret.
+}
+
+replace restart {
+	%4	a,%1
+	jp	NZ,%2
+	xor	a,a
+} by {
+	%4	a,%1
+	jp	NZ,%2
+	; common peephole 154a removed redundant zeroing of a (which has just been tested to be #0x00).
+} if same(%4 'or' 'and'), notUsed('f')
+
+replace restart {
+	%4	a
+	jp	NZ,%2
+	xor	a,a
+} by {
+	%4	a
+	jp	NZ,%2
+	; common peephole 154b removed redundant zeroing of a (which has just been tested to be #0x00).
+} if same(%4 'inc' 'dec'), notUsed('f')
+
+replace restart {
+	%4	%1
+	jp	NZ,%2
+	xor	a,a
+} by {
+	%4	%1
+	jp	NZ,%2
+	; common peephole 154c reuseded zero of register (which has just been tested to be #0x00).
+	ld	a, %1
+} if same(%4 'inc' 'dec'), notUsed('f')
+
+replace restart {
+	add	a, #%1
+} by {
+	; common peephole 155a turned add into inc.
+	inc	a
+} if operandsLiteral(%1), immdInRange(1 1 '+' %1 0 %2), notUsed('cf')
+
+replace restart {
+	sub	a, #%1
+} by {
+	; common peephole 155b turned sub into dec.
+	dec	a
+} if operandsLiteral(%1), immdInRange(1 1 '+' %1 0 %2), notUsed('cf')
+
+replace restart {
+	add	a, #%1
+} by {
+	; common peephole 155c turned add into dec.
+	dec	a
+} if operandsLiteral(%1), immdInRange(0xFF 0xFF '+' %1 0 %2), notUsed('cf')
+
+replace restart {
+	dec	%1
+	inc	%1
+} by {
+	; common peephole 156a swap dec %1 / inc %1 pair.
+	inc	%1
+	dec	%1
+}
+
+replace restart {
+	inc	%1
+	dec	%1
+} by {
+	; common peephole 156b removed inc %1 / dec %1 pair.
+} if same(%1 'bc' 'de' 'hl' 'ix' 'iy' 'sp')
+
+replace restart {
+	inc	%1
+	dec	%1
+} by {
+	; common peephole 156c removed inc %1 / dec %1 pair.
+} if same(%1 'a' 'b' 'c' 'd' 'e' 'h' 'l' 'ixh' 'ixl' 'iyh' 'iyl'), notUsed('zf' 'vf' 'sf' 'nf' 'hf')
+
+replace restart {
+	inc	%2
+	inc	%1
+	dec	%1
+} by {
+	; common peephole 156e removed inc %1 / dec %1 pair.
+	inc	%1
+	inc	%2
+	dec	%1
+} if same(%1 'bc' 'de' 'hl' 'ix' 'iy' 'sp'), same(%2 'bc' 'de' 'hl' 'ix' 'iy' 'sp'), operandsNotRelated(%1 %2)
+
+replace restart {
+	jp	Z, %2
+	ld	a, #%3
+	jp	%1
+%2:
+	ld	a, #%4
+%1:
+} by {
+	ld	a, #%3
+	jp	NZ, %1
+%2:
+	ld	a, #%4
+	; common peephole 168z used double assignment in case of Z condition.
+%1:
+} if labelRefCountChange(%2 -1)
+
+replace restart {
+	jp	NZ, %2
+	ld	a, #%3
+	jp	%1
+%2:
+	ld	a, #%4
+%1:
+} by {
+	ld	a, #%3
+	jp	Z, %1
+%2:
+	ld	a, #%4
+	; common peephole 168nz used double assignment in case of NZ condition.
+%1:
+} if labelRefCountChange(%2 -1)
+
+replace restart {
+	jp	Z, %2
+	ld	a, #%3
+	jp	%1
+%2:
+	xor	a, a
+%1:
+} by {
+	ld	a, #%3
+	jp	NZ, %1
+	; common peephole 169xz used double assignment in case of Z condition.
+%2:
+	xor	a, a
+%1:
+} if labelRefCountChange(%2 -1)
+
+replace restart {
+	jp	NZ, %2
+	ld	a, #%3
+	jp	%1
+%2:
+	xor	a, a
+%1:
+} by {
+	ld	a, #%3
+	jp	Z, %1
+	; common peephole 169xnz used double assignment in case of NZ condition.
+%2:
+	xor	a, a
+%1:
+} if labelRefCountChange(%2 -1)
+
+replace restart {
+	jp	Z, %2
+	ld	c, #%3
+	jp	%1
+%2:
+	ld	c, #%4
+%1:
+} by {
+	ld	c, #%3
+	jp	NZ, %1
+%2:
+	ld	c, #%4
+	; common peephole 170z used double assignment in case of Z condition.
+%1:
+} if labelRefCountChange(%2 -1)
+
+replace restart {
+	jp	NZ, %2
+	ld	c, #%3
+	jp	%1
+%2:
+	ld	c, #%4
+%1:
+} by {
+	ld	c, #%3
+	jp	Z, %1
+%2:
+	ld	c, #%4
+	; common peephole 170nz used double assignment in case of NZ condition.
+%1:
+} if labelRefCountChange(%2 -1)
+
+replace restart {
+	jp	Z, %2
+	ld	e, #%3
+	jp	%1
+%2:
+	ld	e, #%4
+%1:
+} by {
+	ld	e, #%3
+	jp	NZ, %1
+%2:
+	ld	e, #%4
+	; common peephole 171z used double assignment in case of Z condition.
+%1:
+} if labelRefCountChange(%2 -1)
+
+replace restart {
+	jp	NZ, %2
+	ld	e, #%3
+	jp	%1
+%2:
+	ld	e, #%4
+%1:
+} by {
+	ld	e, #%3
+	jp	Z, %1
+%2:
+	ld	e, #%4
+	; common peephole 171nz used double assignment in case of NZ condition.
+%1:
+} if labelRefCountChange(%2 -1)
+
+replace restart {
+	jp	Z, %2
+	ld	l, #%3
+	jp	%1
+%2:
+	ld	l, #%4
+%1:
+} by {
+	ld	l, #%3
+	jp	NZ, %1
+%2:
+	ld	l, #%4
+	; common peephole 172z used double assignment in case of Z condition.
+%1:
+} if labelRefCountChange(%2 -1)
+
+replace restart {
+	jp	NZ, %2
+	ld	l, #%3
+	jp	%1
+%2:
+	ld	l, #%4
+%1:
+} by {
+	ld	l, #%3
+	jp	Z, %1
+%2:
+	ld	l, #%4
+	; common peephole 172nz used double assignment in case of NZ condition.
+%1:
+} if labelRefCountChange(%2 -1)
+
+replace restart {
+	ld	%1, %3
+	ld	%2, %4
+	push	%5
+} by {
+	; common peephole 173 eliminated assignment by pushing %6
+	push	%6
+} if canJoinRegs(%2 %1 %7), same(%7 %5), canJoinRegs(%4 %3 %6), notUsed(%5)
+
+replace restart {
+	ld	%1,%2
+	ld	%2,%1
+} by {
+	ld	%1,%2
+	; common peephole 176 remove unnecessary load back
+} if notVolatile(%1), notVolatile(%2), notSame(%1 '(hl+)' '(hl-)'), notSame(%2 '(hl+)' '(hl-)')
+
+replace restart {
+	ld	a, %1
+	push	af
+} by {
+	push	%2
+	; common peephole 177 replace pushed register pair
+} if notUsed('a'), canJoinRegs(%1 '' %2), canSplitReg(%2 %3), same(%3 %1)
+
+replace restart {
+	inc	%3
+	ld	%1, %2 (%3)
+} by {
+	; common peephole 178 moved increment of %3 after ld instruction
+	ld	%1, %4 (%3)
+	inc	%3
+} if operandsNotRelated(%1 %3), immdInRange(-128 127 '+' %2 1 %4)
+
+replace restart {
+	dec	%3
+	ld	%1, %2 (%3)
+} by {
+	; common peephole 179 moved decrement of %3 after ld instruction
+	ld	%1, %4 (%3)
+	dec	%3
+} if operandsNotRelated(%1 %3), immdInRange(-128 127 '-' %2 1 %4)
+
+//next rules optimize code after the call
+//replaces lot of `inc sp` by `ld hl,#n; add hl,sp; ld sp,hl`
+replace restart {
+	inc	sp
+	pop	%1
+	ld	%2 (%3), %4
+} by {
+	inc	sp
+	; common peephole 190: move pop instruction after register store
+	ld	%2 (%3), %4
+	pop	%1
+} if notSame(%1 %3 %4), operandsNotRelated(%1 %4)
+
+replace restart {
+	inc	sp
+	ld	%1 (%2), %3
+} by {
+	; common peephole 191a: move register store before stack restore
+	ld	%1 (%2), %3
+	inc	sp
+} if notSame(%2 'sp')
+
+replace restart {
+	inc	sp
+	pop	%1
+	ld	%2, %3
+} by {
+	; common peephole 191b: move register to register copy before SP increment
+	ld	%2, %3
+	inc	sp
+	pop	%1
+} if same(%3 'l' 'h'), notSame(%2 'l' 'h'), notUsed('hl'), operandsNotRelated(%1 %2 %3), notSame('sp' %2 %3)
+
+replace restart {
+	inc	sp
+	ld	%1, %2
+} by {
+	; common peephole 191c: move register store before stack restore
+	ld	%1, %2
+	inc	sp
+} if notUsed('hl'), same(%2 'h' 'l' 'sp'), notSame(%1 'h' 'l' 'sp')
+
+replace restart {
+	inc	sp
+	ld	%3, #%1
+	add	%3, sp
+	ld	sp, %3
+} by {
+	; common peephole 192: increase SP by addition
+	ld	%3, #%2
+	add	%3, sp
+	ld	sp, %3
+} if notUsed(%3), same(%3 'hl' 'ix' 'iy'), immdInRange(0 0x7fff '+' %1 1 %2)
+
+replace restart {
+	inc	sp
+	inc	sp
+	inc	sp
+	inc	sp
+	inc	sp
+} by {
+	; common peephole 193: increase SP by addition
+	ld	hl, #5
+	add	hl, sp
+	ld	sp, hl
+} if notUsed('hl')
+
+//next rules optimized some checks
+replace restart {
+	ld	a, %1
+	sub	a, #%7
+	ld	a, %2
+	sbc	a, #0x00
+	ld	a, %3
+	sbc	a, #0x00
+	ld	a, %4
+	sbc	a, #0x00
+	%5	C, %6
+} by {
+	; common peephole 194-1: symplify 32-bit compare for 8 bit values
+	ld	a, %2
+	or	a, %3
+	or	a, %4
+	jp	NZ, %9
+	ld	a, %1
+	cp	a, #%7
+	%5	C, %6
+%9:
+} if same(%5 'jr' 'jp' 'call'), notUsed('a'), canAssign('b' %3), canAssign('b' %3), newLabel(%9)
+
+replace restart {
+	ld	a, %1
+	sub	a, #%7
+	ld	a, %2
+	sbc	a, #%8
+	ld	a, %3
+	sbc	a, #0x00
+	ld	a, %4
+	sbc	a, #0x00
+	%5	C, %6
+} by {
+	; common peephole 194-2: symplify 32-bit compare for 16 bit values
+	ld	a, %3
+	or	a, %4
+	jp	NZ, %9
+	ld	a, %1
+	sub	a, #%7
+	ld	a, %2
+	sbc	a, #%8
+	%5	C, %6
+%9:
+} if same(%5 'jr' 'jp' 'call'), notUsed('a'), canAssign('b' %3), newLabel(%9)
+
+replace restart {
+	ld	a, #0xff
+	cp	a, %1
+	%2	NC, %3
+} by {
+	; common peephole 195-1: remove always true check
+} if same(%2 'jr' 'jp' 'call'), notUsed('a'), labelRefCountChange(%3 -1)
+
+replace restart {
+	ld	a, #0xff
+	sub	a, %1
+	ld	a, #0xff
+	sbc	a, %2
+	%3	NC, %4
+} by {
+	; common peephole 195-2: remove always true check
+} if same(%3 'jr' 'jp' 'call'), notUsed('a'), labelRefCountChange(%4 -1)
+
+// These ex-generating rules should be among the last ones since ex counts as a read from both hl and de for notUsed().
+barrier
+
+replace restart {
+	ld	e,l
+	ld	d,h
+} by {
+	; common peephole 156 used ex to load hl into de.
+	ex	de,hl
+} if isPort('z80' 'ez80_z80' 'z180' 'z80n' 'r2k' 'r2ka' 'r3ka' 'tlcs90'), notUsed('hl')
+
+replace restart {
+	ld	l,e
+	ld	h,d
+} by {
+	; common peephole 157 used ex to load de into hl.
+	ex	de,hl
+} if isPort('z80' 'ez80_z80' 'z180' 'z80n' 'r2k' 'r2ka' 'r3ka' 'tlcs90'), notUsed('de')
+
+barrier
+
+// Should be one of the last ones. Opens the code to further peephole optimization.
+replace restart {
+%1:
+} by {
+	; common peephole 158 removed unused label %1.
+} if labelRefCount(%1 0)
+
+// Ensure that all rules above see only jp, not jr.
+barrier
+
+replace {
+	add	hl,de
+	pop	de
+	jp	(hl)
+%1:
+	jp	%5
+	jp	%6
+	jp	%7
+%2:
+} by {
+	; common peephole 159-3 removed addition using short jumps in jump-table.
+	pop	de
+	jp	(hl)
+%1:
+	jr	%5
+	jr	%6
+	jr	%7
+%2:
+} if labelJTInRange
+
+replace {
+	add	hl,de
+	jp	(hl)
+%1:
+	jp	%5
+	jp	%6
+	jp	%7
+%2:
+} by {
+	; common peephole 159-3' removed addition using short jumps in jump-table.
+	jp	(hl)
+%1:
+	jr	%5
+	jr	%6
+	jr	%7
+%2:
+} if labelJTInRange
+
+replace {
+	add	hl,de
+	pop	de
+	jp	(hl)
+%1:
+	jp	%5
+	jp	%6
+	jp	%7
+	jp	%8
+%2:
+} by {
+	; common peephole 159-4 removed addition using short jumps in jump-table.
+	pop	de
+	jp	(hl)
+%1:
+	jr	%5
+	jr	%6
+	jr	%7
+	jr	%8
+%2:
+} if labelJTInRange
+
+replace {
+	add	hl,de
+	jp	(hl)
+%1:
+	jp	%5
+	jp	%6
+	jp	%7
+	jp	%8
+%2:
+} by {
+	; common peephole 159-4' removed addition using short jumps in jump-table.
+	jp	(hl)
+%1:
+	jr	%5
+	jr	%6
+	jr	%7
+	jr	%8
+%2:
+} if labelJTInRange
+
+replace {
+	add	hl,de
+	pop	de
+	jp	(hl)
+%1:
+	jp	%5
+	jp	%6
+	jp	%7
+	jp	%8
+	jp	%9
+%2:
+} by {
+	; common peephole 159-5 removed addition using short jumps in jump-table.
+	pop	de
+	jp	(hl)
+%1:
+	jr	%5
+	jr	%6
+	jr	%7
+	jr	%8
+	jr	%9
+%2:
+} if labelJTInRange
+
+replace {
+	add	hl,de
+	jp	(hl)
+%1:
+	jp	%5
+	jp	%6
+	jp	%7
+	jp	%8
+	jp	%9
+%2:
+} by {
+	; common peephole 159-5' removed addition using short jumps in jump-table.
+	jp	(hl)
+%1:
+	jr	%5
+	jr	%6
+	jr	%7
+	jr	%8
+	jr	%9
+%2:
+} if labelJTInRange
+
+replace {
+	add	hl,de
+	pop	de
+	jp	(hl)
+%1:
+	jp	%5
+	jp	%6
+	jp	%7
+	jp	%8
+	jp	%9
+	jp	%10
+%2:
+} by {
+	; common peephole 159-6 removed addition using short jumps in jump-table.
+	pop	de
+	jp	(hl)
+%1:
+	jr	%5
+	jr	%6
+	jr	%7
+	jr	%8
+	jr	%9
+	jr	%10
+%2:
+} if labelJTInRange
+
+replace {
+	add	hl,de
+	jp	(hl)
+%1:
+	jp	%5
+	jp	%6
+	jp	%7
+	jp	%8
+	jp	%9
+	jp	%10
+%2:
+} by {
+	; common peephole 150-6' removed addition using short jumps in jump-table.
+	jp	(hl)
+%1:
+	jr	%5
+	jr	%6
+	jr	%7
+	jr	%8
+	jr	%9
+	jr	%10
+%2:
+} if isPort('r2k' 'r2ka' 'r3ka'), labelJTInRange
+
+replace {
+	add	hl,de
+	jp	(hl)
+%1:
+	jp	%5
+	jp	%6
+	jp	%7
+	jp	%8
+	jp	%9
+	jp	%10
+%2:
+} by {
+	; common peephole 159-6' removed addition using short jumps in jump-table.
+	jp	(hl)
+%1:
+	jr	%5
+	jr	%6
+	jr	%7
+	jr	%8
+	jr	%9
+	jr	%10
+%2:
+} if labelJTInRange
+
+replace {
+	add	hl,de
+	pop	de
+	jp	(hl)
+%1:
+	jp	%5
+	jp	%6
+	jp	%7
+	jp	%8
+	jp	%9
+	jp	%10
+	jp	%11
+%2:
+} by {
+	; common peephole 159-7 removed addition using short jumps in jump-table.
+	pop	de
+	jp	(hl)
+%1:
+	jr	%5
+	jr	%6
+	jr	%7
+	jr	%8
+	jr	%9
+	jr	%10
+	jr	%11
+%2:
+} if labelJTInRange
+
+replace {
+	add	hl,de
+	jp	(hl)
+%1:
+	jp	%5
+	jp	%6
+	jp	%7
+	jp	%8
+	jp	%9
+	jp	%10
+	jp	%11
+%2:
+} by {
+	; common peephole 159-7' removed addition using short jumps in jump-table.
+	jp	(hl)
+%1:
+	jr	%5
+	jr	%6
+	jr	%7
+	jr	%8
+	jr	%9
+	jr	%10
+	jr	%11
+%2:
+} if labelJTInRange
+
+barrier
+
+// Do all jump optimizations before replacing by ret.
+
+replace restart {
+	jp	%5
+} by {
+	ret
+	; common peephole 160 replaced jump by return.
+} if labelIsReturnOnly(%5), labelRefCountChange(%5 -1)
+
+replace restart {
+	jp	%1,%5
+} by {
+	ret	%1
+	; common peephole 161 replaced jump by return.
+} if labelIsReturnOnly(%5), labelRefCountChange(%5 -1)
+
+// Replace jp by ret before replacing jp by jr outside of jump tables, since using ret can reduce the number of references to jump labels.
+barrier
+
+// On Z80 and Z80N, jr is smaller, but slower than jp.
+replace restart {
+	jp	%5
+} by {
+	; common peephole 162 changed absolute to relative unconditional jump.
+	jr	%5
+} if optimizeFor('!code-speed'), labelInRange(%5)
+
+// On Z180, eZ80, Rabbit and TLCS-90, jr is smaller, and at least as fast as jp.
+replace restart {
+	jp	%5
+} by {
+	; common peephole 162a changed absolute to relative unconditional jump.
+	jr	%5
+} if isPort('z180' 'ez80_z80' 'r2k' 'r2ka' 'r3ka' 'tlcs90' 'gbz80'), labelInRange(%5)
+
+replace restart {
+	jp	%1, %5
+} by {
+	; common peephole 163 changed absolute to relative conditional jump.
+	jr	%1, %5
+} if same(%1 'C' 'NC' 'NZ' 'Z'), labelInRange(%5)
+
+replace {
+	dec	b
+	jr	NZ, %5
+} by {
+	; common peephole 167 used djnz
+	djnz	%5
+} if isPort('z80' 'ez80_z80' 'z180' 'z80n' 'r2k' 'r2ka' 'r3ka' 'tlcs90')
+
+barrier
diff -Nru sdcc-4.0.0+dfsg/src/z80/peeph-ez80_z80.def sdcc-4.2.0+dfsg/src/z80/peeph-ez80_z80.def
--- sdcc-4.0.0+dfsg/src/z80/peeph-ez80_z80.def	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/z80/peeph-ez80_z80.def	2020-07-20 20:08:11.000000000 +0000
@@ -0,0 +1,111 @@
+// peeph-ez80_z80.def - eZ80_Z80 specific peephole rules
+//
+// (c) Philipp Klaus Krause (pkk@spth.de, philipp@colecovision.eu) 2006 - 2020
+//
+// This program is free software; you can redistribute it and/or modify it
+// under the terms of the GNU General Public License as published by the
+// Free Software Foundation; either version 2, or (at your option) any
+// later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+replace {
+	inc	%1
+	inc	%1
+} by {
+	;peephole ez80-1: replace 2 increments of index register by one LEA instruction
+	lea	%1, %1, #+2
+} if canAssign('d' '0' %1)
+
+replace {
+	lea	%1, %2, #%3
+	inc	%1
+} by {
+	lea	%1, %2, #%4
+	;peephole ez80-2: replace decrement by decreased index of LEA instruction
+} if immdInRange(-128 127 '+' %3 1 %4)
+
+replace {
+	dec	%1
+	dec	%1
+} by {
+	;peephole ez80-3: replace 2 decrements of index register by one LEA instruction
+	lea	%1, %1, #-2
+} if canAssign('e' '0' %1)
+
+replace {
+	lea	%1, %2, #%3
+	dec	%1
+} by {
+	lea	%1, %2, #%4
+	;peephole ez80-4: replace increment by incremented index of LEA instruction
+} if immdInRange(-128 127 '-' %3 1 %4)
+
+replace restart {
+	ld      %3, %4 (%1)
+	ld      %2, %5 (%1)
+} by {
+	;eZ80 peephole 5: replace 2 8-bit indirect loads to register pair by one 16-bit
+	ld      %6, %4 (%1)
+} if canJoinRegs(%2 %3 %6), immdInRange(-128 127 '+' %4 1 %7), same(%5 %7)
+
+replace restart {
+	ld	a, (hl)
+	inc	hl
+	ld	h, (hl)
+	ld	l, a
+} by {
+	;eZ80 peephole 6: replace Z80 style load to HL from memory addressed by HL itself
+	ld	hl, (hl)
+} if notUsed('a')
+
+replace restart {
+	ld	%2, (hl)
+	inc	hl
+	ld	%1, (hl)
+} by {
+	;eZ80 peephole 7: replace Z80 style load to register pair from memory addressed by HL
+	ld	%3, (hl)
+	inc	hl
+} if canJoinRegs(%1 %2 %3)
+
+replace restart {
+	ld	%4 (%1), %3
+	ld	%5 (%1), %2
+} by {
+	;eZ80 peephole 8: replace 2 8-bit indirect register pair stores by one 16-bit
+	ld	%4 (%1), %6
+} if canJoinRegs(%2 %3 %6), immdInRange(-128 127 '+' %4 1 %7), same(%5 %7)
+
+replace restart {
+	ld	a, %1 (%2)
+	ld	%3 (%4), a
+	ld	a, %5 (%2)
+	ld	%6 (%4), a
+} by {
+	;eZ80 peephole 9hl: replace byte copy by word copy
+	ld	hl, %1 (%2)
+	ld	%3 (%4), hl
+	ld	a, h
+} if notUsed('hl'), immdInRange(-128 127 '+' %1 1 %7), same(%5 %7), immdInRange(-128 127 '+' %3 1 %8), same(%6 %8)
+
+replace restart {
+	ld	a, %1 (%2)
+	ld	%3 (%4), a
+	ld	a, %5 (%2)
+	ld	%6 (%4), a
+} by {
+	;eZ80 peephole 9de: replace byte copy by word copy
+	ld	de, %1 (%2)
+	ld	%3 (%4), de
+	ld	a, d
+} if notUsed('de'), immdInRange(-128 127 '+' %1 1 %7), same(%5 %7), immdInRange(-128 127 '+' %3 1 %8), same(%6 %8)
+
+barrier
diff -Nru sdcc-4.0.0+dfsg/src/z80/peeph-gbz80.def sdcc-4.2.0+dfsg/src/z80/peeph-gbz80.def
--- sdcc-4.0.0+dfsg/src/z80/peeph-gbz80.def	2019-11-14 11:36:33.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/z80/peeph-gbz80.def	1970-01-01 00:00:00.000000000 +0000
@@ -1,823 +0,0 @@
-// Due to major changes in the Z80 peepholes the old peepholes from peeph.def have been moved here.
-// All new peepholes went into peeph-z80.def. A GBZ80 expert should look into this files and peeph-z80.def
-// And move peepholes that are useful and correct for both Z80 and GBZ80 into peeph.def.
-
-// peeph.def - Common Z80 and gbz80 peephole rules
-//
-//
-// (c) Philipp Klaus Krause (pkk@spth.de, philipp@colecovision.eu) 2006 - 2007
-//
-// This program is free software; you can redistribute it and/or modify it
-// under the terms of the GNU General Public License as published by the
-// Free Software Foundation; either version 2, or (at your option) any
-// later version.
-//
-// This program is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program; if not, write to the Free Software
-// Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-
-replace restart {
-	ld	%1, %1
-} by {
-	; peephole 1 removed redundant load.
-} if notVolatile(%1)
-
-replace restart {
-	ldhl	sp,#%1
-	dec	hl
-} by {
-	; peephole 2 combined ld and dec.
-	ldhl	sp,#(%1 - 1)
-}
-
-replace restart {
-	jp	NC,%1
-	jp	%2
-%1:
-} by {
-	jp	C,%2
-	; peephole 3 removed jp by using inverse jump logic
-%1:
-} if labelRefCountChange(%1 -1)
-
-replace restart {
-	jp	C,%1
-	jp	%2
-%1:
-} by {
-	jp	NC,%2
-	; peephole 4 removed jp by using inverse jump logic
-%1:
-} if labelRefCountChange(%1 -1)
-
-replace restart {
-	jp	NZ,%1
-	jp	%2
-%1:
-} by {
-	jp	Z,%2
-	; peephole 5 removed jp by using inverse jump logic
-%1:
-} if labelRefCountChange(%1 -1)
-
-replace restart {
-	jp	Z,%1
-	jp	%2
-%1:
-} by {
-	jp	NZ,%2
-	; peephole 6 removed jp by using inverse jump logic
-%1:
-} if labelRefCountChange(%1 -1)
-
-replace restart {
-	jp	%5
-} by {
-	jp	%6
-	; peephole 7 jumped to %6 directly instead of via %5.
-} if labelIsUncondJump(), notSame(%5 %6), labelRefCountChange(%5 -1), labelRefCountChange(%6 +1)
-
-replace restart {
-	jp	%1,%5
-} by {
-	jp	%1,%6
-	; peephole 8 jumped to %6 directly instead of via %5.
-} if labelIsUncondJump(), notSame(%5 %6), labelRefCountChange(%5 -1), labelRefCountChange(%6 +1)
-
-replace restart {
-	jp	%1
-%2:
-%1:
-} by {
-   ; peephole 9 eliminated jump.
-%2:
-%1:
-} if labelRefCountChange(%1 -1)
-
-replace {
-	ld	e,#0x%1
-	ld	d,#0x%2
-} by {
-	ld	de,#0x%2%1
-	; peephole 10 combined constant loads into register pair.
-}
-
-replace {
-	ld	l,#0x%1
-	ld	h,#0x%2
-} by {
-	ld	hl,#0x%2%1
-	; peephole 11 combined constant loads into register pair.
-}
-
-replace {
-	ld	c,#0x%1
-	ld	b,#0x%2
-} by {
-	ld	bc,#0x%2%1
-	; peephole 12 combined constant loads into register pair.
-}
-
-replace restart {
-	ld	%1,a
-	ld	a,%1
-} by {
-	ld	%1,a
-	; peephole 13 removed redundant load from %1 into a.
-} if notVolatile(%1), notSame(%1 '(hl+)'), notSame(%1 '(hl-)')
-
-replace restart {
-	ld	a,%1
-	ld	%1,a
-} by {
-	ld	a,%1
-	; peephole 14 removed redundant load from a into %1.
-} if notVolatile(%1), notSame(%1 '(hl+)'), notSame(%1 '(hl-)')
-
-replace restart {
-	and	a,%1
-	or	a,a
-} by {
-	and	a,%1
-	; peephole 15 removed redundant or after and.
-}
-
-replace restart {
-	xor	a,%1
-	or	a,a
-} by {
-	xor	a,%1
-	; peephole 16 removed redundant or after xor.
-}
-
-replace restart {
-	ld	%1,a
-	and	a,%2
-	ld	%1,a
-} by {
-	; peephole 17 removed redundant load into %1.
-	and	a,%2
-	ld	%1,a
-} if notVolatile(%1)
-
-replace {
-	ld	%1,%2
-	ld	a,%2
-} by {
-	ld	a,%2
-	ld	%1,a
-	; peephole 18 loaded value in a first and used it next
-} if notVolatile(%1 %2), canAssign(%1 'a'), operandsNotRelated(%1 %2)
-
-replace restart {
-	ld	%1,%2
-	ld	%3,%4
-	ld	%2,%1
-	ld	%4,%3
-} by {
-	ld	%1,%2
-	ld	%3,%4
-	; peephole 19 removed redundant load from %3%1 into %4%2
-} if notVolatile(%1 %2 %3 %4)
-
-replace restart {
-	ld	a,%1
-	sub	a,%2
-	jp	%3,%4
-	ld	a,%1
-} by {
-	ld	a,%1
-	cp	a,%2
-	jp	%3,%4
-	; peephole 20 removed load by replacing sub with cp
-	assert	a=%1
-} if notVolatile(%1)
-
-replace restart {
-	assert	a=%1
-	sub	a,%2
-	jp	%3,%4
-	ld	a,%1
-} by {
-	cp	a,#%2
-	jp	%3,%4
-	; peephole 21 removed load by replacing sub with cp
-	assert	a=%1
-}
-
-replace restart {
-	assert	a=%1
-} by {
-}
-
-replace restart {
-	rlca
-	ld	a,#0x00
-	rla
-} by {
-	rlca
-	and	a,#0x01
-	; peephole 22 replaced zero load, rla by and since rlca writes the same value to carry bit and least significant bit.
-}
-
-replace restart {
-	add	a,#0x00
-	ld	%2,a
-	ld	a,%3
-	adc	a,%4
-} by {
-	; peephole 23 removed lower part of multibyte addition.
-	ld	%2,a
-	ld	a,%3
-	add	a,%4
-}
-
-replace restart {
-	or	a,%1
-	jp	NZ,%2
-	ld	%3,#0x00
-} by {
-	or	a,%1
-	jp	NZ,%2
-	ld	%3,a
-	; peephole 24 replaced constant #0x00 by a (which has just been tested to be #0x00).
-}
-
-replace restart {
-	and	a,%1
-	jp	NZ,%2
-	ld	%3,#0x00
-} by {
-	and	a,%1
-	jp	NZ,%2
-	ld	%3,a
-	; peephole 25 replaced constant #0x00 by a (which has just been tested to be #0x00).
-}
-
-replace restart {
-	ld	bc,#%1 + %2
-	inc	bc
-	inc	bc
-	inc	bc
-} by {
-	ld	bc,#%1 + %2 + 3
-	; peephole 26 moved triple increment of bc to constant.
-}
-
-replace restart {
-	ld	bc,#%1 + %2
-	inc	bc
-	inc	bc
-} by {
-	ld	bc,#%1 + %2 + 2
-	; peephole 27 moved double increment of bc to constant.
-}
-
-replace restart {
-	ld	bc,#%1 + %2
-	inc	bc
-} by {
-	ld	bc,#%1 + %2 + 1
-	; peephole 28 moved increment of bc to constant.
-}
-
-replace restart {
-	ld	bc,#%1
-	ld	a,c
-	add	a,#0x%2
-	ld	c,a
-	ld	a,b
-	adc	a,#0x%3
-	ld	b,a
-} by {
-	ld	bc,#%1 + 0x%3%2
-	; peephole 29 moved addition of constant 0x%3%2 to bc to constant.
-}
-
-replace restart {
-	ld	bc,#%1 + %4
-	ld	a,c
-	add	a,#0x%2
-	ld	c,a
-	ld	a,b
-	adc	a,#0x%3
-	ld	b,a
-} by {
-	ld	bc,#%1 + %4 + 0x%3%2
-	; peephole 30 moved addition of constant 0x%3%2 to bc to constant.
-}
-
-replace restart {
-	call	%1
-	ret
-} by {
-	jp	%1
-	; peephole 31 replaced call at end of function by jump.
-}
-
-replace restart {
-	jp	Z, %2
-	ld	a, #%3
-	jp	%1
-%2:
-	ld	a, #%4
-%1:
-} by {
-	ld	a, #%3
-	jp	NZ, %1
-%2:
-	ld	a, #%4
-	; peephole 168z used double assignment in case of Z condition.
-%1:
-} if labelRefCountChange(%2 -1) 
-
-replace restart {
-	jp	NZ, %2
-	ld	a, #%3
-	jp	%1
-%2:
-	ld	a, #%4
-%1:
-} by {
-	ld	a, #%3
-	jp	Z, %1
-%2:
-	ld	a, #%4
-	; peephole 168nz used double assignment in case of NZ condition.
-%1:
-} if labelRefCountChange(%2 -1) 
-
-replace restart {
-	jp	Z, %2
-	ld	a, #%3
-	jp	%1
-%2:
-	xor	a, a
-%1:
-} by {
-	ld	a, #%3
-	jp	NZ, %1
-	; peephole 169xz used double assignment in case of Z condition.
-%2:
-	xor	a, a
-%1:
-} if labelRefCountChange(%2 -1)
-
-replace restart {
-	jp	NZ, %2
-	ld	a, #%3
-	jp	%1
-%2:
-	xor	a, a
-%1:
-} by {
-	ld	a, #%3
-	jp	Z, %1
-	; peephole 169xnz used double assignment in case of NZ condition.
-%2:
-	xor	a, a
-%1:
-} if labelRefCountChange(%2 -1)
-
-replace restart {
-	jp	Z, %2
-	ld	c, #%3
-	jp	%1
-%2:
-	ld	c, #%4
-%1:
-} by {
-	ld	c, #%3
-	jp	NZ, %1
-%2:
-	ld	c, #%4
-	; peephole 170z used double assignment in case of Z condition.
-%1:
-} if labelRefCountChange(%2 -1)
-
-replace restart {
-	jp	NZ, %2
-	ld	c, #%3
-	jp	%1
-%2:
-	ld	c, #%4
-%1:
-} by {
-	ld	c, #%3
-	jp	Z, %1
-%2:
-	ld	c, #%4
-	; peephole 170nz used double assignment in case of NZ condition.
-%1:
-} if labelRefCountChange(%2 -1)
-
-replace restart {
-	jp	Z, %2
-	ld	e, #%3
-	jp	%1
-%2:
-	ld	e, #%4
-%1:
-} by {
-	ld	e, #%3
-	jp	NZ, %1
-%2:
-	ld	e, #%4
-	; peephole 171z used double assignment in case of Z condition.
-%1:
-} if labelRefCountChange(%2 -1)
-
-replace restart {
-	jp	NZ, %2
-	ld	e, #%3
-	jp	%1
-%2:
-	ld	e, #%4
-%1:
-} by {
-	ld	e, #%3
-	jp	Z, %1
-%2:
-	ld	e, #%4
-	; peephole 171nz used double assignment in case of NZ condition.
-%1:
-} if labelRefCountChange(%2 -1)
-
-replace restart {
-	jp	Z, %2
-	ld	l, #%3
-	jp	%1
-%2:
-	ld	l, #%4
-%1:
-} by {
-	ld	l, #%3
-	jp	NZ, %1
-%2:
-	ld	l, #%4
-	; peephole 172z used double assignment in case of Z condition.
-%1:
-} if labelRefCountChange(%2 -1)
-
-replace restart {
-	jp	NZ, %2
-	ld	l, #%3
-	jp	%1
-%2:
-	ld	l, #%4
-%1:
-} by {
-	ld	l, #%3
-	jp	Z, %1
-%2:
-	ld	l, #%4
-	; peephole 172nz used double assignment in case of NZ condition.
-%1:
-} if labelRefCountChange(%2 -1)
-
-barrier
-
-// Should be one of the last ones. Opens the code to further peephole optimization.
-replace restart {
-%1:
-} by {
-	; peephole 32 removed unused label %1.
-} if labelRefCount(%1 0)
-
-// Ensure that all rules above see only jp, not jr.
-barrier
-
-replace {
-	add	hl,de
-	pop	de
-	jp	(hl)
-%1:
-	jp	%5
-	jp	%6
-	jp	%7
-%2:
-} by {
-	; peephole 150-3 removed addition using short jumps in jump-table.
-	pop	de
-	jp	(hl)
-%1:
-	jr	%5
-	jr	%6
-	jr	%7
-%2:
-} if labelJTInRange
-
-replace {
-	add	hl,de
-	jp	(hl)
-%1:
-	jp	%5
-	jp	%6
-	jp	%7
-%2:
-} by {
-	; peephole 150-3' removed addition using short jumps in jump-table.
-	jp	(hl)
-%1:
-	jr	%5
-	jr	%6
-	jr	%7
-%2:
-} if labelJTInRange
-
-replace {
-	add	hl,de
-	pop	de
-	jp	(hl)
-%1:
-	jp	%5
-	jp	%6
-	jp	%7
-	jp	%8
-%2:
-} by {
-	; peephole 150-4 removed addition using short jumps in jump-table.
-	pop	de
-	jp	(hl)
-%1:
-	jr	%5
-	jr	%6
-	jr	%7
-	jr	%8
-%2:
-} if labelJTInRange
-
-replace {
-	add	hl,de
-	jp	(hl)
-%1:
-	jp	%5
-	jp	%6
-	jp	%7
-	jp	%8
-%2:
-} by {
-	; peephole 150-4' removed addition using short jumps in jump-table.
-	jp	(hl)
-%1:
-	jr	%5
-	jr	%6
-	jr	%7
-	jr	%8
-%2:
-} if labelJTInRange
-
-replace {
-	add	hl,de
-	pop	de
-	jp	(hl)
-%1:
-	jp	%5
-	jp	%6
-	jp	%7
-	jp	%8
-	jp	%9
-%2:
-} by {
-	; peephole 150-5 removed addition using short jumps in jump-table.
-	pop	de
-	jp	(hl)
-%1:
-	jr	%5
-	jr	%6
-	jr	%7
-	jr	%8
-	jr	%9
-%2:
-} if labelJTInRange
-
-replace {
-	add	hl,de
-	jp	(hl)
-%1:
-	jp	%5
-	jp	%6
-	jp	%7
-	jp	%8
-	jp	%9
-%2:
-} by {
-	; peephole 150-5' removed addition using short jumps in jump-table.
-	jp	(hl)
-%1:
-	jr	%5
-	jr	%6
-	jr	%7
-	jr	%8
-	jr	%9
-%2:
-} if labelJTInRange
-
-replace {
-	add	hl,de
-	pop	de
-	jp	(hl)
-%1:
-	jp	%5
-	jp	%6
-	jp	%7
-	jp	%8
-	jp	%9
-	jp	%10
-%2:
-} by {
-	; peephole 150-6 removed addition using short jumps in jump-table.
-	pop	de
-	jp	(hl)
-%1:
-	jr	%5
-	jr	%6
-	jr	%7
-	jr	%8
-	jr	%9
-	jr	%10
-%2:
-} if labelJTInRange
-
-replace {
-	add	hl,de
-	jp	(hl)
-%1:
-	jp	%5
-	jp	%6
-	jp	%7
-	jp	%8
-	jp	%9
-	jp	%10
-%2:
-} by {
-	; peephole 150-6' removed addition using short jumps in jump-table.
-	jp	(hl)
-%1:
-	jr	%5
-	jr	%6
-	jr	%7
-	jr	%8
-	jr	%9
-	jr	%10
-%2:
-} if labelJTInRange
-
-replace {
-	add	hl,de
-	pop	de
-	jp	(hl)
-%1:
-	jp	%5
-	jp	%6
-	jp	%7
-	jp	%8
-	jp	%9
-	jp	%10
-	jp	%11
-%2:
-} by {
-	; peephole 150-7 removed addition using short jumps in jump-table.
-	pop	de
-	jp	(hl)
-%1:
-	jr	%5
-	jr	%6
-	jr	%7
-	jr	%8
-	jr	%9
-	jr	%10
-	jr	%11
-%2:
-} if labelJTInRange
-
-replace {
-	add	hl,de
-	jp	(hl)
-%1:
-	jp	%5
-	jp	%6
-	jp	%7
-	jp	%8
-	jp	%9
-	jp	%10
-	jp	%11
-%2:
-} by {
-	; peephole 150-7' removed addition using short jumps in jump-table.
-	jp	(hl)
-%1:
-	jr	%5
-	jr	%6
-	jr	%7
-	jr	%8
-	jr	%9
-	jr	%10
-	jr	%11
-%2:
-} if labelJTInRange
-
-barrier
-
-// Do all jump optimizations before replacing by ret.
-
-replace restart {
-	jp	%5
-} by {
-	ret
-	; peephole 151 replaced jump by return.
-} if labelIsReturnOnly(%5), labelRefCountChange(%5 -1)
-
-replace restart {
-	jp	%1,%5
-} by {
-	ret	%1
-	; peephole 152 replaced jump by return.
-} if labelIsReturnOnly(%5), labelRefCountChange(%5 -1)
-
-replace {
-	jp	%5
-} by {
-	jr	%5
-	; peephole 153 changed absolute to relative unconditional jump.
-} if labelInRange(%5)
-
-replace {
-	jp	%1,%5
-} by {
-	jr	%1,%5
-	; peephole 154 changed absolute to relative conditional jump.
-} if labelInRange(%5)
-
-barrier
-
-// Do not try further peephole optimization after these, as other peepholes e.g. might try to generate add a, (hl-), etc otherwise.
-
-replace {
-	ld	a, (hl)
-	inc	hl
-} by {
-	ld	a, (hl+)
-	; peephole GB1 used ldi to increment hl after load
-}
-
-replace {
-	ld	a, (hl)
-	dec	hl
-} by {
-	ld	a, (hl-)
-	; peephole GB2 used ldd to decrement hl after load
-}
-
-replace {
-	ld	(hl), a
-	inc	hl
-} by {
-	ld	(hl+), a
-	; peephole GB3 used ldi to increment hl after load
-}
-
-replace {
-	ld	(hl), a
-	dec	hl
-} by {
-	ld	(hl-), a
-	; peephole GB4 used ldd to decrement hl after load
-}
-
-replace {
-	inc hl
-	dec hl
-} by {
-	; peephole GB5 removed inc hl / dec hl pair
-}
-
-replace {
-	ld	(hl), a
-	inc	de
-	ld	a, (de)
-	inc	hl
-} by {
-	ld	(hl+), a
-	; peephole GB6 used ldi to increment hl
-	inc	de
-	ld	a, (de)
-}
-
-replace {
-	ld	a, (hl)
-	ld	(bc), a
-	inc	bc
-	inc	hl
-} by {
-	ld	a, (hl+)
-	; peephole GB7 used ldi to increment hl
-	ld	(bc), a
-	inc	bc
-}
-
diff -Nru sdcc-4.0.0+dfsg/src/z80/peeph-r2k.def sdcc-4.2.0+dfsg/src/z80/peeph-r2k.def
--- sdcc-4.0.0+dfsg/src/z80/peeph-r2k.def	2019-11-14 11:36:33.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/z80/peeph-r2k.def	2020-09-27 12:58:16.000000000 +0000
@@ -3,7 +3,7 @@
 // Some of these peepholes could be potentially moved to peeph.def, but a
 // GBZ80 expert should have a look at them before.
 //
-// (c) Philipp Klaus Krause (pkk@spth.de, philipp@colecovision.eu) 2006 - 2015
+// (c) Philipp Klaus Krause (pkk@spth.de, philipp@colecovision.eu) 2006 - 2020
 // *** modified by Leland Morrison for rabbit 2000 processor 2011
 //
 // This program is free software; you can redistribute it and/or modify it
@@ -21,1322 +21,96 @@
 // Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
 
 replace restart {
-	ld	%1, %1
-} by {
-	; peephole 0 removed redundant load from %1 into %1.
-} if notVolatile(%1)
-
-replace restart {
-	ld	%1, %2
-} by {
-	; peephole 1 removed dead load from %2 into %1.
-} if notVolatile(%1), notUsed(%1), notVolatile(%2)
-
-replace restart {
-	add	ix,sp
-} by {
-	; peephole 2 removed dead frame pointer setup.
-} if notUsed('ix')
-
-replace restart {
-	ld	%1, %2 + %3
-} by {
-	; peephole 3 removed dead load from %2 + %3 into %1.
-} if notVolatile(%1), notUsed(%1)
-// Should probably check for notVolatile(%2), too, but gives many false positives and no regression tests fail.
-
-replace restart {
-	ld	%1, (iy)
-} by {
-	ld	%1, 0 (iy)
-	; peephole 4 made 0 offset explicit.
-}
-
-replace restart {
-	ld	(iy), %1
-} by {
-	ld	0 (iy), %1
-	; peephole 5 made 0 offset explicit.
-}
-
-replace restart {
-	inc	hl
-} by {
-	; peephole 5a removed dead increment of hl.
-} if notUsed('hl')
-
-replace restart {
-	dec	hl
-} by {
-	; peephole 6 removed dead decrement of hl.
-} if notUsed('hl')
-
-replace restart {
-	ld	%1, %2 (iy)
-} by {
-	; peephole 7 removed dead load from %2 (iy) into %1.
-} if notUsed(%1)
-// Should probably check for notVolatile(), but gives many false positives and no regression tests fail.
-
-replace restart {
-	ld	%1, %2 (ix)
-} by {
-	; peephole 8 removed dead load from %2 (ix) into %1.
-} if notUsed(%1)
-
-replace restart {
-	ld	%1, %2
-	ld	%3, %1
-} by {
-	; peephole 9 loaded %3 from %2 directly instead of going through %1.
-	ld	%3, %2
-} if canAssign(%3 %2), notVolatile(%1), notUsed(%1)
-
-replace restart {
-	ld	%1, hl
-	ld	hl, %1
-} by {
-	; peephole 9a reused value still in hl.
-	ld	%1, hl
-} if notVolatile(%1)
-
-replace restart {
-	ld	%1, %2
-	ld	%3, %4
-	ld	%5, %1
-} by {
-	ld	%5, %2
-	; peephole 10 loaded %5 from %2 directly instead of going through %1.
-	ld	%3, %4
-} if canAssign(%5 %2), notVolatile(%1), operandsNotRelated(%1 %4), operandsNotRelated(%1 %3), operandsNotRelated(%3 %5), operandsNotRelated(%4 %5), notUsed(%1), notSame(%3 %4 '(hl)' '(de)' '(bc)'), notVolatile(%5)
-// Rule OK unless both %5 and %4 are volatile, but we can't express that directly.
-
-replace restart {
-	ld	%1, %2 (%3)
-	ld	%4, %1
-} by {
-	; peephole 11 loaded %2 (%3) into %4 directly instead of going through %1.
-	ld	%4, %2 (%3)
-} if canAssign(%4 %2 %3), notVolatile(%1), notUsed(%1)
-
-replace restart {
-	ld	%1, %2
-	ld	%3 (%4), %1
-} by {
-	; peephole 12 loaded %2 into %3 (%4) directly instead of going through %1.
-	ld	%3 (%4), %2
-} if canAssign(%3 %4 %2), notVolatile(%1), notUsed(%1), notSame(%1 'hl')
-
-replace restart {
-	ld	%1, %2 (%3)
-	ld	%4, %5 (%6)
-	ld	%7, %1
-} by {
-	ld	%7, %2 (%3)
-	; peephole 13 loaded %2 (%3) into %7 directly instead of going through %1.
-	ld	%4, %5 (%6)
-} if canAssign(%7 %2 %3), notVolatile(%1), notUsed(%1), notSame(%1 %4), notSame(%7 %4)
-
-replace restart {
-	ld	%1, %7
-	ld	%5 (%6), %4
-	ld	%2 (%3), %1
-} by {
-	ld	%5 (%6), %4
-	; peephole 14 loaded %7 into %2 (%3) directly instead of going through %1.
-	ld	%2 (%3), %7
-} if canAssign(%2 %3 %7), notVolatile(%1), notUsed(%1), notSame(%1 %4 %1 'hl')
-
-replace restart {
-	ld	%1, %2 (%3)
-	ld	%4, %5
-	ld	%7, %1
-} by {
-	ld	%7, %2 (%3)
-	; peephole 15 loaded %2 (%3) into %7 directly instead of going through %1.
-	ld	%4, %5
-} if canAssign(%7 %2 %3), notVolatile(%1), notUsed(%1), operandsNotRelated(%1 %5), operandsNotRelated(%7 %4), operandsNotRelated(%7 %5), notSame(%4 '(hl)' '(de)' '(bc)'), notSame(%5 '(hl)' '(de)' '(bc)' '(iy)')
-
-replace restart {
-	ld	%1,#%2
-	ld	a,%3 (%1)
-} by {
-	; peephole 16 loaded %2 into a directly instead of going through %1.
-	ld	a,(#%2 + %3)
-} if notUsed(%1)
-
-replace restart {
-	ld	hl,#%1
-	ld	a,(hl)
-} by {
-	ld	a,(#%1)
-	; peephole 17 loaded a from (#%1) directly instead of using hl.
-} if notUsed('hl')
-
-replace restart {
-	ld	hl,#%1 + %2
-	ld	a,(hl)
-} by {
-	; peephole 18 loaded %2 into a directly instead of using hl.
-	ld	a,(#%1 + %2)
-} if notUsed('hl')
-
-replace restart {
-	ld	hl,#%1
-	ld	(hl),a
-} by {
-	ld	(#%1),a
-	; peephole 19 loaded (#%1) from a directly instead of using hl.
-} if notUsed('hl')
-
-replace restart {
-	ld	hl,#%1 + %2
-	ld	(hl),a
-} by {
-	ld	(#%1 + %2),a
-	; peephole 20 loaded (#%1) from a directly instead of using hl.
-} if notUsed('hl')
-
-replace restart {
-	srl	%1
-	ld	a,%1
-} by {
-	ld	a,%1
-	; peephole 21 shifted in a instead of %1.
-	srl	a
-} if notVolatile(%1), notUsed(%1)
-
-replace restart {
-	ld	e, l
-	ld	d, h
-	ld	a, (de)
-	srl	a
-	ld	(de), a
-} by {
-	ld	e, l
-	ld	d, h
-	srl	(hl)
-	; peephole 21a shifted in (hl) instead of a.
-} if notUsed('a')
-
-replace restart {
-	ld	iy, #%1
-	ld	%2, %3 (iy)
-	srl	%2
-	bit %4, %3 (iy)
-} by {
-	ld	hl, #%1 + %3
-	; peephole 21c used hl instead of iy.
-	ld	%2, (hl)
-	srl %2
-	bit %4, (hl)
-} if notUsed('iy'), notUsed('hl')
-
-replace restart {
-	ld	%1,(hl)
-	ld	a,%2 (%3)
-	sub	a,%1
-} by {
-	ld	a,%2 (%3)
-	; peephole 22 used (hl) in sub directly instead of going through %1.
-	sub	a,(hl)
-} if notVolatile(%1), notUsed(%1)
-
-replace restart {
-	inc	bc
-	ld	l,c
-	ld	h,b
-} by {
-	ld	l,c
-	ld	h,b
-	; peephole 23 incremented in hl instead of bc.
-	inc	hl
-} if notUsed('bc')
-
-replace restart {
-	inc	de
-	ld	l,e
-	ld	h,d
-} by {
-	ld	l,e
-	ld	h,d
-	; peephole 24 incremented in hl instead of de.
-	inc	hl
-} if notUsed('de')
-
-replace restart {
-	ld	c,l
-	ld	b,h
-	ld	a,#%1
-	ld	(bc),a
-} by {
-	ld	c,l
-	ld	b,h
-	ld	(hl),#%1
-	; peephole 25 loaded #%1 into (hl) instead of (bc).
-} if notUsed('a')
-
-replace restart {
-	ex	de, hl
-	push	de
-} by {
-	; peephole 26 pushed hl directly instead of going through de.
-	push	hl
-} if notUsed('de'), notUsed('hl')
-
-replace restart {
-	ld	l,%1
-	ld	h,d
-	push	hl
-} by {
-	; peephole 27 pushed de instead of hl removing a load.
-	ld	e,%1
-	push	de
-} if notUsed('hl'), notUsed('e')
-
-replace restart {
-	ex	de, hl
-	push	bc
-	push	de
-} by {
-	; peephole 28 pushed hl directly instead of going through de.
-	push	bc
-	push	hl
-} if notUsed('de'), notUsed('hl')
-
-replace restart {
-	ld	l,c
-	ld	h,b
-	push	hl
-} by {
-	; peephole 29 pushed bc directly instead of going through hl.
-	push	bc
-} if notUsed('hl')
-
-replace restart {
-	ld	l,%1
-	ld	h,b
-	push	hl
-} by {
-	; peephole 30 pushed bc instead of hl removing a load.
-	ld	c,%1
-	push	bc
-} if notUsed('hl'), notUsed('c')
-
-replace restart {
-	ld	c,l
-	ld	b,h
-	push	%1
-	push	bc
-} by {
-	; peephole 31 pushed hl directly instead of going through bc.
-	push	%1
-	push	hl
-} if notUsed('bc'), notSame(%1 'bc')
-
-replace restart {
-	pop	de
-	ld	l, e
-	ld	h, d
-} by {
-	; peephole 32 popped hl directly instead of going through de.
-	pop	hl
-} if notUsed('de')
-
-replace restart {
-	pop	bc
-	ld	l, c
-	ld	h, b
-} by {
-	; peephole 33 popped hl directly instead of going through bc.
-	pop	hl
-} if notUsed('bc')
-
-replace restart {
-	ld	%1 (ix), %2
-	ld	%3, %1 (ix)
-} by {
-	; peephole 34 loaded %3 from %2 instead of going through %1 (ix).
-	ld	%1 (ix), %2
-	ld	%3, %2
-} if canAssign(%3 %2)
-// Don't need to check for volatile, since ix is used for the stack.
-
-replace restart {
-	ld	%1 (ix), a
-	push	de
-	ld	%2, %1 (ix)
-} by {
-	ld	%1 (ix), a
-	push	de
-	; peephole 34a loaded %2 from a instead of %1 (ix)
-	ld	%2, a
-} if canAssign(%2 'a')
-
-replace restart {
-	push	af
-	inc	sp
-	ld	a,e
-	push	af
-	inc	sp
-} by {
-	; peephole 35 pushed de instead of pushing a twice.
-	ld	d,a
-	push	de
-} if notUsed('d'), notUsed('a')
-
-replace restart {
-	push	af
-	inc	sp
-	ld	a,#%1
-	push	af
-	inc	sp
-} by {
-	; peephole 36 pushed de instead of pushing a twice.
-	ld	d,a
-	ld	e,#%1
-	push	de
-} if notUsed('de')
-
-replace restart {
-	push	af
-	inc	sp
-	ld	a,#%1
-	push	af
-	inc	sp
-} by {
-	; peephole 37 pushed bc instead of pushing a twice.
-	ld	b,a
-	ld	c,#%1
-	push	bc
-} if notUsed('bc')
-
-replace restart {
-	push	bc
-	inc	sp
-	push	de
-	inc	sp
-} by {
-	ld	c, d
-	; peephole 37a combined pushing of b and d.
-	push	bc
-} if notUsed('c')
-
-replace restart {
-	push	bc
-	inc	sp
-	ld	a, c
-	push	af
-	inc	sp
-} by {
-	push	bc
-	ld	a, c
-	; peephole 38 simplified pushing bc.
-}
-
-replace restart {
-	push	de
-	inc	sp
-	ld	a, #%1
-	push	af
-	inc	sp
-} by {
-	ld	e, #%1
-	push	de
-	; peephole 39 simplified pushing de.
-} if notUsed('e')
-
-replace restart {
-	ld	a,#%1
-	ld	d,a
-} by {
-	; peephole 40 loaded #%1 into d directly instead of going through a.
-	ld	d,#%1
-} if notUsed('a')
-
-replace restart {
-	ld	%1,a
-	ld	%2,%1
-} by {
-	; peephole 41 loaded %2 from a directly instead of going through %1.
-	ld	%2,a
-} if notUsed(%1)
-
-replace restart {
-	ld	a,%1 (ix)
-	push	af
-	inc	sp
-	ld	a,%2 (ix)
-	push	af
-	inc	sp
-} by {
-	; peephole 42 pushed %1 (ix), %2(ix) through hl instead of af.
-	ld	h,%1 (ix)
-	ld	l,%2 (ix)
-	push	hl
-} if notUsed('a'), notUsed('hl')
-
-replace restart {
-	ld	c, l
-	ld	b, h
-	push	bc
-} by {
-	; peephole 43 pushed hl instead of bc.
-	push	hl
-} if notUsed('bc')
-
-replace restart {
-	pop	%1
-	push	%1
-} by {
-	; peephole 44 eleminated dead pop/push pair.
-} if notUsed(%1)
-
-replace restart {
-	ld	iy,#%1
-	or	a,%2 (iy)
-} by {
-	; peephole 45 used hl instead of iy.
-	ld	hl,#%1 + %2
-	or	a,(hl)
-} if notUsed('iy'), notUsed('hl')
-
-replace restart {
-	ld	iy,#%1
-	ld	%2,%3 (iy)
-} by {
-	; peephole 46 used hl instead of iy.
-	ld	hl,#%1 + %3
-	ld	%2, (hl)
-} if notUsed('iy'), notUsed('hl')
-
-replace restart {
-	ld	iy,#%1
-	ld	h,%3 (iy)
-} by {
-	; peephole 46a used hl instead of iy.
-	ld	hl,#%1 + %3
-	ld	h, (hl)
-} if notUsed('iy'), notUsed('l')
-
-replace restart {
-	ld	iy,#%1
-	ld	%2 (iy), %3
-} by {
-	; peephole 46b used hl instead of iy.
-	ld	hl,#%1 + %2
-	ld	(hl), %3
-} if notUsed('iy'), notUsed('hl'), notSame(%3 'h' 'l')
-
-replace restart {
-	ld	iy,#%1
-	ld	%2,0 (iy)
-	ld	%3,1 (iy)
-} by {
-	; peephole 47 used hl instead of iy.
-	ld	hl,#%1
-	ld	%2, (hl)
-	inc	hl
-	ld	%3, (hl)
-} if notUsed('iy'), notUsed('hl'), operandsNotRelated(%2 'hl')
-
-replace restart {
-	ld	iy,#%1
-	ld	%2 (iy),%3
-	ld	l,%2 (iy)
-} by {
-	; peephole 48 used hl instead of iy.
-	ld	hl,#%1 + %2
-	ld	(hl),%3
-	ld	l,(hl)
-} if notUsed('iy'), notUsed('h')
-
-replace restart {
-	ld	iy,#%1
-	ld	%2 (%3), %4
-} by {
-	; peephole 49 used hl instead of iy.
-	ld	hl,#%1 + %2
-	ld	(hl), %4
-} if notUsed('iy'), notUsed('hl'), operandsNotRelated(%4 'hl')
-
-replace restart {
-	ld	iy,#%1
-	bit	%2,%3 (iy)
-} by {
-	; peephole 49a used hl instead of iy.
-	ld	hl,#%1+%3
-	bit	%2, (hl)
-} if notUsed('iy'), notUsed('hl')
-
-replace restart {
-	ld	iy, #%1
-	add	iy, sp
-	ld	%2, %3 (iy)
-} by {
-	; peephole 49b used hl instead of iy.
-	ld	hl, #%1+%3
-	add	hl, sp
-	ld	%2, (hl)
-} if notUsed('iy'), notUsed('hl')
-
-replace restart {
-	ld	iy, #%1
-	add	iy, sp
-	ld	%2, 0 (iy)
-	ld	%3, 1 (iy)
-} by {
-	; peephole 49c used hl instead of iy.
-	ld	hl, #%1
-	add	hl, sp
-	ld	%2, (hl)
-	inc	hl
-	ld	%3, (hl)
-} if notUsed('iy'), notUsed('hl')
-
-replace restart {
-	ld	iy, #%1
-	add	iy, sp
-	ld	l, 0 (iy)
-	ld	h, 1 (iy)
-} by {
-	; peephole 49d used hl instead of iy.
-	ld	hl, #%1
-	add	hl, sp
-	ld	a, (hl)
-	inc	hl
-	ld	h, (hl)
-	ld	l, a
-} if notUsed('iy'), notUsed('a')
-
-replace restart {
-	ld	iy, #%1
-	add	iy, sp
-	ld	0 (iy), #%2
-	ld	1 (iy), #%3
-} by {
-	; peephole 49e used hl instead of iy.
-	ld	hl, #%1
-	add	hl, sp
-	ld	(hl), #%2
-	inc	hl
-	ld	(hl), #%3
-} if notUsed('iy'), notUsed('hl')
-
-replace restart {
-	ld	iy, #%1
-	ld	a, 1 (iy)
-	or	a, 0 (iy)
-} by {
-	ld	hl, #%1
-	ld	a, (hl)
-	inc	hl
-	or	a, (hl)
-	; peephole 49f used hl instead of iy.
-} if notUsed('iy'), notUsed('hl')
-
-replace restart {
 	ld	iy, #%1
-	add	iy, sp
 	ld	a, 1 (iy)
 	or	a, 0 (iy)
 } by {
 	ld	hl, #%1
-	add	hl, sp
 	ld	a, (hl)
 	inc	hl
 	or	a, (hl)
-	; peephole 49f' used hl instead of iy.
-} if notUsed('iy'), notUsed('hl')
-
-replace restart {
-	ld	iy, #%1
-	add	iy, sp
-	bit	%2, %3 (iy)
-} by {
-	ld	hl, #%1+%3
-	add	hl, sp
-	bit	%2, (hl)
-	; peephole 49g used hl instead of iy.
-} if notUsed('iy'), notUsed('hl')
-
-replace restart {
-	ld	iy, #%1
-	add	iy, sp
-	or	a, %2 (iy)
-} by {
-	ld	hl, #%1+%2
-	add	hl, sp
-	or	a, (hl)
-	; peephole 49h used hl instead of iy.
+	; peephole 65rab used hl instead of iy.
 } if notUsed('iy'), notUsed('hl')
 
 replace restart {
-	ld	%1,(hl)
-	or	a,%1
-} by {
-	or	a,(hl)
-	; peephole 50 used (hl) directly instead of going through %1.
-} if notUsed(%1), notSame(%1 'a')
-
-replace restart {
-	ld	c,l
-	ld	b,h
-	inc	bc
-} by {
-	; peephole 51 incremented in hl instead of bc.
-	inc	hl
-	ld	c,l
-	ld	b,h
-} if notUsed('hl')
-
-replace restart {
-	ld	a,%1 (%2)
-	bit	%3,a
-} by {
-	; peephole 52 tested bit of %1 (%2) directly instead of going through a.
-	bit	%3,%1 (%2)
-} if notUsed('a')
-
-replace restart {
-	ld	a,%1
-	bit	%2,a
-} by {
-	; peephole 53 tested bit %2 of %1 directly instead of going through a.
-	bit	%2,%1
-} if notUsed('a'), canAssign(%1 'b')
-
-replace restart {
-	ld	a, %1
-	set	%2, a
-	ld	%1, a
-} by {
-	; peephole 54 set bit %2 of %1 directly instead of going through a.
-	set	%2, %1
-	ld	a, %1
-} if canAssign(%1 'b')
-// canAssign(%1 'b') is true, iff set b, %1 is possible.
-
-replace restart {
-	ld	a, %1 (%2)
-	set	%3, a
-	ld	%1 (%2), a
-} by {
-	; peephole 55 set bit %3 of %1 (%2) directly instead of going through a.
-	set	%3, %1 (%2)
-	ld	a, %1 (%2)
-}
-
-replace restart {
-	ld	a, %1
-	res	%2, a
-	ld	%1, a
-} by {
-	; peephole 56 reset bit %2 of %1 directly instead of going through a.
-	res	%2, %1
-	ld	a, %1
-} if canAssign(%1 'b')
-// canAssign(%1 'b') is true, iff set b, %1 is possible.
-
-replace restart {
-	ld	a, %1 (%2)
-	res	%3, a
-	ld	%1 (%2), a
-} by {
-	; peephole 57 reset bit %3 of %1 (%2) directly instead of going through a.
-	res	%3, %1 (%2)
-	ld	a, %1 (%2)
-}
-
-replace restart {
-	ld	c, %1 (%2)
-	ld	b, %3 (%4)
-	ld	l,c
-	ld	h,b
-} by {
-	; peephole 58 stored %1 (%2) %3 (%4) into hl directly instead of going through bc.
-	ld	l, %1 (%2)
-	ld	h, %3 (%4)
-} if notUsed('bc')
-
-replace restart {
-	ld	c, %1
-	ld	b, %2
-	ld	l,c
-	ld	h,b
-} by {
-	; peephole 59 stored %2%1 into hl directly instead of going through bc.
-	ld	l, %1
-	ld	h, %2
-} if notUsed('bc'), operandsNotRelated(%2 'l')
-
-replace restart {
-	jp	NC,%1
-	jp	%2
-%1:
-} by {
-	jp	C,%2
-	; peephole 60 removed jp by using inverse jump logic
-%1:
-} if labelRefCountChange(%1 -1)
-
-replace restart {
-	jp	C,%1
-	jp	%2
-%1:
-} by {
-	jp	NC,%2
-	; peephole 61 removed jp by using inverse jump logic
-%1:
-} if labelRefCountChange(%1 -1)
-
-replace restart {
-	jp	NZ,%1
-	jp	%2
-%1:
-} by {
-	jp	Z,%2
-	; peephole 62 removed jp by using inverse jump logic
-%1:
-} if labelRefCountChange(%1 -1)
-
-replace restart {
-	jp	Z,%1
-	jp	%2
-%1:
-} by {
-	jp	NZ,%2
-	; peephole 63 removed jp by using inverse jump logic
-%1:
-} if labelRefCountChange(%1 -1)
-
-replace restart {
-	jp	%5
-} by {
-	jp	%6
-	; peephole 64 jumped to %6 directly instead of via %5.
-} if labelIsUncondJump(), notSame(%5 %6), labelRefCountChange(%5 -1), labelRefCountChange(%6 +1)
-
-replace restart {
-	jp	%1,%5
-} by {
-	jp	%1,%6
-	; peephole 65 jumped to %6 directly instead of via %5.
-} if labelIsUncondJump(), notSame(%5 %6), labelRefCountChange(%5 -1), labelRefCountChange(%6 +1)
-
-replace restart {
-	jp	%1
-%2:
-%1:
-} by {
-   ; peephole 65a eliminated jump.
-%2:
-%1:
-} if labelRefCountChange(%1 -1)
-
-// A peephole that makes the code longer. Let's hope it's worth it in speed gain and further optimization potential.
-replace restart {
-	ld	a,#0x00
-%1:
-	bit	%2,a
-	jp	Z,%3
-} by {
-	ld	a,#0x00
-	jp	%3
-	; peephole 65a jumped directly to %3 instead of testing a first.
-%1:
-	bit	%2,a
-	jp	Z,%3
-} if labelRefCountChange(%3 +1)
-
-replace restart {
-	ld	%1, %2
-	jp	%3
-	jp	%4
-} by {
-	ld	%1, %2
-	jp	%3
-	; peephole 65b removed unreachable jump to %3.
-}
-
-replace restart {
-	ld	%1, %2
-	jp	%3
-%3:
-} by {
-	ld	%1, %2
-%3:
-	; peephole 65c removed redundant jump to %3.
-} if labelRefCountChange(%3 -1)
-
-replace restart {
-	ld	%1, #0x01
-	bit	0, %1
-	jp	Z, %2
-} by {
-	ld	%1, #0x01
-	; peephole 65d removed impossible jump to %2.
-} if labelRefCountChange(%2 -1)
-	
-replace restart {
-	xor	a,a
-	ld	a,#0x00
-} by {
-	xor	a,a
-	; peephole 66 removed redundant load of 0 into a.
-}
-
-replace {
-	ld	e,#0x%1
-	ld	d,#0x%2
-} by {
-	ld	de,#0x%2%1
-	; peephole 67 combined constant loads into register pair.
-}
-
-replace {
-	ld	l,#0x%1
-	ld	h,#0x%2
-} by {
-	ld	hl,#0x%2%1
-	; peephole 68 combined constant loads into register pair.
-}
-
-replace {
-	ld	c,#0x%1
-	ld	b,#0x%2
-} by {
-	ld	bc,#0x%2%1
-	; peephole 69 combined constant loads into register pair.
-}
-
-replace restart {
-	ld	%1,a
-	ld	a,%1
-} by {
-	ld	%1,a
-	; peephole 70 removed redundant load from %1 into a.
-} if notVolatile(%1)
-// This gives many false negatives and without the test no problems are encountered in the regression tests
-// Maybe we can try this after 2.7.0 release
-
-replace restart {
-	ld	a,%1
-	ld	%1,a
-} by {
-	ld	a,%1
-	; peephole 71 removed redundant load from a into %1.
-} if notVolatile(%1)
-// This gives many false negatives and without the test no problems are encountered in the regression tests
-// Maybe we can try this after 2.7.0 release
-
-replace restart {
-	ld	%2 (ix), %1
-	ld	%1, %2 (ix)
-} by {
-	ld	%2 (ix), %1
-	; peephole 71a removed redundant load of %1 from %2 (ix)
-}
-
-replace restart {
-	ld	%1,a
-	ld	a,%2
-	or	a,%1
-} by {
-	ld	%1,a
-	or	a,%2
-	; peephole 72 removed load by reordering or arguments.
-} if notVolatile(%1), canAssign('b' %2)
-// canAssign('b' %2) is true, iff or a,%2 is possible.
-
-replace restart {
-	or	a,%1
-	or	a,a
-} by {
-	or	a,%1
-	; peephole 73 removed redundant or after or.
-}
-
-replace restart {
-	or	a,%1 (%2)
-	or	a,a
-} by {
-	or	a,%1 (%2)
-	; peephole 74 removed redundant or after or.
-}
-
-replace restart {
-	and	a,%1
-	or	a,a
-} by {
-	and	a,%1
-	; peephole 75 removed redundant or after and.
-}
-
-replace restart {
-	xor	a,%1
-	or	a,a
-} by {
-	xor	a,%1
-	; peephole 76 removed redundant or after xor.
-}
-
-replace restart {
-	xor	a,%1 (%2)
-	or	a,a
-} by {
-	xor	a,%1 (%2)
-	; peephole 77 removed redundant or after xor.
-}
-
-replace {
-	ld	%1,%2
-	ld	a,%2
-} by {
-	ld	a,%2
-	ld	%1,a
-	; peephole 78 loaded value in a first and used it next
-} if notVolatile(%1 %2), canAssign(%1 'a'), operandsNotRelated(%1 %2)
-
-replace restart {
-	ld	%1,%2
-	ld	%3,%4
-	ld	%2,%1
-	ld	%4,%3
-} by {
-	ld	%1,%2
-	ld	%3,%4
-	; peephole 79 removed redundant load from %3%1 into %4%2
-} if notVolatile(%1 %2 %3 %4)
-
-replace restart {
-	push	de
-	inc	sp
-	ld	a,e
-	push	af
-	inc	sp
-} by {
-	push	de
-	; peephole 80 pushed de
-} if notUsed('a')
-
-replace restart {
-	ld	iy,%1
-	add	iy,sp
-	ld	sp,iy
-} by {
-	ld	hl,%1
-	add	hl,sp
-	ld	sp,hl
-	; peephole 81 fixed stack using hl instead of iy.
-} if notUsed('hl'), notUsed('iy')
-
-replace restart {
-	ld	a,%1
-	sub	a,%2
-	jp	%3,%4
-	ld	a,%1
-} by {
-	ld	a,%1
-	cp	a,%2
-	jp	%3,%4
-	; peephole 82 removed load by replacing sub with cp
-	assert	a=%1
-} if notVolatile(%1), notUsedFrom(%4 'a')
-
-replace restart {
-	assert	a=%1
-	sub	a,%2
-	jp	%3,%4
-	ld	a,%1
-} by {
-	cp	a,%2
-	jp	%3,%4
-	; peephole 83 removed load by replacing sub with cp
-	assert	a=%1
-} if notUsedFrom(%4 'a')
-
-replace restart {
-	assert	a=%1
-} by {
-}
-
-replace restart {
-	sub	a,#0xFF
-	jp	Z,%1
-} by {
-	inc	a
-	; peephole 84 replaced sub a,#0xFF by inc a.
-	jp	Z,%1
-}
-
-replace restart {
-	sub	a,#0xFF
-	jp	NZ,%1
-} by {
-	inc	a
-	; peephole 85 replaced sub a,#0xFF by inc a.
-	jp	NZ,%1
-}
-
-replace restart {
-	rlca
-	ld	a,#0x00
-	rla
-} by {
-	rlca
-	and	a,#0x01
-	; peephole 86 replaced zero load, rla by and since rlca writes the same value to carry bit and least significant bit.
-}
-
-replace restart {
-	ld	%1,%2
-	push	%1
-	pop	%4
-	ld	%1,%3
-} by {
-	ld	%4,%2
-	; peephole 87 moved %2 directly into de instead of going through %1.
-	ld	%1,%3
-}
-
-replace restart {
-	add	a,#0x00
-	ld	%2,a
-	ld	a,%3
-	adc	a,%4
-} by {
-	; peephole 88 removed lower part of multibyte addition.
-	ld	%2,a
-	ld	a,%3
-	add	a,%4
-}
-
-replace restart {
-	ld	a, l
-	add	a, #0x%1
-	ld	e, a
-	ld	a, h
-	adc	a, #0x%2
-	ld	d, a
-} by {
-	ld	de, #0x%2%1
-	add	hl, de
-	; peephole 89 used 16-bit addition.
-	ld	e, l
-	ld	d, h
-	ld	a, h
-} if notUsed('hl')
-
-replace restart {
-	ld	a, l
-	add	a, #0x%1
-	ld	c, a
-	ld	a, h
-	adc	a, #0x%2
-	ld	b, a
-} by {
-	ld	bc, #0x%2%1
-	add	hl,bc
-	; peephole 90 used 16-bit addition.
-	ld	c, l
-	ld	b, h
-	ld	a, h
-} if notUsed('hl')
-
-replace restart {
-	ld	%1,a
-	ld	a,%2
-	add	a,%1
-} by {
-	; peephole 91 removed loads by exploiting commutativity of addition.
-	add	a,%2
-} if notVolatile(%1), notUsed(%1), canAssign('b' %2)
-// canAssign('b' %2) is true, iff add a,%2 is possible.
-
-replace restart {
-	ld	%1 (ix),a
-	ld	a,#%2
-	add	a,%1 (ix)
-} by {
-	ld	%1 (ix),a
-	; peephole 92 removed loads by exploiting commutativity of addition.
-	add	a,#%2
-}
-// Don't need to check for volatile, since ix is used to access the stack.
-
-replace restart {
-	ld	l,%1 (ix)
-	ld	h,%2 (ix)
-	ld	a,(hl)
-	inc	a
-	ld	l,%1 (ix)
-	ld	h,%2 (ix)
-	ld	(hl),a
-} by {
-	ld	l,%1 (ix)
-	ld	h,%2 (ix)
-	inc	(hl)
-	; peephole 93 incremented in (hl) instead of going through a.
-} if notUsed('a')
-
-replace restart {
-	ld	%1, %2 (%3)
-	inc	%1
-	ld	%2 (%3), %1
-} by {
-	inc	%2 (%3)
-	ld	%1, %2 (%3)
-	; peephole 93a incremented in %2 (%3) instead of going through %1.
-} if notSame(%3 'sp')
-
-replace restart {
-	ld	%1,a
-	ld	a,%2
-	add	a,%1
-} by {
-	ld	%1, a
-	; peephole 94 removed load by exploiting commutativity of addition.
-	add	a,%2
-} if notSame(%2 '(bc)' '(de)'), canAssign('b' %2)
-// canAssign('b' %2) is true, iff add a,%2 is possible.
-
-replace restart {
-	ld	c,l
-	ld	b,h
-	ld	hl,#%1
-	add	hl,bc
-} by {
-	; peephole 95 removed loads by exploiting commutativity of addition.
-	ld	bc,#%1
-	add	hl,bc
-} if notUsed('bc')
-
-replace restart {
-	ld	hl,#%1
-	add	hl,%2
-	ld	bc,#%4
-	add	hl,bc
-} by {
-	; peephole 96 removed loads by exploiting commutativity of addition.
-	ld	hl,#%1 + %4
-	add	hl,%2
-} if notUsed('bc')
-
-replace restart {
-	ld	c,e
-	ld	b,d
-	ld	hl,#%1
-	add	hl,bc
+	ld	%1,(hl)
+	or	a,%1
 } by {
-	; peephole 97 removed loads by exploiting commutativity of addition.
-	ld	hl,#%1
-	add	hl,de
-} if notUsed('bc')
+	or	a,(hl)
+	; peephole 68rab used (hl) directly instead of going through %1.
+} if notUsed(%1), notSame(%1 'a')
 
 replace restart {
 	or	a,%1
-	jp	NZ,%2
-	ld	%3,#0x00
+	or	a,a
 } by {
 	or	a,%1
-	jp	NZ,%2
-	ld	%3,a
-	; peephole 98 replaced constant #0x00 by a (which has just been tested to be #0x00).
+	; peephole 73 removed redundant or after or.
 }
 
 replace restart {
-	and	a,%1
-	jp	NZ,%2
-	ld	%3,#0x00
+	or	a,%1 (%2)
+	or	a,a
 } by {
-	and	a,%1
-	jp	NZ,%2
-	ld	%3,a
-	; peephole 99 replaced constant #0x00 by a (which has just been tested to be #0x00).
+	or	a,%1 (%2)
+	; peephole 74 removed redundant or after or.
 }
 
 replace restart {
-	sub	a,%1
-	jp	NZ,%2
-	ld	%3,#0x00
+	and	a,%1
+	or	a,a
 } by {
-	sub	a,%1
-	jp	NZ,%2
-	ld	%3,a
-	; peephole 100 replaced constant #0x00 by a (which has just been tested to be #0x00).
-}
-
-replace restart {
-	inc	a
-	jp	NZ,%1
-	ld	%2,#0x00
-} by {
-	inc	a
-	jp	NZ,%1
-	ld	%2,a
-	; peephole 101 replaced constant #0x00 by a (which has just been tested to be #0x00).
+	and	a,%1
+	; peephole 75 removed redundant or after and.
 }
 
 replace restart {
-	dec	a
-	jp	NZ,%1
-	ld	%2,#0x00
-} by {
-	dec	a
-	jp	NZ,%1
-	ld	%2,a
-	; peephole 102 replaced constant #0x00 by a (which has just been tested to be #0x00).
+	xor	a,%1
+	or	a,a
+} by {
+	xor	a,%1
+	; peephole 76 removed redundant or after xor.
 }
 
 replace restart {
-	or	a,%1
-	jp	NZ,%2
-	ld	a,%3
+	xor	a,%1 (%2)
 	or	a,a
 } by {
-	or	a,%1
-	jp	NZ,%2
-	or	a,%3
-	; peephole 103 shortened or using a (which has just been tested to be #0x00).
-} if canAssign('b' %3)
-// canAssign('b' %2) is true, iff or a,%2 is possible.
+	xor	a,%1 (%2)
+	; peephole 77 removed redundant or after xor.
+}
 
 replace restart {
-	sub	a,%1
-	jp	NZ,%2
-	ld	a,%3
-	or	a,a
+	sbc	hl, %1
+	ld	a, h
+	or	a, l
+	jp	NZ, %2
 } by {
-	sub	a,%1
-	jp	NZ,%2
-	or	a,%3
-	; peephole 104 shortened or using a (which has just been tested to be #0x00).
-} if canAssign('b' %3)
-// canAssign('b' %2) is true, iff or a,%2 is possible.
+	sbc	hl, %1
+	jp	NZ, %2
+	; common peephole 102c removed redundant or after sbc.
+}
 
 replace restart {
-	or	a,%1
-	jp	NZ,%2
-	push	%3
-	ld	%4,#0x00
+	sbc	hl, %1
+	ld	a, h
+	or	a, l
+	jp	Z, %2
 } by {
-	or	a,%1
-	jp	NZ,%2
-	push	%3
-	ld	%4,a
-	; peephole 105 replaced constant #0x00 by a (which has just been tested to be #0x00).
+	sbc	hl, %1
+	jp	Z, %2
+	; common peephole 102d removed redundant or after sbc.
 }
 
 replace restart {
-	ld	hl,#%1
-	add	hl,%2
-	inc	hl
+	ld	%1, %2 (%3)
+	inc	%1
+	ld	%2 (%3), %1
 } by {
-	ld	hl,#%1+1
-	add	hl,%2
-	; peephole 107 moved increment of hl to constant.
-}
+	inc	%2 (%3)
+	ld	%1, %2 (%3)
+	; peephole 93a incremented in %2 (%3) instead of going through %1.
+} if notSame(%3 'sp')
 
 replace restart {
 	inc	hl
@@ -1345,7 +119,7 @@
 } by {
 	ld	%1,#%2+1
 	add	hl,%1
-	; peephole 108 moved increment of hl to constant.
+	; peephole 129rab moved increment of hl to constant.
 } if notUsed(%1)
 
 replace restart {
@@ -1355,171 +129,18 @@
 } by {
 	ld	%1,#%2-1
 	add	hl,%1
-	; peephole 109 moved decrement of hl to constant.
+	; peephole 129rab' moved decrement of hl to constant.
 } if notUsed(%1)
 
 replace restart {
-	inc	hl
-	inc	hl
-	inc	hl
-	ld	hl, (hl)
-} by {
-	; peephole 109a moved increment of hl to offset.
-	ld	hl, 3 (hl)
-}
-
-replace restart {
-	inc	hl
-	inc	hl
-	ld	hl, (hl)
-} by {
-	; peephole 109b moved increment of hl to offset.
-	ld	hl, 2 (hl)
-}
-
-replace restart {
-	inc	hl
-	ld	hl, (hl)
-} by {
-	; peephole 109c moved increment of hl to offset.
-	ld	hl, 1 (hl)
-}
-
-replace restart {
 	inc	iy
 	ld	%1, %2 (iy)
 } by {
 	ld	%1, %2+1 (iy)
-	; peephole 110 moved increment of iy to offset.
+	; peephole 129rab'' moved increment of iy to offset.
 } if notUsed('iy')
 
 replace restart {
-	push	hl
-	pop	iy
-	pop	hl
-	inc	iy
-} by {
-	inc	hl
-	push	hl
-	pop	iy
-	pop	hl
-	; peephole 111 incremented in hl instead of iy.
-}
-
-replace restart {
-	push	hl
-	pop	iy
-	inc	iy
-} by {
-	inc	hl
-	push	hl
-	pop	iy
-	; peephole 111a incremented in hl instead of iy.
-} if notUsed('hl')
-
-replace restart {
-	push	bc
-	pop	iy
-	inc	iy
-} by {
-	inc	bc
-	push	bc
-	pop	iy
-	; peephole 111b incremented in bc instead of iy.
-} if notUsed('bc')
-
-replace restart {
-	push	de
-	pop	iy
-	inc	iy
-} by {
-	inc	de
-	push	de
-	pop	iy
-	; peephole 111c incremented in de instead of iy.
-} if notUsed('de')
-
-replace restart {
-	ld	hl,%1
-	add	hl,%2
-	push	hl
-	pop	iy
-} by {
-	ld	iy,%1
-	add	iy,%2
-	; peephole 111b added in iy instead of hl.
-} if notUsed('hl'), notSame(%2 'hl')
-
-replace restart {
-	pop	af
-	ld	sp,%1
-} by {
-	; peephole 112 removed redundant pop af.
-	ld	sp,%1
-} if notUsed('a')
-
-replace restart {
-	inc	sp
-	ld	sp,%1
-} by {
-	; peephole 113 removed redundant inc sp.
-	ld	sp,%1
-} if notUsed('a')
-
-replace restart {
-	call    %1
-	ret
-} by {
-	jp  %1
-	; peephole 114 replaced call at end of function by jump (tail call optimization).
-} if symmParmStack(%1)
-
-// Callee saves ix.
-replace restart {
-	call	%1
-	pop	ix
-	ret
-} by {
-	pop	ix
-	jp	%1
-	; peephole115 replaced call at end of function by jump moving call beyond pop ix (tail call optimization).
-} if symmParmStack(%1)
-
-replace restart {
-	ld	%1,#%2
-	ld	%3,%4
-	ld	%1,#%2
-} by {
-	ld	%1,#%2
-	ld	%3,%4
-	; peephole 116 removed load of #%2 into %1 since it's still there.
-} if notVolatile(%1), operandsNotRelated(%3 %1)
-
-replace restart {
-	ld	hl,#%1
-	ld	de,#%1
-} by {
-	; peephole 117 used #%1 from hl for load into de.
-	ld	hl,#%1
-	ld	e,l
-	ld	d,h
-}
-
-replace restart {
-	ld	%1 (ix),l
-	ld	%2 (ix),h
-	ld	%3,%1 (ix)
-	ld	%4,%2 (ix)
-} by {	
-	ld	%1 (ix),l
-	ld	%2 (ix),h
-	; peephole 118 used hl instead of %2 (ix), %1 (ix) to load %4%3.
-	ld	%3,l
-	ld	%4,h
-} if operandsNotRelated('h' %3)
-// Don't check for volatile since ix points to the stack.
-
-replace restart {
 	ld	%1, a
 	ld	a, %2 (%3)
 	adc	a, #%4
@@ -1528,7 +149,7 @@
 	ld	%6, a
 	ld	a, %2 (%3)
 	adc	a, #%4
-	; peephole 119 loaded %6 from a directly instead of going through %1.
+	; peephole 138rab loaded %6 from a directly instead of going through %1.
 } if notUsed(%1)
 
 replace restart {
@@ -1542,177 +163,15 @@
 	ld	a, %2 (%3)
 	adc	a, #%4
 	ld	%5, a
-	; peephole 120 loaded %6 from a directly instead of going through %1.
+	; peephole 138rab' loaded %6 from a directly instead of going through %1.
 } if notUsed(%1), notSame(%5 %1), notSame(%5 '(hl)' '(de)' '(bc)'), notSame(%5 %6), notSame(%6 '(hl)' '(de)' '(bc)'), notSame(%5 'a'), notSame(%6 'a')
 
 replace restart {
-	ld	%1, a
-	ld	a, #%2
-	adc	a, #%3
-	ld	%5, a
-	ld	%6, %1
-} by {
-	ld	%6, a
-	ld	a, #%2
-	adc	a, #%3
-	ld	%5, a
-	; peephole 121 loaded %6 from a directly instead of going through %1.
-} if notUsed(%1), notSame(%5 %1), notSame(%5 %6 '(hl)' '(de)' '(bc)'), notSame(%6 'a')
-
-replace restart {
-	ld	hl, #%1
-	add	hl, %2
-	ex	de, hl
-	ld	hl, #%3
-	add	hl, de
-} by {
-	ld	hl, #%1+%3
-	add	hl, %2
-	; peephole 122 removed addition and loads exploiting commutativity of addition.
-} if notUsed('de')
-
-replace restart {
-	ld	%1,l
-	ld	%2,h
-	ex	de,hl
-	ld	(hl),%1
-	inc	hl
-	ld	(hl),%2
-} by {
-	ld	%1,l
-	ex	de,hl
-	; peephole 122a used de instead of going through %1%2.
-	ld	(hl),e
-	inc	hl
-	ld	(hl),d
-} if notUsed(%2), notSame(%1 'l' 'h' 'e' 'd'), notSame(%2 'l' 'h' 'e' 'd')
-	
-replace restart {
-	ld	e, l
-	ld	d, h
-	ld	hl, #0x0001
-	add	hl, de
-} by {
-	ld	e, l
-	ld	d, h
-	inc	hl
-	; peephole 123 replaced addition by increment.
-}
-
-replace restart {	
-	ld      sp,hl
-	ld      hl,#0x0002
-	add     hl,sp
-} by {
-	ld	sp, hl
-	inc	hl
-	inc	hl
-	; peephole 124 replaced addition by increment.
-}
-
-replace restart {
-	ex	de, hl
-	ld	hl, #%1
-	add	hl, de
-} by {
-	; peephole 125 removed ex exploiting commutativity of addition.
-	ld	de, #%1
-	add	hl, de
-} if notUsed('de')
-
-replace restart {
-	ex	de, hl
-	push	bc
-	ex	de, hl
-} by {
-	push	bc
-	; peephole 126 canceled subsequent ex de, hl.
-}
-
-replace restart {
-	ld	hl, #%1
-	add	hl, %2
-	ex	de, hl
-	inc	de
-} by {
-	ld	hl, #%1+1
-	; peephole 127 moved increment to constant.
-	add	hl, %2
-	ex	de, hl
-} if notUsed('hl')
-
-replace restart {
-	ld	a,#0x01
-	jp	%1
-%2:
-	xor	a,a
-%1:
-	sub	a,#0x01
-	ld	a,#0x00
-	rla
-} by {
-	xor	a,a
-	jp	%1
-%2:
-	ld	a,#0x01
-%1:
-	; peephole 128 removed negation.
-} if labelRefCount(%1 1)
-
-replace restart {
-	and	a,#0x01
-	sub	a,#0x01
-	ld	a,#0x00
-	rla
-} by {
-	and	a,#0x01
-	xor	a,#0x01
-	; peephole 129 used xor for negation.
-}
-
-replace restart {
-	or	a,a
-	sub	a,#%1
-} by {
-	; peephole 130 removed redundant or.
-	sub	a,#%1
-}
-
-replace restart {
-	ld	a,#0x00
-	rla
-	sub	a,#0x01
-	ld	a,#0x00
-	rla
-} by {
-	ld	a,#0x00
-	ccf
-	; peephole 131 moved negation from bit 0 to carry flag.
-	rla
-}
-
-replace restart {
-	ld	a, #<(%1)
-	add	a, l
-	ld	l, a
-	ld	a, #>(%1)
-	adc	a, h
-	ld	h, a
-	push	bc
-} by {
-	push	bc
-	ld	bc, #%1
-	add	hl, bc
-	; peephole 132 used 16 bit addition by moving push bc
-	ld	a, h
-} if notUsed('bc')
-
-replace restart {
 	pop	af
 	push	hl
 } by {
-	; peephole 133 used ex to move hl onto the stack.
-	ld	0(sp),hl
+	; peephole 142rab used 0(sp) to move hl onto the stack.
+	ld	0(sp), hl
 } if notUsed('a'), notUsed('hl')
 
 replace restart {
@@ -1721,8 +180,8 @@
 	push	hl
 } by {
 	ld	hl, #%1
-	; peephole 134 used 0(sp) to move hl onto the stack.
-	ld	0(sp),hl
+	; peephole 143rab used 0(sp) to move hl onto the stack.
+	ld	0(sp), hl
 } if notUsed('a'), notUsed('hl')
 
 replace restart {
@@ -1733,8 +192,8 @@
 } by {
 	inc	sp
 	ld	hl,#%1
-	; peephole 135 used 0(sp) to move #%1 onto the stack.
-	ld	0(sp),hl
+	; peephole 145rab used 0(sp) to move #%1 onto the stack.
+	ld	0(sp), hl
 } if notUsed('a'), notUsed('hl')
 
 replace restart {
@@ -1744,44 +203,12 @@
 	inc	sp
 } by {
 	ld	h,#%1
-	ld	0(sp),hl
-	; peephole 136 used 0(sp) to move #%1 onto the stack.
+	ld	0(sp), hl
+	; peephole 146rab used 0(sp) to move #%1 onto the stack.
 	inc	sp
 } if notUsed('a'), notUsed('hl')
 
-replace restart {
-	ld	%1,#%2
-	ld	%3 (%1),a
-%4:
-	ld	%1,%5
-} by {
-	ld	(#%2 + %3),a
-	; peephole 137 directly used #%2 instead of going through %1 using indirect addressing.
-%4:
-	ld	%1,%5
-}
-
-replace restart {
-	pop	af
-	ld	%1,#%2
-	ld	%3 (%1),%4
-	ld	%1,#%5
-} by {
-	ld	a,%4
-	ld	(#%2 + %3),a
-	; peephole 138 used #%2 directly instead of going through %1 using indirect addressing.
-	pop	af
-	ld	%1,#%5
-} if notSame(%3 'a')
-
-replace restart {
-	ld	%1,a
-	bit	%2,%1
-} by {
-	bit	%2,a
-	; peephole 139 tested bit %2 of a directly instead of going through %1.
-} if notUsed(%1)
-
+// those are not in z80
 replace restart {
 	sbc	a,%1
 	bit	7,a
@@ -1810,546 +237,3 @@
 	dec %1
 	; peephole 141a removed redundant transfer and flag setting in a
 } if notUsed('a')
-
-replace restart {
-	ld	%1,a
-	or	a,a
-	jp	%3,%4
-	ld	a,%1
-} by {
-	ld	%1,a
-	or	a,a
-	jp	%3,%4
-	; peephole 142 used value still in a instead of reloading from %1.
-}
-
-replace {
-	jp	%5
-	ret
-} by {
-	jp	%5
-	; peephole 143 removed unused ret.
-}
-
-replace {
-	jp	%5
-	ld	sp,ix
-	pop	ix
-	ret
-} by {
-	jp	%5
-	; peephole 144 removed unused ret.
-}
-
-replace restart {
-	or	a,%1
-	jp	NZ,%2
-	xor	a,a
-	jp	%3
-} by {
-	or	a,%1
-	jp	NZ,%2
-	; peephole 145 removed redundant zeroing of a (which has just been tested to be #0x00).
-	jp	%3
-}
-
-replace restart {
-	dec	hl
-	inc	hl
-} by {
-	; peephole 145a removed inc hl / dec hl pair.
-}
-
-replace restart {
-	jp	Z, %2
-	ld	a, #%3
-	jp	%1
-%2:
-	ld	a, #%4
-%1:
-} by {
-	ld	a, #%3
-	jp	NZ, %1
-%2:
-	ld	a, #%4
-	; peephole 168z used double assignment in case of Z condition.
-%1:
-} if labelRefCountChange(%2 -1) 
-
-replace restart {
-	jp	NZ, %2
-	ld	a, #%3
-	jp	%1
-%2:
-	ld	a, #%4
-%1:
-} by {
-	ld	a, #%3
-	jp	Z, %1
-%2:
-	ld	a, #%4
-	; peephole 168nz used double assignment in case of NZ condition.
-%1:
-} if labelRefCountChange(%2 -1) 
-
-replace restart {
-	jp	Z, %2
-	ld	a, #%3
-	jp	%1
-%2:
-	xor	a, a
-%1:
-} by {
-	ld	a, #%3
-	jp	NZ, %1
-	; peephole 169xz used double assignment in case of Z condition.
-%2:
-	xor	a, a
-%1:
-} if labelRefCountChange(%2 -1)
-
-replace restart {
-	jp	NZ, %2
-	ld	a, #%3
-	jp	%1
-%2:
-	xor	a, a
-%1:
-} by {
-	ld	a, #%3
-	jp	Z, %1
-	; peephole 169xnz used double assignment in case of NZ condition.
-%2:
-	xor	a, a
-%1:
-} if labelRefCountChange(%2 -1)
-
-replace restart {
-	jp	Z, %2
-	ld	c, #%3
-	jp	%1
-%2:
-	ld	c, #%4
-%1:
-} by {
-	ld	c, #%3
-	jp	NZ, %1
-%2:
-	ld	c, #%4
-	; peephole 170z used double assignment in case of Z condition.
-%1:
-} if labelRefCountChange(%2 -1)
-
-replace restart {
-	jp	NZ, %2
-	ld	c, #%3
-	jp	%1
-%2:
-	ld	c, #%4
-%1:
-} by {
-	ld	c, #%3
-	jp	Z, %1
-%2:
-	ld	c, #%4
-	; peephole 170nz used double assignment in case of NZ condition.
-%1:
-} if labelRefCountChange(%2 -1)
-
-replace restart {
-	jp	Z, %2
-	ld	e, #%3
-	jp	%1
-%2:
-	ld	e, #%4
-%1:
-} by {
-	ld	e, #%3
-	jp	NZ, %1
-%2:
-	ld	e, #%4
-	; peephole 171z used double assignment in case of Z condition.
-%1:
-} if labelRefCountChange(%2 -1)
-
-replace restart {
-	jp	NZ, %2
-	ld	e, #%3
-	jp	%1
-%2:
-	ld	e, #%4
-%1:
-} by {
-	ld	e, #%3
-	jp	Z, %1
-%2:
-	ld	e, #%4
-	; peephole 171nz used double assignment in case of NZ condition.
-%1:
-} if labelRefCountChange(%2 -1)
-
-replace restart {
-	jp	Z, %2
-	ld	l, #%3
-	jp	%1
-%2:
-	ld	l, #%4
-%1:
-} by {
-	ld	l, #%3
-	jp	NZ, %1
-%2:
-	ld	l, #%4
-	; peephole 172z used double assignment in case of Z condition.
-%1:
-} if labelRefCountChange(%2 -1)
-
-replace restart {
-	jp	NZ, %2
-	ld	l, #%3
-	jp	%1
-%2:
-	ld	l, #%4
-%1:
-} by {
-	ld	l, #%3
-	jp	Z, %1
-%2:
-	ld	l, #%4
-	; peephole 172nz used double assignment in case of NZ condition.
-%1:
-} if labelRefCountChange(%2 -1)
-
-// These ex-generating rules should be among the last ones since ex counts as a read from both hl and de for notUsed().
-barrier
-
-replace restart {
-	ld	d,h
-	ld	e,l
-} by {
-	; peephole 146 used ex to load hl into de.
-	ex	de,hl
-} if notUsed('hl')
-
-replace restart {
-	ld	e,l
-	ld	d,h
-} by {
-	; peephole 147 used ex to load hl into de.
-	ex	de,hl
-} if notUsed('hl')
-
-replace restart {
-	ld	l,e
-	ld	h,d
-} by {
-	; peephole 148 used ex to load de into hl.
-	ex	de,hl
-} if notUsed('de')
-
-barrier
-
-// Should be one of the last ones. Opens the code to further peephole optimization.
-replace restart {
-%1:
-} by {
-	; peephole 149 removed unused label %1.
-} if labelRefCount(%1 0)
-
-// Ensure that all rules above see only jp, not jr.
-barrier
-
-replace {
-	add	hl,de
-	pop	de
-	jp	(hl)
-%1:
-	jp	%5
-	jp	%6
-	jp	%7
-%2:
-} by {
-	; peephole 150-3 removed addition using short jumps in jump-table.
-	pop	de
-	jp	(hl)
-%1:
-	jr	%5
-	jr	%6
-	jr	%7
-%2:
-} if labelJTInRange
-
-replace {
-	add	hl,de
-	jp	(hl)
-%1:
-	jp	%5
-	jp	%6
-	jp	%7
-%2:
-} by {
-	; peephole 150-3' removed addition using short jumps in jump-table.
-	jp	(hl)
-%1:
-	jr	%5
-	jr	%6
-	jr	%7
-%2:
-} if labelJTInRange
-
-replace {
-	add	hl,de
-	pop	de
-	jp	(hl)
-%1:
-	jp	%5
-	jp	%6
-	jp	%7
-	jp	%8
-%2:
-} by {
-	; peephole 150-4 removed addition using short jumps in jump-table.
-	pop	de
-	jp	(hl)
-%1:
-	jr	%5
-	jr	%6
-	jr	%7
-	jr	%8
-%2:
-} if labelJTInRange
-
-replace {
-	add	hl,de
-	jp	(hl)
-%1:
-	jp	%5
-	jp	%6
-	jp	%7
-	jp	%8
-%2:
-} by {
-	; peephole 150-4' removed addition using short jumps in jump-table.
-	jp	(hl)
-%1:
-	jr	%5
-	jr	%6
-	jr	%7
-	jr	%8
-%2:
-} if labelJTInRange
-
-replace {
-	add	hl,de
-	pop	de
-	jp	(hl)
-%1:
-	jp	%5
-	jp	%6
-	jp	%7
-	jp	%8
-	jp	%9
-%2:
-} by {
-	; peephole 150-5 removed addition using short jumps in jump-table.
-	pop	de
-	jp	(hl)
-%1:
-	jr	%5
-	jr	%6
-	jr	%7
-	jr	%8
-	jr	%9
-%2:
-} if labelJTInRange
-
-replace {
-	add	hl,de
-	jp	(hl)
-%1:
-	jp	%5
-	jp	%6
-	jp	%7
-	jp	%8
-	jp	%9
-%2:
-} by {
-	; peephole 150-5' removed addition using short jumps in jump-table.
-	jp	(hl)
-%1:
-	jr	%5
-	jr	%6
-	jr	%7
-	jr	%8
-	jr	%9
-%2:
-} if labelJTInRange
-
-replace {
-	add	hl,de
-	pop	de
-	jp	(hl)
-%1:
-	jp	%5
-	jp	%6
-	jp	%7
-	jp	%8
-	jp	%9
-	jp	%10
-%2:
-} by {
-	; peephole 150-6 removed addition using short jumps in jump-table.
-	pop	de
-	jp	(hl)
-%1:
-	jr	%5
-	jr	%6
-	jr	%7
-	jr	%8
-	jr	%9
-	jr	%10
-%2:
-} if labelJTInRange
-
-replace {
-	add	hl,de
-	jp	(hl)
-%1:
-	jp	%5
-	jp	%6
-	jp	%7
-	jp	%8
-	jp	%9
-	jp	%10
-%2:
-} by {
-	; peephole 150-6' removed addition using short jumps in jump-table.
-	jp	(hl)
-%1:
-	jr	%5
-	jr	%6
-	jr	%7
-	jr	%8
-	jr	%9
-	jr	%10
-%2:
-} if labelJTInRange
-
-replace {
-	add	hl,de
-	pop	de
-	jp	(hl)
-%1:
-	jp	%5
-	jp	%6
-	jp	%7
-	jp	%8
-	jp	%9
-	jp	%10
-	jp	%11
-%2:
-} by {
-	; peephole 150-7 removed addition using short jumps in jump-table.
-	pop	de
-	jp	(hl)
-%1:
-	jr	%5
-	jr	%6
-	jr	%7
-	jr	%8
-	jr	%9
-	jr	%10
-	jr	%11
-%2:
-} if labelJTInRange
-
-replace {
-	add	hl,de
-	jp	(hl)
-%1:
-	jp	%5
-	jp	%6
-	jp	%7
-	jp	%8
-	jp	%9
-	jp	%10
-	jp	%11
-%2:
-} by {
-	; peephole 150-7' removed addition using short jumps in jump-table.
-	jp	(hl)
-%1:
-	jr	%5
-	jr	%6
-	jr	%7
-	jr	%8
-	jr	%9
-	jr	%10
-	jr	%11
-%2:
-} if labelJTInRange
-
-barrier
-
-// Do all jump optimizations before replacing by ret.
-
-replace restart {
-	jp	%5
-} by {
-	ret
-	; peephole 151 replaced jump by return.
-} if labelIsReturnOnly(%5), labelRefCountChange(%5 -1)
-
-replace restart {
-	jp	%1,%5
-} by {
-	ret	%1
-	; peephole 152 replaced jump by return.
-} if labelIsReturnOnly(%5), labelRefCountChange(%5 -1)
-
-// Replace jp by ret before replacing jp by jr outside of jump tables, since using ret can reduce the number of references to jump labels.
-barrier
-
-replace {
-	jp	%5
-} by {
-	jr	%5
-	; peephole 153 changed absolute to relative unconditional jump.
-} if labelInRange(%5)
-
-replace {
-	jp	Z,%5
-} by {
-	jr	Z,%5
-	; peephole 154 changed absolute to relative conditional jump.
-} if labelInRange(%5)
-
-replace {
-	jp	NZ,%5
-} by {
-	jr	NZ,%5
-	; peephole 155 changed absolute to relative conditional jump.
-} if labelInRange(%5)
-
-replace {
-	jp	C,%5
-} by {
-	jr	C,%5
-	; peephole 156 changed absolute to relative conditional jump.
-} if labelInRange(%5)
-
-replace {
-	jp	NC,%5
-} by {
-	jr	NC,%5
-	; peephole 157 changed absolute to relative conditional jump.
-} if labelInRange(%5)
-
-replace {
-	dec b
-	jr	NZ,	%5	
-} by {
-	djnz	%5
-	; peephole 158 used djnz
-}
-
diff -Nru sdcc-4.0.0+dfsg/src/z80/peeph-sm83.def sdcc-4.2.0+dfsg/src/z80/peeph-sm83.def
--- sdcc-4.0.0+dfsg/src/z80/peeph-sm83.def	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/z80/peeph-sm83.def	2021-12-10 14:48:15.000000000 +0000
@@ -0,0 +1,468 @@
+// peeph-sm83.def - SM83 peephole rules
+//
+//
+// (c) Philipp Klaus Krause (pkk@spth.de, philipp@colecovision.eu) 2006 - 2007
+// (c) Sebastian 'basxto' Riedel (sdcc@basxto.de) 2020 - 2021
+//
+// This program is free software; you can redistribute it and/or modify it
+// under the terms of the GNU General Public License as published by the
+// Free Software Foundation; either version 2, or (at your option) any
+// later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+replace{
+	ld	hl, #%1
+	ld	a, (hl)
+} by {
+	; sm83 peephole 0 used ldh instead of ld a, (hl).
+	ldh	a, (#%1)
+} if operandsLiteral(%1), immdInRange(0xff00 0xffff '|' %1 0 %2), notUsed('hl')
+
+replace{
+	ld	a, (#%1)
+} by {
+	; sm83 peephole 0b used ldh instead of ld.
+	ldh	a, (#%1)
+} if operandsLiteral(%1), immdInRange(0xff00 0xffff '|' %1 0 %2)
+
+replace{
+	ld	hl, #%1
+	ld	(hl), a
+} by {
+	; sm83 peephole 1 used ldh instead of ld (hl), a.
+	ldh	(#%1), a
+} if operandsLiteral(%1), immdInRange(0xff00 0xffff '|' %1 0 %2), notUsed('hl')
+
+replace{
+	ld	(#%1), a
+} by {
+	; sm83 peephole 1b used ldh instead of ld.
+	ldh	(#%1), a
+} if operandsLiteral(%1), immdInRange(0xff00 0xffff '|' %1 0 %2)
+
+replace {
+	ld	a, (hl)
+	inc	hl
+} by {
+	ld	a, (hl+)
+	; sm83 peephole 2 used ldi to increment hl after load
+}
+
+replace {
+	ld	%1, (hl)
+	inc	hl
+} by {
+	ld	a, (hl+)
+	ld	%1, a
+	; sm83 peephole 2b used ldi to increment hl after load
+} if notUsed('a')
+
+replace {
+	ld	%1, (hl)
+	dec	hl
+} by {
+	ld	a, (hl-)
+	ld	%1, a
+	; sm83 peephole 3 used ldd to decrement hl after load
+} if notUsed('a')
+
+replace {
+	ld	a, (hl)
+	dec	hl
+} by {
+	ld	a, (hl-)
+	; sm83 peephole 3b used ldd to decrement hl after load
+}
+
+replace {
+	ld	(hl), a
+	inc	hl
+} by {
+	ld	(hl+), a
+	; sm83 peephole 4 used ldi to increment hl after load
+}
+
+replace {
+	ld	(hl), %1
+	inc	hl
+} by {
+	ld	a, %1
+	ld	(hl+), a
+	; sm83 peephole 4b used ldi to increment hl after load
+} if notUsed('a')
+
+replace {
+	ld	(hl), a
+	dec	hl
+} by {
+	ld	(hl-), a
+	; sm83 peephole 5 used ldd to decrement hl after load
+}
+
+replace {
+	ld	(hl), %1
+	dec	hl
+} by {
+	ld	a, %1
+	ld	(hl-), a
+	; sm83 peephole 5b used ldd to decrement hl after load
+} if notUsed('a')
+
+replace {
+	ld	(hl), a
+	inc	%2
+	ld	a, (%2)
+	inc	hl
+} by {
+	ld	(hl+), a
+	; sm83 peephole 7 used ldi to increment hl
+	inc	%2
+	ld	a, (%2)
+} if notSame('hl' %2)
+
+replace {
+	ld	a, (hl)
+	ld	(%2), a
+	inc	%2
+	inc	hl
+} by {
+	ld	a, (hl+)
+	; sm83 peephole 8 used ldi to increment hl
+	ld	(%2), a
+	inc	%2
+} if notSame('hl' %2)
+
+replace {
+	dec	hl
+	ld	a, (hl+)
+	ld	h, (hl)
+	ld	l, a
+} by {
+	; sm83 peephole 9 reversed loading order of hl
+	ld	a, (hl-)
+	ld	l, (hl)
+	ld	h, a
+} if notUsed('a')
+
+replace restart {
+	ldhl	sp,#%1
+	ld	%2, %3
+	ldhl	sp,#%1
+} by {
+	; sm83 peephole 10a removed redundant ldhl.
+	ldhl	sp,#%1
+	ld	%2, %3
+} if notSame('(hl+)' %2 %3),  notSame('(hl+)' %2 %3)
+
+// 10b and c are for pushing stack addresses
+replace restart {
+	ldhl	sp,	#%1
+	ld	%3, %4
+	ld	%5, %6
+	ldhl	sp,	#%2
+} by {
+	ldhl	sp,	#1
+	ld	%3, %4
+	ld	%5, %6
+	; sm83 peephole 10b turned ldhl into dec hl
+	dec	hl
+} if operandsLiteral(%1 %2), notSame('l' %3 %5), notSame('l' %3 %5), immdInRange(0x01 0x01 '-' %1 %2 %3), operandsNotRelated('hl' %3 %4 %5 %6)
+
+replace restart {
+	ldhl	sp,	#%1
+	ld	%3, %4
+	ld	%5, %6
+	ldhl	sp,	#%2
+} by {
+	ldhl	sp,	#1
+	ld	%3, %4
+	ld	%5, %6
+	; sm83 peephole 10c turned ldhl into inc hl
+	inc	hl
+} if operandsLiteral(%1 %2), notSame('l' %3 %5), notSame('l' %3 %5), immdInRange(0x01 0x01 '-' %2 %1 %3), operandsNotRelated('hl' %3 %4 %5 %6)
+
+replace restart {
+	ldhl	sp,#%1
+	dec	hl
+} by {
+	; sm83 peephole 10d combined ld and dec.
+	ldhl	sp,#%2
+} if immdInRange(-128 127 '-' %1 1 %2)
+
+replace restart {
+	ldhl	sp,#%1
+	inc	hl
+} by {
+	; sm83 peephole 10e combined ld and inc.
+	ldhl	sp,#%2
+} if immdInRange(-128 127 '+' %1 1 %2)
+
+replace restart {
+	and	a, #%1
+	swap a
+	and	a, #%2
+} by {
+	; sm83 peephole 11 combined redundant ANDs #%2 and swapped #%1.
+	swap a
+	and	a, #%7
+} if operandsLiteral(%1 %2), immdInRange(0x00 0xff '/' %1 0x10 %3), immdInRange(0x00 0xfff '*' %1 0x10 %4), immdInRange(0x00 0xff '&' %4 0xF0 %5), immdInRange(0x00 0xff '|' %3 %5 %6), immdInRange(0x00 0xff '&' %2 %6 %x7)
+
+replace restart {
+	ldh a, (%1)
+	inc a
+	ldh (%1), a
+} by {
+	; sm83 peephole 12 turned ldh into inc (hl).
+	ld hl, #((%1) | 0xFF00)
+	inc (hl)
+} if notSame(%1 'c'), notUsed('a' 'hl')
+
+replace restart {
+	ldh a, (%1)
+	dec a
+	ldh (%1), a
+} by {
+	; sm83 peephole 13 turned ldh into dec (hl).
+	ld hl, #((%1) | 0xFF00)
+	dec (hl)
+} if notSame(%1 'c'), notUsed('a' 'hl')
+
+replace restart {
+	ldh a, (%1)
+	srl a
+	ldh (%1), a
+} by {
+	; sm83 peephole 14 turned ldh into srl (hl).
+	ld hl, #((%1) | 0xFF00)
+	srl (hl)
+} if notSame(%1 'c'), notUsed('a' 'hl')
+
+replace restart {
+	rra
+	rla
+} by {
+	; sm83 peephole 16 removed redundant rra/rla
+} if notUsed('cf' 'hf' 'nf' 'zf')
+
+replace {
+	xor	a, a
+	push 	af
+	inc	sp
+	xor	a, a
+	push 	af
+	inc	sp
+} by {
+	; sm83 peephole 17a pushed double `xor a` fast
+	xor	a, a
+	rrca
+	push	af
+	xor	a, a
+}
+
+//TOOD: fails for unknown reasons
+//replace {
+//	ld	%1, #%2
+//	push	%1
+//} by {
+//	; sm83 peephole 17b pushed #%2 faster
+//	xor	a, a
+//	rra
+//	push	af
+//} if operandsLiteral(%2), immdInRange(0 0 '+' %2 0 %3), notUsed(%1 'af')
+
+replace {
+	ld	%1, #%2
+	push	%1
+} by {
+	; sm83 peephole 18a pushed #%2 faster
+	sub	a, a
+	push	af
+} if operandsLiteral(%2), immdInRange(0x00C0 0x00C0 '+' %2 0 %x3), notUsed(%1 'af')
+
+
+// Those rules save 1 byte and 4 cycles each
+replace {
+	ld	%1, #%2
+	push	%1
+} by {
+	; sm83 peephole 18b pushed #%2 faster
+	xor	a, a
+	push	af
+} if operandsLiteral(%2), immdInRange(0x0080 0x0080 '+' %2 0 %x3), notUsed(%1 'af')
+
+replace {
+	ld	%1, #%2
+	push	%1
+} by {
+	; sm83 peephole 18c pushed #%2 faster
+	xor	a, a
+	scf
+	push	af
+} if operandsLiteral(%2), immdInRange(0x0090 0x0090 '+' %2 0 %x3), notUsed(%1 'af')
+
+replace {
+	ld	%1, #%2
+	push	%1
+} by {
+	; sm83 peephole 18d pushed #%2 faster
+	xor	a, a
+	and	a
+	push	af
+} if operandsLiteral(%2), immdInRange(0x00A0 0x00A0 '+' %2 0 %x3), notUsed(%1 'af')
+
+replace {
+	ld	%1, #%2
+	push	%1
+} by {
+	; sm83 peephole 18e pushed #%2 faster
+	xor	a, a
+	scf
+	push	af
+} if operandsLiteral(%2), immdInRange(0x00D0 0x00D0 '+' %2 0 %x3), notUsed(%1 'af')
+
+replace {
+	ld	%1, #%2
+	push	%1
+} by {
+	; sm83 peephole 18f pushed #%2 faster
+	xor	a, a
+	inc	a
+	push	af
+} if operandsLiteral(%2), immdInRange(0x0100 0x0100 '+' %2 0 %x3), notUsed(%1 'af')
+
+replace {
+	ld	%1, #%2
+	push	%1
+} by {
+	; sm83 peephole 18g pushed #%2 faster
+	scf
+	sbc	a, a
+	push	af
+} if operandsLiteral(%2), immdInRange(0xFF30 0xFF30 '+' %2 0 %x3), notUsed(%1 'af')
+
+replace {
+	ld	%1, #%2
+	push	%1
+} by {
+	; sm83 peephole 18h pushed #%2 faster
+	xor	a, a
+	dec	a
+	push	af
+} if operandsLiteral(%2), immdInRange(0xFF60 0xFF60 '+' %2 0 %x3), notUsed(%1 'af')
+
+replace {
+	push	af
+	inc	sp
+	ld	a, #%2
+	push	af
+	inc	sp
+} by {
+	; sm83 peephole 19 pushed #%2 via flags
+	cp	a
+	push	af
+} if operandsLiteral(%2), immdInRange(0xC0 0xC0 '+' %2 0 %x3), notUsed('f')
+
+replace {
+	pop	%1
+	push	%1
+} by {
+	; peephole sp1 removed not needed push
+	pop	%1
+} if notUsed('sp')
+
+replace {
+	pop	%1
+	pop	%2
+	push	%2
+	push	%1
+} by {
+	; peephole sp2 removed not needed push
+	pop	%1
+	pop	%2
+} if notUsed('sp'), notSame(%1 %2)
+
+replace {
+	add	sp, %1
+} by {
+	; peephole sp3 removed not needed add sp
+} if notUsed('sp')
+
+replace {
+	pop	%1
+} by {
+	; peephole sp6 removed not needed pop
+} if notUsed(%1), notUsed('sp')
+
+// for 2B it wouldn't be worth it
+replace {
+	inc	sp
+	inc	sp
+	inc	sp
+} by {
+	; peephole sp7 increased SP by addition
+	add	sp, #3
+} if notUsed('f')
+
+replace restart {
+	add	sp, #%1
+	inc	sp
+} by {
+	; peephole sp8a increased SP by addition
+	add	sp, #%2
+} if immdInRange(-128 127 '+' %1 1 %2), notUsed('hf' 'cf')
+
+replace restart {
+	inc	sp
+	add	sp, #%1
+} by {
+	; peephole sp8b increased SP by addition
+	add	sp, #%2
+} if immdInRange(-128 127 '+' %1 1 %2)
+
+replace restart {
+	add	sp, #%1
+	add	sp, #%2
+} by {
+	; peephole sp9 combined SP additions
+	add	sp, #%3
+} if immdInRange(-128 127 '+' %1 %2 %3), notUsed('hf' 'cf')
+
+// only handle stack adjustment after calls to not 
+// disturb detection of unitialized reads in emulators
+replace {
+	call	%2
+	add	sp, #%1
+} by {
+	call	%2
+	; peephole sp10a increased SP by %1 through pop
+	pop	%3
+} if immdInRange(2 2 '+' %1 0 %2), unusedReg(%3 'bc' 'de' 'hl'), notUsed('f')
+
+// unusedReg does not support 'af'
+replace {
+	call	%2
+	add	sp, #%1
+} by {
+	call	%2
+	; peephole sp10b increased SP by %1 through pop
+	pop	af
+} if immdInRange(2 2 '+' %1 0 %2), notUsed('af')
+
+// if f was used
+replace {
+	call	%2
+	inc	sp
+	inc	sp
+} by {
+	call	%2
+	; peephole sp10c increased SP by 2 through pop
+	pop	%3
+} if unusedReg(%3 'bc' 'de' 'hl')
diff -Nru sdcc-4.0.0+dfsg/src/z80/peeph-tlcs90.def sdcc-4.2.0+dfsg/src/z80/peeph-tlcs90.def
--- sdcc-4.0.0+dfsg/src/z80/peeph-tlcs90.def	2019-11-14 11:36:33.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/z80/peeph-tlcs90.def	2020-07-16 03:41:15.000000000 +0000
@@ -20,103 +20,6 @@
 // Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
 
 replace restart {
-	ld	%1, %1
-} by {
-	; peephole 0 removed redundant load from %1 into %1.
-} if notVolatile(%1)
-
-replace restart {
-	add	ix,sp
-} by {
-	; peephole 1 removed dead frame pointer setup.
-} if notUsed('ix')
-
-replace restart {
-	ld	%1, %2 + %3
-} by {
-	; peephole 2 removed dead load from %2 + %3 into %1.
-} if notVolatile(%1), notUsed(%1)
-// Should probably check for notVolatile(%2), too, but gives many false positives and no regression tests fail.
-
-replace restart {
-	ld	%1, (iy)
-} by {
-	ld	%1, 0 (iy)
-	; peephole 3 made 0 offset explicit.
-}
-
-replace restart {
-	ld	(iy), %1
-} by {
-	ld	0 (iy), %1
-	; peephole 4 made 0 offset explicit.
-}
-
-replace restart {
-	dec	hl
-} by {
-	; peephole 5 removed dead decrement of hl.
-} if notUsed('hl')
-
-replace restart {
-	ld	%1, %2 (iy)
-} by {
-	; peephole 6 removed dead load from %2 (iy) into %1.
-} if notUsed(%1)
-// Should probably check for notVolatile(), but gives many false positives and no regression tests fail.
-
-replace restart {
-	ld	%1, %2 (ix)
-} by {
-	; peephole 7 removed dead load from %2 (ix) into %1.
-} if notUsed(%1)
-
-replace restart {
-	ld	%1, %2
-	ld	%3, %1
-} by {
-	; peephole 8 loaded %3 from %2 directly instead of going through %1.
-	ld	%3, %2
-} if canAssign(%3 %2), notVolatile(%1), notUsed(%1)
-
-replace restart {
-	ld	%1, %2
-	ld	%3, %4
-	ld	%5, %1
-} by {
-	ld	%5, %2
-	; peephole 9 loaded %5 from %2 directly instead of going through %1.
-	ld	%3, %4
-} if canAssign(%5 %2), notVolatile(%1), operandsNotRelated(%1 %4), operandsNotRelated(%1 %3), operandsNotRelated(%3 %5), operandsNotRelated(%4 %5), notUsed(%1), notSame(%3 %4 '(hl)' '(de)' '(bc)'), notVolatile(%5)
-// Rule OK unless both %5 and %4 are volatile, but we can't express that directly.
-
-replace restart {
-	ld	%1, %2 (%3)
-	ld	%4, %1
-} by {
-	; peephole 10 loaded %2 (%3) into %4 directly instead of going through %1.
-	ld	%4, %2 (%3)
-} if canAssign(%4 %2 %3), notVolatile(%1), notUsed(%1)
-
-replace restart {
-	ld	%1, %2
-	ld	%3 (%4), %1
-} by {
-	; peephole 11 loaded %2 into %3 (%4) directly instead of going through %1.
-	ld	%3 (%4), %2
-} if canAssign(%3 %4 %2), notVolatile(%1), notUsed(%1), notSame(%1 'hl')
-
-replace restart {
-	ld	%1, %2 (%3)
-	ld	%4, %5 (%6)
-	ld	%7, %1
-} by {
-	ld	%7, %2 (%3)
-	; peephole 12 loaded %2 (%3) into %7 directly instead of going through %1.
-	ld	%4, %5 (%6)
-} if canAssign(%7 %2 %3), notVolatile(%1), notUsed(%1), notSame(%1 %4), notSame(%7 %4)
-
-replace restart {
 	ld	%1, %7
 	ld	%5 (%6), %4
 	ld	%2 (%3), %1
@@ -127,389 +30,6 @@
 } if canAssign(%2 %3 %7), notVolatile(%1), notUsed(%1), notSame(%1 %4 %1 'hl')
 
 replace restart {
-	ld	%1, %2 (%3)
-	ld	%4, %5
-	ld	%7, %1
-} by {
-	ld	%7, %2 (%3)
-	; peephole 14 loaded %2 (%3) into %7 directly instead of going through %1.
-	ld	%4, %5
-} if canAssign(%7 %2 %3), notVolatile(%1), notUsed(%1), operandsNotRelated(%1 %5), operandsNotRelated(%7 %4), operandsNotRelated(%7 %5), notSame(%4 '(hl)' '(de)' '(bc)'), notSame(%5 '(hl)' '(de)' '(bc)' '(iy)')
-
-replace restart {
-	ld	%1,#%2
-	ld	a,%3 (%1)
-} by {
-	; peephole 15 loaded %2 into a directly instead of going through %1.
-	ld	a,(#%2 + %3)
-} if notUsed(%1)
-
-replace restart {
-	ld	hl,#%1
-	ld	a,(hl)
-} by {
-	ld	a,(#%1)
-	; peephole 16 loaded a from (#%1) directly instead of using hl.
-} if notUsed('hl')
-
-replace restart {
-	ld	hl,#%1 + %2
-	ld	a,(hl)
-} by {
-	; peephole 17 loaded %2 into a directly instead of using hl.
-	ld	a,(#%1 + %2)
-} if notUsed('hl')
-
-replace restart {
-	ld	hl,#%1
-	ld	(hl),a
-} by {
-	ld	(#%1),a
-	; peephole 18 loaded (#%1) from a directly instead of using hl.
-} if notUsed('hl')
-
-replace restart {
-	ld	hl,#%1 + %2
-	ld	(hl),a
-} by {
-	ld	(#%1 + %2),a
-	; peephole 19 loaded (#%1) from a directly instead of using hl.
-} if notUsed('hl')
-
-replace restart {
-	ld	a, %1 (%2)
-	srl	a
-	ld	%1 (%2), a
-} by {
-	srl	%1 (%2)
-	ld	a, %1 (%2)
-	; peephole 20 shifted in (%2) instead of a.
-}
-
-replace restart {
-	ld	%1,(hl)
-	ld	a,%2 (%3)
-	sub	a,%1
-} by {
-	ld	a,%2 (%3)
-	; peephole 21 used (hl) in sub directly instead of going through %1.
-	sub	a,(hl)
-} if notVolatile(%1), notUsed(%1)
-
-replace restart {
-	inc	bc
-	ld	l,c
-	ld	h,b
-} by {
-	ld	l,c
-	ld	h,b
-	; peephole 22 incremented in hl instead of bc.
-	inc	hl
-} if notUsed('bc')
-
-replace restart {
-	inc	de
-	ld	l,e
-	ld	h,d
-} by {
-	ld	l,e
-	ld	h,d
-	; peephole 23 incremented in hl instead of de.
-	inc	hl
-} if notUsed('de')
-
-replace restart {
-	ld	c,l
-	ld	b,h
-	ld	a,#%1
-	ld	(bc),a
-} by {
-	ld	c,l
-	ld	b,h
-	ld	(hl),#%1
-	; peephole 24 loaded #%1 into (hl) instead of (bc).
-} if notUsed('a')
-
-replace restart {
-	ex	de, hl
-	push	de
-} by {
-	; peephole 25 pushed hl directly instead of going through de.
-	push	hl
-} if notUsed('de'), notUsed('hl')
-
-replace restart {
-	ex	de, hl
-	push	bc
-	push	de
-} by {
-	; peephole 26 pushed hl directly instead of going through de.
-	push	bc
-	push	hl
-} if notUsed('de'), notUsed('hl')
-
-replace restart {
-	ld	c,l
-	ld	b,h
-	push	%1
-	push	bc
-} by {
-	; peephole 27 pushed hl directly instead of going through bc.
-	push	%1
-	push	hl
-} if notUsed('bc'), notSame(%1 'bc')
-
-replace restart {
-	pop	de
-	ld	l, e
-	ld	h, d
-} by {
-	; peephole 28 popped hl directly instead of going through de.
-	pop	hl
-} if notUsed('de')
-
-replace restart {
-	pop	bc
-	ld	l, c
-	ld	h, b
-} by {
-	; peephole 29 popped hl directly instead of going through bc.
-	pop	hl
-} if notUsed('bc')
-
-replace restart {
-	ld	%1 (ix), %2
-	ld	%3, %1 (ix)
-} by {
-	; peephole 30 loaded %3 from %2 instead of going through %1 (ix).
-	ld	%1 (ix), %2
-	ld	%3, %2
-} if canAssign(%3 %2)
-// Don't need to check for volatile, since ix is used for the stack.
-
-replace restart {
-	ld	%1 (ix), a
-	push	de
-	ld	%2, %1 (ix)
-} by {
-	ld	%1 (ix), a
-	push	de
-	; peephole 31 loaded %2 from a instead of %1 (ix)
-	ld	%2, a
-} if canAssign(%2 'a')
-
-replace restart {
-	push	af
-	inc	sp
-	ld	a,e
-	push	af
-	inc	sp
-} by {
-	; peephole 32 pushed de instead of pushing a twice.
-	ld	d,a
-	push	de
-} if notUsed('d'), notUsed('a')
-
-replace restart {
-	push	af
-	inc	sp
-	ld	a,#%1
-	push	af
-	inc	sp
-} by {
-	; peephole 33 pushed de instead of pushing a twice.
-	ld	d,a
-	ld	e,#%1
-	push	de
-} if notUsed('de')
-
-replace restart {
-	push	bc
-	inc	sp
-	push	de
-	inc	sp
-} by {
-	ld	c, d
-	; peephole 34 combined pushing of b and d.
-	push	bc
-} if notUsed('c')
-
-replace restart {
-	ld	a,#%1
-	ld	d,a
-} by {
-	; peephole 35 loaded #%1 into d directly instead of going through a.
-	ld	d,#%1
-} if notUsed('a')
-
-replace restart {
-	ld	%1,a
-	ld	%2,%1
-} by {
-	; peephole 36 loaded %2 from a directly instead of going through %1.
-	ld	%2,a
-} if notUsed(%1)
-
-replace restart {
-	ld	a,%1 (%3)
-	push	af
-	inc	sp
-	ld	a,%2 (%3)
-	push	af
-	inc	sp
-} by {
-	; peephole 37 pushed %1 (%3), %2(%3) through hl instead of af.
-	ld	h,%1 (%3)
-	ld	l,%2 (%3)
-	push	hl
-} if notUsed('a'), notUsed('hl')
-
-replace restart {
-	ld	c, l
-	ld	b, h
-	push	bc
-} by {
-	; peephole 38 pushed hl instead of bc.
-	push	hl
-} if notUsed('bc')
-
-replace restart {
-	ld	a, (hl)
-	inc	hl
-	ld	h, (hl)
-	ld	l, a
-	push	hl
-} by {
-	; peephole 39 pushed bc instead of hl.
-	ld	c, (hl)
-	inc	hl
-	ld	b, (hl)
-	push	bc
-} if notUsed('bc'), notUsed('hl')
-
-replace restart {
-	pop	%1
-	push	%1
-} by {
-	; peephole 40 eleminated dead pop/push pair.
-} if notUsed(%1)
-
-replace restart {
-	push	hl
-	pop	bc
-} by {
-	ld	c, l
-	ld	b, h
-	; peephole 41 replaced push/pop pair by loads.
-} if notUsed('hl')
-
-replace restart {
-	push	hl
-	pop	de
-} by {
-	ld	e, l
-	ld	d, h
-	; peephole 42 replaced push/pop pair by loads.
-} if notUsed('hl')
-
-replace restart {
-	ld	iy,#%1
-	or	a,%2 (iy)
-} by {
-	; peephole 43 used hl instead of iy.
-	ld	hl,#%1 + %2
-	or	a,(hl)
-} if notUsed('iy'), notUsed('hl')
-
-replace restart {
-	ld	iy,#%1
-	ld	%2,%3 (iy)
-} by {
-	; peephole 44 used hl instead of iy.
-	ld	hl,#%1 + %3
-	ld	%2, (hl)
-} if notUsed('iy'), notUsed('hl')
-
-replace restart {
-	ld	iy,#%1
-	ld	h,%3 (iy)
-} by {
-	; peephole 45 used hl instead of iy.
-	ld	hl,#%1 + %3
-	ld	h, (hl)
-} if notUsed('iy'), notUsed('l')
-
-replace restart {
-	ld	iy,#%1
-	ld	%2 (iy), %3
-} by {
-	; peephole 46 used hl instead of iy.
-	ld	hl,#%1 + %2
-	ld	(hl), %3
-} if notUsed('iy'), notUsed('hl'), notSame(%3 'h' 'l')
-
-replace restart {
-	ld	iy,#%1
-	ld	%2,0 (iy)
-	ld	%3,1 (iy)
-} by {
-	; peephole 47 used hl instead of iy.
-	ld	hl,#%1
-	ld	%2, (hl)
-	inc	hl
-	ld	%3, (hl)
-} if notUsed('iy'), notUsed('hl'), operandsNotRelated(%2 'hl')
-
-replace restart {
-	ld	iy,#%1
-	bit	%2,%3 (iy)
-} by {
-	; peephole 48 used hl instead of iy.
-	ld	hl,#%1+%3
-	bit	%2, (hl)
-} if notUsed('iy'), notUsed('hl')
-
-replace restart {
-	ld	iy, #%1
-	add	iy, sp
-	ld	%2, %3 (iy)
-} by {
-	; peephole 49 used hl instead of iy.
-	ld	hl, #%1+%3
-	add	hl, sp
-	ld	%2, (hl)
-} if notUsed('iy'), notUsed('hl')
-
-replace restart {
-	ld	iy, #%1
-	add	iy, sp
-	ld	%2, 0 (iy)
-	ld	%3, 1 (iy)
-} by {
-	; peephole 50 used hl instead of iy.
-	ld	hl, #%1
-	add	hl, sp
-	ld	%2, (hl)
-	inc	hl
-	ld	%3, (hl)
-} if notUsed('iy'), notUsed('hl')
-
-replace restart {
-	ld	iy, #%1
-	add	iy, sp
-	ld	l, 0 (iy)
-	ld	h, 1 (iy)
-} by {
-	; peephole 51 used hl instead of iy.
-	ld	hl, #%1
-	add	hl, sp
-	ld	a, (hl)
-	inc	hl
-	ld	h, (hl)
-	ld	l, a
-} if notUsed('iy'), notUsed('a')
-
-replace restart {
 	ld	iy, #%1+1
 	ld	a, 1 (iy)
 	or	a, 0 (iy)
@@ -522,71 +42,6 @@
 } if notUsed('iy'), notUsed('hl')
 
 replace restart {
-	ld	iy, #%1
-	add	iy, sp
-	ld	a, 1 (iy)
-	or	a, 0 (iy)
-} by {
-	ld	hl, #%1+1
-	add	hl, sp
-	ld	a, (hl)
-	dec	hl
-	or	a, (hl)
-	; peephole 53 used hl instead of iy.
-} if notUsed('iy'), notUsed('hl')
-
-replace restart {
-	ld	iy, #%1
-	add	iy, sp
-	bit	%2, %3 (iy)
-} by {
-	ld	hl, #%1+%3
-	add	hl, sp
-	bit	%2, (hl)
-	; peephole 54 used hl instead of iy.
-} if notUsed('iy'), notUsed('hl')
-
-replace restart {
-	ld	iy, #%1
-	add	iy, sp
-	or	a, %2 (iy)
-} by {
-	ld	hl, #%1+%2
-	add	hl, sp
-	or	a, (hl)
-	; peephole 55 used hl instead of iy.
-} if notUsed('iy'), notUsed('hl')
-
-replace restart {
-	ld	c,l
-	ld	b,h
-	inc	bc
-} by {
-	; peephole 56 incremented in hl instead of bc.
-	inc	hl
-	ld	c,l
-	ld	b,h
-} if notUsed('hl')
-
-replace restart {
-	ld	iy, #%1
-	inc	%2 (iy)
-} by {
-	; peephole 57 incremented in (hl) instead of %2 (iy).
-	ld	hl, #%1+%2
-	inc	(hl)
-} if notUsed('hl'), notUsed('iy')
-
-replace restart {
-	ld	iy, #%1
-	dec	%2 (iy)
-} by {
-	; peephole 58 decremented in (hl) instead of %2 (iy).
-	ld	hl, #%1+%2
-	dec	(hl)
-} if notUsed('hl'), notUsed('iy')
-
-replace restart {
 	add	hl, hl
 	ld	e, l
 	ld	d, h
@@ -633,132 +88,6 @@
 	pop	de
 }
 
-replace restart {
-	ld	a,%1 (%2)
-	bit	%3,a
-} by {
-	; peephole 63 tested bit of %1 (%2) directly instead of going through a.
-	bit	%3,%1 (%2)
-} if notUsed('a')
-
-replace restart {
-	ld	a,%1
-	bit	%2,a
-} by {
-	; peephole 64 tested bit %2 of %1 directly instead of going through a.
-	bit	%2,%1
-} if notUsed('a'), canAssign(%1 'b')
-
-replace restart {
-	ld	a, %1
-	set	%2, a
-	ld	%1, a
-} by {
-	; peephole 65 set bit %2 of %1 directly instead of going through a.
-	set	%2, %1
-	ld	a, %1
-} if canAssign(%1 'b')
-// canAssign(%1 'b') is true, iff set b, %1 is possible.
-
-replace restart {
-	ld	a, %1 (%2)
-	set	%3, a
-	ld	%1 (%2), a
-} by {
-	; peephole 66 set bit %3 of %1 (%2) directly instead of going through a.
-	set	%3, %1 (%2)
-	ld	a, %1 (%2)
-}
-
-replace restart {
-	ld	a, %1 (%2)
-	res	%3, a
-	ld	%1 (%2), a
-} by {
-	; peephole 67 reset bit %3 of %1 (%2) directly instead of going through a.
-	res	%3, %1 (%2)
-	ld	a, %1 (%2)
-}
-
-replace restart {
-	jp	NC,%1
-	jp	%2
-%1:
-} by {
-	jp	C,%2
-	; peephole 68 removed jp by using inverse jump logic
-%1:
-} if labelRefCountChange(%1 -1)
-
-replace restart {
-	jp	C,%1
-	jp	%2
-%1:
-} by {
-	jp	NC,%2
-	; peephole 69 removed jp by using inverse jump logic
-%1:
-} if labelRefCountChange(%1 -1)
-
-replace restart {
-	jp	NZ,%1
-	jp	%2
-%1:
-} by {
-	jp	Z,%2
-	; peephole 70 removed jp by using inverse jump logic
-%1:
-} if labelRefCountChange(%1 -1)
-
-replace restart {
-	jp	Z,%1
-	jp	%2
-%1:
-} by {
-	jp	NZ,%2
-	; peephole 71 removed jp by using inverse jump logic
-%1:
-} if labelRefCountChange(%1 -1)
-
-replace restart {
-	jp	%5
-} by {
-	jp	%6
-	; peephole 72 jumped to %6 directly instead of via %5.
-} if labelIsUncondJump(), notSame(%5 %6), labelRefCountChange(%5 -1), labelRefCountChange(%6 +1)
-
-replace restart {
-	jp	%1,%5
-} by {
-	jp	%1,%6
-	; peephole 73 jumped to %6 directly instead of via %5.
-} if labelIsUncondJump(), notSame(%5 %6), labelRefCountChange(%5 -1), labelRefCountChange(%6 +1)
-
-replace restart {
-	jp	%1
-%2:
-%1:
-} by {
-   ; peephole 74 eliminated jump.
-%2:
-%1:
-} if labelRefCountChange(%1 -1)
-
-// A peephole that makes the code longer. Let's hope it's worth it in speed gain and further optimization potential.
-replace restart {
-	ld	a,#0x00
-%1:
-	bit	%2,a
-	jp	Z,%3
-} by {
-	ld	a,#0x00
-	jp	%3
-	; peephole 77 jumped directly to %3 instead of testing a first.
-%1:
-	bit	%2,a
-	jp	Z,%3
-} if labelRefCountChange(%3 +1)
-
 replace {
 	ld	e,#0x%1
 	ld	d,#0x%2
@@ -808,294 +137,6 @@
 }
 
 replace restart {
-	ld	%1,a
-	ld	a,%1
-} by {
-	ld	%1,a
-	; peephole 84 removed redundant load from %1 into a.
-} if notVolatile(%1)
-// This gives many false negatives and without the test no problems are encountered in the regression tests
-// Maybe we can try this after 2.7.0 release
-
-replace restart {
-	ld	%2 (ix), %1
-	ld	%1, %2 (ix)
-} by {
-	ld	%2 (ix), %1
-	; peephole 84a removed redundant load of %1 from %2 (ix)
-}
-
-replace restart {
-	ld	%1,a
-	ld	a,%2
-	or	a,%1
-} by {
-	ld	%1,a
-	or	a,%2
-	; peephole 85 removed load by reordering or arguments.
-} if notVolatile(%1), canAssign('b' %2)
-// canAssign('b' %2) is true, iff or a,%2 is possible.
-
-replace restart {
-	and	a,%1
-	or	a,a
-} by {
-	and	a,%1
-	; peephole 86 removed redundant or after and.
-}
-
-replace restart {
-	xor	a,%1 (%2)
-	or	a,a
-} by {
-	xor	a,%1 (%2)
-	; peephole 87 removed redundant or after xor.
-}
-
-replace {
-	ld	%1,%2
-	ld	a,%2
-} by {
-	ld	a,%2
-	ld	%1,a
-	; peephole 88 loaded value in a first and used it next
-} if notVolatile(%1 %2), canAssign(%1 'a'), operandsNotRelated(%1 %2)
-
-replace restart {
-	ld	%1,%2
-	ld	%3,%4
-	ld	%2,%1
-	ld	%4,%3
-} by {
-	ld	%1,%2
-	ld	%3,%4
-	; peephole 89 removed redundant load from %3%1 into %4%2
-} if notVolatile(%1 %2 %3 %4)
-
-replace restart {
-	push	de
-	inc	sp
-	ld	a,e
-	push	af
-	inc	sp
-} by {
-	push	de
-	; peephole 90 pushed de
-} if notUsed('a')
-
-replace restart {
-	ld	a,%1
-	sub	a,%2
-	jp	%3,%4
-	ld	a,%1
-} by {
-	ld	a,%1
-	cp	a,%2
-	jp	%3,%4
-	; peephole 91 removed load from %1 into a by replacing sub with cp
-	assert	a=%1
-} if notVolatile(%1), notUsedFrom(%4 'a')
-
-replace restart {
-	assert	a=%1
-} by {
-}
-
-replace restart {
-	rlca
-	ld	a,#0x00
-	rla
-} by {
-	rlca
-	and	a,#0x01
-	; peephole 92 replaced zero load, rla by and since rlca writes the same value to carry bit and least significant bit.
-}
-
-replace restart {
-	ld	%1,%2
-	push	%1
-	pop	%4
-	ld	%1,%3
-} by {
-	ld	%4,%2
-	; peephole 93 moved %2 directly into de instead of going through %1.
-	ld	%1,%3
-}
-
-replace restart {
-	add	a,#0x00
-	ld	%2,a
-	ld	a,%3
-	adc	a,%4
-} by {
-	; peephole 94 removed lower part of multibyte addition.
-	ld	%2,a
-	ld	a,%3
-	add	a,%4
-}
-
-replace restart {
-	ld	a, l
-	add	a, #0x%1
-	ld	e, a
-	ld	a, h
-	adc	a, #0x%2
-	ld	d, a
-} by {
-	ld	de, #0x%2%1
-	add	hl, de
-	; peephole 95 used 16-bit addition.
-	ld	e, l
-	ld	d, h
-	ld	a, h
-} if notUsed('hl')
-
-replace restart {
-	ld	a, l
-	add	a, #0x%1
-	ld	c, a
-	ld	a, h
-	adc	a, #0x%2
-	ld	b, a
-} by {
-	ld	bc, #0x%2%1
-	add	hl,bc
-	; peephole 96 used 16-bit addition.
-	ld	c, l
-	ld	b, h
-	ld	a, h
-} if notUsed('hl')
-
-
-replace restart {
-	ld	a,(hl)
-	inc	a
-	ld	(hl),a
-} by {
-	inc	(hl)
-	; peephole 97 incremented in (hl) instead of going through a.
-} if notUsed('a')
-
-replace restart {
-	ld	c,l
-	ld	b,h
-	ld	hl,#%1
-	add	hl,bc
-} by {
-	; peephole 98 removed loads by exploiting commutativity of addition.
-	ld	bc,#%1
-	add	hl,bc
-} if notUsed('bc')
-
-replace restart {
-	ld	hl,#%1
-	add	hl,%2
-	ld	bc,#%4
-	add	hl,bc
-} by {
-	; peephole 99 removed loads by exploiting commutativity of addition.
-	ld	hl,#%1 + %4
-	add	hl,%2
-} if notUsed('bc')
-
-replace restart {
-	or	a,%1
-	jp	NZ,%2
-	ld	%3,#0x00
-} by {
-	or	a,%1
-	jp	NZ,%2
-	ld	%3,a
-	; peephole 100 replaced constant #0x00 by a (which has just been tested to be #0x00).
-}
-
-replace restart {
-	and	a,%1
-	jp	NZ,%2
-	ld	%3,#0x00
-} by {
-	and	a,%1
-	jp	NZ,%2
-	ld	%3,a
-	; peephole 101 replaced constant #0x00 by a (which has just been tested to be #0x00).
-}
-
-replace restart {
-	inc	a
-	jp	NZ,%1
-	ld	%2,#0x00
-} by {
-	inc	a
-	jp	NZ,%1
-	ld	%2,a
-	; peephole 102 replaced constant #0x00 by a (which has just been tested to be #0x00).
-}
-
-replace restart {
-	or	a,%1
-	jp	NZ,%2
-	ld	a,%3
-	or	a,a
-} by {
-	or	a,%1
-	jp	NZ,%2
-	or	a,%3
-	; peephole 103 shortened or using a (which has just been tested to be #0x00).
-} if canAssign('b' %3)
-// canAssign('b' %2) is true, iff or a,%2 is possible.
-
-replace restart {
-	sub	a,%1
-	jp	NZ,%2
-	ld	a,%3
-	or	a,a
-} by {
-	sub	a,%1
-	jp	NZ,%2
-	or	a,%3
-	; peephole 104 shortened or using a (which has just been tested to be #0x00).
-} if canAssign('b' %3)
-// canAssign('b' %2) is true, iff or a,%2 is possible.
-
-replace restart {
-	ld	hl,#%1
-	add	hl,%2
-	inc	hl
-} by {
-	ld	hl,#%1+1
-	add	hl,%2
-	; peephole 106 moved increment of hl to constant.
-}
-
-replace restart {
-	call    %1
-	ret
-} by {
-	jp  %1
-	; peephole 107 replaced call at end of function by jump (tail call optimization).
-} if symmParmStack(%1)
-
-replace restart {
-	ld	%1,#%2
-	ld	%3,%4
-	ld	%1,#%2
-} by {
-	ld	%1,#%2
-	ld	%3,%4
-	; peephole 108 removed load of #%2 into %1 since it's still there.
-} if notVolatile(%1), operandsNotRelated(%3 %1)
-
-replace restart {
-	ld	hl,#%1
-	ld	de,#%1
-} by {
-	; peephole 109 used #%1 from hl for load into de.
-	ld	hl,#%1
-	ld	e,l
-	ld	d,h
-}
-
-replace restart {
 	ld	%1, a
 	ld	a, %2 (%3)
 	adc	a, #%4
@@ -1108,411 +149,3 @@
 	ld	%5, a
 	; peephole 110 loaded %6 from a directly instead of going through %1.
 } if notUsed(%1), notSame(%5 %1), notSame(%5 '(hl)' '(de)' '(bc)'), notSame(%5 %6), notSame(%6 '(hl)' '(de)' '(bc)'), notSame(%5 'a'), notSame(%6 'a')
-
-replace restart {
-	ex	de, hl
-	ld	hl, #%1
-	add	hl, de
-} by {
-	; peephole 111 removed ex exploiting commutativity of addition.
-	ld	de, #%1
-	add	hl, de
-} if notUsed('de')
-
-replace restart {
-	ld	hl, #%1
-	add	hl, %2
-	ex	de, hl
-	inc	de
-} by {
-	ld	hl, #%1+1
-	; peephole 112 moved increment to constant.
-	add	hl, %2
-	ex	de, hl
-} if notUsed('hl')
-
-replace restart {
-	ld	%1,a
-	bit	%2,%1
-} by {
-	bit	%2,a
-	; peephole 113 tested bit %2 of a directly instead of going through %1.
-} if notUsed(%1)
-
-replace restart {
-	sbc	a,%1
-	bit	7,a
-	jp	NZ,%2
-} by {
-	sbc	a,%1
-	jp	M,%2
-	; peephole 114 used sign flag instead of testing bit 7.
-}
-
-replace restart {
-	ld	%1,a
-	or	a,a
-	jp	%3,%4
-	ld	a,%1
-} by {
-	ld	%1,a
-	or	a,a
-	jp	%3,%4
-	; peephole 115 used value still in a instead of reloading from %1.
-}
-
-replace {
-	jp	%5
-	ret
-} by {
-	jp	%5
-	; peephole 116 removed unused ret.
-}
-
-replace {
-	jp	%5
-	ld	sp,ix
-	pop	ix
-	ret
-} by {
-	jp	%5
-	; peephole 117 removed unused ret.
-}
-
-replace restart {
-	or	a,%1
-	jp	NZ,%2
-	xor	a,a
-	jp	%3
-} by {
-	or	a,%1
-	jp	NZ,%2
-	; peephole 118 removed redundant zeroing of a (which has just been tested to be #0x00).
-	jp	%3
-}
-
-// These ex-generating rules should be among the last ones since ex counts as a read from both hl and de for notUsed().
-barrier
-
-replace restart {
-	ld	e,l
-	ld	d,h
-} by {
-	; peephole 119 used ex to load hl into de.
-	ex	de,hl
-} if notUsed('hl')
-
-replace restart {
-	ld	l,e
-	ld	h,d
-} by {
-	; peephole 120 used ex to load de into hl.
-	ex	de,hl
-} if notUsed('de')
-
-barrier
-
-// Should be one of the last ones. Opens the code to further peephole optimization.
-replace restart {
-%1:
-} by {
-	; peephole 121 removed unused label %1.
-} if labelRefCount(%1 0)
-
-// Ensure that all rules above see only jp, not jr.
-barrier
-
-replace {
-	add	hl,de
-	pop	de
-	jp	(hl)
-%1:
-	jp	%5
-	jp	%6
-	jp	%7
-%2:
-} by {
-	; peephole 123 removed addition using short jumps in jump-table.
-	pop	de
-	jp	(hl)
-%1:
-	jr	%5
-	jr	%6
-	jr	%7
-%2:
-} if labelJTInRange
-
-replace {
-	add	hl,de
-	jp	(hl)
-%1:
-	jp	%5
-	jp	%6
-	jp	%7
-%2:
-} by {
-	; peephole 124 removed addition using short jumps in jump-table.
-	jp	(hl)
-%1:
-	jr	%5
-	jr	%6
-	jr	%7
-%2:
-} if labelJTInRange
-
-replace {
-	add	hl,de
-	pop	de
-	jp	(hl)
-%1:
-	jp	%5
-	jp	%6
-	jp	%7
-	jp	%8
-%2:
-} by {
-	; peephole 125 removed addition using short jumps in jump-table.
-	pop	de
-	jp	(hl)
-%1:
-	jr	%5
-	jr	%6
-	jr	%7
-	jr	%8
-%2:
-} if labelJTInRange
-
-replace {
-	add	hl,de
-	jp	(hl)
-%1:
-	jp	%5
-	jp	%6
-	jp	%7
-	jp	%8
-%2:
-} by {
-	; peephole 126 removed addition using short jumps in jump-table.
-	jp	(hl)
-%1:
-	jr	%5
-	jr	%6
-	jr	%7
-	jr	%8
-%2:
-} if labelJTInRange
-
-replace {
-	add	hl,de
-	pop	de
-	jp	(hl)
-%1:
-	jp	%5
-	jp	%6
-	jp	%7
-	jp	%8
-	jp	%9
-%2:
-} by {
-	; peephole 127 removed addition using short jumps in jump-table.
-	pop	de
-	jp	(hl)
-%1:
-	jr	%5
-	jr	%6
-	jr	%7
-	jr	%8
-	jr	%9
-%2:
-} if labelJTInRange
-
-replace {
-	add	hl,de
-	jp	(hl)
-%1:
-	jp	%5
-	jp	%6
-	jp	%7
-	jp	%8
-	jp	%9
-%2:
-} by {
-	; peephole 128 removed addition using short jumps in jump-table.
-	jp	(hl)
-%1:
-	jr	%5
-	jr	%6
-	jr	%7
-	jr	%8
-	jr	%9
-%2:
-} if labelJTInRange
-
-replace {
-	add	hl,de
-	pop	de
-	jp	(hl)
-%1:
-	jp	%5
-	jp	%6
-	jp	%7
-	jp	%8
-	jp	%9
-	jp	%10
-%2:
-} by {
-	; peephole 129 removed addition using short jumps in jump-table.
-	pop	de
-	jp	(hl)
-%1:
-	jr	%5
-	jr	%6
-	jr	%7
-	jr	%8
-	jr	%9
-	jr	%10
-%2:
-} if labelJTInRange
-
-replace {
-	add	hl,de
-	jp	(hl)
-%1:
-	jp	%5
-	jp	%6
-	jp	%7
-	jp	%8
-	jp	%9
-	jp	%10
-%2:
-} by {
-	; peephole 130 removed addition using short jumps in jump-table.
-	jp	(hl)
-%1:
-	jr	%5
-	jr	%6
-	jr	%7
-	jr	%8
-	jr	%9
-	jr	%10
-%2:
-} if labelJTInRange
-
-replace {
-	add	hl,de
-	pop	de
-	jp	(hl)
-%1:
-	jp	%5
-	jp	%6
-	jp	%7
-	jp	%8
-	jp	%9
-	jp	%10
-	jp	%11
-%2:
-} by {
-	; peephole 131 removed addition using short jumps in jump-table.
-	pop	de
-	jp	(hl)
-%1:
-	jr	%5
-	jr	%6
-	jr	%7
-	jr	%8
-	jr	%9
-	jr	%10
-	jr	%11
-%2:
-} if labelJTInRange
-
-replace {
-	add	hl,de
-	jp	(hl)
-%1:
-	jp	%5
-	jp	%6
-	jp	%7
-	jp	%8
-	jp	%9
-	jp	%10
-	jp	%11
-%2:
-} by {
-	; peephole 132 removed addition using short jumps in jump-table.
-	jp	(hl)
-%1:
-	jr	%5
-	jr	%6
-	jr	%7
-	jr	%8
-	jr	%9
-	jr	%10
-	jr	%11
-%2:
-} if labelJTInRange
-
-barrier
-
-// Do all jump optimizations before replacing by ret.
-
-replace restart {
-	jp	%5
-} by {
-	ret
-	; peephole 122 replaced jump by return.
-} if labelIsReturnOnly(%5), labelRefCountChange(%5 -1)
-
-replace restart {
-	jp	%1,%5
-} by {
-	ret	%1
-	; peephole 134 replaced jump by return.
-} if labelIsReturnOnly(%5), labelRefCountChange(%5 -1)
-
-// Replace jp by ret before replacing jp by jr outside of jump tables, since using ret can reduce the number of references to jump labels.
-barrier
-
-replace {
-	jp	%5
-} by {
-	jr	%5
-	; peephole 135 changed absolute to relative unconditional jump.
-} if labelInRange(%5)
-
-replace {
-	jp	Z,%5
-} by {
-	jr	Z,%5
-	; peephole 136 changed absolute to relative conditional jump.
-} if labelInRange(%5)
-
-replace {
-	jp	NZ,%5
-} by {
-	jr	NZ,%5
-	; peephole 137 changed absolute to relative conditional jump.
-} if labelInRange(%5)
-
-replace {
-	jp	C,%5
-} by {
-	jr	C,%5
-	; peephole 138 changed absolute to relative conditional jump.
-} if labelInRange(%5)
-
-replace {
-	jp	NC,%5
-} by {
-	jr	NC,%5
-	; peephole 139 changed absolute to relative conditional jump.
-} if labelInRange(%5)
-
-replace {
-	dec b
-	jr	NZ,	%5	
-} by {
-	djnz	%5
-	; peephole 140 used djnz
-}
-
diff -Nru sdcc-4.0.0+dfsg/src/z80/peeph-z80.def sdcc-4.2.0+dfsg/src/z80/peeph-z80.def
--- sdcc-4.0.0+dfsg/src/z80/peeph-z80.def	2019-11-14 11:36:33.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/z80/peeph-z80.def	2020-07-16 03:41:15.000000000 +0000
@@ -3,7 +3,7 @@
 // Some of these peepholes could be potentially moved to peeph.def, but a
 // GBZ80 expert should have a look at them before.
 //
-// (c) Philipp Klaus Krause (pkk@spth.de, philipp@colecovision.eu) 2006 - 2015
+// (c) Philipp Klaus Krause (pkk@spth.de, philipp@colecovision.eu) 2006 - 2020
 //
 // This program is free software; you can redistribute it and/or modify it
 // under the terms of the GNU General Public License as published by the
@@ -20,2142 +20,9 @@
 // Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
 
 replace restart {
-	ld	%1, %1
-} by {
-	; peephole 0 removed redundant load from %1 into %1.
-} if notVolatile(%1)
-
-replace restart {
-	ld	%1, %2
-} by {
-	; peephole 1 removed dead load from %2 into %1.
-} if notVolatile(%1), notUsed(%1), notVolatile(%2)
-
-replace restart {
-	add	ix,sp
-} by {
-	; peephole 2 removed dead frame pointer setup.
-} if notUsed('ix')
-
-replace restart {
-	ld	%1, %2 + %3
-} by {
-	; peephole 3 removed dead load from %2 + %3 into %1.
-} if notVolatile(%1), notUsed(%1)
-// Should probably check for notVolatile(%2), too, but gives many false positives and no regression tests fail.
-
-replace restart {
-	ld	%1, (iy)
-} by {
-	ld	%1, 0 (iy)
-	; peephole 4 made 0 offset explicit.
-}
-
-replace restart {
-	ld	(iy), %1
-} by {
-	ld	0 (iy), %1
-	; peephole 5 made 0 offset explicit.
-}
-
-replace restart {
-	inc	hl
-} by {
-	; peephole 5a removed dead increment of hl.
-} if notUsed('hl')
-
-replace restart {
-	dec	hl
-} by {
-	; peephole 6 removed dead decrement of hl.
-} if notUsed('hl')
-
-replace restart {
-	ld	%1, %2 (iy)
-} by {
-	; peephole 7 removed dead load from %2 (iy) into %1.
-} if notUsed(%1)
-// Should probably check for notVolatile(), but gives many false positives and no regression tests fail.
-
-replace restart {
-	ld	%1, %2 (ix)
-} by {
-	; peephole 8 removed dead load from %2 (ix) into %1.
-} if notUsed(%1)
-
-replace restart {
-	ld	%1, %2
-	ld	%3, %1
-} by {
-	; peephole 9 loaded %3 from %2 directly instead of going through %1.
-	ld	%3, %2
-} if canAssign(%3 %2), notVolatile(%1), notUsed(%1), notSame(%3 '(hl)' '(de)' '(bc)')
-
-replace restart {
-	ld	%1, %2
-	ld	%3, %1
-} by {
-	; peephole 9a loaded %3 from %2 directly instead of going through %1.
-	ld	%3, %2
-} if canAssign(%3 %2), notVolatile(%1), notUsed(%1), canAssign('a' %1)
-
-replace restart {
-	ld	%1, hl
-	ld	hl, %1
-} by {
-	; peephole 9b reused value still in hl.
-	ld	%1, hl
-} if notVolatile(%1)
-
-replace restart {
-	ld	%1, %2
-	ld	%3, %4
-	ld	%5, %1
-} by {
-	ld	%5, %2
-	; peephole 10 loaded %5 from %2 directly instead of going through %1.
-	ld	%3, %4
-} if canAssign(%5 %2), notVolatile(%1), operandsNotRelated(%1 %4), operandsNotRelated(%1 %3), operandsNotRelated(%3 %5), operandsNotRelated(%4 %5), notUsed(%1), notSame(%3 %4 '(hl)' '(de)' '(bc)'), notVolatile(%5)
-// Rule OK unless both %5 and %4 are volatile, but we can't express that directly.
-
-replace restart {
-	ld	%3 (ix), %1
-	ld	%4 (ix), %2
-	ld	%5, %3 (ix)
-	ld	%6, %4 (ix)
-} by {
-	ld	%3 (ix), %1
-	ld	%4 (ix), %2
-	; peephole 11 loaded %5%6 from %1%2 directly instead of going through %3 (ix) %4 (ix).
-	ld	%5, %1
-	ld	%6, %2
-} if canAssign(%5 %1), canAssign(%6 %2), notSame(%5 %2)
-
-replace restart {
-	ld	%1, %2 (%3)
-	ld	%4, %1
-} by {
-	; peephole 12 loaded %2 (%3) into %4 directly instead of going through %1.
-	ld	%4, %2 (%3)
-} if canAssign(%4 %2 %3), notVolatile(%1), notUsed(%1)
-
-replace restart {
-	ld	%1, %2
-	ld	%3 (%4), %1
-} by {
-	; peephole 13 loaded %2 into %3 (%4) directly instead of going through %1.
-	ld	%3 (%4), %2
-} if canAssign(%3 %4 %2), notVolatile(%1), notUsed(%1), canAssign('a' %1)
-// canAssign ('a' %1) checks that %1 is an 8-bit value
-
-replace restart {
-	ld	%1, %2 (%3)
-	ld	%4, %5 (%6)
-	ld	%7, %1
-} by {
-	ld	%7, %2 (%3)
-	; peephole 14 loaded %2 (%3) into %7 directly instead of going through %1.
-	ld	%4, %5 (%6)
-} if canAssign(%7 %2 %3), notVolatile(%1), notUsed(%1), notSame(%1 %4), notSame(%7 %4)
-
-replace restart {
-	ld	%1, %2 (%3)
-	ld	%4, %5
-	ld	%7, %1
-} by {
-	ld	%7, %2 (%3)
-	; peephole 15 loaded %2 (%3) into %7 directly instead of going through %1.
-	ld	%4, %5
-} if canAssign(%7 %2 %3), notVolatile(%1), notUsed(%1), operandsNotRelated(%1 %5), operandsNotRelated(%7 %4), operandsNotRelated(%7 %5), notSame(%4 '(hl)' '(de)' '(bc)'), notSame(%5 '(hl)' '(de)' '(bc)' '(iy)')
-
-replace restart {
-	ld	%1,#%2
-	ld	a,%3 (%1)
-} by {
-	; peephole 16 loaded %2 into a directly instead of going through %1.
-	ld	a,(#%2 + %3)
-} if notUsed(%1)
-
-replace restart {
-	ld	hl, #%1
-	ld	a, (hl)
-} by {
-	ld	a, (#%1)
-	; peephole 17 loaded a from (#%1) directly instead of using hl.
-} if notUsed('hl')
-
-replace restart {
-	ld	hl,#%1 + %2
-	ld	a,(hl)
-} by {
-	; peephole 18 loaded %2 into a directly instead of using hl.
-	ld	a,(#%1 + %2)
-} if notUsed('hl')
-
-replace restart {
-	ld	hl,#%1
-	ld	(hl),a
-} by {
-	ld	(#%1),a
-	; peephole 19 loaded (#%1) from a directly instead of using hl.
-} if notUsed('hl')
-
-replace restart {
-	ld	hl,#%1 + %2
-	ld	(hl),a
-} by {
-	ld	(#%1 + %2),a
-	; peephole 20 loaded (#%1) from a directly instead of using hl.
-} if notUsed('hl')
-
-replace restart {
-	ld	a, %1 (%2)
-	srl	a
-	ld	%1 (%2), a
-} by {
-	srl	%1 (%2)
-	ld	a, %1 (%2)
-	; peephole 21 shifted in (%2) instead of a.
-}
-
-replace restart {
-	ld	%1,(hl)
-	ld	a,%2 (%3)
-	sub	a,%1
-} by {
-	ld	a,%2 (%3)
-	; peephole 22 used (hl) in sub directly instead of going through %1.
-	sub	a,(hl)
-} if notVolatile(%1), notUsed(%1)
-
-replace restart {
-	inc	bc
-	ld	l,c
-	ld	h,b
-} by {
-	ld	l,c
-	ld	h,b
-	; peephole 23 incremented in hl instead of bc.
-	inc	hl
-} if notUsed('bc')
-
-replace restart {
-	inc	de
-	ld	l,e
-	ld	h,d
-} by {
-	ld	l,e
-	ld	h,d
-	; peephole 24 incremented in hl instead of de.
-	inc	hl
-} if notUsed('de')
-
-replace restart {
-	ld	c,l
-	ld	b,h
-	ld	a,#%1
-	ld	(bc),a
-} by {
-	ld	c,l
-	ld	b,h
-	ld	(hl),#%1
-	; peephole 25 loaded #%1 into (hl) instead of (bc).
-} if notUsed('a')
-
-replace restart {
-	ex	de, hl
-	push	de
-} by {
-	; peephole 26 pushed hl directly instead of going through de.
-	push	hl
-} if notUsed('de'), notUsed('hl')
-
-replace restart {
-	ld	l,%1
-	ld	h,d
-	push	hl
-} by {
-	; peephole 27 pushed de instead of hl removing a load.
-	ld	e,%1
-	push	de
-} if notUsed('hl'), notUsed('e')
-
-replace restart {
-	ex	de, hl
-	push	bc
-	push	de
-} by {
-	; peephole 28 pushed hl directly instead of going through de.
-	push	bc
-	push	hl
-} if notUsed('de'), notUsed('hl')
-
-replace restart {
-	ld	l,c
-	ld	h,b
-	push	hl
-} by {
-	; peephole 29 pushed bc directly instead of going through hl.
-	push	bc
-} if notUsed('hl')
-
-replace restart {
-	ld	c,l
-	ld	b,h
-	push	%1
-	push	bc
-} by {
-	; peephole 30 pushed hl directly instead of going through bc.
-	push	%1
-	push	hl
-} if notUsed('bc'), notSame(%1 'bc')
-
-replace restart {
-	pop	de
-	ld	l, e
-	ld	h, d
-} by {
-	; peephole 31 popped hl directly instead of going through de.
-	pop	hl
-} if notUsed('de')
-
-replace restart {
-	pop	bc
-	ld	l, c
-	ld	h, b
-} by {
-	; peephole 32 popped hl directly instead of going through bc.
-	pop	hl
-} if notUsed('bc')
-
-replace restart {
-	ld	%1 (ix), %2
-	ld	%3, %1 (ix)
-} by {
-	; peephole 33 loaded %3 from %2 instead of going through %1 (ix).
-	ld	%1 (ix), %2
-	ld	%3, %2
-} if canAssign(%3 %2)
-// Don't need to check for volatile, since ix is used for the stack.
-
-replace restart {
-	ld	%1 (ix), a
-	push	de
-	ld	%2, %1 (ix)
-} by {
-	ld	%1 (ix), a
-	push	de
-	; peephole 34 loaded %2 from a instead of %1 (ix)
-	ld	%2, a
-} if canAssign(%2 'a')
-
-replace restart {
-	push	af
-	inc	sp
-	ld	a,e
-	push	af
-	inc	sp
-} by {
-	; peephole 35 pushed de instead of pushing a twice.
-	ld	d,a
-	push	de
-} if notUsed('d'), notUsed('a')
-
-replace restart {
-	push	de
-	inc	sp
-	push	af
-	inc	sp
-} by {
-	; peephole 36 pushed de instead of pushing twice.
-	ld	e, a
-	push	de
-} if notUsed('e'), notUsed('a')
-
-replace restart {
-	push	af
-	inc	sp
-	ld	a,#%1
-	push	af
-	inc	sp
-} by {
-	; peephole 37 pushed de instead of pushing a twice.
-	ld	d,a
-	ld	e,#%1
-	push	de
-} if notUsed('de')
-
-replace restart {
-	push	af
-	inc	sp
-	ld	a,#%1
-	push	af
-	inc	sp
-} by {
-	; peephole 38 pushed bc instead of pushing a twice.
-	ld	b,a
-	ld	c,#%1
-	push	bc
-} if notUsed('bc')
-
-replace restart {
-	push	hl
-	inc	sp
-	push	de
-	inc	sp
-} by {
-	ld	l, d
-	; peephole 39 combined pushing of b and d.
-	push	hl
-} if notUsed('l')
-
-replace restart {
-	push	bc
-	inc	sp
-	push	de
-	inc	sp
-} by {
-	ld	c, d
-	; peephole 40 combined pushing of b and d.
-	push	bc
-} if notUsed('c')
-
-replace restart {
-	push	de
-	inc	sp
-	push	bc
-	inc	sp
-} by {
-	ld	e, b
-	; peephole 41 combined pushing of d and b.
-	push	de
-} if notUsed('e')
-
-replace restart {
-	push	af
-	inc	sp
-	ld	a, c
-	push	af
-	inc	sp
-} by {
-	ld	b, a
-	; peephole 42 combined pushing of a and c.
-	push	bc
-} if notUsed('b'), notUsed('a')
-
-replace restart {
-	push	de
-	inc	sp
-	ld	a, c
-	push	af
-	inc	sp
-} by {
-	ld	e, c
-	; peephole 43 combined pushing of d and c.
-	push	de
-} if notUsed('e'), notUsed('a')
-
-replace restart {
-	ld	a, e
-	push	af
-	inc	sp
-	ld	a, %2 (ix)
-	push	af
-	inc	sp
-} by {
-	ld	d, e
-	ld	e, %2 (ix)
-	; peephole 44 combined pushing of e and %2 (ix).
-	push	de
-} if notUsed('d'), notUsed('e'), notUsed('a')
-
-replace restart {
-	ld	a,#%1
-	ld	d,a
-} by {
-	; peephole 45 loaded #%1 into d directly instead of going through a.
-	ld	d,#%1
-} if notUsed('a')
-
-replace restart {
-	ld	%1,a
-	ld	%2,%1
-} by {
-	; peephole 46 loaded %2 from a directly instead of going through %1.
-	ld	%2,a
-} if notUsed(%1)
-
-replace restart {
-	ld	a, %1 (%3)
-	push	af
-	inc	sp
-	ld	a, %2 (%3)
-	push	af
-	inc	sp
-} by {
-	; peephole 47 pushed %1 (%3), %2 (%3) through hl instead of af.
-	ld	h, %1 (%3)
-	ld	l, %2 (%3)
-	push	hl
-} if notUsed('a'), notUsed('hl')
-
-replace restart {
-	ld	c, l
-	ld	b, h
-	push	bc
-} by {
-	; peephole 48 pushed hl instead of bc.
-	push	hl
-} if notUsed('bc')
-
-replace restart {
-	ld	a, (hl)
-	inc	hl
-	ld	h, (hl)
-	ld	l, a
-	push	hl
-} by {
-	; peephole 49 pushed bc instead of hl.
-	ld	c, (hl)
-	inc	hl
-	ld	b, (hl)
-	push	bc
-} if notUsed('bc'), notUsed('hl')
-
-replace restart {
-	pop	%1
-	push	%1
-} by {
-	; peephole 50 eleminated dead pop/push pair.
-} if notUsed(%1)
-
-replace restart {
-	pop	%1
-	ld	%2 (ix), %3
-	push	%1
-} by {
-	; peephole 51 eleminated dead pop/push pair.
-	ld	%2 (ix), %3
-} if notUsed(%1), operandsNotRelated(%1 %3)
-
-replace restart {
-	push	hl
-	pop	bc
-} by {
-	ld	c, l
-	ld	b, h
-	; peephole 52 replaced push/pop pair by loads.
-} if notUsed('hl')
-
-replace restart {
-	push	hl
-	pop	de
-} by {
-	ld	e, l
-	ld	d, h
-	; peephole 53 replaced push/pop pair by loads.
-} if notUsed('hl')
-
-replace restart {
-	ld	iy,#%1
-	or	a,%2 (iy)
-} by {
-	; peephole 54 used hl instead of iy.
-	ld	hl,#%1 + %2
-	or	a,(hl)
-} if notUsed('iy'), notUsed('hl')
-
-replace restart {
-	ld	iy,#%1
-	ld	%2,%3 (iy)
-} by {
-	; peephole 55 used hl instead of iy.
-	ld	hl,#%1 + %3
-	ld	%2, (hl)
-} if notUsed('iy'), notUsed('hl')
-
-replace restart {
-	ld	iy,#%1
-	ld	h,%3 (iy)
-} by {
-	; peephole 56 used hl instead of iy.
-	ld	hl,#%1 + %3
-	ld	h, (hl)
-} if notUsed('iy'), notUsed('l')
-
-replace restart {
-	ld	iy,#%1
-	ld	%2 (iy), %3
-} by {
-	; peephole 57 used hl instead of iy.
-	ld	hl,#%1 + %2
-	ld	(hl), %3
-} if notUsed('iy'), notUsed('hl'), notSame(%3 'h' 'l')
-
-replace restart {
-	ld	iy,#%1
-	ld	%2,0 (iy)
-	ld	%3,1 (iy)
-} by {
-	; peephole 58 used hl instead of iy.
-	ld	hl,#%1
-	ld	%2, (hl)
-	inc	hl
-	ld	%3, (hl)
-} if notUsed('iy'), notUsed('hl'), operandsNotRelated(%2 'hl')
-
-replace restart {
-	ld	iy,#%1
-	ld	%2 (iy),%3
-	ld	l,%2 (iy)
-} by {
-	; peephole 59 used hl instead of iy.
-	ld	hl,#%1 + %2
-	ld	(hl),%3
-	ld	l,(hl)
-} if notUsed('iy'), notUsed('h')
-
-replace restart {
-	ld	iy,#%1
-	ld	%2 (%3), %4
-} by {
-	; peephole 60 used hl instead of iy.
-	ld	hl,#%1 + %2
-	ld	(hl), %4
-} if notUsed('iy'), notUsed('hl'), operandsNotRelated(%4 'hl')
-
-replace restart {
-	ld	iy,#%1
-	bit	%2,%3 (iy)
-} by {
-	; peephole 61 used hl instead of iy.
-	ld	hl,#%1+%3
-	bit	%2, (hl)
-} if notUsed('iy'), notUsed('hl')
-
-replace restart {
-	ld	iy, #%1
-	add	iy, sp
-	ld	%2, %3 (iy)
-} by {
-	; peephole 62 used hl instead of iy.
-	ld	hl, #%1+%3
-	add	hl, sp
-	ld	%2, (hl)
-} if notUsed('iy'), notUsed('hl')
-
-replace restart {
-	ld	iy, #%1
-	add	iy, sp
-	ld	%2, 0 (iy)
-	ld	%3, 1 (iy)
-} by {
-	; peephole 63 used hl instead of iy.
-	ld	hl, #%1
-	add	hl, sp
-	ld	%2, (hl)
-	inc	hl
-	ld	%3, (hl)
-} if notUsed('iy'), notUsed('hl')
-
-replace restart {
-	ld	iy, #%1
-	add	iy, sp
-	ld	l, 0 (iy)
-	ld	h, 1 (iy)
-} by {
-	; peephole 64 used hl instead of iy.
-	ld	hl, #%1
-	add	hl, sp
-	ld	a, (hl)
-	inc	hl
-	ld	h, (hl)
-	ld	l, a
-} if notUsed('iy'), notUsed('a')
-
-replace restart {
-	ld	iy, #%1
-	add	iy, sp
-	ld	0 (iy), #%2
-	ld	1 (iy), #%3
-} by {
-	; peephole 65 used hl instead of iy.
-	ld	hl, #%1
-	add	hl, sp
-	ld	(hl), #%2
-	inc	hl
-	ld	(hl), #%3
-} if notUsed('iy'), notUsed('hl')
-
-replace restart {
-	ld	iy, #%1
-	add	iy, sp
-	ld	a, 1 (iy)
-	or	a, 0 (iy)
-} by {
-	ld	hl, #%1+1
-	add	hl, sp
-	ld	a, (hl)
-	dec	hl
-	or	a, (hl)
-	; peephole 66 used hl instead of iy.
-} if notUsed('iy'), notUsed('hl')
-
-replace restart {
-	ld	iy, #%1
-	add	iy, sp
-	bit	%2, %3 (iy)
-} by {
-	ld	hl, #%1+%3
-	add	hl, sp
-	bit	%2, (hl)
-	; peephole 67 used hl instead of iy.
-} if notUsed('iy'), notUsed('hl')
-
-replace restart {
-	ld	iy, #%1
-	add	iy, sp
-	or	a, %2 (iy)
-} by {
-	ld	hl, #%1+%2
-	add	hl, sp
-	or	a, (hl)
-	; peephole 68 used hl instead of iy.
-} if notUsed('iy'), notUsed('hl')
-
-replace restart {
-	ld	c,l
-	ld	b,h
-	inc	bc
-} by {
-	; peephole 69 incremented in hl instead of bc.
-	inc	hl
-	ld	c,l
-	ld	b,h
-} if notUsed('hl')
-
-replace restart {
-	ld	iy, #%1
-	inc	%2 (iy)
-} by {
-	; peephole 70 incremented in (hl) instead of %2 (iy).
-	ld	hl, #%1+%2
-	inc	(hl)
-} if notUsed('hl'), notUsed('iy')
-
-replace restart {
-	ld	iy, #%1
-	dec	%2 (iy)
-} by {
-	; peephole 71 decremented in (hl) instead of %2 (iy).
-	ld	hl, #%1+%2
-	dec	(hl)
-} if notUsed('hl'), notUsed('iy')
-
-replace restart {
-	ld	a,%1 (%2)
-	bit	%3,a
-} by {
-	; peephole 72 tested bit %3 of %1 (%2) directly instead of going through a.
-	bit	%3,%1 (%2)
-} if notUsed('a')
-
-replace restart {
-	ld	%1, (hl)
-	bit	%2, %1
-} by {
-	; peephole 73 tested bit %2 of (hl) directly instead of going through %1.
-	bit	%2, (hl)
-} if notUsed(%1)
-
-replace restart {
-	ld	a,%1
-	bit	%2,a
-} by {
-	; peephole 74 tested bit %2 of %1 directly instead of going through a.
-	bit	%2,%1
-} if notUsed('a'), canAssign(%1 'b')
-
-replace restart {
-	ld	a, %1
-	set	%2, a
-	ld	%1, a
-} by {
-	; peephole 75 set bit %2 of %1 directly instead of going through a.
-	set	%2, %1
-	ld	a, %1
-} if canAssign(%1 'b')
-// canAssign(%1 'b') is true, iff set b, %1 is possible.
-
-replace restart {
-	ld	a, %1 (%2)
-	set	%3, a
-	ld	%1 (%2), a
-} by {
-	; peephole 76 set bit %3 of %1 (%2) directly instead of going through a.
-	set	%3, %1 (%2)
-	ld	a, %1 (%2)
-}
-
-replace restart {
-	ld	a, %1
-	res	%2, a
-	ld	%1, a
-} by {
-	; peephole 77 reset bit %2 of %1 directly instead of going through a.
-	res	%2, %1
-	ld	a, %1
-} if canAssign(%1 'b')
-// canAssign(%1 'b') is true, iff set b, %1 is possible.
-
-replace restart {
-	ld	a, %1 (%2)
-	res	%3, a
-	ld	%1 (%2), a
-} by {
-	; peephole 78 reset bit %3 of %1 (%2) directly instead of going through a.
-	res	%3, %1 (%2)
-	ld	a, %1 (%2)
-}
-
-replace restart {
-	jp	NC,%1
-	jp	%2
-%1:
-} by {
-	jp	C,%2
-	; peephole 79 removed jp by using inverse jump logic
-%1:
-} if labelRefCountChange(%1 -1)
-
-replace restart {
-	jp	C,%1
-	jp	%2
-%1:
-} by {
-	jp	NC,%2
-	; peephole 80 removed jp by using inverse jump logic
-%1:
-} if labelRefCountChange(%1 -1)
-
-replace restart {
-	jp	NZ,%1
-	jp	%2
-%1:
-} by {
-	jp	Z,%2
-	; peephole 81 removed jp by using inverse jump logic
-%1:
-} if labelRefCountChange(%1 -1)
-
-replace restart {
-	jp	Z,%1
-	jp	%2
-%1:
-} by {
-	jp	NZ,%2
-	; peephole 82 removed jp by using inverse jump logic
-%1:
-} if labelRefCountChange(%1 -1)
-
-replace restart {
-	jp	%5
-} by {
-	jp	%6
-	; peephole 83 jumped to %6 directly instead of via %5.
-} if labelIsUncondJump(), notSame(%5 %6), labelRefCountChange(%5 -1), labelRefCountChange(%6 +1)
-
-replace restart {
-	jp	%1,%5
-} by {
-	jp	%1,%6
-	; peephole 84 jumped to %6 directly instead of via %5.
-} if labelIsUncondJump(), notSame(%5 %6), labelRefCountChange(%5 -1), labelRefCountChange(%6 +1)
-
-replace restart {
-	jp	%1
-%2:
-%1:
-} by {
-   ; peephole 85 eliminated jump.
-%2:
-%1:
-} if labelRefCountChange(%1 -1)
-
-// A peephole that makes the code longer. Let's hope it's worth it in speed gain and further optimization potential.
-replace restart {
-	ld	a,#0x00
-%1:
-	bit	%2,a
-	jp	Z,%3
-} by {
-	ld	a,#0x00
-	jp	%3
-	; peephole 86 jumped directly to %3 instead of testing a first.
-%1:
-	bit	%2,a
-	jp	Z,%3
-} if labelRefCountChange(%3 +1)
-
-replace restart {
-	ld	%1, %2
-	jp	%3
-	jp	%4
-} by {
-	ld	%1, %2
-	jp	%3
-	; peephole 87 removed unreachable jump to %3.
-}
-
-replace restart {
-	ld	%1, %2
-	jp	%3
-%3:
-} by {
-	ld	%1, %2
-%3:
-	; peephole 88 removed redundant jump to %3.
-} if labelRefCountChange(%3 -1)
-
-replace restart {
-	ld	%1, #0x01
-	bit	0, %1
-	jp	Z, %2
-} by {
-	ld	%1, #0x01
-	; peephole 89 removed impossible jump to %2.
-} if labelRefCountChange(%2 -1)
-	
-replace restart {
-	rlca
-	and	a, #0x01
-	jp	Z, %1
-} by {
-	rlca
-	; peephole 90 removed and by changing jump condition.
-	jp	NC, %1
-} if notUsed('a'), notUsedFrom(%1 'a')
-
-replace restart {
-	rlca
-	and	a, #0x01
-	jp	NZ, %1
-} by {
-	rlca
-	; peephole 91 removed and by changing jump condition.
-	jp	C, %1
-} if notUsed('a'), notUsedFrom(%1 'a')
-
-replace {
-	ld	e, #0x%1
-	ld	d, #0x%2
-} by {
-	ld	de, #0x%2%1
-	; peephole 92 combined constant loads into register pair.
-}
-
-replace {
-	ld	d, #0x%1
-	ld	e, #0x%2
-} by {
-	ld	de, #0x%1%2
-	; peephole 93 combined constant loads into register pair.
-}
-
-replace {
-	ld	l, #0x%1
-	ld	h, #0x%2
-} by {
-	ld	hl, #0x%2%1
-	; peephole 94 combined constant loads into register pair.
-}
-
-replace {
-	ld	h, #0x%1
-	ld	l, #0x%2
-} by {
-	ld	hl, #0x%1%2
-	; peephole 95 combined constant loads into register pair.
-}
-
-replace {
-	ld	c, #0x%1
-	ld	b, #0x%2
-} by {
-	ld	bc, #0x%2%1
-	; peephole 96 combined constant loads into register pair.
-}
-
-replace {
-	ld	b, #0x%1
-	ld	c, #0x%2
-} by {
-	ld	bc, #0x%1%2
-	; peephole 97 combined constant loads into register pair.
-}
-
-replace restart {
-	ld	%1, a
-	ld	a, %1
-} by {
-	ld	%1, a
-	; peephole 98 removed redundant load from %1 into a.
-} if notVolatile(%1)
-// This gives many false negatives and without the test no problems are encountered in the regression tests
-// Maybe we can try this after 2.7.0 release
-
-replace restart {
-	ld	%2 (ix), %1
-	ld	%1, %2 (ix)
-} by {
-	ld	%2 (ix), %1
-	; peephole 98a removed redundant load of %1 from %2 (ix)
-}
-
-replace restart {
-	ld	%1,a
-	ld	a,%2
-	or	a,%1
-} by {
-	ld	%1,a
-	or	a,%2
-	; peephole 99 removed load by reordering or arguments.
-} if notVolatile(%1), canAssign('b' %2)
-// canAssign('b' %2) is true, iff or a,%2 is possible.
-
-replace restart {
-	ld	%1, (hl)
-	inc	hl
-	ld	a, (hl)
-	or	a, %1
-} by {
-	ld	a, (hl)
-	inc	hl
-	; peephole 99a removed load by reordering or arguments.
-	or	a, (hl)
-} if notUsed(%1)
-
-replace restart {
-	and	a,%1
-	or	a,a
-} by {
-	and	a,%1
-	; peephole 100 removed redundant or after and.
-}
-
-replace restart {
-	xor	a,%1
-	or	a,a
-} by {
-	xor	a,%1
-	; peephole 101 removed redundant or after xor.
-}
-
-replace restart {
-	xor	a,%1 (%2)
-	or	a,a
-} by {
-	xor	a,%1 (%2)
-	; peephole 102 removed redundant or after xor.
-}
-
-replace restart {
-	dec	a
-	or	a, a
-} by {
-	dec	a
-	; peephole 102a removed redundant or after dec.
-}
-
-replace restart {
-	dec	%1
-	ld	a, %1
-	or	a, a
-} by {
-	dec	%1
-	ld	a, %1
-	; peephole 102b removed redundant or after dec.
-}
-
-replace {
-	ld	%1,%2
-	ld	a,%2
-} by {
-	ld	a,%2
-	ld	%1,a
-	; peephole 103 loaded value in a first and used it next
-} if notVolatile(%1 %2), canAssign(%1 'a'), operandsNotRelated(%1 %2)
-
-replace restart {
-	ld	%1,%2
-	ld	%3,%4
-	ld	%2,%1
-	ld	%4,%3
-} by {
-	ld	%1,%2
-	ld	%3,%4
-	; peephole 104 removed redundant load from %3%1 into %4%2
-} if notVolatile(%1 %2 %3 %4)
-
-replace restart {
-	push	de
-	inc	sp
-	ld	a,e
-	push	af
-	inc	sp
-} by {
-	push	de
-	; peephole 105 pushed de
-} if notUsed('a')
-
-replace restart {
-	ld	iy,%1
-	add	iy,sp
-	ld	sp,iy
-} by {
-	ld	hl,%1
-	add	hl,sp
-	ld	sp,hl
-	; peephole 106 fixed stack using hl instead of iy.
-} if notUsed('hl'), notUsed('iy')
-
-replace restart {
-	ld	a,%1
-	sub	a,%2
-	jp	%3,%4
-	ld	a,%1
-} by {
-	ld	a,%1
-	cp	a,%2
-	jp	%3,%4
-	; peephole 107 removed load from %1 into a by replacing sub with cp
-	assert	a=%1
-} if notVolatile(%1), notUsedFrom(%4 'a')
-
-replace restart {
-	assert	a=%1
-	sub	a,%2
-	jp	%3,%4
-	ld	a,%1
-} by {
-	cp	a,%2
-	jp	%3,%4
-	; peephole 108 removed load from %1 into a by replacing sub with cp
-	assert	a=%1
-} if notUsedFrom(%4 'a')
-
-replace restart {
-	assert	a=%1
-} by {
-}
-
-replace restart {
-	rlca
-	ld	a,#0x00
-	rla
-} by {
-	rlca
-	and	a,#0x01
-	; peephole 109 replaced zero load, rla by and since rlca writes the same value to carry bit and least significant bit.
-}
-
-replace restart {
-	ld	%1,%2
-	push	%1
-	pop	%4
-	ld	%1,%3
-} by {
-	ld	%4,%2
-	; peephole 110 moved %2 directly into de instead of going through %1.
-	ld	%1,%3
-}
-
-replace restart {
-	add	a,#0x00
-	ld	%2,a
-	ld	a,%3
-	adc	a,%4
-} by {
-	; peephole 111 removed lower part of multibyte addition.
-	ld	%2,a
-	ld	a,%3
-	add	a,%4
-}
-
-replace restart {
-	ld	a, l
-	add	a, #0x%1
-	ld	e, a
-	ld	a, h
-	adc	a, #0x%2
-	ld	d, a
-} by {
-	ld	de, #0x%2%1
-	add	hl, de
-	; peephole 112 used 16-bit addition.
-	ld	e, l
-	ld	d, h
-	ld	a, h
-} if notUsed('hl')
-
-replace restart {
-	ld	a, l
-	add	a, #0x%1
-	ld	c, a
-	ld	a, h
-	adc	a, #0x%2
-	ld	b, a
-} by {
-	ld	bc, #0x%2%1
-	add	hl,bc
-	; peephole 113 used 16-bit addition.
-	ld	c, l
-	ld	b, h
-	ld	a, h
-} if notUsed('hl')
-
-replace restart {
-	ld	l,%1 (ix)
-	ld	h,%2 (ix)
-	ld	a,(hl)
-	inc	a
-	ld	l,%1 (ix)
-	ld	h,%2 (ix)
-	ld	(hl),a
-} by {
-	ld	l,%1 (ix)
-	ld	h,%2 (ix)
-	inc	(hl)
-	; peephole 114 incremented in (hl) instead of going through a.
-} if notUsed('a')
-
-replace restart {
-	ld	a,(hl)
-	inc	a
-	ld	(hl),a
-} by {
-	inc	(hl)
-	; peephole 115 incremented in (hl) instead of going through a.
-} if notUsed('a')
-
-// TODO: Check for volatile?
-replace restart {
-	ld	%1, %2 (%3)
-	inc	%1
-	ld	%2 (%3), %1
-} by {
-	inc	%2 (%3)
-	ld	%1, %2 (%3)
-	; peephole 116 incremented in %2 (%3) instead of going through %1.
-} if canAssign('a' %1)
-
-// TODO: Check for volatile?
-replace restart {
-	ld	%1, %2 (%3)
-	dec	%1
-	ld	%2 (%3), %1
-} by {
-	dec	%2 (%3)
-	ld	%1, %2 (%3)
-	; peephole 117 decremented in %2 (%3) instead of going through %1.
-} if canAssign('a' %1)
-
-replace restart {
-	ld	%1,a
-	ld	a,%2
-	add	a,%1
-} by {
-	ld	%1, a
-	; peephole 118 removed load by exploiting commutativity of addition.
-	add	a,%2
-} if notSame(%2 '(bc)' '(de)'), canAssign('b' %2)
-// canAssign('b' %2) is true, iff add a,%2 is possible.
-
-replace restart {
-	ld	c,l
-	ld	b,h
-	ld	hl,#%1
-	add	hl,bc
-} by {
-	; peephole 119 removed loads by exploiting commutativity of addition.
-	ld	bc,#%1
-	add	hl,bc
-} if notUsed('bc')
-
-replace restart {
-	ld	hl,#%1
-	add	hl,%2
-	ld	bc,#%4
-	add	hl,bc
-} by {
-	; peephole 120 removed loads by exploiting commutativity of addition.
-	ld	hl,#%1 + %4
-	add	hl,%2
-} if notUsed('bc')
-
-replace restart {
-	or	a,%1
-	jp	NZ,%2
-	ld	%3,#0x00
-} by {
-	or	a,%1
-	jp	NZ,%2
-	ld	%3,a
-	; peephole 121 replaced constant #0x00 by a (which has just been tested to be #0x00).
-}
-
-replace restart {
-	and	a,%1
-	jp	NZ,%2
-	ld	%3,#0x00
-} by {
-	and	a,%1
-	jp	NZ,%2
-	ld	%3,a
-	; peephole 122 replaced constant #0x00 by a (which has just been tested to be #0x00).
-}
-
-replace restart {
-	sub	a,%1
-	jp	NZ,%2
-	ld	%3,#0x00
-} by {
-	sub	a,%1
-	jp	NZ,%2
-	ld	%3,a
-	; peephole 123 replaced constant #0x00 by a (which has just been tested to be #0x00).
-}
-
-replace restart {
-	inc	a
-	jp	NZ,%1
-	ld	%2,#0x00
-} by {
-	inc	a
-	jp	NZ,%1
-	ld	%2,a
-	; peephole 124 replaced constant #0x00 by a (which has just been tested to be #0x00).
-}
-
-replace restart {
-	dec	a
-	jp	NZ,%1
-	ld	%2,#0x00
-} by {
-	dec	a
-	jp	NZ,%1
-	ld	%2,a
-	; peephole 125 replaced constant #0x00 by a (which has just been tested to be #0x00).
-}
-
-replace restart {
-	or	a,%1
-	jp	NZ,%2
-	ld	a,%3
-	or	a,a
-} by {
-	or	a,%1
-	jp	NZ,%2
-	or	a,%3
-	; peephole 126 shortened or using a (which has just been tested to be #0x00).
-} if canAssign('b' %3)
-// canAssign('b' %2) is true, iff or a,%2 is possible.
-
-replace restart {
-	sub	a,%1
-	jp	NZ,%2
-	ld	a,%3
-	or	a,a
-} by {
-	sub	a,%1
-	jp	NZ,%2
-	or	a,%3
-	; peephole 127 shortened or using a (which has just been tested to be #0x00).
-} if canAssign('b' %3)
-// canAssign('b' %2) is true, iff or a,%2 is possible.
-
-replace restart {
-	ld	hl,#%1
-	add	hl,%2
-	inc	hl
-} by {
-	ld	hl,#%1+1
-	add	hl,%2
-	; peephole 129 moved increment of hl to constant.
-}
-
-replace restart {
-	push	hl
-	pop	iy
-	pop	hl
-	inc	iy
-} by {
-	inc	hl
-	push	hl
-	pop	iy
-	pop	hl
-	; peephole 130 incremented in hl instead of iy.
-}
-
-replace restart {
-	push	bc
-	pop	iy
-	inc	iy
-} by {
-	inc	bc
-	push	bc
-	pop	iy
-	; peephole 131 incremented in bc instead of iy.
-} if notUsed('bc')
-
-replace restart {
-	ld	hl,%1
-	add	hl,%2
-	push	hl
-	pop	iy
-} by {
-	ld	iy,%1
-	add	iy,%2
-	; peephole 132 added in iy instead of hl.
-} if notUsed('hl'), notSame(%2 'hl')
-
-replace restart {
-	pop	af
-	ld	sp,%1
-} by {
-	; peephole 133 removed redundant pop af.
-	ld	sp,%1
-} if notUsed('a')
-
-replace restart {
-	inc	sp
-	ld	sp,%1
-} by {
-	; peephole 134 removed redundant inc sp.
-	ld	sp,%1
-} if notUsed('a')
-
-replace restart {
-	call    %1
-	ret
-} by {
-	jp  %1
-	; peephole 135 replaced call at end of function by jump (tail call optimization).
-} if symmParmStack(%1)
-
-// Callee saves ix.
-replace restart {
-	call	%1
-	pop	ix
-	ret
-} by {
-	pop	ix
-	jp	%1
-	; peephole 136 replaced call at end of function by jump moving call beyond pop ix (tail call optimization).
-} if symmParmStack(%1)
-
-replace restart {
-	ld	%1,#%2
-	ld	%3,%4
-	ld	%1,#%2
-} by {
-	ld	%1,#%2
-	ld	%3,%4
-	; peephole 137 removed load of #%2 into %1 since it's still there.
-} if notVolatile(%1), operandsNotRelated(%3 %1)
-
-replace restart {
-	ld	hl,#%1
-	ld	de,#%1
-} by {
-	; peephole 138 used #%1 from hl for load into de.
-	ld	hl,#%1
-	ld	e,l
-	ld	d,h
-}
-
-replace restart {	
-	ld      sp,hl
-	ld      hl,#0x0002
-	add     hl,sp
-} by {
-	ld	sp, hl
-	inc	hl
-	inc	hl
-	; peephole 139 replaced addition by increment.
-}
-
-replace restart {
-	ex	de, hl
-	ld	hl, #%1
-	add	hl, de
-} by {
-	; peephole 140 removed ex exploiting commutativity of addition.
-	ld	de, #%1
-	add	hl, de
-} if notUsed('de')
-
-replace restart {
-	ld	hl, #%1
-	add	hl, %2
-	ex	de, hl
-	inc	de
-} by {
-	ld	hl, #%1+1
-	; peephole 141 moved increment to constant.
-	add	hl, %2
-	ex	de, hl
-} if notUsed('hl')
-
-replace restart {
-	pop	af
-	push	hl
-} by {
-	; peephole 142 used ex to move hl onto the stack.
-	ex	(sp),hl
-} if notUsed('a'), notUsed('hl')
-
-replace restart {
-	pop	af
-	ld	hl, #%1
-	push	hl
-} by {
-	ld	hl, #%1
-	; peephole 143 used ex to move hl onto the stack.
-	ex	(sp),hl
-} if notUsed('a'), notUsed('hl')
-
-replace restart {
-	pop	af
-	inc	sp
-	ld	hl,#%1
-	push	hl
-} by {
-	inc	sp
-	ld	hl,#%1
-	; peephole 144 used ex to move #%1 onto the stack.
-	ex	(sp),hl
-} if notUsed('a'), notUsed('hl')
-
-replace restart {
-	pop	af
-	inc	sp
-	ld	h, %1 (ix)
-	ld	l, %2 (ix)
-	push	hl
-} by {
-	inc	sp
-	ld	h, %1 (ix)
-	ld	l, %2 (ix)
-	; peephole 145 used ex to move %1 (ix) %2 (ix) onto the stack.
-	ex	(sp),hl
-} if notUsed('a'), notUsed('hl')
-
-replace restart {
-	pop	af
-	ld	a,#%1
-	push	af
-	inc	sp
-} by {
-	ld	h,#%1
-	ex	(sp),hl
-	; peephole 146 used ex to move #%1 onto the stack.
-	inc	sp
-} if notUsed('a'), notUsed('hl')
-
-replace restart {
-	ld	%1,#%2
-	ld	%3 (%1),a
-%4:
-	ld	%1,%5
-} by {
-	ld	(#%2 + %3),a
-	; peephole 147 directly used #%2 instead of going through %1 using indirect addressing.
-%4:
-	ld	%1,%5
-}
-
-replace restart {
-	pop	af
-	ld	%1,#%2
-	ld	%3 (%1),%4
-	ld	%1,#%5
-} by {
-	ld	a,%4
-	ld	(#%2 + %3),a
-	; peephole 148 used #%2 directly instead of going through %1 using indirect addressing.
-	pop	af
-	ld	%1,#%5
-} if notSame(%3 'a')
-
-replace restart {
-	ld	%1,a
-	bit	%2,%1
-} by {
-	bit	%2,a
-	; peephole 149 tested bit %2 of a directly instead of going through %1.
-} if notUsed(%1)
-
-replace restart {
-	sbc	a,%1
-	bit	7,a
-	jp	NZ,%2
-} by {
-	sbc	a,%1
-	jp	M,%2
-	; peephole 150 used sign flag instead of testing bit 7.
-}
-
-replace restart {
-	ld	%1,a
-	or	a,a
-	jp	%3,%4
-	ld	a,%1
-} by {
-	ld	%1,a
-	or	a,a
-	jp	%3,%4
-	; peephole 151 used value still in a instead of reloading from %1.
-}
-
-replace {
-	jp	%5
-	ret
-} by {
-	jp	%5
-	; peephole 152 removed unused ret.
-}
-
-replace {
-	jp	%5
-	ld	sp,ix
-	pop	ix
-	ret
-} by {
-	jp	%5
-	; peephole 153 removed unused ret.
-}
-
-replace restart {
-	or	a,%1
-	jp	NZ,%2
-	xor	a,a
-	jp	%3
-} by {
-	or	a,%1
-	jp	NZ,%2
-	; peephole 155 removed redundant zeroing of a (which has just been tested to be #0x00).
-	jp	%3
-}
-
-replace restart {
-	dec	hl
-	inc	hl
-} by {
-	; peephole 155a removed inc hl / dec hl pair.
-}
-
-replace restart {
-	dec	hl
-	inc	bc
-	inc	hl
-} by {
-	inc	bc
-	; peephole 155b removed inc hl / dec hl pair.
-}
-
-replace restart {
-	dec	hl
-	inc	de
-	inc	hl
-} by {
-	inc	de
-	; peephole 155v removed inc hl / dec hl pair.
-}
-
-replace restart {
-	jp	Z, %2
-	ld	a, #%3
-	jp	%1
-%2:
-	ld	a, #%4
-%1:
-} by {
-	ld	a, #%3
-	jp	NZ, %1
-%2:
-	ld	a, #%4
-	; peephole 168z used double assignment in case of Z condition.
-%1:
-} if labelRefCountChange(%2 -1) 
-
-replace restart {
-	jp	NZ, %2
-	ld	a, #%3
-	jp	%1
-%2:
-	ld	a, #%4
-%1:
-} by {
-	ld	a, #%3
-	jp	Z, %1
-%2:
-	ld	a, #%4
-	; peephole 168nz used double assignment in case of NZ condition.
-%1:
-} if labelRefCountChange(%2 -1) 
-
-replace restart {
-	jp	Z, %2
-	ld	a, #%3
-	jp	%1
-%2:
-	xor	a, a
-%1:
-} by {
-	ld	a, #%3
-	jp	NZ, %1
-	; peephole 169xz used double assignment in case of Z condition.
-%2:
-	xor	a, a
-%1:
-} if labelRefCountChange(%2 -1)
-
-replace restart {
-	jp	NZ, %2
-	ld	a, #%3
-	jp	%1
-%2:
-	xor	a, a
-%1:
-} by {
-	ld	a, #%3
-	jp	Z, %1
-	; peephole 169xnz used double assignment in case of NZ condition.
-%2:
 	xor	a, a
-%1:
-} if labelRefCountChange(%2 -1)
-
-replace restart {
-	jp	Z, %2
-	ld	c, #%3
-	jp	%1
-%2:
-	ld	c, #%4
-%1:
-} by {
-	ld	c, #%3
-	jp	NZ, %1
-%2:
-	ld	c, #%4
-	; peephole 170z used double assignment in case of Z condition.
-%1:
-} if labelRefCountChange(%2 -1)
-
-replace restart {
-	jp	NZ, %2
-	ld	c, #%3
-	jp	%1
-%2:
-	ld	c, #%4
-%1:
-} by {
-	ld	c, #%3
-	jp	Z, %1
-%2:
-	ld	c, #%4
-	; peephole 170nz used double assignment in case of NZ condition.
-%1:
-} if labelRefCountChange(%2 -1)
-
-replace restart {
-	jp	Z, %2
-	ld	e, #%3
-	jp	%1
-%2:
-	ld	e, #%4
-%1:
-} by {
-	ld	e, #%3
-	jp	NZ, %1
-%2:
-	ld	e, #%4
-	; peephole 171z used double assignment in case of Z condition.
-%1:
-} if labelRefCountChange(%2 -1)
-
-replace restart {
-	jp	NZ, %2
-	ld	e, #%3
-	jp	%1
-%2:
-	ld	e, #%4
-%1:
-} by {
-	ld	e, #%3
-	jp	Z, %1
-%2:
-	ld	e, #%4
-	; peephole 171nz used double assignment in case of NZ condition.
-%1:
-} if labelRefCountChange(%2 -1)
-
-replace restart {
-	jp	Z, %2
-	ld	l, #%3
-	jp	%1
-%2:
-	ld	l, #%4
-%1:
-} by {
-	ld	l, #%3
-	jp	NZ, %1
-%2:
-	ld	l, #%4
-	; peephole 172z used double assignment in case of Z condition.
-%1:
-} if labelRefCountChange(%2 -1)
-
-replace restart {
-	jp	NZ, %2
-	ld	l, #%3
-	jp	%1
-%2:
-	ld	l, #%4
-%1:
-} by {
-	ld	l, #%3
-	jp	Z, %1
-%2:
-	ld	l, #%4
-	; peephole 172nz used double assignment in case of NZ condition.
-%1:
-} if labelRefCountChange(%2 -1)
-
-// These ex-generating rules should be among the last ones since ex counts as a read from both hl and de for notUsed().
-barrier
-
-replace restart {
-	ld	e,l
-	ld	d,h
-} by {
-	; peephole 156 used ex to load hl into de.
-	ex	de,hl
-} if notUsed('hl')
-
-replace restart {
-	ld	l,e
-	ld	h,d
-} by {
-	; peephole 157 used ex to load de into hl.
-	ex	de,hl
-} if notUsed('de')
-
-barrier
-
-// Should be one of the last ones. Opens the code to further peephole optimization.
-replace restart {
-%1:
-} by {
-	; peephole 158 removed unused label %1.
-} if labelRefCount(%1 0)
-
-// Ensure that all rules above see only jp, not jr.
-barrier
-
-replace {
-	add	hl,de
-	pop	de
-	jp	(hl)
-%1:
-	jp	%5
-	jp	%6
-	jp	%7
-%2:
-} by {
-	; peephole 159-3 removed addition using short jumps in jump-table.
-	pop	de
-	jp	(hl)
-%1:
-	jr	%5
-	jr	%6
-	jr	%7
-%2:
-} if labelJTInRange
-
-replace {
-	add	hl,de
-	jp	(hl)
-%1:
-	jp	%5
-	jp	%6
-	jp	%7
-%2:
-} by {
-	; peephole 159-3' removed addition using short jumps in jump-table.
-	jp	(hl)
-%1:
-	jr	%5
-	jr	%6
-	jr	%7
-%2:
-} if labelJTInRange
-
-replace {
-	add	hl,de
-	pop	de
-	jp	(hl)
-%1:
-	jp	%5
-	jp	%6
-	jp	%7
-	jp	%8
-%2:
-} by {
-	; peephole 159-4 removed addition using short jumps in jump-table.
-	pop	de
-	jp	(hl)
-%1:
-	jr	%5
-	jr	%6
-	jr	%7
-	jr	%8
-%2:
-} if labelJTInRange
-
-replace {
-	add	hl,de
-	jp	(hl)
-%1:
-	jp	%5
-	jp	%6
-	jp	%7
-	jp	%8
-%2:
-} by {
-	; peephole 159-4' removed addition using short jumps in jump-table.
-	jp	(hl)
-%1:
-	jr	%5
-	jr	%6
-	jr	%7
-	jr	%8
-%2:
-} if labelJTInRange
-
-replace {
-	add	hl,de
-	pop	de
-	jp	(hl)
-%1:
-	jp	%5
-	jp	%6
-	jp	%7
-	jp	%8
-	jp	%9
-%2:
-} by {
-	; peephole 159-5 removed addition using short jumps in jump-table.
-	pop	de
-	jp	(hl)
-%1:
-	jr	%5
-	jr	%6
-	jr	%7
-	jr	%8
-	jr	%9
-%2:
-} if labelJTInRange
-
-replace {
-	add	hl,de
-	jp	(hl)
-%1:
-	jp	%5
-	jp	%6
-	jp	%7
-	jp	%8
-	jp	%9
-%2:
-} by {
-	; peephole 159-5' removed addition using short jumps in jump-table.
-	jp	(hl)
-%1:
-	jr	%5
-	jr	%6
-	jr	%7
-	jr	%8
-	jr	%9
-%2:
-} if labelJTInRange
-
-replace {
-	add	hl,de
-	pop	de
-	jp	(hl)
-%1:
-	jp	%5
-	jp	%6
-	jp	%7
-	jp	%8
-	jp	%9
-	jp	%10
-%2:
-} by {
-	; peephole 159-6 removed addition using short jumps in jump-table.
-	pop	de
-	jp	(hl)
-%1:
-	jr	%5
-	jr	%6
-	jr	%7
-	jr	%8
-	jr	%9
-	jr	%10
-%2:
-} if labelJTInRange
-
-replace {
-	add	hl,de
-	jp	(hl)
-%1:
-	jp	%5
-	jp	%6
-	jp	%7
-	jp	%8
-	jp	%9
-	jp	%10
-%2:
-} by {
-	; peephole 159-6' removed addition using short jumps in jump-table.
-	jp	(hl)
-%1:
-	jr	%5
-	jr	%6
-	jr	%7
-	jr	%8
-	jr	%9
-	jr	%10
-%2:
-} if labelJTInRange
-
-replace {
-	add	hl,de
-	pop	de
-	jp	(hl)
-%1:
-	jp	%5
-	jp	%6
-	jp	%7
-	jp	%8
-	jp	%9
-	jp	%10
-	jp	%11
-%2:
-} by {
-	; peephole 159-7 removed addition using short jumps in jump-table.
-	pop	de
-	jp	(hl)
-%1:
-	jr	%5
-	jr	%6
-	jr	%7
-	jr	%8
-	jr	%9
-	jr	%10
-	jr	%11
-%2:
-} if labelJTInRange
-
-replace {
-	add	hl,de
-	jp	(hl)
-%1:
-	jp	%5
-	jp	%6
-	jp	%7
-	jp	%8
-	jp	%9
-	jp	%10
-	jp	%11
-%2:
-} by {
-	; peephole 159-7' removed addition using short jumps in jump-table.
-	jp	(hl)
-%1:
-	jr	%5
-	jr	%6
-	jr	%7
-	jr	%8
-	jr	%9
-	jr	%10
-	jr	%11
-%2:
-} if labelJTInRange
-
-barrier
-
-// Do all jump optimizations before replacing by ret.
-
-replace restart {
-	jp	%5
-} by {
-	ret
-	; peephole 160 replaced jump by return.
-} if labelIsReturnOnly(%5), labelRefCountChange(%5 -1)
-
-replace restart {
-	jp	%1,%5
-} by {
-	ret	%1
-	; peephole 161 replaced jump by return.
-} if labelIsReturnOnly(%5), labelRefCountChange(%5 -1)
-
-// Replace jp by ret before replacing jp by jr outside of jump tables, since using ret can reduce the number of references to jump labels.
-barrier
-
-replace {
-	jp	%5
-} by {
-	jr	%5
-	; peephole 162 changed absolute to relative unconditional jump.
-} if labelInRange(%5)
-
-replace {
-	jp	Z,%5
-} by {
-	jr	Z,%5
-	; peephole 163 changed absolute to relative conditional jump.
-} if labelInRange(%5)
-
-replace {
-	jp	NZ,%5
-} by {
-	jr	NZ,%5
-	; peephole 164 changed absolute to relative conditional jump.
-} if labelInRange(%5)
-
-replace {
-	jp	C,%5
-} by {
-	jr	C,%5
-	; peephole 165 changed absolute to relative conditional jump.
-} if labelInRange(%5)
-
-replace {
-	jp	NC,%5
-} by {
-	jr	NC,%5
-	; peephole 166 changed absolute to relative conditional jump.
-} if labelInRange(%5)
-
-replace {
-	dec b
-	jr	NZ,	%5	
+	ld	%1 (%2), a
 } by {
-	djnz	%5
-	; peephole 167 used djnz
-}
-
-barrier
+	ld	%1 (%2), #0
+	; peephole 178 direct load zero constant to memory addressed by index register
+} if notUsed('a'), canAssign(%1 %2 '#0')
diff -Nru sdcc-4.0.0+dfsg/src/z80/peeph-z80n.def sdcc-4.2.0+dfsg/src/z80/peeph-z80n.def
--- sdcc-4.0.0+dfsg/src/z80/peeph-z80n.def	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/z80/peeph-z80n.def	2020-08-04 09:44:30.000000000 +0000
@@ -0,0 +1,27 @@
+// peeph-z80n.def - Z80N specific peephole rules
+//
+// (c) Philipp Klaus Krause (pkk@spth.de, philipp@colecovision.eu) 2006 - 2020
+//
+// This program is free software; you can redistribute it and/or modify it
+// under the terms of the GNU General Public License as published by the
+// Free Software Foundation; either version 2, or (at your option) any
+// later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+replace restart {
+	push	#%1
+} by {
+	;Z80N peephole 1: replace push %1 by ld %2,#%1 / push %2
+	ld	%2, #%1
+	push	%2
+} if unusedReg(%2 'bc' 'de' 'hl')
+
+barrier
diff -Nru sdcc-4.0.0+dfsg/src/z80/ralloc2.cc sdcc-4.2.0+dfsg/src/z80/ralloc2.cc
--- sdcc-4.0.0+dfsg/src/z80/ralloc2.cc	2019-12-12 09:59:51.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/z80/ralloc2.cc	2021-12-10 14:48:15.000000000 +0000
@@ -27,7 +27,7 @@
 extern "C"
 {
   #include "z80.h"
-  unsigned char dryZ80iCode (iCode * ic);
+  float dryZ80iCode (iCode * ic);
   bool z80_assignment_optimal;
   bool should_omit_frame_ptr;
 }
@@ -91,7 +91,7 @@
 
               if(byteregs[0] == REG_A)
                 c -= 0.4f;
-              else if(OPTRALLOC_HL && byteregs[0] == REG_L)
+              else if(byteregs[0] == REG_L)
                 c -= 0.1f;
               else if((OPTRALLOC_IY && byteregs[0] == REG_IYL) || byteregs[0] == REG_IYH)
                 c += 0.1f;
@@ -399,8 +399,8 @@
   if(!result || !IS_SYMOP(result))
     return;
     
-  if(!(ic->op == UNARYMINUS || ic->op == '+' || ic->op == '-' || ic->op == '^' || ic->op == '|' || ic->op == BITWISEAND)) 
-    return; // Code generation can always handle all other operations. Todo: Handle ^, |, BITWISEAND and float UNARYMINUS there as well.
+  if(!(ic->op == UNARYMINUS || ic->op == '+' || ic->op == '-' || ic->op == '|' || ic->op == BITWISEAND)) 
+    return; // Code generation can always handle all other operations. Todo: Handle |, BITWISEAND and float UNARYMINUS there as well.
    
   operand_map_t::const_iterator oir, oir_end, oirs; 
   boost::tie(oir, oir_end) = n.operands.equal_range(OP_SYMBOL_CONST(result)->key);
@@ -493,6 +493,12 @@
 
   if(OP_SYMBOL_CONST(o)->_isparm && !IS_REGPARM (OP_SYMBOL_CONST(o)->etype))
     return(true);
+    
+  if(IS_TRUE_SYMOP(o) && OP_SYMBOL_CONST(o)->onStack)
+    return(true);
+    
+  if(OP_SYMBOL_CONST(o)->nRegs > 4) // currently all variables > 4 Byte are spilt in ralloc.c.
+    return(true);
 
   operand_map_t::const_iterator oi, oi_end;
   for(boost::tie(oi, oi_end) = G[i].operands.equal_range(OP_SYMBOL_CONST(o)->key); oi != oi_end; ++oi)
@@ -547,7 +553,7 @@
   if(SKIP_IC2(ic))
     return(true);
 
-  bool exstk = (should_omit_frame_ptr || (currFunc && currFunc->stack > 127) || IS_GB);
+  bool exstk = (should_omit_frame_ptr || (currFunc && currFunc->stack > 127) || IS_SM83);
 
   //std::cout << "Ainst_ok at " << G[i].ic->key << ": A = (" << ia.registers[REG_A][0] << ", " << ia.registers[REG_A][1] << "), inst " << i << ", " << ic->key << "\n";
 
@@ -575,10 +581,16 @@
     IS_TRUE_SYMOP (right) && IN_REGSP (SPEC_OCLS (OP_SYMBOL (right)->etype))))
     return(false);
 
-  if (ic->op == '^' || ic->op == BITWISEAND || ic->op == '|' || ic->op == '~') // Codegen can handle it all.
+  // For some iCodes, we can handle anything.
+  if(ic->op == '~' || ic->op == IPUSH || ic->op == LABEL || ic->op == GOTO ||
+    ic->op == '^' || ic->op == '|' || ic->op == BITWISEAND ||
+    ic->op == GETBYTE || ic->op == GETWORD || ic->op == SWAP && (getSize(operandType(IC_RESULT (ic))) == 1 || operand_in_reg(result, ia, i, G)) ||
+    ic->op == LEFT_OP ||
+    ic->op == '=' && !POINTER_SET (ic) || ic->op == CAST)
     return(true);
 
-  if (ic->op == RIGHT_OP && getSize(operandType(result)) == 1 && IS_OP_LITERAL(right))
+  if (ic->op == RIGHT_OP && getSize(operandType(result)) == 1 && IS_OP_LITERAL(right) ||
+    (ic->op == RRC || ic->op == RLC) && getSize(operandType(result)) == 1)
     return(true);
 
   // Can use non-destructive cp on == and < (> might swap operands).
@@ -590,11 +602,11 @@
   const cfg_dying_t &dying = G[i].dying;
   const bool dying_A = result_in_A || dying.find(ia.registers[REG_A][1]) != dying.end() || dying.find(ia.registers[REG_A][0]) != dying.end();
 
-  if((ic->op == '+' || ic->op == '-' && !operand_in_reg(right, REG_A, ia, i, G) || ic->op == UNARYMINUS && !IS_GB) &&
+  if((ic->op == '+' || ic->op == '-' && !operand_in_reg(right, REG_A, ia, i, G) || ic->op == UNARYMINUS && !IS_SM83) &&
     getSize(operandType(IC_RESULT(ic))) == 1 && dying_A)
     return(true);
 
-  if((ic->op == '+' || ic->op == '-' && !operand_in_reg(right, REG_A, ia, i, G) || ic->op == UNARYMINUS && !IS_GB || ic->op == '~') && // First byte of input and last byte of output may be in A.
+  if((ic->op == '+' || ic->op == '-' && !operand_in_reg(right, REG_A, ia, i, G) || ic->op == UNARYMINUS && !IS_SM83) && // First byte of input and last byte of output may be in A.
     IS_ITEMP(result) && dying_A &&
     (IS_ITEMP(left) || IS_OP_LITERAL(left) || operand_on_stack(left, a, i, G)) &&
     (!right || IS_ITEMP(right) || IS_OP_LITERAL(right) || operand_on_stack(right, a, i, G)))
@@ -611,39 +623,23 @@
     operand_byte_in_reg(left, 0, REG_A, a, i, G) || getSize(operandType(left)) >= 2 && !IS_FLOAT (operandType(left)) && operand_byte_in_reg(left, 1, REG_A, a, i, G)))
     return(true);
 
-  // Plain assignment between registers
-  if(ic->op == CAST && getSize(operandType(IC_RESULT(ic))) == 1 &&
-    (operand_in_reg(result, REG_B, ia, i, G) || operand_in_reg(result, REG_C, ia, i, G) || operand_in_reg(result, REG_D, ia, i, G) || operand_in_reg(result, REG_E, ia, i, G) || operand_in_reg(result, REG_A, ia, i, G)) &&
-    (operand_in_reg(result, REG_B, ia, i, G) || operand_in_reg(result, REG_C, ia, i, G) || operand_in_reg(result, REG_D, ia, i, G) || operand_in_reg(result, REG_E, ia, i, G)))
-    return(true);
-
-  // Any input byte in A is ok, when all operands are registers other than iy.
-  if(ic->op == CAST && operand_in_reg(right, REG_A, ia, i, G) &&
-    !operand_in_reg(result, REG_A, ia, i, G) && (operand_in_reg(result, REG_C, ia, i, G) || operand_in_reg(result, REG_E, ia, i, G) || operand_in_reg(result, REG_L, ia, i, G)))
+  // Can test register via inc / dec.
+  if(ic->op == IFX && getSize(operandType(left)) == 1 &&
+    (operand_byte_in_reg(left, 0, REG_B, a, i, G) || operand_byte_in_reg(left, 0, REG_C, a, i, G) || operand_byte_in_reg(left, 0, REG_D, a, i, G) || operand_byte_in_reg(left, 0, REG_E, a, i, G) || operand_byte_in_reg(left, 0, REG_H, a, i, G) || operand_byte_in_reg(left, 0, REG_L, a, i, G)))
     return(true);
 
   // Last byte of output may be in A.
-  if((ic->op == GET_VALUE_AT_ADDRESS || ic->op == CAST && !operand_in_reg(right, REG_A, ia, i, G)) && IS_ITEMP(result) && operand_byte_in_reg(result, getSize(operandType(IC_RESULT(ic))) - 1, REG_A, a, i, G))
-    return(true);
-
-  if (ic->op == LEFT_OP && getSize(operandType(IC_RESULT(ic))) == 2 && IS_OP_LITERAL(right) && byteOfVal (OP_VALUE (IC_RIGHT(ic)), 0) == 7)
-    {
-      if(!operand_in_reg(left, REG_A, ia, i, G) || dying_A)
-        return(true);
-    }
-
-  // Left shift of 1 byte can always handle a.
-  if (ic->op == LEFT_OP && getSize(operandType(IC_RESULT(ic))) == 1 && IS_OP_LITERAL(right))
+  if(ic->op == GET_VALUE_AT_ADDRESS && IS_ITEMP(result) && operand_byte_in_reg(result, getSize(operandType(IC_RESULT(ic))) - 1, REG_A, a, i, G))
     return(true);
 
   // inc / dec does not affect a.
-  if ((ic->op == '+' || ic->op == '-') && IS_OP_LITERAL(right) && ulFromVal (OP_VALUE (IC_RIGHT(ic))) <= 2 &&
+  if ((ic->op == '+' || ic->op == '-') && IS_OP_LITERAL(right) && ulFromVal (OP_VALUE_CONST (right)) <= 2 &&
     (getSize(operandType(IC_RESULT(ic))) == 2 && operand_is_pair(IC_RESULT(ic), a, i, G) || getSize(operandType(IC_RESULT(ic))) == 1 && operand_in_reg(result, ia, i, G) && operand_in_reg(result, ia, i, G)))
     return(true);
 
   if(ic->op == GET_VALUE_AT_ADDRESS) // Any register can be assigned from (hl) and (iy), so we don't need to go through a then.
     return(!IS_BITVAR(getSpec(operandType(result))) &&
-    (getSize(operandType(result)) == 1 || operand_is_pair(left, a, i, G) && (operand_in_reg(left, REG_L, ia, i, G) && !ulFromVal (OP_VALUE (IC_RIGHT(ic))) || operand_in_reg(left, REG_IYL, ia, i, G) && ulFromVal (OP_VALUE (IC_RIGHT(ic))) <= 127)));
+    (getSize(operandType(result)) == 1 || operand_is_pair(left, a, i, G) && (operand_in_reg(left, REG_L, ia, i, G) && !ulFromVal (OP_VALUE_CONST (right)) || operand_in_reg(left, REG_IYL, ia, i, G) && ulFromVal (OP_VALUE_CONST (right)) <= 127)));
 
   if(ic->op == '=' && POINTER_SET (ic) && // Any register can be assigned to (hl) and (iy), so we don't need to go through a then.
     !(IS_BITVAR(getSpec(operandType (result))) || IS_BITVAR(getSpec(operandType (right)))) &&
@@ -666,28 +662,10 @@
     {
       // Variable in A is not used by this instruction
       if(ic->op == '+' && IS_ITEMP (left) && IS_ITEMP (IC_RESULT(ic)) && IS_OP_LITERAL (right) &&
-          ulFromVal (OP_VALUE (IC_RIGHT(ic))) == 1 &&
+          ulFromVal (OP_VALUE_CONST (right)) == 1 &&
           OP_KEY (IC_RESULT(ic)) == OP_KEY (IC_LEFT(ic)))
         return(true);
 
-      if((ic->op == '=' || ic->op == CAST) && !POINTER_SET (ic) && isOperandEqual (result, right))
-        return(true);
-
-      if((ic->op == '=' || ic->op == CAST) && !POINTER_SET (ic) && !(ic->op == CAST && IS_BOOL (operandType (result))) &&
-        (operand_in_reg(right, REG_A, ia, i, G) || operand_in_reg(right, REG_B, ia, i, G) || operand_in_reg(right, REG_C, ia, i, G) || operand_in_reg(right, REG_D, ia, i, G) || operand_in_reg(right, REG_E, ia, i, G) || operand_in_reg(right, REG_H, ia, i, G) || operand_in_reg(right, REG_L, ia, i, G)) &&
-        (operand_in_reg(right, REG_A, ia, i, G) || operand_in_reg(result, REG_B, ia, i, G) || operand_in_reg(result, REG_C, ia, i, G) || operand_in_reg(result, REG_D, ia, i, G) || operand_in_reg(result, REG_E, ia, i, G) || operand_in_reg(right, REG_H, ia, i, G) || operand_in_reg(right, REG_L, ia, i, G)))
-        return(true);
-
-      if(ic->op == GOTO || ic->op == LABEL)
-        return(true);
-
-      if(ic->op == IPUSH && getSize(operandType(IC_LEFT(ic))) <= 2 &&
-        (operand_in_reg(left, REG_A, ia, i, G) ||
-        operand_in_reg(left, REG_B, ia, i, G) && (getSize(operandType(left)) < 2 || operand_in_reg(left, REG_C, ia, i, G) && I[ia.registers[REG_C][1]].byte == 0) ||
-        operand_in_reg(left, REG_D, ia, i, G) && (getSize(operandType(left)) < 2 || operand_in_reg(left, REG_E, ia, i, G) && I[ia.registers[REG_E][1]].byte == 0) ||
-        operand_in_reg(left, REG_H, ia, i, G) && (getSize(operandType(left)) < 2 || operand_in_reg(left, REG_L, ia, i, G) && I[ia.registers[REG_L][1]].byte == 0) ||
-        operand_in_reg(left, REG_IYL, ia, i, G) && I[ia.registers[REG_IYL][1]].byte == 0 && (getSize(operandType(left)) < 2 || operand_in_reg(left, REG_IYH, ia, i, G))))
-        return(true);
       if(!result_in_A && !input_in_A)
         return(false);
     }
@@ -700,8 +678,6 @@
         !((ic->op == RIGHT_OP || ic->op == LEFT_OP) &&
           (IS_OP_LITERAL(right) || operand_in_reg(right, REG_A, ia, i, G) || getSize(operandType(IC_RESULT(ic))) == 1 && ia.registers[REG_B][1] < 0)) &&
         !((ic->op == '=' || ic->op == CAST) && !(IY_RESERVED && POINTER_SET(ic))) &&
-        !IS_BITWISE_OP (ic) &&
-        !(ic->op == '~') &&
         !(ic->op == '*' && (IS_ITEMP(IC_LEFT(ic)) || IS_OP_LITERAL(IC_LEFT(ic))) && (IS_ITEMP(IC_RIGHT(ic)) || IS_OP_LITERAL(IC_RIGHT(ic)))) &&
         !((ic->op == '-' || ic->op == '+' || ic->op == EQ_OP) && IS_OP_LITERAL(IC_RIGHT(ic))))
         {
@@ -724,16 +700,13 @@
       ic->op != '+' &&
       ic->op != '-' &&
       (ic->op != '*' || !IS_OP_LITERAL(IC_LEFT(ic)) && !IS_OP_LITERAL(right)) &&
-      !IS_BITWISE_OP(ic) &&
       ic->op != GET_VALUE_AT_ADDRESS &&
       ic->op != '=' &&
       ic->op != EQ_OP &&
       ic->op != '<' &&
       ic->op != '>' &&
-      ic->op != CAST &&
       ic->op != CALL &&
       ic->op != PCALL &&
-      ic->op != GETHBIT &&
       !((ic->op == LEFT_OP || ic->op == RIGHT_OP) && IS_OP_LITERAL(right)))
     {
       //std::cout << "First use: Dropping at " << i << ", " << ic->key << "(" << int(ic->op) << "\n";
@@ -750,11 +723,7 @@
 {
   const iCode *ic = G[i].ic;
 
-  // HL always unused on gbz80.
-  if(TARGET_IS_GBZ80)
-    return(true);
-
-  bool exstk = (should_omit_frame_ptr || (currFunc && currFunc->stack > 127) || IS_GB);
+  bool exstk = (should_omit_frame_ptr || (currFunc && currFunc->stack > 127) || IS_SM83);
 
   const i_assignment_t &ia = a.i_assignment;
 
@@ -803,25 +772,56 @@
   bool result_only_HL = (result_in_L || unused_L || dying_L) && (result_in_H || unused_H || dying_H);
 
 #if 0
-  if (ic->key == 4)
+  if (ic->key == 6)
     {
-      std::cout << "Result in L: " << result_in_L << ", result in H: " << result_in_H << "\n";
-      std::cout << "Unsued L: " << unused_L << ", unused H: " << unused_H << "\n";
-      std::cout << "Dying L: " << dying_L << ", dying H: " << dying_H << "\n";
-      std::cout << "Result only HL: " << result_only_HL << "\n";
+      std::cout << "  Result in L: " << result_in_L << ", result in H: " << result_in_H << "\n";
+      std::cout << "  Unsued L: " << unused_L << ", unused H: " << unused_H << "\n";
+      std::cout << "  Dying L: " << dying_L << ", dying H: " << dying_H << "\n";
+      std::cout << "  Result only HL: " << result_only_HL << "\n";
     }
 #endif
 
-  if(ic->op == RETURN || ic->op == SEND || ic->op == RECEIVE)
+  // For some iCodes, code generation can handle anything.
+  if(ic->op == '~' || ic->op == CALL || ic->op == RETURN || ic->op == LABEL || ic->op == GOTO ||
+    ic->op == '^' || ic->op == '|' || ic->op == BITWISEAND ||
+    ic->op == GETBYTE || ic->op == GETWORD || ic->op == SWAP && (getSize(operandType(IC_RESULT (ic))) == 1 || operand_in_reg(result, ia, i, G)) ||
+    !((IS_SM83 || IY_RESERVED) && (operand_on_stack(result, a, i, G) || operand_on_stack(right, a, i, G))) && (ic->op == '=' && !POINTER_SET (ic) || ic->op == CAST) ||
+    ic->op == RECEIVE || ic->op == SEND)
+    return(true);
+
+  if((ic->op == EQ_OP || ic->op == NE_OP) && IS_VALOP(right))
     return(true);
 
-  if((IS_GB || IY_RESERVED) && (IS_TRUE_SYMOP(left) || IS_TRUE_SYMOP(right)))
+  // Due to lack of ex hl, (sp), the generic push code generation fallback doesn't work for gbz80, so we need to be able to use hl if we can't just push a pair or use a.
+  if(IS_SM83 && ic->op == IPUSH && !operand_is_pair(left, a, i, G) && ia.registers[REG_A][1] >= 0 &&
+    !(getSize(operandType(left)) == 1 && (operand_in_reg(left, REG_A, ia, i, G) || operand_in_reg(left, REG_B, ia, i, G) || operand_in_reg(left, REG_D, ia, i, G) || operand_in_reg(left, REG_H, ia, i, G))))
+    return(false);
+
+  if(IS_SM83 && ic->op == GET_VALUE_AT_ADDRESS && !result_only_HL && (getSize(operandType(result)) >= 2 || !operand_is_pair(left, a, i, G)))
+    return(false);
+
+  // For some operations, the gbz80 stack access using hl will trash the value there.
+  if(IS_SM83 &&
+    (ic->op == IPUSH && operand_on_stack(left, a, i, G) || ic->op == IFX && operand_on_stack(IC_COND(ic), a, i, G)))
+    return(false);
+  if(IS_SM83 &&
+    (operand_on_stack(result, a, i, G) || operand_on_stack(left, a, i, G) || operand_on_stack(right, a, i, G)) && 
+    (ic->op == RIGHT_OP || ic->op == LEFT_OP || ic->op == '=' || ic->op == CAST || ic->op == '-' || ic->op == UNARYMINUS) &&
+    !(result_only_HL && getSize(operandType(result)) == 1)) // Size of result needs to be checked after checking ic->op to ensure that there is a result operand.
+    return(false);
+
+  if(IS_SM83 && ic->op == GET_VALUE_AT_ADDRESS && !(result_only_HL || getSize(operandType(result)) == 1))
+    return(false);
+  if(IS_SM83 && POINTER_GET(ic) && !(result_only_HL || getSize(operandType(right)) == 1))
+    return(false);
+
+  if((IS_SM83 || IY_RESERVED) && (IS_TRUE_SYMOP(left) || IS_TRUE_SYMOP(right)))
     return(false);
 
-  if((IS_GB || IY_RESERVED) && IS_TRUE_SYMOP(result) && getSize(operandType(IC_RESULT(ic))) > 2)
+  if((IS_SM83 || IY_RESERVED) && IS_TRUE_SYMOP(result) && getSize(operandType(IC_RESULT(ic))) > 2)
     return(false);
 
-  // __z88dk_fastcall passes paramter in hl
+  // __z88dk_fastcall passes parameter in hl
   if(ic->op == PCALL && ic->prev && ic->prev->op == SEND && input_in_HL && IFFUNC_ISZ88DK_FASTCALL(operandType(IC_LEFT(ic))->next))
     return(false);
 
@@ -829,9 +829,9 @@
   if(result_only_HL && ic->op == PCALL)
     return(true);
 
-  if(ic->op == '-' && getSize(operandType(result)) == 2 && !IS_GB && IS_TRUE_SYMOP (left) && IS_TRUE_SYMOP (right) && result_only_HL)
+  if(ic->op == '-' && getSize(operandType(result)) == 2 && IS_TRUE_SYMOP (left) && IS_TRUE_SYMOP (right) && result_only_HL)
     return(true);
-
+    
   if(exstk &&
      (operand_on_stack(result, a, i, G) + operand_on_stack(left, a, i, G) + operand_on_stack(right, a, i, G) >= 2) &&
      (result && IS_SYMOP(result) && getSize(operandType(result)) >= 2 || !result_only_HL))
@@ -849,12 +849,12 @@
      (operand_in_reg(result, REG_L, ia, i, G) && I[ia.registers[REG_L][1]].byte == 0 && operand_in_reg(result, REG_H, ia, i, G)))
     return(true); // Uses inc hl.
 
-  if(ic->op == '+' && getSize(operandType(result)) == 2 && !IS_TRUE_SYMOP (result) &&
+  if(!IS_SM83 && ic->op == '+' && getSize(operandType(result)) == 2 && !IS_TRUE_SYMOP (result) &&
     (result_only_HL || operand_in_reg(result, REG_IYL, ia, i, G) && operand_in_reg(result, REG_IYH, ia, i, G)) &&
     (ia.registers[REG_C][1] < 0 && ia.registers[REG_B][1] < 0 || ia.registers[REG_E][1] < 0 && ia.registers[REG_D][1] < 0)) // Can use ld rr, (nn) instead of (hl).
     return(true);
 
-  if(ic->op == '+' && getSize(operandType(result)) == 2 && IS_TRUE_SYMOP (left) && !IS_GB &&
+  if(!IS_SM83 && ic->op == '+' && getSize(operandType(result)) == 2 && IS_TRUE_SYMOP (left) &&
     (IS_OP_LITERAL (right) && ulFromVal (OP_VALUE (IC_RIGHT(ic))) <= 3 || IS_OP_LITERAL (left) && ulFromVal (OP_VALUE (IC_LEFT(ic))) <= 3) &&
     (operand_in_reg(result, REG_C, ia, i, G) && I[ia.registers[REG_C][1]].byte == 0 && operand_in_reg(result, REG_B, ia, i, G) || operand_in_reg(result, REG_E, ia, i, G) && I[ia.registers[REG_E][1]].byte == 0 && operand_in_reg(result, REG_D, ia, i, G))) // Can use ld rr, (nn) followed by inc rr
     return(true);
@@ -863,7 +863,7 @@
     (IS_TRUE_SYMOP (result) && !operand_on_stack(result, a, i, G) || (operand_on_stack(left, a, i, G) ? exstk : IS_TRUE_SYMOP (left)) || (operand_on_stack(right, a, i, G) ? exstk : IS_TRUE_SYMOP (right)))) // Might use (hl).
     return(false);
 
-  if(ic->op == '+' && input_in_HL && (operand_on_stack(result, a, i, G) ? exstk : IS_TRUE_SYMOP (result))) // Might use (hl) for result.
+  if(IS_SM83 && ic->op == '+' && getSize(operandType(result)) > 1 && input_in_HL && operand_on_stack(result, a, i, G))
     return(false);
 
   // HL overwritten by result.
@@ -879,14 +879,13 @@
   if(!exstk && !isOperandInDirSpace(IC_LEFT(ic)) && !isOperandInDirSpace(IC_RIGHT(ic)) && !isOperandInDirSpace(IC_RESULT(ic)) &&
     (ic->op == '-' ||
     ic->op == UNARYMINUS ||
-    ic->op == '~' ||
     ic->op == '<' ||
     ic->op == '>'))
     return(true);
 
   if(ic->op == LEFT_OP && getSize(operandType(result)) <= 2 && IS_OP_LITERAL (right) && result_only_HL)
     return(true);
-  if((ic->op == LEFT_OP || ic->op == RIGHT_OP) && (getSize(operandType(result)) <= 1 || !IS_TRUE_SYMOP(result) || !IY_RESERVED) &&
+  if((ic->op == LEFT_OP || ic->op == RIGHT_OP) && (getSize(operandType(result)) <= 1 || !IS_TRUE_SYMOP(result) || !(IS_SM83 || IY_RESERVED)) &&
      (!exstk ||
       ((!operand_on_stack(left,  a, i, G) || !input_in_HL && result_only_HL) &&
        (!operand_on_stack(right, a, i, G) || !input_in_HL && result_only_HL) &&
@@ -907,28 +906,11 @@
     return(true);
   if(SKIP_IC2(ic))
     return(true);
-  if(ic->op == IPUSH && input_in_H && (getSize(operandType(IC_LEFT(ic))) <= 2 || ia.registers[REG_L][1] > 0 && I[ia.registers[REG_L][1]].byte == 2 && ia.registers[REG_H][1] > 0 && I[ia.registers[REG_H][1]].byte == 3))
-    return(true);
-  if(ic->op == IPUSH && getSize(operandType(left)) == 1 && IS_OP_LITERAL(left) && ia.registers[REG_A][1] < 0) // Can be pushed in A.
-    return(true);
-  if(ic->op == IPUSH && ic->next && ic->next->op == CALL)
-    return(true);
-  if(ic->op == IPUSH && getSize(operandType(left)) == 2 &&
-    (ia.registers[REG_C][1] < 0 && ia.registers[REG_B][1] < 0 || ia.registers[REG_E][1] < 0 && ia.registers[REG_D][1] < 0)) // Can use pair other than HL.
-    return(true);
-  if(ic->op == IPUSH && getSize(operandType(left)) <= 2 &&
-    (operand_in_reg(left, REG_C, ia, i, G) && I[ia.registers[REG_C][1]].byte == 0 && (getSize(operandType(left)) < 2 || operand_in_reg(left, REG_B, ia, i, G)) ||
-    operand_in_reg(left, REG_E, ia, i, G) && I[ia.registers[REG_E][1]].byte == 0 && (getSize(operandType(left)) < 2 || operand_in_reg(left, REG_D, ia, i, G)) ||
-    operand_in_reg(left, REG_IYL, ia, i, G) && I[ia.registers[REG_IYL][1]].byte == 0 && (getSize(operandType(left)) < 2 || operand_in_reg(left, REG_IYH, ia, i, G))))
-    return(true);
-  if (ic->op == IPUSH && getSize(operandType(left)) == 4 &&
-    operand_in_reg(left, REG_L, ia, i, G) && I[ia.registers[REG_L][1]].byte == 0 && operand_in_reg(left, REG_H, ia, i, G) && I[ia.registers[REG_H][1]].byte == 1 &&
-    (operand_in_reg(left, REG_C, ia, i, G) && I[ia.registers[REG_C][1]].byte == 2 && operand_in_reg(left, REG_B, ia, i, G) && I[ia.registers[REG_B][1]].byte == 3 ||
-    operand_in_reg(left, REG_E, ia, i, G) && I[ia.registers[REG_E][1]].byte == 2 && operand_in_reg(left, REG_D, ia, i, G) && I[ia.registers[REG_D][1]].byte == 3))
+  if(ic->op == IPUSH) // Can handle anything.
     return(true);
   if(POINTER_GET(ic) && input_in_L && input_in_H && (getSize(operandType(IC_RESULT(ic))) == 1 || !result_in_HL))
     return(true);
-  if(!IS_GB && ic->op == ADDRESS_OF &&
+  if(!IS_SM83 && ic->op == ADDRESS_OF &&
     (operand_in_reg(result, REG_IYL, ia, i, G) && ia.registers[REG_IYL][1] > 0 && I[ia.registers[REG_IYL][1]].byte == 0 && operand_in_reg(result, REG_IYH, ia, i, G) ||
     !OP_SYMBOL_CONST (left)->onStack && operand_in_reg(result, REG_C, ia, i, G) && ia.registers[REG_C][1] > 0 && I[ia.registers[REG_C][1]].byte == 0 && operand_in_reg(result, REG_B, ia, i, G) ||
     !OP_SYMBOL_CONST (left)->onStack && operand_in_reg(result, REG_E, ia, i, G) && ia.registers[REG_E][1] > 0 && I[ia.registers[REG_E][1]].byte == 0 && operand_in_reg(result, REG_D, ia, i, G)))
@@ -937,7 +919,7 @@
   if(ic->op == LEFT_OP && isOperandLiteral(IC_RIGHT(ic)))
     return(true);
 
-  if(exstk && !result_only_HL && (operand_on_stack(left, a, i, G) || operand_on_stack(right, a, i, G) || operand_on_stack(result, a, i, G)) && ic->op == '+')
+  if(exstk && !result_only_HL && (operand_on_stack(left, a, i, G) || operand_on_stack(right, a, i, G)) && ic->op == '+')
     return(false);
 
   if((!POINTER_SET(ic) && !POINTER_GET(ic) && (
@@ -951,35 +933,31 @@
          ic->op == '<' ||
          ic->op == EQ_OP ||*/
          (ic->op == '+' && getSize(operandType(IC_RESULT(ic))) == 1) ||
-         (ic->op == '+' && getSize(operandType(IC_RESULT(ic))) <= 2 && (result_only_HL || !IS_GB)) )))) // 16 bit addition on gbz80 might need to use add hl, rr.
+         (ic->op == '+' && (result_only_HL || !IS_SM83)) )))) // addition on gbz80 might need to use add hl, rr.
     return(true);
 
   if((ic->op == '<' || ic->op == '>') && (IS_ITEMP(left) || IS_OP_LITERAL(left) || IS_ITEMP(right) || IS_OP_LITERAL(right))) // Todo: Fix for large stack.
     return(true);
-    
-  if(ic->op == EQ_OP && IS_VALOP(right))
-    return(true);
 
   if(ic->op == CALL)
     return(true);
 
   if(POINTER_GET(ic) && getSize(operandType(IC_RESULT(ic))) == 1 && !IS_BITVAR(getSpec(operandType(result))) &&
-    (operand_in_reg(right, REG_C, ia, i, G) && I[ia.registers[REG_C][1]].byte == 0 && operand_in_reg(right, REG_B, ia, i, G) || // Uses ld a, (bc)
-    operand_in_reg(right, REG_E, ia, i, G) && I[ia.registers[REG_E][1]].byte == 0 && operand_in_reg(right, REG_D, ia, i, G) || // Uses ld a, (de)
-    operand_in_reg(right, REG_IYL, ia, i, G) && I[ia.registers[REG_IYL][1]].byte == 0 && operand_in_reg(right, REG_IYH, ia, i, G))) // Uses ld r, 0 (iy)
+    operand_is_pair(left, a, i, G) && // Use ld a, (dd) or ld r, 0 (iy).
+    IS_OP_LITERAL (right) && ulFromVal (OP_VALUE_CONST(right)) == 0) 
     return(true);
 
-  if((ic->op == '=') && POINTER_SET(ic) && operand_in_reg(result, REG_IYL, ia, i, G) && I[ia.registers[REG_IYL][1]].byte == 0 && operand_in_reg(result, REG_IYH, ia, i, G)) // Uses ld 0 (iy), l etc
+  if(ic->op == '=' && POINTER_SET(ic) && operand_in_reg(result, REG_IYL, ia, i, G) && I[ia.registers[REG_IYL][1]].byte == 0 && operand_in_reg(result, REG_IYH, ia, i, G)) // Uses ld 0 (iy), l etc
     return(true);
 
-  if((ic->op == '=' || ic->op == CAST) && POINTER_SET(ic) && !result_only_HL) // loads result pointer into (hl) first.
+  if(ic->op == '=' && POINTER_SET(ic) && !result_only_HL) // loads result pointer into (hl) first.
     return(false);
 
   if((ic->op == '=' || ic->op == CAST) && !POINTER_GET(ic) && !input_in_HL)
     return(true);
 
 #if 0
-  if(ic->key == 4)
+  if(ic->key == 6)
     {
       std::cout << "HLinst_ok: L = (" << ia.registers[REG_L][0] << ", " << ia.registers[REG_L][1] << "), H = (" << ia.registers[REG_H][0] << ", " << ia.registers[REG_H][1] << ")inst " << i << ", " << ic->key << "\n";
       std::cout << "Result in L: " << result_in_L << ", result in H: " << result_in_H << "\n";
@@ -987,7 +965,13 @@
     }
 #endif
 
-  return(false);
+  // Replaces former default drop here.
+  if (ic->op == GET_VALUE_AT_ADDRESS || POINTER_SET(ic) || ic->op == ADDRESS_OF || ic->op == '*' || ic->op == JUMPTABLE) // Some operations always use hl. TODO: See if they can be changed to save / restore a hl in use or use hl only when free.
+    return(false);
+  if(exstk && (operand_on_stack(result, a, i, G) || IS_TRUE_SYMOP (result) || operand_on_stack(left, a, i, G) || IS_TRUE_SYMOP (left) || operand_on_stack(right, a, i, G) || IS_TRUE_SYMOP (right))) // hl used as pointer to operand.
+    return(false);
+
+  return(true);
 }
 
 template 
@@ -995,8 +979,8 @@
 {
   const iCode *ic = G[i].ic;
 
-  // IY always unused on gbz80.
-  if(TARGET_IS_GBZ80)
+  // IY always unused on sm83.
+  if(IS_SM83)
     return(true);
 
   const i_assignment_t &ia = a.i_assignment;
@@ -1051,7 +1035,14 @@
   if(exstk && (operand_on_stack(result, a, i, G) || operand_on_stack(left, a, i, G) || operand_on_stack(right, a, i, G))) // Todo: Make this more accurate to get better code when using --fomit-frame-pointer
     return(false);
 
-  if(ic->op == CALL)
+  // Some instructions can handle anything.
+  if(ic->op == IPUSH || ic->op == CALL ||
+    ic->op == '+' ||
+    ic->op == '|' ||
+    ic->op == GETBYTE || ic->op == GETWORD || ic->op == SWAP && (getSize(operandType(IC_RESULT (ic))) == 1 || operand_in_reg(result, ia, i, G)) ||
+    ic->op == '=' && !POINTER_SET(ic) ||
+    ic->op == CAST ||
+    ic->op == SEND)
     return(true);
 
   if(!result_in_IY && !input_in_IY &&
@@ -1060,12 +1051,6 @@
     !(IC_LEFT(ic) && IS_TRUE_SYMOP(IC_LEFT(ic))))
     return(true);
 
-  // variables partially in IY can be pushed.
-  if(ic->op == IPUSH &&
-    operand_in_reg(left, REG_IYL, ia, i, G) && operand_in_reg(left, REG_IYH, ia, i, G) &&
-    (I[ia.registers[REG_IYL][1]].byte == 0 && I[ia.registers[REG_IYH][1]].byte == 1 || I[ia.registers[REG_IYL][1]].byte == 2 && I[ia.registers[REG_IYH][1]].byte == 3))
-    return(true);
-
   // Code generator mostly cannot handle variables that are only partially in IY.
   if(unused_IYL ^ unused_IYH)
     return(false);
@@ -1096,17 +1081,12 @@
 #endif
 
   if(result_in_IY &&
-    (ic->op == '=' && !(POINTER_SET(ic) && isOperandInDirSpace(IC_RIGHT(ic))) ||
-    ic->op == CAST && getSize(operandType(IC_RESULT(ic))) <= getSize(operandType(IC_RIGHT(ic))) || 
-    ic->op == '+')) // todo: More instructions that can write iy.
+    (ic->op == '-' || ic->op == UNARYMINUS)) // todo: More instructions that can write iy.
     return(true);
 
   // Todo: Multiplication.
 
-  if(ic->op == LEFT_OP && result_in_IY && input_in_IY && IS_VALOP (IC_RIGHT (ic)) && operandLitValue (IC_RIGHT (ic)) < 8)
-    return(true);
-
-  if(ic->op == '-' && result_in_IY && input_in_IY && IS_VALOP (IC_RIGHT (ic)) && operandLitValue (IC_RIGHT (ic)) < 4)
+  if(ic->op == LEFT_OP)
     return(true);
 
 #if 0
@@ -1124,16 +1104,10 @@
     operand_is_pair(IC_RESULT(ic), a, i, G)) // DirSpace access won't use iy here.
     return(true);
 
-  if(ic->op == IPUSH) // todo: More instructions that can use IY.
-    return(true);
-
   if(ic->op == GET_VALUE_AT_ADDRESS && isOperandInDirSpace(IC_RESULT(ic)))
     return(false);
 
-  if(input_in_IY && !result_in_IY &&
-    (ic->op == '=' && !POINTER_SET(ic) ||
-     ic->op == CAST && getSize(operandType(IC_RESULT(ic))) <= getSize(operandType(IC_RIGHT(ic))) ||
-     ic->op == GET_VALUE_AT_ADDRESS))
+  if(input_in_IY && !result_in_IY && ic->op == GET_VALUE_AT_ADDRESS)
     return(true);
 
 #if 0
@@ -1150,7 +1124,7 @@
 template 
 bool DEinst_ok(const assignment &a, unsigned short int i, const G_t &G, const I_t &I)
 {
-  if(!IS_GB) // Only gbz80 might need de for code generation.
+  if(!IS_SM83) // Only sm83 might need de for code generation.
     return(true);
 
   const i_assignment_t &ia = a.i_assignment;
@@ -1166,8 +1140,6 @@
   const operand *right = IC_RIGHT(ic);
   const operand *result = IC_RESULT(ic);
 
-  //const std::set &dying = G[i].dying;
-
   if(ic->op == PCALL)
     return(false);
 
@@ -1177,18 +1149,22 @@
   if (ic->op == '=' && POINTER_SET(ic) && !operand_is_pair(result, a, i, G))
     return(false);
 
-  if((ic->op == '=' || ic->op == CAST) && getSize(operandType(result)) >= 2 &&
+  if((ic->op == '=' || ic->op == CAST) && getSize(operandType(result)) > 2 &&
      (operand_on_stack(right, a, i, G) || operand_in_reg(right, REG_L, ia, i, G) || operand_in_reg(right, REG_H, ia, i, G)) &&
      (operand_on_stack(result, a, i, G) || operand_in_reg(result, REG_L, ia, i, G) || operand_in_reg(result, REG_H, ia, i, G)))
     return(false);
 
-  if(ic->op == '+' && getSize(operandType(result)) >= 2)
+  if((ic->op == '+' || ic->op == '-' || ic->op == UNARYMINUS) && getSize(operandType(result)) >= 4)
+    return(false);
+
+  if((ic->op == '-' || ic->op == UNARYMINUS) && getSize(operandType(result)) >= 2 && // Stack access requires arithmetic that trashes carry.
+    (operand_on_stack(result, a, i, G) || operand_on_stack(left, a, i, G) || operand_on_stack(right, a, i, G)))
     return(false);
 
-  if(ic->op == UNARYMINUS || ic->op == '-' || ic->op == '*')
+  if(ic->op == '*')
     return(false);
 
-  if(ic->op == '>' || ic->op == '<')
+  if((ic->op == '>' || ic->op == '<') && !SPEC_USIGN(getSpec(operandType(left))) && !SPEC_USIGN(getSpec(operandType(right))))
     return(false);
 
   return(true);
@@ -1226,7 +1202,7 @@
     {
       var_t v = oi->second;
       if(a.global[v] >= 0)
-        { 
+        {
           sym->regs[I[v].byte] = regsZ80 + a.global[v];
           sym->accuse = 0;
           sym->isspilt = false;
@@ -1280,7 +1256,7 @@
   if(!Ainst_ok(a, i, G, I))
     return(std::numeric_limits::infinity());
 
-  if(OPTRALLOC_HL && !HLinst_ok(a, i, G, I))
+  if(!HLinst_ok(a, i, G, I))
     return(std::numeric_limits::infinity());
 
   if(!DEinst_ok(a, i, G, I))
@@ -1298,6 +1274,7 @@
     case GOTO:
     case INLINEASM:
       return(0.0f);
+      
     // Exact cost:
     case '!':
     case '~':
@@ -1318,7 +1295,9 @@
     case EQ_OP:
     case AND_OP:
     case OR_OP:
-    case GETHBIT:
+    case GETABIT:
+    case GETBYTE:
+    case GETWORD:
     case LEFT_OP:
     case RIGHT_OP:
     case GET_VALUE_AT_ADDRESS:
@@ -1337,6 +1316,7 @@
       c = dryZ80iCode(ic);
       ic->generated = false;
       return(c);
+
     // Inexact cost:
     default:
       return(default_instruction_cost(a, i, G, I));
@@ -1397,8 +1377,7 @@
   const i_assignment_t &ia = a.i_assignment;
 
   // Can only check for HLinst_ok() in some cases.
-  if(OPTRALLOC_HL &&
-      (ia.registers[REG_L][1] >= 0 && ia.registers[REG_H][1] >= 0) &&
+  if((ia.registers[REG_L][1] >= 0 && ia.registers[REG_H][1] >= 0) &&
       (ia.registers[REG_L][0] >= 0 && ia.registers[REG_H][0] >= 0) &&
       !HLinst_ok(a, i, G, I))
     return(true);
@@ -1425,7 +1404,7 @@
         {
           varset_t::const_iterator vi, vi_end;
           for(vi = ai->local.begin(), vi_end = ai->local.end(); vi != vi_end; ++vi)
-            if(ai->global[*vi] == REG_A || OPTRALLOC_HL && (ai->global[*vi] == REG_H || ai->global[*vi] == REG_L) || OPTRALLOC_IY && (ai->global[*vi] == REG_IYH || ai->global[*vi] == REG_IYL))
+            if(ai->global[*vi] == REG_A || (ai->global[*vi] == REG_H || ai->global[*vi] == REG_L) || OPTRALLOC_IY && (ai->global[*vi] == REG_IYH || ai->global[*vi] == REG_IYL))
               goto too_risky;
           ai_best = ai;
         }
@@ -1449,8 +1428,7 @@
 
   c += weird_byte_order(a, I);
 
-  if(OPTRALLOC_HL &&
-     ia.registers[REG_L][1] >= 0 &&
+  if(ia.registers[REG_L][1] >= 0 &&
      ia.registers[REG_H][1] >= 0 &&
      ((ia.registers[REG_L][0] >= 0) == (ia.registers[REG_H][0] >= 0)) &&
      !HLinst_ok(a, i, G, I))
@@ -1459,7 +1437,7 @@
   if(ia.registers[REG_A][1] < 0)
     c += 0.03f;
 
-  if(OPTRALLOC_HL && ia.registers[REG_L][1] < 0)
+  if(ia.registers[REG_L][1] < 0)
     c += 0.02f;
 
   // Using IY is rarely a good choice, so discard the IY-users first when in doubt.
@@ -1468,7 +1446,7 @@
       varset_t::const_iterator vi, vi_end;
       for(vi = a.local.begin(), vi_end = a.local.end(); vi != vi_end; ++vi)
         if(a.global[*vi] == REG_IYL || a.global[*vi] == REG_IYH)
-          c += 8.0f;
+          c += 2.0f;
     }
 
   // An artifical ordering of assignments.
@@ -1615,16 +1593,17 @@
 }
 
 // Omit the frame pointer for functions with low register pressure and few parameter accesses.
+// This is just a heuristic, including the magic value of 21. Many other, more complex heuristics have been tried, but didn't perform better for the regression tests.
 template 
 static bool omit_frame_ptr(const G_t &G)
 {
-  if(IS_GB || IY_RESERVED || z80_opts.noOmitFramePtr)
+  if(IS_SM83 || IY_RESERVED || z80_opts.noOmitFramePtr)
     return(false);
 
   if(options.omitFramePtr)
     return(true);
-    
-  signed char omitcost = -16;
+
+  signed char omitcost = -10; // Overhead for setting up frame pointer is 10 bytes of code
   for(unsigned int i = 0; i < boost::num_vertices(G); i++)
     {
       if((int)G[i].alive.size() > port->num_regs - 4)
@@ -1633,6 +1612,7 @@
       const iCode *const ic = G[i].ic;
       const operand *o;
       o = IC_RESULT(ic);
+      // Accesses without frame pointer, when using iy, tend to cost 6 bytes of overhead per variable (there is no difference in per-byte-specific costs).
       if(o && IS_SYMOP(o) && OP_SYMBOL_CONST(o)->_isparm && !IS_REGPARM (OP_SYMBOL_CONST(o)->etype))
         omitcost += 6;
       o = IC_LEFT(ic);
@@ -1642,7 +1622,7 @@
       if(o && IS_SYMOP(o) && OP_SYMBOL_CONST(o)->_isparm && !IS_REGPARM (OP_SYMBOL_CONST(o)->etype))
         omitcost += 6;
 
-      if(omitcost > 14) // Chosen greater than zero, since the peephole optimizer often can optimize the use of iy into use of hl, reducing the cost.
+      if(omitcost > 20) // Chosen greater than zero, since the peephole optimizer often can optimize the use of iy into use of hl, reducing the cost.
         return(false);
     }
 
@@ -1652,7 +1632,7 @@
 // Adjust stack location when deciding to omit frame pointer.
 void move_parms(void)
 {
-  if(!currFunc || IS_GB || options.omitFramePtr || !should_omit_frame_ptr)
+  if(!currFunc || IS_SM83 || options.omitFramePtr || !should_omit_frame_ptr)
     return;
 
   for(value *val = FUNC_ARGS (currFunc->type); val; val = val->next)
diff -Nru sdcc-4.0.0+dfsg/src/z80/ralloc.c sdcc-4.2.0+dfsg/src/z80/ralloc.c
--- sdcc-4.0.0+dfsg/src/z80/ralloc.c	2019-12-09 14:41:31.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/z80/ralloc.c	2022-02-03 09:32:48.000000000 +0000
@@ -64,32 +64,14 @@
 {
   D_ALLOC = 0,
   D_ALLOC2 = 0,
-  D_ACCUSE2 = 0,
-  D_ACCUSE2_VERBOSE = 0,
-  D_HLUSE = 0,
-  D_HLUSE2 = 0,
-  D_HLUSE2_VERBOSE = 0,
-  D_FILL_GAPS = 0,
-  D_PACK_IY = 0,
-  D_PACK_HLUSE3 = 0
 };
 
-// #define D_ALLOC 1
-
 #if 1
 #define D(_a, _s)       if (_a)  { printf _s; fflush(stdout); }
 #else
 #define D(_a, _s)
 #endif
 
-#define DISABLE_PACKREGSFORSUPPORT      1
-#define DISABLE_PACKREGSFORACCUSE       1
-
-// Build the old register allocator. It can be used by command-line options
-#define OLDRALLOC 1
-
-extern void genZ80Code (iCode *);
-
 /** Local static variables */
 static struct
 {
@@ -106,7 +88,7 @@
   int nRegs;
 } _G;
 
-static reg_info _gbz80_regs[] = {
+reg_info sm83_regs[] = {
   {REG_GPR, A_IDX, "a", 1},
   {REG_GPR, C_IDX, "c", 1},
   {REG_GPR, B_IDX, "b", 1},
@@ -117,7 +99,7 @@
   {REG_CND, CND_IDX, "c", 1}
 };
 
-static reg_info _z80_regs[] = {
+reg_info z80_regs[] = {
   {REG_GPR, A_IDX, "a", 1},
   {REG_GPR, C_IDX, "c", 1},
   {REG_GPR, B_IDX, "b", 1},
@@ -133,43 +115,12 @@
 reg_info *regsZ80;
 
 /** Number of usable registers (all but C) */
-#define Z80_MAX_REGS ((sizeof(_z80_regs)/sizeof(_z80_regs[0]))-1)
-#define GBZ80_MAX_REGS ((sizeof(_gbz80_regs)/sizeof(_gbz80_regs[0]))-1)
+#define Z80_MAX_REGS ((sizeof (z80_regs) / sizeof (z80_regs[0]))-1)
+#define SM83_MAX_REGS ((sizeof (sm83_regs) / sizeof (sm83_regs[0]))-1)
 
 void z80SpillThis (symbol *);
 static void freeAllRegs ();
 
-#ifdef OLDRALLOC
-/** Allocates register of given type.
-    'type' is not used on the z80 version.  It was used to select
-    between pointer and general purpose registers on the mcs51 version.
-
-    @return             Pointer to the newly allocated register.
- */
-static reg_info *
-allocReg (short type)
-{
-  int i;
-
-  for (i = C_IDX; i < _G.nRegs; i++)
-    {
-      /* For now we allocate from any free */
-      if (regsZ80[i].isFree)
-        {
-          regsZ80[i].isFree = 0;
-          if (currFunc)
-            {
-              currFunc->regsUsed = bitVectSetBit (currFunc->regsUsed, i);
-            }
-          D (D_ALLOC, ("allocReg: alloced %s\n", regsZ80[i].name));
-          return ®sZ80[i];
-        }
-    }
-  D (D_ALLOC, ("allocReg: No free.\n"));
-  return NULL;
-}
-#endif
-
 /** Returns pointer to register wit index number
  */
 reg_info *
@@ -199,199 +150,6 @@
   D (D_ALLOC, ("freeReg: freed %p\n", reg));
 }
 
-#ifdef OLDRALLOC
-/** Returns number of free registers.
- */
-static int
-nFreeRegs (int type)
-{
-  int i;
-  int nfr = 0;
-
-  for (i = C_IDX; i < _G.nRegs; i++)
-    {
-      /* For now only one reg type */
-      if (regsZ80[i].isFree)
-        {
-          nfr++;
-        }
-    }
-  return nfr;
-}
-#endif
-
-#ifdef OLDRALLOC
-/** Free registers with type.
- */
-static int
-nfreeRegsType (int type)
-{
-  int nfr;
-  if (type == REG_PTR)
-    {
-      if ((nfr = nFreeRegs (type)) == 0)
-        {
-          return nFreeRegs (REG_GPR);
-        }
-    }
-
-  return nFreeRegs (type);
-}
-#endif
-
-#ifdef OLDRALLOC
-/*-----------------------------------------------------------------*/
-/* useReg - marks a register  as used                              */
-/*-----------------------------------------------------------------*/
-static void
-useReg (reg_info * reg)
-{
-  reg->isFree = 0;
-}
-#endif
-
-#ifdef OLDRALLOC
-/*-----------------------------------------------------------------*/
-/* computeSpillable - given a point find the spillable live ranges */
-/*-----------------------------------------------------------------*/
-static bitVect *
-computeSpillable (iCode * ic)
-{
-  bitVect *spillable;
-
-  /* spillable live ranges are those that are live at this
-     point . the following categories need to be subtracted
-     from this set.
-     a) - those that are already spilt
-     b) - if being used by this one
-     c) - defined by this one */
-
-  spillable = bitVectCopy (ic->rlive);
-  spillable = bitVectCplAnd (spillable, _G.spiltSet);   /* those already spilt */
-  spillable = bitVectCplAnd (spillable, ic->uses);      /* used in this one */
-  bitVectUnSetBit (spillable, ic->defKey);
-  spillable = bitVectIntersect (spillable, _G.regAssigned);
-
-  return spillable;
-}
-#endif
-
-#ifdef OLDRALLOC
-/*-----------------------------------------------------------------*/
-/* noSpilLoc - return true if a variable has no spil location      */
-/*-----------------------------------------------------------------*/
-static int
-noSpilLoc (symbol * sym, eBBlock * ebp, iCode * ic)
-{
-  return (sym->usl.spillLoc ? 0 : 1);
-}
-#endif
-
-#ifdef OLDRALLOC
-/*-----------------------------------------------------------------*/
-/* hasSpilLoc - will return 1 if the symbol has spil location      */
-/*-----------------------------------------------------------------*/
-static int
-hasSpilLoc (symbol * sym, eBBlock * ebp, iCode * ic)
-{
-  return (sym->usl.spillLoc ? 1 : 0);
-}
-#endif
-
-#ifdef OLDRALLOC
-/** Will return 1 if the remat flag is set.
-    A symbol is rematerialisable if it doesn't need to be allocated
-    into registers at creation as it can be re-created at any time -
-    i.e. it's constant in some way.
-*/
-static int
-rematable (symbol * sym, eBBlock * ebp, iCode * ic)
-{
-  return sym->remat;
-}
-#endif
-
-#ifdef OLDRALLOC
-/*-----------------------------------------------------------------*/
-/* allLRs - return true for all                                    */
-/*-----------------------------------------------------------------*/
-static int
-allLRs (symbol * sym, eBBlock * ebp, iCode * ic)
-{
-  return 1;
-}
-#endif
-
-#ifdef OLDRALLOC
-/** liveRangesWith - applies function to a given set of live range
- */
-static set *
-liveRangesWith (bitVect * lrs, int (func) (symbol *, eBBlock *, iCode *), eBBlock * ebp, iCode * ic)
-{
-  set *rset = NULL;
-  int i;
-
-  if (!lrs || !lrs->size)
-    return NULL;
-
-  for (i = 1; i < lrs->size; i++)
-    {
-      symbol *sym;
-      if (!bitVectBitValue (lrs, i))
-        continue;
-
-      /* if we don't find it in the live range
-         hash table we are in serious trouble */
-      if (!(sym = hTabItemWithKey (liveRanges, i)))
-        {
-          wassertl (0, "liveRangesWith could not find liveRange");
-          exit (1);
-        }
-
-      if (func (sym, ebp, ic) && bitVectBitValue (_G.regAssigned, sym->key))
-        {
-          addSetHead (&rset, sym);
-        }
-    }
-
-  return rset;
-}
-#endif
-
-#ifdef OLDRALLOC
-/** leastUsedLR - given a set determines which is the least used
- */
-static symbol *
-leastUsedLR (set * sset)
-{
-  symbol *sym = NULL, *lsym = NULL;
-
-  sym = lsym = setFirstItem (sset);
-
-  if (!lsym)
-    return NULL;
-
-  for (; lsym; lsym = setNextItem (sset))
-    {
-
-      /* if usage is the same then prefer
-         the spill the smaller of the two */
-      if (lsym->used == sym->used)
-        if (getSize (lsym->type) < getSize (sym->type))
-          sym = lsym;
-
-      /* if less usage */
-      if (lsym->used < sym->used)
-        sym = lsym;
-
-    }
-
-  setToNull ((void *) &sset);
-  sym->blockSpil = 0;
-  return sym;
-}
-#endif
-
 /** noOverLap - will iterate through the list looking for over lap
  */
 static int
@@ -555,249 +313,6 @@
   return;
 }
 
-#ifdef OLDRALLOC
-/** Select a iTemp to spil : rather a simple procedure.
- */
-symbol *
-selectSpil (iCode * ic, eBBlock * ebp, symbol * forSym)
-{
-  bitVect *lrcs = NULL;
-  set *selectS;
-  symbol *sym;
-
-  D (D_ALLOC, ("selectSpil: finding spill for ic %p\n", ic));
-  /* get the spillable live ranges */
-  lrcs = computeSpillable (ic);
-
-  /* get all live ranges that are rematerizable */
-  if ((selectS = liveRangesWith (lrcs, rematable, ebp, ic)))
-    {
-      D (D_ALLOC, ("selectSpil: using remat.\n"));
-      /* return the least used of these */
-      return leastUsedLR (selectS);
-    }
-
-#if 0
-  /* get live ranges with spillLocations in direct space */
-  if ((selectS = liveRangesWith (lrcs, directSpilLoc, ebp, ic)))
-    {
-      sym = leastUsedLR (selectS);
-      strcpy (sym->rname, (sym->usl.spillLoc->rname[0] ? sym->usl.spillLoc->rname : sym->usl.spillLoc->name));
-      sym->spildir = 1;
-      /* mark it as allocation required */
-      sym->usl.spillLoc->allocreq++;
-      return sym;
-    }
-
-  /* if the symbol is local to the block then */
-  if (forSym->liveTo < ebp->lSeq)
-    {
-
-      /* check if there are any live ranges allocated
-         to registers that are not used in this block */
-      if (!_G.blockSpil && (selectS = liveRangesWith (lrcs, notUsedInBlock, ebp, ic)))
-        {
-          sym = leastUsedLR (selectS);
-          /* if this is not rematerializable */
-          if (!sym->remat)
-            {
-              _G.blockSpil++;
-              wassertl (0, "Attempted to do an unsupported block spill");
-              sym->blockSpil = 1;
-            }
-          return sym;
-        }
-
-      /* check if there are any live ranges that not
-         used in the remainder of the block */
-      if (!_G.blockSpil && (selectS = liveRangesWith (lrcs, notUsedInRemaining, ebp, ic)))
-        {
-          sym = leastUsedLR (selectS);
-          if (sym != forSym)
-            {
-              if (!sym->remat)
-                {
-                  wassertl (0, "Attempted to do an unsupported remain spill");
-                  sym->remainSpil = 1;
-                  _G.blockSpil++;
-                }
-              return sym;
-            }
-        }
-    }
-  /* find live ranges with spillocation && not used as pointers */
-  if ((selectS = liveRangesWith (lrcs, hasSpilLocnoUptr, ebp, ic)))
-    {
-
-      sym = leastUsedLR (selectS);
-      /* mark this as allocation required */
-      sym->usl.spillLoc->allocreq++;
-      return sym;
-    }
-#endif
-
-  /* find live ranges with spillocation */
-  if ((selectS = liveRangesWith (lrcs, hasSpilLoc, ebp, ic)))
-    {
-      D (D_ALLOC, ("selectSpil: using with spill.\n"));
-      sym = leastUsedLR (selectS);
-      sym->usl.spillLoc->allocreq++;
-      return sym;
-    }
-
-  /* couldn't find then we need to create a spil
-     location on the stack , for which one? the least
-     used ofcourse */
-  if ((selectS = liveRangesWith (lrcs, noSpilLoc, ebp, ic)))
-    {
-      D (D_ALLOC, ("selectSpil: creating new spill.\n"));
-      /* return a created spil location */
-      sym = createStackSpil (leastUsedLR (selectS));
-      sym->usl.spillLoc->allocreq++;
-      return sym;
-    }
-
-  /* this is an extreme situation we will spill
-     this one : happens very rarely but it does happen */
-  D (D_ALLOC, ("selectSpil: using z80SpillThis.\n"));
-  z80SpillThis (forSym);
-  return forSym;
-
-}
-#endif
-
-#ifdef OLDRALLOC
-/** Spil some variable & mark registers as free.
-    A spill occurs when an iTemp wont fit into the available registers.
- */
-bool
-spilSomething (iCode * ic, eBBlock * ebp, symbol * forSym)
-{
-  symbol *ssym;
-  int i;
-
-  D (D_ALLOC, ("spilSomething: spilling on ic %p\n", ic));
-
-  /* get something we can spil */
-  ssym = selectSpil (ic, ebp, forSym);
-
-  /* mark it as spilt */
-  ssym->isspilt = ssym->spillA = 1;
-  _G.spiltSet = bitVectSetBit (_G.spiltSet, ssym->key);
-
-  /* mark it as not register assigned &
-     take it away from the set */
-  bitVectUnSetBit (_G.regAssigned, ssym->key);
-  bitVectUnSetBit (_G.totRegAssigned, ssym->key);
-
-  /* mark the registers as free */
-  for (i = 0; i < ssym->nRegs; i++)
-    if (ssym->regs[i])
-      freeReg (ssym->regs[i]);
-
-  wassertl (ssym->blockSpil == 0, "Encountered a sym with a block spill");
-  wassertl (ssym->remainSpil == 0, "Encountered a sym with a remain spill");
-#if 0
-  /* if spilt on stack then free up r0 & r1
-     if they could have been assigned to as gprs */
-  if (!ptrRegReq && isSpiltOnStack (ssym))
-    {
-      ptrRegReq++;
-      spillLRWithPtrReg (ssym);
-    }
-
-  /* if this was a block level spil then insert push & pop
-     at the start & end of block respectively */
-  if (ssym->blockSpil)
-    {
-      iCode *nic = newiCode (IPUSH, operandFromSymbol (ssym), NULL);
-      /* add push to the start of the block */
-      addiCodeToeBBlock (ebp, nic, (ebp->sch->op == LABEL ? ebp->sch->next : ebp->sch));
-      nic = newiCode (IPOP, operandFromSymbol (ssym), NULL);
-      /* add pop to the end of the block */
-      addiCodeToeBBlock (ebp, nic, NULL);
-    }
-
-  /* if spilt because not used in the remainder of the
-     block then add a push before this instruction and
-     a pop at the end of the block */
-  if (ssym->remainSpil)
-    {
-
-      iCode *nic = newiCode (IPUSH, operandFromSymbol (ssym), NULL);
-      /* add push just before this instruction */
-      addiCodeToeBBlock (ebp, nic, ic);
-
-      nic = newiCode (IPOP, operandFromSymbol (ssym), NULL);
-      /* add pop to the end of the block */
-      addiCodeToeBBlock (ebp, nic, NULL);
-    }
-#endif
-
-  D (D_ALLOC, ("spilSomething: done.\n"));
-
-  if (ssym == forSym)
-    return FALSE;
-  else
-    return TRUE;
-}
-#endif
-
-#ifdef OLDRALLOC
-/** Will try for GPR if not spil.
- */
-reg_info *
-getRegGpr (iCode * ic, eBBlock * ebp, symbol * sym)
-{
-  reg_info *reg;
-  int j;
-
-  D (D_ALLOC, ("getRegGpr: on ic %p\n", ic));
-tryAgain:
-  /* try for gpr type */
-  if ((reg = allocReg (REG_GPR)))
-    {
-      D (D_ALLOC, ("getRegGpr: got a reg.\n"));
-      return reg;
-    }
-
-  /* we have to spil */
-  if (!spilSomething (ic, ebp, sym))
-    {
-      D (D_ALLOC, ("getRegGpr: have to spill.\n"));
-      return NULL;
-    }
-
-  /* make sure partially assigned registers aren't reused */
-  for (j = 0; j <= sym->nRegs; j++)
-    if (sym->regs[j])
-      sym->regs[j]->isFree = 0;
-
-  /* this looks like an infinite loop but
-     in really selectSpil will abort  */
-  goto tryAgain;
-}
-#endif
-
-#ifdef OLDRALLOC
-static reg_info *
-getRegGprNoSpil ()
-{
-  reg_info *reg;
-
-  /* try for gpr type */
-  if ((reg = allocReg (REG_GPR)))
-    {
-      D (D_ALLOC, ("getRegGprNoSpil: got a reg.\n"));
-      return reg;
-    }
-  assert (0);
-
-  /* just to make the compiler happy */
-  return 0;
-}
-#endif
-
 /** Symbol has a given register.
  */
 static bool
@@ -820,9 +335,6 @@
 {
   symbol *sym;
   int k;
-#ifdef OLDRALLOC
-  symbol *result;
-#endif
 
   for (sym = hTabFirstItem (liveRanges, &k); sym; sym = hTabNextItem (liveRanges, &k))
     {
@@ -862,46 +374,6 @@
 
           bitVectUnSetBit (_G.regAssigned, sym->key);
 
-#ifdef OLDRALLOC
-          /* if the result of this one needs registers
-             and does not have it then assign it right
-             away */
-          if (options.oldralloc && IC_RESULT (ic) &&
-              !(SKIP_IC2 (ic) || ic->op == JUMPTABLE || ic->op == IFX || ic->op == IPUSH || ic->op == IPOP || ic->op == RETURN) &&
-              IS_SYMOP (IC_RESULT (ic)) && (result = OP_SYMBOL (IC_RESULT (ic))) &&    /* has a result */
-              result->liveTo > ic->seq &&       /* and will live beyond this */
-              result->liveTo <= ebp->lSeq &&    /* does not go beyond this block */
-              result->liveFrom == ic->seq &&    /* does not start before here */
-              result->regType == sym->regType &&        /* same register types */
-              result->nRegs &&  /* which needs registers */
-              !result->isspilt &&       /* and does not already have them */
-              !result->remat && !bitVectBitValue (_G.regAssigned, result->key) &&
-              /* the number of free regs + number of regs in this LR
-                 can accomodate the what result Needs */
-              ((nfreeRegsType (result->regType) + sym->nRegs) >= result->nRegs))
-            {
-              for (i = 0; i < result->nRegs; i++)
-                {
-                  if (i < sym->nRegs)
-                    result->regs[i] = sym->regs[i];
-                  else
-                    result->regs[i] = getRegGpr (ic, ebp, result);
-
-                  /* if the allocation failed which means
-                     this was spilt then break */
-                  if (!result->regs[i])
-                    {
-                      wassert (0);
-                      assert (0);
-                      break;
-                    }
-                }
-
-              _G.regAssigned = bitVectSetBit (_G.regAssigned, result->key);
-              _G.totRegAssigned = bitVectSetBit (_G.totRegAssigned, result->key);
-            }
-#endif
-
           /* free the remaining */
           for (; i < sym->nRegs; i++)
             {
@@ -940,478 +412,32 @@
     sym->regs[i]->isFree = 0;
 }
 
-#ifdef OLDRALLOC
-/** Determines if allocating will cause a spill.
- */
-static int
-willCauseSpill (int nr, int rt)
+/*------------------------------------------------------------------*/
+/* verifyRegsAssigned - make sure an iTemp is properly initialized; */
+/* it should either have registers or have beed spilled. Otherwise, */
+/* there was an uninitialized variable, so just spill this to get   */
+/* the operand in a valid state.                                    */
+/*------------------------------------------------------------------*/
+static void
+verifyRegsAssigned (operand *op, iCode *ic)
 {
-  /* first check if there are any avlb registers
-     of te type required */
-  if (nFreeRegs (0) >= nr)
-    return 0;
+  symbol *sym;
 
-  /* it will cause a spil */
-  return 1;
+  if (!op)
+    return;
+  if (!IS_ITEMP (op))
+    return;
+
+  sym = OP_SYMBOL (op);
+  if (sym->isspilt)
+    return;
+  if (!sym->nRegs)
+    return;
+  if (sym->regs[0])
+    return;
+
+  z80SpillThis (sym);
 }
-#endif
-
-#ifdef OLDRALLOC
-/** The allocator can allocate same registers to result and operand,
-    if this happens make sure they are in the same position as the operand
-    otherwise chaos results.
-*/
-static int
-positionRegs (symbol * result, symbol * opsym)
-{
-  int count = min (result->nRegs, opsym->nRegs);
-  int i, j = 0, shared = 0;
-  int change = 0;
-
-  D (D_ALLOC, ("positionRegs: on result %p opsym %p line %u\n", result, opsym, lineno));
-
-  /* if the result has been spilt then cannot share */
-  if (opsym->isspilt)
-    return 0;
-again:
-  shared = 0;
-  /* first make sure that they actually share */
-
-  for (i = 0; i < count; i++)
-    {
-      for (j = 0; j < count; j++)
-        {
-          if (result->regs[i] == opsym->regs[j] && i != j)
-            {
-              shared = 1;
-              goto xchgPositions;
-            }
-        }
-    }
-xchgPositions:
-  if (shared)
-    {
-      reg_info *tmp = result->regs[i];
-      result->regs[i] = result->regs[j];
-      result->regs[j] = tmp;
-      change++;
-      goto again;
-    }
-  return change;
-}
-#endif
-
-#ifdef OLDRALLOC
-/** Try to allocate a pair of registers to the symbol.
- */
-bool
-tryAllocatingRegPair (symbol * sym)
-{
-  int i;
-  wassert (sym->nRegs == 2);
-  for (i = C_IDX; i < _G.nRegs; i += 2)
-    {
-      if ((regsZ80[i].isFree) && (regsZ80[i + 1].isFree))
-        {
-          regsZ80[i].isFree = 0;
-          sym->regs[0] = ®sZ80[i];
-          regsZ80[i + 1].isFree = 0;
-          sym->regs[1] = ®sZ80[i + 1];
-          sym->regType = REG_PAIR;
-
-          if (currFunc)
-            {
-              currFunc->regsUsed = bitVectSetBit (currFunc->regsUsed, i);
-              currFunc->regsUsed = bitVectSetBit (currFunc->regsUsed, i + 1);
-            }
-          D (D_ALLOC, ("tryAllocatingRegPair: succeded for sym %p\n", sym));
-          return TRUE;
-        }
-    }
-  D (D_ALLOC, ("tryAllocatingRegPair: failed on sym %p\n", sym));
-  return FALSE;
-}
-#endif
-/*------------------------------------------------------------------*/
-/* verifyRegsAssigned - make sure an iTemp is properly initialized; */
-/* it should either have registers or have beed spilled. Otherwise, */
-/* there was an uninitialized variable, so just spill this to get   */
-/* the operand in a valid state.                                    */
-/*------------------------------------------------------------------*/
-static void
-verifyRegsAssigned (operand *op, iCode *ic)
-{
-  symbol *sym;
-
-  if (!op)
-    return;
-  if (!IS_ITEMP (op))
-    return;
-
-  sym = OP_SYMBOL (op);
-  if (sym->isspilt)
-    return;
-  if (!sym->nRegs)
-    return;
-  if (sym->regs[0])
-    return;
-
-  // Don't warn for new allocator, since this is now used by default.
-  if (options.oldralloc)
-    werrorfl (ic->filename, ic->lineno, W_LOCAL_NOINIT, sym->prereqv ? sym->prereqv->name : sym->name);
-  z80SpillThis (sym);
-}
-
-#ifdef OLDRALLOC
-/** Serially allocate registers to the variables.
-    This is the main register allocation function.  It is called after
-    packing.
- */
-static void
-serialRegAssign (eBBlock ** ebbs, int count)
-{
-  int i;
-
-  /* for all blocks */
-  for (i = 0; i < count; i++)
-    {
-      iCode *ic;
-
-      if (ebbs[i]->noPath && (ebbs[i]->entryLabel != entryLabel && ebbs[i]->entryLabel != returnLabel))
-        continue;
-
-      /* for all instructions do */
-      for (ic = ebbs[i]->sch; ic; ic = ic->next)
-        {
-          /* if this is an ipop that means some live
-             range will have to be assigned again */
-          if (ic->op == IPOP)
-            {
-              wassert (0);
-              reassignLR (IC_LEFT (ic));
-            }
-
-          /* if result is present && is a true symbol */
-          if (IC_RESULT (ic) && ic->op != IFX && IS_TRUE_SYMOP (IC_RESULT (ic)))
-            {
-              OP_SYMBOL (IC_RESULT (ic))->allocreq++;
-            }
-
-          /* take away registers from live
-             ranges that end at this instruction */
-          deassignLRs (ic, ebbs[i]);
-
-          /* some don't need registers */
-          if (SKIP_IC2 (ic) ||
-              ic->op == JUMPTABLE || ic->op == IFX || ic->op == IPUSH || ic->op == IPOP || (IC_RESULT (ic) && POINTER_SET (ic)))
-            {
-              continue;
-            }
-
-          /* now we need to allocate registers only for the result */
-          if (IC_RESULT (ic))
-            {
-              symbol *sym = OP_SYMBOL (IC_RESULT (ic));
-              bitVect *spillable;
-              int willCS;
-              int j;
-
-              D (D_ALLOC, ("serialRegAssign: in loop on result %p %s\n", sym, sym->name));
-
-              /* Make sure any spill location is definately allocated */
-              if (sym->isspilt && !sym->remat && sym->usl.spillLoc && !sym->usl.spillLoc->allocreq)
-                {
-                  sym->usl.spillLoc->allocreq++;
-                }
-
-              /* if it does not need or is spilt
-                 or is already assigned to registers
-                 or will not live beyond this instructions */
-              if (!sym->nRegs || sym->isspilt || bitVectBitValue (_G.regAssigned, sym->key) || sym->liveTo <= ic->seq)
-                {
-                  D (D_ALLOC, ("serialRegAssign: won't live long enough.\n"));
-                  continue;
-                }
-
-              /* if some liverange has been spilt at the block level
-                 and this one live beyond this block then spil this
-                 to be safe */
-              if (_G.blockSpil && sym->liveTo > ebbs[i]->lSeq)
-                {
-                  D (D_ALLOC, ("serialRegAssign: \"spilling to be safe.\"\n"));
-                  z80SpillThis (sym);
-                  continue;
-                }
-              /* if trying to allocate this will cause
-                 a spill and there is nothing to spill
-                 or this one is rematerializable then
-                 spill this one */
-              willCS = willCauseSpill (sym->nRegs, sym->regType);
-              spillable = computeSpillable (ic);
-              if (sym->remat || (willCS && bitVectIsZero (spillable)))
-                {
-
-                  D (D_ALLOC, ("serialRegAssign: \"remat spill\"\n"));
-                  z80SpillThis (sym);
-                  continue;
-
-                }
-
-              /* If the live range preceeds the point of definition
-                 then ideally we must take into account registers that
-                 have been allocated after sym->liveFrom but freed
-                 before ic->seq. This is complicated, so spill this
-                 symbol instead and let fillGaps handle the allocation. */
-              if (sym->liveFrom < ic->seq)
-                {
-                  z80SpillThis (sym);
-                  continue;
-                }
-
-              /* if it has a spillocation & is used less than
-                 all other live ranges then spill this */
-              if (willCS)
-                {
-                  if (sym->usl.spillLoc)
-                    {
-                      symbol *leastUsed = leastUsedLR (liveRangesWith (spillable,
-                                                                       allLRs, ebbs[i], ic));
-                      if (leastUsed && leastUsed->used > sym->used)
-                        {
-                          z80SpillThis (sym);
-                          continue;
-                        }
-                    }
-                  else
-                    {
-                      /* if none of the liveRanges have a spillLocation then better
-                         to spill this one than anything else already assigned to registers */
-                      if (liveRangesWith (spillable, noSpilLoc, ebbs[i], ic))
-                        {
-                          /* if this is local to this block then we might find a block spil */
-                          if (!(sym->liveFrom >= ebbs[i]->fSeq && sym->liveTo <= ebbs[i]->lSeq))
-                            {
-                              z80SpillThis (sym);
-                              continue;
-                            }
-                        }
-                    }
-                }
-
-              /* else we assign registers to it */
-              _G.regAssigned = bitVectSetBit (_G.regAssigned, sym->key);
-              _G.totRegAssigned = bitVectSetBit (_G.totRegAssigned, sym->key);
-
-              /* Special case:  Try to fit into a reg pair if
-                 available */
-              D (D_ALLOC, ("serialRegAssign: actually allocing regs!\n"));
-              if ((sym->nRegs == 2) && tryAllocatingRegPair (sym))
-                {
-                }
-              else
-                {
-                  for (j = 0; j < sym->nRegs; j++)
-                    {
-                      sym->regs[j] = getRegGpr (ic, ebbs[i], sym);
-
-                      /* if the allocation falied which means
-                         this was spilt then break */
-                      if (!sym->regs[j])
-                        {
-                          D (D_ALLOC, ("Couldnt alloc (spill)\n")) break;
-                        }
-                    }
-                  /* Make sure we didn't allocate a register pair with bytes swapped */
-                  if (sym->nRegs == 2 && sym->regs[0] == sym->regs[1] + 1 && sym->regs[0] != ®sZ80[2])
-                    {
-                      freeReg (sym->regs[0]);
-                      freeReg (sym->regs[1]);
-                      if (!tryAllocatingRegPair (sym))
-                        wassertl (0, "Failed to swap register pair bytes back.");
-                    }
-                }
-              /* if it shares registers with operands make sure
-                 that they are in the same position */
-              if (IC_LEFT (ic) && IS_SYMOP (IC_LEFT (ic)) && OP_SYMBOL (IC_LEFT (ic))->nRegs && ic->op != '=')
-                positionRegs (OP_SYMBOL (IC_RESULT (ic)), OP_SYMBOL (IC_LEFT (ic)));
-              /* do the same for the right operand */
-              if (IC_RIGHT (ic) && IS_SYMOP (IC_RIGHT (ic)) && OP_SYMBOL (IC_RIGHT (ic))->nRegs)
-                positionRegs (OP_SYMBOL (IC_RESULT (ic)), OP_SYMBOL (IC_RIGHT (ic)));
-
-            }
-        }
-    }
-
-  /* Check for and fix any problems with uninitialized operands */
-  for (i = 0; i < count; i++)
-    {
-      iCode *ic;
-
-      if (ebbs[i]->noPath && (ebbs[i]->entryLabel != entryLabel && ebbs[i]->entryLabel != returnLabel))
-        continue;
-
-      for (ic = ebbs[i]->sch; ic; ic = ic->next)
-        {
-          if (SKIP_IC2 (ic))
-            continue;
-
-          if (ic->op == IFX)
-            {
-              verifyRegsAssigned (IC_COND (ic), ic);
-              continue;
-            }
-
-          if (ic->op == JUMPTABLE)
-            {
-              verifyRegsAssigned (IC_JTCOND (ic), ic);
-              continue;
-            }
-
-          verifyRegsAssigned (IC_RESULT (ic), ic);
-          verifyRegsAssigned (IC_LEFT (ic), ic);
-          verifyRegsAssigned (IC_RIGHT (ic), ic);
-        }
-    }
-
-}
-#endif
-
-#ifdef OLDRALLOC
-/*-----------------------------------------------------------------*/
-/* fillGaps - Try to fill in the Gaps left by Pass1                */
-/*-----------------------------------------------------------------*/
-static void
-fillGaps ()
-{
-  symbol *sym = NULL;
-  int key = 0;
-
-  if (getenv ("DISABLE_FILL_GAPS"))
-    return;
-
-  /* look for livernages that was spilt by the allocator */
-  for (sym = hTabFirstItem (liveRanges, &key); sym; sym = hTabNextItem (liveRanges, &key))
-    {
-
-      int i;
-      int pdone = 0;
-
-      if (sym->accuse == ACCUSE_SCRATCH)
-        {
-          sym->nRegs = getSize (sym->type);
-          sym->regs[0] = regsZ80 + L_IDX;
-          sym->regs[1] = regsZ80 + H_IDX;
-          sym->accuse = 0;
-          sym->isspilt = FALSE;
-          continue;
-        }
-
-      if (!sym->spillA || !sym->clashes || sym->remat)
-        continue;
-
-      /* find the liveRanges this one clashes with, that are
-         still assigned to registers & mark the registers as used */
-      for (i = 0; i < sym->clashes->size; i++)
-        {
-          int k;
-          symbol *clr;
-
-          if (bitVectBitValue (sym->clashes, i) == 0 || /* those that clash with this */
-              bitVectBitValue (_G.totRegAssigned, i) == 0)      /* and are still assigned to registers */
-            continue;
-
-          clr = hTabItemWithKey (liveRanges, i);
-          assert (clr);
-
-          /* mark these registers as used */
-          for (k = 0; k < clr->nRegs; k++)
-            useReg (clr->regs[k]);
-        }
-
-      if (willCauseSpill (sym->nRegs, sym->regType))
-        {
-          /* NOPE :( clear all registers & and continue */
-          freeAllRegs ();
-          continue;
-        }
-
-      /* THERE IS HOPE !!!! */
-      for (i = 0; i < sym->nRegs; i++)
-        {
-          sym->regs[i] = getRegGprNoSpil ();
-        }
-
-      /* for all its definitions check if the registers
-         allocated needs positioning NOTE: we can position
-         only ONCE if more than One positioning required
-         then give up */
-      sym->isspilt = 0;
-      for (i = 0; i < sym->defs->size; i++)
-        {
-          if (bitVectBitValue (sym->defs, i))
-            {
-              iCode *ic;
-              if (!(ic = hTabItemWithKey (iCodehTab, i)))
-                continue;
-              if (SKIP_IC (ic))
-                continue;
-              assert (isSymbolEqual (sym, OP_SYMBOL (IC_RESULT (ic)))); /* just making sure */
-              /* if left is assigned to registers */
-              if (IS_SYMOP (IC_LEFT (ic)) && bitVectBitValue (_G.totRegAssigned, OP_SYMBOL (IC_LEFT (ic))->key))
-                {
-                  pdone += positionRegs (sym, OP_SYMBOL (IC_LEFT (ic)));
-                }
-              if (IS_SYMOP (IC_RIGHT (ic)) && bitVectBitValue (_G.totRegAssigned, OP_SYMBOL (IC_RIGHT (ic))->key))
-                {
-                  pdone += positionRegs (sym, OP_SYMBOL (IC_RIGHT (ic)));
-                }
-              if (pdone > 1)
-                break;
-            }
-        }
-      for (i = 0; i < sym->uses->size; i++)
-        {
-          if (bitVectBitValue (sym->uses, i))
-            {
-              iCode *ic;
-              if (!(ic = hTabItemWithKey (iCodehTab, i)))
-                continue;
-              if (SKIP_IC (ic))
-                continue;
-              if (IS_ASSIGN_ICODE (ic))
-                continue;
-
-              /* if result is assigned to registers */
-              if (IS_SYMOP (IC_RESULT (ic)) && bitVectBitValue (_G.totRegAssigned, OP_SYMBOL (IC_RESULT (ic))->key))
-                {
-                  pdone += positionRegs (sym, OP_SYMBOL (IC_RESULT (ic)));
-                }
-              if (pdone > 1)
-                break;
-            }
-        }
-      /* had to position more than once GIVE UP */
-      if (pdone > 1)
-        {
-          /* UNDO all the changes we made to try this */
-          sym->isspilt = 1;
-          for (i = 0; i < sym->nRegs; i++)
-            {
-              sym->regs[i] = NULL;
-            }
-          freeAllRegs ();
-          D (D_FILL_GAPS,
-             ("Fill Gap gave up due to positioning for %s in function %s\n", sym->name, currFunc ? currFunc->name : "UNKNOWN"));
-          continue;
-        }
-      D (D_FILL_GAPS, ("FILLED GAP for %s in function %s\n", sym->name, currFunc ? currFunc->name : "UNKNOWN"));
-      _G.totRegAssigned = bitVectSetBit (_G.totRegAssigned, sym->key);
-      sym->isspilt = sym->spillA = 0;
-      sym->usl.spillLoc->allocreq--;
-      freeAllRegs ();
-    }
-}
-#endif
 
 /*-----------------------------------------------------------------*/
 /* rUmaskForOp :- returns register mask for an operand             */
@@ -1434,7 +460,7 @@
   if (sym->isspilt || !sym->nRegs)
     return NULL;
 
-  rumask = newBitVect (_G.nRegs + (IS_GB ? 0 : 2));
+  rumask = newBitVect (IS_SM83 ? SM83_MAX_REGS : Z80_MAX_REGS);
 
   for (j = 0; j < sym->nRegs; j++)
     {
@@ -1460,7 +486,7 @@
 bitVect *
 regsUsedIniCode (iCode * ic)
 {
-  bitVect *rmask = newBitVect (_G.nRegs + (IS_GB ? 0 : 2));
+  bitVect *rmask = newBitVect (IS_SM83 ? SM83_MAX_REGS : Z80_MAX_REGS);
 
   /* do the special cases first */
   if (ic->op == IFX)
@@ -1491,138 +517,17 @@
   return rmask;
 }
 
-/** For each instruction will determine the regsUsed.
- */
+/*-----------------------------------------------------------------*/
+/* regTypeNum - computes the type & number of registers required   */
+/*-----------------------------------------------------------------*/
 static void
-createRegMask (eBBlock ** ebbs, int count)
+regTypeNum (void)
 {
-  int i;
+  symbol *sym;
+  int k;
 
-  /* for all blocks */
-  for (i = 0; i < count; i++)
-    {
-      iCode *ic;
-
-      if (ebbs[i]->noPath && (ebbs[i]->entryLabel != entryLabel && ebbs[i]->entryLabel != returnLabel))
-        continue;
-
-      /* for all instructions */
-      for (ic = ebbs[i]->sch; ic; ic = ic->next)
-        {
-
-          int j;
-
-          if (SKIP_IC2 (ic) || !ic->rlive)
-            continue;
-
-          /* first mark the registers used in this
-             instruction */
-
-          ic->rSurv = newBitVect(port->num_regs);
-          ic->rUsed = regsUsedIniCode (ic);
-          _G.funcrUsed = bitVectUnion (_G.funcrUsed, ic->rUsed);
-
-          /* now create the register mask for those
-             registers that are in use : this is a
-             super set of ic->rUsed */
-          ic->rMask = newBitVect (_G.nRegs + 1 + (IS_GB ? 0 : 2));
-
-          /* for all live Ranges alive at this point */
-          for (j = 1; j < ic->rlive->size; j++)
-            {
-              symbol *sym;
-              int k;
-
-              /* if not alive then continue */
-              if (!bitVectBitValue (ic->rlive, j))
-                continue;
-
-              /* find the live range we are interested in */
-              if (!(sym = hTabItemWithKey (liveRanges, j)))
-                {
-                  werror (E_INTERNAL_ERROR, __FILE__, __LINE__, "createRegMask cannot find live range");
-                  exit (0);
-                }
-
-              /* if no register assigned to it */
-              if (!sym->nRegs || sym->isspilt)
-                continue;
-
-              /* for all the registers allocated to it */
-              for (k = 0; k < sym->nRegs; k++)
-                {
-                  if (!sym->regs[k])
-                    continue;
-                  ic->rMask = bitVectSetBit (ic->rMask, sym->regs[k]->rIdx);
-                  if (sym->liveTo != ic->key)
-                    ic->rSurv = bitVectSetBit (ic->rSurv, sym->regs[k]->rIdx);
-                }
-            }
-        }
-    }
-}
-
-#if 0
-/** Returns the rematerialized string for a remat var.
- */
-static char *
-rematStr (symbol * sym)
-{
-  iCode *ic = sym->rematiCode;
-  int offset = 0;
-
-  while (1)
-    {
-      /* if plus adjust offset to right hand side */
-      if (ic->op == '+')
-        {
-          offset += (int) operandLitValue (IC_RIGHT (ic));
-          ic = OP_SYMBOL (IC_LEFT (ic))->rematiCode;
-          continue;
-        }
-
-      /* if minus adjust offset to right hand side */
-      if (ic->op == '-')
-        {
-          offset -= (int) operandLitValue (IC_RIGHT (ic));
-          ic = OP_SYMBOL (IC_LEFT (ic))->rematiCode;
-          continue;
-        }
-
-      /* cast then continue */
-      if (IS_CAST_ICODE (ic))
-        {
-          ic = OP_SYMBOL (IC_RIGHT (ic))->rematiCode;
-          continue;
-        }
-      /* we reached the end */
-      break;
-    }
-
-  if (offset)
-    {
-      SNPRINTF (buffer, sizeof (buffer),
-                "(%s %c 0x%04x)", OP_SYMBOL (IC_LEFT (ic))->rname, offset >= 0 ? '+' : '-', abs (offset) & 0xffff);
-    }
-  else
-    {
-      strncpyz (buffer, OP_SYMBOL (IC_LEFT (ic))->rname, sizeof (buffer));
-    }
-  return buffer;
-}
-#endif
-
-/*-----------------------------------------------------------------*/
-/* regTypeNum - computes the type & number of registers required   */
-/*-----------------------------------------------------------------*/
-static void
-regTypeNum (void)
-{
-  symbol *sym;
-  int k;
-
-  /* for each live range do */
-  for (sym = hTabFirstItem (liveRanges, &k); sym; sym = hTabNextItem (liveRanges, &k))
+  /* for each live range do */
+  for (sym = hTabFirstItem (liveRanges, &k); sym; sym = hTabNextItem (liveRanges, &k))
     {
       /* if used zero times then no registers needed */
       if ((sym->liveTo - sym->liveFrom) == 0 && getSize (sym->type) <= 4)
@@ -1632,6 +537,11 @@
           iCode *dic = hTabItemWithKey (iCodehTab, bitVectFirstBit (sym->defs));
           if (!dic || dic->op != CALL && dic->op != PCALL)
             continue;
+          if (IS_STRUCT (sym->type)) // We found an unused return value of struct or union type.
+            {
+              z80SpillThis (sym);
+              continue;
+            }
         }
 
       D (D_ALLOC, ("regTypeNum: loop on sym %p\n", sym));
@@ -1720,7 +630,7 @@
 
   if (!IS_ITEMP (IC_RIGHT (ic)) || OP_SYMBOL (IC_RIGHT (ic))->isind || OP_LIVETO (IC_RIGHT (ic)) > ic->seq)
     return 0;
-  
+
   /* Avoid having multiple named address spaces in one iCode. */
   if (IS_SYMOP (IC_RESULT (ic)) && SPEC_ADDRSPACE (OP_SYMBOL (IC_RESULT (ic))->etype))
     return 0;
@@ -1912,759 +822,158 @@
   /* now make sure that the right side of dic
      is not defined between ic & dic */
   if (dic)
-    {
-      iCode *sic = dic->next;
-
-      for (; sic != ic; sic = sic->next)
-        if (IC_RESULT (sic) && IC_RESULT (sic)->key == IC_RIGHT (dic)->key)
-          return NULL;
-    }
-
-  return dic;
-
-
-}
-
-#if !DISABLE_PACKREGSFORSUPPORT
-// PENDING
-
-/*-----------------------------------------------------------------*/
-/* packRegsForSupport :- reduce some registers for support calls   */
-/*-----------------------------------------------------------------*/
-static int
-packRegsForSupport (iCode * ic, eBBlock * ebp)
-{
-  int change = 0;
-  /* for the left & right operand :- look to see if the
-     left was assigned a true symbol in far space in that
-     case replace them */
-  D (D_ALLOC, ("packRegsForSupport: running on ic %p\n", ic));
-
-  if (IS_ITEMP (IC_LEFT (ic)) && OP_SYMBOL (IC_LEFT (ic))->liveTo <= ic->seq)
-    {
-      iCode *dic = findAssignToSym (IC_LEFT (ic), ic);
-      iCode *sic;
-
-      if (!dic)
-        goto right;
-
-      /* found it we need to remove it from the
-         block */
-      for (sic = dic; sic != ic; sic = sic->next)
-        bitVectUnSetBit (sic->rlive, IC_LEFT (ic)->key);
-
-      IC_LEFT (ic)->operand.symOperand = IC_RIGHT (dic)->operand.symOperand;
-      IC_LEFT (ic)->key = IC_RIGHT (dic)->operand.symOperand->key;
-      remiCodeFromeBBlock (ebp, dic);
-      bitVectUnSetBit (OP_SYMBOL (IC_RESULT (dic))->defs, dic->key);
-      hTabDeleteItem (&iCodehTab, dic->key, dic, DELETE_ITEM, NULL);
-      // PENDING: Check vs mcs51
-      change++;
-    }
-
-  /* do the same for the right operand */
-right:
-  if (!change && IS_ITEMP (IC_RIGHT (ic)) && OP_SYMBOL (IC_RIGHT (ic))->liveTo <= ic->seq)
-    {
-      iCode *dic = findAssignToSym (IC_RIGHT (ic), ic);
-      iCode *sic;
-
-      if (!dic)
-        return change;
-
-      /* found it we need to remove it from the block */
-      for (sic = dic; sic != ic; sic = sic->next)
-        bitVectUnSetBit (sic->rlive, IC_RIGHT (ic)->key);
-
-      IC_RIGHT (ic)->operand.symOperand = IC_RIGHT (dic)->operand.symOperand;
-      IC_RIGHT (ic)->key = IC_RIGHT (dic)->operand.symOperand->key;
-
-      remiCodeFromeBBlock (ebp, dic);
-      bitVectUnSetBit (OP_SYMBOL (IC_RESULT (dic))->defs, dic->key);
-      hTabDeleteItem (&iCodehTab, dic->key, dic, DELETE_ITEM, NULL);
-      // PENDING: vs mcs51
-      change++;
-    }
-
-  return change;
-}
-#endif
-
-/** Will reduce some registers for single use.
- */
-static iCode *
-packRegsForOneuse (iCode * ic, operand * op, eBBlock * ebp)
-{
-  bitVect *uses;
-  iCode *dic, *sic;
-
-  // PENDING: Disable
-  D (D_ALLOC, ("packRegsForOneUse: running on ic %p\n", ic));
-
-  /* if returning a literal then do nothing */
-  if (!IS_SYMOP (op))
-    return NULL;
-
-  /* only upto 2 bytes since we cannot predict
-     the usage of b, & acc */
-  if (getSize (operandType (op)) > 2)
-    return NULL;
-
-  if (ic->op != RETURN && ic->op != SEND)
-    return NULL;
-
-  /* this routine will mark the a symbol as used in one
-     instruction use only && if the defintion is local
-     (ie. within the basic block) && has only one definition &&
-     that definiion is either a return value from a
-     function or does not contain any variables in
-     far space */
-  uses = bitVectCopy (OP_USES (op));
-  bitVectUnSetBit (uses, ic->key);      /* take away this iCode */
-  if (!bitVectIsZero (uses))    /* has other uses */
-    return NULL;
-
-  /* if it has only one defintion */
-  if (bitVectnBitsOn (OP_DEFS (op)) > 1)
-    return NULL;                /* has more than one definition */
-
-  /* get that definition */
-  if (!(dic = hTabItemWithKey (iCodehTab, bitVectFirstBit (OP_DEFS (op)))))
-    return NULL;
-
-  /* found the definition now check if it is local */
-  if (dic->seq < ebp->fSeq || dic->seq > ebp->lSeq)
-    return NULL;                /* non-local */
-
-  /* now check if it is the return from a function call */
-  if (dic->op == CALL || dic->op == PCALL)
-    {
-      if (ic->op != SEND && ic->op != RETURN && !POINTER_SET (ic) && !POINTER_GET (ic))
-        {
-          OP_SYMBOL (op)->ruonly = 1;
-          return dic;
-        }
-      dic = dic->next;
-    }
-
-  /* otherwise check that the definition does
-     not contain any symbols in far space */
-  if (isOperandInFarSpace (IC_LEFT (dic)) ||
-      isOperandInFarSpace (IC_RIGHT (dic)) || IS_OP_RUONLY (IC_LEFT (ic)) || IS_OP_RUONLY (IC_RIGHT (ic)))
-    {
-      return NULL;
-    }
-
-  /* if pointer set then make sure the pointer is one byte */
-  if (POINTER_SET (dic))
-    return NULL;
-
-  if (POINTER_GET (dic))
-    return NULL;
-
-  sic = dic;
-
-  /* also make sure the intervenening instructions
-     don't have any thing in far space */
-  for (dic = dic->next; dic && dic != ic; dic = dic->next)
-    {
-      /* if there is an intervening function call then no */
-      if (dic->op == CALL || dic->op == PCALL)
-        return NULL;
-      /* if pointer set then make sure the pointer
-         is one byte */
-      if (POINTER_SET (dic))
-        return NULL;
-
-      if (POINTER_GET (dic))
-        return NULL;
-
-      /* if address of & the result is remat the okay */
-      if (dic->op == ADDRESS_OF && OP_SYMBOL (IC_RESULT (dic))->remat)
-        continue;
-
-      /* if left or right or result is in far space */
-      if (isOperandInFarSpace (IC_LEFT (dic)) ||
-          isOperandInFarSpace (IC_RIGHT (dic)) ||
-          isOperandInFarSpace (IC_RESULT (dic)) ||
-          IS_OP_RUONLY (IC_LEFT (dic)) || IS_OP_RUONLY (IC_RIGHT (dic)) || IS_OP_RUONLY (IC_RESULT (dic)))
-        {
-          return NULL;
-        }
-    }
-
-  /* Fixes #2646174, but there might be a better way */
-  if (ic->op == SEND)
-    return NULL;
-
-  /* Fixes #2982135, but there might be a better way */
-  if (ic->op == RETURN)
-    return NULL;
-
-  OP_SYMBOL (op)->ruonly = 1;
-  return sic;
-}
-
-/*-----------------------------------------------------------------*/
-/* isBitwiseOptimizable - requirements of JEAN LOUIS VERN          */
-/*-----------------------------------------------------------------*/
-static bool
-isBitwiseOptimizable (iCode * ic)
-{
-  sym_link *rtype = getSpec (operandType (IC_RIGHT (ic)));
-
-  /* bitwise operations are considered optimizable
-     under the following conditions (Jean-Louis VERN)
-
-     x & lit
-     bit & bit
-     bit & x
-     bit ^ bit
-     bit ^ x
-     x   ^ lit
-     x   | lit
-     bit | bit
-     bit | x
-   */
-  if (IS_LITERAL (rtype))
-    return TRUE;
-  return FALSE;
-}
-
-static iCode *
-packRegsForHLUse3 (iCode * lic, operand * op, eBBlock * ebp)
-{
-  int i, key;
-  symbol *sym;
-  iCode *ic, *dic;
-  bool isFirst = TRUE;
-  bool exstk = (currFunc && currFunc->stack > 127);
-
-  D (D_PACK_HLUSE3,
-     ("Checking HL on %p lic key %u first def %u line %u:\n", OP_SYMBOL (op), lic->key, bitVectFirstBit (OP_DEFS (op)),
-      lic->lineno));
-  if (D_PACK_HLUSE3)
-    piCode (lic, NULL);
-
-  if (OP_SYMBOL (op)->accuse)
-    {
-      return NULL;
-    }
-
-  if (OP_SYMBOL (op)->remat)
-    {
-      return NULL;
-    }
-
-  /* Only defined once */
-  if (bitVectnBitsOn (OP_DEFS (op)) > 1)
-    return NULL;
-
-  if (!options.oldralloc ? getSize (operandType (op)) != 2 : getSize (operandType (op)) > 2)
-    return NULL;
-
-  /* And this is the definition */
-  if (bitVectFirstBit (OP_DEFS (op)) != lic->key)
-    return NULL;
-
-  /* first check if any overlapping liverange has already been
-     assigned to DPTR */
-  if (OP_SYMBOL (op)->clashes)
-    {
-      for (i = 0; i < OP_SYMBOL (op)->clashes->size; i++)
-        {
-          if (bitVectBitValue (OP_SYMBOL (op)->clashes, i))
-            {
-              sym = hTabItemWithKey (liveRanges, i);
-              if (sym->accuse == ACCUSE_SCRATCH)
-                {
-                  return NULL;
-                }
-            }
-        }
-    }
-
-  /* Nothing else that clashes with this is using the scratch
-     register.  Scan through all of the intermediate instructions and
-     see if any of them could nuke HL.
-   */
-  dic = ic = hTabFirstItemWK (iCodeSeqhTab, OP_SYMBOL (op)->liveFrom);
-
-  for (; ic && ic->seq <= OP_SYMBOL (op)->liveTo; ic = hTabNextItem (iCodeSeqhTab, &key))
-    {
-      if (D_PACK_HLUSE3)
-        piCode (ic, NULL);
-      D (D_PACK_HLUSE3, ("(On %p: op: %u next: %p)\n", ic, ic->op, ic->next));
-
-      if (isFirst)
-        {
-          isFirst = FALSE;
-          if (ic->op == ADDRESS_OF)
-            continue;
-          if (POINTER_GET (ic))
-            continue;
-          if (ic->op == '=' && !POINTER_SET (ic))
-            continue;
-        }
-
-      if (IC_RESULT (ic) && IS_SYMOP (IC_RESULT (ic)) && (isOperandInDirSpace (IC_RESULT (ic)) || exstk))
-        return NULL;
-
-      if (IC_LEFT (ic) && IS_SYMOP (IC_LEFT (ic)) && isOperandInDirSpace (IC_LEFT (ic)))
-        return NULL;
-
-      if (IC_RIGHT (ic) && IS_SYMOP (IC_RIGHT (ic)) && isOperandInDirSpace (IC_RIGHT (ic)))
-        return NULL;
-
-      /* Handle the non left/right/result ones first */
-      if (ic->op == IFX)
-        continue;
-      if (ic->op == JUMPTABLE)
-        return NULL;
-
-      if (SKIP_IC2 (ic))
-        continue;
-
-      if (ic->op == CAST)
-        continue;
-
-      if (ic->op == IPUSH && isOperandEqual (op, IC_LEFT (ic)))
-        continue;
-
-      if (ic->op == SEND && isOperandEqual (op, IC_LEFT (ic)))
-        continue;
-
-      if (ic->op == CALL && isOperandEqual (op, IC_RESULT (ic)))
-        continue;
-
-      if (ic->op == LEFT_OP && isOperandLiteral (IC_RIGHT (ic)))
-        continue;
-
-      if (ic->op == '+' && (isOperandEqual (op, IC_LEFT (ic)) || isOperandEqual (op, IC_RIGHT (ic))))
-        continue;
-
-      if ((ic->op == '=' && !POINTER_SET (ic)) ||
-          ic->op == UNARYMINUS ||
-          ic->op == RETURN ||
-          ic->op == RIGHT_OP ||
-          (ic->op == '-'  && getSize (operandType (IC_RESULT (ic))) == 1) ||
-          ic->op == BITWISEAND ||
-          ic->op == '|' ||
-          ic->op == '>' || ic->op == '<' || ic->op == EQ_OP || (ic->op == '+' && getSize (operandType (IC_RESULT (ic))) == 1))
-        /* 16 bit addition uses add hl, rr */
-        continue;
-
-      if (ic->op == '*' && isOperandEqual (op, IC_LEFT (ic)))
-        continue;
-
-      if (POINTER_SET (ic) && isOperandEqual (op, IC_RESULT (ic)))
-        continue;
-
-      if (POINTER_GET (ic) && isOperandEqual (op, IC_LEFT (ic)))
-        continue;
-
-      if (IS_VALOP (IC_RIGHT (ic)) && (ic->op == EQ_OP || 0))
-        {
-          continue;
-        }
-
-      /* By default give up */
-      D (D_PACK_HLUSE3, ("packRegsForHLUse3 giving up at icode %u\n", (unsigned) (ic->op)));
-      return NULL;
-    }
-
-  D (D_PACK_HLUSE3, ("Succeeded!\n")) OP_SYMBOL (op)->accuse = ACCUSE_SCRATCH;
-  return dic;
-}
-
-static iCode *
-packRegsForIYUse (iCode * lic, operand * op, eBBlock * ebp)
-{
-  int i, key;
-  symbol *sym;
-  iCode *ic, *dic;
-  bitVect *uses;
-
-  D (D_PACK_IY,
-     ("Checking IY on %p lic key %u first def %u line %u:\n", OP_SYMBOL (op), lic->key, bitVectFirstBit (OP_DEFS (op)),
-      lic->lineno));
-  if (D_PACK_IY)
-    piCode (lic, NULL);
-
-  if (OP_SYMBOL (op)->accuse)
-    {
-      return NULL;
-    }
-
-  if (OP_SYMBOL (op)->remat)
-    {
-      return NULL;
-    }
-
-  /* Only defined once */
-  if (bitVectnBitsOn (OP_DEFS (op)) > 1)
-    return NULL;
-
-  /* And this is the definition */
-  if (bitVectFirstBit (OP_DEFS (op)) != lic->key)
-    return NULL;
-
-  /* first check if any overlapping liverange has already been
-     assigned to DPTR */
-  if (OP_SYMBOL (op)->clashes)
-    {
-      for (i = 0; i < OP_SYMBOL (op)->clashes->size; i++)
-        {
-          if (bitVectBitValue (OP_SYMBOL (op)->clashes, i))
-            {
-              sym = hTabItemWithKey (liveRanges, i);
-              if (sym->accuse == ACCUSE_IY)
-                {
-                  return NULL;
-                }
-            }
-        }
-    }
-
-  /* Only a few instructions can load into IY */
-  if (lic->op != '=')
-    {
-      return NULL;
-    }
-
-  if (getSize (operandType (op)) != 2)
-    {
-      D (D_PACK_IY, ("  + Dropping as operation has size is too big\n"));
-      return FALSE;
-    }
-
-  /* Nothing else that clashes with this is using the scratch
-     register.  Scan through all of the intermediate instructions and
-     see if any of them could nuke HL.
-   */
-  dic = ic = hTabFirstItemWK (iCodeSeqhTab, OP_SYMBOL (op)->liveFrom);
-  uses = OP_USES (op);
-
-  for (; ic && ic->seq <= OP_SYMBOL (op)->liveTo; ic = hTabNextItem (iCodeSeqhTab, &key))
-    {
-      if (D_PACK_IY)
-        piCode (ic, NULL);
-
-      if (ic->op == PCALL || ic->op == CALL || ic->op == JUMPTABLE)
-        return NULL;
-
-      if (SKIP_IC2 (ic))
-        continue;
-
-      /* Be pessamistic. */
-      if (ic->op == IFX)
-        return NULL;
-
-      D (D_PACK_IY, ("  op: %u uses %u result: %d left: %d right: %d\n", ic->op, bitVectBitValue (uses, ic->key),
-                     IC_RESULT (ic) && IS_SYMOP (IC_RESULT (ic)) ? isOperandInDirSpace (IC_RESULT (ic)) : -1,
-                     IC_LEFT (ic) && IS_SYMOP (IC_LEFT (ic)) ? isOperandInDirSpace (IC_LEFT (ic)) : -1,
-                     IC_RIGHT (ic) && IS_SYMOP (IC_RIGHT (ic)) ? isOperandInDirSpace (IC_RIGHT (ic)) : -1));
-
-      if (IC_RESULT (ic) && IS_SYMOP (IC_RESULT (ic)) && isOperandInDirSpace (IC_RESULT (ic)))
-        return NULL;
-
-      if (IC_RIGHT (ic) && IS_SYMOP (IC_RIGHT (ic)) && isOperandInDirSpace (IC_RIGHT (ic)))
-        return NULL;
-
-      if (IC_LEFT (ic) && IS_SYMOP (IC_LEFT (ic)) && isOperandInDirSpace (IC_LEFT (ic)))
-        return NULL;
-
-      /* Only certain rules will work against IY.  Check if this iCode uses
-         this symbol. */
-      if (bitVectBitValue (uses, ic->key) != 0)
-        {
-          if (ic->op == '=' && isOperandEqual (IC_RESULT (ic), op))
-            continue;
-
-          if (ic->op == GET_VALUE_AT_ADDRESS && isOperandEqual (IC_LEFT (ic), op))
-            continue;
-
-          if (isOperandEqual (IC_RESULT (ic), IC_LEFT (ic)) == FALSE)
-            return NULL;
-
-          if (IC_RIGHT (ic) && IS_VALOP (IC_RIGHT (ic)))
-            {
-              if (ic->op == '+' || ic->op == '-')
-                {
-                  /* Only works if the constant is small */
-                  if (operandLitValue (IC_RIGHT (ic)) < 4)
-                    continue;
-                }
-            }
-
-          return NULL;
-        }
-      else
-        {
-          /* This iCode doesn't use the sym.  See if this iCode preserves IY.
-           */
-          continue;
-        }
+    {
+      iCode *sic = dic->next;
 
-      /* By default give up */
-      return NULL;
+      for (; sic != ic; sic = sic->next)
+        if (IC_RESULT (sic) && IC_RESULT (sic)->key == IC_RIGHT (dic)->key)
+          return NULL;
     }
 
-  D (D_PACK_IY, ("Succeeded IY!\n"));
-
-  OP_SYMBOL (op)->accuse = ACCUSE_IY;
   return dic;
+
+
 }
 
-/** Returns TRUE if this operation can use acc and if it preserves the value.
+/** Will reduce some registers for single use.
  */
-static bool
-opPreservesA (iCode * uic)
+static iCode *
+packRegsForOneuse (iCode * ic, operand * op, eBBlock * ebp)
 {
-  if (uic->op == IFX)
-    {
-      /* If we've gotten this far then the thing to compare must be
-         small enough and must be in A.
-       */
-      return TRUE;
-    }
+  bitVect *uses;
+  iCode *dic, *sic;
 
-  if (uic->op == JUMPTABLE)
-    {
-      D (D_ACCUSE2, ("  + Dropping as operation is a Jumptable\n"));
-      return FALSE;
-    }
+  // PENDING: Disable
+  D (D_ALLOC, ("packRegsForOneUse: running on ic %p\n", ic));
 
-  /* A pointer assign preserves A if A is the left value. */
-  if (uic->op == '=' && POINTER_SET (uic) && !IY_RESERVED)
-    {
-      return TRUE;
-    }
+  /* if returning a literal then do nothing */
+  if (!IS_SYMOP (op))
+    return NULL;
 
-  /* if the usage has only one operand then we can */
-  /* PENDING: check */
-  if (IC_LEFT (uic) == NULL || IC_RIGHT (uic) == NULL)
-    {
-      D (D_ACCUSE2, ("  + Dropping as operation has only one operand\n"));
-      return FALSE;
-    }
+  /* only upto 2 bytes since we cannot predict
+     the usage of b, & acc */
+  if (getSize (operandType (op)) > 2)
+    return NULL;
 
-  /* PENDING: check this rule */
-  if (getSize (operandType (IC_RESULT (uic))) > 1)
-    {
-      D (D_ACCUSE2, ("  + Dropping as operation has size is too big\n"));
-      return FALSE;
-    }
+  if (ic->op != RETURN && ic->op != SEND)
+    return NULL;
 
-  return FALSE;
-}
+  /* this routine will mark the a symbol as used in one
+     instruction use only && if the definition is local
+     (ie. within the basic block) && has only one definition &&
+     that definition is either a return value from a
+     function or does not contain any variables in
+     far space */
+  uses = bitVectCopy (OP_USES (op));
+  bitVectUnSetBit (uses, ic->key);      /* take away this iCode */
+  if (!bitVectIsZero (uses))    /* has other uses */
+    return NULL;
 
-/* Return TRUE if this operation can use A (it doesn't have to keep A unchanged) */
-static bool
-opCanUseA (iCode * uic)
-{
-  if (uic->op == IFX)
-    {
-      /* If we've gotten this far then the thing to compare must be
-         small enough and must be in A.
-       */
-      return TRUE;
-    }
-  if (uic->op == JUMPTABLE)
-    {
-      D (D_ACCUSE2, ("  + Dropping as operation is a Jumptable\n"));
-      return FALSE;
-    }
+  /* if it has only one definition */
+  if (bitVectnBitsOn (OP_DEFS (op)) > 1)
+    return NULL;                /* has more than one definition */
 
-  if (uic->op == '=' && !(IY_RESERVED && POINTER_SET (uic)))
-    {
-      return TRUE;
-    }
+  /* get that definition */
+  if (!(dic = hTabItemWithKey (iCodehTab, bitVectFirstBit (OP_DEFS (op)))))
+    return NULL;
 
-  if ((uic->op == RIGHT_OP || uic->op == LEFT_OP) && IS_OP_LITERAL (IC_RIGHT (uic)))
-    {
-      return TRUE;
-    }
+  /* found the definition now check if it is local */
+  if (dic->seq < ebp->fSeq || dic->seq > ebp->lSeq)
+    return NULL;                /* non-local */
 
-  /* Somehow fails for unary minus. */
-  if (IC_LEFT (uic) == NULL || IC_RIGHT (uic) == NULL)
+  /* now check if it is the return from a function call */
+  if (dic->op == CALL || dic->op == PCALL)
     {
-      D (D_ACCUSE2, ("  + Dropping as operation has only one operand\n"));
-      return FALSE;
+      if (ic->op != SEND && ic->op != RETURN && !POINTER_SET (ic) && !POINTER_GET (ic))
+        {
+          OP_SYMBOL (op)->ruonly = 1;
+          return dic;
+        }
+      dic = dic->next;
     }
 
-  if (IS_BITWISE_OP (uic))
+  /* otherwise check that the definition does
+     not contain any symbols in far space */
+  if (isOperandInFarSpace (IC_LEFT (dic)) ||
+      isOperandInFarSpace (IC_RIGHT (dic)) || IS_OP_RUONLY (IC_LEFT (ic)) || IS_OP_RUONLY (IC_RIGHT (ic)))
     {
-      return TRUE;
+      return NULL;
     }
 
-  return FALSE;
-}
+  /* if pointer set then make sure the pointer is one byte */
+  if (POINTER_SET (dic))
+    return NULL;
 
-/** Returns true if this operand preserves the value of A.
- */
-static bool
-opIgnoresA (iCode * ic, iCode * uic)
-{
-  /* A increment of an iTemp by a constant is OK. */
-  if (uic->op == '+' && IS_ITEMP (IC_LEFT (uic)) && IS_ITEMP (IC_RESULT (uic)) && IS_OP_LITERAL (IC_RIGHT (uic)))
-    {
-      unsigned int icount = (unsigned int) ulFromVal (OP_VALUE (IC_RIGHT (uic)));
+  if (POINTER_GET (dic))
+    return NULL;
 
-      /* Being an ITEMP means that we're already a symbol. */
-      if (icount == 1 && OP_KEY (IC_RESULT (uic)) == OP_KEY (IC_LEFT (uic)))
-        {
-          return TRUE;
-        }
-    }
-  else if (uic->op == '=' && !POINTER_SET (uic))
-    {
-      /* If they are equal and get optimised out then things are OK. */
-      if (isOperandEqual (IC_RESULT (uic), IC_RIGHT (uic)))
-        {
-          /* Straight assign is OK. */
-          return TRUE;
-        }
-    }
+  sic = dic;
 
-  return FALSE;
-}
+  /* also make sure the intervenening instructions
+     don't have any thing in far space */
+  for (dic = dic->next; dic && dic != ic; dic = dic->next)
+    {
+      /* if there is an intervening function call then no */
+      if (dic->op == CALL || dic->op == PCALL)
+        return NULL;
+      /* if pointer set then make sure the pointer
+         is one byte */
+      if (POINTER_SET (dic))
+        return NULL;
 
-/** Pack registers for acc use.
-    When the result of this operation is small and short lived it may
-    be able to be stored in the accumulator.
+      if (POINTER_GET (dic))
+        return NULL;
 
-    Note that the 'A preserving' list is currently emperical :)
- */
-static void
-packRegsForAccUse2 (iCode * ic)
-{
-  iCode *uic;
+      /* if address of & the result is remat the okay */
+      if (dic->op == ADDRESS_OF && OP_SYMBOL (IC_RESULT (dic))->remat)
+        continue;
 
-  D (D_ACCUSE2, ("packRegsForAccUse2: running on ic %p line %u\n", ic, ic->lineno));
-  if (D_ACCUSE2)
-    piCode (ic, NULL);
-
-  /* Filter out all but those 'good' commands */
-  if (!POINTER_GET (ic) &&
-      ic->op != '+' &&
-      ic->op != '-' &&
-      !IS_BITWISE_OP (ic) &&
-      ic->op != '=' &&
-      ic->op != EQ_OP &&
-      ic->op != '<' &&
-      ic->op != '>' &&
-      ic->op != CAST && ic->op != GETHBIT && !((ic->op == LEFT_OP || ic->op == RIGHT_OP) && IS_OP_LITERAL (IC_RIGHT (ic))))
-    {
-      D (D_ACCUSE2, ("  + Dropping as not a 'good' source command\n"));
-      return;
+      /* if left or right or result is in far space */
+      if (isOperandInFarSpace (IC_LEFT (dic)) ||
+          isOperandInFarSpace (IC_RIGHT (dic)) ||
+          isOperandInFarSpace (IC_RESULT (dic)) ||
+          IS_OP_RUONLY (IC_LEFT (dic)) || IS_OP_RUONLY (IC_RIGHT (dic)) || IS_OP_RUONLY (IC_RESULT (dic)))
+        {
+          return NULL;
+        }
     }
 
-  /* if + or - then it has to be one byte result.
-     MLH: Ok.
-   */
-  if ((ic->op == '+' || ic->op == '-' || ic->op == LEFT_OP || ic->op == RIGHT_OP) && getSize (operandType (IC_RESULT (ic))) > 1)
-    {
-      D (D_ACCUSE2, ("  + Dropping as it's a big one\n"));
-      return;
-    }
+  /* Fixes #2646174, but there might be a better way */
+  if (ic->op == SEND)
+    return NULL;
 
-  /* has only one definition */
-  if (bitVectnBitsOn (OP_DEFS (IC_RESULT (ic))) > 1)
-    {
-      D (D_ACCUSE2, ("  + Dropping as it has more than one definition\n"));
-      return;
-    }
+  /* Fixes #2982135, but there might be a better way */
+  if (ic->op == RETURN)
+    return NULL;
 
-  /* Right.  We may be able to propagate it through if:
-     For each in the chain of uses the intermediate is OK.
-   */
-  /* Get next with 'uses result' bit on
-     If this->next == next
-     Validate use of next
-     If OK, increase count
-   */
-  /* and the usage immediately follows this iCode */
-  if (!(uic = hTabItemWithKey (iCodehTab, bitVectFirstBit (OP_USES (IC_RESULT (ic))))))
-    {
-      D (D_ACCUSE2, ("  + Dropping as usage does not follow first\n"));
-      return;
-    }
+  OP_SYMBOL (op)->ruonly = 1;
+  return sic;
+}
 
-  {
-    /* Create a copy of the OP_USES bit vect */
-    bitVect *uses = bitVectCopy (OP_USES (IC_RESULT (ic)));
-    int setBit;
-    iCode *scan = ic, *next;
+/*-----------------------------------------------------------------*/
+/* isBitwiseOptimizable - requirements of JEAN LOUIS VERN          */
+/*-----------------------------------------------------------------*/
+static bool
+isBitwiseOptimizable (iCode * ic)
+{
+  sym_link *rtype = getSpec (operandType (IC_RIGHT (ic)));
 
-    do
-      {
-        setBit = bitVectFirstBit (uses);
-        next = hTabItemWithKey (iCodehTab, setBit);
-        if (scan->next == next)
-          {
-            D (D_ACCUSE2_VERBOSE, ("  ! Is next in line\n"));
-
-            bitVectUnSetBit (uses, setBit);
-
-            if (bitVectIsZero (uses) && opCanUseA (next))
-              {
-                D (D_ACCUSE2, ("  Arrived at last op safely.\n"));
-                break;
-              }
-            /* Still contigous. */
-            if (!opPreservesA (next))
-              {
-                D (D_ACCUSE2, ("  + Dropping as operation doesn't preserve A\n"));
-                return;
-              }
-            D (D_ACCUSE2_VERBOSE, ("  ! Preserves A, so continue scanning\n"));
-            scan = next;
-          }
-        /*else if (scan->next == NULL && bitVectnBitsOn (uses) == 1 && next != NULL)
-           {
-           if (next->prev == NULL)
-           {
-           if (!opPreservesA (next))
-           {
-           D (D_ACCUSE2, ("  + Dropping as operation doesn't preserve A #2\n"));
-           return;
-           }
-           bitVectUnSetBit (uses, setBit);
-           scan = next;
-           }
-           else
-           {
-           D (D_ACCUSE2, ("  + Dropping as last in list and next doesn't start a block\n"));
-           return;
-           }
-           } //This caused bug #1292721 */
-        else if (scan->next == NULL)
-          {
-            D (D_ACCUSE2, ("  + Dropping as hit the end of the list\n"));
-            D (D_ACCUSE2, ("  + Next in htab: %p\n", next));
-            return;
-          }
-        else
-          {
-            if (opIgnoresA (ic, scan->next))
-              {
-                /* Safe for now. */
-                scan = scan->next;
-                D (D_ACCUSE2_VERBOSE, ("  ! Op ignores A, so continue scanning\n"));
-              }
-            else
-              {
-                D (D_ACCUSE2, ("  + Dropping as parts are not consecuitive and intermediate might use A\n"));
-                return;
-              }
-          }
-      }
-    while (!bitVectIsZero (uses));
+  /* bitwise operations are considered optimizable
+     under the following conditions (Jean-Louis VERN)
 
-    OP_SYMBOL (IC_RESULT (ic))->accuse = ACCUSE_A;
-    return;
-  }
+     x & lit
+     bit & bit
+     bit & x
+     bit ^ bit
+     bit ^ x
+     x   ^ lit
+     x   | lit
+     bit | bit
+     bit | x
+   */
+  if (IS_LITERAL (rtype))
+    return TRUE;
+  return FALSE;
 }
 
 /** Does some transformations to reduce register pressure.
@@ -2702,8 +1011,8 @@
       /* if this is an itemp & result of a address of a true sym
          then mark this as rematerialisable   */
       if (ic->op == ADDRESS_OF &&
-          IS_ITEMP (IC_RESULT (ic)) && bitVectnBitsOn (OP_DEFS (IC_RESULT (ic))) == 1 && !IS_PARM (IC_RESULT (ic)) /* The receiving of the paramter isnot accounted for in DEFS */ &&
-          IS_TRUE_SYMOP (IC_LEFT (ic)) && !OP_SYMBOL (IC_LEFT (ic))->onStack)
+          IS_ITEMP (IC_RESULT (ic)) && bitVectnBitsOn (OP_DEFS (IC_RESULT (ic))) == 1 && !IS_PARM (IC_RESULT (ic)) /* The receiving of the parameter is not accounted for in DEFS */ &&
+          IS_TRUE_SYMOP (IC_LEFT (ic)))
         {
           OP_SYMBOL (IC_RESULT (ic))->remat = 1;
           OP_SYMBOL (IC_RESULT (ic))->rematiCode = ic;
@@ -2714,7 +1023,7 @@
       /* if straight assignment then carry remat flag if this is the
          only definition */
       if (ic->op == '=' && !POINTER_SET (ic) && IS_SYMOP (IC_RIGHT (ic)) && OP_SYMBOL (IC_RIGHT (ic))->remat &&
-        !isOperandGlobal (IC_RESULT (ic)) && bitVectnBitsOn (OP_SYMBOL (IC_RESULT (ic))->defs) == 1 && !IS_PARM (IC_RESULT (ic)) && /* The receiving of the paramter isnot accounted for in DEFS */
+        !isOperandGlobal (IC_RESULT (ic)) && bitVectnBitsOn (OP_SYMBOL (IC_RESULT (ic))->defs) == 1 && !IS_PARM (IC_RESULT (ic)) && /* The receiving of the parameter is not accounted for in DEFS */
         !OP_SYMBOL (IC_RESULT (ic))->addrtaken)
         {
           OP_SYMBOL (IC_RESULT (ic))->remat = OP_SYMBOL (IC_RIGHT (ic))->remat;
@@ -2725,7 +1034,7 @@
          cast is remat, then we can remat this cast as well */
       if (ic->op == CAST &&
           IS_SYMOP (IC_RIGHT (ic)) && OP_SYMBOL (IC_RIGHT (ic))->remat &&
-          !isOperandGlobal (IC_RESULT (ic)) && bitVectnBitsOn (OP_DEFS (IC_RESULT (ic))) == 1 && !IS_PARM (IC_RESULT (ic)) && /* The receiving of the paramter isnot accounted for in DEFS */
+          !isOperandGlobal (IC_RESULT (ic)) && bitVectnBitsOn (OP_DEFS (IC_RESULT (ic))) == 1 && !IS_PARM (IC_RESULT (ic)) && /* The receiving of the parameter is not accounted for in DEFS */
           !OP_SYMBOL (IC_RESULT (ic))->addrtaken)
         {
           sym_link *to_type = operandType (IC_LEFT (ic));
@@ -2796,24 +1105,6 @@
         {
           packRegsForOneuse (ic, IC_LEFT (ic), ebp);
         }
-
-      /* pack registers for accumulator use, when the result of an
-         arithmetic or bit wise operation has only one use, that use is
-         immediately following the defintion and the using iCode has
-         only one operand or has two operands but one is literal & the
-         result of that operation is not on stack then we can leave the
-         result of this operation in acc:b combination */
-
-      if ((options.oldralloc || !OPTRALLOC_HL) && !DISABLE_PACK_HL && IS_ITEMP (IC_RESULT (ic)))
-        if (!IS_GB && !IY_RESERVED)
-          packRegsForHLUse3 (ic, IC_RESULT (ic), ebp);
-
-      if ((options.oldralloc || !OPTRALLOC_IY) && !DISABLE_PACK_IY && !IY_RESERVED && IS_ITEMP (IC_RESULT (ic)) && !IS_GB)
-        packRegsForIYUse (ic, IC_RESULT (ic), ebp);
-
-      if (options.oldralloc && !DISABLE_PACK_ACC && IS_ITEMP (IC_RESULT (ic)) &&
-          getSize (operandType (IC_RESULT (ic))) == 1)
-        packRegsForAccUse2 (ic);
     }
 }
 
@@ -2971,7 +1262,7 @@
                   sym->isspilt = false;
                 }
 
-              if (sym->nRegs > 4) /* TODO. Change this once we can allocate bigger variables (but still spill when its a big return value). */
+              if (sym->nRegs > 4) /* TODO. Change this once we can allocate bigger variables (but still spill when its a big return value). Also change in ralloc2.cc, operand_on-stack in that case*/
                 {
                   D (D_ALLOC, ("Spilling %s (too large)\n", sym->name));
                   sym->for_newralloc = 0;
@@ -3031,111 +1322,8 @@
     }
 }
 
-void z80_init_asmops (void);
-
-#ifdef OLDRALLOC
-/*-----------------------------------------------------------------*/
-/* Old, obsolete register allocator                                */
-/*-----------------------------------------------------------------*/
-void
-z80_oldralloc (ebbIndex * ebbi)
-{
-  eBBlock **ebbs = ebbi->bbOrder;
-  int count = ebbi->count;
-  iCode *ic;
-  int i;
-
-  D (D_ALLOC, ("\n-> z80_oldralloc: entered for %s.\n", currFunc ? currFunc->name : "[no function]"));
-
-  setToNull ((void *) &_G.funcrUsed);
-  setToNull ((void *) &_G.totRegAssigned);
-  _G.stackExtend = _G.dataExtend = 0;
-
-  if (IS_GB)
-    {
-      /* DE is required for the code gen. */
-      _G.nRegs = 3;
-      regsZ80 = _gbz80_regs;
-    }
-  else
-    {
-      _G.nRegs = 5;
-      regsZ80 = _z80_regs;
-    }
-    
-  z80_init_asmops ();
-
-  /* change assignments this will remove some
-     live ranges reducing some register pressure */
-  for (i = 0; i < count; i++)
-    packRegisters (ebbs[i]);
-
-  /* liveranges probably changed by register packing
-     so we compute them again */
-  recomputeLiveRanges (ebbs, count, FALSE);
-
-  if (options.dump_i_code)
-    dumpEbbsToFileExt (DUMP_PACK, ebbi);
-
-  /* first determine for each live range the number of
-     registers & the type of registers required for each */
-  regTypeNum ();
-
-  /* and serially allocate registers */
-  serialRegAssign (ebbs, count);
-
-  freeAllRegs ();
-  fillGaps ();
-
-  /* if stack was extended then tell the user */
-  if (_G.stackExtend)
-    {
-/*      werror(W_TOOMANY_SPILS,"stack", */
-/*             _G.stackExtend,currFunc->name,""); */
-      _G.stackExtend = 0;
-    }
-
-  if (_G.dataExtend)
-    {
-/*      werror(W_TOOMANY_SPILS,"data space", */
-/*             _G.dataExtend,currFunc->name,""); */
-      _G.dataExtend = 0;
-    }
-
-  if (options.dump_i_code)
-    {
-      dumpEbbsToFileExt (DUMP_RASSGN, ebbi);
-      dumpLiveRanges (DUMP_LRANGE, liveRanges);
-    }
-
-  /* after that create the register mask
-     for each of the instruction */
-  createRegMask (ebbs, count);
-
-  /* now get back the chain */
-  ic = iCodeLabelOptimize (iCodeFromeBBlock (ebbs, count));
-
-  ic = joinPushes (ic);
-
-  /* redo that offsets for stacked automatic variables */
-  redoStackOffsets ();
-
-  genZ80Code (ic);
-
-  /* free up any stackSpil locations allocated */
-  applyToSet (_G.stackSpil, deallocStackSpil);
-  _G.slocNum = 0;
-  setToNull ((void *) &_G.stackSpil);
-  setToNull ((void *) &_G.spiltSet);
-  /* mark all registers as free */
-  freeAllRegs ();
-
-  return;
-}
-#endif
-
 /*-----------------------------------------------------------------*/
-/* New register allocator                                          */
+/* Register allocator                                          */
 /*-----------------------------------------------------------------*/
 void
 z80_ralloc (ebbIndex *ebbi)
@@ -3151,19 +1339,7 @@
   setToNull ((void *) &_G.totRegAssigned);
   _G.stackExtend = _G.dataExtend = 0;
 
-  if (IS_GB)
-    {
-      /* DE is required for the code gen. */
-      _G.nRegs = GBZ80_MAX_REGS;
-      regsZ80 = _gbz80_regs;
-    }
-  else
-    {
-      _G.nRegs = Z80_MAX_REGS;
-      regsZ80 = _z80_regs;
-    }
-
-  z80_init_asmops ();
+  _G.nRegs = IS_SM83 ? SM83_MAX_REGS : Z80_MAX_REGS;
 
   /* change assignments this will remove some
      live ranges reducing some register pressure */
@@ -3214,11 +1390,6 @@
 void
 z80_assignRegisters (ebbIndex * ebbi)
 {
-#ifdef OLDRALLOC
-  if (options.oldralloc)
-    z80_oldralloc (ebbi);
-  else
-#endif
-    z80_ralloc (ebbi);
+  z80_ralloc (ebbi);
 }
 
diff -Nru sdcc-4.0.0+dfsg/src/z80/z80.h sdcc-4.2.0+dfsg/src/z80/z80.h
--- sdcc-4.0.0+dfsg/src/z80/z80.h	2018-12-11 09:14:02.000000000 +0000
+++ sdcc-4.2.0+dfsg/src/z80/z80.h	2021-12-10 14:48:15.000000000 +0000
@@ -1,5 +1,5 @@
 /** @file z80/z80.h
-    Common definitions between the z80 and gbz80 parts.
+    Common definitions for the the z80-related ports.
 */
 #include "common.h"
 #include "ralloc.h"
@@ -12,10 +12,12 @@
     SUB_Z80,
     SUB_Z180,
     SUB_R2K,
+    SUB_R2KA,
     SUB_R3KA,
-    SUB_GBZ80,
+    SUB_SM83,
     SUB_TLCS90,
-    SUB_EZ80_Z80
+    SUB_EZ80_Z80,
+    SUB_Z80N
   }
 Z80_SUB_PORT;
 
@@ -27,6 +29,8 @@
     int port_back;
     int reserveIY;
     int noOmitFramePtr;
+    int legacyBanking;
+    int nmosZ80;
   }
 Z80_OPTS;
 
@@ -35,16 +39,17 @@
 #define IS_Z80 (z80_opts.sub == SUB_Z80)
 #define IS_Z180 (z80_opts.sub == SUB_Z180)
 #define IS_R2K (z80_opts.sub == SUB_R2K)
+#define IS_R2KA (z80_opts.sub == SUB_R2KA)
 #define IS_R3KA (z80_opts.sub == SUB_R3KA)
-#define IS_RAB (IS_R2K || IS_R3KA)
-#define IS_GB (z80_opts.sub == SUB_GBZ80)
+#define IS_RAB (IS_R2K || IS_R2KA || IS_R3KA)
+#define IS_SM83 (z80_opts.sub == SUB_SM83)
 #define IS_TLCS90 (z80_opts.sub == SUB_TLCS90)
 #define IS_EZ80_Z80 (z80_opts.sub == SUB_EZ80_Z80)
+#define IS_Z80N (z80_opts.sub == SUB_Z80N)
 
 #define IY_RESERVED (z80_opts.reserveIY)
 
-#define OPTRALLOC_HL (!IS_GB)
-#define OPTRALLOC_IY !(IY_RESERVED || IS_GB)
+#define OPTRALLOC_IY !(IY_RESERVED || IS_SM83)
 
 enum
   {
diff -Nru sdcc-4.0.0+dfsg/support/makebin/makebin.c sdcc-4.2.0+dfsg/support/makebin/makebin.c
--- sdcc-4.0.0+dfsg/support/makebin/makebin.c	2017-11-07 10:14:35.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/makebin/makebin.c	2022-02-04 00:56:16.000000000 +0000
@@ -4,6 +4,8 @@
   Copyright (c) 2000 Michael Hope
   Copyright (c) 2010 Borut Razem
   Copyright (c) 2012 Noel Lemouel
+  Copyright (c) 2020-2021 Sebastian 'basxto' Riedel
+  Copyright (c) 2020 'bbbbbr'
 
   This software is provided 'as-is', without any express or implied
   warranty.  In no event will the authors be held liable for any damages
@@ -25,6 +27,7 @@
 
 #include 
 #include 
+#include 
 #include 
 #include 
 
@@ -87,14 +90,36 @@
            "Usage: makebin [options] [ []]\n"
            "Options:\n"
            "  -p             pack mode: the binary file size will be truncated to the last occupied byte\n"
-           "  -s romsize     size of the binary file (default: 32768)\n"
-           "  -Z             genarate GameBoy format binary file\n"
+           "  -s romsize     size of the binary file (default: rom banks * 16384)\n"
+           "  -Z             generate GameBoy format binary file\n"
+           "  -S             generate Sega Master System format binary file\n"
+           "  -o bytes       skip amount of bytes in binary file\n"
+
+           "SMS format options (applicable only with -S option):\n"
+           "  -xo n          rom size (0xa-0x2) (default: 0xc)\n"
+           "  -xj n          set region code (3-7) (default: 4)\n"
+           //"  -xc n          product code (0-159999)\n"
+           "  -xv n          version number (0-15) (default: 0)\n"
+           //"  -xV n          SDSC version number\n"
+           //"  -xd n          SDSC date\n"
+           //"  -xA n          SDSC author pointer\n"
+           //"  -xn n          SDSC program name pointer\n"
+           //"  -xD n          SDSC description pointer\n"
+
            "GameBoy format options (applicable only with -Z option):\n"
-           "  -yo n          number of rom banks (default: 2)\n"
+           "  -yo n          number of rom banks (default: 2) (autosize: A)\n"
            "  -ya n          number of ram banks (default: 0)\n"
            "  -yt n          MBC type (default: no MBC)\n"
+           "  -yl n          old licensee code (default: 0x33)\n"
+           "  -yk cc         new licensee string (default: 00)\n"
            "  -yn name       cartridge name (default: none)\n"
-           "  -yc            GameBoy Color\n"
+           "  -yc            GameBoy Color compatible\n"
+           "  -yC            GameBoy Color only\n"
+           "  -ys            Super GameBoy\n"
+           "  -yS            Convert .noi file named like input file to .sym\n"
+           "  -yj            set non-Japanese region flag\n"
+           "  -yN            do not copy big N validation logo into ROM header\n"
+           "  -yp addr=value Set address in ROM to given value (address 0x100-0x1FE)\n"
            "Arguments:\n"
            "        optional IHX input file, '-' means stdin. (default: stdin)\n"
            "       optional output file, '-' means stdout. (default: stdout)\n");
@@ -105,10 +130,25 @@
 struct gb_opt_s
 {
   char cart_name[CART_NAME_LEN];  /* cartridge name buffer */
+  char licensee_str[2];           /* new licensee string */
   BYTE mbc_type;                  /* MBC type (default: no MBC) */
   short nb_rom_banks;             /* Number of rom banks (default: 2) */
   BYTE nb_ram_banks;              /* Number of ram banks (default: 0) */
-  BYTE is_gbc;                    /* True if GBC, false for all other*/
+  BYTE licensee_id;               /* old licensee code */
+  BYTE is_gbc;                    /* 1 if GBC compatible, 2 if GBC only, false for all other*/
+  BYTE is_sgb;                    /* True if SGB, false for all other*/
+  BYTE sym_conversion;            /* True if .noi file should be converted to .sym (default false)*/
+  BYTE non_jp;                    /* True if non-Japanese region, false for all other*/
+  BYTE rom_banks_autosize;        /* True if rom banks should be auto-sized (default false)*/
+  bool do_logo_copy;              /* True if the nintendo logo should be copied into the ROM (default true) */
+  BYTE address_overwrite[16];     /* For limited compatibility with very old versions */
+};
+
+struct sms_opt_s
+{
+  BYTE rom_size;                  /* Doesn't have to be the real size, needed for checksum */
+  BYTE region_code;               /* Region code Japan/Export/International and SMS/GG */
+  BYTE version;                   /* Game version */
 };
 
 void
@@ -129,7 +169,13 @@
    * If missing, an actual Game Boy won't run the ROM.
    */
 
-  memcpy (&rom[0x104], gb_logo, sizeof (gb_logo));
+  if (o->do_logo_copy)
+    {
+      memcpy (&rom[0x104], gb_logo, sizeof (gb_logo));
+    }
+
+  rom[0x144] = o->licensee_str[0];
+  rom[0x145] = o->licensee_str[1];
 
   /*
    * 0134-0142: Title of the game in UPPER CASE ASCII. If it
@@ -143,11 +189,21 @@
       rom[0x134 + i] = toupper (o->cart_name[i]);
     }
 
-  if (o->is_gbc)
+  if (o->is_gbc == 1)
     {
       rom[0x143] = 0x80;
     }
 
+  if (o->is_gbc == 2)
+    {
+      rom[0x143] = 0xC0;
+    }
+
+  if (o->is_sgb)
+    {
+      rom[0x146] = 0x03;
+    }
+
   /*
    * 0147: Cartridge type:
    * 0-ROM ONLY            12-ROM+MBC3+RAM
@@ -256,6 +312,48 @@
       break;
     }
 
+  rom[0x14A] = o->non_jp;
+
+  rom[0x14B] = o->licensee_id;
+
+  for (i = 0; i < 16; i+=2)
+    {
+      if(o->address_overwrite[i] != 0xFF)
+        {
+          rom[0x0100 | o->address_overwrite[i]] = o->address_overwrite[i+1];
+          // warnings for builds ported from ancient GBDK
+          fprintf (stderr, "caution: -yp0x01%02x=0x%02x is outdated", o->address_overwrite[i], o->address_overwrite[i+1]);
+          if(o->address_overwrite[i] == 0x43)
+            switch(o->address_overwrite[i+1]&0xC0)
+              {
+              case 0x80:
+                fprintf (stderr, ", please use -yc instead");
+                break;
+              case 0xC0:
+                fprintf (stderr, ", please use -yC instead");
+                break;
+              default:
+                o->address_overwrite[i] = 0xFF;
+              }
+          if(o->address_overwrite[i] == 0x44 || o->address_overwrite[i] == 0x45)
+              fprintf (stderr, ", please use -yk cc instead");
+          if(o->address_overwrite[i] == 0x46)
+            if(o->address_overwrite[i+1] == 0x03)
+              fprintf (stderr, ", please use -ys instead");
+            else
+              o->address_overwrite[i] = 0xFF;
+          if(o->address_overwrite[i] == 0x47)
+            fprintf (stderr, ", please use -yt 0x%02x instead", o->address_overwrite[i+1]);
+          if(o->address_overwrite[i] == 0x4A)
+            fprintf (stderr, ", please use -yl 0x%02x instead", o->address_overwrite[i+1]);
+          if(o->address_overwrite[i] == 0x4B && o->address_overwrite[i+1] == 1)
+            fprintf (stderr, ", please use -yj instead");
+          if(o->address_overwrite[i] == 0xFF)
+            fprintf (stderr, ", this setting is the default");
+          fprintf (stderr, ".\n");
+        }
+    }
+
   /* Update complement checksum */
   chk = 0;
   for (i = 0x134; i < 0x14d; ++i)
@@ -275,11 +373,230 @@
     *real_size = 0x150;
 }
 
+void
+sms_postproc (BYTE * rom, int size, int *real_size, struct sms_opt_s *o)
+{
+  // based on https://www.smspower.org/Development/ROMHeader
+  // 0x1ff0 and 0x3ff0 are also possible, but never used
+  static const char tmr_sega[] = "TMR SEGA  ";
+  short header_base = 0x7ff0;
+  int chk = 0;
+  unsigned long i;
+  // choose earlier positions for smaller roms
+  if (header_base > size)
+    header_base = 0x3ff0;
+  if (header_base > size)
+    header_base = 0x1ff0;
+
+  memcpy (&rom[header_base], tmr_sega, sizeof (tmr_sega) - 1);
+  // configure amounts of bytes to check
+  switch(o->rom_size)
+    {
+      case 0xa:
+      default:
+        i = 0x1FEF;
+        break;
+      case 0xb:
+        i = 0x3FEF;
+        break;
+      case 0xc:
+        i = 0x7FEF;
+        break;
+      case 0xd:
+        i = 0xBFEF;
+        break;
+      case 0xe:
+        i = 0xFFFF;
+        break;
+      case 0xf:
+        i = 0x1FFFF;
+        break;
+      case 0x0:
+        i = 0x3FFFF;
+        break;
+      case 0x1:
+        i = 0x7FFFF;
+        break;
+      case 0x2:
+        i = 0xFFFFF;
+        break;
+    }
+  // calculate checksum
+  for(;i > 0; --i)
+    {
+      chk += rom[i];
+      // 0x7FF0 - 0x7FFF is skipped
+      if(i == 0x8000)
+        i = 0x7FF0;
+    }
+  // we  skipped index 0
+  chk += rom[0];
+  // little endian
+  rom[header_base + 0xa] = chk & 0xff;
+  rom[header_base + 0xb] = (chk>>8) & 0xff;
+  // game version
+  rom[header_base + 0xe] &= 0xF0;
+  rom[header_base + 0xe] |= o->version;
+  // rom size
+  rom[header_base + 0xf] = (o->region_code << 4) | o->rom_size;
+}
+
 int
-read_ihx (FILE *fin, BYTE *rom, int size, int *real_size)
+rom_autosize_grow(BYTE **rom, int test_size, int *size, struct gb_opt_s *o)
+{
+  int last_size = *size;
+
+  while ((test_size > *size) && (o->nb_rom_banks <= 512))
+    {
+      o->nb_rom_banks *= 2;
+      // banks work differently for mbc6, they have half the size
+      // but this in general ignored by -yo
+      *size = o->nb_rom_banks * 0x4000;
+    }
+
+  if (o->nb_rom_banks > 512)
+    {
+      fprintf (stderr, "error: auto-size banks exceeded max of 512 banks.\n");
+      return 0;
+    }
+  else
+    {
+      BYTE * t_rom = *rom;
+      *rom = realloc (*rom, *size);
+      if (*rom == NULL)
+        {
+          free(t_rom);
+          fprintf (stderr, "error: couldn't re-allocate size for larger rom image.\n");
+          return 0;
+        }
+      memset (*rom + last_size, FILL_BYTE, *size - last_size);
+    }
+
+  return 1;
+}
+
+int
+noi2sym (char *filename)
+{
+  FILE *noi, *sym;
+  char *nname, *sname;
+  //ssize_t read;
+  char read = ' ';
+  // no$gmb's implementation is limited to 32 character labels
+  // we can safely throw away the rest
+  #define SYM_FILE_NAME_LEN_MAX 32
+  char label[SYM_FILE_NAME_LEN_MAX + 1];
+  // 0x + 6 digit hex number
+  // -> 65536 rom banks is the maximum homebrew cartrideges support (TPP1)
+  char value[9];
+  int name_len = strlen(filename);
+  int i = 0;
+  // copy filename's value to nname and sname
+  nname = malloc((name_len+1) * sizeof(char));
+  strcpy (nname, filename);
+  sname = malloc((name_len+1) * sizeof(char));
+  strcpy (sname, filename);
+  // change the extensions
+  nname[name_len-1]='i';
+  nname[name_len-2]='o';
+  nname[name_len-3]='n';
+  sname[name_len-1]='m';
+  sname[name_len-2]='y';
+  sname[name_len-3]='s';
+
+  if (NULL == (noi = fopen (nname, "r")))
+    {
+      fprintf (stderr, "error: can't open %s: ", nname);
+      perror(NULL);
+      return 1;
+    }
+  if (NULL == (sym = fopen (sname, "w")))
+    {
+      fprintf (stderr, "error: can't create %s: ", sname);
+      perror(NULL);
+      return 1;
+    }
+  // write header
+  fprintf (sym, "; no$gmb compatible .sym file\n; Generated automagically by makebin\n");
+  // iterate through .noi file
+  while (read != EOF && (read = fgetc(noi)) != EOF)
+    {
+      // just skip line breaks
+      if (read == '\r' || read == '\n')
+        continue;
+      // read first 4 chars
+      for (i = 0; i < 4; ++i)
+        {
+          value[i] = read;
+          if ((read = fgetc(noi)) == EOF || read == '\r' || read == '\n')
+            {
+              // leave for-loop
+              break;
+            }
+        }
+      // we left loop early
+      if (i != 4)
+        continue;
+      // only accept if line starts with this
+      if (strncmp(value, "DEF ", 4) == 0)
+        {
+          // read label
+          for (i = 0; i < (SYM_FILE_NAME_LEN_MAX - 1); ++i)
+            {
+              label[i] = read;
+              if ((read = fgetc(noi)) == EOF || read == '\r' || read == '\n' || read == ' ')
+                {
+                  // leave for-loop
+                  break;
+                }
+            }
+          // skip rest of the label
+          while (read != EOF && read != '\r' && read != '\n' && read != ' ')
+            read = fgetc(noi);
+          // it has to be end of file or line if it's not space
+          if (read != ' ')
+            continue;
+          // strings have to end with \0
+          label[i+1] = '\0';
+          // read value
+          for (i = 0; i < 8; ++i)
+            {
+              value[i] = read;
+              if ((read = fgetc(noi)) == EOF || read == '\r' || read == '\n')
+                {
+                  // leave for-loop
+                  break;
+                }
+            }
+          // number is too long; ignore
+          if (read != EOF && read != '\r' && read != '\n')
+            continue;
+          value[i+1] = '\0';
+          // we successfully read label and value
+
+          // but filter out some invalid symbols
+          if (strcmp(label, ".__.ABS.") != 0)
+            fprintf (sym, "%02X:%04X %s\n", (unsigned int)(strtoul(value, NULL, 0)>>16), (unsigned int)strtoul(value, NULL, 0)&0xFFFF, label);
+        }
+      else
+        // skip until file/line end
+        while ((read = fgetc(noi))!= EOF && read != '\r' && read != '\n');
+    }
+
+  // free close files
+  fclose (noi);
+  fclose (sym);
+
+  fprintf (stderr, "Converted %s to %s.\n", nname, sname);
+  return 0;
+}
+
+int
+read_ihx (FILE *fin, BYTE **rom, int *size, int *real_size, struct gb_opt_s *o)
 {
   int record_type;
 
+  int extaddr = 0;
   do
     {
       int nbytes;
@@ -294,22 +611,60 @@
       nbytes = getbyte (fin, &sum);
       addr = getbyte (fin, &sum) << 8 | getbyte (fin, &sum);
       record_type = getbyte (fin, &sum);
+      if(record_type == 4)
+        {
+          extaddr = getbyte (fin, &sum) << 8 | getbyte (fin, &sum);
+          extaddr <<= 16; // those are the upper 16 bits
+          checksum = getbyte (fin, &sum);
+          // move to the next record
+          if (0 != (sum & 0xff))
+            {
+              fprintf (stderr, "error: bad checksum: %02x.\n", checksum);
+              return 0;
+            }
+          while (isspace (sum = getc (fin)))  /* skip all kind of spaces */
+            ;
+          ungetc (sum, fin);
+          if (getc (fin) != ':')
+            {
+              fprintf (stderr, "error: invalid IHX line.\n");
+              return 0;
+            }
+          // parse real data part
+          checksum = sum = 0;
+          nbytes = getbyte (fin, &sum);
+          // lower 16 bits
+          addr = getbyte (fin, &sum) << 8 | getbyte (fin, &sum);
+          record_type = getbyte (fin, &sum);
+        }
+      // add linear address extension
+      addr |= extaddr;
+      // TODO: warn for unreachable banks according to chosen MBC
       if (record_type > 1)
         {
           fprintf (stderr, "error: unsupported record type: %02x.\n", record_type);
           return 0;
         }
 
-      if (addr + nbytes > size)
+      if (addr + nbytes > *size)
         {
-          fprintf (stderr, "error: size of the buffer is too small.\n");
-          return 0;
+          // If auto-size is enabled, grow rom bank size by power of 2 when needed
+          if (o->rom_banks_autosize)
+            {
+              if (rom_autosize_grow(rom, addr + nbytes, size, o) == 0)
+                return 0;
+            }
+          else
+            {
+              fprintf (stderr, "error: size of the buffer is too small.\n");
+              return 0;
+            }
         }
 
       while (nbytes--)
         {
-          if (addr < size)
-            rom[addr++] = getbyte (fin, &sum);
+          if (addr < *size)
+            (*rom)[addr++] = getbyte (fin, &sum);
         }
 
       if (addr > *real_size)
@@ -322,7 +677,7 @@
           return 0;
         }
 
-      while (isspace (sum = getc (fin)))  /* skip all kind of speces */
+      while (isspace (sum = getc (fin)))  /* skip all kind of spaces */
         ;
       ungetc (sum, fin);
     }
@@ -334,12 +689,33 @@
 int
 main (int argc, char **argv)
 {
-  int size = 32768, pack = 0, real_size = 0;
+  int size = 32768, offset = 0, pack = 0, real_size = 0, i = 0;
+  char *token;
   BYTE *rom;
   FILE *fin, *fout;
+  char *filename = NULL;
   int ret;
   int gb = 0;
-  struct gb_opt_s gb_opt = { "", 0, 2, 0 };
+  int sms = 0;
+
+  struct gb_opt_s gb_opt = {.cart_name="",
+                            .licensee_str={'0', '0'},
+                            .mbc_type=0,
+                            .nb_rom_banks=2,
+                            .nb_ram_banks=0,
+                            .licensee_id=0x33,
+                            .is_gbc=0,
+                            .is_sgb=0,
+                            .sym_conversion=0,
+                            .non_jp=0,
+                            .rom_banks_autosize=0,
+                            .do_logo_copy=true,
+                            .address_overwrite={0xFF, 0, 0xFF, 0, 0xFF, 0, 0xFF, 0, 0xFF, 0, 0xFF, 0, 0xFF, 0, 0xFF, 0} };
+
+  // 32KiB, SMS Export, version 0 <- should work with most emulaters (<32K was never used, GG accepts SMS)
+  struct sms_opt_s sms_opt = {.rom_size=0xc,
+                              .region_code=4,
+                              .version=0 };
 
 #if defined(_WIN32)
   setmode (fileno (stdout), O_BINARY);
@@ -355,7 +731,16 @@
               usage ();
               return 1;
             }
-          size = atoi (*argv);
+          size = strtoul (*argv, NULL, 0);
+          break;
+
+        case 'o':
+          if (!*++argv)
+            {
+              usage ();
+              return 1;
+            }
+          offset = strtoul (*argv, NULL, 0);
           break;
 
         case 'h':
@@ -386,7 +771,14 @@
                   usage ();
                   return 1;
                 }
-              gb_opt.nb_rom_banks = atoi (*argv);
+              // Use auto-size for rom banks if -yto size param is 'A'
+              if ((*argv)[0] == 'A' || (*argv)[0] == 'a')
+                  gb_opt.rom_banks_autosize = 1;
+              else
+                {
+                  gb_opt.nb_rom_banks = strtoul (*argv, NULL, 0);
+                  size = gb_opt.nb_rom_banks * 0x4000;
+                }
               break;
 
             case 'a':
@@ -395,7 +787,7 @@
                   usage ();
                   return 1;
                 }
-              gb_opt.nb_ram_banks = atoi (*argv);
+              gb_opt.nb_ram_banks = strtoul (*argv, NULL, 0);
               break;
 
             case 't':
@@ -404,7 +796,7 @@
                   usage ();
                   return 1;
                 }
-              gb_opt.mbc_type = atoi (*argv);
+              gb_opt.mbc_type = strtoul (*argv, NULL, 0);
               break;
 
             case 'n':
@@ -413,13 +805,144 @@
                   usage ();
                   return 1;
                 }
-              strncpy (gb_opt.cart_name, *argv, CART_NAME_LEN);
+              strncpy (gb_opt.cart_name, *argv, CART_NAME_LEN-1);
+              gb_opt.cart_name[CART_NAME_LEN-1] = '\0';
+              break;
+
+            case 'k':
+              if (!*++argv)
+                {
+                  usage ();
+                  return 1;
+                }
+              // we don't need \0
+              strncpy (gb_opt.licensee_str, *argv, 2);
+              break;
+
+            case 'l':
+              if (!*++argv)
+                {
+                  usage ();
+                  return 1;
+                }
+              gb_opt.licensee_id = strtoul (*argv, NULL, 0);
               break;
 
             case 'c':
               gb_opt.is_gbc = 1;
               break;
 
+            case 'C':
+              gb_opt.is_gbc = 2;
+              break;
+
+            case 'N':
+              gb_opt.do_logo_copy = false; // when switch is present, turn off logo copy
+              break;
+
+            case 's':
+              gb_opt.is_sgb = 1;
+              break;
+
+            case 'S':
+              gb_opt.sym_conversion = 1;
+              break;
+
+            case 'j':
+              gb_opt.non_jp = 1;
+              break;
+
+            // like -yp0x143=0x80
+            case 'p':
+              // remove "-yp"
+              *argv += 3;
+
+              // also support -yp 0x143=0x80
+              if (!(*argv)[0])
+                if (!*++argv)
+                  {
+                    usage ();
+                    return 1;
+                  }
+
+              // effectively split string into argv and token
+              strtok(*argv, "=");
+              token = strtok(NULL, "=");
+              for (i = 0; i < 16; i+=2)
+                {
+                  if (gb_opt.address_overwrite[i] == 0xFF)
+                    {
+                      gb_opt.address_overwrite[i] = strtoul (*argv, NULL, 0);
+                      gb_opt.address_overwrite[i+1] = strtoul (token, NULL, 0);
+                      break;
+                    }
+                }
+              break;
+
+            default:
+              usage ();
+              return 1;
+            }
+          break;
+
+        case 'S':
+          /* generate SMS binary file */
+          sms = 1;
+          break;
+
+        case 'x':
+
+          switch (argv[0][2])
+            {
+            case 'o':
+              if (!*++argv)
+                {
+                  usage ();
+                  return 1;
+                }
+              sms_opt.rom_size = strtoul (*argv, NULL, 0);
+              if ( sms_opt.rom_size > 2 && (sms_opt.rom_size < 0xa || sms_opt.rom_size > 0xf ) )
+                {
+                  fprintf (stderr, "error: invalid rom size (0x%X)", sms_opt.rom_size);
+                  perror(NULL);
+                  return 1;
+                }
+              if ( sms_opt.rom_size == 0xd || sms_opt.rom_size == 0x2 )
+                {
+                  fprintf (stderr, "warning: this rom size (0x%X) is bugged in some BIOSes\n", sms_opt.rom_size);
+                }
+              break;
+
+            case 'j':
+              if (!*++argv)
+                {
+                  usage ();
+                  return 1;
+                }
+              sms_opt.region_code = strtoul (*argv, NULL, 0);
+              if ( sms_opt.region_code < 3 && sms_opt.region_code > 7 )
+                {
+                  fprintf (stderr, "error: invalid region code (0x%X)", sms_opt.region_code);
+                  perror(NULL);
+                  return 1;
+                }
+              break;
+
+            case 'v':
+              if (!*++argv)
+                {
+                  usage ();
+                  return 1;
+                }
+              sms_opt.version = strtoul (*argv, NULL, 0);
+              if ( sms_opt.version > 0xf )
+                {
+                  fprintf (stderr, "error: invalid version (0x%X)", sms_opt.version);
+                  perror(NULL);
+                  return 1;
+                }
+              break;
+
             default:
               usage ();
               return 1;
@@ -444,6 +967,7 @@
               perror(NULL);
               return 1;
             }
+          filename = *argv;
         }
       ++argv;
     }
@@ -454,12 +978,6 @@
       return 1;
     }
 
-  if (gb && size != 32768)
-    {
-      fprintf (stderr, "error: only length of 32768 bytes supported for GameBoy binary.\n");
-      return 1;
-    }
-
   rom = malloc (size);
   if (rom == NULL)
     {
@@ -469,7 +987,17 @@
     }
   memset (rom, FILL_BYTE, size);
 
-  ret = read_ihx (fin, rom, size, &real_size);
+  if (gb_opt.sym_conversion == 1)
+    {
+      if (filename)
+        noi2sym(filename);
+      else
+        {
+          fprintf (stderr, "error: .noi to .sym conversion needs an input file.\n");
+        }
+    }
+
+  ret = read_ihx (fin, &rom, &size, &real_size, &gb_opt);
 
   fclose (fin);
 
@@ -477,6 +1005,8 @@
     {
       if (gb)
         gb_postproc (rom, size, &real_size, &gb_opt);
+      else if (sms)
+        sms_postproc (rom, size, &real_size, &sms_opt);
 
       if (*argv)
         {
@@ -490,8 +1020,14 @@
                 }
             }
         }
+      // skip offset
+      if (offset > 0)
+        {
+          memmove (rom, rom + offset, size - offset);
+          memset (rom + size - offset, FILL_BYTE, offset);
+        }
 
-      fwrite (rom, 1, (pack ? real_size : size), fout);
+      fwrite (rom, 1, (pack ? real_size : size) - offset, fout);
 
       fclose (fout);
 
diff -Nru sdcc-4.0.0+dfsg/support/regression/collate-results.py sdcc-4.2.0+dfsg/support/regression/collate-results.py
--- sdcc-4.0.0+dfsg/support/regression/collate-results.py	2019-03-12 10:39:11.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/collate-results.py	2021-07-25 22:43:04.000000000 +0000
@@ -7,6 +7,13 @@
 through stdin and summarises the total number of failures, test
 points, and test cases."""
 
+# Function to parse numbers
+def number_from_string(str_value):
+  if str_value.find("x") != -1:
+    return int(str_value.replace("0x", "").replace("x", ""), 16);
+  else:
+    return int(str_value)
+
 # Read in everything
 if sys.version_info[0]<3:
     safe_stdin = sys.stdin
@@ -21,6 +28,7 @@
 bytes = 0
 ticks = 0
 invalid = 0
+stack_overflow = 0
 halt = 0
 unmatch = 0
 flag = 0
@@ -31,13 +39,22 @@
 name = ""
 
 for line in lines:
+  
+    m = re.match(r'^Simulation started,', line)
+    if (m):
+        flag = 0
+        name = ""
+    
     # --- Running: gen/ucz80/longor/longor
     m = re.match(r'^--- Running: (.*)$', line)
     if (m):
-        name = m.group(1)
+        #take the name only if not a whitespace, this happens if simulator stops when calling to print the name (stack overflow)
+        stripped_name = m.group(1).strip()
+        if stripped_name != "":
+          name = stripped_name
 
     # in case the test program crashes before the "--- Running" message
-    m = re.match(r'^[0-9]+ words read from (.*)\.ihx$',line)
+    m = re.match(r'^[0-9]+ words read from (.*).ihx', line)
     if (m):
         name = m.group(1)
 
@@ -45,16 +62,20 @@
     # c = # test cases.
     if (re.search(r'^--- Summary:', line)):
         try:
-            (summary, data, rest) = re.split(r':', line)
+            if line.count(':') == 1:
+              (summary, data) = re.split(r':', line)
+            else:
+              (summary, data, rest) = re.split(r':', line)
+            
             (nfailures, ntests, ncases) = re.split(r'/', data)
-            failures = failures + int(nfailures)
-            tests = tests + int(ntests)
-            cases = cases + int(ncases)
+            failures = failures + number_from_string(nfailures)
+            tests = tests + number_from_string(ntests)
+            cases = cases + number_from_string(ncases)
         except ValueError:
             print("Parsing error at ", name)
             print("Bad summary line: ", line)
             nfailures = '1'
-        if (int(nfailures)):
+        if (number_from_string(nfailures)):
             messagelog.append("Failure: %s" % name)
         flag = 1 
 
@@ -81,6 +102,11 @@
     if (re.search(r'Invalid instruction', line) or re.search(r'unknown instruction', line)):
         invalid += 1
         messagelog.append("Invalid instruction: %s" % name)
+    
+    # Stop at 0xXXXXXX: (103) Stack overflow
+    if (re.search(r'Stack overflow', line)):
+        stack_overflow += 1
+        messagelog.append("Stack overflow: %s" % name)
 
     # HALT instruction 
     if (re.search(r'HALT instruction', line) or re.search(r'Halt instruction', line) or re.search(r'halt instruction', line)):
@@ -92,6 +118,7 @@
     if (m):
       name = line.split()[-1]
       name = '.'.join(name.split('.')[0:-1])
+    
 
 if (len(sys.argv) > 1):
     print("Summary for '%s':" % sys.argv[1], end=' ')
@@ -99,6 +126,8 @@
     print("%d abnormal stops (" % unmatch, end=' ')
     if (invalid > 0):
         print("%d invalid instructions," % invalid, end=' ')
+    if (stack_overflow > 0):
+        print("%d Stack overflows," % stack_overflow, end=' ')
     if (halt > 0):
         print("%d HALT instructions," % halt, end=' ')
     print("),", end=' ')
diff -Nru sdcc-4.0.0+dfsg/support/regression/compact-results.py sdcc-4.2.0+dfsg/support/regression/compact-results.py
--- sdcc-4.0.0+dfsg/support/regression/compact-results.py	2018-03-25 07:26:52.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/compact-results.py	2021-07-27 22:19:47.000000000 +0000
@@ -7,6 +7,19 @@
 through stdin and summarises the total number of failures, test
 points, and test cases."""
 
+# Function to parse numbers
+def number_from_string(str_value):
+  if str_value.find("x") != -1:
+    return int(str_value.replace("0x", "").replace("x", ""), 16);
+  else:
+    return int(str_value)
+    
+def running_name_valid(name):
+  if (name != "") and (name.find(" ") == -1) and ((name.find("/") != -1) or re.match(r'^(.*).c$', name)):
+    return True
+  else:
+    return False
+
 # Read in everything
 if sys.version_info[0]<3:
     safe_stdin = sys.stdin
@@ -14,25 +27,36 @@
     safe_stdin = io.TextIOWrapper(sys.stdin.buffer, encoding="latin-1")
 lines = safe_stdin.readlines()
 
-found = False
+summary_found = False
 for line in lines:
     if (re.search(r'^--- Summary:', line)):
-        found = True
+        summary_found = True
         break
 
-if not found:
+
+outname = ""
+if len(sys.argv) > 1:
+  outname = sys.argv[1]
+
+# Create lines not present in simulation log
+if not summary_found:
     fp = open(sys.argv[1], "w")
-    fp.write("--- Running: %s\n" % sys.argv[1])
-    fp.write("--- Summary: 1/0/0: 1 failed of 0 tests in 0 cases.\n")
+    fp.write("- Added by compact-results script: %s\n" % sys.argv[1])    
+    m = re.match(r'^(.*).out', outname)
+    if (m):
+      outname = m.group(1)
+    fp.write("--- Running: %s\n" % outname)
+    fp.write("--- Summary: 1/0/0: 1 failed of 0 tests in 0 cases.\n")  
     fp.close()
 
 # Init the running totals
-failures = 0
+failures = 0 if summary_found else 1
 cases = 0
 tests = 0
 bytes = 0
 ticks = 0
 invalid = 0
+stack_overflow = 0
 
 # hack for valdiag
 name = ""
@@ -42,32 +66,42 @@
     # --- Running: gen/ucz80/longor/longor
     m = re.match(r'^--- Running: (.*)$', line)
     if (m):
-        name = m.group(1)
-
-    # in case the test program crashes before the "--- Running" message
-    m = re.match(r'^[0-9]+ words read from (.*)\.ihx$',line)
+        #take the name only if not a whitespace, this happens if simulator stops when calling to print the name (stack overflow)
+        stripped_name = m.group(1).strip()
+        if running_name_valid(stripped_name):
+          name = stripped_name
+        
+    # In case the test program crashes before the "--- Running" message
+    m = re.match(r'^[0-9]+ words read from (.*).ihx', line)
     if (m):
         name = m.group(1)
-
-    base = name
-    m = re.match(r'([^/]*)/([^/]*)/([^/]*)/(.*)$', name)
+        
+    safe_name = name if name != "" else outname
+        
+    # Get base name from name
+    base = safe_name 
+    m = re.match(r'([^/]*)/([^/]*)/([^/]*)/(.*)$', base)
     if (m):
         base = m.group(3)
-
+  
     # '--- Summary: f/t/c: ...', where f = # failures, t = # test points,
     # c = # test cases.
     if (re.search(r'^--- Summary:', line)):
         try:
-            (summary, data, rest) = re.split(r':', line)
+            if line.count(':') == 1:
+              (summary, data) = re.split(r':', line)
+            else:
+              (summary, data, rest) = re.split(r':', line)
+            
             (nfailures, ntests, ncases) = re.split(r'/', data)
-            tests = tests + float(ntests)
-            cases = cases + float(ncases)
+            tests = tests + number_from_string(ntests)
+            cases = cases + number_from_string(ncases)
         except ValueError:
             print("Bad summary line:", line)
             nfailures = '1'
-        failures = failures + float(nfailures)
-        if (float(nfailures)):
-            print("Failure: %s" % name)
+        failures = failures + number_from_string(nfailures)
+        if (number_from_string(nfailures)):
+            print("Failure: %s" % safe_name)
 
     # '--- Simulator: b/t: ...', where b = # bytes, t = # ticks
     if (re.search(r'^--- Simulator:', line)):
@@ -83,7 +117,13 @@
     # Stop at 0x000228: (106) Invalid instruction 0x00fd
     if (re.search(r'Invalid instruction', line) or re.search(r'unknown instruction', line)):
         invalid += 1;
-        print("Invalid instruction: %s" % name)
+        print("Invalid instruction: %s" % safe_name)
+        
+    # Stop at 0xXXXXXX: (103) Stack overflow
+    if (re.search(r'Stack overflow', line)):
+        stack_overflow += 1
+        print("Stack overflow: %s" % safe_name)
+    
 
 print("%-35.35s" % base, end=' ')
 
diff -Nru sdcc-4.0.0+dfsg/support/regression/fwk/include/testfwk.h sdcc-4.2.0+dfsg/support/regression/fwk/include/testfwk.h
--- sdcc-4.0.0+dfsg/support/regression/fwk/include/testfwk.h	2019-10-14 11:33:28.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/fwk/include/testfwk.h	2022-01-08 21:36:53.000000000 +0000
@@ -1,6 +1,31 @@
 #ifndef __TESTFWK_H
 #define __TESTFWK_H   1
 
+// This is used to avoid repeating the same checks over and over again, also much easier to maintain.
+#if defined(__SDCC_pdk13)
+  #define SDCC_PDK 13
+#elif defined(__SDCC_pdk14)
+  #define SDCC_PDK 14
+#elif defined(__SDCC_pdk15)
+  #define SDCC_PDK 15
+#elif defined(__SDCC_pdk16)
+  #define SDCC_PDK 16
+#endif
+
+// This macro allows easy check for multiple devices: SDCC_PDK_BITS(<=13), SDCC_PDK_BITS(>=14)
+#ifdef SDCC_PDK
+  #define SDCC_PDK_BITS(cond) (SDCC_PDK cond)
+#else
+  #define SDCC_PDK_BITS(cond) 0 // Always 0 (false) for other backends
+#endif
+
+// Enable low memory mode for small devices.
+#if SDCC_PDK_BITS(<=14)
+  #define TARGET_VERY_LOW_MEMORY
+  #undef NO_VARARGS
+  #define NO_VARARGS
+#endif
+
 extern int __numTests;
 extern const int __numCases;
 
@@ -18,19 +43,40 @@
  #define _STATMEM
 #endif
 
-#if defined(PORT_HOST) || defined(__SDCC_z80) || defined(__SDCC_z180) || defined(__SDCC_r2k) || defined(__SDCC_r3ka) || defined(__SDCC_gbz80) || defined(__SDCC_stm8) || defined(__SDCC_tlcs90) || defined(__SDCC_ez80_z80)
-# define __data
-# define __idata
-# define __pdata
-# define __xdata
-# define __code
-# define __near
-# define __far
-# define __reentrant
+#if defined(__SDCC_stm8) || defined(PORT_HOST)
+#define __data
+#define __idata
+#define __pdata
+#define __xdata
+#define __code
+#define __near
+#define __far
+#define __reentrant
+#endif
+
+#if defined(__SDCC_z80) || defined(__SDCC_z180) || defined(__SDCC_r2k) || defined(__SDCC_r2ka) || defined(__SDCC_r3ka) || defined(__SDCC_sm83) || defined(__SDCC_tlcs90) || defined(__SDCC_ez80_z80) || defined(__SDCC_z80n)
+#define __data
+#define __idata
+#define __pdata
+#define __xdata
+#define __code
+#define __near
+#define __far
+#define __reentrant
+#else
+#define __smallc
+#define __z88dk_fastcall
+#ifndef __SDCC_stm8
+#define __z88dk_callee
+#endif
+#endif
+
+#ifdef __SDCC_sm83
+#define __z88dk_fastcall
 #endif
 
-#if defined(__SDCC_pdk13) || defined(__SDCC_pdk14) || defined(__SDCC_pdk15)
-# define __data
+#if defined(SDCC_PDK)
+//# define __data // data is implemented for pdk
 # define __idata
 # define __pdata
 # define __xdata
@@ -48,6 +94,11 @@
 # define __pdata __data
 #endif
 
+#if defined(__SDCC_mos6502) || defined(__SDCC_mos65c02)
+# define __idata __data
+# define __pdata __data
+#endif
+
 #if defined(__SDCC_pic14)
 # define __idata __data
 # define __xdata __data
@@ -63,7 +114,9 @@
 void __fail (__code const char *szMsg, __code const char *szCond, __code const char *szFile, int line);
 void __prints (const char *s);
 void __printd (int n);
+#ifndef TARGET_VERY_LOW_MEMORY
 void __printu (unsigned int n);
+#endif
 __code const char *__getSuiteName (void);
 void __runSuite (void);
 
diff -Nru sdcc-4.0.0+dfsg/support/regression/fwk/lib/testfwk.c sdcc-4.2.0+dfsg/support/regression/fwk/lib/testfwk.c
--- sdcc-4.0.0+dfsg/support/regression/fwk/lib/testfwk.c	2018-08-13 19:42:50.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/fwk/lib/testfwk.c	2021-07-25 22:49:39.000000000 +0000
@@ -29,7 +29,7 @@
 int __numTests = 0;
 static int __numFailures = 0;
 
-#if BROKEN_DIV_MOD
+#if BROKEN_DIV_MOD && !defined(TARGET_VERY_LOW_MEMORY)
 static int
 __div(int num, int denom)
 {
@@ -68,6 +68,44 @@
     }
 }
 
+#ifdef TARGET_VERY_LOW_MEMORY
+static void
+__printNibble (unsigned char c)
+{
+  c &= 0x0F;
+  if (c <= 9 )
+    c += '0';
+  else
+    c += 'A' - 10;
+  _putchar(c);
+}
+void
+__printd (int n)
+{
+  unsigned char chr;
+  #define SWAP_BYTE(x)  ((x) >> 4 | (x) << 4)
+
+  if (0 > n)
+    {
+      n = -n;
+      _putchar('-');
+    }
+  _putchar('x');
+
+  // This seems to be the most efficient way to do it for PDK (both in RAM & ROM)
+  chr = n >> 8;
+  chr = SWAP_BYTE(chr);
+  __printNibble(chr);
+  chr = SWAP_BYTE(chr);
+  __printNibble(chr);
+
+  chr = n & 0xFF;
+  chr = SWAP_BYTE(chr);
+  __printNibble(chr);
+  chr = SWAP_BYTE(chr);
+  __printNibble(chr);
+}
+#else
 void
 __printd (int n)
 {
@@ -125,6 +163,7 @@
       __prints(p);
     }
 }
+#endif
 
 #ifndef NO_VARARGS
 void
@@ -236,6 +275,8 @@
   __printd(__numTests);
   _putchar('/');
   __printd(__numCases);
+
+  #ifndef TARGET_VERY_LOW_MEMORY
   __prints(": ");
   __printd(__numFailures);
   __prints(" failed of ");
@@ -243,6 +284,9 @@
   __prints(" tests in ");
   __printd(__numCases);
   __prints(" cases.\n");
+  #else
+  _putchar('\n');
+  #endif
 
   _exitEmu();
 
diff -Nru sdcc-4.0.0+dfsg/support/regression/generate-cases.py sdcc-4.2.0+dfsg/support/regression/generate-cases.py
--- sdcc-4.0.0+dfsg/support/regression/generate-cases.py	2018-03-19 09:26:28.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/generate-cases.py	2022-02-03 09:32:48.000000000 +0000
@@ -55,7 +55,7 @@
         (self.basename, self.ext) = os.path.splitext (self.filename)
 
     def permute(self, basepath, keys, trans = {}):
-        """Permutes across all of the names.  For each value, recursivly creates
+        """Permutes across all of the names.  For each value, recursively creates
         a mangled form of the name, this value, and all the combinations of
         the remaining values.  At the tail of the recursion when one full
         combination is built, generates an instance of the test case from
@@ -69,7 +69,7 @@
             T.substitutions = trans
             T.write(basepath + self.ext)
         else:
-            # Pull off this key, then recursivly iterate through the rest.
+            # Pull off this key, then recursively iterate through the rest.
             key = keys[0]
             for part in self.replacements[key]:
                 trans[key] = part
diff -Nru sdcc-4.0.0+dfsg/support/regression/Makefile.in sdcc-4.2.0+dfsg/support/regression/Makefile.in
--- sdcc-4.0.0+dfsg/support/regression/Makefile.in	2020-01-22 11:31:27.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/Makefile.in	2022-02-01 18:03:45.000000000 +0000
@@ -70,7 +70,7 @@
 # Each directory under ports/ is used as a port name.  Each port is tested.
 # Each port must have a spec.mk which describes how to build the object
 # files and how to run the emulator.
-ALL_PORTS = $(filter-out .svn rrz80 rrgbz80 pic16 pic14 mcs51-common pdk15-stack-auto,$(notdir $(wildcard $(PORTS_DIR)/*)))
+ALL_PORTS = $(filter-out .svn mos6502 mcs51-xstack-auto rrz80 rrgbz80 pic16 pic14 mcs51-common pdk13,$(notdir $(wildcard $(PORTS_DIR)/*)))
 
 # These  ports will be cleaned with 'make clean'
 CLEAN_PORTS = $(filter-out .svn mcs51-common,$(notdir $(wildcard $(PORTS_DIR)/*)))
@@ -134,13 +134,18 @@
 	$(MAKE) test-port PORT=ds390
 
 # Helper rule for testing the z80 related ports only
-test-z80: test-ucz80 test-ucz80-resiy test-ucz180 test-ucgbz80 test-ucr2k test-ucr3ka test-ez80-z80 test-tlcs90
+test-z80: test-ucz80 test-ucz80-resiy test-ucz180 test-ucz80-resiy test-ucz80n test-ucgbz80 test-ucr2k test-ucr2ka test-ucr3ka test-ez80-z80 test-tlcs90
 
 # Helper rule for testing the z80 port only (use uCsim simulator)
 test-ucz80:
 	$(MAKE) test-common
 	$(MAKE) test-port PORT=ucz80
 
+# Helper rule for testing the z80 port with --nmos-z80 only (use uCsim simulator)
+test-ucz80-nmos:
+	$(MAKE) test-common
+	$(MAKE) test-port PORT=ucz80-nmos
+
 # Helper rule for testing the z80 port with --reserve-regs-iy only (use uCsim simulator)
 test-ucz80-resiy:
 	$(MAKE) test-common
@@ -151,6 +156,11 @@
 	$(MAKE) test-common
 	$(MAKE) test-port PORT=ucz180
 
+# Helper rule for testing the z180 port with --reserve-regs-iy only (use uCsim simulator)
+test-ucz180-resiy:
+	$(MAKE) test-common
+	$(MAKE) test-port PORT=ucz180-resiy
+
 # Helper rule for testing the gb/lr35902 port only(use uCsim simulator)
 test-ucgbz80:
 	$(MAKE) test-common
@@ -161,11 +171,20 @@
 	$(MAKE) test-common
 	$(MAKE) test-port PORT=ucr2k
 
+# Helper rule for testing the r2ka port only(use uCsim simulator)
+test-ucr2ka:
+	$(MAKE) test-common
+	$(MAKE) test-port PORT=ucr2ka
+
 # Helper rule for testing the r3k port only(use uCsim simulator)
 test-ucr3ka:
 	$(MAKE) test-common
 	$(MAKE) test-port PORT=ucr3ka
 
+test-ucrxk3a:
+	$(MAKE) test-common
+	$(MAKE) test-port PORT=ucrxk3a
+
 # Helper rule for testing the hc08 port only(use uCsim simulator)
 test-hc08:
 	$(MAKE) test-common
@@ -206,6 +225,19 @@
 	$(MAKE) test-common
 	$(MAKE) test-port PORT=ez80-z80
 
+# Helper rule for testing the z80n port only(use uCsim simulator)
+test-ucz80n:
+	$(MAKE) test-common
+	$(MAKE) test-port PORT=ucz80n
+
+# Helper rule for testing the pdk ports only
+test-pdk: test-pdk14 test-pdk15 test-pdk15-stack-auto
+
+# Helper rule for testing the pdk13 port only(use uCsim simulator)
+test-pdk13:
+	$(MAKE) test-common
+	$(MAKE) test-port PORT=pdk13
+
 # Helper rule for testing the pdk14 port only(use uCsim simulator)
 test-pdk14:
 	$(MAKE) test-common
@@ -221,6 +253,16 @@
 	$(MAKE) test-common
 	$(MAKE) test-port PORT=pdk15-stack-auto
 
+# Helper rule for testing the mos6502 port only(use sim65 simulator)
+test-mos6502:
+	$(MAKE) test-common
+	$(MAKE) test-port PORT=mos6502
+
+# Helper rule for testing the mos6502 port only(use uCsim simulator)
+test-uc6502:
+	$(MAKE) test-common
+	$(MAKE) test-port PORT=uc6502
+
 ### Helper rule for testing the host cc only
 test-host:
 	$(MAKE) test-common
@@ -317,8 +359,8 @@
 
 # Rule to summarise the results for one port after all of the tests
 # have been run.
-port-results: $(PORT_RESULTS)
-	cat $(PORT_RESULTS) | $(PYTHON) $(srcdir)/collate-results.py $(PORT)
+$(RESULTS_DIR)/$(PORT).sum: $(PORT_RESULTS)
+	cat $(PORT_RESULTS) | $(PYTHON) $(srcdir)/collate-results.py $(PORT) > $@
 
 port-fwklib: $(EXTRAS) $(FWKLIB)
 
@@ -334,7 +376,8 @@
 	# recurse: force vpath to re-read the $(CASES_DIR)
 	$(MAKE) port-dirs PORT=$(PORT)
 	$(MAKE) port-fwklib PORT=$(PORT)
-	$(MAKE) port-results PORT=$(PORT)
+	$(MAKE) $(RESULTS_DIR)/$(PORT).sum PORT=$(PORT)
+	cat $(RESULTS_DIR)/$(PORT).sum
 
 # Begin rules that process each iteration generated from the source
 # test
@@ -369,7 +412,7 @@
 # BeginGeneric rules
 
 clean:
-	rm -rf $(CASES_DIR) $(RESULTS_DIR) *.pyc
+	rm -rf $(CASES_DIR) $(RESULTS_DIR) *.pyc __pycache__
 	for i in $(CLEAN_PORTS); do \
 	  $(MAKE) -f $(PORTS_DIR)/$$i/spec.mk _clean PORTS_DIR=$(PORTS_DIR) PORT=$$i srcdir=$(srcdir); \
 	done
diff -Nru sdcc-4.0.0+dfsg/support/regression/ports/ds390/spec.mk sdcc-4.2.0+dfsg/support/regression/ports/ds390/spec.mk
--- sdcc-4.0.0+dfsg/support/regression/ports/ds390/spec.mk	2018-01-05 17:10:47.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/ports/ds390/spec.mk	2021-09-23 13:51:50.000000000 +0000
@@ -9,13 +9,13 @@
 
 # path to uCsim
 ifdef SDCC_BIN_PATH
-  S51 = $(SDCC_BIN_PATH)/s51$(EXEEXT)
+  S51 = $(SDCC_BIN_PATH)/ucsim_51$(EXEEXT)
 else
   ifdef UCSIM_DIR
-    S51A = $(UCSIM_DIR)/s51.src/s51$(EXEEXT)
+    S51A = $(UCSIM_DIR)/s51.src/ucsim_51$(EXEEXT)
   else
-    S51A = $(top_builddir)/sim/ucsim/s51.src/s51$(EXEEXT)
-    S51B = $(top_builddir)/bin/s51$(EXEEXT)
+    S51A = $(top_builddir)/sim/ucsim/s51.src/ucsim_51$(EXEEXT)
+    S51B = $(top_builddir)/bin/ucsim_51$(EXEEXT)
   endif
 
   EMU = $(WINE) $(shell if [ -f $(S51A) ]; then echo $(S51A); else echo $(S51B); fi)
diff -Nru sdcc-4.0.0+dfsg/support/regression/ports/ez80-z80/spec.mk sdcc-4.2.0+dfsg/support/regression/ports/ez80-z80/spec.mk
--- sdcc-4.0.0+dfsg/support/regression/ports/ez80-z80/spec.mk	2019-01-07 14:51:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/ports/ez80-z80/spec.mk	2021-11-17 08:35:03.000000000 +0000
@@ -5,15 +5,15 @@
 
 # path to uCsim
 ifdef SDCC_BIN_PATH
-  UCZ80C = $(SDCC_BIN_PATH)/sz80$(EXEEXT)
+  UCZ80C = $(SDCC_BIN_PATH)/ucsim_z80$(EXEEXT)
 
   AS_Z80C = $(SDCC_BIN_PATH)/sdasz80$(EXEEXT)
 else
   ifdef UCSIM_DIR
-    SZ80A = $(UCSIM_DIR)/z80.src/sz80$(EXEEXT)
+    SZ80A = $(UCSIM_DIR)/z80.src/ucsim_z80$(EXEEXT)
   else
-    SZ80A = $(top_builddir)/sim/ucsim/z80.src/sz80$(EXEEXT)
-    SZ80B = $(top_builddir)/bin/sz80$(EXEEXT)
+    SZ80A = $(top_builddir)/sim/ucsim/z80.src/ucsim_z80$(EXEEXT)
+    SZ80B = $(top_builddir)/bin/ucsim_z80$(EXEEXT)
   endif
 
   EMU = $(WINE) $(shell if [ -f $(SZ80A) ]; then echo $(SZ80A); else echo $(SZ80B); fi)
@@ -30,7 +30,7 @@
   SDCCFLAGS += -I$(top_srcdir)
 endif
 
-SDCCFLAGS += -mez80_z80 --less-pedantic --profile
+SDCCFLAGS += -mez80_z80 --less-pedantic
 LINKFLAGS += ez80_z80.lib
 
 OBJEXT = .rel
diff -Nru sdcc-4.0.0+dfsg/support/regression/ports/ez80-z80/support.asm sdcc-4.2.0+dfsg/support/regression/ports/ez80-z80/support.asm
--- sdcc-4.0.0+dfsg/support/regression/ports/ez80-z80/support.asm	2016-06-16 12:01:50.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/ports/ez80-z80/support.asm	1970-01-01 00:00:00.000000000 +0000
@@ -1,16 +0,0 @@
-        .area   _CODE
-        .globl  _exit
-
-__putchar::
-		ld	hl, #2
-		add	hl, sp
-		ld	l, (hl)
-		ld	a, #1
-		rst	0x08
-		ret
-
-__initEmu::
-        ret
-
-__exitEmu::
-        jp      _exit
diff -Nru sdcc-4.0.0+dfsg/support/regression/ports/ez80-z80/support.c sdcc-4.2.0+dfsg/support/regression/ports/ez80-z80/support.c
--- sdcc-4.0.0+dfsg/support/regression/ports/ez80-z80/support.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/ports/ez80-z80/support.c	2021-05-20 13:17:39.000000000 +0000
@@ -0,0 +1,19 @@
+__sfr __at 0xff sif;
+
+void
+_putchar(unsigned char c)
+{
+  sif= 'p';
+  sif= c;
+}
+
+void
+_initEmu(void)
+{
+}
+
+void
+_exitEmu(void)
+{
+  sif= 's';
+}
diff -Nru sdcc-4.0.0+dfsg/support/regression/ports/ez80-z80/uCsim.cmd sdcc-4.2.0+dfsg/support/regression/ports/ez80-z80/uCsim.cmd
--- sdcc-4.0.0+dfsg/support/regression/ports/ez80-z80/uCsim.cmd	2011-09-24 18:55:19.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/ports/ez80-z80/uCsim.cmd	2021-05-20 13:17:39.000000000 +0000
@@ -2,6 +2,7 @@
 set error unknown_code off
 set error memory off
 set error stack off
+set hw simif outputs 0xff
 run
 state
 quit
diff -Nru sdcc-4.0.0+dfsg/support/regression/ports/hc08/spec.mk sdcc-4.2.0+dfsg/support/regression/ports/hc08/spec.mk
--- sdcc-4.0.0+dfsg/support/regression/ports/hc08/spec.mk	2018-08-22 12:51:20.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/ports/hc08/spec.mk	2022-02-01 18:43:34.000000000 +0000
@@ -1,19 +1,19 @@
 # Regression test specification for the hc08 target running with uCsim
 
 # simulation timeout in seconds
-SIM_TIMEOUT = 40
+SIM_TIMEOUT = 60
 
 # path to uCsim
 ifdef SDCC_BIN_PATH
-  UCHC08C = $(SDCC_BIN_PATH)/shc08$(EXEEXT)
+  UCHC08C = $(SDCC_BIN_PATH)/ucsim_m68hc08$(EXEEXT)
 
   AS_HC08C = $(SDCC_BIN_PATH)/sdas6808$(EXEEXT)
 else
   ifdef UCSIM_DIR
-    UCHC08A = $(UCSIM_DIR)/hc08.src/shc08$(EXEEXT)
+    UCHC08A = $(UCSIM_DIR)/m68hc08.src/ucsim_m68hc08$(EXEEXT)
   else
-    UCHC08A = $(top_builddir)/sim/ucsim/hc08.src/shc08$(EXEEXT)
-    UCHC08B = $(top_builddir)/bin/shc08$(EXEEXT)
+    UCHC08A = $(top_builddir)/sim/ucsim/m68hc08.src/ucsim_m68hc08$(EXEEXT)
+    UCHC08B = $(top_builddir)/bin/ucsim_m68hc08$(EXEEXT)
   endif
 
   EMU = $(WINE) $(shell if [ -f $(UCHC08A) ]; then echo $(UCHC08A); else echo $(UCHC08B); fi)
diff -Nru sdcc-4.0.0+dfsg/support/regression/ports/hc08/support.c sdcc-4.2.0+dfsg/support/regression/ports/hc08/support.c
--- sdcc-4.0.0+dfsg/support/regression/ports/hc08/support.c	2010-01-15 13:26:59.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/ports/hc08/support.c	2020-06-12 07:51:53.000000000 +0000
@@ -1,7 +1,11 @@
+static unsigned char * volatile sif;
 
 void
 _putchar(unsigned char c)
 {
+  *sif= 'p';
+  *sif= c;
+  return;
   c;
   __asm
     .db 0x9e, 0xed
@@ -11,11 +15,14 @@
 void
 _initEmu(void)
 {
+  sif= (unsigned char *)0x7f;
 }
 
 void
 _exitEmu(void)
 {
+  *sif= 's';
+  return;
   __asm
     .db 0x9e, 0xec
   __endasm;
diff -Nru sdcc-4.0.0+dfsg/support/regression/ports/hc08/uCsim.cmd sdcc-4.2.0+dfsg/support/regression/ports/hc08/uCsim.cmd
--- sdcc-4.0.0+dfsg/support/regression/ports/hc08/uCsim.cmd	2005-12-07 12:49:32.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/ports/hc08/uCsim.cmd	2020-06-12 07:51:53.000000000 +0000
@@ -2,6 +2,7 @@
 set error unknown_code off
 set error memory off
 set error stack off
+set hw simif rom 0x7f
 run
 state
 quit
diff -Nru sdcc-4.0.0+dfsg/support/regression/ports/host/spec.mk.in sdcc-4.2.0+dfsg/support/regression/ports/host/spec.mk.in
--- sdcc-4.0.0+dfsg/support/regression/ports/host/spec.mk.in	2011-05-11 15:18:49.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/ports/host/spec.mk.in	2021-04-04 10:00:19.000000000 +0000
@@ -1,4 +1,8 @@
-# Port specification for compiling on the host machines version of gcc
+# Port specification for compiling on the host machines compiler
+
+# runtimeout in seconds
+RUN_TIMEOUT = 1
+
 SDCC = @CC@
 SDCCFLAGS = @CFLAGS@ @C99_FLAG@ $(CPPFLAGS) -DPORT_HOST=1 -DREENTRANT= -I$(top_builddir) -I$(top_srcdir)
 SDLDFLAGS = @LDFLAGS@
@@ -18,9 +22,9 @@
 EXTRAS = $(PORT_CASES_DIR)/testfwk$(OBJEXT) $(PORT_CASES_DIR)/support$(OBJEXT)
 include $(srcdir)/fwk/lib/spec.mk
 
-%.out: %$(BINEXT)
+%.out: %$(BINEXT) $(CASES_DIR)/timeout
 	mkdir -p $(dir $@)
-	-$< > $@
+	-$(CASES_DIR)/timeout $(RUN_TIMEOUT) $< > $@
 	-grep -n FAIL $@ /dev/null || true
 
 %$(BINEXT): %$(OBJEXT) $(EXTRAS) $(FWKLIB)
diff -Nru sdcc-4.0.0+dfsg/support/regression/ports/mcs51-common/spec.mk sdcc-4.2.0+dfsg/support/regression/ports/mcs51-common/spec.mk
--- sdcc-4.0.0+dfsg/support/regression/ports/mcs51-common/spec.mk	2017-10-10 09:08:15.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/ports/mcs51-common/spec.mk	2022-01-11 21:21:11.000000000 +0000
@@ -5,13 +5,13 @@
 
 # path to uCsim
 ifdef SDCC_BIN_PATH
-  S51 = $(SDCC_BIN_PATH)/s51$(EXEEXT)
+  S51 = $(SDCC_BIN_PATH)/ucsim_51$(EXEEXT)
 else
   ifdef UCSIM_DIR
-    S51A = $(UCSIM_DIR)/s51.src/s51$(EXEEXT)
+    S51A = $(UCSIM_DIR)/s51.src/ucsim_51$(EXEEXT)
   else
-    S51A = $(top_builddir)/sim/ucsim/s51.src/s51$(EXEEXT)
-    S51B = $(top_builddir)/bin/s51$(EXEEXT)
+    S51A = $(top_builddir)/sim/ucsim/s51.src/ucsim_51$(EXEEXT)
+    S51B = $(top_builddir)/bin/ucsim_51$(EXEEXT)
   endif
 
   EMU = $(WINE) $(shell if [ -f $(S51A) ]; then echo $(S51A); else echo $(S51B); fi)
@@ -29,8 +29,8 @@
   DEV_NULL ?= /dev/null
 endif
 
-SDCCFLAGS += --less-pedantic
-LINKFLAGS += mcs51.lib libsdcc.lib liblong.lib libint.lib libfloat.lib liblonglong.lib
+SDCCFLAGS += --debug --less-pedantic
+LINKFLAGS += --debug mcs51.lib libsdcc.lib liblong.lib libint.lib libfloat.lib liblonglong.lib
 
 OBJEXT = .rel
 BINEXT = .ihx
diff -Nru sdcc-4.0.0+dfsg/support/regression/ports/mos6502/spec.mk sdcc-4.2.0+dfsg/support/regression/ports/mos6502/spec.mk
--- sdcc-4.0.0+dfsg/support/regression/ports/mos6502/spec.mk	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/ports/mos6502/spec.mk	2022-01-09 13:36:17.000000000 +0000
@@ -0,0 +1,67 @@
+# Regression test specification for the mos6502 target running with sim65
+
+# simulation timeout in cycles
+SIM_CYCLES = 1000000000
+SIM_TIMEOUT = 30
+
+# path to sim65
+EMU = $(WINE) sim65 -c -v -x $(SIM_CYCLES)
+MAKEBIN = $(top_builddir)/bin/makebin$(EXEEXT)
+ifdef SDCC_BIN_PATH
+  AS = $(SDCC_BIN_PATH)/sdas6500$(EXEEXT)
+else
+  AS = $(WINE) $(top_builddir)/bin/sdas6500$(EXEEXT)
+ifndef CROSSCOMPILING
+  SDCCFLAGS += --nostdinc -I$(top_srcdir)
+  LINKFLAGS += --nostdlib -L$(top_builddir)/device/lib/build/mos6502
+endif
+endif
+
+ifdef CROSSCOMPILING
+  SDCCFLAGS += -I$(top_srcdir)
+endif
+
+SDCCFLAGS += -mmos6502 --less-pedantic --out-fmt-ihx --code-loc 0x200 --xram-loc 0xc000
+LINKFLAGS += mos6502.lib
+
+OBJEXT = .rel
+BINEXT = .ihx
+
+# otherwise `make` deletes testfwk.rel and `make -j` will fail
+.PRECIOUS: $(PORT_CASES_DIR)/%$(OBJEXT)
+
+# Required extras
+EXTRAS = $(PORT_CASES_DIR)/testfwk$(OBJEXT) $(PORT_CASES_DIR)/support$(OBJEXT)
+include $(srcdir)/fwk/lib/spec.mk
+
+# Rule to link into .ihx
+%$(BINEXT): %$(OBJEXT) $(EXTRAS) $(FWKLIB) $(PORT_CASES_DIR)/fwk.lib
+	$(SDCC) $(SDCCFLAGS) $(LINKFLAGS) $(EXTRAS) $(PORT_CASES_DIR)/fwk.lib $< -o $@
+
+%$(OBJEXT): %.asm
+	$(AS) -plosgff $<
+
+%$(OBJEXT): %.c
+	$(VALGRIND) $(SDCC) $(SDCCFLAGS) -c $< -o $@
+
+$(PORT_CASES_DIR)/%$(OBJEXT): $(PORTS_DIR)/$(PORT)/%.c
+	$(SDCC) $(SDCCFLAGS) -c $< -o $@
+
+$(PORT_CASES_DIR)/%$(OBJEXT): $(srcdir)/fwk/lib/%.c
+	$(SDCC) $(SDCCFLAGS) -c $< -o $@
+
+$(PORT_CASES_DIR)/fwk.lib: $(srcdir)/fwk/lib/fwk.lib
+	cat < $(srcdir)/fwk/lib/fwk.lib > $@
+
+# run simulator with SIM_TIMEOUT seconds timeout
+%.out: %$(BINEXT) $(CASES_DIR)/timeout
+	mkdir -p $(dir $@)
+	$(MAKEBIN) -s 65536 $< $*.rom
+	printf 'sim65\2\0\0\0\2\0\2' > $*.bin
+	dd status=none if=$*.rom bs=512 count=126 skip=1 >> $*.bin
+	-$(CASES_DIR)/timeout $(SIM_TIMEOUT) $(EMU) $*.bin > $@ \
+	  || echo -e --- FAIL: \"timeout, simulation killed\" in $(<:$(BINEXT)=.c)"\n"--- Summary: 1/1/1: timeout >> $@
+	$(PYTHON) $(srcdir)/get_ticks.py < $@ >> $@
+	-grep -n FAIL $@ /dev/null || true
+
+_clean:
diff -Nru sdcc-4.0.0+dfsg/support/regression/ports/mos6502/support.c sdcc-4.2.0+dfsg/support/regression/ports/mos6502/support.c
--- sdcc-4.0.0+dfsg/support/regression/ports/mos6502/support.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/ports/mos6502/support.c	2022-01-08 21:36:53.000000000 +0000
@@ -0,0 +1,38 @@
+
+// sim65 constants
+#define SYS_open  0xfff4
+#define SYS_close 0xfff5
+#define SYS_read  0xfff6
+#define SYS_write 0xfff7
+#define SYS_args  0xfff8
+#define SYS_exit  0xfff9
+
+typedef void (*sim65_write_t)(int count, const char* buf, int fd) __reentrant;
+
+// sim65 expects a software stack
+unsigned short stack[8];
+
+// stack pointer location defined in sim65 header
+unsigned short* __at(0x0) stackptr;
+
+void
+_putchar(unsigned char c)
+{
+  stackptr = stack;
+  stackptr[0] = (short)&c;
+  stackptr[1] = 1;
+  (*(sim65_write_t)SYS_write)(1, &c, 1);
+}
+
+void
+_initEmu(void)
+{
+}
+
+void
+_exitEmu(void)
+{
+  __asm
+    jsr SYS_exit
+  __endasm;
+}
diff -Nru sdcc-4.0.0+dfsg/support/regression/ports/pdk13/spec.mk sdcc-4.2.0+dfsg/support/regression/ports/pdk13/spec.mk
--- sdcc-4.0.0+dfsg/support/regression/ports/pdk13/spec.mk	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/ports/pdk13/spec.mk	2021-09-23 13:51:50.000000000 +0000
@@ -0,0 +1,73 @@
+# Regression test specification for the pdk13 target running with uCsim
+
+# simulation timeout in seconds
+SIM_TIMEOUT = 30
+
+# path to uCsim
+ifdef SDCC_BIN_PATH
+  UCPDK13C = $(SDCC_BIN_PATH)/ucsim_pdk$(EXEEXT)
+
+  AS_PDK13C = $(SDCC_BIN_PATH)/sdaspdk$(EXEEXT)
+else
+  ifdef UCSIM_DIR
+    UCPDK13A = $(UCSIM_DIR)/pdk.src/ucsim_pdk$(EXEEXT)
+  else
+    UCPDK13A = $(top_builddir)/sim/ucsim/pdk.src/ucsim_pdk$(EXEEXT)
+    UCPDK13B = $(top_builddir)/bin/ucsim_pdk$(EXEEXT)
+  endif
+
+  EMU = $(WINE) $(shell if [ -f $(UCPDK13A) ]; then echo $(UCPDK13A); else echo $(UCPDK13B); fi)
+
+  AS = $(WINE) $(top_builddir)/bin/sdaspdk$(EXEEXT)
+
+ifndef CROSSCOMPILING
+  SDCCFLAGS += --nostdinc -I$(top_srcdir)
+  LINKFLAGS += --nostdlib -L$(top_builddir)/device/lib/build/pdk13
+endif
+endif
+
+ifdef CROSSCOMPILING
+  SDCCFLAGS += -I$(top_srcdir)
+endif
+
+SDCCFLAGS += -mpdk13 --less-pedantic --out-fmt-ihx
+LINKFLAGS += pdk13.lib
+
+OBJEXT = .rel
+BINEXT = .ihx
+
+# otherwise `make` deletes testfwk.rel and `make -j` will fail
+.PRECIOUS: $(PORT_CASES_DIR)/%$(OBJEXT)
+
+# Required extras
+EXTRAS = $(PORT_CASES_DIR)/testfwk$(OBJEXT) $(PORT_CASES_DIR)/support$(OBJEXT)
+include $(srcdir)/fwk/lib/spec.mk
+
+# Rule to link into .ihx
+%$(BINEXT): %$(OBJEXT) $(EXTRAS) $(FWKLIB) $(PORT_CASES_DIR)/fwk.lib
+	$(SDCC) $(SDCCFLAGS) $(LINKFLAGS) $(EXTRAS) $(PORT_CASES_DIR)/fwk.lib $< -o $@
+
+%$(OBJEXT): %.asm
+	$(AS) -plosgff $<
+
+%$(OBJEXT): %.c
+	$(SDCC) $(SDCCFLAGS) -c $< -o $@
+
+$(PORT_CASES_DIR)/%$(OBJEXT): $(PORTS_DIR)/$(PORT)/%.c
+	$(SDCC) $(SDCCFLAGS) -c $< -o $@
+
+$(PORT_CASES_DIR)/%$(OBJEXT): $(srcdir)/fwk/lib/%.c
+	$(SDCC) $(SDCCFLAGS) -c $< -o $@
+
+$(PORT_CASES_DIR)/fwk.lib: $(srcdir)/fwk/lib/fwk.lib
+	cat < $(srcdir)/fwk/lib/fwk.lib > $@
+
+# run simulator with SIM_TIMEOUT seconds timeout
+%.out: %$(BINEXT) $(CASES_DIR)/timeout
+	mkdir -p $(dir $@)
+	-$(CASES_DIR)/timeout $(SIM_TIMEOUT) $(EMU) -tPDK13 $< < $(PORTS_DIR)/$(PORT)/uCsim.cmd > $@ \
+	  || echo -e --- FAIL: \"timeout, simulation killed\" in $(<:$(BINEXT)=.c)"\n"--- Summary: 1/1/1: timeout >> $@
+	$(PYTHON) $(srcdir)/get_ticks.py < $@ >> $@
+	-grep -n FAIL $@ /dev/null || true
+
+_clean:
diff -Nru sdcc-4.0.0+dfsg/support/regression/ports/pdk13/support.c sdcc-4.2.0+dfsg/support/regression/ports/pdk13/support.c
--- sdcc-4.0.0+dfsg/support/regression/ports/pdk13/support.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/ports/pdk13/support.c	2021-07-25 22:55:31.000000000 +0000
@@ -0,0 +1,39 @@
+__sfr __at 0x1f sif;
+
+void
+_putchar(unsigned char c)
+{
+  sif= 'p';
+  sif= c;
+  return;
+  c;
+#ifndef __SDCC_STACK_AUTO
+  __asm
+    mov a, __putchar_PARM_1+0
+    .db 0x00, 0xff
+  __endasm;
+#else
+  __asm
+    mov	a, sp
+    add	a, #0xfc
+    mov	p, a
+    idxm	a, p
+    .db 0x00, 0xff
+  __endasm;
+#endif
+}
+
+void
+_initEmu(void)
+{
+}
+
+void
+_exitEmu(void)
+{
+  sif= 's';
+  return;
+  __asm
+    stopsys
+  __endasm;
+}
diff -Nru sdcc-4.0.0+dfsg/support/regression/ports/pdk13/uCsim.cmd sdcc-4.2.0+dfsg/support/regression/ports/pdk13/uCsim.cmd
--- sdcc-4.0.0+dfsg/support/regression/ports/pdk13/uCsim.cmd	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/ports/pdk13/uCsim.cmd	2021-07-25 22:55:31.000000000 +0000
@@ -0,0 +1,8 @@
+set error non-classified off
+set error unknown_code off
+set error memory off
+set error stack off
+set hw simif regs8 0x1f
+run
+state
+quit
diff -Nru sdcc-4.0.0+dfsg/support/regression/ports/pdk14/spec.mk sdcc-4.2.0+dfsg/support/regression/ports/pdk14/spec.mk
--- sdcc-4.0.0+dfsg/support/regression/ports/pdk14/spec.mk	2019-03-04 18:48:58.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/ports/pdk14/spec.mk	2021-09-23 13:51:50.000000000 +0000
@@ -5,15 +5,15 @@
 
 # path to uCsim
 ifdef SDCC_BIN_PATH
-  UCPDK14C = $(SDCC_BIN_PATH)/spdk$(EXEEXT)
+  UCPDK14C = $(SDCC_BIN_PATH)/ucsim_pdk$(EXEEXT)
 
   AS_PDK14C = $(SDCC_BIN_PATH)/sdaspdk$(EXEEXT)
 else
   ifdef UCSIM_DIR
-    UCPDK14A = $(UCSIM_DIR)/pdk.src/spdk$(EXEEXT)
+    UCPDK14A = $(UCSIM_DIR)/pdk.src/ucsim_pdk$(EXEEXT)
   else
-    UCPDK14A = $(top_builddir)/sim/ucsim/pdk.src/spdk$(EXEEXT)
-    UCPDK14B = $(top_builddir)/bin/spdk$(EXEEXT)
+    UCPDK14A = $(top_builddir)/sim/ucsim/pdk.src/ucsim_pdk$(EXEEXT)
+    UCPDK14B = $(top_builddir)/bin/ucsim_pdk$(EXEEXT)
   endif
 
   EMU = $(WINE) $(shell if [ -f $(UCPDK14A) ]; then echo $(UCPDK14A); else echo $(UCPDK14B); fi)
diff -Nru sdcc-4.0.0+dfsg/support/regression/ports/pdk14/support.c sdcc-4.2.0+dfsg/support/regression/ports/pdk14/support.c
--- sdcc-4.0.0+dfsg/support/regression/ports/pdk14/support.c	2019-09-24 15:36:05.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/ports/pdk14/support.c	2021-05-20 09:02:23.000000000 +0000
@@ -1,6 +1,11 @@
+__sfr __at 0x3f sif;
+
 void
 _putchar(unsigned char c)
 {
+  sif= 'p';
+  sif= c;
+  return;
   c;
 #ifndef __SDCC_STACK_AUTO
   __asm
@@ -26,6 +31,8 @@
 void
 _exitEmu(void)
 {
+  sif= 's';
+  return;
   __asm
     stopsys
   __endasm;
diff -Nru sdcc-4.0.0+dfsg/support/regression/ports/pdk14/uCsim.cmd sdcc-4.2.0+dfsg/support/regression/ports/pdk14/uCsim.cmd
--- sdcc-4.0.0+dfsg/support/regression/ports/pdk14/uCsim.cmd	2013-04-21 16:51:14.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/ports/pdk14/uCsim.cmd	2021-05-20 09:02:23.000000000 +0000
@@ -2,6 +2,7 @@
 set error unknown_code off
 set error memory off
 set error stack off
+set hw simif regs8 0x3f
 run
 state
 quit
diff -Nru sdcc-4.0.0+dfsg/support/regression/ports/pdk15/spec.mk sdcc-4.2.0+dfsg/support/regression/ports/pdk15/spec.mk
--- sdcc-4.0.0+dfsg/support/regression/ports/pdk15/spec.mk	2019-04-04 15:16:57.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/ports/pdk15/spec.mk	2021-09-23 13:51:50.000000000 +0000
@@ -5,15 +5,15 @@
 
 # path to uCsim
 ifdef SDCC_BIN_PATH
-  UCPDK15C = $(SDCC_BIN_PATH)/spdk$(EXEEXT)
+  UCPDK15C = $(SDCC_BIN_PATH)/ucsim_pdk$(EXEEXT)
 
   AS_PDK15C = $(SDCC_BIN_PATH)/sdaspdk$(EXEEXT)
 else
   ifdef UCSIM_DIR
-    UCPDK15A = $(UCSIM_DIR)/pdk.src/spdk$(EXEEXT)
+    UCPDK15A = $(UCSIM_DIR)/pdk.src/ucsim_pdk$(EXEEXT)
   else
-    UCPDK15A = $(top_builddir)/sim/ucsim/pdk.src/spdk$(EXEEXT)
-    UCPDK15B = $(top_builddir)/bin/spdk$(EXEEXT)
+    UCPDK15A = $(top_builddir)/sim/ucsim/pdk.src/ucsim_pdk$(EXEEXT)
+    UCPDK15B = $(top_builddir)/bin/ucsim_pdk$(EXEEXT)
   endif
 
   EMU = $(WINE) $(shell if [ -f $(UCPDK15A) ]; then echo $(UCPDK15A); else echo $(UCPDK15B); fi)
diff -Nru sdcc-4.0.0+dfsg/support/regression/ports/pdk15/support.c sdcc-4.2.0+dfsg/support/regression/ports/pdk15/support.c
--- sdcc-4.0.0+dfsg/support/regression/ports/pdk15/support.c	2019-09-24 15:36:05.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/ports/pdk15/support.c	2021-05-20 09:02:23.000000000 +0000
@@ -1,6 +1,11 @@
+__sfr __at 0x3f sif;
+
 void
 _putchar(unsigned char c)
 {
+  sif= 'p';
+  sif= c;
+  return;
   c;
 #ifndef __SDCC_STACK_AUTO
   __asm
@@ -26,6 +31,8 @@
 void
 _exitEmu(void)
 {
+  sif= 's';
+  return;
   __asm
     stopsys
   __endasm;
diff -Nru sdcc-4.0.0+dfsg/support/regression/ports/pdk15/uCsim.cmd sdcc-4.2.0+dfsg/support/regression/ports/pdk15/uCsim.cmd
--- sdcc-4.0.0+dfsg/support/regression/ports/pdk15/uCsim.cmd	2013-04-21 16:51:14.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/ports/pdk15/uCsim.cmd	2021-05-20 09:02:23.000000000 +0000
@@ -2,6 +2,7 @@
 set error unknown_code off
 set error memory off
 set error stack off
+set hw simif regs8 0x3f
 run
 state
 quit
diff -Nru sdcc-4.0.0+dfsg/support/regression/ports/pdk15-stack-auto/spec.mk sdcc-4.2.0+dfsg/support/regression/ports/pdk15-stack-auto/spec.mk
--- sdcc-4.0.0+dfsg/support/regression/ports/pdk15-stack-auto/spec.mk	2019-11-06 11:15:45.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/ports/pdk15-stack-auto/spec.mk	2021-09-23 13:51:50.000000000 +0000
@@ -5,15 +5,15 @@
 
 # path to uCsim
 ifdef SDCC_BIN_PATH
-  UCPDK15C = $(SDCC_BIN_PATH)/spdk$(EXEEXT)
+  UCPDK15C = $(SDCC_BIN_PATH)/ucsim_pdk$(EXEEXT)
 
   AS_PDK15C = $(SDCC_BIN_PATH)/sdaspdk$(EXEEXT)
 else
   ifdef UCSIM_DIR
-    UCPDK15A = $(UCSIM_DIR)/pdk.src/spdk$(EXEEXT)
+    UCPDK15A = $(UCSIM_DIR)/pdk.src/ucsim_pdk$(EXEEXT)
   else
-    UCPDK15A = $(top_builddir)/sim/ucsim/pdk.src/spdk$(EXEEXT)
-    UCPDK15B = $(top_builddir)/bin/spdk$(EXEEXT)
+    UCPDK15A = $(top_builddir)/sim/ucsim/pdk.src/ucsim_pdk$(EXEEXT)
+    UCPDK15B = $(top_builddir)/bin/ucsim_pdk$(EXEEXT)
   endif
 
   EMU = $(WINE) $(shell if [ -f $(UCPDK15A) ]; then echo $(UCPDK15A); else echo $(UCPDK15B); fi)
diff -Nru sdcc-4.0.0+dfsg/support/regression/ports/pdk15-stack-auto/support.c sdcc-4.2.0+dfsg/support/regression/ports/pdk15-stack-auto/support.c
--- sdcc-4.0.0+dfsg/support/regression/ports/pdk15-stack-auto/support.c	2019-09-24 15:36:05.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/ports/pdk15-stack-auto/support.c	2021-05-20 09:02:23.000000000 +0000
@@ -1,6 +1,11 @@
+__sfr __at 0x3f sif;
+
 void
 _putchar(unsigned char c)
 {
+  sif= 'p';
+  sif= c;
+  return;
   c;
 #ifndef __SDCC_STACK_AUTO
   __asm
@@ -26,6 +31,8 @@
 void
 _exitEmu(void)
 {
+  sif= 's';
+  return;
   __asm
     stopsys
   __endasm;
diff -Nru sdcc-4.0.0+dfsg/support/regression/ports/pdk15-stack-auto/uCsim.cmd sdcc-4.2.0+dfsg/support/regression/ports/pdk15-stack-auto/uCsim.cmd
--- sdcc-4.0.0+dfsg/support/regression/ports/pdk15-stack-auto/uCsim.cmd	2013-04-21 16:51:14.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/ports/pdk15-stack-auto/uCsim.cmd	2021-05-20 09:02:23.000000000 +0000
@@ -2,6 +2,7 @@
 set error unknown_code off
 set error memory off
 set error stack off
+set hw simif regs8 0x3f
 run
 state
 quit
diff -Nru sdcc-4.0.0+dfsg/support/regression/ports/rrz80/spec.mk sdcc-4.2.0+dfsg/support/regression/ports/rrz80/spec.mk
--- sdcc-4.0.0+dfsg/support/regression/ports/rrz80/spec.mk	2016-10-22 11:38:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/ports/rrz80/spec.mk	2021-09-25 12:02:20.000000000 +0000
@@ -7,7 +7,7 @@
 SDCCFLAGS += --nostdinc -I$(top_srcdir)
 LINKFLAGS += --nostdlib -L$(top_builddir)/device/lib/build/z80
 
-SDCCFLAGS += -mz80 --less-pedantic --profile
+SDCCFLAGS += -mz80 --less-pedantic
 LINKFLAGS += --out-fmt-ihx z80.lib
 
 OBJEXT = .rel
diff -Nru sdcc-4.0.0+dfsg/support/regression/ports/s08/spec.mk sdcc-4.2.0+dfsg/support/regression/ports/s08/spec.mk
--- sdcc-4.0.0+dfsg/support/regression/ports/s08/spec.mk	2018-08-22 12:51:20.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/ports/s08/spec.mk	2022-02-01 18:43:34.000000000 +0000
@@ -1,21 +1,21 @@
 # Regression test specification for the s08 target running with uCsim
 
 # simulation timeout in seconds
-SIM_TIMEOUT = 40
+SIM_TIMEOUT = 60
 
 EMU_PORT_FLAG=-thcs08
 
 # path to uCsim
 ifdef SDCC_BIN_PATH
-  UCHC08C = $(SDCC_BIN_PATH)/shc08$(EXEEXT)
+  UCHC08C = $(SDCC_BIN_PATH)/ucsim_hc08$(EXEEXT)
 
   AS_HC08C = $(SDCC_BIN_PATH)/sdas6808$(EXEEXT)
 else
   ifdef UCSIM_DIR
-    UCHC08A = $(UCSIM_DIR)/hc08.src/shc08$(EXEEXT)
+    UCHC08A = $(UCSIM_DIR)/m68hc08.src/ucsim_hc08$(EXEEXT)
   else
-    UCHC08A = $(top_builddir)/sim/ucsim/hc08.src/shc08$(EXEEXT)
-    UCHC08B = $(top_builddir)/bin/shc08$(EXEEXT)
+    UCHC08A = $(top_builddir)/sim/ucsim/m68hc08.src/ucsim_hc08$(EXEEXT)
+    UCHC08B = $(top_builddir)/bin/ucsim_hc08$(EXEEXT)
   endif
 
   EMU = $(WINE) $(shell if [ -f $(UCHC08A) ]; then echo $(UCHC08A); else echo $(UCHC08B); fi)
diff -Nru sdcc-4.0.0+dfsg/support/regression/ports/s08/support.c sdcc-4.2.0+dfsg/support/regression/ports/s08/support.c
--- sdcc-4.0.0+dfsg/support/regression/ports/s08/support.c	2010-01-15 13:26:59.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/ports/s08/support.c	2020-06-12 07:51:53.000000000 +0000
@@ -1,7 +1,11 @@
+static unsigned char * volatile sif;
 
 void
 _putchar(unsigned char c)
 {
+  *sif= 'p';
+  *sif= c;
+  return;
   c;
   __asm
     .db 0x9e, 0xed
@@ -11,11 +15,14 @@
 void
 _initEmu(void)
 {
+  sif= (unsigned char *)0x7f;
 }
 
 void
 _exitEmu(void)
 {
+  *sif= 's';
+  return;
   __asm
     .db 0x9e, 0xec
   __endasm;
diff -Nru sdcc-4.0.0+dfsg/support/regression/ports/s08/uCsim.cmd sdcc-4.2.0+dfsg/support/regression/ports/s08/uCsim.cmd
--- sdcc-4.0.0+dfsg/support/regression/ports/s08/uCsim.cmd	2005-12-07 12:49:32.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/ports/s08/uCsim.cmd	2020-06-12 07:51:53.000000000 +0000
@@ -2,6 +2,7 @@
 set error unknown_code off
 set error memory off
 set error stack off
+set hw simif rom 0x7f
 run
 state
 quit
diff -Nru sdcc-4.0.0+dfsg/support/regression/ports/stm8/spec.mk sdcc-4.2.0+dfsg/support/regression/ports/stm8/spec.mk
--- sdcc-4.0.0+dfsg/support/regression/ports/stm8/spec.mk	2017-03-27 09:02:05.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/ports/stm8/spec.mk	2022-02-01 18:43:34.000000000 +0000
@@ -1,19 +1,19 @@
 # Regression test specification for the stm8 target running with uCsim
 
 # simulation timeout in seconds
-SIM_TIMEOUT = 30
+SIM_TIMEOUT = 60
 
 # path to uCsim
 ifdef SDCC_BIN_PATH
-  UCSTM8C = $(SDCC_BIN_PATH)/sstm8$(EXEEXT)
+  UCSTM8C = $(SDCC_BIN_PATH)/ucsim_stm8$(EXEEXT)
 
   AS_STM8C = $(SDCC_BIN_PATH)/sdasstm8$(EXEEXT)
 else
   ifdef UCSIM_DIR
-    UCSTM8A = $(UCSIM_DIR)/stm8.src/sstm8$(EXEEXT)
+    UCSTM8A = $(UCSIM_DIR)/stm8.src/ucsim_stm8$(EXEEXT)
   else
-    UCSTM8A = $(top_builddir)/sim/ucsim/stm8.src/sstm8$(EXEEXT)
-    UCSTM8B = $(top_builddir)/bin/sstm8$(EXEEXT)
+    UCSTM8A = $(top_builddir)/sim/ucsim/stm8.src/ucsim_stm8$(EXEEXT)
+    UCSTM8B = $(top_builddir)/bin/ucsim_stm8$(EXEEXT)
   endif
 
   EMU = $(WINE) $(shell if [ -f $(UCSTM8A) ]; then echo $(UCSTM8A); else echo $(UCSTM8B); fi)
@@ -30,8 +30,8 @@
   SDCCFLAGS += -I$(top_srcdir)
 endif
 
-SDCCFLAGS += -mstm8 --less-pedantic --out-fmt-ihx
-LINKFLAGS += stm8.lib
+SDCCFLAGS += --debug -mstm8 --less-pedantic --out-fmt-ihx
+LINKFLAGS += --debug stm8.lib
 
 OBJEXT = .rel
 BINEXT = .ihx
@@ -65,7 +65,7 @@
 # run simulator with SIM_TIMEOUT seconds timeout
 %.out: %$(BINEXT) $(CASES_DIR)/timeout
 	mkdir -p $(dir $@)
-	-$(CASES_DIR)/timeout $(SIM_TIMEOUT) $(EMU) $< < $(PORTS_DIR)/$(PORT)/uCsim.cmd > $@ \
+	-$(CASES_DIR)/timeout $(SIM_TIMEOUT) $(EMU) -w $< < $(PORTS_DIR)/$(PORT)/uCsim.cmd > $@ \
 	  || echo -e --- FAIL: \"timeout, simulation killed\" in $(<:$(BINEXT)=.c)"\n"--- Summary: 1/1/1: timeout >> $@
 	$(PYTHON) $(srcdir)/get_ticks.py < $@ >> $@
 	-grep -n FAIL $@ /dev/null || true
diff -Nru sdcc-4.0.0+dfsg/support/regression/ports/stm8/support.c sdcc-4.2.0+dfsg/support/regression/ports/stm8/support.c
--- sdcc-4.0.0+dfsg/support/regression/ports/stm8/support.c	2013-05-15 10:03:50.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/ports/stm8/support.c	2021-05-20 07:41:51.000000000 +0000
@@ -1,6 +1,11 @@
+static unsigned char * volatile sif;
+
 void
 _putchar(unsigned char c)
 {
+  *sif= 'p';
+  *sif= c;
+  return;
   c;
   __asm
     ld	a, (0x03, sp)
@@ -11,11 +16,14 @@
 void
 _initEmu(void)
 {
+  sif= (unsigned char *)0x7fff;
 }
 
 void
 _exitEmu(void)
 {
+  *sif= 's';
+  return;
   __asm
     .db 0x71, 0xec
   __endasm;
diff -Nru sdcc-4.0.0+dfsg/support/regression/ports/stm8/uCsim.cmd sdcc-4.2.0+dfsg/support/regression/ports/stm8/uCsim.cmd
--- sdcc-4.0.0+dfsg/support/regression/ports/stm8/uCsim.cmd	2013-04-21 16:51:14.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/ports/stm8/uCsim.cmd	2021-05-20 07:41:51.000000000 +0000
@@ -2,6 +2,7 @@
 set error unknown_code off
 set error memory off
 set error stack off
+set hw simif rom 0x7fff
 run
 state
 quit
diff -Nru sdcc-4.0.0+dfsg/support/regression/ports/stm8-large/spec.mk sdcc-4.2.0+dfsg/support/regression/ports/stm8-large/spec.mk
--- sdcc-4.0.0+dfsg/support/regression/ports/stm8-large/spec.mk	2018-03-24 17:20:58.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/ports/stm8-large/spec.mk	2022-02-01 18:43:34.000000000 +0000
@@ -1,19 +1,19 @@
 # Regression test specification for the stm8-large target running with uCsim
 
 # simulation timeout in seconds
-SIM_TIMEOUT = 30
+SIM_TIMEOUT = 60
 
 # path to uCsim
 ifdef SDCC_BIN_PATH
-  UCSTM8C = $(SDCC_BIN_PATH)/sstm8$(EXEEXT)
+  UCSTM8C = $(SDCC_BIN_PATH)/ucsim_stm8$(EXEEXT)
 
   AS_STM8C = $(SDCC_BIN_PATH)/sdasstm8$(EXEEXT)
 else
   ifdef UCSIM_DIR
-    UCSTM8A = $(UCSIM_DIR)/stm8.src/sstm8$(EXEEXT)
+    UCSTM8A = $(UCSIM_DIR)/stm8.src/ucsim_stm8$(EXEEXT)
   else
-    UCSTM8A = $(top_builddir)/sim/ucsim/stm8.src/sstm8$(EXEEXT)
-    UCSTM8B = $(top_builddir)/bin/sstm8$(EXEEXT)
+    UCSTM8A = $(top_builddir)/sim/ucsim/stm8.src/ucsim_stm8$(EXEEXT)
+    UCSTM8B = $(top_builddir)/bin/ucsim_stm8$(EXEEXT)
   endif
 
   EMU = $(WINE) $(shell if [ -f $(UCSTM8A) ]; then echo $(UCSTM8A); else echo $(UCSTM8B); fi)
diff -Nru sdcc-4.0.0+dfsg/support/regression/ports/stm8-large/support.c sdcc-4.2.0+dfsg/support/regression/ports/stm8-large/support.c
--- sdcc-4.0.0+dfsg/support/regression/ports/stm8-large/support.c	2018-03-25 13:52:55.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/ports/stm8-large/support.c	2021-05-20 07:41:51.000000000 +0000
@@ -1,6 +1,11 @@
+static unsigned char * volatile sif;
+
 void
 _putchar(unsigned char c)
 {
+  *sif= 'p';
+  *sif= c;
+  return;
   c;
   __asm
     ld	a, (0x04, sp)
@@ -11,11 +16,14 @@
 void
 _initEmu(void)
 {
+  sif= (unsigned char *)0x7fff;
 }
 
 void
 _exitEmu(void)
 {
+  *sif= 's';
+  return;
   __asm
     .db 0x71, 0xec
   __endasm;
diff -Nru sdcc-4.0.0+dfsg/support/regression/ports/stm8-large/uCsim.cmd sdcc-4.2.0+dfsg/support/regression/ports/stm8-large/uCsim.cmd
--- sdcc-4.0.0+dfsg/support/regression/ports/stm8-large/uCsim.cmd	2013-04-21 16:51:14.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/ports/stm8-large/uCsim.cmd	2021-05-20 07:41:51.000000000 +0000
@@ -2,6 +2,7 @@
 set error unknown_code off
 set error memory off
 set error stack off
+set hw simif rom 0x7fff
 run
 state
 quit
diff -Nru sdcc-4.0.0+dfsg/support/regression/ports/tlcs90/spec.mk sdcc-4.2.0+dfsg/support/regression/ports/tlcs90/spec.mk
--- sdcc-4.0.0+dfsg/support/regression/ports/tlcs90/spec.mk	2018-08-02 06:25:16.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/ports/tlcs90/spec.mk	2021-09-23 13:51:50.000000000 +0000
@@ -5,15 +5,15 @@
 
 # path to uCsim
 ifdef SDCC_BIN_PATH
-  UCTLCS90C = $(SDCC_BIN_PATH)/stlcs$(EXEEXT)
+  UCTLCS90C = $(SDCC_BIN_PATH)/ucsim_tlcs$(EXEEXT)
 
   AS_TLCS90C = $(SDCC_BIN_PATH)/sdastlcs90$(EXEEXT)
 else
   ifdef UCSIM_DIR
-    UCTLCS90A = $(UCSIM_DIR)/tlcs.src/stlcs$(EXEEXT)
+    UCTLCS90A = $(UCSIM_DIR)/tlcs.src/ucsim_tlcs$(EXEEXT)
   else
-    UCTLCS90A = $(top_builddir)/sim/ucsim/tlcs.src/stlcs$(EXEEXT)
-    UCTLCS90B = $(top_builddir)/bin/stlcs$(EXEEXT)
+    UCTLCS90A = $(top_builddir)/sim/ucsim/tlcs.src/ucsim_tlcs$(EXEEXT)
+    UCTLCS90B = $(top_builddir)/bin/ucsim_tlcs$(EXEEXT)
   endif
 
   EMU = $(WINE) $(shell if [ -f $(UCTLCS90A) ]; then echo $(UCTLCS90A); else echo $(UCTLCS90B); fi)
diff -Nru sdcc-4.0.0+dfsg/support/regression/ports/uc6502/spec.mk sdcc-4.2.0+dfsg/support/regression/ports/uc6502/spec.mk
--- sdcc-4.0.0+dfsg/support/regression/ports/uc6502/spec.mk	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/ports/uc6502/spec.mk	2022-01-15 21:16:00.000000000 +0000
@@ -0,0 +1,69 @@
+# Regression test specification for the mos6502 target running with uCsim
+
+# simulation timeout in cycles
+SIM_CYCLES = 1000000000
+SIM_TIMEOUT = 30
+
+ifdef SDCC_BIN_PATH
+  AS = $(SDCC_BIN_PATH)/sdas6500$(EXEEXT)
+  UC65 = $(SDCC_BIN_PATH)/ucsim_mos6502$(EXEEXT)
+else
+  ifdef UCSIM_DIR
+    UC65 = $(UCSIM_DIR)/mos6502.src/ucsim_mos6502$(EXEEXT)
+  else
+    UC65 = $(top_builddir)/sim/ucsim/mos6502.src/ucsim_mos6502$(EXEEXT)
+  endif
+  AS = $(WINE) $(top_builddir)/bin/sdas6500$(EXEEXT)
+ifndef CROSSCOMPILING
+  SDCCFLAGS += --nostdinc -I$(top_srcdir)
+  LINKFLAGS += --nostdlib -L$(top_builddir)/device/lib/build/mos6502
+endif
+endif
+
+  EMU = $(WINE) $(UC65)
+
+ifdef CROSSCOMPILING
+  SDCCFLAGS += -I$(top_srcdir)
+endif
+
+SDCCFLAGS += -mmos6502 --less-pedantic --out-fmt-ihx --code-loc 0x200 --xram-loc 0xc000
+LINKFLAGS += mos6502.lib
+
+OBJEXT = .rel
+BINEXT = .ihx
+
+# otherwise `make` deletes testfwk.rel and `make -j` will fail
+.PRECIOUS: $(PORT_CASES_DIR)/%$(OBJEXT)
+
+# Required extras
+EXTRAS = $(PORT_CASES_DIR)/testfwk$(OBJEXT) $(PORT_CASES_DIR)/support$(OBJEXT)
+include $(srcdir)/fwk/lib/spec.mk
+
+# Rule to link into .ihx
+%$(BINEXT): %$(OBJEXT) $(EXTRAS) $(FWKLIB) $(PORT_CASES_DIR)/fwk.lib
+	$(SDCC) $(SDCCFLAGS) $(LINKFLAGS) $(EXTRAS) $(PORT_CASES_DIR)/fwk.lib $< -o $@
+
+%$(OBJEXT): %.asm
+	$(AS) -plosgff $<
+
+%$(OBJEXT): %.c
+	$(VALGRIND) $(SDCC) $(SDCCFLAGS) -c $< -o $@
+
+$(PORT_CASES_DIR)/%$(OBJEXT): $(PORTS_DIR)/$(PORT)/%.c
+	$(SDCC) $(SDCCFLAGS) -c $< -o $@
+
+$(PORT_CASES_DIR)/%$(OBJEXT): $(srcdir)/fwk/lib/%.c
+	$(SDCC) $(SDCCFLAGS) -c $< -o $@
+
+$(PORT_CASES_DIR)/fwk.lib: $(srcdir)/fwk/lib/fwk.lib
+	cat < $(srcdir)/fwk/lib/fwk.lib > $@
+
+# run simulator with SIM_TIMEOUT seconds timeout
+%.out: %$(BINEXT) $(CASES_DIR)/timeout
+	mkdir -p $(dir $@)
+	-$(CASES_DIR)/timeout $(SIM_TIMEOUT) $(EMU) $(EMU_PORT_FLAG) $< < $(PORTS_DIR)/$(PORT)/uCsim.cmd > $@ \
+	  || echo -e --- FAIL: \"timeout, simulation killed\" in $(<:$(BINEXT)=.c)"\n"--- Summary: 1/1/1: timeout >> $@
+	$(PYTHON) $(srcdir)/get_ticks.py < $@ >> $@
+	-grep -n FAIL $@ /dev/null || true
+
+_clean:
diff -Nru sdcc-4.0.0+dfsg/support/regression/ports/uc6502/support.c sdcc-4.2.0+dfsg/support/regression/ports/uc6502/support.c
--- sdcc-4.0.0+dfsg/support/regression/ports/uc6502/support.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/ports/uc6502/support.c	2021-11-20 19:18:53.000000000 +0000
@@ -0,0 +1,22 @@
+static unsigned char * volatile sif;
+
+void
+_putchar(unsigned char c)
+{
+  *sif= 'p';
+  *sif= c;
+  return;
+}
+
+void
+_initEmu(void)
+{
+  sif= (unsigned char *)0xdfff;
+}
+
+void
+_exitEmu(void)
+{
+  *sif= 's';
+  return;
+}
diff -Nru sdcc-4.0.0+dfsg/support/regression/ports/uc6502/uCsim.cmd sdcc-4.2.0+dfsg/support/regression/ports/uc6502/uCsim.cmd
--- sdcc-4.0.0+dfsg/support/regression/ports/uc6502/uCsim.cmd	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/ports/uc6502/uCsim.cmd	2021-11-20 19:18:53.000000000 +0000
@@ -0,0 +1,8 @@
+set error non-classified off
+set error unknown_code off
+set error memory off
+set error stack off
+set hw simif rom 0xdfff
+run
+state
+quit
diff -Nru sdcc-4.0.0+dfsg/support/regression/ports/ucgbz80/spec.mk sdcc-4.2.0+dfsg/support/regression/ports/ucgbz80/spec.mk
--- sdcc-4.0.0+dfsg/support/regression/ports/ucgbz80/spec.mk	2018-08-02 06:25:16.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/ports/ucgbz80/spec.mk	2022-02-01 18:43:34.000000000 +0000
@@ -1,21 +1,21 @@
-# Regression test specification for the gbz80 target running with uCsim
+# Regression test specification for the sm83 target running with uCsim
 
 # simulation timeout in seconds
-SIM_TIMEOUT = 40
+SIM_TIMEOUT = 60
 
 EMU_PORT_FLAG=-tlr35902
 
 # path to uCsim
 ifdef SDCC_BIN_PATH
-  UCZ80C = $(SDCC_BIN_PATH)/sz80$(EXEEXT)
+  UCZ80C = $(SDCC_BIN_PATH)/ucsim_z80$(EXEEXT)
 
   AS_Z80C = $(SDCC_BIN_PATH)/sdasgb$(EXEEXT)
 else
   ifdef UCSIM_DIR
-    SZ80A = $(UCSIM_DIR)/z80.src/sz80$(EXEEXT)
+    SZ80A = $(UCSIM_DIR)/z80.src/ucsim_z80$(EXEEXT)
   else
-    SZ80A = $(top_builddir)/sim/ucsim/z80.src/sz80$(EXEEXT)
-    SZ80B = $(top_builddir)/bin/sz80$(EXEEXT)
+    SZ80A = $(top_builddir)/sim/ucsim/z80.src/ucsim_z80$(EXEEXT)
+    SZ80B = $(top_builddir)/bin/ucsim_z80$(EXEEXT)
   endif
 
   EMU = $(WINE) $(shell if [ -f $(SZ80A) ]; then echo $(SZ80A); else echo $(SZ80B); fi)
@@ -24,7 +24,7 @@
 
 ifndef CROSSCOMPILING
   SDCCFLAGS += --nostdinc -I$(top_srcdir)
-  LINKFLAGS += --nostdlib -L$(top_builddir)/device/lib/build/gbz80
+  LINKFLAGS += --nostdlib -L$(top_builddir)/device/lib/build/sm83
 endif
 endif
 
@@ -32,8 +32,8 @@
   SDCCFLAGS += -I$(top_srcdir)
 endif
 
-SDCCFLAGS += -mgbz80 --less-pedantic --profile
-LINKFLAGS += gbz80.lib
+SDCCFLAGS += -msm83 --less-pedantic
+LINKFLAGS += sm83.lib
 
 OBJEXT = .rel
 BINEXT = .ihx
diff -Nru sdcc-4.0.0+dfsg/support/regression/ports/ucgbz80/support.asm sdcc-4.2.0+dfsg/support/regression/ports/ucgbz80/support.asm
--- sdcc-4.0.0+dfsg/support/regression/ports/ucgbz80/support.asm	2016-06-16 12:01:50.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/ports/ucgbz80/support.asm	1970-01-01 00:00:00.000000000 +0000
@@ -1,16 +0,0 @@
-        .area   _CODE
-        .globl  _exit
-
-__putchar::
-		ld	hl, #2
-		add	hl, sp
-		ld	l, (hl)
-		ld	a, #1
-		rst	0x08
-		ret
-
-__initEmu::
-        ret
-
-__exitEmu::
-        jp      _exit
diff -Nru sdcc-4.0.0+dfsg/support/regression/ports/ucgbz80/support.c sdcc-4.2.0+dfsg/support/regression/ports/ucgbz80/support.c
--- sdcc-4.0.0+dfsg/support/regression/ports/ucgbz80/support.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/ports/ucgbz80/support.c	2020-06-09 19:35:59.000000000 +0000
@@ -0,0 +1,19 @@
+static unsigned char * volatile sif= (unsigned char *)0xbfff;
+
+void
+_putchar(unsigned char c)
+{
+  *sif= 'p';
+  *sif= c;
+}
+
+void
+_initEmu(void)
+{
+}
+
+void
+_exitEmu(void)
+{
+  *sif= 's';
+}
diff -Nru sdcc-4.0.0+dfsg/support/regression/ports/ucgbz80/uCsim.cmd sdcc-4.2.0+dfsg/support/regression/ports/ucgbz80/uCsim.cmd
--- sdcc-4.0.0+dfsg/support/regression/ports/ucgbz80/uCsim.cmd	2011-12-28 00:10:47.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/ports/ucgbz80/uCsim.cmd	2021-03-22 01:30:09.000000000 +0000
@@ -2,6 +2,8 @@
 set error unknown_code off
 set error memory off
 set error stack off
+set hw simif xram 0xbfff
+pc 0x100
 run
 state
 quit
diff -Nru sdcc-4.0.0+dfsg/support/regression/ports/ucr2k/spec.mk sdcc-4.2.0+dfsg/support/regression/ports/ucr2k/spec.mk
--- sdcc-4.0.0+dfsg/support/regression/ports/ucr2k/spec.mk	2018-08-02 06:25:16.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/ports/ucr2k/spec.mk	2021-11-17 08:35:03.000000000 +0000
@@ -7,15 +7,15 @@
 
 # path to uCsim
 ifdef SDCC_BIN_PATH
-  UCZ80C = $(SDCC_BIN_PATH)/sz80$(EXEEXT)
+  UCZ80C = $(SDCC_BIN_PATH)/ucsim_z80$(EXEEXT)
 
   AS_Z80C = $(SDCC_BIN_PATH)/sdasrab$(EXEEXT)
 else
   ifdef UCSIM_DIR
-    SZ80A = $(UCSIM_DIR)/z80.src/sz80$(EXEEXT)
+    SZ80A = $(UCSIM_DIR)/z80.src/ucsim_z80$(EXEEXT)
   else
-    SZ80A = $(top_builddir)/sim/ucsim/z80.src/sz80$(EXEEXT)
-    SZ80B = $(top_builddir)/bin/sz80$(EXEEXT)
+    SZ80A = $(top_builddir)/sim/ucsim/z80.src/ucsim_z80$(EXEEXT)
+    SZ80B = $(top_builddir)/bin/ucsim_z80$(EXEEXT)
   endif
 
   EMU = $(WINE) $(shell if [ -f $(SZ80A) ]; then echo $(SZ80A); else echo $(SZ80B); fi)
@@ -32,7 +32,7 @@
   SDCCFLAGS += -I$(top_srcdir)
 endif
 
-SDCCFLAGS += -mr2k --less-pedantic --profile
+SDCCFLAGS += -mr2k --less-pedantic
 LINKFLAGS += r2k.lib
 
 OBJEXT = .rel
diff -Nru sdcc-4.0.0+dfsg/support/regression/ports/ucr2k/support.asm sdcc-4.2.0+dfsg/support/regression/ports/ucr2k/support.asm
--- sdcc-4.0.0+dfsg/support/regression/ports/ucr2k/support.asm	2016-06-17 16:39:17.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/ports/ucr2k/support.asm	1970-01-01 00:00:00.000000000 +0000
@@ -1,16 +0,0 @@
-        .area   _CODE
-        .globl  _exit
-
-__putchar::
-		ld	hl, #2
-		add	hl, sp
-		ld	l, (hl)
-		ld	a, #1
-		rst	0x28
-		ret
-
-__initEmu::
-        ret
-
-__exitEmu::
-        jp      _exit
diff -Nru sdcc-4.0.0+dfsg/support/regression/ports/ucr2k/support.c sdcc-4.2.0+dfsg/support/regression/ports/ucr2k/support.c
--- sdcc-4.0.0+dfsg/support/regression/ports/ucr2k/support.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/ports/ucr2k/support.c	2020-06-09 19:35:59.000000000 +0000
@@ -0,0 +1,19 @@
+static unsigned char * volatile sif= (unsigned char *)0x7fff;
+
+void
+_putchar(unsigned char c)
+{
+  *sif= 'p';
+  *sif= c;
+}
+
+void
+_initEmu(void)
+{
+}
+
+void
+_exitEmu(void)
+{
+  *sif= 's';
+}
diff -Nru sdcc-4.0.0+dfsg/support/regression/ports/ucr2k/uCsim.cmd sdcc-4.2.0+dfsg/support/regression/ports/ucr2k/uCsim.cmd
--- sdcc-4.0.0+dfsg/support/regression/ports/ucr2k/uCsim.cmd	2011-10-09 18:21:10.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/ports/ucr2k/uCsim.cmd	2020-06-09 19:35:59.000000000 +0000
@@ -2,6 +2,7 @@
 set error unknown_code off
 set error memory off
 set error stack off
+set hw simif rom 0x7fff
 run
 state
 quit
diff -Nru sdcc-4.0.0+dfsg/support/regression/ports/ucr2ka/spec.mk sdcc-4.2.0+dfsg/support/regression/ports/ucr2ka/spec.mk
--- sdcc-4.0.0+dfsg/support/regression/ports/ucr2ka/spec.mk	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/ports/ucr2ka/spec.mk	2021-11-17 08:35:03.000000000 +0000
@@ -0,0 +1,78 @@
+# Regression test specification for the z80 target running with uCsim
+
+# simulation timeout in seconds
+SIM_TIMEOUT = 40
+
+EMU_PORT_FLAG=-tr2k
+
+# path to uCsim
+ifdef SDCC_BIN_PATH
+  UCZ80C = $(SDCC_BIN_PATH)/ucsim_z80$(EXEEXT)
+
+  AS_Z80C = $(SDCC_BIN_PATH)/sdasrab$(EXEEXT)
+else
+  ifdef UCSIM_DIR
+    SZ80A = $(UCSIM_DIR)/z80.src/ucsim_z80$(EXEEXT)
+  else
+    SZ80A = $(top_builddir)/sim/ucsim/z80.src/ucsim_z80$(EXEEXT)
+    SZ80B = $(top_builddir)/bin/ucsim_z80$(EXEEXT)
+  endif
+
+  EMU = $(WINE) $(shell if [ -f $(SZ80A) ]; then echo $(SZ80A); else echo $(SZ80B); fi)
+
+  AS = $(WINE) $(top_builddir)/bin/sdasrab$(EXEEXT)
+
+ifndef CROSSCOMPILING
+  SDCCFLAGS += --nostdinc -I$(top_srcdir)
+  LINKFLAGS += --nostdlib -L$(top_builddir)/device/lib/build/r2ka
+endif
+endif
+
+ifdef CROSSCOMPILING
+  SDCCFLAGS += -I$(top_srcdir)
+endif
+
+SDCCFLAGS += -mr2ka --less-pedantic
+LINKFLAGS += r2ka.lib
+
+OBJEXT = .rel
+BINEXT = .ihx
+
+# otherwise `make` deletes testfwk.rel and `make -j` will fail
+.PRECIOUS: $(PORT_CASES_DIR)/%$(OBJEXT)
+
+# Required extras
+EXTRAS = $(PORT_CASES_DIR)/testfwk$(OBJEXT) $(PORT_CASES_DIR)/support$(OBJEXT)
+include $(srcdir)/fwk/lib/spec.mk
+
+# Rule to link into .ihx
+%.ihx: %$(OBJEXT) $(EXTRAS) $(FWKLIB) $(PORT_CASES_DIR)/fwk.lib
+	$(SDCC) $(SDCCFLAGS) $(LINKFLAGS) $(EXTRAS) $(PORT_CASES_DIR)/fwk.lib $< -o $@
+
+$(PORT_CASES_DIR)/%$(OBJEXT): $(PORTS_DIR)/$(PORT)/%.asm
+	@# TODO: sdas should place it\'s output in the current dir
+	cp $< $(PORT_CASES_DIR)
+	$(AS) -plosgff $(PORT_CASES_DIR)/$(notdir $<)
+	rm $(PORT_CASES_DIR)/$(notdir $<)
+
+%$(OBJEXT): %.c
+	$(SDCC) $(SDCCFLAGS) -c $< -o $@
+
+$(PORT_CASES_DIR)/%$(OBJEXT): $(PORTS_DIR)/$(PORT)/%.c
+	$(SDCC) $(SDCCFLAGS) -c $< -o $@
+
+$(PORT_CASES_DIR)/%$(OBJEXT): $(srcdir)/fwk/lib/%.c
+	$(SDCC) $(SDCCFLAGS) -c $< -o $@
+
+$(PORT_CASES_DIR)/fwk.lib: $(srcdir)/fwk/lib/fwk.lib
+	cat < $(srcdir)/fwk/lib/fwk.lib > $@
+
+# run simulator with SIM_TIMEOUT seconds timeout
+%.out: %$(BINEXT) $(CASES_DIR)/timeout
+	mkdir -p $(dir $@)
+	-$(CASES_DIR)/timeout $(SIM_TIMEOUT) $(EMU) $(EMU_PORT_FLAG) $< < $(PORTS_DIR)/$(PORT)/uCsim.cmd > $@ \
+	  || echo -e --- FAIL: \"timeout, simulation killed\" in $(<:$(BINEXT)=.c)"\n"--- Summary: 1/1/1: timeout >> $@
+	$(PYTHON) $(srcdir)/get_ticks.py < $@ >> $@
+	-grep -n FAIL $@ /dev/null || true
+
+_clean:
diff -Nru sdcc-4.0.0+dfsg/support/regression/ports/ucr2ka/support.c sdcc-4.2.0+dfsg/support/regression/ports/ucr2ka/support.c
--- sdcc-4.0.0+dfsg/support/regression/ports/ucr2ka/support.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/ports/ucr2ka/support.c	2020-06-09 19:35:59.000000000 +0000
@@ -0,0 +1,19 @@
+static unsigned char * volatile sif= (unsigned char *)0x7fff;
+
+void
+_putchar(unsigned char c)
+{
+  *sif= 'p';
+  *sif= c;
+}
+
+void
+_initEmu(void)
+{
+}
+
+void
+_exitEmu(void)
+{
+  *sif= 's';
+}
diff -Nru sdcc-4.0.0+dfsg/support/regression/ports/ucr2ka/uCsim.cmd sdcc-4.2.0+dfsg/support/regression/ports/ucr2ka/uCsim.cmd
--- sdcc-4.0.0+dfsg/support/regression/ports/ucr2ka/uCsim.cmd	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/ports/ucr2ka/uCsim.cmd	2020-06-09 19:35:59.000000000 +0000
@@ -0,0 +1,8 @@
+set error non-classified off
+set error unknown_code off
+set error memory off
+set error stack off
+set hw simif rom 0x7fff
+run
+state
+quit
diff -Nru sdcc-4.0.0+dfsg/support/regression/ports/ucr3ka/spec.mk sdcc-4.2.0+dfsg/support/regression/ports/ucr3ka/spec.mk
--- sdcc-4.0.0+dfsg/support/regression/ports/ucr3ka/spec.mk	2018-08-02 06:25:16.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/ports/ucr3ka/spec.mk	2021-09-23 13:51:50.000000000 +0000
@@ -7,15 +7,15 @@
 
 # path to uCsim
 ifdef SDCC_BIN_PATH
-  UCZ80C = $(SDCC_BIN_PATH)/sz80$(EXEEXT)
+  UCZ80C = $(SDCC_BIN_PATH)/ucsim_z80$(EXEEXT)
 
   AS_Z80C = $(SDCC_BIN_PATH)/sdasrab$(EXEEXT)
 else
   ifdef UCSIM_DIR
-    SZ80A = $(UCSIM_DIR)/z80.src/sz80$(EXEEXT)
+    SZ80A = $(UCSIM_DIR)/z80.src/ucsim_z80$(EXEEXT)
   else
-    SZ80A = $(top_builddir)/sim/ucsim/z80.src/sz80$(EXEEXT)
-    SZ80B = $(top_builddir)/bin/sz80$(EXEEXT)
+    SZ80A = $(top_builddir)/sim/ucsim/z80.src/ucsim_z80$(EXEEXT)
+    SZ80B = $(top_builddir)/bin/ucsim_z80$(EXEEXT)
   endif
 
   EMU = $(WINE) $(shell if [ -f $(SZ80A) ]; then echo $(SZ80A); else echo $(SZ80B); fi)
@@ -32,7 +32,7 @@
   SDCCFLAGS += -I$(top_srcdir)
 endif
 
-SDCCFLAGS += -mr3ka --less-pedantic --profile
+SDCCFLAGS += -mr3ka --less-pedantic
 LINKFLAGS += r3ka.lib
 
 OBJEXT = .rel
diff -Nru sdcc-4.0.0+dfsg/support/regression/ports/ucr3ka/support.asm sdcc-4.2.0+dfsg/support/regression/ports/ucr3ka/support.asm
--- sdcc-4.0.0+dfsg/support/regression/ports/ucr3ka/support.asm	2016-06-16 12:01:50.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/ports/ucr3ka/support.asm	1970-01-01 00:00:00.000000000 +0000
@@ -1,15 +0,0 @@
-        .area   _CODE
-        .globl  _exit
-
-SADR=0xC0
-        
-__putchar::
-        ioi
-        ld      (SADR),a
-        ret
-
-__initEmu::
-        ret
-
-__exitEmu::
-        jp      _exit
diff -Nru sdcc-4.0.0+dfsg/support/regression/ports/ucr3ka/support.c sdcc-4.2.0+dfsg/support/regression/ports/ucr3ka/support.c
--- sdcc-4.0.0+dfsg/support/regression/ports/ucr3ka/support.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/ports/ucr3ka/support.c	2020-06-09 19:35:59.000000000 +0000
@@ -0,0 +1,19 @@
+static unsigned char * volatile sif= (unsigned char *)0x7fff;
+
+void
+_putchar(unsigned char c)
+{
+  *sif= 'p';
+  *sif= c;
+}
+
+void
+_initEmu(void)
+{
+}
+
+void
+_exitEmu(void)
+{
+  *sif= 's';
+}
diff -Nru sdcc-4.0.0+dfsg/support/regression/ports/ucr3ka/uCsim.cmd sdcc-4.2.0+dfsg/support/regression/ports/ucr3ka/uCsim.cmd
--- sdcc-4.0.0+dfsg/support/regression/ports/ucr3ka/uCsim.cmd	2012-05-21 02:54:59.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/ports/ucr3ka/uCsim.cmd	2020-06-09 19:35:59.000000000 +0000
@@ -2,6 +2,7 @@
 set error unknown_code off
 set error memory off
 set error stack off
+set hw simif rom 0x7fff
 run
 state
 quit
diff -Nru sdcc-4.0.0+dfsg/support/regression/ports/ucrxk3a/spec.mk sdcc-4.2.0+dfsg/support/regression/ports/ucrxk3a/spec.mk
--- sdcc-4.0.0+dfsg/support/regression/ports/ucrxk3a/spec.mk	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/ports/ucrxk3a/spec.mk	2021-09-26 11:09:51.000000000 +0000
@@ -0,0 +1,81 @@
+# Regression test specification for the z80 target running with uCsim
+
+# simulation timeout in seconds
+SIM_TIMEOUT = 40
+
+EMU_PORT_FLAG=-tr3ka
+
+# path to uCsim
+ifdef SDCC_BIN_PATH
+  UCZ80C = $(SDCC_BIN_PATH)/ucsim_rxk$(EXEEXT)
+
+  AS_Z80C = $(SDCC_BIN_PATH)/sdasrab$(EXEEXT)
+else
+  ifdef UCSIM_DIR
+    SZ80A = $(UCSIM_DIR)/rxk.src/ucsim_rxk$(EXEEXT)
+  else
+    SZ80A = $(top_builddir)/sim/ucsim/rxk.src/ucsim_rxk$(EXEEXT)
+    SZ80B = $(top_builddir)/bin/ucsim_rxk$(EXEEXT)
+  endif
+
+  EMU = $(WINE) $(shell if [ -f $(SZ80A) ]; then echo $(SZ80A); else echo $(SZ80B); fi)
+
+  AS = $(WINE) $(top_builddir)/bin/sdasrab$(EXEEXT)
+
+ifndef CROSSCOMPILING
+  SDCCFLAGS += --nostdinc -I$(top_srcdir)
+  LINKFLAGS += --nostdlib -L$(top_builddir)/device/lib/build/r3ka
+endif
+endif
+
+ifdef CROSSCOMPILING
+  SDCCFLAGS += -I$(top_srcdir)
+endif
+
+SDCCFLAGS += -mr3ka --less-pedantic
+LINKFLAGS += r3ka.lib
+
+OBJEXT = .rel
+BINEXT = .ihx
+
+# otherwise `make` deletes testfwk.rel and `make -j` will fail
+.PRECIOUS: $(PORT_CASES_DIR)/%$(OBJEXT)
+
+# Required extras
+EXTRAS = $(PORT_CASES_DIR)/testfwk$(OBJEXT) $(PORT_CASES_DIR)/support$(OBJEXT)
+include $(srcdir)/fwk/lib/spec.mk
+
+# Rule to link into .ihx
+%.ihx: %$(OBJEXT) $(EXTRAS) $(FWKLIB) $(PORT_CASES_DIR)/fwk.lib
+	$(SDCC) $(SDCCFLAGS) $(LINKFLAGS) $(EXTRAS) $(PORT_CASES_DIR)/fwk.lib $< -o $@
+
+$(PORT_CASES_DIR)/%$(OBJEXT): $(PORTS_DIR)/$(PORT)/%.asm
+	@# TODO: sdas should place it\'s output in the current dir
+	cp $< $(PORT_CASES_DIR)
+	$(AS) -plosgff $(PORT_CASES_DIR)/$(notdir $<)
+	rm $(PORT_CASES_DIR)/$(notdir $<)
+
+%$(OBJEXT): %.c
+	$(SDCC) $(SDCCFLAGS) -c $< -o $@
+
+$(PORT_CASES_DIR)/%$(OBJEXT): $(PORTS_DIR)/$(PORT)/%.c
+	$(SDCC) $(SDCCFLAGS) -c $< -o $@
+
+$(PORT_CASES_DIR)/%$(OBJEXT): $(srcdir)/fwk/lib/%.c
+	$(SDCC) $(SDCCFLAGS) -c $< -o $@
+
+$(PORT_CASES_DIR)/fwk.lib: $(srcdir)/fwk/lib/fwk.lib
+	cat < $(srcdir)/fwk/lib/fwk.lib > $@
+
+# run simulator with SIM_TIMEOUT seconds timeout
+%.out: %$(BINEXT) $(CASES_DIR)/timeout
+	mkdir -p $(dir $@)
+	-$(CASES_DIR)/timeout $(SIM_TIMEOUT) $(EMU) $(EMU_PORT_FLAG) $< < $(PORTS_DIR)/$(PORT)/uCsim.cmd > $@ \
+	  || echo -e --- FAIL: \"timeout, simulation killed\" in $(<:$(BINEXT)=.c)"\n"--- Summary: 1/1/1: timeout >> $@
+	$(PYTHON) $(srcdir)/get_ticks.py < $@ >> $@
+	-grep -n FAIL $@ /dev/null || true
+
+
+#	echo Running $(CASES_DIR)/timeout $(SIM_TIMEOUT) $(EMU) $(EMU_PORT_FLAG) $< < $(PORTS_DIR)/$(PORT)/uCsim.cmd
+
+_clean:
diff -Nru sdcc-4.0.0+dfsg/support/regression/ports/ucrxk3a/support.c sdcc-4.2.0+dfsg/support/regression/ports/ucrxk3a/support.c
--- sdcc-4.0.0+dfsg/support/regression/ports/ucrxk3a/support.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/ports/ucrxk3a/support.c	2020-06-09 19:35:59.000000000 +0000
@@ -0,0 +1,19 @@
+static unsigned char * volatile sif= (unsigned char *)0x7fff;
+
+void
+_putchar(unsigned char c)
+{
+  *sif= 'p';
+  *sif= c;
+}
+
+void
+_initEmu(void)
+{
+}
+
+void
+_exitEmu(void)
+{
+  *sif= 's';
+}
diff -Nru sdcc-4.0.0+dfsg/support/regression/ports/ucrxk3a/uCsim.cmd sdcc-4.2.0+dfsg/support/regression/ports/ucrxk3a/uCsim.cmd
--- sdcc-4.0.0+dfsg/support/regression/ports/ucrxk3a/uCsim.cmd	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/ports/ucrxk3a/uCsim.cmd	2021-09-26 11:09:51.000000000 +0000
@@ -0,0 +1,9 @@
+set error non-classified off
+set error unknown_code off
+set error memory off
+set error stack off
+set hw simif rom 0x7fff
+expr IIR=1
+run
+state
+quit
diff -Nru sdcc-4.0.0+dfsg/support/regression/ports/ucz180/conf.cmd sdcc-4.2.0+dfsg/support/regression/ports/ucz180/conf.cmd
--- sdcc-4.0.0+dfsg/support/regression/ports/ucz180/conf.cmd	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/ports/ucz180/conf.cmd	2021-11-02 12:41:18.000000000 +0000
@@ -0,0 +1 @@
+fill rom 0 0xffff 0
diff -Nru sdcc-4.0.0+dfsg/support/regression/ports/ucz180/spec.mk sdcc-4.2.0+dfsg/support/regression/ports/ucz180/spec.mk
--- sdcc-4.0.0+dfsg/support/regression/ports/ucz180/spec.mk	2018-12-11 09:14:02.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/ports/ucz180/spec.mk	2021-11-02 12:41:18.000000000 +0000
@@ -5,15 +5,15 @@
 
 # path to uCsim
 ifdef SDCC_BIN_PATH
-  UCZ80C = $(SDCC_BIN_PATH)/sz80$(EXEEXT)
+  UCZ80C = $(SDCC_BIN_PATH)/ucsim_z80$(EXEEXT)
 
   AS_Z80C = $(SDCC_BIN_PATH)/sdasz80$(EXEEXT)
 else
   ifdef UCSIM_DIR
-    SZ80A = $(UCSIM_DIR)/z80.src/sz80$(EXEEXT)
+    SZ80A = $(UCSIM_DIR)/z80.src/ucsim_z80$(EXEEXT)
   else
-    SZ80A = $(top_builddir)/sim/ucsim/z80.src/sz80$(EXEEXT)
-    SZ80B = $(top_builddir)/bin/sz80$(EXEEXT)
+    SZ80A = $(top_builddir)/sim/ucsim/z80.src/ucsim_z80$(EXEEXT)
+    SZ80B = $(top_builddir)/bin/ucsim_z80$(EXEEXT)
   endif
 
   EMU = $(WINE) $(shell if [ -f $(SZ80A) ]; then echo $(SZ80A); else echo $(SZ80B); fi)
@@ -30,7 +30,7 @@
   SDCCFLAGS += -I$(top_srcdir)
 endif
 
-SDCCFLAGS += -mz180 --less-pedantic --profile
+SDCCFLAGS += -mz180 --less-pedantic
 LINKFLAGS += z180.lib
 
 OBJEXT = .rel
@@ -68,7 +68,7 @@
 # run simulator with SIM_TIMEOUT seconds timeout
 %.out: %$(BINEXT) $(CASES_DIR)/timeout
 	mkdir -p $(dir $@)
-	-$(CASES_DIR)/timeout $(SIM_TIMEOUT) $(EMU) -tz180 $< < $(PORTS_DIR)/$(PORT)/uCsim.cmd > $@ \
+	-$(CASES_DIR)/timeout $(SIM_TIMEOUT) $(EMU) -tz180 -C $(PORTS_DIR)/$(PORT)/conf.cmd $< < $(PORTS_DIR)/$(PORT)/uCsim.cmd > $@ \
 	  || echo -e --- FAIL: \"timeout, simulation killed\" in $(<:$(BINEXT)=.c)"\n"--- Summary: 1/1/1: timeout >> $@
 	$(PYTHON) $(srcdir)/get_ticks.py < $@ >> $@
 	-grep -n FAIL $@ /dev/null || true
diff -Nru sdcc-4.0.0+dfsg/support/regression/ports/ucz180/support.asm sdcc-4.2.0+dfsg/support/regression/ports/ucz180/support.asm
--- sdcc-4.0.0+dfsg/support/regression/ports/ucz180/support.asm	2016-06-16 12:01:50.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/ports/ucz180/support.asm	1970-01-01 00:00:00.000000000 +0000
@@ -1,16 +0,0 @@
-        .area   _CODE
-        .globl  _exit
-
-__putchar::
-		ld	hl, #2
-		add	hl, sp
-		ld	l, (hl)
-		ld	a, #1
-		rst	0x08
-		ret
-
-__initEmu::
-        ret
-
-__exitEmu::
-        jp      _exit
diff -Nru sdcc-4.0.0+dfsg/support/regression/ports/ucz180/support.c sdcc-4.2.0+dfsg/support/regression/ports/ucz180/support.c
--- sdcc-4.0.0+dfsg/support/regression/ports/ucz180/support.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/ports/ucz180/support.c	2021-05-20 13:17:39.000000000 +0000
@@ -0,0 +1,19 @@
+__sfr __at 0xff sif;
+
+void
+_putchar(unsigned char c)
+{
+  sif= 'p';
+  sif= c;
+}
+
+void
+_initEmu(void)
+{
+}
+
+void
+_exitEmu(void)
+{
+  sif= 's';
+}
diff -Nru sdcc-4.0.0+dfsg/support/regression/ports/ucz180/uCsim.cmd sdcc-4.2.0+dfsg/support/regression/ports/ucz180/uCsim.cmd
--- sdcc-4.0.0+dfsg/support/regression/ports/ucz180/uCsim.cmd	2011-09-24 18:55:19.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/ports/ucz180/uCsim.cmd	2021-05-20 13:17:39.000000000 +0000
@@ -2,6 +2,7 @@
 set error unknown_code off
 set error memory off
 set error stack off
+set hw simif outputs 0xff
 run
 state
 quit
diff -Nru sdcc-4.0.0+dfsg/support/regression/ports/ucz180-resiy/conf.cmd sdcc-4.2.0+dfsg/support/regression/ports/ucz180-resiy/conf.cmd
--- sdcc-4.0.0+dfsg/support/regression/ports/ucz180-resiy/conf.cmd	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/ports/ucz180-resiy/conf.cmd	2021-11-05 06:46:07.000000000 +0000
@@ -0,0 +1 @@
+fill rom 0 0xffff 0
diff -Nru sdcc-4.0.0+dfsg/support/regression/ports/ucz180-resiy/spec.mk sdcc-4.2.0+dfsg/support/regression/ports/ucz180-resiy/spec.mk
--- sdcc-4.0.0+dfsg/support/regression/ports/ucz180-resiy/spec.mk	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/ports/ucz180-resiy/spec.mk	2021-11-05 06:46:07.000000000 +0000
@@ -0,0 +1,76 @@
+# Regression test specification for the z180 target running with uCsim
+
+# simulation timeout in seconds
+SIM_TIMEOUT = 40
+
+# path to uCsim
+ifdef SDCC_BIN_PATH
+  UCZ80C = $(SDCC_BIN_PATH)/ucsim_z80$(EXEEXT)
+
+  AS_Z80C = $(SDCC_BIN_PATH)/sdasz80$(EXEEXT)
+else
+  ifdef UCSIM_DIR
+    SZ80A = $(UCSIM_DIR)/z80.src/ucsim_z80$(EXEEXT)
+  else
+    SZ80A = $(top_builddir)/sim/ucsim/z80.src/ucsim_z80$(EXEEXT)
+    SZ80B = $(top_builddir)/bin/ucsim_z80$(EXEEXT)
+  endif
+
+  EMU = $(WINE) $(shell if [ -f $(SZ80A) ]; then echo $(SZ80A); else echo $(SZ80B); fi)
+
+  AS = $(WINE) $(top_builddir)/bin/sdasz80$(EXEEXT)
+
+ifndef CROSSCOMPILING
+  SDCCFLAGS += --nostdinc -I$(top_srcdir)
+  LINKFLAGS += --nostdlib -L$(top_builddir)/device/lib/build/z180
+endif
+endif
+
+ifdef CROSSCOMPILING
+  SDCCFLAGS += -I$(top_srcdir)
+endif
+
+SDCCFLAGS += -mz180 --less-pedantic --reserve-regs-iy
+LINKFLAGS += z180.lib
+
+OBJEXT = .rel
+BINEXT = .ihx
+
+# otherwise `make` deletes testfwk.rel and `make -j` will fail
+.PRECIOUS: $(PORT_CASES_DIR)/%$(OBJEXT)
+
+# Required extras
+EXTRAS = $(PORT_CASES_DIR)/testfwk$(OBJEXT) $(PORT_CASES_DIR)/support$(OBJEXT)
+include $(srcdir)/fwk/lib/spec.mk
+
+# Rule to link into .ihx
+%.ihx: %$(OBJEXT) $(EXTRAS) $(FWKLIB) $(PORT_CASES_DIR)/fwk.lib
+	$(SDCC) $(SDCCFLAGS) $(LINKFLAGS) $(EXTRAS) $(PORT_CASES_DIR)/fwk.lib $< -o $@
+
+$(PORT_CASES_DIR)/%$(OBJEXT): $(PORTS_DIR)/$(PORT)/%.asm
+	@# TODO: sdas should place it\'s output in the current dir
+	cp $< $(PORT_CASES_DIR)
+	$(AS) -plosgff $(PORT_CASES_DIR)/$(notdir $<)
+	rm $(PORT_CASES_DIR)/$(notdir $<)
+
+%$(OBJEXT): %.c
+	$(SDCC) $(SDCCFLAGS) -c $< -o $@
+
+$(PORT_CASES_DIR)/%$(OBJEXT): $(PORTS_DIR)/$(PORT)/%.c
+	$(SDCC) $(SDCCFLAGS) -c $< -o $@
+
+$(PORT_CASES_DIR)/%$(OBJEXT): $(srcdir)/fwk/lib/%.c
+	$(SDCC) $(SDCCFLAGS) -c $< -o $@
+
+$(PORT_CASES_DIR)/fwk.lib: $(srcdir)/fwk/lib/fwk.lib
+	cat < $(srcdir)/fwk/lib/fwk.lib > $@
+
+# run simulator with SIM_TIMEOUT seconds timeout
+%.out: %$(BINEXT) $(CASES_DIR)/timeout
+	mkdir -p $(dir $@)
+	-$(CASES_DIR)/timeout $(SIM_TIMEOUT) $(EMU) -tz180 -C $(PORTS_DIR)/$(PORT)/conf.cmd $< < $(PORTS_DIR)/$(PORT)/uCsim.cmd > $@ \
+	  || echo -e --- FAIL: \"timeout, simulation killed\" in $(<:$(BINEXT)=.c)"\n"--- Summary: 1/1/1: timeout >> $@
+	$(PYTHON) $(srcdir)/get_ticks.py < $@ >> $@
+	-grep -n FAIL $@ /dev/null || true
+
+_clean:
diff -Nru sdcc-4.0.0+dfsg/support/regression/ports/ucz180-resiy/support.c sdcc-4.2.0+dfsg/support/regression/ports/ucz180-resiy/support.c
--- sdcc-4.0.0+dfsg/support/regression/ports/ucz180-resiy/support.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/ports/ucz180-resiy/support.c	2021-05-20 13:17:39.000000000 +0000
@@ -0,0 +1,19 @@
+__sfr __at 0xff sif;
+
+void
+_putchar(unsigned char c)
+{
+  sif= 'p';
+  sif= c;
+}
+
+void
+_initEmu(void)
+{
+}
+
+void
+_exitEmu(void)
+{
+  sif= 's';
+}
diff -Nru sdcc-4.0.0+dfsg/support/regression/ports/ucz180-resiy/uCsim.cmd sdcc-4.2.0+dfsg/support/regression/ports/ucz180-resiy/uCsim.cmd
--- sdcc-4.0.0+dfsg/support/regression/ports/ucz180-resiy/uCsim.cmd	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/ports/ucz180-resiy/uCsim.cmd	2021-05-20 13:17:39.000000000 +0000
@@ -0,0 +1,8 @@
+set error non-classified off
+set error unknown_code off
+set error memory off
+set error stack off
+set hw simif outputs 0xff
+run
+state
+quit
diff -Nru sdcc-4.0.0+dfsg/support/regression/ports/ucz80/conf.cmd sdcc-4.2.0+dfsg/support/regression/ports/ucz80/conf.cmd
--- sdcc-4.0.0+dfsg/support/regression/ports/ucz80/conf.cmd	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/ports/ucz80/conf.cmd	2021-11-03 09:52:11.000000000 +0000
@@ -0,0 +1 @@
+fill rom 0 0xffff 0
diff -Nru sdcc-4.0.0+dfsg/support/regression/ports/ucz80/spec.mk sdcc-4.2.0+dfsg/support/regression/ports/ucz80/spec.mk
--- sdcc-4.0.0+dfsg/support/regression/ports/ucz80/spec.mk	2017-10-26 11:53:55.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/ports/ucz80/spec.mk	2022-02-01 18:43:34.000000000 +0000
@@ -1,19 +1,19 @@
 # Regression test specification for the z80 target running with uCsim
 
 # simulation timeout in seconds
-SIM_TIMEOUT = 40
+SIM_TIMEOUT = 60
 
 # path to uCsim
 ifdef SDCC_BIN_PATH
-  UCZ80C = $(SDCC_BIN_PATH)/sz80$(EXEEXT)
+  UCZ80C = $(SDCC_BIN_PATH)/ucsim_z80$(EXEEXT)
 
   AS_Z80C = $(SDCC_BIN_PATH)/sdasz80$(EXEEXT)
 else
   ifdef UCSIM_DIR
-    SZ80A = $(UCSIM_DIR)/z80.src/sz80$(EXEEXT)
+    SZ80A = $(UCSIM_DIR)/z80.src/ucsim_z80$(EXEEXT)
   else
-    SZ80A = $(top_builddir)/sim/ucsim/z80.src/sz80$(EXEEXT)
-    SZ80B = $(top_builddir)/bin/sz80$(EXEEXT)
+    SZ80A = $(top_builddir)/sim/ucsim/z80.src/ucsim_z80$(EXEEXT)
+    SZ80B = $(top_builddir)/bin/ucsim_z80$(EXEEXT)
   endif
 
   EMU = $(WINE) $(shell if [ -f $(SZ80A) ]; then echo $(SZ80A); else echo $(SZ80B); fi)
@@ -30,7 +30,7 @@
   SDCCFLAGS += -I$(top_srcdir)
 endif
 
-SDCCFLAGS += -mz80 --less-pedantic --profile
+SDCCFLAGS += -mz80 --less-pedantic
 LINKFLAGS += z80.lib
 
 OBJEXT = .rel
@@ -68,7 +68,7 @@
 # run simulator with SIM_TIMEOUT seconds timeout
 %.out: %$(BINEXT) $(CASES_DIR)/timeout
 	mkdir -p $(dir $@)
-	-$(CASES_DIR)/timeout $(SIM_TIMEOUT) $(EMU) $< < $(PORTS_DIR)/$(PORT)/uCsim.cmd > $@ \
+	-$(CASES_DIR)/timeout $(SIM_TIMEOUT) $(EMU) -C $(PORTS_DIR)/$(PORT)/conf.cmd $< < $(PORTS_DIR)/$(PORT)/uCsim.cmd > $@ \
 	  || echo -e --- FAIL: \"timeout, simulation killed\" in $(<:$(BINEXT)=.c)"\n"--- Summary: 1/1/1: timeout >> $@
 	$(PYTHON) $(srcdir)/get_ticks.py < $@ >> $@
 	-grep -n FAIL $@ /dev/null || true
diff -Nru sdcc-4.0.0+dfsg/support/regression/ports/ucz80/support.asm sdcc-4.2.0+dfsg/support/regression/ports/ucz80/support.asm
--- sdcc-4.0.0+dfsg/support/regression/ports/ucz80/support.asm	2016-06-16 12:01:50.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/ports/ucz80/support.asm	1970-01-01 00:00:00.000000000 +0000
@@ -1,16 +0,0 @@
-        .area   _CODE
-        .globl  _exit
-
-__putchar::
-		ld	hl, #2
-		add	hl, sp
-		ld	l, (hl)
-		ld	a, #1
-		rst	0x08
-		ret
-
-__initEmu::
-        ret
-
-__exitEmu::
-        jp      _exit
diff -Nru sdcc-4.0.0+dfsg/support/regression/ports/ucz80/support.c sdcc-4.2.0+dfsg/support/regression/ports/ucz80/support.c
--- sdcc-4.0.0+dfsg/support/regression/ports/ucz80/support.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/ports/ucz80/support.c	2021-05-20 13:17:39.000000000 +0000
@@ -0,0 +1,19 @@
+__sfr __at 0xff sif;
+
+void
+_putchar(unsigned char c)
+{
+  sif= 'p';
+  sif= c;
+}
+
+void
+_initEmu(void)
+{
+}
+
+void
+_exitEmu(void)
+{
+  sif= 's';
+}
diff -Nru sdcc-4.0.0+dfsg/support/regression/ports/ucz80/uCsim.cmd sdcc-4.2.0+dfsg/support/regression/ports/ucz80/uCsim.cmd
--- sdcc-4.0.0+dfsg/support/regression/ports/ucz80/uCsim.cmd	2007-04-29 20:33:44.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/ports/ucz80/uCsim.cmd	2021-05-20 13:17:39.000000000 +0000
@@ -2,6 +2,7 @@
 set error unknown_code off
 set error memory off
 set error stack off
+set hw simif outputs 0xff
 run
 state
 quit
diff -Nru sdcc-4.0.0+dfsg/support/regression/ports/ucz80n/conf.cmd sdcc-4.2.0+dfsg/support/regression/ports/ucz80n/conf.cmd
--- sdcc-4.0.0+dfsg/support/regression/ports/ucz80n/conf.cmd	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/ports/ucz80n/conf.cmd	2021-11-04 09:01:17.000000000 +0000
@@ -0,0 +1 @@
+fill rom 0 0xffff 0
diff -Nru sdcc-4.0.0+dfsg/support/regression/ports/ucz80n/spec.mk sdcc-4.2.0+dfsg/support/regression/ports/ucz80n/spec.mk
--- sdcc-4.0.0+dfsg/support/regression/ports/ucz80n/spec.mk	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/ports/ucz80n/spec.mk	2022-02-01 18:43:34.000000000 +0000
@@ -0,0 +1,76 @@
+# Regression test specification for the z80 target running with uCsim
+
+# simulation timeout in seconds
+SIM_TIMEOUT = 60
+
+# path to uCsim
+ifdef SDCC_BIN_PATH
+  UCZ80C = $(SDCC_BIN_PATH)/ucsim_z80$(EXEEXT)
+
+  AS_Z80C = $(SDCC_BIN_PATH)/sdasz80$(EXEEXT)
+else
+  ifdef UCSIM_DIR
+    SZ80A = $(UCSIM_DIR)/z80.src/ucsim_z80$(EXEEXT)
+  else
+    SZ80A = $(top_builddir)/sim/ucsim/z80.src/ucsim_z80$(EXEEXT)
+    SZ80B = $(top_builddir)/bin/ucsim_z80$(EXEEXT)
+  endif
+
+  EMU = $(WINE) $(shell if [ -f $(SZ80A) ]; then echo $(SZ80A); else echo $(SZ80B); fi)
+
+  AS = $(WINE) $(top_builddir)/bin/sdasz80$(EXEEXT)
+
+ifndef CROSSCOMPILING
+  SDCCFLAGS += --nostdinc -I$(top_srcdir)
+  LINKFLAGS += --nostdlib -L$(top_builddir)/device/lib/build/z80n
+endif
+endif
+
+ifdef CROSSCOMPILING
+  SDCCFLAGS += -I$(top_srcdir)
+endif
+
+SDCCFLAGS += -mz80n --less-pedantic
+LINKFLAGS += z80n.lib
+
+OBJEXT = .rel
+BINEXT = .ihx
+
+# otherwise `make` deletes testfwk.rel and `make -j` will fail
+.PRECIOUS: $(PORT_CASES_DIR)/%$(OBJEXT)
+
+# Required extras
+EXTRAS = $(PORT_CASES_DIR)/testfwk$(OBJEXT) $(PORT_CASES_DIR)/support$(OBJEXT)
+include $(srcdir)/fwk/lib/spec.mk
+
+# Rule to link into .ihx
+%.ihx: %$(OBJEXT) $(EXTRAS) $(FWKLIB) $(PORT_CASES_DIR)/fwk.lib
+	$(SDCC) $(SDCCFLAGS) $(LINKFLAGS) $(EXTRAS) $(PORT_CASES_DIR)/fwk.lib $< -o $@
+
+$(PORT_CASES_DIR)/%$(OBJEXT): $(PORTS_DIR)/$(PORT)/%.asm
+	@# TODO: sdas should place it\'s output in the current dir
+	cp $< $(PORT_CASES_DIR)
+	$(AS) -plosgff $(PORT_CASES_DIR)/$(notdir $<)
+	rm $(PORT_CASES_DIR)/$(notdir $<)
+
+%$(OBJEXT): %.c
+	$(SDCC) $(SDCCFLAGS) -c $< -o $@
+
+$(PORT_CASES_DIR)/%$(OBJEXT): $(PORTS_DIR)/$(PORT)/%.c
+	$(SDCC) $(SDCCFLAGS) -c $< -o $@
+
+$(PORT_CASES_DIR)/%$(OBJEXT): $(srcdir)/fwk/lib/%.c
+	$(SDCC) $(SDCCFLAGS) -c $< -o $@
+
+$(PORT_CASES_DIR)/fwk.lib: $(srcdir)/fwk/lib/fwk.lib
+	cat < $(srcdir)/fwk/lib/fwk.lib > $@
+
+# run simulator with SIM_TIMEOUT seconds timeout
+%.out: %$(BINEXT) $(CASES_DIR)/timeout
+	mkdir -p $(dir $@)
+	-$(CASES_DIR)/timeout $(SIM_TIMEOUT) $(EMU) -tz80n -C $(PORTS_DIR)/$(PORT)/conf.cmd $< < $(PORTS_DIR)/$(PORT)/uCsim.cmd > $@ \
+	  || echo -e --- FAIL: \"timeout, simulation killed\" in $(<:$(BINEXT)=.c)"\n"--- Summary: 1/1/1: timeout >> $@
+	$(PYTHON) $(srcdir)/get_ticks.py < $@ >> $@
+	-grep -n FAIL $@ /dev/null || true
+
+_clean:
diff -Nru sdcc-4.0.0+dfsg/support/regression/ports/ucz80n/support.c sdcc-4.2.0+dfsg/support/regression/ports/ucz80n/support.c
--- sdcc-4.0.0+dfsg/support/regression/ports/ucz80n/support.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/ports/ucz80n/support.c	2021-05-20 13:17:39.000000000 +0000
@@ -0,0 +1,19 @@
+__sfr __at 0xff sif;
+
+void
+_putchar(unsigned char c)
+{
+  sif= 'p';
+  sif= c;
+}
+
+void
+_initEmu(void)
+{
+}
+
+void
+_exitEmu(void)
+{
+  sif= 's';
+}
diff -Nru sdcc-4.0.0+dfsg/support/regression/ports/ucz80n/uCsim.cmd sdcc-4.2.0+dfsg/support/regression/ports/ucz80n/uCsim.cmd
--- sdcc-4.0.0+dfsg/support/regression/ports/ucz80n/uCsim.cmd	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/ports/ucz80n/uCsim.cmd	2021-05-20 13:17:39.000000000 +0000
@@ -0,0 +1,8 @@
+set error non-classified off
+set error unknown_code off
+set error memory off
+set error stack off
+set hw simif outputs 0xff
+run
+state
+quit
diff -Nru sdcc-4.0.0+dfsg/support/regression/ports/ucz80-nmos/spec.mk sdcc-4.2.0+dfsg/support/regression/ports/ucz80-nmos/spec.mk
--- sdcc-4.0.0+dfsg/support/regression/ports/ucz80-nmos/spec.mk	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/ports/ucz80-nmos/spec.mk	2022-02-01 18:43:34.000000000 +0000
@@ -0,0 +1,76 @@
+# Regression test specification for the z80 target running with uCsim
+
+# simulation timeout in seconds
+SIM_TIMEOUT = 60
+
+# path to uCsim
+ifdef SDCC_BIN_PATH
+  UCZ80C = $(SDCC_BIN_PATH)/ucsim_z80$(EXEEXT)
+
+  AS_Z80C = $(SDCC_BIN_PATH)/sdasz80$(EXEEXT)
+else
+  ifdef UCSIM_DIR
+    SZ80A = $(UCSIM_DIR)/z80.src/ucsim_z80$(EXEEXT)
+  else
+    SZ80A = $(top_builddir)/sim/ucsim/z80.src/ucsim_z80$(EXEEXT)
+    SZ80B = $(top_builddir)/bin/ucsim_z80$(EXEEXT)
+  endif
+
+  EMU = $(WINE) $(shell if [ -f $(SZ80A) ]; then echo $(SZ80A); else echo $(SZ80B); fi)
+
+  AS = $(WINE) $(top_builddir)/bin/sdasz80$(EXEEXT)
+
+ifndef CROSSCOMPILING
+  SDCCFLAGS += --nostdinc -I$(top_srcdir)
+  LINKFLAGS += --nostdlib -L$(top_builddir)/device/lib/build/z80
+endif
+endif
+
+ifdef CROSSCOMPILING
+  SDCCFLAGS += -I$(top_srcdir)
+endif
+
+SDCCFLAGS += -mz80 --less-pedantic --nmos-z80
+LINKFLAGS += z80.lib
+
+OBJEXT = .rel
+BINEXT = .ihx
+
+# otherwise `make` deletes testfwk.rel and `make -j` will fail
+.PRECIOUS: $(PORT_CASES_DIR)/%$(OBJEXT)
+
+# Required extras
+EXTRAS = $(PORT_CASES_DIR)/testfwk$(OBJEXT) $(PORT_CASES_DIR)/support$(OBJEXT)
+include $(srcdir)/fwk/lib/spec.mk
+
+# Rule to link into .ihx
+%.ihx: %$(OBJEXT) $(EXTRAS) $(FWKLIB) $(PORT_CASES_DIR)/fwk.lib
+	$(SDCC) $(SDCCFLAGS) $(LINKFLAGS) $(EXTRAS) $(PORT_CASES_DIR)/fwk.lib $< -o $@
+
+$(PORT_CASES_DIR)/%$(OBJEXT): $(PORTS_DIR)/$(PORT)/%.asm
+	@# TODO: sdas should place it\'s output in the current dir
+	cp $< $(PORT_CASES_DIR)
+	$(AS) -plosgff $(PORT_CASES_DIR)/$(notdir $<)
+	rm $(PORT_CASES_DIR)/$(notdir $<)
+
+%$(OBJEXT): %.c
+	$(SDCC) $(SDCCFLAGS) -c $< -o $@
+
+$(PORT_CASES_DIR)/%$(OBJEXT): $(PORTS_DIR)/$(PORT)/%.c
+	$(SDCC) $(SDCCFLAGS) -c $< -o $@
+
+$(PORT_CASES_DIR)/%$(OBJEXT): $(srcdir)/fwk/lib/%.c
+	$(SDCC) $(SDCCFLAGS) -c $< -o $@
+
+$(PORT_CASES_DIR)/fwk.lib: $(srcdir)/fwk/lib/fwk.lib
+	cat < $(srcdir)/fwk/lib/fwk.lib > $@
+
+# run simulator with SIM_TIMEOUT seconds timeout
+%.out: %$(BINEXT) $(CASES_DIR)/timeout
+	mkdir -p $(dir $@)
+	-$(CASES_DIR)/timeout $(SIM_TIMEOUT) $(EMU) $< < $(PORTS_DIR)/$(PORT)/uCsim.cmd > $@ \
+	  || echo -e --- FAIL: \"timeout, simulation killed\" in $(<:$(BINEXT)=.c)"\n"--- Summary: 1/1/1: timeout >> $@
+	$(PYTHON) $(srcdir)/get_ticks.py < $@ >> $@
+	-grep -n FAIL $@ /dev/null || true
+
+_clean:
diff -Nru sdcc-4.0.0+dfsg/support/regression/ports/ucz80-nmos/support.c sdcc-4.2.0+dfsg/support/regression/ports/ucz80-nmos/support.c
--- sdcc-4.0.0+dfsg/support/regression/ports/ucz80-nmos/support.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/ports/ucz80-nmos/support.c	2021-05-20 13:17:39.000000000 +0000
@@ -0,0 +1,19 @@
+__sfr __at 0xff sif;
+
+void
+_putchar(unsigned char c)
+{
+  sif= 'p';
+  sif= c;
+}
+
+void
+_initEmu(void)
+{
+}
+
+void
+_exitEmu(void)
+{
+  sif= 's';
+}
diff -Nru sdcc-4.0.0+dfsg/support/regression/ports/ucz80-nmos/uCsim.cmd sdcc-4.2.0+dfsg/support/regression/ports/ucz80-nmos/uCsim.cmd
--- sdcc-4.0.0+dfsg/support/regression/ports/ucz80-nmos/uCsim.cmd	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/ports/ucz80-nmos/uCsim.cmd	2021-05-20 13:17:39.000000000 +0000
@@ -0,0 +1,8 @@
+set error non-classified off
+set error unknown_code off
+set error memory off
+set error stack off
+set hw simif outputs 0xff
+run
+state
+quit
diff -Nru sdcc-4.0.0+dfsg/support/regression/ports/ucz80-resiy/conf.cmd sdcc-4.2.0+dfsg/support/regression/ports/ucz80-resiy/conf.cmd
--- sdcc-4.0.0+dfsg/support/regression/ports/ucz80-resiy/conf.cmd	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/ports/ucz80-resiy/conf.cmd	2021-11-04 12:01:01.000000000 +0000
@@ -0,0 +1 @@
+fill rom 0 0xffff 0
diff -Nru sdcc-4.0.0+dfsg/support/regression/ports/ucz80-resiy/spec.mk sdcc-4.2.0+dfsg/support/regression/ports/ucz80-resiy/spec.mk
--- sdcc-4.0.0+dfsg/support/regression/ports/ucz80-resiy/spec.mk	2017-10-29 09:36:13.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/ports/ucz80-resiy/spec.mk	2022-02-01 18:43:34.000000000 +0000
@@ -1,19 +1,19 @@
 # Regression test specification for the z80 target running with uCsim
 
 # simulation timeout in seconds
-SIM_TIMEOUT = 40
+SIM_TIMEOUT = 60
 
 # path to uCsim
 ifdef SDCC_BIN_PATH
-  UCZ80C = $(SDCC_BIN_PATH)/sz80$(EXEEXT)
+  UCZ80C = $(SDCC_BIN_PATH)/ucsim_z80$(EXEEXT)
 
   AS_Z80C = $(SDCC_BIN_PATH)/sdasz80$(EXEEXT)
 else
   ifdef UCSIM_DIR
-    SZ80A = $(UCSIM_DIR)/z80.src/sz80$(EXEEXT)
+    SZ80A = $(UCSIM_DIR)/z80.src/ucsim_z80$(EXEEXT)
   else
-    SZ80A = $(top_builddir)/sim/ucsim/z80.src/sz80$(EXEEXT)
-    SZ80B = $(top_builddir)/bin/sz80$(EXEEXT)
+    SZ80A = $(top_builddir)/sim/ucsim/z80.src/ucsim_z80$(EXEEXT)
+    SZ80B = $(top_builddir)/bin/ucsim_z80$(EXEEXT)
   endif
 
   EMU = $(WINE) $(shell if [ -f $(SZ80A) ]; then echo $(SZ80A); else echo $(SZ80B); fi)
@@ -30,7 +30,7 @@
   SDCCFLAGS += -I$(top_srcdir)
 endif
 
-SDCCFLAGS += -mz80 --less-pedantic --profile --reserve-regs-iy
+SDCCFLAGS += -mz80 --less-pedantic --reserve-regs-iy
 LINKFLAGS += z80.lib
 
 OBJEXT = .rel
@@ -68,7 +68,7 @@
 # run simulator with SIM_TIMEOUT seconds timeout
 %.out: %$(BINEXT) $(CASES_DIR)/timeout
 	mkdir -p $(dir $@)
-	-$(CASES_DIR)/timeout $(SIM_TIMEOUT) $(EMU) $< < $(PORTS_DIR)/$(PORT)/uCsim.cmd > $@ \
+	-$(CASES_DIR)/timeout $(SIM_TIMEOUT) $(EMU) -C $(PORTS_DIR)/$(PORT)/conf.cmd $< < $(PORTS_DIR)/$(PORT)/uCsim.cmd > $@ \
 	  || echo -e --- FAIL: \"timeout, simulation killed\" in $(<:$(BINEXT)=.c)"\n"--- Summary: 1/1/1: timeout >> $@
 	$(PYTHON) $(srcdir)/get_ticks.py < $@ >> $@
 	-grep -n FAIL $@ /dev/null || true
diff -Nru sdcc-4.0.0+dfsg/support/regression/ports/ucz80-resiy/support.asm sdcc-4.2.0+dfsg/support/regression/ports/ucz80-resiy/support.asm
--- sdcc-4.0.0+dfsg/support/regression/ports/ucz80-resiy/support.asm	2016-06-16 12:01:50.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/ports/ucz80-resiy/support.asm	1970-01-01 00:00:00.000000000 +0000
@@ -1,16 +0,0 @@
-        .area   _CODE
-        .globl  _exit
-
-__putchar::
-		ld	hl, #2
-		add	hl, sp
-		ld	l, (hl)
-		ld	a, #1
-		rst	0x08
-		ret
-
-__initEmu::
-        ret
-
-__exitEmu::
-        jp      _exit
diff -Nru sdcc-4.0.0+dfsg/support/regression/ports/ucz80-resiy/support.c sdcc-4.2.0+dfsg/support/regression/ports/ucz80-resiy/support.c
--- sdcc-4.0.0+dfsg/support/regression/ports/ucz80-resiy/support.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/ports/ucz80-resiy/support.c	2021-05-20 13:17:39.000000000 +0000
@@ -0,0 +1,19 @@
+__sfr __at 0xff sif;
+
+void
+_putchar(unsigned char c)
+{
+  sif= 'p';
+  sif= c;
+}
+
+void
+_initEmu(void)
+{
+}
+
+void
+_exitEmu(void)
+{
+  sif= 's';
+}
diff -Nru sdcc-4.0.0+dfsg/support/regression/ports/ucz80-resiy/uCsim.cmd sdcc-4.2.0+dfsg/support/regression/ports/ucz80-resiy/uCsim.cmd
--- sdcc-4.0.0+dfsg/support/regression/ports/ucz80-resiy/uCsim.cmd	2007-04-29 20:33:44.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/ports/ucz80-resiy/uCsim.cmd	2021-05-20 13:17:39.000000000 +0000
@@ -2,6 +2,7 @@
 set error unknown_code off
 set error memory off
 set error stack off
+set hw simif outputs 0xff
 run
 state
 quit
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/addrspace.c sdcc-4.2.0+dfsg/support/regression/tests/addrspace.c
--- sdcc-4.0.0+dfsg/support/regression/tests/addrspace.c	2013-09-09 08:58:43.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/addrspace.c	2020-04-25 14:03:43.000000000 +0000
@@ -1,7 +1,7 @@
-/** addrsapce.c
+/** addrspace.c
 */
+
 #include 
-#include 
 
 void set_a(void)
 {
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/atomic.c sdcc-4.2.0+dfsg/support/regression/tests/atomic.c
--- sdcc-4.0.0+dfsg/support/regression/tests/atomic.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/atomic.c	2020-08-11 15:39:22.000000000 +0000
@@ -0,0 +1,39 @@
+/** atomic.c
+*/
+#include 
+
+// Some ports do not have atomic_flag yet.
+#if !defined(__SDCC_pic14) && !defined(__SDCC_pic16) && !defined(__SDCC_pdk13) && !defined(__SDCC_pdk14) && !defined(__SDCC_pdk15)
+
+#include 
+#include 
+
+#if (defined(__SDCC_mcs51) && !defined(__SDCC_MODEL_SMALL)) || defined(__SDCC_ds390)
+#define memory __idata	/* mcs51 atomic_flag must be in __data or __idata */
+#else
+#define memory
+#endif
+
+memory atomic_flag f1 = ATOMIC_FLAG_INIT;
+memory atomic_flag f2;
+memory struct { int a; atomic_flag f; } s = {0, ATOMIC_FLAG_INIT};
+
+#endif
+
+void testAtomic(void)
+{
+#if !defined(__SDCC_pic14) && !defined(__SDCC_pic16) && !defined(__SDCC_pdk13) && !defined(__SDCC_pdk14) && !defined(__SDCC_pdk15)
+	ASSERT(atomic_flag_test_and_set(&f1) == false);
+	ASSERT(atomic_flag_test_and_set(&f1) == true);
+	atomic_flag_clear(&f1);
+	atomic_flag_clear(&f2);
+	ASSERT(atomic_flag_test_and_set(&f1) == false);
+	ASSERT(atomic_flag_test_and_set(&f2) == false);
+
+	ASSERT(atomic_flag_test_and_set(&s.f) == false);
+	ASSERT(atomic_flag_test_and_set(&s.f) == true);
+	atomic_flag_clear(&s.f);
+	ASSERT(atomic_flag_test_and_set(&s.f) == false);
+#endif
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/banked.c sdcc-4.2.0+dfsg/support/regression/tests/banked.c
--- sdcc-4.0.0+dfsg/support/regression/tests/banked.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/banked.c	2021-12-27 11:03:23.000000000 +0000
@@ -0,0 +1,70 @@
+/* banked.c
+   returntype: char, int, long
+*/
+#include 
+
+#if defined(__SDCC_z80) || defined(__SDCC_z80n) || defined(__SDCC_z180) /*|| defined(__SDCC_sm83)*/ || defined(__SDCC_ez80_z80)
+#define DO_CHECK
+#endif
+
+static unsigned char bank;
+#ifdef DO_CHECK
+{returntype} c_ab(unsigned a, unsigned b) __banked;
+{returntype} f_ab(unsigned a) __banked __z88dk_fastcall;
+{returntype} c_51(unsigned a, unsigned b) __banked;
+{returntype} f_51(unsigned a) __banked __z88dk_fastcall;
+#endif
+
+void
+testBanked(void)
+{
+    ASSERT (bank == 0);
+#ifdef DO_CHECK
+    ASSERT (c_ab(0x0e, 0x4) == ({returntype})0xabe4);
+    ASSERT (bank == 0);
+    ASSERT (f_ab(0x4e) == ({returntype})0xab4e);
+    ASSERT (bank == 0);
+    ASSERT (c_51(0x02, 0xd) == ({returntype})0x51d2);
+    ASSERT (bank == 0);
+    ASSERT (f_51(0x2d) == ({returntype})0x2d51);
+    ASSERT (bank == 0);
+#endif
+}
+
+
+#ifdef DO_CHECK
+void set_bank(void) __naked
+{
+    __asm
+set_bank::
+	ld	(_bank), a
+	ret
+    __endasm;
+}
+void get_bank(void) __naked
+{
+    __asm
+get_bank::
+	ld	a, (_bank)
+	ret
+    __endasm;
+}
+#pragma bank 0xab
+{returntype} c_ab(unsigned a, unsigned b) __banked
+{
+  return bank * 0x100 + a * 16 + b;
+}
+{returntype} f_ab(unsigned a) __banked __z88dk_fastcall
+{
+  return bank * 0x100 + a;
+}
+#pragma bank 0x51
+{returntype} c_51(unsigned a, unsigned b) __banked
+{
+  return bank * 0x100 + b * 16 + a;
+}
+{returntype} f_51(unsigned a) __banked __z88dk_fastcall
+{
+  return bank + a * 0x100;
+}
+#endif
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/bitfields-bits1.c sdcc-4.2.0+dfsg/support/regression/tests/bitfields-bits1.c
--- sdcc-4.0.0+dfsg/support/regression/tests/bitfields-bits1.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/bitfields-bits1.c	2022-02-08 20:31:38.000000000 +0000
@@ -0,0 +1,490 @@
+/** Operations with 1-bit sized bitfields
+    preBits: 0, 8, 16
+    pattern: 0, 1
+    varType: 0, 1, 2, 3, 4, 5, 6
+*/
+
+#pragma disable_warning 88
+
+// Disable for ds390: bug #3211
+// Absolute addressing has some issues for pdk. And if those are fixed, there might be  alack of memory, still.
+// mcs51 fails tests. Don't know if that is a bug or just a bad choice for ABS_ADDR1 and ABS_ADDR2 below.
+#if defined(__SDCC_ds390) || defined(__SDCC_pdk14) || defined(__SDCC_pdk15) || defined(__SDCC_mcs51)
+#define DUMMY_CASE
+#endif
+
+// These tests assume the bitfields are allocated in LSB to MSB order
+// but some hosts allocate them in MSB to LSB order. Disable the
+// tests on these hosts
+#if defined(PORT_HOST) && (defined(__ppc__) || defined(__PPC__) || defined(__sparc) || defined(__sparc64__))
+#define DUMMY_CASE
+#endif
+
+#include 
+#ifdef __sun__
+#include 
+#else
+#include 
+#endif
+
+#define PRE_BITS ({preBits})
+#define PATTERN ({pattern})
+#define VAR_TYPE ({varType})
+
+typedef struct
+{
+    #if PRE_BITS > 0
+        unsigned int preBits   : PRE_BITS;
+    #endif
+    unsigned int bit0       : 1;
+    unsigned int bit1       : 1;
+    unsigned int bit2       : 1;
+    unsigned int bit3       : 1;
+    unsigned int bit4       : 1;
+    unsigned int bit5       : 1;
+    unsigned int bit6       : 1;
+    unsigned int bit7       : 1;
+    
+    unsigned int postBits   : 8;
+}struct_8bits;
+
+typedef struct
+{
+    #if PRE_BITS > 0
+        unsigned int preBits   : PRE_BITS;
+    #endif
+    unsigned int bits       : 8;
+    unsigned int postBits   : 8;
+}struct_8bits_joined;
+
+
+#define bitToTest__(b) bit ## b
+#define bitToTest_(b) bitToTest__(b)
+#define bitToTest bitToTest_(BIT_TO_TEST)
+
+#if defined(__SDCC_pic16)
+    #define ABS_ADDR1 0x0200
+    #define ABS_ADDR2 0x0204
+#elif defined(__SDCC_pic14)
+    #define ABS_ADDR1 0x0100
+    #define ABS_ADDR2 0x0104
+#elif defined(__SDCC_stm8)
+    #define ABS_ADDR1 0x1000
+    #define ABS_ADDR2 0x1004
+#else
+    #if !defined(__SDCC_pdk14) && !defined(__SDCC_pdk15) // TODO: Make test suitable for pdk
+        #if !defined(PORT_HOST) // Never do absolute address test with host
+            #define ABS_ADDR1 0xCA00
+            #define ABS_ADDR2 0xCA04
+        #endif
+    #endif
+#endif
+
+#if VAR_TYPE == 0
+    volatile struct_8bits volatileBits;
+#elif VAR_TYPE == 1
+    #ifdef ABS_ADDR1
+        #define volatileBits (*(volatile struct_8bits*)ABS_ADDR1)
+    #else
+        #define DUMMY_CASE
+    #endif
+#elif VAR_TYPE == 2
+    #ifdef ABS_ADDR2
+        #define volatileBits (*(volatile struct_8bits*)ABS_ADDR2)
+    #else
+        #define DUMMY_CASE
+    #endif
+#elif VAR_TYPE == 3
+    #define VOLATILE_BITS_DEF volatile struct_8bits volatileBits
+#elif VAR_TYPE == 4
+    #define VOLATILE_BITS_DEF static volatile struct_8bits volatileBits
+#elif VAR_TYPE == 5
+    #ifdef ABS_ADDR1
+        #define VOLATILE_BITS_DEF static volatile __at(ABS_ADDR1) struct_8bits volatileBits
+    #else
+        #define DUMMY_CASE
+    #endif
+#elif VAR_TYPE == 6
+    #ifdef ABS_ADDR2
+        #define VOLATILE_BITS_DEF static volatile __at(ABS_ADDR2) struct_8bits volatileBits
+        #define USE_ONLY_1_BYTE
+    #else
+        #define DUMMY_CASE
+    #endif
+#else
+    #error "Unknown VAR_TYPE case"
+#endif
+
+#ifndef VOLATILE_BITS_DEF
+    #define VOLATILE_BITS_DEF
+#endif
+
+#if PATTERN == 0
+    #define PRE_BIT_VALUE 0
+    #define POST_BIT_VALUE 0
+#else
+    #define PRE_BIT_VALUE ((1UL << PRE_BITS) - 1)
+    #define POST_BIT_VALUE 0xFF
+#endif
+
+#ifndef DUMMY_CASE
+
+void dummy_f(void)
+{
+    return;
+}
+
+// Return type of this function is uint16_t to trigger some peephole rules for STM8
+uint16_t 
+bits_check_value(const struct_8bits * const var, const uint8_t value)
+{
+    #if PRE_BITS > 0
+        if(var->preBits != PRE_BIT_VALUE) return 0;
+    #endif
+    if(var->postBits != POST_BIT_VALUE) return 0;
+    
+    if(((struct_8bits_joined*)var)->bits != value) return 0;
+    
+    return 1;
+}
+void 
+bits_set_value(struct_8bits * const var, const uint8_t value)
+{
+    #if PRE_BITS > 0
+        var->preBits = PRE_BIT_VALUE;
+    #endif
+    var->postBits = POST_BIT_VALUE;
+    
+    ((struct_8bits_joined*)var)->bits = value;
+}
+
+
+void 
+bit_test_0(void)
+{
+    VOLATILE_BITS_DEF;
+    
+    #undef BIT_TO_TEST
+    #define BIT_TO_TEST 0
+    
+    bits_set_value(&volatileBits, 0x00);
+    volatileBits.bitToTest = 1;
+    dummy_f();
+    ASSERT(bits_check_value(&volatileBits,   1 << BIT_TO_TEST));
+    
+    bits_set_value(&volatileBits, 0xFF);
+    volatileBits.bitToTest = 0;
+    dummy_f();
+    ASSERT(bits_check_value(&volatileBits, ~(1 << BIT_TO_TEST)));
+    
+    bits_set_value(&volatileBits, 0x00);
+    volatileBits.bitToTest = ! volatileBits.bitToTest;
+    dummy_f();
+    ASSERT(bits_check_value(&volatileBits,   1 << BIT_TO_TEST));
+    
+    bits_set_value(&volatileBits, 0xFF);
+    volatileBits.bitToTest = ! volatileBits.bitToTest;
+    dummy_f();
+    ASSERT(bits_check_value(&volatileBits, ~(1 << BIT_TO_TEST)));
+    
+    bits_set_value(&volatileBits, 0x00);
+    volatileBits.bitToTest ^= 1;
+    dummy_f();
+    ASSERT(bits_check_value(&volatileBits,   1 << BIT_TO_TEST));
+    
+    bits_set_value(&volatileBits, 0xFF);
+    volatileBits.bitToTest ^= 1;
+    dummy_f();
+    ASSERT(bits_check_value(&volatileBits, ~(1 << BIT_TO_TEST)));
+}
+
+void 
+bit_test_1(void)
+{
+    VOLATILE_BITS_DEF;
+    
+    #undef BIT_TO_TEST
+    #define BIT_TO_TEST 1
+    
+    bits_set_value(&volatileBits, 0x00);
+    volatileBits.bitToTest = 1;
+    dummy_f();
+    ASSERT(bits_check_value(&volatileBits,   1 << BIT_TO_TEST));
+    
+    bits_set_value(&volatileBits, 0xFF);
+    volatileBits.bitToTest = 0;
+    dummy_f();
+    ASSERT(bits_check_value(&volatileBits, ~(1 << BIT_TO_TEST)));
+    
+    bits_set_value(&volatileBits, 0x00);
+    volatileBits.bitToTest = ! volatileBits.bitToTest;
+    dummy_f();
+    ASSERT(bits_check_value(&volatileBits,   1 << BIT_TO_TEST));
+    
+    bits_set_value(&volatileBits, 0xFF);
+    volatileBits.bitToTest = ! volatileBits.bitToTest;
+    dummy_f();
+    ASSERT(bits_check_value(&volatileBits, ~(1 << BIT_TO_TEST)));
+    
+    bits_set_value(&volatileBits, 0x00);
+    volatileBits.bitToTest ^= 1;
+    dummy_f();
+    ASSERT(bits_check_value(&volatileBits,   1 << BIT_TO_TEST));
+    
+    bits_set_value(&volatileBits, 0xFF);
+    volatileBits.bitToTest ^= 1;
+    dummy_f();
+    ASSERT(bits_check_value(&volatileBits, ~(1 << BIT_TO_TEST)));
+}
+
+void 
+bit_test_2(void)
+{
+    VOLATILE_BITS_DEF;
+    
+    #undef BIT_TO_TEST
+    #define BIT_TO_TEST 2
+    
+    bits_set_value(&volatileBits, 0x00);
+    volatileBits.bitToTest = 1;
+    dummy_f();
+    ASSERT(bits_check_value(&volatileBits,   1 << BIT_TO_TEST));
+    
+    bits_set_value(&volatileBits, 0xFF);
+    volatileBits.bitToTest = 0;
+    dummy_f();
+    ASSERT(bits_check_value(&volatileBits, ~(1 << BIT_TO_TEST)));
+    
+    bits_set_value(&volatileBits, 0x00);
+    volatileBits.bitToTest = ! volatileBits.bitToTest;
+    dummy_f();
+    ASSERT(bits_check_value(&volatileBits,   1 << BIT_TO_TEST));
+    
+    bits_set_value(&volatileBits, 0xFF);
+    volatileBits.bitToTest = ! volatileBits.bitToTest;
+    dummy_f();
+    ASSERT(bits_check_value(&volatileBits, ~(1 << BIT_TO_TEST)));
+    
+    bits_set_value(&volatileBits, 0x00);
+    volatileBits.bitToTest ^= 1;
+    dummy_f();
+    ASSERT(bits_check_value(&volatileBits,   1 << BIT_TO_TEST));
+    
+    bits_set_value(&volatileBits, 0xFF);
+    volatileBits.bitToTest ^= 1;
+    dummy_f();
+    ASSERT(bits_check_value(&volatileBits, ~(1 << BIT_TO_TEST)));
+}
+
+void 
+bit_test_3(void)
+{
+    VOLATILE_BITS_DEF;
+    
+    #undef BIT_TO_TEST
+    #define BIT_TO_TEST 3
+    
+    bits_set_value(&volatileBits, 0x00);
+    volatileBits.bitToTest = 1;
+    dummy_f();
+    ASSERT(bits_check_value(&volatileBits,   1 << BIT_TO_TEST));
+    
+    bits_set_value(&volatileBits, 0xFF);
+    volatileBits.bitToTest = 0;
+    dummy_f();
+    ASSERT(bits_check_value(&volatileBits, ~(1 << BIT_TO_TEST)));
+    
+    bits_set_value(&volatileBits, 0x00);
+    volatileBits.bitToTest = ! volatileBits.bitToTest;
+    dummy_f();
+    ASSERT(bits_check_value(&volatileBits,   1 << BIT_TO_TEST));
+    
+    bits_set_value(&volatileBits, 0xFF);
+    volatileBits.bitToTest = ! volatileBits.bitToTest;
+    dummy_f();
+    ASSERT(bits_check_value(&volatileBits, ~(1 << BIT_TO_TEST)));
+    
+    bits_set_value(&volatileBits, 0x00);
+    volatileBits.bitToTest ^= 1;
+    dummy_f();
+    ASSERT(bits_check_value(&volatileBits,   1 << BIT_TO_TEST));
+    
+    bits_set_value(&volatileBits, 0xFF);
+    volatileBits.bitToTest ^= 1;
+    dummy_f();
+    ASSERT(bits_check_value(&volatileBits, ~(1 << BIT_TO_TEST)));
+}
+
+void 
+bit_test_4(void)
+{
+    VOLATILE_BITS_DEF;
+    
+    #undef BIT_TO_TEST
+    #define BIT_TO_TEST 4
+    
+    bits_set_value(&volatileBits, 0x00);
+    volatileBits.bitToTest = 1;
+    dummy_f();
+    ASSERT(bits_check_value(&volatileBits,   1 << BIT_TO_TEST));
+    
+    bits_set_value(&volatileBits, 0xFF);
+    volatileBits.bitToTest = 0;
+    dummy_f();
+    ASSERT(bits_check_value(&volatileBits, ~(1 << BIT_TO_TEST)));
+    
+    bits_set_value(&volatileBits, 0x00);
+    volatileBits.bitToTest = ! volatileBits.bitToTest;
+    dummy_f();
+    ASSERT(bits_check_value(&volatileBits,   1 << BIT_TO_TEST));
+    
+    bits_set_value(&volatileBits, 0xFF);
+    volatileBits.bitToTest = ! volatileBits.bitToTest;
+    dummy_f();
+    ASSERT(bits_check_value(&volatileBits, ~(1 << BIT_TO_TEST)));
+    
+    bits_set_value(&volatileBits, 0x00);
+    volatileBits.bitToTest ^= 1;
+    dummy_f();
+    ASSERT(bits_check_value(&volatileBits,   1 << BIT_TO_TEST));
+    
+    bits_set_value(&volatileBits, 0xFF);
+    volatileBits.bitToTest ^= 1;
+    dummy_f();
+    ASSERT(bits_check_value(&volatileBits, ~(1 << BIT_TO_TEST)));
+}
+
+void 
+bit_test_5(void)
+{
+    VOLATILE_BITS_DEF;
+    
+    #undef BIT_TO_TEST
+    #define BIT_TO_TEST 5
+    
+    bits_set_value(&volatileBits, 0x00);
+    volatileBits.bitToTest = 1;
+    dummy_f();
+    ASSERT(bits_check_value(&volatileBits,   1 << BIT_TO_TEST));
+    
+    bits_set_value(&volatileBits, 0xFF);
+    volatileBits.bitToTest = 0;
+    dummy_f();
+    ASSERT(bits_check_value(&volatileBits, ~(1 << BIT_TO_TEST)));
+    
+    bits_set_value(&volatileBits, 0x00);
+    volatileBits.bitToTest = ! volatileBits.bitToTest;
+    dummy_f();
+    ASSERT(bits_check_value(&volatileBits,   1 << BIT_TO_TEST));
+    
+    bits_set_value(&volatileBits, 0xFF);
+    volatileBits.bitToTest = ! volatileBits.bitToTest;
+    dummy_f();
+    ASSERT(bits_check_value(&volatileBits, ~(1 << BIT_TO_TEST)));
+    
+    bits_set_value(&volatileBits, 0x00);
+    volatileBits.bitToTest ^= 1;
+    dummy_f();
+    ASSERT(bits_check_value(&volatileBits,   1 << BIT_TO_TEST));
+    
+    bits_set_value(&volatileBits, 0xFF);
+    volatileBits.bitToTest ^= 1;
+    dummy_f();
+    ASSERT(bits_check_value(&volatileBits, ~(1 << BIT_TO_TEST)));
+}
+
+void 
+bit_test_6(void)
+{
+    VOLATILE_BITS_DEF;
+    
+    #undef BIT_TO_TEST
+    #define BIT_TO_TEST 6
+    
+    bits_set_value(&volatileBits, 0x00);
+    volatileBits.bitToTest = 1;
+    dummy_f();
+    ASSERT(bits_check_value(&volatileBits,   1 << BIT_TO_TEST));
+    
+    bits_set_value(&volatileBits, 0xFF);
+    volatileBits.bitToTest = 0;
+    dummy_f();
+    ASSERT(bits_check_value(&volatileBits, ~(1 << BIT_TO_TEST)));
+    
+    bits_set_value(&volatileBits, 0x00);
+    volatileBits.bitToTest = ! volatileBits.bitToTest;
+    dummy_f();
+    ASSERT(bits_check_value(&volatileBits,   1 << BIT_TO_TEST));
+    
+    bits_set_value(&volatileBits, 0xFF);
+    volatileBits.bitToTest = ! volatileBits.bitToTest;
+    dummy_f();
+    ASSERT(bits_check_value(&volatileBits, ~(1 << BIT_TO_TEST)));
+    
+    bits_set_value(&volatileBits, 0x00);
+    volatileBits.bitToTest ^= 1;
+    dummy_f();
+    ASSERT(bits_check_value(&volatileBits,   1 << BIT_TO_TEST));
+    
+    bits_set_value(&volatileBits, 0xFF);
+    volatileBits.bitToTest ^= 1;
+    dummy_f();
+    ASSERT(bits_check_value(&volatileBits, ~(1 << BIT_TO_TEST)));
+}
+
+void 
+bit_test_7(void)
+{
+    VOLATILE_BITS_DEF;
+    
+    #undef BIT_TO_TEST
+    #define BIT_TO_TEST 7
+    
+    bits_set_value(&volatileBits, 0x00);
+    volatileBits.bitToTest = 1;
+    dummy_f();
+    ASSERT(bits_check_value(&volatileBits,   1 << BIT_TO_TEST));
+    
+    bits_set_value(&volatileBits, 0xFF);
+    volatileBits.bitToTest = 0;
+    dummy_f();
+    ASSERT(bits_check_value(&volatileBits, ~(1 << BIT_TO_TEST)));
+    
+    bits_set_value(&volatileBits, 0x00);
+    volatileBits.bitToTest = ! volatileBits.bitToTest;
+    dummy_f();
+    ASSERT(bits_check_value(&volatileBits,   1 << BIT_TO_TEST));
+    
+    bits_set_value(&volatileBits, 0xFF);
+    volatileBits.bitToTest = ! volatileBits.bitToTest;
+    dummy_f();
+    ASSERT(bits_check_value(&volatileBits, ~(1 << BIT_TO_TEST)));
+    
+    bits_set_value(&volatileBits, 0x00);
+    volatileBits.bitToTest ^= 1;
+    dummy_f();
+    ASSERT(bits_check_value(&volatileBits,   1 << BIT_TO_TEST));
+    
+    bits_set_value(&volatileBits, 0xFF);
+    volatileBits.bitToTest ^= 1;
+    dummy_f();
+    ASSERT(bits_check_value(&volatileBits, ~(1 << BIT_TO_TEST)));
+}
+#endif
+
+static void
+testBitfields(void)
+{
+    #ifndef DUMMY_CASE
+        bit_test_0();
+        bit_test_1();
+        bit_test_2();
+        bit_test_3();
+        
+        bit_test_4();
+        bit_test_5();
+        bit_test_6();
+        bit_test_7();
+    #endif
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/bitfields-bits2.c sdcc-4.2.0+dfsg/support/regression/tests/bitfields-bits2.c
--- sdcc-4.0.0+dfsg/support/regression/tests/bitfields-bits2.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/bitfields-bits2.c	2021-04-09 08:10:17.000000000 +0000
@@ -0,0 +1,136 @@
+/** Operations with 1-bit sized bitfields
+    preBits: 0, 8, 16
+    pattern: 0, 1
+*/
+
+#pragma disable_warning 88
+
+#include 
+#ifdef __sun__
+#include 
+#else
+#include 
+#endif
+
+#include 
+
+#define PRE_BITS ({preBits})
+
+typedef struct
+{
+    #if PRE_BITS > 0
+        unsigned int preBits   : PRE_BITS;
+    #endif
+    unsigned int bit0       : 1;
+    unsigned int bit1       : 1;
+    unsigned int bit2       : 1;
+    unsigned int bit3       : 1;
+    unsigned int bit4       : 1;
+    unsigned int bit5       : 1;
+    unsigned int bit6       : 1;
+    unsigned int bit7       : 1;
+    
+    unsigned int postBits   : 8;
+}struct_8bits;
+
+
+#if PATTERN == 0
+    #define PRE_BIT_VALUE 0
+    #define POST_BIT_VALUE 0
+#else
+    #define PRE_BIT_VALUE ((1UL << PRE_BITS) - 1)
+    #define POST_BIT_VALUE 0xFF
+#endif
+
+bool
+bits_check_value_no_cast(const struct_8bits * var, const uint8_t value)
+{
+    if((var->bit0 > 0) != ((value & 0x01) > 0)) return false;
+    if((var->bit1 > 0) != ((value & 0x02) > 0)) return false;
+    if((var->bit2 > 0) != ((value & 0x04) > 0)) return false;
+    if((var->bit3 > 0) != ((value & 0x08) > 0)) return false;
+        
+    if((var->bit4 > 0) != ((value & 0x10) > 0)) return false;
+    if((var->bit5 > 0) != ((value & 0x20) > 0)) return false;
+    if((var->bit6 > 0) != ((value & 0x40) > 0)) return false;
+    if((var->bit7 > 0) != ((value & 0x80) > 0)) return false;
+    
+    return true;
+}
+
+
+#define CAST_TO_UINT8(x) ((uint8_t)(x))
+
+// Lack of memory.
+#if !defined(__SDCC_pdk14) && !defined(__SDCC_pdk15)
+
+bool
+bits_check_value(const struct_8bits * const var, const uint8_t value)
+{
+    #if PRE_BITS > 0
+        if(var->preBits != PRE_BIT_VALUE) return false;
+    #endif
+
+    if(var->postBits != POST_BIT_VALUE) return false;
+    
+    if((var->bit0 > 0) != (CAST_TO_UINT8(value & 0x01) > 0)) return false;
+    if((var->bit1 > 0) != (CAST_TO_UINT8(value & 0x02) > 0)) return false;
+    if((var->bit2 > 0) != (CAST_TO_UINT8(value & 0x04) > 0)) return false;
+    if((var->bit3 > 0) != (CAST_TO_UINT8(value & 0x08) > 0)) return false;
+        
+    if((var->bit4 > 0) != (CAST_TO_UINT8(value & 0x10) > 0)) return false;
+    if((var->bit5 > 0) != (CAST_TO_UINT8(value & 0x20) > 0)) return false;
+    if((var->bit6 > 0) != (CAST_TO_UINT8(value & 0x40) > 0)) return false;
+    if((var->bit7 > 0) != (CAST_TO_UINT8(value & 0x80) > 0)) return false;
+    
+    return bits_check_value_no_cast(var, value);
+}
+
+void 
+bits_set_value(struct_8bits * const var, const uint8_t value)
+{
+    #if PRE_BITS > 0
+        var->preBits = PRE_BIT_VALUE;
+    #endif
+    
+    var->postBits = POST_BIT_VALUE;
+    
+    var->bit0 = CAST_TO_UINT8(value & 0x01) > 0;
+    var->bit1 = CAST_TO_UINT8(value & 0x02) > 0;
+    var->bit2 = CAST_TO_UINT8(value & 0x04) > 0;
+    var->bit3 = CAST_TO_UINT8(value & 0x08) > 0;
+        
+    var->bit4 = CAST_TO_UINT8(value & 0x10) > 0;
+    var->bit5 = CAST_TO_UINT8(value & 0x20) > 0;
+    var->bit6 = CAST_TO_UINT8(value & 0x40) > 0;
+    var->bit7 = CAST_TO_UINT8(value & 0x80) > 0;
+}
+#endif
+
+#define BITS_SET_AND_CHECK(value) bits_set_value(&volatileBits, value); ASSERT(bits_check_value(&volatileBits, value))
+
+static void
+testBitfields(void)
+{
+// Lack of memory.
+#if !defined(__SDCC_pdk14) && !defined(__SDCC_pdk15)
+    volatile struct_8bits volatileBits;
+
+    BITS_SET_AND_CHECK(0x00);
+    BITS_SET_AND_CHECK(0xFF);
+    
+    BITS_SET_AND_CHECK(0x0F);
+    BITS_SET_AND_CHECK(0xF0);
+    
+    BITS_SET_AND_CHECK(0x01);
+    BITS_SET_AND_CHECK(0x02);
+    BITS_SET_AND_CHECK(0x04);
+    BITS_SET_AND_CHECK(0x08);
+    
+    BITS_SET_AND_CHECK(0x10);
+    BITS_SET_AND_CHECK(0x20);
+    BITS_SET_AND_CHECK(0x40);
+    BITS_SET_AND_CHECK(0x80);
+#endif
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/bitfields-checks.c sdcc-4.2.0+dfsg/support/regression/tests/bitfields-checks.c
--- sdcc-4.0.0+dfsg/support/regression/tests/bitfields-checks.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/bitfields-checks.c	2022-02-08 20:31:38.000000000 +0000
@@ -0,0 +1,234 @@
+/** Test for checks of bitfields or bits in a byte.
+    struct: 0, 1
+    varType: 0, 1, 2, 3, 4, 5, 6
+    bit: 0, 1, 2, 3, 4, 5, 6, 7
+*/
+
+#pragma disable_warning 88
+
+// Disable for ds390: bug #3211
+// Absolute addressing has some issues for pdk. And if those are fixed, there might be  alack of memory, still.
+// mcs51 creates invalid assembler. Don't know if that is a bug or just a bad choice for ABS_ADDR1 and ABS_ADDR2 below.
+#if defined(__SDCC_ds390) || defined(__SDCC_pdk14) || defined(__SDCC_pdk15) || defined(__SDCC_mcs51)
+#define DUMMY_CASE
+#endif
+
+#include 
+#ifdef __sun__
+#include 
+#else
+#include 
+#endif
+
+#define VAR_TYPE ({varType})
+#define BIT_TO_TEST {bit}
+#define TYPE_IS_STRUCT ({struct})
+
+
+typedef struct
+{
+// Use MSB to LSB order for hosts that use this order for bitfields
+#if defined(PORT_HOST) && (defined(__ppc__) || defined(__PPC__) || defined(__sparc) || defined(__sparc64__))
+    unsigned int bit7       : 1;
+    unsigned int bit6       : 1;
+    unsigned int bit5       : 1;
+    unsigned int bit4       : 1;
+    unsigned int bit3       : 1;
+    unsigned int bit2       : 1;
+    unsigned int bit1       : 1;
+    unsigned int bit0       : 1;
+#else
+// Use LSB to MSB order for SDCC and generic hosts (likely to be
+// x86 or other little endian)
+    unsigned int bit0       : 1;
+    unsigned int bit1       : 1;
+    unsigned int bit2       : 1;
+    unsigned int bit3       : 1;
+    unsigned int bit4       : 1;
+    unsigned int bit5       : 1;
+    unsigned int bit6       : 1;
+    unsigned int bit7       : 1;
+#endif
+}struct_8bits;
+
+#define bitToTest__(b) bit ## b
+#define bitToTest_(b) bitToTest__(b)
+
+#define bitToTest bitToTest_(BIT_TO_TEST)
+
+#if TYPE_IS_STRUCT
+    #define TYPE struct_8bits
+#else
+    #define TYPE uint8_t
+#endif
+
+#if defined(__SDCC_pic16)
+    #define ABS_ADDR1 0x0200
+    #define ABS_ADDR2 0x0204
+#elif defined(__SDCC_pic14)
+    #define ABS_ADDR1 0x0100
+    #define ABS_ADDR2 0x0104
+#elif defined(__SDCC_stm8)
+    #define ABS_ADDR1 0x1000
+    #define ABS_ADDR2 0x1004
+#else
+    #if !defined(__SDCC_pdk14) && !defined(__SDCC_pdk15) // TODO: Make test suitable for pdk
+        #if !defined(PORT_HOST) // Never do absolute address test with host
+            #define ABS_ADDR1 0xCA00
+            #define ABS_ADDR2 0xCA04
+        #endif
+    #endif
+#endif
+
+#if VAR_TYPE == 0
+    volatile TYPE volatileBits;
+#elif VAR_TYPE == 1
+    #ifdef ABS_ADDR1
+        #define volatileBits (*(volatile TYPE*)ABS_ADDR1)
+    #else
+        #define DUMMY_CASE
+    #endif
+#elif VAR_TYPE == 2
+    #ifdef ABS_ADDR2
+        #define volatileBits (*(volatile TYPE*)ABS_ADDR2)
+    #else
+        #define DUMMY_CASE
+    #endif
+#elif VAR_TYPE == 3
+    #define VOLATILE_BITS_DEF volatile TYPE volatileBits
+#elif VAR_TYPE == 4
+    #define VOLATILE_BITS_DEF static volatile TYPE volatileBits
+#elif VAR_TYPE == 5
+    #ifdef ABS_ADDR1
+        #define VOLATILE_BITS_DEF static volatile __at(ABS_ADDR1) TYPE volatileBits
+    #else
+        #define DUMMY_CASE
+    #endif
+#elif VAR_TYPE == 6
+    #ifdef ABS_ADDR2
+        #define VOLATILE_BITS_DEF static volatile __at(ABS_ADDR2) TYPE volatileBits
+        #define USE_ONLY_1_BYTE
+    #else
+        #define DUMMY_CASE
+    #endif
+#else
+    #error "Unknown VAR_TYPE case"
+#endif
+
+#ifndef VOLATILE_BITS_DEF
+    #define VOLATILE_BITS_DEF
+#endif
+
+
+#ifndef DUMMY_CASE
+
+#if TYPE_IS_STRUCT
+    #define AS_UINT8(x) (*(uint8_t *)&x)
+    void 
+    bit_test_byte(void)
+    {
+        VOLATILE_BITS_DEF;
+        volatile uint8_t dummy;
+        
+        AS_UINT8(volatileBits) = 1 << BIT_TO_TEST;
+        ASSERT(AS_UINT8(volatileBits) == (1 << BIT_TO_TEST));
+        ASSERT(volatileBits.bitToTest);
+        dummy = 0;
+        if(volatileBits.bitToTest) dummy = 1;
+        ASSERT(dummy);
+    
+        AS_UINT8(volatileBits) = ~(1 << BIT_TO_TEST);
+        ASSERT(AS_UINT8(volatileBits) == (uint8_t)(~(1 << BIT_TO_TEST)));
+        ASSERT(!volatileBits.bitToTest);
+        dummy = 0;
+        if(!volatileBits.bitToTest) dummy = 1;
+        ASSERT(dummy);
+        
+        AS_UINT8(volatileBits) = 0x00;
+        volatileBits.bitToTest = 1;
+        ASSERT(AS_UINT8(volatileBits) == (1 << BIT_TO_TEST));
+    
+        AS_UINT8(volatileBits) = 0xFF;
+        volatileBits.bitToTest = 1;
+        ASSERT(AS_UINT8(volatileBits) == 0xFF);
+    
+        AS_UINT8(volatileBits) = 0x00;
+        volatileBits.bitToTest = 0;
+        ASSERT(AS_UINT8(volatileBits) == 0x00);
+    
+        AS_UINT8(volatileBits) = 0xFF;
+        volatileBits.bitToTest = 0;
+        ASSERT(AS_UINT8(volatileBits) == (uint8_t)(~(1 << BIT_TO_TEST)));
+        
+        AS_UINT8(volatileBits) = 0x00;
+        volatileBits.bitToTest ^= 1;
+        ASSERT(AS_UINT8(volatileBits) == (1 << BIT_TO_TEST));
+    
+        AS_UINT8(volatileBits) = 0xFF;
+        volatileBits.bitToTest ^= 1;
+        ASSERT(AS_UINT8(volatileBits) == (uint8_t)(~(1 << BIT_TO_TEST)));
+        
+        AS_UINT8(volatileBits) = 0x00; // keep it to keep environment of all assert calls the same way
+    }
+#else
+    void 
+    bit_test_byte(void)
+    {
+        VOLATILE_BITS_DEF;
+        volatile uint8_t dummy;
+    
+        // Casts to int16_t are used because the code generator generates different code
+        // and as a result also different peephole rules are applied
+        
+        volatileBits = 1 << BIT_TO_TEST;
+        ASSERT(volatileBits & (1 << BIT_TO_TEST));
+        ASSERT(volatileBits & (int16_t)(1 << BIT_TO_TEST));
+        dummy = 0;
+        if(volatileBits & (int16_t)(1 << BIT_TO_TEST)) dummy = 1;
+        ASSERT(dummy);
+    
+        volatileBits = ~(1 << BIT_TO_TEST);
+        ASSERT(!(volatileBits & (1 << BIT_TO_TEST)));
+        ASSERT(!(volatileBits & (int16_t)(1 << BIT_TO_TEST)));
+        dummy = 0;
+        if(!(volatileBits & (int16_t)(1 << BIT_TO_TEST))) dummy = 1;
+        ASSERT(dummy);
+        
+        volatileBits = 0x00;
+        volatileBits |= 1 << BIT_TO_TEST;
+        ASSERT(volatileBits == (1 << BIT_TO_TEST));
+    
+        volatileBits = 0xFF;
+        volatileBits |= 1 << BIT_TO_TEST;
+        ASSERT(volatileBits == 0xFF);
+    
+        volatileBits = 0x00;
+        volatileBits &= (uint8_t)(~(1 << BIT_TO_TEST));
+        ASSERT(volatileBits == 0x00);
+    
+        volatileBits = 0xFF;
+        volatileBits &= (uint8_t)(~(1 << BIT_TO_TEST));
+        ASSERT(volatileBits == (uint8_t)(~(1 << BIT_TO_TEST)));
+        
+        volatileBits = 0x00;
+        volatileBits ^= 1 << BIT_TO_TEST;
+        ASSERT(volatileBits == (1 << BIT_TO_TEST));
+    
+        volatileBits = 0xFF;
+        volatileBits ^= 1 << BIT_TO_TEST;
+        ASSERT(volatileBits == (uint8_t)(~(1 << BIT_TO_TEST)));
+        
+        volatileBits = 0x00; // keep it to keep environment of all assert calls the same way
+    }
+#endif
+
+#endif // DUMMY_CASE
+
+static void
+testBitfieldsChecks(void)
+{
+    #ifndef DUMMY_CASE
+        bit_test_byte();
+    #endif
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/bitfields-dead-loop.c sdcc-4.2.0+dfsg/support/regression/tests/bitfields-dead-loop.c
--- sdcc-4.0.0+dfsg/support/regression/tests/bitfields-dead-loop.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/bitfields-dead-loop.c	2022-02-08 20:31:38.000000000 +0000
@@ -0,0 +1,217 @@
+/** Test for "dead-loops" over bitfield or bit tests in a byte.
+    struct: 0, 1
+    varType: 0, 1, 2, 3, 4, 5, 6
+*/
+
+#pragma disable_warning 88
+
+// Disable for ds390: bug #3211
+// Absolute addressing has some issues for pdk. And if those are fixed, there might be  alack of memory, still.
+// mcs51 creates invalid assembler. Don't know if that is a bug or just a bad choice for ABS_ADDR1 and ABS_ADDR2 below.
+#if defined(__SDCC_ds390) || defined(__SDCC_pdk14) || defined(__SDCC_pdk15) || defined(__SDCC_mcs51)
+#define DUMMY_CASE
+#endif
+
+// These tests assume the bitfields are allocated in LSB to MSB order
+// but some hosts allocate them in MSB to LSB order. Disable the
+// tests on these hosts
+#if defined(PORT_HOST) && (defined(__ppc__) || defined(__PPC__) || defined(__sparc) || defined(__sparc64__))
+#define DUMMY_CASE
+#endif
+
+#include 
+#ifdef __sun__
+#include 
+#else
+#include 
+#endif
+
+#define VAR_TYPE ({varType})
+#define TYPE_IS_STRUCT ({struct})
+
+
+typedef struct
+{
+    unsigned int bit0       : 1;
+    unsigned int bit1       : 1;
+    unsigned int bit2       : 1;
+    unsigned int bit3       : 1;
+    unsigned int high       : 4;
+}struct_8bits;
+
+#if TYPE_IS_STRUCT
+    #define TYPE struct_8bits
+#else
+    #define TYPE uint8_t
+#endif
+
+#if defined(__SDCC_pic16)
+    #define ABS_ADDR1 0x0200
+    #define ABS_ADDR2 0x0204
+#elif defined(__SDCC_pic14)
+    #define ABS_ADDR1 0x0100
+    #define ABS_ADDR2 0x0104
+#elif defined(__SDCC_stm8)
+    #define ABS_ADDR1 0x1000
+    #define ABS_ADDR2 0x1004
+#else
+    #if !defined(__SDCC_pdk14) && !defined(__SDCC_pdk15) // TODO: Make test suitable for pdk
+        #if !defined(PORT_HOST) // Never do absolute address test with host
+            #define ABS_ADDR1 0xCA00
+            #define ABS_ADDR2 0xCA04
+        #endif
+    #endif
+#endif
+
+#if VAR_TYPE == 0
+    volatile TYPE volatileBits;
+#elif VAR_TYPE == 1
+    #ifdef ABS_ADDR1
+        #define volatileBits (*(volatile TYPE*)ABS_ADDR1)
+    #else
+        #define DUMMY_CASE
+    #endif
+#elif VAR_TYPE == 2
+    #ifdef ABS_ADDR2
+        #define volatileBits (*(volatile TYPE*)ABS_ADDR2)
+    #else
+        #define DUMMY_CASE
+    #endif
+#elif VAR_TYPE == 3
+    #define VOLATILE_BITS_DEF volatile TYPE volatileBits
+#elif VAR_TYPE == 4
+    #define VOLATILE_BITS_DEF static volatile TYPE volatileBits
+#elif VAR_TYPE == 5
+    #ifdef ABS_ADDR1
+        #define VOLATILE_BITS_DEF static volatile __at(ABS_ADDR1) TYPE volatileBits
+    #else
+        #define DUMMY_CASE
+    #endif
+#elif VAR_TYPE == 6
+    #ifdef ABS_ADDR2
+        #define VOLATILE_BITS_DEF static volatile __at(ABS_ADDR2) TYPE volatileBits
+        #define USE_ONLY_1_BYTE
+    #else
+        #define DUMMY_CASE
+    #endif
+#else
+    #error "Unknown VAR_TYPE case"
+#endif
+
+#ifndef VOLATILE_BITS_DEF
+    #define VOLATILE_BITS_DEF
+#endif
+
+
+#ifndef DUMMY_CASE
+
+#if TYPE_IS_STRUCT
+    #define AS_UINT8(x) (*(uint8_t *)&x)
+    void 
+    loop_test_byte(void)
+    {
+        VOLATILE_BITS_DEF;
+        
+        AS_UINT8(volatileBits) = 0x00;
+        while(AS_UINT8(volatileBits) != 0x00);
+        while(volatileBits.high != 0x00);
+        while(volatileBits.bit0);
+        while(volatileBits.bit1);
+        while(volatileBits.bit2);
+        while(volatileBits.bit3);
+        
+        AS_UINT8(volatileBits) = 0xFF;
+        while(AS_UINT8(volatileBits) != 0xFF);
+        while(volatileBits.high != 0x0F);
+        while(!volatileBits.bit0);
+        while(!volatileBits.bit1);
+        while(!volatileBits.bit2);
+        while(!volatileBits.bit3);
+        
+        AS_UINT8(volatileBits) = 0x01;
+        while(AS_UINT8(volatileBits) != 0x01);
+        while(volatileBits.high != 0x00);
+        while(!volatileBits.bit0);
+        while( volatileBits.bit1);
+        while( volatileBits.bit2);
+        while( volatileBits.bit3);
+        
+        AS_UINT8(volatileBits) = 0x02;
+        while(AS_UINT8(volatileBits) != 0x02);
+        while(volatileBits.high != 0x00);
+        while( volatileBits.bit0);
+        while(!volatileBits.bit1);
+        while( volatileBits.bit2);
+        while( volatileBits.bit3);
+        
+        AS_UINT8(volatileBits) = 0xF0;
+        while(AS_UINT8(volatileBits) != 0xF0);
+        while(volatileBits.high != 0x0F);
+        while(volatileBits.bit0);
+        while(volatileBits.bit1);
+        while(volatileBits.bit2);
+        while(volatileBits.bit3);
+        
+        ASSERT(1);
+    }
+#else
+    #define AS_UINT8(x) x
+    void 
+    loop_test_byte(void)
+    {
+        VOLATILE_BITS_DEF;
+        
+        volatileBits = 0x00;
+        while(volatileBits != 0x00);
+        while((volatileBits & 0xF0) != 0x00);
+        while((volatileBits & 0x01) != 0x00);
+        while((volatileBits & 0x02) != 0x00);
+        while((volatileBits & 0x04) != 0x00);
+        while((volatileBits & 0x08) != 0x00);
+        
+        volatileBits = 0xFF;
+        while(volatileBits != 0xFF);
+        while((uint8_t)(volatileBits & 0xF0) != 0xF0);
+        while((uint8_t)(volatileBits & 0x01) != 0x01);
+        while((uint8_t)(volatileBits & 0x02) != 0x02);
+        while((uint8_t)(volatileBits & 0x04) != 0x04);
+        while((uint8_t)(volatileBits & 0x08) != 0x08);
+        
+        volatileBits = 0x01;
+        while(volatileBits != 0x01);
+        while(         (volatileBits & 0xF0) != 0x00);
+        while((uint8_t)(volatileBits & 0x01) != 0x01);
+        while(         (volatileBits & 0x02) != 0x00);
+        while(         (volatileBits & 0x04) != 0x00);
+        while(         (volatileBits & 0x08) != 0x00);
+        
+        volatileBits = 0x02;
+        while(volatileBits != 0x02);
+        while(         (volatileBits & 0xF0) != 0x00);
+        while(         (volatileBits & 0x01) != 0x00);
+        while((uint8_t)(volatileBits & 0x02) != 0x02);
+        while(         (volatileBits & 0x04) != 0x00);
+        while(         (volatileBits & 0x08) != 0x00);
+        
+        volatileBits = 0xF0;
+        while(volatileBits != 0xF0);
+        while((uint8_t)(volatileBits & 0xF0) != 0xF0);
+        while(         (volatileBits & 0x01) != 0x00);
+        while(         (volatileBits & 0x02) != 0x00);
+        while(         (volatileBits & 0x04) != 0x00);
+        while(         (volatileBits & 0x08) != 0x00);
+        
+        ASSERT(1);
+    }
+#endif
+
+#endif // DUMMY_CASE
+
+static void
+testBitfieldsDeadLoop(void)
+{
+    #ifndef DUMMY_CASE
+        loop_test_byte();
+    #endif
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/bitfields-nibbles.c sdcc-4.2.0+dfsg/support/regression/tests/bitfields-nibbles.c
--- sdcc-4.0.0+dfsg/support/regression/tests/bitfields-nibbles.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/bitfields-nibbles.c	2021-05-28 06:34:30.000000000 +0000
@@ -0,0 +1,471 @@
+/** Operations with 4bit-sized bitfields
+    operation: 0, 1, 2, 3, 4
+    pattern: 0, 1
+    varType: 0, 1, 2, 3, 4, 5, 6
+*/
+
+// Uncomment this line to run the full test
+//#define FULL_TEST
+
+#pragma disable_warning 88 // cast of LITERAL value to 'generic' pointer
+
+// Absolute addressing has some issues for pdk. And if those are fixed, there might be a lack of memory, still.
+#if defined(__SDCC_pdk14) || defined(__SDCC_pdk15)
+    #define DUMMY_CASE
+#endif
+
+#include 
+#ifdef __sun__
+#include 
+#else
+#include 
+#endif
+
+#include 
+
+#define OPERATION ({operation})
+#define PATTERN ({pattern})
+#define VAR_TYPE ({varType})
+
+#define OPERATION_ASSING    0
+#define OPERATION_OR        1
+#define OPERATION_AND       2
+#define OPERATION_XOR       3
+#define OPERATION_COM       4
+
+typedef struct
+{
+    unsigned int low    : 4;
+    unsigned int high   : 4;
+} struct_nibbles;
+
+#if defined(__SDCC_pic16)
+    #define ABS_ADDR1 0x0200
+    #define ABS_ADDR2 0x0204
+#elif defined(__SDCC_pic14)
+    #define ABS_ADDR1 0x0100
+    #define ABS_ADDR2 0x0104
+#elif defined(__SDCC_stm8)
+    #define ABS_ADDR1 0x1000
+    #define ABS_ADDR2 0x1004
+#else
+    // TODO: Make test suitable for pdk
+    // mcs51 creates invalid assembler. Don't know if that is a bug or just a bad choice for ABS_ADDR1 and ABS_ADDR2 below.
+    // Disable for ds390: bug #3211
+    #if !defined(__SDCC_pdk14) && !defined(__SDCC_pdk15) && !defined(__SDCC_mcs51) && !defined(__SDCC_ds390)
+        #if !defined(PORT_HOST) // Never do absolute address test with host
+            #define ABS_ADDR1 0xCA00
+            #define ABS_ADDR2 0xCA04
+        #endif
+    #endif
+#endif
+
+#if VAR_TYPE == 0
+    volatile struct_nibbles volatileBits;
+#elif VAR_TYPE == 1
+    #ifdef ABS_ADDR1
+        #define volatileBits (*(volatile struct_nibbles*)ABS_ADDR1)
+    #else
+        #define DUMMY_CASE
+    #endif
+#elif VAR_TYPE == 2
+    #ifdef ABS_ADDR2
+        #define volatileBits (*(volatile struct_nibbles*)ABS_ADDR2)
+    #else
+        #define DUMMY_CASE
+    #endif
+#elif VAR_TYPE == 3
+    #define VOLATILE_BITS_DEF volatile struct_nibbles volatileBits
+#elif VAR_TYPE == 4
+    #define VOLATILE_BITS_DEF static volatile struct_nibbles volatileBits
+#elif VAR_TYPE == 5
+    #ifdef ABS_ADDR1
+        #define VOLATILE_BITS_DEF static volatile __at(ABS_ADDR1) struct_nibbles volatileBits
+    #else
+        #define DUMMY_CASE
+    #endif
+#elif VAR_TYPE == 6
+    #ifdef ABS_ADDR2
+        #define VOLATILE_BITS_DEF static volatile __at(ABS_ADDR2) struct_nibbles volatileBits
+        #define USE_ONLY_1_BYTE
+    #else
+        #define DUMMY_CASE
+    #endif
+#else
+    #error "Unknown VAR_TYPE case"
+#endif
+
+#ifndef VOLATILE_BITS_DEF
+    #define VOLATILE_BITS_DEF
+#endif
+
+
+#if PATTERN == 0
+    #define OTHER_FIELD_VALUE 0x00
+#else
+    #define OTHER_FIELD_VALUE 0x0F
+    #if OPERATION == OPERATION_COM
+        #ifndef DUMMY_CASE
+            // No need to test case, because we have only one case for complement operation
+            #define DUMMY_CASE 
+        #endif
+    #endif
+#endif
+
+#define OTHER_FIELD_high low
+#define OTHER_FIELD_low  high
+
+#define OTHER_FIELD_(x) OTHER_FIELD_##x
+#define OTHER_FIELD(x) OTHER_FIELD_(x)
+
+
+#ifndef DUMMY_CASE
+
+static bool success = false;
+
+#if OPERATION == OPERATION_ASSING
+    #define OP
+    #define TEST(field, value)   \
+        success = true; \
+        volatileBits.OTHER_FIELD(field) = OTHER_FIELD_VALUE; \
+        volatileBits.field = value; \
+        if((volatileBits.field != (value & 0x0F)) || (volatileBits.OTHER_FIELD(field) != OTHER_FIELD_VALUE)) success = false; \
+        ASSERT(success)
+#elif OPERATION == OPERATION_OR
+    #define OP |
+#elif OPERATION == OPERATION_AND
+    #define OP &
+#elif OPERATION == OPERATION_XOR
+    #define OP ^
+#elif OPERATION == OPERATION_COM
+    #define OP ~
+    #define TEST(valueLow, valueHigh)   \
+        volatileBits.low = valueLow;  \
+        volatileBits.high = valueHigh;  \
+        \
+        volatileBits.low = ~volatileBits.low;   \
+        ASSERT(volatileBits.low  == ((~valueLow) & 0x0F)); \
+        ASSERT(volatileBits.high == (valueHigh & 0x0F)); \
+        \
+        volatileBits.high = ~volatileBits.high; \
+        ASSERT(volatileBits.low == ((~valueLow)  & 0x0F)); \
+        ASSERT(volatileBits.high == ((~valueHigh) & 0x0F))
+    
+#else
+    #error "Unknown OPERATION case"
+#endif
+
+#ifndef TEST // GENERIC CASE FOR 'AND', 'OR' & 'XOR'
+    #define OP_EQUALS__(x) x##=
+    #define OP_EQUALS_(x) OP_EQUALS__(x)
+    #define OP_EQUALS OP_EQUALS_(OP)
+
+    #define TEST(field, value)   \
+        success = true; \
+        volatileBits.field = 0x00; \
+        volatileBits.OTHER_FIELD(field) = OTHER_FIELD_VALUE; \
+        if((volatileBits.field != 0x00) || (volatileBits.OTHER_FIELD(field) != OTHER_FIELD_VALUE)) success = false; \
+        \
+        volatileBits.field OP_EQUALS value; \
+        if((volatileBits.field != ((value OP 0x00) & 0x0F)) || (volatileBits.OTHER_FIELD(field) != OTHER_FIELD_VALUE)) success = false; \
+        \
+        volatileBits.field = 0x0F; \
+        if((volatileBits.field != 0x0F) || (volatileBits.OTHER_FIELD(field) != OTHER_FIELD_VALUE)) success = false; \
+        \
+        volatileBits.field OP_EQUALS value; \
+        if((volatileBits.field != ((value OP 0x0F) & 0x0F)) || (volatileBits.OTHER_FIELD(field) != OTHER_FIELD_VALUE)) success = false; \
+        ASSERT(success)
+#endif
+
+#if OPERATION == OPERATION_COM
+    static void
+    nibble_com_test1(void)
+    {
+        VOLATILE_BITS_DEF;
+        TEST(0xFF, 0xFF);
+        TEST(0x00, 0x00);
+        TEST(0x0F, 0x0F);
+        TEST(0xF0, 0xF0);
+    }
+    
+    static void
+    nibble_com_test2_1(void)
+    {
+        VOLATILE_BITS_DEF;
+        TEST(0x01, 0x01);
+        TEST(0x01, 0x02);
+        TEST(0x01, 0x04);
+        TEST(0x01, 0x08);
+    }
+    static void
+    nibble_com_test2_2(void)
+    {
+        VOLATILE_BITS_DEF;
+        TEST(0x02, 0x01);
+        TEST(0x02, 0x02);
+        TEST(0x02, 0x04);
+        TEST(0x02, 0x08);
+    }
+    static void
+    nibble_com_test2_3(void)
+    {
+        VOLATILE_BITS_DEF;
+        TEST(0x04, 0x01);
+        TEST(0x04, 0x02);
+        TEST(0x04, 0x04);
+        TEST(0x04, 0x08);
+    }
+    static void
+    nibble_com_test2_4(void)
+    {
+        VOLATILE_BITS_DEF;
+        TEST(0x08, 0x01);
+        TEST(0x08, 0x02);
+        TEST(0x08, 0x04);
+        TEST(0x08, 0x08);
+    }
+    
+    static void
+    nibble_com_test3_1(void)
+    {
+        VOLATILE_BITS_DEF;
+        TEST(0x0E, 0x0E);
+        TEST(0x0E, 0x0D);
+        TEST(0x0E, 0x0B);
+        TEST(0x0E, 0x07);
+    }
+    static void
+    nibble_com_test3_2(void)
+    {
+        VOLATILE_BITS_DEF;
+        TEST(0x0D, 0x0E);
+        TEST(0x0D, 0x0D);
+        TEST(0x0D, 0x0B);
+        TEST(0x0D, 0x07);
+    }
+    static void
+    nibble_com_test3_3(void)
+    {
+        VOLATILE_BITS_DEF;
+        TEST(0x0B, 0x0E);
+        TEST(0x0B, 0x0D);
+        TEST(0x0B, 0x0B);
+        TEST(0x0B, 0x07);
+    }
+    static void
+    nibble_com_test3_4(void)
+    {
+        VOLATILE_BITS_DEF;
+        TEST(0x07, 0x0E);
+        TEST(0x07, 0x0D);
+        TEST(0x07, 0x0B);
+        TEST(0x07, 0x07);
+    }
+    
+    static void
+    nibble_com_test4_1(void)
+    {
+        VOLATILE_BITS_DEF;
+        TEST(0x03, 0x03);
+        TEST(0x03, 0x06);
+        TEST(0x03, 0x0C);
+    }
+    static void
+    nibble_com_test4_2(void)
+    {
+        VOLATILE_BITS_DEF;
+        TEST(0x06, 0x03);
+        TEST(0x06, 0x06);
+        TEST(0x06, 0x0C);
+    }
+    static void
+    nibble_com_test4_3(void)
+    {
+        VOLATILE_BITS_DEF;        
+        TEST(0x0C, 0x03);
+        TEST(0x0C, 0x06);
+        TEST(0x0C, 0x0C);
+    }
+#else
+    static void
+    nibble_op_test_low1_1(void)
+    {
+        VOLATILE_BITS_DEF;
+        TEST(low, 0xFF);
+        TEST(low, 0x00);
+    }
+    static void
+    nibble_op_test_low1_2(void)
+    {
+        VOLATILE_BITS_DEF;
+        TEST(low, 0x0F);
+        TEST(low, 0xF0);
+    }
+    static void
+    nibble_op_test_low2_1(void)
+    {
+        VOLATILE_BITS_DEF;
+        TEST(low, 0x01);
+        TEST(low, 0x02);
+    }
+    #ifdef FULL_TEST
+      static void
+      nibble_op_test_low2_2(void)
+      {
+          VOLATILE_BITS_DEF;
+          TEST(low, 0x04);
+          TEST(low, 0x08);
+      }
+    #endif
+    static void
+    nibble_op_test_low3_1(void)
+    {
+        VOLATILE_BITS_DEF;
+        TEST(low, 0x0E);
+        TEST(low, 0x0D);
+    }
+    #ifdef FULL_TEST
+      static void
+      nibble_op_test_low3_2(void)
+      {
+          VOLATILE_BITS_DEF;
+          TEST(low, 0x0B);
+          TEST(low, 0x07);
+      }
+      #endif
+    static void
+    nibble_op_test_low4_1(void)
+    {
+        VOLATILE_BITS_DEF;
+        TEST(low, 0x10);
+        TEST(low, 0x20);
+    }
+    #ifdef FULL_TEST
+      static void
+      nibble_op_test_low4_2(void)
+      {
+          VOLATILE_BITS_DEF;
+          TEST(low, 0x40);
+          TEST(low, 0x80);
+      }
+    #endif
+    
+    static void
+    nibble_op_test_high1_1(void)
+    {
+        VOLATILE_BITS_DEF;
+        TEST(high, 0xFF);
+        TEST(high, 0x00);
+    }
+    static void
+    nibble_op_test_high1_2(void)
+    {
+        VOLATILE_BITS_DEF;
+        TEST(high, 0x0F);
+        TEST(high, 0xF0);
+    }
+    static void
+    nibble_op_test_high2_1(void)
+    {
+        VOLATILE_BITS_DEF;
+        TEST(high, 0x01);
+        TEST(high, 0x02);
+    }
+    #ifdef FULL_TEST
+      static void
+      nibble_op_test_high2_2(void)
+      {
+          VOLATILE_BITS_DEF;
+          TEST(high, 0x04);
+          TEST(high, 0x08);
+      }
+    #endif
+    static void
+    nibble_op_test_high3_1(void)
+    {
+        VOLATILE_BITS_DEF;
+        TEST(high, 0x0E);
+        TEST(high, 0x0D);
+    }
+    #ifdef FULL_TEST
+      static void
+      nibble_op_test_high3_2(void)
+      {
+          VOLATILE_BITS_DEF;
+          TEST(high, 0x0B);
+          TEST(high, 0x07);
+      }
+      #endif
+    static void
+    nibble_op_test_high4_1(void)
+    {
+        VOLATILE_BITS_DEF;
+        TEST(high, 0x10);
+        TEST(high, 0x20);
+    }
+    #ifdef FULL_TEST
+      static void
+      nibble_op_test_high4_2(void)
+      {
+          VOLATILE_BITS_DEF;
+          TEST(high, 0x40);
+          TEST(high, 0x80);
+      }
+    #endif
+#endif
+
+#endif // DUMMY_CASE
+
+static void
+testBitfields(void)
+{
+    #ifndef DUMMY_CASE
+        #if OPERATION == OPERATION_COM
+            nibble_com_test1();
+            
+            nibble_com_test2_1();
+            nibble_com_test2_2();
+            nibble_com_test2_3();
+            nibble_com_test2_4();
+            
+            nibble_com_test3_1();
+            nibble_com_test3_2();
+            nibble_com_test3_3();
+            nibble_com_test3_4();
+            
+            nibble_com_test4_1();
+            nibble_com_test4_2();
+            nibble_com_test4_3();
+        #else
+            nibble_op_test_low1_1();
+            nibble_op_test_low1_2();
+            nibble_op_test_low2_1();
+            #ifdef FULL_TEST
+                nibble_op_test_low2_2();
+            #endif
+            nibble_op_test_low3_1();
+            #ifdef FULL_TEST
+                nibble_op_test_low3_2();
+            #endif
+            nibble_op_test_low4_1();
+            #ifdef FULL_TEST
+                nibble_op_test_low4_2();
+            #endif
+            
+            nibble_op_test_high1_1();
+            nibble_op_test_high1_2();
+            nibble_op_test_high2_1();
+            #ifdef FULL_TEST
+                nibble_op_test_high2_2();
+            #endif
+            nibble_op_test_high3_1();
+            #ifdef FULL_TEST
+                nibble_op_test_high3_2();
+            #endif
+            nibble_op_test_high4_1();
+            #ifdef FULL_TEST
+                nibble_op_test_high4_2();
+            #endif
+        #endif
+    #endif
+}
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/bitwise8reg.c sdcc-4.2.0+dfsg/support/regression/tests/bitwise8reg.c
--- sdcc-4.0.0+dfsg/support/regression/tests/bitwise8reg.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/bitwise8reg.c	2021-04-09 16:57:57.000000000 +0000
@@ -0,0 +1,51 @@
+/** Test the 8-bit bitwise operators under regsiter pressure
+    Meant to trigger use of 16-bit bitwise instructions for 8-bit operations.
+
+ */
+
+#include 
+
+unsigned char c0, c1, c2, c3;
+
+unsigned char and8(void)
+{
+	unsigned char t0, t1, t2, t3, t4, t5;
+	
+	t0 = c0 + 1;
+	t1 = c1 + 1;
+	t2 = c2 + 1;
+	t3 = c3 + 1;
+	
+	t4 = t0 & t1;
+	t5 = t2 & t3;
+	
+	return(t4 + t5);
+}
+
+unsigned char or8(void)
+{
+	unsigned char t0, t1, t2, t3, t4, t5;
+	
+	t0 = c0 + 1;
+	t1 = c1 + 1;
+	t2 = c2 + 1;
+	t3 = c3 + 1;
+	
+	t4 = t0 | t1;
+	t5 = t2 | t3;
+	
+	return(t4 + t5);
+}
+
+void
+test8(void)
+{
+	c0 = 2;
+	c1 = 2;
+	c2 = 4;
+	c3 = 4;
+	
+	ASSERT(and8() == 8);
+	ASSERT(or8() == 8);
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/bitwise.c sdcc-4.2.0+dfsg/support/regression/tests/bitwise.c
--- sdcc-4.0.0+dfsg/support/regression/tests/bitwise.c	2019-09-24 20:05:59.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/bitwise.c	2021-04-09 16:57:57.000000000 +0000
@@ -331,3 +331,4 @@
 
   ASSERT(ep == 127);
 }
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/bug1253.c sdcc-4.2.0+dfsg/support/regression/tests/bug1253.c
--- sdcc-4.0.0+dfsg/support/regression/tests/bug1253.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/bug1253.c	2020-05-23 11:39:29.000000000 +0000
@@ -0,0 +1,29 @@
+/*  Bug 1253, was bug 1609244
+ */
+
+#include 
+
+typedef char * PCHAR;
+
+char KAR;
+
+// bug.c:7: warning 60: function return value mismatch from type 'char near* '
+// to type 'char generic* unknown type'
+// bug.c:5: warning 59: function 'foo' must return value
+
+PCHAR foo(void) __reentrant //this fails
+{
+  return &KAR;
+}
+
+PCHAR bar(void) // this is ok
+{
+  return &KAR;
+}
+
+void
+testBug(void)
+{
+  ASSERT(foo() == bar());
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/bug2084206.c sdcc-4.2.0+dfsg/support/regression/tests/bug2084206.c
--- sdcc-4.0.0+dfsg/support/regression/tests/bug2084206.c	2019-04-17 14:48:53.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/bug2084206.c	2021-05-17 10:27:16.000000000 +0000
@@ -36,6 +36,8 @@
 #ifndef __SDCC_pdk14 // Lack of memory - see RFE # 613.
 #ifndef __SDCC_pdk15 // TODO: Decide on support for casts between object and function pointers for pdk!
 #ifndef __SDCC_pic16
+#if !((defined __SDCC_stm8) && defined(__SDCC_MODEL_LARGE)) // STM8 large model has sizeof(void *) < size of function pointers.
+#if !defined(__SDCC_ds390) && !defined(__SDCC_mcs51) // DS390 and at least some MCS-51 memory models have sizeof(void *) > size of function pointers.
 	void* ptr = testBug;
 	mydata.f = testBug;
 	ASSERT (varargs(1, mydata.f) == (long)ptr);
@@ -45,4 +47,6 @@
 #endif
 #endif
 #endif
+#endif
+#endif
 }
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/bug-2305.c sdcc-4.2.0+dfsg/support/regression/tests/bug-2305.c
--- sdcc-4.0.0+dfsg/support/regression/tests/bug-2305.c	2019-04-16 10:04:43.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/bug-2305.c	2022-01-09 00:53:30.000000000 +0000
@@ -4,7 +4,7 @@
 
 #include 
 
-#if !defined(PORT_HOST) && !defined(__SDCC_hc08) && !defined(__SDCC_s08) && !defined(__SDCC_gbz80) && !defined(__SDCC_stm8) && !defined(__SDCC_tlcs90) && !defined(__SDCC_pdk14) && !defined(__SDCC_pdk15)
+#if !defined(PORT_HOST) && !defined(__SDCC_hc08) && !defined(__SDCC_s08) && !defined(__SDCC_mos6502) && !defined(__SDCC_mos65c02) && !defined(__SDCC_sm83) && !defined(__SDCC_stm8) && !defined(__SDCC_tlcs90) && !defined(__SDCC_pdk14) && !defined(__SDCC_pdk15)
 __sfr __at 0xF4 fd_select;
 
 static void foo(unsigned char x)
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/bug-2349.c sdcc-4.2.0+dfsg/support/regression/tests/bug-2349.c
--- sdcc-4.0.0+dfsg/support/regression/tests/bug-2349.c	2019-04-16 10:04:43.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/bug-2349.c	2021-06-11 10:22:54.000000000 +0000
@@ -40,7 +40,7 @@
 
 subfunc_t dosub(subfunc_t f)
 {
-#if !defined( __SDCC_pdk14) && !defined( __SDCC_pdk15)
+#if !defined(__SDCC_pdk14) && !defined(__SDCC_pdk15)
   if (f == subchar)
     return subint;
   else if (f == subint)
@@ -56,7 +56,7 @@
 
 void testBug(void)
 {
-#if !defined( __SDCC_pdk14) && !defined( __SDCC_pdk15)
+#if !defined(__SDCC_pdk14) && !defined(__SDCC_pdk15)
   ASSERT (dosub(subchar) == subint);
   ASSERT (dosub(subint) == sublong);
   ASSERT (dosub(sublong) == subchar);
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/bug-2363.c sdcc-4.2.0+dfsg/support/regression/tests/bug-2363.c
--- sdcc-4.0.0+dfsg/support/regression/tests/bug-2363.c	2019-10-14 11:33:28.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/bug-2363.c	2020-08-06 11:10:04.000000000 +0000
@@ -20,7 +20,7 @@
 
 static void Durak_CpuMoves (void)
 {
-#ifndef __SDCC
+#if !(defined(__SDCC_mcs51) && defined(__SDCC_MODEL_SMALL)) && !defined(__SDCC_pdk14) && !defined(__SDCC_pdk15) && !defined(__SDCC_pic14) // Not enough memory
 	signed char i, l;
 	signed int z;
 	signed char _for__14;
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/bug-2368.c sdcc-4.2.0+dfsg/support/regression/tests/bug-2368.c
--- sdcc-4.0.0+dfsg/support/regression/tests/bug-2368.c	2015-04-06 12:55:47.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/bug-2368.c	2020-09-28 10:06:29.000000000 +0000
@@ -9,10 +9,15 @@
 #pragma std_c99
 #endif
 
-#if defined (__SDCC_stm8) || defined (__SDCC_z80)
+#if defined (__SDCC_stm8) || defined (__SDCC_z80) || defined (__SDCC_z180) || defined (__SDCC_r2k) || defined (__SDCC_r2ka) || defined (__SDCC_r3ka)
 
 #define TEST_VAL 0x1234
+
+#ifdef __SDCC_stm8 // data memory in lower half of 16-bit address space
 #define loc ((volatile uint16_t *) 0x7fd)
+#else // data memory in upper half of 16-bit address space
+#define loc ((volatile uint16_t *) 0x87fd)
+#endif
 
 volatile uint16_t *p = loc;
 
@@ -30,7 +35,7 @@
 
 void testBug (void)
 {
-#if defined (__SDCC_stm8) || defined (__SDCC_z80)
+#if defined (__SDCC_stm8) || defined (__SDCC_z80) || defined (__SDCC_z180) || defined (__SDCC_r2k) || defined (__SDCC_r2ka) || defined (__SDCC_r3ka)
   volatile uint16_t *q = loc;
 
   foo1 ();
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/bug-2376.c sdcc-4.2.0+dfsg/support/regression/tests/bug-2376.c
--- sdcc-4.0.0+dfsg/support/regression/tests/bug-2376.c	2017-03-13 12:28:41.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/bug-2376.c	2020-09-28 10:06:29.000000000 +0000
@@ -4,10 +4,6 @@
    A peephole optimizer bug in calls to __z88dk_fastcall.
 */
 
-#if !defined(__SDCC_z80) && !defined(__SDCC_z180) && !defined(__SDCC_r2k) && !defined(__SDCC_r3ka) && !defined(__SDCC_tlcs90)
-#define __z88dk_fastcall
-#endif
-
 #include 
 #include 
 
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/bug-2516.c sdcc-4.2.0+dfsg/support/regression/tests/bug-2516.c
--- sdcc-4.0.0+dfsg/support/regression/tests/bug-2516.c	2019-04-16 10:04:43.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/bug-2516.c	2021-03-22 08:18:36.000000000 +0000
@@ -59,7 +59,7 @@
   ASSERT (!isinf (divTest (1.0, 0.5)));
   ASSERT (!isnan (divTest (1.0, 0.5)));
 
-  ASSERT (!isnan (divTest (1e38, 1e-38)));
-  ASSERT (isinf (divTest (1e38, 1e-38)));
+  ASSERT (!isnan (divTest (3e38, 2e-38)));
+  ASSERT (isinf (divTest (3e38, 2e-38)));
 #endif
 }
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/bug-2580.c sdcc-4.2.0+dfsg/support/regression/tests/bug-2580.c
--- sdcc-4.0.0+dfsg/support/regression/tests/bug-2580.c	2017-10-29 08:35:06.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/bug-2580.c	2020-09-28 10:06:29.000000000 +0000
@@ -10,10 +10,7 @@
 unsigned {type} game_menu_sel;
 unsigned {type} s_lin1;
 
-void game_menu_back(unsigned {type} f_start)
-#if defined(__SDCC_z80) || defined(__SDCC_z180) || defined(__SDCC_tlcs90) || defined(__SDCC_r2k) || defined(__SDCC_r3ka)
-__z88dk_fastcall
-#endif
+void game_menu_back(unsigned {type} f_start) __z88dk_fastcall
 {
     game_menu_sel = 0;
     s_lin1 = f_start;
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/bug-2590.c sdcc-4.2.0+dfsg/support/regression/tests/bug-2590.c
--- sdcc-4.0.0+dfsg/support/regression/tests/bug-2590.c	2018-09-14 13:31:29.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/bug-2590.c	2020-09-28 10:06:29.000000000 +0000
@@ -4,8 +4,6 @@
 
 #include 
 
-#if (defined __SDCC_z80 || defined __SDCC_z180 || defined __SDCC_gbz80 || defined __SDCC_r2k || defined __SDCC_r3ka || defined __SDCC_tlcs90)
-
 #pragma disable_warning 85
 
 const unsigned char *letras_tiles01;
@@ -38,8 +36,6 @@
         }
 }
 
-#endif
-
 void testBug(void)
 {
 }
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/bug-2645.c sdcc-4.2.0+dfsg/support/regression/tests/bug-2645.c
--- sdcc-4.0.0+dfsg/support/regression/tests/bug-2645.c	2017-11-05 14:12:58.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/bug-2645.c	2020-08-12 04:55:14.000000000 +0000
@@ -4,7 +4,10 @@
 
 #include 
 
+#ifdef __SDCC
+#pragma disable_warning 154
 #pragma disable_warning 88
+#endif
 
 unsigned char *backgrounds[1] = {25768 + 32 + 32 + 32 + 32 + 32 + 32};
 
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/bug-2663.c sdcc-4.2.0+dfsg/support/regression/tests/bug-2663.c
--- sdcc-4.0.0+dfsg/support/regression/tests/bug-2663.c	2019-04-16 10:04:43.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/bug-2663.c	2022-01-09 00:53:30.000000000 +0000
@@ -25,7 +25,7 @@
 
 void testBug(void)
 {
-#if !defined(__SDCC_mcs51) && !defined(__SDCC_ds390) && !defined(__SDCC_hc08) && !defined(__SDCC_s08) && !defined(__SDCC_pdk14) && !defined(__SDCC_pdk14) && !defined(__SDCC_pdk15) /* mcs51, hc08, s08 and pdk14 have restrictions on function pointers wrt. reentrancy */
+#if !defined(__SDCC_mcs51) && !defined(__SDCC_ds390) && !defined(__SDCC_hc08) && !defined(__SDCC_s08) && !defined(__SDCC_mos6502) && !defined(__SDCC_mos65c02) && !defined(__SDCC_pdk14) && !defined(__SDCC_pdk14) && !defined(__SDCC_pdk15) /* mcs51, hc08, s08 and pdk14 have restrictions on function pointers wrt. reentrancy */
 	ASSERT(((int (*)(long, long))(string_binop1[0].op_func))(1, 1) == 0);
 	ASSERT(((int (*)(long, long))(string_binop1[0].op_func))(1, 2) == 1);
 	ASSERT(((int (*)(long, long))(string_binop2[0].op_func))(1, 1) == 0);
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/bug2686159.c sdcc-4.2.0+dfsg/support/regression/tests/bug2686159.c
--- sdcc-4.0.0+dfsg/support/regression/tests/bug2686159.c	2019-10-14 11:33:28.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/bug2686159.c	2021-06-25 23:24:04.000000000 +0000
@@ -10,6 +10,8 @@
 # define ADDRESS(x) (0x01A0 + 0x ## x)
 #elif defined(__SDCC_stm8)
 # define ADDRESS(x) (0x10 ## x)
+#elif defined( __SDCC_pdk14) || defined( __SDCC_pdk15) // No RAM above 0x7f / 0xff.
+# define ADDRESS(x) (0x78 + 0x ## x)
 #else
 # define ADDRESS(x) (0xCA ## x)
 #endif
@@ -17,6 +19,10 @@
 /* This produces incorrect code */
 #define REG_1 (*(__xdata unsigned char*)ADDRESS(00))
 
+// Absolute addresses should use an initial value to make sure compiler does not use these addresses.
+// From manual: If you provide an initializer actual memory allocation will take place and overlaps will be detected by the linker
+__xdata unsigned char  __at(ADDRESS(00)) REG_1_RES = 0;
+
 void incorrect(void)
 {
 	REG_1 |= 1;
@@ -24,7 +30,7 @@
 }
 
 /* This produces correct code */
-__xdata unsigned char __at(ADDRESS(01)) REG_2;
+__xdata unsigned char __at(ADDRESS(01)) REG_2 = 0;
 
 void correct(void)
 {
@@ -34,7 +40,6 @@
 
 void testBug(void)
 {
-#if !defined( __SDCC_pdk14) && !defined( __SDCC_pdk15) // No RAM above 0x7f / 0xff.
 #ifdef __SDCC
 	REG_1 = 0x40;
 	incorrect();
@@ -43,5 +48,4 @@
 	REG_2 = 0x50;
 	correct();
 	ASSERT (REG_2 == 0x53);
-#endif
 }
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/bug2729218.c sdcc-4.2.0+dfsg/support/regression/tests/bug2729218.c
--- sdcc-4.0.0+dfsg/support/regression/tests/bug2729218.c	2019-03-14 16:34:34.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/bug2729218.c	2021-12-10 14:48:15.000000000 +0000
@@ -29,7 +29,7 @@
   unsigned char input_cnt;
 };
 
-#if !defined(__SDCC_gbz80) && !defined(__SDCC_pdk14)
+#if !defined(__SDCC_sm83) && !defined(__SDCC_pdk14)
 #define ig (*(__idata struct iglobals *) 0xf0)
 #else
 struct iglobals ig;
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/bug-2767.c sdcc-4.2.0+dfsg/support/regression/tests/bug-2767.c
--- sdcc-4.0.0+dfsg/support/regression/tests/bug-2767.c	2019-04-16 10:04:43.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/bug-2767.c	2022-01-09 00:53:30.000000000 +0000
@@ -6,7 +6,7 @@
 
 #include 
 
-#if !defined(__SDCC_mcs51) && !defined(__SDCC_ds390) && !defined(__SDCC_hc08) && !defined(__SDCC_s08) && !defined(__SDCC_pdk14) && !defined (__SDCC_pdk15) /* mcs51, hc08, s08 and pdk14 have restrictions on function pointers wrt. reentrancy */
+#if !defined(__SDCC_mcs51) && !defined(__SDCC_ds390) && !defined(__SDCC_hc08) && !defined(__SDCC_s08) && !defined (__SDCC_mos6502) && !defined(__SDCC_mos65c02) && !defined(__SDCC_pdk14) && !defined (__SDCC_pdk15) /* mcs51, hc08, s08 and pdk14 have restrictions on function pointers wrt. reentrancy */
 void f(void)
 {
 	((void (*)(int)) 0)(0);
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/bug-2770.c sdcc-4.2.0+dfsg/support/regression/tests/bug-2770.c
--- sdcc-4.0.0+dfsg/support/regression/tests/bug-2770.c	2018-07-12 08:29:38.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/bug-2770.c	2020-09-28 10:06:29.000000000 +0000
@@ -4,7 +4,7 @@
 
 #include 
 
-#if defined(__SDCC_z80) || defined(__SDCC_z180) || defined(__SDCC_r2k) || defined(__SDCC_r3ka) || defined(__SDCC_mcs51)
+#if defined(__SDCC_z80) || defined(__SDCC_z180) || defined(__SDCC_r2k) || defined(__SDCC_r2ka) || defined(__SDCC_r3ka) || defined(__SDCC_mcs51)
 __sfr __at 0xB0 rtc_secl;
 
 void fooX(void)
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/bug-2771.c sdcc-4.2.0+dfsg/support/regression/tests/bug-2771.c
--- sdcc-4.0.0+dfsg/support/regression/tests/bug-2771.c	2018-07-13 14:06:30.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/bug-2771.c	2020-09-28 10:06:29.000000000 +0000
@@ -4,7 +4,7 @@
 
 #include 
 
-#if defined(__SDCC_z80) || defined(__SDCC_z180) || defined(__SDCC_r2k) || defined(__SDCC_r3ka)
+#if defined(__SDCC_z80) || defined(__SDCC_z180) || defined(__SDCC_r2k) || defined(__SDCC_r2ka) || defined(__SDCC_r3ka)
 unsigned int port;
 
 static unsigned char cpu_id;
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/bug-2817.c sdcc-4.2.0+dfsg/support/regression/tests/bug-2817.c
--- sdcc-4.0.0+dfsg/support/regression/tests/bug-2817.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/bug-2817.c	2020-03-12 14:36:33.000000000 +0000
@@ -0,0 +1,19 @@
+/*
+    bug-2973.c
+*/
+
+#include 
+
+typedef int *foo_t;
+
+void f(foo_t *const x)
+{
+  *x = 0;
+}
+
+// nothing to run - bug is a compilation failure
+
+void testBug (void)
+{
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/bug-2822.c sdcc-4.2.0+dfsg/support/regression/tests/bug-2822.c
--- sdcc-4.0.0+dfsg/support/regression/tests/bug-2822.c	2019-03-14 16:34:34.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/bug-2822.c	2020-09-28 10:06:29.000000000 +0000
@@ -6,10 +6,6 @@
 
 #include 
 
-#if !defined(__SDCC_z80) && !defined(__SDCC_z180) && !defined(__SDCC_r2k) && !defined(__SDCC_r3ka) && !defined(__SDCC_tlcs90)
-#define __z88dk_fastcall
-#endif
-
 #ifndef __SDCC_pdk14 // Lack of memory
 struct wibble
 {
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/bug-2855.c sdcc-4.2.0+dfsg/support/regression/tests/bug-2855.c
--- sdcc-4.0.0+dfsg/support/regression/tests/bug-2855.c	2019-03-21 20:04:43.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/bug-2855.c	2022-01-09 00:53:30.000000000 +0000
@@ -9,7 +9,7 @@
 #include 
 
 #if __STDC_VERSION__ >= 201112L
-#if !defined(__SDCC_hc08) && !defined(__SDCC_s08) && !defined(__SDCC_mcs51) && !defined(__SDCC_ds390) && !defined(__SDCC_pdk13) && !defined(__SDCC_pdk14) && !defined(__SDCC_pdk15) || defined (__SDCC_STACK_AUTO) // Reentrancy required for function pointers.
+#if !defined(__SDCC_hc08) && !defined(__SDCC_s08) && !defined(__SDCC_mcs51) && !defined(__SDCC_ds390) && !defined(__SDCC_pdk13) && !defined(__SDCC_pdk14) && !defined(__SDCC_pdk15) && !defined (__SDCC_mos6502) && !defined(__SDCC_mos65c02) || defined (__SDCC_STACK_AUTO) // Reentrancy required for function pointers.
 void *(*volatile f)(size_t, size_t) = &aligned_alloc;
 #endif
 #endif
@@ -17,7 +17,7 @@
 void testBug(void)
 {
 #if __STDC_VERSION__ >= 201112L
-#if !defined(__SDCC_hc08) && !defined(__SDCC_s08) && !defined(__SDCC_mcs51) && !defined(__SDCC_ds390) && !defined(__SDCC_pdk13) && !defined(__SDCC_pdk14) && !defined(__SDCC_pdk15) || defined (__SDCC_STACK_AUTO)
+#if !defined(__SDCC_hc08) && !defined(__SDCC_s08) && !defined(__SDCC_mcs51) && !defined(__SDCC_ds390) && !defined(__SDCC_pdk13) && !defined(__SDCC_pdk14) && !defined(__SDCC_pdk15) && !defined (__SDCC_mos6502) && !defined(__SDCC_mos65c02) || defined (__SDCC_STACK_AUTO)
 	int *buffer = (*f)(_Alignof(int), sizeof(int) * 2);
 	buffer[0] = 23;
 	buffer[1] = 42;
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/bug-2881.c sdcc-4.2.0+dfsg/support/regression/tests/bug-2881.c
--- sdcc-4.0.0+dfsg/support/regression/tests/bug-2881.c	2019-03-16 14:47:35.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/bug-2881.c	2020-09-28 10:06:29.000000000 +0000
@@ -5,10 +5,6 @@
 
 #include 
 
-#if !defined(__SDCC_z80) && !defined(__SDCC_z180) && !defined(__SDCC_r2k) && !defined(__SDCC_r3ka) && !defined(__SDCC_tlcs90) && !defined(__SDCC_ez80_z80)
-#define __z88dk_fastcall
-#endif
-
 void g(void *p)
 {
     p;
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/bug-2912.c sdcc-4.2.0+dfsg/support/regression/tests/bug-2912.c
--- sdcc-4.0.0+dfsg/support/regression/tests/bug-2912.c	2019-06-17 10:48:05.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/bug-2912.c	2022-02-10 12:17:03.000000000 +0000
@@ -4,8 +4,8 @@
 
 #include 
 
-#if !defined(__SDCC_z80) && !defined(__SDCC_z180) && !defined(__SDCC_r2k) && !defined(__SDCC_r3ka) && !defined(__SDCC_tlcs90) && !defined(__SDCC_ez80_z80)
-#define __z88dk_fastcall
+#ifdef __SDCC
+#pragma disable_warning 85
 #endif
 
 #if !defined(__SDCC_pdk14) && !defined(__SDCC_pdk15) // lack of memory
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/bug-2932.c sdcc-4.2.0+dfsg/support/regression/tests/bug-2932.c
--- sdcc-4.0.0+dfsg/support/regression/tests/bug-2932.c	2019-12-14 10:34:43.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/bug-2932.c	2020-09-28 10:06:29.000000000 +0000
@@ -13,10 +13,6 @@
 #pragma disable_warning 85
 #endif
 
-#if !(defined(__SDCC_z80) || defined(__SDCC_gbz80) || defined(__SDCC_z180) || defined(__SDCC_r2k))
-#define __smallc
-#endif
-
 int fg(void *fp)
 {
     volatile int i = 1;
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/bug-2973.c sdcc-4.2.0+dfsg/support/regression/tests/bug-2973.c
--- sdcc-4.0.0+dfsg/support/regression/tests/bug-2973.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/bug-2973.c	2020-03-12 14:36:33.000000000 +0000
@@ -0,0 +1,19 @@
+/*
+    bug-2973.c
+*/
+
+#include 
+
+typedef int *foo_t;
+
+void f(const foo_t x)
+{
+  *x = 1;
+}
+
+// nothing to run - bug is a compilation failure
+
+void testBug (void)
+{
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/bug-2982.c sdcc-4.2.0+dfsg/support/regression/tests/bug-2982.c
--- sdcc-4.0.0+dfsg/support/regression/tests/bug-2982.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/bug-2982.c	2020-03-06 07:28:28.000000000 +0000
@@ -0,0 +1,36 @@
+/* bug-2982.c
+   A bug in the z80 peephole optimizer.
+ */
+
+#include 
+
+#pragma disable_warning 85
+
+static int L, STEP;
+
+void Basic_PRINT(int i)
+{
+  ASSERT (i == 36);
+}
+
+signed char Basic_RND(char a)
+{
+  return 51;
+}
+
+int f(int argc, char **argv)
+{
+    STEP = Basic_RND(0);
+    do {
+        // A load of L into register pair de got optimized out, though it was still needed for the claculation of L + 50
+        Basic_PRINT((L + 50) / 100);
+        L += STEP;
+    } while (!(L > 3600));
+}
+
+void testBug(void)
+{
+	L = 3550;
+	f(0, 0);
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/bug-2993.c sdcc-4.2.0+dfsg/support/regression/tests/bug-2993.c
--- sdcc-4.0.0+dfsg/support/regression/tests/bug-2993.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/bug-2993.c	2021-06-29 08:53:46.000000000 +0000
@@ -0,0 +1,38 @@
+/* bug-2993.c
+   Invalid asm was generated in the stm8 backend for calls via immediate (or literal) function pointers.
+ */
+
+#include 
+
+void f(void)
+{
+	void (*p)(void) __reentrant = (void (*)(void))0x24;
+	(*p)();
+}
+
+int func(void *var,int val) __reentrant;
+typedef int (*SetVal)(void *, int) __reentrant;
+typedef struct {
+                int val;
+                SetVal setval;
+                } my_struct; 
+
+void
+testBug(void)
+{  
+    my_struct str1 = {0,func};
+    my_struct str2 = {0,func};
+    str1.setval(&str1,11);  
+    str2.setval(&str2,5);
+    
+    ASSERT (str1.val == 11);
+    ASSERT (str2.val == 5);
+}
+
+int func(void *var,int val) __reentrant
+{
+    my_struct *tmp = (my_struct*)var;
+    tmp->val = val;
+    return 0;
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/bug-2995.c sdcc-4.2.0+dfsg/support/regression/tests/bug-2995.c
--- sdcc-4.0.0+dfsg/support/regression/tests/bug-2995.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/bug-2995.c	2020-04-26 19:09:41.000000000 +0000
@@ -0,0 +1,38 @@
+/** bug-2995.c
+    Getting the address of an object in a named address space was
+    considered a read access of that space resulting in inefficiencies
+    (i.e. unnecessary calls to the function for switching address spaces).
+*/
+
+#include 
+#include 
+
+bool a_accessed, b_accessed;
+
+void set_a(void)
+{
+  a_accessed = true;
+}
+
+void set_b(void)
+{
+  b_accessed = true;
+}
+
+#if !defined(PORT_HOST) && !defined(__SDCC_pdk14) && !defined(__SDCC_pdk15) && !defined(__SDCC_mcs51) // For pdk14, pdk15 and mcs51: Need to pass segment ordering to linker somehow, to place space_a somewhere in RAM.
+__addressmod set_a space_a;
+__addressmod set_b space_b;
+
+space_a int i; 
+space_a int *space_b j;
+#endif
+
+void testSpace(void)
+{
+#if !defined(PORT_HOST) && !defined(__SDCC_pdk14) && !defined(__SDCC_pdk15) && !defined(__SDCC_mcs51)
+  j = &i;
+  ASSERT (!a_accessed);
+  ASSERT (b_accessed);
+#endif
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/bug-3002.c sdcc-4.2.0+dfsg/support/regression/tests/bug-3002.c
--- sdcc-4.0.0+dfsg/support/regression/tests/bug-3002.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/bug-3002.c	2020-05-15 13:10:38.000000000 +0000
@@ -0,0 +1,17 @@
+/*
+   bug-3002.c - a bug in stm8 code generation for right shifts.
+ */
+
+#include 
+
+#include 
+
+uint_least32_t f(uint_least32_t arg)
+{
+	return((arg >> 22) | 0x15000000); // Operands chosen to encourage allocation of upper byte of shift result in accumulator and use of div for shift.
+}
+void testBug(void)
+{
+	ASSERT(f(0xaaa00000) == 0x150002aa);
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/bug-3003.c sdcc-4.2.0+dfsg/support/regression/tests/bug-3003.c
--- sdcc-4.0.0+dfsg/support/regression/tests/bug-3003.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/bug-3003.c	2020-05-23 06:09:31.000000000 +0000
@@ -0,0 +1,58 @@
+/*
+   bug-3003.c
+
+   The wrong location is used for a local variable; observable effects vary by backend.
+   For stm8, this results in overwriting other local variables.
+   For z80, it results in use of location below the stack.
+*/
+
+#include 
+
+#include 
+#include 
+
+#pragma disable_warning 88
+
+void g(void)
+{
+}
+
+static volatile uint8_t* f(const uint8_t id)
+{
+    volatile uint8_t* result = 0; // Bug: For stm8, this variable is accessed at stack at sp+255, overwriting part of buffer.
+    switch (id)
+    {
+        case 0:
+            result = (volatile uint8_t *)0x5000;
+            break;
+        case 1:
+            result = (volatile uint8_t *)0x5005;
+            break;
+        case 2:
+            result = (volatile uint8_t *)0x500a;
+            break;
+    }
+    g(); // This call overwrites result by hte return address for z80.
+    return result;
+}
+
+#if defined (__SDCC_pdk14) || defined (__SDCC_pdk15) || defined (__SDCC_mcs51) // Lack of memory
+#define BUFFERSIZE 20
+#else
+#define BUFFERSIZE 300
+#endif
+
+void testBug(void)
+{
+	unsigned char buffer[BUFFERSIZE]; // Bug: Overwritten in f() on stm8.
+	
+	memset(buffer, 0xa5, BUFFERSIZE);
+
+	ASSERT(f(0) == (volatile uint8_t *)0x5000);
+	ASSERT(f(1) == (volatile uint8_t *)0x5005);
+	ASSERT(f(2) == (volatile uint8_t *)0x500a);
+
+	for(size_t i = 0; i < BUFFERSIZE; i++)
+		ASSERT (buffer[i] == 0xa5);
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/bug-3007.c sdcc-4.2.0+dfsg/support/regression/tests/bug-3007.c
--- sdcc-4.0.0+dfsg/support/regression/tests/bug-3007.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/bug-3007.c	2020-05-29 09:15:39.000000000 +0000
@@ -0,0 +1,36 @@
+/* bug 3007
+  type: char, int, long, long long
+ */
+#include 
+
+{type} a = 0;
+
+void inc(void)
+{
+  a++;
+}
+
+void testBug(void)
+{
+  {type} i;
+  for (i = 0; i < ({type})300; i++)
+    inc();
+  ASSERT (a == ({type})300);
+}
+
+{type} a1, a2;
+
+void inc2(void)
+{
+  while(--a1)
+    a2++;
+}
+
+void testBug2(void)
+{
+  a1 = 31;
+  inc2();
+  ASSERT(a1 == 0);
+  ASSERT(a2 == 30);
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/bug-3027.c sdcc-4.2.0+dfsg/support/regression/tests/bug-3027.c
--- sdcc-4.0.0+dfsg/support/regression/tests/bug-3027.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/bug-3027.c	2020-06-08 07:22:43.000000000 +0000
@@ -0,0 +1,17 @@
+/*
+   bug-3027.c - loop induction left iTemp marked used in a deleted iCode,
+                causing segfault in loop narrowing
+ */
+
+#include 
+
+void f(int **p, int x)
+{
+  for (unsigned int i=0; i<100; i++)
+    *p[i] = x;
+}
+
+void testBug(void)
+{
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/bug-3040.c sdcc-4.2.0+dfsg/support/regression/tests/bug-3040.c
--- sdcc-4.0.0+dfsg/support/regression/tests/bug-3040.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/bug-3040.c	2020-07-01 13:56:17.000000000 +0000
@@ -0,0 +1,27 @@
+/* bug 3040
+   crash in pdk code generation when both operands of an additive operator are block-scope static const int.
+   type: char, signed char, unsigned char, signed int, unsigned int, signed long, unsigned long, signed long long, unsigned long long
+ */
+#include 
+
+{type} f(void)
+{
+  static const {type} a;
+  static const {type} b;
+  return a + b;
+}
+
+{type} g(void)
+{
+  static const {type} a;
+  static const {type} b;
+  return a - b;
+}
+
+void testBug(void)
+{
+# if 0 // Bug #3073.
+	ASSERT(!f());
+#endif
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/bug-3043.c sdcc-4.2.0+dfsg/support/regression/tests/bug-3043.c
--- sdcc-4.0.0+dfsg/support/regression/tests/bug-3043.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/bug-3043.c	2020-06-12 21:33:57.000000000 +0000
@@ -0,0 +1,34 @@
+/* bug 3048
+   stm8 and pdk code generator hang on shift by negative literal
+   type: char, signed char, unsigned char, signed int, unsigned int, signed long, unsigned long, signed long long, unsigned long long
+ */
+#include 
+
+#pragma disable_warning 259
+
+void g(void)
+{
+}
+
+void fr({type} x)
+{
+  if (((x >> -1))) // Undefined behaviour, but we should be fine if this is never executed at runtime.
+    g();
+}
+
+void fl({type} x)
+{
+  if (((x << -1))) // Undefined behaviour, but we should be fine if this is never executed at runtime.
+    g();
+}
+
+void testBug(void)
+{
+  volatile _Bool b = 0;
+  {type} i = 0x5a;
+  if (b)
+    fr(i);
+  if (b)
+    fl(i);
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/bug-3056.c sdcc-4.2.0+dfsg/support/regression/tests/bug-3056.c
--- sdcc-4.0.0+dfsg/support/regression/tests/bug-3056.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/bug-3056.c	2020-06-18 06:40:05.000000000 +0000
@@ -0,0 +1,33 @@
+/*
+   bug-3056.c - function name not promoted to function pointer
+                inside conditional operator
+ */
+
+#include 
+
+unsigned char x;
+
+void f1(void)
+{
+  x = 1;
+}
+
+void f2(void)
+{
+  x = 2;
+}
+
+void bug(int i)
+{
+  (i ? f1 : f2)();
+}
+
+void testBug(void)
+{
+  ASSERT(x == 0);
+  bug(1);
+  ASSERT(x == 1);
+  bug(0);
+  ASSERT(x == 2);
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/bug-3065.c sdcc-4.2.0+dfsg/support/regression/tests/bug-3065.c
--- sdcc-4.0.0+dfsg/support/regression/tests/bug-3065.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/bug-3065.c	2020-06-25 07:14:34.000000000 +0000
@@ -0,0 +1,23 @@
+/* bug 3065
+   pdk backend generating invalid asm for some bitwise and on __sfr-
+ */
+#include 
+
+#if defined(__SDCC_pdk13) || defined(__SDCC_pdk14) || defined(__SDCC_pdk15)
+
+__sfr __at(0x10) _pa;
+#define PA        _pa
+
+unsigned char b = 0;
+
+void f(void)
+{
+    PA &= (unsigned char)~(1<
+
+#include 
+
+typedef uint16_t atom;
+
+struct node {
+    atom lhs;
+    atom rhs;
+};
+
+#define MAX_NODES 10
+
+static struct node nodes[MAX_NODES];
+uint16_t node_freelist = 0;
+
+atom alloc_node(atom lhsval, atom rhsval)
+{
+    atom a = node_freelist;
+    node_freelist = nodes[a].lhs;
+    nodes[a].lhs = lhsval;
+    nodes[a].rhs = rhsval;
+    return a;
+}
+
+void testBug(void)
+{
+    nodes[0].lhs = 23;
+
+    atom a = alloc_node(0xa5a5, 0x5a5a);
+
+    ASSERT (nodes[0].lhs == 0xa5a5);
+    ASSERT (nodes[0].rhs == 0x5a5a);
+    ASSERT (node_freelist == 23);
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/bug-3079.c sdcc-4.2.0+dfsg/support/regression/tests/bug-3079.c
--- sdcc-4.0.0+dfsg/support/regression/tests/bug-3079.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/bug-3079.c	2020-07-05 06:17:17.000000000 +0000
@@ -0,0 +1,30 @@
+/* bug-3079.c
+   A crash in code generation for 8-bit parameters to __smallc functions.
+ */
+ 
+#include 
+
+#if !defined(__SDCC_z80) && !defined(__SDCC_z180) && !defined(__SDCC_gz80)
+#define __smallc
+#endif
+
+unsigned char func2()
+{
+	return 0xa5;
+}
+
+int esxdos_f_read(unsigned char handle) __smallc
+{
+	ASSERT (handle == 0xa5);
+	return 0;
+}
+
+void
+testBug(void)
+{
+        unsigned char h;
+
+        h =func2();
+        esxdos_f_read(h); // SIGSEGV when h allocated to lower half of register pair.
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/bug-3080.c sdcc-4.2.0+dfsg/support/regression/tests/bug-3080.c
--- sdcc-4.0.0+dfsg/support/regression/tests/bug-3080.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/bug-3080.c	2020-07-17 09:16:59.000000000 +0000
@@ -0,0 +1,31 @@
+/* bug-3080.c
+   A crash in code generation for some I/O operations.
+ */
+ 
+#include 
+
+#if defined(__SDCC_pdk13) || defined(__SDCC_pdk14) || defined(__SDCC_pdk15)
+
+#define PB_ADDR             0x13
+__sfr __at(PB_ADDR)          pb;
+#define PB                   pb
+
+unsigned char test;
+
+void f(void)
+{
+  PB = ~PB;
+}
+
+void g(void)
+{
+  PB |= 0;
+}
+
+#endif
+
+void
+testBug(void)
+{
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/bug-3081.c sdcc-4.2.0+dfsg/support/regression/tests/bug-3081.c
--- sdcc-4.0.0+dfsg/support/regression/tests/bug-3081.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/bug-3081.c	2021-01-03 09:47:54.000000000 +0000
@@ -0,0 +1,41 @@
+/* bug-3081.c
+   z80 backend inserted extra whitespace in call vie __z88dk_fastcall function pointer 
+   for --reserve-regs-iy, confusing peephole optimizer
+ */
+
+
+#include 
+
+#include 
+
+#if defined(__SDCC_mcs51) || defined(__SDCC_pdk14) || defined(__SDCC_pdk15)
+#ifdef __z88dk_fastcall
+#undef __z88dk_fastcall
+#endif
+#define __z88dk_fastcall __reentrant
+#elif !(defined(__SDCC_z80) || defined(__SDCC_z180))
+#define __z88dk_fastcall
+#endif
+
+short example(short x) __z88dk_fastcall
+{
+    return x+1;
+}
+
+short (*ifunc)(short arg) __z88dk_fastcall;
+
+int m()
+{
+    int i, sum;
+    ifunc = example;
+    sum = 0;
+    for (i = 0; i < 42; ++i)
+	sum += (ifunc)(i);
+    return sum;
+}
+
+void
+testBug(void)
+{
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/bug-3083.c sdcc-4.2.0+dfsg/support/regression/tests/bug-3083.c
--- sdcc-4.0.0+dfsg/support/regression/tests/bug-3083.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/bug-3083.c	2020-07-31 16:53:54.000000000 +0000
@@ -0,0 +1,33 @@
+/* bug-3083.c
+   Invalid asm generated for bitwise or of variable allocated to a with sfr.
+ */
+
+#include 
+
+#include 
+
+#if defined (__SDCC_pdk14) || defined (__SDCC_pdk15)
+__sfr __at(0x0c) _integs;
+#else
+unsigned char _integs;
+#endif
+
+#define INTEGS _integs
+
+struct {
+  uint8_t val;
+} my_struct;
+
+volatile uint8_t val = 123;
+
+void f(void)
+{
+  INTEGS |= val; // works
+  INTEGS |= my_struct.val; // error
+}
+
+void
+testBug(void)
+{
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/bug-3085.c sdcc-4.2.0+dfsg/support/regression/tests/bug-3085.c
--- sdcc-4.0.0+dfsg/support/regression/tests/bug-3085.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/bug-3085.c	2020-07-17 09:38:23.000000000 +0000
@@ -0,0 +1,26 @@
+/* bug-3085.c
+   Pdk code generation for wide < overwrote upper byte of operand in p.
+ */
+ 
+#include 
+
+#include 
+
+uint16_t f(void)
+{
+  uint16_t cc = 0;
+  for (uint16_t j = 0; j < 500; j++) { // Code generation for upper byte for < overwrote upper byte of j.
+    cc++;
+  }
+
+  cc = ~cc;
+
+  return cc;
+}
+
+void
+testBug(void)
+{
+  ASSERT (f() == (uint16_t)(~(uint16_t)500));
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/bug-3087.c sdcc-4.2.0+dfsg/support/regression/tests/bug-3087.c
--- sdcc-4.0.0+dfsg/support/regression/tests/bug-3087.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/bug-3087.c	2020-07-29 19:58:25.000000000 +0000
@@ -0,0 +1,60 @@
+/* bug-3087.c
+   A bug in z80 register allocation resultingin broken code for gbz80.
+ */
+
+#include 
+
+#ifndef PORT_HOST
+#pragma disable_warning 84
+#endif
+
+void Proc_2 (int *Int_Par_Ref)
+{
+	Int_Par_Ref;
+}
+
+void Proc_7 (int Int_1_Par_Val, int Int_2_Par_Val, int *Int_Par_Ref)
+{
+	Int_1_Par_Val;
+	Int_2_Par_Val;
+	*Int_Par_Ref = 1;
+}
+
+
+int f(void)
+{
+  int       Int_1_Loc;
+  int       Int_2_Loc;
+  int       Int_3_Loc;
+  int       Run_Index;
+  int       Number_Of_Runs;
+
+  Number_Of_Runs = 2;
+
+  for (Run_Index = 1; Run_Index <= Number_Of_Runs; ++Run_Index)
+  {
+
+    Int_1_Loc = 2;
+    Int_2_Loc = 3;
+
+    while (Int_1_Loc < Int_2_Loc)
+    {
+      Proc_7 (Int_1_Loc, Int_2_Loc, &Int_3_Loc);
+      Int_1_Loc += 1;
+    }
+
+    Int_2_Loc = Int_2_Loc * Int_1_Loc;
+    Int_1_Loc = Int_2_Loc / Int_3_Loc;
+    Int_2_Loc = 7 * (Int_2_Loc - Int_3_Loc) - Int_1_Loc; // Operand overwritten on second subtraction.
+    Proc_2 (&Int_1_Loc);
+  }
+
+  return Int_2_Loc;
+}
+
+void
+testBug(void)
+{
+  ASSERT(f() == 47);
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/bug-3090.c sdcc-4.2.0+dfsg/support/regression/tests/bug-3090.c
--- sdcc-4.0.0+dfsg/support/regression/tests/bug-3090.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/bug-3090.c	2020-07-29 19:58:25.000000000 +0000
@@ -0,0 +1,52 @@
+/* bug-3090.c
+   A bug in gbz80 code generation for 16-bit addition with operands allocated to bc and de, result spilt.
+ */
+ 
+#include 
+ 
+#define UINT8           unsigned char
+#define specialchar_nl  '\n'
+
+#define buffer_length (16)
+UINT8 buffer[buffer_length];
+
+UINT8 smart_write(const UINT8 y, const UINT8 height, char *str){
+    UINT8 length;
+    UINT8 run = 1;
+    UINT8 tmp_y = y;
+    UINT8 jump_back = 0;
+    UINT8 ret = 0;
+    // string pointer
+    char *str_ptr = str;
+    while(run){
+        for(length = 0; length < 16; ++length){
+            if(*str_ptr == specialchar_nl || *str_ptr == '\0'){
+                buffer[length] = '\0';
+                break;
+            }
+            buffer[length] = *str_ptr;
+            ++str_ptr;
+            if(jump_back != 0){
+                --jump_back;
+            }
+        }
+        if(*str_ptr == '\0'){
+            run = 0;
+        } else {
+            if(*str_ptr == specialchar_nl)
+                ++str_ptr;
+            tmp_y += 1;
+        }
+        if(tmp_y >= y+height){ // Wrong code generated for addition here.
+            tmp_y = y;
+            ++ret;
+        }
+    }
+    return ret;
+}
+
+void
+testBug(void){
+    ASSERT(smart_write(1, 20, "test\n") == 0);
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/bug-3093.c sdcc-4.2.0+dfsg/support/regression/tests/bug-3093.c
--- sdcc-4.0.0+dfsg/support/regression/tests/bug-3093.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/bug-3093.c	2020-08-19 10:33:23.000000000 +0000
@@ -0,0 +1,50 @@
+/* bug-3093.c
+   An optimization used an incorrect cast to bool.
+ */
+
+#include 
+
+#include 
+#include 
+
+#define UINT8 uint8_t
+#define UINT16 uint16_t
+
+#define U_LESS_THAN(A, B) ((A) - (B) & 0x8000u)
+#define DISTANCE(A, B) (U_LESS_THAN(A, B) ? (B - A) : (A - B))
+
+struct Sprite {
+	UINT8 anim_accum_ticks;
+	UINT8 anim_speed;
+	UINT8 anim_frame;
+	UINT8 frame;
+
+	UINT16 x;
+	UINT16 y;
+};
+
+struct Sprite spr, tgt;
+
+struct Sprite *THIS, *scroll_target;
+
+#define DIST_ACTION 10
+
+int mputs(const char *s)
+{
+    ASSERT (!strcmp (s, "no action"));
+}
+
+void test() {
+    if(U_LESS_THAN(DISTANCE(THIS->x + 8, scroll_target->x + 8), DIST_ACTION)) mputs("action"); else mputs("no action");
+}
+
+void
+testBug(void){
+    spr.x = 10, THIS = &spr;
+    tgt.x = 30, scroll_target = &tgt;
+    test();
+    spr.x = 5;
+    tgt.x = 5;    
+    test();
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/bug-3097.c sdcc-4.2.0+dfsg/support/regression/tests/bug-3097.c
--- sdcc-4.0.0+dfsg/support/regression/tests/bug-3097.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/bug-3097.c	2020-08-12 20:10:18.000000000 +0000
@@ -0,0 +1,68 @@
+/* bug-3097.c
+   gbz80 backend overwrote still-needed value by using hl as address register for a global variable when the to-be-stored value was allocated to h or l.
+ */
+
+
+#include 
+
+#if !defined(__SDCC_mcs51) && !defined(__SDCC_pdk13) && !defined(__SDCC_pdk14) && !defined(__SDCC_pdk15) // Lack of memory
+
+#define max_scene_x 9
+#define max_scene_y 9
+#define max_scene_z 4
+
+#define to_x(x,y,z) ((x) + (y))
+#define to_y(x,y,z) ((7u * 8u) + ((x) << 2u) - ((y) << 2u) - ((z) << 3u))
+#define to_coords(x,y,z) (((x) << 8u) | ((8u - (y)) << 4u) | (z))
+#define from_coords(coord, x, y, z) (x = ((coord) >> 8u), y = (8u - ((coord) >> 4u) & 0x0f), z = ((coord) & 0x0f))
+
+typedef unsigned char UBYTE;
+typedef unsigned int UWORD;
+
+typedef unsigned char scene_t[max_scene_x][max_scene_z][max_scene_y];
+
+typedef struct scene_item_t {
+    UBYTE id, x, y, n;
+    UWORD coords;
+    struct scene_item_t * next;
+} scene_item_t;
+
+scene_t collision_buf;
+
+void clear_map(void * data) {
+    data;
+}
+
+void scene_to_map(const scene_item_t * sour, scene_t * dest) {
+    static scene_item_t * src;
+    static UBYTE x, y, z;
+    
+    clear_map(dest);
+    
+    src = (scene_item_t *)sour;
+    while (src) {
+        from_coords(src->coords, x, y, z);
+        if ((x < max_scene_x) && (y < max_scene_y) && (z < max_scene_z)) {
+            (*dest)[x][z][y] = src->id + 1;
+        }
+        src = src->next;
+    }    
+}
+const scene_item_t scene_items[] = {
+{.id=1, .x=to_x(0, 8, 0), .y=to_y(0, 8, 0), .coords=to_coords(0, 8, 0), .next=&scene_items[1]},
+{.id=1, .x=to_x(0, 8, 1), .y=to_y(0, 8, 1), .coords=to_coords(0, 8, 1), .next=0},
+};
+
+#endif
+
+void
+testBug(void)
+{
+#if !defined(__SDCC_mcs51) && !defined(__SDCC_pdk13) && !defined(__SDCC_pdk14) && !defined(__SDCC_pdk15) // Lack of memory
+    scene_to_map(scene_items, &collision_buf);
+    
+    ASSERT(collision_buf[0][0][max_scene_y - 1] == 2);
+    ASSERT(collision_buf[0][1][max_scene_y - 1] == 2);
+#endif
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/bug-3101.c sdcc-4.2.0+dfsg/support/regression/tests/bug-3101.c
--- sdcc-4.0.0+dfsg/support/regression/tests/bug-3101.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/bug-3101.c	2020-08-22 17:41:15.000000000 +0000
@@ -0,0 +1,58 @@
+/* bug-3101.c
+   A bug in gbz80 code generation when storing a value in l or h onto the stack.
+ */
+
+#include 
+
+#include 
+#include 
+
+typedef unsigned char UBYTE;
+typedef unsigned int UWORD;
+typedef int WORD;
+
+typedef struct {
+    WORD x, y;
+} fly_coord_t; 
+
+fly_coord_t flies[3]; // = {{(14 * 8), (5 * 8)}, {(6 * 8), (9 * 8)}, {(22 * 8), (12 * 8)}};
+fly_coord_t * fly_ptr;
+
+UBYTE __temp_i, __temp_j, __temp_k, __temp_l, __temp_m; 
+
+int my_puts(const char *s)
+{
+    ASSERT (!strcmp(s, "ok"));
+}
+
+fly_coord_t * find_firefly(UBYTE tile_x, UBYTE tile_y) {
+    UBYTE ff_tile_x, ff_tile_y;
+    for (__temp_i = 0; __temp_i < 3; __temp_i++) {
+        fly_ptr = &flies[__temp_i];
+        
+        ff_tile_x = fly_ptr->x >> 3, ff_tile_y = fly_ptr->y >> 3;        
+        
+        if ((ff_tile_x >= tile_x) && (ff_tile_x <= tile_x + 2) &&
+            (ff_tile_y >= tile_y) && (ff_tile_y <= tile_y + 1)) return fly_ptr;
+    }
+    return 0;
+}
+
+UBYTE dizzy_catches_firefly(UBYTE tile_x, UBYTE tile_y, UBYTE id) {
+    id;
+    fly_coord_t * temp_fly;
+    temp_fly = find_firefly(tile_x, tile_y);
+    if (temp_fly) my_puts("ok"); else my_puts("fail");
+    return 0;
+}
+
+
+void
+testBug(void)
+{
+    flies[0].x=7*8;    flies[0].y=16*8+5;
+    flies[1].x=11*8+2; flies[1].y=14*8+3;
+    flies[2].x=18*8;   flies[2].y=5*8+1;
+    dizzy_catches_firefly(10, 14, 0);
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/bug-3102.c sdcc-4.2.0+dfsg/support/regression/tests/bug-3102.c
--- sdcc-4.0.0+dfsg/support/regression/tests/bug-3102.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/bug-3102.c	2022-02-10 12:17:03.000000000 +0000
@@ -0,0 +1,48 @@
+/* bug-3102.c
+   A problem in the interaction of two peephole rules with rare code and an assembler quirk.
+ */
+ 
+#include 
+
+#ifdef __SDCC
+#pragma disable_warning 85
+#endif
+
+static unsigned char Flag[10];
+static unsigned char Object[10];
+
+#define CARRIED		(Flag[2])
+#define WORN		(Flag[3])
+
+static void Message(unsigned char m)
+{
+}
+
+static void DropItem(void)
+{
+}
+
+static void Put(unsigned char obj, unsigned char loc)
+{
+}
+
+static void Wear(unsigned char obj)
+{
+	if (Object[obj] == WORN) {
+		Message(29);
+		return;
+	}
+	if (Object[obj] != CARRIED) {
+		Message(23);
+		return;
+	}
+	DropItem();
+	Put(obj, WORN);
+}
+
+void
+testBug(void)
+{
+	Wear(0);
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/bug-3126.c sdcc-4.2.0+dfsg/support/regression/tests/bug-3126.c
--- sdcc-4.0.0+dfsg/support/regression/tests/bug-3126.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/bug-3126.c	2020-10-08 10:07:06.000000000 +0000
@@ -0,0 +1,44 @@
+/* bug-3126.c
+   A still-needed pointer in register pair hl was overwritten when hl was used for a stack access on gbz80.
+ */
+
+#include 
+
+unsigned char test1;
+unsigned char test2;
+
+typedef struct _BankPtr
+{
+  unsigned char bank;
+  unsigned int offset;
+} BankPtr;
+
+const BankPtr scene_bank_ptrs[] = {{0x06, 0x3C53}};
+
+void TestFn2(unsigned char i)
+{
+  test2 = i;
+}
+
+void TestFn(unsigned int index)
+{
+  unsigned char bank;
+  unsigned int data_ptr;
+
+  bank = scene_bank_ptrs[index].bank;
+  data_ptr = scene_bank_ptrs[index].offset;
+
+  /* This section doesn't matter but the bug doesn't trigger without it */
+  test1 = 1;
+  TestFn2(bank);
+  /**/
+
+  ASSERT(data_ptr == 0x3C53);
+}
+
+void
+testBug(void)
+{
+  TestFn(0);
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/bug-3127.c sdcc-4.2.0+dfsg/support/regression/tests/bug-3127.c
--- sdcc-4.0.0+dfsg/support/regression/tests/bug-3127.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/bug-3127.c	2020-10-11 11:55:42.000000000 +0000
@@ -0,0 +1,64 @@
+/* bug-3126.c
+   32-bit addition used a register that held already-computed result bytes as temporary for upper bytes of literal operand.
+ */
+
+#include 
+
+#include 
+#include 
+
+#ifndef __SDCC_pdk14 // Lack of memory
+
+#if ULONG_MAX == 0xffffffff
+typedef unsigned long UINT4;
+#elif UINT_MAX == 0xffffffff
+typedef unsigned UINT4;
+#elif USHRT_MAX == 0xffffffff
+#else
+#error No suitable UINT4 type
+#endif
+
+void check(const char *format, ...)
+{
+  va_list arg;
+  static int i;
+
+  va_start (arg, format);
+  
+  ASSERT(va_arg(arg, UINT4) == (i ? 0xd76ae33a : 0x67452301));
+  ASSERT(va_arg(arg, UINT4) == 0xefcdab89);
+  ASSERT(va_arg(arg, UINT4) == 0x98badcfe);
+  ASSERT(va_arg(arg, UINT4) == (i > 1 ? 0xc8d2cb98 : 0x10325476));
+  
+  i++;
+  
+  va_end (arg);
+}
+
+void func(UINT4 *buf, UINT4 *in)
+{
+  UINT4 a = buf[0], b = buf[1], c = buf[2], d = buf[3];
+
+  check("%lx %lx %lx %lx\n",a,b,c,d);
+
+  {( a ) +=  ((( ( b ) ) & ( ( c ) )) | ((~ ( b ) ) & ( ( d ) )))  + ( in[ 0] ) + (UINT4)( 3614090360 );} // Bug affected addition here
+
+  check("%lx %lx %lx %lx\n",a,b,c,d);
+
+  {( d ) +=  ((( ( a ) ) & ( ( b ) )) | ((~ ( a ) ) & ( ( c ) )))  + ( in[ 1] ) + (UINT4)( 3905402710 ); }
+
+  check("%lx %lx %lx %lx\n",a,b,c,d);
+}
+#endif
+
+void
+testBug (void)
+{
+#ifndef __SDCC_pdk14 // Lack of memory
+   UINT4 buf[] = {0x67452301,0xefcdab89,0x98badcfe,0x10325476};
+   UINT4 in[] = {0x3ec3,0x0,0x3dc3,0x0,0x3ac3};
+
+   func(buf, in);
+#endif
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/bug-3129.c sdcc-4.2.0+dfsg/support/regression/tests/bug-3129.c
--- sdcc-4.0.0+dfsg/support/regression/tests/bug-3129.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/bug-3129.c	2022-01-16 05:50:33.000000000 +0000
@@ -0,0 +1,472 @@
+/*
+   bug-3129.c
+   Based on an error in the stdcbench self-test. 
+ */
+
+#include 
+
+#ifdef __SDCC
+#pragma disable_warning 85
+#endif
+
+#if !defined(__SDCC_pdk14) && !defined(__SDCC_pdk15) && !defined(__SDCC_mcs51) && !defined(__SDCC_ds390) // Lack of memory
+extern const char stdcbench_name_version_string[];
+
+unsigned long stdcbench(void);
+
+void stdcbench_error(const char *message);
+
+union stdcbench_buffer
+{
+	unsigned char unsigned_char [1536];
+	char basic_char [1536];
+	signed int signed_int [32];
+};
+
+extern union stdcbench_buffer stdcbench_buffer;
+
+#include 
+#include 
+#include 
+
+#include 
+#include 
+typedef uint_least8_t node_t; // Needs to be an unsigned integer type, that has a maximum value >= MAX_N.
+typedef uint_fast8_t count_t; // Needs to be an unsigned type, that has a maximum value >= 2^MAX_K.
+
+#define MAX_K 4
+#define MAX_N 8
+
+bool ref_adjacency_matrix[MAX_N][MAX_N];
+node_t ref_n;
+node_t max_k;
+
+bool check_lnlc(bool);
+
+
+static bool adjacency_matrix[MAX_N][MAX_N];
+static node_t n;
+static node_t node_degrees[MAX_N];
+static node_t degree_list[MAX_N];
+static node_t num_edges;
+
+static node_t k;
+static node_t node_colors[MAX_N];
+
+bool ref_adjacency_matrix[MAX_N][MAX_N];
+node_t ref_n;
+static node_t ref_node_degrees[MAX_N];
+static node_t ref_degree_list[MAX_N];
+static node_t ref_mindeg, ref_maxdeg;
+static node_t ref_num_edges;
+static node_t ref_neighbour_degrees[MAX_N];
+
+node_t max_k;
+
+static char *instructions; /* Should point to a buffer of size at least MAX_N^2 * 80 + MAX_N * MAX_K to get instructions or 0 if those are not needed. */
+
+bool add(void);
+bool recolor(void);
+bool test(void);
+
+/* Add a new, colored node, connect it to a subset of existing colors. */
+bool add(void) __reentrant
+{
+	bool ret = false;
+	node_t sum, ref_sum;
+	node_t i;
+	node_t new_node_color; /* Color of new node */
+	count_t connect_colors; /* Colors new node is connected to (bitmask) */
+
+	node_t node_degrees_backup[MAX_N];
+	node_t degree_list_backup[MAX_N];
+	node_t num_edges_backup;
+
+	memcpy(node_degrees_backup, node_degrees, MAX_N * sizeof(node_t)); /* Copying fixed size is more efficient than copying only the part needed. */
+	memcpy(degree_list_backup, degree_list, MAX_N * sizeof(node_t));
+	num_edges_backup = num_edges;
+
+	for(connect_colors = 0; connect_colors < (1 << k) && !ret; connect_colors++) /* New node can connect to any subset of existing colors. */
+	{
+		node_degrees[n] = 0;
+		n++;
+		memset(adjacency_matrix[n - 1], 0, (n - 1) * sizeof(bool)); /* Doing it once here is faster than having an else branch in the loop below. */
+
+		/* Connect new node to existing nodes. */
+		for(i = 0; i < n - 1; i++)
+			if (connect_colors & (1 << node_colors[i]))
+			{
+				num_edges++;
+				if(num_edges + (ref_n - n) * ref_mindeg / 2 > ref_num_edges) /* Early abort when there are too many edges already. */
+ 					goto tried;
+				if(num_edges - num_edges_backup > ref_maxdeg) /* Early abort when there are too many edges at the new node already. */
+					goto tried;
+
+				adjacency_matrix[n - 1][i] = true;
+
+				degree_list[node_degrees[i]]--;
+				node_degrees[i]++;
+				degree_list[node_degrees[i]]++;
+
+				node_degrees[n - 1]++;
+			}
+		degree_list[node_degrees[n - 1]]++;
+
+		if(num_edges + (ref_n - n) * ref_maxdeg < ref_num_edges) /* Early abort when there are too few edges still. */
+			goto tried;
+
+		if(n == ref_n)
+		{
+			if(test())
+			{
+				if(instructions)
+				{
+					instructions += sprintf(instructions, "Add node %d of color 0, connect it to nodes of the following colors: ", n - 1);
+					for(i = 0; i < k; i++)
+						if (connect_colors & (1 << i))
+							instructions += sprintf(instructions, "%d ", i);
+					instructions += sprintf(instructions, "\n");
+				}
+
+				ret = true;
+			}
+			goto tried;
+		}
+
+		/* Early abort when degrees are too high. */
+		sum = 0;
+		ref_sum = 0;
+		for(i = ref_n - 1; i > 0; i--)
+		{
+			sum += degree_list[i];
+			ref_sum += ref_degree_list[i];
+			if(sum > ref_sum)
+				goto tried;
+		}
+
+		for(new_node_color = 0; new_node_color <= k && new_node_color < max_k; new_node_color++) /* New node uses existing color, or exactly one above. */
+		{
+			node_t k_backup = k;
+
+			if(new_node_color == k)
+				k++;
+
+			node_colors[n - 1] = new_node_color;
+
+			/* Recurse to recoloring. */
+			if(recolor())
+			{
+				if(instructions)
+				{
+					instructions += sprintf(instructions, "Add node %d of color %d, connect it to nodes of the following colors: ", n - 1, new_node_color);
+					for(i = 0; i < k; i++)
+						if (connect_colors & (1 << i))
+							instructions += sprintf(instructions, "%d ", i);
+					instructions +=  sprintf(instructions, "\n");
+				}
+
+				ret = true;
+
+				goto tried;
+			}
+
+			k = k_backup;
+		}
+
+tried:
+		n--;
+		degree_list[n] = 0;
+		memcpy(degree_list, degree_list_backup, MAX_N * sizeof(node_t));
+		memcpy(node_degrees, node_degrees_backup, MAX_N * sizeof(node_t));
+		num_edges = num_edges_backup;
+	}
+
+	return(ret);
+}
+
+static node_t recolormap[MAX_K];
+
+bool do_recolor(void)  __reentrant
+{
+	bool ret = false;
+	node_t i;
+	node_t node_colors_backup[MAX_N];
+	bool used_colors[MAX_N];
+	node_t k_backup;
+
+	/* Skip colorings that would recolor the most recently added node - it could have been added with target color in the first place instead. */
+	if(recolormap[node_colors[n - 1]] != node_colors[n - 1] &&
+		recolormap[node_colors[n - 1]] == recolormap[recolormap[node_colors[n - 1]]]) /* Recoloring the new node just for closing gaps created by recoloring of other nodes is ok. */
+		return(false);
+
+	k_backup = k;
+	memcpy(node_colors_backup, node_colors, MAX_N * sizeof(node_t));
+
+	/* Check coloring */
+	memset(used_colors, 0, MAX_N * sizeof(bool));
+	k = 0;
+	for(i = 0; i < k_backup; i++)
+	{
+		used_colors[recolormap[i]] = true;
+		if(recolormap[i] >= k)
+			k = recolormap[i] + 1;
+	}
+	/* Do not allow gaps in colors. */
+	for(i = 0; i < k; i++)
+		if(!used_colors[i])
+			goto tried;
+
+	/* Recolor graph. */
+	for(i = 0; i < n; i++)
+		node_colors[i] = recolormap[node_colors[i]];
+
+	/* Recurse to node addition. */
+	if(ret = add())
+	{
+		for(i = 0; i < n; i++)
+			if (node_colors[i] != node_colors_backup[i] && instructions)
+				instructions += sprintf(instructions, "Recolor node %d from %d to %d\n", i, node_colors_backup[i], node_colors[i]);
+	}
+
+tried:
+	memcpy(node_colors, node_colors_backup, MAX_N * sizeof(node_t));
+	k = k_backup;
+
+	return(ret);
+}
+
+bool maprecolor(node_t i)  __reentrant
+{
+	node_t j;
+
+	if (i == k) /* Recurse in graph construction algorithm. */
+		return(do_recolor());
+	else /* Recurse in recoloring construction algorithm. */
+		for(j = 0; j <= i; j++)	/* Never consider higher colors for recoloring. */
+		{
+			recolormap[i] = j;
+			if(maprecolor(i + 1))
+				return(true);
+		}
+	return(false);
+}
+
+/* Recolor nodes. */
+bool recolor(void)  __reentrant
+{
+	return(maprecolor(0));
+}
+
+static node_t testperm[MAX_N];
+
+/* Recursively generate permutations for isomorphism test. */
+bool permtest(node_t i) __reentrant
+{
+	node_t j;
+
+	/* Check that all edges to the most recently considered node are ok. */
+	for(j = 0; j + 2 < i; j++)
+		if((testperm[i - 1] > testperm[j] ? adjacency_matrix[testperm[i - 1]][testperm[j]] : adjacency_matrix[testperm[j]][testperm[i - 1]]) != ref_adjacency_matrix[i - 1][j])
+			return(false);
+
+	if(i == n)
+		return(true);
+
+	for(j = i; j < n; j++)
+	{
+		node_t t;
+
+		if (node_degrees[testperm[j]] != ref_node_degrees[i]) /* Do not try permutations where degrees do not match. */
+			continue;
+
+		t = testperm[i];
+		testperm[i] = testperm[j];
+		testperm[j] = t;
+
+		if(permtest(i + 1))
+			return(true);
+
+		t = testperm[i];
+		testperm[i] = testperm[j];
+		testperm[j] = t;
+	}
+
+	return(false);
+}
+
+int cmp(const void *l, const void *r) __reentrant
+{
+	return *((node_t*)r) - *((node_t *)l);
+}
+
+void calc_neighbour_degrees(node_t *restrict neighbour_degrees, bool (*adjacency_matrix)[MAX_N], const node_t *restrict degrees)
+{
+	node_t i, j;
+
+	memset(neighbour_degrees, 0, MAX_N);
+	for(i = 0; i < ref_n; i++)
+		for(j = 0; j < i; j++)
+			if(adjacency_matrix[i][j])
+			{
+				neighbour_degrees[i] += (1 << (degrees[j] - 1));
+				neighbour_degrees[j] += (1 << (degrees[i] - 1));
+			}
+	qsort(neighbour_degrees, ref_n, sizeof(node_t), cmp);
+}
+
+/* Isomorphism test */
+bool test(void)
+{
+	node_t i;
+	node_t neighbour_degrees[MAX_N];
+
+	/* Compare degree list first. */
+	if (memcmp(ref_degree_list, degree_list, n * sizeof(node_t)))
+		return(false);
+
+	/* Compare degress of neighbours next. */
+	calc_neighbour_degrees(neighbour_degrees, adjacency_matrix, node_degrees);
+	if (memcmp(ref_neighbour_degrees, neighbour_degrees, n * sizeof(node_t)))
+		return(false);
+
+	for(i = 0; i < n; i++)
+		testperm[i] = i;
+
+	return(permtest(0));
+}
+
+
+/* Has the graph ref_adjacency_matrix of ref_n nodes linear nlc-width at most k? */
+bool check_lnlc(bool output_instructions)
+{
+	bool ret;
+	char *startinstructions;
+	char *outinstructions = stdcbench_buffer.basic_char;
+	node_t i, j;
+
+	if(!ref_n)
+		return(true);
+
+	memset(ref_node_degrees, 0, MAX_N * sizeof(node_t));
+	memset(ref_degree_list + 1, 0, (MAX_N - 1) * sizeof(node_t));
+	ref_degree_list[0] = ref_n;
+	ref_num_edges = 0;
+	for(i = 0; i < ref_n; i++)
+		for(j = 0; j < i; j++)
+			if(ref_adjacency_matrix[i][j])
+			{
+				ref_degree_list[ref_node_degrees[i]]--;
+				ref_node_degrees[i]++;
+				ref_degree_list[ref_node_degrees[i]]++;
+				ref_degree_list[ref_node_degrees[j]]--;
+				ref_node_degrees[j]++;
+				ref_degree_list[ref_node_degrees[j]]++;
+				ref_num_edges++;
+			}
+
+	for(i = 1, ref_mindeg = ref_maxdeg = ref_node_degrees[0]; i < ref_n; i++)
+	{
+		node_t ref_deg = ref_node_degrees[i];
+		if (ref_deg < ref_mindeg)
+			ref_mindeg = ref_deg;
+		if (ref_deg > ref_maxdeg)
+			ref_maxdeg = ref_deg;
+	}
+
+	calc_neighbour_degrees(ref_neighbour_degrees, ref_adjacency_matrix, ref_node_degrees);
+
+	memset(degree_list, 0, MAX_N * sizeof(node_t));
+	num_edges = 0;
+	k = 0;
+
+	if(output_instructions)
+	{
+		if(!(startinstructions = instructions = malloc (60 + (ref_n) * (72 + max_k / 8 * 2) + (ref_n - 1) * (ref_n - 2) / 2 * 28)))
+			stdcbench_error("c90lib c90lib_lnlc(): malloc() failed\n");
+		else
+			startinstructions[0] = 0;
+	}
+	else
+		startinstructions = instructions = 0;
+	
+	ret = add();
+
+	if (ret && startinstructions)
+	{
+		char *c;
+
+		outinstructions += sprintf(outinstructions, "Instructions for constructing the graph:");
+
+		while(c = strrchr(startinstructions, '\n'))
+		{
+			outinstructions += sprintf(outinstructions, c);
+			*c = 0;
+		}
+		outinstructions += sprintf(outinstructions, "\n%s\n", startinstructions);
+	}
+
+	free(startinstructions);
+
+	return(ret);
+}
+
+static const char resultinstructions[] =
+	"Instructions for constructing the graph:\n"
+	"\n"
+	"Add node 0 of color 0, connect it to nodes of the following colors: \n"
+	"Add node 1 of color 1, connect it to nodes of the following colors: \n"
+	"Add node 2 of color 2, connect it to nodes of the following colors: 0 1 \n"
+	"Add node 3 of color 1, connect it to nodes of the following colors: 0 \n"
+	"Add node 4 of color 0, connect it to nodes of the following colors: 0 1 \n"
+	"Recolor node 2 from 2 to 1\n"
+	"Add node 5 of color 0, connect it to nodes of the following colors: 1 \n";
+
+static volatile const bool prism[6][6] =
+	{{0, 1, 1, 1, 0, 0},
+	{1, 0, 1, 0, 1, 0},
+	{1, 1, 0, 0, 0, 1},
+	{1, 0, 0, 0, 1, 1},
+	{0, 1, 0, 1, 0, 1},
+	{0, 0, 1, 1, 1, 0}};
+
+void c90lib_lnlc(void)
+{
+	node_t i, j;
+
+	ref_n = 6;
+	for(i = 0; i < ref_n; i++)
+		for(j = 0; j < ref_n; j++)
+			ref_adjacency_matrix[i][j] = prism[i][j];
+
+	for(max_k = 0; max_k <= MAX_K; max_k++)
+		if(check_lnlc(true))
+			break;
+
+	if(k != 1 || strcmp(stdcbench_buffer.basic_char, resultinstructions))
+		stdcbench_error("c90lib c90lib_lnlc(): Result validation failed");
+}
+
+#define REG(addr, reg)	__sfr __at(addr) reg
+
+void stdcbench_error(const char *message)
+{
+	ASSERT(0);
+}
+
+extern void c90lib_lnlc(void);
+
+union stdcbench_buffer stdcbench_buffer;
+
+const char stdcbench_name_version_string[] = "stdcbench 0.6";
+#endif
+
+void
+testBug(void)
+{
+#if !defined(__SDCC_mos6502) && !defined(__SDCC_mos65c02) // insufficient stack space
+#if !defined(__SDCC_pdk14) && !defined(__SDCC_pdk15) && !defined(__SDCC_mcs51) && !defined(__SDCC_ds390) // Lack of memory
+	c90lib_lnlc();
+#endif
+#endif
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/bug-3132.c sdcc-4.2.0+dfsg/support/regression/tests/bug-3132.c
--- sdcc-4.0.0+dfsg/support/regression/tests/bug-3132.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/bug-3132.c	2020-10-13 08:57:20.000000000 +0000
@@ -0,0 +1,28 @@
+/*
+   bug-3132.c
+   A bug in pdk code generation for jump on & if all bytes of the mask are 0xff or 0x00 and the highest byte is 0x00.
+ */
+
+#include 
+
+#include 
+
+volatile uint8_t block = 0;
+
+void f(void)
+{
+
+  for( uint16_t t=0; t<0x101; t++ )
+  {
+    if( 0 == (t&0xFF) ) // BUG: this compare is compiled to "if( 0 == t )"
+      block++;
+  }
+}
+
+void
+testBug (void)
+{
+  f();
+  ASSERT (block == 2);
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/bug-3135.c sdcc-4.2.0+dfsg/support/regression/tests/bug-3135.c
--- sdcc-4.0.0+dfsg/support/regression/tests/bug-3135.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/bug-3135.c	2020-10-26 11:52:30.000000000 +0000
@@ -0,0 +1,62 @@
+/* bug-3135.c
+   A stack access overwrote a value held in hl on gbz80.
+ */
+ 
+#include 
+
+typedef unsigned char UBYTE;
+
+#define MAX_PROJECTILES 2
+#define MAX_ACTIVE_ACTORS 3
+#define MAX_ACTORS 4
+
+typedef struct _BankPtr
+{
+  unsigned char bank;
+  unsigned int offset;
+} BankPtr;
+
+typedef struct _PROJECTILE {
+  UBYTE col_group;
+} Projectile;
+
+typedef struct {
+  BankPtr hit_1_ptr;
+  BankPtr hit_2_ptr;
+} Actor;
+
+Projectile projectiles[MAX_PROJECTILES];
+UBYTE actors_active[MAX_ACTIVE_ACTORS];
+Actor actors[MAX_ACTORS];
+
+void TestFn2(BankPtr* events_ptr) {
+  ASSERT (events_ptr->bank == 5 && events_ptr->offset == 0xFC00);
+}
+
+void TestFn() {
+  UBYTE hit;
+  UBYTE i;
+
+  for (i = 0; i != 1; i++) {
+      hit = actors_active[0];
+      if (hit != 0xFF) {
+        if (projectiles[i].col_group == 2) {
+            TestFn2(&actors[hit].hit_1_ptr);
+        } else if (projectiles[i].col_group == 4) {
+            TestFn2(&actors[hit].hit_2_ptr);
+        }
+      }
+  }
+}
+
+void
+testBug(void)
+{
+  projectiles[0].col_group = 2;
+  actors_active[0] = 0;
+  actors[0].hit_1_ptr.bank = 5;
+  actors[0].hit_1_ptr.offset = 0xFC00;
+
+  TestFn();
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/bug-3141.c sdcc-4.2.0+dfsg/support/regression/tests/bug-3141.c
--- sdcc-4.0.0+dfsg/support/regression/tests/bug-3141.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/bug-3141.c	2021-07-10 07:10:07.000000000 +0000
@@ -0,0 +1,25 @@
+/* bug 3141
+   a bug in code generation for stm8 large meory model (24-bit function pointers),
+   when returning function pointers fromk a function with a single 16-bit parameter while optimizing for code size.
+ */
+#include 
+
+#pragma opt_code_size
+
+void f(void)
+{
+}
+
+typedef void (*p) (void);
+
+p g(int b)
+{
+	return (b ? &f : (p)0);
+}
+
+void testBug(void)
+{
+	ASSERT (g(0) == 0);
+	ASSERT (g(1) == &f);
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/bug-3166.c sdcc-4.2.0+dfsg/support/regression/tests/bug-3166.c
--- sdcc-4.0.0+dfsg/support/regression/tests/bug-3166.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/bug-3166.c	2021-07-04 08:59:36.000000000 +0000
@@ -0,0 +1,135 @@
+/*
+   bug-3166.c
+ */
+
+#include 
+
+#define NDEBUG
+#include 
+#include 
+
+#if !defined(__SDCC_pdk13) && !defined(__SDCC_pdk14) && !defined(__SDCC_pdk15) && !(defined(__SDCC_mcs51) && (defined(__SDCC_MODEL_SMALL) || defined(__SDCC_MODEL_MEDIUM))) // Lack of memory
+
+enum { RULES_MAX = 4 };
+
+typedef int* rule_seq;
+typedef rule_seq* rule_alts;
+
+int       rule_seq_lists[] = { 3, 1, 3, -1,
+                               2, -1,
+                               2, 1, -1 };
+rule_seq  rule_alts_lists[] = { &rule_seq_lists[0], NULL,
+                                &rule_seq_lists[4], &rule_seq_lists[6], NULL };
+rule_alts rule[RULES_MAX] = { &rule_alts_lists[0],
+                              &rule_alts_lists[2],
+                              NULL,
+                              NULL };
+char      rule_terminal[RULES_MAX] = { 0, 0, 'a', 'b' };
+
+enum { GOOD_POOL_MAX = 64,
+       BAD_STACK_MAX  = 16 };
+
+struct good {
+   rule_seq seq;
+   struct good* prev;
+} good_pool[GOOD_POOL_MAX+1];  /* +1 to avoid incorrect SDCC warning */
+
+struct bad {
+   rule_alts    alts;
+   char*        old_pos;
+   struct good* old_good;
+} bad_stack[BAD_STACK_MAX+1];  /* +1 to avoid incorrect SDCC warning */
+
+int match(char* pos_arg)
+{
+    static char* pos;
+    static struct bad*  bad_sp;
+#ifdef AVOID_SCCZ80_BUG
+    #define static
+#endif
+    static struct good* good_alloc;
+    static struct good* good;
+    static struct good* rgood;
+    static rule_alts    alts;
+#ifdef AVOID_SDCC_BUG
+           rule_seq     seq;
+#else
+    static rule_seq     seq; /* this line breaks SDCC */
+#endif
+#ifdef AVOID_SCCZ80_BUG
+    #undef static
+#endif
+    static char*        rpos;
+    static int          ruleno;
+    pos        = pos_arg;
+    bad_sp     = bad_stack;
+    good_alloc = good_pool;
+    good       = NULL;
+    rgood      = NULL;
+    alts       = NULL;
+    seq        = NULL;
+    rpos       = NULL;
+    ruleno     = 0;
+
+    while (1) {
+        assert(bad_sp < &bad_stack[BAD_STACK_MAX]);
+        assert(good_alloc < &good_pool[GOOD_POOL_MAX]);
+        assert(ruleno >= 0 && ruleno < RULES_MAX);
+        alts = rule[ruleno];
+        if (alts) {
+            rgood = good;
+            rpos = pos;
+            goto first_alt;
+        }
+        assert(rule_terminal[ruleno]);        
+        if (*pos != rule_terminal[ruleno])
+            goto failure;
+        ++pos;
+    success:
+        if (!good) {
+            if (*pos != '\0')
+                goto failure;
+            return 1;
+        }
+        seq = good->seq;
+        good = good->prev;
+        ruleno = *seq++;
+        if (*seq >= 0) {
+            struct good* ngood = good_alloc++;
+            ngood->seq = seq;
+            ngood->prev = good;
+            good = ngood;
+        }
+        continue;
+    failure:
+        if (bad_sp == bad_stack) {
+            return 0;       
+        }
+        --bad_sp;
+        alts = bad_sp->alts;
+        rgood = bad_sp->old_good;
+        rpos = bad_sp->old_pos;
+    first_alt:
+        good = good_alloc++;
+        good->seq = *alts++;
+        good->prev = rgood;
+        pos = rpos;
+        if (*alts) {
+            bad_sp->alts = alts;
+            bad_sp->old_good = rgood;
+            bad_sp->old_pos  = pos;
+            ++bad_sp;
+        }
+        goto success;
+    }
+}
+#endif
+
+void
+testBug(void)
+{
+#if !defined(__SDCC_pdk13) && !defined(__SDCC_pdk14) && !defined(__SDCC_pdk15) && !(defined(__SDCC_mcs51) && (defined(__SDCC_MODEL_SMALL) || defined(__SDCC_MODEL_MEDIUM))) // Lack of memory
+    ASSERT (match("baaab"));
+#endif
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/bug-3167.c sdcc-4.2.0+dfsg/support/regression/tests/bug-3167.c
--- sdcc-4.0.0+dfsg/support/regression/tests/bug-3167.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/bug-3167.c	2022-01-09 00:53:30.000000000 +0000
@@ -0,0 +1,23 @@
+/*
+   bug-3167.c
+   a crash in z80 code generation on __sfr right subtraction operand.
+ */
+
+#include 
+
+#if !defined(PORT_HOST) && !defined(__SDCC_stm8) && !defined(__SDCC_hc08) && !defined(__SDCC_s08) && !defined(__SDCC_mos6502) && !defined(__SDCC_mos65c02)&& !defined(__SDCC_mcs51) && !defined(__SDCC_ds390) && !defined(__SDCC_tlcs90)
+unsigned char effect_y_line;
+volatile __sfr __at(0x02) reg_SCY;
+volatile __sfr __at(0x04) reg_LY;
+
+void f(void) {
+    effect_y_line = 10;
+    reg_SCY = effect_y_line - reg_LY;
+}
+#endif
+
+void
+testBug(void)
+{
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/bug-3169.c sdcc-4.2.0+dfsg/support/regression/tests/bug-3169.c
--- sdcc-4.0.0+dfsg/support/regression/tests/bug-3169.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/bug-3169.c	2021-01-21 13:34:00.000000000 +0000
@@ -0,0 +1,52 @@
+/*
+   bug-3169.c
+   A bug in z80 pointer write code generation handling of non-dead register pair de when using --reserve-regs-iy.
+ */
+
+#include 
+
+typedef unsigned char uint8_t;
+typedef unsigned int uint16_t;
+typedef unsigned char bool;
+
+typedef struct _Struct {
+  uint8_t abyte1;
+  uint8_t abyte2;
+  uint16_t aint;
+} Struct;
+
+Struct storage;
+
+uint16_t srcInt;
+bool flag;
+
+extern void fn1(const Struct*) __z88dk_fastcall;
+
+void f() {
+
+  storage.abyte1 = 1;
+  storage.abyte2 = 10;
+
+  if (flag) {
+    storage.aint = srcInt;
+    fn1(&storage);
+
+    return;
+  }
+
+  storage.aint = 1;
+  fn1(&storage);
+}
+
+void fn1(const Struct *sp) __z88dk_fastcall
+{
+  ASSERT(sp == &storage);
+}
+
+void
+testBug(void)
+{
+  flag = 1;
+  f();
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/bug-3172.c sdcc-4.2.0+dfsg/support/regression/tests/bug-3172.c
--- sdcc-4.0.0+dfsg/support/regression/tests/bug-3172.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/bug-3172.c	2021-01-27 09:48:07.000000000 +0000
@@ -0,0 +1,51 @@
+/*
+   bug-3172.c
+   An issue in variable-argument argument promotion. Most backends, when not using --std-cXX, omit integer promotion on explicitly variable cast arguments.
+   
+   promotion: PROMOTE, NOPROMOTE
+ */
+
+#include 
+
+#define {promotion}
+
+#if defined(__SDCC) && defined(PROMOTE)
+#pragma std_c99
+#elif defined(__SDCC) && defined(NOPROMOTE)
+#pragma std_sdcc99
+#endif
+
+#include 
+
+void
+receive(const char *s, ...)
+{
+	va_list ap;
+	
+	va_start(ap, s);
+#if defined(__SDCC) && defined(NOPROMOTE) && !defined(__SDCC_pdk13) && !defined(__SDCC_pdk14) && !defined(__SDCC_pdk15)
+#if 0 // Bug #3172 not yet fixed.
+	ASSERT(va_arg(ap, unsigned char) == 0x5a);
+	ASSERT(va_arg(ap, unsigned char) == 0xa5);
+#endif
+#else
+	ASSERT(va_arg(ap, int) == 0x5a);
+	ASSERT(va_arg(ap, int) == 0xa5);
+#endif
+	va_end(ap);
+}
+
+void
+testPass(void)
+{
+	receive(0, (unsigned char)0x5a, (unsigned char)0xa5);
+	
+	unsigned char i1 = 0x5a;
+	unsigned char i2 = 0xa5;
+	receive(0, (unsigned char)i1, (unsigned char)i2);
+	
+	unsigned char *p1 = &i1;
+	unsigned char *p2 = &i2;
+	receive(0, (unsigned char)(*p1), (unsigned char)(*p2));
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/bug-3178.c sdcc-4.2.0+dfsg/support/regression/tests/bug-3178.c
--- sdcc-4.0.0+dfsg/support/regression/tests/bug-3178.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/bug-3178.c	2021-02-09 21:58:36.000000000 +0000
@@ -0,0 +1,21 @@
+/*
+   bug-3178.c
+   a bug in peephole optimizer helper function that affects empty functions
+   with function arguments when compiled with#
+   --opt-code-size --reserve-regs-iy and targeting z80 or z180.
+ */
+ 
+#include 
+
+#pragma opt_code_size
+#pragma disable_warning 85
+
+static void L (char c) { } // Bug messed up stack frame here.
+
+void
+testBug (void)
+{
+    L('L');
+    ASSERT (1);
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/bug-3205.c sdcc-4.2.0+dfsg/support/regression/tests/bug-3205.c
--- sdcc-4.0.0+dfsg/support/regression/tests/bug-3205.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/bug-3205.c	2021-04-04 19:37:18.000000000 +0000
@@ -0,0 +1,31 @@
+/*
+whatever
+*/
+
+#include 
+
+volatile char c[1];
+
+#define INVOKE_1(X) X
+#define INVOKE_2(X) INVOKE_1(X) INVOKE_1(X)
+#define INVOKE_4(X) INVOKE_2(X) INVOKE_2(X)
+#define INVOKE_8(X) INVOKE_4(X) INVOKE_4(X)
+#define INVOKE_16(X) INVOKE_8(X) INVOKE_8(X)
+#define INVOKE_32(X) INVOKE_16(X) INVOKE_16(X)
+#define INVOKE_64(X) INVOKE_32(X) INVOKE_32(X)
+#define INVOKE_128(X) INVOKE_64(X) INVOKE_64(X)
+#define INVOKE_256(X) INVOKE_128(X) INVOKE_128(X)
+#define INVOKE_512(X) INVOKE_256(X) INVOKE_256(X)
+#define INVOKE_1024(X) INVOKE_512(X) INVOKE_512(X)
+#define INVOKE_2048(X) INVOKE_1024(X) INVOKE_1024(X)
+
+void
+testBug (void)
+{
+#if 0 // Bug  no yet fixed
+#if !defined(__SDCC_pdk14) // Lack of memory
+	INVOKE_2048(c[0] = 0;)
+#endif
+#endif
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/bug-3215.c sdcc-4.2.0+dfsg/support/regression/tests/bug-3215.c
--- sdcc-4.0.0+dfsg/support/regression/tests/bug-3215.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/bug-3215.c	2021-05-01 07:34:15.000000000 +0000
@@ -0,0 +1,43 @@
+/*
+   bug-3215.c
+   A bug in merging sequences of puts
+ */
+
+#include 
+
+#include 
+
+void foo(void);
+
+int
+bug ()
+{
+    puts ("1");
+    puts ("2");
+
+    foo();
+
+    // Second sequence used same string as first one.
+    puts ("4");
+    puts ("5");
+    return 0;
+}
+
+#ifndef PORT_HOST
+int putchar (int c)
+{
+	static int i;
+	ASSERT (c == "1\n2\n4\n5\n"[i++]);
+}
+#endif
+
+void foo(void)
+{
+}
+
+void
+testBug(void)
+{
+	bug ();
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/bug-3216.c sdcc-4.2.0+dfsg/support/regression/tests/bug-3216.c
--- sdcc-4.0.0+dfsg/support/regression/tests/bug-3216.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/bug-3216.c	2021-04-24 14:14:36.000000000 +0000
@@ -0,0 +1,41 @@
+/*
+   bug-3216.c
+   A bug in r3ka code generation for 32-bit additions in handling iy
+ */
+
+#include 
+
+unsigned long c90base(void);
+unsigned long c90lib(void);
+
+unsigned long c90base_score, c90lib_score;
+
+unsigned long stdcbench(void)
+{
+	unsigned long score = 0;
+
+	score += c90base_score = c90base();
+
+	score += c90lib_score = c90lib();
+
+	return(score);
+}
+
+unsigned long c90base(void)
+{
+	return 0x01020304ul;
+}
+
+unsigned long c90lib(void)
+{
+	return 0x10203040ul;
+}
+
+void
+testBug (void)
+{
+	ASSERT(stdcbench() == 0x11223344ul);
+	ASSERT(c90base_score == 0x01020304ul);
+	ASSERT(c90lib_score == 0x10203040ul);
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/bug-3223.c sdcc-4.2.0+dfsg/support/regression/tests/bug-3223.c
--- sdcc-4.0.0+dfsg/support/regression/tests/bug-3223.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/bug-3223.c	2021-05-04 08:38:46.000000000 +0000
@@ -0,0 +1,33 @@
+/*
+   bug-3223.c
+   A bug in tracking of register pair hl over ldir
+ */
+
+#include 
+
+typedef unsigned long   uint32;
+typedef unsigned short  addr16;
+typedef unsigned short  uint16;
+typedef unsigned char   uint8;
+
+uint32* memory = 0;
+
+void memWrite(uint32 sectorNumber){
+    uint16 value = 200;
+    uint32* byte51202 = memory + 02;
+    *byte51202 = sectorNumber;
+    memory[3]=100;
+    memory[0]=value;
+}
+
+void
+testBug (void)
+{
+    uint32 buffer[4];
+    memory = buffer;
+    memWrite(42);
+    ASSERT(buffer[2] == 42);
+    ASSERT(buffer[3] == 100);
+    ASSERT(buffer[0] == 200);
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/bug-3229.c sdcc-4.2.0+dfsg/support/regression/tests/bug-3229.c
--- sdcc-4.0.0+dfsg/support/regression/tests/bug-3229.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/bug-3229.c	2021-05-07 21:37:27.000000000 +0000
@@ -0,0 +1,32 @@
+/*
+   bug-3229.c
+   A bug in code generation for __z88dk_callee functions returning long long
+ */
+ 
+#include 
+
+long long f0(void) __z88dk_callee
+{
+  return 0xa5;
+}
+
+long long f1(int i) __z88dk_callee
+{
+  return 0xa5 + i;
+}
+
+long long f4(long long l) __z88dk_callee
+{
+  return 0xa5 + l;
+}
+
+void
+testBug (void)
+{
+  volatile long long l = 0xaa55;
+  ASSERT (f0()  == 0xa5);
+  ASSERT (f1(1) == 0xa6);
+  ASSERT (f4(2) == 0xa7);
+  ASSERT (l == 0xaa55);
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/bug-3230.c sdcc-4.2.0+dfsg/support/regression/tests/bug-3230.c
--- sdcc-4.0.0+dfsg/support/regression/tests/bug-3230.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/bug-3230.c	2021-05-08 20:19:03.000000000 +0000
@@ -0,0 +1,23 @@
+/*
+   bug-3230.c
+   A bug in code generation for __z88dk_callee __smallc functions with parameters wider than char
+ */
+
+#include 
+
+unsigned int f2(unsigned int c) __smallc __z88dk_callee
+{
+	return c + 1;
+}
+
+unsigned int s2(unsigned int c, unsigned int d) __smallc __z88dk_callee
+{
+	return c - d;
+}
+
+void testBug(void)
+{
+	ASSERT (f2(2) == 3);
+	ASSERT (s2(2, 3) == -1);
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/bug-3231.c sdcc-4.2.0+dfsg/support/regression/tests/bug-3231.c
--- sdcc-4.0.0+dfsg/support/regression/tests/bug-3231.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/bug-3231.c	2021-05-11 09:51:44.000000000 +0000
@@ -0,0 +1,30 @@
+/*
+   bug-3230.c
+   A bug in code generation for __z88dk_callee __critical functions with parameters.
+ */
+
+#include 
+
+#if defined(__SDCC_mcs51) || defined(__SDCC_z80) || defined(__SDCC_z180) || defined(__SDCC_r2k) || defined(__SDCC_r2ka) || defined(__SDCC_r3ka) || defined(__SDCC_hc08) || defined(__SDCC_s08) || defined(__SDCC_tlcs90) || defined(__SDCC_stm8)
+volatile int j;
+
+void f0(int i) __z88dk_callee __critical
+{
+	j = i;
+}
+
+int f1(int i) __z88dk_callee __critical
+{
+	return (i + j);
+}
+#endif
+
+void testBug(void)
+{
+#if defined(__SDCC_mcs51) || defined(__SDCC_z80) || defined(__SDCC_z180) || defined(__SDCC_r2k) || defined(__SDCC_r2ka) || defined(__SDCC_r3ka) || defined(__SDCC_hc08) || defined(__SDCC_s08) || defined(__SDCC_tlcs90) || defined(__SDCC_stm8)
+	f0(23);
+	ASSERT (j == 23);
+	ASSERT (f1(23) == 46);
+#endif
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/bug-3238.c sdcc-4.2.0+dfsg/support/regression/tests/bug-3238.c
--- sdcc-4.0.0+dfsg/support/regression/tests/bug-3238.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/bug-3238.c	2021-05-17 13:45:17.000000000 +0000
@@ -0,0 +1,41 @@
+/*
+   bug-3238.c. Spilt register parameters were not correctly checked for having their address taken
+   resulting in incorrect tail call optimization, thus calls where spilt local variables in the calle
+   overwrote the spilt register parameter.
+ */
+
+#include 
+
+#include 
+
+int *c;
+
+void bar(void);
+
+void foo(int a) __z88dk_fastcall
+{
+  c = &a;
+  bar();
+}
+
+void check(char *buffer)
+{
+	ASSERT (*c == 23);
+	ASSERT (buffer[0] == 42);
+}
+
+void bar(void)
+{
+	char buffer[8];
+	memset(buffer, 42, 8);
+	check(buffer);
+}
+
+void
+testBug (void)
+{
+  foo(23);
+  return;
+}
+
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/bug-3239.c sdcc-4.2.0+dfsg/support/regression/tests/bug-3239.c
--- sdcc-4.0.0+dfsg/support/regression/tests/bug-3239.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/bug-3239.c	2021-05-17 17:19:37.000000000 +0000
@@ -0,0 +1,32 @@
+/*
+   bug-3239.c. A jump was incorrectly redirected to a non-exisitng label in the peephole optimizer when the name of the callee was a prefix of the caller's name.
+ */
+ 
+#include 
+
+#ifdef __SDCC
+#pragma std_c99
+#endif
+
+#ifndef __SDCC_stm8
+#define __cosmic
+#endif
+
+unsigned char f(unsigned char i) __cosmic;
+
+unsigned char f_wrap_cosmic(unsigned char i) __cosmic
+{
+	return f(i);
+}
+
+void
+testBug (void)
+{
+	ASSERT (f_wrap_cosmic (23) == 42);
+}
+
+unsigned char f(unsigned char i) __cosmic
+{
+	return i == 23 ? 42 : 3;
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/bug-3240.c sdcc-4.2.0+dfsg/support/regression/tests/bug-3240.c
--- sdcc-4.0.0+dfsg/support/regression/tests/bug-3240.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/bug-3240.c	2021-05-17 13:45:17.000000000 +0000
@@ -0,0 +1,40 @@
+/*
+   bug-3240.c. Stack register parameters were not correctly checked for having their address taken
+   resulting in incorrect tail call optimization, thus calls where spilt local variables in the calle
+   overwrote the spilt register parameter.
+ */
+
+#include 
+
+#include 
+
+void bar(void);
+
+int *p;
+
+void foo(int a) __z88dk_callee
+{
+	p = &a;
+	bar();
+}
+
+void check(char *buffer)
+{
+	ASSERT (*p == 23);
+	ASSERT (buffer[0] == 42);
+}
+
+void bar(void)
+{
+	char buffer[8];
+	memset(buffer, 42, 8);
+	check(buffer);
+}
+
+void
+testBug (void)
+{
+  foo(23);
+  return;
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/bug-3242.c sdcc-4.2.0+dfsg/support/regression/tests/bug-3242.c
--- sdcc-4.0.0+dfsg/support/regression/tests/bug-3242.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/bug-3242.c	2021-05-18 10:26:51.000000000 +0000
@@ -0,0 +1,33 @@
+/*
+   bug-3240.c. A bug in z80 code generation regarding handling of register pair hl.
+ */
+
+#include 
+
+typedef unsigned short uint16;
+
+uint16 x, y;
+
+char flag;
+
+static uint16 printHello() {
+    flag = 1;
+    return 1;
+}
+
+static uint16 hello(uint16 a, uint16 b) {
+    uint16 result = 0;
+    if(a + b > x - y){
+        result = printHello();
+    }
+    return result;
+}
+
+void
+testBug(void) {
+    x = 2000;
+    y = 1000;
+    hello(600,600);
+    ASSERT (flag);
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/bug-3244.c sdcc-4.2.0+dfsg/support/regression/tests/bug-3244.c
--- sdcc-4.0.0+dfsg/support/regression/tests/bug-3244.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/bug-3244.c	2021-06-11 10:22:54.000000000 +0000
@@ -0,0 +1,43 @@
+/*
+   bug-3240.c. A bug in z80 code generation on comparisons with 0x00 lower bytes.
+ */
+ 
+#include 
+
+#include 
+
+#ifndef PORT_HOST
+#pragma disable_warning 85
+#endif
+
+uint16_t p = 0x202;
+
+int aprintf(const char *c, ...)
+{
+  ASSERT(0);
+}
+
+int bprintf(const char *c, ...)
+{
+  ASSERT(1);
+}
+
+void f(void)
+{
+  if (p < 0x0200)
+    aprintf("1. First time it does not evaluate to TRUE\r\n");
+  else
+    bprintf("2. First time it does evaluate to FALSE\r\n");
+
+  if (p < 0x0200)
+    aprintf("3. But now it incorrectly evaluates to TRUE\r\n");
+  else
+    bprintf("4. It should have been FALSE\r\n");
+}
+
+void
+testBug (void)
+{
+  f();
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/bug-3251.c sdcc-4.2.0+dfsg/support/regression/tests/bug-3251.c
--- sdcc-4.0.0+dfsg/support/regression/tests/bug-3251.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/bug-3251.c	2021-06-11 10:22:54.000000000 +0000
@@ -0,0 +1,27 @@
+/*
+   bug-3251.c An assertion failure in stm8 code generation.
+   convention: , __raisonance, __iar, __cosmic
+ */
+ 
+#include 
+
+#ifdef __SDCC_stm8
+int f(int i, int j, int (*c)(int , int) {convention})
+{
+	return (*c)(i, j);
+}
+
+int add(int i, int j) {convention}
+{
+	return(i + j);
+}
+#endif
+
+void
+testBug(void)
+{
+#ifdef __SDCC_stm8
+	ASSERT (f(1, 1, add) == 2);
+#endif
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/bug-3256.c sdcc-4.2.0+dfsg/support/regression/tests/bug-3256.c
--- sdcc-4.0.0+dfsg/support/regression/tests/bug-3256.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/bug-3256.c	2021-06-20 17:45:21.000000000 +0000
@@ -0,0 +1,30 @@
+/*
+   bug-3256.c
+   A bug in the stm8 peephole optimizer for functions calls through function pointers where the caller has no non-pointer calls, and the callee has register arguments.
+ */
+
+#include 
+
+#ifndef __SDCC_stm8
+#define __raisonance
+#endif
+
+int (*volatile twocharargptr)(char, char) __raisonance __reentrant;
+
+int f(void)
+{
+	return (*twocharargptr)(23, 42);
+}
+
+int twochararg(char a, char b) __raisonance __reentrant
+{
+	return a + b;
+}
+
+void
+testBug(void)
+{
+	twocharargptr = &twochararg;
+	ASSERT (f() == 23 + 42);
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/bug-3257.c sdcc-4.2.0+dfsg/support/regression/tests/bug-3257.c
--- sdcc-4.0.0+dfsg/support/regression/tests/bug-3257.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/bug-3257.c	2021-06-16 20:52:18.000000000 +0000
@@ -0,0 +1,28 @@
+/*
+   bug-3256.c
+   A bug in the stm8 code generation for tail calls from __z88dk_callee with stack parameters.
+ */
+
+#include 
+
+char
+g (void)
+{
+  return 23;
+}
+
+char
+f (unsigned short a, unsigned short b) __z88dk_callee
+{
+  if (a == b)
+    return g ();
+  return 42;
+}
+
+void
+testBug (void)
+{
+  ASSERT (f (23, 23) == 23);
+  ASSERT (f (23, 42) == 42);
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/bug-3260.c sdcc-4.2.0+dfsg/support/regression/tests/bug-3260.c
--- sdcc-4.0.0+dfsg/support/regression/tests/bug-3260.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/bug-3260.c	2021-07-19 09:49:35.000000000 +0000
@@ -0,0 +1,41 @@
+#include 
+
+/* Bug #3260 caused typecast function pointers to pass all */
+/* parameters via the stack and not pass any paramter via  */
+/* register, even when some should have been passed via    */
+/* register. */
+
+/* Look for __SDCC_STACK_AUTO to make sure the port is     */
+/* parameters in registers and/or stack and not statically */
+#if defined(__SDCC_STACK_AUTO) || defined(PORT_HOST)
+int (*p)(int, int) __reentrant;
+
+void (*q)(void) __reentrant;
+
+int f(void)
+{
+    return (*p)(23, 42);
+}
+
+int g(void)
+{
+    return (*(((int (*)(int, int))q)))(23, 42);
+}
+
+int c(int a, int b) __reentrant
+{
+    return a - b;
+}
+#endif
+
+void
+testBug(void)
+{
+#if defined(__SDCC_STACK_AUTO) || defined(PORT_HOST)
+    p = &c;
+    q = (void (*)(void))(&c);
+    ASSERT (f() == 23 - 42);
+    ASSERT (g() == 23 - 42);
+#endif
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/bug-3276.c sdcc-4.2.0+dfsg/support/regression/tests/bug-3276.c
--- sdcc-4.0.0+dfsg/support/regression/tests/bug-3276.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/bug-3276.c	2022-01-15 22:05:18.000000000 +0000
@@ -0,0 +1,29 @@
+/* bug-3276.c
+ * A billion became zero when converted to and from float.  Also test related range issues.
+ */
+
+#include 
+
+volatile unsigned long ul1;
+volatile unsigned long ul2;
+volatile float f1;
+
+void
+testBug(void)
+{
+#if !defined(__SDCC_pdk14)
+    ul1 = 1000000000ul;
+    f1 = (float)ul1;
+    ASSERT (f1 == 1000000000.0f);
+    ul2 = (unsigned long)f1;
+    ASSERT (ul2 == ul1);
+    ul1 = 4000000000ul;
+    f1 = (float)ul1;
+    ASSERT (f1 == 4000000000.0f);
+    ul2 = (unsigned long)f1;
+    ASSERT (ul2 == ul1);
+    ul1 = 0xfffffffful;
+    f1 = (float)ul1;
+    ASSERT (f1 == 4294967296.0f);
+#endif
+}
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/bug-3282.c sdcc-4.2.0+dfsg/support/regression/tests/bug-3282.c
--- sdcc-4.0.0+dfsg/support/regression/tests/bug-3282.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/bug-3282.c	2021-09-22 09:27:01.000000000 +0000
@@ -0,0 +1,45 @@
+/*
+   bug-3282.c. On stm8, the register allocator decided that one byte of a stack-pointer-relative address
+   should be rematerialized, and the other stored in a register. stm8 code generation can't handle that yet.
+ */
+
+#include 
+
+void g1(void);
+
+void f1(void)
+{
+	_Bool i;
+	if (&i)
+		g1();
+}
+
+void g2(void);
+
+void f2(void)
+{
+	_Bool i;
+	_Bool *volatile p = &i;
+	if (p)
+		g2();
+}
+
+void
+testBug (void)
+{
+	f1();
+	f2();
+}
+
+int g;
+
+void g1(void)
+{
+	ASSERT(++g == 1);
+}
+
+void g2(void)
+{
+	ASSERT(++g == 2);
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/bug-3283.c sdcc-4.2.0+dfsg/support/regression/tests/bug-3283.c
--- sdcc-4.0.0+dfsg/support/regression/tests/bug-3283.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/bug-3283.c	2021-09-22 09:27:01.000000000 +0000
@@ -0,0 +1,58 @@
+/*
+   bug-3283.c. On z80, a veriable allocated to iy was overwritten by the use of iy for an address at a cast.
+ */
+
+#include 
+
+#pragma disable_warning 85
+
+typedef struct object_d {
+    unsigned char code;
+    char *desc;
+    unsigned int position;
+    unsigned char attributes;
+} object;
+
+
+object *odummy;
+unsigned char current_position;
+
+char *message1006;
+char *message1005;
+
+extern object *search_object_p(unsigned int o);
+extern void show_message(const char *m);
+
+unsigned char get(unsigned int o)
+{
+    odummy=search_object_p(o); // odummy in iy.
+    if(odummy->position!=current_position) { // a cast from unsigned char to unsigned int here used iy to point to current_position.
+        show_message(message1006);
+    } else if((odummy->attributes&1)==0) {
+        show_message(message1005);
+    } else {
+        odummy->position=1500; // odummy used again here.
+        return 0;
+    }
+    return 1;
+}
+
+object obj = {0, 0, 0, 1};
+
+void
+testBug (void)
+{
+    ASSERT(!get(0));
+    ASSERT(obj.position==1500);
+}
+
+object *search_object_p(unsigned int o)
+{
+    return &obj;
+}
+
+void show_message(const char *m)
+{
+    ASSERT (0);
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/bug-3289.c sdcc-4.2.0+dfsg/support/regression/tests/bug-3289.c
--- sdcc-4.0.0+dfsg/support/regression/tests/bug-3289.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/bug-3289.c	2022-02-14 08:34:29.000000000 +0000
@@ -0,0 +1,17 @@
+/*
+   bug-3289.c
+   A bug in the frontend in handling enum scope
+   */
+
+#include 
+
+void testBug(void)
+{
+  enum { EV1 = 3, EV2 = 13, EV3 = 7 };
+
+  volatile int test1;
+  test1 = EV2;   //this works as expected
+  volatile int test2;
+  test2 = EV2;   //BUG: ==> test.c:8: error 20: Undefined identifier 'EV2'
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/bug-3296.c sdcc-4.2.0+dfsg/support/regression/tests/bug-3296.c
--- sdcc-4.0.0+dfsg/support/regression/tests/bug-3296.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/bug-3296.c	2021-12-10 14:48:15.000000000 +0000
@@ -0,0 +1,79 @@
+/*
+   bug-3229.c
+   A crash in code generation for stm8 in the modular inversion of the NTRU reference implementation.
+ */
+ 
+#include 
+
+#include 
+#include 
+
+#define NTRU_N 67 // Smallest prime for which the bug could be reproduced.
+
+typedef struct{
+  uint16_t coeffs[NTRU_N];
+} poly;
+
+static inline uint8_t mod3(uint8_t a) /* a between 0 and 9 */
+{
+  int16_t t, c;
+  a = (a >> 2) + (a & 3); /* between 0 and 4 */
+  t = a - 3;
+  c = t >> 5;
+  return (uint8_t) (t^(c&(a^t)));
+}
+
+/* return -1 if x<0 and y<0; otherwise return 0 */
+static inline int16_t both_negative_mask(int16_t x,int16_t y)
+{
+  return (x & y) >> 15;
+}
+
+#if !defined(__SDCC_mcs51) && !defined(__SDCC_sm83) && !defined(__SDCC_pdk13) && !defined(__SDCC_pdk14) && !defined(__SDCC_pdk15) && !defined(__SDCC_pdk16) // Lack of memory
+void poly_S3_inv(poly *r, const poly *a)
+{
+  poly f, g, v, w;
+  size_t i,loop;
+  int16_t delta,sign,swap,t;
+
+  for (i = 0;i < NTRU_N;++i) v.coeffs[i] = 0;
+  for (i = 0;i < NTRU_N;++i) w.coeffs[i] = 0;
+  w.coeffs[0] = 1;
+
+  for (i = 0;i < NTRU_N;++i) f.coeffs[i] = 1;
+  for (i = 0;i < NTRU_N-1;++i) g.coeffs[NTRU_N-2-i] = mod3((a->coeffs[i] & 3) + 2*(a->coeffs[NTRU_N-1] & 3));
+  g.coeffs[NTRU_N-1] = 0;
+
+  delta = 1;
+
+  for (loop = 0;loop < 2*(NTRU_N-1)-1;++loop) {
+    for (i = NTRU_N-1;i > 0;--i) v.coeffs[i] = v.coeffs[i-1];
+    v.coeffs[0] = 0;
+
+    sign = mod3((uint8_t) (2 * g.coeffs[0] * f.coeffs[0]));
+    swap = both_negative_mask(-delta,-(int16_t) g.coeffs[0]);
+    delta ^= swap & (delta ^ -delta);
+    delta += 1;
+
+    for (i = 0;i < NTRU_N;++i) {
+      t = swap&(f.coeffs[i]^g.coeffs[i]); f.coeffs[i] ^= t; g.coeffs[i] ^= t;
+      t = swap&(v.coeffs[i]^w.coeffs[i]); v.coeffs[i] ^= t; w.coeffs[i] ^= t;
+    }
+
+    for (i = 0;i < NTRU_N;++i) g.coeffs[i] = mod3((uint8_t) (g.coeffs[i]+sign*f.coeffs[i]));
+    for (i = 0;i < NTRU_N;++i) w.coeffs[i] = mod3((uint8_t) (w.coeffs[i]+sign*v.coeffs[i]));
+    for (i = 0;i < NTRU_N-1;++i) g.coeffs[i] = g.coeffs[i+1];
+    g.coeffs[NTRU_N-1] = 0;
+  }
+
+  sign = f.coeffs[0];
+  for (i = 0;i < NTRU_N-1;++i) r->coeffs[i] = mod3((uint8_t) (sign*v.coeffs[NTRU_N-2-i]));
+  r->coeffs[NTRU_N-1] = 0;
+}
+#endif
+
+void
+testBug (void)
+{
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/bug-3320.c sdcc-4.2.0+dfsg/support/regression/tests/bug-3320.c
--- sdcc-4.0.0+dfsg/support/regression/tests/bug-3320.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/bug-3320.c	2022-02-16 22:32:19.000000000 +0000
@@ -0,0 +1,24 @@
+/*
+   bug-3320.c
+   A variable scope issue resulting in an invalid compile-time error message.
+   */
+
+#include 
+
+char c;
+
+void foo()
+{
+  char *dest = &c;
+  {
+    *dest++ |= 1;
+  }
+}
+
+void testBug(void)
+{
+  c = 42;
+  foo ();
+  ASSERT (c == 43);
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/bug-3322.c sdcc-4.2.0+dfsg/support/regression/tests/bug-3322.c
--- sdcc-4.0.0+dfsg/support/regression/tests/bug-3322.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/bug-3322.c	2022-02-16 22:32:19.000000000 +0000
@@ -0,0 +1,113 @@
+/*
+   bug-3322.c
+   A z80 code generation (overwriting a value in iy during an assignment) bug found by z88dk
+   */
+
+#include 
+
+#define PIECE_IS_NEXT 255
+
+#define STARTBOARD_X 15
+#define STARTBOARD_Y 2
+
+#define POS_NEXT_X 3
+#define POS_NEXT_Y 1
+
+#define NEXT_X (POS_NEXT_X+2)
+#define NEXT_Y (POS_NEXT_Y+3)
+
+#define EMPTY_GR_CHAR  32
+#define EMPTY_GR_COLOR 0
+#define FONTS 0
+
+typedef unsigned char byte;
+
+// tetromino sprite
+typedef struct {
+   int x;          // signed integers to allow negative board positions
+   int y;          // -1 means piece is preview ("next")
+   byte piece;
+   byte angle;
+} sprite;
+
+#define gr4_tile(x,y,tile,color,tileset) _gr4_tile_x = (x); _gr4_tile_y = (y); _gr4_tile_tile = (tile); _gr4_tile_color = (color); _gr4_tile_tileset = (tileset); _gr4_tile()
+
+byte _gr4_tile_x;
+byte _gr4_tile_y;
+byte _gr4_tile_tile;
+byte _gr4_tile_color;
+byte *_gr4_tile_tileset;
+
+byte *_gr4_tile_source;
+byte *_gr4_tile_dest;
+
+void _gr4_tile() {
+}
+
+// offset of a single tile composing a piece
+typedef struct {
+   byte offset_x;
+   byte offset_y;
+} tile_offset;
+
+tile_offset *get_piece_offsets(byte piece, byte angle);
+
+tile_offset pieces_XY[4] = {  
+   {+1,+1}  ,  {+2,+1}  ,  {+3,+1}  ,  {+1,+2}  ,
+};
+
+void SLOT1_VIDEO_START() {
+}
+
+void SLOT1_END() {
+}
+
+// given a piece number and an angle returns the 4 byte "offsets" of the piece
+tile_offset *get_piece_offsets(byte piece, byte angle) {
+   return &pieces_XY[(piece*sizeof(tile_offset)*4*2)+angle*4];
+}
+
+void gr_erasepiece(sprite *p);
+
+// erase piece from the screen
+void gr_erasepiece(sprite *p) {
+   tile_offset *data = get_piece_offsets(p->piece, p->angle);   // bug if this declaration is here
+
+   int px = p->x;
+   int py = p->y;
+
+   // are we erasing the "next" piece ?
+   if(py==PIECE_IS_NEXT) {
+      px = NEXT_X;
+      py = NEXT_Y;
+   }
+   else {
+      px += STARTBOARD_X;
+      py += STARTBOARD_Y;
+   }
+
+   // tile_offset *data = get_piece_offsets(p->piece, p->angle);   // no bug if this declaration is here
+
+   SLOT1_VIDEO_START();
+   for(byte t=0; t<4; t++) {
+      int x = px + data->offset_x;
+      int y = py + data->offset_y;      
+      data++;
+      gr4_tile((byte)x,(byte)y,EMPTY_GR_CHAR,EMPTY_GR_COLOR,FONTS);
+   }
+   SLOT1_END();
+}
+
+void testBug(void)
+{
+   sprite s;
+
+   s.x = 0;
+   s.y = 0;
+   s.piece = 0;
+   s.angle = 0;
+   gr_erasepiece(&s);
+   ASSERT(_gr4_tile_x == s.x + STARTBOARD_X + pieces_XY[3].offset_x);
+   ASSERT(_gr4_tile_y == s.y + STARTBOARD_Y + pieces_XY[3].offset_y);
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/bug-3332.c sdcc-4.2.0+dfsg/support/regression/tests/bug-3332.c
--- sdcc-4.0.0+dfsg/support/regression/tests/bug-3332.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/bug-3332.c	2022-02-26 16:53:55.000000000 +0000
@@ -0,0 +1,55 @@
+/*
+   bug-3322.c
+   A bug in __naked __sdcccall(N) functions (as opposed to __sdcccall(0) __naked, which worked)
+   */
+
+#include 
+
+#pragma disable_warning 85
+
+#if defined(__SDCC_stm8) || defined(__SDCC_z80) || defined(__SDCC_z180) || defined(__SDCC_z80n) || defined(__SDCC_sm83)
+#define NAKED __naked
+#define SDCCCALL0 __sdcccall(0)
+#else
+#define NAKED
+#define SDCCCALL0
+#endif
+
+static unsigned char test_2(const unsigned char foo) NAKED SDCCCALL0  {
+#if defined(__SDCC_stm8) && defined(__SDCC_MODEL_MEDIUM)
+    __asm
+        ld   a, (0x03, sp)
+        inc  a
+        ret
+    __endasm;
+#elif defined(__SDCC_stm8) && defined(__SDCC_MODEL_LARGE)
+    __asm
+        ld   a, (0x04, sp)
+        inc  a
+        retf
+    __endasm;
+#elif defined(__SDCC_z80) || defined(__SDCC_z180) || defined(__SDCC_z80n)
+    __asm
+        ld   iy, #2
+        add  iy, sp
+        ld   l, 0 (iy)
+        inc  l
+        ret
+    __endasm;
+#elif defined(__SDCC_sm83)
+    __asm
+        ldhl sp,	#2
+        ld   e, (hl)
+        inc  e
+        ret
+    __endasm;
+#else
+    return foo + 1;
+#endif
+}
+
+void testBug(void) {
+    volatile unsigned char bar = test_2(23);
+    ASSERT(bar == 24);
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/bug3379723.c sdcc-4.2.0+dfsg/support/regression/tests/bug3379723.c
--- sdcc-4.0.0+dfsg/support/regression/tests/bug3379723.c	2019-04-16 10:04:43.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/bug3379723.c	2022-01-09 00:53:30.000000000 +0000
@@ -4,7 +4,7 @@
 
 #include 
 
-#if !defined(PORT_HOST) && !defined(__SDCC_hc08) && !defined(__SDCC_s08) && !defined(__SDCC_gbz80) && !defined(__SDCC_stm8) && !defined(__SDCC_tlcs90) && !defined(__SDCC_pdk14) && !defined(__SDCC_pdk15)
+#if !defined(PORT_HOST) && !defined(__SDCC_hc08) && !defined(__SDCC_s08) && !defined(__SDCC_mos6502) && !defined(__SDCC_mos65c02) && !defined(__SDCC_sm83) && !defined(__SDCC_stm8) && !defined(__SDCC_tlcs90) && !defined(__SDCC_pdk14) && !defined(__SDCC_pdk15)
 
 #define UCHAR	unsigned char
 
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/callee_saves.c sdcc-4.2.0+dfsg/support/regression/tests/callee_saves.c
--- sdcc-4.0.0+dfsg/support/regression/tests/callee_saves.c	2014-05-04 17:23:19.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/callee_saves.c	2020-04-21 09:55:12.000000000 +0000
@@ -4,7 +4,7 @@
 
 #include 
 
-#if defined (__mcs51) && !defined (SDCC_MODEL_HUGE)
+#if defined (__SDCC_mcs51) && !defined (__SDCC_MODEL_HUGE)
 
 int x(int a, int b)
 {
@@ -31,7 +31,7 @@
 
 void testBug(void)
 {
-#if defined (__mcs51) && !defined (SDCC_MODEL_HUGE)
+#if defined (__SDCC_mcs51) && !defined (__SDCC_MODEL_HUGE)
 	int a = g;
 	ASSERT (y(1, 2) == 3);
 	ASSERT (a == 100);
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/critical.c sdcc-4.2.0+dfsg/support/regression/tests/critical.c
--- sdcc-4.0.0+dfsg/support/regression/tests/critical.c	2015-09-16 12:24:21.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/critical.c	2022-01-09 00:53:30.000000000 +0000
@@ -26,7 +26,7 @@
 }
 #endif
 
-#if defined(__SDCC_mcs51) || defined(__SDCC_z80) || defined(__SDCC_z180) || defined(__SDCC_r2k) || defined(__SDCC_r3ka) || defined(__SDCC_hc08) || defined(__SDCC_s08) || defined(__SDCC_tlcs90) || defined(__SDCC_stm8)
+#if defined(__SDCC_mcs51) || defined(__SDCC_z80) || defined(__SDCC_z180) || defined(__SDCC_r2k) || defined(__SDCC_r2ka) || defined(__SDCC_r3ka) || defined(__SDCC_hc08) || defined(__SDCC_s08) || defined(__SDCC_mos6502) || defined(__SDCC_mos65c02) || defined(__SDCC_tlcs90) || defined(__SDCC_stm8)
 // Check that param offsets are correctly adjusted for critial functions
 long critical_function(long a, long b, long c) __critical
 {
@@ -84,7 +84,7 @@
   ASSERT (1);
 #endif
 
-#if defined(__SDCC_mcs51) || defined(__SDCC_z80) || defined(__SDCC_z180) || defined(__SDCC_r2k) || defined(__SDCC_r3ka) || defined(__SDCC_hc08) || defined(__SDCC_s08) || defined(__SDCC_tlcs90) || defined(__SDCC_stm8)
+#if defined(__SDCC_mcs51) || defined(__SDCC_z80) || defined(__SDCC_z180) || defined(__SDCC_r2k) || defined(__SDCC_r2ka) || defined(__SDCC_r3ka) || defined(__SDCC_hc08) || defined(__SDCC_s08) || defined(__SDCC_mos6502) || defined(__SDCC_mos65c02) || defined(__SDCC_tlcs90) || defined(__SDCC_stm8)
   ASSERT(critical_function(11, 1, 1) == 13);
   ASSERT(critical_function(5, 1, 1) == 3);
   ASSERT(critical_function(5, 11, 1) == 15);
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/digit_separators.c sdcc-4.2.0+dfsg/support/regression/tests/digit_separators.c
--- sdcc-4.0.0+dfsg/support/regression/tests/digit_separators.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/digit_separators.c	2020-12-03 22:06:56.000000000 +0000
@@ -0,0 +1,21 @@
+/** 
+  ISO C23 digit separators.
+*/
+
+#include 
+
+#ifdef __SDCC
+#pragma std_c2x
+#endif
+
+void
+testDigitSeparators(void)
+{
+#ifdef __SDCC
+  ASSERT (1'120'377 == 1120377);
+  ASSERT (0b0'00'11'00'01 == 0b000110001);
+  ASSERT (0x01'ff'5a == 0x01ff5a);
+  ASSERT (012'3'4 == 01234);
+#endif
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/enum.c sdcc-4.2.0+dfsg/support/regression/tests/enum.c
--- sdcc-4.0.0+dfsg/support/regression/tests/enum.c	2017-04-26 22:23:51.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/enum.c	2020-05-10 16:54:59.000000000 +0000
@@ -35,6 +35,12 @@
   SIGNED_NEG = -1
 } se;
 
+enum comma {
+  COMMA_ZERO,
+  COMMA_ONE,
+  COMMA_TWO, // Trailing comma after enumerator list is a C99 feature.
+}; 
+
 volatile enum _IntEnum {
   INT_256 = 256,
   INT_ZERO = 0
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/gcc-torture-execute-20000113-1.c sdcc-4.2.0+dfsg/support/regression/tests/gcc-torture-execute-20000113-1.c
--- sdcc-4.0.0+dfsg/support/regression/tests/gcc-torture-execute-20000113-1.c	2019-10-21 10:27:24.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/gcc-torture-execute-20000113-1.c	2020-04-29 15:04:34.000000000 +0000
@@ -29,8 +29,6 @@
 void
 testTortureExecute (void)
 {
-#if !(defined(__SDCC_pdk15) && defined(__SDCC_STACK_AUTO)) // Bug #2937
   foobar (1, 2, 3);
-#endif
 }
 
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/gcc-torture-execute-20000412-2.c sdcc-4.2.0+dfsg/support/regression/tests/gcc-torture-execute-20000412-2.c
--- sdcc-4.0.0+dfsg/support/regression/tests/gcc-torture-execute-20000412-2.c	2019-10-14 11:33:28.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/gcc-torture-execute-20000412-2.c	2022-01-09 00:53:30.000000000 +0000
@@ -8,7 +8,7 @@
 #pragma std_c99
 #endif
 
-#if !(defined (__SDCC_hc08) || defined (__SDCC_s08))
+#if !(defined (__SDCC_hc08) || defined (__SDCC_s08) || defined (__SDCC_mos6502) || defined (__SDCC_mos65c02) )
 int f(int a,int *y)
 {
   int x = a;
@@ -24,7 +24,7 @@
 testTortureExecute (void)
 {
 #ifndef __SDCC_pic16
-#if !(defined (__SDCC_mcs51) || defined (__SDCC_hc08) || defined (__SDCC_s08) || defined (__SDCC_ds390) || defined (__SDCC_pdk13) || defined (__SDCC_pdk14) || defined (__SDCC_pdk15))
+#if !(defined (__SDCC_mcs51) || defined (__SDCC_hc08) || defined (__SDCC_s08) || defined (__SDCC_mos6502) || defined (__SDCC_mos65c02) || defined (__SDCC_ds390) || defined (__SDCC_pdk13) || defined (__SDCC_pdk14) || defined (__SDCC_pdk15))
 #if !defined(__SDCC_pic14) // Unsupported reentrancy
   if (f (10, (int *) 0) != 1)
     ASSERT (0);
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/gcc-torture-execute-20031012-1.c sdcc-4.2.0+dfsg/support/regression/tests/gcc-torture-execute-20031012-1.c
--- sdcc-4.0.0+dfsg/support/regression/tests/gcc-torture-execute-20031012-1.c	2019-04-16 10:04:43.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/gcc-torture-execute-20031012-1.c	2021-12-10 14:48:15.000000000 +0000
@@ -25,7 +25,7 @@
 
 static void foo ()
 {
-#if !defined (__SDCC_gbz80) && !defined (__SDCC_mcs51) && !defined (__SDCC_stm8) && !defined (__SDCC_pdk14) && !defined (__SDCC_pdk15)
+#if !defined (__SDCC_sm83) && !defined (__SDCC_mcs51) && !defined (__SDCC_stm8) && !defined (__SDCC_pdk14) && !defined (__SDCC_pdk15)
     char a[ARRAY_SIZE]; /* Too big for mcs51 and gbz80 and stm8 and pdk14. */
     a[0]=0;
     memset( &a[0], 0xCD, STRLEN );
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/gcc-torture-execute-20040409-1.c sdcc-4.2.0+dfsg/support/regression/tests/gcc-torture-execute-20040409-1.c
--- sdcc-4.0.0+dfsg/support/regression/tests/gcc-torture-execute-20040409-1.c	2020-01-09 14:10:52.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/gcc-torture-execute-20040409-1.c	2021-04-22 09:01:18.000000000 +0000
@@ -99,6 +99,8 @@
 void
 testTortureExecute (void)
 {
+#if !(defined(__clang__) && __clang_major__ <= 11)
+
 #if INT_MAX == 2147483647
   ftest(0x00000000,0x80000000);
   ftest(0x80000000,0x00000000);
@@ -132,5 +134,6 @@
 #endif
 
   return;
-}
 
+#endif // __clang__
+}
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/gcc-torture-execute-20040409-2.c sdcc-4.2.0+dfsg/support/regression/tests/gcc-torture-execute-20040409-2.c
--- sdcc-4.0.0+dfsg/support/regression/tests/gcc-torture-execute-20040409-2.c	2020-01-09 14:10:52.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/gcc-torture-execute-20040409-2.c	2021-04-22 09:01:18.000000000 +0000
@@ -192,6 +192,8 @@
 void
 testTortureExecute (void)
 {
+#if !(defined(__clang__) && __clang_major__ <= 11)
+
 #if INT_MAX == 2147483647
   ftest(0x00000000,0x80001234);
   ftest(0x00001234,0x80000000);
@@ -224,5 +226,6 @@
 #endif
 
   return;
-}
 
+#endif // __clang__
+}
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/gcc-torture-execute-20040409-3.c sdcc-4.2.0+dfsg/support/regression/tests/gcc-torture-execute-20040409-3.c
--- sdcc-4.0.0+dfsg/support/regression/tests/gcc-torture-execute-20040409-3.c	2020-01-09 14:10:52.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/gcc-torture-execute-20040409-3.c	2021-04-22 09:01:18.000000000 +0000
@@ -99,6 +99,8 @@
 void
 testTortureExecute (void)
 {
+#if !(defined(__clang__) && __clang_major__ <= 11)
+
 #if INT_MAX == 2147483647
   ftest(0x00000000,0x7fffffff);
   ftest(0x80000000,0xffffffff);
@@ -132,5 +134,6 @@
 #endif
 
   return;
-}
 
+#endif // __clang__
+}
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/gcc-torture-execute-20060110-volatile.c sdcc-4.2.0+dfsg/support/regression/tests/gcc-torture-execute-20060110-volatile.c
--- sdcc-4.0.0+dfsg/support/regression/tests/gcc-torture-execute-20060110-volatile.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/gcc-torture-execute-20060110-volatile.c	2021-04-07 12:39:18.000000000 +0000
@@ -0,0 +1,32 @@
+/*
+   Modified 20060110-?.c from the execute part of the gcc torture suite.
+   Volatile input to trigger some peephole rules for STM8
+ */
+
+#include 
+
+#ifdef __SDCC
+#pragma std_c99
+#endif
+
+#if !defined(__SDCC_pic14) && !defined(__SDCC_pic16) && !defined(__SDCC_pdk14) // Lack of memory
+long long 
+f (volatile long long a, volatile long long b) 
+{ 
+  return ((a + b) << 32) >> 32; 
+} 
+
+long long a = 0x1234567876543210LL;
+long long b = 0x2345678765432101LL;
+long long c = ((0x1234567876543210LL + 0x2345678765432101LL) << 32) >> 32;
+#endif
+
+void
+testTortureExecute (void)
+{
+#if !defined(__SDCC_pic14) && !defined(__SDCC_pic16) && !defined(__SDCC_pdk14) // Lack of memory
+  ASSERT (f (a, b) == c);
+  return;
+#endif
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/gcc-torture-execute-920711-1.c sdcc-4.2.0+dfsg/support/regression/tests/gcc-torture-execute-920711-1.c
--- sdcc-4.0.0+dfsg/support/regression/tests/gcc-torture-execute-920711-1.c	2018-03-12 07:03:22.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/gcc-torture-execute-920711-1.c	2022-02-01 19:25:12.000000000 +0000
@@ -16,7 +16,7 @@
 void
 testTortureExecute (void)
 {
-#if !(defined (__GNUC__) && (__GNUC__ < 5)) && !defined(__POWERPC__)
+#if !(defined (__GNUC__) && (__GNUC__ <= 6)) && !defined(__POWERPC__)
   if(f (0x80000000L) == 0)
     ASSERT(0);
   return;
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/gcc-torture-execute-921208-1.c sdcc-4.2.0+dfsg/support/regression/tests/gcc-torture-execute-921208-1.c
--- sdcc-4.0.0+dfsg/support/regression/tests/gcc-torture-execute-921208-1.c	2019-04-16 10:04:43.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/gcc-torture-execute-921208-1.c	2022-01-09 00:53:30.000000000 +0000
@@ -9,7 +9,7 @@
 #pragma disable_warning 93
 #endif
 
-#if !defined(__SDCC_hc08) && !defined(__SDCC_s08) && !defined(__SDCC_pdk14) && !defined(__SDCC_pdk15)
+#if !defined(__SDCC_hc08) && !defined(__SDCC_s08) && !defined(__SDCC_mos6502) && !defined(__SDCC_mos65c02) && !defined(__SDCC_pdk14) && !defined(__SDCC_pdk15)
 double
 f(double x)
 {
@@ -26,7 +26,7 @@
 void
 testTortureExecute (void)
 {
-#if !defined(__SDCC_hc08) && !defined(__SDCC_s08) && !defined(__SDCC_pdk14) && !defined(__SDCC_pdk15)
+#if !defined(__SDCC_hc08) && !defined(__SDCC_s08) && !defined(__SDCC_mos6502) && !defined(__SDCC_mos65c02) && !defined(__SDCC_pdk14) && !defined(__SDCC_pdk15)
   if (Int(&f,2.0) != 4.0)
     ASSERT(0);
   return;
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/gcc-torture-execute-930702-1.c sdcc-4.2.0+dfsg/support/regression/tests/gcc-torture-execute-930702-1.c
--- sdcc-4.0.0+dfsg/support/regression/tests/gcc-torture-execute-930702-1.c	2019-04-16 10:04:43.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/gcc-torture-execute-930702-1.c	2022-01-09 00:53:30.000000000 +0000
@@ -19,7 +19,7 @@
 void
 testTortureExecute (void)
 {
-#if !defined(__SDCC_hc08) && !defined(__SDCC_s08) && !defined(__SDCC_ds390) && !defined(__SDCC_mcs51) && !defined(__SDCC_pdk14) && !defined(__SDCC_pdk15)
+#if !defined(__SDCC_hc08) && !defined(__SDCC_s08) && !defined(__SDCC_mos6502) && !defined(__SDCC_mos65c02) && !defined(__SDCC_ds390) && !defined(__SDCC_mcs51) && !defined(__SDCC_pdk14) && !defined(__SDCC_pdk15)
   int (*f) (double, int) = fp;
 
   fp (33, 11);
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/gcc-torture-execute-941021-1.c sdcc-4.2.0+dfsg/support/regression/tests/gcc-torture-execute-941021-1.c
--- sdcc-4.0.0+dfsg/support/regression/tests/gcc-torture-execute-941021-1.c	2012-03-22 21:42:57.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/gcc-torture-execute-941021-1.c	2022-02-01 19:25:12.000000000 +0000
@@ -22,7 +22,7 @@
 void
 testTortureExecute (void)
 {
-#if !(defined (__GNUC__) && defined (__GNUC_MINOR__) && (__GNUC__ < 5))
+#if !(defined (__GNUC__) && (__GNUC__ <= 6))
   f ((void *) 0, 55.1);
 
   if (glob_dbl != 55.1)
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/gcc-torture-execute-950511-1.c sdcc-4.2.0+dfsg/support/regression/tests/gcc-torture-execute-950511-1.c
--- sdcc-4.0.0+dfsg/support/regression/tests/gcc-torture-execute-950511-1.c	2019-10-21 10:27:24.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/gcc-torture-execute-950511-1.c	2020-04-29 19:21:11.000000000 +0000
@@ -11,7 +11,6 @@
 void
 testTortureExecute (void)
 {
-#if !(defined(__SDCC_pdk15) && defined(__SDCC_STACK_AUTO)) // Bug #2938
 #if !defined(__SDCC_pic14) && !defined(__SDCC_pic16) && !defined(__SDCC_pdk14)
 
   unsigned long long xx;
@@ -24,6 +23,5 @@
   return;
 
 #endif
-#endif
 }
 
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/gcc-torture-execute-991112-1.c sdcc-4.2.0+dfsg/support/regression/tests/gcc-torture-execute-991112-1.c
--- sdcc-4.0.0+dfsg/support/regression/tests/gcc-torture-execute-991112-1.c	2019-04-16 10:04:43.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/gcc-torture-execute-991112-1.c	2022-01-09 00:53:30.000000000 +0000
@@ -24,7 +24,7 @@
 void
 testTortureExecute (void)
 {
-#if !defined (__SDCC_hc08) && !defined (__SDCC_s08) && !defined (__SDCC_ds390) && !defined (__SDCC_mcs51) && !defined (__SDCC_pdk14) && !defined (__SDCC_pdk15)
+#if !defined (__SDCC_hc08) && !defined (__SDCC_s08) && !defined(__SDCC_mos6502) && !defined(__SDCC_mos65c02) && !defined (__SDCC_ds390) && !defined (__SDCC_mcs51) && !defined (__SDCC_pdk14) && !defined (__SDCC_pdk15)
   int (*x)(int, int) = rl_character_len;
   if (x('a', 1) != 1)
     ASSERT (0);
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/gcc-torture-execute-func-ptr-1.c sdcc-4.2.0+dfsg/support/regression/tests/gcc-torture-execute-func-ptr-1.c
--- sdcc-4.0.0+dfsg/support/regression/tests/gcc-torture-execute-func-ptr-1.c	2019-04-16 10:04:43.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/gcc-torture-execute-func-ptr-1.c	2022-01-09 00:53:30.000000000 +0000
@@ -15,7 +15,7 @@
 void
 testTortureExecute (void)
 {
-#if !defined(__SDCC_hc08) && !defined(__SDCC_s08) && !defined(__SDCC_pdk14) && !defined(__SDCC_pdk15)
+#if !defined(__SDCC_hc08) && !defined(__SDCC_s08) && !defined(__SDCC_mos6502) && !defined(__SDCC_mos65c02) && !defined(__SDCC_pdk14) && !defined(__SDCC_pdk15)
   fp = f;
   if (fp ((float) 1) != 1.0)
     ASSERT (0);
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/gcc-torture-execute-pr88714.c sdcc-4.2.0+dfsg/support/regression/tests/gcc-torture-execute-pr88714.c
--- sdcc-4.0.0+dfsg/support/regression/tests/gcc-torture-execute-pr88714.c	2019-11-19 13:00:17.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/gcc-torture-execute-pr88714.c	2020-05-02 14:02:51.000000000 +0000
@@ -36,7 +36,7 @@
 void
 testTortureExecute (void)
 {
-#ifndef __SDCC_pdk14 // Bug
+#ifndef __SDCC_pdk14 // Lack of RAM
   int a[4] = { 8, 9, 10, 11 };
   struct S s = { 1, 2, 3, &a[0] };
   struct T u = { 0, 0, &a[3] };
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/gcc-torture-execute-strlen-4.c sdcc-4.2.0+dfsg/support/regression/tests/gcc-torture-execute-strlen-4.c
--- sdcc-4.0.0+dfsg/support/regression/tests/gcc-torture-execute-strlen-4.c	2019-11-19 12:05:03.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/gcc-torture-execute-strlen-4.c	2022-01-09 00:53:30.000000000 +0000
@@ -40,7 +40,8 @@
 
 void test_array_ptr (void)
 {
-#if 0 // Bug
+#if !defined( __SDCC_pdk14) && !defined( __SDCC_pdk15) // Lack of memory
+#if !defined(__SDCC_hc08) && !defined(__SDCC_s08) && !defined(__SDCC_mos6502) && !defined(__SDCC_mos65c02) // Bug #2987
   /* Compute the length of the string at the refeenced array.  */
   A (*(&a[0][0] + 0), 1);
   A (*(&a[0][0] + 1), 3);
@@ -170,21 +171,20 @@
   A (*(&a[i0][v1] + i0) + i3, 0);
   A (*(&a[i0][v1] + i1) + i5, 0);
 #endif
+#endif
 }
 
-#if 0 // Bug #
 static const A3_28* const pa0 = &a[0];
 static const A3_28* const pa1 = &a[1];
 
 static const A3_28* const paa[] = { &a[0], &a[1] };
-#endif
 
 /* Verify that strlen() involving pointers and arrays of pointers
    to array arguments computes the correct result.  */
 
 void test_ptr_array (void)
 {
-#if 0 // Bug #
+#if 0 // Bug #2987
   int i0 = 0;
   int i1 = i0 + 1;
   int i2 = i1 + 1;
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/getbyte_param.c sdcc-4.2.0+dfsg/support/regression/tests/getbyte_param.c
--- sdcc-4.0.0+dfsg/support/regression/tests/getbyte_param.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/getbyte_param.c	2021-07-27 01:21:59.000000000 +0000
@@ -0,0 +1,33 @@
+/** getbyte_param.c - test for bug #3269
+*/
+#include 
+#include 
+
+void
+fCheckPlus (unsigned char c)
+{
+  ASSERT (c == 0x15);
+}
+void
+fCheckMinus (unsigned char c)
+{
+  ASSERT (c == 0x13);
+}
+void
+getByteParam (unsigned int i)
+{
+  unsigned char c;
+
+  c = i >> 8;
+  c++;
+  fCheckPlus(c);
+  c = i >> 8;
+  c--;
+  fCheckMinus(c);
+}
+
+void
+testGetByte (void)
+{
+  getByteParam(0x147A);
+}
\ No newline at end of file
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/inline.c sdcc-4.2.0+dfsg/support/regression/tests/inline.c
--- sdcc-4.0.0+dfsg/support/regression/tests/inline.c	2019-04-16 10:04:43.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/inline.c	2021-07-12 03:56:21.000000000 +0000
@@ -263,6 +263,26 @@
   ASSERT (z == 1);
 }
 
+/*--------------
+    bug 3264
+    A const parameter of an inline function inside another inline function
+    would lose its initMode flag, resulting in an error about an attempt
+    to assign a value to a const variable.
+*/
+static inline int f_3264 (const int x) {
+  return x;
+}
+
+static inline void g_3264 (void) {
+  f_3264 (0);
+}
+
+void bug_3264 (void)
+{
+  g_3264 ();
+}
+
+
 /*--------------*/
 #endif
 
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/iso646.c sdcc-4.2.0+dfsg/support/regression/tests/iso646.c
--- sdcc-4.0.0+dfsg/support/regression/tests/iso646.c	2019-03-14 16:34:34.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/iso646.c	2020-05-19 15:34:40.000000000 +0000
@@ -59,3 +59,11 @@
 	ASSERT(true not_eq false);
 }
 
+static void
+testUnary(void)
+{
+  int i;
+  ASSERT(compl 0xaa55 == ~0xaa55);
+  ASSERT(bitand i == &i);
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/itoa.c sdcc-4.2.0+dfsg/support/regression/tests/itoa.c
--- sdcc-4.0.0+dfsg/support/regression/tests/itoa.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/itoa.c	2020-07-16 08:13:25.000000000 +0000
@@ -0,0 +1,374 @@
+/** Simple test for the _itoa and _uitoa.
+  test: uitoa, itoa
+  part: 1, 2, 3, 4, 5
+*/
+
+#include 
+#include 
+#include 
+
+#if !defined(PORT_HOST) && !defined(__SDCC_pdk14) && !defined(__SDCC_pdk15) // Lack of memory
+/* do not run tests for listed above platforms - out of memory */
+
+#define TEST_{test} 1
+#define ITOA(num,base,res) check_i(num, base, res)
+#define UITOA(num,base,res) check_ui(num, base, res)
+
+static char
+check_i (int n, int b, const char *r)
+{
+  char buf[34];
+  __itoa(n, buf, b);
+  return !strcmp (buf, r);
+}
+
+static char
+check_ui (int n, int b, const char *r)
+{
+  char buf[34];
+  __uitoa(n, buf, b);
+  return !strcmp (buf, r);
+}
+
+#endif
+
+void test_itoa (void)
+{
+#ifdef TEST_itoa
+#if {part} == 1
+  ASSERT (ITOA (0, 2, "0"));
+  ASSERT (ITOA (0, 8, "0"));
+  ASSERT (ITOA (0, 10, "0"));
+  ASSERT (ITOA (0, 16, "0"));
+  ASSERT (ITOA (1, 2, "1"));
+  ASSERT (ITOA (1, 8, "1"));
+  ASSERT (ITOA (1, 10, "1"));
+  ASSERT (ITOA (1, 16, "1"));
+  ASSERT (ITOA (2, 2, "10"));
+  ASSERT (ITOA (2, 8, "2"));
+  ASSERT (ITOA (2, 10, "2"));
+  ASSERT (ITOA (2, 16, "2"));
+  ASSERT (ITOA (3, 2, "11"));
+  ASSERT (ITOA (3, 8, "3"));
+  ASSERT (ITOA (3, 10, "3"));
+  ASSERT (ITOA (3, 16, "3"));
+  ASSERT (ITOA (4, 2, "100"));
+  ASSERT (ITOA (4, 8, "4"));
+  ASSERT (ITOA (4, 10, "4"));
+  ASSERT (ITOA (4, 16, "4"));
+  ASSERT (ITOA (5, 2, "101"));
+  ASSERT (ITOA (5, 8, "5"));
+  ASSERT (ITOA (5, 10, "5"));
+  ASSERT (ITOA (5, 16, "5"));
+  ASSERT (ITOA (6, 2, "110"));
+  ASSERT (ITOA (6, 8, "6"));
+  ASSERT (ITOA (6, 10, "6"));
+  ASSERT (ITOA (6, 16, "6"));
+  ASSERT (ITOA (7, 2, "111"));
+  ASSERT (ITOA (7, 8, "7"));
+  ASSERT (ITOA (7, 10, "7"));
+  ASSERT (ITOA (7, 16, "7"));
+  ASSERT (ITOA (8, 2, "1000"));
+  ASSERT (ITOA (8, 8, "10"));
+  ASSERT (ITOA (8, 10, "8"));
+  ASSERT (ITOA (8, 16, "8"));
+  ASSERT (ITOA (9, 2, "1001"));
+  ASSERT (ITOA (9, 8, "11"));
+  ASSERT (ITOA (9, 10, "9"));
+  ASSERT (ITOA (9, 16, "9"));
+  ASSERT (ITOA (10, 2, "1010"));
+  ASSERT (ITOA (10, 8, "12"));
+  ASSERT (ITOA (10, 10, "10"));
+  ASSERT (ITOA (10, 16, "A"));
+  ASSERT (ITOA (11, 2, "1011"));
+  ASSERT (ITOA (11, 8, "13"));
+  ASSERT (ITOA (11, 10, "11"));
+  ASSERT (ITOA (11, 16, "B"));
+  ASSERT (ITOA (12, 2, "1100"));
+  ASSERT (ITOA (12, 8, "14"));
+  ASSERT (ITOA (12, 10, "12"));
+#elif {part} == 2
+  ASSERT (ITOA (12, 16, "C"));
+  ASSERT (ITOA (13, 2, "1101"));
+  ASSERT (ITOA (13, 8, "15"));
+  ASSERT (ITOA (13, 10, "13"));
+  ASSERT (ITOA (13, 16, "D"));
+  ASSERT (ITOA (14, 2, "1110"));
+  ASSERT (ITOA (14, 8, "16"));
+  ASSERT (ITOA (14, 10, "14"));
+  ASSERT (ITOA (14, 16, "E"));
+  ASSERT (ITOA (15, 2, "1111"));
+  ASSERT (ITOA (15, 8, "17"));
+  ASSERT (ITOA (15, 10, "15"));
+  ASSERT (ITOA (15, 16, "F"));
+  ASSERT (ITOA (16, 2, "10000"));
+  ASSERT (ITOA (16, 8, "20"));
+  ASSERT (ITOA (16, 10, "16"));
+  ASSERT (ITOA (16, 16, "10"));
+  ASSERT (ITOA (-1, 2, "1111111111111111"));
+  ASSERT (ITOA (-1, 8, "177777"));
+  ASSERT (ITOA (-1, 10, "-1"));
+  ASSERT (ITOA (-1, 16, "FFFF"));
+  ASSERT (ITOA (-2, 2, "1111111111111110"));
+  ASSERT (ITOA (-2, 8, "177776"));
+  ASSERT (ITOA (-2, 10, "-2"));
+  ASSERT (ITOA (-2, 16, "FFFE"));
+  ASSERT (ITOA (-3, 2, "1111111111111101"));
+  ASSERT (ITOA (-3, 8, "177775"));
+  ASSERT (ITOA (-3, 10, "-3"));
+  ASSERT (ITOA (-3, 16, "FFFD"));
+  ASSERT (ITOA (-4, 2, "1111111111111100"));
+  ASSERT (ITOA (-4, 8, "177774"));
+  ASSERT (ITOA (-4, 10, "-4"));
+  ASSERT (ITOA (-4, 16, "FFFC"));
+  ASSERT (ITOA (-5, 2, "1111111111111011"));
+  ASSERT (ITOA (-5, 8, "177773"));
+  ASSERT (ITOA (-5, 10, "-5"));
+  ASSERT (ITOA (-5, 16, "FFFB"));
+  ASSERT (ITOA (-6, 2, "1111111111111010"));
+  ASSERT (ITOA (-6, 8, "177772"));
+  ASSERT (ITOA (-6, 10, "-6"));
+  ASSERT (ITOA (-6, 16, "FFFA"));
+  ASSERT (ITOA (-7, 2, "1111111111111001"));
+  ASSERT (ITOA (-7, 8, "177771"));
+  ASSERT (ITOA (-7, 10, "-7"));
+  ASSERT (ITOA (-7, 16, "FFF9"));
+  ASSERT (ITOA (-8, 2, "1111111111111000"));
+  ASSERT (ITOA (-8, 8, "177770"));
+  ASSERT (ITOA (-8, 10, "-8"));
+  ASSERT (ITOA (-8, 16, "FFF8"));
+  ASSERT (ITOA (-9, 2, "1111111111110111"));
+#elif {part} == 3
+  ASSERT (ITOA (-9, 8, "177767"));
+  ASSERT (ITOA (-9, 10, "-9"));
+  ASSERT (ITOA (-9, 16, "FFF7"));
+  ASSERT (ITOA (-10, 2, "1111111111110110"));
+  ASSERT (ITOA (-10, 8, "177766"));
+  ASSERT (ITOA (-10, 10, "-10"));
+  ASSERT (ITOA (-10, 16, "FFF6"));
+  ASSERT (ITOA (-11, 2, "1111111111110101"));
+  ASSERT (ITOA (-11, 8, "177765"));
+  ASSERT (ITOA (-11, 10, "-11"));
+  ASSERT (ITOA (-11, 16, "FFF5"));
+  ASSERT (ITOA (-12, 2, "1111111111110100"));
+  ASSERT (ITOA (-12, 8, "177764"));
+  ASSERT (ITOA (-12, 10, "-12"));
+  ASSERT (ITOA (-12, 16, "FFF4"));
+  ASSERT (ITOA (-13, 2, "1111111111110011"));
+  ASSERT (ITOA (-13, 8, "177763"));
+  ASSERT (ITOA (-13, 10, "-13"));
+  ASSERT (ITOA (-13, 16, "FFF3"));
+  ASSERT (ITOA (-14, 2, "1111111111110010"));
+  ASSERT (ITOA (-14, 8, "177762"));
+  ASSERT (ITOA (-14, 10, "-14"));
+  ASSERT (ITOA (-14, 16, "FFF2"));
+  ASSERT (ITOA (-15, 2, "1111111111110001"));
+  ASSERT (ITOA (-15, 8, "177761"));
+  ASSERT (ITOA (-15, 10, "-15"));
+  ASSERT (ITOA (-15, 16, "FFF1"));
+  ASSERT (ITOA (-16, 2, "1111111111110000"));
+  ASSERT (ITOA (-16, 8, "177760"));
+  ASSERT (ITOA (-16, 10, "-16"));
+  ASSERT (ITOA (-16, 16, "FFF0"));
+  ASSERT (ITOA (127, 2, "1111111"));
+  ASSERT (ITOA (127, 8, "177"));
+  ASSERT (ITOA (127, 10, "127"));
+  ASSERT (ITOA (127, 16, "7F"));
+  ASSERT (ITOA (-127, 2, "1111111110000001"));
+  ASSERT (ITOA (-127, 8, "177601"));
+  ASSERT (ITOA (-127, 10, "-127"));
+  ASSERT (ITOA (-127, 16, "FF81"));
+  ASSERT (ITOA (128, 2, "10000000"));
+  ASSERT (ITOA (128, 8, "200"));
+  ASSERT (ITOA (128, 10, "128"));
+  ASSERT (ITOA (128, 16, "80"));
+  ASSERT (ITOA (-128, 2, "1111111110000000"));
+  ASSERT (ITOA (-128, 8, "177600"));
+  ASSERT (ITOA (-128, 10, "-128"));
+  ASSERT (ITOA (-128, 16, "FF80"));
+#elif {part} == 4
+  ASSERT (ITOA (255, 2, "11111111"));
+  ASSERT (ITOA (255, 8, "377"));
+  ASSERT (ITOA (255, 10, "255"));
+  ASSERT (ITOA (255, 16, "FF"));
+  ASSERT (ITOA (-255, 2, "1111111100000001"));
+  ASSERT (ITOA (-255, 8, "177401"));
+  ASSERT (ITOA (-255, 10, "-255"));
+  ASSERT (ITOA (-255, 16, "FF01"));
+  ASSERT (ITOA (256, 2, "100000000"));
+  ASSERT (ITOA (256, 8, "400"));
+  ASSERT (ITOA (256, 10, "256"));
+  ASSERT (ITOA (256, 16, "100"));
+  ASSERT (ITOA (-256, 2, "1111111100000000"));
+  ASSERT (ITOA (-256, 8, "177400"));
+  ASSERT (ITOA (-256, 10, "-256"));
+  ASSERT (ITOA (-256, 16, "FF00"));
+  ASSERT (ITOA (0x1234, 2, "1001000110100"));
+  ASSERT (ITOA (0x1234, 8, "11064"));
+  ASSERT (ITOA (0x1234, 10, "4660"));
+  ASSERT (ITOA (0x1234, 16, "1234"));
+  ASSERT (ITOA (-0x1234, 2, "1110110111001100"));
+  ASSERT (ITOA (-0x1234, 8, "166714"));
+  ASSERT (ITOA (-0x1234, 10, "-4660"));
+  ASSERT (ITOA (-0x1234, 16, "EDCC"));
+  ASSERT (ITOA (0x5678, 2, "101011001111000"));
+  ASSERT (ITOA (0x5678, 8, "53170"));
+  ASSERT (ITOA (0x5678, 10, "22136"));
+  ASSERT (ITOA (0x5678, 16, "5678"));
+  ASSERT (ITOA (-0x5678, 2, "1010100110001000"));
+  ASSERT (ITOA (-0x5678, 8, "124610"));
+  ASSERT (ITOA (-0x5678, 10, "-22136"));
+  ASSERT (ITOA (-0x5678, 16, "A988"));
+  ASSERT (ITOA (012345, 2, "1010011100101"));
+  ASSERT (ITOA (012345, 8, "12345"));
+  ASSERT (ITOA (012345, 10, "5349"));
+  ASSERT (ITOA (012345, 16, "14E5"));
+  ASSERT (ITOA (-012345, 2, "1110101100011011"));
+  ASSERT (ITOA (-012345, 8, "165433"));
+  ASSERT (ITOA (-012345, 10, "-5349"));
+  ASSERT (ITOA (-012345, 16, "EB1B"));
+  ASSERT (ITOA (32767, 2, "111111111111111"));
+  ASSERT (ITOA (32767, 8, "77777"));
+  ASSERT (ITOA (32767, 10, "32767"));
+  ASSERT (ITOA (32767, 16, "7FFF"));
+  ASSERT (ITOA (-32767, 2, "1000000000000001"));
+  ASSERT (ITOA (-32767, 8, "100001"));
+  ASSERT (ITOA (-32767, 10, "-32767"));
+  ASSERT (ITOA (-32767, 16, "8001"));
+  ASSERT (ITOA (-32768, 2, "1000000000000000"));
+  ASSERT (ITOA (-32768, 8, "100000"));
+  ASSERT (ITOA (-32768, 10, "-32768"));
+  ASSERT (ITOA (-32768, 16, "8000"));
+#elif {part} == 5
+  ASSERT (ITOA (1, 6, "1"));
+  ASSERT (ITOA (12, 6, "20"));
+  ASSERT (ITOA (123, 6, "323"));
+#endif
+#undef ITOA
+#endif /* TEST_itoa */
+}
+
+void test_uitoa(void)
+{
+#ifdef TEST_uitoa
+#if {part} == 1
+  ASSERT (UITOA (0, 2, "0"));
+  ASSERT (UITOA (0, 8, "0"));
+  ASSERT (UITOA (0, 10, "0"));
+  ASSERT (UITOA (0, 16, "0"));
+  ASSERT (UITOA (1, 2, "1"));
+  ASSERT (UITOA (1, 8, "1"));
+  ASSERT (UITOA (1, 10, "1"));
+  ASSERT (UITOA (1, 16, "1"));
+  ASSERT (UITOA (2, 2, "10"));
+  ASSERT (UITOA (2, 8, "2"));
+  ASSERT (UITOA (2, 10, "2"));
+  ASSERT (UITOA (2, 16, "2"));
+  ASSERT (UITOA (3, 2, "11"));
+  ASSERT (UITOA (3, 8, "3"));
+  ASSERT (UITOA (3, 10, "3"));
+  ASSERT (UITOA (3, 16, "3"));
+  ASSERT (UITOA (4, 2, "100"));
+  ASSERT (UITOA (4, 8, "4"));
+  ASSERT (UITOA (4, 10, "4"));
+  ASSERT (UITOA (4, 16, "4"));
+  ASSERT (UITOA (5, 2, "101"));
+  ASSERT (UITOA (5, 8, "5"));
+  ASSERT (UITOA (5, 10, "5"));
+  ASSERT (UITOA (5, 16, "5"));
+  ASSERT (UITOA (6, 2, "110"));
+  ASSERT (UITOA (6, 8, "6"));
+  ASSERT (UITOA (6, 10, "6"));
+#elif {part} == 2
+  ASSERT (UITOA (6, 16, "6"));
+  ASSERT (UITOA (7, 2, "111"));
+  ASSERT (UITOA (7, 8, "7"));
+  ASSERT (UITOA (7, 10, "7"));
+  ASSERT (UITOA (7, 16, "7"));
+  ASSERT (UITOA (8, 2, "1000"));
+  ASSERT (UITOA (8, 8, "10"));
+  ASSERT (UITOA (8, 10, "8"));
+  ASSERT (UITOA (8, 16, "8"));
+  ASSERT (UITOA (9, 2, "1001"));
+  ASSERT (UITOA (9, 8, "11"));
+  ASSERT (UITOA (9, 10, "9"));
+  ASSERT (UITOA (9, 16, "9"));
+  ASSERT (UITOA (10, 2, "1010"));
+  ASSERT (UITOA (10, 8, "12"));
+  ASSERT (UITOA (10, 10, "10"));
+  ASSERT (UITOA (10, 16, "A"));
+  ASSERT (UITOA (11, 2, "1011"));
+  ASSERT (UITOA (11, 8, "13"));
+  ASSERT (UITOA (11, 10, "11"));
+  ASSERT (UITOA (11, 16, "B"));
+  ASSERT (UITOA (12, 2, "1100"));
+  ASSERT (UITOA (12, 8, "14"));
+  ASSERT (UITOA (12, 10, "12"));
+  ASSERT (UITOA (12, 16, "C"));
+  ASSERT (UITOA (13, 2, "1101"));
+  ASSERT (UITOA (13, 8, "15"));
+#elif {part} == 3
+  ASSERT (UITOA (13, 10, "13"));
+  ASSERT (UITOA (13, 16, "D"));
+  ASSERT (UITOA (14, 2, "1110"));
+  ASSERT (UITOA (14, 8, "16"));
+  ASSERT (UITOA (14, 10, "14"));
+  ASSERT (UITOA (14, 16, "E"));
+  ASSERT (UITOA (15, 2, "1111"));
+  ASSERT (UITOA (15, 8, "17"));
+  ASSERT (UITOA (15, 10, "15"));
+  ASSERT (UITOA (15, 16, "F"));
+  ASSERT (UITOA (16, 2, "10000"));
+  ASSERT (UITOA (16, 8, "20"));
+  ASSERT (UITOA (16, 10, "16"));
+  ASSERT (UITOA (16, 16, "10"));
+  ASSERT (UITOA (127, 2, "1111111"));
+  ASSERT (UITOA (127, 8, "177"));
+  ASSERT (UITOA (127, 10, "127"));
+  ASSERT (UITOA (127, 16, "7F"));
+  ASSERT (UITOA (255, 2, "11111111"));
+  ASSERT (UITOA (255, 8, "377"));
+  ASSERT (UITOA (255, 10, "255"));
+  ASSERT (UITOA (255, 16, "FF"));
+  ASSERT (UITOA (0x1234, 2, "1001000110100"));
+  ASSERT (UITOA (0x1234, 8, "11064"));
+  ASSERT (UITOA (0x1234, 10, "4660"));
+  ASSERT (UITOA (0x1234, 16, "1234"));
+  ASSERT (UITOA (0x5678, 2, "101011001111000"));
+#elif {part} == 4
+  ASSERT (UITOA (0x5678, 8, "53170"));
+  ASSERT (UITOA (0x5678, 10, "22136"));
+  ASSERT (UITOA (0x5678, 16, "5678"));
+  ASSERT (UITOA (0x9abc, 2, "1001101010111100"));
+  ASSERT (UITOA (0x9abc, 8, "115274"));
+  ASSERT (UITOA (0x9abc, 10, "39612"));
+  ASSERT (UITOA (0x9abc, 16, "9ABC"));
+  ASSERT (UITOA (0xdef0, 2, "1101111011110000"));
+  ASSERT (UITOA (0xdef0, 8, "157360"));
+  ASSERT (UITOA (0xdef0, 10, "57072"));
+  ASSERT (UITOA (0xdef0, 16, "DEF0"));
+  ASSERT (UITOA (012345, 2, "1010011100101"));
+  ASSERT (UITOA (012345, 8, "12345"));
+  ASSERT (UITOA (012345, 10, "5349"));
+  ASSERT (UITOA (012345, 16, "14E5"));
+  ASSERT (UITOA (32767, 2, "111111111111111"));
+  ASSERT (UITOA (32767, 8, "77777"));
+  ASSERT (UITOA (32767, 10, "32767"));
+  ASSERT (UITOA (32767, 16, "7FFF"));
+  ASSERT (UITOA (32768, 2, "1000000000000000"));
+  ASSERT (UITOA (32768, 8, "100000"));
+  ASSERT (UITOA (32768, 10, "32768"));
+  ASSERT (UITOA (32768, 16, "8000"));
+  ASSERT (UITOA (65535, 2, "1111111111111111"));
+  ASSERT (UITOA (65535, 8, "177777"));
+  ASSERT (UITOA (65535, 10, "65535"));
+  ASSERT (UITOA (65535, 16, "FFFF"));
+#elif {part} == 5
+  ASSERT (UITOA (1, 6, "1"));
+  ASSERT (UITOA (12, 6, "20"));
+  ASSERT (UITOA (123, 6, "323"));
+#endif
+#undef UITOA
+#endif /* TEST_uitoa */
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/lonesha256.c sdcc-4.2.0+dfsg/support/regression/tests/lonesha256.c
--- sdcc-4.0.0+dfsg/support/regression/tests/lonesha256.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/lonesha256.c	2021-11-09 16:10:05.000000000 +0000
@@ -0,0 +1,208 @@
+/*
+   sha256.c
+   sha256 hash function (once gave wrong result on gbz80)
+
+   Test uses the implementation from lonesha256.
+*/
+
+#include 
+
+#define LONESHA256_STATIC
+
+#if !(defined(__SDCC_mcs51) && (defined(__SDCC_MODEL_SMALL) || defined(__SDCC_MODEL_MEDIUM))) && !defined(__SDCC_pdk14) && !defined(__SDCC_pdk15) // Lack of memory
+
+/*
+   lonesha256.h - Portable, endian-proof, single-file, single-function sha256 implementation, originally based on LibTomCrypt
+
+   To the extent possible under law, the author(s) have dedicated all copyright and related and neighboring
+   rights to this software to the public domain worldwide. This software is distributed without any warranty.
+   You should have received a copy of the CC0 Public Domain Dedication along with this software.
+   If not, see .
+*/
+
+/*
+lonesha256 supports the following three configurations:
+#define LONESHA256_EXTERN
+    Default, should be used when using lonesha256 in multiple compilation units within the same project.
+#define LONESHA256_IMPLEMENTATION
+    Must be defined in exactly one source file within a project for lonesha256 to be found by the linker.
+#define LONESHA256_STATIC
+    Defines the lonesha256() function as static, useful if lonesha256 is only used in a single compilation unit.
+lonesha256 function
+(static|extern) int lonesha256 (unsigned char out[32], const unsigned char* in, size_t len)
+    writes the sha256 hash of the first "len" bytes in buffer "in" to buffer "out"
+    returns 0 on success, may return non-zero in future versions to indicate error
+*/
+
+/* header section */
+#ifndef LONESHA256_H
+#define LONESHA256_H
+
+/* process configuration */
+#ifdef LONESHA256_STATIC
+    #define LONESHA256_IMPLEMENTATION
+    #define LSHA256DEF static
+#else /* LONESHA256_EXTERN */
+    #define LSHA256DEF extern
+#endif
+
+/* includes */
+#include  /* size_t */
+
+/* lonesha256 declaration */
+LSHA256DEF int lonesha256(unsigned char[32], const unsigned char*, size_t);
+
+#endif /* LONESHA256_H */
+
+/* implementation section */
+#ifdef LONESHA256_IMPLEMENTATION
+#undef LONESHA256_IMPLEMENTATION
+
+/* includes */
+#include  /* uint32_t, uint64_t */
+#include  /* memcpy */
+
+/* macros */
+#define S(x, n) (((((uint32_t)(x)&0xFFFFFFFFUL)>>(uint32_t)((n)&31))|((uint32_t)(x)<<(uint32_t)((32-((n)&31))&31)))&0xFFFFFFFFUL)
+#define R(x, n) (((x)&0xFFFFFFFFUL)>>(n))
+#define Gamma0(x) (S(x, 7) ^ S(x, 18) ^ R(x, 3))
+#define Gamma1(x) (S(x, 17) ^ S(x, 19) ^ R(x, 10))
+#define RND(a,b,c,d,e,f,g,h,i) \
+    t0 = h + (S(e, 6) ^ S(e, 11) ^ S(e, 25)) + (g ^ (e & (f ^ g))) + K[i] + W[i]; \
+    t1 = (S(a, 2) ^ S(a, 13) ^ S(a, 22)) + (((a | b) & c) | (a & b)); \
+    d += t0; \
+    h  = t0 + t1;
+#define STORE32H(x, y) \
+    (y)[0] = (unsigned char)(((x)>>24)&255); (y)[1] = (unsigned char)(((x)>>16)&255); \
+    (y)[2] = (unsigned char)(((x)>>8)&255); (y)[3] = (unsigned char)((x)&255);
+#define LOAD32H(x, y) \
+    x = ((uint32_t)((y)[0]&255)<<24)|((uint32_t)((y)[1]&255)<<16)|((uint32_t)((y)[2]&255)<<8)|((uint32_t)((y)[3]&255));
+#define STORE64H(x, y) \
+    (y)[0] = (unsigned char)(((x)>>56)&255); (y)[1] = (unsigned char)(((x)>>48)&255); \
+    (y)[2] = (unsigned char)(((x)>>40)&255); (y)[3] = (unsigned char)(((x)>>32)&255); \
+    (y)[4] = (unsigned char)(((x)>>24)&255); (y)[5] = (unsigned char)(((x)>>16)&255); \
+    (y)[6] = (unsigned char)(((x)>>8)&255); (y)[7] = (unsigned char)((x)&255);
+#define SHA256_COMPRESS(buff) \
+    for (i = 0; i < 8; i++) S[i] = sha256_state[i]; \
+    for (i = 0; i < 16; i++) LOAD32H(W[i], buff + (4*i)); \
+    for (i = 16; i < 64; i++) W[i] = Gamma1(W[i-2]) + W[i-7] + Gamma0(W[i-15]) + W[i-16]; \
+    for (i = 0; i < 64; i++) { \
+        RND(S[0],S[1],S[2],S[3],S[4],S[5],S[6],S[7],i); \
+        t = S[7]; S[7] = S[6]; S[6] = S[5]; S[5] = S[4]; \
+        S[4] = S[3]; S[3] = S[2]; S[2] = S[1]; S[1] = S[0]; S[0] = t; \
+    } \
+    for (i = 0; i < 8; i++) sha256_state[i] = sha256_state[i] + S[i];
+
+/* lonesha256 function */
+LSHA256DEF int lonesha256 (unsigned char out[32], const unsigned char* in, size_t len) {
+    /* writes the sha256 hash of the first "len" bytes in buffer "in" to buffer "out"
+     * returns 0 on success, may return non-zero in future versions to indicate error */
+    int i;
+    const uint32_t K[64] = {
+        0x428a2f98UL, 0x71374491UL, 0xb5c0fbcfUL, 0xe9b5dba5UL,
+        0x3956c25bUL, 0x59f111f1UL, 0x923f82a4UL, 0xab1c5ed5UL,
+        0xd807aa98UL, 0x12835b01UL, 0x243185beUL, 0x550c7dc3UL,
+        0x72be5d74UL, 0x80deb1feUL, 0x9bdc06a7UL, 0xc19bf174UL,
+        0xe49b69c1UL, 0xefbe4786UL, 0x0fc19dc6UL, 0x240ca1ccUL,
+        0x2de92c6fUL, 0x4a7484aaUL, 0x5cb0a9dcUL, 0x76f988daUL,
+        0x983e5152UL, 0xa831c66dUL, 0xb00327c8UL, 0xbf597fc7UL,
+        0xc6e00bf3UL, 0xd5a79147UL, 0x06ca6351UL, 0x14292967UL,
+        0x27b70a85UL, 0x2e1b2138UL, 0x4d2c6dfcUL, 0x53380d13UL,
+        0x650a7354UL, 0x766a0abbUL, 0x81c2c92eUL, 0x92722c85UL,
+        0xa2bfe8a1UL, 0xa81a664bUL, 0xc24b8b70UL, 0xc76c51a3UL,
+        0xd192e819UL, 0xd6990624UL, 0xf40e3585UL, 0x106aa070UL,
+        0x19a4c116UL, 0x1e376c08UL, 0x2748774cUL, 0x34b0bcb5UL,
+        0x391c0cb3UL, 0x4ed8aa4aUL, 0x5b9cca4fUL, 0x682e6ff3UL,
+        0x748f82eeUL, 0x78a5636fUL, 0x84c87814UL, 0x8cc70208UL,
+        0x90befffaUL, 0xa4506cebUL, 0xbef9a3f7UL, 0xc67178f2UL
+    };
+    uint64_t sha256_length = 0;
+    uint32_t sha256_state[8] = {
+        0x6A09E667UL, 0xBB67AE85UL, 0x3C6EF372UL, 0xA54FF53AUL,
+        0x510E527FUL, 0x9B05688CUL, 0x1F83D9ABUL, 0x5BE0CD19UL
+    }, S[8], W[64], t0, t1, t;
+    unsigned char sha256_buf[64];
+    /* process input in 64 byte chunks */
+    while (len >= 64) {
+       SHA256_COMPRESS(in);
+       sha256_length += 64 * 8;
+       in += 64;
+       len -= 64;
+    }
+    /* copy remaining bytes into sha256_buf */
+    memcpy(sha256_buf, in, len);
+    /* finish up (len now number of bytes in sha256_buf) */
+    sha256_length += len * 8;
+    sha256_buf[len++] = 0x80;
+    /* pad then compress if length is above 56 bytes */
+    if (len > 56) {
+        while (len < 64) sha256_buf[len++] = 0;
+        SHA256_COMPRESS(sha256_buf);
+        len = 0;
+    }
+    /* pad up to 56 bytes */
+    while (len < 56) sha256_buf[len++] = 0;
+    /* store length and compress */
+    STORE64H(sha256_length, sha256_buf + 56);
+    SHA256_COMPRESS(sha256_buf);
+    /* copy output */
+    for (i = 0; i < 8; i++) {
+        STORE32H(sha256_state[i], out + 4*i);
+    }
+    /* return */
+    return 0;
+}
+
+#endif /* LONESHA256_IMPLEMENTATION */
+
+/* structs */
+struct pair {
+    unsigned char* in; /* input string */
+    unsigned char out[32]; /* expected output */
+};
+
+/* known input/output pairs */
+const struct pair pairs[] = {
+    /* 0: empty string */
+    {
+        "",
+        {0xE3, 0xB0, 0xC4, 0x42, 0x98, 0xFC, 0x1C, 0x14,
+        0x9A, 0xFB, 0xF4, 0xC8, 0x99, 0x6F, 0xB9, 0x24,
+        0x27, 0xAE, 0x41, 0xE4, 0x64, 0x9B, 0x93, 0x4C,
+        0xA4, 0x95, 0x99, 0x1B, 0x78, 0x52, 0xB8, 0x55}
+    },
+    /* 1: foobar string */
+    {
+        "foobar",
+        {0xC3, 0xAB, 0x8F, 0xF1, 0x37, 0x20, 0xE8, 0xAD,
+        0x90, 0x47, 0xDD, 0x39, 0x46, 0x6B, 0x3C, 0x89,
+        0x74, 0xE5, 0x92, 0xC2, 0xFA, 0x38, 0x3D, 0x4A,
+        0x39, 0x60, 0x71, 0x4C, 0xAE, 0xF0, 0xC4, 0xF2}
+    },
+    /* 2: quick brown fox */
+    {
+        "The quick brown fox jumps over the lazy dog",
+        {0xD7, 0xA8, 0xFB, 0xB3, 0x07, 0xD7, 0x80, 0x94,
+        0x69, 0xCA, 0x9A, 0xBC, 0xB0, 0x08, 0x2E, 0x4F,
+        0x8D, 0x56, 0x51, 0xE4, 0x6D, 0x3C, 0xDB, 0x76,
+        0x2D, 0x02, 0xD0, 0xBF, 0x37, 0xC9, 0xE5, 0x92}
+    }
+};
+#endif
+
+void
+testSha (void)
+{
+#if !defined(__SDCC_ds390) // Fails for unknown reason
+#if !(defined(__SDCC_mcs51) && (defined(__SDCC_MODEL_SMALL) || defined(__SDCC_MODEL_MEDIUM) || defined(__SDCC_STACK_AUTO))) && !defined(__SDCC_pdk14) && !defined(__SDCC_pdk15) // Lack of memory
+    int i;
+
+    for (i = 0; i < sizeof(pairs)/sizeof(pairs[0]); i++) {
+      unsigned char out[32];
+      ASSERT(!lonesha256(out, pairs[i].in, strlen(pairs[i].in)));
+      ASSERT(!memcmp(out, pairs[i].out, sizeof(out)));
+    }
+#endif
+#endif
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/loop.c sdcc-4.2.0+dfsg/support/regression/tests/loop.c
--- sdcc-4.0.0+dfsg/support/regression/tests/loop.c	2019-04-16 10:04:43.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/loop.c	2021-04-22 08:33:00.000000000 +0000
@@ -1,4 +1,4 @@
-/** loopp counter narrowing optimizatrion test
+/** loop counter narrowing optimizatrion test
     type: unsigned long, signed long
 */
 #include 
@@ -85,6 +85,11 @@
 }
 #endif
 
+// Get FreeBSD version to skip part of test for known broken setjmp (FreeBSD bug #255320).
+#ifdef __FreeBSD__
+#include 
+#endif
+
 void testLoop(void)
 {
 #if !defined(__SDCC_mcs51) && !defined(__SDCC_pdk14) && !defined(__SDCC_pdk15)
@@ -106,9 +111,10 @@
 	address (array);
 	ASSERT (array[17] == 17);
 	ASSERT (array[18] == 18);
-
+#if !defined(__FreeBSD__) || __FreeBSD_version > 1300139
 	jump (array);
 	ASSERT (array[0] != 13);
 #endif
+#endif
 }
 
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/ltoa.c sdcc-4.2.0+dfsg/support/regression/tests/ltoa.c
--- sdcc-4.0.0+dfsg/support/regression/tests/ltoa.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/ltoa.c	2020-07-16 08:13:25.000000000 +0000
@@ -0,0 +1,397 @@
+/** Simple test for the _ltoa and _ultoa.
+  test: ultoa, ltoa
+  part: 1, 2, 3, 4, 5
+*/
+
+#include 
+#include 
+#include 
+
+#if !defined(PORT_HOST) && !(defined(__SDCC_mcs51) && !defined(__SDCC_STACK_AUTO) && defined(__SDCC_MODEL_SMALL) ) && !defined(__SDCC_pic14) && !defined(__SDCC_pic16) && !defined(__SDCC_pdk14) && !defined(__SDCC_pdk15) // Lack of memory
+/* do not run tests for listed above platforms - out of memory */
+#define TEST_{test} 1
+#define LTOA(num,base,res) check_l(num, base, res)
+#define ULTOA(num,base,res) check_ul(num, base, res)
+
+static char
+check_l (long n, int b, const char *r)
+{
+  static char buf[66];
+  __ltoa(n, buf, b);
+  return !strcmp (buf, r);
+}
+
+static char
+check_ul (unsigned long n, int b, const char *r)
+{
+  char buf[66];
+  __ultoa(n, buf, b);
+  return !strcmp (buf, r);
+}
+
+#endif
+
+void test_ltoa (void)
+{
+#ifdef TEST_ltoa
+#if {part} == 1
+  ASSERT (LTOA (0, 2, "0"));
+  ASSERT (LTOA (0, 8, "0"));
+  ASSERT (LTOA (0, 10, "0"));
+  ASSERT (LTOA (0, 16, "0"));
+  ASSERT (LTOA (1, 2, "1"));
+  ASSERT (LTOA (1, 8, "1"));
+  ASSERT (LTOA (1, 10, "1"));
+  ASSERT (LTOA (1, 16, "1"));
+  ASSERT (LTOA (2, 2, "10"));
+  ASSERT (LTOA (2, 8, "2"));
+  ASSERT (LTOA (2, 10, "2"));
+  ASSERT (LTOA (2, 16, "2"));
+  ASSERT (LTOA (3, 2, "11"));
+  ASSERT (LTOA (3, 8, "3"));
+  ASSERT (LTOA (3, 10, "3"));
+  ASSERT (LTOA (3, 16, "3"));
+  ASSERT (LTOA (4, 2, "100"));
+  ASSERT (LTOA (4, 8, "4"));
+  ASSERT (LTOA (4, 10, "4"));
+  ASSERT (LTOA (4, 16, "4"));
+  ASSERT (LTOA (5, 2, "101"));
+  ASSERT (LTOA (5, 8, "5"));
+  ASSERT (LTOA (5, 10, "5"));
+  ASSERT (LTOA (5, 16, "5"));
+  ASSERT (LTOA (6, 2, "110"));
+  ASSERT (LTOA (6, 8, "6"));
+  ASSERT (LTOA (6, 10, "6"));
+  ASSERT (LTOA (6, 16, "6"));
+  ASSERT (LTOA (7, 2, "111"));
+  ASSERT (LTOA (7, 8, "7"));
+  ASSERT (LTOA (7, 10, "7"));
+  ASSERT (LTOA (7, 16, "7"));
+  ASSERT (LTOA (8, 2, "1000"));
+  ASSERT (LTOA (8, 8, "10"));
+  ASSERT (LTOA (8, 10, "8"));
+  ASSERT (LTOA (8, 16, "8"));
+  ASSERT (LTOA (9, 2, "1001"));
+  ASSERT (LTOA (9, 8, "11"));
+  ASSERT (LTOA (9, 10, "9"));
+  ASSERT (LTOA (9, 16, "9"));
+  ASSERT (LTOA (10, 2, "1010"));
+  ASSERT (LTOA (10, 8, "12"));
+  ASSERT (LTOA (10, 10, "10"));
+  ASSERT (LTOA (10, 16, "A"));
+  ASSERT (LTOA (11, 2, "1011"));
+  ASSERT (LTOA (11, 8, "13"));
+  ASSERT (LTOA (11, 10, "11"));
+  ASSERT (LTOA (11, 16, "B"));
+  ASSERT (LTOA (12, 2, "1100"));
+  ASSERT (LTOA (12, 8, "14"));
+  ASSERT (LTOA (12, 10, "12"));
+  ASSERT (LTOA (12, 16, "C"));
+  ASSERT (LTOA (13, 2, "1101"));
+  ASSERT (LTOA (13, 8, "15"));
+#elif {part} == 2
+  ASSERT (LTOA (13, 10, "13"));
+  ASSERT (LTOA (13, 16, "D"));
+  ASSERT (LTOA (14, 2, "1110"));
+  ASSERT (LTOA (14, 8, "16"));
+  ASSERT (LTOA (14, 10, "14"));
+  ASSERT (LTOA (14, 16, "E"));
+  ASSERT (LTOA (15, 2, "1111"));
+  ASSERT (LTOA (15, 8, "17"));
+  ASSERT (LTOA (15, 10, "15"));
+  ASSERT (LTOA (15, 16, "F"));
+  ASSERT (LTOA (16, 2, "10000"));
+  ASSERT (LTOA (16, 8, "20"));
+  ASSERT (LTOA (16, 10, "16"));
+  ASSERT (LTOA (16, 16, "10"));
+  ASSERT (LTOA (-1, 2, "11111111111111111111111111111111"));
+  ASSERT (LTOA (-1, 8, "37777777777"));
+  ASSERT (LTOA (-1, 10, "-1"));
+  ASSERT (LTOA (-1, 16, "FFFFFFFF"));
+  ASSERT (LTOA (-2, 2, "11111111111111111111111111111110"));
+  ASSERT (LTOA (-2, 8, "37777777776"));
+  ASSERT (LTOA (-2, 10, "-2"));
+  ASSERT (LTOA (-2, 16, "FFFFFFFE"));
+  ASSERT (LTOA (-3, 2, "11111111111111111111111111111101"));
+  ASSERT (LTOA (-3, 8, "37777777775"));
+  ASSERT (LTOA (-3, 10, "-3"));
+  ASSERT (LTOA (-3, 16, "FFFFFFFD"));
+  ASSERT (LTOA (-4, 2, "11111111111111111111111111111100"));
+  ASSERT (LTOA (-4, 8, "37777777774"));
+  ASSERT (LTOA (-4, 10, "-4"));
+  ASSERT (LTOA (-4, 16, "FFFFFFFC"));
+  ASSERT (LTOA (-5, 2, "11111111111111111111111111111011"));
+  ASSERT (LTOA (-5, 8, "37777777773"));
+  ASSERT (LTOA (-5, 10, "-5"));
+  ASSERT (LTOA (-5, 16, "FFFFFFFB"));
+  ASSERT (LTOA (-6, 2, "11111111111111111111111111111010"));
+  ASSERT (LTOA (-6, 8, "37777777772"));
+  ASSERT (LTOA (-6, 10, "-6"));
+  ASSERT (LTOA (-6, 16, "FFFFFFFA"));
+  ASSERT (LTOA (-7, 2, "11111111111111111111111111111001"));
+  ASSERT (LTOA (-7, 8, "37777777771"));
+  ASSERT (LTOA (-7, 10, "-7"));
+  ASSERT (LTOA (-7, 16, "FFFFFFF9"));
+  ASSERT (LTOA (-8, 2, "11111111111111111111111111111000"));
+  ASSERT (LTOA (-8, 8, "37777777770"));
+  ASSERT (LTOA (-8, 10, "-8"));
+  ASSERT (LTOA (-8, 16, "FFFFFFF8"));
+  ASSERT (LTOA (-9, 2, "11111111111111111111111111110111"));
+  ASSERT (LTOA (-9, 8, "37777777767"));
+  ASSERT (LTOA (-9, 10, "-9"));
+  ASSERT (LTOA (-9, 16, "FFFFFFF7"));
+  ASSERT (LTOA (-10, 2, "11111111111111111111111111110110"));
+  ASSERT (LTOA (-10, 8, "37777777766"));
+  ASSERT (LTOA (-10, 10, "-10"));
+  ASSERT (LTOA (-10, 16, "FFFFFFF6"));
+#elif {part} == 3
+  ASSERT (LTOA (-11, 2, "11111111111111111111111111110101"));
+  ASSERT (LTOA (-11, 8, "37777777765"));
+  ASSERT (LTOA (-11, 10, "-11"));
+  ASSERT (LTOA (-11, 16, "FFFFFFF5"));
+  ASSERT (LTOA (-12, 2, "11111111111111111111111111110100"));
+  ASSERT (LTOA (-12, 8, "37777777764"));
+  ASSERT (LTOA (-12, 10, "-12"));
+  ASSERT (LTOA (-12, 16, "FFFFFFF4"));
+  ASSERT (LTOA (-13, 2, "11111111111111111111111111110011"));
+  ASSERT (LTOA (-13, 8, "37777777763"));
+  ASSERT (LTOA (-13, 10, "-13"));
+  ASSERT (LTOA (-13, 16, "FFFFFFF3"));
+  ASSERT (LTOA (-14, 2, "11111111111111111111111111110010"));
+  ASSERT (LTOA (-14, 8, "37777777762"));
+  ASSERT (LTOA (-14, 10, "-14"));
+  ASSERT (LTOA (-14, 16, "FFFFFFF2"));
+  ASSERT (LTOA (-15, 2, "11111111111111111111111111110001"));
+  ASSERT (LTOA (-15, 8, "37777777761"));
+  ASSERT (LTOA (-15, 10, "-15"));
+  ASSERT (LTOA (-15, 16, "FFFFFFF1"));
+  ASSERT (LTOA (-16, 2, "11111111111111111111111111110000"));
+  ASSERT (LTOA (-16, 8, "37777777760"));
+  ASSERT (LTOA (-16, 10, "-16"));
+  ASSERT (LTOA (-16, 16, "FFFFFFF0"));
+  ASSERT (LTOA (127, 2, "1111111"));
+  ASSERT (LTOA (127, 8, "177"));
+  ASSERT (LTOA (127, 10, "127"));
+  ASSERT (LTOA (127, 16, "7F"));
+  ASSERT (LTOA (-127, 2, "11111111111111111111111110000001"));
+  ASSERT (LTOA (-127, 8, "37777777601"));
+  ASSERT (LTOA (-127, 10, "-127"));
+  ASSERT (LTOA (-127, 16, "FFFFFF81"));
+  ASSERT (LTOA (128, 2, "10000000"));
+  ASSERT (LTOA (128, 8, "200"));
+  ASSERT (LTOA (128, 10, "128"));
+  ASSERT (LTOA (128, 16, "80"));
+  ASSERT (LTOA (-128, 2, "11111111111111111111111110000000"));
+  ASSERT (LTOA (-128, 8, "37777777600"));
+  ASSERT (LTOA (-128, 10, "-128"));
+  ASSERT (LTOA (-128, 16, "FFFFFF80"));
+  ASSERT (LTOA (255, 2, "11111111"));
+  ASSERT (LTOA (255, 8, "377"));
+  ASSERT (LTOA (255, 10, "255"));
+  ASSERT (LTOA (255, 16, "FF"));
+  ASSERT (LTOA (-255, 2, "11111111111111111111111100000001"));
+  ASSERT (LTOA (-255, 8, "37777777401"));
+  ASSERT (LTOA (-255, 10, "-255"));
+  ASSERT (LTOA (-255, 16, "FFFFFF01"));
+  ASSERT (LTOA (256, 2, "100000000"));
+  ASSERT (LTOA (256, 8, "400"));
+  ASSERT (LTOA (256, 10, "256"));
+  ASSERT (LTOA (256, 16, "100"));
+  ASSERT (LTOA (-256, 2, "11111111111111111111111100000000"));
+  ASSERT (LTOA (-256, 8, "37777777400"));
+#elif {part} == 4
+  ASSERT (LTOA (-256, 10, "-256"));
+  ASSERT (LTOA (-256, 16, "FFFFFF00"));
+  ASSERT (LTOA (0x12345678, 2, "10010001101000101011001111000"));
+  ASSERT (LTOA (0x12345678, 8, "2215053170"));
+  ASSERT (LTOA (0x12345678, 10, "305419896"));
+  ASSERT (LTOA (0x12345678, 16, "12345678"));
+  ASSERT (LTOA (-0x12345678, 2, "11101101110010111010100110001000"));
+  ASSERT (LTOA (-0x12345678, 8, "35562724610"));
+  ASSERT (LTOA (-0x12345678, 10, "-305419896"));
+  ASSERT (LTOA (-0x12345678, 16, "EDCBA988"));
+  ASSERT (LTOA (0x70abcdef, 2, "1110000101010111100110111101111"));
+  ASSERT (LTOA (0x70abcdef, 8, "16052746757"));
+  ASSERT (LTOA (0x70abcdef, 10, "1890307567"));
+  ASSERT (LTOA (0x70abcdef, 16, "70ABCDEF"));
+  ASSERT (LTOA (-0x70abcdef, 2, "10001111010101000011001000010001"));
+  ASSERT (LTOA (-0x70abcdef, 8, "21725031021"));
+  ASSERT (LTOA (-0x70abcdef, 10, "-1890307567"));
+  ASSERT (LTOA (-0x70abcdef, 16, "8F543211"));
+  ASSERT (LTOA (01234567, 2, "1010011100101110111"));
+  ASSERT (LTOA (01234567, 8, "1234567"));
+  ASSERT (LTOA (01234567, 10, "342391"));
+  ASSERT (LTOA (01234567, 16, "53977"));
+  ASSERT (LTOA (-01234567, 2, "11111111111110101100011010001001"));
+  ASSERT (LTOA (-01234567, 8, "37776543211"));
+  ASSERT (LTOA (-01234567, 10, "-342391"));
+  ASSERT (LTOA (-01234567, 16, "FFFAC689"));
+  ASSERT (LTOA (32767, 2, "111111111111111"));
+  ASSERT (LTOA (32767, 8, "77777"));
+  ASSERT (LTOA (32767, 10, "32767"));
+  ASSERT (LTOA (32767, 16, "7FFF"));
+  ASSERT (LTOA (-32767, 2, "11111111111111111000000000000001"));
+  ASSERT (LTOA (-32767, 8, "37777700001"));
+  ASSERT (LTOA (-32767, 10, "-32767"));
+  ASSERT (LTOA (-32767, 16, "FFFF8001"));
+  ASSERT (LTOA (32768, 2, "1000000000000000"));
+  ASSERT (LTOA (32768, 8, "100000"));
+  ASSERT (LTOA (32768, 10, "32768"));
+  ASSERT (LTOA (32768, 16, "8000"));
+  ASSERT (LTOA (-32768, 2, "11111111111111111000000000000000"));
+  ASSERT (LTOA (-32768, 8, "37777700000"));
+  ASSERT (LTOA (-32768, 10, "-32768"));
+  ASSERT (LTOA (-32768, 16, "FFFF8000"));
+  ASSERT (LTOA (0x7fffffff, 2, "1111111111111111111111111111111"));
+  ASSERT (LTOA (0x7fffffff, 8, "17777777777"));
+  ASSERT (LTOA (0x7fffffff, 10, "2147483647"));
+  ASSERT (LTOA (0x7fffffff, 16, "7FFFFFFF"));
+  ASSERT (LTOA (-0x7fffffff, 2, "10000000000000000000000000000001"));
+  ASSERT (LTOA (-0x7fffffff, 8, "20000000001"));
+  ASSERT (LTOA (-0x7fffffff, 10, "-2147483647"));
+  ASSERT (LTOA (-0x7fffffff, 16, "80000001"));
+  ASSERT (LTOA (-0x80000000, 2, "10000000000000000000000000000000"));
+  ASSERT (LTOA (-0x80000000, 8, "20000000000"));
+  ASSERT (LTOA (-0x80000000, 10, "-2147483648"));
+  ASSERT (LTOA (-0x80000000, 16, "80000000"));
+#elif {part} == 5
+  ASSERT (LTOA (1, 6, "1"));
+  ASSERT (LTOA (12, 6, "20"));
+  ASSERT (LTOA (123, 6, "323"));
+#endif /* {part} */
+#undef LTOA
+#endif /* TEST_ltoa */
+}
+
+
+void test_ultoa (void)
+{
+#ifdef TEST_ultoa
+#if {part} == 1
+  ASSERT (ULTOA (0, 2, "0"));
+  ASSERT (ULTOA (0, 8, "0"));
+  ASSERT (ULTOA (0, 10, "0"));
+  ASSERT (ULTOA (0, 16, "0"));
+  ASSERT (ULTOA (1, 2, "1"));
+  ASSERT (ULTOA (1, 8, "1"));
+  ASSERT (ULTOA (1, 10, "1"));
+  ASSERT (ULTOA (1, 16, "1"));
+  ASSERT (ULTOA (2, 2, "10"));
+  ASSERT (ULTOA (2, 8, "2"));
+  ASSERT (ULTOA (2, 10, "2"));
+  ASSERT (ULTOA (2, 16, "2"));
+  ASSERT (ULTOA (3, 2, "11"));
+  ASSERT (ULTOA (3, 8, "3"));
+  ASSERT (ULTOA (3, 10, "3"));
+  ASSERT (ULTOA (3, 16, "3"));
+  ASSERT (ULTOA (4, 2, "100"));
+  ASSERT (ULTOA (4, 8, "4"));
+  ASSERT (ULTOA (4, 10, "4"));
+  ASSERT (ULTOA (4, 16, "4"));
+  ASSERT (ULTOA (5, 2, "101"));
+  ASSERT (ULTOA (5, 8, "5"));
+  ASSERT (ULTOA (5, 10, "5"));
+  ASSERT (ULTOA (5, 16, "5"));
+  ASSERT (ULTOA (6, 2, "110"));
+  ASSERT (ULTOA (6, 8, "6"));
+  ASSERT (ULTOA (6, 10, "6"));
+  ASSERT (ULTOA (6, 16, "6"));
+#elif {part} == 2
+  ASSERT (ULTOA (7, 2, "111"));
+  ASSERT (ULTOA (7, 8, "7"));
+  ASSERT (ULTOA (7, 10, "7"));
+  ASSERT (ULTOA (7, 16, "7"));
+  ASSERT (ULTOA (8, 2, "1000"));
+  ASSERT (ULTOA (8, 8, "10"));
+  ASSERT (ULTOA (8, 10, "8"));
+  ASSERT (ULTOA (8, 16, "8"));
+  ASSERT (ULTOA (9, 2, "1001"));
+  ASSERT (ULTOA (9, 8, "11"));
+  ASSERT (ULTOA (9, 10, "9"));
+  ASSERT (ULTOA (9, 16, "9"));
+  ASSERT (ULTOA (10, 2, "1010"));
+  ASSERT (ULTOA (10, 8, "12"));
+  ASSERT (ULTOA (10, 10, "10"));
+  ASSERT (ULTOA (10, 16, "A"));
+  ASSERT (ULTOA (11, 2, "1011"));
+  ASSERT (ULTOA (11, 8, "13"));
+  ASSERT (ULTOA (11, 10, "11"));
+  ASSERT (ULTOA (11, 16, "B"));
+  ASSERT (ULTOA (12, 2, "1100"));
+  ASSERT (ULTOA (12, 8, "14"));
+  ASSERT (ULTOA (12, 10, "12"));
+  ASSERT (ULTOA (12, 16, "C"));
+  ASSERT (ULTOA (13, 2, "1101"));
+  ASSERT (ULTOA (13, 8, "15"));
+  ASSERT (ULTOA (13, 10, "13"));
+  ASSERT (ULTOA (13, 16, "D"));
+#elif {part} == 3
+  ASSERT (ULTOA (14, 2, "1110"));
+  ASSERT (ULTOA (14, 8, "16"));
+  ASSERT (ULTOA (14, 10, "14"));
+  ASSERT (ULTOA (14, 16, "E"));
+  ASSERT (ULTOA (15, 2, "1111"));
+  ASSERT (ULTOA (15, 8, "17"));
+  ASSERT (ULTOA (15, 10, "15"));
+  ASSERT (ULTOA (15, 16, "F"));
+  ASSERT (ULTOA (16, 2, "10000"));
+  ASSERT (ULTOA (16, 8, "20"));
+  ASSERT (ULTOA (16, 10, "16"));
+  ASSERT (ULTOA (16, 16, "10"));
+  ASSERT (ULTOA (127, 2, "1111111"));
+  ASSERT (ULTOA (127, 8, "177"));
+  ASSERT (ULTOA (127, 10, "127"));
+  ASSERT (ULTOA (127, 16, "7F"));
+  ASSERT (ULTOA (255, 2, "11111111"));
+  ASSERT (ULTOA (255, 8, "377"));
+  ASSERT (ULTOA (255, 10, "255"));
+  ASSERT (ULTOA (255, 16, "FF"));
+  ASSERT (ULTOA (65535, 2, "1111111111111111"));
+  ASSERT (ULTOA (65535, 8, "177777"));
+  ASSERT (ULTOA (65535, 10, "65535"));
+  ASSERT (ULTOA (65535, 16, "FFFF"));
+  ASSERT (ULTOA (65536, 2, "10000000000000000"));
+  ASSERT (ULTOA (65536, 8, "200000"));
+  ASSERT (ULTOA (65536, 10, "65536"));
+  ASSERT (ULTOA (65536, 16, "10000"));
+#elif {part} == 4
+  ASSERT (ULTOA (0xffffffff, 2, "11111111111111111111111111111111"));
+  ASSERT (ULTOA (0xffffffff, 8, "37777777777"));
+  ASSERT (ULTOA (0xffffffff, 10, "4294967295"));
+  ASSERT (ULTOA (0xffffffff, 16, "FFFFFFFF"));
+  ASSERT (ULTOA (0x12345678, 2, "10010001101000101011001111000"));
+  ASSERT (ULTOA (0x12345678, 8, "2215053170"));
+  ASSERT (ULTOA (0x12345678, 10, "305419896"));
+  ASSERT (ULTOA (0x12345678, 16, "12345678"));
+  ASSERT (ULTOA (0x56789abc, 2, "1010110011110001001101010111100"));
+  ASSERT (ULTOA (0x56789abc, 8, "12636115274"));
+  ASSERT (ULTOA (0x56789abc, 10, "1450744508"));
+  ASSERT (ULTOA (0x56789abc, 16, "56789ABC"));
+  ASSERT (ULTOA (0xdef01234, 2, "11011110111100000001001000110100"));
+  ASSERT (ULTOA (0xdef01234, 8, "33674011064"));
+  ASSERT (ULTOA (0xdef01234, 10, "3740275252"));
+  ASSERT (ULTOA (0xdef01234, 16, "DEF01234"));
+  ASSERT (ULTOA (01234567, 2, "1010011100101110111"));
+  ASSERT (ULTOA (01234567, 8, "1234567"));
+  ASSERT (ULTOA (01234567, 10, "342391"));
+  ASSERT (ULTOA (01234567, 16, "53977"));
+  ASSERT (ULTOA (0x7fffffff, 2, "1111111111111111111111111111111"));
+  ASSERT (ULTOA (0x7fffffff, 8, "17777777777"));
+  ASSERT (ULTOA (0x7fffffff, 10, "2147483647"));
+  ASSERT (ULTOA (0x7fffffff, 16, "7FFFFFFF"));
+  ASSERT (ULTOA (0x80000000, 2, "10000000000000000000000000000000"));
+  ASSERT (ULTOA (0x80000000, 8, "20000000000"));
+  ASSERT (ULTOA (0x80000000, 10, "2147483648"));
+  ASSERT (ULTOA (0x80000000, 16, "80000000"));
+  ASSERT (ULTOA (0xffffffff, 2, "11111111111111111111111111111111"));
+  ASSERT (ULTOA (0xffffffff, 8, "37777777777"));
+  ASSERT (ULTOA (0xffffffff, 10, "4294967295"));
+  ASSERT (ULTOA (0xffffffff, 16, "FFFFFFFF"));
+#elif {part} == 5
+  ASSERT (ULTOA (1, 6, "1"));
+  ASSERT (ULTOA (12, 6, "20"));
+  ASSERT (ULTOA (123, 6, "323"));
+#endif /* {part} */
+#undef ULTOA
+#endif /*TEST_ultoa */
+}
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/malloc.c sdcc-4.2.0+dfsg/support/regression/tests/malloc.c
--- sdcc-4.0.0+dfsg/support/regression/tests/malloc.c	2019-09-24 20:05:59.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/malloc.c	2021-12-10 14:48:15.000000000 +0000
@@ -116,7 +116,7 @@
 	free(c);
 
 	/* Check that we can allocate at least 256 bytes at once. */
-#if defined(PORT_HOST) || defined(__SDCC_z80) || defined(__SDCC_z180) || defined(__SDCC_r2k) || defined(__SDCC_r3ka)
+#if defined(PORT_HOST) || defined(__SDCC_z80) || defined(__SDCC_z180) || defined(__SDCC_r2k) || defined(__SDCC_r2ka) || defined(__SDCC_r3ka)
 	a = malloc(256);
 	ASSERT(a);
 	free(a);
@@ -150,7 +150,7 @@
   LOG (("p1 == NULL when out of memory\n"));
 #endif
 
-#if !defined(PORT_HOST) && !defined(__SDCC_gbz80) && !defined(__SDCC_z80)
+#if !defined(PORT_HOST) && !defined(__SDCC_sm83) && !defined(__SDCC_z80)
   p1 = malloc (2000);
   ASSERT (p1 == NULL);
   LOG (("p1 == NULL when out of memory\n"));
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/memory.c sdcc-4.2.0+dfsg/support/regression/tests/memory.c
--- sdcc-4.0.0+dfsg/support/regression/tests/memory.c	2019-09-24 20:05:59.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/memory.c	2020-09-28 10:06:29.000000000 +0000
@@ -1,4 +1,6 @@
 /** memory function test
+ builtins: on, off
+ part: 1, 2, 3
 */
 #include 
 
@@ -6,16 +8,41 @@
 
 #if defined(__SDCC_stm8) || defined(PORT_HOST) || defined(__SDCC_ds390) || \
 	(defined(__SDCC_mcs51) && (defined(__SDCC_MODEL_LARGE) || defined(__SDCC_MODEL_HUGE))) || \
-    defined(__SDCC_z80) || defined(__SDCC_z180) || defined(__SDCC_r2k) || defined(__SDCC_r3ka)
+    defined(__SDCC_z80) || defined(__SDCC_z180) || defined(__SDCC_r2k) || defined(__SDCC_r2ka) || defined(__SDCC_r3ka)
 #define TEST_LARGE
 #endif
 
+
+#define BUILTINS_{builtins} 1
+#if defined(BUILTINS_off) && !defined(__SDCC_pdk14)
+#undef memchr
+#undef memcmp
+#undef memcpy
+#undef memccpy
+#undef memmove
+#undef memset
+#undef strlen
+#endif
+
+/* Note: the majority of library function calls purposefully do not assign or
+ * test the return value. This is so that, on some ports (e.g. z80), the
+ * built-in functions are used and tested. */
+
 unsigned char destination[9];
 const unsigned char source[9] = {0, 1, 2, 3};
+unsigned char *ret;
 int c;
 
-void testmemory(void)
+// Some of these tests intentionally do not check the return value of functions:
+// Some backends use built-ins when the return value is not used, but fall back
+// to a library version otherwise. So we need tests with unused return value to
+// test the built-in. Similarly, code paths for built-ns are different depending
+// on the last parameter being a literal vs. not. So we need to test both with a
+// literal and a volatile variable.
+void testMemory(void)
 {
+#if {part} == 1
+  /* Local stack variables */
   volatile size_t zero = 0;
   volatile size_t one = 1;
 
@@ -36,7 +63,6 @@
   ASSERT(destination[0] == 23);
   ASSERT(destination[1] == 42);
   memset(destination, 42, 1);
-
   /* Test memcpy() */
   memcpy(destination, source, 0);
   ASSERT(destination[0] == 42);
@@ -56,23 +82,37 @@
   memcpy(destination, source, 3);
   ASSERT(destination[2] == source[2]);
   ASSERT(destination[3] == 5);
-
   /* Test memcmp() */
   memcpy(destination, source, 4);
   ASSERT(memcmp(destination, source, 4) == 0);
+
 #ifndef __SDCC_pdk14 // Lack of memory
 #if !(defined (__SDCC_pdk15) && defined(__SDCC_STACK_AUTO)) // Lack of code memory
+
   /* Test memmove() */
-  memcpy(destination, source, 4);
-  memmove(destination, destination + 1, 3);
-  ASSERT(destination[0] == source[1]);
-  ASSERT(destination[2] == source[3]);
-  ASSERT(destination[3] == source[3]);
-  memcpy(destination, source, 4);
-  memmove(destination + 1, destination, 3);
-  ASSERT(destination[0] == source[0]);
-  ASSERT(destination[1] == source[0]);
-  ASSERT(destination[3] == source[2]);
+  ret = memmove(destination, "abcdefgh", 9); // Full copy
+  ASSERT(strcmp(destination, "abcdefgh") == 0);
+  ASSERT(ret == destination);
+
+  ret = memmove(destination + 1, "123", 3); // Sub copy with offset
+  ASSERT(strcmp(destination, "a123efgh") == 0);
+  ASSERT(ret == destination + 1);
+
+  ret = memmove(destination, source, 0); // Zero count, changes nothing
+  ASSERT(strcmp(destination, "a123efgh") == 0);
+  ASSERT(ret == destination);
+
+  ret = memmove(destination + 1, destination, 7); // Overlap to right
+  ASSERT(strcmp(destination, "aa123efg") == 0);
+  ASSERT(ret == destination + 1);
+
+  ret = memmove(destination, destination + 1, 8); // Overlap to left
+  ASSERT(strcmp(destination, "a123efg") == 0);
+  ASSERT(ret == destination);
+
+  ret = memmove(destination, destination, 9); // 100% overlap
+  ASSERT(strcmp(destination, "a123efg") == 0);
+  ASSERT(ret == destination);
 
   /* Test memchr() */
   memcpy(destination, source, 4);
@@ -85,6 +125,7 @@
   ASSERT(strlen("t") == 1);
   ASSERT(strlen("") == 0);
 
+  /* Test memccpy() */
   destination[2] = 0;
   destination[3] = 0;
 #ifndef PORT_HOST
@@ -92,6 +133,8 @@
   ASSERT(destination[2] == 2);
   ASSERT(destination[3] == 0);
 #endif
+
+#endif
 #endif
 #endif
 }
@@ -103,6 +146,7 @@
 
 void testLarge(void)
 {
+#if {part} == 2
 #ifdef TEST_LARGE
   memset(largedest, 0, 1050);
   memset(largedest, 1, 4);
@@ -114,5 +158,71 @@
   ASSERT(largedest[1] == 2);
   ASSERT(largedest[1024] == 2);
   ASSERT(largedest[1025] == 0);
+
+  /* Test strlen with large string */
+  memset(largesource, 'x', 999);
+  largesource[999] = '\0';
+  ASSERT(strlen(largesource) == 999);
+
+  /* Test memmove() with large (>255) counts */
+  unsigned char *ls_a = largesource + 0;
+  unsigned char *ls_b = largesource + 500;
+
+  ret = memset(ls_a, 'a', 500);
+  ASSERT(ret == ls_a);
+  ret = memset(ls_b, 'b', 500);
+  ASSERT(ret == ls_b);
+  ASSERT(ls_a[0] == 'a' && ls_a[499] == 'a');
+  ASSERT(ls_b[0] == 'b' && ls_b[499] == 'b');
+
+  // => aa--
+  ret = memmove(largedest, ls_a, 500); // put 'a' in first half of dest
+  ASSERT(ret == largedest);
+  ASSERT(memcmp(largedest, ls_a, 500) == 0);
+
+  // => aaaa
+  ret = memmove(largedest + 500, largedest, 500); // copy to last half (no overlap)
+  ASSERT(ret == largedest + 500);
+  ASSERT(memcmp(largedest + 500, ls_a, 500) == 0);
+
+  // => abba
+  ret = memmove(largedest + 250, ls_b, 500); // put 'b' in middle half
+  ASSERT(ret == largedest + 250);
+  ASSERT(memcmp(largedest, ls_a, 250) == 0);
+  ASSERT(memcmp(largedest + 250, ls_b, 500) == 0);
+  ASSERT(memcmp(largedest + 750, ls_a, 250) == 0);
+
+  // => abaa
+  ret = memmove(largedest + 250, largedest + 500, 500); // overlap to left
+  ASSERT(ret == largedest + 250);
+  ASSERT(memcmp(largedest, ls_a, 250) == 0);
+  ASSERT(memcmp(largedest + 250, ls_b, 250) == 0);
+  ASSERT(memcmp(largedest + 500, ls_a, 500) == 0);
+
+  // => abba
+  ret = memmove(largedest + 500, largedest + 250, 500); // overlap to right
+  ASSERT(ret == largedest + 500);
+  ASSERT(memcmp(largedest, ls_a, 250) == 0);
+  ASSERT(memcmp(largedest + 250, ls_b, 500) == 0);
+  ASSERT(memcmp(largedest + 750, ls_a, 250) == 0);
+#endif
+#endif
+}
+
+void testRetVal(void)
+{
+#if {part} == 3
+  volatile size_t one = 1;
+  volatile size_t zero = 0;
+  ASSERT(destination == memcpy(destination, source, sizeof(source)));
+  ASSERT(destination == memcpy(destination, source, 0));
+  ASSERT(destination == memcpy(destination, source, zero));
+  ASSERT(destination == memcpy(destination, source, one));
+  ASSERT(destination == memset(destination, (int)one, zero));
+  ASSERT(destination == memset(destination, (int)zero, 0));
+  ASSERT(destination == memset(destination, (int)zero, one));
+  ASSERT(destination == memset(destination, (int)one, sizeof(destination)));
+  ASSERT(&one == memset(&one, 0, sizeof(one)));
+  ASSERT(&zero == memcpy(&zero, &one, sizeof(one)));
 #endif
 }
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-pointer_arith_algebraic_properties_2_global.c sdcc-4.2.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-pointer_arith_algebraic_properties_2_global.c
--- sdcc-4.0.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-pointer_arith_algebraic_properties_2_global.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-pointer_arith_algebraic_properties_2_global.c	2020-04-03 19:34:37.000000000 +0000
@@ -0,0 +1,40 @@
+// Derived from test case from the memory model study group of SC22 WG14
+// For this test, behaviour is defined in the PNVI-ae-udi memory model.
+
+/*
+Original test copyright (c) 2012-2016 David Chisnall, Kayvan Memarian, and Peter Sewell.
+
+Permission to use, copy, modify, and/or distribute this software for
+any purpose with or without fee is hereby granted, provided that the
+above copyright notice and this permission notice appear in all
+copies.
+
+THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+PERFORMANCE OF THIS SOFTWARE.
+*/
+
+// Adapted for SDCC by Philipp Klaus Krause in 2020.
+
+#include 
+
+#pragma disable_warning 127
+
+#include 
+
+int y[2], x[2];
+
+void
+testMM(void)
+{
+  int *p=(int*)(((uintptr_t)&(x[0])) + 
+    (((uintptr_t)&(y[1]))-((uintptr_t)&(y[0]))));
+  *p = 11;  // is this free of undefined behaviour?
+  ASSERT (x[1] == *p);
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-pointer_arith_algebraic_properties_3_global.c sdcc-4.2.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-pointer_arith_algebraic_properties_3_global.c
--- sdcc-4.0.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-pointer_arith_algebraic_properties_3_global.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-pointer_arith_algebraic_properties_3_global.c	2020-04-03 19:34:37.000000000 +0000
@@ -0,0 +1,42 @@
+// Derived from test case from the memory model study group of SC22 WG14
+// For this test, behaviour is defined in the PNVI-ae-udi memory model.
+
+/*
+Original test copyright (c) 2012-2016 David Chisnall, Kayvan Memarian, and Peter Sewell.
+
+Permission to use, copy, modify, and/or distribute this software for
+any purpose with or without fee is hereby granted, provided that the
+above copyright notice and this permission notice appear in all
+copies.
+
+THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+PERFORMANCE OF THIS SOFTWARE.
+*/
+
+// Adapted for SDCC by Philipp Klaus Krause in 2020.
+
+#include 
+
+#pragma disable_warning 127
+
+#include 
+
+int y[2], x[2];
+
+void
+testMM(void)
+{
+  int *p=(int*)(
+    (((uintptr_t)&(x[0])) + ((uintptr_t)&(y[1])))
+    -((uintptr_t)&(y[0])) );
+  *p = 11;  // is this free of undefined behaviour?
+  //(equivalent to the &x[0]+(&(y[1])-&(y[0])) version?)
+  ASSERT (x[1] == *p);
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-pointer_copy_memcpy.c sdcc-4.2.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-pointer_copy_memcpy.c
--- sdcc-4.0.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-pointer_copy_memcpy.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-pointer_copy_memcpy.c	2020-04-03 19:34:37.000000000 +0000
@@ -0,0 +1,39 @@
+// Derived from test case from the memory model study group of SC22 WG14
+// For this test, behaviour is defined in the PNVI-ae-udi memory model.
+
+/*
+Original test copyright (c) 2012-2016 David Chisnall, Kayvan Memarian, and Peter Sewell.
+
+Permission to use, copy, modify, and/or distribute this software for
+any purpose with or without fee is hereby granted, provided that the
+above copyright notice and this permission notice appear in all
+copies.
+
+THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+PERFORMANCE OF THIS SOFTWARE.
+*/
+
+// Adapted for SDCC by Philipp Klaus Krause in 2020.
+
+#include 
+
+#include 
+
+int x=1;
+
+void
+testMM(void)
+{
+  int *p = &x;
+  int *q;
+  memcpy (&q, &p, sizeof p); 
+  *q = 11; // is this free of undefined behaviour?
+  ASSERT (*p == *q);
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-pointer_copy_user_ctrlflow_bitwise.c sdcc-4.2.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-pointer_copy_user_ctrlflow_bitwise.c
--- sdcc-4.0.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-pointer_copy_user_ctrlflow_bitwise.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-pointer_copy_user_ctrlflow_bitwise.c	2020-04-03 19:34:37.000000000 +0000
@@ -0,0 +1,53 @@
+// Derived from test case from the memory model study group of SC22 WG14
+// For this test, behaviour is defined in the PNVI-ae-udi memory model.
+
+/*
+Original test copyright (c) 2012-2016 David Chisnall, Kayvan Memarian, and Peter Sewell.
+
+Permission to use, copy, modify, and/or distribute this software for
+any purpose with or without fee is hereby granted, provided that the
+above copyright notice and this permission notice appear in all
+copies.
+
+THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+PERFORMANCE OF THIS SOFTWARE.
+*/
+
+// Adapted for SDCC by Philipp Klaus Krause in 2020.
+
+#include 
+
+#pragma disable_warning 127
+
+#include 
+#include 
+
+int x=1;
+
+void
+testMM(void)
+{
+  int *p = &x;
+  uintptr_t i = (uintptr_t)p;
+  int uintptr_t_width = sizeof(uintptr_t) * CHAR_BIT;
+  uintptr_t bit, j;
+  int k;
+  j=0;
+  for (k=0; k> k;
+    if (bit == 1) 
+      j = j | ((uintptr_t)1 << k);
+    else
+      j = j;
+  }
+  int *q = (int *)j;
+  *q = 11; // is this free of undefined behaviour?
+  ASSERT (*p == *q);
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-pointer_copy_user_ctrlflow_bytewise.c sdcc-4.2.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-pointer_copy_user_ctrlflow_bytewise.c
--- sdcc-4.0.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-pointer_copy_user_ctrlflow_bytewise.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-pointer_copy_user_ctrlflow_bytewise.c	2020-04-03 19:34:37.000000000 +0000
@@ -0,0 +1,313 @@
+// Derived from test case from the memory model study group of SC22 WG14
+// For this test, behaviour is defined in the PNVI-ae-udi memory model.
+
+/*
+Original test copyright (c) 2012-2016 David Chisnall, Kayvan Memarian, and Peter Sewell.
+
+Permission to use, copy, modify, and/or distribute this software for
+any purpose with or without fee is hereby granted, provided that the
+above copyright notice and this permission notice appear in all
+copies.
+
+THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+PERFORMANCE OF THIS SOFTWARE.
+*/
+
+// Adapted for SDCC by Philipp Klaus Krause in 2020.
+
+#include 
+
+#include 
+#include 
+
+int x=1;
+unsigned char control_flow_copy(unsigned char c) {
+  switch (c) {
+  case 0: return(0);
+  case 1: return(1);
+  case 2: return(2);
+  case 3: return(3);
+  case 4: return(4);
+  case 5: return(5);
+  case 6: return(6);
+  case 7: return(7);
+  case 8: return(8);
+  case 9: return(9);
+  case 10: return(10);
+  case 11: return(11);
+  case 12: return(12);
+  case 13: return(13);
+  case 14: return(14);
+  case 15: return(15);
+  case 16: return(16);
+  case 17: return(17);
+  case 18: return(18);
+  case 19: return(19);
+  case 20: return(20);
+  case 21: return(21);
+  case 22: return(22);
+  case 23: return(23);
+  case 24: return(24);
+  case 25: return(25);
+  case 26: return(26);
+  case 27: return(27);
+  case 28: return(28);
+  case 29: return(29);
+  case 30: return(30);
+  case 31: return(31);
+  case 32: return(32);
+  case 33: return(33);
+  case 34: return(34);
+  case 35: return(35);
+  case 36: return(36);
+  case 37: return(37);
+  case 38: return(38);
+  case 39: return(39);
+  case 40: return(40);
+  case 41: return(41);
+  case 42: return(42);
+  case 43: return(43);
+  case 44: return(44);
+  case 45: return(45);
+  case 46: return(46);
+  case 47: return(47);
+  case 48: return(48);
+  case 49: return(49);
+  case 50: return(50);
+  case 51: return(51);
+  case 52: return(52);
+  case 53: return(53);
+  case 54: return(54);
+  case 55: return(55);
+  case 56: return(56);
+  case 57: return(57);
+  case 58: return(58);
+  case 59: return(59);
+  case 60: return(60);
+  case 61: return(61);
+  case 62: return(62);
+  case 63: return(63);
+  case 64: return(64);
+  case 65: return(65);
+  case 66: return(66);
+  case 67: return(67);
+  case 68: return(68);
+  case 69: return(69);
+  case 70: return(70);
+  case 71: return(71);
+  case 72: return(72);
+  case 73: return(73);
+  case 74: return(74);
+  case 75: return(75);
+  case 76: return(76);
+  case 77: return(77);
+  case 78: return(78);
+  case 79: return(79);
+  case 80: return(80);
+  case 81: return(81);
+  case 82: return(82);
+  case 83: return(83);
+  case 84: return(84);
+  case 85: return(85);
+  case 86: return(86);
+  case 87: return(87);
+  case 88: return(88);
+  case 89: return(89);
+  case 90: return(90);
+  case 91: return(91);
+  case 92: return(92);
+  case 93: return(93);
+  case 94: return(94);
+  case 95: return(95);
+  case 96: return(96);
+  case 97: return(97);
+  case 98: return(98);
+  case 99: return(99);
+  case 100: return(100);
+  case 101: return(101);
+  case 102: return(102);
+  case 103: return(103);
+  case 104: return(104);
+  case 105: return(105);
+  case 106: return(106);
+  case 107: return(107);
+  case 108: return(108);
+  case 109: return(109);
+  case 110: return(110);
+  case 111: return(111);
+  case 112: return(112);
+  case 113: return(113);
+  case 114: return(114);
+  case 115: return(115);
+  case 116: return(116);
+  case 117: return(117);
+  case 118: return(118);
+  case 119: return(119);
+  case 120: return(120);
+  case 121: return(121);
+  case 122: return(122);
+  case 123: return(123);
+  case 124: return(124);
+  case 125: return(125);
+  case 126: return(126);
+  case 127: return(127);
+  case 128: return(128);
+  case 129: return(129);
+  case 130: return(130);
+  case 131: return(131);
+  case 132: return(132);
+  case 133: return(133);
+  case 134: return(134);
+  case 135: return(135);
+  case 136: return(136);
+  case 137: return(137);
+  case 138: return(138);
+  case 139: return(139);
+  case 140: return(140);
+  case 141: return(141);
+  case 142: return(142);
+  case 143: return(143);
+  case 144: return(144);
+  case 145: return(145);
+  case 146: return(146);
+  case 147: return(147);
+  case 148: return(148);
+  case 149: return(149);
+  case 150: return(150);
+  case 151: return(151);
+  case 152: return(152);
+  case 153: return(153);
+  case 154: return(154);
+  case 155: return(155);
+  case 156: return(156);
+  case 157: return(157);
+  case 158: return(158);
+  case 159: return(159);
+  case 160: return(160);
+  case 161: return(161);
+  case 162: return(162);
+  case 163: return(163);
+  case 164: return(164);
+  case 165: return(165);
+  case 166: return(166);
+  case 167: return(167);
+  case 168: return(168);
+  case 169: return(169);
+  case 170: return(170);
+  case 171: return(171);
+  case 172: return(172);
+  case 173: return(173);
+  case 174: return(174);
+  case 175: return(175);
+  case 176: return(176);
+  case 177: return(177);
+  case 178: return(178);
+  case 179: return(179);
+  case 180: return(180);
+  case 181: return(181);
+  case 182: return(182);
+  case 183: return(183);
+  case 184: return(184);
+  case 185: return(185);
+  case 186: return(186);
+  case 187: return(187);
+  case 188: return(188);
+  case 189: return(189);
+  case 190: return(190);
+  case 191: return(191);
+  case 192: return(192);
+  case 193: return(193);
+  case 194: return(194);
+  case 195: return(195);
+  case 196: return(196);
+  case 197: return(197);
+  case 198: return(198);
+  case 199: return(199);
+  case 200: return(200);
+  case 201: return(201);
+  case 202: return(202);
+  case 203: return(203);
+  case 204: return(204);
+  case 205: return(205);
+  case 206: return(206);
+  case 207: return(207);
+  case 208: return(208);
+  case 209: return(209);
+  case 210: return(210);
+  case 211: return(211);
+  case 212: return(212);
+  case 213: return(213);
+  case 214: return(214);
+  case 215: return(215);
+  case 216: return(216);
+  case 217: return(217);
+  case 218: return(218);
+  case 219: return(219);
+  case 220: return(220);
+  case 221: return(221);
+  case 222: return(222);
+  case 223: return(223);
+  case 224: return(224);
+  case 225: return(225);
+  case 226: return(226);
+  case 227: return(227);
+  case 228: return(228);
+  case 229: return(229);
+  case 230: return(230);
+  case 231: return(231);
+  case 232: return(232);
+  case 233: return(233);
+  case 234: return(234);
+  case 235: return(235);
+  case 236: return(236);
+  case 237: return(237);
+  case 238: return(238);
+  case 239: return(239);
+  case 240: return(240);
+  case 241: return(241);
+  case 242: return(242);
+  case 243: return(243);
+  case 244: return(244);
+  case 245: return(245);
+  case 246: return(246);
+  case 247: return(247);
+  case 248: return(248);
+  case 249: return(249);
+  case 250: return(250);
+  case 251: return(251);
+  case 252: return(252);
+  case 253: return(253);
+  case 254: return(254);
+  case 255: return(255);
+  }
+}
+
+void user_memcpy2(unsigned char* dest, 
+                  unsigned char *src, size_t n) {
+  while (n > 0)  {		
+    *dest = control_flow_copy(*src);
+    src += 1;
+    dest += 1;
+    n -= 1;
+  }
+}
+
+void
+testMM(void)
+{
+  int *p = &x;
+  int *q;
+  user_memcpy2((unsigned char*)&q, (unsigned char*)&p, 
+              sizeof(p));
+  if (UCHAR_MAX==255) {
+    *q = 11; // does this have undefined behaviour?
+    ASSERT (*p == *q);
+  }
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-pointer_copy_user_dataflow_direct_bytewise.c sdcc-4.2.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-pointer_copy_user_dataflow_direct_bytewise.c
--- sdcc-4.0.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-pointer_copy_user_dataflow_direct_bytewise.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-pointer_copy_user_dataflow_direct_bytewise.c	2020-04-03 19:34:37.000000000 +0000
@@ -0,0 +1,48 @@
+// Derived from test case from the memory model study group of SC22 WG14
+// For this test, behaviour is defined in the PNVI-ae-udi memory model.
+
+/*
+Original test copyright (c) 2012-2016 David Chisnall, Kayvan Memarian, and Peter Sewell.
+
+Permission to use, copy, modify, and/or distribute this software for
+any purpose with or without fee is hereby granted, provided that the
+above copyright notice and this permission notice appear in all
+copies.
+
+THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+PERFORMANCE OF THIS SOFTWARE.
+*/
+
+// Adapted for SDCC by Philipp Klaus Krause in 2020.
+
+#include 
+
+#include 
+
+int  x=1;
+
+void user_memcpy(unsigned char* dest, 
+                 unsigned char *src, size_t n) {
+  while (n > 0)  {		
+    *dest = *src;
+    src += 1; dest += 1; n -= 1;
+  }
+}
+
+void
+testMM(void)
+{
+  int *p = &x;
+  int *q;
+  user_memcpy((unsigned char*)&q, 
+              (unsigned char*)&p, sizeof(int *));
+  *q = 11; // is this free of undefined behaviour?
+  ASSERT (*p == *q);
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-pointer_from_int_disambiguation_1.c sdcc-4.2.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-pointer_from_int_disambiguation_1.c
--- sdcc-4.0.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-pointer_from_int_disambiguation_1.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-pointer_from_int_disambiguation_1.c	2020-04-03 19:34:37.000000000 +0000
@@ -0,0 +1,48 @@
+// Derived from test case from the memory model study group of SC22 WG14
+// For this test, behaviour is defined in the PNVI-ae-udi memory model.
+
+/*
+Original test copyright (c) 2012-2016 David Chisnall, Kayvan Memarian, and Peter Sewell.
+
+Permission to use, copy, modify, and/or distribute this software for
+any purpose with or without fee is hereby granted, provided that the
+above copyright notice and this permission notice appear in all
+copies.
+
+THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+PERFORMANCE OF THIS SOFTWARE.
+*/
+
+// Adapted for SDCC by Philipp Klaus Krause in 2020.
+
+#include 
+
+#pragma disable_warning 127
+
+#include  
+#include 
+
+int y=2, x=1;
+
+void
+testMM(void)
+{
+#if !(defined (__GNUC__)) // As of GCC 9, GCC is not PNVI-ae-udi-compliant.
+  int *p = &x+1;
+  int *q = &y;
+  uintptr_t i = (uintptr_t)p;
+  uintptr_t j = (uintptr_t)q;
+  if (memcmp(&p, &q, sizeof(p)) == 0) {
+    int *r = (int *)i;
+    *r=11;  // is this free of UB?
+    ASSERT (y == 11);
+  }
+#endif
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-pointer_from_int_disambiguation_1_xy.c sdcc-4.2.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-pointer_from_int_disambiguation_1_xy.c
--- sdcc-4.0.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-pointer_from_int_disambiguation_1_xy.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-pointer_from_int_disambiguation_1_xy.c	2021-04-22 09:19:50.000000000 +0000
@@ -0,0 +1,48 @@
+// Derived from test case from the memory model study group of SC22 WG14
+// For this test, behaviour is defined in the PNVI-ae-udi memory model.
+
+/*
+Original test copyright (c) 2012-2016 David Chisnall, Kayvan Memarian, and Peter Sewell.
+
+Permission to use, copy, modify, and/or distribute this software for
+any purpose with or without fee is hereby granted, provided that the
+above copyright notice and this permission notice appear in all
+copies.
+
+THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+PERFORMANCE OF THIS SOFTWARE.
+*/
+
+// Adapted for SDCC by Philipp Klaus Krause in 2020.
+
+#include 
+
+#pragma disable_warning 127
+
+#include  
+#include 
+
+int x=1, y=2;
+
+void
+testMM(void)
+{
+#if !(defined(__clang__) && __clang_major__ <= 11) // On FreeBSD 13 on arch64, this test fails for clang 11. On amd64 it fails for clang 6.
+  int *p = &x+1;
+  int *q = &y;
+  uintptr_t i = (uintptr_t)p;
+  uintptr_t j = (uintptr_t)q;
+  if (memcmp(&p, &q, sizeof(p)) == 0) {
+    int *r = (int *)i;
+    *r=11;  // is this free of UB?
+    ASSERT (y == 11);
+  }
+#endif // __clang__
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-pointer_from_int_disambiguation_2.c sdcc-4.2.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-pointer_from_int_disambiguation_2.c
--- sdcc-4.0.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-pointer_from_int_disambiguation_2.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-pointer_from_int_disambiguation_2.c	2020-04-04 10:17:57.000000000 +0000
@@ -0,0 +1,50 @@
+// Derived from test case from the memory model study group of SC22 WG14
+// For this test, behaviour is defined in the PNVI-ae-udi memory model.
+
+/*
+Original test copyright (c) 2012-2016 David Chisnall, Kayvan Memarian, and Peter Sewell.
+
+Permission to use, copy, modify, and/or distribute this software for
+any purpose with or without fee is hereby granted, provided that the
+above copyright notice and this permission notice appear in all
+copies.
+
+THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+PERFORMANCE OF THIS SOFTWARE.
+*/
+
+// Adapted for SDCC by Philipp Klaus Krause in 2020.
+
+#include 
+
+#pragma disable_warning 127
+
+#include  
+#include 
+
+int y=2, x=1;
+
+void
+testMM(void)
+{
+#if !(defined (__GNUC__)) // As of GCC 9, GCC is not PNVI-ae-udi-compliant.
+  int *p = &x+1;
+  int *q = &y;
+  uintptr_t i = (uintptr_t)p;
+  uintptr_t j = (uintptr_t)q;
+  if (memcmp(&p, &q, sizeof(p)) == 0) {
+    int *r = (int *)i;
+    r=r-1;  // is this free of UB?
+    *r=11;  // and this?
+    ASSERT (x == *r);
+    ASSERT (x == 11);
+  }
+#endif
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-pointer_from_int_disambiguation_2_xy.c sdcc-4.2.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-pointer_from_int_disambiguation_2_xy.c
--- sdcc-4.0.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-pointer_from_int_disambiguation_2_xy.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-pointer_from_int_disambiguation_2_xy.c	2020-04-04 10:19:59.000000000 +0000
@@ -0,0 +1,46 @@
+// Derived from test case from the memory model study group of SC22 WG14
+// For this test, behaviour is defined in the PNVI-ae-udi memory model.
+
+/*
+Original test copyright (c) 2012-2016 David Chisnall, Kayvan Memarian, and Peter Sewell.
+
+Permission to use, copy, modify, and/or distribute this software for
+any purpose with or without fee is hereby granted, provided that the
+above copyright notice and this permission notice appear in all
+copies.
+
+THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+PERFORMANCE OF THIS SOFTWARE.
+*/
+
+// Adapted for SDCC by Philipp Klaus Krause in 2020.
+
+#include 
+
+#include  
+#include 
+
+int x=1, y=2;
+
+void
+testMM(void)
+{
+  int *p = &x+1;
+  int *q = &y;
+  uintptr_t i = (uintptr_t)p;
+  uintptr_t j = (uintptr_t)q;
+  if (memcmp(&p, &q, sizeof(p)) == 0) {
+    int *r = (int *)i;
+    r=r-1;  // is this free of UB?
+    *r=11;  // and this?    
+    ASSERT (x == *r);
+    ASSERT (x == 11);
+  }
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-pointer_from_integer_2g.c sdcc-4.2.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-pointer_from_integer_2g.c
--- sdcc-4.0.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-pointer_from_integer_2g.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-pointer_from_integer_2g.c	2021-12-10 14:48:15.000000000 +0000
@@ -0,0 +1,56 @@
+// Derived from test case from the memory model study group of SC22 WG14
+// For this test, behaviour is defined in the PNVI-ae-udi memory model.
+
+/*
+Original test copyright (c) 2012-2016 David Chisnall, Kayvan Memarian, and Peter Sewell.
+
+Permission to use, copy, modify, and/or distribute this software for
+any purpose with or without fee is hereby granted, provided that the
+above copyright notice and this permission notice appear in all
+copies.
+
+THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+PERFORMANCE OF THIS SOFTWARE.
+*/
+
+// Adapted for SDCC by Philipp Klaus Krause in 2020.
+
+#include 
+
+#pragma disable_warning 127
+
+#include 
+
+// Guess address of j.
+#if defined (__SDCC_pdk14)
+#define ADDRESS_PFI_2G 42
+#elif defined (__SDCC_pdk14)
+#define ADDRESS_PFI_2G 0x17fc
+#elif defined (__SDCC_sm83)
+#define ADDRESS_PFI_2G 0xdff8
+#else
+#define ADDRESS_PFI_2G 0
+#endif
+
+void f() {
+  uintptr_t i=ADDRESS_PFI_2G;
+  int *p = (int*)i;
+  *p=7;
+}
+
+void
+testMM(void)
+{
+  int j=5;
+  if ((uintptr_t)&j == ADDRESS_PFI_2G) {
+    f();
+    ASSERT (j == 7);
+  }
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-pointer_offset_from_int_subtraction_auto_xy.c sdcc-4.2.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-pointer_offset_from_int_subtraction_auto_xy.c
--- sdcc-4.0.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-pointer_offset_from_int_subtraction_auto_xy.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-pointer_offset_from_int_subtraction_auto_xy.c	2020-04-04 17:43:48.000000000 +0000
@@ -0,0 +1,47 @@
+// Derived from test case from the memory model study group of SC22 WG14
+// For this test, behaviour is defined in the PNVI-ae-udi memory model.
+
+/*
+Original test copyright (c) 2012-2016 David Chisnall, Kayvan Memarian, and Peter Sewell.
+
+Permission to use, copy, modify, and/or distribute this software for
+any purpose with or without fee is hereby granted, provided that the
+above copyright notice and this permission notice appear in all
+copies.
+
+THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+PERFORMANCE OF THIS SOFTWARE.
+*/
+
+// Adapted for SDCC by Philipp Klaus Krause in 2020.
+
+#include 
+
+#pragma disable_warning 127
+
+#include  
+#include 
+
+void
+testMM(void)
+{
+  int x=1, y=2;
+  uintptr_t ux = (uintptr_t)&x;
+  uintptr_t uy = (uintptr_t)&y;
+  uintptr_t offset = uy - ux;
+
+  int *p = (int *)(ux + offset);
+  int *q = &y;
+  if (memcmp(&p, &q, sizeof(p)) == 0) {
+    *p = 11; // is this free of UB?
+    ASSERT (*p == *q);
+    ASSERT (*p == y);
+  }
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-pointer_offset_from_int_subtraction_auto_yx.c sdcc-4.2.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-pointer_offset_from_int_subtraction_auto_yx.c
--- sdcc-4.0.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-pointer_offset_from_int_subtraction_auto_yx.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-pointer_offset_from_int_subtraction_auto_yx.c	2020-04-04 17:43:48.000000000 +0000
@@ -0,0 +1,47 @@
+// Derived from test case from the memory model study group of SC22 WG14
+// For this test, behaviour is defined in the PNVI-ae-udi memory model.
+
+/*
+Original test copyright (c) 2012-2016 David Chisnall, Kayvan Memarian, and Peter Sewell.
+
+Permission to use, copy, modify, and/or distribute this software for
+any purpose with or without fee is hereby granted, provided that the
+above copyright notice and this permission notice appear in all
+copies.
+
+THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+PERFORMANCE OF THIS SOFTWARE.
+*/
+
+// Adapted for SDCC by Philipp Klaus Krause in 2020.
+
+#include 
+
+#pragma disable_warning 127
+
+#include  
+#include 
+
+void
+testMM(void)
+{
+  int y=2, x=1;
+  uintptr_t ux = (uintptr_t)&x;
+  uintptr_t uy = (uintptr_t)&y;
+  uintptr_t offset = uy - ux;
+
+  int *p = (int *)(ux + offset);
+  int *q = &y;
+  if (memcmp(&p, &q, sizeof(p)) == 0) {
+    *p = 11; // is this free of UB?
+    ASSERT (*p == *q);
+    ASSERT (*p == y);
+  }
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-pointer_offset_from_int_subtraction_global_xy.c sdcc-4.2.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-pointer_offset_from_int_subtraction_global_xy.c
--- sdcc-4.0.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-pointer_offset_from_int_subtraction_global_xy.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-pointer_offset_from_int_subtraction_global_xy.c	2020-04-03 19:34:37.000000000 +0000
@@ -0,0 +1,48 @@
+// Derived from test case from the memory model study group of SC22 WG14
+// For this test, behaviour is defined in the PNVI-ae-udi memory model.
+
+/*
+Original test copyright (c) 2012-2016 David Chisnall, Kayvan Memarian, and Peter Sewell.
+
+Permission to use, copy, modify, and/or distribute this software for
+any purpose with or without fee is hereby granted, provided that the
+above copyright notice and this permission notice appear in all
+copies.
+
+THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+PERFORMANCE OF THIS SOFTWARE.
+*/
+
+// Adapted for SDCC by Philipp Klaus Krause in 2020.
+
+#include 
+
+#pragma disable_warning 127
+
+#include  
+#include 
+
+int x=1, y=2;
+
+void
+testMM(void)
+{
+  uintptr_t ux = (uintptr_t)&x;
+  uintptr_t uy = (uintptr_t)&y;
+  uintptr_t offset = uy - ux;
+
+  int *p = (int *)(ux + offset);
+  int *q = &y;
+  if (memcmp(&p, &q, sizeof(p)) == 0) {
+    *p = 11; // is this free of UB?
+    ASSERT (*p == *q);
+    ASSERT (*p == y);
+  }
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-pointer_offset_from_int_subtraction_global_yx.c sdcc-4.2.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-pointer_offset_from_int_subtraction_global_yx.c
--- sdcc-4.0.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-pointer_offset_from_int_subtraction_global_yx.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-pointer_offset_from_int_subtraction_global_yx.c	2020-04-03 19:34:37.000000000 +0000
@@ -0,0 +1,48 @@
+// Derived from test case from the memory model study group of SC22 WG14
+// For this test, behaviour is defined in the PNVI-ae-udi memory model.
+
+/*
+Original test copyright (c) 2012-2016 David Chisnall, Kayvan Memarian, and Peter Sewell.
+
+Permission to use, copy, modify, and/or distribute this software for
+any purpose with or without fee is hereby granted, provided that the
+above copyright notice and this permission notice appear in all
+copies.
+
+THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+PERFORMANCE OF THIS SOFTWARE.
+*/
+
+// Adapted for SDCC by Philipp Klaus Krause in 2020.
+
+#include 
+
+#pragma disable_warning 127
+
+#include  
+#include 
+
+int y=2, x=1;
+
+void
+testMM(void)
+{
+  uintptr_t ux = (uintptr_t)&x;
+  uintptr_t uy = (uintptr_t)&y;
+  uintptr_t offset = uy - ux;
+
+  int *p = (int *)(ux + offset);
+  int *q = &y;
+  if (memcmp(&p, &q, sizeof(p)) == 0) {
+    *p = 11; // is this free of UB?
+    ASSERT (*p == *q);
+    ASSERT (*p == y);
+  }
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-pointer_offset_xor_auto.c sdcc-4.2.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-pointer_offset_xor_auto.c
--- sdcc-4.0.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-pointer_offset_xor_auto.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-pointer_offset_xor_auto.c	2020-04-04 20:04:38.000000000 +0000
@@ -0,0 +1,47 @@
+// Derived from test case from the memory model study group of SC22 WG14
+// For this test, behaviour is defined in the PNVI-ae-udi memory model.
+
+/*
+Original test copyright (c) 2012-2016 David Chisnall, Kayvan Memarian, and Peter Sewell.
+
+Permission to use, copy, modify, and/or distribute this software for
+any purpose with or without fee is hereby granted, provided that the
+above copyright notice and this permission notice appear in all
+copies.
+
+THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+PERFORMANCE OF THIS SOFTWARE.
+*/
+
+// Adapted for SDCC by Philipp Klaus Krause in 2020.
+
+#include 
+
+#pragma disable_warning 127
+
+#include 
+
+void
+testMM(void)
+{
+  int x=1, y=2;
+  int *p = &x;
+  int *q = &y;
+  uintptr_t i = (uintptr_t) p;
+  uintptr_t j = (uintptr_t) q;
+  uintptr_t k = i ^ j;
+  uintptr_t l = k ^ i;
+  int *r = (int *)l;
+  // are r and q now equivalent?  
+  *r = 11;     // does this have defined behaviour?             
+  _Bool b = (r==q); 
+  if (b)
+    ASSERT (*r == y);
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-pointer_offset_xor_global.c sdcc-4.2.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-pointer_offset_xor_global.c
--- sdcc-4.0.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-pointer_offset_xor_global.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-pointer_offset_xor_global.c	2020-04-03 19:34:37.000000000 +0000
@@ -0,0 +1,49 @@
+// Derived from test case from the memory model study group of SC22 WG14
+// For this test, behaviour is defined in the PNVI-ae-udi memory model.
+
+/*
+Original test copyright (c) 2012-2016 David Chisnall, Kayvan Memarian, and Peter Sewell.
+
+Permission to use, copy, modify, and/or distribute this software for
+any purpose with or without fee is hereby granted, provided that the
+above copyright notice and this permission notice appear in all
+copies.
+
+THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+PERFORMANCE OF THIS SOFTWARE.
+*/
+
+// Adapted for SDCC by Philipp Klaus Krause in 2020.
+
+#include 
+
+#pragma disable_warning 127
+
+#include 
+
+int x=1;
+int y=2;  
+
+void
+testMM(void)
+{
+  int *p = &x;
+  int *q = &y;
+  uintptr_t i = (uintptr_t) p;
+  uintptr_t j = (uintptr_t) q;
+  uintptr_t k = i ^ j;
+  uintptr_t l = k ^ i;
+  int *r = (int *)l;
+  // are r and q now equivalent?  
+  *r = 11;     // does this have defined behaviour?             
+  _Bool b = (r==q); 
+  if (b)
+    ASSERT (*r == y);
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-provenance_basic_using_uintptr_t_auto_xy.c sdcc-4.2.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-provenance_basic_using_uintptr_t_auto_xy.c
--- sdcc-4.0.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-provenance_basic_using_uintptr_t_auto_xy.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-provenance_basic_using_uintptr_t_auto_xy.c	2020-04-03 19:34:37.000000000 +0000
@@ -0,0 +1,50 @@
+// Derived from test case from the memory model study group of SC22 WG14
+// For this test, behaviour is defined in the PNVI-ae-udi memory model.
+
+/*
+Original test copyright (c) 2012-2016 David Chisnall, Kayvan Memarian, and Peter Sewell.
+
+Permission to use, copy, modify, and/or distribute this software for
+any purpose with or without fee is hereby granted, provided that the
+above copyright notice and this permission notice appear in all
+copies.
+
+THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+PERFORMANCE OF THIS SOFTWARE.
+*/
+
+// Adapted for SDCC by Philipp Klaus Krause in 2020.
+
+#include 
+
+#pragma disable_warning 127
+
+#include  
+#include 
+
+void
+testMM(void)
+{
+#if !(defined (__GNUC__)) // As of GCC 9, GCC is not PNVI-ae-udi-compliant.
+  int x=1, y=2;
+  uintptr_t ux = (uintptr_t)&x;
+  uintptr_t uy = (uintptr_t)&y;
+  uintptr_t offset = sizeof(int);
+  ux = ux + offset;
+  int *p = (int*)ux; // does this have undefined behaviour?
+  int *q = &y;
+
+  if (memcmp(&p, &q, sizeof(p)) == 0) {
+    *p = 11; // does this have undefined behaviour?
+    ASSERT (*p == *q);
+    ASSERT (*p == y);
+  }
+#endif
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-provenance_basic_using_uintptr_t_auto_yx.c sdcc-4.2.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-provenance_basic_using_uintptr_t_auto_yx.c
--- sdcc-4.0.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-provenance_basic_using_uintptr_t_auto_yx.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-provenance_basic_using_uintptr_t_auto_yx.c	2021-04-22 09:19:50.000000000 +0000
@@ -0,0 +1,53 @@
+// Derived from test case from the memory model study group of SC22 WG14
+// For this test, behaviour is defined in the PNVI-ae-udi memory model.
+
+/*
+Original test copyright (c) 2012-2016 David Chisnall, Kayvan Memarian, and Peter Sewell.
+
+Permission to use, copy, modify, and/or distribute this software for
+any purpose with or without fee is hereby granted, provided that the
+above copyright notice and this permission notice appear in all
+copies.
+
+THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+PERFORMANCE OF THIS SOFTWARE.
+*/
+
+// Adapted for SDCC by Philipp Klaus Krause in 2020.
+
+#include 
+
+#pragma disable_warning 127
+
+#include  
+#include 
+
+void
+testMM(void)
+{
+// PNVI-ae-udi non-compliance in PPC for at least GCC 4.9.2 and GCC 7.2.0
+#if !(defined(__GNUC__) && (defined(__PPC__) || defined(__POWERPC__))) 
+#if !(defined(__clang__) && __clang_major__ <= 11) // On FreeBSD 13 on arch64, this test fails for clang 11. On amd64 it fails for clang 6.
+  int y=2, x=1;
+  uintptr_t ux = (uintptr_t)&x;
+  uintptr_t uy = (uintptr_t)&y;
+  uintptr_t offset = sizeof(int);
+  ux = ux + offset;
+  int *p = (int *)ux; // does this have undefined behaviour?
+  int *q = &y;
+
+  if (memcmp(&p, &q, sizeof(p)) == 0) {
+    *p = 11; // does this have undefined behaviour?
+    ASSERT (*p == *q);
+    ASSERT (*p == y);
+  }
+#endif // __clang__
+#endif
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-provenance_basic_using_uintptr_t_global_xy.c sdcc-4.2.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-provenance_basic_using_uintptr_t_global_xy.c
--- sdcc-4.0.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-provenance_basic_using_uintptr_t_global_xy.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-provenance_basic_using_uintptr_t_global_xy.c	2021-04-22 09:19:50.000000000 +0000
@@ -0,0 +1,50 @@
+// Derived from test case from the memory model study group of SC22 WG14
+// For this test, behaviour is defined in the PNVI-ae-udi memory model.
+
+/*
+Original test copyright (c) 2012-2016 David Chisnall, Kayvan Memarian, and Peter Sewell.
+
+Permission to use, copy, modify, and/or distribute this software for
+any purpose with or without fee is hereby granted, provided that the
+above copyright notice and this permission notice appear in all
+copies.
+
+THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+PERFORMANCE OF THIS SOFTWARE.
+*/
+
+// Adapted for SDCC by Philipp Klaus Krause in 2020.
+
+#include 
+
+#pragma disable_warning 127
+
+#include  
+#include 
+
+int x=1, y=2;
+
+void
+testMM(void)
+{
+#if !(defined(__clang__) && __clang_major__ <= 11) // On FreeBSD 13 on arch64, this test fails for clang 11.
+  uintptr_t ux = (uintptr_t)&x;
+  uintptr_t uy = (uintptr_t)&y;
+  uintptr_t offset = sizeof(int);
+  ux = ux + offset;
+  int *p = (int *)ux; // undefined behaviour?
+  int *q = &y;
+  if (memcmp(&p, &q, sizeof(p)) == 0) {
+    *p = 11; // does this have undefined behaviour?
+    ASSERT (*p == *q);
+    ASSERT (*p == y); 
+  }
+#endif
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-provenance_basic_using_uintptr_t_global_yx.c sdcc-4.2.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-provenance_basic_using_uintptr_t_global_yx.c
--- sdcc-4.0.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-provenance_basic_using_uintptr_t_global_yx.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-provenance_basic_using_uintptr_t_global_yx.c	2020-08-28 10:21:40.000000000 +0000
@@ -0,0 +1,54 @@
+// Derived from test case from the memory model study group of SC22 WG14
+// For this test, behaviour is defined in the PNVI-ae-udi memory model.
+
+/*
+Original test copyright (c) 2012-2016 David Chisnall, Kayvan Memarian, and Peter Sewell.
+
+Permission to use, copy, modify, and/or distribute this software for
+any purpose with or without fee is hereby granted, provided that the
+above copyright notice and this permission notice appear in all
+copies.
+
+THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+PERFORMANCE OF THIS SOFTWARE.
+*/
+
+// Adapted for SDCC by Philipp Klaus Krause in 2020.
+
+#include 
+
+#pragma disable_warning 127
+
+#include  
+#include 
+
+int y=2, x=1;
+
+void
+testMM(void)
+{
+#if !(defined (__GNUC__)) // As of GCC 9, GCC is not PNVI-ae-udi-compliant.
+#if !(defined (__clang__) && __clang_major__ <= 6)
+
+  uintptr_t ux = (uintptr_t)&x;
+  uintptr_t uy = (uintptr_t)&y;
+  uintptr_t offset = sizeof(int);
+  ux = ux + offset;
+  int *p = (int *)ux; // does this have undefined behaviour?
+  int *q = &y;
+  if (memcmp(&p, &q, sizeof(p)) == 0) {
+    *p = 11; // does this have undefined behaviour?
+    ASSERT (*p == *q);
+    ASSERT (*p == y); 
+  }
+
+#endif // __clang__
+#endif
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-provenance_roundtrip_via_intptr_t.c sdcc-4.2.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-provenance_roundtrip_via_intptr_t.c
--- sdcc-4.0.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-provenance_roundtrip_via_intptr_t.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-provenance_roundtrip_via_intptr_t.c	2020-04-03 19:34:37.000000000 +0000
@@ -0,0 +1,41 @@
+// Derived from test case from the memory model study group of SC22 WG14
+// For this test, behaviour is defined in the PNVI-ae-udi memory model.
+
+/*
+Original test copyright (c) 2012-2016 David Chisnall, Kayvan Memarian, and Peter Sewell.
+
+Permission to use, copy, modify, and/or distribute this software for
+any purpose with or without fee is hereby granted, provided that the
+above copyright notice and this permission notice appear in all
+copies.
+
+THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+PERFORMANCE OF THIS SOFTWARE.
+*/
+
+// Adapted for SDCC by Philipp Klaus Krause in 2020.
+
+#include 
+
+#pragma disable_warning 127
+
+#include 
+
+int x=1;
+
+void
+testMM(void)
+{
+  int *p = &x;
+  intptr_t i = (intptr_t)p;
+  int *q = (int *)i;
+  *q = 11; // is this free of undefined behaviour?
+  ASSERT(*p == *q);
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-provenance_roundtrip_via_intptr_t_onepast.c sdcc-4.2.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-provenance_roundtrip_via_intptr_t_onepast.c
--- sdcc-4.0.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-provenance_roundtrip_via_intptr_t_onepast.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-provenance_roundtrip_via_intptr_t_onepast.c	2020-04-03 19:34:37.000000000 +0000
@@ -0,0 +1,43 @@
+// Derived from test case from the memory model study group of SC22 WG14
+// For this test, behaviour is defined in the PNVI-ae-udi memory model.
+
+/*
+Original test copyright (c) 2012-2016 David Chisnall, Kayvan Memarian, and Peter Sewell.
+
+Permission to use, copy, modify, and/or distribute this software for
+any purpose with or without fee is hereby granted, provided that the
+above copyright notice and this permission notice appear in all
+copies.
+
+THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+PERFORMANCE OF THIS SOFTWARE.
+*/
+
+// Adapted for SDCC by Philipp Klaus Krause in 2020.
+
+#include 
+
+#pragma disable_warning 127
+
+#include 
+
+int x=1;
+
+void
+testMM(void)
+{
+  int *p = &x;
+  p=p+1;
+  intptr_t i = (intptr_t)p;
+  int *q = (int *)i;
+  q=q-1;
+  *q = 11; // is this free of undefined behaviour?
+  ASSERT (x == 11);
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-provenance_tag_bits_via_repr_byte_1.c sdcc-4.2.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-provenance_tag_bits_via_repr_byte_1.c
--- sdcc-4.0.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-provenance_tag_bits_via_repr_byte_1.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-provenance_tag_bits_via_repr_byte_1.c	2020-04-03 19:34:37.000000000 +0000
@@ -0,0 +1,52 @@
+// Derived from test case from the memory model study group of SC22 WG14
+// For this test, behaviour is defined in the PNVI-ae-udi memory model.
+
+/*
+Original test copyright (c) 2012-2016 David Chisnall, Kayvan Memarian, and Peter Sewell.
+
+Permission to use, copy, modify, and/or distribute this software for
+any purpose with or without fee is hereby granted, provided that the
+above copyright notice and this permission notice appear in all
+copies.
+
+THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+PERFORMANCE OF THIS SOFTWARE.
+*/
+
+// Adapted for SDCC by Philipp Klaus Krause in 2020.
+
+#include 
+
+#include 
+
+int x=1;
+
+void
+testMM(void)
+{
+  int *p=&x, *q=&x;
+  // read low-order (little endian) representation byte of p 
+  unsigned char i = *(unsigned char*)&p;
+  // check the bottom two bits of an int* are not used#
+  if (_Alignof(int) >= 4 && (i & 3u) == 0u) {
+    // set the low-order bit of the byte
+    i = i | 1u;  
+    // write the representation byte back
+    *(unsigned char*)&p = i; 
+    // [p might be passed around or copied here]
+    // clear the low-order bits again
+    *(unsigned char*)&p = (*(unsigned char*)&p) & ~((unsigned char)3u);
+    // are p and q now equivalent?  
+    *p = 11;          // does this have defined behaviour? 
+    _Bool b = (p==q); // is this true?
+    if (b)
+      ASSERT (x == *p);
+  }
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-provenance_tag_bits_via_uintptr_t_1.c sdcc-4.2.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-provenance_tag_bits_via_uintptr_t_1.c
--- sdcc-4.0.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-provenance_tag_bits_via_uintptr_t_1.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-provenance_tag_bits_via_uintptr_t_1.c	2020-04-03 19:34:37.000000000 +0000
@@ -0,0 +1,55 @@
+// Derived from test case from the memory model study group of SC22 WG14
+// For this test, behaviour is defined in the PNVI-ae-udi memory model.
+
+/*
+Original test copyright (c) 2012-2016 David Chisnall, Kayvan Memarian, and Peter Sewell.
+
+Permission to use, copy, modify, and/or distribute this software for
+any purpose with or without fee is hereby granted, provided that the
+above copyright notice and this permission notice appear in all
+copies.
+
+THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+PERFORMANCE OF THIS SOFTWARE.
+*/
+
+// Adapted for SDCC by Philipp Klaus Krause in 2020.
+
+#include 
+
+#pragma disable_warning 127
+
+#include 
+
+int x=1;
+
+void
+testMM(void)
+{
+  int *p = &x;
+  // cast &x to an integer 
+  uintptr_t i = (uintptr_t) p;
+  // check the bottom two bits of an int* are not used
+  if (_Alignof(int) >= 4 && (i & 3u) == 0u) {
+    // construct an integer like &x with low-order bit set
+    i = i | 1u;  
+    // cast back to a pointer
+    int *q = (int *) i; // does this have defined behaviour?
+    // cast to integer and mask out the low-order two bits
+    uintptr_t j = ((uintptr_t)q) & ~((uintptr_t)3u);  
+    // cast back to a pointer
+    int *r = (int *) j; 
+    // are r and p now equivalent?  
+    *r = 11;           //  does this have defined behaviour? 
+    _Bool b = (r==p);  //  is this true?
+    if (b)
+      ASSERT (*r == x);
+  }
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-provenance_union_punning_3_global.c sdcc-4.2.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-provenance_union_punning_3_global.c
--- sdcc-4.0.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-provenance_union_punning_3_global.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/mm-pnvi-ae-udi-provenance_union_punning_3_global.c	2020-04-03 19:34:37.000000000 +0000
@@ -0,0 +1,45 @@
+// Derived from test case from the memory model study group of SC22 WG14
+// For this test, behaviour is defined in the PNVI-ae-udi memory model.
+
+/*
+Original test copyright (c) 2012-2016 David Chisnall, Kayvan Memarian, and Peter Sewell.
+
+Permission to use, copy, modify, and/or distribute this software for
+any purpose with or without fee is hereby granted, provided that the
+above copyright notice and this permission notice appear in all
+copies.
+
+THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+PERFORMANCE OF THIS SOFTWARE.
+*/
+
+// Adapted for SDCC by Philipp Klaus Krause in 2020.
+
+#include 
+
+#pragma disable_warning 127
+
+#include 
+
+int x=1;
+typedef union { uintptr_t ui; int *up; } un;
+
+void
+testMM(void)
+{
+  un u; 
+  int *p = &x;
+  u.up = p;
+  uintptr_t i = u.ui;
+  int *q = (int*)i;
+  *q = 11;  // does this have UB?
+  ASSERT (x == *p);
+  ASSERT (x == *q);
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/p99-conformance.c sdcc-4.2.0+dfsg/support/regression/tests/p99-conformance.c
--- sdcc-4.0.0+dfsg/support/regression/tests/p99-conformance.c	2019-03-14 16:34:34.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/p99-conformance.c	2020-08-15 03:56:24.000000000 +0000
@@ -49,7 +49,6 @@
 #else /* SDCC issues */
 # define SKIP_HEXDOUBLE /* bug #2536 */
 # define SKIP_LONG_DOUBLE /* long double not yet supported */
-# define SKIP_UNIVERSAL
 # define SKIP_COMPOUND /* compound literals not yet supported */
 # define SKIP_VLA /* variable-length arrays not supported */
 # define SKIP_INLINE /* bug #1900 */
@@ -68,6 +67,11 @@
 #define SKIP_LONG_LONG
 #define SKIP_DIGRAPH
 #define SKIP_TRIGRAPH
+#define SKIP_UNIVERSAL
+#endif
+
+#if defined(__SDCC_mcs51) && defined(__SDCC_MODEL_SMALL) // Lack of memory
+#define SKIP_UNIVERSAL
 #endif
 
 #ifndef SKIP_VA_ARGS_MACRO
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/preserves_regs.c sdcc-4.2.0+dfsg/support/regression/tests/preserves_regs.c
--- sdcc-4.0.0+dfsg/support/regression/tests/preserves_regs.c	2019-06-30 10:33:24.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/preserves_regs.c	2020-09-28 10:06:29.000000000 +0000
@@ -4,7 +4,7 @@
 
 #include 
 
-#if defined(__SDCC_z80) || defined(__SDCC_z180) || defined(__SDCC_r2k) || defined(__SDCC_r3ka) || defined(__SDCC_tlcs90) || defined(__SDCC_ez80_z80)
+#if defined(__SDCC_z80) || defined(__SDCC_z180) || defined(__SDCC_r2k) || defined(__SDCC_r2ka) || defined(__SDCC_r3ka) || defined(__SDCC_tlcs90) || defined(__SDCC_ez80_z80)
 void write_bc(void) __preserves_regs(a, d, e, h, l, iyl, iyh) __naked
 {
 __asm
@@ -75,7 +75,7 @@
 
 void testRegs(void)
 {
-#if defined(__SDCC_z80) || defined(__SDCC_z180) || defined(__SDCC_r2k)|| defined(__SDCC_r3ka)
+#if defined(__SDCC_z80) || defined(__SDCC_z180) || defined(__SDCC_r2k) || defined(__SDCC_r2ka) || defined(__SDCC_r3ka) || defined(__SDCC_tlcs90) || defined(__SDCC_ez80_z80)
 	ASSERT(add_bc(0x55, 0xaa) == ({type})(0x55 + 0xaa));
 	ASSERT(add_de(0x55, 0xaa) == ({type})(0x55 + 0xaa));
 	ASSERT(add_hl(0x55, 0xaa) == ({type})(0x55 + 0xaa));
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/reentrant.c sdcc-4.2.0+dfsg/support/regression/tests/reentrant.c
--- sdcc-4.0.0+dfsg/support/regression/tests/reentrant.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/reentrant.c	2022-01-15 07:55:42.000000000 +0000
@@ -0,0 +1,51 @@
+/** reentrant.c
+
+  type: unsigned char, unsigned int, signed int, unsigned long, signed long, unsigned long long, signed long long, float
+*/
+
+#include 
+#include 
+
+#if !defined( __SDCC_pdk14) && !defined( __SDCC_pdk15) // Lack of memory
+#if !defined( __SDCC_ds390) // Bug 3307
+
+{type} sum({type} a) __reentrant
+{
+  if(a>1) return a+sum(a-1);
+  return 1;
+}
+
+{type} fact({type} a) __reentrant
+{
+  if(a>1) return a*fact(a-1);
+  return 1;
+}
+
+{type} div2n({type} a, int n) __reentrant
+{
+  if(n>0) return div2n(a/2,n-1);
+  return a;
+}
+
+{type} fib({type} a) __reentrant
+{
+  if(a>1) return fib(a-1)+fib(a-2);
+  return a;
+}
+
+#endif
+#endif
+
+void
+testReent(void)
+{
+#if !defined( __SDCC_pdk14) && !defined( __SDCC_pdk15) // Lack of memory
+#if !defined( __SDCC_ds390) // Bug 3307
+  ASSERT(sum(9) == 45);
+  ASSERT(fact(5) == 120);
+  ASSERT(div2n(128, 7) == 1);
+  ASSERT(fib(7) == 13);
+#endif
+#endif
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/rotate2.c sdcc-4.2.0+dfsg/support/regression/tests/rotate2.c
--- sdcc-4.0.0+dfsg/support/regression/tests/rotate2.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/rotate2.c	2021-06-22 04:49:19.000000000 +0000
@@ -0,0 +1,249 @@
+/** Tests covering RRC, RLC & SWAP operations
+
+    size: 8, 16, 32
+    andCase: 0, 1 , 2
+    xorLiteral: 0, 1
+    rotateLeft: 1, -1, 0
+    structVar: 0, 1
+    
+    size. 32
+    andCase. 0
+    xorLiteral. 1
+    rotateLeft. -1, 1, 0
+    structVar. 0, 1
+*/
+
+#include 
+#ifdef __sun__
+#include 
+#else
+#include 
+#endif
+
+#define SIZE ({size})
+#define AND_CASE ({andCase})
+#define XOR_LITERAL ({xorLiteral})
+#define ROTATE_LEFT ({rotateLeft})
+#define STRUCT_VAR ({structVar})
+
+#if SIZE == 8
+    #define TYPE uint8_t
+    #define TEST_VALUE 0x5B
+    #if AND_CASE == 2
+        #define AND_VALUE 0xFE
+    #elif AND_CASE == 1
+        #define AND_VALUE 0xEF
+    #else
+        #undef AND_VALUE
+    #endif
+#endif
+
+#if SIZE == 16
+    #define TYPE uint16_t
+    #define TEST_VALUE 0x3579
+    #if AND_CASE == 2
+        #define AND_VALUE 0xFEFF
+    #elif AND_CASE == 1
+        #define AND_VALUE 0xFFEF
+    #else
+        #undef AND_VALUE
+    #endif
+#endif
+
+#if SIZE == 32
+    #define TYPE uint32_t
+    #define TEST_VALUE 0x13579BDF
+    #if AND_CASE == 2
+        #define AND_VALUE 0xFEFFFEFF
+    #elif AND_CASE == 1
+        #define AND_VALUE 0xFFEFFFEF
+    #else
+        #undef AND_VALUE
+    #endif
+#endif
+
+#if ROTATE_LEFT == 1
+    #define SHIFT_R (SIZE - 1)
+    #define SHIFT_L 1
+    
+#elif ROTATE_LEFT == -1
+    #define SHIFT_R 1
+    #define SHIFT_L (SIZE - 1)
+#elif ROTATE_LEFT == 0
+    #define SHIFT_R (SIZE / 2)
+    #define SHIFT_L (SIZE / 2)
+#else
+    #error "UNKNOWN SHIFT CASE"
+#endif
+
+#ifdef AND_VALUE
+    #define AND_OPERATION & AND_VALUE
+#else
+    #define AND_OPERATION
+#endif
+
+#define XOR_VALUE 0x24
+
+#if XOR_LITERAL
+    #define rotate_test_value_xor XOR_VALUE
+#else
+    volatile TYPE rotate_test_value_xor = XOR_VALUE;
+#endif
+
+#define ROTATE_RESULT     ((TYPE)(((TEST_VALUE << SHIFT_L) | (TEST_VALUE >> SHIFT_R)) AND_OPERATION))
+#define ROTATE_RESULT_XOR ((TYPE)((((TEST_VALUE ^ XOR_VALUE) << SHIFT_L) | ((TEST_VALUE ^ XOR_VALUE) >> SHIFT_R)) AND_OPERATION))
+
+#if STRUCT_VAR
+  typedef struct
+  {
+    TYPE rotate_test_value1;
+    TYPE rotate_test_value2;
+  }rotate_test_struct_;
+  
+  rotate_test_struct_ rotate_test_struct;
+  #define rotate_test_value rotate_test_struct.rotate_test_value2
+#else
+  TYPE rotate_test_value;
+#endif
+
+TYPE rotate_test_1(TYPE value)
+{
+    return ((value << SHIFT_L) | (value >> SHIFT_R)) AND_OPERATION;
+}
+
+TYPE rotate_test_1_xor1(TYPE value)
+{
+    value = value ^ rotate_test_value_xor;
+    return ((value << SHIFT_L) | (value >> SHIFT_R)) AND_OPERATION;
+}
+
+TYPE rotate_test_1_xor2(TYPE value)
+{
+    return (((value ^ rotate_test_value_xor) << SHIFT_L) | ((value ^ rotate_test_value_xor) >> SHIFT_R)) AND_OPERATION;
+}
+
+#if !(defined(__SDCC_pdk14) || defined (__SDCC_pdk15) && defined(__SDCC_STACK_AUTO)) // Lack of memory
+
+TYPE rotate_test_2(TYPE value)
+{
+    TYPE value2 = value;
+    return ((value2 << SHIFT_L) | (value2 >> SHIFT_R)) AND_OPERATION;
+}
+
+TYPE rotate_test_2_xor1(TYPE value)
+{
+    TYPE value2 = value ^ rotate_test_value_xor;
+    return ((value2 << SHIFT_L) | (value2 >> SHIFT_R)) AND_OPERATION;
+}
+
+TYPE rotate_test_2_xor2(TYPE value)
+{
+    TYPE value2 = value;
+    return (((value2 ^ rotate_test_value_xor) << SHIFT_L) | ((value2 ^ rotate_test_value_xor) >> SHIFT_R)) AND_OPERATION;
+}
+
+TYPE rotate_test_3(TYPE value)
+{
+    volatile TYPE value2 = value;
+    value2 = ((value2 << SHIFT_L) | (value2 >> SHIFT_R)) AND_OPERATION;
+    return value2;
+}
+
+TYPE rotate_test_3_xor1(TYPE value)
+{
+    volatile TYPE value2 = value ^ rotate_test_value_xor;
+    value2 = ((value2 << SHIFT_L) | (value2 >> SHIFT_R)) AND_OPERATION;
+    return value2;
+}
+
+TYPE rotate_test_3_xor2(TYPE value)
+{
+    volatile TYPE value2 = value;
+    value2 = (((value2 ^ rotate_test_value_xor) << SHIFT_L) | ((value2 ^ rotate_test_value_xor) >> SHIFT_R)) AND_OPERATION;
+    return value2;
+}
+
+#ifndef __SDCC_pdk15 // Lack of memory
+
+TYPE rotate_test_4(TYPE value)
+{
+    rotate_test_value = value;
+    rotate_test_value = ((rotate_test_value << SHIFT_L) | (rotate_test_value >> SHIFT_R)) AND_OPERATION;
+    return rotate_test_value;
+}
+
+TYPE rotate_test_4_xor1(TYPE value)
+{
+    rotate_test_value = value ^ rotate_test_value_xor;
+    rotate_test_value = ((rotate_test_value << SHIFT_L) | (rotate_test_value >> SHIFT_R)) AND_OPERATION;
+    return rotate_test_value;
+}
+
+TYPE rotate_test_4_xor2(TYPE value)
+{
+    rotate_test_value = value;
+    rotate_test_value = (((rotate_test_value ^ rotate_test_value_xor) << SHIFT_L) | ((rotate_test_value ^ rotate_test_value_xor) >> SHIFT_R)) AND_OPERATION;
+    return rotate_test_value;
+}
+
+rotate_test_load(TYPE value)
+{
+    rotate_test_value = value;
+}
+
+TYPE rotate_test_5(TYPE value)
+{
+    rotate_test_load (value);
+    rotate_test_value = ((rotate_test_value << SHIFT_L) | (rotate_test_value >> SHIFT_R)) AND_OPERATION;
+    return rotate_test_value;
+}
+
+TYPE rotate_test_5_xor1(TYPE value)
+{
+    rotate_test_load (value ^ rotate_test_value_xor);
+    rotate_test_value = ((rotate_test_value << SHIFT_L) | (rotate_test_value >> SHIFT_R)) AND_OPERATION;
+    return rotate_test_value;
+}
+
+TYPE rotate_test_5_xor2(TYPE value)
+{
+    rotate_test_load (value);
+    rotate_test_value = (((rotate_test_value ^ rotate_test_value_xor) << SHIFT_L) | ((rotate_test_value ^ rotate_test_value_xor) >> SHIFT_R)) AND_OPERATION;
+    return rotate_test_value;
+}
+#endif
+#endif
+
+static void
+testSwaps(void)
+{
+#if !(defined(__SDCC_pdk14) || defined (__SDCC_pdk15) && defined(__SDCC_STACK_AUTO)) // Lack of memory
+    volatile TYPE t = TEST_VALUE;
+    TYPE u;
+    
+    u = t;
+
+    ASSERT( rotate_test_1(u)      == ROTATE_RESULT);
+    ASSERT( rotate_test_1_xor1(u) == ROTATE_RESULT_XOR);
+    ASSERT( rotate_test_1_xor2(u) == ROTATE_RESULT_XOR);
+
+    ASSERT( rotate_test_2(u)      == ROTATE_RESULT);
+    ASSERT( rotate_test_2_xor1(u) == ROTATE_RESULT_XOR);
+    ASSERT( rotate_test_2_xor2(u) == ROTATE_RESULT_XOR);
+
+    ASSERT( rotate_test_3(u)      == ROTATE_RESULT);
+    ASSERT( rotate_test_3_xor1(u) == ROTATE_RESULT_XOR);
+    ASSERT( rotate_test_3_xor2(u) == ROTATE_RESULT_XOR);
+
+#ifndef __SDCC_pdk15 // Lack of memory
+    ASSERT( rotate_test_4(u)      == ROTATE_RESULT);
+    ASSERT( rotate_test_4_xor1(u) == ROTATE_RESULT_XOR);
+    ASSERT( rotate_test_4_xor2(u) == ROTATE_RESULT_XOR);
+
+    ASSERT( rotate_test_5(u)      == ROTATE_RESULT);
+    ASSERT( rotate_test_5_xor1(u) == ROTATE_RESULT_XOR);
+    ASSERT( rotate_test_5_xor2(u) == ROTATE_RESULT_XOR);
+#endif
+#endif
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/sdcccall.c sdcc-4.2.0+dfsg/support/regression/tests/sdcccall.c
--- sdcc-4.0.0+dfsg/support/regression/tests/sdcccall.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/sdcccall.c	2021-12-10 14:48:15.000000000 +0000
@@ -0,0 +1,50 @@
+/*
+   sdcccall.c. Test support for differnrt ABI versions.
+   typearg: unsigned char, unsigned int
+   typeret: unsigned char, unsigned int
+   version: 0, 1
+ */
+
+#include 
+
+#if (defined(__SDCC_stm8) || defined(__SDCC_sm83) || defined(__SDCC_z80) || defined(__SDCC_z80n) || defined(__SDCC_z180))
+#define SDCCCALL __sdcccall({version})
+#else
+#define SDCCCALL
+#endif
+
+{typeret} f({typearg} i) SDCCCALL
+{
+	return ++i;
+}
+
+{typeret} g({typearg} i, unsigned int j) SDCCCALL
+{
+	return i + j;
+}
+
+{typeret} h({typearg} i, unsigned int j, unsigned long long k) SDCCCALL
+{
+	return i + j + k;
+}
+
+{typeret} f_wrap_default({typearg} i)
+{
+	return f(i);
+}
+
+{typeret} f_wrap_explicit({typearg} i) SDCCCALL
+{
+	return f(i);
+}
+
+void
+testCallingConvention(void)
+{
+  ASSERT(f(23) == ({typeret})24);
+  ASSERT(g(23, 1001u) == ({typeret})1024ul);
+  ASSERT(h(23, 1001u, 10000000000ul) == ({typeret})10000001024ull);
+  ASSERT(f_wrap_default(23) == ({typeret})24);
+  ASSERT(f_wrap_explicit(23) == ({typeret})24);
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/setjmp.c sdcc-4.2.0+dfsg/support/regression/tests/setjmp.c
--- sdcc-4.0.0+dfsg/support/regression/tests/setjmp.c	2019-10-14 11:33:28.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/setjmp.c	2021-04-22 08:33:00.000000000 +0000
@@ -47,6 +47,11 @@
 
 #endif
 
+// Get FreeBSD version to skip part of test for known broken setjmp (FreeBSD bug #255320).
+#ifdef __FreeBSD__
+#include 
+#endif
+
 void
 testJmp (void)
 {
@@ -70,9 +75,11 @@
       ASSERT (0);
     }
   ASSERT (exception == 1);
-
+  
+#if !defined(__FreeBSD__) || __FreeBSD_version > 1300139
   f1();
 #endif
+#endif
 
 // C99 might require setjmp to be a macro. The standard seems self-contradicting on this issue.
 //#ifndef setjmp
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/shifts2.c sdcc-4.2.0+dfsg/support/regression/tests/shifts2.c
--- sdcc-4.0.0+dfsg/support/regression/tests/shifts2.c	2019-09-24 20:05:59.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/shifts2.c	2020-11-02 12:26:17.000000000 +0000
@@ -5,6 +5,7 @@
     right: 0,1
     vol: 0,1
     sign: u,
+    goal: 0, 1, 2
 */
 #include 
 #ifdef __sun__
@@ -16,6 +17,7 @@
 #define SIZE    ({size})
 #define RIGHT   ({right})
 #define VOL     ({vol})
+#define GOAL    ({goal})
 
 #if SIZE == 8
 #  define TYPE {sign}int8_t
@@ -38,6 +40,12 @@
 #  define SHIFT(x,y) (TYPE)((TYPE)(x)>>(y))
 #endif
 
+#if GOAL == 1
+#pragma opt_code_size
+#elif GOAL == 2
+#pragma opt_code_speed
+#endif
+
 #if VOL == 0
   volatile TYPE s = TEST_VECT;
            TYPE t;
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/sizeof.c sdcc-4.2.0+dfsg/support/regression/tests/sizeof.c
--- sdcc-4.0.0+dfsg/support/regression/tests/sizeof.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/sizeof.c	2021-07-16 01:16:00.000000000 +0000
@@ -0,0 +1,382 @@
+/** Test results of sizeof operator for unusual cases
+    size: 1, 8, 16
+    test : 0, 1, 2, 3, 4, 5
+    vol : 0, 1
+*/
+
+#include 
+#ifdef __sun__
+#include 
+#else
+#include 
+#endif
+#include 
+#include 
+
+#define VAR_SIZE ({size})
+#define TEST ({test})
+#define TEST_VOLATILE ({vol})
+
+// Test is split in several parts to be smaller and for debugging purposes
+#if TEST == 0
+  #define TEST_BASIC
+  #define TEST_ASSING
+  #define TEST_POINTERS
+#elif TEST == 1
+  #define TEST_LITERAL
+  #if VAR_SIZE != 1
+    #define DUMMY_TEST
+  #endif
+#elif TEST == 2
+  #define TEST_VARIABLE
+#elif TEST == 3
+  #define TEST_LITERAL_BOOL_OP
+  #if VAR_SIZE != 1
+    #define DUMMY_TEST
+  #endif
+#elif TEST == 4
+  #define TEST_VARIABLE_BOOL_OP
+#elif TEST == 5
+  #define TEST_VARIABLE_ZERO_RESULT
+#else
+  #error "Unknown test"
+#endif
+
+#if TEST_VOLATILE == 1
+  #define VAR_QUALIFIER volatile
+#else
+  #define VAR_QUALIFIER
+#endif
+
+// Variables for the test.
+typedef struct structBitFields
+{
+  #if VAR_SIZE == 1
+    unsigned int bitField : 1;
+    unsigned int dummy : 7;
+  #elif VAR_SIZE == 8
+    unsigned int bitField : 7;
+    unsigned int dummy : 1;
+  #else
+    unsigned int bitField : 15;
+    unsigned int dummy : 1;
+  #endif
+}
+structBitFields;
+
+VAR_QUALIFIER structBitFields bf;
+
+VAR_QUALIFIER bool b, bt;
+VAR_QUALIFIER uint8_t c, c2, ct;
+VAR_QUALIFIER int16_t i, i2, it;
+
+VAR_QUALIFIER bool    * VAR_QUALIFIER  pb;
+VAR_QUALIFIER uint8_t * VAR_QUALIFIER  pc;
+VAR_QUALIFIER int16_t * VAR_QUALIFIER  pi;
+
+
+// Main test macro, assigns the sizeof expression to the result and checks if result is correct.
+#if defined (__SDCC_pdk13) || defined (__SDCC_pdk14) || defined (__SDCC_pdk15)
+  // Keep the assignment out of the assert, same result, but less memory required by assert strings (worse for debugging).
+  #define DO_TEST(expression, result, type) result = sizeof (expression); ASSERT(sizeof(type)==result)
+#else
+  #define DO_TEST(expression, result, type) ASSERT((result = sizeof (expression), sizeof (type) == result))
+#endif
+
+// Prepare macros depending on variable size to test.
+#if VAR_SIZE == 1
+  #define VAR_TYPE            bool
+  #define TEST_VAR            b
+  #define TEST_VAR2           bt
+  #define TEST_PTR_VAR        pb
+  #define TEST_VAR_OTHER      i
+
+  #define TEST_OP(x)          DO_TEST(x, c2, int) //Test with promotion, int type expected.
+#elif VAR_SIZE == 8
+  #define VAR_TYPE            uint8_t
+  #define TEST_VAR            c
+  #define TEST_VAR2           ct
+  #define TEST_PTR_VAR        pc
+  #define TEST_VAR_OTHER      i
+
+  #define TEST_OP(x)          DO_TEST(x, c2, int) //Test with promotion, int type expected.
+#elif VAR_SIZE == 16
+  #define VAR_TYPE            int16_t
+  #define TEST_VAR            i
+  #define TEST_VAR2           it
+  #define TEST_PTR_VAR        pi
+  #define TEST_VAR_OTHER      c
+
+  #define TEST_OP(x)          DO_TEST(x, i2, int) //Test with promotion, int type expected.
+#else
+  #error "Unknown test size"
+#endif
+
+#define TEST_OP_NOPROMO(x)  DO_TEST(x, c2, VAR_TYPE)    // Test without promotion, same type expected.
+#define TEST_OP_CHAR_PTR(x) DO_TEST(x, c2, VAR_TYPE *)  // Test for pointers, pointer of type expected.
+#define TEST_OP_INT_PTR(x)  DO_TEST(x, i2, VAR_TYPE *)  // Same using integer for the result.
+
+#define TEST_OP_CHAR_PTR_DIFF(x) DO_TEST(x, c2, ptrdiff_t)  // Test for pointers, ptrdiff_t type expected.
+#define TEST_OP_INT_PTR_DIFF(x)  DO_TEST(x, i2, ptrdiff_t)  // Same using integer for the result.
+
+// Check default address space to check the size of the default pointer size correctly
+#if defined (__SDCC_pdk13) || defined (__SDCC_pdk14) || defined (__SDCC_pdk15) || defined (__SDCC_mcs51) || defined (__SDCC_ds390)
+  #if defined (__SDCC_mcs51)
+    #if defined (__SDCC_MODEL_SMALL) || (__SDCC_MODEL_MEDIUM)
+      #define DEFAULT_ADDR_SPACE __near
+    #elif defined (__SDCC_MODEL_LARGE)  || (__SDCC_MODEL_HUGE)
+      #define DEFAULT_ADDR_SPACE __far
+    #endif
+  #elif defined(__SDCC_ds390)
+    #define DEFAULT_ADDR_SPACE __far
+  #else
+    #define DEFAULT_ADDR_SPACE __data // pdk
+  #endif
+#endif
+
+#ifdef DEFAULT_ADDR_SPACE // Tests for backends that need the default address space qualifier
+  #define TEST_OP_CHAR_PTR_DAS(x) DO_TEST(x, c2, VAR_TYPE DEFAULT_ADDR_SPACE *) // Test for pointers, pointer of type default address space expected.
+  #define TEST_OP_INT_PTR_DAS(x)  DO_TEST(x, i2, VAR_TYPE DEFAULT_ADDR_SPACE *) // Same using integer for the result
+#else
+  #define TEST_OP_CHAR_PTR_DAS TEST_OP_CHAR_PTR
+  #define TEST_OP_INT_PTR_DAS  TEST_OP_INT_PTR
+#endif
+
+
+static void
+testSizeof(void)
+{
+#ifndef DUMMY_TEST
+
+#ifdef TEST_BASIC // Macro self test
+  TEST_OP_NOPROMO (VAR_TYPE);
+  TEST_OP_CHAR_PTR (VAR_TYPE *);
+  TEST_OP_INT_PTR (VAR_TYPE *);
+  #ifdef DEFAULT_ADDR_SPACE
+    TEST_OP_CHAR_PTR_DAS (VAR_TYPE DEFAULT_ADDR_SPACE *);
+    TEST_OP_INT_PTR_DAS (VAR_TYPE DEFAULT_ADDR_SPACE *);
+  #endif
+#endif
+
+#ifdef TEST_ASSING
+  TEST_OP_NOPROMO (TEST_VAR = 1);
+  TEST_OP_NOPROMO (TEST_VAR = 1 + 1);
+
+  TEST_OP_NOPROMO (TEST_VAR += 1);
+  TEST_OP_NOPROMO (TEST_VAR -= 1);
+  TEST_OP_NOPROMO (TEST_VAR &= 1);
+  TEST_OP_NOPROMO (TEST_VAR |= 1);
+  TEST_OP_NOPROMO (TEST_VAR ^= 1);
+  TEST_OP_NOPROMO (TEST_VAR *= 5);
+  TEST_OP_NOPROMO (TEST_VAR /= 5);
+  TEST_OP_NOPROMO (TEST_VAR /= 2);
+
+  TEST_OP_NOPROMO (TEST_VAR <<= 2);
+  TEST_OP_NOPROMO (TEST_VAR >>= 2);
+
+  TEST_OP_NOPROMO ((TEST_VAR_OTHER++, TEST_VAR += 1));
+#endif
+
+#ifdef TEST_POINTERS
+
+  TEST_OP_CHAR_PTR(VAR_TYPE *);
+  TEST_OP_INT_PTR (VAR_TYPE *);
+
+  TEST_OP (+(*TEST_PTR_VAR));
+  TEST_OP (-(*TEST_PTR_VAR));
+  TEST_OP (~(*TEST_PTR_VAR));
+
+  TEST_OP_CHAR_PTR(TEST_PTR_VAR);
+  TEST_OP_INT_PTR (TEST_PTR_VAR);
+
+  TEST_OP_CHAR_PTR(TEST_PTR_VAR + 1);
+  TEST_OP_INT_PTR (TEST_PTR_VAR + 1);
+
+  TEST_OP_CHAR_PTR(TEST_PTR_VAR - 1);
+  TEST_OP_INT_PTR (TEST_PTR_VAR - 1);
+
+  TEST_OP_CHAR_PTR(TEST_PTR_VAR++);
+  TEST_OP_INT_PTR (TEST_PTR_VAR--);
+
+  TEST_OP_CHAR_PTR(TEST_PTR_VAR += 1);
+  TEST_OP_INT_PTR (TEST_PTR_VAR -= 1);
+
+  TEST_OP_CHAR_PTR(TEST_PTR_VAR = 1);
+  TEST_OP_INT_PTR (TEST_PTR_VAR = 1);
+
+  TEST_OP_CHAR_PTR_DAS(&TEST_VAR);
+  TEST_OP_INT_PTR_DAS (&TEST_VAR);
+
+  TEST_OP_CHAR_PTR_DAS(&TEST_VAR + 1);
+  TEST_OP_INT_PTR_DAS (&TEST_VAR + 1);
+  TEST_OP_CHAR_PTR_DAS(&TEST_VAR - 1);
+  TEST_OP_INT_PTR_DAS (&TEST_VAR - 1);
+#endif
+
+#ifdef TEST_LITERAL
+  TEST_OP ( 8);
+  TEST_OP (+8);
+  TEST_OP (-8);
+  TEST_OP (~0);
+
+  TEST_OP (1 ? 0 : 0);
+  TEST_OP (0 ? 0 : 0);
+  TEST_OP (1 ? 0 : 1);
+  TEST_OP (0 ? 0 : 1);
+  TEST_OP (1 ? 1 : 0);
+  TEST_OP (0 ? 1 : 0);
+  TEST_OP (1 ? 1 : 1);
+  TEST_OP (0 ? 1 : 1);
+
+  TEST_OP (8 << 1);
+  TEST_OP (8 >> 1);
+  TEST_OP (8 & 8);
+  TEST_OP (8 | 8);
+  TEST_OP (8 ^ 8);
+  TEST_OP (8 + 8);
+  TEST_OP (8 - 8);
+  TEST_OP (8 * 8);
+  TEST_OP (8 / 8);
+  TEST_OP (8 % 2);
+#endif
+
+#ifdef TEST_LITERAL_BOOL_OP
+  TEST_OP (!8);
+  TEST_OP (!0);
+
+  TEST_OP (8 > 1);
+  TEST_OP (8 < 1);
+  TEST_OP (8 >= 1);
+  TEST_OP (8 <= 1);
+  TEST_OP (8 == 1);
+  TEST_OP (8 != 1);
+
+  TEST_OP (1 > 8);
+  TEST_OP (1 < 8);
+  TEST_OP (1 >= 8);
+  TEST_OP (1 <= 8);
+  TEST_OP (1 == 8);
+  TEST_OP (1 != 8);
+
+
+  TEST_OP (1 && 1);
+  TEST_OP (1 && 0);
+  TEST_OP (0 && 0);
+
+  TEST_OP (1 || 1);
+  TEST_OP (1 || 0);
+  TEST_OP (0 || 0);
+#endif
+
+#ifdef TEST_VARIABLE_ZERO_RESULT
+  #if VAR_SIZE == 1 // Do test only once
+    TEST_OP ((1>0) - (1>0));
+  #endif
+
+  TEST_OP (TEST_VAR - TEST_VAR);
+  TEST_OP (*TEST_PTR_VAR - *TEST_PTR_VAR);
+  TEST_OP (bf.bitField - bf.bitField);
+
+  #ifdef __SDCC
+    // Do these tests only for SDCC, behavior is undefined by standard.
+    // SDCC implementation defines the result as 0. 
+    // Type of that value should follow standard promotion for shift.
+    TEST_OP (TEST_VAR >> 32);
+    TEST_OP (TEST_VAR >> -1);
+  #endif
+
+  TEST_OP_CHAR_PTR_DIFF(TEST_PTR_VAR - TEST_PTR_VAR);
+  TEST_OP_INT_PTR_DIFF (TEST_PTR_VAR - TEST_PTR_VAR);
+#endif
+
+#ifdef TEST_VARIABLE
+  TEST_OP_NOPROMO (TEST_VAR);
+  TEST_OP (+TEST_VAR);
+  TEST_OP (-TEST_VAR);
+  TEST_OP (~TEST_VAR);
+
+  TEST_OP_NOPROMO (TEST_VAR++);
+  TEST_OP_NOPROMO (TEST_VAR--);
+
+  TEST_OP_NOPROMO (++TEST_VAR);
+  TEST_OP_NOPROMO (--TEST_VAR);
+
+  TEST_OP (TEST_VAR ? 0 : 0);
+  TEST_OP (TEST_VAR ? 0 : 1);
+  TEST_OP (TEST_VAR ? 1 : 0);
+  TEST_OP (TEST_VAR ? 1 : 1);
+  TEST_OP (1 ? TEST_VAR : 1);
+  TEST_OP (1 ? TEST_VAR : 1);
+  TEST_OP (1 ? 1 : TEST_VAR);
+  TEST_OP (1 ? 1 : TEST_VAR);
+  TEST_OP (0 ? TEST_VAR : 1);
+  TEST_OP (0 ? TEST_VAR : 1);
+  TEST_OP (0 ? 1 : TEST_VAR);
+  TEST_OP (0 ? 1 : TEST_VAR);
+
+  TEST_OP (TEST_VAR << 1);
+  TEST_OP (TEST_VAR << (2 + 1));
+  TEST_OP (TEST_VAR << (2 << 1));
+
+  TEST_OP (TEST_VAR >> 1);
+  TEST_OP (TEST_VAR >> (2 + 1));
+  TEST_OP (TEST_VAR >> (2 << 1));
+
+  TEST_OP (TEST_VAR & 8);
+  TEST_OP (TEST_VAR & (2 + 1));
+  TEST_OP (TEST_VAR & (2 << 1));
+
+  TEST_OP (TEST_VAR | 8);
+  TEST_OP (TEST_VAR | (2 + 1));
+  TEST_OP (TEST_VAR | (2 << 1));
+
+  TEST_OP (TEST_VAR ^ 8);
+  TEST_OP (TEST_VAR ^ (2 + 1));
+  TEST_OP (TEST_VAR ^ (2 << 1));
+
+  TEST_OP (TEST_VAR + 8);
+  TEST_OP (TEST_VAR + (2 + 1));
+  TEST_OP (TEST_VAR + (2 << 1));
+
+  TEST_OP (TEST_VAR - 8);
+  TEST_OP (TEST_VAR - (2 + 1));
+  TEST_OP (TEST_VAR - (2 << 1));
+
+  TEST_OP (TEST_VAR * 8);
+  TEST_OP (TEST_VAR * (2 + 1));
+  TEST_OP (TEST_VAR * (2 << 1));
+
+  TEST_OP (TEST_VAR - TEST_VAR2);
+  #if VAR_SIZE == 8
+    TEST_OP ((TEST_VAR >> 1) | (TEST_VAR << 7));
+  #endif
+#endif
+
+#ifdef TEST_VARIABLE_BOOL_OP
+  TEST_OP (!TEST_VAR);
+
+  TEST_OP (TEST_VAR > 0);
+  TEST_OP (TEST_VAR < 0);
+  TEST_OP (TEST_VAR >= 1);
+  TEST_OP (TEST_VAR <= 1);
+  TEST_OP (TEST_VAR == 1);
+  TEST_OP (TEST_VAR != 1);
+
+  TEST_OP (1 > c);
+  TEST_OP (1 < c);
+  TEST_OP (1 >= c);
+  TEST_OP (1 <= c);
+  TEST_OP (1 == c);
+  TEST_OP (1 != c);
+
+  TEST_OP (c && c);
+  TEST_OP (c && 0);
+  TEST_OP (0 && c);
+  TEST_OP (c || c);
+  TEST_OP (c || 0);
+  TEST_OP (0 || c);
+#endif
+
+#endif //DUMMY_TEST
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/smallc.c sdcc-4.2.0+dfsg/support/regression/tests/smallc.c
--- sdcc-4.0.0+dfsg/support/regression/tests/smallc.c	2018-09-14 13:31:29.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/smallc.c	2020-09-28 10:06:29.000000000 +0000
@@ -6,10 +6,6 @@
 #include 
 #include 
 
-#if !(defined __SDCC_z80 || defined __SDCC_z180 || defined __SDCC_gbz80 || defined __SDCC_r2k || defined __SDCC_r3ka || defined __SDCC_tlcs90)
-#define __smallc
-#endif
-
 unsigned char f1(unsigned char c) __smallc
 {
 	return c + 1;
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/stack-restore.c sdcc-4.2.0+dfsg/support/regression/tests/stack-restore.c
--- sdcc-4.0.0+dfsg/support/regression/tests/stack-restore.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/stack-restore.c	2021-04-07 12:39:18.000000000 +0000
@@ -0,0 +1,81 @@
+/** Check stack restore optimizations for STM8.
+    Should work ok for all other ports as long as enough memory is available for the tests.
+    Check with all levels of optimization (speed, size and balanced).
+    
+    optSize: -1, 0, 1
+*/
+
+#include 
+#ifdef __sun__
+#include 
+#else
+#include 
+#endif
+
+#define OPT_SIZE ({optSize})
+
+#if OPT_SIZE == -1
+    #pragma opt_code_speed
+#elif OPT_SIZE == 1
+    #pragma opt_code_size
+#else
+    #pragma opt_code_balanced
+#endif
+
+
+// Test for size = 1 byte
+// It must assing global variable from input param and return 0
+// The case for STM8 can be triggered by a local array of size 1 or a local volatile
+static volatile char globalValue;
+uint8_t 
+stack_restore_test_byte(const char s)
+{
+    char a[1];
+    a[0] = s;
+    globalValue = a[0];
+    //volatile char dummy;
+    //dummy = s;
+    //globalValue = s;
+    return 0;
+}
+
+#if !defined(__SDCC_mcs51) && !defined(__SDCC_pdk14) && !defined(__SDCC_pdk15) && !defined(__SDCC_pic14) // Lack of memory
+    // Test for size = 2 bytes
+    // Big stack needed (>256 bytes)
+    // Should assert ok 256 times
+    // Returns number of cases ok for double check
+    #define stack_restore_test_word test_stack_restore_word
+    
+    uint16_t 
+    stack_restore_test_word(void)
+    {
+        uint16_t x[256];
+        int i;
+        uint16_t casesOk = 0;
+        
+        for (i = 0; i < 256; i++)
+        {
+            x[i] = i;
+        }
+        for (i = 0; i < 256; i++)
+        {
+            ASSERT (x[i] == i);
+            casesOk += x[i] == i;
+        }
+        return casesOk;
+    }
+#endif
+
+
+static void
+testStackRestore(void)
+{   
+    globalValue = 0;
+    ASSERT(stack_restore_test_byte(0x5C) == 0);
+    ASSERT(globalValue == 0x5C);
+    
+    #ifdef stack_restore_test_word
+        ASSERT(stack_restore_test_word() == 256);
+    #endif
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/stm8-conventions.c sdcc-4.2.0+dfsg/support/regression/tests/stm8-conventions.c
--- sdcc-4.0.0+dfsg/support/regression/tests/stm8-conventions.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/stm8-conventions.c	2021-06-16 10:52:04.000000000 +0000
@@ -0,0 +1,48 @@
+/*
+   stm8-conventions.c. Test support for calling convetions of other STM8-compilers.
+   typearg: unsigned char, unsigned int
+   typeret: unsigned char, unsigned int
+   convention: , __raisonance, __iar, __cosmic
+ */
+
+#include 
+
+#ifdef __SDCC_stm8
+{typeret} f({typearg} i) {convention}
+{
+	return ++i;
+}
+
+{typeret} g({typearg} i, unsigned int j) {convention}
+{
+	return i + j;
+}
+
+{typeret} h({typearg} i, unsigned int j, unsigned long long k) {convention}
+{
+	return i + j + k;
+}
+
+{typeret} f_wrap_sdcc({typearg} i)
+{
+	return f(i);
+}
+
+{typeret} f_wrap_{convention}({typearg} i) {convention}
+{
+	return f(i);
+}
+#endif
+
+void
+testCallingConvention(void)
+{
+#ifdef __SDCC_stm8
+  ASSERT(f(23) == ({typeret})24);
+  ASSERT(g(23, 1001u) == ({typeret})1024ul);
+  ASSERT(h(23, 1001u, 10000000000ul) == ({typeret})10000001024ull);
+  ASSERT(f_wrap_sdcc(23) == ({typeret})24);
+  ASSERT(f_wrap_{convention}(23) == ({typeret})24);
+#endif
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/swap_add.c sdcc-4.2.0+dfsg/support/regression/tests/swap_add.c
--- sdcc-4.0.0+dfsg/support/regression/tests/swap_add.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/swap_add.c	2021-04-07 12:39:18.000000000 +0000
@@ -0,0 +1,40 @@
+/** Swap test using 'addition' instead of usual 'or'
+*/
+
+#include 
+#ifdef __sun__
+#include 
+#else
+#include 
+#endif
+
+uint8_t 
+swap_add_8(uint8_t value)
+{
+    value = (value << 4) + (value >> 4);
+    return value;
+}
+
+#define SWAP_ADD_8(value) (((value << 4) & 0xF0u) | ((value >> 4) & 0x0Fu))
+#define SWAP_ADD_8_EQUALS(value) (swap_add_8(value) == SWAP_ADD_8(value))
+static void
+testSwapAdd(void)
+{
+#ifndef __SDCC_pdk15 // Bug
+    ASSERT(SWAP_ADD_8_EQUALS(0x01));
+    ASSERT(SWAP_ADD_8_EQUALS(0x02));
+    ASSERT(SWAP_ADD_8_EQUALS(0x04));
+    ASSERT(SWAP_ADD_8_EQUALS(0x08));
+    
+    ASSERT(SWAP_ADD_8_EQUALS(0x10));
+    ASSERT(SWAP_ADD_8_EQUALS(0x20));
+    ASSERT(SWAP_ADD_8_EQUALS(0x40));
+    ASSERT(SWAP_ADD_8_EQUALS(0x80));
+    
+    ASSERT(SWAP_ADD_8_EQUALS(0x0F));
+    ASSERT(SWAP_ADD_8_EQUALS(0xF0));
+    ASSERT(SWAP_ADD_8_EQUALS(0x3C));
+    ASSERT(SWAP_ADD_8_EQUALS(0xC3));
+#endif
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/tinyaes.c sdcc-4.2.0+dfsg/support/regression/tests/tinyaes.c
--- sdcc-4.0.0+dfsg/support/regression/tests/tinyaes.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/tinyaes.c	2021-11-09 16:10:05.000000000 +0000
@@ -0,0 +1,834 @@
+/*
+   tinyaes.c
+   mode: CBC, ECB, CTR
+   keylen: 128, 192, 256
+   AES cipher
+
+   Test uses the implementation from tinyaes.
+*/
+
+#include 
+
+#if !defined(__SDCC_pdk13) && !defined(__SDCC_pdk14) && !defined(__SDCC_pdk15) && !defined(__SDCC_mcs51) // Lack of memory
+#define {mode} 1
+#define AES{keylen} 1
+
+/*
+This is free and unencumbered software released into the public domain.
+
+Anyone is free to copy, modify, publish, use, compile, sell, or
+distribute this software, either in source code form or as a compiled
+binary, for any purpose, commercial or non-commercial, and by any
+means.
+
+In jurisdictions that recognize copyright laws, the author or authors
+of this software dedicate any and all copyright interest in the
+software to the public domain. We make this dedication for the benefit
+of the public at large and to the detriment of our heirs and
+successors. We intend this dedication to be an overt act of
+relinquishment in perpetuity of all present and future rights to this
+software under copyright law.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+OTHER DEALINGS IN THE SOFTWARE.
+
+For more information, please refer to 
+*/
+
+#include 
+#include 
+
+#define AES_BLOCKLEN 16 // Block length in bytes - AES is 128b block only
+
+#if defined(AES256) && (AES256 == 1)
+    #define AES_KEYLEN 32
+    #define AES_keyExpSize 240
+#elif defined(AES192) && (AES192 == 1)
+    #define AES_KEYLEN 24
+    #define AES_keyExpSize 208
+#else
+    #define AES_KEYLEN 16   // Key length in bytes
+    #define AES_keyExpSize 176
+#endif
+
+struct AES_ctx
+{
+  uint8_t RoundKey[AES_keyExpSize];
+#if (defined(CBC) && (CBC == 1)) || (defined(CTR) && (CTR == 1))
+  uint8_t Iv[AES_BLOCKLEN];
+#endif
+};
+
+void AES_init_ctx(struct AES_ctx* ctx, const uint8_t* key);
+#if (defined(CBC) && (CBC == 1)) || (defined(CTR) && (CTR == 1))
+void AES_init_ctx_iv(struct AES_ctx* ctx, const uint8_t* key, const uint8_t* iv);
+void AES_ctx_set_iv(struct AES_ctx* ctx, const uint8_t* iv);
+#endif
+
+#if defined(ECB) && (ECB == 1)
+// buffer size is exactly AES_BLOCKLEN bytes; 
+// you need only AES_init_ctx as IV is not used in ECB 
+// NB: ECB is considered insecure for most uses
+void AES_ECB_encrypt(const struct AES_ctx* ctx, uint8_t* buf);
+void AES_ECB_decrypt(const struct AES_ctx* ctx, uint8_t* buf);
+
+#endif // #if defined(ECB) && (ECB == !)
+
+
+#if defined(CBC) && (CBC == 1)
+// buffer size MUST be mutile of AES_BLOCKLEN;
+// Suggest https://en.wikipedia.org/wiki/Padding_(cryptography)#PKCS7 for padding scheme
+// NOTES: you need to set IV in ctx via AES_init_ctx_iv() or AES_ctx_set_iv()
+//        no IV should ever be reused with the same key 
+void AES_CBC_encrypt_buffer(struct AES_ctx* ctx, uint8_t* buf, size_t length);
+void AES_CBC_decrypt_buffer(struct AES_ctx* ctx, uint8_t* buf, size_t length);
+
+#endif // #if defined(CBC) && (CBC == 1)
+
+
+#if defined(CTR) && (CTR == 1)
+
+// Same function for encrypting as for decrypting. 
+// IV is incremented for every block, and used after encryption as XOR-compliment for output
+// Suggesting https://en.wikipedia.org/wiki/Padding_(cryptography)#PKCS7 for padding scheme
+// NOTES: you need to set IV in ctx with AES_init_ctx_iv() or AES_ctx_set_iv()
+//        no IV should ever be reused with the same key 
+void AES_CTR_xcrypt_buffer(struct AES_ctx* ctx, uint8_t* buf, size_t length);
+
+#endif // #if defined(CTR) && (CTR == 1)
+
+#include  // CBC mode, for memset
+
+/*****************************************************************************/
+/* Defines:                                                                  */
+/*****************************************************************************/
+// The number of columns comprising a state in AES. This is a constant in AES. Value=4
+#define Nb 4
+
+#if defined(AES256) && (AES256 == 1)
+    #define Nk 8
+    #define Nr 14
+#elif defined(AES192) && (AES192 == 1)
+    #define Nk 6
+    #define Nr 12
+#else
+    #define Nk 4        // The number of 32 bit words in a key.
+    #define Nr 10       // The number of rounds in AES Cipher.
+#endif
+
+// jcallan@github points out that declaring Multiply as a function 
+// reduces code size considerably with the Keil ARM compiler.
+// See this link for more information: https://github.com/kokke/tiny-AES-C/pull/3
+#ifndef MULTIPLY_AS_A_FUNCTION
+  #define MULTIPLY_AS_A_FUNCTION 0
+#endif
+
+
+
+
+/*****************************************************************************/
+/* Private variables:                                                        */
+/*****************************************************************************/
+// state - array holding the intermediate results during decryption.
+typedef uint8_t state_t[4][4];
+
+
+
+// The lookup-tables are marked const so they can be placed in read-only storage instead of RAM
+// The numbers below can be computed dynamically trading ROM for RAM - 
+// This can be useful in (embedded) bootloader applications, where ROM is often limited.
+static const uint8_t sbox[256] = {
+  //0     1    2      3     4    5     6     7      8    9     A      B    C     D     E     F
+  0x63, 0x7c, 0x77, 0x7b, 0xf2, 0x6b, 0x6f, 0xc5, 0x30, 0x01, 0x67, 0x2b, 0xfe, 0xd7, 0xab, 0x76,
+  0xca, 0x82, 0xc9, 0x7d, 0xfa, 0x59, 0x47, 0xf0, 0xad, 0xd4, 0xa2, 0xaf, 0x9c, 0xa4, 0x72, 0xc0,
+  0xb7, 0xfd, 0x93, 0x26, 0x36, 0x3f, 0xf7, 0xcc, 0x34, 0xa5, 0xe5, 0xf1, 0x71, 0xd8, 0x31, 0x15,
+  0x04, 0xc7, 0x23, 0xc3, 0x18, 0x96, 0x05, 0x9a, 0x07, 0x12, 0x80, 0xe2, 0xeb, 0x27, 0xb2, 0x75,
+  0x09, 0x83, 0x2c, 0x1a, 0x1b, 0x6e, 0x5a, 0xa0, 0x52, 0x3b, 0xd6, 0xb3, 0x29, 0xe3, 0x2f, 0x84,
+  0x53, 0xd1, 0x00, 0xed, 0x20, 0xfc, 0xb1, 0x5b, 0x6a, 0xcb, 0xbe, 0x39, 0x4a, 0x4c, 0x58, 0xcf,
+  0xd0, 0xef, 0xaa, 0xfb, 0x43, 0x4d, 0x33, 0x85, 0x45, 0xf9, 0x02, 0x7f, 0x50, 0x3c, 0x9f, 0xa8,
+  0x51, 0xa3, 0x40, 0x8f, 0x92, 0x9d, 0x38, 0xf5, 0xbc, 0xb6, 0xda, 0x21, 0x10, 0xff, 0xf3, 0xd2,
+  0xcd, 0x0c, 0x13, 0xec, 0x5f, 0x97, 0x44, 0x17, 0xc4, 0xa7, 0x7e, 0x3d, 0x64, 0x5d, 0x19, 0x73,
+  0x60, 0x81, 0x4f, 0xdc, 0x22, 0x2a, 0x90, 0x88, 0x46, 0xee, 0xb8, 0x14, 0xde, 0x5e, 0x0b, 0xdb,
+  0xe0, 0x32, 0x3a, 0x0a, 0x49, 0x06, 0x24, 0x5c, 0xc2, 0xd3, 0xac, 0x62, 0x91, 0x95, 0xe4, 0x79,
+  0xe7, 0xc8, 0x37, 0x6d, 0x8d, 0xd5, 0x4e, 0xa9, 0x6c, 0x56, 0xf4, 0xea, 0x65, 0x7a, 0xae, 0x08,
+  0xba, 0x78, 0x25, 0x2e, 0x1c, 0xa6, 0xb4, 0xc6, 0xe8, 0xdd, 0x74, 0x1f, 0x4b, 0xbd, 0x8b, 0x8a,
+  0x70, 0x3e, 0xb5, 0x66, 0x48, 0x03, 0xf6, 0x0e, 0x61, 0x35, 0x57, 0xb9, 0x86, 0xc1, 0x1d, 0x9e,
+  0xe1, 0xf8, 0x98, 0x11, 0x69, 0xd9, 0x8e, 0x94, 0x9b, 0x1e, 0x87, 0xe9, 0xce, 0x55, 0x28, 0xdf,
+  0x8c, 0xa1, 0x89, 0x0d, 0xbf, 0xe6, 0x42, 0x68, 0x41, 0x99, 0x2d, 0x0f, 0xb0, 0x54, 0xbb, 0x16 };
+
+#if (defined(CBC) && CBC == 1) || (defined(ECB) && ECB == 1)
+static const uint8_t rsbox[256] = {
+  0x52, 0x09, 0x6a, 0xd5, 0x30, 0x36, 0xa5, 0x38, 0xbf, 0x40, 0xa3, 0x9e, 0x81, 0xf3, 0xd7, 0xfb,
+  0x7c, 0xe3, 0x39, 0x82, 0x9b, 0x2f, 0xff, 0x87, 0x34, 0x8e, 0x43, 0x44, 0xc4, 0xde, 0xe9, 0xcb,
+  0x54, 0x7b, 0x94, 0x32, 0xa6, 0xc2, 0x23, 0x3d, 0xee, 0x4c, 0x95, 0x0b, 0x42, 0xfa, 0xc3, 0x4e,
+  0x08, 0x2e, 0xa1, 0x66, 0x28, 0xd9, 0x24, 0xb2, 0x76, 0x5b, 0xa2, 0x49, 0x6d, 0x8b, 0xd1, 0x25,
+  0x72, 0xf8, 0xf6, 0x64, 0x86, 0x68, 0x98, 0x16, 0xd4, 0xa4, 0x5c, 0xcc, 0x5d, 0x65, 0xb6, 0x92,
+  0x6c, 0x70, 0x48, 0x50, 0xfd, 0xed, 0xb9, 0xda, 0x5e, 0x15, 0x46, 0x57, 0xa7, 0x8d, 0x9d, 0x84,
+  0x90, 0xd8, 0xab, 0x00, 0x8c, 0xbc, 0xd3, 0x0a, 0xf7, 0xe4, 0x58, 0x05, 0xb8, 0xb3, 0x45, 0x06,
+  0xd0, 0x2c, 0x1e, 0x8f, 0xca, 0x3f, 0x0f, 0x02, 0xc1, 0xaf, 0xbd, 0x03, 0x01, 0x13, 0x8a, 0x6b,
+  0x3a, 0x91, 0x11, 0x41, 0x4f, 0x67, 0xdc, 0xea, 0x97, 0xf2, 0xcf, 0xce, 0xf0, 0xb4, 0xe6, 0x73,
+  0x96, 0xac, 0x74, 0x22, 0xe7, 0xad, 0x35, 0x85, 0xe2, 0xf9, 0x37, 0xe8, 0x1c, 0x75, 0xdf, 0x6e,
+  0x47, 0xf1, 0x1a, 0x71, 0x1d, 0x29, 0xc5, 0x89, 0x6f, 0xb7, 0x62, 0x0e, 0xaa, 0x18, 0xbe, 0x1b,
+  0xfc, 0x56, 0x3e, 0x4b, 0xc6, 0xd2, 0x79, 0x20, 0x9a, 0xdb, 0xc0, 0xfe, 0x78, 0xcd, 0x5a, 0xf4,
+  0x1f, 0xdd, 0xa8, 0x33, 0x88, 0x07, 0xc7, 0x31, 0xb1, 0x12, 0x10, 0x59, 0x27, 0x80, 0xec, 0x5f,
+  0x60, 0x51, 0x7f, 0xa9, 0x19, 0xb5, 0x4a, 0x0d, 0x2d, 0xe5, 0x7a, 0x9f, 0x93, 0xc9, 0x9c, 0xef,
+  0xa0, 0xe0, 0x3b, 0x4d, 0xae, 0x2a, 0xf5, 0xb0, 0xc8, 0xeb, 0xbb, 0x3c, 0x83, 0x53, 0x99, 0x61,
+  0x17, 0x2b, 0x04, 0x7e, 0xba, 0x77, 0xd6, 0x26, 0xe1, 0x69, 0x14, 0x63, 0x55, 0x21, 0x0c, 0x7d };
+#endif
+
+// The round constant word array, Rcon[i], contains the values given by 
+// x to the power (i-1) being powers of x (x is denoted as {02}) in the field GF(2^8)
+static const uint8_t Rcon[11] = {
+  0x8d, 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0x1b, 0x36 };
+
+/*
+ * Jordan Goulder points out in PR #12 (https://github.com/kokke/tiny-AES-C/pull/12),
+ * that you can remove most of the elements in the Rcon array, because they are unused.
+ *
+ * From Wikipedia's article on the Rijndael key schedule @ https://en.wikipedia.org/wiki/Rijndael_key_schedule#Rcon
+ * 
+ * "Only the first some of these constants are actually used – up to rcon[10] for AES-128 (as 11 round keys are needed), 
+ *  up to rcon[8] for AES-192, up to rcon[7] for AES-256. rcon[0] is not used in AES algorithm."
+ */
+
+
+/*****************************************************************************/
+/* Private functions:                                                        */
+/*****************************************************************************/
+/*
+static uint8_t getSBoxValue(uint8_t num)
+{
+  return sbox[num];
+}
+*/
+#define getSBoxValue(num) (sbox[(num)])
+
+// This function produces Nb(Nr+1) round keys. The round keys are used in each round to decrypt the states. 
+static void KeyExpansion(uint8_t* RoundKey, const uint8_t* Key)
+{
+  unsigned i, j, k;
+  uint8_t tempa[4]; // Used for the column/row operations
+  
+  // The first round key is the key itself.
+  for (i = 0; i < Nk; ++i)
+  {
+    RoundKey[(i * 4) + 0] = Key[(i * 4) + 0];
+    RoundKey[(i * 4) + 1] = Key[(i * 4) + 1];
+    RoundKey[(i * 4) + 2] = Key[(i * 4) + 2];
+    RoundKey[(i * 4) + 3] = Key[(i * 4) + 3];
+  }
+
+  // All other round keys are found from the previous round keys.
+  for (i = Nk; i < Nb * (Nr + 1); ++i)
+  {
+    {
+      k = (i - 1) * 4;
+      tempa[0]=RoundKey[k + 0];
+      tempa[1]=RoundKey[k + 1];
+      tempa[2]=RoundKey[k + 2];
+      tempa[3]=RoundKey[k + 3];
+
+    }
+
+    if (i % Nk == 0)
+    {
+      // This function shifts the 4 bytes in a word to the left once.
+      // [a0,a1,a2,a3] becomes [a1,a2,a3,a0]
+
+      // Function RotWord()
+      {
+        const uint8_t u8tmp = tempa[0];
+        tempa[0] = tempa[1];
+        tempa[1] = tempa[2];
+        tempa[2] = tempa[3];
+        tempa[3] = u8tmp;
+      }
+
+      // SubWord() is a function that takes a four-byte input word and 
+      // applies the S-box to each of the four bytes to produce an output word.
+
+      // Function Subword()
+      {
+        tempa[0] = getSBoxValue(tempa[0]);
+        tempa[1] = getSBoxValue(tempa[1]);
+        tempa[2] = getSBoxValue(tempa[2]);
+        tempa[3] = getSBoxValue(tempa[3]);
+      }
+
+      tempa[0] = tempa[0] ^ Rcon[i/Nk];
+    }
+#if defined(AES256) && (AES256 == 1)
+    if (i % Nk == 4)
+    {
+      // Function Subword()
+      {
+        tempa[0] = getSBoxValue(tempa[0]);
+        tempa[1] = getSBoxValue(tempa[1]);
+        tempa[2] = getSBoxValue(tempa[2]);
+        tempa[3] = getSBoxValue(tempa[3]);
+      }
+    }
+#endif
+    j = i * 4; k=(i - Nk) * 4;
+    RoundKey[j + 0] = RoundKey[k + 0] ^ tempa[0];
+    RoundKey[j + 1] = RoundKey[k + 1] ^ tempa[1];
+    RoundKey[j + 2] = RoundKey[k + 2] ^ tempa[2];
+    RoundKey[j + 3] = RoundKey[k + 3] ^ tempa[3];
+  }
+}
+
+void AES_init_ctx(struct AES_ctx* ctx, const uint8_t* key)
+{
+  KeyExpansion(ctx->RoundKey, key);
+}
+#if (defined(CBC) && (CBC == 1)) || (defined(CTR) && (CTR == 1))
+void AES_init_ctx_iv(struct AES_ctx* ctx, const uint8_t* key, const uint8_t* iv)
+{
+  KeyExpansion(ctx->RoundKey, key);
+  memcpy (ctx->Iv, iv, AES_BLOCKLEN);
+}
+void AES_ctx_set_iv(struct AES_ctx* ctx, const uint8_t* iv)
+{
+  memcpy (ctx->Iv, iv, AES_BLOCKLEN);
+}
+#endif
+
+// This function adds the round key to state.
+// The round key is added to the state by an XOR function.
+static void AddRoundKey(uint8_t round, state_t* state, const uint8_t* RoundKey)
+{
+  uint8_t i,j;
+  for (i = 0; i < 4; ++i)
+  {
+    for (j = 0; j < 4; ++j)
+    {
+      (*state)[i][j] ^= RoundKey[(round * Nb * 4) + (i * Nb) + j];
+    }
+  }
+}
+
+// The SubBytes Function Substitutes the values in the
+// state matrix with values in an S-box.
+static void SubBytes(state_t* state)
+{
+  uint8_t i, j;
+  for (i = 0; i < 4; ++i)
+  {
+    for (j = 0; j < 4; ++j)
+    {
+      (*state)[j][i] = getSBoxValue((*state)[j][i]);
+    }
+  }
+}
+
+// The ShiftRows() function shifts the rows in the state to the left.
+// Each row is shifted with different offset.
+// Offset = Row number. So the first row is not shifted.
+static void ShiftRows(state_t* state)
+{
+  uint8_t temp;
+
+  // Rotate first row 1 columns to left  
+  temp           = (*state)[0][1];
+  (*state)[0][1] = (*state)[1][1];
+  (*state)[1][1] = (*state)[2][1];
+  (*state)[2][1] = (*state)[3][1];
+  (*state)[3][1] = temp;
+
+  // Rotate second row 2 columns to left  
+  temp           = (*state)[0][2];
+  (*state)[0][2] = (*state)[2][2];
+  (*state)[2][2] = temp;
+
+  temp           = (*state)[1][2];
+  (*state)[1][2] = (*state)[3][2];
+  (*state)[3][2] = temp;
+
+  // Rotate third row 3 columns to left
+  temp           = (*state)[0][3];
+  (*state)[0][3] = (*state)[3][3];
+  (*state)[3][3] = (*state)[2][3];
+  (*state)[2][3] = (*state)[1][3];
+  (*state)[1][3] = temp;
+}
+
+static uint8_t xtime(uint8_t x)
+{
+  return ((x<<1) ^ (((x>>7) & 1) * 0x1b));
+}
+
+// MixColumns function mixes the columns of the state matrix
+static void MixColumns(state_t* state)
+{
+  uint8_t i;
+  uint8_t Tmp, Tm, t;
+  for (i = 0; i < 4; ++i)
+  {  
+    t   = (*state)[i][0];
+    Tmp = (*state)[i][0] ^ (*state)[i][1] ^ (*state)[i][2] ^ (*state)[i][3] ;
+    Tm  = (*state)[i][0] ^ (*state)[i][1] ; Tm = xtime(Tm);  (*state)[i][0] ^= Tm ^ Tmp ;
+    Tm  = (*state)[i][1] ^ (*state)[i][2] ; Tm = xtime(Tm);  (*state)[i][1] ^= Tm ^ Tmp ;
+    Tm  = (*state)[i][2] ^ (*state)[i][3] ; Tm = xtime(Tm);  (*state)[i][2] ^= Tm ^ Tmp ;
+    Tm  = (*state)[i][3] ^ t ;              Tm = xtime(Tm);  (*state)[i][3] ^= Tm ^ Tmp ;
+  }
+}
+
+// Multiply is used to multiply numbers in the field GF(2^8)
+// Note: The last call to xtime() is unneeded, but often ends up generating a smaller binary
+//       The compiler seems to be able to vectorize the operation better this way.
+//       See https://github.com/kokke/tiny-AES-c/pull/34
+#if MULTIPLY_AS_A_FUNCTION
+static uint8_t Multiply(uint8_t x, uint8_t y)
+{
+  return (((y & 1) * x) ^
+       ((y>>1 & 1) * xtime(x)) ^
+       ((y>>2 & 1) * xtime(xtime(x))) ^
+       ((y>>3 & 1) * xtime(xtime(xtime(x)))) ^
+       ((y>>4 & 1) * xtime(xtime(xtime(xtime(x)))))); /* this last call to xtime() can be omitted */
+  }
+#else
+#define Multiply(x, y)                                \
+      (  ((y & 1) * x) ^                              \
+      ((y>>1 & 1) * xtime(x)) ^                       \
+      ((y>>2 & 1) * xtime(xtime(x))) ^                \
+      ((y>>3 & 1) * xtime(xtime(xtime(x)))) ^         \
+      ((y>>4 & 1) * xtime(xtime(xtime(xtime(x))))))   \
+
+#endif
+
+#if (defined(CBC) && CBC == 1) || (defined(ECB) && ECB == 1)
+/*
+static uint8_t getSBoxInvert(uint8_t num)
+{
+  return rsbox[num];
+}
+*/
+#define getSBoxInvert(num) (rsbox[(num)])
+
+// MixColumns function mixes the columns of the state matrix.
+// The method used to multiply may be difficult to understand for the inexperienced.
+// Please use the references to gain more information.
+static void InvMixColumns(state_t* state)
+{
+  int i;
+  uint8_t a, b, c, d;
+  for (i = 0; i < 4; ++i)
+  { 
+    a = (*state)[i][0];
+    b = (*state)[i][1];
+    c = (*state)[i][2];
+    d = (*state)[i][3];
+
+    (*state)[i][0] = Multiply(a, 0x0e) ^ Multiply(b, 0x0b) ^ Multiply(c, 0x0d) ^ Multiply(d, 0x09);
+    (*state)[i][1] = Multiply(a, 0x09) ^ Multiply(b, 0x0e) ^ Multiply(c, 0x0b) ^ Multiply(d, 0x0d);
+    (*state)[i][2] = Multiply(a, 0x0d) ^ Multiply(b, 0x09) ^ Multiply(c, 0x0e) ^ Multiply(d, 0x0b);
+    (*state)[i][3] = Multiply(a, 0x0b) ^ Multiply(b, 0x0d) ^ Multiply(c, 0x09) ^ Multiply(d, 0x0e);
+  }
+}
+
+
+// The SubBytes Function Substitutes the values in the
+// state matrix with values in an S-box.
+static void InvSubBytes(state_t* state)
+{
+  uint8_t i, j;
+  for (i = 0; i < 4; ++i)
+  {
+    for (j = 0; j < 4; ++j)
+    {
+      (*state)[j][i] = getSBoxInvert((*state)[j][i]);
+    }
+  }
+}
+
+static void InvShiftRows(state_t* state)
+{
+  uint8_t temp;
+
+  // Rotate first row 1 columns to right  
+  temp = (*state)[3][1];
+  (*state)[3][1] = (*state)[2][1];
+  (*state)[2][1] = (*state)[1][1];
+  (*state)[1][1] = (*state)[0][1];
+  (*state)[0][1] = temp;
+
+  // Rotate second row 2 columns to right 
+  temp = (*state)[0][2];
+  (*state)[0][2] = (*state)[2][2];
+  (*state)[2][2] = temp;
+
+  temp = (*state)[1][2];
+  (*state)[1][2] = (*state)[3][2];
+  (*state)[3][2] = temp;
+
+  // Rotate third row 3 columns to right
+  temp = (*state)[0][3];
+  (*state)[0][3] = (*state)[1][3];
+  (*state)[1][3] = (*state)[2][3];
+  (*state)[2][3] = (*state)[3][3];
+  (*state)[3][3] = temp;
+}
+#endif // #if (defined(CBC) && CBC == 1) || (defined(ECB) && ECB == 1)
+
+// Cipher is the main function that encrypts the PlainText.
+static void Cipher(state_t* state, const uint8_t* RoundKey)
+{
+  uint8_t round = 0;
+
+  // Add the First round key to the state before starting the rounds.
+  AddRoundKey(0, state, RoundKey);
+
+  // There will be Nr rounds.
+  // The first Nr-1 rounds are identical.
+  // These Nr rounds are executed in the loop below.
+  // Last one without MixColumns()
+  for (round = 1; ; ++round)
+  {
+    SubBytes(state);
+    ShiftRows(state);
+    if (round == Nr) {
+      break;
+    }
+    MixColumns(state);
+    AddRoundKey(round, state, RoundKey);
+  }
+  // Add round key to last round
+  AddRoundKey(Nr, state, RoundKey);
+}
+
+#if (defined(CBC) && CBC == 1) || (defined(ECB) && ECB == 1)
+static void InvCipher(state_t* state, const uint8_t* RoundKey)
+{
+  uint8_t round = 0;
+
+  // Add the First round key to the state before starting the rounds.
+  AddRoundKey(Nr, state, RoundKey);
+
+  // There will be Nr rounds.
+  // The first Nr-1 rounds are identical.
+  // These Nr rounds are executed in the loop below.
+  // Last one without InvMixColumn()
+  for (round = (Nr - 1); ; --round)
+  {
+    InvShiftRows(state);
+    InvSubBytes(state);
+    AddRoundKey(round, state, RoundKey);
+    if (round == 0) {
+      break;
+    }
+    InvMixColumns(state);
+  }
+
+}
+#endif // #if (defined(CBC) && CBC == 1) || (defined(ECB) && ECB == 1)
+
+/*****************************************************************************/
+/* Public functions:                                                         */
+/*****************************************************************************/
+#if defined(ECB) && (ECB == 1)
+
+
+void AES_ECB_encrypt(const struct AES_ctx* ctx, uint8_t* buf)
+{
+  // The next function call encrypts the PlainText with the Key using AES algorithm.
+  Cipher((state_t*)buf, ctx->RoundKey);
+}
+
+void AES_ECB_decrypt(const struct AES_ctx* ctx, uint8_t* buf)
+{
+  // The next function call decrypts the PlainText with the Key using AES algorithm.
+  InvCipher((state_t*)buf, ctx->RoundKey);
+}
+
+
+#endif // #if defined(ECB) && (ECB == 1)
+
+
+
+
+
+#if defined(CBC) && (CBC == 1)
+
+
+static void XorWithIv(uint8_t* buf, const uint8_t* Iv)
+{
+  uint8_t i;
+  for (i = 0; i < AES_BLOCKLEN; ++i) // The block in AES is always 128bit no matter the key size
+  {
+    buf[i] ^= Iv[i];
+  }
+}
+
+void AES_CBC_encrypt_buffer(struct AES_ctx *ctx, uint8_t* buf, size_t length)
+{
+  size_t i;
+  uint8_t *Iv = ctx->Iv;
+  for (i = 0; i < length; i += AES_BLOCKLEN)
+  {
+    XorWithIv(buf, Iv);
+    Cipher((state_t*)buf, ctx->RoundKey);
+    Iv = buf;
+    buf += AES_BLOCKLEN;
+  }
+  /* store Iv in ctx for next call */
+  memcpy(ctx->Iv, Iv, AES_BLOCKLEN);
+}
+
+void AES_CBC_decrypt_buffer(struct AES_ctx* ctx, uint8_t* buf, size_t length)
+{
+  size_t i;
+  uint8_t storeNextIv[AES_BLOCKLEN];
+  for (i = 0; i < length; i += AES_BLOCKLEN)
+  {
+    memcpy(storeNextIv, buf, AES_BLOCKLEN);
+    InvCipher((state_t*)buf, ctx->RoundKey);
+    XorWithIv(buf, ctx->Iv);
+    memcpy(ctx->Iv, storeNextIv, AES_BLOCKLEN);
+    buf += AES_BLOCKLEN;
+  }
+
+}
+
+#endif // #if defined(CBC) && (CBC == 1)
+
+
+
+#if defined(CTR) && (CTR == 1)
+
+/* Symmetrical operation: same function for encrypting as for decrypting. Note any IV/nonce should never be reused with the same key */
+void AES_CTR_xcrypt_buffer(struct AES_ctx* ctx, uint8_t* buf, size_t length)
+{
+  uint8_t buffer[AES_BLOCKLEN];
+  
+  size_t i;
+  int bi;
+  for (i = 0, bi = AES_BLOCKLEN; i < length; ++i, ++bi)
+  {
+    if (bi == AES_BLOCKLEN) /* we need to regen xor compliment in buffer */
+    {
+      
+      memcpy(buffer, ctx->Iv, AES_BLOCKLEN);
+      Cipher((state_t*)buffer,ctx->RoundKey);
+
+      /* Increment Iv and handle overflow */
+      for (bi = (AES_BLOCKLEN - 1); bi >= 0; --bi)
+      {
+	/* inc will overflow */
+        if (ctx->Iv[bi] == 255)
+	{
+          ctx->Iv[bi] = 0;
+          continue;
+        } 
+        ctx->Iv[bi] += 1;
+        break;   
+      }
+      bi = 0;
+    }
+
+    buf[i] = (buf[i] ^ buffer[bi]);
+  }
+}
+
+#endif // #if defined(CTR) && (CTR == 1)
+
+#ifdef ECB
+void encrypt_ecb(void)
+{
+#if defined(AES256)
+    uint8_t key[] = { 0x60, 0x3d, 0xeb, 0x10, 0x15, 0xca, 0x71, 0xbe, 0x2b, 0x73, 0xae, 0xf0, 0x85, 0x7d, 0x77, 0x81,
+                      0x1f, 0x35, 0x2c, 0x07, 0x3b, 0x61, 0x08, 0xd7, 0x2d, 0x98, 0x10, 0xa3, 0x09, 0x14, 0xdf, 0xf4 };
+    uint8_t out[] = { 0xf3, 0xee, 0xd1, 0xbd, 0xb5, 0xd2, 0xa0, 0x3c, 0x06, 0x4b, 0x5a, 0x7e, 0x3d, 0xb1, 0x81, 0xf8 };
+#elif defined(AES192)
+    uint8_t key[] = { 0x8e, 0x73, 0xb0, 0xf7, 0xda, 0x0e, 0x64, 0x52, 0xc8, 0x10, 0xf3, 0x2b, 0x80, 0x90, 0x79, 0xe5,
+                      0x62, 0xf8, 0xea, 0xd2, 0x52, 0x2c, 0x6b, 0x7b };
+    uint8_t out[] = { 0xbd, 0x33, 0x4f, 0x1d, 0x6e, 0x45, 0xf2, 0x5f, 0xf7, 0x12, 0xa2, 0x14, 0x57, 0x1f, 0xa5, 0xcc };
+#elif defined(AES128)
+    uint8_t key[] = { 0x2b, 0x7e, 0x15, 0x16, 0x28, 0xae, 0xd2, 0xa6, 0xab, 0xf7, 0x15, 0x88, 0x09, 0xcf, 0x4f, 0x3c };
+    uint8_t out[] = { 0x3a, 0xd7, 0x7b, 0xb4, 0x0d, 0x7a, 0x36, 0x60, 0xa8, 0x9e, 0xca, 0xf3, 0x24, 0x66, 0xef, 0x97 };
+#endif
+
+    uint8_t in[]  = { 0x6b, 0xc1, 0xbe, 0xe2, 0x2e, 0x40, 0x9f, 0x96, 0xe9, 0x3d, 0x7e, 0x11, 0x73, 0x93, 0x17, 0x2a };
+    struct AES_ctx ctx;
+
+    AES_init_ctx(&ctx, key);
+    AES_ECB_encrypt(&ctx, in);
+
+    ASSERT (0 == memcmp((char*) out, (char*) in, 16));
+}
+#endif
+
+#ifdef CBC
+void decrypt_cbc(void)
+{
+
+#if defined(AES256)
+    uint8_t key[] = { 0x60, 0x3d, 0xeb, 0x10, 0x15, 0xca, 0x71, 0xbe, 0x2b, 0x73, 0xae, 0xf0, 0x85, 0x7d, 0x77, 0x81,
+                      0x1f, 0x35, 0x2c, 0x07, 0x3b, 0x61, 0x08, 0xd7, 0x2d, 0x98, 0x10, 0xa3, 0x09, 0x14, 0xdf, 0xf4 };
+    uint8_t in[]  = { 0xf5, 0x8c, 0x4c, 0x04, 0xd6, 0xe5, 0xf1, 0xba, 0x77, 0x9e, 0xab, 0xfb, 0x5f, 0x7b, 0xfb, 0xd6,
+                      0x9c, 0xfc, 0x4e, 0x96, 0x7e, 0xdb, 0x80, 0x8d, 0x67, 0x9f, 0x77, 0x7b, 0xc6, 0x70, 0x2c, 0x7d,
+                      0x39, 0xf2, 0x33, 0x69, 0xa9, 0xd9, 0xba, 0xcf, 0xa5, 0x30, 0xe2, 0x63, 0x04, 0x23, 0x14, 0x61,
+                      0xb2, 0xeb, 0x05, 0xe2, 0xc3, 0x9b, 0xe9, 0xfc, 0xda, 0x6c, 0x19, 0x07, 0x8c, 0x6a, 0x9d, 0x1b };
+#elif defined(AES192)
+    uint8_t key[] = { 0x8e, 0x73, 0xb0, 0xf7, 0xda, 0x0e, 0x64, 0x52, 0xc8, 0x10, 0xf3, 0x2b, 0x80, 0x90, 0x79, 0xe5, 0x62, 0xf8, 0xea, 0xd2, 0x52, 0x2c, 0x6b, 0x7b };
+    uint8_t in[]  = { 0x4f, 0x02, 0x1d, 0xb2, 0x43, 0xbc, 0x63, 0x3d, 0x71, 0x78, 0x18, 0x3a, 0x9f, 0xa0, 0x71, 0xe8,
+                      0xb4, 0xd9, 0xad, 0xa9, 0xad, 0x7d, 0xed, 0xf4, 0xe5, 0xe7, 0x38, 0x76, 0x3f, 0x69, 0x14, 0x5a,
+                      0x57, 0x1b, 0x24, 0x20, 0x12, 0xfb, 0x7a, 0xe0, 0x7f, 0xa9, 0xba, 0xac, 0x3d, 0xf1, 0x02, 0xe0,
+                      0x08, 0xb0, 0xe2, 0x79, 0x88, 0x59, 0x88, 0x81, 0xd9, 0x20, 0xa9, 0xe6, 0x4f, 0x56, 0x15, 0xcd };
+#elif defined(AES128)
+    uint8_t key[] = { 0x2b, 0x7e, 0x15, 0x16, 0x28, 0xae, 0xd2, 0xa6, 0xab, 0xf7, 0x15, 0x88, 0x09, 0xcf, 0x4f, 0x3c };
+    uint8_t in[]  = { 0x76, 0x49, 0xab, 0xac, 0x81, 0x19, 0xb2, 0x46, 0xce, 0xe9, 0x8e, 0x9b, 0x12, 0xe9, 0x19, 0x7d,
+                      0x50, 0x86, 0xcb, 0x9b, 0x50, 0x72, 0x19, 0xee, 0x95, 0xdb, 0x11, 0x3a, 0x91, 0x76, 0x78, 0xb2,
+                      0x73, 0xbe, 0xd6, 0xb8, 0xe3, 0xc1, 0x74, 0x3b, 0x71, 0x16, 0xe6, 0x9e, 0x22, 0x22, 0x95, 0x16,
+                      0x3f, 0xf1, 0xca, 0xa1, 0x68, 0x1f, 0xac, 0x09, 0x12, 0x0e, 0xca, 0x30, 0x75, 0x86, 0xe1, 0xa7 };
+#endif
+    uint8_t iv[]  = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f };
+    uint8_t out[] = { 0x6b, 0xc1, 0xbe, 0xe2, 0x2e, 0x40, 0x9f, 0x96, 0xe9, 0x3d, 0x7e, 0x11, 0x73, 0x93, 0x17, 0x2a,
+                      0xae, 0x2d, 0x8a, 0x57, 0x1e, 0x03, 0xac, 0x9c, 0x9e, 0xb7, 0x6f, 0xac, 0x45, 0xaf, 0x8e, 0x51,
+                      0x30, 0xc8, 0x1c, 0x46, 0xa3, 0x5c, 0xe4, 0x11, 0xe5, 0xfb, 0xc1, 0x19, 0x1a, 0x0a, 0x52, 0xef,
+                      0xf6, 0x9f, 0x24, 0x45, 0xdf, 0x4f, 0x9b, 0x17, 0xad, 0x2b, 0x41, 0x7b, 0xe6, 0x6c, 0x37, 0x10 };
+//  uint8_t buffer[64];
+    struct AES_ctx ctx;
+
+    AES_init_ctx_iv(&ctx, key, iv);
+    AES_CBC_decrypt_buffer(&ctx, in, 64);
+
+    ASSERT (0 == memcmp((char*) out, (char*) in, 64));
+}
+
+void encrypt_cbc(void)
+{
+#if defined(AES256)
+    uint8_t key[] = { 0x60, 0x3d, 0xeb, 0x10, 0x15, 0xca, 0x71, 0xbe, 0x2b, 0x73, 0xae, 0xf0, 0x85, 0x7d, 0x77, 0x81,
+                      0x1f, 0x35, 0x2c, 0x07, 0x3b, 0x61, 0x08, 0xd7, 0x2d, 0x98, 0x10, 0xa3, 0x09, 0x14, 0xdf, 0xf4 };
+    uint8_t out[] = { 0xf5, 0x8c, 0x4c, 0x04, 0xd6, 0xe5, 0xf1, 0xba, 0x77, 0x9e, 0xab, 0xfb, 0x5f, 0x7b, 0xfb, 0xd6,
+                      0x9c, 0xfc, 0x4e, 0x96, 0x7e, 0xdb, 0x80, 0x8d, 0x67, 0x9f, 0x77, 0x7b, 0xc6, 0x70, 0x2c, 0x7d,
+                      0x39, 0xf2, 0x33, 0x69, 0xa9, 0xd9, 0xba, 0xcf, 0xa5, 0x30, 0xe2, 0x63, 0x04, 0x23, 0x14, 0x61,
+                      0xb2, 0xeb, 0x05, 0xe2, 0xc3, 0x9b, 0xe9, 0xfc, 0xda, 0x6c, 0x19, 0x07, 0x8c, 0x6a, 0x9d, 0x1b };
+#elif defined(AES192)
+    uint8_t key[] = { 0x8e, 0x73, 0xb0, 0xf7, 0xda, 0x0e, 0x64, 0x52, 0xc8, 0x10, 0xf3, 0x2b, 0x80, 0x90, 0x79, 0xe5, 0x62, 0xf8, 0xea, 0xd2, 0x52, 0x2c, 0x6b, 0x7b };
+    uint8_t out[] = { 0x4f, 0x02, 0x1d, 0xb2, 0x43, 0xbc, 0x63, 0x3d, 0x71, 0x78, 0x18, 0x3a, 0x9f, 0xa0, 0x71, 0xe8,
+                      0xb4, 0xd9, 0xad, 0xa9, 0xad, 0x7d, 0xed, 0xf4, 0xe5, 0xe7, 0x38, 0x76, 0x3f, 0x69, 0x14, 0x5a,
+                      0x57, 0x1b, 0x24, 0x20, 0x12, 0xfb, 0x7a, 0xe0, 0x7f, 0xa9, 0xba, 0xac, 0x3d, 0xf1, 0x02, 0xe0,
+                      0x08, 0xb0, 0xe2, 0x79, 0x88, 0x59, 0x88, 0x81, 0xd9, 0x20, 0xa9, 0xe6, 0x4f, 0x56, 0x15, 0xcd };
+#elif defined(AES128)
+    uint8_t key[] = { 0x2b, 0x7e, 0x15, 0x16, 0x28, 0xae, 0xd2, 0xa6, 0xab, 0xf7, 0x15, 0x88, 0x09, 0xcf, 0x4f, 0x3c };
+    uint8_t out[] = { 0x76, 0x49, 0xab, 0xac, 0x81, 0x19, 0xb2, 0x46, 0xce, 0xe9, 0x8e, 0x9b, 0x12, 0xe9, 0x19, 0x7d,
+                      0x50, 0x86, 0xcb, 0x9b, 0x50, 0x72, 0x19, 0xee, 0x95, 0xdb, 0x11, 0x3a, 0x91, 0x76, 0x78, 0xb2,
+                      0x73, 0xbe, 0xd6, 0xb8, 0xe3, 0xc1, 0x74, 0x3b, 0x71, 0x16, 0xe6, 0x9e, 0x22, 0x22, 0x95, 0x16,
+                      0x3f, 0xf1, 0xca, 0xa1, 0x68, 0x1f, 0xac, 0x09, 0x12, 0x0e, 0xca, 0x30, 0x75, 0x86, 0xe1, 0xa7 };
+#endif
+    uint8_t iv[]  = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f };
+    uint8_t in[]  = { 0x6b, 0xc1, 0xbe, 0xe2, 0x2e, 0x40, 0x9f, 0x96, 0xe9, 0x3d, 0x7e, 0x11, 0x73, 0x93, 0x17, 0x2a,
+                      0xae, 0x2d, 0x8a, 0x57, 0x1e, 0x03, 0xac, 0x9c, 0x9e, 0xb7, 0x6f, 0xac, 0x45, 0xaf, 0x8e, 0x51,
+                      0x30, 0xc8, 0x1c, 0x46, 0xa3, 0x5c, 0xe4, 0x11, 0xe5, 0xfb, 0xc1, 0x19, 0x1a, 0x0a, 0x52, 0xef,
+                      0xf6, 0x9f, 0x24, 0x45, 0xdf, 0x4f, 0x9b, 0x17, 0xad, 0x2b, 0x41, 0x7b, 0xe6, 0x6c, 0x37, 0x10 };
+    struct AES_ctx ctx;
+
+    AES_init_ctx_iv(&ctx, key, iv);
+    AES_CBC_encrypt_buffer(&ctx, in, 64);
+
+    ASSERT (0 == memcmp((char*) out, (char*) in, 64));
+}
+#endif
+
+#ifdef CTR
+void xcrypt_ctr(void);
+void encrypt_ctr(void)
+{
+    return xcrypt_ctr();
+}
+
+void decrypt_ctr(void)
+{
+    return xcrypt_ctr();
+}
+
+void xcrypt_ctr(void)
+{
+#if defined(AES256)
+    uint8_t key[32] = { 0x60, 0x3d, 0xeb, 0x10, 0x15, 0xca, 0x71, 0xbe, 0x2b, 0x73, 0xae, 0xf0, 0x85, 0x7d, 0x77, 0x81,
+                        0x1f, 0x35, 0x2c, 0x07, 0x3b, 0x61, 0x08, 0xd7, 0x2d, 0x98, 0x10, 0xa3, 0x09, 0x14, 0xdf, 0xf4 };
+    uint8_t in[64]  = { 0x60, 0x1e, 0xc3, 0x13, 0x77, 0x57, 0x89, 0xa5, 0xb7, 0xa7, 0xf5, 0x04, 0xbb, 0xf3, 0xd2, 0x28, 
+                        0xf4, 0x43, 0xe3, 0xca, 0x4d, 0x62, 0xb5, 0x9a, 0xca, 0x84, 0xe9, 0x90, 0xca, 0xca, 0xf5, 0xc5, 
+                        0x2b, 0x09, 0x30, 0xda, 0xa2, 0x3d, 0xe9, 0x4c, 0xe8, 0x70, 0x17, 0xba, 0x2d, 0x84, 0x98, 0x8d, 
+                        0xdf, 0xc9, 0xc5, 0x8d, 0xb6, 0x7a, 0xad, 0xa6, 0x13, 0xc2, 0xdd, 0x08, 0x45, 0x79, 0x41, 0xa6 };
+#elif defined(AES192)
+    uint8_t key[24] = { 0x8e, 0x73, 0xb0, 0xf7, 0xda, 0x0e, 0x64, 0x52, 0xc8, 0x10, 0xf3, 0x2b, 0x80, 0x90, 0x79, 0xe5, 
+                        0x62, 0xf8, 0xea, 0xd2, 0x52, 0x2c, 0x6b, 0x7b };
+    uint8_t in[64]  = { 0x1a, 0xbc, 0x93, 0x24, 0x17, 0x52, 0x1c, 0xa2, 0x4f, 0x2b, 0x04, 0x59, 0xfe, 0x7e, 0x6e, 0x0b, 
+                        0x09, 0x03, 0x39, 0xec, 0x0a, 0xa6, 0xfa, 0xef, 0xd5, 0xcc, 0xc2, 0xc6, 0xf4, 0xce, 0x8e, 0x94, 
+                        0x1e, 0x36, 0xb2, 0x6b, 0xd1, 0xeb, 0xc6, 0x70, 0xd1, 0xbd, 0x1d, 0x66, 0x56, 0x20, 0xab, 0xf7, 
+                        0x4f, 0x78, 0xa7, 0xf6, 0xd2, 0x98, 0x09, 0x58, 0x5a, 0x97, 0xda, 0xec, 0x58, 0xc6, 0xb0, 0x50 };
+#elif defined(AES128)
+    uint8_t key[16] = { 0x2b, 0x7e, 0x15, 0x16, 0x28, 0xae, 0xd2, 0xa6, 0xab, 0xf7, 0x15, 0x88, 0x09, 0xcf, 0x4f, 0x3c };
+    uint8_t in[64]  = { 0x87, 0x4d, 0x61, 0x91, 0xb6, 0x20, 0xe3, 0x26, 0x1b, 0xef, 0x68, 0x64, 0x99, 0x0d, 0xb6, 0xce,
+                        0x98, 0x06, 0xf6, 0x6b, 0x79, 0x70, 0xfd, 0xff, 0x86, 0x17, 0x18, 0x7b, 0xb9, 0xff, 0xfd, 0xff,
+                        0x5a, 0xe4, 0xdf, 0x3e, 0xdb, 0xd5, 0xd3, 0x5e, 0x5b, 0x4f, 0x09, 0x02, 0x0d, 0xb0, 0x3e, 0xab,
+                        0x1e, 0x03, 0x1d, 0xda, 0x2f, 0xbe, 0x03, 0xd1, 0x79, 0x21, 0x70, 0xa0, 0xf3, 0x00, 0x9c, 0xee };
+#endif
+    uint8_t iv[16]  = { 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, 0xf8, 0xf9, 0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff };
+    uint8_t out[64] = { 0x6b, 0xc1, 0xbe, 0xe2, 0x2e, 0x40, 0x9f, 0x96, 0xe9, 0x3d, 0x7e, 0x11, 0x73, 0x93, 0x17, 0x2a,
+                        0xae, 0x2d, 0x8a, 0x57, 0x1e, 0x03, 0xac, 0x9c, 0x9e, 0xb7, 0x6f, 0xac, 0x45, 0xaf, 0x8e, 0x51,
+                        0x30, 0xc8, 0x1c, 0x46, 0xa3, 0x5c, 0xe4, 0x11, 0xe5, 0xfb, 0xc1, 0x19, 0x1a, 0x0a, 0x52, 0xef,
+                        0xf6, 0x9f, 0x24, 0x45, 0xdf, 0x4f, 0x9b, 0x17, 0xad, 0x2b, 0x41, 0x7b, 0xe6, 0x6c, 0x37, 0x10 };
+    struct AES_ctx ctx;
+    
+    AES_init_ctx_iv(&ctx, key, iv);
+    AES_CTR_xcrypt_buffer(&ctx, in, 64);
+  
+    ASSERT (0 == memcmp((char *) out, (char *) in, 64));
+}
+#endif
+
+#ifdef ECB
+void decrypt_ecb(void)
+{
+#if defined(AES256)
+    uint8_t key[] = { 0x60, 0x3d, 0xeb, 0x10, 0x15, 0xca, 0x71, 0xbe, 0x2b, 0x73, 0xae, 0xf0, 0x85, 0x7d, 0x77, 0x81,
+                      0x1f, 0x35, 0x2c, 0x07, 0x3b, 0x61, 0x08, 0xd7, 0x2d, 0x98, 0x10, 0xa3, 0x09, 0x14, 0xdf, 0xf4 };
+    uint8_t in[]  = { 0xf3, 0xee, 0xd1, 0xbd, 0xb5, 0xd2, 0xa0, 0x3c, 0x06, 0x4b, 0x5a, 0x7e, 0x3d, 0xb1, 0x81, 0xf8 };
+#elif defined(AES192)
+    uint8_t key[] = { 0x8e, 0x73, 0xb0, 0xf7, 0xda, 0x0e, 0x64, 0x52, 0xc8, 0x10, 0xf3, 0x2b, 0x80, 0x90, 0x79, 0xe5,
+                      0x62, 0xf8, 0xea, 0xd2, 0x52, 0x2c, 0x6b, 0x7b };
+    uint8_t in[]  = { 0xbd, 0x33, 0x4f, 0x1d, 0x6e, 0x45, 0xf2, 0x5f, 0xf7, 0x12, 0xa2, 0x14, 0x57, 0x1f, 0xa5, 0xcc };
+#elif defined(AES128)
+    uint8_t key[] = { 0x2b, 0x7e, 0x15, 0x16, 0x28, 0xae, 0xd2, 0xa6, 0xab, 0xf7, 0x15, 0x88, 0x09, 0xcf, 0x4f, 0x3c };
+    uint8_t in[]  = { 0x3a, 0xd7, 0x7b, 0xb4, 0x0d, 0x7a, 0x36, 0x60, 0xa8, 0x9e, 0xca, 0xf3, 0x24, 0x66, 0xef, 0x97 };
+#endif
+
+    uint8_t out[]   = { 0x6b, 0xc1, 0xbe, 0xe2, 0x2e, 0x40, 0x9f, 0x96, 0xe9, 0x3d, 0x7e, 0x11, 0x73, 0x93, 0x17, 0x2a };
+    struct AES_ctx ctx;
+    
+    AES_init_ctx(&ctx, key);
+    AES_ECB_decrypt(&ctx, in);
+
+    ASSERT (0 == memcmp((char*) out, (char*) in, 16));
+}
+#endif
+
+#endif // Disable everything until here for some targets with too little memory
+
+void
+testAES (void)
+{
+#ifdef CBC
+    decrypt_cbc();
+	encrypt_cbc();
+#endif
+
+#ifdef ECB
+    encrypt_ecb();
+    decrypt_ecb();
+#endif
+
+#ifdef CTR
+    encrypt_ctr();
+    decrypt_ctr();
+#endif
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/uitobcd.c sdcc-4.2.0+dfsg/support/regression/tests/uitobcd.c
--- sdcc-4.0.0+dfsg/support/regression/tests/uitobcd.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/uitobcd.c	2020-07-15 09:41:13.000000000 +0000
@@ -0,0 +1,49 @@
+/*
+   uitobcd.c
+*/
+
+#include 
+#include 
+
+extern void __uitobcd (unsigned int v, unsigned char r[3]);
+#define CHECK(v)              \
+    do {                      \
+        static const unsigned char u[3] = { 0x##v % 0x100, (0x##v / 0x100) % 0x100, (0x##v / 0x10000) % 0x100 }; \
+        unsigned char r[3] = { 0xff, 0xff, 0xff };   \
+        __uitobcd (v, r);     \
+        unsigned long bcd = r[2] * 0x10000 + r[1] * 0x100 + r[0]; \
+        ASSERT ((#v,(r[0]==u[0]&&r[1]==u[1]&&r[2]==u[2]))); \
+    } while (0)
+
+void test__uitobcd (void)
+{
+#if defined(__SDCC_z80)
+  CHECK(0);
+  CHECK(1);
+  CHECK(2);
+  CHECK(9);
+  CHECK(10);
+  CHECK(11);
+  CHECK(15);
+  CHECK(16);
+  CHECK(31);
+  CHECK(99);
+  CHECK(100);
+  CHECK(101);
+  CHECK(127);
+  CHECK(128);
+  CHECK(998);
+  CHECK(999);
+  CHECK(1000);
+  CHECK(1001);
+  CHECK(1023);
+  CHECK(1024);
+  CHECK(9998);
+  CHECK(9999);
+  CHECK(10000);
+  CHECK(10001);
+  CHECK(32767);
+  CHECK(32768);
+  CHECK(65535);
+#endif
+}
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/ultobcd.c sdcc-4.2.0+dfsg/support/regression/tests/ultobcd.c
--- sdcc-4.0.0+dfsg/support/regression/tests/ultobcd.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/ultobcd.c	2020-07-15 09:41:13.000000000 +0000
@@ -0,0 +1,42 @@
+/*
+   ultobcd.c
+*/
+
+#include 
+#include 
+
+extern void __ultobcd (unsigned long v, unsigned char r[5]);
+#define CHECK(v)              \
+    do {                      \
+        static const unsigned char u[5] = { 0x##v % 0x100, (0x##v / 0x100) % 0x100, (0x##v / 0x10000) % 0x100, (0x##v / 0x1000000) % 0x100, (0x##v / 0x100000000) % 0x100 }; \
+        unsigned char r[5] = { 0xff, 0xff, 0xff, 0xff, 0xff };   \
+        __ultobcd (v, r);     \
+        unsigned long bcd = r[4] * 0x100000000 + r[3] * 0x1000000 + r[2] * 0x10000 + r[1] * 0x100 + r[0]; \
+        ASSERT ((#v,(r[0]==u[0]&&r[1]==u[1]&&r[2]==u[2]&&r[3]==u[3]&&r[4]==u[4]))); \
+    } while (0)
+
+void test__ultobcd (void)
+{
+#if defined(__SDCC_z80)
+  CHECK(0);
+  CHECK(1);
+  CHECK(2);
+  CHECK(9);
+  CHECK(10);
+  CHECK(11);
+  CHECK(15);
+  CHECK(16);
+  CHECK(100000);
+  CHECK(345678);
+  CHECK(2345678);
+  CHECK(12345678);
+  CHECK(16777215);   //0x00ffffff
+  CHECK(234567890);
+  CHECK(2147483647); //0x7fffffff
+  CHECK(2147483648); //0x80000000
+  CHECK(3000000000);
+  CHECK(3999999999);
+  CHECK(4000000000);
+  CHECK(4294967295); //0xffffffff
+#endif
+}
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/wchar.c sdcc-4.2.0+dfsg/support/regression/tests/wchar.c
--- sdcc-4.0.0+dfsg/support/regression/tests/wchar.c	2019-09-24 20:05:59.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/wchar.c	2021-06-21 14:47:22.000000000 +0000
@@ -1,4 +1,5 @@
 /* Tests wide character conversion functions.
+test: wcharnorestart, wcharstringnorestart, wcharrestart, char16restart, char32restart
  */
 #include 
 
@@ -24,10 +25,13 @@
 #endif
 #endif
 
+#define TEST_{test}
+
+#ifdef TEST_wcharnorestart
 static void
-testwcharnorestart(void)
+wcharnorestart(void)
 {
-#if defined(__STDC_VERSION__) && __STDC_VERSION__ >= 199409L && !(defined(__SDCC_mcs51) && defined(__SDCC_MODEL_SMALL)) && !defined(__SDCC_pdk14) // Not enough memory
+#if defined(__STDC_VERSION__) && __STDC_VERSION__ >= 199409L && !defined(__SDCC_pdk14) // Not enough memory
 #if !(defined (__SDCC_pdk15) && defined(__SDCC_STACK_AUTO)) // Lack of code memory
 	wchar_t w;
 	char c[MB_LEN_MAX];
@@ -50,11 +54,13 @@
 #endif
 #endif
 }
+#endif
 
+#ifdef TEST_wcharstringnorestart
 static void
-testwcharstringnorestart(void)
+wcharstringnorestart(void)
 {
-#if defined(__STDC_VERSION__) && __STDC_VERSION__ >= 199409L && !(defined(__SDCC_mcs51) && (defined(__SDCC_MODEL_SMALL) || defined(__SDCC_MODEL_MEDIUM))) && !defined(__SDCC_pdk14) && !defined(__SDCC_pdk15) // Not enough memory
+#if defined(__STDC_VERSION__) && __STDC_VERSION__ >= 199409L && !defined(__SDCC_pdk14) && !defined(__SDCC_pdk15) // Not enough memory
 	wchar_t wcs1[5] = L"Test";
 	wchar_t wcs2[5];
 	char mbs[5 * MB_LEN_MAX];
@@ -67,7 +73,9 @@
 	ASSERT(wcs2[3] == L't');
 	ASSERT(!wcscmp(wcs1, wcs2));
 
-#if !(defined (__GNUC__) && defined (__GNUC_MINOR__) && ((__GNUC__ < 5) || (__GNUC__ == 5 && __GNUC_MINOR__ < 5)))
+// glibc with _FORTIFY_SOURCE == 2 is not standard-compliant (and fails the tests below)
+// However, Ubuntu decided to make _FORTIFY_SOURCE = 2 the default for GCC.
+#if !(defined(__GNUC__) && _FORTIFY_SOURCE == 2)
 	// Test for 0-terminated strings
 	ASSERT(wcstombs(mbs, wcs1, 1000) > 0);
 	ASSERT(mbstowcs(wcs2, mbs, 1000) > 0);
@@ -83,12 +91,14 @@
 	ASSERT(!wcscmp(L"Te", wcs2));
 #endif
 }
+#endif
 
+#ifdef TEST_wcharrestart
 static void
-testwcharrestart(void)
+wcharrestart(void)
 {
 #if !defined( __SDCC_pdk14) && !defined( __SDCC_pdk15) // Lack of memory
-#if defined(__STDC_VERSION__) && __STDC_VERSION__ >= 201112L && !(defined(__SDCC_mcs51) && defined(__SDCC_MODEL_SMALL))
+#if defined(__STDC_VERSION__) && __STDC_VERSION__ >= 201112L
 	static mbstate_t ps;
 	wchar_t w;
 	char c[MB_LEN_MAX];
@@ -109,9 +119,11 @@
 #endif
 #endif
 }
+#endif
 
+#ifdef TEST_char16restart
 static void
-testchar16restart(void)
+char16restart(void)
 {
 #if !defined( __SDCC_pdk14) && !defined( __SDCC_pdk15) // Lack of memory
 #if defined(__STDC_VERSION__) && __STDC_VERSION__ >= 201112L && !(defined(__SDCC_mcs51) && defined(__SDCC_MODEL_SMALL))
@@ -134,7 +146,7 @@
 	errno = 0;
 	ASSERT(c16rtomb(c, u'\0', 0) == 1);    // Converting a 0 character resets internal state.
 
-#ifdef __SDCC // The stadnard was defective (fixed in C2X). SDCC always behaves according to the fixed standard.
+#ifdef __SDCC // The standard was defective (fixed in C2X). SDCC always behaves according to the fixed standard.
 	ASSERT(c16rtomb(c, 0xd800, 0) == 0);
 	ASSERT(c16rtomb(c, 0xd800, 0) == -1);  // Invalid: Unpaired UTF-16 surrogate.
 
@@ -146,12 +158,14 @@
 #endif
 #endif
 }
+#endif
 
+#ifdef TEST_char32restart
 static void
-testchar32restart(void)
+char32restart(void)
 {
 #if !defined( __SDCC_pdk14) && !defined( __SDCC_pdk15) // Lack of memory
-#if defined(__STDC_VERSION__) && __STDC_VERSION__ >= 201112L && !(defined(__SDCC_mcs51) && defined(__SDCC_MODEL_SMALL))
+#if defined(__STDC_VERSION__) && __STDC_VERSION__ >= 201112L
 	static mbstate_t ps;
 	char32_t c32[2];
 	char c[MB_LEN_MAX];
@@ -164,4 +178,10 @@
 #endif
 #endif
 }
+#endif
 
+static void
+testwchar(void)
+{
+	{test}();
+}
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/z80n-push-nn.c sdcc-4.2.0+dfsg/support/regression/tests/z80n-push-nn.c
--- sdcc-4.0.0+dfsg/support/regression/tests/z80n-push-nn.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/z80n-push-nn.c	2021-09-25 12:02:20.000000000 +0000
@@ -0,0 +1,55 @@
+/* z80n-push-nn
+   Invalid relocation of Z80N PUSH nn instruction value
+ */
+#include 
+#include 
+
+int x;
+typedef void* (*memcpy_p)(void *d, const void *s, size_t c);
+
+#ifdef __SDCC_z80n
+int f(void) __naked
+{
+    __asm
+	push	#0x1234
+	push	#_x
+	pop	hl
+	pop	de
+	ld	a, (hl)
+	inc	hl
+	ld	h, (hl)
+	ld	l, a
+	add	hl, de
+	ex	de, hl
+	ret
+;
+	.db	#>_x, #<_x
+	.dw	#_x
+    __endasm;
+}
+memcpy_p g(void) __naked
+{
+    __asm
+	push	#_memcpy
+	pop	de
+	ret
+    __endasm;
+}
+#else
+int f(void)
+{
+    return x + 0x1234;
+}
+memcpy_p g(void)
+{
+    return &memcpy;
+}
+#endif
+
+void testBug3032(void)
+{
+    x = 0x7531;
+    ASSERT (f() == 0x8765);
+    ASSERT (g() == &memcpy);
+}
+
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/z88dk.c sdcc-4.2.0+dfsg/support/regression/tests/z88dk.c
--- sdcc-4.0.0+dfsg/support/regression/tests/z88dk.c	2019-04-16 10:04:43.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/z88dk.c	2022-01-09 00:53:30.000000000 +0000
@@ -4,15 +4,6 @@
 #include 
 
 #ifndef __SDCC_pdk14
-#if !defined(__SDCC_z80) && !defined(__SDCC_z180) && !defined(__SDCC_r2k) && !defined(__SDCC_r3ka) && !defined(__SDCC_tlcs90) && !defined(__SDCC_ez80_z80)
-#define __z88dk_fastcall
-#define __z88dk_callee
-#endif
-#if !defined(__SDCC_z80) && !defined(__SDCC_z180) && !defined(__SDCC_r2k) && !defined(__SDCC_r3ka) && !defined(__SDCC_tlcs90) && !defined(__SDCC_ez80_z80)
-#define __smallc
-#endif
-
-/* __z88dk_fastcall is supported both on the caller and the callee side */
 
 unsigned char f1(unsigned char c) __z88dk_fastcall
 {
@@ -24,7 +15,7 @@
 	return c + 1;
 }
 
-#if !defined(__SDCC_hc08) && !defined(__SDCC_s08)
+#if !defined(__SDCC_hc08) && !defined(__SDCC_s08) && !defined(__SDCC_mos6502) && !defined(__SDCC_mos65c02)
 unsigned long int f4(unsigned long int c) __z88dk_fastcall
 #else
 unsigned long int f4(unsigned long int c) __z88dk_fastcall __reentrant
@@ -35,14 +26,12 @@
 
 unsigned char (*p1)(unsigned char) __z88dk_fastcall;
 unsigned int (*p2)(unsigned int) __z88dk_fastcall;
-#if !defined(__SDCC_hc08) && !defined(__SDCC_s08)
+#if !defined(__SDCC_hc08) && !defined(__SDCC_s08) && !defined(__SDCC_mos6502) && !defined(__SDCC_mos65c02)
 unsigned long int (*p4)(unsigned long int) __z88dk_fastcall;
 #else
 unsigned long int (*p4)(unsigned long int) __z88dk_fastcall __reentrant;
 #endif
 
-/* __z88dk_callee is currently only supported on the caller side */
-
 void s1(int x, int y) __smallc;
 
 void s2(int x, int y) __z88dk_callee;
diff -Nru sdcc-4.0.0+dfsg/support/regression/tests/z88dk_callee.c sdcc-4.2.0+dfsg/support/regression/tests/z88dk_callee.c
--- sdcc-4.0.0+dfsg/support/regression/tests/z88dk_callee.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/regression/tests/z88dk_callee.c	2022-01-09 00:53:30.000000000 +0000
@@ -0,0 +1,75 @@
+/** z88dk.c
+*/
+#include 
+#include 
+
+unsigned char f1(unsigned char c) __z88dk_callee
+{
+	return c + 1;
+}
+
+unsigned int f2(unsigned int c) __z88dk_callee
+{
+	return c + 1;
+}
+
+unsigned int f3(unsigned char c, unsigned char d) __z88dk_callee __smallc __reentrant
+{
+	return c + d;
+}
+
+#if !defined(__SDCC_hc08) && !defined(__SDCC_s08) && !defined(__SDCC_mos6502) && !defined(__SDCC_mos65c02)
+unsigned long int f4(unsigned long int c) __z88dk_callee
+#else
+unsigned long int f4(unsigned long int c) __z88dk_callee __reentrant
+#endif
+{
+	return c + 1;
+}
+
+unsigned char (*p1)(unsigned char) __z88dk_callee;
+unsigned int (*p2)(unsigned int) __z88dk_callee;
+unsigned int (*p3)(unsigned char, unsigned char) __z88dk_callee __smallc __reentrant;
+#if !defined(__SDCC_hc08) && !defined(__SDCC_s08) && !defined(__SDCC_mos6502) && !defined(__SDCC_mos65c02)
+unsigned long int (*p4)(unsigned long int) __z88dk_callee;
+#else
+unsigned long int (*p4)(unsigned long int) __z88dk_callee __reentrant;
+#endif
+
+int j;
+
+void g0(void)
+{
+	j++;
+}
+
+void g1(int i) __z88dk_callee
+{
+	j = i;
+	g0(); // Tail call optimization needs to do extra work here, to avoid skipping stack cleanup.
+}
+
+void
+testZ88dk(void)
+{
+#if !defined(__SDCC_pdk14) && !defined(__SDCC_pdk15)
+  ASSERT (f1 (23) == 24);
+  ASSERT (f2 (23) == 24);
+  ASSERT (f3 (23, 42) == 65);
+  ASSERT (f4 (23) == 24);
+
+  p1 = &f1;
+  p2 = &f2;
+  p3 = &f3;
+  p4 = &f4;
+
+  ASSERT ((*p1) (23) == 24);
+  ASSERT ((*p2) (23) == 24);
+  ASSERT ((*p3) (23, 42) == 65);
+  ASSERT ((*p4) (23) == 24);
+#endif
+
+  g1(1);
+  ASSERT (j == 2);
+}
+
Binary files /tmp/tmpfj_tdy7x/FvGPWZvfhF/sdcc-4.0.0+dfsg/support/scripts/sdcc.ico and /tmp/tmpfj_tdy7x/HU37cAdXJL/sdcc-4.2.0+dfsg/support/scripts/sdcc.ico differ
diff -Nru sdcc-4.0.0+dfsg/support/scripts/sdcc.nsi sdcc-4.2.0+dfsg/support/scripts/sdcc.nsi
--- sdcc-4.0.0+dfsg/support/scripts/sdcc.nsi	2019-11-02 10:10:02.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/scripts/sdcc.nsi	2022-02-06 12:57:13.000000000 +0000
@@ -386,6 +386,7 @@
   File "${SDCC_ROOT}\bin\sdaspdk14.exe"
   File "${SDCC_ROOT}\bin\sdaspdk15.exe"
   File "${SDCC_ROOT}\bin\sdastlcs90.exe"
+  File "${SDCC_ROOT}\bin\sdas6500.exe"
   File "${SDCC_ROOT}\bin\sdld.exe"
   File "${SDCC_ROOT}\bin\sdldgb.exe"
   File "${SDCC_ROOT}\bin\sdld6808.exe"
@@ -442,8 +443,8 @@
   File "${DEV_ROOT}\include\asm\default\features.h"
   SetOutPath "$INSTDIR\include\asm\ds390"
   File "${DEV_ROOT}\include\asm\ds390\features.h"
-  SetOutPath "$INSTDIR\include\asm\gbz80"
-  File "${DEV_ROOT}\include\asm\gbz80\features.h"
+  SetOutPath "$INSTDIR\include\asm\sm83"
+  File "${DEV_ROOT}\include\asm\sm83\features.h"
   SetOutPath "$INSTDIR\include\asm\mcs51"
   File "${DEV_ROOT}\include\asm\mcs51\features.h"
   SetOutPath "$INSTDIR\include\asm\pic14"
@@ -452,14 +453,10 @@
   File "${DEV_ROOT}\include\asm\pic16\features.h"
   SetOutPath "$INSTDIR\include\asm\z80"
   File "${DEV_ROOT}\include\asm\z80\features.h"
-  SetOutPath "$INSTDIR\include\asm\z180"
-  File "${DEV_ROOT}\include\asm\z180\features.h"
   SetOutPath "$INSTDIR\include\asm\r2k"
   File "${DEV_ROOT}\include\asm\r2k\features.h"
   SetOutPath "$INSTDIR\include\asm\r3ka"
   File "${DEV_ROOT}\include\asm\r3ka\features.h"
-  SetOutPath "$INSTDIR\include\asm\ez80_z80"
-  File "${DEV_ROOT}\include\asm\ez80_z80\features.h"
   SetOutPath "$INSTDIR\include\asm\stm8"
   File "${DEV_ROOT}\include\asm\stm8\features.h"
 
@@ -502,10 +499,10 @@
   File "${DEV_ROOT}\lib\ds400\*.*"
 ${SectionEnd}
 
-${Section} "SDCC GBZ80 library" SEC08
+${Section} "SDCC SM83 library" SEC08
   SectionIn 1 2
-  SetOutPath "$INSTDIR\lib\gbz80"
-  File "${DEV_ROOT}\lib\gbz80\*.*"
+  SetOutPath "$INSTDIR\lib\sm83"
+  File "${DEV_ROOT}\lib\sm83\*.*"
 ${SectionEnd}
 
 ${Section} "SDCC Z180 library" SEC09
@@ -624,9 +621,9 @@
   File "${DEV_ROOT}\lib\src\ds400\*.c"
 #  File "${DEV_ROOT}\lib\src\ds400\Makefile"
 
-  SetOutPath "$INSTDIR\lib\src\gbz80"
-  File "${DEV_ROOT}\lib\src\gbz80\*.s"
-#  File "${DEV_ROOT}\lib\src\gbz80\Makefile"
+  SetOutPath "$INSTDIR\lib\src\sm83"
+  File "${DEV_ROOT}\lib\src\sm83\*.s"
+#  File "${DEV_ROOT}\lib\src\sm83\Makefile"
 
   SetOutPath "$INSTDIR\lib\src\z80"
   File "${DEV_ROOT}\lib\src\z80\*.s"
@@ -655,6 +652,14 @@
   SetOutPath "$INSTDIR\lib\src\stm8"
 #  File "${DEV_ROOT}\lib\src\stm8\Makefile"
 
+  SetOutPath "$INSTDIR\lib\src\tlcs90"
+  File "${DEV_ROOT}\lib\src\tlcs90\*.s"
+#  File "${DEV_ROOT}\lib\src\tlcs90\Makefile"
+
+  SetOutPath "$INSTDIR\lib\src\mos6502"
+  File "${DEV_ROOT}\lib\src\mos6502\*.s"
+#  File "${DEV_ROOT}\lib\src\mos6502\Makefile"
+
   SetOutPath "$INSTDIR\lib\src\mcs51"
   File "${DEV_ROOT}\lib\src\mcs51\*.asm"
 #  File "${DEV_ROOT}\lib\src\mcs51\Makefile"
@@ -856,6 +861,23 @@
   File "${DEV_ROOT}\lib\pdk15-stack-auto\*.*"
 ${SectionEnd}
 
+${Section} "SDCC Z80N library" SEC32
+  SectionIn 1 2
+  SetOutPath "$INSTDIR\lib\z80n"
+  File "${DEV_ROOT}\lib\z80n\*.*"
+${SectionEnd}
+
+${Section} "SDCC Rabbit 2000A library" SEC33
+  SectionIn 1 2
+  SetOutPath "$INSTDIR\lib\r2ka"
+  File "${DEV_ROOT}\lib\r2ka\*.*"
+${SectionEnd}
+
+${Section} "SDCC MOS 6502 library" SEC34
+  SectionIn 1 2
+  SetOutPath "$INSTDIR\lib\mos6502"
+  File "${DEV_ROOT}\lib\mos6502\*.*"
+${SectionEnd}
 
 ;--------------------------------
 ;Descriptions
@@ -868,7 +890,7 @@
 LangString DESC_SEC05 ${LANG_ENGLISH} "SDCC include files"
 LangString DESC_SEC06 ${LANG_ENGLISH} "SDCC DS390 library"
 LangString DESC_SEC07 ${LANG_ENGLISH} "SDCC DS400 library"
-LangString DESC_SEC08 ${LANG_ENGLISH} "SDCC GBZ80 library"
+LangString DESC_SEC08 ${LANG_ENGLISH} "SDCC SM83 library"
 LangString DESC_SEC09 ${LANG_ENGLISH} "SDCC Z180 library"
 LangString DESC_SEC10 ${LANG_ENGLISH} "SDCC Rabbit 2000 library"
 LangString DESC_SEC11 ${LANG_ENGLISH} "SDCC Rabbit 3000A library"
@@ -892,6 +914,9 @@
 LangString DESC_SEC29 ${LANG_ENGLISH} "SDCC PDK14 library"
 LangString DESC_SEC30 ${LANG_ENGLISH} "SDCC PDK15 library"
 LangString DESC_SEC31 ${LANG_ENGLISH} "SDCC PDK15 stack-auto library"
+LangString DESC_SEC32 ${LANG_ENGLISH} "SDCC Z80N library"
+LangString DESC_SEC33 ${LANG_ENGLISH} "SDCC Rabbit 2000A library"
+LangString DESC_SEC34 ${LANG_ENGLISH} "SDCC MOS 6502 library"
 
 ;Assign language strings to sections
 !insertmacro MUI_FUNCTION_DESCRIPTION_BEGIN
@@ -922,6 +947,15 @@
   !insertmacro MUI_DESCRIPTION_TEXT ${SEC26} $(DESC_SEC26)
   !insertmacro MUI_DESCRIPTION_TEXT ${SEC24} $(DESC_SEC24)
   !insertmacro MUI_DESCRIPTION_TEXT ${SEC25} $(DESC_SEC25)
+  !insertmacro MUI_DESCRIPTION_TEXT ${SEC16} $(DESC_SEC26)
+  !insertmacro MUI_DESCRIPTION_TEXT ${SEC17} $(DESC_SEC27)
+  !insertmacro MUI_DESCRIPTION_TEXT ${SEC18} $(DESC_SEC28)
+  !insertmacro MUI_DESCRIPTION_TEXT ${SEC19} $(DESC_SEC29)
+  !insertmacro MUI_DESCRIPTION_TEXT ${SEC20} $(DESC_SEC30)
+  !insertmacro MUI_DESCRIPTION_TEXT ${SEC31} $(DESC_SEC31)
+  !insertmacro MUI_DESCRIPTION_TEXT ${SEC32} $(DESC_SEC32)
+  !insertmacro MUI_DESCRIPTION_TEXT ${SEC33} $(DESC_SEC33)
+  !insertmacro MUI_DESCRIPTION_TEXT ${SEC34} $(DESC_SEC34)
 !insertmacro MUI_FUNCTION_DESCRIPTION_END
 ;--------------------------------
 
@@ -999,6 +1033,8 @@
 
   RMDir "$SMPROGRAMS\$MUI_STARTMENUPAGE_VARIABLE"
 
+  Delete "$INSTDIR\lib\src\huge\Makefile"
+
   Delete "$INSTDIR\lib\src\large\Makefile"
 
   Delete "$INSTDIR\lib\src\medium\Makefile"
@@ -1033,17 +1069,19 @@
   Delete "$INSTDIR\lib\src\z180\README"
   Delete "$INSTDIR\lib\src\z180\Makefile"
 
-  Delete "$INSTDIR\lib\src\gbz80\*.s"
-  Delete "$INSTDIR\lib\src\gbz80\gbz80.lib"
-  Delete "$INSTDIR\lib\src\gbz80\README"
-  Delete "$INSTDIR\lib\src\gbz80\Makefile"
+  Delete "$INSTDIR\lib\src\sm83\*.s"
+  Delete "$INSTDIR\lib\src\sm83\sm83.lib"
+  Delete "$INSTDIR\lib\src\sm83\README"
+  Delete "$INSTDIR\lib\src\sm83\Makefile"
 
   Delete "$INSTDIR\lib\src\r2k\*.s"
 
+  Delete "$INSTDIR\lib\src\r2ka\*.s"
+
   Delete "$INSTDIR\lib\src\r3ka\*.s"
 
   Delete "$INSTDIR\lib\src\ez80_z80\*.s"
-  Delete "$INSTDIR\lib\src\ez80_z80\z80.lib"
+  Delete "$INSTDIR\lib\src\ez80_z80\ez80_z80.lib"
   Delete "$INSTDIR\lib\src\ez80_z80\README"
   Delete "$INSTDIR\lib\src\ez80_z80\Makefile"
 
@@ -1070,6 +1108,20 @@
   Delete "$INSTDIR\lib\src\pdk15-stack-auto\pdk15.lib"
   Delete "$INSTDIR\lib\src\pdk15-stack-auto\Makefile"
 
+  Delete "$INSTDIR\lib\src\tlcs90\*.s"
+  Delete "$INSTDIR\lib\src\tlcs90\tlcs90.lib"
+  Delete "$INSTDIR\lib\src\tlcs90\README"
+  Delete "$INSTDIR\lib\src\tlcs90\Makefile"
+
+  Delete "$INSTDIR\lib\src\mos6502\*.s"
+  Delete "$INSTDIR\lib\src\mos6502\mos6502.lib"
+  Delete "$INSTDIR\lib\src\mos6502\Makefile"
+
+  Delete "$INSTDIR\lib\src\z80n\*.s"
+  Delete "$INSTDIR\lib\src\z80n\z80n.lib"
+  Delete "$INSTDIR\lib\src\z80n\README"
+  Delete "$INSTDIR\lib\src\z80n\Makefile"
+
   Delete "$INSTDIR\lib\src\*.c"
 
   Delete "$INSTDIR\lib\pic14\*.lib"
@@ -1098,6 +1150,9 @@
   Delete "$INSTDIR\lib\r2k\*.rel"
   Delete "$INSTDIR\lib\r2k\*.lib"
 
+  Delete "$INSTDIR\lib\r2ka\*.rel"
+  Delete "$INSTDIR\lib\r2ka\*.lib"
+
   Delete "$INSTDIR\lib\r3ka\*.rel"
   Delete "$INSTDIR\lib\r3ka\*.lib"
 
@@ -1110,11 +1165,13 @@
 
   Delete "$INSTDIR\lib\large\*.lib"
 
+  Delete "$INSTDIR\lib\huge\*.lib"
+
   Delete "$INSTDIR\lib\small-stack-auto\*.lib"
   Delete "$INSTDIR\lib\large-stack-auto\*.lib"
 
-  Delete "$INSTDIR\lib\gbz80\*.rel"
-  Delete "$INSTDIR\lib\gbz80\*.lib"
+  Delete "$INSTDIR\lib\sm83\*.rel"
+  Delete "$INSTDIR\lib\sm83\*.lib"
 
   Delete "$INSTDIR\lib\ds390\*.lib"
 
@@ -1128,15 +1185,22 @@
 
   Delete "$INSTDIR\lib\pdk15-stack-auto\*.lib"
 
+  Delete "$INSTDIR\lib\tlcs90\*.rel"
+  Delete "$INSTDIR\lib\tlcs90\*.lib"
+
+  Delete "$INSTDIR\lib\mos6502\*.rel"
+  Delete "$INSTDIR\lib\mos6502\*.lib"
+
+  Delete "$INSTDIR\lib\z80n\*.rel"
+  Delete "$INSTDIR\lib\z80n\*.lib"
+
   Delete "$INSTDIR\include\asm\z80\*.h"
-  Delete "$INSTDIR\include\asm\z180\*.h"
   Delete "$INSTDIR\include\asm\r2k\*.h"
   Delete "$INSTDIR\include\asm\r3ka\*.h"
-  Delete "$INSTDIR\include\asm\ez80_z80\*.h"
   Delete "$INSTDIR\include\asm\pic16\*.h"
   Delete "$INSTDIR\include\asm\pic14\*.h"
   Delete "$INSTDIR\include\asm\mcs51\*.h"
-  Delete "$INSTDIR\include\asm\gbz80\*.h"
+  Delete "$INSTDIR\include\asm\sm83\*.h"
   Delete "$INSTDIR\include\asm\ds390\*.h"
   Delete "$INSTDIR\include\asm\stm8\*.h"
   Delete "$INSTDIR\include\asm\default\*.h"
@@ -1170,6 +1234,7 @@
   Delete "$INSTDIR\bin\sdaspdk14.exe"
   Delete "$INSTDIR\bin\sdaspdk15.exe"
   Delete "$INSTDIR\bin\sdastlcs90.exe"
+  Delete "$INSTDIR\bin\sdas6500.exe"
   Delete "$INSTDIR\bin\sdld.exe"
   Delete "$INSTDIR\bin\sdldgb.exe"
   Delete "$INSTDIR\bin\sdld6808.exe"
@@ -1214,11 +1279,13 @@
   RMDir "$INSTDIR\lib\src\small"
   RMDir "$INSTDIR\lib\src\medium"
   RMDir "$INSTDIR\lib\src\large"
+  RMDir "$INSTDIR\lib\src\huge"
   RMDir "$INSTDIR\lib\src\mcs51"
   RMDir "$INSTDIR\lib\src\z80"
   RMDir "$INSTDIR\lib\src\z180"
-  RMDir "$INSTDIR\lib\src\gbz80"
+  RMDir "$INSTDIR\lib\src\sm83"
   RMDir "$INSTDIR\lib\src\r2k"
+  RMDir "$INSTDIR\lib\src\r2ka"
   RMDir "$INSTDIR\lib\src\r3ka"
   RMDir "$INSTDIR\lib\src\ez80_z80"
   RMDir "$INSTDIR\lib\src\ds390\examples"
@@ -1232,6 +1299,9 @@
   RMDir "$INSTDIR\lib\src\pdk14"
   RMDir "$INSTDIR\lib\src\pdk15"
   RMDir "$INSTDIR\lib\src\pdk15-stack-auto"
+  RMDir "$INSTDIR\lib\src\tlcs90"
+  RMDir "$INSTDIR\lib\src\mos6502"
+  RMDir "$INSTDIR\lib\src\z80n"
   RMDir "$INSTDIR\lib\src"
   RMDir "$INSTDIR\non-free\lib\src"
 
@@ -1242,14 +1312,16 @@
   RMDir "$INSTDIR\lib\z80"
   RMDir "$INSTDIR\lib\z180"
   RMDir "$INSTDIR\lib\r2k"
+  RMDir "$INSTDIR\lib\r2ka"
   RMDir "$INSTDIR\lib\r3ka"
   RMDir "$INSTDIR\lib\ez80_z80"
   RMDir "$INSTDIR\lib\small"
   RMDir "$INSTDIR\lib\medium"
   RMDir "$INSTDIR\lib\large"
+  RMDir "$INSTDIR\lib\huge"
   RMDir "$INSTDIR\lib\small-stack-auto"
   RMDir "$INSTDIR\lib\large-stack-auto"
-  RMDir "$INSTDIR\lib\gbz80"
+  RMDir "$INSTDIR\lib\sm83"
   RMDir "$INSTDIR\lib\ds390"
   RMDir "$INSTDIR\lib\ds400"
   RMDir "$INSTDIR\lib\hc08"
@@ -1260,20 +1332,21 @@
   RMDir "$INSTDIR\lib\pdk14"
   RMDir "$INSTDIR\lib\pdk15"
   RMDir "$INSTDIR\lib\pdk15-stack-auto"
+  RMDir "$INSTDIR\lib\tlcs90"
+  RMDir "$INSTDIR\lib\mos6502"
+  RMDir "$INSTDIR\lib\z80n"
   RMDir "$INSTDIR\lib"
   RMDir "$INSTDIR\non-free\lib"
 
   RMDir "$INSTDIR\include\asm\z80"
-  RMDir "$INSTDIR\include\asm\z180"
   RMDir "$INSTDIR\include\asm\r2k"
   RMDir "$INSTDIR\include\asm\r3ka"
-  RMDir "$INSTDIR\include\asm\ez80_z80"
   RMDir "$INSTDIR\include\asm\pic16"
   RMDir "$INSTDIR\non-free\include\asm\pic16"
   RMDir "$INSTDIR\include\asm\pic14"
   RMDir "$INSTDIR\non-free\include\asm\pic14"
   RMDir "$INSTDIR\include\asm\mcs51"
-  RMDir "$INSTDIR\include\asm\gbz80"
+  RMDir "$INSTDIR\include\asm\sm83"
   RMDir "$INSTDIR\include\asm\ds390"
   RMDir "$INSTDIR\include\asm\stm8"
   RMDir "$INSTDIR\include\asm\default"
diff -Nru sdcc-4.0.0+dfsg/support/sdbinutils/binutils/bfdtest2.c sdcc-4.2.0+dfsg/support/sdbinutils/binutils/bfdtest2.c
--- sdcc-4.0.0+dfsg/support/sdbinutils/binutils/bfdtest2.c	2018-03-18 17:46:53.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/sdbinutils/binutils/bfdtest2.c	2022-02-08 20:31:38.000000000 +0000
@@ -1,106 +1,106 @@
-/* A program to test BFD.
+/* A program to test BFD.
    Copyright (C) 2012-2018 Free Software Foundation, Inc.
-
-   This file is part of the GNU Binutils.
-
-   This program is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 3 of the License, or
-   (at your option) any later version.
-
-   This program is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-   GNU General Public License for more details.
-
-   You should have received a copy of the GNU General Public License
-   along with this program; if not, write to the Free Software
-   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
-   MA 02110-1301, USA.  */
-
-#include "sysdep.h"
-#include "bfd.h"
-
-static void
-die (const char *s)
-{
-  printf ("oops: %s\n", s);
-  exit (1);
-}
-
-static void *
-iovec_open (struct bfd *nbfd ATTRIBUTE_UNUSED, void *open_closure)
-{
-  return open_closure;
-}
-
-static file_ptr iovec_read (struct bfd *nbfd ATTRIBUTE_UNUSED,
-			    void *stream, void *buf, file_ptr nbytes,
-			    file_ptr offset)
-{
-  FILE* file = (FILE*) stream;
-
-  if (fseek(file, offset, SEEK_SET) != 0)
-    die ("fseek error");
-
-  return fread (buf, 1, nbytes, file);
-}
-
-static int
-iovec_stat (struct bfd *abfd ATTRIBUTE_UNUSED, 
-	    void *stream, struct stat *sb)
-{
-  return fstat (fileno ((FILE*) stream), sb);
-}
-
-static bfd_boolean
-check_format_any (struct bfd *abfd, bfd_format format)
-{
-  char** targets = NULL;
-
-  if (bfd_check_format_matches (abfd, format, &targets))
-    return TRUE;
-
-  if (targets)
-    {
-      bfd_find_target (targets[0], abfd);
-
-      return bfd_check_format (abfd, format);
-    }
-
-  return FALSE;
-}
-
-int
-main (int argc, const char** argv)
-{
-  FILE* file;
-  bfd *abfd, *mbfd;
-
-  if (argc < 2)
-    die ("Usage: test archivefile");
-
-  file = fopen(argv[1], "rb");
-  if (!file)
-    die ("file not found");
-
-  abfd = bfd_openr_iovec (argv[1], 0, iovec_open, file,
-			  iovec_read, NULL, iovec_stat);
-  if (!abfd)
-    die ("error opening file");
-
-  if (!check_format_any (abfd, bfd_archive))
-    die ("not an archive");
-
-  mbfd = bfd_openr_next_archived_file (abfd, 0);
-  if (!mbfd)
-    die ("error opening archive member");
-
-  if (!bfd_close (mbfd))
-    die ("error closing archive member");
-
-  if (!bfd_close (abfd))
-    die ("error closing archive");
-
-  return 0;
-}
+
+   This file is part of the GNU Binutils.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#include "sysdep.h"
+#include "bfd.h"
+
+static void
+die (const char *s)
+{
+  printf ("oops: %s\n", s);
+  exit (1);
+}
+
+static void *
+iovec_open (struct bfd *nbfd ATTRIBUTE_UNUSED, void *open_closure)
+{
+  return open_closure;
+}
+
+static file_ptr iovec_read (struct bfd *nbfd ATTRIBUTE_UNUSED,
+			    void *stream, void *buf, file_ptr nbytes,
+			    file_ptr offset)
+{
+  FILE* file = (FILE*) stream;
+
+  if (fseek(file, offset, SEEK_SET) != 0)
+    die ("fseek error");
+
+  return fread (buf, 1, nbytes, file);
+}
+
+static int
+iovec_stat (struct bfd *abfd ATTRIBUTE_UNUSED, 
+	    void *stream, struct stat *sb)
+{
+  return fstat (fileno ((FILE*) stream), sb);
+}
+
+static bfd_boolean
+check_format_any (struct bfd *abfd, bfd_format format)
+{
+  char** targets = NULL;
+
+  if (bfd_check_format_matches (abfd, format, &targets))
+    return TRUE;
+
+  if (targets)
+    {
+      bfd_find_target (targets[0], abfd);
+
+      return bfd_check_format (abfd, format);
+    }
+
+  return FALSE;
+}
+
+int
+main (int argc, const char** argv)
+{
+  FILE* file;
+  bfd *abfd, *mbfd;
+
+  if (argc < 2)
+    die ("Usage: test archivefile");
+
+  file = fopen(argv[1], "rb");
+  if (!file)
+    die ("file not found");
+
+  abfd = bfd_openr_iovec (argv[1], 0, iovec_open, file,
+			  iovec_read, NULL, iovec_stat);
+  if (!abfd)
+    die ("error opening file");
+
+  if (!check_format_any (abfd, bfd_archive))
+    die ("not an archive");
+
+  mbfd = bfd_openr_next_archived_file (abfd, 0);
+  if (!mbfd)
+    die ("error opening archive member");
+
+  if (!bfd_close (mbfd))
+    die ("error closing archive member");
+
+  if (!bfd_close (abfd))
+    die ("error closing archive");
+
+  return 0;
+}
diff -Nru sdcc-4.0.0+dfsg/support/valdiag/Makefile.in sdcc-4.2.0+dfsg/support/valdiag/Makefile.in
--- sdcc-4.0.0+dfsg/support/valdiag/Makefile.in	2019-03-18 10:25:57.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/valdiag/Makefile.in	2022-02-12 16:50:17.000000000 +0000
@@ -10,7 +10,7 @@
 RESULTS_DIR = results
 PORTS_DIR = $(srcdir)/ports
 BUILD_DIR = gen
-ALL_PORTS = mcs51 mcs51-large mcs51-stack-auto ds390 z80 z180 r2k gbz80 tlcs90 hc08 s08 stm8 pdk14
+ALL_PORTS = mcs51 mcs51-large mcs51-stack-auto ds390 z80 z180 r2k sm83 tlcs90 hc08 s08 mos6502 stm8 pdk13 pdk14 pdk15
 
 ALL_TESTS = $(shell find $(TESTS_DIR) -name "*.c")
 
@@ -25,7 +25,7 @@
 
 test-mcs51:
 	$(MAKE) test-port PORT=mcs51
-        
+
 test-port: port-results
 
 clean: clean-gen
@@ -41,7 +41,7 @@
 clean-port:
 	rm -rf $(PORT_BUILD_DIR)
 
-$(PORT_RESULTS_DIR)/%.out: $(TESTS_DIR)/%.c
+$(PORT_RESULTS_DIR)/%.out: $(TESTS_DIR)/%.c port-dirs
 	$(PYTHON) $(srcdir)/valdiag.py $(PORT) $< $(PORT_BUILD_DIR)/$* $(srcdir)/../../device/include > $@
 	grep FAIL $@ ; true
 	cat $@ | $(PYTHON) $(srcdir)/../regression/compact-results.py
diff -Nru sdcc-4.0.0+dfsg/support/valdiag/tests/bug-2798.c sdcc-4.2.0+dfsg/support/valdiag/tests/bug-2798.c
--- sdcc-4.0.0+dfsg/support/valdiag/tests/bug-2798.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/valdiag/tests/bug-2798.c	2022-01-10 00:52:31.000000000 +0000
@@ -0,0 +1,22 @@
+/* bug-2798.c
+
+   z80 and pdk code generator do not support address of __sfr, but failed to warn
+ */
+
+#ifdef TEST1
+#if !defined(__SDCC_stm8) && !defined(__SDCC_hc08) && !defined(__SDCC_s08) && !defined(__SDCC_mos6502) && !defined(__SDCC_mos65c02) && !defined(__SDCC_tlcs90) && !defined(__SDCC_sm83) 
+__sfr __at 0x1234 x; /* IGNORE */
+
+unsigned char *foo(void)
+{
+    return &x; /* WARNING(SDCC_z80|SDCC_z180|SDCC_r2k|SDCC_r2ka|SDCC_r3ka|SDCC_pdk13|SDCC_pdk14|SDCC_pdk15) */
+}
+
+#endif
+
+void bar(void)
+{
+}
+
+#endif
+
diff -Nru sdcc-4.0.0+dfsg/support/valdiag/tests/bug-2984.c sdcc-4.2.0+dfsg/support/valdiag/tests/bug-2984.c
--- sdcc-4.0.0+dfsg/support/valdiag/tests/bug-2984.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/valdiag/tests/bug-2984.c	2020-03-22 10:30:53.000000000 +0000
@@ -0,0 +1,20 @@
+/* bug-2984.c
+
+   Missing diagnostic and crash on incomplete type in offsetof
+ */
+
+#ifdef TEST1
+#include 
+
+volatile unsigned char test1=0;
+volatile unsigned char test2=0;
+
+int f(void) {
+
+  test1=offsetof(struct test_t,v1); /* ERROR */
+  test2=offsetof(int,v1);           /* ERROR */
+
+  return 0;
+}
+#endif
+
diff -Nru sdcc-4.0.0+dfsg/support/valdiag/tests/bug-3009.c sdcc-4.2.0+dfsg/support/valdiag/tests/bug-3009.c
--- sdcc-4.0.0+dfsg/support/valdiag/tests/bug-3009.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/valdiag/tests/bug-3009.c	2020-06-03 10:40:47.000000000 +0000
@@ -0,0 +1,14 @@
+/* bug-3009.c
+
+   Segfault on expression that is not an integer constant.
+ */
+
+#ifdef TEST1
+int f();
+
+enum some_enum
+{
+val = f() /* ERROR */
+};
+#endif
+
diff -Nru sdcc-4.0.0+dfsg/support/valdiag/tests/bug-3010.c sdcc-4.2.0+dfsg/support/valdiag/tests/bug-3010.c
--- sdcc-4.0.0+dfsg/support/valdiag/tests/bug-3010.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/valdiag/tests/bug-3010.c	2021-04-23 16:05:49.000000000 +0000
@@ -0,0 +1,9 @@
+/* bug-3010.c
+
+   Segfault on invalid function declaration
+ */
+
+#ifdef TEST1
+int f(int)_; /* ERROR */
+#endif
+
diff -Nru sdcc-4.0.0+dfsg/support/valdiag/tests/bug-3011.c sdcc-4.2.0+dfsg/support/valdiag/tests/bug-3011.c
--- sdcc-4.0.0+dfsg/support/valdiag/tests/bug-3011.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/valdiag/tests/bug-3011.c	2020-06-05 08:42:57.000000000 +0000
@@ -0,0 +1,12 @@
+/* bug-3011.c
+
+   Crash on (not-yet-implemented as of mid-2020) compound literal.
+ */
+
+#ifdef TEST1
+void f()
+{
+    int *p = (int *){1}; /* IGNORE */
+}
+#endif
+
diff -Nru sdcc-4.0.0+dfsg/support/valdiag/tests/bug-3014.c sdcc-4.2.0+dfsg/support/valdiag/tests/bug-3014.c
--- sdcc-4.0.0+dfsg/support/valdiag/tests/bug-3014.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/valdiag/tests/bug-3014.c	2020-06-05 07:57:20.000000000 +0000
@@ -0,0 +1,9 @@
+/* bug-3014.c
+
+   Crash on incomplete semi-K&R function.
+ */
+
+#ifdef TEST1
+void *f(a) /* ERROR */
+#endif /* IGNORE */
+
diff -Nru sdcc-4.0.0+dfsg/support/valdiag/tests/bug-3043.c sdcc-4.2.0+dfsg/support/valdiag/tests/bug-3043.c
--- sdcc-4.0.0+dfsg/support/valdiag/tests/bug-3043.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/valdiag/tests/bug-3043.c	2020-06-12 21:33:57.000000000 +0000
@@ -0,0 +1,23 @@
+/* bug-3043.c
+
+   stm8 and pdk code generator hang on shift by negative literal
+ */
+
+#ifdef TEST1
+void g(void)
+{
+}
+
+void fr(int x)
+{
+  if (((x >> -1))) /* WARNING */
+    g();            /* IGNORE */
+}
+
+void fl(int x)
+{
+  if (((x << -1))) /* WARNING */
+    g();           /* IGNORE */
+}
+#endif
+
diff -Nru sdcc-4.0.0+dfsg/support/valdiag/tests/callingconvention.c sdcc-4.2.0+dfsg/support/valdiag/tests/callingconvention.c
--- sdcc-4.0.0+dfsg/support/valdiag/tests/callingconvention.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/valdiag/tests/callingconvention.c	2021-08-29 07:55:18.000000000 +0000
@@ -0,0 +1,66 @@
+
+#if defined(__SDCC) && defined(__has_sdcccall)
+#define SDCCCALL0  __sdcccall(0)
+#define SDCCCALL1  __sdcccall(1)
+#else
+#define SDCCCALL0
+#define SDCCCALL1
+#endif
+
+#if defined(__SDCC) && defined(__has_z88dk_fastcall)
+#define Z88DK_FASTCALL  __z88dk_fastcall
+#else
+#define Z88DK_FASTCALL
+#endif
+
+#if defined(__SDCC) && defined(__has_raisonance)
+#define RAISONANCE  __raisonance
+#else
+#define RAISONANCE
+#endif
+
+#ifdef TEST1
+int f(int i) SDCCCALL0;        /* IGNORE */
+int f(int i) SDCCCALL1 {       /* ERROR(__has_sdcccall) */
+  return i;
+}
+#endif
+
+#ifdef TEST2
+int f(int i) SDCCCALL1;        /* IGNORE */
+int f(int i) SDCCCALL0 {       /* ERROR(__has_sdcccall) */
+
+  return i;
+}
+#endif
+
+#ifdef TEST3
+int f(int i) Z88DK_FASTCALL;   /* IGNORE */
+int f(int i) {                 /* ERROR(__has_z88dk_fastcall) */
+  return i;
+}
+#endif
+
+#ifdef TEST4
+int f(int i);                  /* IGNORE */
+int f(int i) Z88DK_FASTCALL {  /* ERROR(__has_z88dk_fastcall) */
+
+  return i;
+}
+#endif
+
+#ifdef TEST5
+int f(int i) RAISONANCE;       /* IGNORE */
+int f(int i) {                 /* ERROR(__has_raisonance) */
+  return i;
+}
+#endif
+
+#ifdef TEST6
+int f(int i);                  /* IGNORE */
+int f(int i) RAISONANCE {      /* ERROR(__has_raisonance) */
+
+  return i;
+}
+#endif
+
diff -Nru sdcc-4.0.0+dfsg/support/valdiag/tests/enum.c sdcc-4.2.0+dfsg/support/valdiag/tests/enum.c
--- sdcc-4.0.0+dfsg/support/valdiag/tests/enum.c	2018-03-23 08:38:20.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/valdiag/tests/enum.c	2020-05-10 16:54:59.000000000 +0000
@@ -87,3 +87,11 @@
   third
 };
 #endif
+
+#ifdef TEST9
+enum comma
+{
+  first,
+  second,,	/* ERROR */
+}
+#endif
diff -Nru sdcc-4.0.0+dfsg/support/valdiag/tests/strings.c sdcc-4.2.0+dfsg/support/valdiag/tests/strings.c
--- sdcc-4.0.0+dfsg/support/valdiag/tests/strings.c	1970-01-01 00:00:00.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/valdiag/tests/strings.c	2020-12-03 20:32:27.000000000 +0000
@@ -0,0 +1,41 @@
+#include 
+#include 
+
+// Concatenation of string literals, some prefixed, all prefixed ones have same prefix. Allowed.
+#ifdef TEST1
+const char *str1 = u8"testu8" "test" u8"testu8";
+const char *str2 = u8"testu8" u8"testu8";
+const char *str3 = u8"testu8" u8"testu8" u8"testu8";
+const char16_t *str4 = u"testu8" "test";
+const char32_t *str5 = U"testu8" "test";
+#endif
+
+// Concatenation of string literals, some prefixed, prefixed have different prefixes. Implementation-defined in C11, C17. Requires diagnostic in C23.
+#ifdef TEST2
+const char *str1 = u8"testu8" "test" u"testu"; /* WARNING(SDCC) */ /* IGNORE(GCC) */
+#endif
+
+#ifdef TEST3
+const char *str1 = u8"testu8" "test" L"testL"; /* WARNING(SDCC) */ /* IGNORE(GCC) */
+#endif
+
+#ifdef TEST4
+const char *str1 = L"testuL" "test" u"testu"; /* WARNING(SDCC) */ /* IGNORE(GCC) */
+#endif
+
+#ifdef TEST5
+const char32_t *str1 = U"testU" "test" u"testu"; /* WARNING(SDCC) */ /* IGNORE(GCC) */
+#endif
+
+#ifdef TEST6
+const char32_t *str1 = U"testU" u"testu"; /* WARNING(SDCC) */ /* IGNORE(GCC) */
+#endif
+
+#ifdef TEST7
+const char32_t *str1 = U"testU" L"testL"; /* WARNING(SDCC) */ /* IGNORE(GCC) */
+#endif
+
+#ifdef TEST8
+const wchar_t *str1 = L"testL" u"testu"; /* WARNING(SDCC) */ /* IGNORE(GCC) */
+#endif
+
diff -Nru sdcc-4.0.0+dfsg/support/valdiag/tests/struct.c sdcc-4.2.0+dfsg/support/valdiag/tests/struct.c
--- sdcc-4.0.0+dfsg/support/valdiag/tests/struct.c	2018-09-27 09:43:47.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/valdiag/tests/struct.c	2021-07-11 06:05:15.000000000 +0000
@@ -113,3 +113,12 @@
 }
 
 #endif
+
+/* bug 3086: SDCC had infinite loop on this error */
+#ifdef TEST9
+struct tag1 {
+  union {
+    struct tag2;	/* ERROR(SDCC) */ /* IGNORE(GCC) */
+  } tag3;		/* IGNORE */
+};
+#endif
diff -Nru sdcc-4.0.0+dfsg/support/valdiag/valdiag.py sdcc-4.2.0+dfsg/support/valdiag/valdiag.py
--- sdcc-4.0.0+dfsg/support/valdiag/valdiag.py	2019-03-18 10:25:57.000000000 +0000
+++ sdcc-4.2.0+dfsg/support/valdiag/valdiag.py	2022-01-08 21:36:53.000000000 +0000
@@ -122,23 +122,38 @@
     },
     "z80":{
         "compiler":sdcc,
-        "port":"z80"
+        "port":"z80",
+        "extra-defines": {
+            "__has_z88dk_fastcall":"1"
+        }
     },
     "z180":{
         "compiler":sdcc,
-        "port":"z180"
+        "port":"z180",
+        "extra-defines": {
+            "__has_z88dk_fastcall":"1"
+        }
     },
     "r2k":{
         "compiler":sdcc,
-        "port":"r2k"
+        "port":"r2k",
+        "extra-defines": {
+            "__has_z88dk_fastcall":"1"
+        }
     },
-    "gbz80":{
+    "sm83":{
         "compiler":sdcc,
-        "port":"gbz80"
+        "port":"sm83",
+        "extra-defines": {
+            "__has_sdcccall":"1"
+        }
     },
     "tlcs90":{
         "compiler":sdcc,
-        "port":"tlcs90"
+        "port":"tlcs90",
+        "extra-defines": {
+            "__has_z88dk_fastcall":"1"
+        }
     },
     "hc08":{
         "compiler":sdcc,
@@ -158,14 +173,44 @@
             "__has_reentrant":"1"
         }
     },
+    "mos6502":{
+        "compiler":sdcc,
+        "port":"mos6502",
+        "extra-defines": {
+            "__has_data":"1",
+            "__has_xdata":"1",
+            "__has_reentrant":"1"
+        }
+    },
+    "mos65c02":{
+        "compiler":sdcc,
+        "port":"mos65c02",
+        "extra-defines": {
+            "__has_data":"1",
+            "__has_xdata":"1",
+            "__has_reentrant":"1"
+        }
+    },
     "stm8":{
         "compiler":sdcc,
-        "port":"stm8"
+        "port":"stm8",
+        "extra-defines": {
+            "__has_raisonance":"1",
+            "__has_sdcccall":"1"
+        }
+    },
+    "pdk13":{
+        "compiler":sdcc,
+        "port":"pdk13"
     },
     "pdk14":{
         "compiler":sdcc,
         "port":"pdk14"
     },
+    "pdk15":{
+        "compiler":sdcc,
+        "port":"pdk15"
+    },
     "pic14":{
         "compiler":sdcc,
         "port":"pic14"
diff -Nru sdcc-4.0.0+dfsg/.version sdcc-4.2.0+dfsg/.version
--- sdcc-4.0.0+dfsg/.version	2020-01-18 19:03:15.000000000 +0000
+++ sdcc-4.2.0+dfsg/.version	2022-02-14 13:00:32.000000000 +0000
@@ -1 +1,2 @@
-4.0.0
+4.2.0
+

Legend
	Decode
	Execute
	Fetch
	Flush
	Fetch Stall - space in prefetch buffer but bus busy
	Decode Stall - bus busy
	Decode Stall - insufficient data in prefetch buffer
	Decode Stall - read after write

Address	Instruction	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18	19	20	21	22

0x08204	adc A,#0x55
0x08206	jra 0x8208

0x08208	adc A,0x10
0x0820a	jra 0x820c

0x0820c	adc A,0x1000
0x0820f	jra 0x8214

0x08214	adc A,(X)
0x08215	jra 0x8218

0x08218	adc A,(0x10,X)
0x0821a	jra 0x821c

0x0821c	adc A,(0x1000,X)
0x0821f	jra 0x8224

0x08224	adc A,(Y)
0x08226	jra 0x8228

0x08228	adc A,(0x10,Y)
0x0822b	jra 0x8230

0x08230	adc A,(0x1000,Y)
0x08234	jra 0x8238

0x08238	adc A,(0x10,SP)
0x0823a	jra 0x823c

0x0823c	adc A,[0x10.w]
0x0823f	jra 0x8244

0x08244	adc A,[0x1000.w]
0x08248	jra 0x824c

0x0824c	adc A,([0x10.w],X)
0x0824f	jra 0x8254

0x08254	adc A,([0x1000.w],X)
0x08258	jra 0x825c

0x0825c	adc A,([0x10.w],Y)
0x0825f	jra 0x8264

0x08264	add A,#0x55
0x08266	jra 0x8268

0x08268	add A,0x10
0x0826a	jra 0x826c

0x0826c	add A,0x1000
0x0826f	jra 0x8274

0x08274	add A,(X)
0x08275	jra 0x8278

0x08278	add A,(0x10,X)
0x0827a	jra 0x827c

0x0827c	add A,(0x1000,X)
0x0827f	jra 0x8284

0x08284	add A,(Y)
0x08286	jra 0x8288

0x08288	add A,(0x10,Y)
0x0828b	jra 0x8290

0x08290	add A,(0x1000,Y)
0x08294	jra 0x8298

0x08298	add A,(0x10,SP)
0x0829a	jra 0x829c

0x0829c	add A,[0x10.w]
0x0829f	jra 0x82a4

0x082a4	add A,[0x1000.w]
0x082a8	jra 0x82ac

0x082ac	add A,([0x10.w],X)
0x082af	jra 0x82b4

0x082b4	add A,([0x1000.w],X)
0x082b8	jra 0x82bc

0x082bc	add A,([0x10.w],Y)
0x082bf	jra 0x82c4

0x082c4	addw X,#0x1000
0x082c7	jra 0x82cc

0x082cc	addw X,0x1000
0x082d0	jra 0x82d4

0x082d4	addw X,(0x10,SP)
0x082d7	jra 0x82dc

0x082dc	addw Y,#0x1000
0x082e0	jra 0x82e4

0x082e4	addw Y,0x1000
0x082e8	jra 0x82ec

0x082ec	addw Y,0x10
0x082ef	jra 0x82f4

0x082f4	add SP,#0x55
0x082f6	jra 0x82f8

0x082f8	and A,#0x55
0x082fa	jra 0x82fc

0x082fc	and A,0x10
0x082fe	jra 0x8300

0x08300	and A,0x1000
0x08303	jra 0x8308

0x08308	and A,(X)
0x08309	jra 0x830c

0x0830c	and A,(0x10,X)
0x0830e	jra 0x8310

0x08310	and A,(0x1000,X)
0x08313	jra 0x8318

0x08318	and A,(Y)
0x0831a	jra 0x831c

0x0831c	and A,(0x10,Y)
0x0831f	jra 0x8324

0x08324	and A,(0x1000,Y)
0x08328	jra 0x832c

0x0832c	and A,(0x10,SP)
0x0832e	jra 0x8330

0x08330	and A,[0x10.w]
0x08333	jra 0x8338

0x08338	and A,[0x1000.w]
0x0833c	jra 0x8340

0x08340	and A,([0x10.w],X)
0x08343	jra 0x8348

0x08348	and A,([0x1000.w],X)
0x0834c	jra 0x8350

0x08350	and A,([0x10.w],Y)
0x08353	jra 0x8358

0x08358	bccm 0x10,#2
0x0835c	jra 0x8360

0x08360	bcp A,#0x55
0x08362	jra 0x8364

0x08364	bcp A,0x10
0x08366	jra 0x8368

0x08368	bcp A,0x1000
0x0836b	jra 0x8370

0x08370	bcp A,(X)
0x08371	jra 0x8374

0x08374	bcp A,(0x10,X)
0x08376	jra 0x8378

0x08378	bcp A,(0x1000,X)
0x0837b	jra 0x8380

0x08380	bcp A,(Y)
0x08382	jra 0x8384

0x08384	bcp A,(0x10,Y)
0x08387	jra 0x838c

0x0838c	bcp A,(0x1000,Y)
0x08390	jra 0x8394

0x08394	bcp A,(0x10,SP)
0x08396	jra 0x8398

0x08398	bcp A,[0x10.w]
0x0839b	jra 0x83a0

0x083a0	bcp A,[0x1000.w]
0x083a4	jra 0x83a8

0x083a8	bcp A,([0x10.w],X)
0x083ab	jra 0x83b0

0x083b0	bcp A,([0x1000.w],X)
0x083b4	jra 0x83b8

0x083b8	bcp A,([0x10.w],Y)
0x083bb	jra 0x83c0

0x083c0	bcpl 0x10,#2
0x083c4	jra 0x83c8

0x083c8	bres 0x1000,#2
0x083cc	jra 0x83d0

0x083d0	bset 0x1000,#2
0x083d4	jra 0x83d8

0x083d8	ccf
0x083d9	jra 0x83dc

0x083dc	clr A
0x083dd	jra 0x83e0

0x083e0	clr 0xf5
0x083e2	jra 0x83e4

0x083e4	clr 0xf5c2
0x083e8	jra 0x83ec

0x083ec	clr (X)
0x083ed	jra 0x83f0

0x083f0	clr (0xf5,X)
0x083f2	jra 0x83f4

0x083f4	clr (0xf5c2,X)
0x083f8	jra 0x83fc

0x083fc	clr (Y)
0x083fe	jra 0x8400

0x08400	clr (0xf5,Y)
0x08403	jra 0x8408

0x08408	clr (0xf5c2,Y)
0x0840c	jra 0x8410

0x08410	clr (0xf5,SP)
0x08412	jra 0x8414

0x08414	clr [0xf5.w]
0x08417	jra 0x841c

0x0841c	clr [0xf5c2.w]
0x08420	jra 0x8424

0x08424	clr ([0xf5.w],X)
0x08427	jra 0x842c

0x0842c	clr ([0xf5c2.w],X)
0x08430	jra 0x8434

0x08434	clr ([0xf5.w],Y)
0x08437	jra 0x843c

0x0843c	clrw X
0x0843d	jra 0x8440

0x08440	clrw Y
0x08442	jra 0x8444

0x08444	cp A,#0x55
0x08446	jra 0x8448

0x08448	cp A,0x10
0x0844a	jra 0x844c

0x0844c	cp A,0x1000
0x0844f	jra 0x8454

0x08454	cp A,(X)
0x08455	jra 0x8458

0x08458	cp A,(0x10,X)
0x0845a	jra 0x845c

0x0845c	cp A,(0x1000,X)
0x0845f	jra 0x8464

0x08464	cp A,(Y)
0x08466	jra 0x8468

0x08468	cp A,(0x10,Y)
0x0846b	jra 0x8470

0x08470	cp A,(0x1000,Y)
0x08474	jra 0x8478

0x08478	cp A,(0x10,SP)
0x0847a	jra 0x847c

0x0847c	cp A,[0x10.w]
0x0847f	jra 0x8484

0x08484	cp A,[0x1000.w]
0x08488	jra 0x848c

0x0848c	cp A,([0x10.w],X)
0x0848f	jra 0x8494

0x08494	cp A,([0x1000.w],X)
0x08498	jra 0x849c

0x0849c	cp A,([0x10.w],Y)
0x0849f	jra 0x84a4

0x084a4	cpw X,#0x0055
0x084a7	jra 0x84ac

0x084ac	cpw X,0x10
0x084ae	jra 0x84b0

0x084b0	cpw X,0x1000
0x084b3	jra 0x84b8

0x084b8	cpw X,(Y)
0x084ba	jra 0x84bc

0x084bc	cpw X,(0x10,Y)
0x084bf	jra 0x84c4

0x084c4	cpw X,(0x1000,Y)
0x084c8	jra 0x84cc

0x084cc	cpw X,(0x10,SP)
0x084ce	jra 0x84d0

0x084d0	cpw X,[0x10.w]
0x084d3	jra 0x84d8

0x084d8	cpw Y,[0x1000.w]
0x084dc	jra 0x84e0

0x084e0	cpw X,([0x10.w],Y)
0x084e3	jra 0x84e8

0x084e8	cpw Y,([0x1000.w],X)
0x084ec	jra 0x84f0

0x084f0	cpl A
0x084f1	jra 0x84f4

0x084f4	cpl 0xf5
0x084f6	jra 0x84f8

0x084f8	cpl 0xf5c2
0x084fc	jra 0x8500

0x08500	cpl (X)
0x08501	jra 0x8504

0x08504	cpl (0xf5,X)
0x08506	jra 0x8508

0x08508	cpl (0xf5c2,X)
0x0850c	jra 0x8510

0x08510	cpl (Y)
0x08512	jra 0x8514

0x08514	cpl (0xf5,Y)
0x08517	jra 0x851c

0x0851c	cpl (0xf5c2,Y)
0x08520	jra 0x8524

0x08524	cpl (0xf5,SP)
0x08526	jra 0x8528

0x08528	cpl [0xf5.w]
0x0852b	jra 0x8530

0x08530	cpl [0xf5c2.w]
0x08534	jra 0x8538

0x08538	cpl ([0xf5.w],X)
0x0853b	jra 0x8540

0x08540	cpl ([0xf5c2.w],X)
0x08544	jra 0x8548

0x08548	cpl ([0xf5.w],Y)
0x0854b	jra 0x8550

0x08550	cplw X
0x08551	jra 0x8554

0x08554	cplw Y
0x08556	jra 0x8558

0x08558	dec A
0x08559	jra 0x855c

0x0855c	dec 0xf5
0x0855e	jra 0x8560

0x08560	dec 0xf5c2
0x08564	jra 0x8568

0x08568	dec (X)
0x08569	jra 0x856c

0x0856c	dec (0xf5,X)
0x0856e	jra 0x8570

0x08570	dec (0xf5c2,X)
0x08574	jra 0x8578

0x08578	dec (Y)
0x0857a	jra 0x857c

0x0857c	dec (0xf5,Y)
0x0857f	jra 0x8584

0x08584	dec (0xf5c2,Y)
0x08588	jra 0x858c

0x0858c	dec (0xf5,SP)
0x0858e	jra 0x8590

0x08590	dec [0xf5.w]
0x08593	jra 0x8598

0x08598	dec [0xf5c2.w]
0x0859c	jra 0x85a0

0x085a0	dec ([0xf5.w],X)
0x085a3	jra 0x85a8

0x085a8	dec ([0xf5c2.w],X)
0x085ac	jra 0x85b0

0x085b0	dec ([0xf5.w],Y)
0x085b3	jra 0x85b8

0x085b8	decw X
0x085b9	jra 0x85bc

0x085bc	decw Y
0x085be	jra 0x85c0

0x085c0	exg A,XL
0x085c1	jra 0x85c4

0x085c4	exg A,YL
0x085c5	jra 0x85c8

0x085c8	exg A,0x1000
0x085cb	jra 0x85d0

0x085d0	exgw X,Y
0x085d1	jra 0x85d4

0x085d4	inc A
0x085d5	jra 0x85d8

0x085d8	inc 0xf5
0x085da	jra 0x85dc

0x085dc	inc 0xf5c2
0x085e0	jra 0x85e4

0x085e4	inc (X)
0x085e5	jra 0x85e8

0x085e8	inc (0xf5,X)
0x085ea	jra 0x85ec

0x085ec	inc (0xf5c2,X)
0x085f0	jra 0x85f4

0x085f4	inc (Y)
0x085f6	jra 0x85f8

0x085f8	inc (0xf5,Y)
0x085fb	jra 0x8600

0x08600	inc (0xf5c2,Y)
0x08604	jra 0x8608

0x08608	inc (0xf5,SP)
0x0860a	jra 0x860c

0x0860c	inc [0xf5.w]
0x0860f	jra 0x8614

0x08614	inc [0xf5c2.w]
0x08618	jra 0x861c

0x0861c	inc ([0xf5.w],X)
0x0861f	jra 0x8624

0x08624	inc ([0xf5c2.w],X)
0x08628	jra 0x862c

0x0862c	inc ([0xf5.w],Y)
0x0862f	jra 0x8634

0x08634	incw X
0x08635	jra 0x8638

0x08638	incw Y
0x0863a	jra 0x863c

0x0863c	ld A,#0x55
0x0863e	jra 0x8640

0x08640	ld A,0x10
0x08642	jra 0x8644

0x08644	ld A,0x1000
0x08647	jra 0x864c

0x0864c	ld A,(X)
0x0864d	jra 0x8650

0x08650	ld A,(0x10,X)
0x08652	jra 0x8654

0x08654	ld A,(0x1000,X)
0x08657	jra 0x865c

0x0865c	ld A,(Y)
0x0865e	jra 0x8660

0x08660	ld A,(0x10,Y)
0x08663	jra 0x8668

0x08668	ld A,(0x1000,Y)
0x0866c	jra 0x8670

0x08670	ld A,(0x10,SP)
0x08672	jra 0x8674

0x08674	ld A,[0x10.w]
0x08677	jra 0x867c

0x0867c	ld A,[0x1000.w]
0x08680	jra 0x8684

0x08684	ld A,([0x10.w],X)
0x08687	jra 0x868c

0x0868c	ld A,([0x1000.w],X)
0x08690	jra 0x8694

0x08694	ld A,([0x10.w],Y)
0x08697	jra 0x869c

0x0869c	ld 0x10,A
0x0869e	jra 0x86a0

0x086a0	ld 0x1000,A
0x086a3	jra 0x86a8

0x086a8	ld (X),A
0x086a9	jra 0x86ac

0x086ac	ld (0x10,X),A
0x086ae	jra 0x86b0

0x086b0	ld (0x1000,X),A
0x086b3	jra 0x86b8

0x086b8	ld (Y),A
0x086ba	jra 0x86bc

0x086bc	ld (0x10,Y),A
0x086bf	jra 0x86c4

0x086c4	ld (0x1000,Y),A
0x086c8	jra 0x86cc

0x086cc	ld (0x10,SP),A
0x086ce	jra 0x86d0

0x086d0	ld [0x10.w],A
0x086d3	jra 0x86d8

0x086d8	ld [0x1000.w],A
0x086dc	jra 0x86e0

0x086e0	ld ([0x10.w],X),A
0x086e3	jra 0x86e8

0x086e8	ld ([0x1000.w],X),A
0x086ec	jra 0x86f0

0x086f0	ld ([0x10.w],Y),A
0x086f3	jra 0x86f8

0x086f8	ldf A,0x500000
0x086fc	jra 0x8700

0x08700	ldf A,(0x500000,X)
0x08704	jra 0x8708

0x08708	ldf A,(0x500000,Y)
0x0870d	jra 0x8710

0x08710	ldf A,([0x5000 <pa_odr>.e],X)
0x08714	jra 0x8718

0x08718	ldf A,([0x5000 <pa_odr>.e],Y)
0x0871c	jra 0x8720

0x08720	ldf A,[0x50.e]
0x08724	jra 0x8728

0x08728	ldw X,#0x0055
0x0872b	jra 0x8730

0x08730	ldw X,0x10
0x08732	jra 0x8734

0x08734	ldw X,0x1000
0x08737	jra 0x873c

0x0873c	ldw X,(X)
0x0873d	jra 0x8740

0x08740	ldw X,(0x10,X)
0x08742	jra 0x8744

0x08744	ldw X,(0x1000,X)
0x08747	jra 0x874c

0x0874c	ldw X,(0x10,SP)
0x0874e	jra 0x8750

0x08750	ldw X,[0x10.w]
0x08753	jra 0x8758

0x08758	ldw X,[0x1000.w]
0x0875c	jra 0x8760

0x08760	ldw X,([0x10.w],X)
0x08763	jra 0x8768

0x08768	ldw X,([0x1000.w],X)
0x0876c	jra 0x8770

0x08770	mov 0x8000,#0xaa
0x08774	jra 0x8778

0x08778	mov 0x80,0x10
0x0877b	jra 0x8780

0x08780	mov 0x8000,0x1000
0x08785	jra 0x8788

0x08788	mul X,A
0x08789	jra 0x878c

0x0878c	neg A
0x0878d	jra 0x8790

0x08790	neg 0xf5
0x08792	jra 0x8794

0x08794	neg 0xf5c2
0x08798	jra 0x879c

0x0879c	neg (X)
0x0879d	jra 0x87a0

0x087a0	neg (0xf5,X)
0x087a2	jra 0x87a4

0x087a4	neg (0xf5c2,X)
0x087a8	jra 0x87ac

0x087ac	neg (Y)
0x087ae	jra 0x87b0

0x087b0	neg (0xf5,Y)
0x087b3	jra 0x87b8

0x087b8	neg (0xf5c2,Y)
0x087bc	jra 0x87c0

0x087c0	neg (0xf5,SP)
0x087c2	jra 0x87c4

0x087c4	neg [0xf5.w]
0x087c7	jra 0x87cc

0x087cc	neg [0xf5c2.w]
0x087d0	jra 0x87d4

0x087d4	neg ([0xf5.w],X)
0x087d7	jra 0x87dc

0x087dc	neg ([0xf5c2.w],X)
0x087e0	jra 0x87e4

0x087e4	neg ([0xf5.w],Y)
0x087e7	jra 0x87ec

0x087ec	negw X
0x087ed	jra 0x87f0

0x087f0	negw Y
0x087f2	jra 0x87f4

0x087f4	nop
0x087f5	jra 0x87f8

0x087f8	or A,#0x55
0x087fa	jra 0x87fc

0x087fc	or A,0x10
0x087fe	jra 0x8800

0x08800	or A,0x1000
0x08803	jra 0x8808

0x08808	or A,(X)
0x08809	jra 0x880c

0x0880c	or A,(0x10,X)
0x0880e	jra 0x8810

0x08810	or A,(0x1000,X)
0x08813	jra 0x8818

0x08818	or A,(Y)
0x0881a	jra 0x881c

0x0881c	or A,(0x10,Y)
0x0881f	jra 0x8824

0x08824	or A,(0x1000,Y)
0x08828	jra 0x882c

0x0882c	or A,(0x10,SP)
0x0882e	jra 0x8830

0x08830	or A,[0x10.w]
0x08833	jra 0x8838

0x08838	or A,[0x1000.w]
0x0883c	jra 0x8840

0x08840	or A,([0x10.w],X)
0x08843	jra 0x8848

0x08848	or A,([0x1000.w],X)
0x0884c	jra 0x8850

0x08850	or A,([0x10.w],Y)
0x08853	jra 0x8858

0x08858	rcf
0x08859	jra 0x885c

0x0885c	rlc A
0x0885d	jra 0x8860

0x08860	rlc 0xf5
0x08862	jra 0x8864

0x08864	rlc 0xf5c2
0x08868	jra 0x886c

0x0886c	rlc (X)
0x0886d	jra 0x8870

0x08870	rlc (0xf5,X)
0x08872	jra 0x8874

0x08874	rlc (0xf5c2,X)
0x08878	jra 0x887c

0x0887c	rlc (Y)
0x0887e	jra 0x8880

0x08880	rlc (0xf5,Y)
0x08883	jra 0x8888

0x08888	rlc (0xf5c2,Y)
0x0888c	jra 0x8890

0x08890	rlc (0xf5,SP)
0x08892	jra 0x8894

0x08894	rlc [0xf5.w]
0x08897	jra 0x889c

0x0889c	rlc [0xf5c2.w]
0x088a0	jra 0x88a4

0x088a4	rlc ([0xf5.w],X)
0x088a7	jra 0x88ac

0x088ac	rlc ([0xf5c2.w],X)
0x088b0	jra 0x88b4

0x088b4	rlc ([0xf5.w],Y)
0x088b7	jra 0x88bc

0x088bc	rlcw X
0x088bd	jra 0x88c0

0x088c0	rlcw Y
0x088c2	jra 0x88c4

0x088c4	rlwa X
0x088c5	jra 0x88c8

0x088c8	rlwa Y
0x088ca	jra 0x88cc

0x088cc	rrc A
0x088cd	jra 0x88d0

0x088d0	rrc 0xf5
0x088d2	jra 0x88d4

0x088d4	rrc 0xf5c2
0x088d8	jra 0x88dc

0x088dc	rrc (X)
0x088dd	jra 0x88e0

0x088e0	rrc (0xf5,X)
0x088e2	jra 0x88e4

0x088e4	rrc (0xf5c2,X)
0x088e8	jra 0x88ec

0x088ec	rrc (Y)
0x088ee	jra 0x88f0

0x088f0	rrc (0xf5,Y)
0x088f3	jra 0x88f8

0x088f8	rrc (0xf5c2,Y)
0x088fc	jra 0x8900

0x08900	rrc (0xf5,SP)
0x08902	jra 0x8904

0x08904	rrc [0xf5.w]
0x08907	jra 0x890c

0x0890c	rrc [0xf5c2.w]
0x08910	jra 0x8914

0x08914	rrc ([0xf5.w],X)
0x08917	jra 0x891c

0x0891c	rrc ([0xf5c2.w],X)
0x08920	jra 0x8924

0x08924	rrc ([0xf5.w],Y)
0x08927	jra 0x892c

0x0892c	rrcw X
0x0892d	jra 0x8930

0x08930	rrcw Y
0x08932	jra 0x8934

0x08934	rrwa X
0x08935	jra 0x8938

0x08938	rrwa Y
0x0893a	jra 0x893c

0x0893c	rvf
0x0893d	jra 0x8940

0x08940	sbc A,#0x55
0x08942	jra 0x8944

0x08944	sbc A,0x10
0x08946	jra 0x8948

0x08948	sbc A,0x1000
0x0894b	jra 0x8950

0x08950	sbc A,(X)
0x08951	jra 0x8954

0x08954	sbc A,(0x10,X)
0x08956	jra 0x8958

0x08958	sbc A,(0x1000,X)
0x0895b	jra 0x8960

0x08960	sbc A,(Y)
0x08962	jra 0x8964

0x08964	sbc A,(0x10,Y)
0x08967	jra 0x896c

0x0896c	sbc A,(0x1000,Y)
0x08970	jra 0x8974

0x08974	sbc A,(0x10,SP)
0x08976	jra 0x8978

0x08978	sbc A,[0x10.w]
0x0897b	jra 0x8980

0x08980	sbc A,[0x1000.w]
0x08984	jra 0x8988

0x08988	sbc A,([0x10.w],X)
0x0898b	jra 0x8990

0x08990	sbc A,([0x1000.w],X)
0x08994	jra 0x8998

0x08998	sbc A,([0x10.w],Y)
0x0899b	jra 0x89a0

0x089a0	scf
0x089a1	jra 0x89a4

0x089a4	subw X,#0x5500
0x089a7	jra 0x89ac

0x089ac	subw X,0x10
0x089b0	jra 0x89b4

0x089b4	subw X,(0x10,SP)
0x089b7	jra 0x89bc

0x089bc	ldw Y,X
0x089be	jra 0x89c0

0x089c0	ldw 0x10,X
0x089c2	jra 0x89c4

0x089c4	ldw 0x1000,X
0x089c7	jra 0x89cc

0x089cc	ldw (X),Y
0x089cd	jra 0x89d0

0x089d0	ldw (0x10,X),Y
0x089d2	jra 0x89d4

0x089d4	ldw (0x1000,X),Y
0x089d7	jra 0x89dc

0x089dc	ldw (0x10,SP),X
0x089de	jra 0x89e0

0x089e0	ldw [0x10.w],X
0x089e3	jra 0x89e8

0x089e8	ldw [0x1000.w],X
0x089ec	jra 0x89f0

0x089f0	ldw ([0x10.w],X),Y
0x089f3	jra 0x89f8

0x089f8	ldw ([0x1000.w],X),Y
0x089fc	jra 0x8a00

0x08a00	sla A
0x08a01	jra 0x8a04

0x08a04	sla 0xf5
0x08a06	jra 0x8a08

0x08a08	sla 0xf5c2
0x08a0c	jra 0x8a10

0x08a10	sla (X)
0x08a11	jra 0x8a14

0x08a14	sla (0xf5,X)
0x08a16	jra 0x8a18

0x08a18	sla (0xf5c2,X)
0x08a1c	jra 0x8a20

0x08a20	sla (Y)
0x08a22	jra 0x8a24

0x08a24	sla (0xf5,Y)
0x08a27	jra 0x8a2c

0x08a2c	sla (0xf5c2,Y)
0x08a30	jra 0x8a34

0x08a34	sla (0xf5,SP)
0x08a36	jra 0x8a38

0x08a38	sla [0xf5.w]
0x08a3b	jra 0x8a40

0x08a40	sla [0xf5c2.w]
0x08a44	jra 0x8a48

0x08a48	sla ([0xf5.w],X)
0x08a4b	jra 0x8a50

0x08a50	sla ([0xf5c2.w],X)
0x08a54	jra 0x8a58

0x08a58	sla ([0xf5.w],Y)
0x08a5b	jra 0x8a60

0x08a60	slaw X
0x08a61	jra 0x8a64

0x08a64	slaw Y
0x08a66	jra 0x8a68

0x08a68	sla A
0x08a69	jra 0x8a6c

0x08a6c	sla 0xf5
0x08a6e	jra 0x8a70

0x08a70	sla 0xf5c2
0x08a74	jra 0x8a78

0x08a78	sla (X)
0x08a79	jra 0x8a7c

0x08a7c	sla (0xf5,X)
0x08a7e	jra 0x8a80

0x08a80	sla (0xf5c2,X)
0x08a84	jra 0x8a88

0x08a88	sla (Y)
0x08a8a	jra 0x8a8c

0x08a8c	sla (0xf5,Y)
0x08a8f	jra 0x8a94

0x08a94	sla (0xf5c2,Y)
0x08a98	jra 0x8a9c

0x08a9c	sla (0xf5,SP)
0x08a9e	jra 0x8aa0

0x08aa0	sla [0xf5.w]
0x08aa3	jra 0x8aa8

0x08aa8	sla [0xf5c2.w]
0x08aac	jra 0x8ab0

0x08ab0	sla ([0xf5.w],X)
0x08ab3	jra 0x8ab8

0x08ab8	sla ([0xf5c2.w],X)
0x08abc	jra 0x8ac0

0x08ac0	sla ([0xf5.w],Y)
0x08ac3	jra 0x8ac8

0x08ac8	slaw X
0x08ac9	jra 0x8acc

0x08acc	slaw Y
0x08ace	jra 0x8ad0

0x08ad0	sra A
0x08ad1	jra 0x8ad4

0x08ad4	sra 0xf5
0x08ad6	jra 0x8ad8

0x08ad8	sra 0xf5c2
0x08adc	jra 0x8ae0

0x08ae0	sra (X)
0x08ae1	jra 0x8ae4

0x08ae4	sra (0xf5,X)
0x08ae6	jra 0x8ae8

0x08ae8	sra (0xf5c2,X)
0x08aec	jra 0x8af0

0x08af0	sra (Y)
0x08af2	jra 0x8af4

0x08af4	sra (0xf5,Y)
0x08af7	jra 0x8afc

0x08afc	sra (0xf5c2,Y)
0x08b00	jra 0x8b04

0x08b04	sra (0xf5,SP)
0x08b06	jra 0x8b08

0x08b08	sra [0xf5.w]
0x08b0b	jra 0x8b10

0x08b10	sra [0xf5c2.w]
0x08b14	jra 0x8b18

0x08b18	sra ([0xf5.w],X)
0x08b1b	jra 0x8b20

0x08b20	sra ([0xf5c2.w],X)
0x08b24	jra 0x8b28

0x08b28	sra ([0xf5.w],Y)
0x08b2b	jra 0x8b30

0x08b30	sraw X
0x08b31	jra 0x8b34

0x08b34	sraw Y
0x08b36	jra 0x8b38

0x08b38	srl A
0x08b39	jra 0x8b3c

0x08b3c	srl 0xf5
0x08b3e	jra 0x8b40

0x08b40	srl 0xf5c2
0x08b44	jra 0x8b48

0x08b48	srl (X)
0x08b49	jra 0x8b4c

0x08b4c	srl (0xf5,X)
0x08b4e	jra 0x8b50

0x08b50	srl (0xf5c2,X)
0x08b54	jra 0x8b58

0x08b58	srl (Y)
0x08b5a	jra 0x8b5c

0x08b5c	srl (0xf5,Y)
0x08b5f	jra 0x8b64

0x08b64	srl (0xf5c2,Y)
0x08b68	jra 0x8b6c

0x08b6c	srl (0xf5,SP)
0x08b6e	jra 0x8b70

0x08b70	srl [0xf5.w]
0x08b73	jra 0x8b78

0x08b78	srl [0xf5c2.w]
0x08b7c	jra 0x8b80

0x08b80	srl ([0xf5.w],X)
0x08b83	jra 0x8b88

0x08b88	srl ([0xf5c2.w],X)
0x08b8c	jra 0x8b90

0x08b90	srl ([0xf5.w],Y)
0x08b93	jra 0x8b98

0x08b98	srlw X
0x08b99	jra 0x8b9c

0x08b9c	srlw Y
0x08b9e	jra 0x8ba0

0x08ba0	sub A,#0x55
0x08ba2	jra 0x8ba4

0x08ba4	sub A,0x10
0x08ba6	jra 0x8ba8

0x08ba8	sub A,0x1000
0x08bab	jra 0x8bb0

0x08bb0	sub A,(X)
0x08bb1	jra 0x8bb4

0x08bb4	sub A,(0x10,X)
0x08bb6	jra 0x8bb8

0x08bb8	sub A,(0x1000,X)
0x08bbb	jra 0x8bc0

0x08bc0	sub A,(Y)
0x08bc2	jra 0x8bc4

0x08bc4	sub A,(0x10,Y)
0x08bc7	jra 0x8bcc

0x08bcc	sub A,(0x1000,Y)
0x08bd0	jra 0x8bd4

0x08bd4	sub A,(0x10,SP)
0x08bd6	jra 0x8bd8

0x08bd8	sub A,[0x10.w]
0x08bdb	jra 0x8be0

0x08be0	sub A,[0x1000.w]
0x08be4	jra 0x8be8

0x08be8	sub A,([0x10.w],X)
0x08beb	jra 0x8bf0

0x08bf0	sub A,([0x1000.w],X)
0x08bf4	jra 0x8bf8

0x08bf8	sub A,([0x10.w],Y)
0x08bfb	jra 0x8c00

0x08c00	sub SP,#0x55
0x08c02	jra 0x8c04

0x08c04	swap A
0x08c05	jra 0x8c08

0x08c08	swap 0xf5
0x08c0a	jra 0x8c0c

0x08c0c	swap 0xf5c2
0x08c10	jra 0x8c14

0x08c14	swap (X)
0x08c15	jra 0x8c18

0x08c18	swap (0xf5,X)
0x08c1a	jra 0x8c1c

0x08c1c	swap (0xf5c2,X)
0x08c20	jra 0x8c24

0x08c24	swap (Y)
0x08c26	jra 0x8c28

0x08c28	swap (0xf5,Y)
0x08c2b	jra 0x8c30

0x08c30	swap (0xf5c2,Y)
0x08c34	jra 0x8c38

0x08c38	swap (0xf5,SP)
0x08c3a	jra 0x8c3c

0x08c3c	swap [0xf5.w]
0x08c3f	jra 0x8c44

0x08c44	swap [0xf5c2.w]
0x08c48	jra 0x8c4c

0x08c4c	swap ([0xf5.w],X)
0x08c4f	jra 0x8c54

0x08c54	swap ([0xf5c2.w],X)
0x08c58	jra 0x8c5c

0x08c5c	swap ([0xf5.w],Y)
0x08c5f	jra 0x8c64

0x08c64	swapw X
0x08c65	jra 0x8c68

0x08c68	swapw Y
0x08c6a	jra 0x8c6c

0x08c6c	tnz A
0x08c6d	jra 0x8c70

0x08c70	tnz 0xf5
0x08c72	jra 0x8c74

0x08c74	tnz 0xf5c2
0x08c78	jra 0x8c7c

0x08c7c	tnz (X)
0x08c7d	jra 0x8c80

0x08c80	tnz (0xf5,X)
0x08c82	jra 0x8c84

0x08c84	tnz (0xf5c2,X)
0x08c88	jra 0x8c8c

0x08c8c	tnz (Y)
0x08c8e	jra 0x8c90

0x08c90	tnz (0xf5,Y)
0x08c93	jra 0x8c98

0x08c98	tnz (0xf5c2,Y)
0x08c9c	jra 0x8ca0

0x08ca0	tnz (0xf5,SP)
0x08ca2	jra 0x8ca4

0x08ca4	tnz [0xf5.w]
0x08ca7	jra 0x8cac

0x08cac	tnz [0xf5c2.w]
0x08cb0	jra 0x8cb4

0x08cb4	tnz ([0xf5.w],X)
0x08cb7	jra 0x8cbc

0x08cbc	tnz ([0xf5c2.w],X)
0x08cc0	jra 0x8cc4

0x08cc4	tnz ([0xf5.w],Y)
0x08cc7	jra 0x8ccc

0x08ccc	tnzw X
0x08ccd	jra 0x8cd0

0x08cd0	tnzw Y
0x08cd2	jra 0x8cd4

0x08cd4	xor A,#0x55
0x08cd6	jra 0x8cd8

0x08cd8	xor A,0x10
0x08cda	jra 0x8cdc

0x08cdc	xor A,0x1000
0x08cdf	jra 0x8ce4

0x08ce4	xor A,(X)
0x08ce5	jra 0x8ce8

0x08ce8	xor A,(0x10,X)
0x08cea	jra 0x8cec

0x08cec	xor A,(0x1000,X)
0x08cef	jra 0x8cf4

0x08cf4	xor A,(Y)
0x08cf6	jra 0x8cf8

0x08cf8	xor A,(0x10,Y)
0x08cfb	jra 0x8d00

0x08d00	xor A,(0x1000,Y)
0x08d04	jra 0x8d08

0x08d08	xor A,(0x10,SP)
0x08d0a	jra 0x8d0c

0x08d0c	xor A,[0x10.w]
0x08d0f	jra 0x8d14

0x08d14	xor A,[0x1000.w]
0x08d18	jra 0x8d1c

0x08d1c	xor A,([0x10.w],X)
0x08d1f	jra 0x8d24

0x08d24	xor A,([0x1000.w],X)
0x08d28	jra 0x8d2c

0x08d2c	xor A,([0x10.w],Y)
0x08d2f	jra 0x8d34

0x08d34	ldw X,#0x8000
0x08d37	ld A,#0x02
0x08d39	div X,A
0x08d3a	jra 0x8d3c

0x08d3c	ldw X,#0x4000
0x08d3f	ld A,#0x02
0x08d41	div X,A
0x08d42	jra 0x8d44

0x08d44	ldw X,#0x2000
0x08d47	ld A,#0x02
0x08d49	div X,A
0x08d4a	jra 0x8d4c

0x08d4c	ldw X,#0x1000
0x08d4f	ld A,#0x02
0x08d51	div X,A
0x08d52	jra 0x8d54

0x08d54	ldw X,#0x0800
0x08d57	ld A,#0x02
0x08d59	div X,A
0x08d5a	jra 0x8d5c

0x08d5c	ldw X,#0x0400
0x08d5f	ld A,#0x02
0x08d61	div X,A
0x08d62	jra 0x8d64

0x08d64	ldw X,#0x0200
0x08d67	ld A,#0x02
0x08d69	div X,A
0x08d6a	jra 0x8d6c

0x08d6c	ldw X,#0x0100
0x08d6f	ld A,#0x02
0x08d71	div X,A
0x08d72	jra 0x8d74

0x08d74	ldw X,#0x0080
0x08d77	ld A,#0x02
0x08d79	div X,A
0x08d7a	jra 0x8d7c

0x08d7c	ldw X,#0x0040
0x08d7f	ld A,#0x02
0x08d81	div X,A
0x08d82	jra 0x8d84

0x08d84	ldw X,#0x0020
0x08d87	ld A,#0x02
0x08d89	div X,A
0x08d8a	jra 0x8d8c

0x08d8c	ldw X,#0x0010
0x08d8f	ld A,#0x02
0x08d91	div X,A
0x08d92	jra 0x8d94

0x08d94	ldw X,#0x0008
0x08d97	ld A,#0x02
0x08d99	div X,A
0x08d9a	jra 0x8d9c

0x08d9c	ldw X,#0x0004
0x08d9f	ld A,#0x02
0x08da1	div X,A
0x08da2	jra 0x8da4

0x08da4	ldw X,#0x0002
0x08da7	ld A,#0x02
0x08da9	div X,A
0x08daa	jra 0x8dac

0x08dac	ldw X,#0xffff
0x08daf	ld A,#0x02
0x08db1	div X,A
0x08db2	jra 0x8db4

0x08db4	ldw X,#0x7fff
0x08db7	ld A,#0x02
0x08db9	div X,A
0x08dba	jra 0x8dbc

0x08dbc	ldw X,#0x3fff
0x08dbf	ld A,#0x02
0x08dc1	div X,A
0x08dc2	jra 0x8dc4

0x08dc4	ldw X,#0x1fff
0x08dc7	ld A,#0x02
0x08dc9	div X,A
0x08dca	jra 0x8dcc

0x08dcc	ldw X,#0x0fff
0x08dcf	ld A,#0x02
0x08dd1	div X,A
0x08dd2	jra 0x8dd4

0x08dd4	ldw X,#0x07ff
0x08dd7	ld A,#0x02
0x08dd9	div X,A
0x08dda	jra 0x8ddc

0x08ddc	ldw X,#0x03ff
0x08ddf	ld A,#0x02
0x08de1	div X,A
0x08de2	jra 0x8de4

0x08de4	ldw X,#0x01ff
0x08de7	ld A,#0x02
0x08de9	div X,A
0x08dea	jra 0x8dec

0x08dec	ldw X,#0x00ff
0x08def	ld A,#0x02
0x08df1	div X,A
0x08df2	jra 0x8df4

0x08df4	ldw X,#0x007f
0x08df7	ld A,#0x02
0x08df9	div X,A
0x08dfa	jra 0x8dfc

0x08dfc	ldw X,#0x003f
0x08dff	ld A,#0x02
0x08e01	div X,A
0x08e02	jra 0x8e04

0x08e04	ldw X,#0x001f
0x08e07	ld A,#0x02
0x08e09	div X,A
0x08e0a	jra 0x8e0c

0x08e0c	ldw X,#0x000f
0x08e0f	ld A,#0x02
0x08e11	div X,A
0x08e12	jra 0x8e14

0x08e14	ldw X,#0x0007
0x08e17	ld A,#0x02
0x08e19	div X,A
0x08e1a	jra 0x8e1c

0x08e1c	ldw X,#0x0003
0x08e1f	ld A,#0x02
0x08e21	div X,A
0x08e22	jra 0x8e24

0x08e24	ldw X,#0x2000
0x08e27	ld A,#0x02
0x08e29	div X,A
0x08e2a	jra 0x8e2c

0x08e2c	ldw X,#0x2040
0x08e2f	ld A,#0x02
0x08e31	div X,A
0x08e32	jra 0x8e34

0x08e34	ldw X,#0x2048
0x08e37	ld A,#0x02
0x08e39	div X,A
0x08e3a	jra 0x8e3c

0x08e3c	ldw X,#0x2148
0x08e3f	ld A,#0x02
0x08e41	div X,A
0x08e42	jra 0x8e44

0x08e44	ldw X,#0x21c8
0x08e47	ld A,#0x02
0x08e49	div X,A
0x08e4a	jra 0x8e4c

0x08e4c	ldw X,#0xb307
0x08e4f	ld A,#0x5e
0x08e51	div X,A
0x08e52	halt

Address	Instruction	1	2	3	4	5	6	7	8	9	10	11

0x080c4	inc A
0x080c5	jp 0x80cc

0x080cc	neg A
0x080cd	call 0x80d8

0x080d8	incw X

Address	Instruction	1	2	3	4	5	6	7	8	9	10	11	12

0x080e0	sub SP,#0x14
0x080e2	ld A,#0x14
0x080e4	btjt 0x0010,#5,0x80f8
0x080e9	inc A
0x080ea	btjf 0x0020,#3,0x80f8

0x080f8	incw Y
0x080fa	ld A,(X)

Address	Instruction	1	2	3	4	5	6	7	8	9	10	11	12	13

0x0808c	ldw X,[0x50.w]
0x0808f	addw X,#0x0014
0x08092	ld A,[0x30.w]

Address	Instruction	1	2	3	4	5	6	7	8	9	10	11	12	13	14

0x08098	neg A
0x08099	xor A,0x10
0x0809b	ld A,#0x14
0x0809d	sub A,0x1000
0x080a0	inc A
0x080a1	ld XL,A
0x080a2	srl A
0x080a3	swap A
0x080a4	sla 0x15
0x080a6	cp A,#0xfe
0x080a8	mov 0x0100,#0x0b
0x080ac	mov 0x0101,#0x16

Address	Instruction	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18	19	20	21

0x00104	neg A
0x00105	xor A,0x10
0x00107	ld A,#0x14
0x00109	sub A,0x1000
0x0010c	inc A
0x0010d	ld XL,A
0x0010e	srl A
0x0010f	swap A
0x00110	sla 0x15
0x00112	cp A,#0xfe

Code analyser

Commands of μCsim to manage breakpoints

Commands of μCsim to manage breakpoints

clear [addr...]

commands script

commands [breakpoint-nr] script

Dump commands of μCsim

dump [/format] memory_type [start [end [bytes_per_line]]] - dump bit_name...

dump [/format] memory_type [start [end [bytes_per_line]]]

dump [/format] memory_type [start [end [bytes_per_line]]] + + dump bit...

dump [/format] memory_name [start [end + [bytes_per_line]]]

dump bit_name...

Execution commands of μCsim

Execution commands of μCsim

r,run,go [start [stop]]

stop

s,step [steps]

n,next

pc [address]

history list [nr] + history print [nr]

General commands of μCsim

General commands of μCsim

Registers of MCS51 family

Registers of AVR family

Registers of Z80 family

Registers of XA family

Registers of HC08 family

Command reference of μCsim

Command reference of μCsim

Memory manipulation commands of μCsim

Memory manipulation commands of μCsim

file,load "FILE"

file,load "file"

download,dl

fill memory_type start end data

where,Where memory_type data...

hole [memory [length [value]]]

memory

memory createchip|cchip id size - cellsize

memory create

memory create chip id size cellsize

memory -createaddressspace|caddressspace|caddrspace|caspace|createaddrspace|createaspace - id startaddr size

memory -createaddressdecoder|caddrdecoder|caddressdecoder|cadecoder|createaddrdecoder|createadecoder - addressspace begin end chip begin

memory create as|addressspace|addr|addrs|addrspace|aspace id + startaddr size

memory create + ad|addrdec|addrdecoder|addressdec|addressdecoder|adec|adecoder addressspace + begin end chip begin

memory info

memory create banker switcher_addressspace switcher_address + switcher_mask banked_addressspace start end

memory create bank addressspace begin bank_nr chip begin

memory create bander addressspace begin end chip begin + bits_per_chip [distance]

memory remove|rm|del

memory remove chip id

memory info

var name [memory addr]

rmvar name

wi,Wi string

Software simulator for microcontrollers

Starting the simulator

Using multiple consoles

Why?

How?

What to do with it?

Stop

Tricks

News

version 0.6

Using serial interfaces

Connecting two instances of simulator

Simulator interface

Features of the STM8 Simulator

Cycle Counts

Notes on Documention

PM0044 Section 5.3 Pipelined execution examples

PM0044 Section 7.4 Instruction Set

Stall Cycle Detection

Cycle and Pipeline Analysis

Example Analyses

Documented Examples

Additional Examples

Hardware Cycle Counting

DIV tests - available ST docs simply say '2-17 cycles'

dump [/format] memory_type [start [end [bytes_per_line]]]
- dump bit_name...

dump [/format] memory_type [start [end [bytes_per_line]]] +
+ dump bit...

history list [nr]
+ history print [nr]