diff -u xserver-xorg-video-intel-2.99.910/debian/changelog xserver-xorg-video-intel-2.99.910/debian/changelog --- xserver-xorg-video-intel-2.99.910/debian/changelog +++ xserver-xorg-video-intel-2.99.910/debian/changelog @@ -1,3 +1,18 @@ +xserver-xorg-video-intel (2:2.99.910-0ubuntu1.6) trusty-proposed; urgency=medium + + * sna-mark-the-chv-vsync-method-as-unknown.diff: Fix video playback + on CHV. (LP: #1445221) + + -- Timo Aaltonen Fri, 17 Apr 2015 08:00:47 +0300 + +xserver-xorg-video-intel (2:2.99.910-0ubuntu1.5) trusty-proposed; urgency=medium + + * bdw-annotate-more-64bit-pointer-locations.diff + bdw-clamp-urb-allocations-for-gt3.diff: + Fix BDW GT3. (LP: #1444436) + + -- Timo Aaltonen Thu, 16 Apr 2015 07:27:37 +0300 + xserver-xorg-video-intel (2:2.99.910-0ubuntu1.4) trusty-proposed; urgency=medium [ Timo Aaltonen ] diff -u xserver-xorg-video-intel-2.99.910/debian/patches/series xserver-xorg-video-intel-2.99.910/debian/patches/series --- xserver-xorg-video-intel-2.99.910/debian/patches/series +++ xserver-xorg-video-intel-2.99.910/debian/patches/series @@ -28,0 +29,3 @@ +bdw-annotate-more-64bit-pointer-locations.diff +bdw-clamp-urb-allocations-for-gt3.diff +sna-mark-the-chv-vsync-method-as-unknown.diff only in patch2: unchanged: --- xserver-xorg-video-intel-2.99.910.orig/debian/patches/bdw-annotate-more-64bit-pointer-locations.diff +++ xserver-xorg-video-intel-2.99.910/debian/patches/bdw-annotate-more-64bit-pointer-locations.diff @@ -0,0 +1,132 @@ +commit de54a93217cc550c44ee138f0511ede6925d84e0 +Author: Chris Wilson +Date: Wed Oct 22 19:30:21 2014 +0100 + + sna/gen8: Annotate more 64bit pointer locations + + Signed-off-by: Chris Wilson + +--- a/src/sna/gen8_render.c ++++ b/src/sna/gen8_render.c +@@ -474,7 +474,7 @@ gen8_emit_vs_invariant(struct sna *sna) + OUT_BATCH(GEN8_3DSTATE_VS | (9 - 2)); + OUT_BATCH64(0); /* no VS kernel */ + OUT_BATCH(0); +- OUT_BATCH64(0); ++ OUT_BATCH64(0); /* scratch */ + OUT_BATCH(0); + OUT_BATCH(1 << 1); /* pass-through */ + OUT_BATCH(1 << 16 | 1 << 21); /* urb write to SBE */ +@@ -500,12 +500,10 @@ static void + gen8_emit_hs_invariant(struct sna *sna) + { + OUT_BATCH(GEN8_3DSTATE_HS | (9 - 2)); +- OUT_BATCH(0); /* no HS kernel */ +- OUT_BATCH(0); +- OUT_BATCH(0); +- OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); ++ OUT_BATCH64(0); /* no HS kernel */ ++ OUT_BATCH64(0); /* scratch */ + OUT_BATCH(0); + OUT_BATCH(0); /* pass-through */ + +@@ -541,11 +539,9 @@ static void + gen8_emit_ds_invariant(struct sna *sna) + { + OUT_BATCH(GEN8_3DSTATE_DS | (9 - 2)); ++ OUT_BATCH64(0); /* no kernel */ + OUT_BATCH(0); +- OUT_BATCH(0); +- OUT_BATCH(0); +- OUT_BATCH(0); +- OUT_BATCH(0); ++ OUT_BATCH64(0); /* scratch */ + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); +@@ -573,15 +569,13 @@ static void + gen8_emit_gs_invariant(struct sna *sna) + { + OUT_BATCH(GEN8_3DSTATE_GS | (10 - 2)); +- OUT_BATCH(0); /* no GS kernel */ +- OUT_BATCH(0); +- OUT_BATCH(0); +- OUT_BATCH(0); ++ OUT_BATCH64(0); /* no GS kernel */ + OUT_BATCH(0); ++ OUT_BATCH64(0); /* scratch */ + OUT_BATCH(0); ++ OUT_BATCH(0); /* pass-through */ + OUT_BATCH(0); + OUT_BATCH(0); +- OUT_BATCH(0); /* pass-through */ + + #if SIM + OUT_BATCH(GEN8_3DSTATE_CONSTANT_GS | (11 - 2)); +@@ -690,13 +684,15 @@ gen8_emit_wm_invariant(struct sna *sna) + OUT_BATCH(WM_PERSPECTIVE_PIXEL_BARYCENTRIC); + + #if SIM +- OUT_BATCH(GEN8_3DSTATE_WM_HZ_OP | (5 - 2)); ++ OUT_BATCH(GEN8_3DSTATE_WM_CHROMAKEY | (2 - 2)); + OUT_BATCH(0); ++#endif ++ ++#if 0 ++ OUT_BATCH(GEN8_3DSTATE_WM_HZ_OP | (5 - 2)); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); +- +- OUT_BATCH(GEN8_3DSTATE_WM_CHROMAKEY | (2 - 2)); + OUT_BATCH(0); + #endif + +@@ -834,6 +830,7 @@ gen8_emit_cc(struct sna *sna, uint32_t b + } else + OUT_BATCH(PS_BLEND_HAS_WRITEABLE_RT); + ++ assert(is_aligned(render->cc_blend + blend * GEN8_BLEND_STATE_PADDED_SIZE, 64)); + OUT_BATCH(GEN8_3DSTATE_BLEND_STATE_POINTERS | (2 - 2)); + OUT_BATCH((render->cc_blend + blend * GEN8_BLEND_STATE_PADDED_SIZE) | 1); + +@@ -896,6 +893,9 @@ gen8_emit_wm(struct sna *sna, int kernel + wm_kernels[kernel].name, + wm_kernels[kernel].num_surfaces, + kernels[0], kernels[1], kernels[2])); ++ assert(is_aligned(kernels[0], 64)); ++ assert(is_aligned(kernels[1], 64)); ++ assert(is_aligned(kernels[2], 64)); + + OUT_BATCH(GEN8_3DSTATE_PS | (12 - 2)); + OUT_BATCH64(kernels[0] ?: kernels[1] ?: kernels[2]); +@@ -1185,8 +1185,8 @@ static bool gen8_magic_ca_pass(struct sn + true, true, + op->is_affine)); + +- OUT_BATCH(GEN8_3DPRIMITIVE | (7- 2)); +- OUT_BATCH(RECTLIST); /* ignored, see VF_TOPOLOGY */ ++ OUT_BATCH(GEN8_3DPRIMITIVE | (7 - 2)); ++ OUT_BATCH(0); /* ignored, see VF_TOPOLOGY */ + OUT_BATCH(sna->render.vertex_index - sna->render.vertex_start); + OUT_BATCH(sna->render.vertex_start); + OUT_BATCH(1); /* single instance */ +@@ -1371,7 +1371,7 @@ static void gen8_emit_primitive(struct s + } + + OUT_BATCH(GEN8_3DPRIMITIVE | (7 - 2)); +- OUT_BATCH(RECTLIST); /* ignored, see VF_TOPOLOGY */ ++ OUT_BATCH(0); /* ignored, see VF_TOPOLOGY */ + sna->render.vertex_offset = sna->kgem.nbatch; + OUT_BATCH(0); /* vertex count, to be filled in later */ + OUT_BATCH(sna->render.vertex_index); +@@ -1712,6 +1712,7 @@ gen8_create_blend_state(struct sna_stati + assert(((ptr - base) & 63) == 0); + COMPILE_TIME_ASSERT(sizeof(blend->common) == 4); + COMPILE_TIME_ASSERT(sizeof(blend->rt) == 8); ++ COMPILE_TIME_ASSERT((char *)&blend->rt - (char *)blend == 4); + + blend->rt.post_blend_clamp = 1; + blend->rt.pre_blend_clamp = 1; only in patch2: unchanged: --- xserver-xorg-video-intel-2.99.910.orig/debian/patches/bdw-clamp-urb-allocations-for-gt3.diff +++ xserver-xorg-video-intel-2.99.910/debian/patches/bdw-clamp-urb-allocations-for-gt3.diff @@ -0,0 +1,38 @@ +commit 7a9bdadd71730adc5266bc6758982abec5917b93 +Author: Chris Wilson +Date: Wed Oct 22 19:31:10 2014 +0100 + + sna/gen8: Clamp URB allocations for GT3 + + GT3 requires some reserved space in the URB allocation and so we must + reduce the amount we allocate to our vertices. + + Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=81583 + Signed-off-by: Chris Wilson + +--- a/src/sna/gen8_render.c ++++ b/src/sna/gen8_render.c +@@ -419,19 +419,19 @@ gen8_emit_urb(struct sna *sna) + OUT_BATCH(GEN8_3DSTATE_URB_VS | (2 - 2)); + OUT_BATCH(960 << URB_ENTRY_NUMBER_SHIFT | + (2 - 1) << URB_ENTRY_SIZE_SHIFT | +- 1 << URB_STARTING_ADDRESS_SHIFT); ++ 4 << URB_STARTING_ADDRESS_SHIFT); + + OUT_BATCH(GEN8_3DSTATE_URB_HS | (2 - 2)); + OUT_BATCH(0 << URB_ENTRY_SIZE_SHIFT | +- 0 << URB_STARTING_ADDRESS_SHIFT); ++ 4 << URB_STARTING_ADDRESS_SHIFT); + + OUT_BATCH(GEN8_3DSTATE_URB_DS | (2 - 2)); + OUT_BATCH(0 << URB_ENTRY_SIZE_SHIFT | +- 0 << URB_STARTING_ADDRESS_SHIFT); ++ 4 << URB_STARTING_ADDRESS_SHIFT); + + OUT_BATCH(GEN8_3DSTATE_URB_GS | (2 - 2)); + OUT_BATCH(0 << URB_ENTRY_SIZE_SHIFT | +- 0 << URB_STARTING_ADDRESS_SHIFT); ++ 4 << URB_STARTING_ADDRESS_SHIFT); + } + + static void only in patch2: unchanged: --- xserver-xorg-video-intel-2.99.910.orig/debian/patches/sna-mark-the-chv-vsync-method-as-unknown.diff +++ xserver-xorg-video-intel-2.99.910/debian/patches/sna-mark-the-chv-vsync-method-as-unknown.diff @@ -0,0 +1,79 @@ +commit 2afeef0c3ffeae768198fc08c9f365ccd28b7f5d +Author: Chris Wilson +Date: Thu May 15 11:28:48 2014 +0100 + + sna: Mark the CHV vsync method as unknown + + Similar to the story with Baytrail, vsync is a lost art. + + Signed-off-by: Chris Wilson + +--- a/src/sna/sna_display.c ++++ b/src/sna/sna_display.c +@@ -4209,52 +4209,6 @@ static bool sna_emit_wait_for_scanline_h + return true; + } + +-static bool sna_emit_wait_for_scanline_vlv(struct sna *sna, +- xf86CrtcPtr crtc, +- int pipe, int y1, int y2, +- bool full_height) +-{ +- uint32_t display_base = 0x180000; +- uint32_t event; +- uint32_t *b; +- +- return false; /* synchronisation? I've heard of that */ +- +- if (!sna->kgem.has_secure_batches) +- return false; +- +- assert(y1 >= 0); +- assert(y2 > y1); +- assert(sna->kgem.mode); +- +- /* Always program one less than the desired value */ +- if (--y1 < 0) +- y1 = crtc->bounds.y2; +- y2--; +- +- b = kgem_get_batch(&sna->kgem); +- sna->kgem.nbatch += 4; +- +- if (pipe == 0) { +- if (full_height) +- event = MI_WAIT_FOR_PIPEA_SVBLANK; +- else +- event = MI_WAIT_FOR_PIPEA_SCAN_LINE_WINDOW; +- } else { +- if (full_height) +- event = MI_WAIT_FOR_PIPEB_SVBLANK; +- else +- event = MI_WAIT_FOR_PIPEB_SCAN_LINE_WINDOW; +- } +- b[0] = MI_LOAD_REGISTER_IMM | 1; +- b[1] = display_base + 0x70004 + 0x1000 * pipe; +- b[2] = (1 << 31) | (y1 << 16) | y2; +- b[3] = MI_WAIT_FOR_EVENT | event; +- +- sna->kgem.batch_flags |= I915_EXEC_SECURE; +- return true; +-} +- + static bool sna_emit_wait_for_scanline_ivb(struct sna *sna, + xf86CrtcPtr crtc, + int pipe, int y1, int y2, +@@ -4472,10 +4426,12 @@ sna_wait_for_scanline(struct sna *sna, + + if (sna->kgem.gen >= 0110) + ret = false; ++ else if (sna->kgem.gen == 0101) ++ ret = false; /* chv, vsync method unknown */ + else if (sna->kgem.gen >= 075) + ret = sna_emit_wait_for_scanline_hsw(sna, crtc, pipe, y1, y2, full_height); + else if (sna->kgem.gen == 071) +- ret = sna_emit_wait_for_scanline_vlv(sna, crtc, pipe, y1, y2, full_height); ++ ret = false; /* vlv, vsync method unknown */ + else if (sna->kgem.gen >= 070) + ret = sna_emit_wait_for_scanline_ivb(sna, crtc, pipe, y1, y2, full_height); + else if (sna->kgem.gen >= 060)