--- electric-8.07.orig/debian/menu +++ electric-8.07/debian/menu @@ -0,0 +1,5 @@ +?package(electric):needs="X11"\ + section="Applications/Science/Engineering"\ + hints="CAD,Electric"\ + title="electric" \ + command="/usr/bin/electric" --- electric-8.07.orig/debian/control +++ electric-8.07/debian/control @@ -0,0 +1,19 @@ +Source: electric +Section: electronics +Priority: optional +Build-Depends: debhelper (>= 6), cdbs, ant +Build-Depends-Indep: default-jdk | openjdk-6-jdk | sun-java5-jdk | sun-java6-jdk, bsh +Maintainer: Ubuntu MOTU Developers +XSBC-Original-Maintainer: Onkar Shinde +Standards-Version: 3.8.0 +Homepage: http://www.staticfreesoft.com/productsFree.html + +Package: electric +Architecture: all +Depends: default-jre | java2-runtime, bsh +Description: electrical CAD system + Electric is a sophisticated electrical CAD system that can handle many forms + of circuit design, including custom IC layout (ASICs), schematic drawing, + hardware description language specifications, and electro-mechanical hybrid + layout. + --- electric-8.07.orig/debian/rules +++ electric-8.07/debian/rules @@ -0,0 +1,21 @@ +#!/usr/bin/make -f + +export VERSION = $(shell head -1 debian/changelog | cut -f2 -d\( | cut -f1 -d\) | cut -f1 -d\-) + +include /usr/share/cdbs/1/rules/debhelper.mk +include /usr/share/cdbs/1/rules/simple-patchsys.mk +include /usr/share/cdbs/1/class/ant.mk + +JAVA_HOME_DIRS := /usr/lib/jvm/default-java /usr/lib/jvm/java-6-openjdk /usr/lib/jvm/java-1.5.0-sun /usr/lib/jvm/java-6-sun +DEB_JARS := bsh +DEB_INSTALL_CHANGELOGS_ALL := ChangeLog.txt + + +get-orig-source:: + cd .. && wget -c http://ftp.gnu.org/pub/gnu/electric/electric-$(VERSION).jar + mkdir debian/electric-$(VERSION) && cd debian/electric-$(VERSION) && jar -xvf ../../../electric-$(VERSION).jar + find debian/electric-$(VERSION)/ -name *.class | xargs rm -f + cd debian && tar -cf ../../electric_$(VERSION).orig.tar electric-$(VERSION)/ + gzip -9 ../electric_$(VERSION).orig.tar + rm -rf debian/electric-$(VERSION) + --- electric-8.07.orig/debian/watch +++ electric-8.07/debian/watch @@ -0,0 +1,7 @@ +# Example watch control file for uscan +# Rename this file to "watch" and then you can run the "uscan" command +# to check for upstream updates and more. +# Site Directory Pattern Version Script +version=3 + +ftp.gnu.org /pub/gnu/electric/ electric-(.*)\.jar --- electric-8.07.orig/debian/README.source +++ electric-8.07/debian/README.source @@ -0,0 +1,33 @@ +This package uses CDBS (and therefore simple-patchsys.mk) in order to +apply patches to the upstream source. Patches are stored in +debian/patches and their filenames usually end in .patch or .diff . +For further details, see the man page for cdbs-edit-patch. + +All commands described below should be run from the top directory of the +package source tree, unless otherwise stated. + + * To generate the fully patched source, in a form ready for + editing, that would be built to create Debian packages, run: + + make -f debian/rules apply-patches + + Note: This should happen automatically when you run + dpkg-source -x on a CDBS simple-patchsys.mk source package. + + * To modify the source and save those modifications so that + they will be applied when building the package, pick a + suitably informative patch file name, for example + 01_add_README.source_file.patch, and then run: + + cdbs-edit-patch 01_add_README.source_file.patch + + This will place you in a new shell in a temporary copy of the + source tree. Make your desired modifications to it, and then + exit the shell to create the patch file containing them (this + file will appear in debian/patches). + + * To remove source modifications that are currently being + applied when building the package, run: + + make -f debian/rules reverse-patches + --- electric-8.07.orig/debian/electric.docs +++ electric-8.07/debian/electric.docs @@ -0,0 +1,3 @@ +README.txt +#ChangeLog.txt + --- electric-8.07.orig/debian/changelog +++ electric-8.07/debian/changelog @@ -0,0 +1,148 @@ +electric (8.07-0ubuntu1) intrepid; urgency=low + + * New Upstream version. Please check changelog for details. (LP: #242720) + * debian/control + - Add build dependencies *-jdk, cdbs and bsh. + - Remove build dependency dpatch. We will be using CDBS simple patchsys. + - Refreshed runtime dependencies to default-jre | java2-runtime and bsh. + - Added home page field. + - Standard version 3.8.0. + - Modify Maintainer value to match the DebianMaintainerField + specification. + - Changed email address for original maintainer to indicate who has + refreshed the packaging. + * debian/rules + - Revamped to use cdbs. + - Added get-orig-source target. + * debian/patches + - 00list, 02_sensible-browser.dpatch, 01_errors-numbers.dpatch, + 03_manpage.dpatch - Deleted, not relevant anymore. + - 01_fix_build_xml.patch - Patch to fix the build.xml. + * debian/ant.properties + - File to set various compilation properties. + * debian/electric.1 + - Remove the entry that causes lintian warning. + * debian/electric.desktop + - Change as suggested by desktop-file-validate. + * debian/electric.docs + - Updated as per changes in file names. + * debian/electric.svg + - Name changed from electric_icon.svg. + * debian/install + - Added appropriate locations for jar file, desktop file and wrapper shell + script. + * debian/README.source + - Added to comply with standards version 3.8.0. + * debian/TODO.Debian + - Name changed form TODO. + * debain/wrapper/electric + - Wrapper shell script to launch the application. + * debian/manpages + - Added for installation of manpage. + * debian/watch + - Updated to match jar files instead of older tar.gz files. + * debian/dirs + - Removed, not needed anymore. + * debian/{electric.doc-base, electric.examples, substvars} + - Removed, not relevant anymore. + * debian/*.debhelper + - Removed auto generated files. Not relevant anymore. + + -- Onkar Shinde Wed, 23 Jul 2008 02:09:53 +0530 + +electric (6.05-4) unstable; urgency=low + + * QA upload + * Use dpatch for patch management + * debhelper compatibility level 6: use in debian/rules as package tree + debian/electric instead of debian/tmp + * debian/rules: do not ignore errors of make clean + * renamed debian/electric.copyright to debian/copyright, change "Authors(s)" + to "Author". + * renamed debian/electric/menu to debianmenu, changed menu section to + Applications/Science/Engineering, quote strings. + * src/vhdl/vhdlparser.c: fix bug concerning display of numbers in error + messages. Patch contributed by Ian Jackson (thanks!) (Closes: Bug#156613). + * src/graph/graphqt.cpp and src/graph/graphunixx11.c: call sensible-browser + instad of netscape. Add dependency on www-browser (Closes: Bug#140058). + * Add electric.desktop file contributed by Vassilis Pandis (thanks!) + (Closes: Bug#367242). + * Renamed debian/electric.dirs to debian/dirs, + added /usr/share/{pixmaps,applicatins}. + * Install electric icon (taken from Ubuntu patch). + * Fix some nroff errors in manpage, patch by Nicolas François (thanks!) + (Closes: Bug#349892). + + -- Ralf Treinen Thu, 17 Jan 2008 23:04:59 +0100 + +electric (6.05-3) unstable; urgency=low + + * Non-maintainer upload. + * lesstif1 is deprecated, transition to lesstif2 (Closes: #374242) + * Fixed copyright to point to GPL license to fix lintian error + + -- Kai Hendry Fri, 14 Jul 2006 13:26:04 +0900 + +electric (6.05-2.1) unstable; urgency=low + + * Orphaning this package, setting maintainer to QA. + + -- Kyle McMartin Thu, 17 Mar 2005 11:18:49 -0500 + +electric (6.05-2) unstable; urgency=low + + * New maintainer. (closes: #277731) + + -- Kyle McMartin Fri, 22 Oct 2004 21:22:14 -0400 + +electric (6.05-1) unstable; urgency=low + + * new upstream release + * added menu hints (closes: #128765) + * changed doc-base to go into Technical section per menu-policy + + -- Chris Ruffin Sat, 23 Mar 2002 11:02:56 -0500 + +electric (6.03-3) unstable; urgency=low + + * Upgraded standards conformance to 3.5.4.0 + + -- Chris Ruffin Sun, 3 Jun 2001 22:06:41 -0400 + +electric (6.03-2) unstable; urgency=low + + * Moved documentation to /usr/share/doc (closes: Bug#94788) + + -- Chris Ruffin Thu, 26 Apr 2001 20:32:27 -0400 + +electric (6.03-1) unstable; urgency=low + + * New upstream sources. + + -- Chris Ruffin Mon, 2 Apr 2001 20:44:08 -0400 + +electric (6.02.1-1) unstable; urgency=low + + * New upstrem sources. + * Restructured package + + -- Chris Ruffin Sat, 13 Jan 2001 20:57:44 -0500 + +electric (6.00-2) unstable; urgency=low + + * Added upstream-provided man page + + -- Chris Ruffin Sat, 13 Jan 2001 15:05:06 -0500 + +electric (6.00-1) unstable; urgency=low + + * Initial Release. (closes: Bug#76824, Bug#76825) + * Modified Makefile.in and src/include/config.h to bring package into + into compliance with Debian standards. + * Modified src/usr/usrcomek.c to specify the location of the documentation + directory (/usr/share/doc/electric/html) + + -- Chris Ruffin Sat, 9 Sep 2000 16:50:25 -0400 + + + --- electric-8.07.orig/debian/manpages +++ electric-8.07/debian/manpages @@ -0,0 +1 @@ +debian/electric.1 --- electric-8.07.orig/debian/compat +++ electric-8.07/debian/compat @@ -0,0 +1,2 @@ +6 + --- electric-8.07.orig/debian/electric.svg +++ electric-8.07/debian/electric.svg @@ -0,0 +1,103 @@ + + + + + + + + + image/svg+xml + + + + + + + + + + + + + + + + + + --- electric-8.07.orig/debian/electric.desktop +++ electric-8.07/debian/electric.desktop @@ -0,0 +1,9 @@ +[Desktop Entry] +Version=1.0 +Name=electric +GenericName=Electrical CAD +Comment=Electrical CAD System +Type=Application +Exec=electric +Icon=electric +Categories=Education;Electronics;Engineering; --- electric-8.07.orig/debian/TODO.Debian +++ electric-8.07/debian/TODO.Debian @@ -0,0 +1 @@ +- add icon for electric in the debian menu system --- electric-8.07.orig/debian/electric.1 +++ electric-8.07/debian/electric.1 @@ -0,0 +1,285 @@ +.TH electric 1 11/12/00 +.SH NAME +electric - a VLSI design system + +.SH SYNOPSIS +\fBelectric\fR [\fI-m\fR] [\fI-t technology\fR] [\fIlibrary\fR] + +.SH DESCRIPTION +Electric is a general purpose system for all electrical design. +It currently knows about nMOS, CMOS, Bipolar, artwork, +schematics, printed-circuit boards, and many other technologies. +Its has a large set of tools including +multiple design-rule checkers (both incremental and hierarchical), +an electrical rules checker, +over a dozen simulator interfaces, +multiple generators (PLA and pad frame), +multiple routers (stitching, maze, river), +network comparison, +compaction, +compensation, +a VHDL compiler, +and +a silicon compiler that places-and-routes standard cells. +.PP +In addition to the text terminal used to invoke the program, +Electric uses a color display with a mouse as a work station. +Separate windows are used for text and graphics. +.PP +If a \fIlibrary\fR disk file is mentioned on the command line, that +file is read as the initial design for editing. +In addition, the following switches are recognized: +.IP -t +specifies an initial technology. The argument must be a technology name such as +"nmos", "cmos", "mocmos" (MOSIS CMOS), "mocmossub" (MOSIS CMOS Submicron), +"bipolar" (simple Bipolar), +"schematic" (Schematic capture), or "artwork" (sketchpad mode). +.IP -m +specifies there may be multiple monitors and that Electric should look for them. + +.SH REPRESENTATION +Circuits are represented as networks that contain +\fInodes\fR and connecting \fIarcs\fR. +The nodes are electrical components such as transistors, logic gates, and +contacts. +The arcs are simply wires that connect the nodes. +In addition, each node has a set of \fIports\fR which are the sites +of arc connection. +A \fItechnology\fR, then, is simply a set of primitive nodes and arcs +that are the building blocks of circuits designed in that environment. +.PP +Collections of nodes and arcs can also be aggregated into +\fIfacets\fR of \fIcells\fR which can be used higher +in the hierarchy to act as nodes. +These user-defined nodes have ports that come from internal nodes +whose ports are \fIexported\fR. +Facets are collected in \fIlibraries\fR which contain a hierarchically +consistent design. +.PP +Arcs have properties that help constrain the design. +For example, an arc may rotate arbitrarily or be fixed in their angle. +Arcs can also be stretchable or \fIrigid\fR under modification of their +connecting nodes. +These constraints propagate hierarchically from the bottom-up. + +.SH TECHNOLOGIES +A large set of technologies is provided in Electric. +These can be modified with the technology editor, or completely +new technologies can be created. +The following paragraphs describe some of the basic technologies. +.PP +The nMOS technologies have arcs available in Metal, Polysilicon, and Diffusion. +The primitive nodes include normal contacts, +buried contacts, transistors, and "pins" for making arc corners. +Transistors may be serpentine and the pure layer nodes may be polygonally +described with the \fBnode trace\fR command. +The "nmos" technology has the standard Mead&Conway design rules. +.PP +The CMOS technologies have arcs available in Metal, Polysilicon, and Diffusion. +The Diffusion arcs may be found in a P-well implant or in a P+ implant. +Thus, there are two types of metal-to-diffusion contacts, two types +of diffusion pins, and two types of transistors: in P-well and in P+ implant. +As with nMOS, the transistors may be serpentine and the pure layer primitives +may be polygonally defined. +The "cmos" technology has the standard design rules according to Griswold; +the "mocmos" technology has design rules for the MOSIS CMOS process (double metal); +the "mocmossub" technology has design rules for the MOSIS CMOS Submicron process (double poly and up to 6 metal); +the "rcmos" technology has round geometry for the MOSIS CMOS process. +.PP +The "schematic" technology provides basic symbols for doing schematic capture. +It contains the logic symbols: BUFFER, AND, OR, and XOR. +Negating bubbles can be placed by negating a connecting arc. +There are also more complex components such as +flip-flop, off-page-connector, black-box, meter, and power source. +Finally, there are the electrical components: +transistor, resistor, diode, capacitor, and inductor. +Two arc types exist for normal wires and variable-width busses. +.PP +The "artwork" technology is a sketchpad environment for doing +general-purpose graphics. +Components can be placed with arbitrary color and shape. +.PP +The "generic" technology exists for those miscellaneous purposes that do +not fall into the domain of other technologies. +It has the universal arc and pin which can connect to ANY other object +and are therefore useful in mixed-technology designs. +The invisible arc can be used for constraining two nodes without +making a connection. +The unrouted arc can be used for electrical connections that are +to be routed later with real wires. +The facet-center primitive, when placed in a facet, defines +the cursor origin on instances of that facet. + +.SH "DESIGN-RULE CHECKING" +The incremental design-rule checker is normally on and watches all changes +made to the circuit. +It does not correct but prints error messages when design rules are violated. +Hierarchy is not handled, so the contents of subfacets are not checked. +.PP +The hierarchical checker looks all the way down the circuit for all design-rules. +Another option allows an input deck to prepared for ECAD's Dracula +design-rule checker. + +.SH COMPACTION +The compactor attempts to reduce the size of a facet by removing unnecessary +space between elements. +When invoked it will +compact in the vertical and horizontal directions until it can find no way +to compact the facet any further. +It does not do hierarchical compaction, does not guarantee optimal compaction, +nor can it handle non-manhattan geometry properly. +The compactor will also spread out the facet to guarantee no design-rule +violations, if the "spread" option is set. + +.SH SIMULATION +There are many simulator interfaces: +ESIM (the default simulator: switch-level for nMOS without timing), +RSIM (switch-level for MOS with timing), +RNL (switch-level for MOS with timing and LISP front-end), +MOSSIM (switch-level for MOS with timing), +COSMOS (switch-level for MOS with timing), +VERILOG (Cadence simulator), +TEXSIM (a commercial simulator), +SILOS (a commercial simulator), +ABEL (PAL generator/simulator for schematic), and +SPICE (circuit level). +MOSSIM, COSMOS, VERILOG, TEXSIM, SILOS, and ABEL +do not actually simulate: they only write an input deck of your circuit. +.PP +In preparation for most simulators, it is necessary to +export those ports that you wish to manipulate or examine. +You must also export power and ground ports. +.PP +In preparation for SPICE simulation, you must export power and ground signals and. +explicitly connect them to source nodes. +The source should then be parameterized to indicate the amount and whether +it is voltage or current. +For example, to make a 5 volt supply, create a source node and set the SPICE card to: +"DC 5". +Next, all input ports must be exported and connected to the positive side +of sources. +Next, all values that are being plotted must be exported and have meter nodes +placed on them. +The node should have the top and bottom ports connected appropriately. + +.SH "PLA GENERATION" +There are two PLA generators, one specific to nMOS layout, and another +specific to CMOS layout. +The nMOS PLA generator reads a single personality table and generates the +array and all driving circuitry including power and ground connections. +The CMOS PLA generator reads two personality tables (AND and OR) and also +reads a library of PLA helper components (called "pla_mocmos") and generates +the array. + +.SH ROUTING +The router is able to do river routing, maze routing, and simple facet stitching +(the explicit wiring of implicitly connected nodes that abut). +River routing runs a bus of wires between the two opposite sides of a routing channel. +The connections on each side must be in a line so that the bus runs between +two parallel sets of points. +You must use the Unrouted arc from the Generic technology +to indicate the ports to be connected. +The river router can also connect wires to the perpendicular sides of the +routing channel if one or more Unrouted wires cross these sides. +.PP +There are two stitching modes: auto stitching and mimic stitching. +In auto stitching, all ports that physically touch will be stitched. +Mimic stitching watches arcs that are created by the user +and adds similar ones at other places in the facet. + +.SH "NETWORK COMPARISON" +The network maintainer tool is able to compare the networks in the two +facets being displayed on the screen. +Once compared, nodes in one facet can be equated with nodes in the other. +If the two networks are automorphic or otherwise difficult to distinguish, +equivalence information can be specified prior to comparison by selecting +a component in the first facet then selecting a component in the second facet. + +.SH AUTHOR +.nf +Steven M. Rubin + Static Free Software + 4119 Alpine Road + Portola Valley, Ca 94028 + +Also a cast of thousands: + Philip Attfield (Queens University): Polygon merging, facet dates + Ron Bolton (University of Saskatchewan): Miscellaneous help + Mark Brinsmead (Calgary): Apollo porting + Stefano Concina (Schlumberger): Polygon clipping + Peter Gallant (Queen's University): ALS simulation + T. J. Goodman (University of Canterbury) TEXSIM simulation + D. Guptill (Technical University of Nova Scotia): X-window interface + Robert Hon (Columbia University): CIF input + Sundaravarathan Iyengar (Case Western Reserve University): nMOS PLA generator + Allan Jost (Technical University of Nova Scotia): X-window interface + Wallace Kroeker (University of Calgary): Digital filter technology, CMOS PLA generator + Andrew Kostiuk (Queen's University): QUISC 1.0 Silicon compiler + Glen Lawson (S-MOS Systems): GDS-II input + David Lewis (University of Toronto): Short circuit checker + John Mohammed (Schlumberger): Miscellaneous help + Mark Moraes (University of Toronto): X-window interface + Sid Penstone (Queens University): many technologies, GDS-II output, SPICE improvements, SILOS simulation, GENERIC simulation + J. P. Polonovski (Ecole Polytechnique, France): Memory management improvement + Kevin Ryan (Technical University of Nova Scotia): X-window interface + Nora Ryan (Schlumberger): Technology translation, Compaction + Brent Serbin (Queen's University): ALS Simulator + Lyndon Swab (Queen's University): Northern Telecom CMOS technologies + Brian W. Thomson (University of Toronto): Mimic stitcher, RSIM interface + Burnie West (Schlumberger): Network maintainer help, bipolar technology + Telle Whitney (Schlumberger): River router + Rob Winstanley (University of Calgary): CIF input, RNL interface + Russell Wright (Queen's University): Lots of help + David J. Yurach (Queen's University): QUISC 2.0 Silicon compiler +.fi + +.SH "SEE ALSO" +Rubin, Steven M., "A General-Purpose Framework for CAD Algorithms", +\fIIEEE Communications\fR, Special Issue on Communications and VLSI, May 1991. +.br +Rubin, Steven M., \fIComputer Aids for VLSI Design\fR, Addison-Wesley, +Reading, Massachusetts, 1987. +.br +Rubin, Steven M., "An Integrated Aid for Top-Down Electrical Design", +\fIProceedings, VLSI '83\fR (Anceau and Aas, eds.), North Holland, Amsterdam, 1983. +.br +Mead, C. and Conway, L., \fIIntroduction to VLSI Systems\fR, +Addison-Wesley, 1980. +.br +Electrical User's Guide. +.br +Electric Internals manual. + +.SH FILES +.TS +l l. +~/.cadrc Personal startup file +~/electric.log Session logging file +*.elib Binary input/output files +*.txt Text input/output files +*.cif CIF input/output files +*.pla PLA personality input files +*.map Color map files +*.mac Macro files +*.sim ESIM, RSIM, RNL, and COSMOS simulation output +rsim.in RSIM simulation binary output +rnl.in RNL simulation binary output +*.spi SPICE simulation output +*.ver VERILOG simulation output +*.ntk MOSSIM simulation output +*.sil SILOS simulation output +*.tdl TEXSIM simulation output +*.pal ABLE PAL simulation output + +/usr/local/bin/findfastshorts Fast short circuit checker +/usr/local/bin/fastshorts Slow short circuit checker +/usr/local/bin/esim Switch level simulator: ESIM +/usr/local/bin/rsim Switch level simulator: RSIM +/usr/local/bin/rnl Switch level simulator: RNL +/usr/local/bin/presim RNL and RSIM pre-filter +/usr/local/bin/spice Circuit level simulator: SPICE +/usr/local/electric/lib/nl.l RNL startup file +.TE + + + --- electric-8.07.orig/debian/patches/01_fix_build_xml.patch +++ electric-8.07/debian/patches/01_fix_build_xml.patch @@ -0,0 +1,44 @@ +diff -Nur -x '*.orig' -x '*~' electric-8.07/build.xml electric-8.07.new/build.xml +--- electric-8.07/build.xml 2008-07-23 23:57:01.000000000 +0530 ++++ electric-8.07.new/build.xml 2008-07-24 01:07:43.000000000 +0530 +@@ -75,6 +75,7 @@ + + + ++ + + + +@@ -97,8 +98,8 @@ + + +- +- ++ + + + +@@ -337,10 +338,10 @@ + + + +- ++ + +- +- ++ + + + +@@ -360,6 +361,7 @@ + + + ++ + + + --- electric-8.07.orig/debian/copyright +++ electric-8.07/debian/copyright @@ -0,0 +1,19 @@ +This package was debianized by Chris Ruffin on +Sat, 9 Sep 2000 16:50:25 -0400. + +It was downloaded from ftp://ftp.gnu.org/pub/gnu/electric/ + +Upstream Author: Static Free Software + or + Steven Rubin + +Copyright: + +Copyright (c) 2000 Static Free Software +These scripts are free software; you can redistribute it and/or modify it +under the terms of the GNU General Public License as published by the +Free Software Foundation; either version 2, or (at your option) any +later version. + +On Debian GNU/Linux systems, the complete text of the GNU General +Public License can be found in `/usr/share/common-licenses/GPL'. --- electric-8.07.orig/debian/wrappers/electric +++ electric-8.07/debian/wrappers/electric @@ -0,0 +1,12 @@ +#!/bin/sh + +if [ "$1" = "-classpath" ] +then + CLASSPATH="$2" + shift 2 +fi + +CLASSPATH="${CLASSPATH:-.}:/usr/share/java/bsh.jar:/usr/share/electric/electric.jar" +export CLASSPATH + +exec /usr/bin/java com.sun.electric.Launcher "$@" --- electric-8.07.orig/debian/install +++ electric-8.07/debian/install @@ -0,0 +1,4 @@ +electric.jar usr/share/electric/ +debian/electric.svg usr/share/icons/hicolor/scalable/apps/ +debian/electric.desktop usr/share/applications/ +debian/wrappers/electric usr/bin/ --- electric-8.07.orig/debian/ant.properties +++ electric-8.07/debian/ant.properties @@ -0,0 +1,4 @@ +ant.build.javac.source=1.5 +ant.build.javac.target=1.5 +NO3D=1 +GNU=1