--- verilog-0.8.5.orig/elab_scope.cc +++ verilog-0.8.5/elab_scope.cc @@ -23,6 +23,7 @@ # include "config.h" # include "compiler.h" # include +# include # include /* --- verilog-0.8.5.orig/emit.cc +++ verilog-0.8.5/emit.cc @@ -23,6 +23,7 @@ # include "config.h" # include +# include /* * The emit function is called to generate the output required of the --- verilog-0.8.5.orig/main.cc +++ verilog-0.8.5/main.cc @@ -41,6 +41,7 @@ ; # include +# include # include # include # include --- verilog-0.8.5.orig/elab_expr.cc +++ verilog-0.8.5/elab_expr.cc @@ -28,6 +28,8 @@ # include "netmisc.h" # include "util.h" +#include + NetExpr* PExpr::elaborate_expr(Design*des, NetScope*, bool) const { cerr << get_line() << ": internal error: I do not know how to elaborate" --- verilog-0.8.5.orig/sys_funcs.cc +++ verilog-0.8.5/sys_funcs.cc @@ -22,6 +22,8 @@ # include "config.h" # include "compiler.h" +# include +# include # include /* --- verilog-0.8.5.orig/debian/rules +++ verilog-0.8.5/debian/rules @@ -0,0 +1,70 @@ +#!/usr/bin/make -f + +build: build-stamp +build-stamp: + dh_testdir + cp -f /usr/share/misc/config.guess $(CURDIR) + cp -f /usr/share/misc/config.sub $(CURDIR) + cp -f /usr/share/misc/config.guess $(CURDIR)/vvp + cp -f /usr/share/misc/config.sub $(CURDIR)/vvp + ./configure --prefix=/usr + $(MAKE) + + # Test that build was successful; sometimes system.vpi fails to + # build :-( + test -f vpi/system.vpi + + touch build-stamp + +clean: + dh_testdir + [ ! -f Makefile ] || $(MAKE) clean + [ ! -f Makefile ] || $(MAKE) distclean + dh_clean + -rm build-stamp + -rm config.guess config.sub vvp/config.guess vvp/config.sub + + rm -f vpi/system.vpi driver/iverilog ivlpp/ivlpp ivlpp/Makefile + rm -f tgt-null/null.tgt tgt-stub/stub.tgt tgt-verilog/verilog.tgt + rm -f vpi/sys_readmem_lex.c tgt-verilog/Makefile + rm -f tgt-null/Makefile tgt-pal/Makefile tgt-stub/Makefile + rm -f syn-rules.cc syn-rules.cc.output config.h vvp/tables.cc + rm -f vvp/parse.output parse.output syn-rules.output + rm -f driver-vpi/Makefile libveriuser/config.h vpi/config.log + rm -f config.log driver/Makefile confdefs.h config.status + rm -f Makefile _pli_types.h vpi/config.status vpi/Makefile + rm -f vpi/vpi_config.h vvp/config.log tgt-vvp/vvp_config.h + rm -f tgt-edif/libedif_tgt.a + +binary-indep: build + dh_testroot + dh_testdir + # There are no architecture-independent files to be uploaded + # generated by this package. If there were any they would be + # made here. + +binary-arch: build + dh_testroot + dh_testdir + dh_clean + + dh_installdirs + $(MAKE) install prefix=`pwd`/debian/verilog/usr + mv debian/verilog/usr/man debian/verilog/usr/share + cp -a examples debian/verilog/usr/share/doc/verilog + -rm -f debian/verilog/usr/share/doc/verilog/examples/.cvsignore + + dh_installdocs *.txt + dh_installchangelogs + dh_undocumented + dh_strip + dh_compress + dh_fixperms + dh_installdeb + dh_shlibdeps + dh_gencontrol + dh_md5sums + dh_builddeb + +binary: binary-indep binary-arch +.PHONY: binary binary-arch binary-indep clean checkroot --- verilog-0.8.5.orig/debian/copyright +++ verilog-0.8.5/debian/copyright @@ -0,0 +1,14 @@ +This is Debian GNU/Linux's prepackaged version of the Icarus +Verilog Compilation System. Icarus verilog was developed by Stephen +Williams . + +This package was prepared by Hamish Moffatt . +No source changes were required. + +Original sources were obtained from + + ftp://icarus.com/pub/eda/verilog + +Copyright: ivl is licensed under the GNU General Public License. +Please refer to the full text of the GPL in /usr/share/common-licenses/GPL. + --- verilog-0.8.5.orig/debian/compat +++ verilog-0.8.5/debian/compat @@ -0,0 +1 @@ +4 --- verilog-0.8.5.orig/debian/control +++ verilog-0.8.5/debian/control @@ -0,0 +1,13 @@ +Source: verilog +Section: electronics +Priority: optional +Maintainer: Hamish Moffatt +Standards-Version: 3.7.3 +Build-Depends: gperf, debhelper (>= 4), bison, flex, libbz2-dev, autotools-dev, libreadline5-dev | libreadline-dev + +Package: verilog +Architecture: any +Depends: ${shlibs:Depends} +Description: Icarus verilog compiler + The Icarus verilog compiler for the verilog hardware description language. + The compiler can target either simulation, or netlist (EDIF). --- verilog-0.8.5.orig/debian/changelog +++ verilog-0.8.5/debian/changelog @@ -0,0 +1,219 @@ +verilog (0.8.5-1.2) unstable; urgency=medium + + * Non-maintainer upload. + * Fix FTBFS with GCC 4.3 (Closes: #455643). + + -- Luk Claes Sat, 22 Mar 2008 17:17:44 +0000 + +verilog (0.8.5-1.1) unstable; urgency=low + + * Non-maintainer upload. + * Fix double-build FTBFS by also removing “tgt-edif/libedif_tgt.a” in + the clean target (Closes: #442759). + * No longer ignore “make clean” and “make distclean” errors. Also use + “$(MAKE)” instead of “make”. + * Bump Standards-Version from 3.7.2 to 3.7.3, no changes needed. + + -- Cyril Brulebois Wed, 27 Feb 2008 16:59:44 +0100 + +verilog (0.8.5-1) unstable; urgency=low + + * New upstream patch release. Includes source changes for newer gcc and + kernel headers that were included in previous Debian uploads. + (closes: #417448) + * Add libreadline5-dev to build-dependencies, as verilog will use it + if available + * Update package description to mention EDIF output support + (closes: #403276) + * Included patch for compilation with gcc 4.3; thanks to Martin Michlmayr + (closes: #417742) + * Acknowledge NMUs. (closes: #357962, #411063) + * Update standards-revision to 3.7.2. + + -- Hamish Moffatt Sat, 28 Jul 2007 17:28:31 +1000 + +verilog (0.8-4.2) unstable; urgency=high + + * Non-maintainer upload. + * Use sysconf(_SC_PAGESIZE) instead of PAGE_SIZE macro; fixes FTBFS with + newer kernel headers. (Closes: #411063) + + -- Steinar H. Gunderson Wed, 28 Feb 2007 17:16:07 +0100 + +verilog (0.8-4.1) unstable; urgency=low + + * NMU as part of the GCC 4.1 transition. + * Remove extra qualification from C++ header file (closes: #357962) + + -- Martin Michlmayr Fri, 26 May 2006 16:23:18 +0200 + +verilog (0.8-4) unstable; urgency=low + + * Update config.guess/sub at build-time from files provided by + autotools-dev; added build-dep on autotools-dev (closes: #342514) + * Updated standards-revision to 3.6.2 + + -- Hamish Moffatt Mon, 20 Mar 2006 00:10:25 +1100 + +verilog (0.8-3) unstable; urgency=low + + * Updated config.guess/sub to work with GNU/kFreeBSD (closes: #320689) + + -- Hamish Moffatt Sat, 20 Aug 2005 01:25:45 +1000 + +verilog (0.8-2) unstable; urgency=low + + * Rebuild with g++ 4.0 + * Fix FTBFS with g++-4.0 (closes: #301388); thanks to Andreas Jochens + for the patch. Also made additional changes in netlist.h to fix + missing forward-declarations. + + -- Hamish Moffatt Sun, 31 Jul 2005 13:20:09 +0000 + +verilog (0.8-1) unstable; urgency=low + + * New official upstream release + + -- Hamish Moffatt Fri, 15 Oct 2004 19:54:34 +1000 + +verilog (0.7+20041004-1) unstable; urgency=low + + * New upstream snapshot; close to 0.8 release + + -- Hamish Moffatt Sun, 10 Oct 2004 13:30:22 +1000 + +verilog (0.7+20040915-1) unstable; urgency=low + + * New upstream snapshot + + -- Hamish Moffatt Sun, 19 Sep 2004 01:02:29 +1000 + +verilog (0.7+20040828-1) unstable; urgency=medium + + * New upstream snapshot; fixes build order problem that + was creating useless packages on some architectures (closes: #236549) + * Include examples in package (closes: #269094) + + -- Hamish Moffatt Wed, 8 Sep 2004 08:04:52 +1000 + +verilog (0.7+20040606-1) unstable; urgency=low + + * New upstream snapshot + + -- Hamish Moffatt Wed, 30 Jun 2004 23:16:21 +1000 + +verilog (0.7+20040220-1) unstable; urgency=low + + * New upstream snapshot + + -- Hamish Moffatt Wed, 12 May 2004 21:16:29 +1000 + +verilog (0.7+20030815-1) unstable; urgency=low + + * New upstream snapshot; fixes build problems with gcc-3.3 (closes: #195512) + + -- Hamish Moffatt Sat, 23 Aug 2003 17:38:03 +1000 + +verilog (0.7-3) unstable; urgency=low + + * Fixed build failure due to apparent changes in flex (closes: #191201) + + -- Hamish Moffatt Thu, 8 May 2003 09:00:30 +1000 + +verilog (0.7-2) unstable; urgency=low + + * Recompile with new gcc + * Upgrade to debhelper revision 4 compatibility + + -- Hamish Moffatt Wed, 12 Mar 2003 08:52:04 +1100 + +verilog (0.7-1) unstable; urgency=low + + * New upstream release + + -- Hamish Moffatt Sun, 15 Dec 2002 23:44:46 +1100 + +verilog (0.6+20021207-1) unstable; urgency=low + + * Another pre-release of 0.7 + * Upstream: fixed more insecure handling of temporary files (closes: #167614) + + -- Hamish Moffatt Sun, 8 Dec 2002 22:49:28 +1100 + +verilog (0.6+20021117-1) unstable; urgency=low + + * Pre-release of 0.7 + * Upstream: works with latest bison (closes: #167057) + * Upstream: fixed insecure handling of temporary files (closes: #167614) + + -- Hamish Moffatt Tue, 26 Nov 2002 08:33:47 +1100 + +verilog (0.6-1) unstable; urgency=low + + * New upstream release + + -- Hamish Moffatt Wed, 6 Feb 2002 20:23:00 +1100 + +verilog (0.5-1) unstable; urgency=low + + * New upstream release + * Includes recent config.guess/sub and builds OK with + g++-3.0 (closes: #104832) + + -- Hamish Moffatt Sat, 4 Aug 2001 10:06:10 +1000 + +verilog (0.4.20010728-1) unstable; urgency=low + + * Upstream snapshot release (not intended for upload to Debian) + + -- Hamish Moffatt Tue, 31 Jul 2001 23:12:24 +1000 + +verilog (0.4-1) unstable; urgency=low + + * New upstream release + + -- Hamish Moffatt Fri, 9 Feb 2001 08:18:12 +1100 + +verilog (0.3-2) unstable; urgency=low + + * Added missing build-deps for bison and flex (closes: #66683) + + -- Hamish Moffatt Tue, 1 Aug 2000 21:46:48 +1000 + +verilog (0.3-1) unstable; urgency=low + + * New upstream release + + -- Hamish Moffatt Mon, 3 Jul 2000 11:06:02 +1000 + +verilog (0.2-2) unstable; urgency=low + + * Updated copyright file with maintainer info + + -- Hamish Moffatt Sun, 16 Apr 2000 22:16:53 +1000 + +verilog (0.2-1) unstable; urgency=low + + * New upstream version + + -- Hamish Moffatt Wed, 8 Mar 2000 22:14:51 +1100 + +verilog (0.2-0rc2.1) unstable; urgency=low + + * New upstream version -- RELEASE CANDIDATE + + -- Hamish Moffatt Thu, 2 Mar 2000 22:47:58 +1100 + +verilog (0.1-2) unstable; urgency=low + + * Moved /usr/bin/ivl to /usr/lib/ivl + * Modified verilog script to set module path automatically, with warning + + -- Hamish Moffatt Fri, 3 Dec 1999 14:46:51 +1100 + +verilog (0.1-1) unstable; urgency=low + + * New package + + -- Hamish Moffatt Thu, 28 Oct 1999 10:16:54 +1000 + --- verilog-0.8.5.orig/debian/verilog.dirs +++ verilog-0.8.5/debian/verilog.dirs @@ -0,0 +1,5 @@ +usr/share/doc/verilog +usr/man/man1 +usr/bin +usr/lib +usr/lib/ivl --- verilog-0.8.5.orig/synth2.cc +++ verilog-0.8.5/synth2.cc @@ -28,6 +28,7 @@ #include #include "NetLatch.h" #include +#include #include // standard operator new using std::bad_alloc; --- verilog-0.8.5.orig/load_module.cc +++ verilog-0.8.5/load_module.cc @@ -24,6 +24,8 @@ # include "util.h" # include "parse_api.h" # include "compiler.h" +# include +# include # include # include # include --- verilog-0.8.5.orig/net_link.cc +++ verilog-0.8.5/net_link.cc @@ -23,7 +23,7 @@ # include "config.h" # include - +# include # include "netlist.h" # include # include --- verilog-0.8.5.orig/verireal.cc +++ verilog-0.8.5/verireal.cc @@ -27,6 +27,7 @@ # include # include # include +# include # include # include --- verilog-0.8.5.orig/pform.cc +++ verilog-0.8.5/pform.cc @@ -29,6 +29,8 @@ # include "PData.h" # include "PEvent.h" # include "PUdp.h" +# include +# include # include # include # include --- verilog-0.8.5.orig/t-dll-expr.cc +++ verilog-0.8.5/t-dll-expr.cc @@ -23,6 +23,7 @@ # include "config.h" # include +# include # include "t-dll.h" # include "netlist.h" --- verilog-0.8.5.orig/parse.y +++ verilog-0.8.5/parse.y @@ -28,6 +28,7 @@ # include "compiler.h" # include "pform.h" # include +# include extern void lex_start_table(); extern void lex_end_table(); --- verilog-0.8.5.orig/net_design.cc +++ verilog-0.8.5/net_design.cc @@ -23,6 +23,7 @@ # include "config.h" # include +# include /* * This source file contains all the implementations of the Design --- verilog-0.8.5.orig/elab_net.cc +++ verilog-0.8.5/elab_net.cc @@ -28,6 +28,7 @@ # include "compiler.h" # include +# include /* * This is a state flag that determines whether an elaborate_net must --- verilog-0.8.5.orig/elab_sig.cc +++ verilog-0.8.5/elab_sig.cc @@ -22,6 +22,7 @@ # include "config.h" +# include # include # include "Module.h" --- verilog-0.8.5.orig/t-dll.cc +++ verilog-0.8.5/t-dll.cc @@ -23,6 +23,7 @@ # include "config.h" # include +# include # include // sprintf() # include "compiler.h" --- verilog-0.8.5.orig/net_scope.cc +++ verilog-0.8.5/net_scope.cc @@ -25,6 +25,7 @@ # include "netlist.h" # include +# include /* * The NetScope class keeps a scope tree organized. Each node of the --- verilog-0.8.5.orig/t-dll-proc.cc +++ verilog-0.8.5/t-dll-proc.cc @@ -24,6 +24,7 @@ # include "config.h" # include +# include # include "target.h" # include "ivl_target.h"