--- xserver-xorg-driver-ati-6.5.7.3.orig/src/radeon.h +++ xserver-xorg-driver-ati-6.5.7.3/src/radeon.h @@ -147,10 +147,16 @@ CARD32 cap0_trig_cntl; CARD32 cap1_trig_cntl; CARD32 bus_cntl; - CARD32 surface_cntl; CARD32 bios_4_scratch; CARD32 bios_5_scratch; CARD32 bios_6_scratch; + CARD32 surface_cntl; + CARD32 surfaces[8][3]; + CARD32 mc_agp_location; + CARD32 mc_fb_location; + CARD32 display_base_addr; + CARD32 display2_base_addr; + CARD32 ov0_base_addr; /* Other registers to save for VT switches */ CARD32 dp_datatype; @@ -158,8 +164,6 @@ CARD32 clock_cntl_index; CARD32 amcgpio_en_reg; CARD32 amcgpio_mask; - - CARD32 surfaces[8][3]; /* CRTC registers */ CARD32 crtc_gen_cntl; --- xserver-xorg-driver-ati-6.5.7.3.orig/src/radeon_driver.c +++ xserver-xorg-driver-ati-6.5.7.3/src/radeon_driver.c @@ -129,6 +129,7 @@ static int RADEONValidateMergeModes(ScrnInfoPtr pScrn); static void RADEONSetDynamicClock(ScrnInfoPtr pScrn, int mode); static void RADEONUpdatePanelSize(ScrnInfoPtr pScrn); +static void RADEONSaveMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save); /* psuedo xinerama support */ @@ -2253,81 +2254,56 @@ } /* Set up MC_FB_LOCATION and related registers */ -static void -RADEONSetFBLocation(ScrnInfoPtr pScrn) +static void RADEONInitMemMapRegisters(ScrnInfoPtr pScrn,RADEONSavePtr save, + RADEONInfoPtr info) { - RADEONInfoPtr info = RADEONPTR(pScrn); RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); unsigned char *RADEONMMIO = info->MMIO; - CARD32 mc_fb_location; - CARD32 mc_agp_location = INREG(RADEON_MC_AGP_LOCATION); - CARD32 bus_cntl = INREG(RADEON_BUS_CNTL); - - OUTREG (RADEON_BUS_CNTL, bus_cntl | RADEON_BUS_MASTER_DIS); - RADEONWaitForIdleMMIO(pScrn); - /* This function has many problems with newer cards. - * Even with older cards, all registers changed here are not - * restored properly when X quits, this will also cause - * various problems, especially with radeonfb. - * Since we don't have DRI support for R300 and above cards, - * we just hardcode these values for now. - * Need to revisit this whole function!!! - */ + /* Default to existing values */ + save->mc_fb_location = INREG(RADEON_MC_FB_LOCATION); + save->mc_agp_location = INREG(RADEON_MC_AGP_LOCATION); + /* + * Warning: A lot of the stuff down there is fairly bogus. For example, + * we use CONFIG_APER_SIZE which is only _half_ of the PCI exposed area + * since we might expose our VRAM in 2 different non overlapping apertures + * depending on how the card is bootstrapped. + * + * This will have to be fixed some day ... + */ if (info->IsIGP) { - mc_fb_location = INREG(RADEON_NB_TOM); + save->mc_fb_location = INREG(RADEON_NB_TOM); + /* Hack ... FIXME or at least move elsewhere*/ OUTREG(RADEON_GRPH2_BUFFER_CNTL, INREG(RADEON_GRPH2_BUFFER_CNTL) & ~0x7f0000); } else #ifdef XF86DRI if ( info->directRenderingEnabled && info->drmMinor < 10 ) { - mc_fb_location = (INREG(RADEON_CONFIG_APER_SIZE) - 1) & 0xffff0000U; + save->mc_fb_location = (INREG(RADEON_CONFIG_APER_SIZE) - 1) & 0xffff0000U; } else #endif { CARD32 aper0_base = INREG(RADEON_CONFIG_APER_0_BASE); - mc_fb_location = (aper0_base >> 16) - | ((aper0_base + (INREG(RADEON_CONFIG_APER_SIZE) - 1) - ) & 0xffff0000U); + save->mc_fb_location = (aper0_base >> 16) + | ((aper0_base + (INREG(RADEON_CONFIG_APER_SIZE) - 1) + ) & 0xffff0000U); } - info->fbLocation = (mc_fb_location & 0xffff) << 16; + info->fbLocation = (save->mc_fb_location & 0xffff) << 16; - if (((mc_agp_location & 0xffff) << 16) != - ((mc_fb_location & 0xffff0000U) + 0x10000)) { - mc_agp_location = mc_fb_location & 0xffff0000U; - mc_agp_location |= (mc_agp_location + 0x10000) >> 16; + if (((save->mc_agp_location & 0xffff) << 16) != + ((save->mc_fb_location & 0xffff0000U) + 0x10000)) { + save->mc_agp_location = save->mc_fb_location & 0xffff0000U; + save->mc_agp_location |= (save->mc_agp_location + 0x10000) >> 16; } - RADEONWaitForIdleMMIO(pScrn); - - OUTREG(RADEON_MC_FB_LOCATION, mc_fb_location); - OUTREG(RADEON_MC_AGP_LOCATION, mc_agp_location); - OUTREG(RADEON_DISPLAY_BASE_ADDR, info->fbLocation); - if (info->HasCRTC2) - OUTREG(RADEON_DISPLAY2_BASE_ADDR, info->fbLocation); - OUTREG(RADEON_OV0_BASE_ADDR, info->fbLocation); - - OUTREG (RADEON_BUS_CNTL, bus_cntl); - RADEONWaitForIdleMMIO(pScrn); - - /* Set display0/1 priority up on r3/4xx in the memory controller for - * high res modes if the user specifies HIGH for displaypriority - * option. - */ - if ((info->DispPriority == 2) && IS_R300_VARIANT) { - CARD32 mc_init_misc_lat_timer = INREG(R300_MC_INIT_MISC_LAT_TIMER); - if (info->MergedFB || pRADEONEnt->HasSecondary) { - mc_init_misc_lat_timer |= 0x1100; /* display 0 and 1 */ - } else { - mc_init_misc_lat_timer |= 0x0100; /* display 0 only */ - } - OUTREG(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer); - } + save->display_base_addr = info->fbLocation; + save->display2_base_addr = info->fbLocation; + save->ov0_base_addr = info->fbLocation; } @@ -5518,6 +5494,8 @@ unsigned char *RADEONMMIO = info->MMIO; if (!fbdevHWModeInit(pScrn, pScrn->currentMode)) return FALSE; + RADEONSaveMemMapRegisters(pScrn, &info->ModeReg); + info->fbLocation = (info->ModeReg.mc_fb_location & 0xffff) << 16; info->ModeReg.surface_cntl = INREG(RADEON_SURFACE_CNTL); } else { if (!RADEONModeInit(pScrn, pScrn->currentMode)) return FALSE; @@ -5605,8 +5583,6 @@ hasDRI = info->directRenderingEnabled; #endif - RADEONSetFBLocation(pScrn); - if (!fbScreenInit(pScreen, info->FB, pScrn->virtualX, pScrn->virtualY, pScrn->xDpi, pScrn->yDpi, pScrn->displayWidth, @@ -5837,7 +5813,66 @@ return TRUE; } -/* Write common registers (initialized to 0) */ +/* Write memory mapping registers */ +static void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn, + RADEONSavePtr restore) +{ + RADEONInfoPtr info = RADEONPTR(pScrn); + unsigned char *RADEONMMIO = info->MMIO; + int i; + + /* Write memory mapping registers only if their value change + * since we must ensure no access is done while they are + * reprogrammed + */ + if (INREG(RADEON_MC_FB_LOCATION) != restore->mc_fb_location || + INREG(RADEON_MC_AGP_LOCATION) != restore->mc_agp_location) { + CARD32 tmp; + + /* Make sure engine is idle. We assume the CCE is stopped + * at this point + */ + RADEONWaitForIdleMMIO(pScrn); + + /* Stop display & memory access */ + tmp = INREG(RADEON_CRTC_EXT_CNTL); + OUTREG(RADEON_CRTC_EXT_CNTL, tmp | RADEON_CRTC_DISPLAY_DIS); + tmp = INREG(RADEON_CRTC_GEN_CNTL); + tmp &= ~RADEON_CRTC_CUR_EN; + tmp |= RADEON_CRTC_DISP_REQ_EN_B; + OUTREG(RADEON_CRTC_GEN_CNTL, tmp); + if (info->HasCRTC2) { + tmp = INREG(RADEON_CRTC2_GEN_CNTL); + tmp &= ~RADEON_CRTC2_CUR_EN; + tmp |= RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_DISP_REQ_EN_B; + OUTREG(RADEON_CRTC2_GEN_CNTL, tmp); + } + tmp = INREG(RADEON_OV0_SCALE_CNTL); + tmp &= ~RADEON_SCALER_ENABLE; + + /* Clear all surfaces */ + for (i = 0; i < 8; i++) { + OUTREG(RADEON_SURFACE0_INFO + 16 * i, 0); + OUTREG(RADEON_SURFACE0_LOWER_BOUND + 16 * i, 0); + OUTREG(RADEON_SURFACE0_UPPER_BOUND + 16 * i, 0); + } + + /* Make sure the chip settles down and set new map*/ + usleep(100000); + OUTREG(RADEON_MC_FB_LOCATION, restore->mc_fb_location); + OUTREG(RADEON_MC_AGP_LOCATION, restore->mc_agp_location); + /* Make sure map fully reached the chip */ + (void)INREG(RADEON_MC_FB_LOCATION); + + } + + /* Restore base addresses */ + OUTREG(RADEON_DISPLAY_BASE_ADDR, restore->display_base_addr); + OUTREG(RADEON_DISPLAY2_BASE_ADDR, restore->display2_base_addr); + OUTREG(RADEON_OV0_BASE_ADDR, restore->ov0_base_addr); +} + +/* Write common registers */ static void RADEONRestoreCommonRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore) { @@ -6457,6 +6492,7 @@ /* For Non-dual head card, we don't have private field in the Entity */ if (!info->HasCRTC2) { + RADEONRestoreMemMapRegisters(pScrn, restore); RADEONRestoreCommonRegisters(pScrn, restore); RADEONRestoreCrtcRegisters(pScrn, restore); RADEONRestoreFPRegisters(pScrn, restore); @@ -6474,10 +6510,12 @@ * order. Regardless the order of X server issuing the calls, we * have to ensure we set registers in the right order!!! Otherwise * we may get a blank screen. + * + * We always restore MemMap first, the saverec should be up to date + * in all cases */ if (info->IsSecondary) { - if (!pRADEONEnt->RestorePrimary && !info->IsSwitching) - RADEONRestoreCommonRegisters(pScrn, restore); + RADEONRestoreMemMapRegisters(pScrn, restore); RADEONRestoreCrtc2Registers(pScrn, restore); RADEONRestorePLL2Registers(pScrn, restore); @@ -6488,15 +6526,14 @@ if (pRADEONEnt->RestorePrimary) { pRADEONEnt->RestorePrimary = FALSE; + RADEONRestoreCommonRegisters(pScrn, &restore0); RADEONRestoreCrtcRegisters(pScrn, &restore0); RADEONRestoreFPRegisters(pScrn, &restore0); RADEONRestorePLLRegisters(pScrn, &restore0); pRADEONEnt->IsSecondaryRestored = FALSE; } } else { - if (!pRADEONEnt->IsSecondaryRestored) - RADEONRestoreCommonRegisters(pScrn, restore); - + RADEONRestoreMemMapRegisters(pScrn, restore); if (info->MergedFB) { RADEONRestoreCrtc2Registers(pScrn, restore); RADEONRestorePLL2Registers(pScrn, restore); @@ -6506,6 +6543,7 @@ info->IsSwitching) { pRADEONEnt->IsSecondaryRestored = FALSE; + RADEONRestoreCommonRegisters(pScrn, restore); RADEONRestoreCrtcRegisters(pScrn, restore); RADEONRestoreFPRegisters(pScrn, restore); RADEONRestorePLLRegisters(pScrn, restore); @@ -6520,6 +6558,19 @@ #endif } +/* Read memory map */ +static void RADEONSaveMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save) +{ + RADEONInfoPtr info = RADEONPTR(pScrn); + unsigned char *RADEONMMIO = info->MMIO; + + save->mc_fb_location = INREG(RADEON_MC_FB_LOCATION); + save->mc_agp_location = INREG(RADEON_MC_AGP_LOCATION); + save->display_base_addr = INREG(RADEON_DISPLAY_BASE_ADDR); + save->display2_base_addr = INREG(RADEON_DISPLAY2_BASE_ADDR); + save->ov0_base_addr = INREG(RADEON_OV0_BASE_ADDR); +} + /* Read common registers */ static void RADEONSaveCommonRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save) { @@ -6703,6 +6754,7 @@ RADEONInfoPtr info = RADEONPTR(pScrn); RADEONTRACE(("RADEONSaveMode(%p)\n", save)); + RADEONSaveMemMapRegisters(pScrn, save); RADEONSaveCommonRegisters(pScrn, save); if (info->IsSecondary) { RADEONSaveCrtc2Registers(pScrn, save); @@ -6731,6 +6783,7 @@ RADEONTRACE(("RADEONSave\n")); if (info->FBDev) { + RADEONSaveMemMapRegisters(pScrn, save); fbdevHWSave(pScrn); return; } @@ -6914,6 +6967,22 @@ int stop_req, max_stop_req; float read_return_rate, time_disp1_drop_priority; + /* + * Set display0/1 priority up on r3/4xx in the memory controller for + * high res modes if the user specifies HIGH for displaypriority + * option. + */ + if ((info->DispPriority == 2) && IS_R300_VARIANT) { + CARD32 mc_init_misc_lat_timer = INREG(R300_MC_INIT_MISC_LAT_TIMER); + if (info->MergedFB || pRADEONEnt->HasSecondary) { + mc_init_misc_lat_timer |= 0x1100; /* display 0 and 1 */ + } else { + mc_init_misc_lat_timer |= 0x0100; /* display 0 only */ + } + OUTREG(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer); + } + + /* R420 family not supported yet */ if (info->ChipFamily == CHIP_FAMILY_R420) return; @@ -8016,6 +8085,7 @@ info->Flags = mode->Flags; + RADEONInitMemMapRegisters(pScrn, save, info); RADEONInitCommonRegisters(save, info); if (info->IsSecondary) { if (!RADEONInitCrtc2Registers(pScrn, save, mode, info)) @@ -8396,7 +8466,6 @@ } else if (!RADEONModeInit(pScrn, pScrn->currentMode)) return FALSE; - RADEONSetFBLocation(pScrn); if (!info->IsSecondary) RADEONRestoreSurfaces(pScrn, &info->ModeReg); #ifdef XF86DRI --- xserver-xorg-driver-ati-6.5.7.3.orig/debian/copyright +++ xserver-xorg-driver-ati-6.5.7.3/debian/copyright @@ -0,0 +1,119 @@ +Copyright 1997 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that copyright +notice and this permission notice appear in supporting documentation, and +that the name of Marc Aurele La France not be used in advertising or +publicity pertaining to distribution of the software without specific, +written prior permission. Marc Aurele La France makes no representations +about the suitability of this software for any purpose. It is provided +"as-is" without express or implied warranty. + +MARC AURELE LA FRANCE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO +EVENT SHALL MARC AURELE LA FRANCE BE LIABLE FOR ANY SPECIAL, INDIRECT OR +CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, +DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER +TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +PERFORMANCE OF THIS SOFTWARE. + +Copyright 2000 Gareth Hughes +All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining a +copy of this software and associated documentation files (the "Software"), +to deal in the Software without restriction, including without limitation +the rights to use, copy, modify, merge, publish, distribute, sublicense, +and/or sell copies of the Software, and to permit persons to whom the +Software is furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice (including the next +paragraph) shall be included in all copies or substantial portions of the +Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +GARETH HUGHES BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +(c) 2004 Adam Jackson. Standard MIT license applies. + +Copyright 1999-2000 Precision Insight, Inc., Cedar Park, Texas. +All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to +deal in the Software without restriction, including without limitation the +rights to use, copy, modify, merge, publish, distribute, sublicense, and/or +sell copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice (including the next +paragraph) shall be included in all copies or substantial portions of the +Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL +PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR +OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +DEALINGS IN THE SOFTWARE. + +Copyright 1999, 2000 ATI Technologies Inc., Markham, Ontario, +Precision Insight, Inc., Cedar Park, Texas, and +VA Linux Systems Inc., Fremont, California. + +All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining +a copy of this software and associated documentation files (the +"Software"), to deal in the Software without restriction, including +without limitation on the rights to use, copy, modify, merge, +publish, distribute, sublicense, and/or sell copies of the Software, +and to permit persons to whom the Software is furnished to do so, +subject to the following conditions: + +The above copyright notice and this permission notice (including the +next paragraph) shall be included in all copies or substantial +portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +NON-INFRINGEMENT. IN NO EVENT SHALL ATI, PRECISION INSIGHT, VA LINUX +SYSTEMS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR +OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +OTHER DEALINGS IN THE SOFTWARE. + +Copyright 2003 Alex Deucher. + +All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining +a copy of this software and associated documentation files (the +"Software"), to deal in the Software without restriction, including +without limitation on the rights to use, copy, modify, merge, +publish, distribute, sublicense, and/or sell copies of the Software, +and to permit persons to whom the Software is furnished to do so, +subject to the following conditions: + +The above copyright notice and this permission notice (including the +next paragraph) shall be included in all copies or substantial +portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +NON-INFRINGEMENT. IN NO EVENT SHALL ALEX DEUCHER, OR ANY OTHER +CONTRIBUTORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +DEALINGS IN THE SOFTWARE. + +Created by Bogdan D. bogdand@users.sourceforge.net +License: GPL --- xserver-xorg-driver-ati-6.5.7.3.orig/debian/rules +++ xserver-xorg-driver-ati-6.5.7.3/debian/rules @@ -0,0 +1,88 @@ +#!/usr/bin/make -f +# debian/rules for the Debian xserver-xorg-driver-ati package. +# Copyright © 2004 Scott James Remnant +# Copyright © 2005 Daniel Stone + +# Uncomment this to turn on verbose mode. +#export DH_VERBOSE=1 + +CFLAGS = -Wall -g +ifneq (,$(findstring noopt,$(DEB_BUILD_OPTIONS))) + CFLAGS += -O0 +else + CFLAGS += -O2 +endif +ifeq (,$(findstring nostrip,$(DEB_BUILD_OPTIONS))) + INSTALL_PROGRAM += -s +endif + +DEB_HOST_ARCH ?= $(shell dpkg-architecture -qDEB_HOST_ARCH) +DEB_HOST_GNU_TYPE ?= $(shell dpkg-architecture -qDEB_HOST_GNU_TYPE) +DEB_BUILD_GNU_TYPE ?= $(shell dpkg-architecture -qDEB_BUILD_GNU_TYPE) +ifeq ($(DEB_BUILD_GNU_TYPE), $(DEB_HOST_GNU_TYPE)) + confflags += --build=$(DEB_HOST_GNU_TYPE) +else + confflags += --build=$(DEB_BUILD_GNU_TYPE) --host=$(DEB_HOST_GNU_TYPE) +endif + +# kbd_drv.a isn't phenomenally useful; kbd_drv.so more so +confflags += --disable-static + +build: build-stamp +build-stamp: + dh_testdir + + mkdir obj-$(DEB_BUILD_GNU_TYPE) + cd obj-$(DEB_BUILD_GNU_TYPE) && \ + ../configure --prefix=/usr --mandir=\$${prefix}/share/man \ + --infodir=\$${prefix}/share/info $(confflags) \ + CFLAGS="$(CFLAGS)" + cd obj-$(DEB_BUILD_GNU_TYPE) && $(MAKE) + + touch build-stamp + +clean: + dh_testdir + dh_testroot + rm -f build-stamp + + rm -f config.cache config.log config.status + rm -f */config.cache */config.log */config.status + rm -f conftest* */conftest* + rm -rf autom4te.cache */autom4te.cache + rm -rf obj-* + + dh_clean + +install: build + dh_testdir + dh_testroot + dh_clean -k + dh_installdirs + + cd obj-$(DEB_BUILD_GNU_TYPE) && $(MAKE) DESTDIR=$(CURDIR)/debian/tmp install + +# Build architecture-dependent files here. +binary-arch: build install + dh_testdir + dh_testroot + + dh_installdocs + dh_installchangelogs + dh_install --sourcedir=debian/tmp + dh_link + dh_strip + dh_compress + dh_fixperms + dh_installdeb + dh_shlibdeps + dh_gencontrol + dh_md5sums + dh_builddeb + +# Build architecture-independent files here. +binary-indep: build install +# Nothing to do + +binary: binary-indep binary-arch +.PHONY: build clean binary-indep binary-arch binary install --- xserver-xorg-driver-ati-6.5.7.3.orig/debian/xserver-xorg-driver-ati.install +++ xserver-xorg-driver-ati-6.5.7.3/debian/xserver-xorg-driver-ati.install @@ -0,0 +1,3 @@ +usr/lib/xorg/modules/drivers/*.so +usr/lib/xorg/modules/multimedia/*.so +usr/share/man/man4/* --- xserver-xorg-driver-ati-6.5.7.3.orig/debian/ppc-fix.patch +++ xserver-xorg-driver-ati-6.5.7.3/debian/ppc-fix.patch @@ -0,0 +1,360 @@ +diff -urN xc-COMMIT/programs/Xserver/hw/xfree86/drivers/ati/radeon.h xc-HEAD/programs/Xserver/hw/xfree86/drivers/ati/radeon.h +--- xc-COMMIT/programs/Xserver/hw/xfree86/drivers/ati/radeon.h 2005-10-10 15:42:37.000000000 +1000 ++++ xc-HEAD/programs/Xserver/hw/xfree86/drivers/ati/radeon.h 2005-10-24 10:41:14.000000000 +1000 +@@ -146,10 +146,16 @@ + CARD32 cap0_trig_cntl; + CARD32 cap1_trig_cntl; + CARD32 bus_cntl; +- CARD32 surface_cntl; + CARD32 bios_4_scratch; + CARD32 bios_5_scratch; + CARD32 bios_6_scratch; ++ CARD32 surface_cntl; ++ CARD32 surfaces[8][3]; ++ CARD32 mc_agp_location; ++ CARD32 mc_fb_location; ++ CARD32 display_base_addr; ++ CARD32 display2_base_addr; ++ CARD32 ov0_base_addr; + + /* Other registers to save for VT switches */ + CARD32 dp_datatype; +@@ -157,8 +163,6 @@ + CARD32 clock_cntl_index; + CARD32 amcgpio_en_reg; + CARD32 amcgpio_mask; +- +- CARD32 surfaces[8][3]; + + /* CRTC registers */ + CARD32 crtc_gen_cntl; +diff -urN xc-COMMIT/programs/Xserver/hw/xfree86/drivers/ati/radeon_driver.c xc-HEAD/programs/Xserver/hw/xfree86/drivers/ati/radeon_driver.c +--- xc-COMMIT/programs/Xserver/hw/xfree86/drivers/ati/radeon_driver.c 2005-10-10 15:42:37.000000000 +1000 ++++ xc-HEAD/programs/Xserver/hw/xfree86/drivers/ati/radeon_driver.c 2005-10-24 11:30:54.000000000 +1000 +@@ -129,6 +129,7 @@ + static int RADEONValidateMergeModes(ScrnInfoPtr pScrn); + static void RADEONSetDynamicClock(ScrnInfoPtr pScrn, int mode); + static void RADEONUpdatePanelSize(ScrnInfoPtr pScrn); ++static void RADEONSaveMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save); + + /* psuedo xinerama support */ + +@@ -2238,81 +2239,56 @@ + } + + /* Set up MC_FB_LOCATION and related registers */ +-static void +-RADEONSetFBLocation(ScrnInfoPtr pScrn) ++static void RADEONInitMemMapRegisters(ScrnInfoPtr pScrn,RADEONSavePtr save, ++ RADEONInfoPtr info) + { +- RADEONInfoPtr info = RADEONPTR(pScrn); + RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); + unsigned char *RADEONMMIO = info->MMIO; +- CARD32 mc_fb_location; +- CARD32 mc_agp_location = INREG(RADEON_MC_AGP_LOCATION); +- CARD32 bus_cntl = INREG(RADEON_BUS_CNTL); +- +- OUTREG (RADEON_BUS_CNTL, bus_cntl | RADEON_BUS_MASTER_DIS); +- RADEONWaitForIdleMMIO(pScrn); + +- /* This function has many problems with newer cards. +- * Even with older cards, all registers changed here are not +- * restored properly when X quits, this will also cause +- * various problems, especially with radeonfb. +- * Since we don't have DRI support for R300 and above cards, +- * we just hardcode these values for now. +- * Need to revisit this whole function!!! +- */ ++ /* Default to existing values */ ++ save->mc_fb_location = INREG(RADEON_MC_FB_LOCATION); ++ save->mc_agp_location = INREG(RADEON_MC_AGP_LOCATION); + ++ /* ++ * Warning: A lot of the stuff down there is fairly bogus. For example, ++ * we use CONFIG_APER_SIZE which is only _half_ of the PCI exposed area ++ * since we might expose our VRAM in 2 different non overlapping apertures ++ * depending on how the card is bootstrapped. ++ * ++ * This will have to be fixed some day ... ++ */ + if (info->IsIGP) { +- mc_fb_location = INREG(RADEON_NB_TOM); ++ save->mc_fb_location = INREG(RADEON_NB_TOM); + ++ /* Hack ... FIXME or at least move elsewhere*/ + OUTREG(RADEON_GRPH2_BUFFER_CNTL, + INREG(RADEON_GRPH2_BUFFER_CNTL) & ~0x7f0000); + + } else + #ifdef XF86DRI + if ( info->directRenderingEnabled && info->drmMinor < 10 ) { +- mc_fb_location = (INREG(RADEON_CONFIG_APER_SIZE) - 1) & 0xffff0000U; ++ save->mc_fb_location = (INREG(RADEON_CONFIG_APER_SIZE) - 1) & 0xffff0000U; + } else + #endif + { + CARD32 aper0_base = INREG(RADEON_CONFIG_APER_0_BASE); + +- mc_fb_location = (aper0_base >> 16) +- | ((aper0_base + (INREG(RADEON_CONFIG_APER_SIZE) - 1) +- ) & 0xffff0000U); ++ save->mc_fb_location = (aper0_base >> 16) ++ | ((aper0_base + (INREG(RADEON_CONFIG_APER_SIZE) - 1) ++ ) & 0xffff0000U); + } + +- info->fbLocation = (mc_fb_location & 0xffff) << 16; ++ info->fbLocation = (save->mc_fb_location & 0xffff) << 16; + +- if (((mc_agp_location & 0xffff) << 16) != +- ((mc_fb_location & 0xffff0000U) + 0x10000)) { +- mc_agp_location = mc_fb_location & 0xffff0000U; +- mc_agp_location |= (mc_agp_location + 0x10000) >> 16; ++ if (((save->mc_agp_location & 0xffff) << 16) != ++ ((save->mc_fb_location & 0xffff0000U) + 0x10000)) { ++ save->mc_agp_location = save->mc_fb_location & 0xffff0000U; ++ save->mc_agp_location |= (save->mc_agp_location + 0x10000) >> 16; + } + +- RADEONWaitForIdleMMIO(pScrn); +- +- OUTREG(RADEON_MC_FB_LOCATION, mc_fb_location); +- OUTREG(RADEON_MC_AGP_LOCATION, mc_agp_location); +- OUTREG(RADEON_DISPLAY_BASE_ADDR, info->fbLocation); +- if (info->HasCRTC2) +- OUTREG(RADEON_DISPLAY2_BASE_ADDR, info->fbLocation); +- OUTREG(RADEON_OV0_BASE_ADDR, info->fbLocation); +- +- OUTREG (RADEON_BUS_CNTL, bus_cntl); +- RADEONWaitForIdleMMIO(pScrn); +- +- /* Set display0/1 priority up on r3/4xx in the memory controller for +- * high res modes if the user specifies HIGH for displaypriority +- * option. +- */ +- if ((info->DispPriority == 2) && IS_R300_VARIANT) { +- CARD32 mc_init_misc_lat_timer = INREG(R300_MC_INIT_MISC_LAT_TIMER); +- if (info->MergedFB || pRADEONEnt->HasSecondary) { +- mc_init_misc_lat_timer |= 0x1100; /* display 0 and 1 */ +- } else { +- mc_init_misc_lat_timer |= 0x0100; /* display 0 only */ +- } +- OUTREG(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer); +- } ++ save->display_base_addr = info->fbLocation; ++ save->display2_base_addr = info->fbLocation; ++ save->ov0_base_addr = info->fbLocation; + + } + +@@ -5503,6 +5479,8 @@ + unsigned char *RADEONMMIO = info->MMIO; + + if (!fbdevHWModeInit(pScrn, pScrn->currentMode)) return FALSE; ++ RADEONSaveMemMapRegisters(pScrn, &info->ModeReg); ++ info->fbLocation = (info->ModeReg.mc_fb_location & 0xffff) << 16; + info->ModeReg.surface_cntl = INREG(RADEON_SURFACE_CNTL); + } else { + if (!RADEONModeInit(pScrn, pScrn->currentMode)) return FALSE; +@@ -5590,8 +5568,6 @@ + hasDRI = info->directRenderingEnabled; + #endif + +- RADEONSetFBLocation(pScrn); +- + if (!fbScreenInit(pScreen, info->FB, + pScrn->virtualX, pScrn->virtualY, + pScrn->xDpi, pScrn->yDpi, pScrn->displayWidth, +@@ -5830,7 +5806,66 @@ + return TRUE; + } + +-/* Write common registers (initialized to 0) */ ++/* Write memory mapping registers */ ++static void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn, ++ RADEONSavePtr restore) ++{ ++ RADEONInfoPtr info = RADEONPTR(pScrn); ++ unsigned char *RADEONMMIO = info->MMIO; ++ int i; ++ ++ /* Write memory mapping registers only if their value change ++ * since we must ensure no access is done while they are ++ * reprogrammed ++ */ ++ if (INREG(RADEON_MC_FB_LOCATION) != restore->mc_fb_location || ++ INREG(RADEON_MC_AGP_LOCATION) != restore->mc_agp_location) { ++ CARD32 tmp; ++ ++ /* Make sure engine is idle. We assume the CCE is stopped ++ * at this point ++ */ ++ RADEONWaitForIdleMMIO(pScrn); ++ ++ /* Stop display & memory access */ ++ tmp = INREG(RADEON_CRTC_EXT_CNTL); ++ OUTREG(RADEON_CRTC_EXT_CNTL, tmp | RADEON_CRTC_DISPLAY_DIS); ++ tmp = INREG(RADEON_CRTC_GEN_CNTL); ++ tmp &= ~RADEON_CRTC_CUR_EN; ++ tmp |= RADEON_CRTC_DISP_REQ_EN_B; ++ OUTREG(RADEON_CRTC_GEN_CNTL, tmp); ++ if (info->HasCRTC2) { ++ tmp = INREG(RADEON_CRTC2_GEN_CNTL); ++ tmp &= ~RADEON_CRTC2_CUR_EN; ++ tmp |= RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_DISP_REQ_EN_B; ++ OUTREG(RADEON_CRTC2_GEN_CNTL, tmp); ++ } ++ tmp = INREG(RADEON_OV0_SCALE_CNTL); ++ tmp &= ~RADEON_SCALER_ENABLE; ++ ++ /* Clear all surfaces */ ++ for (i = 0; i < 8; i++) { ++ OUTREG(RADEON_SURFACE0_INFO + 16 * i, 0); ++ OUTREG(RADEON_SURFACE0_LOWER_BOUND + 16 * i, 0); ++ OUTREG(RADEON_SURFACE0_UPPER_BOUND + 16 * i, 0); ++ } ++ ++ /* Make sure the chip settles down and set new map*/ ++ usleep(100000); ++ OUTREG(RADEON_MC_FB_LOCATION, restore->mc_fb_location); ++ OUTREG(RADEON_MC_AGP_LOCATION, restore->mc_agp_location); ++ /* Make sure map fully reached the chip */ ++ (void)INREG(RADEON_MC_FB_LOCATION); ++ ++ } ++ ++ /* Restore base addresses */ ++ OUTREG(RADEON_DISPLAY_BASE_ADDR, restore->display_base_addr); ++ OUTREG(RADEON_DISPLAY2_BASE_ADDR, restore->display2_base_addr); ++ OUTREG(RADEON_OV0_BASE_ADDR, restore->ov0_base_addr); ++} ++ ++/* Write common registers */ + static void RADEONRestoreCommonRegisters(ScrnInfoPtr pScrn, + RADEONSavePtr restore) + { +@@ -6450,6 +6485,7 @@ + + /* For Non-dual head card, we don't have private field in the Entity */ + if (!info->HasCRTC2) { ++ RADEONRestoreMemMapRegisters(pScrn, restore); + RADEONRestoreCommonRegisters(pScrn, restore); + RADEONRestoreCrtcRegisters(pScrn, restore); + RADEONRestoreFPRegisters(pScrn, restore); +@@ -6467,10 +6503,12 @@ + * order. Regardless the order of X server issuing the calls, we + * have to ensure we set registers in the right order!!! Otherwise + * we may get a blank screen. ++ * ++ * We always restore MemMap first, the saverec should be up to date ++ * in all cases + */ + if (info->IsSecondary) { +- if (!pRADEONEnt->RestorePrimary && !info->IsSwitching) +- RADEONRestoreCommonRegisters(pScrn, restore); ++ RADEONRestoreMemMapRegisters(pScrn, restore); + RADEONRestoreCrtc2Registers(pScrn, restore); + RADEONRestorePLL2Registers(pScrn, restore); + +@@ -6481,15 +6519,14 @@ + if (pRADEONEnt->RestorePrimary) { + pRADEONEnt->RestorePrimary = FALSE; + ++ RADEONRestoreCommonRegisters(pScrn, &restore0); + RADEONRestoreCrtcRegisters(pScrn, &restore0); + RADEONRestoreFPRegisters(pScrn, &restore0); + RADEONRestorePLLRegisters(pScrn, &restore0); + pRADEONEnt->IsSecondaryRestored = FALSE; + } + } else { +- if (!pRADEONEnt->IsSecondaryRestored) +- RADEONRestoreCommonRegisters(pScrn, restore); +- ++ RADEONRestoreMemMapRegisters(pScrn, restore); + if (info->MergedFB) { + RADEONRestoreCrtc2Registers(pScrn, restore); + RADEONRestorePLL2Registers(pScrn, restore); +@@ -6499,6 +6536,7 @@ + info->IsSwitching) { + pRADEONEnt->IsSecondaryRestored = FALSE; + ++ RADEONRestoreCommonRegisters(pScrn, restore); + RADEONRestoreCrtcRegisters(pScrn, restore); + RADEONRestoreFPRegisters(pScrn, restore); + RADEONRestorePLLRegisters(pScrn, restore); +@@ -6513,6 +6551,19 @@ + #endif + } + ++/* Read memory map */ ++static void RADEONSaveMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save) ++{ ++ RADEONInfoPtr info = RADEONPTR(pScrn); ++ unsigned char *RADEONMMIO = info->MMIO; ++ ++ save->mc_fb_location = INREG(RADEON_MC_FB_LOCATION); ++ save->mc_agp_location = INREG(RADEON_MC_AGP_LOCATION); ++ save->display_base_addr = INREG(RADEON_DISPLAY_BASE_ADDR); ++ save->display2_base_addr = INREG(RADEON_DISPLAY2_BASE_ADDR); ++ save->ov0_base_addr = INREG(RADEON_OV0_BASE_ADDR); ++} ++ + /* Read common registers */ + static void RADEONSaveCommonRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save) + { +@@ -6696,6 +6747,7 @@ + RADEONInfoPtr info = RADEONPTR(pScrn); + + RADEONTRACE(("RADEONSaveMode(%p)\n", save)); ++ RADEONSaveMemMapRegisters(pScrn, save); + RADEONSaveCommonRegisters(pScrn, save); + if (info->IsSecondary) { + RADEONSaveCrtc2Registers(pScrn, save); +@@ -6724,6 +6776,7 @@ + + RADEONTRACE(("RADEONSave\n")); + if (info->FBDev) { ++ RADEONSaveMemMapRegisters(pScrn, save); + fbdevHWSave(pScrn); + return; + } +@@ -6907,6 +6960,22 @@ + int stop_req, max_stop_req; + float read_return_rate, time_disp1_drop_priority; + ++ /* ++ * Set display0/1 priority up on r3/4xx in the memory controller for ++ * high res modes if the user specifies HIGH for displaypriority ++ * option. ++ */ ++ if ((info->DispPriority == 2) && IS_R300_VARIANT) { ++ CARD32 mc_init_misc_lat_timer = INREG(R300_MC_INIT_MISC_LAT_TIMER); ++ if (info->MergedFB || pRADEONEnt->HasSecondary) { ++ mc_init_misc_lat_timer |= 0x1100; /* display 0 and 1 */ ++ } else { ++ mc_init_misc_lat_timer |= 0x0100; /* display 0 only */ ++ } ++ OUTREG(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer); ++ } ++ ++ + /* R420 family not supported yet */ + if (info->ChipFamily == CHIP_FAMILY_R420) return; + +@@ -8009,6 +8078,7 @@ + + info->Flags = mode->Flags; + ++ RADEONInitMemMapRegisters(pScrn, save, info); + RADEONInitCommonRegisters(save, info); + if (info->IsSecondary) { + if (!RADEONInitCrtc2Registers(pScrn, save, mode, info)) +@@ -8389,7 +8459,6 @@ + } else + if (!RADEONModeInit(pScrn, pScrn->currentMode)) return FALSE; + +- RADEONSetFBLocation(pScrn); + if (!info->IsSecondary) + RADEONRestoreSurfaces(pScrn, &info->ModeReg); + #ifdef XF86DRI --- xserver-xorg-driver-ati-6.5.7.3.orig/debian/changelog +++ xserver-xorg-driver-ati-6.5.7.3/debian/changelog @@ -0,0 +1,46 @@ +xserver-xorg-driver-ati (1:6.5.7.3-0ubuntu2) dapper; urgency=low + + * Provide xserver-xorg-driver (closes: Malone #29004). + + -- Colin Watson Wed, 15 Mar 2006 12:26:30 +0000 + +xserver-xorg-driver-ati (1:6.5.7.3-0ubuntu1) dapper; urgency=low + + * New upstream release. + * Also install Rage Theatre multimedia modules. + + -- Daniel Stone Wed, 4 Jan 2006 17:21:27 +1100 + +xserver-xorg-driver-ati (1:6.5.7-0ubuntu3) dapper; urgency=low + + * Add missing Build-Depends (x11proto-fonts-dev, x11proto-randr-dev, + x11proto-render-dev, libdrm (>> 1.0.5), x11proto-xf86dri-dev). + + -- Daniel Stone Mon, 5 Dec 2005 14:52:47 +1100 + +xserver-xorg-driver-ati (1:6.5.7-0ubuntu2) dapper; urgency=low + + * Apply patch from https://bugs.freedesktop.org/attachment.cgi?id=3620 to + fix hard crash on powerpc. The patch is also stored in + debian/ppc-fix.patch. + NOTE: according to benh the patch still needs some extra polishing. + + -- Fabio M. Di Nitto Fri, 25 Nov 2005 11:34:33 +0100 + +xserver-xorg-driver-ati (1:6.5.7-0ubuntu1) dapper; urgency=low + + * New upstream release. + + -- Daniel Stone Tue, 22 Nov 2005 13:25:16 +1100 + +xserver-xorg-driver-ati (1:6.5.6.1-1) dapper; urgency=low + + * New upstream release. + + -- Daniel Stone Tue, 25 Oct 2005 18:01:13 +1000 + +xserver-xorg-driver-ati (1:6.5.6-1) breezy; urgency=low + + * First xserver-xorg-driver-ati release. + + -- Daniel Stone Wed, 6 Jul 2005 15:48:17 +1000 --- xserver-xorg-driver-ati-6.5.7.3.orig/debian/control +++ xserver-xorg-driver-ati-6.5.7.3/debian/control @@ -0,0 +1,31 @@ +Source: xserver-xorg-driver-ati +Section: x11 +Priority: optional +Maintainer: Daniel Stone +Build-Depends: debhelper (>= 4.0.0), pkg-config, xserver-xorg-dev, x11proto-gl-dev, x11proto-xext-dev, x11proto-core-dev, x11proto-video-dev, x11proto-xinerama-dev, x11proto-xf86misc-dev, libgl1-mesa-dev | libgl-dev, x11proto-fonts-dev, x11proto-randr-dev, x11proto-render-dev, libdrm-dev (>> 1.0.5), x11proto-xf86dri-dev +Standards-Version: 3.6.1.0 + +Package: xserver-xorg-driver-ati +Architecture: any +Depends: ${shlibs:Depends}, ${misc:Depends}, xserver-xorg-core (>= 1:0.99.0-1) +Replaces: xserver-xorg (<< 6.8.2-35), xserver-xorg-driver-atimisc, xserver-xorg-driver-r128, xserver-xorg-driver-radeon +Conflicts: xserver-xorg-driver-atimisc, xserver-xorg-driver-r128, xserver-xorg-driver-radeon +Provides: xserver-xorg-driver, xserver-xorg-driver-atimisc, xserver-xorg-driver-r128, xserver-xorg-driver-radeon +Description: X.Org X server -- ATI display driver + This driver for the X.Org X server (see xserver-xorg for a further description) + provides support for the ATI Mach, Rage, Radeon, and FireGL series. It + provides the 'atimisc', 'r128' and 'radeon' sub-drivers. + . + Note that this is not the same as the ATI-provided, binary-only, 'fglrx' + driver, which provides additional 3D functionality for some newer Radeon + cards, but is not supported. + . + This driver provides support for Mach, Rage, Rage128, Radeon, and most + FireGL series ATI cards. + . + More information about X.Org can be found at: + + + . + This module can be found as the module 'driver/xf86-video-ati' at + :pserver:anoncvs@cvs.freedesktop.org:/cvs/xorg --- xserver-xorg-driver-ati-6.5.7.3.orig/debian/compat +++ xserver-xorg-driver-ati-6.5.7.3/debian/compat @@ -0,0 +1 @@ +4