alliance 5.1.1-1.1build1 source package in Ubuntu

Changelog

alliance (5.1.1-1.1build1) bionic; urgency=high

  * No change rebuild to pick up -fPIE compiler default

 -- Balint Reczey <email address hidden>  Tue, 03 Apr 2018 12:12:20 +0000

Upload details

Uploaded by:
Balint Reczey on 2018-04-03
Uploaded to:
Bionic
Original maintainer:
Ubuntu Developers
Architectures:
any
Section:
electronics
Urgency:
Very Urgent

See full publishing history Publishing

Series Pocket Published Component Section
Bionic release on 2018-04-03 universe electronics

Downloads

File Size SHA-256 Checksum
alliance_5.1.1.orig.tar.bz2 4.3 MiB 50f1832228d3bda6129df0e65a5afc38168f4c7ddd01ec09d3f0d752e782f74c
alliance_5.1.1-1.1build1.debian.tar.xz 12.8 KiB 5f5219f28360fb37349d0a11c8c7c6c8d45abcb1ca6f2d8662a26e9de0c6c96b
alliance_5.1.1-1.1build1.dsc 2.1 KiB 0d7e53d4593a291a02ea7f7429994859172406bf4509473ce3085c7dbd591e4e

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Binary packages built by this source

alliance: VLSI CAD Tools

 Alliance is a complete set of free CAD tools and portable libraries for
 VLSI design. It includes a VHDL compiler and simulator, logic synthesis
 tools, and automatic place and route tools.
 .
 A complete set of portable CMOS libraries is provided, including a
 RAM generator, a ROM generator and a data-path compiler.
 .
 Alliance is the result of more than ten years effort spent at ASIM department
 of LIP6 laboratory of the Pierre et Marie Curie University (Paris VI, France).
 .
 Alliance has been used for research projects such as the 875 000 transistors
 StaCS superscalar microprocessor and 400 000 transistors IEEE Gigabit HSL
 Router.
 .
 Alliance provides CAD tools covering most of all the digital design flow:
  * VHDL Compilation and Simulation
  * Model checking and formal proof
  * RTL and Logic synthesis
  * Data-Path compilation
  * Macro-cells generation
  * Place and route
  * Layout edition
  * Netlist extraction and verification
  * Design rules checking

alliance-dbgsym: debug symbols for alliance