alliance 5.1.1-3 source package in Ubuntu


alliance (5.1.1-3) unstable; urgency=medium

  * Fix FTBFS with recent TeX Live by specifying the input encoding
    of overview.tex.

 -- Adrian Bunk <email address hidden>  Fri, 20 Apr 2018 11:04:52 +0300

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Uploaded by:
Debian QA Group on 2018-04-20
Uploaded to:
Original maintainer:
Debian QA Group
Medium Urgency

See full publishing history Publishing

Series Pocket Published Component Section
Eoan release on 2019-04-18 universe electronics
Disco release on 2018-10-30 universe electronics
Cosmic release on 2018-05-05 universe electronics


File Size SHA-256 Checksum
alliance_5.1.1-3.dsc 2.0 KiB a47dc417b4ee67a2a430b1a6aee799f605925a1ca2c14c0a91e7af6853902229
alliance_5.1.1.orig.tar.bz2 4.3 MiB 50f1832228d3bda6129df0e65a5afc38168f4c7ddd01ec09d3f0d752e782f74c
alliance_5.1.1-3.debian.tar.xz 13.5 KiB bad0de61df136e5924f2301cd59a2095a1bfff023a713b7607c68592ce3726da

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Binary packages built by this source

alliance: VLSI CAD Tools

 Alliance is a complete set of free CAD tools and portable libraries for
 VLSI design. It includes a VHDL compiler and simulator, logic synthesis
 tools, and automatic place and route tools.
 A complete set of portable CMOS libraries is provided, including a
 RAM generator, a ROM generator and a data-path compiler.
 Alliance is the result of more than ten years effort spent at ASIM department
 of LIP6 laboratory of the Pierre et Marie Curie University (Paris VI, France).
 Alliance has been used for research projects such as the 875 000 transistors
 StaCS superscalar microprocessor and 400 000 transistors IEEE Gigabit HSL
 Alliance provides CAD tools covering most of all the digital design flow:
  * VHDL Compilation and Simulation
  * Model checking and formal proof
  * RTL and Logic synthesis
  * Data-Path compilation
  * Macro-cells generation
  * Place and route
  * Layout edition
  * Netlist extraction and verification
  * Design rules checking

alliance-dbgsym: debug symbols for alliance