libverilog-perl 3.403-1 source package in Ubuntu
Changelog
libverilog-perl (3.403-1) unstable; urgency=medium [ gregor herrmann ] * Strip trailing slash from metacpan URLs. [ Florian Schlichting ] * Import Upstream version 3.403 * Email change: Florian Schlichting -> <email address hidden> * Bump copyright years * Declare compliance with Debian Policy 3.9.5 -- Florian Schlichting <email address hidden> Sat, 15 Mar 2014 21:57:49 +0100
Upload details
- Uploaded by:
- Debian Perl Group
- Uploaded to:
- Sid
- Original maintainer:
- Debian Perl Group
- Architectures:
- any
- Section:
- perl
- Urgency:
- Medium Urgency
See full publishing history Publishing
Series | Published | Component | Section | |
---|---|---|---|---|
Trusty | release | universe | perl |
Downloads
File | Size | SHA-256 Checksum |
---|---|---|
libverilog-perl_3.403-1.dsc | 2.2 KiB | 053906c22c278de588c16bc99fa5823c4c06e601a6ed81914934c8472b9caeb1 |
libverilog-perl_3.403.orig.tar.gz | 543.3 KiB | f7e2108648f7af8bdf3b37d96e54f02fe2224a1948391e742b3a9ce8ab5e95b3 |
libverilog-perl_3.403-1.debian.tar.xz | 7.1 KiB | b7639e2120c5e25b52d91e4780ab9271b5452e46916928385dce0f4a519f8b76 |
Available diffs
- diff from 3.402-1 to 3.403-1 (290.1 KiB)
No changes file available.
Binary packages built by this source
- libverilog-perl: framework providing Verilog support
Verilog is a Perl framework providing Verilog support in the Perl language.
It includes:
.
* Verilog::Getopt, which parses command line options similar to C++ and VCS
* Verilog::Language, which knows the language keywords and parses numbers.
* Verilog::Netlist, which builds netlists out of Verilog files. This allows
easy scripts to determine things such as the hierarchy of modules.
* Verilog::Parser, which invokes callbacks for language tokens
* Verilog::Preproc, preprocesses the language, and allows reading
post-processed files right from Perl without temporary files.
.
It also includes a variety of useful utilities:
.
* vpassert inserts PLIish warnings and assertions for any simulator
* vppreproc preprocesses the complete Verilog 2001 and SystemVerilog
language
* vrename renames and cross-references Verilog symbols. It creates Verilog
cross references and makes it easy to rename signal and module names over
multiple files.