verilator 3.832-1 source package in Ubuntu

Changelog

verilator (3.832-1) unstable; urgency=low


  * New upstream release.
  * Bumped compat level to 9.
  * debian/control: Updated Standards-Version to 3.9.3
  * debian/copyright: Updated copyright format & years.

 -- أحمد المحمودي (Ahmed El-Mahmoudy) <email address hidden>  Thu, 08 Mar 2012 16:34:21 +0200

Upload details

Uploaded by:
Debian Electronics Team on 2012-03-09
Uploaded to:
Sid
Original maintainer:
Debian Electronics Team
Architectures:
any
Section:
electronics
Urgency:
Low Urgency

See full publishing history Publishing

Series Pocket Published Component Section
Precise release on 2012-03-20 universe electronics

Downloads

File Size SHA-256 Checksum
verilator_3.832-1.dsc 1.6 KiB dd611a5e01ac0b208cdc522e848f0ef540319567ba97e898e1f64357de9a0ca5
verilator_3.832.orig.tar.gz 1.5 MiB c1619d18406265484c612e0bcd1743785f9025e7d645194a2d52cf09095204a3
verilator_3.832-1.debian.tar.gz 7.0 KiB 72026165c6a8f54b591dd30fae4fc553aa2eda3bd837899e56f1479e3f0b07fd

Available diffs

No changes file available.

Binary packages built by this source

verilator: fast free Verilog simulator

 Verilator is the fastest free Verilog HDL simulator, and beats many commercial
 simulators. It compiles synthesizable Verilog (not test-bench code!), plus
 some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code.
 It is designed for large projects where fast simulation performance is of
 primary concern, and is especially well suited to generate executable models
 of CPUs for embedded software design teams.