verilator 3.853-1 source package in Ubuntu

Changelog

verilator (3.853-1) unstable; urgency=low


  * New upstream release.

 -- أحمد المحمودي (Ahmed El-Mahmoudy) <email address hidden>  Tue, 01 Oct 2013 23:09:16 +0200

Upload details

Uploaded by:
Debian Electronics Team on 2013-10-02
Uploaded to:
Sid
Original maintainer:
Debian Electronics Team
Architectures:
any
Section:
electronics
Urgency:
Low Urgency

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Downloads

File Size SHA-256 Checksum
verilator_3.853-1.dsc 1.6 KiB 78566a420b004d2e110f3766861f0ec409085f650b9c5558b0f14224842dce2d
verilator_3.853.orig.tar.gz 1.8 MiB 6e346b7d23be546e058a2eec7102b5a5df0b0db4280079508216ff83f1654c7e
verilator_3.853-1.debian.tar.gz 7.2 KiB f38e3b469ccb31064400552826d6dfcf08859e08f92a53f66b9245b4026ac74c

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Binary packages built by this source

verilator: fast free Verilog simulator

 Verilator is the fastest free Verilog HDL simulator, and beats many commercial
 simulators. It compiles synthesizable Verilog (not test-bench code!), plus
 some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code.
 It is designed for large projects where fast simulation performance is of
 primary concern, and is especially well suited to generate executable models
 of CPUs for embedded software design teams.