verilator 3.854-1 source package in Ubuntu

Changelog

verilator (3.854-1) unstable; urgency=low


  * New upstream release.
  * debian/control: Bumped Standards-Version to 3.9.5

 -- أحمد المحمودي (Ahmed El-Mahmoudy) <email address hidden>  Tue, 03 Dec 2013 09:22:24 +0200

Upload details

Uploaded by:
Debian Electronics Team on 2013-12-03
Uploaded to:
Sid
Original maintainer:
Debian Electronics Team
Architectures:
any
Section:
electronics
Urgency:
Low Urgency

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Downloads

File Size SHA-256 Checksum
verilator_3.854-1.dsc 1.6 KiB efc3f865edfa970e06cccad01b3e6a1e71a4f59e3e8922492f7a870497312e5d
verilator_3.854.orig.tar.gz 1.9 MiB bcfc1985944ba1b0c51fc3db289610a884a941f6e96b26a50c4e65e78ce8f089
verilator_3.854-1.debian.tar.gz 7.3 KiB 324d1f0f38800fe703d1b0a47a9bc75da7ff4bd3d2e26841561d7388c9f16a51

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Binary packages built by this source

verilator: fast free Verilog simulator

 Verilator is the fastest free Verilog HDL simulator, and beats many commercial
 simulators. It compiles synthesizable Verilog (not test-bench code!), plus
 some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code.
 It is designed for large projects where fast simulation performance is of
 primary concern, and is especially well suited to generate executable models
 of CPUs for embedded software design teams.