verilator 3.874-1 source package in Ubuntu

Changelog

verilator (3.874-1) unstable; urgency=medium

  * Upload to unstable.
  * Drop patches that got merged upstream: install_all_manpages.diff,
    typos.diff
  * Add pkgconfig.diff patch to remove un-necessary 'libdir' field from
    pkgconfig file. lintian complained that this field had a multi-arch.
    value, yet the file is installed in /usr/share/pkgconfig

 -- أحمد المحمودي (Ahmed El-Mahmoudy) <email address hidden>  Sun, 07 Jun 2015 16:06:17 +0200

Upload details

Uploaded by:
Debian Electronics Team on 2015-06-08
Uploaded to:
Sid
Original maintainer:
Debian Electronics Team
Architectures:
any
Section:
electronics
Urgency:
Medium Urgency

See full publishing history Publishing

Series Pocket Published Component Section
Xenial release on 2015-10-22 universe electronics

Downloads

File Size SHA-256 Checksum
verilator_3.874-1.dsc 1.6 KiB 048b823088308b777b7abaff18e4c2fc9335a5cf3bb4e73616dadc672bfb1264
verilator_3.874.orig.tar.gz 1.9 MiB d20086626fdf6346d309e435881600c2d8bc8da8b3106e22d4ca4a70b98d0b1c
verilator_3.874-1.debian.tar.xz 7.0 KiB 5c03552e2c40c0953863daf302db5bc4e8f3281c24438764c412654bfcc01bdf

Available diffs

No changes file available.

Binary packages built by this source

verilator: fast free Verilog simulator

 Verilator is the fastest free Verilog HDL simulator, and beats many commercial
 simulators. It compiles synthesizable Verilog (not test-bench code!), plus
 some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code.
 It is designed for large projects where fast simulation performance is of
 primary concern, and is especially well suited to generate executable models
 of CPUs for embedded software design teams.

verilator-dbgsym: debug symbols for package verilator

 Verilator is the fastest free Verilog HDL simulator, and beats many commercial
 simulators. It compiles synthesizable Verilog (not test-bench code!), plus
 some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code.
 It is designed for large projects where fast simulation performance is of
 primary concern, and is especially well suited to generate executable models
 of CPUs for embedded software design teams.