verilator 3.916-1 source package in Ubuntu

Changelog

verilator (3.916-1) unstable; urgency=medium

  * New upstream release
  * Dropped patches:
    + fix_spelling.diff, applied upstream
    + fix_smoke.diff, no longer needed
  * Switch to a secure URL in watch file

 -- أحمد المحمودي (Ahmed El-Mahmoudy) <email address hidden>  Sun, 26 Nov 2017 01:27:17 +0100

Upload details

Uploaded by:
Debian Electronics Team on 2017-11-26
Uploaded to:
Sid
Original maintainer:
Debian Electronics Team
Architectures:
any
Section:
electronics
Urgency:
Medium Urgency

See full publishing history Publishing

Series Pocket Published Component Section

Downloads

File Size SHA-256 Checksum
verilator_3.916-1.dsc 1.6 KiB 162ca1e66d4f64388415b7915036168dfb67afe25f5331a6ae7227f259ecf17c
verilator_3.916.orig.tar.gz 2.0 MiB c8729b762bc40f90afecf5a412331d8c38ee751a177b2db925161da6e9d5b7f0
verilator_3.916-1.debian.tar.xz 7.4 KiB 973913384accdc05c082d336ea5445d85aa0b4807b38b9d0e3b9be70dcf78393

Available diffs

No changes file available.

Binary packages built by this source

verilator: fast free Verilog simulator

 Verilator is the fastest free Verilog HDL simulator, and beats many commercial
 simulators. It compiles synthesizable Verilog (not test-bench code!), plus
 some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code.
 It is designed for large projects where fast simulation performance is of
 primary concern, and is especially well suited to generate executable models
 of CPUs for embedded software design teams.

verilator-dbgsym: debug symbols for verilator