verilator 3.916-1build1 source package in Ubuntu

Changelog

verilator (3.916-1build1) bionic; urgency=medium

  * No-change rebuild to pick up the shared flex library.

 -- Matthias Klose <email address hidden>  Tue, 20 Feb 2018 07:11:15 +0000

Upload details

Uploaded by:
Matthias Klose on 2018-02-20
Uploaded to:
Bionic
Original maintainer:
Debian Electronics Team
Architectures:
any
Section:
electronics
Urgency:
Medium Urgency

See full publishing history Publishing

Series Pocket Published Component Section
Bionic release on 2018-02-20 universe electronics

Downloads

File Size SHA-256 Checksum
verilator_3.916.orig.tar.gz 2.0 MiB c8729b762bc40f90afecf5a412331d8c38ee751a177b2db925161da6e9d5b7f0
verilator_3.916-1build1.debian.tar.xz 7.5 KiB 2700b54a0ea253ca87774c64a55782103e234b4de7f49d98bcabc8dc35822031
verilator_3.916-1build1.dsc 2.0 KiB 456a21d8489a48c6bb1f6e62c4d845cae37b606c441905f39e16a3f0156ce3de

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Binary packages built by this source

verilator: fast free Verilog simulator

 Verilator is the fastest free Verilog HDL simulator, and beats many commercial
 simulators. It compiles synthesizable Verilog (not test-bench code!), plus
 some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code.
 It is designed for large projects where fast simulation performance is of
 primary concern, and is especially well suited to generate executable models
 of CPUs for embedded software design teams.

verilator-dbgsym: debug symbols for verilator