verilator 4.006-1 source package in Ubuntu

Changelog

verilator (4.006-1) unstable; urgency=medium

  * New upstream release
  * Build with SystemC support
  * Suggest libsystemc-dev instead of systemc
  * Updated standards version to 4.2.0
  * shebang.diff patch: add bin_verilator_gantt
  * Only enable SystemC to archs. supported by the library

 -- أحمد المحمودي (Ahmed El-Mahmoudy) <email address hidden>  Mon, 12 Nov 2018 13:38:21 +0100

Upload details

Uploaded by:
Debian Electronics Team on 2018-11-15
Uploaded to:
Sid
Original maintainer:
Debian Electronics Team
Architectures:
any
Section:
electronics
Urgency:
Medium Urgency

See full publishing history Publishing

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Downloads

File Size SHA-256 Checksum
verilator_4.006-1.dsc 1.6 KiB 107fc723ad7655b37f0e5b018fa35aabe183f87af2fa7a791fd533efced0e841
verilator_4.006.orig.tar.gz 2.4 MiB 31dc2d2dcdfa09e935e9622169005e34262471740e00c4dde0941267e75dde6e
verilator_4.006-1.debian.tar.xz 7.9 KiB 55f50a2c07637eb2acf20bd07d9a4a61598a5907b12e524e6f97f207f3643109

Available diffs

No changes file available.

Binary packages built by this source

verilator: fast free Verilog simulator

 Verilator is the fastest free Verilog HDL simulator, and beats many commercial
 simulators. It compiles synthesizable Verilog (not test-bench code!), plus
 some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code.
 It is designed for large projects where fast simulation performance is of
 primary concern, and is especially well suited to generate executable models
 of CPUs for embedded software design teams.

verilator-dbgsym: debug symbols for verilator