verilator 4.008-1 source package in Ubuntu

Changelog

verilator (4.008-1) unstable; urgency=medium

  * New upstream release
  * Update standards version to 4.2.1, no changes needed
  * Add typos.diff patch to fix spelling mistakes

 -- أحمد المحمودي (Ahmed El-Mahmoudy) <email address hidden>  Sun, 16 Dec 2018 05:59:48 +0100

Upload details

Uploaded by:
Debian Electronics Team on 2018-12-16
Uploaded to:
Sid
Original maintainer:
Debian Electronics Team
Architectures:
any
Section:
electronics
Urgency:
Medium Urgency

See full publishing history Publishing

Series Pocket Published Component Section

Downloads

File Size SHA-256 Checksum
verilator_4.008-1.dsc 1.6 KiB 8ca001dc5155c26dc284a18cdb1be34a5b487e17c9d6c6da860c4ae0207ea7db
verilator_4.008.orig.tar.gz 2.4 MiB d5cef6edd3bdb7754776d902daae7a7e5dd662baa7c7f895cb7028b1d6910cac
verilator_4.008-1.debian.tar.xz 8.9 KiB b939ea47ba5c0d83a88a1912021dd61f3afdadccbcd19da365de572c07564133

Available diffs

No changes file available.

Binary packages built by this source

verilator: fast free Verilog simulator

 Verilator is the fastest free Verilog HDL simulator, and beats many commercial
 simulators. It compiles synthesizable Verilog (not test-bench code!), plus
 some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code.
 It is designed for large projects where fast simulation performance is of
 primary concern, and is especially well suited to generate executable models
 of CPUs for embedded software design teams.

verilator-dbgsym: debug symbols for verilator