verilator 4.008-2 source package in Ubuntu

Changelog

verilator (4.008-2) unstable; urgency=medium

  * Promote libsystemc-dev to Recommends
  * Added reproducible_build.diff patch for verilated_vcd_c.cpp to make it
    reproducible.
    Thanks to Anoop Nadig <email address hidden>

 -- أحمد المحمودي (Ahmed El-Mahmoudy) <email address hidden>  Fri, 21 Dec 2018 05:18:18 +0100

Upload details

Uploaded by:
Debian Electronics Team on 2018-12-21
Uploaded to:
Sid
Original maintainer:
Debian Electronics Team
Architectures:
any
Section:
electronics
Urgency:
Medium Urgency

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Series Pocket Published Component Section

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File Size SHA-256 Checksum
verilator_4.008-2.dsc 1.6 KiB 753e01c2d3c2f1b0681218d1f08eb1a447d230ac4ff410ce5d4eb7586ba38b2f
verilator_4.008.orig.tar.gz 2.4 MiB d5cef6edd3bdb7754776d902daae7a7e5dd662baa7c7f895cb7028b1d6910cac
verilator_4.008-2.debian.tar.xz 9.3 KiB 5fd2e3b430469eeaac93d6869b97d890e1e6c706295a312bbdb1c6c6cc1d5b8e

Available diffs

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Binary packages built by this source

verilator: fast free Verilog simulator

 Verilator is the fastest free Verilog HDL simulator, and beats many commercial
 simulators. It compiles synthesizable Verilog (not test-bench code!), plus
 some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code.
 It is designed for large projects where fast simulation performance is of
 primary concern, and is especially well suited to generate executable models
 of CPUs for embedded software design teams.

verilator-dbgsym: debug symbols for verilator