verilator 4.010-1 source package in Ubuntu

Changelog

verilator (4.010-1) unstable; urgency=medium

  * New upstream release
  * Update copyright years
  * Update to standards version 4.3.0
  * Bump to compat level 12
  * Refresh patches

 -- أحمد المحمودي (Ahmed El-Mahmoudy) <email address hidden>  Sun, 10 Feb 2019 04:49:41 +0100

Upload details

Uploaded by:
Debian Electronics Team on 2019-02-10
Uploaded to:
Sid
Original maintainer:
Debian Electronics Team
Architectures:
any
Section:
electronics
Urgency:
Medium Urgency

See full publishing history Publishing

Series Pocket Published Component Section
Disco release on 2019-02-10 universe electronics

Downloads

File Size SHA-256 Checksum
verilator_4.010-1.dsc 1.6 KiB 063506a2f98a1466d6e462ce2603b2f8ce05fbbac9382d069032b8a032a63597
verilator_4.010.orig.tar.gz 2.4 MiB 5651748fe28e373ebf7a6364f5e7935ec9b39d29671f683f366e99d5e157d571
verilator_4.010-1.debian.tar.xz 9.2 KiB 2359ec28065546dbd760b1f01590603271440a7fdcc246f0e2f503ddd3d5f0e6

Available diffs

No changes file available.

Binary packages built by this source

verilator: fast free Verilog simulator

 Verilator is the fastest free Verilog HDL simulator, and beats many commercial
 simulators. It compiles synthesizable Verilog (not test-bench code!), plus
 some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code.
 It is designed for large projects where fast simulation performance is of
 primary concern, and is especially well suited to generate executable models
 of CPUs for embedded software design teams.

verilator-dbgsym: debug symbols for verilator