verilator 4.016-3~build1 source package in Ubuntu

Changelog

verilator (4.016-3~build1) eoan; urgency=medium

  * Upload to ubuntu

 -- Gianfranco Costamagna <email address hidden>  Mon, 08 Jul 2019 09:29:48 +0200

Upload details

Uploaded by:
Gianfranco Costamagna on 2019-07-08
Uploaded to:
Eoan
Original maintainer:
Debian Electronics Team
Architectures:
any
Section:
electronics
Urgency:
Medium Urgency

See full publishing history Publishing

Series Pocket Published Component Section

Downloads

File Size SHA-256 Checksum
verilator_4.016.orig.tar.gz 2.4 MiB 328a8f85c4fb0ecdabbf56e3c261485234dd1c28211e413101c533fdaea9d8a1
verilator_4.016-3~build1.debian.tar.xz 9.7 KiB a312866cb9e62f06ce59e30df8f57dff5b80f3bbe17a6fa6743ec55796ccb9d4
verilator_4.016-3~build1.dsc 2.0 KiB 05ccc222c66bc10d9008315416fd178b9e4ba055787cf01fba1840353535e27b

Available diffs

View changes file

Binary packages built by this source

verilator: fast free Verilog simulator

 Verilator is the fastest free Verilog HDL simulator, and beats many commercial
 simulators. It compiles synthesizable Verilog (not test-bench code!), plus
 some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code.
 It is designed for large projects where fast simulation performance is of
 primary concern, and is especially well suited to generate executable models
 of CPUs for embedded software design teams.

verilator-dbgsym: debug symbols for verilator