verilator 4.010-1 (ppc64el binary) in ubuntu eoan

 Verilator is the fastest free Verilog HDL simulator, and beats many commercial
 simulators. It compiles synthesizable Verilog (not test-bench code!), plus
 some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code.
 It is designed for large projects where fast simulation performance is of
 primary concern, and is especially well suited to generate executable models
 of CPUs for embedded software design teams.

Details

Package version:
4.010-1
Source:
verilator 4.010-1 source package in Ubuntu
Status:
Superseded
Component:
universe
Priority:
Optional