VLSI CAD Tools

 Alliance is a complete set of free CAD tools and portable libraries for
 VLSI design. It includes a VHDL compiler and simulator, logic synthesis
 tools, and automatic place and route tools.
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 A complete set of portable CMOS libraries is provided, including a
 RAM generator, a ROM generator and a data-path compiler.
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 Alliance is the result of more than ten years effort spent at ASIM department
 of LIP6 laboratory of the Pierre et Marie Curie University (Paris VI, France).
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 Alliance has been used for research projects such as the 875 000 transistors
 StaCS superscalar microprocessor and 400 000 transistors IEEE Gigabit HSL
 Router.
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 Alliance provides CAD tools covering most of all the digital design flow:
  * VHDL Compilation and Simulation
  * Model checking and formal proof
  * RTL and Logic synthesis
  * Data-Path compilation
  * Macro-cells generation
  * Place and route
  * Layout edition
  * Netlist extraction and verification
  * Design rules checking