yosys-dbgsym 0.6-7 (s390x binary) in ubuntu yakkety

 This is a framework for Verilog RTL synthesis. It currently has extensive
 Verilog-2005 support and provides a basic set of synthesis algorithms for
 various application domains.
 .
 Yosys can be adapted to perform any synthesis job by combining the existing
 passes (algorithms) using synthesis scripts and adding additional passes as
 needed by extending the yosys C++ code base.