diff -Nru xserver-xorg-video-amdgpu-1.2.0/autogen.sh xserver-xorg-video-amdgpu-1.3.0/autogen.sh --- xserver-xorg-video-amdgpu-1.2.0/autogen.sh 2017-03-31 19:05:30.000000000 +0000 +++ xserver-xorg-video-amdgpu-1.3.0/autogen.sh 2017-03-31 19:05:30.000000000 +0000 @@ -1,14 +1,17 @@ #! /bin/sh -srcdir=`dirname $0` +srcdir=`dirname "$0"` test -z "$srcdir" && srcdir=. ORIGDIR=`pwd` -cd $srcdir +cd "$srcdir" autoreconf -v --install || exit 1 -cd $ORIGDIR || exit $? +cd "$ORIGDIR" || exit $? + +git config --local --get format.subjectPrefix >/dev/null 2>&1 || + git config --local format.subjectPrefix "PATCH xf86-video-amdgpu" if test -z "$NOCONFIGURE"; then - $srcdir/configure "$@" + exec "$srcdir"/configure "$@" fi diff -Nru xserver-xorg-video-amdgpu-1.2.0/ChangeLog xserver-xorg-video-amdgpu-1.3.0/ChangeLog --- xserver-xorg-video-amdgpu-1.2.0/ChangeLog 2017-03-31 19:05:30.000000000 +0000 +++ xserver-xorg-video-amdgpu-1.3.0/ChangeLog 2017-03-31 19:05:30.000000000 +0000 @@ -1,3 +1,612 @@ +commit 804e30e14e51f94403a0721ef2aae28f1fa9e9f2 +Author: Michel Dänzer +Date: Thu Mar 16 17:28:11 2017 +0900 + + Bump version for 1.3.0 release + +commit 3a8582944ed3fef1b75f8871489e6e19963e2ea6 +Author: Michel Dänzer +Date: Thu Mar 9 15:56:59 2017 +0900 + + Pass TRUE to drmmode_set_desired_modes the first time for GPU screens + + This is the only place we call drmmode_set_desired_modes for GPU screens + during server startup. Without this change, the display outputs of + secondary GPUs may stay on even while Xorg isn't using them. + + (Ported from radeon commit 9a71445094b728f3d78db8f6808b4782ee19a453) + Reviewed-by: Alex Deucher + +commit 82b15a4da156e18da4c8fc0093500c32b549e487 +Author: Michel Dänzer +Date: Thu Mar 9 15:47:24 2017 +0900 + + Skip some initialization steps for GPU screens + + Xorg doesn't use the following functionality of GPU screens, so don't + bother initializing it: + + * DRI page flipping + * DRI3 / Present / SYNC fences + * XVideo / XvMC + * Root window with background None + + (Ported from radeon commit 67ae5e00a748ad52cf92738d401afff2947b1891) + Reviewed-by: Alex Deucher + +commit fa85331f0ce27e16a9338516518433955133840e +Author: Michel Dänzer +Date: Tue Mar 7 18:02:29 2017 +0900 + + glamor: Use glamor_finish when available + + Reviewed-by: Alex Deucher + +commit 7884e38e94c2cbd6c205f556f2b31ad59b4089b4 +Author: Hans De Goede +Date: Tue Oct 18 16:48:40 2016 +0200 + + amdgpu_probe: Do not close server managed drm fds + + This fixes the xserver only seeing AMD/ATI devices supported by the amdgpu + driver, as by the time xf86-video-ati gets a chance to probe them, the + fd has been closed. + + This fixes e.g. Xorg not seeing the dGPU on a Lenovo Thinkpad E465 laptop + with a CARRIZO iGPU and a HAINAN dGPU. + + Signed-off-by: Hans de Goede + + v2: Rebased on top of new patch 1. + + Reviewed-by: Alex Deucher + +commit a2c360fa1d33d6a5aa64c396197e119ff77d1379 +Author: Michel Dänzer +Date: Mon Mar 6 18:59:23 2017 +0900 + + Refactor amdgpu_kernel_close_fd helper + + Preparation for the following change. + + Assign pAMDGPUEnt->fd = -1 instead of 0 when we're not using the file + descriptor anymore. + + Reviewed-by: Hans de Goede + Reviewed-by: Alex Deucher + +commit 947017194d07e32876a43ee0efc45fdc71385748 +Author: Michel Dänzer +Date: Fri Mar 3 17:59:19 2017 +0900 + + glamor: Don't flush in BlockHandler with Xorg >= 1.19 + + This was only necessary with older versions for driving the FBO cache + expiry mechanism. + + Reviewed-by: Alex Deucher + +commit 86907a5e4ce33154167b330570491f88218725d3 +Author: Michel Dänzer +Date: Mon Mar 6 18:23:41 2017 +0900 + + Only define transform_region for XF86_CRTC_VERSION >= 4 + + Not used with older versions of Xorg. Fixes warning in that case: + + ../../src/amdgpu_kms.c:328:1: warning: ‘transform_region’ defined but not used [-Wunused-function] + transform_region(RegionPtr region, struct pict_f_transform *transform, + ^~~~~~~~~~~~~~~~ + + Reviewed-by: Alex Deucher + +commit 8d2b7d1758e3fcac520a18a0684c073f0ac62389 +Author: Michel Dänzer +Date: Mon Mar 6 18:09:58 2017 +0900 + + Use local implementation of RegionDuplicate for older xserver + + It was only added in xserver 1.15. Fixes build against older xserver. + + Reported-by: Pali Rohár + (Ported from radeon commit 80cc892ee1ce54fad3cb7dd11bd9df18c359136f) + Reviewed-by: Alex Deucher + +commit cd73100114a18642d9c40f1df33cef8311e96a8b +Author: Michel Dänzer +Date: Mon Mar 6 18:07:19 2017 +0900 + + Don't use pScrn->is_gpu in AMDGPUCreateScreenResources_KMS + + Looks like this snuck in accidentally. + + Brings us back in line with the radeon driver, and fixes the build + against older versions of xserver which didn't have the is_gpu field + yet. + + Fixes: 6bab8fabb37e ("Remove info->dri2.drm_fd and info->drmmode->fd") + Reviewed-by: Alex Deucher + +commit 351baa89b9b0ecfb6c666af3a2d10c559a9224a9 +Author: Michel Dänzer +Date: Fri Mar 3 16:44:15 2017 +0900 + + Don't call amdgpu_glamor_flush in drmmode_copy_fb + + AMDGPUWindowExposures_oneshot takes care of it. + + (Ported from radeon commit d63881623f0686a66a2e3e3c1f84e496aa52ec6b) + Reviewed-by: Alex Deucher + +commit ad53635af150cda9b8da413be5a011d74f972ac7 +Author: Michel Dänzer +Date: Fri Mar 3 16:41:49 2017 +0900 + + Move DPMS check from amdgpu_scanout_do_update to amdgpu_scanout_flip + + When amdgpu_scanout_do_update is called from + drmmode_crtc_scanout_update, drmmode_crtc->pending_dpms_mode may still + be != DPMSModeOn, e.g. during server startup. + + Fixes intermittently showing garbage with TearFree enabled. + + (Ported from radeon commit cc9d6b7db9c2078be1e530a64af6d517c6a42024) + Reviewed-by: Alex Deucher + +commit 378bd05c849ad3092f138bdc8917d35d0b967389 +Author: Michel Dänzer +Date: Fri Mar 3 16:36:24 2017 +0900 + + Call drmmode_set_desired_modes from a WindowExposures hook + + This is the earliest opportunity where the root window contents are + guaranteed to be initialized, and prevents drmmode_set_mode_major from + getting called before drmmode_set_desired_modes via AMDGPUUnblank -> + drmmode_crtc_dpms. Also, in contrast to the BlockHandler hook, this is + called when running Xorg with -pogo. + + Fixes intermittently showing garbage on server startup or after server + reset. + + As a bonus, this avoids trouble due to higher layers (e.g. the tigervnc + Xorg module) calling AMDGPUBlockHandler_oneshot repeatedly even after + we set pScreen->BlockHandler = AMDGPUBlockHandler_KMS. + + Bugzilla: https://bugs.freedesktop.org/99457 + (Ported from radeon commits 0a12bf1085505017068dfdfd31d23133e51b45b9 and + f0e7948e1c0e984fc27f235f365639e9cf628291) + Reviewed-by: Alex Deucher + +commit 8d4d73e05ce34eb353daec7b2c0e7c844113c7de +Author: Michel Dänzer +Date: Fri Mar 3 16:34:16 2017 +0900 + + present: Flush before flipping + + This isn't necessary for DRI clients, but the Present extension can also + be used for presenting normal pixmaps rendered to via the X11 protocol. + + (Ported from radeon commit 9035b6abea557828e672ee455f0c84e43da0906f) + Reviewed-by: Alex Deucher + +commit 88725b68cad92418c9bb03cb7f20526ce238d64e +Author: Michel Dänzer +Date: Fri Mar 3 16:30:27 2017 +0900 + + present: Use async flip for unflip if possible + + In that case, unflip operations should finish faster in general. + + (Ported from radeon commit 0a4eb0e12f0c9c653cf4cea6fd62e1a507eb261c) + Reviewed-by: Alex Deucher + +commit b31489c086b4bc50c824e85fa26d97c0f43afb20 +Author: Michel Dänzer +Date: Fri Mar 3 16:28:41 2017 +0900 + + present: Also flush before using a flip to unflip + + Not doing so might result in intermittently scanning out stale contents + of the screen pixmap. + + (Ported from radeon commit 9a951a3e551db58ba50e7a594521ceac54d90615) + Reviewed-by: Alex Deucher + +commit f6a3c87c3097e8d5c1d2159bc90d6541a46ed8be +Author: Michel Dänzer +Date: Fri Mar 3 16:26:26 2017 +0900 + + present: Wait for GPU idle before setting modes for unflip + + To make sure the screen pixmap contents are up to date when it starts + being scanned out. + + (Ported from radeon commit 244d4bc7f8c8f6bc90f49556c0b9344c8aa40295) + Reviewed-by: Alex Deucher + +commit 012ffffb45119059f3610fb8fd6ae103186b3e3c +Author: Michel Dänzer +Date: Fri Mar 3 16:22:39 2017 +0900 + + present: Only call drmModeRmFB after setting modes for unflip + + Fixes display intermittently blanking when a modeset is used for unflip. + + (Ported from radeon commit 3ff29e5a14451916bc66b4e0028e9a317f0723f8) + Reviewed-by: Alex Deucher + +commit f4719bb473df897012f8830f46e99cb781d67b6f +Author: Michel Dänzer +Date: Fri Mar 3 16:19:11 2017 +0900 + + Use drmmode_crtc_scanout_free in drmmode_fini + + We were leaking drmmode_crtc->scanout_damage, which caused trouble on + server reset. Fixes server reset with active separate scanout pixmaps. + + (Cherry picked from radeon commit 0c29deb5a97d9a57e994cc0053c49ddf7aca6ecb) + Reviewed-by: Alex Deucher + +commit af0b24c1aca4cba2692d5aa410e63cb536478dbe +Author: Michel Dänzer +Date: Thu Mar 2 17:24:03 2017 +0900 + + Allow toggling TearFree at runtime via output property + + Option "TearFree" now sets the default value of the output property. + See the manpage update for details. + + TearFree is now enabled by default for outputs using rotation or other + RandR transforms, and for RandR 1.4 slave outputs. + + (Ported from radeon commit 58cd1600057e41aade0106d4acf78e23eac6e44f) + Reviewed-by: Alex Deucher + +commit 77853f02e5b879e7042f55c672cf2d8e6955309f +Author: Michel Dänzer +Date: Thu Mar 2 17:19:59 2017 +0900 + + Factor out drmmode_crtc_scanout_update helper + + Cleanup in preparation for following change, no functional change + intended. + + (Ported from radeon commit 305e2cbf335837a2ab6a24e9ff65815afe038296) + Reviewed-by: Alex Deucher + +commit d25cc3b2b3b2d257aea247b85fea405d7e84e5b1 +Author: Michel Dänzer +Date: Thu Mar 2 17:15:03 2017 +0900 + + Factor out amdgpu_prime_dirty_to_crtc helper + + Cleanup in preparation for the following change, no functional change + intended. + + (Ported from radeon commit 649644a88347a6d03de68f8c41db03a82deeb23b) + Reviewed-by: Alex Deucher + +commit a6d363008e2b55f0aa6151be1a99f01b97870e91 +Author: Michel Dänzer +Date: Thu Mar 2 17:13:06 2017 +0900 + + Don't destroy current FB if drmModeAddFB fails + + It would probably result in a black screen. + + (Ported from radeon commit 1351e48efe7a2c28eab447e16f36a00fbd02ae48) + Reviewed-by: Alex Deucher + +commit 53926db2355de0a324c205703a0377b498136f65 +Author: Michel Dänzer +Date: Thu Mar 2 17:08:19 2017 +0900 + + Fix flip event data leak if calloc or drmModeAddFB fails + + (Ported from radeon commit 481394e3c9f9f7d88bb66fe9ae8834c87952a8ab) + Reviewed-by: Alex Deucher + +commit 45a8ec6257c370eecf43b6b8010863e37b704872 +Author: Mihail Konev +Date: Thu Mar 2 17:04:36 2017 +0900 + + autogen: add default patch prefix + + (Ported from radeon commit 8e6a4e96b7b27559e186f71b5547abb0a80b96dd) + Reviewed-by: Alex Deucher + +commit ba2aa0a8c12a2bea1e8be01ca3134b518d4cb0f2 +Author: Michel Dänzer +Date: Thu Mar 2 16:55:38 2017 +0900 + + Handle rotation in the driver also with Xorg 1.12-1.18 + + We cannot use the HW cursor in that case, but in turn we get more + efficient and less teary updates of rotated outputs. + + (Ported from radeon commit f2bc882f1c1082bed9f496cfab6c8f07a76bc122) + Reviewed-by: Alex Deucher + +commit 7f3abf35a2e1225ffd6a777b23f6a7a6355c1691 +Author: Michel Dänzer +Date: Thu Mar 2 16:47:06 2017 +0900 + + Fold drmmode_crtc_scanout_allocate into drmmode_crtc_scanout_create + + Not used anywhere else anymore. + + (Ported from radeon commit ae921a3150f69c38b5b3c88a9e37d54fdf0d5093) + Reviewed-by: Alex Deucher + +commit 03c2db3c67bf5ad3c0744add9e0bb611b6cd3df7 +Author: Michel Dänzer +Date: Thu Mar 2 16:42:04 2017 +0900 + + Call drmmode_crtc_scanout_create in drmmode_crtc_shadow_allocate as well + + Calling drmmode_crtc_scanout_allocate in drmmode_crtc_shadow_allocate + resulted in drmmode_crtc_scanout_create called from + drmmode_crtc_shadow_create passing an uninitialized pitch value to + drmmode_create_bo_pixmap. + + Fixes issues such as failure to allocate the scanout pixmap or visual + corruption and GPUVM faults when attempting to use rotation with Xorg + <1.19. + + Bugzilla: https://bugs.freedesktop.org/99916 + Fixes: 5f7123808833 ("Pass pitch from drmmode_crtc_scanout_allocate to + drmmode_create_bo_pixmap") + (Ported from radeon commit 987a34adb319923ad36e2b47a26837248f187c3e) + Reviewed-by: Alex Deucher + +commit 49b092563cb3958911d28a006f155b4f4e38ed73 +Author: Emil Velikov +Date: Thu Jan 26 11:10:12 2017 +0900 + + autogen.sh: use quoted string variables + + Place quotes around the $srcdir, $ORIGDIR and $0 variables to prevent + fall-outs, when they contain space. + + Signed-off-by: Emil Velikov + Reviewed-by: Peter Hutterer + Signed-off-by: Peter Hutterer + +commit 457fcc5935c659aab5b88cf26d065180b47ed632 +Author: Peter Hutterer +Date: Thu Jan 26 11:09:07 2017 +0900 + + autogen.sh: use exec instead of waiting for configure to finish + + Syncs the invocation of configure with the one from the server. + + Signed-off-by: Peter Hutterer + Reviewed-by: Emil Velikov + +commit 5f712380883357d03c9934a753ef302e109aeb14 +Author: Michel Dänzer +Date: Fri Jan 6 17:42:25 2017 +0900 + + Pass pitch from drmmode_crtc_scanout_allocate to drmmode_create_bo_pixmap + + Mostly to align with radeon commit + ea30d856ba5e7274c8ea499293b8b0e721b8e082, but also gets rid of a + gbm_bo_get_stride call. + + Reviewed-by: Alex Deucher + +commit b5c189473dba2cffc9e4df310ce5c86ceca99a94 +Author: Jammy Zhou +Date: Tue Dec 13 12:32:39 2016 +0900 + + Use render node for DRI3 if available + + Signed-off-by: Jammy Zhou + Reviewed-by: Michel Dänzer + [ Second attempt, let's see if there's any fallout this time... ] + +commit edd276185d42962a13faf9ec9eeebc754ef284e7 +Author: Michel Dänzer +Date: Thu Dec 15 12:42:44 2016 +0900 + + Simplify drmmode_handle_uevents + + No functional change intended. + + Reviewed-by: Jim Qu + +commit 732cf4d3a248b288532ad0f3443da49e08dc7507 +Author: jimqu +Date: Tue Dec 13 16:33:26 2016 +0800 + + udev_monitor_receive_device() will block when hotplug monitor + + udev_monitor_receive_device() will block and wait for the event of udev + use select() to ensure that this will not block. + + Signed-off-by: JimQu + Reviewed-by: Michel Dänzer + +commit d60ea478cf2215ded7e1acf5817a0dae07e54026 +Author: Michel Dänzer +Date: Wed Nov 30 16:28:27 2016 +0900 + + Call amdgpu_drm_abort_entry on failure to flip to a scanout pixmap + + Fixes leaking the corresponding struct amdgpu_drm_queue list entry in + that case. + + (Ported from radeon commit e2942449171fe628a7726e59bcaab65e27d88563) + Reviewed-by: Alex Deucher + +commit aea70298ef0d53fc81aa1fd22c8566920a856223 +Author: Michel Dänzer +Date: Wed Nov 30 16:27:10 2016 +0900 + + Call ValidateGC after ChangeClip in amdgpu_sync_scanout_pixmaps + + The wrong order meant that the clipping region wasn't actually applied, + so it always copied the full contents from the other scanout pixmap. + + (Ported from radeon commit 14c3f59f5157885ad8f941f0bad6c0c5e3db12f8) + Reviewed-by: Alex Deucher + +commit 0f79c30619168c6845b143c6ed94ade307383068 +Author: Michel Dänzer +Date: Wed Nov 30 16:25:52 2016 +0900 + + Fix amdgpu_scanout_extents_intersect for GPU screens + + Fixes incorrect screen updates with TearFree enabled on PRIME slave + outputs which are not located at (0, 0). + + (Ported from radeon commit a995f5830916a0fee5126263d1bfe48632be3a15) + Reviewed-by: Alex Deucher + +commit 082b6b8ca1878f4b7ab0b25d16b85ba40748ac57 +Author: Michel Dänzer +Date: Wed Nov 30 16:21:28 2016 +0900 + + Take current scanout_id into account everywhere involved with TearFree + + Fixes various potential issues with TearFree enabled, e.g. outputs + freezing after display configuration changes. + + (Ported from radeon commit e543ef3a2fb304cbe3a965fb780632af2e4186f4) + Reviewed-by: Alex Deucher + +commit 82729b1f3b9d57f3002ac2689bfbf37ece0bc3f2 +Author: Michel Dänzer +Date: Mon Nov 28 17:47:17 2016 +0900 + + Add amdgpu_is_gpu_screen helper + + This will hopefully decrease the chance of accidentally breaking the + build against xserver < 1.13 in the future. + + (Ported from radeon commit f130b10e63f7526360b41aa0918b4940f63f662a) + Reviewed-by: Alex Deucher + +commit 7fe2a8ed67ef82916a1eb5b241c5a602a26e10b2 +Author: Michel Dänzer +Date: Tue Nov 22 16:50:59 2016 +0900 + + Don't install Flush/EventCallback for GPU screens + + Their purpose is to flush GPU rendering commands corresponding to damage + events, but there can be no damage events corresponding to GPU screen + rendering operations. + + (Ported from radeon commits 13c6bc5e382765fe567091e1c616c0a26eec04ca and + 487aa62a2a23b86e4ea4714fdfd465c9e513141f) + + v2: Squash in radeon fix for build against xserver < 1.13 + + Reviewed-by: Alex Deucher (v1) + +commit ff31320644b4d17b9b3f0abd612c99769d3d9643 +Author: Michel Dänzer +Date: Fri Nov 25 18:34:40 2016 +0900 + + Make libdrm >= 2.4.72 requirement explicit + + And drop compatibility code for older versions. + + Reviewed-by: Alex Deucher + +commit f9ba1e8fd48cd967a09c4e083b277505d08d3849 +Author: Michel Dänzer +Date: Tue Nov 22 16:30:59 2016 +0900 + + Use DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE/RELATIVE flags when available + + (Ported from radeon commits 1106b2f773ad0611c729b27f4c192a26b43ef1e7 + and 5fea5ef2f07eee4a0f94baab427010b936f1d4b4) + + v2: + * Squash in radeon fix for TearFree regression + * Remove preprocessor guards for compatibility with libdrm < 2.4.72 + (Emil Velikov) + + Reviewed-by: Alex Deucher + +commit e8aa4e7ea59f00d5527654b7181a05aab8c78928 +Author: Michel Dänzer +Date: Wed Oct 26 18:38:20 2016 +0900 + + Remove generated header files + + No longer used. + + Reviewed-by: Alex Deucher + +commit d69fd22b6d13052d667929a0e3db61829ce1396e +Author: Michel Dänzer +Date: Wed Oct 26 18:36:18 2016 +0900 + + Stop using AMDGPU(Unique)Chipsets + + Use libdrm_amdgpu's amdgpu_get_marketing_name for the chipset name, or + "Unknown AMD Radeon GPU" as a fallback. + + v2: Require libdrm_amdgpu >= 2.4.72 for amdgpu_get_marketing_name + + Reviewed-by: Alex Deucher (v1) + +commit 8a5ff54af32a75ae56d3369a828a50ae28dd1acd +Author: Michel Dänzer +Date: Wed Oct 26 18:09:18 2016 +0900 + + Stop using AMDGPUPciChipsets + + Not actually used by Xorg. + + Reviewed-by: Alex Deucher + +commit 298eaf58a57efa6acc53d374eea239b6bb55c0f8 +Author: Michel Dänzer +Date: Wed Oct 26 18:05:58 2016 +0900 + + Remove amdpciids.h + + Not useful anymore. + + Reviewed-by: Alex Deucher + +commit a0881d55fe80d639d31cdfeadd6014322c037791 +Author: Michel Dänzer +Date: Wed Oct 26 18:02:39 2016 +0900 + + Stop using generated amdgpu_device_match + + Just match on PCI device ID 0x1002. + + Reviewed-by: Alex Deucher + +commit 40ddc52b2ae32b17ef7eea1602fdf59b63f06f17 +Author: Michel Dänzer +Date: Wed Oct 26 17:42:36 2016 +0900 + + Use family information from libdrm_amdgpu / kernel + + Reviewed-by: Alex Deucher + +commit 5c9d1c5097e326c69f1be4427c62a0d348e8a4a6 +Author: Michel Dänzer +Date: Wed Oct 26 17:32:56 2016 +0900 + + Move struct amdgpu_gpu_info out of amdgpu_get_tile_config + + Preparation for the following change, no functional change intended. + + Reviewed-by: Alex Deucher + +commit adf7dabdf9c8acd674190e25050b0885a05d0e92 +Author: Michel Dänzer +Date: Mon Nov 21 17:50:22 2016 +0900 + + Post-release version bump + commit a00032050873fc99f3ceaa3293468dad1d94d4b1 Author: Michel Dänzer Date: Thu Nov 17 15:17:10 2016 +0900 diff -Nru xserver-xorg-video-amdgpu-1.2.0/config.guess xserver-xorg-video-amdgpu-1.3.0/config.guess --- xserver-xorg-video-amdgpu-1.2.0/config.guess 2015-11-19 08:24:46.000000000 +0000 +++ xserver-xorg-video-amdgpu-1.3.0/config.guess 2017-03-16 08:33:02.000000000 +0000 @@ -1,8 +1,8 @@ #! /bin/sh # Attempt to guess a canonical system name. -# Copyright 1992-2015 Free Software Foundation, Inc. +# Copyright 1992-2016 Free Software Foundation, Inc. -timestamp='2015-08-20' +timestamp='2016-10-02' # This file is free software; you can redistribute it and/or modify it # under the terms of the GNU General Public License as published by @@ -27,7 +27,7 @@ # Originally written by Per Bothner; maintained since 2000 by Ben Elliston. # # You can get the latest version of this script from: -# http://git.savannah.gnu.org/gitweb/?p=config.git;a=blob_plain;f=config.guess;hb=HEAD +# http://git.savannah.gnu.org/gitweb/?p=config.git;a=blob_plain;f=config.guess # # Please send patches to . @@ -50,7 +50,7 @@ GNU config.guess ($timestamp) Originally written by Per Bothner. -Copyright 1992-2015 Free Software Foundation, Inc. +Copyright 1992-2016 Free Software Foundation, Inc. This is free software; see the source for copying conditions. There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE." @@ -186,9 +186,12 @@ *) machine=${UNAME_MACHINE_ARCH}-unknown ;; esac # The Operating System including object format, if it has switched - # to ELF recently, or will in the future. + # to ELF recently (or will in the future) and ABI. case "${UNAME_MACHINE_ARCH}" in - arm*|earm*|i386|m68k|ns32k|sh3*|sparc|vax) + earm*) + os=netbsdelf + ;; + arm*|i386|m68k|ns32k|sh3*|sparc|vax) eval $set_cc_for_build if echo __ELF__ | $CC_FOR_BUILD -E - 2>/dev/null \ | grep -q __ELF__ @@ -237,6 +240,10 @@ UNAME_MACHINE_ARCH=`arch | sed 's/OpenBSD.//'` echo ${UNAME_MACHINE_ARCH}-unknown-openbsd${UNAME_RELEASE} exit ;; + *:LibertyBSD:*:*) + UNAME_MACHINE_ARCH=`arch | sed 's/^.*BSD\.//'` + echo ${UNAME_MACHINE_ARCH}-unknown-libertybsd${UNAME_RELEASE} + exit ;; *:ekkoBSD:*:*) echo ${UNAME_MACHINE}-unknown-ekkobsd${UNAME_RELEASE} exit ;; @@ -268,42 +275,42 @@ ALPHA_CPU_TYPE=`/usr/sbin/psrinfo -v | sed -n -e 's/^ The alpha \(.*\) processor.*$/\1/p' | head -n 1` case "$ALPHA_CPU_TYPE" in "EV4 (21064)") - UNAME_MACHINE="alpha" ;; + UNAME_MACHINE=alpha ;; "EV4.5 (21064)") - UNAME_MACHINE="alpha" ;; + UNAME_MACHINE=alpha ;; "LCA4 (21066/21068)") - UNAME_MACHINE="alpha" ;; + UNAME_MACHINE=alpha ;; "EV5 (21164)") - UNAME_MACHINE="alphaev5" ;; + UNAME_MACHINE=alphaev5 ;; "EV5.6 (21164A)") - UNAME_MACHINE="alphaev56" ;; + UNAME_MACHINE=alphaev56 ;; "EV5.6 (21164PC)") - UNAME_MACHINE="alphapca56" ;; + UNAME_MACHINE=alphapca56 ;; "EV5.7 (21164PC)") - UNAME_MACHINE="alphapca57" ;; + UNAME_MACHINE=alphapca57 ;; "EV6 (21264)") - UNAME_MACHINE="alphaev6" ;; + UNAME_MACHINE=alphaev6 ;; "EV6.7 (21264A)") - UNAME_MACHINE="alphaev67" ;; + UNAME_MACHINE=alphaev67 ;; "EV6.8CB (21264C)") - UNAME_MACHINE="alphaev68" ;; + UNAME_MACHINE=alphaev68 ;; "EV6.8AL (21264B)") - UNAME_MACHINE="alphaev68" ;; + UNAME_MACHINE=alphaev68 ;; "EV6.8CX (21264D)") - UNAME_MACHINE="alphaev68" ;; + UNAME_MACHINE=alphaev68 ;; "EV6.9A (21264/EV69A)") - UNAME_MACHINE="alphaev69" ;; + UNAME_MACHINE=alphaev69 ;; "EV7 (21364)") - UNAME_MACHINE="alphaev7" ;; + UNAME_MACHINE=alphaev7 ;; "EV7.9 (21364A)") - UNAME_MACHINE="alphaev79" ;; + UNAME_MACHINE=alphaev79 ;; esac # A Pn.n version is a patched version. # A Vn.n version is a released version. # A Tn.n version is a released field test version. # A Xn.n version is an unreleased experimental baselevel. # 1.2 uses "1.2" for uname -r. - echo ${UNAME_MACHINE}-dec-osf`echo ${UNAME_RELEASE} | sed -e 's/^[PVTX]//' | tr 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' 'abcdefghijklmnopqrstuvwxyz'` + echo ${UNAME_MACHINE}-dec-osf`echo ${UNAME_RELEASE} | sed -e 's/^[PVTX]//' | tr ABCDEFGHIJKLMNOPQRSTUVWXYZ abcdefghijklmnopqrstuvwxyz` # Reset EXIT trap before exiting to avoid spurious non-zero exit code. exitcode=$? trap '' 0 @@ -376,16 +383,16 @@ exit ;; i86pc:SunOS:5.*:* | i86xen:SunOS:5.*:*) eval $set_cc_for_build - SUN_ARCH="i386" + SUN_ARCH=i386 # If there is a compiler, see if it is configured for 64-bit objects. # Note that the Sun cc does not turn __LP64__ into 1 like gcc does. # This test works for both compilers. - if [ "$CC_FOR_BUILD" != 'no_compiler_found' ]; then + if [ "$CC_FOR_BUILD" != no_compiler_found ]; then if (echo '#ifdef __amd64'; echo IS_64BIT_ARCH; echo '#endif') | \ - (CCOPTS= $CC_FOR_BUILD -E - 2>/dev/null) | \ + (CCOPTS="" $CC_FOR_BUILD -E - 2>/dev/null) | \ grep IS_64BIT_ARCH >/dev/null then - SUN_ARCH="x86_64" + SUN_ARCH=x86_64 fi fi echo ${SUN_ARCH}-pc-solaris2`echo ${UNAME_RELEASE}|sed -e 's/[^.]*//'` @@ -410,7 +417,7 @@ exit ;; sun*:*:4.2BSD:*) UNAME_RELEASE=`(sed 1q /etc/motd | awk '{print substr($5,1,3)}') 2>/dev/null` - test "x${UNAME_RELEASE}" = "x" && UNAME_RELEASE=3 + test "x${UNAME_RELEASE}" = x && UNAME_RELEASE=3 case "`/bin/arch`" in sun3) echo m68k-sun-sunos${UNAME_RELEASE} @@ -635,13 +642,13 @@ sc_cpu_version=`/usr/bin/getconf SC_CPU_VERSION 2>/dev/null` sc_kernel_bits=`/usr/bin/getconf SC_KERNEL_BITS 2>/dev/null` case "${sc_cpu_version}" in - 523) HP_ARCH="hppa1.0" ;; # CPU_PA_RISC1_0 - 528) HP_ARCH="hppa1.1" ;; # CPU_PA_RISC1_1 + 523) HP_ARCH=hppa1.0 ;; # CPU_PA_RISC1_0 + 528) HP_ARCH=hppa1.1 ;; # CPU_PA_RISC1_1 532) # CPU_PA_RISC2_0 case "${sc_kernel_bits}" in - 32) HP_ARCH="hppa2.0n" ;; - 64) HP_ARCH="hppa2.0w" ;; - '') HP_ARCH="hppa2.0" ;; # HP-UX 10.20 + 32) HP_ARCH=hppa2.0n ;; + 64) HP_ARCH=hppa2.0w ;; + '') HP_ARCH=hppa2.0 ;; # HP-UX 10.20 esac ;; esac fi @@ -680,11 +687,11 @@ exit (0); } EOF - (CCOPTS= $CC_FOR_BUILD -o $dummy $dummy.c 2>/dev/null) && HP_ARCH=`$dummy` + (CCOPTS="" $CC_FOR_BUILD -o $dummy $dummy.c 2>/dev/null) && HP_ARCH=`$dummy` test -z "$HP_ARCH" && HP_ARCH=hppa fi ;; esac - if [ ${HP_ARCH} = "hppa2.0w" ] + if [ ${HP_ARCH} = hppa2.0w ] then eval $set_cc_for_build @@ -697,12 +704,12 @@ # $ CC_FOR_BUILD="cc +DA2.0w" ./config.guess # => hppa64-hp-hpux11.23 - if echo __LP64__ | (CCOPTS= $CC_FOR_BUILD -E - 2>/dev/null) | + if echo __LP64__ | (CCOPTS="" $CC_FOR_BUILD -E - 2>/dev/null) | grep -q __LP64__ then - HP_ARCH="hppa2.0w" + HP_ARCH=hppa2.0w else - HP_ARCH="hppa64" + HP_ARCH=hppa64 fi fi echo ${HP_ARCH}-hp-hpux${HPUX_REV} @@ -807,14 +814,14 @@ echo craynv-cray-unicosmp${UNAME_RELEASE} | sed -e 's/\.[^.]*$/.X/' exit ;; F30[01]:UNIX_System_V:*:* | F700:UNIX_System_V:*:*) - FUJITSU_PROC=`uname -m | tr 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' 'abcdefghijklmnopqrstuvwxyz'` - FUJITSU_SYS=`uname -p | tr 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' 'abcdefghijklmnopqrstuvwxyz' | sed -e 's/\///'` + FUJITSU_PROC=`uname -m | tr ABCDEFGHIJKLMNOPQRSTUVWXYZ abcdefghijklmnopqrstuvwxyz` + FUJITSU_SYS=`uname -p | tr ABCDEFGHIJKLMNOPQRSTUVWXYZ abcdefghijklmnopqrstuvwxyz | sed -e 's/\///'` FUJITSU_REL=`echo ${UNAME_RELEASE} | sed -e 's/ /_/'` echo "${FUJITSU_PROC}-fujitsu-${FUJITSU_SYS}${FUJITSU_REL}" exit ;; 5000:UNIX_System_V:4.*:*) - FUJITSU_SYS=`uname -p | tr 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' 'abcdefghijklmnopqrstuvwxyz' | sed -e 's/\///'` - FUJITSU_REL=`echo ${UNAME_RELEASE} | tr 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' 'abcdefghijklmnopqrstuvwxyz' | sed -e 's/ /_/'` + FUJITSU_SYS=`uname -p | tr ABCDEFGHIJKLMNOPQRSTUVWXYZ abcdefghijklmnopqrstuvwxyz | sed -e 's/\///'` + FUJITSU_REL=`echo ${UNAME_RELEASE} | tr ABCDEFGHIJKLMNOPQRSTUVWXYZ abcdefghijklmnopqrstuvwxyz | sed -e 's/ /_/'` echo "sparc-fujitsu-${FUJITSU_SYS}${FUJITSU_REL}" exit ;; i*86:BSD/386:*:* | i*86:BSD/OS:*:* | *:Ascend\ Embedded/OS:*:*) @@ -896,7 +903,7 @@ exit ;; *:GNU/*:*:*) # other systems with GNU libc and userland - echo ${UNAME_MACHINE}-unknown-`echo ${UNAME_SYSTEM} | sed 's,^[^/]*/,,' | tr '[A-Z]' '[a-z]'``echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'`-${LIBC} + echo ${UNAME_MACHINE}-unknown-`echo ${UNAME_SYSTEM} | sed 's,^[^/]*/,,' | tr "[:upper:]" "[:lower:]"``echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'`-${LIBC} exit ;; i*86:Minix:*:*) echo ${UNAME_MACHINE}-pc-minix @@ -919,7 +926,7 @@ EV68*) UNAME_MACHINE=alphaev68 ;; esac objdump --private-headers /bin/sh | grep -q ld.so.1 - if test "$?" = 0 ; then LIBC="gnulibc1" ; fi + if test "$?" = 0 ; then LIBC=gnulibc1 ; fi echo ${UNAME_MACHINE}-unknown-linux-${LIBC} exit ;; arc:Linux:*:* | arceb:Linux:*:*) @@ -965,6 +972,9 @@ ia64:Linux:*:*) echo ${UNAME_MACHINE}-unknown-linux-${LIBC} exit ;; + k1om:Linux:*:*) + echo ${UNAME_MACHINE}-unknown-linux-${LIBC} + exit ;; m32r*:Linux:*:*) echo ${UNAME_MACHINE}-unknown-linux-${LIBC} exit ;; @@ -990,6 +1000,9 @@ eval `$CC_FOR_BUILD -E $dummy.c 2>/dev/null | grep '^CPU'` test x"${CPU}" != x && { echo "${CPU}-unknown-linux-${LIBC}"; exit; } ;; + mips64el:Linux:*:*) + echo ${UNAME_MACHINE}-unknown-linux-${LIBC} + exit ;; openrisc*:Linux:*:*) echo or1k-unknown-linux-${LIBC} exit ;; @@ -1022,6 +1035,9 @@ ppcle:Linux:*:*) echo powerpcle-unknown-linux-${LIBC} exit ;; + riscv32:Linux:*:* | riscv64:Linux:*:*) + echo ${UNAME_MACHINE}-unknown-linux-${LIBC} + exit ;; s390:Linux:*:* | s390x:Linux:*:*) echo ${UNAME_MACHINE}-ibm-linux-${LIBC} exit ;; @@ -1120,7 +1136,7 @@ # uname -m prints for DJGPP always 'pc', but it prints nothing about # the processor, so we play safe by assuming i586. # Note: whatever this is, it MUST be the same as what config.sub - # prints for the "djgpp" host, or else GDB configury will decide that + # prints for the "djgpp" host, or else GDB configure will decide that # this is a cross-build. echo i586-pc-msdosdjgpp exit ;; @@ -1269,6 +1285,9 @@ SX-8R:SUPER-UX:*:*) echo sx8r-nec-superux${UNAME_RELEASE} exit ;; + SX-ACE:SUPER-UX:*:*) + echo sxace-nec-superux${UNAME_RELEASE} + exit ;; Power*:Rhapsody:*:*) echo powerpc-apple-rhapsody${UNAME_RELEASE} exit ;; @@ -1282,9 +1301,9 @@ UNAME_PROCESSOR=powerpc fi if test `echo "$UNAME_RELEASE" | sed -e 's/\..*//'` -le 10 ; then - if [ "$CC_FOR_BUILD" != 'no_compiler_found' ]; then + if [ "$CC_FOR_BUILD" != no_compiler_found ]; then if (echo '#ifdef __LP64__'; echo IS_64BIT_ARCH; echo '#endif') | \ - (CCOPTS= $CC_FOR_BUILD -E - 2>/dev/null) | \ + (CCOPTS="" $CC_FOR_BUILD -E - 2>/dev/null) | \ grep IS_64BIT_ARCH >/dev/null then case $UNAME_PROCESSOR in @@ -1306,7 +1325,7 @@ exit ;; *:procnto*:*:* | *:QNX:[0123456789]*:*) UNAME_PROCESSOR=`uname -p` - if test "$UNAME_PROCESSOR" = "x86"; then + if test "$UNAME_PROCESSOR" = x86; then UNAME_PROCESSOR=i386 UNAME_MACHINE=pc fi @@ -1337,7 +1356,7 @@ # "uname -m" is not consistent, so use $cputype instead. 386 # is converted to i386 for consistency with other x86 # operating systems. - if test "$cputype" = "386"; then + if test "$cputype" = 386; then UNAME_MACHINE=i386 else UNAME_MACHINE="$cputype" @@ -1379,7 +1398,7 @@ echo i386-pc-xenix exit ;; i*86:skyos:*:*) - echo ${UNAME_MACHINE}-pc-skyos`echo ${UNAME_RELEASE}` | sed -e 's/ .*$//' + echo ${UNAME_MACHINE}-pc-skyos`echo ${UNAME_RELEASE} | sed -e 's/ .*$//'` exit ;; i*86:rdos:*:*) echo ${UNAME_MACHINE}-pc-rdos @@ -1390,23 +1409,25 @@ x86_64:VMkernel:*:*) echo ${UNAME_MACHINE}-unknown-esx exit ;; + amd64:Isilon\ OneFS:*:*) + echo x86_64-unknown-onefs + exit ;; esac cat >&2 < in order to provide the needed -information to handle your system. +If $0 has already been updated, send the following data and any +information you think might be pertinent to config-patches@gnu.org to +provide the necessary information to handle your system. config.guess timestamp = $timestamp diff -Nru xserver-xorg-video-amdgpu-1.2.0/config.h.in xserver-xorg-video-amdgpu-1.3.0/config.h.in --- xserver-xorg-video-amdgpu-1.2.0/config.h.in 2016-11-17 06:16:20.000000000 +0000 +++ xserver-xorg-video-amdgpu-1.3.0/config.h.in 2017-03-16 08:33:01.000000000 +0000 @@ -20,6 +20,9 @@ /* Have glamor_egl_destroy_textured_pixmap API */ #undef HAVE_GLAMOR_EGL_DESTROY_TEXTURED_PIXMAP +/* Have glamor_finish API */ +#undef HAVE_GLAMOR_FINISH + /* Have glamor_glyphs_init API */ #undef HAVE_GLAMOR_GLYPHS_INIT @@ -41,6 +44,9 @@ /* Define to 1 if you have the header file. */ #undef HAVE_PRESENT_H +/* Have RegionDuplicate API */ +#undef HAVE_REGIONDUPLICATE + /* Define to 1 if you have the header file. */ #undef HAVE_STDINT_H diff -Nru xserver-xorg-video-amdgpu-1.2.0/config.sub xserver-xorg-video-amdgpu-1.3.0/config.sub --- xserver-xorg-video-amdgpu-1.2.0/config.sub 2015-11-19 08:24:46.000000000 +0000 +++ xserver-xorg-video-amdgpu-1.3.0/config.sub 2017-03-16 08:33:02.000000000 +0000 @@ -1,8 +1,8 @@ #! /bin/sh # Configuration validation subroutine script. -# Copyright 1992-2015 Free Software Foundation, Inc. +# Copyright 1992-2016 Free Software Foundation, Inc. -timestamp='2015-08-20' +timestamp='2016-11-04' # This file is free software; you can redistribute it and/or modify it # under the terms of the GNU General Public License as published by @@ -33,7 +33,7 @@ # Otherwise, we print the canonical config type on stdout and succeed. # You can get the latest version of this script from: -# http://git.savannah.gnu.org/gitweb/?p=config.git;a=blob_plain;f=config.sub;hb=HEAD +# http://git.savannah.gnu.org/gitweb/?p=config.git;a=blob_plain;f=config.sub # This file is supposed to be the same for all GNU packages # and recognize all the CPU types, system types and aliases @@ -53,8 +53,7 @@ me=`echo "$0" | sed -e 's,.*/,,'` usage="\ -Usage: $0 [OPTION] CPU-MFR-OPSYS - $0 [OPTION] ALIAS +Usage: $0 [OPTION] CPU-MFR-OPSYS or ALIAS Canonicalize a configuration name. @@ -68,7 +67,7 @@ version="\ GNU config.sub ($timestamp) -Copyright 1992-2015 Free Software Foundation, Inc. +Copyright 1992-2016 Free Software Foundation, Inc. This is free software; see the source for copying conditions. There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE." @@ -118,7 +117,7 @@ nto-qnx* | linux-gnu* | linux-android* | linux-dietlibc | linux-newlib* | \ linux-musl* | linux-uclibc* | uclinux-uclibc* | uclinux-gnu* | kfreebsd*-gnu* | \ knetbsd*-gnu* | netbsd*-gnu* | netbsd*-eabi* | \ - kopensolaris*-gnu* | \ + kopensolaris*-gnu* | cloudabi*-eabi* | \ storm-chaos* | os2-emx* | rtmk-nova*) os=-$maybe_os basic_machine=`echo $1 | sed 's/^\(.*\)-\([^-]*-[^-]*\)$/\1/'` @@ -302,6 +301,7 @@ | open8 | or1k | or1knd | or32 \ | pdp10 | pdp11 | pj | pjl \ | powerpc | powerpc64 | powerpc64le | powerpcle \ + | pru \ | pyramid \ | riscv32 | riscv64 \ | rl78 | rx \ @@ -429,6 +429,7 @@ | orion-* \ | pdp10-* | pdp11-* | pj-* | pjl-* | pn-* | power-* \ | powerpc-* | powerpc64-* | powerpc64le-* | powerpcle-* \ + | pru-* \ | pyramid-* \ | riscv32-* | riscv64-* \ | rl78-* | romp-* | rs6000-* | rx-* \ @@ -521,7 +522,7 @@ basic_machine=i386-pc os=-aros ;; - asmjs) + asmjs) basic_machine=asmjs-unknown ;; aux) @@ -644,6 +645,14 @@ basic_machine=m68k-bull os=-sysv3 ;; + e500v[12]) + basic_machine=powerpc-unknown + os=$os"spe" + ;; + e500v[12]-*) + basic_machine=powerpc-`echo $basic_machine | sed 's/^[^-]*-//'` + os=$os"spe" + ;; ebmon29k) basic_machine=a29k-amd os=-ebmon @@ -1023,7 +1032,7 @@ ppc-* | ppcbe-*) basic_machine=powerpc-`echo $basic_machine | sed 's/^[^-]*-//'` ;; - ppcle | powerpclittle | ppc-le | powerpc-little) + ppcle | powerpclittle) basic_machine=powerpcle-unknown ;; ppcle-* | powerpclittle-*) @@ -1033,7 +1042,7 @@ ;; ppc64-*) basic_machine=powerpc64-`echo $basic_machine | sed 's/^[^-]*-//'` ;; - ppc64le | powerpc64little | ppc64-le | powerpc64-little) + ppc64le | powerpc64little) basic_machine=powerpc64le-unknown ;; ppc64le-* | powerpc64little-*) @@ -1383,14 +1392,14 @@ | -nindy* | -vxsim* | -vxworks* | -ebmon* | -hms* | -mvs* \ | -clix* | -riscos* | -uniplus* | -iris* | -rtu* | -xenix* \ | -hiux* | -386bsd* | -knetbsd* | -mirbsd* | -netbsd* \ - | -bitrig* | -openbsd* | -solidbsd* \ + | -bitrig* | -openbsd* | -solidbsd* | -libertybsd* \ | -ekkobsd* | -kfreebsd* | -freebsd* | -riscix* | -lynxos* \ | -bosx* | -nextstep* | -cxux* | -aout* | -elf* | -oabi* \ | -ptx* | -coff* | -ecoff* | -winnt* | -domain* | -vsta* \ | -udi* | -eabi* | -lites* | -ieee* | -go32* | -aux* \ | -chorusos* | -chorusrdb* | -cegcc* \ | -cygwin* | -msys* | -pe* | -psos* | -moss* | -proelf* | -rtems* \ - | -mingw32* | -mingw64* | -linux-gnu* | -linux-android* \ + | -midipix* | -mingw32* | -mingw64* | -linux-gnu* | -linux-android* \ | -linux-newlib* | -linux-musl* | -linux-uclibc* \ | -uxpv* | -beos* | -mpeix* | -udk* | -moxiebox* \ | -interix* | -uwin* | -mks* | -rhapsody* | -darwin* | -opened* \ @@ -1399,7 +1408,8 @@ | -os2* | -vos* | -palmos* | -uclinux* | -nucleus* \ | -morphos* | -superux* | -rtmk* | -rtmk-nova* | -windiss* \ | -powermax* | -dnix* | -nx6 | -nx7 | -sei* | -dragonfly* \ - | -skyos* | -haiku* | -rdos* | -toppers* | -drops* | -es* | -tirtos*) + | -skyos* | -haiku* | -rdos* | -toppers* | -drops* | -es* \ + | -onefs* | -tirtos* | -phoenix* | -fuchsia*) # Remember, each alternative MUST END IN *, to match a version number. ;; -qnx*) @@ -1531,6 +1541,8 @@ ;; -nacl*) ;; + -ios) + ;; -none) ;; *) diff -Nru xserver-xorg-video-amdgpu-1.2.0/configure xserver-xorg-video-amdgpu-1.3.0/configure --- xserver-xorg-video-amdgpu-1.2.0/configure 2016-11-17 06:16:10.000000000 +0000 +++ xserver-xorg-video-amdgpu-1.3.0/configure 2017-03-16 08:33:00.000000000 +0000 @@ -1,6 +1,6 @@ #! /bin/sh # Guess values for system-dependent variables and create Makefiles. -# Generated by GNU Autoconf 2.69 for xf86-video-amdgpu 1.2.0. +# Generated by GNU Autoconf 2.69 for xf86-video-amdgpu 1.3.0. # # Report bugs to . # @@ -591,8 +591,8 @@ # Identity of this package. PACKAGE_NAME='xf86-video-amdgpu' PACKAGE_TARNAME='xf86-video-amdgpu' -PACKAGE_VERSION='1.2.0' -PACKAGE_STRING='xf86-video-amdgpu 1.2.0' +PACKAGE_VERSION='1.3.0' +PACKAGE_STRING='xf86-video-amdgpu 1.3.0' PACKAGE_BUGREPORT='https://bugs.freedesktop.org/enter_bug.cgi?product=xorg' PACKAGE_URL='' @@ -1404,7 +1404,7 @@ # Omit some internal or obsolete options to make the list less imposing. # This message is too long to be a string in the A/UX 3.1 sh. cat <<_ACEOF -\`configure' configures xf86-video-amdgpu 1.2.0 to adapt to many kinds of systems. +\`configure' configures xf86-video-amdgpu 1.3.0 to adapt to many kinds of systems. Usage: $0 [OPTION]... [VAR=VALUE]... @@ -1476,7 +1476,7 @@ if test -n "$ac_init_help"; then case $ac_init_help in - short | recursive ) echo "Configuration of xf86-video-amdgpu 1.2.0:";; + short | recursive ) echo "Configuration of xf86-video-amdgpu 1.3.0:";; esac cat <<\_ACEOF @@ -1635,7 +1635,7 @@ test -n "$ac_init_help" && exit $ac_status if $ac_init_version; then cat <<\_ACEOF -xf86-video-amdgpu configure 1.2.0 +xf86-video-amdgpu configure 1.3.0 generated by GNU Autoconf 2.69 Copyright (C) 2012 Free Software Foundation, Inc. @@ -2050,7 +2050,7 @@ This file contains any messages produced by compilers while running configure, to aid debugging if configure makes a mistake. -It was created by xf86-video-amdgpu $as_me 1.2.0, which was +It was created by xf86-video-amdgpu $as_me 1.3.0, which was generated by GNU Autoconf 2.69. Invocation command line was $ $0 $@ @@ -2920,7 +2920,7 @@ # Define the identity of the package. PACKAGE='xf86-video-amdgpu' - VERSION='1.2.0' + VERSION='1.3.0' cat >>confdefs.h <<_ACEOF @@ -18896,12 +18896,12 @@ pkg_cv_LIBDRM_CFLAGS="$LIBDRM_CFLAGS" elif test -n "$PKG_CONFIG"; then if test -n "$PKG_CONFIG" && \ - { { $as_echo "$as_me:${as_lineno-$LINENO}: \$PKG_CONFIG --exists --print-errors \"libdrm >= 2.4.58\""; } >&5 - ($PKG_CONFIG --exists --print-errors "libdrm >= 2.4.58") 2>&5 + { { $as_echo "$as_me:${as_lineno-$LINENO}: \$PKG_CONFIG --exists --print-errors \"libdrm >= 2.4.72\""; } >&5 + ($PKG_CONFIG --exists --print-errors "libdrm >= 2.4.72") 2>&5 ac_status=$? $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 test $ac_status = 0; }; then - pkg_cv_LIBDRM_CFLAGS=`$PKG_CONFIG --cflags "libdrm >= 2.4.58" 2>/dev/null` + pkg_cv_LIBDRM_CFLAGS=`$PKG_CONFIG --cflags "libdrm >= 2.4.72" 2>/dev/null` test "x$?" != "x0" && pkg_failed=yes else pkg_failed=yes @@ -18913,12 +18913,12 @@ pkg_cv_LIBDRM_LIBS="$LIBDRM_LIBS" elif test -n "$PKG_CONFIG"; then if test -n "$PKG_CONFIG" && \ - { { $as_echo "$as_me:${as_lineno-$LINENO}: \$PKG_CONFIG --exists --print-errors \"libdrm >= 2.4.58\""; } >&5 - ($PKG_CONFIG --exists --print-errors "libdrm >= 2.4.58") 2>&5 + { { $as_echo "$as_me:${as_lineno-$LINENO}: \$PKG_CONFIG --exists --print-errors \"libdrm >= 2.4.72\""; } >&5 + ($PKG_CONFIG --exists --print-errors "libdrm >= 2.4.72") 2>&5 ac_status=$? $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 test $ac_status = 0; }; then - pkg_cv_LIBDRM_LIBS=`$PKG_CONFIG --libs "libdrm >= 2.4.58" 2>/dev/null` + pkg_cv_LIBDRM_LIBS=`$PKG_CONFIG --libs "libdrm >= 2.4.72" 2>/dev/null` test "x$?" != "x0" && pkg_failed=yes else pkg_failed=yes @@ -18939,14 +18939,14 @@ _pkg_short_errors_supported=no fi if test $_pkg_short_errors_supported = yes; then - LIBDRM_PKG_ERRORS=`$PKG_CONFIG --short-errors --print-errors --cflags --libs "libdrm >= 2.4.58" 2>&1` + LIBDRM_PKG_ERRORS=`$PKG_CONFIG --short-errors --print-errors --cflags --libs "libdrm >= 2.4.72" 2>&1` else - LIBDRM_PKG_ERRORS=`$PKG_CONFIG --print-errors --cflags --libs "libdrm >= 2.4.58" 2>&1` + LIBDRM_PKG_ERRORS=`$PKG_CONFIG --print-errors --cflags --libs "libdrm >= 2.4.72" 2>&1` fi # Put the nasty error message in config.log where it belongs echo "$LIBDRM_PKG_ERRORS" >&5 - as_fn_error $? "Package requirements (libdrm >= 2.4.58) were not met: + as_fn_error $? "Package requirements (libdrm >= 2.4.72) were not met: $LIBDRM_PKG_ERRORS @@ -18987,12 +18987,12 @@ pkg_cv_LIBDRM_AMDGPU_CFLAGS="$LIBDRM_AMDGPU_CFLAGS" elif test -n "$PKG_CONFIG"; then if test -n "$PKG_CONFIG" && \ - { { $as_echo "$as_me:${as_lineno-$LINENO}: \$PKG_CONFIG --exists --print-errors \"libdrm_amdgpu\""; } >&5 - ($PKG_CONFIG --exists --print-errors "libdrm_amdgpu") 2>&5 + { { $as_echo "$as_me:${as_lineno-$LINENO}: \$PKG_CONFIG --exists --print-errors \"libdrm_amdgpu >= 2.4.72\""; } >&5 + ($PKG_CONFIG --exists --print-errors "libdrm_amdgpu >= 2.4.72") 2>&5 ac_status=$? $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 test $ac_status = 0; }; then - pkg_cv_LIBDRM_AMDGPU_CFLAGS=`$PKG_CONFIG --cflags "libdrm_amdgpu" 2>/dev/null` + pkg_cv_LIBDRM_AMDGPU_CFLAGS=`$PKG_CONFIG --cflags "libdrm_amdgpu >= 2.4.72" 2>/dev/null` test "x$?" != "x0" && pkg_failed=yes else pkg_failed=yes @@ -19004,12 +19004,12 @@ pkg_cv_LIBDRM_AMDGPU_LIBS="$LIBDRM_AMDGPU_LIBS" elif test -n "$PKG_CONFIG"; then if test -n "$PKG_CONFIG" && \ - { { $as_echo "$as_me:${as_lineno-$LINENO}: \$PKG_CONFIG --exists --print-errors \"libdrm_amdgpu\""; } >&5 - ($PKG_CONFIG --exists --print-errors "libdrm_amdgpu") 2>&5 + { { $as_echo "$as_me:${as_lineno-$LINENO}: \$PKG_CONFIG --exists --print-errors \"libdrm_amdgpu >= 2.4.72\""; } >&5 + ($PKG_CONFIG --exists --print-errors "libdrm_amdgpu >= 2.4.72") 2>&5 ac_status=$? $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 test $ac_status = 0; }; then - pkg_cv_LIBDRM_AMDGPU_LIBS=`$PKG_CONFIG --libs "libdrm_amdgpu" 2>/dev/null` + pkg_cv_LIBDRM_AMDGPU_LIBS=`$PKG_CONFIG --libs "libdrm_amdgpu >= 2.4.72" 2>/dev/null` test "x$?" != "x0" && pkg_failed=yes else pkg_failed=yes @@ -19030,14 +19030,14 @@ _pkg_short_errors_supported=no fi if test $_pkg_short_errors_supported = yes; then - LIBDRM_AMDGPU_PKG_ERRORS=`$PKG_CONFIG --short-errors --print-errors --cflags --libs "libdrm_amdgpu" 2>&1` + LIBDRM_AMDGPU_PKG_ERRORS=`$PKG_CONFIG --short-errors --print-errors --cflags --libs "libdrm_amdgpu >= 2.4.72" 2>&1` else - LIBDRM_AMDGPU_PKG_ERRORS=`$PKG_CONFIG --print-errors --cflags --libs "libdrm_amdgpu" 2>&1` + LIBDRM_AMDGPU_PKG_ERRORS=`$PKG_CONFIG --print-errors --cflags --libs "libdrm_amdgpu >= 2.4.72" 2>&1` fi # Put the nasty error message in config.log where it belongs echo "$LIBDRM_AMDGPU_PKG_ERRORS" >&5 - as_fn_error $? "Package requirements (libdrm_amdgpu) were not met: + as_fn_error $? "Package requirements (libdrm_amdgpu >= 2.4.72) were not met: $LIBDRM_AMDGPU_PKG_ERRORS @@ -19522,8 +19522,15 @@ fi - fi + ac_fn_c_check_decl "$LINENO" "glamor_finish" "ac_cv_have_decl_glamor_finish" "#include \"xorg-server.h\" + #include \"glamor.h\" +" +if test "x$ac_cv_have_decl_glamor_finish" = xyes; then : + +$as_echo "#define HAVE_GLAMOR_FINISH 1" >>confdefs.h + +else pkg_failed=no { $as_echo "$as_me:${as_lineno-$LINENO}: checking for LIBGL" >&5 @@ -19615,6 +19622,9 @@ $as_echo "yes" >&6; } fi +fi + + fi if test "x$GLAMOR_XSERVER" != xyes; then @@ -19816,6 +19826,16 @@ fi +ac_fn_c_check_decl "$LINENO" "RegionDuplicate" "ac_cv_have_decl_RegionDuplicate" "#include + #include +" +if test "x$ac_cv_have_decl_RegionDuplicate" = xyes; then : + +$as_echo "#define HAVE_REGIONDUPLICATE 1" >>confdefs.h + +fi + + ac_fn_c_check_decl "$LINENO" "fbGlyphs" "ac_cv_have_decl_fbGlyphs" "#include #include #include @@ -20592,7 +20612,7 @@ # report actual input values of CONFIG_FILES etc. instead of their # values after options handling. ac_log=" -This file was extended by xf86-video-amdgpu $as_me 1.2.0, which was +This file was extended by xf86-video-amdgpu $as_me 1.3.0, which was generated by GNU Autoconf 2.69. Invocation command line was CONFIG_FILES = $CONFIG_FILES @@ -20658,7 +20678,7 @@ cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 ac_cs_config="`$as_echo "$ac_configure_args" | sed 's/^ //; s/[\\""\`\$]/\\\\&/g'`" ac_cs_version="\\ -xf86-video-amdgpu config.status 1.2.0 +xf86-video-amdgpu config.status 1.3.0 configured by $0, generated by GNU Autoconf 2.69, with options \\"\$ac_cs_config\\" diff -Nru xserver-xorg-video-amdgpu-1.2.0/configure.ac xserver-xorg-video-amdgpu-1.3.0/configure.ac --- xserver-xorg-video-amdgpu-1.2.0/configure.ac 2016-11-17 06:15:50.000000000 +0000 +++ xserver-xorg-video-amdgpu-1.3.0/configure.ac 2017-03-16 08:32:47.000000000 +0000 @@ -23,7 +23,7 @@ # Initialize Autoconf AC_PREREQ([2.60]) AC_INIT([xf86-video-amdgpu], - [1.2.0], + [1.3.0], [https://bugs.freedesktop.org/enter_bug.cgi?product=xorg], [xf86-video-amdgpu]) @@ -69,8 +69,8 @@ XORG_DRIVER_CHECK_EXT(DPMSExtension, xextproto) # Checks for libraries. -PKG_CHECK_MODULES(LIBDRM, [libdrm >= 2.4.58]) -PKG_CHECK_MODULES(LIBDRM_AMDGPU, [libdrm_amdgpu]) +PKG_CHECK_MODULES(LIBDRM, [libdrm >= 2.4.72]) +PKG_CHECK_MODULES(LIBDRM_AMDGPU, [libdrm_amdgpu >= 2.4.72]) PKG_CHECK_MODULES(GBM, [gbm]) # Obtain compiler/linker options for the driver dependencies @@ -138,9 +138,14 @@ [Have glamor_egl_destroy_textured_pixmap API])], [], [#include "xorg-server.h" #include "glamor.h"]) - fi - PKG_CHECK_MODULES(LIBGL, [gl]) + AC_CHECK_DECL(glamor_finish, + [AC_DEFINE(HAVE_GLAMOR_FINISH, 1, + [Have glamor_finish API])], + [PKG_CHECK_MODULES(LIBGL, [gl])], + [#include "xorg-server.h" + #include "glamor.h"]) + fi if test "x$GLAMOR_XSERVER" != xyes; then PKG_CHECK_MODULES(LIBGLAMOR, [glamor >= 0.6.0]) @@ -152,6 +157,12 @@ fi AM_CONDITIONAL(GLAMOR, test x$GLAMOR != xno) +AC_CHECK_DECL(RegionDuplicate, + [AC_DEFINE(HAVE_REGIONDUPLICATE, 1, + [Have RegionDuplicate API])], [], + [#include + #include ]) + AC_CHECK_DECL(fbGlyphs, [AC_DEFINE(HAVE_FBGLYPHS, 1, [Have fbGlyphs API])], [], [#include diff -Nru xserver-xorg-video-amdgpu-1.2.0/debian/changelog xserver-xorg-video-amdgpu-1.3.0/debian/changelog --- xserver-xorg-video-amdgpu-1.2.0/debian/changelog 2017-03-31 19:05:30.000000000 +0000 +++ xserver-xorg-video-amdgpu-1.3.0/debian/changelog 2017-03-31 19:05:30.000000000 +0000 @@ -1,8 +1,20 @@ -xserver-xorg-video-amdgpu (1.2.0-1~ubuntu16.04.1) xenial; urgency=medium +xserver-xorg-video-amdgpu (1.3.0-0ubuntu1~ubuntu16.04.1) xenial; urgency=medium * No-change backport to xenial - -- Donk donk Tue, 20 Dec 2016 17:20:01 +0100 + -- Donk donk Fri, 31 Mar 2017 19:50:53 +0200 + +xserver-xorg-video-amdgpu (1.3.0-0ubuntu1) zesty; urgency=medium + + * Sync from Debian git. + + -- Timo Aaltonen Thu, 16 Mar 2017 16:07:02 +0200 + +xserver-xorg-video-amdgpu (1.3.0-1) UNRELEASED; urgency=medium + + * New upstream release. + + -- Timo Aaltonen Thu, 16 Mar 2017 16:06:26 +0200 xserver-xorg-video-amdgpu (1.2.0-1) unstable; urgency=medium diff -Nru xserver-xorg-video-amdgpu-1.2.0/ltmain.sh xserver-xorg-video-amdgpu-1.3.0/ltmain.sh --- xserver-xorg-video-amdgpu-1.2.0/ltmain.sh 2016-02-19 03:10:50.000000000 +0000 +++ xserver-xorg-video-amdgpu-1.3.0/ltmain.sh 2017-03-16 08:32:54.000000000 +0000 @@ -31,7 +31,7 @@ PROGRAM=libtool PACKAGE=libtool -VERSION="2.4.6 Debian-2.4.6-0.1" +VERSION="2.4.6 Debian-2.4.6-2" package_revision=2.4.6 @@ -2068,7 +2068,7 @@ compiler: $LTCC compiler flags: $LTCFLAGS linker: $LD (gnu? $with_gnu_ld) - version: $progname (GNU libtool) 2.4.6 + version: $progname $scriptversion Debian-2.4.6-2 automake: `($AUTOMAKE --version) 2>/dev/null |$SED 1q` autoconf: `($AUTOCONF --version) 2>/dev/null |$SED 1q` diff -Nru xserver-xorg-video-amdgpu-1.2.0/Makefile.in xserver-xorg-video-amdgpu-1.3.0/Makefile.in --- xserver-xorg-video-amdgpu-1.2.0/Makefile.in 2016-11-17 06:16:10.000000000 +0000 +++ xserver-xorg-video-amdgpu-1.3.0/Makefile.in 2017-03-16 08:33:02.000000000 +0000 @@ -179,7 +179,7 @@ DIST_SUBDIRS = $(SUBDIRS) am__DIST_COMMON = $(srcdir)/Makefile.in $(srcdir)/config.h.in COPYING \ ChangeLog INSTALL README compile config.guess config.sub \ - depcomp install-sh ltmain.sh missing + install-sh ltmain.sh missing DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST) distdir = $(PACKAGE)-$(VERSION) top_distdir = $(distdir) diff -Nru xserver-xorg-video-amdgpu-1.2.0/man/amdgpu.man xserver-xorg-video-amdgpu-1.3.0/man/amdgpu.man --- xserver-xorg-video-amdgpu-1.2.0/man/amdgpu.man 2016-11-17 06:12:12.000000000 +0000 +++ xserver-xorg-video-amdgpu-1.3.0/man/amdgpu.man 2017-03-16 08:32:47.000000000 +0000 @@ -73,10 +73,17 @@ .B on. .TP .BI "Option \*qTearFree\*q \*q" boolean \*q -Enable tearing prevention using the hardware page flipping mechanism. Requires allocating two -separate scanout buffers for each CRTC. Enabling this option currently disables Option -\*qEnablePageFlip\*q. The default is -.B off. +Set the default value of the per-output 'TearFree' property, which controls +tearing prevention using the hardware page flipping mechanism. TearFree is +on for any CRTC associated with one or more outputs with TearFree on. Two +separate scanout buffers need to be allocated for each CRTC with TearFree +on. While TearFree is on for any CRTC, it currently prevents clients from using +DRI page flipping. If this option is set, the default value of the property is +'on' or 'off' accordingly. If this option isn't set, the default value of the +property is +.B auto, +which means that TearFree is on for outputs with rotation or other RandR +transforms, and for RandR 1.4 slave outputs, otherwise off. .TP .BI "Option \*qAccelMethod\*q \*q" string \*q Setting this option to diff -Nru xserver-xorg-video-amdgpu-1.2.0/src/amdgpu_chipinfo_gen.h xserver-xorg-video-amdgpu-1.3.0/src/amdgpu_chipinfo_gen.h --- xserver-xorg-video-amdgpu-1.2.0/src/amdgpu_chipinfo_gen.h 2016-09-16 06:47:43.000000000 +0000 +++ xserver-xorg-video-amdgpu-1.3.0/src/amdgpu_chipinfo_gen.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,194 +0,0 @@ -/* This file is autogenerated please do not edit */ -static AMDGPUCardInfo AMDGPUCards[] = { - { 0x6600, CHIP_FAMILY_OLAND }, - { 0x6601, CHIP_FAMILY_OLAND }, - { 0x6602, CHIP_FAMILY_OLAND }, - { 0x6603, CHIP_FAMILY_OLAND }, - { 0x6604, CHIP_FAMILY_OLAND }, - { 0x6605, CHIP_FAMILY_OLAND }, - { 0x6606, CHIP_FAMILY_OLAND }, - { 0x6607, CHIP_FAMILY_OLAND }, - { 0x6608, CHIP_FAMILY_OLAND }, - { 0x6610, CHIP_FAMILY_OLAND }, - { 0x6611, CHIP_FAMILY_OLAND }, - { 0x6613, CHIP_FAMILY_OLAND }, - { 0x6617, CHIP_FAMILY_OLAND }, - { 0x6620, CHIP_FAMILY_OLAND }, - { 0x6621, CHIP_FAMILY_OLAND }, - { 0x6623, CHIP_FAMILY_OLAND }, - { 0x6631, CHIP_FAMILY_OLAND }, - { 0x6660, CHIP_FAMILY_HAINAN }, - { 0x6663, CHIP_FAMILY_HAINAN }, - { 0x6664, CHIP_FAMILY_HAINAN }, - { 0x6665, CHIP_FAMILY_HAINAN }, - { 0x6667, CHIP_FAMILY_HAINAN }, - { 0x666F, CHIP_FAMILY_HAINAN }, - { 0x6780, CHIP_FAMILY_TAHITI }, - { 0x6784, CHIP_FAMILY_TAHITI }, - { 0x6788, CHIP_FAMILY_TAHITI }, - { 0x678A, CHIP_FAMILY_TAHITI }, - { 0x6790, CHIP_FAMILY_TAHITI }, - { 0x6791, CHIP_FAMILY_TAHITI }, - { 0x6792, CHIP_FAMILY_TAHITI }, - { 0x6798, CHIP_FAMILY_TAHITI }, - { 0x6799, CHIP_FAMILY_TAHITI }, - { 0x679A, CHIP_FAMILY_TAHITI }, - { 0x679B, CHIP_FAMILY_TAHITI }, - { 0x679E, CHIP_FAMILY_TAHITI }, - { 0x679F, CHIP_FAMILY_TAHITI }, - { 0x6800, CHIP_FAMILY_PITCAIRN }, - { 0x6801, CHIP_FAMILY_PITCAIRN }, - { 0x6802, CHIP_FAMILY_PITCAIRN }, - { 0x6806, CHIP_FAMILY_PITCAIRN }, - { 0x6808, CHIP_FAMILY_PITCAIRN }, - { 0x6809, CHIP_FAMILY_PITCAIRN }, - { 0x6810, CHIP_FAMILY_PITCAIRN }, - { 0x6811, CHIP_FAMILY_PITCAIRN }, - { 0x6816, CHIP_FAMILY_PITCAIRN }, - { 0x6817, CHIP_FAMILY_PITCAIRN }, - { 0x6818, CHIP_FAMILY_PITCAIRN }, - { 0x6819, CHIP_FAMILY_PITCAIRN }, - { 0x6820, CHIP_FAMILY_VERDE }, - { 0x6821, CHIP_FAMILY_VERDE }, - { 0x6822, CHIP_FAMILY_VERDE }, - { 0x6823, CHIP_FAMILY_VERDE }, - { 0x6824, CHIP_FAMILY_VERDE }, - { 0x6825, CHIP_FAMILY_VERDE }, - { 0x6826, CHIP_FAMILY_VERDE }, - { 0x6827, CHIP_FAMILY_VERDE }, - { 0x6828, CHIP_FAMILY_VERDE }, - { 0x6829, CHIP_FAMILY_VERDE }, - { 0x682A, CHIP_FAMILY_VERDE }, - { 0x682B, CHIP_FAMILY_VERDE }, - { 0x682C, CHIP_FAMILY_VERDE }, - { 0x682D, CHIP_FAMILY_VERDE }, - { 0x682F, CHIP_FAMILY_VERDE }, - { 0x6830, CHIP_FAMILY_VERDE }, - { 0x6831, CHIP_FAMILY_VERDE }, - { 0x6835, CHIP_FAMILY_VERDE }, - { 0x6837, CHIP_FAMILY_VERDE }, - { 0x6838, CHIP_FAMILY_VERDE }, - { 0x6839, CHIP_FAMILY_VERDE }, - { 0x683B, CHIP_FAMILY_VERDE }, - { 0x683D, CHIP_FAMILY_VERDE }, - { 0x683F, CHIP_FAMILY_VERDE }, - { 0x684C, CHIP_FAMILY_PITCAIRN }, - { 0x6640, CHIP_FAMILY_BONAIRE }, - { 0x6641, CHIP_FAMILY_BONAIRE }, - { 0x6646, CHIP_FAMILY_BONAIRE }, - { 0x6647, CHIP_FAMILY_BONAIRE }, - { 0x6649, CHIP_FAMILY_BONAIRE }, - { 0x6650, CHIP_FAMILY_BONAIRE }, - { 0x6651, CHIP_FAMILY_BONAIRE }, - { 0x6658, CHIP_FAMILY_BONAIRE }, - { 0x665C, CHIP_FAMILY_BONAIRE }, - { 0x665D, CHIP_FAMILY_BONAIRE }, - { 0x665F, CHIP_FAMILY_BONAIRE }, - { 0x9830, CHIP_FAMILY_KABINI }, - { 0x9831, CHIP_FAMILY_KABINI }, - { 0x9832, CHIP_FAMILY_KABINI }, - { 0x9833, CHIP_FAMILY_KABINI }, - { 0x9834, CHIP_FAMILY_KABINI }, - { 0x9835, CHIP_FAMILY_KABINI }, - { 0x9836, CHIP_FAMILY_KABINI }, - { 0x9837, CHIP_FAMILY_KABINI }, - { 0x9838, CHIP_FAMILY_KABINI }, - { 0x9839, CHIP_FAMILY_KABINI }, - { 0x983A, CHIP_FAMILY_KABINI }, - { 0x983B, CHIP_FAMILY_KABINI }, - { 0x983C, CHIP_FAMILY_KABINI }, - { 0x983D, CHIP_FAMILY_KABINI }, - { 0x983E, CHIP_FAMILY_KABINI }, - { 0x983F, CHIP_FAMILY_KABINI }, - { 0x9850, CHIP_FAMILY_MULLINS }, - { 0x9851, CHIP_FAMILY_MULLINS }, - { 0x9852, CHIP_FAMILY_MULLINS }, - { 0x9853, CHIP_FAMILY_MULLINS }, - { 0x9854, CHIP_FAMILY_MULLINS }, - { 0x9855, CHIP_FAMILY_MULLINS }, - { 0x9856, CHIP_FAMILY_MULLINS }, - { 0x9857, CHIP_FAMILY_MULLINS }, - { 0x9858, CHIP_FAMILY_MULLINS }, - { 0x9859, CHIP_FAMILY_MULLINS }, - { 0x985A, CHIP_FAMILY_MULLINS }, - { 0x985B, CHIP_FAMILY_MULLINS }, - { 0x985C, CHIP_FAMILY_MULLINS }, - { 0x985D, CHIP_FAMILY_MULLINS }, - { 0x985E, CHIP_FAMILY_MULLINS }, - { 0x985F, CHIP_FAMILY_MULLINS }, - { 0x1304, CHIP_FAMILY_KAVERI }, - { 0x1305, CHIP_FAMILY_KAVERI }, - { 0x1306, CHIP_FAMILY_KAVERI }, - { 0x1307, CHIP_FAMILY_KAVERI }, - { 0x1309, CHIP_FAMILY_KAVERI }, - { 0x130A, CHIP_FAMILY_KAVERI }, - { 0x130B, CHIP_FAMILY_KAVERI }, - { 0x130C, CHIP_FAMILY_KAVERI }, - { 0x130D, CHIP_FAMILY_KAVERI }, - { 0x130E, CHIP_FAMILY_KAVERI }, - { 0x130F, CHIP_FAMILY_KAVERI }, - { 0x1310, CHIP_FAMILY_KAVERI }, - { 0x1311, CHIP_FAMILY_KAVERI }, - { 0x1312, CHIP_FAMILY_KAVERI }, - { 0x1313, CHIP_FAMILY_KAVERI }, - { 0x1315, CHIP_FAMILY_KAVERI }, - { 0x1316, CHIP_FAMILY_KAVERI }, - { 0x1317, CHIP_FAMILY_KAVERI }, - { 0x1318, CHIP_FAMILY_KAVERI }, - { 0x131B, CHIP_FAMILY_KAVERI }, - { 0x131C, CHIP_FAMILY_KAVERI }, - { 0x131D, CHIP_FAMILY_KAVERI }, - { 0x67A0, CHIP_FAMILY_HAWAII }, - { 0x67A1, CHIP_FAMILY_HAWAII }, - { 0x67A2, CHIP_FAMILY_HAWAII }, - { 0x67A8, CHIP_FAMILY_HAWAII }, - { 0x67A9, CHIP_FAMILY_HAWAII }, - { 0x67AA, CHIP_FAMILY_HAWAII }, - { 0x67B0, CHIP_FAMILY_HAWAII }, - { 0x67B1, CHIP_FAMILY_HAWAII }, - { 0x67B8, CHIP_FAMILY_HAWAII }, - { 0x67B9, CHIP_FAMILY_HAWAII }, - { 0x67BA, CHIP_FAMILY_HAWAII }, - { 0x67BE, CHIP_FAMILY_HAWAII }, - { 0x6900, CHIP_FAMILY_TOPAZ }, - { 0x6901, CHIP_FAMILY_TOPAZ }, - { 0x6902, CHIP_FAMILY_TOPAZ }, - { 0x6903, CHIP_FAMILY_TOPAZ }, - { 0x6907, CHIP_FAMILY_TOPAZ }, - { 0x6920, CHIP_FAMILY_TONGA }, - { 0x6921, CHIP_FAMILY_TONGA }, - { 0x6928, CHIP_FAMILY_TONGA }, - { 0x6929, CHIP_FAMILY_TONGA }, - { 0x692B, CHIP_FAMILY_TONGA }, - { 0x692F, CHIP_FAMILY_TONGA }, - { 0x6930, CHIP_FAMILY_TONGA }, - { 0x6938, CHIP_FAMILY_TONGA }, - { 0x6939, CHIP_FAMILY_TONGA }, - { 0x9870, CHIP_FAMILY_CARRIZO }, - { 0x9874, CHIP_FAMILY_CARRIZO }, - { 0x9875, CHIP_FAMILY_CARRIZO }, - { 0x9876, CHIP_FAMILY_CARRIZO }, - { 0x9877, CHIP_FAMILY_CARRIZO }, - { 0x7300, CHIP_FAMILY_FIJI }, - { 0x98E4, CHIP_FAMILY_STONEY }, - { 0x67E0, CHIP_FAMILY_POLARIS11 }, - { 0x67E3, CHIP_FAMILY_POLARIS11 }, - { 0x67E8, CHIP_FAMILY_POLARIS11 }, - { 0x67EB, CHIP_FAMILY_POLARIS11 }, - { 0x67EF, CHIP_FAMILY_POLARIS11 }, - { 0x67FF, CHIP_FAMILY_POLARIS11 }, - { 0x67E1, CHIP_FAMILY_POLARIS11 }, - { 0x67E7, CHIP_FAMILY_POLARIS11 }, - { 0x67E9, CHIP_FAMILY_POLARIS11 }, - { 0x67C0, CHIP_FAMILY_POLARIS10 }, - { 0x67C1, CHIP_FAMILY_POLARIS10 }, - { 0x67C2, CHIP_FAMILY_POLARIS10 }, - { 0x67C4, CHIP_FAMILY_POLARIS10 }, - { 0x67C7, CHIP_FAMILY_POLARIS10 }, - { 0x67DF, CHIP_FAMILY_POLARIS10 }, - { 0x67C8, CHIP_FAMILY_POLARIS10 }, - { 0x67C9, CHIP_FAMILY_POLARIS10 }, - { 0x67CA, CHIP_FAMILY_POLARIS10 }, - { 0x67CC, CHIP_FAMILY_POLARIS10 }, - { 0x67CF, CHIP_FAMILY_POLARIS10 }, -}; diff -Nru xserver-xorg-video-amdgpu-1.2.0/src/amdgpu_chipset_gen.h xserver-xorg-video-amdgpu-1.3.0/src/amdgpu_chipset_gen.h --- xserver-xorg-video-amdgpu-1.2.0/src/amdgpu_chipset_gen.h 2016-11-17 06:07:48.000000000 +0000 +++ xserver-xorg-video-amdgpu-1.3.0/src/amdgpu_chipset_gen.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,216 +0,0 @@ -/* This file is autogenerated please do not edit */ -SymTabRec AMDGPUChipsets[] = { - { PCI_CHIP_OLAND_6600, "OLAND" }, - { PCI_CHIP_OLAND_6601, "OLAND" }, - { PCI_CHIP_OLAND_6602, "OLAND" }, - { PCI_CHIP_OLAND_6603, "OLAND" }, - { PCI_CHIP_OLAND_6604, "OLAND" }, - { PCI_CHIP_OLAND_6605, "OLAND" }, - { PCI_CHIP_OLAND_6606, "OLAND" }, - { PCI_CHIP_OLAND_6607, "OLAND" }, - { PCI_CHIP_OLAND_6608, "OLAND" }, - { PCI_CHIP_OLAND_6610, "OLAND" }, - { PCI_CHIP_OLAND_6611, "OLAND" }, - { PCI_CHIP_OLAND_6613, "OLAND" }, - { PCI_CHIP_OLAND_6617, "OLAND" }, - { PCI_CHIP_OLAND_6620, "OLAND" }, - { PCI_CHIP_OLAND_6621, "OLAND" }, - { PCI_CHIP_OLAND_6623, "OLAND" }, - { PCI_CHIP_OLAND_6631, "OLAND" }, - { PCI_CHIP_HAINAN_6660, "HAINAN" }, - { PCI_CHIP_HAINAN_6663, "HAINAN" }, - { PCI_CHIP_HAINAN_6664, "HAINAN" }, - { PCI_CHIP_HAINAN_6665, "HAINAN" }, - { PCI_CHIP_HAINAN_6667, "HAINAN" }, - { PCI_CHIP_HAINAN_666F, "HAINAN" }, - { PCI_CHIP_TAHITI_6780, "TAHITI" }, - { PCI_CHIP_TAHITI_6784, "TAHITI" }, - { PCI_CHIP_TAHITI_6788, "TAHITI" }, - { PCI_CHIP_TAHITI_678A, "TAHITI" }, - { PCI_CHIP_TAHITI_6790, "TAHITI" }, - { PCI_CHIP_TAHITI_6791, "TAHITI" }, - { PCI_CHIP_TAHITI_6792, "TAHITI" }, - { PCI_CHIP_TAHITI_6798, "TAHITI" }, - { PCI_CHIP_TAHITI_6799, "TAHITI" }, - { PCI_CHIP_TAHITI_679A, "TAHITI" }, - { PCI_CHIP_TAHITI_679B, "TAHITI" }, - { PCI_CHIP_TAHITI_679E, "TAHITI" }, - { PCI_CHIP_TAHITI_679F, "TAHITI" }, - { PCI_CHIP_PITCAIRN_6800, "PITCAIRN" }, - { PCI_CHIP_PITCAIRN_6801, "PITCAIRN" }, - { PCI_CHIP_PITCAIRN_6802, "PITCAIRN" }, - { PCI_CHIP_PITCAIRN_6806, "PITCAIRN" }, - { PCI_CHIP_PITCAIRN_6808, "PITCAIRN" }, - { PCI_CHIP_PITCAIRN_6809, "PITCAIRN" }, - { PCI_CHIP_PITCAIRN_6810, "PITCAIRN" }, - { PCI_CHIP_PITCAIRN_6811, "PITCAIRN" }, - { PCI_CHIP_PITCAIRN_6816, "PITCAIRN" }, - { PCI_CHIP_PITCAIRN_6817, "PITCAIRN" }, - { PCI_CHIP_PITCAIRN_6818, "PITCAIRN" }, - { PCI_CHIP_PITCAIRN_6819, "PITCAIRN" }, - { PCI_CHIP_VERDE_6820, "VERDE" }, - { PCI_CHIP_VERDE_6821, "VERDE" }, - { PCI_CHIP_VERDE_6822, "VERDE" }, - { PCI_CHIP_VERDE_6823, "VERDE" }, - { PCI_CHIP_VERDE_6824, "VERDE" }, - { PCI_CHIP_VERDE_6825, "VERDE" }, - { PCI_CHIP_VERDE_6826, "VERDE" }, - { PCI_CHIP_VERDE_6827, "VERDE" }, - { PCI_CHIP_VERDE_6828, "VERDE" }, - { PCI_CHIP_VERDE_6829, "VERDE" }, - { PCI_CHIP_VERDE_682A, "VERDE" }, - { PCI_CHIP_VERDE_682B, "VERDE" }, - { PCI_CHIP_VERDE_682C, "VERDE" }, - { PCI_CHIP_VERDE_682D, "VERDE" }, - { PCI_CHIP_VERDE_682F, "VERDE" }, - { PCI_CHIP_VERDE_6830, "VERDE" }, - { PCI_CHIP_VERDE_6831, "VERDE" }, - { PCI_CHIP_VERDE_6835, "VERDE" }, - { PCI_CHIP_VERDE_6837, "VERDE" }, - { PCI_CHIP_VERDE_6838, "VERDE" }, - { PCI_CHIP_VERDE_6839, "VERDE" }, - { PCI_CHIP_VERDE_683B, "VERDE" }, - { PCI_CHIP_VERDE_683D, "VERDE" }, - { PCI_CHIP_VERDE_683F, "VERDE" }, - { PCI_CHIP_PITCAIRN_684C, "PITCAIRN" }, - { PCI_CHIP_BONAIRE_6640, "BONAIRE" }, - { PCI_CHIP_BONAIRE_6641, "BONAIRE" }, - { PCI_CHIP_BONAIRE_6646, "BONAIRE" }, - { PCI_CHIP_BONAIRE_6647, "BONAIRE" }, - { PCI_CHIP_BONAIRE_6649, "BONAIRE" }, - { PCI_CHIP_BONAIRE_6650, "BONAIRE" }, - { PCI_CHIP_BONAIRE_6651, "BONAIRE" }, - { PCI_CHIP_BONAIRE_6658, "BONAIRE" }, - { PCI_CHIP_BONAIRE_665C, "BONAIRE" }, - { PCI_CHIP_BONAIRE_665D, "BONAIRE" }, - { PCI_CHIP_BONAIRE_665F, "BONAIRE" }, - { PCI_CHIP_KABINI_9830, "KABINI" }, - { PCI_CHIP_KABINI_9831, "KABINI" }, - { PCI_CHIP_KABINI_9832, "KABINI" }, - { PCI_CHIP_KABINI_9833, "KABINI" }, - { PCI_CHIP_KABINI_9834, "KABINI" }, - { PCI_CHIP_KABINI_9835, "KABINI" }, - { PCI_CHIP_KABINI_9836, "KABINI" }, - { PCI_CHIP_KABINI_9837, "KABINI" }, - { PCI_CHIP_KABINI_9838, "KABINI" }, - { PCI_CHIP_KABINI_9839, "KABINI" }, - { PCI_CHIP_KABINI_983A, "KABINI" }, - { PCI_CHIP_KABINI_983B, "KABINI" }, - { PCI_CHIP_KABINI_983C, "KABINI" }, - { PCI_CHIP_KABINI_983D, "KABINI" }, - { PCI_CHIP_KABINI_983E, "KABINI" }, - { PCI_CHIP_KABINI_983F, "KABINI" }, - { PCI_CHIP_MULLINS_9850, "MULLINS" }, - { PCI_CHIP_MULLINS_9851, "MULLINS" }, - { PCI_CHIP_MULLINS_9852, "MULLINS" }, - { PCI_CHIP_MULLINS_9853, "MULLINS" }, - { PCI_CHIP_MULLINS_9854, "MULLINS" }, - { PCI_CHIP_MULLINS_9855, "MULLINS" }, - { PCI_CHIP_MULLINS_9856, "MULLINS" }, - { PCI_CHIP_MULLINS_9857, "MULLINS" }, - { PCI_CHIP_MULLINS_9858, "MULLINS" }, - { PCI_CHIP_MULLINS_9859, "MULLINS" }, - { PCI_CHIP_MULLINS_985A, "MULLINS" }, - { PCI_CHIP_MULLINS_985B, "MULLINS" }, - { PCI_CHIP_MULLINS_985C, "MULLINS" }, - { PCI_CHIP_MULLINS_985D, "MULLINS" }, - { PCI_CHIP_MULLINS_985E, "MULLINS" }, - { PCI_CHIP_MULLINS_985F, "MULLINS" }, - { PCI_CHIP_KAVERI_1304, "KAVERI" }, - { PCI_CHIP_KAVERI_1305, "KAVERI" }, - { PCI_CHIP_KAVERI_1306, "KAVERI" }, - { PCI_CHIP_KAVERI_1307, "KAVERI" }, - { PCI_CHIP_KAVERI_1309, "KAVERI" }, - { PCI_CHIP_KAVERI_130A, "KAVERI" }, - { PCI_CHIP_KAVERI_130B, "KAVERI" }, - { PCI_CHIP_KAVERI_130C, "KAVERI" }, - { PCI_CHIP_KAVERI_130D, "KAVERI" }, - { PCI_CHIP_KAVERI_130E, "KAVERI" }, - { PCI_CHIP_KAVERI_130F, "KAVERI" }, - { PCI_CHIP_KAVERI_1310, "KAVERI" }, - { PCI_CHIP_KAVERI_1311, "KAVERI" }, - { PCI_CHIP_KAVERI_1312, "KAVERI" }, - { PCI_CHIP_KAVERI_1313, "KAVERI" }, - { PCI_CHIP_KAVERI_1315, "KAVERI" }, - { PCI_CHIP_KAVERI_1316, "KAVERI" }, - { PCI_CHIP_KAVERI_1317, "KAVERI" }, - { PCI_CHIP_KAVERI_1318, "KAVERI" }, - { PCI_CHIP_KAVERI_131B, "KAVERI" }, - { PCI_CHIP_KAVERI_131C, "KAVERI" }, - { PCI_CHIP_KAVERI_131D, "KAVERI" }, - { PCI_CHIP_HAWAII_67A0, "HAWAII" }, - { PCI_CHIP_HAWAII_67A1, "HAWAII" }, - { PCI_CHIP_HAWAII_67A2, "HAWAII" }, - { PCI_CHIP_HAWAII_67A8, "HAWAII" }, - { PCI_CHIP_HAWAII_67A9, "HAWAII" }, - { PCI_CHIP_HAWAII_67AA, "HAWAII" }, - { PCI_CHIP_HAWAII_67B0, "HAWAII" }, - { PCI_CHIP_HAWAII_67B1, "HAWAII" }, - { PCI_CHIP_HAWAII_67B8, "HAWAII" }, - { PCI_CHIP_HAWAII_67B9, "HAWAII" }, - { PCI_CHIP_HAWAII_67BA, "HAWAII" }, - { PCI_CHIP_HAWAII_67BE, "HAWAII" }, - { PCI_CHIP_TOPAZ_6900, "TOPAZ" }, - { PCI_CHIP_TOPAZ_6901, "TOPAZ" }, - { PCI_CHIP_TOPAZ_6902, "TOPAZ" }, - { PCI_CHIP_TOPAZ_6903, "TOPAZ" }, - { PCI_CHIP_TOPAZ_6907, "TOPAZ" }, - { PCI_CHIP_TONGA_6920, "TONGA" }, - { PCI_CHIP_TONGA_6921, "TONGA" }, - { PCI_CHIP_TONGA_6928, "TONGA" }, - { PCI_CHIP_TONGA_6929, "TONGA" }, - { PCI_CHIP_TONGA_692B, "TONGA" }, - { PCI_CHIP_TONGA_692F, "TONGA" }, - { PCI_CHIP_TONGA_6930, "TONGA" }, - { PCI_CHIP_TONGA_6938, "TONGA" }, - { PCI_CHIP_TONGA_6939, "TONGA" }, - { PCI_CHIP_CARRIZO_9870, "CARRIZO" }, - { PCI_CHIP_CARRIZO_9874, "CARRIZO" }, - { PCI_CHIP_CARRIZO_9875, "CARRIZO" }, - { PCI_CHIP_CARRIZO_9876, "CARRIZO" }, - { PCI_CHIP_CARRIZO_9877, "CARRIZO" }, - { PCI_CHIP_FIJI_7300, "FIJI" }, - { PCI_CHIP_STONEY_98E4, "STONEY" }, - { PCI_CHIP_POLARIS11_67E0, "POLARIS11" }, - { PCI_CHIP_POLARIS11_67E3, "POLARIS11" }, - { PCI_CHIP_POLARIS11_67E8, "POLARIS11" }, - { PCI_CHIP_POLARIS11_67EB, "POLARIS11" }, - { PCI_CHIP_POLARIS11_67EF, "POLARIS11" }, - { PCI_CHIP_POLARIS11_67FF, "POLARIS11" }, - { PCI_CHIP_POLARIS11_67E1, "POLARIS11" }, - { PCI_CHIP_POLARIS11_67E7, "POLARIS11" }, - { PCI_CHIP_POLARIS11_67E9, "POLARIS11" }, - { PCI_CHIP_POLARIS10_67C0, "POLARIS10" }, - { PCI_CHIP_POLARIS10_67C1, "POLARIS10" }, - { PCI_CHIP_POLARIS10_67C2, "POLARIS10" }, - { PCI_CHIP_POLARIS10_67C4, "POLARIS10" }, - { PCI_CHIP_POLARIS10_67C7, "POLARIS10" }, - { PCI_CHIP_POLARIS10_67DF, "POLARIS10" }, - { PCI_CHIP_POLARIS10_67C8, "POLARIS10" }, - { PCI_CHIP_POLARIS10_67C9, "POLARIS10" }, - { PCI_CHIP_POLARIS10_67CA, "POLARIS10" }, - { PCI_CHIP_POLARIS10_67CC, "POLARIS10" }, - { PCI_CHIP_POLARIS10_67CF, "POLARIS10" }, - { -1, NULL } -}; - -SymTabRec AMDGPUUniqueChipsets[] = { - { 0, "OLAND" }, - { 0, "HAINAN" }, - { 0, "TAHITI" }, - { 0, "PITCAIRN" }, - { 0, "VERDE" }, - { 0, "BONAIRE" }, - { 0, "KABINI" }, - { 0, "MULLINS" }, - { 0, "KAVERI" }, - { 0, "HAWAII" }, - { 0, "TOPAZ" }, - { 0, "TONGA" }, - { 0, "CARRIZO" }, - { 0, "FIJI" }, - { 0, "STONEY" }, - { 0, "POLARIS11" }, - { 0, "POLARIS10" }, - { -1, NULL } -}; diff -Nru xserver-xorg-video-amdgpu-1.2.0/src/amdgpu_dri2.c xserver-xorg-video-amdgpu-1.3.0/src/amdgpu_dri2.c --- xserver-xorg-video-amdgpu-1.2.0/src/amdgpu_dri2.c 2016-09-20 08:19:15.000000000 +0000 +++ xserver-xorg-video-amdgpu-1.3.0/src/amdgpu_dri2.c 2017-03-16 08:32:47.000000000 +0000 @@ -51,6 +51,7 @@ #include "amdgpu_list.h" #include +#include #if DRI2INFOREC_VERSION >= 9 #define USE_DRI2_PRIME @@ -465,9 +466,9 @@ static void amdgpu_dri2_flip_event_abort(xf86CrtcPtr crtc, void *event_data) { - AMDGPUInfoPtr info = AMDGPUPTR(crtc->scrn); + if (crtc) + AMDGPUPTR(crtc->scrn)->drmmode.dri2_flipping = FALSE; - info->drmmode.dri2_flipping = FALSE; free(event_data); } @@ -563,7 +564,8 @@ AMDGPU_DRM_QUEUE_ID_DEFAULT, flip_info, ref_crtc_hw_id, amdgpu_dri2_flip_event_handler, - amdgpu_dri2_flip_event_abort, FLIP_VSYNC)) { + amdgpu_dri2_flip_event_abort, FLIP_VSYNC, + target_msc - amdgpu_get_msc_delta(draw, crtc))) { info->drmmode.dri2_flipping = TRUE; return TRUE; } @@ -636,13 +638,34 @@ DRI2BufferPtr front, DRI2BufferPtr back) { AMDGPUInfoPtr info = AMDGPUPTR(pScrn); + xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR(pScrn); + int num_crtcs_on; + int i; + + if (draw->type != DRAWABLE_WINDOW || + !info->allowPageFlip || + info->hwcursor_disabled || + info->drmmode.present_flipping || + !pScrn->vtSema || + !DRI2CanFlip(draw)) + return FALSE; + + for (i = 0, num_crtcs_on = 0; i < config->num_crtc; i++) { + xf86CrtcPtr crtc = config->crtc[i]; + drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private; + + if (!crtc->enabled) + continue; - return draw->type == DRAWABLE_WINDOW && - info->allowPageFlip && - !info->hwcursor_disabled && - !info->drmmode.present_flipping && - pScrn->vtSema && - DRI2CanFlip(draw) && can_exchange(pScrn, draw, front, back); + if (!drmmode_crtc || drmmode_crtc->rotate.bo || + drmmode_crtc->scanout[0].bo) + return FALSE; + + if (drmmode_crtc->pending_dpms_mode == DPMSModeOn) + num_crtcs_on++; + } + + return num_crtcs_on > 0 && can_exchange(pScrn, draw, front, back); } static void @@ -783,14 +806,8 @@ if (crtc_id == 1) type |= DRM_VBLANK_SECONDARY; else if (crtc_id > 1) -#ifdef DRM_VBLANK_HIGH_CRTC_SHIFT type |= (crtc_id << DRM_VBLANK_HIGH_CRTC_SHIFT) & DRM_VBLANK_HIGH_CRTC_MASK; -#else - ErrorF("amdgpu driver bug: %s called for CRTC %d > 1, but " - "DRM_VBLANK_HIGH_CRTC_MASK not defined at build time\n", - __func__, crtc_id); -#endif return type; } @@ -1365,7 +1382,6 @@ dri2_info.CopyRegion = amdgpu_dri2_copy_region; if (info->drmmode.count_crtcs > 2) { -#ifdef DRM_CAP_VBLANK_HIGH_CRTC uint64_t cap_value; if (drmGetCap @@ -1380,12 +1396,6 @@ "handle VBLANKs on CRTC > 1\n"); scheduling_works = FALSE; } -#else - xf86DrvMsg(pScrn->scrnIndex, X_WARNING, - "You need to rebuild against a " - "newer libdrm to handle VBLANKs on CRTC > 1\n"); - scheduling_works = FALSE; -#endif } if (scheduling_works) { diff -Nru xserver-xorg-video-amdgpu-1.2.0/src/amdgpu_dri3.c xserver-xorg-video-amdgpu-1.3.0/src/amdgpu_dri3.c --- xserver-xorg-video-amdgpu-1.2.0/src/amdgpu_dri3.c 2016-09-20 08:19:15.000000000 +0000 +++ xserver-xorg-video-amdgpu-1.3.0/src/amdgpu_dri3.c 2017-03-16 08:32:47.000000000 +0000 @@ -40,9 +40,7 @@ #include #include - -static int -amdgpu_dri3_open(ScreenPtr screen, RRProviderPtr provider, int *out) +static int open_master_node(ScreenPtr screen, int *out) { ScrnInfoPtr scrn = xf86ScreenToScrn(screen); AMDGPUEntPtr pAMDGPUEnt = AMDGPUEntPriv(scrn); @@ -88,6 +86,36 @@ return Success; } +static int open_render_node(ScreenPtr screen, int *out) +{ + ScrnInfoPtr scrn = xf86ScreenToScrn(screen); + AMDGPUEntPtr pAMDGPUEnt = AMDGPUEntPriv(scrn); + int fd; + + fd = open(pAMDGPUEnt->render_node, O_RDWR | O_CLOEXEC); + if (fd < 0) + return BadAlloc; + + *out = fd; + return Success; +} + +static int +amdgpu_dri3_open(ScreenPtr screen, RRProviderPtr provider, int *out) +{ + ScrnInfoPtr scrn = xf86ScreenToScrn(screen); + AMDGPUEntPtr pAMDGPUEnt = AMDGPUEntPriv(scrn); + int ret = BadAlloc; + + if (pAMDGPUEnt->render_node) + ret = open_render_node(screen, out); + + if (ret != Success) + ret = open_master_node(screen, out); + + return ret; +} + #if DRI3_SCREEN_INFO_VERSION >= 1 && XORG_VERSION_CURRENT <= XORG_VERSION_NUMERIC(1,18,99,1,0) static int @@ -229,6 +257,9 @@ amdgpu_dri3_screen_init(ScreenPtr screen) { ScrnInfoPtr scrn = xf86ScreenToScrn(screen); + AMDGPUEntPtr pAMDGPUEnt = AMDGPUEntPriv(scrn); + + pAMDGPUEnt->render_node = drmGetRenderDeviceNameFromFd(pAMDGPUEnt->fd); if (!dri3_screen_init(screen, &amdgpu_dri3_screen_info)) { xf86DrvMsg(scrn->scrnIndex, X_WARNING, diff -Nru xserver-xorg-video-amdgpu-1.2.0/src/amdgpu_drv.h xserver-xorg-video-amdgpu-1.3.0/src/amdgpu_drv.h --- xserver-xorg-video-amdgpu-1.2.0/src/amdgpu_drv.h 2016-11-17 06:07:48.000000000 +0000 +++ xserver-xorg-video-amdgpu-1.3.0/src/amdgpu_drv.h 2017-03-16 08:32:47.000000000 +0000 @@ -86,10 +86,28 @@ #include "compat-api.h" #include "simple_list.h" -#include "amdpciids.h" struct _SyncFence; +#ifndef HAVE_REGIONDUPLICATE + +static inline RegionPtr +RegionDuplicate(RegionPtr pOld) +{ + RegionPtr pNew; + + pNew = RegionCreate(&pOld->extents, 0); + if (!pNew) + return NULL; + if (!RegionCopy(pNew, pOld)) { + RegionDestroy(pNew); + return NULL; + } + return pNew; +} + +#endif + #ifndef MAX #define MAX(a,b) ((a)>(b)?(a):(b)) #endif @@ -150,6 +168,11 @@ #if XF86_CRTC_VERSION >= 5 #define AMDGPU_PIXMAP_SHARING 1 +#define amdgpu_is_gpu_screen(screen) (screen)->isGPU +#define amdgpu_is_gpu_scrn(scrn) (scrn)->is_gpu +#else +#define amdgpu_is_gpu_screen(screen) 0 +#define amdgpu_is_gpu_scrn(scrn) 0 #endif #define AMDGPU_VSYNC_TIMEOUT 20000 /* Maximum wait for VSYNC (in usecs) */ @@ -191,9 +214,9 @@ typedef struct { EntityInfoPtr pEnt; - pciVideoPtr PciInfo; + struct pci_device *PciInfo; int Chipset; - AMDGPUChipFamily ChipFamily; + uint32_t family; struct gbm_device *gbm; Bool(*CloseScreen) (CLOSE_SCREEN_ARGS_DECL); @@ -219,7 +242,7 @@ Bool use_glamor; Bool force_accel; Bool shadow_primary; - Bool tear_free; + int tear_free; /* general */ OptionInfoPtr Options; @@ -228,6 +251,7 @@ CreateScreenResourcesProcPtr CreateScreenResources; CreateWindowProcPtr CreateWindow; + WindowExposuresProcPtr WindowExposures; Bool IsSecondary; @@ -290,8 +314,7 @@ Bool amdgpu_dri3_screen_init(ScreenPtr screen); /* amdgpu_kms.c */ -void amdgpu_scanout_update_handler(xf86CrtcPtr crtc, uint32_t frame, - uint64_t usec, void *event_data); +Bool amdgpu_scanout_do_update(xf86CrtcPtr xf86_crtc, int scanout_id); /* amdgpu_present.c */ Bool amdgpu_present_screen_init(ScreenPtr screen); diff -Nru xserver-xorg-video-amdgpu-1.2.0/src/amdgpu_glamor.c xserver-xorg-video-amdgpu-1.3.0/src/amdgpu_glamor.c --- xserver-xorg-video-amdgpu-1.2.0/src/amdgpu_glamor.c 2016-09-20 08:19:15.000000000 +0000 +++ xserver-xorg-video-amdgpu-1.3.0/src/amdgpu_glamor.c 2017-03-16 08:32:47.000000000 +0000 @@ -36,7 +36,9 @@ #include +#ifndef HAVE_GLAMOR_FINISH #include +#endif DevPrivateKeyRec amdgpu_pixmap_index; @@ -470,8 +472,13 @@ AMDGPUInfoPtr info = AMDGPUPTR(pScrn); if (info->use_glamor) { +#if HAVE_GLAMOR_FINISH + glamor_finish(pScrn->pScreen); + info->gpu_flushed++; +#else amdgpu_glamor_flush(pScrn); glFinish(); +#endif } } diff -Nru xserver-xorg-video-amdgpu-1.2.0/src/amdgpu_kms.c xserver-xorg-video-amdgpu-1.3.0/src/amdgpu_kms.c --- xserver-xorg-video-amdgpu-1.2.0/src/amdgpu_kms.c 2016-11-17 06:07:48.000000000 +0000 +++ xserver-xorg-video-amdgpu-1.3.0/src/amdgpu_kms.c 2017-03-16 08:32:47.000000000 +0000 @@ -41,8 +41,6 @@ #include "shadow.h" #include -#include "amdpciids.h" - /* DPMS */ #ifdef HAVE_XEXTPROTO_71 #include @@ -53,7 +51,6 @@ #include -#include "amdgpu_chipinfo_gen.h" #include "amdgpu_bo_helper.h" #include "amdgpu_pixmap.h" @@ -61,7 +58,6 @@ static DevScreenPrivateKeyRec amdgpu_client_private_key; -extern SymTabRec AMDGPUChipsets[]; static Bool amdgpu_setup_kernel_mem(ScreenPtr pScreen); const OptionInfoRec AMDGPUOptions_KMS[] = { @@ -136,12 +132,7 @@ pAMDGPUEnt->fd_ref--; if (!pAMDGPUEnt->fd_ref) { amdgpu_device_deinitialize(pAMDGPUEnt->pDev); -#ifdef XF86_PDEV_SERVER_FD - if (!(pAMDGPUEnt->platform_dev && - pAMDGPUEnt->platform_dev->flags & XF86_PDEV_SERVER_FD)) -#endif - drmClose(pAMDGPUEnt->fd); - pAMDGPUEnt->fd = 0; + amdgpu_kernel_close_fd(pAMDGPUEnt); } } @@ -227,7 +218,7 @@ static Bool AMDGPUCreateScreenResources_KMS(ScreenPtr pScreen) { - ExtensionEntry *damage_ext = CheckExtension("DAMAGE"); + ExtensionEntry *damage_ext; ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); AMDGPUInfoPtr info = AMDGPUPTR(pScrn); PixmapPtr pixmap; @@ -241,10 +232,7 @@ if (dixPrivateKeyRegistered(rrPrivKey)) { rrScrPrivPtr rrScrPriv = rrGetScrPriv(pScreen); - if ( -#ifdef AMDGPU_PIXMAP_SHARING - !pScreen->isGPU && -#endif + if (!amdgpu_is_gpu_screen(pScreen) && !rrScrPriv->primaryOutput) { xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); @@ -255,7 +243,8 @@ } } - if (!drmmode_set_desired_modes(pScrn, &info->drmmode, pScrn->is_gpu)) + if (!drmmode_set_desired_modes(pScrn, &info->drmmode, + amdgpu_is_gpu_screen(pScreen))) return FALSE; drmmode_uevent_init(pScrn, &info->drmmode); @@ -281,7 +270,8 @@ amdgpu_glamor_create_screen_resources(pScreen); info->callback_event_type = -1; - if (damage_ext) { + if (!amdgpu_is_gpu_screen(pScreen) && + (damage_ext = CheckExtension("DAMAGE"))) { info->callback_event_type = damage_ext->eventBase + XDamageNotify; if (!AddCallback(&FlushCallback, amdgpu_flush_callback, pScrn)) @@ -306,11 +296,21 @@ static Bool amdgpu_scanout_extents_intersect(xf86CrtcPtr xf86_crtc, BoxPtr extents) { - extents->x1 -= xf86_crtc->filter_width >> 1; - extents->x2 += xf86_crtc->filter_width >> 1; - extents->y1 -= xf86_crtc->filter_height >> 1; - extents->y2 += xf86_crtc->filter_height >> 1; - pixman_f_transform_bounds(&xf86_crtc->f_framebuffer_to_crtc, extents); +#ifdef AMDGPU_PIXMAP_SHARING + if (xf86_crtc->scrn->is_gpu) { + extents->x1 -= xf86_crtc->x; + extents->y1 -= xf86_crtc->y; + extents->x2 -= xf86_crtc->x; + extents->y2 -= xf86_crtc->y; + } else +#endif + { + extents->x1 -= xf86_crtc->filter_width >> 1; + extents->x2 += xf86_crtc->filter_width >> 1; + extents->y1 -= xf86_crtc->filter_height >> 1; + extents->y2 += xf86_crtc->filter_height >> 1; + pixman_f_transform_bounds(&xf86_crtc->f_framebuffer_to_crtc, extents); + } extents->x1 = max(extents->x1, 0); extents->y1 = max(extents->y1, 0); @@ -320,6 +320,8 @@ return (extents->x1 < extents->x2 && extents->y1 < extents->y2); } +#if XF86_CRTC_VERSION >= 4 + static RegionPtr transform_region(RegionPtr region, struct pict_f_transform *transform, int w, int h) @@ -358,6 +360,8 @@ return transformed; } +#endif + static void amdgpu_sync_scanout_pixmaps(xf86CrtcPtr xf86_crtc, RegionPtr new_region, int scanout_id) @@ -399,8 +403,8 @@ gc = GetScratchGC(dst->depth, pScreen); if (gc) { - ValidateGC(dst, gc); gc->funcs->ChangeClip(gc, CT_REGION, sync_region, 0); + ValidateGC(dst, gc); sync_region = NULL; gc->ops->CopyArea(src, dst, gc, 0, 0, dst->width, dst->height, 0, 0); FreeScratchGC(gc); @@ -545,12 +549,32 @@ #endif /* HAS_SYNC_SHARED_PIXMAPS */ +static xf86CrtcPtr +amdgpu_prime_dirty_to_crtc(PixmapDirtyUpdatePtr dirty) +{ + ScreenPtr screen = dirty->slave_dst->drawable.pScreen; + ScrnInfoPtr scrn = xf86ScreenToScrn(screen); + xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(scrn); + int c; + + /* Find the CRTC which is scanning out from this slave pixmap */ + for (c = 0; c < xf86_config->num_crtc; c++) { + xf86CrtcPtr xf86_crtc = xf86_config->crtc[c]; + drmmode_crtc_private_ptr drmmode_crtc = xf86_crtc->driver_private; + + if (drmmode_crtc->scanout[0].pixmap == dirty->slave_dst || + drmmode_crtc->scanout[1].pixmap == dirty->slave_dst) + return xf86_crtc; + } + + return NULL; +} + static Bool amdgpu_prime_scanout_do_update(xf86CrtcPtr crtc, unsigned scanout_id) { ScrnInfoPtr scrn = crtc->scrn; ScreenPtr screen = scrn->pScreen; - AMDGPUInfoPtr info = AMDGPUPTR(scrn); drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private; PixmapPtr scanoutpix = crtc->randr_crtc->scanout_pixmap; PixmapDirtyUpdatePtr dirty; @@ -558,7 +582,7 @@ xorg_list_for_each_entry(dirty, &screen->pixmap_dirty_list, ent) { if (dirty->src == scanoutpix && dirty->slave_dst == - drmmode_crtc->scanout[scanout_id ^ info->tear_free].pixmap) { + drmmode_crtc->scanout[scanout_id ^ drmmode_crtc->tear_free].pixmap) { RegionPtr region; if (master_has_sync_shared_pixmap(scrn, dirty)) @@ -568,7 +592,7 @@ if (RegionNil(region)) goto destroy; - if (info->tear_free) { + if (drmmode_crtc->tear_free) { RegionTranslate(region, crtc->x, crtc->y); amdgpu_sync_scanout_pixmaps(crtc, region, scanout_id); amdgpu_glamor_flush(scrn); @@ -588,7 +612,7 @@ return ret; } -void +static void amdgpu_prime_scanout_update_handler(xf86CrtcPtr crtc, uint32_t frame, uint64_t usec, void *event_data) { @@ -604,24 +628,16 @@ ScreenPtr screen = dirty->slave_dst->drawable.pScreen; ScrnInfoPtr scrn = xf86ScreenToScrn(screen); AMDGPUEntPtr pAMDGPUEnt = AMDGPUEntPriv(scrn); - xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(scrn); - xf86CrtcPtr xf86_crtc = NULL; - drmmode_crtc_private_ptr drmmode_crtc = NULL; + xf86CrtcPtr xf86_crtc = amdgpu_prime_dirty_to_crtc(dirty); + drmmode_crtc_private_ptr drmmode_crtc; uintptr_t drm_queue_seq; drmVBlank vbl; - int c; - /* Find the CRTC which is scanning out from this slave pixmap */ - for (c = 0; c < xf86_config->num_crtc; c++) { - xf86_crtc = xf86_config->crtc[c]; - drmmode_crtc = xf86_crtc->driver_private; - if (drmmode_crtc->scanout[0].pixmap == dirty->slave_dst) - break; - } + if (!xf86_crtc || !xf86_crtc->enabled) + return; - if (c == xf86_config->num_crtc || - !xf86_crtc->enabled || - drmmode_crtc->scanout_update_pending || + drmmode_crtc = xf86_crtc->driver_private; + if (drmmode_crtc->scanout_update_pending || !drmmode_crtc->scanout[0].pixmap || drmmode_crtc->pending_dpms_mode != DPMSModeOn) return; @@ -667,25 +683,16 @@ ScreenPtr screen = ent->slave_dst->drawable.pScreen; ScrnInfoPtr scrn = xf86ScreenToScrn(screen); AMDGPUEntPtr pAMDGPUEnt = AMDGPUEntPriv(scrn); - xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(scrn); - xf86CrtcPtr crtc = NULL; - drmmode_crtc_private_ptr drmmode_crtc = NULL; + xf86CrtcPtr crtc = amdgpu_prime_dirty_to_crtc(ent); + drmmode_crtc_private_ptr drmmode_crtc; uintptr_t drm_queue_seq; unsigned scanout_id; - int c; - /* Find the CRTC which is scanning out from this slave pixmap */ - for (c = 0; c < xf86_config->num_crtc; c++) { - crtc = xf86_config->crtc[c]; - drmmode_crtc = crtc->driver_private; - scanout_id = drmmode_crtc->scanout_id; - if (drmmode_crtc->scanout[scanout_id].pixmap == ent->slave_dst) - break; - } + if (!crtc || !crtc->enabled) + return; - if (c == xf86_config->num_crtc || - !crtc->enabled || - drmmode_crtc->scanout_update_pending || + drmmode_crtc = crtc->driver_private; + if (drmmode_crtc->scanout_update_pending || !drmmode_crtc->scanout[drmmode_crtc->scanout_id].pixmap || drmmode_crtc->pending_dpms_mode != DPMSModeOn) return; @@ -705,11 +712,12 @@ return; } - if (drmModePageFlip(pAMDGPUEnt->fd, drmmode_crtc->mode_crtc->crtc_id, - drmmode_crtc->scanout[scanout_id].fb_id, - DRM_MODE_PAGE_FLIP_EVENT, (void*)drm_queue_seq)) { + if (drmmode_page_flip_target_relative(pAMDGPUEnt, drmmode_crtc, + drmmode_crtc->scanout[scanout_id].fb_id, + 0, drm_queue_seq, 0) != 0) { xf86DrvMsg(scrn->scrnIndex, X_WARNING, "flip queue failed in %s: %s\n", __func__, strerror(errno)); + amdgpu_drm_abort_entry(drm_queue_seq); return; } @@ -721,7 +729,6 @@ static void amdgpu_dirty_update(ScrnInfoPtr scrn) { - AMDGPUInfoPtr info = AMDGPUPTR(scrn); ScreenPtr screen = scrn->pScreen; PixmapDirtyUpdatePtr ent; RegionPtr region; @@ -742,7 +749,13 @@ region = dirty_region(region_ent); if (RegionNotEmpty(region)) { - if (info->tear_free) + xf86CrtcPtr crtc = amdgpu_prime_dirty_to_crtc(ent); + drmmode_crtc_private_ptr drmmode_crtc = NULL; + + if (crtc) + drmmode_crtc = crtc->driver_private; + + if (drmmode_crtc && drmmode_crtc->tear_free) amdgpu_prime_scanout_flip(ent); else amdgpu_prime_scanout_update(ent); @@ -763,19 +776,17 @@ } #endif -static Bool +Bool amdgpu_scanout_do_update(xf86CrtcPtr xf86_crtc, int scanout_id) { drmmode_crtc_private_ptr drmmode_crtc = xf86_crtc->driver_private; RegionPtr pRegion = DamageRegion(drmmode_crtc->scanout_damage); ScrnInfoPtr scrn = xf86_crtc->scrn; ScreenPtr pScreen = scrn->pScreen; - AMDGPUInfoPtr info = AMDGPUPTR(scrn); DrawablePtr pDraw; BoxRec extents; if (!xf86_crtc->enabled || - drmmode_crtc->pending_dpms_mode != DPMSModeOn || !drmmode_crtc->scanout[scanout_id].pixmap) return FALSE; @@ -787,7 +798,7 @@ if (!amdgpu_scanout_extents_intersect(xf86_crtc, &extents)) return FALSE; - if (info->tear_free) { + if (drmmode_crtc->tear_free) { amdgpu_sync_scanout_pixmaps(xf86_crtc, pRegion, scanout_id); RegionCopy(&drmmode_crtc->scanout_last_region, pRegion); } @@ -869,7 +880,7 @@ drmmode_crtc->scanout_update_pending = FALSE; } -void +static void amdgpu_scanout_update_handler(xf86CrtcPtr crtc, uint32_t frame, uint64_t usec, void *event_data) { @@ -953,19 +964,19 @@ xf86CrtcPtr xf86_crtc) { drmmode_crtc_private_ptr drmmode_crtc = xf86_crtc->driver_private; - ScrnInfoPtr scrn; - AMDGPUEntPtr pAMDGPUEnt; + ScrnInfoPtr scrn = xf86_crtc->scrn; + AMDGPUEntPtr pAMDGPUEnt = AMDGPUEntPriv(scrn); uintptr_t drm_queue_seq; unsigned scanout_id; - if (drmmode_crtc->scanout_update_pending) + if (drmmode_crtc->scanout_update_pending || + drmmode_crtc->pending_dpms_mode != DPMSModeOn) return; scanout_id = drmmode_crtc->scanout_id ^ 1; if (!amdgpu_scanout_do_update(xf86_crtc, scanout_id)) return; - scrn = xf86_crtc->scrn; drm_queue_seq = amdgpu_drm_queue_alloc(xf86_crtc, AMDGPU_DRM_QUEUE_CLIENT_DEFAULT, AMDGPU_DRM_QUEUE_ID_DEFAULT, @@ -977,12 +988,12 @@ return; } - pAMDGPUEnt = AMDGPUEntPriv(scrn); - if (drmModePageFlip(pAMDGPUEnt->fd, drmmode_crtc->mode_crtc->crtc_id, - drmmode_crtc->scanout[scanout_id].fb_id, - DRM_MODE_PAGE_FLIP_EVENT, (void*)drm_queue_seq)) { + if (drmmode_page_flip_target_relative(pAMDGPUEnt, drmmode_crtc, + drmmode_crtc->scanout[scanout_id].fb_id, + 0, drm_queue_seq, 0) != 0) { xf86DrvMsg(scrn->scrnIndex, X_WARNING, "flip queue failed in %s: %s\n", __func__, strerror(errno)); + amdgpu_drm_abort_entry(drm_queue_seq); return; } @@ -1003,41 +1014,33 @@ (*pScreen->BlockHandler) (BLOCKHANDLER_ARGS); pScreen->BlockHandler = AMDGPUBlockHandler_KMS; -#ifdef AMDGPU_PIXMAP_SHARING - if (!pScreen->isGPU) -#endif + if (!amdgpu_is_gpu_screen(pScreen)) { for (c = 0; c < xf86_config->num_crtc; c++) { - if (info->tear_free) - amdgpu_scanout_flip(pScreen, info, xf86_config->crtc[c]); + xf86CrtcPtr crtc = xf86_config->crtc[c]; + drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private; + + if (drmmode_crtc->tear_free) + amdgpu_scanout_flip(pScreen, info, crtc); else if (info->shadow_primary #if XF86_CRTC_VERSION >= 4 - || xf86_config->crtc[c]->driverIsPerformingTransform + || crtc->driverIsPerformingTransform #endif ) - amdgpu_scanout_update(xf86_config->crtc[c]); + amdgpu_scanout_update(crtc); } } +#if XORG_VERSION_CURRENT < XORG_VERSION_NUMERIC(1,19,0,0,0) if (info->use_glamor) amdgpu_glamor_flush(pScrn); +#endif #ifdef AMDGPU_PIXMAP_SHARING amdgpu_dirty_update(pScrn); #endif } -static void AMDGPUBlockHandler_oneshot(BLOCKHANDLER_ARGS_DECL) -{ - SCREEN_PTR(arg); - ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); - AMDGPUInfoPtr info = AMDGPUPTR(pScrn); - - AMDGPUBlockHandler_KMS(BLOCKHANDLER_ARGS); - - drmmode_set_desired_modes(pScrn, &info->drmmode, TRUE); -} - /* This is called by AMDGPUPreInit to set up the default visual */ static Bool AMDGPUPreInitVisual(ScrnInfoPtr pScrn) { @@ -1159,19 +1162,16 @@ return TRUE; } -static Bool AMDGPUPreInitChipType_KMS(ScrnInfoPtr pScrn) +static Bool AMDGPUPreInitChipType_KMS(ScrnInfoPtr pScrn, + struct amdgpu_gpu_info *gpu_info) { AMDGPUInfoPtr info = AMDGPUPTR(pScrn); - int i; + AMDGPUEntPtr pAMDGPUEnt = AMDGPUEntPriv(pScrn); - info->Chipset = PCI_DEV_DEVICE_ID(info->PciInfo); - pScrn->chipset = - (char *)xf86TokenToString(AMDGPUChipsets, info->Chipset); - if (!pScrn->chipset) { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "ChipID 0x%04x is not recognized\n", info->Chipset); - return FALSE; - } + info->Chipset = info->PciInfo->device_id; + pScrn->chipset = amdgpu_get_marketing_name(pAMDGPUEnt->pDev); + if (!pScrn->chipset) + pScrn->chipset = "Unknown AMD Radeon GPU"; if (info->Chipset < 0) { xf86DrvMsg(pScrn->scrnIndex, X_ERROR, @@ -1183,27 +1183,15 @@ "Chipset: \"%s\" (ChipID = 0x%04x)\n", pScrn->chipset, info->Chipset); - for (i = 0; i < sizeof(AMDGPUCards) / sizeof(AMDGPUCardInfo); i++) { - if (info->Chipset == AMDGPUCards[i].pci_device_id) { - AMDGPUCardInfo *card = &AMDGPUCards[i]; - info->ChipFamily = card->chip_family; - break; - } - } + info->family = gpu_info->family_id; return TRUE; } -static Bool amdgpu_get_tile_config(ScrnInfoPtr pScrn) +static Bool amdgpu_get_tile_config(AMDGPUInfoPtr info, + struct amdgpu_gpu_info *gpu_info) { - AMDGPUInfoPtr info = AMDGPUPTR(pScrn); - AMDGPUEntPtr pAMDGPUEnt = AMDGPUEntPriv(pScrn); - struct amdgpu_gpu_info gpu_info; - - memset(&gpu_info, 0, sizeof(gpu_info)); - amdgpu_query_gpu_info(pAMDGPUEnt->pDev, &gpu_info); - - switch ((gpu_info.gb_addr_cfg & 0x70) >> 4) { + switch ((gpu_info->gb_addr_cfg & 0x70) >> 4) { case 0: info->group_bytes = 256; break; @@ -1269,10 +1257,37 @@ return ret; } +/* When the root window is mapped, set the initial modes */ +static void AMDGPUWindowExposures_oneshot(WindowPtr pWin, RegionPtr pRegion +#if XORG_VERSION_CURRENT < XORG_VERSION_NUMERIC(1,16,99,901,0) + , RegionPtr pBSRegion +#endif + ) +{ + ScreenPtr pScreen = pWin->drawable.pScreen; + ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); + AMDGPUInfoPtr info = AMDGPUPTR(pScrn); + + if (pWin != pScreen->root) + ErrorF("%s called for non-root window %p\n", __func__, pWin); + + pScreen->WindowExposures = info->WindowExposures; +#if XORG_VERSION_CURRENT < XORG_VERSION_NUMERIC(1,16,99,901,0) + pScreen->WindowExposures(pWin, pRegion, pBSRegion); +#else + pScreen->WindowExposures(pWin, pRegion); +#endif + + amdgpu_glamor_finish(pScrn); + drmmode_set_desired_modes(pScrn, &info->drmmode, TRUE); +} + Bool AMDGPUPreInit_KMS(ScrnInfoPtr pScrn, int flags) { AMDGPUInfoPtr info; AMDGPUEntPtr pAMDGPUEnt; + struct amdgpu_gpu_info gpu_info; + MessageType from; DevUnion *pPriv; Gamma zeros = { 0.0, 0.0, 0.0 }; int cpp; @@ -1334,7 +1349,10 @@ if (!AMDGPUPreInitWeight(pScrn)) goto fail; - if (!AMDGPUPreInitChipType_KMS(pScrn)) + memset(&gpu_info, 0, sizeof(gpu_info)); + amdgpu_query_gpu_info(pAMDGPUEnt->pDev, &gpu_info); + + if (!AMDGPUPreInitChipType_KMS(pScrn, &gpu_info)) goto fail; info->dri2.available = FALSE; @@ -1360,16 +1378,18 @@ /* set default group bytes, overridden by kernel info below */ info->group_bytes = 256; info->have_tiling_info = FALSE; - amdgpu_get_tile_config(pScrn); + amdgpu_get_tile_config(info, &gpu_info); } if (info->use_glamor) { - info->tear_free = xf86ReturnOptValBool(info->Options, - OPTION_TEAR_FREE, FALSE); + from = X_DEFAULT; - if (info->tear_free) - xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, - "TearFree enabled\n"); + info->tear_free = 2; + if (xf86GetOptValBool(info->Options, OPTION_TEAR_FREE, + &info->tear_free)) + from = X_CONFIG; + xf86DrvMsg(pScrn->scrnIndex, from, "TearFree property default: %s\n", + info->tear_free == 2 ? "auto" : (info->tear_free ? "on" : "off")); info->shadow_primary = xf86ReturnOptValBool(info->Options, OPTION_SHADOW_PRIMARY, FALSE); @@ -1378,23 +1398,26 @@ xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "ShadowPrimary enabled\n"); } - sw_cursor = xf86ReturnOptValBool(info->Options, OPTION_SW_CURSOR, FALSE); - - info->allowPageFlip = xf86ReturnOptValBool(info->Options, - OPTION_PAGE_FLIP, - TRUE); - if (sw_cursor || info->tear_free || info->shadow_primary) { - xf86DrvMsg(pScrn->scrnIndex, - info->allowPageFlip ? X_WARNING : X_DEFAULT, - "KMS Pageflipping: disabled%s\n", - info->allowPageFlip ? - (sw_cursor ? " because of SWcursor" : - " because of ShadowPrimary/TearFree") : ""); - info->allowPageFlip = FALSE; - } else { - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "KMS Pageflipping: %sabled\n", - info->allowPageFlip ? "en" : "dis"); + if (!amdgpu_is_gpu_scrn(pScrn)) { + sw_cursor = xf86ReturnOptValBool(info->Options, + OPTION_SW_CURSOR, FALSE); + + info->allowPageFlip = xf86ReturnOptValBool(info->Options, + OPTION_PAGE_FLIP, + TRUE); + if (sw_cursor || info->shadow_primary) { + xf86DrvMsg(pScrn->scrnIndex, + info->allowPageFlip ? X_WARNING : X_DEFAULT, + "KMS Pageflipping: disabled%s\n", + info->allowPageFlip ? + (sw_cursor ? " because of SWcursor" : + " because of ShadowPrimary") : ""); + info->allowPageFlip = FALSE; + } else { + xf86DrvMsg(pScrn->scrnIndex, X_INFO, + "KMS Pageflipping: %sabled\n", + info->allowPageFlip ? "en" : "dis"); + } } if (xf86ReturnOptValBool(info->Options, OPTION_DELETE_DP12, FALSE)) { @@ -1415,8 +1438,7 @@ else pAMDGPUEnt->HasCRTC2 = TRUE; - if (info->ChipFamily >= CHIP_FAMILY_TAHITI && - info->ChipFamily <= CHIP_FAMILY_HAINAN) { + if (info->family < AMDGPU_FAMILY_CI) { info->cursor_w = CURSOR_WIDTH; info->cursor_h = CURSOR_HEIGHT; } else { @@ -1718,31 +1740,33 @@ } #endif - value = xorgGetVersion() >= XORG_VERSION_NUMERIC(1,18,3,0,0); - from = X_DEFAULT; + if (!amdgpu_is_gpu_screen(pScreen)) { + value = xorgGetVersion() >= XORG_VERSION_NUMERIC(1,18,3,0,0); + from = X_DEFAULT; + + if (info->use_glamor) { + if (xf86GetOptValBool(info->Options, OPTION_DRI3, &value)) + from = X_CONFIG; + + if (xf86GetOptValInteger(info->Options, OPTION_DRI, &driLevel) && + (driLevel == 2 || driLevel == 3)) { + from = X_CONFIG; + value = driLevel == 3; + } + } - if (info->use_glamor) { - if (xf86GetOptValBool(info->Options, OPTION_DRI3, &value)) - from = X_CONFIG; + if (value) { + value = amdgpu_sync_init(pScreen) && + amdgpu_present_screen_init(pScreen) && + amdgpu_dri3_screen_init(pScreen); - if (xf86GetOptValInteger(info->Options, OPTION_DRI, &driLevel) && - (driLevel == 2 || driLevel == 3)) { - from = X_CONFIG; - value = driLevel == 3; + if (!value) + from = X_WARNING; } - } - - if (value) { - value = amdgpu_sync_init(pScreen) && - amdgpu_present_screen_init(pScreen) && - amdgpu_dri3_screen_init(pScreen); - if (!value) - from = X_WARNING; + xf86DrvMsg(pScrn->scrnIndex, from, "DRI3 %sabled\n", value ? "en" : "dis"); } - xf86DrvMsg(pScrn->scrnIndex, from, "DRI3 %sabled\n", value ? "en" : "dis"); - pScrn->vtSema = TRUE; xf86SetBackingStore(pScreen); @@ -1801,7 +1825,8 @@ */ /* xf86DiDGAInit(pScreen, info->LinearAddr + pScrn->fbOffset); */ #endif - if (info->shadow_fb == FALSE) { + if (info->shadow_fb == FALSE && + !amdgpu_is_gpu_screen(pScreen)) { /* Init Xv */ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, AMDGPU_LOGLEVEL_DEBUG, "Initializing Xv\n"); @@ -1817,9 +1842,13 @@ } pScrn->pScreen = pScreen; - if (serverGeneration == 1 && bgNoneRoot && info->use_glamor) { - info->CreateWindow = pScreen->CreateWindow; - pScreen->CreateWindow = AMDGPUCreateWindow_oneshot; + if (!amdgpu_is_gpu_screen(pScreen)) { + if (serverGeneration == 1 && bgNoneRoot && info->use_glamor) { + info->CreateWindow = pScreen->CreateWindow; + pScreen->CreateWindow = AMDGPUCreateWindow_oneshot; + } + info->WindowExposures = pScreen->WindowExposures; + pScreen->WindowExposures = AMDGPUWindowExposures_oneshot; } /* Provide SaveScreen & wrap BlockHandler and CloseScreen */ @@ -1828,7 +1857,7 @@ pScreen->CloseScreen = AMDGPUCloseScreen_KMS; pScreen->SaveScreen = AMDGPUSaveScreen_KMS; info->BlockHandler = pScreen->BlockHandler; - pScreen->BlockHandler = AMDGPUBlockHandler_oneshot; + pScreen->BlockHandler = AMDGPUBlockHandler_KMS; info->CreateScreenResources = pScreen->CreateScreenResources; pScreen->CreateScreenResources = AMDGPUCreateScreenResources_KMS; diff -Nru xserver-xorg-video-amdgpu-1.2.0/src/amdgpu_pci_chipset_gen.h xserver-xorg-video-amdgpu-1.3.0/src/amdgpu_pci_chipset_gen.h --- xserver-xorg-video-amdgpu-1.2.0/src/amdgpu_pci_chipset_gen.h 2016-09-16 06:47:43.000000000 +0000 +++ xserver-xorg-video-amdgpu-1.3.0/src/amdgpu_pci_chipset_gen.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,195 +0,0 @@ -/* This file is autogenerated please do not edit */ -static PciChipsets AMDGPUPciChipsets[] = { - { PCI_CHIP_OLAND_6600, PCI_CHIP_OLAND_6600, RES_SHARED_VGA }, - { PCI_CHIP_OLAND_6601, PCI_CHIP_OLAND_6601, RES_SHARED_VGA }, - { PCI_CHIP_OLAND_6602, PCI_CHIP_OLAND_6602, RES_SHARED_VGA }, - { PCI_CHIP_OLAND_6603, PCI_CHIP_OLAND_6603, RES_SHARED_VGA }, - { PCI_CHIP_OLAND_6604, PCI_CHIP_OLAND_6604, RES_SHARED_VGA }, - { PCI_CHIP_OLAND_6605, PCI_CHIP_OLAND_6605, RES_SHARED_VGA }, - { PCI_CHIP_OLAND_6606, PCI_CHIP_OLAND_6606, RES_SHARED_VGA }, - { PCI_CHIP_OLAND_6607, PCI_CHIP_OLAND_6607, RES_SHARED_VGA }, - { PCI_CHIP_OLAND_6608, PCI_CHIP_OLAND_6608, RES_SHARED_VGA }, - { PCI_CHIP_OLAND_6610, PCI_CHIP_OLAND_6610, RES_SHARED_VGA }, - { PCI_CHIP_OLAND_6611, PCI_CHIP_OLAND_6611, RES_SHARED_VGA }, - { PCI_CHIP_OLAND_6613, PCI_CHIP_OLAND_6613, RES_SHARED_VGA }, - { PCI_CHIP_OLAND_6617, PCI_CHIP_OLAND_6617, RES_SHARED_VGA }, - { PCI_CHIP_OLAND_6620, PCI_CHIP_OLAND_6620, RES_SHARED_VGA }, - { PCI_CHIP_OLAND_6621, PCI_CHIP_OLAND_6621, RES_SHARED_VGA }, - { PCI_CHIP_OLAND_6623, PCI_CHIP_OLAND_6623, RES_SHARED_VGA }, - { PCI_CHIP_OLAND_6631, PCI_CHIP_OLAND_6631, RES_SHARED_VGA }, - { PCI_CHIP_HAINAN_6660, PCI_CHIP_HAINAN_6660, RES_SHARED_VGA }, - { PCI_CHIP_HAINAN_6663, PCI_CHIP_HAINAN_6663, RES_SHARED_VGA }, - { PCI_CHIP_HAINAN_6664, PCI_CHIP_HAINAN_6664, RES_SHARED_VGA }, - { PCI_CHIP_HAINAN_6665, PCI_CHIP_HAINAN_6665, RES_SHARED_VGA }, - { PCI_CHIP_HAINAN_6667, PCI_CHIP_HAINAN_6667, RES_SHARED_VGA }, - { PCI_CHIP_HAINAN_666F, PCI_CHIP_HAINAN_666F, RES_SHARED_VGA }, - { PCI_CHIP_TAHITI_6780, PCI_CHIP_TAHITI_6780, RES_SHARED_VGA }, - { PCI_CHIP_TAHITI_6784, PCI_CHIP_TAHITI_6784, RES_SHARED_VGA }, - { PCI_CHIP_TAHITI_6788, PCI_CHIP_TAHITI_6788, RES_SHARED_VGA }, - { PCI_CHIP_TAHITI_678A, PCI_CHIP_TAHITI_678A, RES_SHARED_VGA }, - { PCI_CHIP_TAHITI_6790, PCI_CHIP_TAHITI_6790, RES_SHARED_VGA }, - { PCI_CHIP_TAHITI_6791, PCI_CHIP_TAHITI_6791, RES_SHARED_VGA }, - { PCI_CHIP_TAHITI_6792, PCI_CHIP_TAHITI_6792, RES_SHARED_VGA }, - { PCI_CHIP_TAHITI_6798, PCI_CHIP_TAHITI_6798, RES_SHARED_VGA }, - { PCI_CHIP_TAHITI_6799, PCI_CHIP_TAHITI_6799, RES_SHARED_VGA }, - { PCI_CHIP_TAHITI_679A, PCI_CHIP_TAHITI_679A, RES_SHARED_VGA }, - { PCI_CHIP_TAHITI_679B, PCI_CHIP_TAHITI_679B, RES_SHARED_VGA }, - { PCI_CHIP_TAHITI_679E, PCI_CHIP_TAHITI_679E, RES_SHARED_VGA }, - { PCI_CHIP_TAHITI_679F, PCI_CHIP_TAHITI_679F, RES_SHARED_VGA }, - { PCI_CHIP_PITCAIRN_6800, PCI_CHIP_PITCAIRN_6800, RES_SHARED_VGA }, - { PCI_CHIP_PITCAIRN_6801, PCI_CHIP_PITCAIRN_6801, RES_SHARED_VGA }, - { PCI_CHIP_PITCAIRN_6802, PCI_CHIP_PITCAIRN_6802, RES_SHARED_VGA }, - { PCI_CHIP_PITCAIRN_6806, PCI_CHIP_PITCAIRN_6806, RES_SHARED_VGA }, - { PCI_CHIP_PITCAIRN_6808, PCI_CHIP_PITCAIRN_6808, RES_SHARED_VGA }, - { PCI_CHIP_PITCAIRN_6809, PCI_CHIP_PITCAIRN_6809, RES_SHARED_VGA }, - { PCI_CHIP_PITCAIRN_6810, PCI_CHIP_PITCAIRN_6810, RES_SHARED_VGA }, - { PCI_CHIP_PITCAIRN_6811, PCI_CHIP_PITCAIRN_6811, RES_SHARED_VGA }, - { PCI_CHIP_PITCAIRN_6816, PCI_CHIP_PITCAIRN_6816, RES_SHARED_VGA }, - { PCI_CHIP_PITCAIRN_6817, PCI_CHIP_PITCAIRN_6817, RES_SHARED_VGA }, - { PCI_CHIP_PITCAIRN_6818, PCI_CHIP_PITCAIRN_6818, RES_SHARED_VGA }, - { PCI_CHIP_PITCAIRN_6819, PCI_CHIP_PITCAIRN_6819, RES_SHARED_VGA }, - { PCI_CHIP_VERDE_6820, PCI_CHIP_VERDE_6820, RES_SHARED_VGA }, - { PCI_CHIP_VERDE_6821, PCI_CHIP_VERDE_6821, RES_SHARED_VGA }, - { PCI_CHIP_VERDE_6822, PCI_CHIP_VERDE_6822, RES_SHARED_VGA }, - { PCI_CHIP_VERDE_6823, PCI_CHIP_VERDE_6823, RES_SHARED_VGA }, - { PCI_CHIP_VERDE_6824, PCI_CHIP_VERDE_6824, RES_SHARED_VGA }, - { PCI_CHIP_VERDE_6825, PCI_CHIP_VERDE_6825, RES_SHARED_VGA }, - { PCI_CHIP_VERDE_6826, PCI_CHIP_VERDE_6826, RES_SHARED_VGA }, - { PCI_CHIP_VERDE_6827, PCI_CHIP_VERDE_6827, RES_SHARED_VGA }, - { PCI_CHIP_VERDE_6828, PCI_CHIP_VERDE_6828, RES_SHARED_VGA }, - { PCI_CHIP_VERDE_6829, PCI_CHIP_VERDE_6829, RES_SHARED_VGA }, - { PCI_CHIP_VERDE_682A, PCI_CHIP_VERDE_682A, RES_SHARED_VGA }, - { PCI_CHIP_VERDE_682B, PCI_CHIP_VERDE_682B, RES_SHARED_VGA }, - { PCI_CHIP_VERDE_682C, PCI_CHIP_VERDE_682C, RES_SHARED_VGA }, - { PCI_CHIP_VERDE_682D, PCI_CHIP_VERDE_682D, RES_SHARED_VGA }, - { PCI_CHIP_VERDE_682F, PCI_CHIP_VERDE_682F, RES_SHARED_VGA }, - { PCI_CHIP_VERDE_6830, PCI_CHIP_VERDE_6830, RES_SHARED_VGA }, - { PCI_CHIP_VERDE_6831, PCI_CHIP_VERDE_6831, RES_SHARED_VGA }, - { PCI_CHIP_VERDE_6835, PCI_CHIP_VERDE_6835, RES_SHARED_VGA }, - { PCI_CHIP_VERDE_6837, PCI_CHIP_VERDE_6837, RES_SHARED_VGA }, - { PCI_CHIP_VERDE_6838, PCI_CHIP_VERDE_6838, RES_SHARED_VGA }, - { PCI_CHIP_VERDE_6839, PCI_CHIP_VERDE_6839, RES_SHARED_VGA }, - { PCI_CHIP_VERDE_683B, PCI_CHIP_VERDE_683B, RES_SHARED_VGA }, - { PCI_CHIP_VERDE_683D, PCI_CHIP_VERDE_683D, RES_SHARED_VGA }, - { PCI_CHIP_VERDE_683F, PCI_CHIP_VERDE_683F, RES_SHARED_VGA }, - { PCI_CHIP_PITCAIRN_684C, PCI_CHIP_PITCAIRN_684C, RES_SHARED_VGA }, - { PCI_CHIP_BONAIRE_6640, PCI_CHIP_BONAIRE_6640, RES_SHARED_VGA }, - { PCI_CHIP_BONAIRE_6641, PCI_CHIP_BONAIRE_6641, RES_SHARED_VGA }, - { PCI_CHIP_BONAIRE_6646, PCI_CHIP_BONAIRE_6646, RES_SHARED_VGA }, - { PCI_CHIP_BONAIRE_6647, PCI_CHIP_BONAIRE_6647, RES_SHARED_VGA }, - { PCI_CHIP_BONAIRE_6649, PCI_CHIP_BONAIRE_6649, RES_SHARED_VGA }, - { PCI_CHIP_BONAIRE_6650, PCI_CHIP_BONAIRE_6650, RES_SHARED_VGA }, - { PCI_CHIP_BONAIRE_6651, PCI_CHIP_BONAIRE_6651, RES_SHARED_VGA }, - { PCI_CHIP_BONAIRE_6658, PCI_CHIP_BONAIRE_6658, RES_SHARED_VGA }, - { PCI_CHIP_BONAIRE_665C, PCI_CHIP_BONAIRE_665C, RES_SHARED_VGA }, - { PCI_CHIP_BONAIRE_665D, PCI_CHIP_BONAIRE_665D, RES_SHARED_VGA }, - { PCI_CHIP_BONAIRE_665F, PCI_CHIP_BONAIRE_665F, RES_SHARED_VGA }, - { PCI_CHIP_KABINI_9830, PCI_CHIP_KABINI_9830, RES_SHARED_VGA }, - { PCI_CHIP_KABINI_9831, PCI_CHIP_KABINI_9831, RES_SHARED_VGA }, - { PCI_CHIP_KABINI_9832, PCI_CHIP_KABINI_9832, RES_SHARED_VGA }, - { PCI_CHIP_KABINI_9833, PCI_CHIP_KABINI_9833, RES_SHARED_VGA }, - { PCI_CHIP_KABINI_9834, PCI_CHIP_KABINI_9834, RES_SHARED_VGA }, - { PCI_CHIP_KABINI_9835, PCI_CHIP_KABINI_9835, RES_SHARED_VGA }, - { PCI_CHIP_KABINI_9836, PCI_CHIP_KABINI_9836, RES_SHARED_VGA }, - { PCI_CHIP_KABINI_9837, PCI_CHIP_KABINI_9837, RES_SHARED_VGA }, - { PCI_CHIP_KABINI_9838, PCI_CHIP_KABINI_9838, RES_SHARED_VGA }, - { PCI_CHIP_KABINI_9839, PCI_CHIP_KABINI_9839, RES_SHARED_VGA }, - { PCI_CHIP_KABINI_983A, PCI_CHIP_KABINI_983A, RES_SHARED_VGA }, - { PCI_CHIP_KABINI_983B, PCI_CHIP_KABINI_983B, RES_SHARED_VGA }, - { PCI_CHIP_KABINI_983C, PCI_CHIP_KABINI_983C, RES_SHARED_VGA }, - { PCI_CHIP_KABINI_983D, PCI_CHIP_KABINI_983D, RES_SHARED_VGA }, - { PCI_CHIP_KABINI_983E, PCI_CHIP_KABINI_983E, RES_SHARED_VGA }, - { PCI_CHIP_KABINI_983F, PCI_CHIP_KABINI_983F, RES_SHARED_VGA }, - { PCI_CHIP_MULLINS_9850, PCI_CHIP_MULLINS_9850, RES_SHARED_VGA }, - { PCI_CHIP_MULLINS_9851, PCI_CHIP_MULLINS_9851, RES_SHARED_VGA }, - { PCI_CHIP_MULLINS_9852, PCI_CHIP_MULLINS_9852, RES_SHARED_VGA }, - { PCI_CHIP_MULLINS_9853, PCI_CHIP_MULLINS_9853, RES_SHARED_VGA }, - { PCI_CHIP_MULLINS_9854, PCI_CHIP_MULLINS_9854, RES_SHARED_VGA }, - { PCI_CHIP_MULLINS_9855, PCI_CHIP_MULLINS_9855, RES_SHARED_VGA }, - { PCI_CHIP_MULLINS_9856, PCI_CHIP_MULLINS_9856, RES_SHARED_VGA }, - { PCI_CHIP_MULLINS_9857, PCI_CHIP_MULLINS_9857, RES_SHARED_VGA }, - { PCI_CHIP_MULLINS_9858, PCI_CHIP_MULLINS_9858, RES_SHARED_VGA }, - { PCI_CHIP_MULLINS_9859, PCI_CHIP_MULLINS_9859, RES_SHARED_VGA }, - { PCI_CHIP_MULLINS_985A, PCI_CHIP_MULLINS_985A, RES_SHARED_VGA }, - { PCI_CHIP_MULLINS_985B, PCI_CHIP_MULLINS_985B, RES_SHARED_VGA }, - { PCI_CHIP_MULLINS_985C, PCI_CHIP_MULLINS_985C, RES_SHARED_VGA }, - { PCI_CHIP_MULLINS_985D, PCI_CHIP_MULLINS_985D, RES_SHARED_VGA }, - { PCI_CHIP_MULLINS_985E, PCI_CHIP_MULLINS_985E, RES_SHARED_VGA }, - { PCI_CHIP_MULLINS_985F, PCI_CHIP_MULLINS_985F, RES_SHARED_VGA }, - { PCI_CHIP_KAVERI_1304, PCI_CHIP_KAVERI_1304, RES_SHARED_VGA }, - { PCI_CHIP_KAVERI_1305, PCI_CHIP_KAVERI_1305, RES_SHARED_VGA }, - { PCI_CHIP_KAVERI_1306, PCI_CHIP_KAVERI_1306, RES_SHARED_VGA }, - { PCI_CHIP_KAVERI_1307, PCI_CHIP_KAVERI_1307, RES_SHARED_VGA }, - { PCI_CHIP_KAVERI_1309, PCI_CHIP_KAVERI_1309, RES_SHARED_VGA }, - { PCI_CHIP_KAVERI_130A, PCI_CHIP_KAVERI_130A, RES_SHARED_VGA }, - { PCI_CHIP_KAVERI_130B, PCI_CHIP_KAVERI_130B, RES_SHARED_VGA }, - { PCI_CHIP_KAVERI_130C, PCI_CHIP_KAVERI_130C, RES_SHARED_VGA }, - { PCI_CHIP_KAVERI_130D, PCI_CHIP_KAVERI_130D, RES_SHARED_VGA }, - { PCI_CHIP_KAVERI_130E, PCI_CHIP_KAVERI_130E, RES_SHARED_VGA }, - { PCI_CHIP_KAVERI_130F, PCI_CHIP_KAVERI_130F, RES_SHARED_VGA }, - { PCI_CHIP_KAVERI_1310, PCI_CHIP_KAVERI_1310, RES_SHARED_VGA }, - { PCI_CHIP_KAVERI_1311, PCI_CHIP_KAVERI_1311, RES_SHARED_VGA }, - { PCI_CHIP_KAVERI_1312, PCI_CHIP_KAVERI_1312, RES_SHARED_VGA }, - { PCI_CHIP_KAVERI_1313, PCI_CHIP_KAVERI_1313, RES_SHARED_VGA }, - { PCI_CHIP_KAVERI_1315, PCI_CHIP_KAVERI_1315, RES_SHARED_VGA }, - { PCI_CHIP_KAVERI_1316, PCI_CHIP_KAVERI_1316, RES_SHARED_VGA }, - { PCI_CHIP_KAVERI_1317, PCI_CHIP_KAVERI_1317, RES_SHARED_VGA }, - { PCI_CHIP_KAVERI_1318, PCI_CHIP_KAVERI_1318, RES_SHARED_VGA }, - { PCI_CHIP_KAVERI_131B, PCI_CHIP_KAVERI_131B, RES_SHARED_VGA }, - { PCI_CHIP_KAVERI_131C, PCI_CHIP_KAVERI_131C, RES_SHARED_VGA }, - { PCI_CHIP_KAVERI_131D, PCI_CHIP_KAVERI_131D, RES_SHARED_VGA }, - { PCI_CHIP_HAWAII_67A0, PCI_CHIP_HAWAII_67A0, RES_SHARED_VGA }, - { PCI_CHIP_HAWAII_67A1, PCI_CHIP_HAWAII_67A1, RES_SHARED_VGA }, - { PCI_CHIP_HAWAII_67A2, PCI_CHIP_HAWAII_67A2, RES_SHARED_VGA }, - { PCI_CHIP_HAWAII_67A8, PCI_CHIP_HAWAII_67A8, RES_SHARED_VGA }, - { PCI_CHIP_HAWAII_67A9, PCI_CHIP_HAWAII_67A9, RES_SHARED_VGA }, - { PCI_CHIP_HAWAII_67AA, PCI_CHIP_HAWAII_67AA, RES_SHARED_VGA }, - { PCI_CHIP_HAWAII_67B0, PCI_CHIP_HAWAII_67B0, RES_SHARED_VGA }, - { PCI_CHIP_HAWAII_67B1, PCI_CHIP_HAWAII_67B1, RES_SHARED_VGA }, - { PCI_CHIP_HAWAII_67B8, PCI_CHIP_HAWAII_67B8, RES_SHARED_VGA }, - { PCI_CHIP_HAWAII_67B9, PCI_CHIP_HAWAII_67B9, RES_SHARED_VGA }, - { PCI_CHIP_HAWAII_67BA, PCI_CHIP_HAWAII_67BA, RES_SHARED_VGA }, - { PCI_CHIP_HAWAII_67BE, PCI_CHIP_HAWAII_67BE, RES_SHARED_VGA }, - { PCI_CHIP_TOPAZ_6900, PCI_CHIP_TOPAZ_6900, RES_SHARED_VGA }, - { PCI_CHIP_TOPAZ_6901, PCI_CHIP_TOPAZ_6901, RES_SHARED_VGA }, - { PCI_CHIP_TOPAZ_6902, PCI_CHIP_TOPAZ_6902, RES_SHARED_VGA }, - { PCI_CHIP_TOPAZ_6903, PCI_CHIP_TOPAZ_6903, RES_SHARED_VGA }, - { PCI_CHIP_TOPAZ_6907, PCI_CHIP_TOPAZ_6907, RES_SHARED_VGA }, - { PCI_CHIP_TONGA_6920, PCI_CHIP_TONGA_6920, RES_SHARED_VGA }, - { PCI_CHIP_TONGA_6921, PCI_CHIP_TONGA_6921, RES_SHARED_VGA }, - { PCI_CHIP_TONGA_6928, PCI_CHIP_TONGA_6928, RES_SHARED_VGA }, - { PCI_CHIP_TONGA_6929, PCI_CHIP_TONGA_6929, RES_SHARED_VGA }, - { PCI_CHIP_TONGA_692B, PCI_CHIP_TONGA_692B, RES_SHARED_VGA }, - { PCI_CHIP_TONGA_692F, PCI_CHIP_TONGA_692F, RES_SHARED_VGA }, - { PCI_CHIP_TONGA_6930, PCI_CHIP_TONGA_6930, RES_SHARED_VGA }, - { PCI_CHIP_TONGA_6938, PCI_CHIP_TONGA_6938, RES_SHARED_VGA }, - { PCI_CHIP_TONGA_6939, PCI_CHIP_TONGA_6939, RES_SHARED_VGA }, - { PCI_CHIP_CARRIZO_9870, PCI_CHIP_CARRIZO_9870, RES_SHARED_VGA }, - { PCI_CHIP_CARRIZO_9874, PCI_CHIP_CARRIZO_9874, RES_SHARED_VGA }, - { PCI_CHIP_CARRIZO_9875, PCI_CHIP_CARRIZO_9875, RES_SHARED_VGA }, - { PCI_CHIP_CARRIZO_9876, PCI_CHIP_CARRIZO_9876, RES_SHARED_VGA }, - { PCI_CHIP_CARRIZO_9877, PCI_CHIP_CARRIZO_9877, RES_SHARED_VGA }, - { PCI_CHIP_FIJI_7300, PCI_CHIP_FIJI_7300, RES_SHARED_VGA }, - { PCI_CHIP_STONEY_98E4, PCI_CHIP_STONEY_98E4, RES_SHARED_VGA }, - { PCI_CHIP_POLARIS11_67E0, PCI_CHIP_POLARIS11_67E0, RES_SHARED_VGA }, - { PCI_CHIP_POLARIS11_67E3, PCI_CHIP_POLARIS11_67E3, RES_SHARED_VGA }, - { PCI_CHIP_POLARIS11_67E8, PCI_CHIP_POLARIS11_67E8, RES_SHARED_VGA }, - { PCI_CHIP_POLARIS11_67EB, PCI_CHIP_POLARIS11_67EB, RES_SHARED_VGA }, - { PCI_CHIP_POLARIS11_67EF, PCI_CHIP_POLARIS11_67EF, RES_SHARED_VGA }, - { PCI_CHIP_POLARIS11_67FF, PCI_CHIP_POLARIS11_67FF, RES_SHARED_VGA }, - { PCI_CHIP_POLARIS11_67E1, PCI_CHIP_POLARIS11_67E1, RES_SHARED_VGA }, - { PCI_CHIP_POLARIS11_67E7, PCI_CHIP_POLARIS11_67E7, RES_SHARED_VGA }, - { PCI_CHIP_POLARIS11_67E9, PCI_CHIP_POLARIS11_67E9, RES_SHARED_VGA }, - { PCI_CHIP_POLARIS10_67C0, PCI_CHIP_POLARIS10_67C0, RES_SHARED_VGA }, - { PCI_CHIP_POLARIS10_67C1, PCI_CHIP_POLARIS10_67C1, RES_SHARED_VGA }, - { PCI_CHIP_POLARIS10_67C2, PCI_CHIP_POLARIS10_67C2, RES_SHARED_VGA }, - { PCI_CHIP_POLARIS10_67C4, PCI_CHIP_POLARIS10_67C4, RES_SHARED_VGA }, - { PCI_CHIP_POLARIS10_67C7, PCI_CHIP_POLARIS10_67C7, RES_SHARED_VGA }, - { PCI_CHIP_POLARIS10_67DF, PCI_CHIP_POLARIS10_67DF, RES_SHARED_VGA }, - { PCI_CHIP_POLARIS10_67C8, PCI_CHIP_POLARIS10_67C8, RES_SHARED_VGA }, - { PCI_CHIP_POLARIS10_67C9, PCI_CHIP_POLARIS10_67C9, RES_SHARED_VGA }, - { PCI_CHIP_POLARIS10_67CA, PCI_CHIP_POLARIS10_67CA, RES_SHARED_VGA }, - { PCI_CHIP_POLARIS10_67CC, PCI_CHIP_POLARIS10_67CC, RES_SHARED_VGA }, - { PCI_CHIP_POLARIS10_67CF, PCI_CHIP_POLARIS10_67CF, RES_SHARED_VGA }, - { -1, -1, RES_UNDEFINED } -}; diff -Nru xserver-xorg-video-amdgpu-1.2.0/src/amdgpu_pci_device_match_gen.h xserver-xorg-video-amdgpu-1.3.0/src/amdgpu_pci_device_match_gen.h --- xserver-xorg-video-amdgpu-1.2.0/src/amdgpu_pci_device_match_gen.h 2016-09-16 06:47:43.000000000 +0000 +++ xserver-xorg-video-amdgpu-1.3.0/src/amdgpu_pci_device_match_gen.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,195 +0,0 @@ -/* This file is autogenerated please do not edit */ -static const struct pci_id_match amdgpu_device_match[] = { - ATI_DEVICE_MATCH( PCI_CHIP_OLAND_6600, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_OLAND_6601, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_OLAND_6602, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_OLAND_6603, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_OLAND_6604, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_OLAND_6605, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_OLAND_6606, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_OLAND_6607, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_OLAND_6608, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_OLAND_6610, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_OLAND_6611, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_OLAND_6613, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_OLAND_6617, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_OLAND_6620, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_OLAND_6621, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_OLAND_6623, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_OLAND_6631, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_HAINAN_6660, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_HAINAN_6663, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_HAINAN_6664, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_HAINAN_6665, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_HAINAN_6667, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_HAINAN_666F, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_TAHITI_6780, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_TAHITI_6784, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_TAHITI_6788, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_TAHITI_678A, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_TAHITI_6790, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_TAHITI_6791, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_TAHITI_6792, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_TAHITI_6798, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_TAHITI_6799, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_TAHITI_679A, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_TAHITI_679B, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_TAHITI_679E, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_TAHITI_679F, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_PITCAIRN_6800, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_PITCAIRN_6801, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_PITCAIRN_6802, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_PITCAIRN_6806, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_PITCAIRN_6808, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_PITCAIRN_6809, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_PITCAIRN_6810, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_PITCAIRN_6811, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_PITCAIRN_6816, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_PITCAIRN_6817, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_PITCAIRN_6818, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_PITCAIRN_6819, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_VERDE_6820, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_VERDE_6821, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_VERDE_6822, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_VERDE_6823, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_VERDE_6824, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_VERDE_6825, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_VERDE_6826, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_VERDE_6827, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_VERDE_6828, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_VERDE_6829, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_VERDE_682A, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_VERDE_682B, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_VERDE_682C, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_VERDE_682D, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_VERDE_682F, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_VERDE_6830, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_VERDE_6831, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_VERDE_6835, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_VERDE_6837, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_VERDE_6838, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_VERDE_6839, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_VERDE_683B, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_VERDE_683D, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_VERDE_683F, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_PITCAIRN_684C, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_BONAIRE_6640, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_BONAIRE_6641, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_BONAIRE_6646, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_BONAIRE_6647, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_BONAIRE_6649, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_BONAIRE_6650, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_BONAIRE_6651, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_BONAIRE_6658, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_BONAIRE_665C, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_BONAIRE_665D, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_BONAIRE_665F, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_KABINI_9830, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_KABINI_9831, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_KABINI_9832, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_KABINI_9833, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_KABINI_9834, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_KABINI_9835, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_KABINI_9836, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_KABINI_9837, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_KABINI_9838, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_KABINI_9839, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_KABINI_983A, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_KABINI_983B, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_KABINI_983C, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_KABINI_983D, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_KABINI_983E, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_KABINI_983F, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_MULLINS_9850, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_MULLINS_9851, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_MULLINS_9852, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_MULLINS_9853, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_MULLINS_9854, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_MULLINS_9855, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_MULLINS_9856, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_MULLINS_9857, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_MULLINS_9858, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_MULLINS_9859, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_MULLINS_985A, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_MULLINS_985B, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_MULLINS_985C, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_MULLINS_985D, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_MULLINS_985E, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_MULLINS_985F, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_1304, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_1305, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_1306, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_1307, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_1309, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_130A, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_130B, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_130C, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_130D, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_130E, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_130F, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_1310, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_1311, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_1312, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_1313, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_1315, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_1316, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_1317, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_1318, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_131B, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_131C, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_131D, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_HAWAII_67A0, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_HAWAII_67A1, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_HAWAII_67A2, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_HAWAII_67A8, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_HAWAII_67A9, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_HAWAII_67AA, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_HAWAII_67B0, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_HAWAII_67B1, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_HAWAII_67B8, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_HAWAII_67B9, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_HAWAII_67BA, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_HAWAII_67BE, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_TOPAZ_6900, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_TOPAZ_6901, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_TOPAZ_6902, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_TOPAZ_6903, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_TOPAZ_6907, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_TONGA_6920, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_TONGA_6921, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_TONGA_6928, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_TONGA_6929, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_TONGA_692B, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_TONGA_692F, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_TONGA_6930, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_TONGA_6938, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_TONGA_6939, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_CARRIZO_9870, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_CARRIZO_9874, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_CARRIZO_9875, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_CARRIZO_9876, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_CARRIZO_9877, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_FIJI_7300, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_STONEY_98E4, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_POLARIS11_67E0, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_POLARIS11_67E3, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_POLARIS11_67E8, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_POLARIS11_67EB, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_POLARIS11_67EF, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_POLARIS11_67FF, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_POLARIS11_67E1, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_POLARIS11_67E7, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_POLARIS11_67E9, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_POLARIS10_67C0, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_POLARIS10_67C1, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_POLARIS10_67C2, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_POLARIS10_67C4, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_POLARIS10_67C7, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_POLARIS10_67DF, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_POLARIS10_67C8, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_POLARIS10_67C9, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_POLARIS10_67CA, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_POLARIS10_67CC, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_POLARIS10_67CF, 0 ), - { 0, 0, 0 } -}; diff -Nru xserver-xorg-video-amdgpu-1.2.0/src/amdgpu_present.c xserver-xorg-video-amdgpu-1.3.0/src/amdgpu_present.c --- xserver-xorg-video-amdgpu-1.2.0/src/amdgpu_present.c 2016-11-17 06:07:48.000000000 +0000 +++ xserver-xorg-video-amdgpu-1.3.0/src/amdgpu_present.c 2017-03-16 08:32:47.000000000 +0000 @@ -48,6 +48,8 @@ #include "present.h" +static present_screen_info_rec amdgpu_present_screen_info; + struct amdgpu_present_vblank_event { uint64_t event_id; Bool unflip; @@ -325,11 +327,14 @@ event->event_id = event_id; + amdgpu_glamor_flush(scrn); + ret = amdgpu_do_pageflip(scrn, AMDGPU_DRM_QUEUE_CLIENT_DEFAULT, pixmap, event_id, event, crtc_id, amdgpu_present_flip_event, amdgpu_present_flip_abort, - sync_flip ? FLIP_VSYNC : FLIP_ASYNC); + sync_flip ? FLIP_VSYNC : FLIP_ASYNC, + target_msc); if (!ret) xf86DrvMsg(scrn->scrnIndex, X_ERROR, "present flip failed\n"); else @@ -350,6 +355,10 @@ xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR(scrn); struct amdgpu_present_vblank_event *event; PixmapPtr pixmap = screen->GetScreenPixmap(screen); + enum drmmode_flip_sync flip_sync = + (amdgpu_present_screen_info.capabilities & PresentCapabilityAsync) ? + FLIP_ASYNC : FLIP_VSYNC; + int old_fb_id; int i; if (!amdgpu_present_check_unflip(scrn)) @@ -364,18 +373,20 @@ event->event_id = event_id; event->unflip = TRUE; + amdgpu_glamor_flush(scrn); if (amdgpu_do_pageflip(scrn, AMDGPU_DRM_QUEUE_CLIENT_DEFAULT, pixmap, event_id, event, -1, amdgpu_present_flip_event, - amdgpu_present_flip_abort, FLIP_VSYNC)) + amdgpu_present_flip_abort, flip_sync, 0)) return; modeset: /* info->drmmode.fb_id still points to the FB for the last flipped BO. * Clear it, drmmode_set_mode_major will re-create it */ - drmModeRmFB(pAMDGPUEnt->fd, info->drmmode.fb_id); + old_fb_id = info->drmmode.fb_id; info->drmmode.fb_id = 0; + amdgpu_glamor_finish(scrn); for (i = 0; i < config->num_crtc; i++) { xf86CrtcPtr crtc = config->crtc[i]; drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private; @@ -390,6 +401,7 @@ drmmode_crtc->need_modeset = TRUE; } + drmModeRmFB(pAMDGPUEnt->fd, old_fb_id); present_event_notify(event_id, 0, 0); info->drmmode.present_flipping = FALSE; } diff -Nru xserver-xorg-video-amdgpu-1.2.0/src/amdgpu_probe.c xserver-xorg-video-amdgpu-1.3.0/src/amdgpu_probe.c --- xserver-xorg-video-amdgpu-1.2.0/src/amdgpu_probe.c 2016-11-17 06:07:48.000000000 +0000 +++ xserver-xorg-video-amdgpu-1.3.0/src/amdgpu_probe.c 2017-03-16 08:32:47.000000000 +0000 @@ -44,7 +44,6 @@ #include "amdgpu_probe.h" #include "amdgpu_version.h" #include "amdgpu_drv.h" -#include "amdpciids.h" #include "xf86.h" @@ -59,12 +58,6 @@ #include #endif -#include "amdgpu_chipset_gen.h" - -#include "amdgpu_pci_chipset_gen.h" - -#include "amdgpu_pci_device_match_gen.h" - _X_EXPORT int gAMDGPUEntityIndex = -1; /* Return the options for supported chipset 'n'; NULL otherwise */ @@ -73,11 +66,15 @@ return AMDGPUOptionsWeak(); } +static SymTabRec AMDGPUAny[] = { + { 0, "All GPUs supported by the amdgpu kernel driver" }, + { -1, NULL } +}; + /* Return the string name for supported chipset 'n'; NULL otherwise. */ static void AMDGPUIdentify(int flags) { - xf86PrintChipsets(AMDGPU_NAME, - "Driver for AMD Radeon chipsets", AMDGPUUniqueChipsets); + xf86PrintChipsets(AMDGPU_NAME, "Driver for AMD Radeon", AMDGPUAny); } static char *amdgpu_bus_id(ScrnInfoPtr pScrn, struct pci_device *dev) @@ -137,6 +134,16 @@ return fd; } +void amdgpu_kernel_close_fd(AMDGPUEntPtr pAMDGPUEnt) +{ +#ifdef XF86_PDEV_SERVER_FD + if (!(pAMDGPUEnt->platform_dev && + pAMDGPUEnt->platform_dev->flags & XF86_PDEV_SERVER_FD)) +#endif + drmClose(pAMDGPUEnt->fd); + pAMDGPUEnt->fd = -1; +} + static Bool amdgpu_open_drm_master(ScrnInfoPtr pScrn, AMDGPUEntPtr pAMDGPUEnt, char *busid) { @@ -159,7 +166,7 @@ if (err != 0) { xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "[drm] failed to set drm interface version.\n"); - drmClose(pAMDGPUEnt->fd); + amdgpu_kernel_close_fd(pAMDGPUEnt); return FALSE; } @@ -174,7 +181,7 @@ DevUnion *pPriv; AMDGPUEntPtr pAMDGPUEnt; - pScrn = xf86ConfigPciEntity(pScrn, 0, entity_num, AMDGPUPciChipsets, + pScrn = xf86ConfigPciEntity(pScrn, 0, entity_num, NULL, NULL, NULL, NULL, NULL, NULL); if (!pScrn) @@ -247,7 +254,7 @@ return TRUE; error_amdgpu: - drmClose(pAMDGPUEnt->fd); + amdgpu_kernel_close_fd(pAMDGPUEnt); error_fd: free(pPriv->ptr); error: @@ -342,6 +349,7 @@ pPriv->ptr = xnfcalloc(sizeof(AMDGPUEntRec), 1); pAMDGPUEnt = pPriv->ptr; + pAMDGPUEnt->platform_dev = dev; pAMDGPUEnt->fd = amdgpu_kernel_open_fd(pScrn, busid, dev); if (pAMDGPUEnt->fd < 0) goto error_fd; @@ -360,7 +368,6 @@ pAMDGPUEnt = pPriv->ptr; pAMDGPUEnt->fd_ref++; } - pAMDGPUEnt->platform_dev = dev; xf86SetEntityInstanceForScreen(pScrn, pEnt->index, xf86GetNumEntityInstances(pEnt-> @@ -372,7 +379,7 @@ return TRUE; error_amdgpu: - drmClose(pAMDGPUEnt->fd); + amdgpu_kernel_close_fd(pAMDGPUEnt); error_fd: free(pPriv->ptr); error: @@ -381,6 +388,11 @@ } #endif +static const struct pci_id_match amdgpu_device_match[] = { + {0x1002, PCI_MATCH_ANY, PCI_MATCH_ANY, PCI_MATCH_ANY, 0, 0, 0}, + {0, 0, 0}, +}; + _X_EXPORT DriverRec AMDGPU = { AMDGPU_VERSION_CURRENT, AMDGPU_DRIVER_NAME, diff -Nru xserver-xorg-video-amdgpu-1.2.0/src/amdgpu_probe.h xserver-xorg-video-amdgpu-1.3.0/src/amdgpu_probe.h --- xserver-xorg-video-amdgpu-1.2.0/src/amdgpu_probe.h 2016-11-17 06:07:48.000000000 +0000 +++ xserver-xorg-video-amdgpu-1.3.0/src/amdgpu_probe.h 2017-03-16 08:32:47.000000000 +0000 @@ -54,37 +54,9 @@ extern DriverRec AMDGPU; -typedef enum { - CHIP_FAMILY_UNKNOW, - CHIP_FAMILY_LEGACY, - CHIP_FAMILY_AMDGPU, - CHIP_FAMILY_TAHITI, - CHIP_FAMILY_PITCAIRN, - CHIP_FAMILY_VERDE, - CHIP_FAMILY_OLAND, - CHIP_FAMILY_HAINAN, - CHIP_FAMILY_BONAIRE, - CHIP_FAMILY_KAVERI, - CHIP_FAMILY_KABINI, - CHIP_FAMILY_HAWAII, - CHIP_FAMILY_MULLINS, - CHIP_FAMILY_TOPAZ, - CHIP_FAMILY_TONGA, - CHIP_FAMILY_CARRIZO, - CHIP_FAMILY_FIJI, - CHIP_FAMILY_STONEY, - CHIP_FAMILY_POLARIS10, - CHIP_FAMILY_POLARIS11, - CHIP_FAMILY_LAST -} AMDGPUChipFamily; - -typedef struct { - uint32_t pci_device_id; - AMDGPUChipFamily chip_family; -} AMDGPUCardInfo; - typedef struct { Bool HasCRTC2; /* All cards except original Radeon */ + Bool has_page_flip_target; amdgpu_device_handle pDev; @@ -96,8 +68,11 @@ ScrnInfoPtr primary_scrn; ScrnInfoPtr secondary_scrn; struct xf86_platform_device *platform_dev; + char *render_node; } AMDGPUEntRec, *AMDGPUEntPtr; +extern void amdgpu_kernel_close_fd(AMDGPUEntPtr pAMDGPUEnt); + extern const OptionInfoRec *AMDGPUOptionsWeak(void); extern Bool AMDGPUPreInit_KMS(ScrnInfoPtr, int); diff -Nru xserver-xorg-video-amdgpu-1.2.0/src/amdpciids.h xserver-xorg-video-amdgpu-1.3.0/src/amdpciids.h --- xserver-xorg-video-amdgpu-1.2.0/src/amdpciids.h 2015-04-26 01:41:53.000000000 +0000 +++ xserver-xorg-video-amdgpu-1.3.0/src/amdpciids.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,39 +0,0 @@ -/* - * Copyright 2014 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * -*/ - - -#ifndef _AMDPCIIDS_H -#define _AMDPCIIDS_H - -#define PCI_VENDOR_ATI 0x1002 - -#include "ati_pciids_gen.h" - -typedef struct pci_device *pciVideoPtr; - -#define PCI_DEV_DEVICE_ID(_pcidev) ((_pcidev)->device_id) - -#define ATI_DEVICE_MATCH(d, i) \ - { PCI_VENDOR_ATI, (d), PCI_MATCH_ANY, PCI_MATCH_ANY, 0, 0, (i) } - -#endif /* AMDPCIIDS_H */ diff -Nru xserver-xorg-video-amdgpu-1.2.0/src/ati_pciids_gen.h xserver-xorg-video-amdgpu-1.3.0/src/ati_pciids_gen.h --- xserver-xorg-video-amdgpu-1.2.0/src/ati_pciids_gen.h 2016-09-16 06:47:43.000000000 +0000 +++ xserver-xorg-video-amdgpu-1.3.0/src/ati_pciids_gen.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,191 +0,0 @@ -#define PCI_CHIP_OLAND_6600 0x6600 -#define PCI_CHIP_OLAND_6601 0x6601 -#define PCI_CHIP_OLAND_6602 0x6602 -#define PCI_CHIP_OLAND_6603 0x6603 -#define PCI_CHIP_OLAND_6604 0x6604 -#define PCI_CHIP_OLAND_6605 0x6605 -#define PCI_CHIP_OLAND_6606 0x6606 -#define PCI_CHIP_OLAND_6607 0x6607 -#define PCI_CHIP_OLAND_6608 0x6608 -#define PCI_CHIP_OLAND_6610 0x6610 -#define PCI_CHIP_OLAND_6611 0x6611 -#define PCI_CHIP_OLAND_6613 0x6613 -#define PCI_CHIP_OLAND_6617 0x6617 -#define PCI_CHIP_OLAND_6620 0x6620 -#define PCI_CHIP_OLAND_6621 0x6621 -#define PCI_CHIP_OLAND_6623 0x6623 -#define PCI_CHIP_OLAND_6631 0x6631 -#define PCI_CHIP_HAINAN_6660 0x6660 -#define PCI_CHIP_HAINAN_6663 0x6663 -#define PCI_CHIP_HAINAN_6664 0x6664 -#define PCI_CHIP_HAINAN_6665 0x6665 -#define PCI_CHIP_HAINAN_6667 0x6667 -#define PCI_CHIP_HAINAN_666F 0x666F -#define PCI_CHIP_TAHITI_6780 0x6780 -#define PCI_CHIP_TAHITI_6784 0x6784 -#define PCI_CHIP_TAHITI_6788 0x6788 -#define PCI_CHIP_TAHITI_678A 0x678A -#define PCI_CHIP_TAHITI_6790 0x6790 -#define PCI_CHIP_TAHITI_6791 0x6791 -#define PCI_CHIP_TAHITI_6792 0x6792 -#define PCI_CHIP_TAHITI_6798 0x6798 -#define PCI_CHIP_TAHITI_6799 0x6799 -#define PCI_CHIP_TAHITI_679A 0x679A -#define PCI_CHIP_TAHITI_679B 0x679B -#define PCI_CHIP_TAHITI_679E 0x679E -#define PCI_CHIP_TAHITI_679F 0x679F -#define PCI_CHIP_PITCAIRN_6800 0x6800 -#define PCI_CHIP_PITCAIRN_6801 0x6801 -#define PCI_CHIP_PITCAIRN_6802 0x6802 -#define PCI_CHIP_PITCAIRN_6806 0x6806 -#define PCI_CHIP_PITCAIRN_6808 0x6808 -#define PCI_CHIP_PITCAIRN_6809 0x6809 -#define PCI_CHIP_PITCAIRN_6810 0x6810 -#define PCI_CHIP_PITCAIRN_6811 0x6811 -#define PCI_CHIP_PITCAIRN_6816 0x6816 -#define PCI_CHIP_PITCAIRN_6817 0x6817 -#define PCI_CHIP_PITCAIRN_6818 0x6818 -#define PCI_CHIP_PITCAIRN_6819 0x6819 -#define PCI_CHIP_VERDE_6820 0x6820 -#define PCI_CHIP_VERDE_6821 0x6821 -#define PCI_CHIP_VERDE_6822 0x6822 -#define PCI_CHIP_VERDE_6823 0x6823 -#define PCI_CHIP_VERDE_6824 0x6824 -#define PCI_CHIP_VERDE_6825 0x6825 -#define PCI_CHIP_VERDE_6826 0x6826 -#define PCI_CHIP_VERDE_6827 0x6827 -#define PCI_CHIP_VERDE_6828 0x6828 -#define PCI_CHIP_VERDE_6829 0x6829 -#define PCI_CHIP_VERDE_682A 0x682A -#define PCI_CHIP_VERDE_682B 0x682B -#define PCI_CHIP_VERDE_682C 0x682C -#define PCI_CHIP_VERDE_682D 0x682D -#define PCI_CHIP_VERDE_682F 0x682F -#define PCI_CHIP_VERDE_6830 0x6830 -#define PCI_CHIP_VERDE_6831 0x6831 -#define PCI_CHIP_VERDE_6835 0x6835 -#define PCI_CHIP_VERDE_6837 0x6837 -#define PCI_CHIP_VERDE_6838 0x6838 -#define PCI_CHIP_VERDE_6839 0x6839 -#define PCI_CHIP_VERDE_683B 0x683B -#define PCI_CHIP_VERDE_683D 0x683D -#define PCI_CHIP_VERDE_683F 0x683F -#define PCI_CHIP_PITCAIRN_684C 0x684C -#define PCI_CHIP_BONAIRE_6640 0x6640 -#define PCI_CHIP_BONAIRE_6641 0x6641 -#define PCI_CHIP_BONAIRE_6646 0x6646 -#define PCI_CHIP_BONAIRE_6647 0x6647 -#define PCI_CHIP_BONAIRE_6649 0x6649 -#define PCI_CHIP_BONAIRE_6650 0x6650 -#define PCI_CHIP_BONAIRE_6651 0x6651 -#define PCI_CHIP_BONAIRE_6658 0x6658 -#define PCI_CHIP_BONAIRE_665C 0x665C -#define PCI_CHIP_BONAIRE_665D 0x665D -#define PCI_CHIP_BONAIRE_665F 0x665F -#define PCI_CHIP_KABINI_9830 0x9830 -#define PCI_CHIP_KABINI_9831 0x9831 -#define PCI_CHIP_KABINI_9832 0x9832 -#define PCI_CHIP_KABINI_9833 0x9833 -#define PCI_CHIP_KABINI_9834 0x9834 -#define PCI_CHIP_KABINI_9835 0x9835 -#define PCI_CHIP_KABINI_9836 0x9836 -#define PCI_CHIP_KABINI_9837 0x9837 -#define PCI_CHIP_KABINI_9838 0x9838 -#define PCI_CHIP_KABINI_9839 0x9839 -#define PCI_CHIP_KABINI_983A 0x983A -#define PCI_CHIP_KABINI_983B 0x983B -#define PCI_CHIP_KABINI_983C 0x983C -#define PCI_CHIP_KABINI_983D 0x983D -#define PCI_CHIP_KABINI_983E 0x983E -#define PCI_CHIP_KABINI_983F 0x983F -#define PCI_CHIP_MULLINS_9850 0x9850 -#define PCI_CHIP_MULLINS_9851 0x9851 -#define PCI_CHIP_MULLINS_9852 0x9852 -#define PCI_CHIP_MULLINS_9853 0x9853 -#define PCI_CHIP_MULLINS_9854 0x9854 -#define PCI_CHIP_MULLINS_9855 0x9855 -#define PCI_CHIP_MULLINS_9856 0x9856 -#define PCI_CHIP_MULLINS_9857 0x9857 -#define PCI_CHIP_MULLINS_9858 0x9858 -#define PCI_CHIP_MULLINS_9859 0x9859 -#define PCI_CHIP_MULLINS_985A 0x985A -#define PCI_CHIP_MULLINS_985B 0x985B -#define PCI_CHIP_MULLINS_985C 0x985C -#define PCI_CHIP_MULLINS_985D 0x985D -#define PCI_CHIP_MULLINS_985E 0x985E -#define PCI_CHIP_MULLINS_985F 0x985F -#define PCI_CHIP_KAVERI_1304 0x1304 -#define PCI_CHIP_KAVERI_1305 0x1305 -#define PCI_CHIP_KAVERI_1306 0x1306 -#define PCI_CHIP_KAVERI_1307 0x1307 -#define PCI_CHIP_KAVERI_1309 0x1309 -#define PCI_CHIP_KAVERI_130A 0x130A -#define PCI_CHIP_KAVERI_130B 0x130B -#define PCI_CHIP_KAVERI_130C 0x130C -#define PCI_CHIP_KAVERI_130D 0x130D -#define PCI_CHIP_KAVERI_130E 0x130E -#define PCI_CHIP_KAVERI_130F 0x130F -#define PCI_CHIP_KAVERI_1310 0x1310 -#define PCI_CHIP_KAVERI_1311 0x1311 -#define PCI_CHIP_KAVERI_1312 0x1312 -#define PCI_CHIP_KAVERI_1313 0x1313 -#define PCI_CHIP_KAVERI_1315 0x1315 -#define PCI_CHIP_KAVERI_1316 0x1316 -#define PCI_CHIP_KAVERI_1317 0x1317 -#define PCI_CHIP_KAVERI_1318 0x1318 -#define PCI_CHIP_KAVERI_131B 0x131B -#define PCI_CHIP_KAVERI_131C 0x131C -#define PCI_CHIP_KAVERI_131D 0x131D -#define PCI_CHIP_HAWAII_67A0 0x67A0 -#define PCI_CHIP_HAWAII_67A1 0x67A1 -#define PCI_CHIP_HAWAII_67A2 0x67A2 -#define PCI_CHIP_HAWAII_67A8 0x67A8 -#define PCI_CHIP_HAWAII_67A9 0x67A9 -#define PCI_CHIP_HAWAII_67AA 0x67AA -#define PCI_CHIP_HAWAII_67B0 0x67B0 -#define PCI_CHIP_HAWAII_67B1 0x67B1 -#define PCI_CHIP_HAWAII_67B8 0x67B8 -#define PCI_CHIP_HAWAII_67B9 0x67B9 -#define PCI_CHIP_HAWAII_67BA 0x67BA -#define PCI_CHIP_HAWAII_67BE 0x67BE -#define PCI_CHIP_TOPAZ_6900 0x6900 -#define PCI_CHIP_TOPAZ_6901 0x6901 -#define PCI_CHIP_TOPAZ_6902 0x6902 -#define PCI_CHIP_TOPAZ_6903 0x6903 -#define PCI_CHIP_TOPAZ_6907 0x6907 -#define PCI_CHIP_TONGA_6920 0x6920 -#define PCI_CHIP_TONGA_6921 0x6921 -#define PCI_CHIP_TONGA_6928 0x6928 -#define PCI_CHIP_TONGA_6929 0x6929 -#define PCI_CHIP_TONGA_692B 0x692B -#define PCI_CHIP_TONGA_692F 0x692F -#define PCI_CHIP_TONGA_6930 0x6930 -#define PCI_CHIP_TONGA_6938 0x6938 -#define PCI_CHIP_TONGA_6939 0x6939 -#define PCI_CHIP_CARRIZO_9870 0x9870 -#define PCI_CHIP_CARRIZO_9874 0x9874 -#define PCI_CHIP_CARRIZO_9875 0x9875 -#define PCI_CHIP_CARRIZO_9876 0x9876 -#define PCI_CHIP_CARRIZO_9877 0x9877 -#define PCI_CHIP_FIJI_7300 0x7300 -#define PCI_CHIP_STONEY_98E4 0x98E4 -#define PCI_CHIP_POLARIS11_67E0 0x67E0 -#define PCI_CHIP_POLARIS11_67E3 0x67E3 -#define PCI_CHIP_POLARIS11_67E8 0x67E8 -#define PCI_CHIP_POLARIS11_67EB 0x67EB -#define PCI_CHIP_POLARIS11_67EF 0x67EF -#define PCI_CHIP_POLARIS11_67FF 0x67FF -#define PCI_CHIP_POLARIS11_67E1 0x67E1 -#define PCI_CHIP_POLARIS11_67E7 0x67E7 -#define PCI_CHIP_POLARIS11_67E9 0x67E9 -#define PCI_CHIP_POLARIS10_67C0 0x67C0 -#define PCI_CHIP_POLARIS10_67C1 0x67C1 -#define PCI_CHIP_POLARIS10_67C2 0x67C2 -#define PCI_CHIP_POLARIS10_67C4 0x67C4 -#define PCI_CHIP_POLARIS10_67C7 0x67C7 -#define PCI_CHIP_POLARIS10_67DF 0x67DF -#define PCI_CHIP_POLARIS10_67C8 0x67C8 -#define PCI_CHIP_POLARIS10_67C9 0x67C9 -#define PCI_CHIP_POLARIS10_67CA 0x67CA -#define PCI_CHIP_POLARIS10_67CC 0x67CC -#define PCI_CHIP_POLARIS10_67CF 0x67CF diff -Nru xserver-xorg-video-amdgpu-1.2.0/src/drmmode_display.c xserver-xorg-video-amdgpu-1.3.0/src/drmmode_display.c --- xserver-xorg-video-amdgpu-1.2.0/src/drmmode_display.c 2016-11-17 06:07:48.000000000 +0000 +++ xserver-xorg-video-amdgpu-1.3.0/src/drmmode_display.c 2017-03-16 08:32:47.000000000 +0000 @@ -429,8 +429,6 @@ FreeScratchGC(gc); - amdgpu_glamor_finish(pScrn); - pScreen->canDoBGNoneRoot = TRUE; if (info->fbcon_pixmap) @@ -494,87 +492,57 @@ drmmode_crtc_scanout_free(xf86_config->crtc[c]->driver_private); } -static void * -drmmode_crtc_scanout_allocate(xf86CrtcPtr crtc, - struct drmmode_scanout *scanout, - int width, int height) +static PixmapPtr +drmmode_crtc_scanout_create(xf86CrtcPtr crtc, struct drmmode_scanout *scanout, + int width, int height) { ScrnInfoPtr pScrn = crtc->scrn; AMDGPUEntPtr pAMDGPUEnt = AMDGPUEntPriv(pScrn); drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private; drmmode_ptr drmmode = drmmode_crtc->drmmode; - int ret; - int pitch; union gbm_bo_handle bo_handle; + int pitch; - if (scanout->bo) { + if (scanout->pixmap) { if (scanout->width == width && scanout->height == height) - return scanout->bo; + return scanout->pixmap; drmmode_crtc_scanout_destroy(drmmode, scanout); } scanout->bo = amdgpu_alloc_pixmap_bo(pScrn, width, height, - pScrn->depth, 0, - pScrn->bitsPerPixel, &pitch); + pScrn->depth, 0, + pScrn->bitsPerPixel, &pitch); if (!scanout->bo) { xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "Failed to allocate rotation buffer memory\n"); - return NULL; + "Failed to allocate scanout buffer memory\n"); + goto error; } bo_handle = gbm_bo_get_handle(scanout->bo->bo.gbm); - ret = drmModeAddFB(pAMDGPUEnt->fd, width, height, pScrn->depth, - pScrn->bitsPerPixel, pitch, - bo_handle.u32, &scanout->fb_id); - if (ret) { - ErrorF("failed to add rotate fb\n"); - amdgpu_bo_unref(&scanout->bo); - scanout->bo = NULL; - return NULL; - } - - scanout->width = width; - scanout->height = height; - return scanout->bo; -} - -static PixmapPtr -drmmode_crtc_scanout_create(xf86CrtcPtr crtc, - struct drmmode_scanout *scanout, - int width, int height) -{ - ScrnInfoPtr pScrn = crtc->scrn; - drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private; - drmmode_ptr drmmode = drmmode_crtc->drmmode; - unsigned long rotate_pitch; - - if (scanout->pixmap) { - if (scanout->width == width && scanout->height == height) - return scanout->pixmap; - - drmmode_crtc_scanout_destroy(drmmode, scanout); - } - - if (!scanout->bo) { - if (!drmmode_crtc_scanout_allocate(crtc, scanout, width, height)) - return NULL; + if (drmModeAddFB(pAMDGPUEnt->fd, width, height, pScrn->depth, + pScrn->bitsPerPixel, pitch, + bo_handle.u32, &scanout->fb_id) != 0) { + ErrorF("failed to add scanout fb\n"); + goto error; } - rotate_pitch = gbm_bo_get_stride(scanout->bo->bo.gbm); - scanout->pixmap = drmmode_create_bo_pixmap(pScrn, width, height, pScrn->depth, pScrn->bitsPerPixel, - rotate_pitch, - scanout->bo); - if (scanout->pixmap == NULL) { + pitch, scanout->bo); + if (scanout->pixmap) { + scanout->width = width; + scanout->height = height; + } else { xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "Couldn't allocate shadow pixmap for rotated CRTC\n"); + "Couldn't allocate scanout pixmap for CRTC\n"); +error: + drmmode_crtc_scanout_destroy(drmmode, scanout); } - return scanout->pixmap; + return scanout->pixmap; } static void @@ -617,24 +585,50 @@ return TRUE; } +static void +drmmode_crtc_update_tear_free(xf86CrtcPtr crtc) +{ + AMDGPUInfoPtr info = AMDGPUPTR(crtc->scrn); + xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(crtc->scrn); + drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private; + int i; + + drmmode_crtc->tear_free = FALSE; + + for (i = 0; i < xf86_config->num_output; i++) { + xf86OutputPtr output = xf86_config->output[i]; + drmmode_output_private_ptr drmmode_output = output->driver_private; + + if (output->crtc != crtc) + continue; + + if (drmmode_output->tear_free == 1 || + (drmmode_output->tear_free == 2 && + (amdgpu_is_gpu_screen(crtc->scrn->pScreen) || + info->shadow_primary || + crtc->transformPresent || crtc->rotation != RR_Rotate_0))) { + drmmode_crtc->tear_free = TRUE; + return; + } + } +} + #if XF86_CRTC_VERSION >= 4 +#if XF86_CRTC_VERSION < 7 +#define XF86DriverTransformOutput TRUE +#define XF86DriverTransformNone FALSE +#endif + static Bool drmmode_handle_transform(xf86CrtcPtr crtc) { Bool ret; -#if XF86_CRTC_VERSION >= 7 if (crtc->transformPresent || crtc->rotation != RR_Rotate_0) crtc->driverIsPerformingTransform = XF86DriverTransformOutput; else crtc->driverIsPerformingTransform = XF86DriverTransformNone; -#else - AMDGPUInfoPtr info = AMDGPUPTR(crtc->scrn); - - crtc->driverIsPerformingTransform = crtc->transformPresent || - (info->tear_free && crtc->rotation != RR_Rotate_0); -#endif ret = xf86CrtcRotate(crtc); @@ -653,6 +647,115 @@ #endif +#ifdef AMDGPU_PIXMAP_SHARING + +static void +drmmode_crtc_prime_scanout_update(xf86CrtcPtr crtc, DisplayModePtr mode, + unsigned scanout_id, int *fb_id, int *x, + int *y) +{ + ScrnInfoPtr scrn = crtc->scrn; + ScreenPtr screen = scrn->pScreen; + drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private; + + if (drmmode_crtc->tear_free && + !drmmode_crtc->scanout[1].pixmap) { + RegionPtr region; + BoxPtr box; + + drmmode_crtc_scanout_create(crtc, &drmmode_crtc->scanout[1], + mode->HDisplay, + mode->VDisplay); + region = &drmmode_crtc->scanout_last_region; + RegionUninit(region); + region->data = NULL; + box = RegionExtents(region); + box->x1 = crtc->x; + box->y1 = crtc->y; + box->x2 = crtc->x + mode->HDisplay; + box->y2 = crtc->y + mode->VDisplay; + } + + if (scanout_id != drmmode_crtc->scanout_id) { + PixmapDirtyUpdatePtr dirty = NULL; + + xorg_list_for_each_entry(dirty, &screen->pixmap_dirty_list, + ent) { + if (dirty->src == crtc->randr_crtc->scanout_pixmap && + dirty->slave_dst == + drmmode_crtc->scanout[drmmode_crtc->scanout_id].pixmap) { + dirty->slave_dst = + drmmode_crtc->scanout[scanout_id].pixmap; + break; + } + } + + if (!drmmode_crtc->tear_free) { + GCPtr gc = GetScratchGC(scrn->depth, screen); + + ValidateGC(&drmmode_crtc->scanout[0].pixmap->drawable, gc); + gc->ops->CopyArea(&drmmode_crtc->scanout[1].pixmap->drawable, + &drmmode_crtc->scanout[0].pixmap->drawable, + gc, 0, 0, mode->HDisplay, mode->VDisplay, + 0, 0); + FreeScratchGC(gc); + amdgpu_glamor_finish(scrn); + } + } + + *fb_id = drmmode_crtc->scanout[scanout_id].fb_id; + *x = *y = 0; + drmmode_crtc->scanout_id = scanout_id; +} + +#endif /* AMDGPU_PIXMAP_SHARING */ + +static void +drmmode_crtc_scanout_update(xf86CrtcPtr crtc, DisplayModePtr mode, + unsigned scanout_id, int *fb_id, int *x, int *y) +{ + ScrnInfoPtr scrn = crtc->scrn; + ScreenPtr screen = scrn->pScreen; + drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private; + + drmmode_crtc_scanout_create(crtc, &drmmode_crtc->scanout[0], + mode->HDisplay, mode->VDisplay); + if (drmmode_crtc->tear_free) { + drmmode_crtc_scanout_create(crtc, &drmmode_crtc->scanout[1], + mode->HDisplay, mode->VDisplay); + } + + if (drmmode_crtc->scanout[0].pixmap && + (!drmmode_crtc->tear_free || drmmode_crtc->scanout[1].pixmap)) { + RegionPtr region; + BoxPtr box; + + if (!drmmode_crtc->scanout_damage) { + drmmode_crtc->scanout_damage = + DamageCreate(amdgpu_screen_damage_report, + NULL, DamageReportRawRegion, + TRUE, screen, NULL); + DamageRegister(&screen->GetScreenPixmap(screen)->drawable, + drmmode_crtc->scanout_damage); + } + + region = DamageRegion(drmmode_crtc->scanout_damage); + RegionUninit(region); + region->data = NULL; + box = RegionExtents(region); + box->x1 = 0; + box->y1 = 0; + box->x2 = max(box->x2, scrn->virtualX); + box->y2 = max(box->y2, scrn->virtualY); + + *fb_id = drmmode_crtc->scanout[scanout_id].fb_id; + *x = *y = 0; + + amdgpu_scanout_do_update(crtc, scanout_id); + amdgpu_glamor_finish(scrn); + } +} + static Bool drmmode_set_mode_major(xf86CrtcPtr crtc, DisplayModePtr mode, Rotation rotation, int x, int y) @@ -663,6 +766,7 @@ AMDGPUEntPtr pAMDGPUEnt = AMDGPUEntPriv(pScrn); xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(crtc->scrn); drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private; + unsigned scanout_id = 0; drmmode_ptr drmmode = drmmode_crtc->drmmode; int saved_x, saved_y; Rotation saved_rotation; @@ -706,6 +810,10 @@ if (!drmmode_handle_transform(crtc)) goto done; + drmmode_crtc_update_tear_free(crtc); + if (drmmode_crtc->tear_free) + scanout_id = drmmode_crtc->scanout_id; + crtc->funcs->gamma_set(crtc, crtc->gamma_red, crtc->gamma_green, crtc->gamma_blue, crtc->gamma_size); @@ -714,59 +822,22 @@ fb_id = drmmode->fb_id; #ifdef AMDGPU_PIXMAP_SHARING if (crtc->randr_crtc && crtc->randr_crtc->scanout_pixmap) { - fb_id = drmmode_crtc->scanout[0].fb_id; - x = y = 0; + drmmode_crtc_prime_scanout_update(crtc, mode, scanout_id, + &fb_id, &x, &y); } else #endif if (drmmode_crtc->rotate.fb_id) { fb_id = drmmode_crtc->rotate.fb_id; x = y = 0; - } else if ( -#ifdef AMDGPU_PIXMAP_SHARING - !pScreen->isGPU && -#endif - (info->tear_free || + + } else if (!amdgpu_is_gpu_screen(pScreen) && + (drmmode_crtc->tear_free || #if XF86_CRTC_VERSION >= 4 crtc->driverIsPerformingTransform || #endif info->shadow_primary)) { - for (i = 0; i < (info->tear_free ? 2 : 1); i++) { - drmmode_crtc_scanout_create(crtc, - &drmmode_crtc->scanout[i], - mode->HDisplay, - mode->VDisplay); - } - - if (drmmode_crtc->scanout[0].pixmap && - (!info->tear_free || drmmode_crtc->scanout[1].pixmap)) { - RegionPtr pRegion; - BoxPtr pBox; - - if (!drmmode_crtc->scanout_damage) { - drmmode_crtc->scanout_damage = - DamageCreate(amdgpu_screen_damage_report, - NULL, DamageReportRawRegion, - TRUE, pScreen, NULL); - DamageRegister(&pScreen->GetScreenPixmap(pScreen)->drawable, - drmmode_crtc->scanout_damage); - } - - pRegion = DamageRegion(drmmode_crtc->scanout_damage); - RegionUninit(pRegion); - pRegion->data = NULL; - pBox = RegionExtents(pRegion); - pBox->x1 = 0; - pBox->y1 = 0; - pBox->x2 = max(pBox->x2, pScrn->virtualX); - pBox->y2 = max(pBox->y2, pScrn->virtualY); - - drmmode_crtc->scanout_id = 0; - fb_id = drmmode_crtc->scanout[0].fb_id; - x = y = 0; - - amdgpu_scanout_update_handler(crtc, 0, 0, drmmode_crtc); - amdgpu_glamor_finish(pScrn); - } + drmmode_crtc_scanout_update(crtc, mode, scanout_id, + &fb_id, &x, &y); } if (fb_id == 0) { @@ -847,8 +918,12 @@ } else { crtc->active = TRUE; - if (fb_id != drmmode_crtc->scanout[0].fb_id) + if (fb_id != drmmode_crtc->scanout[scanout_id].fb_id) drmmode_crtc_scanout_free(drmmode_crtc); + else if (!drmmode_crtc->tear_free) { + drmmode_crtc_scanout_destroy(drmmode, + &drmmode_crtc->scanout[1]); + } } return ret; @@ -1052,13 +1127,20 @@ info->cursor_w, info->cursor_h); } -static void *drmmode_crtc_shadow_allocate(xf86CrtcPtr crtc, int width, - int height) +/* Xorg expects a non-NULL return value from drmmode_crtc_shadow_allocate, and + * passes that back to drmmode_crtc_scanout_create; it doesn't use it for + * anything else. + */ +static void * +drmmode_crtc_shadow_allocate(xf86CrtcPtr crtc, int width, int height) { drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private; - return drmmode_crtc_scanout_allocate(crtc, &drmmode_crtc->rotate, - width, height); + if (!drmmode_crtc_scanout_create(crtc, &drmmode_crtc->rotate, width, + height)) + return NULL; + + return (void*)~0UL; } static PixmapPtr @@ -1066,11 +1148,12 @@ { drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private; - /* Xorg passes in the return value of drmmode_crtc_shadow_allocate - * for data, but that's redundant for drmmode_crtc_scanout_create. - */ - return drmmode_crtc_scanout_create(crtc, &drmmode_crtc->rotate, width, - height); + if (!data) { + drmmode_crtc_scanout_create(crtc, &drmmode_crtc->rotate, width, + height); + } + + return drmmode_crtc->rotate.pixmap; } static void @@ -1098,13 +1181,12 @@ static Bool drmmode_set_scanout_pixmap(xf86CrtcPtr crtc, PixmapPtr ppix) { drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private; - AMDGPUInfoPtr info = AMDGPUPTR(crtc->scrn); + unsigned scanout_id = drmmode_crtc->scanout_id; ScreenPtr screen = crtc->scrn->pScreen; PixmapDirtyUpdatePtr dirty; xorg_list_for_each_entry(dirty, &screen->pixmap_dirty_list, ent) { - if (dirty->slave_dst != - drmmode_crtc->scanout[drmmode_crtc->scanout_id].pixmap) + if (dirty->slave_dst != drmmode_crtc->scanout[scanout_id].pixmap) continue; PixmapStopDirtyTracking(dirty->src, dirty->slave_dst); @@ -1120,7 +1202,7 @@ ppix->drawable.height)) return FALSE; - if (info->tear_free && + if (drmmode_crtc->tear_free && !drmmode_crtc_scanout_create(crtc, &drmmode_crtc->scanout[1], ppix->drawable.width, ppix->drawable.height)) { @@ -1129,13 +1211,13 @@ } #ifdef HAS_DIRTYTRACKING_ROTATION - PixmapStartDirtyTracking(ppix, drmmode_crtc->scanout[0].pixmap, + PixmapStartDirtyTracking(ppix, drmmode_crtc->scanout[scanout_id].pixmap, 0, 0, 0, 0, RR_Rotate_0); #elif defined(HAS_DIRTYTRACKING2) - PixmapStartDirtyTracking2(ppix, drmmode_crtc->scanout[0].pixmap, + PixmapStartDirtyTracking2(ppix, drmmode_crtc->scanout[scanout_id].pixmap, 0, 0, 0, 0); #else - PixmapStartDirtyTracking(ppix, drmmode_crtc->scanout[0].pixmap, 0, 0); + PixmapStartDirtyTracking(ppix, drmmode_crtc->scanout[scanout_id].pixmap, 0, 0); #endif return TRUE; } @@ -1367,14 +1449,15 @@ static void drmmode_output_create_resources(xf86OutputPtr output) { + AMDGPUInfoPtr info = AMDGPUPTR(output->scrn); drmmode_output_private_ptr drmmode_output = output->driver_private; drmModeConnectorPtr mode_output = drmmode_output->mode_output; AMDGPUEntPtr pAMDGPUEnt = AMDGPUEntPriv(output->scrn); - drmModePropertyPtr drmmode_prop; + drmModePropertyPtr drmmode_prop, tearfree_prop; int i, j, err; drmmode_output->props = - calloc(mode_output->count_props, sizeof(drmmode_prop_rec)); + calloc(mode_output->count_props + 1, sizeof(drmmode_prop_rec)); if (!drmmode_output->props) return; @@ -1392,6 +1475,23 @@ j++; } + /* Userspace-only property for TearFree */ + tearfree_prop = calloc(1, sizeof(*tearfree_prop)); + tearfree_prop->flags = DRM_MODE_PROP_ENUM; + strncpy(tearfree_prop->name, "TearFree", 8); + tearfree_prop->count_enums = 3; + tearfree_prop->enums = calloc(tearfree_prop->count_enums, + sizeof(*tearfree_prop->enums)); + strncpy(tearfree_prop->enums[0].name, "off", 3); + strncpy(tearfree_prop->enums[1].name, "on", 2); + tearfree_prop->enums[1].value = 1; + strncpy(tearfree_prop->enums[2].name, "auto", 4); + tearfree_prop->enums[2].value = 2; + drmmode_output->props[j].mode_prop = tearfree_prop; + drmmode_output->props[j].value = info->tear_free; + drmmode_output->tear_free = info->tear_free; + drmmode_output->num_props++; + for (i = 0; i < drmmode_output->num_props; i++) { drmmode_prop_ptr p = &drmmode_output->props[i]; drmmode_prop = p->mode_prop; @@ -1517,11 +1617,26 @@ /* search for matching name string, then set its value down */ for (j = 0; j < p->mode_prop->count_enums; j++) { if (!strcmp(p->mode_prop->enums[j].name, name)) { - drmModeConnectorSetProperty(pAMDGPUEnt->fd, - drmmode_output->output_id, - p->mode_prop->prop_id, - p->mode_prop->enums - [j].value); + if (i == (drmmode_output->num_props - 1)) { + if (drmmode_output->tear_free != j) { + xf86CrtcPtr crtc = output->crtc; + + drmmode_output->tear_free = j; + if (crtc) { + drmmode_set_mode_major(crtc, + &crtc->mode, + crtc->rotation, + crtc->x, + crtc->y); + } + } + } else { + drmModeConnectorSetProperty(pAMDGPUEnt->fd, + drmmode_output->output_id, + p->mode_prop->prop_id, + p->mode_prop->enums[j].value); + } + return TRUE; } } @@ -2132,6 +2247,59 @@ } #endif +static Bool drmmode_probe_page_flip_target(AMDGPUEntPtr pAMDGPUEnt) +{ + uint64_t cap_value; + + return drmGetCap(pAMDGPUEnt->fd, DRM_CAP_PAGE_FLIP_TARGET, + &cap_value) == 0 && cap_value != 0; +} + +static int +drmmode_page_flip(AMDGPUEntPtr pAMDGPUEnt, drmmode_crtc_private_ptr drmmode_crtc, + int fb_id, uint32_t flags, uintptr_t drm_queue_seq) +{ + flags |= DRM_MODE_PAGE_FLIP_EVENT; + return drmModePageFlip(pAMDGPUEnt->fd, drmmode_crtc->mode_crtc->crtc_id, + fb_id, flags, (void*)drm_queue_seq); +} + +int +drmmode_page_flip_target_absolute(AMDGPUEntPtr pAMDGPUEnt, + drmmode_crtc_private_ptr drmmode_crtc, + int fb_id, uint32_t flags, + uintptr_t drm_queue_seq, uint32_t target_msc) +{ + if (pAMDGPUEnt->has_page_flip_target) { + flags |= DRM_MODE_PAGE_FLIP_EVENT | DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE; + return drmModePageFlipTarget(pAMDGPUEnt->fd, + drmmode_crtc->mode_crtc->crtc_id, + fb_id, flags, (void*)drm_queue_seq, + target_msc); + } + + return drmmode_page_flip(pAMDGPUEnt, drmmode_crtc, fb_id, flags, + drm_queue_seq); +} + +int +drmmode_page_flip_target_relative(AMDGPUEntPtr pAMDGPUEnt, + drmmode_crtc_private_ptr drmmode_crtc, + int fb_id, uint32_t flags, + uintptr_t drm_queue_seq, uint32_t target_msc) +{ + if (pAMDGPUEnt->has_page_flip_target) { + flags |= DRM_MODE_PAGE_FLIP_EVENT | DRM_MODE_PAGE_FLIP_TARGET_RELATIVE; + return drmModePageFlipTarget(pAMDGPUEnt->fd, + drmmode_crtc->mode_crtc->crtc_id, + fb_id, flags, (void*)drm_queue_seq, + target_msc); + } + + return drmmode_page_flip(pAMDGPUEnt, drmmode_crtc, fb_id, flags, + drm_queue_seq); +} + Bool drmmode_pre_init(ScrnInfoPtr pScrn, drmmode_ptr drmmode, int cpp) { AMDGPUEntPtr pAMDGPUEnt = AMDGPUEntPriv(pScrn); @@ -2198,6 +2366,8 @@ drmmode->event_context.vblank_handler = amdgpu_drm_queue_handler; drmmode->event_context.page_flip_handler = amdgpu_drm_queue_handler; + pAMDGPUEnt->has_page_flip_target = drmmode_probe_page_flip_target(pAMDGPUEnt); + drmModeFreeResources(mode_res); return TRUE; } @@ -2243,13 +2413,8 @@ #endif } - for (c = 0; c < config->num_crtc; c++) { - xf86CrtcPtr crtc = config->crtc[c]; - drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private; - - drmmode_crtc_scanout_destroy(&info->drmmode, &drmmode_crtc->scanout[0]); - drmmode_crtc_scanout_destroy(&info->drmmode, &drmmode_crtc->scanout[1]); - } + for (c = 0; c < config->num_crtc; c++) + drmmode_crtc_scanout_free(config->crtc[c]->driver_private); } void drmmode_set_cursor(ScrnInfoPtr scrn, drmmode_ptr drmmode, int id, @@ -2475,10 +2640,20 @@ ScrnInfoPtr scrn = drmmode->scrn; struct udev_device *dev; Bool received = FALSE; + struct timeval tv = { 0, 0 }; + fd_set readfd; + + FD_ZERO(&readfd); + FD_SET(fd, &readfd); - while ((dev = udev_monitor_receive_device(drmmode->uevent_monitor))) { - udev_device_unref(dev); - received = TRUE; + while (select(fd + 1, &readfd, NULL, NULL, &tv) > 0 && + FD_ISSET(fd, &readfd)) { + /* select() ensured that this will not block */ + dev = udev_monitor_receive_device(drmmode->uevent_monitor); + if (dev) { + udev_device_unref(dev); + received = TRUE; + } } if (received) @@ -2535,7 +2710,8 @@ PixmapPtr new_front, uint64_t id, void *data, int ref_crtc_hw_id, amdgpu_drm_handler_proc handler, amdgpu_drm_abort_proc abort, - enum drmmode_flip_sync flip_sync) + enum drmmode_flip_sync flip_sync, + uint32_t target_msc) { AMDGPUEntPtr pAMDGPUEnt = AMDGPUEntPriv(scrn); xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR(scrn); @@ -2543,7 +2719,7 @@ drmmode_crtc_private_ptr drmmode_crtc = config->crtc[0]->driver_private; drmmode_ptr drmmode = drmmode_crtc->drmmode; int i; - uint32_t flip_flags = DRM_MODE_PAGE_FLIP_EVENT; + uint32_t flip_flags = flip_sync == FLIP_ASYNC ? DRM_MODE_PAGE_FLIP_ASYNC : 0; drmmode_flipdata_ptr flipdata; uintptr_t drm_queue_seq = 0; uint32_t new_front_handle; @@ -2585,9 +2761,6 @@ flipdata->handler = handler; flipdata->abort = abort; - if (flip_sync == FLIP_ASYNC) - flip_flags |= DRM_MODE_PAGE_FLIP_ASYNC; - for (i = 0; i < config->num_crtc; i++) { crtc = config->crtc[i]; @@ -2613,13 +2786,23 @@ goto error; } - if (drmModePageFlip(pAMDGPUEnt->fd, drmmode_crtc->mode_crtc->crtc_id, - drmmode->fb_id, flip_flags, - (void*)drm_queue_seq)) { - xf86DrvMsg(scrn->scrnIndex, X_WARNING, - "flip queue failed: %s\n", strerror(errno)); - goto error; + if (drmmode_crtc->hw_id == ref_crtc_hw_id) { + if (drmmode_page_flip_target_absolute(pAMDGPUEnt, + drmmode_crtc, + drmmode->fb_id, + flip_flags, + drm_queue_seq, + target_msc) != 0) + goto flip_error; + } else { + if (drmmode_page_flip_target_relative(pAMDGPUEnt, + drmmode_crtc, + drmmode->fb_id, + flip_flags, + drm_queue_seq, 0) != 0) + goto flip_error; } + drmmode_crtc->flip_pending = TRUE; drm_queue_seq = 0; } @@ -2627,8 +2810,13 @@ if (flipdata->flip_count > 0) return TRUE; +flip_error: + xf86DrvMsg(scrn->scrnIndex, X_WARNING, "flip queue failed: %s\n", + strerror(errno)); + error: - if (flipdata && flipdata->flip_count <= 1) { + if (flipdata && flipdata->flip_count <= 1 && + drmmode->fb_id != flipdata->old_fb_id) { drmModeRmFB(pAMDGPUEnt->fd, drmmode->fb_id); drmmode->fb_id = flipdata->old_fb_id; } @@ -2637,8 +2825,10 @@ amdgpu_drm_abort_entry(drm_queue_seq); else if (crtc) drmmode_flip_abort(crtc, flipdata); - else if (flipdata && flipdata->flip_count <= 1) + else { + abort(NULL, data); free(flipdata); + } xf86DrvMsg(scrn->scrnIndex, X_WARNING, "Page flip failed: %s\n", strerror(errno)); diff -Nru xserver-xorg-video-amdgpu-1.2.0/src/drmmode_display.h xserver-xorg-video-amdgpu-1.3.0/src/drmmode_display.h --- xserver-xorg-video-amdgpu-1.2.0/src/drmmode_display.h 2016-11-17 06:07:48.000000000 +0000 +++ xserver-xorg-video-amdgpu-1.3.0/src/drmmode_display.h 2017-03-16 08:32:47.000000000 +0000 @@ -36,10 +36,6 @@ #include "amdgpu_probe.h" #include "amdgpu.h" -#ifndef DRM_CAP_TIMESTAMP_MONOTONIC -#define DRM_CAP_TIMESTAMP_MONOTONIC 0x6 -#endif - typedef struct { unsigned fb_id; drmModeFBPtr mode_fb; @@ -89,6 +85,7 @@ RegionRec scanout_last_region; unsigned scanout_id; Bool scanout_update_pending; + Bool tear_free; int dpms_mode; /* For when a flip is pending when DPMS off requested */ int pending_dpms_mode; @@ -121,6 +118,7 @@ drmmode_prop_ptr props; int enc_mask; int enc_clone_mask; + int tear_free; } drmmode_output_private_rec, *drmmode_output_private_ptr; @@ -130,6 +128,16 @@ }; +extern int drmmode_page_flip_target_absolute(AMDGPUEntPtr pAMDGPUEnt, + drmmode_crtc_private_ptr drmmode_crtc, + int fb_id, uint32_t flags, + uintptr_t drm_queue_seq, + uint32_t target_msc); +extern int drmmode_page_flip_target_relative(AMDGPUEntPtr pAMDGPUEnt, + drmmode_crtc_private_ptr drmmode_crtc, + int fb_id, uint32_t flags, + uintptr_t drm_queue_seq, + uint32_t target_msc); extern Bool drmmode_pre_init(ScrnInfoPtr pScrn, drmmode_ptr drmmode, int cpp); extern void drmmode_init(ScrnInfoPtr pScrn, drmmode_ptr drmmode); extern void drmmode_fini(ScrnInfoPtr pScrn, drmmode_ptr drmmode); @@ -153,7 +161,8 @@ PixmapPtr new_front, uint64_t id, void *data, int ref_crtc_hw_id, amdgpu_drm_handler_proc handler, amdgpu_drm_abort_proc abort, - enum drmmode_flip_sync flip_sync); + enum drmmode_flip_sync flip_sync, + uint32_t target_msc); int drmmode_crtc_get_ust_msc(xf86CrtcPtr crtc, CARD64 *ust, CARD64 *msc); int drmmode_get_current_ust(int drm_fd, CARD64 * ust); diff -Nru xserver-xorg-video-amdgpu-1.2.0/src/Makefile.am xserver-xorg-video-amdgpu-1.3.0/src/Makefile.am --- xserver-xorg-video-amdgpu-1.2.0/src/Makefile.am 2015-11-19 08:24:14.000000000 +0000 +++ xserver-xorg-video-amdgpu-1.3.0/src/Makefile.am 2017-03-16 08:32:47.000000000 +0000 @@ -68,13 +68,5 @@ amdgpu_version.h \ amdgpu_video.h \ simple_list.h \ - amdpciids.h \ - ati_pciids_gen.h \ - amdgpu_chipinfo_gen.h \ - amdgpu_chipset_gen.h \ - amdgpu_pci_chipset_gen.h \ - amdgpu_pci_device_match_gen.h \ - pcidb/ati_pciids.csv \ - pcidb/parse_pci_ids.pl \ amdgpu_dri2.h \ drmmode_display.h diff -Nru xserver-xorg-video-amdgpu-1.2.0/src/Makefile.in xserver-xorg-video-amdgpu-1.3.0/src/Makefile.in --- xserver-xorg-video-amdgpu-1.2.0/src/Makefile.in 2016-11-17 06:16:10.000000000 +0000 +++ xserver-xorg-video-amdgpu-1.3.0/src/Makefile.in 2017-03-16 08:33:02.000000000 +0000 @@ -419,14 +419,6 @@ amdgpu_version.h \ amdgpu_video.h \ simple_list.h \ - amdpciids.h \ - ati_pciids_gen.h \ - amdgpu_chipinfo_gen.h \ - amdgpu_chipset_gen.h \ - amdgpu_pci_chipset_gen.h \ - amdgpu_pci_device_match_gen.h \ - pcidb/ati_pciids.csv \ - pcidb/parse_pci_ids.pl \ amdgpu_dri2.h \ drmmode_display.h diff -Nru xserver-xorg-video-amdgpu-1.2.0/src/pcidb/ati_pciids.csv xserver-xorg-video-amdgpu-1.3.0/src/pcidb/ati_pciids.csv --- xserver-xorg-video-amdgpu-1.2.0/src/pcidb/ati_pciids.csv 2016-09-16 06:47:43.000000000 +0000 +++ xserver-xorg-video-amdgpu-1.3.0/src/pcidb/ati_pciids.csv 1970-01-01 00:00:00.000000000 +0000 @@ -1,192 +0,0 @@ -"#pciid","define","family","name" -"0x6600","OLAND_6600","OLAND","OLAND" -"0x6601","OLAND_6601","OLAND","OLAND" -"0x6602","OLAND_6602","OLAND","OLAND" -"0x6603","OLAND_6603","OLAND","OLAND" -"0x6604","OLAND_6604","OLAND","OLAND" -"0x6605","OLAND_6605","OLAND","OLAND" -"0x6606","OLAND_6606","OLAND","OLAND" -"0x6607","OLAND_6607","OLAND","OLAND" -"0x6608","OLAND_6608","OLAND","OLAND" -"0x6610","OLAND_6610","OLAND","OLAND" -"0x6611","OLAND_6611","OLAND","OLAND" -"0x6613","OLAND_6613","OLAND","OLAND" -"0x6617","OLAND_6617","OLAND","OLAND" -"0x6620","OLAND_6620","OLAND","OLAND" -"0x6621","OLAND_6621","OLAND","OLAND" -"0x6623","OLAND_6623","OLAND","OLAND" -"0x6631","OLAND_6631","OLAND","OLAND" -"0x6660","HAINAN_6660","HAINAN","HAINAN" -"0x6663","HAINAN_6663","HAINAN","HAINAN" -"0x6664","HAINAN_6664","HAINAN","HAINAN" -"0x6665","HAINAN_6665","HAINAN","HAINAN" -"0x6667","HAINAN_6667","HAINAN","HAINAN" -"0x666F","HAINAN_666F","HAINAN","HAINAN" -"0x6780","TAHITI_6780","TAHITI","TAHITI" -"0x6784","TAHITI_6784","TAHITI","TAHITI" -"0x6788","TAHITI_6788","TAHITI","TAHITI" -"0x678A","TAHITI_678A","TAHITI","TAHITI" -"0x6790","TAHITI_6790","TAHITI","TAHITI" -"0x6791","TAHITI_6791","TAHITI","TAHITI" -"0x6792","TAHITI_6792","TAHITI","TAHITI" -"0x6798","TAHITI_6798","TAHITI","TAHITI" -"0x6799","TAHITI_6799","TAHITI","TAHITI" -"0x679A","TAHITI_679A","TAHITI","TAHITI" -"0x679B","TAHITI_679B","TAHITI","TAHITI" -"0x679E","TAHITI_679E","TAHITI","TAHITI" -"0x679F","TAHITI_679F","TAHITI","TAHITI" -"0x6800","PITCAIRN_6800","PITCAIRN","PITCAIRN" -"0x6801","PITCAIRN_6801","PITCAIRN","PITCAIRN" -"0x6802","PITCAIRN_6802","PITCAIRN","PITCAIRN" -"0x6806","PITCAIRN_6806","PITCAIRN","PITCAIRN" -"0x6808","PITCAIRN_6808","PITCAIRN","PITCAIRN" -"0x6809","PITCAIRN_6809","PITCAIRN","PITCAIRN" -"0x6810","PITCAIRN_6810","PITCAIRN","PITCAIRN" -"0x6811","PITCAIRN_6811","PITCAIRN","PITCAIRN" -"0x6816","PITCAIRN_6816","PITCAIRN","PITCAIRN" -"0x6817","PITCAIRN_6817","PITCAIRN","PITCAIRN" -"0x6818","PITCAIRN_6818","PITCAIRN","PITCAIRN" -"0x6819","PITCAIRN_6819","PITCAIRN","PITCAIRN" -"0x6820","VERDE_6820","VERDE","VERDE" -"0x6821","VERDE_6821","VERDE","VERDE" -"0x6822","VERDE_6822","VERDE","VERDE" -"0x6823","VERDE_6823","VERDE","VERDE" -"0x6824","VERDE_6824","VERDE","VERDE" -"0x6825","VERDE_6825","VERDE","VERDE" -"0x6826","VERDE_6826","VERDE","VERDE" -"0x6827","VERDE_6827","VERDE","VERDE" -"0x6828","VERDE_6828","VERDE","VERDE" -"0x6829","VERDE_6829","VERDE","VERDE" -"0x682A","VERDE_682A","VERDE","VERDE" -"0x682B","VERDE_682B","VERDE","VERDE" -"0x682C","VERDE_682C","VERDE","VERDE" -"0x682D","VERDE_682D","VERDE","VERDE" -"0x682F","VERDE_682F","VERDE","VERDE" -"0x6830","VERDE_6830","VERDE","VERDE" -"0x6831","VERDE_6831","VERDE","VERDE" -"0x6835","VERDE_6835","VERDE","VERDE" -"0x6837","VERDE_6837","VERDE","VERDE" -"0x6838","VERDE_6838","VERDE","VERDE" -"0x6839","VERDE_6839","VERDE","VERDE" -"0x683B","VERDE_683B","VERDE","VERDE" -"0x683D","VERDE_683D","VERDE","VERDE" -"0x683F","VERDE_683F","VERDE","VERDE" -"0x684C","PITCAIRN_684C","PITCAIRN","PITCAIRN" -"0x6640","BONAIRE_6640","BONAIRE","BONAIRE" -"0x6641","BONAIRE_6641","BONAIRE","BONAIRE" -"0x6646","BONAIRE_6646","BONAIRE","BONAIRE" -"0x6647","BONAIRE_6647","BONAIRE","BONAIRE" -"0x6649","BONAIRE_6649","BONAIRE","BONAIRE" -"0x6650","BONAIRE_6650","BONAIRE","BONAIRE" -"0x6651","BONAIRE_6651","BONAIRE","BONAIRE" -"0x6658","BONAIRE_6658","BONAIRE","BONAIRE" -"0x665C","BONAIRE_665C","BONAIRE","BONAIRE" -"0x665D","BONAIRE_665D","BONAIRE","BONAIRE" -"0x665F","BONAIRE_665F","BONAIRE","BONAIRE" -"0x9830","KABINI_9830","KABINI","KABINI" -"0x9831","KABINI_9831","KABINI","KABINI" -"0x9832","KABINI_9832","KABINI","KABINI" -"0x9833","KABINI_9833","KABINI","KABINI" -"0x9834","KABINI_9834","KABINI","KABINI" -"0x9835","KABINI_9835","KABINI","KABINI" -"0x9836","KABINI_9836","KABINI","KABINI" -"0x9837","KABINI_9837","KABINI","KABINI" -"0x9838","KABINI_9838","KABINI","KABINI" -"0x9839","KABINI_9839","KABINI","KABINI" -"0x983A","KABINI_983A","KABINI","KABINI" -"0x983B","KABINI_983B","KABINI","KABINI" -"0x983C","KABINI_983C","KABINI","KABINI" -"0x983D","KABINI_983D","KABINI","KABINI" -"0x983E","KABINI_983E","KABINI","KABINI" -"0x983F","KABINI_983F","KABINI","KABINI" -"0x9850","MULLINS_9850","MULLINS","MULLINS" -"0x9851","MULLINS_9851","MULLINS","MULLINS" -"0x9852","MULLINS_9852","MULLINS","MULLINS" -"0x9853","MULLINS_9853","MULLINS","MULLINS" -"0x9854","MULLINS_9854","MULLINS","MULLINS" -"0x9855","MULLINS_9855","MULLINS","MULLINS" -"0x9856","MULLINS_9856","MULLINS","MULLINS" -"0x9857","MULLINS_9857","MULLINS","MULLINS" -"0x9858","MULLINS_9858","MULLINS","MULLINS" -"0x9859","MULLINS_9859","MULLINS","MULLINS" -"0x985A","MULLINS_985A","MULLINS","MULLINS" -"0x985B","MULLINS_985B","MULLINS","MULLINS" -"0x985C","MULLINS_985C","MULLINS","MULLINS" -"0x985D","MULLINS_985D","MULLINS","MULLINS" -"0x985E","MULLINS_985E","MULLINS","MULLINS" -"0x985F","MULLINS_985F","MULLINS","MULLINS" -"0x1304","KAVERI_1304","KAVERI","KAVERI" -"0x1305","KAVERI_1305","KAVERI","KAVERI" -"0x1306","KAVERI_1306","KAVERI","KAVERI" -"0x1307","KAVERI_1307","KAVERI","KAVERI" -"0x1309","KAVERI_1309","KAVERI","KAVERI" -"0x130A","KAVERI_130A","KAVERI","KAVERI" -"0x130B","KAVERI_130B","KAVERI","KAVERI" -"0x130C","KAVERI_130C","KAVERI","KAVERI" -"0x130D","KAVERI_130D","KAVERI","KAVERI" -"0x130E","KAVERI_130E","KAVERI","KAVERI" -"0x130F","KAVERI_130F","KAVERI","KAVERI" -"0x1310","KAVERI_1310","KAVERI","KAVERI" -"0x1311","KAVERI_1311","KAVERI","KAVERI" -"0x1312","KAVERI_1312","KAVERI","KAVERI" -"0x1313","KAVERI_1313","KAVERI","KAVERI" -"0x1315","KAVERI_1315","KAVERI","KAVERI" -"0x1316","KAVERI_1316","KAVERI","KAVERI" -"0x1317","KAVERI_1317","KAVERI","KAVERI" -"0x1318","KAVERI_1318","KAVERI","KAVERI" -"0x131B","KAVERI_131B","KAVERI","KAVERI" -"0x131C","KAVERI_131C","KAVERI","KAVERI" -"0x131D","KAVERI_131D","KAVERI","KAVERI" -"0x67A0","HAWAII_67A0","HAWAII","HAWAII" -"0x67A1","HAWAII_67A1","HAWAII","HAWAII" -"0x67A2","HAWAII_67A2","HAWAII","HAWAII" -"0x67A8","HAWAII_67A8","HAWAII","HAWAII" -"0x67A9","HAWAII_67A9","HAWAII","HAWAII" -"0x67AA","HAWAII_67AA","HAWAII","HAWAII" -"0x67B0","HAWAII_67B0","HAWAII","HAWAII" -"0x67B1","HAWAII_67B1","HAWAII","HAWAII" -"0x67B8","HAWAII_67B8","HAWAII","HAWAII" -"0x67B9","HAWAII_67B9","HAWAII","HAWAII" -"0x67BA","HAWAII_67BA","HAWAII","HAWAII" -"0x67BE","HAWAII_67BE","HAWAII","HAWAII" -"0x6900","TOPAZ_6900","TOPAZ","TOPAZ" -"0x6901","TOPAZ_6901","TOPAZ","TOPAZ" -"0x6902","TOPAZ_6902","TOPAZ","TOPAZ" -"0x6903","TOPAZ_6903","TOPAZ","TOPAZ" -"0x6907","TOPAZ_6907","TOPAZ","TOPAZ" -"0x6920","TONGA_6920","TONGA","TONGA" -"0x6921","TONGA_6921","TONGA","TONGA" -"0x6928","TONGA_6928","TONGA","TONGA" -"0x6929","TONGA_6929","TONGA","TONGA" -"0x692B","TONGA_692B","TONGA","TONGA" -"0x692F","TONGA_692F","TONGA","TONGA" -"0x6930","TONGA_6930","TONGA","TONGA" -"0x6938","TONGA_6938","TONGA","TONGA" -"0x6939","TONGA_6939","TONGA","TONGA" -"0x9870","CARRIZO_9870","CARRIZO","CARRIZO" -"0x9874","CARRIZO_9874","CARRIZO","CARRIZO" -"0x9875","CARRIZO_9875","CARRIZO","CARRIZO" -"0x9876","CARRIZO_9876","CARRIZO","CARRIZO" -"0x9877","CARRIZO_9877","CARRIZO","CARRIZO" -"0x7300","FIJI_7300","FIJI","FIJI" -"0x98E4","STONEY_98E4","STONEY","STONEY" -"0x67E0","POLARIS11_67E0","POLARIS11","POLARIS11" -"0x67E3","POLARIS11_67E3","POLARIS11","POLARIS11" -"0x67E8","POLARIS11_67E8","POLARIS11","POLARIS11" -"0x67EB","POLARIS11_67EB","POLARIS11","POLARIS11" -"0x67EF","POLARIS11_67EF","POLARIS11","POLARIS11" -"0x67FF","POLARIS11_67FF","POLARIS11","POLARIS11" -"0x67E1","POLARIS11_67E1","POLARIS11","POLARIS11" -"0x67E7","POLARIS11_67E7","POLARIS11","POLARIS11" -"0x67E9","POLARIS11_67E9","POLARIS11","POLARIS11" -"0x67C0","POLARIS10_67C0","POLARIS10","POLARIS10" -"0x67C1","POLARIS10_67C1","POLARIS10","POLARIS10" -"0x67C2","POLARIS10_67C2","POLARIS10","POLARIS10" -"0x67C4","POLARIS10_67C4","POLARIS10","POLARIS10" -"0x67C7","POLARIS10_67C7","POLARIS10","POLARIS10" -"0x67DF","POLARIS10_67DF","POLARIS10","POLARIS10" -"0x67C8","POLARIS10_67C8","POLARIS10","POLARIS10" -"0x67C9","POLARIS10_67C9","POLARIS10","POLARIS10" -"0x67CA","POLARIS10_67CA","POLARIS10","POLARIS10" -"0x67CC","POLARIS10_67CC","POLARIS10","POLARIS10" -"0x67CF","POLARIS10_67CF","POLARIS10","POLARIS10" diff -Nru xserver-xorg-video-amdgpu-1.2.0/src/pcidb/parse_pci_ids.pl xserver-xorg-video-amdgpu-1.3.0/src/pcidb/parse_pci_ids.pl --- xserver-xorg-video-amdgpu-1.2.0/src/pcidb/parse_pci_ids.pl 2016-11-17 06:07:48.000000000 +0000 +++ xserver-xorg-video-amdgpu-1.3.0/src/pcidb/parse_pci_ids.pl 1970-01-01 00:00:00.000000000 +0000 @@ -1,82 +0,0 @@ -#!/usr/bin/perl -# -# Copyright 2007 Red Hat Inc. -# This crappy script written by Dave Airlie to avoid hassle of adding -# ids in every place. -# -use strict; -use warnings; -use Text::CSV_XS; - -my $file = $ARGV[0]; - -my $atioutfile = 'ati_pciids_gen.h'; -my $amdgpupcichipsetfile = 'amdgpu_pci_chipset_gen.h'; -my $amdgpupcidevicematchfile = 'amdgpu_pci_device_match_gen.h'; -my $amdgpuchipsetfile = 'amdgpu_chipset_gen.h'; -my $amdgpuchipinfofile = 'amdgpu_chipinfo_gen.h'; - -my %uniquechipsets; -my @uniquearray; -my $numunique = 0; - -my $csv = Text::CSV_XS->new(); - -open (CSV, "<", $file) or die $!; - -open (ATIOUT, ">", $atioutfile) or die; -open (PCICHIPSET, ">", $amdgpupcichipsetfile) or die; -open (PCIDEVICEMATCH, ">", $amdgpupcidevicematchfile) or die; -open (AMDGPUCHIPSET, ">", $amdgpuchipsetfile) or die; -open (AMDGPUCHIPINFO, ">", $amdgpuchipinfofile) or die; - -print AMDGPUCHIPSET "/* This file is autogenerated please do not edit */\n"; -print AMDGPUCHIPSET "SymTabRec AMDGPUChipsets[] = {\n"; -print PCICHIPSET "/* This file is autogenerated please do not edit */\n"; -print PCICHIPSET "static PciChipsets AMDGPUPciChipsets[] = {\n"; -print PCIDEVICEMATCH "/* This file is autogenerated please do not edit */\n"; -print PCIDEVICEMATCH "static const struct pci_id_match amdgpu_device_match[] = {\n"; -print AMDGPUCHIPINFO "/* This file is autogenerated please do not edit */\n"; -print AMDGPUCHIPINFO "static AMDGPUCardInfo AMDGPUCards[] = {\n"; -while () { - if ($csv->parse($_)) { - my @columns = $csv->fields(); - - if ((substr($columns[0], 0, 1) ne "#")) { - - print ATIOUT "#define PCI_CHIP_$columns[1] $columns[0]\n"; - - if (($columns[2] ne "R128") && ($columns[2] ne "MACH64") && ($columns[2] ne "MACH32")) { - print PCICHIPSET " { PCI_CHIP_$columns[1], PCI_CHIP_$columns[1], RES_SHARED_VGA },\n"; - - print PCIDEVICEMATCH " ATI_DEVICE_MATCH( PCI_CHIP_$columns[1], 0 ),\n"; - - print AMDGPUCHIPSET " { PCI_CHIP_$columns[1], \"$columns[3]\" },\n"; - if (!$uniquechipsets{$columns[3]}) { - $uniquearray[$numunique] = $columns[3]; - $uniquechipsets{$columns[3]} = ++$numunique; - } - - print AMDGPUCHIPINFO " { $columns[0], CHIP_FAMILY_$columns[2] },\n"; - } - } - } else { - my $err = $csv->error_input; - print "Failed to parse line: $err"; - } -} - -print AMDGPUCHIPINFO "};\n"; -print AMDGPUCHIPSET " { -1, NULL }\n};\n\nSymTabRec AMDGPUUniqueChipsets[] = {\n"; -foreach (@uniquearray) { - print AMDGPUCHIPSET " { 0, \"$_\" },\n"; -} -print AMDGPUCHIPSET " { -1, NULL }\n};\n"; -print PCICHIPSET " { -1, -1, RES_UNDEFINED }\n};\n"; -print PCIDEVICEMATCH " { 0, 0, 0 }\n};\n"; -close CSV; -close ATIOUT; -close PCICHIPSET; -close PCIDEVICEMATCH; -close AMDGPUCHIPSET; -close AMDGPUCHIPINFO;