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"notes": null + }, + { + "sha": "896c9cf486182a0058deeec0036ceaca1ddd2819", + "description": "radv: remove radv_device::physical_device", + "nominated": false, + "nomination_type": 3, + "resolution": 4, + "main_sha": null, + "because_sha": null, + "notes": null + }, + { + "sha": "310597cab6efb95210ec89d5fe0046876849cb76", + "description": "radv: rename radv_physical_device::rad_info to info", + "nominated": false, + "nomination_type": 3, + "resolution": 4, + "main_sha": null, + "because_sha": null, + "notes": null + }, + { + "sha": "2686cd59dfe296d94571969a9eb870bfd271827c", + "description": "radv: rename radeon_info variables to gpu_info everywhere", + "nominated": false, + "nomination_type": 3, + "resolution": 4, + "main_sha": null, + "because_sha": null, + "notes": null + }, + { + "sha": "52663ec80fd8a4fa4fe82ea27188964740d4b319", + "description": "radv/winsys: rename gpu_info to pci_ids in the null winsys", + "nominated": false, + "nomination_type": 3, + "resolution": 4, + "main_sha": null, + "because_sha": null, + "notes": null + }, + { + "sha": "ce1c32e358cdd74497b4bfc4302c057947808df6", + "description": "radv: rename radv_physical_device variables to pdev everywhere", + "nominated": false, + "nomination_type": 3, + "resolution": 4, + "main_sha": null, + "because_sha": null, + "notes": null + }, + { + "sha": "f674fdee726ca634f1b21cd293e72ae6cd87147f", + "description": "ci: take kws farm offline", + "nominated": false, + "nomination_type": 3, + "resolution": 4, + "main_sha": null, + "because_sha": null, + "notes": null + }, + { "sha": "fcb568a5d5a52db75fa2f6d04579bb404ca7f597", "description": "docs: add alpha-to-one features for RADV", "nominated": false, @@ -7564,7 +13034,7 @@ "description": "Pass no-verify-fixpoint option to instcombine in LLVM 18", "nominated": false, "nomination_type": 3, - "resolution": 4, + "resolution": 1, "main_sha": null, "because_sha": null, "notes": null @@ -9624,7 +15094,7 @@ "description": "intel: Enable Xe KMD support by default", "nominated": false, "nomination_type": 3, - "resolution": 4, + "resolution": 1, "main_sha": null, "because_sha": null, "notes": null @@ -28564,7 +34034,7 @@ "description": "iris: Wait for drm_xe_exec_queue to be idle before destroying it", "nominated": false, "nomination_type": 3, - "resolution": 4, + "resolution": 1, "main_sha": null, "because_sha": null, "notes": null @@ -34474,7 +39944,7 @@ "description": "anv: Fix calculation of syncs required in Xe KMD", "nominated": false, "nomination_type": 3, - "resolution": 4, + "resolution": 1, "main_sha": null, "because_sha": null, "notes": null diff -Nru mesa-24.0.4+git2404011708.52549327115~n~mesarc5/VERSION mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/VERSION --- mesa-24.0.4+git2404011708.52549327115~n~mesarc5/VERSION 2024-03-27 22:11:05.000000000 +0000 +++ mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/VERSION 2024-04-14 19:01:05.000000000 +0000 @@ -1 +1 @@ -24.0.4 +24.0.5 diff -Nru mesa-24.0.4+git2404011708.52549327115~n~mesarc5/debian/changelog mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/debian/changelog --- mesa-24.0.4+git2404011708.52549327115~n~mesarc5/debian/changelog 2024-04-05 04:04:02.000000000 +0000 +++ mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/debian/changelog 2024-04-14 19:01:42.000000000 +0000 @@ -1,8 +1,54 @@ -mesa (24.0.4+git2404011708.52549327115~n~mesarc5) noble; urgency=medium +mesa (24.0.5+git2404102228.976b75c8c5f~n~mesarc5) noble; urgency=medium * Build for noble - -- Ernst Persson Fri, 05 Apr 2024 06:04:02 +0200 + -- Ernst Persson Sun, 14 Apr 2024 21:01:42 +0200 + +mesa (24.0.5+git2404102228.976b75c8c5f~f~mesarc5) focal; urgency=medium + + * New snapshot: + * 976b75c8c5f docs: add sha256sum for 24.0.5 + * 77376147202 VERSION: bump for 24.0.5 + * 4de817cee28 docs: add release notes for 24.0.5 + * 066c61c7485 intel: Enable Xe KMD support by default + * cbbf9d781ba r600: add license information to the sfn_shader_gs.h + * 4a33e47af56 r600: add license info to the r600_opcodes.h + * df4f6b54919 r600: add license header to r600_formats.h + * b1087acbcbb frontend/nine: Reset should EndScene + * 7bf97678ddb frontend/nine: Fix destruction race + * 63873590d82 frontend/nine: Fix missing light flag check + * 64b06290628 frontend/nine: Fix programmable vs check + * e1c686778a7 frontend/nine: Fix ff ps key + * ad2594ead47 nir/serialize: Encode data for temporaries + * b573f698853 driconf: add a workaround for Joe Danger + * b351969fa25 driconf: add a workaround for Joe Danger 2 + * 50669655ed4 glsl: allow out arrays in #110 with + allow_glsl_120_subset_in_110 + * dac8689fc32 anv, iris: add missing CS_STALL bit for GPGPU texture + invalidation + * c73e830dc91 svga: Fix instanced draw detection + * 5eb9128a52c etnaviv: rs: take src dimensions into account when + increasing height alignment + * a6aa5d30d7e isl: set NullPageCoherencyEnable for depth/stencil + sparse surfaces + * b3a65a18818 anv: mark descriptors & pipeline dirty after blorp + compute + * 60c8db6cd12 nvk: Add a _pad field to nvk_fs_key + * 3e9ac50d376 gallium: handle copy_image of depth textures + * 6dab9b4a6de anv: add missing data flush out of L3 for transform + feedback writes + * 45904c576d5 glsl: Use a stable attr sort for VS in / FS out + * 1971a267bc1 .pick_status.json: Update to + 2c1cb65949933a05eedb2eacc15cd893ecaef8aa + * 5681b3604a5 ci/amd: drop old PIGLIT_REPLAY_DESCRIPTION_FILE + surpassed by PIGLIT_TRACES_FILE + * 0d608f1b5bf anv: Create protected engine context when i915 supports + vm control + * a5d4638ed50 radv: make sure the heap budget is less than or equal to + the heap size + * 0deacc982bb intel/dev: Add 0x56be and 0x56bf DG2 PCI IDs + + -- Ernst Persson Sun, 14 Apr 2024 21:01:05 +0200 mesa (24.0.4+git2404011708.52549327115~f~mesarc5) focal; urgency=medium diff -Nru mesa-24.0.4+git2404011708.52549327115~n~mesarc5/docs/relnotes/24.0.5.rst mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/docs/relnotes/24.0.5.rst --- mesa-24.0.4+git2404011708.52549327115~n~mesarc5/docs/relnotes/24.0.5.rst 1970-01-01 00:00:00.000000000 +0000 +++ mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/docs/relnotes/24.0.5.rst 2024-04-14 19:01:05.000000000 +0000 @@ -0,0 +1,212 @@ +Mesa 24.0.5 Release Notes / 2024-04-10 +====================================== + +Mesa 24.0.5 is a bug fix release which fixes bugs found since the 24.0.4 release. + +Mesa 24.0.5 implements the OpenGL 4.6 API, but the version reported by +glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) / +glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used. +Some drivers don't support all the features required in OpenGL 4.6. OpenGL +4.6 is **only** available if requested at context creation. +Compatibility contexts may report a lower version depending on each driver. + +Mesa 24.0.5 implements the Vulkan 1.3 API, but the version reported by +the apiVersion property of the VkPhysicalDeviceProperties struct +depends on the particular driver being used. + +SHA256 checksum +--------------- + +:: + + 38cc245ca8faa3c69da6d2687f8906377001f63365348a62cc6f7fafb1e8c018 mesa-24.0.5.tar.xz + + +New features +------------ + +- None + + +Bug fixes +--------- + +- anv: vkd3d-proton test_stress_suballocation failure +- d3d12: Zwift renders with bad textures/lighting +- NVK: Misrendering with Civilization 6 +- radv: RDR2 might need zerovram +- Issues rendering gtk4 window decorations on v3d on Fedora-40/mesa-24.0 +- clc: Failure when linking with llvm+clang 18.1 (-Dshared-llvm=disabled) +- LLVM-18 build issue + + +Changes +------- + +Axel Davy (5): + +- frontend/nine: Fix ff ps key +- frontend/nine: Fix programmable vs check +- frontend/nine: Fix missing light flag check +- frontend/nine: Fix destruction race +- frontend/nine: Reset should EndScene + +Connor Abbott (2): + +- freedreno/a7xx: Add CP_CCHE_INVALIDATE +- tu: Implement CCHE invalidation + +Dave Airlie (1): + +- mesa: reorder st context teardown + +David Heidelberg (7): + +- r300: add missing licence to the r300_public.h +- r300: add missing copyright header +- docs: we support EGL 1.5 for a long time +- ci/amd: drop old PIGLIT_REPLAY_DESCRIPTION_FILE surpassed by PIGLIT_TRACES_FILE +- r600: add license header to r600_formats.h +- r600: add license info to the r600_opcodes.h +- r600: add license information to the sfn_shader_gs.h + +David Stern (1): + +- vulkan/wsi/x11: Explicitly discard errors from xcb_present_pixmap. + +Eric Engestrom (5): + +- docs: add sha256sum for 24.0.4 +- .pick_status.json: Update to 3d68dd78d07b30cefe90d76af681075f4ed6b33d +- .pick_status.json: Update to fcb568a5d5a52db75fa2f6d04579bb404ca7f597 +- .pick_status.json: Update to 078fe5454e97d073feb18bcdcf7ed1874e8b4835 +- .pick_status.json: Update to 2c1cb65949933a05eedb2eacc15cd893ecaef8aa + +Eric R. Smith (2): + +- panfrost: mark indirect compute buffer as read +- gallium: handle copy_image of depth textures + +Faith Ekstrand (2): + +- nvk: Add a _pad field to nvk_cbuf +- nvk: Add a _pad field to nvk_fs_key + +Georg Lehmann (2): + +- aco: don't combine mul+add_clamp to mad_clamp +- aco/ra: use SDWA for 16bit instructions when the second byte is blocked + +Iago Toral Quiroga (2): + +- v3d: implement fix for GFXH-1602 +- broadcom/compiler: fix workaround for GFXH-1602 + +Ian Romanick (3): + +- intel/brw: Clear write_accumulator flag when changing the destination +- intel/brw: Use enums for DPAS source regioning +- nir: intel/brw: Change the order of sources for nir_dpas_intel + +Jesse Natalie (1): + +- glsl: Use a stable attr sort for VS in / FS out + +Jordan Justen (1): + +- intel/dev: Add 0x56be and 0x56bf DG2 PCI IDs + +José Roberto de Souza (4): + +- anv: Fix calculation of syncs required in Xe KMD +- iris: Wait for drm_xe_exec_queue to be idle before destroying it +- anv: Create protected engine context when i915 supports vm control +- intel: Enable Xe KMD support by default + +Juston Li (1): + +- Revert "zink: store last pipeline directly for zink_gfx_program::last_pipeline" + +Karol Herbst (1): + +- meson: fix link failure with llvm-18 + +Kenneth Graunke (2): + +- intel/brw: Fix generate_mov_indirect to check has_64bit_int not float +- intel/brw: Fix lower_regioning for BROADCAST, MOV_INDIRECT on Q types + +Konstantin Seurer (1): + +- nir/serialize: Encode data for temporaries + +Lionel Landwerlin (7): + +- anv: fix protected memory allocations +- anv: disable protected content around surface state copies +- anv: disable generated draws in protected command buffers +- anv: update protection fault property +- anv: add missing data flush out of L3 for transform feedback writes +- anv: mark descriptors & pipeline dirty after blorp compute +- isl: set NullPageCoherencyEnable for depth/stencil sparse surfaces + +Lucas Stach (2): + +- etnaviv: fix depth writes without testing +- etnaviv: rs: take src dimensions into account when increasing height alignment + +Mike Blumenkrantz (12): + +- zink: only check that CUBE_COMPATIBLE for images doesn't subtract flags +- zink: don't use set_foreach_remove with dmabuf_exports +- zink: make descriptor pool creation more robust +- zink: fix shaderdb pipeline compile +- zink: don't clobber indirect array reads with missing components +- zink: fix add_derefs case for compact arrays +- llvmpipe: fix DRAW_USE_LLVM=0 +- glsl: handle xfb resources for spirv before running varying opts +- mesa: clamp binary pointer in ShaderBinary if length==0 +- glsl: set PSIZ bit in outputs_written when injecting a 1.0 psiz write +- nir/lower_clamp_color_outputs: fix use with lowered io +- nir/texcoord_replace: fix scalarized io handling + +Nikita Popov (1): + +- Pass no-verify-fixpoint option to instcombine in LLVM 18 + +Patrick Lerda (1): + +- r300: fix constants_remap_table memory leak related to the dummy shader path + +Paul Gofman (3): + +- glsl: allow out arrays in #110 with allow_glsl_120_subset_in_110 +- driconf: add a workaround for Joe Danger 2 +- driconf: add a workaround for Joe Danger + +Paulo Zanoni (2): + +- anv/xe: don't leak xe_syncs during trtt submission +- anv, iris: add missing CS_STALL bit for GPGPU texture invalidation + +Samuel Pitoiset (3): + +- radv: fix conditional rendering with mesh+task and multiview (again) +- radv: enable radv_zero_vram for Red Dead Redemption 2 +- radv: make sure the heap budget is less than or equal to the heap size + +Tapani Pälli (1): + +- anv: disable fcv optimization on >= gfx125 + +Yonggang Luo (1): + +- util: Fixes futex_wait on win32 + +Zack Rusin (1): + +- svga: Fix instanced draw detection + +Zan Dobersek (1): + +- tu: fix memory leaks in tu_shader diff -Nru mesa-24.0.4+git2404011708.52549327115~n~mesarc5/docs/relnotes.rst mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/docs/relnotes.rst --- mesa-24.0.4+git2404011708.52549327115~n~mesarc5/docs/relnotes.rst 2024-03-27 22:11:05.000000000 +0000 +++ mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/docs/relnotes.rst 2024-04-14 19:01:05.000000000 +0000 @@ -3,6 +3,7 @@ The release notes summarize what's new or changed in each Mesa release. +- :doc:`24.0.5 release notes ` - :doc:`24.0.4 release notes ` - :doc:`24.0.3 release notes ` - :doc:`24.0.2 release notes ` @@ -412,6 +413,7 @@ :maxdepth: 1 :hidden: + 24.0.5 24.0.4 24.0.3 24.0.2 diff -Nru mesa-24.0.4+git2404011708.52549327115~n~mesarc5/include/pci_ids/iris_pci_ids.h mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/include/pci_ids/iris_pci_ids.h --- mesa-24.0.4+git2404011708.52549327115~n~mesarc5/include/pci_ids/iris_pci_ids.h 2024-03-14 07:32:36.000000000 +0000 +++ mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/include/pci_ids/iris_pci_ids.h 2024-04-14 19:01:05.000000000 +0000 @@ -251,6 +251,8 @@ CHIPSET(0x56bb, dg2_g11, "DG2", "Intel(R) Graphics") CHIPSET(0x56bc, dg2_g11, "DG2", "Intel(R) Graphics") CHIPSET(0x56bd, dg2_g11, "DG2", "Intel(R) Graphics") +CHIPSET(0x56be, dg2_g10, "DG2", "Intel(R) Graphics") +CHIPSET(0x56bf, dg2_g10, "DG2", "Intel(R) Graphics") CHIPSET(0x56c0, atsm_g10, "ATS-M", "Intel(R) Data Center GPU Flex Series 170 Graphics") CHIPSET(0x56c1, atsm_g11, "ATS-M", "Intel(R) Data Center GPU Flex Series 140 Graphics") diff -Nru mesa-24.0.4+git2404011708.52549327115~n~mesarc5/meson.build mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/meson.build --- mesa-24.0.4+git2404011708.52549327115~n~mesarc5/meson.build 2024-04-05 04:03:25.000000000 +0000 +++ mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/meson.build 2024-04-14 19:01:05.000000000 +0000 @@ -1523,11 +1523,6 @@ pre_args += '-DSUPPORT_INTEL_INTEGRATED_GPUS' endif -if get_option('intel-xe-kmd').enabled() - pre_args += '-DINTEL_XE_KMD_SUPPORTED' -endif - - if with_gallium_i915 and host_machine.cpu_family().startswith('x86') == false error('Intel "i915" Gallium driver requires x86 or x86_64 CPU family') endif diff -Nru mesa-24.0.4+git2404011708.52549327115~n~mesarc5/meson_options.txt mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/meson_options.txt --- mesa-24.0.4+git2404011708.52549327115~n~mesarc5/meson_options.txt 2024-01-18 07:13:29.000000000 +0000 +++ mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/meson_options.txt 2024-04-14 19:01:05.000000000 +0000 @@ -682,11 +682,4 @@ description : 'Build custom xmlconfig (driconf) support. If disabled, ' + 'the default driconf file is hardcoded into Mesa. ' + 'Requires expat.' -) - -option ( - 'intel-xe-kmd', - type : 'feature', - value : 'disabled', - description: 'Enable Intel Xe KMD support.' -) +) \ No newline at end of file diff -Nru mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/amd/ci/gitlab-ci.yml mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/amd/ci/gitlab-ci.yml --- mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/amd/ci/gitlab-ci.yml 2024-02-26 14:45:03.000000000 +0000 +++ mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/amd/ci/gitlab-ci.yml 2024-04-14 19:01:05.000000000 +0000 @@ -46,7 +46,6 @@ variables: EGL_PLATFORM: surfaceless PIGLIT_TRACES_FILE: traces-amd.yml - PIGLIT_REPLAY_DESCRIPTION_FILE: "/install/traces-amd.yml" PIGLIT_REPLAY_EXTRA_ARGS: --keep-image radv-raven-vkcts:x86_64: diff -Nru mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/amd/compiler/aco_register_allocation.cpp mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/amd/compiler/aco_register_allocation.cpp --- mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/amd/compiler/aco_register_allocation.cpp 2024-03-14 07:32:36.000000000 +0000 +++ mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/amd/compiler/aco_register_allocation.cpp 2024-04-14 19:01:05.000000000 +0000 @@ -47,7 +47,8 @@ RegClass rc); std::pair get_subdword_definition_info(Program* program, const aco_ptr& instr, RegClass rc); -void add_subdword_definition(Program* program, aco_ptr& instr, PhysReg reg); +void add_subdword_definition(Program* program, aco_ptr& instr, PhysReg reg, + bool allow_16bit_write); struct assignment { PhysReg reg; @@ -678,7 +679,8 @@ } void -add_subdword_definition(Program* program, aco_ptr& instr, PhysReg reg) +add_subdword_definition(Program* program, aco_ptr& instr, PhysReg reg, + bool allow_16bit_write) { if (instr->isPseudo()) return; @@ -687,7 +689,7 @@ amd_gfx_level gfx_level = program->gfx_level; assert(instr->definitions[0].bytes() <= 2); - if (reg.byte() == 0 && instr_is_16bit(gfx_level, instr->opcode)) + if (reg.byte() == 0 && allow_16bit_write && instr_is_16bit(gfx_level, instr->opcode)) return; /* use SDWA */ @@ -696,6 +698,8 @@ return; } + assert(allow_16bit_write); + if (instr->opcode == aco_opcode::v_fma_mixlo_f16) { instr->opcode = aco_opcode::v_fma_mixhi_f16; return; @@ -2979,7 +2983,8 @@ PhysReg reg = get_reg(ctx, register_file, tmp, parallelcopy, instr); definition->setFixed(reg); if (reg.byte() || register_file.test(reg, 4)) { - add_subdword_definition(program, instr, reg); + bool allow_16bit_write = reg.byte() % 2 == 0 && !register_file.test(reg, 2); + add_subdword_definition(program, instr, reg, allow_16bit_write); definition = &instr->definitions[i]; /* add_subdword_definition can invalidate the reference */ } diff -Nru mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/amd/vulkan/radv_physical_device.c mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/amd/vulkan/radv_physical_device.c --- mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/amd/vulkan/radv_physical_device.c 2024-02-12 22:13:35.000000000 +0000 +++ mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/amd/vulkan/radv_physical_device.c 2024-04-14 19:01:05.000000000 +0000 @@ -2380,6 +2380,11 @@ assert(heap == memory_properties->memoryHeapCount); } + /* The heapBudget value must be less than or equal to VkMemoryHeap::size for each heap. */ + for (uint32_t i = 0; i < memory_properties->memoryHeapCount; i++) { + memoryBudget->heapBudget[i] = MIN2(memory_properties->memoryHeaps[i].size, memoryBudget->heapBudget[i]); + } + /* The heapBudget and heapUsage values must be zero for array elements * greater than or equal to * VkPhysicalDeviceMemoryProperties::memoryHeapCount. diff -Nru mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/compiler/glsl/ast_to_hir.cpp mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/compiler/glsl/ast_to_hir.cpp --- mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/compiler/glsl/ast_to_hir.cpp 2024-01-18 07:13:29.000000000 +0000 +++ mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/compiler/glsl/ast_to_hir.cpp 2024-04-14 19:01:05.000000000 +0000 @@ -6058,7 +6058,7 @@ */ if ((var->data.mode == ir_var_function_inout || var->data.mode == ir_var_function_out) && glsl_type_is_array(type) - && !state->check_version(120, 100, &loc, + && !state->check_version(state->allow_glsl_120_subset_in_110 ? 110 : 120, 100, &loc, "arrays cannot be out or inout parameters")) { type = &glsl_type_builtin_error; } diff -Nru mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/compiler/glsl/gl_nir_link_varyings.c mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/compiler/glsl/gl_nir_link_varyings.c --- mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/compiler/glsl/gl_nir_link_varyings.c 2024-01-18 07:13:29.000000000 +0000 +++ mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/compiler/glsl/gl_nir_link_varyings.c 2024-04-14 19:01:05.000000000 +0000 @@ -50,6 +50,7 @@ /* Temporary storage for the set of attributes that need locations assigned. */ struct temp_attr { unsigned slots; + unsigned original_idx; nir_variable *var; }; @@ -61,7 +62,10 @@ const struct temp_attr *const r = (const struct temp_attr *) b; /* Reversed because we want a descending order sort below. */ - return r->slots - l->slots; + if (r->slots != l->slots) + return r->slots - l->slots; + + return l->original_idx - r->original_idx; } /** @@ -1238,6 +1242,7 @@ } to_assign[num_attr].slots = slots; to_assign[num_attr].var = var; + to_assign[num_attr].original_idx = num_attr; num_attr++; } diff -Nru mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/compiler/glsl/gl_nir_linker.c mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/compiler/glsl/gl_nir_linker.c --- mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/compiler/glsl/gl_nir_linker.c 2024-01-18 07:13:29.000000000 +0000 +++ mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/compiler/glsl/gl_nir_linker.c 2024-04-14 19:01:05.000000000 +0000 @@ -921,6 +921,8 @@ nir_deref_instr *deref = nir_build_deref_var(&b, psiz); nir_store_deref(&b, deref, nir_imm_float(&b, 1.0), BITFIELD_BIT(0)); } + + nir->info.outputs_written |= VARYING_BIT_PSIZ; } static void @@ -1162,6 +1164,8 @@ if (!prelink_lowering(consts, exts, prog, linked_shader, num_shaders)) return false; + gl_nir_link_assign_xfb_resources(consts, prog); + /* Linking the stages in the opposite order (from fragment to vertex) * ensures that inter-shader outputs written to in an earlier stage * are eliminated if they are (transitively) not used in a later @@ -1191,7 +1195,6 @@ return false; gl_nir_link_assign_atomic_counter_resources(consts, prog); - gl_nir_link_assign_xfb_resources(consts, prog); return true; } diff -Nru mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/compiler/nir/nir_lower_clamp_color_outputs.c mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/compiler/nir/nir_lower_clamp_color_outputs.c --- mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/compiler/nir/nir_lower_clamp_color_outputs.c 2023-10-25 21:39:06.000000000 +0000 +++ mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/compiler/nir/nir_lower_clamp_color_outputs.c 2024-04-14 19:01:05.000000000 +0000 @@ -25,13 +25,13 @@ #include "nir_builder.h" static bool -is_color_output(nir_shader *shader, nir_variable *out) +is_color_output(nir_shader *shader, int location) { switch (shader->info.stage) { case MESA_SHADER_VERTEX: case MESA_SHADER_GEOMETRY: case MESA_SHADER_TESS_EVAL: - switch (out->data.location) { + switch (location) { case VARYING_SLOT_COL0: case VARYING_SLOT_COL1: case VARYING_SLOT_BFC0: @@ -42,8 +42,8 @@ } break; case MESA_SHADER_FRAGMENT: - return (out->data.location == FRAG_RESULT_COLOR || - out->data.location >= FRAG_RESULT_DATA0); + return (location == FRAG_RESULT_COLOR || + location >= FRAG_RESULT_DATA0); default: return false; } @@ -54,30 +54,23 @@ { nir_variable *out = NULL; nir_def *s; + int loc = -1; switch (intr->intrinsic) { case nir_intrinsic_store_deref: out = nir_intrinsic_get_var(intr, 0); + if (out->data.mode != nir_var_shader_out) + return false; + loc = out->data.location; break; case nir_intrinsic_store_output: - /* already had i/o lowered.. lookup the matching output var: */ - nir_foreach_shader_out_variable(var, shader) { - int drvloc = var->data.driver_location; - if (nir_intrinsic_base(intr) == drvloc) { - out = var; - break; - } - } - assume(out); + loc = nir_intrinsic_io_semantics(intr).location; break; default: return false; } - if (out->data.mode != nir_var_shader_out) - return false; - - if (is_color_output(shader, out)) { + if (is_color_output(shader, loc)) { b->cursor = nir_before_instr(&intr->instr); int src = intr->intrinsic == nir_intrinsic_store_deref ? 1 : 0; s = intr->src[src].ssa; diff -Nru mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/compiler/nir/nir_lower_texcoord_replace.c mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/compiler/nir/nir_lower_texcoord_replace.c --- mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/compiler/nir/nir_lower_texcoord_replace.c 2023-10-25 21:39:06.000000000 +0000 +++ mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/compiler/nir/nir_lower_texcoord_replace.c 2024-04-14 19:01:05.000000000 +0000 @@ -107,6 +107,7 @@ unsigned base = var->data.location - VARYING_SLOT_TEX0; b.cursor = nir_after_instr(instr); + uint32_t component_mask = BITFIELD_MASK(glsl_get_vector_elements(var->type)) << var->data.location_frac; nir_deref_instr *deref = nir_src_as_deref(intrin->src[0]); nir_def *index = get_io_index(&b, deref); nir_def *mask = @@ -114,7 +115,7 @@ nir_iadd_imm(&b, index, base)); nir_def *cond = nir_test_mask(&b, mask, coord_replace); - nir_def *result = nir_bcsel(&b, cond, new_coord, + nir_def *result = nir_bcsel(&b, cond, nir_channels(&b, new_coord, component_mask), &intrin->def); nir_def_rewrite_uses_after(&intrin->def, diff -Nru mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/compiler/nir/nir_serialize.c mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/compiler/nir/nir_serialize.c --- mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/compiler/nir/nir_serialize.c 2024-01-18 07:13:29.000000000 +0000 +++ mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/compiler/nir/nir_serialize.c 2024-04-14 19:01:05.000000000 +0000 @@ -202,8 +202,6 @@ enum var_data_encoding { var_encode_full, - var_encode_shader_temp, - var_encode_function_temp, var_encode_location_diff, }; @@ -264,30 +262,23 @@ data.mode != nir_var_shader_out) data.location = 0; - /* Temporary variables don't serialize var->data. */ - if (data.mode == nir_var_shader_temp) - flags.u.data_encoding = var_encode_shader_temp; - else if (data.mode == nir_var_function_temp) - flags.u.data_encoding = var_encode_function_temp; - else { - struct nir_variable_data tmp = data; - - tmp.location = ctx->last_var_data.location; - tmp.location_frac = ctx->last_var_data.location_frac; - tmp.driver_location = ctx->last_var_data.driver_location; + struct nir_variable_data tmp = data; - /* See if we can encode only the difference in locations from the last - * variable. - */ - if (memcmp(&ctx->last_var_data, &tmp, sizeof(tmp)) == 0 && - abs((int)data.location - - (int)ctx->last_var_data.location) < (1 << 12) && - abs((int)data.driver_location - - (int)ctx->last_var_data.driver_location) < (1 << 15)) - flags.u.data_encoding = var_encode_location_diff; - else - flags.u.data_encoding = var_encode_full; - } + tmp.location = ctx->last_var_data.location; + tmp.location_frac = ctx->last_var_data.location_frac; + tmp.driver_location = ctx->last_var_data.driver_location; + + /* See if we can encode only the difference in locations from the last + * variable. + */ + if (memcmp(&ctx->last_var_data, &tmp, sizeof(tmp)) == 0 && + abs((int)data.location - + (int)ctx->last_var_data.location) < (1 << 12) && + abs((int)data.driver_location - + (int)ctx->last_var_data.driver_location) < (1 << 15)) + flags.u.data_encoding = var_encode_location_diff; + else + flags.u.data_encoding = var_encode_full; flags.u.ray_query = var->data.ray_query; @@ -306,27 +297,24 @@ if (flags.u.has_name) blob_write_string(ctx->blob, var->name); - if (flags.u.data_encoding == var_encode_full || - flags.u.data_encoding == var_encode_location_diff) { - if (flags.u.data_encoding == var_encode_full) { - blob_write_bytes(ctx->blob, &data, sizeof(data)); - } else { - /* Serialize only the difference in locations from the last variable. - */ - union packed_var_data_diff diff; - - diff.u.location = data.location - ctx->last_var_data.location; - diff.u.location_frac = data.location_frac - - ctx->last_var_data.location_frac; - diff.u.driver_location = data.driver_location - - ctx->last_var_data.driver_location; + if (flags.u.data_encoding == var_encode_full) { + blob_write_bytes(ctx->blob, &data, sizeof(data)); + } else { + /* Serialize only the difference in locations from the last variable. + */ + union packed_var_data_diff diff; - blob_write_uint32(ctx->blob, diff.u32); - } + diff.u.location = data.location - ctx->last_var_data.location; + diff.u.location_frac = data.location_frac - + ctx->last_var_data.location_frac; + diff.u.driver_location = data.driver_location - + ctx->last_var_data.driver_location; - ctx->last_var_data = data; + blob_write_uint32(ctx->blob, diff.u32); } + ctx->last_var_data = data; + for (unsigned i = 0; i < var->num_state_slots; i++) { blob_write_bytes(ctx->blob, &var->state_slots[i], sizeof(var->state_slots[i])); @@ -374,11 +362,7 @@ var->name = NULL; } - if (flags.u.data_encoding == var_encode_shader_temp) - var->data.mode = nir_var_shader_temp; - else if (flags.u.data_encoding == var_encode_function_temp) - var->data.mode = nir_var_function_temp; - else if (flags.u.data_encoding == var_encode_full) { + if (flags.u.data_encoding == var_encode_full) { blob_copy_bytes(ctx->blob, (uint8_t *)&var->data, sizeof(var->data)); ctx->last_var_data = var->data; } else { /* var_encode_location_diff */ diff -Nru mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/freedreno/.gitlab-ci/reference/afuc_test.asm mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/freedreno/.gitlab-ci/reference/afuc_test.asm --- mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/freedreno/.gitlab-ci/reference/afuc_test.asm 2024-01-18 07:13:29.000000000 +0000 +++ mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/freedreno/.gitlab-ci/reference/afuc_test.asm 2024-04-14 19:01:05.000000000 +0000 @@ -162,7 +162,6 @@ CP_BLIT: CP_BOOTSTRAP_UCODE: CP_COND_EXEC: -CP_COND_INDIRECT_BUFFER_PFE: CP_COND_REG_EXEC: CP_COND_WRITE5: CP_CONTEXT_REG_BUNCH: @@ -268,6 +267,7 @@ UNKN32: UNKN48: UNKN5: +UNKN58: UNKN6: UNKN7: UNKN73: diff -Nru mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/freedreno/.gitlab-ci/traces/afuc_test.asm mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/freedreno/.gitlab-ci/traces/afuc_test.asm --- mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/freedreno/.gitlab-ci/traces/afuc_test.asm 2024-01-18 07:13:29.000000000 +0000 +++ mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/freedreno/.gitlab-ci/traces/afuc_test.asm 2024-04-14 19:01:05.000000000 +0000 @@ -269,7 +269,7 @@ CP_INDIRECT_BUFFER_PFD: CP_DRAW_INDX_OFFSET: CP_REG_TEST: -CP_COND_INDIRECT_BUFFER_PFE: +UNKN58: CP_INVALIDATE_STATE: CP_WAIT_REG_MEM: CP_REG_TO_MEM: diff -Nru mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/freedreno/registers/adreno/adreno_pm4.xml mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/freedreno/registers/adreno/adreno_pm4.xml --- mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/freedreno/registers/adreno/adreno_pm4.xml 2024-01-18 07:13:29.000000000 +0000 +++ mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/freedreno/registers/adreno/adreno_pm4.xml 2024-04-14 19:01:05.000000000 +0000 @@ -371,7 +371,7 @@ Conditionally load a IB based on a flag, prefetch enabled - + Conditionally load a IB based on a flag, prefetch disabled Load a buffer with pre-fetch enabled @@ -648,6 +648,9 @@ Reset various on-chip state used for synchronization + + Invalidates the "CCHE" introduced on a740 + diff -Nru mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/freedreno/vulkan/tu_cmd_buffer.cc mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/freedreno/vulkan/tu_cmd_buffer.cc --- mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/freedreno/vulkan/tu_cmd_buffer.cc 2024-03-14 07:32:36.000000000 +0000 +++ mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/freedreno/vulkan/tu_cmd_buffer.cc 2024-04-14 19:01:05.000000000 +0000 @@ -187,6 +187,10 @@ .gfx_bindless = CHIP == A6XX ? 0x1f : 0xff, )); } + if (CHIP >= A7XX && (flushes & TU_CMD_FLAG_CCHE_INVALIDATE) && + /* Invalidating UCHE seems to also invalidate CCHE */ + !(flushes & TU_CMD_FLAG_CACHE_INVALIDATE)) + tu_cs_emit_pkt7(cs, CP_CCHE_INVALIDATE, 0); if (flushes & TU_CMD_FLAG_WAIT_MEM_WRITES) tu_cs_emit_pkt7(cs, CP_WAIT_MEM_WRITES, 0); if (flushes & TU_CMD_FLAG_WAIT_FOR_IDLE) @@ -3246,6 +3250,13 @@ flush_bits |= TU_CMD_FLAG_BINDLESS_DESCRIPTOR_INVALIDATE; } + /* There are multiple incoherent copies of CCHE, so any read through it may + * require invalidating it and we cannot optimize away invalidates. + */ + if (dst_mask & TU_ACCESS_CCHE_READ) { + flush_bits |= TU_CMD_FLAG_CCHE_INVALIDATE; + } + #undef DST_INCOHERENT_FLUSH cache->flush_bits |= flush_bits; @@ -3347,12 +3358,13 @@ VK_PIPELINE_STAGE_2_VERTEX_INPUT_BIT | VK_PIPELINE_STAGE_2_VERTEX_ATTRIBUTE_INPUT_BIT | SHADER_STAGES)) - mask |= TU_ACCESS_UCHE_READ; + mask |= TU_ACCESS_UCHE_READ | TU_ACCESS_CCHE_READ; if (gfx_read_access(flags, stages, VK_ACCESS_2_DESCRIPTOR_BUFFER_READ_BIT_EXT, SHADER_STAGES)) { - mask |= TU_ACCESS_UCHE_READ | TU_ACCESS_BINDLESS_DESCRIPTOR_READ; + mask |= TU_ACCESS_UCHE_READ | TU_ACCESS_BINDLESS_DESCRIPTOR_READ | + TU_ACCESS_CCHE_READ; } if (gfx_write_access(flags, stages, diff -Nru mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/freedreno/vulkan/tu_cmd_buffer.h mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/freedreno/vulkan/tu_cmd_buffer.h --- mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/freedreno/vulkan/tu_cmd_buffer.h 2024-03-02 08:16:57.000000000 +0000 +++ mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/freedreno/vulkan/tu_cmd_buffer.h 2024-04-14 19:01:05.000000000 +0000 @@ -132,6 +132,13 @@ */ TU_ACCESS_BINDLESS_DESCRIPTOR_READ = 1 << 13, + /* The CCHE is a write-through cache which sits behind UCHE, with multiple + * incoherent copies. Because it's write-through we only have to worry + * about invalidating it for reads. It's invalidated by "ccinv" in the + * shader and CP_CCHE_INVALIDATE in the command stream. + */ + TU_ACCESS_CCHE_READ = 1 << 16, + TU_ACCESS_READ = TU_ACCESS_UCHE_READ | TU_ACCESS_CCU_COLOR_READ | @@ -139,7 +146,8 @@ TU_ACCESS_CCU_COLOR_INCOHERENT_READ | TU_ACCESS_CCU_DEPTH_INCOHERENT_READ | TU_ACCESS_SYSMEM_READ | - TU_ACCESS_BINDLESS_DESCRIPTOR_READ, + TU_ACCESS_BINDLESS_DESCRIPTOR_READ | + TU_ACCESS_CCHE_READ, TU_ACCESS_WRITE = TU_ACCESS_UCHE_WRITE | @@ -186,10 +194,11 @@ TU_CMD_FLAG_CCU_INVALIDATE_COLOR = 1 << 3, TU_CMD_FLAG_CACHE_FLUSH = 1 << 4, TU_CMD_FLAG_CACHE_INVALIDATE = 1 << 5, - TU_CMD_FLAG_WAIT_MEM_WRITES = 1 << 6, - TU_CMD_FLAG_WAIT_FOR_IDLE = 1 << 7, - TU_CMD_FLAG_WAIT_FOR_ME = 1 << 8, - TU_CMD_FLAG_BINDLESS_DESCRIPTOR_INVALIDATE = 1 << 9, + TU_CMD_FLAG_CCHE_INVALIDATE = 1 << 6, + TU_CMD_FLAG_WAIT_MEM_WRITES = 1 << 7, + TU_CMD_FLAG_WAIT_FOR_IDLE = 1 << 8, + TU_CMD_FLAG_WAIT_FOR_ME = 1 << 9, + TU_CMD_FLAG_BINDLESS_DESCRIPTOR_INVALIDATE = 1 << 10, TU_CMD_FLAG_ALL_FLUSH = TU_CMD_FLAG_CCU_FLUSH_DEPTH | @@ -205,6 +214,7 @@ TU_CMD_FLAG_CCU_INVALIDATE_COLOR | TU_CMD_FLAG_CACHE_INVALIDATE | TU_CMD_FLAG_BINDLESS_DESCRIPTOR_INVALIDATE | + TU_CMD_FLAG_CCHE_INVALIDATE | /* Treat CP_WAIT_FOR_ME as a "cache" that needs to be invalidated when a * a command that needs CP_WAIT_FOR_ME is executed. This means we may * insert an extra WAIT_FOR_ME before an indirect command requiring it diff -Nru mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/gallium/auxiliary/gallivm/lp_bld_init.c mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/gallium/auxiliary/gallivm/lp_bld_init.c --- mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/gallium/auxiliary/gallivm/lp_bld_init.c 2023-07-19 22:22:16.000000000 +0000 +++ mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/gallium/auxiliary/gallivm/lp_bld_init.c 2024-04-14 19:01:05.000000000 +0000 @@ -609,7 +609,11 @@ LLVMRunPasses(gallivm->module, passes, LLVMGetExecutionEngineTargetMachine(gallivm->engine), opts); if (!(gallivm_perf & GALLIVM_PERF_NO_OPT)) +#if LLVM_VERSION_MAJOR >= 18 + strcpy(passes, "sroa,early-cse,simplifycfg,reassociate,mem2reg,instsimplify,instcombine"); +#else strcpy(passes, "sroa,early-cse,simplifycfg,reassociate,mem2reg,instsimplify,instcombine"); +#endif else strcpy(passes, "mem2reg"); diff -Nru mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/gallium/drivers/etnaviv/etnaviv_rs.c mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/gallium/drivers/etnaviv/etnaviv_rs.c --- mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/gallium/drivers/etnaviv/etnaviv_rs.c 2024-01-18 07:13:29.000000000 +0000 +++ mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/gallium/drivers/etnaviv/etnaviv_rs.c 2024-04-14 19:01:05.000000000 +0000 @@ -711,12 +711,17 @@ width = align(width, w_align); if (height & (h_align - 1) && height >= src_lev->height * src_yscale && height >= dst_lev->height) { - if (!ctx->screen->specs.single_buffer && - align(height, h_align * ctx->screen->specs.pixel_pipes) <= - dst_lev->padded_height * src_yscale) - height = align(height, h_align * ctx->screen->specs.pixel_pipes); - else - height = align(height, h_align); + height = align(height, h_align); + + /* Try to increase alignment to multi-pipe requirements to unlock + * multi-pipe resolve for increased performance. */ + if (!ctx->screen->specs.single_buffer) { + unsigned int pipe_align = align(height, h_align * ctx->screen->specs.pixel_pipes); + + if (pipe_align <= src_lev->padded_height && + pipe_align <= dst_lev->padded_height * src_yscale) + height = pipe_align; + } } /* The padded dimensions are in samples */ diff -Nru mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/gallium/drivers/iris/iris_batch.c mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/gallium/drivers/iris/iris_batch.c --- mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/gallium/drivers/iris/iris_batch.c 2024-01-18 07:13:29.000000000 +0000 +++ mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/gallium/drivers/iris/iris_batch.c 2024-04-14 19:01:05.000000000 +0000 @@ -862,8 +862,8 @@ return names[name]; } -static inline bool -context_or_exec_queue_was_banned(struct iris_bufmgr *bufmgr, int ret) +bool +iris_batch_is_banned(struct iris_bufmgr *bufmgr, int ret) { enum intel_kmd_type kmd_type = iris_bufmgr_get_device_info(bufmgr)->kmd_type; @@ -960,7 +960,7 @@ * has been lost and needs to be re-initialized. If this succeeds, * dubiously claim success... */ - if (ret && context_or_exec_queue_was_banned(bufmgr, ret)) { + if (ret && iris_batch_is_banned(bufmgr, ret)) { enum pipe_reset_status status = iris_batch_check_for_reset(batch); if (status != PIPE_NO_RESET || ice->context_reset_signaled) diff -Nru mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/gallium/drivers/iris/iris_batch.h mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/gallium/drivers/iris/iris_batch.h --- mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/gallium/drivers/iris/iris_batch.h 2024-01-18 07:13:29.000000000 +0000 +++ mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/gallium/drivers/iris/iris_batch.h 2024-04-14 19:01:05.000000000 +0000 @@ -446,6 +446,9 @@ const char * iris_batch_name_to_string(enum iris_batch_name name); +bool +iris_batch_is_banned(struct iris_bufmgr *bufmgr, int ret); + #define iris_foreach_batch(ice, batch) \ for (struct iris_batch *batch = &ice->batches[0]; \ batch <= &ice->batches[((struct iris_screen *)ice->ctx.screen)->devinfo->ver >= 12 ? IRIS_BATCH_BLITTER : IRIS_BATCH_COMPUTE]; \ diff -Nru mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/gallium/drivers/iris/iris_state.c mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/gallium/drivers/iris/iris_state.c --- mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/gallium/drivers/iris/iris_state.c 2024-03-14 07:32:36.000000000 +0000 +++ mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/gallium/drivers/iris/iris_state.c 2024-04-14 19:01:05.000000000 +0000 @@ -9537,10 +9537,12 @@ /* "GPGPU specific workarounds" (both post-sync and flush) ------------ */ if (IS_COMPUTE_PIPELINE(batch)) { - if ((GFX_VER == 9 || GFX_VER == 11) && - (flags & PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE)) { - /* Project: SKL, ICL / Argument: Tex Invalidate - * "Requires stall bit ([20] of DW) set for all GPGPU Workloads." + if (GFX_VER >= 9 && (flags & PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE)) { + /* SKL PRMs, Volume 7: 3D-Media-GPGPU, Programming Restrictions for + * PIPE_CONTROL, Flush Types: + * "Requires stall bit ([20] of DW) set for all GPGPU Workloads." + * For newer platforms this is documented in the PIPE_CONTROL + * instruction page. */ flags |= PIPE_CONTROL_CS_STALL; } diff -Nru mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/gallium/drivers/iris/xe/iris_batch.c mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/gallium/drivers/iris/xe/iris_batch.c --- mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/gallium/drivers/iris/xe/iris_batch.c 2024-01-18 07:13:29.000000000 +0000 +++ mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/gallium/drivers/iris/xe/iris_batch.c 2024-04-14 19:01:05.000000000 +0000 @@ -151,7 +151,45 @@ free(engines_info); } -void iris_xe_destroy_batch(struct iris_batch *batch) +/* + * Wait for all previous DRM_IOCTL_XE_EXEC calls over the + * drm_xe_exec_queue in this iris_batch to complete. + **/ +static void +iris_xe_wait_exec_queue_idle(struct iris_batch *batch) +{ + struct iris_bufmgr *bufmgr = batch->screen->bufmgr; + struct iris_syncobj *syncobj = iris_create_syncobj(bufmgr); + struct drm_xe_sync xe_sync = { + .type = DRM_XE_SYNC_TYPE_SYNCOBJ, + .flags = DRM_XE_SYNC_FLAG_SIGNAL, + }; + struct drm_xe_exec exec = { + .exec_queue_id = batch->xe.exec_queue_id, + .num_syncs = 1, + .syncs = (uintptr_t)&xe_sync, + }; + int ret; + + if (!syncobj) + return; + + xe_sync.handle = syncobj->handle; + /* Using the special exec.num_batch_buffer == 0 handling to get syncobj + * signaled when the last DRM_IOCTL_XE_EXEC is completed. + */ + ret = intel_ioctl(iris_bufmgr_get_fd(bufmgr), DRM_IOCTL_XE_EXEC, &exec); + if (ret == 0) { + assert(iris_wait_syncobj(bufmgr, syncobj, INT64_MAX)); + } else { + assert(iris_batch_is_banned(bufmgr, errno) == true); + } + + iris_syncobj_destroy(bufmgr, syncobj); +} + +static void +iris_xe_destroy_exec_queue(struct iris_batch *batch) { struct iris_screen *screen = batch->screen; struct iris_bufmgr *bufmgr = screen->bufmgr; @@ -165,6 +203,15 @@ assert(ret == 0); } +void iris_xe_destroy_batch(struct iris_batch *batch) +{ + /* Xe KMD don't refcount anything, so resources could be freed while they + * are still in use if we don't wait for exec_queue to be idle. + */ + iris_xe_wait_exec_queue_idle(batch); + iris_xe_destroy_exec_queue(batch); +} + bool iris_xe_replace_batch(struct iris_batch *batch) { enum intel_engine_class engine_classes[IRIS_BATCH_COUNT]; @@ -184,7 +231,7 @@ ret = iris_xe_init_batch(bufmgr, engines_info, engine_classes[batch->name], ice->priority, &new_exec_queue_id); if (ret) { - iris_xe_destroy_batch(batch); + iris_xe_destroy_exec_queue(batch); batch->xe.exec_queue_id = new_exec_queue_id; iris_lost_context_state(batch); } diff -Nru mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/gallium/drivers/llvmpipe/lp_screen.c mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/gallium/drivers/llvmpipe/lp_screen.c --- mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/gallium/drivers/llvmpipe/lp_screen.c 2024-01-31 06:30:04.000000000 +0000 +++ mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/gallium/drivers/llvmpipe/lp_screen.c 2024-04-14 19:01:05.000000000 +0000 @@ -410,6 +410,11 @@ return PIPE_MAX_SHADER_SAMPLER_VIEWS; else return 0; + case PIPE_SHADER_CAP_MAX_CONST_BUFFERS: + if (debug_get_bool_option("DRAW_USE_LLVM", false)) + return LP_MAX_TGSI_CONST_BUFFERS; + else + return draw_get_shader_param(shader, param); default: return draw_get_shader_param(shader, param); } diff -Nru mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/gallium/drivers/panfrost/pan_cmdstream.c mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/gallium/drivers/panfrost/pan_cmdstream.c --- mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/gallium/drivers/panfrost/pan_cmdstream.c 2024-01-31 06:30:04.000000000 +0000 +++ mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/gallium/drivers/panfrost/pan_cmdstream.c 2024-04-14 19:01:05.000000000 +0000 @@ -3021,6 +3021,11 @@ mali_ptr saved_tls = batch->tls.gpu; batch->tls.gpu = panfrost_emit_shared_memory(batch, info); + /* if indirect, mark the indirect buffer as being read */ + if (info->indirect) + panfrost_batch_read_rsrc(batch, pan_resource(info->indirect), PIPE_SHADER_COMPUTE); + + /* launch it */ JOBX(launch_grid)(batch, info); batch->compute_count++; batch->tls.gpu = saved_tls; diff -Nru mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/gallium/drivers/r300/r300_fs.c mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/gallium/drivers/r300/r300_fs.c --- mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/gallium/drivers/r300/r300_fs.c 2024-03-02 08:16:57.000000000 +0000 +++ mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/gallium/drivers/r300/r300_fs.c 2024-04-14 19:01:05.000000000 +0000 @@ -526,6 +526,7 @@ } free(compiler.code->constants.Constants); + free(compiler.code->constants_remap_table); rc_destroy(&compiler.Base); r300_dummy_fragment_shader(r300, shader); return; diff -Nru mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/gallium/drivers/r600/r600_formats.h mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/gallium/drivers/r600/r600_formats.h --- mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/gallium/drivers/r600/r600_formats.h 2023-10-25 21:39:07.000000000 +0000 +++ mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/gallium/drivers/r600/r600_formats.h 2024-04-14 19:01:05.000000000 +0000 @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: MIT #ifndef R600_FORMATS_H #define R600_FORMATS_H diff -Nru mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/gallium/drivers/r600/r600_opcodes.h mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/gallium/drivers/r600/r600_opcodes.h --- mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/gallium/drivers/r600/r600_opcodes.h 2022-08-07 11:40:03.000000000 +0000 +++ mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/gallium/drivers/r600/r600_opcodes.h 2024-04-14 19:01:05.000000000 +0000 @@ -1,4 +1,4 @@ - +// SPDX-License-Identifier: MIT #ifndef R600_OPCODES_H #define R600_OPCODES_H diff -Nru mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/gallium/drivers/r600/sfn/sfn_shader_gs.h mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/gallium/drivers/r600/sfn/sfn_shader_gs.h --- mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/gallium/drivers/r600/sfn/sfn_shader_gs.h 2022-11-04 18:33:21.000000000 +0000 +++ mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/gallium/drivers/r600/sfn/sfn_shader_gs.h 2024-04-14 19:01:05.000000000 +0000 @@ -1,3 +1,9 @@ +/* + * Copyright 2021 Collabora LTD + * Author: Gert Wollny + * SPDX-License-Identifier: MIT + */ + #ifndef SFN_GEOMETRYSHADER_H #define SFN_GEOMETRYSHADER_H diff -Nru mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/gallium/drivers/svga/svga_draw.c mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/gallium/drivers/svga/svga_draw.c --- mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/gallium/drivers/svga/svga_draw.c 2023-10-25 21:39:07.000000000 +0000 +++ mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/gallium/drivers/svga/svga_draw.c 2024-04-14 19:01:05.000000000 +0000 @@ -1006,6 +1006,7 @@ struct svga_context *svga = hwtnl->svga; struct svga_winsys_surface *indirect_handle; enum pipe_error ret; + bool is_instanced_draw = instance_count > 1 || start_instance > 0; assert(svga_have_vgpu10(svga)); assert(hwtnl->cmd.prim_count == 0); @@ -1096,7 +1097,7 @@ indirect_handle, indirect->offset); } - else if (instance_count > 1) { + else if (is_instanced_draw) { ret = SVGA3D_vgpu10_DrawIndexedInstanced(svga->swc, vcount, instance_count, @@ -1139,7 +1140,7 @@ indirect_handle, indirect->offset); } - else if (instance_count > 1) { + else if (is_instanced_draw) { ret = SVGA3D_vgpu10_DrawInstanced(svga->swc, vcount, instance_count, diff -Nru mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/gallium/drivers/zink/ci/zink-anv-tgl-fails.txt mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/gallium/drivers/zink/ci/zink-anv-tgl-fails.txt --- mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/gallium/drivers/zink/ci/zink-anv-tgl-fails.txt 2024-03-27 22:11:05.000000000 +0000 +++ mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/gallium/drivers/zink/ci/zink-anv-tgl-fails.txt 2024-04-14 19:01:05.000000000 +0000 @@ -526,10 +526,6 @@ spec@arb_shader_image_load_store@early-z,Fail spec@arb_shader_image_load_store@early-z@occlusion query test/early-z pass,Fail -spec@arb_shader_image_load_store@host-mem-barrier,Fail -spec@arb_shader_image_load_store@host-mem-barrier@Transform feedback/WaW/one bit barrier test/16x16,Fail -spec@arb_shader_image_load_store@host-mem-barrier@Transform feedback/WaW/one bit barrier test/4x4,Fail -spec@arb_shader_image_load_store@host-mem-barrier@Transform feedback/WaW/one bit barrier test/64x64,Fail spec@arb_shader_texture_lod@execution@arb_shader_texture_lod-texgradcube,Fail diff -Nru mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/gallium/drivers/zink/zink_batch.c mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/gallium/drivers/zink/zink_batch.c --- mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/gallium/drivers/zink/zink_batch.c 2024-02-26 14:45:03.000000000 +0000 +++ mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/gallium/drivers/zink/zink_batch.c 2024-04-14 19:01:05.000000000 +0000 @@ -757,7 +757,7 @@ unsigned i = 0; VkSemaphore *sem = bs->signal_semaphores.data; - set_foreach_remove(&bs->dmabuf_exports, entry) { + set_foreach(&bs->dmabuf_exports, entry) { struct zink_resource *res = (void*)entry->key; for (; res; res = zink_resource(res->base.b.next)) zink_screen_import_dmabuf_semaphore(screen, res, sem[i++]); @@ -765,6 +765,7 @@ struct pipe_resource *pres = (void*)entry->key; pipe_resource_reference(&pres, NULL); } + _mesa_set_clear(&bs->dmabuf_exports, NULL); bs->usage.submit_count++; end: diff -Nru mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/gallium/drivers/zink/zink_compiler.c mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/gallium/drivers/zink/zink_compiler.c --- mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/gallium/drivers/zink/zink_compiler.c 2024-03-27 22:11:05.000000000 +0000 +++ mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/gallium/drivers/zink/zink_compiler.c 2024-04-14 19:01:05.000000000 +0000 @@ -2671,13 +2671,11 @@ if (intr->def.bit_size == 64) num_components *= 2; nir_src *src_offset = nir_get_io_offset_src(intr); - if (nir_src_is_const(*src_offset)) { - unsigned slot_offset = nir_src_as_uint(*src_offset); - if (s.location + slot_offset != wc->slot) - return false; - } else if (s.location > wc->slot || s.location + s.num_slots <= wc->slot) { + if (!nir_src_is_const(*src_offset)) + return false; + unsigned slot_offset = nir_src_as_uint(*src_offset); + if (s.location + slot_offset != wc->slot) return false; - } uint32_t readmask = BITFIELD_MASK(intr->num_components) << c; if (intr->def.bit_size == 64) readmask |= readmask << (intr->num_components + c); @@ -3633,6 +3631,8 @@ bool is_interp = false; if (!filter_io_instr(intr, &is_load, &is_input, &is_interp)) return false; + bool is_special_io = (b->shader->info.stage == MESA_SHADER_VERTEX && is_input) || + (b->shader->info.stage == MESA_SHADER_FRAGMENT && !is_input); unsigned loc = nir_intrinsic_io_semantics(intr).location; nir_src *src_offset = nir_get_io_offset_src(intr); const unsigned slot_offset = src_offset && nir_src_is_const(*src_offset) ? nir_src_as_uint(*src_offset) : 0; @@ -3661,9 +3661,8 @@ bool is_struct = glsl_type_is_struct(glsl_without_array(type)); if (is_struct) size = get_slot_components(var, var->data.location + slot_offset, var->data.location); - else if ((var->data.mode == nir_var_shader_out && var->data.location < VARYING_SLOT_VAR0) || - (var->data.mode == nir_var_shader_in && var->data.location < (b->shader->info.stage == MESA_SHADER_VERTEX ? VERT_ATTRIB_GENERIC0 : VARYING_SLOT_VAR0))) - size = glsl_type_is_array(type) ? glsl_get_aoa_size(type) : glsl_get_vector_elements(type); + else if (!is_special_io && var->data.compact) + size = glsl_get_aoa_size(type); else size = glsl_get_vector_elements(glsl_without_array(type)); assert(size); diff -Nru mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/gallium/drivers/zink/zink_descriptors.c mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/gallium/drivers/zink/zink_descriptors.c --- mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/gallium/drivers/zink/zink_descriptors.c 2024-03-14 07:32:36.000000000 +0000 +++ mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/gallium/drivers/zink/zink_descriptors.c 2024-04-14 19:01:05.000000000 +0000 @@ -825,11 +825,14 @@ dpci.poolSizeCount = num_type_sizes; dpci.flags = flags; dpci.maxSets = MAX_LAZY_DESCRIPTORS; - VkResult result = VKSCR(CreateDescriptorPool)(screen->dev, &dpci, 0, &pool); - if (result != VK_SUCCESS) { - mesa_loge("ZINK: vkCreateDescriptorPool failed (%s)", vk_Result_to_str(result)); - return VK_NULL_HANDLE; - } + VkResult result; + VRAM_ALLOC_LOOP(result, + VKSCR(CreateDescriptorPool)(screen->dev, &dpci, 0, &pool), + if (result != VK_SUCCESS) { + mesa_loge("ZINK: vkCreateDescriptorPool failed (%s)", vk_Result_to_str(result)); + return VK_NULL_HANDLE; + } + ); return pool; } diff -Nru mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/gallium/drivers/zink/zink_pipeline.c mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/gallium/drivers/zink/zink_pipeline.c --- mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/gallium/drivers/zink/zink_pipeline.c 2024-01-18 07:13:30.000000000 +0000 +++ mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/gallium/drivers/zink/zink_pipeline.c 2024-04-14 19:01:05.000000000 +0000 @@ -273,7 +273,7 @@ if (screen->info.have_EXT_color_write_enable) dynamicStateEnables[state_count++] = VK_DYNAMIC_STATE_COLOR_WRITE_ENABLE_EXT; - assert(state->rast_prim != MESA_PRIM_COUNT); + assert(state->rast_prim != MESA_PRIM_COUNT || zink_debug & ZINK_DEBUG_SHADERDB); VkPipelineRasterizationLineStateCreateInfoEXT rast_line_state; if (screen->info.have_EXT_line_rasterization && diff -Nru mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/gallium/frontends/nine/device9.c mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/gallium/frontends/nine/device9.c --- mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/gallium/frontends/nine/device9.c 2023-10-25 21:39:07.000000000 +0000 +++ mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/gallium/frontends/nine/device9.c 2024-04-14 19:01:05.000000000 +0000 @@ -1062,6 +1062,7 @@ /* XXX: better use GetBackBuffer here ? */ This->device_needs_reset = (hr != D3D_OK); + This->in_scene = FALSE; /* Not sure if should be done also for ResetEx */ return hr; } diff -Nru mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/gallium/frontends/nine/iunknown.c mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/gallium/frontends/nine/iunknown.c --- mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/gallium/frontends/nine/iunknown.c 2023-07-19 22:22:16.000000000 +0000 +++ mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/gallium/frontends/nine/iunknown.c 2024-04-14 19:01:05.000000000 +0000 @@ -48,6 +48,7 @@ This->forward = false; This->bind = 0; } + This->has_bind_or_refs = This->bind + This->refs; This->container = pParams->container; This->device = pParams->device; @@ -119,6 +120,7 @@ r = p_atomic_inc_return(&This->refs); if (r == 1) { + p_atomic_inc(&This->has_bind_or_refs); if (This->device) NineUnknown_AddRef(NineUnknown(This->device)); } @@ -142,9 +144,11 @@ if (r == 0) { struct NineDevice9 *device = This->device; + UINT b_or_ref = p_atomic_dec_return(&This->has_bind_or_refs); /* Containers (here with !forward) take care of item destruction */ - if (!This->container && This->bind == 0) { + if (!This->container && b_or_ref == 0) { + assert(p_atomic_read(&This->bind) == 0); This->dtor(This); } if (device) { @@ -166,8 +170,10 @@ if (r == 0) { struct NineDevice9 *device = This->device; + UINT b_or_ref = p_atomic_dec_return(&This->has_bind_or_refs); /* Containers (here with !forward) take care of item destruction */ - if (!This->container && This->bind == 0) { + if (!This->container && b_or_ref == 0) { + assert(p_atomic_read(&This->bind) == 0); NineLockGlobalMutex(); This->dtor(This); NineUnlockGlobalMutex(); diff -Nru mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/gallium/frontends/nine/iunknown.h mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/gallium/frontends/nine/iunknown.h --- mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/gallium/frontends/nine/iunknown.h 2023-07-19 22:22:16.000000000 +0000 +++ mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/gallium/frontends/nine/iunknown.h 2024-04-14 19:01:05.000000000 +0000 @@ -47,6 +47,7 @@ int32_t refs; /* external reference count */ int32_t bind; /* internal bind count */ + int32_t has_bind_or_refs; /* 0 if no ref, 1 if bind or ref, 2 if both */ bool forward; /* whether to forward references to the container */ /* container: for surfaces and volumes only. @@ -130,7 +131,7 @@ static inline void NineUnknown_Destroy( struct NineUnknown *This ) { - assert(!(This->refs | This->bind)); + assert(!(This->refs | This->bind) && !This->has_bind_or_refs); This->dtor(This); } @@ -140,6 +141,8 @@ UINT b = p_atomic_inc_return(&This->bind); assert(b); + if (b == 1) + p_atomic_inc(&This->has_bind_or_refs); if (b == 1 && This->forward) NineUnknown_Bind(This->container); @@ -150,10 +153,13 @@ NineUnknown_Unbind( struct NineUnknown *This ) { UINT b = p_atomic_dec_return(&This->bind); + UINT b_or_ref = 1; + if (b == 0) + b_or_ref = p_atomic_dec_return(&This->has_bind_or_refs); if (b == 0 && This->forward) NineUnknown_Unbind(This->container); - else if (b == 0 && This->refs == 0 && !This->container) + else if (b_or_ref == 0 && !This->container) This->dtor(This); return b; @@ -173,7 +179,7 @@ assert(This->container && !This->forward); This->container = NULL; - if (!(This->refs | This->bind)) + if (!(This->has_bind_or_refs)) This->dtor(This); } diff -Nru mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/gallium/frontends/nine/nine_ff.c mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/gallium/frontends/nine/nine_ff.c --- mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/gallium/frontends/nine/nine_ff.c 2023-07-19 22:22:16.000000000 +0000 +++ mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/gallium/frontends/nine/nine_ff.c 2024-04-14 19:01:05.000000000 +0000 @@ -1953,7 +1953,7 @@ dst[19].z = dst[25].z * mtl->Ambient.b + mtl->Emissive.b; } - if (!(context->changed.group & NINE_STATE_FF_LIGHTING)) + if (!(context->changed.group & NINE_STATE_FF_LIGHTING) && !IS_D3DTS_DIRTY(context, VIEW)) return; for (l = 0; l < context->ff.num_lights_active; ++l) { diff -Nru mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/gallium/frontends/nine/nine_ff.h mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/gallium/frontends/nine/nine_ff.h --- mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/gallium/frontends/nine/nine_ff.h 2023-07-19 22:22:16.000000000 +0000 +++ mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/gallium/frontends/nine/nine_ff.h 2024-04-14 19:01:05.000000000 +0000 @@ -83,20 +83,21 @@ for (s = 0; s < num_stages; ++s) { unsigned gen = (context->ff.tex_stage[s][D3DTSS_TEXCOORDINDEX] >> 16) + 1; unsigned dim = context->ff.tex_stage[s][D3DTSS_TEXTURETRANSFORMFLAGS] & 0x7; + unsigned idx = context->ff.tex_stage[s][D3DTSS_TEXCOORDINDEX] & 7; unsigned proj = !!(context->ff.tex_stage[s][D3DTSS_TEXTURETRANSFORMFLAGS] & D3DTTFF_PROJECTED); - if (!context->vs) { + if (!context->programmable_vs) { if (dim > 4) - dim = input_texture_coord[s]; + dim = input_texture_coord[idx]; if (!dim && gen == NINED3DTSS_TCI_PASSTHRU) - dim = input_texture_coord[s]; + dim = input_texture_coord[idx]; else if (!dim) dim = 4; if (dim == 1) /* NV behaviour */ proj = 0; - if (dim > input_texture_coord[s] && gen == NINED3DTSS_TCI_PASSTHRU) + if (dim > input_texture_coord[idx] && gen == NINED3DTSS_TCI_PASSTHRU) proj = 0; } else { dim = 4; diff -Nru mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/intel/compiler/brw_fs_generator.cpp mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/intel/compiler/brw_fs_generator.cpp --- mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/intel/compiler/brw_fs_generator.cpp 2024-01-18 07:13:30.000000000 +0000 +++ mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/intel/compiler/brw_fs_generator.cpp 2024-04-14 19:01:05.000000000 +0000 @@ -485,7 +485,7 @@ reg.nr = imm_byte_offset / REG_SIZE; reg.subnr = imm_byte_offset % REG_SIZE; - if (type_sz(reg.type) > 4 && !devinfo->has_64bit_float) { + if (type_sz(reg.type) > 4 && !devinfo->has_64bit_int) { brw_MOV(p, subscript(dst, BRW_REGISTER_TYPE_D, 0), subscript(reg, BRW_REGISTER_TYPE_D, 0)); brw_set_default_swsb(p, tgl_swsb_null()); @@ -567,7 +567,7 @@ if (type_sz(reg.type) > 4 && ((devinfo->verx10 == 70) || devinfo->platform == INTEL_PLATFORM_CHV || intel_device_info_is_9lp(devinfo) || - !devinfo->has_64bit_float || devinfo->verx10 >= 125)) { + !devinfo->has_64bit_int)) { /* IVB has an issue (which we found empirically) where it reads two * address register components per channel for indirectly addressed * 64-bit sources. diff -Nru mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/intel/compiler/brw_fs_lower_regioning.cpp mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/intel/compiler/brw_fs_lower_regioning.cpp --- mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/intel/compiler/brw_fs_lower_regioning.cpp 2024-04-05 04:03:25.000000000 +0000 +++ mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/intel/compiler/brw_fs_lower_regioning.cpp 2024-04-14 19:01:05.000000000 +0000 @@ -190,18 +190,6 @@ else return brw_int_type(type_sz(t), false); - case SHADER_OPCODE_BROADCAST: - case SHADER_OPCODE_MOV_INDIRECT: - if (((devinfo->verx10 == 70 || - devinfo->platform == INTEL_PLATFORM_CHV || - intel_device_info_is_9lp(devinfo) || - devinfo->verx10 >= 125) && type_sz(inst->src[0].type) > 4) || - (devinfo->verx10 >= 125 && - brw_reg_type_is_floating_point(inst->src[0].type))) - return brw_int_type(type_sz(t), false); - else - return t; - default: return t; } diff -Nru mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/intel/dev/intel_device_info.c mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/intel/dev/intel_device_info.c --- mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/intel/dev/intel_device_info.c 2024-01-18 07:13:30.000000000 +0000 +++ mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/intel/dev/intel_device_info.c 2024-04-14 19:01:05.000000000 +0000 @@ -1667,6 +1667,8 @@ break; case INTEL_KMD_TYPE_XE: ret = intel_device_info_xe_get_info_from_fd(fd, devinfo); + if (devinfo->verx10 < 200) + mesa_logw("Support for this platform is experimental with Xe KMD, bug reports may be ignored."); break; default: ret = false; diff -Nru mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/intel/dev/intel_kmd.c mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/intel/dev/intel_kmd.c --- mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/intel/dev/intel_kmd.c 2024-01-18 07:13:30.000000000 +0000 +++ mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/intel/dev/intel_kmd.c 2024-04-14 19:01:05.000000000 +0000 @@ -37,10 +37,8 @@ if (strcmp(version->name, "i915") == 0) type = INTEL_KMD_TYPE_I915; -#ifdef INTEL_XE_KMD_SUPPORTED else if (strcmp(version->name, "xe") == 0) type = INTEL_KMD_TYPE_XE; -#endif drmFreeVersion(version); return type; diff -Nru mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/intel/isl/isl_emit_depth_stencil.c mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/intel/isl/isl_emit_depth_stencil.c --- mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/intel/isl/isl_emit_depth_stencil.c 2024-01-18 07:13:30.000000000 +0000 +++ mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/intel/isl/isl_emit_depth_stencil.c 2024-04-14 19:01:05.000000000 +0000 @@ -200,6 +200,9 @@ db.ControlSurfaceEnable = db.DepthBufferCompressionEnable = isl_aux_usage_has_ccs(info->hiz_usage); #endif +#if GFX_VER >= 12 + db.NullPageCoherencyEnable = info->depth_surf->usage & ISL_SURF_USAGE_SPARSE_BIT; +#endif } #if GFX_VER == 5 || GFX_VER == 6 @@ -271,6 +274,9 @@ sb.SurfaceQPitch = isl_surf_get_array_pitch_el_rows(info->stencil_surf) >> 2; #endif +#if GFX_VER >= 12 + sb.NullPageCoherencyEnable = info->stencil_surf->usage & ISL_SURF_USAGE_SPARSE_BIT; +#endif } else { #if GFX_VER >= 12 sb.SurfaceType = SURFTYPE_NULL; diff -Nru mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/intel/vulkan/anv_device.c mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/intel/vulkan/anv_device.c --- mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/intel/vulkan/anv_device.c 2024-03-27 22:11:05.000000000 +0000 +++ mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/intel/vulkan/anv_device.c 2024-04-14 19:01:05.000000000 +0000 @@ -944,9 +944,10 @@ p->maxMultiviewViewCount = 16; p->maxMultiviewInstanceIndex = UINT32_MAX / 16; /* Our protected implementation is a memory encryption mechanism, it - * doesn't page fault. + * shouldn't page fault, but it hangs the HW so in terms of user visibility + * it's similar to a fault. */ - p->protectedNoFault = true; + p->protectedNoFault = false; /* This value doesn't matter for us today as our per-stage descriptors are * the real limit. */ @@ -2239,7 +2240,7 @@ device->flush_astc_ldr_void_extent_denorms = device->has_astc_ldr && !device->emu_astc_ldr; } - device->disable_fcv = intel_device_info_is_mtl(&device->info) || + device->disable_fcv = device->info.verx10 >= 125 || instance->disable_fcv; result = anv_physical_device_init_heaps(device, fd); @@ -4063,7 +4064,7 @@ if (mem->vk.alloc_flags & VK_MEMORY_ALLOCATE_DEVICE_ADDRESS_BIT) alloc_flags |= ANV_BO_ALLOC_CLIENT_VISIBLE_ADDRESS; - if (mem->vk.alloc_flags & VK_MEMORY_PROPERTY_PROTECTED_BIT) + if (mem_type->propertyFlags & VK_MEMORY_PROPERTY_PROTECTED_BIT) alloc_flags |= ANV_BO_ALLOC_PROTECTED; /* For now, always allocated AUX-TT aligned memory, regardless of dedicated diff -Nru mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/intel/vulkan/genX_blorp_exec.c mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/intel/vulkan/genX_blorp_exec.c --- mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/intel/vulkan/genX_blorp_exec.c 2024-01-18 07:13:30.000000000 +0000 +++ mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/intel/vulkan/genX_blorp_exec.c 2024-04-14 19:01:05.000000000 +0000 @@ -417,7 +417,9 @@ blorp_exec(batch, params); + cmd_buffer->state.descriptors_dirty |= VK_SHADER_STAGE_COMPUTE_BIT; cmd_buffer->state.push_constants_dirty |= VK_SHADER_STAGE_COMPUTE_BIT; + cmd_buffer->state.compute.pipeline_dirty = true; } static void diff -Nru mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/intel/vulkan/genX_cmd_buffer.c mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/intel/vulkan/genX_cmd_buffer.c --- mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/intel/vulkan/genX_cmd_buffer.c 2024-03-14 07:32:36.000000000 +0000 +++ mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/intel/vulkan/genX_cmd_buffer.c 2024-04-14 19:01:05.000000000 +0000 @@ -2928,6 +2928,16 @@ }; } + /* SKL PRMs, Volume 7: 3D-Media-GPGPU, Programming Restrictions for + * PIPE_CONTROL, Flush Types: + * "Requires stall bit ([20] of DW) set for all GPGPU Workloads." + * For newer platforms this is documented in the PIPE_CONTROL instruction + * page. + */ + if (current_pipeline == GPGPU && + (bits & ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT)) + bits |= ANV_PIPE_CS_STALL_BIT; + #if INTEL_NEEDS_WA_1409600907 /* Wa_1409600907: "PIPE_CONTROL with Depth Stall Enable bit must * be set with any PIPE_CONTROL with Depth Flush Enable bit set. @@ -3333,6 +3343,10 @@ const struct anv_graphics_pipeline *pipeline = anv_pipeline_to_graphics(cmd_buffer->state.gfx.base.pipeline); + /* We cannot generate readable commands in protected mode. */ + if (cmd_buffer->vk.pool->flags & VK_COMMAND_POOL_CREATE_PROTECTED_BIT) + return false; + /* Limit generated draws to pipelines without HS stage. This makes things * simpler for implementing Wa_1306463417, Wa_16011107343. */ @@ -3343,6 +3357,33 @@ return count >= device->physical->instance->generated_indirect_threshold; } +static void +genX(cmd_buffer_set_protected_memory)(struct anv_cmd_buffer *cmd_buffer, + bool enabled) +{ +#if GFX_VER >= 12 + if (enabled) { + anv_batch_emit(&cmd_buffer->batch, GENX(MI_SET_APPID), appid) { + /* Default value for single session. */ + appid.ProtectedMemoryApplicationID = cmd_buffer->device->protected_session_id; + appid.ProtectedMemoryApplicationIDType = DISPLAY_APP; + } + } + anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) { + pc.PipeControlFlushEnable = true; + pc.DCFlushEnable = true; + pc.RenderTargetCacheFlushEnable = true; + pc.CommandStreamerStallEnable = true; + if (enabled) + pc.ProtectedMemoryEnable = true; + else + pc.ProtectedMemoryDisable = true; + } +#else + unreachable("Protected content not supported"); +#endif +} + VkResult genX(BeginCommandBuffer)( VkCommandBuffer commandBuffer, @@ -3417,19 +3458,8 @@ #if GFX_VER >= 12 if (cmd_buffer->vk.level == VK_COMMAND_BUFFER_LEVEL_PRIMARY && - cmd_buffer->vk.pool->flags & VK_COMMAND_POOL_CREATE_PROTECTED_BIT) { - anv_batch_emit(&cmd_buffer->batch, GENX(MI_SET_APPID), appid) { - /* Default value for single session. */ - appid.ProtectedMemoryApplicationID = cmd_buffer->device->protected_session_id; - appid.ProtectedMemoryApplicationIDType = DISPLAY_APP; - } - anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) { - pc.CommandStreamerStallEnable = true; - pc.DCFlushEnable = true; - pc.RenderTargetCacheFlushEnable = true; - pc.ProtectedMemoryEnable = true; - } - } + cmd_buffer->vk.pool->flags & VK_COMMAND_POOL_CREATE_PROTECTED_BIT) + genX(cmd_buffer_set_protected_memory)(cmd_buffer, true); #endif genX(cmd_buffer_emit_state_base_address)(cmd_buffer); @@ -3643,14 +3673,8 @@ #if GFX_VER >= 12 if (cmd_buffer->vk.level == VK_COMMAND_BUFFER_LEVEL_PRIMARY && - cmd_buffer->vk.pool->flags & VK_COMMAND_POOL_CREATE_PROTECTED_BIT) { - anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) { - pc.CommandStreamerStallEnable = true; - pc.DCFlushEnable = true; - pc.RenderTargetCacheFlushEnable = true; - pc.ProtectedMemoryDisable = true; - } - } + cmd_buffer->vk.pool->flags & VK_COMMAND_POOL_CREATE_PROTECTED_BIT) + genX(cmd_buffer_set_protected_memory)(cmd_buffer, false); #endif trace_intel_end_cmd_buffer(&cmd_buffer->trace, cmd_buffer->vk.level); @@ -4072,6 +4096,7 @@ * tile cache flush to make sure any previous write is not going to * create WaW hazards. */ + pipe_bits |= ANV_PIPE_DATA_CACHE_FLUSH_BIT; pipe_bits |= ANV_PIPE_TILE_CACHE_FLUSH_BIT; break; case VK_ACCESS_2_SHADER_STORAGE_READ_BIT: diff -Nru mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/intel/vulkan/genX_init_state.c mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/intel/vulkan/genX_init_state.c --- mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/intel/vulkan/genX_init_state.c 2024-02-12 22:13:35.000000000 +0000 +++ mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/intel/vulkan/genX_init_state.c 2024-04-14 19:01:05.000000000 +0000 @@ -158,12 +158,15 @@ } /* TODO: Figure out FCV support for other platforms - * Testing indicates that FCV is broken on MTL, but works fine on DG2. - * Let's disable FCV on MTL for now till we figure out what's wrong. + * Testing indicates that FCV is broken gfx125. + * Let's disable FCV for now till we figure out what's wrong. * * Alternatively, it can be toggled off via drirc option 'anv_disable_fcv'. * * Ref: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9987 + * Ref: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10318 + * Ref: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10795 + * Ref: Internal issue 1480 about Unreal Engine 5.1 */ anv_batch_emit(batch, GENX(3DSTATE_3D_MODE), mode) { mode.SliceHashingTableEnable = true; diff -Nru mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/intel/vulkan/i915/anv_queue.c mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/intel/vulkan/i915/anv_queue.c --- mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/intel/vulkan/i915/anv_queue.c 2023-10-25 21:39:07.000000000 +0000 +++ mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/intel/vulkan/i915/anv_queue.c 2024-04-14 19:01:05.000000000 +0000 @@ -58,8 +58,13 @@ } else if (device->physical->has_vm_control) { assert(pCreateInfo->queueFamilyIndex < physical->queue.family_count); enum intel_engine_class engine_classes[1]; + enum intel_gem_create_context_flags flags = 0; + engine_classes[0] = queue_family->engine_class; - if (!intel_gem_create_context_engines(device->fd, 0 /* flags */, + if (pCreateInfo->flags & VK_DEVICE_QUEUE_CREATE_PROTECTED_BIT) + flags |= INTEL_GEM_CREATE_CONTEXT_EXT_PROTECTED_FLAG; + + if (!intel_gem_create_context_engines(device->fd, flags, physical->engine_info, 1, engine_classes, device->vm_id, @@ -74,7 +79,7 @@ queue_family->engine_class == INTEL_ENGINE_CLASS_COMPUTE) { uint32_t *context_id = (uint32_t *)&queue->companion_rcs_id; engine_classes[0] = INTEL_ENGINE_CLASS_RENDER; - if (!intel_gem_create_context_engines(device->fd, 0 /* flags */, + if (!intel_gem_create_context_engines(device->fd, flags, physical->engine_info, 1, engine_classes, device->vm_id, diff -Nru mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/intel/vulkan/xe/anv_batch_chain.c mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/intel/vulkan/xe/anv_batch_chain.c --- mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/intel/vulkan/xe/anv_batch_chain.c 2024-01-18 07:13:30.000000000 +0000 +++ mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/intel/vulkan/xe/anv_batch_chain.c 2024-04-14 19:01:05.000000000 +0000 @@ -114,9 +114,15 @@ struct drm_xe_sync **ret, uint32_t *ret_count) { struct anv_device *device = queue->device; - uint32_t num_syncs = wait_count + signal_count + extra_sync_count + - (utrace_submit ? 1 : 0) + - ((queue->sync && !is_companion_rcs_queue) ? 1 : 0); + /* Signal the utrace sync only if it doesn't have a batch. Otherwise the + * it's the utrace batch that should signal its own sync. + */ + const bool has_utrace_sync = utrace_submit && + util_dynarray_num_elements(&utrace_submit->batch_bos, struct anv_bo *) == 0; + const uint32_t num_syncs = wait_count + signal_count + extra_sync_count + + (has_utrace_sync ? 1 : 0) + + ((queue->sync && !is_companion_rcs_queue) ? 1 : 0); + if (!num_syncs) return VK_SUCCESS; @@ -128,12 +134,7 @@ uint32_t count = 0; - /* Signal the utrace sync only if it doesn't have a batch. Otherwise the - * it's the utrace batch that should signal its own sync. - */ - if (utrace_submit && - util_dynarray_num_elements(&utrace_submit->batch_bos, - struct anv_bo *) == 0) { + if (has_utrace_sync) { struct drm_xe_sync *xe_sync = &xe_syncs[count++]; xe_exec_fill_sync(xe_sync, utrace_submit->sync, 0, TYPE_SIGNAL); @@ -191,7 +192,7 @@ struct anv_queue *queue = submit->queue; struct anv_device *device = queue->device; struct anv_trtt *trtt = &device->trtt; - VkResult result; + VkResult result = VK_SUCCESS; struct drm_xe_sync extra_sync = { .type = DRM_XE_SYNC_TYPE_TIMELINE_SYNCOBJ, @@ -220,18 +221,22 @@ }; if (!device->info->no_hw) { - if (intel_ioctl(device->fd, DRM_IOCTL_XE_EXEC, &exec)) - return vk_device_set_lost(&device->vk, "XE_EXEC failed: %m"); + if (intel_ioctl(device->fd, DRM_IOCTL_XE_EXEC, &exec)) { + result = vk_device_set_lost(&device->vk, "XE_EXEC failed: %m"); + goto out; + } } if (queue->sync) { result = vk_sync_wait(&device->vk, queue->sync, 0, VK_SYNC_WAIT_COMPLETE, UINT64_MAX); if (result != VK_SUCCESS) - return vk_queue_set_lost(&queue->vk, "trtt sync wait failed"); + result = vk_queue_set_lost(&queue->vk, "trtt sync wait failed"); } - return VK_SUCCESS; +out: + vk_free(&device->vk.alloc, xe_syncs); + return result; } VkResult diff -Nru mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/mesa/main/shaderapi.c mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/mesa/main/shaderapi.c --- mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/mesa/main/shaderapi.c 2024-02-12 22:13:35.000000000 +0000 +++ mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/mesa/main/shaderapi.c 2024-04-14 19:01:05.000000000 +0000 @@ -2363,6 +2363,10 @@ GET_CURRENT_CONTEXT(ctx); struct gl_shader **sh; + /* no binary data can be loaded if length==0 */ + if (!length) + binary = NULL; + /* Page 68, section 7.2 'Shader Binaries" of the of the OpenGL ES 3.1, and * page 88 of the OpenGL 4.5 specs state: * diff -Nru mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/mesa/state_tracker/st_cb_copyimage.c mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/mesa/state_tracker/st_cb_copyimage.c --- mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/mesa/state_tracker/st_cb_copyimage.c 2024-01-18 07:13:30.000000000 +0000 +++ mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/mesa/state_tracker/st_cb_copyimage.c 2024-04-14 19:01:05.000000000 +0000 @@ -282,7 +282,10 @@ blit.src.box = *src_box; u_box_3d(dstx, dsty, dstz, src_box->width, src_box->height, src_box->depth, &blit.dst.box); - blit.mask = PIPE_MASK_RGBA; + if (util_format_is_depth_or_stencil(dst_format)) + blit.mask = PIPE_MASK_ZS; + else + blit.mask = PIPE_MASK_RGBA; blit.filter = PIPE_TEX_FILTER_NEAREST; pipe->blit(pipe, &blit); diff -Nru mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/mesa/state_tracker/st_context.c mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/mesa/state_tracker/st_context.c --- mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/mesa/state_tracker/st_context.c 2024-01-18 07:13:30.000000000 +0000 +++ mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/mesa/state_tracker/st_context.c 2024-04-14 19:01:05.000000000 +0000 @@ -987,17 +987,17 @@ st_destroy_program_variants(st); - st_context_free_zombie_objects(st); - - simple_mtx_destroy(&st->zombie_sampler_views.mutex); - simple_mtx_destroy(&st->zombie_shaders.mutex); - /* Do not release debug_output yet because it might be in use by other threads. * These threads will be terminated by _mesa_free_context_data and * st_destroy_context_priv. */ _mesa_free_context_data(ctx, false); + st_context_free_zombie_objects(st); + + simple_mtx_destroy(&st->zombie_sampler_views.mutex); + simple_mtx_destroy(&st->zombie_shaders.mutex); + /* This will free the st_context too, so 'st' must not be accessed * afterwards. */ st_destroy_context_priv(st, true); diff -Nru mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/nouveau/compiler/nak.h mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/nouveau/compiler/nak.h --- mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/nouveau/compiler/nak.h 2024-01-18 07:13:30.000000000 +0000 +++ mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/nouveau/compiler/nak.h 2024-04-14 19:01:05.000000000 +0000 @@ -32,6 +32,8 @@ void nak_optimize_nir(nir_shader *nir, const struct nak_compiler *nak); void nak_preprocess_nir(nir_shader *nir, const struct nak_compiler *nak); +PRAGMA_DIAGNOSTIC_PUSH +PRAGMA_DIAGNOSTIC_ERROR(-Wpadded) struct nak_fs_key { bool zs_self_dep; @@ -40,6 +42,8 @@ */ bool force_sample_shading; + uint8_t _pad; + /** * The constant buffer index and offset at which the sample locations table lives. * Each sample location is two 4-bit unorm values packed into an 8-bit value @@ -48,6 +52,9 @@ uint8_t sample_locations_cb; uint32_t sample_locations_offset; }; +PRAGMA_DIAGNOSTIC_POP +static_assert(sizeof(struct nak_fs_key) == 8, "This struct has no holes"); + void nak_postprocess_nir(nir_shader *nir, const struct nak_compiler *nak, nir_variable_mode robust2_modes, diff -Nru mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/nouveau/vulkan/nvk_shader.h mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/nouveau/vulkan/nvk_shader.h --- mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/nouveau/vulkan/nvk_shader.h 2024-01-18 07:13:30.000000000 +0000 +++ mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/nouveau/vulkan/nvk_shader.h 2024-04-14 19:01:05.000000000 +0000 @@ -39,8 +39,10 @@ enum nvk_cbuf_type type; uint8_t desc_set; uint8_t dynamic_idx; + uint8_t _pad; uint32_t desc_offset; }; +static_assert(sizeof(struct nvk_cbuf) == 8, "This struct has no holes"); struct nvk_cbuf_map { uint32_t cbuf_count; diff -Nru mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/util/00-mesa-defaults.conf mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/util/00-mesa-defaults.conf --- mesa-24.0.4+git2404011708.52549327115~n~mesarc5/src/util/00-mesa-defaults.conf 2024-03-14 07:32:36.000000000 +0000 +++ mesa-24.0.5+git2404102228.976b75c8c5f~n~mesarc5/src/util/00-mesa-defaults.conf 2024-04-14 19:01:05.000000000 +0000 @@ -431,6 +431,13 @@