diff -u mesa-7.11/debian/changelog mesa-7.11/debian/changelog --- mesa-7.11/debian/changelog +++ mesa-7.11/debian/changelog @@ -1,9 +1,26 @@ -mesa (7.11-0ubuntu3.1linaro1) oneiric; urgency=low +mesa (7.11-0ubuntu3.2linaro1) oneiric; urgency=low * debian/patches/200_upgrade_gl2ext.patch: updating gl2ext to enable GL_TEXTURE_EXTERNAL_OES (used by xbmc) - -- Ricardo Salveti de Araujo Thu, 01 Mar 2012 22:30:42 -0300 + -- Ricardo Salveti de Araujo Mon, 16 Apr 2012 17:38:49 -0300 + +mesa (7.11-0ubuntu3.2) oneiric-proposed; urgency=low + + * Add patch series from upstream stable release to fix various issues: + - 121-i965-fix-border-color.patch: Fixes wrong colors in lightsmark + (LP: #966399) + - 122-i965-apply-post-sync-workaround.patch: Fixes GPU hangs in + Civilization 4, PlaneShift, Minecraft, Neverwinter Nights + (among others) on Sandybridge and Ivybridge. (LP: #966399) + - 123-i965-emit-depth-stalls-and-flushes.patch: Fixes GPU hangs when + running qgears2, lightsmark, and openarena on Ivybridge. (LP: #966399) + - 124-i965-last-render-target-select.patch: Fixes a GPU hang when + running Trine, or Unigine Heaven which crashes the desktop. (LP: #966399) + * Drop 120_fix_tfp_texture_free.patch from previous SRU, it was the + incorrect patch. + + -- Robert Hooker Tue, 20 Mar 2012 10:44:16 -0400 mesa (7.11-0ubuntu3.1) oneiric-proposed; urgency=low reverted: --- mesa-7.11/debian/patches/120_fix_tfp_texture_free.patch +++ mesa-7.11.orig/debian/patches/120_fix_tfp_texture_free.patch @@ -1,37 +0,0 @@ -commit b2f1366c2825aeee3411c88db5c8e6b426191487 -Author: Bryce Harrington -Date: Thu Jan 26 15:30:24 2012 -0800 - - Backport of the following patch to oneiric: - - commit d430e81c3287eba4ee84ca1639a23f92bbe22c8e - Author: Eric Anholt - Date: Wed Sep 21 15:17:36 2011 -0700 - - intel: Fix improper freeing of texture data in TFP. - - If there happened to be ->Data present, we assertion failed instead - of handling it correctly. - - Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=35234 - Acked-by: Kenneth Graunke - - Most of the surrounding code has changed, so it's unclear if this change - alone is sufficient to resolve the problem. - -diff --git a/src/mesa/drivers/dri/intel/intel_tex_image.c b/src/mesa/drivers/dri/intel/intel_tex_image.c -index 269faef..4d0968e 100644 ---- a/src/mesa/drivers/dri/intel/intel_tex_image.c -+++ b/src/mesa/drivers/dri/intel/intel_tex_image.c -@@ -822,10 +822,7 @@ intelSetTexBuffer2(__DRIcontext *pDRICtx, GLint target, - texImage = _mesa_get_tex_image(&intel->ctx, texObj, target, level); - intelImage = intel_texture_image(texImage); - -- if (intelImage->mt) { -- intel_miptree_release(intel, &intelImage->mt); -- assert(!texImage->Data); -- } -+ ctx->Driver.FreeTextureImageBuffer(ctx, image); - if (intelObj->mt) - intel_miptree_release(intel, &intelObj->mt); - diff -u mesa-7.11/debian/patches/series mesa-7.11/debian/patches/series --- mesa-7.11/debian/patches/series +++ mesa-7.11/debian/patches/series @@ -17,7 +17,10 @@ 117_handle_dri2connect_errors_when_indirect.diff 118_fix_24bpp_software_renering.diff 119_r600g_gnome_shell_rendering_fix.diff -120_fix_tfp_texture_free.patch +121-i965-fix-border-color.patch +122-i965-apply-post-sync-workaround.patch +123-i965-emit-depth-stalls-and-flushes.patch +124-i965-last-render-target-select.patch # Linaro patches 200_upgrade_gl2ext.patch only in patch2: unchanged: --- mesa-7.11.orig/debian/patches/121-i965-fix-border-color.patch +++ mesa-7.11/debian/patches/121-i965-fix-border-color.patch @@ -0,0 +1,48 @@ +From da33bb5fde8f752c74ca4cd15c067c3a593bac97 Mon Sep 17 00:00:00 2001 +From: Kenneth Graunke +Date: Fri, 20 Jan 2012 03:33:40 -0800 +Subject: [PATCH] i965: Fix border color on Sandybridge and Ivybridge. + +While reading through the simulator, I found some interesting code that +looks like it checks the sampler default color pointer against the bound +set in STATE_BASE_ADDRESS. On failure, it appears to program it to the +base address itself. + +So I decided to try programming a legitimate bound, and lo and behold, +border color worked. + ++92 piglits on Sandybridge. Also fixes Lightsmark on Ivybridge. + +NOTE: This is a candidate for stable release branches. + +Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=28924 +Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=38868 +Signed-off-by: Kenneth Graunke +Reviewed-by: Yuanhan Liu +Reviewed-by: Eric Anholt +--- + src/mesa/drivers/dri/i965/brw_misc_state.c | 8 +++++++- + 1 files changed, 7 insertions(+), 1 deletions(-) + +diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c +index 033c77c..fd3ac13 100644 +--- a/src/mesa/drivers/dri/i965/brw_misc_state.c ++++ b/src/mesa/drivers/dri/i965/brw_misc_state.c +@@ -752,7 +752,13 @@ static void upload_state_base_address( struct brw_context *brw ) + 1); /* Instruction base address: shader kernels (incl. SIP) */ + + OUT_BATCH(1); /* General state upper bound */ +- OUT_BATCH(1); /* Dynamic state upper bound */ ++ /* Dynamic state upper bound. Although the documentation says that ++ * programming it to zero will cause it to be ignored, that is a lie. ++ * If this isn't programmed to a real bound, the sampler border color ++ * pointer is rejected, causing border color to mysteriously fail. ++ */ ++ OUT_RELOC(intel->batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, ++ intel->batch.bo->size | 1); + OUT_BATCH(1); /* Indirect object upper bound */ + OUT_BATCH(1); /* Instruction access upper bound */ + ADVANCE_BATCH(); +-- +1.7.9.1 + only in patch2: unchanged: --- mesa-7.11.orig/debian/patches/122-i965-apply-post-sync-workaround.patch +++ mesa-7.11/debian/patches/122-i965-apply-post-sync-workaround.patch @@ -0,0 +1,40 @@ +From 439628318bfd4596d0d8129a0792d2c3ea849bb7 Mon Sep 17 00:00:00 2001 +From: Kenneth Graunke +Date: Fri, 21 Oct 2011 08:03:37 +0000 +Subject: i965: Apply post-sync non-zero workaround to homebrew workaround. + +In commit 3e5d3626, Eric added a homebrew workaround to fix GPU hangs in +the Mesa "engine" demo and oglc's api-texcoord test. + +Unfortunately, his PIPE_CONTROL contains a Depth Stall, which +necessitates the post-sync non-zero workaround, + +Fixes GPU hangs in Civilization 4, PlaneShift, Minecraft, Neverwinter +Nights, 3DMMES, and hopefully Heroes of Newerth as well. + +Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=40324 +Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=41096 +Signed-off-by: Kenneth Graunke +Reviewed-by: Eric Anholt +Tested-by: Joel (Neverwinter Nights) +Tested-by: brot (Minecraft) +Tested-by: Eric Anholt (3DMMES) +Tested-by: Kenneth Graunke (Civ 4 & PlaneShift) + +(cherry-picked from commit 3cc0a7be23ab603ed40d602595f673a44e079885) +--- +diff --git a/src/mesa/drivers/dri/i965/gen6_vs_state.c b/src/mesa/drivers/dri/i965/gen6_vs_state.c +index b30ae26..3e62dfd 100644 +--- a/src/mesa/drivers/dri/i965/gen6_vs_state.c ++++ b/src/mesa/drivers/dri/i965/gen6_vs_state.c +@@ -178,6 +178,8 @@ upload_vs_state(struct brw_context *brw) + * bug reports that led to this workaround, and may be more than + * what is strictly required to avoid the issue. + */ ++ intel_emit_post_sync_nonzero_flush(intel); ++ + BEGIN_BATCH(4); + OUT_BATCH(_3DSTATE_PIPE_CONTROL); + OUT_BATCH(PIPE_CONTROL_DEPTH_STALL | +-- +cgit v0.9.0.2-2-gbebe only in patch2: unchanged: --- mesa-7.11.orig/debian/patches/123-i965-emit-depth-stalls-and-flushes.patch +++ mesa-7.11/debian/patches/123-i965-emit-depth-stalls-and-flushes.patch @@ -0,0 +1,153 @@ +From 38dfedccb2a2b695a600350a75113e8c35683498 Mon Sep 17 00:00:00 2001 +From: Kenneth Graunke +Date: Thu, 01 Sep 2011 11:18:20 +0000 +Subject: i965: Emit depth stalls and flushes before changing depth state on Gen6+. + +Fixes OpenArena on Gen7. Technically, adding only the first depth stall +fixes it, but the documentation says to do all three, and the Windows +driver seems to do it. + +Not observed to fix anything on Gen6 yet. + +Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=38863 +Signed-off-by: Kenneth Graunke +Reviewed-by: Eric Anholt +(cherry picked from commit 02c4dc807e91640c69c8addc3c797300a3c536ad) + +Additional patch to src/mesa/drivers/dri/i965/intel_batchbuffer.c added because +intel_* symlinks are dereferenced on tarball creation. + +Signed-off-by: Robert Hooker +--- +diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c +index e574806..a1429ce 100644 +--- a/src/mesa/drivers/dri/i965/brw_misc_state.c ++++ b/src/mesa/drivers/dri/i965/brw_misc_state.c +@@ -226,8 +226,10 @@ static void emit_depthbuffer(struct brw_context *brw) + /* 3DSTATE_DEPTH_BUFFER, 3DSTATE_STENCIL_BUFFER are both + * non-pipelined state that will need the PIPE_CONTROL workaround. + */ +- if (intel->gen == 6) ++ if (intel->gen == 6) { + intel_emit_post_sync_nonzero_flush(intel); ++ intel_emit_depth_stall_flushes(intel); ++ } + + /* + * If either depth or stencil buffer has packed depth/stencil format, +diff --git a/src/mesa/drivers/dri/i965/gen7_misc_state.c b/src/mesa/drivers/dri/i965/gen7_misc_state.c +index 7544f96..9eb75e2 100644 +--- a/src/mesa/drivers/dri/i965/gen7_misc_state.c ++++ b/src/mesa/drivers/dri/i965/gen7_misc_state.c +@@ -80,6 +80,8 @@ static void emit_depthbuffer(struct brw_context *brw) + struct intel_renderbuffer *drb = intel_get_renderbuffer(fb, BUFFER_DEPTH); + struct intel_renderbuffer *srb = intel_get_renderbuffer(fb, BUFFER_STENCIL); + ++ intel_emit_depth_stall_flushes(intel); ++ + /* Gen7 doesn't support packed depth/stencil */ + assert(srb == NULL || srb != drb); + +diff --git a/src/mesa/drivers/dri/intel/intel_batchbuffer.c b/src/mesa/drivers/dri/intel/intel_batchbuffer.c +index 7ee802b..7ef8e65 100644 +--- a/src/mesa/drivers/dri/intel/intel_batchbuffer.c ++++ b/src/mesa/drivers/dri/intel/intel_batchbuffer.c +@@ -294,6 +294,45 @@ emit: + } + + /** ++ * Restriction [DevSNB, DevIVB]: ++ * ++ * Prior to changing Depth/Stencil Buffer state (i.e. any combination of ++ * 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS, 3DSTATE_STENCIL_BUFFER, ++ * 3DSTATE_HIER_DEPTH_BUFFER) SW must first issue a pipelined depth stall ++ * (PIPE_CONTROL with Depth Stall bit set), followed by a pipelined depth ++ * cache flush (PIPE_CONTROL with Depth Flush Bit set), followed by ++ * another pipelined depth stall (PIPE_CONTROL with Depth Stall bit set), ++ * unless SW can otherwise guarantee that the pipeline from WM onwards is ++ * already flushed (e.g., via a preceding MI_FLUSH). ++ */ ++void ++intel_emit_depth_stall_flushes(struct intel_context *intel) ++{ ++ assert(intel->gen >= 6 && intel->gen <= 7); ++ ++ BEGIN_BATCH(4); ++ OUT_BATCH(_3DSTATE_PIPE_CONTROL); ++ OUT_BATCH(PIPE_CONTROL_DEPTH_STALL); ++ OUT_BATCH(0); /* address */ ++ OUT_BATCH(0); /* write data */ ++ ADVANCE_BATCH() ++ ++ BEGIN_BATCH(4); ++ OUT_BATCH(_3DSTATE_PIPE_CONTROL); ++ OUT_BATCH(PIPE_CONTROL_DEPTH_CACHE_FLUSH); ++ OUT_BATCH(0); /* address */ ++ OUT_BATCH(0); /* write data */ ++ ADVANCE_BATCH(); ++ ++ BEGIN_BATCH(4); ++ OUT_BATCH(_3DSTATE_PIPE_CONTROL); ++ OUT_BATCH(PIPE_CONTROL_DEPTH_STALL); ++ OUT_BATCH(0); /* address */ ++ OUT_BATCH(0); /* write data */ ++ ADVANCE_BATCH(); ++} ++ ++/** + * Emits a PIPE_CONTROL with a non-zero post-sync operation, for + * implementing two workarounds on gen6. From section 1.4.7.1 + * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1: +diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c b/src/mesa/drivers/dri/i965/intel_batchbuffer.c +index 7ee802b..7ef8e65 100644 +--- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c ++++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c +@@ -294,6 +294,45 @@ emit: + } + + /** ++ * Restriction [DevSNB, DevIVB]: ++ * ++ * Prior to changing Depth/Stencil Buffer state (i.e. any combination of ++ * 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS, 3DSTATE_STENCIL_BUFFER, ++ * 3DSTATE_HIER_DEPTH_BUFFER) SW must first issue a pipelined depth stall ++ * (PIPE_CONTROL with Depth Stall bit set), followed by a pipelined depth ++ * cache flush (PIPE_CONTROL with Depth Flush Bit set), followed by ++ * another pipelined depth stall (PIPE_CONTROL with Depth Stall bit set), ++ * unless SW can otherwise guarantee that the pipeline from WM onwards is ++ * already flushed (e.g., via a preceding MI_FLUSH). ++ */ ++void ++intel_emit_depth_stall_flushes(struct intel_context *intel) ++{ ++ assert(intel->gen >= 6 && intel->gen <= 7); ++ ++ BEGIN_BATCH(4); ++ OUT_BATCH(_3DSTATE_PIPE_CONTROL); ++ OUT_BATCH(PIPE_CONTROL_DEPTH_STALL); ++ OUT_BATCH(0); /* address */ ++ OUT_BATCH(0); /* write data */ ++ ADVANCE_BATCH() ++ ++ BEGIN_BATCH(4); ++ OUT_BATCH(_3DSTATE_PIPE_CONTROL); ++ OUT_BATCH(PIPE_CONTROL_DEPTH_CACHE_FLUSH); ++ OUT_BATCH(0); /* address */ ++ OUT_BATCH(0); /* write data */ ++ ADVANCE_BATCH(); ++ ++ BEGIN_BATCH(4); ++ OUT_BATCH(_3DSTATE_PIPE_CONTROL); ++ OUT_BATCH(PIPE_CONTROL_DEPTH_STALL); ++ OUT_BATCH(0); /* address */ ++ OUT_BATCH(0); /* write data */ ++ ADVANCE_BATCH(); ++} ++ ++/** + * Emits a PIPE_CONTROL with a non-zero post-sync operation, for + * implementing two workarounds on gen6. From section 1.4.7.1 + * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1: + +-- +cgit v0.9.0.2-2-gbebe only in patch2: unchanged: --- mesa-7.11.orig/debian/patches/124-i965-last-render-target-select.patch +++ mesa-7.11/debian/patches/124-i965-last-render-target-select.patch @@ -0,0 +1,32 @@ +From 16cc79f975816c0741711560be48fc498d4b4794 Mon Sep 17 00:00:00 2001 +From: Kenneth Graunke +Date: Sun, 19 Feb 2012 05:29:29 +0000 +Subject: i965: Only set Last Render Target Select on the last FB write. + +Fixes GPU hangs in OilRush, Trine, and Amnesia: The Dark Descent, +which all use MRT (multiple render targets). + +Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=38720 +Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=40059 +Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=45216 +Reviewed-by: Eric Anholt +Signed-off-by: Kenneth Graunke +(cherry picked from commit 172bb92db1a3c317867d9cfec6f15c09c37a0f6c) + +pixel scoreboard comment changed to make it apply to 7.11 branch. +Signed-off-by: Robert Hooker +--- + +diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c +index e7370f3..6a2a42a 100644 +--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c ++++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c +@@ -2086,7 +2086,7 @@ void brw_fb_WRITE(struct brw_compile *p, + msg_type, + msg_length, + header_present, +- 1, /* pixel scoreboard */ ++ eot, /* pixel scoreboard */ + response_length, + eot, + 0 /* send_commit_msg */);