If you are eager to try out building the JDK, these simple steps works most of the time. They assume that you have installed Mercurial (and Cygwin if running on Windows) and cloned the top-level JDK repository that you want to build.
+
If you are eager to try out building the JDK, these simple steps works most of the time. They assume that you have installed Git (and Cygwin if running on Windows) and cloned the top-level JDK repository that you want to build.
If configure fails due to missing dependencies (to either the toolchain, build tools, external libraries or the boot JDK), most of the time it prints a suggestion on how to resolve the situation on your platform. Follow the instructions, and try running bash configure again.
@@ -131,8 +129,8 @@
The JDK is a complex software project. Building it requires a certain amount of technical expertise, a fair number of dependencies on external software, and reasonably powerful hardware.
If you just want to use the JDK and not build it yourself, this document is not for you. See for instance OpenJDK installation for some methods of installing a prebuilt JDK.
Getting the Source Code
-
Make sure you are getting the correct version. As of JDK 10, the source is no longer split into separate repositories so you only need to clone one single repository. At the OpenJDK Mercurial server you can see a list of all available forests. If you want to build an older version, e.g. JDK 8, it is recommended that you get the jdk8u forest, which contains incremental updates, instead of the jdk8 forest, which was frozen at JDK 8 GA.
-
If you are new to Mercurial, a good place to start is the Mercurial Beginner's Guide. The rest of this document assumes a working knowledge of Mercurial.
+
Make sure you are getting the correct version. As of JDK 10, the source is no longer split into separate repositories so you only need to clone one single repository. At the OpenJDK Git site you can see a list of all available repositories. If you want to build an older version, e.g. JDK 8, it is recommended that you get the jdk8u forest, which contains incremental updates, instead of the jdk8 forest, which was frozen at JDK 8 GA.
+
If you are new to Git, a good place to start is the book Pro Git. The rest of this document assumes a working knowledge of Git.
Special Considerations
For a smooth building experience, it is recommended that you follow these rules on where and how to check out the source code.
@@ -143,7 +141,11 @@
Create the directory that is going to contain the top directory of the JDK clone by using the mkdir command in the Cygwin bash shell. That is, do not create it using Windows Explorer. This will ensure that it will have proper Cygwin attributes, and that it's children will inherit those attributes.
Do not put the JDK clone in a path under your Cygwin home directory. This is especially important if your user name contains spaces and/or mixed upper and lower case letters.
-
Clone the JDK repository using the Cygwin command line hg client as instructed in this document. That is, do not use another Mercurial client such as TortoiseHg.
+
You need to install a git client. You have two choices, Cygwin git or Git for Windows. Unfortunately there are pros and cons with each choice.
+
+
The Cygwin git client has no line ending issues and understands Cygwin paths (which are used throughout the JDK build system). However, it does not currently work well with the Skara CLI tooling. Please see the Skara wiki on Git clients for up-to-date information about the Skara git client support.
+
The Git for Windows client has issues with line endings, and do not understand Cygwin paths. It does work well with the Skara CLI tooling, however. To alleviate the line ending problems, make sure you set core.autocrlf to false (this is asked during installation).
+
Failure to follow this procedure might result in hard-to-debug build problems.
@@ -193,7 +195,7 @@
Windows XP is not a supported platform, but all newer Windows should be able to build the JDK.
On Windows, it is important that you pay attention to the instructions in the Special Considerations.
Windows is the only non-POSIX OS supported by the JDK, and as such, requires some extra care. A POSIX support layer is required to build on Windows. Currently, the only supported such layer is Cygwin. (Msys is no longer supported due to a too old bash; msys2 and the new Windows Subsystem for Linux (WSL) would likely be possible to support in a future version but that would require effort to implement.)
-
Internally in the build system, all paths are represented as Unix-style paths, e.g. /cygdrive/c/hg/jdk9/Makefile rather than C:\hg\jdk9\Makefile. This rule also applies to input to the build system, e.g. in arguments to configure. So, use --with-msvcr-dll=/cygdrive/c/msvcr100.dll rather than --with-msvcr-dll=c:\msvcr100.dll. For details on this conversion, see the section on Fixpath.
+
Internally in the build system, all paths are represented as Unix-style paths, e.g. /cygdrive/c/git/jdk/Makefile rather than C:\git\jdk\Makefile. This rule also applies to input to the build system, e.g. in arguments to configure. So, use --with-msvcr-dll=/cygdrive/c/msvcr100.dll rather than --with-msvcr-dll=c:\msvcr100.dll. For details on this conversion, see the section on Fixpath.
Cygwin
A functioning Cygwin environment is thus required for building the JDK on Windows. If you have a 64-bit OS, we strongly recommend using the 64-bit version of Cygwin.
Note: Cygwin has a model of continuously updating all packages without any easy way to install or revert to a specific version of a package. This means that whenever you add or update a package in Cygwin, you might (inadvertently) update tools that are used by the JDK build process, and that can cause unexpected build problems.
@@ -355,7 +357,7 @@
$ CC -V
CC: Sun C++ 5.13 SunOS_i386 151846-10 2015/10/30
Microsoft Visual Studio
-
The minimum accepted version of Visual Studio is 2010. Older versions will not be accepted by configure. The maximum accepted version of Visual Studio is 2017. Versions older than 2017 are unlikely to continue working for long.
+
The minimum accepted version of Visual Studio is 2010. Older versions will not be accepted by configure. The maximum accepted version of Visual Studio is 2019. Versions older than 2017 are unlikely to continue working for long.
If you have multiple versions of Visual Studio installed, configure will by default pick the latest. You can request a specific version to be used by setting --with-toolchain-version, e.g. --with-toolchain-version=2015.
If you get LINK: fatal error LNK1123: failure during conversion to COFF: file invalid when building using Visual Studio 2010, you have encountered KB2757355, a bug triggered by a specific installation order. However, the solution suggested by the KB article does not always resolve the problem. See this stackoverflow discussion for other suggestions.
Make sure the symlinks inside the newly created chroot point to proper locations:
+
sudo chroot ~/sysroot-arm64 symlinks -cr .
Configure and build with newly created chroot as sysroot/toolchain-path:
-
CC=aarch64-linux-gnu-gcc CXX=aarch64-linux-gnu-g++ sh ./configure --openjdk-target=aarch64-linux-gnu --with-sysroot=/chroots/arm64/ --with-toolchain-path=/chroots/arm64/
+
CC=aarch64-linux-gnu-gcc CXX=aarch64-linux-gnu-g++ sh ./configure \
+ --openjdk-target=aarch64-linux-gnu \
+ --with-sysroot=~/sysroot-arm64 \
+ --with-toolchain-path=~/sysroot-arm64 \
+ --with-freetype-lib=~/sysroot-arm64/usr/lib/aarch64-linux-gnu/ \
+ --with-freetype-include=~/sysroot-arm64/usr/include/freetype2/ \
+ --x-libraries=~/sysroot-arm64/usr/lib/aarch64-linux-gnu/
make images
ls build/linux-aarch64-normal-server-release/
@@ -700,8 +715,8 @@
Target
CC
CXX
-
--arch=...
-
--openjdk-target=...
+
--arch=...
+
--openjdk-target=...
@@ -709,36 +724,36 @@
x86
default
default
-
i386
-
i386-linux-gnu
+
i386
+
i386-linux-gnu
armhf
gcc-arm-linux-gnueabihf
g++-arm-linux-gnueabihf
-
armhf
-
arm-linux-gnueabihf
+
armhf
+
arm-linux-gnueabihf
aarch64
gcc-aarch64-linux-gnu
g++-aarch64-linux-gnu
-
arm64
-
aarch64-linux-gnu
+
arm64
+
aarch64-linux-gnu
ppc64el
gcc-powerpc64le-linux-gnu
g++-powerpc64le-linux-gnu
-
ppc64el
-
powerpc64le-linux-gnu
+
ppc64el
+
powerpc64le-linux-gnu
s390x
gcc-s390x-linux-gnu
g++-s390x-linux-gnu
-
s390x
-
s390x-linux-gnu
+
s390x
+
s390x-linux-gnu
@@ -789,14 +804,14 @@
=== Output from failing command(s) repeated here ===
* For target hotspot_variant-server_libjvm_objs_psMemoryPool.o:
-/localhome/hg/jdk9-sandbox/hotspot/src/share/vm/services/psMemoryPool.cpp:1:1: error: 'failhere' does not name a type
+/localhome/git/jdk-sandbox/hotspot/src/share/vm/services/psMemoryPool.cpp:1:1: error: 'failhere' does not name a type
... (rest of output omitted)
-* All command lines available in /localhome/hg/jdk9-sandbox/build/linux-x64/make-support/failure-logs.
+* All command lines available in /localhome/git/jdk-sandbox/build/linux-x64/make-support/failure-logs.
=== End of repeated output ===
=== Make failed targets repeated here ===
-lib/CompileJvm.gmk:207: recipe for target '/localhome/hg/jdk9-sandbox/build/linux-x64/hotspot/variant-server/libjvm/objs/psMemoryPool.o' failed
+lib/CompileJvm.gmk:207: recipe for target '/localhome/git/jdk-sandbox/build/linux-x64/hotspot/variant-server/libjvm/objs/psMemoryPool.o' failed
make/Main.gmk:263: recipe for target 'hotspot-server-libs' failed
=== End of repeated output ===
@@ -819,11 +834,11 @@
Verify that the summary at the end looks correct. Are you indeed using the Boot JDK and native toolchain that you expect?
By default, the JDK has a strict approach where warnings from the compiler is considered errors which fail the build. For very new or very old compiler versions, this can trigger new classes of warnings, which thus fails the build. Run configure with --disable-warnings-as-errors to turn of this behavior. (The warnings will still show, but not make the build fail.)
Problems with Incremental Rebuilds
-
Incremental rebuilds mean that when you modify part of the product, only the affected parts get rebuilt. While this works great in most cases, and significantly speed up the development process, from time to time complex interdependencies will result in an incorrect build result. This is the most common cause for unexpected build problems, together with inconsistencies between the different Mercurial repositories in the forest.
+
Incremental rebuilds mean that when you modify part of the product, only the affected parts get rebuilt. While this works great in most cases, and significantly speed up the development process, from time to time complex interdependencies will result in an incorrect build result. This is the most common cause for unexpected build problems.
Here are a suggested list of things to try if you are having unexpected build problems. Each step requires more time than the one before, so try them in order. Most issues will be solved at step 1 or 2.
-
Make sure your forest is up-to-date
-
Run bash get_source.sh to make sure you have the latest version of all repositories.
+
Make sure your repository is up-to-date
+
Run git pull origin master to make sure you have the latest changes.
Clean build results
The simplest way to fix incremental rebuild issues is to run make clean. This will remove all build results, but not the configuration or any build system support artifacts. In most cases, this will solve build errors resulting from incremental build mismatches.
Completely clean the build directory.
@@ -832,8 +847,8 @@
make dist-clean
bash configure $(cat current-configuration)
make
-
Re-clone the Mercurial forest
-
Sometimes the Mercurial repositories themselves gets in a state that causes the product to be un-buildable. In such a case, the simplest solution is often the "sledgehammer approach": delete the entire forest, and re-clone it. If you have local changes, save them first to a different location using hg export.
+
Re-clone the Git repository
+
Sometimes the Git repository gets in a state that causes the product to be un-buildable. In such a case, the simplest solution is often the "sledgehammer approach": delete the entire repository, and re-clone it. If you have local changes, save them first to a different location using git format-patch.
Specific Build Issues
Clock Skew
@@ -852,28 +867,9 @@
spawn failed
This can be a sign of a Cygwin problem. See the information about solving problems in the Cygwin section. Rebooting the computer might help temporarily.
Getting Help
-
If none of the suggestions in this document helps you, or if you find what you believe is a bug in the build system, please contact the Build Group by sending a mail to . Please include the relevant parts of the configure and/or build log.
+
If none of the suggestions in this document helps you, or if you find what you believe is a bug in the build system, please contact the Build Group by sending a mail to build-dev@openjdk.java.net. Please include the relevant parts of the configure and/or build log.
If you need general help or advice about developing for the JDK, you can also contact the Adoption Group. See the section on Contributing to OpenJDK for more information.
Hints and Suggestions for Advanced Users
-
Setting Up a Forest for Pushing Changes (defpath)
-
To help you prepare a proper push path for a Mercurial repository, there exists a useful tool known as defpath. It will help you setup a proper push path for pushing changes to the JDK.
-
Install the extension by cloning http://hg.openjdk.java.net/code-tools/defpath and updating your .hgrc file. Here's one way to do this:
If you also have the trees extension installed in Mercurial, you will automatically get a tdefpath command, which is even more useful. By running hg tdefpath -du <username> in the top repository of your forest, all repos will get setup automatically. This is the recommended usage.
Bash Completion
The configure and make commands tries to play nice with bash command-line completion (using <tab> or <tab><tab>). To use this functionality, make sure you enable completion in your ~/.bashrc (see instructions for bash in your operating system).
Make completion will work out of the box, and will complete valid make targets. For instance, typing make jdk-i<tab> will complete to make jdk-image.
@@ -927,14 +923,6 @@
Rebuilding Part of java.base (JDK_FILTER)
If you are modifying files in java.base, which is the by far largest module in the JDK, then you need to rebuild all those files whenever a single file has changed. (This inefficiency will hopefully be addressed in JDK 10.)
As a hack, you can use the make control variable JDK_FILTER to specify a pattern that will be used to limit the set of files being recompiled. For instance, make java.base JDK_FILTER=javax/crypto (or, to combine methods, make java.base-java-only JDK_FILTER=javax/crypto) will limit the compilation to files in the javax.crypto package.
-
Learn About Mercurial
-
To become an efficient JDK developer, it is recommended that you invest in learning Mercurial properly. Here are some links that can get you started:
This section will give you a more technical description on the details of the build system.
Configurations
diff -Nru openjdk-lts-11.0.11+9/doc/building.md openjdk-lts-11.0.14+9/doc/building.md
--- openjdk-lts-11.0.11+9/doc/building.md 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/doc/building.md 2022-01-13 21:56:25.000000000 +0000
@@ -3,11 +3,11 @@
## TL;DR (Instructions for the Impatient)
If you are eager to try out building the JDK, these simple steps works most of
-the time. They assume that you have installed Mercurial (and Cygwin if running
+the time. They assume that you have installed Git (and Cygwin if running
on Windows) and cloned the top-level JDK repository that you want to build.
1. [Get the complete source code](#getting-the-source-code): \
- `hg clone http://hg.openjdk.java.net/jdk/jdk`
+ `git clone https://git.openjdk.java.net/jdk/`
2. [Run configure](#running-configure): \
`bash configure`
@@ -47,14 +47,14 @@
Make sure you are getting the correct version. As of JDK 10, the source is no
longer split into separate repositories so you only need to clone one single
-repository. At the [OpenJDK Mercurial server](http://hg.openjdk.java.net/) you
-can see a list of all available forests. If you want to build an older version,
+repository. At the [OpenJDK Git site](https://git.openjdk.java.net/) you
+can see a list of all available repositories. If you want to build an older version,
e.g. JDK 8, it is recommended that you get the `jdk8u` forest, which contains
incremental updates, instead of the `jdk8` forest, which was frozen at JDK 8 GA.
-If you are new to Mercurial, a good place to start is the [Mercurial Beginner's
-Guide](http://www.mercurial-scm.org/guide). The rest of this document assumes a
-working knowledge of Mercurial.
+If you are new to Git, a good place to start is the book [Pro
+Git](https://git-scm.com/book/en/v2). The rest of this document
+assumes a working knowledge of Git.
### Special Considerations
@@ -89,9 +89,21 @@
directory. This is especially important if your user name contains
spaces and/or mixed upper and lower case letters.
- * Clone the JDK repository using the Cygwin command line `hg` client
- as instructed in this document. That is, do *not* use another Mercurial
- client such as TortoiseHg.
+ * You need to install a git client. You have two choices, Cygwin git or
+ Git for Windows. Unfortunately there are pros and cons with each choice.
+
+ * The Cygwin `git` client has no line ending issues and understands
+ Cygwin paths (which are used throughout the JDK build system).
+ However, it does not currently work well with the Skara CLI tooling.
+ Please see the [Skara wiki on Git clients](
+ https://wiki.openjdk.java.net/display/SKARA/Skara#Skara-Git) for
+ up-to-date information about the Skara git client support.
+
+ * The [Git for Windows](https://gitforwindows.org) client has issues
+ with line endings, and do not understand Cygwin paths. It does work
+ well with the Skara CLI tooling, however. To alleviate the line ending
+ problems, make sure you set `core.autocrlf` to `false` (this is asked
+ during installation).
Failure to follow this procedure might result in hard-to-debug build
problems.
@@ -171,7 +183,7 @@
require effort to implement.)
Internally in the build system, all paths are represented as Unix-style paths,
-e.g. `/cygdrive/c/hg/jdk9/Makefile` rather than `C:\hg\jdk9\Makefile`. This
+e.g. `/cygdrive/c/git/jdk/Makefile` rather than `C:\git\jdk\Makefile`. This
rule also applies to input to the build system, e.g. in arguments to
`configure`. So, use `--with-msvcr-dll=/cygdrive/c/msvcr100.dll` rather than
`--with-msvcr-dll=c:\msvcr100.dll`. For details on this conversion, see the section
@@ -371,7 +383,7 @@
The minimum accepted version of Visual Studio is 2010. Older versions will not
be accepted by `configure`. The maximum accepted version of Visual Studio is
-2017. Versions older than 2017 are unlikely to continue working for long.
+2019. Versions older than 2017 are unlikely to continue working for long.
If you have multiple versions of Visual Studio installed, `configure` will by
default pick the latest. You can request a specific version to be used by
@@ -1088,23 +1100,39 @@
For example, cross-compiling to AArch64 from x86_64 could be done like this:
* Install cross-compiler on the *build* system:
-```
-apt install g++-aarch64-linux-gnu gcc-aarch64-linux-gnu
-```
+ ```
+ apt install g++-aarch64-linux-gnu gcc-aarch64-linux-gnu
+ ```
* Create chroot on the *build* system, configuring it for *target* system:
-```
-sudo qemu-debootstrap --arch=arm64 --verbose \
- --include=fakeroot,build-essential,libx11-dev,libxext-dev,libxrender-dev,libxtst-dev,libxt-dev,libcups2-dev,libfontconfig1-dev,libasound2-dev,libfreetype6-dev,libpng12-dev \
- --resolve-deps jessie /chroots/arm64 http://httpredir.debian.org/debian/
-```
+ ```
+ sudo qemu-debootstrap \
+ --arch=arm64 \
+ --verbose \
+ --include=fakeroot,symlinks,build-essential,libx11-dev,libxext-dev,libxrender-dev,libxrandr-dev,libxtst-dev,libxt-dev,libcups2-dev,libfontconfig1-dev,libasound2-dev,libfreetype6-dev,libpng-dev \
+ --resolve-deps \
+ buster \
+ ~/sysroot-arm64 \
+ http://httpredir.debian.org/debian/
+ ```
+
+ * Make sure the symlinks inside the newly created chroot point to proper locations:
+ ```
+ sudo chroot ~/sysroot-arm64 symlinks -cr .
+ ```
* Configure and build with newly created chroot as sysroot/toolchain-path:
-```
-CC=aarch64-linux-gnu-gcc CXX=aarch64-linux-gnu-g++ sh ./configure --openjdk-target=aarch64-linux-gnu --with-sysroot=/chroots/arm64/ --with-toolchain-path=/chroots/arm64/
-make images
-ls build/linux-aarch64-normal-server-release/
-```
+ ```
+ CC=aarch64-linux-gnu-gcc CXX=aarch64-linux-gnu-g++ sh ./configure \
+ --openjdk-target=aarch64-linux-gnu \
+ --with-sysroot=~/sysroot-arm64 \
+ --with-toolchain-path=~/sysroot-arm64 \
+ --with-freetype-lib=~/sysroot-arm64/usr/lib/aarch64-linux-gnu/ \
+ --with-freetype-include=~/sysroot-arm64/usr/include/freetype2/ \
+ --x-libraries=~/sysroot-arm64/usr/lib/aarch64-linux-gnu/
+ make images
+ ls build/linux-aarch64-normal-server-release/
+ ```
The build does not create new files in that chroot, so it can be reused for multiple builds
without additional cleanup.
@@ -1261,14 +1289,14 @@
=== Output from failing command(s) repeated here ===
* For target hotspot_variant-server_libjvm_objs_psMemoryPool.o:
-/localhome/hg/jdk9-sandbox/hotspot/src/share/vm/services/psMemoryPool.cpp:1:1: error: 'failhere' does not name a type
+/localhome/git/jdk-sandbox/hotspot/src/share/vm/services/psMemoryPool.cpp:1:1: error: 'failhere' does not name a type
... (rest of output omitted)
-* All command lines available in /localhome/hg/jdk9-sandbox/build/linux-x64/make-support/failure-logs.
+* All command lines available in /localhome/git/jdk-sandbox/build/linux-x64/make-support/failure-logs.
=== End of repeated output ===
=== Make failed targets repeated here ===
-lib/CompileJvm.gmk:207: recipe for target '/localhome/hg/jdk9-sandbox/build/linux-x64/hotspot/variant-server/libjvm/objs/psMemoryPool.o' failed
+lib/CompileJvm.gmk:207: recipe for target '/localhome/git/jdk-sandbox/build/linux-x64/hotspot/variant-server/libjvm/objs/psMemoryPool.o' failed
make/Main.gmk:263: recipe for target 'hotspot-server-libs' failed
=== End of repeated output ===
@@ -1358,17 +1386,15 @@
affected parts get rebuilt. While this works great in most cases, and
significantly speed up the development process, from time to time complex
interdependencies will result in an incorrect build result. This is the most
-common cause for unexpected build problems, together with inconsistencies
-between the different Mercurial repositories in the forest.
+common cause for unexpected build problems.
Here are a suggested list of things to try if you are having unexpected build
problems. Each step requires more time than the one before, so try them in
order. Most issues will be solved at step 1 or 2.
- 1. Make sure your forest is up-to-date
+ 1. Make sure your repository is up-to-date
- Run `bash get_source.sh` to make sure you have the latest version of all
- repositories.
+ Run `git pull origin master` to make sure you have the latest changes.
2. Clean build results
@@ -1393,13 +1419,13 @@
make
```
- 4. Re-clone the Mercurial forest
+ 4. Re-clone the Git repository
- Sometimes the Mercurial repositories themselves gets in a state that causes
- the product to be un-buildable. In such a case, the simplest solution is
- often the "sledgehammer approach": delete the entire forest, and re-clone
- it. If you have local changes, save them first to a different location
- using `hg export`.
+ Sometimes the Git repository gets in a state that causes the product
+ to be un-buildable. In such a case, the simplest solution is often the
+ "sledgehammer approach": delete the entire repository, and re-clone it.
+ If you have local changes, save them first to a different location using
+ `git format-patch`.
### Specific Build Issues
@@ -1450,38 +1476,6 @@
## Hints and Suggestions for Advanced Users
-### Setting Up a Forest for Pushing Changes (defpath)
-
-To help you prepare a proper push path for a Mercurial repository, there exists
-a useful tool known as [defpath](
-http://openjdk.java.net/projects/code-tools/defpath). It will help you setup a
-proper push path for pushing changes to the JDK.
-
-Install the extension by cloning
-`http://hg.openjdk.java.net/code-tools/defpath` and updating your `.hgrc` file.
-Here's one way to do this:
-
-```
-cd ~
-mkdir hg-ext
-cd hg-ext
-hg clone http://hg.openjdk.java.net/code-tools/defpath
-cat << EOT >> ~/.hgrc
-[extensions]
-defpath=~/hg-ext/defpath/defpath.py
-EOT
-```
-
-You can now setup a proper push path using:
-```
-hg defpath -d -u
-```
-
-If you also have the `trees` extension installed in Mercurial, you will
-automatically get a `tdefpath` command, which is even more useful. By running
-`hg tdefpath -du ` in the top repository of your forest, all repos
-will get setup automatically. This is the recommended usage.
-
### Bash Completion
The `configure` and `make` commands tries to play nice with bash command-line
@@ -1624,16 +1618,6 @@
`make java.base-java-only JDK_FILTER=javax/crypto`) will limit the compilation
to files in the `javax.crypto` package.
-### Learn About Mercurial
-
-To become an efficient JDK developer, it is recommended that you invest in
-learning Mercurial properly. Here are some links that can get you started:
-
- * [Mercurial for git users](http://www.mercurial-scm.org/wiki/GitConcepts)
- * [The official Mercurial tutorial](http://www.mercurial-scm.org/wiki/Tutorial)
- * [hg init](http://hginit.com/)
- * [Mercurial: The Definitive Guide](http://hgbook.red-bean.com/read/)
-
## Understanding the Build System
This section will give you a more technical description on the details of the
diff -Nru openjdk-lts-11.0.11+9/doc/testing.html openjdk-lts-11.0.14+9/doc/testing.html
--- openjdk-lts-11.0.11+9/doc/testing.html 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/doc/testing.html 2022-01-13 21:56:25.000000000 +0000
@@ -27,6 +27,7 @@
All functionality is available using the run-test make target. In this use case, the test or tests to be executed is controlled using the TEST variable. To speed up subsequent test runs with no source code changes, run-test-only can be used instead, which do not depend on the source and test image build.
For some common top-level tests, direct make targets have been generated. This includes all JTReg test groups, the hotspot gtest, and custom tests (if present). This means that make run-test-tier1 is equivalent to make run-test TEST="tier1", but the latter is more tab-completion friendly. For more complex test runs, the run-test TEST="x" solution needs to be used.
The test specifications given in TEST is parsed into fully qualified test descriptors, which clearly and unambigously show which tests will be run. As an example, :tier1 will expand to jtreg:$(TOPDIR)/test/hotspot/jtreg:tier1 jtreg:$(TOPDIR)/test/jdk:tier1 jtreg:$(TOPDIR)/test/langtools:tier1 jtreg:$(TOPDIR)/test/nashorn:tier1 jtreg:$(TOPDIR)/test/jaxp:tier1. You can always submit a list of fully qualified test descriptors in the TEST variable if you want to shortcut the parser.
+
Common Test Groups
+
Ideally, all tests are run for every change but this may not be practical due to the limited testing resources, the scope of the change, etc.
+
The source tree currently defines a few common test groups in the relevant TEST.groups files. There are test groups that cover a specific component, for example hotspot_gc. It is a good idea to look into TEST.groups files to get a sense what tests are relevant to a particular JDK component.
+
Component-specific tests may miss some unintended consequences of a change, so other tests should also be run. Again, it might be impractical to run all tests, and therefore tiered test groups exist. Tiered test groups are not component-specific, but rather cover the significant parts of the entire JDK.
+
Multiple tiers allow balancing test coverage and testing costs. Lower test tiers are supposed to contain the simpler, quicker and more stable tests. Higher tiers are supposed to contain progressively more thorough, slower, and sometimes less stable tests, or the tests that require special configuration.
+
Contributors are expected to run the tests for the areas that are changed, and the first N tiers they can afford to run, but at least tier1.
+
A brief description of the tiered test groups:
+
+
tier1: This is the lowest test tier. Multiple developers run these tests every day. Because of the widespread use, the tests in tier1 are carefully selected and optimized to run fast, and to run in the most stable manner. The test failures in tier1 are usually followed up on quickly, either with fixes, or adding relevant tests to problem list. GitHub Actions workflows, if enabled, run tier1 tests.
+
tier2: This test group covers even more ground. These contain, among other things, tests that either run for too long to be at tier1, or may require special configuration, or tests that are less stable, or cover the broader range of non-core JVM and JDK features/components (for example, XML).
+
tier3: This test group includes more stressful tests, the tests for corner cases not covered by previous tiers, plus the tests that require GUIs. As such, this suite should either be run with low concurrency (TEST_JOBS=1), or without headful tests (JTREG_KEYWORDS=\!headful), or both.
+
tier4: This test group includes every other test not covered by previous tiers. It includes, for example, vmTestbase suites for Hotspot, which run for many hours even on large machines. It also runs GUI tests, so the same TEST_JOBS and JTREG_KEYWORDS caveats apply.
+
JTReg
JTReg tests can be selected either by picking a JTReg test group, or a selection of files or directories containing JTReg tests.
JTReg test groups can be specified either without a test root, e.g. :tier1 (or tier1, the initial colon is optional), or with, e.g. hotspot:tier1, test/jdk:jdk_util or $(TOPDIR)/test/hotspot/jtreg:hotspot_all. The test root can be specified either as an absolute path, or a path relative to the JDK top directory, or the test directory. For simplicity, the hotspot JTReg test root, which really is hotspot/jtreg can be abbreviated as just hotspot.
@@ -142,6 +156,8 @@
Additional VM options to JTReg (-vmoption).
AOT_MODULES
Generate AOT modules before testing for the specified module, or set of modules. If multiple modules are specified, they should be separated by space (or, to help avoid quoting issues, the special value %20).
+
RETRY_COUNT
+
Retry failed tests up to a set number of times. Defaults to 0.
Gtest keywords
REPEAT
The number of times to repeat the tests (--gtest_repeat).
diff -Nru openjdk-lts-11.0.11+9/doc/testing.md openjdk-lts-11.0.14+9/doc/testing.md
--- openjdk-lts-11.0.11+9/doc/testing.md 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/doc/testing.md 2022-01-13 21:56:25.000000000 +0000
@@ -52,6 +52,52 @@
always submit a list of fully qualified test descriptors in the `TEST` variable
if you want to shortcut the parser.
+### Common Test Groups
+
+Ideally, all tests are run for every change but this may not be practical due to the limited
+testing resources, the scope of the change, etc.
+
+The source tree currently defines a few common test groups in the relevant `TEST.groups`
+files. There are test groups that cover a specific component, for example `hotspot_gc`.
+It is a good idea to look into `TEST.groups` files to get a sense what tests are relevant
+to a particular JDK component.
+
+Component-specific tests may miss some unintended consequences of a change, so other
+tests should also be run. Again, it might be impractical to run all tests, and therefore
+_tiered_ test groups exist. Tiered test groups are not component-specific, but rather cover
+the significant parts of the entire JDK.
+
+Multiple tiers allow balancing test coverage and testing costs. Lower test tiers are supposed to
+contain the simpler, quicker and more stable tests. Higher tiers are supposed to contain
+progressively more thorough, slower, and sometimes less stable tests, or the tests that require
+special configuration.
+
+Contributors are expected to run the tests for the areas that are changed, and the first N tiers
+they can afford to run, but at least tier1.
+
+A brief description of the tiered test groups:
+
+- `tier1`: This is the lowest test tier. Multiple developers run these tests every day.
+Because of the widespread use, the tests in `tier1` are carefully selected and optimized to run
+fast, and to run in the most stable manner. The test failures in `tier1` are usually followed up
+on quickly, either with fixes, or adding relevant tests to problem list. GitHub Actions workflows,
+if enabled, run `tier1` tests.
+
+- `tier2`: This test group covers even more ground. These contain, among other things,
+tests that either run for too long to be at `tier1`, or may require special configuration,
+or tests that are less stable, or cover the broader range of non-core JVM and JDK features/components
+(for example, XML).
+
+- `tier3`: This test group includes more stressful tests, the tests for corner cases
+not covered by previous tiers, plus the tests that require GUIs. As such, this suite
+should either be run with low concurrency (`TEST_JOBS=1`), or without headful tests
+(`JTREG_KEYWORDS=\!headful`), or both.
+
+- `tier4`: This test group includes every other test not covered by previous tiers. It includes,
+for example, `vmTestbase` suites for Hotspot, which run for many hours even on large
+machines. It also runs GUI tests, so the same `TEST_JOBS` and `JTREG_KEYWORDS` caveats
+apply.
+
### JTReg
JTReg tests can be selected either by picking a JTReg test group, or a selection
@@ -269,6 +315,10 @@
modules. If multiple modules are specified, they should be separated by space
(or, to help avoid quoting issues, the special value `%20`).
+#### RETRY_COUNT
+
+Retry failed tests up to a set number of times. Defaults to 0.
+
### Gtest keywords
#### REPEAT
diff -Nru openjdk-lts-11.0.11+9/.hg_archival.txt openjdk-lts-11.0.14+9/.hg_archival.txt
--- openjdk-lts-11.0.11+9/.hg_archival.txt 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/.hg_archival.txt 1970-01-01 00:00:00.000000000 +0000
@@ -1,5 +0,0 @@
-repo: fd16c54261b32be1aaedd863b7e856801b7f8543
-node: 15862747ee15445292b4b9949b4f0f4badba4812
-branch: default
-tag: jdk-11.0.11+9
-tag: jdk-11.0.11-ga
diff -Nru openjdk-lts-11.0.11+9/.hgtags openjdk-lts-11.0.14+9/.hgtags
--- openjdk-lts-11.0.11+9/.hgtags 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/.hgtags 2022-01-13 21:56:25.000000000 +0000
@@ -636,6 +636,17 @@
14cc036b17a5f4be5b0643e6b24ed32563684ab9 jdk-11.0.11+3
c4405735470a92e2c45490b89a8099252f3481d2 jdk-11.0.11+4
38430a8a4488582612c6a87ab58d109cc5217e8b jdk-11.0.11+5
+595a965d85afdd01c30dbc7b2efd75f4cb202816 jdk-11.0.12+0
e41ae00add1d76a8f25adb558933382947ea840d jdk-11.0.11+6
14f9928caac31368d27f13e4e21ca25c1e0be950 jdk-11.0.11+7
9f0347b029d3a0349f23befcfb68ee02d85d9034 jdk-11.0.11+8
+15862747ee15445292b4b9949b4f0f4badba4812 jdk-11.0.11+9
+15862747ee15445292b4b9949b4f0f4badba4812 jdk-11.0.11-ga
+5720ffa08f8514b9f0ea8b3a49e05a872c9c0efe jdk-11.0.12+1
+70a4031a8bef3e693f34864fdd482429c73dc76a jdk-11.0.12+2
+873a691b1ae4fa8b55ca5d08fa21aca3a4904fb8 jdk-11.0.12+3
+40d1e784e1937aaea696a9654cc2d944d3d78996 jdk-11.0.12+4
+6aa6f6860508fca3a97aea1de7a36574498d22bf jdk-11.0.12+5
+91e81ac088545abdc3eaaa707853d31a6cf99af3 jdk-11.0.12+6
+f412f2537f1502a9697a9684c77bea8d848db1ab jdk-11.0.12+7
+f412f2537f1502a9697a9684c77bea8d848db1ab jdk-11.0.12-ga
diff -Nru openjdk-lts-11.0.11+9/.jcheck/conf openjdk-lts-11.0.14+9/.jcheck/conf
--- openjdk-lts-11.0.11+9/.jcheck/conf 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/.jcheck/conf 2022-01-13 21:56:25.000000000 +0000
@@ -1,2 +1,31 @@
-project=jdk10
-bugids=dup
+[general]
+project=jdk-updates
+jbs=JDK
+version=11.0.14
+
+[checks]
+error=author,committer,reviewers,merge,issues,executable,symlink,message,hg-tag,whitespace
+
+[repository]
+tags=(?:jdk-(?:[1-9]([0-9]*)(?:\.(?:0|[1-9][0-9]*)){0,4})(?:\+(?:(?:[0-9]+))|(?:-ga)))|(?:jdk[4-9](?:u\d{1,3})?-(?:(?:b\d{2,3})|(?:ga)))|(?:hs\d\d(?:\.\d{1,2})?-b\d\d)
+branches=
+
+[census]
+version=0
+domain=openjdk.org
+
+[checks "whitespace"]
+files=.*\.cpp|.*\.hpp|.*\.c|.*\.h|.*\.java
+
+[checks "merge"]
+message=Merge
+
+[checks "reviewers"]
+reviewers=1
+ignore=duke
+
+[checks "committer"]
+role=committer
+
+[checks "issues"]
+pattern=^([124-8][0-9]{6}): (\S.*)$
diff -Nru openjdk-lts-11.0.11+9/make/autoconf/basics.m4 openjdk-lts-11.0.14+9/make/autoconf/basics.m4
--- openjdk-lts-11.0.11+9/make/autoconf/basics.m4 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/make/autoconf/basics.m4 2022-01-13 21:56:25.000000000 +0000
@@ -673,6 +673,16 @@
])
###############################################################################
+# Evaluates platform specific overrides for build devkit variables.
+# $1: Name of variable
+AC_DEFUN([BASIC_EVAL_BUILD_DEVKIT_VARIABLE],
+[
+ if test "x[$]$1" = x; then
+ eval $1="\${$1_${OPENJDK_BUILD_CPU}}"
+ fi
+])
+
+###############################################################################
AC_DEFUN_ONCE([BASIC_SETUP_DEVKIT],
[
AC_ARG_WITH([devkit], [AS_HELP_STRING([--with-devkit],
diff -Nru openjdk-lts-11.0.11+9/make/autoconf/basics_windows.m4 openjdk-lts-11.0.14+9/make/autoconf/basics_windows.m4
--- openjdk-lts-11.0.11+9/make/autoconf/basics_windows.m4 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/make/autoconf/basics_windows.m4 2022-01-13 21:56:25.000000000 +0000
@@ -381,10 +381,44 @@
# called fixpath.
FIXPATH=
if test "x$OPENJDK_BUILD_OS" = xwindows; then
- AC_MSG_CHECKING([if fixpath can be created])
FIXPATH_SRC="$TOPDIR/make/src/native/fixpath.c"
- FIXPATH_BIN="$CONFIGURESUPPORT_OUTPUTDIR/bin/fixpath.exe"
FIXPATH_DIR="$CONFIGURESUPPORT_OUTPUTDIR/fixpath"
+
+ if test "x$OPENJDK_TARGET_CPU" != "xaarch64"; then
+ AC_MSG_CHECKING([if fixpath can be created])
+
+ FIXPATH_BIN="$CONFIGURESUPPORT_OUTPUTDIR/bin/fixpath.exe"
+ FIXPATH_SRC_W="$FIXPATH_SRC"
+ FIXPATH_BIN_W="$FIXPATH_BIN"
+ BASIC_WINDOWS_REWRITE_AS_WINDOWS_MIXED_PATH([FIXPATH_SRC_W])
+ BASIC_WINDOWS_REWRITE_AS_WINDOWS_MIXED_PATH([FIXPATH_BIN_W])
+ $RM -rf $FIXPATH_BIN $FIXPATH_DIR
+ $MKDIR -p $FIXPATH_DIR $CONFIGURESUPPORT_OUTPUTDIR/bin
+ cd $FIXPATH_DIR
+ $CC $FIXPATH_SRC_W -Fe$FIXPATH_BIN_W > $FIXPATH_DIR/fixpath1.log 2>&1
+ cd $CURDIR
+
+ if test ! -x $FIXPATH_BIN; then
+ AC_MSG_RESULT([no])
+ cat $FIXPATH_DIR/fixpath1.log
+ AC_MSG_ERROR([Could not create $FIXPATH_BIN])
+ fi
+ AC_MSG_RESULT([yes])
+
+ else # OPENJDK_TARGET_CPU is aarch64
+ AC_MSG_CHECKING([if fixpath is in place])
+
+ FIXPATH_BIN="$TOPDIR/fixpath.exe"
+ $RM -rf $FIXPATH_DIR
+ $MKDIR -p $FIXPATH_DIR
+
+ if test ! -x $FIXPATH_BIN; then
+ AC_MSG_RESULT([no])
+ AC_MSG_ERROR([Could not find fixpath.exe under $TOPDIR])
+ fi
+ AC_MSG_RESULT([yes])
+ fi
+
if test "x$OPENJDK_BUILD_OS_ENV" = xwindows.cygwin; then
# Important to keep the .exe suffix on Cygwin for Hotspot makefiles
FIXPATH="$FIXPATH_BIN -c"
@@ -396,22 +430,7 @@
fixpath_argument_list=`echo $all_unique_prefixes | tr ' ' '@'`
FIXPATH="$FIXPATH_BIN -m$fixpath_argument_list"
fi
- FIXPATH_SRC_W="$FIXPATH_SRC"
- FIXPATH_BIN_W="$FIXPATH_BIN"
- BASIC_WINDOWS_REWRITE_AS_WINDOWS_MIXED_PATH([FIXPATH_SRC_W])
- BASIC_WINDOWS_REWRITE_AS_WINDOWS_MIXED_PATH([FIXPATH_BIN_W])
- $RM -rf $FIXPATH_BIN $FIXPATH_DIR
- $MKDIR -p $FIXPATH_DIR $CONFIGURESUPPORT_OUTPUTDIR/bin
- cd $FIXPATH_DIR
- $CC $FIXPATH_SRC_W -Fe$FIXPATH_BIN_W > $FIXPATH_DIR/fixpath1.log 2>&1
- cd $CURDIR
- if test ! -x $FIXPATH_BIN; then
- AC_MSG_RESULT([no])
- cat $FIXPATH_DIR/fixpath1.log
- AC_MSG_ERROR([Could not create $FIXPATH_BIN])
- fi
- AC_MSG_RESULT([yes])
AC_MSG_CHECKING([if fixpath.exe works])
cd $FIXPATH_DIR
$FIXPATH $CC $FIXPATH_SRC -Fe$FIXPATH_DIR/fixpath2.exe \
diff -Nru openjdk-lts-11.0.11+9/make/autoconf/build-aux/config.guess openjdk-lts-11.0.14+9/make/autoconf/build-aux/config.guess
--- openjdk-lts-11.0.11+9/make/autoconf/build-aux/config.guess 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/make/autoconf/build-aux/config.guess 2022-01-13 21:56:25.000000000 +0000
@@ -97,6 +97,15 @@
fi
fi
+# Test and fix LoongArch64.
+if [ "x$OUT" = x ]; then
+ if [ `uname -s` = Linux ]; then
+ if [ `uname -m` = loongarch64 ]; then
+ OUT=loongarch64-unknown-linux-gnu
+ fi
+ fi
+fi
+
# Test and fix cpu on Macosx when C preprocessor is not on the path
echo $OUT | grep i386-apple-darwin > /dev/null 2> /dev/null
if test $? = 0; then
diff -Nru openjdk-lts-11.0.11+9/make/autoconf/flags-cflags.m4 openjdk-lts-11.0.14+9/make/autoconf/flags-cflags.m4
--- openjdk-lts-11.0.11+9/make/autoconf/flags-cflags.m4 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/make/autoconf/flags-cflags.m4 2022-01-13 21:56:25.000000000 +0000
@@ -391,16 +391,6 @@
CFLAGS="$CFLAGS_OLD"
CXXFLAGS="$CXXFLAGS_OLD"
- # Tests are only ever compiled for TARGET
- CFLAGS_TESTLIB="$CFLAGS_JDKLIB"
- CXXFLAGS_TESTLIB="$CXXFLAGS_JDKLIB"
- CFLAGS_TESTEXE="$CFLAGS_JDKEXE"
- CXXFLAGS_TESTEXE="$CXXFLAGS_JDKEXE"
-
- AC_SUBST(CFLAGS_TESTLIB)
- AC_SUBST(CFLAGS_TESTEXE)
- AC_SUBST(CXXFLAGS_TESTLIB)
- AC_SUBST(CXXFLAGS_TESTEXE)
])
################################################################################
@@ -705,7 +695,9 @@
$1_DEFINES_CPU_JDK="${$1_DEFINES_CPU_JDK} -DcpuIntel -Di586 -D$FLAGS_CPU_LEGACY_LIB"
fi
elif test "x$TOOLCHAIN_TYPE" = xmicrosoft; then
- if test "x$FLAGS_CPU" = xx86_64; then
+ if test "x$FLAGS_CPU" = xaarch64; then
+ $1_DEFINES_CPU_JDK="${$1_DEFINES_CPU_JDK} -D_ARM64_ -Darm64"
+ elif test "x$FLAGS_CPU" = xx86_64; then
$1_DEFINES_CPU_JDK="${$1_DEFINES_CPU_JDK} -D_AMD64_ -Damd64"
else
$1_DEFINES_CPU_JDK="${$1_DEFINES_CPU_JDK} -D_X86_ -Dx86"
diff -Nru openjdk-lts-11.0.11+9/make/autoconf/flags-ldflags.m4 openjdk-lts-11.0.14+9/make/autoconf/flags-ldflags.m4
--- openjdk-lts-11.0.11+9/make/autoconf/flags-ldflags.m4 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/make/autoconf/flags-ldflags.m4 2022-01-13 21:56:25.000000000 +0000
@@ -51,9 +51,7 @@
FLAGS_SETUP_LDFLAGS_CPU_DEP([BUILD], [OPENJDK_BUILD_])
- LDFLAGS_TESTLIB="$LDFLAGS_JDKLIB"
- LDFLAGS_TESTEXE="$LDFLAGS_JDKEXE ${TARGET_LDFLAGS_JDK_LIBPATH}"
- AC_SUBST(LDFLAGS_TESTLIB)
+ LDFLAGS_TESTEXE="${TARGET_LDFLAGS_JDK_LIBPATH}"
AC_SUBST(LDFLAGS_TESTEXE)
])
@@ -187,12 +185,14 @@
$1_CPU_LDFLAGS_JVM_ONLY="-xarch=sparc"
fi
- elif test "x$TOOLCHAIN_TYPE" = xmicrosoft; then
+ elif test "x$TOOLCHAIN_TYPE" = xmicrosoft; then
if test "x${OPENJDK_$1_CPU}" = "xx86"; then
$1_CPU_LDFLAGS="-safeseh"
# NOTE: Old build added -machine. Probably not needed.
$1_CPU_LDFLAGS_JVM_ONLY="-machine:I386"
$1_CPU_EXECUTABLE_LDFLAGS="-stack:327680"
+ elif test "x${OPENJDK_$1_CPU}" = "xaarch64"; then
+ $1_CPU_EXECUTABLE_LDFLAGS="-stack:1048576"
else
$1_CPU_LDFLAGS_JVM_ONLY="-machine:AMD64"
$1_CPU_EXECUTABLE_LDFLAGS="-stack:1048576"
diff -Nru openjdk-lts-11.0.11+9/make/autoconf/flags.m4 openjdk-lts-11.0.14+9/make/autoconf/flags.m4
--- openjdk-lts-11.0.11+9/make/autoconf/flags.m4 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/make/autoconf/flags.m4 2022-01-13 21:56:25.000000000 +0000
@@ -224,10 +224,12 @@
# We also need -iframework/System/Library/Frameworks
$1SYSROOT_CFLAGS="[$]$1SYSROOT_CFLAGS -iframework [$]$1SYSROOT/System/Library/Frameworks"
$1SYSROOT_LDFLAGS="[$]$1SYSROOT_LDFLAGS -iframework [$]$1SYSROOT/System/Library/Frameworks"
- # These always need to be set, or we can't find the frameworks embedded in JavaVM.framework
- # set this here so it doesn't have to be peppered throughout the forest
- $1SYSROOT_CFLAGS="[$]$1SYSROOT_CFLAGS -F [$]$1SYSROOT/System/Library/Frameworks/JavaVM.framework/Frameworks"
- $1SYSROOT_LDFLAGS="[$]$1SYSROOT_LDFLAGS -F [$]$1SYSROOT/System/Library/Frameworks/JavaVM.framework/Frameworks"
+ if test -d "[$]$1SYSROOT/System/Library/Frameworks/JavaVM.framework/Frameworks" ; then
+ # These always need to be set on macOS 10.X, or we can't find the frameworks embedded in JavaVM.framework
+ # set this here so it doesn't have to be peppered throughout the forest
+ $1SYSROOT_CFLAGS="[$]$1SYSROOT_CFLAGS -F [$]$1SYSROOT/System/Library/Frameworks/JavaVM.framework/Frameworks"
+ $1SYSROOT_LDFLAGS="[$]$1SYSROOT_LDFLAGS -F [$]$1SYSROOT/System/Library/Frameworks/JavaVM.framework/Frameworks"
+ fi
fi
AC_SUBST($1SYSROOT_CFLAGS)
diff -Nru openjdk-lts-11.0.11+9/make/autoconf/flags-other.m4 openjdk-lts-11.0.14+9/make/autoconf/flags-other.m4
--- openjdk-lts-11.0.11+9/make/autoconf/flags-other.m4 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/make/autoconf/flags-other.m4 2022-01-13 21:56:25.000000000 +0000
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2011, 2019, Oracle and/or its affiliates. All rights reserved.
+# Copyright (c) 2011, 2021, Oracle and/or its affiliates. All rights reserved.
# DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
#
# This code is free software; you can redistribute it and/or modify it
@@ -107,6 +107,16 @@
[
if test "x$OPENJDK_TARGET_OS" = xmacosx; then
JVM_BASIC_ASFLAGS="-x assembler-with-cpp -mno-omit-leaf-frame-pointer -mstack-alignment=16"
+
+ # Fix linker warning.
+ # Code taken from make/autoconf/flags-cflags.m4 and adapted.
+ JVM_BASIC_ASFLAGS+=" -DMAC_OS_X_VERSION_MIN_REQUIRED=$MACOSX_VERSION_MIN_NODOTS \
+ -mmacosx-version-min=$MACOSX_VERSION_MIN"
+
+ if test -n "$MACOSX_VERSION_MAX"; then
+ JVM_BASIC_ASFLAGS+=" $OS_CFLAGS \
+ -DMAC_OS_X_VERSION_MAX_ALLOWED=$MACOSX_VERSION_MAX_NODOTS"
+ fi
fi
])
diff -Nru openjdk-lts-11.0.11+9/make/autoconf/help.m4 openjdk-lts-11.0.14+9/make/autoconf/help.m4
--- openjdk-lts-11.0.11+9/make/autoconf/help.m4 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/make/autoconf/help.m4 2022-01-13 21:56:25.000000000 +0000
@@ -90,7 +90,7 @@
devkit)
PKGHANDLER_COMMAND="sudo apt-get install build-essential" ;;
openjdk)
- PKGHANDLER_COMMAND="sudo apt-get install openjdk-8-jdk" ;;
+ PKGHANDLER_COMMAND="sudo apt-get install openjdk-11-jdk" ;;
alsa)
PKGHANDLER_COMMAND="sudo apt-get install libasound2-dev" ;;
cups)
@@ -117,7 +117,7 @@
devkit)
PKGHANDLER_COMMAND="sudo yum groupinstall \"Development Tools\"" ;;
openjdk)
- PKGHANDLER_COMMAND="sudo yum install java-1.8.0-openjdk-devel" ;;
+ PKGHANDLER_COMMAND="sudo yum install java-11-openjdk-devel" ;;
alsa)
PKGHANDLER_COMMAND="sudo yum install alsa-lib-devel" ;;
cups)
diff -Nru openjdk-lts-11.0.11+9/make/autoconf/hotspot.m4 openjdk-lts-11.0.14+9/make/autoconf/hotspot.m4
--- openjdk-lts-11.0.11+9/make/autoconf/hotspot.m4 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/make/autoconf/hotspot.m4 2022-01-13 21:56:25.000000000 +0000
@@ -221,7 +221,7 @@
if test "x$ENABLE_AOT" = "xtrue"; then
# Only enable AOT on X64 platforms.
- if test "x$OPENJDK_TARGET_CPU" = "xx86_64" || test "x$OPENJDK_TARGET_CPU" = "xaarch64" ; then
+ if test "x$OPENJDK_TARGET_CPU" = "xx86_64" || test "x$OPENJDK_TARGET_OS-$OPENJDK_TARGET_CPU" = "xlinux-aarch64" ; then
if test -e "${TOPDIR}/src/jdk.aot"; then
if test -e "${TOPDIR}/src/jdk.internal.vm.compiler"; then
ENABLE_AOT="true"
@@ -240,7 +240,7 @@
else
ENABLE_AOT="false"
if test "x$enable_aot" = "xyes"; then
- AC_MSG_ERROR([AOT is currently only supported on x86_64 and aarch64. Remove --enable-aot.])
+ AC_MSG_ERROR([AOT is currently only supported on x86_64 and linux-aarch64. Remove --enable-aot.])
fi
fi
fi
@@ -355,7 +355,8 @@
# Only enable Shenandoah on supported arches, and only if requested
AC_MSG_CHECKING([if shenandoah can be built])
if HOTSPOT_CHECK_JVM_FEATURE(shenandoahgc); then
- if test "x$OPENJDK_TARGET_CPU_ARCH" = "xx86" || test "x$OPENJDK_TARGET_CPU" = "xaarch64" ; then
+ if test "x$OPENJDK_TARGET_CPU_ARCH" = "xx86" || \
+ test "x$OPENJDK_TARGET_CPU" = "xaarch64"; then
AC_MSG_RESULT([yes])
else
DISABLED_JVM_FEATURES="$DISABLED_JVM_FEATURES shenandoahgc"
@@ -412,7 +413,7 @@
# Only enable jvmci on x86_64, sparcv9 and aarch64
if test "x$OPENJDK_TARGET_CPU" = "xx86_64" || \
test "x$OPENJDK_TARGET_CPU" = "xsparcv9" || \
- test "x$OPENJDK_TARGET_CPU" = "xaarch64" ; then
+ test "x$OPENJDK_TARGET_OS-$OPENJDK_TARGET_CPU" = "xlinux-aarch64" ; then
AC_MSG_RESULT([yes])
JVM_FEATURES_jvmci="jvmci"
INCLUDE_JVMCI="true"
diff -Nru openjdk-lts-11.0.11+9/make/autoconf/jdk-options.m4 openjdk-lts-11.0.14+9/make/autoconf/jdk-options.m4
--- openjdk-lts-11.0.11+9/make/autoconf/jdk-options.m4 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/make/autoconf/jdk-options.m4 2022-01-13 21:56:25.000000000 +0000
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2011, 2020, Oracle and/or its affiliates. All rights reserved.
+# Copyright (c) 2011, 2021, Oracle and/or its affiliates. All rights reserved.
# DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
#
# This code is free software; you can redistribute it and/or modify it
@@ -291,11 +291,7 @@
[AS_HELP_STRING([--with-native-debug-symbols],
[set the native debug symbol configuration (none, internal, external, zipped) @<:@varying@:>@])],
[
- if test "x$OPENJDK_TARGET_OS" = xaix; then
- if test "x$withval" = xexternal || test "x$withval" = xzipped; then
- AC_MSG_ERROR([AIX only supports the parameters 'none' and 'internal' for --with-native-debug-symbols])
- fi
- elif test "x$OPENJDK_TARGET_OS" = xwindows; then
+ if test "x$OPENJDK_TARGET_OS" = xwindows; then
if test "x$withval" = xinternal; then
AC_MSG_ERROR([Windows does not support the parameter 'internal' for --with-native-debug-symbols])
fi
@@ -305,12 +301,7 @@
if test "x$STATIC_BUILD" = xtrue; then
with_native_debug_symbols="none"
else
- if test "x$OPENJDK_TARGET_OS" = xaix; then
- # AIX doesn't support 'external' so use 'internal' as default
- with_native_debug_symbols="internal"
- else
- with_native_debug_symbols="external"
- fi
+ with_native_debug_symbols="external"
fi
])
AC_MSG_RESULT([$with_native_debug_symbols])
diff -Nru openjdk-lts-11.0.11+9/make/autoconf/lib-freetype.m4 openjdk-lts-11.0.14+9/make/autoconf/lib-freetype.m4
--- openjdk-lts-11.0.11+9/make/autoconf/lib-freetype.m4 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/make/autoconf/lib-freetype.m4 2022-01-13 21:56:25.000000000 +0000
@@ -173,6 +173,16 @@
FREETYPE_BASE_DIR="$SYSROOT/usr"
LIB_CHECK_POTENTIAL_FREETYPE([$FREETYPE_BASE_DIR/include], [$FREETYPE_BASE_DIR/lib], [well-known location])
+ if test "x$FOUND_FREETYPE" != "xyes" ; then
+ LIB_CHECK_POTENTIAL_FREETYPE([$FREETYPE_BASE_DIR/include],
+ [$FREETYPE_BASE_DIR/lib/$OPENJDK_TARGET_CPU-$OPENJDK_TARGET_OS-$OPENJDK_TARGET_ABI], [well-known location])
+ fi
+
+ if test "x$FOUND_FREETYPE" != "xyes" ; then
+ LIB_CHECK_POTENTIAL_FREETYPE([$FREETYPE_BASE_DIR/include],
+ [$FREETYPE_BASE_DIR/lib/$OPENJDK_TARGET_CPU_AUTOCONF-$OPENJDK_TARGET_OS-$OPENJDK_TARGET_ABI], [well-known location])
+ fi
+
if (test "x$FOUND_FREETYPE" != "xyes"); then
FREETYPE_BASE_DIR="$SYSROOT/usr/X11"
LIB_CHECK_POTENTIAL_FREETYPE([$FREETYPE_BASE_DIR/include], [$FREETYPE_BASE_DIR/lib], [well-known location])
diff -Nru openjdk-lts-11.0.11+9/make/autoconf/lib-x11.m4 openjdk-lts-11.0.14+9/make/autoconf/lib-x11.m4
--- openjdk-lts-11.0.11+9/make/autoconf/lib-x11.m4 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/make/autoconf/lib-x11.m4 2022-01-13 21:56:25.000000000 +0000
@@ -68,6 +68,10 @@
x_libraries="$SYSROOT/usr/lib64"
elif test -f "$SYSROOT/usr/lib/libX11.so"; then
x_libraries="$SYSROOT/usr/lib"
+ elif test -f "$SYSROOT/usr/lib/$OPENJDK_TARGET_CPU-$OPENJDK_TARGET_OS-$OPENJDK_TARGET_ABI/libX11.so"; then
+ x_libraries="$SYSROOT/usr/lib/$OPENJDK_TARGET_CPU-$OPENJDK_TARGET_OS-$OPENJDK_TARGET_ABI/libX11.so"
+ elif test -f "$SYSROOT/usr/lib/$OPENJDK_TARGET_CPU_AUTOCONF-$OPENJDK_TARGET_OS-$OPENJDK_TARGET_ABI/libX11.so"; then
+ x_libraries="$SYSROOT/usr/lib/$OPENJDK_TARGET_CPU_AUTOCONF-$OPENJDK_TARGET_OS-$OPENJDK_TARGET_ABI/libX11.so"
fi
fi
fi
diff -Nru openjdk-lts-11.0.11+9/make/autoconf/platform.m4 openjdk-lts-11.0.14+9/make/autoconf/platform.m4
--- openjdk-lts-11.0.11+9/make/autoconf/platform.m4 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/make/autoconf/platform.m4 2022-01-13 21:56:25.000000000 +0000
@@ -66,6 +66,12 @@
VAR_CPU_BITS=64
VAR_CPU_ENDIAN=little
;;
+ loongarch64)
+ VAR_CPU=loongarch64
+ VAR_CPU_ARCH=loongarch
+ VAR_CPU_BITS=64
+ VAR_CPU_ENDIAN=little
+ ;;
m68k)
VAR_CPU=m68k
VAR_CPU_ARCH=m68k
@@ -114,6 +120,12 @@
VAR_CPU_BITS=64
VAR_CPU_ENDIAN=little
;;
+ riscv64)
+ VAR_CPU=riscv64
+ VAR_CPU_ARCH=riscv
+ VAR_CPU_BITS=64
+ VAR_CPU_ENDIAN=little
+ ;;
s390)
VAR_CPU=s390
VAR_CPU_ARCH=s390
@@ -196,6 +208,33 @@
esac
])
+# Support macro for PLATFORM_EXTRACT_TARGET_AND_BUILD.
+# Converts autoconf style OS name to OpenJDK style, into
+# VAR_ABI.
+AC_DEFUN([PLATFORM_EXTRACT_VARS_FROM_ABI],
+[
+ case "$1" in
+ *linux*-musl)
+ VAR_ABI=musl
+ ;;
+ *linux*-gnu)
+ VAR_ABI=gnu
+ ;;
+ *linux*-gnueabi)
+ VAR_ABI=gnueabi
+ ;;
+ *linux*-gnueabihf)
+ VAR_ABI=gnueabihf
+ ;;
+ *linux*-gnuabi64)
+ VAR_ABI=gnuabi64
+ ;;
+ *)
+ VAR_ABI=default
+ ;;
+ esac
+])
+
# Expects $host_os $host_cpu $build_os and $build_cpu
# and $with_target_bits to have been setup!
#
@@ -216,6 +255,7 @@
# Convert the autoconf OS/CPU value to our own data, into the VAR_OS/CPU variables.
PLATFORM_EXTRACT_VARS_FROM_OS($build_os)
PLATFORM_EXTRACT_VARS_FROM_CPU($build_cpu)
+ PLATFORM_EXTRACT_VARS_FROM_ABI($build_os)
# ..and setup our own variables. (Do this explicitly to facilitate searching)
OPENJDK_BUILD_OS="$VAR_OS"
if test "x$VAR_OS_TYPE" != x; then
@@ -232,6 +272,8 @@
OPENJDK_BUILD_CPU_ARCH="$VAR_CPU_ARCH"
OPENJDK_BUILD_CPU_BITS="$VAR_CPU_BITS"
OPENJDK_BUILD_CPU_ENDIAN="$VAR_CPU_ENDIAN"
+ OPENJDK_BUILD_CPU_AUTOCONF="$build_cpu"
+ OPENJDK_BUILD_ABI="$VAR_ABI"
AC_SUBST(OPENJDK_BUILD_OS)
AC_SUBST(OPENJDK_BUILD_OS_TYPE)
AC_SUBST(OPENJDK_BUILD_OS_ENV)
@@ -239,6 +281,8 @@
AC_SUBST(OPENJDK_BUILD_CPU_ARCH)
AC_SUBST(OPENJDK_BUILD_CPU_BITS)
AC_SUBST(OPENJDK_BUILD_CPU_ENDIAN)
+ AC_SUBST(OPENJDK_BUILD_CPU_AUTOCONF)
+ AC_SUBST(OPENJDK_BUILD_ABI)
AC_MSG_CHECKING([openjdk-build os-cpu])
AC_MSG_RESULT([$OPENJDK_BUILD_OS-$OPENJDK_BUILD_CPU])
@@ -246,6 +290,7 @@
# Convert the autoconf OS/CPU value to our own data, into the VAR_OS/CPU variables.
PLATFORM_EXTRACT_VARS_FROM_OS($host_os)
PLATFORM_EXTRACT_VARS_FROM_CPU($host_cpu)
+ PLATFORM_EXTRACT_VARS_FROM_ABI($host_os)
# ... and setup our own variables. (Do this explicitly to facilitate searching)
OPENJDK_TARGET_OS="$VAR_OS"
if test "x$VAR_OS_TYPE" != x; then
@@ -262,7 +307,9 @@
OPENJDK_TARGET_CPU_ARCH="$VAR_CPU_ARCH"
OPENJDK_TARGET_CPU_BITS="$VAR_CPU_BITS"
OPENJDK_TARGET_CPU_ENDIAN="$VAR_CPU_ENDIAN"
+ OPENJDK_TARGET_CPU_AUTOCONF="$host_cpu"
OPENJDK_TARGET_OS_UPPERCASE=`$ECHO $OPENJDK_TARGET_OS | $TR 'abcdefghijklmnopqrstuvwxyz' 'ABCDEFGHIJKLMNOPQRSTUVWXYZ'`
+ OPENJDK_TARGET_ABI="$VAR_ABI"
AC_SUBST(OPENJDK_TARGET_OS)
AC_SUBST(OPENJDK_TARGET_OS_TYPE)
@@ -272,6 +319,8 @@
AC_SUBST(OPENJDK_TARGET_CPU_ARCH)
AC_SUBST(OPENJDK_TARGET_CPU_BITS)
AC_SUBST(OPENJDK_TARGET_CPU_ENDIAN)
+ AC_SUBST(OPENJDK_TARGET_CPU_AUTOCONF)
+ AC_SUBST(OPENJDK_TARGET_ABI)
AC_MSG_CHECKING([openjdk-target os-cpu])
AC_MSG_RESULT([$OPENJDK_TARGET_OS-$OPENJDK_TARGET_CPU])
@@ -473,6 +522,8 @@
HOTSPOT_$1_CPU_DEFINE=S390
elif test "x$OPENJDK_$1_CPU" = xs390x; then
HOTSPOT_$1_CPU_DEFINE=S390
+ elif test "x$OPENJDK_$1_CPU" = xriscv64; then
+ HOTSPOT_$1_CPU_DEFINE=RISCV
elif test "x$OPENJDK_$1_CPU" != x; then
HOTSPOT_$1_CPU_DEFINE=$(echo $OPENJDK_$1_CPU | tr a-z A-Z)
fi
diff -Nru openjdk-lts-11.0.11+9/make/autoconf/spec.gmk.in openjdk-lts-11.0.14+9/make/autoconf/spec.gmk.in
--- openjdk-lts-11.0.11+9/make/autoconf/spec.gmk.in 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/make/autoconf/spec.gmk.in 2022-01-13 21:56:25.000000000 +0000
@@ -382,7 +382,7 @@
export ASAN_ENABLED:=@ASAN_ENABLED@
export DEVKIT_LIB_DIR:=@DEVKIT_LIB_DIR@
ifeq ($(ASAN_ENABLED), yes)
- export ASAN_OPTIONS="handle_segv=0 detect_leaks=0"
+ export ASAN_OPTIONS=handle_segv=0 detect_leaks=0
ifneq ($(DEVKIT_LIB_DIR),)
export LD_LIBRARY_PATH:=$(LD_LIBRARY_PATH):$(DEVKIT_LIB_DIR)
endif
@@ -508,11 +508,6 @@
LIBCXX:=@LIBCXX@
# Compiler and linker flags used when building native tests
-CFLAGS_TESTLIB:=@CFLAGS_TESTLIB@
-CXXFLAGS_TESTLIB:=@CXXFLAGS_TESTLIB@
-CFLAGS_TESTEXE:=@CFLAGS_TESTEXE@
-CXXFLAGS_TESTEXE:=@CXXFLAGS_TESTEXE@
-LDFLAGS_TESTLIB:=@LDFLAGS_TESTLIB@
LDFLAGS_TESTEXE:=@LDFLAGS_TESTEXE@
# BUILD_CC/BUILD_LD is a compiler/linker that generates code that is runnable on the
diff -Nru openjdk-lts-11.0.11+9/make/autoconf/toolchain.m4 openjdk-lts-11.0.14+9/make/autoconf/toolchain.m4
--- openjdk-lts-11.0.11+9/make/autoconf/toolchain.m4 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/make/autoconf/toolchain.m4 2022-01-13 21:56:25.000000000 +0000
@@ -918,14 +918,18 @@
. $CONFIGURESUPPORT_OUTPUTDIR/build-devkit.info
# This potentially sets the following:
# A descriptive name of the devkit
- BASIC_EVAL_DEVKIT_VARIABLE([BUILD_DEVKIT_NAME])
+ BASIC_EVAL_BUILD_DEVKIT_VARIABLE([BUILD_DEVKIT_NAME])
# Corresponds to --with-extra-path
- BASIC_EVAL_DEVKIT_VARIABLE([BUILD_DEVKIT_EXTRA_PATH])
+ BASIC_EVAL_BUILD_DEVKIT_VARIABLE([BUILD_DEVKIT_EXTRA_PATH])
# Corresponds to --with-toolchain-path
- BASIC_EVAL_DEVKIT_VARIABLE([BUILD_DEVKIT_TOOLCHAIN_PATH])
+ BASIC_EVAL_BUILD_DEVKIT_VARIABLE([BUILD_DEVKIT_TOOLCHAIN_PATH])
# Corresponds to --with-sysroot
- BASIC_EVAL_DEVKIT_VARIABLE([BUILD_DEVKIT_SYSROOT])
- # Skip the Window specific parts
+ BASIC_EVAL_BUILD_DEVKIT_VARIABLE([BUILD_DEVKIT_SYSROOT])
+
+ if test "x$TOOLCHAIN_TYPE" = xmicrosoft; then
+ BASIC_EVAL_BUILD_DEVKIT_VARIABLE([BUILD_DEVKIT_VS_INCLUDE])
+ BASIC_EVAL_BUILD_DEVKIT_VARIABLE([BUILD_DEVKIT_VS_LIB])
+ fi
fi
AC_MSG_CHECKING([for build platform devkit])
@@ -935,22 +939,36 @@
AC_MSG_RESULT([$BUILD_DEVKIT_ROOT])
fi
- BUILD_SYSROOT="$BUILD_DEVKIT_SYSROOT"
+ PATH="$BUILD_DEVKIT_EXTRA_PATH:$PATH"
- # Fallback default of just /bin if DEVKIT_PATH is not defined
+ # Fallback default of just /bin if DEVKIT_PATH is not defined
if test "x$BUILD_DEVKIT_TOOLCHAIN_PATH" = x; then
BUILD_DEVKIT_TOOLCHAIN_PATH="$BUILD_DEVKIT_ROOT/bin"
fi
- PATH="$BUILD_DEVKIT_TOOLCHAIN_PATH:$BUILD_DEVKIT_EXTRA_PATH"
+ PATH="$BUILD_DEVKIT_TOOLCHAIN_PATH:$PATH"
+
+ BUILD_SYSROOT="$BUILD_DEVKIT_SYSROOT"
+
+ if test "x$TOOLCHAIN_TYPE" = xmicrosoft; then
+ BUILD_VS_INCLUDE="$BUILD_DEVKIT_VS_INCLUDE"
+ BUILD_VS_LIB="$BUILD_DEVKIT_VS_LIB"
+
+ TOOLCHAIN_SETUP_VISUAL_STUDIO_SYSROOT_FLAGS([BUILD_])
+ fi
fi
fi
# FIXME: we should list the discovered compilers as an exclude pattern!
# If we do that, we can do this detection before POST_DETECTION, and still
# find the build compilers in the tools dir, if needed.
- BASIC_REQUIRE_PROGS(BUILD_CC, [cl cc gcc])
+ if test "x$OPENJDK_BUILD_OS" = xmacosx; then
+ BASIC_REQUIRE_PROGS(BUILD_CC, [clang cl cc gcc])
+ BASIC_REQUIRE_PROGS(BUILD_CXX, [clang++ cl CC g++])
+ else
+ BASIC_REQUIRE_PROGS(BUILD_CC, [cl cc gcc])
+ BASIC_REQUIRE_PROGS(BUILD_CXX, [cl CC g++])
+ fi
BASIC_FIXUP_EXECUTABLE(BUILD_CC)
- BASIC_REQUIRE_PROGS(BUILD_CXX, [cl CC g++])
BASIC_FIXUP_EXECUTABLE(BUILD_CXX)
BASIC_PATH_PROGS(BUILD_NM, nm gcc-nm)
BASIC_FIXUP_EXECUTABLE(BUILD_NM)
@@ -962,9 +980,37 @@
BASIC_FIXUP_EXECUTABLE(BUILD_STRIP)
# Assume the C compiler is the assembler
BUILD_AS="$BUILD_CC -c"
- # Just like for the target compiler, use the compiler as linker
- BUILD_LD="$BUILD_CC"
- BUILD_LDCXX="$BUILD_CXX"
+ if test "x$TOOLCHAIN_TYPE" = xmicrosoft; then
+ # In the Microsoft toolchain we have a separate LD command "link".
+ # Make sure we reject /usr/bin/link (as determined in CYGWIN_LINK), which is
+ # a cygwin program for something completely different.
+ AC_CHECK_PROG([BUILD_LD], [link$EXE_SUFFIX],[link$EXE_SUFFIX],,, [$CYGWIN_LINK])
+ BASIC_FIXUP_EXECUTABLE(BUILD_LD)
+ # Verify that we indeed succeeded with this trick.
+ AC_MSG_CHECKING([if the found link.exe is actually the Visual Studio linker])
+
+ # Reset PATH since it can contain a mix of WSL/linux paths and Windows paths from VS,
+ # which, in combination with WSLENV, will make the WSL layer complain
+ old_path="$PATH"
+ PATH=
+
+ "$BUILD_LD" --version > /dev/null
+
+ if test $? -eq 0 ; then
+ AC_MSG_RESULT([no])
+ AC_MSG_ERROR([This is the Cygwin link tool. Please check your PATH and rerun configure.])
+ else
+ AC_MSG_RESULT([yes])
+ fi
+
+ PATH="$old_path"
+
+ BUILD_LDCXX="$BUILD_LD"
+ else
+ # Just like for the target compiler, use the compiler as linker
+ BUILD_LD="$BUILD_CC"
+ BUILD_LDCXX="$BUILD_CXX"
+ fi
PATH="$OLDPATH"
@@ -1020,6 +1066,10 @@
if test "x$COMPILER_CPU_TEST" != "xx64"; then
AC_MSG_ERROR([Target CPU mismatch. We are building for $OPENJDK_TARGET_CPU but CL is for "$COMPILER_CPU_TEST"; expected "x64".])
fi
+ elif test "x$OPENJDK_TARGET_CPU" = "xaarch64"; then
+ if test "x$COMPILER_CPU_TEST" != "xARM64"; then
+ AC_MSG_ERROR([Target CPU mismatch. We are building for $OPENJDK_TARGET_CPU but CL is for "$COMPILER_CPU_TEST"; expected "arm64".])
+ fi
fi
fi
diff -Nru openjdk-lts-11.0.11+9/make/autoconf/toolchain_windows.m4 openjdk-lts-11.0.14+9/make/autoconf/toolchain_windows.m4
--- openjdk-lts-11.0.11+9/make/autoconf/toolchain_windows.m4 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/make/autoconf/toolchain_windows.m4 2022-01-13 21:56:25.000000000 +0000
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2011, 2012, Oracle and/or its affiliates. All rights reserved.
+# Copyright (c) 2011, 2019, Oracle and/or its affiliates. All rights reserved.
# DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
#
# This code is free software; you can redistribute it and/or modify it
@@ -25,7 +25,7 @@
################################################################################
# The order of these defines the priority by which we try to find them.
-VALID_VS_VERSIONS="2017 2013 2015 2012 2010"
+VALID_VS_VERSIONS="2017 2019 2013 2015 2012 2010"
VS_DESCRIPTION_2010="Microsoft Visual Studio 2010"
VS_VERSION_INTERNAL_2010=100
@@ -87,6 +87,21 @@
VS_VS_PLATFORM_NAME_2017="v141"
VS_SDK_PLATFORM_NAME_2017=
VS_SUPPORTED_2017=true
+VS_TOOLSET_SUPPORTED_2017=true
+
+VS_DESCRIPTION_2019="Microsoft Visual Studio 2019"
+VS_VERSION_INTERNAL_2019=141
+VS_MSVCR_2019=vcruntime140.dll
+VS_MSVCP_2019=msvcp140.dll
+VS_ENVVAR_2019="VS160COMNTOOLS"
+VS_USE_UCRT_2019="true"
+VS_VS_INSTALLDIR_2019="Microsoft Visual Studio/2019"
+VS_EDITIONS_2019="BuildTools Community Professional Enterprise"
+VS_SDK_INSTALLDIR_2019=
+VS_VS_PLATFORM_NAME_2019="v142"
+VS_SDK_PLATFORM_NAME_2019=
+VS_SUPPORTED_2019=false
+VS_TOOLSET_SUPPORTED_2019=false
################################################################################
@@ -98,7 +113,7 @@
METHOD="$3"
BASIC_WINDOWS_REWRITE_AS_UNIX_PATH(VS_BASE)
- # In VS 2017, the default installation is in a subdir named after the edition.
+ # In VS 2017 and VS 2019, the default installation is in a subdir named after the edition.
# Find the first one present and use that.
if test "x$VS_EDITIONS" != x; then
for edition in $VS_EDITIONS; do
@@ -111,11 +126,15 @@
if test -d "$VS_BASE"; then
AC_MSG_NOTICE([Found Visual Studio installation at $VS_BASE using $METHOD])
- if test "x$OPENJDK_TARGET_CPU_BITS" = x32; then
+ if test "x$OPENJDK_TARGET_CPU" = xx86; then
VCVARSFILES="vc/bin/vcvars32.bat vc/auxiliary/build/vcvars32.bat"
- else
+ elif test "x$OPENJDK_TARGET_CPU" = xx86_64; then
VCVARSFILES="vc/bin/amd64/vcvars64.bat vc/bin/x86_amd64/vcvarsx86_amd64.bat \
vc/auxiliary/build/vcvarsx86_amd64.bat vc/auxiliary/build/vcvars64.bat"
+ elif test "x$OPENJDK_TARGET_CPU" = xaarch64; then
+ # for host x86-64, target aarch64
+ VCVARSFILES="vc/auxiliary/build/vcvarsamd64_arm64.bat \
+ vc/auxiliary/build/vcvarsx86_arm64.bat"
fi
for VCVARSFILE in $VCVARSFILES; do
@@ -155,10 +174,12 @@
elif test -f "$WIN_SDK_BASE/Bin/SetEnv.Cmd"; then
AC_MSG_NOTICE([Found Windows SDK installation at $WIN_SDK_BASE using $METHOD])
VS_ENV_CMD="$WIN_SDK_BASE/Bin/SetEnv.Cmd"
- if test "x$OPENJDK_TARGET_CPU_BITS" = x32; then
+ if test "x$OPENJDK_TARGET_CPU" = xx86; then
VS_ENV_ARGS="/x86"
- else
+ elif test "x$OPENJDK_TARGET_CPU" = xx86_64; then
VS_ENV_ARGS="/x64"
+ elif test "x$OPENJDK_TARGET_CPU" = xaarch64; then
+ VS_ENV_ARGS="/arm64"
fi
# PLATFORM_TOOLSET is used during the compilation of the freetype sources (see
# 'LIB_BUILD_FREETYPE' in libraries.m4) and must be 'Windows7.1SDK' for Windows7.1SDK
@@ -177,6 +198,15 @@
# build environment and assigns it to VS_ENV_CMD
AC_DEFUN([TOOLCHAIN_FIND_VISUAL_STUDIO_BAT_FILE],
[
+ # VS2017 provides the option to install previous minor versions of the MSVC
+ # toolsets. It is not possible to directly download earlier minor versions of
+ # VS2017 and in order to build with a previous minor compiler toolset version,
+ # it is now possible to compile with earlier minor versions by passing
+ # -vcvars_ver= argument to vcvarsall.bat.
+ AC_ARG_WITH(msvc-toolset-version, [AS_HELP_STRING([--with-msvc-toolset-version],
+ [specific MSVC toolset version to use, passed as -vcvars_ver argument to
+ pass to vcvarsall.bat (Windows only)])])
+
VS_VERSION="$1"
eval VS_COMNTOOLS_VAR="\${VS_ENVVAR_${VS_VERSION}}"
eval VS_COMNTOOLS="\$${VS_COMNTOOLS_VAR}"
@@ -184,6 +214,7 @@
eval VS_EDITIONS="\${VS_EDITIONS_${VS_VERSION}}"
eval SDK_INSTALL_DIR="\${VS_SDK_INSTALLDIR_${VS_VERSION}}"
eval VS_ENV_ARGS="\${VS_ENV_ARGS_${VS_VERSION}}"
+ eval VS_TOOLSET_SUPPORTED="\${VS_TOOLSET_SUPPORTED_${VS_VERSION}}"
VS_ENV_CMD=""
@@ -241,6 +272,12 @@
TOOLCHAIN_CHECK_POSSIBLE_WIN_SDK_ROOT([${VS_VERSION}],
[C:/Program Files (x86)/$SDK_INSTALL_DIR], [well-known name])
fi
+
+ if test "x$VS_TOOLSET_SUPPORTED" != x; then
+ if test "x$with_msvc_toolset_version" != x; then
+ VS_ENV_ARGS="$VS_ENV_ARGS -vcvars_ver=$with_msvc_toolset_version"
+ fi
+ fi
])
################################################################################
@@ -397,6 +434,8 @@
>> $EXTRACT_VC_ENV_BAT_FILE
$ECHO "$WINPATH_BASH -c 'echo VCINSTALLDIR="'\"$VCINSTALLDIR \" >> set-vs-env.sh' \
>> $EXTRACT_VC_ENV_BAT_FILE
+ $ECHO "$WINPATH_BASH -c 'echo VCToolsRedistDir="'\"$VCToolsRedistDir \" >> set-vs-env.sh' \
+ >> $EXTRACT_VC_ENV_BAT_FILE
$ECHO "$WINPATH_BASH -c 'echo WindowsSdkDir="'\"$WindowsSdkDir \" >> set-vs-env.sh' \
>> $EXTRACT_VC_ENV_BAT_FILE
$ECHO "$WINPATH_BASH -c 'echo WINDOWSSDKDIR="'\"$WINDOWSSDKDIR \" >> set-vs-env.sh' \
@@ -442,6 +481,7 @@
VS_INCLUDE=`$ECHO "$VS_INCLUDE" | $SED -e 's/\\\\*;* *$//'`
VS_LIB=`$ECHO "$VS_LIB" | $SED 's/\\\\*;* *$//'`
VCINSTALLDIR=`$ECHO "$VCINSTALLDIR" | $SED 's/\\\\* *$//'`
+ VCToolsRedistDir=`$ECHO "$VCToolsRedistDir" | $SED 's/\\\\* *$//'`
WindowsSdkDir=`$ECHO "$WindowsSdkDir" | $SED 's/\\\\* *$//'`
WINDOWSSDKDIR=`$ECHO "$WINDOWSSDKDIR" | $SED 's/\\\\* *$//'`
if test -z "$WINDOWSSDKDIR"; then
@@ -455,41 +495,7 @@
AC_SUBST(VS_INCLUDE)
AC_SUBST(VS_LIB)
- # Convert VS_INCLUDE into SYSROOT_CFLAGS
- OLDIFS="$IFS"
- IFS=";"
- for i in $VS_INCLUDE; do
- ipath=$i
- # Only process non-empty elements
- if test "x$ipath" != x; then
- IFS="$OLDIFS"
- # Check that directory exists before calling fixup_path
- testpath=$ipath
- BASIC_WINDOWS_REWRITE_AS_UNIX_PATH([testpath])
- if test -d "$testpath"; then
- BASIC_FIXUP_PATH([ipath])
- SYSROOT_CFLAGS="$SYSROOT_CFLAGS -I$ipath"
- fi
- IFS=";"
- fi
- done
- # Convert VS_LIB into SYSROOT_LDFLAGS
- for i in $VS_LIB; do
- libpath=$i
- # Only process non-empty elements
- if test "x$libpath" != x; then
- IFS="$OLDIFS"
- # Check that directory exists before calling fixup_path
- testpath=$libpath
- BASIC_WINDOWS_REWRITE_AS_UNIX_PATH([testpath])
- if test -d "$testpath"; then
- BASIC_FIXUP_PATH([libpath])
- SYSROOT_LDFLAGS="$SYSROOT_LDFLAGS -libpath:$libpath"
- fi
- IFS=";"
- fi
- done
- IFS="$OLDIFS"
+ TOOLCHAIN_SETUP_VISUAL_STUDIO_SYSROOT_FLAGS
fi
else
AC_MSG_RESULT([not found])
@@ -526,10 +532,15 @@
CORRECT_MSVCR_ARCH="PE32+ executable"
fi
else
- if test "x$OPENJDK_TARGET_CPU_BITS" = x32; then
+ if test "x$OPENJDK_TARGET_CPU" = xx86; then
CORRECT_MSVCR_ARCH=386
- else
+ elif test "x$OPENJDK_TARGET_CPU" = xx86_64; then
CORRECT_MSVCR_ARCH=x86-64
+ elif test "x$OPENJDK_TARGET_CPU" = xaarch64; then
+ # The cygwin 'file' command only returns "PE32+ executable (DLL) (console), for MS Windows",
+ # without specifying which architecture it is for specifically. This has been fixed upstream.
+ # https://github.com/file/file/commit/b849b1af098ddd530094bf779b58431395db2e10#diff-ff2eced09e6860de75057dd731d092aeR142
+ CORRECT_MSVCR_ARCH="PE32+ executable"
fi
fi
if $ECHO "$MSVC_DLL_FILETYPE" | $GREP "$CORRECT_MSVCR_ARCH" 2>&1 > /dev/null; then
@@ -549,24 +560,26 @@
DLL_NAME="$1"
MSVC_DLL=
+ if test "x$OPENJDK_TARGET_CPU" = xx86; then
+ vs_target_cpu=x86
+ elif test "x$OPENJDK_TARGET_CPU" = xx86_64; then
+ vs_target_cpu=x64
+ elif test "x$OPENJDK_TARGET_CPU" = xaarch64; then
+ vs_target_cpu=arm64
+ fi
+
if test "x$MSVC_DLL" = x; then
if test "x$VCINSTALLDIR" != x; then
CYGWIN_VC_INSTALL_DIR="$VCINSTALLDIR"
BASIC_FIXUP_PATH(CYGWIN_VC_INSTALL_DIR)
if test "$VS_VERSION" -lt 2017; then
# Probe: Using well-known location from Visual Studio 12.0 and older
- if test "x$OPENJDK_TARGET_CPU_BITS" = x64; then
- POSSIBLE_MSVC_DLL="$CYGWIN_VC_INSTALL_DIR/redist/x64/Microsoft.VC${VS_VERSION_INTERNAL}.CRT/$DLL_NAME"
- else
- POSSIBLE_MSVC_DLL="$CYGWIN_VC_INSTALL_DIR/redist/x86/Microsoft.VC${VS_VERSION_INTERNAL}.CRT/$DLL_NAME"
- fi
+ POSSIBLE_MSVC_DLL="$CYGWIN_VC_INSTALL_DIR/redist/$vs_target_cpu/Microsoft.VC${VS_VERSION_INTERNAL}.CRT/$DLL_NAME"
else
- # Probe: Using well-known location from VS 2017
- if test "x$OPENJDK_TARGET_CPU_BITS" = x64; then
- POSSIBLE_MSVC_DLL="`ls $CYGWIN_VC_INSTALL_DIR/Redist/MSVC/*/x64/Microsoft.VC${VS_VERSION_INTERNAL}.CRT/$DLL_NAME`"
- else
- POSSIBLE_MSVC_DLL="`ls $CYGWIN_VC_INSTALL_DIR/Redist/MSVC/*/x86/Microsoft.VC${VS_VERSION_INTERNAL}.CRT/$DLL_NAME`"
- fi
+ CYGWIN_VC_TOOLS_REDIST_DIR="$VCToolsRedistDir"
+ BASIC_FIXUP_PATH(CYGWIN_VC_TOOLS_REDIST_DIR)
+ # Probe: Using well-known location from VS 2017 and VS 2019
+ POSSIBLE_MSVC_DLL="`ls $CYGWIN_VC_TOOLS_REDIST_DIR/$vs_target_cpu/Microsoft.VC${VS_VERSION_INTERNAL}.CRT/$DLL_NAME`"
fi
# In case any of the above finds more than one file, loop over them.
for possible_msvc_dll in $POSSIBLE_MSVC_DLL; do
@@ -598,13 +611,8 @@
if test "x$VS100COMNTOOLS" != x; then
CYGWIN_VS_TOOLS_DIR="$VS100COMNTOOLS/.."
BASIC_WINDOWS_REWRITE_AS_UNIX_PATH(CYGWIN_VS_TOOLS_DIR)
- if test "x$OPENJDK_TARGET_CPU_BITS" = x64; then
- POSSIBLE_MSVC_DLL=`$FIND "$CYGWIN_VS_TOOLS_DIR" -name $DLL_NAME \
- | $GREP -i /x64/ | $HEAD --lines 1`
- else
- POSSIBLE_MSVC_DLL=`$FIND "$CYGWIN_VS_TOOLS_DIR" -name $DLL_NAME \
- | $GREP -i /x86/ | $HEAD --lines 1`
- fi
+ POSSIBLE_MSVC_DLL=`$FIND "$CYGWIN_VS_TOOLS_DIR" -name $DLL_NAME \
+ | $GREP -i /$vs_target_cpu/ | $HEAD --lines 1`
TOOLCHAIN_CHECK_POSSIBLE_MSVC_DLL([$DLL_NAME], [$POSSIBLE_MSVC_DLL],
[search of VS100COMNTOOLS])
fi
@@ -614,17 +622,17 @@
# Probe: Search wildly in the VCINSTALLDIR. We've probably lost by now.
# (This was the original behaviour; kept since it might turn something up)
if test "x$CYGWIN_VC_INSTALL_DIR" != x; then
- if test "x$OPENJDK_TARGET_CPU_BITS" = x64; then
- POSSIBLE_MSVC_DLL=`$FIND "$CYGWIN_VC_INSTALL_DIR" -name $DLL_NAME \
- | $GREP x64 | $HEAD --lines 1`
- else
+ if test "x$OPENJDK_TARGET_CPU" = xx86; then
POSSIBLE_MSVC_DLL=`$FIND "$CYGWIN_VC_INSTALL_DIR" -name $DLL_NAME \
- | $GREP x86 | $GREP -v ia64 | $GREP -v x64 | $HEAD --lines 1`
+ | $GREP x86 | $GREP -v ia64 | $GREP -v x64 | $GREP -v arm64 | $HEAD --lines 1`
if test "x$POSSIBLE_MSVC_DLL" = x; then
# We're grasping at straws now...
POSSIBLE_MSVC_DLL=`$FIND "$CYGWIN_VC_INSTALL_DIR" -name $DLL_NAME \
| $HEAD --lines 1`
fi
+ else
+ POSSIBLE_MSVC_DLL=`$FIND "$CYGWIN_VC_INSTALL_DIR" -name $DLL_NAME \
+ | $GREP $vs_target_cpu | $HEAD --lines 1`
fi
TOOLCHAIN_CHECK_POSSIBLE_MSVC_DLL([$DLL_NAME], [$POSSIBLE_MSVC_DLL],
@@ -708,8 +716,12 @@
CYGWIN_WINDOWSSDKDIR="${WINDOWSSDKDIR}"
BASIC_FIXUP_PATH([CYGWIN_WINDOWSSDKDIR])
dll_subdir=$OPENJDK_TARGET_CPU
- if test "x$dll_subdir" = "xx86_64"; then
+ if test "x$OPENJDK_TARGET_CPU" = "xaarch64"; then
+ dll_subdir="arm64"
+ elif test "x$OPENJDK_TARGET_CPU" = "xx86_64"; then
dll_subdir="x64"
+ elif test "x$OPENJDK_TARGET_CPU" = "xx86"; then
+ dll_subdir="x86"
fi
UCRT_DLL_DIR="$CYGWIN_WINDOWSSDKDIR/Redist/ucrt/DLLs/$dll_subdir"
if test -z "$(ls -d "$UCRT_DLL_DIR/"*.dll 2> /dev/null)"; then
@@ -732,3 +744,49 @@
fi
AC_SUBST(UCRT_DLL_DIR)
])
+
+# Setup the sysroot flags and add them to global CFLAGS and LDFLAGS so
+# that configure can use them while detecting compilers.
+# TOOLCHAIN_TYPE is available here.
+# Param 1 - Optional prefix to all variables. (e.g BUILD_)
+AC_DEFUN([TOOLCHAIN_SETUP_VISUAL_STUDIO_SYSROOT_FLAGS],
+[
+ # Convert $1VS_INCLUDE into $1SYSROOT_CFLAGS
+ OLDIFS="$IFS"
+ IFS=";"
+ for i in [$]$1VS_INCLUDE; do
+ ipath=$i
+ # Only process non-empty elements
+ if test "x$ipath" != x; then
+ IFS="$OLDIFS"
+ # Check that directory exists before calling fixup_path
+ testpath=$ipath
+ BASIC_WINDOWS_REWRITE_AS_UNIX_PATH([testpath])
+ if test -d "$testpath"; then
+ BASIC_FIXUP_PATH([ipath])
+ $1SYSROOT_CFLAGS="[$]$1SYSROOT_CFLAGS -I$ipath"
+ fi
+ IFS=";"
+ fi
+ done
+ # Convert $1VS_LIB into $1SYSROOT_LDFLAGS
+ for i in [$]$1VS_LIB; do
+ libpath=$i
+ # Only process non-empty elements
+ if test "x$libpath" != x; then
+ IFS="$OLDIFS"
+ # Check that directory exists before calling fixup_path
+ testpath=$libpath
+ BASIC_WINDOWS_REWRITE_AS_UNIX_PATH([testpath])
+ if test -d "$testpath"; then
+ BASIC_FIXUP_PATH([libpath])
+ $1SYSROOT_LDFLAGS="[$]$1SYSROOT_LDFLAGS -libpath:$libpath"
+ fi
+ IFS=";"
+ fi
+ done
+ IFS="$OLDIFS"
+
+ AC_SUBST($1SYSROOT_CFLAGS)
+ AC_SUBST($1SYSROOT_LDFLAGS)
+])
diff -Nru openjdk-lts-11.0.11+9/make/autoconf/version-numbers openjdk-lts-11.0.14+9/make/autoconf/version-numbers
--- openjdk-lts-11.0.11+9/make/autoconf/version-numbers 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/make/autoconf/version-numbers 2022-01-13 21:56:25.000000000 +0000
@@ -28,16 +28,16 @@
DEFAULT_VERSION_FEATURE=11
DEFAULT_VERSION_INTERIM=0
-DEFAULT_VERSION_UPDATE=11
+DEFAULT_VERSION_UPDATE=14
DEFAULT_VERSION_PATCH=0
DEFAULT_VERSION_EXTRA1=0
DEFAULT_VERSION_EXTRA2=0
DEFAULT_VERSION_EXTRA3=0
-DEFAULT_VERSION_DATE=2021-04-20
+DEFAULT_VERSION_DATE=2022-01-18
DEFAULT_VERSION_CLASSFILE_MAJOR=55 # "`$EXPR $DEFAULT_VERSION_FEATURE + 44`"
DEFAULT_VERSION_CLASSFILE_MINOR=0
DEFAULT_ACCEPTABLE_BOOT_VERSIONS="10 11"
-DEFAULT_PROMOTED_VERSION_PRE=ea
+DEFAULT_PROMOTED_VERSION_PRE=
LAUNCHER_NAME=openjdk
PRODUCT_NAME=OpenJDK
diff -Nru openjdk-lts-11.0.11+9/make/common/NativeCompilation.gmk openjdk-lts-11.0.14+9/make/common/NativeCompilation.gmk
--- openjdk-lts-11.0.11+9/make/common/NativeCompilation.gmk 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/make/common/NativeCompilation.gmk 2022-01-13 21:56:25.000000000 +0000
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2011, 2020, Oracle and/or its affiliates. All rights reserved.
+# Copyright (c) 2011, 2021, Oracle and/or its affiliates. All rights reserved.
# DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
#
# This code is free software; you can redistribute it and/or modify it
@@ -1008,6 +1008,13 @@
$(CD) $$($1_OUTPUT_DIR) && \
$$($1_OBJCOPY) --add-gnu-debuglink=$$($1_DEBUGINFO_FILES) $$($1_TARGET)
+ else ifeq ($(OPENJDK_TARGET_OS), aix)
+ # AIX does not provide the equivalent of OBJCOPY to extract debug symbols,
+ # so we copy the compiled object with symbols to the .debuginfo file, which
+ # happens prior to the STRIP_CMD on the original target object file.
+ $1_DEBUGINFO_FILES := $$($1_OUTPUT_DIR)/$$($1_NOSUFFIX).debuginfo
+ $1_CREATE_DEBUGINFO_CMDS := $(CP) $$($1_TARGET) $$($1_DEBUGINFO_FILES)
+
else ifeq ($(OPENJDK_TARGET_OS), macosx)
$1_DEBUGINFO_FILES := \
$$($1_OUTPUT_DIR)/$$($1_BASENAME).dSYM/Contents/Info.plist \
diff -Nru openjdk-lts-11.0.11+9/make/common/TestFilesCompilation.gmk openjdk-lts-11.0.14+9/make/common/TestFilesCompilation.gmk
--- openjdk-lts-11.0.11+9/make/common/TestFilesCompilation.gmk 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/make/common/TestFilesCompilation.gmk 2022-01-13 21:56:25.000000000 +0000
@@ -60,14 +60,16 @@
ifeq ($$($1_TYPE), LIBRARY)
$1_PREFIX = lib
$1_OUTPUT_SUBDIR := lib
- $1_CFLAGS := $(CFLAGS_TESTLIB)
- $1_LDFLAGS := $(LDFLAGS_TESTLIB) $(call SET_SHARED_LIBRARY_ORIGIN)
+ $1_BASE_CFLAGS := $(CFLAGS_JDKLIB)
+ $1_BASE_CXXFLAGS := $(CXXFLAGS_JDKLIB)
+ $1_LDFLAGS := $(LDFLAGS_JDKLIB) $(call SET_SHARED_LIBRARY_ORIGIN)
$1_COMPILATION_TYPE := LIBRARY
else ifeq ($$($1_TYPE), PROGRAM)
$1_PREFIX = exe
$1_OUTPUT_SUBDIR := bin
- $1_CFLAGS := $(CFLAGS_TESTEXE)
- $1_LDFLAGS := $(LDFLAGS_TESTEXE)
+ $1_BASE_CFLAGS := $(CFLAGS_JDKEXE)
+ $1_BASE_CXXFLAGS := $(CXXFLAGS_JDKEXE)
+ $1_LDFLAGS := $(LDFLAGS_JDKEXE) $(LDFLAGS_TESTEXE)
$1_COMPILATION_TYPE := EXECUTABLE
else
$$(error Unknown type: $$($1_TYPE))
@@ -75,7 +77,7 @@
# Locate all files with the matching prefix
$1_FILE_LIST := \
- $$(call FindFiles, $$($1_SOURCE_DIRS), $$($1_PREFIX)*.c)
+ $$(call FindFiles, $$($1_SOURCE_DIRS), $$($1_PREFIX)*.c $$($1_PREFIX)*.cpp $$($1_PREFIX)*.m)
$1_EXCLUDE_PATTERN := $$(addprefix %/, $$($1_EXCLUDE))
$1_FILTERED_FILE_LIST := $$(filter-out $$($1_EXCLUDE_PATTERN), $$($1_FILE_LIST))
@@ -91,9 +93,13 @@
INCLUDE_FILES := $$(notdir $$(file)), \
OBJECT_DIR := $$($1_OUTPUT_DIR)/support/$$(name), \
OUTPUT_DIR := $$($1_OUTPUT_DIR)/$$($1_OUTPUT_SUBDIR), \
- CFLAGS := $$($1_CFLAGS) $$($1_CFLAGS_$$(name)), \
+ CFLAGS := $$($1_BASE_CFLAGS) $$($1_CFLAGS) $$($1_CFLAGS_$$(name)), \
+ CXXFLAGS := $$($1_BASE_CXXFLAGS) $$($1_CFLAGS) $$($1_CFLAGS_$$(name)), \
LDFLAGS := $$($1_LDFLAGS) $$($1_LDFLAGS_$$(name)), \
+ DISABLED_WARNINGS_CXX_solstudio := wvarhidenmem, \
+ DISABLED_WARNINGS_CXX_gcc := format, \
LIBS := $$($1_LIBS_$$(name)), \
+ TOOLCHAIN := $(if $$(filter %.cpp, $$(file)), TOOLCHAIN_LINK_CXX, TOOLCHAIN_DEFAULT), \
OPTIMIZATION := $$(if $$($1_OPTIMIZATION_$$(name)),$$($1_OPTIMIZATION_$$(name)),LOW), \
COPY_DEBUG_SYMBOLS := false, \
STRIP_SYMBOLS := false, \
diff -Nru openjdk-lts-11.0.11+9/make/conf/jib-profiles.js openjdk-lts-11.0.14+9/make/conf/jib-profiles.js
--- openjdk-lts-11.0.11+9/make/conf/jib-profiles.js 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/make/conf/jib-profiles.js 2022-01-13 21:56:25.000000000 +0000
@@ -242,7 +242,7 @@
dependencies: ["boot_jdk", "gnumake", "jtreg", "jib", "autoconf"],
default_make_targets: ["product-bundles", "test-bundles", "static-libs-bundles"],
configure_args: concat(["--enable-jtreg-failure-handler"],
- "--with-exclude-translations=de,es,fr,it,ko,pt_BR,sv,ca,tr,cs,sk,ja_JP_A,ja_JP_HA,ja_JP_HI,ja_JP_I,zh_TW,zh_HK",
+ "--with-exclude-translations=es,fr,it,ko,pt_BR,sv,ca,tr,cs,sk,ja_JP_A,ja_JP_HA,ja_JP_HI,ja_JP_I,zh_TW,zh_HK",
"--disable-manpages",
versionArgs(input, common))
};
@@ -854,7 +854,7 @@
var devkit_platform_revisions = {
linux_x64: "gcc7.3.0-OEL6.4+1.1",
- macosx_x64: "Xcode9.4-MacOSX10.13+1.0",
+ macosx_x64: "Xcode11.3.1-MacOSX10.15+1.0",
solaris_x64: "SS12u4-Solaris11u1+1.0",
solaris_sparcv9: "SS12u4-Solaris11u1+1.1",
windows_x64: "VS2017-15.9.16+1.0",
@@ -918,11 +918,12 @@
},
jtreg: {
- server: "javare",
- revision: "4.2",
- build_number: "b13",
+ server: "jpg",
+ product: "jtreg",
+ version: "5.1",
+ build_number: "b01",
checksum_file: "MD5_VALUES",
- file: "jtreg_bin-4.2.zip",
+ file: "bundles/jtreg_bin-5.1.zip",
environment_name: "JT_HOME",
environment_path: input.get("jtreg", "install_path") + "/jtreg/bin"
},
@@ -1160,15 +1161,15 @@
* @param patch Override patch version
* @returns {String} The numeric version string
*/
-var getVersion = function (feature, interim, update, patch) {
+var getVersion = function (feature, interim, update, patch, extra1, extra2, extra3) {
var version_numbers = getVersionNumbers();
var version = (feature != null ? feature : version_numbers.get("DEFAULT_VERSION_FEATURE"))
+ "." + (interim != null ? interim : version_numbers.get("DEFAULT_VERSION_INTERIM"))
+ "." + (update != null ? update : version_numbers.get("DEFAULT_VERSION_UPDATE"))
+ "." + (patch != null ? patch : version_numbers.get("DEFAULT_VERSION_PATCH"))
- + "." + version_numbers.get("DEFAULT_VERSION_EXTRA1")
- + "." + version_numbers.get("DEFAULT_VERSION_EXTRA2")
- + "." + version_numbers.get("DEFAULT_VERSION_EXTRA3");
+ + "." + (extra1 != null ? extra1 : version_numbers.get("DEFAULT_VERSION_EXTRA1"))
+ + "." + (extra2 != null ? extra2 : version_numbers.get("DEFAULT_VERSION_EXTRA2"))
+ + "." + (extra3 != null ? extra3 : version_numbers.get("DEFAULT_VERSION_EXTRA3"));
while (version.match(".*\\.0$")) {
version = version.substring(0, version.length - 2);
}
diff -Nru openjdk-lts-11.0.11+9/make/conf/test-dependencies openjdk-lts-11.0.14+9/make/conf/test-dependencies
--- openjdk-lts-11.0.11+9/make/conf/test-dependencies 1970-01-01 00:00:00.000000000 +0000
+++ openjdk-lts-11.0.14+9/make/conf/test-dependencies 2022-01-13 21:56:25.000000000 +0000
@@ -0,0 +1,43 @@
+#
+# Copyright (c) 2020, 2021, Oracle and/or its affiliates. All rights reserved.
+# DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+#
+# This code is free software; you can redistribute it and/or modify it
+# under the terms of the GNU General Public License version 2 only, as
+# published by the Free Software Foundation. Oracle designates this
+# particular file as subject to the "Classpath" exception as provided
+# by Oracle in the LICENSE file that accompanied this code.
+#
+# This code is distributed in the hope that it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+# version 2 for more details (a copy is included in the LICENSE file that
+# accompanied this code).
+#
+# You should have received a copy of the GNU General Public License version
+# 2 along with this work; if not, write to the Free Software Foundation,
+# Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
+#
+# Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
+# or visit www.oracle.com if you need additional information or have any
+# questions.
+#
+
+# Versions and download locations for dependencies used by pre-submit testing.
+
+BOOT_JDK_VERSION=11
+JTREG_VERSION=5.1
+JTREG_BUILD=b01
+GTEST_VERSION=1.8.1
+
+LINUX_X64_BOOT_JDK_FILENAME=openjdk-11_linux-x64_bin.tar.gz
+LINUX_X64_BOOT_JDK_URL=https://github.com/adoptium/temurin11-binaries/releases/download/jdk-11.0.12%2B7/OpenJDK11U-jdk_x64_linux_hotspot_11.0.12_7.tar.gz
+LINUX_X64_BOOT_JDK_SHA256=8770f600fc3b89bf331213c7aa21f8eedd9ca5d96036d1cd48cb2748a3dbefd2
+
+WINDOWS_X64_BOOT_JDK_FILENAME=openjdk-11_windows-x64_bin.zip
+WINDOWS_X64_BOOT_JDK_URL=https://github.com/adoptium/temurin11-binaries/releases/download/jdk-11.0.12%2B7/OpenJDK11U-jdk_x64_windows_hotspot_11.0.12_7.zip
+WINDOWS_X64_BOOT_JDK_SHA256=c54123dd4b0d6473221539e7003b8ca1c1757c5588c46465565b03bf8781f807
+
+MACOS_X64_BOOT_JDK_FILENAME=openjdk-11_osx-x64_bin.tar.gz
+MACOS_X64_BOOT_JDK_URL=https://github.com/adoptium/temurin11-binaries/releases/download/jdk-11.0.12%2B7/OpenJDK11U-jdk_x64_mac_hotspot_11.0.12_7.tar.gz
+MACOS_X64_BOOT_JDK_SHA256=13d056ee9a57bf2d5b3af4504c8f8cf7a246c4dff78f96b70dd05dad98075855
diff -Nru openjdk-lts-11.0.11+9/make/data/blacklistedcertsconverter/blacklisted.certs.pem openjdk-lts-11.0.14+9/make/data/blacklistedcertsconverter/blacklisted.certs.pem
--- openjdk-lts-11.0.11+9/make/data/blacklistedcertsconverter/blacklisted.certs.pem 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/make/data/blacklistedcertsconverter/blacklisted.certs.pem 1970-01-01 00:00:00.000000000 +0000
@@ -1,749 +0,0 @@
-#! java BlacklistedCertsConverter SHA-256
-
-# The line above must be the first line of this file. Do not
-# remove it.
-
-// Subject: CN=Digisign Server ID (Enrich),
-// OU=457608-K,
-// O=Digicert Sdn. Bhd.,
-// C=MY
-// Issuer: CN=GTE CyberTrust Global Root,
-// OU=GTE CyberTrust Solutions, Inc.,
-// O=GTE Corporation,
-// C=US
-// Serial: 120001705 (07:27:14:a9)
------BEGIN CERTIFICATE-----
-MIIDyzCCAzSgAwIBAgIEBycUqTANBgkqhkiG9w0BAQUFADB1MQswCQYDVQQGEwJV
-UzEYMBYGA1UEChMPR1RFIENvcnBvcmF0aW9uMScwJQYDVQQLEx5HVEUgQ3liZXJU
-cnVzdCBTb2x1dGlvbnMsIEluYy4xIzAhBgNVBAMTGkdURSBDeWJlclRydXN0IEds
-b2JhbCBSb290MB4XDTA3MDcxNzE1MTc0OFoXDTEyMDcxNzE1MTY1NFowYzELMAkG
-A1UEBhMCTVkxGzAZBgNVBAoTEkRpZ2ljZXJ0IFNkbi4gQmhkLjERMA8GA1UECxMI
-NDU3NjA4LUsxJDAiBgNVBAMTG0RpZ2lzaWduIFNlcnZlciBJRCAoRW5yaWNoKTCB
-nzANBgkqhkiG9w0BAQEFAAOBjQAwgYkCgYEArahkS02Hx4RZufuQRqCmicDx/tXa
-VII3DZkrRSYK6Fawf8qo9I5HhAGCKeOzarWR8/uVhbxyqGToCkCcxfRxrnt7agfq
-kBRPjYmvlKuyBtQCanuYH1m5Os1U+iDfsioK6bjdaZDAKdNO0JftZszFGUkGf/pe
-LHx7hRsyQt97lSUCAwEAAaOCAXgwggF0MBIGA1UdEwEB/wQIMAYBAf8CAQAwXAYD
-VR0gBFUwUzBIBgkrBgEEAbE+AQAwOzA5BggrBgEFBQcCARYtaHR0cDovL2N5YmVy
-dHJ1c3Qub21uaXJvb3QuY29tL3JlcG9zaXRvcnkuY2ZtMAcGBWCDSgEBMA4GA1Ud
-DwEB/wQEAwIB5jCBiQYDVR0jBIGBMH+heaR3MHUxCzAJBgNVBAYTAlVTMRgwFgYD
-VQQKEw9HVEUgQ29ycG9yYXRpb24xJzAlBgNVBAsTHkdURSBDeWJlclRydXN0IFNv
-bHV0aW9ucywgSW5jLjEjMCEGA1UEAxMaR1RFIEN5YmVyVHJ1c3QgR2xvYmFsIFJv
-b3SCAgGlMEUGA1UdHwQ+MDwwOqA4oDaGNGh0dHA6Ly93d3cucHVibGljLXRydXN0
-LmNvbS9jZ2ktYmluL0NSTC8yMDE4L2NkcC5jcmwwHQYDVR0OBBYEFMYWk04WF+wW
-royUdvOGbcV0boR3MA0GCSqGSIb3DQEBBQUAA4GBAHYAe6Z4K2Ydjl42xqSOBfIj
-knyTZ9P0wAp9iy3Z6tVvGvPhSilaIoRNUC9LDPL/hcJ7VdREgr5trGeOvLQfkpxR
-gBoU9m6rYYgLrRx/90tQUdZlG6ZHcRVesHHzNRTyN71jyNXwk1o0X9g96F33xR7A
-5c8fhiSpPAdmzcHSNmNZ
------END CERTIFICATE-----
-
-// Subject: CN=Digisign Server ID - (Enrich),
-// OU=457608-K,
-// O=Digicert Sdn. Bhd.,
-// C=MY
-// Issuer: CN=Entrust.net Certification Authority (2048)
-// OU=(c) 1999 Entrust.net Limited,
-// OU=www.entrust.net/CPS_2048 incorp. by ref. (limits liab.),
-// O=Entrust.net
-// Serial: 1184644297 (4c:0e:63:6a)
------BEGIN CERTIFICATE-----
-MIIEzjCCA7agAwIBAgIETA5jajANBgkqhkiG9w0BAQUFADCBtDEUMBIGA1UEChML
-RW50cnVzdC5uZXQxQDA+BgNVBAsUN3d3dy5lbnRydXN0Lm5ldC9DUFNfMjA0OCBp
-bmNvcnAuIGJ5IHJlZi4gKGxpbWl0cyBsaWFiLikxJTAjBgNVBAsTHChjKSAxOTk5
-IEVudHJ1c3QubmV0IExpbWl0ZWQxMzAxBgNVBAMTKkVudHJ1c3QubmV0IENlcnRp
-ZmljYXRpb24gQXV0aG9yaXR5ICgyMDQ4KTAeFw0xMDA3MTYxNzIzMzdaFw0xNTA3
-MTYxNzUzMzdaMGUxCzAJBgNVBAYTAk1ZMRswGQYDVQQKExJEaWdpY2VydCBTZG4u
-IEJoZC4xETAPBgNVBAsTCDQ1NzYwOC1LMSYwJAYDVQQDEx1EaWdpc2lnbiBTZXJ2
-ZXIgSUQgLSAoRW5yaWNoKTCCASIwDQYJKoZIhvcNAQEBBQADggEPADCCAQoCggEB
-AMWJ5PQNBkCSWccaszXRDkwqM/n4r8qef+65p21g9FTob9Wb8xtjMQRoctE0Foy0
-FyyX3nPF2JAVoBor9cuzSIZE8B2ITM5BQhrv9Qze/kDaOSD3BlU6ap1GwdJvpbLI
-Vz4po5zg6YV3ZuiYpyR+vsBZIOVEb7ZX2L7OwmV3WMZhQdF0BMh/SULFcqlyFu6M
-3RJdtErU0a9Qt9iqdXZorT5dqjBtYairEFs+E78z4K9EnTgiW+9ML6ZxJhUmyiiM
-2fqOjqmiFDXimySItPR/hZ2DTwehthSQNsQ0HI0mYW0Tb3i+6I8nx0uElqOGaAwj
-vgvsjJQAqQSKE5D334VsDLECAwEAAaOCATQwggEwMA4GA1UdDwEB/wQEAwIBBjAS
-BgNVHRMBAf8ECDAGAQH/AgEAMCcGA1UdJQQgMB4GCCsGAQUFBwMBBggrBgEFBQcD
-AgYIKwYBBQUHAwQwMwYIKwYBBQUHAQEEJzAlMCMGCCsGAQUFBzABhhdodHRwOi8v
-b2NzcC5lbnRydXN0Lm5ldDBEBgNVHSAEPTA7MDkGBWCDSgEBMDAwLgYIKwYBBQUH
-AgEWImh0dHA6Ly93d3cuZGlnaWNlcnQuY29tLm15L2Nwcy5odG0wMgYDVR0fBCsw
-KTAnoCWgI4YhaHR0cDovL2NybC5lbnRydXN0Lm5ldC8yMDQ4Y2EuY3JsMBEGA1Ud
-DgQKBAhMTswlKAMpgTAfBgNVHSMEGDAWgBRV5IHREYC+2Im5CKMx+aEkCRa5cDAN
-BgkqhkiG9w0BAQUFAAOCAQEAl0zvSjpJrHL8MCBrtClbp8WVBJD5MtXChWreA6E3
-+YkAsFqsVX7bQzX/yQH4Ub7MJsrIaqTEVD4mHucMo82XZ5TdpkLrXM2POXlrM3kh
-Bnn6gkQVmczBtznTRmJ8snDrb84gqj4Zt+l0gpy0pUtNYQA35IfS8hQ6ZHy4qXth
-4JMi59WfPkfmNnagU9gAAzoPtTP+lsrT0oI6Lt3XSOHkp2nMHOmZSufKcEXXCwcO
-mnUb0C+Sb/akB8O9HEumhLZ9qJqp0qcp8QtXaR6XVybsK0Os1EWDBQDp4/BGQAf6
-6rFRc5Mcpd1TETfIKqcVJx20qsx/qjEw/LhFn0gJ7RDixQ==
------END CERTIFICATE-----
-
-// Subject: CN=Java Media APIs,
-// OU=Java Signed Extensions,
-// OU=Corporate Object Signing,
-// O=Sun Microsystems Inc
-// Issuer: CN=Object Signing CA,
-// OU=Class 2 OnSite Subscriber CA,
-// OU=VeriSign Trust Network,
-// O=Sun Microsystems Inc
-// Serial: 6a:8b:99:91:37:59:4f:89:53:e2:97:18:9f:19:1e:4e
------BEGIN CERTIFICATE-----
-MIIFdzCCBF+gAwIBAgIQaouZkTdZT4lT4pcYnxkeTjANBgkqhkiG9w0BAQUFADCB
-gzEdMBsGA1UEChMUU3VuIE1pY3Jvc3lzdGVtcyBJbmMxHzAdBgNVBAsTFlZlcmlT
-aWduIFRydXN0IE5ldHdvcmsxJTAjBgNVBAsTHENsYXNzIDIgT25TaXRlIFN1YnNj
-cmliZXIgQ0ExGjAYBgNVBAMTEU9iamVjdCBTaWduaW5nIENBMB4XDTA5MDUxMjAw
-MDAwMFoXDTEyMDUxMTIzNTk1OVowfTEdMBsGA1UEChQUU3VuIE1pY3Jvc3lzdGVt
-cyBJbmMxITAfBgNVBAsUGENvcnBvcmF0ZSBPYmplY3QgU2lnbmluZzEfMB0GA1UE
-CxQWSmF2YSBTaWduZWQgRXh0ZW5zaW9uczEYMBYGA1UEAxQPSmF2YSBNZWRpYSBB
-UElzMIIBIjANBgkqhkiG9w0BAQEFAAOCAQ8AMIIBCgKCAQEAl5blzoKTVE8y4Hpz
-q6E15RZz1bF5HnYEyYqgHkZXnAKedmYCoMzm1XK8s+gQWShLEvGEAvs5yqarx9gE
-nnC21N28aEZgIJMa2/arKxCUkS4pxdGPYGexL9UzSRkUpoBShCZKEGdmX7gfJE2K
-/sd9MFvGV5/yZtWXrADzvm0Kd/9mg1KRv1gfrZIq0TJbupoXPYYqb73AkI9eT2ZD
-q9MdwD4E5+oojsDFXt8GU/D00fUhtXpYwuplU7D667WHYdJhIah0ST6JywyqcLXG
-XSuFTXOgITT2idSHluZVmx3dqJ72u9kPkO4JdJTMDfaK8zgNLaRkiU8Qcj+qhLYH
-ytaqcwIDAQABo4IB6jCCAeYwCQYDVR0TBAIwADAOBgNVHQ8BAf8EBAMCB4AwfwYD
-VR0fBHgwdjB0oHKgcIZuaHR0cDovL29uc2l0ZWNybC52ZXJpc2lnbi5jb20vU3Vu
-TWljcm9zeXN0ZW1zSW5jQ29ycG9yYXRlT2JqZWN0U2lnbmluZ0phdmFTaWduZWRF
-eHRlbnNpb25zQ2xhc3NCL0xhdGVzdENSTC5jcmwwHwYDVR0jBBgwFoAUs0crgn5T
-tHPKuLsZt76BTQeVx+0wHQYDVR0OBBYEFKS32mVx0gNWTeS4ProHEaeSpvvIMDsG
-CCsGAQUFBwEBBC8wLTArBggrBgEFBQcwAYYfaHR0cDovL29uc2l0ZS1vY3NwLnZl
-cmlzaWduLmNvbTCBtQYDVR0gBIGtMIGqMDkGC2CGSAGG+EUBBxcCMCowKAYIKwYB
-BQUHAgEWHGh0dHBzOi8vd3d3LnZlcmlzaWduLmNvbS9ycGEwbQYLYIZIAYb3AIN9
-nD8wXjAnBggrBgEFBQcCARYbaHR0cHM6Ly93d3cuc3VuLmNvbS9wa2kvY3BzMDMG
-CCsGAQUFBwICMCcaJVZhbGlkYXRlZCBGb3IgU3VuIEJ1c2luZXNzIE9wZXJhdGlv
-bnMwEwYDVR0lBAwwCgYIKwYBBQUHAwMwDQYJKoZIhvcNAQEFBQADggEBAAe6BO4W
-3TSNWfezyelJs6kE3HfulT6Bdyz4UUoh9ykXcV8nRwT+kh25I5MdyG2GfkJoADPR
-VhC5DYo13UFpIsTNVjq+hGYe2hML93bN7ad9SxCCyjHUo3yMz2qgBbHZI3VA9ZHA
-aWM4Tx0saMwbcnVvlbuGh+PXvStfypJqYT6lzcdFfjNVX4FI/QQNGhBswMY51tC8
-GTBCL2qhJon0gSCU4zaawDOf7+XxJWirLamYL1Aal1/h2z2sFrvA/1ftxtU3kZ6I
-7De8DyoHeZg7pYGdrj7g+lPhCga/WvEhN152I+aP08YbFcJHYmK05ngl/Ye4c6Bd
-cdrdfbw6QzEUIYY=
------END CERTIFICATE-----
-
-// Subject: CN=JavaFX 1.0 Runtime,
-// OU=Java Signed Extensions,
-// OU=Corporate Object Signing,
-// O=Sun Microsystems Inc
-// Issuer: CN=Object Signing CA,
-// OU=Class 2 OnSite Subscriber CA,
-// OU=VeriSign Trust Network,
-// O=Sun Microsystems Inc
-// Serial: 55:c0:e6:44:59:59:79:9e:d9:26:f1:b0:4a:1e:f0:27
------BEGIN CERTIFICATE-----
-MIIFezCCBGOgAwIBAgIQVcDmRFlZeZ7ZJvGwSh7wJzANBgkqhkiG9w0BAQUFADCB
-gzEdMBsGA1UEChMUU3VuIE1pY3Jvc3lzdGVtcyBJbmMxHzAdBgNVBAsTFlZlcmlT
-aWduIFRydXN0IE5ldHdvcmsxJTAjBgNVBAsTHENsYXNzIDIgT25TaXRlIFN1YnNj
-cmliZXIgQ0ExGjAYBgNVBAMTEU9iamVjdCBTaWduaW5nIENBMB4XDTA4MTAwOTAw
-MDAwMFoXDTExMTAwOTIzNTk1OVowgYAxHTAbBgNVBAoUFFN1biBNaWNyb3N5c3Rl
-bXMgSW5jMSEwHwYDVQQLFBhDb3Jwb3JhdGUgT2JqZWN0IFNpZ25pbmcxHzAdBgNV
-BAsUFkphdmEgU2lnbmVkIEV4dGVuc2lvbnMxGzAZBgNVBAMUEkphdmFGWCAxLjAg
-UnVudGltZTCCASIwDQYJKoZIhvcNAQEBBQADggEPADCCAQoCggEBAM+WDc6+bu+4
-tmAcS/lBtUc02WOt9QZpVsXg9cG2pu/8bUtmDELa8iiYBVFpIs8DU58HLrGQtCUY
-SIAGOVPsOJoN29UKCDWfY9j5JeVhfhMGqk9DwrWhzgsjy4cpZ1pIp+k/fJ8zT8Ul
-aYLpow1vg3UNddsmwz02tN7cOrMw9WYIG4CRYnY1OrtJSfe2pYzheC4zyvR+aiVl
-nang2OtqikSQsNFOFHsLOJFxngy9LrO8evDSu25VTKI6zlWU6/bMeqtztJPN0VOn
-NyUrJZvkxZ207Jg0T693BGSxNC1n+ihztXogql8950M/pEuUbDjylv5FFvlp6DSB
-dDT2MkutmyMCAwEAAaOCAeowggHmMAkGA1UdEwQCMAAwDgYDVR0PAQH/BAQDAgeA
-MH8GA1UdHwR4MHYwdKByoHCGbmh0dHA6Ly9vbnNpdGVjcmwudmVyaXNpZ24uY29t
-L1N1bk1pY3Jvc3lzdGVtc0luY0NvcnBvcmF0ZU9iamVjdFNpZ25pbmdKYXZhU2ln
-bmVkRXh0ZW5zaW9uc0NsYXNzQi9MYXRlc3RDUkwuY3JsMB8GA1UdIwQYMBaAFLNH
-K4J+U7Rzyri7Gbe+gU0HlcftMB0GA1UdDgQWBBTjgufVi3XJ3gx1ewsA6Rr7BR4Z
-zjA7BggrBgEFBQcBAQQvMC0wKwYIKwYBBQUHMAGGH2h0dHA6Ly9vbnNpdGUtb2Nz
-cC52ZXJpc2lnbi5jb20wgbUGA1UdIASBrTCBqjA5BgtghkgBhvhFAQcXAjAqMCgG
-CCsGAQUFBwIBFhxodHRwczovL3d3dy52ZXJpc2lnbi5jb20vcnBhMG0GC2CGSAGG
-9wCDfZw/MF4wJwYIKwYBBQUHAgEWG2h0dHBzOi8vd3d3LnN1bi5jb20vcGtpL2Nw
-czAzBggrBgEFBQcCAjAnGiVWYWxpZGF0ZWQgRm9yIFN1biBCdXNpbmVzcyBPcGVy
-YXRpb25zMBMGA1UdJQQMMAoGCCsGAQUFBwMDMA0GCSqGSIb3DQEBBQUAA4IBAQAB
-YVJTTVe7rzyTO4jc3zajErOT/COkdQTfNo0eIX1QbNynFieJvwY/jRzUZwjktIFR
-2p4JtbpHGAtKtjOAOTieQ8xdDOoC1djzpE7/AbMvuvlTavtUKT+F7tPdhfXgWXJV
-6Wbt8jryKyk3zZGiEhauIwZUkfjRkEtffEmZWLUd8c8rURJjfC/XHH2oyurscoxc
-CjX29c9ynxSiS/VvQp1an0HvErGh69N48wj7cj8mtZ1yHzd2XCzSSR1OfTPfk0Pt
-yg51p7yJaFiH21PTZegEL6zyVNOYBTKwwIi2OzpwYalD3uvK6e3OKDrfFCOxu17u
-4PveESbrdyrmvLe7IVez
------END CERTIFICATE-----
-
-// Subject: CN=JavaFX Runtime,
-// OU=Java Signed Extensions,
-// OU=Corporate Object Signing,
-// O=Sun Microsystems Inc
-// Issuer: CN=Object Signing CA,
-// OU=Class 2 OnSite Subscriber CA,
-// OU=VeriSign Trust Network,
-// O=Sun Microsystems Inc
-// Serial: 47:f4:55:f1:da:4a:5e:f9:e3:f7:a8:03:62:17:c0:ff
------BEGIN CERTIFICATE-----
-MIIFdjCCBF6gAwIBAgIQR/RV8dpKXvnj96gDYhfA/zANBgkqhkiG9w0BAQUFADCB
-gzEdMBsGA1UEChMUU3VuIE1pY3Jvc3lzdGVtcyBJbmMxHzAdBgNVBAsTFlZlcmlT
-aWduIFRydXN0IE5ldHdvcmsxJTAjBgNVBAsTHENsYXNzIDIgT25TaXRlIFN1YnNj
-cmliZXIgQ0ExGjAYBgNVBAMTEU9iamVjdCBTaWduaW5nIENBMB4XDTA5MDEyOTAw
-MDAwMFoXDTEyMDEyOTIzNTk1OVowfDEdMBsGA1UEChQUU3VuIE1pY3Jvc3lzdGVt
-cyBJbmMxITAfBgNVBAsUGENvcnBvcmF0ZSBPYmplY3QgU2lnbmluZzEfMB0GA1UE
-CxQWSmF2YSBTaWduZWQgRXh0ZW5zaW9uczEXMBUGA1UEAxQOSmF2YUZYIFJ1bnRp
-bWUwggEiMA0GCSqGSIb3DQEBAQUAA4IBDwAwggEKAoIBAQCIzd0fAk8mI9ONc6RJ
-aGieioK2FLdXEwj8zL3vdGDVmBwyR1zwYkaOIFFgF9IW/8qc4iAYA5sGUY+0g8q3
-5DuYAxfTzBB5KdaYvbuq6GGnoHIWmTirXY+1friFp8lyXSvtuEaGB1VHaBoZchEg
-k+UgeVDA43dHwcT1Ov3DePczJRUes8T/QHzLX+BxUDG43vjyncCEO/AjqLZxXEz2
-xrNbKLcH3lGMJK7hdbfssUfF5BjC38Hn71HauYlA43b2no+2y0Sjulwzez2YPbDC
-0GLR3TnKtA8dqOrnl5t3DniDbfOBNtBE3VOydJO0XW57Ng1HRXD023nm9ECPY2xp
-0N/pAgMBAAGjggHqMIIB5jAJBgNVHRMEAjAAMA4GA1UdDwEB/wQEAwIHgDB/BgNV
-HR8EeDB2MHSgcqBwhm5odHRwOi8vb25zaXRlY3JsLnZlcmlzaWduLmNvbS9TdW5N
-aWNyb3N5c3RlbXNJbmNDb3Jwb3JhdGVPYmplY3RTaWduaW5nSmF2YVNpZ25lZEV4
-dGVuc2lvbnNDbGFzc0IvTGF0ZXN0Q1JMLmNybDAfBgNVHSMEGDAWgBSzRyuCflO0
-c8q4uxm3voFNB5XH7TAdBgNVHQ4EFgQUvOdd0cKPj+Yik/iOBwTdphh5A+gwOwYI
-KwYBBQUHAQEELzAtMCsGCCsGAQUFBzABhh9odHRwOi8vb25zaXRlLW9jc3AudmVy
-aXNpZ24uY29tMIG1BgNVHSAEga0wgaowOQYLYIZIAYb4RQEHFwIwKjAoBggrBgEF
-BQcCARYcaHR0cHM6Ly93d3cudmVyaXNpZ24uY29tL3JwYTBtBgtghkgBhvcAg32c
-PzBeMCcGCCsGAQUFBwIBFhtodHRwczovL3d3dy5zdW4uY29tL3BraS9jcHMwMwYI
-KwYBBQUHAgIwJxolVmFsaWRhdGVkIEZvciBTdW4gQnVzaW5lc3MgT3BlcmF0aW9u
-czATBgNVHSUEDDAKBggrBgEFBQcDAzANBgkqhkiG9w0BAQUFAAOCAQEAbGcf2NjL
-AI93HG6ny2BbepaZA1a8xa/R6uUc7xV+Qw6MgLwFD4Q4i6LWUztQDvg9l68MM2/i
-Y9LEi1KM4lcNbK5+D+t9x98wXBiuojXhVdp5ZmC03EyEBbriopdBsmXVLDSu/Y3+
-zowOO5xwpMK3dbgsSDs2Vt0UosD3FTcRaD3GNfOhXMp+o1grHNiXF9YgkmdQbPPZ
-DQ2KBhFPCRJXBGvyKOqno/DTg0sQ3crGH/C4/4t7mnQXWldZotmJUZ0ONc9oD+Q1
-JAaguUKqIwn9yZ093ie+JWHbYNid9IIIPXYgtRxmf9a376WBhqhu56uJftBJ7x9g
-eQ7Lot6CSWCiFw==
------END CERTIFICATE-----
-
-// Subject: CN=Solaris INTERNAL DEVELOPMENT USE ONLY,
-// OU=Solaris Cryptographic Framework,
-// OU=Corporate Object Signing,
-// O=Sun Microsystems Inc
-// Issuer: CN=Object Signing CA,
-// OU=Class 2 OnSite Subscriber CA,
-// OU=VeriSign Trust Network,
-// O=Sun Microsystems Inc
-// Serial: 77:29:77:52:6a:19:7b:9a:a6:a2:c7:99:a0:e1:cd:8c
------BEGIN CERTIFICATE-----
-MIIFHjCCBAagAwIBAgIQdyl3UmoZe5qmoseZoOHNjDANBgkqhkiG9w0BAQUFADCB
-gzEdMBsGA1UEChMUU3VuIE1pY3Jvc3lzdGVtcyBJbmMxHzAdBgNVBAsTFlZlcmlT
-aWduIFRydXN0IE5ldHdvcmsxJTAjBgNVBAsTHENsYXNzIDIgT25TaXRlIFN1YnNj
-cmliZXIgQ0ExGjAYBgNVBAMTEU9iamVjdCBTaWduaW5nIENBMB4XDTA3MDEwNDAw
-MDAwMFoXDTEwMDEwMzIzNTk1OVowgZwxHTAbBgNVBAoUFFN1biBNaWNyb3N5c3Rl
-bXMgSW5jMSEwHwYDVQQLFBhDb3Jwb3JhdGUgT2JqZWN0IFNpZ25pbmcxKDAmBgNV
-BAsUH1NvbGFyaXMgQ3J5cHRvZ3JhcGhpYyBGcmFtZXdvcmsxLjAsBgNVBAMUJVNv
-bGFyaXMgSU5URVJOQUwgREVWRUxPUE1FTlQgVVNFIE9OTFkwgZ8wDQYJKoZIhvcN
-AQEBBQADgY0AMIGJAoGBALbNU4hf3mD5ArDI9pjgioAyvV3bjMPRQdCZniIeGJBp
-odFlSEH+Mh64W1DsY8coeZ7FvvGJkx9IpTMJW9k8w1oJK9UNqHyAQfaYjQyXi3xQ
-LJp62EvYdGfDlwOZejEcR/MbzZG+GOPMMvQj5+xyFDvLXNGfQNTnxw2qnBgCJXjj
-AgMBAAGjggH1MIIB8TAJBgNVHRMEAjAAMA4GA1UdDwEB/wQEAwIHgDCBiQYDVR0f
-BIGBMH8wfaB7oHmGd2h0dHA6Ly9vbnNpdGVjcmwudmVyaXNpZ24uY29tL1N1bk1p
-Y3Jvc3lzdGVtc0luY0NvcnBvcmF0ZU9iamVjdFNpZ25pbmdTb2xhcmlzQ3J5cHRv
-Z3JhcGhpY0ZyYW1ld29ya0NsYXNzQi9MYXRlc3RDUkwuY3JsMB8GA1UdIwQYMBaA
-FLNHK4J+U7Rzyri7Gbe+gU0HlcftMB0GA1UdDgQWBBRpfiGYkehTnsIzuN2H6AFb
-VCZG8jA7BggrBgEFBQcBAQQvMC0wKwYIKwYBBQUHMAGGH2h0dHA6Ly9vbnNpdGUt
-b2NzcC52ZXJpc2lnbi5jb20wgbUGA1UdIASBrTCBqjA5BgtghkgBhvhFAQcXAjAq
-MCgGCCsGAQUFBwIBFhxodHRwczovL3d3dy52ZXJpc2lnbi5jb20vcnBhMG0GC2CG
-SAGG9wCDfZw/MF4wJwYIKwYBBQUHAgEWG2h0dHBzOi8vd3d3LnN1bi5jb20vcGtp
-L2NwczAzBggrBgEFBQcCAjAnFiVWYWxpZGF0ZWQgRm9yIFN1biBCdXNpbmVzcyBP
-cGVyYXRpb25zMBMGA1UdJQQMMAoGCCsGAQUFBwMDMA0GCSqGSIb3DQEBBQUAA4IB
-AQCG5soy3LFHTFbA8/5SzDRhQoJkHUnOP0t3b6nvX6vZYRp649fje7TQOPRm1pFd
-CZ17J+tggdZwgzTqY4aYpJ00jZaK6pV37q/vgFC/ia6jDs8Q+ly9cEcadBZ5loYg
-cmxp9p57W2MNWx8VA8oFdNtKfF0jUNXbLNtvwGHmgR6YcwLrGN1b6/9Lt9bO3ODl
-FO+ZDwkfQz5ClUVrTx2dGBvKRYFqSG5S8JAfsgYhPvcacUQkA7ExyKvfRXLWVrce
-ZiPpcElbx+819H2sAPvVvparVeAruZGMAtejHZp9NFoowKen5drJp9VxePS4eM49
-3DepB6lKRrNRw66LNQol4ZBz
------END CERTIFICATE-----
-
-// Subject: EMAILADDRESS=info@diginotar.nl, CN=DigiNotar Cyber CA,
-// O=DigiNotar, C=NL
-// Issuer: CN=GTE CyberTrust Global Root,
-// OU=GTE CyberTrust Solutions, Inc.,
-// O=GTE Corporation,
-// C=US
-// Serial: 120000525 (07:27:10:0D)
------BEGIN CERTIFICATE-----
-MIIFWjCCBMOgAwIBAgIEBycQDTANBgkqhkiG9w0BAQUFADB1MQswCQYDVQQGEwJV
-UzEYMBYGA1UEChMPR1RFIENvcnBvcmF0aW9uMScwJQYDVQQLEx5HVEUgQ3liZXJU
-cnVzdCBTb2x1dGlvbnMsIEluYy4xIzAhBgNVBAMTGkdURSBDeWJlclRydXN0IEds
-b2JhbCBSb290MB4XDTA2MTAwNDEwNTQxMVoXDTExMTAwNDEwNTMxMVowYDELMAkG
-A1UEBhMCTkwxEjAQBgNVBAoTCURpZ2lOb3RhcjEbMBkGA1UEAxMSRGlnaU5vdGFy
-IEN5YmVyIENBMSAwHgYJKoZIhvcNAQkBFhFpbmZvQGRpZ2lub3Rhci5ubDCCAiIw
-DQYJKoZIhvcNAQEBBQADggIPADCCAgoCggIBANLOFQotqF6EZ639vu9Gx8i5z3P8
-9DS5+SxD52ATPXrjss87Z2yQrcC5P4RS8DVC3HTcKDu9UrSnrHJFF8bwieu0qiXy
-XUte0dmHutZ9fPXOMp8QM8WxSrtekTHC0OlBwpFkfglBO9uLCDdqqspS3rU5HsCI
-A6U/i5kTYUO1m4Kz7iBvz6FEouova0CfjytXraFTwoUiaZ2gP1HfC0GRDaXhqKpc
-SQhdvd5wQbEPyWNr0380dAIvNFp4dRxoeoFnivPaQPBgY/SSINcDpj2jHmfEhBtB
-pcmM5r3qSLYFFgizNxJa92E89zhvLpfgb1Y4VNMota0Ubi5LZLUnZbd1JQm2Bz2V
-VgIKgmCyc0XgMyZRdJq51FAc9k1bW1JSE1qmf6cO4ehBVGeYjIfVydNsy9NUkgYJ
-NEH3gW8/nsl8dVWw58Gzd+jDxAA1lUBwEEoF3iW7n1mlZLxHYL9g43aLE1Xd4XR6
-uc8kpmp/3mQiRFhogmoQ+T3lPhu5vfwi9GAEibtVbShV+t6OjRshFNc3izR7Tfay
-shDPM7F9HGKZSMsrbHaWVb8ZDR0fu2WqG46ZtcYokOWCLXhQIJr9eS8kf/CJKWn0
-fc1zvrPtTsHR7VJej/e4142HrbLZG1ES/1az4a80fVykeIgQnp0DxqWqoiRR90kU
-xbHuWUOV36toKDA/AgMBAAGjggGGMIIBgjASBgNVHRMBAf8ECDAGAQH/AgEBMFMG
-A1UdIARMMEowSAYJKwYBBAGxPgEAMDswOQYIKwYBBQUHAgEWLWh0dHA6Ly93d3cu
-cHVibGljLXRydXN0LmNvbS9DUFMvT21uaVJvb3QuaHRtbDAOBgNVHQ8BAf8EBAMC
-AQYwgaAGA1UdIwSBmDCBlYAUpgwdn2H/Bxe1vzhG20Mw1Y6wUgaheaR3MHUxCzAJ
-BgNVBAYTAlVTMRgwFgYDVQQKEw9HVEUgQ29ycG9yYXRpb24xJzAlBgNVBAsTHkdU
-RSBDeWJlclRydXN0IFNvbHV0aW9ucywgSW5jLjEjMCEGA1UEAxMaR1RFIEN5YmVy
-VHJ1c3QgR2xvYmFsIFJvb3SCAgGlMEUGA1UdHwQ+MDwwOqA4oDaGNGh0dHA6Ly93
-d3cucHVibGljLXRydXN0LmNvbS9jZ2ktYmluL0NSTC8yMDE4L2NkcC5jcmwwHQYD
-VR0OBBYEFKv5aN/PSjfXe0WMX3LeQETDZbvCMA0GCSqGSIb3DQEBBQUAA4GBAI9o
-a6VbB7pEZg4cqFwwezPkCiYE/O+eGjjWLqEf0JlHwnVkJP2eOyh2uSYoYZEMbSz4
-BJ98UAHV42mv7xXSRZskCSpmBU8lgcpdvqrBWSeuM46C9990sFWzjvjnN8huqlZE
-9r1TgSOWPbT6MopTZkQloiXGpjwljPDgKAYityZB
------END CERTIFICATE-----
-
-// Subject: CN=DigiNotar Cyber CA, O=DigiNotar, C=NL
-// Issuer: CN=GTE CyberTrust Global Root,
-// OU=GTE CyberTrust Solutions, Inc.,
-// O=GTE Corporation,
-// C=US
-// Serial: 120000505 (07:27:0F:F9)
------BEGIN CERTIFICATE-----
-MIIFODCCBKGgAwIBAgIEBycP+TANBgkqhkiG9w0BAQUFADB1MQswCQYDVQQGEwJV
-UzEYMBYGA1UEChMPR1RFIENvcnBvcmF0aW9uMScwJQYDVQQLEx5HVEUgQ3liZXJU
-cnVzdCBTb2x1dGlvbnMsIEluYy4xIzAhBgNVBAMTGkdURSBDeWJlclRydXN0IEds
-b2JhbCBSb290MB4XDTA2MDkyMDA5NDUzMloXDTEzMDkyMDA5NDQwNlowPjELMAkG
-A1UEBhMCTkwxEjAQBgNVBAoTCURpZ2lOb3RhcjEbMBkGA1UEAxMSRGlnaU5vdGFy
-IEN5YmVyIENBMIICIjANBgkqhkiG9w0BAQEFAAOCAg8AMIICCgKCAgEA0s4VCi2o
-XoRnrf2+70bHyLnPc/z0NLn5LEPnYBM9euOyzztnbJCtwLk/hFLwNULcdNwoO71S
-tKesckUXxvCJ67SqJfJdS17R2Ye61n189c4ynxAzxbFKu16RMcLQ6UHCkWR+CUE7
-24sIN2qqylLetTkewIgDpT+LmRNhQ7WbgrPuIG/PoUSi6i9rQJ+PK1etoVPChSJp
-naA/Ud8LQZENpeGoqlxJCF293nBBsQ/JY2vTfzR0Ai80Wnh1HGh6gWeK89pA8GBj
-9JIg1wOmPaMeZ8SEG0GlyYzmvepItgUWCLM3Elr3YTz3OG8ul+BvVjhU0yi1rRRu
-LktktSdlt3UlCbYHPZVWAgqCYLJzReAzJlF0mrnUUBz2TVtbUlITWqZ/pw7h6EFU
-Z5iMh9XJ02zL01SSBgk0QfeBbz+eyXx1VbDnwbN36MPEADWVQHAQSgXeJbufWaVk
-vEdgv2DjdosTVd3hdHq5zySman/eZCJEWGiCahD5PeU+G7m9/CL0YASJu1VtKFX6
-3o6NGyEU1zeLNHtN9rKyEM8zsX0cYplIyytsdpZVvxkNHR+7Zaobjpm1xiiQ5YIt
-eFAgmv15LyR/8IkpafR9zXO+s+1OwdHtUl6P97jXjYetstkbURL/VrPhrzR9XKR4
-iBCenQPGpaqiJFH3SRTFse5ZQ5Xfq2goMD8CAwEAAaOCAYYwggGCMBIGA1UdEwEB
-/wQIMAYBAf8CAQEwUwYDVR0gBEwwSjBIBgkrBgEEAbE+AQAwOzA5BggrBgEFBQcC
-ARYtaHR0cDovL3d3dy5wdWJsaWMtdHJ1c3QuY29tL0NQUy9PbW5pUm9vdC5odG1s
-MA4GA1UdDwEB/wQEAwIBBjCBoAYDVR0jBIGYMIGVgBSmDB2fYf8HF7W/OEbbQzDV
-jrBSBqF5pHcwdTELMAkGA1UEBhMCVVMxGDAWBgNVBAoTD0dURSBDb3Jwb3JhdGlv
-bjEnMCUGA1UECxMeR1RFIEN5YmVyVHJ1c3QgU29sdXRpb25zLCBJbmMuMSMwIQYD
-VQQDExpHVEUgQ3liZXJUcnVzdCBHbG9iYWwgUm9vdIICAaUwRQYDVR0fBD4wPDA6
-oDigNoY0aHR0cDovL3d3dy5wdWJsaWMtdHJ1c3QuY29tL2NnaS1iaW4vQ1JMLzIw
-MTgvY2RwLmNybDAdBgNVHQ4EFgQUq/lo389KN9d7RYxfct5ARMNlu8IwDQYJKoZI
-hvcNAQEFBQADgYEACcpiD427SuDUejUrBi3RKGG2rAH7g0m8rtQvLYauGYOl1h0T
-4he+/jJ06XoUOMqUXvcpAWlxG5Ea/aO7qh3Ke+IW/aGjDvMMX7LhIDGUK16Sdu36
-6bUjpr8KOwOpb1JgVM1f6bcvfKIn/UGDdbYN+3gm87FF6TKVKho1IZXFonU=
------END CERTIFICATE-----
-
-// Subject: CN=DigiNotar Cyber CA, O=DigiNotar, C=NL
-// Issuer: CN=GTE CyberTrust Global Root,
-// OU=GTE CyberTrust Solutions, Inc.,
-// O=GTE Corporation,
-// C=US
-// Serial: 120000515 (07:27:10:03)
------BEGIN CERTIFICATE-----
-MIIFODCCBKGgAwIBAgIEBycQAzANBgkqhkiG9w0BAQUFADB1MQswCQYDVQQGEwJV
-UzEYMBYGA1UEChMPR1RFIENvcnBvcmF0aW9uMScwJQYDVQQLEx5HVEUgQ3liZXJU
-cnVzdCBTb2x1dGlvbnMsIEluYy4xIzAhBgNVBAMTGkdURSBDeWJlclRydXN0IEds
-b2JhbCBSb290MB4XDTA2MDkyNzEwNTMzMloXDTExMDkyNzEwNTIzMFowPjELMAkG
-A1UEBhMCTkwxEjAQBgNVBAoTCURpZ2lOb3RhcjEbMBkGA1UEAxMSRGlnaU5vdGFy
-IEN5YmVyIENBMIICIjANBgkqhkiG9w0BAQEFAAOCAg8AMIICCgKCAgEA0s4VCi2o
-XoRnrf2+70bHyLnPc/z0NLn5LEPnYBM9euOyzztnbJCtwLk/hFLwNULcdNwoO71S
-tKesckUXxvCJ67SqJfJdS17R2Ye61n189c4ynxAzxbFKu16RMcLQ6UHCkWR+CUE7
-24sIN2qqylLetTkewIgDpT+LmRNhQ7WbgrPuIG/PoUSi6i9rQJ+PK1etoVPChSJp
-naA/Ud8LQZENpeGoqlxJCF293nBBsQ/JY2vTfzR0Ai80Wnh1HGh6gWeK89pA8GBj
-9JIg1wOmPaMeZ8SEG0GlyYzmvepItgUWCLM3Elr3YTz3OG8ul+BvVjhU0yi1rRRu
-LktktSdlt3UlCbYHPZVWAgqCYLJzReAzJlF0mrnUUBz2TVtbUlITWqZ/pw7h6EFU
-Z5iMh9XJ02zL01SSBgk0QfeBbz+eyXx1VbDnwbN36MPEADWVQHAQSgXeJbufWaVk
-vEdgv2DjdosTVd3hdHq5zySman/eZCJEWGiCahD5PeU+G7m9/CL0YASJu1VtKFX6
-3o6NGyEU1zeLNHtN9rKyEM8zsX0cYplIyytsdpZVvxkNHR+7Zaobjpm1xiiQ5YIt
-eFAgmv15LyR/8IkpafR9zXO+s+1OwdHtUl6P97jXjYetstkbURL/VrPhrzR9XKR4
-iBCenQPGpaqiJFH3SRTFse5ZQ5Xfq2goMD8CAwEAAaOCAYYwggGCMBIGA1UdEwEB
-/wQIMAYBAf8CAQEwUwYDVR0gBEwwSjBIBgkrBgEEAbE+AQAwOzA5BggrBgEFBQcC
-ARYtaHR0cDovL3d3dy5wdWJsaWMtdHJ1c3QuY29tL0NQUy9PbW5pUm9vdC5odG1s
-MA4GA1UdDwEB/wQEAwIBBjCBoAYDVR0jBIGYMIGVgBSmDB2fYf8HF7W/OEbbQzDV
-jrBSBqF5pHcwdTELMAkGA1UEBhMCVVMxGDAWBgNVBAoTD0dURSBDb3Jwb3JhdGlv
-bjEnMCUGA1UECxMeR1RFIEN5YmVyVHJ1c3QgU29sdXRpb25zLCBJbmMuMSMwIQYD
-VQQDExpHVEUgQ3liZXJUcnVzdCBHbG9iYWwgUm9vdIICAaUwRQYDVR0fBD4wPDA6
-oDigNoY0aHR0cDovL3d3dy5wdWJsaWMtdHJ1c3QuY29tL2NnaS1iaW4vQ1JMLzIw
-MTgvY2RwLmNybDAdBgNVHQ4EFgQUq/lo389KN9d7RYxfct5ARMNlu8IwDQYJKoZI
-hvcNAQEFBQADgYEAWcyGZhizJlRP1jjNupZey+yZG6oMDW4Z11boriMHbYPCndBE
-bVh07zmPbZsihOw9w/vm5KbVX5CgxUv4Rhzh/20Faixf3P3bpWg0qgzHVVusNVR/
-P50aKkpdK3hp+QLl56e+lWOddSAINIpmcuyDI1hyuzB+GJEASm9tNU/6rs8=
------END CERTIFICATE-----
-
-// Subject: EMAILADDRESS=info@diginotar.nl,
-// CN=DigiNotar Root CA,
-// O=DigiNotar, C=NL
-// Issuer: CN=Entrust.net Secure Server Certification Authority
-// OU=(c) 1999 Entrust.net Limited,
-// OU=www.entrust.net/CPS incorp. by ref. (limits liab.),
-// O=Entrust.net,
-// C=US,
-// Serial: 1184644297 (46:9C:3C:C9)
------BEGIN CERTIFICATE-----
-MIIFSDCCBLGgAwIBAgIERpw8yTANBgkqhkiG9w0BAQUFADCBwzELMAkGA1UEBhMC
-VVMxFDASBgNVBAoTC0VudHJ1c3QubmV0MTswOQYDVQQLEzJ3d3cuZW50cnVzdC5u
-ZXQvQ1BTIGluY29ycC4gYnkgcmVmLiAobGltaXRzIGxpYWIuKTElMCMGA1UECxMc
-KGMpIDE5OTkgRW50cnVzdC5uZXQgTGltaXRlZDE6MDgGA1UEAxMxRW50cnVzdC5u
-ZXQgU2VjdXJlIFNlcnZlciBDZXJ0aWZpY2F0aW9uIEF1dGhvcml0eTAeFw0wNzA0
-MjYwNTAwMDBaFw0xMzA4MTQyMDEyMzZaMF8xCzAJBgNVBAYTAk5MMRIwEAYDVQQK
-EwlEaWdpTm90YXIxGjAYBgNVBAMTEURpZ2lOb3RhciBSb290IENBMSAwHgYJKoZI
-hvcNAQkBFhFpbmZvQGRpZ2lub3Rhci5ubDCCAiIwDQYJKoZIhvcNAQEBBQADggIP
-ADCCAgoCggIBAKywWMEAvdghCAsrmv5uVjAFnxt3kBBBXMMNhxF3joHxynzpjGrt
-OHQ1u9rf+bvACTe0lnOBfTMamDn3k2+Vfz25sXWHulFI6ItwPpUExdi2wxbZiLCx
-hx1w2oa0DxSLes8Q0XQ2ohJ7d4ZKeeZ73wIRaKVOhq40WJskE3hWIiUeAYtLUXH7
-gsxZlmmIWmhTxbkNAjfLS7xmSpB+KgsFB+0WX1WQddhGyRuD4gi+8SPMmR3WKg+D
-IBVYJ4Iu+uIiwkmxuQGBap1tnUB3aHZOISpthECFTnaZfILz87cCWdQmARuO361T
-BtGuGN3isjrL14g4jqxbKbkZ05j5GAPPSIKGZgsbaQ/J6ziIeiYaBUyS1yTUlvKs
-Ui2jR9VS9j/+zoQGcKaqPqLytlY0GFei5IFt58rwatPHkWsCg0F8Fe9rmmRe49A8
-5bHre12G+8vmd0nNo2Xc97mcuOQLX5PPzDAaMhzOHGOVpfnq4XSLnukrqTB7oBgf
-DhgL5Vup09FsHgdnj5FLqYq80maqkwGIspH6MVzVpsFSCAnNCmOi0yKm6KHZOQaX
-9W6NApCMFHs/gM0bnLrEWHIjr7ZWn8Z6QjMpBz+CyeYfBQ3NTCg2i9PIPhzGiO9e
-7olk6R3r2ol+MqZp0d3MiJ/R0MlmIdwGZ8WUepptYkx9zOBkgLKeR46jAgMBAAGj
-ggEmMIIBIjASBgNVHRMBAf8ECDAGAQH/AgEBMCcGA1UdJQQgMB4GCCsGAQUFBwMB
-BggrBgEFBQcDAgYIKwYBBQUHAwQwEQYDVR0gBAowCDAGBgRVHSAAMDMGCCsGAQUF
-BwEBBCcwJTAjBggrBgEFBQcwAYYXaHR0cDovL29jc3AuZW50cnVzdC5uZXQwMwYD
-VR0fBCwwKjAooCagJIYiaHR0cDovL2NybC5lbnRydXN0Lm5ldC9zZXJ2ZXIxLmNy
-bDAdBgNVHQ4EFgQUiGi/4I41xDs4a2L3KDuEgcgM100wCwYDVR0PBAQDAgEGMB8G
-A1UdIwQYMBaAFPAXYhNVPbP/CgBr+1CEl/PtYtAaMBkGCSqGSIb2fQdBAAQMMAob
-BFY3LjEDAgCBMA0GCSqGSIb3DQEBBQUAA4GBAI979rBep8tu3TeLunapgsZ0jtXp
-GDFjKWSk87dj1jCyYi+q/GyDyZ6ZQZNRP0sF+6twscq05lClWNy3TROMp7QeuoLO
-G7Utw3OJaswUtp4YglANMRTHEe3g9ltifUXRH5tSuy7u6yi4LD4WTm5ULP6r/g6l
-0CnjXYb0+b1Fmz6U
------END CERTIFICATE-----
-
-// Subject: EMAILADDRESS=info@diginotar.nl,
-// CN=DigiNotar Root CA,
-// O=DigiNotar, C=NL
-// Issuer: CN=Entrust.net Secure Server Certification Authority
-// OU=(c) 1999 Entrust.net Limited,
-// OU=www.entrust.net/CPS incorp. by ref. (limits liab.),
-// O=Entrust.net,
-// C=US,
-// Serial: 1184640175 (46:9C:2C:AF)
------BEGIN CERTIFICATE-----
-MIIFSDCCBLGgAwIBAgIERpwsrzANBgkqhkiG9w0BAQUFADCBwzELMAkGA1UEBhMC
-VVMxFDASBgNVBAoTC0VudHJ1c3QubmV0MTswOQYDVQQLEzJ3d3cuZW50cnVzdC5u
-ZXQvQ1BTIGluY29ycC4gYnkgcmVmLiAobGltaXRzIGxpYWIuKTElMCMGA1UECxMc
-KGMpIDE5OTkgRW50cnVzdC5uZXQgTGltaXRlZDE6MDgGA1UEAxMxRW50cnVzdC5u
-ZXQgU2VjdXJlIFNlcnZlciBDZXJ0aWZpY2F0aW9uIEF1dGhvcml0eTAeFw0wNzA3
-MjYxNTU3MzlaFw0xMzA4MjYxNjI3MzlaMF8xCzAJBgNVBAYTAk5MMRIwEAYDVQQK
-EwlEaWdpTm90YXIxGjAYBgNVBAMTEURpZ2lOb3RhciBSb290IENBMSAwHgYJKoZI
-hvcNAQkBFhFpbmZvQGRpZ2lub3Rhci5ubDCCAiIwDQYJKoZIhvcNAQEBBQADggIP
-ADCCAgoCggIBAKywWMEAvdghCAsrmv5uVjAFnxt3kBBBXMMNhxF3joHxynzpjGrt
-OHQ1u9rf+bvACTe0lnOBfTMamDn3k2+Vfz25sXWHulFI6ItwPpUExdi2wxbZiLCx
-hx1w2oa0DxSLes8Q0XQ2ohJ7d4ZKeeZ73wIRaKVOhq40WJskE3hWIiUeAYtLUXH7
-gsxZlmmIWmhTxbkNAjfLS7xmSpB+KgsFB+0WX1WQddhGyRuD4gi+8SPMmR3WKg+D
-IBVYJ4Iu+uIiwkmxuQGBap1tnUB3aHZOISpthECFTnaZfILz87cCWdQmARuO361T
-BtGuGN3isjrL14g4jqxbKbkZ05j5GAPPSIKGZgsbaQ/J6ziIeiYaBUyS1yTUlvKs
-Ui2jR9VS9j/+zoQGcKaqPqLytlY0GFei5IFt58rwatPHkWsCg0F8Fe9rmmRe49A8
-5bHre12G+8vmd0nNo2Xc97mcuOQLX5PPzDAaMhzOHGOVpfnq4XSLnukrqTB7oBgf
-DhgL5Vup09FsHgdnj5FLqYq80maqkwGIspH6MVzVpsFSCAnNCmOi0yKm6KHZOQaX
-9W6NApCMFHs/gM0bnLrEWHIjr7ZWn8Z6QjMpBz+CyeYfBQ3NTCg2i9PIPhzGiO9e
-7olk6R3r2ol+MqZp0d3MiJ/R0MlmIdwGZ8WUepptYkx9zOBkgLKeR46jAgMBAAGj
-ggEmMIIBIjASBgNVHRMBAf8ECDAGAQH/AgEBMCcGA1UdJQQgMB4GCCsGAQUFBwMB
-BggrBgEFBQcDAgYIKwYBBQUHAwQwEQYDVR0gBAowCDAGBgRVHSAAMDMGCCsGAQUF
-BwEBBCcwJTAjBggrBgEFBQcwAYYXaHR0cDovL29jc3AuZW50cnVzdC5uZXQwMwYD
-VR0fBCwwKjAooCagJIYiaHR0cDovL2NybC5lbnRydXN0Lm5ldC9zZXJ2ZXIxLmNy
-bDAdBgNVHQ4EFgQUiGi/4I41xDs4a2L3KDuEgcgM100wCwYDVR0PBAQDAgEGMB8G
-A1UdIwQYMBaAFPAXYhNVPbP/CgBr+1CEl/PtYtAaMBkGCSqGSIb2fQdBAAQMMAob
-BFY3LjEDAgCBMA0GCSqGSIb3DQEBBQUAA4GBAEa6RcDNcEIGUlkDJUY/pWTds4zh
-xbVkp3wSmpwPFhx5fxTyF4HD2L60jl3aqjTB7gPpsL2Pk5QZlNsi3t4UkCV70UOd
-ueJRN3o/LOtk4+bjXY2lC0qTHbN80VMLqPjmaf9ghSA9hwhskdtMgRsgfd90q5QP
-ZFdYf+hthc3m6IcJ
------END CERTIFICATE-----
-
-// Subject: CN=DigiNotar PKIoverheid CA Organisatie - G2,
-// O=DigiNotar B.V.,
-// C=NL
-// Issuer: CN=Staat der Nederlanden Organisatie CA - G2,
-// O=Staat der Nederlanden,
-// C=NL
-// Serial: 20001983 (01:31:34:bf)
------BEGIN CERTIFICATE-----
-MIIGnDCCBISgAwIBAgIEATE0vzANBgkqhkiG9w0BAQsFADBhMQswCQYDVQQGEwJO
-TDEeMBwGA1UECgwVU3RhYXQgZGVyIE5lZGVybGFuZGVuMTIwMAYDVQQDDClTdGFh
-dCBkZXIgTmVkZXJsYW5kZW4gT3JnYW5pc2F0aWUgQ0EgLSBHMjAeFw0xMDA1MTIw
-ODUxMzhaFw0yMDAzMjMwOTUwMDRaMFoxCzAJBgNVBAYTAk5MMRcwFQYDVQQKDA5E
-aWdpTm90YXIgQi5WLjEyMDAGA1UEAwwpRGlnaU5vdGFyIFBLSW92ZXJoZWlkIENB
-IE9yZ2FuaXNhdGllIC0gRzIwggIiMA0GCSqGSIb3DQEBAQUAA4ICDwAwggIKAoIC
-AQCxExkPJ+Zs1FWGS9DsiYpFkXisR71HK+T8RetPtCZzWzfTw3/2497Xo/gtaMUI
-PkuU1uSHJTZrhLUYdPMoWHMvm2rPvAQe9t7dr/xLqvXbZmIlASWC3vKXWhBu3V2p
-IrEEqSNzOvhxrR3PhETrR9Gvbch8KKvH8jd6dF9fxQIUiqNa4xtsAeNdjtlo1vQJ
-GzLckbUs9SDrjANtJkm4k8SFXdjSm69WaswFM8ygQp40VUSca6DUEtArVM23iQ3l
-9uvo+4UBM096a/GdcjOWDveyhKWlJ8Qn8VFzKXe6Z27+TNy04qGhgS85SY1DOBPO
-0KVcwoc6AGdlQiPxNlkKHaNRyLyjlCox3+M88p0aPASw77EKMBNzttfzo0wBdRSF
-eMDXijlYhVD6LubFvs+LP6+PNtQlCS3SD6xyk/K/i9RQs/kVUJuZ9RTZ+4uRozIm
-JqD43ztggYaDeVsr6xM9KTrBbd29no6H1kquNJcF7hSm9tw4fkrpJFQHPZdoN0Zr
-DceoIa8TVOQJavFNRgrJXfubT73e+7dUy7g4nKc5+2otwHuNq6WnV+xKkoozxeEg
-XHPYkJIrgNUPhhhpfDlPhIa890xb89W0yqDC8DciynlSH1PmqvOQsDvd8ij9rOvF
-BiSgydQvD1j9tZ7sD8+yWdCiBHo4aq5y+73wJWKUCacFCwIDAQABo4IBYTCCAV0w
-SAYDVR0gBEEwPzA9BgRVHSAAMDUwMwYIKwYBBQUHAgEWJ2h0dHA6Ly93d3cuZGln
-aW5vdGFyLm5sL2Nwcy9wa2lvdmVyaGVpZDAPBgNVHRMBAf8EBTADAQH/MA4GA1Ud
-DwEB/wQEAwIBBjCBhQYDVR0jBH4wfIAUORCLSZJc22ESIM1JnRqO2pxnQLmhXqRc
-MFoxCzAJBgNVBAYTAk5MMR4wHAYDVQQKDBVTdGFhdCBkZXIgTmVkZXJsYW5kZW4x
-KzApBgNVBAMMIlN0YWF0IGRlciBOZWRlcmxhbmRlbiBSb290IENBIC0gRzKCBACY
-lvQwSQYDVR0fBEIwQDA+oDygOoY4aHR0cDovL2NybC5wa2lvdmVyaGVpZC5ubC9E
-b21PcmdhbmlzYXRpZUxhdGVzdENSTC1HMi5jcmwwHQYDVR0OBBYEFLxdlDvZq3sD
-JXNhwtst7vyrj2WhMA0GCSqGSIb3DQEBCwUAA4ICAQCP/C1Mt9kt1R+978v0t2gX
-dZ1O1ffdnPEqJu2forYcA9VTs+wIzzTi48P0tRYvyMO+19NzqwA2+RpKftZj6V5G
-uqW2jhW3oyrYQx3vXcgfgYWzi/f/PPTZ9EYIP5y8HaDZqEzNJVJOCrEg9x/pQ9lU
-RoETmsBedGwqmDLq/He7DaWiMZgifnx859qkrey3LhoZcfhIUNpDjyyE3cFAJ+O1
-8BVOltT4XOOGKUYr1zsH6zh/yIZXl9PvKjPEF1DVZGlrK2tFXl0vF8paTs/D1zk8
-9TufRrmb5w5Jl53W1eMbD+qPAU6aE5RZCgIHSEsaYKt/T+0L2FUNaG9VnGllFULs
-wNzdbKzDFs4LHVabpMTE0i7gD+JEJytQaaTcYuiKISlCbMwAOpZ2m+9AwKRed4Qy
-bCYqOWauXeO5ubIsaB8empADOfCqs6TMSYsYNOk3yXspx4R8b0QVL+xhWQTJRcui
-1lKifH8pktZKxYtCqNT+6tjHhyMY5J16fXNAUpigrm7jBT8FD+Clxm1N7YM3iJzH
-89xCmmq21yFJNnfy7xhPxXDZnunetyuL9Lx+KN8NQMmFXK6dxTH/0FwOtah+8Okv
-uq+IruW10Vilr5xxpykBkINpN4IFuvwJwQhujHg7wzMCgD9EhQgd31VWCK0shS1d
-sQPhrqp0xaTzTro3mHuCuQ==
------END CERTIFICATE-----
-
-// Subject: CN=DigiNotar PKIoverheid CA Overheid en Bedrijven,
-// O=DigiNotar B.V.,
-// C=NL
-// Issuer: CN=Staat der Nederlanden Overheid CA
-// O=Staat der Nederlanden,
-// C=NL
-// Serial: 20015536 (01:31:69:b0)
------BEGIN CERTIFICATE-----
-MIIEiDCCA3CgAwIBAgIEATFpsDANBgkqhkiG9w0BAQUFADBZMQswCQYDVQQGEwJO
-TDEeMBwGA1UEChMVU3RhYXQgZGVyIE5lZGVybGFuZGVuMSowKAYDVQQDEyFTdGFh
-dCBkZXIgTmVkZXJsYW5kZW4gT3ZlcmhlaWQgQ0EwHhcNMDcwNzA1MDg0MjA3WhcN
-MTUwNzI3MDgzOTQ2WjBfMQswCQYDVQQGEwJOTDEXMBUGA1UEChMORGlnaU5vdGFy
-IEIuVi4xNzA1BgNVBAMTLkRpZ2lOb3RhciBQS0lvdmVyaGVpZCBDQSBPdmVyaGVp
-ZCBlbiBCZWRyaWp2ZW4wggEiMA0GCSqGSIb3DQEBAQUAA4IBDwAwggEKAoIBAQDc
-vdKnTmoKuzuiheF/AK2+tDBomAfNoHrElM9x+Yo35FPrV3bMi+Zs/u6HVcg+uwQ5
-AKeAeKxbT370vbhUuHE7BzFJOZNUfCA7eSuPu2GQfbGs5h+QLp1FAalkLU3DL7nn
-UNVOKlyrdnY3Rtd57EKZ96LspIlw3Dgrh6aqJOadkiQbvvb91C8ZF3rmMgeUVAVT
-Q+lsvK9Hy7zL/b07RBKB8WtLu+20z6slTxjSzAL8o0+1QjPLWc0J3NNQ/aB2jKx+
-ZopC9q0ckvO2+xRG603XLzDgbe5bNr5EdLcgBVeFTegAGaL2DOauocBC36esgl3H
-aLcY5olLmmv6znn58yynAgMBAAGjggFQMIIBTDBIBgNVHSAEQTA/MD0GBFUdIAAw
-NTAzBggrBgEFBQcCARYnaHR0cDovL3d3dy5kaWdpbm90YXIubmwvY3BzL3BraW92
-ZXJoZWlkMA8GA1UdEwEB/wQFMAMBAf8wDgYDVR0PAQH/BAQDAgEGMIGABgNVHSME
-eTB3gBQLhtYPd6NosftkCcOIblwEHFfpPaFZpFcwVTELMAkGA1UEBhMCTkwxHjAc
-BgNVBAoTFVN0YWF0IGRlciBOZWRlcmxhbmRlbjEmMCQGA1UEAxMdU3RhYXQgZGVy
-IE5lZGVybGFuZGVuIFJvb3QgQ0GCBACYmnkwPQYDVR0fBDYwNDAyoDCgLoYsaHR0
-cDovL2NybC5wa2lvdmVyaGVpZC5ubC9Eb21PdkxhdGVzdENSTC5jcmwwHQYDVR0O
-BBYEFEwIyY128ZjHPt881y91DbF2eZfMMA0GCSqGSIb3DQEBBQUAA4IBAQAMlIca
-v03jheLu19hjeQ5Q38aEW9K72fUxCho1l3TfFPoqDz7toOMI9tVOW6+mriXiRWsi
-D7dUKH6S3o0UbNEc5W50BJy37zRERd/Jgx0ZH8Apad+J1T/CsFNt5U4X5HNhIxMm
-cUP9TFnLw98iqiEr2b+VERqKpOKrp11Lbyn1UtHk0hWxi/7wA8+nfemZhzizDXMU
-5HIs4c71rQZIZPrTKbmi2Lv01QulQERDjqC/zlqlUkxk0xcxYczopIro5Ij76eUv
-BjMzm5RmZrGrUDqhCYF0U1onuabSJc/Tw6f/ltAv6uAejVLpGBwgCkegllYOQJBR
-RKwa/fHuhR/3Qlpl
------END CERTIFICATE-----
-
-// Subject: CN=DigiNotar PKIoverheid CA Overheid
-// O=DigiNotar B.V.,
-// C=NL
-// Issuer: CN=Staat der Nederlanden Overheid CA
-// O=Staat der Nederlanden,
-// C=NL
-// Serial: 20006006 (01:31:44:76)
------BEGIN CERTIFICATE-----
-MIIEezCCA2OgAwIBAgIEATFEdjANBgkqhkiG9w0BAQUFADBZMQswCQYDVQQGEwJO
-TDEeMBwGA1UEChMVU3RhYXQgZGVyIE5lZGVybGFuZGVuMSowKAYDVQQDEyFTdGFh
-dCBkZXIgTmVkZXJsYW5kZW4gT3ZlcmhlaWQgQ0EwHhcNMDQwNjI0MDgxOTMyWhcN
-MTAwNjIzMDgxNzM2WjBSMQswCQYDVQQGEwJOTDEXMBUGA1UEChMORGlnaU5vdGFy
-IEIuVi4xKjAoBgNVBAMTIURpZ2lOb3RhciBQS0lvdmVyaGVpZCBDQSBPdmVyaGVp
-ZDCCASIwDQYJKoZIhvcNAQEBBQADggEPADCCAQoCggEBANSlrubta5tlOjVCi/gb
-yLCvRqfBjxG8H594VcKHu0WAYc99SPZF9cycj5mw2GyfQvy/WIrGrL4iyNq1gSqR
-0QA/mTXKZIaPqzpDhdm+VvrKkmjrbZfaQxgMSs3ChtBsjcP9Lc0X1zXZ4Q8nBe3k
-BTp+zehINfmbjoEgXLxsMR5RQ6GxzKjuC04PQpbJQgTIakglKaqYcDDZbEscWgPV
-Hgj/2aoHlj6leW/ThHZ+O41jUguEmBLZA3mu3HrCfrHntb5dPt0ihzSx7GtD/SaX
-5HBLxnP189YuqMk5iRA95CtiSdKauvon/xRKRLNgG6XAz0ctSoY7xLDdiBVU5kJd
-FScCAwEAAaOCAVAwggFMMEgGA1UdIARBMD8wPQYEVR0gADA1MDMGCCsGAQUFBwIB
-FidodHRwOi8vd3d3LmRpZ2lub3Rhci5ubC9jcHMvcGtpb3ZlcmhlaWQwDwYDVR0T
-AQH/BAUwAwEB/zAOBgNVHQ8BAf8EBAMCAQYwgYAGA1UdIwR5MHeAFAuG1g93o2ix
-+2QJw4huXAQcV+k9oVmkVzBVMQswCQYDVQQGEwJOTDEeMBwGA1UEChMVU3RhYXQg
-ZGVyIE5lZGVybGFuZGVuMSYwJAYDVQQDEx1TdGFhdCBkZXIgTmVkZXJsYW5kZW4g
-Um9vdCBDQYIEAJiaeTA9BgNVHR8ENjA0MDKgMKAuhixodHRwOi8vY3JsLnBraW92
-ZXJoZWlkLm5sL0RvbU92TGF0ZXN0Q1JMLmNybDAdBgNVHQ4EFgQUvRaYQh2+kdE9
-wpcl4CjXWOC1f+IwDQYJKoZIhvcNAQEFBQADggEBAGhQsCWLiaN2EOhPAW+JQP6o
-XBOrLv5w6joahzBFVn1BiefzmlMKjibqKYxURRvMAsMkh82/MfL8V0w6ugxl81lu
-i42dcxl9cKSVXKMw4bbBzJ2VQI5HTIABwefeNuy/eX6idVwYdt3ajAH7fUA8Q9Cq
-vr6H8B+8mwoEqTVTEVlCSsC/EXsokYEUr06PPzRudKjDmijgj7zFaIioZNc8hk7g
-ufEgrs/tmcNGylrwRHgCXjCRBt2NHlZ08l7A1AGU8HcHlSbG9Un/2q9kVHUkps0D
-gtUaEK+x6jpAu/R8Ojezu/+ZEcwwjI/KOhG+84+ejFmtyEkrUdsAdEdLf/2dKsw=
------END CERTIFICATE-----
-
-// Subject: EMAILADDRESS=info@diginotar.nl,
-// CN=DigiNotar Services 1024 CA
-// O=DigiNotar, C=NL
-// Issuer: CN=Entrust.net Secure Server Certification Authority,
-// OU=(c) 1999 Entrust.net Limited,
-// OU=www.entrust.net/CPS incorp. by ref. (limits liab.),
-// O=Entrust.net,
-// C=US
-// Serial: 1184640176 (46:9c:2c:b0)
------BEGIN CERTIFICATE-----
-MIIDzTCCAzagAwIBAgIERpwssDANBgkqhkiG9w0BAQUFADCBwzELMAkGA1UEBhMC
-VVMxFDASBgNVBAoTC0VudHJ1c3QubmV0MTswOQYDVQQLEzJ3d3cuZW50cnVzdC5u
-ZXQvQ1BTIGluY29ycC4gYnkgcmVmLiAobGltaXRzIGxpYWIuKTElMCMGA1UECxMc
-KGMpIDE5OTkgRW50cnVzdC5uZXQgTGltaXRlZDE6MDgGA1UEAxMxRW50cnVzdC5u
-ZXQgU2VjdXJlIFNlcnZlciBDZXJ0aWZpY2F0aW9uIEF1dGhvcml0eTAeFw0wNzA3
-MjYxNTU5MDBaFw0xMzA4MjYxNjI5MDBaMGgxCzAJBgNVBAYTAk5MMRIwEAYDVQQK
-EwlEaWdpTm90YXIxIzAhBgNVBAMTGkRpZ2lOb3RhciBTZXJ2aWNlcyAxMDI0IENB
-MSAwHgYJKoZIhvcNAQkBFhFpbmZvQGRpZ2lub3Rhci5ubDCBnzANBgkqhkiG9w0B
-AQEFAAOBjQAwgYkCgYEA2ptNXTz50eKLxsYIIMXZHkjsZlhneWIrQWP0iY1o2q+4
-lDaLGSSkoJPSmQ+yrS01Tc0vauH5mxkrvAQafi09UmTN8T5nD4ku6PJPrqYIoYX+
-oakJ5sarPkP8r3oDkdqmOaZh7phPGKjTs69mgumfvN1y+QYEvRLZGCTnq5NTi1kC
-AwEAAaOCASYwggEiMBIGA1UdEwEB/wQIMAYBAf8CAQAwJwYDVR0lBCAwHgYIKwYB
-BQUHAwEGCCsGAQUFBwMCBggrBgEFBQcDBDARBgNVHSAECjAIMAYGBFUdIAAwMwYI
-KwYBBQUHAQEEJzAlMCMGCCsGAQUFBzABhhdodHRwOi8vb2NzcC5lbnRydXN0Lm5l
-dDAzBgNVHR8ELDAqMCigJqAkhiJodHRwOi8vY3JsLmVudHJ1c3QubmV0L3NlcnZl
-cjEuY3JsMB0GA1UdDgQWBBT+3JRJDG/vXH/G8RKZTxZJrfuCZTALBgNVHQ8EBAMC
-AQYwHwYDVR0jBBgwFoAU8BdiE1U9s/8KAGv7UISX8+1i0BowGQYJKoZIhvZ9B0EA
-BAwwChsEVjcuMQMCAIEwDQYJKoZIhvcNAQEFBQADgYEAY3RqN6k/lpxmyFisCcnv
-9WWUf6MCxDgxvV0jh+zUVrLJsm7kBQb87PX6iHBZ1O7m3bV6oKNgLwIMq94SXa/w
-NUuqikeRGvWFLELHHe+VQ7NeuJWTpdrFKKqtci0xrZlrbP+MISevrZqRK8fdWMNu
-B8WfedLHjFW/TMcnXlEWKz4=
------END CERTIFICATE-----
-
-// Subject: CN=Buster Paper Comercial Ltda,
-// O=Buster Paper Comercial Ltda,
-// L=S?o Jos? Dos Campos,
-// ST=S?o Paulo,
-// C=BR
-// Issuer: CN=DigiCert Assured ID Code Signing CA-1,
-// OU=www.digicert.com,
-// O=DigiCert Inc,
-// C=US
-// Serial: 07:b4:4c:db:ff:fb:78:de:05:f4:26:16:72:a6:73:12
------BEGIN CERTIFICATE-----
-MIIGwzCCBaugAwIBAgIQB7RM2//7eN4F9CYWcqZzEjANBgkqhkiG9w0BAQUFADBv
-MQswCQYDVQQGEwJVUzEVMBMGA1UEChMMRGlnaUNlcnQgSW5jMRkwFwYDVQQLExB3
-d3cuZGlnaWNlcnQuY29tMS4wLAYDVQQDEyVEaWdpQ2VydCBBc3N1cmVkIElEIENv
-ZGUgU2lnbmluZyBDQS0xMB4XDTEzMDExNzAwMDAwMFoXDTE0MDEyMjEyMDAwMFow
-gY4xCzAJBgNVBAYTAkJSMRMwEQYDVQQIDApTw6NvIFBhdWxvMR4wHAYDVQQHDBVT
-w6NvIEpvc8OpIERvcyBDYW1wb3MxJDAiBgNVBAoTG0J1c3RlciBQYXBlciBDb21l
-cmNpYWwgTHRkYTEkMCIGA1UEAxMbQnVzdGVyIFBhcGVyIENvbWVyY2lhbCBMdGRh
-MIIBIjANBgkqhkiG9w0BAQEFAAOCAQ8AMIIBCgKCAQEAzO0l6jWIpEfO2oUpVHpL
-HETj5lzivNb0S9jKHgGJax917czh81PnGTxwxFXd6gLJuy/XFHvmiSi8g8jzlymn
-2Ji5zQ3CPaz7nomJokSUDlMVJ2qYWtctw4jrdjuI4qtn+koXXUFkWjkf8h8251I4
-tUs7S49HE2Go5owCYP3byajj7fsFAYR/Xb7TdVtndkZsUB/YgOjHovyACjouaNCi
-mDiRyQ6zLLjZGiyeD65Yiseuhp5b8/BL5h1p7w76QYMYMVQNAdtDKut2R8MBpuWf
-Ny7Eoi0x/gm1p9X5Rcl5aN7K0G4UtTAJKbkuUfXddsyFoM0Nx8uo8SgNQ8Y/X5Jx
-BwIDAQABo4IDOTCCAzUwHwYDVR0jBBgwFoAUe2jOKarAF75JeuHlP9an90WPNTIw
-HQYDVR0OBBYEFFLZ3n5nt/Eer7n1bvtOqMb1qKO5MA4GA1UdDwEB/wQEAwIHgDAT
-BgNVHSUEDDAKBggrBgEFBQcDAzBzBgNVHR8EbDBqMDOgMaAvhi1odHRwOi8vY3Js
-My5kaWdpY2VydC5jb20vYXNzdXJlZC1jcy0yMDExYS5jcmwwM6AxoC+GLWh0dHA6
-Ly9jcmw0LmRpZ2ljZXJ0LmNvbS9hc3N1cmVkLWNzLTIwMTFhLmNybDCCAcQGA1Ud
-IASCAbswggG3MIIBswYJYIZIAYb9bAMBMIIBpDA6BggrBgEFBQcCARYuaHR0cDov
-L3d3dy5kaWdpY2VydC5jb20vc3NsLWNwcy1yZXBvc2l0b3J5Lmh0bTCCAWQGCCsG
-AQUFBwICMIIBVh6CAVIAQQBuAHkAIAB1AHMAZQAgAG8AZgAgAHQAaABpAHMAIABD
-AGUAcgB0AGkAZgBpAGMAYQB0AGUAIABjAG8AbgBzAHQAaQB0AHUAdABlAHMAIABh
-AGMAYwBlAHAAdABhAG4AYwBlACAAbwBmACAAdABoAGUAIABEAGkAZwBpAEMAZQBy
-AHQAIABDAFAALwBDAFAAUwAgAGEAbgBkACAAdABoAGUAIABSAGUAbAB5AGkAbgBn
-ACAAUABhAHIAdAB5ACAAQQBnAHIAZQBlAG0AZQBuAHQAIAB3AGgAaQBjAGgAIABs
-AGkAbQBpAHQAIABsAGkAYQBiAGkAbABpAHQAeQAgAGEAbgBkACAAYQByAGUAIABp
-AG4AYwBvAHIAcABvAHIAYQB0AGUAZAAgAGgAZQByAGUAaQBuACAAYgB5ACAAcgBl
-AGYAZQByAGUAbgBjAGUALjCBggYIKwYBBQUHAQEEdjB0MCQGCCsGAQUFBzABhhho
-dHRwOi8vb2NzcC5kaWdpY2VydC5jb20wTAYIKwYBBQUHMAKGQGh0dHA6Ly9jYWNl
-cnRzLmRpZ2ljZXJ0LmNvbS9EaWdpQ2VydEFzc3VyZWRJRENvZGVTaWduaW5nQ0Et
-MS5jcnQwDAYDVR0TAQH/BAIwADANBgkqhkiG9w0BAQUFAAOCAQEAPTTQvpOIikXI
-hTLnNbajaFRR5GhQpTzUNgBfF9VYSlNw/wMjpGsrh5RxaJCip52jbehmTgjMRhft
-jRYyml44PAVsCcR9uEoDpCZYpI1fHI1R+F8jd1C9rqprbSwwOG4xlg4SmvTHYs6e
-gBItQ/1p9XY+Sf4Wv1qOuOFL1qvV/5VyR2zdlOQCmKCeMgxt6a/tHLBDiAA67D44
-/vfdoNJl0CU2It0PO60jdCPFNWIRcxL+OSDqAoePeUC7xQ+JsTEIxuUE8+d6w6fc
-BV2mYb1flh22t46GLjh4gyo7xw3aL6L0L0jzlTT6IcEw6NIbaPbIKj/npQnHobYj
-XMuKLxbh7g==
------END CERTIFICATE-----
-
-// Subject: CN=BUSTER ASSISTENCIA TECNICA ELETRONICA LTDA - ME,
-// O=BUSTER ASSISTENCIA TECNICA ELETRONICA LTDA - ME,
-// L=S?o Paulo,
-// ST=S?o Paulo,
-// C=BR
-// Issuer: CN=DigiCert Assured ID Code Signing CA-1,
-// OU=www.digicert.com,
-// O=DigiCert Inc,
-// C=US
-// Serial: 0a:38:9b:95:ee:73:6d:d1:3b:c0:ed:74:3f:d7:4d:2f
------BEGIN CERTIFICATE-----
-MIIG4DCCBcigAwIBAgIQCjible5zbdE7wO10P9dNLzANBgkqhkiG9w0BAQUFADBv
-MQswCQYDVQQGEwJVUzEVMBMGA1UEChMMRGlnaUNlcnQgSW5jMRkwFwYDVQQLExB3
-d3cuZGlnaWNlcnQuY29tMS4wLAYDVQQDEyVEaWdpQ2VydCBBc3N1cmVkIElEIENv
-ZGUgU2lnbmluZyBDQS0xMB4XDTEyMTEwOTAwMDAwMFoXDTEzMTExNDEyMDAwMFow
-gasxCzAJBgNVBAYTAkJSMRMwEQYDVQQIDApTw6NvIFBhdWxvMRMwEQYDVQQHDApT
-w6NvIFBhdWxvMTgwNgYDVQQKEy9CVVNURVIgQVNTSVNURU5DSUEgVEVDTklDQSBF
-TEVUUk9OSUNBIExUREEgLSBNRTE4MDYGA1UEAxMvQlVTVEVSIEFTU0lTVEVOQ0lB
-IFRFQ05JQ0EgRUxFVFJPTklDQSBMVERBIC0gTUUwggEiMA0GCSqGSIb3DQEBAQUA
-A4IBDwAwggEKAoIBAQDAqNeEs5/B2CTXGjTOkUIdu6jV6qulOZwdw4sefHWYj1UR
-4z6zPk9kjpUgbnb402RFq88QtfInwddZ/wXn9OxMtDd/3TnC7HrhNS7ga79ZFL2V
-JnmzKHum2Yvh0q82QEJ9tHBR2X9VdKpUIH08Zs3k6cWWM1H0YX0cxA/HohhesQJW
-kwJ3urOIJiH/HeByDk8a1NS8safcCxk5vxvW4WvCg43iT09LeHY5Aa8abKw8lqVb
-0tD5ZSIjdmdj3TT1U37iAHLLRM2DXbxfdbhouUX1c5U1ZHAMA67HwjKiseOiDaHj
-NUGbC37C+cgbc9VVM/cURD8WvS0Kj6fQv7F2QtJDAgMBAAGjggM5MIIDNTAfBgNV
-HSMEGDAWgBR7aM4pqsAXvkl64eU/1qf3RY81MjAdBgNVHQ4EFgQU88EXKAyDsh30
-o9+Gu9a4xUy+FSMwDgYDVR0PAQH/BAQDAgeAMBMGA1UdJQQMMAoGCCsGAQUFBwMD
-MHMGA1UdHwRsMGowM6AxoC+GLWh0dHA6Ly9jcmwzLmRpZ2ljZXJ0LmNvbS9hc3N1
-cmVkLWNzLTIwMTFhLmNybDAzoDGgL4YtaHR0cDovL2NybDQuZGlnaWNlcnQuY29t
-L2Fzc3VyZWQtY3MtMjAxMWEuY3JsMIIBxAYDVR0gBIIBuzCCAbcwggGzBglghkgB
-hv1sAwEwggGkMDoGCCsGAQUFBwIBFi5odHRwOi8vd3d3LmRpZ2ljZXJ0LmNvbS9z
-c2wtY3BzLXJlcG9zaXRvcnkuaHRtMIIBZAYIKwYBBQUHAgIwggFWHoIBUgBBAG4A
-eQAgAHUAcwBlACAAbwBmACAAdABoAGkAcwAgAEMAZQByAHQAaQBmAGkAYwBhAHQA
-ZQAgAGMAbwBuAHMAdABpAHQAdQB0AGUAcwAgAGEAYwBjAGUAcAB0AGEAbgBjAGUA
-IABvAGYAIAB0AGgAZQAgAEQAaQBnAGkAQwBlAHIAdAAgAEMAUAAvAEMAUABTACAA
-YQBuAGQAIAB0AGgAZQAgAFIAZQBsAHkAaQBuAGcAIABQAGEAcgB0AHkAIABBAGcA
-cgBlAGUAbQBlAG4AdAAgAHcAaABpAGMAaAAgAGwAaQBtAGkAdAAgAGwAaQBhAGIA
-aQBsAGkAdAB5ACAAYQBuAGQAIABhAHIAZQAgAGkAbgBjAG8AcgBwAG8AcgBhAHQA
-ZQBkACAAaABlAHIAZQBpAG4AIABiAHkAIAByAGUAZgBlAHIAZQBuAGMAZQAuMIGC
-BggrBgEFBQcBAQR2MHQwJAYIKwYBBQUHMAGGGGh0dHA6Ly9vY3NwLmRpZ2ljZXJ0
-LmNvbTBMBggrBgEFBQcwAoZAaHR0cDovL2NhY2VydHMuZGlnaWNlcnQuY29tL0Rp
-Z2lDZXJ0QXNzdXJlZElEQ29kZVNpZ25pbmdDQS0xLmNydDAMBgNVHRMBAf8EAjAA
-MA0GCSqGSIb3DQEBBQUAA4IBAQAei1QmiXepje8OIfo/WonD4MIXgpPr2dfRaquQ
-A8q63OpTRSveyqdQDCSPpDRF/nvO1Y30yksZvIH1tNBsW5LBdxAKN3lFdBlqBwtE
-Q3jHc0KVVYRJ0FBaGE/PJHmRajscdAhYIcMPhTga0u0tDK+wOHEq3993dfl6yHjA
-XHU2iW5pnk75ZoE39zALD5eKXT8ZXrET5c3XUFJKWA+XuGmdmyzqo0Au49PanBv9
-UlZnabYfqoMArqMS0tGSX4cGgi9/2E+pHG9BX4sFW+ZDumroOA2pxyMWEKjxePEL
-zCOfhbsRWdMLYepauaNZOIMZXmFwcrIl0TGMkTAtATz+XmZc
------END CERTIFICATE-----
-
-// Subject: CN=CLEARESULT CONSULTING INC., OU=Corporate IT,
-// O=CLEARESULT CONSULTING INC., L=Austin, ST=TX, C=US
-// Issuer: SERIALNUMBER=07969287,
-// CN=Go Daddy Secure Certification Authority,
-// OU=http://certificates.godaddy.com/repository,
-// O="GoDaddy.com, Inc.",
-// L=Scottsdale,
-// ST=Arizona,
-// C=US
-// Serial: 2b:73:43:2a:a8:4f:44
------BEGIN CERTIFICATE-----
-MIIFYjCCBEqgAwIBAgIHK3NDKqhPRDANBgkqhkiG9w0BAQUFADCByjELMAkGA1UE
-BhMCVVMxEDAOBgNVBAgTB0FyaXpvbmExEzARBgNVBAcTClNjb3R0c2RhbGUxGjAY
-BgNVBAoTEUdvRGFkZHkuY29tLCBJbmMuMTMwMQYDVQQLEypodHRwOi8vY2VydGlm
-aWNhdGVzLmdvZGFkZHkuY29tL3JlcG9zaXRvcnkxMDAuBgNVBAMTJ0dvIERhZGR5
-IFNlY3VyZSBDZXJ0aWZpY2F0aW9uIEF1dGhvcml0eTERMA8GA1UEBRMIMDc5Njky
-ODcwHhcNMTIwMjE1MjEwOTA2WhcNMTQwMjE1MjEwOTA2WjCBjDELMAkGA1UEBgwC
-VVMxCzAJBgNVBAgMAlRYMQ8wDQYDVQQHDAZBdXN0aW4xIzAhBgNVBAoMGkNMRUFS
-RVNVTFQgQ09OU1VMVElORyBJTkMuMRUwEwYDVQQLDAxDb3Jwb3JhdGUgSVQxIzAh
-BgNVBAMMGkNMRUFSRVNVTFQgQ09OU1VMVElORyBJTkMuMIIBIjANBgkqhkiG9w0B
-AQEFAAOCAQ8AMIIBCgKCAQEAtIOjCKeAicull+7ZIzt0/4ya3IeXUFlfypqKMLkU
-IbKjn0P5uMj6VE3rlbZr44RCegxvdnR6umBh1c0ZXoN3o+yc0JKcKcLiApmJJ277
-p7IbLwYDhBXRQNoIJm187IOMRPIxsKN4hL91txn9jGBmW+9zKlJlNhR5R7vjwU2E
-jrH/6oqsc9EM2yYpfjlNv6+3jSwAYZCkSWr+27PQOV+YHKmIxtJjX0upFz5FdIrV
-9CCX+L2Kji1THOkSgG4QTbYxmEcHqGViWz8hXLeNXjcbEsPuIiAu3hknxRHfUTE/
-U0Lh0Ug1e3LrJu+WnxM2SmUY4krsZ22c0yWUW9hzWITIjQIDAQABo4IBhzCCAYMw
-DwYDVR0TAQH/BAUwAwEBADATBgNVHSUEDDAKBggrBgEFBQcDAzAOBgNVHQ8BAf8E
-BAMCB4AwMwYDVR0fBCwwKjAooCagJIYiaHR0cDovL2NybC5nb2RhZGR5LmNvbS9n
-ZHM1LTE2LmNybDBTBgNVHSAETDBKMEgGC2CGSAGG/W0BBxcCMDkwNwYIKwYBBQUH
-AgEWK2h0dHA6Ly9jZXJ0aWZpY2F0ZXMuZ29kYWRkeS5jb20vcmVwb3NpdG9yeS8w
-gYAGCCsGAQUFBwEBBHQwcjAkBggrBgEFBQcwAYYYaHR0cDovL29jc3AuZ29kYWRk
-eS5jb20vMEoGCCsGAQUFBzAChj5odHRwOi8vY2VydGlmaWNhdGVzLmdvZGFkZHku
-Y29tL3JlcG9zaXRvcnkvZ2RfaW50ZXJtZWRpYXRlLmNydDAfBgNVHSMEGDAWgBT9
-rGEyk2xF1uLuhV+auud2mWjM5zAdBgNVHQ4EFgQUDtdeKqeN2QkcbEp1HovFieNB
-XiowDQYJKoZIhvcNAQEFBQADggEBAD74Agw5tvi2aBl4/f/s7/VE/BClzDsKMb9K
-v9qpeC45ZA/jelxV11HKbQnVF194gDb7D2H9OsAsRUy8HVKbXEcc/8dKvwOqb+BC
-2i/EmfjLgmCfezNFtLq8xcPxF3zIRc44vPrK0z4YZsaHdH+yTEJ51p5EMdTqaLaP
-4n5m8LX3RfqlQB9dYFe6dUoYZjKm9d/pIRww3VqfOzjl42Edi1w6dWmBVMx1NZuR
-DBabJH1vJ9Gd+KwxMCmBZ6pQPl28JDimhJhI2LNqU349uADQVV0HJosddN/ARyyI
-LSIQO7BnNVKVG9Iujf33bvPNeg0qNz5qw+rKKq97Pqeum+L5oKU=
------END CERTIFICATE-----
-
-// Subject: CN=eDellRoot
-// Issuer: CN=eDellRoot
-// Serial Number:
-// 6b:c5:7b:95:18:93:aa:97:4b:62:4a:c0:88:fc:3b:b6
------BEGIN CERTIFICATE-----
-MIIC8zCCAd+gAwIBAgIQa8V7lRiTqpdLYkrAiPw7tjAJBgUrDgMCHQUAMBQxEjAQ
-BgNVBAMTCWVEZWxsUm9vdDAeFw0xNTA0MDcxMDIzMjdaFw0zOTEyMzEyMzU5NTla
-MBQxEjAQBgNVBAMTCWVEZWxsUm9vdDCCASIwDQYJKoZIhvcNAQEBBQADggEPADCC
-AQoCggEBAL3RJg1uzVuEX0Hw4XWGzs6oI9W+o7HZdVdBMMVb4Gzb4uZjCTNjbPx4
-b8LNFL1uArUt+5VVMQDsOTY3Lg/Xe/UNukY2b+0llUOzzBYYpbsFcco4n6SsTvDh
-Ni5t+kPo7c23ZrYBPmOu82eEJ6cavs/t39u+wFOkXXwvRCiHA/lWyNWNEPh17+bC
-EP3q5N+JrV+6Ho3zQPEv5QUJYdmXsMmD2CMQojeQUj68J91P5w5BKjurG0xjivzh
-Soie9ym7VRwLFjWScRuw/9XV6CLqTyL5xrqiiDp1uTOuqNj3uxyts9ocbsoJXuxj
-5iEYkSM1nvLupEv+lgy9WqzIEFMm1l8CAwEAAaNJMEcwRQYDVR0BBD4wPIAQYA/f
-EzPwmaRcZuSaa/VZ1KEWMBQxEjAQBgNVBAMTCWVEZWxsUm9vdIIQa8V7lRiTqpdL
-YkrAiPw7tjAJBgUrDgMCHQUAA4IBAQArfdcScsezj8ooJ92UwwnPgg36noOgiUs5
-XzPLP4h0JpUYQVKB9hY1WTDwRUfTKGh7oNOowd027a/rVSb/TNeoiJIvMKn4gbvV
-CWAiHhO8u2u0RkHCDVsa7e0i4ncpueWsihjn6jBrY8T+7eDYwiFT/F03A8NJ7mK5
-lZA8SFd5CTDy3EBUU5UwzXUc5HoIRUxXSPycu3aIBWawg3sCdKiAoikScPAWj0bM
-0vmsP/8QSlTOBqO+QFQ6R82BtTvBNU3qbVICV4QObsxib++FAFL56NApPqskg7Vz
-LfNIAjKabHUcjbuZkmg6jr4BfYW7+oQDHCsYgADjjKGdKz/8U/fP
------END CERTIFICATE-----
diff -Nru openjdk-lts-11.0.11+9/make/data/blockedcertsconverter/blocked.certs.pem openjdk-lts-11.0.14+9/make/data/blockedcertsconverter/blocked.certs.pem
--- openjdk-lts-11.0.11+9/make/data/blockedcertsconverter/blocked.certs.pem 1970-01-01 00:00:00.000000000 +0000
+++ openjdk-lts-11.0.14+9/make/data/blockedcertsconverter/blocked.certs.pem 2022-01-13 21:56:25.000000000 +0000
@@ -0,0 +1,749 @@
+#! java BlockedCertsConverter SHA-256
+
+# The line above must be the first line of this file. Do not
+# remove it.
+
+// Subject: CN=Digisign Server ID (Enrich),
+// OU=457608-K,
+// O=Digicert Sdn. Bhd.,
+// C=MY
+// Issuer: CN=GTE CyberTrust Global Root,
+// OU=GTE CyberTrust Solutions, Inc.,
+// O=GTE Corporation,
+// C=US
+// Serial: 120001705 (07:27:14:a9)
+-----BEGIN CERTIFICATE-----
+MIIDyzCCAzSgAwIBAgIEBycUqTANBgkqhkiG9w0BAQUFADB1MQswCQYDVQQGEwJV
+UzEYMBYGA1UEChMPR1RFIENvcnBvcmF0aW9uMScwJQYDVQQLEx5HVEUgQ3liZXJU
+cnVzdCBTb2x1dGlvbnMsIEluYy4xIzAhBgNVBAMTGkdURSBDeWJlclRydXN0IEds
+b2JhbCBSb290MB4XDTA3MDcxNzE1MTc0OFoXDTEyMDcxNzE1MTY1NFowYzELMAkG
+A1UEBhMCTVkxGzAZBgNVBAoTEkRpZ2ljZXJ0IFNkbi4gQmhkLjERMA8GA1UECxMI
+NDU3NjA4LUsxJDAiBgNVBAMTG0RpZ2lzaWduIFNlcnZlciBJRCAoRW5yaWNoKTCB
+nzANBgkqhkiG9w0BAQEFAAOBjQAwgYkCgYEArahkS02Hx4RZufuQRqCmicDx/tXa
+VII3DZkrRSYK6Fawf8qo9I5HhAGCKeOzarWR8/uVhbxyqGToCkCcxfRxrnt7agfq
+kBRPjYmvlKuyBtQCanuYH1m5Os1U+iDfsioK6bjdaZDAKdNO0JftZszFGUkGf/pe
+LHx7hRsyQt97lSUCAwEAAaOCAXgwggF0MBIGA1UdEwEB/wQIMAYBAf8CAQAwXAYD
+VR0gBFUwUzBIBgkrBgEEAbE+AQAwOzA5BggrBgEFBQcCARYtaHR0cDovL2N5YmVy
+dHJ1c3Qub21uaXJvb3QuY29tL3JlcG9zaXRvcnkuY2ZtMAcGBWCDSgEBMA4GA1Ud
+DwEB/wQEAwIB5jCBiQYDVR0jBIGBMH+heaR3MHUxCzAJBgNVBAYTAlVTMRgwFgYD
+VQQKEw9HVEUgQ29ycG9yYXRpb24xJzAlBgNVBAsTHkdURSBDeWJlclRydXN0IFNv
+bHV0aW9ucywgSW5jLjEjMCEGA1UEAxMaR1RFIEN5YmVyVHJ1c3QgR2xvYmFsIFJv
+b3SCAgGlMEUGA1UdHwQ+MDwwOqA4oDaGNGh0dHA6Ly93d3cucHVibGljLXRydXN0
+LmNvbS9jZ2ktYmluL0NSTC8yMDE4L2NkcC5jcmwwHQYDVR0OBBYEFMYWk04WF+wW
+royUdvOGbcV0boR3MA0GCSqGSIb3DQEBBQUAA4GBAHYAe6Z4K2Ydjl42xqSOBfIj
+knyTZ9P0wAp9iy3Z6tVvGvPhSilaIoRNUC9LDPL/hcJ7VdREgr5trGeOvLQfkpxR
+gBoU9m6rYYgLrRx/90tQUdZlG6ZHcRVesHHzNRTyN71jyNXwk1o0X9g96F33xR7A
+5c8fhiSpPAdmzcHSNmNZ
+-----END CERTIFICATE-----
+
+// Subject: CN=Digisign Server ID - (Enrich),
+// OU=457608-K,
+// O=Digicert Sdn. Bhd.,
+// C=MY
+// Issuer: CN=Entrust.net Certification Authority (2048)
+// OU=(c) 1999 Entrust.net Limited,
+// OU=www.entrust.net/CPS_2048 incorp. by ref. (limits liab.),
+// O=Entrust.net
+// Serial: 1184644297 (4c:0e:63:6a)
+-----BEGIN CERTIFICATE-----
+MIIEzjCCA7agAwIBAgIETA5jajANBgkqhkiG9w0BAQUFADCBtDEUMBIGA1UEChML
+RW50cnVzdC5uZXQxQDA+BgNVBAsUN3d3dy5lbnRydXN0Lm5ldC9DUFNfMjA0OCBp
+bmNvcnAuIGJ5IHJlZi4gKGxpbWl0cyBsaWFiLikxJTAjBgNVBAsTHChjKSAxOTk5
+IEVudHJ1c3QubmV0IExpbWl0ZWQxMzAxBgNVBAMTKkVudHJ1c3QubmV0IENlcnRp
+ZmljYXRpb24gQXV0aG9yaXR5ICgyMDQ4KTAeFw0xMDA3MTYxNzIzMzdaFw0xNTA3
+MTYxNzUzMzdaMGUxCzAJBgNVBAYTAk1ZMRswGQYDVQQKExJEaWdpY2VydCBTZG4u
+IEJoZC4xETAPBgNVBAsTCDQ1NzYwOC1LMSYwJAYDVQQDEx1EaWdpc2lnbiBTZXJ2
+ZXIgSUQgLSAoRW5yaWNoKTCCASIwDQYJKoZIhvcNAQEBBQADggEPADCCAQoCggEB
+AMWJ5PQNBkCSWccaszXRDkwqM/n4r8qef+65p21g9FTob9Wb8xtjMQRoctE0Foy0
+FyyX3nPF2JAVoBor9cuzSIZE8B2ITM5BQhrv9Qze/kDaOSD3BlU6ap1GwdJvpbLI
+Vz4po5zg6YV3ZuiYpyR+vsBZIOVEb7ZX2L7OwmV3WMZhQdF0BMh/SULFcqlyFu6M
+3RJdtErU0a9Qt9iqdXZorT5dqjBtYairEFs+E78z4K9EnTgiW+9ML6ZxJhUmyiiM
+2fqOjqmiFDXimySItPR/hZ2DTwehthSQNsQ0HI0mYW0Tb3i+6I8nx0uElqOGaAwj
+vgvsjJQAqQSKE5D334VsDLECAwEAAaOCATQwggEwMA4GA1UdDwEB/wQEAwIBBjAS
+BgNVHRMBAf8ECDAGAQH/AgEAMCcGA1UdJQQgMB4GCCsGAQUFBwMBBggrBgEFBQcD
+AgYIKwYBBQUHAwQwMwYIKwYBBQUHAQEEJzAlMCMGCCsGAQUFBzABhhdodHRwOi8v
+b2NzcC5lbnRydXN0Lm5ldDBEBgNVHSAEPTA7MDkGBWCDSgEBMDAwLgYIKwYBBQUH
+AgEWImh0dHA6Ly93d3cuZGlnaWNlcnQuY29tLm15L2Nwcy5odG0wMgYDVR0fBCsw
+KTAnoCWgI4YhaHR0cDovL2NybC5lbnRydXN0Lm5ldC8yMDQ4Y2EuY3JsMBEGA1Ud
+DgQKBAhMTswlKAMpgTAfBgNVHSMEGDAWgBRV5IHREYC+2Im5CKMx+aEkCRa5cDAN
+BgkqhkiG9w0BAQUFAAOCAQEAl0zvSjpJrHL8MCBrtClbp8WVBJD5MtXChWreA6E3
++YkAsFqsVX7bQzX/yQH4Ub7MJsrIaqTEVD4mHucMo82XZ5TdpkLrXM2POXlrM3kh
+Bnn6gkQVmczBtznTRmJ8snDrb84gqj4Zt+l0gpy0pUtNYQA35IfS8hQ6ZHy4qXth
+4JMi59WfPkfmNnagU9gAAzoPtTP+lsrT0oI6Lt3XSOHkp2nMHOmZSufKcEXXCwcO
+mnUb0C+Sb/akB8O9HEumhLZ9qJqp0qcp8QtXaR6XVybsK0Os1EWDBQDp4/BGQAf6
+6rFRc5Mcpd1TETfIKqcVJx20qsx/qjEw/LhFn0gJ7RDixQ==
+-----END CERTIFICATE-----
+
+// Subject: CN=Java Media APIs,
+// OU=Java Signed Extensions,
+// OU=Corporate Object Signing,
+// O=Sun Microsystems Inc
+// Issuer: CN=Object Signing CA,
+// OU=Class 2 OnSite Subscriber CA,
+// OU=VeriSign Trust Network,
+// O=Sun Microsystems Inc
+// Serial: 6a:8b:99:91:37:59:4f:89:53:e2:97:18:9f:19:1e:4e
+-----BEGIN CERTIFICATE-----
+MIIFdzCCBF+gAwIBAgIQaouZkTdZT4lT4pcYnxkeTjANBgkqhkiG9w0BAQUFADCB
+gzEdMBsGA1UEChMUU3VuIE1pY3Jvc3lzdGVtcyBJbmMxHzAdBgNVBAsTFlZlcmlT
+aWduIFRydXN0IE5ldHdvcmsxJTAjBgNVBAsTHENsYXNzIDIgT25TaXRlIFN1YnNj
+cmliZXIgQ0ExGjAYBgNVBAMTEU9iamVjdCBTaWduaW5nIENBMB4XDTA5MDUxMjAw
+MDAwMFoXDTEyMDUxMTIzNTk1OVowfTEdMBsGA1UEChQUU3VuIE1pY3Jvc3lzdGVt
+cyBJbmMxITAfBgNVBAsUGENvcnBvcmF0ZSBPYmplY3QgU2lnbmluZzEfMB0GA1UE
+CxQWSmF2YSBTaWduZWQgRXh0ZW5zaW9uczEYMBYGA1UEAxQPSmF2YSBNZWRpYSBB
+UElzMIIBIjANBgkqhkiG9w0BAQEFAAOCAQ8AMIIBCgKCAQEAl5blzoKTVE8y4Hpz
+q6E15RZz1bF5HnYEyYqgHkZXnAKedmYCoMzm1XK8s+gQWShLEvGEAvs5yqarx9gE
+nnC21N28aEZgIJMa2/arKxCUkS4pxdGPYGexL9UzSRkUpoBShCZKEGdmX7gfJE2K
+/sd9MFvGV5/yZtWXrADzvm0Kd/9mg1KRv1gfrZIq0TJbupoXPYYqb73AkI9eT2ZD
+q9MdwD4E5+oojsDFXt8GU/D00fUhtXpYwuplU7D667WHYdJhIah0ST6JywyqcLXG
+XSuFTXOgITT2idSHluZVmx3dqJ72u9kPkO4JdJTMDfaK8zgNLaRkiU8Qcj+qhLYH
+ytaqcwIDAQABo4IB6jCCAeYwCQYDVR0TBAIwADAOBgNVHQ8BAf8EBAMCB4AwfwYD
+VR0fBHgwdjB0oHKgcIZuaHR0cDovL29uc2l0ZWNybC52ZXJpc2lnbi5jb20vU3Vu
+TWljcm9zeXN0ZW1zSW5jQ29ycG9yYXRlT2JqZWN0U2lnbmluZ0phdmFTaWduZWRF
+eHRlbnNpb25zQ2xhc3NCL0xhdGVzdENSTC5jcmwwHwYDVR0jBBgwFoAUs0crgn5T
+tHPKuLsZt76BTQeVx+0wHQYDVR0OBBYEFKS32mVx0gNWTeS4ProHEaeSpvvIMDsG
+CCsGAQUFBwEBBC8wLTArBggrBgEFBQcwAYYfaHR0cDovL29uc2l0ZS1vY3NwLnZl
+cmlzaWduLmNvbTCBtQYDVR0gBIGtMIGqMDkGC2CGSAGG+EUBBxcCMCowKAYIKwYB
+BQUHAgEWHGh0dHBzOi8vd3d3LnZlcmlzaWduLmNvbS9ycGEwbQYLYIZIAYb3AIN9
+nD8wXjAnBggrBgEFBQcCARYbaHR0cHM6Ly93d3cuc3VuLmNvbS9wa2kvY3BzMDMG
+CCsGAQUFBwICMCcaJVZhbGlkYXRlZCBGb3IgU3VuIEJ1c2luZXNzIE9wZXJhdGlv
+bnMwEwYDVR0lBAwwCgYIKwYBBQUHAwMwDQYJKoZIhvcNAQEFBQADggEBAAe6BO4W
+3TSNWfezyelJs6kE3HfulT6Bdyz4UUoh9ykXcV8nRwT+kh25I5MdyG2GfkJoADPR
+VhC5DYo13UFpIsTNVjq+hGYe2hML93bN7ad9SxCCyjHUo3yMz2qgBbHZI3VA9ZHA
+aWM4Tx0saMwbcnVvlbuGh+PXvStfypJqYT6lzcdFfjNVX4FI/QQNGhBswMY51tC8
+GTBCL2qhJon0gSCU4zaawDOf7+XxJWirLamYL1Aal1/h2z2sFrvA/1ftxtU3kZ6I
+7De8DyoHeZg7pYGdrj7g+lPhCga/WvEhN152I+aP08YbFcJHYmK05ngl/Ye4c6Bd
+cdrdfbw6QzEUIYY=
+-----END CERTIFICATE-----
+
+// Subject: CN=JavaFX 1.0 Runtime,
+// OU=Java Signed Extensions,
+// OU=Corporate Object Signing,
+// O=Sun Microsystems Inc
+// Issuer: CN=Object Signing CA,
+// OU=Class 2 OnSite Subscriber CA,
+// OU=VeriSign Trust Network,
+// O=Sun Microsystems Inc
+// Serial: 55:c0:e6:44:59:59:79:9e:d9:26:f1:b0:4a:1e:f0:27
+-----BEGIN CERTIFICATE-----
+MIIFezCCBGOgAwIBAgIQVcDmRFlZeZ7ZJvGwSh7wJzANBgkqhkiG9w0BAQUFADCB
+gzEdMBsGA1UEChMUU3VuIE1pY3Jvc3lzdGVtcyBJbmMxHzAdBgNVBAsTFlZlcmlT
+aWduIFRydXN0IE5ldHdvcmsxJTAjBgNVBAsTHENsYXNzIDIgT25TaXRlIFN1YnNj
+cmliZXIgQ0ExGjAYBgNVBAMTEU9iamVjdCBTaWduaW5nIENBMB4XDTA4MTAwOTAw
+MDAwMFoXDTExMTAwOTIzNTk1OVowgYAxHTAbBgNVBAoUFFN1biBNaWNyb3N5c3Rl
+bXMgSW5jMSEwHwYDVQQLFBhDb3Jwb3JhdGUgT2JqZWN0IFNpZ25pbmcxHzAdBgNV
+BAsUFkphdmEgU2lnbmVkIEV4dGVuc2lvbnMxGzAZBgNVBAMUEkphdmFGWCAxLjAg
+UnVudGltZTCCASIwDQYJKoZIhvcNAQEBBQADggEPADCCAQoCggEBAM+WDc6+bu+4
+tmAcS/lBtUc02WOt9QZpVsXg9cG2pu/8bUtmDELa8iiYBVFpIs8DU58HLrGQtCUY
+SIAGOVPsOJoN29UKCDWfY9j5JeVhfhMGqk9DwrWhzgsjy4cpZ1pIp+k/fJ8zT8Ul
+aYLpow1vg3UNddsmwz02tN7cOrMw9WYIG4CRYnY1OrtJSfe2pYzheC4zyvR+aiVl
+nang2OtqikSQsNFOFHsLOJFxngy9LrO8evDSu25VTKI6zlWU6/bMeqtztJPN0VOn
+NyUrJZvkxZ207Jg0T693BGSxNC1n+ihztXogql8950M/pEuUbDjylv5FFvlp6DSB
+dDT2MkutmyMCAwEAAaOCAeowggHmMAkGA1UdEwQCMAAwDgYDVR0PAQH/BAQDAgeA
+MH8GA1UdHwR4MHYwdKByoHCGbmh0dHA6Ly9vbnNpdGVjcmwudmVyaXNpZ24uY29t
+L1N1bk1pY3Jvc3lzdGVtc0luY0NvcnBvcmF0ZU9iamVjdFNpZ25pbmdKYXZhU2ln
+bmVkRXh0ZW5zaW9uc0NsYXNzQi9MYXRlc3RDUkwuY3JsMB8GA1UdIwQYMBaAFLNH
+K4J+U7Rzyri7Gbe+gU0HlcftMB0GA1UdDgQWBBTjgufVi3XJ3gx1ewsA6Rr7BR4Z
+zjA7BggrBgEFBQcBAQQvMC0wKwYIKwYBBQUHMAGGH2h0dHA6Ly9vbnNpdGUtb2Nz
+cC52ZXJpc2lnbi5jb20wgbUGA1UdIASBrTCBqjA5BgtghkgBhvhFAQcXAjAqMCgG
+CCsGAQUFBwIBFhxodHRwczovL3d3dy52ZXJpc2lnbi5jb20vcnBhMG0GC2CGSAGG
+9wCDfZw/MF4wJwYIKwYBBQUHAgEWG2h0dHBzOi8vd3d3LnN1bi5jb20vcGtpL2Nw
+czAzBggrBgEFBQcCAjAnGiVWYWxpZGF0ZWQgRm9yIFN1biBCdXNpbmVzcyBPcGVy
+YXRpb25zMBMGA1UdJQQMMAoGCCsGAQUFBwMDMA0GCSqGSIb3DQEBBQUAA4IBAQAB
+YVJTTVe7rzyTO4jc3zajErOT/COkdQTfNo0eIX1QbNynFieJvwY/jRzUZwjktIFR
+2p4JtbpHGAtKtjOAOTieQ8xdDOoC1djzpE7/AbMvuvlTavtUKT+F7tPdhfXgWXJV
+6Wbt8jryKyk3zZGiEhauIwZUkfjRkEtffEmZWLUd8c8rURJjfC/XHH2oyurscoxc
+CjX29c9ynxSiS/VvQp1an0HvErGh69N48wj7cj8mtZ1yHzd2XCzSSR1OfTPfk0Pt
+yg51p7yJaFiH21PTZegEL6zyVNOYBTKwwIi2OzpwYalD3uvK6e3OKDrfFCOxu17u
+4PveESbrdyrmvLe7IVez
+-----END CERTIFICATE-----
+
+// Subject: CN=JavaFX Runtime,
+// OU=Java Signed Extensions,
+// OU=Corporate Object Signing,
+// O=Sun Microsystems Inc
+// Issuer: CN=Object Signing CA,
+// OU=Class 2 OnSite Subscriber CA,
+// OU=VeriSign Trust Network,
+// O=Sun Microsystems Inc
+// Serial: 47:f4:55:f1:da:4a:5e:f9:e3:f7:a8:03:62:17:c0:ff
+-----BEGIN CERTIFICATE-----
+MIIFdjCCBF6gAwIBAgIQR/RV8dpKXvnj96gDYhfA/zANBgkqhkiG9w0BAQUFADCB
+gzEdMBsGA1UEChMUU3VuIE1pY3Jvc3lzdGVtcyBJbmMxHzAdBgNVBAsTFlZlcmlT
+aWduIFRydXN0IE5ldHdvcmsxJTAjBgNVBAsTHENsYXNzIDIgT25TaXRlIFN1YnNj
+cmliZXIgQ0ExGjAYBgNVBAMTEU9iamVjdCBTaWduaW5nIENBMB4XDTA5MDEyOTAw
+MDAwMFoXDTEyMDEyOTIzNTk1OVowfDEdMBsGA1UEChQUU3VuIE1pY3Jvc3lzdGVt
+cyBJbmMxITAfBgNVBAsUGENvcnBvcmF0ZSBPYmplY3QgU2lnbmluZzEfMB0GA1UE
+CxQWSmF2YSBTaWduZWQgRXh0ZW5zaW9uczEXMBUGA1UEAxQOSmF2YUZYIFJ1bnRp
+bWUwggEiMA0GCSqGSIb3DQEBAQUAA4IBDwAwggEKAoIBAQCIzd0fAk8mI9ONc6RJ
+aGieioK2FLdXEwj8zL3vdGDVmBwyR1zwYkaOIFFgF9IW/8qc4iAYA5sGUY+0g8q3
+5DuYAxfTzBB5KdaYvbuq6GGnoHIWmTirXY+1friFp8lyXSvtuEaGB1VHaBoZchEg
+k+UgeVDA43dHwcT1Ov3DePczJRUes8T/QHzLX+BxUDG43vjyncCEO/AjqLZxXEz2
+xrNbKLcH3lGMJK7hdbfssUfF5BjC38Hn71HauYlA43b2no+2y0Sjulwzez2YPbDC
+0GLR3TnKtA8dqOrnl5t3DniDbfOBNtBE3VOydJO0XW57Ng1HRXD023nm9ECPY2xp
+0N/pAgMBAAGjggHqMIIB5jAJBgNVHRMEAjAAMA4GA1UdDwEB/wQEAwIHgDB/BgNV
+HR8EeDB2MHSgcqBwhm5odHRwOi8vb25zaXRlY3JsLnZlcmlzaWduLmNvbS9TdW5N
+aWNyb3N5c3RlbXNJbmNDb3Jwb3JhdGVPYmplY3RTaWduaW5nSmF2YVNpZ25lZEV4
+dGVuc2lvbnNDbGFzc0IvTGF0ZXN0Q1JMLmNybDAfBgNVHSMEGDAWgBSzRyuCflO0
+c8q4uxm3voFNB5XH7TAdBgNVHQ4EFgQUvOdd0cKPj+Yik/iOBwTdphh5A+gwOwYI
+KwYBBQUHAQEELzAtMCsGCCsGAQUFBzABhh9odHRwOi8vb25zaXRlLW9jc3AudmVy
+aXNpZ24uY29tMIG1BgNVHSAEga0wgaowOQYLYIZIAYb4RQEHFwIwKjAoBggrBgEF
+BQcCARYcaHR0cHM6Ly93d3cudmVyaXNpZ24uY29tL3JwYTBtBgtghkgBhvcAg32c
+PzBeMCcGCCsGAQUFBwIBFhtodHRwczovL3d3dy5zdW4uY29tL3BraS9jcHMwMwYI
+KwYBBQUHAgIwJxolVmFsaWRhdGVkIEZvciBTdW4gQnVzaW5lc3MgT3BlcmF0aW9u
+czATBgNVHSUEDDAKBggrBgEFBQcDAzANBgkqhkiG9w0BAQUFAAOCAQEAbGcf2NjL
+AI93HG6ny2BbepaZA1a8xa/R6uUc7xV+Qw6MgLwFD4Q4i6LWUztQDvg9l68MM2/i
+Y9LEi1KM4lcNbK5+D+t9x98wXBiuojXhVdp5ZmC03EyEBbriopdBsmXVLDSu/Y3+
+zowOO5xwpMK3dbgsSDs2Vt0UosD3FTcRaD3GNfOhXMp+o1grHNiXF9YgkmdQbPPZ
+DQ2KBhFPCRJXBGvyKOqno/DTg0sQ3crGH/C4/4t7mnQXWldZotmJUZ0ONc9oD+Q1
+JAaguUKqIwn9yZ093ie+JWHbYNid9IIIPXYgtRxmf9a376WBhqhu56uJftBJ7x9g
+eQ7Lot6CSWCiFw==
+-----END CERTIFICATE-----
+
+// Subject: CN=Solaris INTERNAL DEVELOPMENT USE ONLY,
+// OU=Solaris Cryptographic Framework,
+// OU=Corporate Object Signing,
+// O=Sun Microsystems Inc
+// Issuer: CN=Object Signing CA,
+// OU=Class 2 OnSite Subscriber CA,
+// OU=VeriSign Trust Network,
+// O=Sun Microsystems Inc
+// Serial: 77:29:77:52:6a:19:7b:9a:a6:a2:c7:99:a0:e1:cd:8c
+-----BEGIN CERTIFICATE-----
+MIIFHjCCBAagAwIBAgIQdyl3UmoZe5qmoseZoOHNjDANBgkqhkiG9w0BAQUFADCB
+gzEdMBsGA1UEChMUU3VuIE1pY3Jvc3lzdGVtcyBJbmMxHzAdBgNVBAsTFlZlcmlT
+aWduIFRydXN0IE5ldHdvcmsxJTAjBgNVBAsTHENsYXNzIDIgT25TaXRlIFN1YnNj
+cmliZXIgQ0ExGjAYBgNVBAMTEU9iamVjdCBTaWduaW5nIENBMB4XDTA3MDEwNDAw
+MDAwMFoXDTEwMDEwMzIzNTk1OVowgZwxHTAbBgNVBAoUFFN1biBNaWNyb3N5c3Rl
+bXMgSW5jMSEwHwYDVQQLFBhDb3Jwb3JhdGUgT2JqZWN0IFNpZ25pbmcxKDAmBgNV
+BAsUH1NvbGFyaXMgQ3J5cHRvZ3JhcGhpYyBGcmFtZXdvcmsxLjAsBgNVBAMUJVNv
+bGFyaXMgSU5URVJOQUwgREVWRUxPUE1FTlQgVVNFIE9OTFkwgZ8wDQYJKoZIhvcN
+AQEBBQADgY0AMIGJAoGBALbNU4hf3mD5ArDI9pjgioAyvV3bjMPRQdCZniIeGJBp
+odFlSEH+Mh64W1DsY8coeZ7FvvGJkx9IpTMJW9k8w1oJK9UNqHyAQfaYjQyXi3xQ
+LJp62EvYdGfDlwOZejEcR/MbzZG+GOPMMvQj5+xyFDvLXNGfQNTnxw2qnBgCJXjj
+AgMBAAGjggH1MIIB8TAJBgNVHRMEAjAAMA4GA1UdDwEB/wQEAwIHgDCBiQYDVR0f
+BIGBMH8wfaB7oHmGd2h0dHA6Ly9vbnNpdGVjcmwudmVyaXNpZ24uY29tL1N1bk1p
+Y3Jvc3lzdGVtc0luY0NvcnBvcmF0ZU9iamVjdFNpZ25pbmdTb2xhcmlzQ3J5cHRv
+Z3JhcGhpY0ZyYW1ld29ya0NsYXNzQi9MYXRlc3RDUkwuY3JsMB8GA1UdIwQYMBaA
+FLNHK4J+U7Rzyri7Gbe+gU0HlcftMB0GA1UdDgQWBBRpfiGYkehTnsIzuN2H6AFb
+VCZG8jA7BggrBgEFBQcBAQQvMC0wKwYIKwYBBQUHMAGGH2h0dHA6Ly9vbnNpdGUt
+b2NzcC52ZXJpc2lnbi5jb20wgbUGA1UdIASBrTCBqjA5BgtghkgBhvhFAQcXAjAq
+MCgGCCsGAQUFBwIBFhxodHRwczovL3d3dy52ZXJpc2lnbi5jb20vcnBhMG0GC2CG
+SAGG9wCDfZw/MF4wJwYIKwYBBQUHAgEWG2h0dHBzOi8vd3d3LnN1bi5jb20vcGtp
+L2NwczAzBggrBgEFBQcCAjAnFiVWYWxpZGF0ZWQgRm9yIFN1biBCdXNpbmVzcyBP
+cGVyYXRpb25zMBMGA1UdJQQMMAoGCCsGAQUFBwMDMA0GCSqGSIb3DQEBBQUAA4IB
+AQCG5soy3LFHTFbA8/5SzDRhQoJkHUnOP0t3b6nvX6vZYRp649fje7TQOPRm1pFd
+CZ17J+tggdZwgzTqY4aYpJ00jZaK6pV37q/vgFC/ia6jDs8Q+ly9cEcadBZ5loYg
+cmxp9p57W2MNWx8VA8oFdNtKfF0jUNXbLNtvwGHmgR6YcwLrGN1b6/9Lt9bO3ODl
+FO+ZDwkfQz5ClUVrTx2dGBvKRYFqSG5S8JAfsgYhPvcacUQkA7ExyKvfRXLWVrce
+ZiPpcElbx+819H2sAPvVvparVeAruZGMAtejHZp9NFoowKen5drJp9VxePS4eM49
+3DepB6lKRrNRw66LNQol4ZBz
+-----END CERTIFICATE-----
+
+// Subject: EMAILADDRESS=info@diginotar.nl, CN=DigiNotar Cyber CA,
+// O=DigiNotar, C=NL
+// Issuer: CN=GTE CyberTrust Global Root,
+// OU=GTE CyberTrust Solutions, Inc.,
+// O=GTE Corporation,
+// C=US
+// Serial: 120000525 (07:27:10:0D)
+-----BEGIN CERTIFICATE-----
+MIIFWjCCBMOgAwIBAgIEBycQDTANBgkqhkiG9w0BAQUFADB1MQswCQYDVQQGEwJV
+UzEYMBYGA1UEChMPR1RFIENvcnBvcmF0aW9uMScwJQYDVQQLEx5HVEUgQ3liZXJU
+cnVzdCBTb2x1dGlvbnMsIEluYy4xIzAhBgNVBAMTGkdURSBDeWJlclRydXN0IEds
+b2JhbCBSb290MB4XDTA2MTAwNDEwNTQxMVoXDTExMTAwNDEwNTMxMVowYDELMAkG
+A1UEBhMCTkwxEjAQBgNVBAoTCURpZ2lOb3RhcjEbMBkGA1UEAxMSRGlnaU5vdGFy
+IEN5YmVyIENBMSAwHgYJKoZIhvcNAQkBFhFpbmZvQGRpZ2lub3Rhci5ubDCCAiIw
+DQYJKoZIhvcNAQEBBQADggIPADCCAgoCggIBANLOFQotqF6EZ639vu9Gx8i5z3P8
+9DS5+SxD52ATPXrjss87Z2yQrcC5P4RS8DVC3HTcKDu9UrSnrHJFF8bwieu0qiXy
+XUte0dmHutZ9fPXOMp8QM8WxSrtekTHC0OlBwpFkfglBO9uLCDdqqspS3rU5HsCI
+A6U/i5kTYUO1m4Kz7iBvz6FEouova0CfjytXraFTwoUiaZ2gP1HfC0GRDaXhqKpc
+SQhdvd5wQbEPyWNr0380dAIvNFp4dRxoeoFnivPaQPBgY/SSINcDpj2jHmfEhBtB
+pcmM5r3qSLYFFgizNxJa92E89zhvLpfgb1Y4VNMota0Ubi5LZLUnZbd1JQm2Bz2V
+VgIKgmCyc0XgMyZRdJq51FAc9k1bW1JSE1qmf6cO4ehBVGeYjIfVydNsy9NUkgYJ
+NEH3gW8/nsl8dVWw58Gzd+jDxAA1lUBwEEoF3iW7n1mlZLxHYL9g43aLE1Xd4XR6
+uc8kpmp/3mQiRFhogmoQ+T3lPhu5vfwi9GAEibtVbShV+t6OjRshFNc3izR7Tfay
+shDPM7F9HGKZSMsrbHaWVb8ZDR0fu2WqG46ZtcYokOWCLXhQIJr9eS8kf/CJKWn0
+fc1zvrPtTsHR7VJej/e4142HrbLZG1ES/1az4a80fVykeIgQnp0DxqWqoiRR90kU
+xbHuWUOV36toKDA/AgMBAAGjggGGMIIBgjASBgNVHRMBAf8ECDAGAQH/AgEBMFMG
+A1UdIARMMEowSAYJKwYBBAGxPgEAMDswOQYIKwYBBQUHAgEWLWh0dHA6Ly93d3cu
+cHVibGljLXRydXN0LmNvbS9DUFMvT21uaVJvb3QuaHRtbDAOBgNVHQ8BAf8EBAMC
+AQYwgaAGA1UdIwSBmDCBlYAUpgwdn2H/Bxe1vzhG20Mw1Y6wUgaheaR3MHUxCzAJ
+BgNVBAYTAlVTMRgwFgYDVQQKEw9HVEUgQ29ycG9yYXRpb24xJzAlBgNVBAsTHkdU
+RSBDeWJlclRydXN0IFNvbHV0aW9ucywgSW5jLjEjMCEGA1UEAxMaR1RFIEN5YmVy
+VHJ1c3QgR2xvYmFsIFJvb3SCAgGlMEUGA1UdHwQ+MDwwOqA4oDaGNGh0dHA6Ly93
+d3cucHVibGljLXRydXN0LmNvbS9jZ2ktYmluL0NSTC8yMDE4L2NkcC5jcmwwHQYD
+VR0OBBYEFKv5aN/PSjfXe0WMX3LeQETDZbvCMA0GCSqGSIb3DQEBBQUAA4GBAI9o
+a6VbB7pEZg4cqFwwezPkCiYE/O+eGjjWLqEf0JlHwnVkJP2eOyh2uSYoYZEMbSz4
+BJ98UAHV42mv7xXSRZskCSpmBU8lgcpdvqrBWSeuM46C9990sFWzjvjnN8huqlZE
+9r1TgSOWPbT6MopTZkQloiXGpjwljPDgKAYityZB
+-----END CERTIFICATE-----
+
+// Subject: CN=DigiNotar Cyber CA, O=DigiNotar, C=NL
+// Issuer: CN=GTE CyberTrust Global Root,
+// OU=GTE CyberTrust Solutions, Inc.,
+// O=GTE Corporation,
+// C=US
+// Serial: 120000505 (07:27:0F:F9)
+-----BEGIN CERTIFICATE-----
+MIIFODCCBKGgAwIBAgIEBycP+TANBgkqhkiG9w0BAQUFADB1MQswCQYDVQQGEwJV
+UzEYMBYGA1UEChMPR1RFIENvcnBvcmF0aW9uMScwJQYDVQQLEx5HVEUgQ3liZXJU
+cnVzdCBTb2x1dGlvbnMsIEluYy4xIzAhBgNVBAMTGkdURSBDeWJlclRydXN0IEds
+b2JhbCBSb290MB4XDTA2MDkyMDA5NDUzMloXDTEzMDkyMDA5NDQwNlowPjELMAkG
+A1UEBhMCTkwxEjAQBgNVBAoTCURpZ2lOb3RhcjEbMBkGA1UEAxMSRGlnaU5vdGFy
+IEN5YmVyIENBMIICIjANBgkqhkiG9w0BAQEFAAOCAg8AMIICCgKCAgEA0s4VCi2o
+XoRnrf2+70bHyLnPc/z0NLn5LEPnYBM9euOyzztnbJCtwLk/hFLwNULcdNwoO71S
+tKesckUXxvCJ67SqJfJdS17R2Ye61n189c4ynxAzxbFKu16RMcLQ6UHCkWR+CUE7
+24sIN2qqylLetTkewIgDpT+LmRNhQ7WbgrPuIG/PoUSi6i9rQJ+PK1etoVPChSJp
+naA/Ud8LQZENpeGoqlxJCF293nBBsQ/JY2vTfzR0Ai80Wnh1HGh6gWeK89pA8GBj
+9JIg1wOmPaMeZ8SEG0GlyYzmvepItgUWCLM3Elr3YTz3OG8ul+BvVjhU0yi1rRRu
+LktktSdlt3UlCbYHPZVWAgqCYLJzReAzJlF0mrnUUBz2TVtbUlITWqZ/pw7h6EFU
+Z5iMh9XJ02zL01SSBgk0QfeBbz+eyXx1VbDnwbN36MPEADWVQHAQSgXeJbufWaVk
+vEdgv2DjdosTVd3hdHq5zySman/eZCJEWGiCahD5PeU+G7m9/CL0YASJu1VtKFX6
+3o6NGyEU1zeLNHtN9rKyEM8zsX0cYplIyytsdpZVvxkNHR+7Zaobjpm1xiiQ5YIt
+eFAgmv15LyR/8IkpafR9zXO+s+1OwdHtUl6P97jXjYetstkbURL/VrPhrzR9XKR4
+iBCenQPGpaqiJFH3SRTFse5ZQ5Xfq2goMD8CAwEAAaOCAYYwggGCMBIGA1UdEwEB
+/wQIMAYBAf8CAQEwUwYDVR0gBEwwSjBIBgkrBgEEAbE+AQAwOzA5BggrBgEFBQcC
+ARYtaHR0cDovL3d3dy5wdWJsaWMtdHJ1c3QuY29tL0NQUy9PbW5pUm9vdC5odG1s
+MA4GA1UdDwEB/wQEAwIBBjCBoAYDVR0jBIGYMIGVgBSmDB2fYf8HF7W/OEbbQzDV
+jrBSBqF5pHcwdTELMAkGA1UEBhMCVVMxGDAWBgNVBAoTD0dURSBDb3Jwb3JhdGlv
+bjEnMCUGA1UECxMeR1RFIEN5YmVyVHJ1c3QgU29sdXRpb25zLCBJbmMuMSMwIQYD
+VQQDExpHVEUgQ3liZXJUcnVzdCBHbG9iYWwgUm9vdIICAaUwRQYDVR0fBD4wPDA6
+oDigNoY0aHR0cDovL3d3dy5wdWJsaWMtdHJ1c3QuY29tL2NnaS1iaW4vQ1JMLzIw
+MTgvY2RwLmNybDAdBgNVHQ4EFgQUq/lo389KN9d7RYxfct5ARMNlu8IwDQYJKoZI
+hvcNAQEFBQADgYEACcpiD427SuDUejUrBi3RKGG2rAH7g0m8rtQvLYauGYOl1h0T
+4he+/jJ06XoUOMqUXvcpAWlxG5Ea/aO7qh3Ke+IW/aGjDvMMX7LhIDGUK16Sdu36
+6bUjpr8KOwOpb1JgVM1f6bcvfKIn/UGDdbYN+3gm87FF6TKVKho1IZXFonU=
+-----END CERTIFICATE-----
+
+// Subject: CN=DigiNotar Cyber CA, O=DigiNotar, C=NL
+// Issuer: CN=GTE CyberTrust Global Root,
+// OU=GTE CyberTrust Solutions, Inc.,
+// O=GTE Corporation,
+// C=US
+// Serial: 120000515 (07:27:10:03)
+-----BEGIN CERTIFICATE-----
+MIIFODCCBKGgAwIBAgIEBycQAzANBgkqhkiG9w0BAQUFADB1MQswCQYDVQQGEwJV
+UzEYMBYGA1UEChMPR1RFIENvcnBvcmF0aW9uMScwJQYDVQQLEx5HVEUgQ3liZXJU
+cnVzdCBTb2x1dGlvbnMsIEluYy4xIzAhBgNVBAMTGkdURSBDeWJlclRydXN0IEds
+b2JhbCBSb290MB4XDTA2MDkyNzEwNTMzMloXDTExMDkyNzEwNTIzMFowPjELMAkG
+A1UEBhMCTkwxEjAQBgNVBAoTCURpZ2lOb3RhcjEbMBkGA1UEAxMSRGlnaU5vdGFy
+IEN5YmVyIENBMIICIjANBgkqhkiG9w0BAQEFAAOCAg8AMIICCgKCAgEA0s4VCi2o
+XoRnrf2+70bHyLnPc/z0NLn5LEPnYBM9euOyzztnbJCtwLk/hFLwNULcdNwoO71S
+tKesckUXxvCJ67SqJfJdS17R2Ye61n189c4ynxAzxbFKu16RMcLQ6UHCkWR+CUE7
+24sIN2qqylLetTkewIgDpT+LmRNhQ7WbgrPuIG/PoUSi6i9rQJ+PK1etoVPChSJp
+naA/Ud8LQZENpeGoqlxJCF293nBBsQ/JY2vTfzR0Ai80Wnh1HGh6gWeK89pA8GBj
+9JIg1wOmPaMeZ8SEG0GlyYzmvepItgUWCLM3Elr3YTz3OG8ul+BvVjhU0yi1rRRu
+LktktSdlt3UlCbYHPZVWAgqCYLJzReAzJlF0mrnUUBz2TVtbUlITWqZ/pw7h6EFU
+Z5iMh9XJ02zL01SSBgk0QfeBbz+eyXx1VbDnwbN36MPEADWVQHAQSgXeJbufWaVk
+vEdgv2DjdosTVd3hdHq5zySman/eZCJEWGiCahD5PeU+G7m9/CL0YASJu1VtKFX6
+3o6NGyEU1zeLNHtN9rKyEM8zsX0cYplIyytsdpZVvxkNHR+7Zaobjpm1xiiQ5YIt
+eFAgmv15LyR/8IkpafR9zXO+s+1OwdHtUl6P97jXjYetstkbURL/VrPhrzR9XKR4
+iBCenQPGpaqiJFH3SRTFse5ZQ5Xfq2goMD8CAwEAAaOCAYYwggGCMBIGA1UdEwEB
+/wQIMAYBAf8CAQEwUwYDVR0gBEwwSjBIBgkrBgEEAbE+AQAwOzA5BggrBgEFBQcC
+ARYtaHR0cDovL3d3dy5wdWJsaWMtdHJ1c3QuY29tL0NQUy9PbW5pUm9vdC5odG1s
+MA4GA1UdDwEB/wQEAwIBBjCBoAYDVR0jBIGYMIGVgBSmDB2fYf8HF7W/OEbbQzDV
+jrBSBqF5pHcwdTELMAkGA1UEBhMCVVMxGDAWBgNVBAoTD0dURSBDb3Jwb3JhdGlv
+bjEnMCUGA1UECxMeR1RFIEN5YmVyVHJ1c3QgU29sdXRpb25zLCBJbmMuMSMwIQYD
+VQQDExpHVEUgQ3liZXJUcnVzdCBHbG9iYWwgUm9vdIICAaUwRQYDVR0fBD4wPDA6
+oDigNoY0aHR0cDovL3d3dy5wdWJsaWMtdHJ1c3QuY29tL2NnaS1iaW4vQ1JMLzIw
+MTgvY2RwLmNybDAdBgNVHQ4EFgQUq/lo389KN9d7RYxfct5ARMNlu8IwDQYJKoZI
+hvcNAQEFBQADgYEAWcyGZhizJlRP1jjNupZey+yZG6oMDW4Z11boriMHbYPCndBE
+bVh07zmPbZsihOw9w/vm5KbVX5CgxUv4Rhzh/20Faixf3P3bpWg0qgzHVVusNVR/
+P50aKkpdK3hp+QLl56e+lWOddSAINIpmcuyDI1hyuzB+GJEASm9tNU/6rs8=
+-----END CERTIFICATE-----
+
+// Subject: EMAILADDRESS=info@diginotar.nl,
+// CN=DigiNotar Root CA,
+// O=DigiNotar, C=NL
+// Issuer: CN=Entrust.net Secure Server Certification Authority
+// OU=(c) 1999 Entrust.net Limited,
+// OU=www.entrust.net/CPS incorp. by ref. (limits liab.),
+// O=Entrust.net,
+// C=US,
+// Serial: 1184644297 (46:9C:3C:C9)
+-----BEGIN CERTIFICATE-----
+MIIFSDCCBLGgAwIBAgIERpw8yTANBgkqhkiG9w0BAQUFADCBwzELMAkGA1UEBhMC
+VVMxFDASBgNVBAoTC0VudHJ1c3QubmV0MTswOQYDVQQLEzJ3d3cuZW50cnVzdC5u
+ZXQvQ1BTIGluY29ycC4gYnkgcmVmLiAobGltaXRzIGxpYWIuKTElMCMGA1UECxMc
+KGMpIDE5OTkgRW50cnVzdC5uZXQgTGltaXRlZDE6MDgGA1UEAxMxRW50cnVzdC5u
+ZXQgU2VjdXJlIFNlcnZlciBDZXJ0aWZpY2F0aW9uIEF1dGhvcml0eTAeFw0wNzA0
+MjYwNTAwMDBaFw0xMzA4MTQyMDEyMzZaMF8xCzAJBgNVBAYTAk5MMRIwEAYDVQQK
+EwlEaWdpTm90YXIxGjAYBgNVBAMTEURpZ2lOb3RhciBSb290IENBMSAwHgYJKoZI
+hvcNAQkBFhFpbmZvQGRpZ2lub3Rhci5ubDCCAiIwDQYJKoZIhvcNAQEBBQADggIP
+ADCCAgoCggIBAKywWMEAvdghCAsrmv5uVjAFnxt3kBBBXMMNhxF3joHxynzpjGrt
+OHQ1u9rf+bvACTe0lnOBfTMamDn3k2+Vfz25sXWHulFI6ItwPpUExdi2wxbZiLCx
+hx1w2oa0DxSLes8Q0XQ2ohJ7d4ZKeeZ73wIRaKVOhq40WJskE3hWIiUeAYtLUXH7
+gsxZlmmIWmhTxbkNAjfLS7xmSpB+KgsFB+0WX1WQddhGyRuD4gi+8SPMmR3WKg+D
+IBVYJ4Iu+uIiwkmxuQGBap1tnUB3aHZOISpthECFTnaZfILz87cCWdQmARuO361T
+BtGuGN3isjrL14g4jqxbKbkZ05j5GAPPSIKGZgsbaQ/J6ziIeiYaBUyS1yTUlvKs
+Ui2jR9VS9j/+zoQGcKaqPqLytlY0GFei5IFt58rwatPHkWsCg0F8Fe9rmmRe49A8
+5bHre12G+8vmd0nNo2Xc97mcuOQLX5PPzDAaMhzOHGOVpfnq4XSLnukrqTB7oBgf
+DhgL5Vup09FsHgdnj5FLqYq80maqkwGIspH6MVzVpsFSCAnNCmOi0yKm6KHZOQaX
+9W6NApCMFHs/gM0bnLrEWHIjr7ZWn8Z6QjMpBz+CyeYfBQ3NTCg2i9PIPhzGiO9e
+7olk6R3r2ol+MqZp0d3MiJ/R0MlmIdwGZ8WUepptYkx9zOBkgLKeR46jAgMBAAGj
+ggEmMIIBIjASBgNVHRMBAf8ECDAGAQH/AgEBMCcGA1UdJQQgMB4GCCsGAQUFBwMB
+BggrBgEFBQcDAgYIKwYBBQUHAwQwEQYDVR0gBAowCDAGBgRVHSAAMDMGCCsGAQUF
+BwEBBCcwJTAjBggrBgEFBQcwAYYXaHR0cDovL29jc3AuZW50cnVzdC5uZXQwMwYD
+VR0fBCwwKjAooCagJIYiaHR0cDovL2NybC5lbnRydXN0Lm5ldC9zZXJ2ZXIxLmNy
+bDAdBgNVHQ4EFgQUiGi/4I41xDs4a2L3KDuEgcgM100wCwYDVR0PBAQDAgEGMB8G
+A1UdIwQYMBaAFPAXYhNVPbP/CgBr+1CEl/PtYtAaMBkGCSqGSIb2fQdBAAQMMAob
+BFY3LjEDAgCBMA0GCSqGSIb3DQEBBQUAA4GBAI979rBep8tu3TeLunapgsZ0jtXp
+GDFjKWSk87dj1jCyYi+q/GyDyZ6ZQZNRP0sF+6twscq05lClWNy3TROMp7QeuoLO
+G7Utw3OJaswUtp4YglANMRTHEe3g9ltifUXRH5tSuy7u6yi4LD4WTm5ULP6r/g6l
+0CnjXYb0+b1Fmz6U
+-----END CERTIFICATE-----
+
+// Subject: EMAILADDRESS=info@diginotar.nl,
+// CN=DigiNotar Root CA,
+// O=DigiNotar, C=NL
+// Issuer: CN=Entrust.net Secure Server Certification Authority
+// OU=(c) 1999 Entrust.net Limited,
+// OU=www.entrust.net/CPS incorp. by ref. (limits liab.),
+// O=Entrust.net,
+// C=US,
+// Serial: 1184640175 (46:9C:2C:AF)
+-----BEGIN CERTIFICATE-----
+MIIFSDCCBLGgAwIBAgIERpwsrzANBgkqhkiG9w0BAQUFADCBwzELMAkGA1UEBhMC
+VVMxFDASBgNVBAoTC0VudHJ1c3QubmV0MTswOQYDVQQLEzJ3d3cuZW50cnVzdC5u
+ZXQvQ1BTIGluY29ycC4gYnkgcmVmLiAobGltaXRzIGxpYWIuKTElMCMGA1UECxMc
+KGMpIDE5OTkgRW50cnVzdC5uZXQgTGltaXRlZDE6MDgGA1UEAxMxRW50cnVzdC5u
+ZXQgU2VjdXJlIFNlcnZlciBDZXJ0aWZpY2F0aW9uIEF1dGhvcml0eTAeFw0wNzA3
+MjYxNTU3MzlaFw0xMzA4MjYxNjI3MzlaMF8xCzAJBgNVBAYTAk5MMRIwEAYDVQQK
+EwlEaWdpTm90YXIxGjAYBgNVBAMTEURpZ2lOb3RhciBSb290IENBMSAwHgYJKoZI
+hvcNAQkBFhFpbmZvQGRpZ2lub3Rhci5ubDCCAiIwDQYJKoZIhvcNAQEBBQADggIP
+ADCCAgoCggIBAKywWMEAvdghCAsrmv5uVjAFnxt3kBBBXMMNhxF3joHxynzpjGrt
+OHQ1u9rf+bvACTe0lnOBfTMamDn3k2+Vfz25sXWHulFI6ItwPpUExdi2wxbZiLCx
+hx1w2oa0DxSLes8Q0XQ2ohJ7d4ZKeeZ73wIRaKVOhq40WJskE3hWIiUeAYtLUXH7
+gsxZlmmIWmhTxbkNAjfLS7xmSpB+KgsFB+0WX1WQddhGyRuD4gi+8SPMmR3WKg+D
+IBVYJ4Iu+uIiwkmxuQGBap1tnUB3aHZOISpthECFTnaZfILz87cCWdQmARuO361T
+BtGuGN3isjrL14g4jqxbKbkZ05j5GAPPSIKGZgsbaQ/J6ziIeiYaBUyS1yTUlvKs
+Ui2jR9VS9j/+zoQGcKaqPqLytlY0GFei5IFt58rwatPHkWsCg0F8Fe9rmmRe49A8
+5bHre12G+8vmd0nNo2Xc97mcuOQLX5PPzDAaMhzOHGOVpfnq4XSLnukrqTB7oBgf
+DhgL5Vup09FsHgdnj5FLqYq80maqkwGIspH6MVzVpsFSCAnNCmOi0yKm6KHZOQaX
+9W6NApCMFHs/gM0bnLrEWHIjr7ZWn8Z6QjMpBz+CyeYfBQ3NTCg2i9PIPhzGiO9e
+7olk6R3r2ol+MqZp0d3MiJ/R0MlmIdwGZ8WUepptYkx9zOBkgLKeR46jAgMBAAGj
+ggEmMIIBIjASBgNVHRMBAf8ECDAGAQH/AgEBMCcGA1UdJQQgMB4GCCsGAQUFBwMB
+BggrBgEFBQcDAgYIKwYBBQUHAwQwEQYDVR0gBAowCDAGBgRVHSAAMDMGCCsGAQUF
+BwEBBCcwJTAjBggrBgEFBQcwAYYXaHR0cDovL29jc3AuZW50cnVzdC5uZXQwMwYD
+VR0fBCwwKjAooCagJIYiaHR0cDovL2NybC5lbnRydXN0Lm5ldC9zZXJ2ZXIxLmNy
+bDAdBgNVHQ4EFgQUiGi/4I41xDs4a2L3KDuEgcgM100wCwYDVR0PBAQDAgEGMB8G
+A1UdIwQYMBaAFPAXYhNVPbP/CgBr+1CEl/PtYtAaMBkGCSqGSIb2fQdBAAQMMAob
+BFY3LjEDAgCBMA0GCSqGSIb3DQEBBQUAA4GBAEa6RcDNcEIGUlkDJUY/pWTds4zh
+xbVkp3wSmpwPFhx5fxTyF4HD2L60jl3aqjTB7gPpsL2Pk5QZlNsi3t4UkCV70UOd
+ueJRN3o/LOtk4+bjXY2lC0qTHbN80VMLqPjmaf9ghSA9hwhskdtMgRsgfd90q5QP
+ZFdYf+hthc3m6IcJ
+-----END CERTIFICATE-----
+
+// Subject: CN=DigiNotar PKIoverheid CA Organisatie - G2,
+// O=DigiNotar B.V.,
+// C=NL
+// Issuer: CN=Staat der Nederlanden Organisatie CA - G2,
+// O=Staat der Nederlanden,
+// C=NL
+// Serial: 20001983 (01:31:34:bf)
+-----BEGIN CERTIFICATE-----
+MIIGnDCCBISgAwIBAgIEATE0vzANBgkqhkiG9w0BAQsFADBhMQswCQYDVQQGEwJO
+TDEeMBwGA1UECgwVU3RhYXQgZGVyIE5lZGVybGFuZGVuMTIwMAYDVQQDDClTdGFh
+dCBkZXIgTmVkZXJsYW5kZW4gT3JnYW5pc2F0aWUgQ0EgLSBHMjAeFw0xMDA1MTIw
+ODUxMzhaFw0yMDAzMjMwOTUwMDRaMFoxCzAJBgNVBAYTAk5MMRcwFQYDVQQKDA5E
+aWdpTm90YXIgQi5WLjEyMDAGA1UEAwwpRGlnaU5vdGFyIFBLSW92ZXJoZWlkIENB
+IE9yZ2FuaXNhdGllIC0gRzIwggIiMA0GCSqGSIb3DQEBAQUAA4ICDwAwggIKAoIC
+AQCxExkPJ+Zs1FWGS9DsiYpFkXisR71HK+T8RetPtCZzWzfTw3/2497Xo/gtaMUI
+PkuU1uSHJTZrhLUYdPMoWHMvm2rPvAQe9t7dr/xLqvXbZmIlASWC3vKXWhBu3V2p
+IrEEqSNzOvhxrR3PhETrR9Gvbch8KKvH8jd6dF9fxQIUiqNa4xtsAeNdjtlo1vQJ
+GzLckbUs9SDrjANtJkm4k8SFXdjSm69WaswFM8ygQp40VUSca6DUEtArVM23iQ3l
+9uvo+4UBM096a/GdcjOWDveyhKWlJ8Qn8VFzKXe6Z27+TNy04qGhgS85SY1DOBPO
+0KVcwoc6AGdlQiPxNlkKHaNRyLyjlCox3+M88p0aPASw77EKMBNzttfzo0wBdRSF
+eMDXijlYhVD6LubFvs+LP6+PNtQlCS3SD6xyk/K/i9RQs/kVUJuZ9RTZ+4uRozIm
+JqD43ztggYaDeVsr6xM9KTrBbd29no6H1kquNJcF7hSm9tw4fkrpJFQHPZdoN0Zr
+DceoIa8TVOQJavFNRgrJXfubT73e+7dUy7g4nKc5+2otwHuNq6WnV+xKkoozxeEg
+XHPYkJIrgNUPhhhpfDlPhIa890xb89W0yqDC8DciynlSH1PmqvOQsDvd8ij9rOvF
+BiSgydQvD1j9tZ7sD8+yWdCiBHo4aq5y+73wJWKUCacFCwIDAQABo4IBYTCCAV0w
+SAYDVR0gBEEwPzA9BgRVHSAAMDUwMwYIKwYBBQUHAgEWJ2h0dHA6Ly93d3cuZGln
+aW5vdGFyLm5sL2Nwcy9wa2lvdmVyaGVpZDAPBgNVHRMBAf8EBTADAQH/MA4GA1Ud
+DwEB/wQEAwIBBjCBhQYDVR0jBH4wfIAUORCLSZJc22ESIM1JnRqO2pxnQLmhXqRc
+MFoxCzAJBgNVBAYTAk5MMR4wHAYDVQQKDBVTdGFhdCBkZXIgTmVkZXJsYW5kZW4x
+KzApBgNVBAMMIlN0YWF0IGRlciBOZWRlcmxhbmRlbiBSb290IENBIC0gRzKCBACY
+lvQwSQYDVR0fBEIwQDA+oDygOoY4aHR0cDovL2NybC5wa2lvdmVyaGVpZC5ubC9E
+b21PcmdhbmlzYXRpZUxhdGVzdENSTC1HMi5jcmwwHQYDVR0OBBYEFLxdlDvZq3sD
+JXNhwtst7vyrj2WhMA0GCSqGSIb3DQEBCwUAA4ICAQCP/C1Mt9kt1R+978v0t2gX
+dZ1O1ffdnPEqJu2forYcA9VTs+wIzzTi48P0tRYvyMO+19NzqwA2+RpKftZj6V5G
+uqW2jhW3oyrYQx3vXcgfgYWzi/f/PPTZ9EYIP5y8HaDZqEzNJVJOCrEg9x/pQ9lU
+RoETmsBedGwqmDLq/He7DaWiMZgifnx859qkrey3LhoZcfhIUNpDjyyE3cFAJ+O1
+8BVOltT4XOOGKUYr1zsH6zh/yIZXl9PvKjPEF1DVZGlrK2tFXl0vF8paTs/D1zk8
+9TufRrmb5w5Jl53W1eMbD+qPAU6aE5RZCgIHSEsaYKt/T+0L2FUNaG9VnGllFULs
+wNzdbKzDFs4LHVabpMTE0i7gD+JEJytQaaTcYuiKISlCbMwAOpZ2m+9AwKRed4Qy
+bCYqOWauXeO5ubIsaB8empADOfCqs6TMSYsYNOk3yXspx4R8b0QVL+xhWQTJRcui
+1lKifH8pktZKxYtCqNT+6tjHhyMY5J16fXNAUpigrm7jBT8FD+Clxm1N7YM3iJzH
+89xCmmq21yFJNnfy7xhPxXDZnunetyuL9Lx+KN8NQMmFXK6dxTH/0FwOtah+8Okv
+uq+IruW10Vilr5xxpykBkINpN4IFuvwJwQhujHg7wzMCgD9EhQgd31VWCK0shS1d
+sQPhrqp0xaTzTro3mHuCuQ==
+-----END CERTIFICATE-----
+
+// Subject: CN=DigiNotar PKIoverheid CA Overheid en Bedrijven,
+// O=DigiNotar B.V.,
+// C=NL
+// Issuer: CN=Staat der Nederlanden Overheid CA
+// O=Staat der Nederlanden,
+// C=NL
+// Serial: 20015536 (01:31:69:b0)
+-----BEGIN CERTIFICATE-----
+MIIEiDCCA3CgAwIBAgIEATFpsDANBgkqhkiG9w0BAQUFADBZMQswCQYDVQQGEwJO
+TDEeMBwGA1UEChMVU3RhYXQgZGVyIE5lZGVybGFuZGVuMSowKAYDVQQDEyFTdGFh
+dCBkZXIgTmVkZXJsYW5kZW4gT3ZlcmhlaWQgQ0EwHhcNMDcwNzA1MDg0MjA3WhcN
+MTUwNzI3MDgzOTQ2WjBfMQswCQYDVQQGEwJOTDEXMBUGA1UEChMORGlnaU5vdGFy
+IEIuVi4xNzA1BgNVBAMTLkRpZ2lOb3RhciBQS0lvdmVyaGVpZCBDQSBPdmVyaGVp
+ZCBlbiBCZWRyaWp2ZW4wggEiMA0GCSqGSIb3DQEBAQUAA4IBDwAwggEKAoIBAQDc
+vdKnTmoKuzuiheF/AK2+tDBomAfNoHrElM9x+Yo35FPrV3bMi+Zs/u6HVcg+uwQ5
+AKeAeKxbT370vbhUuHE7BzFJOZNUfCA7eSuPu2GQfbGs5h+QLp1FAalkLU3DL7nn
+UNVOKlyrdnY3Rtd57EKZ96LspIlw3Dgrh6aqJOadkiQbvvb91C8ZF3rmMgeUVAVT
+Q+lsvK9Hy7zL/b07RBKB8WtLu+20z6slTxjSzAL8o0+1QjPLWc0J3NNQ/aB2jKx+
+ZopC9q0ckvO2+xRG603XLzDgbe5bNr5EdLcgBVeFTegAGaL2DOauocBC36esgl3H
+aLcY5olLmmv6znn58yynAgMBAAGjggFQMIIBTDBIBgNVHSAEQTA/MD0GBFUdIAAw
+NTAzBggrBgEFBQcCARYnaHR0cDovL3d3dy5kaWdpbm90YXIubmwvY3BzL3BraW92
+ZXJoZWlkMA8GA1UdEwEB/wQFMAMBAf8wDgYDVR0PAQH/BAQDAgEGMIGABgNVHSME
+eTB3gBQLhtYPd6NosftkCcOIblwEHFfpPaFZpFcwVTELMAkGA1UEBhMCTkwxHjAc
+BgNVBAoTFVN0YWF0IGRlciBOZWRlcmxhbmRlbjEmMCQGA1UEAxMdU3RhYXQgZGVy
+IE5lZGVybGFuZGVuIFJvb3QgQ0GCBACYmnkwPQYDVR0fBDYwNDAyoDCgLoYsaHR0
+cDovL2NybC5wa2lvdmVyaGVpZC5ubC9Eb21PdkxhdGVzdENSTC5jcmwwHQYDVR0O
+BBYEFEwIyY128ZjHPt881y91DbF2eZfMMA0GCSqGSIb3DQEBBQUAA4IBAQAMlIca
+v03jheLu19hjeQ5Q38aEW9K72fUxCho1l3TfFPoqDz7toOMI9tVOW6+mriXiRWsi
+D7dUKH6S3o0UbNEc5W50BJy37zRERd/Jgx0ZH8Apad+J1T/CsFNt5U4X5HNhIxMm
+cUP9TFnLw98iqiEr2b+VERqKpOKrp11Lbyn1UtHk0hWxi/7wA8+nfemZhzizDXMU
+5HIs4c71rQZIZPrTKbmi2Lv01QulQERDjqC/zlqlUkxk0xcxYczopIro5Ij76eUv
+BjMzm5RmZrGrUDqhCYF0U1onuabSJc/Tw6f/ltAv6uAejVLpGBwgCkegllYOQJBR
+RKwa/fHuhR/3Qlpl
+-----END CERTIFICATE-----
+
+// Subject: CN=DigiNotar PKIoverheid CA Overheid
+// O=DigiNotar B.V.,
+// C=NL
+// Issuer: CN=Staat der Nederlanden Overheid CA
+// O=Staat der Nederlanden,
+// C=NL
+// Serial: 20006006 (01:31:44:76)
+-----BEGIN CERTIFICATE-----
+MIIEezCCA2OgAwIBAgIEATFEdjANBgkqhkiG9w0BAQUFADBZMQswCQYDVQQGEwJO
+TDEeMBwGA1UEChMVU3RhYXQgZGVyIE5lZGVybGFuZGVuMSowKAYDVQQDEyFTdGFh
+dCBkZXIgTmVkZXJsYW5kZW4gT3ZlcmhlaWQgQ0EwHhcNMDQwNjI0MDgxOTMyWhcN
+MTAwNjIzMDgxNzM2WjBSMQswCQYDVQQGEwJOTDEXMBUGA1UEChMORGlnaU5vdGFy
+IEIuVi4xKjAoBgNVBAMTIURpZ2lOb3RhciBQS0lvdmVyaGVpZCBDQSBPdmVyaGVp
+ZDCCASIwDQYJKoZIhvcNAQEBBQADggEPADCCAQoCggEBANSlrubta5tlOjVCi/gb
+yLCvRqfBjxG8H594VcKHu0WAYc99SPZF9cycj5mw2GyfQvy/WIrGrL4iyNq1gSqR
+0QA/mTXKZIaPqzpDhdm+VvrKkmjrbZfaQxgMSs3ChtBsjcP9Lc0X1zXZ4Q8nBe3k
+BTp+zehINfmbjoEgXLxsMR5RQ6GxzKjuC04PQpbJQgTIakglKaqYcDDZbEscWgPV
+Hgj/2aoHlj6leW/ThHZ+O41jUguEmBLZA3mu3HrCfrHntb5dPt0ihzSx7GtD/SaX
+5HBLxnP189YuqMk5iRA95CtiSdKauvon/xRKRLNgG6XAz0ctSoY7xLDdiBVU5kJd
+FScCAwEAAaOCAVAwggFMMEgGA1UdIARBMD8wPQYEVR0gADA1MDMGCCsGAQUFBwIB
+FidodHRwOi8vd3d3LmRpZ2lub3Rhci5ubC9jcHMvcGtpb3ZlcmhlaWQwDwYDVR0T
+AQH/BAUwAwEB/zAOBgNVHQ8BAf8EBAMCAQYwgYAGA1UdIwR5MHeAFAuG1g93o2ix
++2QJw4huXAQcV+k9oVmkVzBVMQswCQYDVQQGEwJOTDEeMBwGA1UEChMVU3RhYXQg
+ZGVyIE5lZGVybGFuZGVuMSYwJAYDVQQDEx1TdGFhdCBkZXIgTmVkZXJsYW5kZW4g
+Um9vdCBDQYIEAJiaeTA9BgNVHR8ENjA0MDKgMKAuhixodHRwOi8vY3JsLnBraW92
+ZXJoZWlkLm5sL0RvbU92TGF0ZXN0Q1JMLmNybDAdBgNVHQ4EFgQUvRaYQh2+kdE9
+wpcl4CjXWOC1f+IwDQYJKoZIhvcNAQEFBQADggEBAGhQsCWLiaN2EOhPAW+JQP6o
+XBOrLv5w6joahzBFVn1BiefzmlMKjibqKYxURRvMAsMkh82/MfL8V0w6ugxl81lu
+i42dcxl9cKSVXKMw4bbBzJ2VQI5HTIABwefeNuy/eX6idVwYdt3ajAH7fUA8Q9Cq
+vr6H8B+8mwoEqTVTEVlCSsC/EXsokYEUr06PPzRudKjDmijgj7zFaIioZNc8hk7g
+ufEgrs/tmcNGylrwRHgCXjCRBt2NHlZ08l7A1AGU8HcHlSbG9Un/2q9kVHUkps0D
+gtUaEK+x6jpAu/R8Ojezu/+ZEcwwjI/KOhG+84+ejFmtyEkrUdsAdEdLf/2dKsw=
+-----END CERTIFICATE-----
+
+// Subject: EMAILADDRESS=info@diginotar.nl,
+// CN=DigiNotar Services 1024 CA
+// O=DigiNotar, C=NL
+// Issuer: CN=Entrust.net Secure Server Certification Authority,
+// OU=(c) 1999 Entrust.net Limited,
+// OU=www.entrust.net/CPS incorp. by ref. (limits liab.),
+// O=Entrust.net,
+// C=US
+// Serial: 1184640176 (46:9c:2c:b0)
+-----BEGIN CERTIFICATE-----
+MIIDzTCCAzagAwIBAgIERpwssDANBgkqhkiG9w0BAQUFADCBwzELMAkGA1UEBhMC
+VVMxFDASBgNVBAoTC0VudHJ1c3QubmV0MTswOQYDVQQLEzJ3d3cuZW50cnVzdC5u
+ZXQvQ1BTIGluY29ycC4gYnkgcmVmLiAobGltaXRzIGxpYWIuKTElMCMGA1UECxMc
+KGMpIDE5OTkgRW50cnVzdC5uZXQgTGltaXRlZDE6MDgGA1UEAxMxRW50cnVzdC5u
+ZXQgU2VjdXJlIFNlcnZlciBDZXJ0aWZpY2F0aW9uIEF1dGhvcml0eTAeFw0wNzA3
+MjYxNTU5MDBaFw0xMzA4MjYxNjI5MDBaMGgxCzAJBgNVBAYTAk5MMRIwEAYDVQQK
+EwlEaWdpTm90YXIxIzAhBgNVBAMTGkRpZ2lOb3RhciBTZXJ2aWNlcyAxMDI0IENB
+MSAwHgYJKoZIhvcNAQkBFhFpbmZvQGRpZ2lub3Rhci5ubDCBnzANBgkqhkiG9w0B
+AQEFAAOBjQAwgYkCgYEA2ptNXTz50eKLxsYIIMXZHkjsZlhneWIrQWP0iY1o2q+4
+lDaLGSSkoJPSmQ+yrS01Tc0vauH5mxkrvAQafi09UmTN8T5nD4ku6PJPrqYIoYX+
+oakJ5sarPkP8r3oDkdqmOaZh7phPGKjTs69mgumfvN1y+QYEvRLZGCTnq5NTi1kC
+AwEAAaOCASYwggEiMBIGA1UdEwEB/wQIMAYBAf8CAQAwJwYDVR0lBCAwHgYIKwYB
+BQUHAwEGCCsGAQUFBwMCBggrBgEFBQcDBDARBgNVHSAECjAIMAYGBFUdIAAwMwYI
+KwYBBQUHAQEEJzAlMCMGCCsGAQUFBzABhhdodHRwOi8vb2NzcC5lbnRydXN0Lm5l
+dDAzBgNVHR8ELDAqMCigJqAkhiJodHRwOi8vY3JsLmVudHJ1c3QubmV0L3NlcnZl
+cjEuY3JsMB0GA1UdDgQWBBT+3JRJDG/vXH/G8RKZTxZJrfuCZTALBgNVHQ8EBAMC
+AQYwHwYDVR0jBBgwFoAU8BdiE1U9s/8KAGv7UISX8+1i0BowGQYJKoZIhvZ9B0EA
+BAwwChsEVjcuMQMCAIEwDQYJKoZIhvcNAQEFBQADgYEAY3RqN6k/lpxmyFisCcnv
+9WWUf6MCxDgxvV0jh+zUVrLJsm7kBQb87PX6iHBZ1O7m3bV6oKNgLwIMq94SXa/w
+NUuqikeRGvWFLELHHe+VQ7NeuJWTpdrFKKqtci0xrZlrbP+MISevrZqRK8fdWMNu
+B8WfedLHjFW/TMcnXlEWKz4=
+-----END CERTIFICATE-----
+
+// Subject: CN=Buster Paper Comercial Ltda,
+// O=Buster Paper Comercial Ltda,
+// L=S?o Jos? Dos Campos,
+// ST=S?o Paulo,
+// C=BR
+// Issuer: CN=DigiCert Assured ID Code Signing CA-1,
+// OU=www.digicert.com,
+// O=DigiCert Inc,
+// C=US
+// Serial: 07:b4:4c:db:ff:fb:78:de:05:f4:26:16:72:a6:73:12
+-----BEGIN CERTIFICATE-----
+MIIGwzCCBaugAwIBAgIQB7RM2//7eN4F9CYWcqZzEjANBgkqhkiG9w0BAQUFADBv
+MQswCQYDVQQGEwJVUzEVMBMGA1UEChMMRGlnaUNlcnQgSW5jMRkwFwYDVQQLExB3
+d3cuZGlnaWNlcnQuY29tMS4wLAYDVQQDEyVEaWdpQ2VydCBBc3N1cmVkIElEIENv
+ZGUgU2lnbmluZyBDQS0xMB4XDTEzMDExNzAwMDAwMFoXDTE0MDEyMjEyMDAwMFow
+gY4xCzAJBgNVBAYTAkJSMRMwEQYDVQQIDApTw6NvIFBhdWxvMR4wHAYDVQQHDBVT
+w6NvIEpvc8OpIERvcyBDYW1wb3MxJDAiBgNVBAoTG0J1c3RlciBQYXBlciBDb21l
+cmNpYWwgTHRkYTEkMCIGA1UEAxMbQnVzdGVyIFBhcGVyIENvbWVyY2lhbCBMdGRh
+MIIBIjANBgkqhkiG9w0BAQEFAAOCAQ8AMIIBCgKCAQEAzO0l6jWIpEfO2oUpVHpL
+HETj5lzivNb0S9jKHgGJax917czh81PnGTxwxFXd6gLJuy/XFHvmiSi8g8jzlymn
+2Ji5zQ3CPaz7nomJokSUDlMVJ2qYWtctw4jrdjuI4qtn+koXXUFkWjkf8h8251I4
+tUs7S49HE2Go5owCYP3byajj7fsFAYR/Xb7TdVtndkZsUB/YgOjHovyACjouaNCi
+mDiRyQ6zLLjZGiyeD65Yiseuhp5b8/BL5h1p7w76QYMYMVQNAdtDKut2R8MBpuWf
+Ny7Eoi0x/gm1p9X5Rcl5aN7K0G4UtTAJKbkuUfXddsyFoM0Nx8uo8SgNQ8Y/X5Jx
+BwIDAQABo4IDOTCCAzUwHwYDVR0jBBgwFoAUe2jOKarAF75JeuHlP9an90WPNTIw
+HQYDVR0OBBYEFFLZ3n5nt/Eer7n1bvtOqMb1qKO5MA4GA1UdDwEB/wQEAwIHgDAT
+BgNVHSUEDDAKBggrBgEFBQcDAzBzBgNVHR8EbDBqMDOgMaAvhi1odHRwOi8vY3Js
+My5kaWdpY2VydC5jb20vYXNzdXJlZC1jcy0yMDExYS5jcmwwM6AxoC+GLWh0dHA6
+Ly9jcmw0LmRpZ2ljZXJ0LmNvbS9hc3N1cmVkLWNzLTIwMTFhLmNybDCCAcQGA1Ud
+IASCAbswggG3MIIBswYJYIZIAYb9bAMBMIIBpDA6BggrBgEFBQcCARYuaHR0cDov
+L3d3dy5kaWdpY2VydC5jb20vc3NsLWNwcy1yZXBvc2l0b3J5Lmh0bTCCAWQGCCsG
+AQUFBwICMIIBVh6CAVIAQQBuAHkAIAB1AHMAZQAgAG8AZgAgAHQAaABpAHMAIABD
+AGUAcgB0AGkAZgBpAGMAYQB0AGUAIABjAG8AbgBzAHQAaQB0AHUAdABlAHMAIABh
+AGMAYwBlAHAAdABhAG4AYwBlACAAbwBmACAAdABoAGUAIABEAGkAZwBpAEMAZQBy
+AHQAIABDAFAALwBDAFAAUwAgAGEAbgBkACAAdABoAGUAIABSAGUAbAB5AGkAbgBn
+ACAAUABhAHIAdAB5ACAAQQBnAHIAZQBlAG0AZQBuAHQAIAB3AGgAaQBjAGgAIABs
+AGkAbQBpAHQAIABsAGkAYQBiAGkAbABpAHQAeQAgAGEAbgBkACAAYQByAGUAIABp
+AG4AYwBvAHIAcABvAHIAYQB0AGUAZAAgAGgAZQByAGUAaQBuACAAYgB5ACAAcgBl
+AGYAZQByAGUAbgBjAGUALjCBggYIKwYBBQUHAQEEdjB0MCQGCCsGAQUFBzABhhho
+dHRwOi8vb2NzcC5kaWdpY2VydC5jb20wTAYIKwYBBQUHMAKGQGh0dHA6Ly9jYWNl
+cnRzLmRpZ2ljZXJ0LmNvbS9EaWdpQ2VydEFzc3VyZWRJRENvZGVTaWduaW5nQ0Et
+MS5jcnQwDAYDVR0TAQH/BAIwADANBgkqhkiG9w0BAQUFAAOCAQEAPTTQvpOIikXI
+hTLnNbajaFRR5GhQpTzUNgBfF9VYSlNw/wMjpGsrh5RxaJCip52jbehmTgjMRhft
+jRYyml44PAVsCcR9uEoDpCZYpI1fHI1R+F8jd1C9rqprbSwwOG4xlg4SmvTHYs6e
+gBItQ/1p9XY+Sf4Wv1qOuOFL1qvV/5VyR2zdlOQCmKCeMgxt6a/tHLBDiAA67D44
+/vfdoNJl0CU2It0PO60jdCPFNWIRcxL+OSDqAoePeUC7xQ+JsTEIxuUE8+d6w6fc
+BV2mYb1flh22t46GLjh4gyo7xw3aL6L0L0jzlTT6IcEw6NIbaPbIKj/npQnHobYj
+XMuKLxbh7g==
+-----END CERTIFICATE-----
+
+// Subject: CN=BUSTER ASSISTENCIA TECNICA ELETRONICA LTDA - ME,
+// O=BUSTER ASSISTENCIA TECNICA ELETRONICA LTDA - ME,
+// L=S?o Paulo,
+// ST=S?o Paulo,
+// C=BR
+// Issuer: CN=DigiCert Assured ID Code Signing CA-1,
+// OU=www.digicert.com,
+// O=DigiCert Inc,
+// C=US
+// Serial: 0a:38:9b:95:ee:73:6d:d1:3b:c0:ed:74:3f:d7:4d:2f
+-----BEGIN CERTIFICATE-----
+MIIG4DCCBcigAwIBAgIQCjible5zbdE7wO10P9dNLzANBgkqhkiG9w0BAQUFADBv
+MQswCQYDVQQGEwJVUzEVMBMGA1UEChMMRGlnaUNlcnQgSW5jMRkwFwYDVQQLExB3
+d3cuZGlnaWNlcnQuY29tMS4wLAYDVQQDEyVEaWdpQ2VydCBBc3N1cmVkIElEIENv
+ZGUgU2lnbmluZyBDQS0xMB4XDTEyMTEwOTAwMDAwMFoXDTEzMTExNDEyMDAwMFow
+gasxCzAJBgNVBAYTAkJSMRMwEQYDVQQIDApTw6NvIFBhdWxvMRMwEQYDVQQHDApT
+w6NvIFBhdWxvMTgwNgYDVQQKEy9CVVNURVIgQVNTSVNURU5DSUEgVEVDTklDQSBF
+TEVUUk9OSUNBIExUREEgLSBNRTE4MDYGA1UEAxMvQlVTVEVSIEFTU0lTVEVOQ0lB
+IFRFQ05JQ0EgRUxFVFJPTklDQSBMVERBIC0gTUUwggEiMA0GCSqGSIb3DQEBAQUA
+A4IBDwAwggEKAoIBAQDAqNeEs5/B2CTXGjTOkUIdu6jV6qulOZwdw4sefHWYj1UR
+4z6zPk9kjpUgbnb402RFq88QtfInwddZ/wXn9OxMtDd/3TnC7HrhNS7ga79ZFL2V
+JnmzKHum2Yvh0q82QEJ9tHBR2X9VdKpUIH08Zs3k6cWWM1H0YX0cxA/HohhesQJW
+kwJ3urOIJiH/HeByDk8a1NS8safcCxk5vxvW4WvCg43iT09LeHY5Aa8abKw8lqVb
+0tD5ZSIjdmdj3TT1U37iAHLLRM2DXbxfdbhouUX1c5U1ZHAMA67HwjKiseOiDaHj
+NUGbC37C+cgbc9VVM/cURD8WvS0Kj6fQv7F2QtJDAgMBAAGjggM5MIIDNTAfBgNV
+HSMEGDAWgBR7aM4pqsAXvkl64eU/1qf3RY81MjAdBgNVHQ4EFgQU88EXKAyDsh30
+o9+Gu9a4xUy+FSMwDgYDVR0PAQH/BAQDAgeAMBMGA1UdJQQMMAoGCCsGAQUFBwMD
+MHMGA1UdHwRsMGowM6AxoC+GLWh0dHA6Ly9jcmwzLmRpZ2ljZXJ0LmNvbS9hc3N1
+cmVkLWNzLTIwMTFhLmNybDAzoDGgL4YtaHR0cDovL2NybDQuZGlnaWNlcnQuY29t
+L2Fzc3VyZWQtY3MtMjAxMWEuY3JsMIIBxAYDVR0gBIIBuzCCAbcwggGzBglghkgB
+hv1sAwEwggGkMDoGCCsGAQUFBwIBFi5odHRwOi8vd3d3LmRpZ2ljZXJ0LmNvbS9z
+c2wtY3BzLXJlcG9zaXRvcnkuaHRtMIIBZAYIKwYBBQUHAgIwggFWHoIBUgBBAG4A
+eQAgAHUAcwBlACAAbwBmACAAdABoAGkAcwAgAEMAZQByAHQAaQBmAGkAYwBhAHQA
+ZQAgAGMAbwBuAHMAdABpAHQAdQB0AGUAcwAgAGEAYwBjAGUAcAB0AGEAbgBjAGUA
+IABvAGYAIAB0AGgAZQAgAEQAaQBnAGkAQwBlAHIAdAAgAEMAUAAvAEMAUABTACAA
+YQBuAGQAIAB0AGgAZQAgAFIAZQBsAHkAaQBuAGcAIABQAGEAcgB0AHkAIABBAGcA
+cgBlAGUAbQBlAG4AdAAgAHcAaABpAGMAaAAgAGwAaQBtAGkAdAAgAGwAaQBhAGIA
+aQBsAGkAdAB5ACAAYQBuAGQAIABhAHIAZQAgAGkAbgBjAG8AcgBwAG8AcgBhAHQA
+ZQBkACAAaABlAHIAZQBpAG4AIABiAHkAIAByAGUAZgBlAHIAZQBuAGMAZQAuMIGC
+BggrBgEFBQcBAQR2MHQwJAYIKwYBBQUHMAGGGGh0dHA6Ly9vY3NwLmRpZ2ljZXJ0
+LmNvbTBMBggrBgEFBQcwAoZAaHR0cDovL2NhY2VydHMuZGlnaWNlcnQuY29tL0Rp
+Z2lDZXJ0QXNzdXJlZElEQ29kZVNpZ25pbmdDQS0xLmNydDAMBgNVHRMBAf8EAjAA
+MA0GCSqGSIb3DQEBBQUAA4IBAQAei1QmiXepje8OIfo/WonD4MIXgpPr2dfRaquQ
+A8q63OpTRSveyqdQDCSPpDRF/nvO1Y30yksZvIH1tNBsW5LBdxAKN3lFdBlqBwtE
+Q3jHc0KVVYRJ0FBaGE/PJHmRajscdAhYIcMPhTga0u0tDK+wOHEq3993dfl6yHjA
+XHU2iW5pnk75ZoE39zALD5eKXT8ZXrET5c3XUFJKWA+XuGmdmyzqo0Au49PanBv9
+UlZnabYfqoMArqMS0tGSX4cGgi9/2E+pHG9BX4sFW+ZDumroOA2pxyMWEKjxePEL
+zCOfhbsRWdMLYepauaNZOIMZXmFwcrIl0TGMkTAtATz+XmZc
+-----END CERTIFICATE-----
+
+// Subject: CN=CLEARESULT CONSULTING INC., OU=Corporate IT,
+// O=CLEARESULT CONSULTING INC., L=Austin, ST=TX, C=US
+// Issuer: SERIALNUMBER=07969287,
+// CN=Go Daddy Secure Certification Authority,
+// OU=http://certificates.godaddy.com/repository,
+// O="GoDaddy.com, Inc.",
+// L=Scottsdale,
+// ST=Arizona,
+// C=US
+// Serial: 2b:73:43:2a:a8:4f:44
+-----BEGIN CERTIFICATE-----
+MIIFYjCCBEqgAwIBAgIHK3NDKqhPRDANBgkqhkiG9w0BAQUFADCByjELMAkGA1UE
+BhMCVVMxEDAOBgNVBAgTB0FyaXpvbmExEzARBgNVBAcTClNjb3R0c2RhbGUxGjAY
+BgNVBAoTEUdvRGFkZHkuY29tLCBJbmMuMTMwMQYDVQQLEypodHRwOi8vY2VydGlm
+aWNhdGVzLmdvZGFkZHkuY29tL3JlcG9zaXRvcnkxMDAuBgNVBAMTJ0dvIERhZGR5
+IFNlY3VyZSBDZXJ0aWZpY2F0aW9uIEF1dGhvcml0eTERMA8GA1UEBRMIMDc5Njky
+ODcwHhcNMTIwMjE1MjEwOTA2WhcNMTQwMjE1MjEwOTA2WjCBjDELMAkGA1UEBgwC
+VVMxCzAJBgNVBAgMAlRYMQ8wDQYDVQQHDAZBdXN0aW4xIzAhBgNVBAoMGkNMRUFS
+RVNVTFQgQ09OU1VMVElORyBJTkMuMRUwEwYDVQQLDAxDb3Jwb3JhdGUgSVQxIzAh
+BgNVBAMMGkNMRUFSRVNVTFQgQ09OU1VMVElORyBJTkMuMIIBIjANBgkqhkiG9w0B
+AQEFAAOCAQ8AMIIBCgKCAQEAtIOjCKeAicull+7ZIzt0/4ya3IeXUFlfypqKMLkU
+IbKjn0P5uMj6VE3rlbZr44RCegxvdnR6umBh1c0ZXoN3o+yc0JKcKcLiApmJJ277
+p7IbLwYDhBXRQNoIJm187IOMRPIxsKN4hL91txn9jGBmW+9zKlJlNhR5R7vjwU2E
+jrH/6oqsc9EM2yYpfjlNv6+3jSwAYZCkSWr+27PQOV+YHKmIxtJjX0upFz5FdIrV
+9CCX+L2Kji1THOkSgG4QTbYxmEcHqGViWz8hXLeNXjcbEsPuIiAu3hknxRHfUTE/
+U0Lh0Ug1e3LrJu+WnxM2SmUY4krsZ22c0yWUW9hzWITIjQIDAQABo4IBhzCCAYMw
+DwYDVR0TAQH/BAUwAwEBADATBgNVHSUEDDAKBggrBgEFBQcDAzAOBgNVHQ8BAf8E
+BAMCB4AwMwYDVR0fBCwwKjAooCagJIYiaHR0cDovL2NybC5nb2RhZGR5LmNvbS9n
+ZHM1LTE2LmNybDBTBgNVHSAETDBKMEgGC2CGSAGG/W0BBxcCMDkwNwYIKwYBBQUH
+AgEWK2h0dHA6Ly9jZXJ0aWZpY2F0ZXMuZ29kYWRkeS5jb20vcmVwb3NpdG9yeS8w
+gYAGCCsGAQUFBwEBBHQwcjAkBggrBgEFBQcwAYYYaHR0cDovL29jc3AuZ29kYWRk
+eS5jb20vMEoGCCsGAQUFBzAChj5odHRwOi8vY2VydGlmaWNhdGVzLmdvZGFkZHku
+Y29tL3JlcG9zaXRvcnkvZ2RfaW50ZXJtZWRpYXRlLmNydDAfBgNVHSMEGDAWgBT9
+rGEyk2xF1uLuhV+auud2mWjM5zAdBgNVHQ4EFgQUDtdeKqeN2QkcbEp1HovFieNB
+XiowDQYJKoZIhvcNAQEFBQADggEBAD74Agw5tvi2aBl4/f/s7/VE/BClzDsKMb9K
+v9qpeC45ZA/jelxV11HKbQnVF194gDb7D2H9OsAsRUy8HVKbXEcc/8dKvwOqb+BC
+2i/EmfjLgmCfezNFtLq8xcPxF3zIRc44vPrK0z4YZsaHdH+yTEJ51p5EMdTqaLaP
+4n5m8LX3RfqlQB9dYFe6dUoYZjKm9d/pIRww3VqfOzjl42Edi1w6dWmBVMx1NZuR
+DBabJH1vJ9Gd+KwxMCmBZ6pQPl28JDimhJhI2LNqU349uADQVV0HJosddN/ARyyI
+LSIQO7BnNVKVG9Iujf33bvPNeg0qNz5qw+rKKq97Pqeum+L5oKU=
+-----END CERTIFICATE-----
+
+// Subject: CN=eDellRoot
+// Issuer: CN=eDellRoot
+// Serial Number:
+// 6b:c5:7b:95:18:93:aa:97:4b:62:4a:c0:88:fc:3b:b6
+-----BEGIN CERTIFICATE-----
+MIIC8zCCAd+gAwIBAgIQa8V7lRiTqpdLYkrAiPw7tjAJBgUrDgMCHQUAMBQxEjAQ
+BgNVBAMTCWVEZWxsUm9vdDAeFw0xNTA0MDcxMDIzMjdaFw0zOTEyMzEyMzU5NTla
+MBQxEjAQBgNVBAMTCWVEZWxsUm9vdDCCASIwDQYJKoZIhvcNAQEBBQADggEPADCC
+AQoCggEBAL3RJg1uzVuEX0Hw4XWGzs6oI9W+o7HZdVdBMMVb4Gzb4uZjCTNjbPx4
+b8LNFL1uArUt+5VVMQDsOTY3Lg/Xe/UNukY2b+0llUOzzBYYpbsFcco4n6SsTvDh
+Ni5t+kPo7c23ZrYBPmOu82eEJ6cavs/t39u+wFOkXXwvRCiHA/lWyNWNEPh17+bC
+EP3q5N+JrV+6Ho3zQPEv5QUJYdmXsMmD2CMQojeQUj68J91P5w5BKjurG0xjivzh
+Soie9ym7VRwLFjWScRuw/9XV6CLqTyL5xrqiiDp1uTOuqNj3uxyts9ocbsoJXuxj
+5iEYkSM1nvLupEv+lgy9WqzIEFMm1l8CAwEAAaNJMEcwRQYDVR0BBD4wPIAQYA/f
+EzPwmaRcZuSaa/VZ1KEWMBQxEjAQBgNVBAMTCWVEZWxsUm9vdIIQa8V7lRiTqpdL
+YkrAiPw7tjAJBgUrDgMCHQUAA4IBAQArfdcScsezj8ooJ92UwwnPgg36noOgiUs5
+XzPLP4h0JpUYQVKB9hY1WTDwRUfTKGh7oNOowd027a/rVSb/TNeoiJIvMKn4gbvV
+CWAiHhO8u2u0RkHCDVsa7e0i4ncpueWsihjn6jBrY8T+7eDYwiFT/F03A8NJ7mK5
+lZA8SFd5CTDy3EBUU5UwzXUc5HoIRUxXSPycu3aIBWawg3sCdKiAoikScPAWj0bM
+0vmsP/8QSlTOBqO+QFQ6R82BtTvBNU3qbVICV4QObsxib++FAFL56NApPqskg7Vz
+LfNIAjKabHUcjbuZkmg6jr4BfYW7+oQDHCsYgADjjKGdKz/8U/fP
+-----END CERTIFICATE-----
diff -Nru openjdk-lts-11.0.11+9/make/data/cacerts/globalsignr2ca openjdk-lts-11.0.14+9/make/data/cacerts/globalsignr2ca
--- openjdk-lts-11.0.11+9/make/data/cacerts/globalsignr2ca 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/make/data/cacerts/globalsignr2ca 1970-01-01 00:00:00.000000000 +0000
@@ -1,29 +0,0 @@
-Owner: CN=GlobalSign, O=GlobalSign, OU=GlobalSign Root CA - R2
-Issuer: CN=GlobalSign, O=GlobalSign, OU=GlobalSign Root CA - R2
-Serial number: 400000000010f8626e60d
-Valid from: Fri Dec 15 08:00:00 GMT 2006 until: Wed Dec 15 08:00:00 GMT 2021
-Signature algorithm name: SHA1withRSA
-Subject Public Key Algorithm: 2048-bit RSA key
-Version: 3
------BEGIN CERTIFICATE-----
-MIIDujCCAqKgAwIBAgILBAAAAAABD4Ym5g0wDQYJKoZIhvcNAQEFBQAwTDEgMB4G
-A1UECxMXR2xvYmFsU2lnbiBSb290IENBIC0gUjIxEzARBgNVBAoTCkdsb2JhbFNp
-Z24xEzARBgNVBAMTCkdsb2JhbFNpZ24wHhcNMDYxMjE1MDgwMDAwWhcNMjExMjE1
-MDgwMDAwWjBMMSAwHgYDVQQLExdHbG9iYWxTaWduIFJvb3QgQ0EgLSBSMjETMBEG
-A1UEChMKR2xvYmFsU2lnbjETMBEGA1UEAxMKR2xvYmFsU2lnbjCCASIwDQYJKoZI
-hvcNAQEBBQADggEPADCCAQoCggEBAKbPJA6+Lm8omUVCxKs+IVSbC9N/hHD6ErPL
-v4dfxn+G07IwXNb9rfF73OX4YJYJkhD10FPe+3t+c4isUoh7SqbKSaZeqKeMWhG8
-eoLrvozps6yWJQeXSpkqBy+0Hne/ig+1AnwblrjFuTosvNYSuetZfeLQBoZfXklq
-tTleiDTsvHgMCJiEbKjNS7SgfQx5TfC4LcshytVsW33hoCmEofnTlEnLJGKRILzd
-C9XZzPnqJworc5HGnRusyMvo4KD0L5CLTfuwNhv2GXqF4G3yYROIXJ/gkwpRl4pa
-zq+r1feqCapgvdzZX99yqWATXgAByUr6P6TqBwMhAo6CygPCm48CAwEAAaOBnDCB
-mTAOBgNVHQ8BAf8EBAMCAQYwDwYDVR0TAQH/BAUwAwEB/zAdBgNVHQ4EFgQUm+IH
-V2ccHsBqBt5ZtJot39wZhi4wNgYDVR0fBC8wLTAroCmgJ4YlaHR0cDovL2NybC5n
-bG9iYWxzaWduLm5ldC9yb290LXIyLmNybDAfBgNVHSMEGDAWgBSb4gdXZxwewGoG
-3lm0mi3f3BmGLjANBgkqhkiG9w0BAQUFAAOCAQEAmYFThxxol4aR7OBKuEQLq4Gs
-J0/WwbgcQ3izDJr86iw8bmEbTUsp9Z8FHSbBuOmDAGJFtqkIk7mpM0sYmsL4h4hO
-291xNBrBVNpGP+DTKqttVCL1OmLNIG+6KYnX3ZHu01yiPqFbQfXf5WRDLenVOavS
-ot+3i9DAgBkcRcAtjOj4LaR0VknFBbVPFd5uRHg5h6h+u/N5GJG79G+dwfCMNYxd
-AfvDbbnvRG15RjF+Cv6pgsH/76tuIMRQyV+dTZsXjAzlAcmgQWpzU/qlULRuJQ/7
-TBj0/VLZjmmx6BEP3ojY+x1J96relc8geMJgEtslQIxq/H5COEBkEveegeGTLg==
------END CERTIFICATE-----
diff -Nru openjdk-lts-11.0.11+9/make/data/cacerts/identrustdstx3 openjdk-lts-11.0.14+9/make/data/cacerts/identrustdstx3
--- openjdk-lts-11.0.11+9/make/data/cacerts/identrustdstx3 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/make/data/cacerts/identrustdstx3 1970-01-01 00:00:00.000000000 +0000
@@ -1,27 +0,0 @@
-Owner: CN=DST Root CA X3, O=Digital Signature Trust Co.
-Issuer: CN=DST Root CA X3, O=Digital Signature Trust Co.
-Serial number: 44afb080d6a327ba893039862ef8406b
-Valid from: Sat Sep 30 21:12:19 GMT 2000 until: Thu Sep 30 14:01:15 GMT 2021
-Signature algorithm name: SHA1withRSA
-Subject Public Key Algorithm: 2048-bit RSA key
-Version: 3
------BEGIN CERTIFICATE-----
-MIIDSjCCAjKgAwIBAgIQRK+wgNajJ7qJMDmGLvhAazANBgkqhkiG9w0BAQUFADA/
-MSQwIgYDVQQKExtEaWdpdGFsIFNpZ25hdHVyZSBUcnVzdCBDby4xFzAVBgNVBAMT
-DkRTVCBSb290IENBIFgzMB4XDTAwMDkzMDIxMTIxOVoXDTIxMDkzMDE0MDExNVow
-PzEkMCIGA1UEChMbRGlnaXRhbCBTaWduYXR1cmUgVHJ1c3QgQ28uMRcwFQYDVQQD
-Ew5EU1QgUm9vdCBDQSBYMzCCASIwDQYJKoZIhvcNAQEBBQADggEPADCCAQoCggEB
-AN+v6ZdQCINXtMxiZfaQguzH0yxrMMpb7NnDfcdAwRgUi+DoM3ZJKuM/IUmTrE4O
-rz5Iy2Xu/NMhD2XSKtkyj4zl93ewEnu1lcCJo6m67XMuegwGMoOifooUMM0RoOEq
-OLl5CjH9UL2AZd+3UWODyOKIYepLYYHsUmu5ouJLGiifSKOeDNoJjj4XLh7dIN9b
-xiqKqy69cK3FCxolkHRyxXtqqzTWMIn/5WgTe1QLyNau7Fqckh49ZLOMxt+/yUFw
-7BZy1SbsOFU5Q9D8/RhcQPGX69Wam40dutolucbY38EVAjqr2m7xPi71XAicPNaD
-aeQQmxkqtilX4+U9m5/wAl0CAwEAAaNCMEAwDwYDVR0TAQH/BAUwAwEB/zAOBgNV
-HQ8BAf8EBAMCAQYwHQYDVR0OBBYEFMSnsaR7LHH62+FLkHX/xBVghYkQMA0GCSqG
-SIb3DQEBBQUAA4IBAQCjGiybFwBcqR7uKGY3Or+Dxz9LwwmglSBd49lZRNI+DT69
-ikugdB/OEIKcdBodfpga3csTS7MgROSR6cz8faXbauX+5v3gTt23ADq1cEmv8uXr
-AvHRAosZy5Q6XkjEGB5YGV8eAlrwDPGxrancWYaLbumR9YbK+rlmM6pZW87ipxZz
-R8srzJmwN0jP41ZL9c8PDHIyh8bwRLtTcm1D9SZImlJnt1ir/md2cXjbDaJWFBM5
-JDGFoqgCWjBH4d1QB7wCCZAA62RjYJsWvIjJEubSfZGL+T0yjWW06XyxV3bqxbYo
-Ob8VZRzI9neWagqNdwvYkQsEjgfbKbYK7p2CNTUQ
------END CERTIFICATE-----
diff -Nru openjdk-lts-11.0.11+9/make/data/cacerts/soneraclass2ca openjdk-lts-11.0.14+9/make/data/cacerts/soneraclass2ca
--- openjdk-lts-11.0.11+9/make/data/cacerts/soneraclass2ca 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/make/data/cacerts/soneraclass2ca 1970-01-01 00:00:00.000000000 +0000
@@ -1,26 +0,0 @@
-Owner: CN=Sonera Class2 CA, O=Sonera, C=FI
-Issuer: CN=Sonera Class2 CA, O=Sonera, C=FI
-Serial number: 1d
-Valid from: Fri Apr 06 07:29:40 GMT 2001 until: Tue Apr 06 07:29:40 GMT 2021
-Signature algorithm name: SHA1withRSA
-Subject Public Key Algorithm: 2048-bit RSA key
-Version: 3
------BEGIN CERTIFICATE-----
-MIIDIDCCAgigAwIBAgIBHTANBgkqhkiG9w0BAQUFADA5MQswCQYDVQQGEwJGSTEP
-MA0GA1UEChMGU29uZXJhMRkwFwYDVQQDExBTb25lcmEgQ2xhc3MyIENBMB4XDTAx
-MDQwNjA3Mjk0MFoXDTIxMDQwNjA3Mjk0MFowOTELMAkGA1UEBhMCRkkxDzANBgNV
-BAoTBlNvbmVyYTEZMBcGA1UEAxMQU29uZXJhIENsYXNzMiBDQTCCASIwDQYJKoZI
-hvcNAQEBBQADggEPADCCAQoCggEBAJAXSjWdyvANlsdE+hY3/Ei9vX+ALTU74W+o
-Z6m/AxxNjG8yR9VBaKQTBME1DJqEQ/xcHf+Js+gXGM2RX/uJ4+q/Tl18GybTdXnt
-5oTjV+WtKcT0OijnpXuENmmz/V52vaMtmdOQTiMofRhj8VQ7Jp12W5dCsv+u8E7s
-3TmVToMGf+dJQMjFAbJUWmYdPfz56TwKnoG4cPABi+QjVHzIrviQHgCWctRUz2Ej
-vOr7nQKV0ba5cTppCD8PtOFCx4j1P5iop7oc4HFx71hXgVB6XGt0Rg6DA5jDjqhu
-8nYybieDwnPz3BjotJPqdURrBGAgcVeHnfO+oJAjPYok4doh28MCAwEAAaMzMDEw
-DwYDVR0TAQH/BAUwAwEB/zARBgNVHQ4ECgQISqCqWITTXjwwCwYDVR0PBAQDAgEG
-MA0GCSqGSIb3DQEBBQUAA4IBAQBazof5FnIVV0sd2ZvnoiYw7JNn39Yt0jSv9zil
-zqsWuasvfDXLrNAPtEwr/IDva4yRXzZ299uzGxnq9LIR/WFxRL8oszodv7ND6J+/
-3DEIcbCdjdY0RzKQxmUk96BKfARzjzlvF4xytb1LyHr4e4PDKE6cCepnP7JnBBvD
-FNr450kkkdAdavphOe9r5yF1BgfYErQhIHBCcYHaPJo2vqZbDWpsmh+Re/n570K6
-Tk6ezAyNlNzZRZxe7EJQY670XcSxEtzKO6gunRRaBXW37Ndj4ro1tgQIkejanZz2
-ZrUYrAqmVCY0M9IbwdR/GjqOC6oybtv8TyWf2TLHllpwrN9M
------END CERTIFICATE-----
diff -Nru openjdk-lts-11.0.11+9/make/data/cacerts/thawtepremiumserverca openjdk-lts-11.0.14+9/make/data/cacerts/thawtepremiumserverca
--- openjdk-lts-11.0.11+9/make/data/cacerts/thawtepremiumserverca 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/make/data/cacerts/thawtepremiumserverca 1970-01-01 00:00:00.000000000 +0000
@@ -1,27 +0,0 @@
-Owner: EMAILADDRESS=premium-server@thawte.com, CN=Thawte Premium Server CA, OU=Certification Services Division, O=Thawte Consulting cc, L=Cape Town, ST=Western Cape, C=ZA
-Issuer: EMAILADDRESS=premium-server@thawte.com, CN=Thawte Premium Server CA, OU=Certification Services Division, O=Thawte Consulting cc, L=Cape Town, ST=Western Cape, C=ZA
-Serial number: 36122296c5e338a520a1d25f4cd70954
-Valid from: Thu Aug 01 00:00:00 GMT 1996 until: Fri Jan 01 23:59:59 GMT 2021
-Signature algorithm name: SHA1withRSA
-Subject Public Key Algorithm: 1024-bit RSA key
-Version: 3
------BEGIN CERTIFICATE-----
-MIIDNjCCAp+gAwIBAgIQNhIilsXjOKUgodJfTNcJVDANBgkqhkiG9w0BAQUFADCB
-zjELMAkGA1UEBhMCWkExFTATBgNVBAgTDFdlc3Rlcm4gQ2FwZTESMBAGA1UEBxMJ
-Q2FwZSBUb3duMR0wGwYDVQQKExRUaGF3dGUgQ29uc3VsdGluZyBjYzEoMCYGA1UE
-CxMfQ2VydGlmaWNhdGlvbiBTZXJ2aWNlcyBEaXZpc2lvbjEhMB8GA1UEAxMYVGhh
-d3RlIFByZW1pdW0gU2VydmVyIENBMSgwJgYJKoZIhvcNAQkBFhlwcmVtaXVtLXNl
-cnZlckB0aGF3dGUuY29tMB4XDTk2MDgwMTAwMDAwMFoXDTIxMDEwMTIzNTk1OVow
-gc4xCzAJBgNVBAYTAlpBMRUwEwYDVQQIEwxXZXN0ZXJuIENhcGUxEjAQBgNVBAcT
-CUNhcGUgVG93bjEdMBsGA1UEChMUVGhhd3RlIENvbnN1bHRpbmcgY2MxKDAmBgNV
-BAsTH0NlcnRpZmljYXRpb24gU2VydmljZXMgRGl2aXNpb24xITAfBgNVBAMTGFRo
-YXd0ZSBQcmVtaXVtIFNlcnZlciBDQTEoMCYGCSqGSIb3DQEJARYZcHJlbWl1bS1z
-ZXJ2ZXJAdGhhd3RlLmNvbTCBnzANBgkqhkiG9w0BAQEFAAOBjQAwgYkCgYEA0jY2
-aovXwlue2oFBYo847kkEVdbQ7xwblRZH7xhINTpS9CtqBo87L+pW46+GjZ4X9560
-ZXUCTe/LCaIhUdib0GfQug2SBhRz1JPLlyoAnFxODLz6FVL88kRu2hFKbgifLy3j
-+ao6hnO2RlNYyIkFvYMRuHM/qgeN9EJN50CdHDcCAwEAAaMTMBEwDwYDVR0TAQH/
-BAUwAwEB/zANBgkqhkiG9w0BAQUFAAOBgQBlkKyID1bZ5jA01CbH0FDxkt5r1DmI
-CSLGpmODA/eZd9iy5Ri4XWPz1HP7bJyZePFLeH0ZJMMrAoT4vCLZiiLXoPxx7JGH
-IPG47LHlVYCsPVLIOQ7C8MAFT9aCdYy9X9LcdpoFEsmvcsPcJX6kTY4XpeCHf+Ga
-WuFg3GQjPEIuTQ==
------END CERTIFICATE-----
diff -Nru openjdk-lts-11.0.11+9/make/data/cacerts/verisignclass2g2ca openjdk-lts-11.0.14+9/make/data/cacerts/verisignclass2g2ca
--- openjdk-lts-11.0.11+9/make/data/cacerts/verisignclass2g2ca 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/make/data/cacerts/verisignclass2g2ca 1970-01-01 00:00:00.000000000 +0000
@@ -1,26 +0,0 @@
-Owner: OU=VeriSign Trust Network, OU="(c) 1998 VeriSign, Inc. - For authorized use only", OU=Class 2 Public Primary Certification Authority - G2, O="VeriSign, Inc.", C=US
-Issuer: OU=VeriSign Trust Network, OU="(c) 1998 VeriSign, Inc. - For authorized use only", OU=Class 2 Public Primary Certification Authority - G2, O="VeriSign, Inc.", C=US
-Serial number: b92f60cc889fa17a4609b85b706c8aaf
-Valid from: Mon May 18 00:00:00 GMT 1998 until: Tue Aug 01 23:59:59 GMT 2028
-Signature algorithm name: SHA1withRSA
-Subject Public Key Algorithm: 1024-bit RSA key
-Version: 1
------BEGIN CERTIFICATE-----
-MIIDAzCCAmwCEQC5L2DMiJ+hekYJuFtwbIqvMA0GCSqGSIb3DQEBBQUAMIHBMQsw
-CQYDVQQGEwJVUzEXMBUGA1UEChMOVmVyaVNpZ24sIEluYy4xPDA6BgNVBAsTM0Ns
-YXNzIDIgUHVibGljIFByaW1hcnkgQ2VydGlmaWNhdGlvbiBBdXRob3JpdHkgLSBH
-MjE6MDgGA1UECxMxKGMpIDE5OTggVmVyaVNpZ24sIEluYy4gLSBGb3IgYXV0aG9y
-aXplZCB1c2Ugb25seTEfMB0GA1UECxMWVmVyaVNpZ24gVHJ1c3QgTmV0d29yazAe
-Fw05ODA1MTgwMDAwMDBaFw0yODA4MDEyMzU5NTlaMIHBMQswCQYDVQQGEwJVUzEX
-MBUGA1UEChMOVmVyaVNpZ24sIEluYy4xPDA6BgNVBAsTM0NsYXNzIDIgUHVibGlj
-IFByaW1hcnkgQ2VydGlmaWNhdGlvbiBBdXRob3JpdHkgLSBHMjE6MDgGA1UECxMx
-KGMpIDE5OTggVmVyaVNpZ24sIEluYy4gLSBGb3IgYXV0aG9yaXplZCB1c2Ugb25s
-eTEfMB0GA1UECxMWVmVyaVNpZ24gVHJ1c3QgTmV0d29yazCBnzANBgkqhkiG9w0B
-AQEFAAOBjQAwgYkCgYEAp4gBIXQs5xoD8JjhlzwPIQjxnNuX6Zr8wgQGE75fUsjM
-HiwSViy4AWkszJkfrbCWrnkE8hM5wXuYuggs6MKEEyyqaekJ9MepAqRCwiNPStjw
-DqL7MWzJ5m+ZJwf15vRMeJ5t60aG+rmGyVTyssSv1EYcWskVMP8NbPUtDm3Of3cC
-AwEAATANBgkqhkiG9w0BAQUFAAOBgQByLvl/0fFx+8Se9sVeUYpAmLho+Jscg9ji
-nb3/7aHmZuovCfTK1+qlK5X2JGCGTUQug6XELaDTrnhpb3LabK4I8GOSN+a7xDAX
-rXfMSTWqz9iP0b63GJZHc2pUIjRkLbYWm1lbtFFZOrMLFPQS32eg9K0yZF6xRnIn
-jBJ7xUS0rg==
------END CERTIFICATE-----
diff -Nru openjdk-lts-11.0.11+9/make/data/cacerts/verisignclass3ca openjdk-lts-11.0.14+9/make/data/cacerts/verisignclass3ca
--- openjdk-lts-11.0.11+9/make/data/cacerts/verisignclass3ca 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/make/data/cacerts/verisignclass3ca 1970-01-01 00:00:00.000000000 +0000
@@ -1,21 +0,0 @@
-Owner: OU=Class 3 Public Primary Certification Authority, O="VeriSign, Inc.", C=US
-Issuer: OU=Class 3 Public Primary Certification Authority, O="VeriSign, Inc.", C=US
-Serial number: 3c9131cb1ff6d01b0e9ab8d044bf12be
-Valid from: Mon Jan 29 00:00:00 GMT 1996 until: Wed Aug 02 23:59:59 GMT 2028
-Signature algorithm name: SHA1withRSA
-Subject Public Key Algorithm: 1024-bit RSA key
-Version: 1
------BEGIN CERTIFICATE-----
-MIICPDCCAaUCEDyRMcsf9tAbDpq40ES/Er4wDQYJKoZIhvcNAQEFBQAwXzELMAkG
-A1UEBhMCVVMxFzAVBgNVBAoTDlZlcmlTaWduLCBJbmMuMTcwNQYDVQQLEy5DbGFz
-cyAzIFB1YmxpYyBQcmltYXJ5IENlcnRpZmljYXRpb24gQXV0aG9yaXR5MB4XDTk2
-MDEyOTAwMDAwMFoXDTI4MDgwMjIzNTk1OVowXzELMAkGA1UEBhMCVVMxFzAVBgNV
-BAoTDlZlcmlTaWduLCBJbmMuMTcwNQYDVQQLEy5DbGFzcyAzIFB1YmxpYyBQcmlt
-YXJ5IENlcnRpZmljYXRpb24gQXV0aG9yaXR5MIGfMA0GCSqGSIb3DQEBAQUAA4GN
-ADCBiQKBgQDJXFme8huKARS0EN8EQNvjV69qRUCPhAwL0TPZ2RHP7gJYHyX3KqhE
-BarsAx94f56TuZoAqiN91qyFomNFx3InzPRMxnVx0jnvT0Lwdd8KkMaOIG+YD/is
-I19wKTakyYbnsZogy1Olhec9vn2a/iRFM9x2Fe0PonFkTGUugWhFpwIDAQABMA0G
-CSqGSIb3DQEBBQUAA4GBABByUqkFFBkyCEHwxWsKzH4PIRnN5GfcX6kb5sroc50i
-2JhucwNhkcV8sEVAbkSdjbCxlnRhLQ2pRdKkkirWmnWXbj9T/UWZYB2oK0z5XqcJ
-2HUw19JlYD1n1khVdWk/kfVIC0dpImmClr7JyDiGSnoscxlIaU5rfGW/D/xwzoiQ
------END CERTIFICATE-----
diff -Nru openjdk-lts-11.0.11+9/make/data/cacerts/verisignclass3g2ca openjdk-lts-11.0.14+9/make/data/cacerts/verisignclass3g2ca
--- openjdk-lts-11.0.11+9/make/data/cacerts/verisignclass3g2ca 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/make/data/cacerts/verisignclass3g2ca 1970-01-01 00:00:00.000000000 +0000
@@ -1,26 +0,0 @@
-Owner: OU=VeriSign Trust Network, OU="(c) 1998 VeriSign, Inc. - For authorized use only", OU=Class 3 Public Primary Certification Authority - G2, O="VeriSign, Inc.", C=US
-Issuer: OU=VeriSign Trust Network, OU="(c) 1998 VeriSign, Inc. - For authorized use only", OU=Class 3 Public Primary Certification Authority - G2, O="VeriSign, Inc.", C=US
-Serial number: 7dd9fe07cfa81eb7107967fba78934c6
-Valid from: Mon May 18 00:00:00 GMT 1998 until: Tue Aug 01 23:59:59 GMT 2028
-Signature algorithm name: SHA1withRSA
-Subject Public Key Algorithm: 1024-bit RSA key
-Version: 1
------BEGIN CERTIFICATE-----
-MIIDAjCCAmsCEH3Z/gfPqB63EHln+6eJNMYwDQYJKoZIhvcNAQEFBQAwgcExCzAJ
-BgNVBAYTAlVTMRcwFQYDVQQKEw5WZXJpU2lnbiwgSW5jLjE8MDoGA1UECxMzQ2xh
-c3MgMyBQdWJsaWMgUHJpbWFyeSBDZXJ0aWZpY2F0aW9uIEF1dGhvcml0eSAtIEcy
-MTowOAYDVQQLEzEoYykgMTk5OCBWZXJpU2lnbiwgSW5jLiAtIEZvciBhdXRob3Jp
-emVkIHVzZSBvbmx5MR8wHQYDVQQLExZWZXJpU2lnbiBUcnVzdCBOZXR3b3JrMB4X
-DTk4MDUxODAwMDAwMFoXDTI4MDgwMTIzNTk1OVowgcExCzAJBgNVBAYTAlVTMRcw
-FQYDVQQKEw5WZXJpU2lnbiwgSW5jLjE8MDoGA1UECxMzQ2xhc3MgMyBQdWJsaWMg
-UHJpbWFyeSBDZXJ0aWZpY2F0aW9uIEF1dGhvcml0eSAtIEcyMTowOAYDVQQLEzEo
-YykgMTk5OCBWZXJpU2lnbiwgSW5jLiAtIEZvciBhdXRob3JpemVkIHVzZSBvbmx5
-MR8wHQYDVQQLExZWZXJpU2lnbiBUcnVzdCBOZXR3b3JrMIGfMA0GCSqGSIb3DQEB
-AQUAA4GNADCBiQKBgQDMXtERXVxp0KvTuWpMmR9ZmDCOFoUgRm1HP9SFIIThbbP4
-pO0M8RcPO/mn+SXXwc+EY/J8Y8+iR/LGWzOOZEAEaMGAuWQcRXfH2G71lSk8UOg0
-13gfqLptQ5GVj0VXXn7F+8qkBOvqlzdUMG+7AUcyM83cV5tkaWH4mx0ciU9cZwID
-AQABMA0GCSqGSIb3DQEBBQUAA4GBAFFNzb5cy5gZnBWyATl4Lk0PZ3BwmcYQWpSk
-U01UbSuvDV1Ai2TT1+7eVmGSX6bEHRBhNtMsJzzoKQm5EWR0zLVznxxIqbxhAe7i
-F6YM40AIOw7n60RzKprxaZLvcRTDOaxxp5EJb+RxBrO6WVcmeQD2+A2iMzAo1KpY
-oJ2daZH9
------END CERTIFICATE-----
diff -Nru openjdk-lts-11.0.11+9/make/data/cacerts/verisigntsaca openjdk-lts-11.0.14+9/make/data/cacerts/verisigntsaca
--- openjdk-lts-11.0.11+9/make/data/cacerts/verisigntsaca 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/make/data/cacerts/verisigntsaca 1970-01-01 00:00:00.000000000 +0000
@@ -1,24 +0,0 @@
-Owner: CN=Thawte Timestamping CA, OU=Thawte Certification, O=Thawte, L=Durbanville, ST=Western Cape, C=ZA
-Issuer: CN=Thawte Timestamping CA, OU=Thawte Certification, O=Thawte, L=Durbanville, ST=Western Cape, C=ZA
-Serial number: 67c8e1e8e3be1cbdfc913b8ea6238749
-Valid from: Wed Jan 01 00:00:00 GMT 1997 until: Fri Jan 01 23:59:59 GMT 2021
-Signature algorithm name: SHA1withRSA
-Subject Public Key Algorithm: 1024-bit RSA key
-Version: 3
------BEGIN CERTIFICATE-----
-MIICsDCCAhmgAwIBAgIQZ8jh6OO+HL38kTuOpiOHSTANBgkqhkiG9w0BAQUFADCB
-izELMAkGA1UEBhMCWkExFTATBgNVBAgTDFdlc3Rlcm4gQ2FwZTEUMBIGA1UEBxML
-RHVyYmFudmlsbGUxDzANBgNVBAoTBlRoYXd0ZTEdMBsGA1UECxMUVGhhd3RlIENl
-cnRpZmljYXRpb24xHzAdBgNVBAMTFlRoYXd0ZSBUaW1lc3RhbXBpbmcgQ0EwHhcN
-OTcwMTAxMDAwMDAwWhcNMjEwMTAxMjM1OTU5WjCBizELMAkGA1UEBhMCWkExFTAT
-BgNVBAgTDFdlc3Rlcm4gQ2FwZTEUMBIGA1UEBxMLRHVyYmFudmlsbGUxDzANBgNV
-BAoTBlRoYXd0ZTEdMBsGA1UECxMUVGhhd3RlIENlcnRpZmljYXRpb24xHzAdBgNV
-BAMTFlRoYXd0ZSBUaW1lc3RhbXBpbmcgQ0EwgZ8wDQYJKoZIhvcNAQEBBQADgY0A
-MIGJAoGBANYrWHhhRYZT6jR7UZztsOYuGA7+4F+oJ9O0yeB8WU4WDnNUYMF/9p8u
-6TqFJBU820cEY8OexJQaWt9MevPZQx08EHp5JduQ/vBR5zDWQQD9nyjfeb6Uu522
-FOMjhdepQeBMpHmwKxqL8vg7ij5FrHGSALSQQZj7X+36ty6K+Ig3AgMBAAGjEzAR
-MA8GA1UdEwEB/wQFMAMBAf8wDQYJKoZIhvcNAQEFBQADgYEAS+mqF4EF+3kKMZ/F
-QfRWVKvpwuWXjhj+kckMPiZkyaFMJ2SnvQGTVXFuF0853BvcSTUQOSP/ypvIz2Y/
-3Ewa1IEGQlIf4SaxFhe65nByMUToTo1b5NP50OOPJWQx5yr4GIg2GlLFDUE1G2m3
-JvUXzMEZXkt8XOKDgJH6L/uatxY=
------END CERTIFICATE-----
diff -Nru openjdk-lts-11.0.11+9/make/data/charsetmapping/SingleByte-X.java.template openjdk-lts-11.0.14+9/make/data/charsetmapping/SingleByte-X.java.template
--- openjdk-lts-11.0.11+9/make/data/charsetmapping/SingleByte-X.java.template 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/make/data/charsetmapping/SingleByte-X.java.template 2022-01-13 21:56:25.000000000 +0000
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2008, 2013, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2008, 2019, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@@ -48,7 +48,7 @@
}
public CharsetDecoder newDecoder() {
- return new SingleByte.Decoder(this, b2c, $ASCIICOMPATIBLE$);
+ return new SingleByte.Decoder(this, b2c, $ASCIICOMPATIBLE$, $LATIN1DECODABLE$);
}
public CharsetEncoder newEncoder() {
diff -Nru openjdk-lts-11.0.11+9/make/data/lsrdata/language-subtag-registry.txt openjdk-lts-11.0.14+9/make/data/lsrdata/language-subtag-registry.txt
--- openjdk-lts-11.0.11+9/make/data/lsrdata/language-subtag-registry.txt 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/make/data/lsrdata/language-subtag-registry.txt 2022-01-13 21:56:25.000000000 +0000
@@ -1,4 +1,4 @@
-File-Date: 2019-09-16
+File-Date: 2020-09-29
%%
Type: language
Subtag: aa
@@ -1530,7 +1530,7 @@
%%
Type: language
Subtag: adb
-Description: Adabe
+Description: Atauran
Added: 2009-07-29
%%
Type: language
@@ -2707,6 +2707,7 @@
Subtag: aoh
Description: Arma
Added: 2009-07-29
+Deprecated: 2020-03-28
%%
Type: language
Subtag: aoi
@@ -3770,6 +3771,7 @@
Subtag: ayy
Description: Tayabas Ayta
Added: 2009-07-29
+Deprecated: 2020-03-28
%%
Type: language
Subtag: ayz
@@ -4085,6 +4087,7 @@
Subtag: bbz
Description: Babalia Creole Arabic
Added: 2009-07-29
+Deprecated: 2020-03-28
Macrolanguage: ar
%%
Type: language
@@ -5755,6 +5758,7 @@
Subtag: bpb
Description: Barbacoas
Added: 2009-07-29
+Deprecated: 2020-03-28
%%
Type: language
Subtag: bpd
@@ -6011,7 +6015,7 @@
%%
Type: language
Subtag: brf
-Description: Bera
+Description: Bira
Added: 2009-07-29
%%
Type: language
@@ -7374,6 +7378,7 @@
Subtag: cca
Description: Cauca
Added: 2009-07-29
+Deprecated: 2020-03-28
%%
Type: language
Subtag: ccc
@@ -7480,6 +7485,7 @@
Subtag: cdg
Description: Chamari
Added: 2009-07-29
+Deprecated: 2020-03-28
%%
Type: language
Subtag: cdh
@@ -7875,6 +7881,11 @@
Added: 2009-07-29
%%
Type: language
+Subtag: ckm
+Description: Chakavian
+Added: 2020-03-28
+%%
+Type: language
Subtag: ckn
Description: Kaang Chin
Added: 2013-09-10
@@ -8121,6 +8132,13 @@
Added: 2009-07-29
%%
Type: language
+Subtag: cnp
+Description: Northern Ping Chinese
+Description: Northern Pinghua
+Added: 2020-03-28
+Macrolanguage: zh
+%%
+Type: language
Subtag: cnr
Description: Montenegrin
Added: 2018-01-23
@@ -8564,6 +8582,13 @@
Added: 2009-07-29
%%
Type: language
+Subtag: csp
+Description: Southern Ping Chinese
+Description: Southern Pinghua
+Added: 2020-03-28
+Macrolanguage: zh
+%%
+Type: language
Subtag: csq
Description: Croatia Sign Language
Added: 2009-07-29
@@ -9318,6 +9343,7 @@
Type: language
Subtag: dgr
Description: Dogrib
+Description: Tłı̨chǫ
Added: 2005-10-16
%%
Type: language
@@ -9334,6 +9360,7 @@
Subtag: dgu
Description: Degaru
Added: 2009-07-29
+Deprecated: 2020-03-28
%%
Type: language
Subtag: dgw
@@ -9720,6 +9747,11 @@
Added: 2009-07-29
%%
Type: language
+Subtag: dmf
+Description: Medefaidrin
+Added: 2020-03-28
+%%
+Type: language
Subtag: dmg
Description: Upper Kinabatangan
Added: 2009-07-29
@@ -10041,6 +10073,8 @@
Subtag: drr
Description: Dororo
Added: 2009-07-29
+Deprecated: 2020-03-28
+Preferred-Value: kzk
%%
Type: language
Subtag: drs
@@ -10330,6 +10364,11 @@
Added: 2009-07-29
%%
Type: language
+Subtag: dwk
+Description: Dawik Kui
+Added: 2020-03-28
+%%
+Type: language
Subtag: dwl
Description: Walo Kumbe Dogon
Added: 2009-07-29
@@ -10455,6 +10494,11 @@
Added: 2013-09-10
%%
Type: language
+Subtag: ebc
+Description: Beginci
+Added: 2020-03-28
+%%
+Type: language
Subtag: ebg
Description: Ebughu
Added: 2009-07-29
@@ -10576,6 +10620,7 @@
Subtag: ekc
Description: Eastern Karnic
Added: 2013-09-10
+Deprecated: 2020-03-28
%%
Type: language
Subtag: eke
@@ -11215,6 +11260,11 @@
Added: 2009-07-29
%%
Type: language
+Subtag: fif
+Description: Faifi
+Added: 2020-06-08
+%%
+Type: language
Subtag: fil
Description: Filipino
Description: Pilipino
@@ -11881,6 +11931,7 @@
Type: language
Subtag: gdh
Description: Gadjerawang
+Description: Gajirrabeng
Added: 2009-07-29
%%
Type: language
@@ -11970,6 +12021,11 @@
Added: 2009-07-29
%%
Type: language
+Subtag: gef
+Description: Gerai
+Added: 2020-03-28
+%%
+Type: language
Subtag: geg
Description: Gengle
Added: 2009-07-29
@@ -12381,6 +12437,8 @@
Subtag: gli
Description: Guliguli
Added: 2009-07-29
+Deprecated: 2020-03-28
+Preferred-Value: kzk
%%
Type: language
Subtag: glj
@@ -12476,6 +12534,12 @@
Scope: collection
%%
Type: language
+Subtag: gmr
+Description: Mirning
+Description: Mirniny
+Added: 2020-03-28
+%%
+Type: language
Subtag: gmu
Description: Gumalu
Added: 2009-07-29
@@ -13155,6 +13219,7 @@
%%
Type: language
Subtag: gwc
+Description: Gawri
Description: Kalami
Added: 2009-07-29
%%
@@ -13859,6 +13924,11 @@
Added: 2009-07-29
%%
Type: language
+Subtag: hng
+Description: Hungu
+Added: 2020-03-28
+%%
+Type: language
Subtag: hnh
Description: ǁAni
Added: 2009-07-29
@@ -14140,6 +14210,7 @@
Type: language
Subtag: huc
Description: ǂHua
+Description: ǂʼAmkhoe
Added: 2009-07-29
%%
Type: language
@@ -15910,6 +15981,7 @@
Type: language
Subtag: kaa
Description: Kara-Kalpak
+Description: Karakalpak
Added: 2005-10-16
%%
Type: language
@@ -17067,8 +17139,9 @@
%%
Type: language
Subtag: kjf
-Description: Khalaj
+Description: Khalaj [Indo-Iranian]
Added: 2009-07-29
+Deprecated: 2020-03-28
%%
Type: language
Subtag: kjg
@@ -17248,7 +17321,7 @@
%%
Type: language
Subtag: kkq
-Description: Kaiku
+Description: Kaeku
Added: 2009-07-29
%%
Type: language
@@ -17344,7 +17417,7 @@
%%
Type: language
Subtag: klj
-Description: Turkic Khalaj
+Description: Khalaj
Added: 2009-07-29
%%
Type: language
@@ -18497,6 +18570,7 @@
Type: language
Subtag: kui
Description: Kuikúro-Kalapálo
+Description: Kalapalo
Added: 2009-07-29
%%
Type: language
@@ -18908,6 +18982,8 @@
Subtag: kxl
Description: Nepali Kurux
Added: 2009-07-29
+Deprecated: 2020-03-28
+Preferred-Value: kru
%%
Type: language
Subtag: kxm
@@ -18953,6 +19029,8 @@
Subtag: kxu
Description: Kui (India)
Added: 2009-07-29
+Deprecated: 2020-03-28
+Comments: see dwk, uki
%%
Type: language
Subtag: kxv
@@ -20337,6 +20415,7 @@
Subtag: lmz
Description: Lumbee
Added: 2009-07-29
+Deprecated: 2020-03-28
%%
Type: language
Subtag: lna
@@ -22788,6 +22867,7 @@
%%
Type: language
Subtag: moe
+Description: Innu
Description: Montagnais
Added: 2009-07-29
%%
@@ -26199,6 +26279,11 @@
Added: 2009-07-29
%%
Type: language
+Subtag: nsb
+Description: Lower Nossob
+Added: 2020-03-28
+%%
+Type: language
Subtag: nsc
Description: Nshi
Added: 2009-07-29
@@ -26667,6 +26752,8 @@
Subtag: nxu
Description: Narau
Added: 2009-07-29
+Deprecated: 2020-03-28
+Preferred-Value: bpp
%%
Type: language
Subtag: nxx
@@ -28166,7 +28253,7 @@
%%
Type: language
Subtag: pfe
-Description: Peere
+Description: Pere
Added: 2009-07-29
%%
Type: language
@@ -28572,6 +28659,7 @@
Subtag: plp
Description: Palpa
Added: 2009-07-29
+Deprecated: 2020-03-28
%%
Type: language
Subtag: plq
@@ -31132,6 +31220,8 @@
Subtag: sdm
Description: Semandang
Added: 2009-07-29
+Deprecated: 2020-03-28
+Comments: see ebc, gef, sdq
%%
Type: language
Subtag: sdn
@@ -31150,6 +31240,11 @@
Added: 2009-07-29
%%
Type: language
+Subtag: sdq
+Description: Semandang
+Added: 2020-03-28
+%%
+Type: language
Subtag: sdr
Description: Oraon Sadri
Added: 2009-07-29
@@ -33502,6 +33597,7 @@
Subtag: tbb
Description: Tapeba
Added: 2009-07-29
+Deprecated: 2020-03-28
%%
Type: language
Subtag: tbc
@@ -34219,6 +34315,8 @@
Subtag: thw
Description: Thudam
Added: 2009-07-29
+Deprecated: 2020-06-08
+Preferred-Value: ola
%%
Type: language
Subtag: thx
@@ -36240,6 +36338,11 @@
Added: 2009-07-29
%%
Type: language
+Subtag: uki
+Description: Kui (India)
+Added: 2020-03-28
+%%
+Type: language
Subtag: ukk
Description: Muak Sa-aak
Added: 2017-02-23
@@ -36271,6 +36374,11 @@
Added: 2009-07-29
%%
Type: language
+Subtag: ukv
+Description: Kuku
+Added: 2020-03-28
+%%
+Type: language
Subtag: ukw
Description: Ukwuani-Aboh-Ndoni
Added: 2009-07-29
@@ -37760,6 +37868,11 @@
Added: 2009-07-29
%%
Type: language
+Subtag: wlh
+Description: Welaun
+Added: 2020-03-28
+%%
+Type: language
Subtag: wli
Description: Waioli
Added: 2009-07-29
@@ -39232,6 +39345,11 @@
Added: 2013-09-10
%%
Type: language
+Subtag: xnm
+Description: Ngumbarl
+Added: 2020-03-28
+%%
+Type: language
Subtag: xnn
Description: Northern Kankanay
Added: 2009-07-29
@@ -39334,22 +39452,45 @@
Added: 2013-09-10
%%
Type: language
+Subtag: xpb
+Description: Northeastern Tasmanian
+Description: Pyemmairrener
+Added: 2020-03-28
+%%
+Type: language
Subtag: xpc
Description: Pecheneg
Added: 2009-07-29
%%
Type: language
+Subtag: xpd
+Description: Oyster Bay Tasmanian
+Added: 2020-03-28
+%%
+Type: language
Subtag: xpe
Description: Liberia Kpelle
Added: 2009-07-29
Macrolanguage: kpe
%%
Type: language
+Subtag: xpf
+Description: Southeast Tasmanian
+Description: Nuenonne
+Added: 2020-03-28
+%%
+Type: language
Subtag: xpg
Description: Phrygian
Added: 2009-07-29
%%
Type: language
+Subtag: xph
+Description: North Midlands Tasmanian
+Description: Tyerrenoterpanner
+Added: 2020-03-28
+%%
+Type: language
Subtag: xpi
Description: Pictish
Added: 2009-07-29
@@ -39365,6 +39506,11 @@
Added: 2009-07-29
%%
Type: language
+Subtag: xpl
+Description: Port Sorell Tasmanian
+Added: 2020-03-28
+%%
+Type: language
Subtag: xpm
Description: Pumpokol
Added: 2009-07-29
@@ -39410,11 +39556,34 @@
Added: 2009-07-29
%%
Type: language
+Subtag: xpv
+Description: Northern Tasmanian
+Description: Tommeginne
+Added: 2020-03-28
+%%
+Type: language
+Subtag: xpw
+Description: Northwestern Tasmanian
+Description: Peerapper
+Added: 2020-03-28
+%%
+Type: language
+Subtag: xpx
+Description: Southwestern Tasmanian
+Description: Toogee
+Added: 2020-03-28
+%%
+Type: language
Subtag: xpy
Description: Puyo
Added: 2009-07-29
%%
Type: language
+Subtag: xpz
+Description: Bruny Island Tasmanian
+Added: 2020-03-28
+%%
+Type: language
Subtag: xqa
Description: Karakhanid
Added: 2009-07-29
@@ -39468,6 +39637,8 @@
Subtag: xrq
Description: Karranga
Added: 2013-09-10
+Deprecated: 2020-03-28
+Preferred-Value: dmw
%%
Type: language
Subtag: xrr
@@ -39700,6 +39871,8 @@
Subtag: xtz
Description: Tasmanian
Added: 2009-07-29
+Deprecated: 2020-03-28
+Comments: see xpb, xpd, xpf, xph, xpl, xpv, xpw, xpx, xpz
%%
Type: language
Subtag: xua
@@ -39729,6 +39902,7 @@
Type: language
Subtag: xul
Description: Ngunawal
+Description: Nunukul
Added: 2013-09-10
%%
Type: language
@@ -41321,6 +41495,11 @@
Added: 2009-07-29
%%
Type: language
+Subtag: zba
+Description: Balaibalan
+Added: 2020-03-28
+%%
+Type: language
Subtag: zbc
Description: Central Berawan
Added: 2009-07-29
@@ -41486,6 +41665,8 @@
Subtag: zir
Description: Ziriya
Added: 2009-07-29
+Deprecated: 2020-03-28
+Preferred-Value: scv
%%
Type: language
Subtag: ziw
@@ -42463,6 +42644,7 @@
Subtag: bbz
Description: Babalia Creole Arabic
Added: 2009-07-29
+Deprecated: 2020-03-28
Preferred-Value: bbz
Prefix: ar
Macrolanguage: ar
@@ -42580,6 +42762,15 @@
Macrolanguage: zh
%%
Type: extlang
+Subtag: cnp
+Description: Northern Ping Chinese
+Description: Northern Pinghua
+Added: 2020-03-28
+Preferred-Value: cnp
+Prefix: zh
+Macrolanguage: zh
+%%
+Type: extlang
Subtag: coa
Description: Cocos Islands Malay
Added: 2009-07-29
@@ -42647,6 +42838,15 @@
Prefix: sgn
%%
Type: extlang
+Subtag: csp
+Description: Southern Ping Chinese
+Description: Southern Pinghua
+Added: 2020-03-28
+Preferred-Value: csp
+Prefix: zh
+Macrolanguage: zh
+%%
+Type: extlang
Subtag: csq
Description: Croatia Sign Language
Added: 2009-07-29
@@ -44928,6 +45128,11 @@
Added: 2011-08-16
%%
Type: script
+Subtag: Toto
+Description: Toto
+Added: 2020-05-12
+%%
+Type: script
Subtag: Ugar
Description: Ugaritic
Added: 2005-10-16
@@ -46630,6 +46835,12 @@
Letras in 1943 and generally used in Brazil until 2009
%%
Type: variant
+Subtag: akuapem
+Description: Akuapem Twi
+Added: 2017-06-05
+Prefix: tw
+%%
+Type: variant
Subtag: alalc97
Description: ALA-LC Romanization, 1997 edition
Added: 2009-12-09
@@ -46648,12 +46859,6 @@
continuum in Eastern Suriname and Western French Guiana
%%
Type: variant
-Subtag: akuapem
-Description: Akuapem Twi
-Added: 2017-06-05
-Prefix: tw
-%%
-Type: variant
Subtag: ao1990
Description: Portuguese Language Orthographic Agreement of 1990 (Acordo
Ortográfico da Língua Portuguesa de 1990)
@@ -47129,6 +47334,16 @@
Creole continuum in Eastern Suriname and Western French Guiana
%%
Type: variant
+Subtag: peano
+Description: Latino Sine Flexione
+Description: Interlingua de API
+Description: Interlingua de Peano
+Prefix: la
+Comments: Peano’s Interlingua, created in 1903 by Giuseppe Peano as an
+ international auxiliary language
+Added: 2020-03-12
+%%
+Type: variant
Subtag: petr1708
Description: Petrine orthography
Added: 2010-10-10
@@ -47266,6 +47481,23 @@
Miensk 2005).
%%
Type: variant
+Subtag: tongyong
+Description: Tongyong Pinyin romanization
+Added: 2020-06-08
+Prefix: zh-Latn
+Comments: Former official transcription standard for Mandarin Chinese in
+ Taiwan.
+%%
+Type: variant
+Subtag: tunumiit
+Description: Tunumiisiut
+Description: East Greenlandic
+Description: Østgrønlandsk
+Added: 2020-07-16
+Prefix: kl
+Comments: Also known as Tunumiit oraasiat
+%%
+Type: variant
Subtag: uccor
Description: Unified Cornish orthography of Revived Cornish
Added: 2008-10-14
@@ -47318,6 +47550,14 @@
"idioms" of the Romansh language.
%%
Type: variant
+Subtag: vecdruka
+Description: Latvian orthography used before 1920s ("vecā druka")
+Added: 2020-09-26
+Prefix: lv
+Comments: The subtag represents the old orthography of the Latvian
+ language used during c. 1600s–1920s.
+%%
+Type: variant
Subtag: vivaraup
Description: Vivaro-Alpine
Added: 2018-04-22
diff -Nru openjdk-lts-11.0.11+9/make/data/tzdata/africa openjdk-lts-11.0.14+9/make/data/tzdata/africa
--- openjdk-lts-11.0.11+9/make/data/tzdata/africa 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/make/data/tzdata/africa 2022-01-13 21:56:25.000000000 +0000
@@ -53,9 +53,6 @@
# Milne J. Civil time. Geogr J. 1899 Feb;13(2):173-94.
# https://www.jstor.org/stable/1774359
#
-# A reliable and entertaining source about time zones is
-# Derek Howse, Greenwich time and longitude, Philip Wilson Publishers (1997).
-#
# European-style abbreviations are commonly used along the Mediterranean.
# For sub-Saharan Africa abbreviations were less standardized.
# Previous editions of this database used WAT, CAT, SAT, and EAT
@@ -176,8 +173,9 @@
# Zone NAME STDOFF RULES FORMAT [UNTIL]
Zone Africa/Abidjan -0:16:08 - LMT 1912
0:00 - GMT
+Link Africa/Abidjan Africa/Accra # Ghana
Link Africa/Abidjan Africa/Bamako # Mali
-Link Africa/Abidjan Africa/Banjul # Gambia
+Link Africa/Abidjan Africa/Banjul # The Gambia
Link Africa/Abidjan Africa/Conakry # Guinea
Link Africa/Abidjan Africa/Dakar # Senegal
Link Africa/Abidjan Africa/Freetown # Sierra Leone
@@ -404,93 +402,8 @@
# Gabon
# See Africa/Lagos.
-# Gambia
-# See Africa/Abidjan.
-
+# The Gambia
# Ghana
-
-# From P Chan (2020-11-20):
-# Interpretation Amendment Ordinance, 1915 (No.24 of 1915) [1915-11-02]
-# Ordinances of the Gold Coast, Ashanti, Northern Territories 1915, p 69-71
-# https://books.google.com/books?id=ErA-AQAAIAAJ&pg=PA70
-# This Ordinance added "'Time' shall mean Greenwich Mean Time" to the
-# Interpretation Ordinance, 1876.
-#
-# Determination of the Time Ordinance, 1919 (No. 18 of 1919) [1919-11-24]
-# Ordinances of the Gold Coast, Ashanti, Northern Territories 1919, p 75-76
-# https://books.google.com/books?id=MbA-AQAAIAAJ&pg=PA75
-# This Ordinance removed the previous definition of time and introduced DST.
-#
-# Time Determination Ordinance (Cap. 214)
-# The Laws of the Gold Coast (including Togoland Under British Mandate)
-# Vol. II (1937), p 2328
-# https://books.google.com/books?id=Z7M-AQAAIAAJ&pg=PA2328
-# Revised edition of the 1919 Ordinance.
-#
-# Time Determination (Amendment) Ordinance, 1940 (No. 9 of 1940) [1940-04-06]
-# Annual Volume of the Laws of the Gold Coast:
-# Containing All Legislation Enacted During Year 1940, p 22
-# https://books.google.com/books?id=1ao-AQAAIAAJ&pg=PA22
-# This Ordinance changed the forward transition from September to May.
-#
-# Defence (Time Determination Ordinance Amendment) Regulations, 1942
-# (Regulations No. 6 of 1942) [1942-01-31, commenced on 1942-02-08]
-# Annual Volume of the Laws of the Gold Coast:
-# Containing All Legislation Enacted During Year 1942, p 48
-# https://books.google.com/books?id=Das-AQAAIAAJ&pg=PA48
-# These regulations advanced the [standard] time by thirty minutes.
-#
-# Defence (Time Determination Ordinance Amendment (No.2)) Regulations,
-# 1942 (Regulations No. 28 of 1942) [1942-04-25]
-# Annual Volume of the Laws of the Gold Coast:
-# Containing All Legislation Enacted During Year 1942, p 87
-# https://books.google.com/books?id=Das-AQAAIAAJ&pg=PA87
-# These regulations abolished DST and changed the time to GMT+0:30.
-#
-# Defence (Revocation) (No.4) Regulations, 1945 (Regulations No. 45 of
-# 1945) [1945-10-24, commenced on 1946-01-06]
-# Annual Volume of the Laws of the Gold Coast:
-# Containing All Legislation Enacted During Year 1945, p 256
-# https://books.google.com/books?id=9as-AQAAIAAJ&pg=PA256
-# These regulations revoked the previous two sets of Regulations.
-#
-# Time Determination (Amendment) Ordinance, 1945 (No. 18 of 1945) [1946-01-06]
-# Annual Volume of the Laws of the Gold Coast:
-# Containing All Legislation Enacted During Year 1945, p 69
-# https://books.google.com/books?id=9as-AQAAIAAJ&pg=PA69
-# This Ordinance abolished DST.
-#
-# Time Determination (Amendment) Ordinance, 1950 (No. 26 of 1950) [1950-07-22]
-# Annual Volume of the Laws of the Gold Coast:
-# Containing All Legislation Enacted During Year 1950, p 35
-# https://books.google.com/books?id=e60-AQAAIAAJ&pg=PA35
-# This Ordinance restored DST but with thirty minutes offset.
-#
-# Time Determination Ordinance (Cap. 264)
-# The Laws of the Gold Coast, Vol. V (1954), p 380
-# https://books.google.com/books?id=Mqc-AQAAIAAJ&pg=PA380
-# Revised edition of the Time Determination Ordinance.
-#
-# Time Determination (Amendment) Ordinance, 1956 (No. 21 of 1956) [1956-08-29]
-# Annual Volume of the Ordinances of the Gold Coast Enacted During the
-# Year 1956, p 83
-# https://books.google.com/books?id=VLE-AQAAIAAJ&pg=PA83
-# This Ordinance abolished DST.
-
-# Rule NAME FROM TO - IN ON AT SAVE LETTER/S
-Rule Ghana 1919 only - Nov 24 0:00 0:20 +0020
-Rule Ghana 1920 1942 - Jan 1 2:00 0 GMT
-Rule Ghana 1920 1939 - Sep 1 2:00 0:20 +0020
-Rule Ghana 1940 1941 - May 1 2:00 0:20 +0020
-Rule Ghana 1950 1955 - Sep 1 2:00 0:30 +0030
-Rule Ghana 1951 1956 - Jan 1 2:00 0 GMT
-
-# Zone NAME STDOFF RULES FORMAT [UNTIL]
-Zone Africa/Accra -0:00:52 - LMT 1915 Nov 2
- 0:00 Ghana %s 1942 Feb 8
- 0:30 - +0030 1946 Jan 6
- 0:00 Ghana %s
-
# Guinea
# See Africa/Abidjan.
@@ -755,7 +668,7 @@
# See Africa/Nairobi.
# Morocco
-# See the 'europe' file for Spanish Morocco (Africa/Ceuta).
+# See Africa/Ceuta for Spanish Morocco.
# From Alex Krivenyshev (2008-05-09):
# Here is an article that Morocco plan to introduce Daylight Saving Time between
@@ -1405,23 +1318,21 @@
0:13:35 - LMT 1914 Jan 1
0:30 - +0030 1919 Sep 1
1:00 - WAT
-Link Africa/Lagos Africa/Bangui # Central African Republic
-Link Africa/Lagos Africa/Brazzaville # Rep. of the Congo
-Link Africa/Lagos Africa/Douala # Cameroon
-Link Africa/Lagos Africa/Kinshasa # Dem. Rep. of the Congo (west)
-Link Africa/Lagos Africa/Libreville # Gabon
-Link Africa/Lagos Africa/Luanda # Angola
-Link Africa/Lagos Africa/Malabo # Equatorial Guinea
-Link Africa/Lagos Africa/Niamey # Niger
-Link Africa/Lagos Africa/Porto-Novo # Benin
+Link Africa/Lagos Africa/Bangui # Central African Republic
+Link Africa/Lagos Africa/Brazzaville # Rep. of the Congo
+Link Africa/Lagos Africa/Douala # Cameroon
+Link Africa/Lagos Africa/Kinshasa # Dem. Rep. of the Congo (west)
+Link Africa/Lagos Africa/Libreville # Gabon
+Link Africa/Lagos Africa/Luanda # Angola
+Link Africa/Lagos Africa/Malabo # Equatorial Guinea
+Link Africa/Lagos Africa/Niamey # Niger
+Link Africa/Lagos Africa/Porto-Novo # Benin
# Réunion
# Zone NAME STDOFF RULES FORMAT [UNTIL]
Zone Indian/Reunion 3:41:52 - LMT 1911 Jun # Saint-Denis
4:00 - +04
#
-# Crozet Islands also observes Réunion time; see the 'antarctica' file.
-#
# Scattered Islands (Îles Éparses) administered from Réunion are as follows.
# The following information about them is taken from
# Îles Éparses (, 1997-07-22,
@@ -1513,8 +1424,8 @@
Zone Africa/Johannesburg 1:52:00 - LMT 1892 Feb 8
1:30 - SAST 1903 Mar
2:00 SA SAST
-Link Africa/Johannesburg Africa/Maseru # Lesotho
-Link Africa/Johannesburg Africa/Mbabane # Eswatini
+Link Africa/Johannesburg Africa/Maseru # Lesotho
+Link Africa/Johannesburg Africa/Mbabane # Eswatini
#
# Marion and Prince Edward Is
# scientific station since 1947
@@ -1550,12 +1461,13 @@
3:00 - EAT 2017 Nov 1
2:00 - CAT
+# South Sudan
+
# From Steffen Thorsen (2021-01-18):
# "South Sudan will change its time zone by setting the clock back 1
# hour on February 1, 2021...."
# from https://eyeradio.org/south-sudan-adopts-new-time-zone-makuei/
-# South Sudan
# Zone NAME STDOFF RULES FORMAT [UNTIL]
Zone Africa/Juba 2:06:28 - LMT 1931
2:00 Sudan CA%sT 2000 Jan 15 12:00
@@ -1660,7 +1572,7 @@
Rule Tunisia 2006 2008 - Mar lastSun 2:00s 1:00 S
Rule Tunisia 2006 2008 - Oct lastSun 2:00s 0 -
-# See Europe/Paris for PMT-related transitions.
+# See Europe/Paris commentary for PMT-related transitions.
# Zone NAME STDOFF RULES FORMAT [UNTIL]
Zone Africa/Tunis 0:40:44 - LMT 1881 May 12
0:09:21 - PMT 1911 Mar 11 # Paris Mean Time
diff -Nru openjdk-lts-11.0.11+9/make/data/tzdata/antarctica openjdk-lts-11.0.14+9/make/data/tzdata/antarctica
--- openjdk-lts-11.0.11+9/make/data/tzdata/antarctica 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/make/data/tzdata/antarctica 2022-01-13 21:56:25.000000000 +0000
@@ -171,7 +171,7 @@
#
# Alfred Faure, Possession Island, Crozet Islands, -462551+0515152, since 1964;
# sealing & whaling stations operated variously 1802/1911+;
-# see Indian/Reunion.
+# see Asia/Dubai.
#
# Martin-de-Viviès, Amsterdam Island, -374105+0773155, since 1950
# Port-aux-Français, Kerguelen Islands, -492110+0701303, since 1951;
@@ -185,17 +185,7 @@
5:00 - +05
#
# year-round base in the main continent
-# Dumont d'Urville, Île des Pétrels, -6640+14001, since 1956-11
-# (2005-12-05)
-#
-# Another base at Port-Martin, 50km east, began operation in 1947.
-# It was destroyed by fire on 1952-01-14.
-#
-# Zone NAME STDOFF RULES FORMAT [UNTIL]
-Zone Antarctica/DumontDUrville 0 - -00 1947
- 10:00 - +10 1952 Jan 14
- 0 - -00 1956 Nov
- 10:00 - +10
+# Dumont d'Urville - see Pacific/Port_Moresby.
# France & Italy - year-round base
# Concordia, -750600+1232000, since 2005
@@ -211,20 +201,7 @@
# Zuchelli, Terra Nova Bay, -744140+1640647, since 1986
# Japan - year-round bases
-# Syowa (also known as Showa), -690022+0393524, since 1957
-#
-# From Hideyuki Suzuki (1999-02-06):
-# In all Japanese stations, +0300 is used as the standard time.
-#
-# Syowa station, which is the first antarctic station of Japan,
-# was established on 1957-01-29. Since Syowa station is still the main
-# station of Japan, it's appropriate for the principal location.
-# Zone NAME STDOFF RULES FORMAT [UNTIL]
-Zone Antarctica/Syowa 0 - -00 1957 Jan 29
- 3:00 - +03
-# See:
-# NIPR Antarctic Research Activities (1999-08-17)
-# http://www.nipr.ac.jp/english/ara01.html
+# See Asia/Riyadh.
# S Korea - year-round base
# Jang Bogo, Terra Nova Bay, -743700+1641205 since 2014
diff -Nru openjdk-lts-11.0.11+9/make/data/tzdata/asia openjdk-lts-11.0.14+9/make/data/tzdata/asia
--- openjdk-lts-11.0.11+9/make/data/tzdata/asia 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/make/data/tzdata/asia 2022-01-13 21:56:25.000000000 +0000
@@ -57,9 +57,6 @@
# Byalokoz EL. New Counting of Time in Russia since July 1, 1919.
# (See the 'europe' file for a fuller citation.)
#
-# A reliable and entertaining source about time zones is
-# Derek Howse, Greenwich time and longitude, Philip Wilson Publishers (1997).
-#
# The following alphabetic abbreviations appear in these tables
# (corrections are welcome):
# std dst
@@ -2257,6 +2254,14 @@
# From Paul Eggert (2013-12-11):
# As Steffen suggested, consider the past 21-month experiment to be DST.
+# From Steffen Thorsen (2021-09-24):
+# The Jordanian Government announced yesterday that they will start DST
+# in February instead of March:
+# https://petra.gov.jo/Include/InnerPage.jsp?ID=37683&lang=en&name=en_news (English)
+# https://petra.gov.jo/Include/InnerPage.jsp?ID=189969&lang=ar&name=news (Arabic)
+# From the Arabic version, it seems to say it would be at midnight
+# (assume 24:00) on the last Thursday in February, starting from 2022.
+
# Rule NAME FROM TO - IN ON AT SAVE LETTER/S
Rule Jordan 1973 only - Jun 6 0:00 1:00 S
Rule Jordan 1973 1975 - Oct 1 0:00 0 -
@@ -2287,8 +2292,9 @@
Rule Jordan 2005 only - Sep lastFri 0:00s 0 -
Rule Jordan 2006 2011 - Oct lastFri 0:00s 0 -
Rule Jordan 2013 only - Dec 20 0:00 0 -
-Rule Jordan 2014 max - Mar lastThu 24:00 1:00 S
+Rule Jordan 2014 2021 - Mar lastThu 24:00 1:00 S
Rule Jordan 2014 max - Oct lastFri 0:00s 0 -
+Rule Jordan 2022 max - Feb lastThu 24:00 1:00 S
# Zone NAME STDOFF RULES FORMAT [UNTIL]
Zone Asia/Amman 2:23:44 - LMT 1931
2:00 Jordan EE%sT
@@ -2763,7 +2769,8 @@
#
# peninsular Malaysia
# taken from Mok Ly Yng (2003-10-30)
-# http://www.math.nus.edu.sg/aslaksen/teaching/timezone.html
+# https://web.archive.org/web/20190822231045/http://www.math.nus.edu.sg/~mathelmr/teaching/timezone.html
+# This agrees with Singapore since 1905-06-01.
# Zone NAME STDOFF RULES FORMAT [UNTIL]
Zone Asia/Kuala_Lumpur 6:46:46 - LMT 1901 Jan 1
6:55:25 - SMT 1905 Jun 1 # Singapore M.T.
@@ -3402,11 +3409,6 @@
# shall [end] on Oct 24th 2020 at 01:00AM by delaying the clock by 60 minutes.
# http://www.palestinecabinet.gov.ps/portal/Meeting/Details/51584
-# From Tim Parenti (2020-10-20):
-# Predict future fall transitions at 01:00 on the Saturday preceding October's
-# last Sunday (i.e., Sat>=24). This is consistent with our predictions since
-# 2016, although the time of the change differed slightly in 2019.
-
# From Pierre Cashon (2020-10-20):
# The summer time this year started on March 28 at 00:00.
# https://wafa.ps/ar_page.aspx?id=GveQNZa872839351758aGveQNZ
@@ -3419,6 +3421,17 @@
# For now, guess spring-ahead transitions are at 00:00 on the Saturday
# preceding March's last Sunday (i.e., Sat>=24).
+# From P Chan (2021-10-18):
+# http://wafa.ps/Pages/Details/34701
+# Palestine winter time will start from midnight 2021-10-29 (Thursday-Friday).
+#
+# From Heba Hemad, Palestine Ministry of Telecom & IT (2021-10-20):
+# ... winter time will begin in Palestine from Friday 10-29, 01:00 AM
+# by 60 minutes backwards.
+#
+# From Paul Eggert (2021-10-20):
+# Guess future fall transitions on October's last Friday at 01:00.
+
# Rule NAME FROM TO - IN ON AT SAVE LETTER/S
Rule EgyptAsia 1957 only - May 10 0:00 1:00 S
Rule EgyptAsia 1957 1958 - Oct 1 0:00 0 -
@@ -3454,7 +3467,8 @@
Rule Palestine 2019 only - Mar 29 0:00 1:00 S
Rule Palestine 2019 only - Oct Sat>=24 0:00 0 -
Rule Palestine 2020 max - Mar Sat>=24 0:00 1:00 S
-Rule Palestine 2020 max - Oct Sat>=24 1:00 0 -
+Rule Palestine 2020 only - Oct 24 1:00 0 -
+Rule Palestine 2021 max - Oct lastFri 1:00 0 -
# Zone NAME STDOFF RULES FORMAT [UNTIL]
Zone Asia/Gaza 2:17:52 - LMT 1900 Oct
@@ -3523,6 +3537,12 @@
# influence of the sources. There is no current abbreviation for DST,
# so use "PDT", the usual American style.
+# From P Chan (2021-05-10):
+# Here's a fairly comprehensive article in Japanese:
+# https://wiki.suikawiki.org/n/Philippine%20Time
+# From Paul Eggert (2021-05-10):
+# The info in the Japanese table has not been absorbed (yet) below.
+
# Rule NAME FROM TO - IN ON AT SAVE LETTER/S
Rule Phil 1936 only - Nov 1 0:00 1:00 D
Rule Phil 1937 only - Feb 1 0:00 0 S
@@ -3589,12 +3609,13 @@
# Zone NAME STDOFF RULES FORMAT [UNTIL]
Zone Asia/Riyadh 3:06:52 - LMT 1947 Mar 14
3:00 - +03
+Link Asia/Riyadh Antarctica/Syowa
Link Asia/Riyadh Asia/Aden # Yemen
Link Asia/Riyadh Asia/Kuwait
# Singapore
# taken from Mok Ly Yng (2003-10-30)
-# http://www.math.nus.edu.sg/aslaksen/teaching/timezone.html
+# https://web.archive.org/web/20190822231045/http://www.math.nus.edu.sg/~mathelmr/teaching/timezone.html
# Zone NAME STDOFF RULES FORMAT [UNTIL]
Zone Asia/Singapore 6:55:25 - LMT 1901 Jan 1
6:55:25 - SMT 1905 Jun 1 # Singapore M.T.
diff -Nru openjdk-lts-11.0.11+9/make/data/tzdata/australasia openjdk-lts-11.0.14+9/make/data/tzdata/australasia
--- openjdk-lts-11.0.11+9/make/data/tzdata/australasia 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/make/data/tzdata/australasia 2022-01-13 21:56:25.000000000 +0000
@@ -408,9 +408,22 @@
# "Minister for Employment, Parveen Bala says they had never thought of
# stopping daylight saving. He says it was just to decide on when it should
# start and end. Bala says it is a short period..."
-# Since the end date is still in line with our ongoing predictions, assume for
-# now that the later-than-usual start date is a one-time departure from the
-# recent second Sunday in November pattern.
+#
+# From Tim Parenti (2021-10-11), per Jashneel Kumar (2021-10-11) and P Chan
+# (2021-10-12):
+# https://www.fiji.gov.fj/Media-Centre/Speeches/English/PM-BAINIMARAMA-S-COVID-19-ANNOUNCEMENT-10-10-21
+# https://www.fbcnews.com.fj/news/covid-19/curfew-moved-back-to-11pm/
+# In a 2021-10-10 speech concerning updated Covid-19 mitigation measures in
+# Fiji, prime minister Josaia Voreqe "Frank" Bainimarama announced the
+# suspension of DST for the 2021/2022 season: "Given that we are in the process
+# of readjusting in the midst of so many changes, we will also put Daylight
+# Savings Time on hold for this year. It will also make the reopening of
+# scheduled commercial air service much smoother if we don't have to be
+# concerned shifting arrival and departure times, which may look like a simple
+# thing but requires some significant logistical adjustments domestically and
+# internationally."
+# Assume for now that DST will resume with the recent pre-2020 rules for the
+# 2022/2023 season.
# Rule NAME FROM TO - IN ON AT SAVE LETTER/S
Rule Fiji 1998 1999 - Nov Sun>=1 2:00 1:00 -
@@ -422,10 +435,11 @@
Rule Fiji 2012 2013 - Jan Sun>=18 3:00 0 -
Rule Fiji 2014 only - Jan Sun>=18 2:00 0 -
Rule Fiji 2014 2018 - Nov Sun>=1 2:00 1:00 -
-Rule Fiji 2015 max - Jan Sun>=12 3:00 0 -
+Rule Fiji 2015 2021 - Jan Sun>=12 3:00 0 -
Rule Fiji 2019 only - Nov Sun>=8 2:00 1:00 -
Rule Fiji 2020 only - Dec 20 2:00 1:00 -
-Rule Fiji 2021 max - Nov Sun>=8 2:00 1:00 -
+Rule Fiji 2022 max - Nov Sun>=8 2:00 1:00 -
+Rule Fiji 2023 max - Jan Sun>=12 3:00 0 -
# Zone NAME STDOFF RULES FORMAT [UNTIL]
Zone Pacific/Fiji 11:55:44 - LMT 1915 Oct 26 # Suva
12:00 Fiji +12/+13
@@ -487,7 +501,7 @@
# Zone NAME STDOFF RULES FORMAT [UNTIL]
Zone Pacific/Tarawa 11:32:04 - LMT 1901 # Bairiki
12:00 - +12
-Zone Pacific/Enderbury -11:24:20 - LMT 1901
+Zone Pacific/Kanton 0 - -00 1937 Aug 31
-12:00 - -12 1979 Oct
-11:00 - -11 1994 Dec 31
13:00 - +13
@@ -620,13 +634,46 @@
# was probably like Pacific/Auckland
# Cook Is
-# From Shanks & Pottenger:
+#
+# From Alexander Krivenyshev (2021-03-24):
+# In 1899 the Cook Islands celebrated Christmas twice to correct the calendar.
+# According to the old books, missionaries were unaware of
+# the International Date line, when they came from Sydney.
+# Thus the Cook Islands were one day ahead....
+# http://nzetc.victoria.ac.nz/tm/scholarly/tei-KloDisc-t1-body-d18.html
+# ... Appendix to the Journals of the House of Representatives, 1900
+# https://atojs.natlib.govt.nz/cgi-bin/atojs?a=d&d=AJHR1900-I.2.1.2.3
+# (page 20)
+#
+# From Michael Deckers (2021-03-24):
+# ... in the Cook Island Act of 1915-10-11, online at
+# http://www.paclii.org/ck/legis/ck-nz_act/cia1915132/
+# "651. The hour of the day shall in each of the islands included in the
+# Cook Islands be determined in accordance with the meridian of that island."
+# so that local (mean?) time was still used in Rarotonga (and Niue) in 1915.
+# This was changed in the Cook Island Amendment Act of 1952-10-16 ...
+# http://www.paclii.org/ck/legis/ck-nz_act/ciaa1952212/
+# "651 (1) The hour of the day in each of the islands included in the Cook
+# Islands, other than Niue, shall be determined as if each island were
+# situated on the meridian one hundred and fifty-seven degrees thirty minutes
+# West of Greenwich. (2) The hour of the day in the Island of Niue shall be
+# determined as if that island were situated on the meridian one hundred and
+# seventy degrees West of Greenwich."
+# This act does not state when it takes effect, so one has to assume it
+# applies since 1952-10-16. But there is the possibility that the act just
+# legalized prior existing practice, as we had seen with the Guernsey law of
+# 1913-06-18 for the switch in 1909-04-19.
+#
+# From Paul Eggert (2021-03-24):
+# Transitions after 1952 are from Shanks & Pottenger.
+#
# Rule NAME FROM TO - IN ON AT SAVE LETTER/S
Rule Cook 1978 only - Nov 12 0:00 0:30 -
Rule Cook 1979 1991 - Mar Sun>=1 0:00 0 -
Rule Cook 1979 1990 - Oct lastSun 0:00 0:30 -
# Zone NAME STDOFF RULES FORMAT [UNTIL]
-Zone Pacific/Rarotonga -10:39:04 - LMT 1901 # Avarua
+Zone Pacific/Rarotonga 13:20:56 - LMT 1899 Dec 26 # Avarua
+ -10:39:04 - LMT 1952 Oct 16
-10:30 - -1030 1978 Nov 12
-10:00 Cook -10/-0930
@@ -634,10 +681,18 @@
# Niue
+# See Pacific/Raratonga comments for 1952 transition.
+#
+# From Tim Parenti (2021-09-13):
+# Consecutive contemporaneous editions of The Air Almanac listed -11:20 for
+# Niue as of Apr 1964 but -11 as of Aug 1964:
+# Apr 1964: https://books.google.com/books?id=_1So677Y5vUC&pg=SL1-PA23
+# Aug 1964: https://books.google.com/books?id=MbJloqd-zyUC&pg=SL1-PA23
+# Without greater specificity, guess 1964-07-01 for this transition.
+
# Zone NAME STDOFF RULES FORMAT [UNTIL]
-Zone Pacific/Niue -11:19:40 - LMT 1901 # Alofi
- -11:20 - -1120 1951
- -11:30 - -1130 1978 Oct 1
+Zone Pacific/Niue -11:19:40 - LMT 1952 Oct 16 # Alofi
+ -11:20 - -1120 1964 Jul
-11:00 - -11
# Norfolk
@@ -661,6 +716,7 @@
Zone Pacific/Port_Moresby 9:48:40 - LMT 1880
9:48:32 - PMMT 1895 # Port Moresby Mean Time
10:00 - +10
+Link Pacific/Port_Moresby Antarctica/DumontDUrville
#
# From Paul Eggert (2014-10-13):
# Base the Bougainville entry on the Arawa-Kieta region, which appears to have
@@ -765,13 +821,17 @@
# From Paul Eggert (2014-07-08):
# That web page currently lists transitions for 2012/3 and 2013/4.
# Assume the pattern instituted in 2012 will continue indefinitely.
+#
+# From Geoffrey D. Bennett (2021-09-20):
+# https://www.mcil.gov.ws/storage/2021/09/MCIL-Scan_20210920_120553.pdf
+# DST has been cancelled for this year.
# Rule NAME FROM TO - IN ON AT SAVE LETTER/S
Rule WS 2010 only - Sep lastSun 0:00 1 -
Rule WS 2011 only - Apr Sat>=1 4:00 0 -
Rule WS 2011 only - Sep lastSat 3:00 1 -
-Rule WS 2012 max - Apr Sun>=1 4:00 0 -
-Rule WS 2012 max - Sep lastSun 3:00 1 -
+Rule WS 2012 2021 - Apr Sun>=1 4:00 0 -
+Rule WS 2012 2020 - Sep lastSun 3:00 1 -
# Zone NAME STDOFF RULES FORMAT [UNTIL]
Zone Pacific/Apia 12:33:04 - LMT 1892 Jul 5
-11:26:56 - LMT 1911
@@ -818,8 +878,8 @@
Rule Tonga 2016 only - Nov Sun>=1 2:00 1:00 -
Rule Tonga 2017 only - Jan Sun>=15 3:00 0 -
# Zone NAME STDOFF RULES FORMAT [UNTIL]
-Zone Pacific/Tongatapu 12:19:20 - LMT 1901
- 12:20 - +1220 1941
+Zone Pacific/Tongatapu 12:19:12 - LMT 1945 Sep 10
+ 12:20 - +1220 1961
13:00 - +13 1999
13:00 Tonga +13/+14
@@ -1761,6 +1821,23 @@
# One source for this is page 202 of: Bartky IR. One Time Fits All:
# The Campaigns for Global Uniformity (2007).
+# Kanton
+
+# From Paul Eggert (2021-05-27):
+# Kiribati's +13 timezone is represented by Kanton, its only populated
+# island. (It was formerly spelled "Canton", but Gilbertese lacks "C".)
+# Kanton was settled on 1937-08-31 by two British radio operators
+# ;
+# Americans came the next year and built an airfield, partly to
+# establish airline service and perhaps partly anticipating the
+# next war. Aside from the war, the airfield was used by commercial
+# airlines until long-range jets became standard; although currently
+# for emergency use only, China says it is considering rebuilding the
+# airfield for high-end niche tourism. Kanton has about two dozen
+# people, caretakers who rotate in from the rest of Kiribati in 2-5
+# year shifts, and who use some of the leftover structures
+# .
+
# Kwajalein
# From an AP article (1993-08-22):
@@ -2044,6 +2121,17 @@
# Tonga
+# From Paul Eggert (2021-03-04):
+# In 1943 "The standard time kept is 12 hrs. 19 min. 12 sec. fast
+# on Greenwich mean time." according to the Admiralty's Hydrographic
+# Dept., Pacific Islands Pilot, Vol. II, 7th ed., 1943, p 360.
+
+# From Michael Deckers (2021-03-03):
+# [Ian R Bartky: "One Time Fits All: The Campaigns for Global Uniformity".
+# Stanford University Press. 2007. p. 255]:
+# On 10 September 1945 Tonga adopted a standard time 12 hours,
+# 20 minutes in advance of Greenwich.
+
# From Paul Eggert (1996-01-22):
# Today's _Wall Street Journal_ (p 1) reports that "Tonga has been plotting
# to sneak ahead of [New Zealanders] by introducing daylight-saving time."
@@ -2072,9 +2160,26 @@
# The Crown Prince, presented an unanswerable argument: "Remember that
# on the World Day of Prayer, you would be the first people on Earth
# to say your prayers in the morning."
-
-# From Paul Eggert (2006-03-22):
-# Shanks & Pottenger say the transition was on 1968-10-01; go with Mundell.
+#
+# From Tim Parenti (2021-09-13), per Paul Eggert (2006-03-22) and Michael
+# Deckers (2021-03-03):
+# Mundell places the transition from +12:20 to +13 in 1941, while Shanks &
+# Pottenger say the transition was on 1968-10-01.
+#
+# The Air Almanac published contemporaneous tables of standard times,
+# which listed +12:20 as of Nov 1960 and +13 as of Mar 1961:
+# Nov 1960: https://books.google.com/books?id=bVgtWM6kPZUC&pg=SL1-PA19
+# Mar 1961: https://books.google.com/books?id=W2nItAul4g0C&pg=SL1-PA19
+# (Thanks to P Chan for pointing us toward these sources.)
+# This agrees with Bartky, who writes that "since 1961 [Tonga's] official time
+# has been thirteen hours in advance of Greenwich time" (p. 202) and further
+# writes in an endnote that this was because "the legislation was amended" on
+# 1960-10-19. (p. 255)
+#
+# Without greater specificity, presume that Bartky and the Air Almanac point to
+# a 1961-01-01 transition, as Tāufaʻāhau Tupou IV was still Crown Prince in
+# 1961 and this still jives with the gist of Mundell's telling, and go with
+# this over Shanks & Pottenger.
# From Eric Ulevik (1999-05-03):
# Tonga's director of tourism, who is also secretary of the National Millennium
diff -Nru openjdk-lts-11.0.11+9/make/data/tzdata/backward openjdk-lts-11.0.14+9/make/data/tzdata/backward
--- openjdk-lts-11.0.11+9/make/data/tzdata/backward 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/make/data/tzdata/backward 2022-01-13 21:56:25.000000000 +0000
@@ -26,8 +26,10 @@
# This file is in the public domain, so clarified as of
# 2009-05-17 by Arthur David Olson.
-# This file provides links between current names for timezones
-# and their old names. Many names changed in late 1993.
+# This file provides links from old or merged timezone names to current ones.
+# Many names changed in late 1993. Several of these names are
+# also present in the file 'backzone', which has data important only
+# for pre-1970 timestamps and so is out of scope for tzdb proper.
# Link TARGET LINK-NAME
Link Africa/Nairobi Africa/Asmera
@@ -36,7 +38,7 @@
Link America/Adak America/Atka
Link America/Argentina/Buenos_Aires America/Buenos_Aires
Link America/Argentina/Catamarca America/Catamarca
-Link America/Atikokan America/Coral_Harbour
+Link America/Panama America/Coral_Harbour
Link America/Argentina/Cordoba America/Cordoba
Link America/Tijuana America/Ensenada
Link America/Indiana/Indianapolis America/Fort_Wayne
@@ -51,7 +53,7 @@
Link America/Argentina/Cordoba America/Rosario
Link America/Tijuana America/Santa_Isabel
Link America/Denver America/Shiprock
-Link America/Port_of_Spain America/Virgin
+Link America/Puerto_Rico America/Virgin
Link Pacific/Auckland Antarctica/South_Pole
Link Asia/Ashgabat Asia/Ashkhabad
Link Asia/Kolkata Asia/Calcutta
@@ -126,6 +128,7 @@
Link Pacific/Chatham NZ-CHAT
Link America/Denver Navajo
Link Asia/Shanghai PRC
+Link Pacific/Kanton Pacific/Enderbury
Link Pacific/Honolulu Pacific/Johnston
Link Pacific/Pohnpei Pacific/Ponape
Link Pacific/Pago_Pago Pacific/Samoa
diff -Nru openjdk-lts-11.0.11+9/make/data/tzdata/europe openjdk-lts-11.0.14+9/make/data/tzdata/europe
--- openjdk-lts-11.0.11+9/make/data/tzdata/europe 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/make/data/tzdata/europe 2022-01-13 21:56:25.000000000 +0000
@@ -91,7 +91,6 @@
# 0:00 GMT BST BDST Greenwich, British Summer
# 0:00 GMT IST Greenwich, Irish Summer
# 0:00 WET WEST WEMT Western Europe
-# 0:19:32.13 AMT* NST* Amsterdam, Netherlands Summer (1835-1937)
# 1:00 BST British Standard (1968-1971)
# 1:00 IST GMT Irish Standard (1968-) with winter DST
# 1:00 CET CEST CEMT Central Europe
@@ -845,7 +844,7 @@
# Shanks & Pottenger give 02:00, the BEV 00:00. Go with the BEV,
# and guess 02:00 for 1945-04-12.
-# From Alois Triendl (2019-07-22):
+# From Alois Treindl (2019-07-22):
# In 1946 the end of DST was on Monday, 7 October 1946, at 3:00 am.
# Shanks had this right. Source: Die Weltpresse, 5. Oktober 1946, page 5.
@@ -1759,19 +1758,22 @@
# advanced to sixty minutes later starting at hour two on 1944-04-02; ...
# Starting at hour three on the date 1944-09-17 standard time will be resumed.
#
-# From Alois Triendl (2019-07-02):
+# From Alois Treindl (2019-07-02):
# I spent 6 Euros to buy two archive copies of Il Messaggero, a Roman paper,
# for 1 and 2 April 1944. The edition of 2 April has this note: "Tonight at 2
# am, put forward the clock by one hour. Remember that in the night between
# today and Monday the 'ora legale' will come in force again." That makes it
# clear that in Rome the change was on Monday, 3 April 1944 at 2 am.
#
-# From Paul Eggert (2016-10-27):
+# From Paul Eggert (2021-10-05):
# Go with INRiM for DST rules, except as corrected by Inglis for 1944
# for the Kingdom of Italy. This is consistent with Renzo Baldini.
# Model Rome's occupation by using C-Eur rules from 1943-09-10
# to 1944-06-04; although Rome was an open city during this period, it
-# was effectively controlled by Germany.
+# was effectively controlled by Germany. Using C-Eur is consistent
+# with Treindl's comment about Rome in April 1944, as the "Rule Italy"
+# lines during German occupation do not affect Europe/Rome
+# (though they do affect Europe/Malta).
#
# Rule NAME FROM TO - IN ON AT SAVE LETTER/S
Rule Italy 1916 only - Jun 3 24:00 1:00 S
@@ -1823,6 +1825,10 @@
1:00 Italy CE%sT 1980
1:00 EU CE%sT
+# Kosovo
+# See Europe/Belgrade.
+
+
Link Europe/Rome Europe/Vatican
Link Europe/Rome Europe/San_Marino
@@ -2173,6 +2179,10 @@
# The data entries before 1945 are taken from
# https://www.staff.science.uu.nl/~gent0113/wettijd/wettijd.htm
+# From Paul Eggert (2021-05-09):
+# I invented the abbreviations AMT for Amsterdam Mean Time and NST for
+# Netherlands Summer Time, used in the Netherlands from 1835 to 1937.
+
# Rule NAME FROM TO - IN ON AT SAVE LETTER/S
Rule Neth 1916 only - May 1 0:00 1:00 NST # Netherlands Summer Time
Rule Neth 1916 only - Oct 1 0:00 0 AMT # Amsterdam Mean Time
@@ -2399,12 +2409,10 @@
Rule Port 1944 1945 - Apr Sat>=21 22:00s 2:00 M
Rule Port 1946 only - Apr Sat>=1 23:00s 1:00 S
Rule Port 1946 only - Oct Sat>=1 23:00s 0 -
-Rule Port 1947 1949 - Apr Sun>=1 2:00s 1:00 S
-Rule Port 1947 1949 - Oct Sun>=1 2:00s 0 -
-# Shanks & Pottenger say DST was observed in 1950; go with Whitman.
+# Whitman says DST was not observed in 1950; go with Shanks & Pottenger.
# Whitman gives Oct lastSun for 1952 on; go with Shanks & Pottenger.
-Rule Port 1951 1965 - Apr Sun>=1 2:00s 1:00 S
-Rule Port 1951 1965 - Oct Sun>=1 2:00s 0 -
+Rule Port 1947 1965 - Apr Sun>=1 2:00s 1:00 S
+Rule Port 1947 1965 - Oct Sun>=1 2:00s 0 -
Rule Port 1977 only - Mar 27 0:00s 1:00 S
Rule Port 1977 only - Sep 25 0:00s 0 -
Rule Port 1978 1979 - Apr Sun>=1 0:00s 1:00 S
@@ -2641,7 +2649,7 @@
# Although Shanks lists 1945-01-01 as the date for transition from
# +01/+02 to +02/+03, more likely this is a placeholder. Guess that
# the transition occurred at 1945-04-10 00:00, which is about when
-# Königsberg surrendered to Soviet troops. (Thanks to Alois Triendl.)
+# Königsberg surrendered to Soviet troops. (Thanks to Alois Treindl.)
# From Paul Eggert (2016-03-18):
# The 1989 transition is from USSR act No. 227 (1989-03-14).
@@ -3706,6 +3714,9 @@
#
# Source: The newspaper "Dagens Nyheter", 1916-10-01, page 7 upper left.
+# An extra-special abbreviation style is SET for Swedish Time (svensk
+# normaltid) 1879-1899, 3° west of the Stockholm Observatory.
+
# Zone NAME STDOFF RULES FORMAT [UNTIL]
Zone Europe/Stockholm 1:12:12 - LMT 1879 Jan 1
1:00:14 - SET 1900 Jan 1 # Swedish Time
diff -Nru openjdk-lts-11.0.11+9/make/data/tzdata/leapseconds openjdk-lts-11.0.14+9/make/data/tzdata/leapseconds
--- openjdk-lts-11.0.11+9/make/data/tzdata/leapseconds 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/make/data/tzdata/leapseconds 2022-01-13 21:56:25.000000000 +0000
@@ -95,11 +95,11 @@
# Any additional leap seconds will come after this.
# This Expires line is commented out for now,
# so that pre-2020a zic implementations do not reject this file.
-#Expires 2021 Dec 28 00:00:00
+#Expires 2022 Jun 28 00:00:00
# POSIX timestamps for the data in this file:
#updated 1467936000 (2016-07-08 00:00:00 UTC)
-#expires 1640649600 (2021-12-28 00:00:00 UTC)
+#expires 1656374400 (2022-06-28 00:00:00 UTC)
-# Updated through IERS Bulletin C61
-# File expires on: 28 December 2021
+# Updated through IERS Bulletin C62
+# File expires on: 28 June 2022
diff -Nru openjdk-lts-11.0.11+9/make/data/tzdata/northamerica openjdk-lts-11.0.14+9/make/data/tzdata/northamerica
--- openjdk-lts-11.0.11+9/make/data/tzdata/northamerica 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/make/data/tzdata/northamerica 2022-01-13 21:56:25.000000000 +0000
@@ -752,7 +752,11 @@
-11:00 US B%sT 1983 Oct 30 2:00
-10:00 US AH%sT 1983 Nov 30
-10:00 US H%sT
-# The following switches don't quite make our 1970 cutoff.
+# The following switches don't make our 1970 cutoff.
+#
+# Kiska observed Tokyo date and time during Japanese occupation from
+# 1942-06-06 to 1943-07-29, and similarly for Attu from 1942-06-07 to
+# 1943-05-29 (all dates American). Both islands are now uninhabited.
#
# Shanks writes that part of southwest Alaska (e.g. Aniak)
# switched from -11:00 to -10:00 on 1968-09-22 at 02:00,
@@ -848,6 +852,8 @@
-7:00 - MST 1967
-7:00 US M%sT 1968 Mar 21
-7:00 - MST
+Link America/Phoenix America/Creston
+
# From Arthur David Olson (1988-02-13):
# A writer from the Inter Tribal Council of Arizona, Inc.,
# notes in private correspondence dated 1987-12-28 that "Presently, only the
@@ -993,7 +999,7 @@
-5:00 US E%sT
#
# Perry County, Indiana, switched from eastern to central time in April 2006.
-# From Alois Triendl (2019-07-09):
+# From Alois Treindl (2019-07-09):
# The Indianapolis News, Friday 27 October 1967 states that Perry County
# returned to CST. It went again to EST on 27 April 1969, as documented by the
# Indianapolis star of Saturday 26 April.
@@ -1616,24 +1622,7 @@
# From Paul Eggert (2020-01-10):
# See America/Toronto for most of Quebec, including Montreal.
# See America/Halifax for the Îles de la Madeleine and the Listuguj reserve.
-#
-# Matthews and Vincent (1998) also write that Quebec east of the -63
-# meridian is supposed to observe AST, but residents as far east as
-# Natashquan use EST/EDT, and residents east of Natashquan use AST.
-# The Quebec department of justice writes in
-# "The situation in Minganie and Basse-Côte-Nord"
-# https://www.justice.gouv.qc.ca/en/department/ministre/functions-and-responsabilities/legal-time-in-quebec/the-situation-in-minganie-and-basse-cote-nord/
-# that the coastal strip from just east of Natashquan to Blanc-Sablon
-# observes Atlantic standard time all year round.
-# This common practice was codified into law as of 2007; see Legal Time Act,
-# CQLR c T-5.1 .
-# For lack of better info, guess this practice began around 1970, contra to
-# Shanks & Pottenger who have this region observing AST/ADT.
-
-# Zone NAME STDOFF RULES FORMAT [UNTIL]
-Zone America/Blanc-Sablon -3:48:28 - LMT 1884
- -4:00 Canada A%sT 1970
- -4:00 - AST
+# See America/Puerto_Rico for east of Natashquan.
# Ontario
@@ -1672,54 +1661,6 @@
# time became a comic failure in Orillia. Toronto Star 2017-07-08.
# https://www.thestar.com/news/insight/2017/07/08/bold-attempt-at-daylight-saving-time-became-a-comic-failure-in-orillia.html
-# From Paul Eggert (1997-10-17):
-# Mark Brader writes that an article in the 1997-10-14 Toronto Star
-# says that Atikokan, Ontario currently does not observe DST,
-# but will vote on 11-10 whether to use EST/EDT.
-# He also writes that the Ontario Time Act (1990, Chapter T.9)
-# http://www.gov.on.ca/MBS/english/publications/statregs/conttext.html
-# says that Ontario east of 90W uses EST/EDT, and west of 90W uses CST/CDT.
-# Officially Atikokan is therefore on CST/CDT, and most likely this report
-# concerns a non-official time observed as a matter of local practice.
-#
-# From Paul Eggert (2000-10-02):
-# Matthews and Vincent (1998) write that Atikokan, Pickle Lake, and
-# New Osnaburgh observe CST all year, that Big Trout Lake observes
-# CST/CDT, and that Upsala and Shebandowan observe EST/EDT, all in
-# violation of the official Ontario rules.
-#
-# From Paul Eggert (2006-07-09):
-# Chris Walton (2006-07-06) mentioned an article by Stephanie MacLellan in the
-# 2005-07-21 Chronicle-Journal, which said:
-#
-# The clocks in Atikokan stay set on standard time year-round.
-# This means they spend about half the time on central time and
-# the other half on eastern time.
-#
-# For the most part, the system works, Mayor Dennis Brown said.
-#
-# "The majority of businesses in Atikokan deal more with Eastern
-# Canada, but there are some that deal with Western Canada," he
-# said. "I don't see any changes happening here."
-#
-# Walton also writes "Supposedly Pickle Lake and Mishkeegogamang
-# [New Osnaburgh] follow the same practice."
-
-# From Garry McKinnon (2006-07-14) via Chris Walton:
-# I chatted with a member of my board who has an outstanding memory
-# and a long history in Atikokan (and in the telecom industry) and he
-# can say for certain that Atikokan has been practicing the current
-# time keeping since 1952, at least.
-
-# From Paul Eggert (2006-07-17):
-# Shanks & Pottenger say that Atikokan has agreed with Rainy River
-# ever since standard time was introduced, but the information from
-# McKinnon sounds more authoritative. For now, assume that Atikokan
-# switched to EST immediately after WWII era daylight saving time
-# ended. This matches the old (less-populous) America/Coral_Harbour
-# entry since our cutoff date of 1970, so we can move
-# America/Coral_Harbour to the 'backward' file.
-
# From Mark Brader (2010-03-06):
#
# Currently the database has:
@@ -1850,6 +1791,7 @@
-5:00 Canada E%sT 1946
-5:00 Toronto E%sT 1974
-5:00 Canada E%sT
+Link America/Toronto America/Nassau
Zone America/Thunder_Bay -5:57:00 - LMT 1895
-6:00 - CST 1910
-5:00 - EST 1942
@@ -1865,11 +1807,7 @@
-6:00 Canada C%sT 1940 Sep 29
-6:00 1:00 CDT 1942 Feb 9 2:00s
-6:00 Canada C%sT
-Zone America/Atikokan -6:06:28 - LMT 1895
- -6:00 Canada C%sT 1940 Sep 29
- -6:00 1:00 CDT 1942 Feb 9 2:00s
- -6:00 Canada C%sT 1945 Sep 30 2:00
- -5:00 - EST
+# For Atikokan see America/Panama.
# Manitoba
@@ -2021,7 +1959,7 @@
# Alberta
-# From Alois Triendl (2019-07-19):
+# From Alois Treindl (2019-07-19):
# There was no DST in Alberta in 1967... Calgary Herald, 29 April 1967.
# 1969, no DST, from Edmonton Journal 18 April 1969
#
@@ -2060,60 +1998,6 @@
# Shanks & Pottenger write that since 1970 most of this region has
# been like Vancouver.
# Dawson Creek uses MST. Much of east BC is like Edmonton.
-# Matthews and Vincent (1998) write that Creston is like Dawson Creek.
-
-# It seems though that (re: Creston) is not entirely correct:
-
-# From Chris Walton (2011-12-01):
-# There are two areas within the Canadian province of British Columbia
-# that do not currently observe daylight saving:
-# a) The Creston Valley (includes the town of Creston and surrounding area)
-# b) The eastern half of the Peace River Regional District
-# (includes the cities of Dawson Creek and Fort St. John)
-
-# Earlier this year I stumbled across a detailed article about the time
-# keeping history of Creston; it was written by Tammy Hardwick who is the
-# manager of the Creston & District Museum. The article was written in May 2009.
-# http://www.ilovecreston.com/?p=articles&t=spec&ar=260
-# According to the article, Creston has not changed its clocks since June 1918.
-# i.e. Creston has been stuck on UT-7 for 93 years.
-# Dawson Creek, on the other hand, changed its clocks as recently as April 1972.
-
-# Unfortunately the exact date for the time change in June 1918 remains
-# unknown and will be difficult to ascertain. I e-mailed Tammy a few months
-# ago to ask if Sunday June 2 was a reasonable guess. She said it was just
-# as plausible as any other date (in June). She also said that after writing
-# the article she had discovered another time change in 1916; this is the
-# subject of another article which she wrote in October 2010.
-# http://www.creston.museum.bc.ca/index.php?module=comments&uop=view_comment&cm+id=56
-
-# Here is a summary of the three clock change events in Creston's history:
-# 1. 1884 or 1885: adoption of Mountain Standard Time (GMT-7)
-# Exact date unknown
-# 2. Oct 1916: switch to Pacific Standard Time (GMT-8)
-# Exact date in October unknown; Sunday October 1 is a reasonable guess.
-# 3. June 1918: switch to Pacific Daylight Time (GMT-7)
-# Exact date in June unknown; Sunday June 2 is a reasonable guess.
-# note 1:
-# On Oct 27/1918 when daylight saving ended in the rest of Canada,
-# Creston did not change its clocks.
-# note 2:
-# During WWII when the Federal Government legislated a mandatory clock change,
-# Creston did not oblige.
-# note 3:
-# There is no guarantee that Creston will remain on Mountain Standard Time
-# (UTC-7) forever.
-# The subject was debated at least once this year by the town Council.
-# http://www.bclocalnews.com/kootenay_rockies/crestonvalleyadvance/news/116760809.html
-
-# During a period WWII, summer time (Daylight saying) was mandatory in Canada.
-# In Creston, that was handled by shifting the area to PST (-8:00) then applying
-# summer time to cause the offset to be -7:00, the same as it had been before
-# the change. It can be argued that the timezone abbreviation during this
-# period should be PDT rather than MST, but that doesn't seem important enough
-# (to anyone) to further complicate the rules.
-
-# The transition dates (and times) are guesses.
# From Matt Johnson (2015-09-21):
# Fort Nelson, BC, Canada will cancel DST this year. So while previously they
@@ -2130,7 +2014,7 @@
#
# From Paul Eggert (2019-07-25):
# Shanks says Fort Nelson did not observe DST in 1946, unlike Vancouver.
-# Alois Triendl confirmed this on 07-22, citing the 1946-04-27 Vancouver Daily
+# Alois Treindl confirmed this on 07-22, citing the 1946-04-27 Vancouver Daily
# Province. He also cited the 1946-09-28 Victoria Daily Times, which said
# that Vancouver, Victoria, etc. "change at midnight Saturday"; for now,
# guess they meant 02:00 Sunday since 02:00 was common practice in Vancouver.
@@ -2167,10 +2051,7 @@
-8:00 Vanc P%sT 1987
-8:00 Canada P%sT 2015 Mar 8 2:00
-7:00 - MST
-Zone America/Creston -7:46:04 - LMT 1884
- -7:00 - MST 1916 Oct 1
- -8:00 - PST 1918 Jun 2
- -7:00 - MST
+# For Creston see America/Phoenix.
# Northwest Territories, Nunavut, Yukon
@@ -2952,64 +2833,61 @@
# Anguilla
# Antigua and Barbuda
-# See America/Port_of_Spain.
+# See America/Puerto_Rico.
+
+# The Bahamas
+# See America/Toronto.
-# Bahamas
-#
-# For 1899 Milne gives -5:09:29.5; round that.
-#
-# From P Chan (2020-11-27, corrected on 2020-12-02):
-# There were two periods of DST observed in 1942-1945: 1942-05-01
-# midnight to 1944-12-31 midnight and 1945-02-01 to 1945-10-17 midnight.
-# "midnight" should mean 24:00 from the context.
-#
-# War Time Order 1942 [1942-05-01] and War Time (No. 2) Order 1942 [1942-09-29]
-# Appendix to the Statutes of 7 George VI. and the Year 1942. p 34, 43
-# https://books.google.com/books?id=5rlNAQAAIAAJ&pg=RA3-PA34
-# https://books.google.com/books?id=5rlNAQAAIAAJ&pg=RA3-PA43
-#
-# War Time Order 1943 [1943-03-31] and War Time Order 1944 [1943-12-29]
-# Appendix to the Statutes of 8 George VI. and the Year 1943. p 9-10, 28-29
-# https://books.google.com/books?id=5rlNAQAAIAAJ&pg=RA4-PA9
-# https://books.google.com/books?id=5rlNAQAAIAAJ&pg=RA4-PA28
-#
-# War Time Order 1945 [1945-01-31] and the Order which revoke War Time Order
-# 1945 [1945-10-16] Appendix to the Statutes of 9 George VI. and the Year
-# 1945. p 160, 247-248
-# https://books.google.com/books?id=5rlNAQAAIAAJ&pg=RA6-PA160
-# https://books.google.com/books?id=5rlNAQAAIAAJ&pg=RA6-PA247
-#
-# From Sue Williams (2006-12-07):
-# The Bahamas announced about a month ago that they plan to change their DST
-# rules to sync with the U.S. starting in 2007....
-# http://www.jonesbahamas.com/?c=45&a=10412
-
-# Rule NAME FROM TO - IN ON AT SAVE LETTER/S
-Rule Bahamas 1942 only - May 1 24:00 1:00 W
-Rule Bahamas 1944 only - Dec 31 24:00 0 S
-Rule Bahamas 1945 only - Feb 1 0:00 1:00 W
-Rule Bahamas 1945 only - Aug 14 23:00u 1:00 P # Peace
-Rule Bahamas 1945 only - Oct 17 24:00 0 S
-Rule Bahamas 1964 1975 - Oct lastSun 2:00 0 S
-Rule Bahamas 1964 1975 - Apr lastSun 2:00 1:00 D
-# Zone NAME STDOFF RULES FORMAT [UNTIL]
-Zone America/Nassau -5:09:30 - LMT 1912 Mar 2
- -5:00 Bahamas E%sT 1976
- -5:00 US E%sT
# Barbados
# For 1899 Milne gives -3:58:29.2; round that.
-# Rule NAME FROM TO - IN ON AT SAVE LETTER/S
+# From P Chan (2020-12-09 and 2020-12-11):
+# Standard time of GMT-4 was adopted in 1911.
+# Definition of Time Act, 1911 (1911-7) [1911-08-28]
+# 1912, Laws of Barbados (5 v.), OCLC Number: 919801291, Vol. 4, Image No. 522
+# 1944, Laws of Barbados (5 v.), OCLC Number: 84548697, Vol. 4, Image No. 122
+# http://llmc.com/browse.aspx?type=2&coll=85&div=297
+#
+# DST was observed in 1942-44.
+# Defence (Daylight Saving) Regulations, 1942, 1942-04-13
+# Defence (Daylight Saving) (Repeal) Regulations, 1942, 1942-08-22
+# Defence (Daylight Saving) Regulations, 1943, 1943-04-16
+# Defence (Daylight Saving) (Repeal) Regulations, 1943, 1943-09-01
+# Defence (Daylight Saving) Regulations, 1944, 1944-03-21
+# [Defence (Daylight Saving) (Amendment) Regulations 1944, 1944-03-28]
+# Defence (Daylight Saving) (Repeal) Regulations, 1944, 1944-08-30
+#
+# 1914-, Subsidiary Legis., Annual Vols. OCLC Number: 226290591
+# 1942: Image Nos. 527-528, 555-556
+# 1943: Image Nos. 178-179, 198
+# 1944: Image Nos. 113-115, 129
+# http://llmc.com/titledescfull.aspx?type=2&coll=85&div=297&set=98437
+#
+# From Tim Parenti (2021-02-20):
+# The transitions below are derived from P Chan's sources, except that the 1977
+# through 1980 transitions are from Shanks & Pottenger since we have no better
+# data there. Of particular note, the 1944 DST regulation only advanced the
+# time to "exactly three and a half hours later than Greenwich mean time", as
+# opposed to "three hours" in the 1942 and 1943 regulations.
+
+# Rule NAME FROM TO - IN ON AT SAVE LETTER/S
+Rule Barb 1942 only - Apr 19 5:00u 1:00 D
+Rule Barb 1942 only - Aug 31 6:00u 0 S
+Rule Barb 1943 only - May 2 5:00u 1:00 D
+Rule Barb 1943 only - Sep 5 6:00u 0 S
+Rule Barb 1944 only - Apr 10 5:00u 0:30 -
+Rule Barb 1944 only - Sep 10 6:00u 0 S
Rule Barb 1977 only - Jun 12 2:00 1:00 D
Rule Barb 1977 1978 - Oct Sun>=1 2:00 0 S
Rule Barb 1978 1980 - Apr Sun>=15 2:00 1:00 D
Rule Barb 1979 only - Sep 30 2:00 0 S
Rule Barb 1980 only - Sep 25 2:00 0 S
# Zone NAME STDOFF RULES FORMAT [UNTIL]
-Zone America/Barbados -3:58:29 - LMT 1924 # Bridgetown
- -3:58:29 - BMT 1932 # Bridgetown Mean Time
+Zone America/Barbados -3:58:29 - LMT 1911 Aug 28 # Bridgetown
+ -4:00 Barb A%sT 1944
+ -4:00 Barb AST/-0330 1945
-4:00 Barb A%sT
# Belize
@@ -3171,6 +3049,9 @@
-4:00 Canada A%sT 1976
-4:00 US A%sT
+# Caribbean Netherlands
+# See America/Puerto_Rico.
+
# Cayman Is
# See America/Panama.
@@ -3399,7 +3280,7 @@
-5:00 Cuba C%sT
# Dominica
-# See America/Port_of_Spain.
+# See America/Puerto_Rico.
# Dominican Republic
@@ -3451,7 +3332,7 @@
# Guadeloupe
# St Barthélemy
# St Martin (French part)
-# See America/Port_of_Spain.
+# See America/Puerto_Rico.
# Guatemala
#
@@ -3638,7 +3519,7 @@
-4:00 - AST
# Montserrat
-# See America/Port_of_Spain.
+# See America/Puerto_Rico.
# Nicaragua
#
@@ -3710,6 +3591,7 @@
Zone America/Panama -5:18:08 - LMT 1890
-5:19:36 - CMT 1908 Apr 22 # Colón Mean Time
-5:00 - EST
+Link America/Panama America/Atikokan
Link America/Panama America/Cayman
# Puerto Rico
@@ -3719,10 +3601,29 @@
-4:00 - AST 1942 May 3
-4:00 US A%sT 1946
-4:00 - AST
+Link America/Puerto_Rico America/Anguilla
+Link America/Puerto_Rico America/Antigua
+Link America/Puerto_Rico America/Aruba
+Link America/Puerto_Rico America/Curacao
+Link America/Puerto_Rico America/Blanc-Sablon # Quebec (Lower North Shore)
+Link America/Puerto_Rico America/Dominica
+Link America/Puerto_Rico America/Grenada
+Link America/Puerto_Rico America/Guadeloupe
+Link America/Puerto_Rico America/Kralendijk # Caribbean Netherlands
+Link America/Puerto_Rico America/Lower_Princes # Sint Maarten
+Link America/Puerto_Rico America/Marigot # St Martin (French part)
+Link America/Puerto_Rico America/Montserrat
+Link America/Puerto_Rico America/Port_of_Spain # Trinidad & Tobago
+Link America/Puerto_Rico America/St_Barthelemy # St Barthélemy
+Link America/Puerto_Rico America/St_Kitts # St Kitts & Nevis
+Link America/Puerto_Rico America/St_Lucia
+Link America/Puerto_Rico America/St_Thomas # Virgin Islands (US)
+Link America/Puerto_Rico America/St_Vincent
+Link America/Puerto_Rico America/Tortola # Virgin Islands (UK)
# St Kitts-Nevis
# St Lucia
-# See America/Port_of_Spain.
+# See America/Puerto_Rico.
# St Pierre and Miquelon
# There are too many St Pierres elsewhere, so we'll use 'Miquelon'.
@@ -3733,7 +3634,10 @@
-3:00 Canada -03/-02
# St Vincent and the Grenadines
-# See America/Port_of_Spain.
+# See America/Puerto_Rico.
+
+# Sint Maarten
+# See America/Puerto_Rico.
# Turks and Caicos
#
@@ -3804,8 +3708,8 @@
-5:00 US E%sT
# British Virgin Is
-# Virgin Is
-# See America/Port_of_Spain.
+# US Virgin Is
+# See America/Puerto_Rico.
# Local Variables:
diff -Nru openjdk-lts-11.0.11+9/make/data/tzdata/southamerica openjdk-lts-11.0.14+9/make/data/tzdata/southamerica
--- openjdk-lts-11.0.11+9/make/data/tzdata/southamerica 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/make/data/tzdata/southamerica 2022-01-13 21:56:25.000000000 +0000
@@ -597,7 +597,7 @@
-3:00 - -03
# Aruba
-Link America/Curacao America/Aruba
+# See America/Puerto_Rico.
# Bolivia
# Zone NAME STDOFF RULES FORMAT [UNTIL]
@@ -1392,35 +1392,14 @@
# no information; probably like America/Bogota
# Curaçao
-
-# Milne gives 4:35:46.9 for Curaçao mean time; round to nearest.
-#
-# From Paul Eggert (2006-03-22):
-# Shanks & Pottenger say that The Bottom and Philipsburg have been at
-# -4:00 since standard time was introduced on 1912-03-02; and that
-# Kralendijk and Rincon used Kralendijk Mean Time (-4:33:08) from
-# 1912-02-02 to 1965-01-01. The former is dubious, since S&P also say
-# Saba Island has been like Curaçao.
-# This all predates our 1970 cutoff, though.
-#
-# By July 2007 Curaçao and St Maarten are planned to become
-# associated states within the Netherlands, much like Aruba;
-# Bonaire, Saba and St Eustatius would become directly part of the
-# Netherlands as Kingdom Islands. This won't affect their time zones
-# though, as far as we know.
+# See America/Puerto_Rico.
#
-# Zone NAME STDOFF RULES FORMAT [UNTIL]
-Zone America/Curacao -4:35:47 - LMT 1912 Feb 12 # Willemstad
- -4:30 - -0430 1965
- -4:00 - AST
-
# From Arthur David Olson (2011-06-15):
# use links for places with new iso3166 codes.
# The name "Lower Prince's Quarter" is both longer than fourteen characters
-# and contains an apostrophe; use "Lower_Princes" below.
-
-Link America/Curacao America/Lower_Princes # Sint Maarten
-Link America/Curacao America/Kralendijk # Caribbean Netherlands
+# and contains an apostrophe; use "Lower_Princes"....
+# From Paul Eggert (2021-09-29):
+# These backward-compatibility links now are in the 'northamerica' file.
# Ecuador
#
@@ -1563,11 +1542,40 @@
-3:00 - -03
# Guyana
+
+# From P Chan (2020-11-27):
+# https://books.google.com/books?id=5-5CAQAAMAAJ&pg=SA1-PA547
+# The Official Gazette of British Guiana. (New Series.) Vol. XL. July to
+# December, 1915, p 1547, lists as several notes:
+# "Local Mean Time 3 hours 52 mins. 39 secs. slow of Greenwich Mean Time
+# (Georgetown.) From 1st August, 1911, British Guiana Standard Mean Time 4
+# hours slow of Greenwich Mean Time, by notice in Official Gazette on 1st July,
+# 1911. From 1st March, 1915, British Guiana Standard Mean Time 3 hours 45
+# mins. 0 secs. slow of Greenwich Mean Time, by notice in Official Gazette on
+# 23rd January, 1915."
+#
+# https://parliament.gov.gy/documents/acts/10923-act_no._27_of_1975_-_interpretation_and_general_clauses_(amendment)_act_1975.pdf
+# Interpretation and general clauses (Amendment) Act 1975 (Act No. 27 of 1975)
+# [dated 1975-07-31]
+# "This Act...shall come into operation on 1st August, 1975."
+# "...where any expression of time occurs...the time referred to shall signify
+# the standard time of Guyana which shall be three hours behind Greenwich Mean
+# Time."
+#
+# Circular No. 10/1992 dated 1992-03-20
+# https://dps.gov.gy/wp-content/uploads/2018/12/1992-03-20-Circular-010.pdf
+# "...cabinet has decided that with effect from Sunday 29th March, 1992, Guyana
+# Standard Time would be re-established at 01:00 hours by adjusting the hands
+# of the clock back to 24:00 hours."
+# Legislated in the Interpretation and general clauses (Amendment) Act 1992
+# (Act No. 6 of 1992) [passed 1992-03-27, published 1992-04-18]
+# https://parliament.gov.gy/documents/acts/5885-6_of_1992_interpretation_and_general_clauses_(amendment)_act_1992.pdf
+
# Zone NAME STDOFF RULES FORMAT [UNTIL]
-Zone America/Guyana -3:52:40 - LMT 1915 Mar # Georgetown
- -3:45 - -0345 1975 Jul 31
- -3:00 - -03 1991
-# IATA SSIM (1996-06) says -4:00. Assume a 1991 switch.
+Zone America/Guyana -3:52:39 - LMT 1911 Aug 1 # Georgetown
+ -4:00 - -04 1915 Mar 1
+ -3:45 - -0345 1975 Aug 1
+ -3:00 - -03 1992 Mar 29 1:00
-4:00 - -04
# Paraguay
@@ -1708,24 +1716,7 @@
-3:00 - -03
# Trinidad and Tobago
-# Zone NAME STDOFF RULES FORMAT [UNTIL]
-Zone America/Port_of_Spain -4:06:04 - LMT 1912 Mar 2
- -4:00 - AST
-
-# These all agree with Trinidad and Tobago since 1970.
-Link America/Port_of_Spain America/Anguilla
-Link America/Port_of_Spain America/Antigua
-Link America/Port_of_Spain America/Dominica
-Link America/Port_of_Spain America/Grenada
-Link America/Port_of_Spain America/Guadeloupe
-Link America/Port_of_Spain America/Marigot # St Martin (French part)
-Link America/Port_of_Spain America/Montserrat
-Link America/Port_of_Spain America/St_Barthelemy # St Barthélemy
-Link America/Port_of_Spain America/St_Kitts # St Kitts & Nevis
-Link America/Port_of_Spain America/St_Lucia
-Link America/Port_of_Spain America/St_Thomas # Virgin Islands (US)
-Link America/Port_of_Spain America/St_Vincent
-Link America/Port_of_Spain America/Tortola # Virgin Islands (UK)
+# See America/Puerto_Rico.
# Uruguay
# From Paul Eggert (1993-11-18):
diff -Nru openjdk-lts-11.0.11+9/make/data/tzdata/VERSION openjdk-lts-11.0.14+9/make/data/tzdata/VERSION
--- openjdk-lts-11.0.11+9/make/data/tzdata/VERSION 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/make/data/tzdata/VERSION 2022-01-13 21:56:25.000000000 +0000
@@ -21,4 +21,4 @@
# or visit www.oracle.com if you need additional information or have any
# questions.
#
-tzdata2021a
+tzdata2021e
diff -Nru openjdk-lts-11.0.11+9/make/data/tzdata/zone.tab openjdk-lts-11.0.14+9/make/data/tzdata/zone.tab
--- openjdk-lts-11.0.11+9/make/data/tzdata/zone.tab 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/make/data/tzdata/zone.tab 2022-01-13 21:56:25.000000000 +0000
@@ -26,7 +26,7 @@
# This file is in the public domain, so clarified as of
# 2009-05-17 by Arthur David Olson.
#
-# From Paul Eggert (2018-06-27):
+# From Paul Eggert (2021-09-20):
# This file is intended as a backward-compatibility aid for older programs.
# New programs should use zone1970.tab. This file is like zone1970.tab (see
# zone1970.tab's comments), but with the following additional restrictions:
@@ -39,6 +39,9 @@
# clocks have agreed since 1970; this is a narrower definition than
# that of zone1970.tab.
#
+# Unlike zone1970.tab, a row's third column can be a Link from
+# 'backward' instead of a Zone.
+#
# This table is intended as an aid for users, to help them select timezones
# appropriate for their practical needs. It is not intended to take or
# endorse any position on legal or territorial claims.
@@ -251,7 +254,7 @@
KG +4254+07436 Asia/Bishkek
KH +1133+10455 Asia/Phnom_Penh
KI +0125+17300 Pacific/Tarawa Gilbert Islands
-KI -0308-17105 Pacific/Enderbury Phoenix Islands
+KI -0247-17143 Pacific/Kanton Phoenix Islands
KI +0152-15720 Pacific/Kiritimati Line Islands
KM -1141+04316 Indian/Comoro
KN +1718-06243 America/St_Kitts
@@ -414,7 +417,7 @@
TL -0833+12535 Asia/Dili
TM +3757+05823 Asia/Ashgabat
TN +3648+01011 Africa/Tunis
-TO -2110-17510 Pacific/Tongatapu
+TO -210800-1751200 Pacific/Tongatapu
TR +4101+02858 Europe/Istanbul
TT +1039-06131 America/Port_of_Spain
TV -0831+17913 Pacific/Funafuti
diff -Nru openjdk-lts-11.0.11+9/make/devkit/createMacosxDevkit6.sh openjdk-lts-11.0.14+9/make/devkit/createMacosxDevkit6.sh
--- openjdk-lts-11.0.11+9/make/devkit/createMacosxDevkit6.sh 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/make/devkit/createMacosxDevkit6.sh 1970-01-01 00:00:00.000000000 +0000
@@ -1,161 +0,0 @@
-#!/bin/bash
-#
-# Copyright (c) 2015, Oracle and/or its affiliates. All rights reserved.
-# DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
-#
-# This code is free software; you can redistribute it and/or modify it
-# under the terms of the GNU General Public License version 2 only, as
-# published by the Free Software Foundation. Oracle designates this
-# particular file as subject to the "Classpath" exception as provided
-# by Oracle in the LICENSE file that accompanied this code.
-#
-# This code is distributed in the hope that it will be useful, but WITHOUT
-# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-# version 2 for more details (a copy is included in the LICENSE file that
-# accompanied this code).
-#
-# You should have received a copy of the GNU General Public License version
-# 2 along with this work; if not, write to the Free Software Foundation,
-# Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
-#
-# Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
-# or visit www.oracle.com if you need additional information or have any
-# questions.
-#
-
-# This script copies part of an Xcode installer into a devkit suitable
-# for building OpenJDK and OracleJDK. The installation .dmg files for Xcode
-# and the aux tools need to be available.
-# erik.joelsson@oracle.com
-
-USAGE="$0 []"
-
-if [ "$1" = "" ] || [ "$2" = "" ]; then
- echo $USAGE
- exit 1
-fi
-
-XCODE_DMG="$1"
-XQUARTZ_DMG="$2"
-GNU_MAKE="$3"
-AUXTOOLS_DMG="$4"
-
-SCRIPT_DIR="$(cd "$(dirname $0)" > /dev/null && pwd)"
-BUILD_DIR="${SCRIPT_DIR}/../../build/devkit"
-
-# Mount XCODE_DMG
-if [ -e "/Volumes/Xcode" ]; then
- hdiutil detach /Volumes/Xcode
-fi
-hdiutil attach $XCODE_DMG
-
-# Find the version of Xcode
-XCODE_VERSION="$(/Volumes/Xcode/Xcode.app/Contents/Developer/usr/bin/xcodebuild -version \
- | awk '/Xcode/ { print $2 }' )"
-SDK_VERSION="MacOSX10.9"
-if [ ! -e "/Volumes/Xcode/Xcode.app/Contents/Developer/Platforms/MacOSX.platform/Developer/SDKs/${SDK_VERSION}.sdk" ]; then
- echo "Expected SDK version not found: ${SDK_VERSION}"
- exit 1
-fi
-
-DEVKIT_ROOT="${BUILD_DIR}/Xcode${XCODE_VERSION}-${SDK_VERSION}"
-DEVKIT_BUNDLE="${DEVKIT_ROOT}.tar.gz"
-
-echo "Xcode version: $XCODE_VERSION"
-echo "Creating devkit in $DEVKIT_ROOT"
-
-################################################################################
-# Copy files to root
-mkdir -p $DEVKIT_ROOT
-if [ ! -d $DEVKIT_ROOT/Xcode.app ]; then
- echo "Copying Xcode.app..."
- cp -RH "/Volumes/Xcode/Xcode.app" $DEVKIT_ROOT/
-fi
-# Trim out some seemingly unneeded parts to save space.
-rm -rf $DEVKIT_ROOT/Xcode.app/Contents/Applications
-rm -rf $DEVKIT_ROOT/Xcode.app/Contents/Developer/Platforms/iPhone*
-rm -rf $DEVKIT_ROOT/Xcode.app/Contents/Developer/Documentation
-rm -rf $DEVKIT_ROOT/Xcode.app/Contents/Developer/usr/share/man
-( cd $DEVKIT_ROOT/Xcode.app/Contents/Developer/Platforms/MacOSX.platform/Developer/SDKs \
- && rm -rf `ls | grep -v ${SDK_VERSION}` )
-rm -rf $DEVKIT_ROOT/Xcode.app/Contents/Developer/Platforms/MacOSX.platform/Developer/SDKs/${SDK_VERSION}.sdk/usr/share/man
-
-hdiutil detach /Volumes/Xcode
-
-################################################################################
-# Copy Freetype into sysroot
-if [ -e "/Volumes/XQuartz-*" ]; then
- hdiutil detach /Volumes/XQuartz-*
-fi
-hdiutil attach $XQUARTZ_DMG
-
-echo "Copying freetype..."
-rm -rf /tmp/XQuartz
-pkgutil --expand /Volumes/XQuartz-*/XQuartz.pkg /tmp/XQuartz/
-rm -rf /tmp/x11
-mkdir /tmp/x11
-cd /tmp/x11
-cat /tmp/XQuartz/x11.pkg/Payload | gunzip -dc | cpio -i
-
-mkdir -p $DEVKIT_ROOT/Xcode.app/Contents/Developer/Platforms/MacOSX.platform/Developer/SDKs/MacOSX10.9.sdk/usr/X11/include/
-mkdir -p $DEVKIT_ROOT/Xcode.app/Contents/Developer/Platforms/MacOSX.platform/Developer/SDKs/MacOSX10.9.sdk/usr/X11/lib/
-cp -RH opt/X11/include/freetype2 \
- $DEVKIT_ROOT/Xcode.app/Contents/Developer/Platforms/MacOSX.platform/Developer/SDKs/MacOSX10.9.sdk/usr/X11/include/
-cp -RH opt/X11/include/ft2build.h \
- $DEVKIT_ROOT/Xcode.app/Contents/Developer/Platforms/MacOSX.platform/Developer/SDKs/MacOSX10.9.sdk/usr/X11/include/
-cp -RH opt/X11/lib/libfreetype.* \
- $DEVKIT_ROOT/Xcode.app/Contents/Developer/Platforms/MacOSX.platform/Developer/SDKs/MacOSX10.9.sdk/usr/X11/lib/
-
-cd -
-
-hdiutil detach /Volumes/XQuartz-*
-
-################################################################################
-# Copy gnu make
-mkdir -p $DEVKIT_ROOT/bin
-cp $GNU_MAKE $DEVKIT_ROOT/bin
-
-################################################################################
-# Optionally copy PackageMaker
-
-if [ -e "$AUXTOOLS_DMG" ]; then
- if [ -e "/Volumes/Auxiliary Tools" ]; then
- hdiutil detach "/Volumes/Auxiliary Tools"
- fi
- hdiutil attach $AUXTOOLS_DMG
-
- echo "Copying PackageMaker.app..."
- cp -RH "/Volumes/Auxiliary Tools/PackageMaker.app" $DEVKIT_ROOT/
-
- hdiutil detach "/Volumes/Auxiliary Tools"
-fi
-
-################################################################################
-# Generate devkit.info
-
-echo-info() {
- echo "$1" >> $DEVKIT_ROOT/devkit.info
-}
-
-echo "Generating devkit.info..."
-rm -f $DEVKIT_ROOT/devkit.info
-echo-info "# This file describes to configure how to interpret the contents of this devkit"
-echo-info "# The parameters used to create this devkit were:"
-echo-info "# $*"
-echo-info "DEVKIT_NAME=\"Xcode $XCODE_VERSION (devkit)\""
-echo-info "DEVKIT_TOOLCHAIN_PATH=\"\$DEVKIT_ROOT/Xcode.app/Contents/Developer/Toolchains/XcodeDefault.xctoolchain/usr/bin:\$DEVKIT_ROOT/Xcode.app/Contents/Developer/usr/bin\""
-echo-info "DEVKIT_SYSROOT=\"\$DEVKIT_ROOT/Xcode.app/Contents/Developer/Platforms/MacOSX.platform/Developer/SDKs/MacOSX10.9.sdk\""
-echo-info "DEVKIT_EXTRA_PATH=\"\$DEVKIT_ROOT/bin:\$DEVKIT_ROOT/PackageMaker.app/Contents/MacOS:\$DEVKIT_TOOLCHAIN_PATH\""
-
-################################################################################
-# Copy this script
-
-echo "Copying this script..."
-cp $0 $DEVKIT_ROOT/
-
-################################################################################
-# Create bundle
-
-echo "Creating bundle..."
-(cd $DEVKIT_ROOT && tar c - . | gzip - > "$DEVKIT_BUNDLE")
diff -Nru openjdk-lts-11.0.11+9/make/devkit/createMacosxDevkit9.sh openjdk-lts-11.0.14+9/make/devkit/createMacosxDevkit9.sh
--- openjdk-lts-11.0.11+9/make/devkit/createMacosxDevkit9.sh 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/make/devkit/createMacosxDevkit9.sh 1970-01-01 00:00:00.000000000 +0000
@@ -1,146 +0,0 @@
-#!/bin/bash
-#
-# Copyright (c) 2015, 2018, Oracle and/or its affiliates. All rights reserved.
-# DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
-#
-# This code is free software; you can redistribute it and/or modify it
-# under the terms of the GNU General Public License version 2 only, as
-# published by the Free Software Foundation. Oracle designates this
-# particular file as subject to the "Classpath" exception as provided
-# by Oracle in the LICENSE file that accompanied this code.
-#
-# This code is distributed in the hope that it will be useful, but WITHOUT
-# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-# version 2 for more details (a copy is included in the LICENSE file that
-# accompanied this code).
-#
-# You should have received a copy of the GNU General Public License version
-# 2 along with this work; if not, write to the Free Software Foundation,
-# Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
-#
-# Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
-# or visit www.oracle.com if you need additional information or have any
-# questions.
-#
-
-# This script copies parts of an Xcode installation into a devkit suitable
-# for building OpenJDK and OracleJDK. The installation Xcode_X.X.xip needs
-# to be either installed or extracted using for example Archive Utility.
-# The easiest way to accomplish this is to right click the file in Finder
-# and choose "Open With -> Archive Utility", or possible typing
-# "open Xcode_9.2.xip" in a terminal.
-# erik.joelsson@oracle.com
-
-USAGE="$0 "
-
-if [ "$1" = "" ]; then
- echo $USAGE
- exit 1
-fi
-
-XCODE_APP="$1"
-XCODE_APP_DIR_NAME="${XCODE_APP##*/}"
-
-SCRIPT_DIR="$(cd "$(dirname $0)" > /dev/null && pwd)"
-BUILD_DIR="${SCRIPT_DIR}/../../build/devkit"
-
-# Find the version of Xcode
-XCODE_VERSION="$($XCODE_APP/Contents/Developer/usr/bin/xcodebuild -version \
- | awk '/Xcode/ { print $2 }' )"
-SDK_VERSION="MacOSX10.13"
-if [ ! -e "$XCODE_APP/Contents/Developer/Platforms/MacOSX.platform/Developer/SDKs/${SDK_VERSION}.sdk" ]; then
- echo "Expected SDK version not found: ${SDK_VERSION}"
- exit 1
-fi
-
-DEVKIT_ROOT="${BUILD_DIR}/Xcode${XCODE_VERSION}-${SDK_VERSION}"
-DEVKIT_BUNDLE="${DEVKIT_ROOT}.tar.gz"
-
-echo "Xcode version: $XCODE_VERSION"
-echo "Creating devkit in $DEVKIT_ROOT"
-
-mkdir -p $DEVKIT_ROOT
-
-################################################################################
-# Copy the relevant parts of Xcode.app, removing things that are both big and
-# unecessary for our purposes, without building an impossibly long exclude list.
-#
-# Not including WatchSimulator.platform makes ibtool crashes in some situations.
-# It doesn't seem to matter which extra platform is included, but that is the
-# smallest one.
-
-EXCLUDE_DIRS=" \
- Contents/_CodeSignature \
- $XCODE_APP_DIR_NAME/Contents/Applications \
- $XCODE_APP_DIR_NAME/Contents/Resources \
- $XCODE_APP_DIR_NAME/Contents/Library \
- $XCODE_APP_DIR_NAME/Contents/XPCServices \
- $XCODE_APP_DIR_NAME/Contents/OtherFrameworks \
- $XCODE_APP_DIR_NAME/Contents/Developer/Documentation \
- $XCODE_APP_DIR_NAME/Contents/Developer/usr/share \
- $XCODE_APP_DIR_NAME/Contents/Developer/usr/libexec/git-core \
- $XCODE_APP_DIR_NAME/Contents/Developer/usr/bin/git* \
- $XCODE_APP_DIR_NAME/Contents/Developer/usr/bin/svn* \
- $XCODE_APP_DIR_NAME/Contents/Developer/usr/lib/libgit* \
- $XCODE_APP_DIR_NAME/Contents/Developer/usr/lib/libsvn* \
- $XCODE_APP_DIR_NAME/Contents/Developer/Platforms/MacOSX.platform/Developer/SDKs/MacOSX.sdk/usr/share/man \
- $XCODE_APP_DIR_NAME/Contents/Developer/Platforms/MacOSX.platform/Developer/SDKs/${SDK_VERSION}.sdk/usr/share/man \
- $XCODE_APP_DIR_NAME/Contents/Developer/Platforms/MacOSX.platform/Developer/usr/share/man \
- $XCODE_APP_DIR_NAME/Contents/Developer/Platforms/MacOSX.platform/usr \
- $XCODE_APP_DIR_NAME/Contents/Developer/Toolchains/XcodeDefault.xctoolchain/usr/share/man \
- $XCODE_APP_DIR_NAME/Contents/Developer/Toolchains/XcodeDefault.xctoolchain/usr/bin/swift* \
- $XCODE_APP_DIR_NAME/Contents/Developer/Toolchains/XcodeDefault.xctoolchain/usr/lib/swift* \
- $XCODE_APP_DIR_NAME/Contents/Developer/Toolchains/XcodeDefault.xctoolchain/usr/lib/sourcekitd.framework \
- $XCODE_APP_DIR_NAME/Contents/Developer/Toolchains/XcodeDefault.xctoolchain/usr/libexec/swift* \
- $XCODE_APP_DIR_NAME/Contents/Developer/Toolchains/XcodeDefault.xctoolchain/usr/include/swift* \
- $XCODE_APP_DIR_NAME/Contents/Developer/Toolchains/XcodeDefault.xctoolchain/usr/arc \
- Platforms/AppleTVSimulator.platform \
- Platforms/iPhoneSimulator.platform \
- $XCODE_APP_DIR_NAME/Contents/SharedFrameworks/LLDB.framework \
- $XCODE_APP_DIR_NAME/Contents/SharedFrameworks/ModelIO.framework \
- $XCODE_APP_DIR_NAME/Contents/SharedFrameworks/XCSUI.framework \
- $XCODE_APP_DIR_NAME/Contents/SharedFrameworks/SceneKit.framework \
- $XCODE_APP_DIR_NAME/Contents/SharedFrameworks/XCBuild.framework \
- $XCODE_APP_DIR_NAME/Contents/SharedFrameworks/GPUTools.framework \
- $(cd $XCODE_APP/.. && ls -d $XCODE_APP_DIR_NAME/Contents/Developer/Platforms/* \
- | grep -v MacOSX.platform | grep -v WatchSimulator.platform) \
-"
-
-for ex in $EXCLUDE_DIRS; do
- EXCLUDE_ARGS+="--exclude=$ex "
-done
-
-echo "Copying Xcode.app..."
-echo rsync -rlH $INCLUDE_ARGS $EXCLUDE_ARGS "$XCODE_APP" $DEVKIT_ROOT/
-rsync -rlH $INCLUDE_ARGS $EXCLUDE_ARGS "$XCODE_APP" $DEVKIT_ROOT/
-
-################################################################################
-
-echo-info() {
- echo "$1" >> $DEVKIT_ROOT/devkit.info
-}
-
-echo "Generating devkit.info..."
-rm -f $DEVKIT_ROOT/devkit.info
-echo-info "# This file describes to configure how to interpret the contents of this devkit"
-echo-info "DEVKIT_NAME=\"Xcode $XCODE_VERSION (devkit)\""
-echo-info "DEVKIT_TOOLCHAIN_PATH=\"\$DEVKIT_ROOT/Xcode.app/Contents/Developer/Toolchains/XcodeDefault.xctoolchain/usr/bin:\$DEVKIT_ROOT/Xcode.app/Contents/Developer/usr/bin\""
-echo-info "DEVKIT_SYSROOT=\"\$DEVKIT_ROOT/Xcode.app/Contents/Developer/Platforms/MacOSX.platform/Developer/SDKs/$SDK_VERSION.sdk\""
-echo-info "DEVKIT_EXTRA_PATH=\"\$DEVKIT_TOOLCHAIN_PATH\""
-
-################################################################################
-# Copy this script
-
-echo "Copying this script..."
-cp $0 $DEVKIT_ROOT/
-
-################################################################################
-# Create bundle
-
-echo "Creating bundle..."
-GZIP=$(command -v pigz)
-if [ -z "$GZIP" ]; then
- GZIP="gzip"
-fi
-(cd $DEVKIT_ROOT && tar c - . | $GZIP - > "$DEVKIT_BUNDLE")
diff -Nru openjdk-lts-11.0.11+9/make/devkit/createMacosxDevkit.sh openjdk-lts-11.0.14+9/make/devkit/createMacosxDevkit.sh
--- openjdk-lts-11.0.11+9/make/devkit/createMacosxDevkit.sh 1970-01-01 00:00:00.000000000 +0000
+++ openjdk-lts-11.0.14+9/make/devkit/createMacosxDevkit.sh 2022-01-13 21:56:25.000000000 +0000
@@ -0,0 +1,141 @@
+#!/bin/bash
+#
+# Copyright (c) 2015, 2020, Oracle and/or its affiliates. All rights reserved.
+# DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+#
+# This code is free software; you can redistribute it and/or modify it
+# under the terms of the GNU General Public License version 2 only, as
+# published by the Free Software Foundation. Oracle designates this
+# particular file as subject to the "Classpath" exception as provided
+# by Oracle in the LICENSE file that accompanied this code.
+#
+# This code is distributed in the hope that it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+# version 2 for more details (a copy is included in the LICENSE file that
+# accompanied this code).
+#
+# You should have received a copy of the GNU General Public License version
+# 2 along with this work; if not, write to the Free Software Foundation,
+# Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
+#
+# Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
+# or visit www.oracle.com if you need additional information or have any
+# questions.
+#
+
+# This script copies parts of an Xcode installation into a devkit suitable
+# for building OpenJDK and OracleJDK. The installation Xcode_X.X.xip needs
+# to be either installed or extracted using for example Archive Utility.
+# The easiest way to accomplish this is to right click the file in Finder
+# and choose "Open With -> Archive Utility", or possible typing
+# "open Xcode_9.2.xip" in a terminal.
+# erik.joelsson@oracle.com
+
+USAGE="$0 "
+
+if [ "$1" = "" ]; then
+ echo $USAGE
+ exit 1
+fi
+
+XCODE_APP="$1"
+XCODE_APP_DIR_NAME="${XCODE_APP##*/}"
+
+SCRIPT_DIR="$(cd "$(dirname $0)" > /dev/null && pwd)"
+BUILD_DIR="${SCRIPT_DIR}/../../build/devkit"
+
+# Find the version of Xcode
+XCODE_VERSION="$($XCODE_APP/Contents/Developer/usr/bin/xcodebuild -version \
+ | awk '/Xcode/ { print $2 }' )"
+SDK_VERSION="$(ls $XCODE_APP/Contents/Developer/Platforms/MacOSX.platform/Developer/SDKs \
+ | grep [0-9] | sort -r | head -n1 | sed 's/\.sdk//')"
+
+DEVKIT_ROOT="${BUILD_DIR}/Xcode${XCODE_VERSION}-${SDK_VERSION}"
+DEVKIT_BUNDLE="${DEVKIT_ROOT}.tar.gz"
+
+echo "Xcode version: $XCODE_VERSION"
+echo "SDK version: $SDK_VERSION"
+echo "Creating devkit in $DEVKIT_ROOT"
+
+mkdir -p $DEVKIT_ROOT
+
+################################################################################
+# Copy the relevant parts of Xcode.app, removing things that are both big and
+# unecessary for our purposes, without building an impossibly long exclude list.
+EXCLUDE_DIRS=" \
+ Contents/_CodeSignature \
+ Contents/Applications \
+ Contents/Resources \
+ Contents/Library \
+ Contents/XPCServices \
+ Contents/OtherFrameworks \
+ Contents/Developer/Documentation \
+ Contents/Developer/usr/share \
+ Contents/Developer/usr/libexec/git-core \
+ Contents/Developer/usr/bin/git* \
+ Contents/Developer/usr/bin/svn* \
+ Contents/Developer/usr/lib/libgit* \
+ Contents/Developer/usr/lib/libsvn* \
+ Contents/Developer/Platforms/MacOSX.platform/Developer/SDKs/MacOSX.sdk/usr/share/man \
+ Contents/Developer/Platforms/MacOSX.platform/Developer/SDKs/${SDK_VERSION}.sdk/usr/share/man \
+ Contents/Developer/Platforms/MacOSX.platform/Developer/usr/share/man \
+ Contents/Developer/Platforms/MacOSX.platform/usr \
+ Contents/Developer/Toolchains/XcodeDefault.xctoolchain/usr/share/man \
+ Contents/Developer/Toolchains/XcodeDefault.xctoolchain/usr/bin/swift* \
+ Contents/Developer/Toolchains/XcodeDefault.xctoolchain/usr/lib/swift* \
+ Contents/Developer/Toolchains/XcodeDefault.xctoolchain/usr/lib/sourcekitd.framework \
+ Contents/Developer/Toolchains/XcodeDefault.xctoolchain/usr/libexec/swift* \
+ Contents/Developer/Toolchains/XcodeDefault.xctoolchain/usr/include/swift* \
+ Contents/Developer/Toolchains/XcodeDefault.xctoolchain/usr/arc \
+ Platforms/AppleTVSimulator.platform \
+ Platforms/iPhoneSimulator.platform \
+ Platforms/WatchSimulator.platform \
+ Contents/SharedFrameworks/LLDB.framework \
+ Contents/SharedFrameworks/ModelIO.framework \
+ Contents/SharedFrameworks/XCSUI.framework \
+ Contents/SharedFrameworks/SceneKit.framework \
+ Contents/SharedFrameworks/XCBuild.framework \
+ Contents/SharedFrameworks/GPUTools*.framework \
+ Contents/SharedFrameworks/DNTDocumentationSupport.framework/Versions/A/Resources/external \
+ $(cd $XCODE_APP && ls -d Contents/Developer/Platforms/* \
+ | grep -v MacOSX.platform | grep -v WatchSimulator.platform) \
+"
+
+for ex in $EXCLUDE_DIRS; do
+ EXCLUDE_ARGS+="--exclude=$ex "
+done
+
+echo "Copying Xcode.app..."
+echo rsync -rlH $INCLUDE_ARGS $EXCLUDE_ARGS "$XCODE_APP/." $DEVKIT_ROOT/Xcode.app/
+rsync -rlH $INCLUDE_ARGS $EXCLUDE_ARGS "$XCODE_APP/." $DEVKIT_ROOT/Xcode.app/
+
+################################################################################
+
+echo-info() {
+ echo "$1" >> $DEVKIT_ROOT/devkit.info
+}
+
+echo "Generating devkit.info..."
+rm -f $DEVKIT_ROOT/devkit.info
+echo-info "# This file describes to configure how to interpret the contents of this devkit"
+echo-info "DEVKIT_NAME=\"Xcode $XCODE_VERSION (devkit)\""
+echo-info "DEVKIT_TOOLCHAIN_PATH=\"\$DEVKIT_ROOT/Xcode.app/Contents/Developer/Toolchains/XcodeDefault.xctoolchain/usr/bin:\$DEVKIT_ROOT/Xcode.app/Contents/Developer/usr/bin\""
+echo-info "DEVKIT_SYSROOT=\"\$DEVKIT_ROOT/Xcode.app/Contents/Developer/Platforms/MacOSX.platform/Developer/SDKs/$SDK_VERSION.sdk\""
+echo-info "DEVKIT_EXTRA_PATH=\"\$DEVKIT_TOOLCHAIN_PATH\""
+
+################################################################################
+# Copy this script
+
+echo "Copying this script..."
+cp $0 $DEVKIT_ROOT/
+
+################################################################################
+# Create bundle
+
+echo "Creating bundle..."
+GZIP=$(command -v pigz)
+if [ -z "$GZIP" ]; then
+ GZIP="gzip"
+fi
+(cd $DEVKIT_ROOT && tar c - . | $GZIP - > "$DEVKIT_BUNDLE")
diff -Nru openjdk-lts-11.0.11+9/make/devkit/createWindowsDevkit2017.sh openjdk-lts-11.0.14+9/make/devkit/createWindowsDevkit2017.sh
--- openjdk-lts-11.0.11+9/make/devkit/createWindowsDevkit2017.sh 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/make/devkit/createWindowsDevkit2017.sh 2022-01-13 21:56:25.000000000 +0000
@@ -89,19 +89,23 @@
REDIST_SUBDIR="VC/Redist/MSVC/14.12.25810"
echo "Copying VC..."
mkdir -p $DEVKIT_ROOT/VC/bin
+ cp -r "$VS_INSTALL_DIR/${VC_SUBDIR}/bin/Hostx64/arm64" $DEVKIT_ROOT/VC/bin/
cp -r "$VS_INSTALL_DIR/${VC_SUBDIR}/bin/Hostx64/x64" $DEVKIT_ROOT/VC/bin/
cp -r "$VS_INSTALL_DIR/${VC_SUBDIR}/bin/Hostx86/x86" $DEVKIT_ROOT/VC/bin/
mkdir -p $DEVKIT_ROOT/VC/lib
+ cp -r "$VS_INSTALL_DIR/${VC_SUBDIR}/lib/arm64" $DEVKIT_ROOT/VC/lib/
cp -r "$VS_INSTALL_DIR/${VC_SUBDIR}/lib/x64" $DEVKIT_ROOT/VC/lib/
cp -r "$VS_INSTALL_DIR/${VC_SUBDIR}/lib/x86" $DEVKIT_ROOT/VC/lib/
cp -r "$VS_INSTALL_DIR/${VC_SUBDIR}/include" $DEVKIT_ROOT/VC/
mkdir -p $DEVKIT_ROOT/VC/atlmfc/lib
+ cp -r "$VS_INSTALL_DIR/${VC_SUBDIR}/atlmfc/lib/arm64" $DEVKIT_ROOT/VC/atlmfc/lib/
cp -r "$VS_INSTALL_DIR/${VC_SUBDIR}/atlmfc/lib/x64" $DEVKIT_ROOT/VC/atlmfc/lib/
cp -r "$VS_INSTALL_DIR/${VC_SUBDIR}/atlmfc/lib/x86" $DEVKIT_ROOT/VC/atlmfc/lib/
cp -r "$VS_INSTALL_DIR/${VC_SUBDIR}/atlmfc/include" $DEVKIT_ROOT/VC/atlmfc/
mkdir -p $DEVKIT_ROOT/VC/Auxiliary
cp -r "$VS_INSTALL_DIR/VC/Auxiliary/Build" $DEVKIT_ROOT/VC/Auxiliary/
mkdir -p $DEVKIT_ROOT/VC/redist
+ cp -r "$VS_INSTALL_DIR/$REDIST_SUBDIR/arm64" $DEVKIT_ROOT/VC/redist/
cp -r "$VS_INSTALL_DIR/$REDIST_SUBDIR/x64" $DEVKIT_ROOT/VC/redist/
cp -r "$VS_INSTALL_DIR/$REDIST_SUBDIR/x86" $DEVKIT_ROOT/VC/redist/
@@ -111,6 +115,8 @@
cp $DEVKIT_ROOT/VC/redist/x86/$MSVCP_DLL $DEVKIT_ROOT/VC/bin/x86
cp $DEVKIT_ROOT/VC/redist/x64/$MSVCR_DLL $DEVKIT_ROOT/VC/bin/x64
cp $DEVKIT_ROOT/VC/redist/x64/$MSVCP_DLL $DEVKIT_ROOT/VC/bin/x64
+ cp $DEVKIT_ROOT/VC/redist/arm64/$MSVCR_DLL $DEVKIT_ROOT/VC/bin/arm64
+ cp $DEVKIT_ROOT/VC/redist/arm64/$MSVCP_DLL $DEVKIT_ROOT/VC/bin/arm64
fi
################################################################################
@@ -128,8 +134,10 @@
cp -r "$SDK_INSTALL_DIR/bin/$SDK_FULL_VERSION/x64" $DEVKIT_ROOT/$SDK_VERSION/bin/
cp -r "$SDK_INSTALL_DIR/bin/$SDK_FULL_VERSION/x86" $DEVKIT_ROOT/$SDK_VERSION/bin/
mkdir -p $DEVKIT_ROOT/$SDK_VERSION/lib
+ cp -r "$SDK_INSTALL_DIR/lib/$SDK_FULL_VERSION/um/arm64" $DEVKIT_ROOT/$SDK_VERSION/lib/
cp -r "$SDK_INSTALL_DIR/lib/$SDK_FULL_VERSION/um/x64" $DEVKIT_ROOT/$SDK_VERSION/lib/
cp -r "$SDK_INSTALL_DIR/lib/$SDK_FULL_VERSION/um/x86" $DEVKIT_ROOT/$SDK_VERSION/lib/
+ cp -r "$SDK_INSTALL_DIR/lib/$SDK_FULL_VERSION/ucrt/arm64" $DEVKIT_ROOT/$SDK_VERSION/lib/
cp -r "$SDK_INSTALL_DIR/lib/$SDK_FULL_VERSION/ucrt/x64" $DEVKIT_ROOT/$SDK_VERSION/lib/
cp -r "$SDK_INSTALL_DIR/lib/$SDK_FULL_VERSION/ucrt/x86" $DEVKIT_ROOT/$SDK_VERSION/lib/
mkdir -p $DEVKIT_ROOT/$SDK_VERSION/Redist
@@ -164,6 +172,13 @@
echo-info "DEVKIT_MSVCR_DLL_x86_64=\"\$DEVKIT_ROOT/VC/redist/x64/$MSVCR_DLL\""
echo-info "DEVKIT_MSVCP_DLL_x86_64=\"\$DEVKIT_ROOT/VC/redist/x64/$MSVCP_DLL\""
echo-info "DEVKIT_UCRT_DLL_DIR_x86_64=\"\$DEVKIT_ROOT/10/Redist/ucrt/DLLs/x64\""
+echo-info ""
+echo-info "DEVKIT_TOOLCHAIN_PATH_aarch64=\"\$DEVKIT_ROOT/VC/bin/arm64:\$DEVKIT_ROOT/$SDK_VERSION/bin/x64:\$DEVKIT_ROOT/$SDK_VERSION/bin/x86\""
+echo-info "DEVKIT_VS_INCLUDE_aarch64=\"\$DEVKIT_ROOT/VC/include;\$DEVKIT_ROOT/VC/atlmfc/include;\$DEVKIT_ROOT/$SDK_VERSION/include/shared;\$DEVKIT_ROOT/$SDK_VERSION/include/ucrt;\$DEVKIT_ROOT/$SDK_VERSION/include/um;\$DEVKIT_ROOT/$SDK_VERSION/include/winrt\""
+echo-info "DEVKIT_VS_LIB_aarch64=\"\$DEVKIT_ROOT/VC/lib/arm64;\$DEVKIT_ROOT/VC/atlmfc/lib/arm64;\$DEVKIT_ROOT/$SDK_VERSION/lib/arm64\""
+echo-info "DEVKIT_MSVCR_DLL_aarch64=\"\$DEVKIT_ROOT/VC/redist/arm64/$MSVCR_DLL\""
+echo-info "DEVKIT_MSVCP_DLL_aarch64=\"\$DEVKIT_ROOT/VC/redist/arm64/$MSVCP_DLL\""
+echo-info "DEVKIT_UCRT_DLL_DIR_aarch64=\"\$DEVKIT_ROOT/10/Redist/ucrt/DLLs/arm64\""
################################################################################
# Copy this script
diff -Nru openjdk-lts-11.0.11+9/make/devkit/createWindowsDevkit2019.sh openjdk-lts-11.0.14+9/make/devkit/createWindowsDevkit2019.sh
--- openjdk-lts-11.0.11+9/make/devkit/createWindowsDevkit2019.sh 1970-01-01 00:00:00.000000000 +0000
+++ openjdk-lts-11.0.14+9/make/devkit/createWindowsDevkit2019.sh 2022-01-13 21:56:25.000000000 +0000
@@ -0,0 +1,209 @@
+#!/bin/bash
+#
+# Copyright (c) 2019, Oracle and/or its affiliates. All rights reserved.
+# DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+#
+# This code is free software; you can redistribute it and/or modify it
+# under the terms of the GNU General Public License version 2 only, as
+# published by the Free Software Foundation. Oracle designates this
+# particular file as subject to the "Classpath" exception as provided
+# by Oracle in the LICENSE file that accompanied this code.
+#
+# This code is distributed in the hope that it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+# version 2 for more details (a copy is included in the LICENSE file that
+# accompanied this code).
+#
+# You should have received a copy of the GNU General Public License version
+# 2 along with this work; if not, write to the Free Software Foundation,
+# Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
+#
+# Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
+# or visit www.oracle.com if you need additional information or have any
+# questions.
+#
+
+# This script copies parts of a Visual Studio installation into a devkit
+# suitable for building OpenJDK and OracleJDK. Needs to run in Cygwin or WSL.
+# erik.joelsson@oracle.com
+
+VS_VERSION="2019"
+VS_VERSION_NUM_NODOT="160"
+VS_DLL_VERSION="140"
+SDK_VERSION="10"
+SDK_FULL_VERSION="10.0.17763.0"
+MSVC_DIR="Microsoft.VC141.CRT"
+MSVC_FULL_VERSION="14.12.27508"
+REDIST_FULL_VERSION="14.20.27508"
+
+SCRIPT_DIR="$(cd "$(dirname $0)" > /dev/null && pwd)"
+BUILD_DIR="${SCRIPT_DIR}/../../build/devkit"
+
+################################################################################
+# Prepare settings
+
+UNAME_SYSTEM=`uname -s`
+UNAME_RELEASE=`uname -r`
+
+# Detect cygwin or WSL
+IS_CYGWIN=`echo $UNAME_SYSTEM | grep -i CYGWIN`
+IS_WSL=`echo $UNAME_RELEASE | grep Microsoft`
+if test "x$IS_CYGWIN" != "x"; then
+ BUILD_ENV="cygwin"
+elif test "x$IS_WSL" != "x"; then
+ BUILD_ENV="wsl"
+else
+ echo "Unknown environment; only Cygwin and WSL are supported."
+ exit 1
+fi
+
+if test "x$BUILD_ENV" = "xcygwin"; then
+ WINDOWS_PATH_TO_UNIX_PATH="cygpath -u"
+elif test "x$BUILD_ENV" = "xwsl"; then
+ WINDOWS_PATH_TO_UNIX_PATH="wslpath -u"
+fi
+
+# Work around the insanely named ProgramFiles(x86) env variable
+PROGRAMFILES_X86="$($WINDOWS_PATH_TO_UNIX_PATH "$(cmd.exe /c set | sed -n 's/^ProgramFiles(x86)=//p' | tr -d '\r')")"
+
+# Find Visual Studio installation dir
+VSNNNCOMNTOOLS=`cmd.exe /c echo %VS${VS_VERSION_NUM_NODOT}COMNTOOLS% | tr -d '\r'`
+if [ -d "$VSNNNCOMNTOOLS" ]; then
+ VS_INSTALL_DIR="$($WINDOWS_PATH_TO_UNIX_PATH "$VSNNNCOMNTOOLS/../..")"
+else
+ VS_INSTALL_DIR="${PROGRAMFILES_X86}/Microsoft Visual Studio/2019"
+ VS_INSTALL_DIR="$(ls -d "${VS_INSTALL_DIR}/"{Community,Professional,Enterprise} 2>/dev/null | head -n1)"
+fi
+echo "VS_INSTALL_DIR: $VS_INSTALL_DIR"
+
+# Extract semantic version
+POTENTIAL_INI_FILES="Common7/IDE/wdexpress.isolation.ini Common7/IDE/devenv.isolation.ini"
+for f in $POTENTIAL_INI_FILES; do
+ if [ -f "$VS_INSTALL_DIR/$f" ]; then
+ VS_VERSION_SP="$(grep ^SemanticVersion= "$VS_INSTALL_DIR/$f")"
+ # Remove SemnaticVersion=
+ VS_VERSION_SP="${VS_VERSION_SP#*=}"
+ # Remove suffix of too detailed numbering starting with +
+ VS_VERSION_SP="${VS_VERSION_SP%+*}"
+ break
+ fi
+done
+if [ -z "$VS_VERSION_SP" ]; then
+ echo "Failed to find SP version"
+ exit 1
+fi
+echo "Found Version SP: $VS_VERSION_SP"
+
+# Setup output dirs
+DEVKIT_ROOT="${BUILD_DIR}/VS${VS_VERSION}-${VS_VERSION_SP}-devkit"
+DEVKIT_BUNDLE="${DEVKIT_ROOT}.tar.gz"
+
+echo "Creating devkit in $DEVKIT_ROOT"
+
+MSVCR_DLL=${MSVC_DIR}/vcruntime${VS_DLL_VERSION}.dll
+MSVCP_DLL=${MSVC_DIR}/msvcp${VS_DLL_VERSION}.dll
+
+################################################################################
+# Copy Visual Studio files
+
+TOOLS_VERSION="$(ls "$VS_INSTALL_DIR/VC/Tools/MSVC" | sort -r -n | head -n1)"
+echo "Found Tools version: $TOOLS_VERSION"
+VC_SUBDIR="VC/Tools/MSVC/$TOOLS_VERSION"
+REDIST_VERSION="$(ls "$VS_INSTALL_DIR/VC/Redist/MSVC" | sort -r -n | head -n1)"
+echo "Found Redist version: $REDIST_VERSION"
+REDIST_SUBDIR="VC/Redist/MSVC/$REDIST_VERSION"
+echo "Copying VC..."
+rm -rf $DEVKIT_ROOT/VC
+mkdir -p $DEVKIT_ROOT/VC/bin
+cp -r "$VS_INSTALL_DIR/${VC_SUBDIR}/bin/Hostx64/x64" $DEVKIT_ROOT/VC/bin/
+cp -r "$VS_INSTALL_DIR/${VC_SUBDIR}/bin/Hostx86/x86" $DEVKIT_ROOT/VC/bin/
+mkdir -p $DEVKIT_ROOT/VC/lib
+cp -r "$VS_INSTALL_DIR/${VC_SUBDIR}/lib/x64" $DEVKIT_ROOT/VC/lib/
+cp -r "$VS_INSTALL_DIR/${VC_SUBDIR}/lib/x86" $DEVKIT_ROOT/VC/lib/
+cp -r "$VS_INSTALL_DIR/${VC_SUBDIR}/include" $DEVKIT_ROOT/VC/
+mkdir -p $DEVKIT_ROOT/VC/atlmfc/lib
+cp -r "$VS_INSTALL_DIR/${VC_SUBDIR}/atlmfc/lib/x64" $DEVKIT_ROOT/VC/atlmfc/lib/
+cp -r "$VS_INSTALL_DIR/${VC_SUBDIR}/atlmfc/lib/x86" $DEVKIT_ROOT/VC/atlmfc/lib/
+cp -r "$VS_INSTALL_DIR/${VC_SUBDIR}/atlmfc/include" $DEVKIT_ROOT/VC/atlmfc/
+mkdir -p $DEVKIT_ROOT/VC/Auxiliary
+cp -r "$VS_INSTALL_DIR/VC/Auxiliary/Build" $DEVKIT_ROOT/VC/Auxiliary/
+mkdir -p $DEVKIT_ROOT/VC/redist
+cp -r "$VS_INSTALL_DIR/$REDIST_SUBDIR/x64" $DEVKIT_ROOT/VC/redist/
+cp -r "$VS_INSTALL_DIR/$REDIST_SUBDIR/x86" $DEVKIT_ROOT/VC/redist/
+
+# The redist runtime libs are needed to run the compiler but may not be
+# installed on the machine where the devkit will be used.
+cp $DEVKIT_ROOT/VC/redist/x86/$MSVCR_DLL $DEVKIT_ROOT/VC/bin/x86
+cp $DEVKIT_ROOT/VC/redist/x86/$MSVCP_DLL $DEVKIT_ROOT/VC/bin/x86
+cp $DEVKIT_ROOT/VC/redist/x64/$MSVCR_DLL $DEVKIT_ROOT/VC/bin/x64
+cp $DEVKIT_ROOT/VC/redist/x64/$MSVCP_DLL $DEVKIT_ROOT/VC/bin/x64
+
+################################################################################
+# Copy SDK files
+
+SDK_INSTALL_DIR="$PROGRAMFILES_X86/Windows Kits/$SDK_VERSION"
+echo "SDK_INSTALL_DIR: $SDK_INSTALL_DIR"
+
+SDK_FULL_VERSION="$(ls "$SDK_INSTALL_DIR/bin" | sort -r -n | head -n1)"
+echo "Found SDK version: $SDK_FULL_VERSION"
+UCRT_VERSION="$(ls "$SDK_INSTALL_DIR/Redist" | grep $SDK_VERSION | sort -r -n | head -n1)"
+echo "Found UCRT version: $UCRT_VERSION"
+echo "Copying SDK..."
+rm -rf $DEVKIT_ROOT/$SDK_VERSION
+mkdir -p $DEVKIT_ROOT/$SDK_VERSION/bin
+cp -r "$SDK_INSTALL_DIR/bin/$SDK_FULL_VERSION/x64" $DEVKIT_ROOT/$SDK_VERSION/bin/
+cp -r "$SDK_INSTALL_DIR/bin/$SDK_FULL_VERSION/x86" $DEVKIT_ROOT/$SDK_VERSION/bin/
+mkdir -p $DEVKIT_ROOT/$SDK_VERSION/lib
+cp -r "$SDK_INSTALL_DIR/lib/$SDK_FULL_VERSION/um/x64" $DEVKIT_ROOT/$SDK_VERSION/lib/
+cp -r "$SDK_INSTALL_DIR/lib/$SDK_FULL_VERSION/um/x86" $DEVKIT_ROOT/$SDK_VERSION/lib/
+cp -r "$SDK_INSTALL_DIR/lib/$SDK_FULL_VERSION/ucrt/x64" $DEVKIT_ROOT/$SDK_VERSION/lib/
+cp -r "$SDK_INSTALL_DIR/lib/$SDK_FULL_VERSION/ucrt/x86" $DEVKIT_ROOT/$SDK_VERSION/lib/
+mkdir -p $DEVKIT_ROOT/$SDK_VERSION/Redist
+cp -r "$SDK_INSTALL_DIR/Redist/$UCRT_VERSION/ucrt" $DEVKIT_ROOT/$SDK_VERSION/Redist/
+mkdir -p $DEVKIT_ROOT/$SDK_VERSION/include
+cp -r "$SDK_INSTALL_DIR/include/$SDK_FULL_VERSION/"* $DEVKIT_ROOT/$SDK_VERSION/include/
+
+################################################################################
+# Generate devkit.info
+
+echo-info() {
+ echo "$1" >> $DEVKIT_ROOT/devkit.info
+}
+
+echo "Generating devkit.info..."
+rm -f $DEVKIT_ROOT/devkit.info
+echo-info "# This file describes to configure how to interpret the contents of this devkit"
+echo-info "DEVKIT_NAME=\"Microsoft Visual Studio $VS_VERSION $VS_VERSION_SP (devkit)\""
+echo-info "DEVKIT_VS_VERSION=\"$VS_VERSION\""
+echo-info ""
+echo-info "DEVKIT_TOOLCHAIN_PATH_x86=\"\$DEVKIT_ROOT/VC/bin/x86:\$DEVKIT_ROOT/$SDK_VERSION/bin/x86\""
+echo-info "DEVKIT_VS_INCLUDE_x86=\"\$DEVKIT_ROOT/VC/include;\$DEVKIT_ROOT/VC/atlmfc/include;\$DEVKIT_ROOT/$SDK_VERSION/include/shared;\$DEVKIT_ROOT/$SDK_VERSION/include/ucrt;\$DEVKIT_ROOT/$SDK_VERSION/include/um;\$DEVKIT_ROOT/$SDK_VERSION/include/winrt\""
+echo-info "DEVKIT_VS_LIB_x86=\"\$DEVKIT_ROOT/VC/lib/x86;\$DEVKIT_ROOT/VC/atlmfc/lib/x86;\$DEVKIT_ROOT/$SDK_VERSION/lib/x86\""
+echo-info "DEVKIT_MSVCR_DLL_x86=\"\$DEVKIT_ROOT/VC/redist/x86/$MSVCR_DLL\""
+echo-info "DEVKIT_MSVCP_DLL_x86=\"\$DEVKIT_ROOT/VC/redist/x86/$MSVCP_DLL\""
+echo-info "DEVKIT_UCRT_DLL_DIR_x86=\"\$DEVKIT_ROOT/10/Redist/ucrt/DLLs/x86\""
+echo-info ""
+echo-info "DEVKIT_TOOLCHAIN_PATH_x86_64=\"\$DEVKIT_ROOT/VC/bin/x64:\$DEVKIT_ROOT/$SDK_VERSION/bin/x64:\$DEVKIT_ROOT/$SDK_VERSION/bin/x86\""
+echo-info "DEVKIT_VS_INCLUDE_x86_64=\"\$DEVKIT_ROOT/VC/include;\$DEVKIT_ROOT/VC/atlmfc/include;\$DEVKIT_ROOT/$SDK_VERSION/include/shared;\$DEVKIT_ROOT/$SDK_VERSION/include/ucrt;\$DEVKIT_ROOT/$SDK_VERSION/include/um;\$DEVKIT_ROOT/$SDK_VERSION/include/winrt\""
+echo-info "DEVKIT_VS_LIB_x86_64=\"\$DEVKIT_ROOT/VC/lib/x64;\$DEVKIT_ROOT/VC/atlmfc/lib/x64;\$DEVKIT_ROOT/$SDK_VERSION/lib/x64\""
+echo-info "DEVKIT_MSVCR_DLL_x86_64=\"\$DEVKIT_ROOT/VC/redist/x64/$MSVCR_DLL\""
+echo-info "DEVKIT_MSVCP_DLL_x86_64=\"\$DEVKIT_ROOT/VC/redist/x64/$MSVCP_DLL\""
+echo-info "DEVKIT_UCRT_DLL_DIR_x86_64=\"\$DEVKIT_ROOT/10/Redist/ucrt/DLLs/x64\""
+echo-info ""
+echo-info "DEVKIT_TOOLS_VERSION=\"$TOOLS_VERSION\""
+echo-info "DEVKIT_REDIST_VERSION=\"$REDIST_VERSION\""
+echo-info "DEVKIT_SDK_VERSION=\"$SDK_FULL_VERSION\""
+echo-info "DEVKIT_UCRT_VERSION=\"$UCRT_VERSION\""
+
+################################################################################
+# Copy this script
+
+echo "Copying this script..."
+cp $0 $DEVKIT_ROOT/
+
+################################################################################
+# Create bundle
+
+echo "Creating bundle: $DEVKIT_BUNDLE"
+(cd "$DEVKIT_ROOT" && tar zcf "$DEVKIT_BUNDLE" .)
diff -Nru openjdk-lts-11.0.11+9/make/gendata/GendataBlacklistedCerts.gmk openjdk-lts-11.0.14+9/make/gendata/GendataBlacklistedCerts.gmk
--- openjdk-lts-11.0.11+9/make/gendata/GendataBlacklistedCerts.gmk 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/make/gendata/GendataBlacklistedCerts.gmk 1970-01-01 00:00:00.000000000 +0000
@@ -1,36 +0,0 @@
-#
-# Copyright (c) 2014, 2016, Oracle and/or its affiliates. All rights reserved.
-# DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
-#
-# This code is free software; you can redistribute it and/or modify it
-# under the terms of the GNU General Public License version 2 only, as
-# published by the Free Software Foundation. Oracle designates this
-# particular file as subject to the "Classpath" exception as provided
-# by Oracle in the LICENSE file that accompanied this code.
-#
-# This code is distributed in the hope that it will be useful, but WITHOUT
-# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-# version 2 for more details (a copy is included in the LICENSE file that
-# accompanied this code).
-#
-# You should have received a copy of the GNU General Public License version
-# 2 along with this work; if not, write to the Free Software Foundation,
-# Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
-#
-# Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
-# or visit www.oracle.com if you need additional information or have any
-# questions.
-#
-
-$(eval $(call IncludeCustomExtension, gendata/GendataBlacklistedCerts.gmk))
-
-GENDATA_BLACKLISTED_CERTS_SRC += $(TOPDIR)/make/data/blacklistedcertsconverter/blacklisted.certs.pem
-GENDATA_BLACKLISTED_CERTS := $(SUPPORT_OUTPUTDIR)/modules_libs/$(MODULE)/security/blacklisted.certs
-
-$(GENDATA_BLACKLISTED_CERTS): $(BUILD_TOOLS_JDK) $(GENDATA_BLACKLISTED_CERTS_SRC)
- $(call LogInfo, Generating blacklisted certs)
- $(call MakeDir, $(@D))
- ($(CAT) $(GENDATA_BLACKLISTED_CERTS_SRC) | $(TOOL_BLACKLISTED_CERTS) > $@) || exit 1
-
-TARGETS += $(GENDATA_BLACKLISTED_CERTS)
diff -Nru openjdk-lts-11.0.11+9/make/gendata/GendataBlockedCerts.gmk openjdk-lts-11.0.14+9/make/gendata/GendataBlockedCerts.gmk
--- openjdk-lts-11.0.11+9/make/gendata/GendataBlockedCerts.gmk 1970-01-01 00:00:00.000000000 +0000
+++ openjdk-lts-11.0.14+9/make/gendata/GendataBlockedCerts.gmk 2022-01-13 21:56:25.000000000 +0000
@@ -0,0 +1,36 @@
+#
+# Copyright (c) 2014, 2021, Oracle and/or its affiliates. All rights reserved.
+# DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+#
+# This code is free software; you can redistribute it and/or modify it
+# under the terms of the GNU General Public License version 2 only, as
+# published by the Free Software Foundation. Oracle designates this
+# particular file as subject to the "Classpath" exception as provided
+# by Oracle in the LICENSE file that accompanied this code.
+#
+# This code is distributed in the hope that it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+# version 2 for more details (a copy is included in the LICENSE file that
+# accompanied this code).
+#
+# You should have received a copy of the GNU General Public License version
+# 2 along with this work; if not, write to the Free Software Foundation,
+# Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
+#
+# Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
+# or visit www.oracle.com if you need additional information or have any
+# questions.
+#
+
+$(eval $(call IncludeCustomExtension, gendata/GendataBlockedCerts.gmk))
+
+GENDATA_BLOCKED_CERTS_SRC += $(TOPDIR)/make/data/blockedcertsconverter/blocked.certs.pem
+GENDATA_BLOCKED_CERTS := $(SUPPORT_OUTPUTDIR)/modules_libs/$(MODULE)/security/blocked.certs
+
+$(GENDATA_BLOCKED_CERTS): $(BUILD_TOOLS_JDK) $(GENDATA_BLOCKED_CERTS_SRC)
+ $(call LogInfo, Generating blocked certs)
+ $(call MakeDir, $(@D))
+ ($(CAT) $(GENDATA_BLOCKED_CERTS_SRC) | $(TOOL_BLOCKED_CERTS) > $@) || exit 1
+
+TARGETS += $(GENDATA_BLOCKED_CERTS)
diff -Nru openjdk-lts-11.0.11+9/make/gendata/Gendata-java.base.gmk openjdk-lts-11.0.14+9/make/gendata/Gendata-java.base.gmk
--- openjdk-lts-11.0.11+9/make/gendata/Gendata-java.base.gmk 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/make/gendata/Gendata-java.base.gmk 2022-01-13 21:56:25.000000000 +0000
@@ -32,7 +32,7 @@
include GendataTZDB.gmk
-include GendataBlacklistedCerts.gmk
+include GendataBlockedCerts.gmk
include GendataCryptoPolicy.gmk
diff -Nru openjdk-lts-11.0.11+9/make/gensrc/GensrcMisc.gmk openjdk-lts-11.0.14+9/make/gensrc/GensrcMisc.gmk
--- openjdk-lts-11.0.11+9/make/gensrc/GensrcMisc.gmk 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/make/gensrc/GensrcMisc.gmk 2022-01-13 21:56:25.000000000 +0000
@@ -63,6 +63,12 @@
CPP_FLAGS += -x c
else ifeq ($(TOOLCHAIN_TYPE), microsoft)
CPP_FLAGS += -nologo
+
+ ifeq ($(OPENJDK_TARGET_CPU),aarch64)
+ # cl.exe does only recognize few file extensions as valid (ex: .c, .h, .cpp), so
+ # make sure *.java.template files are recognized as valid input files
+ CPP_FILEPREFIX = -Tc
+ endif
endif
# Generate a java source file from a template through the C preprocessor for the
@@ -75,7 +81,7 @@
define generate-preproc-src
$(call MakeDir, $(@D))
( $(NAWK) '/@@END_COPYRIGHT@@/{exit}1' $< && \
- $(CPP) $(CPP_FLAGS) $(SYSROOT_CFLAGS) $(CFLAGS_JDKLIB) $< \
+ $(CPP) $(CPP_FLAGS) $(SYSROOT_CFLAGS) $(CFLAGS_JDKLIB) $(CPP_FILEPREFIX) $< \
2> >($(GREP) -v '^$(&2) \
| $(NAWK) '/@@START_HERE@@/,0' \
| $(SED) -e 's/@@START_HERE@@/\/\/ AUTOMATICALLY GENERATED FILE - DO NOT EDIT/' \
diff -Nru openjdk-lts-11.0.11+9/make/hotspot/gensrc/GensrcAdlc.gmk openjdk-lts-11.0.14+9/make/hotspot/gensrc/GensrcAdlc.gmk
--- openjdk-lts-11.0.11+9/make/hotspot/gensrc/GensrcAdlc.gmk 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/make/hotspot/gensrc/GensrcAdlc.gmk 2022-01-13 21:56:25.000000000 +0000
@@ -99,6 +99,13 @@
ADLCFLAGS += -DAIX=1
else ifeq ($(OPENJDK_TARGET_OS), macosx)
ADLCFLAGS += -D_ALLBSD_SOURCE=1 -D_GNU_SOURCE=1
+ else ifeq ($(OPENJDK_TARGET_OS), windows)
+ ifeq ($(call isTargetCpuBits, 64), true)
+ ADLCFLAGS += -D_WIN64=1
+ endif
+ ifeq ($(HOTSPOT_TARGET_CPU_ARCH), aarch64)
+ ADLCFLAGS += -DR18_RESERVED=1
+ endif
endif
ifneq ($(OPENJDK_TARGET_OS), windows)
diff -Nru openjdk-lts-11.0.11+9/make/hotspot/lib/CompileJvm.gmk openjdk-lts-11.0.14+9/make/hotspot/lib/CompileJvm.gmk
--- openjdk-lts-11.0.11+9/make/hotspot/lib/CompileJvm.gmk 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/make/hotspot/lib/CompileJvm.gmk 2022-01-13 21:56:25.000000000 +0000
@@ -57,7 +57,7 @@
JVM_EXCLUDE_FILES += args.cc
JVM_EXCLUDES += adlc
-# Needed by vm_version.cpp
+# Needed by abstract_vm_version.cpp
ifeq ($(OPENJDK_TARGET_CPU), x86_64)
OPENJDK_TARGET_CPU_VM_VERSION := amd64
else ifeq ($(OPENJDK_TARGET_CPU), sparcv9)
@@ -158,7 +158,7 @@
EXCLUDE_PATTERNS := $(JVM_EXCLUDE_PATTERNS), \
EXTRA_OBJECT_FILES := $(DTRACE_EXTRA_OBJECT_FILES), \
CFLAGS := $(JVM_CFLAGS), \
- vm_version.cpp_CXXFLAGS := $(CFLAGS_VM_VERSION), \
+ abstract_vm_version.cpp_CXXFLAGS := $(CFLAGS_VM_VERSION), \
arguments.cpp_CXXFLAGS := $(CFLAGS_VM_VERSION), \
DISABLED_WARNINGS_clang := tautological-compare, \
DISABLED_WARNINGS_solstudio := $(DISABLED_WARNINGS_solstudio), \
@@ -179,11 +179,11 @@
PRECOMPILED_HEADER_EXCLUDE := $(JVM_PRECOMPILED_HEADER_EXCLUDE), \
))
-# Always recompile vm_version.cpp if libjvm needs to be relinked. This ensures
+# Always recompile abstract_vm_version.cpp if libjvm needs to be relinked. This ensures
# that the internal vm version is updated as it relies on __DATE__ and __TIME__
# macros.
-VM_VERSION_OBJ := $(JVM_OUTPUTDIR)/objs/vm_version$(OBJ_SUFFIX)
-$(VM_VERSION_OBJ): $(filter-out $(VM_VERSION_OBJ) $(JVM_MAPFILE), \
+ABSTRACT_VM_VERSION_OBJ := $(JVM_OUTPUTDIR)/objs/abstract_vm_version$(OBJ_SUFFIX)
+$(ABSTRACT_VM_VERSION_OBJ): $(filter-out $(ABSTRACT_VM_VERSION_OBJ) $(JVM_MAPFILE), \
$(BUILD_LIBJVM_TARGET_DEPS))
ifneq ($(GENERATE_COMPILE_COMMANDS_ONLY), true)
diff -Nru openjdk-lts-11.0.11+9/make/jdk/src/classes/build/tools/blacklistedcertsconverter/BlacklistedCertsConverter.java openjdk-lts-11.0.14+9/make/jdk/src/classes/build/tools/blacklistedcertsconverter/BlacklistedCertsConverter.java
--- openjdk-lts-11.0.11+9/make/jdk/src/classes/build/tools/blacklistedcertsconverter/BlacklistedCertsConverter.java 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/make/jdk/src/classes/build/tools/blacklistedcertsconverter/BlacklistedCertsConverter.java 1970-01-01 00:00:00.000000000 +0000
@@ -1,196 +0,0 @@
-/*
- * Copyright (c) 2013, 2020, Oracle and/or its affiliates. All rights reserved.
- * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
- *
- * This code is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 only, as
- * published by the Free Software Foundation. Oracle designates this
- * particular file as subject to the "Classpath" exception as provided
- * by Oracle in the LICENSE file that accompanied this code.
- *
- * This code is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
- * version 2 for more details (a copy is included in the LICENSE file that
- * accompanied this code).
- *
- * You should have received a copy of the GNU General Public License version
- * 2 along with this work; if not, write to the Free Software Foundation,
- * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
- * or visit www.oracle.com if you need additional information or have any
- * questions.
- */
-
-package build.tools.blacklistedcertsconverter;
-
-import java.io.IOException;
-import java.math.BigInteger;
-import java.security.MessageDigest;
-import java.security.PublicKey;
-import java.security.cert.Certificate;
-import java.security.cert.CertificateFactory;
-import java.security.cert.X509Certificate;
-import java.security.interfaces.ECPublicKey;
-import java.util.ArrayList;
-import java.util.Arrays;
-import java.util.Collection;
-import java.util.List;
-import java.util.Set;
-import java.util.TreeSet;
-
-import sun.security.util.DerInputStream;
-import sun.security.util.DerOutputStream;
-import sun.security.util.DerValue;
-
-/**
- * Converts blacklisted.certs.pem from System.in to blacklisted.certs in
- * System.out. The input must start with a #! line including the fingerprint
- * algorithm. The output is sorted and unique.
- */
-public class BlacklistedCertsConverter {
-
- public static void main(String[] args) throws Exception {
-
- byte[] pattern = "#! java BlacklistedCertsConverter ".getBytes();
- String mdAlg = "";
-
- for (int i=0; ; i++) {
- int n = System.in.read();
- if (n < 0) {
- throw new Exception("Unexpected EOF");
- }
- if (i < pattern.length) {
- if (n != pattern[i]) {
- throw new Exception("The first line must start with \""
- + new String(pattern) + "\"");
- }
- } else if (i < pattern.length + 100) {
- if (n < 32) {
- break;
- } else {
- mdAlg = mdAlg + String.format("%c", n);
- }
- }
- }
-
- mdAlg = mdAlg.trim();
- System.out.println("Algorithm=" + mdAlg);
-
- CertificateFactory cf = CertificateFactory.getInstance("X.509");
- Collection extends Certificate> certs
- = cf.generateCertificates(System.in);
-
- // Output sorted so that it's easy to locate an entry.
- Set fingerprints = new TreeSet<>();
- for (Certificate cert: certs) {
- fingerprints.addAll(
- getCertificateFingerPrints(mdAlg, (X509Certificate)cert));
- }
-
- for (String s: fingerprints) {
- System.out.println(s);
- }
- }
-
- /**
- * Converts a byte to hex digit and writes to the supplied buffer
- */
- private static void byte2hex(byte b, StringBuffer buf) {
- char[] hexChars = { '0', '1', '2', '3', '4', '5', '6', '7', '8',
- '9', 'A', 'B', 'C', 'D', 'E', 'F' };
- int high = ((b & 0xf0) >> 4);
- int low = (b & 0x0f);
- buf.append(hexChars[high]);
- buf.append(hexChars[low]);
- }
-
- /**
- * Computes the possible fingerprints of the certificate.
- */
- private static List getCertificateFingerPrints(
- String mdAlg, X509Certificate cert) throws Exception {
- List fingerprints = new ArrayList<>();
- for (byte[] encoding : altEncodings(cert)) {
- MessageDigest md = MessageDigest.getInstance(mdAlg);
- byte[] digest = md.digest(encoding);
- StringBuffer buf = new StringBuffer();
- for (int i = 0; i < digest.length; i++) {
- byte2hex(digest[i], buf);
- }
- fingerprints.add(buf.toString());
- }
- return fingerprints;
- }
-
- private static List altEncodings(X509Certificate c)
- throws Exception {
- List result = new ArrayList<>();
-
- DerValue d = new DerValue(c.getEncoded());
- DerValue[] seq = new DerValue[3];
- // tbsCertificate
- seq[0] = d.data.getDerValue();
- // signatureAlgorithm
- seq[1] = d.data.getDerValue();
- // signature
- seq[2] = d.data.getDerValue();
-
- List algIds = Arrays.asList(seq[1], altAlgId(seq[1]));
-
- List sigs;
- PublicKey p = c.getPublicKey();
- if (p instanceof ECPublicKey) {
- ECPublicKey ep = (ECPublicKey) p;
- BigInteger mod = ep.getParams().getOrder();
- sigs = Arrays.asList(seq[2], altSig(mod, seq[2]));
- } else {
- sigs = Arrays.asList(seq[2]);
- }
-
- for (DerValue algId : algIds) {
- for (DerValue sig : sigs) {
- DerOutputStream tmp = new DerOutputStream();
- tmp.putDerValue(seq[0]);
- tmp.putDerValue(algId);
- tmp.putDerValue(sig);
- DerOutputStream tmp2 = new DerOutputStream();
- tmp2.write(DerValue.tag_Sequence, tmp);
- result.add(tmp2.toByteArray());
- }
- }
- return result;
- }
-
- private static DerValue altSig(BigInteger mod, DerValue sig)
- throws IOException {
- byte[] sigBits = sig.getBitString();
- DerInputStream in =
- new DerInputStream(sigBits, 0, sigBits.length, false);
- DerValue[] values = in.getSequence(2);
- BigInteger r = values[0].getBigInteger();
- BigInteger s = values[1].getBigInteger();
- BigInteger s2 = s.negate().mod(mod);
- DerOutputStream out = new DerOutputStream();
- out.putInteger(r);
- out.putInteger(s2);
- DerOutputStream tmp = new DerOutputStream();
- tmp.putBitString(new DerValue(DerValue.tag_Sequence,
- out.toByteArray()).toByteArray());
- return new DerValue(tmp.toByteArray());
- }
-
- private static DerValue altAlgId(DerValue algId) throws IOException {
- DerInputStream in = algId.toDerInputStream();
- DerOutputStream bytes = new DerOutputStream();
- bytes.putOID(in.getOID());
- // encode parameters as NULL if not present or omit if NULL
- if (in.available() == 0) {
- bytes.putNull();
- }
- DerOutputStream tmp = new DerOutputStream();
- tmp.write(DerValue.tag_Sequence, bytes);
- return new DerValue(tmp.toByteArray());
- }
-}
diff -Nru openjdk-lts-11.0.11+9/make/jdk/src/classes/build/tools/blockedcertsconverter/BlockedCertsConverter.java openjdk-lts-11.0.14+9/make/jdk/src/classes/build/tools/blockedcertsconverter/BlockedCertsConverter.java
--- openjdk-lts-11.0.11+9/make/jdk/src/classes/build/tools/blockedcertsconverter/BlockedCertsConverter.java 1970-01-01 00:00:00.000000000 +0000
+++ openjdk-lts-11.0.14+9/make/jdk/src/classes/build/tools/blockedcertsconverter/BlockedCertsConverter.java 2022-01-13 21:56:25.000000000 +0000
@@ -0,0 +1,196 @@
+/*
+ * Copyright (c) 2013, 2021, Oracle and/or its affiliates. All rights reserved.
+ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+ *
+ * This code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 only, as
+ * published by the Free Software Foundation. Oracle designates this
+ * particular file as subject to the "Classpath" exception as provided
+ * by Oracle in the LICENSE file that accompanied this code.
+ *
+ * This code is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * version 2 for more details (a copy is included in the LICENSE file that
+ * accompanied this code).
+ *
+ * You should have received a copy of the GNU General Public License version
+ * 2 along with this work; if not, write to the Free Software Foundation,
+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
+ * or visit www.oracle.com if you need additional information or have any
+ * questions.
+ */
+
+package build.tools.blockedcertsconverter;
+
+import java.io.IOException;
+import java.math.BigInteger;
+import java.security.MessageDigest;
+import java.security.PublicKey;
+import java.security.cert.Certificate;
+import java.security.cert.CertificateFactory;
+import java.security.cert.X509Certificate;
+import java.security.interfaces.ECPublicKey;
+import java.util.ArrayList;
+import java.util.Arrays;
+import java.util.Collection;
+import java.util.List;
+import java.util.Set;
+import java.util.TreeSet;
+
+import sun.security.util.DerInputStream;
+import sun.security.util.DerOutputStream;
+import sun.security.util.DerValue;
+
+/**
+ * Converts blocked.certs.pem from System.in to blocked.certs in
+ * System.out. The input must start with a #! line including the fingerprint
+ * algorithm. The output is sorted and unique.
+ */
+public class BlockedCertsConverter {
+
+ public static void main(String[] args) throws Exception {
+
+ byte[] pattern = "#! java BlockedCertsConverter ".getBytes();
+ String mdAlg = "";
+
+ for (int i=0; ; i++) {
+ int n = System.in.read();
+ if (n < 0) {
+ throw new Exception("Unexpected EOF");
+ }
+ if (i < pattern.length) {
+ if (n != pattern[i]) {
+ throw new Exception("The first line must start with \""
+ + new String(pattern) + "\"");
+ }
+ } else if (i < pattern.length + 100) {
+ if (n < 32) {
+ break;
+ } else {
+ mdAlg = mdAlg + String.format("%c", n);
+ }
+ }
+ }
+
+ mdAlg = mdAlg.trim();
+ System.out.println("Algorithm=" + mdAlg);
+
+ CertificateFactory cf = CertificateFactory.getInstance("X.509");
+ Collection extends Certificate> certs
+ = cf.generateCertificates(System.in);
+
+ // Output sorted so that it's easy to locate an entry.
+ Set fingerprints = new TreeSet<>();
+ for (Certificate cert: certs) {
+ fingerprints.addAll(
+ getCertificateFingerPrints(mdAlg, (X509Certificate)cert));
+ }
+
+ for (String s: fingerprints) {
+ System.out.println(s);
+ }
+ }
+
+ /**
+ * Converts a byte to hex digit and writes to the supplied buffer
+ */
+ private static void byte2hex(byte b, StringBuffer buf) {
+ char[] hexChars = { '0', '1', '2', '3', '4', '5', '6', '7', '8',
+ '9', 'A', 'B', 'C', 'D', 'E', 'F' };
+ int high = ((b & 0xf0) >> 4);
+ int low = (b & 0x0f);
+ buf.append(hexChars[high]);
+ buf.append(hexChars[low]);
+ }
+
+ /**
+ * Computes the possible fingerprints of the certificate.
+ */
+ private static List getCertificateFingerPrints(
+ String mdAlg, X509Certificate cert) throws Exception {
+ List fingerprints = new ArrayList<>();
+ for (byte[] encoding : altEncodings(cert)) {
+ MessageDigest md = MessageDigest.getInstance(mdAlg);
+ byte[] digest = md.digest(encoding);
+ StringBuffer buf = new StringBuffer();
+ for (int i = 0; i < digest.length; i++) {
+ byte2hex(digest[i], buf);
+ }
+ fingerprints.add(buf.toString());
+ }
+ return fingerprints;
+ }
+
+ private static List altEncodings(X509Certificate c)
+ throws Exception {
+ List result = new ArrayList<>();
+
+ DerValue d = new DerValue(c.getEncoded());
+ DerValue[] seq = new DerValue[3];
+ // tbsCertificate
+ seq[0] = d.data.getDerValue();
+ // signatureAlgorithm
+ seq[1] = d.data.getDerValue();
+ // signature
+ seq[2] = d.data.getDerValue();
+
+ List algIds = Arrays.asList(seq[1], altAlgId(seq[1]));
+
+ List sigs;
+ PublicKey p = c.getPublicKey();
+ if (p instanceof ECPublicKey) {
+ ECPublicKey ep = (ECPublicKey) p;
+ BigInteger mod = ep.getParams().getOrder();
+ sigs = Arrays.asList(seq[2], altSig(mod, seq[2]));
+ } else {
+ sigs = Arrays.asList(seq[2]);
+ }
+
+ for (DerValue algId : algIds) {
+ for (DerValue sig : sigs) {
+ DerOutputStream tmp = new DerOutputStream();
+ tmp.putDerValue(seq[0]);
+ tmp.putDerValue(algId);
+ tmp.putDerValue(sig);
+ DerOutputStream tmp2 = new DerOutputStream();
+ tmp2.write(DerValue.tag_Sequence, tmp);
+ result.add(tmp2.toByteArray());
+ }
+ }
+ return result;
+ }
+
+ private static DerValue altSig(BigInteger mod, DerValue sig)
+ throws IOException {
+ byte[] sigBits = sig.getBitString();
+ DerInputStream in =
+ new DerInputStream(sigBits, 0, sigBits.length, false);
+ DerValue[] values = in.getSequence(2);
+ BigInteger r = values[0].getBigInteger();
+ BigInteger s = values[1].getBigInteger();
+ BigInteger s2 = s.negate().mod(mod);
+ DerOutputStream out = new DerOutputStream();
+ out.putInteger(r);
+ out.putInteger(s2);
+ DerOutputStream tmp = new DerOutputStream();
+ tmp.putBitString(new DerValue(DerValue.tag_Sequence,
+ out.toByteArray()).toByteArray());
+ return new DerValue(tmp.toByteArray());
+ }
+
+ private static DerValue altAlgId(DerValue algId) throws IOException {
+ DerInputStream in = algId.toDerInputStream();
+ DerOutputStream bytes = new DerOutputStream();
+ bytes.putOID(in.getOID());
+ // encode parameters as NULL if not present or omit if NULL
+ if (in.available() == 0) {
+ bytes.putNull();
+ }
+ DerOutputStream tmp = new DerOutputStream();
+ tmp.write(DerValue.tag_Sequence, bytes);
+ return new DerValue(tmp.toByteArray());
+ }
+}
diff -Nru openjdk-lts-11.0.11+9/make/jdk/src/classes/build/tools/charsetmapping/SBCS.java openjdk-lts-11.0.14+9/make/jdk/src/classes/build/tools/charsetmapping/SBCS.java
--- openjdk-lts-11.0.11+9/make/jdk/src/classes/build/tools/charsetmapping/SBCS.java 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/make/jdk/src/classes/build/tools/charsetmapping/SBCS.java 2022-01-13 21:56:25.000000000 +0000
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2008, 2015, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2008, 2019, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@@ -46,6 +46,7 @@
String hisName = cs.hisName;
String pkgName = cs.pkgName;
boolean isASCII = cs.isASCII;
+ boolean isLatin1Decodable = true;
StringBuilder b2cSB = new StringBuilder();
StringBuilder b2cNRSB = new StringBuilder();
@@ -69,6 +70,9 @@
c2bOff += 0x100;
c2bIndex[e.cp>>8] = 1;
}
+ if (e.cp > 0xFF) {
+ isLatin1Decodable = false;
+ }
}
Formatter fm = new Formatter(b2cSB);
@@ -178,6 +182,9 @@
if (line.indexOf("$ASCIICOMPATIBLE$") != -1) {
line = line.replace("$ASCIICOMPATIBLE$", isASCII ? "true" : "false");
}
+ if (line.indexOf("$LATIN1DECODABLE$") != -1) {
+ line = line.replace("$LATIN1DECODABLE$", isLatin1Decodable ? "true" : "false");
+ }
if (line.indexOf("$B2CTABLE$") != -1) {
line = line.replace("$B2CTABLE$", b2c);
}
diff -Nru openjdk-lts-11.0.11+9/make/jdk/src/classes/build/tools/depend/Depend.java openjdk-lts-11.0.14+9/make/jdk/src/classes/build/tools/depend/Depend.java
--- openjdk-lts-11.0.11+9/make/jdk/src/classes/build/tools/depend/Depend.java 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/make/jdk/src/classes/build/tools/depend/Depend.java 2022-01-13 21:56:25.000000000 +0000
@@ -101,7 +101,7 @@
private final MessageDigest apiHash;
{
try {
- apiHash = MessageDigest.getInstance("MD5");
+ apiHash = MessageDigest.getInstance("SHA-256");
} catch (NoSuchAlgorithmException ex) {
throw new IllegalStateException(ex);
}
diff -Nru openjdk-lts-11.0.11+9/make/jdk/src/classes/build/tools/generatelsrequivmaps/EquivMapsGenerator.java openjdk-lts-11.0.14+9/make/jdk/src/classes/build/tools/generatelsrequivmaps/EquivMapsGenerator.java
--- openjdk-lts-11.0.11+9/make/jdk/src/classes/build/tools/generatelsrequivmaps/EquivMapsGenerator.java 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/make/jdk/src/classes/build/tools/generatelsrequivmaps/EquivMapsGenerator.java 2022-01-13 21:56:25.000000000 +0000
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2012, 2017, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2012, 2020, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@@ -33,10 +33,12 @@
import java.time.ZoneId;
import java.time.ZonedDateTime;
import java.util.ArrayList;
+import java.util.Arrays;
import java.util.List;
import java.util.Locale;
import java.util.Map;
import java.util.TreeMap;
+import java.util.stream.Collectors;
/**
* This tool reads the IANA Language Subtag Registry data file downloaded from
@@ -75,32 +77,49 @@
String type = null;
String tag = null;
String preferred = null;
+ String prefix = null;
for (String line : Files.readAllLines(Paths.get(filename),
Charset.forName("UTF-8"))) {
line = line.toLowerCase(Locale.ROOT);
- int index = line.indexOf(' ')+1;
+ int index = line.indexOf(' ') + 1;
if (line.startsWith("file-date:")) {
LSRrevisionDate = line.substring(index);
} else if (line.startsWith("type:")) {
type = line.substring(index);
} else if (line.startsWith("tag:") || line.startsWith("subtag:")) {
tag = line.substring(index);
- } else if (line.startsWith("preferred-value:")
- && !type.equals("extlang")) {
+ } else if (line.startsWith("preferred-value:")) {
preferred = line.substring(index);
- processDeprecatedData(type, tag, preferred);
+ } else if (line.startsWith("prefix:")) {
+ prefix = line.substring(index);
} else if (line.equals("%%")) {
+ processDeprecatedData(type, tag, preferred, prefix);
type = null;
tag = null;
+ preferred = null;
+ prefix = null;
}
}
+
+ // Last entry
+ processDeprecatedData(type, tag, preferred, prefix);
}
private static void processDeprecatedData(String type,
String tag,
- String preferred) {
+ String preferred,
+ String prefix) {
StringBuilder sb;
+
+ if (type == null || tag == null || preferred == null) {
+ return;
+ }
+
+ if (type.equals("extlang") && prefix != null) {
+ tag = prefix + "-" + tag;
+ }
+
if (type.equals("region") || type.equals("variant")) {
if (!initialRegionVariantMap.containsKey(preferred)) {
sb = new StringBuilder("-");
@@ -113,7 +132,7 @@
+ " A region/variant subtag \"" + preferred
+ "\" is registered for more than one subtags.");
}
- } else { // language, grandfahered, and redundant
+ } else { // language, extlang, legacy, and redundant
if (!initialLanguageMap.containsKey(preferred)) {
sb = new StringBuilder(preferred);
sb.append(',');
@@ -131,7 +150,12 @@
private static void generateEquivalentMap() {
String[] subtags;
for (String preferred : initialLanguageMap.keySet()) {
- subtags = initialLanguageMap.get(preferred).toString().split(",");
+ // There are cases where the same tag may appear in two entries, e.g.,
+ // "yue" is defined both as extlang and redundant. Remove the dup.
+ subtags = Arrays.stream(initialLanguageMap.get(preferred).toString().split(","))
+ .distinct()
+ .collect(Collectors.toList())
+ .toArray(new String[0]);
if (subtags.length == 2) {
sortedLanguageMap1.put(subtags[0], subtags[1]);
@@ -215,10 +239,7 @@
+ " static final Map multiEquivsMap;\n"
+ " static final Map regionVariantEquivMap;\n\n"
+ " static {\n"
- + " singleEquivMap = new HashMap<>();\n"
- + " multiEquivsMap = new HashMap<>();\n"
- + " regionVariantEquivMap = new HashMap<>();\n\n"
- + " // This is an auto-generated file and should not be manually edited.\n";
+ + " singleEquivMap = new HashMap<>(";
private static final String footerText =
" }\n\n"
@@ -242,6 +263,12 @@
Paths.get(fileName))) {
writer.write(getOpenJDKCopyright());
writer.write(headerText
+ + (int)(sortedLanguageMap1.size() / 0.75f + 1) + ");\n"
+ + " multiEquivsMap = new HashMap<>("
+ + (int)(sortedLanguageMap2.size() / 0.75f + 1) + ");\n"
+ + " regionVariantEquivMap = new HashMap<>("
+ + (int)(sortedRegionVariantMap.size() / 0.75f + 1) + ");\n\n"
+ + " // This is an auto-generated file and should not be manually edited.\n"
+ " // LSR Revision: " + LSRrevisionDate);
writer.newLine();
diff -Nru openjdk-lts-11.0.11+9/make/lib/Awt2dLibraries.gmk openjdk-lts-11.0.14+9/make/lib/Awt2dLibraries.gmk
--- openjdk-lts-11.0.11+9/make/lib/Awt2dLibraries.gmk 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/make/lib/Awt2dLibraries.gmk 2022-01-13 21:56:25.000000000 +0000
@@ -244,7 +244,6 @@
LIBS_macosx := -lmlib_image \
-framework Cocoa \
-framework OpenGL \
- -framework JavaNativeFoundation \
-framework JavaRuntimeSupport \
-framework ApplicationServices \
-framework AudioToolbox, \
@@ -390,7 +389,7 @@
common/awt/debug \
libawt/java2d, \
HEADERS_FROM_SRC := $(LIBLCMS_HEADERS_FROM_SRC), \
- DISABLED_WARNINGS_gcc := format-nonliteral type-limits misleading-indentation, \
+ DISABLED_WARNINGS_gcc := format-nonliteral type-limits misleading-indentation stringop-truncation, \
DISABLED_WARNINGS_clang := tautological-compare, \
DISABLED_WARNINGS_solstudio := E_STATEMENT_NOT_REACHED, \
DISABLED_WARNINGS_microsoft := 4819, \
@@ -536,26 +535,13 @@
###########################################################################
+
ifeq ($(USE_EXTERNAL_HARFBUZZ), true)
- LIBHARFBUZZ_LIBS := $(HARFBUZZ_LIBS)
+ LIBFONTMANAGER_EXTRA_SRC =
+ BUILD_LIBFONTMANAGER_FONTLIB += $(HARFBUZZ_LIBS)
else
+ LIBFONTMANAGER_EXTRA_SRC = libharfbuzz
HARFBUZZ_CFLAGS := -DHAVE_OT -DHAVE_FALLBACK -DHAVE_UCDN -DHAVE_ROUND
- # This is better than adding EXPORT_ALL_SYMBOLS
- ifneq ($(filter $(TOOLCHAIN_TYPE), gcc clang solstudio), )
- HARFBUZZ_CFLAGS += -DHB_EXTERN=__attribute__\(\(visibility\(\"default\"\)\)\)
- else ifeq ($(TOOLCHAIN_TYPE), microsoft)
- HARFBUZZ_CFLAGS += -DHB_EXTERN=__declspec\(dllexport\)
- endif
-
- LIBHARFBUZZ_LDFLAGS := $(LDFLAGS_JDKLIB) \
- $(call SET_SHARED_LIBRARY_ORIGIN)
- ifeq ($(TOOLCHAIN_TYPE), gcc)
- ifeq ($(CC_VERSION_NUMBER), 4.4.7)
- LIBHARFBUZZ_LDFLAGS := $(subst -Xlinker -z -Xlinker defs,, \
- $(subst -Wl$(COMMA)-z$(COMMA)defs,,$(LDFLAGS_JDKLIB))) \
- $(call SET_SHARED_LIBRARY_ORIGIN)
- endif
- endif
ifneq ($(OPENJDK_TARGET_OS), windows)
HARFBUZZ_CFLAGS += -DGETPAGESIZE -DHAVE_MPROTECT -DHAVE_PTHREAD \
@@ -568,77 +554,32 @@
ifeq ($(OPENJDK_TARGET_OS), solaris)
HARFBUZZ_CFLAGS += -DHAVE_SOLARIS_ATOMIC_OPS
endif
- ifeq ($(OPENJDK_TARGET_OS), macosx)
- HARFBUZZ_CFLAGS += -DHAVE_CORETEXT
- endif
- ifneq ($(OPENJDK_TARGET_OS), macosx)
- LIBHARFBUZZ_EXCLUDE_FILES += harfbuzz/hb-coretext.cc
- endif
# hb-ft.cc is not presently needed, and requires freetype 2.4.2 or later.
- LIBHARFBUZZ_EXCLUDE_FILES += harfbuzz/hb-ft.cc
-
- LIBHARFBUZZ_CFLAGS += $(HARFBUZZ_CFLAGS)
-
- # For use by libfontmanager:
- ifeq ($(OPENJDK_TARGET_OS), windows)
- LIBHARFBUZZ_LIBS := $(SUPPORT_OUTPUTDIR)/native/$(MODULE)/libharfbuzz/harfbuzz.lib
- else
- LIBHARFBUZZ_LIBS := -lharfbuzz
- endif
-
- LIBHARFBUZZ_EXTRA_HEADER_DIRS := \
- libharfbuzz/hb-ucdn \
- #
+ LIBFONTMANAGER_EXCLUDE_FILES += libharfbuzz/hb-ft.cc
- LIBHARFBUZZ_OPTIMIZATION := HIGH
-
- LIBHARFBUZZ_CFLAGS += $(X_CFLAGS) -DLE_STANDALONE -DHEADLESS
-
- $(eval $(call SetupJdkLibrary, BUILD_LIBHARFBUZZ, \
- NAME := harfbuzz, \
- EXCLUDE_FILES := $(LIBHARFBUZZ_EXCLUDE_FILES), \
- TOOLCHAIN := TOOLCHAIN_LINK_CXX, \
- CFLAGS := $(CFLAGS_JDKLIB) $(LIBHARFBUZZ_CFLAGS), \
- CXXFLAGS := $(CXXFLAGS_JDKLIB) $(LIBHARFBUZZ_CFLAGS), \
- OPTIMIZATION := $(LIBHARFBUZZ_OPTIMIZATION), \
- CFLAGS_windows = -DCC_NOEX, \
- EXTRA_HEADER_DIRS := $(LIBHARFBUZZ_EXTRA_HEADER_DIRS), \
- WARNINGS_AS_ERRORS_xlc := false, \
- DISABLED_WARNINGS_gcc := type-limits missing-field-initializers strict-aliasing, \
- DISABLED_WARNINGS_CXX_gcc := reorder delete-non-virtual-dtor strict-overflow \
- maybe-uninitialized class-memaccess, \
- DISABLED_WARNINGS_clang := unused-value incompatible-pointer-types \
- tautological-constant-out-of-range-compare int-to-pointer-cast \
- undef missing-field-initializers, \
- DISABLED_WARNINGS_C_solstudio := \
- E_INTEGER_OVERFLOW_DETECTED \
- E_ARG_INCOMPATIBLE_WITH_ARG_L \
- E_ENUM_VAL_OVERFLOWS_INT_MAX, \
- DISABLED_WARNINGS_CXX_solstudio := \
- truncwarn wvarhidenmem wvarhidemem wbadlkginit identexpected \
- hidevf w_novirtualdescr arrowrtn2 unknownpragma, \
- DISABLED_WARNINGS_microsoft := 4267 4244 4090 4146 4334 4819 4101 4068 4805 4138, \
- LDFLAGS := $(LIBHARFBUZZ_LDFLAGS), \
- LDFLAGS_unix := -L$(INSTALL_LIBRARIES_HERE), \
- LDFLAGS_aix := -Wl$(COMMA)-berok, \
- LIBS := $(BUILD_LIBHARFBUZZ), \
- LIBS_unix := $(LIBM) $(LIBCXX), \
- LIBS_macosx := -framework CoreText -framework CoreFoundation -framework CoreGraphics, \
- LIBS_windows := user32.lib, \
- ))
-
- ifeq ($(FREETYPE_TO_USE), bundled)
- $(BUILD_LIBHARFBUZZ): $(BUILD_LIBFREETYPE)
- endif
+ HARFBUZZ_DISABLED_WARNINGS_gcc := type-limits missing-field-initializers strict-aliasing
+ HARFBUZZ_DISABLED_WARNINGS_CXX_gcc := reorder delete-non-virtual-dtor strict-overflow \
+ maybe-uninitialized class-memaccess
+ HARFBUZZ_DISABLED_WARNINGS_clang := unused-value incompatible-pointer-types \
+ tautological-constant-out-of-range-compare int-to-pointer-cast \
+ undef missing-field-initializers
+ HARFBUZZ_DISABLED_WARNINGS_microsoft := 4267 4244 4090 4146 4334 4819 4101 4068 4805 4138
+ HARFBUZZ_DISABLED_WARNINGS_C_solstudio := \
+ E_INTEGER_OVERFLOW_DETECTED \
+ E_ARG_INCOMPATIBLE_WITH_ARG_L \
+ E_ENUM_VAL_OVERFLOWS_INT_MAX
+ HARFBUZZ_DISABLED_WARNINGS_CXX_solstudio := \
+ truncwarn wvarhidenmem wvarhidemem wbadlkginit identexpected \
+ hidevf w_novirtualdescr arrowrtn2 unknownpragma
- TARGETS += $(BUILD_LIBHARFBUZZ)
+ LIBFONTMANAGER_CFLAGS += $(HARFBUZZ_CFLAGS)
endif
-###########################################################################
LIBFONTMANAGER_EXTRA_HEADER_DIRS := \
libharfbuzz \
+ libharfbuzz/hb-ucdn \
common/awt \
common/font \
libawt/java2d \
@@ -646,10 +587,10 @@
libawt/java2d/loops \
#
-LIBFONTMANAGER_CFLAGS += $(LIBFREETYPE_CFLAGS) $(HARFBUZZ_FLAGS)
-BUILD_LIBFONTMANAGER_FONTLIB += $(LIBHARFBUZZ_LIBS) $(LIBFREETYPE_LIBS)
+LIBFONTMANAGER_CFLAGS += $(LIBFREETYPE_CFLAGS)
+BUILD_LIBFONTMANAGER_FONTLIB += $(LIBFREETYPE_LIBS)
-LIBFONTMANAGER_OPTIMIZATION := HIGH
+LIBFONTMANAGER_OPTIMIZATION := HIGHEST
ifeq ($(OPENJDK_TARGET_OS), windows)
LIBFONTMANAGER_EXCLUDE_FILES += X11FontScaler.c \
@@ -687,17 +628,14 @@
OPTIMIZATION := $(LIBFONTMANAGER_OPTIMIZATION), \
CFLAGS_windows = -DCC_NOEX, \
EXTRA_HEADER_DIRS := $(LIBFONTMANAGER_EXTRA_HEADER_DIRS), \
+ EXTRA_SRC := $(LIBFONTMANAGER_EXTRA_SRC), \
WARNINGS_AS_ERRORS_xlc := false, \
- DISABLED_WARNINGS_gcc := sign-compare unused-function int-to-pointer-cast, \
- DISABLED_WARNINGS_clang := sign-compare, \
- DISABLED_WARNINGS_C_solstudio := \
- E_INTEGER_OVERFLOW_DETECTED \
- E_ARG_INCOMPATIBLE_WITH_ARG_L \
- E_ENUM_VAL_OVERFLOWS_INT_MAX, \
- DISABLED_WARNINGS_CXX_solstudio := \
- truncwarn wvarhidenmem wvarhidemem wbadlkginit identexpected \
- hidevf w_novirtualdescr arrowrtn2 unknownpragma, \
- DISABLED_WARNINGS_microsoft := 4018 4146 4244 4996 4996 4146 4334 4819 4101 4068 4805 4138, \
+ DISABLED_WARNINGS_gcc := sign-compare unused-function int-to-pointer-cast $(HARFBUZZ_DISABLED_WARNINGS_gcc), \
+ DISABLED_WARNINGS_CXX_gcc := $(HARFBUZZ_DISABLED_WARNINGS_CXX_gcc), \
+ DISABLED_WARNINGS_clang := sign-compare $(HARFBUZZ_DISABLED_WARNINGS_clang), \
+ DISABLED_WARNINGS_C_solstudio := $(HARFBUZZ_DISABLED_WARNINGS_C_solstudio), \
+ DISABLED_WARNINGS_CXX_solstudio := $(HARFBUZZ_DISABLED_WARNINGS_CXX_solstudio), \
+ DISABLED_WARNINGS_microsoft := 4018 4996 $(HARFBUZZ_DISABLED_WARNINGS_microsoft), \
LDFLAGS := $(subst -Xlinker -z -Xlinker defs,, \
$(subst -Wl$(COMMA)-z$(COMMA)defs,,$(LDFLAGS_JDKLIB))) $(LDFLAGS_CXX_JDK) \
$(call SET_SHARED_LIBRARY_ORIGIN), \
@@ -705,17 +643,13 @@
LDFLAGS_aix := -Wl$(COMMA)-berok, \
LIBS := $(BUILD_LIBFONTMANAGER_FONTLIB), \
LIBS_unix := -lawt -ljava -ljvm $(LIBM) $(LIBCXX), \
- LIBS_macosx := -lawt_lwawt, \
+ LIBS_macosx := -lawt_lwawt -framework CoreText -framework CoreFoundation -framework CoreGraphics, \
LIBS_windows := $(WIN_JAVA_LIB) advapi32.lib user32.lib gdi32.lib \
$(WIN_AWT_LIB), \
))
$(BUILD_LIBFONTMANAGER): $(BUILD_LIBAWT)
-ifeq ($(USE_EXTERNAL_HARFBUZZ), false)
- $(BUILD_LIBFONTMANAGER): $(BUILD_LIBHARFBUZZ)
-endif
-
ifeq ($(OPENJDK_TARGET_OS), macosx)
$(BUILD_LIBFONTMANAGER): $(call FindLib, $(MODULE), awt_lwawt)
endif
@@ -902,8 +836,7 @@
$(LIBM) -lpthread -liconv -losxapp \
-framework ApplicationServices \
-framework Foundation \
- -framework Cocoa \
- -framework JavaNativeFoundation
+ -framework Cocoa
else ifeq ($(OPENJDK_TARGET_OS), windows)
LIBSPLASHSCREEN_LIBS += kernel32.lib user32.lib gdi32.lib delayimp.lib $(WIN_JAVA_LIB) jvm.lib
else
@@ -999,7 +932,6 @@
-framework Cocoa \
-framework Security \
-framework ExceptionHandling \
- -framework JavaNativeFoundation \
-framework JavaRuntimeSupport \
-framework OpenGL \
-framework QuartzCore -ljava, \
@@ -1037,7 +969,6 @@
-framework Cocoa \
-framework Carbon \
-framework ApplicationServices \
- -framework JavaNativeFoundation \
-framework JavaRuntimeSupport \
-ljava -ljvm, \
))
diff -Nru openjdk-lts-11.0.11+9/make/lib/Lib-java.base.gmk openjdk-lts-11.0.14+9/make/lib/Lib-java.base.gmk
--- openjdk-lts-11.0.11+9/make/lib/Lib-java.base.gmk 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/make/lib/Lib-java.base.gmk 2022-01-13 21:56:25.000000000 +0000
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2011, 2019, Oracle and/or its affiliates. All rights reserved.
+# Copyright (c) 2011, 2021, Oracle and/or its affiliates. All rights reserved.
# DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
#
# This code is free software; you can redistribute it and/or modify it
@@ -110,9 +110,9 @@
$(call SET_SHARED_LIBRARY_ORIGIN), \
LIBS := \
-lobjc \
- -framework JavaNativeFoundation \
-framework CoreServices \
-framework Security \
+ -framework Foundation \
$(JDKLIB_LIBS), \
))
diff -Nru openjdk-lts-11.0.11+9/make/lib/Lib-java.desktop.gmk openjdk-lts-11.0.14+9/make/lib/Lib-java.desktop.gmk
--- openjdk-lts-11.0.11+9/make/lib/Lib-java.desktop.gmk 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/make/lib/Lib-java.desktop.gmk 2022-01-13 21:56:25.000000000 +0000
@@ -96,6 +96,7 @@
LDFLAGS := $(LDFLAGS_JDKLIB) \
$(call SET_SHARED_LIBRARY_ORIGIN), \
LIBS := \
+ -ljava \
-framework Accelerate \
-framework ApplicationServices \
-framework AudioToolbox \
@@ -103,13 +104,14 @@
-framework Cocoa \
-framework Security \
-framework ExceptionHandling \
- -framework JavaNativeFoundation \
-framework JavaRuntimeSupport \
-framework OpenGL \
-framework IOSurface \
-framework QuartzCore, \
))
+ $(BUILD_LIBOSXAPP): $(call FindLib, java.base, java)
+
TARGETS += $(BUILD_LIBOSXAPP)
##############################################################################
@@ -127,7 +129,6 @@
-losxapp \
-framework Cocoa \
-framework ApplicationServices \
- -framework JavaNativeFoundation \
-framework JavaRuntimeSupport \
-framework SystemConfiguration \
$(JDKLIB_LIBS), \
diff -Nru openjdk-lts-11.0.11+9/make/lib/Lib-java.security.jgss.gmk openjdk-lts-11.0.14+9/make/lib/Lib-java.security.jgss.gmk
--- openjdk-lts-11.0.11+9/make/lib/Lib-java.security.jgss.gmk 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/make/lib/Lib-java.security.jgss.gmk 2022-01-13 21:56:25.000000000 +0000
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2011, 2019, Oracle and/or its affiliates. All rights reserved.
+# Copyright (c) 2011, 2021, Oracle and/or its affiliates. All rights reserved.
# DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
#
# This code is free software; you can redistribute it and/or modify it
@@ -78,8 +78,8 @@
DISABLED_WARNINGS_clang := deprecated-declarations, \
LDFLAGS := $(LDFLAGS_JDKLIB) \
$(call SET_SHARED_LIBRARY_ORIGIN), \
- LIBS := -framework JavaNativeFoundation -framework Cocoa \
- -framework SystemConfiguration -framework Kerberos, \
+ LIBS := -framework Cocoa -framework SystemConfiguration \
+ -framework Kerberos, \
))
TARGETS += $(BUILD_LIBOSXKRB5)
diff -Nru openjdk-lts-11.0.11+9/make/lib/Lib-jdk.hotspot.agent.gmk openjdk-lts-11.0.14+9/make/lib/Lib-jdk.hotspot.agent.gmk
--- openjdk-lts-11.0.11+9/make/lib/Lib-jdk.hotspot.agent.gmk 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/make/lib/Lib-jdk.hotspot.agent.gmk 2022-01-13 21:56:25.000000000 +0000
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2015, 2018, Oracle and/or its affiliates. All rights reserved.
+# Copyright (c) 2015, 2019, Oracle and/or its affiliates. All rights reserved.
# DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
#
# This code is free software; you can redistribute it and/or modify it
@@ -65,9 +65,9 @@
CXXFLAGS := $(CXXFLAGS_JDKLIB) $(SA_CFLAGS) $(SA_CXXFLAGS), \
EXTRA_SRC := $(LIBSA_EXTRA_SRC), \
LDFLAGS := $(LDFLAGS_JDKLIB) $(SA_LDFLAGS), \
- LIBS_linux := -lthread_db $(LIBDL), \
+ LIBS_linux := $(LIBDL), \
LIBS_solaris := -ldl -ldemangle -lthread -lproc, \
- LIBS_macosx := -framework Foundation -framework JavaNativeFoundation \
+ LIBS_macosx := -framework Foundation \
-framework JavaRuntimeSupport -framework Security -framework CoreFoundation, \
LIBS_windows := dbgeng.lib, \
))
diff -Nru openjdk-lts-11.0.11+9/make/RunTests.gmk openjdk-lts-11.0.14+9/make/RunTests.gmk
--- openjdk-lts-11.0.11+9/make/RunTests.gmk 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/make/RunTests.gmk 2022-01-13 21:56:25.000000000 +0000
@@ -276,7 +276,7 @@
$(eval $(call ParseKeywordVariable, JTREG, \
SINGLE_KEYWORDS := JOBS TIMEOUT_FACTOR TEST_MODE ASSERT VERBOSE RETAIN \
- MAX_MEM, \
+ MAX_MEM RETRY_COUNT, \
STRING_KEYWORDS := OPTIONS JAVA_OPTIONS VM_OPTIONS KEYWORDS \
EXTRA_PROBLEM_LISTS AOT_MODULES, \
))
@@ -312,8 +312,6 @@
nashorn_JTREG_PROBLEM_LIST += $(TOPDIR)/test/nashorn/ProblemList.txt
hotspot_JTREG_PROBLEM_LIST += $(TOPDIR)/test/hotspot/jtreg/ProblemList.txt
-langtools_JTREG_MAX_MEM := 768m
-
################################################################################
# Parse test selection
#
@@ -532,6 +530,7 @@
$$(FIXPATH) $$(TEST_IMAGE_DIR)/hotspot/gtest/$$($1_VARIANT)/gtestLauncher \
-jdk $(JDK_IMAGE_DIR) $$($1_GTEST_FILTER) \
--gtest_output=xml:$$($1_TEST_RESULTS_DIR)/gtest.xml \
+ --gtest_catch_exceptions=0 \
$$($1_GTEST_REPEAT) $$(GTEST_OPTIONS) $$(GTEST_VM_OPTIONS) \
$$(GTEST_JAVA_OPTIONS) $$($1_AOT_OPTIONS) \
> >($(TEE) $$($1_TEST_RESULTS_DIR)/gtest.txt) \
@@ -626,7 +625,7 @@
# Convert JTREG_foo into $1_JTREG_foo with a suitable value.
$$(eval $$(call SetJtregValue,$1,JTREG_TEST_MODE,agentvm))
$$(eval $$(call SetJtregValue,$1,JTREG_ASSERT,true))
- $$(eval $$(call SetJtregValue,$1,JTREG_MAX_MEM,512m))
+ $$(eval $$(call SetJtregValue,$1,JTREG_MAX_MEM,768m))
$$(eval $$(call SetJtregValue,$1,JTREG_NATIVEPATH))
$$(eval $$(call SetJtregValue,$1,JTREG_BASIC_OPTIONS))
$$(eval $$(call SetJtregValue,$1,JTREG_PROBLEM_LIST))
@@ -642,7 +641,7 @@
# Make sure MaxRAMPercentage is high enough to not cause OOM or swapping since
# we may end up with a lot of JVM's
- $1_JTREG_MAX_RAM_PERCENTAGE := $$(shell $$(EXPR) 25 / $$($1_JTREG_JOBS))
+ $1_JTREG_MAX_RAM_PERCENTAGE := $$(shell $(AWK) 'BEGIN { print 25 / $$($1_JTREG_JOBS); }')
# SPARC is in general slower per core so need to scale up timeouts a bit.
ifeq ($(OPENJDK_TARGET_CPU_ARCH), sparc)
@@ -652,6 +651,7 @@
endif
JTREG_VERBOSE ?= fail,error,summary
JTREG_RETAIN ?= fail,error
+ JTREG_RETRY_COUNT ?= 0
ifneq ($$($1_JTREG_MAX_MEM), 0)
$1_JTREG_BASIC_OPTIONS += -vmoption:-Xmx$$($1_JTREG_MAX_MEM)
@@ -741,24 +741,43 @@
clean-workdir-$1:
$$(RM) -r $$($1_TEST_SUPPORT_DIR)
+ $1_COMMAND_LINE := \
+ $$(JAVA) $$($1_JTREG_LAUNCHER_OPTIONS) \
+ -Dprogram=jtreg -jar $$(JT_HOME)/lib/jtreg.jar \
+ $$($1_JTREG_BASIC_OPTIONS) \
+ -testjdk:$$(JDK_IMAGE_DIR) \
+ -dir:$$(JTREG_TOPDIR) \
+ -reportDir:$$($1_TEST_RESULTS_DIR) \
+ -workDir:$$($1_TEST_SUPPORT_DIR) \
+ -status:$$$${JTREG_STATUS} \
+ $$(JTREG_OPTIONS) \
+ $$(JTREG_FAILURE_HANDLER_OPTIONS) \
+ $$($1_TEST_NAME) \
+ && $$(ECHO) $$$$? > $$($1_EXITCODE) \
+ || $$(ECHO) $$$$? > $$($1_EXITCODE)
+
+
+ ifneq ($$(JTREG_RETRY_COUNT), 0)
+ $1_COMMAND_LINE := \
+ for i in {0..$$(JTREG_RETRY_COUNT)}; do \
+ if [ "$$$$i" != 0 ]; then \
+ $$(PRINTF) "\nRetrying Jtreg run. Attempt: $$$$i\n"; \
+ fi; \
+ $$($1_COMMAND_LINE); \
+ if [ "`$$(CAT) $$($1_EXITCODE)`" = "0" ]; then \
+ break; \
+ fi; \
+ export JTREG_STATUS="-status:error,fail"; \
+ done
+ endif
+
run-test-$1: clean-workdir-$1 $$($1_AOT_TARGETS)
$$(call LogWarn)
$$(call LogWarn, Running test '$$($1_TEST)')
$$(call MakeDir, $$($1_TEST_RESULTS_DIR) $$($1_TEST_SUPPORT_DIR) \
$$($1_TEST_TMP_DIR))
$$(call ExecuteWithLog, $$($1_TEST_SUPPORT_DIR)/jtreg, ( \
- $$(JAVA) $$($1_JTREG_LAUNCHER_OPTIONS) \
- -Dprogram=jtreg -jar $$(JT_HOME)/lib/jtreg.jar \
- $$($1_JTREG_BASIC_OPTIONS) \
- -testjdk:$$(JDK_IMAGE_DIR) \
- -dir:$$(JTREG_TOPDIR) \
- -reportDir:$$($1_TEST_RESULTS_DIR) \
- -workDir:$$($1_TEST_SUPPORT_DIR) \
- $$(JTREG_OPTIONS) \
- $$(JTREG_FAILURE_HANDLER_OPTIONS) \
- $$($1_TEST_NAME) \
- && $$(ECHO) $$$$? > $$($1_EXITCODE) \
- || $$(ECHO) $$$$? > $$($1_EXITCODE) \
+ $$($1_COMMAND_LINE) \
))
$1_RESULT_FILE := $$($1_TEST_RESULTS_DIR)/text/stats.txt
diff -Nru openjdk-lts-11.0.11+9/make/scripts/compare.sh openjdk-lts-11.0.14+9/make/scripts/compare.sh
--- openjdk-lts-11.0.11+9/make/scripts/compare.sh 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/make/scripts/compare.sh 2022-01-13 21:56:25.000000000 +0000
@@ -1,6 +1,6 @@
#!/bin/bash
#
-# Copyright (c) 2012, 2020, Oracle and/or its affiliates. All rights reserved.
+# Copyright (c) 2012, 2021, Oracle and/or its affiliates. All rights reserved.
# DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
#
# This code is free software; you can redistribute it and/or modify it
@@ -1044,7 +1044,7 @@
-o -name '*.zip' -o -name '*.jimage' -o -name '*.java' -o -name '*.mf' \
-o -name '*.jpg' -o -name '*.wsdl' -o -name '*.js' -o -name '*.sh' \
-o -name '*.bat' -o -name '*LICENSE' -o -name '*.d' -o -name '*store' \
- -o -name 'blacklist' -o -name '*certs' -o -name '*.ttf' \
+ -o -name 'blocked' -o -name '*certs' -o -name '*.ttf' \
-o -name '*.jfc' -o -name '*.dat' -o -name 'release' -o -name '*.dir'\
-o -name '*.sym' -o -name '*.idl' -o -name '*.h' -o -name '*.access' \
-o -name '*.template' -o -name '*.policy' -o -name '*.security' \
diff -Nru openjdk-lts-11.0.11+9/make/test/JtregNativeHotspot.gmk openjdk-lts-11.0.14+9/make/test/JtregNativeHotspot.gmk
--- openjdk-lts-11.0.11+9/make/test/JtregNativeHotspot.gmk 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/make/test/JtregNativeHotspot.gmk 2022-01-13 21:56:25.000000000 +0000
@@ -148,6 +148,9 @@
# Optimization -O3 needed, HIGH == -O3
BUILD_HOTSPOT_JTREG_LIBRARIES_OPTIMIZATION_libNoFramePointer := HIGH
+BUILD_HOTSPOT_JTREG_LIBRARIES_CFLAGS := -D__STDC_FORMAT_MACROS -D__STDC_LIMIT_MACROS -D__STDC_CONSTANT_MACROS
+BUILD_HOTSPOT_JTREG_EXECUTABLES_CFLAGS := -D__STDC_FORMAT_MACROS -D__STDC_LIMIT_MACROS -D__STDC_CONSTANT_MACROS
+
BUILD_HOTSPOT_JTREG_LIBRARIES_CFLAGS_libProcessUtils := $(VM_SHARE_INCLUDES)
BUILD_HOTSPOT_JTREG_LIBRARIES_CFLAGS_libThreadController := $(NSK_MONITORING_INCLUDES)
@@ -845,10 +848,6 @@
################################################################################
-ifeq ($(TOOLCHAIN_TYPE), solstudio)
- BUILD_HOTSPOT_JTREG_LIBRARIES_CFLAGS_libji06t001 += -erroff=E_END_OF_LOOP_CODE_NOT_REACHED
-endif
-
# Platform specific setup
ifneq ($(OPENJDK_TARGET_OS)-$(OPENJDK_TARGET_CPU_ARCH), solaris-sparc)
BUILD_HOTSPOT_JTREG_EXCLUDE += liboverflow.c exeThreadSignalMask.c
diff -Nru openjdk-lts-11.0.11+9/make/test/JtregNativeJdk.gmk openjdk-lts-11.0.14+9/make/test/JtregNativeJdk.gmk
--- openjdk-lts-11.0.11+9/make/test/JtregNativeJdk.gmk 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/make/test/JtregNativeJdk.gmk 2022-01-13 21:56:25.000000000 +0000
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2015, 2018, Oracle and/or its affiliates. All rights reserved.
+# Copyright (c) 2015, 2021, Oracle and/or its affiliates. All rights reserved.
# DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
#
# This code is free software; you can redistribute it and/or modify it
@@ -76,11 +76,13 @@
endif
ifeq ($(OPENJDK_TARGET_OS), macosx)
- BUILD_JDK_JTREG_LIBRARIES_CFLAGS_libTestMainKeyWindow := -ObjC
BUILD_JDK_JTREG_LIBRARIES_LIBS_libTestMainKeyWindow := \
- -framework Cocoa -framework JavaNativeFoundation
+ -framework Cocoa
+ BUILD_JDK_JTREG_LIBRARIES_LIBS_libTestDynamicStore := \
+ -framework Cocoa -framework SystemConfiguration
else
- BUILD_JDK_JTREG_EXCLUDE += libTestMainKeyWindow.c
+ BUILD_JDK_JTREG_EXCLUDE += libTestMainKeyWindow.m
+ BUILD_JDK_JTREG_EXCLUDE += libTestDynamicStore.m
endif
$(eval $(call SetupTestFilesCompilation, BUILD_JDK_JTREG_LIBRARIES, \
diff -Nru openjdk-lts-11.0.11+9/make/ToolsJdk.gmk openjdk-lts-11.0.14+9/make/ToolsJdk.gmk
--- openjdk-lts-11.0.11+9/make/ToolsJdk.gmk 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/make/ToolsJdk.gmk 2022-01-13 21:56:25.000000000 +0000
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2011, 2020, Oracle and/or its affiliates. All rights reserved.
+# Copyright (c) 2011, 2021, Oracle and/or its affiliates. All rights reserved.
# DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
#
# This code is free software; you can redistribute it and/or modify it
@@ -73,9 +73,9 @@
TOOL_TZDB = $(JAVA_SMALL) -cp $(BUILDTOOLS_OUTPUTDIR)/jdk_tools_classes \
build.tools.tzdb.TzdbZoneRulesCompiler
-TOOL_BLACKLISTED_CERTS = $(JAVA_SMALL) -cp $(BUILDTOOLS_OUTPUTDIR)/jdk_tools_classes \
+TOOL_BLOCKED_CERTS = $(JAVA_SMALL) -cp $(BUILDTOOLS_OUTPUTDIR)/jdk_tools_classes \
--add-exports java.base/sun.security.util=ALL-UNNAMED \
- build.tools.blacklistedcertsconverter.BlacklistedCertsConverter
+ build.tools.blockedcertsconverter.BlockedCertsConverter
TOOL_MAKEJAVASECURITY = $(JAVA_SMALL) -cp $(BUILDTOOLS_OUTPUTDIR)/jdk_tools_classes \
build.tools.makejavasecurity.MakeJavaSecurity
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/aarch64.ad openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/aarch64.ad
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/aarch64.ad 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/aarch64.ad 2022-01-13 21:56:25.000000000 +0000
@@ -110,8 +110,8 @@
reg_def R16_H ( SOC, SOC, Op_RegI, 16, r16->as_VMReg()->next());
reg_def R17 ( SOC, SOC, Op_RegI, 17, r17->as_VMReg() );
reg_def R17_H ( SOC, SOC, Op_RegI, 17, r17->as_VMReg()->next());
-reg_def R18 ( SOC, SOC, Op_RegI, 18, r18->as_VMReg() );
-reg_def R18_H ( SOC, SOC, Op_RegI, 18, r18->as_VMReg()->next());
+reg_def R18 ( SOC, SOC, Op_RegI, 18, r18_tls->as_VMReg() );
+reg_def R18_H ( SOC, SOC, Op_RegI, 18, r18_tls->as_VMReg()->next());
reg_def R19 ( SOC, SOE, Op_RegI, 19, r19->as_VMReg() );
reg_def R19_H ( SOC, SOE, Op_RegI, 19, r19->as_VMReg()->next());
reg_def R20 ( SOC, SOE, Op_RegI, 20, r20->as_VMReg() ); // caller esp
@@ -201,43 +201,43 @@
reg_def V7_J ( SOC, SOC, Op_RegF, 7, v7->as_VMReg()->next(2) );
reg_def V7_K ( SOC, SOC, Op_RegF, 7, v7->as_VMReg()->next(3) );
- reg_def V8 ( SOC, SOC, Op_RegF, 8, v8->as_VMReg() );
- reg_def V8_H ( SOC, SOC, Op_RegF, 8, v8->as_VMReg()->next() );
+ reg_def V8 ( SOC, SOE, Op_RegF, 8, v8->as_VMReg() );
+ reg_def V8_H ( SOC, SOE, Op_RegF, 8, v8->as_VMReg()->next() );
reg_def V8_J ( SOC, SOC, Op_RegF, 8, v8->as_VMReg()->next(2) );
reg_def V8_K ( SOC, SOC, Op_RegF, 8, v8->as_VMReg()->next(3) );
- reg_def V9 ( SOC, SOC, Op_RegF, 9, v9->as_VMReg() );
- reg_def V9_H ( SOC, SOC, Op_RegF, 9, v9->as_VMReg()->next() );
+ reg_def V9 ( SOC, SOE, Op_RegF, 9, v9->as_VMReg() );
+ reg_def V9_H ( SOC, SOE, Op_RegF, 9, v9->as_VMReg()->next() );
reg_def V9_J ( SOC, SOC, Op_RegF, 9, v9->as_VMReg()->next(2) );
reg_def V9_K ( SOC, SOC, Op_RegF, 9, v9->as_VMReg()->next(3) );
- reg_def V10 ( SOC, SOC, Op_RegF, 10, v10->as_VMReg() );
- reg_def V10_H( SOC, SOC, Op_RegF, 10, v10->as_VMReg()->next() );
+ reg_def V10 ( SOC, SOE, Op_RegF, 10, v10->as_VMReg() );
+ reg_def V10_H( SOC, SOE, Op_RegF, 10, v10->as_VMReg()->next() );
reg_def V10_J( SOC, SOC, Op_RegF, 10, v10->as_VMReg()->next(2));
reg_def V10_K( SOC, SOC, Op_RegF, 10, v10->as_VMReg()->next(3));
- reg_def V11 ( SOC, SOC, Op_RegF, 11, v11->as_VMReg() );
- reg_def V11_H( SOC, SOC, Op_RegF, 11, v11->as_VMReg()->next() );
+ reg_def V11 ( SOC, SOE, Op_RegF, 11, v11->as_VMReg() );
+ reg_def V11_H( SOC, SOE, Op_RegF, 11, v11->as_VMReg()->next() );
reg_def V11_J( SOC, SOC, Op_RegF, 11, v11->as_VMReg()->next(2));
reg_def V11_K( SOC, SOC, Op_RegF, 11, v11->as_VMReg()->next(3));
- reg_def V12 ( SOC, SOC, Op_RegF, 12, v12->as_VMReg() );
- reg_def V12_H( SOC, SOC, Op_RegF, 12, v12->as_VMReg()->next() );
+ reg_def V12 ( SOC, SOE, Op_RegF, 12, v12->as_VMReg() );
+ reg_def V12_H( SOC, SOE, Op_RegF, 12, v12->as_VMReg()->next() );
reg_def V12_J( SOC, SOC, Op_RegF, 12, v12->as_VMReg()->next(2));
reg_def V12_K( SOC, SOC, Op_RegF, 12, v12->as_VMReg()->next(3));
- reg_def V13 ( SOC, SOC, Op_RegF, 13, v13->as_VMReg() );
- reg_def V13_H( SOC, SOC, Op_RegF, 13, v13->as_VMReg()->next() );
+ reg_def V13 ( SOC, SOE, Op_RegF, 13, v13->as_VMReg() );
+ reg_def V13_H( SOC, SOE, Op_RegF, 13, v13->as_VMReg()->next() );
reg_def V13_J( SOC, SOC, Op_RegF, 13, v13->as_VMReg()->next(2));
reg_def V13_K( SOC, SOC, Op_RegF, 13, v13->as_VMReg()->next(3));
- reg_def V14 ( SOC, SOC, Op_RegF, 14, v14->as_VMReg() );
- reg_def V14_H( SOC, SOC, Op_RegF, 14, v14->as_VMReg()->next() );
+ reg_def V14 ( SOC, SOE, Op_RegF, 14, v14->as_VMReg() );
+ reg_def V14_H( SOC, SOE, Op_RegF, 14, v14->as_VMReg()->next() );
reg_def V14_J( SOC, SOC, Op_RegF, 14, v14->as_VMReg()->next(2));
reg_def V14_K( SOC, SOC, Op_RegF, 14, v14->as_VMReg()->next(3));
- reg_def V15 ( SOC, SOC, Op_RegF, 15, v15->as_VMReg() );
- reg_def V15_H( SOC, SOC, Op_RegF, 15, v15->as_VMReg()->next() );
+ reg_def V15 ( SOC, SOE, Op_RegF, 15, v15->as_VMReg() );
+ reg_def V15_H( SOC, SOE, Op_RegF, 15, v15->as_VMReg()->next() );
reg_def V15_J( SOC, SOC, Op_RegF, 15, v15->as_VMReg()->next(2));
reg_def V15_K( SOC, SOC, Op_RegF, 15, v15->as_VMReg()->next(3));
@@ -352,7 +352,6 @@
R15, R15_H,
R16, R16_H,
R17, R17_H,
- R18, R18_H,
// arg registers
R0, R0_H,
@@ -375,7 +374,7 @@
R26, R26_H,
// non-allocatable registers
-
+ R18, R18_H, // platform
R27, R27_H, // heapbase
R28, R28_H, // thread
R29, R29_H, // fp
@@ -533,7 +532,10 @@
R15,
R16,
R17,
+#ifndef R18_RESERVED
+ // See comment in register_aarch64.hpp
R18,
+#endif
R19,
R20,
R21,
@@ -566,7 +568,10 @@
R15,
R16,
R17,
+#ifndef R18_RESERVED
+ // See comment in register_aarch64.hpp
R18,
+#endif
R19,
R20,
R21,
@@ -602,7 +607,10 @@
R15, R15_H,
R16, R16_H,
R17, R17_H,
+#ifndef R18_RESERVED
+ // See comment in register_aarch64.hpp
R18, R18_H,
+#endif
R19, R19_H,
R20, R20_H,
R21, R21_H,
@@ -635,7 +643,10 @@
R15, R15_H,
R16, R16_H,
R17, R17_H,
+#ifndef R18_RESERVED
+ // See comment in register_aarch64.hpp
R18, R18_H,
+#endif
R19, R19_H,
R20, R20_H,
R21, R21_H,
@@ -775,7 +786,10 @@
R15, R15_H,
R16, R16_H,
R17, R17_H,
+#ifndef R18_RESERVED
+ // See comment in register_aarch64.hpp
R18, R18_H,
+#endif
R19, R19_H,
R20, R20_H,
R21, R21_H,
@@ -1615,7 +1629,7 @@
MacroAssembler _masm(&cbuf);
// n.b. frame size includes space for return pc and rfp
- const long framesize = C->frame_size_in_bytes();
+ const int framesize = C->frame_size_in_bytes();
assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment");
// insert a nop at the start of the prolog so we can patch in a
@@ -1733,13 +1747,14 @@
// we have 30 int registers * 2 halves
// (rscratch1 and rscratch2 are omitted)
+ int slots_of_int_registers = RegisterImpl::max_slots_per_register * (RegisterImpl::number_of_registers - 2);
- if (reg < 60) {
+ if (reg < slots_of_int_registers) {
return rc_int;
}
- // we have 32 float register * 2 halves
- if (reg < 60 + 128) {
+ // we have 32 float register * 4 halves
+ if (reg < slots_of_int_registers + FloatRegisterImpl::max_slots_per_register * FloatRegisterImpl::number_of_registers) {
return rc_float;
}
@@ -2296,6 +2311,13 @@
bool size_fits_all_mem_uses(AddPNode* addp, int shift) {
for (DUIterator_Fast imax, i = addp->fast_outs(imax); i < imax; i++) {
Node* u = addp->fast_out(i);
+ if (u->is_LoadStore()) {
+ // On AArch64, LoadStoreNodes (i.e. compare and swap
+ // instructions) only take register indirect as an operand, so
+ // any attempt to use an AddPNode as an input to a LoadStoreNode
+ // must fail.
+ return false;
+ }
if (u->is_Mem()) {
int opsize = u->as_Mem()->memory_size();
assert(opsize > 0, "unexpected memory operand size");
@@ -2967,7 +2989,7 @@
enc_class aarch64_enc_movw_imm(iRegI dst, immI src) %{
MacroAssembler _masm(&cbuf);
- u_int32_t con = (u_int32_t)$src$$constant;
+ uint32_t con = (uint32_t)$src$$constant;
Register dst_reg = as_Register($dst$$reg);
if (con == 0) {
__ movw(dst_reg, zr);
@@ -2979,7 +3001,7 @@
enc_class aarch64_enc_mov_imm(iRegL dst, immL src) %{
MacroAssembler _masm(&cbuf);
Register dst_reg = as_Register($dst$$reg);
- u_int64_t con = (u_int64_t)$src$$constant;
+ uint64_t con = (uint64_t)$src$$constant;
if (con == 0) {
__ mov(dst_reg, zr);
} else {
@@ -3004,7 +3026,7 @@
if (con < (address)(uintptr_t)os::vm_page_size()) {
__ mov(dst_reg, con);
} else {
- unsigned long offset;
+ uint64_t offset;
__ adrp(dst_reg, con, offset);
__ add(dst_reg, dst_reg, offset);
}
@@ -3021,14 +3043,14 @@
enc_class aarch64_enc_mov_p1(iRegP dst, immP_1 src) %{
MacroAssembler _masm(&cbuf);
Register dst_reg = as_Register($dst$$reg);
- __ mov(dst_reg, (u_int64_t)1);
+ __ mov(dst_reg, (uint64_t)1);
%}
enc_class aarch64_enc_mov_poll_page(iRegP dst, immPollPage src) %{
MacroAssembler _masm(&cbuf);
address page = (address)$src$$constant;
Register dst_reg = as_Register($dst$$reg);
- unsigned long off;
+ uint64_t off;
__ adrp(dst_reg, Address(page, relocInfo::poll_type), off);
assert(off == 0, "assumed offset == 0");
%}
@@ -3155,7 +3177,7 @@
enc_class aarch64_enc_cmpw_imm(iRegI src1, immI src2) %{
MacroAssembler _masm(&cbuf);
Register reg1 = as_Register($src1$$reg);
- u_int32_t val = (u_int32_t)$src2$$constant;
+ uint32_t val = (uint32_t)$src2$$constant;
__ movw(rscratch1, val);
__ cmpw(reg1, rscratch1);
%}
@@ -3177,7 +3199,7 @@
__ adds(zr, reg, -val);
} else {
// aargh, Long.MIN_VALUE is a special case
- __ orr(rscratch1, zr, (u_int64_t)val);
+ __ orr(rscratch1, zr, (uint64_t)val);
__ subs(zr, reg, rscratch1);
}
%}
@@ -3185,7 +3207,7 @@
enc_class aarch64_enc_cmp_imm(iRegL src1, immL src2) %{
MacroAssembler _masm(&cbuf);
Register reg1 = as_Register($src1$$reg);
- u_int64_t val = (u_int64_t)$src2$$constant;
+ uint64_t val = (uint64_t)$src2$$constant;
__ mov(rscratch1, val);
__ cmp(reg1, rscratch1);
%}
@@ -3260,12 +3282,19 @@
if (!_method) {
// A call to a runtime wrapper, e.g. new, new_typeArray_Java, uncommon_trap.
call = __ trampoline_call(Address(addr, relocInfo::runtime_call_type), &cbuf);
+ if (call == NULL) {
+ ciEnv::current()->record_failure("CodeCache is full");
+ return;
+ }
} else {
int method_index = resolved_method_index(cbuf);
RelocationHolder rspec = _optimized_virtual ? opt_virtual_call_Relocation::spec(method_index)
: static_call_Relocation::spec(method_index);
call = __ trampoline_call(Address(addr, rspec), &cbuf);
-
+ if (call == NULL) {
+ ciEnv::current()->record_failure("CodeCache is full");
+ return;
+ }
// Emit stub for static call
address stub = CompiledStaticCall::emit_to_interp_stub(cbuf);
if (stub == NULL) {
@@ -3273,10 +3302,6 @@
return;
}
}
- if (call == NULL) {
- ciEnv::current()->record_failure("CodeCache is full");
- return;
- }
%}
enc_class aarch64_enc_java_dynamic_call(method meth) %{
@@ -3925,6 +3950,18 @@
interface(CONST_INTER);
%}
+operand immL_positive_bitmaskI()
+%{
+ predicate((n->get_long() != 0)
+ && ((julong)n->get_long() < 0x80000000ULL)
+ && is_power_of_2(n->get_long() + 1));
+ match(ConL);
+
+ op_cost(0);
+ format %{ %}
+ interface(CONST_INTER);
+%}
+
// Scale values for scaled offset addressing modes (up to long but not quad)
operand immIScale()
%{
@@ -4063,7 +4100,7 @@
// 32 bit integer valid for add sub immediate
operand immIAddSub()
%{
- predicate(Assembler::operand_valid_for_add_sub_immediate((long)n->get_int()));
+ predicate(Assembler::operand_valid_for_add_sub_immediate((int64_t)n->get_int()));
match(ConI);
op_cost(0);
format %{ %}
@@ -4074,7 +4111,7 @@
// TODO -- check this is right when e.g the mask is 0x80000000
operand immILog()
%{
- predicate(Assembler::operand_valid_for_logical_immediate(/*is32*/true, (unsigned long)n->get_int()));
+ predicate(Assembler::operand_valid_for_logical_immediate(/*is32*/true, (uint64_t)n->get_int()));
match(ConI);
op_cost(0);
@@ -4152,7 +4189,7 @@
// 64 bit integer valid for logical immediate
operand immLLog()
%{
- predicate(Assembler::operand_valid_for_logical_immediate(/*is32*/false, (unsigned long)n->get_long()));
+ predicate(Assembler::operand_valid_for_logical_immediate(/*is32*/false, (uint64_t)n->get_long()));
match(ConL);
op_cost(0);
format %{ %}
@@ -9644,7 +9681,7 @@
ins_encode %{
__ sbfiz(as_Register($dst$$reg),
as_Register($src$$reg),
- $scale$$constant & 63, MIN(32, (-$scale$$constant) & 63));
+ $scale$$constant & 63, MIN2(32, (int)((-$scale$$constant) & 63)));
%}
ins_pipe(ialu_reg_shift);
@@ -9927,40 +9964,66 @@
ins_pipe(lmac_reg_reg);
%}
-// Integer Divide
+// Combine Integer Signed Multiply & Add/Sub/Neg Long
-instruct divI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
- match(Set dst (DivI src1 src2));
+instruct smaddL(iRegLNoSp dst, iRegIorL2I src1, iRegIorL2I src2, iRegLNoSp src3) %{
+ match(Set dst (AddL src3 (MulL (ConvI2L src1) (ConvI2L src2))));
- ins_cost(INSN_COST * 19);
- format %{ "sdivw $dst, $src1, $src2" %}
+ ins_cost(INSN_COST * 3);
+ format %{ "smaddl $dst, $src1, $src2, $src3" %}
- ins_encode(aarch64_enc_divw(dst, src1, src2));
- ins_pipe(idiv_reg_reg);
+ ins_encode %{
+ __ smaddl(as_Register($dst$$reg),
+ as_Register($src1$$reg),
+ as_Register($src2$$reg),
+ as_Register($src3$$reg));
+ %}
+
+ ins_pipe(imac_reg_reg);
%}
-instruct signExtract(iRegINoSp dst, iRegIorL2I src1, immI_31 div1, immI_31 div2) %{
- match(Set dst (URShiftI (RShiftI src1 div1) div2));
- ins_cost(INSN_COST);
- format %{ "lsrw $dst, $src1, $div1" %}
+instruct smsubL(iRegLNoSp dst, iRegIorL2I src1, iRegIorL2I src2, iRegLNoSp src3) %{
+ match(Set dst (SubL src3 (MulL (ConvI2L src1) (ConvI2L src2))));
+
+ ins_cost(INSN_COST * 3);
+ format %{ "smsubl $dst, $src1, $src2, $src3" %}
+
ins_encode %{
- __ lsrw(as_Register($dst$$reg), as_Register($src1$$reg), 31);
+ __ smsubl(as_Register($dst$$reg),
+ as_Register($src1$$reg),
+ as_Register($src2$$reg),
+ as_Register($src3$$reg));
%}
- ins_pipe(ialu_reg_shift);
+
+ ins_pipe(imac_reg_reg);
%}
-instruct div2Round(iRegINoSp dst, iRegIorL2I src, immI_31 div1, immI_31 div2) %{
- match(Set dst (AddI src (URShiftI (RShiftI src div1) div2)));
- ins_cost(INSN_COST);
- format %{ "addw $dst, $src, LSR $div1" %}
+instruct smnegL(iRegLNoSp dst, iRegIorL2I src1, iRegIorL2I src2, immL0 zero) %{
+ match(Set dst (MulL (SubL zero (ConvI2L src1)) (ConvI2L src2)));
+ match(Set dst (MulL (ConvI2L src1) (SubL zero (ConvI2L src2))));
+
+ ins_cost(INSN_COST * 3);
+ format %{ "smnegl $dst, $src1, $src2" %}
ins_encode %{
- __ addw(as_Register($dst$$reg),
- as_Register($src$$reg),
- as_Register($src$$reg),
- Assembler::LSR, 31);
+ __ smnegl(as_Register($dst$$reg),
+ as_Register($src1$$reg),
+ as_Register($src2$$reg));
%}
- ins_pipe(ialu_reg);
+
+ ins_pipe(imac_reg_reg);
+%}
+
+// Integer Divide
+
+instruct divI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
+ match(Set dst (DivI src1 src2));
+
+ ins_cost(INSN_COST * 19);
+ format %{ "sdivw $dst, $src1, $src2" %}
+
+ ins_encode(aarch64_enc_divw(dst, src1, src2));
+ ins_pipe(idiv_reg_reg);
%}
// Long Divide
@@ -9975,30 +10038,6 @@
ins_pipe(ldiv_reg_reg);
%}
-instruct signExtractL(iRegLNoSp dst, iRegL src1, immI_63 div1, immI_63 div2) %{
- match(Set dst (URShiftL (RShiftL src1 div1) div2));
- ins_cost(INSN_COST);
- format %{ "lsr $dst, $src1, $div1" %}
- ins_encode %{
- __ lsr(as_Register($dst$$reg), as_Register($src1$$reg), 63);
- %}
- ins_pipe(ialu_reg_shift);
-%}
-
-instruct div2RoundL(iRegLNoSp dst, iRegL src, immI_63 div1, immI_63 div2) %{
- match(Set dst (AddL src (URShiftL (RShiftL src div1) div2)));
- ins_cost(INSN_COST);
- format %{ "add $dst, $src, $div1" %}
-
- ins_encode %{
- __ add(as_Register($dst$$reg),
- as_Register($src$$reg),
- as_Register($src$$reg),
- Assembler::LSR, 63);
- %}
- ins_pipe(ialu_reg);
-%}
-
// Integer Remainder
instruct modI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
@@ -10242,6 +10281,10 @@
// BEGIN This section of the file is automatically generated. Do not edit --------------
+
+
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct regL_not_reg(iRegLNoSp dst,
iRegL src1, immL_M1 m1,
rFlagsReg cr) %{
@@ -10258,6 +10301,9 @@
ins_pipe(ialu_reg);
%}
+
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct regI_not_reg(iRegINoSp dst,
iRegIorL2I src1, immI_M1 m1,
rFlagsReg cr) %{
@@ -10275,6 +10321,8 @@
ins_pipe(ialu_reg);
%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct AndI_reg_not_reg(iRegINoSp dst,
iRegIorL2I src1, iRegIorL2I src2, immI_M1 m1,
rFlagsReg cr) %{
@@ -10292,6 +10340,8 @@
ins_pipe(ialu_reg_reg);
%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct AndL_reg_not_reg(iRegLNoSp dst,
iRegL src1, iRegL src2, immL_M1 m1,
rFlagsReg cr) %{
@@ -10309,6 +10359,8 @@
ins_pipe(ialu_reg_reg);
%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct OrI_reg_not_reg(iRegINoSp dst,
iRegIorL2I src1, iRegIorL2I src2, immI_M1 m1,
rFlagsReg cr) %{
@@ -10326,6 +10378,8 @@
ins_pipe(ialu_reg_reg);
%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct OrL_reg_not_reg(iRegLNoSp dst,
iRegL src1, iRegL src2, immL_M1 m1,
rFlagsReg cr) %{
@@ -10343,6 +10397,8 @@
ins_pipe(ialu_reg_reg);
%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct XorI_reg_not_reg(iRegINoSp dst,
iRegIorL2I src1, iRegIorL2I src2, immI_M1 m1,
rFlagsReg cr) %{
@@ -10360,6 +10416,8 @@
ins_pipe(ialu_reg_reg);
%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct XorL_reg_not_reg(iRegLNoSp dst,
iRegL src1, iRegL src2, immL_M1 m1,
rFlagsReg cr) %{
@@ -10377,6 +10435,8 @@
ins_pipe(ialu_reg_reg);
%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct AndI_reg_URShift_not_reg(iRegINoSp dst,
iRegIorL2I src1, iRegIorL2I src2,
immI src3, immI_M1 src4, rFlagsReg cr) %{
@@ -10395,6 +10455,8 @@
ins_pipe(ialu_reg_reg_shift);
%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct AndL_reg_URShift_not_reg(iRegLNoSp dst,
iRegL src1, iRegL src2,
immI src3, immL_M1 src4, rFlagsReg cr) %{
@@ -10413,6 +10475,8 @@
ins_pipe(ialu_reg_reg_shift);
%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct AndI_reg_RShift_not_reg(iRegINoSp dst,
iRegIorL2I src1, iRegIorL2I src2,
immI src3, immI_M1 src4, rFlagsReg cr) %{
@@ -10431,6 +10495,8 @@
ins_pipe(ialu_reg_reg_shift);
%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct AndL_reg_RShift_not_reg(iRegLNoSp dst,
iRegL src1, iRegL src2,
immI src3, immL_M1 src4, rFlagsReg cr) %{
@@ -10449,6 +10515,8 @@
ins_pipe(ialu_reg_reg_shift);
%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct AndI_reg_LShift_not_reg(iRegINoSp dst,
iRegIorL2I src1, iRegIorL2I src2,
immI src3, immI_M1 src4, rFlagsReg cr) %{
@@ -10467,6 +10535,8 @@
ins_pipe(ialu_reg_reg_shift);
%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct AndL_reg_LShift_not_reg(iRegLNoSp dst,
iRegL src1, iRegL src2,
immI src3, immL_M1 src4, rFlagsReg cr) %{
@@ -10485,6 +10555,8 @@
ins_pipe(ialu_reg_reg_shift);
%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct XorI_reg_URShift_not_reg(iRegINoSp dst,
iRegIorL2I src1, iRegIorL2I src2,
immI src3, immI_M1 src4, rFlagsReg cr) %{
@@ -10503,6 +10575,8 @@
ins_pipe(ialu_reg_reg_shift);
%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct XorL_reg_URShift_not_reg(iRegLNoSp dst,
iRegL src1, iRegL src2,
immI src3, immL_M1 src4, rFlagsReg cr) %{
@@ -10521,6 +10595,8 @@
ins_pipe(ialu_reg_reg_shift);
%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct XorI_reg_RShift_not_reg(iRegINoSp dst,
iRegIorL2I src1, iRegIorL2I src2,
immI src3, immI_M1 src4, rFlagsReg cr) %{
@@ -10539,6 +10615,8 @@
ins_pipe(ialu_reg_reg_shift);
%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct XorL_reg_RShift_not_reg(iRegLNoSp dst,
iRegL src1, iRegL src2,
immI src3, immL_M1 src4, rFlagsReg cr) %{
@@ -10557,6 +10635,8 @@
ins_pipe(ialu_reg_reg_shift);
%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct XorI_reg_LShift_not_reg(iRegINoSp dst,
iRegIorL2I src1, iRegIorL2I src2,
immI src3, immI_M1 src4, rFlagsReg cr) %{
@@ -10575,6 +10655,8 @@
ins_pipe(ialu_reg_reg_shift);
%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct XorL_reg_LShift_not_reg(iRegLNoSp dst,
iRegL src1, iRegL src2,
immI src3, immL_M1 src4, rFlagsReg cr) %{
@@ -10593,6 +10675,8 @@
ins_pipe(ialu_reg_reg_shift);
%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct OrI_reg_URShift_not_reg(iRegINoSp dst,
iRegIorL2I src1, iRegIorL2I src2,
immI src3, immI_M1 src4, rFlagsReg cr) %{
@@ -10611,6 +10695,8 @@
ins_pipe(ialu_reg_reg_shift);
%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct OrL_reg_URShift_not_reg(iRegLNoSp dst,
iRegL src1, iRegL src2,
immI src3, immL_M1 src4, rFlagsReg cr) %{
@@ -10629,6 +10715,8 @@
ins_pipe(ialu_reg_reg_shift);
%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct OrI_reg_RShift_not_reg(iRegINoSp dst,
iRegIorL2I src1, iRegIorL2I src2,
immI src3, immI_M1 src4, rFlagsReg cr) %{
@@ -10647,6 +10735,8 @@
ins_pipe(ialu_reg_reg_shift);
%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct OrL_reg_RShift_not_reg(iRegLNoSp dst,
iRegL src1, iRegL src2,
immI src3, immL_M1 src4, rFlagsReg cr) %{
@@ -10665,6 +10755,8 @@
ins_pipe(ialu_reg_reg_shift);
%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct OrI_reg_LShift_not_reg(iRegINoSp dst,
iRegIorL2I src1, iRegIorL2I src2,
immI src3, immI_M1 src4, rFlagsReg cr) %{
@@ -10683,6 +10775,8 @@
ins_pipe(ialu_reg_reg_shift);
%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct OrL_reg_LShift_not_reg(iRegLNoSp dst,
iRegL src1, iRegL src2,
immI src3, immL_M1 src4, rFlagsReg cr) %{
@@ -10701,6 +10795,8 @@
ins_pipe(ialu_reg_reg_shift);
%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct AndI_reg_URShift_reg(iRegINoSp dst,
iRegIorL2I src1, iRegIorL2I src2,
immI src3, rFlagsReg cr) %{
@@ -10720,6 +10816,8 @@
ins_pipe(ialu_reg_reg_shift);
%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct AndL_reg_URShift_reg(iRegLNoSp dst,
iRegL src1, iRegL src2,
immI src3, rFlagsReg cr) %{
@@ -10739,6 +10837,8 @@
ins_pipe(ialu_reg_reg_shift);
%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct AndI_reg_RShift_reg(iRegINoSp dst,
iRegIorL2I src1, iRegIorL2I src2,
immI src3, rFlagsReg cr) %{
@@ -10758,6 +10858,8 @@
ins_pipe(ialu_reg_reg_shift);
%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct AndL_reg_RShift_reg(iRegLNoSp dst,
iRegL src1, iRegL src2,
immI src3, rFlagsReg cr) %{
@@ -10777,6 +10879,8 @@
ins_pipe(ialu_reg_reg_shift);
%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct AndI_reg_LShift_reg(iRegINoSp dst,
iRegIorL2I src1, iRegIorL2I src2,
immI src3, rFlagsReg cr) %{
@@ -10796,6 +10900,8 @@
ins_pipe(ialu_reg_reg_shift);
%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct AndL_reg_LShift_reg(iRegLNoSp dst,
iRegL src1, iRegL src2,
immI src3, rFlagsReg cr) %{
@@ -10815,6 +10921,8 @@
ins_pipe(ialu_reg_reg_shift);
%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct XorI_reg_URShift_reg(iRegINoSp dst,
iRegIorL2I src1, iRegIorL2I src2,
immI src3, rFlagsReg cr) %{
@@ -10834,6 +10942,8 @@
ins_pipe(ialu_reg_reg_shift);
%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct XorL_reg_URShift_reg(iRegLNoSp dst,
iRegL src1, iRegL src2,
immI src3, rFlagsReg cr) %{
@@ -10853,6 +10963,8 @@
ins_pipe(ialu_reg_reg_shift);
%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct XorI_reg_RShift_reg(iRegINoSp dst,
iRegIorL2I src1, iRegIorL2I src2,
immI src3, rFlagsReg cr) %{
@@ -10872,6 +10984,8 @@
ins_pipe(ialu_reg_reg_shift);
%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct XorL_reg_RShift_reg(iRegLNoSp dst,
iRegL src1, iRegL src2,
immI src3, rFlagsReg cr) %{
@@ -10891,6 +11005,8 @@
ins_pipe(ialu_reg_reg_shift);
%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct XorI_reg_LShift_reg(iRegINoSp dst,
iRegIorL2I src1, iRegIorL2I src2,
immI src3, rFlagsReg cr) %{
@@ -10910,6 +11026,8 @@
ins_pipe(ialu_reg_reg_shift);
%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct XorL_reg_LShift_reg(iRegLNoSp dst,
iRegL src1, iRegL src2,
immI src3, rFlagsReg cr) %{
@@ -10929,6 +11047,8 @@
ins_pipe(ialu_reg_reg_shift);
%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct OrI_reg_URShift_reg(iRegINoSp dst,
iRegIorL2I src1, iRegIorL2I src2,
immI src3, rFlagsReg cr) %{
@@ -10948,6 +11068,8 @@
ins_pipe(ialu_reg_reg_shift);
%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct OrL_reg_URShift_reg(iRegLNoSp dst,
iRegL src1, iRegL src2,
immI src3, rFlagsReg cr) %{
@@ -10967,6 +11089,8 @@
ins_pipe(ialu_reg_reg_shift);
%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct OrI_reg_RShift_reg(iRegINoSp dst,
iRegIorL2I src1, iRegIorL2I src2,
immI src3, rFlagsReg cr) %{
@@ -10986,6 +11110,8 @@
ins_pipe(ialu_reg_reg_shift);
%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct OrL_reg_RShift_reg(iRegLNoSp dst,
iRegL src1, iRegL src2,
immI src3, rFlagsReg cr) %{
@@ -11005,6 +11131,8 @@
ins_pipe(ialu_reg_reg_shift);
%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct OrI_reg_LShift_reg(iRegINoSp dst,
iRegIorL2I src1, iRegIorL2I src2,
immI src3, rFlagsReg cr) %{
@@ -11024,6 +11152,8 @@
ins_pipe(ialu_reg_reg_shift);
%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct OrL_reg_LShift_reg(iRegLNoSp dst,
iRegL src1, iRegL src2,
immI src3, rFlagsReg cr) %{
@@ -11043,6 +11173,8 @@
ins_pipe(ialu_reg_reg_shift);
%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct AddI_reg_URShift_reg(iRegINoSp dst,
iRegIorL2I src1, iRegIorL2I src2,
immI src3, rFlagsReg cr) %{
@@ -11062,6 +11194,8 @@
ins_pipe(ialu_reg_reg_shift);
%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct AddL_reg_URShift_reg(iRegLNoSp dst,
iRegL src1, iRegL src2,
immI src3, rFlagsReg cr) %{
@@ -11081,6 +11215,8 @@
ins_pipe(ialu_reg_reg_shift);
%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct AddI_reg_RShift_reg(iRegINoSp dst,
iRegIorL2I src1, iRegIorL2I src2,
immI src3, rFlagsReg cr) %{
@@ -11100,6 +11236,8 @@
ins_pipe(ialu_reg_reg_shift);
%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct AddL_reg_RShift_reg(iRegLNoSp dst,
iRegL src1, iRegL src2,
immI src3, rFlagsReg cr) %{
@@ -11119,6 +11257,8 @@
ins_pipe(ialu_reg_reg_shift);
%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct AddI_reg_LShift_reg(iRegINoSp dst,
iRegIorL2I src1, iRegIorL2I src2,
immI src3, rFlagsReg cr) %{
@@ -11138,6 +11278,8 @@
ins_pipe(ialu_reg_reg_shift);
%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct AddL_reg_LShift_reg(iRegLNoSp dst,
iRegL src1, iRegL src2,
immI src3, rFlagsReg cr) %{
@@ -11157,6 +11299,8 @@
ins_pipe(ialu_reg_reg_shift);
%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct SubI_reg_URShift_reg(iRegINoSp dst,
iRegIorL2I src1, iRegIorL2I src2,
immI src3, rFlagsReg cr) %{
@@ -11176,6 +11320,8 @@
ins_pipe(ialu_reg_reg_shift);
%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct SubL_reg_URShift_reg(iRegLNoSp dst,
iRegL src1, iRegL src2,
immI src3, rFlagsReg cr) %{
@@ -11195,6 +11341,8 @@
ins_pipe(ialu_reg_reg_shift);
%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct SubI_reg_RShift_reg(iRegINoSp dst,
iRegIorL2I src1, iRegIorL2I src2,
immI src3, rFlagsReg cr) %{
@@ -11214,6 +11362,8 @@
ins_pipe(ialu_reg_reg_shift);
%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct SubL_reg_RShift_reg(iRegLNoSp dst,
iRegL src1, iRegL src2,
immI src3, rFlagsReg cr) %{
@@ -11233,6 +11383,8 @@
ins_pipe(ialu_reg_reg_shift);
%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct SubI_reg_LShift_reg(iRegINoSp dst,
iRegIorL2I src1, iRegIorL2I src2,
immI src3, rFlagsReg cr) %{
@@ -11252,6 +11404,8 @@
ins_pipe(ialu_reg_reg_shift);
%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct SubL_reg_LShift_reg(iRegLNoSp dst,
iRegL src1, iRegL src2,
immI src3, rFlagsReg cr) %{
@@ -11271,7 +11425,9 @@
ins_pipe(ialu_reg_reg_shift);
%}
-
+
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
// Shift Left followed by Shift Right.
// This idiom is used by the compiler for the i2b bytecode etc.
@@ -11293,6 +11449,9 @@
ins_pipe(ialu_reg_shift);
%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
+
// Shift Left followed by Shift Right.
// This idiom is used by the compiler for the i2b bytecode etc.
instruct sbfmwI(iRegINoSp dst, iRegIorL2I src, immI lshift_count, immI rshift_count)
@@ -11313,6 +11472,9 @@
ins_pipe(ialu_reg_shift);
%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
+
// Shift Left followed by Shift Right.
// This idiom is used by the compiler for the i2b bytecode etc.
instruct ubfmL(iRegLNoSp dst, iRegL src, immI lshift_count, immI rshift_count)
@@ -11333,6 +11495,9 @@
ins_pipe(ialu_reg_shift);
%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
+
// Shift Left followed by Shift Right.
// This idiom is used by the compiler for the i2b bytecode etc.
instruct ubfmwI(iRegINoSp dst, iRegIorL2I src, immI lshift_count, immI rshift_count)
@@ -11352,8 +11517,11 @@
ins_pipe(ialu_reg_shift);
%}
+
// Bitfield extract with shift & mask
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct ubfxwI(iRegINoSp dst, iRegIorL2I src, immI rshift, immI_bitmask mask)
%{
match(Set dst (AndI (URShiftI src rshift) mask));
@@ -11364,13 +11532,16 @@
format %{ "ubfxw $dst, $src, $rshift, $mask" %}
ins_encode %{
int rshift = $rshift$$constant & 31;
- long mask = $mask$$constant;
+ intptr_t mask = $mask$$constant;
int width = exact_log2(mask+1);
__ ubfxw(as_Register($dst$$reg),
as_Register($src$$reg), rshift, width);
%}
ins_pipe(ialu_reg_shift);
%}
+
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct ubfxL(iRegLNoSp dst, iRegL src, immI rshift, immL_bitmask mask)
%{
match(Set dst (AndL (URShiftL src rshift) mask));
@@ -11381,7 +11552,7 @@
format %{ "ubfx $dst, $src, $rshift, $mask" %}
ins_encode %{
int rshift = $rshift$$constant & 63;
- long mask = $mask$$constant;
+ intptr_t mask = $mask$$constant;
int width = exact_log2_long(mask+1);
__ ubfx(as_Register($dst$$reg),
as_Register($src$$reg), rshift, width);
@@ -11389,6 +11560,10 @@
ins_pipe(ialu_reg_shift);
%}
+
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
+
// We can use ubfx when extending an And with a mask when we know mask
// is positive. We know that because immI_bitmask guarantees it.
instruct ubfxIConvI2L(iRegLNoSp dst, iRegIorL2I src, immI rshift, immI_bitmask mask)
@@ -11401,7 +11576,7 @@
format %{ "ubfx $dst, $src, $rshift, $mask" %}
ins_encode %{
int rshift = $rshift$$constant & 31;
- long mask = $mask$$constant;
+ intptr_t mask = $mask$$constant;
int width = exact_log2(mask+1);
__ ubfx(as_Register($dst$$reg),
as_Register($src$$reg), rshift, width);
@@ -11409,6 +11584,10 @@
ins_pipe(ialu_reg_shift);
%}
+
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
+
// We can use ubfiz when masking by a positive number and then left shifting the result.
// We know that the mask is positive because immI_bitmask guarantees it.
instruct ubfizwI(iRegINoSp dst, iRegIorL2I src, immI lshift, immI_bitmask mask)
@@ -11420,13 +11599,17 @@
format %{ "ubfizw $dst, $src, $lshift, $mask" %}
ins_encode %{
int lshift = $lshift$$constant & 31;
- long mask = $mask$$constant;
+ intptr_t mask = $mask$$constant;
int width = exact_log2(mask+1);
__ ubfizw(as_Register($dst$$reg),
as_Register($src$$reg), lshift, width);
%}
ins_pipe(ialu_reg_shift);
%}
+
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
+
// We can use ubfiz when masking by a positive number and then left shifting the result.
// We know that the mask is positive because immL_bitmask guarantees it.
instruct ubfizL(iRegLNoSp dst, iRegL src, immI lshift, immL_bitmask mask)
@@ -11438,7 +11621,7 @@
format %{ "ubfiz $dst, $src, $lshift, $mask" %}
ins_encode %{
int lshift = $lshift$$constant & 63;
- long mask = $mask$$constant;
+ intptr_t mask = $mask$$constant;
int width = exact_log2_long(mask+1);
__ ubfiz(as_Register($dst$$reg),
as_Register($src$$reg), lshift, width);
@@ -11446,6 +11629,54 @@
ins_pipe(ialu_reg_shift);
%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
+
+// We can use ubfiz when masking by a positive number and then left shifting the result.
+// We know that the mask is positive because immI_bitmask guarantees it.
+instruct ubfizwIConvI2L(iRegLNoSp dst, iRegIorL2I src, immI lshift, immI_bitmask mask)
+%{
+ match(Set dst (ConvI2L (LShiftI (AndI src mask) lshift)));
+ predicate((exact_log2(n->in(1)->in(1)->in(2)->get_int() + 1) + (n->in(1)->in(2)->get_int() & 31)) <= 31);
+
+ ins_cost(INSN_COST);
+ format %{ "ubfizw $dst, $src, $lshift, $mask" %}
+ ins_encode %{
+ int lshift = $lshift$$constant & 31;
+ intptr_t mask = $mask$$constant;
+ int width = exact_log2(mask+1);
+ __ ubfizw(as_Register($dst$$reg),
+ as_Register($src$$reg), lshift, width);
+ %}
+ ins_pipe(ialu_reg_shift);
+%}
+
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
+
+// We can use ubfiz when masking by a positive number and then left shifting the result.
+// We know that the mask is positive because immL_bitmask guarantees it.
+instruct ubfizLConvL2I(iRegINoSp dst, iRegL src, immI lshift, immL_positive_bitmaskI mask)
+%{
+ match(Set dst (ConvL2I (LShiftL (AndL src mask) lshift)));
+ predicate((exact_log2_long(n->in(1)->in(1)->in(2)->get_long() + 1) + (n->in(1)->in(2)->get_int() & 63)) <= 31);
+
+ ins_cost(INSN_COST);
+ format %{ "ubfiz $dst, $src, $lshift, $mask" %}
+ ins_encode %{
+ int lshift = $lshift$$constant & 63;
+ intptr_t mask = $mask$$constant;
+ int width = exact_log2_long(mask+1);
+ __ ubfiz(as_Register($dst$$reg),
+ as_Register($src$$reg), lshift, width);
+ %}
+ ins_pipe(ialu_reg_shift);
+%}
+
+
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
+
// If there is a convert I to L block between and AndI and a LShiftL, we can also match ubfiz
instruct ubfizIConvI2L(iRegLNoSp dst, iRegIorL2I src, immI lshift, immI_bitmask mask)
%{
@@ -11456,7 +11687,7 @@
format %{ "ubfiz $dst, $src, $lshift, $mask" %}
ins_encode %{
int lshift = $lshift$$constant & 63;
- long mask = $mask$$constant;
+ intptr_t mask = $mask$$constant;
int width = exact_log2(mask+1);
__ ubfiz(as_Register($dst$$reg),
as_Register($src$$reg), lshift, width);
@@ -11464,8 +11695,43 @@
ins_pipe(ialu_reg_shift);
%}
-// Rotations
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
+// If there is a convert L to I block between and AndL and a LShiftI, we can also match ubfiz
+instruct ubfizLConvL2Ix(iRegINoSp dst, iRegL src, immI lshift, immL_positive_bitmaskI mask)
+%{
+ match(Set dst (LShiftI (ConvL2I (AndL src mask)) lshift));
+ predicate((exact_log2_long(n->in(1)->in(1)->in(2)->get_long() + 1) + (n->in(2)->get_int() & 31)) <= 31);
+
+ ins_cost(INSN_COST);
+ format %{ "ubfiz $dst, $src, $lshift, $mask" %}
+ ins_encode %{
+ int lshift = $lshift$$constant & 31;
+ intptr_t mask = $mask$$constant;
+ int width = exact_log2(mask+1);
+ __ ubfiz(as_Register($dst$$reg),
+ as_Register($src$$reg), lshift, width);
+ %}
+ ins_pipe(ialu_reg_shift);
+%}
+
+// Can skip int2long conversions after AND with small bitmask
+instruct ubfizIConvI2LAndI(iRegLNoSp dst, iRegI src, immI_bitmask msk)
+%{
+ match(Set dst (ConvI2L (AndI src msk)));
+ ins_cost(INSN_COST);
+ format %{ "ubfiz $dst, $src, 0, exact_log2($msk + 1) " %}
+ ins_encode %{
+ __ ubfiz(as_Register($dst$$reg), as_Register($src$$reg), 0, exact_log2($msk$$constant + 1));
+ %}
+ ins_pipe(ialu_reg_shift);
+%}
+
+
+// Rotations
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct extrOrL(iRegLNoSp dst, iRegL src1, iRegL src2, immI lshift, immI rshift, rFlagsReg cr)
%{
match(Set dst (OrL (LShiftL src1 lshift) (URShiftL src2 rshift)));
@@ -11481,6 +11747,9 @@
ins_pipe(ialu_reg_reg_extr);
%}
+
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct extrOrI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI lshift, immI rshift, rFlagsReg cr)
%{
match(Set dst (OrI (LShiftI src1 lshift) (URShiftI src2 rshift)));
@@ -11496,6 +11765,9 @@
ins_pipe(ialu_reg_reg_extr);
%}
+
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct extrAddL(iRegLNoSp dst, iRegL src1, iRegL src2, immI lshift, immI rshift, rFlagsReg cr)
%{
match(Set dst (AddL (LShiftL src1 lshift) (URShiftL src2 rshift)));
@@ -11511,6 +11783,9 @@
ins_pipe(ialu_reg_reg_extr);
%}
+
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct extrAddI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI lshift, immI rshift, rFlagsReg cr)
%{
match(Set dst (AddI (LShiftI src1 lshift) (URShiftI src2 rshift)));
@@ -11527,8 +11802,10 @@
%}
-// rol expander
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
+// rol expander
instruct rolL_rReg(iRegLNoSp dst, iRegL src, iRegI shift, rFlagsReg cr)
%{
effect(DEF dst, USE src, USE shift);
@@ -11543,8 +11820,10 @@
ins_pipe(ialu_reg_reg_vshift);
%}
-// rol expander
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
+// rol expander
instruct rolI_rReg(iRegINoSp dst, iRegI src, iRegI shift, rFlagsReg cr)
%{
effect(DEF dst, USE src, USE shift);
@@ -11559,6 +11838,8 @@
ins_pipe(ialu_reg_reg_vshift);
%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct rolL_rReg_Var_C_64(iRegLNoSp dst, iRegL src, iRegI shift, immI_64 c_64, rFlagsReg cr)
%{
match(Set dst (OrL (LShiftL src shift) (URShiftL src (SubI c_64 shift))));
@@ -11568,6 +11849,8 @@
%}
%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct rolL_rReg_Var_C0(iRegLNoSp dst, iRegL src, iRegI shift, immI0 c0, rFlagsReg cr)
%{
match(Set dst (OrL (LShiftL src shift) (URShiftL src (SubI c0 shift))));
@@ -11577,6 +11860,8 @@
%}
%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct rolI_rReg_Var_C_32(iRegINoSp dst, iRegI src, iRegI shift, immI_32 c_32, rFlagsReg cr)
%{
match(Set dst (OrI (LShiftI src shift) (URShiftI src (SubI c_32 shift))));
@@ -11586,6 +11871,8 @@
%}
%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct rolI_rReg_Var_C0(iRegINoSp dst, iRegI src, iRegI shift, immI0 c0, rFlagsReg cr)
%{
match(Set dst (OrI (LShiftI src shift) (URShiftI src (SubI c0 shift))));
@@ -11595,8 +11882,10 @@
%}
%}
-// ror expander
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
+// ror expander
instruct rorL_rReg(iRegLNoSp dst, iRegL src, iRegI shift, rFlagsReg cr)
%{
effect(DEF dst, USE src, USE shift);
@@ -11610,8 +11899,10 @@
ins_pipe(ialu_reg_reg_vshift);
%}
-// ror expander
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
+// ror expander
instruct rorI_rReg(iRegINoSp dst, iRegI src, iRegI shift, rFlagsReg cr)
%{
effect(DEF dst, USE src, USE shift);
@@ -11625,6 +11916,8 @@
ins_pipe(ialu_reg_reg_vshift);
%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct rorL_rReg_Var_C_64(iRegLNoSp dst, iRegL src, iRegI shift, immI_64 c_64, rFlagsReg cr)
%{
match(Set dst (OrL (URShiftL src shift) (LShiftL src (SubI c_64 shift))));
@@ -11634,6 +11927,8 @@
%}
%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct rorL_rReg_Var_C0(iRegLNoSp dst, iRegL src, iRegI shift, immI0 c0, rFlagsReg cr)
%{
match(Set dst (OrL (URShiftL src shift) (LShiftL src (SubI c0 shift))));
@@ -11643,6 +11938,8 @@
%}
%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct rorI_rReg_Var_C_32(iRegINoSp dst, iRegI src, iRegI shift, immI_32 c_32, rFlagsReg cr)
%{
match(Set dst (OrI (URShiftI src shift) (LShiftI src (SubI c_32 shift))));
@@ -11652,6 +11949,8 @@
%}
%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct rorI_rReg_Var_C0(iRegINoSp dst, iRegI src, iRegI shift, immI0 c0, rFlagsReg cr)
%{
match(Set dst (OrI (URShiftI src shift) (LShiftI src (SubI c0 shift))));
@@ -11661,8 +11960,11 @@
%}
%}
+
// Add/subtract (extended)
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct AddExtI(iRegLNoSp dst, iRegL src1, iRegIorL2I src2, rFlagsReg cr)
%{
match(Set dst (AddL src1 (ConvI2L src2)));
@@ -11674,8 +11976,10 @@
as_Register($src2$$reg), ext::sxtw);
%}
ins_pipe(ialu_reg_reg);
-%};
+%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct SubExtI(iRegLNoSp dst, iRegL src1, iRegIorL2I src2, rFlagsReg cr)
%{
match(Set dst (SubL src1 (ConvI2L src2)));
@@ -11687,9 +11991,10 @@
as_Register($src2$$reg), ext::sxtw);
%}
ins_pipe(ialu_reg_reg);
-%};
-
+%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct AddExtI_sxth(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI_16 lshift, immI_16 rshift, rFlagsReg cr)
%{
match(Set dst (AddI src1 (RShiftI (LShiftI src2 lshift) rshift)));
@@ -11703,6 +12008,8 @@
ins_pipe(ialu_reg_reg);
%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct AddExtI_sxtb(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI_24 lshift, immI_24 rshift, rFlagsReg cr)
%{
match(Set dst (AddI src1 (RShiftI (LShiftI src2 lshift) rshift)));
@@ -11716,6 +12023,8 @@
ins_pipe(ialu_reg_reg);
%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct AddExtI_uxtb(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI_24 lshift, immI_24 rshift, rFlagsReg cr)
%{
match(Set dst (AddI src1 (URShiftI (LShiftI src2 lshift) rshift)));
@@ -11729,6 +12038,8 @@
ins_pipe(ialu_reg_reg);
%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct AddExtL_sxth(iRegLNoSp dst, iRegL src1, iRegL src2, immI_48 lshift, immI_48 rshift, rFlagsReg cr)
%{
match(Set dst (AddL src1 (RShiftL (LShiftL src2 lshift) rshift)));
@@ -11742,6 +12053,8 @@
ins_pipe(ialu_reg_reg);
%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct AddExtL_sxtw(iRegLNoSp dst, iRegL src1, iRegL src2, immI_32 lshift, immI_32 rshift, rFlagsReg cr)
%{
match(Set dst (AddL src1 (RShiftL (LShiftL src2 lshift) rshift)));
@@ -11755,6 +12068,8 @@
ins_pipe(ialu_reg_reg);
%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct AddExtL_sxtb(iRegLNoSp dst, iRegL src1, iRegL src2, immI_56 lshift, immI_56 rshift, rFlagsReg cr)
%{
match(Set dst (AddL src1 (RShiftL (LShiftL src2 lshift) rshift)));
@@ -11768,6 +12083,8 @@
ins_pipe(ialu_reg_reg);
%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct AddExtL_uxtb(iRegLNoSp dst, iRegL src1, iRegL src2, immI_56 lshift, immI_56 rshift, rFlagsReg cr)
%{
match(Set dst (AddL src1 (URShiftL (LShiftL src2 lshift) rshift)));
@@ -11781,7 +12098,8 @@
ins_pipe(ialu_reg_reg);
%}
-
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct AddExtI_uxtb_and(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI_255 mask, rFlagsReg cr)
%{
match(Set dst (AddI src1 (AndI src2 mask)));
@@ -11795,6 +12113,8 @@
ins_pipe(ialu_reg_reg);
%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct AddExtI_uxth_and(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI_65535 mask, rFlagsReg cr)
%{
match(Set dst (AddI src1 (AndI src2 mask)));
@@ -11808,6 +12128,8 @@
ins_pipe(ialu_reg_reg);
%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct AddExtL_uxtb_and(iRegLNoSp dst, iRegL src1, iRegL src2, immL_255 mask, rFlagsReg cr)
%{
match(Set dst (AddL src1 (AndL src2 mask)));
@@ -11821,6 +12143,8 @@
ins_pipe(ialu_reg_reg);
%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct AddExtL_uxth_and(iRegLNoSp dst, iRegL src1, iRegL src2, immL_65535 mask, rFlagsReg cr)
%{
match(Set dst (AddL src1 (AndL src2 mask)));
@@ -11834,6 +12158,8 @@
ins_pipe(ialu_reg_reg);
%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct AddExtL_uxtw_and(iRegLNoSp dst, iRegL src1, iRegL src2, immL_4294967295 mask, rFlagsReg cr)
%{
match(Set dst (AddL src1 (AndL src2 mask)));
@@ -11847,6 +12173,8 @@
ins_pipe(ialu_reg_reg);
%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct SubExtI_uxtb_and(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI_255 mask, rFlagsReg cr)
%{
match(Set dst (SubI src1 (AndI src2 mask)));
@@ -11860,6 +12188,8 @@
ins_pipe(ialu_reg_reg);
%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct SubExtI_uxth_and(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI_65535 mask, rFlagsReg cr)
%{
match(Set dst (SubI src1 (AndI src2 mask)));
@@ -11873,6 +12203,8 @@
ins_pipe(ialu_reg_reg);
%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct SubExtL_uxtb_and(iRegLNoSp dst, iRegL src1, iRegL src2, immL_255 mask, rFlagsReg cr)
%{
match(Set dst (SubL src1 (AndL src2 mask)));
@@ -11886,6 +12218,8 @@
ins_pipe(ialu_reg_reg);
%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct SubExtL_uxth_and(iRegLNoSp dst, iRegL src1, iRegL src2, immL_65535 mask, rFlagsReg cr)
%{
match(Set dst (SubL src1 (AndL src2 mask)));
@@ -11899,6 +12233,8 @@
ins_pipe(ialu_reg_reg);
%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct SubExtL_uxtw_and(iRegLNoSp dst, iRegL src1, iRegL src2, immL_4294967295 mask, rFlagsReg cr)
%{
match(Set dst (SubL src1 (AndL src2 mask)));
@@ -11913,6 +12249,8 @@
%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct AddExtL_sxtb_shift(iRegLNoSp dst, iRegL src1, iRegL src2, immIExt lshift2, immI_56 lshift1, immI_56 rshift1, rFlagsReg cr)
%{
match(Set dst (AddL src1 (LShiftL (RShiftL (LShiftL src2 lshift1) rshift1) lshift2)));
@@ -11926,6 +12264,8 @@
ins_pipe(ialu_reg_reg_shift);
%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct AddExtL_sxth_shift(iRegLNoSp dst, iRegL src1, iRegL src2, immIExt lshift2, immI_48 lshift1, immI_48 rshift1, rFlagsReg cr)
%{
match(Set dst (AddL src1 (LShiftL (RShiftL (LShiftL src2 lshift1) rshift1) lshift2)));
@@ -11939,6 +12279,8 @@
ins_pipe(ialu_reg_reg_shift);
%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct AddExtL_sxtw_shift(iRegLNoSp dst, iRegL src1, iRegL src2, immIExt lshift2, immI_32 lshift1, immI_32 rshift1, rFlagsReg cr)
%{
match(Set dst (AddL src1 (LShiftL (RShiftL (LShiftL src2 lshift1) rshift1) lshift2)));
@@ -11952,6 +12294,8 @@
ins_pipe(ialu_reg_reg_shift);
%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct SubExtL_sxtb_shift(iRegLNoSp dst, iRegL src1, iRegL src2, immIExt lshift2, immI_56 lshift1, immI_56 rshift1, rFlagsReg cr)
%{
match(Set dst (SubL src1 (LShiftL (RShiftL (LShiftL src2 lshift1) rshift1) lshift2)));
@@ -11965,6 +12309,8 @@
ins_pipe(ialu_reg_reg_shift);
%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct SubExtL_sxth_shift(iRegLNoSp dst, iRegL src1, iRegL src2, immIExt lshift2, immI_48 lshift1, immI_48 rshift1, rFlagsReg cr)
%{
match(Set dst (SubL src1 (LShiftL (RShiftL (LShiftL src2 lshift1) rshift1) lshift2)));
@@ -11978,6 +12324,8 @@
ins_pipe(ialu_reg_reg_shift);
%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct SubExtL_sxtw_shift(iRegLNoSp dst, iRegL src1, iRegL src2, immIExt lshift2, immI_32 lshift1, immI_32 rshift1, rFlagsReg cr)
%{
match(Set dst (SubL src1 (LShiftL (RShiftL (LShiftL src2 lshift1) rshift1) lshift2)));
@@ -11991,6 +12339,8 @@
ins_pipe(ialu_reg_reg_shift);
%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct AddExtI_sxtb_shift(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immIExt lshift2, immI_24 lshift1, immI_24 rshift1, rFlagsReg cr)
%{
match(Set dst (AddI src1 (LShiftI (RShiftI (LShiftI src2 lshift1) rshift1) lshift2)));
@@ -12004,6 +12354,8 @@
ins_pipe(ialu_reg_reg_shift);
%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct AddExtI_sxth_shift(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immIExt lshift2, immI_16 lshift1, immI_16 rshift1, rFlagsReg cr)
%{
match(Set dst (AddI src1 (LShiftI (RShiftI (LShiftI src2 lshift1) rshift1) lshift2)));
@@ -12017,6 +12369,8 @@
ins_pipe(ialu_reg_reg_shift);
%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct SubExtI_sxtb_shift(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immIExt lshift2, immI_24 lshift1, immI_24 rshift1, rFlagsReg cr)
%{
match(Set dst (SubI src1 (LShiftI (RShiftI (LShiftI src2 lshift1) rshift1) lshift2)));
@@ -12030,6 +12384,8 @@
ins_pipe(ialu_reg_reg_shift);
%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct SubExtI_sxth_shift(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immIExt lshift2, immI_16 lshift1, immI_16 rshift1, rFlagsReg cr)
%{
match(Set dst (SubI src1 (LShiftI (RShiftI (LShiftI src2 lshift1) rshift1) lshift2)));
@@ -12043,7 +12399,8 @@
ins_pipe(ialu_reg_reg_shift);
%}
-
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct AddExtI_shift(iRegLNoSp dst, iRegL src1, iRegIorL2I src2, immIExt lshift, rFlagsReg cr)
%{
match(Set dst (AddL src1 (LShiftL (ConvI2L src2) lshift)));
@@ -12055,8 +12412,10 @@
as_Register($src2$$reg), ext::sxtw, ($lshift$$constant));
%}
ins_pipe(ialu_reg_reg_shift);
-%};
+%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct SubExtI_shift(iRegLNoSp dst, iRegL src1, iRegIorL2I src2, immIExt lshift, rFlagsReg cr)
%{
match(Set dst (SubL src1 (LShiftL (ConvI2L src2) lshift)));
@@ -12068,9 +12427,10 @@
as_Register($src2$$reg), ext::sxtw, ($lshift$$constant));
%}
ins_pipe(ialu_reg_reg_shift);
-%};
-
+%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct AddExtL_uxtb_and_shift(iRegLNoSp dst, iRegL src1, iRegL src2, immL_255 mask, immIExt lshift, rFlagsReg cr)
%{
match(Set dst (AddL src1 (LShiftL (AndL src2 mask) lshift)));
@@ -12084,6 +12444,8 @@
ins_pipe(ialu_reg_reg_shift);
%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct AddExtL_uxth_and_shift(iRegLNoSp dst, iRegL src1, iRegL src2, immL_65535 mask, immIExt lshift, rFlagsReg cr)
%{
match(Set dst (AddL src1 (LShiftL (AndL src2 mask) lshift)));
@@ -12097,6 +12459,8 @@
ins_pipe(ialu_reg_reg_shift);
%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct AddExtL_uxtw_and_shift(iRegLNoSp dst, iRegL src1, iRegL src2, immL_4294967295 mask, immIExt lshift, rFlagsReg cr)
%{
match(Set dst (AddL src1 (LShiftL (AndL src2 mask) lshift)));
@@ -12110,6 +12474,8 @@
ins_pipe(ialu_reg_reg_shift);
%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct SubExtL_uxtb_and_shift(iRegLNoSp dst, iRegL src1, iRegL src2, immL_255 mask, immIExt lshift, rFlagsReg cr)
%{
match(Set dst (SubL src1 (LShiftL (AndL src2 mask) lshift)));
@@ -12123,6 +12489,8 @@
ins_pipe(ialu_reg_reg_shift);
%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct SubExtL_uxth_and_shift(iRegLNoSp dst, iRegL src1, iRegL src2, immL_65535 mask, immIExt lshift, rFlagsReg cr)
%{
match(Set dst (SubL src1 (LShiftL (AndL src2 mask) lshift)));
@@ -12136,6 +12504,8 @@
ins_pipe(ialu_reg_reg_shift);
%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct SubExtL_uxtw_and_shift(iRegLNoSp dst, iRegL src1, iRegL src2, immL_4294967295 mask, immIExt lshift, rFlagsReg cr)
%{
match(Set dst (SubL src1 (LShiftL (AndL src2 mask) lshift)));
@@ -12149,6 +12519,8 @@
ins_pipe(ialu_reg_reg_shift);
%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct AddExtI_uxtb_and_shift(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI_255 mask, immIExt lshift, rFlagsReg cr)
%{
match(Set dst (AddI src1 (LShiftI (AndI src2 mask) lshift)));
@@ -12162,6 +12534,8 @@
ins_pipe(ialu_reg_reg_shift);
%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct AddExtI_uxth_and_shift(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI_65535 mask, immIExt lshift, rFlagsReg cr)
%{
match(Set dst (AddI src1 (LShiftI (AndI src2 mask) lshift)));
@@ -12175,6 +12549,8 @@
ins_pipe(ialu_reg_reg_shift);
%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct SubExtI_uxtb_and_shift(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI_255 mask, immIExt lshift, rFlagsReg cr)
%{
match(Set dst (SubI src1 (LShiftI (AndI src2 mask) lshift)));
@@ -12188,6 +12564,8 @@
ins_pipe(ialu_reg_reg_shift);
%}
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct SubExtI_uxth_and_shift(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI_65535 mask, immIExt lshift, rFlagsReg cr)
%{
match(Set dst (SubI src1 (LShiftI (AndI src2 mask) lshift)));
@@ -12200,8 +12578,12 @@
%}
ins_pipe(ialu_reg_reg_shift);
%}
+
+
+
// END This section of the file is automatically generated. Do not edit --------------
+
// ============================================================================
// Floating Point Arithmetic Instructions
@@ -12552,6 +12934,40 @@
ins_pipe(fp_uop_d);
%}
+instruct absI_reg(iRegINoSp dst, iRegIorL2I src, rFlagsReg cr)
+%{
+ match(Set dst (AbsI src));
+
+ effect(KILL cr);
+ ins_cost(INSN_COST * 2);
+ format %{ "cmpw $src, zr\n\t"
+ "cnegw $dst, $src, Assembler::LT\t# int abs"
+ %}
+
+ ins_encode %{
+ __ cmpw(as_Register($src$$reg), zr);
+ __ cnegw(as_Register($dst$$reg), as_Register($src$$reg), Assembler::LT);
+ %}
+ ins_pipe(pipe_class_default);
+%}
+
+instruct absL_reg(iRegLNoSp dst, iRegL src, rFlagsReg cr)
+%{
+ match(Set dst (AbsL src));
+
+ effect(KILL cr);
+ ins_cost(INSN_COST * 2);
+ format %{ "cmp $src, zr\n\t"
+ "cneg $dst, $src, Assembler::LT\t# long abs"
+ %}
+
+ ins_encode %{
+ __ cmp(as_Register($src$$reg), zr);
+ __ cneg(as_Register($dst$$reg), as_Register($src$$reg), Assembler::LT);
+ %}
+ ins_pipe(pipe_class_default);
+%}
+
instruct absF_reg(vRegF dst, vRegF src) %{
match(Set dst (AbsF src));
@@ -12592,7 +13008,7 @@
%}
instruct sqrtF_reg(vRegF dst, vRegF src) %{
- match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
+ match(Set dst (SqrtF src));
ins_cost(INSN_COST * 50);
format %{ "fsqrts $dst, $src" %}
@@ -12604,6 +13020,77 @@
ins_pipe(fp_div_d);
%}
+instruct copySignD_reg(vRegD dst, vRegD src1, vRegD src2, vRegD zero) %{
+ match(Set dst (CopySignD src1 (Binary src2 zero)));
+ effect(TEMP_DEF dst, USE src1, USE src2, USE zero);
+ format %{ "CopySignD $dst $src1 $src2" %}
+ ins_encode %{
+ FloatRegister dst = as_FloatRegister($dst$$reg),
+ src1 = as_FloatRegister($src1$$reg),
+ src2 = as_FloatRegister($src2$$reg),
+ zero = as_FloatRegister($zero$$reg);
+ __ fnegd(dst, zero);
+ __ bsl(dst, __ T8B, src2, src1);
+ %}
+ ins_pipe(fp_uop_d);
+%}
+
+instruct copySignF_reg(vRegF dst, vRegF src1, vRegF src2) %{
+ match(Set dst (CopySignF src1 src2));
+ effect(TEMP_DEF dst, USE src1, USE src2);
+ format %{ "CopySignF $dst $src1 $src2" %}
+ ins_encode %{
+ FloatRegister dst = as_FloatRegister($dst$$reg),
+ src1 = as_FloatRegister($src1$$reg),
+ src2 = as_FloatRegister($src2$$reg);
+ __ movi(dst, __ T2S, 0x80, 24);
+ __ bsl(dst, __ T8B, src2, src1);
+ %}
+ ins_pipe(fp_uop_d);
+%}
+
+instruct signumD_reg(vRegD dst, vRegD src, vRegD zero, vRegD one) %{
+ match(Set dst (SignumD src (Binary zero one)));
+ effect(TEMP_DEF dst, USE src, USE zero, USE one);
+ format %{ "signumD $dst, $src" %}
+ ins_encode %{
+ FloatRegister src = as_FloatRegister($src$$reg),
+ dst = as_FloatRegister($dst$$reg),
+ zero = as_FloatRegister($zero$$reg),
+ one = as_FloatRegister($one$$reg);
+ __ facgtd(dst, src, zero); // dst=0 for +-0.0 and NaN. 0xFFF..F otherwise
+ __ ushrd(dst, dst, 1); // dst=0 for +-0.0 and NaN. 0x7FF..F otherwise
+ // Bit selection instruction gets bit from "one" for each enabled bit in
+ // "dst", otherwise gets a bit from "src". For "src" that contains +-0.0 or
+ // NaN the whole "src" will be copied because "dst" is zero. For all other
+ // "src" values dst is 0x7FF..F, which means only the sign bit is copied
+ // from "src", and all other bits are copied from 1.0.
+ __ bsl(dst, __ T8B, one, src);
+ %}
+ ins_pipe(fp_uop_d);
+%}
+
+instruct signumF_reg(vRegF dst, vRegF src, vRegF zero, vRegF one) %{
+ match(Set dst (SignumF src (Binary zero one)));
+ effect(TEMP_DEF dst, USE src, USE zero, USE one);
+ format %{ "signumF $dst, $src" %}
+ ins_encode %{
+ FloatRegister src = as_FloatRegister($src$$reg),
+ dst = as_FloatRegister($dst$$reg),
+ zero = as_FloatRegister($zero$$reg),
+ one = as_FloatRegister($one$$reg);
+ __ facgts(dst, src, zero); // dst=0 for +-0.0 and NaN. 0xFFF..F otherwise
+ __ ushr(dst, __ T2S, dst, 1); // dst=0 for +-0.0 and NaN. 0x7FF..F otherwise
+ // Bit selection instruction gets bit from "one" for each enabled bit in
+ // "dst", otherwise gets a bit from "src". For "src" that contains +-0.0 or
+ // NaN the whole "src" will be copied because "dst" is zero. For all other
+ // "src" values dst is 0x7FF..F, which means only the sign bit is copied
+ // from "src", and all other bits are copied from 1.0.
+ __ bsl(dst, __ T8B, one, src);
+ %}
+ ins_pipe(fp_uop_d);
+%}
+
// ============================================================================
// Logical Instructions
@@ -12636,7 +13123,7 @@
ins_encode %{
__ andw(as_Register($dst$$reg),
as_Register($src1$$reg),
- (unsigned long)($src2$$constant));
+ (uint64_t)($src2$$constant));
%}
ins_pipe(ialu_reg_imm);
@@ -12668,7 +13155,7 @@
ins_encode %{
__ orrw(as_Register($dst$$reg),
as_Register($src1$$reg),
- (unsigned long)($src2$$constant));
+ (uint64_t)($src2$$constant));
%}
ins_pipe(ialu_reg_imm);
@@ -12700,7 +13187,7 @@
ins_encode %{
__ eorw(as_Register($dst$$reg),
as_Register($src1$$reg),
- (unsigned long)($src2$$constant));
+ (uint64_t)($src2$$constant));
%}
ins_pipe(ialu_reg_imm);
@@ -12733,7 +13220,7 @@
ins_encode %{
__ andr(as_Register($dst$$reg),
as_Register($src1$$reg),
- (unsigned long)($src2$$constant));
+ (uint64_t)($src2$$constant));
%}
ins_pipe(ialu_reg_imm);
@@ -12765,7 +13252,7 @@
ins_encode %{
__ orr(as_Register($dst$$reg),
as_Register($src1$$reg),
- (unsigned long)($src2$$constant));
+ (uint64_t)($src2$$constant));
%}
ins_pipe(ialu_reg_imm);
@@ -12797,7 +13284,7 @@
ins_encode %{
__ eor(as_Register($dst$$reg),
as_Register($src1$$reg),
- (unsigned long)($src2$$constant));
+ (uint64_t)($src2$$constant));
%}
ins_pipe(ialu_reg_imm);
@@ -13238,7 +13725,11 @@
format %{ "ClearArray $cnt, $base" %}
ins_encode %{
- __ zero_words($base$$Register, $cnt$$Register);
+ address tpc = __ zero_words($base$$Register, $cnt$$Register);
+ if (tpc == NULL) {
+ ciEnv::current()->record_failure("CodeCache is full");
+ return;
+ }
%}
ins_pipe(pipe_class_memory);
@@ -13246,8 +13737,8 @@
instruct clearArray_imm_reg(immL cnt, iRegP_R10 base, Universe dummy, rFlagsReg cr)
%{
- predicate((u_int64_t)n->in(2)->get_long()
- < (u_int64_t)(BlockZeroingLowLimit >> LogBytesPerWord));
+ predicate((uint64_t)n->in(2)->get_long()
+ < (uint64_t)(BlockZeroingLowLimit >> LogBytesPerWord));
match(Set dummy (ClearArray cnt base));
effect(USE_KILL base);
@@ -13255,7 +13746,7 @@
format %{ "ClearArray $cnt, $base" %}
ins_encode %{
- __ zero_words($base$$Register, (u_int64_t)$cnt$$constant);
+ __ zero_words($base$$Register, (uint64_t)$cnt$$constant);
%}
ins_pipe(pipe_class_memory);
@@ -13981,55 +14472,63 @@
// ============================================================================
// Max and Min
-instruct minI_rReg(iRegINoSp dst, iRegI src1, iRegI src2, rFlagsReg cr)
+instruct cmovI_reg_reg_lt(iRegINoSp dst, iRegI src1, iRegI src2, rFlagsReg cr)
%{
- match(Set dst (MinI src1 src2));
+ effect( DEF dst, USE src1, USE src2, USE cr );
- effect(DEF dst, USE src1, USE src2, KILL cr);
- size(8);
-
- ins_cost(INSN_COST * 3);
- format %{
- "cmpw $src1 $src2\t signed int\n\t"
- "cselw $dst, $src1, $src2 lt\t"
- %}
+ ins_cost(INSN_COST * 2);
+ format %{ "cselw $dst, $src1, $src2 lt\t" %}
ins_encode %{
- __ cmpw(as_Register($src1$$reg),
- as_Register($src2$$reg));
__ cselw(as_Register($dst$$reg),
as_Register($src1$$reg),
as_Register($src2$$reg),
Assembler::LT);
%}
- ins_pipe(ialu_reg_reg);
+ ins_pipe(icond_reg_reg);
%}
-// FROM HERE
-instruct maxI_rReg(iRegINoSp dst, iRegI src1, iRegI src2, rFlagsReg cr)
+instruct minI_rReg(iRegINoSp dst, iRegI src1, iRegI src2)
%{
- match(Set dst (MaxI src1 src2));
-
- effect(DEF dst, USE src1, USE src2, KILL cr);
- size(8);
-
+ match(Set dst (MinI src1 src2));
ins_cost(INSN_COST * 3);
- format %{
- "cmpw $src1 $src2\t signed int\n\t"
- "cselw $dst, $src1, $src2 gt\t"
+
+ expand %{
+ rFlagsReg cr;
+ compI_reg_reg(cr, src1, src2);
+ cmovI_reg_reg_lt(dst, src1, src2, cr);
%}
+%}
+// FROM HERE
+
+instruct cmovI_reg_reg_gt(iRegINoSp dst, iRegI src1, iRegI src2, rFlagsReg cr)
+%{
+ effect( DEF dst, USE src1, USE src2, USE cr );
+
+ ins_cost(INSN_COST * 2);
+ format %{ "cselw $dst, $src1, $src2 gt\t" %}
+
ins_encode %{
- __ cmpw(as_Register($src1$$reg),
- as_Register($src2$$reg));
__ cselw(as_Register($dst$$reg),
as_Register($src1$$reg),
as_Register($src2$$reg),
Assembler::GT);
%}
- ins_pipe(ialu_reg_reg);
+ ins_pipe(icond_reg_reg);
+%}
+
+instruct maxI_rReg(iRegINoSp dst, iRegI src1, iRegI src2)
+%{
+ match(Set dst (MaxI src1 src2));
+ ins_cost(INSN_COST * 3);
+ expand %{
+ rFlagsReg cr;
+ compI_reg_reg(cr, src1, src2);
+ cmovI_reg_reg_gt(dst, src1, src2, cr);
+ %}
%}
// ============================================================================
@@ -14974,10 +15473,14 @@
format %{ "Array Equals $ary1,ary2 -> $result // KILL $tmp" %}
ins_encode %{
- __ arrays_equals($ary1$$Register, $ary2$$Register,
- $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
- $result$$Register, $tmp$$Register, 1);
- %}
+ address tpc = __ arrays_equals($ary1$$Register, $ary2$$Register,
+ $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
+ $result$$Register, $tmp$$Register, 1);
+ if (tpc == NULL) {
+ ciEnv::current()->record_failure("CodeCache is full");
+ return;
+ }
+ %}
ins_pipe(pipe_class_memory);
%}
@@ -14991,9 +15494,13 @@
format %{ "Array Equals $ary1,ary2 -> $result // KILL $tmp" %}
ins_encode %{
- __ arrays_equals($ary1$$Register, $ary2$$Register,
- $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
- $result$$Register, $tmp$$Register, 2);
+ address tpc = __ arrays_equals($ary1$$Register, $ary2$$Register,
+ $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
+ $result$$Register, $tmp$$Register, 2);
+ if (tpc == NULL) {
+ ciEnv::current()->record_failure("CodeCache is full");
+ return;
+ }
%}
ins_pipe(pipe_class_memory);
%}
@@ -15004,7 +15511,11 @@
effect(USE_KILL ary1, USE_KILL len, KILL cr);
format %{ "has negatives byte[] $ary1,$len -> $result" %}
ins_encode %{
- __ has_negatives($ary1$$Register, $len$$Register, $result$$Register);
+ address tpc = __ has_negatives($ary1$$Register, $len$$Register, $result$$Register);
+ if (tpc == NULL) {
+ ciEnv::current()->record_failure("CodeCache is full");
+ return;
+ }
%}
ins_pipe( pipe_slow );
%}
@@ -15037,8 +15548,13 @@
format %{ "String Inflate $src,$dst // KILL $tmp1, $tmp2" %}
ins_encode %{
- __ byte_array_inflate($src$$Register, $dst$$Register, $len$$Register,
- $tmp1$$FloatRegister, $tmp2$$FloatRegister, $tmp3$$FloatRegister, $tmp4$$Register);
+ address tpc = __ byte_array_inflate($src$$Register, $dst$$Register, $len$$Register,
+ $tmp1$$FloatRegister, $tmp2$$FloatRegister,
+ $tmp3$$FloatRegister, $tmp4$$Register);
+ if (tpc == NULL) {
+ ciEnv::current()->record_failure("CodeCache is full");
+ return;
+ }
%}
ins_pipe(pipe_class_memory);
%}
@@ -15589,6 +16105,98 @@
ins_pipe(pipe_class_default);
%}
+instruct reduce_max2F(vRegF dst, vRegF src1, vecD src2, vecD tmp) %{
+ predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_FLOAT);
+ match(Set dst (MaxReductionV src1 src2));
+ ins_cost(INSN_COST);
+ effect(TEMP_DEF dst, TEMP tmp);
+ format %{ "fmaxs $dst, $src1, $src2\n\t"
+ "ins $tmp, S, $src2, 0, 1\n\t"
+ "fmaxs $dst, $dst, $tmp\t# max reduction2F" %}
+ ins_encode %{
+ __ fmaxs(as_FloatRegister($dst$$reg), as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
+ __ ins(as_FloatRegister($tmp$$reg), __ S, as_FloatRegister($src2$$reg), 0, 1);
+ __ fmaxs(as_FloatRegister($dst$$reg), as_FloatRegister($dst$$reg), as_FloatRegister($tmp$$reg));
+ %}
+ ins_pipe(pipe_class_default);
+%}
+
+instruct reduce_max4F(vRegF dst, vRegF src1, vecX src2) %{
+ predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_FLOAT);
+ match(Set dst (MaxReductionV src1 src2));
+ ins_cost(INSN_COST);
+ effect(TEMP_DEF dst);
+ format %{ "fmaxv $dst, T4S, $src2\n\t"
+ "fmaxs $dst, $dst, $src1\t# max reduction4F" %}
+ ins_encode %{
+ __ fmaxv(as_FloatRegister($dst$$reg), __ T4S, as_FloatRegister($src2$$reg));
+ __ fmaxs(as_FloatRegister($dst$$reg), as_FloatRegister($dst$$reg), as_FloatRegister($src1$$reg));
+ %}
+ ins_pipe(pipe_class_default);
+%}
+
+instruct reduce_max2D(vRegD dst, vRegD src1, vecX src2, vecX tmp) %{
+ predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_DOUBLE);
+ match(Set dst (MaxReductionV src1 src2));
+ ins_cost(INSN_COST);
+ effect(TEMP_DEF dst, TEMP tmp);
+ format %{ "fmaxd $dst, $src1, $src2\n\t"
+ "ins $tmp, D, $src2, 0, 1\n\t"
+ "fmaxd $dst, $dst, $tmp\t# max reduction2D" %}
+ ins_encode %{
+ __ fmaxd(as_FloatRegister($dst$$reg), as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
+ __ ins(as_FloatRegister($tmp$$reg), __ D, as_FloatRegister($src2$$reg), 0, 1);
+ __ fmaxd(as_FloatRegister($dst$$reg), as_FloatRegister($dst$$reg), as_FloatRegister($tmp$$reg));
+ %}
+ ins_pipe(pipe_class_default);
+%}
+
+instruct reduce_min2F(vRegF dst, vRegF src1, vecD src2, vecD tmp) %{
+ predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_FLOAT);
+ match(Set dst (MinReductionV src1 src2));
+ ins_cost(INSN_COST);
+ effect(TEMP_DEF dst, TEMP tmp);
+ format %{ "fmins $dst, $src1, $src2\n\t"
+ "ins $tmp, S, $src2, 0, 1\n\t"
+ "fmins $dst, $dst, $tmp\t# min reduction2F" %}
+ ins_encode %{
+ __ fmins(as_FloatRegister($dst$$reg), as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
+ __ ins(as_FloatRegister($tmp$$reg), __ S, as_FloatRegister($src2$$reg), 0, 1);
+ __ fmins(as_FloatRegister($dst$$reg), as_FloatRegister($dst$$reg), as_FloatRegister($tmp$$reg));
+ %}
+ ins_pipe(pipe_class_default);
+%}
+
+instruct reduce_min4F(vRegF dst, vRegF src1, vecX src2) %{
+ predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_FLOAT);
+ match(Set dst (MinReductionV src1 src2));
+ ins_cost(INSN_COST);
+ effect(TEMP_DEF dst);
+ format %{ "fminv $dst, T4S, $src2\n\t"
+ "fmins $dst, $dst, $src1\t# min reduction4F" %}
+ ins_encode %{
+ __ fminv(as_FloatRegister($dst$$reg), __ T4S, as_FloatRegister($src2$$reg));
+ __ fmins(as_FloatRegister($dst$$reg), as_FloatRegister($dst$$reg), as_FloatRegister($src1$$reg));
+ %}
+ ins_pipe(pipe_class_default);
+%}
+
+instruct reduce_min2D(vRegD dst, vRegD src1, vecX src2, vecX tmp) %{
+ predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_DOUBLE);
+ match(Set dst (MinReductionV src1 src2));
+ ins_cost(INSN_COST);
+ effect(TEMP_DEF dst, TEMP tmp);
+ format %{ "fmind $dst, $src1, $src2\n\t"
+ "ins $tmp, D, $src2, 0, 1\n\t"
+ "fmind $dst, $dst, $tmp\t# min reduction2D" %}
+ ins_encode %{
+ __ fmind(as_FloatRegister($dst$$reg), as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
+ __ ins(as_FloatRegister($tmp$$reg), __ D, as_FloatRegister($src2$$reg), 0, 1);
+ __ fmind(as_FloatRegister($dst$$reg), as_FloatRegister($dst$$reg), as_FloatRegister($tmp$$reg));
+ %}
+ ins_pipe(pipe_class_default);
+%}
+
// ====================VECTOR ARITHMETIC=======================================
// --------------------------------- ADD --------------------------------------
@@ -15880,6 +16488,35 @@
// --------------------------------- MUL --------------------------------------
+instruct vmul8B(vecD dst, vecD src1, vecD src2)
+%{
+ predicate(n->as_Vector()->length() == 4 ||
+ n->as_Vector()->length() == 8);
+ match(Set dst (MulVB src1 src2));
+ ins_cost(INSN_COST);
+ format %{ "mulv $dst,$src1,$src2\t# vector (8B)" %}
+ ins_encode %{
+ __ mulv(as_FloatRegister($dst$$reg), __ T8B,
+ as_FloatRegister($src1$$reg),
+ as_FloatRegister($src2$$reg));
+ %}
+ ins_pipe(vmul64);
+%}
+
+instruct vmul16B(vecX dst, vecX src1, vecX src2)
+%{
+ predicate(n->as_Vector()->length() == 16);
+ match(Set dst (MulVB src1 src2));
+ ins_cost(INSN_COST);
+ format %{ "mulv $dst,$src1,$src2\t# vector (16B)" %}
+ ins_encode %{
+ __ mulv(as_FloatRegister($dst$$reg), __ T16B,
+ as_FloatRegister($src1$$reg),
+ as_FloatRegister($src2$$reg));
+ %}
+ ins_pipe(vmul128);
+%}
+
instruct vmul4S(vecD dst, vecD src1, vecD src2)
%{
predicate(n->as_Vector()->length() == 2 ||
@@ -16230,6 +16867,28 @@
// --------------------------------- SQRT -------------------------------------
+instruct vsqrt2F(vecD dst, vecD src)
+%{
+ predicate(n->as_Vector()->length() == 2);
+ match(Set dst (SqrtVF src));
+ format %{ "fsqrt $dst, $src\t# vector (2F)" %}
+ ins_encode %{
+ __ fsqrt(as_FloatRegister($dst$$reg), __ T2S, as_FloatRegister($src$$reg));
+ %}
+ ins_pipe(vunop_fp64);
+%}
+
+instruct vsqrt4F(vecX dst, vecX src)
+%{
+ predicate(n->as_Vector()->length() == 4);
+ match(Set dst (SqrtVF src));
+ format %{ "fsqrt $dst, $src\t# vector (4F)" %}
+ ins_encode %{
+ __ fsqrt(as_FloatRegister($dst$$reg), __ T4S, as_FloatRegister($src$$reg));
+ %}
+ ins_pipe(vsqrt_fp128);
+%}
+
instruct vsqrt2D(vecX dst, vecX src)
%{
predicate(n->as_Vector()->length() == 2);
@@ -16244,6 +16903,91 @@
// --------------------------------- ABS --------------------------------------
+instruct vabs8B(vecD dst, vecD src)
+%{
+ predicate(n->as_Vector()->length() == 4 ||
+ n->as_Vector()->length() == 8);
+ match(Set dst (AbsVB src));
+ ins_cost(INSN_COST);
+ format %{ "abs $dst, $src\t# vector (8B)" %}
+ ins_encode %{
+ __ absr(as_FloatRegister($dst$$reg), __ T8B, as_FloatRegister($src$$reg));
+ %}
+ ins_pipe(vlogical64);
+%}
+
+instruct vabs16B(vecX dst, vecX src)
+%{
+ predicate(n->as_Vector()->length() == 16);
+ match(Set dst (AbsVB src));
+ ins_cost(INSN_COST);
+ format %{ "abs $dst, $src\t# vector (16B)" %}
+ ins_encode %{
+ __ absr(as_FloatRegister($dst$$reg), __ T16B, as_FloatRegister($src$$reg));
+ %}
+ ins_pipe(vlogical128);
+%}
+
+instruct vabs4S(vecD dst, vecD src)
+%{
+ predicate(n->as_Vector()->length() == 4);
+ match(Set dst (AbsVS src));
+ ins_cost(INSN_COST);
+ format %{ "abs $dst, $src\t# vector (4H)" %}
+ ins_encode %{
+ __ absr(as_FloatRegister($dst$$reg), __ T4H, as_FloatRegister($src$$reg));
+ %}
+ ins_pipe(vlogical64);
+%}
+
+instruct vabs8S(vecX dst, vecX src)
+%{
+ predicate(n->as_Vector()->length() == 8);
+ match(Set dst (AbsVS src));
+ ins_cost(INSN_COST);
+ format %{ "abs $dst, $src\t# vector (8H)" %}
+ ins_encode %{
+ __ absr(as_FloatRegister($dst$$reg), __ T8H, as_FloatRegister($src$$reg));
+ %}
+ ins_pipe(vlogical128);
+%}
+
+instruct vabs2I(vecD dst, vecD src)
+%{
+ predicate(n->as_Vector()->length() == 2);
+ match(Set dst (AbsVI src));
+ ins_cost(INSN_COST);
+ format %{ "abs $dst, $src\t# vector (2S)" %}
+ ins_encode %{
+ __ absr(as_FloatRegister($dst$$reg), __ T2S, as_FloatRegister($src$$reg));
+ %}
+ ins_pipe(vlogical64);
+%}
+
+instruct vabs4I(vecX dst, vecX src)
+%{
+ predicate(n->as_Vector()->length() == 4);
+ match(Set dst (AbsVI src));
+ ins_cost(INSN_COST);
+ format %{ "abs $dst, $src\t# vector (4S)" %}
+ ins_encode %{
+ __ absr(as_FloatRegister($dst$$reg), __ T4S, as_FloatRegister($src$$reg));
+ %}
+ ins_pipe(vlogical128);
+%}
+
+instruct vabs2L(vecX dst, vecX src)
+%{
+ predicate(n->as_Vector()->length() == 2);
+ match(Set dst (AbsVL src));
+ ins_cost(INSN_COST);
+ format %{ "abs $dst, $src\t# vector (2D)" %}
+ ins_encode %{
+ __ absr(as_FloatRegister($dst$$reg), __ T2D, as_FloatRegister($src$$reg));
+ %}
+ ins_pipe(vlogical128);
+%}
+
instruct vabs2F(vecD dst, vecD src)
%{
predicate(n->as_Vector()->length() == 2);
@@ -17127,6 +17871,128 @@
ins_pipe(vshift128_imm);
%}
+instruct vmax2F(vecD dst, vecD src1, vecD src2)
+%{
+ predicate(n->as_Vector()->length() == 2 && n->bottom_type()->is_vect()->element_basic_type() == T_FLOAT);
+ match(Set dst (MaxV src1 src2));
+ ins_cost(INSN_COST);
+ format %{ "fmax $dst,$src1,$src2\t# vector (2F)" %}
+ ins_encode %{
+ __ fmax(as_FloatRegister($dst$$reg), __ T2S,
+ as_FloatRegister($src1$$reg),
+ as_FloatRegister($src2$$reg));
+ %}
+ ins_pipe(vdop_fp64);
+%}
+
+instruct vmax4F(vecX dst, vecX src1, vecX src2)
+%{
+ predicate(n->as_Vector()->length() == 4 && n->bottom_type()->is_vect()->element_basic_type() == T_FLOAT);
+ match(Set dst (MaxV src1 src2));
+ ins_cost(INSN_COST);
+ format %{ "fmax $dst,$src1,$src2\t# vector (4S)" %}
+ ins_encode %{
+ __ fmax(as_FloatRegister($dst$$reg), __ T4S,
+ as_FloatRegister($src1$$reg),
+ as_FloatRegister($src2$$reg));
+ %}
+ ins_pipe(vdop_fp128);
+%}
+
+instruct vmax2D(vecX dst, vecX src1, vecX src2)
+%{
+ predicate(n->as_Vector()->length() == 2 && n->bottom_type()->is_vect()->element_basic_type() == T_DOUBLE);
+ match(Set dst (MaxV src1 src2));
+ ins_cost(INSN_COST);
+ format %{ "fmax $dst,$src1,$src2\t# vector (2D)" %}
+ ins_encode %{
+ __ fmax(as_FloatRegister($dst$$reg), __ T2D,
+ as_FloatRegister($src1$$reg),
+ as_FloatRegister($src2$$reg));
+ %}
+ ins_pipe(vdop_fp128);
+%}
+
+instruct vmin2F(vecD dst, vecD src1, vecD src2)
+%{
+ predicate(n->as_Vector()->length() == 2 && n->bottom_type()->is_vect()->element_basic_type() == T_FLOAT);
+ match(Set dst (MinV src1 src2));
+ ins_cost(INSN_COST);
+ format %{ "fmin $dst,$src1,$src2\t# vector (2F)" %}
+ ins_encode %{
+ __ fmin(as_FloatRegister($dst$$reg), __ T2S,
+ as_FloatRegister($src1$$reg),
+ as_FloatRegister($src2$$reg));
+ %}
+ ins_pipe(vdop_fp64);
+%}
+
+instruct vmin4F(vecX dst, vecX src1, vecX src2)
+%{
+ predicate(n->as_Vector()->length() == 4 && n->bottom_type()->is_vect()->element_basic_type() == T_FLOAT);
+ match(Set dst (MinV src1 src2));
+ ins_cost(INSN_COST);
+ format %{ "fmin $dst,$src1,$src2\t# vector (4S)" %}
+ ins_encode %{
+ __ fmin(as_FloatRegister($dst$$reg), __ T4S,
+ as_FloatRegister($src1$$reg),
+ as_FloatRegister($src2$$reg));
+ %}
+ ins_pipe(vdop_fp128);
+%}
+
+instruct vmin2D(vecX dst, vecX src1, vecX src2)
+%{
+ predicate(n->as_Vector()->length() == 2 && n->bottom_type()->is_vect()->element_basic_type() == T_DOUBLE);
+ match(Set dst (MinV src1 src2));
+ ins_cost(INSN_COST);
+ format %{ "fmin $dst,$src1,$src2\t# vector (2D)" %}
+ ins_encode %{
+ __ fmin(as_FloatRegister($dst$$reg), __ T2D,
+ as_FloatRegister($src1$$reg),
+ as_FloatRegister($src2$$reg));
+ %}
+ ins_pipe(vdop_fp128);
+%}
+
+instruct vpopcount4I(vecX dst, vecX src) %{
+ predicate(UsePopCountInstruction && n->as_Vector()->length() == 4);
+ match(Set dst (PopCountVI src));
+ format %{
+ "cnt $dst, $src\t# vector (16B)\n\t"
+ "uaddlp $dst, $dst\t# vector (16B)\n\t"
+ "uaddlp $dst, $dst\t# vector (8H)"
+ %}
+ ins_encode %{
+ __ cnt(as_FloatRegister($dst$$reg), __ T16B,
+ as_FloatRegister($src$$reg));
+ __ uaddlp(as_FloatRegister($dst$$reg), __ T16B,
+ as_FloatRegister($dst$$reg));
+ __ uaddlp(as_FloatRegister($dst$$reg), __ T8H,
+ as_FloatRegister($dst$$reg));
+ %}
+ ins_pipe(pipe_class_default);
+%}
+
+instruct vpopcount2I(vecD dst, vecD src) %{
+ predicate(UsePopCountInstruction && n->as_Vector()->length() == 2);
+ match(Set dst (PopCountVI src));
+ format %{
+ "cnt $dst, $src\t# vector (8B)\n\t"
+ "uaddlp $dst, $dst\t# vector (8B)\n\t"
+ "uaddlp $dst, $dst\t# vector (4H)"
+ %}
+ ins_encode %{
+ __ cnt(as_FloatRegister($dst$$reg), __ T8B,
+ as_FloatRegister($src$$reg));
+ __ uaddlp(as_FloatRegister($dst$$reg), __ T8B,
+ as_FloatRegister($dst$$reg));
+ __ uaddlp(as_FloatRegister($dst$$reg), __ T4H,
+ as_FloatRegister($dst$$reg));
+ %}
+ ins_pipe(pipe_class_default);
+%}
+
//----------PEEPHOLE RULES-----------------------------------------------------
// These must follow all instruction definitions as they use the names
// defined in the instructions definitions.
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/aarch64_ad.m4 openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/aarch64_ad.m4
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/aarch64_ad.m4 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/aarch64_ad.m4 2022-01-13 21:56:25.000000000 +0000
@@ -1,4 +1,4 @@
-dnl Copyright (c) 2014, Red Hat Inc. All rights reserved.
+dnl Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
dnl DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
dnl
dnl This code is free software; you can redistribute it and/or modify it
@@ -23,12 +23,12 @@
dnl Process this file with m4 aarch64_ad.m4 to generate the arithmetic
dnl and shift patterns patterns used in aarch64.ad.
dnl
-// BEGIN This section of the file is automatically generated. Do not edit --------------
dnl
define(`ORL2I', `ifelse($1,I,orL2I)')
dnl
define(`BASE_SHIFT_INSN',
-`
+`// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct $2$1_reg_$4_reg(iReg$1NoSp dst,
iReg$1`'ORL2I($1) src1, iReg$1`'ORL2I($1) src2,
immI src3, rFlagsReg cr) %{
@@ -46,9 +46,11 @@
%}
ins_pipe(ialu_reg_reg_shift);
-%}')dnl
+%}
+')dnl
define(`BASE_INVERTED_INSN',
-`
+`// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct $2$1_reg_not_reg(iReg$1NoSp dst,
iReg$1`'ORL2I($1) src1, iReg$1`'ORL2I($1) src2, imm$1_M1 m1,
rFlagsReg cr) %{
@@ -68,9 +70,11 @@
%}
ins_pipe(ialu_reg_reg);
-%}')dnl
+%}
+')dnl
define(`INVERTED_SHIFT_INSN',
-`
+`// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct $2$1_reg_$4_not_reg(iReg$1NoSp dst,
iReg$1`'ORL2I($1) src1, iReg$1`'ORL2I($1) src2,
immI src3, imm$1_M1 src4, rFlagsReg cr) %{
@@ -91,9 +95,12 @@
%}
ins_pipe(ialu_reg_reg_shift);
-%}')dnl
+%}
+')dnl
define(`NOT_INSN',
-`instruct reg$1_not_reg(iReg$1NoSp dst,
+`// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
+instruct reg$1_not_reg(iReg$1NoSp dst,
iReg$1`'ORL2I($1) src1, imm$1_M1 m1,
rFlagsReg cr) %{
match(Set dst (Xor$1 src1 m1));
@@ -108,7 +115,8 @@
%}
ins_pipe(ialu_reg);
-%}')dnl
+%}
+')dnl
dnl
define(`BOTH_SHIFT_INSNS',
`BASE_SHIFT_INSN(I, $1, ifelse($2,andr,andw,$2w), $3, $4)
@@ -120,7 +128,7 @@
dnl
define(`BOTH_INVERTED_SHIFT_INSNS',
`INVERTED_SHIFT_INSN(I, $1, $2w, $3, $4, ~0, int)
-INVERTED_SHIFT_INSN(L, $1, $2, $3, $4, ~0l, long)')dnl
+INVERTED_SHIFT_INSN(L, $1, $2, $3, $4, ~0l, jlong)')dnl
dnl
define(`ALL_SHIFT_KINDS',
`BOTH_SHIFT_INSNS($1, $2, URShift, LSR)
@@ -147,8 +155,10 @@
ALL_SHIFT_KINDS(Sub, sub)
dnl
dnl EXTEND mode, rshift_op, src, lshift_count, rshift_count
-define(`EXTEND', `($2$1 (LShift$1 $3 $4) $5)')
-define(`BFM_INSN',`
+define(`EXTEND', `($2$1 (LShift$1 $3 $4) $5)') dnl
+define(`BFM_INSN',`// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
+
// Shift Left followed by Shift Right.
// This idiom is used by the compiler for the i2b bytecode etc.
instruct $4$1(iReg$1NoSp dst, iReg$1`'ORL2I($1) src, immI lshift_count, immI rshift_count)
@@ -167,7 +177,8 @@
%}
ins_pipe(ialu_reg_shift);
-%}')
+%}
+')
BFM_INSN(L, 63, RShift, sbfm)
BFM_INSN(I, 31, RShift, sbfmw)
BFM_INSN(L, 63, URShift, ubfm)
@@ -175,7 +186,9 @@
dnl
// Bitfield extract with shift & mask
define(`BFX_INSN',
-`instruct $3$1(iReg$1NoSp dst, iReg$1`'ORL2I($1) src, immI rshift, imm$1_bitmask mask)
+`// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
+instruct $3$1(iReg$1NoSp dst, iReg$1`'ORL2I($1) src, immI rshift, imm$1_bitmask mask)
%{
match(Set dst (And$1 ($2$1 src rshift) mask));
// Make sure we are not going to exceed what $3 can do.
@@ -185,16 +198,20 @@
format %{ "$3 $dst, $src, $rshift, $mask" %}
ins_encode %{
int rshift = $rshift$$constant & $4;
- long mask = $mask$$constant;
+ intptr_t mask = $mask$$constant;
int width = exact_log2$6(mask+1);
__ $3(as_Register($dst$$reg),
as_Register($src$$reg), rshift, width);
%}
ins_pipe(ialu_reg_shift);
-%}')
+%}
+')
BFX_INSN(I, URShift, ubfxw, 31, int)
BFX_INSN(L, URShift, ubfx, 63, long, _long)
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
+
// We can use ubfx when extending an And with a mask when we know mask
// is positive. We know that because immI_bitmask guarantees it.
instruct ubfxIConvI2L(iRegLNoSp dst, iRegIorL2I src, immI rshift, immI_bitmask mask)
@@ -207,7 +224,7 @@
format %{ "ubfx $dst, $src, $rshift, $mask" %}
ins_encode %{
int rshift = $rshift$$constant & 31;
- long mask = $mask$$constant;
+ intptr_t mask = $mask$$constant;
int width = exact_log2(mask+1);
__ ubfx(as_Register($dst$$reg),
as_Register($src$$reg), rshift, width);
@@ -215,50 +232,78 @@
ins_pipe(ialu_reg_shift);
%}
-define(`UBFIZ_INSN',
+define(`UBFIZ_INSN', `// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
+
// We can use ubfiz when masking by a positive number and then left shifting the result.
// We know that the mask is positive because imm$1_bitmask guarantees it.
-`instruct $2$1(iReg$1NoSp dst, iReg$1`'ORL2I($1) src, immI lshift, imm$1_bitmask mask)
+instruct $3$1$8(iReg$2NoSp dst, iReg$1`'ORL2I($1) src, immI lshift, $7 mask)
%{
- match(Set dst (LShift$1 (And$1 src mask) lshift));
- predicate((exact_log2$5(n->in(1)->in(2)->get_$4() + 1) + (n->in(2)->get_int() & $3)) <= ($3 + 1));
+ ifelse($8,,
+ match(Set dst (LShift$1 (And$1 src mask) lshift));,
+ match(Set dst ($8 (LShift$1 (And$1 src mask) lshift)));)
+ ifelse($8,,
+ predicate(($6(n->in(1)->in(2)->get_$5() + 1) + (n->in(2)->get_int() & $4)) <= ($4 + 1));,
+ predicate(($6(n->in(1)->in(1)->in(2)->get_$5() + 1) + (n->in(1)->in(2)->get_int() & $4)) <= 31);)
ins_cost(INSN_COST);
- format %{ "$2 $dst, $src, $lshift, $mask" %}
+ format %{ "$3 $dst, $src, $lshift, $mask" %}
ins_encode %{
- int lshift = $lshift$$constant & $3;
- long mask = $mask$$constant;
- int width = exact_log2$5(mask+1);
- __ $2(as_Register($dst$$reg),
+ int lshift = $lshift$$constant & $4;
+ intptr_t mask = $mask$$constant;
+ int width = $6(mask+1);
+ __ $3(as_Register($dst$$reg),
as_Register($src$$reg), lshift, width);
%}
ins_pipe(ialu_reg_shift);
-%}')
-UBFIZ_INSN(I, ubfizw, 31, int)
-UBFIZ_INSN(L, ubfiz, 63, long, _long)
+%}
+')
+UBFIZ_INSN(I, I, ubfizw, 31, int, exact_log2, immI_bitmask)
+UBFIZ_INSN(L, L, ubfiz, 63, long, exact_log2_long, immL_bitmask)
+UBFIZ_INSN(I, L, ubfizw, 31, int, exact_log2, immI_bitmask, ConvI2L)
+UBFIZ_INSN(L, I, ubfiz, 63, long, exact_log2_long, immL_positive_bitmaskI, ConvL2I)
+
+define(`BFX1_INSN', `// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
-// If there is a convert I to L block between and AndI and a LShiftL, we can also match ubfiz
-instruct ubfizIConvI2L(iRegLNoSp dst, iRegIorL2I src, immI lshift, immI_bitmask mask)
+// If there is a convert $1 to $2 block between and And$1 and a LShift$2, we can also match ubfiz
+instruct ubfiz$1Conv$3$9(iReg$2NoSp dst, iReg$1`'ORL2I($1) src, immI lshift, $8 mask)
%{
- match(Set dst (LShiftL (ConvI2L (AndI src mask)) lshift));
- predicate((exact_log2(n->in(1)->in(1)->in(2)->get_int() + 1) + (n->in(2)->get_int() & 63)) <= (63 + 1));
+ match(Set dst (LShift$2 (Conv$3 (And$1 src mask)) lshift));
+ predicate(($4(n->in(1)->in(1)->in(2)->$5() + 1) + (n->in(2)->get_int() & $6)) <= $7);
ins_cost(INSN_COST);
format %{ "ubfiz $dst, $src, $lshift, $mask" %}
ins_encode %{
- int lshift = $lshift$$constant & 63;
- long mask = $mask$$constant;
+ int lshift = $lshift$$constant & $6;
+ intptr_t mask = $mask$$constant;
int width = exact_log2(mask+1);
__ ubfiz(as_Register($dst$$reg),
as_Register($src$$reg), lshift, width);
%}
ins_pipe(ialu_reg_shift);
%}
+')dnl
+BFX1_INSN(I, L, I2L, exact_log2, get_int, 63, (63 + 1), immI_bitmask)
+BFX1_INSN(L, I, L2I, exact_log2_long, get_long, 31, 31, immL_positive_bitmaskI, x)
+// Can skip int2long conversions after AND with small bitmask
+instruct ubfizIConvI2LAndI(iRegLNoSp dst, iRegI src, immI_bitmask msk)
+%{
+ match(Set dst (ConvI2L (AndI src msk)));
+ ins_cost(INSN_COST);
+ format %{ "ubfiz $dst, $src, 0, exact_log2($msk + 1) " %}
+ ins_encode %{
+ __ ubfiz(as_Register($dst$$reg), as_Register($src$$reg), 0, exact_log2($msk$$constant + 1));
+ %}
+ ins_pipe(ialu_reg_shift);
+%}
-// Rotations
-define(`EXTRACT_INSN',
-`instruct extr$3$1(iReg$1NoSp dst, iReg$1`'ORL2I($1) src1, iReg$1`'ORL2I($1) src2, immI lshift, immI rshift, rFlagsReg cr)
+// Rotations dnl
+define(`EXTRACT_INSN',`
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
+instruct extr$3$1(iReg$1NoSp dst, iReg$1`'ORL2I($1) src1, iReg$1`'ORL2I($1) src2, immI lshift, immI rshift, rFlagsReg cr)
%{
match(Set dst ($3$1 (LShift$1 src1 lshift) (URShift$1 src2 rshift)));
predicate(0 == (((n->in(1)->in(2)->get_int() & $2) + (n->in(2)->in(2)->get_int() & $2)) & $2));
@@ -277,9 +322,10 @@
EXTRACT_INSN(I, 31, Or, extrw)
EXTRACT_INSN(L, 63, Add, extr)
EXTRACT_INSN(I, 31, Add, extrw)
-define(`ROL_EXPAND', `
-// $2 expander
+define(`ROL_EXPAND', `// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
+// $2 expander
instruct $2$1_rReg(iReg$1NoSp dst, iReg$1 src, iRegI shift, rFlagsReg cr)
%{
effect(DEF dst, USE src, USE shift);
@@ -292,10 +338,12 @@
rscratch1);
%}
ins_pipe(ialu_reg_reg_vshift);
-%}')dnl
-define(`ROR_EXPAND', `
-// $2 expander
+%}
+')
+define(`ROR_EXPAND', `// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
+// $2 expander
instruct $2$1_rReg(iReg$1NoSp dst, iReg$1 src, iRegI shift, rFlagsReg cr)
%{
effect(DEF dst, USE src, USE shift);
@@ -307,8 +355,10 @@
as_Register($shift$$reg));
%}
ins_pipe(ialu_reg_reg_vshift);
-%}')dnl
-define(ROL_INSN, `
+%}
+')dnl
+define(ROL_INSN, `// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct $3$1_rReg_Var_C$2(iReg$1NoSp dst, iReg$1 src, iRegI shift, immI$2 c$2, rFlagsReg cr)
%{
match(Set dst (Or$1 (LShift$1 src shift) (URShift$1 src (SubI c$2 shift))));
@@ -316,8 +366,10 @@
expand %{
$3$1_rReg(dst, src, shift, cr);
%}
-%}')dnl
-define(ROR_INSN, `
+%}
+')dnl
+define(ROR_INSN, `// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct $3$1_rReg_Var_C$2(iReg$1NoSp dst, iReg$1 src, iRegI shift, immI$2 c$2, rFlagsReg cr)
%{
match(Set dst (Or$1 (URShift$1 src shift) (LShift$1 src (SubI c$2 shift))));
@@ -325,7 +377,8 @@
expand %{
$3$1_rReg(dst, src, shift, cr);
%}
-%}')dnl
+%}
+')dnl
ROL_EXPAND(L, rol, rorv)
ROL_EXPAND(I, rol, rorvw)
ROL_INSN(L, _64, rol)
@@ -342,6 +395,8 @@
// Add/subtract (extended)
dnl ADD_SUB_EXTENDED(mode, size, add node, shift node, insn, shift type, wordsize
define(`ADD_SUB_CONV', `
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct $3Ext$1(iReg$2NoSp dst, iReg$2`'ORL2I($2) src1, iReg$1`'ORL2I($1) src2, rFlagsReg cr)
%{
match(Set dst ($3$2 src1 (ConvI2L src2)));
@@ -354,10 +409,12 @@
%}
ins_pipe(ialu_reg_reg);
%}')dnl
-ADD_SUB_CONV(I,L,Add,add,sxtw);
-ADD_SUB_CONV(I,L,Sub,sub,sxtw);
+ADD_SUB_CONV(I,L,Add,add,sxtw)
+ADD_SUB_CONV(I,L,Sub,sub,sxtw)
dnl
define(`ADD_SUB_EXTENDED', `
+// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct $3Ext$1_$6(iReg$1NoSp dst, iReg$1`'ORL2I($1) src1, iReg$1`'ORL2I($1) src2, immI_`'eval($7-$2) lshift, immI_`'eval($7-$2) rshift, rFlagsReg cr)
%{
match(Set dst ($3$1 src1 EXTEND($1, $4, src2, lshift, rshift)));
@@ -369,7 +426,7 @@
as_Register($src2$$reg), ext::$6);
%}
ins_pipe(ialu_reg_reg);
-%}')
+%}')dnl
ADD_SUB_EXTENDED(I,16,Add,RShift,add,sxth,32)
ADD_SUB_EXTENDED(I,8,Add,RShift,add,sxtb,32)
ADD_SUB_EXTENDED(I,8,Add,URShift,add,uxtb,32)
@@ -379,7 +436,8 @@
ADD_SUB_EXTENDED(L,8,Add,URShift,add,uxtb,64)
dnl
dnl ADD_SUB_ZERO_EXTEND(mode, size, add node, insn, shift type)
-define(`ADD_SUB_ZERO_EXTEND', `
+define(`ADD_SUB_ZERO_EXTEND', `// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct $3Ext$1_$5_and(iReg$1NoSp dst, iReg$1`'ORL2I($1) src1, iReg$1`'ORL2I($1) src2, imm$1_$2 mask, rFlagsReg cr)
%{
match(Set dst ($3$1 src1 (And$1 src2 mask)));
@@ -391,7 +449,8 @@
as_Register($src2$$reg), ext::$5);
%}
ins_pipe(ialu_reg_reg);
-%}')
+%}
+')
dnl
ADD_SUB_ZERO_EXTEND(I,255,Add,addw,uxtb)
ADD_SUB_ZERO_EXTEND(I,65535,Add,addw,uxth)
@@ -406,7 +465,8 @@
ADD_SUB_ZERO_EXTEND(L,4294967295,Sub,sub,uxtw)
dnl
dnl ADD_SUB_ZERO_EXTEND_SHIFT(mode, size, add node, insn, ext type)
-define(`ADD_SUB_EXTENDED_SHIFT', `
+define(`ADD_SUB_EXTENDED_SHIFT', `// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct $3Ext$1_$6_shift(iReg$1NoSp dst, iReg$1`'ORL2I($1) src1, iReg$1`'ORL2I($1) src2, immIExt lshift2, immI_`'eval($7-$2) lshift1, immI_`'eval($7-$2) rshift1, rFlagsReg cr)
%{
match(Set dst ($3$1 src1 (LShift$1 EXTEND($1, $4, src2, lshift1, rshift1) lshift2)));
@@ -418,7 +478,8 @@
as_Register($src2$$reg), ext::$6, ($lshift2$$constant));
%}
ins_pipe(ialu_reg_reg_shift);
-%}')
+%}
+')
dnl $1 $2 $3 $4 $5 $6 $7
ADD_SUB_EXTENDED_SHIFT(L,8,Add,RShift,add,sxtb,64)
ADD_SUB_EXTENDED_SHIFT(L,16,Add,RShift,add,sxth,64)
@@ -435,7 +496,8 @@
ADD_SUB_EXTENDED_SHIFT(I,16,Sub,RShift,subw,sxth,32)
dnl
dnl ADD_SUB_CONV_SHIFT(mode, add node, insn, ext type)
-define(`ADD_SUB_CONV_SHIFT', `
+define(`ADD_SUB_CONV_SHIFT', `// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct $2ExtI_shift(iReg$1NoSp dst, iReg$1`'ORL2I($1) src1, iRegIorL2I src2, immIExt lshift, rFlagsReg cr)
%{
match(Set dst ($2$1 src1 (LShiftL (ConvI2L src2) lshift)));
@@ -447,13 +509,14 @@
as_Register($src2$$reg), ext::$4, ($lshift$$constant));
%}
ins_pipe(ialu_reg_reg_shift);
-%}')
-dnl
-ADD_SUB_CONV_SHIFT(L,Add,add,sxtw);
-ADD_SUB_CONV_SHIFT(L,Sub,sub,sxtw);
+%}
+')dnl
+ADD_SUB_CONV_SHIFT(L,Add,add,sxtw)
+ADD_SUB_CONV_SHIFT(L,Sub,sub,sxtw)
dnl
dnl ADD_SUB_ZERO_EXTEND(mode, size, add node, insn, ext type)
-define(`ADD_SUB_ZERO_EXTEND_SHIFT', `
+define(`ADD_SUB_ZERO_EXTEND_SHIFT', `// This pattern is automatically generated from aarch64_ad.m4
+// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct $3Ext$1_$5_and_shift(iReg$1NoSp dst, iReg$1`'ORL2I($1) src1, iReg$1`'ORL2I($1) src2, imm$1_$2 mask, immIExt lshift, rFlagsReg cr)
%{
match(Set dst ($3$1 src1 (LShift$1 (And$1 src2 mask) lshift)));
@@ -465,8 +528,8 @@
as_Register($src2$$reg), ext::$5, ($lshift$$constant));
%}
ins_pipe(ialu_reg_reg_shift);
-%}')
-dnl
+%}
+')dnl
dnl $1 $2 $3 $4 $5
ADD_SUB_ZERO_EXTEND_SHIFT(L,255,Add,add,uxtb)
ADD_SUB_ZERO_EXTEND_SHIFT(L,65535,Add,add,uxth)
@@ -482,4 +545,4 @@
ADD_SUB_ZERO_EXTEND_SHIFT(I,255,Sub,subw,uxtb)
ADD_SUB_ZERO_EXTEND_SHIFT(I,65535,Sub,subw,uxth)
dnl
-// END This section of the file is automatically generated. Do not edit --------------
+
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/aarch64-asmtest.py openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/aarch64-asmtest.py
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/aarch64-asmtest.py 1970-01-01 00:00:00.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/aarch64-asmtest.py 2022-01-13 21:56:25.000000000 +0000
@@ -0,0 +1,1183 @@
+import random
+
+AARCH64_AS = "as"
+AARCH64_OBJDUMP = "objdump"
+AARCH64_OBJCOPY = "objcopy"
+
+class Operand(object):
+
+ def generate(self):
+ return self
+
+class Register(Operand):
+
+ def generate(self):
+ self.number = random.randint(0, 30)
+ if self.number == 18:
+ self.number = 17
+ return self
+
+ def astr(self, prefix):
+ return prefix + str(self.number)
+
+class FloatRegister(Register):
+
+ def __str__(self):
+ return self.astr("v")
+
+ def nextReg(self):
+ next = FloatRegister()
+ next.number = (self.number + 1) % 32
+ return next
+
+class GeneralRegister(Register):
+
+ def __str__(self):
+ return self.astr("r")
+
+class GeneralRegisterOrZr(Register):
+
+ def generate(self):
+ self.number = random.randint(0, 31)
+ if self.number == 18:
+ self.number = 16
+ return self
+
+ def astr(self, prefix = ""):
+ if (self.number == 31):
+ return prefix + "zr"
+ else:
+ return prefix + str(self.number)
+
+ def __str__(self):
+ if (self.number == 31):
+ return self.astr()
+ else:
+ return self.astr("r")
+
+class GeneralRegisterOrSp(Register):
+ def generate(self):
+ self.number = random.randint(0, 31)
+ if self.number == 18:
+ self.number = 15
+ return self
+
+ def astr(self, prefix = ""):
+ if (self.number == 31):
+ return "sp"
+ else:
+ return prefix + str(self.number)
+
+ def __str__(self):
+ if (self.number == 31):
+ return self.astr()
+ else:
+ return self.astr("r")
+
+class FloatZero(Operand):
+
+ def __str__(self):
+ return "0.0"
+
+ def astr(self, ignored):
+ return "#0.0"
+
+class OperandFactory:
+
+ _modes = {'x' : GeneralRegister,
+ 'w' : GeneralRegister,
+ 's' : FloatRegister,
+ 'd' : FloatRegister,
+ 'z' : FloatZero}
+
+ @classmethod
+ def create(cls, mode):
+ return OperandFactory._modes[mode]()
+
+class ShiftKind:
+
+ def generate(self):
+ self.kind = ["LSL", "LSR", "ASR"][random.randint(0,2)]
+ return self
+
+ def cstr(self):
+ return self.kind
+
+class Instruction(object):
+
+ def __init__(self, name):
+ self._name = name
+ self.isWord = name.endswith("w") | name.endswith("wi")
+ self.asmRegPrefix = ["x", "w"][self.isWord]
+
+ def aname(self):
+ if (self._name.endswith("wi")):
+ return self._name[:len(self._name)-2]
+ else:
+ if (self._name.endswith("i") | self._name.endswith("w")):
+ return self._name[:len(self._name)-1]
+ else:
+ return self._name
+
+ def emit(self) :
+ pass
+
+ def compare(self) :
+ pass
+
+ def generate(self) :
+ return self
+
+ def cstr(self):
+ return '__ %s(' % self.name()
+
+ def astr(self):
+ return '%s\t' % self.aname()
+
+ def name(self):
+ name = self._name
+ if name == "and":
+ name = "andr" # Special case: the name "and" can't be used
+ # in HotSpot, even for a member.
+ return name
+
+ def multipleForms(self):
+ return 0
+
+class InstructionWithModes(Instruction):
+
+ def __init__(self, name, mode):
+ Instruction.__init__(self, name)
+ self.mode = mode
+ self.isFloat = (mode == 'd') | (mode == 's')
+ if self.isFloat:
+ self.isWord = mode != 'd'
+ self.asmRegPrefix = ["d", "s"][self.isWord]
+ else:
+ self.isWord = mode != 'x'
+ self.asmRegPrefix = ["x", "w"][self.isWord]
+
+ def name(self):
+ return self._name + (self.mode if self.mode != 'x' else '')
+
+ def aname(self):
+ return (self._name+mode if (mode == 'b' or mode == 'h')
+ else self._name)
+
+class ThreeRegInstruction(Instruction):
+
+ def generate(self):
+ self.reg = [GeneralRegister().generate(), GeneralRegister().generate(),
+ GeneralRegister().generate()]
+ return self
+
+
+ def cstr(self):
+ return (super(ThreeRegInstruction, self).cstr()
+ + ('%s, %s, %s'
+ % (self.reg[0],
+ self.reg[1], self.reg[2])))
+
+ def astr(self):
+ prefix = self.asmRegPrefix
+ return (super(ThreeRegInstruction, self).astr()
+ + ('%s, %s, %s'
+ % (self.reg[0].astr(prefix),
+ self.reg[1].astr(prefix), self.reg[2].astr(prefix))))
+
+class FourRegInstruction(ThreeRegInstruction):
+
+ def generate(self):
+ self.reg = ThreeRegInstruction.generate(self).reg + [GeneralRegister().generate()]
+ return self
+
+
+ def cstr(self):
+ return (super(FourRegInstruction, self).cstr()
+ + (', %s' % self.reg[3]))
+
+ def astr(self):
+ prefix = self.asmRegPrefix
+ return (super(FourRegInstruction, self).astr()
+ + (', %s' % self.reg[3].astr(prefix)))
+
+class TwoRegInstruction(Instruction):
+
+ def generate(self):
+ self.reg = [GeneralRegister().generate(), GeneralRegister().generate()]
+ return self
+
+ def cstr(self):
+ return (super(TwoRegInstruction, self).cstr()
+ + '%s, %s' % (self.reg[0],
+ self.reg[1]))
+
+ def astr(self):
+ prefix = self.asmRegPrefix
+ return (super(TwoRegInstruction, self).astr()
+ + ('%s, %s'
+ % (self.reg[0].astr(prefix),
+ self.reg[1].astr(prefix))))
+
+class TwoRegImmedInstruction(TwoRegInstruction):
+
+ def generate(self):
+ super(TwoRegImmedInstruction, self).generate()
+ self.immed = random.randint(0, 1<<11 -1)
+ return self
+
+ def cstr(self):
+ return (super(TwoRegImmedInstruction, self).cstr()
+ + ', %su' % self.immed)
+
+ def astr(self):
+ return (super(TwoRegImmedInstruction, self).astr()
+ + ', #%s' % self.immed)
+
+class OneRegOp(Instruction):
+
+ def generate(self):
+ self.reg = GeneralRegister().generate()
+ return self
+
+ def cstr(self):
+ return (super(OneRegOp, self).cstr()
+ + '%s);' % self.reg)
+
+ def astr(self):
+ return (super(OneRegOp, self).astr()
+ + '%s' % self.reg.astr(self.asmRegPrefix))
+
+class ArithOp(ThreeRegInstruction):
+
+ def generate(self):
+ super(ArithOp, self).generate()
+ self.kind = ShiftKind().generate()
+ self.distance = random.randint(0, (1<<5)-1 if self.isWord else (1<<6)-1)
+ return self
+
+ def cstr(self):
+ return ('%s, Assembler::%s, %s);'
+ % (ThreeRegInstruction.cstr(self),
+ self.kind.cstr(), self.distance))
+
+ def astr(self):
+ return ('%s, %s #%s'
+ % (ThreeRegInstruction.astr(self),
+ self.kind.cstr(),
+ self.distance))
+
+class AddSubCarryOp(ThreeRegInstruction):
+
+ def cstr(self):
+ return ('%s);'
+ % (ThreeRegInstruction.cstr(self)))
+
+class AddSubExtendedOp(ThreeRegInstruction):
+
+ uxtb, uxth, uxtw, uxtx, sxtb, sxth, sxtw, sxtx = range(8)
+ optNames = ["uxtb", "uxth", "uxtw", "uxtx", "sxtb", "sxth", "sxtw", "sxtx"]
+
+ def generate(self):
+ super(AddSubExtendedOp, self).generate()
+ self.amount = random.randint(1, 4)
+ self.option = random.randint(0, 7)
+ return self
+
+ def cstr(self):
+ return (super(AddSubExtendedOp, self).cstr()
+ + (", ext::" + AddSubExtendedOp.optNames[self.option]
+ + ", " + str(self.amount) + ");"))
+
+ def astr(self):
+ return (super(AddSubExtendedOp, self).astr()
+ + (", " + AddSubExtendedOp.optNames[self.option]
+ + " #" + str(self.amount)))
+
+class AddSubImmOp(TwoRegImmedInstruction):
+
+ def cstr(self):
+ return super(AddSubImmOp, self).cstr() + ");"
+
+class LogicalImmOp(AddSubImmOp):
+
+ # These tables are legal immediate logical operands
+ immediates32 \
+ = [0x1, 0x3f, 0x1f0, 0x7e0,
+ 0x1c00, 0x3ff0, 0x8000, 0x1e000,
+ 0x3e000, 0x78000, 0xe0000, 0x100000,
+ 0x1fffe0, 0x3fe000, 0x780000, 0x7ffff8,
+ 0xff8000, 0x1800180, 0x1fffc00, 0x3c003c0,
+ 0x3ffff00, 0x7c00000, 0x7fffe00, 0xf000f00,
+ 0xfffe000, 0x18181818, 0x1ffc0000, 0x1ffffffe,
+ 0x3f003f00, 0x3fffe000, 0x60006000, 0x7f807f80,
+ 0x7ffffc00, 0x800001ff, 0x803fffff, 0x9f9f9f9f,
+ 0xc0000fff, 0xc0c0c0c0, 0xe0000000, 0xe003e003,
+ 0xe3ffffff, 0xf0000fff, 0xf0f0f0f0, 0xf80000ff,
+ 0xf83ff83f, 0xfc00007f, 0xfc1fffff, 0xfe0001ff,
+ 0xfe3fffff, 0xff003fff, 0xff800003, 0xff87ff87,
+ 0xffc00fff, 0xffe0000f, 0xffefffef, 0xfff1fff1,
+ 0xfff83fff, 0xfffc0fff, 0xfffe0fff, 0xffff3fff,
+ 0xffffc007, 0xffffe1ff, 0xfffff80f, 0xfffffe07,
+ 0xffffffbf, 0xfffffffd]
+
+ immediates \
+ = [0x1, 0x1f80, 0x3fff0, 0x3ffffc,
+ 0x3fe0000, 0x1ffc0000, 0xf8000000, 0x3ffffc000,
+ 0xffffffe00, 0x3ffffff800, 0xffffc00000, 0x3f000000000,
+ 0x7fffffff800, 0x1fe000001fe0, 0x3ffffff80000, 0xc00000000000,
+ 0x1ffc000000000, 0x3ffff0003ffff, 0x7ffffffe00000, 0xfffffffffc000,
+ 0x1ffffffffffc00, 0x3fffffffffff00, 0x7ffffffffffc00, 0xffffffffff8000,
+ 0x1ffffffff800000, 0x3fffffc03fffffc, 0x7fffc0000000000, 0xff80ff80ff80ff8,
+ 0x1c00000000000000, 0x1fffffffffff0000, 0x3fffff803fffff80, 0x7fc000007fc00000,
+ 0x8000000000000000, 0x803fffff803fffff, 0xc000007fc000007f, 0xe00000000000ffff,
+ 0xe3ffffffffffffff, 0xf007f007f007f007, 0xf80003ffffffffff, 0xfc000003fc000003,
+ 0xfe000000007fffff, 0xff00000000007fff, 0xff800000000003ff, 0xffc00000000000ff,
+ 0xffe00000000003ff, 0xfff0000000003fff, 0xfff80000001fffff, 0xfffc0000fffc0000,
+ 0xfffe003fffffffff, 0xffff3fffffffffff, 0xffffc0000007ffff, 0xffffe01fffffe01f,
+ 0xfffff800000007ff, 0xfffffc0fffffffff, 0xffffff00003fffff, 0xffffffc0000007ff,
+ 0xfffffff0000001ff, 0xfffffffc00003fff, 0xffffffff07ffffff, 0xffffffffe003ffff,
+ 0xfffffffffc01ffff, 0xffffffffffc00003, 0xfffffffffffc000f, 0xffffffffffffe07f]
+
+ def generate(self):
+ AddSubImmOp.generate(self)
+ self.immed = \
+ self.immediates32[random.randint(0, len(self.immediates32)-1)] \
+ if self.isWord \
+ else \
+ self.immediates[random.randint(0, len(self.immediates)-1)]
+
+ return self
+
+ def astr(self):
+ return (super(TwoRegImmedInstruction, self).astr()
+ + ', #0x%x' % self.immed)
+
+ def cstr(self):
+ return super(AddSubImmOp, self).cstr() + "ll);"
+
+class MultiOp():
+
+ def multipleForms(self):
+ return 3
+
+ def forms(self):
+ return ["__ pc()", "back", "forth"]
+
+ def aforms(self):
+ return [".", "back", "forth"]
+
+class AbsOp(MultiOp, Instruction):
+
+ def cstr(self):
+ return super(AbsOp, self).cstr() + "%s);"
+
+ def astr(self):
+ return Instruction.astr(self) + "%s"
+
+class RegAndAbsOp(MultiOp, Instruction):
+
+ def multipleForms(self):
+ if self.name() == "adrp":
+ # We can only test one form of adrp because anything other
+ # than "adrp ." requires relocs in the assembler output
+ return 1
+ return 3
+
+ def generate(self):
+ Instruction.generate(self)
+ self.reg = GeneralRegister().generate()
+ return self
+
+ def cstr(self):
+ if self.name() == "adrp":
+ return "__ _adrp(" + "%s, %s);" % (self.reg, "%s")
+ return (super(RegAndAbsOp, self).cstr()
+ + "%s, %s);" % (self.reg, "%s"))
+
+ def astr(self):
+ return (super(RegAndAbsOp, self).astr()
+ + self.reg.astr(self.asmRegPrefix) + ", %s")
+
+class RegImmAbsOp(RegAndAbsOp):
+
+ def cstr(self):
+ return (Instruction.cstr(self)
+ + "%s, %s, %s);" % (self.reg, self.immed, "%s"))
+
+ def astr(self):
+ return (Instruction.astr(self)
+ + ("%s, #%s, %s"
+ % (self.reg.astr(self.asmRegPrefix), self.immed, "%s")))
+
+ def generate(self):
+ super(RegImmAbsOp, self).generate()
+ self.immed = random.randint(0, 1<<5 -1)
+ return self
+
+class MoveWideImmOp(RegImmAbsOp):
+
+ def multipleForms(self):
+ return 0
+
+ def cstr(self):
+ return (Instruction.cstr(self)
+ + "%s, %s, %s);" % (self.reg, self.immed, self.shift))
+
+ def astr(self):
+ return (Instruction.astr(self)
+ + ("%s, #%s, lsl %s"
+ % (self.reg.astr(self.asmRegPrefix),
+ self.immed, self.shift)))
+
+ def generate(self):
+ super(RegImmAbsOp, self).generate()
+ self.immed = random.randint(0, 1<<16 -1)
+ if self.isWord:
+ self.shift = random.randint(0, 1) * 16
+ else:
+ self.shift = random.randint(0, 3) * 16
+ return self
+
+class BitfieldOp(TwoRegInstruction):
+
+ def cstr(self):
+ return (Instruction.cstr(self)
+ + ("%s, %s, %s, %s);"
+ % (self.reg[0], self.reg[1], self.immr, self.imms)))
+
+ def astr(self):
+ return (TwoRegInstruction.astr(self)
+ + (", #%s, #%s"
+ % (self.immr, self.imms)))
+
+ def generate(self):
+ TwoRegInstruction.generate(self)
+ self.immr = random.randint(0, 31)
+ self.imms = random.randint(0, 31)
+ return self
+
+class ExtractOp(ThreeRegInstruction):
+
+ def generate(self):
+ super(ExtractOp, self).generate()
+ self.lsb = random.randint(0, (1<<5)-1 if self.isWord else (1<<6)-1)
+ return self
+
+ def cstr(self):
+ return (ThreeRegInstruction.cstr(self)
+ + (", %s);" % self.lsb))
+
+ def astr(self):
+ return (ThreeRegInstruction.astr(self)
+ + (", #%s" % self.lsb))
+
+class CondBranchOp(MultiOp, Instruction):
+
+ def cstr(self):
+ return "__ br(Assembler::" + self.name() + ", %s);"
+
+ def astr(self):
+ return "b." + self.name() + "\t%s"
+
+class ImmOp(Instruction):
+
+ def cstr(self):
+ return "%s%s);" % (Instruction.cstr(self), self.immed)
+
+ def astr(self):
+ return Instruction.astr(self) + "#" + str(self.immed)
+
+ def generate(self):
+ self.immed = random.randint(0, 1<<16 -1)
+ return self
+
+class Op(Instruction):
+
+ def cstr(self):
+ return Instruction.cstr(self) + ");"
+
+class SystemOp(Instruction):
+
+ def __init__(self, op):
+ Instruction.__init__(self, op[0])
+ self.barriers = op[1]
+
+ def generate(self):
+ Instruction.generate(self)
+ self.barrier \
+ = self.barriers[random.randint(0, len(self.barriers)-1)]
+ return self
+
+ def cstr(self):
+ return Instruction.cstr(self) + "Assembler::" + self.barrier + ");"
+
+ def astr(self):
+ return Instruction.astr(self) + self.barrier
+
+conditionCodes = ["EQ", "NE", "HS", "CS", "LO", "CC", "MI", "PL", "VS", \
+ "VC", "HI", "LS", "GE", "LT", "GT", "LE", "AL", "NV"]
+
+class ConditionalCompareOp(TwoRegImmedInstruction):
+
+ def generate(self):
+ TwoRegImmedInstruction.generate(self)
+ self.cond = random.randint(0, 15)
+ self.immed = random.randint(0, 15)
+ return self
+
+ def cstr(self):
+ return (super(ConditionalCompareOp, self).cstr() + ", "
+ + "Assembler::" + conditionCodes[self.cond] + ");")
+
+ def astr(self):
+ return (super(ConditionalCompareOp, self).astr() +
+ ", " + conditionCodes[self.cond])
+
+class ConditionalCompareImmedOp(Instruction):
+
+ def generate(self):
+ self.reg = GeneralRegister().generate()
+ self.cond = random.randint(0, 15)
+ self.immed2 = random.randint(0, 15)
+ self.immed = random.randint(0, 31)
+ return self
+
+ def cstr(self):
+ return (Instruction.cstr(self) + str(self.reg) + ", "
+ + str(self.immed) + ", "
+ + str(self.immed2) + ", "
+ + "Assembler::" + conditionCodes[self.cond] + ");")
+
+ def astr(self):
+ return (Instruction.astr(self)
+ + self.reg.astr(self.asmRegPrefix)
+ + ", #" + str(self.immed)
+ + ", #" + str(self.immed2)
+ + ", " + conditionCodes[self.cond])
+
+class TwoRegOp(TwoRegInstruction):
+
+ def cstr(self):
+ return TwoRegInstruction.cstr(self) + ");"
+
+class ThreeRegOp(ThreeRegInstruction):
+
+ def cstr(self):
+ return ThreeRegInstruction.cstr(self) + ");"
+
+class FourRegMulOp(FourRegInstruction):
+
+ def cstr(self):
+ return FourRegInstruction.cstr(self) + ");"
+
+ def astr(self):
+ isMaddsub = self.name().startswith("madd") | self.name().startswith("msub")
+ midPrefix = self.asmRegPrefix if isMaddsub else "w"
+ return (Instruction.astr(self)
+ + self.reg[0].astr(self.asmRegPrefix)
+ + ", " + self.reg[1].astr(midPrefix)
+ + ", " + self.reg[2].astr(midPrefix)
+ + ", " + self.reg[3].astr(self.asmRegPrefix))
+
+class ConditionalSelectOp(ThreeRegInstruction):
+
+ def generate(self):
+ ThreeRegInstruction.generate(self)
+ self.cond = random.randint(0, 15)
+ return self
+
+ def cstr(self):
+ return (ThreeRegInstruction.cstr(self) + ", "
+ + "Assembler::" + conditionCodes[self.cond] + ");")
+
+ def astr(self):
+ return (ThreeRegInstruction.astr(self)
+ + ", " + conditionCodes[self.cond])
+
+class LoadStoreExclusiveOp(InstructionWithModes):
+
+ def __init__(self, op): # op is a tuple of ["name", "mode", registers]
+ InstructionWithModes.__init__(self, op[0], op[1])
+ self.num_registers = op[2]
+
+ def astr(self):
+ result = self.aname() + '\t'
+ regs = list(self.regs)
+ index = regs.pop() # The last reg is the index register
+ prefix = ('x' if (self.mode == 'x')
+ & ((self.name().startswith("ld"))
+ | (self.name().startswith("stlr"))) # Ewww :-(
+ else 'w')
+ result = result + regs.pop(0).astr(prefix) + ", "
+ for s in regs:
+ result = result + s.astr(self.asmRegPrefix) + ", "
+ result = result + "[" + index.astr("x") + "]"
+ return result
+
+ def cstr(self):
+ result = InstructionWithModes.cstr(self)
+ regs = list(self.regs)
+ index = regs.pop() # The last reg is the index register
+ for s in regs:
+ result = result + str(s) + ", "
+ result = result + str(index) + ");"
+ return result
+
+ def appendUniqueReg(self):
+ result = 0
+ while result == 0:
+ newReg = GeneralRegister().generate()
+ result = 1
+ for i in self.regs:
+ result = result and (i.number != newReg.number)
+ self.regs.append(newReg)
+
+ def generate(self):
+ self.regs = []
+ for i in range(self.num_registers):
+ self.appendUniqueReg()
+ return self
+
+ def name(self):
+ if self.mode == 'x':
+ return self._name
+ else:
+ return self._name + self.mode
+
+ def aname(self):
+ if (self.mode == 'b') | (self.mode == 'h'):
+ return self._name + self.mode
+ else:
+ return self._name
+
+class Address(object):
+
+ base_plus_unscaled_offset, pre, post, base_plus_reg, \
+ base_plus_scaled_offset, pcrel, post_reg, base_only = range(8)
+ kinds = ["base_plus_unscaled_offset", "pre", "post", "base_plus_reg",
+ "base_plus_scaled_offset", "pcrel", "post_reg", "base_only"]
+ extend_kinds = ["uxtw", "lsl", "sxtw", "sxtx"]
+
+ @classmethod
+ def kindToStr(cls, i):
+ return cls.kinds[i]
+
+ def generate(self, kind, shift_distance):
+ self.kind = kind
+ self.base = GeneralRegister().generate()
+ self.index = GeneralRegister().generate()
+ self.offset = {
+ Address.base_plus_unscaled_offset: random.randint(-1<<8, 1<<8-1) | 1,
+ Address.pre: random.randint(-1<<8, 1<<8-1),
+ Address.post: random.randint(-1<<8, 1<<8-1),
+ Address.pcrel: random.randint(0, 2),
+ Address.base_plus_reg: 0,
+ Address.base_plus_scaled_offset: (random.randint(0, 1<<11-1) | (3 << 9))*8,
+ Address.post_reg: 0,
+ Address.base_only: 0} [kind]
+ self.offset >>= (3 - shift_distance)
+ self.extend_kind = Address.extend_kinds[random.randint(0, 3)]
+ self.shift_distance = random.randint(0, 1) * shift_distance
+ return self
+
+ def __str__(self):
+ result = {
+ Address.base_plus_unscaled_offset: "Address(%s, %s)" \
+ % (str(self.base), self.offset),
+ Address.pre: "Address(__ pre(%s, %s))" % (str(self.base), self.offset),
+ Address.post: "Address(__ post(%s, %s))" % (str(self.base), self.offset),
+ Address.post_reg: "Address(__ post(%s, %s))" % (str(self.base), self.index),
+ Address.base_only: "Address(%s)" % (str(self.base)),
+ Address.pcrel: "",
+ Address.base_plus_reg: "Address(%s, %s, Address::%s(%s))" \
+ % (self.base, self.index, self.extend_kind, self.shift_distance),
+ Address.base_plus_scaled_offset:
+ "Address(%s, %s)" % (self.base, self.offset) } [self.kind]
+ if (self.kind == Address.pcrel):
+ result = ["__ pc()", "back", "forth"][self.offset]
+ return result
+
+ def astr(self, prefix):
+ extend_prefix = prefix
+ if self.kind == Address.base_plus_reg:
+ if self.extend_kind.endswith("w"):
+ extend_prefix = "w"
+ result = {
+ Address.base_plus_unscaled_offset: "[%s, %s]" \
+ % (self.base.astr(prefix), self.offset),
+ Address.pre: "[%s, %s]!" % (self.base.astr(prefix), self.offset),
+ Address.post: "[%s], %s" % (self.base.astr(prefix), self.offset),
+ Address.post_reg: "[%s], %s" % (self.base.astr(prefix), self.index.astr(prefix)),
+ Address.base_only: "[%s]" % (self.base.astr(prefix)),
+ Address.pcrel: "",
+ Address.base_plus_reg: "[%s, %s, %s #%s]" \
+ % (self.base.astr(prefix), self.index.astr(extend_prefix),
+ self.extend_kind, self.shift_distance),
+ Address.base_plus_scaled_offset: \
+ "[%s, %s]" \
+ % (self.base.astr(prefix), self.offset)
+ } [self.kind]
+ if (self.kind == Address.pcrel):
+ result = [".", "back", "forth"][self.offset]
+ return result
+
+class LoadStoreOp(InstructionWithModes):
+
+ def __init__(self, args):
+ name, self.asmname, self.kind, mode = args
+ InstructionWithModes.__init__(self, name, mode)
+
+ def generate(self):
+
+ # This is something of a kludge, but the offset needs to be
+ # scaled by the memory datamode somehow.
+ shift = 3
+ if (self.mode == 'b') | (self.asmname.endswith("b")):
+ shift = 0
+ elif (self.mode == 'h') | (self.asmname.endswith("h")):
+ shift = 1
+ elif (self.mode == 'w') | (self.asmname.endswith("w")) \
+ | (self.mode == 's') :
+ shift = 2
+
+ self.adr = Address().generate(self.kind, shift)
+
+ isFloat = (self.mode == 'd') | (self.mode == 's')
+
+ regMode = FloatRegister if isFloat else GeneralRegister
+ self.reg = regMode().generate()
+ return self
+
+ def cstr(self):
+ if not(self._name.startswith("prfm")):
+ return "%s%s, %s);" % (Instruction.cstr(self), str(self.reg), str(self.adr))
+ else: # No target register for a prefetch
+ return "%s%s);" % (Instruction.cstr(self), str(self.adr))
+
+ def astr(self):
+ if not(self._name.startswith("prfm")):
+ return "%s\t%s, %s" % (self.aname(), self.reg.astr(self.asmRegPrefix),
+ self.adr.astr("x"))
+ else: # No target register for a prefetch
+ return "%s %s" % (self.aname(),
+ self.adr.astr("x"))
+
+ def aname(self):
+ result = self.asmname
+ # if self.kind == Address.base_plus_unscaled_offset:
+ # result = result.replace("ld", "ldu", 1)
+ # result = result.replace("st", "stu", 1)
+ return result
+
+class LoadStorePairOp(InstructionWithModes):
+
+ numRegs = 2
+
+ def __init__(self, args):
+ name, self.asmname, self.kind, mode = args
+ InstructionWithModes.__init__(self, name, mode)
+ self.offset = random.randint(-1<<4, 1<<4-1) << 4
+
+ def generate(self):
+ self.reg = [OperandFactory.create(self.mode).generate()
+ for i in range(self.numRegs)]
+ self.base = OperandFactory.create('x').generate()
+ return self
+
+ def astr(self):
+ address = ["[%s, #%s]", "[%s, #%s]!", "[%s], #%s"][self.kind]
+ address = address % (self.base.astr('x'), self.offset)
+ result = "%s\t%s, %s, %s" \
+ % (self.asmname,
+ self.reg[0].astr(self.asmRegPrefix),
+ self.reg[1].astr(self.asmRegPrefix), address)
+ return result
+
+ def cstr(self):
+ address = {
+ Address.base_plus_unscaled_offset: "Address(%s, %s)" \
+ % (str(self.base), self.offset),
+ Address.pre: "Address(__ pre(%s, %s))" % (str(self.base), self.offset),
+ Address.post: "Address(__ post(%s, %s))" % (str(self.base), self.offset),
+ } [self.kind]
+ result = "__ %s(%s, %s, %s);" \
+ % (self.name(), self.reg[0], self.reg[1], address)
+ return result
+
+class FloatInstruction(Instruction):
+
+ def aname(self):
+ if (self._name.endswith("s") | self._name.endswith("d")):
+ return self._name[:len(self._name)-1]
+ else:
+ return self._name
+
+ def __init__(self, args):
+ name, self.modes = args
+ Instruction.__init__(self, name)
+
+ def generate(self):
+ self.reg = [OperandFactory.create(self.modes[i]).generate()
+ for i in range(self.numRegs)]
+ return self
+
+ def cstr(self):
+ formatStr = "%s%s" + ''.join([", %s" for i in range(1, self.numRegs)] + [");"])
+ return (formatStr
+ % tuple([Instruction.cstr(self)] +
+ [str(self.reg[i]) for i in range(self.numRegs)])) # Yowza
+
+ def astr(self):
+ formatStr = "%s%s" + ''.join([", %s" for i in range(1, self.numRegs)])
+ return (formatStr
+ % tuple([Instruction.astr(self)] +
+ [(self.reg[i].astr(self.modes[i])) for i in range(self.numRegs)]))
+
+class LdStSIMDOp(Instruction):
+ def __init__(self, args):
+ self._name, self.regnum, self.arrangement, self.addresskind = args
+
+ def generate(self):
+ self.address = Address().generate(self.addresskind, 0)
+ self._firstSIMDreg = FloatRegister().generate()
+ if (self.addresskind == Address.post):
+ if (self._name in ["ld1r", "ld2r", "ld3r", "ld4r"]):
+ elem_size = {"8B" : 1, "16B" : 1, "4H" : 2, "8H" : 2, "2S" : 4, "4S" : 4, "1D" : 8, "2D" : 8} [self.arrangement]
+ self.address.offset = self.regnum * elem_size
+ else:
+ if (self.arrangement in ["8B", "4H", "2S", "1D"]):
+ self.address.offset = self.regnum * 8
+ else:
+ self.address.offset = self.regnum * 16
+ return self
+
+ def cstr(self):
+ buf = super(LdStSIMDOp, self).cstr() + str(self._firstSIMDreg)
+ current = self._firstSIMDreg
+ for cnt in range(1, self.regnum):
+ buf = '%s, %s' % (buf, current.nextReg())
+ current = current.nextReg()
+ return '%s, __ T%s, %s);' % (buf, self.arrangement, str(self.address))
+
+ def astr(self):
+ buf = '%s\t{%s.%s' % (self._name, self._firstSIMDreg, self.arrangement)
+ current = self._firstSIMDreg
+ for cnt in range(1, self.regnum):
+ buf = '%s, %s.%s' % (buf, current.nextReg(), self.arrangement)
+ current = current.nextReg()
+ return '%s}, %s' % (buf, self.address.astr("x"))
+
+ def aname(self):
+ return self._name
+
+class LSEOp(Instruction):
+ def __init__(self, args):
+ self._name, self.asmname, self.size, self.suffix = args
+
+ def generate(self):
+ self._name = "%s%s" % (self._name, self.suffix)
+ self.asmname = "%s%s" % (self.asmname, self.suffix)
+ self.srcReg = GeneralRegisterOrZr().generate()
+ self.tgtReg = GeneralRegisterOrZr().generate()
+ self.adrReg = GeneralRegisterOrSp().generate()
+
+ return self
+
+ def cstr(self):
+ sizeSpec = {"x" : "Assembler::xword", "w" : "Assembler::word"} [self.size]
+ return super(LSEOp, self).cstr() + "%s, %s, %s, %s);" % (sizeSpec, self.srcReg, self.tgtReg, self.adrReg)
+
+ def astr(self):
+ return "%s\t%s, %s, [%s]" % (self.asmname, self.srcReg.astr(self.size), self.tgtReg.astr(self.size), self.adrReg.astr("x"))
+
+ def aname(self):
+ return self.asmname
+
+class TwoRegFloatOp(FloatInstruction):
+ numRegs = 2
+
+class ThreeRegFloatOp(TwoRegFloatOp):
+ numRegs = 3
+
+class FourRegFloatOp(TwoRegFloatOp):
+ numRegs = 4
+
+class FloatConvertOp(TwoRegFloatOp):
+
+ def __init__(self, args):
+ self._cname, self._aname, modes = args
+ TwoRegFloatOp.__init__(self, [self._cname, modes])
+
+ def aname(self):
+ return self._aname
+
+ def cname(self):
+ return self._cname
+
+class SpecialCases(Instruction):
+ def __init__(self, data):
+ self._name = data[0]
+ self._cstr = data[1]
+ self._astr = data[2]
+
+ def cstr(self):
+ return self._cstr
+
+ def astr(self):
+ return self._astr
+
+def generate(kind, names):
+ outfile.write("# " + kind.__name__ + "\n");
+ print "\n// " + kind.__name__
+ for name in names:
+ for i in range(1):
+ op = kind(name).generate()
+ if op.multipleForms():
+ forms = op.forms()
+ aforms = op.aforms()
+ for i in range(op.multipleForms()):
+ cstr = op.cstr() % forms[i]
+ astr = op.astr() % aforms[i]
+ print " %-50s //\t%s" % (cstr, astr)
+ outfile.write("\t" + astr + "\n")
+ else:
+ print " %-50s //\t%s" % (op.cstr(), op.astr())
+ outfile.write("\t" + op.astr() + "\n")
+
+outfile = open("aarch64ops.s", "w")
+
+print "// BEGIN Generated code -- do not edit"
+print "// Generated by aarch64-asmtest.py"
+
+print " Label back, forth;"
+print " __ bind(back);"
+
+outfile.write("back:\n")
+
+generate (ArithOp,
+ [ "add", "sub", "adds", "subs",
+ "addw", "subw", "addsw", "subsw",
+ "and", "orr", "eor", "ands",
+ "andw", "orrw", "eorw", "andsw",
+ "bic", "orn", "eon", "bics",
+ "bicw", "ornw", "eonw", "bicsw" ])
+
+generate (AddSubImmOp,
+ [ "addw", "addsw", "subw", "subsw",
+ "add", "adds", "sub", "subs"])
+generate (LogicalImmOp,
+ [ "andw", "orrw", "eorw", "andsw",
+ "and", "orr", "eor", "ands"])
+
+generate (AbsOp, [ "b", "bl" ])
+
+generate (RegAndAbsOp, ["cbzw", "cbnzw", "cbz", "cbnz", "adr", "adrp"])
+
+generate (RegImmAbsOp, ["tbz", "tbnz"])
+
+generate (MoveWideImmOp, ["movnw", "movzw", "movkw", "movn", "movz", "movk"])
+
+generate (BitfieldOp, ["sbfm", "bfmw", "ubfmw", "sbfm", "bfm", "ubfm"])
+
+generate (ExtractOp, ["extrw", "extr"])
+
+generate (CondBranchOp, ["EQ", "NE", "HS", "CS", "LO", "CC", "MI", "PL", "VS", "VC",
+ "HI", "LS", "GE", "LT", "GT", "LE", "AL", "NV" ])
+
+generate (ImmOp, ["svc", "hvc", "smc", "brk", "hlt", # "dpcs1", "dpcs2", "dpcs3"
+ ])
+
+generate (Op, ["nop", "eret", "drps", "isb"])
+
+barriers = ["OSHLD", "OSHST", "OSH", "NSHLD", "NSHST", "NSH",
+ "ISHLD", "ISHST", "ISH", "LD", "ST", "SY"]
+
+generate (SystemOp, [["dsb", barriers], ["dmb", barriers]])
+
+generate (OneRegOp, ["br", "blr"])
+
+for mode in 'xwhb':
+ generate (LoadStoreExclusiveOp, [["stxr", mode, 3], ["stlxr", mode, 3],
+ ["ldxr", mode, 2], ["ldaxr", mode, 2],
+ ["stlr", mode, 2], ["ldar", mode, 2]])
+
+for mode in 'xw':
+ generate (LoadStoreExclusiveOp, [["ldxp", mode, 3], ["ldaxp", mode, 3],
+ ["stxp", mode, 4], ["stlxp", mode, 4]])
+
+for kind in range(6):
+ print "\n// " + Address.kindToStr(kind),
+ if kind != Address.pcrel:
+ generate (LoadStoreOp,
+ [["str", "str", kind, "x"], ["str", "str", kind, "w"],
+ ["str", "strb", kind, "b"], ["str", "strh", kind, "h"],
+ ["ldr", "ldr", kind, "x"], ["ldr", "ldr", kind, "w"],
+ ["ldr", "ldrb", kind, "b"], ["ldr", "ldrh", kind, "h"],
+ ["ldrsb", "ldrsb", kind, "x"], ["ldrsh", "ldrsh", kind, "x"],
+ ["ldrsh", "ldrsh", kind, "w"], ["ldrsw", "ldrsw", kind, "x"],
+ ["ldr", "ldr", kind, "d"], ["ldr", "ldr", kind, "s"],
+ ["str", "str", kind, "d"], ["str", "str", kind, "s"],
+ ])
+ else:
+ generate (LoadStoreOp,
+ [["ldr", "ldr", kind, "x"], ["ldr", "ldr", kind, "w"]])
+
+
+for kind in (Address.base_plus_unscaled_offset, Address.pcrel, Address.base_plus_reg, \
+ Address.base_plus_scaled_offset):
+ generate (LoadStoreOp,
+ [["prfm", "prfm\tPLDL1KEEP,", kind, "x"]])
+
+generate(AddSubCarryOp, ["adcw", "adcsw", "sbcw", "sbcsw", "adc", "adcs", "sbc", "sbcs"])
+
+generate(AddSubExtendedOp, ["addw", "addsw", "sub", "subsw", "add", "adds", "sub", "subs"])
+
+generate(ConditionalCompareOp, ["ccmnw", "ccmpw", "ccmn", "ccmp"])
+generate(ConditionalCompareImmedOp, ["ccmnw", "ccmpw", "ccmn", "ccmp"])
+generate(ConditionalSelectOp,
+ ["cselw", "csincw", "csinvw", "csnegw", "csel", "csinc", "csinv", "csneg"])
+
+generate(TwoRegOp,
+ ["rbitw", "rev16w", "revw", "clzw", "clsw", "rbit",
+ "rev16", "rev32", "rev", "clz", "cls"])
+generate(ThreeRegOp,
+ ["udivw", "sdivw", "lslvw", "lsrvw", "asrvw", "rorvw", "udiv", "sdiv",
+ "lslv", "lsrv", "asrv", "rorv", "umulh", "smulh"])
+generate(FourRegMulOp,
+ ["maddw", "msubw", "madd", "msub", "smaddl", "smsubl", "umaddl", "umsubl"])
+
+generate(ThreeRegFloatOp,
+ [["fmuls", "sss"], ["fdivs", "sss"], ["fadds", "sss"], ["fsubs", "sss"],
+ ["fmuls", "sss"],
+ ["fmuld", "ddd"], ["fdivd", "ddd"], ["faddd", "ddd"], ["fsubd", "ddd"],
+ ["fmuld", "ddd"]])
+
+generate(FourRegFloatOp,
+ [["fmadds", "ssss"], ["fmsubs", "ssss"], ["fnmadds", "ssss"], ["fnmadds", "ssss"],
+ ["fmaddd", "dddd"], ["fmsubd", "dddd"], ["fnmaddd", "dddd"], ["fnmaddd", "dddd"],])
+
+generate(TwoRegFloatOp,
+ [["fmovs", "ss"], ["fabss", "ss"], ["fnegs", "ss"], ["fsqrts", "ss"],
+ ["fcvts", "ds"],
+ ["fmovd", "dd"], ["fabsd", "dd"], ["fnegd", "dd"], ["fsqrtd", "dd"],
+ ["fcvtd", "sd"],
+ ])
+
+generate(FloatConvertOp, [["fcvtzsw", "fcvtzs", "ws"], ["fcvtzs", "fcvtzs", "xs"],
+ ["fcvtzdw", "fcvtzs", "wd"], ["fcvtzd", "fcvtzs", "xd"],
+ ["scvtfws", "scvtf", "sw"], ["scvtfs", "scvtf", "sx"],
+ ["scvtfwd", "scvtf", "dw"], ["scvtfd", "scvtf", "dx"],
+ ["fmovs", "fmov", "ws"], ["fmovd", "fmov", "xd"],
+ ["fmovs", "fmov", "sw"], ["fmovd", "fmov", "dx"]])
+
+generate(TwoRegFloatOp, [["fcmps", "ss"], ["fcmpd", "dd"],
+ ["fcmps", "sz"], ["fcmpd", "dz"]])
+
+for kind in range(3):
+ generate(LoadStorePairOp, [["stp", "stp", kind, "w"], ["ldp", "ldp", kind, "w"],
+ ["ldpsw", "ldpsw", kind, "x"],
+ ["stp", "stp", kind, "x"], ["ldp", "ldp", kind, "x"]
+ ])
+generate(LoadStorePairOp, [["stnp", "stnp", 0, "w"], ["ldnp", "ldnp", 0, "w"],
+ ["stnp", "stnp", 0, "x"], ["ldnp", "ldnp", 0, "x"]])
+
+generate(LdStSIMDOp, [["ld1", 1, "8B", Address.base_only],
+ ["ld1", 2, "16B", Address.post],
+ ["ld1", 3, "1D", Address.post_reg],
+ ["ld1", 4, "8H", Address.post],
+ ["ld1r", 1, "8B", Address.base_only],
+ ["ld1r", 1, "4S", Address.post],
+ ["ld1r", 1, "1D", Address.post_reg],
+ ["ld2", 2, "2D", Address.base_only],
+ ["ld2", 2, "4H", Address.post],
+ ["ld2r", 2, "16B", Address.base_only],
+ ["ld2r", 2, "2S", Address.post],
+ ["ld2r", 2, "2D", Address.post_reg],
+ ["ld3", 3, "4S", Address.post_reg],
+ ["ld3", 3, "2S", Address.base_only],
+ ["ld3r", 3, "8H", Address.base_only],
+ ["ld3r", 3, "4S", Address.post],
+ ["ld3r", 3, "1D", Address.post_reg],
+ ["ld4", 4, "8H", Address.post],
+ ["ld4", 4, "8B", Address.post_reg],
+ ["ld4r", 4, "8B", Address.base_only],
+ ["ld4r", 4, "4H", Address.post],
+ ["ld4r", 4, "2S", Address.post_reg],
+])
+
+generate(SpecialCases, [["ccmn", "__ ccmn(zr, zr, 3u, Assembler::LE);", "ccmn\txzr, xzr, #3, LE"],
+ ["ccmnw", "__ ccmnw(zr, zr, 5u, Assembler::EQ);", "ccmn\twzr, wzr, #5, EQ"],
+ ["ccmp", "__ ccmp(zr, 1, 4u, Assembler::NE);", "ccmp\txzr, 1, #4, NE"],
+ ["ccmpw", "__ ccmpw(zr, 2, 2, Assembler::GT);", "ccmp\twzr, 2, #2, GT"],
+ ["extr", "__ extr(zr, zr, zr, 0);", "extr\txzr, xzr, xzr, 0"],
+ ["stlxp", "__ stlxp(r0, zr, zr, sp);", "stlxp\tw0, xzr, xzr, [sp]"],
+ ["stlxpw", "__ stlxpw(r2, zr, zr, r3);", "stlxp\tw2, wzr, wzr, [x3]"],
+ ["stxp", "__ stxp(r4, zr, zr, r5);", "stxp\tw4, xzr, xzr, [x5]"],
+ ["stxpw", "__ stxpw(r6, zr, zr, sp);", "stxp\tw6, wzr, wzr, [sp]"],
+ ["dup", "__ dup(v0, __ T16B, zr);", "dup\tv0.16b, wzr"],
+ ["mov", "__ mov(v1, __ T1D, 0, zr);", "mov\tv1.d[0], xzr"],
+ ["mov", "__ mov(v1, __ T2S, 1, zr);", "mov\tv1.s[1], wzr"],
+ ["mov", "__ mov(v1, __ T4H, 2, zr);", "mov\tv1.h[2], wzr"],
+ ["mov", "__ mov(v1, __ T8B, 3, zr);", "mov\tv1.b[3], wzr"],
+ ["ld1", "__ ld1(v31, v0, __ T2D, Address(__ post(r1, r0)));", "ld1\t{v31.2d, v0.2d}, [x1], x0"]])
+
+print "\n// FloatImmediateOp"
+for float in ("2.0", "2.125", "4.0", "4.25", "8.0", "8.5", "16.0", "17.0", "0.125",
+ "0.1328125", "0.25", "0.265625", "0.5", "0.53125", "1.0", "1.0625",
+ "-2.0", "-2.125", "-4.0", "-4.25", "-8.0", "-8.5", "-16.0", "-17.0",
+ "-0.125", "-0.1328125", "-0.25", "-0.265625", "-0.5", "-0.53125", "-1.0", "-1.0625"):
+ astr = "fmov d0, #" + float
+ cstr = "__ fmovd(v0, " + float + ");"
+ print " %-50s //\t%s" % (cstr, astr)
+ outfile.write("\t" + astr + "\n")
+
+# ARMv8.1A
+for size in ("x", "w"):
+ for suffix in ("", "a", "al", "l"):
+ generate(LSEOp, [["swp", "swp", size, suffix],
+ ["ldadd", "ldadd", size, suffix],
+ ["ldbic", "ldclr", size, suffix],
+ ["ldeor", "ldeor", size, suffix],
+ ["ldorr", "ldset", size, suffix],
+ ["ldsmin", "ldsmin", size, suffix],
+ ["ldsmax", "ldsmax", size, suffix],
+ ["ldumin", "ldumin", size, suffix],
+ ["ldumax", "ldumax", size, suffix]]);
+
+print "\n __ bind(forth);"
+outfile.write("forth:\n")
+
+outfile.close()
+
+import subprocess
+import sys
+
+# compile for 8.1 because of lse atomics
+subprocess.check_call([AARCH64_AS, "-march=armv8.1-a", "aarch64ops.s", "-o", "aarch64ops.o"])
+
+print
+print "/*",
+sys.stdout.flush()
+subprocess.check_call([AARCH64_OBJDUMP, "-d", "aarch64ops.o"])
+print "*/"
+
+subprocess.check_call([AARCH64_OBJCOPY, "-O", "binary", "-j", ".text", "aarch64ops.o", "aarch64ops.bin"])
+
+infile = open("aarch64ops.bin", "r")
+bytes = bytearray(infile.read())
+
+print
+print " static const unsigned int insns[] ="
+print " {"
+
+i = 0
+while i < len(bytes):
+ print " 0x%02x%02x%02x%02x," % (bytes[i+3], bytes[i+2], bytes[i+1], bytes[i]),
+ i += 4
+ if i%16 == 0:
+ print
+print "\n };"
+print "// END Generated code -- do not edit"
+
+
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/abstractInterpreter_aarch64.cpp openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/abstractInterpreter_aarch64.cpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/abstractInterpreter_aarch64.cpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/abstractInterpreter_aarch64.cpp 2022-01-13 21:56:25.000000000 +0000
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2003, 2017, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2003, 2020, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2014, Red Hat Inc. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
@@ -135,7 +135,20 @@
// interpreter_frame_sender_sp interpreter_frame_sender_sp is
// the original sp of the caller (the unextended_sp) and
// sender_sp is fp+8/16 (32bit/64bit) XXX
- intptr_t* locals = interpreter_frame->sender_sp() + max_locals - 1;
+ //
+ // The interpreted method entry on AArch64 aligns SP to 16 bytes
+ // before generating the fixed part of the activation frame. So there
+ // may be a gap between the locals block and the saved sender SP. For
+ // an interpreted caller we need to recreate this gap and exactly
+ // align the incoming parameters with the caller's temporary
+ // expression stack. For other types of caller frame it doesn't
+ // matter.
+ intptr_t* locals;
+ if (caller->is_interpreted_frame()) {
+ locals = caller->interpreter_frame_last_sp() + caller_actual_parameters - 1;
+ } else {
+ locals = interpreter_frame->sender_sp() + max_locals - 1;
+ }
#ifdef ASSERT
if (caller->is_interpreted_frame()) {
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/assembler_aarch64.cpp openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/assembler_aarch64.cpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/assembler_aarch64.cpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/assembler_aarch64.cpp 2022-01-13 21:56:25.000000000 +0000
@@ -31,7 +31,7 @@
#include "interpreter/interpreter.hpp"
#ifndef PRODUCT
-const unsigned long Assembler::asm_bp = 0x00007fffee09ac88;
+const uintptr_t Assembler::asm_bp = 0x00007fffee09ac88;
#endif
#include "compiler/disassembler.hpp"
@@ -96,531 +96,662 @@
__ bind(back);
// ArithOp
- __ add(r19, r22, r7, Assembler::LSL, 28); // add x19, x22, x7, LSL #28
- __ sub(r16, r11, r10, Assembler::LSR, 13); // sub x16, x11, x10, LSR #13
- __ adds(r27, r13, r28, Assembler::ASR, 2); // adds x27, x13, x28, ASR #2
- __ subs(r20, r28, r26, Assembler::ASR, 41); // subs x20, x28, x26, ASR #41
- __ addw(r8, r19, r19, Assembler::ASR, 19); // add w8, w19, w19, ASR #19
- __ subw(r4, r9, r10, Assembler::LSL, 14); // sub w4, w9, w10, LSL #14
- __ addsw(r8, r11, r30, Assembler::LSL, 13); // adds w8, w11, w30, LSL #13
- __ subsw(r0, r25, r19, Assembler::LSL, 9); // subs w0, w25, w19, LSL #9
- __ andr(r20, r0, r21, Assembler::LSL, 19); // and x20, x0, x21, LSL #19
- __ orr(r21, r14, r20, Assembler::LSL, 17); // orr x21, x14, x20, LSL #17
- __ eor(r25, r28, r1, Assembler::LSL, 51); // eor x25, x28, x1, LSL #51
- __ ands(r10, r27, r11, Assembler::ASR, 15); // ands x10, x27, x11, ASR #15
- __ andw(r25, r5, r12, Assembler::ASR, 23); // and w25, w5, w12, ASR #23
- __ orrw(r18, r14, r10, Assembler::LSR, 4); // orr w18, w14, w10, LSR #4
- __ eorw(r4, r21, r5, Assembler::ASR, 22); // eor w4, w21, w5, ASR #22
- __ andsw(r21, r0, r5, Assembler::ASR, 29); // ands w21, w0, w5, ASR #29
- __ bic(r26, r30, r6, Assembler::ASR, 37); // bic x26, x30, x6, ASR #37
- __ orn(r3, r1, r13, Assembler::LSR, 29); // orn x3, x1, x13, LSR #29
- __ eon(r0, r28, r9, Assembler::LSL, 47); // eon x0, x28, x9, LSL #47
- __ bics(r29, r5, r28, Assembler::LSL, 46); // bics x29, x5, x28, LSL #46
- __ bicw(r9, r18, r7, Assembler::LSR, 20); // bic w9, w18, w7, LSR #20
- __ ornw(r26, r13, r25, Assembler::ASR, 24); // orn w26, w13, w25, ASR #24
- __ eonw(r25, r4, r19, Assembler::LSL, 6); // eon w25, w4, w19, LSL #6
- __ bicsw(r5, r26, r4, Assembler::LSR, 24); // bics w5, w26, w4, LSR #24
+ __ add(r15, r0, r24, Assembler::LSL, 59); // add x15, x0, x24, LSL #59
+ __ sub(r17, r22, r22, Assembler::ASR, 13); // sub x17, x22, x22, ASR #13
+ __ adds(r10, r26, r28, Assembler::LSL, 57); // adds x10, x26, x28, LSL #57
+ __ subs(r25, r16, r24, Assembler::LSL, 18); // subs x25, x16, x24, LSL #18
+ __ addw(r8, r5, r28, Assembler::LSL, 7); // add w8, w5, w28, LSL #7
+ __ subw(r8, r28, r1, Assembler::ASR, 28); // sub w8, w28, w1, ASR #28
+ __ addsw(r12, r2, r1, Assembler::LSL, 0); // adds w12, w2, w1, LSL #0
+ __ subsw(r23, r5, r17, Assembler::LSR, 25); // subs w23, w5, w17, LSR #25
+ __ andr(r21, r12, r13, Assembler::LSL, 21); // and x21, x12, x13, LSL #21
+ __ orr(r21, r15, r23, Assembler::ASR, 36); // orr x21, x15, x23, ASR #36
+ __ eor(r22, r24, r27, Assembler::ASR, 48); // eor x22, x24, x27, ASR #48
+ __ ands(r22, r15, r2, Assembler::ASR, 52); // ands x22, x15, x2, ASR #52
+ __ andw(r1, r17, r24, Assembler::ASR, 3); // and w1, w17, w24, ASR #3
+ __ orrw(r5, r2, r6, Assembler::ASR, 11); // orr w5, w2, w6, ASR #11
+ __ eorw(r23, r1, r5, Assembler::LSR, 12); // eor w23, w1, w5, LSR #12
+ __ andsw(r0, r12, r14, Assembler::ASR, 20); // ands w0, w12, w14, ASR #20
+ __ bic(r1, r6, r2, Assembler::LSR, 7); // bic x1, x6, x2, LSR #7
+ __ orn(r30, r8, r4, Assembler::LSL, 47); // orn x30, x8, x4, LSL #47
+ __ eon(r17, r22, r20, Assembler::ASR, 53); // eon x17, x22, x20, ASR #53
+ __ bics(r29, r15, r5, Assembler::ASR, 36); // bics x29, x15, x5, ASR #36
+ __ bicw(r30, r23, r29, Assembler::LSR, 27); // bic w30, w23, w29, LSR #27
+ __ ornw(r12, r29, r2, Assembler::LSL, 20); // orn w12, w29, w2, LSL #20
+ __ eonw(r7, r12, r6, Assembler::ASR, 4); // eon w7, w12, w6, ASR #4
+ __ bicsw(r16, r13, r7, Assembler::ASR, 21); // bics w16, w13, w7, ASR #21
// AddSubImmOp
- __ addw(r7, r19, 340u); // add w7, w19, #340
- __ addsw(r8, r0, 401u); // adds w8, w0, #401
- __ subw(r29, r20, 163u); // sub w29, w20, #163
- __ subsw(r8, r23, 759u); // subs w8, w23, #759
- __ add(r1, r12, 523u); // add x1, x12, #523
- __ adds(r2, r11, 426u); // adds x2, x11, #426
- __ sub(r14, r29, 716u); // sub x14, x29, #716
- __ subs(r11, r5, 582u); // subs x11, x5, #582
+ __ addw(r5, r17, 726u); // add w5, w17, #726
+ __ addsw(r10, r16, 347u); // adds w10, w16, #347
+ __ subw(r26, r5, 978u); // sub w26, w5, #978
+ __ subsw(r21, r24, 689u); // subs w21, w24, #689
+ __ add(r10, r16, 987u); // add x10, x16, #987
+ __ adds(r15, r15, 665u); // adds x15, x15, #665
+ __ sub(r24, r20, 39u); // sub x24, x20, #39
+ __ subs(r10, r13, 76u); // subs x10, x13, #76
// LogicalImmOp
- __ andw(r23, r22, 32768ul); // and w23, w22, #0x8000
- __ orrw(r4, r10, 4042322160ul); // orr w4, w10, #0xf0f0f0f0
- __ eorw(r0, r24, 4042322160ul); // eor w0, w24, #0xf0f0f0f0
- __ andsw(r19, r29, 2139127680ul); // ands w19, w29, #0x7f807f80
- __ andr(r5, r10, 4503599627354112ul); // and x5, x10, #0xfffffffffc000
- __ orr(r12, r30, 18445618178097414144ul); // orr x12, x30, #0xfffc0000fffc0000
- __ eor(r30, r5, 262128ul); // eor x30, x5, #0x3fff0
- __ ands(r26, r23, 4194300ul); // ands x26, x23, #0x3ffffc
+ __ andw(r7, r19, 8388600ull); // and w7, w19, #0x7ffff8
+ __ orrw(r5, r17, 4026535935ull); // orr w5, w17, #0xf0000fff
+ __ eorw(r16, r28, 4186112ull); // eor w16, w28, #0x3fe000
+ __ andsw(r14, r24, 7168ull); // ands w14, w24, #0x1c00
+ __ andr(r14, r27, 18446744073709543551ull); // and x14, x27, #0xffffffffffffe07f
+ __ orr(r12, r11, 576456354256912384ull); // orr x12, x11, #0x7fffc0000000000
+ __ eor(r2, r0, 18437736874454811647ull); // eor x2, x0, #0xffe00000000003ff
+ __ ands(r13, r20, 18446744073642573823ull); // ands x13, x20, #0xfffffffffc01ffff
// AbsOp
- __ b(__ pc()); // b .
- __ b(back); // b back
- __ b(forth); // b forth
- __ bl(__ pc()); // bl .
- __ bl(back); // bl back
- __ bl(forth); // bl forth
+ __ b(__ pc()); // b .
+ __ b(back); // b back
+ __ b(forth); // b forth
+ __ bl(__ pc()); // bl .
+ __ bl(back); // bl back
+ __ bl(forth); // bl forth
// RegAndAbsOp
- __ cbzw(r12, __ pc()); // cbz w12, .
- __ cbzw(r12, back); // cbz w12, back
- __ cbzw(r12, forth); // cbz w12, forth
- __ cbnzw(r20, __ pc()); // cbnz w20, .
- __ cbnzw(r20, back); // cbnz w20, back
- __ cbnzw(r20, forth); // cbnz w20, forth
- __ cbz(r12, __ pc()); // cbz x12, .
- __ cbz(r12, back); // cbz x12, back
- __ cbz(r12, forth); // cbz x12, forth
- __ cbnz(r24, __ pc()); // cbnz x24, .
- __ cbnz(r24, back); // cbnz x24, back
- __ cbnz(r24, forth); // cbnz x24, forth
- __ adr(r6, __ pc()); // adr x6, .
- __ adr(r6, back); // adr x6, back
- __ adr(r6, forth); // adr x6, forth
- __ _adrp(r21, __ pc()); // adrp x21, .
+ __ cbzw(r15, __ pc()); // cbz w15, .
+ __ cbzw(r15, back); // cbz w15, back
+ __ cbzw(r15, forth); // cbz w15, forth
+ __ cbnzw(r28, __ pc()); // cbnz w28, .
+ __ cbnzw(r28, back); // cbnz w28, back
+ __ cbnzw(r28, forth); // cbnz w28, forth
+ __ cbz(r27, __ pc()); // cbz x27, .
+ __ cbz(r27, back); // cbz x27, back
+ __ cbz(r27, forth); // cbz x27, forth
+ __ cbnz(r0, __ pc()); // cbnz x0, .
+ __ cbnz(r0, back); // cbnz x0, back
+ __ cbnz(r0, forth); // cbnz x0, forth
+ __ adr(r13, __ pc()); // adr x13, .
+ __ adr(r13, back); // adr x13, back
+ __ adr(r13, forth); // adr x13, forth
+ __ _adrp(r3, __ pc()); // adrp x3, .
// RegImmAbsOp
- __ tbz(r1, 1, __ pc()); // tbz x1, #1, .
- __ tbz(r1, 1, back); // tbz x1, #1, back
- __ tbz(r1, 1, forth); // tbz x1, #1, forth
- __ tbnz(r8, 9, __ pc()); // tbnz x8, #9, .
- __ tbnz(r8, 9, back); // tbnz x8, #9, back
- __ tbnz(r8, 9, forth); // tbnz x8, #9, forth
+ __ tbz(r21, 7, __ pc()); // tbz x21, #7, .
+ __ tbz(r21, 7, back); // tbz x21, #7, back
+ __ tbz(r21, 7, forth); // tbz x21, #7, forth
+ __ tbnz(r15, 9, __ pc()); // tbnz x15, #9, .
+ __ tbnz(r15, 9, back); // tbnz x15, #9, back
+ __ tbnz(r15, 9, forth); // tbnz x15, #9, forth
// MoveWideImmOp
- __ movnw(r12, 23175, 0); // movn w12, #23175, lsl 0
- __ movzw(r11, 20476, 16); // movz w11, #20476, lsl 16
- __ movkw(r21, 3716, 0); // movk w21, #3716, lsl 0
- __ movn(r29, 28661, 48); // movn x29, #28661, lsl 48
- __ movz(r3, 6927, 0); // movz x3, #6927, lsl 0
- __ movk(r22, 9828, 16); // movk x22, #9828, lsl 16
+ __ movnw(r14, 2655, 16); // movn w14, #2655, lsl 16
+ __ movzw(r17, 7642, 0); // movz w17, #7642, lsl 0
+ __ movkw(r27, 11381, 0); // movk w27, #11381, lsl 0
+ __ movn(r1, 19524, 32); // movn x1, #19524, lsl 32
+ __ movz(r20, 21126, 16); // movz x20, #21126, lsl 16
+ __ movk(r20, 32462, 16); // movk x20, #32462, lsl 16
// BitfieldOp
- __ sbfm(r12, r8, 6, 22); // sbfm x12, x8, #6, #22
- __ bfmw(r19, r25, 25, 19); // bfm w19, w25, #25, #19
- __ ubfmw(r9, r12, 29, 15); // ubfm w9, w12, #29, #15
- __ sbfm(r28, r25, 16, 16); // sbfm x28, x25, #16, #16
- __ bfm(r12, r5, 4, 25); // bfm x12, x5, #4, #25
- __ ubfm(r0, r10, 6, 8); // ubfm x0, x10, #6, #8
+ __ sbfm(r13, r2, 28, 20); // sbfm x13, x2, #28, #20
+ __ bfmw(r16, r20, 19, 15); // bfm w16, w20, #19, #15
+ __ ubfmw(r11, r11, 9, 6); // ubfm w11, w11, #9, #6
+ __ sbfm(r2, r4, 25, 21); // sbfm x2, x4, #25, #21
+ __ bfm(r13, r16, 2, 19); // bfm x13, x16, #2, #19
+ __ ubfm(r8, r25, 8, 5); // ubfm x8, x25, #8, #5
// ExtractOp
- __ extrw(r4, r13, r26, 24); // extr w4, w13, w26, #24
- __ extr(r23, r30, r24, 31); // extr x23, x30, x24, #31
+ __ extrw(r29, r27, r10, 14); // extr w29, w27, w10, #14
+ __ extr(r6, r20, r6, 24); // extr x6, x20, x6, #24
// CondBranchOp
- __ br(Assembler::EQ, __ pc()); // b.EQ .
- __ br(Assembler::EQ, back); // b.EQ back
- __ br(Assembler::EQ, forth); // b.EQ forth
- __ br(Assembler::NE, __ pc()); // b.NE .
- __ br(Assembler::NE, back); // b.NE back
- __ br(Assembler::NE, forth); // b.NE forth
- __ br(Assembler::HS, __ pc()); // b.HS .
- __ br(Assembler::HS, back); // b.HS back
- __ br(Assembler::HS, forth); // b.HS forth
- __ br(Assembler::CS, __ pc()); // b.CS .
- __ br(Assembler::CS, back); // b.CS back
- __ br(Assembler::CS, forth); // b.CS forth
- __ br(Assembler::LO, __ pc()); // b.LO .
- __ br(Assembler::LO, back); // b.LO back
- __ br(Assembler::LO, forth); // b.LO forth
- __ br(Assembler::CC, __ pc()); // b.CC .
- __ br(Assembler::CC, back); // b.CC back
- __ br(Assembler::CC, forth); // b.CC forth
- __ br(Assembler::MI, __ pc()); // b.MI .
- __ br(Assembler::MI, back); // b.MI back
- __ br(Assembler::MI, forth); // b.MI forth
- __ br(Assembler::PL, __ pc()); // b.PL .
- __ br(Assembler::PL, back); // b.PL back
- __ br(Assembler::PL, forth); // b.PL forth
- __ br(Assembler::VS, __ pc()); // b.VS .
- __ br(Assembler::VS, back); // b.VS back
- __ br(Assembler::VS, forth); // b.VS forth
- __ br(Assembler::VC, __ pc()); // b.VC .
- __ br(Assembler::VC, back); // b.VC back
- __ br(Assembler::VC, forth); // b.VC forth
- __ br(Assembler::HI, __ pc()); // b.HI .
- __ br(Assembler::HI, back); // b.HI back
- __ br(Assembler::HI, forth); // b.HI forth
- __ br(Assembler::LS, __ pc()); // b.LS .
- __ br(Assembler::LS, back); // b.LS back
- __ br(Assembler::LS, forth); // b.LS forth
- __ br(Assembler::GE, __ pc()); // b.GE .
- __ br(Assembler::GE, back); // b.GE back
- __ br(Assembler::GE, forth); // b.GE forth
- __ br(Assembler::LT, __ pc()); // b.LT .
- __ br(Assembler::LT, back); // b.LT back
- __ br(Assembler::LT, forth); // b.LT forth
- __ br(Assembler::GT, __ pc()); // b.GT .
- __ br(Assembler::GT, back); // b.GT back
- __ br(Assembler::GT, forth); // b.GT forth
- __ br(Assembler::LE, __ pc()); // b.LE .
- __ br(Assembler::LE, back); // b.LE back
- __ br(Assembler::LE, forth); // b.LE forth
- __ br(Assembler::AL, __ pc()); // b.AL .
- __ br(Assembler::AL, back); // b.AL back
- __ br(Assembler::AL, forth); // b.AL forth
- __ br(Assembler::NV, __ pc()); // b.NV .
- __ br(Assembler::NV, back); // b.NV back
- __ br(Assembler::NV, forth); // b.NV forth
+ __ br(Assembler::EQ, __ pc()); // b.EQ .
+ __ br(Assembler::EQ, back); // b.EQ back
+ __ br(Assembler::EQ, forth); // b.EQ forth
+ __ br(Assembler::NE, __ pc()); // b.NE .
+ __ br(Assembler::NE, back); // b.NE back
+ __ br(Assembler::NE, forth); // b.NE forth
+ __ br(Assembler::HS, __ pc()); // b.HS .
+ __ br(Assembler::HS, back); // b.HS back
+ __ br(Assembler::HS, forth); // b.HS forth
+ __ br(Assembler::CS, __ pc()); // b.CS .
+ __ br(Assembler::CS, back); // b.CS back
+ __ br(Assembler::CS, forth); // b.CS forth
+ __ br(Assembler::LO, __ pc()); // b.LO .
+ __ br(Assembler::LO, back); // b.LO back
+ __ br(Assembler::LO, forth); // b.LO forth
+ __ br(Assembler::CC, __ pc()); // b.CC .
+ __ br(Assembler::CC, back); // b.CC back
+ __ br(Assembler::CC, forth); // b.CC forth
+ __ br(Assembler::MI, __ pc()); // b.MI .
+ __ br(Assembler::MI, back); // b.MI back
+ __ br(Assembler::MI, forth); // b.MI forth
+ __ br(Assembler::PL, __ pc()); // b.PL .
+ __ br(Assembler::PL, back); // b.PL back
+ __ br(Assembler::PL, forth); // b.PL forth
+ __ br(Assembler::VS, __ pc()); // b.VS .
+ __ br(Assembler::VS, back); // b.VS back
+ __ br(Assembler::VS, forth); // b.VS forth
+ __ br(Assembler::VC, __ pc()); // b.VC .
+ __ br(Assembler::VC, back); // b.VC back
+ __ br(Assembler::VC, forth); // b.VC forth
+ __ br(Assembler::HI, __ pc()); // b.HI .
+ __ br(Assembler::HI, back); // b.HI back
+ __ br(Assembler::HI, forth); // b.HI forth
+ __ br(Assembler::LS, __ pc()); // b.LS .
+ __ br(Assembler::LS, back); // b.LS back
+ __ br(Assembler::LS, forth); // b.LS forth
+ __ br(Assembler::GE, __ pc()); // b.GE .
+ __ br(Assembler::GE, back); // b.GE back
+ __ br(Assembler::GE, forth); // b.GE forth
+ __ br(Assembler::LT, __ pc()); // b.LT .
+ __ br(Assembler::LT, back); // b.LT back
+ __ br(Assembler::LT, forth); // b.LT forth
+ __ br(Assembler::GT, __ pc()); // b.GT .
+ __ br(Assembler::GT, back); // b.GT back
+ __ br(Assembler::GT, forth); // b.GT forth
+ __ br(Assembler::LE, __ pc()); // b.LE .
+ __ br(Assembler::LE, back); // b.LE back
+ __ br(Assembler::LE, forth); // b.LE forth
+ __ br(Assembler::AL, __ pc()); // b.AL .
+ __ br(Assembler::AL, back); // b.AL back
+ __ br(Assembler::AL, forth); // b.AL forth
+ __ br(Assembler::NV, __ pc()); // b.NV .
+ __ br(Assembler::NV, back); // b.NV back
+ __ br(Assembler::NV, forth); // b.NV forth
// ImmOp
- __ svc(12729); // svc #12729
- __ hvc(6788); // hvc #6788
- __ smc(1535); // smc #1535
- __ brk(16766); // brk #16766
- __ hlt(9753); // hlt #9753
+ __ svc(26948); // svc #26948
+ __ hvc(29998); // hvc #29998
+ __ smc(10437); // smc #10437
+ __ brk(30290); // brk #30290
+ __ hlt(20851); // hlt #20851
// Op
- __ nop(); // nop
- __ eret(); // eret
- __ drps(); // drps
- __ isb(); // isb
+ __ nop(); // nop
+ __ eret(); // eret
+ __ drps(); // drps
+ __ isb(); // isb
// SystemOp
- __ dsb(Assembler::SY); // dsb SY
- __ dmb(Assembler::ISHST); // dmb ISHST
+ __ dsb(Assembler::LD); // dsb LD
+ __ dmb(Assembler::ISH); // dmb ISH
// OneRegOp
- __ br(r2); // br x2
- __ blr(r5); // blr x5
+ __ br(r9); // br x9
+ __ blr(r9); // blr x9
// LoadStoreExclusiveOp
- __ stxr(r20, r21, r2); // stxr w20, x21, [x2]
- __ stlxr(r5, r29, r7); // stlxr w5, x29, [x7]
- __ ldxr(r5, r16); // ldxr x5, [x16]
- __ ldaxr(r27, r29); // ldaxr x27, [x29]
- __ stlr(r0, r29); // stlr x0, [x29]
- __ ldar(r21, r28); // ldar x21, [x28]
+ __ stxr(r2, r29, r11); // stxr w2, x29, [x11]
+ __ stlxr(r22, r5, r28); // stlxr w22, x5, [x28]
+ __ ldxr(r14, r20); // ldxr x14, [x20]
+ __ ldaxr(r29, r19); // ldaxr x29, [x19]
+ __ stlr(r6, r21); // stlr x6, [x21]
+ __ ldar(r19, r3); // ldar x19, [x3]
// LoadStoreExclusiveOp
- __ stxrw(r21, r24, r7); // stxr w21, w24, [x7]
- __ stlxrw(r21, r26, r28); // stlxr w21, w26, [x28]
- __ ldxrw(r21, r6); // ldxr w21, [x6]
- __ ldaxrw(r15, r30); // ldaxr w15, [x30]
- __ stlrw(r19, r3); // stlr w19, [x3]
- __ ldarw(r22, r2); // ldar w22, [x2]
+ __ stxrw(r12, r3, r27); // stxr w12, w3, [x27]
+ __ stlxrw(r17, r26, r15); // stlxr w17, w26, [x15]
+ __ ldxrw(r13, r14); // ldxr w13, [x14]
+ __ ldaxrw(r12, r26); // ldaxr w12, [x26]
+ __ stlrw(r8, r17); // stlr w8, [x17]
+ __ ldarw(r21, r30); // ldar w21, [x30]
// LoadStoreExclusiveOp
- __ stxrh(r18, r15, r0); // stxrh w18, w15, [x0]
- __ stlxrh(r11, r5, r28); // stlxrh w11, w5, [x28]
- __ ldxrh(r29, r6); // ldxrh w29, [x6]
- __ ldaxrh(r18, r7); // ldaxrh w18, [x7]
- __ stlrh(r25, r28); // stlrh w25, [x28]
- __ ldarh(r2, r19); // ldarh w2, [x19]
+ __ stxrh(r0, r15, r11); // stxrh w0, w15, [x11]
+ __ stlxrh(r17, r20, r1); // stlxrh w17, w20, [x1]
+ __ ldxrh(r29, r8); // ldxrh w29, [x8]
+ __ ldaxrh(r17, r12); // ldaxrh w17, [x12]
+ __ stlrh(r11, r4); // stlrh w11, [x4]
+ __ ldarh(r16, r4); // ldarh w16, [x4]
// LoadStoreExclusiveOp
- __ stxrb(r10, r30, r1); // stxrb w10, w30, [x1]
- __ stlxrb(r20, r21, r22); // stlxrb w20, w21, [x22]
- __ ldxrb(r25, r2); // ldxrb w25, [x2]
- __ ldaxrb(r24, r5); // ldaxrb w24, [x5]
- __ stlrb(r16, r3); // stlrb w16, [x3]
- __ ldarb(r22, r29); // ldarb w22, [x29]
+ __ stxrb(r14, r5, r4); // stxrb w14, w5, [x4]
+ __ stlxrb(r27, r17, r16); // stlxrb w27, w17, [x16]
+ __ ldxrb(r6, r27); // ldxrb w6, [x27]
+ __ ldaxrb(r27, r24); // ldaxrb w27, [x24]
+ __ stlrb(r10, r20); // stlrb w10, [x20]
+ __ ldarb(r9, r26); // ldarb w9, [x26]
// LoadStoreExclusiveOp
- __ ldxp(r8, r2, r19); // ldxp x8, x2, [x19]
- __ ldaxp(r7, r19, r14); // ldaxp x7, x19, [x14]
- __ stxp(r8, r27, r28, r5); // stxp w8, x27, x28, [x5]
- __ stlxp(r5, r8, r14, r6); // stlxp w5, x8, x14, [x6]
+ __ ldxp(r5, r30, r28); // ldxp x5, x30, [x28]
+ __ ldaxp(r10, r9, r19); // ldaxp x10, x9, [x19]
+ __ stxp(r11, r16, r21, r12); // stxp w11, x16, x21, [x12]
+ __ stlxp(r10, r20, r23, r4); // stlxp w10, x20, x23, [x4]
// LoadStoreExclusiveOp
- __ ldxpw(r25, r4, r22); // ldxp w25, w4, [x22]
- __ ldaxpw(r13, r14, r15); // ldaxp w13, w14, [x15]
- __ stxpw(r20, r26, r8, r10); // stxp w20, w26, w8, [x10]
- __ stlxpw(r23, r18, r18, r18); // stlxp w23, w18, w18, [x18]
+ __ ldxpw(r22, r1, r0); // ldxp w22, w1, [x0]
+ __ ldaxpw(r3, r1, r8); // ldaxp w3, w1, [x8]
+ __ stxpw(r0, r9, r23, r30); // stxp w0, w9, w23, [x30]
+ __ stlxpw(r23, r0, r17, r11); // stlxp w23, w0, w17, [x11]
// base_plus_unscaled_offset
// LoadStoreOp
- __ str(r30, Address(r11, 99)); // str x30, [x11, 99]
- __ strw(r23, Address(r25, -77)); // str w23, [x25, -77]
- __ strb(r2, Address(r14, 3)); // strb w2, [x14, 3]
- __ strh(r9, Address(r10, 5)); // strh w9, [x10, 5]
- __ ldr(r20, Address(r15, 57)); // ldr x20, [x15, 57]
- __ ldrw(r12, Address(r16, -78)); // ldr w12, [x16, -78]
- __ ldrb(r22, Address(r26, -3)); // ldrb w22, [x26, -3]
- __ ldrh(r30, Address(r19, -47)); // ldrh w30, [x19, -47]
- __ ldrsb(r9, Address(r10, -12)); // ldrsb x9, [x10, -12]
- __ ldrsh(r28, Address(r17, 14)); // ldrsh x28, [x17, 14]
- __ ldrshw(r3, Address(r5, 10)); // ldrsh w3, [x5, 10]
- __ ldrsw(r17, Address(r17, -91)); // ldrsw x17, [x17, -91]
- __ ldrd(v2, Address(r20, -17)); // ldr d2, [x20, -17]
- __ ldrs(v22, Address(r7, -10)); // ldr s22, [x7, -10]
- __ strd(v30, Address(r18, -223)); // str d30, [x18, -223]
- __ strs(v13, Address(r22, 21)); // str s13, [x22, 21]
+ __ str(r6, Address(r10, -31)); // str x6, [x10, -31]
+ __ strw(r7, Address(r0, -5)); // str w7, [x0, -5]
+ __ strb(r5, Address(r16, -13)); // strb w5, [x16, -13]
+ __ strh(r30, Address(r19, 31)); // strh w30, [x19, 31]
+ __ ldr(r16, Address(r9, 119)); // ldr x16, [x9, 119]
+ __ ldrw(r8, Address(r16, 59)); // ldr w8, [x16, 59]
+ __ ldrb(r10, Address(r12, -7)); // ldrb w10, [x12, -7]
+ __ ldrh(r14, Address(r9, -38)); // ldrh w14, [x9, -38]
+ __ ldrsb(r24, Address(r30, -8)); // ldrsb x24, [x30, -8]
+ __ ldrsh(r7, Address(r4, 23)); // ldrsh x7, [x4, 23]
+ __ ldrshw(r17, Address(r14, -39)); // ldrsh w17, [x14, -39]
+ __ ldrsw(r11, Address(r27, -31)); // ldrsw x11, [x27, -31]
+ __ ldrd(v12, Address(r7, 65)); // ldr d12, [x7, 65]
+ __ ldrs(v0, Address(r16, -2)); // ldr s0, [x16, -2]
+ __ strd(v13, Address(r23, -161)); // str d13, [x23, -161]
+ __ strs(v21, Address(r3, -62)); // str s21, [x3, -62]
// pre
// LoadStoreOp
- __ str(r9, Address(__ pre(r18, -112))); // str x9, [x18, -112]!
- __ strw(r29, Address(__ pre(r23, 11))); // str w29, [x23, 11]!
- __ strb(r18, Address(__ pre(r12, -1))); // strb w18, [x12, -1]!
- __ strh(r16, Address(__ pre(r20, -23))); // strh w16, [x20, -23]!
- __ ldr(r3, Address(__ pre(r29, 9))); // ldr x3, [x29, 9]!
- __ ldrw(r25, Address(__ pre(r3, 19))); // ldr w25, [x3, 19]!
- __ ldrb(r1, Address(__ pre(r29, -1))); // ldrb w1, [x29, -1]!
- __ ldrh(r8, Address(__ pre(r29, -57))); // ldrh w8, [x29, -57]!
- __ ldrsb(r5, Address(__ pre(r14, -13))); // ldrsb x5, [x14, -13]!
- __ ldrsh(r10, Address(__ pre(r27, 1))); // ldrsh x10, [x27, 1]!
- __ ldrshw(r11, Address(__ pre(r10, 25))); // ldrsh w11, [x10, 25]!
- __ ldrsw(r4, Address(__ pre(r22, -92))); // ldrsw x4, [x22, -92]!
- __ ldrd(v11, Address(__ pre(r23, 8))); // ldr d11, [x23, 8]!
- __ ldrs(v25, Address(__ pre(r19, 54))); // ldr s25, [x19, 54]!
- __ strd(v1, Address(__ pre(r7, -174))); // str d1, [x7, -174]!
- __ strs(v8, Address(__ pre(r25, 54))); // str s8, [x25, 54]!
+ __ str(r2, Address(__ pre(r5, 100))); // str x2, [x5, 100]!
+ __ strw(r9, Address(__ pre(r1, -92))); // str w9, [x1, -92]!
+ __ strb(r27, Address(__ pre(r30, -5))); // strb w27, [x30, -5]!
+ __ strh(r27, Address(__ pre(r15, 12))); // strh w27, [x15, 12]!
+ __ ldr(r4, Address(__ pre(r17, -212))); // ldr x4, [x17, -212]!
+ __ ldrw(r21, Address(__ pre(r23, 30))); // ldr w21, [x23, 30]!
+ __ ldrb(r13, Address(__ pre(r17, -7))); // ldrb w13, [x17, -7]!
+ __ ldrh(r25, Address(__ pre(r0, -50))); // ldrh w25, [x0, -50]!
+ __ ldrsb(r1, Address(__ pre(r21, -21))); // ldrsb x1, [x21, -21]!
+ __ ldrsh(r28, Address(__ pre(r21, -54))); // ldrsh x28, [x21, -54]!
+ __ ldrshw(r11, Address(__ pre(r4, 2))); // ldrsh w11, [x4, 2]!
+ __ ldrsw(r17, Address(__ pre(r9, 61))); // ldrsw x17, [x9, 61]!
+ __ ldrd(v29, Address(__ pre(r19, 39))); // ldr d29, [x19, 39]!
+ __ ldrs(v22, Address(__ pre(r22, -85))); // ldr s22, [x22, -85]!
+ __ strd(v9, Address(__ pre(r25, -225))); // str d9, [x25, -225]!
+ __ strs(v9, Address(__ pre(r2, -15))); // str s9, [x2, -15]!
// post
// LoadStoreOp
- __ str(r5, Address(__ post(r11, 37))); // str x5, [x11], 37
- __ strw(r24, Address(__ post(r15, 19))); // str w24, [x15], 19
- __ strb(r15, Address(__ post(r26, -1))); // strb w15, [x26], -1
- __ strh(r18, Address(__ post(r18, -6))); // strh w18, [x18], -6
- __ ldr(r7, Address(__ post(r2, -230))); // ldr x7, [x2], -230
- __ ldrw(r27, Address(__ post(r11, -27))); // ldr w27, [x11], -27
- __ ldrb(r18, Address(__ post(r3, -25))); // ldrb w18, [x3], -25
- __ ldrh(r10, Address(__ post(r24, -32))); // ldrh w10, [x24], -32
- __ ldrsb(r22, Address(__ post(r10, 4))); // ldrsb x22, [x10], 4
- __ ldrsh(r17, Address(__ post(r12, 25))); // ldrsh x17, [x12], 25
- __ ldrshw(r8, Address(__ post(r7, -62))); // ldrsh w8, [x7], -62
- __ ldrsw(r23, Address(__ post(r22, -51))); // ldrsw x23, [x22], -51
- __ ldrd(v24, Address(__ post(r25, 48))); // ldr d24, [x25], 48
- __ ldrs(v21, Address(__ post(r12, -10))); // ldr s21, [x12], -10
- __ strd(v18, Address(__ post(r13, -222))); // str d18, [x13], -222
- __ strs(v16, Address(__ post(r1, -41))); // str s16, [x1], -41
+ __ str(r13, Address(__ post(r23, -66))); // str x13, [x23], -66
+ __ strw(r17, Address(__ post(r16, 10))); // str w17, [x16], 10
+ __ strb(r1, Address(__ post(r14, -32))); // strb w1, [x14], -32
+ __ strh(r17, Address(__ post(r0, 6))); // strh w17, [x0], 6
+ __ ldr(r27, Address(__ post(r25, -172))); // ldr x27, [x25], -172
+ __ ldrw(r13, Address(__ post(r25, -38))); // ldr w13, [x25], -38
+ __ ldrb(r11, Address(__ post(r25, -29))); // ldrb w11, [x25], -29
+ __ ldrh(r30, Address(__ post(r5, 20))); // ldrh w30, [x5], 20
+ __ ldrsb(r9, Address(__ post(r7, -7))); // ldrsb x9, [x7], -7
+ __ ldrsh(r0, Address(__ post(r3, -62))); // ldrsh x0, [x3], -62
+ __ ldrshw(r7, Address(__ post(r14, 31))); // ldrsh w7, [x14], 31
+ __ ldrsw(r17, Address(__ post(r27, 39))); // ldrsw x17, [x27], 39
+ __ ldrd(v17, Address(__ post(r4, -235))); // ldr d17, [x4], -235
+ __ ldrs(v26, Address(__ post(r21, 34))); // ldr s26, [x21], 34
+ __ strd(v5, Address(__ post(r17, -57))); // str d5, [x17], -57
+ __ strs(v13, Address(__ post(r13, -109))); // str s13, [x13], -109
// base_plus_reg
// LoadStoreOp
- __ str(r2, Address(r22, r15, Address::sxtw(0))); // str x2, [x22, w15, sxtw #0]
- __ strw(r2, Address(r16, r29, Address::lsl(0))); // str w2, [x16, x29, lsl #0]
- __ strb(r20, Address(r18, r14, Address::uxtw(0))); // strb w20, [x18, w14, uxtw #0]
- __ strh(r6, Address(r19, r20, Address::sxtx(1))); // strh w6, [x19, x20, sxtx #1]
- __ ldr(r14, Address(r29, r14, Address::sxtw(0))); // ldr x14, [x29, w14, sxtw #0]
- __ ldrw(r16, Address(r20, r12, Address::sxtw(2))); // ldr w16, [x20, w12, sxtw #2]
- __ ldrb(r9, Address(r12, r0, Address::sxtw(0))); // ldrb w9, [x12, w0, sxtw #0]
- __ ldrh(r12, Address(r17, r3, Address::lsl(1))); // ldrh w12, [x17, x3, lsl #1]
- __ ldrsb(r2, Address(r17, r3, Address::sxtx(0))); // ldrsb x2, [x17, x3, sxtx #0]
- __ ldrsh(r7, Address(r1, r17, Address::uxtw(1))); // ldrsh x7, [x1, w17, uxtw #1]
- __ ldrshw(r25, Address(r15, r18, Address::sxtw(1))); // ldrsh w25, [x15, w18, sxtw #1]
- __ ldrsw(r23, Address(r21, r12, Address::lsl(0))); // ldrsw x23, [x21, x12, lsl #0]
- __ ldrd(v5, Address(r13, r8, Address::lsl(3))); // ldr d5, [x13, x8, lsl #3]
- __ ldrs(v3, Address(r10, r22, Address::lsl(2))); // ldr s3, [x10, x22, lsl #2]
- __ strd(v14, Address(r2, r27, Address::sxtw(0))); // str d14, [x2, w27, sxtw #0]
- __ strs(v20, Address(r6, r25, Address::lsl(0))); // str s20, [x6, x25, lsl #0]
+ __ str(r6, Address(r16, r4, Address::sxtw(3))); // str x6, [x16, w4, sxtw #3]
+ __ strw(r9, Address(r24, r20, Address::sxtw(2))); // str w9, [x24, w20, sxtw #2]
+ __ strb(r3, Address(r29, r3, Address::lsl(0))); // strb w3, [x29, x3, lsl #0]
+ __ strh(r10, Address(r17, r30, Address::lsl(0))); // strh w10, [x17, x30, lsl #0]
+ __ ldr(r27, Address(r11, r7, Address::uxtw(0))); // ldr x27, [x11, w7, uxtw #0]
+ __ ldrw(r14, Address(r15, r25, Address::uxtw(0))); // ldr w14, [x15, w25, uxtw #0]
+ __ ldrb(r24, Address(r14, r19, Address::lsl(0))); // ldrb w24, [x14, x19, lsl #0]
+ __ ldrh(r16, Address(r0, r6, Address::sxtw(0))); // ldrh w16, [x0, w6, sxtw #0]
+ __ ldrsb(r10, Address(r12, r12, Address::sxtw(0))); // ldrsb x10, [x12, w12, sxtw #0]
+ __ ldrsh(r26, Address(r12, r16, Address::uxtw(0))); // ldrsh x26, [x12, w16, uxtw #0]
+ __ ldrshw(r26, Address(r0, r14, Address::lsl(1))); // ldrsh w26, [x0, x14, lsl #1]
+ __ ldrsw(r17, Address(r11, r27, Address::sxtx(2))); // ldrsw x17, [x11, x27, sxtx #2]
+ __ ldrd(v3, Address(r0, r19, Address::sxtw(3))); // ldr d3, [x0, w19, sxtw #3]
+ __ ldrs(v26, Address(r15, r9, Address::lsl(2))); // ldr s26, [x15, x9, lsl #2]
+ __ strd(v11, Address(r13, r16, Address::sxtx(0))); // str d11, [x13, x16, sxtx #0]
+ __ strs(v26, Address(r19, r21, Address::uxtw(2))); // str s26, [x19, w21, uxtw #2]
// base_plus_scaled_offset
// LoadStoreOp
- __ str(r30, Address(r7, 16256)); // str x30, [x7, 16256]
- __ strw(r15, Address(r8, 7588)); // str w15, [x8, 7588]
- __ strb(r11, Address(r0, 1866)); // strb w11, [x0, 1866]
- __ strh(r3, Address(r17, 3734)); // strh w3, [x17, 3734]
- __ ldr(r2, Address(r7, 14224)); // ldr x2, [x7, 14224]
- __ ldrw(r5, Address(r9, 7396)); // ldr w5, [x9, 7396]
- __ ldrb(r28, Address(r9, 1721)); // ldrb w28, [x9, 1721]
- __ ldrh(r2, Address(r20, 3656)); // ldrh w2, [x20, 3656]
- __ ldrsb(r22, Address(r14, 1887)); // ldrsb x22, [x14, 1887]
- __ ldrsh(r8, Address(r0, 4080)); // ldrsh x8, [x0, 4080]
- __ ldrshw(r0, Address(r30, 3916)); // ldrsh w0, [x30, 3916]
- __ ldrsw(r24, Address(r19, 6828)); // ldrsw x24, [x19, 6828]
- __ ldrd(v24, Address(r12, 13032)); // ldr d24, [x12, 13032]
- __ ldrs(v8, Address(r8, 7452)); // ldr s8, [x8, 7452]
- __ strd(v10, Address(r15, 15992)); // str d10, [x15, 15992]
- __ strs(v26, Address(r19, 6688)); // str s26, [x19, 6688]
+ __ str(r8, Address(r21, 12552)); // str x8, [x21, 12552]
+ __ strw(r10, Address(r27, 6380)); // str w10, [x27, 6380]
+ __ strb(r27, Address(r14, 1733)); // strb w27, [x14, 1733]
+ __ strh(r16, Address(r7, 3424)); // strh w16, [x7, 3424]
+ __ ldr(r27, Address(r9, 12520)); // ldr x27, [x9, 12520]
+ __ ldrw(r24, Address(r10, 6680)); // ldr w24, [x10, 6680]
+ __ ldrb(r24, Address(r24, 1743)); // ldrb w24, [x24, 1743]
+ __ ldrh(r20, Address(r5, 3072)); // ldrh w20, [x5, 3072]
+ __ ldrsb(r17, Address(r4, 1570)); // ldrsb x17, [x4, 1570]
+ __ ldrsh(r14, Address(r13, 3392)); // ldrsh x14, [x13, 3392]
+ __ ldrshw(r10, Address(r25, 3722)); // ldrsh w10, [x25, 3722]
+ __ ldrsw(r2, Address(r26, 6160)); // ldrsw x2, [x26, 6160]
+ __ ldrd(v26, Address(r14, 14912)); // ldr d26, [x14, 14912]
+ __ ldrs(v28, Address(r4, 7804)); // ldr s28, [x4, 7804]
+ __ strd(v14, Address(r19, 13984)); // str d14, [x19, 13984]
+ __ strs(v23, Address(r28, 6364)); // str s23, [x28, 6364]
// pcrel
// LoadStoreOp
- __ ldr(r10, forth); // ldr x10, forth
- __ ldrw(r3, __ pc()); // ldr w3, .
+ __ ldr(r8, forth); // ldr x8, forth
+ __ ldrw(r17, back); // ldr w17, back
// LoadStoreOp
- __ prfm(Address(r23, 9)); // prfm PLDL1KEEP, [x23, 9]
+ __ prfm(Address(r4, -175)); // prfm PLDL1KEEP, [x4, -175]
// LoadStoreOp
- __ prfm(back); // prfm PLDL1KEEP, back
+ __ prfm(__ pc()); // prfm PLDL1KEEP, .
// LoadStoreOp
- __ prfm(Address(r3, r8, Address::uxtw(0))); // prfm PLDL1KEEP, [x3, w8, uxtw #0]
+ __ prfm(Address(r8, r4, Address::sxtw(0))); // prfm PLDL1KEEP, [x8, w4, sxtw #0]
// LoadStoreOp
- __ prfm(Address(r11, 15080)); // prfm PLDL1KEEP, [x11, 15080]
+ __ prfm(Address(r12, 13248)); // prfm PLDL1KEEP, [x12, 13248]
// AddSubCarryOp
- __ adcw(r13, r9, r28); // adc w13, w9, w28
- __ adcsw(r27, r19, r28); // adcs w27, w19, w28
- __ sbcw(r19, r18, r6); // sbc w19, w18, w6
- __ sbcsw(r14, r20, r3); // sbcs w14, w20, w3
- __ adc(r16, r14, r8); // adc x16, x14, x8
- __ adcs(r0, r29, r8); // adcs x0, x29, x8
- __ sbc(r8, r24, r20); // sbc x8, x24, x20
- __ sbcs(r12, r28, r0); // sbcs x12, x28, x0
+ __ adcw(r20, r27, r21); // adc w20, w27, w21
+ __ adcsw(r7, r17, r6); // adcs w7, w17, w6
+ __ sbcw(r5, r6, r25); // sbc w5, w6, w25
+ __ sbcsw(r30, r11, r14); // sbcs w30, w11, w14
+ __ adc(r3, r17, r11); // adc x3, x17, x11
+ __ adcs(r25, r10, r17); // adcs x25, x10, x17
+ __ sbc(r7, r16, r23); // sbc x7, x16, x23
+ __ sbcs(r4, r10, r5); // sbcs x4, x10, x5
// AddSubExtendedOp
- __ addw(r23, r6, r16, ext::uxtb, 4); // add w23, w6, w16, uxtb #4
- __ addsw(r25, r25, r23, ext::sxth, 2); // adds w25, w25, w23, sxth #2
- __ sub(r26, r22, r4, ext::uxtx, 1); // sub x26, x22, x4, uxtx #1
- __ subsw(r17, r29, r19, ext::sxtx, 3); // subs w17, w29, w19, sxtx #3
- __ add(r11, r30, r21, ext::uxtb, 3); // add x11, x30, x21, uxtb #3
- __ adds(r16, r19, r0, ext::sxtb, 2); // adds x16, x19, x0, sxtb #2
- __ sub(r11, r9, r25, ext::sxtx, 1); // sub x11, x9, x25, sxtx #1
- __ subs(r17, r20, r12, ext::sxtb, 4); // subs x17, x20, x12, sxtb #4
+ __ addw(r9, r30, r9, ext::uxtx, 4); // add w9, w30, w9, uxtx #4
+ __ addsw(r0, r5, r16, ext::sxth, 2); // adds w0, w5, w16, sxth #2
+ __ sub(r15, r29, r27, ext::sxtb, 2); // sub x15, x29, x27, sxtb #2
+ __ subsw(r11, r9, r1, ext::sxtx, 4); // subs w11, w9, w1, sxtx #4
+ __ add(r2, r24, r6, ext::uxtw, 3); // add x2, x24, x6, uxtw #3
+ __ adds(r19, r6, r26, ext::uxtx, 4); // adds x19, x6, x26, uxtx #4
+ __ sub(r8, r26, r25, ext::sxtx, 3); // sub x8, x26, x25, sxtx #3
+ __ subs(r26, r20, r9, ext::uxth, 4); // subs x26, x20, x9, uxth #4
// ConditionalCompareOp
- __ ccmnw(r13, r11, 3u, Assembler::LE); // ccmn w13, w11, #3, LE
- __ ccmpw(r13, r12, 2u, Assembler::HI); // ccmp w13, w12, #2, HI
- __ ccmn(r3, r2, 12u, Assembler::NE); // ccmn x3, x2, #12, NE
- __ ccmp(r7, r21, 3u, Assembler::VS); // ccmp x7, x21, #3, VS
+ __ ccmnw(r13, r26, 7u, Assembler::MI); // ccmn w13, w26, #7, MI
+ __ ccmpw(r8, r20, 15u, Assembler::LO); // ccmp w8, w20, #15, LO
+ __ ccmn(r22, r3, 8u, Assembler::EQ); // ccmn x22, x3, #8, EQ
+ __ ccmp(r2, r24, 10u, Assembler::GE); // ccmp x2, x24, #10, GE
// ConditionalCompareImmedOp
- __ ccmnw(r2, 14, 4, Assembler::CC); // ccmn w2, #14, #4, CC
- __ ccmpw(r17, 17, 6, Assembler::PL); // ccmp w17, #17, #6, PL
- __ ccmn(r10, 12, 0, Assembler::CS); // ccmn x10, #12, #0, CS
- __ ccmp(r21, 18, 14, Assembler::GE); // ccmp x21, #18, #14, GE
+ __ ccmnw(r8, 16, 13, Assembler::MI); // ccmn w8, #16, #13, MI
+ __ ccmpw(r16, 12, 1, Assembler::EQ); // ccmp w16, #12, #1, EQ
+ __ ccmn(r15, 31, 3, Assembler::VC); // ccmn x15, #31, #3, VC
+ __ ccmp(r23, 12, 15, Assembler::EQ); // ccmp x23, #12, #15, EQ
// ConditionalSelectOp
- __ cselw(r21, r13, r12, Assembler::GT); // csel w21, w13, w12, GT
- __ csincw(r10, r27, r15, Assembler::LS); // csinc w10, w27, w15, LS
- __ csinvw(r0, r13, r9, Assembler::HI); // csinv w0, w13, w9, HI
- __ csnegw(r18, r4, r26, Assembler::VS); // csneg w18, w4, w26, VS
- __ csel(r12, r29, r7, Assembler::LS); // csel x12, x29, x7, LS
- __ csinc(r6, r7, r20, Assembler::VC); // csinc x6, x7, x20, VC
- __ csinv(r22, r21, r3, Assembler::LE); // csinv x22, x21, x3, LE
- __ csneg(r19, r12, r27, Assembler::LS); // csneg x19, x12, x27, LS
+ __ cselw(r14, r7, r26, Assembler::LO); // csel w14, w7, w26, LO
+ __ csincw(r3, r27, r30, Assembler::LE); // csinc w3, w27, w30, LE
+ __ csinvw(r11, r21, r23, Assembler::EQ); // csinv w11, w21, w23, EQ
+ __ csnegw(r26, r30, r21, Assembler::GT); // csneg w26, w30, w21, GT
+ __ csel(r28, r26, r13, Assembler::HI); // csel x28, x26, x13, HI
+ __ csinc(r17, r3, r16, Assembler::LS); // csinc x17, x3, x16, LS
+ __ csinv(r11, r5, r3, Assembler::HI); // csinv x11, x5, x3, HI
+ __ csneg(r1, r3, r19, Assembler::GT); // csneg x1, x3, x19, GT
// TwoRegOp
- __ rbitw(r0, r16); // rbit w0, w16
- __ rev16w(r17, r23); // rev16 w17, w23
- __ revw(r17, r14); // rev w17, w14
- __ clzw(r24, r30); // clz w24, w30
- __ clsw(r24, r22); // cls w24, w22
- __ rbit(r3, r17); // rbit x3, x17
- __ rev16(r12, r13); // rev16 x12, x13
- __ rev32(r9, r22); // rev32 x9, x22
- __ rev(r0, r0); // rev x0, x0
- __ clz(r5, r16); // clz x5, x16
- __ cls(r25, r22); // cls x25, x22
+ __ rbitw(r0, r9); // rbit w0, w9
+ __ rev16w(r26, r14); // rev16 w26, w14
+ __ revw(r13, r17); // rev w13, w17
+ __ clzw(r11, r20); // clz w11, w20
+ __ clsw(r28, r17); // cls w28, w17
+ __ rbit(r13, r4); // rbit x13, x4
+ __ rev16(r1, r30); // rev16 x1, x30
+ __ rev32(r13, r14); // rev32 x13, x14
+ __ rev(r5, r8); // rev x5, x8
+ __ clz(r2, r25); // clz x2, x25
+ __ cls(r20, r8); // cls x20, x8
// ThreeRegOp
- __ udivw(r29, r4, r0); // udiv w29, w4, w0
- __ sdivw(r0, r29, r29); // sdiv w0, w29, w29
- __ lslvw(r5, r17, r21); // lslv w5, w17, w21
- __ lsrvw(r9, r9, r18); // lsrv w9, w9, w18
- __ asrvw(r1, r27, r8); // asrv w1, w27, w8
- __ rorvw(r18, r20, r13); // rorv w18, w20, w13
- __ udiv(r8, r25, r12); // udiv x8, x25, x12
- __ sdiv(r7, r5, r28); // sdiv x7, x5, x28
- __ lslv(r5, r17, r27); // lslv x5, x17, x27
- __ lsrv(r23, r26, r20); // lsrv x23, x26, x20
- __ asrv(r28, r8, r28); // asrv x28, x8, x28
- __ rorv(r3, r29, r4); // rorv x3, x29, x4
+ __ udivw(r21, r25, r27); // udiv w21, w25, w27
+ __ sdivw(r13, r10, r16); // sdiv w13, w10, w16
+ __ lslvw(r28, r1, r17); // lslv w28, w1, w17
+ __ lsrvw(r25, r23, r10); // lsrv w25, w23, w10
+ __ asrvw(r7, r3, r7); // asrv w7, w3, w7
+ __ rorvw(r14, r30, r14); // rorv w14, w30, w14
+ __ udiv(r12, r22, r15); // udiv x12, x22, x15
+ __ sdiv(r2, r25, r13); // sdiv x2, x25, x13
+ __ lslv(r7, r23, r21); // lslv x7, x23, x21
+ __ lsrv(r11, r12, r0); // lsrv x11, x12, x0
+ __ asrv(r30, r9, r28); // asrv x30, x9, x28
+ __ rorv(r13, r5, r22); // rorv x13, x5, x22
+ __ umulh(r5, r21, r4); // umulh x5, x21, x4
+ __ smulh(r17, r2, r7); // smulh x17, x2, x7
// FourRegMulOp
- __ maddw(r17, r14, r26, r21); // madd w17, w14, w26, w21
- __ msubw(r1, r30, r11, r11); // msub w1, w30, w11, w11
- __ madd(r1, r17, r6, r28); // madd x1, x17, x6, x28
- __ msub(r30, r6, r30, r8); // msub x30, x6, x30, x8
- __ smaddl(r21, r6, r14, r8); // smaddl x21, w6, w14, x8
- __ smsubl(r10, r10, r24, r19); // smsubl x10, w10, w24, x19
- __ umaddl(r20, r18, r14, r24); // umaddl x20, w18, w14, x24
- __ umsubl(r18, r2, r5, r5); // umsubl x18, w2, w5, x5
+ __ maddw(r12, r12, r17, r12); // madd w12, w12, w17, w12
+ __ msubw(r30, r15, r1, r27); // msub w30, w15, w1, w27
+ __ madd(r2, r19, r17, r29); // madd x2, x19, x17, x29
+ __ msub(r4, r23, r3, r30); // msub x4, x23, x3, x30
+ __ smaddl(r15, r23, r17, r15); // smaddl x15, w23, w17, x15
+ __ smsubl(r27, r12, r1, r13); // smsubl x27, w12, w1, x13
+ __ umaddl(r6, r13, r12, r17); // umaddl x6, w13, w12, x17
+ __ umsubl(r25, r1, r6, r10); // umsubl x25, w1, w6, x10
// ThreeRegFloatOp
- __ fmuls(v8, v18, v13); // fmul s8, s18, s13
- __ fdivs(v2, v14, v28); // fdiv s2, s14, s28
- __ fadds(v15, v12, v28); // fadd s15, s12, s28
- __ fsubs(v0, v12, v1); // fsub s0, s12, s1
- __ fmuls(v15, v29, v4); // fmul s15, s29, s4
- __ fmuld(v12, v1, v23); // fmul d12, d1, d23
- __ fdivd(v27, v8, v18); // fdiv d27, d8, d18
- __ faddd(v23, v20, v11); // fadd d23, d20, d11
- __ fsubd(v8, v12, v18); // fsub d8, d12, d18
- __ fmuld(v26, v24, v23); // fmul d26, d24, d23
+ __ fmuls(v17, v3, v4); // fmul s17, s3, s4
+ __ fdivs(v16, v5, v21); // fdiv s16, s5, s21
+ __ fadds(v3, v27, v17); // fadd s3, s27, s17
+ __ fsubs(v25, v10, v15); // fsub s25, s10, s15
+ __ fmuls(v10, v17, v0); // fmul s10, s17, s0
+ __ fmuld(v28, v26, v3); // fmul d28, d26, d3
+ __ fdivd(v4, v0, v27); // fdiv d4, d0, d27
+ __ faddd(v28, v14, v2); // fadd d28, d14, d2
+ __ fsubd(v12, v26, v23); // fsub d12, d26, d23
+ __ fmuld(v15, v30, v1); // fmul d15, d30, d1
// FourRegFloatOp
- __ fmadds(v21, v23, v13, v25); // fmadd s21, s23, s13, s25
- __ fmsubs(v22, v10, v1, v14); // fmsub s22, s10, s1, s14
- __ fnmadds(v14, v20, v2, v30); // fnmadd s14, s20, s2, s30
- __ fnmadds(v7, v29, v22, v22); // fnmadd s7, s29, s22, s22
- __ fmaddd(v13, v5, v15, v5); // fmadd d13, d5, d15, d5
- __ fmsubd(v14, v12, v5, v10); // fmsub d14, d12, d5, d10
- __ fnmaddd(v10, v19, v0, v1); // fnmadd d10, d19, d0, d1
- __ fnmaddd(v20, v2, v2, v0); // fnmadd d20, d2, d2, d0
+ __ fmadds(v4, v5, v5, v13); // fmadd s4, s5, s5, s13
+ __ fmsubs(v21, v13, v28, v1); // fmsub s21, s13, s28, s1
+ __ fnmadds(v17, v3, v29, v7); // fnmadd s17, s3, s29, s7
+ __ fnmadds(v23, v25, v29, v26); // fnmadd s23, s25, s29, s26
+ __ fmaddd(v14, v7, v30, v26); // fmadd d14, d7, d30, d26
+ __ fmsubd(v22, v7, v10, v9); // fmsub d22, d7, d10, d9
+ __ fnmaddd(v7, v7, v14, v9); // fnmadd d7, d7, d14, d9
+ __ fnmaddd(v14, v24, v15, v24); // fnmadd d14, d24, d15, d24
// TwoRegFloatOp
- __ fmovs(v25, v9); // fmov s25, s9
- __ fabss(v20, v4); // fabs s20, s4
- __ fnegs(v3, v27); // fneg s3, s27
- __ fsqrts(v1, v2); // fsqrt s1, s2
- __ fcvts(v30, v0); // fcvt d30, s0
- __ fmovd(v12, v4); // fmov d12, d4
- __ fabsd(v1, v27); // fabs d1, d27
- __ fnegd(v8, v22); // fneg d8, d22
- __ fsqrtd(v11, v11); // fsqrt d11, d11
- __ fcvtd(v22, v28); // fcvt s22, d28
+ __ fmovs(v22, v2); // fmov s22, s2
+ __ fabss(v0, v3); // fabs s0, s3
+ __ fnegs(v9, v17); // fneg s9, s17
+ __ fsqrts(v24, v11); // fsqrt s24, s11
+ __ fcvts(v15, v25); // fcvt d15, s25
+ __ fmovd(v4, v3); // fmov d4, d3
+ __ fabsd(v26, v22); // fabs d26, d22
+ __ fnegd(v30, v19); // fneg d30, d19
+ __ fsqrtd(v12, v14); // fsqrt d12, d14
+ __ fcvtd(v17, v7); // fcvt s17, d7
// FloatConvertOp
- __ fcvtzsw(r28, v22); // fcvtzs w28, s22
- __ fcvtzs(r20, v27); // fcvtzs x20, s27
- __ fcvtzdw(r14, v0); // fcvtzs w14, d0
- __ fcvtzd(r26, v11); // fcvtzs x26, d11
- __ scvtfws(v28, r22); // scvtf s28, w22
- __ scvtfs(v16, r10); // scvtf s16, x10
- __ scvtfwd(v8, r21); // scvtf d8, w21
- __ scvtfd(v21, r28); // scvtf d21, x28
- __ fmovs(r24, v24); // fmov w24, s24
- __ fmovd(r8, v19); // fmov x8, d19
- __ fmovs(v8, r12); // fmov s8, w12
- __ fmovd(v6, r7); // fmov d6, x7
+ __ fcvtzsw(r24, v14); // fcvtzs w24, s14
+ __ fcvtzs(r13, v26); // fcvtzs x13, s26
+ __ fcvtzdw(r2, v1); // fcvtzs w2, d1
+ __ fcvtzd(r5, v11); // fcvtzs x5, d11
+ __ scvtfws(v14, r19); // scvtf s14, w19
+ __ scvtfs(v1, r22); // scvtf s1, x22
+ __ scvtfwd(v27, r17); // scvtf d27, w17
+ __ scvtfd(v22, r9); // scvtf d22, x9
+ __ fmovs(r14, v3); // fmov w14, s3
+ __ fmovd(r12, v17); // fmov x12, d17
+ __ fmovs(v8, r27); // fmov s8, w27
+ __ fmovd(v29, r28); // fmov d29, x28
// TwoRegFloatOp
- __ fcmps(v30, v16); // fcmp s30, s16
- __ fcmpd(v25, v11); // fcmp d25, d11
- __ fcmps(v11, 0.0); // fcmp s11, #0.0
- __ fcmpd(v11, 0.0); // fcmp d11, #0.0
+ __ fcmps(v0, v30); // fcmp s0, s30
+ __ fcmpd(v12, v9); // fcmp d12, d9
+ __ fcmps(v10, 0.0); // fcmp s10, #0.0
+ __ fcmpd(v25, 0.0); // fcmp d25, #0.0
// LoadStorePairOp
- __ stpw(r29, r12, Address(r17, 128)); // stp w29, w12, [x17, #128]
- __ ldpw(r22, r18, Address(r14, -96)); // ldp w22, w18, [x14, #-96]
- __ ldpsw(r11, r16, Address(r1, 64)); // ldpsw x11, x16, [x1, #64]
- __ stp(r0, r11, Address(r26, 112)); // stp x0, x11, [x26, #112]
- __ ldp(r7, r1, Address(r26, 16)); // ldp x7, x1, [x26, #16]
+ __ stpw(r8, r30, Address(r27, -144)); // stp w8, w30, [x27, #-144]
+ __ ldpw(r21, r19, Address(r24, 80)); // ldp w21, w19, [x24, #80]
+ __ ldpsw(r16, r27, Address(r2, -240)); // ldpsw x16, x27, [x2, #-240]
+ __ stp(r21, r5, Address(r6, -128)); // stp x21, x5, [x6, #-128]
+ __ ldp(r29, r25, Address(r28, -32)); // ldp x29, x25, [x28, #-32]
// LoadStorePairOp
- __ stpw(r10, r7, Address(__ pre(r24, 0))); // stp w10, w7, [x24, #0]!
- __ ldpw(r7, r28, Address(__ pre(r24, -256))); // ldp w7, w28, [x24, #-256]!
- __ ldpsw(r25, r28, Address(__ pre(r21, -240))); // ldpsw x25, x28, [x21, #-240]!
- __ stp(r20, r18, Address(__ pre(r14, -16))); // stp x20, x18, [x14, #-16]!
- __ ldp(r8, r10, Address(__ pre(r13, 80))); // ldp x8, x10, [x13, #80]!
+ __ stpw(r8, r13, Address(__ pre(r0, 128))); // stp w8, w13, [x0, #128]!
+ __ ldpw(r25, r20, Address(__ pre(r1, -160))); // ldp w25, w20, [x1, #-160]!
+ __ ldpsw(r14, r24, Address(__ pre(r22, -32))); // ldpsw x14, x24, [x22, #-32]!
+ __ stp(r17, r1, Address(__ pre(r6, 80))); // stp x17, x1, [x6, #80]!
+ __ ldp(r21, r17, Address(__ pre(r25, -64))); // ldp x21, x17, [x25, #-64]!
// LoadStorePairOp
- __ stpw(r26, r24, Address(__ post(r2, -128))); // stp w26, w24, [x2], #-128
- __ ldpw(r2, r25, Address(__ post(r21, -192))); // ldp w2, w25, [x21], #-192
- __ ldpsw(r17, r2, Address(__ post(r21, -144))); // ldpsw x17, x2, [x21], #-144
- __ stp(r12, r10, Address(__ post(r11, 96))); // stp x12, x10, [x11], #96
- __ ldp(r24, r6, Address(__ post(r17, -32))); // ldp x24, x6, [x17], #-32
+ __ stpw(r17, r21, Address(__ post(r20, -128))); // stp w17, w21, [x20], #-128
+ __ ldpw(r28, r28, Address(__ post(r2, 64))); // ldp w28, w28, [x2], #64
+ __ ldpsw(r19, r30, Address(__ post(r10, -256))); // ldpsw x19, x30, [x10], #-256
+ __ stp(r17, r15, Address(__ post(r17, -16))); // stp x17, x15, [x17], #-16
+ __ ldp(r17, r0, Address(__ post(r25, -32))); // ldp x17, x0, [x25], #-32
// LoadStorePairOp
- __ stnpw(r3, r30, Address(r14, -224)); // stnp w3, w30, [x14, #-224]
- __ ldnpw(r15, r20, Address(r26, -144)); // ldnp w15, w20, [x26, #-144]
- __ stnp(r22, r25, Address(r12, -128)); // stnp x22, x25, [x12, #-128]
- __ ldnp(r27, r22, Address(r17, -176)); // ldnp x27, x22, [x17, #-176]
+ __ stnpw(r14, r5, Address(r24, -32)); // stnp w14, w5, [x24, #-32]
+ __ ldnpw(r23, r19, Address(r1, 112)); // ldnp w23, w19, [x1, #112]
+ __ stnp(r11, r6, Address(r14, 64)); // stnp x11, x6, [x14, #64]
+ __ ldnp(r2, r11, Address(r27, -224)); // ldnp x2, x11, [x27, #-224]
+
+// LdStSIMDOp
+ __ ld1(v16, __ T8B, Address(r17)); // ld1 {v16.8B}, [x17]
+ __ ld1(v29, v30, __ T16B, Address(__ post(r9, 32))); // ld1 {v29.16B, v30.16B}, [x9], 32
+ __ ld1(v30, v31, v0, __ T1D, Address(__ post(r24, r21))); // ld1 {v30.1D, v31.1D, v0.1D}, [x24], x21
+ __ ld1(v0, v1, v2, v3, __ T8H, Address(__ post(r2, 64))); // ld1 {v0.8H, v1.8H, v2.8H, v3.8H}, [x2], 64
+ __ ld1r(v20, __ T8B, Address(r9)); // ld1r {v20.8B}, [x9]
+ __ ld1r(v17, __ T4S, Address(__ post(r0, 4))); // ld1r {v17.4S}, [x0], 4
+ __ ld1r(v21, __ T1D, Address(__ post(r22, r26))); // ld1r {v21.1D}, [x22], x26
+ __ ld2(v19, v20, __ T2D, Address(r25)); // ld2 {v19.2D, v20.2D}, [x25]
+ __ ld2(v10, v11, __ T4H, Address(__ post(r5, 16))); // ld2 {v10.4H, v11.4H}, [x5], 16
+ __ ld2r(v10, v11, __ T16B, Address(r24)); // ld2r {v10.16B, v11.16B}, [x24]
+ __ ld2r(v13, v14, __ T2S, Address(__ post(r29, 8))); // ld2r {v13.2S, v14.2S}, [x29], 8
+ __ ld2r(v22, v23, __ T2D, Address(__ post(r28, r2))); // ld2r {v22.2D, v23.2D}, [x28], x2
+ __ ld3(v30, v31, v0, __ T4S, Address(__ post(r4, r11))); // ld3 {v30.4S, v31.4S, v0.4S}, [x4], x11
+ __ ld3(v29, v30, v31, __ T2S, Address(r0)); // ld3 {v29.2S, v30.2S, v31.2S}, [x0]
+ __ ld3r(v23, v24, v25, __ T8H, Address(r27)); // ld3r {v23.8H, v24.8H, v25.8H}, [x27]
+ __ ld3r(v3, v4, v5, __ T4S, Address(__ post(r10, 12))); // ld3r {v3.4S, v4.4S, v5.4S}, [x10], 12
+ __ ld3r(v19, v20, v21, __ T1D, Address(__ post(r14, r22))); // ld3r {v19.1D, v20.1D, v21.1D}, [x14], x22
+ __ ld4(v14, v15, v16, v17, __ T8H, Address(__ post(r0, 64))); // ld4 {v14.8H, v15.8H, v16.8H, v17.8H}, [x0], 64
+ __ ld4(v30, v31, v0, v1, __ T8B, Address(__ post(r22, r25))); // ld4 {v30.8B, v31.8B, v0.8B, v1.8B}, [x22], x25
+ __ ld4r(v25, v26, v27, v28, __ T8B, Address(r0)); // ld4r {v25.8B, v26.8B, v27.8B, v28.8B}, [x0]
+ __ ld4r(v10, v11, v12, v13, __ T4H, Address(__ post(r8, 8))); // ld4r {v10.4H, v11.4H, v12.4H, v13.4H}, [x8], 8
+ __ ld4r(v1, v2, v3, v4, __ T2S, Address(__ post(r6, r28))); // ld4r {v1.2S, v2.2S, v3.2S, v4.2S}, [x6], x28
+
+// SpecialCases
+ __ ccmn(zr, zr, 3u, Assembler::LE); // ccmn xzr, xzr, #3, LE
+ __ ccmnw(zr, zr, 5u, Assembler::EQ); // ccmn wzr, wzr, #5, EQ
+ __ ccmp(zr, 1, 4u, Assembler::NE); // ccmp xzr, 1, #4, NE
+ __ ccmpw(zr, 2, 2, Assembler::GT); // ccmp wzr, 2, #2, GT
+ __ extr(zr, zr, zr, 0); // extr xzr, xzr, xzr, 0
+ __ stlxp(r0, zr, zr, sp); // stlxp w0, xzr, xzr, [sp]
+ __ stlxpw(r2, zr, zr, r3); // stlxp w2, wzr, wzr, [x3]
+ __ stxp(r4, zr, zr, r5); // stxp w4, xzr, xzr, [x5]
+ __ stxpw(r6, zr, zr, sp); // stxp w6, wzr, wzr, [sp]
+ __ dup(v0, __ T16B, zr); // dup v0.16b, wzr
+ __ mov(v1, __ T1D, 0, zr); // mov v1.d[0], xzr
+ __ mov(v1, __ T2S, 1, zr); // mov v1.s[1], wzr
+ __ mov(v1, __ T4H, 2, zr); // mov v1.h[2], wzr
+ __ mov(v1, __ T8B, 3, zr); // mov v1.b[3], wzr
+ __ ld1(v31, v0, __ T2D, Address(__ post(r1, r0))); // ld1 {v31.2d, v0.2d}, [x1], x0
// FloatImmediateOp
- __ fmovd(v0, 2.0); // fmov d0, #2.0
- __ fmovd(v0, 2.125); // fmov d0, #2.125
- __ fmovd(v0, 4.0); // fmov d0, #4.0
- __ fmovd(v0, 4.25); // fmov d0, #4.25
- __ fmovd(v0, 8.0); // fmov d0, #8.0
- __ fmovd(v0, 8.5); // fmov d0, #8.5
- __ fmovd(v0, 16.0); // fmov d0, #16.0
- __ fmovd(v0, 17.0); // fmov d0, #17.0
- __ fmovd(v0, 0.125); // fmov d0, #0.125
- __ fmovd(v0, 0.1328125); // fmov d0, #0.1328125
- __ fmovd(v0, 0.25); // fmov d0, #0.25
- __ fmovd(v0, 0.265625); // fmov d0, #0.265625
- __ fmovd(v0, 0.5); // fmov d0, #0.5
- __ fmovd(v0, 0.53125); // fmov d0, #0.53125
- __ fmovd(v0, 1.0); // fmov d0, #1.0
- __ fmovd(v0, 1.0625); // fmov d0, #1.0625
- __ fmovd(v0, -2.0); // fmov d0, #-2.0
- __ fmovd(v0, -2.125); // fmov d0, #-2.125
- __ fmovd(v0, -4.0); // fmov d0, #-4.0
- __ fmovd(v0, -4.25); // fmov d0, #-4.25
- __ fmovd(v0, -8.0); // fmov d0, #-8.0
- __ fmovd(v0, -8.5); // fmov d0, #-8.5
- __ fmovd(v0, -16.0); // fmov d0, #-16.0
- __ fmovd(v0, -17.0); // fmov d0, #-17.0
- __ fmovd(v0, -0.125); // fmov d0, #-0.125
- __ fmovd(v0, -0.1328125); // fmov d0, #-0.1328125
- __ fmovd(v0, -0.25); // fmov d0, #-0.25
- __ fmovd(v0, -0.265625); // fmov d0, #-0.265625
- __ fmovd(v0, -0.5); // fmov d0, #-0.5
- __ fmovd(v0, -0.53125); // fmov d0, #-0.53125
- __ fmovd(v0, -1.0); // fmov d0, #-1.0
- __ fmovd(v0, -1.0625); // fmov d0, #-1.0625
+ __ fmovd(v0, 2.0); // fmov d0, #2.0
+ __ fmovd(v0, 2.125); // fmov d0, #2.125
+ __ fmovd(v0, 4.0); // fmov d0, #4.0
+ __ fmovd(v0, 4.25); // fmov d0, #4.25
+ __ fmovd(v0, 8.0); // fmov d0, #8.0
+ __ fmovd(v0, 8.5); // fmov d0, #8.5
+ __ fmovd(v0, 16.0); // fmov d0, #16.0
+ __ fmovd(v0, 17.0); // fmov d0, #17.0
+ __ fmovd(v0, 0.125); // fmov d0, #0.125
+ __ fmovd(v0, 0.1328125); // fmov d0, #0.1328125
+ __ fmovd(v0, 0.25); // fmov d0, #0.25
+ __ fmovd(v0, 0.265625); // fmov d0, #0.265625
+ __ fmovd(v0, 0.5); // fmov d0, #0.5
+ __ fmovd(v0, 0.53125); // fmov d0, #0.53125
+ __ fmovd(v0, 1.0); // fmov d0, #1.0
+ __ fmovd(v0, 1.0625); // fmov d0, #1.0625
+ __ fmovd(v0, -2.0); // fmov d0, #-2.0
+ __ fmovd(v0, -2.125); // fmov d0, #-2.125
+ __ fmovd(v0, -4.0); // fmov d0, #-4.0
+ __ fmovd(v0, -4.25); // fmov d0, #-4.25
+ __ fmovd(v0, -8.0); // fmov d0, #-8.0
+ __ fmovd(v0, -8.5); // fmov d0, #-8.5
+ __ fmovd(v0, -16.0); // fmov d0, #-16.0
+ __ fmovd(v0, -17.0); // fmov d0, #-17.0
+ __ fmovd(v0, -0.125); // fmov d0, #-0.125
+ __ fmovd(v0, -0.1328125); // fmov d0, #-0.1328125
+ __ fmovd(v0, -0.25); // fmov d0, #-0.25
+ __ fmovd(v0, -0.265625); // fmov d0, #-0.265625
+ __ fmovd(v0, -0.5); // fmov d0, #-0.5
+ __ fmovd(v0, -0.53125); // fmov d0, #-0.53125
+ __ fmovd(v0, -1.0); // fmov d0, #-1.0
+ __ fmovd(v0, -1.0625); // fmov d0, #-1.0625
+
+// LSEOp
+ __ swp(Assembler::xword, r16, r20, r15); // swp x16, x20, [x15]
+ __ ldadd(Assembler::xword, r2, r7, r28); // ldadd x2, x7, [x28]
+ __ ldbic(Assembler::xword, r20, r10, r25); // ldclr x20, x10, [x25]
+ __ ldeor(Assembler::xword, r22, r11, r2); // ldeor x22, x11, [x2]
+ __ ldorr(Assembler::xword, r1, r10, r19); // ldset x1, x10, [x19]
+ __ ldsmin(Assembler::xword, r14, r21, r3); // ldsmin x14, x21, [x3]
+ __ ldsmax(Assembler::xword, r28, r27, r13); // ldsmax x28, x27, [x13]
+ __ ldumin(Assembler::xword, r17, r30, r21); // ldumin x17, x30, [x21]
+ __ ldumax(Assembler::xword, r27, r16, r29); // ldumax x27, x16, [x29]
+
+// LSEOp
+ __ swpa(Assembler::xword, r30, r9, r0); // swpa x30, x9, [x0]
+ __ ldadda(Assembler::xword, r28, r27, r28); // ldadda x28, x27, [x28]
+ __ ldbica(Assembler::xword, r21, r25, r10); // ldclra x21, x25, [x10]
+ __ ldeora(Assembler::xword, zr, r20, r15); // ldeora xzr, x20, [x15]
+ __ ldorra(Assembler::xword, r1, r25, r14); // ldseta x1, x25, [x14]
+ __ ldsmina(Assembler::xword, r21, r26, r29); // ldsmina x21, x26, [x29]
+ __ ldsmaxa(Assembler::xword, r8, r29, r25); // ldsmaxa x8, x29, [x25]
+ __ ldumina(Assembler::xword, r13, r2, r25); // ldumina x13, x2, [x25]
+ __ ldumaxa(Assembler::xword, r15, r23, r0); // ldumaxa x15, x23, [x0]
+
+// LSEOp
+ __ swpal(Assembler::xword, r3, r1, r2); // swpal x3, x1, [x2]
+ __ ldaddal(Assembler::xword, r28, r3, r20); // ldaddal x28, x3, [x20]
+ __ ldbical(Assembler::xword, r14, zr, r14); // ldclral x14, xzr, [x14]
+ __ ldeoral(Assembler::xword, r7, r28, r2); // ldeoral x7, x28, [x2]
+ __ ldorral(Assembler::xword, r0, r11, r5); // ldsetal x0, x11, [x5]
+ __ ldsminal(Assembler::xword, r11, r14, r20); // ldsminal x11, x14, [x20]
+ __ ldsmaxal(Assembler::xword, zr, r4, r2); // ldsmaxal xzr, x4, [x2]
+ __ lduminal(Assembler::xword, r26, r0, r22); // lduminal x26, x0, [x22]
+ __ ldumaxal(Assembler::xword, r17, r1, r13); // ldumaxal x17, x1, [x13]
+
+// LSEOp
+ __ swpl(Assembler::xword, r23, r26, r20); // swpl x23, x26, [x20]
+ __ ldaddl(Assembler::xword, r14, r11, r12); // ldaddl x14, x11, [x12]
+ __ ldbicl(Assembler::xword, r12, zr, r15); // ldclrl x12, xzr, [x15]
+ __ ldeorl(Assembler::xword, r27, r14, r8); // ldeorl x27, x14, [x8]
+ __ ldorrl(Assembler::xword, r10, r30, r25); // ldsetl x10, x30, [x25]
+ __ ldsminl(Assembler::xword, r22, r7, r16); // ldsminl x22, x7, [x16]
+ __ ldsmaxl(Assembler::xword, r1, r16, r8); // ldsmaxl x1, x16, [x8]
+ __ lduminl(Assembler::xword, r1, r1, r26); // lduminl x1, x1, [x26]
+ __ ldumaxl(Assembler::xword, r0, r23, r15); // ldumaxl x0, x23, [x15]
+
+// LSEOp
+ __ swp(Assembler::word, r11, r16, r8); // swp w11, w16, [x8]
+ __ ldadd(Assembler::word, r1, r7, r14); // ldadd w1, w7, [x14]
+ __ ldbic(Assembler::word, r16, zr, r9); // ldclr w16, wzr, [x9]
+ __ ldeor(Assembler::word, r22, r6, r13); // ldeor w22, w6, [x13]
+ __ ldorr(Assembler::word, r11, r13, r4); // ldset w11, w13, [x4]
+ __ ldsmin(Assembler::word, r16, r22, r0); // ldsmin w16, w22, [x0]
+ __ ldsmax(Assembler::word, r28, zr, r10); // ldsmax w28, wzr, [x10]
+ __ ldumin(Assembler::word, r16, r5, r8); // ldumin w16, w5, [x8]
+ __ ldumax(Assembler::word, r26, r20, r15); // ldumax w26, w20, [x15]
+
+// LSEOp
+ __ swpa(Assembler::word, r27, r6, r16); // swpa w27, w6, [x16]
+ __ ldadda(Assembler::word, zr, zr, r2); // ldadda wzr, wzr, [x2]
+ __ ldbica(Assembler::word, r24, r28, r8); // ldclra w24, w28, [x8]
+ __ ldeora(Assembler::word, r15, r9, r23); // ldeora w15, w9, [x23]
+ __ ldorra(Assembler::word, r26, r2, r7); // ldseta w26, w2, [x7]
+ __ ldsmina(Assembler::word, r3, r17, r15); // ldsmina w3, w17, [x15]
+ __ ldsmaxa(Assembler::word, r19, r5, r21); // ldsmaxa w19, w5, [x21]
+ __ ldumina(Assembler::word, r7, r26, r12); // ldumina w7, w26, [x12]
+ __ ldumaxa(Assembler::word, r12, r7, r29); // ldumaxa w12, w7, [x29]
+
+// LSEOp
+ __ swpal(Assembler::word, r9, r8, r20); // swpal w9, w8, [x20]
+ __ ldaddal(Assembler::word, r8, zr, r30); // ldaddal w8, wzr, [x30]
+ __ ldbical(Assembler::word, r0, r6, r12); // ldclral w0, w6, [x12]
+ __ ldeoral(Assembler::word, r17, r23, r2); // ldeoral w17, w23, [x2]
+ __ ldorral(Assembler::word, r0, r30, r1); // ldsetal w0, w30, [x1]
+ __ ldsminal(Assembler::word, r22, r3, r15); // ldsminal w22, w3, [x15]
+ __ ldsmaxal(Assembler::word, r25, r21, r13); // ldsmaxal w25, w21, [x13]
+ __ lduminal(Assembler::word, r13, r24, r27); // lduminal w13, w24, [x27]
+ __ ldumaxal(Assembler::word, r20, r3, r11); // ldumaxal w20, w3, [x11]
+
+// LSEOp
+ __ swpl(Assembler::word, r3, r13, r21); // swpl w3, w13, [x21]
+ __ ldaddl(Assembler::word, r26, r15, r26); // ldaddl w26, w15, [x26]
+ __ ldbicl(Assembler::word, r9, r19, r2); // ldclrl w9, w19, [x2]
+ __ ldeorl(Assembler::word, r24, r29, r7); // ldeorl w24, w29, [x7]
+ __ ldorrl(Assembler::word, r29, r25, r15); // ldsetl w29, w25, [x15]
+ __ ldsminl(Assembler::word, r11, r30, r7); // ldsminl w11, w30, [x7]
+ __ ldsmaxl(Assembler::word, r11, r2, r6); // ldsmaxl w11, w2, [x6]
+ __ lduminl(Assembler::word, r16, r11, r14); // lduminl w16, w11, [x14]
+ __ ldumaxl(Assembler::word, r5, r8, r11); // ldumaxl w5, w8, [x11]
__ bind(forth);
@@ -631,542 +762,681 @@
Disassembly of section .text:
0000000000000000 :
- 0: 8b0772d3 add x19, x22, x7, lsl #28
- 4: cb4a3570 sub x16, x11, x10, lsr #13
- 8: ab9c09bb adds x27, x13, x28, asr #2
- c: eb9aa794 subs x20, x28, x26, asr #41
- 10: 0b934e68 add w8, w19, w19, asr #19
- 14: 4b0a3924 sub w4, w9, w10, lsl #14
- 18: 2b1e3568 adds w8, w11, w30, lsl #13
- 1c: 6b132720 subs w0, w25, w19, lsl #9
- 20: 8a154c14 and x20, x0, x21, lsl #19
- 24: aa1445d5 orr x21, x14, x20, lsl #17
- 28: ca01cf99 eor x25, x28, x1, lsl #51
- 2c: ea8b3f6a ands x10, x27, x11, asr #15
- 30: 0a8c5cb9 and w25, w5, w12, asr #23
- 34: 2a4a11d2 orr w18, w14, w10, lsr #4
- 38: 4a855aa4 eor w4, w21, w5, asr #22
- 3c: 6a857415 ands w21, w0, w5, asr #29
- 40: 8aa697da bic x26, x30, x6, asr #37
- 44: aa6d7423 orn x3, x1, x13, lsr #29
- 48: ca29bf80 eon x0, x28, x9, lsl #47
- 4c: ea3cb8bd bics x29, x5, x28, lsl #46
- 50: 0a675249 bic w9, w18, w7, lsr #20
- 54: 2ab961ba orn w26, w13, w25, asr #24
- 58: 4a331899 eon w25, w4, w19, lsl #6
- 5c: 6a646345 bics w5, w26, w4, lsr #24
- 60: 11055267 add w7, w19, #0x154
- 64: 31064408 adds w8, w0, #0x191
- 68: 51028e9d sub w29, w20, #0xa3
- 6c: 710bdee8 subs w8, w23, #0x2f7
- 70: 91082d81 add x1, x12, #0x20b
- 74: b106a962 adds x2, x11, #0x1aa
- 78: d10b33ae sub x14, x29, #0x2cc
- 7c: f10918ab subs x11, x5, #0x246
- 80: 121102d7 and w23, w22, #0x8000
- 84: 3204cd44 orr w4, w10, #0xf0f0f0f0
- 88: 5204cf00 eor w0, w24, #0xf0f0f0f0
- 8c: 72099fb3 ands w19, w29, #0x7f807f80
- 90: 92729545 and x5, x10, #0xfffffffffc000
- 94: b20e37cc orr x12, x30, #0xfffc0000fffc0000
- 98: d27c34be eor x30, x5, #0x3fff0
- 9c: f27e4efa ands x26, x23, #0x3ffffc
- a0: 14000000 b a0
- a4: 17ffffd7 b 0
- a8: 1400017f b 6a4
- ac: 94000000 bl ac
- b0: 97ffffd4 bl 0
- b4: 9400017c bl 6a4
- b8: 3400000c cbz w12, b8
- bc: 34fffa2c cbz w12, 0
- c0: 34002f2c cbz w12, 6a4
- c4: 35000014 cbnz w20, c4
- c8: 35fff9d4 cbnz w20, 0
- cc: 35002ed4 cbnz w20, 6a4
- d0: b400000c cbz x12, d0
- d4: b4fff96c cbz x12, 0
- d8: b4002e6c cbz x12, 6a4
- dc: b5000018 cbnz x24, dc
- e0: b5fff918 cbnz x24, 0
- e4: b5002e18 cbnz x24, 6a4
- e8: 10000006 adr x6, e8
- ec: 10fff8a6 adr x6, 0
- f0: 10002da6 adr x6, 6a4
- f4: 90000015 adrp x21, 0
- f8: 36080001 tbz w1, #1, f8
- fc: 360ff821 tbz w1, #1, 0
- 100: 36082d21 tbz w1, #1, 6a4
- 104: 37480008 tbnz w8, #9, 104
- 108: 374ff7c8 tbnz w8, #9, 0
- 10c: 37482cc8 tbnz w8, #9, 6a4
- 110: 128b50ec movn w12, #0x5a87
- 114: 52a9ff8b movz w11, #0x4ffc, lsl #16
- 118: 7281d095 movk w21, #0xe84
- 11c: 92edfebd movn x29, #0x6ff5, lsl #48
- 120: d28361e3 movz x3, #0x1b0f
- 124: f2a4cc96 movk x22, #0x2664, lsl #16
- 128: 9346590c sbfx x12, x8, #6, #17
- 12c: 33194f33 bfi w19, w25, #7, #20
- 130: 531d3d89 ubfiz w9, w12, #3, #16
- 134: 9350433c sbfx x28, x25, #16, #1
- 138: b34464ac bfxil x12, x5, #4, #22
- 13c: d3462140 ubfx x0, x10, #6, #3
- 140: 139a61a4 extr w4, w13, w26, #24
- 144: 93d87fd7 extr x23, x30, x24, #31
- 148: 54000000 b.eq 148
- 14c: 54fff5a0 b.eq 0
- 150: 54002aa0 b.eq 6a4
- 154: 54000001 b.ne 154
- 158: 54fff541 b.ne 0
- 15c: 54002a41 b.ne 6a4
- 160: 54000002 b.cs 160
- 164: 54fff4e2 b.cs 0
- 168: 540029e2 b.cs 6a4
- 16c: 54000002 b.cs 16c
- 170: 54fff482 b.cs 0
- 174: 54002982 b.cs 6a4
- 178: 54000003 b.cc 178
- 17c: 54fff423 b.cc 0
- 180: 54002923 b.cc 6a4
- 184: 54000003 b.cc 184
- 188: 54fff3c3 b.cc 0
- 18c: 540028c3 b.cc 6a4
- 190: 54000004 b.mi 190
- 194: 54fff364 b.mi 0
- 198: 54002864 b.mi 6a4
- 19c: 54000005 b.pl 19c
- 1a0: 54fff305 b.pl 0
- 1a4: 54002805 b.pl 6a4
- 1a8: 54000006 b.vs 1a8
- 1ac: 54fff2a6 b.vs 0
- 1b0: 540027a6 b.vs 6a4
- 1b4: 54000007 b.vc 1b4
- 1b8: 54fff247 b.vc 0
- 1bc: 54002747 b.vc 6a4
- 1c0: 54000008 b.hi 1c0
- 1c4: 54fff1e8 b.hi 0
- 1c8: 540026e8 b.hi 6a4
- 1cc: 54000009 b.ls 1cc
- 1d0: 54fff189 b.ls 0
- 1d4: 54002689 b.ls 6a4
- 1d8: 5400000a b.ge 1d8
- 1dc: 54fff12a b.ge 0
- 1e0: 5400262a b.ge 6a4
- 1e4: 5400000b b.lt 1e4
- 1e8: 54fff0cb b.lt 0
- 1ec: 540025cb b.lt 6a4
- 1f0: 5400000c b.gt 1f0
- 1f4: 54fff06c b.gt 0
- 1f8: 5400256c b.gt 6a4
- 1fc: 5400000d b.le 1fc
- 200: 54fff00d b.le 0
- 204: 5400250d b.le 6a4
- 208: 5400000e b.al 208
- 20c: 54ffefae b.al 0
- 210: 540024ae b.al 6a4
- 214: 5400000f b.nv 214
- 218: 54ffef4f b.nv 0
- 21c: 5400244f b.nv 6a4
- 220: d4063721 svc #0x31b9
- 224: d4035082 hvc #0x1a84
- 228: d400bfe3 smc #0x5ff
- 22c: d4282fc0 brk #0x417e
- 230: d444c320 hlt #0x2619
- 234: d503201f nop
- 238: d69f03e0 eret
- 23c: d6bf03e0 drps
- 240: d5033fdf isb
- 244: d5033f9f dsb sy
- 248: d5033abf dmb ishst
- 24c: d61f0040 br x2
- 250: d63f00a0 blr x5
- 254: c8147c55 stxr w20, x21, [x2]
- 258: c805fcfd stlxr w5, x29, [x7]
- 25c: c85f7e05 ldxr x5, [x16]
- 260: c85fffbb ldaxr x27, [x29]
- 264: c89fffa0 stlr x0, [x29]
- 268: c8dfff95 ldar x21, [x28]
- 26c: 88157cf8 stxr w21, w24, [x7]
- 270: 8815ff9a stlxr w21, w26, [x28]
- 274: 885f7cd5 ldxr w21, [x6]
- 278: 885fffcf ldaxr w15, [x30]
- 27c: 889ffc73 stlr w19, [x3]
- 280: 88dffc56 ldar w22, [x2]
- 284: 48127c0f stxrh w18, w15, [x0]
- 288: 480bff85 stlxrh w11, w5, [x28]
- 28c: 485f7cdd ldxrh w29, [x6]
- 290: 485ffcf2 ldaxrh w18, [x7]
- 294: 489fff99 stlrh w25, [x28]
- 298: 48dffe62 ldarh w2, [x19]
- 29c: 080a7c3e stxrb w10, w30, [x1]
- 2a0: 0814fed5 stlxrb w20, w21, [x22]
- 2a4: 085f7c59 ldxrb w25, [x2]
- 2a8: 085ffcb8 ldaxrb w24, [x5]
- 2ac: 089ffc70 stlrb w16, [x3]
- 2b0: 08dfffb6 ldarb w22, [x29]
- 2b4: c87f0a68 ldxp x8, x2, [x19]
- 2b8: c87fcdc7 ldaxp x7, x19, [x14]
- 2bc: c82870bb stxp w8, x27, x28, [x5]
- 2c0: c825b8c8 stlxp w5, x8, x14, [x6]
- 2c4: 887f12d9 ldxp w25, w4, [x22]
- 2c8: 887fb9ed ldaxp w13, w14, [x15]
- 2cc: 8834215a stxp w20, w26, w8, [x10]
- 2d0: 8837ca52 stlxp w23, w18, w18, [x18]
- 2d4: f806317e str x30, [x11,#99]
- 2d8: b81b3337 str w23, [x25,#-77]
- 2dc: 39000dc2 strb w2, [x14,#3]
- 2e0: 78005149 strh w9, [x10,#5]
- 2e4: f84391f4 ldr x20, [x15,#57]
- 2e8: b85b220c ldr w12, [x16,#-78]
- 2ec: 385fd356 ldrb w22, [x26,#-3]
- 2f0: 785d127e ldrh w30, [x19,#-47]
- 2f4: 389f4149 ldrsb x9, [x10,#-12]
- 2f8: 79801e3c ldrsh x28, [x17,#14]
- 2fc: 79c014a3 ldrsh w3, [x5,#10]
- 300: b89a5231 ldrsw x17, [x17,#-91]
- 304: fc5ef282 ldr d2, [x20,#-17]
- 308: bc5f60f6 ldr s22, [x7,#-10]
- 30c: fc12125e str d30, [x18,#-223]
- 310: bc0152cd str s13, [x22,#21]
- 314: f8190e49 str x9, [x18,#-112]!
- 318: b800befd str w29, [x23,#11]!
- 31c: 381ffd92 strb w18, [x12,#-1]!
- 320: 781e9e90 strh w16, [x20,#-23]!
- 324: f8409fa3 ldr x3, [x29,#9]!
- 328: b8413c79 ldr w25, [x3,#19]!
- 32c: 385fffa1 ldrb w1, [x29,#-1]!
- 330: 785c7fa8 ldrh w8, [x29,#-57]!
- 334: 389f3dc5 ldrsb x5, [x14,#-13]!
- 338: 78801f6a ldrsh x10, [x27,#1]!
- 33c: 78c19d4b ldrsh w11, [x10,#25]!
- 340: b89a4ec4 ldrsw x4, [x22,#-92]!
- 344: fc408eeb ldr d11, [x23,#8]!
- 348: bc436e79 ldr s25, [x19,#54]!
- 34c: fc152ce1 str d1, [x7,#-174]!
- 350: bc036f28 str s8, [x25,#54]!
- 354: f8025565 str x5, [x11],#37
- 358: b80135f8 str w24, [x15],#19
- 35c: 381ff74f strb w15, [x26],#-1
- 360: 781fa652 strh w18, [x18],#-6
- 364: f851a447 ldr x7, [x2],#-230
- 368: b85e557b ldr w27, [x11],#-27
- 36c: 385e7472 ldrb w18, [x3],#-25
- 370: 785e070a ldrh w10, [x24],#-32
- 374: 38804556 ldrsb x22, [x10],#4
- 378: 78819591 ldrsh x17, [x12],#25
- 37c: 78dc24e8 ldrsh w8, [x7],#-62
- 380: b89cd6d7 ldrsw x23, [x22],#-51
- 384: fc430738 ldr d24, [x25],#48
- 388: bc5f6595 ldr s21, [x12],#-10
- 38c: fc1225b2 str d18, [x13],#-222
- 390: bc1d7430 str s16, [x1],#-41
- 394: f82fcac2 str x2, [x22,w15,sxtw]
- 398: b83d6a02 str w2, [x16,x29]
- 39c: 382e5a54 strb w20, [x18,w14,uxtw #0]
- 3a0: 7834fa66 strh w6, [x19,x20,sxtx #1]
- 3a4: f86ecbae ldr x14, [x29,w14,sxtw]
- 3a8: b86cda90 ldr w16, [x20,w12,sxtw #2]
- 3ac: 3860d989 ldrb w9, [x12,w0,sxtw #0]
- 3b0: 78637a2c ldrh w12, [x17,x3,lsl #1]
- 3b4: 38a3fa22 ldrsb x2, [x17,x3,sxtx #0]
- 3b8: 78b15827 ldrsh x7, [x1,w17,uxtw #1]
- 3bc: 78f2d9f9 ldrsh w25, [x15,w18,sxtw #1]
- 3c0: b8ac6ab7 ldrsw x23, [x21,x12]
- 3c4: fc6879a5 ldr d5, [x13,x8,lsl #3]
- 3c8: bc767943 ldr s3, [x10,x22,lsl #2]
- 3cc: fc3bc84e str d14, [x2,w27,sxtw]
- 3d0: bc3968d4 str s20, [x6,x25]
- 3d4: f91fc0fe str x30, [x7,#16256]
- 3d8: b91da50f str w15, [x8,#7588]
- 3dc: 391d280b strb w11, [x0,#1866]
- 3e0: 791d2e23 strh w3, [x17,#3734]
- 3e4: f95bc8e2 ldr x2, [x7,#14224]
- 3e8: b95ce525 ldr w5, [x9,#7396]
- 3ec: 395ae53c ldrb w28, [x9,#1721]
- 3f0: 795c9282 ldrh w2, [x20,#3656]
- 3f4: 399d7dd6 ldrsb x22, [x14,#1887]
- 3f8: 799fe008 ldrsh x8, [x0,#4080]
- 3fc: 79de9bc0 ldrsh w0, [x30,#3916]
- 400: b99aae78 ldrsw x24, [x19,#6828]
- 404: fd597598 ldr d24, [x12,#13032]
- 408: bd5d1d08 ldr s8, [x8,#7452]
- 40c: fd1f3dea str d10, [x15,#15992]
- 410: bd1a227a str s26, [x19,#6688]
- 414: 5800148a ldr x10, 6a4
- 418: 18000003 ldr w3, 418
- 41c: f88092e0 prfm pldl1keep, [x23,#9]
- 420: d8ffdf00 prfm pldl1keep, 0
- 424: f8a84860 prfm pldl1keep, [x3,w8,uxtw]
- 428: f99d7560 prfm pldl1keep, [x11,#15080]
- 42c: 1a1c012d adc w13, w9, w28
- 430: 3a1c027b adcs w27, w19, w28
- 434: 5a060253 sbc w19, w18, w6
- 438: 7a03028e sbcs w14, w20, w3
- 43c: 9a0801d0 adc x16, x14, x8
- 440: ba0803a0 adcs x0, x29, x8
- 444: da140308 sbc x8, x24, x20
- 448: fa00038c sbcs x12, x28, x0
- 44c: 0b3010d7 add w23, w6, w16, uxtb #4
- 450: 2b37ab39 adds w25, w25, w23, sxth #2
- 454: cb2466da sub x26, x22, x4, uxtx #1
- 458: 6b33efb1 subs w17, w29, w19, sxtx #3
- 45c: 8b350fcb add x11, x30, w21, uxtb #3
- 460: ab208a70 adds x16, x19, w0, sxtb #2
- 464: cb39e52b sub x11, x9, x25, sxtx #1
- 468: eb2c9291 subs x17, x20, w12, sxtb #4
- 46c: 3a4bd1a3 ccmn w13, w11, #0x3, le
- 470: 7a4c81a2 ccmp w13, w12, #0x2, hi
- 474: ba42106c ccmn x3, x2, #0xc, ne
- 478: fa5560e3 ccmp x7, x21, #0x3, vs
- 47c: 3a4e3844 ccmn w2, #0xe, #0x4, cc
- 480: 7a515a26 ccmp w17, #0x11, #0x6, pl
- 484: ba4c2940 ccmn x10, #0xc, #0x0, cs
- 488: fa52aaae ccmp x21, #0x12, #0xe, ge
- 48c: 1a8cc1b5 csel w21, w13, w12, gt
- 490: 1a8f976a csinc w10, w27, w15, ls
- 494: 5a8981a0 csinv w0, w13, w9, hi
- 498: 5a9a6492 csneg w18, w4, w26, vs
- 49c: 9a8793ac csel x12, x29, x7, ls
- 4a0: 9a9474e6 csinc x6, x7, x20, vc
- 4a4: da83d2b6 csinv x22, x21, x3, le
- 4a8: da9b9593 csneg x19, x12, x27, ls
- 4ac: 5ac00200 rbit w0, w16
- 4b0: 5ac006f1 rev16 w17, w23
- 4b4: 5ac009d1 rev w17, w14
- 4b8: 5ac013d8 clz w24, w30
- 4bc: 5ac016d8 cls w24, w22
- 4c0: dac00223 rbit x3, x17
- 4c4: dac005ac rev16 x12, x13
- 4c8: dac00ac9 rev32 x9, x22
- 4cc: dac00c00 rev x0, x0
- 4d0: dac01205 clz x5, x16
- 4d4: dac016d9 cls x25, x22
- 4d8: 1ac0089d udiv w29, w4, w0
- 4dc: 1add0fa0 sdiv w0, w29, w29
- 4e0: 1ad52225 lsl w5, w17, w21
- 4e4: 1ad22529 lsr w9, w9, w18
- 4e8: 1ac82b61 asr w1, w27, w8
- 4ec: 1acd2e92 ror w18, w20, w13
- 4f0: 9acc0b28 udiv x8, x25, x12
- 4f4: 9adc0ca7 sdiv x7, x5, x28
- 4f8: 9adb2225 lsl x5, x17, x27
- 4fc: 9ad42757 lsr x23, x26, x20
- 500: 9adc291c asr x28, x8, x28
- 504: 9ac42fa3 ror x3, x29, x4
- 508: 1b1a55d1 madd w17, w14, w26, w21
- 50c: 1b0bafc1 msub w1, w30, w11, w11
- 510: 9b067221 madd x1, x17, x6, x28
- 514: 9b1ea0de msub x30, x6, x30, x8
- 518: 9b2e20d5 smaddl x21, w6, w14, x8
- 51c: 9b38cd4a smsubl x10, w10, w24, x19
- 520: 9bae6254 umaddl x20, w18, w14, x24
- 524: 9ba59452 umsubl x18, w2, w5, x5
- 528: 1e2d0a48 fmul s8, s18, s13
- 52c: 1e3c19c2 fdiv s2, s14, s28
- 530: 1e3c298f fadd s15, s12, s28
- 534: 1e213980 fsub s0, s12, s1
- 538: 1e240baf fmul s15, s29, s4
- 53c: 1e77082c fmul d12, d1, d23
- 540: 1e72191b fdiv d27, d8, d18
- 544: 1e6b2a97 fadd d23, d20, d11
- 548: 1e723988 fsub d8, d12, d18
- 54c: 1e770b1a fmul d26, d24, d23
- 550: 1f0d66f5 fmadd s21, s23, s13, s25
- 554: 1f01b956 fmsub s22, s10, s1, s14
- 558: 1f227a8e fnmadd s14, s20, s2, s30
- 55c: 1f365ba7 fnmadd s7, s29, s22, s22
- 560: 1f4f14ad fmadd d13, d5, d15, d5
- 564: 1f45a98e fmsub d14, d12, d5, d10
- 568: 1f60066a fnmadd d10, d19, d0, d1
- 56c: 1f620054 fnmadd d20, d2, d2, d0
- 570: 1e204139 fmov s25, s9
- 574: 1e20c094 fabs s20, s4
- 578: 1e214363 fneg s3, s27
- 57c: 1e21c041 fsqrt s1, s2
- 580: 1e22c01e fcvt d30, s0
- 584: 1e60408c fmov d12, d4
- 588: 1e60c361 fabs d1, d27
- 58c: 1e6142c8 fneg d8, d22
- 590: 1e61c16b fsqrt d11, d11
- 594: 1e624396 fcvt s22, d28
- 598: 1e3802dc fcvtzs w28, s22
- 59c: 9e380374 fcvtzs x20, s27
- 5a0: 1e78000e fcvtzs w14, d0
- 5a4: 9e78017a fcvtzs x26, d11
- 5a8: 1e2202dc scvtf s28, w22
- 5ac: 9e220150 scvtf s16, x10
- 5b0: 1e6202a8 scvtf d8, w21
- 5b4: 9e620395 scvtf d21, x28
- 5b8: 1e260318 fmov w24, s24
- 5bc: 9e660268 fmov x8, d19
- 5c0: 1e270188 fmov s8, w12
- 5c4: 9e6700e6 fmov d6, x7
- 5c8: 1e3023c0 fcmp s30, s16
- 5cc: 1e6b2320 fcmp d25, d11
- 5d0: 1e202168 fcmp s11, #0.0
- 5d4: 1e602168 fcmp d11, #0.0
- 5d8: 2910323d stp w29, w12, [x17,#128]
- 5dc: 297449d6 ldp w22, w18, [x14,#-96]
- 5e0: 6948402b ldpsw x11, x16, [x1,#64]
- 5e4: a9072f40 stp x0, x11, [x26,#112]
- 5e8: a9410747 ldp x7, x1, [x26,#16]
- 5ec: 29801f0a stp w10, w7, [x24,#0]!
- 5f0: 29e07307 ldp w7, w28, [x24,#-256]!
- 5f4: 69e272b9 ldpsw x25, x28, [x21,#-240]!
- 5f8: a9bf49d4 stp x20, x18, [x14,#-16]!
- 5fc: a9c529a8 ldp x8, x10, [x13,#80]!
- 600: 28b0605a stp w26, w24, [x2],#-128
- 604: 28e866a2 ldp w2, w25, [x21],#-192
- 608: 68ee0ab1 ldpsw x17, x2, [x21],#-144
- 60c: a886296c stp x12, x10, [x11],#96
- 610: a8fe1a38 ldp x24, x6, [x17],#-32
- 614: 282479c3 stnp w3, w30, [x14,#-224]
- 618: 286e534f ldnp w15, w20, [x26,#-144]
- 61c: a8386596 stnp x22, x25, [x12,#-128]
- 620: a8755a3b ldnp x27, x22, [x17,#-176]
- 624: 1e601000 fmov d0, #2.000000000000000000e+00
- 628: 1e603000 fmov d0, #2.125000000000000000e+00
- 62c: 1e621000 fmov d0, #4.000000000000000000e+00
- 630: 1e623000 fmov d0, #4.250000000000000000e+00
- 634: 1e641000 fmov d0, #8.000000000000000000e+00
- 638: 1e643000 fmov d0, #8.500000000000000000e+00
- 63c: 1e661000 fmov d0, #1.600000000000000000e+01
- 640: 1e663000 fmov d0, #1.700000000000000000e+01
- 644: 1e681000 fmov d0, #1.250000000000000000e-01
- 648: 1e683000 fmov d0, #1.328125000000000000e-01
- 64c: 1e6a1000 fmov d0, #2.500000000000000000e-01
- 650: 1e6a3000 fmov d0, #2.656250000000000000e-01
- 654: 1e6c1000 fmov d0, #5.000000000000000000e-01
- 658: 1e6c3000 fmov d0, #5.312500000000000000e-01
- 65c: 1e6e1000 fmov d0, #1.000000000000000000e+00
- 660: 1e6e3000 fmov d0, #1.062500000000000000e+00
- 664: 1e701000 fmov d0, #-2.000000000000000000e+00
- 668: 1e703000 fmov d0, #-2.125000000000000000e+00
- 66c: 1e721000 fmov d0, #-4.000000000000000000e+00
- 670: 1e723000 fmov d0, #-4.250000000000000000e+00
- 674: 1e741000 fmov d0, #-8.000000000000000000e+00
- 678: 1e743000 fmov d0, #-8.500000000000000000e+00
- 67c: 1e761000 fmov d0, #-1.600000000000000000e+01
- 680: 1e763000 fmov d0, #-1.700000000000000000e+01
- 684: 1e781000 fmov d0, #-1.250000000000000000e-01
- 688: 1e783000 fmov d0, #-1.328125000000000000e-01
- 68c: 1e7a1000 fmov d0, #-2.500000000000000000e-01
- 690: 1e7a3000 fmov d0, #-2.656250000000000000e-01
- 694: 1e7c1000 fmov d0, #-5.000000000000000000e-01
- 698: 1e7c3000 fmov d0, #-5.312500000000000000e-01
- 69c: 1e7e1000 fmov d0, #-1.000000000000000000e+00
- 6a0: 1e7e3000 fmov d0, #-1.062500000000000000e+00
+ 0: 8b18ec0f add x15, x0, x24, lsl #59
+ 4: cb9636d1 sub x17, x22, x22, asr #13
+ 8: ab1ce74a adds x10, x26, x28, lsl #57
+ c: eb184a19 subs x25, x16, x24, lsl #18
+ 10: 0b1c1ca8 add w8, w5, w28, lsl #7
+ 14: 4b817388 sub w8, w28, w1, asr #28
+ 18: 2b01004c adds w12, w2, w1
+ 1c: 6b5164b7 subs w23, w5, w17, lsr #25
+ 20: 8a0d5595 and x21, x12, x13, lsl #21
+ 24: aa9791f5 orr x21, x15, x23, asr #36
+ 28: ca9bc316 eor x22, x24, x27, asr #48
+ 2c: ea82d1f6 ands x22, x15, x2, asr #52
+ 30: 0a980e21 and w1, w17, w24, asr #3
+ 34: 2a862c45 orr w5, w2, w6, asr #11
+ 38: 4a453037 eor w23, w1, w5, lsr #12
+ 3c: 6a8e5180 ands w0, w12, w14, asr #20
+ 40: 8a621cc1 bic x1, x6, x2, lsr #7
+ 44: aa24bd1e orn x30, x8, x4, lsl #47
+ 48: cab4d6d1 eon x17, x22, x20, asr #53
+ 4c: eaa591fd bics x29, x15, x5, asr #36
+ 50: 0a7d6efe bic w30, w23, w29, lsr #27
+ 54: 2a2253ac orn w12, w29, w2, lsl #20
+ 58: 4aa61187 eon w7, w12, w6, asr #4
+ 5c: 6aa755b0 bics w16, w13, w7, asr #21
+ 60: 110b5a25 add w5, w17, #0x2d6
+ 64: 31056e0a adds w10, w16, #0x15b
+ 68: 510f48ba sub w26, w5, #0x3d2
+ 6c: 710ac715 subs w21, w24, #0x2b1
+ 70: 910f6e0a add x10, x16, #0x3db
+ 74: b10a65ef adds x15, x15, #0x299
+ 78: d1009e98 sub x24, x20, #0x27
+ 7c: f10131aa subs x10, x13, #0x4c
+ 80: 121d4e67 and w7, w19, #0x7ffff8
+ 84: 32043e25 orr w5, w17, #0xf0000fff
+ 88: 52132390 eor w16, w28, #0x3fe000
+ 8c: 72160b0e ands w14, w24, #0x1c00
+ 90: 9273e76e and x14, x27, #0xffffffffffffe07f
+ 94: b256416c orr x12, x11, #0x7fffc0000000000
+ 98: d24b5002 eor x2, x0, #0xffe00000000003ff
+ 9c: f266da8d ands x13, x20, #0xfffffffffc01ffff
+ a0: 14000000 b a0
+ a4: 17ffffd7 b 0
+ a8: 140001ee b 860
+ ac: 94000000 bl ac
+ b0: 97ffffd4 bl 0
+ b4: 940001eb bl 860
+ b8: 3400000f cbz w15, b8
+ bc: 34fffa2f cbz w15, 0
+ c0: 34003d0f cbz w15, 860
+ c4: 3500001c cbnz w28, c4
+ c8: 35fff9dc cbnz w28, 0
+ cc: 35003cbc cbnz w28, 860
+ d0: b400001b cbz x27, d0
+ d4: b4fff97b cbz x27, 0
+ d8: b4003c5b cbz x27, 860
+ dc: b5000000 cbnz x0, dc
+ e0: b5fff900 cbnz x0, 0
+ e4: b5003be0 cbnz x0, 860
+ e8: 1000000d adr x13, e8
+ ec: 10fff8ad adr x13, 0
+ f0: 10003b8d adr x13, 860
+ f4: 90000003 adrp x3, 0
+ f8: 36380015 tbz w21, #7, f8
+ fc: 363ff835 tbz w21, #7, 0
+ 100: 36383b15 tbz w21, #7, 860
+ 104: 3748000f tbnz w15, #9, 104
+ 108: 374ff7cf tbnz w15, #9, 0
+ 10c: 37483aaf tbnz w15, #9, 860
+ 110: 12a14bee mov w14, #0xf5a0ffff // #-173998081
+ 114: 5283bb51 mov w17, #0x1dda // #7642
+ 118: 72858ebb movk w27, #0x2c75
+ 11c: 92c98881 mov x1, #0xffffb3bbffffffff // #-83854941487105
+ 120: d2aa50d4 mov x20, #0x52860000 // #1384513536
+ 124: f2afd9d4 movk x20, #0x7ece, lsl #16
+ 128: 935c504d sbfiz x13, x2, #36, #21
+ 12c: 33133e90 bfi w16, w20, #13, #16
+ 130: 5309196b ubfiz w11, w11, #23, #7
+ 134: 93595482 sbfiz x2, x4, #39, #22
+ 138: b3424e0d bfxil x13, x16, #2, #18
+ 13c: d3481728 ubfiz x8, x25, #56, #6
+ 140: 138a3b7d extr w29, w27, w10, #14
+ 144: 93c66286 extr x6, x20, x6, #24
+ 148: 54000000 b.eq 148 // b.none
+ 14c: 54fff5a0 b.eq 0 // b.none
+ 150: 54003880 b.eq 860 // b.none
+ 154: 54000001 b.ne 154 // b.any
+ 158: 54fff541 b.ne 0 // b.any
+ 15c: 54003821 b.ne 860 // b.any
+ 160: 54000002 b.cs 160 // b.hs, b.nlast
+ 164: 54fff4e2 b.cs 0 // b.hs, b.nlast
+ 168: 540037c2 b.cs 860 // b.hs, b.nlast
+ 16c: 54000002 b.cs 16c // b.hs, b.nlast
+ 170: 54fff482 b.cs 0 // b.hs, b.nlast
+ 174: 54003762 b.cs 860 // b.hs, b.nlast
+ 178: 54000003 b.cc 178 // b.lo, b.ul, b.last
+ 17c: 54fff423 b.cc 0 // b.lo, b.ul, b.last
+ 180: 54003703 b.cc 860 // b.lo, b.ul, b.last
+ 184: 54000003 b.cc 184 // b.lo, b.ul, b.last
+ 188: 54fff3c3 b.cc 0 // b.lo, b.ul, b.last
+ 18c: 540036a3 b.cc 860 // b.lo, b.ul, b.last
+ 190: 54000004 b.mi 190 // b.first
+ 194: 54fff364 b.mi 0 // b.first
+ 198: 54003644 b.mi 860 // b.first
+ 19c: 54000005 b.pl 19c // b.nfrst
+ 1a0: 54fff305 b.pl 0 // b.nfrst
+ 1a4: 540035e5 b.pl 860 // b.nfrst
+ 1a8: 54000006 b.vs 1a8
+ 1ac: 54fff2a6 b.vs 0
+ 1b0: 54003586 b.vs 860
+ 1b4: 54000007 b.vc 1b4
+ 1b8: 54fff247 b.vc 0
+ 1bc: 54003527 b.vc 860
+ 1c0: 54000008 b.hi 1c0 // b.pmore
+ 1c4: 54fff1e8 b.hi 0 // b.pmore
+ 1c8: 540034c8 b.hi 860 // b.pmore
+ 1cc: 54000009 b.ls 1cc // b.plast
+ 1d0: 54fff189 b.ls 0 // b.plast
+ 1d4: 54003469 b.ls 860 // b.plast
+ 1d8: 5400000a b.ge 1d8 // b.tcont
+ 1dc: 54fff12a b.ge 0 // b.tcont
+ 1e0: 5400340a b.ge 860 // b.tcont
+ 1e4: 5400000b b.lt 1e4 // b.tstop
+ 1e8: 54fff0cb b.lt 0 // b.tstop
+ 1ec: 540033ab b.lt 860 // b.tstop
+ 1f0: 5400000c b.gt 1f0
+ 1f4: 54fff06c b.gt 0
+ 1f8: 5400334c b.gt 860
+ 1fc: 5400000d b.le 1fc
+ 200: 54fff00d b.le 0
+ 204: 540032ed b.le 860
+ 208: 5400000e b.al 208
+ 20c: 54ffefae b.al 0
+ 210: 5400328e b.al 860
+ 214: 5400000f b.nv 214
+ 218: 54ffef4f b.nv 0
+ 21c: 5400322f b.nv 860
+ 220: d40d2881 svc #0x6944
+ 224: d40ea5c2 hvc #0x752e
+ 228: d40518a3 smc #0x28c5
+ 22c: d42eca40 brk #0x7652
+ 230: d44a2e60 hlt #0x5173
+ 234: d503201f nop
+ 238: d69f03e0 eret
+ 23c: d6bf03e0 drps
+ 240: d5033fdf isb
+ 244: d5033d9f dsb ld
+ 248: d5033bbf dmb ish
+ 24c: d61f0120 br x9
+ 250: d63f0120 blr x9
+ 254: c8027d7d stxr w2, x29, [x11]
+ 258: c816ff85 stlxr w22, x5, [x28]
+ 25c: c85f7e8e ldxr x14, [x20]
+ 260: c85ffe7d ldaxr x29, [x19]
+ 264: c89ffea6 stlr x6, [x21]
+ 268: c8dffc73 ldar x19, [x3]
+ 26c: 880c7f63 stxr w12, w3, [x27]
+ 270: 8811fdfa stlxr w17, w26, [x15]
+ 274: 885f7dcd ldxr w13, [x14]
+ 278: 885fff4c ldaxr w12, [x26]
+ 27c: 889ffe28 stlr w8, [x17]
+ 280: 88dfffd5 ldar w21, [x30]
+ 284: 48007d6f stxrh w0, w15, [x11]
+ 288: 4811fc34 stlxrh w17, w20, [x1]
+ 28c: 485f7d1d ldxrh w29, [x8]
+ 290: 485ffd91 ldaxrh w17, [x12]
+ 294: 489ffc8b stlrh w11, [x4]
+ 298: 48dffc90 ldarh w16, [x4]
+ 29c: 080e7c85 stxrb w14, w5, [x4]
+ 2a0: 081bfe11 stlxrb w27, w17, [x16]
+ 2a4: 085f7f66 ldxrb w6, [x27]
+ 2a8: 085fff1b ldaxrb w27, [x24]
+ 2ac: 089ffe8a stlrb w10, [x20]
+ 2b0: 08dfff49 ldarb w9, [x26]
+ 2b4: c87f7b85 ldxp x5, x30, [x28]
+ 2b8: c87fa66a ldaxp x10, x9, [x19]
+ 2bc: c82b5590 stxp w11, x16, x21, [x12]
+ 2c0: c82adc94 stlxp w10, x20, x23, [x4]
+ 2c4: 887f0416 ldxp w22, w1, [x0]
+ 2c8: 887f8503 ldaxp w3, w1, [x8]
+ 2cc: 88205fc9 stxp w0, w9, w23, [x30]
+ 2d0: 8837c560 stlxp w23, w0, w17, [x11]
+ 2d4: f81e1146 stur x6, [x10, #-31]
+ 2d8: b81fb007 stur w7, [x0, #-5]
+ 2dc: 381f3205 sturb w5, [x16, #-13]
+ 2e0: 7801f27e sturh w30, [x19, #31]
+ 2e4: f8477130 ldur x16, [x9, #119]
+ 2e8: b843b208 ldur w8, [x16, #59]
+ 2ec: 385f918a ldurb w10, [x12, #-7]
+ 2f0: 785da12e ldurh w14, [x9, #-38]
+ 2f4: 389f83d8 ldursb x24, [x30, #-8]
+ 2f8: 78817087 ldursh x7, [x4, #23]
+ 2fc: 78dd91d1 ldursh w17, [x14, #-39]
+ 300: b89e136b ldursw x11, [x27, #-31]
+ 304: fc4410ec ldur d12, [x7, #65]
+ 308: bc5fe200 ldur s0, [x16, #-2]
+ 30c: fc15f2ed stur d13, [x23, #-161]
+ 310: bc1c2075 stur s21, [x3, #-62]
+ 314: f8064ca2 str x2, [x5, #100]!
+ 318: b81a4c29 str w9, [x1, #-92]!
+ 31c: 381fbfdb strb w27, [x30, #-5]!
+ 320: 7800cdfb strh w27, [x15, #12]!
+ 324: f852ce24 ldr x4, [x17, #-212]!
+ 328: b841eef5 ldr w21, [x23, #30]!
+ 32c: 385f9e2d ldrb w13, [x17, #-7]!
+ 330: 785cec19 ldrh w25, [x0, #-50]!
+ 334: 389ebea1 ldrsb x1, [x21, #-21]!
+ 338: 789caebc ldrsh x28, [x21, #-54]!
+ 33c: 78c02c8b ldrsh w11, [x4, #2]!
+ 340: b883dd31 ldrsw x17, [x9, #61]!
+ 344: fc427e7d ldr d29, [x19, #39]!
+ 348: bc5abed6 ldr s22, [x22, #-85]!
+ 34c: fc11ff29 str d9, [x25, #-225]!
+ 350: bc1f1c49 str s9, [x2, #-15]!
+ 354: f81be6ed str x13, [x23], #-66
+ 358: b800a611 str w17, [x16], #10
+ 35c: 381e05c1 strb w1, [x14], #-32
+ 360: 78006411 strh w17, [x0], #6
+ 364: f855473b ldr x27, [x25], #-172
+ 368: b85da72d ldr w13, [x25], #-38
+ 36c: 385e372b ldrb w11, [x25], #-29
+ 370: 784144be ldrh w30, [x5], #20
+ 374: 389f94e9 ldrsb x9, [x7], #-7
+ 378: 789c2460 ldrsh x0, [x3], #-62
+ 37c: 78c1f5c7 ldrsh w7, [x14], #31
+ 380: b8827771 ldrsw x17, [x27], #39
+ 384: fc515491 ldr d17, [x4], #-235
+ 388: bc4226ba ldr s26, [x21], #34
+ 38c: fc1c7625 str d5, [x17], #-57
+ 390: bc1935ad str s13, [x13], #-109
+ 394: f824da06 str x6, [x16, w4, sxtw #3]
+ 398: b834db09 str w9, [x24, w20, sxtw #2]
+ 39c: 38237ba3 strb w3, [x29, x3, lsl #0]
+ 3a0: 783e6a2a strh w10, [x17, x30]
+ 3a4: f867497b ldr x27, [x11, w7, uxtw]
+ 3a8: b87949ee ldr w14, [x15, w25, uxtw]
+ 3ac: 387379d8 ldrb w24, [x14, x19, lsl #0]
+ 3b0: 7866c810 ldrh w16, [x0, w6, sxtw]
+ 3b4: 38acd98a ldrsb x10, [x12, w12, sxtw #0]
+ 3b8: 78b0499a ldrsh x26, [x12, w16, uxtw]
+ 3bc: 78ee781a ldrsh w26, [x0, x14, lsl #1]
+ 3c0: b8bbf971 ldrsw x17, [x11, x27, sxtx #2]
+ 3c4: fc73d803 ldr d3, [x0, w19, sxtw #3]
+ 3c8: bc6979fa ldr s26, [x15, x9, lsl #2]
+ 3cc: fc30e9ab str d11, [x13, x16, sxtx]
+ 3d0: bc355a7a str s26, [x19, w21, uxtw #2]
+ 3d4: f91886a8 str x8, [x21, #12552]
+ 3d8: b918ef6a str w10, [x27, #6380]
+ 3dc: 391b15db strb w27, [x14, #1733]
+ 3e0: 791ac0f0 strh w16, [x7, #3424]
+ 3e4: f958753b ldr x27, [x9, #12520]
+ 3e8: b95a1958 ldr w24, [x10, #6680]
+ 3ec: 395b3f18 ldrb w24, [x24, #1743]
+ 3f0: 795800b4 ldrh w20, [x5, #3072]
+ 3f4: 39988891 ldrsb x17, [x4, #1570]
+ 3f8: 799a81ae ldrsh x14, [x13, #3392]
+ 3fc: 79dd172a ldrsh w10, [x25, #3722]
+ 400: b9981342 ldrsw x2, [x26, #6160]
+ 404: fd5d21da ldr d26, [x14, #14912]
+ 408: bd5e7c9c ldr s28, [x4, #7804]
+ 40c: fd1b526e str d14, [x19, #13984]
+ 410: bd18df97 str s23, [x28, #6364]
+ 414: 58002268 ldr x8, 860
+ 418: 18ffdf51 ldr w17, 0
+ 41c: f8951080 prfum pldl1keep, [x4, #-175]
+ 420: d8000000 prfm pldl1keep, 420
+ 424: f8a4c900 prfm pldl1keep, [x8, w4, sxtw]
+ 428: f999e180 prfm pldl1keep, [x12, #13248]
+ 42c: 1a150374 adc w20, w27, w21
+ 430: 3a060227 adcs w7, w17, w6
+ 434: 5a1900c5 sbc w5, w6, w25
+ 438: 7a0e017e sbcs w30, w11, w14
+ 43c: 9a0b0223 adc x3, x17, x11
+ 440: ba110159 adcs x25, x10, x17
+ 444: da170207 sbc x7, x16, x23
+ 448: fa050144 sbcs x4, x10, x5
+ 44c: 0b2973c9 add w9, w30, w9, uxtx #4
+ 450: 2b30a8a0 adds w0, w5, w16, sxth #2
+ 454: cb3b8baf sub x15, x29, w27, sxtb #2
+ 458: 6b21f12b subs w11, w9, w1, sxtx #4
+ 45c: 8b264f02 add x2, x24, w6, uxtw #3
+ 460: ab3a70d3 adds x19, x6, x26, uxtx #4
+ 464: cb39ef48 sub x8, x26, x25, sxtx #3
+ 468: eb29329a subs x26, x20, w9, uxth #4
+ 46c: 3a5a41a7 ccmn w13, w26, #0x7, mi // mi = first
+ 470: 7a54310f ccmp w8, w20, #0xf, cc // cc = lo, ul, last
+ 474: ba4302c8 ccmn x22, x3, #0x8, eq // eq = none
+ 478: fa58a04a ccmp x2, x24, #0xa, ge // ge = tcont
+ 47c: 3a50490d ccmn w8, #0x10, #0xd, mi // mi = first
+ 480: 7a4c0a01 ccmp w16, #0xc, #0x1, eq // eq = none
+ 484: ba5f79e3 ccmn x15, #0x1f, #0x3, vc
+ 488: fa4c0aef ccmp x23, #0xc, #0xf, eq // eq = none
+ 48c: 1a9a30ee csel w14, w7, w26, cc // cc = lo, ul, last
+ 490: 1a9ed763 csinc w3, w27, w30, le
+ 494: 5a9702ab csinv w11, w21, w23, eq // eq = none
+ 498: 5a95c7da csneg w26, w30, w21, gt
+ 49c: 9a8d835c csel x28, x26, x13, hi // hi = pmore
+ 4a0: 9a909471 csinc x17, x3, x16, ls // ls = plast
+ 4a4: da8380ab csinv x11, x5, x3, hi // hi = pmore
+ 4a8: da93c461 csneg x1, x3, x19, gt
+ 4ac: 5ac00120 rbit w0, w9
+ 4b0: 5ac005da rev16 w26, w14
+ 4b4: 5ac00a2d rev w13, w17
+ 4b8: 5ac0128b clz w11, w20
+ 4bc: 5ac0163c cls w28, w17
+ 4c0: dac0008d rbit x13, x4
+ 4c4: dac007c1 rev16 x1, x30
+ 4c8: dac009cd rev32 x13, x14
+ 4cc: dac00d05 rev x5, x8
+ 4d0: dac01322 clz x2, x25
+ 4d4: dac01514 cls x20, x8
+ 4d8: 1adb0b35 udiv w21, w25, w27
+ 4dc: 1ad00d4d sdiv w13, w10, w16
+ 4e0: 1ad1203c lsl w28, w1, w17
+ 4e4: 1aca26f9 lsr w25, w23, w10
+ 4e8: 1ac72867 asr w7, w3, w7
+ 4ec: 1ace2fce ror w14, w30, w14
+ 4f0: 9acf0acc udiv x12, x22, x15
+ 4f4: 9acd0f22 sdiv x2, x25, x13
+ 4f8: 9ad522e7 lsl x7, x23, x21
+ 4fc: 9ac0258b lsr x11, x12, x0
+ 500: 9adc293e asr x30, x9, x28
+ 504: 9ad62cad ror x13, x5, x22
+ 508: 9bc47ea5 umulh x5, x21, x4
+ 50c: 9b477c51 smulh x17, x2, x7
+ 510: 1b11318c madd w12, w12, w17, w12
+ 514: 1b01edfe msub w30, w15, w1, w27
+ 518: 9b117662 madd x2, x19, x17, x29
+ 51c: 9b03fae4 msub x4, x23, x3, x30
+ 520: 9b313eef smaddl x15, w23, w17, x15
+ 524: 9b21b59b smsubl x27, w12, w1, x13
+ 528: 9bac45a6 umaddl x6, w13, w12, x17
+ 52c: 9ba6a839 umsubl x25, w1, w6, x10
+ 530: 1e240871 fmul s17, s3, s4
+ 534: 1e3518b0 fdiv s16, s5, s21
+ 538: 1e312b63 fadd s3, s27, s17
+ 53c: 1e2f3959 fsub s25, s10, s15
+ 540: 1e200a2a fmul s10, s17, s0
+ 544: 1e630b5c fmul d28, d26, d3
+ 548: 1e7b1804 fdiv d4, d0, d27
+ 54c: 1e6229dc fadd d28, d14, d2
+ 550: 1e773b4c fsub d12, d26, d23
+ 554: 1e610bcf fmul d15, d30, d1
+ 558: 1f0534a4 fmadd s4, s5, s5, s13
+ 55c: 1f1c85b5 fmsub s21, s13, s28, s1
+ 560: 1f3d1c71 fnmadd s17, s3, s29, s7
+ 564: 1f3d6b37 fnmadd s23, s25, s29, s26
+ 568: 1f5e68ee fmadd d14, d7, d30, d26
+ 56c: 1f4aa4f6 fmsub d22, d7, d10, d9
+ 570: 1f6e24e7 fnmadd d7, d7, d14, d9
+ 574: 1f6f630e fnmadd d14, d24, d15, d24
+ 578: 1e204056 fmov s22, s2
+ 57c: 1e20c060 fabs s0, s3
+ 580: 1e214229 fneg s9, s17
+ 584: 1e21c178 fsqrt s24, s11
+ 588: 1e22c32f fcvt d15, s25
+ 58c: 1e604064 fmov d4, d3
+ 590: 1e60c2da fabs d26, d22
+ 594: 1e61427e fneg d30, d19
+ 598: 1e61c1cc fsqrt d12, d14
+ 59c: 1e6240f1 fcvt s17, d7
+ 5a0: 1e3801d8 fcvtzs w24, s14
+ 5a4: 9e38034d fcvtzs x13, s26
+ 5a8: 1e780022 fcvtzs w2, d1
+ 5ac: 9e780165 fcvtzs x5, d11
+ 5b0: 1e22026e scvtf s14, w19
+ 5b4: 9e2202c1 scvtf s1, x22
+ 5b8: 1e62023b scvtf d27, w17
+ 5bc: 9e620136 scvtf d22, x9
+ 5c0: 1e26006e fmov w14, s3
+ 5c4: 9e66022c fmov x12, d17
+ 5c8: 1e270368 fmov s8, w27
+ 5cc: 9e67039d fmov d29, x28
+ 5d0: 1e3e2000 fcmp s0, s30
+ 5d4: 1e692180 fcmp d12, d9
+ 5d8: 1e202148 fcmp s10, #0.0
+ 5dc: 1e602328 fcmp d25, #0.0
+ 5e0: 292e7b68 stp w8, w30, [x27, #-144]
+ 5e4: 294a4f15 ldp w21, w19, [x24, #80]
+ 5e8: 69626c50 ldpsw x16, x27, [x2, #-240]
+ 5ec: a93814d5 stp x21, x5, [x6, #-128]
+ 5f0: a97e679d ldp x29, x25, [x28, #-32]
+ 5f4: 29903408 stp w8, w13, [x0, #128]!
+ 5f8: 29ec5039 ldp w25, w20, [x1, #-160]!
+ 5fc: 69fc62ce ldpsw x14, x24, [x22, #-32]!
+ 600: a98504d1 stp x17, x1, [x6, #80]!
+ 604: a9fc4735 ldp x21, x17, [x25, #-64]!
+ 608: 28b05691 stp w17, w21, [x20], #-128
+ 60c: 28c8705c ldp w28, w28, [x2], #64
+ 610: 68e07953 ldpsw x19, x30, [x10], #-256
+ 614: a8bf3e31 stp x17, x15, [x17], #-16
+ 618: a8fe0331 ldp x17, x0, [x25], #-32
+ 61c: 283c170e stnp w14, w5, [x24, #-32]
+ 620: 284e4c37 ldnp w23, w19, [x1, #112]
+ 624: a80419cb stnp x11, x6, [x14, #64]
+ 628: a8722f62 ldnp x2, x11, [x27, #-224]
+ 62c: 0c407230 ld1 {v16.8b}, [x17]
+ 630: 4cdfa13d ld1 {v29.16b, v30.16b}, [x9], #32
+ 634: 0cd56f1e ld1 {v30.1d, v31.1d, v0.1d}, [x24], x21
+ 638: 4cdf2440 ld1 {v0.8h-v3.8h}, [x2], #64
+ 63c: 0d40c134 ld1r {v20.8b}, [x9]
+ 640: 4ddfc811 ld1r {v17.4s}, [x0], #4
+ 644: 0ddaced5 ld1r {v21.1d}, [x22], x26
+ 648: 4c408f33 ld2 {v19.2d, v20.2d}, [x25]
+ 64c: 0cdf84aa ld2 {v10.4h, v11.4h}, [x5], #16
+ 650: 4d60c30a ld2r {v10.16b, v11.16b}, [x24]
+ 654: 0dffcbad ld2r {v13.2s, v14.2s}, [x29], #8
+ 658: 4de2cf96 ld2r {v22.2d, v23.2d}, [x28], x2
+ 65c: 4ccb489e ld3 {v30.4s, v31.4s, v0.4s}, [x4], x11
+ 660: 0c40481d ld3 {v29.2s-v31.2s}, [x0]
+ 664: 4d40e777 ld3r {v23.8h-v25.8h}, [x27]
+ 668: 4ddfe943 ld3r {v3.4s-v5.4s}, [x10], #12
+ 66c: 0dd6edd3 ld3r {v19.1d-v21.1d}, [x14], x22
+ 670: 4cdf040e ld4 {v14.8h-v17.8h}, [x0], #64
+ 674: 0cd902de ld4 {v30.8b, v31.8b, v0.8b, v1.8b}, [x22], x25
+ 678: 0d60e019 ld4r {v25.8b-v28.8b}, [x0]
+ 67c: 0dffe50a ld4r {v10.4h-v13.4h}, [x8], #8
+ 680: 0dfce8c1 ld4r {v1.2s-v4.2s}, [x6], x28
+ 684: ba5fd3e3 ccmn xzr, xzr, #0x3, le
+ 688: 3a5f03e5 ccmn wzr, wzr, #0x5, eq // eq = none
+ 68c: fa411be4 ccmp xzr, #0x1, #0x4, ne // ne = any
+ 690: 7a42cbe2 ccmp wzr, #0x2, #0x2, gt
+ 694: 93df03ff ror xzr, xzr, #0
+ 698: c820ffff stlxp w0, xzr, xzr, [sp]
+ 69c: 8822fc7f stlxp w2, wzr, wzr, [x3]
+ 6a0: c8247cbf stxp w4, xzr, xzr, [x5]
+ 6a4: 88267fff stxp w6, wzr, wzr, [sp]
+ 6a8: 4e010fe0 dup v0.16b, wzr
+ 6ac: 4e081fe1 mov v1.d[0], xzr
+ 6b0: 4e0c1fe1 mov v1.s[1], wzr
+ 6b4: 4e0a1fe1 mov v1.h[2], wzr
+ 6b8: 4e071fe1 mov v1.b[3], wzr
+ 6bc: 4cc0ac3f ld1 {v31.2d, v0.2d}, [x1], x0
+ 6c0: 1e601000 fmov d0, #2.000000000000000000e+00
+ 6c4: 1e603000 fmov d0, #2.125000000000000000e+00
+ 6c8: 1e621000 fmov d0, #4.000000000000000000e+00
+ 6cc: 1e623000 fmov d0, #4.250000000000000000e+00
+ 6d0: 1e641000 fmov d0, #8.000000000000000000e+00
+ 6d4: 1e643000 fmov d0, #8.500000000000000000e+00
+ 6d8: 1e661000 fmov d0, #1.600000000000000000e+01
+ 6dc: 1e663000 fmov d0, #1.700000000000000000e+01
+ 6e0: 1e681000 fmov d0, #1.250000000000000000e-01
+ 6e4: 1e683000 fmov d0, #1.328125000000000000e-01
+ 6e8: 1e6a1000 fmov d0, #2.500000000000000000e-01
+ 6ec: 1e6a3000 fmov d0, #2.656250000000000000e-01
+ 6f0: 1e6c1000 fmov d0, #5.000000000000000000e-01
+ 6f4: 1e6c3000 fmov d0, #5.312500000000000000e-01
+ 6f8: 1e6e1000 fmov d0, #1.000000000000000000e+00
+ 6fc: 1e6e3000 fmov d0, #1.062500000000000000e+00
+ 700: 1e701000 fmov d0, #-2.000000000000000000e+00
+ 704: 1e703000 fmov d0, #-2.125000000000000000e+00
+ 708: 1e721000 fmov d0, #-4.000000000000000000e+00
+ 70c: 1e723000 fmov d0, #-4.250000000000000000e+00
+ 710: 1e741000 fmov d0, #-8.000000000000000000e+00
+ 714: 1e743000 fmov d0, #-8.500000000000000000e+00
+ 718: 1e761000 fmov d0, #-1.600000000000000000e+01
+ 71c: 1e763000 fmov d0, #-1.700000000000000000e+01
+ 720: 1e781000 fmov d0, #-1.250000000000000000e-01
+ 724: 1e783000 fmov d0, #-1.328125000000000000e-01
+ 728: 1e7a1000 fmov d0, #-2.500000000000000000e-01
+ 72c: 1e7a3000 fmov d0, #-2.656250000000000000e-01
+ 730: 1e7c1000 fmov d0, #-5.000000000000000000e-01
+ 734: 1e7c3000 fmov d0, #-5.312500000000000000e-01
+ 738: 1e7e1000 fmov d0, #-1.000000000000000000e+00
+ 73c: 1e7e3000 fmov d0, #-1.062500000000000000e+00
+ 740: f83081f4 swp x16, x20, [x15]
+ 744: f8220387 ldadd x2, x7, [x28]
+ 748: f834132a ldclr x20, x10, [x25]
+ 74c: f836204b ldeor x22, x11, [x2]
+ 750: f821326a ldset x1, x10, [x19]
+ 754: f82e5075 ldsmin x14, x21, [x3]
+ 758: f83c41bb ldsmax x28, x27, [x13]
+ 75c: f83172be ldumin x17, x30, [x21]
+ 760: f83b63b0 ldumax x27, x16, [x29]
+ 764: f8be8009 swpa x30, x9, [x0]
+ 768: f8bc039b ldadda x28, x27, [x28]
+ 76c: f8b51159 ldclra x21, x25, [x10]
+ 770: f8bf21f4 ldeora xzr, x20, [x15]
+ 774: f8a131d9 ldseta x1, x25, [x14]
+ 778: f8b553ba ldsmina x21, x26, [x29]
+ 77c: f8a8433d ldsmaxa x8, x29, [x25]
+ 780: f8ad7322 ldumina x13, x2, [x25]
+ 784: f8af6017 ldumaxa x15, x23, [x0]
+ 788: f8e38041 swpal x3, x1, [x2]
+ 78c: f8fc0283 ldaddal x28, x3, [x20]
+ 790: f8ee11df ldclral x14, xzr, [x14]
+ 794: f8e7205c ldeoral x7, x28, [x2]
+ 798: f8e030ab ldsetal x0, x11, [x5]
+ 79c: f8eb528e ldsminal x11, x14, [x20]
+ 7a0: f8ff4044 ldsmaxal xzr, x4, [x2]
+ 7a4: f8fa72c0 lduminal x26, x0, [x22]
+ 7a8: f8f161a1 ldumaxal x17, x1, [x13]
+ 7ac: f877829a swpl x23, x26, [x20]
+ 7b0: f86e018b ldaddl x14, x11, [x12]
+ 7b4: f86c11ff stclrl x12, [x15]
+ 7b8: f87b210e ldeorl x27, x14, [x8]
+ 7bc: f86a333e ldsetl x10, x30, [x25]
+ 7c0: f8765207 ldsminl x22, x7, [x16]
+ 7c4: f8614110 ldsmaxl x1, x16, [x8]
+ 7c8: f8617341 lduminl x1, x1, [x26]
+ 7cc: f86061f7 ldumaxl x0, x23, [x15]
+ 7d0: b82b8110 swp w11, w16, [x8]
+ 7d4: b82101c7 ldadd w1, w7, [x14]
+ 7d8: b830113f stclr w16, [x9]
+ 7dc: b83621a6 ldeor w22, w6, [x13]
+ 7e0: b82b308d ldset w11, w13, [x4]
+ 7e4: b8305016 ldsmin w16, w22, [x0]
+ 7e8: b83c415f stsmax w28, [x10]
+ 7ec: b8307105 ldumin w16, w5, [x8]
+ 7f0: b83a61f4 ldumax w26, w20, [x15]
+ 7f4: b8bb8206 swpa w27, w6, [x16]
+ 7f8: b8bf005f ldadda wzr, wzr, [x2]
+ 7fc: b8b8111c ldclra w24, w28, [x8]
+ 800: b8af22e9 ldeora w15, w9, [x23]
+ 804: b8ba30e2 ldseta w26, w2, [x7]
+ 808: b8a351f1 ldsmina w3, w17, [x15]
+ 80c: b8b342a5 ldsmaxa w19, w5, [x21]
+ 810: b8a7719a ldumina w7, w26, [x12]
+ 814: b8ac63a7 ldumaxa w12, w7, [x29]
+ 818: b8e98288 swpal w9, w8, [x20]
+ 81c: b8e803df ldaddal w8, wzr, [x30]
+ 820: b8e01186 ldclral w0, w6, [x12]
+ 824: b8f12057 ldeoral w17, w23, [x2]
+ 828: b8e0303e ldsetal w0, w30, [x1]
+ 82c: b8f651e3 ldsminal w22, w3, [x15]
+ 830: b8f941b5 ldsmaxal w25, w21, [x13]
+ 834: b8ed7378 lduminal w13, w24, [x27]
+ 838: b8f46163 ldumaxal w20, w3, [x11]
+ 83c: b86382ad swpl w3, w13, [x21]
+ 840: b87a034f ldaddl w26, w15, [x26]
+ 844: b8691053 ldclrl w9, w19, [x2]
+ 848: b87820fd ldeorl w24, w29, [x7]
+ 84c: b87d31f9 ldsetl w29, w25, [x15]
+ 850: b86b50fe ldsminl w11, w30, [x7]
+ 854: b86b40c2 ldsmaxl w11, w2, [x6]
+ 858: b87071cb lduminl w16, w11, [x14]
+ 85c: b8656168 ldumaxl w5, w8, [x11]
*/
static const unsigned int insns[] =
{
- 0x8b0772d3, 0xcb4a3570, 0xab9c09bb, 0xeb9aa794,
- 0x0b934e68, 0x4b0a3924, 0x2b1e3568, 0x6b132720,
- 0x8a154c14, 0xaa1445d5, 0xca01cf99, 0xea8b3f6a,
- 0x0a8c5cb9, 0x2a4a11d2, 0x4a855aa4, 0x6a857415,
- 0x8aa697da, 0xaa6d7423, 0xca29bf80, 0xea3cb8bd,
- 0x0a675249, 0x2ab961ba, 0x4a331899, 0x6a646345,
- 0x11055267, 0x31064408, 0x51028e9d, 0x710bdee8,
- 0x91082d81, 0xb106a962, 0xd10b33ae, 0xf10918ab,
- 0x121102d7, 0x3204cd44, 0x5204cf00, 0x72099fb3,
- 0x92729545, 0xb20e37cc, 0xd27c34be, 0xf27e4efa,
- 0x14000000, 0x17ffffd7, 0x1400017f, 0x94000000,
- 0x97ffffd4, 0x9400017c, 0x3400000c, 0x34fffa2c,
- 0x34002f2c, 0x35000014, 0x35fff9d4, 0x35002ed4,
- 0xb400000c, 0xb4fff96c, 0xb4002e6c, 0xb5000018,
- 0xb5fff918, 0xb5002e18, 0x10000006, 0x10fff8a6,
- 0x10002da6, 0x90000015, 0x36080001, 0x360ff821,
- 0x36082d21, 0x37480008, 0x374ff7c8, 0x37482cc8,
- 0x128b50ec, 0x52a9ff8b, 0x7281d095, 0x92edfebd,
- 0xd28361e3, 0xf2a4cc96, 0x9346590c, 0x33194f33,
- 0x531d3d89, 0x9350433c, 0xb34464ac, 0xd3462140,
- 0x139a61a4, 0x93d87fd7, 0x54000000, 0x54fff5a0,
- 0x54002aa0, 0x54000001, 0x54fff541, 0x54002a41,
- 0x54000002, 0x54fff4e2, 0x540029e2, 0x54000002,
- 0x54fff482, 0x54002982, 0x54000003, 0x54fff423,
- 0x54002923, 0x54000003, 0x54fff3c3, 0x540028c3,
- 0x54000004, 0x54fff364, 0x54002864, 0x54000005,
- 0x54fff305, 0x54002805, 0x54000006, 0x54fff2a6,
- 0x540027a6, 0x54000007, 0x54fff247, 0x54002747,
- 0x54000008, 0x54fff1e8, 0x540026e8, 0x54000009,
- 0x54fff189, 0x54002689, 0x5400000a, 0x54fff12a,
- 0x5400262a, 0x5400000b, 0x54fff0cb, 0x540025cb,
- 0x5400000c, 0x54fff06c, 0x5400256c, 0x5400000d,
- 0x54fff00d, 0x5400250d, 0x5400000e, 0x54ffefae,
- 0x540024ae, 0x5400000f, 0x54ffef4f, 0x5400244f,
- 0xd4063721, 0xd4035082, 0xd400bfe3, 0xd4282fc0,
- 0xd444c320, 0xd503201f, 0xd69f03e0, 0xd6bf03e0,
- 0xd5033fdf, 0xd5033f9f, 0xd5033abf, 0xd61f0040,
- 0xd63f00a0, 0xc8147c55, 0xc805fcfd, 0xc85f7e05,
- 0xc85fffbb, 0xc89fffa0, 0xc8dfff95, 0x88157cf8,
- 0x8815ff9a, 0x885f7cd5, 0x885fffcf, 0x889ffc73,
- 0x88dffc56, 0x48127c0f, 0x480bff85, 0x485f7cdd,
- 0x485ffcf2, 0x489fff99, 0x48dffe62, 0x080a7c3e,
- 0x0814fed5, 0x085f7c59, 0x085ffcb8, 0x089ffc70,
- 0x08dfffb6, 0xc87f0a68, 0xc87fcdc7, 0xc82870bb,
- 0xc825b8c8, 0x887f12d9, 0x887fb9ed, 0x8834215a,
- 0x8837ca52, 0xf806317e, 0xb81b3337, 0x39000dc2,
- 0x78005149, 0xf84391f4, 0xb85b220c, 0x385fd356,
- 0x785d127e, 0x389f4149, 0x79801e3c, 0x79c014a3,
- 0xb89a5231, 0xfc5ef282, 0xbc5f60f6, 0xfc12125e,
- 0xbc0152cd, 0xf8190e49, 0xb800befd, 0x381ffd92,
- 0x781e9e90, 0xf8409fa3, 0xb8413c79, 0x385fffa1,
- 0x785c7fa8, 0x389f3dc5, 0x78801f6a, 0x78c19d4b,
- 0xb89a4ec4, 0xfc408eeb, 0xbc436e79, 0xfc152ce1,
- 0xbc036f28, 0xf8025565, 0xb80135f8, 0x381ff74f,
- 0x781fa652, 0xf851a447, 0xb85e557b, 0x385e7472,
- 0x785e070a, 0x38804556, 0x78819591, 0x78dc24e8,
- 0xb89cd6d7, 0xfc430738, 0xbc5f6595, 0xfc1225b2,
- 0xbc1d7430, 0xf82fcac2, 0xb83d6a02, 0x382e5a54,
- 0x7834fa66, 0xf86ecbae, 0xb86cda90, 0x3860d989,
- 0x78637a2c, 0x38a3fa22, 0x78b15827, 0x78f2d9f9,
- 0xb8ac6ab7, 0xfc6879a5, 0xbc767943, 0xfc3bc84e,
- 0xbc3968d4, 0xf91fc0fe, 0xb91da50f, 0x391d280b,
- 0x791d2e23, 0xf95bc8e2, 0xb95ce525, 0x395ae53c,
- 0x795c9282, 0x399d7dd6, 0x799fe008, 0x79de9bc0,
- 0xb99aae78, 0xfd597598, 0xbd5d1d08, 0xfd1f3dea,
- 0xbd1a227a, 0x5800148a, 0x18000003, 0xf88092e0,
- 0xd8ffdf00, 0xf8a84860, 0xf99d7560, 0x1a1c012d,
- 0x3a1c027b, 0x5a060253, 0x7a03028e, 0x9a0801d0,
- 0xba0803a0, 0xda140308, 0xfa00038c, 0x0b3010d7,
- 0x2b37ab39, 0xcb2466da, 0x6b33efb1, 0x8b350fcb,
- 0xab208a70, 0xcb39e52b, 0xeb2c9291, 0x3a4bd1a3,
- 0x7a4c81a2, 0xba42106c, 0xfa5560e3, 0x3a4e3844,
- 0x7a515a26, 0xba4c2940, 0xfa52aaae, 0x1a8cc1b5,
- 0x1a8f976a, 0x5a8981a0, 0x5a9a6492, 0x9a8793ac,
- 0x9a9474e6, 0xda83d2b6, 0xda9b9593, 0x5ac00200,
- 0x5ac006f1, 0x5ac009d1, 0x5ac013d8, 0x5ac016d8,
- 0xdac00223, 0xdac005ac, 0xdac00ac9, 0xdac00c00,
- 0xdac01205, 0xdac016d9, 0x1ac0089d, 0x1add0fa0,
- 0x1ad52225, 0x1ad22529, 0x1ac82b61, 0x1acd2e92,
- 0x9acc0b28, 0x9adc0ca7, 0x9adb2225, 0x9ad42757,
- 0x9adc291c, 0x9ac42fa3, 0x1b1a55d1, 0x1b0bafc1,
- 0x9b067221, 0x9b1ea0de, 0x9b2e20d5, 0x9b38cd4a,
- 0x9bae6254, 0x9ba59452, 0x1e2d0a48, 0x1e3c19c2,
- 0x1e3c298f, 0x1e213980, 0x1e240baf, 0x1e77082c,
- 0x1e72191b, 0x1e6b2a97, 0x1e723988, 0x1e770b1a,
- 0x1f0d66f5, 0x1f01b956, 0x1f227a8e, 0x1f365ba7,
- 0x1f4f14ad, 0x1f45a98e, 0x1f60066a, 0x1f620054,
- 0x1e204139, 0x1e20c094, 0x1e214363, 0x1e21c041,
- 0x1e22c01e, 0x1e60408c, 0x1e60c361, 0x1e6142c8,
- 0x1e61c16b, 0x1e624396, 0x1e3802dc, 0x9e380374,
- 0x1e78000e, 0x9e78017a, 0x1e2202dc, 0x9e220150,
- 0x1e6202a8, 0x9e620395, 0x1e260318, 0x9e660268,
- 0x1e270188, 0x9e6700e6, 0x1e3023c0, 0x1e6b2320,
- 0x1e202168, 0x1e602168, 0x2910323d, 0x297449d6,
- 0x6948402b, 0xa9072f40, 0xa9410747, 0x29801f0a,
- 0x29e07307, 0x69e272b9, 0xa9bf49d4, 0xa9c529a8,
- 0x28b0605a, 0x28e866a2, 0x68ee0ab1, 0xa886296c,
- 0xa8fe1a38, 0x282479c3, 0x286e534f, 0xa8386596,
- 0xa8755a3b, 0x1e601000, 0x1e603000, 0x1e621000,
- 0x1e623000, 0x1e641000, 0x1e643000, 0x1e661000,
- 0x1e663000, 0x1e681000, 0x1e683000, 0x1e6a1000,
- 0x1e6a3000, 0x1e6c1000, 0x1e6c3000, 0x1e6e1000,
- 0x1e6e3000, 0x1e701000, 0x1e703000, 0x1e721000,
- 0x1e723000, 0x1e741000, 0x1e743000, 0x1e761000,
- 0x1e763000, 0x1e781000, 0x1e783000, 0x1e7a1000,
- 0x1e7a3000, 0x1e7c1000, 0x1e7c3000, 0x1e7e1000,
- 0x1e7e3000,
+ 0x8b18ec0f, 0xcb9636d1, 0xab1ce74a, 0xeb184a19,
+ 0x0b1c1ca8, 0x4b817388, 0x2b01004c, 0x6b5164b7,
+ 0x8a0d5595, 0xaa9791f5, 0xca9bc316, 0xea82d1f6,
+ 0x0a980e21, 0x2a862c45, 0x4a453037, 0x6a8e5180,
+ 0x8a621cc1, 0xaa24bd1e, 0xcab4d6d1, 0xeaa591fd,
+ 0x0a7d6efe, 0x2a2253ac, 0x4aa61187, 0x6aa755b0,
+ 0x110b5a25, 0x31056e0a, 0x510f48ba, 0x710ac715,
+ 0x910f6e0a, 0xb10a65ef, 0xd1009e98, 0xf10131aa,
+ 0x121d4e67, 0x32043e25, 0x52132390, 0x72160b0e,
+ 0x9273e76e, 0xb256416c, 0xd24b5002, 0xf266da8d,
+ 0x14000000, 0x17ffffd7, 0x140001ee, 0x94000000,
+ 0x97ffffd4, 0x940001eb, 0x3400000f, 0x34fffa2f,
+ 0x34003d0f, 0x3500001c, 0x35fff9dc, 0x35003cbc,
+ 0xb400001b, 0xb4fff97b, 0xb4003c5b, 0xb5000000,
+ 0xb5fff900, 0xb5003be0, 0x1000000d, 0x10fff8ad,
+ 0x10003b8d, 0x90000003, 0x36380015, 0x363ff835,
+ 0x36383b15, 0x3748000f, 0x374ff7cf, 0x37483aaf,
+ 0x12a14bee, 0x5283bb51, 0x72858ebb, 0x92c98881,
+ 0xd2aa50d4, 0xf2afd9d4, 0x935c504d, 0x33133e90,
+ 0x5309196b, 0x93595482, 0xb3424e0d, 0xd3481728,
+ 0x138a3b7d, 0x93c66286, 0x54000000, 0x54fff5a0,
+ 0x54003880, 0x54000001, 0x54fff541, 0x54003821,
+ 0x54000002, 0x54fff4e2, 0x540037c2, 0x54000002,
+ 0x54fff482, 0x54003762, 0x54000003, 0x54fff423,
+ 0x54003703, 0x54000003, 0x54fff3c3, 0x540036a3,
+ 0x54000004, 0x54fff364, 0x54003644, 0x54000005,
+ 0x54fff305, 0x540035e5, 0x54000006, 0x54fff2a6,
+ 0x54003586, 0x54000007, 0x54fff247, 0x54003527,
+ 0x54000008, 0x54fff1e8, 0x540034c8, 0x54000009,
+ 0x54fff189, 0x54003469, 0x5400000a, 0x54fff12a,
+ 0x5400340a, 0x5400000b, 0x54fff0cb, 0x540033ab,
+ 0x5400000c, 0x54fff06c, 0x5400334c, 0x5400000d,
+ 0x54fff00d, 0x540032ed, 0x5400000e, 0x54ffefae,
+ 0x5400328e, 0x5400000f, 0x54ffef4f, 0x5400322f,
+ 0xd40d2881, 0xd40ea5c2, 0xd40518a3, 0xd42eca40,
+ 0xd44a2e60, 0xd503201f, 0xd69f03e0, 0xd6bf03e0,
+ 0xd5033fdf, 0xd5033d9f, 0xd5033bbf, 0xd61f0120,
+ 0xd63f0120, 0xc8027d7d, 0xc816ff85, 0xc85f7e8e,
+ 0xc85ffe7d, 0xc89ffea6, 0xc8dffc73, 0x880c7f63,
+ 0x8811fdfa, 0x885f7dcd, 0x885fff4c, 0x889ffe28,
+ 0x88dfffd5, 0x48007d6f, 0x4811fc34, 0x485f7d1d,
+ 0x485ffd91, 0x489ffc8b, 0x48dffc90, 0x080e7c85,
+ 0x081bfe11, 0x085f7f66, 0x085fff1b, 0x089ffe8a,
+ 0x08dfff49, 0xc87f7b85, 0xc87fa66a, 0xc82b5590,
+ 0xc82adc94, 0x887f0416, 0x887f8503, 0x88205fc9,
+ 0x8837c560, 0xf81e1146, 0xb81fb007, 0x381f3205,
+ 0x7801f27e, 0xf8477130, 0xb843b208, 0x385f918a,
+ 0x785da12e, 0x389f83d8, 0x78817087, 0x78dd91d1,
+ 0xb89e136b, 0xfc4410ec, 0xbc5fe200, 0xfc15f2ed,
+ 0xbc1c2075, 0xf8064ca2, 0xb81a4c29, 0x381fbfdb,
+ 0x7800cdfb, 0xf852ce24, 0xb841eef5, 0x385f9e2d,
+ 0x785cec19, 0x389ebea1, 0x789caebc, 0x78c02c8b,
+ 0xb883dd31, 0xfc427e7d, 0xbc5abed6, 0xfc11ff29,
+ 0xbc1f1c49, 0xf81be6ed, 0xb800a611, 0x381e05c1,
+ 0x78006411, 0xf855473b, 0xb85da72d, 0x385e372b,
+ 0x784144be, 0x389f94e9, 0x789c2460, 0x78c1f5c7,
+ 0xb8827771, 0xfc515491, 0xbc4226ba, 0xfc1c7625,
+ 0xbc1935ad, 0xf824da06, 0xb834db09, 0x38237ba3,
+ 0x783e6a2a, 0xf867497b, 0xb87949ee, 0x387379d8,
+ 0x7866c810, 0x38acd98a, 0x78b0499a, 0x78ee781a,
+ 0xb8bbf971, 0xfc73d803, 0xbc6979fa, 0xfc30e9ab,
+ 0xbc355a7a, 0xf91886a8, 0xb918ef6a, 0x391b15db,
+ 0x791ac0f0, 0xf958753b, 0xb95a1958, 0x395b3f18,
+ 0x795800b4, 0x39988891, 0x799a81ae, 0x79dd172a,
+ 0xb9981342, 0xfd5d21da, 0xbd5e7c9c, 0xfd1b526e,
+ 0xbd18df97, 0x58002268, 0x18ffdf51, 0xf8951080,
+ 0xd8000000, 0xf8a4c900, 0xf999e180, 0x1a150374,
+ 0x3a060227, 0x5a1900c5, 0x7a0e017e, 0x9a0b0223,
+ 0xba110159, 0xda170207, 0xfa050144, 0x0b2973c9,
+ 0x2b30a8a0, 0xcb3b8baf, 0x6b21f12b, 0x8b264f02,
+ 0xab3a70d3, 0xcb39ef48, 0xeb29329a, 0x3a5a41a7,
+ 0x7a54310f, 0xba4302c8, 0xfa58a04a, 0x3a50490d,
+ 0x7a4c0a01, 0xba5f79e3, 0xfa4c0aef, 0x1a9a30ee,
+ 0x1a9ed763, 0x5a9702ab, 0x5a95c7da, 0x9a8d835c,
+ 0x9a909471, 0xda8380ab, 0xda93c461, 0x5ac00120,
+ 0x5ac005da, 0x5ac00a2d, 0x5ac0128b, 0x5ac0163c,
+ 0xdac0008d, 0xdac007c1, 0xdac009cd, 0xdac00d05,
+ 0xdac01322, 0xdac01514, 0x1adb0b35, 0x1ad00d4d,
+ 0x1ad1203c, 0x1aca26f9, 0x1ac72867, 0x1ace2fce,
+ 0x9acf0acc, 0x9acd0f22, 0x9ad522e7, 0x9ac0258b,
+ 0x9adc293e, 0x9ad62cad, 0x9bc47ea5, 0x9b477c51,
+ 0x1b11318c, 0x1b01edfe, 0x9b117662, 0x9b03fae4,
+ 0x9b313eef, 0x9b21b59b, 0x9bac45a6, 0x9ba6a839,
+ 0x1e240871, 0x1e3518b0, 0x1e312b63, 0x1e2f3959,
+ 0x1e200a2a, 0x1e630b5c, 0x1e7b1804, 0x1e6229dc,
+ 0x1e773b4c, 0x1e610bcf, 0x1f0534a4, 0x1f1c85b5,
+ 0x1f3d1c71, 0x1f3d6b37, 0x1f5e68ee, 0x1f4aa4f6,
+ 0x1f6e24e7, 0x1f6f630e, 0x1e204056, 0x1e20c060,
+ 0x1e214229, 0x1e21c178, 0x1e22c32f, 0x1e604064,
+ 0x1e60c2da, 0x1e61427e, 0x1e61c1cc, 0x1e6240f1,
+ 0x1e3801d8, 0x9e38034d, 0x1e780022, 0x9e780165,
+ 0x1e22026e, 0x9e2202c1, 0x1e62023b, 0x9e620136,
+ 0x1e26006e, 0x9e66022c, 0x1e270368, 0x9e67039d,
+ 0x1e3e2000, 0x1e692180, 0x1e202148, 0x1e602328,
+ 0x292e7b68, 0x294a4f15, 0x69626c50, 0xa93814d5,
+ 0xa97e679d, 0x29903408, 0x29ec5039, 0x69fc62ce,
+ 0xa98504d1, 0xa9fc4735, 0x28b05691, 0x28c8705c,
+ 0x68e07953, 0xa8bf3e31, 0xa8fe0331, 0x283c170e,
+ 0x284e4c37, 0xa80419cb, 0xa8722f62, 0x0c407230,
+ 0x4cdfa13d, 0x0cd56f1e, 0x4cdf2440, 0x0d40c134,
+ 0x4ddfc811, 0x0ddaced5, 0x4c408f33, 0x0cdf84aa,
+ 0x4d60c30a, 0x0dffcbad, 0x4de2cf96, 0x4ccb489e,
+ 0x0c40481d, 0x4d40e777, 0x4ddfe943, 0x0dd6edd3,
+ 0x4cdf040e, 0x0cd902de, 0x0d60e019, 0x0dffe50a,
+ 0x0dfce8c1, 0xba5fd3e3, 0x3a5f03e5, 0xfa411be4,
+ 0x7a42cbe2, 0x93df03ff, 0xc820ffff, 0x8822fc7f,
+ 0xc8247cbf, 0x88267fff, 0x4e010fe0, 0x4e081fe1,
+ 0x4e0c1fe1, 0x4e0a1fe1, 0x4e071fe1, 0x4cc0ac3f,
+ 0x1e601000, 0x1e603000, 0x1e621000, 0x1e623000,
+ 0x1e641000, 0x1e643000, 0x1e661000, 0x1e663000,
+ 0x1e681000, 0x1e683000, 0x1e6a1000, 0x1e6a3000,
+ 0x1e6c1000, 0x1e6c3000, 0x1e6e1000, 0x1e6e3000,
+ 0x1e701000, 0x1e703000, 0x1e721000, 0x1e723000,
+ 0x1e741000, 0x1e743000, 0x1e761000, 0x1e763000,
+ 0x1e781000, 0x1e783000, 0x1e7a1000, 0x1e7a3000,
+ 0x1e7c1000, 0x1e7c3000, 0x1e7e1000, 0x1e7e3000,
+ 0xf83081f4, 0xf8220387, 0xf834132a, 0xf836204b,
+ 0xf821326a, 0xf82e5075, 0xf83c41bb, 0xf83172be,
+ 0xf83b63b0, 0xf8be8009, 0xf8bc039b, 0xf8b51159,
+ 0xf8bf21f4, 0xf8a131d9, 0xf8b553ba, 0xf8a8433d,
+ 0xf8ad7322, 0xf8af6017, 0xf8e38041, 0xf8fc0283,
+ 0xf8ee11df, 0xf8e7205c, 0xf8e030ab, 0xf8eb528e,
+ 0xf8ff4044, 0xf8fa72c0, 0xf8f161a1, 0xf877829a,
+ 0xf86e018b, 0xf86c11ff, 0xf87b210e, 0xf86a333e,
+ 0xf8765207, 0xf8614110, 0xf8617341, 0xf86061f7,
+ 0xb82b8110, 0xb82101c7, 0xb830113f, 0xb83621a6,
+ 0xb82b308d, 0xb8305016, 0xb83c415f, 0xb8307105,
+ 0xb83a61f4, 0xb8bb8206, 0xb8bf005f, 0xb8b8111c,
+ 0xb8af22e9, 0xb8ba30e2, 0xb8a351f1, 0xb8b342a5,
+ 0xb8a7719a, 0xb8ac63a7, 0xb8e98288, 0xb8e803df,
+ 0xb8e01186, 0xb8f12057, 0xb8e0303e, 0xb8f651e3,
+ 0xb8f941b5, 0xb8ed7378, 0xb8f46163, 0xb86382ad,
+ 0xb87a034f, 0xb8691053, 0xb87820fd, 0xb87d31f9,
+ 0xb86b50fe, 0xb86b40c2, 0xb87071cb, 0xb8656168,
+
};
// END Generated code -- do not edit
@@ -1223,7 +1493,7 @@
Disassembler::decode((address)start, (address)start + len);
}
- JNIEXPORT void das1(unsigned long insn) {
+ JNIEXPORT void das1(uintptr_t insn) {
das(insn, 1);
}
}
@@ -1247,7 +1517,7 @@
break;
}
case base_plus_offset_reg: {
- __ add(r, _base, _index, _ext.op(), MAX(_ext.shift(), 0));
+ __ add(r, _base, _index, _ext.op(), MAX2(_ext.shift(), 0));
break;
}
case literal: {
@@ -1262,7 +1532,7 @@
}
}
-void Assembler::adrp(Register reg1, const Address &dest, unsigned long &byte_offset) {
+void Assembler::adrp(Register reg1, const Address &dest, uint64_t &byte_offset) {
ShouldNotReachHere();
}
@@ -1271,7 +1541,7 @@
#define starti Instruction_aarch64 do_not_use(this); set_current(&do_not_use)
void Assembler::adr(Register Rd, address adr) {
- long offset = adr - pc();
+ intptr_t offset = adr - pc();
int offset_lo = offset & 3;
offset >>= 2;
starti;
@@ -1282,7 +1552,7 @@
void Assembler::_adrp(Register Rd, address adr) {
uint64_t pc_page = (uint64_t)pc() >> 12;
uint64_t adr_page = (uint64_t)adr >> 12;
- long offset = adr_page - pc_page;
+ intptr_t offset = adr_page - pc_page;
int offset_lo = offset & 3;
offset >>= 2;
starti;
@@ -1431,9 +1701,8 @@
srf(Rn, 5);
}
-bool Assembler::operand_valid_for_add_sub_immediate(long imm) {
- bool shift = false;
- unsigned long uimm = uabs(imm);
+bool Assembler::operand_valid_for_add_sub_immediate(int64_t imm) {
+ uint64_t uimm = (uint64_t)uabs((jlong)imm);
if (uimm < (1 << 12))
return true;
if (uimm < (1 << 24)
@@ -1514,3 +1783,7 @@
ival = fp_immediate_for_encoding(value, 0);
return val;
}
+
+address Assembler::locate_next_instruction(address inst) {
+ return inst + Assembler::instruction_size;
+}
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/assembler_aarch64.hpp openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/assembler_aarch64.hpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/assembler_aarch64.hpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/assembler_aarch64.hpp 2022-01-13 21:56:25.000000000 +0000
@@ -28,6 +28,19 @@
#include "asm/register.hpp"
+#ifdef __GNUC__
+
+// __nop needs volatile so that compiler doesn't optimize it away
+#define NOP() asm volatile ("nop");
+
+#elif defined(_MSC_VER)
+
+// Use MSVC instrinsic: https://docs.microsoft.com/en-us/cpp/intrinsics/arm64-intrinsics?view=vs-2019#I
+#define NOP() __nop();
+
+#endif
+
+
// definitions of various symbolic names for machine registers
// First intercalls between C and Java which use 8 general registers
@@ -199,7 +212,7 @@
return extend(uval, msb - lsb);
}
- static void patch(address a, int msb, int lsb, unsigned long val) {
+ static void patch(address a, int msb, int lsb, uint64_t val) {
int nbits = msb - lsb + 1;
guarantee(val < (1U << nbits), "Field too big for insn");
assert_cond(msb >= lsb);
@@ -212,9 +225,9 @@
*(unsigned *)a = target;
}
- static void spatch(address a, int msb, int lsb, long val) {
+ static void spatch(address a, int msb, int lsb, int64_t val) {
int nbits = msb - lsb + 1;
- long chk = val >> (nbits - 1);
+ int64_t chk = val >> (nbits - 1);
guarantee (chk == -1 || chk == 0, "Field too big for insn");
unsigned uval = val;
unsigned mask = checked_cast(right_n_bits(nbits));
@@ -245,9 +258,9 @@
f(val, bit, bit);
}
- void sf(long val, int msb, int lsb) {
+ void sf(int64_t val, int msb, int lsb) {
int nbits = msb - lsb + 1;
- long chk = val >> (nbits - 1);
+ int64_t chk = val >> (nbits - 1);
guarantee (chk == -1 || chk == 0, "Field too big for insn");
unsigned uval = val;
unsigned mask = checked_cast(right_n_bits(nbits));
@@ -306,10 +319,12 @@
};
class Post : public PrePost {
Register _idx;
+ bool _is_postreg;
public:
- Post(Register reg, int o) : PrePost(reg, o) { _idx = NULL; }
- Post(Register reg, Register idx) : PrePost(reg, 0) { _idx = idx; }
+ Post(Register reg, int o) : PrePost(reg, o) { _idx = NULL; _is_postreg = false; }
+ Post(Register reg, Register idx) : PrePost(reg, 0) { _idx = idx; _is_postreg = true; }
Register idx_reg() { return _idx; }
+ bool is_postreg() {return _is_postreg; }
};
namespace ext
@@ -355,7 +370,7 @@
private:
Register _base;
Register _index;
- long _offset;
+ int64_t _offset;
enum mode _mode;
extend _ext;
@@ -380,8 +395,14 @@
: _base(r), _index(noreg), _offset(o), _mode(base_plus_offset), _target(0) { }
Address(Register r, long o)
: _base(r), _index(noreg), _offset(o), _mode(base_plus_offset), _target(0) { }
+ Address(Register r, long long o)
+ : _base(r), _index(noreg), _offset(o), _mode(base_plus_offset), _target(0) { }
+ Address(Register r, unsigned int o)
+ : _base(r), _index(noreg), _offset(o), _mode(base_plus_offset), _target(0) { }
Address(Register r, unsigned long o)
: _base(r), _index(noreg), _offset(o), _mode(base_plus_offset), _target(0) { }
+ Address(Register r, unsigned long long o)
+ : _base(r), _index(noreg), _offset(o), _mode(base_plus_offset), _target(0) { }
#ifdef ASSERT
Address(Register r, ByteSize disp)
: _base(r), _index(noreg), _offset(in_bytes(disp)), _mode(base_plus_offset), _target(0) { }
@@ -393,7 +414,7 @@
: _base(p.reg()), _offset(p.offset()), _mode(pre) { }
Address(Post p)
: _base(p.reg()), _index(p.idx_reg()), _offset(p.offset()),
- _mode(p.idx_reg() == NULL ? post : post_reg), _target(0) { }
+ _mode(p.is_postreg() ? post_reg : post), _target(0) { }
Address(address target, RelocationHolder const& rspec)
: _mode(literal),
_rspec(rspec),
@@ -420,7 +441,7 @@
"wrong mode");
return _base;
}
- long offset() const {
+ int64_t offset() const {
return _offset;
}
Register index() const {
@@ -594,7 +615,9 @@
InternalAddress(address target) : Address(target, relocInfo::internal_word_type) {}
};
-const int FPUStateSizeInWords = 32 * 2;
+const int FPUStateSizeInWords = FloatRegisterImpl::number_of_registers *
+ FloatRegisterImpl::save_slots_per_register;
+
typedef enum {
PLDL1KEEP = 0b00000, PLDL1STRM, PLDL2KEEP, PLDL2STRM, PLDL3KEEP, PLDL3STRM,
PSTL1KEEP = 0b10000, PSTL1STRM, PSTL2KEEP, PSTL2STRM, PSTL3KEEP, PSTL3STRM,
@@ -604,11 +627,11 @@
class Assembler : public AbstractAssembler {
#ifndef PRODUCT
- static const unsigned long asm_bp;
+ static const uintptr_t asm_bp;
void emit_long(jint x) {
- if ((unsigned long)pc() == asm_bp)
- asm volatile ("nop");
+ if ((uintptr_t)pc() == asm_bp)
+ NOP();
AbstractAssembler::emit_int32(x);
}
#else
@@ -640,6 +663,8 @@
return Address(Post(base, idx));
}
+ static address locate_next_instruction(address inst);
+
Instruction_aarch64* current;
void set_current(Instruction_aarch64* i) { current = i; }
@@ -650,7 +675,7 @@
void f(unsigned val, int msb) {
current->f(val, msb, msb);
}
- void sf(long val, int msb, int lsb) {
+ void sf(int64_t val, int msb, int lsb) {
current->sf(val, msb, lsb);
}
void rf(Register reg, int lsb) {
@@ -700,7 +725,7 @@
wrap_label(Rd, L, &Assembler::_adrp);
}
- void adrp(Register Rd, const Address &dest, unsigned long &offset);
+ void adrp(Register Rd, const Address &dest, uint64_t &offset);
#undef INSN
@@ -791,32 +816,34 @@
#undef INSN
// Bitfield
-#define INSN(NAME, opcode) \
+#define INSN(NAME, opcode, size) \
void NAME(Register Rd, Register Rn, unsigned immr, unsigned imms) { \
starti; \
+ guarantee(size == 1 || (immr < 32 && imms < 32), "incorrect immr/imms");\
f(opcode, 31, 22), f(immr, 21, 16), f(imms, 15, 10); \
zrf(Rn, 5), rf(Rd, 0); \
}
- INSN(sbfmw, 0b0001001100);
- INSN(bfmw, 0b0011001100);
- INSN(ubfmw, 0b0101001100);
- INSN(sbfm, 0b1001001101);
- INSN(bfm, 0b1011001101);
- INSN(ubfm, 0b1101001101);
+ INSN(sbfmw, 0b0001001100, 0);
+ INSN(bfmw, 0b0011001100, 0);
+ INSN(ubfmw, 0b0101001100, 0);
+ INSN(sbfm, 0b1001001101, 1);
+ INSN(bfm, 0b1011001101, 1);
+ INSN(ubfm, 0b1101001101, 1);
#undef INSN
// Extract
-#define INSN(NAME, opcode) \
+#define INSN(NAME, opcode, size) \
void NAME(Register Rd, Register Rn, Register Rm, unsigned imms) { \
starti; \
+ guarantee(size == 1 || imms < 32, "incorrect imms"); \
f(opcode, 31, 21), f(imms, 15, 10); \
- rf(Rm, 16), rf(Rn, 5), rf(Rd, 0); \
+ zrf(Rm, 16), zrf(Rn, 5), zrf(Rd, 0); \
}
- INSN(extrw, 0b00010011100);
- INSN(extr, 0b10010011110);
+ INSN(extrw, 0b00010011100, 0);
+ INSN(extr, 0b10010011110, 1);
#undef INSN
@@ -824,7 +851,7 @@
// architecture. In debug mode we shrink it in order to test
// trampolines, but not so small that branches in the interpreter
// are out of range.
- static const unsigned long branch_range = NOT_DEBUG(128 * M) DEBUG_ONLY(2 * M);
+ static const uint64_t branch_range = NOT_DEBUG(128 * M) DEBUG_ONLY(2 * M);
static bool reachable_from_branch_at(address branch, address target) {
return uabs(target - branch) < branch_range;
@@ -834,7 +861,7 @@
#define INSN(NAME, opcode) \
void NAME(address dest) { \
starti; \
- long offset = (dest - pc()) >> 2; \
+ int64_t offset = (dest - pc()) >> 2; \
DEBUG_ONLY(assert(reachable_from_branch_at(pc(), dest), "debug only")); \
f(opcode, 31), f(0b00101, 30, 26), sf(offset, 25, 0); \
} \
@@ -851,7 +878,7 @@
// Compare & branch (immediate)
#define INSN(NAME, opcode) \
void NAME(Register Rt, address dest) { \
- long offset = (dest - pc()) >> 2; \
+ int64_t offset = (dest - pc()) >> 2; \
starti; \
f(opcode, 31, 24), sf(offset, 23, 5), rf(Rt, 0); \
} \
@@ -869,7 +896,7 @@
// Test & branch (immediate)
#define INSN(NAME, opcode) \
void NAME(Register Rt, int bitpos, address dest) { \
- long offset = (dest - pc()) >> 2; \
+ int64_t offset = (dest - pc()) >> 2; \
int b5 = bitpos >> 5; \
bitpos &= 0x1f; \
starti; \
@@ -890,7 +917,7 @@
{EQ, NE, HS, CS=HS, LO, CC=LO, MI, PL, VS, VC, HI, LS, GE, LT, GT, LE, AL, NV};
void br(Condition cond, address dest) {
- long offset = (dest - pc()) >> 2;
+ int64_t offset = (dest - pc()) >> 2;
starti;
f(0b0101010, 31, 25), f(0, 24), sf(offset, 23, 5), f(0, 4), f(cond, 3, 0);
}
@@ -1110,7 +1137,7 @@
Register Rn, enum operand_size sz, int op, bool ordered) {
starti;
f(sz, 31, 30), f(0b001000, 29, 24), f(op, 23, 21);
- rf(Rs, 16), f(ordered, 15), rf(Rt2, 10), srf(Rn, 5), zrf(Rt1, 0);
+ rf(Rs, 16), f(ordered, 15), zrf(Rt2, 10), srf(Rn, 5), zrf(Rt1, 0);
}
void load_exclusive(Register dst, Register addr,
@@ -1239,7 +1266,7 @@
enum operand_size sz, int op1, int op2, bool a, bool r) {
starti;
f(sz, 31, 30), f(0b111000, 29, 24), f(a, 23), f(r, 22), f(1, 21);
- rf(Rs, 16), f(op1, 15), f(op2, 14, 12), f(0, 11, 10), rf(Rn, 5), zrf(Rt, 0);
+ zrf(Rs, 16), f(op1, 15), f(op2, 14, 12), f(0, 11, 10), srf(Rn, 5), zrf(Rt, 0);
}
#define INSN(NAME, NAME_A, NAME_L, NAME_AL, op1, op2) \
@@ -1269,7 +1296,7 @@
// Load register (literal)
#define INSN(NAME, opc, V) \
void NAME(Register Rt, address dest) { \
- long offset = (dest - pc()) >> 2; \
+ int64_t offset = (dest - pc()) >> 2; \
starti; \
f(opc, 31, 30), f(0b011, 29, 27), f(V, 26), f(0b00, 25, 24), \
sf(offset, 23, 5); \
@@ -1294,7 +1321,7 @@
#define INSN(NAME, opc, V) \
void NAME(FloatRegister Rt, address dest) { \
- long offset = (dest - pc()) >> 2; \
+ int64_t offset = (dest - pc()) >> 2; \
starti; \
f(opc, 31, 30), f(0b011, 29, 27), f(V, 26), f(0b00, 25, 24), \
sf(offset, 23, 5); \
@@ -1309,7 +1336,7 @@
#define INSN(NAME, opc, V) \
void NAME(address dest, prfop op = PLDL1KEEP) { \
- long offset = (dest - pc()) >> 2; \
+ int64_t offset = (dest - pc()) >> 2; \
starti; \
f(opc, 31, 30), f(0b011, 29, 27), f(V, 26), f(0b00, 25, 24), \
sf(offset, 23, 5); \
@@ -1385,7 +1412,7 @@
assert(size == 0b10 || size == 0b11, "bad operand size in ldr");
assert(op == 0b01, "literal form can only be used with loads");
f(size & 0b01, 31, 30), f(0b011, 29, 27), f(0b00, 25, 24);
- long offset = (adr.target() - pc()) >> 2;
+ int64_t offset = (adr.target() - pc()) >> 2;
sf(offset, 23, 5);
code_section()->relocate(pc(), adr.rspec());
return;
@@ -1461,6 +1488,7 @@
void NAME(Register Rd, Register Rn, Register Rm, \
enum shift_kind kind = LSL, unsigned shift = 0) { \
starti; \
+ guarantee(size == 1 || shift < 32, "incorrect shift"); \
f(N, 21); \
zrf(Rm, 16), zrf(Rn, 5), zrf(Rd, 0); \
op_shifted_reg(0b01010, kind, shift, size, op); \
@@ -1505,6 +1533,11 @@
#undef INSN
+#ifdef _WIN64
+// In MSVC, `mvn` is defined as a macro and it affects compilation
+#undef mvn
+#endif
+
// Aliases for short forms of orn
void mvn(Register Rd, Register Rm,
enum shift_kind kind = LSL, unsigned shift = 0) {
@@ -1523,6 +1556,7 @@
starti; \
f(0, 21); \
assert_cond(kind != ROR); \
+ guarantee(size == 1 || shift < 32, "incorrect shift");\
zrf(Rd, 0), zrf(Rn, 5), zrf(Rm, 16); \
op_shifted_reg(0b01011, kind, shift, size, op); \
}
@@ -1551,7 +1585,7 @@
void add_sub_extended_reg(unsigned op, unsigned decode,
Register Rd, Register Rn, Register Rm,
unsigned opt, ext::operation option, unsigned imm) {
- guarantee(imm <= 4, "shift amount must be < 4");
+ guarantee(imm <= 4, "shift amount must be <= 4");
f(op, 31, 29), f(decode, 28, 24), f(opt, 23, 22), f(1, 21);
f(option, 15, 13), f(imm, 12, 10);
}
@@ -1636,7 +1670,7 @@
f(o2, 10);
f(o3, 4);
f(nzcv, 3, 0);
- f(imm5, 20, 16), rf(Rn, 5);
+ f(imm5, 20, 16), zrf(Rn, 5);
}
#define INSN(NAME, op) \
@@ -1989,6 +2023,21 @@
#undef INSN
#undef INSN1
+// Floating-point compare. 3-registers versions (scalar).
+#define INSN(NAME, sz, e) \
+ void NAME(FloatRegister Vd, FloatRegister Vn, FloatRegister Vm) { \
+ starti; \
+ f(0b01111110, 31, 24), f(e, 23), f(sz, 22), f(1, 21), rf(Vm, 16); \
+ f(0b111011, 15, 10), rf(Vn, 5), rf(Vd, 0); \
+ } \
+
+ INSN(facged, 1, 0); // facge-double
+ INSN(facges, 0, 0); // facge-single
+ INSN(facgtd, 1, 1); // facgt-double
+ INSN(facgts, 0, 1); // facgt-single
+
+#undef INSN
+
// Floating-point Move (immediate)
private:
unsigned pack(double value);
@@ -2105,7 +2154,12 @@
}
void ld_st(FloatRegister Vt, SIMD_Arrangement T, Register Xn,
int imm, int op1, int op2, int regs) {
- guarantee(T <= T1Q && imm == SIMD_Size_in_bytes[T] * regs, "bad offset");
+
+ bool replicate = op2 >> 2 == 3;
+ // post-index value (imm) is formed differently for replicate/non-replicate ld* instructions
+ int expectedImmediate = replicate ? regs * (1 << (T >> 1)) : SIMD_Size_in_bytes[T] * regs;
+ guarantee(T < T1Q , "incorrect arrangement");
+ guarantee(imm == expectedImmediate, "bad offset");
starti;
f(0,31), f((int)T & 1, 30);
f(op1 | 0b100, 29, 21), f(0b11111, 20, 16), f(op2, 15, 12);
@@ -2212,39 +2266,62 @@
#undef INSN
-#define INSN(NAME, opc, opc2) \
+#define INSN(NAME, opc, opc2, acceptT2D) \
void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \
+ guarantee(T != T1Q && T != T1D, "incorrect arrangement"); \
+ if (!acceptT2D) guarantee(T != T2D, "incorrect arrangement"); \
starti; \
f(0, 31), f((int)T & 1, 30), f(opc, 29), f(0b01110, 28, 24); \
f((int)T >> 1, 23, 22), f(1, 21), rf(Vm, 16), f(opc2, 15, 10); \
rf(Vn, 5), rf(Vd, 0); \
}
- INSN(addv, 0, 0b100001);
- INSN(subv, 1, 0b100001);
- INSN(mulv, 0, 0b100111);
- INSN(mlav, 0, 0b100101);
- INSN(mlsv, 1, 0b100101);
- INSN(sshl, 0, 0b010001);
- INSN(ushl, 1, 0b010001);
+ INSN(addv, 0, 0b100001, true); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S, T2D
+ INSN(subv, 1, 0b100001, true); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S, T2D
+ INSN(mulv, 0, 0b100111, false); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S
+ INSN(mlav, 0, 0b100101, false); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S
+ INSN(mlsv, 1, 0b100101, false); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S
+ INSN(sshl, 0, 0b010001, true); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S, T2D
+ INSN(ushl, 1, 0b010001, true); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S, T2D
+ INSN(umullv, 1, 0b110000, false); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S
+ INSN(umlalv, 1, 0b100000, false); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S
#undef INSN
-#define INSN(NAME, opc, opc2) \
+#define INSN(NAME, opc, opc2, accepted) \
void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) { \
+ guarantee(T != T1Q && T != T1D, "incorrect arrangement"); \
+ if (accepted < 3) guarantee(T != T2D, "incorrect arrangement"); \
+ if (accepted < 2) guarantee(T != T2S, "incorrect arrangement"); \
+ if (accepted < 1) guarantee(T == T8B || T == T16B, "incorrect arrangement"); \
starti; \
f(0, 31), f((int)T & 1, 30), f(opc, 29), f(0b01110, 28, 24); \
f((int)T >> 1, 23, 22), f(opc2, 21, 10); \
rf(Vn, 5), rf(Vd, 0); \
}
- INSN(absr, 0, 0b100000101110);
- INSN(negr, 1, 0b100000101110);
- INSN(notr, 1, 0b100000010110);
- INSN(addv, 0, 0b110001101110);
- INSN(cls, 0, 0b100000010010);
- INSN(clz, 1, 0b100000010010);
- INSN(cnt, 0, 0b100000010110);
+ INSN(absr, 0, 0b100000101110, 3); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S, T2D
+ INSN(negr, 1, 0b100000101110, 3); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S, T2D
+ INSN(notr, 1, 0b100000010110, 0); // accepted arrangements: T8B, T16B
+ INSN(addv, 0, 0b110001101110, 1); // accepted arrangements: T8B, T16B, T4H, T8H, T4S
+ INSN(cls, 0, 0b100000010010, 2); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S
+ INSN(clz, 1, 0b100000010010, 2); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S
+ INSN(cnt, 0, 0b100000010110, 0); // accepted arrangements: T8B, T16B
+ INSN(uaddlp, 1, 0b100000001010, 2); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S
+ INSN(uaddlv, 1, 0b110000001110, 1); // accepted arrangements: T8B, T16B, T4H, T8H, T4S
+
+#undef INSN
+
+#define INSN(NAME, opc) \
+ void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) { \
+ starti; \
+ assert(T == T4S, "arrangement must be T4S"); \
+ f(0, 31), f((int)T & 1, 30), f(0b101110, 29, 24), f(opc, 23), \
+ f(T == T4S ? 0 : 1, 22), f(0b110000111110, 21, 10); rf(Vn, 5), rf(Vd, 0); \
+ }
+
+ INSN(fmaxv, 0);
+ INSN(fminv, 1);
#undef INSN
@@ -2255,7 +2332,7 @@
starti; \
assert(lsl == 0 || \
((T == T4H || T == T8H) && lsl == 8) || \
- ((T == T2S || T == T4S) && ((lsl >> 3) < 4)), "invalid shift"); \
+ ((T == T2S || T == T4S) && ((lsl >> 3) < 4) && ((lsl & 7) == 0)), "invalid shift");\
cmode |= lsl >> 2; \
if (T == T4H || T == T8H) cmode |= 0b1000; \
if (!(T == T4H || T == T8H || T == T2S || T == T4S)) { \
@@ -2289,6 +2366,8 @@
INSN(fsub, 0, 1, 0b110101);
INSN(fmla, 0, 0, 0b110011);
INSN(fmls, 0, 1, 0b110011);
+ INSN(fmax, 0, 0, 0b111101);
+ INSN(fmin, 0, 1, 0b111101);
#undef INSN
@@ -2414,7 +2493,22 @@
#undef INSN
- void ushll(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, SIMD_Arrangement Tb, int shift) {
+#define INSN(NAME, opc, opc2, isSHR) \
+ void NAME(FloatRegister Vd, FloatRegister Vn, int shift){ \
+ starti; \
+ int encodedShift = isSHR ? 128 - shift : 64 + shift; \
+ f(0b01, 31, 30), f(opc, 29), f(0b111110, 28, 23), \
+ f(encodedShift, 22, 16); f(opc2, 15, 10), rf(Vn, 5), rf(Vd, 0); \
+ }
+
+ INSN(shld, 0, 0b010101, /* isSHR = */ false);
+ INSN(sshrd, 0, 0b000001, /* isSHR = */ true);
+ INSN(ushrd, 1, 0b000001, /* isSHR = */ true);
+
+#undef INSN
+
+private:
+ void _ushll(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, SIMD_Arrangement Tb, int shift) {
starti;
/* The encodings for the immh:immb fields (bits 22:16) are
* 0001 xxx 8H, 8B/16b shift = xxx
@@ -2427,8 +2521,16 @@
f(0, 31), f(Tb & 1, 30), f(0b1011110, 29, 23), f((1 << ((Tb>>1)+3))|shift, 22, 16);
f(0b101001, 15, 10), rf(Vn, 5), rf(Vd, 0);
}
+
+public:
+ void ushll(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, SIMD_Arrangement Tb, int shift) {
+ assert(Tb == T8B || Tb == T4H || Tb == T2S, "invalid arrangement");
+ _ushll(Vd, Ta, Vn, Tb, shift);
+ }
+
void ushll2(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, SIMD_Arrangement Tb, int shift) {
- ushll(Vd, Ta, Vn, Tb, shift);
+ assert(Tb == T16B || Tb == T8H || Tb == T4S, "invalid arrangement");
+ _ushll(Vd, Ta, Vn, Tb, shift);
}
// Move from general purpose register
@@ -2436,19 +2538,21 @@
void mov(FloatRegister Vd, SIMD_Arrangement T, int index, Register Xn) {
starti;
f(0b01001110000, 31, 21), f(((1 << (T >> 1)) | (index << ((T >> 1) + 1))), 20, 16);
- f(0b000111, 15, 10), rf(Xn, 5), rf(Vd, 0);
+ f(0b000111, 15, 10), zrf(Xn, 5), rf(Vd, 0);
}
// Move to general purpose register
// mov Rd, Vn.T[index]
void mov(Register Xd, FloatRegister Vn, SIMD_Arrangement T, int index) {
+ guarantee(T >= T2S && T < T1Q, "only D and S arrangements are supported");
starti;
f(0, 31), f((T >= T1D) ? 1:0, 30), f(0b001110000, 29, 21);
f(((1 << (T >> 1)) | (index << ((T >> 1) + 1))), 20, 16);
f(0b001111, 15, 10), rf(Vn, 5), rf(Xd, 0);
}
- void pmull(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, FloatRegister Vm, SIMD_Arrangement Tb) {
+private:
+ void _pmull(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, FloatRegister Vm, SIMD_Arrangement Tb) {
starti;
assert((Ta == T1Q && (Tb == T1D || Tb == T2D)) ||
(Ta == T8H && (Tb == T8B || Tb == T16B)), "Invalid Size specifier");
@@ -2456,9 +2560,16 @@
f(0, 31), f(Tb & 1, 30), f(0b001110, 29, 24), f(size, 23, 22);
f(1, 21), rf(Vm, 16), f(0b111000, 15, 10), rf(Vn, 5), rf(Vd, 0);
}
+
+public:
+ void pmull(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, FloatRegister Vm, SIMD_Arrangement Tb) {
+ assert(Tb == T1D || Tb == T8B, "pmull assumes T1D or T8B as the second size specifier");
+ _pmull(Vd, Ta, Vn, Vm, Tb);
+ }
+
void pmull2(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, FloatRegister Vm, SIMD_Arrangement Tb) {
assert(Tb == T2D || Tb == T16B, "pmull2 assumes T2D or T16B as the second size specifier");
- pmull(Vd, Ta, Vn, Vm, Tb);
+ _pmull(Vd, Ta, Vn, Vm, Tb);
}
void uqxtn(FloatRegister Vd, SIMD_Arrangement Tb, FloatRegister Vn, SIMD_Arrangement Ta) {
@@ -2475,7 +2586,7 @@
starti;
assert(T != T1D, "reserved encoding");
f(0,31), f((int)T & 1, 30), f(0b001110000, 29, 21);
- f((1 << (T >> 1)), 20, 16), f(0b000011, 15, 10), rf(Xs, 5), rf(Vd, 0);
+ f((1 << (T >> 1)), 20, 16), f(0b000011, 15, 10), zrf(Xs, 5), rf(Vd, 0);
}
void dup(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, int index = 0)
@@ -2490,6 +2601,7 @@
// AdvSIMD ZIP/UZP/TRN
#define INSN(NAME, opcode) \
void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \
+ guarantee(T != T1D && T != T1Q, "invalid arrangement"); \
starti; \
f(0, 31), f(0b001110, 29, 24), f(0, 21), f(0, 15); \
f(opcode, 14, 12), f(0b10, 11, 10); \
@@ -2607,7 +2719,7 @@
virtual void bang_stack_with_offset(int offset);
static bool operand_valid_for_logical_immediate(bool is32, uint64_t imm);
- static bool operand_valid_for_add_sub_immediate(long imm);
+ static bool operand_valid_for_add_sub_immediate(int64_t imm);
static bool operand_valid_for_float_immediate(double imm);
void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0);
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/atomic_aarch64.hpp openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/atomic_aarch64.hpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/atomic_aarch64.hpp 1970-01-01 00:00:00.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/atomic_aarch64.hpp 2022-01-13 21:56:25.000000000 +0000
@@ -0,0 +1,49 @@
+/* Copyright (c) 2021, Red Hat Inc. All rights reserved.
+ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+ *
+ * This code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 only, as
+ * published by the Free Software Foundation.
+ *
+ * This code is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * version 2 for more details (a copy is included in the LICENSE file that
+ * accompanied this code).
+ *
+ * You should have received a copy of the GNU General Public License version
+ * 2 along with this work; if not, write to the Free Software Foundation,
+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
+ * or visit www.oracle.com if you need additional information or have any
+ * questions.
+ *
+ */
+
+#ifndef CPU_AARCH64_ATOMIC_AARCH64_HPP
+#define CPU_AARCH64_ATOMIC_AARCH64_HPP
+
+// Atomic stub implementation.
+// Default implementations are in atomic_linux_aarch64.S
+//
+// All stubs pass arguments the same way
+// x0: src/dest address
+// x1: arg1
+// x2: arg2 (optional)
+// x3, x8, x9: scratch
+typedef uint64_t (*aarch64_atomic_stub_t)(volatile void *ptr, uint64_t arg1, uint64_t arg2);
+
+// Pointers to stubs
+extern aarch64_atomic_stub_t aarch64_atomic_fetch_add_4_impl;
+extern aarch64_atomic_stub_t aarch64_atomic_fetch_add_8_impl;
+extern aarch64_atomic_stub_t aarch64_atomic_xchg_4_impl;
+extern aarch64_atomic_stub_t aarch64_atomic_xchg_8_impl;
+extern aarch64_atomic_stub_t aarch64_atomic_cmpxchg_1_impl;
+extern aarch64_atomic_stub_t aarch64_atomic_cmpxchg_4_impl;
+extern aarch64_atomic_stub_t aarch64_atomic_cmpxchg_8_impl;
+extern aarch64_atomic_stub_t aarch64_atomic_cmpxchg_1_relaxed_impl;
+extern aarch64_atomic_stub_t aarch64_atomic_cmpxchg_4_relaxed_impl;
+extern aarch64_atomic_stub_t aarch64_atomic_cmpxchg_8_relaxed_impl;
+
+#endif // CPU_AARCH64_ATOMIC_AARCH64_HPP
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/c1_Defs_aarch64.hpp openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/c1_Defs_aarch64.hpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/c1_Defs_aarch64.hpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/c1_Defs_aarch64.hpp 2022-01-13 21:56:25.000000000 +0000
@@ -44,13 +44,13 @@
pd_nof_cpu_regs_frame_map = RegisterImpl::number_of_registers, // number of registers used during code emission
pd_nof_fpu_regs_frame_map = FloatRegisterImpl::number_of_registers, // number of registers used during code emission
- pd_nof_caller_save_cpu_regs_frame_map = 19 - 2, // number of registers killed by calls
+ pd_nof_caller_save_cpu_regs_frame_map = 19 - 2 /* rscratch1 and rscratch2 */ R18_RESERVED_ONLY(- 1), // number of registers killed by calls
pd_nof_caller_save_fpu_regs_frame_map = 32, // number of registers killed by calls
- pd_first_callee_saved_reg = 19 - 2,
- pd_last_callee_saved_reg = 26 - 2,
+ pd_first_callee_saved_reg = 19 - 2 /* rscratch1 and rscratch2 */ R18_RESERVED_ONLY(- 1),
+ pd_last_callee_saved_reg = 26 - 2 /* rscratch1 and rscratch2 */ R18_RESERVED_ONLY(- 1),
- pd_last_allocatable_cpu_reg = 16,
+ pd_last_allocatable_cpu_reg = 16 R18_RESERVED_ONLY(- 1),
pd_nof_cpu_regs_reg_alloc
= pd_last_allocatable_cpu_reg + 1, // number of registers that are visible to register allocator
@@ -60,9 +60,9 @@
pd_nof_fpu_regs_linearscan = pd_nof_fpu_regs_frame_map, // number of registers visible to linear scan
pd_nof_xmm_regs_linearscan = 0, // like sparc we don't have any of these
pd_first_cpu_reg = 0,
- pd_last_cpu_reg = 16,
+ pd_last_cpu_reg = 16 R18_RESERVED_ONLY(- 1),
pd_first_byte_reg = 0,
- pd_last_byte_reg = 16,
+ pd_last_byte_reg = 16 R18_RESERVED_ONLY(- 1),
pd_first_fpu_reg = pd_nof_cpu_regs_frame_map,
pd_last_fpu_reg = pd_first_fpu_reg + 31,
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/c1_FpuStackSim_aarch64.cpp openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/c1_FpuStackSim_aarch64.cpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/c1_FpuStackSim_aarch64.cpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/c1_FpuStackSim_aarch64.cpp 2022-01-13 21:56:25.000000000 +0000
@@ -28,3 +28,6 @@
//--------------------------------------------------------
// No FPU stack on AARCH64
+
+// This include is needed to avoid MSVC error C1010 on Windows.
+#include "precompiled.hpp"
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/c1_FrameMap_aarch64.cpp openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/c1_FrameMap_aarch64.cpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/c1_FrameMap_aarch64.cpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/c1_FrameMap_aarch64.cpp 2022-01-13 21:56:25.000000000 +0000
@@ -181,7 +181,10 @@
map_register(i, r15); r15_opr = LIR_OprFact::single_cpu(i); i++;
map_register(i, r16); r16_opr = LIR_OprFact::single_cpu(i); i++;
map_register(i, r17); r17_opr = LIR_OprFact::single_cpu(i); i++;
- map_register(i, r18); r18_opr = LIR_OprFact::single_cpu(i); i++;
+#ifndef R18_RESERVED
+ // See comment in register_aarch64.hpp
+ map_register(i, r18_tls); r18_opr = LIR_OprFact::single_cpu(i); i++;
+#endif
map_register(i, r19); r19_opr = LIR_OprFact::single_cpu(i); i++;
map_register(i, r20); r20_opr = LIR_OprFact::single_cpu(i); i++;
map_register(i, r21); r21_opr = LIR_OprFact::single_cpu(i); i++;
@@ -199,6 +202,11 @@
map_register(i, r8); r8_opr = LIR_OprFact::single_cpu(i); i++; // rscratch1
map_register(i, r9); r9_opr = LIR_OprFact::single_cpu(i); i++; // rscratch2
+#ifdef R18_RESERVED
+ // See comment in register_aarch64.hpp
+ map_register(i, r18_tls); r18_opr = LIR_OprFact::single_cpu(i); i++;
+#endif
+
rscratch1_opr = r8_opr;
rscratch2_opr = r9_opr;
rscratch1_long_opr = LIR_OprFact::double_cpu(r8_opr->cpu_regnr(), r8_opr->cpu_regnr());
@@ -227,7 +235,10 @@
_caller_save_cpu_regs[13] = r15_opr;
_caller_save_cpu_regs[14] = r16_opr;
_caller_save_cpu_regs[15] = r17_opr;
+#ifndef R18_RESERVED
+ // See comment in register_aarch64.hpp
_caller_save_cpu_regs[16] = r18_opr;
+#endif
for (int i = 0; i < 8; i++) {
_caller_save_fpu_regs[i] = LIR_OprFact::single_fpu(i);
@@ -253,7 +264,7 @@
r15_oop_opr = as_oop_opr(r15);
r16_oop_opr = as_oop_opr(r16);
r17_oop_opr = as_oop_opr(r17);
- r18_oop_opr = as_oop_opr(r18);
+ r18_oop_opr = as_oop_opr(r18_tls);
r19_oop_opr = as_oop_opr(r19);
r20_oop_opr = as_oop_opr(r20);
r21_oop_opr = as_oop_opr(r21);
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/c1_LIRAssembler_aarch64.cpp openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/c1_LIRAssembler_aarch64.cpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/c1_LIRAssembler_aarch64.cpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/c1_LIRAssembler_aarch64.cpp 2022-01-13 21:56:25.000000000 +0000
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2000, 2020, Oracle and/or its affiliates. All rights reserved.
- * Copyright (c) 2014, Red Hat Inc. All rights reserved.
+ * Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@@ -1378,7 +1378,7 @@
__ load_klass(klass_RInfo, obj);
if (k->is_loaded()) {
// See if we get an immediate positive hit
- __ ldr(rscratch1, Address(klass_RInfo, long(k->super_check_offset())));
+ __ ldr(rscratch1, Address(klass_RInfo, int64_t(k->super_check_offset())));
__ cmp(k_RInfo, rscratch1);
if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) {
__ br(Assembler::NE, *failure_target);
@@ -2042,7 +2042,7 @@
} else if (code == lir_cmp_l2i) {
Label done;
__ cmp(left->as_register_lo(), right->as_register_lo());
- __ mov(dst->as_register(), (u_int64_t)-1L);
+ __ mov(dst->as_register(), (uint64_t)-1L);
__ br(Assembler::LT, done);
__ csinc(dst->as_register(), zr, zr, Assembler::EQ);
__ bind(done);
@@ -2314,7 +2314,6 @@
assert(default_type != NULL && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
int elem_size = type2aelembytes(basic_type);
- int shift_amount;
int scale = exact_log2(elem_size);
Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
@@ -2704,7 +2703,7 @@
Register res = op->result_opr()->as_register();
assert_different_registers(val, crc, res);
- unsigned long offset;
+ uint64_t offset;
__ adrp(res, ExternalAddress(StubRoutines::crc_table_addr()), offset);
if (offset) __ add(res, res, offset);
@@ -2851,7 +2850,7 @@
}
#endif
// first time here. Set profile type.
- __ ldr(tmp, mdo_addr);
+ __ str(tmp, mdo_addr);
} else {
assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/c1_LIRGenerator_aarch64.cpp openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/c1_LIRGenerator_aarch64.cpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/c1_LIRGenerator_aarch64.cpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/c1_LIRGenerator_aarch64.cpp 2022-01-13 21:56:25.000000000 +0000
@@ -173,10 +173,10 @@
if (large_disp != 0) {
LIR_Opr tmp = new_pointer_register();
if (Assembler::operand_valid_for_add_sub_immediate(large_disp)) {
- __ add(tmp, tmp, LIR_OprFact::intptrConst(large_disp));
+ __ add(index, LIR_OprFact::intptrConst(large_disp), tmp);
index = tmp;
} else {
- __ move(tmp, LIR_OprFact::intptrConst(large_disp));
+ __ move(LIR_OprFact::intptrConst(large_disp), tmp);
__ add(tmp, index, tmp);
index = tmp;
}
@@ -190,7 +190,7 @@
}
// at this point we either have base + index or base + displacement
- if (large_disp == 0) {
+ if (large_disp == 0 && index->is_register()) {
return new LIR_Address(base, index, type);
} else {
assert(Address::offset_ok_for_immed(large_disp, 0), "must be");
@@ -290,7 +290,7 @@
}
-bool LIRGenerator::strength_reduce_multiply(LIR_Opr left, int c, LIR_Opr result, LIR_Opr tmp) {
+bool LIRGenerator::strength_reduce_multiply(LIR_Opr left, jint c, LIR_Opr result, LIR_Opr tmp) {
if (is_power_of_2(c - 1)) {
__ shift_left(left, exact_log2(c - 1), tmp);
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/c1_Runtime1_aarch64.cpp openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/c1_Runtime1_aarch64.cpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/c1_Runtime1_aarch64.cpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/c1_Runtime1_aarch64.cpp 2022-01-13 21:56:25.000000000 +0000
@@ -143,7 +143,7 @@
if (arg1 == c_rarg2 || arg1 == c_rarg3 ||
arg2 == c_rarg1 || arg2 == c_rarg3 ||
arg3 == c_rarg1 || arg3 == c_rarg2) {
- stp(arg3, arg2, Address(pre(sp, 2 * wordSize)));
+ stp(arg3, arg2, Address(pre(sp, -2 * wordSize)));
stp(arg1, zr, Address(pre(sp, -2 * wordSize)));
ldp(c_rarg1, zr, Address(post(sp, 2 * wordSize)));
ldp(c_rarg3, c_rarg2, Address(post(sp, 2 * wordSize)));
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/c2_globals_aarch64.hpp openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/c2_globals_aarch64.hpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/c2_globals_aarch64.hpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/c2_globals_aarch64.hpp 2022-01-13 21:56:25.000000000 +0000
@@ -46,7 +46,7 @@
define_pd_global(intx, OnStackReplacePercentage, 140);
define_pd_global(intx, ConditionalMoveLimit, 3);
-define_pd_global(intx, FLOATPRESSURE, 64);
+define_pd_global(intx, FLOATPRESSURE, 32);
define_pd_global(intx, FreqInlineSize, 325);
define_pd_global(intx, MinJumpTableSize, 10);
define_pd_global(intx, INTPRESSURE, 24);
@@ -76,7 +76,7 @@
define_pd_global(intx, NonProfiledCodeHeapSize, 21*M);
define_pd_global(intx, ProfiledCodeHeapSize, 22*M);
define_pd_global(intx, NonNMethodCodeHeapSize, 5*M );
-define_pd_global(uintx, CodeCacheMinBlockLength, 4);
+define_pd_global(uintx, CodeCacheMinBlockLength, 6);
define_pd_global(uintx, CodeCacheMinimumUseSpace, 400*K);
// Heap related flags
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/compiledIC_aarch64.cpp openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/compiledIC_aarch64.cpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/compiledIC_aarch64.cpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/compiledIC_aarch64.cpp 2022-01-13 21:56:25.000000000 +0000
@@ -36,6 +36,9 @@
#define __ _masm.
address CompiledStaticCall::emit_to_interp_stub(CodeBuffer &cbuf, address mark) {
+ precond(cbuf.stubs()->start() != badAddress);
+ precond(cbuf.stubs()->end() != badAddress);
+
// Stub is fixed up when the corresponding call is converted from
// calling compiled code to calling interpreted code.
// mov rmethod, 0
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/frame_aarch64.cpp openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/frame_aarch64.cpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/frame_aarch64.cpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/frame_aarch64.cpp 2022-01-13 21:56:25.000000000 +0000
@@ -1,6 +1,6 @@
/*
- * Copyright (c) 1997, 2019, Oracle and/or its affiliates. All rights reserved.
- * Copyright (c) 2014, Red Hat Inc. All rights reserved.
+ * Copyright (c) 1997, 2021, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2014, 2021, Red Hat Inc. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@@ -284,6 +284,9 @@
tty->print_cr("patch_pc at address " INTPTR_FORMAT " [" INTPTR_FORMAT " -> " INTPTR_FORMAT "]",
p2i(pc_addr), p2i(*pc_addr), p2i(pc));
}
+
+ // Only generated code frames should be patched, therefore the return address will not be signed.
+ assert(pauth_ptr_is_raw(*pc_addr), "cannot be signed");
// Either the return address is the original one or we are going to
// patch in the same address that's already there.
assert(_pc == *pc_addr || pc == *pc_addr, "must be");
@@ -448,7 +451,9 @@
}
#endif // COMPILER2_OR_JVMCI
- return frame(sender_sp, unextended_sp, link(), sender_pc());
+ // Use the raw version of pc - the interpreter should not have signed it.
+
+ return frame(sender_sp, unextended_sp, link(), sender_pc_maybe_signed());
}
@@ -511,6 +516,7 @@
// Must be native-compiled frame, i.e. the marshaling code for native
// methods that exists in the core system.
+
return frame(sender_sp(), link(), sender_pc());
}
@@ -539,7 +545,7 @@
Method* m = *interpreter_frame_method_addr();
// validate the method we'd find in this potential sender
- if (!m->is_valid_method()) return false;
+ if (!Method::is_valid_method(m)) return false;
// stack frames shouldn't be much larger than max_stack elements
// this test requires the use of unextended_sp which is the sp as seen by
@@ -672,15 +678,15 @@
#define DESCRIBE_FP_OFFSET(name) \
{ \
- unsigned long *p = (unsigned long *)fp; \
- printf("0x%016lx 0x%016lx %s\n", (unsigned long)(p + frame::name##_offset), \
+ uintptr_t *p = (uintptr_t *)fp; \
+ printf("0x%016lx 0x%016lx %s\n", (uintptr_t)(p + frame::name##_offset), \
p[frame::name##_offset], #name); \
}
-static __thread unsigned long nextfp;
-static __thread unsigned long nextpc;
-static __thread unsigned long nextsp;
-static __thread RegisterMap *reg_map;
+static THREAD_LOCAL_DECL uintptr_t nextfp;
+static THREAD_LOCAL_DECL uintptr_t nextpc;
+static THREAD_LOCAL_DECL uintptr_t nextsp;
+static THREAD_LOCAL_DECL RegisterMap *reg_map;
static void printbc(Method *m, intptr_t bcx) {
const char *name;
@@ -698,7 +704,7 @@
printf("%s : %s ==> %s\n", m->name_and_sig_as_C_string(), buf, name);
}
-void internal_pf(unsigned long sp, unsigned long fp, unsigned long pc, unsigned long bcx) {
+void internal_pf(uintptr_t sp, uintptr_t fp, uintptr_t pc, uintptr_t bcx) {
if (! fp)
return;
@@ -712,7 +718,7 @@
DESCRIBE_FP_OFFSET(interpreter_frame_locals);
DESCRIBE_FP_OFFSET(interpreter_frame_bcp);
DESCRIBE_FP_OFFSET(interpreter_frame_initial_sp);
- unsigned long *p = (unsigned long *)fp;
+ uintptr_t *p = (uintptr_t *)fp;
// We want to see all frames, native and Java. For compiled and
// interpreted frames we have special information that allows us to
@@ -722,16 +728,16 @@
if (this_frame.is_compiled_frame() ||
this_frame.is_interpreted_frame()) {
frame sender = this_frame.sender(reg_map);
- nextfp = (unsigned long)sender.fp();
- nextpc = (unsigned long)sender.pc();
- nextsp = (unsigned long)sender.unextended_sp();
+ nextfp = (uintptr_t)sender.fp();
+ nextpc = (uintptr_t)sender.pc();
+ nextsp = (uintptr_t)sender.unextended_sp();
} else {
nextfp = p[frame::link_offset];
nextpc = p[frame::return_addr_offset];
- nextsp = (unsigned long)&p[frame::sender_sp_offset];
+ nextsp = (uintptr_t)&p[frame::sender_sp_offset];
}
- if (bcx == -1ul)
+ if (bcx == -1ULL)
bcx = p[frame::interpreter_frame_bcp_offset];
if (Interpreter::contains((address)pc)) {
@@ -765,8 +771,8 @@
internal_pf (nextsp, nextfp, nextpc, -1);
}
-extern "C" void pf(unsigned long sp, unsigned long fp, unsigned long pc,
- unsigned long bcx, unsigned long thread) {
+extern "C" void pf(uintptr_t sp, uintptr_t fp, uintptr_t pc,
+ uintptr_t bcx, uintptr_t thread) {
if (!reg_map) {
reg_map = NEW_C_HEAP_OBJ(RegisterMap, mtNone);
::new (reg_map) RegisterMap((JavaThread*)thread, false);
@@ -785,9 +791,9 @@
// support for printing out where we are in a Java method
// needs to be passed current fp and bcp register values
// prints method name, bc index and bytecode name
-extern "C" void pm(unsigned long fp, unsigned long bcx) {
+extern "C" void pm(uintptr_t fp, uintptr_t bcx) {
DESCRIBE_FP_OFFSET(interpreter_frame_method);
- unsigned long *p = (unsigned long *)fp;
+ uintptr_t *p = (uintptr_t *)fp;
Method* m = (Method*)p[frame::interpreter_frame_method_offset];
printbc(m, bcx);
}
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/frame_aarch64.hpp openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/frame_aarch64.hpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/frame_aarch64.hpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/frame_aarch64.hpp 2022-01-13 21:56:25.000000000 +0000
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 1997, 2021, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2014, Red Hat Inc. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
@@ -61,6 +61,7 @@
// [last sp ]
// [oop temp ] (only for native calls)
+// [padding ] (to preserve machine SP alignment)
// [locals and parameters ]
// <- sender sp
// ------------------------------ Asm interpreter ----------------------------------------
@@ -148,6 +149,7 @@
intptr_t* fp() const { return _fp; }
inline address* sender_pc_addr() const;
+ inline address sender_pc_maybe_signed() const;
// expression stack tos if we are nested in a java call
intptr_t* interpreter_frame_last_sp() const;
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/frame_aarch64.inline.hpp openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/frame_aarch64.inline.hpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/frame_aarch64.inline.hpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/frame_aarch64.inline.hpp 2022-01-13 21:56:25.000000000 +0000
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 1997, 2021, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2014, Red Hat Inc. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
@@ -28,6 +28,7 @@
#include "code/codeCache.hpp"
#include "code/vmreg.inline.hpp"
+#include "pauth_aarch64.hpp"
// Inline functions for AArch64 frames:
@@ -45,6 +46,7 @@
static int spin;
inline void frame::init(intptr_t* sp, intptr_t* fp, address pc) {
+ assert(pauth_ptr_is_raw(pc), "cannot be signed");
intptr_t a = intptr_t(sp);
intptr_t b = intptr_t(fp);
_sp = sp;
@@ -69,6 +71,7 @@
}
inline frame::frame(intptr_t* sp, intptr_t* unextended_sp, intptr_t* fp, address pc) {
+ assert(pauth_ptr_is_raw(pc), "cannot be signed");
intptr_t a = intptr_t(sp);
intptr_t b = intptr_t(fp);
_sp = sp;
@@ -155,8 +158,9 @@
// Return address:
-inline address* frame::sender_pc_addr() const { return (address*) addr_at( return_addr_offset); }
-inline address frame::sender_pc() const { return *sender_pc_addr(); }
+inline address* frame::sender_pc_addr() const { return (address*) addr_at( return_addr_offset); }
+inline address frame::sender_pc_maybe_signed() const { return *sender_pc_addr(); }
+inline address frame::sender_pc() const { return pauth_strip_pointer(sender_pc_maybe_signed()); }
inline intptr_t* frame::sender_sp() const { return addr_at( sender_sp_offset); }
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/gc/shared/barrierSetAssembler_aarch64.cpp openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/gc/shared/barrierSetAssembler_aarch64.cpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/gc/shared/barrierSetAssembler_aarch64.cpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/gc/shared/barrierSetAssembler_aarch64.cpp 2022-01-13 21:56:25.000000000 +0000
@@ -172,7 +172,7 @@
Label retry;
__ bind(retry);
{
- unsigned long offset;
+ uint64_t offset;
__ adrp(rscratch1, ExternalAddress((address) Universe::heap()->end_addr()), offset);
__ ldr(heap_end, Address(rscratch1, offset));
}
@@ -181,7 +181,7 @@
// Get the current top of the heap
{
- unsigned long offset;
+ uint64_t offset;
__ adrp(rscratch1, heap_top, offset);
// Use add() here after ARDP, rather than lea().
// lea() does not generate anything if its offset is zero.
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/gc/shenandoah/c1/shenandoahBarrierSetC1_aarch64.cpp openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/gc/shenandoah/c1/shenandoahBarrierSetC1_aarch64.cpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/gc/shenandoah/c1/shenandoahBarrierSetC1_aarch64.cpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/gc/shenandoah/c1/shenandoahBarrierSetC1_aarch64.cpp 2022-01-13 21:56:25.000000000 +0000
@@ -1,5 +1,6 @@
/*
- * Copyright (c) 2018, Red Hat, Inc. All rights reserved.
+ * Copyright (c) 2018, 2020, Red Hat, Inc. All rights reserved.
+ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 only, as
@@ -47,7 +48,16 @@
newval = tmp2;
}
- ShenandoahBarrierSet::assembler()->cmpxchg_oop(masm->masm(), addr, cmpval, newval, /*acquire*/ false, /*release*/ true, /*weak*/ false, /*is_cae*/ false, result);
+ ShenandoahBarrierSet::assembler()->cmpxchg_oop(masm->masm(), addr, cmpval, newval, /*acquire*/ true, /*release*/ true, /*is_cae*/ false, result);
+
+ if (UseBarriersForVolatile) {
+ // The membar here is necessary to prevent reordering between the
+ // release store in the CAS above and a subsequent volatile load.
+ // However for !UseBarriersForVolatile, C1 inserts a full barrier before
+ // volatile loads which means we don't need an additional barrier
+ // here (see LIRGenerator::volatile_field_load()).
+ __ membar(__ AnyAny);
+ }
}
#undef __
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/gc/shenandoah/shenandoah_aarch64.ad openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/gc/shenandoah/shenandoah_aarch64.ad
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/gc/shenandoah/shenandoah_aarch64.ad 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/gc/shenandoah/shenandoah_aarch64.ad 2022-01-13 21:56:25.000000000 +0000
@@ -33,7 +33,7 @@
Register tmp = $tmp$$Register;
__ mov(tmp, $oldval$$Register); // Must not clobber oldval.
ShenandoahBarrierSet::assembler()->cmpxchg_oop(&_masm, $mem$$Register, tmp, $newval$$Register,
- /*acquire*/ false, /*release*/ true, /*weak*/ false, /*is_cae*/ false, $res$$Register);
+ /*acquire*/ false, /*release*/ true, /*is_cae*/ false, $res$$Register);
%}
enc_class aarch64_enc_cmpxchg_acq_oop_shenandoah(memory mem, iRegP oldval, iRegP newval, iRegPNoSp tmp, iRegINoSp res) %{
@@ -42,7 +42,7 @@
Register tmp = $tmp$$Register;
__ mov(tmp, $oldval$$Register); // Must not clobber oldval.
ShenandoahBarrierSet::assembler()->cmpxchg_oop(&_masm, $mem$$Register, tmp, $newval$$Register,
- /*acquire*/ true, /*release*/ true, /*weak*/ false, /*is_cae*/ false, $res$$Register);
+ /*acquire*/ true, /*release*/ true, /*is_cae*/ false, $res$$Register);
%}
%}
@@ -76,7 +76,7 @@
ins_encode %{
Register tmp = $tmp$$Register;
__ mov(tmp, $oldval$$Register); // Must not clobber oldval.
- ShenandoahBarrierSet::assembler()->cmpxchg_oop(&_masm, $mem$$Register, tmp, $newval$$Register, /*acquire*/ false, /*release*/ true, /*weak*/ false, /*is_cae*/ false, $res$$Register);
+ ShenandoahBarrierSet::assembler()->cmpxchg_oop(&_masm, $mem$$Register, tmp, $newval$$Register, /*acquire*/ false, /*release*/ true, /*is_cae*/ false, $res$$Register);
%}
ins_pipe(pipe_slow);
@@ -114,7 +114,7 @@
ins_encode %{
Register tmp = $tmp$$Register;
__ mov(tmp, $oldval$$Register); // Must not clobber oldval.
- ShenandoahBarrierSet::assembler()->cmpxchg_oop(&_masm, $mem$$Register, tmp, $newval$$Register, /*acquire*/ true, /*release*/ true, /*weak*/ false, /*is_cae*/ false, $res$$Register);
+ ShenandoahBarrierSet::assembler()->cmpxchg_oop(&_masm, $mem$$Register, tmp, $newval$$Register, /*acquire*/ true, /*release*/ true, /*is_cae*/ false, $res$$Register);
%}
ins_pipe(pipe_slow);
@@ -131,7 +131,7 @@
Register tmp = $tmp$$Register;
__ mov(tmp, $oldval$$Register); // Must not clobber oldval.
ShenandoahBarrierSet::assembler()->cmpxchg_oop(&_masm, $mem$$Register, tmp, $newval$$Register,
- /*acquire*/ false, /*release*/ true, /*weak*/ false, /*is_cae*/ true, $res$$Register);
+ /*acquire*/ false, /*release*/ true, /*is_cae*/ true, $res$$Register);
%}
ins_pipe(pipe_slow);
%}
@@ -147,7 +147,7 @@
Register tmp = $tmp$$Register;
__ mov(tmp, $oldval$$Register); // Must not clobber oldval.
ShenandoahBarrierSet::assembler()->cmpxchg_oop(&_masm, $mem$$Register, tmp, $newval$$Register,
- /*acquire*/ false, /*release*/ true, /*weak*/ false, /*is_cae*/ true, $res$$Register);
+ /*acquire*/ false, /*release*/ true, /*is_cae*/ true, $res$$Register);
%}
ins_pipe(pipe_slow);
%}
@@ -162,8 +162,9 @@
ins_encode %{
Register tmp = $tmp$$Register;
__ mov(tmp, $oldval$$Register); // Must not clobber oldval.
+ // Weak is not currently supported by ShenandoahBarrierSet::cmpxchg_oop
ShenandoahBarrierSet::assembler()->cmpxchg_oop(&_masm, $mem$$Register, tmp, $newval$$Register,
- /*acquire*/ false, /*release*/ true, /*weak*/ true, /*is_cae*/ false, $res$$Register);
+ /*acquire*/ false, /*release*/ true, /*is_cae*/ false, $res$$Register);
%}
ins_pipe(pipe_slow);
%}
@@ -178,8 +179,9 @@
ins_encode %{
Register tmp = $tmp$$Register;
__ mov(tmp, $oldval$$Register); // Must not clobber oldval.
+ // Weak is not currently supported by ShenandoahBarrierSet::cmpxchg_oop
ShenandoahBarrierSet::assembler()->cmpxchg_oop(&_masm, $mem$$Register, tmp, $newval$$Register,
- /*acquire*/ false, /*release*/ true, /*weak*/ true, /*is_cae*/ false, $res$$Register);
+ /*acquire*/ false, /*release*/ true, /*is_cae*/ false, $res$$Register);
%}
ins_pipe(pipe_slow);
%}
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/gc/shenandoah/shenandoahBarrierSetAssembler_aarch64.cpp openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/gc/shenandoah/shenandoahBarrierSetAssembler_aarch64.cpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/gc/shenandoah/shenandoahBarrierSetAssembler_aarch64.cpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/gc/shenandoah/shenandoahBarrierSetAssembler_aarch64.cpp 2022-01-13 21:56:25.000000000 +0000
@@ -263,16 +263,9 @@
void ShenandoahBarrierSetAssembler::iu_barrier(MacroAssembler* masm, Register dst, Register tmp) {
if (ShenandoahIUBarrier) {
- // Save possibly live regs.
- RegSet live_regs = RegSet::range(r0, r4) - dst;
- __ push(live_regs, sp);
- __ strd(v0, __ pre(sp, 2 * -wordSize));
-
+ __ push_call_clobbered_registers();
satb_write_barrier_pre(masm, noreg, dst, rthread, tmp, true, false);
-
- // Restore possibly live regs.
- __ ldrd(v0, __ post(sp, 2 * wordSize));
- __ pop(live_regs, sp);
+ __ pop_call_clobbered_registers();
}
}
@@ -406,9 +399,35 @@
__ bind(done);
}
-
-void ShenandoahBarrierSetAssembler::cmpxchg_oop(MacroAssembler* masm, Register addr, Register expected, Register new_val,
- bool acquire, bool release, bool weak, bool is_cae,
+// Special Shenandoah CAS implementation that handles false negatives due
+// to concurrent evacuation. The service is more complex than a
+// traditional CAS operation because the CAS operation is intended to
+// succeed if the reference at addr exactly matches expected or if the
+// reference at addr holds a pointer to a from-space object that has
+// been relocated to the location named by expected. There are two
+// races that must be addressed:
+// a) A parallel thread may mutate the contents of addr so that it points
+// to a different object. In this case, the CAS operation should fail.
+// b) A parallel thread may heal the contents of addr, replacing a
+// from-space pointer held in addr with the to-space pointer
+// representing the new location of the object.
+// Upon entry to cmpxchg_oop, it is assured that new_val equals NULL
+// or it refers to an object that is not being evacuated out of
+// from-space, or it refers to the to-space version of an object that
+// is being evacuated out of from-space.
+//
+// By default the value held in the result register following execution
+// of the generated code sequence is 0 to indicate failure of CAS,
+// non-zero to indicate success. If is_cae, the result is the value most
+// recently fetched from addr rather than a boolean success indicator.
+//
+// Clobbers rscratch1, rscratch2
+void ShenandoahBarrierSetAssembler::cmpxchg_oop(MacroAssembler* masm,
+ Register addr,
+ Register expected,
+ Register new_val,
+ bool acquire, bool release,
+ bool is_cae,
Register result) {
Register tmp1 = rscratch1;
Register tmp2 = rscratch2;
@@ -418,48 +437,123 @@
assert_different_registers(addr, expected, tmp1, tmp2);
assert_different_registers(addr, new_val, tmp1, tmp2);
- Label retry, done, fail;
+ Label step4, done;
- // CAS, using LL/SC pair.
- __ bind(retry);
- __ load_exclusive(tmp1, addr, size, acquire);
- if (is_narrow) {
- __ cmpw(tmp1, expected);
- } else {
- __ cmp(tmp1, expected);
- }
- __ br(Assembler::NE, fail);
- __ store_exclusive(tmp2, new_val, addr, size, release);
- if (weak) {
- __ cmpw(tmp2, 0u); // If the store fails, return NE to our caller
- } else {
- __ cbnzw(tmp2, retry);
- }
- __ b(done);
+ // There are two ways to reach this label. Initial entry into the
+ // cmpxchg_oop code expansion starts at step1 (which is equivalent
+ // to label step4). Additionally, in the rare case that four steps
+ // are required to perform the requested operation, the fourth step
+ // is the same as the first. On a second pass through step 1,
+ // control may flow through step 2 on its way to failure. It will
+ // not flow from step 2 to step 3 since we are assured that the
+ // memory at addr no longer holds a from-space pointer.
+ //
+ // The comments that immediately follow the step4 label apply only
+ // to the case in which control reaches this label by branch from
+ // step 3.
+
+ __ bind (step4);
+
+ // Step 4. CAS has failed because the value most recently fetched
+ // from addr is no longer the from-space pointer held in tmp2. If a
+ // different thread replaced the in-memory value with its equivalent
+ // to-space pointer, then CAS may still be able to succeed. The
+ // value held in the expected register has not changed.
+ //
+ // It is extremely rare we reach this point. For this reason, the
+ // implementation opts for smaller rather than potentially faster
+ // code. Ultimately, smaller code for this rare case most likely
+ // delivers higher overall throughput by enabling improved icache
+ // performance.
+
+ // Step 1. Fast-path.
+ //
+ // Try to CAS with given arguments. If successful, then we are done.
+ //
+ // No label required for step 1.
+
+ __ cmpxchg(addr, expected, new_val, size, acquire, release, false, tmp2);
+ // EQ flag set iff success. tmp2 holds value fetched.
+
+ // If expected equals null but tmp2 does not equal null, the
+ // following branches to done to report failure of CAS. If both
+ // expected and tmp2 equal null, the following branches to done to
+ // report success of CAS. There's no need for a special test of
+ // expected equal to null.
+
+ __ br(Assembler::EQ, done);
+ // if CAS failed, fall through to step 2
+
+ // Step 2. CAS has failed because the value held at addr does not
+ // match expected. This may be a false negative because the value fetched
+ // from addr (now held in tmp2) may be a from-space pointer to the
+ // original copy of same object referenced by to-space pointer expected.
+ //
+ // To resolve this, it suffices to find the forward pointer associated
+ // with fetched value. If this matches expected, retry CAS with new
+ // parameters. If this mismatches, then we have a legitimate
+ // failure, and we're done.
+ //
+ // No need for step2 label.
+
+ // overwrite tmp1 with from-space pointer fetched from memory
+ __ mov(tmp1, tmp2);
- __ bind(fail);
- // Check if rb(expected)==rb(tmp1)
- // Shuffle registers so that we have memory value ready for next expected.
- __ mov(tmp2, expected);
- __ mov(expected, tmp1);
if (is_narrow) {
+ // Decode tmp1 in order to resolve its forward pointer
__ decode_heap_oop(tmp1, tmp1);
- __ decode_heap_oop(tmp2, tmp2);
}
resolve_forward_pointer(masm, tmp1);
- resolve_forward_pointer(masm, tmp2);
- __ cmp(tmp1, tmp2);
- // Retry with expected now being the value we just loaded from addr.
- __ br(Assembler::EQ, retry);
- if (is_cae && is_narrow) {
- // For cmp-and-exchange and narrow oops, we need to restore
- // the compressed old-value. We moved it to 'expected' a few lines up.
- __ mov(tmp1, expected);
+ // Encode tmp1 to compare against expected.
+ __ encode_heap_oop(tmp1, tmp1);
+
+ // Does forwarded value of fetched from-space pointer match original
+ // value of expected? If tmp1 holds null, this comparison will fail
+ // because we know from step1 that expected is not null. There is
+ // no need for a separate test for tmp1 (the value originally held
+ // in memory) equal to null.
+ __ cmp(tmp1, expected);
+
+ // If not, then the failure was legitimate and we're done.
+ // Branching to done with NE condition denotes failure.
+ __ br(Assembler::NE, done);
+
+ // Fall through to step 3. No need for step3 label.
+
+ // Step 3. We've confirmed that the value originally held in memory
+ // (now held in tmp2) pointed to from-space version of original
+ // expected value. Try the CAS again with the from-space expected
+ // value. If it now succeeds, we're good.
+ //
+ // Note: tmp2 holds encoded from-space pointer that matches to-space
+ // object residing at expected. tmp2 is the new "expected".
+
+ // Note that macro implementation of __cmpxchg cannot use same register
+ // tmp2 for result and expected since it overwrites result before it
+ // compares result with expected.
+ __ cmpxchg(addr, tmp2, new_val, size, acquire, release, false, noreg);
+ // EQ flag set iff success. tmp2 holds value fetched, tmp1 (rscratch1) clobbered.
+
+ // If fetched value did not equal the new expected, this could
+ // still be a false negative because some other thread may have
+ // newly overwritten the memory value with its to-space equivalent.
+ __ br(Assembler::NE, step4);
+
+ if (is_cae) {
+ // We're falling through to done to indicate success. Success
+ // with is_cae is denoted by returning the value of expected as
+ // result.
+ __ mov(tmp2, expected);
}
+
__ bind(done);
+ // At entry to done, the Z (EQ) flag is on iff if the CAS
+ // operation was successful. Additionally, if is_cae, tmp2 holds
+ // the value most recently fetched from addr. In this case, success
+ // is denoted by tmp2 matching expected.
if (is_cae) {
- __ mov(result, tmp1);
+ __ mov(result, tmp2);
} else {
__ cset(result, Assembler::EQ);
}
@@ -562,9 +656,7 @@
// Is marking still active?
Address gc_state(thread, in_bytes(ShenandoahThreadLocalData::gc_state_offset()));
__ ldrb(tmp, gc_state);
- __ mov(rscratch2, ShenandoahHeap::MARKING);
- __ tst(tmp, rscratch2);
- __ br(Assembler::EQ, done);
+ __ tbz(tmp, ShenandoahHeap::MARKING_BITPOS, done);
// Can we store original value in the thread's buffer?
__ ldr(tmp, queue_index);
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/gc/shenandoah/shenandoahBarrierSetAssembler_aarch64.hpp openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/gc/shenandoah/shenandoahBarrierSetAssembler_aarch64.hpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/gc/shenandoah/shenandoahBarrierSetAssembler_aarch64.hpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/gc/shenandoah/shenandoahBarrierSetAssembler_aarch64.hpp 2022-01-13 21:56:25.000000000 +0000
@@ -82,7 +82,7 @@
virtual void try_resolve_jobject_in_native(MacroAssembler* masm, Register jni_env,
Register obj, Register tmp, Label& slowpath);
virtual void cmpxchg_oop(MacroAssembler* masm, Register addr, Register expected, Register new_val,
- bool acquire, bool release, bool weak, bool is_cae, Register result);
+ bool acquire, bool release, bool is_cae, Register result);
virtual void barrier_stubs_init();
};
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/globalDefinitions_aarch64.hpp openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/globalDefinitions_aarch64.hpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/globalDefinitions_aarch64.hpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/globalDefinitions_aarch64.hpp 2022-01-13 21:56:25.000000000 +0000
@@ -53,4 +53,13 @@
#define THREAD_LOCAL_POLL
+#if defined(_WIN64)
+#define R18_RESERVED
+#define R18_RESERVED_ONLY(code) code
+#define NOT_R18_RESERVED(code)
+#else
+#define R18_RESERVED_ONLY(code)
+#define NOT_R18_RESERVED(code) code
+#endif
+
#endif // CPU_AARCH64_VM_GLOBALDEFINITIONS_AARCH64_HPP
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/icache_aarch64.hpp openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/icache_aarch64.hpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/icache_aarch64.hpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/icache_aarch64.hpp 2022-01-13 21:56:25.000000000 +0000
@@ -26,19 +26,6 @@
#ifndef CPU_AARCH64_VM_ICACHE_AARCH64_HPP
#define CPU_AARCH64_VM_ICACHE_AARCH64_HPP
-// Interface for updating the instruction cache. Whenever the VM
-// modifies code, part of the processor instruction cache potentially
-// has to be flushed.
-
-class ICache : public AbstractICache {
- public:
- static void initialize();
- static void invalidate_word(address addr) {
- __clear_cache((char *)addr, (char *)(addr + 3));
- }
- static void invalidate_range(address start, int nbytes) {
- __clear_cache((char *)start, (char *)(start + nbytes));
- }
-};
+#include OS_CPU_HEADER(icache)
#endif // CPU_AARCH64_VM_ICACHE_AARCH64_HPP
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/immediate_aarch64.cpp openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/immediate_aarch64.cpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/immediate_aarch64.cpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/immediate_aarch64.cpp 2022-01-13 21:56:25.000000000 +0000
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014, Red Hat Inc. All rights reserved.
+ * Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@@ -23,6 +23,10 @@
*/
#include
+#include
+
+#include "precompiled.hpp"
+#include "utilities/globalDefinitions.hpp"
#include "immediate_aarch64.hpp"
// there are at most 2^13 possible logical immediate encodings
@@ -34,14 +38,14 @@
// for forward lookup we just use a direct array lookup
// and assume that the cient has supplied a valid encoding
// table[encoding] = immediate
-static u_int64_t LITable[LI_TABLE_SIZE];
+static uint64_t LITable[LI_TABLE_SIZE];
// for reverse lookup we need a sparse map so we store a table of
// immediate and encoding pairs sorted by immediate value
struct li_pair {
- u_int64_t immediate;
- u_int32_t encoding;
+ uint64_t immediate;
+ uint32_t encoding;
};
static struct li_pair InverseLITable[LI_TABLE_SIZE];
@@ -63,9 +67,9 @@
// helper functions used by expandLogicalImmediate
// for i = 1, ... N result = 1 other bits are zero
-static inline u_int64_t ones(int N)
+static inline uint64_t ones(int N)
{
- return (N == 64 ? (u_int64_t)-1UL : ((1UL << N) - 1));
+ return (N == 64 ? -1ULL : (1ULL << N) - 1);
}
/*
@@ -73,49 +77,49 @@
*/
// 32 bit mask with bits [hi,...,lo] set
-static inline u_int32_t mask32(int hi = 31, int lo = 0)
+static inline uint32_t mask32(int hi = 31, int lo = 0)
{
int nbits = (hi + 1) - lo;
return ((1 << nbits) - 1) << lo;
}
-static inline u_int64_t mask64(int hi = 63, int lo = 0)
+static inline uint64_t mask64(int hi = 63, int lo = 0)
{
int nbits = (hi + 1) - lo;
return ((1L << nbits) - 1) << lo;
}
// pick bits [hi,...,lo] from val
-static inline u_int32_t pick32(u_int32_t val, int hi = 31, int lo = 0)
+static inline uint32_t pick32(uint32_t val, int hi = 31, int lo = 0)
{
return (val & mask32(hi, lo));
}
// pick bits [hi,...,lo] from val
-static inline u_int64_t pick64(u_int64_t val, int hi = 31, int lo = 0)
+static inline uint64_t pick64(uint64_t val, int hi = 31, int lo = 0)
{
return (val & mask64(hi, lo));
}
// mask [hi,lo] and shift down to start at bit 0
-static inline u_int32_t pickbits32(u_int32_t val, int hi = 31, int lo = 0)
+static inline uint32_t pickbits32(uint32_t val, int hi = 31, int lo = 0)
{
return (pick32(val, hi, lo) >> lo);
}
// mask [hi,lo] and shift down to start at bit 0
-static inline u_int64_t pickbits64(u_int64_t val, int hi = 63, int lo = 0)
+static inline uint64_t pickbits64(uint64_t val, int hi = 63, int lo = 0)
{
return (pick64(val, hi, lo) >> lo);
}
// result<0> to val
-static inline u_int64_t pickbit(u_int64_t val, int N)
+static inline uint64_t pickbit(uint64_t val, int N)
{
return pickbits64(val, N, N);
}
-static inline u_int32_t uimm(u_int32_t val, int hi, int lo)
+static inline uint32_t uimm(uint32_t val, int hi, int lo)
{
return pickbits32(val, hi, lo);
}
@@ -123,11 +127,11 @@
// SPEC bits(M*N) Replicate(bits(M) x, integer N);
// this is just an educated guess
-u_int64_t replicate(u_int64_t bits, int nbits, int count)
+uint64_t replicate(uint64_t bits, int nbits, int count)
{
- u_int64_t result = 0;
+ uint64_t result = 0;
// nbits may be 64 in which case we want mask to be -1
- u_int64_t mask = ones(nbits);
+ uint64_t mask = ones(nbits);
for (int i = 0; i < count ; i++) {
result <<= nbits;
result |= (bits & mask);
@@ -140,24 +144,24 @@
// encoding must be treated as an UNALLOC instruction
// construct a 32 bit immediate value for a logical immediate operation
-int expandLogicalImmediate(u_int32_t immN, u_int32_t immr,
- u_int32_t imms, u_int64_t &bimm)
+int expandLogicalImmediate(uint32_t immN, uint32_t immr,
+ uint32_t imms, uint64_t &bimm)
{
- int len; // ought to be <= 6
- u_int32_t levels; // 6 bits
- u_int32_t tmask_and; // 6 bits
- u_int32_t wmask_and; // 6 bits
- u_int32_t tmask_or; // 6 bits
- u_int32_t wmask_or; // 6 bits
- u_int64_t imm64; // 64 bits
- u_int64_t tmask, wmask; // 64 bits
- u_int32_t S, R, diff; // 6 bits?
+ int len; // ought to be <= 6
+ uint32_t levels; // 6 bits
+ uint32_t tmask_and; // 6 bits
+ uint32_t wmask_and; // 6 bits
+ uint32_t tmask_or; // 6 bits
+ uint32_t wmask_or; // 6 bits
+ uint64_t imm64; // 64 bits
+ uint64_t tmask, wmask; // 64 bits
+ uint32_t S, R, diff; // 6 bits?
if (immN == 1) {
len = 6; // looks like 7 given the spec above but this cannot be!
} else {
len = 0;
- u_int32_t val = (~imms & 0x3f);
+ uint32_t val = (~imms & 0x3f);
for (int i = 5; i > 0; i--) {
if (val & (1 << i)) {
len = i;
@@ -170,7 +174,7 @@
// for valid inputs leading 1s in immr must be less than leading
// zeros in imms
int len2 = 0; // ought to be < len
- u_int32_t val2 = (~immr & 0x3f);
+ uint32_t val2 = (~immr & 0x3f);
for (int i = 5; i > 0; i--) {
if (!(val2 & (1 << i))) {
len2 = i;
@@ -199,12 +203,12 @@
for (int i = 0; i < 6; i++) {
int nbits = 1 << i;
- u_int64_t and_bit = pickbit(tmask_and, i);
- u_int64_t or_bit = pickbit(tmask_or, i);
- u_int64_t and_bits_sub = replicate(and_bit, 1, nbits);
- u_int64_t or_bits_sub = replicate(or_bit, 1, nbits);
- u_int64_t and_bits_top = (and_bits_sub << nbits) | ones(nbits);
- u_int64_t or_bits_top = (0 << nbits) | or_bits_sub;
+ uint64_t and_bit = pickbit(tmask_and, i);
+ uint64_t or_bit = pickbit(tmask_or, i);
+ uint64_t and_bits_sub = replicate(and_bit, 1, nbits);
+ uint64_t or_bits_sub = replicate(or_bit, 1, nbits);
+ uint64_t and_bits_top = (and_bits_sub << nbits) | ones(nbits);
+ uint64_t or_bits_top = (0 << nbits) | or_bits_sub;
tmask = ((tmask
& (replicate(and_bits_top, 2 * nbits, 32 / nbits)))
@@ -218,12 +222,12 @@
for (int i = 0; i < 6; i++) {
int nbits = 1 << i;
- u_int64_t and_bit = pickbit(wmask_and, i);
- u_int64_t or_bit = pickbit(wmask_or, i);
- u_int64_t and_bits_sub = replicate(and_bit, 1, nbits);
- u_int64_t or_bits_sub = replicate(or_bit, 1, nbits);
- u_int64_t and_bits_top = (ones(nbits) << nbits) | and_bits_sub;
- u_int64_t or_bits_top = (or_bits_sub << nbits) | 0;
+ uint64_t and_bit = pickbit(wmask_and, i);
+ uint64_t or_bit = pickbit(wmask_or, i);
+ uint64_t and_bits_sub = replicate(and_bit, 1, nbits);
+ uint64_t or_bits_sub = replicate(or_bit, 1, nbits);
+ uint64_t and_bits_top = (ones(nbits) << nbits) | and_bits_sub;
+ uint64_t or_bits_top = (or_bits_sub << nbits) | 0;
wmask = ((wmask
& (replicate(and_bits_top, 2 * nbits, 32 / nbits)))
@@ -243,14 +247,17 @@
// constructor to initialise the lookup tables
-static void initLITables() __attribute__ ((constructor));
+static void initLITables();
+// Use an empty struct with a construtor as MSVC doesn't support `__attribute__ ((constructor))`
+// See https://stackoverflow.com/questions/1113409/attribute-constructor-equivalent-in-vc
+static struct initLITables_t { initLITables_t(void) { initLITables(); } } _initLITables;
static void initLITables()
{
li_table_entry_count = 0;
for (unsigned index = 0; index < LI_TABLE_SIZE; index++) {
- u_int32_t N = uimm(index, 12, 12);
- u_int32_t immr = uimm(index, 11, 6);
- u_int32_t imms = uimm(index, 5, 0);
+ uint32_t N = uimm(index, 12, 12);
+ uint32_t immr = uimm(index, 11, 6);
+ uint32_t imms = uimm(index, 5, 0);
if (expandLogicalImmediate(N, immr, imms, LITable[index])) {
InverseLITable[li_table_entry_count].immediate = LITable[index];
InverseLITable[li_table_entry_count].encoding = index;
@@ -264,12 +271,12 @@
// public APIs provided for logical immediate lookup and reverse lookup
-u_int64_t logical_immediate_for_encoding(u_int32_t encoding)
+uint64_t logical_immediate_for_encoding(uint32_t encoding)
{
return LITable[encoding];
}
-u_int32_t encoding_for_logical_immediate(u_int64_t immediate)
+uint32_t encoding_for_logical_immediate(uint64_t immediate)
{
struct li_pair pair;
struct li_pair *result;
@@ -293,15 +300,15 @@
// fpimm[3:0] = fraction (assuming leading 1)
// i.e. F = s * 1.f * 2^(e - b)
-u_int64_t fp_immediate_for_encoding(u_int32_t imm8, int is_dp)
+uint64_t fp_immediate_for_encoding(uint32_t imm8, int is_dp)
{
union {
float fpval;
double dpval;
- u_int64_t val;
+ uint64_t val;
};
- u_int32_t s, e, f;
+ uint32_t s, e, f;
s = (imm8 >> 7 ) & 0x1;
e = (imm8 >> 4) & 0x7;
f = imm8 & 0xf;
@@ -329,7 +336,7 @@
return val;
}
-u_int32_t encoding_for_fp_immediate(float immediate)
+uint32_t encoding_for_fp_immediate(float immediate)
{
// given a float which is of the form
//
@@ -341,10 +348,10 @@
union {
float fpval;
- u_int32_t val;
+ uint32_t val;
};
fpval = immediate;
- u_int32_t s, r, f, res;
+ uint32_t s, r, f, res;
// sign bit is 31
s = (val >> 31) & 0x1;
// exponent is bits 30-23 but we only want the bottom 3 bits
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/immediate_aarch64.hpp openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/immediate_aarch64.hpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/immediate_aarch64.hpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/immediate_aarch64.hpp 2022-01-13 21:56:25.000000000 +0000
@@ -46,9 +46,9 @@
* encoding then a map lookup will return 0xffffffff.
*/
-u_int64_t logical_immediate_for_encoding(u_int32_t encoding);
-u_int32_t encoding_for_logical_immediate(u_int64_t immediate);
-u_int64_t fp_immediate_for_encoding(u_int32_t imm8, int is_dp);
-u_int32_t encoding_for_fp_immediate(float immediate);
+uint64_t logical_immediate_for_encoding(uint32_t encoding);
+uint32_t encoding_for_logical_immediate(uint64_t immediate);
+uint64_t fp_immediate_for_encoding(uint32_t imm8, int is_dp);
+uint32_t encoding_for_fp_immediate(float immediate);
#endif // _IMMEDIATE_H
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/interp_masm_aarch64.cpp openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/interp_masm_aarch64.cpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/interp_masm_aarch64.cpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/interp_masm_aarch64.cpp 2022-01-13 21:56:25.000000000 +0000
@@ -1,6 +1,6 @@
/*
- * Copyright (c) 2003, 2018, Oracle and/or its affiliates. All rights reserved.
- * Copyright (c) 2014, Red Hat Inc. All rights reserved.
+ * Copyright (c) 2003, 2020, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@@ -168,7 +168,7 @@
}
void InterpreterMacroAssembler::get_dispatch() {
- unsigned long offset;
+ uint64_t offset;
adrp(rdispatch, ExternalAddress((address)Interpreter::dispatch_table()), offset);
lea(rdispatch, Address(rdispatch, offset));
}
@@ -759,7 +759,7 @@
// copy
mov(rscratch1, sp);
sub(swap_reg, swap_reg, rscratch1);
- ands(swap_reg, swap_reg, (unsigned long)(7 - os::vm_page_size()));
+ ands(swap_reg, swap_reg, (uint64_t)(7 - os::vm_page_size()));
// Save the test result, for recursive case, the result is zero
str(swap_reg, Address(lock_reg, mark_offset));
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/interpreterRT_aarch64.cpp openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/interpreterRT_aarch64.cpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/interpreterRT_aarch64.cpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/interpreterRT_aarch64.cpp 2022-01-13 21:56:25.000000000 +0000
@@ -1,6 +1,6 @@
/*
- * Copyright (c) 2003, 2018, Oracle and/or its affiliates. All rights reserved.
- * Copyright (c) 2014, Red Hat Inc. All rights reserved.
+ * Copyright (c) 2003, 2020, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@@ -44,215 +44,103 @@
Register InterpreterRuntime::SignatureHandlerGenerator::to() { return sp; }
Register InterpreterRuntime::SignatureHandlerGenerator::temp() { return rscratch1; }
+Register InterpreterRuntime::SignatureHandlerGenerator::next_gpr() {
+ if (_num_reg_int_args < Argument::n_int_register_parameters_c-1) {
+ return as_Register(_num_reg_int_args++ + c_rarg1->encoding());
+ }
+ return noreg;
+}
+
+FloatRegister InterpreterRuntime::SignatureHandlerGenerator::next_fpr() {
+ if (_num_reg_fp_args < Argument::n_float_register_parameters_c) {
+ return as_FloatRegister(_num_reg_fp_args++);
+ }
+ return fnoreg;
+}
+
+int InterpreterRuntime::SignatureHandlerGenerator::next_stack_offset() {
+ int ret = _stack_offset;
+ _stack_offset += wordSize;
+ return ret;
+}
+
InterpreterRuntime::SignatureHandlerGenerator::SignatureHandlerGenerator(
const methodHandle& method, CodeBuffer* buffer) : NativeSignatureIterator(method) {
_masm = new MacroAssembler(buffer);
- _num_int_args = (method->is_static() ? 1 : 0);
- _num_fp_args = 0;
+ _num_reg_int_args = (method->is_static() ? 1 : 0);
+ _num_reg_fp_args = 0;
_stack_offset = 0;
}
void InterpreterRuntime::SignatureHandlerGenerator::pass_int() {
const Address src(from(), Interpreter::local_offset_in_bytes(offset()));
- switch (_num_int_args) {
- case 0:
- __ ldr(c_rarg1, src);
- _num_int_args++;
- break;
- case 1:
- __ ldr(c_rarg2, src);
- _num_int_args++;
- break;
- case 2:
- __ ldr(c_rarg3, src);
- _num_int_args++;
- break;
- case 3:
- __ ldr(c_rarg4, src);
- _num_int_args++;
- break;
- case 4:
- __ ldr(c_rarg5, src);
- _num_int_args++;
- break;
- case 5:
- __ ldr(c_rarg6, src);
- _num_int_args++;
- break;
- case 6:
- __ ldr(c_rarg7, src);
- _num_int_args++;
- break;
- default:
- __ ldr(r0, src);
- __ str(r0, Address(to(), _stack_offset));
- _stack_offset += wordSize;
- _num_int_args++;
- break;
+ Register reg = next_gpr();
+ if (reg != noreg) {
+ __ ldr(reg, src);
+ } else {
+ __ ldrw(r0, src);
+ __ strw(r0, Address(to(), next_stack_offset()));
}
}
void InterpreterRuntime::SignatureHandlerGenerator::pass_long() {
const Address src(from(), Interpreter::local_offset_in_bytes(offset() + 1));
- switch (_num_int_args) {
- case 0:
- __ ldr(c_rarg1, src);
- _num_int_args++;
- break;
- case 1:
- __ ldr(c_rarg2, src);
- _num_int_args++;
- break;
- case 2:
- __ ldr(c_rarg3, src);
- _num_int_args++;
- break;
- case 3:
- __ ldr(c_rarg4, src);
- _num_int_args++;
- break;
- case 4:
- __ ldr(c_rarg5, src);
- _num_int_args++;
- break;
- case 5:
- __ ldr(c_rarg6, src);
- _num_int_args++;
- break;
- case 6:
- __ ldr(c_rarg7, src);
- _num_int_args++;
- break;
- default:
+ Register reg = next_gpr();
+ if (reg != noreg) {
+ __ ldr(reg, src);
+ } else {
__ ldr(r0, src);
- __ str(r0, Address(to(), _stack_offset));
- _stack_offset += wordSize;
- _num_int_args++;
- break;
+ __ str(r0, Address(to(), next_stack_offset()));
}
}
void InterpreterRuntime::SignatureHandlerGenerator::pass_float() {
const Address src(from(), Interpreter::local_offset_in_bytes(offset()));
- if (_num_fp_args < Argument::n_float_register_parameters_c) {
- __ ldrs(as_FloatRegister(_num_fp_args++), src);
+ FloatRegister reg = next_fpr();
+ if (reg != fnoreg) {
+ __ ldrs(reg, src);
} else {
__ ldrw(r0, src);
- __ strw(r0, Address(to(), _stack_offset));
- _stack_offset += wordSize;
- _num_fp_args++;
+ __ strw(r0, Address(to(), next_stack_offset()));
}
}
void InterpreterRuntime::SignatureHandlerGenerator::pass_double() {
const Address src(from(), Interpreter::local_offset_in_bytes(offset() + 1));
- if (_num_fp_args < Argument::n_float_register_parameters_c) {
- __ ldrd(as_FloatRegister(_num_fp_args++), src);
+ FloatRegister reg = next_fpr();
+ if (reg != fnoreg) {
+ __ ldrd(reg, src);
} else {
__ ldr(r0, src);
- __ str(r0, Address(to(), _stack_offset));
- _stack_offset += wordSize;
- _num_fp_args++;
+ __ str(r0, Address(to(), next_stack_offset()));
}
}
void InterpreterRuntime::SignatureHandlerGenerator::pass_object() {
-
- switch (_num_int_args) {
- case 0:
+ Register reg = next_gpr();
+ if (reg == c_rarg1) {
assert(offset() == 0, "argument register 1 can only be (non-null) receiver");
__ add(c_rarg1, from(), Interpreter::local_offset_in_bytes(offset()));
- _num_int_args++;
- break;
- case 1:
- {
- __ add(r0, from(), Interpreter::local_offset_in_bytes(offset()));
- __ mov(c_rarg2, 0);
- __ ldr(temp(), r0);
- Label L;
- __ cbz(temp(), L);
- __ mov(c_rarg2, r0);
- __ bind(L);
- _num_int_args++;
- break;
- }
- case 2:
- {
- __ add(r0, from(), Interpreter::local_offset_in_bytes(offset()));
- __ mov(c_rarg3, 0);
- __ ldr(temp(), r0);
- Label L;
- __ cbz(temp(), L);
- __ mov(c_rarg3, r0);
- __ bind(L);
- _num_int_args++;
- break;
- }
- case 3:
- {
- __ add(r0, from(), Interpreter::local_offset_in_bytes(offset()));
- __ mov(c_rarg4, 0);
- __ ldr(temp(), r0);
- Label L;
- __ cbz(temp(), L);
- __ mov(c_rarg4, r0);
- __ bind(L);
- _num_int_args++;
- break;
- }
- case 4:
- {
- __ add(r0, from(), Interpreter::local_offset_in_bytes(offset()));
- __ mov(c_rarg5, 0);
- __ ldr(temp(), r0);
- Label L;
- __ cbz(temp(), L);
- __ mov(c_rarg5, r0);
- __ bind(L);
- _num_int_args++;
- break;
- }
- case 5:
- {
- __ add(r0, from(), Interpreter::local_offset_in_bytes(offset()));
- __ mov(c_rarg6, 0);
- __ ldr(temp(), r0);
- Label L;
- __ cbz(temp(), L);
- __ mov(c_rarg6, r0);
- __ bind(L);
- _num_int_args++;
- break;
- }
- case 6:
- {
- __ add(r0, from(), Interpreter::local_offset_in_bytes(offset()));
- __ mov(c_rarg7, 0);
- __ ldr(temp(), r0);
- Label L;
- __ cbz(temp(), L);
- __ mov(c_rarg7, r0);
- __ bind(L);
- _num_int_args++;
- break;
- }
- default:
- {
- __ add(r0, from(), Interpreter::local_offset_in_bytes(offset()));
- __ ldr(temp(), r0);
- Label L;
- __ cbnz(temp(), L);
- __ mov(r0, zr);
- __ bind(L);
- __ str(r0, Address(to(), _stack_offset));
- _stack_offset += wordSize;
- _num_int_args++;
- break;
- }
+ } else if (reg != noreg) {
+ __ add(r0, from(), Interpreter::local_offset_in_bytes(offset()));
+ __ mov(reg, 0);
+ __ ldr(temp(), r0);
+ Label L;
+ __ cbz(temp(), L);
+ __ mov(reg, r0);
+ __ bind(L);
+ } else {
+ __ add(r0, from(), Interpreter::local_offset_in_bytes(offset()));
+ __ ldr(temp(), r0);
+ Label L;
+ __ cbnz(temp(), L);
+ __ mov(r0, zr);
+ __ bind(L);
+ __ str(r0, Address(to(), next_stack_offset()));
}
}
@@ -281,77 +169,77 @@
intptr_t* _int_args;
intptr_t* _fp_args;
intptr_t* _fp_identifiers;
- unsigned int _num_int_args;
- unsigned int _num_fp_args;
+ unsigned int _num_reg_int_args;
+ unsigned int _num_reg_fp_args;
- virtual void pass_int()
- {
- jint from_obj = *(jint *)(_from+Interpreter::local_offset_in_bytes(0));
+ intptr_t* single_slot_addr() {
+ intptr_t* from_addr = (intptr_t*)(_from+Interpreter::local_offset_in_bytes(0));
_from -= Interpreter::stackElementSize;
-
- if (_num_int_args < Argument::n_int_register_parameters_c-1) {
- *_int_args++ = from_obj;
- _num_int_args++;
- } else {
- *_to++ = from_obj;
- _num_int_args++;
- }
+ return from_addr;
}
- virtual void pass_long()
- {
- intptr_t from_obj = *(intptr_t*)(_from+Interpreter::local_offset_in_bytes(1));
+ intptr_t* double_slot_addr() {
+ intptr_t* from_addr = (intptr_t*)(_from+Interpreter::local_offset_in_bytes(1));
_from -= 2*Interpreter::stackElementSize;
+ return from_addr;
+ }
- if (_num_int_args < Argument::n_int_register_parameters_c-1) {
- *_int_args++ = from_obj;
- _num_int_args++;
- } else {
- *_to++ = from_obj;
- _num_int_args++;
+ int pass_gpr(intptr_t value) {
+ if (_num_reg_int_args < Argument::n_int_register_parameters_c-1) {
+ *_int_args++ = value;
+ return _num_reg_int_args++;
}
+ return -1;
}
- virtual void pass_object()
- {
- intptr_t *from_addr = (intptr_t*)(_from + Interpreter::local_offset_in_bytes(0));
- _from -= Interpreter::stackElementSize;
+ int pass_fpr(intptr_t value) {
+ if (_num_reg_fp_args < Argument::n_float_register_parameters_c) {
+ *_fp_args++ = value;
+ return _num_reg_fp_args++;
+ }
+ return -1;
+ }
- if (_num_int_args < Argument::n_int_register_parameters_c-1) {
- *_int_args++ = (*from_addr == 0) ? NULL : (intptr_t)from_addr;
- _num_int_args++;
- } else {
- *_to++ = (*from_addr == 0) ? NULL : (intptr_t) from_addr;
- _num_int_args++;
+ void pass_stack(intptr_t value) {
+ *_to++ = value;
+ }
+
+ virtual void pass_int() {
+ jint value = *(jint*)single_slot_addr();
+ if (pass_gpr(value) < 0) {
+ pass_stack(value);
}
}
- virtual void pass_float()
- {
- jint from_obj = *(jint*)(_from+Interpreter::local_offset_in_bytes(0));
- _from -= Interpreter::stackElementSize;
+ virtual void pass_long() {
+ intptr_t value = *double_slot_addr();
+ if (pass_gpr(value) < 0) {
+ pass_stack(value);
+ }
+ }
- if (_num_fp_args < Argument::n_float_register_parameters_c) {
- *_fp_args++ = from_obj;
- _num_fp_args++;
- } else {
- *_to++ = from_obj;
- _num_fp_args++;
+ virtual void pass_object() {
+ intptr_t* addr = single_slot_addr();
+ intptr_t value = *addr == 0 ? NULL : (intptr_t)addr;
+ if (pass_gpr(value) < 0) {
+ pass_stack(value);
}
}
- virtual void pass_double()
- {
- intptr_t from_obj = *(intptr_t*)(_from+Interpreter::local_offset_in_bytes(1));
- _from -= 2*Interpreter::stackElementSize;
+ virtual void pass_float() {
+ jint value = *(jint*)single_slot_addr();
+ if (pass_fpr(value) < 0) {
+ pass_stack(value);
+ }
+ }
- if (_num_fp_args < Argument::n_float_register_parameters_c) {
- *_fp_args++ = from_obj;
- *_fp_identifiers |= (1 << _num_fp_args); // mark as double
- _num_fp_args++;
+ virtual void pass_double() {
+ intptr_t value = *double_slot_addr();
+ int arg = pass_fpr(value);
+ if (0 <= arg) {
+ *_fp_identifiers |= (1ull << arg); // mark as double
} else {
- *_to++ = from_obj;
- _num_fp_args++;
+ pass_stack(value);
}
}
@@ -366,8 +254,8 @@
_fp_args = to - 8;
_fp_identifiers = to - 9;
*(int*) _fp_identifiers = 0;
- _num_int_args = (method->is_static() ? 1 : 0);
- _num_fp_args = 0;
+ _num_reg_int_args = (method->is_static() ? 1 : 0);
+ _num_reg_fp_args = 0;
}
};
@@ -383,7 +271,7 @@
// handle arguments
SlowSignatureHandler ssh(m, (address)from, to);
- ssh.iterate(UCONST64(-1));
+ ssh.iterate((uint64_t)CONST64(-1));
// return result handler
return Interpreter::result_handler(m->result_type());
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/interpreterRT_aarch64.hpp openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/interpreterRT_aarch64.hpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/interpreterRT_aarch64.hpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/interpreterRT_aarch64.hpp 2022-01-13 21:56:25.000000000 +0000
@@ -34,8 +34,8 @@
class SignatureHandlerGenerator: public NativeSignatureIterator {
private:
MacroAssembler* _masm;
- unsigned int _num_fp_args;
- unsigned int _num_int_args;
+ unsigned int _num_reg_fp_args;
+ unsigned int _num_reg_int_args;
int _stack_offset;
void pass_int();
@@ -44,6 +44,10 @@
void pass_double();
void pass_object();
+ Register next_gpr();
+ FloatRegister next_fpr();
+ int next_stack_offset();
+
public:
// Creation
SignatureHandlerGenerator(const methodHandle& method, CodeBuffer* buffer);
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/jniFastGetField_aarch64.cpp openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/jniFastGetField_aarch64.cpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/jniFastGetField_aarch64.cpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/jniFastGetField_aarch64.cpp 2022-01-13 21:56:25.000000000 +0000
@@ -1,6 +1,6 @@
/*
- * Copyright (c) 2004, 2017, Oracle and/or its affiliates. All rights reserved.
- * Copyright (c) 2014, Red Hat Inc. All rights reserved.
+ * Copyright (c) 2004, 2020, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@@ -73,7 +73,7 @@
Label slow;
- unsigned long offset;
+ uint64_t offset;
__ adrp(rcounter_addr,
SafepointSynchronize::safepoint_counter_addr(), offset);
Address safepoint_counter_addr(rcounter_addr, offset);
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/macroAssembler_aarch64_aes.cpp openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/macroAssembler_aarch64_aes.cpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/macroAssembler_aarch64_aes.cpp 1970-01-01 00:00:00.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/macroAssembler_aarch64_aes.cpp 2022-01-13 21:56:25.000000000 +0000
@@ -0,0 +1,685 @@
+/*
+ * Copyright (c) 2003, 2021, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2014, 2021, Red Hat Inc. All rights reserved.
+ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+ *
+ * This code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 only, as
+ * published by the Free Software Foundation.
+ *
+ * This code is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * version 2 for more details (a copy is included in the LICENSE file that
+ * accompanied this code).
+ *
+ * You should have received a copy of the GNU General Public License version
+ * 2 along with this work; if not, write to the Free Software Foundation,
+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
+ * or visit www.oracle.com if you need additional information or have any
+ * questions.
+ *
+ */
+
+#include "precompiled.hpp"
+
+#include "asm/assembler.hpp"
+#include "asm/assembler.inline.hpp"
+#include "macroAssembler_aarch64.hpp"
+#include "memory/resourceArea.hpp"
+#include "runtime/stubRoutines.hpp"
+
+void MacroAssembler::aesecb_decrypt(Register from, Register to, Register key, Register keylen) {
+ Label L_doLast;
+
+ ld1(v0, T16B, from); // get 16 bytes of input
+
+ ld1(v5, T16B, post(key, 16));
+ rev32(v5, T16B, v5);
+
+ ld1(v1, v2, v3, v4, T16B, post(key, 64));
+ rev32(v1, T16B, v1);
+ rev32(v2, T16B, v2);
+ rev32(v3, T16B, v3);
+ rev32(v4, T16B, v4);
+ aesd(v0, v1);
+ aesimc(v0, v0);
+ aesd(v0, v2);
+ aesimc(v0, v0);
+ aesd(v0, v3);
+ aesimc(v0, v0);
+ aesd(v0, v4);
+ aesimc(v0, v0);
+
+ ld1(v1, v2, v3, v4, T16B, post(key, 64));
+ rev32(v1, T16B, v1);
+ rev32(v2, T16B, v2);
+ rev32(v3, T16B, v3);
+ rev32(v4, T16B, v4);
+ aesd(v0, v1);
+ aesimc(v0, v0);
+ aesd(v0, v2);
+ aesimc(v0, v0);
+ aesd(v0, v3);
+ aesimc(v0, v0);
+ aesd(v0, v4);
+ aesimc(v0, v0);
+
+ ld1(v1, v2, T16B, post(key, 32));
+ rev32(v1, T16B, v1);
+ rev32(v2, T16B, v2);
+
+ cmpw(keylen, 44);
+ br(Assembler::EQ, L_doLast);
+
+ aesd(v0, v1);
+ aesimc(v0, v0);
+ aesd(v0, v2);
+ aesimc(v0, v0);
+
+ ld1(v1, v2, T16B, post(key, 32));
+ rev32(v1, T16B, v1);
+ rev32(v2, T16B, v2);
+
+ cmpw(keylen, 52);
+ br(Assembler::EQ, L_doLast);
+
+ aesd(v0, v1);
+ aesimc(v0, v0);
+ aesd(v0, v2);
+ aesimc(v0, v0);
+
+ ld1(v1, v2, T16B, post(key, 32));
+ rev32(v1, T16B, v1);
+ rev32(v2, T16B, v2);
+
+ bind(L_doLast);
+
+ aesd(v0, v1);
+ aesimc(v0, v0);
+ aesd(v0, v2);
+
+ eor(v0, T16B, v0, v5);
+
+ st1(v0, T16B, to);
+
+ // Preserve the address of the start of the key
+ sub(key, key, keylen, LSL, exact_log2(sizeof (jint)));
+}
+
+// Load expanded key into v17..v31
+void MacroAssembler::aesenc_loadkeys(Register key, Register keylen) {
+ Label L_loadkeys_44, L_loadkeys_52;
+ cmpw(keylen, 52);
+ br(Assembler::LO, L_loadkeys_44);
+ br(Assembler::EQ, L_loadkeys_52);
+
+ ld1(v17, v18, T16B, post(key, 32));
+ rev32(v17, T16B, v17);
+ rev32(v18, T16B, v18);
+ bind(L_loadkeys_52);
+ ld1(v19, v20, T16B, post(key, 32));
+ rev32(v19, T16B, v19);
+ rev32(v20, T16B, v20);
+ bind(L_loadkeys_44);
+ ld1(v21, v22, v23, v24, T16B, post(key, 64));
+ rev32(v21, T16B, v21);
+ rev32(v22, T16B, v22);
+ rev32(v23, T16B, v23);
+ rev32(v24, T16B, v24);
+ ld1(v25, v26, v27, v28, T16B, post(key, 64));
+ rev32(v25, T16B, v25);
+ rev32(v26, T16B, v26);
+ rev32(v27, T16B, v27);
+ rev32(v28, T16B, v28);
+ ld1(v29, v30, v31, T16B, post(key, 48));
+ rev32(v29, T16B, v29);
+ rev32(v30, T16B, v30);
+ rev32(v31, T16B, v31);
+
+ // Preserve the address of the start of the key
+ sub(key, key, keylen, LSL, exact_log2(sizeof (jint)));
+}
+
+// NeoverseTM N1Software Optimization Guide:
+// Adjacent AESE/AESMC instruction pairs and adjacent AESD/AESIMC
+// instruction pairs will exhibit the performance characteristics
+// described in Section 4.6.
+void MacroAssembler::aes_round(FloatRegister input, FloatRegister subkey) {
+ aese(input, subkey); aesmc(input, input);
+}
+
+// KernelGenerator
+//
+// The abstract base class of an unrolled function generator.
+// Subclasses override generate(), length(), and next() to generate
+// unrolled and interleaved functions.
+//
+// The core idea is that a subclass defines a method which generates
+// the base case of a function and a method to generate a clone of it,
+// shifted to a different set of registers. KernelGenerator will then
+// generate several interleaved copies of the function, with each one
+// using a different set of registers.
+
+// The subclass must implement three methods: length(), which is the
+// number of instruction bundles in the intrinsic, generate(int n)
+// which emits the nth instruction bundle in the intrinsic, and next()
+// which takes an instance of the generator and returns a version of it,
+// shifted to a new set of registers.
+
+class KernelGenerator: public MacroAssembler {
+protected:
+ const int _unrolls;
+public:
+ KernelGenerator(Assembler *as, int unrolls)
+ : MacroAssembler(as->code()), _unrolls(unrolls) { }
+ virtual void generate(int index) = 0;
+ virtual int length() = 0;
+ virtual KernelGenerator *next() = 0;
+ int unrolls() { return _unrolls; }
+ void unroll();
+};
+
+void KernelGenerator::unroll() {
+ ResourceMark rm;
+ KernelGenerator **generators
+ = NEW_RESOURCE_ARRAY(KernelGenerator *, unrolls());
+
+ generators[0] = this;
+ for (int i = 1; i < unrolls(); i++) {
+ generators[i] = generators[i-1]->next();
+ }
+
+ for (int j = 0; j < length(); j++) {
+ for (int i = 0; i < unrolls(); i++) {
+ generators[i]->generate(j);
+ }
+ }
+}
+
+// An unrolled and interleaved generator for AES encryption.
+class AESKernelGenerator: public KernelGenerator {
+ Register _from, _to;
+ const Register _keylen;
+ FloatRegister _data;
+ const FloatRegister _subkeys;
+ bool _once;
+ Label _rounds_44, _rounds_52;
+
+public:
+ AESKernelGenerator(Assembler *as, int unrolls,
+ Register from, Register to, Register keylen, FloatRegister data,
+ FloatRegister subkeys, bool once = true)
+ : KernelGenerator(as, unrolls),
+ _from(from), _to(to), _keylen(keylen), _data(data),
+ _subkeys(subkeys), _once(once) {
+ }
+
+ virtual void generate(int index) {
+ switch (index) {
+ case 0:
+ if (_from != noreg) {
+ ld1(_data, T16B, _from); // get 16 bytes of input
+ }
+ break;
+ case 1:
+ if (_once) {
+ cmpw(_keylen, 52);
+ br(Assembler::LO, _rounds_44);
+ br(Assembler::EQ, _rounds_52);
+ }
+ break;
+ case 2: aes_round(_data, _subkeys + 0); break;
+ case 3: aes_round(_data, _subkeys + 1); break;
+ case 4:
+ if (_once) bind(_rounds_52);
+ break;
+ case 5: aes_round(_data, _subkeys + 2); break;
+ case 6: aes_round(_data, _subkeys + 3); break;
+ case 7:
+ if (_once) bind(_rounds_44);
+ break;
+ case 8: aes_round(_data, _subkeys + 4); break;
+ case 9: aes_round(_data, _subkeys + 5); break;
+ case 10: aes_round(_data, _subkeys + 6); break;
+ case 11: aes_round(_data, _subkeys + 7); break;
+ case 12: aes_round(_data, _subkeys + 8); break;
+ case 13: aes_round(_data, _subkeys + 9); break;
+ case 14: aes_round(_data, _subkeys + 10); break;
+ case 15: aes_round(_data, _subkeys + 11); break;
+ case 16: aes_round(_data, _subkeys + 12); break;
+ case 17: aese(_data, _subkeys + 13); break;
+ case 18: eor(_data, T16B, _data, _subkeys + 14); break;
+ case 19:
+ if (_to != noreg) {
+ st1(_data, T16B, _to);
+ }
+ break;
+ default: ShouldNotReachHere();
+ }
+ }
+
+ virtual KernelGenerator *next() {
+ return new AESKernelGenerator(this, _unrolls,
+ _from, _to, _keylen,
+ _data + 1, _subkeys, /*once*/false);
+ }
+
+ virtual int length() { return 20; }
+};
+
+// Uses expanded key in v17..v31
+// Returns encrypted values in inputs.
+// If to != noreg, store value at to; likewise from
+// Preserves key, keylen
+// Increments from, to
+// Input data in v0, v1, ...
+// unrolls controls the number of times to unroll the generated function
+void MacroAssembler::aesecb_encrypt(Register from, Register to, Register keylen,
+ FloatRegister data, int unrolls) {
+ AESKernelGenerator(this, unrolls, from, to, keylen, data, v17) .unroll();
+}
+
+// ghash_multiply and ghash_reduce are the non-unrolled versions of
+// the GHASH function generators.
+void MacroAssembler::ghash_multiply(FloatRegister result_lo, FloatRegister result_hi,
+ FloatRegister a, FloatRegister b, FloatRegister a1_xor_a0,
+ FloatRegister tmp1, FloatRegister tmp2, FloatRegister tmp3) {
+ // Karatsuba multiplication performs a 128*128 -> 256-bit
+ // multiplication in three 128-bit multiplications and a few
+ // additions.
+ //
+ // (C1:C0) = A1*B1, (D1:D0) = A0*B0, (E1:E0) = (A0+A1)(B0+B1)
+ // (A1:A0)(B1:B0) = C1:(C0+C1+D1+E1):(D1+C0+D0+E0):D0
+ //
+ // Inputs:
+ //
+ // A0 in a.d[0] (subkey)
+ // A1 in a.d[1]
+ // (A1+A0) in a1_xor_a0.d[0]
+ //
+ // B0 in b.d[0] (state)
+ // B1 in b.d[1]
+
+ ext(tmp1, T16B, b, b, 0x08);
+ pmull2(result_hi, T1Q, b, a, T2D); // A1*B1
+ eor(tmp1, T16B, tmp1, b); // (B1+B0)
+ pmull(result_lo, T1Q, b, a, T1D); // A0*B0
+ pmull(tmp2, T1Q, tmp1, a1_xor_a0, T1D); // (A1+A0)(B1+B0)
+
+ ext(tmp1, T16B, result_lo, result_hi, 0x08);
+ eor(tmp3, T16B, result_hi, result_lo); // A1*B1+A0*B0
+ eor(tmp2, T16B, tmp2, tmp1);
+ eor(tmp2, T16B, tmp2, tmp3);
+
+ // Register pair holds the result of carry-less multiplication
+ ins(result_hi, D, tmp2, 0, 1);
+ ins(result_lo, D, tmp2, 1, 0);
+}
+
+void MacroAssembler::ghash_reduce(FloatRegister result, FloatRegister lo, FloatRegister hi,
+ FloatRegister p, FloatRegister vzr, FloatRegister t1) {
+ const FloatRegister t0 = result;
+
+ // The GCM field polynomial f is z^128 + p(z), where p =
+ // z^7+z^2+z+1.
+ //
+ // z^128 === -p(z) (mod (z^128 + p(z)))
+ //
+ // so, given that the product we're reducing is
+ // a == lo + hi * z^128
+ // substituting,
+ // === lo - hi * p(z) (mod (z^128 + p(z)))
+ //
+ // we reduce by multiplying hi by p(z) and subtracting the result
+ // from (i.e. XORing it with) lo. Because p has no nonzero high
+ // bits we can do this with two 64-bit multiplications, lo*p and
+ // hi*p.
+
+ pmull2(t0, T1Q, hi, p, T2D);
+ ext(t1, T16B, t0, vzr, 8);
+ eor(hi, T16B, hi, t1);
+ ext(t1, T16B, vzr, t0, 8);
+ eor(lo, T16B, lo, t1);
+ pmull(t0, T1Q, hi, p, T1D);
+ eor(result, T16B, lo, t0);
+}
+
+class GHASHMultiplyGenerator: public KernelGenerator {
+ FloatRegister _result_lo, _result_hi, _b,
+ _a, _vzr, _a1_xor_a0, _p,
+ _tmp1, _tmp2, _tmp3;
+
+public:
+ GHASHMultiplyGenerator(Assembler *as, int unrolls,
+ FloatRegister result_lo, FloatRegister result_hi,
+ /* offsetted registers */
+ FloatRegister b,
+ /* non-offsetted (shared) registers */
+ FloatRegister a, FloatRegister a1_xor_a0, FloatRegister p, FloatRegister vzr,
+ /* offseted (temp) registers */
+ FloatRegister tmp1, FloatRegister tmp2, FloatRegister tmp3)
+ : KernelGenerator(as, unrolls),
+ _result_lo(result_lo), _result_hi(result_hi), _b(b),
+ _a(a), _vzr(vzr), _a1_xor_a0(a1_xor_a0), _p(p),
+ _tmp1(tmp1), _tmp2(tmp2), _tmp3(tmp3) { }
+
+ static const int register_stride = 7;
+
+ virtual void generate(int index) {
+ // Karatsuba multiplication performs a 128*128 -> 256-bit
+ // multiplication in three 128-bit multiplications and a few
+ // additions.
+ //
+ // (C1:C0) = A1*B1, (D1:D0) = A0*B0, (E1:E0) = (A0+A1)(B0+B1)
+ // (A1:A0)(B1:B0) = C1:(C0+C1+D1+E1):(D1+C0+D0+E0):D0
+ //
+ // Inputs:
+ //
+ // A0 in a.d[0] (subkey)
+ // A1 in a.d[1]
+ // (A1+A0) in a1_xor_a0.d[0]
+ //
+ // B0 in b.d[0] (state)
+ // B1 in b.d[1]
+
+ switch (index) {
+ case 0: ext(_tmp1, T16B, _b, _b, 0x08); break;
+ case 1: pmull2(_result_hi, T1Q, _b, _a, T2D); // A1*B1
+ break;
+ case 2: eor(_tmp1, T16B, _tmp1, _b); // (B1+B0)
+ break;
+ case 3: pmull(_result_lo, T1Q, _b, _a, T1D); // A0*B0
+ break;
+ case 4: pmull(_tmp2, T1Q, _tmp1, _a1_xor_a0, T1D); // (A1+A0)(B1+B0)
+ break;
+
+ case 5: ext(_tmp1, T16B, _result_lo, _result_hi, 0x08); break;
+ case 6: eor(_tmp3, T16B, _result_hi, _result_lo); // A1*B1+A0*B0
+ break;
+ case 7: eor(_tmp2, T16B, _tmp2, _tmp1); break;
+ case 8: eor(_tmp2, T16B, _tmp2, _tmp3); break;
+
+ // Register pair <_result_hi:_result_lo> holds the _result of carry-less multiplication
+ case 9: ins(_result_hi, D, _tmp2, 0, 1); break;
+ case 10: ins(_result_lo, D, _tmp2, 1, 0); break;
+ default: ShouldNotReachHere();
+ }
+ }
+
+ virtual KernelGenerator *next() {
+ GHASHMultiplyGenerator *result
+ = new GHASHMultiplyGenerator(this, _unrolls, _result_lo, _result_hi,
+ _b, _a, _a1_xor_a0, _p, _vzr,
+ _tmp1, _tmp2, _tmp3);
+ result->_result_lo += register_stride;
+ result->_result_hi += register_stride;
+ result->_b += register_stride;
+ result->_tmp1 += register_stride;
+ result->_tmp2 += register_stride;
+ result->_tmp3 += register_stride;
+ return result;
+ }
+
+ virtual int length() { return 11; }
+};
+
+// Reduce the 128-bit product in hi:lo by the GCM field polynomial.
+// The FloatRegister argument called data is optional: if it is a
+// valid register, we interleave LD1 instructions with the
+// reduction. This is to reduce latency next time around the loop.
+class GHASHReduceGenerator: public KernelGenerator {
+ FloatRegister _result, _lo, _hi, _p, _vzr, _data, _t1;
+ int _once;
+public:
+ GHASHReduceGenerator(Assembler *as, int unrolls,
+ /* offsetted registers */
+ FloatRegister result, FloatRegister lo, FloatRegister hi,
+ /* non-offsetted (shared) registers */
+ FloatRegister p, FloatRegister vzr, FloatRegister data,
+ /* offseted (temp) registers */
+ FloatRegister t1)
+ : KernelGenerator(as, unrolls),
+ _result(result), _lo(lo), _hi(hi),
+ _p(p), _vzr(vzr), _data(data), _t1(t1), _once(true) { }
+
+ static const int register_stride = 7;
+
+ virtual void generate(int index) {
+ const FloatRegister t0 = _result;
+
+ switch (index) {
+ // The GCM field polynomial f is z^128 + p(z), where p =
+ // z^7+z^2+z+1.
+ //
+ // z^128 === -p(z) (mod (z^128 + p(z)))
+ //
+ // so, given that the product we're reducing is
+ // a == lo + hi * z^128
+ // substituting,
+ // === lo - hi * p(z) (mod (z^128 + p(z)))
+ //
+ // we reduce by multiplying hi by p(z) and subtracting the _result
+ // from (i.e. XORing it with) lo. Because p has no nonzero high
+ // bits we can do this with two 64-bit multiplications, lo*p and
+ // hi*p.
+
+ case 0: pmull2(t0, T1Q, _hi, _p, T2D); break;
+ case 1: ext(_t1, T16B, t0, _vzr, 8); break;
+ case 2: eor(_hi, T16B, _hi, _t1); break;
+ case 3: ext(_t1, T16B, _vzr, t0, 8); break;
+ case 4: eor(_lo, T16B, _lo, _t1); break;
+ case 5: pmull(t0, T1Q, _hi, _p, T1D); break;
+ case 6: eor(_result, T16B, _lo, t0); break;
+ default: ShouldNotReachHere();
+ }
+
+ // Sprinkle load instructions into the generated instructions
+ if (_data->is_valid() && _once) {
+ assert(length() >= unrolls(), "not enough room for inteleaved loads");
+ if (index < unrolls()) {
+ ld1((_data + index*register_stride), T16B, post(r2, 0x10));
+ }
+ }
+ }
+
+ virtual KernelGenerator *next() {
+ GHASHReduceGenerator *result
+ = new GHASHReduceGenerator(this, _unrolls,
+ _result, _lo, _hi, _p, _vzr, _data, _t1);
+ result->_result += register_stride;
+ result->_hi += register_stride;
+ result->_lo += register_stride;
+ result->_t1 += register_stride;
+ result->_once = false;
+ return result;
+ }
+
+ int length() { return 7; }
+};
+
+// Perform a GHASH multiply/reduce on a single FloatRegister.
+void MacroAssembler::ghash_modmul(FloatRegister result,
+ FloatRegister result_lo, FloatRegister result_hi, FloatRegister b,
+ FloatRegister a, FloatRegister vzr, FloatRegister a1_xor_a0, FloatRegister p,
+ FloatRegister t1, FloatRegister t2, FloatRegister t3) {
+ ghash_multiply(result_lo, result_hi, a, b, a1_xor_a0, t1, t2, t3);
+ ghash_reduce(result, result_lo, result_hi, p, vzr, t1);
+}
+
+// Interleaved GHASH processing.
+//
+// Clobbers all vector registers.
+//
+void MacroAssembler::ghash_processBlocks_wide(address field_polynomial, Register state,
+ Register subkeyH,
+ Register data, Register blocks, int unrolls) {
+ int register_stride = 7;
+
+ // Bafflingly, GCM uses little-endian for the byte order, but
+ // big-endian for the bit order. For example, the polynomial 1 is
+ // represented as the 16-byte string 80 00 00 00 | 12 bytes of 00.
+ //
+ // So, we must either reverse the bytes in each word and do
+ // everything big-endian or reverse the bits in each byte and do
+ // it little-endian. On AArch64 it's more idiomatic to reverse
+ // the bits in each byte (we have an instruction, RBIT, to do
+ // that) and keep the data in little-endian bit order throught the
+ // calculation, bit-reversing the inputs and outputs.
+
+ assert(unrolls * register_stride < 32, "out of registers");
+
+ FloatRegister a1_xor_a0 = v28;
+ FloatRegister Hprime = v29;
+ FloatRegister vzr = v30;
+ FloatRegister p = v31;
+ eor(vzr, T16B, vzr, vzr); // zero register
+
+ ldrq(p, field_polynomial); // The field polynomial
+
+ ldrq(v0, Address(state));
+ ldrq(Hprime, Address(subkeyH));
+
+ rev64(v0, T16B, v0); // Bit-reverse words in state and subkeyH
+ rbit(v0, T16B, v0);
+ rev64(Hprime, T16B, Hprime);
+ rbit(Hprime, T16B, Hprime);
+
+ // Powers of H -> Hprime
+
+ Label already_calculated, done;
+ {
+ // The first time around we'll have to calculate H**2, H**3, etc.
+ // Look at the largest power of H in the subkeyH array to see if
+ // it's already been calculated.
+ ldp(rscratch1, rscratch2, Address(subkeyH, 16 * (unrolls - 1)));
+ orr(rscratch1, rscratch1, rscratch2);
+ cbnz(rscratch1, already_calculated);
+
+ orr(v6, T16B, Hprime, Hprime); // Start with H in v6 and Hprime
+ for (int i = 1; i < unrolls; i++) {
+ ext(a1_xor_a0, T16B, Hprime, Hprime, 0x08); // long-swap subkeyH into a1_xor_a0
+ eor(a1_xor_a0, T16B, a1_xor_a0, Hprime); // xor subkeyH into subkeyL (Karatsuba: (A1+A0))
+ ghash_modmul(/*result*/v6, /*result_lo*/v5, /*result_hi*/v4, /*b*/v6,
+ Hprime, vzr, a1_xor_a0, p,
+ /*temps*/v1, v3, v2);
+ rev64(v1, T16B, v6);
+ rbit(v1, T16B, v1);
+ strq(v1, Address(subkeyH, 16 * i));
+ }
+ b(done);
+ }
+ {
+ bind(already_calculated);
+
+ // Load the largest power of H we need into v6.
+ ldrq(v6, Address(subkeyH, 16 * (unrolls - 1)));
+ rev64(v6, T16B, v6);
+ rbit(v6, T16B, v6);
+ }
+ bind(done);
+
+ orr(Hprime, T16B, v6, v6); // Move H ** unrolls into Hprime
+
+ // Hprime contains (H ** 1, H ** 2, ... H ** unrolls)
+ // v0 contains the initial state. Clear the others.
+ for (int i = 1; i < unrolls; i++) {
+ int ofs = register_stride * i;
+ eor(ofs+v0, T16B, ofs+v0, ofs+v0); // zero each state register
+ }
+
+ ext(a1_xor_a0, T16B, Hprime, Hprime, 0x08); // long-swap subkeyH into a1_xor_a0
+ eor(a1_xor_a0, T16B, a1_xor_a0, Hprime); // xor subkeyH into subkeyL (Karatsuba: (A1+A0))
+
+ // Load #unrolls blocks of data
+ for (int ofs = 0; ofs < unrolls * register_stride; ofs += register_stride) {
+ ld1(v2+ofs, T16B, post(data, 0x10));
+ }
+
+ // Register assignments, replicated across 4 clones, v0 ... v23
+ //
+ // v0: input / output: current state, result of multiply/reduce
+ // v1: temp
+ // v2: input: one block of data (the ciphertext)
+ // also used as a temp once the data has been consumed
+ // v3: temp
+ // v4: output: high part of product
+ // v5: output: low part ...
+ // v6: unused
+ //
+ // Not replicated:
+ //
+ // v28: High part of H xor low part of H'
+ // v29: H' (hash subkey)
+ // v30: zero
+ // v31: Reduction polynomial of the Galois field
+
+ // Inner loop.
+ // Do the whole load/add/multiply/reduce over all our data except
+ // the last few rows.
+ {
+ Label L_ghash_loop;
+ bind(L_ghash_loop);
+
+ // Prefetching doesn't help here. In fact, on Neoverse N1 it's worse.
+ // prfm(Address(data, 128), PLDL1KEEP);
+
+ // Xor data into current state
+ for (int ofs = 0; ofs < unrolls * register_stride; ofs += register_stride) {
+ rbit((v2+ofs), T16B, (v2+ofs));
+ eor((v2+ofs), T16B, v0+ofs, (v2+ofs)); // bit-swapped data ^ bit-swapped state
+ }
+
+ // Generate fully-unrolled multiply-reduce in two stages.
+
+ (new GHASHMultiplyGenerator(this, unrolls,
+ /*result_lo*/v5, /*result_hi*/v4, /*data*/v2,
+ Hprime, a1_xor_a0, p, vzr,
+ /*temps*/v1, v3, /* reuse b*/v2))->unroll();
+
+ // NB: GHASHReduceGenerator also loads the next #unrolls blocks of
+ // data into v0, v0+ofs, the current state.
+ (new GHASHReduceGenerator (this, unrolls,
+ /*result*/v0, /*lo*/v5, /*hi*/v4, p, vzr,
+ /*data*/v2, /*temp*/v3))->unroll();
+
+ sub(blocks, blocks, unrolls);
+ cmp(blocks, (unsigned char)(unrolls * 2));
+ br(GE, L_ghash_loop);
+ }
+
+ // Merge the #unrolls states. Note that the data for the next
+ // iteration has already been loaded into v4, v4+ofs, etc...
+
+ // First, we multiply/reduce each clone by the appropriate power of H.
+ for (int i = 0; i < unrolls; i++) {
+ int ofs = register_stride * i;
+ ldrq(Hprime, Address(subkeyH, 16 * (unrolls - i - 1)));
+
+ rbit(v2+ofs, T16B, v2+ofs);
+ eor(v2+ofs, T16B, ofs+v0, v2+ofs); // bit-swapped data ^ bit-swapped state
+
+ rev64(Hprime, T16B, Hprime);
+ rbit(Hprime, T16B, Hprime);
+ ext(a1_xor_a0, T16B, Hprime, Hprime, 0x08); // long-swap subkeyH into a1_xor_a0
+ eor(a1_xor_a0, T16B, a1_xor_a0, Hprime); // xor subkeyH into subkeyL (Karatsuba: (A1+A0))
+ ghash_modmul(/*result*/v0+ofs, /*result_lo*/v5+ofs, /*result_hi*/v4+ofs, /*b*/v2+ofs,
+ Hprime, vzr, a1_xor_a0, p,
+ /*temps*/v1+ofs, v3+ofs, /* reuse b*/v2+ofs);
+ }
+
+ // Then we sum the results.
+ for (int i = 0; i < unrolls - 1; i++) {
+ int ofs = register_stride * i;
+ eor(v0, T16B, v0, v0 + register_stride + ofs);
+ }
+
+ sub(blocks, blocks, (unsigned char)unrolls);
+
+ // And finally bit-reverse the state back to big endian.
+ rev64(v0, T16B, v0);
+ rbit(v0, T16B, v0);
+ st1(v0, T16B, state);
+}
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/macroAssembler_aarch64.cpp openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/macroAssembler_aarch64.cpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/macroAssembler_aarch64.cpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/macroAssembler_aarch64.cpp 2022-01-13 21:56:25.000000000 +0000
@@ -40,16 +40,21 @@
#include "oops/accessDecorators.hpp"
#include "oops/compressedOops.inline.hpp"
#include "oops/klass.inline.hpp"
-#include "oops/oop.hpp"
-#include "opto/compile.hpp"
-#include "opto/intrinsicnode.hpp"
-#include "opto/node.hpp"
#include "runtime/biasedLocking.hpp"
#include "runtime/icache.hpp"
#include "runtime/interfaceSupport.inline.hpp"
#include "runtime/jniHandles.inline.hpp"
#include "runtime/sharedRuntime.hpp"
#include "runtime/thread.hpp"
+#ifdef COMPILER1
+#include "c1/c1_LIRAssembler.hpp"
+#endif
+#ifdef COMPILER2
+#include "oops/oop.hpp"
+#include "opto/compile.hpp"
+#include "opto/intrinsicnode.hpp"
+#include "opto/node.hpp"
+#endif
#ifdef PRODUCT
#define BLOCK_COMMENT(str) /* nothing */
@@ -65,8 +70,8 @@
// Return the total length (in bytes) of the instructions.
int MacroAssembler::pd_patch_instruction_size(address branch, address target) {
int instructions = 1;
- assert((uint64_t)target < (1ul << 48), "48-bit overflow in address constant");
- long offset = (target - branch) >> 2;
+ assert((uint64_t)target < (1ull << 48), "48-bit overflow in address constant");
+ intptr_t offset = (target - branch) >> 2;
unsigned insn = *(unsigned*)branch;
if ((Instruction_aarch64::extract(insn, 29, 24) & 0b111011) == 0b011000) {
// Load register (literal)
@@ -88,7 +93,7 @@
offset = target-branch;
int shift = Instruction_aarch64::extract(insn, 31, 31);
if (shift) {
- u_int64_t dest = (u_int64_t)target;
+ uint64_t dest = (uint64_t)target;
uint64_t pc_page = (uint64_t)branch >> 12;
uint64_t adr_page = (uint64_t)target >> 12;
unsigned offset_lo = dest & 0xfff;
@@ -129,9 +134,9 @@
Instruction_aarch64::extract(insn2, 4, 0)) {
// movk #imm16<<32
Instruction_aarch64::patch(branch + 4, 20, 5, (uint64_t)target >> 32);
- long dest = ((long)target & 0xffffffffL) | ((long)branch & 0xffff00000000L);
- long pc_page = (long)branch >> 12;
- long adr_page = (long)dest >> 12;
+ uintptr_t dest = ((uintptr_t)target & 0xffffffffULL) | ((uintptr_t)branch & 0xffff00000000ULL);
+ uintptr_t pc_page = (uintptr_t)branch >> 12;
+ uintptr_t adr_page = (uintptr_t)dest >> 12;
offset = adr_page - pc_page;
instructions = 2;
}
@@ -141,7 +146,7 @@
Instruction_aarch64::spatch(branch, 23, 5, offset);
Instruction_aarch64::patch(branch, 30, 29, offset_lo);
} else if (Instruction_aarch64::extract(insn, 31, 21) == 0b11010010100) {
- u_int64_t dest = (u_int64_t)target;
+ uint64_t dest = (uint64_t)target;
// Move wide constant
assert(nativeInstruction_at(branch+4)->is_movk(), "wrong insns in patch");
assert(nativeInstruction_at(branch+8)->is_movk(), "wrong insns in patch");
@@ -200,7 +205,7 @@
}
address MacroAssembler::target_addr_for_insn(address insn_addr, unsigned insn) {
- long offset = 0;
+ intptr_t offset = 0;
if ((Instruction_aarch64::extract(insn, 29, 24) & 0b011011) == 0b00011000) {
// Load register (literal)
offset = Instruction_aarch64::sextract(insn, 23, 5);
@@ -267,13 +272,13 @@
ShouldNotReachHere();
}
} else if (Instruction_aarch64::extract(insn, 31, 23) == 0b110100101) {
- u_int32_t *insns = (u_int32_t *)insn_addr;
+ uint32_t *insns = (uint32_t *)insn_addr;
// Move wide constant: movz, movk, movk. See movptr().
assert(nativeInstruction_at(insns+1)->is_movk(), "wrong insns in patch");
assert(nativeInstruction_at(insns+2)->is_movk(), "wrong insns in patch");
- return address(u_int64_t(Instruction_aarch64::extract(insns[0], 20, 5))
- + (u_int64_t(Instruction_aarch64::extract(insns[1], 20, 5)) << 16)
- + (u_int64_t(Instruction_aarch64::extract(insns[2], 20, 5)) << 32));
+ return address(uint64_t(Instruction_aarch64::extract(insns[0], 20, 5))
+ + (uint64_t(Instruction_aarch64::extract(insns[1], 20, 5)) << 16)
+ + (uint64_t(Instruction_aarch64::extract(insns[2], 20, 5)) << 32));
} else if (Instruction_aarch64::extract(insn, 31, 22) == 0b1011100101 &&
Instruction_aarch64::extract(insn, 4, 0) == 0b11111) {
return 0;
@@ -292,7 +297,7 @@
ldr(rscratch1, Address(rthread, Thread::polling_page_offset()));
tbnz(rscratch1, exact_log2(SafepointMechanism::poll_bit()), slow_path);
} else {
- unsigned long offset;
+ uint64_t offset;
adrp(rscratch1, ExternalAddress(SafepointSynchronize::address_of_state()), offset);
ldrw(rscratch1, Address(rscratch1, offset));
assert(SafepointSynchronize::_not_synchronized == 0, "rewrite this code");
@@ -400,7 +405,7 @@
assert(CodeCache::find_blob(entry.target()) != NULL,
"destination of far call not found in code cache");
if (far_branches()) {
- unsigned long offset;
+ uint64_t offset;
// We can use ADRP here because we know that the total size of
// the code cache cannot exceed 2Gb.
adrp(tmp, entry, offset);
@@ -418,7 +423,7 @@
assert(CodeCache::find_blob(entry.target()) != NULL,
"destination of far call not found in code cache");
if (far_branches()) {
- unsigned long offset;
+ uint64_t offset;
// We can use ADRP here because we know that the total size of
// the code cache cannot exceed 2Gb.
adrp(tmp, entry, offset);
@@ -695,6 +700,11 @@
// do the call, remove parameters
MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments, &l);
+ // lr could be poisoned with PAC signature during throw_pending_exception
+ // if it was tail-call optimized by compiler, since lr is not callee-saved
+ // reload it with proper value
+ adr(lr, l);
+
// reset last Java frame
// Only interpreter should have to clear fp
reset_last_Java_frame(true);
@@ -735,15 +745,19 @@
// We need a trampoline if branches are far.
if (far_branches()) {
+ bool in_scratch_emit_size = false;
+#ifdef COMPILER2
// We don't want to emit a trampoline if C2 is generating dummy
// code during its branch shortening phase.
CompileTask* task = ciEnv::current()->task();
- bool in_scratch_emit_size =
+ in_scratch_emit_size =
(task != NULL && is_c2_compile(task->comp_level()) &&
Compile::current()->in_scratch_emit_size());
+#endif
if (!in_scratch_emit_size) {
address stub = emit_trampoline_stub(offset(), entry.target());
if (stub == NULL) {
+ postcond(pc() == badAddress);
return NULL; // CodeCache is full
}
}
@@ -757,6 +771,7 @@
bl(pc());
}
// just need to return a non-null address
+ postcond(pc() != badAddress);
return pc();
}
@@ -774,7 +789,9 @@
address MacroAssembler::emit_trampoline_stub(int insts_call_instruction_offset,
address dest) {
- address stub = start_a_stub(Compile::MAX_stubs_size/2);
+ // Max stub size: alignment nop, TrampolineStub.
+ address stub = start_a_stub(NativeInstruction::instruction_size
+ + NativeCallTrampolineStub::instruction_size);
if (stub == NULL) {
return NULL; // CodeBuffer::expand failed
}
@@ -830,7 +847,7 @@
address MacroAssembler::ic_call(address entry, jint method_index) {
RelocationHolder rh = virtual_call_Relocation::spec(pc(), method_index);
// address const_ptr = long_constant((jlong)Universe::non_oop_word());
- // unsigned long offset;
+ // uintptr_t offset;
// ldr_constant(rscratch2, const_ptr);
movptr(rscratch2, (uintptr_t)Universe::non_oop_word());
return trampoline_call(Address(entry, rh));
@@ -1014,27 +1031,22 @@
// }
Label search, found_method;
- for (int peel = 1; peel >= 0; peel--) {
- ldr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset_in_bytes()));
- cmp(intf_klass, method_result);
-
- if (peel) {
- br(Assembler::EQ, found_method);
- } else {
- br(Assembler::NE, search);
- // (invert the test to fall through to found_method...)
- }
-
- if (!peel) break;
-
- bind(search);
-
- // Check that the previous entry is non-null. A null entry means that
- // the receiver class doesn't implement the interface, and wasn't the
- // same as when the caller was compiled.
- cbz(method_result, L_no_such_interface);
+ ldr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset_in_bytes()));
+ cmp(intf_klass, method_result);
+ br(Assembler::EQ, found_method);
+ bind(search);
+ // Check that the previous entry is non-null. A null entry means that
+ // the receiver class doesn't implement the interface, and wasn't the
+ // same as when the caller was compiled.
+ cbz(method_result, L_no_such_interface);
+ if (itableOffsetEntry::interface_offset_in_bytes() != 0) {
add(scan_temp, scan_temp, scan_step);
+ ldr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset_in_bytes()));
+ } else {
+ ldr(method_result, Address(pre(scan_temp, scan_step)));
}
+ cmp(intf_klass, method_result);
+ br(Assembler::NE, search);
bind(found_method);
@@ -1468,7 +1480,7 @@
void MacroAssembler::mov(Register r, Address dest) {
code_section()->relocate(pc(), dest.rspec());
- u_int64_t imm64 = (u_int64_t)dest.target();
+ uint64_t imm64 = (uint64_t)dest.target();
movptr(r, imm64);
}
@@ -1480,11 +1492,11 @@
#ifndef PRODUCT
{
char buffer[64];
- snprintf(buffer, sizeof(buffer), "0x%"PRIX64, imm64);
+ snprintf(buffer, sizeof(buffer), PTR64_FORMAT, imm64);
block_comment(buffer);
}
#endif
- assert(imm64 < (1ul << 48), "48-bit overflow in address constant");
+ assert(imm64 < (1ull << 48), "48-bit overflow in address constant");
movz(r, imm64 & 0xffff);
imm64 >>= 16;
movk(r, imm64 & 0xffff, 16);
@@ -1501,20 +1513,20 @@
// imm32 == hex abcdefgh T2S: Vd = abcdefghabcdefgh
// imm32 == hex abcdefgh T4S: Vd = abcdefghabcdefghabcdefghabcdefgh
// T1D/T2D: invalid
-void MacroAssembler::mov(FloatRegister Vd, SIMD_Arrangement T, u_int32_t imm32) {
+void MacroAssembler::mov(FloatRegister Vd, SIMD_Arrangement T, uint32_t imm32) {
assert(T != T1D && T != T2D, "invalid arrangement");
if (T == T8B || T == T16B) {
assert((imm32 & ~0xff) == 0, "extraneous bits in unsigned imm32 (T8B/T16B)");
movi(Vd, T, imm32 & 0xff, 0);
return;
}
- u_int32_t nimm32 = ~imm32;
+ uint32_t nimm32 = ~imm32;
if (T == T4H || T == T8H) {
assert((imm32 & ~0xffff) == 0, "extraneous bits in unsigned imm32 (T4H/T8H)");
imm32 &= 0xffff;
nimm32 &= 0xffff;
}
- u_int32_t x = imm32;
+ uint32_t x = imm32;
int movi_cnt = 0;
int movn_cnt = 0;
while (x) { if (x & 0xff) movi_cnt++; x >>= 8; }
@@ -1538,12 +1550,12 @@
}
}
-void MacroAssembler::mov_immediate64(Register dst, u_int64_t imm64)
+void MacroAssembler::mov_immediate64(Register dst, uint64_t imm64)
{
#ifndef PRODUCT
{
char buffer[64];
- snprintf(buffer, sizeof(buffer), "0x%"PRIX64, imm64);
+ snprintf(buffer, sizeof(buffer), PTR64_FORMAT, imm64);
block_comment(buffer);
}
#endif
@@ -1552,7 +1564,7 @@
} else {
// we can use a combination of MOVZ or MOVN with
// MOVK to build up the constant
- u_int64_t imm_h[4];
+ uint64_t imm_h[4];
int zero_count = 0;
int neg_count = 0;
int i;
@@ -1573,7 +1585,7 @@
} else if (zero_count == 3) {
for (i = 0; i < 4; i++) {
if (imm_h[i] != 0L) {
- movz(dst, (u_int32_t)imm_h[i], (i << 4));
+ movz(dst, (uint32_t)imm_h[i], (i << 4));
break;
}
}
@@ -1581,7 +1593,7 @@
// one MOVN will do
for (int i = 0; i < 4; i++) {
if (imm_h[i] != 0xffffL) {
- movn(dst, (u_int32_t)imm_h[i] ^ 0xffffL, (i << 4));
+ movn(dst, (uint32_t)imm_h[i] ^ 0xffffL, (i << 4));
break;
}
}
@@ -1589,74 +1601,74 @@
// one MOVZ and one MOVK will do
for (i = 0; i < 3; i++) {
if (imm_h[i] != 0L) {
- movz(dst, (u_int32_t)imm_h[i], (i << 4));
+ movz(dst, (uint32_t)imm_h[i], (i << 4));
i++;
break;
}
}
for (;i < 4; i++) {
if (imm_h[i] != 0L) {
- movk(dst, (u_int32_t)imm_h[i], (i << 4));
+ movk(dst, (uint32_t)imm_h[i], (i << 4));
}
}
} else if (neg_count == 2) {
// one MOVN and one MOVK will do
for (i = 0; i < 4; i++) {
if (imm_h[i] != 0xffffL) {
- movn(dst, (u_int32_t)imm_h[i] ^ 0xffffL, (i << 4));
+ movn(dst, (uint32_t)imm_h[i] ^ 0xffffL, (i << 4));
i++;
break;
}
}
for (;i < 4; i++) {
if (imm_h[i] != 0xffffL) {
- movk(dst, (u_int32_t)imm_h[i], (i << 4));
+ movk(dst, (uint32_t)imm_h[i], (i << 4));
}
}
} else if (zero_count == 1) {
// one MOVZ and two MOVKs will do
for (i = 0; i < 4; i++) {
if (imm_h[i] != 0L) {
- movz(dst, (u_int32_t)imm_h[i], (i << 4));
+ movz(dst, (uint32_t)imm_h[i], (i << 4));
i++;
break;
}
}
for (;i < 4; i++) {
if (imm_h[i] != 0x0L) {
- movk(dst, (u_int32_t)imm_h[i], (i << 4));
+ movk(dst, (uint32_t)imm_h[i], (i << 4));
}
}
} else if (neg_count == 1) {
// one MOVN and two MOVKs will do
for (i = 0; i < 4; i++) {
if (imm_h[i] != 0xffffL) {
- movn(dst, (u_int32_t)imm_h[i] ^ 0xffffL, (i << 4));
+ movn(dst, (uint32_t)imm_h[i] ^ 0xffffL, (i << 4));
i++;
break;
}
}
for (;i < 4; i++) {
if (imm_h[i] != 0xffffL) {
- movk(dst, (u_int32_t)imm_h[i], (i << 4));
+ movk(dst, (uint32_t)imm_h[i], (i << 4));
}
}
} else {
// use a MOVZ and 3 MOVKs (makes it easier to debug)
- movz(dst, (u_int32_t)imm_h[0], 0);
+ movz(dst, (uint32_t)imm_h[0], 0);
for (i = 1; i < 4; i++) {
- movk(dst, (u_int32_t)imm_h[i], (i << 4));
+ movk(dst, (uint32_t)imm_h[i], (i << 4));
}
}
}
}
-void MacroAssembler::mov_immediate32(Register dst, u_int32_t imm32)
+void MacroAssembler::mov_immediate32(Register dst, uint32_t imm32)
{
#ifndef PRODUCT
{
char buffer[64];
- snprintf(buffer, sizeof(buffer), "0x%"PRIX32, imm32);
+ snprintf(buffer, sizeof(buffer), PTR32_FORMAT, imm32);
block_comment(buffer);
}
#endif
@@ -1665,7 +1677,7 @@
} else {
// we can use MOVZ, MOVN or two calls to MOVK to build up the
// constant
- u_int32_t imm_h[2];
+ uint32_t imm_h[2];
imm_h[0] = imm32 & 0xffff;
imm_h[1] = ((imm32 >> 16) & 0xffff);
if (imm_h[0] == 0) {
@@ -1688,7 +1700,7 @@
// not actually be used: you must use the Address that is returned.
// It is up to you to ensure that the shift provided matches the size
// of your data.
-Address MacroAssembler::form_address(Register Rd, Register base, long byte_offset, int shift) {
+Address MacroAssembler::form_address(Register Rd, Register base, int64_t byte_offset, int shift) {
if (Address::offset_ok_for_immed(byte_offset, shift))
// It fits; no need for any heroics
return Address(base, byte_offset);
@@ -1703,9 +1715,9 @@
// See if we can do this with two 12-bit offsets
{
- unsigned long word_offset = byte_offset >> shift;
- unsigned long masked_offset = word_offset & 0xfff000;
- if (Address::offset_ok_for_immed(word_offset - masked_offset)
+ uint64_t word_offset = byte_offset >> shift;
+ uint64_t masked_offset = word_offset & 0xfff000;
+ if (Address::offset_ok_for_immed(word_offset - masked_offset, 0)
&& Assembler::operand_valid_for_add_sub_immediate(masked_offset << shift)) {
add(Rd, base, masked_offset << shift);
word_offset -= masked_offset;
@@ -1945,7 +1957,7 @@
if (value < (1 << 12)) { sub(reg, reg, value); return; }
/* else */ {
assert(reg != rscratch2, "invalid dst for register decrement");
- mov(rscratch2, (unsigned long)value);
+ mov(rscratch2, (uint64_t)value);
sub(reg, reg, rscratch2);
}
}
@@ -2458,6 +2470,8 @@
ATOMIC_XCHG(xchg, swp, ldxr, stxr, Assembler::xword)
ATOMIC_XCHG(xchgw, swp, ldxrw, stxrw, Assembler::word)
+ATOMIC_XCHG(xchgl, swpl, ldxr, stlxr, Assembler::xword)
+ATOMIC_XCHG(xchglw, swpl, ldxrw, stlxrw, Assembler::word)
ATOMIC_XCHG(xchgal, swpal, ldaxr, stlxr, Assembler::xword)
ATOMIC_XCHG(xchgalw, swpal, ldaxrw, stlxrw, Assembler::word)
@@ -2482,43 +2496,43 @@
#endif
if (os::message_box(msg, "Execution stopped, print registers?")) {
ttyLocker ttyl;
- tty->print_cr(" pc = 0x%016lx", pc);
+ tty->print_cr(" pc = 0x%016" PRIx64, pc);
#ifndef PRODUCT
tty->cr();
findpc(pc);
tty->cr();
#endif
- tty->print_cr(" r0 = 0x%016lx", regs[0]);
- tty->print_cr(" r1 = 0x%016lx", regs[1]);
- tty->print_cr(" r2 = 0x%016lx", regs[2]);
- tty->print_cr(" r3 = 0x%016lx", regs[3]);
- tty->print_cr(" r4 = 0x%016lx", regs[4]);
- tty->print_cr(" r5 = 0x%016lx", regs[5]);
- tty->print_cr(" r6 = 0x%016lx", regs[6]);
- tty->print_cr(" r7 = 0x%016lx", regs[7]);
- tty->print_cr(" r8 = 0x%016lx", regs[8]);
- tty->print_cr(" r9 = 0x%016lx", regs[9]);
- tty->print_cr("r10 = 0x%016lx", regs[10]);
- tty->print_cr("r11 = 0x%016lx", regs[11]);
- tty->print_cr("r12 = 0x%016lx", regs[12]);
- tty->print_cr("r13 = 0x%016lx", regs[13]);
- tty->print_cr("r14 = 0x%016lx", regs[14]);
- tty->print_cr("r15 = 0x%016lx", regs[15]);
- tty->print_cr("r16 = 0x%016lx", regs[16]);
- tty->print_cr("r17 = 0x%016lx", regs[17]);
- tty->print_cr("r18 = 0x%016lx", regs[18]);
- tty->print_cr("r19 = 0x%016lx", regs[19]);
- tty->print_cr("r20 = 0x%016lx", regs[20]);
- tty->print_cr("r21 = 0x%016lx", regs[21]);
- tty->print_cr("r22 = 0x%016lx", regs[22]);
- tty->print_cr("r23 = 0x%016lx", regs[23]);
- tty->print_cr("r24 = 0x%016lx", regs[24]);
- tty->print_cr("r25 = 0x%016lx", regs[25]);
- tty->print_cr("r26 = 0x%016lx", regs[26]);
- tty->print_cr("r27 = 0x%016lx", regs[27]);
- tty->print_cr("r28 = 0x%016lx", regs[28]);
- tty->print_cr("r30 = 0x%016lx", regs[30]);
- tty->print_cr("r31 = 0x%016lx", regs[31]);
+ tty->print_cr(" r0 = 0x%016" PRIx64, regs[0]);
+ tty->print_cr(" r1 = 0x%016" PRIx64, regs[1]);
+ tty->print_cr(" r2 = 0x%016" PRIx64, regs[2]);
+ tty->print_cr(" r3 = 0x%016" PRIx64, regs[3]);
+ tty->print_cr(" r4 = 0x%016" PRIx64, regs[4]);
+ tty->print_cr(" r5 = 0x%016" PRIx64, regs[5]);
+ tty->print_cr(" r6 = 0x%016" PRIx64, regs[6]);
+ tty->print_cr(" r7 = 0x%016" PRIx64, regs[7]);
+ tty->print_cr(" r8 = 0x%016" PRIx64, regs[8]);
+ tty->print_cr(" r9 = 0x%016" PRIx64, regs[9]);
+ tty->print_cr("r10 = 0x%016" PRIx64, regs[10]);
+ tty->print_cr("r11 = 0x%016" PRIx64, regs[11]);
+ tty->print_cr("r12 = 0x%016" PRIx64, regs[12]);
+ tty->print_cr("r13 = 0x%016" PRIx64, regs[13]);
+ tty->print_cr("r14 = 0x%016" PRIx64, regs[14]);
+ tty->print_cr("r15 = 0x%016" PRIx64, regs[15]);
+ tty->print_cr("r16 = 0x%016" PRIx64, regs[16]);
+ tty->print_cr("r17 = 0x%016" PRIx64, regs[17]);
+ tty->print_cr("r18 = 0x%016" PRIx64, regs[18]);
+ tty->print_cr("r19 = 0x%016" PRIx64, regs[19]);
+ tty->print_cr("r20 = 0x%016" PRIx64, regs[20]);
+ tty->print_cr("r21 = 0x%016" PRIx64, regs[21]);
+ tty->print_cr("r22 = 0x%016" PRIx64, regs[22]);
+ tty->print_cr("r23 = 0x%016" PRIx64, regs[23]);
+ tty->print_cr("r24 = 0x%016" PRIx64, regs[24]);
+ tty->print_cr("r25 = 0x%016" PRIx64, regs[25]);
+ tty->print_cr("r26 = 0x%016" PRIx64, regs[26]);
+ tty->print_cr("r27 = 0x%016" PRIx64, regs[27]);
+ tty->print_cr("r28 = 0x%016" PRIx64, regs[28]);
+ tty->print_cr("r30 = 0x%016" PRIx64, regs[30]);
+ tty->print_cr("r31 = 0x%016" PRIx64, regs[31]);
BREAKPOINT;
}
ThreadStateTransition::transition(thread, _thread_in_vm, saved_state);
@@ -2530,9 +2544,17 @@
}
}
+RegSet MacroAssembler::call_clobbered_registers() {
+ RegSet regs = RegSet::range(r0, r17) - RegSet::of(rscratch1, rscratch2);
+#ifndef R18_RESERVED
+ regs += r18_tls;
+#endif
+ return regs;
+}
+
void MacroAssembler::push_call_clobbered_registers() {
int step = 4 * wordSize;
- push(RegSet::range(r0, r18) - RegSet::of(rscratch1, rscratch2), sp);
+ push(call_clobbered_registers(), sp);
sub(sp, sp, step);
mov(rscratch1, -step);
// Push v0-v7, v16-v31.
@@ -2552,7 +2574,7 @@
as_FloatRegister(i+3), T1D, Address(post(sp, 4 * wordSize)));
}
- pop(RegSet::range(r0, r18) - RegSet::of(rscratch1, rscratch2), sp);
+ pop(call_clobbered_registers() - RegSet::of(rscratch1, rscratch2), sp);
}
void MacroAssembler::push_CPU_state(bool save_vectors) {
@@ -2624,19 +2646,19 @@
// Returns true if it is, else false.
bool MacroAssembler::merge_alignment_check(Register base,
size_t size,
- long cur_offset,
- long prev_offset) const {
+ int64_t cur_offset,
+ int64_t prev_offset) const {
if (AvoidUnalignedAccesses) {
if (base == sp) {
// Checks whether low offset if aligned to pair of registers.
- long pair_mask = size * 2 - 1;
- long offset = prev_offset > cur_offset ? cur_offset : prev_offset;
+ int64_t pair_mask = size * 2 - 1;
+ int64_t offset = prev_offset > cur_offset ? cur_offset : prev_offset;
return (offset & pair_mask) == 0;
} else { // If base is not sp, we can't guarantee the access is aligned.
return false;
}
} else {
- long mask = size - 1;
+ int64_t mask = size - 1;
// Load/store pair instruction only supports element size aligned offset.
return (cur_offset & mask) == 0 && (prev_offset & mask) == 0;
}
@@ -2669,8 +2691,8 @@
return false;
}
- long max_offset = 63 * prev_size_in_bytes;
- long min_offset = -64 * prev_size_in_bytes;
+ int64_t max_offset = 63 * prev_size_in_bytes;
+ int64_t min_offset = -64 * prev_size_in_bytes;
assert(prev_ldst->is_not_pre_post_index(), "pre-index or post-index is not supported to be merged.");
@@ -2679,8 +2701,8 @@
return false;
}
- long cur_offset = adr.offset();
- long prev_offset = prev_ldst->offset();
+ int64_t cur_offset = adr.offset();
+ int64_t prev_offset = prev_ldst->offset();
size_t diff = abs(cur_offset - prev_offset);
if (diff != prev_size_in_bytes) {
return false;
@@ -2697,7 +2719,7 @@
return false;
}
- long low_offset = prev_offset > cur_offset ? cur_offset : prev_offset;
+ int64_t low_offset = prev_offset > cur_offset ? cur_offset : prev_offset;
// Offset range must be in ldp/stp instruction's range.
if (low_offset > max_offset || low_offset < min_offset) {
return false;
@@ -2722,7 +2744,7 @@
address prev = pc() - NativeInstruction::instruction_size;
NativeLdSt* prev_ldst = NativeLdSt_at(prev);
- long offset;
+ int64_t offset;
if (adr.offset() < prev_ldst->offset()) {
offset = adr.offset();
@@ -3268,7 +3290,7 @@
Register table0, Register table1, Register table2, Register table3,
Register tmp, Register tmp2, Register tmp3) {
Label L_by16, L_by16_loop, L_by4, L_by4_loop, L_by1, L_by1_loop, L_exit;
- unsigned long offset;
+ uint64_t offset;
if (UseCRC32) {
kernel_crc32_using_crc32(crc, buf, len, table0, table1, table2, table3);
@@ -3570,7 +3592,7 @@
SkipIfEqual::SkipIfEqual(
MacroAssembler* masm, const bool* flag_addr, bool value) {
_masm = masm;
- unsigned long offset;
+ uint64_t offset;
_masm->adrp(rscratch1, ExternalAddress((address)flag_addr), offset);
_masm->ldrb(rscratch1, Address(rscratch1, offset));
_masm->cbzw(rscratch1, _label);
@@ -3599,7 +3621,7 @@
}
void MacroAssembler::cmpptr(Register src1, Address src2) {
- unsigned long offset;
+ uint64_t offset;
adrp(rscratch1, src2, offset);
ldr(rscratch1, Address(rscratch1, offset));
cmp(src1, rscratch1);
@@ -4185,7 +4207,7 @@
if (SafepointMechanism::uses_thread_local_poll()) {
ldr(dest, Address(rthread, Thread::polling_page_offset()));
} else {
- unsigned long off;
+ uint64_t off;
adrp(dest, Address(page, rtype), off);
assert(off == 0, "polling page must be page aligned");
}
@@ -4207,13 +4229,12 @@
return inst_mark();
}
-void MacroAssembler::adrp(Register reg1, const Address &dest, unsigned long &byte_offset) {
- relocInfo::relocType rtype = dest.rspec().reloc()->type();
- unsigned long low_page = (unsigned long)CodeCache::low_bound() >> 12;
- unsigned long high_page = (unsigned long)(CodeCache::high_bound()-1) >> 12;
- unsigned long dest_page = (unsigned long)dest.target() >> 12;
- long offset_low = dest_page - low_page;
- long offset_high = dest_page - high_page;
+void MacroAssembler::adrp(Register reg1, const Address &dest, uint64_t &byte_offset) {
+ uint64_t low_page = (uint64_t)CodeCache::low_bound() >> 12;
+ uint64_t high_page = (uint64_t)(CodeCache::high_bound()-1) >> 12;
+ uint64_t dest_page = (uint64_t)dest.target() >> 12;
+ int64_t offset_low = dest_page - low_page;
+ int64_t offset_high = dest_page - high_page;
assert(is_valid_AArch64_address(dest.target()), "bad address");
assert(dest.getMode() == Address::literal, "ADRP must be applied to a literal address");
@@ -4225,14 +4246,14 @@
if (offset_high >= -(1<<20) && offset_low < (1<<20)) {
_adrp(reg1, dest.target());
} else {
- unsigned long target = (unsigned long)dest.target();
- unsigned long adrp_target
- = (target & 0xffffffffUL) | ((unsigned long)pc() & 0xffff00000000UL);
+ uint64_t target = (uint64_t)dest.target();
+ uint64_t adrp_target
+ = (target & 0xffffffffULL) | ((uint64_t)pc() & 0xffff00000000ULL);
_adrp(reg1, (address)adrp_target);
movk(reg1, target >> 32, 32);
}
- byte_offset = (unsigned long)dest.target() & 0xfff;
+ byte_offset = (uint64_t)dest.target() & 0xfff;
}
void MacroAssembler::load_byte_map_base(Register reg) {
@@ -4278,6 +4299,7 @@
}
}
+#ifdef COMPILER2
typedef void (MacroAssembler::* chr_insn)(Register Rt, const Address &adr);
// Search for str1 in str2 and return index or -1
@@ -4783,7 +4805,7 @@
Register cnt1, Register cnt2, Register result, Register tmp1, Register tmp2,
FloatRegister vtmp1, FloatRegister vtmp2, FloatRegister vtmp3, int ae) {
Label DONE, SHORT_LOOP, SHORT_STRING, SHORT_LAST, TAIL, STUB,
- DIFFERENCE, NEXT_WORD, SHORT_LOOP_TAIL, SHORT_LAST2, SHORT_LAST_INIT,
+ DIFF, NEXT_WORD, SHORT_LOOP_TAIL, SHORT_LAST2, SHORT_LAST_INIT,
SHORT_LOOP_START, TAIL_CHECK;
const int STUB_THRESHOLD = 64 + 8;
@@ -4870,7 +4892,7 @@
adds(cnt2, cnt2, isUL ? 4 : 8);
br(GE, TAIL);
eor(rscratch2, tmp1, tmp2);
- cbnz(rscratch2, DIFFERENCE);
+ cbnz(rscratch2, DIFF);
// main loop
bind(NEXT_WORD);
if (str1_isL == str2_isL) {
@@ -4896,10 +4918,10 @@
eor(rscratch2, tmp1, tmp2);
cbz(rscratch2, NEXT_WORD);
- b(DIFFERENCE);
+ b(DIFF);
bind(TAIL);
eor(rscratch2, tmp1, tmp2);
- cbnz(rscratch2, DIFFERENCE);
+ cbnz(rscratch2, DIFF);
// Last longword. In the case where length == 4 we compare the
// same longword twice, but that's still faster than another
// conditional branch.
@@ -4923,7 +4945,7 @@
// Find the first different characters in the longwords and
// compute their difference.
- bind(DIFFERENCE);
+ bind(DIFF);
rev(rscratch2, rscratch2);
clz(rscratch2, rscratch2);
andr(rscratch2, rscratch2, isLL ? -8 : -16);
@@ -5003,9 +5025,10 @@
BLOCK_COMMENT("} string_compare");
}
+#endif // COMPILER2
// This method checks if provided byte array contains byte with highest bit set.
-void MacroAssembler::has_negatives(Register ary1, Register len, Register result) {
+address MacroAssembler::has_negatives(Register ary1, Register len, Register result) {
// Simple and most common case of aligned small array which is not at the
// end of memory page is placed here. All other cases are in stub.
Label LOOP, END, STUB, STUB_LONG, SET_RESULT, DONE;
@@ -5042,27 +5065,38 @@
b(SET_RESULT);
BIND(STUB);
- RuntimeAddress has_neg = RuntimeAddress(StubRoutines::aarch64::has_negatives());
+ RuntimeAddress has_neg = RuntimeAddress(StubRoutines::aarch64::has_negatives());
assert(has_neg.target() != NULL, "has_negatives stub has not been generated");
- trampoline_call(has_neg);
+ address tpc1 = trampoline_call(has_neg);
+ if (tpc1 == NULL) {
+ DEBUG_ONLY(reset_labels3(STUB_LONG, SET_RESULT, DONE));
+ postcond(pc() == badAddress);
+ return NULL;
+ }
b(DONE);
BIND(STUB_LONG);
- RuntimeAddress has_neg_long = RuntimeAddress(
- StubRoutines::aarch64::has_negatives_long());
+ RuntimeAddress has_neg_long = RuntimeAddress(StubRoutines::aarch64::has_negatives_long());
assert(has_neg_long.target() != NULL, "has_negatives stub has not been generated");
- trampoline_call(has_neg_long);
+ address tpc2 = trampoline_call(has_neg_long);
+ if (tpc2 == NULL) {
+ DEBUG_ONLY(reset_labels2(SET_RESULT, DONE));
+ postcond(pc() == badAddress);
+ return NULL;
+ }
b(DONE);
BIND(SET_RESULT);
cset(result, NE); // set true or false
BIND(DONE);
+ postcond(pc() != badAddress);
+ return pc();
}
-void MacroAssembler::arrays_equals(Register a1, Register a2, Register tmp3,
- Register tmp4, Register tmp5, Register result,
- Register cnt1, int elem_size) {
+address MacroAssembler::arrays_equals(Register a1, Register a2, Register tmp3,
+ Register tmp4, Register tmp5, Register result,
+ Register cnt1, int elem_size) {
Label DONE, SAME;
Register tmp1 = rscratch1;
Register tmp2 = rscratch2;
@@ -5166,7 +5200,7 @@
}
}
} else {
- Label NEXT_DWORD, SHORT, TAIL, TAIL2, STUB, EARLY_OUT,
+ Label NEXT_DWORD, SHORT, TAIL, TAIL2, STUB,
CSET_EQ, LAST_CHECK;
mov(result, false);
cbz(a1, DONE);
@@ -5225,10 +5259,14 @@
cbnz(tmp5, DONE);
RuntimeAddress stub = RuntimeAddress(StubRoutines::aarch64::large_array_equals());
assert(stub.target() != NULL, "array_equals_long stub has not been generated");
- trampoline_call(stub);
+ address tpc = trampoline_call(stub);
+ if (tpc == NULL) {
+ DEBUG_ONLY(reset_labels5(SHORT, LAST_CHECK, CSET_EQ, SAME, DONE));
+ postcond(pc() == badAddress);
+ return NULL;
+ }
b(DONE);
- bind(EARLY_OUT);
// (a1 != null && a2 == null) || (a1 != null && a2 != null && a1 == a2)
// so, if a2 == null => return false(0), else return true, so we can return a2
mov(result, a2);
@@ -5255,6 +5293,8 @@
bind(DONE);
BLOCK_COMMENT("} array_equals");
+ postcond(pc() != badAddress);
+ return pc();
}
// Compare Strings
@@ -5362,7 +5402,7 @@
// cnt: Count in HeapWords.
//
// ptr, cnt, rscratch1, and rscratch2 are clobbered.
-void MacroAssembler::zero_words(Register ptr, Register cnt)
+address MacroAssembler::zero_words(Register ptr, Register cnt)
{
assert(is_power_of_2(zero_words_block_size), "adjust this");
assert(ptr == r10 && cnt == r11, "mismatch in register usage");
@@ -5372,10 +5412,15 @@
Label around, done, done16;
br(LO, around);
{
- RuntimeAddress zero_blocks = RuntimeAddress(StubRoutines::aarch64::zero_blocks());
+ RuntimeAddress zero_blocks = RuntimeAddress(StubRoutines::aarch64::zero_blocks());
assert(zero_blocks.target() != NULL, "zero_blocks stub has not been generated");
if (StubRoutines::aarch64::complete()) {
- trampoline_call(zero_blocks);
+ address tpc = trampoline_call(zero_blocks);
+ if (tpc == NULL) {
+ DEBUG_ONLY(reset_labels1(around));
+ postcond(pc() == badAddress);
+ return NULL;
+ }
} else {
bl(zero_blocks);
}
@@ -5396,26 +5441,29 @@
bind(l);
}
BLOCK_COMMENT("} zero_words");
+ postcond(pc() != badAddress);
+ return pc();
}
// base: Address of a buffer to be zeroed, 8 bytes aligned.
// cnt: Immediate count in HeapWords.
#define SmallArraySize (18 * BytesPerLong)
-void MacroAssembler::zero_words(Register base, u_int64_t cnt)
+void MacroAssembler::zero_words(Register base, uint64_t cnt)
{
BLOCK_COMMENT("zero_words {");
int i = cnt & 1; // store any odd word to start
if (i) str(zr, Address(base));
if (cnt <= SmallArraySize / BytesPerLong) {
- for (; i < (int)cnt; i += 2)
+ for (; i < (int)cnt; i += 2) {
stp(zr, zr, Address(base, i * wordSize));
+ }
} else {
const int unroll = 4; // Number of stp(zr, zr) instructions we'll unroll
int remainder = cnt % (2 * unroll);
- for (; i < remainder; i += 2)
+ for (; i < remainder; i += 2) {
stp(zr, zr, Address(base, i * wordSize));
-
+ }
Label loop;
Register cnt_reg = rscratch1;
Register loop_base = rscratch2;
@@ -5425,8 +5473,9 @@
add(loop_base, base, (remainder - 2) * wordSize);
bind(loop);
sub(cnt_reg, cnt_reg, 2 * unroll);
- for (i = 1; i < unroll; i++)
+ for (i = 1; i < unroll; i++) {
stp(zr, zr, Address(loop_base, 2 * i * wordSize));
+ }
stp(zr, zr, Address(pre(loop_base, 2 * unroll * wordSize)));
cbnz(cnt_reg, loop);
}
@@ -5642,9 +5691,9 @@
// Inflate byte[] array to char[].
-void MacroAssembler::byte_array_inflate(Register src, Register dst, Register len,
- FloatRegister vtmp1, FloatRegister vtmp2, FloatRegister vtmp3,
- Register tmp4) {
+address MacroAssembler::byte_array_inflate(Register src, Register dst, Register len,
+ FloatRegister vtmp1, FloatRegister vtmp2,
+ FloatRegister vtmp3, Register tmp4) {
Label big, done, after_init, to_stub;
assert_different_registers(src, dst, len, tmp4, rscratch1);
@@ -5681,9 +5730,14 @@
if (SoftwarePrefetchHintDistance >= 0) {
bind(to_stub);
- RuntimeAddress stub = RuntimeAddress(StubRoutines::aarch64::large_byte_array_inflate());
+ RuntimeAddress stub = RuntimeAddress(StubRoutines::aarch64::large_byte_array_inflate());
assert(stub.target() != NULL, "large_byte_array_inflate stub has not been generated");
- trampoline_call(stub);
+ address tpc = trampoline_call(stub);
+ if (tpc == NULL) {
+ DEBUG_ONLY(reset_labels2(big, done));
+ postcond(pc() == badAddress);
+ return NULL;
+ }
b(after_init);
}
@@ -5737,6 +5791,8 @@
strq(vtmp3, Address(dst, -16));
bind(done);
+ postcond(pc() != badAddress);
+ return pc();
}
// Compress char[] array to byte[].
@@ -5755,10 +5811,14 @@
// by the call to JavaThread::aarch64_get_thread_helper() or, indeed,
// the call setup code.
//
-// aarch64_get_thread_helper() clobbers only r0, r1, and flags.
+// On Linux, aarch64_get_thread_helper() clobbers only r0, r1, and flags.
+// On other systems, the helper is a usual C function.
//
void MacroAssembler::get_thread(Register dst) {
- RegSet saved_regs = RegSet::range(r0, r1) + lr - dst;
+ RegSet saved_regs =
+ LINUX_ONLY(RegSet::range(r0, r1) + lr - dst)
+ NOT_LINUX (RegSet::range(r0, r17) + lr - dst);
+
push(saved_regs, sp);
mov(lr, CAST_FROM_FN_PTR(address, JavaThread::aarch64_get_thread_helper));
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/macroAssembler_aarch64.hpp openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/macroAssembler_aarch64.hpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/macroAssembler_aarch64.hpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/macroAssembler_aarch64.hpp 2022-01-13 21:56:25.000000000 +0000
@@ -185,7 +185,15 @@
mov(rscratch2, call_site);
}
+// Microsoft's MSVC team thinks that the __FUNCSIG__ is approximately (sympathy for calling conventions) equivalent to __PRETTY_FUNCTION__
+// Also, from Clang patch: "It is very similar to GCC's PRETTY_FUNCTION, except it prints the calling convention."
+// https://reviews.llvm.org/D3311
+
+#ifdef _WIN64
+#define call_Unimplemented() _call_Unimplemented((address)__FUNCSIG__)
+#else
#define call_Unimplemented() _call_Unimplemented((address)__PRETTY_FUNCTION__)
+#endif
// aliases defined in AARCH64 spec
@@ -448,8 +456,8 @@
// first two private routines for loading 32 bit or 64 bit constants
private:
- void mov_immediate64(Register dst, u_int64_t imm64);
- void mov_immediate32(Register dst, u_int32_t imm32);
+ void mov_immediate64(Register dst, uint64_t imm64);
+ void mov_immediate32(Register dst, uint32_t imm32);
int push(unsigned int bitset, Register stack);
int pop(unsigned int bitset, Register stack);
@@ -460,6 +468,8 @@
void push(RegSet regs, Register stack) { if (regs.bits()) push(regs.bits(), stack); }
void pop(RegSet regs, Register stack) { if (regs.bits()) pop(regs.bits(), stack); }
+ static RegSet call_clobbered_registers();
+
// Push and pop everything that might be clobbered by a native
// runtime call except rscratch1 and rscratch2. (They are always
// scratch, so we don't have to protect them.) Only save the lower
@@ -470,31 +480,20 @@
// now mov instructions for loading absolute addresses and 32 or
// 64 bit integers
- inline void mov(Register dst, address addr)
- {
- mov_immediate64(dst, (u_int64_t)addr);
- }
+ inline void mov(Register dst, address addr) { mov_immediate64(dst, (uint64_t)addr); }
- inline void mov(Register dst, u_int64_t imm64)
- {
- mov_immediate64(dst, imm64);
- }
+ inline void mov(Register dst, int imm64) { mov_immediate64(dst, (uint64_t)imm64); }
+ inline void mov(Register dst, long imm64) { mov_immediate64(dst, (uint64_t)imm64); }
+ inline void mov(Register dst, long long imm64) { mov_immediate64(dst, (uint64_t)imm64); }
+ inline void mov(Register dst, unsigned int imm64) { mov_immediate64(dst, (uint64_t)imm64); }
+ inline void mov(Register dst, unsigned long imm64) { mov_immediate64(dst, (uint64_t)imm64); }
+ inline void mov(Register dst, unsigned long long imm64) { mov_immediate64(dst, (uint64_t)imm64); }
- inline void movw(Register dst, u_int32_t imm32)
+ inline void movw(Register dst, uint32_t imm32)
{
mov_immediate32(dst, imm32);
}
- inline void mov(Register dst, long l)
- {
- mov(dst, (u_int64_t)l);
- }
-
- inline void mov(Register dst, int i)
- {
- mov(dst, (long)i);
- }
-
void mov(Register dst, RegisterOrConstant src) {
if (src.is_register())
mov(dst, src.as_register());
@@ -504,7 +503,7 @@
void movptr(Register r, uintptr_t imm64);
- void mov(FloatRegister Vd, SIMD_Arrangement T, u_int32_t imm32);
+ void mov(FloatRegister Vd, SIMD_Arrangement T, uint32_t imm32);
void mov(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) {
orr(Vd, T, Vn, Vn);
@@ -514,10 +513,10 @@
// Generalized Test Bit And Branch, including a "far" variety which
// spans more than 32KiB.
- void tbr(Condition cond, Register Rt, int bitpos, Label &dest, bool far = false) {
+ void tbr(Condition cond, Register Rt, int bitpos, Label &dest, bool isfar = false) {
assert(cond == EQ || cond == NE, "must be");
- if (far)
+ if (isfar)
cond = ~cond;
void (Assembler::* branch)(Register Rt, int bitpos, Label &L);
@@ -526,7 +525,7 @@
else
branch = &Assembler::tbnz;
- if (far) {
+ if (isfar) {
Label L;
(this->*branch)(Rt, bitpos, L);
b(dest);
@@ -1009,6 +1008,8 @@
void atomic_xchg(Register prev, Register newv, Register addr);
void atomic_xchgw(Register prev, Register newv, Register addr);
+ void atomic_xchgl(Register prev, Register newv, Register addr);
+ void atomic_xchglw(Register prev, Register newv, Register addr);
void atomic_xchgal(Register prev, Register newv, Register addr);
void atomic_xchgalw(Register prev, Register newv, Register addr);
@@ -1030,6 +1031,16 @@
private:
void compare_eq(Register rn, Register rm, enum operand_size size);
+#ifdef ASSERT
+ // Macro short-hand support to clean-up after a failed call to trampoline
+ // call generation (see trampoline_call() below), when a set of Labels must
+ // be reset (before returning).
+#define reset_labels1(L1) L1.reset()
+#define reset_labels2(L1, L2) L1.reset(); L2.reset()
+#define reset_labels3(L1, L2, L3) L1.reset(); reset_labels2(L2, L3)
+#define reset_labels5(L1, L2, L3, L4, L5) reset_labels2(L1, L2); reset_labels3(L3, L4, L5)
+#endif
+
public:
// Calls
@@ -1148,7 +1159,7 @@
void sub(Register Rd, Register Rn, RegisterOrConstant decrement);
void subw(Register Rd, Register Rn, RegisterOrConstant decrement);
- void adrp(Register reg1, const Address &dest, unsigned long &byte_offset);
+ void adrp(Register reg1, const Address &dest, uint64_t &byte_offset);
void tableswitch(Register index, jint lowbound, jint highbound,
Label &jumptable, Label &jumptable_end, int stride = 1) {
@@ -1165,7 +1176,7 @@
// actually be used: you must use the Address that is returned. It
// is up to you to ensure that the shift provided matches the size
// of your data.
- Address form_address(Register Rd, Register base, long byte_offset, int shift);
+ Address form_address(Register Rd, Register base, int64_t byte_offset, int shift);
// Return true iff an address is within the 48-bit AArch64 address
// space.
@@ -1190,7 +1201,7 @@
if (NearCpool) {
ldr(dest, const_addr);
} else {
- unsigned long offset;
+ uint64_t offset;
adrp(dest, InternalAddress(const_addr.target()), offset);
ldr(dest, Address(dest, offset));
}
@@ -1211,24 +1222,24 @@
Register tmp1, Register tmp2, FloatRegister vtmp1,
FloatRegister vtmp2, FloatRegister vtmp3, int ae);
- void has_negatives(Register ary1, Register len, Register result);
+ address has_negatives(Register ary1, Register len, Register result);
- void arrays_equals(Register a1, Register a2, Register result, Register cnt1,
- Register tmp1, Register tmp2, Register tmp3, int elem_size);
+ address arrays_equals(Register a1, Register a2, Register result, Register cnt1,
+ Register tmp1, Register tmp2, Register tmp3, int elem_size);
void string_equals(Register a1, Register a2, Register result, Register cnt1,
int elem_size);
void fill_words(Register base, Register cnt, Register value);
- void zero_words(Register base, u_int64_t cnt);
- void zero_words(Register ptr, Register cnt);
+ void zero_words(Register base, uint64_t cnt);
+ address zero_words(Register ptr, Register cnt);
void zero_dcache_blocks(Register base, Register cnt);
static const int zero_words_block_size;
- void byte_array_inflate(Register src, Register dst, Register len,
- FloatRegister vtmp1, FloatRegister vtmp2,
- FloatRegister vtmp3, Register tmp4);
+ address byte_array_inflate(Register src, Register dst, Register len,
+ FloatRegister vtmp1, FloatRegister vtmp2,
+ FloatRegister vtmp3, Register tmp4);
void char_array_compress(Register src, Register dst, Register len,
FloatRegister tmp1Reg, FloatRegister tmp2Reg,
@@ -1288,6 +1299,24 @@
Register zlen, Register tmp1, Register tmp2, Register tmp3,
Register tmp4, Register tmp5, Register tmp6, Register tmp7);
void mul_add(Register out, Register in, Register offs, Register len, Register k);
+ void ghash_multiply(FloatRegister result_lo, FloatRegister result_hi,
+ FloatRegister a, FloatRegister b, FloatRegister a1_xor_a0,
+ FloatRegister tmp1, FloatRegister tmp2, FloatRegister tmp3);
+ void ghash_reduce(FloatRegister result, FloatRegister lo, FloatRegister hi,
+ FloatRegister p, FloatRegister z, FloatRegister t1);
+ void ghash_processBlocks_wide(address p, Register state, Register subkeyH,
+ Register data, Register blocks, int unrolls);
+ void ghash_modmul (FloatRegister result,
+ FloatRegister result_lo, FloatRegister result_hi, FloatRegister b,
+ FloatRegister a, FloatRegister vzr, FloatRegister a1_xor_a0, FloatRegister p,
+ FloatRegister t1, FloatRegister t2, FloatRegister t3);
+
+ void aesenc_loadkeys(Register key, Register keylen);
+ void aesecb_encrypt(Register from, Register to, Register keylen,
+ FloatRegister data = v0, int unrolls = 1);
+ void aesecb_decrypt(Register from, Register to, Register key, Register keylen);
+ void aes_round(FloatRegister input, FloatRegister subkey);
+
// ISB may be needed because of a safepoint
void maybe_isb() { isb(); }
@@ -1302,7 +1331,7 @@
// Uses rscratch2 if the address is not directly reachable
Address spill_address(int size, int offset, Register tmp=rscratch2);
- bool merge_alignment_check(Register base, size_t size, long cur_offset, long prev_offset) const;
+ bool merge_alignment_check(Register base, size_t size, int64_t cur_offset, int64_t prev_offset) const;
// Check whether two loads/stores can be merged into ldp/stp.
bool ldst_can_merge(Register rx, const Address &adr, size_t cur_size_in_bytes, bool is_store) const;
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/macroAssembler_aarch64_log.cpp openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/macroAssembler_aarch64_log.cpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/macroAssembler_aarch64_log.cpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/macroAssembler_aarch64_log.cpp 2022-01-13 21:56:25.000000000 +0000
@@ -65,7 +65,7 @@
// Table with p(r) polynomial coefficients
// and table representation of logarithm values (hi and low parts)
-__attribute__ ((aligned(64))) juint _L_tbl[] =
+ATTRIBUTE_ALIGNED(64) juint _L_tbl[] =
{
// coefficients of p(r) polynomial:
// _coeff[]
@@ -260,9 +260,9 @@
Register tmp4, Register tmp5) {
Label DONE, CHECK_CORNER_CASES, SMALL_VALUE, MAIN,
CHECKED_CORNER_CASES, RETURN_MINF_OR_NAN;
- const long INF_OR_NAN_PREFIX = 0x7FF0;
- const long MINF_OR_MNAN_PREFIX = 0xFFF0;
- const long ONE_PREFIX = 0x3FF0;
+ const int64_t INF_OR_NAN_PREFIX = 0x7FF0;
+ const int64_t MINF_OR_MNAN_PREFIX = 0xFFF0;
+ const int64_t ONE_PREFIX = 0x3FF0;
movz(tmp2, ONE_PREFIX, 48);
movz(tmp4, 0x0010, 48);
fmovd(rscratch1, v0); // rscratch1 = AS_LONG_BITS(X)
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/macroAssembler_aarch64_trig.cpp openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/macroAssembler_aarch64_trig.cpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/macroAssembler_aarch64_trig.cpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/macroAssembler_aarch64_trig.cpp 2022-01-13 21:56:25.000000000 +0000
@@ -201,9 +201,9 @@
// NOTE: fpu registers are actively reused. See comments in code about their usage
void MacroAssembler::generate__ieee754_rem_pio2(address npio2_hw,
address two_over_pi, address pio2) {
- const long PIO2_1t = 0x3DD0B4611A626331UL;
- const long PIO2_2 = 0x3DD0B4611A600000UL;
- const long PIO2_2t = 0x3BA3198A2E037073UL;
+ const int64_t PIO2_1t = 0x3DD0B4611A626331ULL;
+ const int64_t PIO2_2 = 0x3DD0B4611A600000ULL;
+ const int64_t PIO2_2t = 0x3BA3198A2E037073ULL;
Label X_IS_NEGATIVE, X_IS_MEDIUM_OR_LARGE, X_IS_POSITIVE_LONG_PI, LARGE_ELSE,
REDUCTION_DONE, X_IS_MEDIUM_BRANCH_DONE, X_IS_LARGE, NX_SET,
X_IS_NEGATIVE_LONG_PI;
@@ -360,7 +360,7 @@
lsr(rscratch1, ix, 20); // ix >> 20
movz(tmp5, 0x4170, 48);
subw(rscratch1, rscratch1, 1046); // e0
- fmovd(v10, tmp5); // init two24A value
+ fmovd(v24, tmp5); // init two24A value
subw(jv, ix, rscratch1, LSL, 20); // ix - (e0<<20)
lsl(jv, jv, 32);
subw(rscratch2, rscratch1, 3);
@@ -374,7 +374,7 @@
sdivw(jv, rscratch2, i); // jv = (e0 - 3)/24
fsubd(v26, v26, v6);
sub(sp, sp, 560);
- fmuld(v26, v26, v10);
+ fmuld(v26, v26, v24);
frintzd(v7, v26); // v7 = (double)((int)v26)
movw(jx, 2); // calculate jx as nx - 1, which is initially 2. Not a part of unrolled loop
fsubd(v26, v26, v7);
@@ -383,7 +383,7 @@
block_comment("nx calculation with unrolled while(tx[nx-1]==zeroA) nx--;"); {
fcmpd(v26, 0.0); // if NE then jx == 2. else it's 1 or 0
add(iqBase, sp, 480); // base of iq[]
- fmuld(v3, v26, v10);
+ fmuld(v3, v26, v24);
br(NE, NX_SET);
fcmpd(v7, 0.0); // v7 == 0 => jx = 0. Else jx = 1
csetw(jx, NE);
@@ -689,7 +689,7 @@
RECOMP_FOR1_CHECK;
Register tmp2 = r1, n = r2, jv = r4, tmp5 = r5, jx = r6,
tmp3 = r7, iqBase = r10, ih = r11, tmp4 = r12, tmp1 = r13,
- jz = r14, j = r15, twoOverPiBase = r16, i = r17, qBase = r18;
+ jz = r14, j = r15, twoOverPiBase = r16, i = r17, qBase = r19;
// jp = jk == init_jk[prec] = init_jk[2] == {2,3,4,6}[2] == 4
// jx = nx - 1
lea(twoOverPiBase, ExternalAddress(two_over_pi));
@@ -839,7 +839,7 @@
ldrd(v27, post(tmp2, -8));
fmuld(v29, v17, v18); // twon24*z
frintzd(v29, v29); // (double)(int)
- fmsubd(v28, v10, v29, v18); // v28 = z-two24A*fw
+ fmsubd(v28, v24, v29, v18); // v28 = z-two24A*fw
fcvtzdw(tmp1, v28); // (int)(z-two24A*fw)
strw(tmp1, Address(iqBase, i, Address::lsl(2)));
faddd(v18, v27, v29);
@@ -1000,11 +1000,11 @@
block_comment("else block of if(z==0.0) {"); {
bind(RECOMP_CHECK_DONE_NOT_ZERO);
fmuld(v18, v18, v22);
- fcmpd(v18, v10); // v10 is stil two24A
+ fcmpd(v18, v24); // v24 is stil two24A
br(LT, Z_IS_LESS_THAN_TWO24B);
fmuld(v1, v18, v17); // twon24*z
frintzd(v1, v1); // v1 = (double)(int)(v1)
- fmaddd(v2, v10, v1, v18);
+ fmaddd(v2, v24, v1, v18);
fcvtzdw(tmp3, v1); // (int)fw
fcvtzdw(tmp2, v2); // double to int
strw(tmp2, Address(iqBase, jz, Address::lsl(2)));
@@ -1421,6 +1421,12 @@
Label DONE, ARG_REDUCTION, TINY_X, RETURN_SIN, EARLY_CASE;
Register X = r0, absX = r1, n = r2, ix = r3;
FloatRegister y0 = v4, y1 = v5;
+
+ enter();
+ // r19 is used in TemplateInterpreterGenerator::generate_math_entry
+ RegSet saved_regs = RegSet::of(r19);
+ push (saved_regs, sp);
+
block_comment("check |x| ~< pi/4, NaN, Inf and |x| < 2**-27 cases"); {
fmovd(X, v0);
mov(rscratch2, 0x3e400000);
@@ -1438,14 +1444,14 @@
// Set last bit unconditionally to make it NaN
orr(r10, r10, 1);
fmovd(v0, r10);
- ret(lr);
+ b(DONE);
}
block_comment("kernel_sin/kernel_cos: if(ix<0x3e400000) {}"); {
bind(TINY_X);
if (isCos) {
fmovd(v0, 1.0);
}
- ret(lr);
+ b(DONE);
}
bind(ARG_REDUCTION); /* argument reduction needed */
block_comment("n = __ieee754_rem_pio2(x,y);"); {
@@ -1465,7 +1471,7 @@
tbz(n, 1, DONE);
}
fnegd(v0, v0);
- ret(lr);
+ b(DONE);
bind(RETURN_SIN);
generate_kernel_sin(y0, true, dsin_coef);
if (isCos) {
@@ -1474,7 +1480,7 @@
tbz(n, 1, DONE);
}
fnegd(v0, v0);
- ret(lr);
+ b(DONE);
}
bind(EARLY_CASE);
eor(y1, T8B, y1, y1);
@@ -1484,5 +1490,7 @@
generate_kernel_sin(v0, false, dsin_coef);
}
bind(DONE);
+ pop(saved_regs, sp);
+ leave();
ret(lr);
}
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/nativeInst_aarch64.cpp openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/nativeInst_aarch64.cpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/nativeInst_aarch64.cpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/nativeInst_aarch64.cpp 2022-01-13 21:56:25.000000000 +0000
@@ -1,6 +1,6 @@
/*
- * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved.
- * Copyright (c) 2014, 2018, Red Hat Inc. All rights reserved.
+ * Copyright (c) 1997, 2020, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@@ -301,7 +301,7 @@
unsigned insn = *(unsigned*)pc;
if (maybe_cpool_ref(pc)) {
address addr = MacroAssembler::target_addr_for_insn(pc);
- *(long*)addr = x;
+ *(int64_t*)addr = x;
} else {
MacroAssembler::pd_patch_instruction(pc, (address)intptr_t(x));
ICache::invalidate_range(instruction_address(), instruction_size);
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/pauth_aarch64.hpp openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/pauth_aarch64.hpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/pauth_aarch64.hpp 1970-01-01 00:00:00.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/pauth_aarch64.hpp 2022-01-13 21:56:25.000000000 +0000
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2021, Arm Limited. All rights reserved.
+ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+ *
+ * This code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 only, as
+ * published by the Free Software Foundation.
+ *
+ * This code is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * version 2 for more details (a copy is included in the LICENSE file that
+ * accompanied this code).
+ *
+ * You should have received a copy of the GNU General Public License version
+ * 2 along with this work; if not, write to the Free Software Foundation,
+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
+ * or visit www.oracle.com if you need additional information or have any
+ * questions.
+ *
+ */
+
+#ifndef CPU_AARCH64_PAUTH_AARCH64_INLINE_HPP
+#define CPU_AARCH64_PAUTH_AARCH64_INLINE_HPP
+
+#include OS_CPU_HEADER_INLINE(pauth)
+
+inline bool pauth_ptr_is_raw(address ptr) {
+ // Confirm none of the high bits are set in the pointer.
+ return ptr == pauth_strip_pointer(ptr);
+}
+
+#endif // CPU_AARCH64_PAUTH_AARCH64_INLINE_HPP
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/register_aarch64.cpp openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/register_aarch64.cpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/register_aarch64.cpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/register_aarch64.cpp 2022-01-13 21:56:25.000000000 +0000
@@ -26,17 +26,19 @@
#include "precompiled.hpp"
#include "register_aarch64.hpp"
-const int ConcreteRegisterImpl::max_gpr = RegisterImpl::number_of_registers << 1;
+const int ConcreteRegisterImpl::max_gpr = RegisterImpl::number_of_registers *
+ RegisterImpl::max_slots_per_register;
const int ConcreteRegisterImpl::max_fpr
- = ConcreteRegisterImpl::max_gpr + (FloatRegisterImpl::number_of_registers << 1);
+ = ConcreteRegisterImpl::max_gpr +
+ FloatRegisterImpl::number_of_registers * FloatRegisterImpl::max_slots_per_register;
const char* RegisterImpl::name() const {
const char* names[number_of_registers] = {
"c_rarg0", "c_rarg1", "c_rarg2", "c_rarg3", "c_rarg4", "c_rarg5", "c_rarg6", "c_rarg7",
"rscratch1", "rscratch2",
"r10", "r11", "r12", "r13", "r14", "r15", "r16",
- "r17", "r18", "r19",
+ "r17", "r18_tls", "r19",
"resp", "rdispatch", "rbcp", "r23", "rlocals", "rmonitors", "rcpool", "rheapbase",
"rthread", "rfp", "lr", "sp"
};
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/register_aarch64.hpp openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/register_aarch64.hpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/register_aarch64.hpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/register_aarch64.hpp 2022-01-13 21:56:25.000000000 +0000
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2000, 2010, Oracle and/or its affiliates. All rights reserved.
- * Copyright (c) 2014, Red Hat Inc. All rights reserved.
+ * Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@@ -44,7 +44,8 @@
enum {
number_of_registers = 32,
number_of_byte_registers = 32,
- number_of_registers_for_jvmci = 34 // Including SP and ZR.
+ number_of_registers_for_jvmci = 34, // Including SP and ZR.
+ max_slots_per_register = 2
};
// derived registers, offsets, and addresses
@@ -64,7 +65,7 @@
// Return the bit which represents this register. This is intended
// to be ORed into a bitmask: for usage see class RegSet below.
- unsigned long bit(bool should_set = true) const { return should_set ? 1 << encoding() : 0; }
+ uint64_t bit(bool should_set = true) const { return should_set ? 1 << encoding() : 0; }
};
// The integer registers of the aarch64 architecture
@@ -90,7 +91,18 @@
CONSTANT_REGISTER_DECLARATION(Register, r15, (15));
CONSTANT_REGISTER_DECLARATION(Register, r16, (16));
CONSTANT_REGISTER_DECLARATION(Register, r17, (17));
-CONSTANT_REGISTER_DECLARATION(Register, r18, (18));
+
+// In the ABI for Windows+AArch64 the register r18 is used to store the pointer
+// to the current thread's TEB (where TLS variables are stored). We could
+// carefully save and restore r18 at key places, however Win32 Structured
+// Exception Handling (SEH) is using TLS to unwind the stack. If r18 is used
+// for any other purpose at the time of an exception happening, SEH would not
+// be able to unwind the stack properly and most likely crash.
+//
+// It's easier to avoid allocating r18 altogether.
+//
+// See https://docs.microsoft.com/en-us/cpp/build/arm64-windows-abi-conventions?view=vs-2019#integer-registers
+CONSTANT_REGISTER_DECLARATION(Register, r18_tls, (18));
CONSTANT_REGISTER_DECLARATION(Register, r19, (19));
CONSTANT_REGISTER_DECLARATION(Register, r20, (20));
CONSTANT_REGISTER_DECLARATION(Register, r21, (21));
@@ -127,7 +139,10 @@
class FloatRegisterImpl: public AbstractRegisterImpl {
public:
enum {
- number_of_registers = 32
+ number_of_registers = 32,
+ max_slots_per_register = 4,
+ save_slots_per_register = 2,
+ extra_save_slots_per_register = max_slots_per_register - save_slots_per_register
};
// construction
@@ -136,7 +151,7 @@
VMReg as_VMReg();
// derived registers, offsets, and addresses
- FloatRegister successor() const { return as_FloatRegister(encoding() + 1); }
+ FloatRegister successor() const { return as_FloatRegister((encoding() + 1) % 32); }
// accessors
int encoding() const { assert(is_valid(), "invalid register"); return (intptr_t)this; }
@@ -193,8 +208,8 @@
// There is no requirement that any ordering here matches any ordering c2 gives
// it's optoregs.
- number_of_registers = (2 * RegisterImpl::number_of_registers +
- 4 * FloatRegisterImpl::number_of_registers +
+ number_of_registers = (RegisterImpl::max_slots_per_register * RegisterImpl::number_of_registers +
+ FloatRegisterImpl::max_slots_per_register * FloatRegisterImpl::number_of_registers +
1) // flags
};
@@ -203,6 +218,8 @@
static const int max_fpr;
};
+class RegSetIterator;
+
// A set of registers
class RegSet {
uint32_t _bitset;
@@ -230,6 +247,11 @@
return *this;
}
+ RegSet &operator-=(const RegSet aSet) {
+ *this = *this - aSet;
+ return *this;
+ }
+
static RegSet of(Register r1) {
return RegSet(r1);
}
@@ -256,6 +278,49 @@
}
uint32_t bits() const { return _bitset; }
+
+private:
+
+ Register first() {
+ uint32_t first = _bitset & -_bitset;
+ return first ? as_Register(exact_log2(first)) : noreg;
+ }
+
+public:
+
+ friend class RegSetIterator;
+
+ RegSetIterator begin();
+};
+
+class RegSetIterator {
+ RegSet _regs;
+
+public:
+ RegSetIterator(RegSet x): _regs(x) {}
+ RegSetIterator(const RegSetIterator& mit) : _regs(mit._regs) {}
+
+ RegSetIterator& operator++() {
+ Register r = _regs.first();
+ if (r != noreg)
+ _regs -= r;
+ return *this;
+ }
+
+ bool operator==(const RegSetIterator& rhs) const {
+ return _regs.bits() == rhs._regs.bits();
+ }
+ bool operator!=(const RegSetIterator& rhs) const {
+ return ! (rhs == *this);
+ }
+
+ Register operator*() {
+ return _regs.first();
+ }
};
+inline RegSetIterator RegSet::begin() {
+ return RegSetIterator(*this);
+}
+
#endif // CPU_AARCH64_VM_REGISTER_AARCH64_HPP
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/register_definitions_aarch64.cpp openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/register_definitions_aarch64.cpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/register_definitions_aarch64.cpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/register_definitions_aarch64.cpp 2022-01-13 21:56:25.000000000 +0000
@@ -50,7 +50,7 @@
REGISTER_DEFINITION(Register, r15);
REGISTER_DEFINITION(Register, r16);
REGISTER_DEFINITION(Register, r17);
-REGISTER_DEFINITION(Register, r18);
+REGISTER_DEFINITION(Register, r18_tls); // see comment in register_aarch64.hpp
REGISTER_DEFINITION(Register, r19);
REGISTER_DEFINITION(Register, r20);
REGISTER_DEFINITION(Register, r21);
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/sharedRuntime_aarch64.cpp openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/sharedRuntime_aarch64.cpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/sharedRuntime_aarch64.cpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/sharedRuntime_aarch64.cpp 2022-01-13 21:56:25.000000000 +0000
@@ -98,15 +98,15 @@
// Capture info about frame layout
enum layout {
fpu_state_off = 0,
- fpu_state_end = fpu_state_off+FPUStateSizeInWords-1,
+ fpu_state_end = fpu_state_off + FPUStateSizeInWords - 1,
// The frame sender code expects that rfp will be in
// the "natural" place and will override any oopMap
// setting for it. We must therefore force the layout
// so that it agrees with the frame sender code.
- r0_off = fpu_state_off+FPUStateSizeInWords,
- rfp_off = r0_off + 30 * 2,
- return_off = rfp_off + 2, // slot for return address
- reg_save_size = return_off + 2};
+ r0_off = fpu_state_off + FPUStateSizeInWords,
+ rfp_off = r0_off + (RegisterImpl::number_of_registers - 2) * RegisterImpl::max_slots_per_register,
+ return_off = rfp_off + RegisterImpl::max_slots_per_register, // slot for return address
+ reg_save_size = return_off + RegisterImpl::max_slots_per_register};
};
@@ -114,19 +114,20 @@
#if COMPILER2_OR_JVMCI
if (save_vectors) {
// Save upper half of vector registers
- int vect_words = 32 * 8 / wordSize;
+ int vect_words = FloatRegisterImpl::number_of_registers * FloatRegisterImpl::extra_save_slots_per_register /
+ VMRegImpl::slots_per_word;
additional_frame_words += vect_words;
}
#else
assert(!save_vectors, "vectors are generated only by C2 and JVMCI");
#endif
- int frame_size_in_bytes = align_up(additional_frame_words*wordSize +
- reg_save_size*BytesPerInt, 16);
+ int frame_size_in_bytes = align_up(additional_frame_words * wordSize +
+ reg_save_size * BytesPerInt, 16);
// OopMap frame size is in compiler stack slots (jint's) not bytes or words
int frame_size_in_slots = frame_size_in_bytes / BytesPerInt;
// The caller will allocate additional_frame_words
- int additional_frame_slots = additional_frame_words*wordSize / BytesPerInt;
+ int additional_frame_slots = additional_frame_words * wordSize / BytesPerInt;
// CodeBlob frame size is in words.
int frame_size_in_words = frame_size_in_bytes / wordSize;
*total_frame_words = frame_size_in_words;
@@ -146,10 +147,10 @@
for (int i = 0; i < RegisterImpl::number_of_registers; i++) {
Register r = as_Register(i);
if (r < rheapbase && r != rscratch1 && r != rscratch2) {
- int sp_offset = 2 * (i + 32); // SP offsets are in 4-byte words,
- // register slots are 8 bytes
- // wide, 32 floating-point
- // registers
+ // SP offsets are in 4-byte words.
+ // Register slots are 8 bytes wide, 32 floating-point registers.
+ int sp_offset = RegisterImpl::max_slots_per_register * i +
+ FloatRegisterImpl::save_slots_per_register * FloatRegisterImpl::number_of_registers;
oop_map->set_callee_saved(VMRegImpl::stack2reg(sp_offset + additional_frame_slots),
r->as_VMReg());
}
@@ -157,7 +158,8 @@
for (int i = 0; i < FloatRegisterImpl::number_of_registers; i++) {
FloatRegister r = as_FloatRegister(i);
- int sp_offset = save_vectors ? (4 * i) : (2 * i);
+ int sp_offset = save_vectors ? (FloatRegisterImpl::max_slots_per_register * i) :
+ (FloatRegisterImpl::save_slots_per_register * i);
oop_map->set_callee_saved(VMRegImpl::stack2reg(sp_offset),
r->as_VMReg());
}
@@ -396,7 +398,7 @@
// 3 8 T_BOOL
// - 0 return address
//
- // However to make thing extra confusing. Because we can fit a long/double in
+ // However to make thing extra confusing. Because we can fit a Java long/double in
// a single slot on a 64 bt vm and it would be silly to break them up, the interpreter
// leaves one slot empty and only stores to a single slot. In this case the
// slot that is occupied is the T_VOID slot. See I said it was confusing.
@@ -429,7 +431,7 @@
__ str(rscratch1, Address(sp, next_off));
#ifdef ASSERT
// Overwrite the unused slot with known junk
- __ mov(rscratch1, 0xdeadffffdeadaaaaul);
+ __ mov(rscratch1, (uint64_t)0xdeadffffdeadaaaaull);
__ str(rscratch1, Address(sp, st_off));
#endif /* ASSERT */
} else {
@@ -446,10 +448,9 @@
// Two VMREgs|OptoRegs can be T_OBJECT, T_ADDRESS, T_DOUBLE, T_LONG
// T_DOUBLE and T_LONG use two slots in the interpreter
if ( sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) {
- // long/double in gpr
+ // jlong/double in gpr
#ifdef ASSERT
- // Overwrite the unused slot with known junk
- __ mov(rscratch1, 0xdeadffffdeadaaabul);
+ __ mov(rscratch1, (uint64_t)0xdeadffffdeadaaabull);
__ str(rscratch1, Address(sp, st_off));
#endif /* ASSERT */
__ str(r, Address(sp, next_off));
@@ -465,7 +466,7 @@
} else {
#ifdef ASSERT
// Overwrite the unused slot with known junk
- __ mov(rscratch1, 0xdeadffffdeadaaacul);
+ __ mov(rscratch1, (uint64_t)0xdeadffffdeadaaacull);
__ str(rscratch1, Address(sp, st_off));
#endif /* ASSERT */
__ strd(r_1->as_FloatRegister(), Address(sp, next_off));
@@ -1673,7 +1674,7 @@
Label dtrace_method_entry, dtrace_method_entry_done;
{
- unsigned long offset;
+ uint64_t offset;
__ adrp(rscratch1, ExternalAddress((address)&DTraceMethodProbes), offset);
__ ldrb(rscratch1, Address(rscratch1, offset));
__ cbnzw(rscratch1, dtrace_method_entry);
@@ -1898,7 +1899,7 @@
Label dtrace_method_exit, dtrace_method_exit_done;
{
- unsigned long offset;
+ uint64_t offset;
__ adrp(rscratch1, ExternalAddress((address)&DTraceMethodProbes), offset);
__ ldrb(rscratch1, Address(rscratch1, offset));
__ cbnzw(rscratch1, dtrace_method_exit);
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/stubGenerator_aarch64.cpp openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/stubGenerator_aarch64.cpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/stubGenerator_aarch64.cpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/stubGenerator_aarch64.cpp 2022-01-13 21:56:25.000000000 +0000
@@ -26,6 +26,7 @@
#include "precompiled.hpp"
#include "asm/macroAssembler.hpp"
#include "asm/macroAssembler.inline.hpp"
+#include "atomic_aarch64.hpp"
#include "gc/shared/barrierSet.hpp"
#include "gc/shared/barrierSetAssembler.hpp"
#include "interpreter/interpreter.hpp"
@@ -35,6 +36,7 @@
#include "oops/objArrayKlass.hpp"
#include "oops/oop.inline.hpp"
#include "prims/methodHandles.hpp"
+#include "runtime/atomic.hpp"
#include "runtime/frame.inline.hpp"
#include "runtime/handles.inline.hpp"
#include "runtime/sharedRuntime.hpp"
@@ -681,7 +683,6 @@
int unit = wordSize * direction;
int bias = (UseSIMDForMemoryOps ? 4:2) * wordSize;
- int offset;
const Register t0 = r3, t1 = r4, t2 = r5, t3 = r6,
t4 = r7, t5 = r10, t6 = r11, t7 = r12;
const Register stride = r13;
@@ -1072,7 +1073,7 @@
Label copy4, copy8, copy16, copy32, copy80, copy128, copy_big, finish;
const Register t2 = r5, t3 = r6, t4 = r7, t5 = r8;
const Register t6 = r9, t7 = r10, t8 = r11, t9 = r12;
- const Register send = r17, dend = r18;
+ const Register send = r17, dend = r16;
if (PrefetchCopyIntervalInBytes > 0)
__ prfm(Address(s, 0), PLDL1KEEP);
@@ -1285,11 +1286,15 @@
void clobber_registers() {
#ifdef ASSERT
+ RegSet clobbered
+ = MacroAssembler::call_clobbered_registers() - rscratch1;
__ mov(rscratch1, (uint64_t)0xdeadbeef);
__ orr(rscratch1, rscratch1, rscratch1, Assembler::LSL, 32);
- for (Register r = r3; r <= r18; r++)
- if (r != rscratch1) __ mov(r, rscratch1);
+ for (RegSetIterator it = clobbered.begin(); *it != noreg; ++it) {
+ __ mov(*it, rscratch1);
+ }
#endif
+
}
// Scan over array at a for count oops, verifying each one.
@@ -1326,7 +1331,7 @@
//
// If 'from' and/or 'to' are aligned on 4-byte boundaries, we let
// the hardware handle it. The two dwords within qwords that span
- // cache line boundaries will still be loaded and stored atomicly.
+ // cache line boundaries will still be loaded and stored atomically.
//
// Side Effects:
// disjoint_int_copy_entry is set to the no-overlap entry point
@@ -1391,7 +1396,7 @@
//
// If 'from' and/or 'to' are aligned on 4-byte boundaries, we let
// the hardware handle it. The two dwords within qwords that span
- // cache line boundaries will still be loaded and stored atomicly.
+ // cache line boundaries will still be loaded and stored atomically.
//
address generate_conjoint_copy(size_t size, bool aligned, bool is_oop, address nooverlap_target,
address *entry, const char *name,
@@ -1551,7 +1556,7 @@
//
// If 'from' and/or 'to' are aligned on 4-byte boundaries, we let
// the hardware handle it. The two dwords within qwords that span
- // cache line boundaries will still be loaded and stored atomicly.
+ // cache line boundaries will still be loaded and stored atomically.
//
// Side Effects:
// disjoint_int_copy_entry is set to the no-overlap entry point
@@ -1575,7 +1580,7 @@
//
// If 'from' and/or 'to' are aligned on 4-byte boundaries, we let
// the hardware handle it. The two dwords within qwords that span
- // cache line boundaries will still be loaded and stored atomicly.
+ // cache line boundaries will still be loaded and stored atomically.
//
address generate_conjoint_int_copy(bool aligned, address nooverlap_target,
address *entry, const char *name,
@@ -1712,10 +1717,10 @@
RegSet wb_pre_saved_regs = RegSet::range(c_rarg0, c_rarg4);
RegSet wb_post_saved_regs = RegSet::of(count);
- // Registers used as temps (r18, r19, r20 are save-on-entry)
+ // Registers used as temps (r19, r20, r21, r22 are save-on-entry)
+ const Register copied_oop = r22; // actual oop copied
const Register count_save = r21; // orig elementscount
const Register start_to = r20; // destination array start address
- const Register copied_oop = r18; // actual oop copied
const Register r19_klass = r19; // oop._klass
//---------------------------------------------------------------
@@ -1752,8 +1757,7 @@
// Empty array: Nothing to do.
__ cbz(count, L_done);
-
- __ push(RegSet::of(r18, r19, r20, r21), sp);
+ __ push(RegSet::of(r19, r20, r21, r22), sp);
#ifdef ASSERT
BLOCK_COMMENT("assert consistent ckoff/ckval");
@@ -1822,7 +1826,7 @@
bs->arraycopy_epilogue(_masm, decorators, is_oop, start_to, count_save, rscratch1, wb_post_saved_regs);
__ bind(L_done_pop);
- __ pop(RegSet::of(r18, r19, r20, r21), sp);
+ __ pop(RegSet::of(r19, r20, r21, r22), sp);
inc_counter_np(SharedRuntime::_checkcast_array_copy_ctr);
__ bind(L_done);
@@ -1998,7 +2002,7 @@
// registers used as temp
const Register scratch_length = r16; // elements count to copy
const Register scratch_src_klass = r17; // array klass
- const Register lh = r18; // layout helper
+ const Register lh = r15; // layout helper
// if (length < 0) return -1;
__ movw(scratch_length, length); // length (elements count, 32-bits value)
@@ -2069,7 +2073,7 @@
//
const Register rscratch1_offset = rscratch1; // array offset
- const Register r18_elsize = lh; // element size
+ const Register r15_elsize = lh; // element size
__ ubfx(rscratch1_offset, lh, Klass::_lh_header_size_shift,
exact_log2(Klass::_lh_header_size_mask+1)); // array_offset
@@ -2090,8 +2094,8 @@
// The possible values of elsize are 0-3, i.e. exact_log2(element
// size in bytes). We do a simple bitwise binary search.
__ BIND(L_copy_bytes);
- __ tbnz(r18_elsize, 1, L_copy_ints);
- __ tbnz(r18_elsize, 0, L_copy_shorts);
+ __ tbnz(r15_elsize, 1, L_copy_ints);
+ __ tbnz(r15_elsize, 0, L_copy_shorts);
__ lea(from, Address(src, src_pos));// src_addr
__ lea(to, Address(dst, dst_pos));// dst_addr
__ movw(count, scratch_length); // length
@@ -2104,7 +2108,7 @@
__ b(RuntimeAddress(short_copy_entry));
__ BIND(L_copy_ints);
- __ tbnz(r18_elsize, 0, L_copy_longs);
+ __ tbnz(r15_elsize, 0, L_copy_longs);
__ lea(from, Address(src, src_pos, Address::lsl(2)));// src_addr
__ lea(to, Address(dst, dst_pos, Address::lsl(2)));// dst_addr
__ movw(count, scratch_length); // length
@@ -2115,8 +2119,8 @@
{
BLOCK_COMMENT("assert long copy {");
Label L;
- __ andw(lh, lh, Klass::_lh_log2_element_size_mask); // lh -> r18_elsize
- __ cmpw(r18_elsize, LogBytesPerLong);
+ __ andw(lh, lh, Klass::_lh_log2_element_size_mask); // lh -> r15_elsize
+ __ cmpw(r15_elsize, LogBytesPerLong);
__ br(Assembler::EQ, L);
__ stop("must be long copy, but elsize is wrong");
__ bind(L);
@@ -2134,8 +2138,8 @@
Label L_plain_copy, L_checkcast_copy;
// test array classes for subtyping
- __ load_klass(r18, dst);
- __ cmp(scratch_src_klass, r18); // usual case is exact equality
+ __ load_klass(r15, dst);
+ __ cmp(scratch_src_klass, r15); // usual case is exact equality
__ br(Assembler::NE, L_checkcast_copy);
// Identically typed arrays can be copied without element-wise checks.
@@ -2151,17 +2155,17 @@
__ b(RuntimeAddress(oop_copy_entry));
__ BIND(L_checkcast_copy);
- // live at this point: scratch_src_klass, scratch_length, r18 (dst_klass)
+ // live at this point: scratch_src_klass, scratch_length, r15 (dst_klass)
{
// Before looking at dst.length, make sure dst is also an objArray.
- __ ldrw(rscratch1, Address(r18, lh_offset));
+ __ ldrw(rscratch1, Address(r15, lh_offset));
__ movw(rscratch2, objArray_lh);
__ eorw(rscratch1, rscratch1, rscratch2);
__ cbnzw(rscratch1, L_failed);
// It is safe to examine both src.length and dst.length.
arraycopy_range_checks(src, src_pos, dst, dst_pos, scratch_length,
- r18, L_failed);
+ r15, L_failed);
__ load_klass(dst_klass, dst); // reload
@@ -2878,6 +2882,265 @@
return start;
}
+ // CTR AES crypt.
+ // Arguments:
+ //
+ // Inputs:
+ // c_rarg0 - source byte array address
+ // c_rarg1 - destination byte array address
+ // c_rarg2 - K (key) in little endian int array
+ // c_rarg3 - counter vector byte array address
+ // c_rarg4 - input length
+ // c_rarg5 - saved encryptedCounter start
+ // c_rarg6 - saved used length
+ //
+ // Output:
+ // r0 - input length
+ //
+ address generate_counterMode_AESCrypt() {
+ const Register in = c_rarg0;
+ const Register out = c_rarg1;
+ const Register key = c_rarg2;
+ const Register counter = c_rarg3;
+ const Register saved_len = c_rarg4, len = r10;
+ const Register saved_encrypted_ctr = c_rarg5;
+ const Register used_ptr = c_rarg6, used = r12;
+
+ const Register offset = r7;
+ const Register keylen = r11;
+
+ const unsigned char block_size = 16;
+ const int bulk_width = 4;
+ // NB: bulk_width can be 4 or 8. 8 gives slightly faster
+ // performance with larger data sizes, but it also means that the
+ // fast path isn't used until you have at least 8 blocks, and up
+ // to 127 bytes of data will be executed on the slow path. For
+ // that reason, and also so as not to blow away too much icache, 4
+ // blocks seems like a sensible compromise.
+
+ // Algorithm:
+ //
+ // if (len == 0) {
+ // goto DONE;
+ // }
+ // int result = len;
+ // do {
+ // if (used >= blockSize) {
+ // if (len >= bulk_width * blockSize) {
+ // CTR_large_block();
+ // if (len == 0)
+ // goto DONE;
+ // }
+ // for (;;) {
+ // 16ByteVector v0 = counter;
+ // embeddedCipher.encryptBlock(v0, 0, encryptedCounter, 0);
+ // used = 0;
+ // if (len < blockSize)
+ // break; /* goto NEXT */
+ // 16ByteVector v1 = load16Bytes(in, offset);
+ // v1 = v1 ^ encryptedCounter;
+ // store16Bytes(out, offset);
+ // used = blockSize;
+ // offset += blockSize;
+ // len -= blockSize;
+ // if (len == 0)
+ // goto DONE;
+ // }
+ // }
+ // NEXT:
+ // out[outOff++] = (byte)(in[inOff++] ^ encryptedCounter[used++]);
+ // len--;
+ // } while (len != 0);
+ // DONE:
+ // return result;
+ //
+ // CTR_large_block()
+ // Wide bulk encryption of whole blocks.
+
+ __ align(CodeEntryAlignment);
+ StubCodeMark mark(this, "StubRoutines", "counterMode_AESCrypt");
+ const address start = __ pc();
+ __ enter();
+
+ Label DONE, CTR_large_block, large_block_return;
+ __ ldrw(used, Address(used_ptr));
+ __ cbzw(saved_len, DONE);
+
+ __ mov(len, saved_len);
+ __ mov(offset, 0);
+
+ // Compute #rounds for AES based on the length of the key array
+ __ ldrw(keylen, Address(key, arrayOopDesc::length_offset_in_bytes() - arrayOopDesc::base_offset_in_bytes(T_INT)));
+
+ __ aesenc_loadkeys(key, keylen);
+
+ {
+ Label L_CTR_loop, NEXT;
+
+ __ bind(L_CTR_loop);
+
+ __ cmp(used, block_size);
+ __ br(__ LO, NEXT);
+
+ // Maybe we have a lot of data
+ __ subsw(rscratch1, len, bulk_width * block_size);
+ __ br(__ HS, CTR_large_block);
+ __ BIND(large_block_return);
+ __ cbzw(len, DONE);
+
+ // Setup the counter
+ __ movi(v4, __ T4S, 0);
+ __ movi(v5, __ T4S, 1);
+ __ ins(v4, __ S, v5, 3, 3); // v4 contains { 0, 0, 0, 1 }
+
+ __ ld1(v0, __ T16B, counter); // Load the counter into v0
+ __ rev32(v16, __ T16B, v0);
+ __ addv(v16, __ T4S, v16, v4);
+ __ rev32(v16, __ T16B, v16);
+ __ st1(v16, __ T16B, counter); // Save the incremented counter back
+
+ {
+ // We have fewer than bulk_width blocks of data left. Encrypt
+ // them one by one until there is less than a full block
+ // remaining, being careful to save both the encrypted counter
+ // and the counter.
+
+ Label inner_loop;
+ __ bind(inner_loop);
+ // Counter to encrypt is in v0
+ __ aesecb_encrypt(noreg, noreg, keylen);
+ __ st1(v0, __ T16B, saved_encrypted_ctr);
+
+ // Do we have a remaining full block?
+
+ __ mov(used, 0);
+ __ cmp(len, block_size);
+ __ br(__ LO, NEXT);
+
+ // Yes, we have a full block
+ __ ldrq(v1, Address(in, offset));
+ __ eor(v1, __ T16B, v1, v0);
+ __ strq(v1, Address(out, offset));
+ __ mov(used, block_size);
+ __ add(offset, offset, block_size);
+
+ __ subw(len, len, block_size);
+ __ cbzw(len, DONE);
+
+ // Increment the counter, store it back
+ __ orr(v0, __ T16B, v16, v16);
+ __ rev32(v16, __ T16B, v16);
+ __ addv(v16, __ T4S, v16, v4);
+ __ rev32(v16, __ T16B, v16);
+ __ st1(v16, __ T16B, counter); // Save the incremented counter back
+
+ __ b(inner_loop);
+ }
+
+ __ BIND(NEXT);
+
+ // Encrypt a single byte, and loop.
+ // We expect this to be a rare event.
+ __ ldrb(rscratch1, Address(in, offset));
+ __ ldrb(rscratch2, Address(saved_encrypted_ctr, used));
+ __ eor(rscratch1, rscratch1, rscratch2);
+ __ strb(rscratch1, Address(out, offset));
+ __ add(offset, offset, 1);
+ __ add(used, used, 1);
+ __ subw(len, len,1);
+ __ cbnzw(len, L_CTR_loop);
+ }
+
+ __ bind(DONE);
+ __ strw(used, Address(used_ptr));
+ __ mov(r0, saved_len);
+
+ __ leave(); // required for proper stackwalking of RuntimeStub frame
+ __ ret(lr);
+
+ // Bulk encryption
+
+ __ BIND (CTR_large_block);
+ assert(bulk_width == 4 || bulk_width == 8, "must be");
+
+ if (bulk_width == 8) {
+ __ sub(sp, sp, 4 * 16);
+ __ st1(v12, v13, v14, v15, __ T16B, Address(sp));
+ }
+ __ sub(sp, sp, 4 * 16);
+ __ st1(v8, v9, v10, v11, __ T16B, Address(sp));
+ RegSet saved_regs = (RegSet::of(in, out, offset)
+ + RegSet::of(saved_encrypted_ctr, used_ptr, len));
+ __ push(saved_regs, sp);
+ __ andr(len, len, -16 * bulk_width); // 8/4 encryptions, 16 bytes per encryption
+ __ add(in, in, offset);
+ __ add(out, out, offset);
+
+ // Keys should already be loaded into the correct registers
+
+ __ ld1(v0, __ T16B, counter); // v0 contains the first counter
+ __ rev32(v16, __ T16B, v0); // v16 contains byte-reversed counter
+
+ // AES/CTR loop
+ {
+ Label L_CTR_loop;
+ __ BIND(L_CTR_loop);
+
+ // Setup the counters
+ __ movi(v8, __ T4S, 0);
+ __ movi(v9, __ T4S, 1);
+ __ ins(v8, __ S, v9, 3, 3); // v8 contains { 0, 0, 0, 1 }
+
+ for (FloatRegister f = v0; f < v0 + bulk_width; f++) {
+ __ rev32(f, __ T16B, v16);
+ __ addv(v16, __ T4S, v16, v8);
+ }
+
+ __ ld1(v8, v9, v10, v11, __ T16B, __ post(in, 4 * 16));
+
+ // Encrypt the counters
+ __ aesecb_encrypt(noreg, noreg, keylen, v0, bulk_width);
+
+ if (bulk_width == 8) {
+ __ ld1(v12, v13, v14, v15, __ T16B, __ post(in, 4 * 16));
+ }
+
+ // XOR the encrypted counters with the inputs
+ for (int i = 0; i < bulk_width; i++) {
+ __ eor(v0 + i, __ T16B, v0 + i, v8 + i);
+ }
+
+ // Write the encrypted data
+ __ st1(v0, v1, v2, v3, __ T16B, __ post(out, 4 * 16));
+ if (bulk_width == 8) {
+ __ st1(v4, v5, v6, v7, __ T16B, __ post(out, 4 * 16));
+ }
+
+ __ subw(len, len, 16 * bulk_width);
+ __ cbnzw(len, L_CTR_loop);
+ }
+
+ // Save the counter back where it goes
+ __ rev32(v16, __ T16B, v16);
+ __ st1(v16, __ T16B, counter);
+
+ __ pop(saved_regs, sp);
+
+ __ ld1(v8, v9, v10, v11, __ T16B, __ post(sp, 4 * 16));
+ if (bulk_width == 8) {
+ __ ld1(v12, v13, v14, v15, __ T16B, __ post(sp, 4 * 16));
+ }
+
+ __ andr(rscratch1, len, -16 * bulk_width);
+ __ sub(len, len, rscratch1);
+ __ add(offset, offset, rscratch1);
+ __ mov(used, 16);
+ __ strw(used, Address(used_ptr));
+ __ b(large_block_return);
+
+ return start;
+ }
+
// Arguments:
//
// Inputs:
@@ -3230,20 +3493,27 @@
Register buff = c_rarg1;
Register len = c_rarg2;
Register nmax = r4;
- Register base = r5;
+ Register base = r5;
Register count = r6;
Register temp0 = rscratch1;
Register temp1 = rscratch2;
- Register temp2 = r7;
+ FloatRegister vbytes = v0;
+ FloatRegister vs1acc = v1;
+ FloatRegister vs2acc = v2;
+ FloatRegister vtable = v3;
// Max number of bytes we can process before having to take the mod
// 0x15B0 is 5552 in decimal, the largest n such that 255n(n+1)/2 + (n+1)(BASE-1) <= 2^32-1
- unsigned long BASE = 0xfff1;
- unsigned long NMAX = 0x15B0;
+ uint64_t BASE = 0xfff1;
+ uint64_t NMAX = 0x15B0;
__ mov(base, BASE);
__ mov(nmax, NMAX);
+ // Load accumulation coefficients for the upper 16 bits
+ __ lea(temp0, ExternalAddress((address) StubRoutines::aarch64::_adler_table));
+ __ ld1(vtable, __ T16B, Address(temp0));
+
// s1 is initialized to the lower 16 bits of adler
// s2 is initialized to the upper 16 bits of adler
__ ubfx(s2, adler, 16, 16); // s2 = ((adler >> 16) & 0xffff)
@@ -3284,53 +3554,8 @@
__ bind(L_nmax_loop);
- __ ldp(temp0, temp1, Address(__ post(buff, 16)));
-
- __ add(s1, s1, temp0, ext::uxtb);
- __ ubfx(temp2, temp0, 8, 8);
- __ add(s2, s2, s1);
- __ add(s1, s1, temp2);
- __ ubfx(temp2, temp0, 16, 8);
- __ add(s2, s2, s1);
- __ add(s1, s1, temp2);
- __ ubfx(temp2, temp0, 24, 8);
- __ add(s2, s2, s1);
- __ add(s1, s1, temp2);
- __ ubfx(temp2, temp0, 32, 8);
- __ add(s2, s2, s1);
- __ add(s1, s1, temp2);
- __ ubfx(temp2, temp0, 40, 8);
- __ add(s2, s2, s1);
- __ add(s1, s1, temp2);
- __ ubfx(temp2, temp0, 48, 8);
- __ add(s2, s2, s1);
- __ add(s1, s1, temp2);
- __ add(s2, s2, s1);
- __ add(s1, s1, temp0, Assembler::LSR, 56);
- __ add(s2, s2, s1);
-
- __ add(s1, s1, temp1, ext::uxtb);
- __ ubfx(temp2, temp1, 8, 8);
- __ add(s2, s2, s1);
- __ add(s1, s1, temp2);
- __ ubfx(temp2, temp1, 16, 8);
- __ add(s2, s2, s1);
- __ add(s1, s1, temp2);
- __ ubfx(temp2, temp1, 24, 8);
- __ add(s2, s2, s1);
- __ add(s1, s1, temp2);
- __ ubfx(temp2, temp1, 32, 8);
- __ add(s2, s2, s1);
- __ add(s1, s1, temp2);
- __ ubfx(temp2, temp1, 40, 8);
- __ add(s2, s2, s1);
- __ add(s1, s1, temp2);
- __ ubfx(temp2, temp1, 48, 8);
- __ add(s2, s2, s1);
- __ add(s1, s1, temp2);
- __ add(s2, s2, s1);
- __ add(s1, s1, temp1, Assembler::LSR, 56);
- __ add(s2, s2, s1);
+ generate_updateBytesAdler32_accum(s1, s2, buff, temp0, temp1,
+ vbytes, vs1acc, vs2acc, vtable);
__ subs(count, count, 16);
__ br(Assembler::HS, L_nmax_loop);
@@ -3373,53 +3598,8 @@
__ bind(L_by16_loop);
- __ ldp(temp0, temp1, Address(__ post(buff, 16)));
-
- __ add(s1, s1, temp0, ext::uxtb);
- __ ubfx(temp2, temp0, 8, 8);
- __ add(s2, s2, s1);
- __ add(s1, s1, temp2);
- __ ubfx(temp2, temp0, 16, 8);
- __ add(s2, s2, s1);
- __ add(s1, s1, temp2);
- __ ubfx(temp2, temp0, 24, 8);
- __ add(s2, s2, s1);
- __ add(s1, s1, temp2);
- __ ubfx(temp2, temp0, 32, 8);
- __ add(s2, s2, s1);
- __ add(s1, s1, temp2);
- __ ubfx(temp2, temp0, 40, 8);
- __ add(s2, s2, s1);
- __ add(s1, s1, temp2);
- __ ubfx(temp2, temp0, 48, 8);
- __ add(s2, s2, s1);
- __ add(s1, s1, temp2);
- __ add(s2, s2, s1);
- __ add(s1, s1, temp0, Assembler::LSR, 56);
- __ add(s2, s2, s1);
-
- __ add(s1, s1, temp1, ext::uxtb);
- __ ubfx(temp2, temp1, 8, 8);
- __ add(s2, s2, s1);
- __ add(s1, s1, temp2);
- __ ubfx(temp2, temp1, 16, 8);
- __ add(s2, s2, s1);
- __ add(s1, s1, temp2);
- __ ubfx(temp2, temp1, 24, 8);
- __ add(s2, s2, s1);
- __ add(s1, s1, temp2);
- __ ubfx(temp2, temp1, 32, 8);
- __ add(s2, s2, s1);
- __ add(s1, s1, temp2);
- __ ubfx(temp2, temp1, 40, 8);
- __ add(s2, s2, s1);
- __ add(s1, s1, temp2);
- __ ubfx(temp2, temp1, 48, 8);
- __ add(s2, s2, s1);
- __ add(s1, s1, temp2);
- __ add(s2, s2, s1);
- __ add(s1, s1, temp1, Assembler::LSR, 56);
- __ add(s2, s2, s1);
+ generate_updateBytesAdler32_accum(s1, s2, buff, temp0, temp1,
+ vbytes, vs1acc, vs2acc, vtable);
__ subs(len, len, 16);
__ br(Assembler::HS, L_by16_loop);
@@ -3473,6 +3653,43 @@
return start;
}
+ void generate_updateBytesAdler32_accum(Register s1, Register s2, Register buff,
+ Register temp0, Register temp1, FloatRegister vbytes,
+ FloatRegister vs1acc, FloatRegister vs2acc, FloatRegister vtable) {
+ // Below is a vectorized implementation of updating s1 and s2 for 16 bytes.
+ // We use b1, b2, ..., b16 to denote the 16 bytes loaded in each iteration.
+ // In non-vectorized code, we update s1 and s2 as:
+ // s1 <- s1 + b1
+ // s2 <- s2 + s1
+ // s1 <- s1 + b2
+ // s2 <- s2 + b1
+ // ...
+ // s1 <- s1 + b16
+ // s2 <- s2 + s1
+ // Putting above assignments together, we have:
+ // s1_new = s1 + b1 + b2 + ... + b16
+ // s2_new = s2 + (s1 + b1) + (s1 + b1 + b2) + ... + (s1 + b1 + b2 + ... + b16)
+ // = s2 + s1 * 16 + (b1 * 16 + b2 * 15 + ... + b16 * 1)
+ // = s2 + s1 * 16 + (b1, b2, ... b16) dot (16, 15, ... 1)
+ __ ld1(vbytes, __ T16B, Address(__ post(buff, 16)));
+
+ // s2 = s2 + s1 * 16
+ __ add(s2, s2, s1, Assembler::LSL, 4);
+
+ // vs1acc = b1 + b2 + b3 + ... + b16
+ // vs2acc = (b1 * 16) + (b2 * 15) + (b3 * 14) + ... + (b16 * 1)
+ __ umullv(vs2acc, __ T8B, vtable, vbytes);
+ __ umlalv(vs2acc, __ T16B, vtable, vbytes);
+ __ uaddlv(vs1acc, __ T16B, vbytes);
+ __ uaddlv(vs2acc, __ T8H, vs2acc);
+
+ // s1 = s1 + vs1acc, s2 = s2 + vs2acc
+ __ fmovd(temp0, vs1acc);
+ __ fmovd(temp1, vs2acc);
+ __ add(s1, s1, temp0);
+ __ add(s2, s2, temp1);
+ }
+
/**
* Arguments:
*
@@ -4065,7 +4282,7 @@
FloatRegister vtmpZ = v0, vtmp = v1, vtmp3 = v2;
RegSet spilled_regs = RegSet::of(tmp3, tmp4);
- int prefetchLoopExitCondition = MAX(64, SoftwarePrefetchHintDistance/2);
+ int prefetchLoopExitCondition = MAX2(64, SoftwarePrefetchHintDistance/2);
__ eor(vtmpZ, __ T16B, vtmpZ, vtmpZ);
// cnt2 == amount of characters left to compare
@@ -4181,7 +4398,7 @@
DIFF_LAST_POSITION, DIFF_LAST_POSITION2;
// exit from large loop when less than 64 bytes left to read or we're about
// to prefetch memory behind array border
- int largeLoopExitCondition = MAX(64, SoftwarePrefetchHintDistance)/(isLL ? 1 : 2);
+ int largeLoopExitCondition = MAX2(64, SoftwarePrefetchHintDistance)/(isLL ? 1 : 2);
// cnt1/cnt2 contains amount of characters to compare. cnt1 can be re-used
// update cnt2 counter with already loaded 8 bytes
__ sub(cnt2, cnt2, wordSize/(isLL ? 1 : 2));
@@ -4606,7 +4823,7 @@
address entry = __ pc();
Label LOOP, LOOP_START, LOOP_PRFM, LOOP_PRFM_START, DONE;
Register src = r0, dst = r1, len = r2, octetCounter = r3;
- const int large_loop_threshold = MAX(64, SoftwarePrefetchHintDistance)/8 + 4;
+ const int large_loop_threshold = MAX2(64, SoftwarePrefetchHintDistance)/8 + 4;
// do one more 8-byte read to have address 16-byte aligned in most cases
// also use single store instruction
@@ -4730,6 +4947,364 @@
return start;
}
+ address generate_ghash_processBlocks_wide() {
+ address small = generate_ghash_processBlocks();
+
+ StubCodeMark mark(this, "StubRoutines", "ghash_processBlocks_wide");
+ __ align(wordSize * 2);
+ address p = __ pc();
+ __ emit_int64(0x87); // The low-order bits of the field
+ // polynomial (i.e. p = z^7+z^2+z+1)
+ // repeated in the low and high parts of a
+ // 128-bit vector
+ __ emit_int64(0x87);
+
+ __ align(CodeEntryAlignment);
+ address start = __ pc();
+
+ Register state = c_rarg0;
+ Register subkeyH = c_rarg1;
+ Register data = c_rarg2;
+ Register blocks = c_rarg3;
+
+ const int unroll = 4;
+
+ __ cmp(blocks, (unsigned char)(unroll * 2));
+ __ br(__ LT, small);
+
+ if (unroll > 1) {
+ // Save state before entering routine
+ __ sub(sp, sp, 4 * 16);
+ __ st1(v12, v13, v14, v15, __ T16B, Address(sp));
+ __ sub(sp, sp, 4 * 16);
+ __ st1(v8, v9, v10, v11, __ T16B, Address(sp));
+ }
+
+ __ ghash_processBlocks_wide(p, state, subkeyH, data, blocks, unroll);
+
+ if (unroll > 1) {
+ // And restore state
+ __ ld1(v8, v9, v10, v11, __ T16B, __ post(sp, 4 * 16));
+ __ ld1(v12, v13, v14, v15, __ T16B, __ post(sp, 4 * 16));
+ }
+
+ __ cmp(blocks, 0u);
+ __ br(__ GT, small);
+
+ __ ret(lr);
+
+ return start;
+ }
+
+#ifdef LINUX
+
+ // ARMv8.1 LSE versions of the atomic stubs used by Atomic::PlatformXX.
+ //
+ // If LSE is in use, generate LSE versions of all the stubs. The
+ // non-LSE versions are in atomic_aarch64.S.
+
+ // class AtomicStubMark records the entry point of a stub and the
+ // stub pointer which will point to it. The stub pointer is set to
+ // the entry point when ~AtomicStubMark() is called, which must be
+ // after ICache::invalidate_range. This ensures safe publication of
+ // the generated code.
+ class AtomicStubMark {
+ address _entry_point;
+ aarch64_atomic_stub_t *_stub;
+ MacroAssembler *_masm;
+ public:
+ AtomicStubMark(MacroAssembler *masm, aarch64_atomic_stub_t *stub) {
+ _masm = masm;
+ __ align(32);
+ _entry_point = __ pc();
+ _stub = stub;
+ }
+ ~AtomicStubMark() {
+ *_stub = (aarch64_atomic_stub_t)_entry_point;
+ }
+ };
+
+ // NB: For memory_order_conservative we need a trailing membar after
+ // LSE atomic operations but not a leading membar.
+ //
+ // We don't need a leading membar because a clause in the Arm ARM
+ // says:
+ //
+ // Barrier-ordered-before
+ //
+ // Barrier instructions order prior Memory effects before subsequent
+ // Memory effects generated by the same Observer. A read or a write
+ // RW1 is Barrier-ordered-before a read or a write RW 2 from the same
+ // Observer if and only if RW1 appears in program order before RW 2
+ // and [ ... ] at least one of RW 1 and RW 2 is generated by an atomic
+ // instruction with both Acquire and Release semantics.
+ //
+ // All the atomic instructions {ldaddal, swapal, casal} have Acquire
+ // and Release semantics, therefore we don't need a leading
+ // barrier. However, there is no corresponding Barrier-ordered-after
+ // relationship, therefore we need a trailing membar to prevent a
+ // later store or load from being reordered with the store in an
+ // atomic instruction.
+ //
+ // This was checked by using the herd7 consistency model simulator
+ // (http://diy.inria.fr/) with this test case:
+ //
+ // AArch64 LseCas
+ // { 0:X1=x; 0:X2=y; 1:X1=x; 1:X2=y; }
+ // P0 | P1;
+ // LDR W4, [X2] | MOV W3, #0;
+ // DMB LD | MOV W4, #1;
+ // LDR W3, [X1] | CASAL W3, W4, [X1];
+ // | DMB ISH;
+ // | STR W4, [X2];
+ // exists
+ // (0:X3=0 /\ 0:X4=1)
+ //
+ // If X3 == 0 && X4 == 1, the store to y in P1 has been reordered
+ // with the store to x in P1. Without the DMB in P1 this may happen.
+ //
+ // At the time of writing we don't know of any AArch64 hardware that
+ // reorders stores in this way, but the Reference Manual permits it.
+
+ void gen_cas_entry(Assembler::operand_size size,
+ atomic_memory_order order) {
+ Register prev = r3, ptr = c_rarg0, compare_val = c_rarg1,
+ exchange_val = c_rarg2;
+ bool acquire, release;
+ switch (order) {
+ case memory_order_relaxed:
+ acquire = false;
+ release = false;
+ break;
+ default:
+ acquire = true;
+ release = true;
+ break;
+ }
+ __ mov(prev, compare_val);
+ __ lse_cas(prev, exchange_val, ptr, size, acquire, release, /*not_pair*/true);
+ if (order == memory_order_conservative) {
+ __ membar(Assembler::StoreStore|Assembler::StoreLoad);
+ }
+ if (size == Assembler::xword) {
+ __ mov(r0, prev);
+ } else {
+ __ movw(r0, prev);
+ }
+ __ ret(lr);
+ }
+
+ void gen_ldaddal_entry(Assembler::operand_size size) {
+ Register prev = r2, addr = c_rarg0, incr = c_rarg1;
+ __ ldaddal(size, incr, prev, addr);
+ __ membar(Assembler::StoreStore|Assembler::StoreLoad);
+ if (size == Assembler::xword) {
+ __ mov(r0, prev);
+ } else {
+ __ movw(r0, prev);
+ }
+ __ ret(lr);
+ }
+
+ void gen_swpal_entry(Assembler::operand_size size) {
+ Register prev = r2, addr = c_rarg0, incr = c_rarg1;
+ __ swpal(size, incr, prev, addr);
+ __ membar(Assembler::StoreStore|Assembler::StoreLoad);
+ if (size == Assembler::xword) {
+ __ mov(r0, prev);
+ } else {
+ __ movw(r0, prev);
+ }
+ __ ret(lr);
+ }
+
+ void generate_atomic_entry_points() {
+ if (! UseLSE) {
+ return;
+ }
+
+ __ align(CodeEntryAlignment);
+ StubCodeMark mark(this, "StubRoutines", "atomic entry points");
+ address first_entry = __ pc();
+
+ // All memory_order_conservative
+ AtomicStubMark mark_fetch_add_4(_masm, &aarch64_atomic_fetch_add_4_impl);
+ gen_ldaddal_entry(Assembler::word);
+ AtomicStubMark mark_fetch_add_8(_masm, &aarch64_atomic_fetch_add_8_impl);
+ gen_ldaddal_entry(Assembler::xword);
+
+ AtomicStubMark mark_xchg_4(_masm, &aarch64_atomic_xchg_4_impl);
+ gen_swpal_entry(Assembler::word);
+ AtomicStubMark mark_xchg_8_impl(_masm, &aarch64_atomic_xchg_8_impl);
+ gen_swpal_entry(Assembler::xword);
+
+ // CAS, memory_order_conservative
+ AtomicStubMark mark_cmpxchg_1(_masm, &aarch64_atomic_cmpxchg_1_impl);
+ gen_cas_entry(MacroAssembler::byte, memory_order_conservative);
+ AtomicStubMark mark_cmpxchg_4(_masm, &aarch64_atomic_cmpxchg_4_impl);
+ gen_cas_entry(MacroAssembler::word, memory_order_conservative);
+ AtomicStubMark mark_cmpxchg_8(_masm, &aarch64_atomic_cmpxchg_8_impl);
+ gen_cas_entry(MacroAssembler::xword, memory_order_conservative);
+
+ // CAS, memory_order_relaxed
+ AtomicStubMark mark_cmpxchg_1_relaxed
+ (_masm, &aarch64_atomic_cmpxchg_1_relaxed_impl);
+ gen_cas_entry(MacroAssembler::byte, memory_order_relaxed);
+ AtomicStubMark mark_cmpxchg_4_relaxed
+ (_masm, &aarch64_atomic_cmpxchg_4_relaxed_impl);
+ gen_cas_entry(MacroAssembler::word, memory_order_relaxed);
+ AtomicStubMark mark_cmpxchg_8_relaxed
+ (_masm, &aarch64_atomic_cmpxchg_8_relaxed_impl);
+ gen_cas_entry(MacroAssembler::xword, memory_order_relaxed);
+
+ ICache::invalidate_range(first_entry, __ pc() - first_entry);
+ }
+#endif // LINUX
+
+ void generate_base64_encode_simdround(Register src, Register dst,
+ FloatRegister codec, u8 size) {
+
+ FloatRegister in0 = v4, in1 = v5, in2 = v6;
+ FloatRegister out0 = v16, out1 = v17, out2 = v18, out3 = v19;
+ FloatRegister ind0 = v20, ind1 = v21, ind2 = v22, ind3 = v23;
+
+ Assembler::SIMD_Arrangement arrangement = size == 16 ? __ T16B : __ T8B;
+
+ __ ld3(in0, in1, in2, arrangement, __ post(src, 3 * size));
+
+ __ ushr(ind0, arrangement, in0, 2);
+
+ __ ushr(ind1, arrangement, in1, 2);
+ __ shl(in0, arrangement, in0, 6);
+ __ orr(ind1, arrangement, ind1, in0);
+ __ ushr(ind1, arrangement, ind1, 2);
+
+ __ ushr(ind2, arrangement, in2, 4);
+ __ shl(in1, arrangement, in1, 4);
+ __ orr(ind2, arrangement, in1, ind2);
+ __ ushr(ind2, arrangement, ind2, 2);
+
+ __ shl(ind3, arrangement, in2, 2);
+ __ ushr(ind3, arrangement, ind3, 2);
+
+ __ tbl(out0, arrangement, codec, 4, ind0);
+ __ tbl(out1, arrangement, codec, 4, ind1);
+ __ tbl(out2, arrangement, codec, 4, ind2);
+ __ tbl(out3, arrangement, codec, 4, ind3);
+
+ __ st4(out0, out1, out2, out3, arrangement, __ post(dst, 4 * size));
+ }
+
+ /**
+ * Arguments:
+ *
+ * Input:
+ * c_rarg0 - src_start
+ * c_rarg1 - src_offset
+ * c_rarg2 - src_length
+ * c_rarg3 - dest_start
+ * c_rarg4 - dest_offset
+ * c_rarg5 - isURL
+ *
+ */
+ address generate_base64_encodeBlock() {
+
+ static const char toBase64[64] = {
+ 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J', 'K', 'L', 'M',
+ 'N', 'O', 'P', 'Q', 'R', 'S', 'T', 'U', 'V', 'W', 'X', 'Y', 'Z',
+ 'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j', 'k', 'l', 'm',
+ 'n', 'o', 'p', 'q', 'r', 's', 't', 'u', 'v', 'w', 'x', 'y', 'z',
+ '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', '+', '/'
+ };
+
+ static const char toBase64URL[64] = {
+ 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J', 'K', 'L', 'M',
+ 'N', 'O', 'P', 'Q', 'R', 'S', 'T', 'U', 'V', 'W', 'X', 'Y', 'Z',
+ 'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j', 'k', 'l', 'm',
+ 'n', 'o', 'p', 'q', 'r', 's', 't', 'u', 'v', 'w', 'x', 'y', 'z',
+ '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', '-', '_'
+ };
+
+ __ align(CodeEntryAlignment);
+ StubCodeMark mark(this, "StubRoutines", "encodeBlock");
+ address start = __ pc();
+
+ Register src = c_rarg0; // source array
+ Register soff = c_rarg1; // source start offset
+ Register send = c_rarg2; // source end offset
+ Register dst = c_rarg3; // dest array
+ Register doff = c_rarg4; // position for writing to dest array
+ Register isURL = c_rarg5; // Base64 or URL chracter set
+
+ // c_rarg6 and c_rarg7 are free to use as temps
+ Register codec = c_rarg6;
+ Register length = c_rarg7;
+
+ Label ProcessData, Process48B, Process24B, Process3B, SIMDExit, Exit;
+
+ __ add(src, src, soff);
+ __ add(dst, dst, doff);
+ __ sub(length, send, soff);
+
+ // load the codec base address
+ __ lea(codec, ExternalAddress((address) toBase64));
+ __ cbz(isURL, ProcessData);
+ __ lea(codec, ExternalAddress((address) toBase64URL));
+
+ __ BIND(ProcessData);
+
+ // too short to formup a SIMD loop, roll back
+ __ cmp(length, (u1)24);
+ __ br(Assembler::LT, Process3B);
+
+ __ ld1(v0, v1, v2, v3, __ T16B, Address(codec));
+
+ __ BIND(Process48B);
+ __ cmp(length, (u1)48);
+ __ br(Assembler::LT, Process24B);
+ generate_base64_encode_simdround(src, dst, v0, 16);
+ __ sub(length, length, 48);
+ __ b(Process48B);
+
+ __ BIND(Process24B);
+ __ cmp(length, (u1)24);
+ __ br(Assembler::LT, SIMDExit);
+ generate_base64_encode_simdround(src, dst, v0, 8);
+ __ sub(length, length, 24);
+
+ __ BIND(SIMDExit);
+ __ cbz(length, Exit);
+
+ __ BIND(Process3B);
+ // 3 src bytes, 24 bits
+ __ ldrb(r10, __ post(src, 1));
+ __ ldrb(r11, __ post(src, 1));
+ __ ldrb(r12, __ post(src, 1));
+ __ orrw(r11, r11, r10, Assembler::LSL, 8);
+ __ orrw(r12, r12, r11, Assembler::LSL, 8);
+ // codec index
+ __ ubfmw(r15, r12, 18, 23);
+ __ ubfmw(r14, r12, 12, 17);
+ __ ubfmw(r13, r12, 6, 11);
+ __ andw(r12, r12, 63);
+ // get the code based on the codec
+ __ ldrb(r15, Address(codec, r15, Address::uxtw(0)));
+ __ ldrb(r14, Address(codec, r14, Address::uxtw(0)));
+ __ ldrb(r13, Address(codec, r13, Address::uxtw(0)));
+ __ ldrb(r12, Address(codec, r12, Address::uxtw(0)));
+ __ strb(r15, __ post(dst, 1));
+ __ strb(r14, __ post(dst, 1));
+ __ strb(r13, __ post(dst, 1));
+ __ strb(r12, __ post(dst, 1));
+ __ sub(length, length, 3);
+ __ cbnz(length, Process3B);
+
+ __ BIND(Exit);
+ __ ret(lr);
+
+ return start;
+ }
+
// Continuation point for throwing of implicit exceptions that are
// not handled in the current activation. Fabricates an exception
// oop and initiates normal exception dispatching in this
@@ -4851,42 +5426,42 @@
// Register allocation
- Register reg = c_rarg0;
- Pa_base = reg; // Argument registers
+ RegSetIterator regs = (RegSet::range(r0, r26) - r18_tls).begin();
+ Pa_base = *regs; // Argument registers
if (squaring)
Pb_base = Pa_base;
else
- Pb_base = ++reg;
- Pn_base = ++reg;
- Rlen= ++reg;
- inv = ++reg;
- Pm_base = ++reg;
+ Pb_base = *++regs;
+ Pn_base = *++regs;
+ Rlen= *++regs;
+ inv = *++regs;
+ Pm_base = *++regs;
// Working registers:
- Ra = ++reg; // The current digit of a, b, n, and m.
- Rb = ++reg;
- Rm = ++reg;
- Rn = ++reg;
-
- Pa = ++reg; // Pointers to the current/next digit of a, b, n, and m.
- Pb = ++reg;
- Pm = ++reg;
- Pn = ++reg;
-
- t0 = ++reg; // Three registers which form a
- t1 = ++reg; // triple-precision accumuator.
- t2 = ++reg;
-
- Ri = ++reg; // Inner and outer loop indexes.
- Rj = ++reg;
-
- Rhi_ab = ++reg; // Product registers: low and high parts
- Rlo_ab = ++reg; // of a*b and m*n.
- Rhi_mn = ++reg;
- Rlo_mn = ++reg;
+ Ra = *++regs; // The current digit of a, b, n, and m.
+ Rb = *++regs;
+ Rm = *++regs;
+ Rn = *++regs;
+
+ Pa = *++regs; // Pointers to the current/next digit of a, b, n, and m.
+ Pb = *++regs;
+ Pm = *++regs;
+ Pn = *++regs;
+
+ t0 = *++regs; // Three registers which form a
+ t1 = *++regs; // triple-precision accumuator.
+ t2 = *++regs;
+
+ Ri = *++regs; // Inner and outer loop indexes.
+ Rj = *++regs;
+
+ Rhi_ab = *++regs; // Product registers: low and high parts
+ Rlo_ab = *++regs; // of a*b and m*n.
+ Rhi_mn = *++regs;
+ Rlo_mn = *++regs;
// r19 and up are callee-saved.
- _toSave = RegSet::range(r19, reg) + Pm_base;
+ _toSave = RegSet::range(r19, *regs) + Pm_base;
}
private:
@@ -5342,12 +5917,12 @@
// In C, approximately:
// void
- // montgomery_multiply(unsigned long Pa_base[], unsigned long Pb_base[],
- // unsigned long Pn_base[], unsigned long Pm_base[],
- // unsigned long inv, int len) {
- // unsigned long t0 = 0, t1 = 0, t2 = 0; // Triple-precision accumulator
- // unsigned long *Pa, *Pb, *Pn, *Pm;
- // unsigned long Ra, Rb, Rn, Rm;
+ // montgomery_multiply(julong Pa_base[], julong Pb_base[],
+ // julong Pn_base[], julong Pm_base[],
+ // julong inv, int len) {
+ // julong t0 = 0, t1 = 0, t2 = 0; // Triple-precision accumulator
+ // julong *Pa, *Pb, *Pn, *Pm;
+ // julong Ra, Rb, Rn, Rm;
// int i;
@@ -5555,11 +6130,12 @@
// In C, approximately:
// void
- // montgomery_square(unsigned long Pa_base[], unsigned long Pn_base[],
- // unsigned long Pm_base[], unsigned long inv, int len) {
- // unsigned long t0 = 0, t1 = 0, t2 = 0; // Triple-precision accumulator
- // unsigned long *Pa, *Pb, *Pn, *Pm;
- // unsigned long Ra, Rb, Rn, Rm;
+ // montgomery_multiply(julong Pa_base[], julong Pb_base[],
+ // julong Pn_base[], julong Pm_base[],
+ // julong inv, int len) {
+ // julong t0 = 0, t1 = 0, t2 = 0; // Triple-precision accumulator
+ // julong *Pa, *Pb, *Pn, *Pm;
+ // julong Ra, Rb, Rn, Rm;
// int i;
@@ -5752,6 +6328,7 @@
// byte_array_inflate stub for large arrays.
StubRoutines::aarch64::_large_byte_array_inflate = generate_large_byte_array_inflate();
+#ifdef COMPILER2
if (UseMultiplyToLenIntrinsic) {
StubRoutines::_multiplyToLen = generate_multiplyToLen();
}
@@ -5777,10 +6354,19 @@
// because it's faster for the sizes of modulus we care about.
StubRoutines::_montgomerySquare = g.generate_multiply();
}
+#endif // COMPILER2
// generate GHASH intrinsics code
if (UseGHASHIntrinsics) {
- StubRoutines::_ghash_processBlocks = generate_ghash_processBlocks();
+ if (UseAESCTRIntrinsics) {
+ StubRoutines::_ghash_processBlocks = generate_ghash_processBlocks_wide();
+ } else {
+ StubRoutines::_ghash_processBlocks = generate_ghash_processBlocks();
+ }
+ }
+
+ if (UseBASE64Intrinsics) {
+ StubRoutines::_base64_encodeBlock = generate_base64_encodeBlock();
}
if (UseAESIntrinsics) {
@@ -5790,6 +6376,10 @@
StubRoutines::_cipherBlockChaining_decryptAESCrypt = generate_cipherBlockChaining_decryptAESCrypt();
}
+ if (UseAESCTRIntrinsics) {
+ StubRoutines::_counterMode_AESCrypt = generate_counterMode_AESCrypt();
+ }
+
if (UseSHA1Intrinsics) {
StubRoutines::_sha1_implCompress = generate_sha1_implCompress(false, "sha1_implCompress");
StubRoutines::_sha1_implCompressMB = generate_sha1_implCompress(true, "sha1_implCompressMB");
@@ -5811,7 +6401,13 @@
generate_safefetch("SafeFetchN", sizeof(intptr_t), &StubRoutines::_safefetchN_entry,
&StubRoutines::_safefetchN_fault_pc,
&StubRoutines::_safefetchN_continuation_pc);
- StubRoutines::aarch64::set_completed();
+#ifdef LINUX
+
+ generate_atomic_entry_points();
+
+#endif // LINUX
+
+ StubRoutines::aarch64::set_completed();
}
public:
@@ -5827,3 +6423,30 @@
void StubGenerator_generate(CodeBuffer* code, bool all) {
StubGenerator g(code, all);
}
+
+
+#ifdef LINUX
+
+// Define pointers to atomic stubs and initialize them to point to the
+// code in atomic_aarch64.S.
+
+#define DEFAULT_ATOMIC_OP(OPNAME, SIZE, RELAXED) \
+ extern "C" uint64_t aarch64_atomic_ ## OPNAME ## _ ## SIZE ## RELAXED ## _default_impl \
+ (volatile void *ptr, uint64_t arg1, uint64_t arg2); \
+ aarch64_atomic_stub_t aarch64_atomic_ ## OPNAME ## _ ## SIZE ## RELAXED ## _impl \
+ = aarch64_atomic_ ## OPNAME ## _ ## SIZE ## RELAXED ## _default_impl;
+
+DEFAULT_ATOMIC_OP(fetch_add, 4, )
+DEFAULT_ATOMIC_OP(fetch_add, 8, )
+DEFAULT_ATOMIC_OP(xchg, 4, )
+DEFAULT_ATOMIC_OP(xchg, 8, )
+DEFAULT_ATOMIC_OP(cmpxchg, 1, )
+DEFAULT_ATOMIC_OP(cmpxchg, 4, )
+DEFAULT_ATOMIC_OP(cmpxchg, 8, )
+DEFAULT_ATOMIC_OP(cmpxchg, 1, _relaxed)
+DEFAULT_ATOMIC_OP(cmpxchg, 4, _relaxed)
+DEFAULT_ATOMIC_OP(cmpxchg, 8, _relaxed)
+
+#undef DEFAULT_ATOMIC_OP
+
+#endif // LINUX
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/stubRoutines_aarch64.cpp openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/stubRoutines_aarch64.cpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/stubRoutines_aarch64.cpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/stubRoutines_aarch64.cpp 2022-01-13 21:56:25.000000000 +0000
@@ -61,7 +61,7 @@
/**
* crc_table[] from jdk/src/share/native/java/util/zip/zlib-1.2.5/crc32.h
*/
-juint StubRoutines::aarch64::_crc_table[] ATTRIBUTE_ALIGNED(4096) =
+ATTRIBUTE_ALIGNED(4096) juint StubRoutines::aarch64::_crc_table[] =
{
// Table 0
0x00000000UL, 0x77073096UL, 0xee0e612cUL, 0x990951baUL, 0x076dc419UL,
@@ -287,7 +287,12 @@
0xD502ED78UL, 0xAE7D62EDUL, // byte swap of word swap
};
-juint StubRoutines::aarch64::_npio2_hw[] __attribute__ ((aligned(64))) = {
+// Accumulation coefficients for adler32 upper 16 bits
+ATTRIBUTE_ALIGNED(64) jubyte StubRoutines::aarch64::_adler_table[] = {
+ 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1
+};
+
+ATTRIBUTE_ALIGNED(64) juint StubRoutines::aarch64::_npio2_hw[] = {
// first, various coefficient values: 0.5, invpio2, pio2_1, pio2_1t, pio2_2,
// pio2_2t, pio2_3, pio2_3t
// This is a small optimization wich keeping double[8] values in int[] table
@@ -319,7 +324,7 @@
// Coefficients for sin(x) polynomial approximation: S1..S6.
// See kernel_sin comments in macroAssembler_aarch64_trig.cpp for details
-jdouble StubRoutines::aarch64::_dsin_coef[] __attribute__ ((aligned(64))) = {
+ATTRIBUTE_ALIGNED(64) jdouble StubRoutines::aarch64::_dsin_coef[] = {
-1.66666666666666324348e-01, // 0xBFC5555555555549
8.33333333332248946124e-03, // 0x3F8111111110F8A6
-1.98412698298579493134e-04, // 0xBF2A01A019C161D5
@@ -330,7 +335,7 @@
// Coefficients for cos(x) polynomial approximation: C1..C6.
// See kernel_cos comments in macroAssembler_aarch64_trig.cpp for details
-jdouble StubRoutines::aarch64::_dcos_coef[] __attribute__ ((aligned(64))) = {
+ATTRIBUTE_ALIGNED(64) jdouble StubRoutines::aarch64::_dcos_coef[] = {
4.16666666666666019037e-02, // c0x3FA555555555554C
-1.38888888888741095749e-03, // 0xBF56C16C16C15177
2.48015872894767294178e-05, // 0x3EFA01A019CB1590
@@ -345,7 +350,7 @@
// Converted to double to avoid unnecessary conversion in code
// NOTE: table looks like original int table: {0xA2F983, 0x6E4E44,...} with
// only (double) conversion added
-jdouble StubRoutines::aarch64::_two_over_pi[] __attribute__ ((aligned(64))) = {
+ATTRIBUTE_ALIGNED(64) jdouble StubRoutines::aarch64::_two_over_pi[] = {
(double)0xA2F983, (double)0x6E4E44, (double)0x1529FC, (double)0x2757D1, (double)0xF534DD, (double)0xC0DB62,
(double)0x95993C, (double)0x439041, (double)0xFE5163, (double)0xABDEBB, (double)0xC561B7, (double)0x246E3A,
(double)0x424DD2, (double)0xE00649, (double)0x2EEA09, (double)0xD1921C, (double)0xFE1DEB, (double)0x1CB129,
@@ -360,7 +365,7 @@
};
// Pi over 2 value
-jdouble StubRoutines::aarch64::_pio2[] __attribute__ ((aligned(64))) = {
+ATTRIBUTE_ALIGNED(64) jdouble StubRoutines::aarch64::_pio2[] = {
1.57079625129699707031e+00, // 0x3FF921FB40000000
7.54978941586159635335e-08, // 0x3E74442D00000000
5.39030252995776476554e-15, // 0x3CF8469880000000
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/stubRoutines_aarch64.hpp openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/stubRoutines_aarch64.hpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/stubRoutines_aarch64.hpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/stubRoutines_aarch64.hpp 2022-01-13 21:56:25.000000000 +0000
@@ -36,7 +36,7 @@
enum platform_dependent_constants {
code_size1 = 19000, // simply increase if too small (assembler will crash if too small)
- code_size2 = 28000 // simply increase if too small (assembler will crash if too small)
+ code_size2 = 32000 // simply increase if too small (assembler will crash if too small)
};
class aarch64 {
@@ -181,6 +181,7 @@
private:
static juint _crc_table[];
+ static jubyte _adler_table[];
// begin trigonometric tables block. See comments in .cpp file
static juint _npio2_hw[];
static jdouble _two_over_pi[];
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/templateInterpreterGenerator_aarch64.cpp openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/templateInterpreterGenerator_aarch64.cpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/templateInterpreterGenerator_aarch64.cpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/templateInterpreterGenerator_aarch64.cpp 2022-01-13 21:56:25.000000000 +0000
@@ -1,6 +1,6 @@
/*
- * Copyright (c) 2003, 2019, Oracle and/or its affiliates. All rights reserved.
- * Copyright (c) 2014, 2019, Red Hat Inc. All rights reserved.
+ * Copyright (c) 2003, 2020, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@@ -1003,7 +1003,7 @@
__ ldrw(val, Address(esp, 0)); // byte value
__ ldrw(crc, Address(esp, wordSize)); // Initial CRC
- unsigned long offset;
+ uint64_t offset;
__ adrp(tbl, ExternalAddress(StubRoutines::crc_table_addr()), offset);
__ add(tbl, tbl, offset);
@@ -1593,24 +1593,30 @@
__ add(rlocals, esp, r2, ext::uxtx, 3);
__ sub(rlocals, rlocals, wordSize);
- // Make room for locals
- __ sub(rscratch1, esp, r3, ext::uxtx, 3);
- __ andr(sp, rscratch1, -16);
+ __ mov(rscratch1, esp);
// r3 - # of additional locals
// allocate space for locals
// explicitly initialize locals
+ // Initializing memory allocated for locals in the same direction as
+ // the stack grows to ensure page initialization order according
+ // to windows-aarch64 stack page growth requirement (see
+ // https://docs.microsoft.com/en-us/cpp/build/arm64-windows-abi-conventions?view=msvc-160#stack)
{
Label exit, loop;
__ ands(zr, r3, r3);
__ br(Assembler::LE, exit); // do nothing if r3 <= 0
__ bind(loop);
- __ str(zr, Address(__ post(rscratch1, wordSize)));
+ __ str(zr, Address(__ pre(rscratch1, -wordSize)));
__ sub(r3, r3, 1); // until everything initialized
__ cbnz(r3, loop);
__ bind(exit);
}
+ // Padding between locals and fixed part of activation frame to ensure
+ // SP is always 16-byte aligned.
+ __ andr(sp, rscratch1, -16);
+
// And the base dispatch table
__ get_dispatch();
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/templateTable_aarch64.cpp openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/templateTable_aarch64.cpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/templateTable_aarch64.cpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/templateTable_aarch64.cpp 2022-01-13 21:56:25.000000000 +0000
@@ -1705,7 +1705,7 @@
Label done;
__ pop_l(r1);
__ cmp(r1, r0);
- __ mov(r0, (u_int64_t)-1L);
+ __ mov(r0, (uint64_t)-1L);
__ br(Assembler::LT, done);
// __ mov(r0, 1UL);
// __ csel(r0, r0, zr, Assembler::NE);
@@ -1729,7 +1729,7 @@
if (unordered_result < 0) {
// we want -1 for unordered or less than, 0 for equal and 1 for
// greater than.
- __ mov(r0, (u_int64_t)-1L);
+ __ mov(r0, (uint64_t)-1L);
// for FP LT tests less than or unordered
__ br(Assembler::LT, done);
// install 0 for EQ otherwise 1
@@ -1910,7 +1910,7 @@
__ dispatch_only(vtos, /*generate_poll*/true);
if (UseLoopCounter) {
- if (ProfileInterpreter) {
+ if (ProfileInterpreter && !TieredCompilation) {
// Out-of-line code to allocate method data oop.
__ bind(profile_method);
__ call_VM(noreg, CAST_FROM_FN_PTR(address, InterpreterRuntime::profile_method));
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/vmreg_aarch64.cpp openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/vmreg_aarch64.cpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/vmreg_aarch64.cpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/vmreg_aarch64.cpp 2022-01-13 21:56:25.000000000 +0000
@@ -33,15 +33,17 @@
Register reg = ::as_Register(0);
int i;
for (i = 0; i < ConcreteRegisterImpl::max_gpr ; ) {
- regName[i++] = reg->name();
- regName[i++] = reg->name();
+ for (int j = 0 ; j < RegisterImpl::max_slots_per_register ; j++) {
+ regName[i++] = reg->name();
+ }
reg = reg->successor();
}
FloatRegister freg = ::as_FloatRegister(0);
for ( ; i < ConcreteRegisterImpl::max_fpr ; ) {
- regName[i++] = freg->name();
- regName[i++] = freg->name();
+ for (int j = 0 ; j < FloatRegisterImpl::max_slots_per_register ; j++) {
+ regName[i++] = freg->name();
+ }
freg = freg->successor();
}
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/vmreg_aarch64.hpp openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/vmreg_aarch64.hpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/vmreg_aarch64.hpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/vmreg_aarch64.hpp 2022-01-13 21:56:25.000000000 +0000
@@ -38,13 +38,14 @@
assert( is_Register(), "must be");
// Yuk
- return ::as_Register(value() >> 1);
+ return ::as_Register(value() / RegisterImpl::max_slots_per_register);
}
inline FloatRegister as_FloatRegister() {
assert( is_FloatRegister() && is_even(value()), "must be" );
// Yuk
- return ::as_FloatRegister((value() - ConcreteRegisterImpl::max_gpr) >> 1);
+ return ::as_FloatRegister((value() - ConcreteRegisterImpl::max_gpr) /
+ FloatRegisterImpl::max_slots_per_register);
}
inline bool is_concrete() {
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/vmreg_aarch64.inline.hpp openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/vmreg_aarch64.inline.hpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/vmreg_aarch64.inline.hpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/vmreg_aarch64.inline.hpp 2022-01-13 21:56:25.000000000 +0000
@@ -28,11 +28,12 @@
inline VMReg RegisterImpl::as_VMReg() {
if( this==noreg ) return VMRegImpl::Bad();
- return VMRegImpl::as_VMReg(encoding() << 1 );
+ return VMRegImpl::as_VMReg(encoding() * RegisterImpl::max_slots_per_register);
}
inline VMReg FloatRegisterImpl::as_VMReg() {
- return VMRegImpl::as_VMReg((encoding() << 1) + ConcreteRegisterImpl::max_gpr);
+ return VMRegImpl::as_VMReg((encoding() * FloatRegisterImpl::max_slots_per_register) +
+ ConcreteRegisterImpl::max_gpr);
}
#endif // CPU_AARCH64_VM_VMREG_AARCH64_INLINE_HPP
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/vm_version_aarch64.cpp openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/vm_version_aarch64.cpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/vm_version_aarch64.cpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/vm_version_aarch64.cpp 2022-01-13 21:56:25.000000000 +0000
@@ -24,100 +24,35 @@
*/
#include "precompiled.hpp"
-#include "asm/macroAssembler.hpp"
-#include "asm/macroAssembler.inline.hpp"
-#include "memory/resourceArea.hpp"
+#include "runtime/arguments.hpp"
+#include "runtime/globals_extension.hpp"
#include "runtime/java.hpp"
-#include "runtime/stubCodeGenerator.hpp"
+#include "runtime/os.hpp"
+#include "runtime/vm_version.hpp"
+#include "utilities/formatBuffer.hpp"
#include "utilities/macros.hpp"
-#include "vm_version_aarch64.hpp"
#include OS_HEADER_INLINE(os)
-#include
-#include
-
-#ifndef HWCAP_AES
-#define HWCAP_AES (1<<3)
-#endif
-
-#ifndef HWCAP_PMULL
-#define HWCAP_PMULL (1<<4)
-#endif
-
-#ifndef HWCAP_SHA1
-#define HWCAP_SHA1 (1<<5)
-#endif
-
-#ifndef HWCAP_SHA2
-#define HWCAP_SHA2 (1<<6)
-#endif
-
-#ifndef HWCAP_CRC32
-#define HWCAP_CRC32 (1<<7)
-#endif
-
-#ifndef HWCAP_ATOMICS
-#define HWCAP_ATOMICS (1<<8)
-#endif
-
int VM_Version::_cpu;
int VM_Version::_model;
int VM_Version::_model2;
int VM_Version::_variant;
int VM_Version::_revision;
int VM_Version::_stepping;
-VM_Version::PsrInfo VM_Version::_psr_info = { 0, };
-
-static BufferBlob* stub_blob;
-static const int stub_size = 550;
-
-extern "C" {
- typedef void (*getPsrInfo_stub_t)(void*);
-}
-static getPsrInfo_stub_t getPsrInfo_stub = NULL;
-
-
-class VM_Version_StubGenerator: public StubCodeGenerator {
- public:
- VM_Version_StubGenerator(CodeBuffer *c) : StubCodeGenerator(c) {}
+int VM_Version::_zva_length;
+int VM_Version::_dcache_line_size;
+int VM_Version::_icache_line_size;
- address generate_getPsrInfo() {
- StubCodeMark mark(this, "VM_Version", "getPsrInfo_stub");
-# define __ _masm->
- address start = __ pc();
-
- // void getPsrInfo(VM_Version::PsrInfo* psr_info);
-
- address entry = __ pc();
-
- __ enter();
-
- __ get_dczid_el0(rscratch1);
- __ strw(rscratch1, Address(c_rarg0, in_bytes(VM_Version::dczid_el0_offset())));
-
- __ get_ctr_el0(rscratch1);
- __ strw(rscratch1, Address(c_rarg0, in_bytes(VM_Version::ctr_el0_offset())));
-
- __ leave();
- __ ret(lr);
-
-# undef __
-
- return start;
- }
-};
-
-
-void VM_Version::get_processor_features() {
+void VM_Version::initialize() {
_supports_cx8 = true;
_supports_atomic_getset4 = true;
_supports_atomic_getadd4 = true;
_supports_atomic_getset8 = true;
_supports_atomic_getadd8 = true;
- getPsrInfo_stub(&_psr_info);
+ get_os_cpu_info();
int dcache_line = VM_Version::dcache_line_size();
@@ -159,32 +94,8 @@
SoftwarePrefetchHintDistance &= ~7;
}
- unsigned long auxv = getauxval(AT_HWCAP);
-
- char buf[512];
-
- _features = auxv;
-
- int cpu_lines = 0;
- if (FILE *f = fopen("/proc/cpuinfo", "r")) {
- char buf[128], *p;
- while (fgets(buf, sizeof (buf), f) != NULL) {
- if ((p = strchr(buf, ':')) != NULL) {
- long v = strtol(p+1, NULL, 0);
- if (strncmp(buf, "CPU implementer", sizeof "CPU implementer" - 1) == 0) {
- _cpu = v;
- cpu_lines++;
- } else if (strncmp(buf, "CPU variant", sizeof "CPU variant" - 1) == 0) {
- _variant = v;
- } else if (strncmp(buf, "CPU part", sizeof "CPU part" - 1) == 0) {
- if (_model != v) _model2 = _model;
- _model = v;
- } else if (strncmp(buf, "CPU revision", sizeof "CPU revision" - 1) == 0) {
- _revision = v;
- }
- }
- }
- fclose(f);
+ if (FLAG_IS_DEFAULT(ContendedPaddingWidth) && (dcache_line > ContendedPaddingWidth)) {
+ ContendedPaddingWidth = dcache_line;
}
// Enable vendor specific features
@@ -212,9 +123,11 @@
if (FLAG_IS_DEFAULT(UseSIMDForMemoryOps)) {
FLAG_SET_DEFAULT(UseSIMDForMemoryOps, true);
}
+#ifdef COMPILER2
if (FLAG_IS_DEFAULT(UseFPUForSpilling)) {
FLAG_SET_DEFAULT(UseFPUForSpilling, true);
}
+#endif
}
// Cortex A53
@@ -243,28 +156,35 @@
}
}
+ if (_cpu == CPU_ARM) {
+ if (FLAG_IS_DEFAULT(UseSignumIntrinsic)) {
+ FLAG_SET_DEFAULT(UseSignumIntrinsic, true);
+ }
+ }
+
if (_cpu == CPU_ARM && (_model == 0xd07 || _model2 == 0xd07)) _features |= CPU_STXR_PREFETCH;
- // If an olde style /proc/cpuinfo (cpu_lines == 1) then if _model is an A57 (0xd07)
+ // If an olde style /proc/cpuinfo (cores == 1) then if _model is an A57 (0xd07)
// we assume the worst and assume we could be on a big little system and have
// undisclosed A53 cores which we could be swapped to at any stage
- if (_cpu == CPU_ARM && cpu_lines == 1 && _model == 0xd07) _features |= CPU_A53MAC;
+ if (_cpu == CPU_ARM && os::processor_count() == 1 && _model == 0xd07) _features |= CPU_A53MAC;
+ char buf[512];
sprintf(buf, "0x%02x:0x%x:0x%03x:%d", _cpu, _variant, _model, _revision);
if (_model2) sprintf(buf+strlen(buf), "(0x%03x)", _model2);
- if (auxv & HWCAP_ASIMD) strcat(buf, ", simd");
- if (auxv & HWCAP_CRC32) strcat(buf, ", crc");
- if (auxv & HWCAP_AES) strcat(buf, ", aes");
- if (auxv & HWCAP_SHA1) strcat(buf, ", sha1");
- if (auxv & HWCAP_SHA2) strcat(buf, ", sha256");
- if (auxv & HWCAP_ATOMICS) strcat(buf, ", lse");
+ if (_features & CPU_ASIMD) strcat(buf, ", simd");
+ if (_features & CPU_CRC32) strcat(buf, ", crc");
+ if (_features & CPU_AES) strcat(buf, ", aes");
+ if (_features & CPU_SHA1) strcat(buf, ", sha1");
+ if (_features & CPU_SHA2) strcat(buf, ", sha256");
+ if (_features & CPU_LSE) strcat(buf, ", lse");
_features_string = os::strdup(buf);
if (FLAG_IS_DEFAULT(UseCRC32)) {
- UseCRC32 = (auxv & HWCAP_CRC32) != 0;
+ UseCRC32 = (_features & CPU_CRC32) != 0;
}
- if (UseCRC32 && (auxv & HWCAP_CRC32) == 0) {
+ if (UseCRC32 && (_features & CPU_CRC32) == 0) {
warning("UseCRC32 specified, but not supported on this CPU");
FLAG_SET_DEFAULT(UseCRC32, false);
}
@@ -278,7 +198,7 @@
FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false);
}
- if (auxv & HWCAP_ATOMICS) {
+ if (_features & CPU_LSE) {
if (FLAG_IS_DEFAULT(UseLSE))
FLAG_SET_DEFAULT(UseLSE, true);
} else {
@@ -288,7 +208,7 @@
}
}
- if (auxv & HWCAP_AES) {
+ if (_features & CPU_AES) {
UseAES = UseAES || FLAG_IS_DEFAULT(UseAES);
UseAESIntrinsics =
UseAESIntrinsics || (UseAES && FLAG_IS_DEFAULT(UseAESIntrinsics));
@@ -296,6 +216,9 @@
warning("UseAESIntrinsics enabled, but UseAES not, enabling");
UseAES = true;
}
+ if (FLAG_IS_DEFAULT(UseAESCTRIntrinsics)) {
+ FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
+ }
} else {
if (UseAES) {
warning("AES instructions are not available on this CPU");
@@ -305,18 +228,17 @@
warning("AES intrinsics are not available on this CPU");
FLAG_SET_DEFAULT(UseAESIntrinsics, false);
}
- }
-
- if (UseAESCTRIntrinsics) {
- warning("AES/CTR intrinsics are not available on this CPU");
- FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
+ if (UseAESCTRIntrinsics) {
+ warning("AES/CTR intrinsics are not available on this CPU");
+ FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
+ }
}
if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
UseCRC32Intrinsics = true;
}
- if (auxv & HWCAP_CRC32) {
+ if (_features & CPU_CRC32) {
if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
FLAG_SET_DEFAULT(UseCRC32CIntrinsics, true);
}
@@ -329,7 +251,7 @@
FLAG_SET_DEFAULT(UseFMA, true);
}
- if (auxv & (HWCAP_SHA1 | HWCAP_SHA2)) {
+ if (_features & (CPU_SHA1 | CPU_SHA2)) {
if (FLAG_IS_DEFAULT(UseSHA)) {
FLAG_SET_DEFAULT(UseSHA, true);
}
@@ -338,7 +260,7 @@
FLAG_SET_DEFAULT(UseSHA, false);
}
- if (UseSHA && (auxv & HWCAP_SHA1)) {
+ if (UseSHA && (_features & CPU_SHA1)) {
if (FLAG_IS_DEFAULT(UseSHA1Intrinsics)) {
FLAG_SET_DEFAULT(UseSHA1Intrinsics, true);
}
@@ -347,7 +269,7 @@
FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
}
- if (UseSHA && (auxv & HWCAP_SHA2)) {
+ if (UseSHA && (_features & CPU_SHA2)) {
if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) {
FLAG_SET_DEFAULT(UseSHA256Intrinsics, true);
}
@@ -365,7 +287,7 @@
FLAG_SET_DEFAULT(UseSHA, false);
}
- if (auxv & HWCAP_PMULL) {
+ if (_features & CPU_PMULL) {
if (FLAG_IS_DEFAULT(UseGHASHIntrinsics)) {
FLAG_SET_DEFAULT(UseGHASHIntrinsics, true);
}
@@ -374,6 +296,10 @@
FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
}
+ if (FLAG_IS_DEFAULT(UseBASE64Intrinsics)) {
+ UseBASE64Intrinsics = true;
+ }
+
if (is_zva_enabled()) {
if (FLAG_IS_DEFAULT(UseBlockZeroing)) {
FLAG_SET_DEFAULT(UseBlockZeroing, true);
@@ -391,6 +317,15 @@
FLAG_SET_DEFAULT(UseUnalignedAccesses, true);
}
+ if (FLAG_IS_DEFAULT(UseBarriersForVolatile)) {
+ UseBarriersForVolatile = (_features & CPU_DMB_ATOMICS) != 0;
+ }
+
+ if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
+ UsePopCountInstruction = true;
+ }
+
+#ifdef COMPILER2
if (FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
UseMultiplyToLenIntrinsic = true;
}
@@ -403,14 +338,6 @@
UseMulAddIntrinsic = true;
}
- if (FLAG_IS_DEFAULT(UseBarriersForVolatile)) {
- UseBarriersForVolatile = (_features & CPU_DMB_ATOMICS) != 0;
- }
-
- if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
- UsePopCountInstruction = true;
- }
-
if (FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) {
UseMontgomeryMultiplyIntrinsic = true;
}
@@ -418,27 +345,10 @@
UseMontgomerySquareIntrinsic = true;
}
-#ifdef COMPILER2
if (FLAG_IS_DEFAULT(OptoScheduling)) {
OptoScheduling = true;
}
#endif
-}
-
-void VM_Version::initialize() {
- ResourceMark rm;
-
- stub_blob = BufferBlob::create("getPsrInfo_stub", stub_size);
- if (stub_blob == NULL) {
- vm_exit_during_initialization("Unable to allocate getPsrInfo_stub");
- }
-
- CodeBuffer c(stub_blob);
- VM_Version_StubGenerator g(&c);
- getPsrInfo_stub = CAST_TO_FN_PTR(getPsrInfo_stub_t,
- g.generate_getPsrInfo());
-
- get_processor_features();
UNSUPPORTED_OPTION(CriticalJNINatives);
}
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/vm_version_aarch64.hpp openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/vm_version_aarch64.hpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/vm_version_aarch64.hpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/vm_version_aarch64.hpp 2022-01-13 21:56:25.000000000 +0000
@@ -26,8 +26,8 @@
#ifndef CPU_AARCH64_VM_VM_VERSION_AARCH64_HPP
#define CPU_AARCH64_VM_VM_VERSION_AARCH64_HPP
+#include "runtime/abstract_vm_version.hpp"
#include "runtime/globals_extension.hpp"
-#include "runtime/vm_version.hpp"
#include "utilities/sizes.hpp"
class VM_Version : public Abstract_VM_Version {
@@ -41,12 +41,12 @@
static int _revision;
static int _stepping;
- struct PsrInfo {
- uint32_t dczid_el0;
- uint32_t ctr_el0;
- };
- static PsrInfo _psr_info;
- static void get_processor_features();
+ static int _zva_length;
+ static int _dcache_line_size;
+ static int _icache_line_size;
+
+ // Read additional info using OS-specific interfaces
+ static void get_os_cpu_info();
public:
// Initialization
@@ -91,6 +91,7 @@
CPU_SHA2 = (1<<6),
CPU_CRC32 = (1<<7),
CPU_LSE = (1<<8),
+ // flags above must follow Linux HWCAP
CPU_STXR_PREFETCH= (1 << 29),
CPU_A53MAC = (1 << 30),
CPU_DMB_ATOMICS = (1 << 31),
@@ -101,24 +102,15 @@
static int cpu_model2() { return _model2; }
static int cpu_variant() { return _variant; }
static int cpu_revision() { return _revision; }
- static ByteSize dczid_el0_offset() { return byte_offset_of(PsrInfo, dczid_el0); }
- static ByteSize ctr_el0_offset() { return byte_offset_of(PsrInfo, ctr_el0); }
- static bool is_zva_enabled() {
- // Check the DZP bit (bit 4) of dczid_el0 is zero
- // and block size (bit 0~3) is not zero.
- return ((_psr_info.dczid_el0 & 0x10) == 0 &&
- (_psr_info.dczid_el0 & 0xf) != 0);
- }
+
+ static bool is_zva_enabled() { return 0 <= _zva_length; }
static int zva_length() {
assert(is_zva_enabled(), "ZVA not available");
- return 4 << (_psr_info.dczid_el0 & 0xf);
- }
- static int icache_line_size() {
- return (1 << (_psr_info.ctr_el0 & 0x0f)) * 4;
- }
- static int dcache_line_size() {
- return (1 << ((_psr_info.ctr_el0 >> 16) & 0x0f)) * 4;
+ return _zva_length;
}
+
+ static int icache_line_size() { return _icache_line_size; }
+ static int dcache_line_size() { return _dcache_line_size; }
};
#endif // CPU_AARCH64_VM_VM_VERSION_AARCH64_HPP
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/vm_version_ext_aarch64.cpp openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/vm_version_ext_aarch64.cpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/vm_version_ext_aarch64.cpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/vm_version_ext_aarch64.cpp 2022-01-13 21:56:25.000000000 +0000
@@ -22,6 +22,7 @@
*
*/
+#include "precompiled.hpp"
#include "memory/allocation.hpp"
#include "memory/allocation.inline.hpp"
#include "runtime/os.inline.hpp"
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/vm_version_ext_aarch64.hpp openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/vm_version_ext_aarch64.hpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/vm_version_ext_aarch64.hpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/vm_version_ext_aarch64.hpp 2022-01-13 21:56:25.000000000 +0000
@@ -25,8 +25,8 @@
#ifndef CPU_AARCH64_VM_VM_VERSION_EXT_AARCH64_HPP
#define CPU_AARCH64_VM_VM_VERSION_EXT_AARCH64_HPP
+#include "runtime/vm_version.hpp"
#include "utilities/macros.hpp"
-#include "vm_version_aarch64.hpp"
class VM_Version_Ext : public VM_Version {
private:
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/vtableStubs_aarch64.cpp openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/vtableStubs_aarch64.cpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/aarch64/vtableStubs_aarch64.cpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/aarch64/vtableStubs_aarch64.cpp 2022-01-13 21:56:25.000000000 +0000
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2003, 2018, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2003, 2021, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2014, Red Hat Inc. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
@@ -70,7 +70,7 @@
#if (!defined(PRODUCT) && defined(COMPILER2))
if (CountCompiledCalls) {
__ lea(r16, ExternalAddress((address) SharedRuntime::nof_megamorphic_calls_addr()));
- __ incrementw(Address(r16));
+ __ increment(Address(r16));
}
#endif
@@ -145,6 +145,7 @@
if (s == NULL) {
return NULL;
}
+
// Count unused bytes in instruction sequences of variable size.
// We add them to the computed buffer size in order to avoid
// overflow in subsequently generated stubs.
@@ -159,7 +160,7 @@
#if (!defined(PRODUCT) && defined(COMPILER2))
if (CountCompiledCalls) {
__ lea(r10, ExternalAddress((address) SharedRuntime::nof_megamorphic_calls_addr()));
- __ incrementw(Address(r10));
+ __ increment(Address(r10));
}
#endif
@@ -170,11 +171,13 @@
// rscratch2: CompiledICHolder
// j_rarg0: Receiver
- // Most registers are in use; we'll use r16, rmethod, r10, r11
+ // This stub is called from compiled code which has no callee-saved registers,
+ // so all registers except arguments are free at this point.
const Register recv_klass_reg = r10;
const Register holder_klass_reg = r16; // declaring interface klass (DECC)
const Register resolved_klass_reg = rmethod; // resolved interface klass (REFC)
const Register temp_reg = r11;
+ const Register temp_reg2 = r15;
const Register icholder_reg = rscratch2;
Label L_no_such_interface;
@@ -189,11 +192,10 @@
__ load_klass(recv_klass_reg, j_rarg0);
// Receiver subtype check against REFC.
- // Destroys recv_klass_reg value.
__ lookup_interface_method(// inputs: rec. class, interface
recv_klass_reg, resolved_klass_reg, noreg,
// outputs: scan temp. reg1, scan temp. reg2
- recv_klass_reg, temp_reg,
+ temp_reg2, temp_reg,
L_no_such_interface,
/*return_method=*/false);
@@ -201,7 +203,6 @@
start_pc = __ pc();
// Get selected method from declaring class and itable index
- __ load_klass(recv_klass_reg, j_rarg0); // restore recv_klass_reg
__ lookup_interface_method(// inputs: rec. class, interface, itable index
recv_klass_reg, holder_klass_reg, itable_index,
// outputs: method, scan temp. reg
@@ -211,7 +212,7 @@
const ptrdiff_t lookupSize = __ pc() - start_pc;
// Reduce "estimate" such that "padding" does not drop below 8.
- const ptrdiff_t estimate = 152;
+ const ptrdiff_t estimate = 124;
const ptrdiff_t codesize = typecheckSize + lookupSize;
slop_delta = (int)(estimate - codesize);
slop_bytes += slop_delta;
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/arm/arm.ad openjdk-lts-11.0.14+9/src/hotspot/cpu/arm/arm.ad
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/arm/arm.ad 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/arm/arm.ad 2022-01-13 21:56:25.000000000 +0000
@@ -12016,9 +12016,10 @@
#ifdef AARCH64
effect(TEMP scratch, TEMP scratch2, TEMP scratch3);
#else
+ predicate(!(UseBiasedLocking && !UseOptoBiasInlining));
effect(TEMP scratch, TEMP scratch2);
#endif
- ins_cost(100);
+ ins_cost(DEFAULT_COST*3);
#ifdef AARCH64
format %{ "FASTLOCK $object, $box; KILL $scratch, $scratch2, $scratch3" %}
@@ -12048,6 +12049,21 @@
ins_pipe(long_memory_op);
%}
#else
+instruct cmpFastLock_noBiasInline(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2,
+ iRegP scratch, iRegP scratch3) %{
+ match(Set pcc (FastLock object box));
+ predicate(UseBiasedLocking && !UseOptoBiasInlining);
+
+ effect(TEMP scratch, TEMP scratch2, TEMP scratch3);
+ ins_cost(DEFAULT_COST*5);
+
+ format %{ "FASTLOCK $object, $box; KILL $scratch, $scratch2, $scratch3" %}
+ ins_encode %{
+ __ fast_lock($object$$Register, $box$$Register, $scratch$$Register, $scratch2$$Register, $scratch3$$Register);
+ %}
+ ins_pipe(long_memory_op);
+%}
+
instruct cmpFastUnlock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, iRegP scratch ) %{
match(Set pcc (FastUnlock object box));
effect(TEMP scratch, TEMP scratch2);
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/arm/assembler_arm_32.hpp openjdk-lts-11.0.14+9/src/hotspot/cpu/arm/assembler_arm_32.hpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/arm/assembler_arm_32.hpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/arm/assembler_arm_32.hpp 2022-01-13 21:56:25.000000000 +0000
@@ -1083,6 +1083,7 @@
break;
default:
ShouldNotReachHere();
+ return;
}
emit_int32(0xf << 28 | 0x1 << 25 | 0x1 << 23 | 0x1 << 4 |
(imm8 >> 7) << 24 | ((imm8 & 0x70) >> 4) << 16 | (imm8 & 0xf) |
@@ -1113,6 +1114,7 @@
break;
default:
ShouldNotReachHere();
+ return;
}
emit_int32(cond << 28 | 0x1D /* 0b11101 */ << 23 | 0xB /* 0b1011 */ << 8 | 0x1 << 4 |
quad << 21 | b << 22 | e << 5 | Rs->encoding() << 12 |
@@ -1143,6 +1145,7 @@
break;
default:
ShouldNotReachHere();
+ return;
}
emit_int32(0xF /* 0b1111 */ << 28 | 0x3B /* 0b00111011 */ << 20 | 0x6 /* 0b110 */ << 9 |
quad << 6 | imm4 << 16 |
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/arm/c1_CodeStubs_arm.cpp openjdk-lts-11.0.14+9/src/hotspot/cpu/arm/c1_CodeStubs_arm.cpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/arm/c1_CodeStubs_arm.cpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/arm/c1_CodeStubs_arm.cpp 2022-01-13 21:56:25.000000000 +0000
@@ -52,13 +52,13 @@
RangeCheckStub::RangeCheckStub(CodeEmitInfo* info, LIR_Opr index, LIR_Opr array)
- : _throw_index_out_of_bounds_exception(false), _index(index), _array(array) {
+ : _index(index), _array(array), _throw_index_out_of_bounds_exception(false) {
assert(info != NULL, "must have info");
_info = new CodeEmitInfo(info);
}
RangeCheckStub::RangeCheckStub(CodeEmitInfo* info, LIR_Opr index)
- : _throw_index_out_of_bounds_exception(true), _index(index), _array(NULL) {
+ : _index(index), _array(NULL), _throw_index_out_of_bounds_exception(true) {
assert(info != NULL, "must have info");
_info = new CodeEmitInfo(info);
}
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/arm/c1_LIRAssembler_arm.cpp openjdk-lts-11.0.14+9/src/hotspot/cpu/arm/c1_LIRAssembler_arm.cpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/arm/c1_LIRAssembler_arm.cpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/arm/c1_LIRAssembler_arm.cpp 2022-01-13 21:56:25.000000000 +0000
@@ -3097,7 +3097,7 @@
Label ok;
if (op->condition() != lir_cond_always) {
- AsmCondition acond;
+ AsmCondition acond = al;
switch (op->condition()) {
case lir_cond_equal: acond = eq; break;
case lir_cond_notEqual: acond = ne; break;
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/arm/c1_LIRGenerator_arm.cpp openjdk-lts-11.0.14+9/src/hotspot/cpu/arm/c1_LIRGenerator_arm.cpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/arm/c1_LIRGenerator_arm.cpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/arm/c1_LIRGenerator_arm.cpp 2022-01-13 21:56:25.000000000 +0000
@@ -436,7 +436,7 @@
}
-bool LIRGenerator::strength_reduce_multiply(LIR_Opr left, int c, LIR_Opr result, LIR_Opr tmp) {
+bool LIRGenerator::strength_reduce_multiply(LIR_Opr left, jint c, LIR_Opr result, LIR_Opr tmp) {
assert(left != result, "should be different registers");
if (is_power_of_2(c + 1)) {
#ifdef AARCH64
@@ -733,6 +733,7 @@
default:
ShouldNotReachHere();
+ return;
}
#else
switch (x->op()) {
@@ -757,6 +758,7 @@
break;
default:
ShouldNotReachHere();
+ return;
}
LIR_Opr result = call_runtime(x->y(), x->x(), entry, x->type(), NULL);
set_result(x, result);
@@ -824,7 +826,7 @@
if (x->op() == Bytecodes::_irem) {
out_reg = FrameMap::R0_opr;
__ irem(left_arg->result(), right_arg->result(), out_reg, tmp, info);
- } else if (x->op() == Bytecodes::_idiv) {
+ } else { // (x->op() == Bytecodes::_idiv)
out_reg = FrameMap::R1_opr;
__ idiv(left_arg->result(), right_arg->result(), out_reg, tmp, info);
}
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/arm/c1_MacroAssembler_arm.cpp openjdk-lts-11.0.14+9/src/hotspot/cpu/arm/c1_MacroAssembler_arm.cpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/arm/c1_MacroAssembler_arm.cpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/arm/c1_MacroAssembler_arm.cpp 2022-01-13 21:56:25.000000000 +0000
@@ -323,8 +323,9 @@
// -2- test (hdr - SP) if the low two bits are 0
sub(tmp2, hdr, SP, eq);
movs(tmp2, AsmOperand(tmp2, lsr, exact_log2(os::vm_page_size())), eq);
- // If 'eq' then OK for recursive fast locking: store 0 into a lock record.
- str(tmp2, Address(disp_hdr, mark_offset), eq);
+ // If still 'eq' then recursive locking OK
+ // set to zero if recursive lock, set to non zero otherwise (see discussion in JDK-8267042)
+ str(tmp2, Address(disp_hdr, mark_offset));
b(fast_lock_done, eq);
// else need slow case
b(slow_case);
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/arm/c2_globals_arm.hpp openjdk-lts-11.0.14+9/src/hotspot/cpu/arm/c2_globals_arm.hpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/arm/c2_globals_arm.hpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/arm/c2_globals_arm.hpp 2022-01-13 21:56:25.000000000 +0000
@@ -109,7 +109,7 @@
// Ergonomics related flags
define_pd_global(uint64_t, MaxRAM, 4ULL*G);
#endif
-define_pd_global(uintx, CodeCacheMinBlockLength, 4);
+define_pd_global(uintx, CodeCacheMinBlockLength, 6);
define_pd_global(size_t, CodeCacheMinimumUseSpace, 400*K);
define_pd_global(bool, TrapBasedRangeChecks, false); // Not needed
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/arm/frame_arm.cpp openjdk-lts-11.0.14+9/src/hotspot/cpu/arm/frame_arm.cpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/arm/frame_arm.cpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/arm/frame_arm.cpp 2022-01-13 21:56:25.000000000 +0000
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2008, 2017, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2008, 2018, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@@ -500,7 +500,7 @@
Method* m = *interpreter_frame_method_addr();
// validate the method we'd find in this potential sender
- if (!m->is_valid_method()) return false;
+ if (!Method::is_valid_method(m)) return false;
// stack frames shouldn't be much larger than max_stack elements
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/arm/globalDefinitions_arm.hpp openjdk-lts-11.0.14+9/src/hotspot/cpu/arm/globalDefinitions_arm.hpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/arm/globalDefinitions_arm.hpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/arm/globalDefinitions_arm.hpp 2022-01-13 21:56:25.000000000 +0000
@@ -69,11 +69,4 @@
#endif
#define C1_LIRGENERATOR_MD_HPP "c1_LIRGenerator_arm.hpp"
-#ifdef TARGET_COMPILER_gcc
-#ifdef ARM32
-#undef BREAKPOINT
-#define BREAKPOINT __asm__ volatile ("bkpt")
-#endif
-#endif
-
#endif // CPU_ARM_VM_GLOBALDEFINITIONS_ARM_HPP
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/arm/interpreterRT_arm.cpp openjdk-lts-11.0.14+9/src/hotspot/cpu/arm/interpreterRT_arm.cpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/arm/interpreterRT_arm.cpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/arm/interpreterRT_arm.cpp 2022-01-13 21:56:25.000000000 +0000
@@ -86,11 +86,12 @@
// For ARM, the fast signature handler only needs to know whether
// the return value must be unboxed. T_OBJECT and T_ARRAY need not
// be distinguished from each other and all other return values
- // behave like integers with respect to the handler.
+ // behave like integers with respect to the handler except T_BOOLEAN
+ // which must be mapped to the range 0..1.
bool unbox = (ret_type == T_OBJECT) || (ret_type == T_ARRAY);
if (unbox) {
ret_type = T_OBJECT;
- } else {
+ } else if (ret_type != T_BOOLEAN) {
ret_type = T_INT;
}
result |= ((uint64_t) ret_type) << shift;
@@ -281,14 +282,7 @@
address result_handler = Interpreter::result_handler(result_type);
-#ifdef AARCH64
- __ mov_slow(R0, (address)result_handler);
-#else
- // Check that result handlers are not real handler on ARM (0 or -1).
- // This ensures the signature handlers do not need symbolic information.
- assert((result_handler == NULL)||(result_handler==(address)0xffffffff),"");
__ mov_slow(R0, (intptr_t)result_handler);
-#endif
__ ret();
}
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/arm/macroAssembler_arm.cpp openjdk-lts-11.0.14+9/src/hotspot/cpu/arm/macroAssembler_arm.cpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/arm/macroAssembler_arm.cpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/arm/macroAssembler_arm.cpp 2022-01-13 21:56:25.000000000 +0000
@@ -1229,6 +1229,15 @@
bind(done);
}
+void MacroAssembler::c2bool(Register x) {
+ tst(x, 0xff); // Only look at the lowest byte
+#ifdef AARCH64
+ cset(x, ne);
+#else
+ mov(x, 1, ne);
+#endif
+}
+
void MacroAssembler::null_check(Register reg, Register tmp, int offset) {
if (needs_explicit_null_check(offset)) {
#ifdef AARCH64
@@ -2987,7 +2996,7 @@
#endif // AARCH64
#ifdef COMPILER2
-void MacroAssembler::fast_lock(Register Roop, Register Rbox, Register Rscratch, Register Rscratch2 AARCH64_ONLY_ARG(Register Rscratch3))
+void MacroAssembler::fast_lock(Register Roop, Register Rbox, Register Rscratch, Register Rscratch2, Register scratch3)
{
assert(VM_Version::supports_ldrex(), "unsupported, yet?");
@@ -3001,15 +3010,13 @@
Label fast_lock, done;
if (UseBiasedLocking && !UseOptoBiasInlining) {
- Label failed;
-#ifdef AARCH64
- biased_locking_enter(Roop, Rmark, Rscratch, false, Rscratch3, done, failed);
-#else
- biased_locking_enter(Roop, Rmark, Rscratch, false, noreg, done, failed);
-#endif
- bind(failed);
+ assert(scratch3 != noreg, "need extra temporary for -XX:-UseOptoBiasInlining");
+ biased_locking_enter(Roop, Rmark, Rscratch, false, scratch3, done, done);
+ // Fall through if lock not biased otherwise branch to done
}
+ // Invariant: Rmark loaded below does not contain biased lock pattern
+
ldr(Rmark, Address(Roop, oopDesc::mark_offset_in_bytes()));
tst(Rmark, markOopDesc::unlocked_value);
b(fast_lock, ne);
@@ -3048,6 +3055,9 @@
bind(done);
+ // At this point flags are set as follows:
+ // EQ -> Success
+ // NE -> Failure, branch to slow path
}
void MacroAssembler::fast_unlock(Register Roop, Register Rbox, Register Rscratch, Register Rscratch2 AARCH64_ONLY_ARG(Register Rscratch3))
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/arm/macroAssembler_arm.hpp openjdk-lts-11.0.14+9/src/hotspot/cpu/arm/macroAssembler_arm.hpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/arm/macroAssembler_arm.hpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/arm/macroAssembler_arm.hpp 2022-01-13 21:56:25.000000000 +0000
@@ -376,10 +376,10 @@
// lock_reg and obj_reg must be loaded up with the appropriate values.
// swap_reg must be supplied.
// tmp_reg must be supplied.
- // Optional slow case is for implementations (interpreter and C1) which branch to
- // slow case directly. If slow_case is NULL, then leaves condition
- // codes set (for C2's Fast_Lock node) and jumps to done label.
- // Falls through for the fast locking attempt.
+ // Done label is branched to with condition code EQ set if the lock is
+ // biased and we acquired it. Slow case label is branched to with
+ // condition code NE set if the lock is biased but we failed to acquire
+ // it. Otherwise fall through.
// Returns offset of first potentially-faulting instruction for null
// check info (currently consumed only by C1). If
// swap_reg_contains_mark is true then returns -1 as it is assumed
@@ -1054,6 +1054,8 @@
#endif
}
+ // C 'boolean' to Java boolean: x == 0 ? 0 : 1
+ void c2bool(Register x);
// klass oop manipulations if compressed
@@ -1346,12 +1348,11 @@
void restore_default_fp_mode();
#ifdef COMPILER2
-#ifdef AARCH64
// Code used by cmpFastLock and cmpFastUnlock mach instructions in .ad file.
- void fast_lock(Register obj, Register box, Register scratch, Register scratch2, Register scratch3);
+ void fast_lock(Register obj, Register box, Register scratch, Register scratch2, Register scratch3 = noreg);
+#ifdef AARCH64
void fast_unlock(Register obj, Register box, Register scratch, Register scratch2, Register scratch3);
#else
- void fast_lock(Register obj, Register box, Register scratch, Register scratch2);
void fast_unlock(Register obj, Register box, Register scratch, Register scratch2);
#endif
#endif
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/arm/register_arm.hpp openjdk-lts-11.0.14+9/src/hotspot/cpu/arm/register_arm.hpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/arm/register_arm.hpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/arm/register_arm.hpp 2022-01-13 21:56:25.000000000 +0000
@@ -26,7 +26,7 @@
#define CPU_ARM_VM_REGISTER_ARM_HPP
#include "asm/register.hpp"
-#include "vm_version_arm.hpp"
+#include "runtime/vm_version.hpp"
class VMRegImpl;
typedef VMRegImpl* VMReg;
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/arm/sharedRuntime_arm.cpp openjdk-lts-11.0.14+9/src/hotspot/cpu/arm/sharedRuntime_arm.cpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/arm/sharedRuntime_arm.cpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/arm/sharedRuntime_arm.cpp 2022-01-13 21:56:25.000000000 +0000
@@ -1622,8 +1622,9 @@
// -2- test (hdr - SP) if the low two bits are 0
__ sub(Rtemp, mark, SP, eq);
__ movs(Rtemp, AsmOperand(Rtemp, lsr, exact_log2(os::vm_page_size())), eq);
- // If still 'eq' then recursive locking OK: set displaced header to 0
- __ str(Rtemp, Address(disp_hdr, BasicLock::displaced_header_offset_in_bytes()), eq);
+ // If still 'eq' then recursive locking OK
+ // set to zero if recursive lock, set to non zero otherwise (see discussion in JDK-8267042)
+ __ str(Rtemp, Address(disp_hdr, BasicLock::displaced_header_offset_in_bytes()));
__ b(lock_done, eq);
__ b(slow_lock);
@@ -1657,6 +1658,11 @@
__ restore_default_fp_mode();
}
+ // Ensure a Boolean result is mapped to 0..1
+ if (ret_type == T_BOOLEAN) {
+ __ c2bool(R0);
+ }
+
// Do a safepoint check while thread is in transition state
InlinedAddress safepoint_state(SafepointSynchronize::address_of_state());
Label call_safepoint_runtime, return_to_java;
@@ -2113,9 +2119,9 @@
__ mov(R0, Rthread);
__ mov(R1, Rkind);
- pc_offset = __ set_last_Java_frame(SP, FP, false, Rtemp);
+ pc_offset = __ set_last_Java_frame(SP, FP, true, Rtemp);
assert(((__ pc()) - start) == __ offset(), "warning: start differs from code_begin");
- __ call(CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames));
+ __ call_VM_leaf(CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames));
if (pc_offset == -1) {
pc_offset = __ offset();
}
@@ -2330,8 +2336,8 @@
// Call unpack_frames with proper arguments
__ mov(R0, Rthread);
__ mov(R1, Deoptimization::Unpack_uncommon_trap);
- __ set_last_Java_frame(SP, FP, false, Rtemp);
- __ call(CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames));
+ __ set_last_Java_frame(SP, FP, true, Rtemp);
+ __ call_VM_leaf(CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames));
// oop_maps->add_gc_map(__ pc() - start, new OopMap(frame_size_in_words, 0));
__ reset_last_Java_frame(Rtemp);
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/arm/templateInterpreterGenerator_arm.cpp openjdk-lts-11.0.14+9/src/hotspot/cpu/arm/templateInterpreterGenerator_arm.cpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/arm/templateInterpreterGenerator_arm.cpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/arm/templateInterpreterGenerator_arm.cpp 2022-01-13 21:56:25.000000000 +0000
@@ -351,16 +351,12 @@
}
address TemplateInterpreterGenerator::generate_result_handler_for(BasicType type) {
-#ifdef AARCH64
address entry = __ pc();
switch (type) {
- case T_BOOLEAN:
- __ tst(R0, 0xff);
- __ cset(R0, ne);
- break;
- case T_CHAR : __ zero_extend(R0, R0, 16); break;
- case T_BYTE : __ sign_extend(R0, R0, 8); break;
- case T_SHORT : __ sign_extend(R0, R0, 16); break;
+ case T_BOOLEAN: __ c2bool(R0); break;
+ case T_CHAR : AARCH64_ONLY(__ zero_extend(R0, R0, 16);) break;
+ case T_BYTE : AARCH64_ONLY(__ sign_extend(R0, R0, 8);) break;
+ case T_SHORT : AARCH64_ONLY(__ sign_extend(R0, R0, 16);) break;
case T_INT : // fall through
case T_LONG : // fall through
case T_VOID : // fall through
@@ -372,19 +368,10 @@
// and verify it
__ verify_oop(R0);
break;
- default : ShouldNotReachHere();
+ default : __ should_not_reach_here(); break;
}
__ ret();
return entry;
-#else
- // Result handlers are not used on 32-bit ARM
- // since the returned value is already in appropriate format.
- __ should_not_reach_here(); // to avoid empty code block
-
- // The result handler non-zero indicates an object is returned and this is
- // used in the native entry code.
- return type == T_OBJECT ? (address)(-1) : NULL;
-#endif // AARCH64
}
address TemplateInterpreterGenerator::generate_safept_entry_for(TosState state, address runtime_entry) {
@@ -1216,14 +1203,9 @@
// Unbox oop result, e.g. JNIHandles::resolve result if it's an oop.
{
Label Lnot_oop;
-#ifdef AARCH64
__ mov_slow(Rtemp, AbstractInterpreter::result_handler(T_OBJECT));
__ cmp(Rresult_handler, Rtemp);
__ b(Lnot_oop, ne);
-#else // !AARCH64
- // For ARM32, Rresult_handler is -1 for oop result, 0 otherwise.
- __ cbz(Rresult_handler, Lnot_oop);
-#endif // !AARCH64
Register value = AARCH64_ONLY(Rsaved_result) NOT_AARCH64(Rsaved_result_lo);
__ resolve_jobject(value, // value
Rtemp, // tmp1
@@ -1296,25 +1278,14 @@
__ blr(Rresult_handler);
#else
- __ cmp(Rresult_handler, 0);
- __ ldr(R0, Address(FP, frame::interpreter_frame_oop_temp_offset * wordSize), ne);
- __ mov(R0, Rsaved_result_lo, eq);
+ __ mov(R0, Rsaved_result_lo);
__ mov(R1, Rsaved_result_hi);
#ifdef __ABI_HARD__
// reload native FP result
__ fcpyd(D0, D8);
#endif // __ABI_HARD__
-
-#ifdef ASSERT
- if (VerifyOops) {
- Label L;
- __ cmp(Rresult_handler, 0);
- __ b(L, eq);
- __ verify_oop(R0);
- __ bind(L);
- }
-#endif // ASSERT
+ __ blx(Rresult_handler);
#endif // AARCH64
// Restore FP/LR, sender_sp and return
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/arm/templateTable_arm.cpp openjdk-lts-11.0.14+9/src/hotspot/cpu/arm/templateTable_arm.cpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/arm/templateTable_arm.cpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/arm/templateTable_arm.cpp 2022-01-13 21:56:25.000000000 +0000
@@ -2374,7 +2374,7 @@
const Address mask(Rcounters, in_bytes(MethodCounters::backedge_mask_offset()));
__ increment_mask_and_jump(Address(Rcounters, be_offset), increment, mask,
Rcnt, R4_tmp, eq, &backedge_counter_overflow);
- } else {
+ } else { // not TieredCompilation
// Increment backedge counter in MethodCounters*
__ get_method_counters(Rmethod, Rcounters, dispatch, true /*saveRegs*/,
Rdisp, R3_bytecode,
@@ -2447,7 +2447,7 @@
__ dispatch_only(vtos);
if (UseLoopCounter) {
- if (ProfileInterpreter) {
+ if (ProfileInterpreter && !TieredCompilation) {
// Out-of-line code to allocate method data oop.
__ bind(profile_method);
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/arm/vm_version_arm_32.cpp openjdk-lts-11.0.14+9/src/hotspot/cpu/arm/vm_version_arm_32.cpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/arm/vm_version_arm_32.cpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/arm/vm_version_arm_32.cpp 2022-01-13 21:56:25.000000000 +0000
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2008, 2018, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2008, 2019, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@@ -29,7 +29,7 @@
#include "runtime/java.hpp"
#include "runtime/os.inline.hpp"
#include "runtime/stubCodeGenerator.hpp"
-#include "vm_version_arm.hpp"
+#include "runtime/vm_version.hpp"
int VM_Version::_stored_pc_adjustment = 4;
int VM_Version::_arm_arch = 5;
@@ -296,6 +296,9 @@
Tier3MinInvocationThreshold = 500;
}
+ UNSUPPORTED_OPTION(TypeProfileLevel);
+ UNSUPPORTED_OPTION(CriticalJNINatives);
+
FLAG_SET_DEFAULT(TypeProfileLevel, 0); // unsupported
// This machine does not allow unaligned memory accesses
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/arm/vm_version_arm.hpp openjdk-lts-11.0.14+9/src/hotspot/cpu/arm/vm_version_arm.hpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/arm/vm_version_arm.hpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/arm/vm_version_arm.hpp 2022-01-13 21:56:25.000000000 +0000
@@ -25,8 +25,8 @@
#ifndef CPU_ARM_VM_VM_VERSION_ARM_HPP
#define CPU_ARM_VM_VM_VERSION_ARM_HPP
+#include "runtime/abstract_vm_version.hpp"
#include "runtime/globals_extension.hpp"
-#include "runtime/vm_version.hpp"
class VM_Version: public Abstract_VM_Version {
friend class JVMCIVMStructs;
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/arm/vm_version_ext_arm.hpp openjdk-lts-11.0.14+9/src/hotspot/cpu/arm/vm_version_ext_arm.hpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/arm/vm_version_ext_arm.hpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/arm/vm_version_ext_arm.hpp 2022-01-13 21:56:25.000000000 +0000
@@ -25,8 +25,8 @@
#ifndef CPU_ARM_VM_VM_VERSION_EXT_ARM_HPP
#define CPU_ARM_VM_VM_VERSION_EXT_ARM_HPP
+#include "runtime/vm_version.hpp"
#include "utilities/macros.hpp"
-#include "vm_version_arm.hpp"
class VM_Version_Ext : public VM_Version {
private:
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/ppc/c1_LIRGenerator_ppc.cpp openjdk-lts-11.0.14+9/src/hotspot/cpu/ppc/c1_LIRGenerator_ppc.cpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/ppc/c1_LIRGenerator_ppc.cpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/ppc/c1_LIRGenerator_ppc.cpp 2022-01-13 21:56:25.000000000 +0000
@@ -289,7 +289,7 @@
}
-bool LIRGenerator::strength_reduce_multiply(LIR_Opr left, int c, LIR_Opr result, LIR_Opr tmp) {
+bool LIRGenerator::strength_reduce_multiply(LIR_Opr left, jint c, LIR_Opr result, LIR_Opr tmp) {
assert(left != result, "should be different registers");
if (is_power_of_2(c + 1)) {
__ shift_left(left, log2_int(c + 1), result);
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/ppc/c2_globals_ppc.hpp openjdk-lts-11.0.14+9/src/hotspot/cpu/ppc/c2_globals_ppc.hpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/ppc/c2_globals_ppc.hpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/ppc/c2_globals_ppc.hpp 2022-01-13 21:56:25.000000000 +0000
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2000, 2018, Oracle and/or its affiliates. All rights reserved.
- * Copyright (c) 2012, 2018 SAP SE. All rights reserved.
+ * Copyright (c) 2012, 2019 SAP SE. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@@ -90,7 +90,7 @@
// Ergonomics related flags
define_pd_global(uint64_t, MaxRAM, 128ULL*G);
-define_pd_global(uintx, CodeCacheMinBlockLength, 4);
+define_pd_global(uintx, CodeCacheMinBlockLength, 6);
define_pd_global(uintx, CodeCacheMinimumUseSpace, 400*K);
define_pd_global(bool, TrapBasedRangeChecks, true);
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/ppc/frame_ppc.cpp openjdk-lts-11.0.14+9/src/hotspot/cpu/ppc/frame_ppc.cpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/ppc/frame_ppc.cpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/ppc/frame_ppc.cpp 2022-01-13 21:56:25.000000000 +0000
@@ -48,7 +48,6 @@
#endif // ASSERT
bool frame::safe_for_sender(JavaThread *thread) {
- bool safe = false;
address sp = (address)_sp;
address fp = (address)_fp;
address unextended_sp = (address)_unextended_sp;
@@ -76,29 +75,23 @@
// An fp must be within the stack and above (but not equal) sp.
bool fp_safe = (fp <= thread->stack_base()) && (fp > sp);
- // An interpreter fp must be within the stack and above (but not equal) sp.
- // Moreover, it must be at least the size of the ijava_state structure.
- bool fp_interp_safe = (fp <= thread->stack_base()) && (fp > sp) &&
- ((fp - sp) >= ijava_state_size);
+ // An interpreter fp must be fp_safe.
+ // Moreover, it must be at a distance at least the size of the ijava_state structure.
+ bool fp_interp_safe = fp_safe && ((fp - sp) >= ijava_state_size);
// We know sp/unextended_sp are safe, only fp is questionable here
// If the current frame is known to the code cache then we can attempt to
- // to construct the sender and do some validation of it. This goes a long way
+ // construct the sender and do some validation of it. This goes a long way
// toward eliminating issues when we get in frame construction code
if (_cb != NULL ){
- // Entry frame checks
- if (is_entry_frame()) {
- // An entry frame must have a valid fp.
- return fp_safe && is_entry_frame_valid(thread);
- }
- // Now check if the frame is complete and the test is
- // reliable. Unfortunately we can only check frame completeness for
- // runtime stubs and nmethods. Other generic buffer blobs are more
- // problematic so we just assume they are OK. Adapter blobs never have a
- // complete frame and are never OK
+ // First check if the frame is complete and the test is reliable.
+ // Unfortunately we can only check frame completeness for runtime stubs
+ // and nmethods. Other generic buffer blobs are more problematic
+ // so we just assume they are OK.
+ // Adapter blobs never have a complete frame and are never OK
if (!_cb->is_frame_complete_at(_pc)) {
if (_cb->is_compiled() || _cb->is_adapter_blob() || _cb->is_runtime_stub()) {
return false;
@@ -110,10 +103,23 @@
return false;
}
+ // Entry frame checks
+ if (is_entry_frame()) {
+ // An entry frame must have a valid fp.
+ return fp_safe && is_entry_frame_valid(thread);
+ }
+
if (is_interpreted_frame() && !fp_interp_safe) {
return false;
}
+ // At this point, there still is a chance that fp_safe is false.
+ // In particular, (fp == NULL) might be true. So let's check and
+ // bail out before we actually dereference from fp.
+ if (!fp_safe) {
+ return false;
+ }
+
abi_minframe* sender_abi = (abi_minframe*) fp;
intptr_t* sender_sp = (intptr_t*) fp;
address sender_pc = (address) sender_abi->lr;;
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/ppc/ppc.ad openjdk-lts-11.0.14+9/src/hotspot/cpu/ppc/ppc.ad
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/ppc/ppc.ad 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/ppc/ppc.ad 2022-01-13 21:56:25.000000000 +0000
@@ -4085,7 +4085,7 @@
// The `sig' array is to be updated. sig[j] represents the location
// of the j-th argument, either a register or a stack slot.
- // Comment taken from i486.ad:
+ // Comment taken from x86_32.ad:
// Body of function which returns an integer array locating
// arguments either in registers or in stack slots. Passed an array
// of ideal registers called "sig" and a "length" count. Stack-slot
@@ -4097,7 +4097,7 @@
SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
%}
- // Comment taken from i486.ad:
+ // Comment taken from x86_32.ad:
// Body of function which returns an integer array locating
// arguments either in registers or in stack slots. Passed an array
// of ideal registers called "sig" and a "length" count. Stack-slot
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/ppc/vm_version_ext_ppc.hpp openjdk-lts-11.0.14+9/src/hotspot/cpu/ppc/vm_version_ext_ppc.hpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/ppc/vm_version_ext_ppc.hpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/ppc/vm_version_ext_ppc.hpp 2022-01-13 21:56:25.000000000 +0000
@@ -25,8 +25,8 @@
#ifndef CPU_PPC_VM_VM_VERSION_EXT_PPC_HPP
#define CPU_PPC_VM_VM_VERSION_EXT_PPC_HPP
+#include "runtime/vm_version.hpp"
#include "utilities/macros.hpp"
-#include "vm_version_ppc.hpp"
#define CPU_INFO "cpu_info"
#define CPU_TYPE "fpu_type"
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/ppc/vm_version_ppc.cpp openjdk-lts-11.0.14+9/src/hotspot/cpu/ppc/vm_version_ppc.cpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/ppc/vm_version_ppc.cpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/ppc/vm_version_ppc.cpp 2022-01-13 21:56:25.000000000 +0000
@@ -32,10 +32,10 @@
#include "runtime/java.hpp"
#include "runtime/os.hpp"
#include "runtime/stubCodeGenerator.hpp"
+#include "runtime/vm_version.hpp"
#include "utilities/align.hpp"
#include "utilities/defaultStream.hpp"
#include "utilities/globalDefinitions.hpp"
-#include "vm_version_ppc.hpp"
#include
#if defined(_AIX)
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/ppc/vm_version_ppc.hpp openjdk-lts-11.0.14+9/src/hotspot/cpu/ppc/vm_version_ppc.hpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/ppc/vm_version_ppc.hpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/ppc/vm_version_ppc.hpp 2022-01-13 21:56:25.000000000 +0000
@@ -26,8 +26,8 @@
#ifndef CPU_PPC_VM_VM_VERSION_PPC_HPP
#define CPU_PPC_VM_VM_VERSION_PPC_HPP
+#include "runtime/abstract_vm_version.hpp"
#include "runtime/globals_extension.hpp"
-#include "runtime/vm_version.hpp"
class VM_Version: public Abstract_VM_Version {
protected:
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/ppc/vtableStubs_ppc_64.cpp openjdk-lts-11.0.14+9/src/hotspot/cpu/ppc/vtableStubs_ppc_64.cpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/ppc/vtableStubs_ppc_64.cpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/ppc/vtableStubs_ppc_64.cpp 2022-01-13 21:56:25.000000000 +0000
@@ -1,6 +1,6 @@
/*
- * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved.
- * Copyright (c) 2012, 2018 SAP SE. All rights reserved.
+ * Copyright (c) 1997, 2021, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2012, 2021 SAP SE. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@@ -72,9 +72,9 @@
slop_delta = load_const_maxLen - (__ pc() - start_pc);
slop_bytes += slop_delta;
assert(slop_delta >= 0, "negative slop(%d) encountered, adjust code size estimate!", slop_delta);
- __ lwz(R12_scratch2, offs, R11_scratch1);
+ __ ld(R12_scratch2, offs, R11_scratch1);
__ addi(R12_scratch2, R12_scratch2, 1);
- __ stw(R12_scratch2, offs, R11_scratch1);
+ __ std(R12_scratch2, offs, R11_scratch1);
}
#endif
@@ -140,6 +140,7 @@
if (s == NULL) {
return NULL;
}
+
// Count unused bytes in instruction sequences of variable size.
// We add them to the computed buffer size in order to avoid
// overflow in subsequently generated stubs.
@@ -159,9 +160,9 @@
slop_delta = load_const_maxLen - (__ pc() - start_pc);
slop_bytes += slop_delta;
assert(slop_delta >= 0, "negative slop(%d) encountered, adjust code size estimate!", slop_delta);
- __ lwz(R12_scratch2, offs, R11_scratch1);
+ __ ld(R12_scratch2, offs, R11_scratch1);
__ addi(R12_scratch2, R12_scratch2, 1);
- __ stw(R12_scratch2, offs, R11_scratch1);
+ __ std(R12_scratch2, offs, R11_scratch1);
}
#endif
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/s390/assembler_s390.hpp openjdk-lts-11.0.14+9/src/hotspot/cpu/s390/assembler_s390.hpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/s390/assembler_s390.hpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/s390/assembler_s390.hpp 2022-01-13 21:56:25.000000000 +0000
@@ -1,6 +1,6 @@
/*
- * Copyright (c) 2016, 2018, Oracle and/or its affiliates. All rights reserved.
- * Copyright (c) 2016, 2017 SAP SE. All rights reserved.
+ * Copyright (c) 2016, 2021, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2016, 2021 SAP SE. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@@ -1344,6 +1344,10 @@
#define CKSM_ZOPC (unsigned int)(0xb2 << 24 | 0x41 << 16) // checksum. This is NOT CRC32
#define KM_ZOPC (unsigned int)(0xb9 << 24 | 0x2e << 16) // cipher
#define KMC_ZOPC (unsigned int)(0xb9 << 24 | 0x2f << 16) // cipher
+#define KMA_ZOPC (unsigned int)(0xb9 << 24 | 0x29 << 16) // cipher
+#define KMF_ZOPC (unsigned int)(0xb9 << 24 | 0x2a << 16) // cipher
+#define KMCTR_ZOPC (unsigned int)(0xb9 << 24 | 0x2d << 16) // cipher
+#define KMO_ZOPC (unsigned int)(0xb9 << 24 | 0x2b << 16) // cipher
#define KIMD_ZOPC (unsigned int)(0xb9 << 24 | 0x3e << 16) // SHA (msg digest)
#define KLMD_ZOPC (unsigned int)(0xb9 << 24 | 0x3f << 16) // SHA (msg digest)
#define KMAC_ZOPC (unsigned int)(0xb9 << 24 | 0x1e << 16) // Message Authentication Code
@@ -2389,12 +2393,16 @@
// Complex CISC instructions
// ==========================
- inline void z_cksm(Register r1, Register r2); // checksum. This is NOT CRC32
- inline void z_km( Register r1, Register r2); // cipher message
- inline void z_kmc( Register r1, Register r2); // cipher message with chaining
- inline void z_kimd(Register r1, Register r2); // msg digest (SHA)
- inline void z_klmd(Register r1, Register r2); // msg digest (SHA)
- inline void z_kmac(Register r1, Register r2); // msg authentication code
+ inline void z_cksm( Register r1, Register r2); // checksum. This is NOT CRC32
+ inline void z_km( Register r1, Register r2); // cipher message
+ inline void z_kmc( Register r1, Register r2); // cipher message with chaining
+ inline void z_kma( Register r1, Register r3, Register r2); // cipher message with authentication
+ inline void z_kmf( Register r1, Register r2); // cipher message with cipher feedback
+ inline void z_kmctr(Register r1, Register r3, Register r2); // cipher message with counter
+ inline void z_kmo( Register r1, Register r2); // cipher message with output feedback
+ inline void z_kimd( Register r1, Register r2); // msg digest (SHA)
+ inline void z_klmd( Register r1, Register r2); // msg digest (SHA)
+ inline void z_kmac( Register r1, Register r2); // msg authentication code
inline void z_ex(Register r1, int64_t d2, Register x2, Register b2);// execute
inline void z_exrl(Register r1, int64_t i2); // execute relative long -- z10
@@ -3030,8 +3038,8 @@
inline void z_bvat(Label& L); // all true
inline void z_bvnt(Label& L); // not all true (mixed or all false)
inline void z_bvmix(Label& L); // mixed true and false
- inline void z_bvaf(Label& L); // not all false (mixed or all true)
- inline void z_bvnf(Label& L); // all false
+ inline void z_bvnf(Label& L); // not all false (mixed or all true)
+ inline void z_bvaf(Label& L); // all false
inline void z_brno( Label& L);
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/s390/assembler_s390.inline.hpp openjdk-lts-11.0.14+9/src/hotspot/cpu/s390/assembler_s390.inline.hpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/s390/assembler_s390.inline.hpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/s390/assembler_s390.inline.hpp 2022-01-13 21:56:25.000000000 +0000
@@ -1,6 +1,6 @@
/*
- * Copyright (c) 2016, 2017, Oracle and/or its affiliates. All rights reserved.
- * Copyright (c) 2016, 2017 SAP SE. All rights reserved.
+ * Copyright (c) 2016, 2021, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2016, 2021 SAP SE. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@@ -90,15 +90,19 @@
inline void Assembler::z_llgfrl(Register r1, int64_t i2){ emit_48( LLGFRL_ZOPC | regt(r1, 8, 48) | simm32(i2, 16, 48)); }
inline void Assembler::z_sthrl(Register r1, int64_t i2) { emit_48( STHRL_ZOPC | regt(r1, 8, 48) | simm32(i2, 16, 48)); }
-inline void Assembler::z_strl(Register r1, int64_t i2) { emit_48( STRL_ZOPC | regt(r1, 8, 48) | simm32(i2, 16, 48)); }
+inline void Assembler::z_strl( Register r1, int64_t i2) { emit_48( STRL_ZOPC | regt(r1, 8, 48) | simm32(i2, 16, 48)); }
inline void Assembler::z_stgrl(Register r1, int64_t i2) { emit_48( STGRL_ZOPC | regt(r1, 8, 48) | simm32(i2, 16, 48)); }
-inline void Assembler::z_cksm(Register r1, Register r2) { emit_32( CKSM_ZOPC | regt(r1, 24, 32) | regt(r2, 28, 32)); }
-inline void Assembler::z_km( Register r1, Register r2) { emit_32( KM_ZOPC | regt(r1, 24, 32) | regt(r2, 28, 32)); }
-inline void Assembler::z_kmc( Register r1, Register r2) { emit_32( KMC_ZOPC | regt(r1, 24, 32) | regt(r2, 28, 32)); }
-inline void Assembler::z_kimd(Register r1, Register r2) { emit_32( KIMD_ZOPC | regt(r1, 24, 32) | regt(r2, 28, 32)); }
-inline void Assembler::z_klmd(Register r1, Register r2) { emit_32( KLMD_ZOPC | regt(r1, 24, 32) | regt(r2, 28, 32)); }
-inline void Assembler::z_kmac(Register r1, Register r2) { emit_32( KMAC_ZOPC | regt(r1, 24, 32) | regt(r2, 28, 32)); }
+inline void Assembler::z_cksm( Register r1, Register r2) { emit_32( CKSM_ZOPC | regt(r1, 24, 32) | regt(r2, 28, 32)); }
+inline void Assembler::z_km( Register r1, Register r2) { emit_32( KM_ZOPC | regt(r1, 24, 32) | regt(r2, 28, 32)); }
+inline void Assembler::z_kmc( Register r1, Register r2) { emit_32( KMC_ZOPC | regt(r1, 24, 32) | regt(r2, 28, 32)); }
+inline void Assembler::z_kma( Register r1, Register r3, Register r2) { emit_32( KMA_ZOPC | regt(r3, 16, 32) | regt(r1, 24, 32) | regt(r2, 28, 32)); }
+inline void Assembler::z_kmf( Register r1, Register r2) { emit_32( KMF_ZOPC | regt(r1, 24, 32) | regt(r2, 28, 32)); }
+inline void Assembler::z_kmctr(Register r1, Register r3, Register r2) { emit_32( KMCTR_ZOPC | regt(r3, 16, 32) | regt(r1, 24, 32) | regt(r2, 28, 32)); }
+inline void Assembler::z_kmo( Register r1, Register r2) { emit_32( KMO_ZOPC | regt(r1, 24, 32) | regt(r2, 28, 32)); }
+inline void Assembler::z_kimd( Register r1, Register r2) { emit_32( KIMD_ZOPC | regt(r1, 24, 32) | regt(r2, 28, 32)); }
+inline void Assembler::z_klmd( Register r1, Register r2) { emit_32( KLMD_ZOPC | regt(r1, 24, 32) | regt(r2, 28, 32)); }
+inline void Assembler::z_kmac( Register r1, Register r2) { emit_32( KMAC_ZOPC | regt(r1, 24, 32) | regt(r2, 28, 32)); }
inline void Assembler::z_exrl(Register r1, int64_t i2) { emit_48( EXRL_ZOPC | regt(r1, 8, 48) | simm32(i2, 16, 48)); } // z10
inline void Assembler::z_exrl(Register r1, address a2) { emit_48( EXRL_ZOPC | regt(r1, 8, 48) | simm32(RelAddr::pcrel_off32(a2, pc()), 16, 48)); } // z10
@@ -1383,6 +1387,7 @@
// The length as returned from instr_len() can only be 2, 4, or 6 bytes.
// Having a default clause makes the compiler happy.
ShouldNotReachHere();
+ *instr = 0L; // This assignment is there to make gcc8 happy.
break;
}
return len;
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/s390/c1_LIRGenerator_s390.cpp openjdk-lts-11.0.14+9/src/hotspot/cpu/s390/c1_LIRGenerator_s390.cpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/s390/c1_LIRGenerator_s390.cpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/s390/c1_LIRGenerator_s390.cpp 2022-01-13 21:56:25.000000000 +0000
@@ -223,7 +223,7 @@
__ cmp_reg_mem(condition, reg, new LIR_Address(base, disp, type), info);
}
-bool LIRGenerator::strength_reduce_multiply(LIR_Opr left, int c, LIR_Opr result, LIR_Opr tmp) {
+bool LIRGenerator::strength_reduce_multiply(LIR_Opr left, jint c, LIR_Opr result, LIR_Opr tmp) {
if (tmp->is_valid()) {
if (is_power_of_2(c + 1)) {
__ move(left, tmp);
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/s390/frame_s390.cpp openjdk-lts-11.0.14+9/src/hotspot/cpu/s390/frame_s390.cpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/s390/frame_s390.cpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/s390/frame_s390.cpp 2022-01-13 21:56:25.000000000 +0000
@@ -52,7 +52,6 @@
// Profiling/safepoint support
bool frame::safe_for_sender(JavaThread *thread) {
- bool safe = false;
address sp = (address)_sp;
address fp = (address)_fp;
address unextended_sp = (address)_unextended_sp;
@@ -80,29 +79,23 @@
// An fp must be within the stack and above (but not equal) sp.
bool fp_safe = (fp <= thread->stack_base()) && (fp > sp);
- // An interpreter fp must be within the stack and above (but not equal) sp.
- // Moreover, it must be at least the size of the z_ijava_state structure.
- bool fp_interp_safe = (fp <= thread->stack_base()) && (fp > sp) &&
- ((fp - sp) >= z_ijava_state_size);
+ // An interpreter fp must be fp_safe.
+ // Moreover, it must be at a distance at least the size of the z_ijava_state structure.
+ bool fp_interp_safe = fp_safe && ((fp - sp) >= z_ijava_state_size);
// We know sp/unextended_sp are safe, only fp is questionable here
// If the current frame is known to the code cache then we can attempt to
- // to construct the sender and do some validation of it. This goes a long way
+ // construct the sender and do some validation of it. This goes a long way
// toward eliminating issues when we get in frame construction code
if (_cb != NULL ) {
- // Entry frame checks
- if (is_entry_frame()) {
- // An entry frame must have a valid fp.
- return fp_safe && is_entry_frame_valid(thread);
- }
- // Now check if the frame is complete and the test is
- // reliable. Unfortunately we can only check frame completeness for
- // runtime stubs. Other generic buffer blobs are more
- // problematic so we just assume they are OK. Adapter blobs never have a
- // complete frame and are never OK. nmethods should be OK on s390.
+ // First check if the frame is complete and the test is reliable.
+ // Unfortunately we can only check frame completeness for runtime stubs.
+ // Other generic buffer blobs are more problematic so we just assume they are OK.
+ // Adapter blobs never have a complete frame and are never OK.
+ // nmethods should be OK on s390.
if (!_cb->is_frame_complete_at(_pc)) {
if (_cb->is_adapter_blob() || _cb->is_runtime_stub()) {
return false;
@@ -114,13 +107,26 @@
return false;
}
+ // Entry frame checks
+ if (is_entry_frame()) {
+ // An entry frame must have a valid fp.
+ return fp_safe && is_entry_frame_valid(thread);
+ }
+
if (is_interpreted_frame() && !fp_interp_safe) {
return false;
}
+ // At this point, there still is a chance that fp_safe is false.
+ // In particular, (fp == NULL) might be true. So let's check and
+ // bail out before we actually dereference from fp.
+ if (!fp_safe) {
+ return false;
+ }
+
z_abi_160* sender_abi = (z_abi_160*) fp;
intptr_t* sender_sp = (intptr_t*) sender_abi->callers_sp;
- address sender_pc = (address) sender_abi->return_pc;
+ address sender_pc = (address) sender_abi->return_pc;
// We must always be able to find a recognizable pc.
CodeBlob* sender_blob = CodeCache::find_blob_unsafe(sender_pc);
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/s390/register_s390.hpp openjdk-lts-11.0.14+9/src/hotspot/cpu/s390/register_s390.hpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/s390/register_s390.hpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/s390/register_s390.hpp 2022-01-13 21:56:25.000000000 +0000
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2016, 2017, Oracle and/or its affiliates. All rights reserved.
- * Copyright (c) 2016, 2017 SAP SE. All rights reserved.
+ * Copyright (c) 2016, 2019 SAP SE. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@@ -27,7 +27,7 @@
#define CPU_S390_VM_REGISTER_S390_HPP
#include "asm/register.hpp"
-#include "vm_version_s390.hpp"
+#include "runtime/vm_version.hpp"
class Address;
class VMRegImpl;
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/s390/templateTable_s390.cpp openjdk-lts-11.0.14+9/src/hotspot/cpu/s390/templateTable_s390.cpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/s390/templateTable_s390.cpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/s390/templateTable_s390.cpp 2022-01-13 21:56:25.000000000 +0000
@@ -2010,7 +2010,7 @@
// Out-of-line code runtime calls.
if (UseLoopCounter) {
- if (ProfileInterpreter) {
+ if (ProfileInterpreter && !TieredCompilation) {
// Out-of-line code to allocate method data oop.
__ bind(profile_method);
@@ -3815,9 +3815,8 @@
// Get instance_size in InstanceKlass (scaled to a count of bytes).
Register Rsize = offset;
- const int mask = 1 << Klass::_lh_instance_slow_path_bit;
__ z_llgf(Rsize, Address(iklass, Klass::layout_helper_offset()));
- __ z_tmll(Rsize, mask);
+ __ z_tmll(Rsize, Klass::_lh_instance_slow_path_bit);
__ z_btrue(slow_case);
// Allocate the instance
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/s390/vm_version_ext_s390.hpp openjdk-lts-11.0.14+9/src/hotspot/cpu/s390/vm_version_ext_s390.hpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/s390/vm_version_ext_s390.hpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/s390/vm_version_ext_s390.hpp 2022-01-13 21:56:25.000000000 +0000
@@ -25,8 +25,8 @@
#ifndef CPU_S390_VM_VM_VERSION_EXT_S390_HPP
#define CPU_S390_VM_VM_VERSION_EXT_S390_HPP
+#include "runtime/vm_version.hpp"
#include "utilities/macros.hpp"
-#include "vm_version_s390.hpp"
#define CPU_INFO "cpu_info"
#define CPU_TYPE "fpu_type"
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/s390/vm_version_s390.cpp openjdk-lts-11.0.14+9/src/hotspot/cpu/s390/vm_version_s390.cpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/s390/vm_version_s390.cpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/s390/vm_version_s390.cpp 2022-01-13 21:56:25.000000000 +0000
@@ -1,6 +1,6 @@
/*
- * Copyright (c) 2016, 2019, Oracle and/or its affiliates. All rights reserved.
- * Copyright (c) 2016, 2019 SAP SE. All rights reserved.
+ * Copyright (c) 2016, 2021, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2016, 2021 SAP SE. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@@ -31,32 +31,67 @@
#include "memory/resourceArea.hpp"
#include "runtime/java.hpp"
#include "runtime/stubCodeGenerator.hpp"
-#include "vm_version_s390.hpp"
+#include "runtime/vm_version.hpp"
# include
bool VM_Version::_is_determine_features_test_running = false;
const char* VM_Version::_model_string;
-unsigned long VM_Version::_features[_features_buffer_len] = {0, 0, 0, 0};
-unsigned long VM_Version::_cipher_features[_features_buffer_len] = {0, 0, 0, 0};
-unsigned long VM_Version::_msgdigest_features[_features_buffer_len] = {0, 0, 0, 0};
-unsigned int VM_Version::_nfeatures = 0;
-unsigned int VM_Version::_ncipher_features = 0;
-unsigned int VM_Version::_nmsgdigest_features = 0;
-unsigned int VM_Version::_Dcache_lineSize = 256;
-unsigned int VM_Version::_Icache_lineSize = 256;
-
-static const char* z_gen[] = {" ", "G1", "G2", "G3", "G4", "G5", "G6", "G7" };
-static const char* z_machine[] = {" ", "2064", "2084", "2094", "2097", "2817", " ", "2964" };
-static const char* z_name[] = {" ", "z900", "z990", "z9 EC", "z10 EC", "z196 EC", "ec12", "z13" };
+unsigned long VM_Version::_features[_features_buffer_len] = {0, 0, 0, 0};
+unsigned long VM_Version::_cipher_features_KM[_features_buffer_len] = {0, 0, 0, 0};
+unsigned long VM_Version::_cipher_features_KMA[_features_buffer_len] = {0, 0, 0, 0};
+unsigned long VM_Version::_cipher_features_KMF[_features_buffer_len] = {0, 0, 0, 0};
+unsigned long VM_Version::_cipher_features_KMCTR[_features_buffer_len] = {0, 0, 0, 0};
+unsigned long VM_Version::_cipher_features_KMO[_features_buffer_len] = {0, 0, 0, 0};
+unsigned long VM_Version::_msgdigest_features[_features_buffer_len] = {0, 0, 0, 0};
+unsigned int VM_Version::_nfeatures = 0;
+unsigned int VM_Version::_ncipher_features_KM = 0;
+unsigned int VM_Version::_ncipher_features_KMA = 0;
+unsigned int VM_Version::_ncipher_features_KMF = 0;
+unsigned int VM_Version::_ncipher_features_KMCTR = 0;
+unsigned int VM_Version::_ncipher_features_KMO = 0;
+unsigned int VM_Version::_nmsgdigest_features = 0;
+unsigned int VM_Version::_Dcache_lineSize = DEFAULT_CACHE_LINE_SIZE;
+unsigned int VM_Version::_Icache_lineSize = DEFAULT_CACHE_LINE_SIZE;
+
+// The following list contains the (approximate) announcement/availability
+// dates of the many System z generations in existence as of now.
+// Information compiled from https://www.ibm.com/support/techdocs/atsmastr.nsf/WebIndex/TD105503
+// z900: 2000-10
+// z990: 2003-06
+// z9: 2005-09
+// z10: 2007-04
+// z10: 2008-02
+// z196: 2010-08
+// ec12: 2012-09
+// z13: 2015-03
+// z14: 2017-09
+// z15: 2019-09
+
+static const char* z_gen[] = {" ", "G1", "G2", "G3", "G4", "G5", "G6", "G7", "G8", "G9" };
+static const char* z_machine[] = {" ", "2064", "2084", "2094", "2097", "2817", "2827", "2964", "3906", "8561" };
+static const char* z_name[] = {" ", "z900", "z990", "z9 EC", "z10 EC", "z196 EC", "ec12", "z13", "z14", "z15" };
+static const char* z_WDFM[] = {" ", "2006-06-30", "2008-06-30", "2010-06-30", "2012-06-30", "2014-06-30", "2016-12-31", "2019-06-30", "2021-06-30", "tbd" };
+static const char* z_EOS[] = {" ", "2014-12-31", "2014-12-31", "2017-10-31", "2019-12-31", "2021-12-31", "tbd", "tbd", "tbd", "tbd" };
+static const char* z_features[] = {" ",
+ "system-z, g1-z900, ldisp",
+ "system-z, g2-z990, ldisp_fast",
+ "system-z, g3-z9, ldisp_fast, extimm",
+ "system-z, g4-z10, ldisp_fast, extimm, pcrel_load/store, cmpb",
+ "system-z, g5-z196, ldisp_fast, extimm, pcrel_load/store, cmpb, cond_load/store, interlocked_update",
+ "system-z, g6-ec12, ldisp_fast, extimm, pcrel_load/store, cmpb, cond_load/store, interlocked_update, txm",
+ "system-z, g7-z13, ldisp_fast, extimm, pcrel_load/store, cmpb, cond_load/store, interlocked_update, txm, vectorinstr",
+ "system-z, g8-z14, ldisp_fast, extimm, pcrel_load/store, cmpb, cond_load/store, interlocked_update, txm, vectorinstr, instrext2, venh1)",
+ "system-z, g9-z15, ldisp_fast, extimm, pcrel_load/store, cmpb, cond_load/store, interlocked_update, txm, vectorinstr, instrext2, venh1, instrext3, VEnh2 )"
+ };
void VM_Version::initialize() {
determine_features(); // Get processor capabilities.
set_features_string(); // Set a descriptive feature indication.
- if (Verbose) {
- print_features();
+ if (Verbose || PrintAssembly || PrintStubCode) {
+ print_features_internal("CPU Version as detected internally:", PrintAssembly || PrintStubCode);
}
intx cache_line_size = Dcache_lineSize(0);
@@ -252,76 +287,104 @@
}
-void VM_Version::set_features_string() {
-
- unsigned int ambiguity = 0;
- _model_string = z_name[0];
+int VM_Version::get_model_index() {
+ // returns the index used to access the various model-dependent strings.
+ // > 0 valid (known) model detected.
+ // = 0 model not recognized, maybe not yet supported.
+ // < 0 model detection is ambiguous. The absolute value of the returned value
+ // is the index of the oldest detected model.
+ int ambiguity = 0;
+ int model_ix = 0;
+ if (is_z15()) {
+ model_ix = 9;
+ ambiguity++;
+ }
+ if (is_z14()) {
+ model_ix = 8;
+ ambiguity++;
+ }
if (is_z13()) {
- _features_string = "System z G7-z13 (LDISP_fast, ExtImm, PCrel Load/Store, CmpB, Cond Load/Store, Interlocked Update, TxM, VectorInstr)";
- _model_string = z_name[7];
+ model_ix = 7;
ambiguity++;
}
if (is_ec12()) {
- _features_string = "System z G6-EC12 (LDISP_fast, ExtImm, PCrel Load/Store, CmpB, Cond Load/Store, Interlocked Update, TxM)";
- _model_string = z_name[6];
+ model_ix = 6;
ambiguity++;
}
if (is_z196()) {
- _features_string = "System z G5-z196 (LDISP_fast, ExtImm, PCrel Load/Store, CmpB, Cond Load/Store, Interlocked Update)";
- _model_string = z_name[5];
+ model_ix = 5;
ambiguity++;
}
if (is_z10()) {
- _features_string = "System z G4-z10 (LDISP_fast, ExtImm, PCrel Load/Store, CmpB)";
- _model_string = z_name[4];
+ model_ix = 4;
ambiguity++;
}
if (is_z9()) {
- _features_string = "System z G3-z9 (LDISP_fast, ExtImm), out-of-support as of 2016-04-01";
- _model_string = z_name[3];
+ model_ix = 3;
ambiguity++;
}
if (is_z990()) {
- _features_string = "System z G2-z990 (LDISP_fast), out-of-support as of 2014-07-01";
- _model_string = z_name[2];
+ model_ix = 2;
ambiguity++;
}
if (is_z900()) {
- _features_string = "System z G1-z900 (LDISP), out-of-support as of 2014-07-01";
- _model_string = z_name[1];
+ model_ix = 1;
ambiguity++;
}
- if (ambiguity == 0) {
- _features_string = "z/Architecture (unknown generation)";
- } else if (ambiguity > 1) {
- tty->print_cr("*** WARNING *** Ambiguous z/Architecture detection, ambiguity = %d", ambiguity);
- tty->print_cr(" oldest detected generation is %s", _features_string);
- _features_string = "z/Architecture (ambiguous detection)";
+ if (ambiguity > 1) {
+ model_ix = -model_ix;
+ }
+ return model_ix;
+}
+
+
+void VM_Version::set_features_string() {
+ // A note on the _features_string format:
+ // There are jtreg tests checking the _features_string for various properties.
+ // For some strange reason, these tests require the string to contain
+ // only _lowercase_ characters. Keep that in mind when being surprised
+ // about the unusual notation of features - and when adding new ones.
+ // Features may have one comma at the end.
+ // Furthermore, use one, and only one, separator space between features.
+ // Multiple spaces are considered separate tokens, messing up everything.
+
+ int model_ix = get_model_index();
+ char buf[512];
+ if (model_ix == 0) {
+ _model_string = "unknown model";
+ strcpy(buf, "z/Architecture (unknown generation)");
+ } else if (model_ix > 0) {
+ _model_string = z_name[model_ix];
+ jio_snprintf(buf, sizeof(buf), "%s, out-of-support_as_of_", z_features[model_ix], z_EOS[model_ix]);
+ } else if (model_ix < 0) {
+ tty->print_cr("*** WARNING *** Ambiguous z/Architecture detection!");
+ tty->print_cr(" oldest detected generation is %s", z_features[-model_ix]);
+ _model_string = "unknown model";
+ strcpy(buf, "z/Architecture (ambiguous detection)");
}
+ _features_string = os::strdup(buf);
if (has_Crypto_AES()) {
- char buf[256];
- assert(strlen(_features_string) + 4 + 3*4 + 1 < sizeof(buf), "increase buffer size");
- jio_snprintf(buf, sizeof(buf), "%s aes%s%s%s", // String 'aes' must be surrounded by spaces so that jtreg tests recognize it.
+ assert(strlen(_features_string) + 3*8 < sizeof(buf), "increase buffer size");
+ jio_snprintf(buf, sizeof(buf), "%s%s%s%s",
_features_string,
- has_Crypto_AES128() ? " 128" : "",
- has_Crypto_AES192() ? " 192" : "",
- has_Crypto_AES256() ? " 256" : "");
+ has_Crypto_AES128() ? ", aes128" : "",
+ has_Crypto_AES192() ? ", aes192" : "",
+ has_Crypto_AES256() ? ", aes256" : "");
+ os::free((void *)_features_string);
_features_string = os::strdup(buf);
}
if (has_Crypto_SHA()) {
- char buf[256];
- assert(strlen(_features_string) + 4 + 2 + 2*4 + 6 + 1 < sizeof(buf), "increase buffer size");
- // String 'sha1' etc must be surrounded by spaces so that jtreg tests recognize it.
- jio_snprintf(buf, sizeof(buf), "%s %s%s%s%s",
+ assert(strlen(_features_string) + 6 + 2*8 + 7 < sizeof(buf), "increase buffer size");
+ jio_snprintf(buf, sizeof(buf), "%s%s%s%s%s",
_features_string,
- has_Crypto_SHA1() ? " sha1" : "",
- has_Crypto_SHA256() ? " sha256" : "",
- has_Crypto_SHA512() ? " sha512" : "",
- has_Crypto_GHASH() ? " ghash" : "");
- if (has_Crypto_AES()) { os::free((void *)_features_string); }
+ has_Crypto_SHA1() ? ", sha1" : "",
+ has_Crypto_SHA256() ? ", sha256" : "",
+ has_Crypto_SHA512() ? ", sha512" : "",
+ has_Crypto_GHASH() ? ", ghash" : "");
+ os::free((void *)_features_string);
_features_string = os::strdup(buf);
}
}
@@ -352,11 +415,7 @@
}
void VM_Version::print_features_internal(const char* text, bool print_anyway) {
- tty->print_cr("%s %s", text, features_string());
- tty->print("%s", text);
- for (unsigned int i = 0; i < _nfeatures; i++) {
- tty->print(" 0x%16.16lx", _features[i]);
- }
+ tty->print_cr("%s %s", text, features_string());
tty->cr();
if (Verbose || print_anyway) {
@@ -386,7 +445,7 @@
if (has_Prefetch() ) tty->print_cr(" available: %s", "Prefetch");
if (has_MoveImmToMem() ) tty->print_cr(" available: %s", "Direct Moves Immediate to Memory");
if (has_MemWithImmALUOps() ) tty->print_cr(" available: %s", "Direct ALU Ops Memory .op. Immediate");
- if (has_ExtractCPUAttributes() ) tty->print_cr(" available: %s", "Extract CPU Atributes");
+ if (has_ExtractCPUAttributes() ) tty->print_cr(" available: %s", "Extract CPU Attributes");
if (has_ExecuteExtensions() ) tty->print_cr("available: %s", "ExecuteExtensions");
if (has_FPSupportEnhancements() ) tty->print_cr("available: %s", "FPSupportEnhancements");
if (has_DecimalFloatingPoint() ) tty->print_cr("available: %s", "DecimalFloatingPoint");
@@ -402,7 +461,7 @@
if (has_CryptoExt3() ) tty->print_cr("available: %s", "Crypto Extensions 3");
if (has_CryptoExt4() ) tty->print_cr("available: %s", "Crypto Extensions 4");
// EC12
- if (has_MiscInstrExt() ) tty->print_cr("available: %s", "Miscelaneous Instruction Extensions");
+ if (has_MiscInstrExt() ) tty->print_cr("available: %s", "Miscellaneous Instruction Extensions");
if (has_ExecutionHint() ) tty->print_cr(" available: %s", "Execution Hints (branch prediction)");
if (has_ProcessorAssist() ) tty->print_cr(" available: %s", "Processor Assists");
if (has_LoadAndTrap() ) tty->print_cr(" available: %s", "Load and Trap");
@@ -414,23 +473,27 @@
if (has_CryptoExt5() ) tty->print_cr("available: %s", "Crypto Extensions 5");
if (has_DFPPackedConversion() ) tty->print_cr("available: %s", "DFP Packed Conversions");
if (has_VectorFacility() ) tty->print_cr("available: %s", "Vector Facility");
- // test switches
- if (has_TestFeature1Impl() ) tty->print_cr("available: %s", "TestFeature1Impl");
- if (has_TestFeature2Impl() ) tty->print_cr("available: %s", "TestFeature2Impl");
- if (has_TestFeature4Impl() ) tty->print_cr("available: %s", "TestFeature4Impl");
- if (has_TestFeature8Impl() ) tty->print_cr("available: %s", "TestFeature8Impl");
+ // z14
+ if (has_MiscInstrExt2() ) tty->print_cr("available: %s", "Miscellaneous Instruction Extensions 2");
+ if (has_VectorEnhancements1() ) tty->print_cr("available: %s", "Vector Facility Enhancements 3");
+ if (has_CryptoExt8() ) tty->print_cr("available: %s", "Crypto Extensions 8");
+ // z15
+ if (has_MiscInstrExt3() ) tty->print_cr("available: %s", "Miscellaneous Instruction Extensions 3");
+ if (has_VectorEnhancements2() ) tty->print_cr("available: %s", "Vector Facility Enhancements 3");
+ if (has_CryptoExt9() ) tty->print_cr("available: %s", "Crypto Extensions 9");
if (has_Crypto()) {
tty->cr();
tty->print_cr("detailed availability of %s capabilities:", "CryptoFacility");
- if (test_feature_bit(&_cipher_features[0], -1, 2*Cipher::_featureBits)) {
+ if (test_feature_bit(&_cipher_features_KM[0], -1, 2*Cipher::_featureBits)) {
tty->cr();
tty->print_cr(" available: %s", "Message Cipher Functions");
}
- if (test_feature_bit(&_cipher_features[0], -1, (int)Cipher::_featureBits)) {
+
+ if (test_feature_bit(&_cipher_features_KM[0], -1, (int)Cipher::_featureBits)) {
tty->print_cr(" available Crypto Features of KM (Cipher Message):");
for (unsigned int i = 0; i < Cipher::_featureBits; i++) {
- if (test_feature_bit(&_cipher_features[0], i, (int)Cipher::_featureBits)) {
+ if (test_feature_bit(&_cipher_features_KM[0], i, (int)Cipher::_featureBits)) {
switch (i) {
case Cipher::_Query: tty->print_cr(" available: KM Query"); break;
case Cipher::_DEA: tty->print_cr(" available: KM DEA"); break;
@@ -454,10 +517,11 @@
}
}
}
- if (test_feature_bit(&_cipher_features[2], -1, (int)Cipher::_featureBits)) {
+
+ if (test_feature_bit(&_cipher_features_KM[2], -1, (int)Cipher::_featureBits)) {
tty->print_cr(" available Crypto Features of KMC (Cipher Message with Chaining):");
for (unsigned int i = 0; i < Cipher::_featureBits; i++) {
- if (test_feature_bit(&_cipher_features[2], i, (int)Cipher::_featureBits)) {
+ if (test_feature_bit(&_cipher_features_KM[2], i, (int)Cipher::_featureBits)) {
switch (i) {
case Cipher::_Query: tty->print_cr(" available: KMC Query"); break;
case Cipher::_DEA: tty->print_cr(" available: KMC DEA"); break;
@@ -478,35 +542,145 @@
}
}
}
+ }
+
+ if (has_CryptoExt4()) {
+ if (test_feature_bit(&_cipher_features_KMF[0], -1, (int)Cipher::_featureBits)) {
+ tty->print_cr(" available Crypto Features of KMF (Cipher Message with Cipher Feedback):");
+ for (unsigned int i = 0; i < Cipher::_featureBits; i++) {
+ if (test_feature_bit(&_cipher_features_KMF[0], i, (int)Cipher::_featureBits)) {
+ switch (i) {
+ case Cipher::_Query: tty->print_cr(" available: KMF Query"); break;
+ case Cipher::_DEA: tty->print_cr(" available: KMF DEA"); break;
+ case Cipher::_TDEA128: tty->print_cr(" available: KMF TDEA-128"); break;
+ case Cipher::_TDEA192: tty->print_cr(" available: KMF TDEA-192"); break;
+ case Cipher::_EncryptedDEA: tty->print_cr(" available: KMF Encrypted DEA"); break;
+ case Cipher::_EncryptedDEA128: tty->print_cr(" available: KMF Encrypted DEA-128"); break;
+ case Cipher::_EncryptedDEA192: tty->print_cr(" available: KMF Encrypted DEA-192"); break;
+ case Cipher::_AES128: tty->print_cr(" available: KMF AES-128"); break;
+ case Cipher::_AES192: tty->print_cr(" available: KMF AES-192"); break;
+ case Cipher::_AES256: tty->print_cr(" available: KMF AES-256"); break;
+ case Cipher::_EnccryptedAES128: tty->print_cr(" available: KMF Encrypted-AES-128"); break;
+ case Cipher::_EnccryptedAES192: tty->print_cr(" available: KMF Encrypted-AES-192"); break;
+ case Cipher::_EnccryptedAES256: tty->print_cr(" available: KMF Encrypted-AES-256"); break;
+ default: tty->print_cr(" available: unknown KMF code %d", i); break;
+ }
+ }
+ }
+ }
+
+ if (test_feature_bit(&_cipher_features_KMCTR[0], -1, (int)Cipher::_featureBits)) {
+ tty->print_cr(" available Crypto Features of KMCTR (Cipher Message with Counter):");
+ for (unsigned int i = 0; i < Cipher::_featureBits; i++) {
+ if (test_feature_bit(&_cipher_features_KMCTR[0], i, (int)Cipher::_featureBits)) {
+ switch (i) {
+ case Cipher::_Query: tty->print_cr(" available: KMCTR Query"); break;
+ case Cipher::_DEA: tty->print_cr(" available: KMCTR DEA"); break;
+ case Cipher::_TDEA128: tty->print_cr(" available: KMCTR TDEA-128"); break;
+ case Cipher::_TDEA192: tty->print_cr(" available: KMCTR TDEA-192"); break;
+ case Cipher::_EncryptedDEA: tty->print_cr(" available: KMCTR Encrypted DEA"); break;
+ case Cipher::_EncryptedDEA128: tty->print_cr(" available: KMCTR Encrypted DEA-128"); break;
+ case Cipher::_EncryptedDEA192: tty->print_cr(" available: KMCTR Encrypted DEA-192"); break;
+ case Cipher::_AES128: tty->print_cr(" available: KMCTR AES-128"); break;
+ case Cipher::_AES192: tty->print_cr(" available: KMCTR AES-192"); break;
+ case Cipher::_AES256: tty->print_cr(" available: KMCTR AES-256"); break;
+ case Cipher::_EnccryptedAES128: tty->print_cr(" available: KMCTR Encrypted-AES-128"); break;
+ case Cipher::_EnccryptedAES192: tty->print_cr(" available: KMCTR Encrypted-AES-192"); break;
+ case Cipher::_EnccryptedAES256: tty->print_cr(" available: KMCTR Encrypted-AES-256"); break;
+ default: tty->print_cr(" available: unknown KMCTR code %d", i); break;
+ }
+ }
+ }
+ }
+
+ if (test_feature_bit(&_cipher_features_KMO[0], -1, (int)Cipher::_featureBits)) {
+ tty->print_cr(" available Crypto Features of KMO (Cipher Message with Output Feedback):");
+ for (unsigned int i = 0; i < Cipher::_featureBits; i++) {
+ if (test_feature_bit(&_cipher_features_KMO[0], i, (int)Cipher::_featureBits)) {
+ switch (i) {
+ case Cipher::_Query: tty->print_cr(" available: KMO Query"); break;
+ case Cipher::_DEA: tty->print_cr(" available: KMO DEA"); break;
+ case Cipher::_TDEA128: tty->print_cr(" available: KMO TDEA-128"); break;
+ case Cipher::_TDEA192: tty->print_cr(" available: KMO TDEA-192"); break;
+ case Cipher::_EncryptedDEA: tty->print_cr(" available: KMO Encrypted DEA"); break;
+ case Cipher::_EncryptedDEA128: tty->print_cr(" available: KMO Encrypted DEA-128"); break;
+ case Cipher::_EncryptedDEA192: tty->print_cr(" available: KMO Encrypted DEA-192"); break;
+ case Cipher::_AES128: tty->print_cr(" available: KMO AES-128"); break;
+ case Cipher::_AES192: tty->print_cr(" available: KMO AES-192"); break;
+ case Cipher::_AES256: tty->print_cr(" available: KMO AES-256"); break;
+ case Cipher::_EnccryptedAES128: tty->print_cr(" available: KMO Encrypted-AES-128"); break;
+ case Cipher::_EnccryptedAES192: tty->print_cr(" available: KMO Encrypted-AES-192"); break;
+ case Cipher::_EnccryptedAES256: tty->print_cr(" available: KMO Encrypted-AES-256"); break;
+ default: tty->print_cr(" available: unknown KMO code %d", i); break;
+ }
+ }
+ }
+ }
+ }
+ if (has_CryptoExt8()) {
+ if (test_feature_bit(&_cipher_features_KMA[0], -1, (int)Cipher::_featureBits)) {
+ tty->print_cr(" available Crypto Features of KMA (Cipher Message with Authentication):");
+ for (unsigned int i = 0; i < Cipher::_featureBits; i++) {
+ if (test_feature_bit(&_cipher_features_KMA[0], i, (int)Cipher::_featureBits)) {
+ switch (i) {
+ case Cipher::_Query: tty->print_cr(" available: KMA Query"); break;
+ case Cipher::_AES128: tty->print_cr(" available: KMA-GCM AES-128"); break;
+ case Cipher::_AES192: tty->print_cr(" available: KMA-GCM AES-192"); break;
+ case Cipher::_AES256: tty->print_cr(" available: KMA-GCM AES-256"); break;
+ case Cipher::_EnccryptedAES128: tty->print_cr(" available: KMA-GCM Encrypted-AES-128"); break;
+ case Cipher::_EnccryptedAES192: tty->print_cr(" available: KMA-GCM Encrypted-AES-192"); break;
+ case Cipher::_EnccryptedAES256: tty->print_cr(" available: KMA-GCM Encrypted-AES-256"); break;
+ default: tty->print_cr(" available: unknown KMA code %d", i); break;
+ }
+ }
+ }
+ }
+ }
+
+ if (has_Crypto()) {
if (test_feature_bit(&_msgdigest_features[0], -1, 2*MsgDigest::_featureBits)) {
tty->cr();
tty->print_cr(" available: %s", "Message Digest Functions for SHA");
}
+
if (test_feature_bit(&_msgdigest_features[0], -1, (int)MsgDigest::_featureBits)) {
tty->print_cr(" available Features of KIMD (Msg Digest):");
for (unsigned int i = 0; i < MsgDigest::_featureBits; i++) {
- if (test_feature_bit(&_msgdigest_features[0], i, (int)MsgDigest::_featureBits)) {
+ if (test_feature_bit(&_msgdigest_features[0], i, (int)MsgDigest::_featureBits)) {
switch (i) {
- case MsgDigest::_Query: tty->print_cr(" available: KIMD Query"); break;
- case MsgDigest::_SHA1: tty->print_cr(" available: KIMD SHA-1"); break;
- case MsgDigest::_SHA256: tty->print_cr(" available: KIMD SHA-256"); break;
- case MsgDigest::_SHA512: tty->print_cr(" available: KIMD SHA-512"); break;
- case MsgDigest::_GHASH: tty->print_cr(" available: KIMD GHASH"); break;
+ case MsgDigest::_Query: tty->print_cr(" available: KIMD Query"); break;
+ case MsgDigest::_SHA1: tty->print_cr(" available: KIMD SHA-1"); break;
+ case MsgDigest::_SHA256: tty->print_cr(" available: KIMD SHA-256"); break;
+ case MsgDigest::_SHA512: tty->print_cr(" available: KIMD SHA-512"); break;
+ case MsgDigest::_SHA3_224: tty->print_cr(" available: KIMD SHA3-224"); break;
+ case MsgDigest::_SHA3_256: tty->print_cr(" available: KIMD SHA3-256"); break;
+ case MsgDigest::_SHA3_384: tty->print_cr(" available: KIMD SHA3-384"); break;
+ case MsgDigest::_SHA3_512: tty->print_cr(" available: KIMD SHA3-512"); break;
+ case MsgDigest::_SHAKE_128: tty->print_cr(" available: KIMD SHAKE-128"); break;
+ case MsgDigest::_SHAKE_256: tty->print_cr(" available: KIMD SHAKE-256"); break;
+ case MsgDigest::_GHASH: tty->print_cr(" available: KIMD GHASH"); break;
default: tty->print_cr(" available: unknown code %d", i); break;
}
}
}
}
+
if (test_feature_bit(&_msgdigest_features[2], -1, (int)MsgDigest::_featureBits)) {
tty->print_cr(" available Features of KLMD (Msg Digest):");
for (unsigned int i = 0; i < MsgDigest::_featureBits; i++) {
if (test_feature_bit(&_msgdigest_features[2], i, (int)MsgDigest::_featureBits)) {
switch (i) {
- case MsgDigest::_Query: tty->print_cr(" available: KLMD Query"); break;
- case MsgDigest::_SHA1: tty->print_cr(" available: KLMD SHA-1"); break;
- case MsgDigest::_SHA256: tty->print_cr(" available: KLMD SHA-256"); break;
- case MsgDigest::_SHA512: tty->print_cr(" available: KLMD SHA-512"); break;
+ case MsgDigest::_Query: tty->print_cr(" available: KLMD Query"); break;
+ case MsgDigest::_SHA1: tty->print_cr(" available: KLMD SHA-1"); break;
+ case MsgDigest::_SHA256: tty->print_cr(" available: KLMD SHA-256"); break;
+ case MsgDigest::_SHA512: tty->print_cr(" available: KLMD SHA-512"); break;
+ case MsgDigest::_SHA3_224: tty->print_cr(" available: KLMD SHA3-224"); break;
+ case MsgDigest::_SHA3_256: tty->print_cr(" available: KLMD SHA3-256"); break;
+ case MsgDigest::_SHA3_384: tty->print_cr(" available: KLMD SHA3-384"); break;
+ case MsgDigest::_SHA3_512: tty->print_cr(" available: KLMD SHA3-512"); break;
+ case MsgDigest::_SHAKE_128: tty->print_cr(" available: KLMD SHAKE-128"); break;
+ case MsgDigest::_SHAKE_256: tty->print_cr(" available: KLMD SHAKE-256"); break;
default: tty->print_cr(" available: unknown code %d", i); break;
}
}
@@ -626,6 +800,26 @@
set_has_VectorFacility();
}
+void VM_Version::set_features_z14(bool reset) {
+ reset_features(reset);
+
+ set_features_z13(false);
+ set_has_MiscInstrExt2();
+ set_has_VectorEnhancements1();
+ has_VectorPackedDecimal();
+ set_has_CryptoExt8();
+}
+
+void VM_Version::set_features_z15(bool reset) {
+ reset_features(reset);
+
+ set_features_z14(false);
+ set_has_MiscInstrExt3();
+ set_has_VectorEnhancements2();
+ has_VectorPackedDecimalEnh();
+ set_has_CryptoExt9();
+}
+
void VM_Version::set_features_from(const char* march) {
bool err = false;
bool prt = false;
@@ -655,33 +849,10 @@
set_features_ec12();
} else if (!strcmp(march, "z13")) {
set_features_z13();
- } else if (!strcmp(buf, "ztest")) {
- assert(!has_TestFeaturesImpl(), "possible facility list flag conflict");
- if (strlen(march) > hdr_len) {
- int itest = 0;
- if ((strlen(march)-hdr_len) >= buf_len) err = true;
- if (!err) {
- memcpy(buf, &march[hdr_len], strlen(march)-hdr_len);
- buf[strlen(march)-hdr_len] = '\00';
- for (size_t i = 0; !err && (i < strlen(buf)); i++) {
- itest = itest*10 + buf[i]-'0';
- err = err || ((buf[i]-'0') < 0) || ((buf[i]-'0') > 9) || (itest > 15);
- }
- }
- if (!err) {
- prt = true;
- if (itest & 0x01) { set_has_TestFeature1Impl(); }
- if (itest & 0x02) { set_has_TestFeature2Impl(); }
- if (itest & 0x04) { set_has_TestFeature4Impl(); }
- if (itest & 0x08) { set_has_TestFeature8Impl(); }
- }
- } else {
- prt = true;
- set_has_TestFeature1Impl();
- set_has_TestFeature2Impl();
- set_has_TestFeature4Impl();
- set_has_TestFeature8Impl();
- }
+ } else if (!strcmp(march, "z14")) {
+ set_features_z14();
+ } else if (!strcmp(march, "z15")) {
+ set_features_z15();
} else {
err = true;
}
@@ -697,6 +868,29 @@
}
+// getFeatures call interface
+// Z_ARG1 (R2) - feature bit buffer address.
+// Must be DW aligned.
+// Z_ARG2 (R3) - > 0 feature bit buffer length (#DWs).
+// Implies request to store cpu feature list via STFLE.
+// = 0 invalid
+// < 0 function code (which feature information to retrieve)
+// Implies that a buffer of at least two DWs is passed in.
+// =-1 - retrieve cache topology
+// =-2 - basic cipher instruction capabilities
+// =-3 - msg digest (secure hash) instruction capabilities
+// =-4 - vector instruction OS support availability
+// =-17 - cipher (KMF) support
+// =-18 - cipher (KMCTR) support
+// =-19 - cipher (KMO) support
+// =-20 - cipher (KMA) support
+// Z_ARG3 (R4) - feature code for ECAG instruction
+//
+// Z_RET (R2) - return value
+// > 0: success: number of retrieved feature bit string words.
+// < 0: failure: required number of feature bit string words (buffer too small).
+// == 0: failure: operation aborted.
+//
static long (*getFeatures)(unsigned long*, int, int) = NULL;
void VM_Version::set_getFeatures(address entryPoint) {
@@ -719,6 +913,14 @@
return (attributeIndication<<4) | (levelIndication<<1) | typeIndication;
}
+void VM_Version::clear_buffer(unsigned long* buffer, unsigned int len) {
+ memset(buffer, 0, sizeof(buffer[0])*len);
+}
+
+void VM_Version::copy_buffer(unsigned long* to, unsigned long* from, unsigned int len) {
+ memcpy(to, from, sizeof(to[0])*len);
+}
+
void VM_Version::determine_features() {
const int cbuf_size = _code_buffer_len;
@@ -736,27 +938,38 @@
// Try STFLE. Possible INVOP will cause defaults to be used.
Label getFEATURES;
Label getCPUFEATURES; // fcode = -1 (cache)
- Label getCIPHERFEATURES; // fcode = -2 (cipher)
+ Label getCIPHERFEATURES_KM; // fcode = -2 (cipher)
+ Label getCIPHERFEATURES_KMA; // fcode = -20 (cipher)
+ Label getCIPHERFEATURES_KMF; // fcode = -17 (cipher)
+ Label getCIPHERFEATURES_KMCTR; // fcode = -18 (cipher)
+ Label getCIPHERFEATURES_KMO; // fcode = -19 (cipher)
Label getMSGDIGESTFEATURES; // fcode = -3 (SHA)
Label getVECTORFEATURES; // fcode = -4 (OS support for vector instructions)
Label errRTN;
- a->z_ltgfr(Z_R0, Z_ARG2); // Buf len to r0 and test.
- a->z_brl(getFEATURES); // negative -> Get machine features not covered by facility list.
+ a->z_ltgfr(Z_R0, Z_ARG2); // buf_len/fcode to r0 and test.
+ a->z_brl(getFEATURES); // negative -> Get machine features or instruction-specific features
a->z_lghi(Z_R1,0);
a->z_brz(errRTN); // zero -> Function code currently not used, indicate "aborted".
- a->z_aghi(Z_R0, -1);
+ //---< store feature list >---
+ // We have three possible outcomes here:
+ // success: cc = 0 and first DW of feature bit array != 0
+ // Z_R0 contains index of last stored DW (used_len - 1)
+ // incomplete: cc = 3 and first DW of feature bit array != 0
+ // Z_R0 contains index of last DW that would have been stored (required_len - 1)
+ a->z_aghi(Z_R0, -1); // STFLE needs last index, not length, of feature bit array.
a->z_stfle(0, Z_ARG1);
- a->z_lg(Z_R1, 0, Z_ARG1); // Get first DW of facility list.
- a->z_lgr(Z_RET, Z_R0); // Calculate rtn value for success.
- a->z_la(Z_RET, 1, Z_RET);
+ a->z_lg(Z_R1, Address(Z_ARG1, (intptr_t)0)); // Get first DW of facility list.
+ a->z_lgr(Z_RET, Z_R0); // Calculate used/required len
+ a->z_la(Z_RET, 1, Z_RET); // don't destroy cc from stfle!
a->z_brnz(errRTN); // Instr failed if non-zero CC.
- a->z_ltgr(Z_R1, Z_R1); // Instr failed if first DW == 0.
+ a->z_ltgr(Z_R1, Z_R1); // Check if first DW of facility list was filled.
a->z_bcr(Assembler::bcondNotZero, Z_R14); // Successful return.
+ //---< error exit >---
a->bind(errRTN);
- a->z_lngr(Z_RET, Z_RET);
- a->z_ltgr(Z_R1, Z_R1);
+ a->z_lngr(Z_RET, Z_RET); // negative return value to indicate "buffer too small"
+ a->z_ltgr(Z_R1, Z_R1); // Check if first DW of facility list was filled.
a->z_bcr(Assembler::bcondNotZero, Z_R14); // Return "buffer too small".
a->z_xgr(Z_RET, Z_RET);
a->z_br(Z_R14); // Return "operation aborted".
@@ -765,12 +978,21 @@
a->z_cghi(Z_R0, -1); // -1: Extract CPU attributes, currently: cache layout only.
a->z_bre(getCPUFEATURES);
a->z_cghi(Z_R0, -2); // -2: Extract detailed crypto capabilities (cipher instructions).
- a->z_bre(getCIPHERFEATURES);
+ a->z_bre(getCIPHERFEATURES_KM);
a->z_cghi(Z_R0, -3); // -3: Extract detailed crypto capabilities (msg digest instructions).
a->z_bre(getMSGDIGESTFEATURES);
a->z_cghi(Z_R0, -4); // -4: Verify vector instruction availability (OS support).
a->z_bre(getVECTORFEATURES);
+ a->z_cghi(Z_R0, -17); // -17: Extract detailed crypto capabilities (cipher instructions).
+ a->z_bre(getCIPHERFEATURES_KMF);
+ a->z_cghi(Z_R0, -18); // -18: Extract detailed crypto capabilities (cipher instructions).
+ a->z_bre(getCIPHERFEATURES_KMCTR);
+ a->z_cghi(Z_R0, -19); // -19: Extract detailed crypto capabilities (cipher instructions).
+ a->z_bre(getCIPHERFEATURES_KMO);
+ a->z_cghi(Z_R0, -20); // -20: Extract detailed crypto capabilities (cipher instructions).
+ a->z_bre(getCIPHERFEATURES_KMA);
+
a->z_xgr(Z_RET, Z_RET); // Not a valid function code.
a->z_br(Z_R14); // Return "operation aborted".
@@ -778,20 +1000,52 @@
a->bind(getMSGDIGESTFEATURES);
a->z_lghi(Z_R0,(int)MsgDigest::_Query); // query function code
a->z_lgr(Z_R1,Z_R2); // param block addr, 2*16 bytes min size
- a->z_kimd(Z_R2,Z_R2); // Get available KIMD functions (bit pattern in param blk).
+ a->z_kimd(Z_R2,Z_R2); // Get available KIMD functions (bit pattern in param blk). Must use even regs.
a->z_la(Z_R1,16,Z_R1); // next param block addr
- a->z_klmd(Z_R2,Z_R2); // Get available KLMD functions (bit pattern in param blk).
- a->z_lghi(Z_RET,4);
+ a->z_klmd(Z_R2,Z_R4); // Get available KLMD functions (bit pattern in param blk). Must use distinct even regs.
+ a->z_lghi(Z_RET,4); // #used words in output buffer
a->z_br(Z_R14);
// Try KM/KMC query function to get details about crypto instructions.
- a->bind(getCIPHERFEATURES);
+ a->bind(getCIPHERFEATURES_KM);
a->z_lghi(Z_R0,(int)Cipher::_Query); // query function code
a->z_lgr(Z_R1,Z_R2); // param block addr, 2*16 bytes min size (KIMD/KLMD output)
- a->z_km(Z_R2,Z_R2); // get available KM functions
+ a->z_km(Z_R2,Z_R2); // get available KM functions. Must use even regs.
a->z_la(Z_R1,16,Z_R1); // next param block addr
a->z_kmc(Z_R2,Z_R2); // get available KMC functions
- a->z_lghi(Z_RET,4);
+ a->z_lghi(Z_RET,4); // #used words in output buffer
+ a->z_br(Z_R14);
+
+ // Try KMA query function to get details about crypto instructions.
+ a->bind(getCIPHERFEATURES_KMA);
+ a->z_lghi(Z_R0,(int)Cipher::_Query); // query function code
+ a->z_lgr(Z_R1,Z_R2); // param block addr, 2*16 bytes min size (KIMD/KLMD output)
+ a->z_kma(Z_R2,Z_R4,Z_R6); // get available KMA functions. Must use distinct even regs.
+ a->z_lghi(Z_RET,2); // #used words in output buffer
+ a->z_br(Z_R14);
+
+ // Try KMF query function to get details about crypto instructions.
+ a->bind(getCIPHERFEATURES_KMF);
+ a->z_lghi(Z_R0,(int)Cipher::_Query); // query function code
+ a->z_lgr(Z_R1,Z_R2); // param block addr, 2*16 bytes min size (KIMD/KLMD output)
+ a->z_kmf(Z_R2,Z_R2); // get available KMA functions. Must use even regs.
+ a->z_lghi(Z_RET,2); // #used words in output buffer
+ a->z_br(Z_R14);
+
+ // Try KMCTR query function to get details about crypto instructions.
+ a->bind(getCIPHERFEATURES_KMCTR);
+ a->z_lghi(Z_R0,(int)Cipher::_Query); // query function code
+ a->z_lgr(Z_R1,Z_R2); // param block addr, 2*16 bytes min size (KIMD/KLMD output)
+ a->z_kmctr(Z_R2,Z_R2,Z_R2); // get available KMCTR functions. Must use even regs.
+ a->z_lghi(Z_RET,2); // #used words in output buffer
+ a->z_br(Z_R14);
+
+ // Try KMO query function to get details about crypto instructions.
+ a->bind(getCIPHERFEATURES_KMO);
+ a->z_lghi(Z_R0,(int)Cipher::_Query); // query function code
+ a->z_lgr(Z_R1,Z_R2); // param block addr, 2*16 bytes min size (KIMD/KLMD output)
+ a->z_kmo(Z_R2,Z_R2); // get available KMO functions. Must use even regs.
+ a->z_lghi(Z_RET,2); // #used words in output buffer
a->z_br(Z_R14);
// Use EXTRACT CPU ATTRIBUTE instruction to get information about cache layout.
@@ -820,14 +1074,9 @@
Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
}
- // Prepare for detection code execution and clear work buffer.
- _nfeatures = 0;
- _ncipher_features = 0;
+ // prepare work buffer
unsigned long buffer[buf_len];
-
- for (int i = 0; i < buf_len; i++) {
- buffer[i] = 0L;
- }
+ clear_buffer(buffer, buf_len);
// execute code
// Illegal instructions will be replaced by 0 in signal handler.
@@ -835,40 +1084,37 @@
long used_len = call_getFeatures(buffer, buf_len, 0);
bool ok;
- if (used_len == 1) {
- ok = true;
- } else if (used_len > 1) {
- unsigned int used_lenU = (unsigned int)used_len;
+ if ((used_len > 0) && (used_len <= buf_len)) {
ok = true;
- for (unsigned int i = 1; i < used_lenU; i++) {
- ok = ok && (buffer[i] == 0L);
- }
- if (printVerbose && !ok) {
- bool compact = false;
- tty->print_cr("Note: feature list has %d (i.e. more than one) array elements.", used_lenU);
+ if (printVerbose) {
+ bool compact = Verbose;
+ tty->print_cr("Note: feature list uses %ld array elements.", used_len);
if (compact) {
tty->print("non-zero feature list elements:");
- for (unsigned int i = 0; i < used_lenU; i++) {
- tty->print(" [%d]: 0x%16.16lx", i, buffer[i]);
+ for (unsigned int k = 0; k < used_len; k++) {
+ if (buffer[k] != 0) {
+ tty->print(" [%d]: 0x%16.16lx", k, buffer[k]);
+ }
}
tty->cr();
} else {
- for (unsigned int i = 0; i < used_lenU; i++) {
- tty->print_cr("non-zero feature list[%d]: 0x%16.16lx", i, buffer[i]);
+ for (unsigned int k = 0; k < used_len; k++) {
+ tty->print_cr("non-zero feature list[%d]: 0x%16.16lx", k, buffer[k]);
}
}
if (compact) {
tty->print_cr("Active features (compact view):");
- for (unsigned int k = 0; k < used_lenU; k++) {
+ for (unsigned int k = 0; k < used_len; k++) {
tty->print_cr(" buffer[%d]:", k);
for (unsigned int j = k*sizeof(long); j < (k+1)*sizeof(long); j++) {
bool line = false;
for (unsigned int i = j*8; i < (j+1)*8; i++) {
- bool bit = test_feature_bit(buffer, i, used_lenU*sizeof(long)*8);
+ bool bit = test_feature_bit(buffer, i, used_len*sizeof(long)*8);
if (bit) {
if (!line) {
tty->print(" byte[%d]:", j);
+ tty->fill_to(13);
line = true;
}
tty->print(" [%3.3d]", i);
@@ -881,12 +1127,13 @@
}
} else {
tty->print_cr("Active features (full view):");
- for (unsigned int k = 0; k < used_lenU; k++) {
+ for (unsigned int k = 0; k < used_len; k++) {
tty->print_cr(" buffer[%d]:", k);
for (unsigned int j = k*sizeof(long); j < (k+1)*sizeof(long); j++) {
tty->print(" byte[%d]:", j);
+ tty->fill_to(13);
for (unsigned int i = j*8; i < (j+1)*8; i++) {
- bool bit = test_feature_bit(buffer, i, used_lenU*sizeof(long)*8);
+ bool bit = test_feature_bit(buffer, i, used_len*sizeof(long)*8);
if (bit) {
tty->print(" [%3.3d]", i);
} else {
@@ -898,69 +1145,32 @@
}
}
}
- ok = true;
} else { // No features retrieved if we reach here. Buffer too short or instr not available.
+ ok = false;
if (used_len < 0) {
- ok = false;
if (printVerbose) {
tty->print_cr("feature list buffer[%d] too short, required: buffer[%ld]", buf_len, -used_len);
}
} else {
if (printVerbose) {
- tty->print_cr("feature list could not be retrieved. Running on z900 or z990? Trying to find out...");
- }
- used_len = call_getFeatures(buffer, 0, 0); // Must provide at least two DW buffer elements!!!!
-
- ok = used_len > 0;
- if (ok) {
- if (buffer[1]*10 < buffer[0]) {
- set_features_z900();
- } else {
- set_features_z990();
- }
-
- if (printVerbose) {
- tty->print_cr("Note: high-speed long displacement test used %ld iterations.", used_len);
- tty->print_cr(" Positive displacement loads took %8.8lu microseconds.", buffer[1]);
- tty->print_cr(" Negative displacement loads took %8.8lu microseconds.", buffer[0]);
- if (has_long_displacement_fast()) {
- tty->print_cr(" assuming high-speed long displacement IS available.");
- } else {
- tty->print_cr(" assuming high-speed long displacement is NOT available.");
- }
- }
- } else {
- if (printVerbose) {
- tty->print_cr("Note: high-speed long displacement test was not successful.");
- tty->print_cr(" assuming long displacement is NOT available.");
- }
+ tty->print_cr("feature list could not be retrieved. Bad function code? Running on z900 or z990?");
}
- return; // Do not copy buffer to _features, no test for cipher features.
}
}
if (ok) {
- // Fill features buffer.
- // Clear work buffer.
- for (int i = 0; i < buf_len; i++) {
- _features[i] = buffer[i];
- _cipher_features[i] = 0;
- _msgdigest_features[i] = 0;
- buffer[i] = 0L;
- }
+ // Copy detected features to features buffer.
+ copy_buffer(_features, buffer, buf_len);
_nfeatures = used_len;
} else {
- for (int i = 0; i < buf_len; i++) {
- _features[i] = 0;
- _cipher_features[i] = 0;
- _msgdigest_features[i] = 0;
- buffer[i] = 0L;
- }
+ // Something went wrong with feature detection. Disable everything.
+ clear_buffer(_features, buf_len);
_nfeatures = 0;
}
if (has_VectorFacility()) {
// Verify that feature can actually be used. OS support required.
+ // We will get a signal if not. Signal handler will disable vector facility
call_getFeatures(buffer, -4, 0);
if (printVerbose) {
ttyLocker ttyl;
@@ -972,23 +1182,69 @@
}
}
- // Extract Crypto Facility details.
+ // Clear all Cipher feature buffers and the work buffer.
+ clear_buffer(_cipher_features_KM, buf_len);
+ clear_buffer(_cipher_features_KMA, buf_len);
+ clear_buffer(_cipher_features_KMF, buf_len);
+ clear_buffer(_cipher_features_KMCTR, buf_len);
+ clear_buffer(_cipher_features_KMO, buf_len);
+ clear_buffer(_msgdigest_features, buf_len);
+ _ncipher_features_KM = 0;
+ _ncipher_features_KMA = 0;
+ _ncipher_features_KMF = 0;
+ _ncipher_features_KMCTR = 0;
+ _ncipher_features_KMO = 0;
+ _nmsgdigest_features = 0;
+
+ //---------------------------------------
+ //-- Extract Crypto Facility details --
+ //---------------------------------------
+
if (has_Crypto()) {
- // Get cipher features.
+ // Get features of KM/KMC cipher instructions
+ clear_buffer(buffer, buf_len);
used_len = call_getFeatures(buffer, -2, 0);
- for (int i = 0; i < buf_len; i++) {
- _cipher_features[i] = buffer[i];
- }
- _ncipher_features = used_len;
+ copy_buffer(_cipher_features_KM, buffer, buf_len);
+ _ncipher_features_KM = used_len;
// Get msg digest features.
+ clear_buffer(buffer, buf_len);
used_len = call_getFeatures(buffer, -3, 0);
- for (int i = 0; i < buf_len; i++) {
- _msgdigest_features[i] = buffer[i];
- }
+ copy_buffer(_msgdigest_features, buffer, buf_len);
_nmsgdigest_features = used_len;
}
+ if (has_CryptoExt4()) {
+ // Get features of KMF cipher instruction
+ clear_buffer(buffer, buf_len);
+ used_len = call_getFeatures(buffer, -17, 0);
+ copy_buffer(_cipher_features_KMF, buffer, buf_len);
+ _ncipher_features_KMF = used_len;
+
+ // Get features of KMCTR cipher instruction
+ clear_buffer(buffer, buf_len);
+ used_len = call_getFeatures(buffer, -18, 0);
+ copy_buffer(_cipher_features_KMCTR, buffer, buf_len);
+ _ncipher_features_KMCTR = used_len;
+
+ // Get features of KMO cipher instruction
+ clear_buffer(buffer, buf_len);
+ used_len = call_getFeatures(buffer, -19, 0);
+ copy_buffer(_cipher_features_KMO, buffer, buf_len);
+ _ncipher_features_KMO = used_len;
+ }
+
+ if (has_CryptoExt8()) {
+ // Get features of KMA cipher instruction
+ clear_buffer(buffer, buf_len);
+ used_len = call_getFeatures(buffer, -20, 0);
+ copy_buffer(_cipher_features_KMA, buffer, buf_len);
+ _ncipher_features_KMA = used_len;
+ }
+ if (printVerbose) {
+ tty->print_cr(" Crypto capabilities retrieved.");
+ }
+
static int levelProperties[_max_cache_levels]; // All property indications per level.
static int levelScope[_max_cache_levels]; // private/shared
static const char* levelScopeText[4] = {"No cache ",
@@ -1222,4 +1478,3 @@
);
return ZeroBuffer;
}
-
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/s390/vm_version_s390.hpp openjdk-lts-11.0.14+9/src/hotspot/cpu/s390/vm_version_s390.hpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/s390/vm_version_s390.hpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/s390/vm_version_s390.hpp 2022-01-13 21:56:25.000000000 +0000
@@ -1,6 +1,6 @@
/*
- * Copyright (c) 2016, 2018, Oracle and/or its affiliates. All rights reserved.
- * Copyright (c) 2016, 2018 SAP SE. All rights reserved.
+ * Copyright (c) 2016, 2021, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2016, 2021 SAP SE. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@@ -27,27 +27,19 @@
#define CPU_S390_VM_VM_VERSION_S390_HPP
+#include "runtime/abstract_vm_version.hpp"
#include "runtime/globals_extension.hpp"
-#include "runtime/vm_version.hpp"
class VM_Version: public Abstract_VM_Version {
protected:
-// The following list contains the (approximate) announcement/availability
-// dates of the many System z generations in existence as of now which
-// implement the z/Architecture.
-// z900: 2000-10
-// z990: 2003-06
-// z9: 2005-09
-// z10: 2007-04
-// z10: 2008-02
-// z196: 2010-08
-// ec12: 2012-09
-// z13: 2015-03
-//
// z/Architecture is the name of the 64-bit extension of the 31-bit s390
// architecture.
//
+// For information concerning the life span of the individual
+// z/Architecture models, please check out the comments/tables
+// in vm_version_s390.cpp
+
// ----------------------------------------------
// --- FeatureBitString Bits 0.. 63 (DW[0]) ---
// ----------------------------------------------
@@ -55,7 +47,7 @@
// 04826048260482604
#define StoreFacilityListExtendedMask 0x0100000000000000UL // z9
#define ETF2Mask 0x0000800000000000UL // z900
-#define CryptoFacilityMask 0x0000400000000000UL // z990
+#define CryptoFacilityMask 0x0000400000000000UL // z990 (aka message-security assist)
#define LongDispFacilityMask 0x0000200000000000UL // z900 with microcode update
#define LongDispFacilityHighPerfMask 0x0000300000000000UL // z990
#define HFPMultiplyAndAddMask 0x0000080000000000UL // z990
@@ -94,11 +86,8 @@
#define LoadStoreConditional2Mask 0x0000000000000400UL // z13
#define CryptoExtension5Mask 0x0000000000000040UL // z13
// z13 end
-// Feature-DW[0] starts to fill up. Use of these masks is risky.
-#define TestFeature1ImplMask 0x0000000000000001UL
-#define TestFeature2ImplMask 0x0000000000000002UL
-#define TestFeature4ImplMask 0x0000000000000004UL
-#define TestFeature8ImplMask 0x0000000000000008UL
+#define MiscInstrExt2Mask 0x0000000000000020UL // z14
+#define MiscInstrExt3Mask 0x0000000000000004UL // z15
// ----------------------------------------------
// --- FeatureBitString Bits 64..127 (DW[1]) ---
// ----------------------------------------------
@@ -107,7 +96,7 @@
// 48260482604826048
#define TransactionalExecutionMask 0x0040000000000000UL // ec12
#define CryptoExtension3Mask 0x0008000000000000UL // z196
-#define CryptoExtension4Mask 0x0004000000000000UL // z196
+#define CryptoExtension4Mask 0x0004000000000000UL // z196 (aka message-security assist extension 4, for KMF, KMCTR, KMO)
#define DFPPackedConversionMask 0x0000800000000000UL // z13
// ----------------------------------------------
// --- FeatureBitString Bits 128..192 (DW[2]) ---
@@ -116,6 +105,15 @@
// 23344455666778889
// 82604826048260482
#define VectorFacilityMask 0x4000000000000000UL // z13, not avail in VM guest mode!
+#define ExecutionProtectionMask 0x2000000000000000UL // z14
+#define GuardedStorageMask 0x0400000000000000UL // z14
+#define VectorEnhancements1Mask 0x0100000000000000UL // z14
+#define VectorPackedDecimalMask 0x0200000000000000UL // z14
+#define CryptoExtension8Mask 0x0000200000000000UL // z14 (aka message-security assist extension 8, for KMA)
+#define VectorEnhancements2Mask 0x0000080000000000UL // z15
+#define VectorPackedDecimalEnhMask 0x0000008000000000UL // z15
+#define CryptoExtension9Mask 0x0000001000000000UL // z15 (aka message-security assist extension 9)
+#define DeflateMask 0x0000010000000000UL // z15
enum {
_max_cache_levels = 8, // As limited by ECAG instruction.
@@ -123,10 +121,18 @@
_code_buffer_len = 2*256 // For feature detection code.
};
static unsigned long _features[_features_buffer_len];
- static unsigned long _cipher_features[_features_buffer_len];
+ static unsigned long _cipher_features_KM[_features_buffer_len];
+ static unsigned long _cipher_features_KMA[_features_buffer_len];
+ static unsigned long _cipher_features_KMF[_features_buffer_len];
+ static unsigned long _cipher_features_KMCTR[_features_buffer_len];
+ static unsigned long _cipher_features_KMO[_features_buffer_len];
static unsigned long _msgdigest_features[_features_buffer_len];
static unsigned int _nfeatures;
- static unsigned int _ncipher_features;
+ static unsigned int _ncipher_features_KM;
+ static unsigned int _ncipher_features_KMA;
+ static unsigned int _ncipher_features_KMF;
+ static unsigned int _ncipher_features_KMCTR;
+ static unsigned int _ncipher_features_KMO;
static unsigned int _nmsgdigest_features;
static unsigned int _Dcache_lineSize;
static unsigned int _Icache_lineSize;
@@ -134,16 +140,19 @@
static const char* _model_string;
static bool test_feature_bit(unsigned long* featureBuffer, int featureNum, unsigned int bufLen);
+ static int get_model_index();
static void set_features_string();
static void print_features_internal(const char* text, bool print_anyway=false);
static void determine_features();
static long call_getFeatures(unsigned long* buffer, int buflen, int functionCode);
static void set_getFeatures(address entryPoint);
+ static void clear_buffer(unsigned long* buffer, unsigned int len);
+ static void copy_buffer(unsigned long* to, unsigned long* from, unsigned int len);
static int calculate_ECAG_functionCode(unsigned int attributeIndication,
unsigned int levelIndication,
unsigned int typeIndication);
- // Setting features via march=z900|z990|z9|z10|z196|ec12|z13|ztest commandline option.
+ // Setting features via march=z900|z990|z9|z10|z196|ec12|z13|z14|z15 commandline option.
static void reset_features(bool reset);
static void set_features_z900(bool reset = true);
static void set_features_z990(bool reset = true);
@@ -152,8 +161,17 @@
static void set_features_z196(bool reset = true);
static void set_features_ec12(bool reset = true);
static void set_features_z13(bool reset = true);
+ static void set_features_z14(bool reset = true);
+ static void set_features_z15(bool reset = true);
static void set_features_from(const char* march);
+ // Get information about cache line sizes.
+ // As of now and the foreseeable future, line size of all levels will be the same and 256.
+ static unsigned int Dcache_lineSize(unsigned int level = 0) { return _Dcache_lineSize; }
+ static unsigned int Icache_lineSize(unsigned int level = 0) { return _Icache_lineSize; }
+
+ public:
+
// Get the CPU type from feature bit settings.
static bool is_z900() { return has_long_displacement() && !has_long_displacement_fast(); }
static bool is_z990() { return has_long_displacement_fast() && !has_extended_immediate(); }
@@ -161,14 +179,9 @@
static bool is_z10() { return has_GnrlInstrExtensions() && !has_DistinctOpnds(); }
static bool is_z196() { return has_DistinctOpnds() && !has_MiscInstrExt(); }
static bool is_ec12() { return has_MiscInstrExt() && !has_CryptoExt5(); }
- static bool is_z13() { return has_CryptoExt5();}
-
- // Get information about cache line sizes.
- // As of now and the foreseeable future, line size of all levels will be the same and 256.
- static unsigned int Dcache_lineSize(unsigned int level = 0) { return _Dcache_lineSize; }
- static unsigned int Icache_lineSize(unsigned int level = 0) { return _Icache_lineSize; }
-
- public:
+ static bool is_z13() { return has_CryptoExt5() && !has_MiscInstrExt2();}
+ static bool is_z14() { return has_MiscInstrExt2() && !has_MiscInstrExt3();}
+ static bool is_z15() { return has_MiscInstrExt3();}
// Need to use nested class with unscoped enum.
// C++11 declaration "enum class Cipher { ... } is not supported.
@@ -265,32 +278,56 @@
class MsgDigest {
public:
enum {
- _Query = 0,
- _SHA1 = 1,
- _SHA256 = 2,
- _SHA512 = 3,
- _GHASH = 65,
- _featureBits = 128,
+ _Query = 0,
+ _SHA1 = 1,
+ _SHA256 = 2,
+ _SHA512 = 3,
+ _SHA3_224 = 32,
+ _SHA3_256 = 33,
+ _SHA3_384 = 34,
+ _SHA3_512 = 35,
+ _SHAKE_128 = 36,
+ _SHAKE_256 = 37,
+ _GHASH = 65,
+ _featureBits = 128,
// Parameter block sizes (in bytes) for KIMD.
- _Query_parmBlk_I = 16,
- _SHA1_parmBlk_I = 20,
- _SHA256_parmBlk_I = 32,
- _SHA512_parmBlk_I = 64,
- _GHASH_parmBlk_I = 32,
+ _Query_parmBlk_I = 16,
+ _SHA1_parmBlk_I = 20,
+ _SHA256_parmBlk_I = 32,
+ _SHA512_parmBlk_I = 64,
+ _SHA3_224_parmBlk_I = 200,
+ _SHA3_256_parmBlk_I = 200,
+ _SHA3_384_parmBlk_I = 200,
+ _SHA3_512_parmBlk_I = 200,
+ _SHAKE_128_parmBlk_I = 200,
+ _SHAKE_256_parmBlk_I = 200,
+ _GHASH_parmBlk_I = 32,
// Parameter block sizes (in bytes) for KLMD.
- _Query_parmBlk_L = 16,
- _SHA1_parmBlk_L = 28,
- _SHA256_parmBlk_L = 40,
- _SHA512_parmBlk_L = 80,
+ _Query_parmBlk_L = 16,
+ _SHA1_parmBlk_L = 28,
+ _SHA256_parmBlk_L = 40,
+ _SHA512_parmBlk_L = 80,
+ _SHA3_224_parmBlk_L = 200,
+ _SHA3_256_parmBlk_L = 200,
+ _SHA3_384_parmBlk_L = 200,
+ _SHA3_512_parmBlk_L = 200,
+ _SHAKE_128_parmBlk_L = 200,
+ _SHAKE_256_parmBlk_L = 200,
// Data block sizes (in bytes).
- _Query_dataBlk = 0,
- _SHA1_dataBlk = 64,
- _SHA256_dataBlk = 64,
- _SHA512_dataBlk = 128,
- _GHASH_dataBlk = 16
+ _Query_dataBlk = 0,
+ _SHA1_dataBlk = 64,
+ _SHA256_dataBlk = 64,
+ _SHA512_dataBlk = 128,
+ _SHA3_224_dataBlk = 144,
+ _SHA3_256_dataBlk = 136,
+ _SHA3_384_dataBlk = 104,
+ _SHA3_512_dataBlk = 72,
+ _SHAKE_128_dataBlk = 168,
+ _SHAKE_256_dataBlk = 136,
+ _GHASH_dataBlk = 16
};
};
class MsgAuthent {
@@ -394,11 +431,11 @@
static bool has_HighWordInstr() { return (_features[0] & HighWordMask) == HighWordMask; }
static bool has_FastSync() { return (_features[0] & FastBCRSerializationMask) == FastBCRSerializationMask; }
static bool has_DistinctOpnds() { return (_features[0] & DistinctOpndsMask) == DistinctOpndsMask; }
- static bool has_CryptoExt3() { return (_features[1] & CryptoExtension3Mask) == CryptoExtension3Mask; }
- static bool has_CryptoExt4() { return (_features[1] & CryptoExtension4Mask) == CryptoExtension4Mask; }
static bool has_DFPZonedConversion() { return (_features[0] & DFPZonedConversionMask) == DFPZonedConversionMask; }
static bool has_DFPPackedConversion() { return (_features[1] & DFPPackedConversionMask) == DFPPackedConversionMask; }
static bool has_MiscInstrExt() { return (_features[0] & MiscInstrExtMask) == MiscInstrExtMask; }
+ static bool has_MiscInstrExt2() { return (_features[0] & MiscInstrExt2Mask) == MiscInstrExt2Mask; }
+ static bool has_MiscInstrExt3() { return (_features[0] & MiscInstrExt3Mask) == MiscInstrExt3Mask; }
static bool has_ExecutionHint() { return (_features[0] & ExecutionHintMask) == ExecutionHintMask; }
static bool has_LoadAndTrap() { return (_features[0] & LoadAndTrapMask) == LoadAndTrapMask; }
static bool has_ProcessorAssist() { return (_features[0] & ProcessorAssistMask) == ProcessorAssistMask; }
@@ -406,21 +443,22 @@
static bool has_LoadAndALUAtomicV2() { return (_features[0] & InterlockedAccess2Mask) == InterlockedAccess2Mask; }
static bool has_TxMem() { return ((_features[1] & TransactionalExecutionMask) == TransactionalExecutionMask) &&
((_features[0] & ConstrainedTxExecutionMask) == ConstrainedTxExecutionMask); }
+ static bool has_CryptoExt3() { return (_features[1] & CryptoExtension3Mask) == CryptoExtension3Mask; }
+ static bool has_CryptoExt4() { return (_features[1] & CryptoExtension4Mask) == CryptoExtension4Mask; }
static bool has_CryptoExt5() { return (_features[0] & CryptoExtension5Mask) == CryptoExtension5Mask; }
+ static bool has_CryptoExt8() { return (_features[2] & CryptoExtension8Mask) == CryptoExtension8Mask; }
+ static bool has_CryptoExt9() { return (_features[2] & CryptoExtension9Mask) == CryptoExtension9Mask; }
static bool has_LoadStoreConditional2() { return (_features[0] & LoadStoreConditional2Mask) == LoadStoreConditional2Mask; }
static bool has_VectorFacility() { return (_features[2] & VectorFacilityMask) == VectorFacilityMask; }
-
- static bool has_TestFeatureImpl() { return (_features[0] & TestFeature1ImplMask) == TestFeature1ImplMask; }
- static bool has_TestFeature1Impl() { return (_features[0] & TestFeature1ImplMask) == TestFeature1ImplMask; }
- static bool has_TestFeature2Impl() { return (_features[0] & TestFeature2ImplMask) == TestFeature2ImplMask; }
- static bool has_TestFeature4Impl() { return (_features[0] & TestFeature4ImplMask) == TestFeature4ImplMask; }
- static bool has_TestFeature8Impl() { return (_features[0] & TestFeature8ImplMask) == TestFeature8ImplMask; }
- static bool has_TestFeaturesImpl() { return has_TestFeature1Impl() || has_TestFeature2Impl() || has_TestFeature4Impl() || has_TestFeature8Impl(); }
+ static bool has_VectorEnhancements1() { return (_features[2] & VectorEnhancements1Mask) == VectorEnhancements1Mask; }
+ static bool has_VectorEnhancements2() { return (_features[2] & VectorEnhancements2Mask) == VectorEnhancements2Mask; }
+ static bool has_VectorPackedDecimal() { return (_features[2] & VectorPackedDecimalMask) == VectorPackedDecimalMask; }
+ static bool has_VectorPackedDecimalEnh() { return (_features[2] & VectorPackedDecimalEnhMask) == VectorPackedDecimalEnhMask; }
// Crypto features query functions.
- static bool has_Crypto_AES128() { return has_Crypto() && test_feature_bit(&_cipher_features[0], Cipher::_AES128, Cipher::_featureBits); }
- static bool has_Crypto_AES192() { return has_Crypto() && test_feature_bit(&_cipher_features[0], Cipher::_AES192, Cipher::_featureBits); }
- static bool has_Crypto_AES256() { return has_Crypto() && test_feature_bit(&_cipher_features[0], Cipher::_AES256, Cipher::_featureBits); }
+ static bool has_Crypto_AES128() { return has_Crypto() && test_feature_bit(&_cipher_features_KM[0], Cipher::_AES128, Cipher::_featureBits); }
+ static bool has_Crypto_AES192() { return has_Crypto() && test_feature_bit(&_cipher_features_KM[0], Cipher::_AES192, Cipher::_featureBits); }
+ static bool has_Crypto_AES256() { return has_Crypto() && test_feature_bit(&_cipher_features_KM[0], Cipher::_AES256, Cipher::_featureBits); }
static bool has_Crypto_AES() { return has_Crypto_AES128() || has_Crypto_AES192() || has_Crypto_AES256(); }
static bool has_Crypto_SHA1() { return has_Crypto() && test_feature_bit(&_msgdigest_features[0], MsgDigest::_SHA1, MsgDigest::_featureBits); }
@@ -430,10 +468,6 @@
static bool has_Crypto_SHA() { return has_Crypto_SHA1() || has_Crypto_SHA256() || has_Crypto_SHA512() || has_Crypto_GHASH(); }
// CPU feature setters (to force model-specific behaviour). Test/debugging only.
- static void set_has_TestFeature1Impl() { _features[0] |= TestFeature1ImplMask; }
- static void set_has_TestFeature2Impl() { _features[0] |= TestFeature2ImplMask; }
- static void set_has_TestFeature4Impl() { _features[0] |= TestFeature4ImplMask; }
- static void set_has_TestFeature8Impl() { _features[0] |= TestFeature8ImplMask; }
static void set_has_DecimalFloatingPoint() { _features[0] |= DecimalFloatingPointMask; }
static void set_has_FPSupportEnhancements() { _features[0] |= FPSupportEnhancementsMask; }
static void set_has_ExecuteExtensions() { _features[0] |= ExecuteExtensionsMask; }
@@ -468,15 +502,23 @@
static void set_has_DistinctOpnds() { _features[0] |= DistinctOpndsMask; }
static void set_has_FPExtensions() { _features[0] |= FPExtensionsMask; }
static void set_has_MiscInstrExt() { _features[0] |= MiscInstrExtMask; }
+ static void set_has_MiscInstrExt2() { _features[0] |= MiscInstrExt2Mask; }
+ static void set_has_MiscInstrExt3() { _features[0] |= MiscInstrExt3Mask; }
static void set_has_ProcessorAssist() { _features[0] |= ProcessorAssistMask; }
static void set_has_InterlockedAccessV2() { _features[0] |= InterlockedAccess2Mask; }
static void set_has_LoadAndALUAtomicV2() { _features[0] |= InterlockedAccess2Mask; }
static void set_has_TxMem() { _features[0] |= ConstrainedTxExecutionMask; _features[1] |= TransactionalExecutionMask; }
+ static void set_has_LoadStoreConditional2() { _features[0] |= LoadStoreConditional2Mask; }
static void set_has_CryptoExt3() { _features[1] |= CryptoExtension3Mask; }
static void set_has_CryptoExt4() { _features[1] |= CryptoExtension4Mask; }
- static void set_has_LoadStoreConditional2() { _features[0] |= LoadStoreConditional2Mask; }
static void set_has_CryptoExt5() { _features[0] |= CryptoExtension5Mask; }
+ static void set_has_CryptoExt8() { _features[2] |= CryptoExtension8Mask; }
+ static void set_has_CryptoExt9() { _features[2] |= CryptoExtension9Mask; }
static void set_has_VectorFacility() { _features[2] |= VectorFacilityMask; }
+ static void set_has_VectorEnhancements1() { _features[2] |= VectorEnhancements1Mask; }
+ static void set_has_VectorEnhancements2() { _features[2] |= VectorEnhancements2Mask; }
+ static void set_has_VectorPackedDecimal() { _features[2] |= VectorPackedDecimalMask; }
+ static void set_has_VectorPackedDecimalEnh() { _features[2] |= VectorPackedDecimalEnhMask; }
static void reset_has_VectorFacility() { _features[2] &= ~VectorFacilityMask; }
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/s390/vtableStubs_s390.cpp openjdk-lts-11.0.14+9/src/hotspot/cpu/s390/vtableStubs_s390.cpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/s390/vtableStubs_s390.cpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/s390/vtableStubs_s390.cpp 2022-01-13 21:56:25.000000000 +0000
@@ -1,6 +1,6 @@
/*
- * Copyright (c) 2016, 2018, Oracle and/or its affiliates. All rights reserved.
- * Copyright (c) 2016, 2018 SAP SE. All rights reserved.
+ * Copyright (c) 2016, 2021, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2016, 2021 SAP SE. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@@ -74,7 +74,7 @@
// Abuse Z_method as scratch register for generic emitter.
// It is loaded further down anyway before it is first used.
// No dynamic code size variance here, increment is 1, always.
- __ add2mem_32(Address(Z_R1_scratch), 1, Z_method);
+ __ add2mem_64(Address(Z_R1_scratch), 1, Z_method);
}
#endif
@@ -157,6 +157,7 @@
if (s == NULL) {
return NULL;
}
+
// Count unused bytes in instruction sequences of variable size.
// We add them to the computed buffer size in order to avoid
// overflow in subsequently generated stubs.
@@ -178,7 +179,7 @@
// Abuse Z_method as scratch register for generic emitter.
// It is loaded further down anyway before it is first used.
// No dynamic code size variance here, increment is 1, always.
- __ add2mem_32(Address(Z_R1_scratch), 1, Z_method);
+ __ add2mem_64(Address(Z_R1_scratch), 1, Z_method);
}
#endif
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/sparc/c2_globals_sparc.hpp openjdk-lts-11.0.14+9/src/hotspot/cpu/sparc/c2_globals_sparc.hpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/sparc/c2_globals_sparc.hpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/sparc/c2_globals_sparc.hpp 2022-01-13 21:56:25.000000000 +0000
@@ -80,7 +80,7 @@
// Ergonomics related flags
define_pd_global(uint64_t,MaxRAM, 128ULL*G);
-define_pd_global(uintx, CodeCacheMinBlockLength, 4);
+define_pd_global(uintx, CodeCacheMinBlockLength, 6);
define_pd_global(uintx, CodeCacheMinimumUseSpace, 400*K);
define_pd_global(bool, TrapBasedRangeChecks, false); // Not needed on sparc.
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/sparc/frame_sparc.cpp openjdk-lts-11.0.14+9/src/hotspot/cpu/sparc/frame_sparc.cpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/sparc/frame_sparc.cpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/sparc/frame_sparc.cpp 2022-01-13 21:56:25.000000000 +0000
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 1997, 2017, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@@ -648,7 +648,7 @@
Method* m = *interpreter_frame_method_addr();
// validate the method we'd find in this potential sender
- if (!m->is_valid_method()) return false;
+ if (!Method::is_valid_method(m)) return false;
// stack frames shouldn't be much larger than max_stack elements
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/sparc/vm_version_ext_sparc.hpp openjdk-lts-11.0.14+9/src/hotspot/cpu/sparc/vm_version_ext_sparc.hpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/sparc/vm_version_ext_sparc.hpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/sparc/vm_version_ext_sparc.hpp 2022-01-13 21:56:25.000000000 +0000
@@ -25,8 +25,8 @@
#ifndef CPU_SPARC_VM_VM_VERSION_EXT_SPARC_HPP
#define CPU_SPARC_VM_VM_VERSION_EXT_SPARC_HPP
+#include "runtime/vm_version.hpp"
#include "utilities/macros.hpp"
-#include "vm_version_sparc.hpp"
#if defined(SOLARIS)
#include
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/sparc/vm_version_sparc.cpp openjdk-lts-11.0.14+9/src/hotspot/cpu/sparc/vm_version_sparc.cpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/sparc/vm_version_sparc.cpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/sparc/vm_version_sparc.cpp 2022-01-13 21:56:25.000000000 +0000
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 1997, 2017, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 1997, 2019, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@@ -31,7 +31,7 @@
#include "runtime/java.hpp"
#include "runtime/os.hpp"
#include "runtime/stubCodeGenerator.hpp"
-#include "vm_version_sparc.hpp"
+#include "runtime/vm_version.hpp"
#include
@@ -160,7 +160,8 @@
// Use compare and branch instructions if available.
if (has_cbcond()) {
- if (FLAG_IS_DEFAULT(UseCBCond)) {
+ // cbcond suspected to cause issues on Athena CPUs
+ if (FLAG_IS_DEFAULT(UseCBCond) && !is_athena()) {
FLAG_SET_DEFAULT(UseCBCond, true);
}
} else if (UseCBCond) {
@@ -218,7 +219,7 @@
char buf[512];
jio_snprintf(buf, sizeof(buf),
- "%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s"
+ "%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s"
"%s%s%s%s%s%s%s%s%s" "%s%s%s%s%s%s%s%s%s"
"%s%s%s%s%s%s%s",
(has_v9() ? "v9" : ""),
@@ -228,6 +229,7 @@
(has_blk_init() ? ", blk_init" : ""),
(has_fmaf() ? ", fmaf" : ""),
(has_hpc() ? ", hpc" : ""),
+ (has_athena() ? ", athena" : ""),
(has_ima() ? ", ima" : ""),
(has_aes() ? ", aes" : ""),
(has_des() ? ", des" : ""),
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/sparc/vm_version_sparc.hpp openjdk-lts-11.0.14+9/src/hotspot/cpu/sparc/vm_version_sparc.hpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/sparc/vm_version_sparc.hpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/sparc/vm_version_sparc.hpp 2022-01-13 21:56:25.000000000 +0000
@@ -25,8 +25,8 @@
#ifndef CPU_SPARC_VM_VM_VERSION_SPARC_HPP
#define CPU_SPARC_VM_VM_VERSION_SPARC_HPP
+#include "runtime/abstract_vm_version.hpp"
#include "runtime/globals_extension.hpp"
-#include "runtime/vm_version.hpp"
class VM_Version: public Abstract_VM_Version {
friend class VMStructs;
@@ -42,6 +42,7 @@
ISA_FMAF,
ISA_VIS3,
ISA_HPC,
+ ISA_FJATHHPC,
ISA_IMA,
ISA_AES,
ISA_DES,
@@ -104,6 +105,7 @@
ISA_fmaf_msk = UINT64_C(1) << ISA_FMAF,
ISA_vis3_msk = UINT64_C(1) << ISA_VIS3,
ISA_hpc_msk = UINT64_C(1) << ISA_HPC,
+ ISA_fjathhpc_msk = UINT64_C(1) << ISA_FJATHHPC,
ISA_ima_msk = UINT64_C(1) << ISA_IMA,
ISA_aes_msk = UINT64_C(1) << ISA_AES,
ISA_des_msk = UINT64_C(1) << ISA_DES,
@@ -253,6 +255,7 @@
static bool has_fmaf() { return (_features & ISA_fmaf_msk) != 0; }
static bool has_vis3() { return (_features & ISA_vis3_msk) != 0; }
static bool has_hpc() { return (_features & ISA_hpc_msk) != 0; }
+ static bool has_athena() { return (_features & ISA_fjathhpc_msk) != 0; }
static bool has_ima() { return (_features & ISA_ima_msk) != 0; }
static bool has_aes() { return (_features & ISA_aes_msk) != 0; }
static bool has_des() { return (_features & ISA_des_msk) != 0; }
@@ -306,6 +309,10 @@
return (_features & niagara2_msk) == niagara2_msk;
}
+ static bool is_athena() {
+ return has_athena() || has_athena_plus() || has_athena_plus2();
+ }
+
// Default prefetch block size on SPARC.
static uint prefetch_data_size() { return L2_data_cache_line_size(); }
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/x86/assembler_x86.cpp openjdk-lts-11.0.14+9/src/hotspot/cpu/x86/assembler_x86.cpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/x86/assembler_x86.cpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/x86/assembler_x86.cpp 2022-01-13 21:56:25.000000000 +0000
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 1997, 2019, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@@ -4704,6 +4704,25 @@
emit_int8((unsigned char)0xA5);
}
+void Assembler::roundsd(XMMRegister dst, XMMRegister src, int32_t rmode) {
+ assert(VM_Version::supports_sse4_1(), "");
+ InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
+ int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
+ emit_int8(0x0B);
+ emit_int8((unsigned char)(0xC0 | encode));
+ emit_int8((unsigned char)rmode);
+}
+
+void Assembler::roundsd(XMMRegister dst, Address src, int32_t rmode) {
+ assert(VM_Version::supports_sse4_1(), "");
+ InstructionMark im(this);
+ InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
+ simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
+ emit_int8(0x0B);
+ emit_operand(dst, src);
+ emit_int8((unsigned char)rmode);
+}
+
void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) {
NOT_LP64(assert(VM_Version::supports_sse2(), ""));
InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
@@ -5501,6 +5520,49 @@
emit_operand(dst, src);
}
+void Assembler::vroundpd(XMMRegister dst, XMMRegister src, int32_t rmode, int vector_len) {
+ assert(VM_Version::supports_avx(), "");
+ InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
+ int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
+ emit_int8(0x09);
+ emit_int8((unsigned char)(0xC0 | encode));
+ emit_int8((unsigned char)(rmode));
+}
+
+void Assembler::vroundpd(XMMRegister dst, Address src, int32_t rmode, int vector_len) {
+ assert(VM_Version::supports_avx(), "");
+ InstructionMark im(this);
+ InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
+ vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
+ emit_int8(0x09);
+ emit_operand(dst, src);
+ emit_int8((unsigned char)(rmode));
+}
+
+void Assembler::vrndscalepd(XMMRegister dst, XMMRegister src, int32_t rmode, int vector_len) {
+ assert(VM_Version::supports_evex(), "requires EVEX support");
+ InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
+ attributes.set_is_evex_instruction();
+ int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
+ emit_int8((unsigned char)0x09);
+ emit_int8((unsigned char)(0xC0 | encode));
+ emit_int8((unsigned char)(rmode));
+}
+
+void Assembler::vrndscalepd(XMMRegister dst, Address src, int32_t rmode, int vector_len) {
+ assert(VM_Version::supports_evex(), "requires EVEX support");
+ assert(dst != xnoreg, "sanity");
+ InstructionMark im(this);
+ InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
+ attributes.set_is_evex_instruction();
+ attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
+ vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
+ emit_int8((unsigned char)0x09);
+ emit_operand(dst, src);
+ emit_int8((unsigned char)(rmode));
+}
+
+
void Assembler::vsqrtpd(XMMRegister dst, XMMRegister src, int vector_len) {
assert(VM_Version::supports_avx(), "");
InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
@@ -7889,9 +7951,43 @@
}
}
+void Assembler::vmaxss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
+ assert(VM_Version::supports_avx(), "");
+ InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
+ int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
+ emit_int8(0x5F);
+ emit_int8((unsigned char)(0xC0 | encode));
+}
+
+void Assembler::vmaxsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
+ assert(VM_Version::supports_avx(), "");
+ InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
+ attributes.set_rex_vex_w_reverted();
+ int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
+ emit_int8(0x5F);
+ emit_int8((unsigned char)(0xC0 | encode));
+}
+
+void Assembler::vminss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
+ assert(VM_Version::supports_avx(), "");
+ InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
+ int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
+ emit_int8(0x5D);
+ emit_int8((unsigned char)(0xC0 | encode));
+}
+
+void Assembler::vminsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
+ assert(VM_Version::supports_avx(), "");
+ InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
+ attributes.set_rex_vex_w_reverted();
+ int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
+ emit_int8(0x5D);
+ emit_int8((unsigned char)(0xC0 | encode));
+}
+
void Assembler::cmppd(XMMRegister dst, XMMRegister nds, XMMRegister src, int cop, int vector_len) {
assert(VM_Version::supports_avx(), "");
- assert(!VM_Version::supports_evex(), "");
+ assert(vector_len <= AVX_256bit, "");
InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
emit_int8((unsigned char)0xC2);
@@ -7912,7 +8008,7 @@
void Assembler::blendvpd(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len) {
assert(VM_Version::supports_avx(), "");
- assert(!VM_Version::supports_evex(), "");
+ assert(vector_len <= AVX_256bit, "");
InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
emit_int8((unsigned char)0x4B);
@@ -7923,7 +8019,7 @@
void Assembler::cmpps(XMMRegister dst, XMMRegister nds, XMMRegister src, int cop, int vector_len) {
assert(VM_Version::supports_avx(), "");
- assert(!VM_Version::supports_evex(), "");
+ assert(vector_len <= AVX_256bit, "");
InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
emit_int8((unsigned char)0xC2);
@@ -7933,7 +8029,7 @@
void Assembler::blendvps(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len) {
assert(VM_Version::supports_avx(), "");
- assert(!VM_Version::supports_evex(), "");
+ assert(vector_len <= AVX_256bit, "");
InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
emit_int8((unsigned char)0x4A);
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/x86/assembler_x86.hpp openjdk-lts-11.0.14+9/src/hotspot/cpu/x86/assembler_x86.hpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/x86/assembler_x86.hpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/x86/assembler_x86.hpp 2022-01-13 21:56:25.000000000 +0000
@@ -26,7 +26,7 @@
#define CPU_X86_VM_ASSEMBLER_X86_HPP
#include "asm/register.hpp"
-#include "vm_version_x86.hpp"
+#include "runtime/vm_version.hpp"
class BiasedLockingCounters;
@@ -1830,6 +1830,9 @@
void sqrtsd(XMMRegister dst, Address src);
void sqrtsd(XMMRegister dst, XMMRegister src);
+ void roundsd(XMMRegister dst, Address src, int32_t rmode);
+ void roundsd(XMMRegister dst, XMMRegister src, int32_t rmode);
+
// Compute Square Root of Scalar Single-Precision Floating-Point Value
void sqrtss(XMMRegister dst, Address src);
void sqrtss(XMMRegister dst, XMMRegister src);
@@ -1939,6 +1942,11 @@
void vsubss(XMMRegister dst, XMMRegister nds, Address src);
void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src);
+ void vmaxss(XMMRegister dst, XMMRegister nds, XMMRegister src);
+ void vmaxsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
+ void vminss(XMMRegister dst, XMMRegister nds, XMMRegister src);
+ void vminsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
+
void shlxl(Register dst, Register src1, Register src2);
void shlxq(Register dst, Register src1, Register src2);
@@ -1989,6 +1997,12 @@
void vsqrtps(XMMRegister dst, XMMRegister src, int vector_len);
void vsqrtps(XMMRegister dst, Address src, int vector_len);
+ // Round Packed Double precision value.
+ void vroundpd(XMMRegister dst, XMMRegister src, int32_t rmode, int vector_len);
+ void vroundpd(XMMRegister dst, Address src, int32_t rmode, int vector_len);
+ void vrndscalepd(XMMRegister dst, XMMRegister src, int32_t rmode, int vector_len);
+ void vrndscalepd(XMMRegister dst, Address src, int32_t rmode, int vector_len);
+
// Bitwise Logical AND of Packed Floating-Point Values
void andpd(XMMRegister dst, XMMRegister src);
void andps(XMMRegister dst, XMMRegister src);
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/x86/c1_LIRGenerator_x86.cpp openjdk-lts-11.0.14+9/src/hotspot/cpu/x86/c1_LIRGenerator_x86.cpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/x86/c1_LIRGenerator_x86.cpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/x86/c1_LIRGenerator_x86.cpp 2022-01-13 21:56:25.000000000 +0000
@@ -188,8 +188,32 @@
LIR_Address* addr;
if (index_opr->is_constant()) {
int elem_size = type2aelembytes(type);
- addr = new LIR_Address(array_opr,
- offset_in_bytes + (intx)(index_opr->as_jint()) * elem_size, type);
+#ifdef _LP64
+ jint index = index_opr->as_jint();
+ jlong disp = offset_in_bytes + (jlong)(index) * elem_size;
+ if (disp > max_jint) {
+ // Displacement overflow. Cannot directly use instruction with 32-bit displacement for 64-bit addresses.
+ // Convert array index to long to do array offset computation with 64-bit values.
+ index_opr = new_register(T_LONG);
+ __ move(LIR_OprFact::longConst(index), index_opr);
+ addr = new LIR_Address(array_opr, index_opr, LIR_Address::scale(type), offset_in_bytes, type);
+ } else {
+ addr = new LIR_Address(array_opr, (intx)disp, type);
+ }
+#else
+ // A displacement overflow can also occur for x86 but that is not a problem due to the 32-bit address range!
+ // Let's assume an array 'a' and an access with displacement 'disp'. When disp overflows, then "a + disp" will
+ // always be negative (i.e. underflows the 32-bit address range):
+ // Let N = 2^32: a + signed_overflow(disp) = a + disp - N.
+ // "a + disp" is always smaller than N. If an index was chosen which would point to an address beyond N, then
+ // range checks would catch that and throw an exception. Thus, a + disp < 0 holds which means that it always
+ // underflows the 32-bit address range:
+ // unsigned_underflow(a + signed_overflow(disp)) = unsigned_underflow(a + disp - N)
+ // = (a + disp - N) + N = a + disp
+ // This shows that we still end up at the correct address with a displacement overflow due to the 32-bit address
+ // range limitation. This overflow only needs to be handled if addresses can be larger as on 64-bit platforms.
+ addr = new LIR_Address(array_opr, offset_in_bytes + (intx)(index_opr->as_jint()) * elem_size, type);
+#endif // _LP64
} else {
#ifdef _LP64
if (index_opr->type() == T_INT) {
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/x86/c2_globals_x86.hpp openjdk-lts-11.0.14+9/src/hotspot/cpu/x86/c2_globals_x86.hpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/x86/c2_globals_x86.hpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/x86/c2_globals_x86.hpp 2022-01-13 21:56:25.000000000 +0000
@@ -46,7 +46,7 @@
define_pd_global(intx, ConditionalMoveLimit, 3);
define_pd_global(intx, FreqInlineSize, 325);
define_pd_global(intx, MinJumpTableSize, 10);
-define_pd_global(intx, LoopPercentProfileLimit, 30);
+define_pd_global(intx, LoopPercentProfileLimit, 10);
#ifdef AMD64
define_pd_global(intx, INTPRESSURE, 13);
define_pd_global(intx, FLOATPRESSURE, 14);
@@ -88,7 +88,7 @@
define_pd_global(uintx, NonProfiledCodeHeapSize, 21*M);
define_pd_global(uintx, ProfiledCodeHeapSize, 22*M);
define_pd_global(uintx, NonNMethodCodeHeapSize, 5*M );
-define_pd_global(uintx, CodeCacheMinBlockLength, 4);
+define_pd_global(uintx, CodeCacheMinBlockLength, 6);
define_pd_global(uintx, CodeCacheMinimumUseSpace, 400*K);
define_pd_global(bool, TrapBasedRangeChecks, false); // Not needed on x86.
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/x86/frame_x86.cpp openjdk-lts-11.0.14+9/src/hotspot/cpu/x86/frame_x86.cpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/x86/frame_x86.cpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/x86/frame_x86.cpp 2022-01-13 21:56:25.000000000 +0000
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 1997, 2017, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@@ -526,7 +526,7 @@
Method* m = *interpreter_frame_method_addr();
// validate the method we'd find in this potential sender
- if (!m->is_valid_method()) return false;
+ if (!Method::is_valid_method(m)) return false;
// stack frames shouldn't be much larger than max_stack elements
// this test requires the use the unextended_sp which is the sp as seen by
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/x86/gc/shenandoah/shenandoahBarrierSetAssembler_x86.cpp openjdk-lts-11.0.14+9/src/hotspot/cpu/x86/gc/shenandoah/shenandoahBarrierSetAssembler_x86.cpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/x86/gc/shenandoah/shenandoahBarrierSetAssembler_x86.cpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/x86/gc/shenandoah/shenandoahBarrierSetAssembler_x86.cpp 2022-01-13 21:56:25.000000000 +0000
@@ -46,6 +46,77 @@
address ShenandoahBarrierSetAssembler::_shenandoah_lrb = NULL;
+static void save_machine_state(MacroAssembler* masm, bool handle_gpr, bool handle_fp) {
+ if (handle_gpr) {
+ __ push_IU_state();
+ }
+
+ if (handle_fp) {
+ // Some paths can be reached from the c2i adapter with live fp arguments in registers.
+ LP64_ONLY(assert(Argument::n_float_register_parameters_j == 8, "8 fp registers to save at java call"));
+
+ if (UseSSE >= 2) {
+ const int xmm_size = wordSize * LP64_ONLY(2) NOT_LP64(4);
+ __ subptr(rsp, xmm_size * 8);
+ __ movdbl(Address(rsp, xmm_size * 0), xmm0);
+ __ movdbl(Address(rsp, xmm_size * 1), xmm1);
+ __ movdbl(Address(rsp, xmm_size * 2), xmm2);
+ __ movdbl(Address(rsp, xmm_size * 3), xmm3);
+ __ movdbl(Address(rsp, xmm_size * 4), xmm4);
+ __ movdbl(Address(rsp, xmm_size * 5), xmm5);
+ __ movdbl(Address(rsp, xmm_size * 6), xmm6);
+ __ movdbl(Address(rsp, xmm_size * 7), xmm7);
+ } else if (UseSSE >= 1) {
+ const int xmm_size = wordSize * LP64_ONLY(1) NOT_LP64(2);
+ __ subptr(rsp, xmm_size * 8);
+ __ movflt(Address(rsp, xmm_size * 0), xmm0);
+ __ movflt(Address(rsp, xmm_size * 1), xmm1);
+ __ movflt(Address(rsp, xmm_size * 2), xmm2);
+ __ movflt(Address(rsp, xmm_size * 3), xmm3);
+ __ movflt(Address(rsp, xmm_size * 4), xmm4);
+ __ movflt(Address(rsp, xmm_size * 5), xmm5);
+ __ movflt(Address(rsp, xmm_size * 6), xmm6);
+ __ movflt(Address(rsp, xmm_size * 7), xmm7);
+ } else {
+ __ push_FPU_state();
+ }
+ }
+}
+
+static void restore_machine_state(MacroAssembler* masm, bool handle_gpr, bool handle_fp) {
+ if (handle_fp) {
+ if (UseSSE >= 2) {
+ const int xmm_size = wordSize * LP64_ONLY(2) NOT_LP64(4);
+ __ movdbl(xmm0, Address(rsp, xmm_size * 0));
+ __ movdbl(xmm1, Address(rsp, xmm_size * 1));
+ __ movdbl(xmm2, Address(rsp, xmm_size * 2));
+ __ movdbl(xmm3, Address(rsp, xmm_size * 3));
+ __ movdbl(xmm4, Address(rsp, xmm_size * 4));
+ __ movdbl(xmm5, Address(rsp, xmm_size * 5));
+ __ movdbl(xmm6, Address(rsp, xmm_size * 6));
+ __ movdbl(xmm7, Address(rsp, xmm_size * 7));
+ __ addptr(rsp, xmm_size * 8);
+ } else if (UseSSE >= 1) {
+ const int xmm_size = wordSize * LP64_ONLY(1) NOT_LP64(2);
+ __ movflt(xmm0, Address(rsp, xmm_size * 0));
+ __ movflt(xmm1, Address(rsp, xmm_size * 1));
+ __ movflt(xmm2, Address(rsp, xmm_size * 2));
+ __ movflt(xmm3, Address(rsp, xmm_size * 3));
+ __ movflt(xmm4, Address(rsp, xmm_size * 4));
+ __ movflt(xmm5, Address(rsp, xmm_size * 5));
+ __ movflt(xmm6, Address(rsp, xmm_size * 6));
+ __ movflt(xmm7, Address(rsp, xmm_size * 7));
+ __ addptr(rsp, xmm_size * 8);
+ } else {
+ __ pop_FPU_state();
+ }
+ }
+
+ if (handle_gpr) {
+ __ pop_IU_state();
+ }
+}
+
void ShenandoahBarrierSetAssembler::arraycopy_prologue(MacroAssembler* masm, DecoratorSet decorators, BasicType type,
Register src, Register dst, Register count) {
@@ -88,7 +159,7 @@
__ testb(gc_state, flags);
__ jcc(Assembler::zero, done);
- __ pusha(); // push registers
+ save_machine_state(masm, /* handle_gpr = */ true, /* handle_fp = */ false);
#ifdef _LP64
assert(src == rdi, "expected");
@@ -104,7 +175,8 @@
src, dst, count);
}
- __ popa();
+ restore_machine_state(masm, /* handle_gpr = */ true, /* handle_fp = */ false);
+
__ bind(done);
NOT_LP64(__ pop(thread);)
}
@@ -265,7 +337,9 @@
Address gc_state(thread, in_bytes(ShenandoahThreadLocalData::gc_state_offset()));
__ testb(gc_state, ShenandoahHeap::HAS_FORWARDED);
- __ jccb(Assembler::zero, done);
+ __ jcc(Assembler::zero, done);
+
+ save_machine_state(masm, /* handle_gpr = */ false, /* handle_fp = */ true);
// Use rsi for src address
const Register src_addr = rsi;
@@ -303,6 +377,8 @@
__ pop(rax);
}
+ restore_machine_state(masm, /* handle_gpr = */ false, /* handle_fp = */ true);
+
__ bind(done);
#ifndef _LP64
@@ -322,12 +398,7 @@
if (dst == noreg) return;
if (ShenandoahIUBarrier) {
- // The set of registers to be saved+restored is the same as in the write-barrier above.
- // Those are the commonly used registers in the interpreter.
- __ pusha();
- // __ push_callee_saved_registers();
- __ subptr(rsp, 2 * Interpreter::stackElementSize);
- __ movdbl(Address(rsp, 0), xmm0);
+ save_machine_state(masm, /* handle_gpr = */ true, /* handle_fp = */ true);
#ifdef _LP64
Register thread = r15_thread;
@@ -344,10 +415,8 @@
assert_different_registers(dst, tmp, thread);
satb_write_barrier_pre(masm, noreg, dst, thread, tmp, true, false);
- __ movdbl(xmm0, Address(rsp, 0));
- __ addptr(rsp, 2 * Interpreter::stackElementSize);
- //__ pop_callee_saved_registers();
- __ popa();
+
+ restore_machine_state(masm, /* handle_gpr = */ true, /* handle_fp = */ true);
}
}
@@ -422,19 +491,7 @@
// 3: apply keep-alive barrier if needed
if (ShenandoahBarrierSet::need_keep_alive_barrier(decorators, type)) {
- __ push_IU_state();
- // That path can be reached from the c2i adapter with live fp
- // arguments in registers.
- LP64_ONLY(assert(Argument::n_float_register_parameters_j == 8, "8 fp registers to save at java call"));
- __ subptr(rsp, 64);
- __ movdbl(Address(rsp, 0), xmm0);
- __ movdbl(Address(rsp, 8), xmm1);
- __ movdbl(Address(rsp, 16), xmm2);
- __ movdbl(Address(rsp, 24), xmm3);
- __ movdbl(Address(rsp, 32), xmm4);
- __ movdbl(Address(rsp, 40), xmm5);
- __ movdbl(Address(rsp, 48), xmm6);
- __ movdbl(Address(rsp, 56), xmm7);
+ save_machine_state(masm, /* handle_gpr = */ true, /* handle_fp = */ true);
Register thread = NOT_LP64(tmp_thread) LP64_ONLY(r15_thread);
assert_different_registers(dst, tmp1, tmp_thread);
@@ -451,16 +508,8 @@
tmp1 /* tmp */,
true /* tosca_live */,
true /* expand_call */);
- __ movdbl(xmm0, Address(rsp, 0));
- __ movdbl(xmm1, Address(rsp, 8));
- __ movdbl(xmm2, Address(rsp, 16));
- __ movdbl(xmm3, Address(rsp, 24));
- __ movdbl(xmm4, Address(rsp, 32));
- __ movdbl(xmm5, Address(rsp, 40));
- __ movdbl(xmm6, Address(rsp, 48));
- __ movdbl(xmm7, Address(rsp, 56));
- __ addptr(rsp, 64);
- __ pop_IU_state();
+
+ restore_machine_state(masm, /* handle_gpr = */ true, /* handle_fp = */ true);
}
}
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/x86/macroAssembler_x86.cpp openjdk-lts-11.0.14+9/src/hotspot/cpu/x86/macroAssembler_x86.cpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/x86/macroAssembler_x86.cpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/x86/macroAssembler_x86.cpp 2022-01-13 21:56:25.000000000 +0000
@@ -3894,6 +3894,15 @@
}
}
+void MacroAssembler::roundsd(XMMRegister dst, AddressLiteral src, int32_t rmode, Register scratch_reg) {
+ if (reachable(src)) {
+ Assembler::roundsd(dst, as_Address(src), rmode);
+ } else {
+ lea(scratch_reg, src);
+ Assembler::roundsd(dst, Address(scratch_reg, 0), rmode);
+ }
+}
+
void MacroAssembler::subss(XMMRegister dst, AddressLiteral src) {
if (reachable(src)) {
Assembler::subss(dst, as_Address(src));
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/x86/macroAssembler_x86.hpp openjdk-lts-11.0.14+9/src/hotspot/cpu/x86/macroAssembler_x86.hpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/x86/macroAssembler_x86.hpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/x86/macroAssembler_x86.hpp 2022-01-13 21:56:25.000000000 +0000
@@ -164,6 +164,7 @@
// Support optimal SSE move instructions.
void movflt(XMMRegister dst, XMMRegister src) {
+ if (dst-> encoding() == src->encoding()) return;
if (UseXmmRegToRegMoveAll) { movaps(dst, src); return; }
else { movss (dst, src); return; }
}
@@ -172,6 +173,7 @@
void movflt(Address dst, XMMRegister src) { movss(dst, src); }
void movdbl(XMMRegister dst, XMMRegister src) {
+ if (dst-> encoding() == src->encoding()) return;
if (UseXmmRegToRegMoveAll) { movapd(dst, src); return; }
else { movsd (dst, src); return; }
}
@@ -1169,6 +1171,10 @@
void sqrtsd(XMMRegister dst, Address src) { Assembler::sqrtsd(dst, src); }
void sqrtsd(XMMRegister dst, AddressLiteral src);
+ void roundsd(XMMRegister dst, XMMRegister src, int32_t rmode) { Assembler::roundsd(dst, src, rmode); }
+ void roundsd(XMMRegister dst, Address src, int32_t rmode) { Assembler::roundsd(dst, src, rmode); }
+ void roundsd(XMMRegister dst, AddressLiteral src, int32_t rmode, Register scratch_reg);
+
void sqrtss(XMMRegister dst, XMMRegister src) { Assembler::sqrtss(dst, src); }
void sqrtss(XMMRegister dst, Address src) { Assembler::sqrtss(dst, src); }
void sqrtss(XMMRegister dst, AddressLiteral src);
@@ -1339,7 +1345,7 @@
void vinserti128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
- Assembler::vinserti32x4(dst, dst, src, imm8);
+ Assembler::vinserti32x4(dst, nds, src, imm8);
} else if (UseAVX > 1) {
// vinserti128 is available only in AVX2
Assembler::vinserti128(dst, nds, src, imm8);
@@ -1350,7 +1356,7 @@
void vinserti128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
- Assembler::vinserti32x4(dst, dst, src, imm8);
+ Assembler::vinserti32x4(dst, nds, src, imm8);
} else if (UseAVX > 1) {
// vinserti128 is available only in AVX2
Assembler::vinserti128(dst, nds, src, imm8);
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/x86/register_x86.hpp openjdk-lts-11.0.14+9/src/hotspot/cpu/x86/register_x86.hpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/x86/register_x86.hpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/x86/register_x86.hpp 2022-01-13 21:56:25.000000000 +0000
@@ -50,7 +50,7 @@
#else
number_of_registers = 16,
number_of_byte_registers = 16,
- max_slots_per_register = 1
+ max_slots_per_register = 2
#endif // AMD64
};
@@ -274,10 +274,7 @@
// There is no requirement that any ordering here matches any ordering c2 gives
// it's optoregs.
- number_of_registers = RegisterImpl::number_of_registers +
-#ifdef AMD64
- RegisterImpl::number_of_registers + // "H" half of a 64bit register
-#endif // AMD64
+ number_of_registers = RegisterImpl::number_of_registers * RegisterImpl::max_slots_per_register +
2 * FloatRegisterImpl::number_of_registers +
XMMRegisterImpl::max_slots_per_register * XMMRegisterImpl::number_of_registers +
KRegisterImpl::number_of_registers + // mask registers
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/x86/sharedRuntime_x86_32.cpp openjdk-lts-11.0.14+9/src/hotspot/cpu/x86/sharedRuntime_x86_32.cpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/x86/sharedRuntime_x86_32.cpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/x86/sharedRuntime_x86_32.cpp 2022-01-13 21:56:25.000000000 +0000
@@ -37,6 +37,7 @@
#include "runtime/safepointMechanism.hpp"
#include "runtime/sharedRuntime.hpp"
#include "runtime/vframeArray.hpp"
+#include "runtime/vm_version.hpp"
#include "utilities/align.hpp"
#include "utilities/macros.hpp"
#include "vmreg_x86.inline.hpp"
@@ -46,7 +47,6 @@
#ifdef COMPILER2
#include "opto/runtime.hpp"
#endif
-#include "vm_version_x86.hpp"
#if INCLUDE_SHENANDOAHGC
#include "gc/shenandoah/shenandoahBarrierSet.hpp"
#include "gc/shenandoah/shenandoahBarrierSetAssembler.hpp"
@@ -315,18 +315,19 @@
}
if (restore_vectors) {
+ off = additional_frame_bytes - ymm_bytes;
+ // Restore upper half of YMM registers.
+ for (int n = 0; n < num_xmm_regs; n++) {
+ __ vinsertf128_high(as_XMMRegister(n), Address(rsp, n*16+off));
+ }
+
if (UseAVX > 2) {
// Restore upper half of ZMM registers.
for (int n = 0; n < num_xmm_regs; n++) {
__ vinsertf64x4_high(as_XMMRegister(n), Address(rsp, n*32));
}
- __ addptr(rsp, zmm_bytes);
- }
- // Restore upper half of YMM registers.
- for (int n = 0; n < num_xmm_regs; n++) {
- __ vinsertf128_high(as_XMMRegister(n), Address(rsp, n*16));
}
- __ addptr(rsp, ymm_bytes);
+ __ addptr(rsp, additional_frame_bytes);
}
__ pop_FPU_state();
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/x86/sharedRuntime_x86_64.cpp openjdk-lts-11.0.14+9/src/hotspot/cpu/x86/sharedRuntime_x86_64.cpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/x86/sharedRuntime_x86_64.cpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/x86/sharedRuntime_x86_64.cpp 2022-01-13 21:56:25.000000000 +0000
@@ -40,10 +40,10 @@
#include "runtime/safepointMechanism.hpp"
#include "runtime/sharedRuntime.hpp"
#include "runtime/vframeArray.hpp"
+#include "runtime/vm_version.hpp"
#include "utilities/align.hpp"
#include "utilities/formatBuffer.hpp"
#include "utilities/macros.hpp"
-#include "vm_version_x86.hpp"
#include "vmreg_x86.inline.hpp"
#ifdef COMPILER1
#include "c1/c1_Runtime1.hpp"
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/x86/templateTable_x86.cpp openjdk-lts-11.0.14+9/src/hotspot/cpu/x86/templateTable_x86.cpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/x86/templateTable_x86.cpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/x86/templateTable_x86.cpp 2022-01-13 21:56:25.000000000 +0000
@@ -2297,7 +2297,7 @@
__ dispatch_only(vtos, true);
if (UseLoopCounter) {
- if (ProfileInterpreter) {
+ if (ProfileInterpreter && !TieredCompilation) {
// Out-of-line code to allocate method data oop.
__ bind(profile_method);
__ call_VM(noreg, CAST_FROM_FN_PTR(address, InterpreterRuntime::profile_method));
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/x86/vm_version_ext_x86.hpp openjdk-lts-11.0.14+9/src/hotspot/cpu/x86/vm_version_ext_x86.hpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/x86/vm_version_ext_x86.hpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/x86/vm_version_ext_x86.hpp 2022-01-13 21:56:25.000000000 +0000
@@ -25,8 +25,8 @@
#ifndef CPU_X86_VM_VM_VERSION_EXT_X86_HPP
#define CPU_X86_VM_VM_VERSION_EXT_X86_HPP
+#include "runtime/vm_version.hpp"
#include "utilities/macros.hpp"
-#include "vm_version_x86.hpp"
class VM_Version_Ext : public VM_Version {
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/x86/vm_version_x86.cpp openjdk-lts-11.0.14+9/src/hotspot/cpu/x86/vm_version_x86.cpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/x86/vm_version_x86.cpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/x86/vm_version_x86.cpp 2022-01-13 21:56:25.000000000 +0000
@@ -32,8 +32,8 @@
#include "runtime/java.hpp"
#include "runtime/os.hpp"
#include "runtime/stubCodeGenerator.hpp"
+#include "runtime/vm_version.hpp"
#include "utilities/virtualizationSupport.hpp"
-#include "vm_version_x86.hpp"
int VM_Version::_cpu;
@@ -745,7 +745,7 @@
}
}
- char buf[256];
+ char buf[512];
jio_snprintf(buf, sizeof(buf),
"(%u cores per cpu, %u threads per core) family %d model %d stepping %d microcode 0x%x"
"%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/x86/vm_version_x86.hpp openjdk-lts-11.0.14+9/src/hotspot/cpu/x86/vm_version_x86.hpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/x86/vm_version_x86.hpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/x86/vm_version_x86.hpp 2022-01-13 21:56:25.000000000 +0000
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 1997, 2020, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 1997, 2021, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@@ -25,8 +25,8 @@
#ifndef CPU_X86_VM_VM_VERSION_X86_HPP
#define CPU_X86_VM_VM_VERSION_X86_HPP
+#include "runtime/abstract_vm_version.hpp"
#include "runtime/globals_extension.hpp"
-#include "runtime/vm_version.hpp"
class VM_Version : public Abstract_VM_Version {
friend class VMStructs;
@@ -940,6 +940,11 @@
// the intrinsic for java.lang.Thread.onSpinWait()
static bool supports_on_spin_wait() { return supports_sse2(); }
+#ifdef __APPLE__
+ // Is the CPU running emulated (for example macOS Rosetta running x86_64 code on M1 ARM (aarch64)
+ static bool is_cpu_emulated();
+#endif
+
// support functions for virtualization detection
private:
static void check_virtualizations();
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/x86/vtableStubs_x86_64.cpp openjdk-lts-11.0.14+9/src/hotspot/cpu/x86/vtableStubs_x86_64.cpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/x86/vtableStubs_x86_64.cpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/x86/vtableStubs_x86_64.cpp 2022-01-13 21:56:25.000000000 +0000
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2003, 2020, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2003, 2021, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@@ -69,7 +69,7 @@
#if (!defined(PRODUCT) && defined(COMPILER2))
if (CountCompiledCalls) {
- __ incrementl(ExternalAddress((address) SharedRuntime::nof_megamorphic_calls_addr()));
+ __ incrementq(ExternalAddress((address) SharedRuntime::nof_megamorphic_calls_addr()));
}
#endif
@@ -147,6 +147,7 @@
if (s == NULL) {
return NULL;
}
+
// Count unused bytes in instruction sequences of variable size.
// We add them to the computed buffer size in order to avoid
// overflow in subsequently generated stubs.
@@ -162,7 +163,7 @@
#if (!defined(PRODUCT) && defined(COMPILER2))
if (CountCompiledCalls) {
- __ incrementl(ExternalAddress((address) SharedRuntime::nof_megamorphic_calls_addr()));
+ __ incrementq(ExternalAddress((address) SharedRuntime::nof_megamorphic_calls_addr()));
}
#endif // PRODUCT
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/x86/x86_64.ad openjdk-lts-11.0.14+9/src/hotspot/cpu/x86/x86_64.ad
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/x86/x86_64.ad 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/x86/x86_64.ad 2022-01-13 21:56:25.000000000 +0000
@@ -826,6 +826,87 @@
__ bind(done);
}
+// Math.min() # Math.max()
+// --------------------------
+// ucomis[s/d] #
+// ja -> b # a
+// jp -> NaN # NaN
+// jb -> a # b
+// je #
+// |-jz -> a | b # a & b
+// | -> a #
+void emit_fp_min_max(MacroAssembler& _masm, XMMRegister dst,
+ XMMRegister a, XMMRegister b,
+ XMMRegister xmmt, Register rt,
+ bool min, bool single) {
+
+ Label nan, zero, below, above, done;
+
+ if (single)
+ __ ucomiss(a, b);
+ else
+ __ ucomisd(a, b);
+
+ if (dst->encoding() != (min ? b : a)->encoding())
+ __ jccb(Assembler::above, above); // CF=0 & ZF=0
+ else
+ __ jccb(Assembler::above, done);
+
+ __ jccb(Assembler::parity, nan); // PF=1
+ __ jccb(Assembler::below, below); // CF=1
+
+ // equal
+ __ vpxor(xmmt, xmmt, xmmt, Assembler::AVX_128bit);
+ if (single) {
+ __ ucomiss(a, xmmt);
+ __ jccb(Assembler::equal, zero);
+
+ __ movflt(dst, a);
+ __ jmp(done);
+ }
+ else {
+ __ ucomisd(a, xmmt);
+ __ jccb(Assembler::equal, zero);
+
+ __ movdbl(dst, a);
+ __ jmp(done);
+ }
+
+ __ bind(zero);
+ if (min)
+ __ vpor(dst, a, b, Assembler::AVX_128bit);
+ else
+ __ vpand(dst, a, b, Assembler::AVX_128bit);
+
+ __ jmp(done);
+
+ __ bind(above);
+ if (single)
+ __ movflt(dst, min ? b : a);
+ else
+ __ movdbl(dst, min ? b : a);
+
+ __ jmp(done);
+
+ __ bind(nan);
+ if (single) {
+ __ movl(rt, 0x7fc00000); // Float.NaN
+ __ movdl(dst, rt);
+ }
+ else {
+ __ mov64(rt, 0x7ff8000000000000L); // Double.NaN
+ __ movdq(dst, rt);
+ }
+ __ jmp(done);
+
+ __ bind(below);
+ if (single)
+ __ movflt(dst, min ? a : b);
+ else
+ __ movdbl(dst, min ? a : b);
+
+ __ bind(done);
+}
//=============================================================================
const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
@@ -3679,6 +3760,15 @@
%}
// Float register operands
+operand legRegF() %{
+ constraint(ALLOC_IN_RC(float_reg_legacy));
+ match(RegF);
+
+ format %{ %}
+ interface(REG_INTER);
+%}
+
+// Float register operands
operand vlRegF() %{
constraint(ALLOC_IN_RC(float_reg_vl));
match(RegF);
@@ -3697,6 +3787,15 @@
%}
// Double register operands
+operand legRegD() %{
+ constraint(ALLOC_IN_RC(double_reg_legacy));
+ match(RegD);
+
+ format %{ %}
+ interface(REG_INTER);
+%}
+
+// Double register operands
operand vlRegD() %{
constraint(ALLOC_IN_RC(double_reg_vl));
match(RegD);
@@ -5371,6 +5470,16 @@
%}
// Load Float
+instruct MoveF2LEG(legRegF dst, regF src) %{
+ match(Set dst src);
+ format %{ "movss $dst,$src\t# if src != dst load float (4 bytes)" %}
+ ins_encode %{
+ __ movflt($dst$$XMMRegister, $src$$XMMRegister);
+ %}
+ ins_pipe( fpu_reg_reg );
+%}
+
+// Load Float
instruct MoveVL2F(regF dst, vlRegF src) %{
match(Set dst src);
format %{ "movss $dst,$src\t! load float (4 bytes)" %}
@@ -5380,6 +5489,16 @@
ins_pipe( fpu_reg_reg );
%}
+// Load Float
+instruct MoveLEG2F(regF dst, legRegF src) %{
+ match(Set dst src);
+ format %{ "movss $dst,$src\t# if src != dst load float (4 bytes)" %}
+ ins_encode %{
+ __ movflt($dst$$XMMRegister, $src$$XMMRegister);
+ %}
+ ins_pipe( fpu_reg_reg );
+%}
+
// Load Double
instruct loadD_partial(regD dst, memory mem)
%{
@@ -5418,6 +5537,16 @@
%}
// Load Double
+instruct MoveD2LEG(legRegD dst, regD src) %{
+ match(Set dst src);
+ format %{ "movsd $dst,$src\t# if src != dst load double (8 bytes)" %}
+ ins_encode %{
+ __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
+ %}
+ ins_pipe( fpu_reg_reg );
+%}
+
+// Load Double
instruct MoveVL2D(regD dst, vlRegD src) %{
match(Set dst src);
format %{ "movsd $dst,$src\t! load double (8 bytes)" %}
@@ -5427,6 +5556,167 @@
ins_pipe( fpu_reg_reg );
%}
+// Load Double
+instruct MoveLEG2D(regD dst, legRegD src) %{
+ match(Set dst src);
+ format %{ "movsd $dst,$src\t# if src != dst load double (8 bytes)" %}
+ ins_encode %{
+ __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
+ %}
+ ins_pipe( fpu_reg_reg );
+%}
+
+// Following pseudo code describes the algorithm for max[FD]:
+// Min algorithm is on similar lines
+// btmp = (b < +0.0) ? a : b
+// atmp = (b < +0.0) ? b : a
+// Tmp = Max_Float(atmp , btmp)
+// Res = (atmp == NaN) ? atmp : Tmp
+
+// max = java.lang.Math.max(float a, float b)
+instruct maxF_reg(legRegF dst, legRegF a, legRegF b, legRegF tmp, legRegF atmp, legRegF btmp) %{
+ predicate(UseAVX > 0 && !n->is_reduction());
+ match(Set dst (MaxF a b));
+ effect(USE a, USE b, TEMP tmp, TEMP atmp, TEMP btmp);
+ format %{
+ "blendvps $btmp,$b,$a,$b \n\t"
+ "blendvps $atmp,$a,$b,$b \n\t"
+ "vmaxss $tmp,$atmp,$btmp \n\t"
+ "cmpps.unordered $btmp,$atmp,$atmp \n\t"
+ "blendvps $dst,$tmp,$atmp,$btmp \n\t"
+ %}
+ ins_encode %{
+ int vector_len = Assembler::AVX_128bit;
+ __ blendvps($btmp$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, vector_len);
+ __ blendvps($atmp$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $b$$XMMRegister, vector_len);
+ __ vmaxss($tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister);
+ __ cmpps($btmp$$XMMRegister, $atmp$$XMMRegister, $atmp$$XMMRegister, Assembler::_false, vector_len);
+ __ blendvps($dst$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, vector_len);
+ %}
+ ins_pipe( pipe_slow );
+%}
+
+instruct maxF_reduction_reg(legRegF dst, legRegF a, legRegF b, legRegF xmmt, rRegI tmp, rFlagsReg cr) %{
+ predicate(UseAVX > 0 && n->is_reduction());
+ match(Set dst (MaxF a b));
+ effect(USE a, USE b, TEMP xmmt, TEMP tmp, KILL cr);
+
+ format %{ "$dst = max($a, $b)\t# intrinsic (float)" %}
+ ins_encode %{
+ emit_fp_min_max(_masm, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $xmmt$$XMMRegister, $tmp$$Register,
+ false /*min*/, true /*single*/);
+ %}
+ ins_pipe( pipe_slow );
+%}
+
+// max = java.lang.Math.max(double a, double b)
+instruct maxD_reg(legRegD dst, legRegD a, legRegD b, legRegD tmp, legRegD atmp, legRegD btmp) %{
+ predicate(UseAVX > 0 && !n->is_reduction());
+ match(Set dst (MaxD a b));
+ effect(USE a, USE b, TEMP atmp, TEMP btmp, TEMP tmp);
+ format %{
+ "blendvpd $btmp,$b,$a,$b \n\t"
+ "blendvpd $atmp,$a,$b,$b \n\t"
+ "vmaxsd $tmp,$atmp,$btmp \n\t"
+ "cmppd.unordered $btmp,$atmp,$atmp \n\t"
+ "blendvpd $dst,$tmp,$atmp,$btmp \n\t"
+ %}
+ ins_encode %{
+ int vector_len = Assembler::AVX_128bit;
+ __ blendvpd($btmp$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, vector_len);
+ __ blendvpd($atmp$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $b$$XMMRegister, vector_len);
+ __ vmaxsd($tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister);
+ __ cmppd($btmp$$XMMRegister, $atmp$$XMMRegister, $atmp$$XMMRegister, Assembler::_false, vector_len);
+ __ blendvpd($dst$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, vector_len);
+ %}
+ ins_pipe( pipe_slow );
+%}
+
+instruct maxD_reduction_reg(legRegD dst, legRegD a, legRegD b, legRegD xmmt, rRegL tmp, rFlagsReg cr) %{
+ predicate(UseAVX > 0 && n->is_reduction());
+ match(Set dst (MaxD a b));
+ effect(USE a, USE b, TEMP xmmt, TEMP tmp, KILL cr);
+
+ format %{ "$dst = max($a, $b)\t# intrinsic (double)" %}
+ ins_encode %{
+ emit_fp_min_max(_masm, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $xmmt$$XMMRegister, $tmp$$Register,
+ false /*min*/, false /*single*/);
+ %}
+ ins_pipe( pipe_slow );
+%}
+
+// min = java.lang.Math.min(float a, float b)
+instruct minF_reg(legRegF dst, legRegF a, legRegF b, legRegF tmp, legRegF atmp, legRegF btmp) %{
+ predicate(UseAVX > 0 && !n->is_reduction());
+ match(Set dst (MinF a b));
+ effect(USE a, USE b, TEMP tmp, TEMP atmp, TEMP btmp);
+ format %{
+ "blendvps $atmp,$a,$b,$a \n\t"
+ "blendvps $btmp,$b,$a,$a \n\t"
+ "vminss $tmp,$atmp,$btmp \n\t"
+ "cmpps.unordered $btmp,$atmp,$atmp \n\t"
+ "blendvps $dst,$tmp,$atmp,$btmp \n\t"
+ %}
+ ins_encode %{
+ int vector_len = Assembler::AVX_128bit;
+ __ blendvps($atmp$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, vector_len);
+ __ blendvps($btmp$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, $a$$XMMRegister, vector_len);
+ __ vminss($tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister);
+ __ cmpps($btmp$$XMMRegister, $atmp$$XMMRegister, $atmp$$XMMRegister, Assembler::_false, vector_len);
+ __ blendvps($dst$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, vector_len);
+ %}
+ ins_pipe( pipe_slow );
+%}
+
+instruct minF_reduction_reg(legRegF dst, legRegF a, legRegF b, legRegF xmmt, rRegI tmp, rFlagsReg cr) %{
+ predicate(UseAVX > 0 && n->is_reduction());
+ match(Set dst (MinF a b));
+ effect(USE a, USE b, TEMP xmmt, TEMP tmp, KILL cr);
+
+ format %{ "$dst = min($a, $b)\t# intrinsic (float)" %}
+ ins_encode %{
+ emit_fp_min_max(_masm, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $xmmt$$XMMRegister, $tmp$$Register,
+ true /*min*/, true /*single*/);
+ %}
+ ins_pipe( pipe_slow );
+%}
+
+// min = java.lang.Math.min(double a, double b)
+instruct minD_reg(legRegD dst, legRegD a, legRegD b, legRegD tmp, legRegD atmp, legRegD btmp) %{
+ predicate(UseAVX > 0 && !n->is_reduction());
+ match(Set dst (MinD a b));
+ effect(USE a, USE b, TEMP tmp, TEMP atmp, TEMP btmp);
+ format %{
+ "blendvpd $atmp,$a,$b,$a \n\t"
+ "blendvpd $btmp,$b,$a,$a \n\t"
+ "vminsd $tmp,$atmp,$btmp \n\t"
+ "cmppd.unordered $btmp,$atmp,$atmp \n\t"
+ "blendvpd $dst,$tmp,$atmp,$btmp \n\t"
+ %}
+ ins_encode %{
+ int vector_len = Assembler::AVX_128bit;
+ __ blendvpd($atmp$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, vector_len);
+ __ blendvpd($btmp$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, $a$$XMMRegister, vector_len);
+ __ vminsd($tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister);
+ __ cmppd($btmp$$XMMRegister, $atmp$$XMMRegister, $atmp$$XMMRegister, Assembler::_false, vector_len);
+ __ blendvpd($dst$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, vector_len);
+ %}
+ ins_pipe( pipe_slow );
+%}
+
+instruct minD_reduction_reg(legRegD dst, legRegD a, legRegD b, legRegD xmmt, rRegL tmp, rFlagsReg cr) %{
+ predicate(UseAVX > 0 && n->is_reduction());
+ match(Set dst (MinD a b));
+ effect(USE a, USE b, TEMP xmmt, TEMP tmp, KILL cr);
+
+ format %{ "$dst = min($a, $b)\t# intrinsic (double)" %}
+ ins_encode %{
+ emit_fp_min_max(_masm, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $xmmt$$XMMRegister, $tmp$$Register,
+ true /*min*/, false /*single*/);
+ %}
+ ins_pipe( pipe_slow );
+%}
+
// Load Effective Address
instruct leaP8(rRegP dst, indOffset8 mem)
%{
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/x86/x86.ad openjdk-lts-11.0.14+9/src/hotspot/cpu/x86/x86.ad
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/x86/x86.ad 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/x86/x86.ad 2022-01-13 21:56:25.000000000 +0000
@@ -1,5 +1,5 @@
//
-// Copyright (c) 2011, 2018, Oracle and/or its affiliates. All rights reserved.
+// Copyright (c) 2011, 2019, Oracle and/or its affiliates. All rights reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
//
// This code is free software; you can redistribute it and/or modify it
@@ -1297,6 +1297,16 @@
#endif
};
+inline uint vector_length(const Node* n) {
+ const TypeVect* vt = n->bottom_type()->is_vect();
+ return vt->length();
+}
+
+inline uint vector_length_in_bytes(const Node* n) {
+ const TypeVect* vt = n->bottom_type()->is_vect();
+ return vt->length_in_bytes();
+}
+
%} // end source_hpp
source %{
@@ -1468,6 +1478,19 @@
if (UseSSE < 4)
ret_value = false;
break;
+#ifdef _LP64
+ case Op_MaxD:
+ case Op_MaxF:
+ case Op_MinD:
+ case Op_MinF:
+ if (UseAVX < 1) // enabled for AVX only
+ ret_value = false;
+ break;
+#endif
+ case Op_RoundDoubleMode:
+ if (UseSSE < 4)
+ ret_value = false;
+ break;
}
return ret_value; // Per default match rules are supported.
@@ -1519,6 +1542,10 @@
if (vlen != 4)
ret_value = false;
break;
+ case Op_RoundDoubleModeV:
+ if (VM_Version::supports_avx() == false)
+ ret_value = false;
+ break;
}
}
@@ -2839,6 +2866,110 @@
ins_pipe(pipe_slow);
%}
+
+#ifdef _LP64
+instruct roundD_reg(legRegD dst, legRegD src, immU8 rmode) %{
+ predicate(UseSSE>=4);
+ match(Set dst (RoundDoubleMode src rmode));
+ format %{ "roundsd $dst, $src" %}
+ ins_cost(150);
+ ins_encode %{
+ __ roundsd($dst$$XMMRegister, $src$$XMMRegister, $rmode$$constant);
+ %}
+ ins_pipe(pipe_slow);
+%}
+
+instruct roundD_mem(legRegD dst, memory src, immU8 rmode) %{
+ predicate(UseSSE>=4);
+ match(Set dst (RoundDoubleMode (LoadD src) rmode));
+ format %{ "roundsd $dst, $src" %}
+ ins_cost(150);
+ ins_encode %{
+ __ roundsd($dst$$XMMRegister, $src$$Address, $rmode$$constant);
+ %}
+ ins_pipe(pipe_slow);
+%}
+
+instruct roundD_imm(legRegD dst, immD con, immU8 rmode, rRegI scratch_reg) %{
+ predicate(UseSSE>=4);
+ match(Set dst (RoundDoubleMode con rmode));
+ effect(TEMP scratch_reg);
+ format %{ "roundsd $dst, [$constantaddress]\t# load from constant table: double=$con" %}
+ ins_cost(150);
+ ins_encode %{
+ __ roundsd($dst$$XMMRegister, $constantaddress($con), $rmode$$constant, $scratch_reg$$Register);
+ %}
+ ins_pipe(pipe_slow);
+%}
+
+instruct vround2D_reg(legVecX dst, legVecX src, immU8 rmode) %{
+ predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
+ match(Set dst (RoundDoubleModeV src rmode));
+ format %{ "vroundpd $dst, $src, $rmode\t! round packed2D" %}
+ ins_encode %{
+ int vector_len = 0;
+ __ vroundpd($dst$$XMMRegister, $src$$XMMRegister, $rmode$$constant, vector_len);
+ %}
+ ins_pipe( pipe_slow );
+%}
+
+instruct vround2D_mem(legVecX dst, memory mem, immU8 rmode) %{
+ predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
+ match(Set dst (RoundDoubleModeV (LoadVector mem) rmode));
+ format %{ "vroundpd $dst, $mem, $rmode\t! round packed2D" %}
+ ins_encode %{
+ int vector_len = 0;
+ __ vroundpd($dst$$XMMRegister, $mem$$Address, $rmode$$constant, vector_len);
+ %}
+ ins_pipe( pipe_slow );
+%}
+
+instruct vround4D_reg(legVecY dst, legVecY src, legVecY rmode) %{
+ predicate(UseAVX > 0 && n->as_Vector()->length() == 4);
+ match(Set dst (RoundDoubleModeV src rmode));
+ format %{ "vroundpd $dst, $src, $rmode\t! round packed4D" %}
+ ins_encode %{
+ int vector_len = 1;
+ __ vroundpd($dst$$XMMRegister, $src$$XMMRegister, $rmode$$constant, vector_len);
+ %}
+ ins_pipe( pipe_slow );
+%}
+
+instruct vround4D_mem(legVecY dst, memory mem, immU8 rmode) %{
+ predicate(UseAVX > 0 && n->as_Vector()->length() == 4);
+ match(Set dst (RoundDoubleModeV (LoadVector mem) rmode));
+ format %{ "vroundpd $dst, $mem, $rmode\t! round packed4D" %}
+ ins_encode %{
+ int vector_len = 1;
+ __ vroundpd($dst$$XMMRegister, $mem$$Address, $rmode$$constant, vector_len);
+ %}
+ ins_pipe( pipe_slow );
+%}
+
+
+instruct vround8D_reg(vecZ dst, vecZ src, immU8 rmode) %{
+ predicate(UseAVX > 2 && n->as_Vector()->length() == 8);
+ match(Set dst (RoundDoubleModeV src rmode));
+ format %{ "vrndscalepd $dst, $src, $rmode\t! round packed8D" %}
+ ins_encode %{
+ int vector_len = 2;
+ __ vrndscalepd($dst$$XMMRegister, $src$$XMMRegister, $rmode$$constant, vector_len);
+ %}
+ ins_pipe( pipe_slow );
+%}
+
+instruct vround8D_mem(vecZ dst, memory mem, immU8 rmode) %{
+ predicate(UseAVX > 2 && n->as_Vector()->length() == 8);
+ match(Set dst (RoundDoubleModeV (LoadVector mem) rmode));
+ format %{ "vrndscalepd $dst, $mem, $rmode\t! round packed8D" %}
+ ins_encode %{
+ int vector_len = 2;
+ __ vrndscalepd($dst$$XMMRegister, $mem$$Address, $rmode$$constant, vector_len);
+ %}
+ ins_pipe( pipe_slow );
+%}
+#endif // _LP64
+
instruct onspinwait() %{
match(OnSpinWait);
ins_cost(200);
@@ -5913,7 +6044,8 @@
instruct vadd4B_mem(vecS dst, vecS src, memory mem) %{
- predicate(UseAVX > 0 && n->as_Vector()->length() == 4);
+ predicate((UseAVX > 0) && (n->as_Vector()->length() == 4) &&
+ (vector_length_in_bytes(n->in(1)) > 8));
match(Set dst (AddVB src (LoadVector mem)));
format %{ "vpaddb $dst,$src,$mem\t! add packed4B" %}
ins_encode %{
@@ -5946,7 +6078,8 @@
instruct vadd8B_mem(vecD dst, vecD src, memory mem) %{
- predicate(UseAVX > 0 && n->as_Vector()->length() == 8);
+ predicate((UseAVX > 0) && (n->as_Vector()->length() == 8) &&
+ (vector_length_in_bytes(n->in(1)) > 8));
match(Set dst (AddVB src (LoadVector mem)));
format %{ "vpaddb $dst,$src,$mem\t! add packed8B" %}
ins_encode %{
@@ -6055,7 +6188,8 @@
%}
instruct vadd2S_mem(vecS dst, vecS src, memory mem) %{
- predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
+ predicate((UseAVX > 0) && (n->as_Vector()->length() == 2) &&
+ (vector_length_in_bytes(n->in(1)) > 8));
match(Set dst (AddVS src (LoadVector mem)));
format %{ "vpaddw $dst,$src,$mem\t! add packed2S" %}
ins_encode %{
@@ -6087,7 +6221,8 @@
%}
instruct vadd4S_mem(vecD dst, vecD src, memory mem) %{
- predicate(UseAVX > 0 && n->as_Vector()->length() == 4);
+ predicate((UseAVX == 0) && (n->as_Vector()->length() == 4) &&
+ (vector_length_in_bytes(n->in(1)) > 8));
match(Set dst (AddVS src (LoadVector mem)));
format %{ "vpaddw $dst,$src,$mem\t! add packed4S" %}
ins_encode %{
@@ -6196,7 +6331,8 @@
%}
instruct vadd2I_mem(vecD dst, vecD src, memory mem) %{
- predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
+ predicate((UseAVX > 0) && (n->as_Vector()->length() == 2) &&
+ (vector_length_in_bytes(n->in(1)) > 8));
match(Set dst (AddVI src (LoadVector mem)));
format %{ "vpaddd $dst,$src,$mem\t! add packed2I" %}
ins_encode %{
@@ -6382,7 +6518,8 @@
%}
instruct vadd2F_mem(vecD dst, vecD src, memory mem) %{
- predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
+ predicate((UseAVX == 0) && (n->as_Vector()->length() == 2) &&
+ (vector_length_in_bytes(n->in(1)) > 8));
match(Set dst (AddVF src (LoadVector mem)));
format %{ "vaddps $dst,$src,$mem\t! add packed2F" %}
ins_encode %{
@@ -6570,7 +6707,8 @@
%}
instruct vsub4B_mem(vecS dst, vecS src, memory mem) %{
- predicate(UseAVX > 0 && n->as_Vector()->length() == 4);
+ predicate((UseAVX == 0) && (n->as_Vector()->length() == 4) &&
+ (vector_length_in_bytes(n->in(1)) > 8));
match(Set dst (SubVB src (LoadVector mem)));
format %{ "vpsubb $dst,$src,$mem\t! sub packed4B" %}
ins_encode %{
@@ -6602,7 +6740,8 @@
%}
instruct vsub8B_mem(vecD dst, vecD src, memory mem) %{
- predicate(UseAVX > 0 && n->as_Vector()->length() == 8);
+ predicate((UseAVX > 0) && (n->as_Vector()->length() == 8) &&
+ (vector_length_in_bytes(n->in(1)) > 8));
match(Set dst (SubVB src (LoadVector mem)));
format %{ "vpsubb $dst,$src,$mem\t! sub packed8B" %}
ins_encode %{
@@ -6711,7 +6850,8 @@
%}
instruct vsub2S_mem(vecS dst, vecS src, memory mem) %{
- predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
+ predicate((UseAVX == 0) && (n->as_Vector()->length() == 2) &&
+ (vector_length_in_bytes(n->in(1)) > 8));
match(Set dst (SubVS src (LoadVector mem)));
format %{ "vpsubw $dst,$src,$mem\t! sub packed2S" %}
ins_encode %{
@@ -6743,7 +6883,8 @@
%}
instruct vsub4S_mem(vecD dst, vecD src, memory mem) %{
- predicate(UseAVX > 0 && n->as_Vector()->length() == 4);
+ predicate((UseAVX > 0) && (n->as_Vector()->length() == 4) &&
+ (vector_length_in_bytes(n->in(1)) > 8));
match(Set dst (SubVS src (LoadVector mem)));
format %{ "vpsubw $dst,$src,$mem\t! sub packed4S" %}
ins_encode %{
@@ -6852,7 +6993,8 @@
%}
instruct vsub2I_mem(vecD dst, vecD src, memory mem) %{
- predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
+ predicate((UseAVX > 0) && (n->as_Vector()->length() == 2) &&
+ (vector_length_in_bytes(n->in(1)) > 8));
match(Set dst (SubVI src (LoadVector mem)));
format %{ "vpsubd $dst,$src,$mem\t! sub packed2I" %}
ins_encode %{
@@ -7038,7 +7180,8 @@
%}
instruct vsub2F_mem(vecD dst, vecD src, memory mem) %{
- predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
+ predicate((UseAVX == 0) && (n->as_Vector()->length() == 2) &&
+ (vector_length_in_bytes(n->in(1)) > 8));
match(Set dst (SubVF src (LoadVector mem)));
format %{ "vsubps $dst,$src,$mem\t! sub packed2F" %}
ins_encode %{
@@ -7406,7 +7549,8 @@
%}
instruct vmul2S_mem(vecS dst, vecS src, memory mem) %{
- predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
+ predicate((UseAVX > 0) && (n->as_Vector()->length() == 2) &&
+ (vector_length_in_bytes(n->in(1)) > 8));
match(Set dst (MulVS src (LoadVector mem)));
format %{ "vpmullw $dst,$src,$mem\t! mul packed2S" %}
ins_encode %{
@@ -7438,7 +7582,8 @@
%}
instruct vmul4S_mem(vecD dst, vecD src, memory mem) %{
- predicate(UseAVX > 0 && n->as_Vector()->length() == 4);
+ predicate((UseAVX > 0) && (n->as_Vector()->length() == 4) &&
+ (vector_length_in_bytes(n->in(1)) > 8));
match(Set dst (MulVS src (LoadVector mem)));
format %{ "vpmullw $dst,$src,$mem\t! mul packed4S" %}
ins_encode %{
@@ -7547,7 +7692,8 @@
%}
instruct vmul2I_mem(vecD dst, vecD src, memory mem) %{
- predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
+ predicate((UseAVX > 0) && (n->as_Vector()->length() == 2) &&
+ (vector_length_in_bytes(n->in(1)) > 8));
match(Set dst (MulVI src (LoadVector mem)));
format %{ "vpmulld $dst,$src,$mem\t! mul packed2I" %}
ins_encode %{
@@ -7722,7 +7868,8 @@
%}
instruct vmul2F_mem(vecD dst, vecD src, memory mem) %{
- predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
+ predicate((UseAVX > 0) && (n->as_Vector()->length() == 2) &&
+ (vector_length_in_bytes(n->in(1)) > 8));
match(Set dst (MulVF src (LoadVector mem)));
format %{ "vmulps $dst,$src,$mem\t! mul packed2F" %}
ins_encode %{
@@ -7942,7 +8089,8 @@
%}
instruct vdiv2F_mem(vecD dst, vecD src, memory mem) %{
- predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
+ predicate((UseAVX > 0) && (n->as_Vector()->length() == 2) &&
+ (vector_length_in_bytes(n->in(1)) > 8));
match(Set dst (DivVF src (LoadVector mem)));
format %{ "vdivps $dst,$src,$mem\t! div packed2F" %}
ins_encode %{
@@ -8186,7 +8334,8 @@
%}
instruct vsqrt2F_mem(vecD dst, memory mem) %{
- predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
+ predicate((UseAVX > 0) && (n->as_Vector()->length() == 2) &&
+ (vector_length_in_bytes(n->in(1)) > 8));
match(Set dst (SqrtVF (LoadVector mem)));
format %{ "vsqrtps $dst,$mem\t! sqrt packed2F" %}
ins_encode %{
@@ -8771,7 +8920,8 @@
%}
instruct vand4B_mem(vecS dst, vecS src, memory mem) %{
- predicate(UseAVX > 0 && n->as_Vector()->length_in_bytes() == 4);
+ predicate((UseAVX > 0) && (n->as_Vector()->length_in_bytes() == 4) &&
+ (vector_length_in_bytes(n->in(1)) > 8));
match(Set dst (AndV src (LoadVector mem)));
format %{ "vpand $dst,$src,$mem\t! and vectors (4 bytes)" %}
ins_encode %{
@@ -8803,7 +8953,8 @@
%}
instruct vand8B_mem(vecD dst, vecD src, memory mem) %{
- predicate(UseAVX > 0 && n->as_Vector()->length_in_bytes() == 8);
+ predicate((UseAVX > 0) && (n->as_Vector()->length_in_bytes() == 8) &&
+ (vector_length_in_bytes(n->in(1)) > 8));
match(Set dst (AndV src (LoadVector mem)));
format %{ "vpand $dst,$src,$mem\t! and vectors (8 bytes)" %}
ins_encode %{
@@ -8913,7 +9064,8 @@
%}
instruct vor4B_mem(vecS dst, vecS src, memory mem) %{
- predicate(UseAVX > 0 && n->as_Vector()->length_in_bytes() == 4);
+ predicate((UseAVX > 0) && (n->as_Vector()->length_in_bytes() == 4) &&
+ (vector_length_in_bytes(n->in(1)) > 8));
match(Set dst (OrV src (LoadVector mem)));
format %{ "vpor $dst,$src,$mem\t! or vectors (4 bytes)" %}
ins_encode %{
@@ -8945,7 +9097,8 @@
%}
instruct vor8B_mem(vecD dst, vecD src, memory mem) %{
- predicate(UseAVX > 0 && n->as_Vector()->length_in_bytes() == 4);
+ predicate((UseAVX > 0) && (n->as_Vector()->length_in_bytes() == 8) &&
+ (vector_length_in_bytes(n->in(1)) > 8));
match(Set dst (OrV src (LoadVector mem)));
format %{ "vpor $dst,$src,$mem\t! or vectors (8 bytes)" %}
ins_encode %{
@@ -9055,7 +9208,8 @@
%}
instruct vxor4B_mem(vecS dst, vecS src, memory mem) %{
- predicate(UseAVX > 0 && n->as_Vector()->length_in_bytes() == 4);
+ predicate((UseAVX > 0) && (n->as_Vector()->length_in_bytes() == 4) &&
+ (vector_length_in_bytes(n->in(1)) > 8));
match(Set dst (XorV src (LoadVector mem)));
format %{ "vpxor $dst,$src,$mem\t! xor vectors (4 bytes)" %}
ins_encode %{
@@ -9087,7 +9241,8 @@
%}
instruct vxor8B_mem(vecD dst, vecD src, memory mem) %{
- predicate(UseAVX > 0 && n->as_Vector()->length_in_bytes() == 8);
+ predicate((UseAVX > 0) && (n->as_Vector()->length_in_bytes() == 8) &&
+ (vector_length_in_bytes(n->in(1)) > 8));
match(Set dst (XorV src (LoadVector mem)));
format %{ "vpxor $dst,$src,$mem\t! xor vectors (8 bytes)" %}
ins_encode %{
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/zero/register_zero.hpp openjdk-lts-11.0.14+9/src/hotspot/cpu/zero/register_zero.hpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/zero/register_zero.hpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/zero/register_zero.hpp 2022-01-13 21:56:25.000000000 +0000
@@ -27,7 +27,7 @@
#define CPU_ZERO_VM_REGISTER_ZERO_HPP
#include "asm/register.hpp"
-#include "vm_version_zero.hpp"
+#include "runtime/vm_version.hpp"
class VMRegImpl;
typedef VMRegImpl* VMReg;
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/zero/vm_version_ext_zero.hpp openjdk-lts-11.0.14+9/src/hotspot/cpu/zero/vm_version_ext_zero.hpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/zero/vm_version_ext_zero.hpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/zero/vm_version_ext_zero.hpp 2022-01-13 21:56:25.000000000 +0000
@@ -25,8 +25,8 @@
#ifndef CPU_ZERO_VM_VM_VERSION_EXT_ZERO_HPP
#define CPU_ZERO_VM_VM_VERSION_EXT_ZERO_HPP
+#include "runtime/vm_version.hpp"
#include "utilities/macros.hpp"
-#include "vm_version_zero.hpp"
class VM_Version_Ext : public VM_Version {
private:
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/zero/vm_version_zero.cpp openjdk-lts-11.0.14+9/src/hotspot/cpu/zero/vm_version_zero.cpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/zero/vm_version_zero.cpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/zero/vm_version_zero.cpp 2022-01-13 21:56:25.000000000 +0000
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 1997, 2019, Oracle and/or its affiliates. All rights reserved.
* Copyright 2009 Red Hat, Inc.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
@@ -28,7 +28,7 @@
#include "memory/resourceArea.hpp"
#include "runtime/java.hpp"
#include "runtime/stubCodeGenerator.hpp"
-#include "vm_version_zero.hpp"
+#include "runtime/vm_version.hpp"
void VM_Version::initialize() {
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/cpu/zero/vm_version_zero.hpp openjdk-lts-11.0.14+9/src/hotspot/cpu/zero/vm_version_zero.hpp
--- openjdk-lts-11.0.11+9/src/hotspot/cpu/zero/vm_version_zero.hpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/cpu/zero/vm_version_zero.hpp 2022-01-13 21:56:25.000000000 +0000
@@ -26,8 +26,8 @@
#ifndef CPU_ZERO_VM_VM_VERSION_ZERO_HPP
#define CPU_ZERO_VM_VM_VERSION_ZERO_HPP
+#include "runtime/abstract_vm_version.hpp"
#include "runtime/globals_extension.hpp"
-#include "runtime/vm_version.hpp"
class VM_Version : public Abstract_VM_Version {
public:
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/os/aix/attachListener_aix.cpp openjdk-lts-11.0.14+9/src/hotspot/os/aix/attachListener_aix.cpp
--- openjdk-lts-11.0.11+9/src/hotspot/os/aix/attachListener_aix.cpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/os/aix/attachListener_aix.cpp 2022-01-13 21:56:25.000000000 +0000
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2005, 2018, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2005, 2020, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2012, 2018 SAP SE. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
@@ -66,22 +66,12 @@
static char _path[UNIX_PATH_MAX];
static bool _has_path;
// Shutdown marker to prevent accept blocking during clean-up.
- static bool _shutdown;
+ static volatile bool _shutdown;
// the file descriptor for the listening socket
- static int _listener;
+ static volatile int _listener;
- static void set_path(char* path) {
- if (path == NULL) {
- _has_path = false;
- } else {
- strncpy(_path, path, UNIX_PATH_MAX);
- _path[UNIX_PATH_MAX-1] = '\0';
- _has_path = true;
- }
- }
-
- static void set_listener(int s) { _listener = s; }
+ static bool _atexit_registered;
// reads a request from the given connected socket
static AixAttachOperation* read_request(int s);
@@ -94,6 +84,19 @@
ATTACH_ERROR_BADVERSION = 101 // error codes
};
+ static void set_path(char* path) {
+ if (path == NULL) {
+ _path[0] = '\0';
+ _has_path = false;
+ } else {
+ strncpy(_path, path, UNIX_PATH_MAX);
+ _path[UNIX_PATH_MAX-1] = '\0';
+ _has_path = true;
+ }
+ }
+
+ static void set_listener(int s) { _listener = s; }
+
// initialize the listener, returns 0 if okay
static int init();
@@ -129,9 +132,10 @@
// statics
char AixAttachListener::_path[UNIX_PATH_MAX];
bool AixAttachListener::_has_path;
-int AixAttachListener::_listener = -1;
+volatile int AixAttachListener::_listener = -1;
+bool AixAttachListener::_atexit_registered = false;
// Shutdown marker to prevent accept blocking during clean-up
-bool AixAttachListener::_shutdown = false;
+volatile bool AixAttachListener::_shutdown = false;
// Supporting class to help split a buffer into individual components
class ArgumentIterator : public StackObj {
@@ -177,17 +181,14 @@
// should be sufficient for cleanup.
extern "C" {
static void listener_cleanup() {
- static int cleanup_done;
- if (!cleanup_done) {
- cleanup_done = 1;
- AixAttachListener::set_shutdown(true);
- int s = AixAttachListener::listener();
- if (s != -1) {
- ::shutdown(s, 2);
- }
- if (AixAttachListener::has_path()) {
- ::unlink(AixAttachListener::path());
- }
+ AixAttachListener::set_shutdown(true);
+ int s = AixAttachListener::listener();
+ if (s != -1) {
+ ::shutdown(s, 2);
+ }
+ if (AixAttachListener::has_path()) {
+ ::unlink(AixAttachListener::path());
+ AixAttachListener::set_path(NULL);
}
}
}
@@ -200,7 +201,10 @@
int listener; // listener socket (file descriptor)
// register function to cleanup
- ::atexit(listener_cleanup);
+ if (!_atexit_registered) {
+ _atexit_registered = true;
+ ::atexit(listener_cleanup);
+ }
int n = snprintf(path, UNIX_PATH_MAX, "%s/.java_pid%d",
os::get_temp_directory(), os::current_process_id());
@@ -371,10 +375,14 @@
// We must prevent accept blocking on the socket if it has been shut down.
// Therefore we allow interrupts and check whether we have been shut down already.
if (AixAttachListener::is_shutdown()) {
+ ::close(listener());
+ set_listener(-1);
return NULL;
}
- s=::accept(listener(), &addr, &len);
+ s = ::accept(listener(), &addr, &len);
if (s == -1) {
+ ::close(listener());
+ set_listener(-1);
return NULL; // log a warning?
}
@@ -515,6 +523,30 @@
return ret_code;
}
+bool AttachListener::check_socket_file() {
+ int ret;
+ struct stat64 st;
+ ret = stat64(AixAttachListener::path(), &st);
+ if (ret == -1) { // need to restart attach listener.
+ log_debug(attach)("Socket file %s does not exist - Restart Attach Listener",
+ AixAttachListener::path());
+
+ listener_cleanup();
+
+ // wait to terminate current attach listener instance...
+ {
+ // avoid deadlock if AttachListener thread is blocked at safepoint
+ ThreadBlockInVM tbivm(JavaThread::current());
+ while (AttachListener::transit_state(AL_INITIALIZING,
+ AL_NOT_INITIALIZED) != AL_NOT_INITIALIZED) {
+ os::naked_yield();
+ }
+ }
+ return is_init_trigger();
+ }
+ return false;
+}
+
// Attach Listener is started lazily except in the case when
// +ReduseSignalUsage is used
bool AttachListener::init_at_startup() {
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/os/aix/os_aix.cpp openjdk-lts-11.0.14+9/src/hotspot/os/aix/os_aix.cpp
--- openjdk-lts-11.0.11+9/src/hotspot/os/aix/os_aix.cpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/os/aix/os_aix.cpp 2022-01-13 21:56:25.000000000 +0000
@@ -64,9 +64,9 @@
#include "runtime/os.hpp"
#include "runtime/osThread.hpp"
#include "runtime/perfMemory.hpp"
+#include "runtime/safefetch.inline.hpp"
#include "runtime/sharedRuntime.hpp"
#include "runtime/statSampler.hpp"
-#include "runtime/stubRoutines.hpp"
#include "runtime/thread.inline.hpp"
#include "runtime/threadCritical.hpp"
#include "runtime/timer.hpp"
@@ -1188,7 +1188,7 @@
::abort(); // dump core
}
- ::exit(1);
+ ::_exit(1);
}
// Die immediately, no exit hook, no abort hook, no cleanup.
@@ -3789,9 +3789,7 @@
// create binary file, rewriting existing file if required
int os::create_binary_file(const char* path, bool rewrite_existing) {
int oflags = O_WRONLY | O_CREAT;
- if (!rewrite_existing) {
- oflags |= O_EXCL;
- }
+ oflags |= rewrite_existing ? O_TRUNC : O_EXCL;
return ::open64(path, oflags, S_IREAD | S_IWRITE);
}
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/os/aix/perfMemory_aix.cpp openjdk-lts-11.0.14+9/src/hotspot/os/aix/perfMemory_aix.cpp
--- openjdk-lts-11.0.11+9/src/hotspot/os/aix/perfMemory_aix.cpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/os/aix/perfMemory_aix.cpp 2022-01-13 21:56:25.000000000 +0000
@@ -538,7 +538,7 @@
char* pwbuf = NEW_C_HEAP_ARRAY(char, bufsize, mtInternal);
- struct passwd* p;
+ struct passwd* p = NULL;
int result = getpwuid_r(uid, &pwent, pwbuf, (size_t)bufsize, &p);
if (result != 0 || p == NULL || p->pw_name == NULL || *(p->pw_name) == '\0') {
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/os/bsd/attachListener_bsd.cpp openjdk-lts-11.0.14+9/src/hotspot/os/bsd/attachListener_bsd.cpp
--- openjdk-lts-11.0.11+9/src/hotspot/os/bsd/attachListener_bsd.cpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/os/bsd/attachListener_bsd.cpp 2022-01-13 21:56:25.000000000 +0000
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2005, 2018, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2005, 2020, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@@ -66,19 +66,9 @@
static bool _has_path;
// the file descriptor for the listening socket
- static int _listener;
+ static volatile int _listener;
- static void set_path(char* path) {
- if (path == NULL) {
- _has_path = false;
- } else {
- strncpy(_path, path, UNIX_PATH_MAX);
- _path[UNIX_PATH_MAX-1] = '\0';
- _has_path = true;
- }
- }
-
- static void set_listener(int s) { _listener = s; }
+ static bool _atexit_registered;
// reads a request from the given connected socket
static BsdAttachOperation* read_request(int s);
@@ -91,6 +81,19 @@
ATTACH_ERROR_BADVERSION = 101 // error codes
};
+ static void set_path(char* path) {
+ if (path == NULL) {
+ _path[0] = '\0';
+ _has_path = false;
+ } else {
+ strncpy(_path, path, UNIX_PATH_MAX);
+ _path[UNIX_PATH_MAX-1] = '\0';
+ _has_path = true;
+ }
+ }
+
+ static void set_listener(int s) { _listener = s; }
+
// initialize the listener, returns 0 if okay
static int init();
@@ -123,7 +126,8 @@
// statics
char BsdAttachListener::_path[UNIX_PATH_MAX];
bool BsdAttachListener::_has_path;
-int BsdAttachListener::_listener = -1;
+volatile int BsdAttachListener::_listener = -1;
+bool BsdAttachListener::_atexit_registered = false;
// Supporting class to help split a buffer into individual components
class ArgumentIterator : public StackObj {
@@ -158,16 +162,15 @@
// bound too.
extern "C" {
static void listener_cleanup() {
- static int cleanup_done;
- if (!cleanup_done) {
- cleanup_done = 1;
- int s = BsdAttachListener::listener();
- if (s != -1) {
- ::close(s);
- }
- if (BsdAttachListener::has_path()) {
- ::unlink(BsdAttachListener::path());
- }
+ int s = BsdAttachListener::listener();
+ if (s != -1) {
+ BsdAttachListener::set_listener(-1);
+ ::shutdown(s, SHUT_RDWR);
+ ::close(s);
+ }
+ if (BsdAttachListener::has_path()) {
+ ::unlink(BsdAttachListener::path());
+ BsdAttachListener::set_path(NULL);
}
}
}
@@ -180,7 +183,10 @@
int listener; // listener socket (file descriptor)
// register function to cleanup
- ::atexit(listener_cleanup);
+ if (!_atexit_registered) {
+ _atexit_registered = true;
+ ::atexit(listener_cleanup);
+ }
int n = snprintf(path, UNIX_PATH_MAX, "%s/.java_pid%d",
os::get_temp_directory(), os::current_process_id());
@@ -485,6 +491,30 @@
return ret_code;
}
+bool AttachListener::check_socket_file() {
+ int ret;
+ struct stat st;
+ ret = stat(BsdAttachListener::path(), &st);
+ if (ret == -1) { // need to restart attach listener.
+ log_debug(attach)("Socket file %s does not exist - Restart Attach Listener",
+ BsdAttachListener::path());
+
+ listener_cleanup();
+
+ // wait to terminate current attach listener instance...
+ {
+ // avoid deadlock if AttachListener thread is blocked at safepoint
+ ThreadBlockInVM tbivm(JavaThread::current());
+ while (AttachListener::transit_state(AL_INITIALIZING,
+ AL_NOT_INITIALIZED) != AL_NOT_INITIALIZED) {
+ os::naked_yield();
+ }
+ }
+ return is_init_trigger();
+ }
+ return false;
+}
+
// Attach Listener is started lazily except in the case when
// +ReduseSignalUsage is used
bool AttachListener::init_at_startup() {
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/os/bsd/os_bsd.cpp openjdk-lts-11.0.14+9/src/hotspot/os/bsd/os_bsd.cpp
--- openjdk-lts-11.0.11+9/src/hotspot/os/bsd/os_bsd.cpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/os/bsd/os_bsd.cpp 2022-01-13 21:56:25.000000000 +0000
@@ -1092,7 +1092,7 @@
::abort(); // dump core
}
- ::exit(1);
+ ::_exit(1);
}
// Die immediately, no exit hook, no abort hook, no cleanup.
@@ -1729,6 +1729,7 @@
}
char dli_fname[MAXPATHLEN];
+ dli_fname[0] = '\0';
bool ret = dll_address_to_library_name(
CAST_FROM_FN_PTR(address, os::jvm_path),
dli_fname, sizeof(dli_fname), NULL);
@@ -3296,16 +3297,6 @@
Bsd::clock_init();
initial_time_count = javaTimeNanos();
-#ifdef __APPLE__
- // XXXDARWIN
- // Work around the unaligned VM callbacks in hotspot's
- // sharedRuntime. The callbacks don't use SSE2 instructions, and work on
- // Linux, Solaris, and FreeBSD. On Mac OS X, dyld (rightly so) enforces
- // alignment when doing symbol lookup. To work around this, we force early
- // binding of all symbols now, thus binding when alignment is known-good.
- _dyld_bind_fully_image_containing_address((const void *) &os::init);
-#endif
-
os::Posix::init();
}
@@ -3637,9 +3628,7 @@
// create binary file, rewriting existing file if required
int os::create_binary_file(const char* path, bool rewrite_existing) {
int oflags = O_WRONLY | O_CREAT;
- if (!rewrite_existing) {
- oflags |= O_EXCL;
- }
+ oflags |= rewrite_existing ? O_TRUNC : O_EXCL;
return ::open(path, oflags, S_IREAD | S_IWRITE);
}
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/os/bsd/os_perf_bsd.cpp openjdk-lts-11.0.14+9/src/hotspot/os/bsd/os_perf_bsd.cpp
--- openjdk-lts-11.0.11+9/src/hotspot/os/bsd/os_perf_bsd.cpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/os/bsd/os_perf_bsd.cpp 2022-01-13 21:56:25.000000000 +0000
@@ -27,7 +27,7 @@
#include "runtime/os.hpp"
#include "runtime/os_perf.hpp"
#include "utilities/globalDefinitions.hpp"
-#include "vm_version_ext_x86.hpp"
+#include CPU_HEADER(vm_version_ext)
#ifdef __APPLE__
#import
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/os/bsd/perfMemory_bsd.cpp openjdk-lts-11.0.14+9/src/hotspot/os/bsd/perfMemory_bsd.cpp
--- openjdk-lts-11.0.11+9/src/hotspot/os/bsd/perfMemory_bsd.cpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/os/bsd/perfMemory_bsd.cpp 2022-01-13 21:56:25.000000000 +0000
@@ -454,7 +454,7 @@
char* pwbuf = NEW_C_HEAP_ARRAY(char, bufsize, mtInternal);
// POSIX interface to getpwuid_r is used on LINUX
- struct passwd* p;
+ struct passwd* p = NULL;
int result = getpwuid_r(uid, &pwent, pwbuf, (size_t)bufsize, &p);
if (result != 0 || p == NULL || p->pw_name == NULL || *(p->pw_name) == '\0') {
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/os/linux/attachListener_linux.cpp openjdk-lts-11.0.14+9/src/hotspot/os/linux/attachListener_linux.cpp
--- openjdk-lts-11.0.11+9/src/hotspot/os/linux/attachListener_linux.cpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/os/linux/attachListener_linux.cpp 2022-01-13 21:56:25.000000000 +0000
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2005, 2018, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2005, 2020, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@@ -67,19 +67,9 @@
static bool _has_path;
// the file descriptor for the listening socket
- static int _listener;
+ static volatile int _listener;
- static void set_path(char* path) {
- if (path == NULL) {
- _has_path = false;
- } else {
- strncpy(_path, path, UNIX_PATH_MAX);
- _path[UNIX_PATH_MAX-1] = '\0';
- _has_path = true;
- }
- }
-
- static void set_listener(int s) { _listener = s; }
+ static bool _atexit_registered;
// reads a request from the given connected socket
static LinuxAttachOperation* read_request(int s);
@@ -92,6 +82,19 @@
ATTACH_ERROR_BADVERSION = 101 // error codes
};
+ static void set_path(char* path) {
+ if (path == NULL) {
+ _path[0] = '\0';
+ _has_path = false;
+ } else {
+ strncpy(_path, path, UNIX_PATH_MAX);
+ _path[UNIX_PATH_MAX-1] = '\0';
+ _has_path = true;
+ }
+ }
+
+ static void set_listener(int s) { _listener = s; }
+
// initialize the listener, returns 0 if okay
static int init();
@@ -124,7 +127,8 @@
// statics
char LinuxAttachListener::_path[UNIX_PATH_MAX];
bool LinuxAttachListener::_has_path;
-int LinuxAttachListener::_listener = -1;
+volatile int LinuxAttachListener::_listener = -1;
+bool LinuxAttachListener::_atexit_registered = false;
// Supporting class to help split a buffer into individual components
class ArgumentIterator : public StackObj {
@@ -159,16 +163,15 @@
// bound too.
extern "C" {
static void listener_cleanup() {
- static int cleanup_done;
- if (!cleanup_done) {
- cleanup_done = 1;
- int s = LinuxAttachListener::listener();
- if (s != -1) {
- ::close(s);
- }
- if (LinuxAttachListener::has_path()) {
- ::unlink(LinuxAttachListener::path());
- }
+ int s = LinuxAttachListener::listener();
+ if (s != -1) {
+ LinuxAttachListener::set_listener(-1);
+ ::shutdown(s, SHUT_RDWR);
+ ::close(s);
+ }
+ if (LinuxAttachListener::has_path()) {
+ ::unlink(LinuxAttachListener::path());
+ LinuxAttachListener::set_path(NULL);
}
}
}
@@ -181,7 +184,10 @@
int listener; // listener socket (file descriptor)
// register function to cleanup
- ::atexit(listener_cleanup);
+ if (!_atexit_registered) {
+ _atexit_registered = true;
+ ::atexit(listener_cleanup);
+ }
int n = snprintf(path, UNIX_PATH_MAX, "%s/.java_pid%d",
os::get_temp_directory(), os::current_process_id());
@@ -485,6 +491,30 @@
return ret_code;
}
+bool AttachListener::check_socket_file() {
+ int ret;
+ struct stat64 st;
+ ret = stat64(LinuxAttachListener::path(), &st);
+ if (ret == -1) { // need to restart attach listener.
+ log_debug(attach)("Socket file %s does not exist - Restart Attach Listener",
+ LinuxAttachListener::path());
+
+ listener_cleanup();
+
+ // wait to terminate current attach listener instance...
+ {
+ // avoid deadlock if AttachListener thread is blocked at safepoint
+ ThreadBlockInVM tbivm(JavaThread::current());
+ while (AttachListener::transit_state(AL_INITIALIZING,
+ AL_NOT_INITIALIZED) != AL_NOT_INITIALIZED) {
+ os::naked_yield();
+ }
+ }
+ return is_init_trigger();
+ }
+ return false;
+}
+
// Attach Listener is started lazily except in the case when
// +ReduseSignalUsage is used
bool AttachListener::init_at_startup() {
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/os/linux/os_linux.cpp openjdk-lts-11.0.14+9/src/hotspot/os/linux/os_linux.cpp
--- openjdk-lts-11.0.11+9/src/hotspot/os/linux/os_linux.cpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/os/linux/os_linux.cpp 2022-01-13 21:56:25.000000000 +0000
@@ -414,7 +414,14 @@
#if defined(AMD64) || (defined(_LP64) && defined(SPARC)) || defined(PPC64) || defined(S390)
#define DEFAULT_LIBPATH "/usr/lib64:/lib64:/lib:/usr/lib"
#else
+#if defined(AARCH64)
+ // Use 32-bit locations first for AARCH64 (a 64-bit architecture), since some systems
+ // might not adhere to the FHS and it would be a change in behaviour if we used
+ // DEFAULT_LIBPATH of other 64-bit architectures which prefer the 64-bit paths.
+ #define DEFAULT_LIBPATH "/lib:/usr/lib:/usr/lib64:/lib64"
+#else
#define DEFAULT_LIBPATH "/lib:/usr/lib"
+#endif // AARCH64
#endif
// Base path of extensions installed on the system.
@@ -1505,7 +1512,7 @@
::abort(); // dump core
}
- ::exit(1);
+ ::_exit(1);
}
// Die immediately, no exit hook, no abort hook, no cleanup.
@@ -1828,6 +1835,12 @@
#ifndef EM_AARCH64
#define EM_AARCH64 183 /* ARM AARCH64 */
#endif
+#ifndef EM_RISCV
+ #define EM_RISCV 243 /* RISC-V */
+#endif
+#ifndef EM_LOONGARCH
+ #define EM_LOONGARCH 258 /* LoongArch */
+#endif
static const arch_t arch_array[]={
{EM_386, EM_386, ELFCLASS32, ELFDATA2LSB, (char*)"IA 32"},
@@ -1853,6 +1866,8 @@
{EM_PARISC, EM_PARISC, ELFCLASS32, ELFDATA2MSB, (char*)"PARISC"},
{EM_68K, EM_68K, ELFCLASS32, ELFDATA2MSB, (char*)"M68k"},
{EM_AARCH64, EM_AARCH64, ELFCLASS64, ELFDATA2LSB, (char*)"AARCH64"},
+ {EM_RISCV, EM_RISCV, ELFCLASS64, ELFDATA2LSB, (char*)"RISC-V"},
+ {EM_LOONGARCH, EM_LOONGARCH, ELFCLASS64, ELFDATA2LSB, (char*)"LoongArch"},
};
#if (defined IA32)
@@ -1887,9 +1902,13 @@
static Elf32_Half running_arch_code=EM_68K;
#elif (defined SH)
static Elf32_Half running_arch_code=EM_SH;
+#elif (defined RISCV)
+ static Elf32_Half running_arch_code=EM_RISCV;
+#elif (defined LOONGARCH)
+ static Elf32_Half running_arch_code=EM_LOONGARCH;
#else
#error Method os::dll_load requires that one of following is defined:\
- AARCH64, ALPHA, ARM, AMD64, IA32, IA64, M68K, MIPS, MIPSEL, PARISC, __powerpc__, __powerpc64__, S390, SH, __sparc
+ AARCH64, ALPHA, ARM, AMD64, IA32, IA64, LOONGARCH, M68K, MIPS, MIPSEL, PARISC, __powerpc__, __powerpc64__, RISCV, S390, SH, __sparc
#endif
// Identify compatability class for VM's architecture and library's architecture
@@ -2292,29 +2311,35 @@
int num_found = 0;
FILE* f = ::fopen("/proc/self/status", "r");
char buf[256];
- while (::fgets(buf, sizeof(buf), f) != NULL && num_found < num_values) {
- if ( (vmsize == -1 && sscanf(buf, "VmSize: " SSIZE_FORMAT " kB", &vmsize) == 1) ||
- (vmpeak == -1 && sscanf(buf, "VmPeak: " SSIZE_FORMAT " kB", &vmpeak) == 1) ||
- (vmswap == -1 && sscanf(buf, "VmSwap: " SSIZE_FORMAT " kB", &vmswap) == 1) ||
- (vmhwm == -1 && sscanf(buf, "VmHWM: " SSIZE_FORMAT " kB", &vmhwm) == 1) ||
- (vmrss == -1 && sscanf(buf, "VmRSS: " SSIZE_FORMAT " kB", &vmrss) == 1) ||
- (rssanon == -1 && sscanf(buf, "RssAnon: " SSIZE_FORMAT " kB", &rssanon) == 1) ||
- (rssfile == -1 && sscanf(buf, "RssFile: " SSIZE_FORMAT " kB", &rssfile) == 1) ||
- (rssshmem == -1 && sscanf(buf, "RssShmem: " SSIZE_FORMAT " kB", &rssshmem) == 1)
- )
- {
- num_found ++;
+ if (f != NULL) {
+ while (::fgets(buf, sizeof(buf), f) != NULL && num_found < num_values) {
+ if ( (vmsize == -1 && sscanf(buf, "VmSize: " SSIZE_FORMAT " kB", &vmsize) == 1) ||
+ (vmpeak == -1 && sscanf(buf, "VmPeak: " SSIZE_FORMAT " kB", &vmpeak) == 1) ||
+ (vmswap == -1 && sscanf(buf, "VmSwap: " SSIZE_FORMAT " kB", &vmswap) == 1) ||
+ (vmhwm == -1 && sscanf(buf, "VmHWM: " SSIZE_FORMAT " kB", &vmhwm) == 1) ||
+ (vmrss == -1 && sscanf(buf, "VmRSS: " SSIZE_FORMAT " kB", &vmrss) == 1) ||
+ (rssanon == -1 && sscanf(buf, "RssAnon: " SSIZE_FORMAT " kB", &rssanon) == 1) ||
+ (rssfile == -1 && sscanf(buf, "RssFile: " SSIZE_FORMAT " kB", &rssfile) == 1) ||
+ (rssshmem == -1 && sscanf(buf, "RssShmem: " SSIZE_FORMAT " kB", &rssshmem) == 1)
+ )
+ {
+ num_found ++;
+ }
}
- }
- st->print_cr("Virtual Size: " SSIZE_FORMAT "K (peak: " SSIZE_FORMAT "K)", vmsize, vmpeak);
- st->print("Resident Set Size: " SSIZE_FORMAT "K (peak: " SSIZE_FORMAT "K)", vmrss, vmhwm);
- if (rssanon != -1) { // requires kernel >= 4.5
- st->print(" (anon: " SSIZE_FORMAT "K, file: " SSIZE_FORMAT "K, shmem: " SSIZE_FORMAT "K)",
- rssanon, rssfile, rssshmem);
- }
- st->cr();
- if (vmswap != -1) { // requires kernel >= 2.6.34
- st->print_cr("Swapped out: " SSIZE_FORMAT "K", vmswap);
+ fclose(f);
+
+ st->print_cr("Virtual Size: " SSIZE_FORMAT "K (peak: " SSIZE_FORMAT "K)", vmsize, vmpeak);
+ st->print("Resident Set Size: " SSIZE_FORMAT "K (peak: " SSIZE_FORMAT "K)", vmrss, vmhwm);
+ if (rssanon != -1) { // requires kernel >= 4.5
+ st->print(" (anon: " SSIZE_FORMAT "K, file: " SSIZE_FORMAT "K, shmem: " SSIZE_FORMAT "K)",
+ rssanon, rssfile, rssshmem);
+ }
+ st->cr();
+ if (vmswap != -1) { // requires kernel >= 2.6.34
+ st->print_cr("Swapped out: " SSIZE_FORMAT "K", vmswap);
+ }
+ } else {
+ st->print_cr("Could not open /proc/self/status to get process memory related information");
}
// Print glibc outstanding allocations.
@@ -2642,6 +2667,7 @@
}
char dli_fname[MAXPATHLEN];
+ dli_fname[0] = '\0';
bool ret = dll_address_to_library_name(
CAST_FROM_FN_PTR(address, os::jvm_path),
dli_fname, sizeof(dli_fname), NULL);
@@ -3508,6 +3534,9 @@
if (mincore((address)stack_extent, os::vm_page_size(), vec) == -1) {
// Fallback to slow path on all errors, including EAGAIN
+ assert((uintptr_t)addr >= stack_extent,
+ "Sanity: addr should be larger than extent, " PTR_FORMAT " >= " PTR_FORMAT,
+ p2i(addr), stack_extent);
stack_extent = (uintptr_t) get_stack_commited_bottom(
os::Linux::initial_thread_stack_bottom(),
(size_t)addr - stack_extent);
@@ -5736,9 +5765,7 @@
// create binary file, rewriting existing file if required
int os::create_binary_file(const char* path, bool rewrite_existing) {
int oflags = O_WRONLY | O_CREAT;
- if (!rewrite_existing) {
- oflags |= O_EXCL;
- }
+ oflags |= rewrite_existing ? O_TRUNC : O_EXCL;
return ::open64(path, oflags, S_IREAD | S_IWRITE);
}
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/os/linux/perfMemory_linux.cpp openjdk-lts-11.0.14+9/src/hotspot/os/linux/perfMemory_linux.cpp
--- openjdk-lts-11.0.11+9/src/hotspot/os/linux/perfMemory_linux.cpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/os/linux/perfMemory_linux.cpp 2022-01-13 21:56:25.000000000 +0000
@@ -467,7 +467,7 @@
char* pwbuf = NEW_C_HEAP_ARRAY(char, bufsize, mtInternal);
// POSIX interface to getpwuid_r is used on LINUX
- struct passwd* p;
+ struct passwd* p = NULL;
int result = getpwuid_r(uid, &pwent, pwbuf, (size_t)bufsize, &p);
if (result != 0 || p == NULL || p->pw_name == NULL || *(p->pw_name) == '\0') {
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/os/posix/os_posix.cpp openjdk-lts-11.0.14+9/src/hotspot/os/posix/os_posix.cpp
--- openjdk-lts-11.0.11+9/src/hotspot/os/posix/os_posix.cpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/os/posix/os_posix.cpp 2022-01-13 21:56:25.000000000 +0000
@@ -1362,7 +1362,11 @@
os->print(", si_addr: " PTR_FORMAT, p2i(si->si_addr));
#ifdef SIGPOLL
} else if (sig == SIGPOLL) {
- os->print(", si_band: %ld", si->si_band);
+ // siginfo_t.si_band is defined as "long", and it is so in most
+ // implementations. But SPARC64 glibc has a bug: si_band is "int".
+ // Cast si_band to "long" to prevent format specifier mismatch.
+ // See: https://sourceware.org/bugzilla/show_bug.cgi?id=23821
+ os->print(", si_band: %ld", (long) si->si_band);
#endif
}
@@ -2016,7 +2020,8 @@
while (_event < 0) {
// OS-level "spurious wakeups" are ignored
status = pthread_cond_wait(_cond, _mutex);
- assert_status(status == 0, status, "cond_wait");
+ assert_status(status == 0 MACOS_ONLY(|| status == ETIMEDOUT),
+ status, "cond_wait");
}
--_nParked;
@@ -2211,7 +2216,8 @@
if (time == 0) {
_cur_index = REL_INDEX; // arbitrary choice when not timed
status = pthread_cond_wait(&_cond[_cur_index], _mutex);
- assert_status(status == 0, status, "cond_timedwait");
+ assert_status(status == 0 MACOS_ONLY(|| status == ETIMEDOUT),
+ status, "cond_wait");
}
else {
_cur_index = isAbsolute ? ABS_INDEX : REL_INDEX;
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/os/solaris/attachListener_solaris.cpp openjdk-lts-11.0.14+9/src/hotspot/os/solaris/attachListener_solaris.cpp
--- openjdk-lts-11.0.11+9/src/hotspot/os/solaris/attachListener_solaris.cpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/os/solaris/attachListener_solaris.cpp 2022-01-13 21:56:25.000000000 +0000
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2005, 2018, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2005, 2019, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@@ -75,17 +75,7 @@
// door descriptor returned by door_create
static int _door_descriptor;
- static void set_door_path(char* path) {
- if (path == NULL) {
- _has_door_path = false;
- } else {
- strncpy(_door_path, path, PATH_MAX);
- _door_path[PATH_MAX] = '\0'; // ensure it's nul terminated
- _has_door_path = true;
- }
- }
-
- static void set_door_descriptor(int dd) { _door_descriptor = dd; }
+ static bool _atexit_registered;
// mutex to protect operation list
static mutex_t _mutex;
@@ -121,6 +111,19 @@
ATTACH_ERROR_DENIED = 104
};
+ static void set_door_path(char* path) {
+ if (path == NULL) {
+ _door_path[0] = '\0';
+ _has_door_path = false;
+ } else {
+ strncpy(_door_path, path, PATH_MAX);
+ _door_path[PATH_MAX] = '\0'; // ensure it's nul terminated
+ _has_door_path = true;
+ }
+ }
+
+ static void set_door_descriptor(int dd) { _door_descriptor = dd; }
+
// initialize the listener
static int init();
@@ -169,6 +172,7 @@
char SolarisAttachListener::_door_path[PATH_MAX+1];
volatile bool SolarisAttachListener::_has_door_path;
int SolarisAttachListener::_door_descriptor = -1;
+bool SolarisAttachListener::_atexit_registered = false;
mutex_t SolarisAttachListener::_mutex;
sema_t SolarisAttachListener::_wakeup;
SolarisAttachOperation* SolarisAttachListener::_head = NULL;
@@ -359,18 +363,16 @@
// atexit hook to detach the door and remove the file
extern "C" {
static void listener_cleanup() {
- static int cleanup_done;
- if (!cleanup_done) {
- cleanup_done = 1;
- int dd = SolarisAttachListener::door_descriptor();
- if (dd >= 0) {
- ::close(dd);
- }
- if (SolarisAttachListener::has_door_path()) {
- char* path = SolarisAttachListener::door_path();
- ::fdetach(path);
- ::unlink(path);
- }
+ int dd = SolarisAttachListener::door_descriptor();
+ if (dd >= 0) {
+ SolarisAttachListener::set_door_descriptor(-1);
+ ::close(dd);
+ }
+ if (SolarisAttachListener::has_door_path()) {
+ char* path = SolarisAttachListener::door_path();
+ ::fdetach(path);
+ ::unlink(path);
+ SolarisAttachListener::set_door_path(NULL);
}
}
}
@@ -382,7 +384,10 @@
int fd, res;
// register exit function
- ::atexit(listener_cleanup);
+ if (!_atexit_registered) {
+ _atexit_registered = true;
+ ::atexit(listener_cleanup);
+ }
// create the door descriptor
int dd = ::door_create(enqueue_proc, NULL, 0);
@@ -638,6 +643,26 @@
}
}
+bool AttachListener::check_socket_file() {
+ int ret;
+ struct stat64 st;
+ ret = stat64(SolarisAttachListener::door_path(), &st);
+ if (ret == -1) { // need to restart attach listener.
+ log_debug(attach)("Door file %s does not exist - Restart Attach Listener",
+ SolarisAttachListener::door_path());
+
+ listener_cleanup();
+
+ // wait to terminate current attach listener instance...
+ while (AttachListener::transit_state(AL_INITIALIZING,
+ AL_NOT_INITIALIZED) != AL_NOT_INITIALIZED) {
+ os::naked_yield();
+ }
+ return is_init_trigger();
+ }
+ return false;
+}
+
// If the file .attach_pid exists in the working directory
// or /tmp then this is the trigger to start the attach mechanism
bool AttachListener::is_init_trigger() {
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/os/solaris/os_solaris.cpp openjdk-lts-11.0.14+9/src/hotspot/os/solaris/os_solaris.cpp
--- openjdk-lts-11.0.11+9/src/hotspot/os/solaris/os_solaris.cpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/os/solaris/os_solaris.cpp 2022-01-13 21:56:25.000000000 +0000
@@ -1343,7 +1343,7 @@
::abort(); // dump core (for debugging)
}
- ::exit(1);
+ ::_exit(1);
}
// Die immediately, no exit hook, no abort hook, no cleanup.
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/os/windows/attachListener_windows.cpp openjdk-lts-11.0.14+9/src/hotspot/os/windows/attachListener_windows.cpp
--- openjdk-lts-11.0.11+9/src/hotspot/os/windows/attachListener_windows.cpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/os/windows/attachListener_windows.cpp 2022-01-13 21:56:25.000000000 +0000
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2005, 2018, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2005, 2019, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@@ -387,6 +387,12 @@
return Win32AttachListener::init();
}
+// This function is used for Un*x OSes only.
+// We need not to implement it for Windows.
+bool AttachListener::check_socket_file() {
+ return false;
+}
+
bool AttachListener::init_at_startup() {
return true;
}
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/os/windows/os_perf_windows.cpp openjdk-lts-11.0.14+9/src/hotspot/os/windows/os_perf_windows.cpp
--- openjdk-lts-11.0.11+9/src/hotspot/os/windows/os_perf_windows.cpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/os/windows/os_perf_windows.cpp 2022-01-13 21:56:25.000000000 +0000
@@ -32,7 +32,7 @@
#include "runtime/os.hpp"
#include "utilities/globalDefinitions.hpp"
#include "utilities/macros.hpp"
-#include "vm_version_ext_x86.hpp"
+#include CPU_HEADER(vm_version_ext)
#include
#include
#include
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/os/windows/os_windows.cpp openjdk-lts-11.0.14+9/src/hotspot/os/windows/os_windows.cpp
--- openjdk-lts-11.0.11+9/src/hotspot/os/windows/os_windows.cpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/os/windows/os_windows.cpp 2022-01-13 21:56:25.000000000 +0000
@@ -31,6 +31,7 @@
#include "classfile/systemDictionary.hpp"
#include "classfile/vmSymbols.hpp"
#include "code/icBuffer.hpp"
+#include "code/nativeInst.hpp"
#include "code/vtableStubs.hpp"
#include "compiler/compileBroker.hpp"
#include "compiler/disassembler.hpp"
@@ -56,9 +57,9 @@
#include "runtime/orderAccess.hpp"
#include "runtime/osThread.hpp"
#include "runtime/perfMemory.hpp"
+#include "runtime/safefetch.inline.hpp"
#include "runtime/sharedRuntime.hpp"
#include "runtime/statSampler.hpp"
-#include "runtime/stubRoutines.hpp"
#include "runtime/thread.inline.hpp"
#include "runtime/threadCritical.hpp"
#include "runtime/timer.hpp"
@@ -120,12 +121,19 @@
static FILETIME process_user_time;
static FILETIME process_kernel_time;
-#ifdef _M_AMD64
+#if defined(_M_ARM64)
+ #define __CPU__ aarch64
+#elif defined(_M_AMD64)
#define __CPU__ amd64
#else
#define __CPU__ i486
#endif
+#if defined(USE_VECTORED_EXCEPTION_HANDLING)
+PVOID topLevelVectoredExceptionHandler = NULL;
+LPTOP_LEVEL_EXCEPTION_FILTER previousUnhandledExceptionFilter = NULL;
+#endif
+
// save DLL module handle, used by GetModuleFileName
HINSTANCE vm_lib_handle;
@@ -144,6 +152,12 @@
if (ForceTimeHighResolution) {
timeEndPeriod(1L);
}
+#if defined(USE_VECTORED_EXCEPTION_HANDLING)
+ if (topLevelVectoredExceptionHandler != NULL) {
+ RemoveVectoredExceptionHandler(topLevelVectoredExceptionHandler);
+ topLevelVectoredExceptionHandler = NULL;
+ }
+#endif
break;
default:
break;
@@ -417,6 +431,7 @@
return NULL;
}
+JNIEXPORT
LONG WINAPI topLevelExceptionFilter(struct _EXCEPTION_POINTERS* exceptionInfo);
// Thread start routine for all newly created threads
@@ -453,6 +468,12 @@
log_info(os, thread)("Thread is alive (tid: " UINTX_FORMAT ").", os::current_thread_id());
+#ifdef USE_VECTORED_EXCEPTION_HANDLING
+ // Any exception is caught by the Vectored Exception Handler, so VM can
+ // generate error dump when an exception occurred in non-Java thread
+ // (e.g. VM thread).
+ thread->call_run();
+#else
// Install a win32 structured exception handler around every thread created
// by VM, so VM can generate error dump when an exception occurred in non-
// Java thread (e.g. VM thread).
@@ -462,6 +483,7 @@
(_EXCEPTION_POINTERS*)_exception_info())) {
// Nothing to do.
}
+#endif
// Note: at this point the thread object may already have deleted itself.
// Do not dereference it from here on out.
@@ -1425,15 +1447,18 @@
static const arch_t arch_array[] = {
{IMAGE_FILE_MACHINE_I386, (char*)"IA 32"},
- {IMAGE_FILE_MACHINE_AMD64, (char*)"AMD 64"}
+ {IMAGE_FILE_MACHINE_AMD64, (char*)"AMD 64"},
+ {IMAGE_FILE_MACHINE_ARM64, (char*)"ARM 64"}
};
-#if (defined _M_AMD64)
+#if (defined _M_ARM64)
+ static const uint16_t running_arch = IMAGE_FILE_MACHINE_ARM64;
+#elif (defined _M_AMD64)
static const uint16_t running_arch = IMAGE_FILE_MACHINE_AMD64;
#elif (defined _M_IX86)
static const uint16_t running_arch = IMAGE_FILE_MACHINE_I386;
#else
#error Method os::dll_load requires that one of following \
- is defined :_M_AMD64 or _M_IX86
+ is defined :_M_AMD64 or _M_IX86 or _M_ARM64
#endif
@@ -1705,11 +1730,19 @@
case 10000:
if (is_workstation) {
- st->print("10");
+ if (build_number >= 22000) {
+ st->print("11");
+ } else {
+ st->print("10");
+ }
} else {
- // distinguish Windows Server 2016 and 2019 by build number
- // Windows server 2019 GA 10/2018 build number is 17763
- if (build_number > 17762) {
+ // distinguish Windows Server by build number
+ // - 2016 GA 10/2016 build: 14393
+ // - 2019 GA 11/2018 build: 17763
+ // - 2022 GA 08/2021 build: 20348
+ if (build_number > 20347) {
+ st->print("Server 2022");
+ } else if (build_number > 17762) {
st->print("Server 2019");
} else {
st->print("Server 2016");
@@ -1728,7 +1761,8 @@
SYSTEM_INFO si;
ZeroMemory(&si, sizeof(SYSTEM_INFO));
GetNativeSystemInfo(&si);
- if (si.wProcessorArchitecture == PROCESSOR_ARCHITECTURE_AMD64) {
+ if ((si.wProcessorArchitecture == PROCESSOR_ARCHITECTURE_AMD64) ||
+ (si.wProcessorArchitecture == PROCESSOR_ARCHITECTURE_ARM64)) {
st->print(" , 64 bit");
}
@@ -2134,23 +2168,25 @@
LONG Handle_Exception(struct _EXCEPTION_POINTERS* exceptionInfo,
address handler) {
- JavaThread* thread = (JavaThread*) Thread::current_or_null();
- // Save pc in thread
-#ifdef _M_AMD64
- // Do not blow up if no thread info available.
- if (thread) {
- thread->set_saved_exception_pc((address)(DWORD_PTR)exceptionInfo->ContextRecord->Rip);
- }
- // Set pc to handler
- exceptionInfo->ContextRecord->Rip = (DWORD64)handler;
+ Thread* thread = Thread::current_or_null();
+
+#if defined(_M_AMD64)
+ #define PC_NAME Rip
+#elif defined(_M_IX86)
+ #define PC_NAME Eip
+#elif defined(_M_ARM64)
+ #define PC_NAME Pc
#else
- // Do not blow up if no thread info available.
- if (thread) {
- thread->set_saved_exception_pc((address)(DWORD_PTR)exceptionInfo->ContextRecord->Eip);
+ #error unknown architecture
+#endif
+
+ // Save pc in thread
+ if (thread != nullptr && thread->is_Java_thread()) {
+ ((JavaThread*)thread)->set_saved_exception_pc((address)(DWORD_PTR)exceptionInfo->ContextRecord->PC_NAME);
}
+
// Set pc to handler
- exceptionInfo->ContextRecord->Eip = (DWORD)(DWORD_PTR)handler;
-#endif
+ exceptionInfo->ContextRecord->PC_NAME = (DWORD64)handler;
// Continue the execution
return EXCEPTION_CONTINUE_EXECUTION;
@@ -2234,7 +2270,17 @@
LONG Handle_IDiv_Exception(struct _EXCEPTION_POINTERS* exceptionInfo) {
// handle exception caused by idiv; should only happen for -MinInt/-1
// (division by zero is handled explicitly)
-#ifdef _M_AMD64
+#if defined(_M_ARM64)
+ PCONTEXT ctx = exceptionInfo->ContextRecord;
+ address pc = (address)ctx->Sp;
+ assert(pc[0] == 0x83, "not an sdiv opcode"); //Fixme did i get the right opcode?
+ assert(ctx->X4 == min_jint, "unexpected idiv exception");
+ // set correct result values and continue after idiv instruction
+ ctx->Pc = (uint64_t)pc + 4; // idiv reg, reg, reg is 4 bytes
+ ctx->X4 = (uint64_t)min_jint; // result
+ ctx->X5 = (uint64_t)0; // remainder
+ // Continue the execution
+#elif defined(_M_AMD64)
PCONTEXT ctx = exceptionInfo->ContextRecord;
address pc = (address)ctx->Rip;
assert(pc[0] >= Assembler::REX && pc[0] <= Assembler::REX_WRXB && pc[1] == 0xF7 || pc[0] == 0xF7, "not an idiv opcode");
@@ -2265,6 +2311,7 @@
return EXCEPTION_CONTINUE_EXECUTION;
}
+#if defined(_M_AMD64) || defined(_M_IX86)
//-----------------------------------------------------------------------------
LONG WINAPI Handle_FLT_Exception(struct _EXCEPTION_POINTERS* exceptionInfo) {
PCONTEXT ctx = exceptionInfo->ContextRecord;
@@ -2310,6 +2357,7 @@
return EXCEPTION_CONTINUE_SEARCH;
}
+#endif
static inline void report_error(Thread* t, DWORD exception_code,
address addr, void* siginfo, void* context) {
@@ -2319,46 +2367,15 @@
// somewhere where we can find it in the minidump.
}
-bool os::win32::get_frame_at_stack_banging_point(JavaThread* thread,
- struct _EXCEPTION_POINTERS* exceptionInfo, address pc, frame* fr) {
- PEXCEPTION_RECORD exceptionRecord = exceptionInfo->ExceptionRecord;
- address addr = (address) exceptionRecord->ExceptionInformation[1];
- if (Interpreter::contains(pc)) {
- *fr = os::fetch_frame_from_context((void*)exceptionInfo->ContextRecord);
- if (!fr->is_first_java_frame()) {
- // get_frame_at_stack_banging_point() is only called when we
- // have well defined stacks so java_sender() calls do not need
- // to assert safe_for_sender() first.
- *fr = fr->java_sender();
- }
- } else {
- // more complex code with compiled code
- assert(!Interpreter::contains(pc), "Interpreted methods should have been handled above");
- CodeBlob* cb = CodeCache::find_blob(pc);
- if (cb == NULL || !cb->is_nmethod() || cb->is_frame_complete_at(pc)) {
- // Not sure where the pc points to, fallback to default
- // stack overflow handling
- return false;
- } else {
- *fr = os::fetch_frame_from_context((void*)exceptionInfo->ContextRecord);
- // in compiled code, the stack banging is performed just after the return pc
- // has been pushed on the stack
- *fr = frame(fr->sp() + 1, fr->fp(), (address)*(fr->sp()));
- if (!fr->is_java_frame()) {
- // See java_sender() comment above.
- *fr = fr->java_sender();
- }
- }
- }
- assert(fr->is_java_frame(), "Safety check");
- return true;
-}
-
//-----------------------------------------------------------------------------
+JNIEXPORT
LONG WINAPI topLevelExceptionFilter(struct _EXCEPTION_POINTERS* exceptionInfo) {
if (InterceptOSException) return EXCEPTION_CONTINUE_SEARCH;
- DWORD exception_code = exceptionInfo->ExceptionRecord->ExceptionCode;
-#ifdef _M_AMD64
+ PEXCEPTION_RECORD exception_record = exceptionInfo->ExceptionRecord;
+ DWORD exception_code = exception_record->ExceptionCode;
+#if defined(_M_ARM64)
+ address pc = (address) exceptionInfo->ContextRecord->Pc;
+#elif defined(_M_AMD64)
address pc = (address) exceptionInfo->ContextRecord->Rip;
#else
address pc = (address) exceptionInfo->ContextRecord->Eip;
@@ -2376,9 +2393,8 @@
// This is safe to do because we have a new/unique ExceptionInformation
// code for this condition.
if (exception_code == EXCEPTION_ACCESS_VIOLATION) {
- PEXCEPTION_RECORD exceptionRecord = exceptionInfo->ExceptionRecord;
- int exception_subcode = (int) exceptionRecord->ExceptionInformation[0];
- address addr = (address) exceptionRecord->ExceptionInformation[1];
+ int exception_subcode = (int) exception_record->ExceptionInformation[0];
+ address addr = (address) exception_record->ExceptionInformation[1];
if (exception_subcode == EXCEPTION_INFO_EXEC_VIOLATION) {
int page_size = os::vm_page_size();
@@ -2442,8 +2458,10 @@
// Last unguard failed or not unguarding
tty->print_raw_cr("Execution protection violation");
- report_error(t, exception_code, addr, exceptionInfo->ExceptionRecord,
+#if !defined(USE_VECTORED_EXCEPTION_HANDLING)
+ report_error(t, exception_code, addr, exception_record,
exceptionInfo->ContextRecord);
+#endif
return EXCEPTION_CONTINUE_SEARCH;
}
}
@@ -2456,33 +2474,33 @@
if (exception_code == EXCEPTION_ACCESS_VIOLATION) {
if (t != NULL && t->is_Java_thread()) {
JavaThread* thread = (JavaThread*) t;
- PEXCEPTION_RECORD exceptionRecord = exceptionInfo->ExceptionRecord;
- address addr = (address) exceptionRecord->ExceptionInformation[1];
+ address addr = (address) exception_record->ExceptionInformation[1];
if (os::is_memory_serialize_page(thread, addr)) {
// Block current thread until the memory serialize page permission restored.
os::block_on_serialize_page_trap();
return EXCEPTION_CONTINUE_EXECUTION;
}
}
- }
- if ((exception_code == EXCEPTION_ACCESS_VIOLATION) &&
- VM_Version::is_cpuinfo_segv_addr(pc)) {
- // Verify that OS save/restore AVX registers.
- return Handle_Exception(exceptionInfo, VM_Version::cpuinfo_cont_addr());
+#if defined(_M_AMD64) || defined(_M_IX86)
+ if (VM_Version::is_cpuinfo_segv_addr(pc)) {
+ // Verify that OS save/restore AVX registers.
+ return Handle_Exception(exceptionInfo, VM_Version::cpuinfo_cont_addr());
+ }
+#endif
}
if (t != NULL && t->is_Java_thread()) {
JavaThread* thread = (JavaThread*) t;
bool in_java = thread->thread_state() == _thread_in_Java;
+ bool in_native = thread->thread_state() == _thread_in_native;
+ bool in_vm = thread->thread_state() == _thread_in_vm;
// Handle potential stack overflows up front.
if (exception_code == EXCEPTION_STACK_OVERFLOW) {
if (thread->stack_guards_enabled()) {
if (in_java) {
frame fr;
- PEXCEPTION_RECORD exceptionRecord = exceptionInfo->ExceptionRecord;
- address addr = (address) exceptionRecord->ExceptionInformation[1];
if (os::win32::get_frame_at_stack_banging_point(thread, exceptionInfo, pc, &fr)) {
assert(fr.is_java_frame(), "Must be a Java frame");
SharedRuntime::look_for_reserved_stack_annotated_method(thread, fr);
@@ -2491,7 +2509,7 @@
// Yellow zone violation. The o/s has unprotected the first yellow
// zone page for us. Note: must call disable_stack_yellow_zone to
// update the enabled status, even if the zone contains only one page.
- assert(thread->thread_state() != _thread_in_vm, "Undersized StackShadowPages");
+ assert(!in_vm, "Undersized StackShadowPages");
thread->disable_stack_yellow_reserved_zone();
// If not in java code, return and hope for the best.
return in_java
@@ -2501,15 +2519,16 @@
// Fatal red zone violation.
thread->disable_stack_red_zone();
tty->print_raw_cr("An unrecoverable stack overflow has occurred.");
- report_error(t, exception_code, pc, exceptionInfo->ExceptionRecord,
- exceptionInfo->ContextRecord);
+#if !defined(USE_VECTORED_EXCEPTION_HANDLING)
+ report_error(t, exception_code, pc, exception_record,
+ exceptionInfo->ContextRecord);
+#endif
return EXCEPTION_CONTINUE_SEARCH;
}
} else if (exception_code == EXCEPTION_ACCESS_VIOLATION) {
- // Either stack overflow or null pointer exception.
if (in_java) {
- PEXCEPTION_RECORD exceptionRecord = exceptionInfo->ExceptionRecord;
- address addr = (address) exceptionRecord->ExceptionInformation[1];
+ // Either stack overflow or null pointer exception.
+ address addr = (address) exception_record->ExceptionInformation[1];
address stack_end = thread->stack_end();
if (addr < stack_end && addr >= stack_end - os::vm_page_size()) {
// Stack overflow.
@@ -2528,48 +2547,41 @@
return Handle_Exception(exceptionInfo, stub);
}
}
- {
#ifdef _WIN64
- // If it's a legal stack address map the entire region in
- //
- PEXCEPTION_RECORD exceptionRecord = exceptionInfo->ExceptionRecord;
- address addr = (address) exceptionRecord->ExceptionInformation[1];
- if (addr > thread->stack_reserved_zone_base() && addr < thread->stack_base()) {
- addr = (address)((uintptr_t)addr &
- (~((uintptr_t)os::vm_page_size() - (uintptr_t)1)));
- os::commit_memory((char *)addr, thread->stack_base() - addr,
- !ExecMem);
- return EXCEPTION_CONTINUE_EXECUTION;
- } else
-#endif
- {
- // Null pointer exception.
- if (!MacroAssembler::needs_explicit_null_check((intptr_t)addr)) {
- address stub = SharedRuntime::continuation_for_implicit_exception(thread, pc, SharedRuntime::IMPLICIT_NULL);
- if (stub != NULL) return Handle_Exception(exceptionInfo, stub);
- }
- report_error(t, exception_code, pc, exceptionInfo->ExceptionRecord,
- exceptionInfo->ContextRecord);
- return EXCEPTION_CONTINUE_SEARCH;
- }
+ // If it's a legal stack address, map the entire region in
+ if (addr > thread->stack_reserved_zone_base() && addr < thread->stack_base()) {
+ addr = (address)((uintptr_t)addr &
+ (~((uintptr_t)os::vm_page_size() - (uintptr_t)1)));
+ os::commit_memory((char *)addr, thread->stack_base() - addr,
+ !ExecMem);
+ return EXCEPTION_CONTINUE_EXECUTION;
}
+#endif
+ // Null pointer exception.
+ if (!MacroAssembler::needs_explicit_null_check((intptr_t)addr)) {
+ address stub = SharedRuntime::continuation_for_implicit_exception(thread, pc, SharedRuntime::IMPLICIT_NULL);
+ if (stub != NULL) return Handle_Exception(exceptionInfo, stub);
+ }
+ report_error(t, exception_code, pc, exception_record,
+ exceptionInfo->ContextRecord);
+ return EXCEPTION_CONTINUE_SEARCH;
}
#ifdef _WIN64
// Special care for fast JNI field accessors.
// jni_fast_GetField can trap at certain pc's if a GC kicks
// in and the heap gets shrunk before the field access.
- if (exception_code == EXCEPTION_ACCESS_VIOLATION) {
- address addr = JNI_FastGetField::find_slowcase_pc(pc);
- if (addr != (address)-1) {
- return Handle_Exception(exceptionInfo, addr);
- }
+ address slowcase_pc = JNI_FastGetField::find_slowcase_pc(pc);
+ if (slowcase_pc != (address)-1) {
+ return Handle_Exception(exceptionInfo, slowcase_pc);
}
#endif
// Stack overflow or null pointer exception in native code.
- report_error(t, exception_code, pc, exceptionInfo->ExceptionRecord,
+#if !defined(USE_VECTORED_EXCEPTION_HANDLING)
+ report_error(t, exception_code, pc, exception_record,
exceptionInfo->ContextRecord);
+#endif
return EXCEPTION_CONTINUE_SEARCH;
} // /EXCEPTION_ACCESS_VIOLATION
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
@@ -2581,13 +2593,25 @@
CodeBlob* cb = CodeCache::find_blob_unsafe(pc);
nm = (cb != NULL) ? cb->as_compiled_method_or_null() : NULL;
}
- if ((thread->thread_state() == _thread_in_vm &&
- thread->doing_unsafe_access()) ||
+ if ((in_vm && thread->doing_unsafe_access()) ||
(nm != NULL && nm->has_unsafe_access())) {
return Handle_Exception(exceptionInfo, SharedRuntime::handle_unsafe_access(thread, (address)Assembler::locate_next_instruction(pc)));
}
}
+#ifdef _M_ARM64
+ if (in_java &&
+ (exception_code == EXCEPTION_ILLEGAL_INSTRUCTION ||
+ exception_code == EXCEPTION_ILLEGAL_INSTRUCTION_2)) {
+ if (nativeInstruction_at(pc)->is_sigill_zombie_not_entrant()) {
+ if (TraceTraps) {
+ tty->print_cr("trap: zombie_not_entrant");
+ }
+ return Handle_Exception(exceptionInfo, SharedRuntime::get_handle_wrong_method_stub());
+ }
+ }
+#endif
+
if (in_java) {
switch (exception_code) {
case EXCEPTION_INT_DIVIDE_BY_ZERO:
@@ -2598,21 +2622,75 @@
} // switch
}
- if (((thread->thread_state() == _thread_in_Java) ||
- (thread->thread_state() == _thread_in_native)) &&
- exception_code != EXCEPTION_UNCAUGHT_CXX_EXCEPTION) {
+
+#if defined(_M_AMD64) || defined(_M_IX86)
+ if ((in_java || in_native) && exception_code != EXCEPTION_UNCAUGHT_CXX_EXCEPTION) {
LONG result=Handle_FLT_Exception(exceptionInfo);
if (result==EXCEPTION_CONTINUE_EXECUTION) return result;
}
+#endif
}
+#if !defined(USE_VECTORED_EXCEPTION_HANDLING)
if (exception_code != EXCEPTION_BREAKPOINT) {
- report_error(t, exception_code, pc, exceptionInfo->ExceptionRecord,
+ report_error(t, exception_code, pc, exception_record,
exceptionInfo->ContextRecord);
}
+#endif
return EXCEPTION_CONTINUE_SEARCH;
}
+#if defined(USE_VECTORED_EXCEPTION_HANDLING)
+LONG WINAPI topLevelVectoredExceptionFilter(struct _EXCEPTION_POINTERS* exceptionInfo) {
+ PEXCEPTION_RECORD exceptionRecord = exceptionInfo->ExceptionRecord;
+#if defined(_M_ARM64)
+ address pc = (address) exceptionInfo->ContextRecord->Pc;
+#elif defined(_M_AMD64)
+ address pc = (address) exceptionInfo->ContextRecord->Rip;
+#else
+ address pc = (address) exceptionInfo->ContextRecord->Eip;
+#endif
+
+ // Fast path for code part of the code cache
+ if (CodeCache::low_bound() <= pc && pc < CodeCache::high_bound()) {
+ return topLevelExceptionFilter(exceptionInfo);
+ }
+
+ // Handle the case where we get an implicit exception in AOT generated
+ // code. AOT DLL's loaded are not registered for structured exceptions.
+ // If the exception occurred in the codeCache or AOT code, pass control
+ // to our normal exception handler.
+ CodeBlob* cb = CodeCache::find_blob(pc);
+ if (cb != NULL) {
+ return topLevelExceptionFilter(exceptionInfo);
+ }
+
+ return EXCEPTION_CONTINUE_SEARCH;
+}
+#endif
+
+#if defined(USE_VECTORED_EXCEPTION_HANDLING)
+LONG WINAPI topLevelUnhandledExceptionFilter(struct _EXCEPTION_POINTERS* exceptionInfo) {
+ if (InterceptOSException) goto exit;
+ DWORD exception_code = exceptionInfo->ExceptionRecord->ExceptionCode;
+#if defined(_M_ARM64)
+ address pc = (address) exceptionInfo->ContextRecord->Pc;
+#elif defined(_M_AMD64)
+ address pc = (address) exceptionInfo->ContextRecord->Rip;
+#else
+ address pc = (address) exceptionInfo->ContextRecord->Eip;
+#endif
+ Thread* t = Thread::current_or_null_safe();
+
+ if (exception_code != EXCEPTION_BREAKPOINT) {
+ report_error(t, exception_code, pc, exceptionInfo->ExceptionRecord,
+ exceptionInfo->ContextRecord);
+ }
+exit:
+ return previousUnhandledExceptionFilter ? previousUnhandledExceptionFilter(exceptionInfo) : EXCEPTION_CONTINUE_SEARCH;
+}
+#endif
+
#ifndef _WIN64
// Special care for fast JNI accessors.
// jni_fast_GetField can trap at certain pc's if a GC kicks in and
@@ -3081,8 +3159,9 @@
assert(extra_size >= size, "overflow, size is too large to allow alignment");
char* aligned_base = NULL;
+ static const int max_attempts = 20;
- do {
+ for (int attempt = 0; attempt < max_attempts && aligned_base == NULL; attempt ++) {
char* extra_base = os::reserve_memory(extra_size, NULL, alignment, file_desc);
if (extra_base == NULL) {
return NULL;
@@ -3090,15 +3169,22 @@
// Do manual alignment
aligned_base = align_up(extra_base, alignment);
+ bool rc = false;
if (file_desc != -1) {
- os::unmap_memory(extra_base, extra_size);
+ rc = os::unmap_memory(extra_base, extra_size);
} else {
- os::release_memory(extra_base, extra_size);
+ rc = os::release_memory(extra_base, extra_size);
+ }
+ assert(rc, "release failed");
+ if (!rc) {
+ return NULL;
}
aligned_base = os::reserve_memory(size, aligned_base, 0, file_desc);
- } while (aligned_base == NULL);
+ }
+
+ assert(aligned_base != NULL, "Did not manage to re-map after %d attempts?", max_attempts);
return aligned_base;
}
@@ -3453,7 +3539,12 @@
// Must never look like an address returned by reserve_memory,
// even in its subfields (as defined by the CPU immediate fields,
// if the CPU splits constants across multiple instructions).
+#ifdef _M_ARM64
+ // AArch64 has a maximum addressable space of 48-bits
+ return (char*)((1ull << 48) - 1);
+#else
return (char*)-1;
+#endif
}
#define MAX_ERROR_COUNT 100
@@ -4127,6 +4218,11 @@
jint os::init_2(void) {
// Setup Windows Exceptions
+#if defined(USE_VECTORED_EXCEPTION_HANDLING)
+ topLevelVectoredExceptionHandler = AddVectoredExceptionHandler(1, topLevelVectoredExceptionFilter);
+ previousUnhandledExceptionFilter = SetUnhandledExceptionFilter(topLevelUnhandledExceptionFilter);
+#endif
+
// for debugging float code generation bugs
if (ForceFloatExceptions) {
#ifndef _WIN64
@@ -4590,9 +4686,7 @@
// create binary file, rewriting existing file if required
int os::create_binary_file(const char* path, bool rewrite_existing) {
int oflags = _O_CREAT | _O_WRONLY | _O_BINARY;
- if (!rewrite_existing) {
- oflags |= _O_EXCL;
- }
+ oflags |= rewrite_existing ? _O_TRUNC : _O_EXCL;
return ::open(path, oflags, _S_IREAD | _S_IWRITE);
}
@@ -4919,15 +5013,25 @@
char* os::pd_map_memory(int fd, const char* file_name, size_t file_offset,
char *addr, size_t bytes, bool read_only,
bool allow_exec) {
+
+ errno_t err;
+ wchar_t* wide_path = wide_abs_unc_path(file_name, err);
+
+ if (wide_path == NULL) {
+ return NULL;
+ }
+
HANDLE hFile;
char* base;
- hFile = CreateFile(file_name, GENERIC_READ, FILE_SHARE_READ, NULL,
+ hFile = CreateFileW(wide_path, GENERIC_READ, FILE_SHARE_READ, NULL,
OPEN_EXISTING, FILE_ATTRIBUTE_NORMAL, NULL);
if (hFile == INVALID_HANDLE_VALUE) {
- log_info(os)("CreateFile() failed: GetLastError->%ld.", GetLastError());
+ log_info(os)("CreateFileW() failed: GetLastError->%ld.", GetLastError());
+ os::free(wide_path);
return NULL;
}
+ os::free(wide_path);
if (allow_exec) {
// CreateFileMapping/MapViewOfFileEx can't map executable memory
@@ -5491,7 +5595,7 @@
// WINDOWS CONTEXT Flags for THREAD_SAMPLING
#if defined(IA32)
#define sampling_context_flags (CONTEXT_FULL | CONTEXT_FLOATING_POINT | CONTEXT_EXTENDED_REGISTERS)
-#elif defined (AMD64)
+#elif defined(AMD64) || defined(_M_ARM64)
#define sampling_context_flags (CONTEXT_FULL | CONTEXT_FLOATING_POINT)
#endif
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/os/windows/threadCritical_windows.cpp openjdk-lts-11.0.14+9/src/hotspot/os/windows/threadCritical_windows.cpp
--- openjdk-lts-11.0.11+9/src/hotspot/os/windows/threadCritical_windows.cpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/os/windows/threadCritical_windows.cpp 2022-01-13 21:56:25.000000000 +0000
@@ -35,10 +35,10 @@
// See threadCritical.hpp for details of this class.
//
-static bool initialized = false;
-static volatile int lock_count = -1;
+static INIT_ONCE initialized = INIT_ONCE_STATIC_INIT;
+static int lock_count = 0;
static HANDLE lock_event;
-static DWORD lock_owner = -1;
+static DWORD lock_owner = 0;
//
// Note that Microsoft's critical region code contains a race
@@ -51,48 +51,36 @@
// and found them ~30 times slower than the critical region code.
//
+static BOOL WINAPI initialize(PINIT_ONCE InitOnce, PVOID Parameter, PVOID *Context) {
+ lock_event = CreateEvent(NULL, false, true, NULL);
+ assert(lock_event != NULL, "unexpected return value from CreateEvent");
+ return true;
+}
+
ThreadCritical::ThreadCritical() {
- DWORD current_thread = GetCurrentThreadId();
+ InitOnceExecuteOnce(&initialized, &initialize, NULL, NULL);
+ DWORD current_thread = GetCurrentThreadId();
if (lock_owner != current_thread) {
// Grab the lock before doing anything.
- while (Atomic::cmpxchg(0, &lock_count, -1) != -1) {
- if (initialized) {
- DWORD ret = WaitForSingleObject(lock_event, INFINITE);
- assert(ret == WAIT_OBJECT_0, "unexpected return value from WaitForSingleObject");
- }
- }
-
- // Make sure the event object is allocated.
- if (!initialized) {
- // Locking will not work correctly unless this is autoreset.
- lock_event = CreateEvent(NULL, false, false, NULL);
- initialized = true;
- }
-
- assert(lock_owner == -1, "Lock acquired illegally.");
+ DWORD ret = WaitForSingleObject(lock_event, INFINITE);
+ assert(ret == WAIT_OBJECT_0, "unexpected return value from WaitForSingleObject");
lock_owner = current_thread;
- } else {
- // Atomicity isn't required. Bump the recursion count.
- lock_count++;
}
-
- assert(lock_owner == GetCurrentThreadId(), "Lock acquired illegally.");
+ // Atomicity isn't required. Bump the recursion count.
+ lock_count++;
}
ThreadCritical::~ThreadCritical() {
assert(lock_owner == GetCurrentThreadId(), "unlock attempt by wrong thread");
assert(lock_count >= 0, "Attempt to unlock when already unlocked");
+ lock_count--;
if (lock_count == 0) {
// We're going to unlock
- lock_owner = -1;
- lock_count = -1;
+ lock_owner = 0;
// No lost wakeups, lock_event stays signaled until reset.
DWORD ret = SetEvent(lock_event);
assert(ret != 0, "unexpected return value from SetEvent");
- } else {
- // Just unwinding a recursive lock;
- lock_count--;
}
}
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/os_cpu/bsd_x86/os_bsd_x86.cpp openjdk-lts-11.0.14+9/src/hotspot/os_cpu/bsd_x86/os_bsd_x86.cpp
--- openjdk-lts-11.0.11+9/src/hotspot/os_cpu/bsd_x86/os_bsd_x86.cpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/os_cpu/bsd_x86/os_bsd_x86.cpp 2022-01-13 21:56:25.000000000 +0000
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 1999, 2017, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 1999, 2021, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@@ -64,7 +64,6 @@
# include
# include
# include
-# include
# include
# include
# include
@@ -492,15 +491,15 @@
}
}
}
-/*
- NOTE: does not seem to work on bsd.
- if (info == NULL || info->si_code <= 0 || info->si_code == SI_NOINFO) {
- // can't decode this kind of signal
- info = NULL;
- } else {
- assert(sig == info->si_signo, "bad siginfo");
+
+ // Handle SafeFetch faults:
+ if (uc != NULL) {
+ address const pc = (address) os::Bsd::ucontext_get_pc(uc);
+ if (pc && StubRoutines::is_safefetch_fault(pc)) {
+ os::Bsd::ucontext_set_pc(uc, StubRoutines::continuation_for_safefetch_fault(pc));
+ return 1;
+ }
}
-*/
// decide if this trap can be handled by a stub
address stub = NULL;
@@ -510,11 +509,6 @@
if (info != NULL && uc != NULL && thread != NULL) {
pc = (address) os::Bsd::ucontext_get_pc(uc);
- if (StubRoutines::is_safefetch_fault(pc)) {
- os::Bsd::ucontext_set_pc(uc, StubRoutines::continuation_for_safefetch_fault(pc));
- return 1;
- }
-
// Handle ALL stack overflow variations here
if (sig == SIGSEGV || sig == SIGBUS) {
address addr = (address) info->si_addr;
@@ -598,7 +592,13 @@
#ifdef AMD64
if (sig == SIGFPE &&
- (info->si_code == FPE_INTDIV || info->si_code == FPE_FLTDIV)) {
+ (info->si_code == FPE_INTDIV || info->si_code == FPE_FLTDIV
+ // Workaround for macOS ARM incorrectly reporting FPE_FLTINV for "div by 0"
+ // instead of the expected FPE_FLTDIV when running x86_64 binary under Rosetta emulation
+#ifdef __APPLE__
+ || (VM_Version::is_cpu_emulated() && info->si_code == FPE_FLTINV)
+#endif
+ )) {
stub =
SharedRuntime::
continuation_for_implicit_exception(thread,
@@ -633,7 +633,7 @@
int op = pc[0];
if (op == 0xDB) {
// FIST
- // TODO: The encoding of D2I in i486.ad can cause an exception
+ // TODO: The encoding of D2I in x86_32.ad can cause an exception
// prior to the fist instruction if there was an invalid operation
// pending. We want to dismiss that exception. From the win_32
// side it also seems that if it really was the fist causing
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/os_cpu/bsd_x86/vm_version_bsd_x86.cpp openjdk-lts-11.0.14+9/src/hotspot/os_cpu/bsd_x86/vm_version_bsd_x86.cpp
--- openjdk-lts-11.0.11+9/src/hotspot/os_cpu/bsd_x86/vm_version_bsd_x86.cpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/os_cpu/bsd_x86/vm_version_bsd_x86.cpp 2022-01-13 21:56:25.000000000 +0000
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2006, 2010, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2006, 2021, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@@ -24,4 +24,25 @@
#include "precompiled.hpp"
#include "runtime/os.hpp"
-#include "vm_version_x86.hpp"
+#include "runtime/vm_version.hpp"
+
+#ifdef __APPLE__
+
+#include
+#include
+
+bool VM_Version::is_cpu_emulated() {
+ int ret = 0;
+ size_t size = sizeof(ret);
+ // Is this process being ran in Rosetta (i.e. emulation) mode on macOS?
+ if (sysctlbyname("sysctl.proc_translated", &ret, &size, NULL, 0) == -1) {
+ // errno == ENOENT is a valid response, but anything else is a real error
+ if (errno != ENOENT) {
+ warning("unable to lookup sysctl.proc_translated");
+ }
+ }
+ return (ret==1);
+}
+
+#endif
+
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/os_cpu/bsd_zero/vm_version_bsd_zero.cpp openjdk-lts-11.0.14+9/src/hotspot/os_cpu/bsd_zero/vm_version_bsd_zero.cpp
--- openjdk-lts-11.0.11+9/src/hotspot/os_cpu/bsd_zero/vm_version_bsd_zero.cpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/os_cpu/bsd_zero/vm_version_bsd_zero.cpp 2022-01-13 21:56:25.000000000 +0000
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 1997, 2019, Oracle and/or its affiliates. All rights reserved.
* Copyright 2009 Red Hat, Inc.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
@@ -25,6 +25,6 @@
#include "precompiled.hpp"
#include "runtime/os.hpp"
-#include "vm_version_zero.hpp"
+#include "runtime/vm_version.hpp"
// This file is intentionally empty
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/os_cpu/linux_aarch64/atomic_linux_aarch64.hpp openjdk-lts-11.0.14+9/src/hotspot/os_cpu/linux_aarch64/atomic_linux_aarch64.hpp
--- openjdk-lts-11.0.11+9/src/hotspot/os_cpu/linux_aarch64/atomic_linux_aarch64.hpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/os_cpu/linux_aarch64/atomic_linux_aarch64.hpp 2022-01-13 21:56:25.000000000 +0000
@@ -1,6 +1,6 @@
/*
- * Copyright (c) 1999, 2018, Oracle and/or its affiliates. All rights reserved.
- * Copyright (c) 2014, Red Hat Inc. All rights reserved.
+ * Copyright (c) 1999, 2019, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2014, 2021, Red Hat Inc. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@@ -26,9 +26,11 @@
#ifndef OS_CPU_LINUX_AARCH64_VM_ATOMIC_LINUX_AARCH64_HPP
#define OS_CPU_LINUX_AARCH64_VM_ATOMIC_LINUX_AARCH64_HPP
-#include "vm_version_aarch64.hpp"
+#include "atomic_aarch64.hpp"
+#include "runtime/vm_version.hpp"
// Implementation of class atomic
+
// Note that memory_order_conservative requires a full barrier after atomic stores.
// See https://patchwork.kernel.org/patch/3575821/
@@ -36,49 +38,145 @@
#define READ_MEM_BARRIER __atomic_thread_fence(__ATOMIC_ACQUIRE);
#define WRITE_MEM_BARRIER __atomic_thread_fence(__ATOMIC_RELEASE);
+// Call one of the stubs from C++. This uses the C calling convention,
+// but this asm definition is used in order only to clobber the
+// registers we use. If we called the stubs via an ABI call we'd have
+// to save X0 - X18 and most of the vectors.
+//
+// This really ought to be a template definition, but see GCC Bug
+// 33661, template methods forget explicit local register asm
+// vars. The problem is that register specifiers attached to local
+// variables are ignored in any template function.
+inline uint64_t bare_atomic_fastcall(address stub, volatile void *ptr, uint64_t arg1, uint64_t arg2 = 0) {
+ register uint64_t reg0 __asm__("x0") = (uint64_t)ptr;
+ register uint64_t reg1 __asm__("x1") = arg1;
+ register uint64_t reg2 __asm__("x2") = arg2;
+ register uint64_t reg3 __asm__("x3") = (uint64_t)stub;
+ register uint64_t result __asm__("x0");
+ asm volatile(// "stp x29, x30, [sp, #-16]!;"
+ " blr %1;"
+ // " ldp x29, x30, [sp], #16 // regs %0, %1, %2, %3, %4"
+ : "=r"(result), "+r"(reg3), "+r"(reg2)
+ : "r"(reg1), "0"(reg0) : "x8", "x9", "x30", "cc", "memory");
+ return result;
+}
+
+template
+inline D atomic_fastcall(F stub, volatile D *dest, T1 arg1) {
+ return (D)bare_atomic_fastcall(CAST_FROM_FN_PTR(address, stub),
+ dest, (uint64_t)arg1);
+}
+
+template
+inline D atomic_fastcall(F stub, volatile D *dest, T1 arg1, T2 arg2) {
+ return (D)bare_atomic_fastcall(CAST_FROM_FN_PTR(address, stub),
+ dest, (uint64_t)arg1, (uint64_t)arg2);
+}
+
template
struct Atomic::PlatformAdd
- : Atomic::AddAndFetch >
+ : Atomic::FetchAndAdd >
{
template
- D add_and_fetch(I add_value, D volatile* dest, atomic_memory_order order) const {
- D res = __atomic_add_fetch(dest, add_value, __ATOMIC_RELEASE);
- FULL_MEM_BARRIER;
- return res;
- }
+ D fetch_and_add(I add_value, D volatile* dest, atomic_memory_order order) const;
};
-template
+template<>
+template
+inline D Atomic::PlatformAdd<4>::fetch_and_add(I add_value,
+ D volatile* dest,
+ atomic_memory_order order) const {
+ STATIC_ASSERT(4 == sizeof(I));
+ STATIC_ASSERT(4 == sizeof(D));
+ D old_value
+ = atomic_fastcall(aarch64_atomic_fetch_add_4_impl, dest, add_value);
+ return old_value;
+}
+
+template<>
+template
+inline D Atomic::PlatformAdd<8>::fetch_and_add(I add_value,
+ D volatile* dest,
+ atomic_memory_order order) const {
+ STATIC_ASSERT(8 == sizeof(I));
+ STATIC_ASSERT(8 == sizeof(D));
+ D old_value
+ = atomic_fastcall(aarch64_atomic_fetch_add_8_impl, dest, add_value);
+ return old_value;
+}
+
+template<>
template
-inline T Atomic::PlatformXchg::operator()(T exchange_value,
- T volatile* dest,
- atomic_memory_order order) const {
- STATIC_ASSERT(byte_size == sizeof(T));
- T res = __atomic_exchange_n(dest, exchange_value, __ATOMIC_RELEASE);
- FULL_MEM_BARRIER;
- return res;
+inline T Atomic::PlatformXchg<4>::operator()(T exchange_value,
+ T volatile* dest,
+ atomic_memory_order order) const {
+ STATIC_ASSERT(4 == sizeof(T));
+ T old_value = atomic_fastcall(aarch64_atomic_xchg_4_impl, dest, exchange_value);
+ return old_value;
}
-template
+template<>
template
-inline T Atomic::PlatformCmpxchg::operator()(T exchange_value,
- T volatile* dest,
- T compare_value,
- atomic_memory_order order) const {
- STATIC_ASSERT(byte_size == sizeof(T));
- if (order == memory_order_relaxed) {
- T value = compare_value;
- __atomic_compare_exchange(dest, &value, &exchange_value, /*weak*/false,
- __ATOMIC_RELAXED, __ATOMIC_RELAXED);
- return value;
- } else {
- T value = compare_value;
- FULL_MEM_BARRIER;
- __atomic_compare_exchange(dest, &value, &exchange_value, /*weak*/false,
- __ATOMIC_RELAXED, __ATOMIC_RELAXED);
- FULL_MEM_BARRIER;
- return value;
+inline T Atomic::PlatformXchg<8>::operator()(T exchange_value,
+ T volatile* dest,
+ atomic_memory_order order) const {
+ STATIC_ASSERT(8 == sizeof(T));
+ T old_value = atomic_fastcall(aarch64_atomic_xchg_8_impl, dest, exchange_value);
+ return old_value;
+}
+
+template<>
+template
+inline T Atomic::PlatformCmpxchg<1>::operator()(T exchange_value,
+ T volatile* dest,
+ T compare_value,
+ atomic_memory_order order) const {
+ STATIC_ASSERT(1 == sizeof(T));
+ aarch64_atomic_stub_t stub;
+ switch (order) {
+ case memory_order_relaxed:
+ stub = aarch64_atomic_cmpxchg_1_relaxed_impl; break;
+ default:
+ stub = aarch64_atomic_cmpxchg_1_impl; break;
+ }
+
+ return atomic_fastcall(stub, dest, compare_value, exchange_value);
+}
+
+template<>
+template
+inline T Atomic::PlatformCmpxchg<4>::operator()(T exchange_value,
+ T volatile* dest,
+ T compare_value,
+ atomic_memory_order order) const {
+ STATIC_ASSERT(4 == sizeof(T));
+ aarch64_atomic_stub_t stub;
+ switch (order) {
+ case memory_order_relaxed:
+ stub = aarch64_atomic_cmpxchg_4_relaxed_impl; break;
+ default:
+ stub = aarch64_atomic_cmpxchg_4_impl; break;
}
+
+ return atomic_fastcall(stub, dest, compare_value, exchange_value);
+}
+
+template<>
+template
+inline T Atomic::PlatformCmpxchg<8>::operator()(T exchange_value,
+ T volatile* dest,
+ T compare_value,
+ atomic_memory_order order) const {
+ STATIC_ASSERT(8 == sizeof(T));
+ aarch64_atomic_stub_t stub;
+ switch (order) {
+ case memory_order_relaxed:
+ stub = aarch64_atomic_cmpxchg_8_relaxed_impl; break;
+ default:
+ stub = aarch64_atomic_cmpxchg_8_impl; break;
+ }
+
+ return atomic_fastcall(stub, dest, compare_value, exchange_value);
}
#endif // OS_CPU_LINUX_AARCH64_VM_ATOMIC_LINUX_AARCH64_HPP
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/os_cpu/linux_aarch64/atomic_linux_aarch64.S openjdk-lts-11.0.14+9/src/hotspot/os_cpu/linux_aarch64/atomic_linux_aarch64.S
--- openjdk-lts-11.0.11+9/src/hotspot/os_cpu/linux_aarch64/atomic_linux_aarch64.S 1970-01-01 00:00:00.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/os_cpu/linux_aarch64/atomic_linux_aarch64.S 2022-01-13 21:56:25.000000000 +0000
@@ -0,0 +1,150 @@
+// Copyright (c) 2021, Red Hat Inc. All rights reserved.
+// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+
+// This code is free software; you can redistribute it and/or modify it
+// under the terms of the GNU General Public License version 2 only, as
+// published by the Free Software Foundation.
+
+// This code is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// version 2 for more details (a copy is included in the LICENSE file that
+// accompanied this code).
+
+// You should have received a copy of the GNU General Public License version
+// 2 along with this work; if not, write to the Free Software Foundation,
+// Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
+
+// Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
+// or visit www.oracle.com if you need additional information or have any
+// questions.
+
+
+
+ .text
+
+ .globl aarch64_atomic_fetch_add_8_default_impl
+ .align 5
+aarch64_atomic_fetch_add_8_default_impl:
+ prfm pstl1strm, [x0]
+0: ldaxr x2, [x0]
+ add x8, x2, x1
+ stlxr w9, x8, [x0]
+ cbnz w9, 0b
+ dmb ish
+ mov x0, x2
+ ret
+
+ .globl aarch64_atomic_fetch_add_4_default_impl
+ .align 5
+aarch64_atomic_fetch_add_4_default_impl:
+ prfm pstl1strm, [x0]
+0: ldaxr w2, [x0]
+ add w8, w2, w1
+ stlxr w9, w8, [x0]
+ cbnz w9, 0b
+ dmb ish
+ mov w0, w2
+ ret
+
+ .globl aarch64_atomic_xchg_4_default_impl
+ .align 5
+aarch64_atomic_xchg_4_default_impl:
+ prfm pstl1strm, [x0]
+0: ldaxr w2, [x0]
+ stlxr w8, w1, [x0]
+ cbnz w8, 0b
+ dmb ish
+ mov w0, w2
+ ret
+
+ .globl aarch64_atomic_xchg_8_default_impl
+ .align 5
+aarch64_atomic_xchg_8_default_impl:
+ prfm pstl1strm, [x0]
+0: ldaxr x2, [x0]
+ stlxr w8, x1, [x0]
+ cbnz w8, 0b
+ dmb ish
+ mov x0, x2
+ ret
+
+ .globl aarch64_atomic_cmpxchg_1_default_impl
+ .align 5
+aarch64_atomic_cmpxchg_1_default_impl:
+ dmb ish
+ prfm pstl1strm, [x0]
+0: ldxrb w3, [x0]
+ eor w8, w3, w1
+ tst x8, #0xff
+ b.ne 1f
+ stxrb w8, w2, [x0]
+ cbnz w8, 0b
+1: mov w0, w3
+ dmb ish
+ ret
+
+ .globl aarch64_atomic_cmpxchg_4_default_impl
+ .align 5
+aarch64_atomic_cmpxchg_4_default_impl:
+ dmb ish
+ prfm pstl1strm, [x0]
+0: ldxr w3, [x0]
+ cmp w3, w1
+ b.ne 1f
+ stxr w8, w2, [x0]
+ cbnz w8, 0b
+1: mov w0, w3
+ dmb ish
+ ret
+
+ .globl aarch64_atomic_cmpxchg_8_default_impl
+ .align 5
+aarch64_atomic_cmpxchg_8_default_impl:
+ dmb ish
+ prfm pstl1strm, [x0]
+0: ldxr x3, [x0]
+ cmp x3, x1
+ b.ne 1f
+ stxr w8, x2, [x0]
+ cbnz w8, 0b
+1: mov x0, x3
+ dmb ish
+ ret
+
+ .globl aarch64_atomic_cmpxchg_1_relaxed_default_impl
+ .align 5
+aarch64_atomic_cmpxchg_1_relaxed_default_impl:
+ prfm pstl1strm, [x0]
+0: ldxrb w3, [x0]
+ eor w8, w3, w1
+ tst x8, #0xff
+ b.ne 1f
+ stxrb w8, w2, [x0]
+ cbnz w8, 0b
+1: mov w0, w3
+ ret
+
+ .globl aarch64_atomic_cmpxchg_4_relaxed_default_impl
+ .align 5
+aarch64_atomic_cmpxchg_4_relaxed_default_impl:
+ prfm pstl1strm, [x0]
+0: ldxr w3, [x0]
+ cmp w3, w1
+ b.ne 1f
+ stxr w8, w2, [x0]
+ cbnz w8, 0b
+1: mov w0, w3
+ ret
+
+ .globl aarch64_atomic_cmpxchg_8_relaxed_default_impl
+ .align 5
+aarch64_atomic_cmpxchg_8_relaxed_default_impl:
+ prfm pstl1strm, [x0]
+0: ldxr x3, [x0]
+ cmp x3, x1
+ b.ne 1f
+ stxr w8, x2, [x0]
+ cbnz w8, 0b
+1: mov x0, x3
+ ret
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/os_cpu/linux_aarch64/icache_linux_aarch64.hpp openjdk-lts-11.0.14+9/src/hotspot/os_cpu/linux_aarch64/icache_linux_aarch64.hpp
--- openjdk-lts-11.0.11+9/src/hotspot/os_cpu/linux_aarch64/icache_linux_aarch64.hpp 1970-01-01 00:00:00.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/os_cpu/linux_aarch64/icache_linux_aarch64.hpp 2022-01-13 21:56:25.000000000 +0000
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 1999, 2020, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2014, Red Hat Inc. All rights reserved.
+ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+ *
+ * This code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 only, as
+ * published by the Free Software Foundation.
+ *
+ * This code is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * version 2 for more details (a copy is included in the LICENSE file that
+ * accompanied this code).
+ *
+ * You should have received a copy of the GNU General Public License version
+ * 2 along with this work; if not, write to the Free Software Foundation,
+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
+ * or visit www.oracle.com if you need additional information or have any
+ * questions.
+ *
+ */
+
+#ifndef OS_CPU_LINUX_AARCH64_ICACHE_AARCH64_HPP
+#define OS_CPU_LINUX_AARCH64_ICACHE_AARCH64_HPP
+
+// Interface for updating the instruction cache. Whenever the VM
+// modifies code, part of the processor instruction cache potentially
+// has to be flushed.
+
+class ICache : public AbstractICache {
+ public:
+ static void initialize();
+ static void invalidate_word(address addr) {
+ __builtin___clear_cache((char *)addr, (char *)(addr + 4));
+ }
+ static void invalidate_range(address start, int nbytes) {
+ __builtin___clear_cache((char *)start, (char *)(start + nbytes));
+ }
+};
+
+#endif // OS_CPU_LINUX_AARCH64_ICACHE_AARCH64_HPP
\ No newline at end of file
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/os_cpu/linux_aarch64/orderAccess_linux_aarch64.hpp openjdk-lts-11.0.14+9/src/hotspot/os_cpu/linux_aarch64/orderAccess_linux_aarch64.hpp
--- openjdk-lts-11.0.11+9/src/hotspot/os_cpu/linux_aarch64/orderAccess_linux_aarch64.hpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/os_cpu/linux_aarch64/orderAccess_linux_aarch64.hpp 2022-01-13 21:56:25.000000000 +0000
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2003, 2018, Oracle and/or its affiliates. All rights reserved.
- * Copyright (c) 2014, Red Hat Inc. All rights reserved.
+ * Copyright (c) 2014, 2019, Red Hat Inc. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@@ -28,7 +28,7 @@
// Included in orderAccess.hpp header file.
-#include "vm_version_aarch64.hpp"
+#include "runtime/vm_version.hpp"
// Implementation of class OrderAccess.
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/os_cpu/linux_aarch64/os_linux_aarch64.cpp openjdk-lts-11.0.14+9/src/hotspot/os_cpu/linux_aarch64/os_linux_aarch64.cpp
--- openjdk-lts-11.0.11+9/src/hotspot/os_cpu/linux_aarch64/os_linux_aarch64.cpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/os_cpu/linux_aarch64/os_linux_aarch64.cpp 2022-01-13 21:56:25.000000000 +0000
@@ -261,6 +261,16 @@
}
}
}
+
+ // Handle SafeFetch faults:
+ if (uc != NULL) {
+ address const pc = (address) os::Linux::ucontext_get_pc(uc);
+ if (pc && StubRoutines::is_safefetch_fault(pc)) {
+ os::Linux::ucontext_set_pc(uc, StubRoutines::continuation_for_safefetch_fault(pc));
+ return 1;
+ }
+ }
+
/*
NOTE: does not seem to work on linux.
if (info == NULL || info->si_code <= 0 || info->si_code == SI_NOINFO) {
@@ -279,11 +289,6 @@
if (info != NULL && uc != NULL && thread != NULL) {
pc = (address) os::Linux::ucontext_get_pc(uc);
- if (StubRoutines::is_safefetch_fault(pc)) {
- os::Linux::ucontext_set_pc(uc, StubRoutines::continuation_for_safefetch_fault(pc));
- return 1;
- }
-
// Handle ALL stack overflow variations here
if (sig == SIGSEGV) {
address addr = (address) info->si_addr;
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/os_cpu/linux_aarch64/pauth_linux_aarch64.inline.hpp openjdk-lts-11.0.14+9/src/hotspot/os_cpu/linux_aarch64/pauth_linux_aarch64.inline.hpp
--- openjdk-lts-11.0.11+9/src/hotspot/os_cpu/linux_aarch64/pauth_linux_aarch64.inline.hpp 1970-01-01 00:00:00.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/os_cpu/linux_aarch64/pauth_linux_aarch64.inline.hpp 2022-01-13 21:56:25.000000000 +0000
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2021, Arm Limited. All rights reserved.
+ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+ *
+ * This code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 only, as
+ * published by the Free Software Foundation.
+ *
+ * This code is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * version 2 for more details (a copy is included in the LICENSE file that
+ * accompanied this code).
+ *
+ * You should have received a copy of the GNU General Public License version
+ * 2 along with this work; if not, write to the Free Software Foundation,
+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
+ * or visit www.oracle.com if you need additional information or have any
+ * questions.
+ *
+ */
+
+#ifndef OS_CPU_LINUX_AARCH64_PAUTH_LINUX_AARCH64_INLINE_HPP
+#define OS_CPU_LINUX_AARCH64_PAUTH_LINUX_AARCH64_INLINE_HPP
+
+// Only the PAC instructions in the NOP space can be used. This ensures the
+// binaries work on systems without PAC. Write these instructions using their
+// alternate "hint" instructions to ensure older compilers can still be used.
+
+#define XPACLRI "hint #0x7;"
+
+inline address pauth_strip_pointer(address ptr) {
+ register address result __asm__("x30") = ptr;
+ asm (XPACLRI : "+r"(result));
+ return result;
+}
+
+#undef XPACLRI
+
+#endif // OS_CPU_LINUX_AARCH64_PAUTH_LINUX_AARCH64_INLINE_HPP
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/os_cpu/linux_aarch64/vm_version_linux_aarch64.cpp openjdk-lts-11.0.14+9/src/hotspot/os_cpu/linux_aarch64/vm_version_linux_aarch64.cpp
--- openjdk-lts-11.0.11+9/src/hotspot/os_cpu/linux_aarch64/vm_version_linux_aarch64.cpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/os_cpu/linux_aarch64/vm_version_linux_aarch64.cpp 2022-01-13 21:56:25.000000000 +0000
@@ -1,6 +1,6 @@
/*
- * Copyright (c) 2006, 2010, Oracle and/or its affiliates. All rights reserved.
- * Copyright (c) 2014, Red Hat Inc. All rights reserved.
+ * Copyright (c) 2006, 2019, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2014, 2019, Red Hat Inc. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@@ -25,5 +25,93 @@
#include "precompiled.hpp"
#include "runtime/os.hpp"
-#include "vm_version_aarch64.hpp"
+#include "runtime/vm_version.hpp"
+#include
+#include
+#include
+
+#ifndef HWCAP_AES
+#define HWCAP_AES (1<<3)
+#endif
+
+#ifndef HWCAP_PMULL
+#define HWCAP_PMULL (1<<4)
+#endif
+
+#ifndef HWCAP_SHA1
+#define HWCAP_SHA1 (1<<5)
+#endif
+
+#ifndef HWCAP_SHA2
+#define HWCAP_SHA2 (1<<6)
+#endif
+
+#ifndef HWCAP_CRC32
+#define HWCAP_CRC32 (1<<7)
+#endif
+
+#ifndef HWCAP_ATOMICS
+#define HWCAP_ATOMICS (1<<8)
+#endif
+
+void VM_Version::get_os_cpu_info() {
+
+ uint64_t auxv = getauxval(AT_HWCAP);
+
+ STATIC_ASSERT(CPU_FP == HWCAP_FP);
+ STATIC_ASSERT(CPU_ASIMD == HWCAP_ASIMD);
+ STATIC_ASSERT(CPU_EVTSTRM == HWCAP_EVTSTRM);
+ STATIC_ASSERT(CPU_AES == HWCAP_AES);
+ STATIC_ASSERT(CPU_PMULL == HWCAP_PMULL);
+ STATIC_ASSERT(CPU_SHA1 == HWCAP_SHA1);
+ STATIC_ASSERT(CPU_SHA2 == HWCAP_SHA2);
+ STATIC_ASSERT(CPU_CRC32 == HWCAP_CRC32);
+ STATIC_ASSERT(CPU_LSE == HWCAP_ATOMICS);
+ _features = auxv & (
+ HWCAP_FP |
+ HWCAP_ASIMD |
+ HWCAP_EVTSTRM |
+ HWCAP_AES |
+ HWCAP_PMULL |
+ HWCAP_SHA1 |
+ HWCAP_SHA2 |
+ HWCAP_CRC32 |
+ HWCAP_ATOMICS);
+
+ uint64_t ctr_el0;
+ uint64_t dczid_el0;
+ __asm__ (
+ "mrs %0, CTR_EL0\n"
+ "mrs %1, DCZID_EL0\n"
+ : "=r"(ctr_el0), "=r"(dczid_el0)
+ );
+
+ _icache_line_size = (1 << (ctr_el0 & 0x0f)) * 4;
+ _dcache_line_size = (1 << ((ctr_el0 >> 16) & 0x0f)) * 4;
+
+ if (!(dczid_el0 & 0x10)) {
+ _zva_length = 4 << (dczid_el0 & 0xf);
+ }
+
+ if (FILE *f = fopen("/proc/cpuinfo", "r")) {
+ // need a large buffer as the flags line may include lots of text
+ char buf[1024], *p;
+ while (fgets(buf, sizeof (buf), f) != NULL) {
+ if ((p = strchr(buf, ':')) != NULL) {
+ long v = strtol(p+1, NULL, 0);
+ if (strncmp(buf, "CPU implementer", sizeof "CPU implementer" - 1) == 0) {
+ _cpu = v;
+ } else if (strncmp(buf, "CPU variant", sizeof "CPU variant" - 1) == 0) {
+ _variant = v;
+ } else if (strncmp(buf, "CPU part", sizeof "CPU part" - 1) == 0) {
+ if (_model != v) _model2 = _model;
+ _model = v;
+ } else if (strncmp(buf, "CPU revision", sizeof "CPU revision" - 1) == 0) {
+ _revision = v;
+ }
+ }
+ }
+ fclose(f);
+ }
+}
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/os_cpu/linux_arm/atomic_linux_arm.hpp openjdk-lts-11.0.14+9/src/hotspot/os_cpu/linux_arm/atomic_linux_arm.hpp
--- openjdk-lts-11.0.11+9/src/hotspot/os_cpu/linux_arm/atomic_linux_arm.hpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/os_cpu/linux_arm/atomic_linux_arm.hpp 2022-01-13 21:56:25.000000000 +0000
@@ -26,7 +26,7 @@
#define OS_CPU_LINUX_ARM_VM_ATOMIC_LINUX_ARM_HPP
#include "runtime/os.hpp"
-#include "vm_version_arm.hpp"
+#include "runtime/vm_version.hpp"
// Implementation of class atomic
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/os_cpu/linux_arm/orderAccess_linux_arm.hpp openjdk-lts-11.0.14+9/src/hotspot/os_cpu/linux_arm/orderAccess_linux_arm.hpp
--- openjdk-lts-11.0.11+9/src/hotspot/os_cpu/linux_arm/orderAccess_linux_arm.hpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/os_cpu/linux_arm/orderAccess_linux_arm.hpp 2022-01-13 21:56:25.000000000 +0000
@@ -28,7 +28,7 @@
// Included in orderAccess.hpp header file.
#include "runtime/os.hpp"
-#include "vm_version_arm.hpp"
+#include "runtime/vm_version.hpp"
// Implementation of class OrderAccess.
// - we define the high level barriers below and use the general
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/os_cpu/linux_arm/os_linux_arm.cpp openjdk-lts-11.0.14+9/src/hotspot/os_cpu/linux_arm/os_linux_arm.cpp
--- openjdk-lts-11.0.11+9/src/hotspot/os_cpu/linux_arm/os_linux_arm.cpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/os_cpu/linux_arm/os_linux_arm.cpp 2022-01-13 21:56:25.000000000 +0000
@@ -329,6 +329,15 @@
}
}
+ // Handle SafeFetch faults:
+ if (uc != NULL) {
+ address const pc = (address) os::Linux::ucontext_get_pc(uc);
+ if (pc && StubRoutines::is_safefetch_fault(pc)) {
+ os::Linux::ucontext_set_pc(uc, StubRoutines::continuation_for_safefetch_fault(pc));
+ return 1;
+ }
+ }
+
address stub = NULL;
address pc = NULL;
bool unsafe_access = false;
@@ -340,10 +349,6 @@
if (sig == SIGSEGV) {
address addr = (address) info->si_addr;
- if (StubRoutines::is_safefetch_fault(pc)) {
- os::Linux::ucontext_set_pc(uc, StubRoutines::continuation_for_safefetch_fault(pc));
- return 1;
- }
// check if fault address is within thread stack
if (addr < thread->stack_base() &&
addr >= thread->stack_base() - thread->stack_size()) {
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/os_cpu/linux_arm/vm_version_linux_arm_32.cpp openjdk-lts-11.0.14+9/src/hotspot/os_cpu/linux_arm/vm_version_linux_arm_32.cpp
--- openjdk-lts-11.0.11+9/src/hotspot/os_cpu/linux_arm/vm_version_linux_arm_32.cpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/os_cpu/linux_arm/vm_version_linux_arm_32.cpp 2022-01-13 21:56:25.000000000 +0000
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2008, 2018, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2008, 2019, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@@ -24,7 +24,7 @@
#include "precompiled.hpp"
#include "runtime/os.hpp"
-#include "vm_version_arm.hpp"
+#include "runtime/vm_version.hpp"
# include
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/os_cpu/linux_ppc/thread_linux_ppc.cpp openjdk-lts-11.0.14+9/src/hotspot/os_cpu/linux_ppc/thread_linux_ppc.cpp
--- openjdk-lts-11.0.11+9/src/hotspot/os_cpu/linux_ppc/thread_linux_ppc.cpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/os_cpu/linux_ppc/thread_linux_ppc.cpp 2022-01-13 21:56:25.000000000 +0000
@@ -34,6 +34,8 @@
address pc = _anchor.last_Java_pc();
// Last_Java_pc ist not set, if we come here from compiled code.
+ // Assume spill slot for link register contains a suitable pc.
+ // Should have been filled by method entry code.
if (pc == NULL) {
pc = (address) *(sp + 2);
}
@@ -64,10 +66,21 @@
return false;
}
+ if (ret_frame.fp() == NULL) {
+ // The found frame does not have a valid frame pointer.
+ // Bail out because this will create big trouble later on, either
+ // - when using istate, calculated as (NULL - ijava_state_size) or
+ // - when using fp() directly in safe_for_sender()
+ //
+ // There is no conclusive description (yet) how this could happen, but it does.
+ // For more details on what was observed, see thread_linux_s390.cpp
+ return false;
+ }
+
if (ret_frame.is_interpreted_frame()) {
frame::ijava_state *istate = ret_frame.get_ijava_state();
const Method *m = (const Method*)(istate->method);
- if (m == NULL || !m->is_valid_method()) return false;
+ if (!Method::is_valid_method(m)) return false;
if (!Metaspace::contains((const void*)m->constMethod())) return false;
uint64_t reg_bcp = uc->uc_mcontext.regs->gpr[14/*R14_bcp*/];
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/os_cpu/linux_s390/atomic_linux_s390.hpp openjdk-lts-11.0.14+9/src/hotspot/os_cpu/linux_s390/atomic_linux_s390.hpp
--- openjdk-lts-11.0.11+9/src/hotspot/os_cpu/linux_s390/atomic_linux_s390.hpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/os_cpu/linux_s390/atomic_linux_s390.hpp 2022-01-13 21:56:25.000000000 +0000
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2016, 2018, Oracle and/or its affiliates. All rights reserved.
- * Copyright (c) 2016, 2018 SAP SE. All rights reserved.
+ * Copyright (c) 2016, 2019 SAP SE. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@@ -28,7 +28,7 @@
#include "runtime/atomic.hpp"
#include "runtime/os.hpp"
-#include "vm_version_s390.hpp"
+#include "runtime/vm_version.hpp"
// Note that the compare-and-swap instructions on System z perform
// a serialization function before the storage operand is fetched
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/os_cpu/linux_s390/orderAccess_linux_s390.hpp openjdk-lts-11.0.14+9/src/hotspot/os_cpu/linux_s390/orderAccess_linux_s390.hpp
--- openjdk-lts-11.0.11+9/src/hotspot/os_cpu/linux_s390/orderAccess_linux_s390.hpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/os_cpu/linux_s390/orderAccess_linux_s390.hpp 2022-01-13 21:56:25.000000000 +0000
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2016, 2018, Oracle and/or its affiliates. All rights reserved.
- * Copyright (c) 2016 SAP SE. All rights reserved.
+ * Copyright (c) 2016, 2019 SAP SE. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@@ -28,7 +28,7 @@
// Included in orderAccess.hpp header file.
-#include "vm_version_s390.hpp"
+#include "runtime/vm_version.hpp"
// Implementation of class OrderAccess.
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/os_cpu/linux_s390/thread_linux_s390.cpp openjdk-lts-11.0.14+9/src/hotspot/os_cpu/linux_s390/thread_linux_s390.cpp
--- openjdk-lts-11.0.11+9/src/hotspot/os_cpu/linux_s390/thread_linux_s390.cpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/os_cpu/linux_s390/thread_linux_s390.cpp 2022-01-13 21:56:25.000000000 +0000
@@ -34,6 +34,8 @@
address pc = _anchor.last_Java_pc();
// Last_Java_pc ist not set if we come here from compiled code.
+ // Assume spill slot for Z_R14 (return register) contains a suitable pc.
+ // Should have been filled by method entry code.
if (pc == NULL) {
pc = (address) *(sp + 14);
}
@@ -51,6 +53,9 @@
return true;
}
+ // At this point, we don't have a last_Java_frame, so
+ // we try to glean some information out of the ucontext
+ // if we were running Java code when SIGPROF came in.
if (isInJava) {
ucontext_t* uc = (ucontext_t*) ucontext;
frame ret_frame((intptr_t*)uc->uc_mcontext.gregs[15/*Z_SP*/],
@@ -61,13 +66,45 @@
return false;
}
+ if (ret_frame.fp() == NULL) {
+ // The found frame does not have a valid frame pointer.
+ // Bail out because this will create big trouble later on, either
+ // - when using istate, calculated as (NULL - z_ijava_state_size (= 0x70 (dbg) or 0x68 (rel)) or
+ // - when using fp() directly in safe_for_sender()
+ //
+ // There is no conclusive description (yet) how this could happen, but it does:
+ //
+ // We observed a SIGSEGV with the following stack trace (openjdk.jdk11u-dev, 2021-07-07, linuxs390x fastdebug)
+ // V [libjvm.so+0x12c8f12] JavaThread::pd_get_top_frame_for_profiling(frame*, void*, bool)+0x142
+ // V [libjvm.so+0xb1020c] JfrGetCallTrace::get_topframe(void*, frame&)+0x3c
+ // V [libjvm.so+0xba0b08] OSThreadSampler::protected_task(os::SuspendedThreadTaskContext const&)+0x98
+ // V [libjvm.so+0xff33c4] os::SuspendedThreadTask::internal_do_task()+0x14c
+ // V [libjvm.so+0xfe3c9c] os::SuspendedThreadTask::run()+0x24
+ // V [libjvm.so+0xba0c66] JfrThreadSampleClosure::sample_thread_in_java(JavaThread*, JfrStackFrame*, unsigned int)+0x66
+ // V [libjvm.so+0xba1718] JfrThreadSampleClosure::do_sample_thread(JavaThread*, JfrStackFrame*, unsigned int, JfrSampleType)+0x278
+ // V [libjvm.so+0xba4f54] JfrThreadSampler::task_stacktrace(JfrSampleType, JavaThread**) [clone .constprop.62]+0x284
+ // V [libjvm.so+0xba5e54] JfrThreadSampler::run()+0x2ec
+ // V [libjvm.so+0x12adc9c] Thread::call_run()+0x9c
+ // V [libjvm.so+0xff5ab0] thread_native_entry(Thread*)+0x128
+ // siginfo: si_signo: 11 (SIGSEGV), si_code: 1 (SEGV_MAPERR), si_addr: 0xfffffffffffff000
+ // failing instruction: e320 6008 0004 LG r2,8(r0,r6)
+ // contents of r6: 0xffffffffffffff90
+ //
+ // Here is the sequence of what happens:
+ // - ret_frame is constructed with _fp == NULL (for whatever reason)
+ // - ijava_state_unchecked() calculates it's result as
+ // istate = fp() - z_ijava_state_size() = NULL - 0x68 DEBUG_ONLY(-8)
+ // - istate->method dereferences memory at offset 8 from istate
+ return false;
+ }
+
if (ret_frame.is_interpreted_frame()) {
frame::z_ijava_state* istate = ret_frame.ijava_state_unchecked();
if (stack_base() >= (address)istate && (address)istate > stack_end()) {
return false;
}
const Method *m = (const Method*)(istate->method);
- if (m == NULL || !m->is_valid_method()) return false;
+ if (!Method::is_valid_method(m)) return false;
if (!Metaspace::contains((const void*)m->constMethod())) return false;
uint64_t reg_bcp = uc->uc_mcontext.gregs[13/*Z_BCP*/];
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/os_cpu/linux_sparc/vm_version_linux_sparc.cpp openjdk-lts-11.0.14+9/src/hotspot/os_cpu/linux_sparc/vm_version_linux_sparc.cpp
--- openjdk-lts-11.0.11+9/src/hotspot/os_cpu/linux_sparc/vm_version_linux_sparc.cpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/os_cpu/linux_sparc/vm_version_linux_sparc.cpp 2022-01-13 21:56:25.000000000 +0000
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2006, 2018, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2006, 2019, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@@ -25,7 +25,7 @@
#include "logging/log.hpp"
#include "precompiled.hpp"
#include "runtime/os.hpp"
-#include "vm_version_sparc.hpp"
+#include "runtime/vm_version.hpp"
#define CPUINFO_LINE_SIZE 1024
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/os_cpu/linux_x86/globals_linux_x86.hpp openjdk-lts-11.0.14+9/src/hotspot/os_cpu/linux_x86/globals_linux_x86.hpp
--- openjdk-lts-11.0.11+9/src/hotspot/os_cpu/linux_x86/globals_linux_x86.hpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/os_cpu/linux_x86/globals_linux_x86.hpp 2022-01-13 21:56:25.000000000 +0000
@@ -34,7 +34,13 @@
define_pd_global(intx, ThreadStackSize, 1024); // 0 => use system default
define_pd_global(intx, VMThreadStackSize, 1024);
#else
-define_pd_global(intx, CompilerThreadStackSize, 512);
+// Some tests in debug VM mode run out of compile thread stack.
+// Observed on some x86_32 VarHandles tests during escape analysis.
+#ifdef ASSERT
+define_pd_global(intx, CompilerThreadStackSize, 768);
+#else
+define_pd_global(intx, CompilerThreadStackSize, 512);
+#endif
// ThreadStackSize 320 allows a couple of test cases to run while
// keeping the number of threads that can be created high. System
// default ThreadStackSize appears to be 512 which is too big.
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/os_cpu/linux_x86/os_linux_x86.cpp openjdk-lts-11.0.14+9/src/hotspot/os_cpu/linux_x86/os_linux_x86.cpp
--- openjdk-lts-11.0.11+9/src/hotspot/os_cpu/linux_x86/os_linux_x86.cpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/os_cpu/linux_x86/os_linux_x86.cpp 2022-01-13 21:56:25.000000000 +0000
@@ -321,6 +321,16 @@
}
}
}
+
+ // Handle SafeFetch faults:
+ if (uc != NULL) {
+ address const pc = (address) os::Linux::ucontext_get_pc(uc);
+ if (pc && StubRoutines::is_safefetch_fault(pc)) {
+ os::Linux::ucontext_set_pc(uc, StubRoutines::continuation_for_safefetch_fault(pc));
+ return 1;
+ }
+ }
+
/*
NOTE: does not seem to work on linux.
if (info == NULL || info->si_code <= 0 || info->si_code == SI_NOINFO) {
@@ -339,11 +349,6 @@
if (info != NULL && uc != NULL && thread != NULL) {
pc = (address) os::Linux::ucontext_get_pc(uc);
- if (StubRoutines::is_safefetch_fault(pc)) {
- os::Linux::ucontext_set_pc(uc, StubRoutines::continuation_for_safefetch_fault(pc));
- return 1;
- }
-
#ifndef AMD64
// Halt if SI_KERNEL before more crashes get misdiagnosed as Java bugs
// This can happen in any running code (currently more frequently in
@@ -458,7 +463,7 @@
int op = pc[0];
if (op == 0xDB) {
// FIST
- // TODO: The encoding of D2I in i486.ad can cause an exception
+ // TODO: The encoding of D2I in x86_32.ad can cause an exception
// prior to the fist instruction if there was an invalid operation
// pending. We want to dismiss that exception. From the win_32
// side it also seems that if it really was the fist causing
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/os_cpu/linux_x86/vm_version_linux_x86.cpp openjdk-lts-11.0.14+9/src/hotspot/os_cpu/linux_x86/vm_version_linux_x86.cpp
--- openjdk-lts-11.0.11+9/src/hotspot/os_cpu/linux_x86/vm_version_linux_x86.cpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/os_cpu/linux_x86/vm_version_linux_x86.cpp 2022-01-13 21:56:25.000000000 +0000
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2006, 2010, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2006, 2019, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@@ -24,5 +24,5 @@
#include "precompiled.hpp"
#include "runtime/os.hpp"
-#include "vm_version_x86.hpp"
+#include "runtime/vm_version.hpp"
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/os_cpu/linux_zero/os_linux_zero.cpp openjdk-lts-11.0.14+9/src/hotspot/os_cpu/linux_zero/os_linux_zero.cpp
--- openjdk-lts-11.0.11+9/src/hotspot/os_cpu/linux_zero/os_linux_zero.cpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/os_cpu/linux_zero/os_linux_zero.cpp 2022-01-13 21:56:25.000000000 +0000
@@ -317,6 +317,20 @@
}
static void current_stack_region(address *bottom, size_t *size) {
+ if (os::is_primordial_thread()) {
+ // primordial thread needs special handling because pthread_getattr_np()
+ // may return bogus value.
+ address stack_bottom = os::Linux::initial_thread_stack_bottom();
+ size_t stack_bytes = os::Linux::initial_thread_stack_size();
+
+ assert(os::current_stack_pointer() >= stack_bottom, "should do");
+ assert(os::current_stack_pointer() < stack_bottom + stack_bytes, "should do");
+
+ *bottom = stack_bottom;
+ *size = stack_bytes;
+ return;
+ }
+
pthread_attr_t attr;
int res = pthread_getattr_np(pthread_self(), &attr);
if (res != 0) {
@@ -365,18 +379,6 @@
pthread_attr_destroy(&attr);
- // The initial thread has a growable stack, and the size reported
- // by pthread_attr_getstack is the maximum size it could possibly
- // be given what currently mapped. This can be huge, so we cap it.
- if (os::is_primordial_thread()) {
- stack_bytes = stack_top - stack_bottom;
-
- if (stack_bytes > JavaThread::stack_size_at_create())
- stack_bytes = JavaThread::stack_size_at_create();
-
- stack_bottom = stack_top - stack_bytes;
- }
-
assert(os::current_stack_pointer() >= stack_bottom, "should do");
assert(os::current_stack_pointer() < stack_top, "should do");
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/os_cpu/linux_zero/vm_version_linux_zero.cpp openjdk-lts-11.0.14+9/src/hotspot/os_cpu/linux_zero/vm_version_linux_zero.cpp
--- openjdk-lts-11.0.11+9/src/hotspot/os_cpu/linux_zero/vm_version_linux_zero.cpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/os_cpu/linux_zero/vm_version_linux_zero.cpp 2022-01-13 21:56:25.000000000 +0000
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 1997, 2019, Oracle and/or its affiliates. All rights reserved.
* Copyright 2009 Red Hat, Inc.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
@@ -25,6 +25,6 @@
#include "precompiled.hpp"
#include "runtime/os.hpp"
-#include "vm_version_zero.hpp"
+#include "runtime/vm_version.hpp"
// This file is intentionally empty
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/os_cpu/solaris_sparc/os_solaris_sparc.cpp openjdk-lts-11.0.14+9/src/hotspot/os_cpu/solaris_sparc/os_solaris_sparc.cpp
--- openjdk-lts-11.0.11+9/src/hotspot/os_cpu/solaris_sparc/os_solaris_sparc.cpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/os_cpu/solaris_sparc/os_solaris_sparc.cpp 2022-01-13 21:56:25.000000000 +0000
@@ -373,6 +373,15 @@
assert(sig == info->si_signo, "bad siginfo");
}
+ // Handle SafeFetch faults:
+ if (uc != NULL) {
+ address const pc = (address) uc->uc_mcontext.gregs[REG_PC];
+ if (pc && StubRoutines::is_safefetch_fault(pc)) {
+ os::Solaris::ucontext_set_pc(uc, StubRoutines::continuation_for_safefetch_fault(pc));
+ return 1;
+ }
+ }
+
// decide if this trap can be handled by a stub
address stub = NULL;
@@ -385,12 +394,6 @@
pc = (address) uc->uc_mcontext.gregs[REG_PC];
npc = (address) uc->uc_mcontext.gregs[REG_nPC];
- // SafeFetch() support
- if (StubRoutines::is_safefetch_fault(pc)) {
- os::Solaris::ucontext_set_pc(uc, StubRoutines::continuation_for_safefetch_fault(pc));
- return 1;
- }
-
// Handle ALL stack overflow variations here
if (sig == SIGSEGV && info->si_code == SEGV_ACCERR) {
address addr = (address) info->si_addr;
diff -Nru openjdk-lts-11.0.11+9/src/hotspot/os_cpu/solaris_sparc/vm_version_solaris_sparc.cpp openjdk-lts-11.0.14+9/src/hotspot/os_cpu/solaris_sparc/vm_version_solaris_sparc.cpp
--- openjdk-lts-11.0.11+9/src/hotspot/os_cpu/solaris_sparc/vm_version_solaris_sparc.cpp 2021-01-21 14:52:08.000000000 +0000
+++ openjdk-lts-11.0.14+9/src/hotspot/os_cpu/solaris_sparc/vm_version_solaris_sparc.cpp 2022-01-13 21:56:25.000000000 +0000
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2006, 2016, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2006, 2019, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@@ -27,7 +27,7 @@
#include "memory/allocation.hpp"
#include "memory/allocation.inline.hpp"
#include "runtime/os.hpp"
-#include "vm_version_sparc.hpp"
+#include "runtime/vm_version.hpp"
#include
#include