diff -Nru libdrm-2.4.100+git1912051032.02e1d0f~b~padoka0/debian/changelog libdrm-2.4.100+git2001081023.9ebfac1~b~padoka0/debian/changelog --- libdrm-2.4.100+git1912051032.02e1d0f~b~padoka0/debian/changelog 2019-12-05 10:32:21.000000000 +0000 +++ libdrm-2.4.100+git2001081023.9ebfac1~b~padoka0/debian/changelog 2020-01-08 10:23:24.000000000 +0000 @@ -1,8 +1,8 @@ -libdrm (2.4.100+git1912051032.02e1d0f~b~padoka0) bionic; urgency=medium +libdrm (2.4.100+git2001081023.9ebfac1~b~padoka0) bionic; urgency=medium - * git up to 02e1d0ff8b30b85b3223ecf1e38fae3b493cb495 + * git up to 9ebfac15a5c443e847b432765e3b3aa35f74c6f1 - -- Paulo Dias Thu, 05 Dec 2019 10:32:21 +0000 + -- Paulo Dias Wed, 08 Jan 2020 10:23:24 +0000 libdrm (2.4.99-1ubuntu1) eoan; urgency=medium diff -Nru libdrm-2.4.100+git1912051032.02e1d0f~b~padoka0/.gitlab-ci.yml libdrm-2.4.100+git2001081023.9ebfac1~b~padoka0/.gitlab-ci.yml --- libdrm-2.4.100+git1912051032.02e1d0f~b~padoka0/.gitlab-ci.yml 2019-12-05 10:31:35.000000000 +0000 +++ libdrm-2.4.100+git2001081023.9ebfac1~b~padoka0/.gitlab-ci.yml 2020-01-08 10:20:05.000000000 +0000 @@ -56,7 +56,7 @@ variables: GIT_DEPTH: 10 script: - - meson _build + - meson build -D amdgpu=true -D cairo-tests=true -D etnaviv=true @@ -75,13 +75,13 @@ -D vc4=true -D vmwgfx=true ${CROSS+--cross /cross_file-$CROSS.txt} - - ninja -C _build - - ninja -C _build test - - DESTDIR=$PWD/install ninja -C _build install + - ninja -C build + - ninja -C build test + - DESTDIR=$PWD/install ninja -C build install artifacts: when: on_failure paths: - - _build/meson-logs/* + - build/meson-logs/* meson-x86_64: extends: diff -Nru libdrm-2.4.100+git1912051032.02e1d0f~b~padoka0/intel/i915_pciids.h libdrm-2.4.100+git2001081023.9ebfac1~b~padoka0/intel/i915_pciids.h --- libdrm-2.4.100+git1912051032.02e1d0f~b~padoka0/intel/i915_pciids.h 2019-10-27 18:27:49.000000000 +0000 +++ libdrm-2.4.100+git2001081023.9ebfac1~b~padoka0/intel/i915_pciids.h 2020-01-08 10:20:05.000000000 +0000 @@ -446,23 +446,18 @@ /* CML GT1 */ #define INTEL_CML_GT1_IDS(info) \ - INTEL_VGA_DEVICE(0x9B21, info), \ - INTEL_VGA_DEVICE(0x9BAA, info), \ - INTEL_VGA_DEVICE(0x9BAB, info), \ - INTEL_VGA_DEVICE(0x9BAC, info), \ - INTEL_VGA_DEVICE(0x9BA0, info), \ INTEL_VGA_DEVICE(0x9BA5, info), \ INTEL_VGA_DEVICE(0x9BA8, info), \ INTEL_VGA_DEVICE(0x9BA4, info), \ INTEL_VGA_DEVICE(0x9BA2, info) +#define INTEL_CML_U_GT1_IDS(info) \ + INTEL_VGA_DEVICE(0x9B21, info), \ + INTEL_VGA_DEVICE(0x9BAA, info), \ + INTEL_VGA_DEVICE(0x9BAC, info) + /* CML GT2 */ #define INTEL_CML_GT2_IDS(info) \ - INTEL_VGA_DEVICE(0x9B41, info), \ - INTEL_VGA_DEVICE(0x9BCA, info), \ - INTEL_VGA_DEVICE(0x9BCB, info), \ - INTEL_VGA_DEVICE(0x9BCC, info), \ - INTEL_VGA_DEVICE(0x9BC0, info), \ INTEL_VGA_DEVICE(0x9BC5, info), \ INTEL_VGA_DEVICE(0x9BC8, info), \ INTEL_VGA_DEVICE(0x9BC4, info), \ @@ -471,6 +466,11 @@ INTEL_VGA_DEVICE(0x9BE6, info), \ INTEL_VGA_DEVICE(0x9BF6, info) +#define INTEL_CML_U_GT2_IDS(info) \ + INTEL_VGA_DEVICE(0x9B41, info), \ + INTEL_VGA_DEVICE(0x9BCA, info), \ + INTEL_VGA_DEVICE(0x9BCC, info) + #define INTEL_KBL_IDS(info) \ INTEL_KBL_GT1_IDS(info), \ INTEL_KBL_GT2_IDS(info), \ @@ -536,7 +536,9 @@ INTEL_WHL_U_GT3_IDS(info), \ INTEL_AML_CFL_GT2_IDS(info), \ INTEL_CML_GT1_IDS(info), \ - INTEL_CML_GT2_IDS(info) + INTEL_CML_GT2_IDS(info), \ + INTEL_CML_U_GT1_IDS(info), \ + INTEL_CML_U_GT2_IDS(info) /* CNL */ #define INTEL_CNL_PORT_F_IDS(info) \ @@ -579,12 +581,15 @@ INTEL_VGA_DEVICE(0x8A51, info), \ INTEL_VGA_DEVICE(0x8A5D, info) -/* EHL */ +/* EHL/JSL */ #define INTEL_EHL_IDS(info) \ INTEL_VGA_DEVICE(0x4500, info), \ INTEL_VGA_DEVICE(0x4571, info), \ INTEL_VGA_DEVICE(0x4551, info), \ - INTEL_VGA_DEVICE(0x4541, info) + INTEL_VGA_DEVICE(0x4541, info), \ + INTEL_VGA_DEVICE(0x4E71, info), \ + INTEL_VGA_DEVICE(0x4E61, info), \ + INTEL_VGA_DEVICE(0x4E51, info) /* TGL */ #define INTEL_TGL_12_IDS(info) \ diff -Nru libdrm-2.4.100+git1912051032.02e1d0f~b~padoka0/meson.build libdrm-2.4.100+git2001081023.9ebfac1~b~padoka0/meson.build --- libdrm-2.4.100+git1912051032.02e1d0f~b~padoka0/meson.build 2019-12-05 10:31:35.000000000 +0000 +++ libdrm-2.4.100+git2001081023.9ebfac1~b~padoka0/meson.build 2020-01-08 10:20:05.000000000 +0000 @@ -52,9 +52,10 @@ lib_atomics = false dep_atomic_ops = dependency('atomic_ops', required : false) -if cc.compiles(''' +if cc.links(''' int atomic_add(int *i) { return __sync_add_and_fetch (i, 1); } int atomic_cmpxchg(int *i, int j, int k) { return __sync_val_compare_and_swap (i, j, k); } + int main() { } ''', name : 'Intel Atomics') intel_atomics = true @@ -284,7 +285,7 @@ configuration : config, output : 'config.h', ) -add_project_arguments('-include', 'config.h', language : 'c') +add_project_arguments('-include', '@0@'.format(config_file), language : 'c') inc_root = include_directories('.') inc_drm = include_directories('include/drm') diff -Nru libdrm-2.4.100+git1912051032.02e1d0f~b~padoka0/tests/amdgpu/amdgpu_test.c libdrm-2.4.100+git2001081023.9ebfac1~b~padoka0/tests/amdgpu/amdgpu_test.c --- libdrm-2.4.100+git1912051032.02e1d0f~b~padoka0/tests/amdgpu/amdgpu_test.c 2019-10-07 12:46:30.000000000 +0000 +++ libdrm-2.4.100+git2001081023.9ebfac1~b~padoka0/tests/amdgpu/amdgpu_test.c 2020-01-08 10:20:05.000000000 +0000 @@ -202,44 +202,42 @@ CU_pSuite pSuite = NULL; CU_pTest pTest = NULL; - printf("Suites\n"); + printf("%5s: %2s: %8s: %s\n", "What", "ID", "Status", "Name"); for (iSuite = 0; suites[iSuite].pName != NULL; iSuite++) { pSuite = CU_get_suite_by_index((unsigned int) iSuite + 1, - CU_get_registry()); + CU_get_registry()); if (!pSuite) { fprintf(stderr, "Invalid suite id : %d\n", iSuite + 1); continue; } - printf("Suite id = %d: Name '%s status: %s'\n", - iSuite + 1, suites[iSuite].pName, - pSuite->fActive ? "ENABLED" : "DISABLED"); - + printf("Suite: %2d: %8s: %s\n", + iSuite + 1, + pSuite->fActive ? "ENABLED" : "DISABLED", + suites[iSuite].pName); + if (!pSuite->fActive) + continue; for (iTest = 0; suites[iSuite].pTests[iTest].pName != NULL; - iTest++) { - + iTest++) { pTest = CU_get_test_by_index((unsigned int) iTest + 1, - pSuite); - + pSuite); if (!pTest) { fprintf(stderr, "Invalid test id : %d\n", iTest + 1); continue; } - - printf("Test id %d: Name: '%s status: %s'\n", iTest + 1, - suites[iSuite].pTests[iTest].pName, - pSuite->fActive && pTest->fActive ? - "ENABLED" : "DISABLED"); + printf(" Test: %2d: %8s: %s\n", + iTest + 1, + pSuite->fActive && pTest->fActive ? "ENABLED" : "DISABLED", + suites[iSuite].pTests[iTest].pName); } } } - /** Help string for command line parameters */ static const char usage[] = "Usage: %s [-hlpr] [<-s > [-t ] [-f]] " @@ -452,6 +450,41 @@ "sdma ring block test (set amdgpu.lockup_timeout=50)", CU_FALSE)) fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg()); + /* This test was ran on GFX9 only */ + //if (family_id < AMDGPU_FAMILY_AI || family_id > AMDGPU_FAMILY_RV) + if (amdgpu_set_test_active(DEADLOCK_TESTS_STR, + "gfx ring bad dispatch test (set amdgpu.lockup_timeout=50)", CU_FALSE)) + fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg()); + + /* This test was ran on GFX9 only */ + //if (family_id < AMDGPU_FAMILY_AI || family_id > AMDGPU_FAMILY_RV) + if (amdgpu_set_test_active(DEADLOCK_TESTS_STR, + "compute ring bad dispatch test (set amdgpu.lockup_timeout=50,50)", CU_FALSE)) + fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg()); + + /* This test was ran on GFX9 only */ + //if (family_id < AMDGPU_FAMILY_AI || family_id > AMDGPU_FAMILY_RV) + if (amdgpu_set_test_active(DEADLOCK_TESTS_STR, + "gfx ring bad slow dispatch test (set amdgpu.lockup_timeout=50)", CU_FALSE)) + fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg()); + + /* This test was ran on GFX9 only */ + //if (family_id < AMDGPU_FAMILY_AI || family_id > AMDGPU_FAMILY_RV) + if (amdgpu_set_test_active(DEADLOCK_TESTS_STR, + "compute ring bad slow dispatch test (set amdgpu.lockup_timeout=50,50)", CU_FALSE)) + fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg()); + + //if (family_id < AMDGPU_FAMILY_AI || family_id > AMDGPU_FAMILY_RV) + if (amdgpu_set_test_active(DEADLOCK_TESTS_STR, + "gfx ring bad draw test (set amdgpu.lockup_timeout=50)", CU_FALSE)) + fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg()); + + /* This test was ran on GFX9 only */ + //if (family_id < AMDGPU_FAMILY_AI || family_id > AMDGPU_FAMILY_RV) + if (amdgpu_set_test_active(DEADLOCK_TESTS_STR, + "gfx ring slow bad draw test (set amdgpu.lockup_timeout=50)", CU_FALSE)) + fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg()); + if (amdgpu_set_test_active(BO_TESTS_STR, "Metadata", CU_FALSE)) fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg()); diff -Nru libdrm-2.4.100+git1912051032.02e1d0f~b~padoka0/tests/amdgpu/amdgpu_test.h libdrm-2.4.100+git2001081023.9ebfac1~b~padoka0/tests/amdgpu/amdgpu_test.h --- libdrm-2.4.100+git1912051032.02e1d0f~b~padoka0/tests/amdgpu/amdgpu_test.h 2019-05-19 19:43:33.000000000 +0000 +++ libdrm-2.4.100+git2001081023.9ebfac1~b~padoka0/tests/amdgpu/amdgpu_test.h 2020-01-08 10:20:05.000000000 +0000 @@ -236,6 +236,11 @@ */ extern CU_TestInfo syncobj_timeline_tests[]; +void amdgpu_dispatch_hang_helper(amdgpu_device_handle device_handle, uint32_t ip_type); +void amdgpu_dispatch_hang_slow_helper(amdgpu_device_handle device_handle, uint32_t ip_type); +void amdgpu_memcpy_draw_test(amdgpu_device_handle device_handle, uint32_t ring, + int hang); +void amdgpu_memcpy_draw_hang_slow_test(amdgpu_device_handle device_handle, uint32_t ring); /** * Helper functions diff -Nru libdrm-2.4.100+git1912051032.02e1d0f~b~padoka0/tests/amdgpu/basic_tests.c libdrm-2.4.100+git2001081023.9ebfac1~b~padoka0/tests/amdgpu/basic_tests.c --- libdrm-2.4.100+git1912051032.02e1d0f~b~padoka0/tests/amdgpu/basic_tests.c 2019-12-05 10:31:35.000000000 +0000 +++ libdrm-2.4.100+git2001081023.9ebfac1~b~padoka0/tests/amdgpu/basic_tests.c 2020-01-08 10:20:05.000000000 +0000 @@ -306,7 +306,9 @@ enum cs_type { CS_BUFFERCLEAR, - CS_BUFFERCOPY + CS_BUFFERCOPY, + CS_HANG, + CS_HANG_SLOW }; static const uint32_t bufferclear_cs_shader_gfx9[] = { @@ -355,7 +357,9 @@ enum ps_type { PS_CONST, - PS_TEX + PS_TEX, + PS_HANG, + PS_HANG_SLOW }; static const uint32_t ps_const_shader_gfx9[] = { @@ -461,13 +465,67 @@ 0xc0016900, 0x0, 0x0, 0xc0026900, 0x3, 0x2a, 0x0, 0xc0046900, 0xa, 0x0, 0x0, 0x0, 0x200020, 0xc0016900, 0x83, 0xffff, 0xc0026900, 0x8e, 0xf, 0xf, - 0xc0056900, 0x105, 0x0, 0x0, 0x0, 0x0, 0x1a, + 0xc0056900, 0x105, 0x0, 0x0, 0x0, 0x0, 0x12, 0xc0026900, 0x10b, 0x0, 0x0, 0xc0016900, 0x1e0, 0x0, 0xc0036900, 0x200, 0x0, 0x10000, 0xcc0011, 0xc0026900, 0x292, 0x20, 0x60201b8, 0xc0026900, 0x2b0, 0x0, 0x0, 0xc0016900, 0x2f8, 0x0 }; +unsigned int memcpy_ps_hang[] = { + 0xFFFFFFFF, 0xBEFE0A7E, 0xBEFC0304, 0xC0C20100, + 0xC0800300, 0xC8080000, 0xC80C0100, 0xC8090001, + 0xC80D0101, 0xBF8C007F, 0xF0800F00, 0x00010002, + 0xBEFE040C, 0xBF8C0F70, 0xBF800000, 0xBF800000, + 0xF800180F, 0x03020100, 0xBF810000 +}; + +struct amdgpu_test_shader { + uint32_t *shader; + uint32_t header_length; + uint32_t body_length; + uint32_t foot_length; +}; + +unsigned int memcpy_cs_hang_slow_ai_codes[] = { + 0xd1fd0000, 0x04010c08, 0xe00c2000, 0x80000100, + 0xbf8c0f70, 0xe01c2000, 0x80010100, 0xbf810000 +}; + +struct amdgpu_test_shader memcpy_cs_hang_slow_ai = { + memcpy_cs_hang_slow_ai_codes, + 4, + 3, + 1 +}; + +unsigned int memcpy_cs_hang_slow_rv_codes[] = { + 0x8e00860c, 0x32000000, 0xe00c2000, 0x80010100, + 0xbf8c0f70, 0xe01c2000, 0x80020100, 0xbf810000 +}; + +struct amdgpu_test_shader memcpy_cs_hang_slow_rv = { + memcpy_cs_hang_slow_rv_codes, + 4, + 3, + 1 +}; + +unsigned int memcpy_ps_hang_slow_ai_codes[] = { + 0xbefc000c, 0xbe8e017e, 0xbefe077e, 0xd4080000, + 0xd4090001, 0xd40c0100, 0xd40d0101, 0xf0800f00, + 0x00400002, 0xbefe010e, 0xbf8c0f70, 0xbf800000, + 0xbf800000, 0xbf800000, 0xbf800000, 0xc400180f, + 0x03020100, 0xbf810000 +}; + +struct amdgpu_test_shader memcpy_ps_hang_slow_ai = { + memcpy_ps_hang_slow_ai_codes, + 7, + 2, + 9 +}; + int amdgpu_bo_alloc_and_map_raw(amdgpu_device_handle dev, unsigned size, unsigned alignment, unsigned heap, uint64_t alloc_flags, uint64_t mapping_flags, amdgpu_bo_handle *bo, void **cpu, @@ -2065,6 +2123,37 @@ free(ibs_request.dependencies); } +static int amdgpu_dispatch_load_cs_shader_hang_slow(uint32_t *ptr, int family) +{ + struct amdgpu_test_shader *shader; + int i, loop = 0x10000; + + switch (family) { + case AMDGPU_FAMILY_AI: + shader = &memcpy_cs_hang_slow_ai; + break; + case AMDGPU_FAMILY_RV: + shader = &memcpy_cs_hang_slow_rv; + break; + default: + return -1; + break; + } + + memcpy(ptr, shader->shader, shader->header_length * sizeof(uint32_t)); + + for (i = 0; i < loop; i++) + memcpy(ptr + shader->header_length + shader->body_length * i, + shader->shader + shader->header_length, + shader->body_length * sizeof(uint32_t)); + + memcpy(ptr + shader->header_length + shader->body_length * loop, + shader->shader + shader->header_length + shader->body_length, + shader->foot_length * sizeof(uint32_t)); + + return 0; +} + static int amdgpu_dispatch_load_cs_shader(uint8_t *ptr, int cs_type) { @@ -2080,6 +2169,10 @@ shader = buffercopy_cs_shader_gfx9; shader_size = sizeof(buffercopy_cs_shader_gfx9); break; + case CS_HANG: + shader = memcpy_ps_hang; + shader_size = sizeof(memcpy_ps_hang); + break; default: return -1; break; @@ -2300,7 +2393,8 @@ static void amdgpu_memcpy_dispatch_test(amdgpu_device_handle device_handle, uint32_t ip_type, - uint32_t ring) + uint32_t ring, + int hang) { amdgpu_context_handle context_handle; amdgpu_bo_handle bo_src, bo_dst, bo_shader, bo_cmd, resources[4]; @@ -2316,7 +2410,8 @@ int bo_cmd_size = 4096; struct amdgpu_cs_request ibs_request = {0}; struct amdgpu_cs_ib_info ib_info= {0}; - uint32_t expired; + uint32_t expired, hang_state, hangs; + enum cs_type cs_type; amdgpu_bo_list_handle bo_list; struct amdgpu_cs_fence fence_status = {0}; @@ -2337,7 +2432,8 @@ CU_ASSERT_EQUAL(r, 0); memset(ptr_shader, 0, bo_shader_size); - r = amdgpu_dispatch_load_cs_shader(ptr_shader, CS_BUFFERCOPY ); + cs_type = hang ? CS_HANG : CS_BUFFERCOPY; + r = amdgpu_dispatch_load_cs_shader(ptr_shader, cs_type); CU_ASSERT_EQUAL(r, 0); r = amdgpu_bo_alloc_and_map(device_handle, bo_dst_size, 4096, @@ -2423,14 +2519,21 @@ r = amdgpu_cs_query_fence_status(&fence_status, AMDGPU_TIMEOUT_INFINITE, 0, &expired); - CU_ASSERT_EQUAL(r, 0); - CU_ASSERT_EQUAL(expired, true); - /* verify if memcpy test result meets with expected */ - i = 0; - while(i < bo_dst_size) { - CU_ASSERT_EQUAL(ptr_dst[i], ptr_src[i]); - i++; + if (!hang) { + CU_ASSERT_EQUAL(r, 0); + CU_ASSERT_EQUAL(expired, true); + + /* verify if memcpy test result meets with expected */ + i = 0; + while(i < bo_dst_size) { + CU_ASSERT_EQUAL(ptr_dst[i], ptr_src[i]); + i++; + } + } else { + r = amdgpu_cs_query_reset_state(context_handle, &hang_state, &hangs); + CU_ASSERT_EQUAL(r, 0); + CU_ASSERT_EQUAL(hang_state, AMDGPU_CTX_UNKNOWN_RESET); } r = amdgpu_bo_list_destroy(bo_list); @@ -2464,7 +2567,7 @@ for (ring_id = 0; (1 << ring_id) & info.available_rings; ring_id++) { amdgpu_memset_dispatch_test(device_handle, AMDGPU_HW_IP_COMPUTE, ring_id); - amdgpu_memcpy_dispatch_test(device_handle, AMDGPU_HW_IP_COMPUTE, ring_id); + amdgpu_memcpy_dispatch_test(device_handle, AMDGPU_HW_IP_COMPUTE, ring_id, 0); } } @@ -2481,10 +2584,226 @@ for (ring_id = 0; (1 << ring_id) & info.available_rings; ring_id++) { amdgpu_memset_dispatch_test(device_handle, AMDGPU_HW_IP_GFX, ring_id); - amdgpu_memcpy_dispatch_test(device_handle, AMDGPU_HW_IP_GFX, ring_id); + amdgpu_memcpy_dispatch_test(device_handle, AMDGPU_HW_IP_GFX, ring_id, 0); + } +} + +void amdgpu_dispatch_hang_helper(amdgpu_device_handle device_handle, uint32_t ip_type) +{ + int r; + struct drm_amdgpu_info_hw_ip info; + uint32_t ring_id; + + r = amdgpu_query_hw_ip_info(device_handle, ip_type, 0, &info); + CU_ASSERT_EQUAL(r, 0); + if (!info.available_rings) + printf("SKIP ... as there's no ring for ip %d\n", ip_type); + + for (ring_id = 0; (1 << ring_id) & info.available_rings; ring_id++) { + amdgpu_memcpy_dispatch_test(device_handle, ip_type, ring_id, 0); + amdgpu_memcpy_dispatch_test(device_handle, ip_type, ring_id, 1); + amdgpu_memcpy_dispatch_test(device_handle, ip_type, ring_id, 0); } } +static void amdgpu_memcpy_dispatch_hang_slow_test(amdgpu_device_handle device_handle, + uint32_t ip_type, uint32_t ring) +{ + amdgpu_context_handle context_handle; + amdgpu_bo_handle bo_src, bo_dst, bo_shader, bo_cmd, resources[4]; + volatile unsigned char *ptr_dst; + void *ptr_shader; + unsigned char *ptr_src; + uint32_t *ptr_cmd; + uint64_t mc_address_src, mc_address_dst, mc_address_shader, mc_address_cmd; + amdgpu_va_handle va_src, va_dst, va_shader, va_cmd; + int i, r; + int bo_dst_size = 0x4000000; + int bo_shader_size = 0x400000; + int bo_cmd_size = 4096; + struct amdgpu_cs_request ibs_request = {0}; + struct amdgpu_cs_ib_info ib_info= {0}; + uint32_t hang_state, hangs, expired; + struct amdgpu_gpu_info gpu_info = {0}; + amdgpu_bo_list_handle bo_list; + struct amdgpu_cs_fence fence_status = {0}; + + r = amdgpu_query_gpu_info(device_handle, &gpu_info); + CU_ASSERT_EQUAL(r, 0); + + r = amdgpu_cs_ctx_create(device_handle, &context_handle); + CU_ASSERT_EQUAL(r, 0); + + r = amdgpu_bo_alloc_and_map(device_handle, bo_cmd_size, 4096, + AMDGPU_GEM_DOMAIN_GTT, 0, + &bo_cmd, (void **)&ptr_cmd, + &mc_address_cmd, &va_cmd); + CU_ASSERT_EQUAL(r, 0); + memset(ptr_cmd, 0, bo_cmd_size); + + r = amdgpu_bo_alloc_and_map(device_handle, bo_shader_size, 4096, + AMDGPU_GEM_DOMAIN_VRAM, 0, + &bo_shader, &ptr_shader, + &mc_address_shader, &va_shader); + CU_ASSERT_EQUAL(r, 0); + memset(ptr_shader, 0, bo_shader_size); + + r = amdgpu_dispatch_load_cs_shader_hang_slow(ptr_shader, gpu_info.family_id); + CU_ASSERT_EQUAL(r, 0); + + r = amdgpu_bo_alloc_and_map(device_handle, bo_dst_size, 4096, + AMDGPU_GEM_DOMAIN_VRAM, 0, + &bo_src, (void **)&ptr_src, + &mc_address_src, &va_src); + CU_ASSERT_EQUAL(r, 0); + + r = amdgpu_bo_alloc_and_map(device_handle, bo_dst_size, 4096, + AMDGPU_GEM_DOMAIN_VRAM, 0, + &bo_dst, (void **)&ptr_dst, + &mc_address_dst, &va_dst); + CU_ASSERT_EQUAL(r, 0); + + memset(ptr_src, 0x55, bo_dst_size); + + i = 0; + i += amdgpu_dispatch_init(ptr_cmd + i, ip_type); + + /* Issue commands to set cu mask used in current dispatch */ + i += amdgpu_dispatch_write_cumask(ptr_cmd + i); + + /* Writes shader state to HW */ + i += amdgpu_dispatch_write2hw(ptr_cmd + i, mc_address_shader); + + /* Write constant data */ + /* Writes the texture resource constants data to the SGPRs */ + ptr_cmd[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 4); + ptr_cmd[i++] = 0x240; + ptr_cmd[i++] = mc_address_src; + ptr_cmd[i++] = (mc_address_src >> 32) | 0x100000; + ptr_cmd[i++] = 0x400000; + ptr_cmd[i++] = 0x74fac; + + /* Writes the UAV constant data to the SGPRs. */ + ptr_cmd[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 4); + ptr_cmd[i++] = 0x244; + ptr_cmd[i++] = mc_address_dst; + ptr_cmd[i++] = (mc_address_dst >> 32) | 0x100000; + ptr_cmd[i++] = 0x400000; + ptr_cmd[i++] = 0x74fac; + + /* clear mmCOMPUTE_RESOURCE_LIMITS */ + ptr_cmd[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 1); + ptr_cmd[i++] = 0x215; + ptr_cmd[i++] = 0; + + /* dispatch direct command */ + ptr_cmd[i++] = PACKET3_COMPUTE(PACKET3_DISPATCH_DIRECT, 3); + ptr_cmd[i++] = 0x10000; + ptr_cmd[i++] = 1; + ptr_cmd[i++] = 1; + ptr_cmd[i++] = 1; + + while (i & 7) + ptr_cmd[i++] = 0xffff1000; /* type3 nop packet */ + + resources[0] = bo_shader; + resources[1] = bo_src; + resources[2] = bo_dst; + resources[3] = bo_cmd; + r = amdgpu_bo_list_create(device_handle, 4, resources, NULL, &bo_list); + CU_ASSERT_EQUAL(r, 0); + + ib_info.ib_mc_address = mc_address_cmd; + ib_info.size = i; + ibs_request.ip_type = ip_type; + ibs_request.ring = ring; + ibs_request.resources = bo_list; + ibs_request.number_of_ibs = 1; + ibs_request.ibs = &ib_info; + ibs_request.fence_info.handle = NULL; + r = amdgpu_cs_submit(context_handle, 0, &ibs_request, 1); + CU_ASSERT_EQUAL(r, 0); + + fence_status.ip_type = ip_type; + fence_status.ip_instance = 0; + fence_status.ring = ring; + fence_status.context = context_handle; + fence_status.fence = ibs_request.seq_no; + + /* wait for IB accomplished */ + r = amdgpu_cs_query_fence_status(&fence_status, + AMDGPU_TIMEOUT_INFINITE, + 0, &expired); + + r = amdgpu_cs_query_reset_state(context_handle, &hang_state, &hangs); + CU_ASSERT_EQUAL(r, 0); + CU_ASSERT_EQUAL(hang_state, AMDGPU_CTX_UNKNOWN_RESET); + + r = amdgpu_bo_list_destroy(bo_list); + CU_ASSERT_EQUAL(r, 0); + + r = amdgpu_bo_unmap_and_free(bo_src, va_src, mc_address_src, bo_dst_size); + CU_ASSERT_EQUAL(r, 0); + r = amdgpu_bo_unmap_and_free(bo_dst, va_dst, mc_address_dst, bo_dst_size); + CU_ASSERT_EQUAL(r, 0); + + r = amdgpu_bo_unmap_and_free(bo_cmd, va_cmd, mc_address_cmd, bo_cmd_size); + CU_ASSERT_EQUAL(r, 0); + + r = amdgpu_bo_unmap_and_free(bo_shader, va_shader, mc_address_shader, bo_shader_size); + CU_ASSERT_EQUAL(r, 0); + + r = amdgpu_cs_ctx_free(context_handle); + CU_ASSERT_EQUAL(r, 0); +} + +void amdgpu_dispatch_hang_slow_helper(amdgpu_device_handle device_handle, uint32_t ip_type) +{ + int r; + struct drm_amdgpu_info_hw_ip info; + uint32_t ring_id; + + r = amdgpu_query_hw_ip_info(device_handle, ip_type, 0, &info); + CU_ASSERT_EQUAL(r, 0); + if (!info.available_rings) + printf("SKIP ... as there's no ring for ip %d\n", ip_type); + + for (ring_id = 0; (1 << ring_id) & info.available_rings; ring_id++) { + amdgpu_memcpy_dispatch_test(device_handle, ip_type, ring_id, 0); + amdgpu_memcpy_dispatch_hang_slow_test(device_handle, ip_type, ring_id); + amdgpu_memcpy_dispatch_test(device_handle, ip_type, ring_id, 0); + } +} + +static int amdgpu_draw_load_ps_shader_hang_slow(uint32_t *ptr, int family) +{ + struct amdgpu_test_shader *shader; + int i, loop = 0x40000; + + switch (family) { + case AMDGPU_FAMILY_AI: + case AMDGPU_FAMILY_RV: + shader = &memcpy_ps_hang_slow_ai; + break; + default: + return -1; + break; + } + + memcpy(ptr, shader->shader, shader->header_length * sizeof(uint32_t)); + + for (i = 0; i < loop; i++) + memcpy(ptr + shader->header_length + shader->body_length * i, + shader->shader + shader->header_length, + shader->body_length * sizeof(uint32_t)); + + memcpy(ptr + shader->header_length + shader->body_length * loop, + shader->shader + shader->header_length + shader->body_length, + shader->foot_length * sizeof(uint32_t)); + + return 0; +} + static int amdgpu_draw_load_ps_shader(uint8_t *ptr, int ps_type) { int i; @@ -2510,6 +2829,12 @@ patchinfo_code_size = ps_tex_shader_patchinfo_code_size_gfx9; patchcode_offset = ps_tex_shader_patchinfo_offset_gfx9; break; + case PS_HANG: + shader = memcpy_ps_hang; + shader_size = sizeof(memcpy_ps_hang); + + memcpy(ptr, shader, shader_size); + return 0; default: return -1; break; @@ -2566,7 +2891,8 @@ } static int amdgpu_draw_setup_and_write_drawblt_surf_info(uint32_t *ptr, - uint64_t dst_addr) + uint64_t dst_addr, + int hang_slow) { int i = 0; @@ -2591,7 +2917,7 @@ ptr[i++] = 0x318; ptr[i++] = dst_addr >> 8; ptr[i++] = dst_addr >> 40; - ptr[i++] = 0x7c01f; + ptr[i++] = hang_slow ? 0x1ffc7ff : 0x7c01f; ptr[i++] = 0; ptr[i++] = 0x50438; ptr[i++] = 0x10140000; @@ -2600,7 +2926,7 @@ /* mmCB_MRT0_EPITCH */ ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1); ptr[i++] = 0x1e8; - ptr[i++] = 0x1f; + ptr[i++] = hang_slow ? 0x7ff : 0x1f; /* 0xA32B CB_COLOR1_BASE */ ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1); @@ -2626,7 +2952,7 @@ return i; } -static int amdgpu_draw_setup_and_write_drawblt_state(uint32_t *ptr) +static int amdgpu_draw_setup_and_write_drawblt_state(uint32_t *ptr, int hang_slow) { int i = 0; const uint32_t *cached_cmd_ptr; @@ -2658,6 +2984,8 @@ cached_cmd_size = sizeof(cached_cmd_gfx9); memcpy(ptr + i, cached_cmd_ptr, cached_cmd_size); + if (hang_slow) + *(ptr + i + 12) = 0x8000800; i += cached_cmd_size/sizeof(uint32_t); return i; @@ -2665,7 +2993,8 @@ static int amdgpu_draw_vs_RectPosTexFast_write2hw(uint32_t *ptr, int ps_type, - uint64_t shader_addr) + uint64_t shader_addr, + int hang_slow) { int i = 0; @@ -2707,8 +3036,8 @@ ptr[i++] = PACKET3(PKT3_SET_SH_REG, 4); ptr[i++] = 0x4c; i += 2; - ptr[i++] = 0x42000000; - ptr[i++] = 0x42000000; + ptr[i++] = hang_slow ? 0x45000000 : 0x42000000; + ptr[i++] = hang_slow ? 0x45000000 : 0x42000000; ptr[i++] = PACKET3(PKT3_SET_SH_REG, 4); ptr[i++] = 0x50; @@ -2845,11 +3174,11 @@ i = 0; i += amdgpu_draw_init(ptr_cmd + i); - i += amdgpu_draw_setup_and_write_drawblt_surf_info(ptr_cmd + i, mc_address_dst); + i += amdgpu_draw_setup_and_write_drawblt_surf_info(ptr_cmd + i, mc_address_dst, 0); - i += amdgpu_draw_setup_and_write_drawblt_state(ptr_cmd + i); + i += amdgpu_draw_setup_and_write_drawblt_state(ptr_cmd + i, 0); - i += amdgpu_draw_vs_RectPosTexFast_write2hw(ptr_cmd + i, PS_CONST, mc_address_shader_vs); + i += amdgpu_draw_vs_RectPosTexFast_write2hw(ptr_cmd + i, PS_CONST, mc_address_shader_vs, 0); i += amdgpu_draw_ps_write2hw(ptr_cmd + i, PS_CONST, mc_address_shader_ps); @@ -2869,7 +3198,7 @@ resources[1] = bo_shader_ps; resources[2] = bo_shader_vs; resources[3] = bo_cmd; - r = amdgpu_bo_list_create(device_handle, 3, resources, NULL, &bo_list); + r = amdgpu_bo_list_create(device_handle, 4, resources, NULL, &bo_list); CU_ASSERT_EQUAL(r, 0); ib_info.ib_mc_address = mc_address_cmd; @@ -2963,7 +3292,7 @@ amdgpu_bo_handle bo_shader_vs, uint64_t mc_address_shader_ps, uint64_t mc_address_shader_vs, - uint32_t ring) + uint32_t ring, int hang) { amdgpu_context_handle context_handle; amdgpu_bo_handle bo_dst, bo_src, bo_cmd, resources[5]; @@ -3008,11 +3337,11 @@ i = 0; i += amdgpu_draw_init(ptr_cmd + i); - i += amdgpu_draw_setup_and_write_drawblt_surf_info(ptr_cmd + i, mc_address_dst); + i += amdgpu_draw_setup_and_write_drawblt_surf_info(ptr_cmd + i, mc_address_dst, 0); - i += amdgpu_draw_setup_and_write_drawblt_state(ptr_cmd + i); + i += amdgpu_draw_setup_and_write_drawblt_state(ptr_cmd + i, 0); - i += amdgpu_draw_vs_RectPosTexFast_write2hw(ptr_cmd + i, PS_TEX, mc_address_shader_vs); + i += amdgpu_draw_vs_RectPosTexFast_write2hw(ptr_cmd + i, PS_TEX, mc_address_shader_vs, 0); i += amdgpu_draw_ps_write2hw(ptr_cmd + i, PS_TEX, mc_address_shader_ps); @@ -3068,14 +3397,20 @@ r = amdgpu_cs_query_fence_status(&fence_status, AMDGPU_TIMEOUT_INFINITE, 0, &expired); - CU_ASSERT_EQUAL(r, 0); - CU_ASSERT_EQUAL(expired, true); + if (!hang) { + CU_ASSERT_EQUAL(r, 0); + CU_ASSERT_EQUAL(expired, true); - /* verify if memcpy test result meets with expected */ - i = 0; - while(i < bo_size) { - CU_ASSERT_EQUAL(ptr_dst[i], ptr_src[i]); - i++; + /* verify if memcpy test result meets with expected */ + i = 0; + while(i < bo_size) { + CU_ASSERT_EQUAL(ptr_dst[i], ptr_src[i]); + i++; + } + } else { + r = amdgpu_cs_query_reset_state(context_handle, &hang_state, &hangs); + CU_ASSERT_EQUAL(r, 0); + CU_ASSERT_EQUAL(hang_state, AMDGPU_CTX_UNKNOWN_RESET); } r = amdgpu_bo_list_destroy(bo_list); @@ -3093,7 +3428,8 @@ CU_ASSERT_EQUAL(r, 0); } -static void amdgpu_memcpy_draw_test(amdgpu_device_handle device_handle, uint32_t ring) +void amdgpu_memcpy_draw_test(amdgpu_device_handle device_handle, uint32_t ring, + int hang) { amdgpu_bo_handle bo_shader_ps, bo_shader_vs; void *ptr_shader_ps; @@ -3101,6 +3437,7 @@ uint64_t mc_address_shader_ps, mc_address_shader_vs; amdgpu_va_handle va_shader_ps, va_shader_vs; int bo_shader_size = 4096; + enum ps_type ps_type = hang ? PS_HANG : PS_TEX; int r; r = amdgpu_bo_alloc_and_map(device_handle, bo_shader_size, 4096, @@ -3117,14 +3454,14 @@ CU_ASSERT_EQUAL(r, 0); memset(ptr_shader_vs, 0, bo_shader_size); - r = amdgpu_draw_load_ps_shader(ptr_shader_ps, PS_TEX); + r = amdgpu_draw_load_ps_shader(ptr_shader_ps, ps_type); CU_ASSERT_EQUAL(r, 0); r = amdgpu_draw_load_vs_shader(ptr_shader_vs); CU_ASSERT_EQUAL(r, 0); amdgpu_memcpy_draw(device_handle, bo_shader_ps, bo_shader_vs, - mc_address_shader_ps, mc_address_shader_vs, ring); + mc_address_shader_ps, mc_address_shader_vs, ring, hang); r = amdgpu_bo_unmap_and_free(bo_shader_ps, va_shader_ps, mc_address_shader_ps, bo_shader_size); CU_ASSERT_EQUAL(r, 0); @@ -3146,10 +3483,172 @@ for (ring_id = 0; (1 << ring_id) & info.available_rings; ring_id++) { amdgpu_memset_draw_test(device_handle, ring_id); - amdgpu_memcpy_draw_test(device_handle, ring_id); + amdgpu_memcpy_draw_test(device_handle, ring_id, 0); } } +void amdgpu_memcpy_draw_hang_slow_test(amdgpu_device_handle device_handle, uint32_t ring) +{ + amdgpu_context_handle context_handle; + amdgpu_bo_handle bo_shader_ps, bo_shader_vs; + amdgpu_bo_handle bo_dst, bo_src, bo_cmd, resources[5]; + void *ptr_shader_ps; + void *ptr_shader_vs; + volatile unsigned char *ptr_dst; + unsigned char *ptr_src; + uint32_t *ptr_cmd; + uint64_t mc_address_dst, mc_address_src, mc_address_cmd; + uint64_t mc_address_shader_ps, mc_address_shader_vs; + amdgpu_va_handle va_shader_ps, va_shader_vs; + amdgpu_va_handle va_dst, va_src, va_cmd; + struct amdgpu_gpu_info gpu_info = {0}; + int i, r; + int bo_size = 0x4000000; + int bo_shader_ps_size = 0x400000; + int bo_shader_vs_size = 4096; + int bo_cmd_size = 4096; + struct amdgpu_cs_request ibs_request = {0}; + struct amdgpu_cs_ib_info ib_info= {0}; + uint32_t hang_state, hangs, expired; + amdgpu_bo_list_handle bo_list; + struct amdgpu_cs_fence fence_status = {0}; + + r = amdgpu_query_gpu_info(device_handle, &gpu_info); + CU_ASSERT_EQUAL(r, 0); + + r = amdgpu_cs_ctx_create(device_handle, &context_handle); + CU_ASSERT_EQUAL(r, 0); + + r = amdgpu_bo_alloc_and_map(device_handle, bo_cmd_size, 4096, + AMDGPU_GEM_DOMAIN_GTT, 0, + &bo_cmd, (void **)&ptr_cmd, + &mc_address_cmd, &va_cmd); + CU_ASSERT_EQUAL(r, 0); + memset(ptr_cmd, 0, bo_cmd_size); + + r = amdgpu_bo_alloc_and_map(device_handle, bo_shader_ps_size, 4096, + AMDGPU_GEM_DOMAIN_VRAM, 0, + &bo_shader_ps, &ptr_shader_ps, + &mc_address_shader_ps, &va_shader_ps); + CU_ASSERT_EQUAL(r, 0); + memset(ptr_shader_ps, 0, bo_shader_ps_size); + + r = amdgpu_bo_alloc_and_map(device_handle, bo_shader_vs_size, 4096, + AMDGPU_GEM_DOMAIN_VRAM, 0, + &bo_shader_vs, &ptr_shader_vs, + &mc_address_shader_vs, &va_shader_vs); + CU_ASSERT_EQUAL(r, 0); + memset(ptr_shader_vs, 0, bo_shader_vs_size); + + r = amdgpu_draw_load_ps_shader_hang_slow(ptr_shader_ps, gpu_info.family_id); + CU_ASSERT_EQUAL(r, 0); + + r = amdgpu_draw_load_vs_shader(ptr_shader_vs); + CU_ASSERT_EQUAL(r, 0); + + r = amdgpu_bo_alloc_and_map(device_handle, bo_size, 4096, + AMDGPU_GEM_DOMAIN_VRAM, 0, + &bo_src, (void **)&ptr_src, + &mc_address_src, &va_src); + CU_ASSERT_EQUAL(r, 0); + + r = amdgpu_bo_alloc_and_map(device_handle, bo_size, 4096, + AMDGPU_GEM_DOMAIN_VRAM, 0, + &bo_dst, (void **)&ptr_dst, + &mc_address_dst, &va_dst); + CU_ASSERT_EQUAL(r, 0); + + memset(ptr_src, 0x55, bo_size); + + i = 0; + i += amdgpu_draw_init(ptr_cmd + i); + + i += amdgpu_draw_setup_and_write_drawblt_surf_info(ptr_cmd + i, mc_address_dst, 1); + + i += amdgpu_draw_setup_and_write_drawblt_state(ptr_cmd + i, 1); + + i += amdgpu_draw_vs_RectPosTexFast_write2hw(ptr_cmd + i, PS_TEX, + mc_address_shader_vs, 1); + + i += amdgpu_draw_ps_write2hw(ptr_cmd + i, PS_TEX, mc_address_shader_ps); + + ptr_cmd[i++] = PACKET3(PKT3_SET_SH_REG, 8); + ptr_cmd[i++] = 0xc; + ptr_cmd[i++] = mc_address_src >> 8; + ptr_cmd[i++] = mc_address_src >> 40 | 0x10e00000; + ptr_cmd[i++] = 0x1ffc7ff; + ptr_cmd[i++] = 0x90500fac; + ptr_cmd[i++] = 0xffe000; + i += 3; + + ptr_cmd[i++] = PACKET3(PKT3_SET_SH_REG, 4); + ptr_cmd[i++] = 0x14; + ptr_cmd[i++] = 0x92; + i += 3; + + ptr_cmd[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1); + ptr_cmd[i++] = 0x191; + ptr_cmd[i++] = 0; + + i += amdgpu_draw_draw(ptr_cmd + i); + + while (i & 7) + ptr_cmd[i++] = 0xffff1000; /* type3 nop packet */ + + resources[0] = bo_dst; + resources[1] = bo_src; + resources[2] = bo_shader_ps; + resources[3] = bo_shader_vs; + resources[4] = bo_cmd; + r = amdgpu_bo_list_create(device_handle, 5, resources, NULL, &bo_list); + CU_ASSERT_EQUAL(r, 0); + + ib_info.ib_mc_address = mc_address_cmd; + ib_info.size = i; + ibs_request.ip_type = AMDGPU_HW_IP_GFX; + ibs_request.ring = ring; + ibs_request.resources = bo_list; + ibs_request.number_of_ibs = 1; + ibs_request.ibs = &ib_info; + ibs_request.fence_info.handle = NULL; + r = amdgpu_cs_submit(context_handle, 0, &ibs_request, 1); + CU_ASSERT_EQUAL(r, 0); + + fence_status.ip_type = AMDGPU_HW_IP_GFX; + fence_status.ip_instance = 0; + fence_status.ring = ring; + fence_status.context = context_handle; + fence_status.fence = ibs_request.seq_no; + + /* wait for IB accomplished */ + r = amdgpu_cs_query_fence_status(&fence_status, + AMDGPU_TIMEOUT_INFINITE, + 0, &expired); + + r = amdgpu_cs_query_reset_state(context_handle, &hang_state, &hangs); + CU_ASSERT_EQUAL(r, 0); + CU_ASSERT_EQUAL(hang_state, AMDGPU_CTX_UNKNOWN_RESET); + + r = amdgpu_bo_list_destroy(bo_list); + CU_ASSERT_EQUAL(r, 0); + + r = amdgpu_bo_unmap_and_free(bo_dst, va_dst, mc_address_dst, bo_size); + CU_ASSERT_EQUAL(r, 0); + r = amdgpu_bo_unmap_and_free(bo_src, va_src, mc_address_src, bo_size); + CU_ASSERT_EQUAL(r, 0); + + r = amdgpu_bo_unmap_and_free(bo_cmd, va_cmd, mc_address_cmd, bo_cmd_size); + CU_ASSERT_EQUAL(r, 0); + + r = amdgpu_bo_unmap_and_free(bo_shader_ps, va_shader_ps, mc_address_shader_ps, bo_shader_ps_size); + CU_ASSERT_EQUAL(r, 0); + r = amdgpu_bo_unmap_and_free(bo_shader_vs, va_shader_vs, mc_address_shader_vs, bo_shader_vs_size); + CU_ASSERT_EQUAL(r, 0); + + r = amdgpu_cs_ctx_free(context_handle); + CU_ASSERT_EQUAL(r, 0); +} + static void amdgpu_gpu_reset_test(void) { int r; diff -Nru libdrm-2.4.100+git1912051032.02e1d0f~b~padoka0/tests/amdgpu/deadlock_tests.c libdrm-2.4.100+git2001081023.9ebfac1~b~padoka0/tests/amdgpu/deadlock_tests.c --- libdrm-2.4.100+git1912051032.02e1d0f~b~padoka0/tests/amdgpu/deadlock_tests.c 2019-03-20 12:29:14.000000000 +0000 +++ libdrm-2.4.100+git2001081023.9ebfac1~b~padoka0/tests/amdgpu/deadlock_tests.c 2020-01-08 10:20:05.000000000 +0000 @@ -114,6 +114,12 @@ static void amdgpu_illegal_reg_access(); static void amdgpu_illegal_mem_access(); static void amdgpu_deadlock_sdma(void); +static void amdgpu_dispatch_hang_gfx(void); +static void amdgpu_dispatch_hang_compute(void); +static void amdgpu_dispatch_hang_slow_gfx(void); +static void amdgpu_dispatch_hang_slow_compute(void); +static void amdgpu_draw_hang_gfx(void); +static void amdgpu_draw_hang_slow_gfx(void); CU_BOOL suite_deadlock_tests_enable(void) { @@ -178,6 +184,12 @@ { "sdma ring block test (set amdgpu.lockup_timeout=50)", amdgpu_deadlock_sdma }, { "illegal reg access test", amdgpu_illegal_reg_access }, { "illegal mem access test (set amdgpu.vm_fault_stop=2)", amdgpu_illegal_mem_access }, + { "gfx ring bad dispatch test (set amdgpu.lockup_timeout=50)", amdgpu_dispatch_hang_gfx }, + { "compute ring bad dispatch test (set amdgpu.lockup_timeout=50,50)", amdgpu_dispatch_hang_compute }, + { "gfx ring bad slow dispatch test (set amdgpu.lockup_timeout=50)", amdgpu_dispatch_hang_slow_gfx }, + { "compute ring bad slow dispatch test (set amdgpu.lockup_timeout=50,50)", amdgpu_dispatch_hang_slow_compute }, + { "gfx ring bad draw test (set amdgpu.lockup_timeout=50)", amdgpu_draw_hang_gfx }, + { "gfx ring slow bad draw test (set amdgpu.lockup_timeout=50)", amdgpu_draw_hang_slow_gfx }, CU_TEST_INFO_NULL, }; @@ -478,3 +490,57 @@ { bad_access_helper(0); } + +static void amdgpu_dispatch_hang_gfx(void) +{ + amdgpu_dispatch_hang_helper(device_handle, AMDGPU_HW_IP_GFX); +} + +static void amdgpu_dispatch_hang_compute(void) +{ + amdgpu_dispatch_hang_helper(device_handle, AMDGPU_HW_IP_COMPUTE); +} + +static void amdgpu_dispatch_hang_slow_gfx(void) +{ + amdgpu_dispatch_hang_slow_helper(device_handle, AMDGPU_HW_IP_GFX); +} + +static void amdgpu_dispatch_hang_slow_compute(void) +{ + amdgpu_dispatch_hang_slow_helper(device_handle, AMDGPU_HW_IP_COMPUTE); +} + +static void amdgpu_draw_hang_gfx(void) +{ + int r; + struct drm_amdgpu_info_hw_ip info; + uint32_t ring_id; + + r = amdgpu_query_hw_ip_info(device_handle, AMDGPU_HW_IP_GFX, 0, &info); + CU_ASSERT_EQUAL(r, 0); + if (!info.available_rings) + printf("SKIP ... as there's no graphic ring\n"); + + for (ring_id = 0; (1 << ring_id) & info.available_rings; ring_id++) { + amdgpu_memcpy_draw_test(device_handle, ring_id, 0); + amdgpu_memcpy_draw_test(device_handle, ring_id, 1); + amdgpu_memcpy_draw_test(device_handle, ring_id, 0); + } +} + +static void amdgpu_draw_hang_slow_gfx(void) +{ + struct drm_amdgpu_info_hw_ip info; + uint32_t ring_id; + int r; + + r = amdgpu_query_hw_ip_info(device_handle, AMDGPU_HW_IP_GFX, 0, &info); + CU_ASSERT_EQUAL(r, 0); + + for (ring_id = 0; (1 << ring_id) & info.available_rings; ring_id++) { + amdgpu_memcpy_draw_test(device_handle, ring_id, 0); + amdgpu_memcpy_draw_hang_slow_test(device_handle, ring_id); + amdgpu_memcpy_draw_test(device_handle, ring_id, 0); + } +} diff -Nru libdrm-2.4.100+git1912051032.02e1d0f~b~padoka0/tests/modetest/modetest.c libdrm-2.4.100+git2001081023.9ebfac1~b~padoka0/tests/modetest/modetest.c --- libdrm-2.4.100+git1912051032.02e1d0f~b~padoka0/tests/modetest/modetest.c 2019-12-05 10:31:35.000000000 +0000 +++ libdrm-2.4.100+git2001081023.9ebfac1~b~padoka0/tests/modetest/modetest.c 2020-01-08 10:20:05.000000000 +0000 @@ -133,6 +133,12 @@ return (int64_t)*((int64_t *)&val); } +static float mode_vrefresh(drmModeModeInfo *mode) +{ + return mode->clock * 1000.00 + / (mode->htotal * mode->vtotal); +} + #define bit_name_fn(res) \ const char * res##_str(int type) { \ unsigned int i; \ @@ -210,9 +216,9 @@ static void dump_mode(drmModeModeInfo *mode) { - printf(" %s %d %d %d %d %d %d %d %d %d %d", + printf(" %s %.2f %d %d %d %d %d %d %d %d %d", mode->name, - mode->vrefresh, + mode_vrefresh(mode), mode->hdisplay, mode->hsync_start, mode->hsync_end, @@ -828,7 +834,6 @@ drmModeConnector *connector; drmModeModeInfo *mode; int i; - float mode_vrefresh; connector = get_connector_by_id(dev, con_id); if (!connector || !connector->count_modes) @@ -837,15 +842,14 @@ for (i = 0; i < connector->count_modes; i++) { mode = &connector->modes[i]; if (!strcmp(mode->name, mode_str)) { - /* If the vertical refresh frequency is not specified then return the - * first mode that match with the name. Else, return the mode that match - * the name and the specified vertical refresh frequency. + /* If the vertical refresh frequency is not specified + * then return the first mode that match with the name. + * Else, return the mode that match the name and + * the specified vertical refresh frequency. */ - mode_vrefresh = mode->clock * 1000.00 - / (mode->htotal * mode->vtotal); if (vrefresh == 0) return mode; - else if (fabs(mode_vrefresh - vrefresh) < 0.005) + else if (fabs(mode_vrefresh(mode) - vrefresh) < 0.005) return mode; } } @@ -911,7 +915,13 @@ mode = connector_find_mode(dev, pipe->con_ids[i], pipe->mode_str, pipe->vrefresh); if (mode == NULL) { - fprintf(stderr, + if (pipe->vrefresh) + fprintf(stderr, + "failed to find mode " + "\"%s-%.2fHz\" for connector %s\n", + pipe->mode_str, pipe->vrefresh, pipe->cons[i]); + else + fprintf(stderr, "failed to find mode \"%s\" for connector %s\n", pipe->mode_str, pipe->cons[i]); return -EINVAL; @@ -1398,7 +1408,7 @@ continue; printf("setting mode %s-%.2fHz on connectors ", - pipe->mode_str, pipe->vrefresh); + pipe->mode->name, mode_vrefresh(pipe->mode)); for (j = 0; j < pipe->num_cons; ++j) { printf("%s, ", pipe->cons[j]); add_property(dev, pipe->con_ids[j], "CRTC_ID", pipe->crtc->crtc->crtc_id); @@ -1481,7 +1491,8 @@ continue; printf("setting mode %s-%.2fHz@%s on connectors ", - pipe->mode_str, pipe->vrefresh, pipe->format_str); + pipe->mode->name, mode_vrefresh(pipe->mode), + pipe->format_str); for (j = 0; j < pipe->num_cons; ++j) printf("%s, ", pipe->cons[j]); printf("crtc %d\n", pipe->crtc->crtc->crtc_id); diff -Nru libdrm-2.4.100+git1912051032.02e1d0f~b~padoka0/xf86atomic.h libdrm-2.4.100+git2001081023.9ebfac1~b~padoka0/xf86atomic.h --- libdrm-2.4.100+git1912051032.02e1d0f~b~padoka0/xf86atomic.h 2019-02-20 21:32:39.000000000 +0000 +++ libdrm-2.4.100+git2001081023.9ebfac1~b~padoka0/xf86atomic.h 2020-01-08 10:20:05.000000000 +0000 @@ -54,6 +54,7 @@ #endif #if HAVE_LIB_ATOMIC_OPS +#define AO_REQUIRE_CAS #include #define HAS_ATOMIC_OPS 1 diff -Nru libdrm-2.4.100+git1912051032.02e1d0f~b~padoka0/xf86drm.h libdrm-2.4.100+git2001081023.9ebfac1~b~padoka0/xf86drm.h --- libdrm-2.4.100+git1912051032.02e1d0f~b~padoka0/xf86drm.h 2019-10-27 18:28:17.000000000 +0000 +++ libdrm-2.4.100+git2001081023.9ebfac1~b~padoka0/xf86drm.h 2020-01-08 10:20:05.000000000 +0000 @@ -481,6 +481,29 @@ : "cr0", "memory"); \ } while (0) +# elif defined (__ARM_ARCH_6__) || defined(__ARM_ARCH_6J__) \ + || defined (__ARM_ARCH_6Z__) || defined(__ARM_ARCH_6ZK__) \ + || defined (__ARM_ARCH_6K__) || defined(__ARM_ARCH_6T2__) \ + || defined (__ARM_ARCH_7__) || defined(__ARM_ARCH_7A__) \ + || defined(__ARM_ARCH_7R__) || defined(__ARM_ARCH_7M__) \ + || defined(__ARM_ARCH_7EM__) + /* excluding ARMv4/ARMv5 and lower (lacking ldrex/strex support) */ + #undef DRM_DEV_MODE + #define DRM_DEV_MODE (S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH|S_IWOTH) + + #define DRM_CAS(lock,old,new,__ret) \ + do { \ + __asm__ __volatile__ ( \ + "1: ldrex %0, [%1]\n" \ + " teq %0, %2\n" \ + " ite eq\n" \ + " strexeq %0, %3, [%1]\n" \ + " movne %0, #1\n" \ + : "=&r" (__ret) \ + : "r" (lock), "r" (old), "r" (new) \ + : "cc","memory"); \ + } while (0) + #endif /* architecture */ #endif /* __GNUC__ >= 2 */